From 0d390c912263d6388ed875ee4972e8094e2ee9c0 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 13 Oct 2011 23:59:24 +0200 Subject: [PATCH 0001/1435] Fix a signedness warning Signed-off-by: Karl Palsson --- src/stlink-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 79709ac0b..ebd6e3558 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -163,7 +163,7 @@ void _stlink_usb_version(stlink_t *sl) { #if 1 /* DEBUG */ { - unsigned int i; + ssize_t i; for (i = 0; i < size; ++i) printf("%02x", buf[i]); printf("\n"); } From 4aa64b2daa46f5a36d8fa10a932833fcf66ee6f6 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 13 Oct 2011 23:25:46 +0200 Subject: [PATCH 0002/1435] Size all USB receive operations Signed-off-by: Karl Palsson --- src/stlink-usb.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index ebd6e3558..5099bfd4f 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -155,7 +155,7 @@ void _stlink_usb_version(stlink_t *sl) { buf[0] = STLINK_GET_VERSION; buf[1] = 0x80; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 6); if (size == -1) { printf("[!] send_recv\n"); return; @@ -211,7 +211,7 @@ int _stlink_usb_current_mode(stlink_t * sl) { ssize_t size; memset(buf, 0, sizeof (sl->q_buf)); buf[0] = STLINK_GET_CURRENT_MODE; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); if (size == -1) { printf("[!] send_recv\n"); return -1; @@ -228,7 +228,7 @@ void _stlink_usb_core_id(stlink_t * sl) { buf[0] = STLINK_DEBUG_COMMAND; buf[1] = STLINK_DEBUG_READCOREID; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 4); if (size == -1) { printf("[!] send_recv\n"); return; @@ -247,7 +247,7 @@ void _stlink_usb_status(stlink_t * sl) { buf[0] = STLINK_DEBUG_COMMAND; buf[1] = STLINK_DEBUG_GETSTATUS; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); if (size == -1) { printf("[!] send_recv\n"); return; @@ -271,7 +271,7 @@ void _stlink_usb_force_debug(stlink_t *sl) { buf[0] = STLINK_DEBUG_COMMAND; buf[1] = STLINK_DEBUG_FORCEDEBUG; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); if (size == -1) { printf("[!] send_recv\n"); return; @@ -290,7 +290,7 @@ void _stlink_usb_enter_swd_mode(stlink_t * sl) { buf[1] = STLINK_SWD_ENTER; buf[2] = STLINK_DEBUG_ENTER_SWD; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); if (size == -1) { printf("[!] send_recv\n"); return; @@ -343,7 +343,7 @@ void _stlink_usb_step(stlink_t* sl) { buf[0] = STLINK_DEBUG_COMMAND; buf[1] = STLINK_DEBUG_STEPCORE; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); if (size == -1) { printf("[!] send_recv\n"); return; @@ -363,7 +363,7 @@ void _stlink_usb_run(stlink_t* sl) { buf[0] = STLINK_DEBUG_COMMAND; buf[1] = STLINK_DEBUG_RUNCORE; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); if (size == -1) { printf("[!] send_recv\n"); return; @@ -404,7 +404,7 @@ void _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { assert (len < 256); buf[6] = (uint8_t) len; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, len); if (size == -1) { printf("[!] send_recv\n"); return; From 06a737c4cc2aa1238fcb44f422e139e1c147c41f Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Fri, 14 Oct 2011 00:03:06 +0200 Subject: [PATCH 0003/1435] Assert size only if Q_BUF_LEN is smaller UINT16_MAX Signed-off-by: Karl Palsson --- src/stlink-usb.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 5099bfd4f..b417d41aa 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -182,6 +182,9 @@ void _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint16(cmd_buf + 6, len); send_only(slu, cmd_buf, STLINK_CMD_SIZE); +#if Q_BUF_LEN < UINT16_MAX + assert(len < sizeof(sl->q_buf)); // makes a compiler warning? always true? +#endif assert((len & 3) == 0); stlink_print_data(sl); send_only(slu, buf, len); @@ -200,6 +203,9 @@ void _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint16(cmd_buf + 6, len); send_only(slu, cmd_buf, STLINK_CMD_SIZE); +#if Q_BUF_LEN < UINT16_MAX + assert(len < sizeof(sl->q_buf)); // makes a compiler warning? always true? +#endif stlink_print_data(sl); send_only(slu, buf, len); } @@ -392,8 +398,9 @@ void _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { unsigned char* const buf = sl->q_buf; ssize_t size; - /* assume len < sizeof(sl->q_buf) */ - assert(len < sizeof(sl->q_buf)); // makes a compiler warning? always true? +#if Q_BUF_LEN < UINT16_MAX + assert(len < sizeof(sl->q_buf)); +#endif memset(buf, 0, sizeof (sl->q_buf)); buf[0] = STLINK_DEBUG_COMMAND; From 7abc08eeefdd4128ca55bcece97eda9c54a9e5bb Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Fri, 14 Oct 2011 00:06:41 +0200 Subject: [PATCH 0004/1435] Remove some debug output Signed-off-by: Karl Palsson --- src/stlink-usb.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index b417d41aa..7bcff82da 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -186,7 +186,6 @@ void _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { assert(len < sizeof(sl->q_buf)); // makes a compiler warning? always true? #endif assert((len & 3) == 0); - stlink_print_data(sl); send_only(slu, buf, len); } @@ -206,7 +205,6 @@ void _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { #if Q_BUF_LEN < UINT16_MAX assert(len < sizeof(sl->q_buf)); // makes a compiler warning? always true? #endif - stlink_print_data(sl); send_only(slu, buf, len); } From a4e5aba21e022750633039fab9efa4119062e096 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 02:06:07 +0000 Subject: [PATCH 0005/1435] Fix character encodings of st provided files. --- example/lcd/stm32l_discovery_lcd.c | 4 ++-- example/lcd/stm32l_discovery_lcd.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/example/lcd/stm32l_discovery_lcd.c b/example/lcd/stm32l_discovery_lcd.c index 64163de40..982a5f259 100644 --- a/example/lcd/stm32l_discovery_lcd.c +++ b/example/lcd/stm32l_discovery_lcd.c @@ -281,7 +281,7 @@ static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column, uint8_t* digit) ch = star; break; - case '' : + case 'µ' : ch = C_UMAP; break; @@ -301,7 +301,7 @@ static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column, uint8_t* digit) ch = C_slatch; break; - case '' : + case '°' : ch = C_percent_1; break; case '%' : diff --git a/example/lcd/stm32l_discovery_lcd.h b/example/lcd/stm32l_discovery_lcd.h index d496b8400..bb8b0d742 100644 --- a/example/lcd/stm32l_discovery_lcd.h +++ b/example/lcd/stm32l_discovery_lcd.h @@ -85,7 +85,7 @@ MSB { 1 , 1 , 0 , 0 } #define BAR3_ON t_bar[0] |= 2 #define BAR3_OFF t_bar[0] &= ~2 -/* code for '' character */ +/* code for 'µ' character */ #define C_UMAP 0x6084 /* code for 'm' character */ @@ -103,7 +103,7 @@ MSB { 1 , 1 , 0 , 0 } /* constant code for '/' */ #define C_slatch 0x00c0 -/* constant code for */ +/* constant code for ° */ #define C_percent_1 0xec00 /* constant code for small o */ From 234e144d5d5aba4fcbe1a9fd9563023f1ca81a57 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 02:06:35 +0000 Subject: [PATCH 0006/1435] Add debug flag by default, no need not to have it in the elf. --- example/blink/Makefile | 2 +- example/lcd/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/example/blink/Makefile b/example/blink/Makefile index 1b310b176..0f4f71277 100644 --- a/example/blink/Makefile +++ b/example/blink/Makefile @@ -4,7 +4,7 @@ BIN_IMAGE=blink.bin CC=arm-none-eabi-gcc OBJCOPY=arm-none-eabi-objcopy -CFLAGS=-O2 -mlittle-endian -mthumb +CFLAGS=-O2 -mlittle-endian -mthumb -g CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc # to run from SRAM diff --git a/example/lcd/Makefile b/example/lcd/Makefile index 0febe4912..0f31ae68b 100644 --- a/example/lcd/Makefile +++ b/example/lcd/Makefile @@ -2,7 +2,7 @@ ELF=lcd.elf CC=arm-none-eabi-gcc -CFLAGS=-O2 -mlittle-endian -mthumb +CFLAGS=-O2 -mlittle-endian -mthumb -g CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc CFLAGS+=-I. From 9bc72d4519e63fb1cf657a6c93008eaa8989fd01 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 02:11:04 +0000 Subject: [PATCH 0007/1435] Merge upstream texane/master --- .gitignore | 1 + AUTHORS | 2 + Makefile | 41 +- TODO | 15 +- doc/tutorial/tutorial.pdf | Bin 106136 -> 110077 bytes doc/tutorial/tutorial.tex | 65 ++- example/blink/Makefile | 11 +- example/blink/main.c | 34 +- example/blink_flash/Makefile | 36 ++ example/blink_flash/main.c | 82 ++++ example/blink_flash/startup_stm32l1xx_md.s | 366 ++++++++++++++ example/blink_flash/stm32_flash.ld | 173 +++++++ example/blink_flash/system_stm32l1xx.c | 367 ++++++++++++++ flash/Makefile | 21 +- flash/main.c | 131 ++++- gdbserver/Makefile | 19 +- gdbserver/gdb-server.c | 53 ++- src/stlink-common.h | 1 + src/stlink-sg.c | 6 +- src/stlink-usb.c | 526 +++++++++++---------- src/stlink-usb.h | 6 +- src/test_sg.c | 4 +- src/test_usb.c | 2 +- 23 files changed, 1626 insertions(+), 336 deletions(-) create mode 100644 example/blink_flash/Makefile create mode 100644 example/blink_flash/main.c create mode 100644 example/blink_flash/startup_stm32l1xx_md.s create mode 100644 example/blink_flash/stm32_flash.ld create mode 100644 example/blink_flash/system_stm32l1xx.c diff --git a/.gitignore b/.gitignore index 78d3fb552..44d2e4ddf 100644 --- a/.gitignore +++ b/.gitignore @@ -3,3 +3,4 @@ libstlink.a test_usb test_sg +gdbserver/st-utils \ No newline at end of file diff --git a/AUTHORS b/AUTHORS index ca1df75a0..0abaac620 100644 --- a/AUTHORS +++ b/AUTHORS @@ -7,3 +7,5 @@ karlp@tweak.net.au h0rr0rrdrag@gmail.com mstempin@com1.fr bon@elektron.ikp.physik.tu-darmstadt.de +nelsonjm@macpod.neta +ned@bike-nomad.com \ No newline at end of file diff --git a/Makefile b/Makefile index 4c3b44b83..c5bb1d9a1 100644 --- a/Makefile +++ b/Makefile @@ -1,21 +1,36 @@ - +# make ... for both libusb and libsg +# +# make CONFIG_USE_LIBSG=0 ... +# for just libusb +# VPATH=src -SOURCES_LIB=stlink-common.c stlink-usb.c stlink-sg.c +SOURCES_LIB=stlink-common.c stlink-usb.c OBJS_LIB=$(SOURCES_LIB:.c=.o) +TEST_PROGRAMS=test_usb +LDFLAGS=-lusb-1.0 -L. -lstlink + +ifeq ($(CONFIG_USE_LIBSG),) +CONFIG_USE_LIBSG=1 +endif + +ifneq ($(CONFIG_USE_LIBSG),0) +SOURCES_LIB+=stlink-sg.c +CFLAGS+=-DCONFIG_USE_LIBSG=1 +LDFLAGS+=-lsgutils2 +TEST_PROGRAMS+=test_sg +endif CFLAGS+=-g -CFLAGS+=-DCONFIG_USE_LIBUSB -CFLAGS+=-DCONFIG_USE_LIBSG -CFLAGS+=-DDEBUG +CFLAGS+=-DCONFIG_USE_LIBUSB=1 +CFLAGS+=-DDEBUG=1 CFLAGS+=-std=gnu99 CFLAGS+=-Wall -Wextra -LDFLAGS=-lstlink -lusb-1.0 -lsgutils2 -L. LIBRARY=libstlink.a -all: $(LIBRARY) test_usb test_sg +all: $(LIBRARY) flash gdbserver $(TEST_PROGRAMS) $(LIBRARY): $(OBJS_LIB) @echo "objs are $(OBJS_LIB)" @@ -42,5 +57,15 @@ clean: rm -rf $(LIBRARY) rm -rf test_usb* rm -rf test_sg* + +distclean: clean + $(MAKE) -C flash clean + $(MAKE) -C gdbserver clean -.PHONY: clean all +flash: + $(MAKE) -C flash CONFIG_USE_LIBSG="$(CONFIG_USE_LIBSG)" + +gdbserver: + $(MAKE) -C gdbserver + +.PHONY: clean all flash gdbserver diff --git a/TODO b/TODO index 4d1929c96..e3795fc32 100644 --- a/TODO +++ b/TODO @@ -1,10 +1,17 @@ -. flash writing is not working from GDB -add a standalone application, flash/ +. flash tool + . test support for reading + . writing is not working. refer to the specs, may have changed for stm32l + . then test with blink_flash example + . then update the documentation -. add a startup.S based example +. documentation + . make README points to doc/tutorial . remove libsg dependency using: https://github.com/afaerber/stlink/tree/master/libstlink . compile and test a realtime kernel, for instance: -http://www.chibios.org/dokuwiki/doku.php?id=start +http://www.chibios.org/dokuwiki/doku.php?id=chibios:articles:stm32l_discovery +svn checkout https://chibios.svn.sourceforge.net/svnroot/chibios/trunk ; +cd chibios/trunk/demos/ARMCM3-STM32L152-DISCOVERY ; +make ; diff --git a/doc/tutorial/tutorial.pdf b/doc/tutorial/tutorial.pdf index b84d061f57921ebc02df6a11261675a97c3d31fa..9202ed4dc33c1bcafdcf4db30807103a22c846c8 100644 GIT binary patch delta 65756 zcmZU(W0WRA(=FPzZQIuLv^{Oxw%z@-ZQHhO+qP}@wC=p$d%kn;TK7jrMP}^SQBkW_ zW@Tihbwhk@Le!ywfUz=h5+xdxPyuWbrfmn9kb-V`gJUy=16Fl^bjo20s>_y2N?St1 zz`~MvR8aPwGxvn@CoGJuP9CdPvTU%;BB6hlHF(lzf(<0X$>`NP48kbt2UrHF1hpq<;E|&YDbaWdNvQM85lkGS3<3G=^+cg> zfL^HYV!O_&3aQ>`Lkn`_KqNX@0d}ix+ii-$0cQ2`Lw`#M__WKNE9--% z)Ic|&Z-=zW*$^84X$c-nC{0X!?$Kva?D0{c zkbU&w^AvRUXuS@*HYqI>RAGF$AZ>v~H@HqB!2iz6ui(!cowt5cpfYuq<=a^eG#Z!Q zWXrMR359SzX>ZyjtLx2d$hP=NB2B0(Ih^i*@J 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zP+L=@{&VEy;O66olKap24~&N&s-pkDF)-IZHUCcx`k9~a4?8Hv_h$?!2I2fCM#7f@ z5C*^v{?`c<{f~fLe^26saQ=}jG+pQl{!D_CgBL2~|Ihfp{x~?ez`W31@CU}t!vV#B z|7FMt;s0y(U?_ioPUhz4`O6_UALK7PE(p&b2|^i$K>mZJf8s+24+rEghY)`7Uk zJb%&7%LC#2GeKSm_&nA5FE}`Oc_Dw5gpd30 zr1`l2W{VH}?}b3u|37u&ExP&w`C4MnZ t4oPk>k2qME`u}h8fm&D?)xpuw-qF?G)C?7x0UswH>WdffQYzA@{|9ZYR;~a5 diff --git a/doc/tutorial/tutorial.tex b/doc/tutorial/tutorial.tex index cef3632ac..d1ba4fdbd 100644 --- a/doc/tutorial/tutorial.tex +++ b/doc/tutorial/tutorial.tex @@ -56,30 +56,37 @@ \section{Installing STLINK} (v1 uses SCSI passthru commands, while v2 uses raw USB). \paragraph{} -Before continuing, the following dependencies are required: +Before continuing, the following dependencies must be met: \begin{itemize} \item libusb-1.0 -\item libsg2 +\item libsgutils2 (optionnal) \end{itemize} +\paragraph{} +STLINK should run on any system meeting the above constraints. + \paragraph{} The STLINK software source code is retrieved using:\\ \begin{small} \begin{lstlisting}[frame=tb] -git clone https://github.com/texane/stlink stlink.git +$> git clone https://github.com/texane/stlink stlink.git \end{lstlisting} \end{small} \paragraph{} -The GDB server is called st-util and is built using:\\ +Everything can be built from the top directory:\\ \begin{small} \begin{lstlisting}[frame=tb] -$> cd stlink.git; -$> make ; -$> cd gdbserver ; -$> make ; +$> cd stlink.git +$> make CONFIG_USE_LIBSG=0 \end{lstlisting} \end{small} +It includes: +\begin{itemize} +\item a communication library (stlink.git/libstlink.a), +\item a GDB server (stlink.git/gdbserver/st-util), +\item a flash manipulation tool (stlink.git/flash/flash). +\end{itemize} \newpage @@ -88,8 +95,9 @@ \section{Building and running a program} A simple LED blinking example is provided in the example directory. It is built using:\\ \begin{small} \begin{lstlisting}[frame=tb] +# update the make option accordingly to your architecture cd stlink.git/example/blink ; -PATH=$TOOLCHAIN_PATH/bin:$PATH make ; +PATH=$TOOLCHAIN_PATH/bin:$PATH make CONFIG_STM32L_DISCOVERY=1; \end{lstlisting} \end{small} @@ -102,7 +110,8 @@ \section{Building and running a program} $> sudo ./st-util /dev/sg2 # STM32L discovery kit -$> sudo ./st-util +# 2 dummy command line arguments needed, will be fixed soon +$> sudo ./st-util fu bar \end{lstlisting} \end{small} @@ -144,6 +153,31 @@ \section{Building and running a program} The board BLUE and GREEN leds should be blinking (those leds are near the user and reset buttons). +\newpage +\section{Reading and writing to flash} +\paragraph{} +Flash memory reading and writing is done by a separate tool. A binary running in flash is assumed to +be linked against address 0x8000000. The flash tool is then used as shown below:\\ +\begin{small} +\begin{lstlisting}[frame=tb] +# change to the flash tool directory +$> cd stlink.git/flash ; + +# stlinkv1 command to read 4096 from flash into out.bin +$> ./flash read /dev/sg2 out.bin 0x8000000 4096 + +# stlinkv2 command +$> ./flash read out.bin 0x8000000 4096 + +# stlinkv1 command to write the file in.bin into flash +$> ./flash write /dev/sg2 in.bin 0x8000000 + +# stlinkv2 command +$> ./flash write in.bin 0x8000000 +\end{lstlisting} +\end{small} + + \newpage \section{Notes} @@ -187,6 +221,17 @@ \subsection{libstm32l\_discovery} \end{lstlisting} \end{small} +\subsection{STM32VL support} +\paragraph{} +It seems support for STM32VL is quite broken. If it does not work, try build STLINK using libsg: +\begin{small} +\begin{lstlisting}[frame=tb] +$> cd stlink.git +$> make CONFIG_USE_LIBSG=1 +\end{lstlisting} +\end{small} + + \newpage \section{References} \begin{itemize} diff --git a/example/blink/Makefile b/example/blink/Makefile index 0f4f71277..e5f704525 100644 --- a/example/blink/Makefile +++ b/example/blink/Makefile @@ -4,8 +4,15 @@ BIN_IMAGE=blink.bin CC=arm-none-eabi-gcc OBJCOPY=arm-none-eabi-objcopy -CFLAGS=-O2 -mlittle-endian -mthumb -g -CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc +CFLAGS=-g -O2 -mlittle-endian -mthumb +ifeq ($(CONFIG_STM32L_DISCOVERY), 1) + CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY +else ifeq ($(CONFIG_STM32VL_DISCOVERY), 1) + CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1 +else ifeq ($(CONFIG_STM32F4_DISCOVERY), 1) + CFLAGS+=-mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1 +endif + CFLAGS+=-ffreestanding -nostdlib -nostdinc # to run from SRAM CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000 diff --git a/example/blink/main.c b/example/blink/main.c index 929e3b9c1..0889b8161 100644 --- a/example/blink/main.c +++ b/example/blink/main.c @@ -5,10 +5,6 @@ typedef unsigned int uint32_t; /* hardware configuration */ -#define CONFIG_STM32L_DISCOVERY 1 -#define CONFIG_STM32VL_DISCOVERY 0 - - #if CONFIG_STM32VL_DISCOVERY # define GPIOC 0x40011000 /* port C */ @@ -58,6 +54,36 @@ static inline void switch_leds_off(void) *(volatile uint32_t*)GPIOB_ODR = 0; } +#elif CONFIG_STM32F4_DISCOVERY + +#define GPIOD 0x40020C00 /* port D */ +# define GPIOD_MODER (GPIOD + 0x00) /* port mode register */ +# define GPIOD_ODR (GPIOD + 0x14) /* port output data register */ + +# define LED_GREEN (1 << 12) /* port B, pin 12 */ +# define LED_ORANGE (1 << 13) /* port B, pin 13 */ +# define LED_RED (1 << 14) /* port B, pin 14 */ +# define LED_BLUE (1 << 15) /* port B, pin 15 */ + +static inline void setup_leds(void) +{ + *(volatile uint32_t*)GPIOD_MODER |= (1 << (12 * 2)) | (1 << (13 * 2)) | + (1 << (13 * 2)) | (1 << (14 * 2)) | (1 << (15 * 2)); +} + + +static inline void switch_leds_on(void) +{ + *(volatile uint32_t*)GPIOD_ODR = LED_GREEN | LED_ORANGE | LED_RED | LED_BLUE; +} + +static inline void switch_leds_off(void) +{ + *(volatile uint32_t*)GPIOD_ODR = 0; +} + +#else +#error "Architecture must be defined!" #endif /* otherwise, error */ diff --git a/example/blink_flash/Makefile b/example/blink_flash/Makefile new file mode 100644 index 000000000..77764715d --- /dev/null +++ b/example/blink_flash/Makefile @@ -0,0 +1,36 @@ +EXECUTABLE=blink.elf +BIN_IMAGE=blink.bin + +CC=arm-none-eabi-gcc +OBJCOPY=arm-none-eabi-objcopy + +CFLAGS=-O2 -mlittle-endian -mthumb + +CFLAGS=-g -O2 -mlittle-endian -mthumb +ifeq ($(CONFIG_STM32L_DISCOVERY), 1) + CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY +else ifeq ($(CONFIG_STM32VL_DISCOVERY), 1) + CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1 +else ifeq ($(CONFIG_STM32F4_DISCOVERY), 1) + CFLAGS+=-mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1 +else +$(error "must specify CONFIG_ for board!") +endif + CFLAGS+=-ffreestanding -nostdlib -nostdinc + +# to run from FLASH +CFLAGS+=-Wl,-T,stm32_flash.ld + +all: $(BIN_IMAGE) + +$(BIN_IMAGE): $(EXECUTABLE) + $(OBJCOPY) -O binary $^ $@ + +$(EXECUTABLE): main.c startup_stm32l1xx_md.s + $(CC) $(CFLAGS) $^ -o $@ + +clean: + rm -rf $(EXECUTABLE) + rm -rf $(BIN_IMAGE) + +.PHONY: all clean diff --git a/example/blink_flash/main.c b/example/blink_flash/main.c new file mode 100644 index 000000000..e93fd728a --- /dev/null +++ b/example/blink_flash/main.c @@ -0,0 +1,82 @@ +/* missing type */ + +typedef unsigned int uint32_t; + + +/* hardware configuration */ + +#define CONFIG_STM32L_DISCOVERY 1 +#define CONFIG_STM32VL_DISCOVERY 0 + + +#if CONFIG_STM32VL_DISCOVERY + +# define GPIOC 0x40011000 /* port C */ +# define GPIOC_CRH (GPIOC + 0x04) /* port configuration register high */ +# define GPIOC_ODR (GPIOC + 0x0c) /* port output data register */ + +# define LED_BLUE (1 << 8) /* port C, pin 8 */ +# define LED_GREEN (1 << 9) /* port C, pin 9 */ + +static inline void setup_leds(void) +{ + *(volatile uint32_t*)GPIOC_CRH = 0x44444411; +} + +static inline void switch_leds_on(void) +{ + *(volatile uint32_t*)GPIOC_ODR = LED_BLUE | LED_GREEN; +} + +static inline void switch_leds_off(void) +{ + *(volatile uint32_t*)GPIOC_ODR = 0; +} + +#elif CONFIG_STM32L_DISCOVERY + +# define GPIOB 0x40020400 /* port B */ +# define GPIOB_MODER (GPIOB + 0x00) /* port mode register */ +# define GPIOB_ODR (GPIOB + 0x14) /* port output data register */ + +# define LED_BLUE (1 << 6) /* port B, pin 6 */ +# define LED_GREEN (1 << 7) /* port B, pin 7 */ + +static inline void setup_leds(void) +{ + /* configure port 6 and 7 as output */ + *(volatile uint32_t*)GPIOB_MODER |= (1 << (7 * 2)) | (1 << (6 * 2)); +} + +static inline void switch_leds_on(void) +{ + *(volatile uint32_t*)GPIOB_ODR = LED_BLUE | LED_GREEN; +} + +static inline void switch_leds_off(void) +{ + *(volatile uint32_t*)GPIOB_ODR = 0; +} + +#endif /* otherwise, error */ + + +#define delay() \ +do { \ + register unsigned int i; \ + for (i = 0; i < 1000000; ++i) \ + __asm__ __volatile__ ("nop\n\t":::"memory"); \ +} while (0) + +void main(void) +{ + setup_leds(); + + while (1) + { + switch_leds_on(); + delay(); + switch_leds_off(); + delay(); + } +} diff --git a/example/blink_flash/startup_stm32l1xx_md.s b/example/blink_flash/startup_stm32l1xx_md.s new file mode 100644 index 000000000..4ec8203b0 --- /dev/null +++ b/example/blink_flash/startup_stm32l1xx_md.s @@ -0,0 +1,366 @@ +/** + ****************************************************************************** + * @file startup_stm32l1xx_md.s + * @author MCD Application Team + * @version V1.0.0 + * @date 31-December-2010 + * @brief STM32L1xx Ultra Low Power Medium-density Devices vector table for + * RIDE7 toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ******************************************************************************* + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ ******************************************************************************* + */ + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +.equ BootRAM, 0xF108F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the clock system intitialization function.*/ +/* let main do the system initialization */ +/* bl SystemInit */ +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/******************************************************************************* +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler + .word PVD_IRQHandler + .word TAMPER_STAMP_IRQHandler + .word RTC_WKUP_IRQHandler + .word FLASH_IRQHandler + .word RCC_IRQHandler + .word EXTI0_IRQHandler + .word EXTI1_IRQHandler + .word EXTI2_IRQHandler + .word EXTI3_IRQHandler + .word EXTI4_IRQHandler + .word DMA1_Channel1_IRQHandler + .word DMA1_Channel2_IRQHandler + .word DMA1_Channel3_IRQHandler + .word DMA1_Channel4_IRQHandler + .word DMA1_Channel5_IRQHandler + .word DMA1_Channel6_IRQHandler + .word DMA1_Channel7_IRQHandler + .word ADC1_IRQHandler + .word USB_HP_IRQHandler + .word USB_LP_IRQHandler + .word DAC_IRQHandler + .word COMP_IRQHandler + .word EXTI9_5_IRQHandler + .word LCD_IRQHandler + .word TIM9_IRQHandler + .word TIM10_IRQHandler + .word TIM11_IRQHandler + .word TIM2_IRQHandler + .word TIM3_IRQHandler + .word TIM4_IRQHandler + .word I2C1_EV_IRQHandler + .word I2C1_ER_IRQHandler + .word I2C2_EV_IRQHandler + .word I2C2_ER_IRQHandler + .word SPI1_IRQHandler + .word SPI2_IRQHandler + .word USART1_IRQHandler + .word USART2_IRQHandler + .word USART3_IRQHandler + .word EXTI15_10_IRQHandler + .word RTC_Alarm_IRQHandler + .word USB_FS_WKUP_IRQHandler + .word TIM6_IRQHandler + .word TIM7_IRQHandler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word BootRAM /* @0x108. This is for boot in RAM mode for + STM32L15x ULtra Low Power Medium-density devices. */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMPER_STAMP_IRQHandler + .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_IRQHandler + .thumb_set DMA1_Channel2_IRQHandler,Default_Handler + + .weak DMA1_Channel3_IRQHandler + .thumb_set DMA1_Channel3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_IRQHandler + .thumb_set DMA1_Channel4_IRQHandler,Default_Handler + + .weak DMA1_Channel5_IRQHandler + .thumb_set DMA1_Channel5_IRQHandler,Default_Handler + + .weak DMA1_Channel6_IRQHandler + .thumb_set DMA1_Channel6_IRQHandler,Default_Handler + + .weak DMA1_Channel7_IRQHandler + .thumb_set DMA1_Channel7_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak USB_HP_IRQHandler + .thumb_set USB_HP_IRQHandler,Default_Handler + + .weak USB_LP_IRQHandler + .thumb_set USB_LP_IRQHandler,Default_Handler + + .weak DAC_IRQHandler + .thumb_set DAC_IRQHandler,Default_Handler + + .weak COMP_IRQHandler + .thumb_set COMP_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak LCD_IRQHandler + .thumb_set LCD_IRQHandler,Default_Handler + + .weak TIM9_IRQHandler + .thumb_set TIM9_IRQHandler,Default_Handler + + .weak TIM10_IRQHandler + .thumb_set TIM10_IRQHandler,Default_Handler + + .weak TIM11_IRQHandler + .thumb_set TIM11_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak USB_FS_WKUP_IRQHandler + .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + +/******************** (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***/ + diff --git a/example/blink_flash/stm32_flash.ld b/example/blink_flash/stm32_flash.ld new file mode 100644 index 000000000..146b16ecc --- /dev/null +++ b/example/blink_flash/stm32_flash.ld @@ -0,0 +1,173 @@ +/* +***************************************************************************** +** +** File : stm32_flash.ld +** +** Abstract : Linker script for STM32L152RB Device with +** 128KByte FLASH, 16KByte RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Environment : Atollic TrueSTUDIO(R) +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +** (c)Copyright Atollic AB. +** You may use this file as-is or modify it according to the needs of your +** project. Distribution of this file (unmodified or modified) is not +** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the +** rights to distribute the assembled, compiled & linked contents of this +** file as part of an application binary file, provided that it is built +** using the Atollic TrueSTUDIO(R) toolchain. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20004000; /* end of 16K RAM */ + +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0; /* required amount of heap */ +_Min_Stack_Size = 0x80; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K + MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K + RW_EEPROM (rw) : ORIGIN = 0x08080000, LENGTH = 32 +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(.fini_array*)) + KEEP (*(SORT(.fini_array.*))) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = .; + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : AT ( _sidata ) + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(4); + } >RAM + + /* MEMORY_bank1 section, code must be located here explicitly */ + /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ + .memory_b1_text : + { + *(.mb1text) /* .mb1text sections (code) */ + *(.mb1text*) /* .mb1text* sections (code) */ + *(.mb1rodata) /* read-only data (constants) */ + *(.mb1rodata*) + } >MEMORY_B1 + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + .DataFlash (NOLOAD): {*(.DataFlash)} >RW_EEPROM +} diff --git a/example/blink_flash/system_stm32l1xx.c b/example/blink_flash/system_stm32l1xx.c new file mode 100644 index 000000000..6deab320c --- /dev/null +++ b/example/blink_flash/system_stm32l1xx.c @@ -0,0 +1,367 @@ +/** + ****************************************************************************** + * @file system_stm32l1xx.c + * @author MCD Application Team + * @version V1.0.0 + * @date 2-June-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32L1xx Ultra + * Low Medium-density devices, and is generated by the clock configuration + * tool "STM32L1xx_Clock_Configuration_V1.0.0.xls". + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l1xx_md.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32l1xx_md.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and MSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define + * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + * System Clock Configuration + *============================================================================= + * System clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK | 16000000 Hz + *----------------------------------------------------------------------------- + * HCLK | 16000000 Hz + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * HSE Frequency | 8000000 Hz + *----------------------------------------------------------------------------- + * PLL DIV | Not Used + *----------------------------------------------------------------------------- + * PLL MUL | Not Used + *----------------------------------------------------------------------------- + * VDD | 3.3 V + *----------------------------------------------------------------------------- + * Vcore | 1.8 V (Range 1) + *----------------------------------------------------------------------------- + * Flash Latency | 0 WS + *----------------------------------------------------------------------------- + * Require 48MHz for USB clock | Disabled + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l1xx_system + * @{ + */ + +/** @addtogroup STM32L1xx_System_Private_Includes + * @{ + */ + +#include "stm32l1xx.h" + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Defines + * @{ + */ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Variables + * @{ + */ +uint32_t SystemCoreClock = 16000000; +__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +/** + * @} + */ + +/** @addtogroup STM32L1xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /*!< Set MSION bit */ + RCC->CR |= (uint32_t)0x00000100; + + /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ + RCC->CFGR &= (uint32_t)0x88FFC00C; + + /*!< Reset HSION, HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xEEFEFFFE; + + /*!< Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ + RCC->CFGR &= (uint32_t)0xFF02FFFF; + + /*!< Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI + * value as defined by the MSI range. + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + SystemCoreClock = (32768 * (1 << (msirange + 1))); + break; + case 0x04: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x08: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x0C: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; + pllmul = PLLMulTable[(pllmul >> 18)]; + plldiv = (plldiv >> 22) + 1; + + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + + if (pllsource == 0x00) + { + /* HSI oscillator clock selected as PLL clock entry */ + SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); + } + else + { + /* HSE selected as PLL clock entry */ + SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); + } + break; + default: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + SystemCoreClock = (32768 * (1 << (msirange + 1))); + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash + * settings. + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ + __IO uint32_t StartUpCounter = 0, HSIStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSI */ + RCC->CR |= ((uint32_t)RCC_CR_HSION); + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC->CR & RCC_CR_HSIRDY; + } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSIRDY) != RESET) + { + HSIStatus = (uint32_t)0x01; + } + else + { + HSIStatus = (uint32_t)0x00; + } + + if (HSIStatus == (uint32_t)0x01) + { + /* Flash 0 wait state */ + FLASH->ACR &= ~FLASH_ACR_LATENCY; + + /* Disable Prefetch Buffer */ + FLASH->ACR &= ~FLASH_ACR_PRFTEN; + + /* Disable 64-bit access */ + FLASH->ACR &= ~FLASH_ACR_ACC64; + + + /* Power enable */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Select the Voltage Range 1 (1.8 V) */ + PWR->CR = PWR_CR_VOS_0; + + + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != RESET) + { + } + + /* HCLK = SYSCLK /1*/ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + /* PCLK2 = HCLK /1*/ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK /1*/ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSI as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI; + + /* Wait till HSI is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI) + { + } + } + else + { + /* If HSI fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/flash/Makefile b/flash/Makefile index fe0dff7ce..8a30b4113 100644 --- a/flash/Makefile +++ b/flash/Makefile @@ -1,12 +1,27 @@ +# make ... for both libusb and libsg +# +# make CONFIG_USE_LIBSG=0 ... +# for just libusb +# +CC=gcc + CFLAGS+=-g -CFLAGS+=-DCONFIG_USE_LIBUSB -CFLAGS+=-DCONFIG_USE_LIBSG +CFLAGS+=-DCONFIG_USE_LIBUSB=1 CFLAGS+=-DDEBUG CFLAGS+=-std=gnu99 CFLAGS+=-Wall -Wextra CFLAGS+=-I../src -LDFLAGS=-L.. -lstlink -lusb-1.0 -lsgutils2 +LDFLAGS=-lusb-1.0 -L.. -lstlink + +ifeq ($(CONFIG_USE_LIBSG),) +CONFIG_USE_LIBSG=1 +endif + +ifneq ($(CONFIG_USE_LIBSG),0) +CFLAGS+=-DCONFIG_USE_LIBSG=1 +LDFLAGS+=-lsgutils2 +endif SRCS=main.c OBJS=$(SRCS:.c=.o) diff --git a/flash/main.c b/flash/main.c index c8b15e0b9..e47417437 100644 --- a/flash/main.c +++ b/flash/main.c @@ -3,47 +3,134 @@ #include #include +#include +#include #include "stlink-common.h" -int main(int ac, char** av) +struct opts { - /* stlinkv1 command line: ./flash /dev/sgX path addr */ - /* stlinkv2 command line: ./flash path addr */ - - stlink_t* sl = NULL; + unsigned int do_read; + const char* devname; + const char* filename; stm32_addr_t addr; - const char* path; - int err; + size_t size; +}; + +static void usage(void) +{ + puts("stlinkv1 command line: ./flash {read|write} /dev/sgX path addr "); + puts("stlinkv2 command line: ./flash {read|write} path addr "); +} + +static int get_opts(struct opts* o, int ac, char** av) +{ + /* stlinkv1 command line: ./flash {read|write} /dev/sgX path addr */ + /* stlinkv2 command line: ./flash {read|write} path addr */ + + unsigned int i = 0; + + if (ac < 3) return -1; - if (ac == 4) /* stlinkv1 */ + /* stlinkv2 */ + o->devname = NULL; + + if (strcmp(av[0], "read") == 0) { - static const int scsi_verbose = 2; - sl = stlink_quirk_open(av[1], scsi_verbose); - path = av[2]; - addr = strtoul(av[3], NULL, 16); + o->do_read = 1; + + /* stlinkv1 mode */ + if (ac == 5) + { + o->devname = av[1]; + i = 1; + } + + o->size = strtoul(av[i + 3], NULL, 10); } - else if (ac == 3) /* stlinkv2 */ + else if (strcmp(av[0], "write") == 0) { - sl = stlink_open_usb(NULL, 10); - path = av[1]; - addr = strtoul(av[2], NULL, 16); + o->do_read = 0; + + /* stlinkv1 mode */ + if (ac == 4) + { + o->devname = av[1]; + i = 1; + } } - else /* invalid */ + else + { + return -1; + } + + o->filename = av[i + 1]; + o->addr = strtoul(av[i + 2], NULL, 16); + + return 0; +} + + +int main(int ac, char** av) +{ + stlink_t* sl = NULL; + struct opts o; + int err = -1; + + if (get_opts(&o, ac - 1, av + 1) == -1) { printf("invalid command line\n"); + usage(); goto on_error; } - if (sl == NULL) goto on_error; - - err = stlink_fwrite_flash(sl, path, addr); - if (err == -1) + if (o.devname != NULL) /* stlinkv1 */ { - printf("stlink_fwrite_flash() == -1\n"); +#if CONFIG_USE_LIBSG + static const int scsi_verbose = 2; + sl = stlink_quirk_open(o.devname, scsi_verbose); + if (sl == NULL) goto on_error; +#else + printf("not compiled for use with STLink/V1"); goto on_error; +#endif + } + else /* stlinkv2 */ + { + sl = stlink_open_usb(10); + if (sl == NULL) goto on_error; } + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) + stlink_exit_dfu_mode(sl); + + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) + stlink_enter_swd_mode(sl); + + stlink_reset(sl); + + if (o.do_read == 0) /* write */ + { + err = stlink_fwrite_flash(sl, o.filename, o.addr); + if (err == -1) + { + printf("stlink_fwrite_flash() == -1\n"); + goto on_error; + } + } + else /* read */ + { + err = stlink_fread(sl, o.filename, o.addr, o.size); + if (err == -1) + { + printf("stlink_fread() == -1\n"); + goto on_error; + } + } + + /* success */ + err = 0; + on_error: if (sl != NULL) stlink_close(sl); diff --git a/gdbserver/Makefile b/gdbserver/Makefile index e9d2774f3..a8d1b90aa 100644 --- a/gdbserver/Makefile +++ b/gdbserver/Makefile @@ -1,13 +1,24 @@ +# make ... for both libusb and libsg +# +# make CONFIG_USE_LIBSG=0 ... +# for just libusb +# PRG := st-util OBJS = gdb-remote.o gdb-server.o CFLAGS+=-g -Wall -Werror -std=gnu99 -I../src -CFLAGS+=-DCONFIG_USE_LIBUSB -CFLAGS+=-DCONFIG_USE_LIBSG -LIBS := -lstlink -lusb-1.0 -lsgutils2 -LDFLAGS+=$(LIBS) -L.. +CFLAGS+=-DCONFIG_USE_LIBUSB=1 +LDFLAGS=-lusb-1.0 -L.. -lstlink +ifeq ($(CONFIG_USE_LIBSG),) +CONFIG_USE_LIBSG=1 +endif + +ifneq ($(CONFIG_USE_LIBSG),0) +CFLAGS+=-DCONFIG_USE_LIBSG=1 +LDFLAGS+=-lsgutils2 +endif all: $(PRG) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 72f433ffe..67f0be0e6 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -14,6 +14,7 @@ #include #include #include +#include #include @@ -24,6 +25,12 @@ #define FLASH_PAGE_MASK (~((1 << 10) - 1)) #define FLASH_SIZE (FLASH_PAGE * 128) +volatile int do_exit = 0; +void ctrl_c(int sig) +{ + do_exit = 1; +} + static const char hex[] = "0123456789abcdef"; static const char* current_memory_map = NULL; @@ -32,6 +39,11 @@ static const char* current_memory_map = NULL; * Chip IDs are explained in the appropriate programming manual for the * DBGMCU_IDCODE register (0xE0042000) */ + +#define CORE_M3_R1 0x1BA00477 +#define CORE_M3_R2 0x4BA00477 +#define CORE_M4_R0 0x2BA01477 + struct chip_params { uint32_t chip_id; char* description; @@ -43,11 +55,11 @@ struct chip_params { { 0x410, "F1 Medium-density device", 0x1ffff7e0, 0x20000, 0x400, 0x5000, 0x1ffff000, 0x800 }, // table 2, pm0063 { 0x411, "F2 device", 0, /* No flash size register found in the docs*/ - 0x100000, 0x20000, 0x20000, 0x1ff00000, 0x7800 }, // table 1, pm0059 + 0x100000, 0x20000, 0x20000, 0x1fff0000, 0x7800 }, // table 1, pm0059 { 0x412, "F1 Low-density device", 0x1ffff7e0, 0x8000, 0x400, 0x2800, 0x1ffff000, 0x800 }, // table 1, pm0063 { 0x413, "F4 device", 0x1FFF7A10, - 0x100000, 0x20000, 0x20000, 0x1ff00000, 0x7800 }, // table 1, pm0081 + 0x100000, 0x20000, 0x30000, 0x1fff0000, 0x7800 }, // table 1, pm0081 { 0x414, "F1 High-density device", 0x1ffff7e0, 0x80000, 0x800, 0x10000, 0x1ffff000, 0x800 }, // table 3 pm0063 // This ignores the EEPROM! (and uses the page erase size, @@ -79,15 +91,10 @@ int main(int argc, char** argv) { switch(argc) { - default: { - fprintf(stderr, HelpStr, NULL); - return 1; - } - case 3 : { //sl = stlink_quirk_open(argv[2], 0); - // FIXME - hardcoded to usb.... - sl = stlink_open_usb(argv[2], 10); + // FIXME - hardcoded to usb.... + sl = stlink_open_usb(10); if(sl == NULL) return 1; break; } @@ -99,6 +106,7 @@ int main(int argc, char** argv) { } } +#if CONFIG_USE_LIBSG case 1 : { // Search ST-LINK (from /dev/sg0 to /dev/sg99) const int DevNumMax = 99; int ExistDevCount = 0; @@ -136,18 +144,32 @@ int main(int argc, char** argv) { } break; } +#endif + + default: { + fprintf(stderr, HelpStr, NULL); + return 1; + } } - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { - stlink_exit_dfu_mode(sl); - } + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { + stlink_exit_dfu_mode(sl); + } if(stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } uint32_t chip_id = stlink_chip_id(sl); - printf("Chip ID is %08x.\n", chip_id); + uint32_t core_id = stlink_core_id(sl); + + /* Fix chip_id for F4 */ + if (((chip_id & 0xFFF) == 0x411) && (core_id == CORE_M4_R0)) { + printf("Fixing wrong chip_id for STM32F4 Rev A errata\n"); + chip_id = 0x413; + } + + printf("Chip ID is %08x, Core ID is %08x.\n", chip_id, core_id); const struct chip_params* params = NULL; @@ -182,6 +204,9 @@ int main(int argc, char** argv) { while(serve(sl, port) == 0); + /* Switch back to mass storage mode before closing. */ + stlink_run(sl); + stlink_exit_debug_mode(sl); stlink_close(sl); return 0; @@ -578,7 +603,9 @@ int serve(stlink_t *sl, int port) { printf("Listening at *:%d...\n", port); + (void) signal (SIGINT, ctrl_c); int client = accept(sock, NULL, NULL); + signal (SIGINT, SIG_DFL); if(client < 0) { perror("accept"); return 1; diff --git a/src/stlink-common.h b/src/stlink-common.h index cb6c6cc09..9481609f6 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -175,6 +175,7 @@ extern "C" { /* sram settings */ #define STM32_SRAM_BASE 0x20000000 #define STM32_SRAM_SIZE (8 * 1024) +#define STM32L_SRAM_SIZE (16 * 1024) stm32_addr_t sram_base; size_t sram_size; diff --git a/src/stlink-sg.c b/src/stlink-sg.c index f8865e1e4..b8220de13 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -80,12 +80,14 @@ #include #include +#include "stlink-common.h" + +#if CONFIG_USE_LIBSG // sgutils2 (apt-get install libsgutils2-dev) #include #include - -#include "stlink-common.h" #include "stlink-sg.h" +#endif // Suspends execution of the calling process for diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 2433d6c16..ff9ef71de 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -1,4 +1,3 @@ -#include #include #include #include @@ -9,6 +8,8 @@ #include "stlink-common.h" #include "stlink-usb.h" +enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; + void _stlink_usb_close(stlink_t* sl) { struct stlink_libusb * const handle = sl->backend_data; // maybe we couldn't even get the usb device? @@ -19,8 +20,9 @@ void _stlink_usb_close(stlink_t* sl) { if (handle->rep_trans != NULL) libusb_free_transfer(handle->rep_trans); - if (handle->usb_handle != NULL) + if (handle->usb_handle != NULL) { libusb_close(handle->usb_handle); + } libusb_exit(handle->libusb_ctx); free(handle); @@ -88,10 +90,11 @@ int submit_wait(struct stlink_libusb *slu, struct libusb_transfer * trans) { return 0; } -ssize_t send_recv(struct stlink_libusb* handle, +ssize_t send_recv(struct stlink_libusb* handle, int terminate, unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, size_t rxsize) { /* note: txbuf and rxbuf can point to the same area */ + int res = 0; libusb_fill_bulk_transfer(handle->req_trans, handle->usb_handle, handle->ep_req, @@ -100,122 +103,146 @@ ssize_t send_recv(struct stlink_libusb* handle, 0 ); - printf("submit_wait(req)\n"); - if (submit_wait(handle, handle->req_trans)) return -1; /* send_only */ - if (rxsize == 0) return 0; - - /* read the response */ - - libusb_fill_bulk_transfer(handle->rep_trans, handle->usb_handle, - handle->ep_rep, rxbuf, rxsize, NULL, NULL, 0); - - printf("submit_wait(rep)\n"); - - if (submit_wait(handle, handle->rep_trans)) return -1; + if (rxsize != 0) { + + /* read the response */ + + libusb_fill_bulk_transfer(handle->rep_trans, handle->usb_handle, + handle->ep_rep, rxbuf, rxsize, NULL, NULL, 0); + + if (submit_wait(handle, handle->rep_trans)) return -1; + res = handle->rep_trans->actual_length; + } + if ((handle->protocoll == 1) && terminate) { + /* Read the SG reply */ + unsigned char sg_buf[13]; + libusb_fill_bulk_transfer + (handle->rep_trans, handle->usb_handle, + handle->ep_rep, sg_buf, 13, NULL, NULL, 0); + res = submit_wait(handle, handle->rep_trans); + /* The STLink doesn't seem to evaluate the sequence number */ + handle->sg_transfer_idx++; + if (res ) return -1; + } return handle->rep_trans->actual_length; } static inline int send_only -(struct stlink_libusb* handle, unsigned char* txbuf, size_t txsize) { - return send_recv(handle, txbuf, txsize, NULL, 0); +(struct stlink_libusb* handle, int terminate, + unsigned char* txbuf, size_t txsize) { + return send_recv(handle, terminate, txbuf, txsize, NULL, 0); } -// KARL - fixme, common code! (or, one per backend) -// candidate for common code... - - -static int is_stlink_device(libusb_device * dev) { +/* Search for a STLINK device, either any or teh one with the given PID + * Return the protocoll version + */ +static int is_stlink_device(libusb_device * dev, uint16_t pid) { struct libusb_device_descriptor desc; + int version; if (libusb_get_device_descriptor(dev, &desc)) return 0; - printf("device: 0x%04x, 0x%04x\n", desc.idVendor, desc.idProduct); - if (desc.idVendor != USB_ST_VID) return 0; - if (desc.idProduct != USB_STLINK_32L_PID) + if ((desc.idProduct != USB_STLINK_32L_PID) && + (desc.idProduct != USB_STLINK_PID )) + return 0; + + if(pid && (pid != desc.idProduct)) return 0; + if (desc.idProduct == USB_STLINK_PID ) + version = 1; + else + version = 2; - return 1; + return version; +} + +static int fill_command +(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t len) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + int i = 0; + memset(cmd, 0, sizeof (sl->c_buf)); + if(slu->protocoll == 1) { + cmd[i++] = 'U'; + cmd[i++] = 'S'; + cmd[i++] = 'B'; + cmd[i++] = 'C'; + write_uint32(&cmd[i], slu->sg_transfer_idx); + write_uint32(&cmd[i + 4], len); + i += 8; + cmd[i++] = (dir == SG_DXFER_FROM_DEV)?0x80:0; + cmd[i++] = 0; /* Logical unit */ + cmd[i++] = 0xa; /* Command length */ + } + return i; } void _stlink_usb_version(stlink_t *sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + uint32_t rep_len = 6; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_GET_VERSION; - buf[1] = 0x80; + cmd[i++] = STLINK_GET_VERSION; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 6); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; } - -#if 1 /* DEBUG */ - { - ssize_t i; - for (i = 0; i < size; ++i) printf("%02x", buf[i]); - printf("\n"); - } -#endif /* DEBUG */ } void _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; - unsigned char *cmd_buf = sl->c_buf; - - memset(cmd_buf, 0, STLINK_CMD_SIZE); - cmd_buf[0] = STLINK_DEBUG_COMMAND; - cmd_buf[1] = STLINK_DEBUG_WRITEMEM_32BIT; - write_uint32(cmd_buf + 2, addr); - write_uint16(cmd_buf + 6, len); - send_only(slu, cmd_buf, STLINK_CMD_SIZE); - -#if Q_BUF_LEN < UINT16_MAX - assert(len < sizeof(sl->q_buf)); // makes a compiler warning? always true? -#endif - assert((len & 3) == 0); - send_only(slu, buf, len); + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + + int i = fill_command(sl, SG_DXFER_TO_DEV, len); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_WRITEMEM_32BIT; + write_uint32(&cmd[i], addr); + write_uint16(&cmd[i + 4], len); + send_only(slu, 0, cmd, slu->cmd_len); + send_only(slu, 1, data, len); } void _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; - unsigned char *cmd_buf = sl->c_buf; - - memset(cmd_buf, 0, STLINK_CMD_SIZE); - cmd_buf[0] = STLINK_DEBUG_COMMAND; - cmd_buf[1] = STLINK_DEBUG_WRITEMEM_8BIT; - write_uint32(cmd_buf + 2, addr); - write_uint16(cmd_buf + 6, len); - send_only(slu, cmd_buf, STLINK_CMD_SIZE); - -#if Q_BUF_LEN < UINT16_MAX - assert(len < sizeof(sl->q_buf)); // makes a compiler warning? always true? -#endif - send_only(slu, buf, len); + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + + int i = fill_command(sl, SG_DXFER_TO_DEV, 0); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_WRITEMEM_8BIT; + write_uint32(&cmd[i], addr); + write_uint16(&cmd[i + 4], len); + send_only(slu, 0, cmd, slu->cmd_len); + send_only(slu, 1, data, len); } int _stlink_usb_current_mode(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + unsigned char* const data = sl->q_buf; ssize_t size; - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_GET_CURRENT_MODE; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_GET_CURRENT_MODE; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return -1; @@ -225,76 +252,71 @@ int _stlink_usb_current_mode(stlink_t * sl) { void _stlink_usb_core_id(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + unsigned char* const data = sl->q_buf; ssize_t size; + int rep_len = 4; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_READCOREID; + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_READCOREID; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 4); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; } - sl->core_id = read_uint32(buf, 0); + sl->core_id = read_uint32(data, 0); } void _stlink_usb_status(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_GETSTATUS; - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_GETSTATUS; - - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; } - - /* todo: stlink_core_stat */ - - // FIXME - decode into sl->core_stat -#if 1 /* DEBUG */ - printf("status == 0x%x\n", buf[0]); -#endif /* DEBUG */ - } void _stlink_usb_force_debug(stlink_t *sl) { struct stlink_libusb *slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); - - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_FORCEDEBUG; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_FORCEDEBUG; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; } } - void _stlink_usb_enter_swd_mode(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + const int rep_len = 0; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_ENTER; + cmd[i++] = STLINK_DEBUG_ENTER_SWD; - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_SWD_ENTER; - buf[2] = STLINK_DEBUG_ENTER_SWD; - - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); + size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -303,14 +325,14 @@ void _stlink_usb_enter_swd_mode(stlink_t * sl) { void _stlink_usb_exit_dfu_mode(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_DFU_COMMAND; - buf[1] = STLINK_DFU_EXIT; + cmd[i++] = STLINK_DFU_COMMAND; + cmd[i++] = STLINK_DFU_EXIT; - size = send_only(slu, buf, 16); + size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -323,14 +345,16 @@ void _stlink_usb_exit_dfu_mode(stlink_t* sl) { */ void _stlink_usb_reset(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_RESETSYS; + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_RESETSYS; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, sizeof (sl->q_buf)); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -340,14 +364,16 @@ void _stlink_usb_reset(stlink_t * sl) { void _stlink_usb_step(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_STEPCORE; + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_STEPCORE; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -360,31 +386,32 @@ void _stlink_usb_step(stlink_t* sl) { */ void _stlink_usb_run(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_RUNCORE; + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_RUNCORE; - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, 2); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; } - } void _stlink_usb_exit_debug_mode(stlink_t *sl) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_EXIT; + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_EXIT; - size = send_only(slu, buf, 16); + size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { printf("[!] send_only\n"); return; @@ -393,21 +420,17 @@ void _stlink_usb_exit_debug_mode(stlink_t *sl) { void _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; + int i = fill_command(sl, SG_DXFER_FROM_DEV, len); - /* assume len < sizeof(sl->q_buf) */ + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_READMEM_32BIT; + write_uint32(&cmd[i], addr); + write_uint16(&cmd[i + 4], len); - memset(buf, 0, sizeof (sl->q_buf)); - buf[0] = STLINK_DEBUG_COMMAND; - buf[1] = STLINK_DEBUG_READMEM_32BIT; - write_uint32(buf + 2, addr); - /* windows usb logs show only one byte is used for length ... */ - // Presumably, this is because usb transfers can't be 16 bits worth of bytes long... - assert (len < 256); - buf[6] = (uint8_t) len; - - size = send_recv(slu, buf, STLINK_CMD_SIZE, buf, len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -418,20 +441,17 @@ void _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { stlink_print_data(sl); } - -#if 1 /* stlinkv1 */ - void _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; - unsigned char* const cmd_buf = sl->c_buf; + unsigned char* const cmd = sl->c_buf; + unsigned char* const data = sl->q_buf; ssize_t size; - int i; + uint32_t rep_len = 84; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(cmd_buf, 0, STLINK_CMD_SIZE); - cmd_buf[0] = STLINK_DEBUG_COMMAND; - cmd_buf[1] = STLINK_DEBUG_READALLREGS; - size = send_recv(slu, cmd_buf, STLINK_CMD_SIZE, buf, 84); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_READALLREGS; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -455,53 +475,19 @@ void _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) { DD(sl, "rw2 = 0x%08x\n", read_uint32(sl->q_buf, 80)); } -#else /* stlinkv2 */ - -static void _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; - unsigned char* const cmd_buf = sl->c_buf; - ssize_t size; - int i; - -#define STLINK_JTAG_COMMAND 0xf2 -#define STLINK_JTAG_READALLREGS2 0x3a - memset(cmd_buf, 0, STLINK_CMD_SIZE); - cmd_buf[0] = STLINK_JTAG_COMMAND; - cmd_buf[1] = STLINK_JTAG_READALLREGS2; - size = send_recv(slu, cmd_buf, STLINK_CMD_SIZE, buf, 84); - - if (size == -1) { - printf("[!] send_recv\n"); - return; - } - - sl->q_len = (size_t) size; - - for(i=0; i<16; i++) - regp->r[i]= read_uint32(sl->q_buf, i*4); - - regp->xpsr = read_uint32(sl->q_buf, 64); - regp->main_sp = read_uint32(sl->q_buf, 68); - regp->process_sp = read_uint32(sl->q_buf, 72); - regp->rw = read_uint32(sl->q_buf, 76); - regp->rw2 = read_uint32(sl->q_buf, 80); -} - -#endif /* stlinkv1 */ - void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; - unsigned char* const cmd_buf = sl->c_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t r; + uint32_t rep_len = 4; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - memset(cmd_buf, 0, STLINK_CMD_SIZE); - cmd_buf[0] = STLINK_DEBUG_COMMAND; - cmd_buf[1] = STLINK_DEBUG_READREG; - cmd_buf[2] = (uint8_t) r_idx; - size = send_recv(slu, cmd_buf, STLINK_CMD_SIZE, buf, 4); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_READREG; + cmd[i++] = (uint8_t) r_idx; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -522,31 +508,29 @@ void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { regp->process_sp = r; break; case 19: - regp->rw = r; //XXX ?(primask, basemask etc.) + regp->rw = r; /* XXX ?(primask, basemask etc.) */ break; case 20: - regp->rw2 = r; //XXX ?(primask, basemask etc.) + regp->rw2 = r; /* XXX ?(primask, basemask etc.) */ break; default: regp->r[r_idx] = r; } } - -#if 1 /* stlinkv1 */ - void _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; - unsigned char *cmd_buf = sl->c_buf; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; ssize_t size; - - memset(cmd_buf, 0, STLINK_CMD_SIZE); - cmd_buf[0] = STLINK_DEBUG_COMMAND; - cmd_buf[1] = STLINK_DEBUG_WRITEREG; - cmd_buf[2] = idx; - write_uint32(cmd_buf + 3, reg); - size = send_recv(slu, cmd_buf, STLINK_CMD_SIZE, buf, 2); + uint32_t rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_WRITEREG; + cmd[i++] = idx; + write_uint32(&cmd[i], reg); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); return; @@ -555,32 +539,6 @@ void _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { stlink_print_data(sl); } -#else /* stlinkv2 */ - -void _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const buf = sl->q_buf; - unsigned char *cmd_buf = sl->c_buf; - ssize_t size; - -#define STLINK_JTAG_WRITEREG2 0x34 - memset(cmd_buf, 0, STLINK_CMD_SIZE); - cmd_buf[0] = STLINK_JTAG_COMMAND; - cmd_buf[1] = STLINK_JTAG_WRITEREG2; - cmd_buf[2] = idx; - write_uint32(cmd_buf + 3, reg); - size = send_recv(slu, cmd_buf, STLINK_CMD_SIZE, buf, 2); - if (size == -1) { - printf("[!] send_recv\n"); - return; - } - sl->q_len = (size_t) size; - stlink_print_data(sl); -} - -#endif /* stlinkv1 */ - - stlink_backend_t _stlink_usb_backend = { _stlink_usb_close, _stlink_usb_exit_debug_mode, @@ -604,38 +562,48 @@ stlink_backend_t _stlink_usb_backend = { }; -stlink_t* stlink_open_usb(const char *dev_name, const int verbose) { +stlink_t* stlink_open_usb(const int verbose) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; - - /* unused */ - dev_name = dev_name; + int error = -1; + libusb_device** devs = NULL; + libusb_device* dev; + ssize_t i; + ssize_t count; + int config; + char *iSerial = NULL; sl = malloc(sizeof (stlink_t)); slu = malloc(sizeof (struct stlink_libusb)); if (sl == NULL) goto on_error; if (slu == NULL) goto on_error; + memset(sl, 0, sizeof (stlink_t)); + memset(slu, 0, sizeof (struct stlink_libusb)); sl->verbose = verbose; + sl->backend = &_stlink_usb_backend; + sl->backend_data = slu; - if (slu->libusb_ctx != NULL) { - fprintf(stderr, "reopening with an existing context? undefined behaviour!\n"); - goto on_error; - } else { - if (libusb_init(&(slu->libusb_ctx))) { - fprintf(stderr, "failed to init libusb context, wrong version of libraries?\n"); - goto on_error; - } - } + sl->core_stat = STLINK_CORE_STAT_UNKNOWN; - int error = -1; + /* flash memory settings */ + sl->flash_base = STM32_FLASH_BASE; + sl->flash_size = STM32_FLASH_SIZE; + sl->flash_pgsz = STM32_FLASH_PGSZ; - libusb_device** devs = NULL; - libusb_device* dev; - ssize_t i; - ssize_t count; - int config; + /* system memory */ + sl->sys_base = STM32_SYSTEM_BASE; + sl->sys_size = STM32_SYSTEM_SIZE; + + /* sram memory settings */ + sl->sram_base = STM32_SRAM_BASE; + sl->sram_size = STM32L_SRAM_SIZE; + if (libusb_init(&(slu->libusb_ctx))) { + fprintf(stderr, "failed to init libusb context, wrong version of libraries?\n"); + goto on_error; + } + count = libusb_get_device_list(slu->libusb_ctx, &devs); if (count < 0) { printf("libusb_get_device_list\n"); @@ -644,14 +612,47 @@ stlink_t* stlink_open_usb(const char *dev_name, const int verbose) { for (i = 0; i < count; ++i) { dev = devs[i]; - if (is_stlink_device(dev)) break; + slu->protocoll = is_stlink_device(dev, 0); + if (slu->protocoll > 0) break; } - if (i == count) return NULL; + if (i == count) goto on_libusb_error; if (libusb_open(dev, &(slu->usb_handle))) { printf("libusb_open()\n"); goto on_libusb_error; } + + if (iSerial) { + unsigned char serial[256]; + struct libusb_device_descriptor desc; + int r; + + r = libusb_get_device_descriptor(dev, &desc); + if (r<0) { + printf("Can't get descriptor to match Iserial\n"); + goto on_libusb_error; + } + r = libusb_get_string_descriptor_ascii + (slu->usb_handle, desc.iSerialNumber, serial, 256); + if (r<0) { + printf("Can't get Serialnumber to match Iserial\n"); + goto on_libusb_error; + } + if (strcmp((char*)serial, iSerial)) { + printf("Mismatch in serial numbers, dev %s vs given %s\n", + serial, iSerial); + goto on_libusb_error; + } + } + + if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { + int r; + + r = libusb_detach_kernel_driver(slu->usb_handle, 0); + if (r<0) + printf("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); + goto on_libusb_error; + } if (libusb_get_configuration(slu->usb_handle, &config)) { /* this may fail for a previous configured device */ @@ -688,15 +689,20 @@ stlink_t* stlink_open_usb(const char *dev_name, const int verbose) { slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; - /* libusb_reset_device(slu->usb_handle); */ + slu->sg_transfer_idx = 0; + slu->cmd_len = (slu->protocoll == 1)? STLINK_SG_SIZE: STLINK_CMD_SIZE; /* success */ + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { + printf("-- exit_dfu_mode\n"); + stlink_exit_dfu_mode(sl); + } + stlink_version(sl); error = 0; on_libusb_error: if (devs != NULL) { libusb_free_device_list(devs, 1); - fprintf(stderr, "freed libusb device list\n"); } if (error == -1) { @@ -704,8 +710,6 @@ stlink_t* stlink_open_usb(const char *dev_name, const int verbose) { return NULL; } - sl->backend = &_stlink_usb_backend; - sl->backend_data = slu; /* success */ return sl; diff --git a/src/stlink-usb.h b/src/stlink-usb.h index 4ed655b7e..c632a8c41 100644 --- a/src/stlink-usb.h +++ b/src/stlink-usb.h @@ -15,6 +15,7 @@ extern "C" { #include #include "stlink-common.h" +#define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 #if defined(CONFIG_USE_LIBUSB) @@ -25,6 +26,9 @@ extern "C" { struct libusb_transfer* rep_trans; unsigned int ep_req; unsigned int ep_rep; + int protocoll; + unsigned int sg_transfer_idx; + unsigned int cmd_len; }; #else #error "it's all bad!" @@ -32,7 +36,7 @@ extern "C" { #endif - stlink_t* stlink_open_usb(const char *dev_name, const int verbose); + stlink_t* stlink_open_usb(const int verbose); #ifdef __cplusplus diff --git a/src/test_sg.c b/src/test_sg.c index 137eca4cf..34fbe540c 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -6,8 +6,10 @@ #include #include +#if CONFIG_USE_LIBSG #include #include +#endif #include "stlink-common.h" int main(int argc, char *argv[]) { @@ -210,4 +212,4 @@ int main(int argc, char *argv[]) { //fflush(stderr); fflush(stdout); return EXIT_SUCCESS; -} \ No newline at end of file +} diff --git a/src/test_usb.c b/src/test_usb.c index bd81ec1d5..343e355a3 100644 --- a/src/test_usb.c +++ b/src/test_usb.c @@ -10,7 +10,7 @@ int main(int ac, char** av) { ac = ac; av = av; - sl = stlink_open_usb(NULL, 10); + sl = stlink_open_usb(10); if (sl != NULL) { printf("-- version\n"); stlink_version(sl); From 2f7b70f1a8ef8d1204b1d16b58c4d3a160f8156a Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 15:13:22 +0000 Subject: [PATCH 0008/1435] Add option parsing and help Supports setting the gdb listen port Supports setting which version of stlink to use Supports setting the device to use (in case autoprobing doesn't work) --- doc/tutorial/tutorial.pdf | Bin 110077 -> 110986 bytes doc/tutorial/tutorial.tex | 12 +-- gdbserver/gdb-server.c | 182 +++++++++++++++++++++++++++++--------- 3 files changed, 145 insertions(+), 49 deletions(-) diff --git a/doc/tutorial/tutorial.pdf b/doc/tutorial/tutorial.pdf index 9202ed4dc33c1bcafdcf4db30807103a22c846c8..4ffcc3e563b3df294e331eb3fae97f9843f31817 100644 GIT binary patch delta 47877 zcmV)IK)k>G+Xjl`2Cx$-n( z+bEVsLOuw=V)YizedAR?Q?Cc^F0Wh^qehfKH&h#_a-8~_JuO#{z7I+wNXPn6NY3_E zUHr9iMd;J+oxANQ;k#|NZT{u^5D5cnjG6}OOPP;Ak8RaoZcl@H{ot79-Of{$v;<~s zN)@Q9rY}1`ls49a9eZA%pWl>i>DDACHyNP;`Cz~Ni|HKG>)oPOiDEGkCc>uYglkxXXC!T^g* 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b/doc/tutorial/tutorial.tex index d1ba4fdbd..a5548058f 100644 --- a/doc/tutorial/tutorial.tex +++ b/doc/tutorial/tutorial.tex @@ -106,12 +106,14 @@ \section{Building and running a program} are using, you must run one of the 2 commands:\\ \begin{small} \begin{lstlisting}[frame=tb] -# STM32VL discovery kit -$> sudo ./st-util /dev/sg2 +# STM32VL discovery kit (onboard ST-link) +$> sudo ./st-util --stlinkv1 [-d /dev/sg2] -# STM32L discovery kit -# 2 dummy command line arguments needed, will be fixed soon -$> sudo ./st-util fu bar +# STM32L discovery kit (onboard ST-link/V2) +$> sudo ./st-util + +# Full help for other options (listen port, version) +$> ./st-util --help \end{lstlisting} \end{small} diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 67f0be0e6..30ee01483 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -6,6 +6,7 @@ license that can be found in the LICENSE file. */ +#include #include #include #include @@ -20,6 +21,12 @@ #include "gdb-remote.h" +#define DEFAULT_LOGGING_LEVEL 10 +#define DEFAULT_GDB_LISTEN_PORT 4242 + +#define STRINGIFY_inner(name) #name +#define STRINGIFY(name) STRINGIFY_inner(name) + #define FLASH_BASE 0x08000000 #define FLASH_PAGE (sl->flash_pgsz) #define FLASH_PAGE_MASK (~((1 << 10) - 1)) @@ -77,79 +84,168 @@ struct chip_params { { 0 } }; +typedef struct _st_state_t { + // things from command line, bleh + int stlink_version; + // "/dev/serial/by-id/usb-FTDI_TTL232R-3V3_FTE531X6-if00-port0" is only 58 chars + char devicename[100]; + int logging_level; + int listen_port; +} st_state_t; + + int serve(stlink_t *sl, int port); char* make_memory_map(const struct chip_params *params, uint32_t flash_size); -int main(int argc, char** argv) { - - stlink_t *sl = NULL; - const char * HelpStr = "Usage:\n" - "\t st-util port [/dev/sgX]\n" - "\t st-util [port]\n" - "\t st-util --help\n"; +int parse_options(int argc, char** argv, st_state_t *st) { + static struct option long_options[] = { + {"help", no_argument, NULL, 'h'}, + {"verbose", optional_argument, NULL, 'v'}, + {"device", required_argument, NULL, 'd'}, + {"stlink_version", required_argument, NULL, 's'}, + {"stlinkv1", no_argument, NULL, '1'}, + {"listen_port", required_argument, NULL, 'p'}, + {0, 0, 0, 0}, + }; + const char * help_str = "%s - usage:\n\n" + " -h, --help\t\tPrint this help\n" + " -vXX, --verbose=XX\tspecify a specific verbosity level (0..99)\n" + " -v, --verbose\tspecify generally verbose logging\n" + " -d , --device=/dev/stlink2_1\n" + "\t\t\tWhere is your stlink device connected?\n" + " -s X, --stlink_version=X\n" + "\t\t\tChoose what version of stlink to use, (defaults to 2)\n" + " -1, --stlinkv1\tForce stlink version 1\n" + " -p 4242, --listen_port=1234\n" + "\t\t\tSet the gdb server listen port. " + "(default port: " STRINGIFY(DEFAULT_GDB_LISTEN_PORT) ")\n" + ; + + + int option_index = 0; + int c; + int q; + while ((c = getopt_long(argc, argv, "hv::d:s:1p:", long_options, &option_index)) != -1) { + switch (c) { + case 0: + printf("XXXXX Shouldn't really normally come here, only if there's no corresponding option\n"); + printf("option %s", long_options[option_index].name); + if (optarg) { + printf(" with arg %s", optarg); + } + printf("\n"); + break; + case 'h': + printf(help_str, argv[0]); + exit(EXIT_SUCCESS); + break; + case 'v': + if (optarg) { + st->logging_level = atoi(optarg); + } else { + st->logging_level = DEFAULT_LOGGING_LEVEL; + } + break; + case 'd': + if (strlen(optarg) > sizeof (st->devicename)) { + fprintf(stderr, "device name too long: %ld\n", strlen(optarg)); + } else { + strcpy(st->devicename, optarg); + } + break; + case '1': + st->stlink_version = 1; + break; + case 's': + sscanf(optarg, "%i", &q); + if (q < 0 || q > 2) { + fprintf(stderr, "stlink version %d unknown!\n", q); + exit(EXIT_FAILURE); + } + st->stlink_version = q; + break; + case 'p': + sscanf(optarg, "%i", &q); + if (q < 0) { + fprintf(stderr, "Can't use a negative port to listen on: %d\n", q); + exit(EXIT_FAILURE); + } + st->listen_port = q; + break; + } + } + + if (optind < argc) { + printf("non-option ARGV-elements: "); + while (optind < argc) + printf("%s ", argv[optind++]); + printf("\n"); + } + return 0; +} - switch(argc) { - case 3 : { - //sl = stlink_quirk_open(argv[2], 0); - // FIXME - hardcoded to usb.... - sl = stlink_open_usb(10); - if(sl == NULL) return 1; - break; - } +int main(int argc, char** argv) { - case 2 : { - if (strcmp(argv[1], "--help") == 0) { - fprintf(stdout, HelpStr, NULL); - return 1; - } - } + stlink_t *sl = NULL; -#if CONFIG_USE_LIBSG - case 1 : { // Search ST-LINK (from /dev/sg0 to /dev/sg99) + st_state_t state; + memset(&state, 0, sizeof(state)); + // set defaults... + state.stlink_version = 2; + state.logging_level = 10; + state.listen_port = DEFAULT_GDB_LISTEN_PORT; + parse_options(argc, argv, &state); + switch (state.stlink_version) { + case 2: + sl = stlink_open_usb(state.logging_level); + if(sl == NULL) return 1; + break; + case 1: +#if (CONFIG_USE_LIBSG == 1) + if (strlen(state.devicename) == 0) { const int DevNumMax = 99; int ExistDevCount = 0; - for(int DevNum = 0; DevNum <= DevNumMax; DevNum++) - { - if(DevNum < 10) { + for (int DevNum = 0; DevNum <= DevNumMax; DevNum++) { + if (DevNum < 10) { char DevName[] = "/dev/sgX"; const int X_index = 7; DevName[X_index] = DevNum + '0'; - if ( !access(DevName, F_OK) ) { + if (!access(DevName, F_OK)) { sl = stlink_quirk_open(DevName, 0); ExistDevCount++; } - } - else if(DevNum < 100) { + } else if (DevNum < 100) { char DevName[] = "/dev/sgXY"; const int X_index = 7; const int Y_index = 8; - DevName[X_index] = DevNum/10 + '0'; - DevName[Y_index] = DevNum%10 + '0'; - if ( !access(DevName, F_OK) ) { + DevName[X_index] = DevNum / 10 + '0'; + DevName[Y_index] = DevNum % 10 + '0'; + if (!access(DevName, F_OK)) { sl = stlink_quirk_open(DevName, 0); ExistDevCount++; } } - if(sl != NULL) break; + if (sl != NULL) break; } - if(sl == NULL) { + if (sl == NULL) { fprintf(stdout, "\nNumber of /dev/sgX devices found: %i \n", - ExistDevCount); + ExistDevCount); fprintf(stderr, "ST-LINK not found\n"); return 1; } - break; + } else { + sl = stlink_quirk_open(state.devicename, state.logging_level); } + break; +#else + fprintf(stderr, "Support for stlink v1 disabled at build time...\n"); + fprintf(stderr, "Perhaps you're on OSX, and we haven't finished removing the libsg deps?\n"); + exit(EXIT_FAILURE); #endif - - default: { - fprintf(stderr, HelpStr, NULL); - return 1; - } } if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { @@ -200,9 +296,7 @@ int main(int argc, char** argv) { // memory map is in 1k blocks. current_memory_map = make_memory_map(params, flash_size * 0x400); - int port = 4242; - - while(serve(sl, port) == 0); + while(serve(sl, state.listen_port) == 0); /* Switch back to mass storage mode before closing. */ stlink_run(sl); From aa479e5b91a2dfd963fcc3063196bee7e159a2aa Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 15:22:24 +0000 Subject: [PATCH 0009/1435] Update netbeans project config to reflect combined makefiles --- ...ge-gdbserver.bash => Package-Default.bash} | 2 +- nbproject/Package-library_cli.bash | 75 --- nbproject/configurations.xml | 502 ++++++++++++++++-- nbproject/project.xml | 6 +- 4 files changed, 458 insertions(+), 127 deletions(-) rename nbproject/{Package-gdbserver.bash => Package-Default.bash} (98%) delete mode 100644 nbproject/Package-library_cli.bash diff --git a/nbproject/Package-gdbserver.bash b/nbproject/Package-Default.bash similarity index 98% rename from nbproject/Package-gdbserver.bash rename to nbproject/Package-Default.bash index 722b818f6..f6abfb43c 100644 --- a/nbproject/Package-gdbserver.bash +++ b/nbproject/Package-Default.bash @@ -7,7 +7,7 @@ # Macros TOP=`pwd` CND_PLATFORM=GNU-Linux-x86 -CND_CONF=gdbserver +CND_CONF=Default CND_DISTDIR=dist CND_BUILDDIR=build NBTMPDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM}/tmp-packaging diff --git a/nbproject/Package-library_cli.bash b/nbproject/Package-library_cli.bash deleted file mode 100644 index 5a644728b..000000000 --- a/nbproject/Package-library_cli.bash +++ /dev/null @@ -1,75 +0,0 @@ -#!/bin/bash -x - -# -# Generated - do not edit! -# - -# Macros -TOP=`pwd` -CND_PLATFORM=GNU-Linux-x86 -CND_CONF=library_cli -CND_DISTDIR=dist -CND_BUILDDIR=build -NBTMPDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM}/tmp-packaging -TMPDIRNAME=tmp-packaging -OUTPUT_PATH=test_usb -OUTPUT_BASENAME=test_usb -PACKAGE_TOP_DIR=stlink/ - -# Functions -function checkReturnCode -{ - rc=$? - if [ $rc != 0 ] - then - exit $rc - fi -} -function makeDirectory -# $1 directory path -# $2 permission (optional) -{ - mkdir -p "$1" - checkReturnCode - if [ "$2" != "" ] - then - chmod $2 "$1" - checkReturnCode - fi -} -function copyFileToTmpDir -# $1 from-file path -# $2 to-file path -# $3 permission -{ - cp "$1" "$2" - checkReturnCode - if [ "$3" != "" ] - then - chmod $3 "$2" - checkReturnCode - fi -} - -# Setup -cd "${TOP}" -mkdir -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package -rm -rf ${NBTMPDIR} -mkdir -p ${NBTMPDIR} - -# Copy files and create directories and links -cd "${TOP}" -makeDirectory "${NBTMPDIR}/stlink/bin" -copyFileToTmpDir "${OUTPUT_PATH}" "${NBTMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755 - - -# Generate tar file -cd "${TOP}" -rm -f ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stlink.tar -cd ${NBTMPDIR} -tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stlink.tar * -checkReturnCode - -# Cleanup -cd "${TOP}" -rm -rf ${NBTMPDIR} diff --git a/nbproject/configurations.xml b/nbproject/configurations.xml index 3d02ea831..794a3ab5c 100644 --- a/nbproject/configurations.xml +++ b/nbproject/configurations.xml @@ -2,7 +2,105 @@ + + + + + + main.c + + + main.c + startup_stm32l1xx_md.s + system_stm32l1xx.c + + + discover_board.h + main.c + stm32l_discovery_lcd.c + stm32l_discovery_lcd.h + + + + + + + stdint.h + + + core_cm3.c + core_cm3.h + + + stm32l1xx.h + system_stm32l1xx.h + + misc.h + stm32l1xx_adc.h + stm32l1xx_comp.h + stm32l1xx_crc.h + stm32l1xx_dac.h + stm32l1xx_dbgmcu.h + stm32l1xx_dma.h + stm32l1xx_exti.h + stm32l1xx_flash.h + stm32l1xx_gpio.h + stm32l1xx_i2c.h + stm32l1xx_iwdg.h + stm32l1xx_lcd.h + stm32l1xx_pwr.h + stm32l1xx_rcc.h + stm32l1xx_rtc.h + stm32l1xx_spi.h + stm32l1xx_syscfg.h + stm32l1xx_tim.h + stm32l1xx_usart.h + stm32l1xx_wwdg.h + + + misc.c + stm32l1xx_adc.c + stm32l1xx_comp.c + stm32l1xx_crc.c + stm32l1xx_dac.c + stm32l1xx_dbgmcu.c + stm32l1xx_dma.c + stm32l1xx_exti.c + stm32l1xx_flash.c + stm32l1xx_flash_ramfunc.c + stm32l1xx_gpio.c + stm32l1xx_i2c.c + stm32l1xx_iwdg.c + stm32l1xx_lcd.c + stm32l1xx_pwr.c + stm32l1xx_rcc.c + stm32l1xx_rtc.c + stm32l1xx_spi.c + stm32l1xx_syscfg.c + stm32l1xx_tim.c + stm32l1xx_usart.c + stm32l1xx_wwdg.c + + + + discover_board.h + discover_functions.c + discover_functions.h + icc_measure.c + icc_measure.h + icc_measure_Ram.c + main.c + stm32_tsl_conf.h + stm32l1xx_conf.h + stm32l1xx_it.c + stm32l1xx_it.h + stm32l_discovery_lcd.c + stm32l_discovery_lcd.h + system_stm32l1xx.c + + + main.c @@ -20,81 +118,393 @@ test_sg.c test_usb.c - + + + + stlink-hw.h + + + + + + + + + + + + + + + + + + - build/Makefile + Makefile ^(nbproject)$ . - build/Makefile + Makefile - - - LOCAL_SOURCES - default - - - - - ${MAKE} -f Makefile - ${MAKE} -f Makefile clean - test_usb - - - stm32l/src - /usr/include/libusb-1.0 - stm32l/build - src - - - CONFIG_USE_LIBUSB=1 - __GNUC_STDC_INLINE__=1 - __OPTIMIZE__=1 - __REGISTER_PREFIX__= - __STDC_VERSION__=199901L - __USER_LABEL_PREFIX__= - - - - - - + LOCAL_SOURCES default - gdbserver + . ${MAKE} -f Makefile ${MAKE} -f Makefile clean gdbserver/st-util - - stm32l/src - /usr/include/libusb-1.0 - stm32l/build - src - + CONFIG_USE_LIBSG=1 CONFIG_USE_LIBUSB=1 - __GNUC_STDC_INLINE__=1 - __OPTIMIZE__=1 - __REGISTER_PREFIX__= - __STDC_VERSION__=199901L - __USER_LABEL_PREFIX__= + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + src + + + + + + + . + + + DEBUG=1 + + + + + + + + + diff --git a/nbproject/project.xml b/nbproject/project.xml index 660863635..cd5248661 100644 --- a/nbproject/project.xml +++ b/nbproject/project.xml @@ -14,11 +14,7 @@ - library_cli - 0 - - - gdbserver + Default 0 From 85ff6038050093c1950e0ec69cd597f848bfa4c6 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 15:46:19 +0000 Subject: [PATCH 0010/1435] Make the blink example build for all platforms. Less mucking around with make parameters, it's a tiny build. Verified with a VL and L board. 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zw^XAEE2E^5!tz_40D~LbeuT##X#Twtr|= zQ}557@Kn9t?2})9Hcd-J(mFIj}x!UBnF z_^U|?=>Le1C};}=V0bMLBCW+pL{Omj)qw$j>azYG(T_2Lf`&j42GA`vgR5~~A&i2`?5Lxlv>`VllyAekSNBfx()1OMX>A%XCJ!GB^{LE+V1 z#FB9QxnhJ49X258Lq;$J=)-tJ13W<=M>IAx!V__;`+_xrAsxki|Ci#RsH1~o`XBf6 W5B76$MXi>{ sudo ./st-util --stlinkv1 [-d /dev/sg2] -# STM32L discovery kit (onboard ST-link/V2) +# STM32L or STM32F4 discovery kit (onboard ST-link/V2) $> sudo ./st-util # Full help for other options (listen port, version) diff --git a/example/blink/Makefile b/example/blink/Makefile index e5f704525..cf7221da8 100644 --- a/example/blink/Makefile +++ b/example/blink/Makefile @@ -1,35 +1,32 @@ -EXECUTABLE=blink.elf -BIN_IMAGE=blink.bin - CC=arm-none-eabi-gcc OBJCOPY=arm-none-eabi-objcopy -CFLAGS=-g -O2 -mlittle-endian -mthumb -ifeq ($(CONFIG_STM32L_DISCOVERY), 1) - CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY -else ifeq ($(CONFIG_STM32VL_DISCOVERY), 1) - CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1 -else ifeq ($(CONFIG_STM32F4_DISCOVERY), 1) - CFLAGS+=-mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1 -endif - CFLAGS+=-ffreestanding -nostdlib -nostdinc +DEF_CFLAGS=-g -O2 -mlittle-endian -mthumb -ffreestanding -nostdlib -nostdinc # to run from SRAM -CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000 +DEF_CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000 # to write to flash then run -# CFLAGS+=-Wl,-Ttext,0x08000000 -Wl,-e,0x08000000 +# DEF_CFLAGS+=-Wl,-Ttext,0x08000000 -Wl,-e,0x08000000 + +CFLAGS_VL=$(DEF_CFLAGS) -mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1 +CFLAGS_L=$(DEF_CFLAGS) -mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY +CFLAGS_F4=$(DEF_CFLAGS) -mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1 -all: $(BIN_IMAGE) +all: blink_32VL.elf blink_32L.elf blink_F4.elf -$(BIN_IMAGE): $(EXECUTABLE) +%.bin: %.elf $(OBJCOPY) -O binary $^ $@ -$(EXECUTABLE): main.c - $(CC) $(CFLAGS) $^ -o $@ +blink_32VL.elf: main.c + $(CC) $(CFLAGS_VL) $^ -o $@ +blink_32L.elf: main.c + $(CC) $(CFLAGS_L) $^ -o $@ +blink_F4.elf: main.c + $(CC) $(CFLAGS_F4) $^ -o $@ clean: - rm -rf $(EXECUTABLE) - rm -rf $(BIN_IMAGE) + rm -rf *.elf + rm -rf *.bin .PHONY: all clean diff --git a/example/blink/main.c b/example/blink/main.c index 0889b8161..e0438a0db 100644 --- a/example/blink/main.c +++ b/example/blink/main.c @@ -7,36 +7,30 @@ typedef unsigned int uint32_t; #if CONFIG_STM32VL_DISCOVERY -# define GPIOC 0x40011000 /* port C */ -# define GPIOC_CRH (GPIOC + 0x04) /* port configuration register high */ -# define GPIOC_ODR (GPIOC + 0x0c) /* port output data register */ +#define GPIOC 0x40011000 /* port C */ +#define GPIOC_CRH (GPIOC + 0x04) /* port configuration register high */ +#define LED_PORT_ODR (GPIOC + 0x0c) /* port output data register */ -# define LED_BLUE (1 << 8) /* port C, pin 8 */ -# define LED_GREEN (1 << 9) /* port C, pin 9 */ +#define LED_BLUE (1 << 8) /* port C, pin 8 */ +#define LED_GREEN (1 << 9) /* port C, pin 9 */ +#define LED_ORANGE 0 +#define LED_RED 0 static inline void setup_leds(void) { *(volatile uint32_t*)GPIOC_CRH = 0x44444411; } -static inline void switch_leds_on(void) -{ - *(volatile uint32_t*)GPIOC_ODR = LED_BLUE | LED_GREEN; -} - -static inline void switch_leds_off(void) -{ - *(volatile uint32_t*)GPIOC_ODR = 0; -} - #elif CONFIG_STM32L_DISCOVERY -# define GPIOB 0x40020400 /* port B */ -# define GPIOB_MODER (GPIOB + 0x00) /* port mode register */ -# define GPIOB_ODR (GPIOB + 0x14) /* port output data register */ +#define GPIOB 0x40020400 /* port B */ +#define GPIOB_MODER (GPIOB + 0x00) /* port mode register */ +#define LED_PORT_ODR (GPIOB + 0x14) /* port output data register */ -# define LED_BLUE (1 << 6) /* port B, pin 6 */ -# define LED_GREEN (1 << 7) /* port B, pin 7 */ +#define LED_BLUE (1 << 6) /* port B, pin 6 */ +#define LED_GREEN (1 << 7) /* port B, pin 7 */ +#define LED_ORANGE 0 +#define LED_RED 0 static inline void setup_leds(void) { @@ -44,26 +38,16 @@ static inline void setup_leds(void) *(volatile uint32_t*)GPIOB_MODER |= (1 << (7 * 2)) | (1 << (6 * 2)); } -static inline void switch_leds_on(void) -{ - *(volatile uint32_t*)GPIOB_ODR = LED_BLUE | LED_GREEN; -} - -static inline void switch_leds_off(void) -{ - *(volatile uint32_t*)GPIOB_ODR = 0; -} - #elif CONFIG_STM32F4_DISCOVERY #define GPIOD 0x40020C00 /* port D */ -# define GPIOD_MODER (GPIOD + 0x00) /* port mode register */ -# define GPIOD_ODR (GPIOD + 0x14) /* port output data register */ +#define GPIOD_MODER (GPIOD + 0x00) /* port mode register */ +#define LED_PORT_ODR (GPIOD + 0x14) /* port output data register */ -# define LED_GREEN (1 << 12) /* port B, pin 12 */ -# define LED_ORANGE (1 << 13) /* port B, pin 13 */ -# define LED_RED (1 << 14) /* port B, pin 14 */ -# define LED_BLUE (1 << 15) /* port B, pin 15 */ +#define LED_GREEN (1 << 12) /* port D, pin 12 */ +#define LED_ORANGE (1 << 13) /* port D, pin 13 */ +#define LED_RED (1 << 14) /* port D, pin 14 */ +#define LED_BLUE (1 << 15) /* port D, pin 15 */ static inline void setup_leds(void) { @@ -71,22 +55,20 @@ static inline void setup_leds(void) (1 << (13 * 2)) | (1 << (14 * 2)) | (1 << (15 * 2)); } +#else +#error "Architecture must be defined!" +#endif /* otherwise, error */ static inline void switch_leds_on(void) { - *(volatile uint32_t*)GPIOD_ODR = LED_GREEN | LED_ORANGE | LED_RED | LED_BLUE; + *(volatile uint32_t*)LED_PORT_ODR = LED_BLUE | LED_GREEN | LED_ORANGE | LED_RED; } static inline void switch_leds_off(void) { - *(volatile uint32_t*)GPIOD_ODR = 0; + *(volatile uint32_t*)LED_PORT_ODR = 0; } -#else -#error "Architecture must be defined!" -#endif /* otherwise, error */ - - #define delay() \ do { \ register unsigned int i; \ diff --git a/example/blink/o.bin b/example/blink/o.bin deleted file mode 100755 index 76324f796a6523d1acb35940d4d351466dd7773e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 64 zcmZ?##KP?INzm!YCr0KYpIn?AKk+b1B>;Jh{$CslTs}D{b0i%2#LvvIpV9iyMIc{^ P8^mV<@~!?{eD@pxMXwtU From c37975c15730ac582945ea3ed85ac59284979819 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 15:53:03 +0000 Subject: [PATCH 0011/1435] remove swallowing of ctrl-c No idea why this was added, but it's not necessary for anything I've found. --- gdbserver/gdb-server.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 30ee01483..e7efbf15b 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -32,12 +32,6 @@ #define FLASH_PAGE_MASK (~((1 << 10) - 1)) #define FLASH_SIZE (FLASH_PAGE * 128) -volatile int do_exit = 0; -void ctrl_c(int sig) -{ - do_exit = 1; -} - static const char hex[] = "0123456789abcdef"; static const char* current_memory_map = NULL; @@ -697,7 +691,6 @@ int serve(stlink_t *sl, int port) { printf("Listening at *:%d...\n", port); - (void) signal (SIGINT, ctrl_c); int client = accept(sock, NULL, NULL); signal (SIGINT, SIG_DFL); if(client < 0) { From 076f1086fa9c0dfa043300fb1776bc10e8eaa77f Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 18:05:24 +0000 Subject: [PATCH 0012/1435] Remove all #ifdefs for sg-utils. We're starting on integration from github.com/afaerber So, instead of scanning all the usb devices, just open what we want. --- Makefile | 25 +++++------------------ flash/main.c | 5 ----- gdbserver/gdb-server.c | 6 ------ src/stlink-usb.c | 45 ++++++------------------------------------ src/stlink-usb.h | 6 ------ src/test_sg.c | 4 ---- 6 files changed, 11 insertions(+), 80 deletions(-) diff --git a/Makefile b/Makefile index c5bb1d9a1..bbd76a807 100644 --- a/Makefile +++ b/Makefile @@ -1,28 +1,13 @@ -# make ... for both libusb and libsg -# -# make CONFIG_USE_LIBSG=0 ... -# for just libusb -# +# make ... for both stlink v1 and stlink v2 support +## VPATH=src -SOURCES_LIB=stlink-common.c stlink-usb.c +SOURCES_LIB=stlink-common.c stlink-usb.c #stlink-sg.c OBJS_LIB=$(SOURCES_LIB:.c=.o) -TEST_PROGRAMS=test_usb +TEST_PROGRAMS=test_usb #test_sg LDFLAGS=-lusb-1.0 -L. -lstlink -ifeq ($(CONFIG_USE_LIBSG),) -CONFIG_USE_LIBSG=1 -endif - -ifneq ($(CONFIG_USE_LIBSG),0) -SOURCES_LIB+=stlink-sg.c -CFLAGS+=-DCONFIG_USE_LIBSG=1 -LDFLAGS+=-lsgutils2 -TEST_PROGRAMS+=test_sg -endif - CFLAGS+=-g -CFLAGS+=-DCONFIG_USE_LIBUSB=1 CFLAGS+=-DDEBUG=1 CFLAGS+=-std=gnu99 CFLAGS+=-Wall -Wextra @@ -63,7 +48,7 @@ distclean: clean $(MAKE) -C gdbserver clean flash: - $(MAKE) -C flash CONFIG_USE_LIBSG="$(CONFIG_USE_LIBSG)" + $(MAKE) -C flash gdbserver: $(MAKE) -C gdbserver diff --git a/flash/main.c b/flash/main.c index e47417437..a443f95f6 100644 --- a/flash/main.c +++ b/flash/main.c @@ -86,14 +86,9 @@ int main(int ac, char** av) if (o.devname != NULL) /* stlinkv1 */ { -#if CONFIG_USE_LIBSG static const int scsi_verbose = 2; sl = stlink_quirk_open(o.devname, scsi_verbose); if (sl == NULL) goto on_error; -#else - printf("not compiled for use with STLink/V1"); - goto on_error; -#endif } else /* stlinkv2 */ { diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index e7efbf15b..f1da63e45 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -197,7 +197,6 @@ int main(int argc, char** argv) { if(sl == NULL) return 1; break; case 1: -#if (CONFIG_USE_LIBSG == 1) if (strlen(state.devicename) == 0) { const int DevNumMax = 99; int ExistDevCount = 0; @@ -235,11 +234,6 @@ int main(int argc, char** argv) { sl = stlink_quirk_open(state.devicename, state.logging_level); } break; -#else - fprintf(stderr, "Support for stlink v1 disabled at build time...\n"); - fprintf(stderr, "Perhaps you're on OSX, and we haven't finished removing the libsg deps?\n"); - exit(EXIT_FAILURE); -#endif } if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { diff --git a/src/stlink-usb.c b/src/stlink-usb.c index ff9ef71de..57a4a2fdd 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -604,47 +604,14 @@ stlink_t* stlink_open_usb(const int verbose) { goto on_error; } - count = libusb_get_device_list(slu->libusb_ctx, &devs); - if (count < 0) { - printf("libusb_get_device_list\n"); - goto on_libusb_error; - } - - for (i = 0; i < count; ++i) { - dev = devs[i]; - slu->protocoll = is_stlink_device(dev, 0); - if (slu->protocoll > 0) break; - } - if (i == count) goto on_libusb_error; - - if (libusb_open(dev, &(slu->usb_handle))) { - printf("libusb_open()\n"); - goto on_libusb_error; + slu->usb_handle = libusb_open_device_with_vid_pid(slu->libusb_ctx, USB_ST_VID, USB_STLINK_32L_PID); + if (slu->usb_handle == NULL) { + // TODO - free usb context too... + free(slu); + fprintf(stderr, "Couldn't find any ST-Link/V2 devices"); + return NULL; } - if (iSerial) { - unsigned char serial[256]; - struct libusb_device_descriptor desc; - int r; - - r = libusb_get_device_descriptor(dev, &desc); - if (r<0) { - printf("Can't get descriptor to match Iserial\n"); - goto on_libusb_error; - } - r = libusb_get_string_descriptor_ascii - (slu->usb_handle, desc.iSerialNumber, serial, 256); - if (r<0) { - printf("Can't get Serialnumber to match Iserial\n"); - goto on_libusb_error; - } - if (strcmp((char*)serial, iSerial)) { - printf("Mismatch in serial numbers, dev %s vs given %s\n", - serial, iSerial); - goto on_libusb_error; - } - } - if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { int r; diff --git a/src/stlink-usb.h b/src/stlink-usb.h index c632a8c41..2f3b8cc3e 100644 --- a/src/stlink-usb.h +++ b/src/stlink-usb.h @@ -18,7 +18,6 @@ extern "C" { #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 -#if defined(CONFIG_USE_LIBUSB) struct stlink_libusb { libusb_context* libusb_ctx; libusb_device_handle* usb_handle; @@ -30,11 +29,6 @@ extern "C" { unsigned int sg_transfer_idx; unsigned int cmd_len; }; -#else -#error "it's all bad!" - struct stlink_libusb {}; -#endif - stlink_t* stlink_open_usb(const int verbose); diff --git a/src/test_sg.c b/src/test_sg.c index 34fbe540c..9efe6d80d 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -6,10 +6,6 @@ #include #include -#if CONFIG_USE_LIBSG -#include -#include -#endif #include "stlink-common.h" int main(int argc, char *argv[]) { From 42d2da531f52ead18091a1211a5e6206e27dc178 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 19:09:31 +0000 Subject: [PATCH 0013/1435] flag out the only scsi specific code Also flag out some places where code appears unused. --- Makefile | 2 +- flash/main.c | 4 +++- gdbserver/gdb-server.c | 6 +++--- src/stlink-sg.c | 13 +++++++------ src/stlink-sg.h | 6 +----- src/stlink-usb.c | 7 ++++++- src/test_sg.c | 2 +- 7 files changed, 22 insertions(+), 18 deletions(-) diff --git a/Makefile b/Makefile index bbd76a807..2c73f165f 100644 --- a/Makefile +++ b/Makefile @@ -2,7 +2,7 @@ ## VPATH=src -SOURCES_LIB=stlink-common.c stlink-usb.c #stlink-sg.c +SOURCES_LIB=stlink-common.c stlink-usb.c stlink-sg.c OBJS_LIB=$(SOURCES_LIB:.c=.o) TEST_PROGRAMS=test_usb #test_sg LDFLAGS=-lusb-1.0 -L. -lstlink diff --git a/flash/main.c b/flash/main.c index a443f95f6..a74525a5a 100644 --- a/flash/main.c +++ b/flash/main.c @@ -1,5 +1,7 @@ /* simple wrapper around the stlink_flash_write function */ +// TODO - this should be done as just a simple flag to the st-util command line... + #include #include @@ -87,7 +89,7 @@ int main(int ac, char** av) if (o.devname != NULL) /* stlinkv1 */ { static const int scsi_verbose = 2; - sl = stlink_quirk_open(o.devname, scsi_verbose); + sl = stlink_v1_open(o.devname, scsi_verbose); if (sl == NULL) goto on_error; } else /* stlinkv2 */ diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index f1da63e45..3e2f99a96 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -207,7 +207,7 @@ int main(int argc, char** argv) { const int X_index = 7; DevName[X_index] = DevNum + '0'; if (!access(DevName, F_OK)) { - sl = stlink_quirk_open(DevName, 0); + sl = stlink_v1_open(DevName, 0); ExistDevCount++; } } else if (DevNum < 100) { @@ -217,7 +217,7 @@ int main(int argc, char** argv) { DevName[X_index] = DevNum / 10 + '0'; DevName[Y_index] = DevNum % 10 + '0'; if (!access(DevName, F_OK)) { - sl = stlink_quirk_open(DevName, 0); + sl = stlink_v1_open(DevName, 0); ExistDevCount++; } } @@ -231,7 +231,7 @@ int main(int argc, char** argv) { return 1; } } else { - sl = stlink_quirk_open(state.devicename, state.logging_level); + sl = stlink_v1_open(state.devicename, state.logging_level); } break; } diff --git a/src/stlink-sg.c b/src/stlink-sg.c index b8220de13..137f6f605 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -82,12 +82,7 @@ #include "stlink-common.h" -#if CONFIG_USE_LIBSG -// sgutils2 (apt-get install libsgutils2-dev) -#include -#include #include "stlink-sg.h" -#endif // Suspends execution of the calling process for @@ -119,15 +114,18 @@ static void clear_buf(stlink_t *sl) { void _stlink_sg_close(stlink_t *sl) { if (sl) { +#if FINISHED_WITH_SG struct stlink_libsg *slsg = sl->backend_data; scsi_pt_close_device(slsg->sg_fd); free(slsg); +#endif } } //TODO rewrite/cleanup, save the error in sl +#if FINISHED_WITH_SG static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { struct stlink_libsg *sl = stl->backend_data; const int e = sl->do_scsi_pt_err; @@ -209,8 +207,10 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { "category (%d)\n", cat); } } +#endif void stlink_q(stlink_t *sl) { +#if FINISHED_WITH_SG struct stlink_libsg* sg = sl->backend_data; DD(sl, "CDB["); for (int i = 0; i < CDB_SL; i++) @@ -245,6 +245,7 @@ void stlink_q(stlink_t *sl) { stlink_confirm_inq(sl, ptvp); // TODO recycle: clear_scsi_pt_obj(struct sg_pt_base * objp); destruct_scsi_pt_obj(ptvp); +#endif } // TODO thinking, cleanup @@ -803,7 +804,7 @@ stlink_t* stlink_open(const char *dev_name, const int verbose) { -stlink_t* stlink_quirk_open(const char *dev_name, const int verbose) { +stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { stlink_t *sl = stlink_open(dev_name, verbose); if (sl == NULL) { diff --git a/src/stlink-sg.h b/src/stlink-sg.h index 523b7d883..afa47c51a 100644 --- a/src/stlink-sg.h +++ b/src/stlink-sg.h @@ -40,7 +40,6 @@ extern "C" { -#if defined(CONFIG_USE_LIBUSB) struct stlink_libsg { int sg_fd; int do_scsi_pt_err; @@ -63,11 +62,8 @@ extern "C" { reg reg; }; -#else - struct stlink_libsg {}; -#endif - stlink_t* stlink_quirk_open(const char *dev_name, const int verbose); + stlink_t* stlink_v1_open(const char *dev_name, const int verbose); #ifdef __cplusplus } diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 57a4a2fdd..526996144 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -116,7 +116,10 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, if (submit_wait(handle, handle->rep_trans)) return -1; res = handle->rep_trans->actual_length; } + if ((handle->protocoll == 1) && terminate) { + fprintf(stderr, "This is never used....\n"); + exit(EXIT_FAILURE); /* Read the SG reply */ unsigned char sg_buf[13]; libusb_fill_bulk_transfer @@ -172,6 +175,7 @@ static int fill_command int i = 0; memset(cmd, 0, sizeof (sl->c_buf)); if(slu->protocoll == 1) { + fprintf(stderr, "This is never used....\n"); cmd[i++] = 'U'; cmd[i++] = 'S'; cmd[i++] = 'B'; @@ -652,11 +656,12 @@ stlink_t* stlink_open_usb(const int verbose) { printf("libusb_alloc_transfer\n"); goto on_libusb_error; } - + // TODO - could use the scanning techniq from stm8 code here... slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; slu->sg_transfer_idx = 0; + // TODO - never used at the moment, always CMD_SIZE slu->cmd_len = (slu->protocoll == 1)? STLINK_SG_SIZE: STLINK_CMD_SIZE; /* success */ diff --git a/src/test_sg.c b/src/test_sg.c index 9efe6d80d..a12ed1f40 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -37,7 +37,7 @@ int main(int argc, char *argv[]) { fprintf(stderr, "Using sg_lib %s : scsi_pt %s\n", sg_lib_version(), scsi_pt_version()); - stlink_t *sl = stlink_quirk_open(dev_name, scsi_verbose); + stlink_t *sl = stlink_v1_open(dev_name, scsi_verbose); if (sl == NULL) return EXIT_FAILURE; From d7e37a684a3ae0c9e52e0486fe46f6d3af1c2b1d Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 22 Oct 2011 20:31:11 +0000 Subject: [PATCH 0014/1435] Replace all logging I needed some sanity... --- Makefile | 2 +- flash/main.c | 2 +- gdbserver/gdb-server.c | 19 +++++----- src/stlink-common.c | 84 +++++++++++++++++++----------------------- src/stlink-common.h | 4 -- src/stlink-sg.c | 75 +++++++++++++++++++------------------ src/stlink-usb.c | 46 ++++++++++++++--------- src/uglylogging.c | 58 +++++++++++++++++++++++++++++ src/uglylogging.h | 27 ++++++++++++++ 9 files changed, 202 insertions(+), 115 deletions(-) create mode 100644 src/uglylogging.c create mode 100644 src/uglylogging.h diff --git a/Makefile b/Makefile index 2c73f165f..c3c345a69 100644 --- a/Makefile +++ b/Makefile @@ -2,7 +2,7 @@ ## VPATH=src -SOURCES_LIB=stlink-common.c stlink-usb.c stlink-sg.c +SOURCES_LIB=stlink-common.c stlink-usb.c stlink-sg.c uglylogging.c OBJS_LIB=$(SOURCES_LIB:.c=.o) TEST_PROGRAMS=test_usb #test_sg LDFLAGS=-lusb-1.0 -L. -lstlink diff --git a/flash/main.c b/flash/main.c index a74525a5a..849b5d6cd 100644 --- a/flash/main.c +++ b/flash/main.c @@ -94,7 +94,7 @@ int main(int ac, char** av) } else /* stlinkv2 */ { - sl = stlink_open_usb(10); + sl = stlink_open_usb(100); if (sl == NULL) goto on_error; } diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 3e2f99a96..3af0d8a90 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -21,7 +21,7 @@ #include "gdb-remote.h" -#define DEFAULT_LOGGING_LEVEL 10 +#define DEFAULT_LOGGING_LEVEL 100 #define DEFAULT_GDB_LISTEN_PORT 4242 #define STRINGIFY_inner(name) #name @@ -188,7 +188,7 @@ int main(int argc, char** argv) { memset(&state, 0, sizeof(state)); // set defaults... state.stlink_version = 2; - state.logging_level = 10; + state.logging_level = DEFAULT_LOGGING_LEVEL; state.listen_port = DEFAULT_GDB_LISTEN_PORT; parse_options(argc, argv, &state); switch (state.stlink_version) { @@ -234,15 +234,14 @@ int main(int argc, char** argv) { sl = stlink_v1_open(state.devicename, state.logging_level); } break; - } - - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { - stlink_exit_dfu_mode(sl); - } + } - if(stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { - stlink_enter_swd_mode(sl); - } + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { + stlink_exit_dfu_mode(sl); + } + stlink_enter_swd_mode(sl); + } uint32_t chip_id = stlink_chip_id(sl); uint32_t core_id = stlink_core_id(sl); diff --git a/src/stlink-common.c b/src/stlink-common.c index 707316cc9..2693eb921 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -13,21 +13,13 @@ #include "stlink-common.h" +#include "uglylogging.h" -void D(stlink_t *sl, char *txt) { - if (sl->verbose > 1) - fputs(txt, stderr); -} - -void DD(stlink_t *sl, char *format, ...) { - if (sl->verbose > 0) { - va_list list; - va_start(list, format); - vfprintf(stderr, format, list); - va_end(list); - } -} - +#define LOG_TAG __FILE__ +#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) +#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) +#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) +#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) /* FPEC flash controller interface, pm0063 manual @@ -256,38 +248,38 @@ static void disable_flash_read_protection(stlink_t *sl) { // Delegates to the backends... void stlink_close(stlink_t *sl) { - D(sl, "\n*** stlink_close ***\n"); + DLOG("*** stlink_close ***\n"); sl->backend->close(sl); free(sl); } void stlink_exit_debug_mode(stlink_t *sl) { - D(sl, "\n*** stlink_exit_debug_mode ***\n"); + DLOG("*** stlink_exit_debug_mode ***\n"); sl->backend->exit_debug_mode(sl); } void stlink_enter_swd_mode(stlink_t *sl) { - D(sl, "\n*** stlink_enter_swd_mode ***\n"); + DLOG("*** stlink_enter_swd_mode ***\n"); sl->backend->enter_swd_mode(sl); } // Force the core into the debug mode -> halted state. void stlink_force_debug(stlink_t *sl) { - D(sl, "\n*** stlink_force_debug_mode ***\n"); + DLOG("*** stlink_force_debug_mode ***\n"); sl->backend->force_debug(sl); } void stlink_exit_dfu_mode(stlink_t *sl) { - D(sl, "\n*** stlink_exit_dfu_mode ***\n"); + DLOG("*** stlink_exit_dfu_mode ***\n"); sl->backend->exit_dfu_mode(sl); } uint32_t stlink_core_id(stlink_t *sl) { - D(sl, "\n*** stlink_core_id ***\n"); + DLOG("*** stlink_core_id ***\n"); sl->backend->core_id(sl); if (sl->verbose > 2) stlink_print_data(sl); - DD(sl, "core_id = 0x%08x\n", sl->core_id); + DLOG("core_id = 0x%08x\n", sl->core_id); return sl->core_id; } @@ -314,17 +306,17 @@ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { } void stlink_reset(stlink_t *sl) { - D(sl, "\n*** stlink_reset ***\n"); + DLOG("*** stlink_reset ***\n"); sl->backend->reset(sl); } void stlink_run(stlink_t *sl) { - D(sl, "\n*** stlink_run ***\n"); + DLOG("*** stlink_run ***\n"); sl->backend->run(sl); } void stlink_status(stlink_t *sl) { - D(sl, "\n*** stlink_status ***\n"); + DLOG("*** stlink_status ***\n"); sl->backend->status(sl); stlink_core_stat(sl); } @@ -355,26 +347,26 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { } void stlink_version(stlink_t *sl) { - D(sl, "*** looking up stlink version\n"); + DLOG("*** looking up stlink version\n"); stlink_version_t slv; sl->backend->version(sl); _parse_version(sl, &slv); - DD(sl, "st vid = 0x%04x (expect 0x%04x)\n", slv.st_vid, USB_ST_VID); - DD(sl, "stlink pid = 0x%04x\n", slv.stlink_pid); - DD(sl, "stlink version = 0x%x\n", slv.stlink_v); - DD(sl, "jtag version = 0x%x\n", slv.jtag_v); - DD(sl, "swim version = 0x%x\n", slv.swim_v); + DLOG("st vid = 0x%04x (expect 0x%04x)\n", slv.st_vid, USB_ST_VID); + DLOG("stlink pid = 0x%04x\n", slv.stlink_pid); + DLOG("stlink version = 0x%x\n", slv.stlink_v); + DLOG("jtag version = 0x%x\n", slv.jtag_v); + DLOG("swim version = 0x%x\n", slv.swim_v); if (slv.jtag_v == 0) { - DD(sl, " notice: the firmware doesn't support a jtag/swd interface\n"); + DLOG(" notice: the firmware doesn't support a jtag/swd interface\n"); } if (slv.swim_v == 0) { - DD(sl, " notice: the firmware doesn't support a swim interface\n"); + DLOG(" notice: the firmware doesn't support a swim interface\n"); } } void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - D(sl, "\n*** stlink_write_mem32 ***\n"); + DLOG("*** stlink_write_mem32 ***\n"); if (len % 4 != 0) { fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); return; @@ -383,7 +375,7 @@ void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { } void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - D(sl, "\n*** stlink_read_mem32 ***\n"); + DLOG("*** stlink_read_mem32 ***\n"); if (len % 4 != 0) { // !!! never ever: fw gives just wrong values fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); @@ -393,23 +385,23 @@ void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { } void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { - D(sl, "\n*** stlink_write_mem8 ***\n"); + DLOG("*** stlink_write_mem8 ***\n"); sl->backend->write_mem8(sl, addr, len); } void stlink_read_all_regs(stlink_t *sl, reg *regp) { - D(sl, "\n*** stlink_read_all_regs ***\n"); + DLOG("*** stlink_read_all_regs ***\n"); sl->backend->read_all_regs(sl, regp); } void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { - D(sl, "\n*** stlink_write_reg\n"); + DLOG("*** stlink_write_reg\n"); sl->backend->write_reg(sl, reg, idx); } void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) { - D(sl, "\n*** stlink_read_reg\n"); - DD(sl, " (%d) ***\n", r_idx); + DLOG("*** stlink_read_reg\n"); + DLOG(" (%d) ***\n", r_idx); if (r_idx > 20 || r_idx < 0) { fprintf(stderr, "Error: register index must be in [0..20]\n"); @@ -426,7 +418,7 @@ unsigned int is_core_halted(stlink_t *sl) { } void stlink_step(stlink_t *sl) { - D(sl, "\n*** stlink_step ***\n"); + DLOG("*** stlink_step ***\n"); sl->backend->step(sl); } @@ -434,16 +426,16 @@ int stlink_current_mode(stlink_t *sl) { int mode = sl->backend->current_mode(sl); switch (mode) { case STLINK_DEV_DFU_MODE: - DD(sl, "stlink current mode: dfu\n"); + DLOG("stlink current mode: dfu\n"); return mode; case STLINK_DEV_DEBUG_MODE: - DD(sl, "stlink current mode: debug (jtag or swd)\n"); + DLOG("stlink current mode: debug (jtag or swd)\n"); return mode; case STLINK_DEV_MASS_MODE: - DD(sl, "stlink current mode: mass\n"); + DLOG("stlink current mode: mass\n"); return mode; } - DD(sl, "stlink mode: unknown!\n"); + DLOG("stlink mode: unknown!\n"); return STLINK_DEV_UNKNOWN_MODE; } @@ -496,11 +488,11 @@ void stlink_core_stat(stlink_t *sl) { switch (sl->q_buf[0]) { case STLINK_CORE_RUNNING: sl->core_stat = STLINK_CORE_RUNNING; - DD(sl, " core status: running\n"); + DLOG(" core status: running\n"); return; case STLINK_CORE_HALTED: sl->core_stat = STLINK_CORE_HALTED; - DD(sl, " core status: halted\n"); + DLOG(" core status: halted\n"); return; default: sl->core_stat = STLINK_CORE_STAT_UNKNOWN; diff --git a/src/stlink-common.h b/src/stlink-common.h index 9481609f6..49867138c 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -181,10 +181,6 @@ extern "C" { }; - // some quick and dirty logging... - void D(stlink_t *sl, char *txt); - void DD(stlink_t *sl, char *format, ...); - //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose); // delegated functions... diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 137f6f605..afce5aca4 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -81,9 +81,14 @@ #include #include "stlink-common.h" - #include "stlink-sg.h" +#include "uglylogging.h" +#define LOG_TAG __FILE__ +#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) +#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) +#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) +#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) // Suspends execution of the calling process for // (at least) ms milliseconds. @@ -104,7 +109,7 @@ static void clear_cdb(struct stlink_libsg *sl) { // E.g. make the valgrind happy. static void clear_buf(stlink_t *sl) { - DD(sl, "*** clear_buf ***\n"); + DLOG("*** clear_buf ***\n"); for (size_t i = 0; i < sizeof (sl->q_buf); i++) sl->q_buf[i] = 0; @@ -142,7 +147,7 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { } const int duration = get_scsi_pt_duration_ms(ptvp); if ((stl->verbose > 1) && (duration >= 0)) - DD(stl, " duration=%d ms\n", duration); + DLOG(" duration=%d ms\n", duration); // XXX stlink fw sends broken residue, so ignore it and use the known q_len // "usb-storage quirks=483:3744:r" @@ -159,7 +164,7 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { switch (cat) { case SCSI_PT_RESULT_GOOD: if (stl->verbose && (resid > 0)) - DD(stl, " notice: requested %d bytes but " + DLOG(" notice: requested %d bytes but " "got %d bytes, ignore [broken] residue = %d\n", stl->q_len, dsize, resid); break; @@ -168,7 +173,7 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { sg_get_scsi_status_str( get_scsi_pt_status_response(ptvp), sizeof (buf), buf); - DD(stl, " scsi status: %s\n", buf); + DLOG(" scsi status: %s\n", buf); } return; case SCSI_PT_RESULT_SENSE: @@ -176,11 +181,11 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { if (stl->verbose) { sg_get_sense_str("", sl->sense_buf, slen, (stl->verbose > 1), sizeof (buf), buf); - DD(stl, "%s", buf); + DLOG("%s", buf); } if (stl->verbose && (resid > 0)) { if ((stl->verbose) || (stl->q_len > 0)) - DD(stl, " requested %d bytes but " + DLOG(" requested %d bytes but " "got %d bytes\n", stl->q_len, dsize); } return; @@ -193,13 +198,13 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { // The 'host_status' field has the following values: // [0x07] Internal error detected in the host adapter. // This may not be fatal (and the command may have succeeded). - DD(stl, " transport: %s", buf); + DLOG(" transport: %s", buf); } return; case SCSI_PT_RESULT_OS_ERR: if (stl->verbose) { get_scsi_pt_os_err_str(ptvp, sizeof (buf), buf); - DD(stl, " os: %s", buf); + DLOG(" os: %s", buf); } return; default: @@ -212,10 +217,10 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { void stlink_q(stlink_t *sl) { #if FINISHED_WITH_SG struct stlink_libsg* sg = sl->backend_data; - DD(sl, "CDB["); + DLOG("CDB["); for (int i = 0; i < CDB_SL; i++) - DD(sl, " 0x%02x", (unsigned int) sg->cdb_cmd_blk[i]); - DD(sl, "]\n"); + DLOG(" 0x%02x", (unsigned int) sg->cdb_cmd_blk[i]); + DLOG("]\n"); // Get control command descriptor of scsi structure, // (one object per command!!) @@ -258,13 +263,13 @@ void stlink_stat(stlink_t *stl, char *txt) { switch (stl->q_buf[0]) { case STLINK_OK: - DD(stl, " %s: ok\n", txt); + DLOG(" %s: ok\n", txt); return; case STLINK_FALSE: - DD(stl, " %s: false\n", txt); + DLOG(" %s: false\n", txt); return; default: - DD(stl, " %s: unknown\n", txt); + DLOG(" %s: unknown\n", txt); } } @@ -300,7 +305,7 @@ static void parse_version(stlink_t *stl) { void _stlink_sg_version(stlink_t *stl) { struct stlink_libsg *sl = stl->backend_data; - D(stl, "\n*** stlink_version ***\n"); + DLOG("\n*** stlink_version ***\n"); clear_cdb(sl); sl->cdb_cmd_blk[0] = STLINK_GET_VERSION; stl->q_len = 6; @@ -339,7 +344,7 @@ void _stlink_sg_enter_swd_mode(stlink_t *sl) { void _stlink_sg_enter_jtag_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - D(sl, "\n*** stlink_enter_jtag_mode ***\n"); + DLOG("\n*** stlink_enter_jtag_mode ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_ENTER; sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_JTAG; @@ -351,7 +356,7 @@ void _stlink_sg_enter_jtag_mode(stlink_t *sl) { void _stlink_sg_exit_dfu_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - D(sl, "\n*** stlink_exit_dfu_mode ***\n"); + DLOG("\n*** stlink_exit_dfu_mode ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[0] = STLINK_DFU_COMMAND; sg->cdb_cmd_blk[1] = STLINK_DFU_EXIT; @@ -428,7 +433,7 @@ void _stlink_sg_reset(stlink_t *sl) { void _stlink_sg_status(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - D(sl, "\n*** stlink_status ***\n"); + DLOG("\n*** stlink_status ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_GETSTATUS; sl->q_len = 2; @@ -440,7 +445,7 @@ void _stlink_sg_status(stlink_t *sl) { void _stlink_sg_force_debug(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - D(sl, "\n*** stlink_force_debug ***\n"); + DLOG("\n*** stlink_force_debug ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_FORCEDEBUG; sl->q_len = 2; @@ -471,7 +476,7 @@ void _stlink_sg_read_all_regs(stlink_t *sl, reg *regp) { for (int i = 0; i < 16; i++) { sg->reg.r[i] = read_uint32(sl->q_buf, 4 * i); if (sl->verbose > 1) - DD(sl, "r%2d = 0x%08x\n", i, sg->reg.r[i]); + DLOG("r%2d = 0x%08x\n", i, sg->reg.r[i]); } sg->reg.xpsr = read_uint32(sl->q_buf, 64); sg->reg.main_sp = read_uint32(sl->q_buf, 68); @@ -481,11 +486,11 @@ void _stlink_sg_read_all_regs(stlink_t *sl, reg *regp) { if (sl->verbose < 2) return; - DD(sl, "xpsr = 0x%08x\n", sg->reg.xpsr); - DD(sl, "main_sp = 0x%08x\n", sg->reg.main_sp); - DD(sl, "process_sp = 0x%08x\n", sg->reg.process_sp); - DD(sl, "rw = 0x%08x\n", sg->reg.rw); - DD(sl, "rw2 = 0x%08x\n", sg->reg.rw2); + DLOG("xpsr = 0x%08x\n", sg->reg.xpsr); + DLOG("main_sp = 0x%08x\n", sg->reg.main_sp); + DLOG("process_sp = 0x%08x\n", sg->reg.process_sp); + DLOG("rw = 0x%08x\n", sg->reg.rw); + DLOG("rw2 = 0x%08x\n", sg->reg.rw2); } // Read an arm-core register, the index must be in the range 0..20. @@ -506,7 +511,7 @@ void _stlink_sg_read_reg(stlink_t *sl, int r_idx, reg *regp) { stlink_print_data(sl); uint32_t r = read_uint32(sl->q_buf, 0); - DD(sl, "r_idx (%2d) = 0x%08x\n", r_idx, r); + DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); switch (r_idx) { case 16: @@ -553,7 +558,7 @@ void _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int idx) { void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { struct stlink_libsg *sg = sl->backend_data; - D(sl, "\n*** stlink_write_dreg ***\n"); + DLOG("\n*** stlink_write_dreg ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_WRITEDEBUGREG; // 2-5: address of reg of the debug module @@ -570,7 +575,7 @@ void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { void _stlink_sg_run(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - D(sl, "\n*** stlink_run ***\n"); + DLOG("\n*** stlink_run ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_RUNCORE; sl->q_len = 2; @@ -595,7 +600,7 @@ void _stlink_sg_step(stlink_t *sl) { // see Cortex-M3 Technical Reference Manual // TODO make delegate! void stlink_set_hw_bp(stlink_t *sl, int fp_nr, uint32_t addr, int fp) { - D(sl, "\n*** stlink_set_hw_bp ***\n"); + DLOG("\n*** stlink_set_hw_bp ***\n"); struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_SETFP; @@ -616,7 +621,7 @@ void stlink_set_hw_bp(stlink_t *sl, int fp_nr, uint32_t addr, int fp) { // TODO make delegate! void stlink_clr_hw_bp(stlink_t *sl, int fp_nr) { struct stlink_libsg *sg = sl->backend_data; - D(sl, "\n*** stlink_clr_hw_bp ***\n"); + DLOG("\n*** stlink_clr_hw_bp ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_CLEARFP; sg->cdb_cmd_blk[2] = fp_nr; @@ -805,7 +810,7 @@ stlink_t* stlink_open(const char *dev_name, const int verbose) { stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { - + ugly_init(verbose); stlink_t *sl = stlink_open(dev_name, verbose); if (sl == NULL) { fputs("Error: could not open stlink device\n", stderr); @@ -825,7 +830,7 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { return NULL; } - D(sl, "\n*** stlink_force_open ***\n"); + DLOG("\n*** stlink_force_open ***\n"); switch (stlink_current_mode(sl)) { case STLINK_DEV_MASS_MODE: return sl; @@ -833,10 +838,10 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { // TODO go to mass? return sl; } - DD(sl, "\n*** switch the stlink to mass mode ***\n"); + DLOG("\n*** switch the stlink to mass mode ***\n"); _stlink_sg_exit_dfu_mode(sl); // exit the dfu mode -> the device is gone - DD(sl, "\n*** reopen the stlink device ***\n"); + DLOG("\n*** reopen the stlink device ***\n"); delay(1000); stlink_close(sl); delay(5000); diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 526996144..c0b0009f2 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -5,8 +5,17 @@ #include #include #include + #include "stlink-common.h" #include "stlink-usb.h" +#include "uglylogging.h" + +#define LOG_TAG __FILE__ +#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) +#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) +#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) +#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) + enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; @@ -472,11 +481,11 @@ void _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) { if (sl->verbose < 2) return; - DD(sl, "xpsr = 0x%08x\n", read_uint32(sl->q_buf, 64)); - DD(sl, "main_sp = 0x%08x\n", read_uint32(sl->q_buf, 68)); - DD(sl, "process_sp = 0x%08x\n", read_uint32(sl->q_buf, 72)); - DD(sl, "rw = 0x%08x\n", read_uint32(sl->q_buf, 76)); - DD(sl, "rw2 = 0x%08x\n", read_uint32(sl->q_buf, 80)); + DLOG("xpsr = 0x%08x\n", read_uint32(sl->q_buf, 64)); + DLOG("main_sp = 0x%08x\n", read_uint32(sl->q_buf, 68)); + DLOG("process_sp = 0x%08x\n", read_uint32(sl->q_buf, 72)); + DLOG("rw = 0x%08x\n", read_uint32(sl->q_buf, 76)); + DLOG("rw2 = 0x%08x\n", read_uint32(sl->q_buf, 80)); } void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { @@ -499,7 +508,7 @@ void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { sl->q_len = (size_t) size; stlink_print_data(sl); r = read_uint32(sl->q_buf, 0); - DD(sl, "r_idx (%2d) = 0x%08x\n", r_idx, r); + DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); switch (r_idx) { case 16: @@ -584,7 +593,7 @@ stlink_t* stlink_open_usb(const int verbose) { memset(sl, 0, sizeof (stlink_t)); memset(slu, 0, sizeof (struct stlink_libusb)); - sl->verbose = verbose; + ugly_init(verbose); sl->backend = &_stlink_usb_backend; sl->backend_data = slu; @@ -604,15 +613,15 @@ stlink_t* stlink_open_usb(const int verbose) { sl->sram_size = STM32L_SRAM_SIZE; if (libusb_init(&(slu->libusb_ctx))) { - fprintf(stderr, "failed to init libusb context, wrong version of libraries?\n"); - goto on_error; + WLOG("failed to init libusb context, wrong version of libraries?\n"); + goto on_error; } slu->usb_handle = libusb_open_device_with_vid_pid(slu->libusb_ctx, USB_ST_VID, USB_STLINK_32L_PID); if (slu->usb_handle == NULL) { // TODO - free usb context too... free(slu); - fprintf(stderr, "Couldn't find any ST-Link/V2 devices"); + WLOG("Couldn't find any ST-Link/V2 devices"); return NULL; } @@ -620,14 +629,15 @@ stlink_t* stlink_open_usb(const int verbose) { int r; r = libusb_detach_kernel_driver(slu->usb_handle, 0); - if (r<0) - printf("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); + if (r<0) { + WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); + } goto on_libusb_error; } if (libusb_get_configuration(slu->usb_handle, &config)) { /* this may fail for a previous configured device */ - printf("libusb_get_configuration()\n"); + WLOG("libusb_get_configuration()\n"); goto on_libusb_error; } @@ -635,25 +645,25 @@ stlink_t* stlink_open_usb(const int verbose) { printf("setting new configuration (%d -> 1)\n", config); if (libusb_set_configuration(slu->usb_handle, 1)) { /* this may fail for a previous configured device */ - printf("libusb_set_configuration()\n"); + WLOG("libusb_set_configuration() failed\n"); goto on_libusb_error; } } if (libusb_claim_interface(slu->usb_handle, 0)) { - printf("libusb_claim_interface()\n"); + WLOG("libusb_claim_interface() failed\n"); goto on_libusb_error; } slu->req_trans = libusb_alloc_transfer(0); if (slu->req_trans == NULL) { - printf("libusb_alloc_transfer\n"); + WLOG("libusb_alloc_transfer failed\n"); goto on_libusb_error; } slu->rep_trans = libusb_alloc_transfer(0); if (slu->rep_trans == NULL) { - printf("libusb_alloc_transfer\n"); + WLOG("libusb_alloc_transfer failed\n"); goto on_libusb_error; } // TODO - could use the scanning techniq from stm8 code here... @@ -666,7 +676,7 @@ stlink_t* stlink_open_usb(const int verbose) { /* success */ if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { - printf("-- exit_dfu_mode\n"); + ILOG("-- exit_dfu_mode\n"); stlink_exit_dfu_mode(sl); } stlink_version(sl); diff --git a/src/uglylogging.c b/src/uglylogging.c new file mode 100644 index 000000000..c6d07f89f --- /dev/null +++ b/src/uglylogging.c @@ -0,0 +1,58 @@ +/* + * UglyLogging. Slow, yet another wheel reinvented, but enough to make the + * rest of our code pretty enough. + * + */ + +#include +#include +#include +#include +#include + +#include "uglylogging.h" + +static int max_level; + +int ugly_init(int maximum_threshold) { + max_level = maximum_threshold; + return 0; +} + +int ugly_log(int level, const char *tag, const char *format, ...) { + if (level > max_level) { + return 0; + } + va_list args; + va_start(args, format); + time_t mytt = time(NULL); + struct tm *tt; + tt = localtime(&mytt); + fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt->tm_year + 1900, tt->tm_mon + 1, tt->tm_mday, tt->tm_hour, tt->tm_min, tt->tm_sec); + switch (level) { + case UDEBUG: + fprintf(stderr, "DEBUG %s: ", tag); + break; + case UINFO: + fprintf(stderr, "INFO %s: ", tag); + break; + case UWARN: + fprintf(stderr, "WARN %s: ", tag); + break; + case UERROR: + fprintf(stderr, "ERROR %s: ", tag); + break; + case UFATAL: + fprintf(stderr, "FATAL %s: ", tag); + vfprintf(stderr, format, args); + exit(EXIT_FAILURE); + // NEVER GETS HERE!!! + break; + default: + fprintf(stderr, "%d %s: ", level, tag); + break; + } + vfprintf(stderr, format, args); + va_end(args); + return 1; +} \ No newline at end of file diff --git a/src/uglylogging.h b/src/uglylogging.h new file mode 100644 index 000000000..fa34d460c --- /dev/null +++ b/src/uglylogging.h @@ -0,0 +1,27 @@ +/* + * Ugly, low performance, configurable level, logging "framework" + */ + +#ifndef UGLYLOGGING_H +#define UGLYLOGGING_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define UDEBUG 90 +#define UINFO 50 +#define UWARN 30 +#define UERROR 20 +#define UFATAL 10 + + int ugly_init(int maximum_threshold); + int ugly_log(int level, const char *tag, const char *format, ...); + + +#ifdef __cplusplus +} +#endif + +#endif /* UGLYLOGGING_H */ + From a672ee1a34f0602079c52bbd04e7d115ccb37651 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 1 Nov 2011 18:50:06 +0000 Subject: [PATCH 0015/1435] Ignore all elf outputs. Ignore pdflatex outputs --- .gitignore | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 44d2e4ddf..0a541c78b 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,9 @@ /nbproject/private/ *.o +*.elf +doc/tutorial/*.log +doc/tutorial/*.aux libstlink.a test_usb test_sg -gdbserver/st-utils \ No newline at end of file +gdbserver/st-utils From ee772151c2aca1508b906982ad30944087e8143b Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 1 Nov 2011 18:51:14 +0000 Subject: [PATCH 0016/1435] Remove unneeded old files --- example/blink/default_bootloader.bin | Bin 2048 -> 0 bytes example/blink/disasm.sh | 3 --- 2 files changed, 3 deletions(-) delete mode 100755 example/blink/default_bootloader.bin delete mode 100755 example/blink/disasm.sh diff --git a/example/blink/default_bootloader.bin b/example/blink/default_bootloader.bin deleted file mode 100755 index 0e3137184c083c5657dd9bd45ffdf7846fc02962..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2048 zcmah~eQaCR6+h2@{vh?zmz8Z!$m*9b&6(UKty&RAQ6G+DKc|6oLy^*{70ftFPTDo{sI=wt;@6K8?7B9)m|t({c#+~Nt1mcBn&6BbRlZIb(%y!Xz| zH7VPFd(!#3_nhP3x#!+vaDlw3jG_xAW(IU9pIHVK5~*7l0@{D(gG}NvqU#Nxp~W{AVO{ zXy${1$lk#~8G&nWp?^ht1MgbVUPX|DS(kBA9;JGby;8x)^H0x~4;PXkUl=&zgOVU; z5*+W@t#7WKG=VU>2%|VWX?jNroqx#}Zuwe>;=XERFA~yciJrpoZ_!pT5UQOO3>d5A>OYxe*s@-eNBC;#Fx5VvXpux6(x?$a)2a|2Qq>7Z#&3tI?q)q73tjm+v^#J z_nNQ4v@|8gS5d~R&XW~SfmWNS_L8Hg6`%XlU_c}5lW(jNtx=q=@p$ejO^@7w)Wia8 z5iYr?6OSf^*u+BlQQ?xCtQ{2#4hWY-vVM{D$Ho`nY2lKGEZ(>FDQH1fi{;b%sm5W# z`y`6-u7APf$o3$~u9$)>#kCf$?Lbc_m;E>r6^lG(pA(L^PxBM{rPEvPYj5Xww^w<4 z^M!NcLT+;b*>>l??yj4C+a%2^Z_}s?O>4Bx$=>;_q-yu~2(rA#pUw(a>0b4|o|p#B zy=9~2oaui^Y-mj-#er1prYH=iHmVzv1yc;_razeUESFZ~r*~`*dEZ&f4dmj51!xJY zqw$8gnDsSJEzi#%%J$9|b{`s~?_lT6z=Ogd$Nzojni(0ERKnFDXw-j4q+ZNAnu1}_ z`dMVo(&#bN-It3y!ko)jY6D`%rlM^74iBfrx9S2`mv=({3Ox|v%XA-u2nfN?PLtbR1ISMM;OQF!e%V*`1=Z11lByS^#DuRcug>P4Hsj@>gM`5%zVS(1K|@_bhIYbr?xRPDSejU#*5empJHo9(f4i3cdtpDJixcmA3e+TJ2GEzWmt z+#QJ3r{bb<(%5OdY>XMF3C)k3vG8w;uC_JB5uZyJ%a+*uLu9Jm0#$loPOKW6^MH_U zuT}0rw#``=S}eNTR{xK$3_J7ViTegm_T_^_WZE`<;{@1PZ zX5d6Kq26N);VtuZr}*mU7P1d)411`Pc{_I+*+1>?8lLxK^{v#85ACt=fqBoVo{8Qv z?D-x|Bkx?6qW(>rSQs$#!l@f&m2;(LcH=%2pM^+8KgrS9!<#T09Yqsv8* z=VoB4s#{MNyxtO@02zx-JIQ=(sqD=qyYos?tRE_jy0r3T2(8D>mD_=WW>DLju&SVe# E2h&9CasU7T diff --git a/example/blink/disasm.sh b/example/blink/disasm.sh deleted file mode 100755 index b3b46da6e..000000000 --- a/example/blink/disasm.sh +++ /dev/null @@ -1,3 +0,0 @@ -#!/usr/bin/env sh -#/home/texane/sat/bin/arm-none-eabi-objdump -marm -Mforce-thumb -EL -b binary -D /tmp/barfoo -/home/texane/sat/bin/arm-none-eabi-objdump -marm -EL -b binary -D /tmp/barfoo From e8bae670d226061d567869d24fe3cbc175dff364 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 1 Nov 2011 21:23:16 +0000 Subject: [PATCH 0017/1435] Fix compilation for 32bit machines %Ld works for size_t only on 64 bit, the correct conversion is %zd --- gdbserver/gdb-server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 3af0d8a90..65297bc0c 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -143,7 +143,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { break; case 'd': if (strlen(optarg) > sizeof (st->devicename)) { - fprintf(stderr, "device name too long: %ld\n", strlen(optarg)); + fprintf(stderr, "device name too long: %zd\n", strlen(optarg)); } else { strcpy(st->devicename, optarg); } From c0c45e259e1d7efd79c22369c7160d910e4035e0 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 1 Nov 2011 21:56:43 +0000 Subject: [PATCH 0018/1435] More generic stlinkv2 udev naming Better support for F4, or anything else that appears as an stlinkv2 --- 49-stm32l-discovery.rules => 49-stlinkv2.rules | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) rename 49-stm32l-discovery.rules => 49-stlinkv2.rules (71%) diff --git a/49-stm32l-discovery.rules b/49-stlinkv2.rules similarity index 71% rename from 49-stm32l-discovery.rules rename to 49-stlinkv2.rules index 1f3ce7795..a11215c57 100644 --- a/49-stm32l-discovery.rules +++ b/49-stlinkv2.rules @@ -1,9 +1,11 @@ -# stm32l discovery board, with onboard st/linkv2 -# +# stm32 discovery boards, with onboard st/linkv2 +# ie, STM32L, STM32F4. +# STM32VL has st/linkv1, which is quite different + SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3748", \ MODE:="0666", \ - SYMLINK+="stm32l_stlink%n" -# + SYMLINK+="stlinkv2_%n" + # If you share your linux system with other users, or just don't like the # idea of write permission for everybody, you can replace MODE:="0666" with # OWNER:="yourusername" to create the device owned by you, or with From 66c50cec899fcb25e6a4ea670208defebe8759cd Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 00:35:19 +0000 Subject: [PATCH 0019/1435] Remove sg-utils test output More bulk cleanup on the path to removing sg-utils dependencies. Trying to make test-sg as simple as possible so I can use it reliably to test on both master and my killsg branch --- src/test_sg.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/test_sg.c b/src/test_sg.c index 34fbe540c..a4db8f236 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -14,7 +14,6 @@ int main(int argc, char *argv[]) { // set scpi lib debug level: 0 for no debug info, 10 for lots - const int scsi_verbose = 2; char *dev_name; switch (argc) { @@ -37,14 +36,11 @@ int main(int argc, char *argv[]) { return EXIT_FAILURE; } - fputs("*** stlink access test ***\n", stderr); - fprintf(stderr, "Using sg_lib %s : scsi_pt %s\n", sg_lib_version(), - scsi_pt_version()); - - stlink_t *sl = stlink_quirk_open(dev_name, scsi_verbose); + stlink_t *sl = stlink_quirk_open(dev_name, 10); if (sl == NULL) return EXIT_FAILURE; - + + // we are in mass mode, go to swd stlink_enter_swd_mode(sl); stlink_current_mode(sl); @@ -176,7 +172,7 @@ int main(int argc, char *argv[]) { stlink_force_debug(sl); stlink_status(sl); #endif -#if 1 /* read the system bootloader */ +#if 0 /* read the system bootloader */ fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr); stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size); #endif @@ -202,6 +198,7 @@ int main(int argc, char *argv[]) { stlink_run_at(sl, sl->sram_base); #endif +#if 0 stlink_run(sl); stlink_status(sl); //---------------------------------------------------------------------- @@ -209,6 +206,7 @@ int main(int argc, char *argv[]) { stlink_exit_debug_mode(sl); stlink_current_mode(sl); stlink_close(sl); +#endif //fflush(stderr); fflush(stdout); return EXIT_SUCCESS; From afb487cfb627762590ee1acf750a77417cf73e18 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 00:36:31 +0000 Subject: [PATCH 0020/1435] Remove -sg's private version decoding Remove duplication of stlink version decoding, and put the decoded version information into the stlink object itself. --- src/stlink-common.c | 17 ++++++++--------- src/stlink-common.h | 1 + src/stlink-sg.c | 37 +++---------------------------------- src/stlink-sg.h | 7 ------- 4 files changed, 12 insertions(+), 50 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 707316cc9..6a9b9383d 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -356,19 +356,18 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { void stlink_version(stlink_t *sl) { D(sl, "*** looking up stlink version\n"); - stlink_version_t slv; sl->backend->version(sl); - _parse_version(sl, &slv); + _parse_version(sl, &sl->version); - DD(sl, "st vid = 0x%04x (expect 0x%04x)\n", slv.st_vid, USB_ST_VID); - DD(sl, "stlink pid = 0x%04x\n", slv.stlink_pid); - DD(sl, "stlink version = 0x%x\n", slv.stlink_v); - DD(sl, "jtag version = 0x%x\n", slv.jtag_v); - DD(sl, "swim version = 0x%x\n", slv.swim_v); - if (slv.jtag_v == 0) { + DD(sl, "st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID); + DD(sl, "stlink pid = 0x%04x\n", sl->version.stlink_pid); + DD(sl, "stlink version = 0x%x\n", sl->version.stlink_v); + DD(sl, "jtag version = 0x%x\n", sl->version.jtag_v); + DD(sl, "swim version = 0x%x\n", sl->version.swim_v); + if (sl->version.jtag_v == 0) { DD(sl, " notice: the firmware doesn't support a jtag/swd interface\n"); } - if (slv.swim_v == 0) { + if (sl->version.swim_v == 0) { DD(sl, " notice: the firmware doesn't support a swim interface\n"); } } diff --git a/src/stlink-common.h b/src/stlink-common.h index 9481609f6..2ac56f2b6 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -179,6 +179,7 @@ extern "C" { stm32_addr_t sram_base; size_t sram_size; + struct stlink_version_ version; }; // some quick and dirty logging... diff --git a/src/stlink-sg.c b/src/stlink-sg.c index b8220de13..e8dee5db0 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -268,35 +268,6 @@ void stlink_stat(stlink_t *stl, char *txt) { } -static void parse_version(stlink_t *stl) { - struct stlink_libsg *sl = stl->backend_data; - - sl->st_vid = 0; - sl->stlink_pid = 0; - - if (stl->q_len <= 0) { - fprintf(stderr, "Error: could not parse the stlink version"); - return; - } - - uint32_t b0 = stl->q_buf[0]; //lsb - uint32_t b1 = stl->q_buf[1]; - uint32_t b2 = stl->q_buf[2]; - uint32_t b3 = stl->q_buf[3]; - uint32_t b4 = stl->q_buf[4]; - uint32_t b5 = stl->q_buf[5]; //msb - - // b0 b1 || b2 b3 | b4 b5 - // 4b | 6b | 6b || 2B | 2B - // stlink_v | jtag_v | swim_v || st_vid | stlink_pid - - sl->stlink_v = (b0 & 0xf0) >> 4; - sl->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); - sl->swim_v = b1 & 0x3f; - sl->st_vid = (b3 << 8) | b2; - sl->stlink_pid = (b5 << 8) | b4; -} - void _stlink_sg_version(stlink_t *stl) { struct stlink_libsg *sl = stl->backend_data; D(stl, "\n*** stlink_version ***\n"); @@ -305,7 +276,6 @@ void _stlink_sg_version(stlink_t *stl) { stl->q_len = 6; sl->q_addr = 0; stlink_q(stl); - parse_version(stl); } // Get stlink mode: @@ -781,7 +751,6 @@ stlink_t* stlink_open(const char *dev_name, const int verbose) { slsg->sg_fd = sg_fd; sl->core_stat = STLINK_CORE_STAT_UNKNOWN; - slsg->core_id = 0; slsg->q_addr = 0; clear_buf(sl); @@ -814,13 +783,13 @@ stlink_t* stlink_quirk_open(const char *dev_name, const int verbose) { stlink_version(sl); struct stlink_libsg *sg = sl->backend_data; - if ((sg->st_vid != USB_ST_VID) || (sg->stlink_pid != USB_STLINK_PID)) { + if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { fprintf(stderr, "Error: the device %s is not a stlink\n", dev_name); fprintf(stderr, " VID: got %04x expect %04x \n", - sg->st_vid, USB_ST_VID); + sl->version.st_vid, USB_ST_VID); fprintf(stderr, " PID: got %04x expect %04x \n", - sg->stlink_pid, USB_STLINK_PID); + sl->version.stlink_pid, USB_STLINK_PID); return NULL; } diff --git a/src/stlink-sg.h b/src/stlink-sg.h index 523b7d883..b3ab9c00e 100644 --- a/src/stlink-sg.h +++ b/src/stlink-sg.h @@ -54,13 +54,6 @@ extern "C" { // Sense (error information) data unsigned char sense_buf[SENSE_BUF_LEN]; - uint32_t st_vid; - uint32_t stlink_pid; - uint32_t stlink_v; - uint32_t jtag_v; - uint32_t swim_v; - uint32_t core_id; - reg reg; }; #else From 7de94e5491c2a5f0bba4e374c6aad6bdd61ee235 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 00:37:32 +0000 Subject: [PATCH 0021/1435] drop non shared directories from netbeans project --- nbproject/configurations.xml | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/nbproject/configurations.xml b/nbproject/configurations.xml index 794a3ab5c..567946524 100644 --- a/nbproject/configurations.xml +++ b/nbproject/configurations.xml @@ -127,20 +127,6 @@ - - - - - - - - - - - - - - Date: Thu, 3 Nov 2011 01:07:15 +0000 Subject: [PATCH 0022/1435] Successfully locate and open stlinkv1 by usb Very very raw, this just finds the device and opens the usb handle. --- Makefile | 2 +- src/stlink-sg.c | 84 ++++++++++++++++++++++++++++++++++++++++++++----- src/stlink-sg.h | 3 ++ src/test_sg.c | 3 +- 4 files changed, 82 insertions(+), 10 deletions(-) diff --git a/Makefile b/Makefile index c3c345a69..646dde12d 100644 --- a/Makefile +++ b/Makefile @@ -4,7 +4,7 @@ VPATH=src SOURCES_LIB=stlink-common.c stlink-usb.c stlink-sg.c uglylogging.c OBJS_LIB=$(SOURCES_LIB:.c=.o) -TEST_PROGRAMS=test_usb #test_sg +TEST_PROGRAMS=test_usb test_sg LDFLAGS=-lusb-1.0 -L. -lstlink CFLAGS+=-g diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 5d1f970cd..3b9958d73 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -736,26 +736,94 @@ stlink_backend_t _stlink_sg_backend = { _stlink_sg_force_debug }; -stlink_t* stlink_open(const char *dev_name, const int verbose) { - fprintf(stderr, "\n*** stlink_open [%s] ***\n", dev_name); - int sg_fd = scsi_pt_open_device(dev_name, RDWR, verbose); - if (sg_fd < 0) { - fprintf(stderr, "error opening device: %s: %s\n", dev_name, - safe_strerror(-sg_fd)); +#if using_stm8_stuff_XXXX +stlink *stlink_open(libusb_context *usb_context) +{ + stlink *stl = malloc(sizeof(stlink)); + stl->handle = libusb_open_device_with_vid_pid(usb_context, USB_VID_ST, USB_PID_STLINK); + if (stl->handle == NULL) { + free(stl); + return NULL; + } + + libusb_device *dev = libusb_get_device(stl->handle); + struct libusb_config_descriptor *conf_desc; + int ret = libusb_get_config_descriptor(dev, 0, &conf_desc); + if (ret != LIBUSB_SUCCESS) { + libusb_close(stl->handle); + free(stl); + return NULL; + } + for (int i = 0; i < conf_desc->bNumInterfaces; i++) { + printf("interface %d\n", i); + for (int j = 0; j < conf_desc->interface[i].num_altsetting; j++) { + for (int k = 0; k < conf_desc->interface[i].altsetting[j].bNumEndpoints; k++) { + const struct libusb_endpoint_descriptor *endpoint; + endpoint = &conf_desc->interface[i].altsetting[j].endpoint[k]; + if (endpoint->bEndpointAddress & LIBUSB_ENDPOINT_IN) { + stl->endpoint_in = endpoint->bEndpointAddress; + printf("Found IN endpoint\n"); + } else { + stl->endpoint_out = endpoint->bEndpointAddress; + printf("Found OUT endpoint\n"); + } + } + } + } + libusb_free_config_descriptor(conf_desc); + + ret = libusb_kernel_driver_active(stl->handle, 0); + if (ret == 1) { + printf("kernel driver active\n"); + } else if (ret == 0) { + //printf("kernel driver not active\n"); + } else { + fprintf(stderr, "libusb_kernel_driver_active = %d\n", ret); + } + ret = libusb_claim_interface(stl->handle, 0); + if (ret != LIBUSB_SUCCESS) { + fprintf(stderr, "claiming interface failed: %d\n", ret); + libusb_close(stl->handle); + free(stl); return NULL; } + return stl; +} +#endif + + +static stlink_t* stlink_open(const char *dev_name, const int verbose) { + fprintf(stderr, "\n*** stlink_open [%s] ***\n", dev_name); + stlink_t *sl = malloc(sizeof (stlink_t)); struct stlink_libsg *slsg = malloc(sizeof (struct stlink_libsg)); if (sl == NULL || slsg == NULL) { - fprintf(stderr, "Couldn't malloc stlink and stlink_sg structures out of memory!\n"); + WLOG("Couldn't malloc stlink and stlink_sg structures out of memory!\n"); + return NULL; + } + + if (libusb_init(&(slsg->libusb_ctx))) { + WLOG("failed to init libusb context, wrong version of libraries?\n"); + free(sl); + free(slsg); return NULL; } + + slsg->handle = libusb_open_device_with_vid_pid(slsg->libusb_ctx, USB_ST_VID, USB_STLINK_PID); + if (slsg->handle == NULL) { + WLOG("Failed to find an stlink v1 by VID:PID\n"); + free(sl); + free(slsg); + return NULL; + } + + DLOG("Successfully opened stlinkv1 by libusb :)\n"); + sl->verbose = verbose; sl->backend_data = slsg; sl->backend = &_stlink_sg_backend; - slsg->sg_fd = sg_fd; sl->core_stat = STLINK_CORE_STAT_UNKNOWN; slsg->q_addr = 0; clear_buf(sl); diff --git a/src/stlink-sg.h b/src/stlink-sg.h index 723c66a05..c9776cddb 100644 --- a/src/stlink-sg.h +++ b/src/stlink-sg.h @@ -41,6 +41,9 @@ extern "C" { struct stlink_libsg { + libusb_context* libusb_ctx; + libusb_device_handle *handle; + int sg_fd; int do_scsi_pt_err; diff --git a/src/test_sg.c b/src/test_sg.c index 30f867a1f..742ba4453 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -29,10 +29,11 @@ int main(int argc, char *argv[]) { dev_name = argv[1]; break; default: + fprintf(stderr, "bzzt\n"); return EXIT_FAILURE; } - stlink_t *sl = stlink_v1_open(dev_name, 10); + stlink_t *sl = stlink_v1_open(dev_name, 99); if (sl == NULL) return EXIT_FAILURE; From 3bf3bbef0ba03fa54c531b94daaf0c4029c0af8b Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 03:45:23 +0000 Subject: [PATCH 0023/1435] Read stlink version info via libusb. Hooray! Stage 1 complete. The stlink version can now be read by sending the scsi commands via libusb directly, instead of using sg-utils. It's very very prototype code however, but should come together from here. Major bugs: Only works when the device has been first plugged in. I'm clearly not resetting some usb state somewhere. Now that libusb is being used directly, you can use linux usb-storage quirks to completely IGNORE the device as mass storage. We'll just grab it via libusb when we want it. --- src/stlink-sg.c | 216 ++++++++++++++++++++++++++++++++++------------- src/stlink-sg.h | 4 +- src/stlink-usb.c | 2 +- 3 files changed, 159 insertions(+), 63 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 3b9958d73..9d71df123 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -281,7 +281,102 @@ void _stlink_sg_version(stlink_t *stl) { sl->cdb_cmd_blk[0] = STLINK_GET_VERSION; stl->q_len = 6; sl->q_addr = 0; - stlink_q(stl); +// stlink_q(stl); + // HACK use my own private version right now... + + int try = 0; + int ret = 0; + int real_transferred; + +/* + uint32_t dCBWSignature; + uint32_t dCBWTag; + uint32_t dCBWDataTransferLength; + uint8_t bmCBWFlags; + uint8_t bCBWLUN; + uint8_t bCBWCBLength; + uint8_t CBWCB[16]; + */ + +#if using_old_code_examples + /* + * and from old code? + cmd[i++] = 'U'; + cmd[i++] = 'S'; + cmd[i++] = 'B'; + cmd[i++] = 'C'; + write_uint32(&cmd[i], sg->sg_transfer_idx); + write_uint32(&cmd[i + 4], len); + i += 8; + cmd[i++] = (dir == SG_DXFER_FROM_DEV)?0x80:0; + cmd[i++] = 0; /* Logical unit */ + cmd[i++] = 0xa; /* Command length */ + */ +#endif + + int i = 0; + stl->c_buf[i++] = 'U'; + stl->c_buf[i++] = 'S'; + stl->c_buf[i++] = 'B'; + stl->c_buf[i++] = 'C'; + // tag is allegedly ignored... TODO - verify + write_uint32(&stl->c_buf[i], 1); + // TODO - Does this even matter? verify with more commands.... + uint32_t command_length = STLINK_CMD_SIZE; + write_uint32(&stl->c_buf[i+4], command_length); + i+= 8; + stl->c_buf[i++] = LIBUSB_ENDPOINT_IN; + // assumption: lun is always 0; + stl->c_buf[i++] = 0; + + stl->c_buf[i++] = sizeof(sl->cdb_cmd_blk); + + // duh, now the actual data... + memcpy(&(stl->c_buf[i]), sl->cdb_cmd_blk, sizeof(sl->cdb_cmd_blk)); + + int sending_length = STLINK_SG_SIZE; + DLOG("sending length set to: %d\n", sending_length); + + // send.... + do { + DLOG("attempting tx...\n"); + ret = libusb_bulk_transfer(sl->usb_handle, sl->ep_req, stl->c_buf, sending_length, + &real_transferred, 3 * 1000); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(sl->usb_handle, sl->ep_req); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { + WLOG("sending failed: %d\n", ret); + return; + } + DLOG("Actually sent: %d\n", real_transferred); + + // now wait for our response... + // length copied from stlink-usb... + int rx_length = 6; + try = 0; + do { + DLOG("attempting rx\n"); + ret = libusb_bulk_transfer(sl->usb_handle, sl->ep_rep, stl->q_buf, rx_length, + &real_transferred, 3 * 1000); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(sl->usb_handle, sl->ep_req); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + + if (ret != LIBUSB_SUCCESS) { + WLOG("Receiving failed: %d\n", ret); + return; + } + + if (real_transferred != rx_length) { + WLOG("received unexpected amount: %d != %d\n", real_transferred, rx_length); + } + + DLOG("Actually received: %d\n", real_transferred); } // Get stlink mode: @@ -736,65 +831,8 @@ stlink_backend_t _stlink_sg_backend = { _stlink_sg_force_debug }; -#if using_stm8_stuff_XXXX -stlink *stlink_open(libusb_context *usb_context) -{ - stlink *stl = malloc(sizeof(stlink)); - stl->handle = libusb_open_device_with_vid_pid(usb_context, USB_VID_ST, USB_PID_STLINK); - if (stl->handle == NULL) { - free(stl); - return NULL; - } - - libusb_device *dev = libusb_get_device(stl->handle); - struct libusb_config_descriptor *conf_desc; - int ret = libusb_get_config_descriptor(dev, 0, &conf_desc); - if (ret != LIBUSB_SUCCESS) { - libusb_close(stl->handle); - free(stl); - return NULL; - } - for (int i = 0; i < conf_desc->bNumInterfaces; i++) { - printf("interface %d\n", i); - for (int j = 0; j < conf_desc->interface[i].num_altsetting; j++) { - for (int k = 0; k < conf_desc->interface[i].altsetting[j].bNumEndpoints; k++) { - const struct libusb_endpoint_descriptor *endpoint; - endpoint = &conf_desc->interface[i].altsetting[j].endpoint[k]; - if (endpoint->bEndpointAddress & LIBUSB_ENDPOINT_IN) { - stl->endpoint_in = endpoint->bEndpointAddress; - printf("Found IN endpoint\n"); - } else { - stl->endpoint_out = endpoint->bEndpointAddress; - printf("Found OUT endpoint\n"); - } - } - } - } - libusb_free_config_descriptor(conf_desc); - - ret = libusb_kernel_driver_active(stl->handle, 0); - if (ret == 1) { - printf("kernel driver active\n"); - } else if (ret == 0) { - //printf("kernel driver not active\n"); - } else { - fprintf(stderr, "libusb_kernel_driver_active = %d\n", ret); - } - ret = libusb_claim_interface(stl->handle, 0); - if (ret != LIBUSB_SUCCESS) { - fprintf(stderr, "claiming interface failed: %d\n", ret); - libusb_close(stl->handle); - free(stl); - return NULL; - } - - return stl; -} -#endif - - static stlink_t* stlink_open(const char *dev_name, const int verbose) { - fprintf(stderr, "\n*** stlink_open [%s] ***\n", dev_name); + DLOG("*** stlink_open [%s] ***\n", dev_name); stlink_t *sl = malloc(sizeof (stlink_t)); struct stlink_libsg *slsg = malloc(sizeof (struct stlink_libsg)); @@ -810,13 +848,69 @@ static stlink_t* stlink_open(const char *dev_name, const int verbose) { return NULL; } - slsg->handle = libusb_open_device_with_vid_pid(slsg->libusb_ctx, USB_ST_VID, USB_STLINK_PID); - if (slsg->handle == NULL) { + libusb_set_debug(slsg->libusb_ctx, 3); + + slsg->usb_handle = libusb_open_device_with_vid_pid(slsg->libusb_ctx, USB_ST_VID, USB_STLINK_PID); + if (slsg->usb_handle == NULL) { WLOG("Failed to find an stlink v1 by VID:PID\n"); + libusb_close(slsg->usb_handle); + free(sl); + free(slsg); + return NULL; + } + + // TODO + // Could read the interface config descriptor, and assert lots of the assumptions + + // assumption: numInterfaces is always 1... + if (libusb_kernel_driver_active(slsg->usb_handle, 0) == 1) { + int r = libusb_detach_kernel_driver(slsg->usb_handle, 0); + if (r < 0) { + WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); + libusb_close(slsg->usb_handle); + free(sl); + free(slsg); + return NULL; + } + DLOG("Kernel driver was successfully detached\n"); + } + + int config; + if (libusb_get_configuration(slsg->usb_handle, &config)) { + /* this may fail for a previous configured device */ + WLOG("libusb_get_configuration()\n"); + libusb_close(slsg->usb_handle); + free(sl); + free(slsg); + return NULL; + + } + + // assumption: bConfigurationValue is always 1 + if (config != 1) { + WLOG("Your stlink got into a real weird configuration, trying to fix it!\n"); + DLOG("setting new configuration (%d -> 1)\n", config); + if (libusb_set_configuration(slsg->usb_handle, 1)) { + /* this may fail for a previous configured device */ + WLOG("libusb_set_configuration() failed\n"); + libusb_close(slsg->usb_handle); + free(sl); + free(slsg); + return NULL; + } + } + + if (libusb_claim_interface(slsg->usb_handle, 0)) { + WLOG("libusb_claim_interface() failed\n"); + libusb_close(slsg->usb_handle); free(sl); free(slsg); return NULL; } + + // assumption: endpoint config is fixed mang. really. + slsg->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; + slsg->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; DLOG("Successfully opened stlinkv1 by libusb :)\n"); diff --git a/src/stlink-sg.h b/src/stlink-sg.h index c9776cddb..2e27ceb5f 100644 --- a/src/stlink-sg.h +++ b/src/stlink-sg.h @@ -42,7 +42,9 @@ extern "C" { struct stlink_libsg { libusb_context* libusb_ctx; - libusb_device_handle *handle; + libusb_device_handle *usb_handle; + unsigned ep_rep; + unsigned ep_req; int sg_fd; int do_scsi_pt_err; diff --git a/src/stlink-usb.c b/src/stlink-usb.c index c0b0009f2..a81676936 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -631,8 +631,8 @@ stlink_t* stlink_open_usb(const int verbose) { r = libusb_detach_kernel_driver(slu->usb_handle, 0); if (r<0) { WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); + goto on_libusb_error; } - goto on_libusb_error; } if (libusb_get_configuration(slu->usb_handle, &config)) { From f587baa03ac9598130fac7f4ab58bef4030cb8df Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 21:28:19 +0000 Subject: [PATCH 0024/1435] Use the libusb based sense and status reading from afaerber Before, I could a single operation (get version) after plugging in, now I can issue two at least :) I suspect there are two problems still. 1, I'm not using tags properly, as the original sg-utils code seemed to skip that. 2) I'm pretty sure I need to be sending variable lengths for the cdb field. --- src/stlink-sg.c | 332 +++++++++++++++++++++++++++++++++--------------- src/stlink-sg.h | 1 + 2 files changed, 233 insertions(+), 100 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 9d71df123..2c52e2a4c 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -70,6 +70,7 @@ #define __USE_GNU +#include #include #include #include @@ -214,14 +215,238 @@ static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { } #endif -void stlink_q(stlink_t *sl) { -#if FINISHED_WITH_SG +static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { + char dbugblah[100]; + char *dbugp = dbugblah; + dbugp += sprintf(dbugp, "Sending CDB ["); + for (uint8_t i = 0; i < cdb_len; i++) { + dbugp += sprintf(dbugp, " %#02x", (unsigned int) cdb[i]); + } + sprintf(dbugp, "]\n"); + DLOG(dbugblah); + return 0; +} + +/** + * Wraps a CDB mass storage command in the appropriate gunk to get it down + * @param handle + * @param endpoint + * @param cdb + * @param cdb_length + * @param lun + * @param flags + * @param expected_rx_size + * @return + */ +int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, + uint8_t *cdb, uint8_t cdb_length, + uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { + DLOG("Sending usb m-s cmd: cdblen:%d, rxsize=%d\n", cdb_length, expected_rx_size); + dump_CDB_command(cdb, cdb_length); + + int try = 0; + int ret = 0; + int real_transferred; + int i = 0; + + uint8_t c_buf[STLINK_SG_SIZE]; + // tag is allegedly ignored... TODO - verify + uint32_t tag = 1; + c_buf[i++] = 'U'; + c_buf[i++] = 'S'; + c_buf[i++] = 'B'; + c_buf[i++] = 'C'; + write_uint32(&c_buf[i], tag); + write_uint32(&c_buf[i+4], expected_rx_size); + i+= 8; + c_buf[i++] = flags; + c_buf[i++] = lun; + + c_buf[i++] = cdb_length; + + // Now the actual CDB request + assert(cdb_length <= CDB_SL); + memcpy(&(c_buf[i]), cdb, cdb_length); + + int sending_length = STLINK_SG_SIZE; + DLOG("sending length set to: %d\n", sending_length); + + // send.... + do { + DLOG("attempting tx...\n"); + ret = libusb_bulk_transfer(handle, endpoint_out, c_buf, sending_length, + &real_transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(handle, endpoint_out); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { + WLOG("sending failed: %d\n", ret); + return -1; + } + DLOG("Actually sent: %d, returning tag: %d\n", real_transferred, tag); + return tag; +} + + +static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, uint32_t *tag) +{ + unsigned char csw[13]; + memset(csw, 0, sizeof(csw)); + int transferred; + int ret; + int try = 0; + do { + ret = libusb_bulk_transfer(handle, endpoint, (unsigned char *)&csw, sizeof(csw), + &transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(handle, endpoint); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { + fprintf(stderr, "%s: receiving failed: %d\n", __func__, ret); + return -1; + } + if (transferred != sizeof(csw)) { + fprintf(stderr, "%s: received unexpected amount: %d\n", __func__, transferred); + return -1; + } + + uint32_t rsig = read_uint32(csw, 0); + uint32_t rtag = read_uint32(csw, 4); + uint32_t residue = read_uint32(csw, 8); +#define USB_CSW_SIGNATURE 0x53425355 // 'U' 'S' 'B' 'S' (reversed) + if (rsig != USB_CSW_SIGNATURE) { + WLOG("status signature was invalid: %#x\n", rsig); + return -1; + } + DLOG("residue was= %#x\n", residue); + *tag = rtag; + uint8_t rstatus = csw[12]; + DLOG("rstatus = %x\n", rstatus); + return rstatus; +} + +/** + * Straight from stm8 stlink code... + * @param handle + * @param endpoint_in + * @param endpoint_out + */ +static void +get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_out) +{ + uint8_t cdb[16]; + memset(cdb, 0, sizeof(cdb)); +#define REQUEST_SENSE 0x03 +#define REQUEST_SENSE_LENGTH 18 + cdb[0] = REQUEST_SENSE; + cdb[4] = REQUEST_SENSE_LENGTH; + uint32_t tag = send_usb_mass_storage_command(handle, endpoint_out, cdb, sizeof(cdb), 0, + LIBUSB_ENDPOINT_IN, REQUEST_SENSE_LENGTH); + if (tag == 0) { + WLOG("refusing to send request sense with tag 0\n"); + return; + } + unsigned char sense[REQUEST_SENSE_LENGTH]; + int transferred; + int ret; + int try = 0; + do { + ret = libusb_bulk_transfer(handle, endpoint_in, sense, sizeof(sense), + &transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(handle, endpoint_in); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { + WLOG("receiving sense failed: %d\n", ret); + return; + } + if (transferred != sizeof(sense)) { + WLOG("received unexpected amount of sense: %d != %d\n", transferred, sizeof(sense)); + } + uint32_t received_tag; + int status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); + if (status != 0) { + WLOG("receiving sense failed with status: %02x\n", status); + return; + } + if (sense[0] != 0x70 && sense[0] != 0x71) { + WLOG("No sense data\n"); + } else { + WLOG("Sense KCQ: %02X %02X %02X\n", sense[2] & 0x0f, sense[12], sense[13]); + } +} + +int stlink_q(stlink_t *sl) { struct stlink_libsg* sg = sl->backend_data; - DLOG("CDB["); - for (int i = 0; i < CDB_SL; i++) - DLOG(" 0x%02x", (unsigned int) sg->cdb_cmd_blk[i]); - DLOG("]\n"); + //uint8_t cdb_len = 6; // FIXME varies!!! + uint8_t cdb_len = 10; // FIXME varies!!! + uint8_t lun = 0; // always zero... + send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, cdb_len, lun, LIBUSB_ENDPOINT_IN, sl->q_len); + + + // now wait for our response... + // length copied from stlink-usb... + int rx_length = sl->q_len; + int try = 0; + int real_transferred; + int ret; + do { + DLOG("attempting rx\n"); + ret = libusb_bulk_transfer(sg->usb_handle, sg->ep_rep, sl->q_buf, rx_length, + &real_transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(sg->usb_handle, sg->ep_req); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { + WLOG("Receiving failed: %d\n", ret); + return -1; + } + + if (real_transferred != rx_length) { + WLOG("received unexpected amount: %d != %d\n", real_transferred, rx_length); + } + + +// stm8 stuff... + + + uint32_t received_tag; + // -ve is for my errors, 0 is good, +ve is libusb sense status bytes + int status = get_usb_mass_storage_status(sg->usb_handle, sg->ep_rep, &received_tag); + if (status < 0) { + WLOG("receiving status failed: %d\n", status); + return -1; + } + if (status != 0) { + WLOG("receiving status not passed :(: %02x\n", status); + } + if (status == 1) { + get_sense(sg->usb_handle, sg->ep_rep, sg->ep_req); + return -1; + } + uint32_t tag = 1; + if (received_tag != tag) { + WLOG("received tag %d but expected %d\n", received_tag, tag); + //return -1; + } + if (rx_length > 0 && real_transferred != rx_length) { + return -1; + } + return 0; + + + DLOG("Actually received: %d\n", real_transferred); + +#if FINISHED_WITH_SG // Get control command descriptor of scsi structure, // (one object per command!!) struct sg_pt_base *ptvp = construct_scsi_pt_obj(); @@ -281,102 +506,9 @@ void _stlink_sg_version(stlink_t *stl) { sl->cdb_cmd_blk[0] = STLINK_GET_VERSION; stl->q_len = 6; sl->q_addr = 0; -// stlink_q(stl); + stlink_q(stl); // HACK use my own private version right now... - int try = 0; - int ret = 0; - int real_transferred; - -/* - uint32_t dCBWSignature; - uint32_t dCBWTag; - uint32_t dCBWDataTransferLength; - uint8_t bmCBWFlags; - uint8_t bCBWLUN; - uint8_t bCBWCBLength; - uint8_t CBWCB[16]; - */ - -#if using_old_code_examples - /* - * and from old code? - cmd[i++] = 'U'; - cmd[i++] = 'S'; - cmd[i++] = 'B'; - cmd[i++] = 'C'; - write_uint32(&cmd[i], sg->sg_transfer_idx); - write_uint32(&cmd[i + 4], len); - i += 8; - cmd[i++] = (dir == SG_DXFER_FROM_DEV)?0x80:0; - cmd[i++] = 0; /* Logical unit */ - cmd[i++] = 0xa; /* Command length */ - */ -#endif - - int i = 0; - stl->c_buf[i++] = 'U'; - stl->c_buf[i++] = 'S'; - stl->c_buf[i++] = 'B'; - stl->c_buf[i++] = 'C'; - // tag is allegedly ignored... TODO - verify - write_uint32(&stl->c_buf[i], 1); - // TODO - Does this even matter? verify with more commands.... - uint32_t command_length = STLINK_CMD_SIZE; - write_uint32(&stl->c_buf[i+4], command_length); - i+= 8; - stl->c_buf[i++] = LIBUSB_ENDPOINT_IN; - // assumption: lun is always 0; - stl->c_buf[i++] = 0; - - stl->c_buf[i++] = sizeof(sl->cdb_cmd_blk); - - // duh, now the actual data... - memcpy(&(stl->c_buf[i]), sl->cdb_cmd_blk, sizeof(sl->cdb_cmd_blk)); - - int sending_length = STLINK_SG_SIZE; - DLOG("sending length set to: %d\n", sending_length); - - // send.... - do { - DLOG("attempting tx...\n"); - ret = libusb_bulk_transfer(sl->usb_handle, sl->ep_req, stl->c_buf, sending_length, - &real_transferred, 3 * 1000); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(sl->usb_handle, sl->ep_req); - } - try++; - } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); - if (ret != LIBUSB_SUCCESS) { - WLOG("sending failed: %d\n", ret); - return; - } - DLOG("Actually sent: %d\n", real_transferred); - - // now wait for our response... - // length copied from stlink-usb... - int rx_length = 6; - try = 0; - do { - DLOG("attempting rx\n"); - ret = libusb_bulk_transfer(sl->usb_handle, sl->ep_rep, stl->q_buf, rx_length, - &real_transferred, 3 * 1000); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(sl->usb_handle, sl->ep_req); - } - try++; - } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); - - if (ret != LIBUSB_SUCCESS) { - WLOG("Receiving failed: %d\n", ret); - return; - } - - if (real_transferred != rx_length) { - WLOG("received unexpected amount: %d != %d\n", real_transferred, rx_length); - } - - DLOG("Actually received: %d\n", real_transferred); } // Get stlink mode: diff --git a/src/stlink-sg.h b/src/stlink-sg.h index 2e27ceb5f..8485d3d88 100644 --- a/src/stlink-sg.h +++ b/src/stlink-sg.h @@ -19,6 +19,7 @@ extern "C" { #define RDWR 0 #define RO 1 #define SG_TIMEOUT_SEC 1 // actually 1 is about 2 sec +#define SG_TIMEOUT_MSEC 3 * 1000 // Each CDB can be a total of 6, 10, 12, or 16 bytes, later version // of the SCSI standard also allow for variable-length CDBs (min. CDB is 6). // the stlink needs max. 10 bytes. From 22d0777df9f4987bd60ddf6bba5ef64ac0628d8a Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 23:16:30 +0000 Subject: [PATCH 0025/1435] Properly use tags. Doesn't help though. --- src/stlink-sg.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 2c52e2a4c..8cf669388 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -244,6 +244,11 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint DLOG("Sending usb m-s cmd: cdblen:%d, rxsize=%d\n", cdb_length, expected_rx_size); dump_CDB_command(cdb, cdb_length); + static uint32_t tag; + if (tag == 0) { + tag = 1; + } + int try = 0; int ret = 0; int real_transferred; @@ -251,12 +256,12 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint uint8_t c_buf[STLINK_SG_SIZE]; // tag is allegedly ignored... TODO - verify - uint32_t tag = 1; c_buf[i++] = 'U'; c_buf[i++] = 'S'; c_buf[i++] = 'B'; c_buf[i++] = 'C'; write_uint32(&c_buf[i], tag); + uint32_t this_tag = tag++; write_uint32(&c_buf[i+4], expected_rx_size); i+= 8; c_buf[i++] = flags; @@ -286,7 +291,7 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint return -1; } DLOG("Actually sent: %d, returning tag: %d\n", real_transferred, tag); - return tag; + return this_tag; } @@ -338,6 +343,7 @@ static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t end static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_out) { + DLOG("Fetching sense...\n"); uint8_t cdb[16]; memset(cdb, 0, sizeof(cdb)); #define REQUEST_SENSE 0x03 @@ -382,12 +388,18 @@ get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_ou } } +int stlink_q2(stlink_t *sl, uint8_t cdb_len); int stlink_q(stlink_t *sl) { + return stlink_q2(sl, 10); +} + +int stlink_q2(stlink_t *sl, uint8_t cdb_len) { struct stlink_libsg* sg = sl->backend_data; //uint8_t cdb_len = 6; // FIXME varies!!! - uint8_t cdb_len = 10; // FIXME varies!!! + //uint8_t cdb_len = 10; // FIXME varies!!! uint8_t lun = 0; // always zero... - send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, cdb_len, lun, LIBUSB_ENDPOINT_IN, sl->q_len); + uint32_t tag = send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, + sg->cdb_cmd_blk, cdb_len, lun, LIBUSB_ENDPOINT_IN, sl->q_len); // now wait for our response... @@ -414,11 +426,7 @@ int stlink_q(stlink_t *sl) { if (real_transferred != rx_length) { WLOG("received unexpected amount: %d != %d\n", real_transferred, rx_length); } - - -// stm8 stuff... - - + uint32_t received_tag; // -ve is for my errors, 0 is good, +ve is libusb sense status bytes int status = get_usb_mass_storage_status(sg->usb_handle, sg->ep_rep, &received_tag); @@ -433,7 +441,6 @@ int stlink_q(stlink_t *sl) { get_sense(sg->usb_handle, sg->ep_rep, sg->ep_req); return -1; } - uint32_t tag = 1; if (received_tag != tag) { WLOG("received tag %d but expected %d\n", received_tag, tag); //return -1; @@ -1093,7 +1100,7 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { return NULL; } - DLOG("\n*** stlink_force_open ***\n"); + DLOG("Reading current mode...\n"); switch (stlink_current_mode(sl)) { case STLINK_DEV_MASS_MODE: return sl; @@ -1101,8 +1108,11 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { // TODO go to mass? return sl; } - DLOG("\n*** switch the stlink to mass mode ***\n"); + + DLOG("Attempting to exit DFU mode\n"); _stlink_sg_exit_dfu_mode(sl); + +#if 0 // exit the dfu mode -> the device is gone DLOG("\n*** reopen the stlink device ***\n"); delay(1000); @@ -1116,6 +1126,7 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { } // re-query device info stlink_version(sl); +#endif return sl; } From 87490393e86fffb812c12e871e31f970324fd677 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 23:24:28 +0000 Subject: [PATCH 0026/1435] Duh, don't try and do a bulk read when we requested 0 bytes back. --- src/stlink-sg.c | 42 +++++++++++++++++++----------------------- 1 file changed, 19 insertions(+), 23 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 8cf669388..2253212bd 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -388,15 +388,10 @@ get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_ou } } -int stlink_q2(stlink_t *sl, uint8_t cdb_len); int stlink_q(stlink_t *sl) { - return stlink_q2(sl, 10); -} - -int stlink_q2(stlink_t *sl, uint8_t cdb_len) { struct stlink_libsg* sg = sl->backend_data; //uint8_t cdb_len = 6; // FIXME varies!!! - //uint8_t cdb_len = 10; // FIXME varies!!! + uint8_t cdb_len = 10; // FIXME varies!!! uint8_t lun = 0; // always zero... uint32_t tag = send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, cdb_len, lun, LIBUSB_ENDPOINT_IN, sl->q_len); @@ -408,23 +403,25 @@ int stlink_q2(stlink_t *sl, uint8_t cdb_len) { int try = 0; int real_transferred; int ret; - do { - DLOG("attempting rx\n"); - ret = libusb_bulk_transfer(sg->usb_handle, sg->ep_rep, sl->q_buf, rx_length, - &real_transferred, SG_TIMEOUT_MSEC); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(sg->usb_handle, sg->ep_req); + if (rx_length > 0) { + do { + DLOG("attempting rx\n"); + ret = libusb_bulk_transfer(sg->usb_handle, sg->ep_rep, sl->q_buf, rx_length, + &real_transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(sg->usb_handle, sg->ep_req); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + + if (ret != LIBUSB_SUCCESS) { + WLOG("Receiving failed: %d\n", ret); + return -1; } - try++; - } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); - if (ret != LIBUSB_SUCCESS) { - WLOG("Receiving failed: %d\n", ret); - return -1; - } - - if (real_transferred != rx_length) { - WLOG("received unexpected amount: %d != %d\n", real_transferred, rx_length); + if (real_transferred != rx_length) { + WLOG("received unexpected amount: %d != %d\n", real_transferred, rx_length); + } } uint32_t received_tag; @@ -1112,13 +1109,13 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { DLOG("Attempting to exit DFU mode\n"); _stlink_sg_exit_dfu_mode(sl); -#if 0 // exit the dfu mode -> the device is gone DLOG("\n*** reopen the stlink device ***\n"); delay(1000); stlink_close(sl); delay(5000); + DLOG("Attempting to reopen the stlink...\n"); sl = stlink_open(dev_name, verbose); if (sl == NULL) { fputs("Error: could not open stlink device\n", stderr); @@ -1126,7 +1123,6 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { } // re-query device info stlink_version(sl); -#endif return sl; } From 0f376a74a51cf3e3134b0e6f2ad0415f43968ed1 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 Nov 2011 23:40:27 +0000 Subject: [PATCH 0027/1435] Remove device names, we now just find it via USB ids. In the future, we might actually want device names back again, if you have multiple stlink's connected. But that would be a new device name, not scanning for /dev/sgX looking for scsi devices. --- gdbserver/gdb-server.c | 38 ++------------------------------------ src/stlink-sg.c | 18 ++++++------------ src/stlink-sg.h | 3 ++- src/test_sg.c | 21 +++++++-------------- 4 files changed, 17 insertions(+), 63 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 65297bc0c..df3657a9b 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -197,42 +197,8 @@ int main(int argc, char** argv) { if(sl == NULL) return 1; break; case 1: - if (strlen(state.devicename) == 0) { - const int DevNumMax = 99; - int ExistDevCount = 0; - - for (int DevNum = 0; DevNum <= DevNumMax; DevNum++) { - if (DevNum < 10) { - char DevName[] = "/dev/sgX"; - const int X_index = 7; - DevName[X_index] = DevNum + '0'; - if (!access(DevName, F_OK)) { - sl = stlink_v1_open(DevName, 0); - ExistDevCount++; - } - } else if (DevNum < 100) { - char DevName[] = "/dev/sgXY"; - const int X_index = 7; - const int Y_index = 8; - DevName[X_index] = DevNum / 10 + '0'; - DevName[Y_index] = DevNum % 10 + '0'; - if (!access(DevName, F_OK)) { - sl = stlink_v1_open(DevName, 0); - ExistDevCount++; - } - } - if (sl != NULL) break; - } - - if (sl == NULL) { - fprintf(stdout, "\nNumber of /dev/sgX devices found: %i \n", - ExistDevCount); - fprintf(stderr, "ST-LINK not found\n"); - return 1; - } - } else { - sl = stlink_v1_open(state.devicename, state.logging_level); - } + sl = stlink_v1_open(NULL, state.logging_level); + if(sl == NULL) return 1; break; } diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 2253212bd..64f182022 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -967,8 +967,7 @@ stlink_backend_t _stlink_sg_backend = { _stlink_sg_force_debug }; -static stlink_t* stlink_open(const char *dev_name, const int verbose) { - DLOG("*** stlink_open [%s] ***\n", dev_name); +static stlink_t* stlink_open(const int verbose) { stlink_t *sl = malloc(sizeof (stlink_t)); struct stlink_libsg *slsg = malloc(sizeof (struct stlink_libsg)); @@ -1076,24 +1075,19 @@ static stlink_t* stlink_open(const char *dev_name, const int verbose) { -stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { +stlink_t* stlink_v1_open(const int verbose) { ugly_init(verbose); - stlink_t *sl = stlink_open(dev_name, verbose); + stlink_t *sl = stlink_open(verbose); if (sl == NULL) { fputs("Error: could not open stlink device\n", stderr); return NULL; } stlink_version(sl); - struct stlink_libsg *sg = sl->backend_data; if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { - fprintf(stderr, "Error: the device %s is not a stlink\n", - dev_name); - fprintf(stderr, " VID: got %04x expect %04x \n", - sl->version.st_vid, USB_ST_VID); - fprintf(stderr, " PID: got %04x expect %04x \n", - sl->version.stlink_pid, USB_STLINK_PID); + ugly_log(UERROR, LOG_TAG, + "WTF? successfully opened, but unable to read version details. BROKEN!\n"); return NULL; } @@ -1116,7 +1110,7 @@ stlink_t* stlink_v1_open(const char *dev_name, const int verbose) { delay(5000); DLOG("Attempting to reopen the stlink...\n"); - sl = stlink_open(dev_name, verbose); + sl = stlink_open(verbose); if (sl == NULL) { fputs("Error: could not open stlink device\n", stderr); return NULL; diff --git a/src/stlink-sg.h b/src/stlink-sg.h index 8485d3d88..d4d7723b8 100644 --- a/src/stlink-sg.h +++ b/src/stlink-sg.h @@ -57,12 +57,13 @@ extern "C" { uint32_t q_addr; // Sense (error information) data + // obsolete, this was fed to the scsi tools unsigned char sense_buf[SENSE_BUF_LEN]; reg reg; }; - stlink_t* stlink_v1_open(const char *dev_name, const int verbose); + stlink_t* stlink_v1_open(const int verbose); #ifdef __cplusplus } diff --git a/src/test_sg.c b/src/test_sg.c index 742ba4453..a8a7022c8 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -10,33 +10,26 @@ int main(int argc, char *argv[]) { // set scpi lib debug level: 0 for no debug info, 10 for lots - char *dev_name; switch (argc) { case 1: fputs( - "\nUsage: stlink-access-test /dev/sg0, sg1, ...\n" + "\nUsage: stlink-access-test [anything at all] ...\n" "\n*** Notice: The stlink firmware violates the USB standard.\n" - "*** If you plug-in the discovery's stlink, wait a several\n" - "*** minutes to let the kernel driver swallow the broken device.\n" - "*** Watch:\ntail -f /var/log/messages\n" - "*** This command sequence can shorten the waiting time and fix some issues.\n" + "*** Because we just use libusb, we can just tell the kernel's\n" + "*** driver to simply ignore the device...\n" "*** Unplug the stlink and execute once as root:\n" - "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:lrwsro\n\n", + "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n", stderr); return EXIT_FAILURE; - case 2: - dev_name = argv[1]; - break; default: - fprintf(stderr, "bzzt\n"); - return EXIT_FAILURE; + break; } - stlink_t *sl = stlink_v1_open(dev_name, 99); + stlink_t *sl = stlink_v1_open(99); if (sl == NULL) return EXIT_FAILURE; - + // we are in mass mode, go to swd stlink_enter_swd_mode(sl); stlink_current_mode(sl); From 8febc74cf1aeacdd57adff1eb85ea55f096ccaec Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 00:44:18 +0000 Subject: [PATCH 0028/1435] Fix write_mem32. Moved some of the static methods up to the top, so they can always be used, so the changes is messier than it needs to be. --- src/stlink-sg.c | 337 ++++++++++++++++++++++++++---------------------- src/test_sg.c | 41 ++++-- 2 files changed, 213 insertions(+), 165 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 64f182022..276986ef7 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -107,15 +107,6 @@ static void clear_cdb(struct stlink_libsg *sl) { sl->q_data_dir = Q_DATA_IN; } -// E.g. make the valgrind happy. - -static void clear_buf(stlink_t *sl) { - DLOG("*** clear_buf ***\n"); - for (size_t i = 0; i < sizeof (sl->q_buf); i++) - sl->q_buf[i] = 0; - -} - // close the device, free the allocated memory void _stlink_sg_close(stlink_t *sl) { @@ -128,92 +119,44 @@ void _stlink_sg_close(stlink_t *sl) { } } - -//TODO rewrite/cleanup, save the error in sl - -#if FINISHED_WITH_SG -static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { - struct stlink_libsg *sl = stl->backend_data; - const int e = sl->do_scsi_pt_err; - if (e < 0) { - fprintf(stderr, "scsi_pt error: pass through os error: %s\n", - safe_strerror(-e)); - return; - } else if (e == SCSI_PT_DO_BAD_PARAMS) { - fprintf(stderr, "scsi_pt error: bad pass through setup\n"); - return; - } else if (e == SCSI_PT_DO_TIMEOUT) { - fprintf(stderr, " pass through timeout\n"); - return; +static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, uint32_t *tag) +{ + unsigned char csw[13]; + memset(csw, 0, sizeof(csw)); + int transferred; + int ret; + int try = 0; + do { + ret = libusb_bulk_transfer(handle, endpoint, (unsigned char *)&csw, sizeof(csw), + &transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(handle, endpoint); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { + fprintf(stderr, "%s: receiving failed: %d\n", __func__, ret); + return -1; + } + if (transferred != sizeof(csw)) { + fprintf(stderr, "%s: received unexpected amount: %d\n", __func__, transferred); + return -1; } - const int duration = get_scsi_pt_duration_ms(ptvp); - if ((stl->verbose > 1) && (duration >= 0)) - DLOG(" duration=%d ms\n", duration); - - // XXX stlink fw sends broken residue, so ignore it and use the known q_len - // "usb-storage quirks=483:3744:r" - // forces residue to be ignored and calculated, but this causes aboard if - // data_len = 0 and by some other data_len values. - - const int resid = get_scsi_pt_resid(ptvp); - const int dsize = stl->q_len - resid; - - const int cat = get_scsi_pt_result_category(ptvp); - char buf[512]; - unsigned int slen; - switch (cat) { - case SCSI_PT_RESULT_GOOD: - if (stl->verbose && (resid > 0)) - DLOG(" notice: requested %d bytes but " - "got %d bytes, ignore [broken] residue = %d\n", - stl->q_len, dsize, resid); - break; - case SCSI_PT_RESULT_STATUS: - if (stl->verbose) { - sg_get_scsi_status_str( - get_scsi_pt_status_response(ptvp), sizeof (buf), - buf); - DLOG(" scsi status: %s\n", buf); - } - return; - case SCSI_PT_RESULT_SENSE: - slen = get_scsi_pt_sense_len(ptvp); - if (stl->verbose) { - sg_get_sense_str("", sl->sense_buf, slen, (stl->verbose - > 1), sizeof (buf), buf); - DLOG("%s", buf); - } - if (stl->verbose && (resid > 0)) { - if ((stl->verbose) || (stl->q_len > 0)) - DLOG(" requested %d bytes but " - "got %d bytes\n", stl->q_len, dsize); - } - return; - case SCSI_PT_RESULT_TRANSPORT_ERR: - if (stl->verbose) { - get_scsi_pt_transport_err_str(ptvp, sizeof (buf), buf); - // http://tldp.org/HOWTO/SCSI-Generic-HOWTO/x291.html - // These codes potentially come from the firmware on a host adapter - // or from one of several hosts that an adapter driver controls. - // The 'host_status' field has the following values: - // [0x07] Internal error detected in the host adapter. - // This may not be fatal (and the command may have succeeded). - DLOG(" transport: %s", buf); - } - return; - case SCSI_PT_RESULT_OS_ERR: - if (stl->verbose) { - get_scsi_pt_os_err_str(ptvp, sizeof (buf), buf); - DLOG(" os: %s", buf); - } - return; - default: - fprintf(stderr, " unknown pass through result " - "category (%d)\n", cat); + uint32_t rsig = read_uint32(csw, 0); + uint32_t rtag = read_uint32(csw, 4); + uint32_t residue = read_uint32(csw, 8); +#define USB_CSW_SIGNATURE 0x53425355 // 'U' 'S' 'B' 'S' (reversed) + if (rsig != USB_CSW_SIGNATURE) { + WLOG("status signature was invalid: %#x\n", rsig); + return -1; } + DLOG("residue was= %#x\n", residue); + *tag = rtag; + uint8_t rstatus = csw[12]; + DLOG("rstatus = %x\n", rstatus); + return rstatus; } -#endif static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { char dbugblah[100]; @@ -295,45 +238,6 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint } -static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, uint32_t *tag) -{ - unsigned char csw[13]; - memset(csw, 0, sizeof(csw)); - int transferred; - int ret; - int try = 0; - do { - ret = libusb_bulk_transfer(handle, endpoint, (unsigned char *)&csw, sizeof(csw), - &transferred, SG_TIMEOUT_MSEC); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(handle, endpoint); - } - try++; - } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); - if (ret != LIBUSB_SUCCESS) { - fprintf(stderr, "%s: receiving failed: %d\n", __func__, ret); - return -1; - } - if (transferred != sizeof(csw)) { - fprintf(stderr, "%s: received unexpected amount: %d\n", __func__, transferred); - return -1; - } - - uint32_t rsig = read_uint32(csw, 0); - uint32_t rtag = read_uint32(csw, 4); - uint32_t residue = read_uint32(csw, 8); -#define USB_CSW_SIGNATURE 0x53425355 // 'U' 'S' 'B' 'S' (reversed) - if (rsig != USB_CSW_SIGNATURE) { - WLOG("status signature was invalid: %#x\n", rsig); - return -1; - } - DLOG("residue was= %#x\n", residue); - *tag = rtag; - uint8_t rstatus = csw[12]; - DLOG("rstatus = %x\n", rstatus); - return rstatus; -} - /** * Straight from stm8 stlink code... * @param handle @@ -388,6 +292,143 @@ get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_ou } } + +//TODO rewrite/cleanup, save the error in sl + +#if FINISHED_WITH_SG +static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { + struct stlink_libsg *sl = stl->backend_data; + const int e = sl->do_scsi_pt_err; + if (e < 0) { + fprintf(stderr, "scsi_pt error: pass through os error: %s\n", + safe_strerror(-e)); + return; + } else if (e == SCSI_PT_DO_BAD_PARAMS) { + fprintf(stderr, "scsi_pt error: bad pass through setup\n"); + return; + } else if (e == SCSI_PT_DO_TIMEOUT) { + fprintf(stderr, " pass through timeout\n"); + return; + } + const int duration = get_scsi_pt_duration_ms(ptvp); + if ((stl->verbose > 1) && (duration >= 0)) + DLOG(" duration=%d ms\n", duration); + + // XXX stlink fw sends broken residue, so ignore it and use the known q_len + // "usb-storage quirks=483:3744:r" + // forces residue to be ignored and calculated, but this causes aboard if + // data_len = 0 and by some other data_len values. + + const int resid = get_scsi_pt_resid(ptvp); + const int dsize = stl->q_len - resid; + + const int cat = get_scsi_pt_result_category(ptvp); + char buf[512]; + unsigned int slen; + + switch (cat) { + case SCSI_PT_RESULT_GOOD: + if (stl->verbose && (resid > 0)) + DLOG(" notice: requested %d bytes but " + "got %d bytes, ignore [broken] residue = %d\n", + stl->q_len, dsize, resid); + break; + case SCSI_PT_RESULT_STATUS: + if (stl->verbose) { + sg_get_scsi_status_str( + get_scsi_pt_status_response(ptvp), sizeof (buf), + buf); + DLOG(" scsi status: %s\n", buf); + } + return; + case SCSI_PT_RESULT_SENSE: + slen = get_scsi_pt_sense_len(ptvp); + if (stl->verbose) { + sg_get_sense_str("", sl->sense_buf, slen, (stl->verbose + > 1), sizeof (buf), buf); + DLOG("%s", buf); + } + if (stl->verbose && (resid > 0)) { + if ((stl->verbose) || (stl->q_len > 0)) + DLOG(" requested %d bytes but " + "got %d bytes\n", stl->q_len, dsize); + } + return; + case SCSI_PT_RESULT_TRANSPORT_ERR: + if (stl->verbose) { + get_scsi_pt_transport_err_str(ptvp, sizeof (buf), buf); + // http://tldp.org/HOWTO/SCSI-Generic-HOWTO/x291.html + // These codes potentially come from the firmware on a host adapter + // or from one of several hosts that an adapter driver controls. + // The 'host_status' field has the following values: + // [0x07] Internal error detected in the host adapter. + // This may not be fatal (and the command may have succeeded). + DLOG(" transport: %s", buf); + } + return; + case SCSI_PT_RESULT_OS_ERR: + if (stl->verbose) { + get_scsi_pt_os_err_str(ptvp, sizeof (buf), buf); + DLOG(" os: %s", buf); + } + return; + default: + fprintf(stderr, " unknown pass through result " + "category (%d)\n", cat); + } +} +#endif + +/** + * Just send a buffer on an endpoint, no questions asked. + * Handles repeats, and time outs. Also handles reading status reports and sense + * @param handle libusb device * + * @param endpoint_out sends + * @param endpoint_in used to read status reports back in + * @param cbuf what to send + * @param length how much to send + * @return number of bytes actually sent, or -1 for failures. + */ +int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, + unsigned char endpoint_in, unsigned char *cbuf, unsigned int length) { + int ret; + int real_transferred; + int try; + do { + DLOG("attempting tx...\n"); + ret = libusb_bulk_transfer(handle, endpoint_out, cbuf, length, + &real_transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { + libusb_clear_halt(handle, endpoint_out); + } + try++; + } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { + WLOG("sending failed: %d\n", ret); + return -1; + } + DLOG("Actually sent: %d\n", real_transferred); + + // now, swallow up the status, so that things behave nicely... + uint32_t received_tag; + // -ve is for my errors, 0 is good, +ve is libusb sense status bytes + int status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); + if (status < 0) { + WLOG("receiving status failed: %d\n", status); + return -1; + } + if (status != 0) { + WLOG("receiving status not passed :(: %02x\n", status); + } + if (status == 1) { + get_sense(handle, endpoint_in, endpoint_out); + return -1; + } + + return real_transferred; +} + + int stlink_q(stlink_t *sl) { struct stlink_libsg* sg = sl->backend_data; //uint8_t cdb_len = 6; // FIXME varies!!! @@ -865,11 +906,10 @@ void _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint32(sg->cdb_cmd_blk + 2, addr); write_uint16(sg->cdb_cmd_blk + 6, len); - // data_out 0-len - sl->q_len = len; - sg->q_addr = addr; - sg->q_data_dir = Q_DATA_OUT; - stlink_q(sl); + // this sends the command... + send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); + // This sends the data... + send_usb_data_only(sg->usb_handle, sg->ep_req, sg->ep_rep, sl->q_buf, len); stlink_print_data(sl); } @@ -884,11 +924,11 @@ void _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint32(sg->cdb_cmd_blk + 2, addr); write_uint16(sg->cdb_cmd_blk + 6, len); - // data_out 0-0x40-...-len - sl->q_len = len; - sg->q_addr = addr; - sg->q_data_dir = Q_DATA_OUT; - stlink_q(sl); + // this sends the command... + send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); + // This sends the data... + send_usb_data_only(sg->usb_handle, sg->ep_req, sg->ep_rep, sl->q_buf, len); + stlink_print_data(sl); } @@ -970,6 +1010,7 @@ stlink_backend_t _stlink_sg_backend = { static stlink_t* stlink_open(const int verbose) { stlink_t *sl = malloc(sizeof (stlink_t)); + memset(sl, 0, sizeof(stlink_t)); struct stlink_libsg *slsg = malloc(sizeof (struct stlink_libsg)); if (sl == NULL || slsg == NULL) { WLOG("Couldn't malloc stlink and stlink_sg structures out of memory!\n"); @@ -1055,7 +1096,6 @@ static stlink_t* stlink_open(const int verbose) { sl->core_stat = STLINK_CORE_STAT_UNKNOWN; slsg->q_addr = 0; - clear_buf(sl); /* flash memory settings */ sl->flash_base = STM32_FLASH_BASE; @@ -1119,18 +1159,3 @@ stlink_t* stlink_v1_open(const int verbose) { stlink_version(sl); return sl; } - -static void __attribute__((unused)) mark_buf(stlink_t *sl) { - clear_buf(sl); - sl->q_buf[0] = 0x12; - sl->q_buf[1] = 0x34; - sl->q_buf[2] = 0x56; - sl->q_buf[3] = 0x78; - sl->q_buf[4] = 0x90; - sl->q_buf[15] = 0x42; - sl->q_buf[16] = 0x43; - sl->q_buf[63] = 0x42; - sl->q_buf[64] = 0x43; - sl->q_buf[1024 * 6 - 1] = 0x42; //6kB - sl->q_buf[1024 * 8 - 1] = 0x42; //8kB -} diff --git a/src/test_sg.c b/src/test_sg.c index a8a7022c8..d9e560c23 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -6,7 +6,31 @@ #include #include +#include #include "stlink-common.h" +#include "uglylogging.h" + +#define LOG_TAG __FILE__ +#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) +#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) +#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) +#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) + +static void __attribute__((unused)) mark_buf(stlink_t *sl) { + memset(sl->q_buf, 0, sizeof(sl->q_buf)); + sl->q_buf[0] = 0xaa; + sl->q_buf[1] = 0xbb; + sl->q_buf[2] = 0xcc; + sl->q_buf[3] = 0xdd; + sl->q_buf[4] = 0x11; + sl->q_buf[15] = 0x22; + sl->q_buf[16] = 0x33; + sl->q_buf[63] = 0x44; + sl->q_buf[64] = 0x69; + sl->q_buf[1024 * 6 - 1] = 0x42; //6kB + sl->q_buf[1024 * 8 - 1] = 0x42; //8kB +} + int main(int argc, char *argv[]) { // set scpi lib debug level: 0 for no debug info, 10 for lots @@ -40,14 +64,14 @@ int main(int argc, char *argv[]) { //stlink_force_debug(sl); stlink_reset(sl); stlink_status(sl); -#if 0 // core system control block stlink_read_mem32(sl, 0xe000ed00, 4); - DD(sl, "cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231", read_uint32(sl->q_buf, 0)); + DLOG("cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231\n", read_uint32(sl->q_buf, 0)); // no MPU stlink_read_mem32(sl, 0xe000ed90, 4); - DD(sl, "mpu type register: MPU_TYPER = got 0x%08x expect 0x0", read_uint32(sl->q_buf, 0)); + DLOG("mpu type register: MPU_TYPER = got 0x%08x expect 0x0\n", read_uint32(sl->q_buf, 0)); +#if 0 stlink_read_mem32(sl, 0xe000edf0, 4); DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0)); @@ -105,10 +129,10 @@ int main(int argc, char *argv[]) { #if 0 // sram 0x20000000 8kB fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); - clear_buf(sl); + memset(sl->q_buf, 0, sizeof(sl->q_buf)); + mark_buf(sl); stlink_write_mem8(sl, 0x20000000, 16); - mark_buf(sl); stlink_write_mem8(sl, 0x20000000, 1); stlink_write_mem8(sl, 0x20000001, 1); stlink_write_mem8(sl, 0x2000000b, 3); @@ -117,9 +141,7 @@ int main(int argc, char *argv[]) { #if 0 // a not aligned mem32 access doesn't work indeed fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); - clear_buf(sl); - stlink_write_mem8(sl, 0x20000000, 32); - + memset(sl->q_buf, 0, sizeof(sl->q_buf)); mark_buf(sl); stlink_write_mem32(sl, 0x20000000, 1); stlink_read_mem32(sl, 0x20000000, 16); @@ -134,9 +156,10 @@ int main(int argc, char *argv[]) { stlink_write_mem32(sl, 0x20000000, 17); stlink_read_mem32(sl, 0x20000000, 32); #endif -#if 0 +#if 1 // sram 0x20000000 8kB fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr); + memset(sl->q_buf, 0, sizeof(sl->q_buf)); mark_buf(sl); stlink_write_mem8(sl, 0x20000000, 64); stlink_read_mem32(sl, 0x20000000, 64); From 2dc7d9f4ec376f9c53dbb9a0413a0b0161378d0a Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 00:51:30 +0000 Subject: [PATCH 0029/1435] write_mem8 works too. I just misinterpreted the test results earlier. --- src/test_sg.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/test_sg.c b/src/test_sg.c index d9e560c23..19a2ef510 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -126,15 +126,15 @@ int main(int argc, char *argv[]) { stlink_read_mem32(sl, 0x08000c00, 256); stlink_read_mem32(sl, 0x08000c00, 256); #endif -#if 0 +#if 1 // sram 0x20000000 8kB fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); memset(sl->q_buf, 0, sizeof(sl->q_buf)); mark_buf(sl); - stlink_write_mem8(sl, 0x20000000, 16); + //stlink_write_mem8(sl, 0x20000000, 16); - stlink_write_mem8(sl, 0x20000000, 1); - stlink_write_mem8(sl, 0x20000001, 1); + //stlink_write_mem8(sl, 0x20000000, 1); + //stlink_write_mem8(sl, 0x20000001, 1); stlink_write_mem8(sl, 0x2000000b, 3); stlink_read_mem32(sl, 0x20000000, 16); #endif @@ -156,7 +156,7 @@ int main(int argc, char *argv[]) { stlink_write_mem32(sl, 0x20000000, 17); stlink_read_mem32(sl, 0x20000000, 32); #endif -#if 1 +#if 0 // sram 0x20000000 8kB fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr); memset(sl->q_buf, 0, sizeof(sl->q_buf)); From 8c7b98a4cbd9848dbd029e02f367ef7b1289044a Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 00:54:01 +0000 Subject: [PATCH 0030/1435] blinking LEDs via stlink also works --- src/test_sg.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/test_sg.c b/src/test_sg.c index 19a2ef510..899efc3a9 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -78,7 +78,7 @@ int main(int argc, char *argv[]) { stlink_read_mem32(sl, 0x4001100c, 4); DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); #endif -#if 0 +#if 1 // happy new year 2011: let blink all the leds // see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs" @@ -89,23 +89,23 @@ int main(int argc, char *argv[]) { #define LED_GREEN (1<<9) // pin 9 stlink_read_mem32(sl, GPIOC_CRH, 4); uint32_t io_conf = read_uint32(sl->q_buf, 0); - DD(sl, "GPIOC_CRH = 0x%08x", io_conf); + DLOG("GPIOC_CRH = 0x%08x\n", io_conf); // set: general purpose output push-pull, output mode, max speed 10 MHz. write_uint32(sl->q_buf, 0x44444411); stlink_write_mem32(sl, GPIOC_CRH, 4); - clear_buf(sl); + memset(sl->q_buf, 0, sizeof(sl->q_buf)); for (int i = 0; i < 100; i++) { write_uint32(sl->q_buf, LED_BLUE | LED_GREEN); stlink_write_mem32(sl, GPIOC_ODR, 4); /* stlink_read_mem32(sl, 0x4001100c, 4); */ /* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */ - delay(100); + usleep(100 * 1000); - clear_buf(sl); + memset(sl->q_buf, 0, sizeof(sl->q_buf)); stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo - delay(100); + usleep(100 * 1000); } write_uint32(sl->q_buf, io_conf); // set old state @@ -126,7 +126,7 @@ int main(int argc, char *argv[]) { stlink_read_mem32(sl, 0x08000c00, 256); stlink_read_mem32(sl, 0x08000c00, 256); #endif -#if 1 +#if 0 // sram 0x20000000 8kB fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); memset(sl->q_buf, 0, sizeof(sl->q_buf)); From a19abbb547116f343c5dcb2b3a6d0f6d1d457dae Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 00:56:50 +0000 Subject: [PATCH 0031/1435] Writing registers works too --- src/test_sg.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/test_sg.c b/src/test_sg.c index 899efc3a9..357f43665 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -78,7 +78,7 @@ int main(int argc, char *argv[]) { stlink_read_mem32(sl, 0x4001100c, 4); DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); #endif -#if 1 +#if 0 // happy new year 2011: let blink all the leds // see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs" @@ -169,13 +169,14 @@ int main(int argc, char *argv[]) { stlink_read_mem32(sl, 0x20000000, 1024 * 6); stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2); #endif -#if 0 - stlink_read_all_regs(sl); +#if 1 + reg regs; + stlink_read_all_regs(sl, ®s); stlink_step(sl); fputs("++++++++++ write r0 = 0x12345678\n", stderr); stlink_write_reg(sl, 0x12345678, 0); - stlink_read_reg(sl, 0); - stlink_read_all_regs(sl); + stlink_read_reg(sl, 0, ®s); + stlink_read_all_regs(sl, ®s); #endif #if 0 stlink_run(sl); From fd5967fba684bb0f4d83b0b72559da8021e1c995 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 01:05:27 +0000 Subject: [PATCH 0032/1435] Fix compilation error after removing devices. --- gdbserver/gdb-server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index df3657a9b..bcb3c974b 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -197,7 +197,7 @@ int main(int argc, char** argv) { if(sl == NULL) return 1; break; case 1: - sl = stlink_v1_open(NULL, state.logging_level); + sl = stlink_v1_open(state.logging_level); if(sl == NULL) return 1; break; } From 3dd1addf929f95e05fa676bab5a41515e990e16a Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 01:05:54 +0000 Subject: [PATCH 0033/1435] Update netbeans project files. --- nbproject/configurations.xml | 355 ++++++++++++++++++++++++++++++++++- nbproject/project.xml | 4 + 2 files changed, 355 insertions(+), 4 deletions(-) diff --git a/nbproject/configurations.xml b/nbproject/configurations.xml index 567946524..47cfb040a 100644 --- a/nbproject/configurations.xml +++ b/nbproject/configurations.xml @@ -117,6 +117,8 @@ stlink-usb.h test_sg.c test_usb.c + uglylogging.c + uglylogging.h @@ -153,9 +155,11 @@ ${MAKE} -f Makefile clean gdbserver/st-util + + . + - CONFIG_USE_LIBSG=1 - CONFIG_USE_LIBUSB=1 + DEBUG=1 @@ -473,6 +477,351 @@ src + + CONFIG_USE_LIBSG=1 + CONFIG_USE_LIBUSB=1 + + + + + + + + + + + + + + + LOCAL_SOURCES + default + + + + gdbserver + ${MAKE} -f Makefile + ${MAKE} -f Makefile clean + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + src + + + CONFIG_USE_LIBSG=1 + CONFIG_USE_LIBUSB=1 + @@ -487,8 +836,6 @@ - - diff --git a/nbproject/project.xml b/nbproject/project.xml index cd5248661..580df1074 100644 --- a/nbproject/project.xml +++ b/nbproject/project.xml @@ -17,6 +17,10 @@ Default 0 + + gdbserver + 0 + From b463d50c5b34935334b26a48903c68c3893b1ff2 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 01:56:22 +0000 Subject: [PATCH 0034/1435] Update documentation removing all sg-utils notes Just libusb now. Verified the modprobe.conf on Ubuntu 10.04 --- 10-stlink.rules | 43 ----------------------------------- README | 50 +++++++++++++++++++++++++++++++---------- TODO | 3 --- src/stlink-sg.c | 24 ++++++++++++-------- stlink.modprobe.conf | 1 - stlink_v1.modprobe.conf | 1 + 6 files changed, 54 insertions(+), 68 deletions(-) delete mode 100644 10-stlink.rules delete mode 100644 stlink.modprobe.conf create mode 100644 stlink_v1.modprobe.conf diff --git a/10-stlink.rules b/10-stlink.rules deleted file mode 100644 index 2413acd8e..000000000 --- a/10-stlink.rules +++ /dev/null @@ -1,43 +0,0 @@ -# This file was taken from arm-utilites project, located at -# http://code.google.com/p/arm-utilities/, which is licensed under GPL3. -# An explicit permission to include any code from that project in -# this one under BSD license was granted by arm-utilites author, Donald Becker. - -# This file watches for a STMicro ST-Link or STM32VLDiscovery board -# and creates a device named /dev/stlink -# See udev(7) for syntax. -# -# Written 2010,2011 by Donald Becker -# -# The STLink on the Discovery has a USB ID 0483:3744 and presents itself -# as a mass storage (i.e. SCSI) device. The SCSI emulation is signficantly -# broken, and the kernel spews error reports for a while until it is -# accepted. Further problems are encountered when if it is automatically -# mounted. -# -# Options that may prevent the mount are -# ENV{UDISKS_PRESENTATION_HIDE}:="1", -# ENV{UDISKS_PRESENTATION_NOPOLICY}:="1", -# ENV{DM_UDEV_DISABLE_DISK_RULES_FLAG}:="1" - -ACTION!="add|change", GOTO="stlink_rules_end" - -SUBSYSTEMS=="usb", ATTR{idVendor}=="0483", ATTR{idProduct}=="3744", \ - MODE="0664", GROUP="tape", NAME="stlinkusb%n", ENV{STLINK}="1", \ - ENV{UDISKS_PRESENTATION_HIDE}:="1", \ - ENV{UDISKS_PRESENTATION_NOPOLICY}:="1", \ - ENV{DM_UDEV_DISABLE_DISK_RULES_FLAG}:="1", \ - OPTIONS="last_rule" - -# Other possible settings: -# OPTIONS="last_rule", ATTRS{vendor}=="STM32" - -KERNEL=="sg[0-9]*", MODE="0664", GROUP:="tape", \ - NAME+="stlink-sg%n", SYMLINK+="stlink", \ - ENV{UDISKS_PRESENTATION_HIDE}:="1", \ - ENV{UDISKS_PRESENTATION_NOPOLICY}:="1", \ - ENV{DM_UDEV_DISABLE_DISK_RULES_FLAG}:="1" - -SUBSYSTEM=="scsi", ATTR{vendor}=="STM32", MODE="0664", GROUP="tape", NAME="stlinksg-scsi%n", SYMLINK+="stlinkscsi", OPTIONS="last_rule" - -LABEL="stlink_rules_end" diff --git a/README b/README index 429b8511f..109aa2500 100644 --- a/README +++ b/README @@ -11,22 +11,47 @@ called stlink and there are 2 versions: . STLINKv1 uses SCSI passthru commands over USB, . STLINKv2 uses raw USB commands. -It means that if you are using a STM32VL board, you have to install and load -SCSI related software. First, load the sg kernel module: -# modprobe sg +Common requirements +~~~~~~~~~~~~~~~~~~~ -Then, you need to install the package libsgutils2-dev. On Ubuntu: -# sudo apt-get install libsgutils2-dev +libusb-1.0 (You probably already have this, but you'll need the +development version to compile) -LIBUSB is required for both cases. +IF YOU HAVE AN STLINKv1 +~~~~~~~~~~~~~~~~~~~~~~~ +The STLINKv1's SCSI emulation is very broken, so the best thing to do +is tell your operating system to completely ignore it. + +Options (do one of these before you plug it in) + *) modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i +or *)1. add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf + *)2. modprobe -r usb-storage && modprobe usb-storage +or *)1. cp stlink_v1.modprobe.conf /etc/modprobe.d + *)2. modprobe -r usb-storage && modprobe usb-storage + +IF YOU HAVE AN STLINKv2 +~~~~~~~~~~~~~~~~~~~~~~~ + +You're ready to go :) To run the gdb server, do (you do not need sudo if you have set up permissions correctly): -$ make -C build && sudo ./build/st-util [/dev/sgX] +$ make && [sudo] ./gdbserver/st-util + +There are a few options: + +./gdbserver/st-util - usage: -Currently, the GDB server listening port is hardcoded to 4242: + -h, --help Print this help + -vXX, --verbose=XX specify a specific verbosity level (0..99) + -v, --verbose specify generally verbose logging + -s X, --stlink_version=X + Choose what version of stlink to use, (defaults to 2) + -1, --stlinkv1 Force stlink version 1 + -p 4242, --listen_port=1234 + Set the gdb server listen port. (default port: 4242) -Then, in gdb: +Then, in gdb: (remember, you need to run an _ARM_ gdb, not an x86 gdb) (gdb) target remote :4242 Have fun! @@ -50,13 +75,14 @@ for GDB. Setting up udev rules ===================== -For convenience, you may install udev rules file, 10-stlink.rules, located +For convenience, you may install udev rules file, 49-stlinkv2.rules, located in the root of repository. You will need to copy it to /etc/udev/rules.d, and then either reboot or execute $ udevadm control --reload-rules -Udev will now create a /dev/stlink file, which will point at appropriate -/dev/sgX device. Good to not accidentally start debugging your flash drive. +Udev will now create a /dev/stlinkv2_XX file, with the appropriate permissions. +This is currently all the device is for, (only one stlinkv2 is supported at +any time presently) Running programs from SRAM ========================== diff --git a/TODO b/TODO index e3795fc32..e415e57b8 100644 --- a/TODO +++ b/TODO @@ -7,9 +7,6 @@ . documentation . make README points to doc/tutorial -. remove libsg dependency using: -https://github.com/afaerber/stlink/tree/master/libstlink - . compile and test a realtime kernel, for instance: http://www.chibios.org/dokuwiki/doku.php?id=chibios:articles:stm32l_discovery svn checkout https://chibios.svn.sourceforge.net/svnroot/chibios/trunk ; diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 276986ef7..2bbbaf9d9 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -12,7 +12,6 @@ The stlink related constants kindly provided by Oliver Spencer (OpenOCD) for use in a GPL compatible license. - Code format ~ TAB = 8, K&R, linux kernel source, golang oriented Tested compatibility: linux, gcc >= 4.3.3 The communication is based on standard USB mass storage device @@ -31,10 +30,18 @@ CBW - Command Block Wrapper CSW - Command Status Wrapper RFU - Reserved for Future Use - scsi_pt - SCSI pass-through - sg - SCSI generic - * usb-storage.quirks + Originally, this driver used scsi pass through commands, which required the + usb-storage module to be loaded, providing the /dev/sgX links. The USB mass + storage implementation on the STLinkv1 is however terribly broken, and it can + take many minutes for the kernel to give up. + + However, in Nov 2011, the scsi pass through was replaced by raw libusb, so + instead of having to let usb-storage struggle with the device, and also greatly + limiting the portability of the driver, you can now tell usb-storage to simply + ignore this device completely. + + usb-storage.quirks http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob_plain;f=Documentation/kernel-parameters.txt Each entry has the form VID:PID:Flags where VID and PID are Vendor and Product ID values (4-digit hex numbers) and Flags is a set of characters, each corresponding @@ -54,18 +61,17 @@ Example: quirks=0419:aaf5:rl,0421:0433:rc http://permalink.gmane.org/gmane.linux.usb.general/35053 + + For the stlinkv1, you just want the following - modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:l + modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i Equivalently, you can add a line saying - options usb-storage quirks=483:3744:l + options usb-storage quirks=483:3744:i to your /etc/modprobe.conf or /etc/modprobe.d/local.conf (or add the "quirks=..." part to an existing options line for usb-storage). - - https://wiki.kubuntu.org/Kernel/Debugging/USB explains the protocoll and - would allow to replace the sg access to pure libusb access */ diff --git a/stlink.modprobe.conf b/stlink.modprobe.conf deleted file mode 100644 index e918c9006..000000000 --- a/stlink.modprobe.conf +++ /dev/null @@ -1 +0,0 @@ -options usb-storage quirks=483:3744:l diff --git a/stlink_v1.modprobe.conf b/stlink_v1.modprobe.conf new file mode 100644 index 000000000..94b3786ff --- /dev/null +++ b/stlink_v1.modprobe.conf @@ -0,0 +1 @@ +options usb-storage quirks=483:3744:i From 388606716eb050914a5c3af08a8ccf669f1c85a9 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 02:23:17 +0000 Subject: [PATCH 0035/1435] Update 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© COPYRIGHT 2010 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x + * @{ + */ + +#ifndef __STM32F10x_H +#define __STM32F10x_H + +#ifdef __cplusplus + extern "C" { +#endif + +#define assert_param(__p) + + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target STM32 device used in your + application + */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) + /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ + /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ + /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ + /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ + /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ + #define STM32F10X_XL /*!< STM32F10X_XL: STM32 XL-density devices */ + /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ +#endif +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + + - Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 16 and 32 Kbytes. + - Low-density value line devices are STM32F100xx microcontrollers where the Flash + memory density ranges between 16 and 32 Kbytes. + - Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers + where the Flash memory density ranges between 64 and 128 Kbytes. + - Medium-density value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 64 and 128 Kbytes. + - High density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 256 and 512 Kbytes. + - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 512 and 1024 Kbytes. + - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. + */ + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_STDPERIPH_DRIVER*/ +#endif + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined HSE_VALUE + #ifdef STM32F10X_CL + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ + #else + #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ + #endif /* STM32F10X_CL */ +#endif /* HSE_VALUE */ + + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ + +/** + * @brief STM32F10x Standard Peripheral Library version number + */ +#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x03) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */ +#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */ +#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\ + | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\ + | __STM32F10X_STDPERIPH_VERSION_SUB2) + +/** + * @} + */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M3 Processor and Core Peripherals + */ +#ifdef STM32F10X_XL + #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ +#else + #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ +#endif /* STM32F10X_XL */ +#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @brief STM32F10x Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ + +/****** STM32 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 2, /*!< Tamper Interrupt */ + RTC_IRQn = 3, /*!< RTC global Interrupt */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ + +#ifdef STM32F10X_LD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_LD */ + +#ifdef STM32F10X_LD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_LD_VL */ + +#ifdef STM32F10X_MD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ +#endif /* STM32F10X_MD */ + +#ifdef STM32F10X_MD_VL + ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ + TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ + TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ + TIM7_IRQn = 55 /*!< TIM7 Interrupt */ +#endif /* STM32F10X_MD_VL */ + +#ifdef STM32F10X_HD + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ + TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_HD */ + +#ifdef STM32F10X_XL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ +#endif /* STM32F10X_XL */ + +#ifdef STM32F10X_CL + ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ + CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ + CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ + TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ + TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ +#endif /* STM32F10X_CL */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm3.h" +#include "system_stm32f10x.h" +#include + +/** @addtogroup Exported_types + * @{ + */ + +/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /*!< Read Only */ +typedef const int16_t sc16; /*!< Read Only */ +typedef const int8_t sc8; /*!< Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /*!< Read Only */ +typedef __I int16_t vsc16; /*!< Read Only */ +typedef __I int8_t vsc8; /*!< Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /*!< Read Only */ +typedef const uint16_t uc16; /*!< Read Only */ +typedef const uint8_t uc8; /*!< Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /*!< Read Only */ +typedef __I uint16_t vuc16; /*!< Read Only */ +typedef __I uint8_t vuc8; /*!< Read Only */ + +#ifndef __cplusplus +typedef enum {FALSE = 0, TRUE = !FALSE} bool; +#endif + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT +#define HSE_Value HSE_VALUE +#define HSI_Value HSI_VALUE +/** + * @} + */ + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t SMPR1; + __IO uint32_t SMPR2; + __IO uint32_t JOFR1; + __IO uint32_t JOFR2; + __IO uint32_t JOFR3; + __IO uint32_t JOFR4; + __IO uint32_t HTR; + __IO uint32_t LTR; + __IO uint32_t SQR1; + __IO uint32_t SQR2; + __IO uint32_t SQR3; + __IO uint32_t JSQR; + __IO uint32_t JDR1; + __IO uint32_t JDR2; + __IO uint32_t JDR3; + __IO uint32_t JDR4; + __IO uint32_t DR; +} ADC_TypeDef; + +/** + * @brief Backup Registers + */ + +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DR1; + uint16_t RESERVED1; + __IO uint16_t DR2; + uint16_t RESERVED2; + __IO uint16_t DR3; + uint16_t RESERVED3; + __IO uint16_t DR4; + uint16_t RESERVED4; + __IO uint16_t DR5; + uint16_t RESERVED5; + __IO uint16_t DR6; + uint16_t RESERVED6; + __IO uint16_t DR7; + uint16_t RESERVED7; + __IO uint16_t DR8; + uint16_t RESERVED8; + __IO uint16_t DR9; + uint16_t RESERVED9; + __IO uint16_t DR10; + uint16_t RESERVED10; + __IO uint16_t RTCCR; + uint16_t RESERVED11; + __IO uint16_t CR; + uint16_t RESERVED12; + __IO uint16_t CSR; + uint16_t RESERVED13[5]; + __IO uint16_t DR11; + uint16_t RESERVED14; + __IO uint16_t DR12; + uint16_t RESERVED15; + __IO uint16_t DR13; + uint16_t RESERVED16; + __IO uint16_t DR14; + uint16_t RESERVED17; + __IO uint16_t DR15; + uint16_t RESERVED18; + __IO uint16_t DR16; + uint16_t RESERVED19; + __IO uint16_t DR17; + uint16_t RESERVED20; + __IO uint16_t DR18; + uint16_t RESERVED21; + __IO uint16_t DR19; + uint16_t RESERVED22; + __IO uint16_t DR20; + uint16_t RESERVED23; + __IO uint16_t DR21; + uint16_t RESERVED24; + __IO uint16_t DR22; + uint16_t RESERVED25; + __IO uint16_t DR23; + uint16_t RESERVED26; + __IO uint16_t DR24; + uint16_t RESERVED27; + __IO uint16_t DR25; + uint16_t RESERVED28; + __IO uint16_t DR26; + uint16_t RESERVED29; + __IO uint16_t DR27; + uint16_t RESERVED30; + __IO uint16_t DR28; + uint16_t RESERVED31; + __IO uint16_t DR29; + uint16_t RESERVED32; + __IO uint16_t DR30; + uint16_t RESERVED33; + __IO uint16_t DR31; + uint16_t RESERVED34; + __IO uint16_t DR32; + uint16_t RESERVED35; + __IO uint16_t DR33; + uint16_t RESERVED36; + __IO uint16_t DR34; + uint16_t RESERVED37; + __IO uint16_t DR35; + uint16_t RESERVED38; + __IO uint16_t DR36; + uint16_t RESERVED39; + __IO uint16_t DR37; + uint16_t RESERVED40; + __IO uint16_t DR38; + uint16_t RESERVED41; + __IO uint16_t DR39; + uint16_t RESERVED42; + __IO uint16_t DR40; + uint16_t RESERVED43; + __IO uint16_t DR41; + uint16_t RESERVED44; + __IO uint16_t DR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; + __IO uint32_t TDTR; + __IO uint32_t TDLR; + __IO uint32_t TDHR; +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; + __IO uint32_t RDTR; + __IO uint32_t RDLR; + __IO uint32_t RDHR; +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; + __IO uint32_t MSR; + __IO uint32_t TSR; + __IO uint32_t RF0R; + __IO uint32_t RF1R; + __IO uint32_t IER; + __IO uint32_t ESR; + __IO uint32_t BTR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FMR; + __IO uint32_t FM1R; + uint32_t RESERVED2; + __IO uint32_t FS1R; + uint32_t RESERVED3; + __IO uint32_t FFA1R; + uint32_t RESERVED4; + __IO uint32_t FA1R; + uint32_t RESERVED5[8]; +#ifndef STM32F10X_CL + CAN_FilterRegister_TypeDef sFilterRegister[14]; +#else + CAN_FilterRegister_TypeDef sFilterRegister[28]; +#endif /* STM32F10X_CL */ +} CAN_TypeDef; + +/** + * @brief Consumer Electronics Control (CEC) + */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t OAR; + __IO uint32_t PRES; + __IO uint32_t ESR; + __IO uint32_t CSR; + __IO uint32_t TXD; + __IO uint32_t RXD; +} CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; + __IO uint8_t IDR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CR; +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SWTRIGR; + __IO uint32_t DHR12R1; + __IO uint32_t DHR12L1; + __IO uint32_t DHR8R1; + __IO uint32_t DHR12R2; + __IO uint32_t DHR12L2; + __IO uint32_t DHR8R2; + __IO uint32_t DHR12RD; + __IO uint32_t DHR12LD; + __IO uint32_t DHR8RD; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + __IO uint32_t SR; +#endif +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; + __IO uint32_t CR; +}DBGMCU_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CCR; + __IO uint32_t CNDTR; + __IO uint32_t CPAR; + __IO uint32_t CMAR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t ISR; + __IO uint32_t IFCR; +} DMA_TypeDef; + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; + __IO uint32_t KEYR; + __IO uint32_t OPTKEYR; + __IO uint32_t SR; + __IO uint32_t CR; + __IO uint32_t AR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WRPR; +#ifdef STM32F10X_XL + uint32_t RESERVED1[8]; + __IO uint32_t KEYR2; + uint32_t RESERVED2; + __IO uint32_t SR2; + __IO uint32_t CR2; + __IO uint32_t AR2; +#endif /* STM32F10X_XL */ +} FLASH_TypeDef; + +/** + * @brief Option Bytes Registers + */ + +typedef struct +{ + __IO uint16_t RDP; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRP0; + __IO uint16_t WRP1; + __IO uint16_t WRP2; + __IO uint16_t WRP3; +} OB_TypeDef; + +/** + * @brief Flexible Static Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank2 + */ + +typedef struct +{ + __IO uint32_t PCR2; + __IO uint32_t SR2; + __IO uint32_t PMEM2; + __IO uint32_t PATT2; + uint32_t RESERVED0; + __IO uint32_t ECCR2; +} FSMC_Bank2_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR3; + __IO uint32_t SR3; + __IO uint32_t PMEM3; + __IO uint32_t PATT3; + uint32_t RESERVED0; + __IO uint32_t ECCR3; +} FSMC_Bank3_TypeDef; + +/** + * @brief Flexible Static Memory Controller Bank4 + */ + +typedef struct +{ + __IO uint32_t PCR4; + __IO uint32_t SR4; + __IO uint32_t PMEM4; + __IO uint32_t PATT4; + __IO uint32_t PIO4; +} FSMC_Bank4_TypeDef; + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t CRL; + __IO uint32_t CRH; + __IO uint32_t IDR; + __IO uint32_t ODR; + __IO uint32_t BSRR; + __IO uint32_t BRR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/** + * @brief Alternate Function I/O + */ + +typedef struct +{ + __IO uint32_t EVCR; + __IO uint32_t MAPR; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t MAPR2; +} AFIO_TypeDef; +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t OAR1; + uint16_t RESERVED2; + __IO uint16_t OAR2; + uint16_t RESERVED3; + __IO uint16_t DR; + uint16_t RESERVED4; + __IO uint16_t SR1; + uint16_t RESERVED5; + __IO uint16_t SR2; + uint16_t RESERVED6; + __IO uint16_t CCR; + uint16_t RESERVED7; + __IO uint16_t TRISE; + uint16_t RESERVED8; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; + __IO uint32_t PR; + __IO uint32_t RLR; + __IO uint32_t SR; +} IWDG_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFGR; + __IO uint32_t CIR; + __IO uint32_t APB2RSTR; + __IO uint32_t APB1RSTR; + __IO uint32_t AHBENR; + __IO uint32_t APB2ENR; + __IO uint32_t APB1ENR; + __IO uint32_t BDCR; + __IO uint32_t CSR; + +#ifdef STM32F10X_CL + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +#endif /* STM32F10X_CL */ + +#if defined STM32F10X_LD_VL || defined STM32F10X_MD_VL + uint32_t RESERVED0; + __IO uint32_t CFGR2; +#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL */ +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint16_t CRH; + uint16_t RESERVED0; + __IO uint16_t CRL; + uint16_t RESERVED1; + __IO uint16_t PRLH; + uint16_t RESERVED2; + __IO uint16_t PRLL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRH; + uint16_t RESERVED8; + __IO uint16_t ALRL; + uint16_t RESERVED9; +} RTC_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[13]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SR; + uint16_t RESERVED2; + __IO uint16_t DR; + uint16_t RESERVED3; + __IO uint16_t CRCPR; + uint16_t RESERVED4; + __IO uint16_t RXCRCR; + uint16_t RESERVED5; + __IO uint16_t TXCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; +} SPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint16_t CR1; + uint16_t RESERVED0; + __IO uint16_t CR2; + uint16_t RESERVED1; + __IO uint16_t SMCR; + uint16_t RESERVED2; + __IO uint16_t DIER; + uint16_t RESERVED3; + __IO uint16_t SR; + uint16_t RESERVED4; + __IO uint16_t EGR; + uint16_t RESERVED5; + __IO uint16_t CCMR1; + uint16_t RESERVED6; + __IO uint16_t CCMR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ARR; + uint16_t RESERVED11; + __IO uint16_t RCR; + uint16_t RESERVED12; + __IO uint16_t CCR1; + uint16_t RESERVED13; + __IO uint16_t CCR2; + uint16_t RESERVED14; + __IO uint16_t CCR3; + uint16_t RESERVED15; + __IO uint16_t CCR4; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DCR; + uint16_t RESERVED18; + __IO uint16_t DMAR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint16_t SR; + uint16_t RESERVED0; + __IO uint16_t DR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CR1; + uint16_t RESERVED3; + __IO uint16_t CR2; + uint16_t RESERVED4; + __IO uint16_t CR3; + uint16_t RESERVED5; + __IO uint16_t GTPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CFR; + __IO uint32_t SR; +} WWDG_TypeDef; + +/** + * @} + */ + +/** @addtogroup Peripheral_memory_map + * @{ + */ + +#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */ +#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */ + +#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the bit-band region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the bit-band region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) +#define CEC_BASE (APB1PERIPH_BASE + 0x7800) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) + +#define SDIO_BASE (PERIPH_BASE + 0x18000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ + +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ +#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ +#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ + +#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ + +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) +#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) +#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ + + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ + +/******************************************************************************/ +/* */ +/* Power Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CR register ********************/ +#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ +#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ +#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ +#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ +#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ + +#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ +#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ +#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ + +/*!< PVD level configuration */ +#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ +#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ +#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ +#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ +#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ +#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ +#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ +#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ + +#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ + + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ + +/******************************************************************************/ +/* */ +/* Backup registers */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DR1 register ********************/ +#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR2 register ********************/ +#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR3 register ********************/ +#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR4 register ********************/ +#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR5 register ********************/ +#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR6 register ********************/ +#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR7 register ********************/ +#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR8 register ********************/ +#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR9 register ********************/ +#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR10 register *******************/ +#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR11 register *******************/ +#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR12 register *******************/ +#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR13 register *******************/ +#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR14 register *******************/ +#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR15 register *******************/ +#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR16 register *******************/ +#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR17 register *******************/ +#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_DR18 register ********************/ +#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR19 register *******************/ +#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR20 register *******************/ +#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR21 register *******************/ +#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR22 register *******************/ +#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR23 register *******************/ +#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR24 register *******************/ +#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR25 register *******************/ +#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR26 register *******************/ +#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR27 register *******************/ +#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR28 register *******************/ +#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR29 register *******************/ +#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR30 register *******************/ +#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR31 register *******************/ +#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR32 register *******************/ +#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR33 register *******************/ +#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR34 register *******************/ +#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR35 register *******************/ +#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR36 register *******************/ +#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR37 register *******************/ +#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR38 register *******************/ +#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR39 register *******************/ +#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR40 register *******************/ +#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR41 register *******************/ +#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/******************* Bit definition for BKP_DR42 register *******************/ +#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ + +/****************** Bit definition for BKP_RTCCR register *******************/ +#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ +#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ +#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ +#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_CR register ********************/ +#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ +#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ + +/******************* Bit definition for BKP_CSR register ********************/ +#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ +#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ +#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ +#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ +#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ + +/******************************************************************************/ +/* */ +/* Reset and Clock Control */ +/* */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CR register ********************/ +#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ +#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ +#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ +#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ +#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ +#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ +#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ +#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ +#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ +#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ + +#ifdef STM32F10X_CL + #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ + #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ + #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ + #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ +#endif /* STM32F10X_CL */ + +/******************* Bit definition for RCC_CFGR register *******************/ +/*!< SW configuration */ +#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ +#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ +#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ +#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ + +/*!< SWS configuration */ +#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ +#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ +#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ + +/*!< HPRE configuration */ +#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ +#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ +#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ +#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + +#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ +#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ +#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ +#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ +#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ +#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ +#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ +#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ + +/*!< PPRE1 configuration */ +#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ + +/*!< PPRE2 configuration */ +#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ +#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ +#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ + +#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ +#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ +#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ +#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ + +/*!< ADCPPRE configuration */ +#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ +#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ +#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ +#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ + +#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ + +#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ + +/*!< PLLMUL configuration */ +#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ +#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ +#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ + +#ifdef STM32F10X_CL + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ + #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ + + #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ + #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ + #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ + #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#else + #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ + #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ + + #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ + #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ + + #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ + #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ + #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ + #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ + #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ + #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ + #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ + #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ + #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ + #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ + #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ + #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ + #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ + #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ + #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ + #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ + +/*!< MCO configuration */ + #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ + #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ + #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + + #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ + #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ + #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ + #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ + #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ +#endif /* STM32F10X_CL */ + +/*!<****************** Bit definition for RCC_CIR register ********************/ +#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ +#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ +#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ +#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ +#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ +#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ +#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ +#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ +#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ +#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ +#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ +#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ +#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ +#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ +#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ +#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ +#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ + +#ifdef STM32F10X_CL + #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ + #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ + #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ + #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ + #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ + #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ +#endif /* STM32F10X_CL */ + +/***************** Bit definition for RCC_APB2RSTR register *****************/ +#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ +#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ +#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ +#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ +#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ +#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) +#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ +#endif + +#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ +#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ +#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ +#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ +#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ + #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ + #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ + #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ + #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ + #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ +#endif /* STM32F10X_XL */ + +/***************** Bit definition for RCC_APB1RSTR register *****************/ +#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ +#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ +#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ +#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ +#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) +#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ +#endif + +#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ +#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ + #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ + #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */ + #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) + #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ + #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ + #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ + #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ + #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ + #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ +#endif + +#ifdef STM32F10X_CL + #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ + #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ + #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ +#endif /* STM32F10X_XL */ + +/****************** Bit definition for RCC_AHBENR register ******************/ +#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ +#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ +#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ +#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) + #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ + #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ +#endif + +#ifdef STM32F10X_CL + #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ + #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ + #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ + #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ +#endif /* STM32F10X_CL */ + +/****************** Bit definition for RCC_APB2ENR register *****************/ +#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ +#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ +#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ +#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ +#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ +#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) +#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ +#endif + +#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ +#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ +#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ +#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ +#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ +#endif + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_XL) + #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ + #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ + #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ + #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ +#endif + +#ifdef STM32F10X_XL + #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ + #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ + #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ +#endif + +/***************** Bit definition for RCC_APB1ENR register ******************/ +#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ +#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ +#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ +#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ +#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) +#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ +#endif + +#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ +#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ + +#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) + #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ + #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ + #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ + #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ +#endif /* STM32F10X_LD && STM32F10X_LD_VL */ + +#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) + #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ +#endif + +#if defined (STM32F10X_HD) || defined (STM32F10X_CL) + #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ + #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ + #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ +#endif + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ + #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ + #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ + #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ +#endif + +#ifdef STM32F10X_CL + #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ +#endif /* STM32F10X_CL */ + +#ifdef STM32F10X_XL + #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ + #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ + #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ +#endif /* STM32F10X_XL */ + +/******************* Bit definition for RCC_BDCR register *******************/ +#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ +#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ +#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ + +#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< RTC congiguration */ +#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ +#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ +#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ +#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ + +/******************* Bit definition for RCC_CSR register ********************/ +#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ +#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ +#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ +#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ +#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ +#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ +#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ +#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ +#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ + +#ifdef STM32F10X_CL +/******************* Bit definition for RCC_AHBRSTR register ****************/ + #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ + #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ + +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ + +/*!< PREDIV2 configuration */ + #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ + #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ + #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ + +/*!< PLL2MUL configuration */ + #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ + #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ + #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ + #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ + #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ + #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ + #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ + #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ + #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ + #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ + #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ + +/*!< PLL3MUL configuration */ + #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ + #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ + #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ + #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ + + #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ + #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ + #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ + #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ + #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ + #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ + #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ + #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ + #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ + + #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ + #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ + #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/******************* Bit definition for RCC_CFGR2 register ******************/ +/*!< PREDIV1 configuration */ + #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ + #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ + #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ + #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ + + #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ + #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ + #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ + #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ + #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ + #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ + #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ + #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ + #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ + #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ + #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ + #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ + #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ + #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ + #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ + #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ +#endif + +/******************************************************************************/ +/* */ +/* General Purpose and Alternate Function I/O */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CRL register *******************/ +#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/******************* Bit definition for GPIO_CRH register *******************/ +#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ + +#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ +#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ + +#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ +#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ +#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ +#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ + +#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ +#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ + +#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ +#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ + +#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ +#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ +#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ +#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ + +#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ +#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ + +/*!<****************** Bit definition for GPIO_IDR register *******************/ +#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ +#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ +#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ +#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ +#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ +#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ +#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ +#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ +#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ +#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ +#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ +#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ +#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ +#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ +#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ +#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ + +/******************* Bit definition for GPIO_ODR register *******************/ +#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ +#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ +#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ +#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ +#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ +#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ +#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ +#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ +#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ +#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ +#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ +#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ +#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ +#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ +#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ +#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSRR register *******************/ +#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ +#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ +#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ +#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ +#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ +#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ +#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ +#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ +#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ +#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ +#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ +#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ +#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ +#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ +#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ +#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ + +#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ +#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ +#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ +#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ +#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ +#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ +#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ +#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ +#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ +#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ +#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ +#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ +#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ +#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ +#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ +#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BRR register *******************/ +#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ +#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ +#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ +#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ +#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ +#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ +#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ +#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ +#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ +#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ +#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ +#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ +#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ +#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ +#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ +#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ +#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ +#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ +#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ +#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ +#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ +#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ +#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ +#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ +#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ +#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ +#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ +#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ +#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ +#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ +#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ +#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ + +/*----------------------------------------------------------------------------*/ + +/****************** Bit definition for AFIO_EVCR register *******************/ +#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ +#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ +#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ + +/*!< PIN configuration */ +#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ +#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ +#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ +#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ +#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ +#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ +#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ +#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ +#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ +#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ +#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ +#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ +#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ +#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ +#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ +#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ + +#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ +#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ +#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ +#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ + +/*!< PORT configuration */ +#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ +#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ +#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ +#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ +#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ + +#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ + +/****************** Bit definition for AFIO_MAPR register *******************/ +#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ +#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ +#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ +#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ + +#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ +#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ + +/* USART3_REMAP configuration */ +#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ +#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ + +/*!< TIM1_REMAP configuration */ +#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ + +/*!< TIM2_REMAP configuration */ +#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ +#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ + +/*!< TIM3_REMAP configuration */ +#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ +#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ + +/*!< CAN_REMAP configuration */ +#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ + +/*!< SWJ_CFG configuration */ +#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ +#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ +#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ + +#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ + +#ifdef STM32F10X_CL +/*!< ETH_REMAP configuration */ + #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ + +/*!< CAN2_REMAP configuration */ + #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ + +/*!< MII_RMII_SEL configuration */ + #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ + +/*!< SPI3_REMAP configuration */ + #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ + +/*!< TIM2ITR1_IREMAP configuration */ + #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ + +/*!< PTP_PPS_REMAP configuration */ + #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ +#endif + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ + +/*!< EXTI0 configuration */ +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ + +/*!< EXTI1 configuration */ +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ + +/*!< EXTI2 configuration */ +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ + +/*!< EXTI3 configuration */ +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ + +/*!< EXTI4 configuration */ +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ + +/* EXTI5 configuration */ +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ + +/*!< EXTI6 configuration */ +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ + +/*!< EXTI7 configuration */ +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ + +/*!< EXTI8 configuration */ +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ + +/*!< EXTI9 configuration */ +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ + +/*!< EXTI10 configuration */ +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ + +/*!< EXTI11 configuration */ +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ + +/* EXTI12 configuration */ +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ + +/* EXTI13 configuration */ +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ + +/*!< EXTI14 configuration */ +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ + +/*!< EXTI15 configuration */ +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ +#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ +#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ +#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ +#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ +#endif + +#ifdef STM32F10X_XL +/****************** Bit definition for AFIO_MAPR2 register ******************/ +#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ +#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ +#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ +#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ +#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ +#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ +#endif + +/******************************************************************************/ +/* */ +/* SystemTick */ +/* */ +/******************************************************************************/ + +/***************** Bit definition for SysTick_CTRL register *****************/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ + +/***************** Bit definition for SysTick_LOAD register *****************/ +#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ + +/***************** Bit definition for SysTick_VAL register ******************/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ + +/***************** Bit definition for SysTick_CALIB register ****************/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ + +/******************************************************************************/ +/* */ +/* Nested Vectored Interrupt Controller */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for NVIC_ISER register *******************/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICER register *******************/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ISPR register *******************/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_ICPR register *******************/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_IABR register *******************/ +#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ +#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ +#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ +#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ +#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ +#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ +#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ +#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ +#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ +#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ +#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ +#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ +#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ +#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ +#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ +#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ +#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ +#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ +#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ +#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ +#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ +#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ +#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ +#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ +#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ +#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ +#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ +#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ +#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ +#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ +#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ +#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ +#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ + +/****************** Bit definition for NVIC_PRI0 register *******************/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ + +/****************** Bit definition for NVIC_PRI1 register *******************/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ + +/****************** Bit definition for NVIC_PRI2 register *******************/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ + +/****************** Bit definition for NVIC_PRI3 register *******************/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ + +/****************** Bit definition for NVIC_PRI4 register *******************/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ + +/****************** Bit definition for NVIC_PRI5 register *******************/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ + +/****************** Bit definition for NVIC_PRI6 register *******************/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ + +/****************** Bit definition for NVIC_PRI7 register *******************/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ + +/****************** Bit definition for SCB_CPUID register *******************/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ + +/******************* Bit definition for SCB_ICSR register *******************/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ +#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ + +/******************* Bit definition for SCB_VTOR register *******************/ +#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ +#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ + +/*!<***************** Bit definition for SCB_AIRCR register *******************/ +#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ + +#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ +#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ +#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ +#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ + +/* prority group configuration */ +#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ +#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ +#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ + +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ + +/******************* Bit definition for SCB_SCR register ********************/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ + +/******************** Bit definition for SCB_CCR register *******************/ +#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ +#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ +#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ +#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ +#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/******************* Bit definition for SCB_SHPR register ********************/ +#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/****************** Bit definition for SCB_SHCSR register *******************/ +#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ +#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ +#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ +#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ +#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ +#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ +#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ +#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ +#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ +#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ +#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ +#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ +#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ + +/******************* Bit definition for SCB_CFSR register *******************/ +/*!< MFSR */ +#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ +#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ +#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ +#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ +#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ +/*!< BFSR */ +#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ +#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ +#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ +#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ +#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ +#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ +/*!< UFSR */ +#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */ +#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ +#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ +#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ +#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ +#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ + +/******************* Bit definition for SCB_HFSR register *******************/ +#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */ +#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ +#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ + +/******************* Bit definition for SCB_DFSR register *******************/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ + +/******************* Bit definition for SCB_MMFAR register ******************/ +#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ + +/******************* Bit definition for SCB_BFAR register *******************/ +#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ + +/******************* Bit definition for SCB_afsr register *******************/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_IMR register *******************/ +#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ +#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ +#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ +#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ +#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ +#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ +#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ +#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ +#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ +#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ +#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ +#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ +#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ +#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ +#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ +#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ +#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ +#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ +#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ +#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EMR register *******************/ +#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ +#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ +#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ +#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ +#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ +#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ +#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ +#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ +#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ +#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ +#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ +#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ +#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ +#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ +#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ +#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ +#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ +#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ +#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ +#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTSR register *******************/ +#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ +#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ +#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ +#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ +#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ +#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ +#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ +#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ +#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ +#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ +#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ +#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ +#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ +#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ +#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ +#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ +#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ +#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ +#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ +#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTSR register *******************/ +#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ +#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ +#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ +#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ +#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ +#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ +#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ +#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ +#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ +#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ +#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ +#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ +#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ +#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ +#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ +#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ +#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ +#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ +#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ +#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIER register ******************/ +#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ +#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_PR register ********************/ +#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ +#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ +#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ +#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ +#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ +#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ +#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ +#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ +#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ +#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ +#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ +#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ +#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ +#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ +#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ +#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ +#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ +#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ +#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ +#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ + +/******************************************************************************/ +/* */ +/* DMA Controller */ +/* */ +/******************************************************************************/ + +/******************* Bit definition for DMA_ISR register ********************/ +#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *******************/ +#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */ +#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR1 register *******************/ +#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ +#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ +#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR2 register *******************/ +#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */ +#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/******************* Bit definition for DMA_CCR3 register *******************/ +#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ +#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ +#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ +#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ +#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ +#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ +#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ +#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ + +#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ +#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ + +#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ +#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ + +#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ +#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ +#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ + +#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ + +/*!<****************** Bit definition for DMA_CCR4 register *******************/ +#define DMA_CCR4_EN ((uint16_t)0x0001) /*!
© COPYRIGHT 2010 STMicroelectronics
+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_STM32F10X_H +#define __SYSTEM_STM32F10X_H + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup STM32F10x_System_Includes + * @{ + */ + +/** + * @} + */ + + +/** @addtogroup STM32F10x_System_Exported_types + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Exported_Functions + * @{ + */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_STM32F10X_H */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/misc.h b/example/libs_stm/inc/stm32f10x/misc.h new file mode 100644 index 000000000..95c9541d3 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/misc.h @@ -0,0 +1,219 @@ +/** + ****************************************************************************** + * @file misc.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MISC_H +#define __MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/** @defgroup MISC_Exported_Types + * @{ + */ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete STM32 Devices IRQ Channels list, please + refer to stm32f10x.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup NVIC_Priority_Table + * @{ + */ + +/** +@code + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + ============================================================================================================================ + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ============================================================================================================================ + NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + | | | 4 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + | | | 3 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bits for subpriority + ============================================================================================================================ +@endcode +*/ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @defgroup SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Exported_Functions + * @{ + */ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_adc.h b/example/libs_stm/inc/stm32f10x/stm32f10x_adc.h new file mode 100644 index 000000000..401241c4c --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_adc.h @@ -0,0 +1,482 @@ +/** + ****************************************************************************** + * @file stm32f10x_adc.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the ADC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_ADC_H +#define __STM32F10x_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/** @defgroup ADC_Exported_Types + * @{ + */ + +/** + * @brief ADC Init structure definition + */ + +typedef struct +{ + uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +}ADC_InitTypeDef; +/** + * @} + */ + +/** @defgroup ADC_Exported_Constants + * @{ + */ + +#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC2) || \ + ((PERIPH) == ADC3)) + +#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC3)) + +/** @defgroup ADC_mode + * @{ + */ + +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ + ((MODE) == ADC_Mode_RegInjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ + ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ + ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ + ((MODE) == ADC_Mode_InjecSimult) || \ + ((MODE) == ADC_Mode_RegSimult) || \ + ((MODE) == ADC_Mode_FastInterl) || \ + ((MODE) == ADC_Mode_SlowInterl) || \ + ((MODE) == ADC_Mode_AlterTrig)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion + * @{ + */ + +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ + +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ + +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ + ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_None) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ + ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) +/** + * @} + */ + +/** @defgroup ADC_data_align + * @{ + */ + +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ + ((ALIGN) == ADC_DataAlign_Left)) +/** + * @} + */ + +/** @defgroup ADC_channels + * @{ + */ + +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ + ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ + ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ + ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ + ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ + ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ + ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ + ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ + ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) +/** + * @} + */ + +/** @defgroup ADC_sampling_time + * @{ + */ + +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ + ((TIME) == ADC_SampleTime_7Cycles5) || \ + ((TIME) == ADC_SampleTime_13Cycles5) || \ + ((TIME) == ADC_SampleTime_28Cycles5) || \ + ((TIME) == ADC_SampleTime_41Cycles5) || \ + ((TIME) == ADC_SampleTime_55Cycles5) || \ + ((TIME) == ADC_SampleTime_71Cycles5) || \ + ((TIME) == ADC_SampleTime_239Cycles5)) +/** + * @} + */ + +/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion + * @{ + */ + +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ + +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ + +#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ + ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) +/** + * @} + */ + +/** @defgroup ADC_injected_channel_selection + * @{ + */ + +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) +#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ + ((CHANNEL) == ADC_InjectedChannel_2) || \ + ((CHANNEL) == ADC_InjectedChannel_3) || \ + ((CHANNEL) == ADC_InjectedChannel_4)) +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_selection + * @{ + */ + +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ + ((WATCHDOG) == ADC_AnalogWatchdog_None)) +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition + * @{ + */ + +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) + +#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ + ((IT) == ADC_IT_JEOC)) +/** + * @} + */ + +/** @defgroup ADC_flags_definition + * @{ + */ + +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) +#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ + ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ + ((FLAG) == ADC_FLAG_STRT)) +/** + * @} + */ + +/** @defgroup ADC_thresholds + * @{ + */ + +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_injected_offset + * @{ + */ + +#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) + +/** + * @} + */ + +/** @defgroup ADC_injected_length + * @{ + */ + +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) + +/** + * @} + */ + +/** @defgroup ADC_injected_rank + * @{ + */ + +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) + +/** + * @} + */ + + +/** @defgroup ADC_regular_length + * @{ + */ + +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) +/** + * @} + */ + +/** @defgroup ADC_regular_rank + * @{ + */ + +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) + +/** + * @} + */ + +/** @defgroup ADC_regular_discontinuous_mode_number + * @{ + */ + +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions + * @{ + */ + +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_StartCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_ADC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_bkp.h b/example/libs_stm/inc/stm32f10x/stm32f10x_bkp.h new file mode 100644 index 000000000..45c4e3500 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_bkp.h @@ -0,0 +1,194 @@ +/** + ****************************************************************************** + * @file stm32f10x_bkp.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the BKP firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_BKP_H +#define __STM32F10x_BKP_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup BKP + * @{ + */ + +/** @defgroup BKP_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Constants + * @{ + */ + +/** @defgroup Tamper_Pin_active_level + * @{ + */ + +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) +#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ + ((LEVEL) == BKP_TamperPinLevel_Low)) +/** + * @} + */ + +/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin + * @{ + */ + +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) +#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ + ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ + ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ + ((SOURCE) == BKP_RTCOutputSource_Second)) +/** + * @} + */ + +/** @defgroup Data_Backup_Register + * @{ + */ + +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + +#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ + ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ + ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ + ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ + ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ + ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ + ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ + ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ + ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ + ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ + ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ + ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ + ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ + ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) + +#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Exported_Functions + * @{ + */ + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_BKP_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_can.h b/example/libs_stm/inc/stm32f10x/stm32f10x_can.h new file mode 100644 index 000000000..d9ae0676f --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_can.h @@ -0,0 +1,535 @@ +/** + ****************************************************************************** + * @file stm32f10x_can.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the CAN firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CAN_H +#define __STM32F10x_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CAN + * @{ + */ + +/** @defgroup CAN_Exported_Types + * @{ + */ + +#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ + ((PERIPH) == CAN2)) + +/** + * @brief CAN init structure definition + */ + +typedef struct +{ + uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE or DISABLE. */ + + FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_InitTypeDef; + +/** + * @brief CAN filter init structure definition + */ + +typedef struct +{ + uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/** + * @brief CAN Tx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */ +} CanTxMsg; + +/** + * @brief CAN Rx message structure definition + */ + +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received. + This parameter can be a value of @ref CAN_identifier_type */ + + uint8_t RTR; /*!< Specifies the type of frame for the received message. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint8_t DLC; /*!< Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */ + + uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. + This parameter can be a value between 0 to 0xFF */ +} CanRxMsg; + +/** + * @} + */ + +/** @defgroup CAN_Exported_Constants + * @{ + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ + +#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */ +#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */ + +/** + * @} + */ + +/** @defgroup CAN_operating_mode + * @{ + */ + +#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \ + ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack)) +/** + * @} + */ + +/** @defgroup CAN_synchronisation_jump_width + * @{ + */ + +#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ + +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ + ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 + * @{ + */ + +#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ + +#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 + * @{ + */ + +#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ + +#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) + +/** + * @} + */ + +/** @defgroup CAN_clock_prescaler + * @{ + */ + +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) + +/** + * @} + */ + +/** @defgroup CAN_filter_number + * @{ + */ +#ifndef STM32F10X_CL + #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) +#else + #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode + * @{ + */ + +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ + +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ + ((MODE) == CAN_FilterMode_IdList)) +/** + * @} + */ + +/** @defgroup CAN_filter_scale + * @{ + */ + +#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ + +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ + ((SCALE) == CAN_FilterScale_32bit)) + +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO + * @{ + */ + +#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ + ((FIFO) == CAN_FilterFIFO1)) + +/** + * @} + */ + +/** @defgroup Start_bank_filter_for_slave_CAN + * @{ + */ +#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) +/** + * @} + */ + +/** @defgroup CAN_Tx + * @{ + */ + +#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) +#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) +#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) + +/** + * @} + */ + +/** @defgroup CAN_identifier_type + * @{ + */ + +#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ +#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT)) + +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request + * @{ + */ + +#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ +#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) + +/** + * @} + */ + +/** @defgroup CAN_transmit_constants + * @{ + */ + +#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */ +#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */ +#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */ +#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ + +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number_constants + * @{ + */ + +#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */ + +#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) + +/** + * @} + */ + +/** @defgroup CAN_sleep_constants + * @{ + */ + +#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ +#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */ + +/** + * @} + */ + +/** @defgroup CAN_wake_up_constants + * @{ + */ + +#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ +#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ + +/** + * @} + */ + +/** @defgroup CAN_flags + * @{ + */ + +#define CAN_FLAG_EWG ((uint32_t)0x00000001) /*!< Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x00000002) /*!< Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ + +#define IS_CAN_FLAG(FLAG) (((FLAG) == CAN_FLAG_EWG) || ((FLAG) == CAN_FLAG_EPV) ||\ + ((FLAG) == CAN_FLAG_BOF)) + +/** + * @} + */ + +/** @defgroup CAN_interrupts + * @{ + */ + +#define CAN_IT_RQCP0 ((uint32_t)0x00000005) /*!< Request completed mailbox 0 */ +#define CAN_IT_RQCP1 ((uint32_t)0x00000006) /*!< Request completed mailbox 1 */ +#define CAN_IT_RQCP2 ((uint32_t)0x00000007) /*!< Request completed mailbox 2 */ +#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending */ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full */ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun */ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending */ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full */ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning */ +#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive */ +#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off */ +#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code */ +#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up */ +#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep */ + +#define IS_CAN_ITConfig(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ + ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ + ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) + +#define IS_CAN_ITStatus(IT) (((IT) == CAN_IT_RQCP0) || ((IT) == CAN_IT_RQCP1) ||\ + ((IT) == CAN_IT_RQCP2) || ((IT) == CAN_IT_FF0) ||\ + ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\ + ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ + ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ + ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions + * @{ + */ + +void CAN_DeInit(CAN_TypeDef* CANx); +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CAN_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_cec.h b/example/libs_stm/inc/stm32f10x/stm32f10x_cec.h new file mode 100644 index 000000000..233a0944f --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_cec.h @@ -0,0 +1,209 @@ +/** + ****************************************************************************** + * @file stm32f10x_cec.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the CEC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CEC_H +#define __STM32F10x_CEC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CEC + * @{ + */ + + +/** @defgroup CEC_Exported_Types + * @{ + */ + +/** + * @brief CEC Init structure definition + */ +typedef struct +{ + uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. + This parameter can be a value of @ref CEC_BitTiming_Mode */ + uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. + This parameter can be a value of @ref CEC_BitPeriod_Mode */ +}CEC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup CEC_Exported_Constants + * @{ + */ + +/** @defgroup CEC_BitTiming_Mode + * @{ + */ +#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ +#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ + +#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ + ((MODE) == CEC_BitTimingErrFreeMode)) +/** + * @} + */ + +/** @defgroup CEC_BitPeriod_Mode + * @{ + */ +#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ +#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ + +#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ + ((MODE) == CEC_BitPeriodFlexibleMode)) +/** + * @} + */ + + +/** @defgroup CEC_interrupts_definition + * @{ + */ +#define CEC_IT_TERR CEC_CSR_TERR +#define CEC_IT_TBTRF CEC_CSR_TBTRF +#define CEC_IT_RERR CEC_CSR_RERR +#define CEC_IT_RBTF CEC_CSR_RBTF +#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ + ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) +/** + * @} + */ + + +/** @defgroup CEC_Own_Addres + * @{ + */ +#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) +/** + * @} + */ + +/** @defgroup CEC_Prescaler + * @{ + */ +#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) + +/** + * @} + */ + +/** @defgroup CEC_flags_definition + * @{ + */ + +/** + * @brief ESR register flags + */ +#define CEC_FLAG_BTE ((uint32_t)0x10010000) +#define CEC_FLAG_BPE ((uint32_t)0x10020000) +#define CEC_FLAG_RBTFE ((uint32_t)0x10040000) +#define CEC_FLAG_SBE ((uint32_t)0x10080000) +#define CEC_FLAG_ACKE ((uint32_t)0x10100000) +#define CEC_FLAG_LINE ((uint32_t)0x10200000) +#define CEC_FLAG_TBTFE ((uint32_t)0x10400000) + +/** + * @brief CSR register flags + */ +#define CEC_FLAG_TEOM ((uint32_t)0x00000002) +#define CEC_FLAG_TERR ((uint32_t)0x00000004) +#define CEC_FLAG_TBTRF ((uint32_t)0x00000008) +#define CEC_FLAG_RSOM ((uint32_t)0x00000010) +#define CEC_FLAG_REOM ((uint32_t)0x00000020) +#define CEC_FLAG_RERR ((uint32_t)0x00000040) +#define CEC_FLAG_RBTF ((uint32_t)0x00000080) + +#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) + +#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ + ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ + ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ + ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ + ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ + ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ + ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup CEC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CEC_Exported_Functions + * @{ + */ +void CEC_DeInit(void); +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); +void CEC_Cmd(FunctionalState NewState); +void CEC_ITConfig(FunctionalState NewState); +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); +void CEC_SetPrescaler(uint16_t CEC_Prescaler); +void CEC_SendDataByte(uint8_t Data); +uint8_t CEC_ReceiveDataByte(void); +void CEC_StartOfMessage(void); +void CEC_EndOfMessageCmd(FunctionalState NewState); +FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); +void CEC_ClearFlag(uint32_t CEC_FLAG); +ITStatus CEC_GetITStatus(uint8_t CEC_IT); +void CEC_ClearITPendingBit(uint16_t CEC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CEC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_crc.h b/example/libs_stm/inc/stm32f10x/stm32f10x_crc.h new file mode 100644 index 000000000..f7b2678c3 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_crc.h @@ -0,0 +1,93 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the CRC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CRC_H +#define __STM32F10x_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup CRC + * @{ + */ + +/** @defgroup CRC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Constants + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Exported_Functions + * @{ + */ + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_CRC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_dac.h b/example/libs_stm/inc/stm32f10x/stm32f10x_dac.h new file mode 100644 index 000000000..16afbce49 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_dac.h @@ -0,0 +1,316 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the DAC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DAC_H +#define __STM32F10x_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DAC + * @{ + */ + +/** @defgroup DAC_Exported_Types + * @{ + */ + +/** + * @brief DAC Init structure definition + */ + +typedef struct +{ + uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DAC_Exported_Constants + * @{ + */ + +/** @defgroup DAC_trigger_selection + * @{ + */ + +#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel + only in High-density devices*/ +#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel + only in Connectivity line, Medium-density and Low-density Value Line devices */ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel + only in Medium-density and Low-density Value Line devices*/ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ + ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ + ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ + ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ + ((TRIGGER) == DAC_Trigger_Software)) + +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) +#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ + ((WAVE) == DAC_WaveGeneration_Noise) || \ + ((WAVE) == DAC_WaveGeneration_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_lfsrunmask_triangleamplitude + * @{ + */ + +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ + ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ + ((VALUE) == DAC_TriangleAmplitude_1) || \ + ((VALUE) == DAC_TriangleAmplitude_3) || \ + ((VALUE) == DAC_TriangleAmplitude_7) || \ + ((VALUE) == DAC_TriangleAmplitude_15) || \ + ((VALUE) == DAC_TriangleAmplitude_31) || \ + ((VALUE) == DAC_TriangleAmplitude_63) || \ + ((VALUE) == DAC_TriangleAmplitude_127) || \ + ((VALUE) == DAC_TriangleAmplitude_255) || \ + ((VALUE) == DAC_TriangleAmplitude_511) || \ + ((VALUE) == DAC_TriangleAmplitude_1023) || \ + ((VALUE) == DAC_TriangleAmplitude_2047) || \ + ((VALUE) == DAC_TriangleAmplitude_4095)) +/** + * @} + */ + +/** @defgroup DAC_output_buffer + * @{ + */ + +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) +#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ + ((STATE) == DAC_OutputBuffer_Disable)) +/** + * @} + */ + +/** @defgroup DAC_Channel_selection + * @{ + */ + +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ + ((CHANNEL) == DAC_Channel_2)) +/** + * @} + */ + +/** @defgroup DAC_data_alignement + * @{ + */ + +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ + ((ALIGN) == DAC_Align_12b_L) || \ + ((ALIGN) == DAC_Align_8b_R)) +/** + * @} + */ + +/** @defgroup DAC_wave_generation + * @{ + */ + +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ + ((WAVE) == DAC_Wave_Triangle)) +/** + * @} + */ + +/** @defgroup DAC_data + * @{ + */ + +#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) +/** + * @} + */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/** @defgroup DAC_interrupts_definition + * @{ + */ + +#define DAC_IT_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) + +/** + * @} + */ + +/** @defgroup DAC_flags_definition + * @{ + */ + +#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) +#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) + +/** + * @} + */ +#endif + +/** + * @} + */ + +/** @defgroup DAC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Exported_Functions + * @{ + */ + +void DAC_DeInit(void); +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); +#endif +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_DAC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_dbgmcu.h b/example/libs_stm/inc/stm32f10x/stm32f10x_dbgmcu.h new file mode 100644 index 000000000..5a78f7355 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_dbgmcu.h @@ -0,0 +1,118 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the DBGMCU + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DBGMCU_H +#define __STM32F10x_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DBGMCU + * @{ + */ + +/** @defgroup DBGMCU_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) +#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) +#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) +#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) +#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) +#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) +#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) +#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) +#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) +#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Exported_Functions + * @{ + */ + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_DBGMCU_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_dma.h b/example/libs_stm/inc/stm32f10x/stm32f10x_dma.h new file mode 100644 index 000000000..35769abc6 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_dma.h @@ -0,0 +1,437 @@ +/** + ****************************************************************************** + * @file stm32f10x_dma.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the DMA firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_DMA_H +#define __STM32F10x_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/** @defgroup DMA_Exported_Types + * @{ + */ + +/** + * @brief DMA Init structure definition + */ + +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +}DMA_InitTypeDef; + +/** + * @} + */ + +/** @defgroup DMA_Exported_Constants + * @{ + */ + +#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ + ((PERIPH) == DMA1_Channel2) || \ + ((PERIPH) == DMA1_Channel3) || \ + ((PERIPH) == DMA1_Channel4) || \ + ((PERIPH) == DMA1_Channel5) || \ + ((PERIPH) == DMA1_Channel6) || \ + ((PERIPH) == DMA1_Channel7) || \ + ((PERIPH) == DMA2_Channel1) || \ + ((PERIPH) == DMA2_Channel2) || \ + ((PERIPH) == DMA2_Channel3) || \ + ((PERIPH) == DMA2_Channel4) || \ + ((PERIPH) == DMA2_Channel5)) + +/** @defgroup DMA_data_transfer_direction + * @{ + */ + +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) +#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ + ((DIR) == DMA_DIR_PeripheralSRC)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_incremented_mode + * @{ + */ + +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ + ((STATE) == DMA_PeripheralInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_memory_incremented_mode + * @{ + */ + +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ + ((STATE) == DMA_MemoryInc_Disable)) +/** + * @} + */ + +/** @defgroup DMA_peripheral_data_size + * @{ + */ + +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ + ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ + ((SIZE) == DMA_PeripheralDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_memory_data_size + * @{ + */ + +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ + ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ + ((SIZE) == DMA_MemoryDataSize_Word)) +/** + * @} + */ + +/** @defgroup DMA_circular_normal_mode + * @{ + */ + +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) +#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) +/** + * @} + */ + +/** @defgroup DMA_priority_level + * @{ + */ + +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ + ((PRIORITY) == DMA_Priority_High) || \ + ((PRIORITY) == DMA_Priority_Medium) || \ + ((PRIORITY) == DMA_Priority_Low)) +/** + * @} + */ + +/** @defgroup DMA_memory_to_memory + * @{ + */ + +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) +#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) + +/** + * @} + */ + +/** @defgroup DMA_interrupts_definition + * @{ + */ + +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) +#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) +#define DMA2_IT_TC1 ((uint32_t)0x10000002) +#define DMA2_IT_HT1 ((uint32_t)0x10000004) +#define DMA2_IT_TE1 ((uint32_t)0x10000008) +#define DMA2_IT_GL2 ((uint32_t)0x10000010) +#define DMA2_IT_TC2 ((uint32_t)0x10000020) +#define DMA2_IT_HT2 ((uint32_t)0x10000040) +#define DMA2_IT_TE2 ((uint32_t)0x10000080) +#define DMA2_IT_GL3 ((uint32_t)0x10000100) +#define DMA2_IT_TC3 ((uint32_t)0x10000200) +#define DMA2_IT_HT3 ((uint32_t)0x10000400) +#define DMA2_IT_TE3 ((uint32_t)0x10000800) +#define DMA2_IT_GL4 ((uint32_t)0x10001000) +#define DMA2_IT_TC4 ((uint32_t)0x10002000) +#define DMA2_IT_HT4 ((uint32_t)0x10004000) +#define DMA2_IT_TE4 ((uint32_t)0x10008000) +#define DMA2_IT_GL5 ((uint32_t)0x10010000) +#define DMA2_IT_TC5 ((uint32_t)0x10020000) +#define DMA2_IT_HT5 ((uint32_t)0x10040000) +#define DMA2_IT_TE5 ((uint32_t)0x10080000) + +#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) + +#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ + ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ + ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ + ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ + ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ + ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ + ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ + ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ + ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ + ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ + ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ + ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ + ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ + ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ + ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ + ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ + ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ + ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ + ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ + ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ + ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ + ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ + ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ + ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) + +/** + * @} + */ + +/** @defgroup DMA_flags_definition + * @{ + */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) + +#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) + +#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ + ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ + ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ + ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ + ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ + ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ + ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ + ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ + ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ + ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ + ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ + ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ + ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ + ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ + ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ + ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ + ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ + ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ + ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ + ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ + ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ + ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ + ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ + ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) +/** + * @} + */ + +/** @defgroup DMA_Buffer_Size + * @{ + */ + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup DMA_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions + * @{ + */ + +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); +void DMA_ClearFlag(uint32_t DMA_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMA_IT); +void DMA_ClearITPendingBit(uint32_t DMA_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_DMA_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_exti.h b/example/libs_stm/inc/stm32f10x/stm32f10x_exti.h new file mode 100644 index 000000000..e5f1c5a06 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_exti.h @@ -0,0 +1,183 @@ +/** + ****************************************************************************** + * @file stm32f10x_exti.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the EXTI firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_EXTI_H +#define __STM32F10x_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ + +/** @defgroup EXTI_Exported_Types + * @{ + */ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Constants + * @{ + */ + +/** @defgroup EXTI_Lines + * @{ + */ + +#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS + Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ + +#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) + + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions + * @{ + */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_EXTI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_flash.h b/example/libs_stm/inc/stm32f10x/stm32f10x_flash.h new file mode 100644 index 000000000..71943013d --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_flash.h @@ -0,0 +1,425 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the FLASH + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FLASH_H +#define __STM32F10x_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/** @defgroup FLASH_Exported_Types + * @{ + */ + +/** + * @brief FLASH Status + */ + +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT +}FLASH_Status; + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup Flash_Latency + * @{ + */ + +#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2)) +/** + * @} + */ + +/** @defgroup Half_Cycle_Enable_Disable + * @{ + */ + +#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ +#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ +#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ + ((STATE) == FLASH_HalfCycleAccess_Disable)) +/** + * @} + */ + +/** @defgroup Prefetch_Buffer_Enable_Disable + * @{ + */ + +#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ +#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ +#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ + ((STATE) == FLASH_PrefetchBuffer_Disable)) +/** + * @} + */ + +/** @defgroup Option_Bytes_Write_Protection + * @{ + */ + +/* Values to be used with STM32 Low and Medium density devices */ +#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ +#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ +#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ +#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ +#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ +#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ +#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ +#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ + +/* Values to be used with STM32 Medium-density devices */ +#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ +#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ +#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ +#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ +#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ +#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ +#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ +#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ +#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ +#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ +#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ +#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ +#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ +#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ +#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ +#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ +#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ +#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ +#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ +#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ +#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ +#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ +#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ +#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ + +/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ +#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 0 to 1 */ +#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 2 to 3 */ +#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 4 to 5 */ +#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 6 to 7 */ +#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 8 to 9 */ +#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 10 to 11 */ +#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 12 to 13 */ +#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 14 to 15 */ +#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 16 to 17 */ +#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 18 to 19 */ +#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 20 to 21 */ +#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 22 to 23 */ +#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 24 to 25 */ +#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 26 to 27 */ +#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 28 to 29 */ +#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 30 to 31 */ +#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 32 to 33 */ +#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 34 to 35 */ +#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 36 to 37 */ +#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 38 to 39 */ +#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 40 to 41 */ +#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 42 to 43 */ +#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 44 to 45 */ +#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 46 to 47 */ +#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 48 to 49 */ +#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 50 to 51 */ +#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 52 to 53 */ +#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 54 to 55 */ +#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 56 to 57 */ +#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 58 to 59 */ +#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices: + Write protection of page 60 to 61 */ +#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ +#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ +#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */ + +#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ + +#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) + +#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) + +#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_IWatchdog + * @{ + */ + +#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STOP + * @{ + */ + +#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) + +/** + * @} + */ + +/** @defgroup Option_Bytes_nRST_STDBY + * @{ + */ + +#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) + +#ifdef STM32F10X_XL +/** + * @} + */ +/** @defgroup FLASH_Boot + * @{ + */ +#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position + and this parameter is selected the device will boot from Bank1(Default) */ +#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position + and this parameter is selected the device will boot from Bank 2 or Bank 1, + depending on the activation of the bank */ +#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2)) +#endif +/** + * @} + */ +/** @defgroup FLASH_Interrupts + * @{ + */ +#ifdef STM32F10X_XL +#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */ +#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */ + +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ + +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */ +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) +#else +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ + +#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) +#endif + +/** + * @} + */ + +/** @defgroup FLASH_Flags + * @{ + */ +#ifdef STM32F10X_XL +#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */ +#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */ +#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */ +#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ + +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)|| \ + ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) +#else +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ + ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ + ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ + ((FLAG) == FLASH_FLAG_OPTERR)) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions + * @{ + */ + +/*------------ Functions used for all STM32F10x devices -----*/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +FlagStatus FLASH_GetPrefetchBufferStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); + +/*------------ New function used for all STM32F10x devices -----*/ +void FLASH_UnlockBank1(void); +void FLASH_LockBank1(void); +FLASH_Status FLASH_EraseAllBank1Pages(void); +FLASH_Status FLASH_GetBank1Status(void); +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); + +#ifdef STM32F10X_XL +/*---- New Functions used only with STM32F10x_XL density devices -----*/ +void FLASH_UnlockBank2(void); +void FLASH_LockBank2(void); +FLASH_Status FLASH_EraseAllBank2Pages(void); +FLASH_Status FLASH_GetBank2Status(void); +FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout); +FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_FLASH_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_fsmc.h b/example/libs_stm/inc/stm32f10x/stm32f10x_fsmc.h new file mode 100644 index 000000000..944f077ed --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_fsmc.h @@ -0,0 +1,716 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the FSMC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_FSMC_H +#define __STM32F10x_FSMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup FSMC + * @{ + */ + +/** @defgroup FSMC_Exported_Types + * @{ + */ + +/** + * @brief Timing parameters For NOR/SRAM Banks + */ + +typedef struct +{ + uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories. */ + + uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories.*/ + + uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 0 and 0xFF. + @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 0xF. + @note: It is only used for multiplexed NOR Flash memories. */ + + uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 0xF. + @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The value of this parameter depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is dont care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 0xF in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +}FSMC_NORSRAMTimingInitTypeDef; + +/** + * @brief FSMC NOR/SRAM Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FSMC_Data_Width */ + + uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash + memory, valid only when accessing Flash memories in burst mode. + This parameter can be a value of @ref FSMC_Wrap_Mode */ + + uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ +}FSMC_NORSRAMInitTypeDef; + +/** + * @brief Timing parameters For FSMC NAND and PCCARD Banks + */ + +typedef struct +{ + uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 0xFF.*/ + + uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command deassertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ +}FSMC_NAND_PCCARDTimingInitTypeDef; + +/** + * @brief FSMC NAND Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FSMC_NAND_Bank */ + + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FSMC_Data_Width */ + + uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FSMC_ECC */ + + uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FSMC_ECC_Page_Size */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + +/** + * @brief FSMC PCCARD Init structure definition + */ + +typedef struct +{ + uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ +}FSMC_PCCARDInitTypeDef; + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Constants + * @{ + */ + +/** @defgroup FSMC_NORSRAM_Bank + * @{ + */ +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) +#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) +#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) +#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) +/** + * @} + */ + +/** @defgroup FSMC_NAND_Bank + * @{ + */ +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) +#define FSMC_Bank3_NAND ((uint32_t)0x00000100) +/** + * @} + */ + +/** @defgroup FSMC_PCCARD_Bank + * @{ + */ +#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) +/** + * @} + */ + +#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ + ((BANK) == FSMC_Bank1_NORSRAM2) || \ + ((BANK) == FSMC_Bank1_NORSRAM3) || \ + ((BANK) == FSMC_Bank1_NORSRAM4)) + +#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND)) + +#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ + ((BANK) == FSMC_Bank3_NAND) || \ + ((BANK) == FSMC_Bank4_PCCARD)) + +/** @defgroup NOR_SRAM_Controller + * @{ + */ + +/** @defgroup FSMC_Data_Address_Bus_Multiplexing + * @{ + */ + +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) +#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ + ((MUX) == FSMC_DataAddressMux_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Memory_Type + * @{ + */ + +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) +#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ + ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ + ((MEMORY) == FSMC_MemoryType_NOR)) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Width + * @{ + */ + +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) +#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ + ((WIDTH) == FSMC_MemoryDataWidth_16b)) + +/** + * @} + */ + +/** @defgroup FSMC_Burst_Access_Mode + * @{ + */ + +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) +#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ + ((STATE) == FSMC_BurstAccessMode_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal_Polarity + * @{ + */ + +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) +#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ + ((POLARITY) == FSMC_WaitSignalPolarity_High)) + +/** + * @} + */ + +/** @defgroup FSMC_Wrap_Mode + * @{ + */ + +#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) +#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) +#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ + ((MODE) == FSMC_WrapMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Timing + * @{ + */ + +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ + ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Operation + * @{ + */ + +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) +#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ + ((OPERATION) == FSMC_WriteOperation_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Signal + * @{ + */ + +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) +#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ + ((SIGNAL) == FSMC_WaitSignal_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Extended_Mode + * @{ + */ + +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ + ((MODE) == FSMC_ExtendedMode_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_Write_Burst + * @{ + */ + +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) +#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ + ((BURST) == FSMC_WriteBurst_Enable)) +/** + * @} + */ + +/** @defgroup FSMC_Address_Setup_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Address_Hold_Time + * @{ + */ + +#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Setup_Time + * @{ + */ + +#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) + +/** + * @} + */ + +/** @defgroup FSMC_Bus_Turn_around_Duration + * @{ + */ + +#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_CLK_Division + * @{ + */ + +#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Data_Latency + * @{ + */ + +#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) + +/** + * @} + */ + +/** @defgroup FSMC_Access_Mode + * @{ + */ + +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) +#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ + ((MODE) == FSMC_AccessMode_B) || \ + ((MODE) == FSMC_AccessMode_C) || \ + ((MODE) == FSMC_AccessMode_D)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup NAND_PCCARD_Controller + * @{ + */ + +/** @defgroup FSMC_Wait_feature + * @{ + */ + +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) +#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ + ((FEATURE) == FSMC_Waitfeature_Enable)) + +/** + * @} + */ + + +/** @defgroup FSMC_ECC + * @{ + */ + +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) +#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ + ((STATE) == FSMC_ECC_Enable)) + +/** + * @} + */ + +/** @defgroup FSMC_ECC_Page_Size + * @{ + */ + +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) +#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ + ((SIZE) == FSMC_ECCPageSize_8192Bytes)) + +/** + * @} + */ + +/** @defgroup FSMC_TCLR_Setup_Time + * @{ + */ + +#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_TAR_Setup_Time + * @{ + */ + +#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Setup_Time + * @{ + */ + +#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Wait_Setup_Time + * @{ + */ + +#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Hold_Setup_Time + * @{ + */ + +#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_HiZ_Setup_Time + * @{ + */ + +#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) + +/** + * @} + */ + +/** @defgroup FSMC_Interrupt_sources + * @{ + */ + +#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) +#define FSMC_IT_Level ((uint32_t)0x00000010) +#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) +#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ + ((IT) == FSMC_IT_Level) || \ + ((IT) == FSMC_IT_FallingEdge)) +/** + * @} + */ + +/** @defgroup FSMC_Flags + * @{ + */ + +#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) +#define FSMC_FLAG_Level ((uint32_t)0x00000002) +#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) +#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ + ((FLAG) == FSMC_FLAG_Level) || \ + ((FLAG) == FSMC_FLAG_FallingEdge) || \ + ((FLAG) == FSMC_FLAG_FEMPT)) + +#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Exported_Functions + * @{ + */ + +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_PCCARDDeInit(void); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_PCCARDCmd(FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_FSMC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_gpio.h b/example/libs_stm/inc/stm32f10x/stm32f10x_gpio.h new file mode 100644 index 000000000..aff7a5c1d --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_gpio.h @@ -0,0 +1,379 @@ +/** + ****************************************************************************** + * @file stm32f10x_gpio.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the GPIO + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_GPIO_H +#define __STM32F10x_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/** @defgroup GPIO_Exported_Types + * @{ + */ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOE) || \ + ((PERIPH) == GPIOF) || \ + ((PERIPH) == GPIOG)) + +/** + * @brief Output Maximum frequency selection + */ + +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ + ((SPEED) == GPIO_Speed_50MHz)) + +/** + * @brief Configuration Mode enumeration + */ + +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ + ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ + ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ + ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) + +/** + * @brief GPIO Init structure definition + */ + +typedef struct +{ + uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +}GPIO_InitTypeDef; + + +/** + * @brief Bit_SET and Bit_RESET enumeration + */ + +typedef enum +{ Bit_RESET = 0, + Bit_SET +}BitAction; + +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** @defgroup GPIO_pins_define + * @{ + */ + +#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/** + * @} + */ + +/** @defgroup GPIO_Remap_define + * @{ + */ + +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ +#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ +#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ +#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ +#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected + to TIM2 Internal Trigger 1 for calibration + (only for Connectivity line devices) */ +#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ + +#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ +#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ + +#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for XL-density devices) */ +#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for XL-density devices) */ + + +#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ + ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ + ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ + ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ + ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ + ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ + ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ + ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ + ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ + ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ + ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ + ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ + ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ + ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ + ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ + ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ + ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ + ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ + ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ + ((REMAP) == GPIO_Remap_FSMC_NADV)) + +/** + * @} + */ + +/** @defgroup GPIO_Port_Sources + * @{ + */ + +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) +#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE)) + +#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ + ((PORTSOURCE) == GPIO_PortSourceGPIOG)) + +/** + * @} + */ + +/** @defgroup GPIO_Pin_sources + * @{ + */ + +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) + +/** + * @} + */ + +/** @defgroup Ethernet_Media_Interface + * @{ + */ +#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) +#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) + +#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ + ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) + +/** + * @} + */ +/** + * @} + */ + +/** @defgroup GPIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions + * @{ + */ + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_GPIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_i2c.h b/example/libs_stm/inc/stm32f10x/stm32f10x_i2c.h new file mode 100644 index 000000000..d9c9346bc --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_i2c.h @@ -0,0 +1,670 @@ +/** + ****************************************************************************** + * @file stm32f10x_i2c.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the I2C firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_I2C_H +#define __STM32F10x_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/** @defgroup I2C_Exported_Types + * @{ + */ + +/** + * @brief I2C Init structure definition + */ + +typedef struct +{ + uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +}I2C_InitTypeDef; + +/** + * @} + */ + + +/** @defgroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ + ((PERIPH) == I2C2)) +/** @defgroup I2C_mode + * @{ + */ + +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ + ((MODE) == I2C_Mode_SMBusDevice) || \ + ((MODE) == I2C_Mode_SMBusHost)) +/** + * @} + */ + +/** @defgroup I2C_duty_cycle_in_fast_mode + * @{ + */ + +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ +#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ + ((CYCLE) == I2C_DutyCycle_2)) +/** + * @} + */ + +/** @defgroup I2C_acknowledgement + * @{ + */ + +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) +#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ + ((STATE) == I2C_Ack_Disable)) +/** + * @} + */ + +/** @defgroup I2C_transfer_direction + * @{ + */ + +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ + ((DIRECTION) == I2C_Direction_Receiver)) +/** + * @} + */ + +/** @defgroup I2C_acknowledged_address + * @{ + */ + +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ + ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) +/** + * @} + */ + +/** @defgroup I2C_registers + * @{ + */ + +#define I2C_Register_CR1 ((uint8_t)0x00) +#define I2C_Register_CR2 ((uint8_t)0x04) +#define I2C_Register_OAR1 ((uint8_t)0x08) +#define I2C_Register_OAR2 ((uint8_t)0x0C) +#define I2C_Register_DR ((uint8_t)0x10) +#define I2C_Register_SR1 ((uint8_t)0x14) +#define I2C_Register_SR2 ((uint8_t)0x18) +#define I2C_Register_CCR ((uint8_t)0x1C) +#define I2C_Register_TRISE ((uint8_t)0x20) +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ + ((REGISTER) == I2C_Register_CR2) || \ + ((REGISTER) == I2C_Register_OAR1) || \ + ((REGISTER) == I2C_Register_OAR2) || \ + ((REGISTER) == I2C_Register_DR) || \ + ((REGISTER) == I2C_Register_SR1) || \ + ((REGISTER) == I2C_Register_SR2) || \ + ((REGISTER) == I2C_Register_CCR) || \ + ((REGISTER) == I2C_Register_TRISE)) +/** + * @} + */ + +/** @defgroup I2C_SMBus_alert_pin_level + * @{ + */ + +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) +#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ + ((ALERT) == I2C_SMBusAlert_High)) +/** + * @} + */ + +/** @defgroup I2C_PEC_position + * @{ + */ + +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) +#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ + ((POSITION) == I2C_PECPosition_Current)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ + ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ + ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ + ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ + ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ + ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ + ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) +/** + * @} + */ + +/** @defgroup I2C_flags_definition + * @{ + */ + +/** + * @brief SR2 register flags + */ + +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/** + * @brief SR1 register flags + */ + +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ + ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ + ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ + ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ + ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ + ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ + ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ + ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ + ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ + ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ + ((FLAG) == I2C_FLAG_SB)) +/** + * @} + */ + +/** @defgroup I2C_Events + * @{ + */ + +/*======================================== + + I2C Master Events (Events grouped in order of communication) + ==========================================*/ +/** + * @brief Communication start + * + * After sending the START condition (I2C_GenerateSTART() function) the master + * has to wait for this event. It means that the Start condition has been correctly + * released on the I2C bus (the bus is free, no other devices is communicating). + * + */ +/* --EV5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/** + * @brief Address Acknowledge + * + * After checking on EV5 (start condition correctly released on the bus), the + * master sends the address of the slave(s) with which it will communicate + * (I2C_Send7bitAddress() function, it also determines the direction of the communication: + * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will + * be set: + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (just after generating the START + * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() + * function). Then master should wait on EV9. It means that the 10-bit addressing + * header has been correctly sent on the bus. Then master should send the second part of + * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master + * should wait for event EV6. + * + */ + +/* --EV6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/* --EV9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/** + * @brief Communication events + * + * If a communication is established (START condition generated and slave address + * acknowledged) then the master has to check on one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EV7 then to read + * the data received from the slave (I2C_ReceiveData() function). + * + * 2) Master Transmitter mode: The master has to send data (I2C_SendData() + * function) then to wait on event EV8 or EV8_2. + * These two events are similar: + * - EV8 means that the data has been written in the data register and is + * being shifted out. + * - EV8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EV8 is sufficient for the application. + * Using EV8_2 leads to a slower communication but ensure more reliable test. + * EV8_2 is also more suitable than EV8 for testing on the last data transmission + * (before Stop condition generation). + * + * @note In case the user software does not guarantee that this event EV7 is + * managed before the current byte end of transfer, then user may check on EV7 + * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Master RECEIVER mode -----------------------------*/ +/* --EV7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master TRANSMITTER mode --------------------------*/ +/* --EV8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* --EV8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + + +/*======================================== + + I2C Slave Events (Events grouped in order of communication) + ==========================================*/ + +/** + * @brief Communication start events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a Start condition on the bus (generated by master + * device) followed by the peripheral address. The peripheral generates an ACK + * condition on the bus (if the acknowledge feature is enabled through function + * I2C_AcknowledgeConfig()) and the events listed above are set : + * + * 1) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * 2) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * 3) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* --EV1 (all the events below are variants of EV1) */ +/* 1) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* 2) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* 3) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/** + * @brief Communication events + * + * Wait on one of these events when EV1 has already been checked and: + * + * - Slave RECEIVER mode: + * - EV2: When the application is expecting a data byte to be received. + * - EV4: When the application is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EV3: When a byte has been transmitted by the slave and the application is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be + * used when the user software doesn't guarantee the EV3 is managed before the + * current byte end of tranfer. + * - EV3_2: When the master sends a NACK in order to tell slave that data transmission + * shall end (before sending the STOP condition). In this case slave has to stop sending + * data bytes and expect a Stop condition on the bus. + * + * @note In case the user software does not guarantee that the event EV2 is + * managed before the current byte end of transfer, then user may check on EV2 + * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). + * In this case the communication may be slower. + * + */ + +/* Slave RECEIVER mode --------------------------*/ +/* --EV2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* --EV4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave TRANSMITTER mode -----------------------*/ +/* --EV3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/* --EV3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + +/*=========================== End of Events Description ==========================================*/ + +#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ + ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ + ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ + ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ + ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ + ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ + ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) +/** + * @} + */ + +/** @defgroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) +/** + * @} + */ + +/** @defgroup I2C_clock_speed + * @{ + */ + +#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions + * @{ + */ + +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (SR1 and SR2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occured. + * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the limitations of I2C_GetFlagStatus() function (see below). + * The returned value could be compared to events already defined in the + * library (stm32f10x_i2c.h) or to custom values defined by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlagStatus() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +/** + * + ******************************************************************************* + */ + +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_I2C_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_iwdg.h b/example/libs_stm/inc/stm32f10x/stm32f10x_iwdg.h new file mode 100644 index 000000000..f9a26bf18 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_iwdg.h @@ -0,0 +1,139 @@ +/** + ****************************************************************************** + * @file stm32f10x_iwdg.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the IWDG + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IWDG_H +#define __STM32F10x_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup IWDG + * @{ + */ + +/** @defgroup IWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Constants + * @{ + */ + +/** @defgroup IWDG_WriteAccess + * @{ + */ + +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ + ((ACCESS) == IWDG_WriteAccess_Disable)) +/** + * @} + */ + +/** @defgroup IWDG_prescaler + * @{ + */ + +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ + ((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) +/** + * @} + */ + +/** @defgroup IWDG_Flag + * @{ + */ + +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Exported_Functions + * @{ + */ + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_IWDG_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_pwr.h b/example/libs_stm/inc/stm32f10x/stm32f10x_pwr.h new file mode 100644 index 000000000..ce168da23 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_pwr.h @@ -0,0 +1,155 @@ +/** + ****************************************************************************** + * @file stm32f10x_pwr.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the PWR firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_PWR_H +#define __STM32F10x_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/** @defgroup PWR_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Constants + * @{ + */ + +/** @defgroup PVD_detection_level + * @{ + */ + +#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) +#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) +#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) +#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) +#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) +#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ + ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ + ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ + ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) +/** + * @} + */ + +/** @defgroup Regulator_state_is_STOP_mode + * @{ + */ + +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ + ((REGULATOR) == PWR_Regulator_LowPower)) +/** + * @} + */ + +/** @defgroup STOP_mode_entry + * @{ + */ + +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) + +/** + * @} + */ + +/** @defgroup PWR_Flag + * @{ + */ + +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO)) + +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions + * @{ + */ + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_PWR_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_rcc.h b/example/libs_stm/inc/stm32f10x/stm32f10x_rcc.h new file mode 100644 index 000000000..19afe3e45 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_rcc.h @@ -0,0 +1,726 @@ +/** + ****************************************************************************** + * @file stm32f10x_rcc.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the RCC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RCC_H +#define __STM32F10x_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/** @defgroup RCC_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/** + * @} + */ + +/** @defgroup RCC_Exported_Constants + * @{ + */ + +/** @defgroup HSE_configuration + * @{ + */ + +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass)) + +/** + * @} + */ + +/** @defgroup PLL_entry_clock_source + * @{ + */ + +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) + +#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_CL) + #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) + #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ + ((SOURCE) == RCC_PLLSource_HSE_Div2)) +#else + #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) + #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ + ((SOURCE) == RCC_PLLSource_PREDIV1)) +#endif /* STM32F10X_CL */ + +/** + * @} + */ + +/** @defgroup PLL_multiplication_factor + * @{ + */ +#ifndef STM32F10X_CL + #define RCC_PLLMul_2 ((uint32_t)0x00000000) + #define RCC_PLLMul_3 ((uint32_t)0x00040000) + #define RCC_PLLMul_4 ((uint32_t)0x00080000) + #define RCC_PLLMul_5 ((uint32_t)0x000C0000) + #define RCC_PLLMul_6 ((uint32_t)0x00100000) + #define RCC_PLLMul_7 ((uint32_t)0x00140000) + #define RCC_PLLMul_8 ((uint32_t)0x00180000) + #define RCC_PLLMul_9 ((uint32_t)0x001C0000) + #define RCC_PLLMul_10 ((uint32_t)0x00200000) + #define RCC_PLLMul_11 ((uint32_t)0x00240000) + #define RCC_PLLMul_12 ((uint32_t)0x00280000) + #define RCC_PLLMul_13 ((uint32_t)0x002C0000) + #define RCC_PLLMul_14 ((uint32_t)0x00300000) + #define RCC_PLLMul_15 ((uint32_t)0x00340000) + #define RCC_PLLMul_16 ((uint32_t)0x00380000) + #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ + ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ + ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ + ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ + ((MUL) == RCC_PLLMul_16)) + +#else + #define RCC_PLLMul_4 ((uint32_t)0x00080000) + #define RCC_PLLMul_5 ((uint32_t)0x000C0000) + #define RCC_PLLMul_6 ((uint32_t)0x00100000) + #define RCC_PLLMul_7 ((uint32_t)0x00140000) + #define RCC_PLLMul_8 ((uint32_t)0x00180000) + #define RCC_PLLMul_9 ((uint32_t)0x001C0000) + #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) + + #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ + ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ + ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ + ((MUL) == RCC_PLLMul_6_5)) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup PREDIV1_division_factor + * @{ + */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) + #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) + #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) + #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) + #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) + #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) + #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) + #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) + #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) + #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) + #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) + #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) + #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) + #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) + #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) + #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) + #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) + + #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ + ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ + ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ + ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ + ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ + ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ + ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ + ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) +#endif +/** + * @} + */ + + +/** @defgroup PREDIV1_clock_source + * @{ + */ +#ifdef STM32F10X_CL +/* PREDIV1 clock source (for STM32 connectivity line devices) */ + #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) + #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) + + #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ + ((SOURCE) == RCC_PREDIV1_Source_PLL2)) +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/* PREDIV1 clock source (for STM32 Value line devices) */ + #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) + + #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) +#endif +/** + * @} + */ + +#ifdef STM32F10X_CL +/** @defgroup PREDIV2_division_factor + * @{ + */ + + #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) + #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) + #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) + #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) + #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) + #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) + #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) + #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) + #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) + #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) + #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) + #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) + #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) + #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) + #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) + #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) + + #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ + ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ + ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ + ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ + ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ + ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ + ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ + ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) +/** + * @} + */ + + +/** @defgroup PLL2_multiplication_factor + * @{ + */ + + #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) + #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) + #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) + #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) + #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) + #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) + #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) + #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) + #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) + + #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ + ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ + ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ + ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ + ((MUL) == RCC_PLL2Mul_20)) +/** + * @} + */ + + +/** @defgroup PLL3_multiplication_factor + * @{ + */ + + #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) + #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) + #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) + #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) + #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) + #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) + #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) + #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) + #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) + + #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ + ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ + ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ + ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ + ((MUL) == RCC_PLL3Mul_20)) +/** + * @} + */ + +#endif /* STM32F10X_CL */ + + +/** @defgroup System_clock_source + * @{ + */ + +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) +#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ + ((SOURCE) == RCC_SYSCLKSource_HSE) || \ + ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) +/** + * @} + */ + +/** @defgroup AHB_clock_source + * @{ + */ + +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ + ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ + ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ + ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ + ((HCLK) == RCC_SYSCLK_Div512)) +/** + * @} + */ + +/** @defgroup APB1_APB2_clock_source + * @{ + */ + +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ + ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ + ((PCLK) == RCC_HCLK_Div16)) +/** + * @} + */ + +/** @defgroup RCC_Interrupt_source + * @{ + */ + +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +#ifndef STM32F10X_CL + #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) + #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) + #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) +#else + #define RCC_IT_PLL2RDY ((uint8_t)0x20) + #define RCC_IT_PLL3RDY ((uint8_t)0x40) + #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) + #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ + ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ + ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ + ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) + #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) +#endif /* STM32F10X_CL */ + + +/** + * @} + */ + +#ifndef STM32F10X_CL +/** @defgroup USB_Device_clock_source + * @{ + */ + + #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) + #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) + + #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ + ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) +/** + * @} + */ +#else +/** @defgroup USB_OTG_FS_clock_source + * @{ + */ + #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) + #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) + + #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ + ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) +/** + * @} + */ +#endif /* STM32F10X_CL */ + + +#ifdef STM32F10X_CL +/** @defgroup I2S2_clock_source + * @{ + */ + #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) + #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) + + #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ + ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) +/** + * @} + */ + +/** @defgroup I2S3_clock_source + * @{ + */ + #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) + #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) + + #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ + ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) +/** + * @} + */ +#endif /* STM32F10X_CL */ + + +/** @defgroup ADC_clock_source + * @{ + */ + +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) +#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ + ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) +/** + * @} + */ + +/** @defgroup LSE_configuration + * @{ + */ + +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_Bypass)) +/** + * @} + */ + +/** @defgroup RTC_clock_source + * @{ + */ + +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ + ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) +/** + * @} + */ + +/** @defgroup AHB_peripheral + * @{ + */ + +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) + +#ifndef STM32F10X_CL + #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) + #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) + #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) +#else + #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) + #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) + #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) + #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) + + #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) + #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) +#endif /* STM32F10X_CL */ +/** + * @} + */ + +/** @defgroup APB2_peripheral + * @{ + */ + +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) +#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) +#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) +#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) +#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) +#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) + +#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) +/** + * @} + */ + +/** @defgroup APB1_peripheral + * @{ + */ + +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) +#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) +#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) + +#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/** @defgroup Clock_source_to_output_on_MCO_pin + * @{ + */ + +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +#ifndef STM32F10X_CL + #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2)) +#else + #define RCC_MCO_PLL2CLK ((uint8_t)0x08) + #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) + #define RCC_MCO_XT1 ((uint8_t)0x0A) + #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) + + #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ + ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ + ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ + ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ + ((MCO) == RCC_MCO_PLL3CLK)) +#endif /* STM32F10X_CL */ + +/** + * @} + */ + +/** @defgroup RCC_Flag + * @{ + */ + +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#ifndef STM32F10X_CL + #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) +#else + #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) + #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) + #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ + ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ + ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ + ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ + ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ + ((FLAG) == RCC_FLAG_LPWRRST)) +#endif /* STM32F10X_CL */ + +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions + * @{ + */ + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) + void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); +#endif + +#ifdef STM32F10X_CL + void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); + void RCC_PLL2Config(uint32_t RCC_PLL2Mul); + void RCC_PLL2Cmd(FunctionalState NewState); + void RCC_PLL3Config(uint32_t RCC_PLL3Mul); + void RCC_PLL3Cmd(FunctionalState NewState); +#endif /* STM32F10X_CL */ + +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); + +#ifndef STM32F10X_CL + void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); +#else + void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); +#endif /* STM32F10X_CL */ + +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); + +#ifdef STM32F10X_CL + void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); + void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); +#endif /* STM32F10X_CL */ + +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); + +#ifdef STM32F10X_CL +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +#endif /* STM32F10X_CL */ + +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_RCC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_rtc.h b/example/libs_stm/inc/stm32f10x/stm32f10x_rtc.h new file mode 100644 index 000000000..833f2fea1 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_rtc.h @@ -0,0 +1,134 @@ +/** + ****************************************************************************** + * @file stm32f10x_rtc.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the RTC firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_RTC_H +#define __STM32F10x_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup RTC + * @{ + */ + +/** @defgroup RTC_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Constants + * @{ + */ + +/** @defgroup RTC_interrupts_define + * @{ + */ + +#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ +#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ + ((IT) == RTC_IT_SEC)) +/** + * @} + */ + +/** @defgroup RTC_interrupts_flags + * @{ + */ + +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ +#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ + ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ + ((FLAG) == RTC_FLAG_SEC)) +#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions + * @{ + */ + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_RTC_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_sdio.h b/example/libs_stm/inc/stm32f10x/stm32f10x_sdio.h new file mode 100644 index 000000000..a6c62cd8b --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_sdio.h @@ -0,0 +1,530 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the SDIO firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SDIO_H +#define __STM32F10x_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SDIO + * @{ + */ + +/** @defgroup SDIO_Exported_Types + * @{ + */ + +typedef struct +{ + uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDIO_Clock_Edge */ + + uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDIO_Clock_Bypass */ + + uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ + + uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. + This parameter can be a value between 0x00 and 0xFF. */ + +} SDIO_InitTypeDef; + +typedef struct +{ + uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ + + uint32_t SDIO_Response; /*!< Specifies the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ + + uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_CPSM_State */ +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDIO_Data_Block_Size */ + + uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDIO_Transfer_Type */ + + uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_DPSM_State */ +} SDIO_DataInitTypeDef; + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Constants + * @{ + */ + +/** @defgroup SDIO_Clock_Edge + * @{ + */ + +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) +#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ + ((EDGE) == SDIO_ClockEdge_Falling)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Bypass + * @{ + */ + +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ + ((BYPASS) == SDIO_ClockBypass_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Clock_Power_Save + * @{ + */ + +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) +#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ + ((SAVE) == SDIO_ClockPowerSave_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Bus_Wide + * @{ + */ + +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) +#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ + ((WIDE) == SDIO_BusWide_8b)) + +/** + * @} + */ + +/** @defgroup SDIO_Hardware_Flow_Control + * @{ + */ + +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) +#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ + ((CONTROL) == SDIO_HardwareFlowControl_Enable)) +/** + * @} + */ + +/** @defgroup SDIO_Power_State + * @{ + */ + +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) +#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) +/** + * @} + */ + + +/** @defgroup SDIO_Interrupt_soucres + * @{ + */ + +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) +/** + * @} + */ + +/** @defgroup SDIO_Command_Index + * @{ + */ + +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) +/** + * @} + */ + +/** @defgroup SDIO_Response_Type + * @{ + */ + +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ + ((RESPONSE) == SDIO_Response_Short) || \ + ((RESPONSE) == SDIO_Response_Long)) +/** + * @} + */ + +/** @defgroup SDIO_Wait_Interrupt_State + * @{ + */ + +#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ +#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ +#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ +#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ + ((WAIT) == SDIO_Wait_Pend)) +/** + * @} + */ + +/** @defgroup SDIO_CPSM_State + * @{ + */ + +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) +#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Response_Registers + * @{ + */ + +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) +#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ + ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) +/** + * @} + */ + +/** @defgroup SDIO_Data_Length + * @{ + */ + +#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) +/** + * @} + */ + +/** @defgroup SDIO_Data_Block_Size + * @{ + */ + +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ + ((SIZE) == SDIO_DataBlockSize_2b) || \ + ((SIZE) == SDIO_DataBlockSize_4b) || \ + ((SIZE) == SDIO_DataBlockSize_8b) || \ + ((SIZE) == SDIO_DataBlockSize_16b) || \ + ((SIZE) == SDIO_DataBlockSize_32b) || \ + ((SIZE) == SDIO_DataBlockSize_64b) || \ + ((SIZE) == SDIO_DataBlockSize_128b) || \ + ((SIZE) == SDIO_DataBlockSize_256b) || \ + ((SIZE) == SDIO_DataBlockSize_512b) || \ + ((SIZE) == SDIO_DataBlockSize_1024b) || \ + ((SIZE) == SDIO_DataBlockSize_2048b) || \ + ((SIZE) == SDIO_DataBlockSize_4096b) || \ + ((SIZE) == SDIO_DataBlockSize_8192b) || \ + ((SIZE) == SDIO_DataBlockSize_16384b)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Direction + * @{ + */ + +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ + ((DIR) == SDIO_TransferDir_ToSDIO)) +/** + * @} + */ + +/** @defgroup SDIO_Transfer_Type + * @{ + */ + +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ + ((MODE) == SDIO_TransferMode_Block)) +/** + * @} + */ + +/** @defgroup SDIO_DPSM_State + * @{ + */ + +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) +#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) +/** + * @} + */ + +/** @defgroup SDIO_Flags + * @{ + */ + +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) +#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ + ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ + ((FLAG) == SDIO_FLAG_TXUNDERR) || \ + ((FLAG) == SDIO_FLAG_RXOVERR) || \ + ((FLAG) == SDIO_FLAG_CMDREND) || \ + ((FLAG) == SDIO_FLAG_CMDSENT) || \ + ((FLAG) == SDIO_FLAG_DATAEND) || \ + ((FLAG) == SDIO_FLAG_STBITERR) || \ + ((FLAG) == SDIO_FLAG_DBCKEND) || \ + ((FLAG) == SDIO_FLAG_CMDACT) || \ + ((FLAG) == SDIO_FLAG_TXACT) || \ + ((FLAG) == SDIO_FLAG_RXACT) || \ + ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOF) || \ + ((FLAG) == SDIO_FLAG_RXFIFOF) || \ + ((FLAG) == SDIO_FLAG_TXFIFOE) || \ + ((FLAG) == SDIO_FLAG_RXFIFOE) || \ + ((FLAG) == SDIO_FLAG_TXDAVL) || \ + ((FLAG) == SDIO_FLAG_RXDAVL) || \ + ((FLAG) == SDIO_FLAG_SDIOIT) || \ + ((FLAG) == SDIO_FLAG_CEATAEND)) + +#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) + +#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ + ((IT) == SDIO_IT_DCRCFAIL) || \ + ((IT) == SDIO_IT_CTIMEOUT) || \ + ((IT) == SDIO_IT_DTIMEOUT) || \ + ((IT) == SDIO_IT_TXUNDERR) || \ + ((IT) == SDIO_IT_RXOVERR) || \ + ((IT) == SDIO_IT_CMDREND) || \ + ((IT) == SDIO_IT_CMDSENT) || \ + ((IT) == SDIO_IT_DATAEND) || \ + ((IT) == SDIO_IT_STBITERR) || \ + ((IT) == SDIO_IT_DBCKEND) || \ + ((IT) == SDIO_IT_CMDACT) || \ + ((IT) == SDIO_IT_TXACT) || \ + ((IT) == SDIO_IT_RXACT) || \ + ((IT) == SDIO_IT_TXFIFOHE) || \ + ((IT) == SDIO_IT_RXFIFOHF) || \ + ((IT) == SDIO_IT_TXFIFOF) || \ + ((IT) == SDIO_IT_RXFIFOF) || \ + ((IT) == SDIO_IT_TXFIFOE) || \ + ((IT) == SDIO_IT_RXFIFOE) || \ + ((IT) == SDIO_IT_TXDAVL) || \ + ((IT) == SDIO_IT_RXDAVL) || \ + ((IT) == SDIO_IT_SDIOIT) || \ + ((IT) == SDIO_IT_CEATAEND)) + +#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) + +/** + * @} + */ + +/** @defgroup SDIO_Read_Wait_Mode + * @{ + */ + +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ + ((MODE) == SDIO_ReadWaitMode_DATA2)) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Exported_Functions + * @{ + */ + +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +void SDIO_DMACmd(FunctionalState NewState); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_SDIO_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_spi.h b/example/libs_stm/inc/stm32f10x/stm32f10x_spi.h new file mode 100644 index 000000000..920c82697 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_spi.h @@ -0,0 +1,490 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the SPI firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_SPI_H +#define __STM32F10x_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/** @defgroup SPI_Exported_Types + * @{ + */ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + + uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/** + * @} + */ + +/** @defgroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +/** @defgroup SPI_data_direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) +/** + * @} + */ + +/** @defgroup SPI_mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** + * @} + */ + +/** @defgroup SPI_data_size + * @{ + */ + +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) +#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ + ((DATASIZE) == SPI_DataSize_8b)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup I2S_Mode + * @{ + */ + +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) +#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ + ((MODE) == I2S_Mode_SlaveRx) || \ + ((MODE) == I2S_Mode_MasterTx) || \ + ((MODE) == I2S_Mode_MasterRx) ) +/** + * @} + */ + +/** @defgroup I2S_Standard + * @{ + */ + +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ + ((STANDARD) == I2S_Standard_MSB) || \ + ((STANDARD) == I2S_Standard_LSB) || \ + ((STANDARD) == I2S_Standard_PCMShort) || \ + ((STANDARD) == I2S_Standard_PCMLong)) +/** + * @} + */ + +/** @defgroup I2S_Data_Format + * @{ + */ + +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ + ((FORMAT) == I2S_DataFormat_16bextended) || \ + ((FORMAT) == I2S_DataFormat_24b) || \ + ((FORMAT) == I2S_DataFormat_32b)) +/** + * @} + */ + +/** @defgroup I2S_MCLK_Output + * @{ + */ + +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ + ((OUTPUT) == I2S_MCLKOutput_Disable)) +/** + * @} + */ + +/** @defgroup I2S_Audio_Frequency + * @{ + */ + +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) +#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_96k) || \ + ((FREQ) == I2S_AudioFreq_48k) || \ + ((FREQ) == I2S_AudioFreq_44k) || \ + ((FREQ) == I2S_AudioFreq_32k) || \ + ((FREQ) == I2S_AudioFreq_22k) || \ + ((FREQ) == I2S_AudioFreq_16k) || \ + ((FREQ) == I2S_AudioFreq_11k) || \ + ((FREQ) == I2S_AudioFreq_8k) || \ + ((FREQ) == I2S_AudioFreq_Default)) +/** + * @} + */ + +/** @defgroup I2S_Clock_Polarity + * @{ + */ + +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ + ((CPOL) == I2S_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_I2S_DMA_transfer_requests + * @{ + */ + +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) +#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) +/** + * @} + */ + +/** @defgroup SPI_NSS_internal_software_mangement + * @{ + */ + +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) +/** + * @} + */ + +/** @defgroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) +/** + * @} + */ + +/** @defgroup SPI_I2S_interrupts_definition + * @{ + */ + +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == SPI_I2S_IT_RXNE) || \ + ((IT) == SPI_I2S_IT_ERR)) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) +#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) +#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ + ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ + ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) +/** + * @} + */ + +/** @defgroup SPI_I2S_flags_definition + * @{ + */ + +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) +#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) +#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ + ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) +/** + * @} + */ + +/** @defgroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions + * @{ + */ + +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_SPI_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_tim.h b/example/libs_stm/inc/stm32f10x/stm32f10x_tim.h new file mode 100644 index 000000000..500c195d2 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_tim.h @@ -0,0 +1,1133 @@ +/** + ****************************************************************************** + * @file stm32f10x_tim.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the TIM firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_TIM_H +#define __STM32F10x_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/** @defgroup TIM_Exported_Types + * @{ + */ + +/** + * @brief TIM Time Base Init structure definition + * @note This sturcture is used with all TIMx except for TIM6 and TIM7. + */ + +typedef struct +{ + uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint16_t TIM_OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + + uint16_t TIM_Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/** + * @brief BDTR structure definition + * @note This sturcture is used only with TIM1 and TIM8. + */ + +typedef struct +{ + + uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/** @defgroup TIM_Exported_constants + * @{ + */ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10)|| \ + ((PERIPH) == TIM11)|| \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM13)|| \ + ((PERIPH) == TIM14)|| \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST1: TIM 1 and 8 */ +#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8)) + +/* LIST2: TIM 1, 8, 15 16 and 17 */ +#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ +#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8)) + +/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */ +#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ +#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)) + +/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */ +#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM15)) + +/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */ +#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM15)) + +/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ +#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM9) || \ + ((PERIPH) == TIM10)|| \ + ((PERIPH) == TIM11)|| \ + ((PERIPH) == TIM12)|| \ + ((PERIPH) == TIM13)|| \ + ((PERIPH) == TIM14)|| \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */ +#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8) || \ + ((PERIPH) == TIM15)|| \ + ((PERIPH) == TIM16)|| \ + ((PERIPH) == TIM17)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ + ((MODE) == TIM_OCMode_Active) || \ + ((MODE) == TIM_OCMode_Inactive) || \ + ((MODE) == TIM_OCMode_Toggle)|| \ + ((MODE) == TIM_OCMode_PWM1) || \ + ((MODE) == TIM_OCMode_PWM2) || \ + ((MODE) == TIM_ForcedAction_Active) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ + ((MODE) == TIM_OPMode_Repetitive)) +/** + * @} + */ + +/** @defgroup TIM_Channel + * @{ + */ + +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) +#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) +/** + * @} + */ + +/** @defgroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ + ((MODE) == TIM_CounterMode_Down) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_state + * @{ + */ + +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_state + * @{ + */ + +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_state + * @{ + */ + +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ + ((CCX) == TIM_CCx_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_N_state + * @{ + */ + +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ + ((CCXN) == TIM_CCxN_Disable)) +/** + * @} + */ + +/** @defgroup Break_Input_enable_disable + * @{ + */ + +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ + ((STATE) == TIM_Break_Disable)) +/** + * @} + */ + +/** @defgroup Break_Polarity + * @{ + */ + +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ + ((POLARITY) == TIM_BreakPolarity_High)) +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/** + * @} + */ + +/** @defgroup Lock_level + * @{ + */ + +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1) || \ + ((LEVEL) == TIM_LOCKLevel_2) || \ + ((LEVEL) == TIM_LOCKLevel_3)) +/** + * @} + */ + +/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ + ((STATE) == TIM_OSSIState_Disable)) +/** + * @} + */ + +/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ + ((STATE) == TIM_OSSRState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ + ((STATE) == TIM_OCIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ + ((STATE) == TIM_OCNIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ + ((POLARITY) == TIM_ICPolarity_Falling)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_interrupt_sources + * @{ + */ + +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) +#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) + +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ + ((IT) == TIM_IT_CC1) || \ + ((IT) == TIM_IT_CC2) || \ + ((IT) == TIM_IT_CC3) || \ + ((IT) == TIM_IT_CC4) || \ + ((IT) == TIM_IT_COM) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ + ((BASE) == TIM_DMABase_CR2) || \ + ((BASE) == TIM_DMABase_SMCR) || \ + ((BASE) == TIM_DMABase_DIER) || \ + ((BASE) == TIM_DMABase_SR) || \ + ((BASE) == TIM_DMABase_EGR) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER) || \ + ((BASE) == TIM_DMABase_CNT) || \ + ((BASE) == TIM_DMABase_PSC) || \ + ((BASE) == TIM_DMABase_ARR) || \ + ((BASE) == TIM_DMABase_RCR) || \ + ((BASE) == TIM_DMABase_CCR1) || \ + ((BASE) == TIM_DMABase_CCR2) || \ + ((BASE) == TIM_DMABase_CCR3) || \ + ((BASE) == TIM_DMABase_CCR4) || \ + ((BASE) == TIM_DMABase_BDTR) || \ + ((BASE) == TIM_DMABase_DCR)) +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length + * @{ + */ + +#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100) +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \ + ((LENGTH) == TIM_DMABurstLength_2Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_3Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_4Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_5Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_6Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_7Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_8Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_9Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_10Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_11Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_12Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_13Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_14Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_15Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_16Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_17Bytes) || \ + ((LENGTH) == TIM_DMABurstLength_18Bytes)) +/** + * @} + */ + +/** @defgroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1) || \ + ((SELECTION) == TIM_TS_TI2FP2) || \ + ((SELECTION) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** + * @} + */ + +/** @defgroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) +#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ + ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** + * @} + */ + +/** @defgroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** + * @} + */ + +/** @defgroup TIM_Forced_Action + * @{ + */ + +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ + ((ACTION) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ + ((MODE) == TIM_EncoderMode_TI2) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** + * @} + */ + + +/** @defgroup TIM_Event_Source + * @{ + */ + +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) + +/** + * @} + */ + +/** @defgroup TIM_Update_Source + * @{ + */ + +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) +/** + * @} + */ + +/** @defgroup TIM_Ouput_Compare_Preload_State + * @{ + */ + +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ + ((STATE) == TIM_OCPreload_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Ouput_Compare_Fast_State + * @{ + */ + +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ + ((STATE) == TIM_OCFast_Disable)) + +/** + * @} + */ + +/** @defgroup TIM_Ouput_Compare_Clear_State + * @{ + */ + +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ + ((STATE) == TIM_OCClear_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Output_Source + * @{ + */ + +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ + ((MODE) == TIM_SlaveMode_Gated) || \ + ((MODE) == TIM_SlaveMode_Trigger) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ + ((FLAG) == TIM_FLAG_CC1) || \ + ((FLAG) == TIM_FLAG_CC2) || \ + ((FLAG) == TIM_FLAG_CC3) || \ + ((FLAG) == TIM_FLAG_CC4) || \ + ((FLAG) == TIM_FLAG_COM) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break) || \ + ((FLAG) == TIM_FLAG_CC1OF) || \ + ((FLAG) == TIM_FLAG_CC2OF) || \ + ((FLAG) == TIM_FLAG_CC3OF) || \ + ((FLAG) == TIM_FLAG_CC4OF)) + + +#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Filter + * @{ + */ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions + * @{ + */ + +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F10x_TIM_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_usart.h b/example/libs_stm/inc/stm32f10x/stm32f10x_usart.h new file mode 100644 index 000000000..b79855a1d --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_usart.h @@ -0,0 +1,411 @@ +/** + ****************************************************************************** + * @file stm32f10x_usart.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the USART + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_USART_H +#define __STM32F10x_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/** @defgroup USART_Exported_Types + * @{ + */ + +/** + * @brief USART Init Structure definition + */ + +typedef struct +{ + uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/** + * @brief USART Clock Init Structure definition + */ + +typedef struct +{ + + uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/** + * @} + */ + +/** @defgroup USART_Exported_Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4) || \ + ((PERIPH) == UART5)) + +#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3)) + +#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == UART4)) +/** @defgroup USART_Word_Length + * @{ + */ + +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ + ((LENGTH) == USART_WordLength_9b)) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits + * @{ + */ + +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) +#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ + ((STOPBITS) == USART_StopBits_0_5) || \ + ((STOPBITS) == USART_StopBits_2) || \ + ((STOPBITS) == USART_StopBits_1_5)) +/** + * @} + */ + +/** @defgroup USART_Parity + * @{ + */ + +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) +#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ + ((PARITY) == USART_Parity_Even) || \ + ((PARITY) == USART_Parity_Odd)) +/** + * @} + */ + +/** @defgroup USART_Mode + * @{ + */ + +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) +#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ + (((CONTROL) == USART_HardwareFlowControl_None) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS) || \ + ((CONTROL) == USART_HardwareFlowControl_CTS) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) +/** + * @} + */ + +/** @defgroup USART_Clock + * @{ + */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ + ((CLOCK) == USART_Clock_Enable)) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity + * @{ + */ + +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) +#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) + +/** + * @} + */ + +/** @defgroup USART_Clock_Phase + * @{ + */ + +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) +#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) + +/** + * @} + */ + +/** @defgroup USART_Last_Bit + * @{ + */ + +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) +#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ + ((LASTBIT) == USART_LastBit_Enable)) +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition + * @{ + */ + +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) +#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) +#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ + ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ + ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ + ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) +#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ + ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) +/** + * @} + */ + +/** @defgroup USART_DMA_Requests + * @{ + */ + +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) +#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) + +/** + * @} + */ + +/** @defgroup USART_WakeUp_methods + * @{ + */ + +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) +#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ + ((WAKEUP) == USART_WakeUp_AddressMark)) +/** + * @} + */ + +/** @defgroup USART_LIN_Break_Detection_Length + * @{ + */ + +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) +#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ + (((LENGTH) == USART_LINBreakDetectLength_10b) || \ + ((LENGTH) == USART_LINBreakDetectLength_11b)) +/** + * @} + */ + +/** @defgroup USART_IrDA_Low_Power + * @{ + */ + +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) +#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ + ((MODE) == USART_IrDAMode_Normal)) +/** + * @} + */ + +/** @defgroup USART_Flags + * @{ + */ + +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) +#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ + ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ + ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ + ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ + ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) + +#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) +#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\ + ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ + || ((USART_FLAG) != USART_FLAG_CTS)) +#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) +#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) +#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions + * @{ + */ + +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); +void USART_SendBreak(USART_TypeDef* USARTx); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_USART_H */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_wwdg.h b/example/libs_stm/inc/stm32f10x/stm32f10x_wwdg.h new file mode 100644 index 000000000..fe238cdb9 --- /dev/null +++ b/example/libs_stm/inc/stm32f10x/stm32f10x_wwdg.h @@ -0,0 +1,114 @@ +/** + ****************************************************************************** + * @file stm32f10x_wwdg.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file contains all the functions prototypes for the WWDG firmware + * library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_WWDG_H +#define __STM32F10x_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ + +/** @defgroup WWDG_Exported_Types + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Constants + * @{ + */ + +/** @defgroup WWDG_Prescaler + * @{ + */ + +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ + ((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup WWDG_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup WWDG_Exported_Functions + * @{ + */ + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F10x_WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/Release_Notes_for_STM32F10x_StdPeriph_Driver.html b/example/libs_stm/src/stm32f10x/Release_Notes_for_STM32F10x_StdPeriph_Driver.html new file mode 100644 index 000000000..018141b98 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/Release_Notes_for_STM32F10x_StdPeriph_Driver.html @@ -0,0 +1,203 @@ + + + + + + +Release Notes for STM32F10x Standard Peripherals Library Drivers + + + + + +
+


+

+
+ + + + + + +
+ + + + + + + + + +
Back to Release page
+

Release +Notes for STM32F10x Standard Peripherals Library Drivers +(StdPeriph_Driver)

+

Copyright 2010 STMicroelectronics

+

+
+

 

+ + + + + + +
+

Contents

+
    +
  1. STM32F10x Standard Peripherals Library +Drivers update History
    2. +
  2. License
    3. +
+ + +

STM32F10x Standard +Peripherals Library Drivers  update History

3.3.0 +- 04/16/2010

+
  1. General
+
  • Add support for STM32F10x XL-density devices.
  • I2C driver: events description and management enhancement.
+
  1. STM32F10x_StdPeriph_Driver
+
  • stm32f10x_dbgmcu.h/.c
    • DBGMCU_Config() function: add new values DBGMCU_TIMx_STOP (x: 9..14) for DBGMCU_Periph parameter.
  • stm32f10x_flash.h/.c: +updated to support Bank2 of XL-density devices (up to 1MByte of Flash +memory). For more details, refer to the description provided within +stm32f10x_flash.c file.
  • stm32f10x_gpio.h/.c
    • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for FSMC_NADV pin and TIM9..11,13,14.
  • stm32f10x_i2c.h/.c: I2C events description and management enhancement.
    • I2C_CheckEvent() +function: updated to check whether the last event contains the +I2C_EVENT  (instead of check whether the last event is equal to +I2C_EVENT)
    • Add +detailed description of I2C events and how to manage them using the +functions provided by this driver. For more information, refer to +stm32f10x_i2c.h and stm32f10x_i2c.c files.
  • stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration
  • stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.
  • stm32f10x_sdio.h: 
    • SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter
      change
        +#define +SDIO_ReadWaitMode_CLK               +  ((uint32_t)0x00000000)
        #define +SDIO_ReadWaitMode_DATA2             +((uint32_t)0x00000001)
      by
        #define +SDIO_ReadWaitMode_CLK               +  ((uint32_t)0x00000001)
        #define +SDIO_ReadWaitMode_DATA2             +((uint32_t)0x00000000)
+

3.2.0 +- 03/01/2010

+
    +
  1. General
    2. +
+
    + +
  • Add support +for STM32 Low-density Value line (STM32F100x4/6) and +Medium-density Value line (STM32F100x8/B) devices.
    • +
  • Almost +peripherals drivers were updated to support Value +line devices features
    • +
  • Drivers limitations fix and enhancements.
    • + +
+
    +
  1. STM32F10x_StdPeriph_Driver
    2. +
+
    +
  • Add new +firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c
    • +
  • Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.
    • +
  • RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.
    • +
  • GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: GPIO_Remap_TIM1_DMA, GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.
    • +
  • USART +driver: add support for Oversampling by 8 mode and onebit method. 2 +functions has been added: USART_OverSampling8Cmd() and +USART_OneBitMethodCmd().
    +
    • +
  • DAC +driver: add new functions handling the DAC under run feature: +DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus() +and DAC_ClearITPendingBit().
    • +
  • DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.
    +
    • +
  • FLASH +driver: the FLASH_EraseOptionBytes() function updated. This is now just +erasing the option bytes without modifying the RDP status either +enabled or disabled.
    • +
  • PWR +driver: the PWR_EnterSTOPMode() function updated. When woken up from +STOP mode, this function resets again the SLEEPDEEP bit in the +Cortex-M3 System Control register to allow Sleep mode entering.
    • + + +
+

License

+

The +enclosed firmware and all the related documentation are not covered by +a License Agreement, if you need such License you can contact your +local STMicroelectronics office.

+

THE +PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO +SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR +ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY +CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY +CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH +THEIR PRODUCTS.

+

 

+
+
+

For +complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers +visit www.st.com/STM32

+
+

+
+
+

 

+
+ \ No newline at end of file diff --git a/example/libs_stm/src/stm32f10x/misc.c b/example/libs_stm/src/stm32f10x/misc.c new file mode 100644 index 000000000..b8349fab9 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/misc.c @@ -0,0 +1,223 @@ +/** + ****************************************************************************** + * @file misc.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "misc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/** @defgroup MISC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Defines + * @{ + */ + +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) +/** + * @} + */ + +/** @defgroup MISC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM + * @arg NVIC_VectTab_FLASH + * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND + * @arg NVIC_LP_SLEEPDEEP + * @arg NVIC_LP_SLEEPONEXIT + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + +/** + * @brief Configures the SysTick clock source. + * @param SysTick_CLKSource: specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); + if (SysTick_CLKSource == SysTick_CLKSource_HCLK) + { + SysTick->CTRL |= SysTick_CLKSource_HCLK; + } + else + { + SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_adc.c b/example/libs_stm/src/stm32f10x/stm32f10x_adc.c new file mode 100644 index 000000000..a027f3304 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_adc.c @@ -0,0 +1,1306 @@ +/** + ****************************************************************************** + * @file stm32f10x_adc.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the ADC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_adc.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup ADC + * @brief ADC driver modules + * @{ + */ + +/** @defgroup ADC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Defines + * @{ + */ + +/* ADC DISCNUM mask */ +#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CR1_DISCEN_Set ((uint32_t)0x00000800) +#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CR1_JAUTO_Set ((uint32_t)0x00000400) +#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CR1 register Mask */ +#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CR2_ADON_Set ((uint32_t)0x00000001) +#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CR2_DMA_Set ((uint32_t)0x00000100) +#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CR2 register Mask */ +#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define SQR3_SQ_Set ((uint32_t)0x0000001F) +#define SQR2_SQ_Set ((uint32_t)0x0000001F) +#define SQR1_SQ_Set ((uint32_t)0x0000001F) + +/* SQR1 register Mask */ +#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define JSQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define JSQR_JL_Set ((uint32_t)0x00300000) +#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SMPR1_SMP_Set ((uint32_t)0x00000007) +#define SMPR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC JDRx registers offset */ +#define JDR_Offset ((uint8_t)0x28) + +/* ADC1 DR register base address */ +#define DR_ADDRESS ((uint32_t)0x4001244C) + +/** + * @} + */ + +/** @defgroup ADC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup ADC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ADCx peripheral registers to their default reset values. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_DeInit(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + if (ADCx == ADC1) + { + /* Enable ADC1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + /* Release ADC1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } + else if (ADCx == ADC2) + { + /* Enable ADC2 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + /* Release ADC2 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + } + else + { + if (ADCx == ADC3) + { + /* Enable ADC3 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); + /* Release ADC3 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); + } + } +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains + * the configuration information for the specified ADC peripheral. + * @retval None + */ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); + + /*---------------------------- ADCx CR1 Configuration -----------------*/ + /* Get the ADCx CR1 value */ + tmpreg1 = ADCx->CR1; + /* Clear DUALMOD and SCAN bits */ + tmpreg1 &= CR1_CLEAR_Mask; + /* Configure ADCx: Dual mode and scan conversion mode */ + /* Set DUALMOD bits according to ADC_Mode value */ + /* Set SCAN bit according to ADC_ScanConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + /* Write to ADCx CR1 */ + ADCx->CR1 = tmpreg1; + + /*---------------------------- ADCx CR2 Configuration -----------------*/ + /* Get the ADCx CR2 value */ + tmpreg1 = ADCx->CR2; + /* Clear CONT, ALIGN and EXTSEL bits */ + tmpreg1 &= CR2_CLEAR_Mask; + /* Configure ADCx: external trigger event and continuous conversion mode */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + /* Write to ADCx CR2 */ + ADCx->CR2 = tmpreg1; + + /*---------------------------- ADCx SQR1 Configuration -----------------*/ + /* Get the ADCx SQR1 value */ + tmpreg1 = ADCx->SQR1; + /* Clear L bits */ + tmpreg1 &= SQR1_CLEAR_Mask; + /* Configure ADCx: regular channel sequence length */ + /* Set L bits according to ADC_NbrOfChannel value */ + tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + /* Write to ADCx SQR1 */ + ADCx->SQR1 = tmpreg1; +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* Initialize the ADC_Mode member */ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + /* initialize the ADC_ScanConvMode member */ + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + /* Initialize the ADC_ExternalTrigConv member */ + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + /* Initialize the ADC_NbrOfChannel member */ + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ADON bit to wake up the ADC from power down mode */ + ADCx->CR2 |= CR2_ADON_Set; + } + else + { + /* Disable the selected ADC peripheral */ + ADCx->CR2 &= CR2_ADON_Reset; + } +} + +/** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx: where x can be 1 or 3 to select the ADC peripheral. + * Note: ADC2 hasn't a DMA capability. + * @param NewState: new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_DMA_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CR2 |= CR2_DMA_Set; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CR2 &= CR2_DMA_Reset; + } +} + +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @param NewState: new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)ADC_IT; + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->CR1 |= itmask; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->CR1 &= (~(uint32_t)itmask); + } +} + +/** + * @brief Resets the selected ADC calibration registers. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_ResetCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Resets the selected ADC calibartion registers */ + ADCx->CR2 |= CR2_RSTCAL_Set; +} + +/** + * @brief Gets the selected ADC reset calibration registers status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC reset calibration registers (SET or RESET). + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of RSTCAL bit */ + if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) + { + /* RSTCAL bit is set */ + bitstatus = SET; + } + else + { + /* RSTCAL bit is reset */ + bitstatus = RESET; + } + /* Return the RSTCAL bit status */ + return bitstatus; +} + +/** + * @brief Starts the selected ADC calibration process. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval None + */ +void ADC_StartCalibration(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Enable the selected ADC calibration process */ + ADCx->CR2 |= CR2_CAL_Set; +} + +/** + * @brief Gets the selected ADC calibration status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC calibration (SET or RESET). + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of CAL bit */ + if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) + { + /* CAL bit is set: calibration on going */ + bitstatus = SET; + } + else + { + /* CAL bit is reset: end of calibration */ + bitstatus = RESET; + } + /* Return the CAL bit status */ + return bitstatus; +} + +/** + * @brief Enables or disables the selected ADC software start conversion . + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC software start conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event and start the selected + ADC conversion */ + ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event and stop the selected + ADC conversion */ + ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; + } +} + +/** + * @brief Gets the selected ADC Software start conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of SWSTART bit */ + if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET) + { + /* SWSTART bit is set */ + bitstatus = SET; + } + else + { + /* SWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the SWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Number: specifies the discontinuous mode regular channel + * count value. This number must be between 1 and 8. + * @retval None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); + /* Get the old register value */ + tmpreg1 = ADCx->CR1; + /* Clear the old discontinuous mode channel count */ + tmpreg1 &= CR1_DISCNUM_Reset; + /* Set the discontinuous mode channel count */ + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + /* Store the new register value */ + ADCx->CR1 = tmpreg1; +} + +/** + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode + * on regular group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC regular discontinuous mode */ + ADCx->CR1 |= CR1_DISCEN_Set; + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + ADCx->CR1 &= CR1_DISCEN_Reset; + } +} + +/** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_REGULAR_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* For Rank 1 to 6 */ + if (Rank < 7) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR3; + /* Calculate the mask to clear */ + tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR3 = tmpreg1; + } + /* For Rank 7 to 12 */ + else if (Rank < 13) + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR2; + /* Calculate the mask to clear */ + tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR2 = tmpreg1; + } + /* For Rank 13 to 16 */ + else + { + /* Get the old register value */ + tmpreg1 = ADCx->SQR1; + /* Calculate the mask to clear */ + tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); + /* Clear the old SQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + /* Set the SQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SQR1 = tmpreg1; + } +} + +/** + * @brief Enables or disables the ADCx conversion through external trigger. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC external trigger start of conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion on external event */ + ADCx->CR2 |= CR2_EXTTRIG_Set; + } + else + { + /* Disable the selected ADC conversion on external event */ + ADCx->CR2 &= CR2_EXTTRIG_Reset; + } +} + +/** + * @brief Returns the last ADCx conversion result data for regular channel. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Return the selected ADC conversion value */ + return (uint16_t) ADCx->DR; +} + +/** + * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. + * @retval The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + /* Return the dual mode conversion value */ + return (*(__IO uint32_t *) DR_ADDRESS); +} + +/** + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC auto injected conversion + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + ADCx->CR1 |= CR1_JAUTO_Set; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + ADCx->CR1 &= CR1_JAUTO_Reset; + } +} + +/** + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC discontinuous mode + * on injected group channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + ADCx->CR1 |= CR1_JDISCEN_Set; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + ADCx->CR1 &= CR1_JDISCEN_Reset; + } +} + +/** + * @brief Configures the ADCx external trigger for injected channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. + * This parameter can be one of the following values: + * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) + * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) + * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8 + * capture compare4 event selected (for ADC1 and ADC2) + * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) + * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not + * by external trigger (for ADC1, ADC2 and ADC3) + * @retval None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); + /* Get the old register value */ + tmpreg = ADCx->CR2; + /* Clear the old external event selection for injected group */ + tmpreg &= CR2_JEXTSEL_Reset; + /* Set the external event selection for injected group */ + tmpreg |= ADC_ExternalTrigInjecConv; + /* Store the new register value */ + ADCx->CR2 = tmpreg; +} + +/** + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC external trigger start of + * injected conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC external event selection for injected group */ + ADCx->CR2 |= CR2_JEXTTRIG_Set; + } + else + { + /* Disable the selected ADC external event selection for injected group */ + ADCx->CR2 &= CR2_JEXTTRIG_Reset; + } +} + +/** + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param NewState: new state of the selected ADC software start injected conversion. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected ADC conversion for injected group on external event and start the selected + ADC injected conversion */ + ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; + } + else + { + /* Disable the selected ADC conversion on external event for injected group and stop the selected + ADC injected conversion */ + ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/** + * @brief Gets the selected ADC Software start injected conversion Status. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @retval The new state of ADC software start injected conversion (SET or RESET). + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + /* Check the status of JSWSTART bit */ + if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET) + { + /* JSWSTART bit is set */ + bitstatus = SET; + } + else + { + /* JSWSTART bit is reset */ + bitstatus = RESET; + } + /* Return the JSWSTART bit status */ + return bitstatus; +} + +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4. + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + assert_param(IS_ADC_INJECTED_RANK(Rank)); + assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); + /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ + if (ADC_Channel > ADC_Channel_9) + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR1; + /* Calculate the mask to clear */ + tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR1 = tmpreg1; + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Get the old register value */ + tmpreg1 = ADCx->SMPR2; + /* Calculate the mask to clear */ + tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); + /* Clear the old channel sample time */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set */ + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + /* Set the new channel sample time */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->SMPR2 = tmpreg1; + } + /* Rank configuration */ + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Get JL value: Number = JL+1 */ + tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; + /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Clear the old JSQx bits for the selected rank */ + tmpreg1 &= ~tmpreg2; + /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + /* Set the JSQx bits for the selected rank */ + tmpreg1 |= tmpreg2; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Configures the sequencer length for injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param Length: The sequencer length. + * This parameter must be a number between 1 to 4. + * @retval None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_LENGTH(Length)); + + /* Get the old register value */ + tmpreg1 = ADCx->JSQR; + /* Clear the old injected sequnence lenght JL bits */ + tmpreg1 &= JSQR_JL_Reset; + /* Set the injected sequnence lenght JL bits */ + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + /* Store the new register value */ + ADCx->JSQR = tmpreg1; +} + +/** + * @brief Set the injected channels conversion value offset + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the ADC injected channel to set its offset. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @param Offset: the offset value for the selected ADC injected channel + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + assert_param(IS_ADC_OFFSET(Offset)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + /* Set the selected injected channel data offset */ + *(__IO uint32_t *) tmp = (uint32_t)Offset; +} + +/** + * @brief Returns the ADC injected channel conversion result + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_InjectedChannel: the converted ADC injected channel. + * This parameter can be one of the following values: + * @arg ADC_InjectedChannel_1: Injected Channel1 selected + * @arg ADC_InjectedChannel_2: Injected Channel2 selected + * @arg ADC_InjectedChannel_3: Injected Channel3 selected + * @arg ADC_InjectedChannel_4: Injected Channel4 selected + * @retval The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + JDR_Offset; + + /* Returns the selected injected channel conversion data value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +/** + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. + * This parameter can be one of the following values: + * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel + * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel + * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel + * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel + * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel + * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels + * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog + * @retval None + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear AWDEN, AWDENJ and AWDSGL bits */ + tmpreg &= CR1_AWDMode_Reset; + /* Set the analog watchdog enable mode */ + tmpreg |= ADC_AnalogWatchdog; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Configures the high and low thresholds of the analog watchdog. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param HighThreshold: the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * @param LowThreshold: the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * @retval None + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_THRESHOLD(HighThreshold)); + assert_param(IS_ADC_THRESHOLD(LowThreshold)); + /* Set the ADCx high threshold */ + ADCx->HTR = HighThreshold; + /* Set the ADCx low threshold */ + ADCx->LTR = LowThreshold; +} + +/** + * @brief Configures the analog watchdog guarded single channel + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @retval None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(ADC_Channel)); + /* Get the old register value */ + tmpreg = ADCx->CR1; + /* Clear the Analog watchdog channel select bits */ + tmpreg &= CR1_AWDCH_Reset; + /* Set the Analog watchdog channel */ + tmpreg |= ADC_Channel; + /* Store the new register value */ + ADCx->CR1 = tmpreg; +} + +/** + * @brief Enables or disables the temperature sensor and Vrefint channel. + * @param NewState: new state of the temperature sensor. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the temperature sensor and Vrefint channel*/ + ADC1->CR2 |= CR2_TSVREFE_Set; + } + else + { + /* Disable the temperature sensor and Vrefint channel*/ + ADC1->CR2 &= CR2_TSVREFE_Reset; + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @retval The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + /* Check the status of the specified ADC flag */ + if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_AWD: Analog watchdog flag + * @arg ADC_FLAG_EOC: End of conversion flag + * @arg ADC_FLAG_JEOC: End of injected group conversion flag + * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag + * @arg ADC_FLAG_STRT: Start of regular group conversion flag + * @retval None + */ +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + /* Clear the selected ADC flags */ + ADCx->SR = ~(uint32_t)ADC_FLAG; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @retval The new state of ADC_IT (SET or RESET). + */ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = ADC_IT >> 8; + /* Get the ADC_IT enable bit status */ + enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ; + /* Check the status of the specified ADC interrupt */ + if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the ADCxs interrupt pending bits. + * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ADC_IT_EOC: End of conversion interrupt mask + * @arg ADC_IT_AWD: Analog watchdog interrupt mask + * @arg ADC_IT_JEOC: End of injected conversion interrupt mask + * @retval None + */ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_IT(ADC_IT)); + /* Get the ADC IT index */ + itmask = (uint8_t)(ADC_IT >> 8); + /* Clear the selected ADC interrupt pending bits */ + ADCx->SR = ~(uint32_t)itmask; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_bkp.c b/example/libs_stm/src/stm32f10x/stm32f10x_bkp.c new file mode 100644 index 000000000..de065648f --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_bkp.c @@ -0,0 +1,311 @@ +/** + ****************************************************************************** + * @file stm32f10x_bkp.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the BKP firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_bkp.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup BKP + * @brief BKP driver modules + * @{ + */ + +/** @defgroup BKP_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Defines + * @{ + */ + +/* ------------ BKP registers bit address in the alias region --------------- */ +#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) + +/* --- CR Register ----*/ + +/* Alias word address of TPAL bit */ +#define CR_OFFSET (BKP_OFFSET + 0x30) +#define TPAL_BitNumber 0x01 +#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) + +/* Alias word address of TPE bit */ +#define TPE_BitNumber 0x00 +#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of TPIE bit */ +#define CSR_OFFSET (BKP_OFFSET + 0x34) +#define TPIE_BitNumber 0x02 +#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) + +/* Alias word address of TIF bit */ +#define TIF_BitNumber 0x09 +#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) + +/* Alias word address of TEF bit */ +#define TEF_BitNumber 0x08 +#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) + +/* ---------------------- BKP registers bit mask ------------------------ */ + +/* RTCCR register bit mask */ +#define RTCCR_CAL_Mask ((uint16_t)0xFF80) +#define RTCCR_Mask ((uint16_t)0xFC7F) + +/* CSR register bit mask */ +#define CSR_CTE_Set ((uint16_t)0x0001) +#define CSR_CTI_Set ((uint16_t)0x0002) + +/** + * @} + */ + + +/** @defgroup BKP_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup BKP_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * @param None + * @retval None + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/** + * @brief Configures the Tamper Pin active level. + * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. + * This parameter can be one of the following values: + * @arg BKP_TamperPinLevel_High: Tamper pin active on high level + * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level + * @retval None + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + /* Check the parameters */ + assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); + *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; +} + +/** + * @brief Enables or disables the Tamper Pin activation. + * @param NewState: new state of the Tamper Pin activation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Tamper Pin Interrupt. + * @param NewState: new state of the Tamper Pin Interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void BKP_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; +} + +/** + * @brief Select the RTC output source to output on the Tamper pin. + * @param BKP_RTCOutputSource: specifies the RTC output source. + * This parameter can be one of the following values: + * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. + * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency + * divided by 64 on the Tamper pin. + * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on + * the Tamper pin. + * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on + * the Tamper pin. + * @retval None + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); + tmpreg = BKP->RTCCR; + /* Clear CCO, ASOE and ASOS bits */ + tmpreg &= RTCCR_Mask; + + /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ + tmpreg |= BKP_RTCOutputSource; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** + * @brief Sets RTC Clock Calibration value. + * @param CalibrationValue: specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x7F. + * @retval None + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); + tmpreg = BKP->RTCCR; + /* Clear CAL[6:0] bits */ + tmpreg &= RTCCR_CAL_Mask; + /* Set CAL[6:0] bits according to CalibrationValue value */ + tmpreg |= CalibrationValue; + /* Store the new value */ + BKP->RTCCR = tmpreg; +} + +/** + * @brief Writes user data to the specified Data Backup Register. + * @param BKP_DR: specifies the Data Backup Register. + * This parameter can be BKP_DRx where x:[1, 42] + * @param Data: data to write + * @retval None + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Reads data from the specified Data Backup Register. + * @param BKP_DR: specifies the Data Backup Register. + * This parameter can be BKP_DRx where x:[1, 42] + * @retval The content of the specified Data Backup Register + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_BKP_DR(BKP_DR)); + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Checks whether the Tamper Pin Event flag is set or not. + * @param None + * @retval The new state of the Tamper Pin Event flag (SET or RESET). + */ +FlagStatus BKP_GetFlagStatus(void) +{ + return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); +} + +/** + * @brief Clears Tamper Pin Event pending flag. + * @param None + * @retval None + */ +void BKP_ClearFlag(void) +{ + /* Set CTE bit to clear Tamper Pin Event flag */ + BKP->CSR |= CSR_CTE_Set; +} + +/** + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * @param None + * @retval The new state of the Tamper Pin Interrupt (SET or RESET). + */ +ITStatus BKP_GetITStatus(void) +{ + return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); +} + +/** + * @brief Clears Tamper Pin Interrupt pending bit. + * @param None + * @retval None + */ +void BKP_ClearITPendingBit(void) +{ + /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ + BKP->CSR |= CSR_CTI_Set; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_can.c b/example/libs_stm/src/stm32f10x/stm32f10x_can.c new file mode 100644 index 000000000..537f333ba --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_can.c @@ -0,0 +1,990 @@ +/** + ****************************************************************************** + * @file stm32f10x_can.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the CAN firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_can.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CAN + * @brief CAN driver modules + * @{ + */ + +/** @defgroup CAN_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Defines + * @{ + */ + +/* CAN Master Control Register bits */ +#define MCR_INRQ ((uint32_t)0x00000001) /* Initialization request */ +#define MCR_SLEEP ((uint32_t)0x00000002) /* Sleep mode request */ +#define MCR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO priority */ +#define MCR_RFLM ((uint32_t)0x00000008) /* Receive FIFO locked mode */ +#define MCR_NART ((uint32_t)0x00000010) /* No automatic retransmission */ +#define MCR_AWUM ((uint32_t)0x00000020) /* Automatic wake up mode */ +#define MCR_ABOM ((uint32_t)0x00000040) /* Automatic bus-off management */ +#define MCR_TTCM ((uint32_t)0x00000080) /* time triggered communication */ +#define MCR_RESET ((uint32_t)0x00008000) /* time triggered communication */ +#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ + +/* CAN Master Status Register bits */ +#define MSR_INAK ((uint32_t)0x00000001) /* Initialization acknowledge */ +#define MSR_WKUI ((uint32_t)0x00000008) /* Wake-up interrupt */ +#define MSR_SLAKI ((uint32_t)0x00000010) /* Sleep acknowledge interrupt */ + +/* CAN Transmit Status Register bits */ +#define TSR_RQCP0 ((uint32_t)0x00000001) /* Request completed mailbox0 */ +#define TSR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of mailbox0 */ +#define TSR_ABRQ0 ((uint32_t)0x00000080) /* Abort request for mailbox0 */ +#define TSR_RQCP1 ((uint32_t)0x00000100) /* Request completed mailbox1 */ +#define TSR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of mailbox1 */ +#define TSR_ABRQ1 ((uint32_t)0x00008000) /* Abort request for mailbox1 */ +#define TSR_RQCP2 ((uint32_t)0x00010000) /* Request completed mailbox2 */ +#define TSR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of mailbox2 */ +#define TSR_ABRQ2 ((uint32_t)0x00800000) /* Abort request for mailbox2 */ +#define TSR_TME0 ((uint32_t)0x04000000) /* Transmit mailbox 0 empty */ +#define TSR_TME1 ((uint32_t)0x08000000) /* Transmit mailbox 1 empty */ +#define TSR_TME2 ((uint32_t)0x10000000) /* Transmit mailbox 2 empty */ + +/* CAN Receive FIFO 0 Register bits */ +#define RF0R_FULL0 ((uint32_t)0x00000008) /* FIFO 0 full */ +#define RF0R_FOVR0 ((uint32_t)0x00000010) /* FIFO 0 overrun */ +#define RF0R_RFOM0 ((uint32_t)0x00000020) /* Release FIFO 0 output mailbox */ + +/* CAN Receive FIFO 1 Register bits */ +#define RF1R_FULL1 ((uint32_t)0x00000008) /* FIFO 1 full */ +#define RF1R_FOVR1 ((uint32_t)0x00000010) /* FIFO 1 overrun */ +#define RF1R_RFOM1 ((uint32_t)0x00000020) /* Release FIFO 1 output mailbox */ + +/* CAN Error Status Register bits */ +#define ESR_EWGF ((uint32_t)0x00000001) /* Error warning flag */ +#define ESR_EPVF ((uint32_t)0x00000002) /* Error passive flag */ +#define ESR_BOFF ((uint32_t)0x00000004) /* Bus-off flag */ + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ + +/* CAN Filter Master Register bits */ +#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ + +/* Time out for INAK bit */ +#define INAK_TimeOut ((uint32_t)0x0000FFFF) + +/* Time out for SLAK bit */ +#define SLAK_TimeOut ((uint32_t)0x0000FFFF) + +/** + * @} + */ + +/** @defgroup CAN_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup CAN_Private_FunctionPrototypes + * @{ + */ + +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + +/** + * @} + */ + +/** @defgroup CAN_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CAN peripheral registers to their default reset values. + * @param CANx: where x can be 1 or 2 to select the CAN peripheral. + * @retval None. + */ +void CAN_DeInit(CAN_TypeDef* CANx) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + if (CANx == CAN1) + { + /* Enable CAN1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + /* Release CAN1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + } + else + { + /* Enable CAN2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + /* Release CAN2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + } +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that + * contains the configuration information for the CAN peripheral. + * @retval Constant indicates initialization succeed which will be + * CANINITFAILED or CANINITOK. + */ +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) +{ + uint8_t InitStatus = CANINITFAILED; + uint32_t wait_ack = 0x00000000; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); + assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); + assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); + assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); + assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); + assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); + assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); + + /* exit from sleep mode */ + CANx->MCR &= ~MCR_SLEEP; + + /* Request initialisation */ + CANx->MCR |= MCR_INRQ ; + + /* Wait the acknowledge */ + while (((CANx->MSR & MSR_INAK) != MSR_INAK) && (wait_ack != INAK_TimeOut)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSR & MSR_INAK) != MSR_INAK) + { + InitStatus = CANINITFAILED; + } + else + { + /* Set the time triggered communication mode */ + if (CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->MCR |= MCR_TTCM; + } + else + { + CANx->MCR &= ~MCR_TTCM; + } + + /* Set the automatic bus-off management */ + if (CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->MCR |= MCR_ABOM; + } + else + { + CANx->MCR &= ~MCR_ABOM; + } + + /* Set the automatic wake-up mode */ + if (CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->MCR |= MCR_AWUM; + } + else + { + CANx->MCR &= ~MCR_AWUM; + } + + /* Set the no automatic retransmission */ + if (CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->MCR |= MCR_NART; + } + else + { + CANx->MCR &= ~MCR_NART; + } + + /* Set the receive FIFO locked mode */ + if (CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->MCR |= MCR_RFLM; + } + else + { + CANx->MCR &= ~MCR_RFLM; + } + + /* Set the transmit FIFO priority */ + if (CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->MCR |= MCR_TXFP; + } + else + { + CANx->MCR &= ~MCR_TXFP; + } + + /* Set the bit timing register */ + CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + + /* Request leave initialisation */ + CANx->MCR &= ~MCR_INRQ; + + /* Wait the acknowledge */ + wait_ack = 0x00; + + while (((CANx->MSR & MSR_INAK) == MSR_INAK) && (wait_ack != INAK_TimeOut)) + { + wait_ack++; + } + + /* ...and check acknowledged */ + if ((CANx->MSR & MSR_INAK) == MSR_INAK) + { + InitStatus = CANINITFAILED; + } + else + { + InitStatus = CANINITOK ; + } + } + + /* At this step, return the status of initialization */ + return InitStatus; +} + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration information. + * @retval None. + */ +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + /* Check the parameters */ + assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); + assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); + assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); + + filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber; + + /* Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + + /* Filter Deactivation */ + CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; + + /* Filter Scale */ + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + /* 16-bit scale for the filter */ + CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + /* 32-bit scale for the filter */ + CAN1->FS1R |= filter_number_bit_pos; + /* 32-bit identifier or First 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + /* 32-bit mask or Second 32-bit identifier */ + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + /* Filter Mode */ + if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + /*Id/Mask mode for the filter*/ + CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /*Identifier list mode for the filter*/ + CAN1->FM1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter FIFO assignment */ + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0) + { + /* FIFO 0 assignation for the filter */ + CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; + } + + if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1) + { + /* FIFO 1 assignation for the filter */ + CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; + } + + /* Filter activation */ + if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FA1R |= filter_number_bit_pos; + } + + /* Leave the initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Fills each CAN_InitStruct member with its default value. + * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which + * will be initialized. + * @retval None. + */ +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) +{ + /* Reset CAN init structure parameters values */ + /* Initialize the time triggered communication mode */ + CAN_InitStruct->CAN_TTCM = DISABLE; + /* Initialize the automatic bus-off management */ + CAN_InitStruct->CAN_ABOM = DISABLE; + /* Initialize the automatic wake-up mode */ + CAN_InitStruct->CAN_AWUM = DISABLE; + /* Initialize the no automatic retransmission */ + CAN_InitStruct->CAN_NART = DISABLE; + /* Initialize the receive FIFO locked mode */ + CAN_InitStruct->CAN_RFLM = DISABLE; + /* Initialize the transmit FIFO priority */ + CAN_InitStruct->CAN_TXFP = DISABLE; + /* Initialize the CAN_Mode member */ + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + /* Initialize the CAN_SJW member */ + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + /* Initialize the CAN_BS1 member */ + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + /* Initialize the CAN_BS2 member */ + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + /* Initialize the CAN_Prescaler member */ + CAN_InitStruct->CAN_Prescaler = 1; +} + +/** + * @brief Select the start bank filter for slave CAN. + * @note This function applies only to STM32 Connectivity line devices. + * @param CAN_BankNumber: Select the start slave bank filter from 1..27. + * @retval None. + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); + /* enter Initialisation mode for the filter */ + CAN1->FMR |= FMR_FINIT; + /* Select the start slave bank */ + CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; + CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; + /* Leave Initialisation mode for the filter */ + CAN1->FMR &= ~FMR_FINIT; +} + +/** + * @brief Enables or disables the specified CAN interrupts. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. + * This parameter can be: CAN_IT_TME, CAN_IT_FMP0, CAN_IT_FF0, + * CAN_IT_FOV0, CAN_IT_FMP1, CAN_IT_FF1, + * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, + * CAN_IT_LEC, CAN_IT_ERR, CAN_IT_WKU or + * CAN_IT_SLK. + * @param NewState: new state of the CAN interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_ITConfig(CAN_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected CAN interrupt */ + CANx->IER |= CAN_IT; + } + else + { + /* Disable the selected CAN interrupt */ + CANx->IER &= ~CAN_IT; + } +} + +/** + * @brief Initiates the transmission of a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param TxMessage: pointer to a structure which contains CAN Id, CAN + * DLC and CAN datas. + * @retval The number of the mailbox that is used for transmission + * or CAN_NO_MB if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) +{ + uint8_t transmit_mailbox = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); + assert_param(IS_CAN_RTR(TxMessage->RTR)); + assert_param(IS_CAN_DLC(TxMessage->DLC)); + + /* Select one empty transmit mailbox */ + if ((CANx->TSR&TSR_TME0) == TSR_TME0) + { + transmit_mailbox = 0; + } + else if ((CANx->TSR&TSR_TME1) == TSR_TME1) + { + transmit_mailbox = 1; + } + else if ((CANx->TSR&TSR_TME2) == TSR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_NO_MB; + } + + if (transmit_mailbox != CAN_NO_MB) + { + /* Set up the Id */ + CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; + if (TxMessage->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(TxMessage->StdId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR); + } + else + { + assert_param(IS_CAN_EXTID(TxMessage->ExtId)); + CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE | + TxMessage->RTR); + } + + + /* Set up the DLC */ + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; + + /* Set up the data field */ + CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + /* Request transmission */ + CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; + } + return transmit_mailbox; +} + +/** + * @brief Checks the transmission of a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param TransmitMailbox: the number of the mailbox that is used for transmission. + * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) +{ + /* RQCP, TXOK and TME bits */ + uint8_t state = 0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); + switch (TransmitMailbox) + { + case (0): state |= (uint8_t)((CANx->TSR & TSR_RQCP0) << 2); + state |= (uint8_t)((CANx->TSR & TSR_TXOK0) >> 0); + state |= (uint8_t)((CANx->TSR & TSR_TME0) >> 26); + break; + case (1): state |= (uint8_t)((CANx->TSR & TSR_RQCP1) >> 6); + state |= (uint8_t)((CANx->TSR & TSR_TXOK1) >> 8); + state |= (uint8_t)((CANx->TSR & TSR_TME1) >> 27); + break; + case (2): state |= (uint8_t)((CANx->TSR & TSR_RQCP2) >> 14); + state |= (uint8_t)((CANx->TSR & TSR_TXOK2) >> 16); + state |= (uint8_t)((CANx->TSR & TSR_TME2) >> 28); + break; + default: + state = CANTXFAILED; + break; + } + switch (state) + { + /* transmit pending */ + case (0x0): state = CANTXPENDING; + break; + /* transmit failed */ + case (0x5): state = CANTXFAILED; + break; + /* transmit succedeed */ + case (0x7): state = CANTXOK; + break; + default: + state = CANTXFAILED; + break; + } + return state; +} + +/** + * @brief Cancels a transmit request. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param Mailbox: Mailbox number. + * @retval None. + */ +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); + /* abort transmission */ + switch (Mailbox) + { + case (0): CANx->TSR |= TSR_ABRQ0; + break; + case (1): CANx->TSR |= TSR_ABRQ1; + break; + case (2): CANx->TSR |= TSR_ABRQ2; + break; + default: + break; + } +} + +/** + * @brief Releases a FIFO. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. + * @retval None. + */ +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Release FIFO0 */ + if (FIFONumber == CAN_FIFO0) + { + CANx->RF0R = RF0R_RFOM0; + } + /* Release FIFO1 */ + else /* FIFONumber == CAN_FIFO1 */ + { + CANx->RF1R = RF1R_RFOM1; + } +} + +/** + * @brief Returns the number of pending messages. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @retval NbMessage which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) +{ + uint8_t message_pending=0; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + if (FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); + } + else if (FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); + } + else + { + message_pending = 0; + } + return message_pending; +} + +/** + * @brief Receives a message. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. + * @param RxMessage: pointer to a structure receive message which + * contains CAN Id, CAN DLC, CAN datas and FMI number. + * @retval None. + */ +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FIFO(FIFONumber)); + /* Get the Id */ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; + if (RxMessage->IDE == CAN_ID_STD) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; + /* Get the DLC */ + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; + /* Get the FMI */ + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); + /* Get the data field */ + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); + /* Release the FIFO */ + CAN_FIFORelease(CANx, FIFONumber); +} + +/** + * @brief Enables or disables the DBG Freeze for CAN. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param NewState: new state of the CAN peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Debug Freeze */ + CANx->MCR |= MCR_DBF; + } + else + { + /* Disable Debug Freeze */ + CANx->MCR &= ~MCR_DBF; + } +} + +/** + * @brief Enters the low power mode. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case. + */ +uint8_t CAN_Sleep(CAN_TypeDef* CANx) +{ + uint8_t sleepstatus = CANSLEEPFAILED; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Request Sleep mode */ + CANx->MCR = (((CANx->MCR) & (uint32_t)(~MCR_INRQ)) | MCR_SLEEP); + + /* Sleep mode status */ + if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) + { + /* Sleep mode not entered */ + sleepstatus = CANSLEEPOK; + } + /* At this step, sleep mode status */ + return (uint8_t)sleepstatus; +} + +/** + * @brief Wakes the CAN up. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case. + */ +uint8_t CAN_WakeUp(CAN_TypeDef* CANx) +{ + uint32_t wait_slak = SLAK_TimeOut ; + uint8_t wakeupstatus = CANWAKEUPFAILED; + + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + + /* Wake up request */ + CANx->MCR &= ~MCR_SLEEP; + + /* Sleep mode status */ + while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) + { + wait_slak--; + } + if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) + { + /* Sleep mode exited */ + wakeupstatus = CANWAKEUPOK; + } + /* At this step, sleep mode status */ + return (uint8_t)wakeupstatus; +} + +/** + * @brief Checks whether the specified CAN flag is set or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to check. + * This parameter can be: CAN_FLAG_EWG, CAN_FLAG_EPV or CAN_FLAG_BOF. + * @retval The new state of CAN_FLAG (SET or RESET). + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FLAG(CAN_FLAG)); + /* Check the status of the specified CAN flag */ + if ((CANx->ESR & CAN_FLAG) != (uint32_t)RESET) + { + /* CAN_FLAG is set */ + bitstatus = SET; + } + else + { + /* CAN_FLAG is reset */ + bitstatus = RESET; + } + /* Return the CAN_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CAN's pending flags. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_FLAG: specifies the flag to clear. + * @retval None. + */ +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_FLAG(CAN_FLAG)); + /* Clear the selected CAN flags */ + CANx->ESR &= ~CAN_FLAG; +} + +/** + * @brief Checks whether the specified CAN interrupt has occurred or not. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the CAN interrupt source to check. + * This parameter can be: CAN_IT_RQCP0, CAN_IT_RQCP1, CAN_IT_RQCP2, + * CAN_IT_FF0, CAN_IT_FOV0, CAN_IT_FF1, + * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, + * CAN_IT_BOF, CAN_IT_WKU or CAN_IT_SLK. + * @retval The new state of CAN_IT (SET or RESET). + */ +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + ITStatus pendingbitstatus = RESET; + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_ITStatus(CAN_IT)); + switch (CAN_IT) + { + case CAN_IT_RQCP0: + pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP0); + break; + case CAN_IT_RQCP1: + pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP1); + break; + case CAN_IT_RQCP2: + pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP2); + break; + case CAN_IT_FF0: + pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FULL0); + break; + case CAN_IT_FOV0: + pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FOVR0); + break; + case CAN_IT_FF1: + pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FULL1); + break; + case CAN_IT_FOV1: + pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FOVR1); + break; + case CAN_IT_EWG: + pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EWGF); + break; + case CAN_IT_EPV: + pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EPVF); + break; + case CAN_IT_BOF: + pendingbitstatus = CheckITStatus(CANx->ESR, ESR_BOFF); + break; + case CAN_IT_SLK: + pendingbitstatus = CheckITStatus(CANx->MSR, MSR_SLAKI); + break; + case CAN_IT_WKU: + pendingbitstatus = CheckITStatus(CANx->MSR, MSR_WKUI); + break; + default : + pendingbitstatus = RESET; + break; + } + /* Return the CAN_IT status */ + return pendingbitstatus; +} + +/** + * @brief Clears the CANs interrupt pending bits. + * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. + * @param CAN_IT: specifies the interrupt pending bit to clear. + * @retval None. + */ +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) +{ + /* Check the parameters */ + assert_param(IS_CAN_ALL_PERIPH(CANx)); + assert_param(IS_CAN_ITStatus(CAN_IT)); + switch (CAN_IT) + { + case CAN_IT_RQCP0: + CANx->TSR = TSR_RQCP0; /* rc_w1*/ + break; + case CAN_IT_RQCP1: + CANx->TSR = TSR_RQCP1; /* rc_w1*/ + break; + case CAN_IT_RQCP2: + CANx->TSR = TSR_RQCP2; /* rc_w1*/ + break; + case CAN_IT_FF0: + CANx->RF0R = RF0R_FULL0; /* rc_w1*/ + break; + case CAN_IT_FOV0: + CANx->RF0R = RF0R_FOVR0; /* rc_w1*/ + break; + case CAN_IT_FF1: + CANx->RF1R = RF1R_FULL1; /* rc_w1*/ + break; + case CAN_IT_FOV1: + CANx->RF1R = RF1R_FOVR1; /* rc_w1*/ + break; + case CAN_IT_EWG: + CANx->ESR &= ~ ESR_EWGF; /* rw */ + break; + case CAN_IT_EPV: + CANx->ESR &= ~ ESR_EPVF; /* rw */ + break; + case CAN_IT_BOF: + CANx->ESR &= ~ ESR_BOFF; /* rw */ + break; + case CAN_IT_WKU: + CANx->MSR = MSR_WKUI; /* rc_w1*/ + break; + case CAN_IT_SLK: + CANx->MSR = MSR_SLAKI; /* rc_w1*/ + break; + default : + break; + } +} + +/** + * @brief Checks whether the CAN interrupt has occurred or not. + * @param CAN_Reg: specifies the CAN interrupt register to check. + * @param It_Bit: specifies the interrupt source bit to check. + * @retval The new state of the CAN Interrupt (SET or RESET). + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if ((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + /* CAN_IT is set */ + pendingbitstatus = SET; + } + else + { + /* CAN_IT is reset */ + pendingbitstatus = RESET; + } + return pendingbitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_cec.c b/example/libs_stm/src/stm32f10x/stm32f10x_cec.c new file mode 100644 index 000000000..4ae244569 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_cec.c @@ -0,0 +1,432 @@ +/** + ****************************************************************************** + * @file stm32f10x_cec.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the CEC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_cec.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CEC + * @brief CEC driver modules + * @{ + */ + +/** @defgroup CEC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Defines + * @{ + */ + +/* ------------ CEC registers bit address in the alias region ----------- */ +#define CEC_OFFSET (CEC_BASE - PERIPH_BASE) + +/* --- CFGR Register ---*/ + +/* Alias word address of PE bit */ +#define CFGR_OFFSET (CEC_OFFSET + 0x00) +#define PE_BitNumber 0x00 +#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) + +/* Alias word address of IE bit */ +#define IE_BitNumber 0x01 +#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of TSOM bit */ +#define CSR_OFFSET (CEC_OFFSET + 0x10) +#define TSOM_BitNumber 0x00 +#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) + +/* Alias word address of TEOM bit */ +#define TEOM_BitNumber 0x01 +#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) + +#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Macros + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Variables + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + + +/** @defgroup CEC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the CEC peripheral registers to their default reset + * values. + * @param None + * @retval None + */ +void CEC_DeInit(void) +{ + /* Enable CEC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); + /* Release CEC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); +} + + +/** + * @brief Initializes the CEC peripheral according to the specified + * parameters in the CEC_InitStruct. + * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that + * contains the configuration information for the specified + * CEC peripheral. + * @retval None + */ +void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); + assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); + + /*---------------------------- CEC CFGR Configuration -----------------*/ + /* Get the CEC CFGR value */ + tmpreg = CEC->CFGR; + + /* Clear BTEM and BPEM bits */ + tmpreg &= CFGR_CLEAR_Mask; + + /* Configure CEC: Bit Timing Error and Bit Period Error */ + tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); + + /* Write to CEC CFGR register*/ + CEC->CFGR = tmpreg; + +} + +/** + * @brief Enables or disables the specified CEC peripheral. + * @param NewState: new state of the CEC peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; + + if(NewState == DISABLE) + { + /* Wait until the PE bit is cleared by hardware (Idle Line detected) */ + while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) + { + } + } +} + +/** + * @brief Enables or disables the CEC interrupt. + * @param NewState: new state of the CEC interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_ITConfig(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; +} + +/** + * @brief Defines the Own Address of the CEC device. + * @param CEC_OwnAddress: The CEC own address + * @retval None + */ +void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) +{ + /* Check the parameters */ + assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); + + /* Set the CEC own address */ + CEC->OAR = CEC_OwnAddress; +} + +/** + * @brief Sets the CEC prescaler value. + * @param CEC_Prescaler: CEC prescaler new value + * @retval None + */ +void CEC_SetPrescaler(uint16_t CEC_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); + + /* Set the Prescaler value*/ + CEC->PRES = CEC_Prescaler; +} + +/** + * @brief Transmits single data through the CEC peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void CEC_SendDataByte(uint8_t Data) +{ + /* Transmit Data */ + CEC->TXD = Data ; +} + + +/** + * @brief Returns the most recent received data by the CEC peripheral. + * @param None + * @retval The received data. + */ +uint8_t CEC_ReceiveDataByte(void) +{ + /* Receive Data */ + return (uint8_t)(CEC->RXD); +} + +/** + * @brief Starts a new message. + * @param None + * @retval None + */ +void CEC_StartOfMessage(void) +{ + /* Starts of new message */ + *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; +} + +/** + * @brief Transmits message with or without an EOM bit. + * @param NewState: new state of the CEC Tx End Of Message. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CEC_EndOfMessageCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* The data byte will be transmitted with or without an EOM bit*/ + *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; +} + +/** + * @brief Gets the CEC flag status + * @param CEC_FLAG: specifies the CEC flag to check. + * This parameter can be one of the following values: + * @arg CEC_FLAG_BTE: Bit Timing Error + * @arg CEC_FLAG_BPE: Bit Period Error + * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error + * @arg CEC_FLAG_SBE: Start Bit Error + * @arg CEC_FLAG_ACKE: Block Acknowledge Error + * @arg CEC_FLAG_LINE: Line Error + * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error + * @arg CEC_FLAG_TEOM: Tx End Of Message + * @arg CEC_FLAG_TERR: Tx Error + * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished + * @arg CEC_FLAG_RSOM: Rx Start Of Message + * @arg CEC_FLAG_REOM: Rx End Of Message + * @arg CEC_FLAG_RERR: Rx Error + * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished + * @retval The new state of CEC_FLAG (SET or RESET) + */ +FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t cecreg = 0, cecbase = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); + + /* Get the CEC peripheral base address */ + cecbase = (uint32_t)(CEC_BASE); + + /* Read flag register index */ + cecreg = CEC_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + CEC_FLAG &= FLAG_Mask; + + if(cecreg != 0) + { + /* Flag in CEC ESR Register */ + CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); + + /* Get the CEC ESR register address */ + cecbase += 0xC; + } + else + { + /* Get the CEC CSR register address */ + cecbase += 0x10; + } + + if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) + { + /* CEC_FLAG is set */ + bitstatus = SET; + } + else + { + /* CEC_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the CEC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's pending flags. + * @param CEC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg CEC_FLAG_TERR: Tx Error + * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished + * @arg CEC_FLAG_RSOM: Rx Start Of Message + * @arg CEC_FLAG_REOM: Rx End Of Message + * @arg CEC_FLAG_RERR: Rx Error + * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished + * @retval None + */ +void CEC_ClearFlag(uint32_t CEC_FLAG) +{ + uint32_t tmp = 0x0; + + /* Check the parameters */ + assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); + + tmp = CEC->CSR & 0x2; + + /* Clear the selected CEC flags */ + CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); +} + +/** + * @brief Checks whether the specified CEC interrupt has occurred or not. + * @param CEC_IT: specifies the CEC interrupt source to check. + * This parameter can be one of the following values: + * @arg CEC_IT_TERR: Tx Error + * @arg CEC_IT_TBTF: Tx Block Transfer Finished + * @arg CEC_IT_RERR: Rx Error + * @arg CEC_IT_RBTF: Rx Block Transfer Finished + * @retval The new state of CEC_IT (SET or RESET). + */ +ITStatus CEC_GetITStatus(uint8_t CEC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + /* Get the CEC IT enable bit status */ + enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; + + /* Check the status of the specified CEC interrupt */ + if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) + { + /* CEC_IT is set */ + bitstatus = SET; + } + else + { + /* CEC_IT is reset */ + bitstatus = RESET; + } + /* Return the CEC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the CEC's interrupt pending bits. + * @param CEC_IT: specifies the CEC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg CEC_IT_TERR: Tx Error + * @arg CEC_IT_TBTF: Tx Block Transfer Finished + * @arg CEC_IT_RERR: Rx Error + * @arg CEC_IT_RBTF: Rx Block Transfer Finished + * @retval None + */ +void CEC_ClearITPendingBit(uint16_t CEC_IT) +{ + uint32_t tmp = 0x0; + + /* Check the parameters */ + assert_param(IS_CEC_GET_IT(CEC_IT)); + + tmp = CEC->CSR & 0x2; + + /* Clear the selected CEC interrupt pending bits */ + CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_crc.c b/example/libs_stm/src/stm32f10x/stm32f10x_crc.c new file mode 100644 index 000000000..c9291f4c4 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_crc.c @@ -0,0 +1,163 @@ +/** + ****************************************************************************** + * @file stm32f10x_crc.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the CRC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_crc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup CRC + * @brief CRC driver modules + * @{ + */ + +/** @defgroup CRC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Defines + * @{ + */ + +/* CR register bit mask */ + +#define CR_RESET_Set ((uint32_t)0x00000001) + +/** + * @} + */ + +/** @defgroup CRC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup CRC_Private_Functions + * @{ + */ + +/** + * @brief Resets the CRC Data register (DR). + * @param None + * @retval None + */ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR = CR_RESET_Set; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param Data: data word(32-bit) to compute its CRC + * @retval 32-bit CRC + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DR = Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer: pointer to the buffer containing the data to be computed + * @param BufferLength: length of the buffer to be computed + * @retval 32-bit CRC + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + return (CRC->DR); +} + +/** + * @brief Returns the current CRC value. + * @param None + * @retval 32-bit CRC + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/** + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param IDValue: 8-bit value to be stored in the ID register + * @retval None + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDR = IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @param None + * @retval 8-bit value of the ID register + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDR); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_dac.c b/example/libs_stm/src/stm32f10x/stm32f10x_dac.c new file mode 100644 index 000000000..e20b4a933 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_dac.c @@ -0,0 +1,579 @@ +/** + ****************************************************************************** + * @file stm32f10x_dac.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the DAC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dac.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DAC + * @brief DAC driver modules + * @{ + */ + +/** @defgroup DAC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Defines + * @{ + */ + +/* DAC EN mask */ +#define CR_EN_Set ((uint32_t)0x00000001) + +/* DAC DMAEN mask */ +#define CR_DMAEN_Set ((uint32_t)0x00001000) + +/* CR register Mask */ +#define CR_CLEAR_Mask ((uint32_t)0x00000FFE) + +/* DAC SWTRIG mask */ +#define SWTRIGR_SWTRIG_Set ((uint32_t)0x00000001) + +/* DAC Dual Channels SWTRIG masks */ +#define DUAL_SWTRIG_Set ((uint32_t)0x00000003) +#define DUAL_SWTRIG_Reset ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_Offset ((uint32_t)0x00000008) +#define DHR12R2_Offset ((uint32_t)0x00000014) +#define DHR12RD_Offset ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_Offset ((uint32_t)0x0000002C) +/** + * @} + */ + +/** @defgroup DAC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DAC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void DAC_DeInit(void) +{ + /* Enable DAC reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + /* Release DAC from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/** + * @brief Initializes the DAC peripheral according to the specified + * parameters in the DAC_InitStruct. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that + * contains the configuration information for the specified DAC channel. + * @retval None + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + /* Check the DAC parameters */ + assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); + assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); + assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); +/*---------------------------- DAC CR Configuration --------------------------*/ + /* Get the DAC CR value */ + tmpreg1 = DAC->CR; + /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ + tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel); + /* Configure for the selected DAC channel: buffer output, trigger, wave genration, + mask/amplitude for wave genration */ + /* Set TSELx and TENx bits according to DAC_Trigger value */ + /* Set WAVEx bits according to DAC_WaveGeneration value */ + /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ + /* Set BOFFx bit according to DAC_OutputBuffer value */ + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); + /* Calculate CR register value depending on DAC_Channel */ + tmpreg1 |= tmpreg2 << DAC_Channel; + /* Write to DAC CR */ + DAC->CR = tmpreg1; +} + +/** + * @brief Fills each DAC_InitStruct member with its default value. + * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) +{ +/*--------------- Reset DAC init structure parameters values -----------------*/ + /* Initialize the DAC_Trigger member */ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + /* Initialize the DAC_WaveGeneration member */ + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + /* Initialize the DAC_OutputBuffer member */ + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/** + * @brief Enables or disables the specified DAC channel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the DAC channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel */ + DAC->CR |= CR_EN_Set << DAC_Channel; + } + else + { + /* Disable the selected DAC channel */ + DAC->CR &= ~(CR_EN_Set << DAC_Channel); + } +} +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/** + * @brief Enables or disables the specified DAC interrupts. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @param NewState: new state of the specified DAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_DAC_IT(DAC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected DAC interrupts */ + DAC->CR |= (DAC_IT << DAC_Channel); + } + else + { + /* Disable the selected DAC interrupts */ + DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); + } +} +#endif + +/** + * @brief Enables or disables the specified DAC channel DMA request. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DAC channel DMA request */ + DAC->CR |= CR_DMAEN_Set << DAC_Channel; + } + else + { + /* Disable the selected DAC channel DMA request */ + DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel); + } +} + +/** + * @brief Enables or disables the selected DAC channel software trigger. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param NewState: new state of the selected DAC channel software trigger. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for the selected DAC channel */ + DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4); + } + else + { + /* Disable software trigger for the selected DAC channel */ + DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4)); + } +} + +/** + * @brief Enables or disables simultaneously the two DAC channels software + * triggers. + * @param NewState: new state of the DAC channels software triggers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable software trigger for both DAC channels */ + DAC->SWTRIGR |= DUAL_SWTRIG_Set ; + } + else + { + /* Disable software trigger for both DAC channels */ + DAC->SWTRIGR &= DUAL_SWTRIG_Reset; + } +} + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_Wave: Specifies the wave type to enable or disable. + * This parameter can be one of the following values: + * @arg DAC_Wave_Noise: noise wave generation + * @arg DAC_Wave_Triangle: triangle wave generation + * @param NewState: new state of the selected DAC channel wave generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_WAVE(DAC_Wave)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected wave generation for the selected DAC channel */ + DAC->CR |= DAC_Wave << DAC_Channel; + } + else + { + /* Disable the selected wave generation for the selected DAC channel */ + DAC->CR &= ~(DAC_Wave << DAC_Channel); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel1. + * @param DAC_Align: Specifies the data alignement for DAC channel1. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignement selected + * @arg DAC_Align_12b_L: 12bit left data alignement selected + * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @param Data : Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_Offset + DAC_Align; + + /* Set the DAC channel1 selected data holding register */ + *(__IO uint32_t *) tmp = Data; +} + +/** + * @brief Set the specified data holding register value for DAC channel2. + * @param DAC_Align: Specifies the data alignement for DAC channel2. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignement selected + * @arg DAC_Align_12b_L: 12bit left data alignement selected + * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @param Data : Data to be loaded in the selected data holding register. + * @retval None + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_Offset + DAC_Align; + + /* Set the DAC channel2 selected data holding register */ + *(__IO uint32_t *)tmp = Data; +} + +/** + * @brief Set the specified data holding register value for dual channel + * DAC. + * @param DAC_Align: Specifies the data alignement for dual channel DAC. + * This parameter can be one of the following values: + * @arg DAC_Align_8b_R: 8bit right data alignement selected + * @arg DAC_Align_12b_L: 12bit left data alignement selected + * @arg DAC_Align_12b_R: 12bit right data alignement selected + * @param Data2: Data for DAC Channel2 to be loaded in the selected data + * holding register. + * @param Data1: Data for DAC Channel1 to be loaded in the selected data + * holding register. + * @retval None + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(DAC_Align)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_Offset + DAC_Align; + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; +} + +/** + * @brief Returns the last data output value of the selected DAC cahnnel. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + + tmp = (uint32_t) DAC_BASE ; + tmp += DOR_Offset + ((uint32_t)DAC_Channel >> 2); + + /* Returns the DAC channel data output register value */ + return (uint16_t) (*(__IO uint32_t*) tmp); +} + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) +/** + * @brief Checks whether the specified DAC flag is set or not. + * @param DAC_Channel: thee selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to check. + * This parameter can be only of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval The new state of DAC_FLAG (SET or RESET). + */ +FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Check the status of the specified DAC flag */ + if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) + { + /* DAC_FLAG is set */ + bitstatus = SET; + } + else + { + /* DAC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DAC_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channelx's pending flags. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_FLAG: specifies the flag to clear. + * This parameter can be of the following value: + * @arg DAC_FLAG_DMAUDR: DMA underrun flag + * @retval None + */ +void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_FLAG(DAC_FLAG)); + + /* Clear the selected DAC flags */ + DAC->SR = (DAC_FLAG << DAC_Channel); +} + +/** + * @brief Checks whether the specified DAC interrupt has occurred or not. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt source to check. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval The new state of DAC_IT (SET or RESET). + */ +ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Get the DAC_IT enable bit status */ + enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; + + /* Check the status of the specified DAC interrupt */ + if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) + { + /* DAC_IT is set */ + bitstatus = SET; + } + else + { + /* DAC_IT is reset */ + bitstatus = RESET; + } + /* Return the DAC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DAC channelxs interrupt pending bits. + * @param DAC_Channel: the selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_Channel_1: DAC Channel1 selected + * @arg DAC_Channel_2: DAC Channel2 selected + * @param DAC_IT: specifies the DAC interrupt pending bit to clear. + * This parameter can be the following values: + * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask + * @retval None + */ +void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(DAC_Channel)); + assert_param(IS_DAC_IT(DAC_IT)); + + /* Clear the selected DAC interrupt pending bits */ + DAC->SR = (DAC_IT << DAC_Channel); +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_dbgmcu.c b/example/libs_stm/src/stm32f10x/stm32f10x_dbgmcu.c new file mode 100644 index 000000000..6cfceba07 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_dbgmcu.c @@ -0,0 +1,161 @@ +/** + ****************************************************************************** + * @file stm32f10x_dbgmcu.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the DBGMCU firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dbgmcu.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DBGMCU + * @brief DBGMCU driver modules + * @{ + */ + +/** @defgroup DBGMCU_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Defines + * @{ + */ + +#define IDCODE_DEVID_Mask ((uint32_t)0x00000FFF) +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DBGMCU_Private_Functions + * @{ + */ + +/** + * @brief Returns the device revision identifier. + * @param None + * @retval Device revision identifier + */ +uint32_t DBGMCU_GetREVID(void) +{ + return(DBGMCU->IDCODE >> 16); +} + +/** + * @brief Returns the device identifier. + * @param None + * @retval Device identifier + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return(DBGMCU->IDCODE & IDCODE_DEVID_Mask); +} + +/** + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * @param DBGMCU_Periph: specifies the peripheral and low power mode. + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted + * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted + * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted + * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted + * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted + * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted + * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted + * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted + * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted + * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted + * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted + * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted + * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted + * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted + * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted + * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted + * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted + * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted + * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted + * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted + * @param NewState: new state of the specified peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->CR |= DBGMCU_Periph; + } + else + { + DBGMCU->CR &= ~DBGMCU_Periph; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_dma.c b/example/libs_stm/src/stm32f10x/stm32f10x_dma.c new file mode 100644 index 000000000..aa890c6a6 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_dma.c @@ -0,0 +1,693 @@ +/** + ****************************************************************************** + * @file stm32f10x_dma.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the DMA firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_dma.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup DMA + * @brief DMA driver modules + * @{ + */ + +/** @defgroup DMA_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup DMA_Private_Defines + * @{ + */ + +/* DMA ENABLE mask */ +#define CCR_ENABLE_Set ((uint32_t)0x00000001) +#define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE) + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F) +#define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0) +#define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00) +#define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000) +#define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000) +#define DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000) +#define DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((uint32_t)0x0000000F) +#define DMA2_Channel2_IT_Mask ((uint32_t)0x000000F0) +#define DMA2_Channel3_IT_Mask ((uint32_t)0x00000F00) +#define DMA2_Channel4_IT_Mask ((uint32_t)0x0000F000) +#define DMA2_Channel5_IT_Mask ((uint32_t)0x000F0000) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/** + * @} + */ + +/** @defgroup DMA_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the DMAy Channelx registers to their default reset + * values. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval None + */ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= CCR_ENABLE_Reset; + /* Reset DMAy Channelx control register */ + DMAy_Channelx->CCR = 0; + + /* Reset DMAy Channelx remaining bytes register */ + DMAy_Channelx->CNDTR = 0; + + /* Reset DMAy Channelx peripheral address register */ + DMAy_Channelx->CPAR = 0; + + /* Reset DMAy Channelx memory address register */ + DMAy_Channelx->CMAR = 0; + + if (DMAy_Channelx == DMA1_Channel1) + { + /* Reset interrupt pending bits for DMA1 Channel1 */ + DMA1->IFCR |= DMA1_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel2) + { + /* Reset interrupt pending bits for DMA1 Channel2 */ + DMA1->IFCR |= DMA1_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel3) + { + /* Reset interrupt pending bits for DMA1 Channel3 */ + DMA1->IFCR |= DMA1_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel4) + { + /* Reset interrupt pending bits for DMA1 Channel4 */ + DMA1->IFCR |= DMA1_Channel4_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel5) + { + /* Reset interrupt pending bits for DMA1 Channel5 */ + DMA1->IFCR |= DMA1_Channel5_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel6) + { + /* Reset interrupt pending bits for DMA1 Channel6 */ + DMA1->IFCR |= DMA1_Channel6_IT_Mask; + } + else if (DMAy_Channelx == DMA1_Channel7) + { + /* Reset interrupt pending bits for DMA1 Channel7 */ + DMA1->IFCR |= DMA1_Channel7_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel1) + { + /* Reset interrupt pending bits for DMA2 Channel1 */ + DMA2->IFCR |= DMA2_Channel1_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel2) + { + /* Reset interrupt pending bits for DMA2 Channel2 */ + DMA2->IFCR |= DMA2_Channel2_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel3) + { + /* Reset interrupt pending bits for DMA2 Channel3 */ + DMA2->IFCR |= DMA2_Channel3_IT_Mask; + } + else if (DMAy_Channelx == DMA2_Channel4) + { + /* Reset interrupt pending bits for DMA2 Channel4 */ + DMA2->IFCR |= DMA2_Channel4_IT_Mask; + } + else + { + if (DMAy_Channelx == DMA2_Channel5) + { + /* Reset interrupt pending bits for DMA2 Channel5 */ + DMA2->IFCR |= DMA2_Channel5_IT_Mask; + } + } +} + +/** + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that + * contains the configuration information for the specified DMA Channel. + * @retval None + */ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); + assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); + assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); + assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); + assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); + +/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ + /* Get the DMAy_Channelx CCR value */ + tmpreg = DMAy_Channelx->CCR; + /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ + tmpreg &= CCR_CLEAR_Mask; + /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ + /* Set DIR bit according to DMA_DIR value */ + /* Set CIRC bit according to DMA_Mode value */ + /* Set PINC bit according to DMA_PeripheralInc value */ + /* Set MINC bit according to DMA_MemoryInc value */ + /* Set PSIZE bits according to DMA_PeripheralDataSize value */ + /* Set MSIZE bits according to DMA_MemoryDataSize value */ + /* Set PL bits according to DMA_Priority value */ + /* Set the MEM2MEM bit according to DMA_M2M value */ + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + /* Write to DMAy Channelx CCR */ + DMAy_Channelx->CCR = tmpreg; + +/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ + /* Write to DMAy Channelx CNDTR */ + DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; + +/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ + /* Write to DMAy Channelx CPAR */ + DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; + +/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ + /* Write to DMAy Channelx CMAR */ + DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/** + * @brief Fills each DMA_InitStruct member with its default value. + * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ +/*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA_PeripheralBaseAddr member */ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + /* Initialize the DMA_MemoryBaseAddr member */ + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + /* Initialize the DMA_DIR member */ + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + /* Initialize the DMA_BufferSize member */ + DMA_InitStruct->DMA_BufferSize = 0; + /* Initialize the DMA_PeripheralInc member */ + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + /* Initialize the DMA_MemoryInc member */ + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + /* Initialize the DMA_PeripheralDataSize member */ + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + /* Initialize the DMA_MemoryDataSize member */ + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + /* Initialize the DMA_Mode member */ + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + /* Initialize the DMA_Priority member */ + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + /* Initialize the DMA_M2M member */ + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param NewState: new state of the DMAy Channelx. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMAy Channelx */ + DMAy_Channelx->CCR |= CCR_ENABLE_Set; + } + else + { + /* Disable the selected DMAy Channelx */ + DMAy_Channelx->CCR &= CCR_ENABLE_Reset; + } +} + +/** + * @brief Enables or disables the specified DMAy Channelx interrupts. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @param DMA_IT: specifies the DMA interrupts sources to be enabled + * or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask + * @arg DMA_IT_HT: Half transfer interrupt mask + * @arg DMA_IT_TE: Transfer error interrupt mask + * @param NewState: new state of the specified DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + assert_param(IS_DMA_CONFIG_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected DMA interrupts */ + DMAy_Channelx->CCR |= DMA_IT; + } + else + { + /* Disable the selected DMA interrupts */ + DMAy_Channelx->CCR &= ~DMA_IT; + } +} + +/** + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and + * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * @retval The number of remaining data units in the current DMAy Channelx + * transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)(DMAy_Channelx->CNDTR)); +} + +/** + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * @param DMA_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval The new state of DMA_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); + + /* Calculate the used DMA */ + if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR ; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + } + + /* Check the status of the specified DMA flag */ + if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) + { + /* DMA_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the DMA_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelx's pending flags. + * @param DMA_FLAG: specifies the flag to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. + * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. + * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. + * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. + * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. + * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. + * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. + * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. + * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. + * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. + * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. + * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. + * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. + * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. + * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. + * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. + * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. + * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. + * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. + * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. + * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. + * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. + * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. + * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. + * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. + * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. + * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. + * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. + * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. + * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. + * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. + * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. + * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. + * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. + * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. + * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. + * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. + * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. + * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. + * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. + * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. + * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. + * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. + * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. + * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. + * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. + * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. + * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. + * @retval None + */ +void DMA_ClearFlag(uint32_t DMA_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); + /* Calculate the used DMA */ + + if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMA flags */ + DMA2->IFCR = DMA_FLAG; + } + else + { + /* Clear the selected DMA flags */ + DMA1->IFCR = DMA_FLAG; + } +} + +/** + * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. + * @param DMA_IT: specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval The new state of DMA_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMA_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_DMA_GET_IT(DMA_IT)); + + /* Calculate the used DMA */ + if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Get DMA2 ISR register value */ + tmpreg = DMA2->ISR ; + } + else + { + /* Get DMA1 ISR register value */ + tmpreg = DMA1->ISR ; + } + + /* Check the status of the specified DMA interrupt */ + if ((tmpreg & DMA_IT) != (uint32_t)RESET) + { + /* DMA_IT is set */ + bitstatus = SET; + } + else + { + /* DMA_IT is reset */ + bitstatus = RESET; + } + /* Return the DMA_IT status */ + return bitstatus; +} + +/** + * @brief Clears the DMAy Channelxs interrupt pending bits. + * @param DMA_IT: specifies the DMA interrupt pending bit to clear. + * This parameter can be any combination (for the same DMA) of the following values: + * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. + * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. + * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. + * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. + * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. + * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. + * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. + * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. + * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. + * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. + * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. + * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. + * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. + * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. + * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. + * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. + * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. + * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. + * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. + * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. + * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. + * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. + * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. + * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. + * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. + * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. + * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. + * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. + * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. + * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. + * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. + * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. + * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. + * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. + * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. + * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. + * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. + * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. + * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. + * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. + * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. + * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. + * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. + * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. + * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. + * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. + * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. + * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. + * @retval None + */ +void DMA_ClearITPendingBit(uint32_t DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_CLEAR_IT(DMA_IT)); + + /* Calculate the used DMA */ + if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET) + { + /* Clear the selected DMA interrupt pending bits */ + DMA2->IFCR = DMA_IT; + } + else + { + /* Clear the selected DMA interrupt pending bits */ + DMA1->IFCR = DMA_IT; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_exti.c b/example/libs_stm/src/stm32f10x/stm32f10x_exti.c new file mode 100644 index 000000000..eae3253ea --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_exti.c @@ -0,0 +1,268 @@ +/** + ****************************************************************************** + * @file stm32f10x_exti.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the EXTI firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_exti.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/** @defgroup EXTI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Defines + * @{ + */ + +#define EXTI_LineNone ((uint32_t)0x00000) /* No interrupt selected */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup EXTI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x00000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->PR = 0x000FFFFF; +} + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure + * that contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected external interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LineNone; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** + * @brief Generates a Software interrupt. + * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line: specifies the EXTI line flag to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..19) + * @retval The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTIs line pending flags. + * @param EXTI_Line: specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line: specifies the EXTI line to check. + * This parameter can be: + * @arg EXTI_Linex: External interrupt line x where x(0..19) + * @retval The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + enablestatus = EXTI->IMR & EXTI_Line; + if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the EXTIs line pending bits. + * @param EXTI_Line: specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..19). + * @retval None + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_flash.c b/example/libs_stm/src/stm32f10x/stm32f10x_flash.c new file mode 100644 index 000000000..3475e6a37 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_flash.c @@ -0,0 +1,1735 @@ +/** + ****************************************************************************** + * @file stm32f10x_flash.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the FLASH firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_flash.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup FLASH + * @brief FLASH driver modules + * @{ + */ + +/** @defgroup FLASH_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Defines + * @{ + */ + +/* Flash Access Control Register bits */ +#define ACR_LATENCY_Mask ((uint32_t)0x00000038) +#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) +#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) + +/* Flash Access Control Register bits */ +#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0x00001FFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0x00001FFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0x00001FFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0x00001FEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0x00001FDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x000B0000) +#define ProgramTimeout ((uint32_t)0x00002000) +/** + * @} + */ + +/** @defgroup FLASH_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup FLASH_Private_Functions + * @{ + */ + +/** +@code + + This driver provides functions to configure and program the Flash memory of all STM32F10x devices, + including the latest STM32F10x_XL density devices. + + STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability: + - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each) + - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each) + While other STM32F10x devices features only one bank with memory up to 512 Kbytes. + + In version V3.3.0, some functions were updated and new ones were added to support + STM32F10x_XL devices. Thus some functions manages all devices, while other are + dedicated for XL devices only. + + The table below presents the list of available functions depending on the used STM32F10x devices. + + *************************************************** + * Legacy functions used for all STM32F10x devices * + *************************************************** + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_SetLatency | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_HalfCycleAccessCmd | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_PrefetchBufferCmd | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. | + | | | | - For other devices: unlock Bank1 and it is equivalent | + | | | | to FLASH_UnlockBank1 function. | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. | + | | | | - For other devices: lock Bank1 and it is equivalent | + | | | | to FLASH_LockBank1 function. | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 | + | | | | - For other devices: erase a page in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 | + | | | | - For other devices: erase all pages in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EraseOptionBytes | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ProgramOptionByteData | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_EnableWriteProtection | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ReadOutProtection | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_UserOptionByteConfig | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetUserOptionByte | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts| + | | | | - For other devices: enable Bank1's interrupts | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status| + | | | | - For other devices: return Bank1's flag status | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag | + | | | | - For other devices: clear Bank1's flag | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) | + | | | | equivalent to FLASH_GetBank1Status function | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) | + | | | | equivalent to: FLASH_WaitForLastBank1Operation function | + +----------------------------------------------------------------------------------------------------------------------------------+ + + ************************************************************************************************************************ + * New functions used for all STM32F10x devices to manage Bank1: * + * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 * + * - For other devices, these functions are optional (covered by functions listed above) * + ************************************************************************************************************************ + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation | + +----------------------------------------------------------------------------------------------------------------------------------+ + + ***************************************************************************** + * New Functions used only with STM32F10x_XL density devices to manage Bank2 * + ***************************************************************************** + +----------------------------------------------------------------------------------------------------------------------------------+ + | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | + | | devices | devices | | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + |FLASH_LockBank2 | Yes | No | - Lock Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation | + |----------------------------------------------------------------------------------------------------------------------------------| + | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 | + +----------------------------------------------------------------------------------------------------------------------------------+ +@endcode +*/ + + +/** + * @brief Sets the code latency value. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_Latency: specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_Latency_0: FLASH Zero Latency cycle + * @arg FLASH_Latency_1: FLASH One Latency cycle + * @arg FLASH_Latency_2: FLASH Two Latency cycles + * @retval None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the ACR register */ + tmpreg = FLASH->ACR; + + /* Sets the Latency value */ + tmpreg &= ACR_LATENCY_Mask; + tmpreg |= FLASH_Latency; + + /* Write the ACR register */ + FLASH->ACR = tmpreg; +} + +/** + * @brief Enables or disables the Half cycle flash access. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. + * This parameter can be one of the following values: + * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable + * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable + * @retval None + */ +void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) +{ + /* Check the parameters */ + assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); + + /* Enable or disable the Half cycle access */ + FLASH->ACR &= ACR_HLFCYA_Mask; + FLASH->ACR |= FLASH_HalfCycleAccess; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @note This function can be used for all STM32F10x devices. + * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status. + * This parameter can be one of the following values: + * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable + * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable + * @retval None + */ +void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) +{ + /* Check the parameters */ + assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); + + /* Enable or disable the Prefetch Buffer */ + FLASH->ACR &= ACR_PRFTBE_Mask; + FLASH->ACR |= FLASH_PrefetchBuffer; +} + +/** + * @brief Unlocks the FLASH Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2. + * - For all other devices it unlocks Bank1 and it is equivalent + * to FLASH_UnlockBank1 function.. + * @param None + * @retval None + */ +void FLASH_Unlock(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + +#ifdef STM32F10X_XL + /* Authorize the FPEC of Bank2 Access */ + FLASH->KEYR2 = FLASH_KEY1; + FLASH->KEYR2 = FLASH_KEY2; +#endif /* STM32F10X_XL */ +} +/** + * @brief Unlocks the FLASH Bank1 Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function unlocks Bank1. + * - For all other devices it unlocks Bank1 and it is + * equivalent to FLASH_Unlock function. + * @param None + * @retval None + */ +void FLASH_UnlockBank1(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +#ifdef STM32F10X_XL +/** + * @brief Unlocks the FLASH Bank2 Program Erase Controller. + * @note This function can be used only for STM32F10X_XL density devices. + * @param None + * @retval None + */ +void FLASH_UnlockBank2(void) +{ + /* Authorize the FPEC of Bank2 Access */ + FLASH->KEYR2 = FLASH_KEY1; + FLASH->KEYR2 = FLASH_KEY2; + +} +#endif /* STM32F10X_XL */ + +/** + * @brief Locks the FLASH Program Erase Controller. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function Locks Bank1 and Bank2. + * - For all other devices it Locks Bank1 and it is equivalent + * to FLASH_LockBank1 function. + * @param None + * @retval None + */ +void FLASH_Lock(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ + FLASH->CR |= CR_LOCK_Set; + +#ifdef STM32F10X_XL + /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ + FLASH->CR2 |= CR_LOCK_Set; +#endif /* STM32F10X_XL */ +} + +/** + * @brief Locks the FLASH Bank1 Program Erase Controller. + * @note this function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function Locks Bank1. + * - For all other devices it Locks Bank1 and it is equivalent + * to FLASH_Lock function. + * @param None + * @retval None + */ +void FLASH_LockBank1(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ + FLASH->CR |= CR_LOCK_Set; +} + +#ifdef STM32F10X_XL +/** + * @brief Locks the FLASH Bank2 Program Erase Controller. + * @note This function can be used only for STM32F10X_XL density devices. + * @param None + * @retval None + */ +void FLASH_LockBank2(void) +{ + /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ + FLASH->CR2 |= CR_LOCK_Set; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Erases a specified FLASH page. + * @note This function can be used for all STM32F10x devices. + * @param Page_Address: The page address to be erased. + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Page_Address)); + +#ifdef STM32F10X_XL + if(Page_Address < FLASH_BANK1_END_ADDRESS) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR|= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } + } + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR2|= CR_PER_Set; + FLASH->AR2 = Page_Address; + FLASH->CR2|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the PER Bit */ + FLASH->CR2 &= CR_PER_Reset; + } + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CR|= CR_PER_Set; + FLASH->AR = Page_Address; + FLASH->CR|= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the PER Bit */ + FLASH->CR &= CR_PER_Reset; + } + } +#endif /* STM32F10X_XL */ + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all FLASH pages. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + +#ifdef STM32F10X_XL + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + } + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR2 |= CR_MER_Set; + FLASH->CR2 |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR2 &= CR_MER_Reset; + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + } +#endif /* STM32F10X_XL */ + + /* Return the Erase Status */ + return status; +} + +/** + * @brief Erases all Bank1 FLASH pages. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices this function erases all Bank1 pages. + * - For all other devices it erases all Bank1 pages and it is equivalent + * to FLASH_EraseAllPages function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank1Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR |= CR_MER_Set; + FLASH->CR |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= CR_MER_Reset; + } + } + /* Return the Erase Status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Erases all Bank2 FLASH pages. + * @note This function can be used only for STM32F10x_XL density devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank2Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CR2 |= CR_MER_Set; + FLASH->CR2 |= CR_STRT_Set; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(EraseTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR2 &= CR_MER_Reset; + } + } + /* Return the Erase Status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Erases the FLASH option bytes. + * @note This functions erases all option bytes except the Read protection (RDP). + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + uint16_t rdptmp = RDP_Key; + + FLASH_Status status = FLASH_COMPLETE; + + /* Get the actual read protection Option Byte value */ + if(FLASH_GetReadOutProtectionStatus() != RESET) + { + rdptmp = 0x00; + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + /* Restore the last read protection Option Byte value */ + OB->RDP = (uint16_t)rdptmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + } + /* Return the erase status */ + return status; +} + +/** + * @brief Programs a word at a specified address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + +#ifdef STM32F10X_XL + if(Address < FLASH_BANK1_END_ADDRESS - 2) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + } + } + else if(Address == (FLASH_BANK1_END_ADDRESS - 1)) + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + FLASH->CR2 |= CR_PG_Set; + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + } + else + { + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR2 |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new first + half word */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = (uint16_t)Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new second + half word */ + tmp = Address + 2; + + *(__IO uint16_t*) tmp = Data >> 16; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + else + { + if (status != FLASH_TIMEOUT) + { + /* Disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + } +#endif /* STM32F10X_XL */ + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + +#ifdef STM32F10X_XL + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(Address < FLASH_BANK1_END_ADDRESS) + { + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank1Operation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } + } + else + { + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR2 |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastBank2Operation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR2 &= CR_PG_Reset; + } + } + } +#else + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* if the previous operation is completed, proceed to program the new data */ + FLASH->CR |= CR_PG_Set; + + *(__IO uint16_t*)Address = Data; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the PG Bit */ + FLASH->CR &= CR_PG_Reset; + } + } +#endif /* STM32F10X_XL */ + + /* Return the Program Status */ + return status; +} + +/** + * @brief Programs a half word at a specified Option Byte Data address. + * @note This function can be used for all STM32F10x devices. + * @param Address: specifies the address to be programmed. + * This parameter can be 0x1FFFF804 or 0x1FFFF806. + * @param Data: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_OB_DATA_ADDRESS(Address)); + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + /* Enables the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + *(__IO uint16_t*)Address = Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte Data Program Status */ + return status; +} + +/** + * @brief Write protects the desired pages + * @note This function can be used for all STM32F10x devices. + * @param FLASH_Pages: specifies the address of the pages to be write protected. + * This parameter can be: + * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 + * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3 + * and FLASH_WRProt_Pages124to127 + * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255 + * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 + * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and + * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511 + * @arg FLASH_WRProt_AllPages + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); + + FLASH_Pages = (uint32_t)(~FLASH_Pages); + WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); + WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); + WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTPG_Set; + if(WRP0_Data != 0xFF) + { + OB->WRP0 = WRP0_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) + { + OB->WRP1 = WRP1_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) + { + OB->WRP2 = WRP2_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF)) + { + OB->WRP3 = WRP3_Data; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + } + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the write protection operation Status */ + return status; +} + +/** + * @brief Enables or disables the read out protection. + * @note If the user has already programmed the other option bytes before calling + * this function, he must re-program them since this function erases all option bytes. + * @note This function can be used for all STM32F10x devices. + * @param Newstate: new state of the ReadOut Protection. + * This parameter can be: ENABLE or DISABLE. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* Authorizes the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + FLASH->CR |= CR_OPTER_Set; + FLASH->CR |= CR_STRT_Set; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + if(NewState != DISABLE) + { + OB->RDP = 0x00; + } + else + { + OB->RDP = RDP_Key; + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CR &= CR_OPTER_Reset; + } + } + } + /* Return the protection operation Status */ + return status; +} + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @note This function can be used for all STM32F10x devices. + * @param OB_IWDG: Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param OB_STOP: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NoRST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param OB_STDBY: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); + assert_param(IS_OB_STOP_SOURCE(OB_STOP)); + assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte program Status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Configures to boot from Bank1 or Bank2. + * @note This function can be used only for STM32F10x_XL density devices. + * @param FLASH_BOOT: select the FLASH Bank to boot from. + * This parameter can be one of the following values: + * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank1(Default). + * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash + * position and this parameter is selected the device will boot from Bank2 or Bank1, + * depending on the activation of the bank. The active banks are checked in + * the following order: Bank2, followed by Bank1. + * The active bank is recognized by the value programmed at the base address + * of the respective bank (corresponding to the initial stack pointer value + * in the interrupt vector table). + * For more information, please refer to AN2606 from www.st.com. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT) +{ + FLASH_Status status = FLASH_COMPLETE; + assert_param(IS_FLASH_BOOT(FLASH_BOOT)); + /* Authorize the small information block programming */ + FLASH->OPTKEYR = FLASH_KEY1; + FLASH->OPTKEYR = FLASH_KEY2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CR |= CR_OPTPG_Set; + + if(FLASH_BOOT == FLASH_BOOT_Bank1) + { + OB->USER |= OB_USER_BFB2; + } + else + { + OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2)); + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CR &= CR_OPTPG_Reset; + } + } + /* Return the Option Byte program Status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @brief Returns the FLASH User Option Bytes values. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + /* Return the User Option Byte */ + return (uint32_t)(FLASH->OBR >> 2); +} + +/** + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval The FLASH Write Protection Option Bytes Register value + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + /* Return the Falsh write protection Register value */ + return (uint32_t)(FLASH->WRPR); +} + +/** + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/** + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * @note This function can be used for all STM32F10x devices. + * @param None + * @retval FLASH Prefetch Buffer Status (SET or RESET). + */ +FlagStatus FLASH_GetPrefetchBufferStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts + for Bank1 and Bank2. + * - For other devices it enables or disables the specified FLASH interrupts for Bank1. + * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_ERROR: FLASH Error Interrupt + * @arg FLASH_IT_EOP: FLASH end of operation Interrupt + * @param NewState: new state of the specified Flash interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if((FLASH_IT & 0x80000000) != 0x0) + { + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF); + } + else + { + /* Disable the interrupt sources */ + FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF); + } + } + else + { + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } + } +#else + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if(NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->CR |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->CR &= ~(uint32_t)FLASH_IT; + } +#endif /* STM32F10X_XL */ +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, this function checks whether the specified + * Bank1 or Bank2 flag is set or not. + * - For other devices, it checks whether the specified Bank1 flag is + * set or not. + * @param FLASH_FLAG: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BSY: FLASH Busy flag + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH_FLAG & 0x80000000) != 0x0) + { + if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + } +#else + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } +#endif /* STM32F10X_XL */ + + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + +/** + * @brief Clears the FLASHs pending flags. + * @note This function can be used for all STM32F10x devices. + * - For STM32F10X_XL devices, this function clears Bank1 or Bank2s pending flags + * - For other devices, it clears Bank1s pending flags. + * @param FLASH_FLAG: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_PGERR: FLASH Program error flag + * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @retval None + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ +#ifdef STM32F10X_XL + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + if((FLASH_FLAG & 0x80000000) != 0x0) + { + /* Clear the flags */ + FLASH->SR2 = FLASH_FLAG; + } + else + { + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; + } + +#else + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; + + /* Clear the flags */ + FLASH->SR = FLASH_FLAG; +#endif /* STM32F10X_XL */ +} + +/** + * @brief Returns the FLASH Status. + * @note This function can be used for all STM32F10x devices, it is equivalent + * to FLASH_GetBank1Status function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +/** + * @brief Returns the FLASH Bank1 Status. + * @note This function can be used for all STM32F10x devices, it is equivalent + * to FLASH_GetStatus function. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} + +#ifdef STM32F10X_XL +/** + * @brief Returns the FLASH Bank2 Status. + * @note This function can be used for STM32F10x_XL density devices. + * @param None + * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE + */ +FLASH_Status FLASH_GetBank2Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0) + { + flashstatus = FLASH_ERROR_PG; + } + else + { + if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 ) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + } + /* Return the Flash Status */ + return flashstatus; +} +#endif /* STM32F10X_XL */ +/** + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * @note This function can be used for all STM32F10x devices, + * it is equivalent to FLASH_WaitForLastBank1Operation. + * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation + * to complete or a TIMEOUT to occur. + * - For all other devices it waits for a Flash operation to complete + * or a TIMEOUT to occur. + * @param Timeout: FLASH progamming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank1Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +/** + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * @note This function can be used for all STM32F10x devices, + * it is equivalent to FLASH_WaitForLastOperation. + * @param Timeout: FLASH progamming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank1Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +#ifdef STM32F10X_XL +/** + * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur. + * @note This function can be used only for STM32F10x_XL density devices. + * @param Timeout: FLASH progamming Timeout + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check for the Flash Status */ + status = FLASH_GetBank2Status(); + /* Wait for a Flash operation to complete or a TIMEOUT to occur */ + while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00)) + { + status = FLASH_GetBank2Status(); + Timeout--; + } + if(Timeout == 0x00 ) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} +#endif /* STM32F10X_XL */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_fsmc.c b/example/libs_stm/src/stm32f10x/stm32f10x_fsmc.c new file mode 100644 index 000000000..d04221942 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_fsmc.c @@ -0,0 +1,858 @@ +/** + ****************************************************************************** + * @file stm32f10x_fsmc.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the FSMC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_fsmc.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup FSMC + * @brief FSMC driver modules + * @{ + */ + +/** @defgroup FSMC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup FSMC_Private_Defines + * @{ + */ + +/* --------------------- FSMC registers bit mask ---------------------------- */ + +/* FSMC BCRx Mask */ +#define BCR_MBKEN_Set ((uint32_t)0x00000001) +#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_Set ((uint32_t)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_Set ((uint32_t)0x00000004) +#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_Set ((uint32_t)0x00000040) +#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) +#define PCR_MemoryType_NAND ((uint32_t)0x00000008) +/** + * @} + */ + +/** @defgroup FSMC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup FSMC_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default + * reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @retval None + */ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + + /* FSMC_Bank1_NORSRAM1 */ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/** + * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval None + */ +void FSMC_NANDDeInit(uint32_t FSMC_Bank) +{ + /* Check the parameter */ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Set the FSMC_Bank2 registers to their reset values */ + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } + /* FSMC_Bank3_NAND */ + else + { + /* Set the FSMC_Bank3 registers to their reset values */ + FSMC_Bank3->PCR3 = 0x00000018; + FSMC_Bank3->SR3 = 0x00000040; + FSMC_Bank3->PMEM3 = 0xFCFCFCFC; + FSMC_Bank3->PATT3 = 0xFCFCFCFC; + } +} + +/** + * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. + * @param None + * @retval None + */ +void FSMC_PCCARDDeInit(void) +{ + /* Set the FSMC_Bank4 registers to their reset values */ + FSMC_Bank4->PCR4 = 0x00000018; + FSMC_Bank4->SR4 = 0x00000000; + FSMC_Bank4->PMEM4 = 0xFCFCFCFC; + FSMC_Bank4->PATT4 = 0xFCFCFCFC; + FSMC_Bank4->PIO4 = 0xFCFCFCFC; +} + +/** + * @brief Initializes the FSMC NOR/SRAM Banks according to the specified + * parameters in the FSMC_NORSRAMInitStruct. + * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef + * structure that contains the configuration information for + * the FSMC NOR/SRAM specified Banks. + * @retval None + */ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); + assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); + assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); + assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); + assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); + assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); + assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); + assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); + assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); + assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); + assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); + assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); + + /* Bank1 NOR/SRAM control register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WrapMode | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; + } + /* Bank1 NOR/SRAM timing register configuration */ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + + /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); + assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); + assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); + assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); + assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); + assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/** + * @brief Initializes the FSMC NAND Banks according to the specified + * parameters in the FSMC_NANDInitStruct. + * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef + * structure that contains the configuration information for the FSMC NAND specified Banks. + * @retval None + */ +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + /* Check the parameters */ + assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); + assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); + assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); + assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); + assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); + assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); + assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ + tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MemoryType_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ + tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ + tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + /* FSMC_Bank2_NAND registers configuration */ + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } + else + { + /* FSMC_Bank3_NAND registers configuration */ + FSMC_Bank3->PCR3 = tmppcr; + FSMC_Bank3->PMEM3 = tmppmem; + FSMC_Bank3->PATT3 = tmppatt; + } +} + +/** + * @brief Initializes the FSMC PCCARD Bank according to the specified + * parameters in the FSMC_PCCARDInitStruct. + * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef + * structure that contains the configuration information for the FSMC PCCARD Bank. + * @retval None + */ +void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Check the parameters */ + assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); + assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); + assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); + + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); + assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); + assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); + assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); + assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); + + /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ + FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | + FSMC_MemoryDataWidth_16b | + (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); + + /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ + FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ + FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ + FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| + (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); +} + +/** + * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. + * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) +{ + /* Reset NOR/SRAM Init structure parameters values */ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; +} + +/** + * @brief Fills each FSMC_NANDInitStruct member with its default value. + * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) +{ + /* Reset NAND Init structure parameters values */ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Fills each FSMC_PCCARDInitStruct member with its default value. + * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef + * structure which will be initialized. + * @retval None + */ +void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) +{ + /* Reset PCCARD Init structure parameters values */ + FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/** + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 + * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 + * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 + * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; + } + else + { + /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; + } +} + +/** + * @brief Enables or disables the specified NAND Memory Bank. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; + } + } + else + { + /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; + } + } +} + +/** + * @brief Enables or disables the PCCARD Memory Bank. + * @param NewState: new state of the PCCARD Memory Bank. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_PCCARDCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; + } + else + { + /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ + FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; + } +} + +/** + * @brief Enables or disables the FSMC NAND ECC feature. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @param NewState: new state of the FSMC NAND ECC feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; + } + else + { + FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; + } + } + else + { + /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; + } + else + { + FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; + } + } +} + +/** + * @brief Returns the error correction code register value. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @retval The Error Correction Code (ECC) value. + */ +uint32_t FSMC_GetECC(uint32_t FSMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + /* Get the ECCR2 register value */ + eccval = FSMC_Bank2->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + eccval = FSMC_Bank3->ECCR3; + } + /* Return the error correction code value */ + return(eccval); +} + +/** + * @brief Enables or disables the specified FSMC interrupts. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @param NewState: new state of the specified FSMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) +{ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 |= FSMC_IT; + } + /* Enable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 |= FSMC_IT; + } + } + else + { + /* Disable the selected FSMC_Bank2 interrupts */ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + + FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank3 interrupts */ + else if (FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; + } + /* Disable the selected FSMC_Bank4 interrupts */ + else + { + FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; + } + } +} + +/** + * @brief Checks whether the specified FSMC flag is set or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. + * @retval The new state of FSMC_FLAG (SET or RESET). + */ +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + /* Get the flag status */ + if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the FSMCs pending flags. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. + * @arg FSMC_FLAG_Level: Level detection Flag. + * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. + * @retval None + */ +void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); + assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~FSMC_FLAG; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~FSMC_FLAG; + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~FSMC_FLAG; + } +} + +/** + * @brief Checks whether the specified FSMC interrupt has occurred or not. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the FSMC interrupt source to check. + * This parameter can be one of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval The new state of FSMC_IT (SET or RESET). + */ +ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_GET_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + tmpsr = FSMC_Bank3->SR3; + } + /* FSMC_Bank4_PCCARD*/ + else + { + tmpsr = FSMC_Bank4->SR4; + } + + itstatus = tmpsr & FSMC_IT; + + itenable = tmpsr & (FSMC_IT >> 3); + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the FSMCs interrupt pending bits. + * @param FSMC_Bank: specifies the FSMC Bank to be used + * This parameter can be one of the following values: + * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND + * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND + * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD + * @param FSMC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. + * @arg FSMC_IT_Level: Level edge detection interrupt. + * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. + * @retval None + */ +void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) +{ + /* Check the parameters */ + assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); + assert_param(IS_FSMC_IT(FSMC_IT)); + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); + } + else if(FSMC_Bank == FSMC_Bank3_NAND) + { + FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); + } + /* FSMC_Bank4_PCCARD*/ + else + { + FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_gpio.c b/example/libs_stm/src/stm32f10x/stm32f10x_gpio.c new file mode 100644 index 000000000..0978e986e --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_gpio.c @@ -0,0 +1,642 @@ +/** + ****************************************************************************** + * @file stm32f10x_gpio.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the GPIO firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_gpio.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup GPIO + * @brief GPIO driver modules + * @{ + */ + +/** @defgroup GPIO_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------------*/ +#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) + +/* --- EVENTCR Register -----*/ + +/* Alias word address of EVOE bit */ +#define EVCR_OFFSET (AFIO_OFFSET + 0x00) +#define EVOE_BitNumber ((uint8_t)0x07) +#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) + + +/* --- MAPR Register ---*/ +/* Alias word address of MII_RMII_SEL bit */ +#define MAPR_OFFSET (AFIO_OFFSET + 0x04) +#define MII_RMII_SEL_BitNumber ((u8)0x17) +#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) + + +#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) +/** + * @} + */ + +/** @defgroup GPIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup GPIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if (GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } + else if (GPIOx == GPIOE) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + } + else if (GPIOx == GPIOF) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); + } + else + { + if (GPIOx == GPIOG) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); + } + } +} + +/** + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * @param None + * @retval None + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified + * parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + +/*---------------------------- GPIO Mode Configuration -----------------------*/ + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + /* Check the parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + /* Output mode */ + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } +/*---------------------------- GPIO CRL Configuration ------------------------*/ + /* Configure the eight low port pins */ + if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CRL; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding low control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << pinpos); + } + else + { + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CRL = tmpreg; + } +/*---------------------------- GPIO CRH Configuration ------------------------*/ + /* Configure the eight high port pins */ + if (GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CRH; + for (pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + /* Get the port pins position */ + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + if (currentpin == pos) + { + pos = pinpos << 2; + /* Clear the corresponding high control register bits */ + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + /* Write the mode configuration in the corresponding bits */ + tmpreg |= (currentmode << pos); + /* Reset the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + /* Set the corresponding ODR bit */ + if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CRH = tmpreg; + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO input data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval GPIO input data port value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRR = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BRR = GPIO_Pin; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enum values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BRR = GPIO_Pin; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param PortVal: specifies the value to be written to the port output data register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; + /* Read LCKK bit*/ + tmp = GPIOx->LCKR; +} + +/** + * @brief Selects the GPIO pin used as Event output. + * @param GPIO_PortSource: selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). + * @param GPIO_PinSource: specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @retval None + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmpreg = AFIO->EVCR; + /* Clear the PORT[6:4] and PIN[3:0] bits */ + tmpreg &= EVCR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->EVCR = tmpreg; +} + +/** + * @brief Enables or disables the Event Output. + * @param NewState: new state of the Event output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; +} + +/** + * @brief Changes the mapping of the specified pin. + * @param GPIO_Remap: selects the pin to remap. + * This parameter can be one of the following values: + * @arg GPIO_Remap_SPI1 + * @arg GPIO_Remap_I2C1 + * @arg GPIO_Remap_USART1 + * @arg GPIO_Remap_USART2 + * @arg GPIO_PartialRemap_USART3 + * @arg GPIO_FullRemap_USART3 + * @arg GPIO_PartialRemap_TIM1 + * @arg GPIO_FullRemap_TIM1 + * @arg GPIO_PartialRemap1_TIM2 + * @arg GPIO_PartialRemap2_TIM2 + * @arg GPIO_FullRemap_TIM2 + * @arg GPIO_PartialRemap_TIM3 + * @arg GPIO_FullRemap_TIM3 + * @arg GPIO_Remap_TIM4 + * @arg GPIO_Remap1_CAN1 + * @arg GPIO_Remap2_CAN1 + * @arg GPIO_Remap_PD01 + * @arg GPIO_Remap_TIM5CH4_LSI + * @arg GPIO_Remap_ADC1_ETRGINJ + * @arg GPIO_Remap_ADC1_ETRGREG + * @arg GPIO_Remap_ADC2_ETRGINJ + * @arg GPIO_Remap_ADC2_ETRGREG + * @arg GPIO_Remap_ETH + * @arg GPIO_Remap_CAN2 + * @arg GPIO_Remap_SWJ_NoJTRST + * @arg GPIO_Remap_SWJ_JTAGDisable + * @arg GPIO_Remap_SWJ_Disable + * @arg GPIO_Remap_SPI3 + * @arg GPIO_Remap_TIM2ITR1_PTP_SOF + * @arg GPIO_Remap_PTP_PPS + * @arg GPIO_Remap_TIM15 + * @arg GPIO_Remap_TIM16 + * @arg GPIO_Remap_TIM17 + * @arg GPIO_Remap_CEC + * @arg GPIO_Remap_TIM1_DMA + * @arg GPIO_Remap_TIM9 + * @arg GPIO_Remap_TIM10 + * @arg GPIO_Remap_TIM11 + * @arg GPIO_Remap_TIM13 + * @arg GPIO_Remap_TIM14 + * @arg GPIO_Remap_FSMC_NADV + * @note If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected + * to Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. + * @param NewState: new state of the port pin remapping. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_REMAP(GPIO_Remap)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg = AFIO->MAPR2; + } + else + { + tmpreg = AFIO->MAPR; + } + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->MAPR &= DBGAFR_SWJCFG_MASK; + } + else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + + if (NewState != DISABLE) + { + tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); + } + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + AFIO->MAPR2 = tmpreg; + } + else + { + AFIO->MAPR = tmpreg; + } +} + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). + * @param GPIO_PinSource: specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * @retval None + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + /* Check the parameters */ + assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/** + * @brief Selects the Ethernet media interface. + * @note This function applies only to STM32 Connectivity line devices. + * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode. + * This parameter can be one of the following values: + * @arg GPIO_ETH_MediaInterface_MII: MII mode + * @arg GPIO_ETH_MediaInterface_RMII: RMII mode + * @retval None + */ +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) +{ + assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); + + /* Configure MII_RMII selection bit */ + *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_i2c.c b/example/libs_stm/src/stm32f10x/stm32f10x_i2c.c new file mode 100644 index 000000000..32545f5ed --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_i2c.c @@ -0,0 +1,1285 @@ +/** + ****************************************************************************** + * @file stm32f10x_i2c.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the I2C firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_i2c.h" +#include "stm32f10x_rcc.h" + + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup I2C + * @brief I2C driver modules + * @{ + */ + +/** @defgroup I2C_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Defines + * @{ + */ + +/* I2C SPE mask */ +#define CR1_PE_Set ((uint16_t)0x0001) +#define CR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CR1_START_Set ((uint16_t)0x0100) +#define CR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CR1_STOP_Set ((uint16_t)0x0200) +#define CR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CR1_ACK_Set ((uint16_t)0x0400) +#define CR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CR1_ENGC_Set ((uint16_t)0x0040) +#define CR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CR1_SWRST_Set ((uint16_t)0x8000) +#define CR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CR1_PEC_Set ((uint16_t)0x1000) +#define CR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CR1_ENPEC_Set ((uint16_t)0x0020) +#define CR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CR1_ENARP_Set ((uint16_t)0x0010) +#define CR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CR2_DMAEN_Set ((uint16_t)0x0800) +#define CR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CR2_LAST_Set ((uint16_t)0x1000) +#define CR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OAR1_ADD0_Set ((uint16_t)0x0001) +#define OAR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OAR2_ENDUAL_Set ((uint16_t)0x0001) +#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OAR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CCR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CCR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/** + * @} + */ + +/** @defgroup I2C_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the I2Cx peripheral registers to their default reset values. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval None + */ +void I2C_DeInit(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + if (I2Cx == I2C1) + { + /* Enable I2C1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + /* Release I2C1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } + else + { + /* Enable I2C2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + /* Release I2C2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + } +} + +/** + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * @retval None + */ +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + RCC_ClocksTypeDef rcc_clocks; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); + assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); + assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + +/*---------------------------- I2Cx CR2 Configuration ------------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear frequency FREQ[5:0] bits */ + tmpreg &= CR2_FREQ_Reset; + /* Get pclk1 frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + /* Set frequency bits depending on pclk1 value */ + freqrange = (uint16_t)(pclk1 / 1000000); + tmpreg |= freqrange; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; + +/*---------------------------- I2Cx CCR Configuration ------------------------*/ + /* Disable the selected I2C peripheral to configure TRISE */ + I2Cx->CR1 &= CR1_PE_Reset; + /* Reset tmpreg value */ + /* Clear F/S, DUTY and CCR[11:0] bits */ + tmpreg = 0; + + /* Configure speed in standard mode */ + if (I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + /* Standard mode speed calculate */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + /* Test if CCR value is under 0x4*/ + if (result < 0x04) + { + /* Set minimum allowed value */ + result = 0x04; + } + /* Set speed value for standard mode */ + tmpreg |= result; + /* Set Maximum Rise Time for standard mode */ + I2Cx->TRISE = freqrange + 1; + } + /* Configure speed in fast mode */ + else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ + { + if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + /* Set DUTY bit */ + result |= I2C_DutyCycle_16_9; + } + + /* Test if CCR value is under 0x1*/ + if ((result & CCR_CCR_Set) == 0) + { + /* Set minimum allowed value */ + result |= (uint16_t)0x0001; + } + /* Set speed value and set F/S bit for fast mode */ + tmpreg |= (uint16_t)(result | CCR_FS_Set); + /* Set Maximum Rise Time for fast mode */ + I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + /* Write to I2Cx CCR */ + I2Cx->CCR = tmpreg; + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + +/*---------------------------- I2Cx CR1 Configuration ------------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear ACK, SMBTYPE and SMBUS bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure I2Cx: mode and acknowledgement */ + /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ + /* Set ACK bit according to I2C_Ack value */ + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + +/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ + /* Set I2Cx Own Address1 and acknowledged address */ + I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ +/*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the I2C_ClockSpeed member */ + I2C_InitStruct->I2C_ClockSpeed = 5000; + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + /* Initialize the I2C_DutyCycle member */ + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= CR1_PE_Set; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= CR1_PE_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C DMA requests. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR2 |= CR2_DMAEN_Set; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR2 &= CR2_DMAEN_Reset; + } +} + +/** + * @brief Specifies if the next DMA transfer will be the last one. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C DMA last transfer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Next DMA transfer is the last transfer */ + I2Cx->CR2 |= CR2_LAST_Set; + } + else + { + /* Next DMA transfer is not the last transfer */ + I2Cx->CR2 &= CR2_LAST_Reset; + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR1 |= CR1_START_Set; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR1 &= CR1_START_Reset; + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR1 |= CR1_STOP_Set; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR1 &= CR1_STOP_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C acknowledge feature. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C Acknowledgement. + * This parameter can be: ENABLE or DISABLE. + * @retval None. + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the acknowledgement */ + I2Cx->CR1 |= CR1_ACK_Set; + } + else + { + /* Disable the acknowledgement */ + I2Cx->CR1 &= CR1_ACK_Reset; + } +} + +/** + * @brief Configures the specified I2C own address2. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the 7bit I2C own address2. + * @retval None. + */ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + tmpreg &= OAR2_ADD2_Reset; + + /* Set I2Cx Own address2 */ + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/** + * @brief Enables or disables the specified I2C dual addressing mode. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C dual addressing mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable dual addressing mode */ + I2Cx->OAR2 |= OAR2_ENDUAL_Set; + } + else + { + /* Disable dual addressing mode */ + I2Cx->OAR2 &= OAR2_ENDUAL_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C general call feature. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C General call. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable generall call */ + I2Cx->CR1 |= CR1_ENGC_Set; + } + else + { + /* Disable generall call */ + I2Cx->CR1 &= CR1_ENGC_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_IT_BUF: Buffer interrupt mask + * @arg I2C_IT_EVT: Event interrupt mask + * @arg I2C_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR2 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR2 &= (uint16_t)~I2C_IT; + } +} + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Data: Byte to be transmitted.. + * @retval None + */ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Write in the DR register the data to be sent */ + I2Cx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the data in the DR register */ + return (uint8_t)I2Cx->DR; +} + +/** + * @brief Transmits the address byte to select the slave device. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param Address: specifies the slave address which will be transmitted + * @param I2C_Direction: specifies whether the I2C device will be a + * Transmitter or a Receiver. This parameter can be one of the following values + * @arg I2C_Direction_Transmitter: Transmitter mode + * @arg I2C_Direction_Receiver: Receiver mode + * @retval None. + */ +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction != I2C_Direction_Transmitter) + { + /* Set the address bit0 for read */ + Address |= OAR1_ADD0_Set; + } + else + { + /* Reset the address bit0 for write */ + Address &= OAR1_ADD0_Reset; + } + /* Send the address */ + I2Cx->DR = Address; +} + +/** + * @brief Reads the specified I2C register and returns its value. + * @param I2C_Register: specifies the register to read. + * This parameter can be one of the following values: + * @arg I2C_Register_CR1: CR1 register. + * @arg I2C_Register_CR2: CR2 register. + * @arg I2C_Register_OAR1: OAR1 register. + * @arg I2C_Register_OAR2: OAR2 register. + * @arg I2C_Register_DR: DR register. + * @arg I2C_Register_SR1: SR1 register. + * @arg I2C_Register_SR2: SR2 register. + * @arg I2C_Register_CCR: CCR register. + * @arg I2C_Register_TRISE: TRISE register. + * @retval The value of the read register. + */ +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (uint32_t) I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t *) tmp); +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C software reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Peripheral under reset */ + I2Cx->CR1 |= CR1_SWRST_Set; + } + else + { + /* Peripheral not under reset */ + I2Cx->CR1 &= CR1_SWRST_Reset; + } +} + +/** + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_SMBusAlert: specifies SMBAlert pin level. + * This parameter can be one of the following values: + * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low + * @arg I2C_SMBusAlert_High: SMBAlert pin driven high + * @retval None + */ +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); + if (I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + /* Drive the SMBusAlert pin Low */ + I2Cx->CR1 |= I2C_SMBusAlert_Low; + } + else + { + /* Drive the SMBusAlert pin High */ + I2Cx->CR1 &= I2C_SMBusAlert_High; + } +} + +/** + * @brief Enables or disables the specified I2C PEC transfer. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2C PEC transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC transmission */ + I2Cx->CR1 |= CR1_PEC_Set; + } + else + { + /* Disable the selected I2C PEC transmission */ + I2Cx->CR1 &= CR1_PEC_Reset; + } +} + +/** + * @brief Selects the specified I2C PEC position. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_PECPosition: specifies the PEC position. + * This parameter can be one of the following values: + * @arg I2C_PECPosition_Next: indicates that the next byte is PEC + * @arg I2C_PECPosition_Current: indicates that current byte is PEC + * @retval None + */ +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); + if (I2C_PECPosition == I2C_PECPosition_Next) + { + /* Next byte in shift register is PEC */ + I2Cx->CR1 |= I2C_PECPosition_Next; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CR1 &= I2C_PECPosition_Current; + } +} + +/** + * @brief Enables or disables the PEC value calculation of the transfered bytes. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C PEC calculation */ + I2Cx->CR1 |= CR1_ENPEC_Set; + } + else + { + /* Disable the selected I2C PEC calculation */ + I2Cx->CR1 &= CR1_ENPEC_Reset; + } +} + +/** + * @brief Returns the PEC value for the specified I2C. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @retval The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + /* Return the selected I2C PEC value */ + return ((I2Cx->SR2) >> 8); +} + +/** + * @brief Enables or disables the specified I2C ARP. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx ARP. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C ARP */ + I2Cx->CR1 |= CR1_ENARP_Set; + } + else + { + /* Disable the selected I2C ARP */ + I2Cx->CR1 &= CR1_ENARP_Reset; + } +} + +/** + * @brief Enables or disables the specified I2C Clock stretching. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState == DISABLE) + { + /* Enable the selected I2C Clock stretching */ + I2Cx->CR1 |= CR1_NOSTRETCH_Set; + } + else + { + /* Disable the selected I2C Clock stretching */ + I2Cx->CR1 &= CR1_NOSTRETCH_Reset; + } +} + +/** + * @brief Selects the specified I2C fast mode duty cycle. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_DutyCycle: specifies the fast mode duty cycle. + * This parameter can be one of the following values: + * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 + * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 + * @retval None + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); + if (I2C_DutyCycle != I2C_DutyCycle_16_9) + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CCR &= I2C_DutyCycle_2; + } + else + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CCR |= I2C_DutyCycle_16_9; + } +} + + + +/** + * @brief + **************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * depending on the application requirements and constraints: + * + * + * 1) Basic state monitoring: + * Using I2C_CheckEvent() function: + * It compares the status registers (SR1 and SR2) content to a given event + * (can be the combination of one or more flags). + * It returns SUCCESS if the current status includes the given flags + * and returns ERROR if one or more flags are missing in the current status. + * - When to use: + * - This function is suitable for most applciations as well as for startup + * activity since the events are fully described in the product reference manual + * (RM0008). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs (ie. error flags are set besides to the monitored flags), + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * hold or corrupted real state. + * In this case, it is advised to use error interrupts to monitor the error + * events and handle them in the interrupt IRQ handler. + * + * @note + * For error management, it is advised to use the following functions: + * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). + * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() + * in order to determine which error occured. + * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() + * and/or I2C_GenerateStop() in order to clear the error flag and source, + * and return to correct communication status. + * + * + * 2) Advanced state monitoring: + * Using the function I2C_GetLastEvent() which returns the image of both status + * registers in a single word (uint32_t) (Status Register 2 value is shifted left + * by 16 bits and concatenated to Status Register 1). + * - When to use: + * - This function is suitable for the same applications above but it allows to + * overcome the mentionned limitation of I2C_GetFlagStatus() function. + * The returned value could be compared to events already defined in the + * library (stm32f10x_i2c.h) or to custom values defiend by user. + * - This function is suitable when multiple flags are monitored at the same time. + * - At the opposite of I2C_CheckEvent() function, this function allows user to + * choose when an event is accepted (when all events flags are set and no + * other flags are set or just when the needed flags are set like + * I2C_CheckEvent() function). + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * 3) Flag-based state monitoring: + * Using the function I2C_GetFlagStatus() which simply returns the status of + * one single flag (ie. I2C_FLAG_RXNE ...). + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed (most I2C events + * are monitored through multiple flags). + * - Limitations: + * - When calling this function, the Status register is accessed. Some flags are + * cleared when the status register is accessed. So checking the status + * of one Flag, may clear other ones. + * - Function may need to be called twice or more in order to monitor one + * single event. + * + * For detailed description of Events, please refer to section I2C_Events in + * stm32f10x_i2c.h file. + * + */ + +/** + * + * 1) Basic state monitoring + ******************************************************************************* + */ + +/** + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_EVENT: specifies the event to be checked. + * This parameter can be one of the following values: + * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1 + * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2 + * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2 + * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3 + * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3 + * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2 + * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 + * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 + * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6 + * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8 + * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2 + * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in stm32f10x_i2c.h file. + * + * @retval An ErrorStatus enumuration value: + * - SUCCESS: Last event is equal to the I2C_EVENT + * - ERROR: Last event is different from the I2C_EVENT + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_EVENT(I2C_EVENT)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + + /* Check whether the last event contains the I2C_EVENT */ + if ((lastevent & I2C_EVENT) == I2C_EVENT) + { + /* SUCCESS: last event is equal to I2C_EVENT */ + status = SUCCESS; + } + else + { + /* ERROR: last event is different from I2C_EVENT */ + status = ERROR; + } + /* Return status */ + return status; +} + +/** + * + * 2) Advanced state monitoring + ******************************************************************************* + */ + +/** + * @brief Returns the last I2Cx Event. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * + * @note: For detailed description of Events, please refer to section + * I2C_Events in stm32f10x_i2c.h file. + * + * @retval The last event + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Read the I2Cx status register */ + flag1 = I2Cx->SR1; + flag2 = I2Cx->SR2; + flag2 = flag2 << 16; + + /* Get the last event value from I2C status register */ + lastevent = (flag1 | flag2) & FLAG_Mask; + + /* Return status */ + return lastevent; +} + +/** + * + * 3) Flag-based state monitoring + ******************************************************************************* + */ + +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) + * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) + * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) + * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) + * @arg I2C_FLAG_TRA: Transmitter/Receiver flag + * @arg I2C_FLAG_BUSY: Bus busy flag + * @arg I2C_FLAG_MSL: Master/Slave flag + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) + * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag + * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) + * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_FLAG_BTF: Byte transfer finished flag + * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) ADSL + * Address matched flag (Slave mode)ENDAD + * @arg I2C_FLAG_SB: Start bit flag (Master mode) + * @retval The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the I2Cx peripheral base address */ + i2cxbase = (uint32_t)I2Cx; + + /* Read flag register index */ + i2creg = I2C_FLAG >> 28; + + /* Get bit[23:0] of the flag */ + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + /* Get the I2Cx SR1 register address */ + i2cxbase += 0x14; + } + else + { + /* Flag in I2Cx SR2 Register */ + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + /* Get the I2Cx SR2 register address */ + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + + /* Return the I2C_FLAG status */ + return bitstatus; +} + + + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_SMBALERT: SMBus Alert flag + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_FLAG_PECERR: PEC error in reception flag + * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_FLAG_AF: Acknowledge failure flag + * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_FLAG_BERR: Bus error flag + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR + * register (I2C_SendData()). + * @retval None + */ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + /* Get the I2C flag position */ + flagpos = I2C_FLAG & FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert flag + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag + * @arg I2C_IT_PECERR: PEC error in reception flag + * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure flag + * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) + * @arg I2C_IT_BERR: Bus error flag + * @arg I2C_IT_TXE: Data register empty flag (Transmitter) + * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag + * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) + * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) + * @arg I2C_IT_BTF: Byte transfer finished flag + * @arg I2C_IT_ADDR: Address sent flag (Master mode) ADSL + * Address matched flag (Slave mode)ENDAD + * @arg I2C_IT_SB: Start bit flag (Master mode) + * @retval The new state of I2C_IT (SET or RESET). + */ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ; + + /* Get bit[23:0] of the flag */ + I2C_IT &= FLAG_Mask; + + /* Check the status of the specified I2C flag */ + if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cxs interrupt pending bits. + * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_IT_SMBALERT: SMBus Alert interrupt + * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt + * @arg I2C_IT_PECERR: PEC error in reception interrupt + * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) + * @arg I2C_IT_AF: Acknowledge failure interrupt + * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) + * @arg I2C_IT_BERR: Bus error interrupt + * + * @note + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_SR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DR register (I2C_SendData()). + * @retval None + */ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + /* Get the I2C flag position */ + flagpos = I2C_IT & FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->SR1 = (uint16_t)~flagpos; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_iwdg.c b/example/libs_stm/src/stm32f10x/stm32f10x_iwdg.c new file mode 100644 index 000000000..58ab061c3 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_iwdg.c @@ -0,0 +1,189 @@ +/** + ****************************************************************************** + * @file stm32f10x_iwdg.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the IWDG firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_iwdg.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup IWDG + * @brief IWDG driver modules + * @{ + */ + +/** @defgroup IWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Defines + * @{ + */ + +/* ---------------------- IWDG registers bit mask ----------------------------*/ + +/* KR register bit mask */ +#define KR_KEY_Reload ((uint16_t)0xAAAA) +#define KR_KEY_Enable ((uint16_t)0xCCCC) + +/** + * @} + */ + +/** @defgroup IWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup IWDG_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers + * @retval None + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + IWDG->KR = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler: specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 + * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 + * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 + * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 + * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 + * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 + * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 + * @retval None + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + IWDG->PR = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload: specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * @retval None + */ +void IWDG_SetReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RLR = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_Reload; +} + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_Enable; +} + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_FLAG_PVU: Prescaler Value Update on going + * @arg IWDG_FLAG_RVU: Reload Value Update on going + * @retval The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_pwr.c b/example/libs_stm/src/stm32f10x/stm32f10x_pwr.c new file mode 100644 index 000000000..a017ac681 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_pwr.c @@ -0,0 +1,316 @@ +/** + ****************************************************************************** + * @file stm32f10x_pwr.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the PWR firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup PWR + * @brief PWR driver modules + * @{ + */ + +/** @defgroup PWR_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Defines + * @{ + */ + +/* --------- PWR registers bit address in the alias region ---------- */ +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of DBP bit */ +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) + +/* Alias word address of PVDE bit */ +#define PVDE_BitNumber 0x04 +#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of EWUP bit */ +#define CSR_OFFSET (PWR_OFFSET + 0x04) +#define EWUP_BitNumber 0x08 +#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_PDDS_Set ((uint32_t)0x00000002) +#define CR_DS_Mask ((uint32_t)0xFFFFFFFC) +#define CR_CWUF_Set ((uint32_t)0x00000004) +#define CR_PLS_Mask ((uint32_t)0xFFFFFF1F) + +/* --------- Cortex System Control register bit mask ---------------- */ + +/* Cortex System Control register address */ +#define SCB_SysCtrl ((uint32_t)0xE000ED10) + +/* SLEEPDEEP bit mask */ +#define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004) +#define SysCtrl_SLEEPDEEP_Reset ((uint32_t)0xFFFFFFFB) + +/** + * @} + */ + +/** @defgroup PWR_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup PWR_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @param None + * @retval None + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/** + * @brief Enables or disables access to the RTC and backup registers. + * @param NewState: new state of the access to the RTC and backup registers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param NewState: new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDLevel: specifies the PVD detection level + * This parameter can be one of the following values: + * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V + * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V + * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V + * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V + * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V + * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V + * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V + * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V + * @retval None + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); + tmpreg = PWR->CR; + /* Clear PLS[7:5] bits */ + tmpreg &= CR_PLS_Mask; + /* Set PLS[7:5] bits according to PWR_PVDLevel value */ + tmpreg |= PWR_PVDLevel; + /* Store the new value */ + PWR->CR = tmpreg; +} + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param NewState: new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; +} + +/** + * @brief Enters STOP mode. + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_Regulator_ON: STOP mode with regulator ON + * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction + * @retval None + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); + + /* Select the regulator state in STOP mode ---------------------------------*/ + tmpreg = PWR->CR; + /* Clear PDDS and LPDS bits */ + tmpreg &= CR_DS_Mask; + /* Set LPDS bit according to PWR_Regulator value */ + tmpreg |= PWR_Regulator; + /* Store the new value */ + PWR->CR = tmpreg; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; + + /* Select STOP mode entry --------------------------------------------------*/ + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + *(__IO uint32_t *) SCB_SysCtrl &= SysCtrl_SLEEPDEEP_Reset; +} + +/** + * @brief Enters STANDBY mode. + * @param None + * @retval None + */ +void PWR_EnterSTANDBYMode(void) +{ + /* Clear Wake-up flag */ + PWR->CR |= CR_CWUF_Set; + /* Select STANDBY mode */ + PWR->CR |= CR_PDDS_Set; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; +/* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM ) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @arg PWR_FLAG_PVDO: PVD Output + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag + * @arg PWR_FLAG_SB: StandBy flag + * @retval None + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + PWR->CR |= PWR_FLAG << 2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_rcc.c b/example/libs_stm/src/stm32f10x/stm32f10x_rcc.c new file mode 100644 index 000000000..0fb0d58a0 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_rcc.c @@ -0,0 +1,1477 @@ +/** + ****************************************************************************** + * @file stm32f10x_rcc.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the RCC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup RCC + * @brief RCC driver modules + * @{ + */ + +/** @defgroup RCC_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Defines + * @{ + */ + +/* ------------ RCC registers bit address in the alias region ----------- */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* --- CR Register ---*/ + +/* Alias word address of HSION bit */ +#define CR_OFFSET (RCC_OFFSET + 0x00) +#define HSION_BitNumber 0x00 +#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) + +/* Alias word address of PLLON bit */ +#define PLLON_BitNumber 0x18 +#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) + +#ifdef STM32F10X_CL + /* Alias word address of PLL2ON bit */ + #define PLL2ON_BitNumber 0x1A + #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) + + /* Alias word address of PLL3ON bit */ + #define PLL3ON_BitNumber 0x1C + #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* Alias word address of CSSON bit */ +#define CSSON_BitNumber 0x13 +#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) + +/* --- CFGR Register ---*/ + +/* Alias word address of USBPRE bit */ +#define CFGR_OFFSET (RCC_OFFSET + 0x04) + +#ifndef STM32F10X_CL + #define USBPRE_BitNumber 0x16 + #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) +#else + #define OTGFSPRE_BitNumber 0x16 + #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* --- BDCR Register ---*/ + +/* Alias word address of RTCEN bit */ +#define BDCR_OFFSET (RCC_OFFSET + 0x20) +#define RTCEN_BitNumber 0x0F +#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) + +/* Alias word address of BDRST bit */ +#define BDRST_BitNumber 0x10 +#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) + +/* --- CSR Register ---*/ + +/* Alias word address of LSION bit */ +#define CSR_OFFSET (RCC_OFFSET + 0x24) +#define LSION_BitNumber 0x00 +#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) + +#ifdef STM32F10X_CL +/* --- CFGR2 Register ---*/ + + /* Alias word address of I2S2SRC bit */ + #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) + #define I2S2SRC_BitNumber 0x11 + #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) + + /* Alias word address of I2S3SRC bit */ + #define I2S3SRC_BitNumber 0x12 + #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) +#endif /* STM32F10X_CL */ + +/* ---------------------- RCC registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CR_HSEBYP_Set ((uint32_t)0x00040000) +#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CR_HSEON_Set ((uint32_t)0x00010000) +#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +/* CFGR register bit mask */ +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) + #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) +#else + #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) +#endif /* STM32F10X_CL */ + +#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* CSR register bit mask */ +#define CSR_RMVF_Set ((uint32_t)0x01000000) + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) +/* CFGR2 register bit mask */ + #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) + #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) +#endif +#ifdef STM32F10X_CL + #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) + #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) + #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) +#endif /* STM32F10X_CL */ + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +#ifndef HSI_Value +/* Typical Value of the HSI in Hz */ + #define HSI_Value ((uint32_t)8000000) +#endif /* HSI_Value */ + +/* CIR register byte 2 (Bits[15:8]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR register byte 4 (Bits[31:24]) base address */ +#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCR register base address */ +#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) + +#ifndef HSEStartUp_TimeOut +/* Time out for HSE start up */ + #define HSEStartUp_TimeOut ((uint16_t)0x0500) +#endif /* HSEStartUp_TimeOut */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Variables + * @{ + */ + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/** + * @} + */ + +/** @defgroup RCC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RCC_Private_Functions + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note HSE can not be stopped if it is used directly or through the PLL as system clock. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: HSE oscillator OFF + * @arg RCC_HSE_ON: HSE oscillator ON + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + /* Reset HSEON bit */ + RCC->CR &= CR_HSEON_Reset; + /* Reset HSEBYP bit */ + RCC->CR &= CR_HSEBYP_Reset; + /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ + switch(RCC_HSE) + { + case RCC_HSE_ON: + /* Set HSEON bit */ + RCC->CR |= CR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + /* Set HSEBYP and HSEON bits */ + RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; + break; + + default: + break; + } +} + +/** + * @brief Waits for HSE start-up. + * @param None + * @retval An ErrorStatus enumuration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSEStartUp_TimeOut) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @param HSICalibrationValue: specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); + tmpreg = RCC->CR; + /* Clear HSITRIM[4:0] bits */ + tmpreg &= CR_HSITRIM_Mask; + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= (uint32_t)HSICalibrationValue << 3; + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note HSI can not be stopped if it is used directly or through the PLL as system clock. + * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the PLL clock source and multiplication factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLSource: specifies the PLL entry clock source. + * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, + * this parameter can be one of the following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry + * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry + * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry + * @param RCC_PLLMul: specifies the PLL multiplication factor. + * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} + * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] + * @retval None + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); + assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); + + tmpreg = RCC->CFGR; + /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ + tmpreg &= CFGR_PLL_Mask; + /* Set the PLL configuration bits */ + tmpreg |= RCC_PLLSource | RCC_PLLMul; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Enables or disables the PLL. + * @note The PLL can not be disabled if it is used as system clock. + * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; +} + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) +/** + * @brief Configures the PREDIV1 division factor. + * @note + * - This function must be used only when the PLL is disabled. + * - This function applies only to STM32 Connectivity line and Value line + * devices. + * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. + * This parameter can be one of the following values: + * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock + * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock + * @note + * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE + * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. + * This parameter can be RCC_PREDIV1_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); + assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV1[3:0] and PREDIV1SRC bits */ + tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); + /* Set the PREDIV1 clock source and division factor */ + tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} +#endif + +#ifdef STM32F10X_CL +/** + * @brief Configures the PREDIV2 division factor. + * @note + * - This function must be used only when both PLL2 and PLL3 are disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. + * This parameter can be RCC_PREDIV2_Divx where x:[1,16] + * @retval None + */ +void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); + + tmpreg = RCC->CFGR2; + /* Clear PREDIV2[3:0] bits */ + tmpreg &= ~CFGR2_PREDIV2; + /* Set the PREDIV2 division factor */ + tmpreg |= RCC_PREDIV2_Div; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + +/** + * @brief Configures the PLL2 multiplication factor. + * @note + * - This function must be used only when the PLL2 is disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. + * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} + * @retval None + */ +void RCC_PLL2Config(uint32_t RCC_PLL2Mul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); + + tmpreg = RCC->CFGR2; + /* Clear PLL2Mul[3:0] bits */ + tmpreg &= ~CFGR2_PLL2MUL; + /* Set the PLL2 configuration bits */ + tmpreg |= RCC_PLL2Mul; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + + +/** + * @brief Enables or disables the PLL2. + * @note + * - The PLL2 can not be disabled if it is used indirectly as system clock + * (i.e. it is used as PLL clock entry that is used as System clock). + * - This function applies only to STM32 Connectivity line devices. + * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLL2Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; +} + + +/** + * @brief Configures the PLL3 multiplication factor. + * @note + * - This function must be used only when the PLL3 is disabled. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. + * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} + * @retval None + */ +void RCC_PLL3Config(uint32_t RCC_PLL3Mul) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); + + tmpreg = RCC->CFGR2; + /* Clear PLL3Mul[3:0] bits */ + tmpreg &= ~CFGR2_PLL3MUL; + /* Set the PLL3 configuration bits */ + tmpreg |= RCC_PLL3Mul; + /* Store the new value */ + RCC->CFGR2 = tmpreg; +} + + +/** + * @brief Enables or disables the PLL3. + * @note This function applies only to STM32 Connectivity line devices. + * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLL3Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the system clock (SYSCLK). + * @param RCC_SYSCLKSource: specifies the clock source used as system clock. + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + tmpreg = RCC->CFGR; + /* Clear SW[1:0] bits */ + tmpreg &= CFGR_SW_Mask; + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can + * be one of the following: + * - 0x00: HSI used as system clock + * - 0x04: HSE used as system clock + * - 0x08: PLL used as system clock + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + tmpreg = RCC->CFGR; + /* Clear HPRE[3:0] bits */ + tmpreg &= CFGR_HPRE_Reset_Mask; + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the Low Speed APB clock (PCLK1). + * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB1 clock = HCLK + * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE1[2:0] bits */ + tmpreg &= CFGR_PPRE1_Reset_Mask; + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the High Speed APB clock (PCLK2). + * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_Div1: APB2 clock = HCLK + * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 + * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 + * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 + * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 + * @retval None + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK)); + tmpreg = RCC->CFGR; + /* Clear PPRE2[2:0] bits */ + tmpreg &= CFGR_PPRE2_Reset_Mask; + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= RCC_HCLK << 3; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Enables or disables the specified RCC interrupts. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_IT(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ + *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +#ifndef STM32F10X_CL +/** + * @brief Configures the USB clock (USBCLK). + * @param RCC_USBCLKSource: specifies the USB clock source. This clock is + * derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB + * clock source + * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source + * @retval None + */ +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); + + *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; +} +#else +/** + * @brief Configures the USB OTG FS clock (OTGFSCLK). + * This function applies only to STM32 Connectivity line devices. + * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. + * This clock is derived from the PLL output. + * This parameter can be one of the following values: + * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source + * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source + * @retval None + */ +void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); + + *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the ADC clock (ADCCLK). + * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * This parameter can be one of the following values: + * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 + * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 + * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 + * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 + * @retval None + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); + tmpreg = RCC->CFGR; + /* Clear ADCPRE[1:0] bits */ + tmpreg &= CFGR_ADCPRE_Reset_Mask; + /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ + tmpreg |= RCC_PCLK2; + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +#ifdef STM32F10X_CL +/** + * @brief Configures the I2S2 clock source(I2S2CLK). + * @note + * - This function must be called before enabling I2S2 APB clock. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_I2S2CLKSource: specifies the I2S2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry + * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry + * @retval None + */ +void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); + + *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; +} + +/** + * @brief Configures the I2S3 clock source(I2S2CLK). + * @note + * - This function must be called before enabling I2S3 APB clock. + * - This function applies only to STM32 Connectivity line devices. + * @param RCC_I2S3CLKSource: specifies the I2S3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry + * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry + * @retval None + */ +void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); + + *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; +} +#endif /* STM32F10X_CL */ + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: LSE oscillator OFF + * @arg RCC_LSE_ON: LSE oscillator ON + * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + /* Reset LSEBYP bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; + /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ + switch(RCC_LSE) + { + case RCC_LSE_ON: + /* Set LSEON bit */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + /* Set LSEBYP and LSEON bits */ + *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; +} + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note Once the RTC clock is selected it cant be changed unless the Backup domain is reset. + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + /* Select the RTC clock source */ + RCC->BDCR |= RCC_RTCCLKSource; +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; +} + +/** + * @brief Returns the frequencies of different on chip clocks. + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + uint32_t prediv1factor = 0; +#endif + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & CFGR_SWS_Mask; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_Value; + break; + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_Value; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & CFGR_PLLMull_Mask; + pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { /* HSE oscillator clock selected as PREDIV1 clock entry */ + RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; + RCC_Clocks->SYSCLK_Frequency = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_Value; + break; + } + + /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + /* Get PCLK1 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get PCLK2 prescaler */ + tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + /* PCLK2 clock frequency */ + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + /* Get ADCCLK prescaler */ + tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + /* ADCCLK clock frequency */ + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/** + * @brief Enables or disables the AHB peripheral clock. + * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values: + * @arg RCC_AHBPeriph_DMA1 + * @arg RCC_AHBPeriph_DMA2 + * @arg RCC_AHBPeriph_SRAM + * @arg RCC_AHBPeriph_FLITF + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_OTG_FS + * @arg RCC_AHBPeriph_ETH_MAC + * @arg RCC_AHBPeriph_ETH_MAC_Tx + * @arg RCC_AHBPeriph_ETH_MAC_Rx + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values: + * @arg RCC_AHBPeriph_DMA1 + * @arg RCC_AHBPeriph_DMA2 + * @arg RCC_AHBPeriph_SRAM + * @arg RCC_AHBPeriph_FLITF + * @arg RCC_AHBPeriph_CRC + * @arg RCC_AHBPeriph_FSMC + * @arg RCC_AHBPeriph_SDIO + * + * @note SRAM and FLITF clock can be disabled only during sleep mode. + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBENR &= ~RCC_AHBPeriph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, + * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, + * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, + * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, + * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, + * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, + * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, + * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, + * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, + * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, + * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, + * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, + * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +#ifdef STM32F10X_CL +/** + * @brief Forces or releases AHB peripheral reset. + * @note This function applies only to STM32 Connectivity line devices. + * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHBPeriph_OTG_FS + * @arg RCC_AHBPeriph_ETH_MAC + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHBRSTR |= RCC_AHBPeriph; + } + else + { + RCC->AHBRSTR &= ~RCC_AHBPeriph; + } +} +#endif /* STM32F10X_CL */ + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, + * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, + * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, + * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, + * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, + * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, + * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, + * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, + * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, + * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, + * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, + * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, + * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, + * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Forces or releases the Backup domain reset. + * @param NewState: new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the Clock Security System. + * @param NewState: new state of the Clock Security System.. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param RCC_MCO: specifies the clock source to output. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_MCO_NoClock: No clock selected + * @arg RCC_MCO_SYSCLK: System clock selected + * @arg RCC_MCO_HSI: HSI oscillator clock selected + * @arg RCC_MCO_HSE: HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected + * @arg RCC_MCO_PLL2CLK: PLL2 clock selected + * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected + * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected + * @arg RCC_MCO_PLL3CLK: PLL3 clock selected + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_MCO_NoClock: No clock selected + * @arg RCC_MCO_SYSCLK: System clock selected + * @arg RCC_MCO_HSI: HSI oscillator clock selected + * @arg RCC_MCO_HSE: HSE oscillator clock selected + * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected + * + * @retval None + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCO)); + + /* Perform Byte access to MCO bits to select the MCO source */ + *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; +} + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG: specifies the flag to check. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready + * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_LPWRRST: Low Power reset + * + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG >> 5; + if (tmp == 1) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + /* Get the flag position */ + tmp = RCC_FLAG & FLAG_Mask; + if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @param None + * @retval None + */ +void RCC_ClearFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= CSR_RMVF_Set; +} + +/** + * @brief Checks whether the specified RCC interrupt has occurred or not. + * @param RCC_IT: specifies the RCC interrupt source to check. + * + * For @b STM32_Connectivity_line_devices, this parameter can be one of the + * following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * For @b other_STM32_devices, this parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * @retval The new state of RCC_IT (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RCC_GET_IT(RCC_IT)); + + /* Check the status of the specified RCC interrupt */ + if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the RCC_IT status */ + return bitstatus; +} + +/** + * @brief Clears the RCCs interrupt pending bits. + * @param RCC_IT: specifies the interrupt pending bit to clear. + * + * For @b STM32_Connectivity_line_devices, this parameter can be any combination + * of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt + * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt + * @arg RCC_IT_CSS: Clock Security System interrupt + * + * For @b other_STM32_devices, this parameter can be any combination of the + * following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt + * @arg RCC_IT_LSERDY: LSE ready interrupt + * @arg RCC_IT_HSIRDY: HSI ready interrupt + * @arg RCC_IT_HSERDY: HSE ready interrupt + * @arg RCC_IT_PLLRDY: PLL ready interrupt + * + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval None + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + /* Check the parameters */ + assert_param(IS_RCC_CLEAR_IT(RCC_IT)); + + /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt + pending bits */ + *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_rtc.c b/example/libs_stm/src/stm32f10x/stm32f10x_rtc.c new file mode 100644 index 000000000..2720124bd --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_rtc.c @@ -0,0 +1,341 @@ +/** + ****************************************************************************** + * @file stm32f10x_rtc.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the RTC firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_rtc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup RTC + * @brief RTC driver modules + * @{ + */ + +/** @defgroup RTC_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup RTC_Private_Defines + * @{ + */ + +#define CRL_CNF_Set ((uint16_t)0x0010) /*!< Configuration Flag Enable Mask */ +#define CRL_CNF_Reset ((uint16_t)0xFFEF) /*!< Configuration Flag Disable Mask */ +#define RTC_LSB_Mask ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ +#define PRLH_MSB_Mask ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Functions + * @{ + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @param NewState: new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RTC->CRH |= RTC_IT; + } + else + { + RTC->CRH &= (uint16_t)~RTC_IT; + } +} + +/** + * @brief Enters the RTC configuration mode. + * @param None + * @retval None + */ +void RTC_EnterConfigMode(void) +{ + /* Set the CNF flag to enter in the Configuration Mode */ + RTC->CRL |= CRL_CNF_Set; +} + +/** + * @brief Exits from the RTC configuration mode. + * @param None + * @retval None + */ +void RTC_ExitConfigMode(void) +{ + /* Reset the CNF flag to exit from the Configuration Mode */ + RTC->CRL &= CRL_CNF_Reset; +} + +/** + * @brief Gets the RTC counter value. + * @param None + * @retval RTC counter value. + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t tmp = 0; + tmp = RTC->CNTL; + return (((uint32_t)RTC->CNTH << 16 ) | tmp) ; +} + +/** + * @brief Sets the RTC counter value. + * @param CounterValue: RTC counter new value. + * @retval None + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + /* Set RTC COUNTER MSB word */ + RTC->CNTH = CounterValue >> 16; + /* Set RTC COUNTER LSB word */ + RTC->CNTL = (CounterValue & RTC_LSB_Mask); + RTC_ExitConfigMode(); +} + +/** + * @brief Sets the RTC prescaler value. + * @param PrescalerValue: RTC prescaler new value. + * @retval None + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + /* Check the parameters */ + assert_param(IS_RTC_PRESCALER(PrescalerValue)); + + RTC_EnterConfigMode(); + /* Set RTC PRESCALER MSB word */ + RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 16; + /* Set RTC PRESCALER LSB word */ + RTC->PRLL = (PrescalerValue & RTC_LSB_Mask); + RTC_ExitConfigMode(); +} + +/** + * @brief Sets the RTC alarm value. + * @param AlarmValue: RTC alarm new value. + * @retval None + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + /* Set the ALARM MSB word */ + RTC->ALRH = AlarmValue >> 16; + /* Set the ALARM LSB word */ + RTC->ALRL = (AlarmValue & RTC_LSB_Mask); + RTC_ExitConfigMode(); +} + +/** + * @brief Gets the RTC divider value. + * @param None + * @retval RTC Divider value. + */ +uint32_t RTC_GetDivider(void) +{ + uint32_t tmp = 0x00; + tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; + tmp |= RTC->DIVL; + return tmp; +} + +/** + * @brief Waits until last write operation on RTC registers has finished. + * @note This function must be called before any write to RTC registers. + * @param None + * @retval None + */ +void RTC_WaitForLastTask(void) +{ + /* Loop until RTOFF flag is set */ + while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/** + * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) + * are synchronized with RTC APB clock. + * @note This function must be called before any read operation after an APB reset + * or an APB clock stop. + * @param None + * @retval None + */ +void RTC_WaitForSynchro(void) +{ + /* Clear RSF flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; + /* Loop until RSF flag is set */ + while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG: specifies the flag to check. + * This parameter can be one the following values: + * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag + * @arg RTC_FLAG_RSF: Registers Synchronized flag + * @arg RTC_FLAG_OW: Overflow flag + * @arg RTC_FLAG_ALR: Alarm flag + * @arg RTC_FLAG_SEC: Second flag + * @retval The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTCs pending flags. + * @param RTC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after + * an APB reset or an APB Clock stop. + * @arg RTC_FLAG_OW: Overflow flag + * @arg RTC_FLAG_ALR: Alarm flag + * @arg RTC_FLAG_SEC: Second flag + * @retval None + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the coressponding RTC flag */ + RTC->CRL &= (uint16_t)~RTC_FLAG; +} + +/** + * @brief Checks whether the specified RTC interrupt has occured or not. + * @param RTC_IT: specifies the RTC interrupts sources to check. + * This parameter can be one of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @retval The new state of the RTC_IT (SET or RESET). + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_RTC_GET_IT(RTC_IT)); + + bitstatus = (ITStatus)(RTC->CRL & RTC_IT); + if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the RTCs interrupt pending bits. + * @param RTC_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_IT_OW: Overflow interrupt + * @arg RTC_IT_ALR: Alarm interrupt + * @arg RTC_IT_SEC: Second interrupt + * @retval None + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + /* Check the parameters */ + assert_param(IS_RTC_IT(RTC_IT)); + + /* Clear the coressponding RTC pending bit */ + RTC->CRL &= (uint16_t)~RTC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_sdio.c b/example/libs_stm/src/stm32f10x/stm32f10x_sdio.c new file mode 100644 index 000000000..9d4a3763d --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_sdio.c @@ -0,0 +1,798 @@ +/** + ****************************************************************************** + * @file stm32f10x_sdio.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the SDIO firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_sdio.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup SDIO + * @brief SDIO driver modules + * @{ + */ + +/** @defgroup SDIO_Private_TypesDefinitions + * @{ + */ + +/* ------------ SDIO registers bit address in the alias region ----------- */ +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* --- CLKCR Register ---*/ + +/* Alias word address of CLKEN bit */ +#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) +#define CLKEN_BitNumber 0x08 +#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) + +/* --- CMD Register ---*/ + +/* Alias word address of SDIOSUSPEND bit */ +#define CMD_OFFSET (SDIO_OFFSET + 0x0C) +#define SDIOSUSPEND_BitNumber 0x0B +#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) + +/* Alias word address of ENCMDCOMPL bit */ +#define ENCMDCOMPL_BitNumber 0x0C +#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) + +/* Alias word address of NIEN bit */ +#define NIEN_BitNumber 0x0D +#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) + +/* Alias word address of ATACMD bit */ +#define ATACMD_BitNumber 0x0E +#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) + +/* --- DCTRL Register ---*/ + +/* Alias word address of DMAEN bit */ +#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) +#define DMAEN_BitNumber 0x03 +#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) + +/* Alias word address of RWSTART bit */ +#define RWSTART_BitNumber 0x08 +#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) + +/* Alias word address of RWSTOP bit */ +#define RWSTOP_BitNumber 0x09 +#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) + +/* Alias word address of RWMOD bit */ +#define RWMOD_BitNumber 0x0A +#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) + +/* Alias word address of SDIOEN bit */ +#define SDIOEN_BitNumber 0x0B +#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) + +/* ---------------------- SDIO registers bit mask ------------------------ */ + +/* --- CLKCR Register ---*/ + +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* --- PWRCTRL Register ---*/ + +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* --- DCTRL Register ---*/ + +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* --- CMD Register ---*/ + +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/** + * @} + */ + +/** @defgroup SDIO_Private_Defines + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SDIO_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SDIO peripheral registers to their default reset values. + * @param None + * @retval None + */ +void SDIO_DeInit(void) +{ + SDIO->POWER = 0x00000000; + SDIO->CLKCR = 0x00000000; + SDIO->ARG = 0x00000000; + SDIO->CMD = 0x00000000; + SDIO->DTIMER = 0x00000000; + SDIO->DLEN = 0x00000000; + SDIO->DCTRL = 0x00000000; + SDIO->ICR = 0x00C007FF; + SDIO->MASK = 0x00000000; +} + +/** + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure + * that contains the configuration information for the SDIO peripheral. + * @retval None + */ +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); + assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); + assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); + assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); + assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); + +/*---------------------------- SDIO CLKCR Configuration ------------------------*/ + /* Get the SDIO CLKCR value */ + tmpreg = SDIO->CLKCR; + + /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ + tmpreg &= CLKCR_CLEAR_MASK; + + /* Set CLKDIV bits according to SDIO_ClockDiv value */ + /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ + /* Set BYPASS bit according to SDIO_ClockBypass value */ + /* Set WIDBUS bits according to SDIO_BusWide value */ + /* Set NEGEDGE bits according to SDIO_ClockEdge value */ + /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + /* Write to SDIO CLKCR */ + SDIO->CLKCR = tmpreg; +} + +/** + * @brief Fills each SDIO_InitStruct member with its default value. + * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) +{ + /* SDIO_InitStruct members default value */ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/** + * @brief Enables or disables the SDIO Clock. + * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ClockCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; +} + +/** + * @brief Sets the power status of the controller. + * @param SDIO_PowerState: new state of the Power state. + * This parameter can be one of the following values: + * @arg SDIO_PowerState_OFF + * @arg SDIO_PowerState_ON + * @retval None + */ +void SDIO_SetPowerState(uint32_t SDIO_PowerState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); + + SDIO->POWER &= PWR_PWRCTRL_MASK; + SDIO->POWER |= SDIO_PowerState; +} + +/** + * @brief Gets the power status of the controller. + * @param None + * @retval Power status of the controller. The returned value can + * be one of the following: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/** + * @brief Enables or disables the SDIO interrupts. + * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @param NewState: new state of the specified SDIO interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SDIO_IT(SDIO_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the SDIO interrupts */ + SDIO->MASK |= SDIO_IT; + } + else + { + /* Disable the SDIO interrupts */ + SDIO->MASK &= ~SDIO_IT; + } +} + +/** + * @brief Enables or disables the SDIO DMA request. + * @param NewState: new state of the selected SDIO DMA request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_DMACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; +} + +/** + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef + * structure that contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); + assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); + assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); + assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); + +/*---------------------------- SDIO ARG Configuration ------------------------*/ + /* Set the SDIO Argument value */ + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + +/*---------------------------- SDIO CMD Configuration ------------------------*/ + /* Get the SDIO CMD value */ + tmpreg = SDIO->CMD; + /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ + tmpreg &= CMD_CLEAR_MASK; + /* Set CMDINDEX bits according to SDIO_CmdIndex value */ + /* Set WAITRESP bits according to SDIO_Response value */ + /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ + /* Set CPSMEN bits according to SDIO_CPSM value */ + tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response + | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + /* Write to SDIO CMD */ + SDIO->CMD = tmpreg; +} + +/** + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef + * structure which will be initialized. + * @retval None + */ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) +{ + /* SDIO_CmdInitStruct members default value */ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/** + * @brief Returns command index of last command for which response received. + * @param None + * @retval Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCommandResponse(void) +{ + return (uint8_t)(SDIO->RESPCMD); +} + +/** + * @brief Returns response received from the card for the last command. + * @param SDIO_RESP: Specifies the SDIO response register. + * This parameter can be one of the following values: + * @arg SDIO_RESP1: Response Register 1 + * @arg SDIO_RESP2: Response Register 2 + * @arg SDIO_RESP3: Response Register 3 + * @arg SDIO_RESP4: Response Register 4 + * @retval The Corresponding response register value. + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_RESP(SDIO_RESP)); + + tmp = SDIO_RESP_ADDR + SDIO_RESP; + + return (*(__IO uint32_t *) tmp); +} + +/** + * @brief Initializes the SDIO data path according to the specified + * parameters in the SDIO_DataInitStruct. + * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that + * contains the configuration information for the SDIO command. + * @retval None + */ +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); + assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); + assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); + assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); + assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); + +/*---------------------------- SDIO DTIMER Configuration ---------------------*/ + /* Set the SDIO Data TimeOut value */ + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + +/*---------------------------- SDIO DLEN Configuration -----------------------*/ + /* Set the SDIO DataLength value */ + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + +/*---------------------------- SDIO DCTRL Configuration ----------------------*/ + /* Get the SDIO DCTRL value */ + tmpreg = SDIO->DCTRL; + /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ + tmpreg &= DCTRL_CLEAR_MASK; + /* Set DEN bit according to SDIO_DPSM value */ + /* Set DTMODE bit according to SDIO_TransferMode value */ + /* Set DTDIR bit according to SDIO_TransferDir value */ + /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ + tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir + | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + /* Write to SDIO DCTRL */ + SDIO->DCTRL = tmpreg; +} + +/** + * @brief Fills each SDIO_DataInitStruct member with its default value. + * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which + * will be initialized. + * @retval None + */ +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) +{ + /* SDIO_DataInitStruct members default value */ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @param None + * @retval Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/** + * @brief Read one data word from Rx FIFO. + * @param None + * @retval Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/** + * @brief Write one data word to Tx FIFO. + * @param Data: 32-bit data word to write. + * @retval None + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->FIFO = Data; +} + +/** + * @brief Returns the number of words left to be written to or read from FIFO. + * @param None + * @retval Remaining number of words. + */ +uint32_t SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/** + * @brief Starts the SD I/O Read Wait operation. + * @param NewState: new state of the Start SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; +} + +/** + * @brief Stops the SD I/O Read Wait operation. + * @param NewState: new state of the Stop SDIO Read Wait operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; +} + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. + * This parametre can be: + * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK + * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 + * @retval None + */ +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); + + *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; +} + +/** + * @brief Enables or disables the SD I/O Mode Operation. + * @param NewState: new state of SDIO specific operation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the SD I/O Mode suspend command sending. + * @param NewState: new state of the SD I/O Mode suspend command. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the command completion signal. + * @param NewState: new state of command completion signal. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; +} + +/** + * @brief Enables or disables the CE-ATA interrupt. + * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); +} + +/** + * @brief Sends CE-ATA command (CMD61). + * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; +} + +/** + * @brief Checks whether the specified SDIO flag is set or not. + * @param SDIO_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode. + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_CMDACT: Command transfer in progress + * @arg SDIO_FLAG_TXACT: Data transmit in progress + * @arg SDIO_FLAG_RXACT: Data receive in progress + * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full + * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval The new state of SDIO_FLAG (SET or RESET). + */ +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_FLAG(SDIO_FLAG)); + + if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIO's pending flags. + * @param SDIO_FLAG: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDIO_FLAG_CTIMEOUT: Command response timeout + * @arg SDIO_FLAG_DTIMEOUT: Data timeout + * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) + * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) + * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide + * bus mode + * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received + * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearFlag(uint32_t SDIO_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); + + SDIO->ICR = SDIO_FLAG; +} + +/** + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * @param SDIO_IT: specifies the SDIO interrupt source to check. + * This parameter can be one of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt + * @arg SDIO_IT_TXACT: Data transmit in progress interrupt + * @arg SDIO_IT_RXACT: Data receive in progress interrupt + * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt + * @retval The new state of SDIO_IT (SET or RESET). + */ +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_SDIO_GET_IT(SDIO_IT)); + if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the SDIOs interrupt pending bits. + * @param SDIO_IT: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt + * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt + * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide + * bus mode interrupt + * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt + * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 + * @retval None + */ +void SDIO_ClearITPendingBit(uint32_t SDIO_IT) +{ + /* Check the parameters */ + assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); + + SDIO->ICR = SDIO_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_spi.c b/example/libs_stm/src/stm32f10x/stm32f10x_spi.c new file mode 100644 index 000000000..b1ff419d9 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_spi.c @@ -0,0 +1,907 @@ +/** + ****************************************************************************** + * @file stm32f10x_spi.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the SPI firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_spi.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup SPI + * @brief SPI driver modules + * @{ + */ + +/** @defgroup SPI_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + + +/** @defgroup SPI_Private_Defines + * @{ + */ + +/* SPI SPE mask */ +#define CR1_SPE_Set ((uint16_t)0x0040) +#define CR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CR1_CRCEN_Set ((uint16_t)0x2000) +#define CR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CR2_SSOE_Set ((uint16_t)0x0004) +#define CR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/** + * @} + */ + +/** @defgroup SPI_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup SPI_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_I2S_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else + { + if (SPIx == SPI3) + { + /* Enable SPI3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + } +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * @retval None + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + +/*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/salve mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + + /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ + SPIx->I2SCFGR &= SPI_Mode_Select; + +/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral + * (configured in I2S mode). + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * @note + * The function calculates the optimal prescaler needed to obtain the most + * accurate audio frequency (depending on the I2S clock source, the PLL values + * and the product configuration). But in case the prescaler value is greater + * than 511, the default value (0x02) will be configured instead. * + * @retval None + */ +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + /* Check the I2S parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); + assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); + assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); + assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); + +/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + + /* Get the I2SCFGR register value */ + tmpreg = SPIx->I2SCFGR; + + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + /* If the requested audio frequency is not the default, compute the prescaler */ + else + { + /* Check the frame length (For the Prescaler computing) */ + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else + { + /* Packet length is 32 bits */ + packetlength = 2; + } + + /* Get the I2S clock source mask depending on the peripheral number */ + if(((uint32_t)SPIx) == SPI2_BASE) + { + /* The mask is relative to I2S2 */ + tmp = I2S2_CLOCK_SRC; + } + else + { + /* The mask is relative to I2S3 */ + tmp = I2S3_CLOCK_SRC; + } + + /* Check the I2S clock source configuration depending on the Device: + Only Connectivity line devices have the PLL3 VCO clock */ +#ifdef STM32F10X_CL + if((RCC->CFGR2 & tmp) != 0) + { + /* Get the configuration bits of RCC PLL3 multiplier */ + tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12); + + /* Get the value of the PLL3 multiplier */ + if((tmp > 5) && (tmp < 15)) + { + /* Multplier is between 8 and 14 (value 15 is forbidden) */ + tmp += 2; + } + else + { + if (tmp == 15) + { + /* Multiplier is 20 */ + tmp = 20; + } + } + /* Get the PREDIV2 value */ + sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1); + + /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */ + sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); + } + else + { + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; + } +#else /* STM32F10X_HD */ + /* I2S Clock source is System clock: Get System Clock frequency */ + RCC_GetClocksFreq(&RCC_Clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = RCC_Clocks.SYSCLK_Frequency; +#endif /* STM32F10X_CL */ + + /* Compute the Real divider depending on the MCLK output state with a flaoting point */ + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + /* MCLK output is enabled */ + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + /* MCLK output is disabled */ + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + /* Remove the flaoting point */ + tmp = tmp / 10; + + /* Check the parity of the divider */ + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + + /* Compute the i2sdiv prescaler */ + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (uint16_t) (i2sodd << 8); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + /* Set the default values */ + i2sdiv = 2; + i2sodd = 0; + } + + /* Write to SPIx I2SPR register the computed value */ + SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + + /* Configure the I2S with the SPI_InitStruct values */ + tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + + /* Write to SPIx I2SCFGR */ + SPIx->I2SCFGR = tmpreg; +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ +/*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + /* initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ +/*--------------- Reset I2S init structure parameters values -----------------*/ + /* Initialize the I2S_Mode member */ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + + /* Initialize the I2S_DataFormat member */ + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + + /* Initialize the I2S_MCLKOutput member */ + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + + /* Initialize the I2S_AudioFreq member */ + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + + /* Initialize the I2S_CPOL member */ + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= CR1_SPE_Set; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= CR1_SPE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_23_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; + } + else + { + /* Disable the selected SPI peripheral (in I2S mode) */ + SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; + } +} + +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask + * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask + * @arg SPI_I2S_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified SPI/I2S interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0 ; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI/I2S interrupt */ + SPIx->CR2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request + * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected SPI/I2S DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); + if (NewState != DISABLE) + { + /* Enable the selected SPI/I2S DMA requests */ + SPIx->CR2 |= SPI_I2S_DMAReq; + } + else + { + /* Disable the selected SPI/I2S DMA requests */ + SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param Data : Data to be transmitted. + * @retval None + */ +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Write in the DR register the data to be sent */ + SPIx->DR = Data; +} + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @retval The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the data in the DR register */ + return SPIx->DR; +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally + * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally + * @retval None + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= CR2_SSOE_Set; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= CR2_SSOE_Reset; + } +} + +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_DataSize: specifies the SPI data size. + * This parameter can be one of the following values: + * @arg SPI_DataSize_16b: Set data frame format to 16bit + * @arg SPI_DataSize_8b: Set data frame format to 8bit + * @retval None + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATASIZE(SPI_DataSize)); + /* Clear DFF bit */ + SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; + /* Set new DFF bit value */ + SPIx->CR1 |= SPI_DataSize; +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= CR1_CRCNext_Set; +} + +/** + * @brief Enables or disables the CRC value calculation of the transfered bytes. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= CR1_CRCEN_Set; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= CR1_CRCEN_Reset; + } +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_CRC: specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_Tx: Selects Tx CRC register + * @arg SPI_CRC_Rx: Selects Rx CRC register + * @retval The selected CRC register value.. + */ +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @retval The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/** + * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. + * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. + * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. + * This parameter can be one of the following values: + * @arg SPI_Direction_Tx: Selects Tx transmission direction + * @arg SPI_Direction_Rx: Selects Rx receive direction + * @retval None + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/** + * @brief Checks whether the specified SPI/I2S flag is set or not. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. + * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. + * @arg SPI_I2S_FLAG_BSY: Busy flag. + * @arg SPI_I2S_FLAG_OVR: Overrun flag. + * @arg SPI_FLAG_MODF: Mode Fault flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * @arg I2S_FLAG_UDR: Underrun Error flag. + * @arg I2S_FLAG_CHSIDE: Channel Side flag. + * @retval The new state of SPI_I2S_FLAG (SET or RESET). + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); + /* Check the status of the specified SPI/I2S flag */ + if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + /* SPI_I2S_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_FLAG: specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @note + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_SR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). + * @retval None + */ +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (uint16_t)~SPI_I2S_FLAG; +} + +/** + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * - 2 or 3 in I2S mode + * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. + * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. + * @arg SPI_I2S_IT_OVR: Overrun interrupt. + * @arg SPI_IT_MODF: Mode Fault interrupt. + * @arg SPI_IT_CRCERR: CRC Error interrupt. + * @arg I2S_IT_UDR: Underrun Error interrupt. + * @retval The new state of SPI_I2S_IT (SET or RESET). + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); + + /* Get the SPI/I2S IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Get the SPI/I2S IT mask */ + itmask = SPI_I2S_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_I2S_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI/I2S interrupt */ + if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_I2S_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_I2S_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_I2S_IT status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * @param SPIx: where x can be + * - 1, 2 or 3 in SPI mode + * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. + * This function clears only CRCERR intetrrupt pending bit. + * @note + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_SR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable + * the SPI). + * @retval None + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); + + /* Get the SPI IT index */ + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + + /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ + SPIx->SR = (uint16_t)~itpos; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_tim.c b/example/libs_stm/src/stm32f10x/stm32f10x_tim.c new file mode 100644 index 000000000..c626dca35 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_tim.c @@ -0,0 +1,2834 @@ +/** + ****************************************************************************** + * @file stm32f10x_tim.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the TIM firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_tim.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup TIM + * @brief TIM driver modules + * @{ + */ + +/** @defgroup TIM_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Defines + * @{ + */ + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCR_ETR_Mask ((uint16_t)0x00FF) +#define CCMR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +/** + * @} + */ + +/** @defgroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_FunctionPrototypes + * @{ + */ + +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +/** + * @} + */ + +/** @defgroup TIM_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval None + */ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + if (TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } + else if (TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if (TIMx == TIM9) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); + } + else if (TIMx == TIM10) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); + } + else if (TIMx == TIM11) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); + } + else if (TIMx == TIM12) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); + } + else if (TIMx == TIM13) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); + } + else if (TIMx == TIM14) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); + } + else if (TIMx == TIM15) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); + } + else if (TIMx == TIM16) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); + } + else + { + if (TIMx == TIM17) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); + } + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef + * structure that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + tmpcr1 = TIMx->CR1; + + if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| + (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if((TIMx != TIM6) && (TIMx != TIM7)) + { + /* Set the clock division */ + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler and the Repetition counter + values immediately */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| + (TIMx == TIM16)|| (TIMx == TIM17)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); + + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); + + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + /* Reset the Output N State */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); + + /* Set the Output N State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + /* Disable the Channel 2: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + /* Reset the Ouput Compare IDLE State */ + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); + /* Set the Output Idle state */ + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM peripheral. + * @retval None + */ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * @param TIMx: where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval None + */ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef + * structure which will be initialized. + * @retval None + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which + * will be initialized. + * @retval None + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. + * @param NewState: new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= TIM_CR1_CEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); + } +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral. + * @param NewState: new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= TIM_BDTR_MOE; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); + } +} + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. + * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can only generate an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @param NewState: new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint16_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_EventSource: specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EventSource_Update: Timer update Event source + * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM: Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break: Timer Break event source + * @note + * - TIM6 and TIM7 can only generate an update event. + * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. + * @retval None + */ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** + * @brief Configures the TIMxs DMA interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select + * the TIM peripheral. + * @param TIM_DMABase: DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, + * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, + * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, + * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, + * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, + * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, + * TIM_DMABase_DCR. + * @param TIM_DMABurstLength: DMA Burst length. + * This parameter can be one value between: + * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes. + * @retval None + */ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMxs DMA Requests. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 + * to select the TIM peripheral. + * @param TIM_DMASource: specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_Update: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_Trigger: TIM Trigger DMA source + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST9_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint16_t)~TIM_DMASource; + } +} + +/** + * @brief Configures the TIMx interrnal Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 + * to select the TIM peripheral. + * @retval None + */ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ITRSource: Trigger source. + * This parameter can be one of the following values: + * @param TIM_TS_ITR0: Internal Trigger 0 + * @param TIM_TS_ITR1: Internal Trigger 1 + * @param TIM_TS_ITR2: Internal Trigger 2 + * @param TIM_TS_ITR3: Internal Trigger 3 + * @retval None + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_TIxExternalCLKSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector + * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 + * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 + * @param TIM_ICPolarity: specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param ICFilter : specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the SMS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + tmpsmcr |= TIM_TS_ETRF; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + /* Enable the External clock mode2 */ + TIMx->SMCR |= TIM_SMCR_ECE; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + tmpsmcr = TIMx->SMCR; + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_Mask; + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Prescaler: specifies the Prescaler Register value + * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. + * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. + * @retval None + */ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_CounterMode: specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CounterMode_Up: TIM Up Counting Mode + * @arg TIM_CounterMode_Down: TIM Down Counting Mode + * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 + * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 + * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 + * @retval None + */ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + tmpcr1 = TIMx->CR1; + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_InputTriggerSource: The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity: specifies the IC1 Polarity + * This parmeter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @param TIM_IC2Polarity: specifies the IC2 Polarity + * This parmeter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising: IC Rising edge. + * @retval None + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); + tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC1REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. + * @retval None + */ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC2REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. + * @retval None + */ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC3REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. + * @retval None + */ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC1M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active: Force active level on OC4REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. + * @retval None + */ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC2M Bits */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param NewState: new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= TIM_CR1_ARPE; + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); + } +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral + * @param NewState: new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= TIM_CR2_CCUS; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select + * the TIM peripheral. + * @param NewState: new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= TIM_CR2_CCDS; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); + } +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 + * to select the TIMx peripheral + * @param NewState: new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= TIM_CR2_CCPC; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); + } +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select + * the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable: TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr1 = TIMx->CCMR1; + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable: TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + tmpccmr2 = TIMx->CCMR2; + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC1 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); + tmpccer |= TIM_OCPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC1N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); + tmpccer |= TIM_OCNPolarity; + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC2 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC2N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC3 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC3N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST1_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC4 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + tmpccer = TIMx->CCER; + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parmeter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. + * @retval None + */ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCX(TIM_CCx)); + + tmp = CCER_CCE_Set << TIM_Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t)~ tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parmeter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. + * @retval None + */ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + tmp = CCER_CCNE_Set << TIM_Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint16_t) ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/** + * @brief Selects the TIM Ouput Compare Mode. + * @note This function disables the selected channel before changing the Ouput + * Compare Mode. + * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parmeter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @param TIM_OCMode: specifies the TIM Output Compare Mode. + * This paramter can be one of the following values: + * @arg TIM_OCMode_Timing + * @arg TIM_OCMode_Active + * @arg TIM_OCMode_Toggle + * @arg TIM_OCMode_PWM1 + * @arg TIM_OCMode_PWM2 + * @arg TIM_ForcedAction_Active + * @arg TIM_ForcedAction_InActive + * @retval None + */ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_OCM(TIM_OCMode)); + + tmp = (uint32_t) TIMx; + tmp += CCMR_Offset; + + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint16_t) ~tmp1; + + if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel>>1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param NewState: new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= TIM_CR1_UDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_UpdateSource: specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. + * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. + * @retval None + */ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= TIM_CR1_URS; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); + } +} + +/** + * @brief Enables or disables the TIMxs Hall sensor interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param NewState: new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= TIM_CR2_TI1S; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); + } +} + +/** + * @brief Selects the TIMxs One Pulse Mode. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_OPMode: specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMode_Single + * @arg TIM_OPMode_Repetitive + * @retval None + */ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + /* Reset the OPM Bit */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_TRGOSource: specifies the Trigger Output source. + * This paramter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs (TRGO). + * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). + * + * @retval None + */ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST7_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + /* Reset the MMS Bits */ + TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_SlaveMode: specifies the Timer Slave Mode. + * This paramter can be one of the following values: + * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes + * the counter and triggers an update of the registers. + * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. + * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. + * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. + * @retval None + */ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + /* Reset the SMS Bits */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. + * This paramter can be one of the following values: + * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer + * and its slaves (through TRGO). + * @arg TIM_MasterSlaveMode_Disable: No action + * @retval None + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + /* Reset the MSM Bit */ + TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Counter: specifies the Counter register new value. + * @retval None + */ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param Autoreload: specifies the Autoreload register new value. + * @retval None + */ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param Compare1: specifies the Capture Compare1 register new value. + * @retval None + */ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param Compare2: specifies the Capture Compare2 register new value. + * @retval None + */ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3: specifies the Capture Compare3 register new value. + * @retval None + */ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4: specifies the Capture Compare4 register new value. + * @retval None + */ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select + * the TIM peripheral. + * @param TIM_CKD: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CKD_DIV1: TDTS = Tck_tim + * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim + * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim + * @retval None + */ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + /* Reset the CKD Bits */ + TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @retval Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST8_PERIPH(TIMx)); + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @retval Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @retval Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, + * TIM_FLAG_CC2 or TIM_FLAG_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_FLAG: specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_Update: TIM update Flag + * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag + * @arg TIM_FLAG_COM: TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break: TIM Break Flag + * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag + * @note + * - TIM6 and TIM7 can have only one update flag. + * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, + * TIM_FLAG_CC2 or TIM_FLAG_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. + * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval None + */ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR = (uint16_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_IT: specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_Update: TIM update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval The new state of the TIM_IT(SET or RESET). + */ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. + * @param TIM_IT: specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update: TIM1 update Interrupt source + * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM: TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break: TIM Break Interrupt source + * @note + * - TIM6 and TIM7 can generate only an update interrupt. + * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2 or TIM_IT_Trigger. + * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. + * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. + * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. + * @retval None + */ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + /* Clear the IT pending Bit */ + TIMx->SR = (uint16_t)~TIM_IT; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + /* Select the Input and set the filter */ + tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity : The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + /* Select the Input and set the filter */ + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_usart.c b/example/libs_stm/src/stm32f10x/stm32f10x_usart.c new file mode 100644 index 000000000..fa0733e89 --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_usart.c @@ -0,0 +1,1054 @@ +/** + ****************************************************************************** + * @file stm32f10x_usart.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the USART firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_usart.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup USART + * @brief USART driver modules + * @{ + */ + +/** @defgroup USART_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Defines + * @{ + */ + +#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */ +#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */ + +#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ + +#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ +#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ +#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */ +#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */ +#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */ + +#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ +#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ + +#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ +#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */ +#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */ + +#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */ +#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ + +#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ +#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ + +#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ +#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ + +#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ +#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */ + +#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ +#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ +#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ +#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */ + +/* USART OverSampling-8 Mask */ +#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */ +#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */ + +/* USART One Bit Sampling Mask */ +#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */ +#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */ + +/** + * @} + */ + +/** @defgroup USART_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the USARTx peripheral registers to their default reset values. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5. + * @retval None + */ +void USART_DeInit(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if (USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if (USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else + { + if (USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + } +} + +/** + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct . + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified USART peripheral. + * @retval None + */ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + /* The hardware flow control is available only for USART1, USART2 and USART3 */ + if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear STOP[13:12] bits */ + tmpreg &= CR2_STOP_CLEAR_Mask; + /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ + /* Set STOP[13:12] bits according to USART_StopBits value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; + +/*---------------------------- USART CR1 Configuration -----------------------*/ + tmpreg = USARTx->CR1; + /* Clear M, PCE, PS, TE and RE bits */ + tmpreg &= CR1_CLEAR_Mask; + /* Configure the USART Word Length, Parity and mode ----------------------- */ + /* Set the M bits according to USART_WordLength value */ + /* Set PCE and PS bits according to USART_Parity value */ + /* Set TE and RE bits according to USART_Mode value */ + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + /* Write to USART CR1 */ + USARTx->CR1 = (uint16_t)tmpreg; + +/*---------------------------- USART CR3 Configuration -----------------------*/ + tmpreg = USARTx->CR3; + /* Clear CTSE and RTSE bits */ + tmpreg &= CR3_CLEAR_Mask; + /* Configure the USART HFC -------------------------------------------------*/ + /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + /* Write to USART CR3 */ + USARTx->CR3 = (uint16_t)tmpreg; + +/*---------------------------- USART BRR Configuration -----------------------*/ + /* Configure the USART Baud Rate -------------------------------------------*/ + RCC_GetClocksFreq(&RCC_ClocksStatus); + if (usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + /* Determine the integer part */ + if ((USARTx->CR1 & CR1_OVER8_Set) != 0) + { + /* Integer part computing in case Oversampling mode is 8 Samples */ + integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + /* Integer part computing in case Oversampling mode is 16 Samples */ + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + } + tmpreg = (integerdivider / 100) << 4; + + /* Determine the fractional part */ + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + + /* Implement the fractional part in the register */ + if ((USARTx->CR1 & CR1_OVER8_Set) != 0) + { + tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); + } + else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ + { + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + } + + /* Write to USART BRR */ + USARTx->BRR = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No ; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/** + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); + assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); + assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); + assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); + +/*---------------------------- USART CR2 Configuration -----------------------*/ + tmpreg = USARTx->CR2; + /* Clear CLKEN, CPOL, CPHA and LBCL bits */ + tmpreg &= CR2_CLOCK_CLEAR_Mask; + /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ + /* Set CLKEN bit according to USART_Clock value */ + /* Set CPOL bit according to USART_CPOL value */ + /* Set CPHA bit according to USART_CPHA value */ + /* Set LBCL bit according to USART_LastBit value */ + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + /* Write to USART CR2 */ + USARTx->CR2 = (uint16_t)tmpreg; +} + +/** + * @brief Fills each USART_ClockInitStruct member with its default value. + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * @retval None + */ +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) +{ + /* USART_ClockInitStruct members default value */ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the UE bit in the CR1 register */ + USARTx->CR1 |= CR1_UE_Set; + } + else + { + /* Disable the selected USART by clearing the UE bit in the CR1 register */ + USARTx->CR1 &= CR1_UE_Reset; + } +} + +/** + * @brief Enables or disables the specified USART interrupts. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) + * @param NewState: new state of the specified USARTx interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CONFIG_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + usartxbase = (uint32_t)USARTx; + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + + /* Get the interrupt position */ + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + usartxbase += 0x0C; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + usartxbase += 0x10; + } + else /* The IT is in CR3 register */ + { + usartxbase += 0x14; + } + if (NewState != DISABLE) + { + *(__IO uint32_t*)usartxbase |= itmask; + } + else + { + *(__IO uint32_t*)usartxbase &= ~itmask; + } +} + +/** + * @brief Enables or disables the USARTs DMA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3 or UART4. + * @param USART_DMAReq: specifies the DMA request. + * This parameter can be any combination of the following values: + * @arg USART_DMAReq_Tx: USART DMA transmit request + * @arg USART_DMAReq_Rx: USART DMA receive request + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @note The DMA mode is not available for UART5. + * @retval None + */ +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_1234_PERIPH(USARTx)); + assert_param(IS_USART_DMAREQ(USART_DMAReq)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the DMA transfer for selected requests by setting the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 |= USART_DMAReq; + } + else + { + /* Disable the DMA transfer for selected requests by clearing the DMAT and/or + DMAR bits in the USART CR3 register */ + USARTx->CR3 &= (uint16_t)~USART_DMAReq; + } +} + +/** + * @brief Sets the address of the USART node. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Address: Indicates the address of the USART node. + * @retval None + */ +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ADDRESS(USART_Address)); + + /* Clear the USART address */ + USARTx->CR2 &= CR2_Address_Mask; + /* Set the USART address node */ + USARTx->CR2 |= USART_Address; +} + +/** + * @brief Selects the USART WakeUp method. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_WakeUp: specifies the USART wakeup method. + * This parameter can be one of the following values: + * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection + * @arg USART_WakeUp_AddressMark: WakeUp by an address mark + * @retval None + */ +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_WAKEUP(USART_WakeUp)); + + USARTx->CR1 &= CR1_WAKE_Mask; + USARTx->CR1 |= USART_WakeUp; +} + +/** + * @brief Determines if the USART is in mute mode or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART mute mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ + USARTx->CR1 |= CR1_RWU_Set; + } + else + { + /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ + USARTx->CR1 &= CR1_RWU_Reset; + } +} + +/** + * @brief Sets the USART LIN Break detection length. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_LINBreakDetectLength: specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg USART_LINBreakDetectLength_10b: 10-bit break detection + * @arg USART_LINBreakDetectLength_11b: 11-bit break detection + * @retval None + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); + + USARTx->CR2 &= CR2_LBDL_Mask; + USARTx->CR2 |= USART_LINBreakDetectLength; +} + +/** + * @brief Enables or disables the USARTs LIN mode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART LIN mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + USARTx->CR2 |= CR2_LINEN_Set; + } + else + { + /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ + USARTx->CR2 &= CR2_LINEN_Reset; + } +} + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param Data: the data to transmit. + * @retval None + */ +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->DR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Receive Data */ + return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); +} + +/** + * @brief Transmits break characters. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @retval None + */ +void USART_SendBreak(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Send break characters */ + USARTx->CR1 |= CR1_SBK_Set; +} + +/** + * @brief Sets the specified USART guard time. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param USART_GuardTime: specifies the guard time. + * @note The guard time bits are not available for UART4 and UART5. + * @retval None + */ +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + + /* Clear the USART Guard time */ + USARTx->GTPR &= GTPR_LSB_Mask; + /* Set the USART guard time */ + USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/** + * @brief Sets the system clock prescaler. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_Prescaler: specifies the prescaler clock. + * @note The function is used for IrDA mode with UART4 and UART5. + * @retval None + */ +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Clear the USART prescaler */ + USARTx->GTPR &= GTPR_MSB_Mask; + /* Set the USART prescaler */ + USARTx->GTPR |= USART_Prescaler; +} + +/** + * @brief Enables or disables the USARTs Smart Card mode. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param NewState: new state of the Smart Card mode. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the SC mode by setting the SCEN bit in the CR3 register */ + USARTx->CR3 |= CR3_SCEN_Set; + } + else + { + /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ + USARTx->CR3 &= CR3_SCEN_Reset; + } +} + +/** + * @brief Enables or disables NACK transmission. + * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. + * @param NewState: new state of the NACK transmission. + * This parameter can be: ENABLE or DISABLE. + * @note The Smart Card mode is not available for UART4 and UART5. + * @retval None + */ +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_123_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ + USARTx->CR3 |= CR3_NACK_Set; + } + else + { + /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ + USARTx->CR3 &= CR3_NACK_Reset; + } +} + +/** + * @brief Enables or disables the USARTs Half Duplex communication. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART Communication. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + USARTx->CR3 |= CR3_HDSEL_Set; + } + else + { + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ + USARTx->CR3 &= CR3_HDSEL_Reset; + } +} + + +/** + * @brief Enables or disables the USART's 8x oversampling mode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART one bit sampling methode. + * This parameter can be: ENABLE or DISABLE. + * @note + * This function has to be called before calling USART_Init() + * function in order to have correct baudrate Divider value. + * @retval None + */ +void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ + USARTx->CR1 |= CR1_OVER8_Set; + } + else + { + /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ + USARTx->CR1 &= CR1_OVER8_Reset; + } +} + +/** + * @brief Enables or disables the USART's one bit sampling methode. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the USART one bit sampling methode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ + USARTx->CR3 |= CR3_ONEBITE_Set; + } + else + { + /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */ + USARTx->CR3 &= CR3_ONEBITE_Reset; + } +} + +/** + * @brief Configures the USARTs IrDA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IrDAMode: specifies the IrDA mode. + * This parameter can be one of the following values: + * @arg USART_IrDAMode_LowPower + * @arg USART_IrDAMode_Normal + * @retval None + */ +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); + + USARTx->CR3 &= CR3_IRLP_Mask; + USARTx->CR3 |= USART_IrDAMode; +} + +/** + * @brief Enables or disables the USARTs IrDA interface. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param NewState: new state of the IrDA mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ + USARTx->CR3 |= CR3_IREN_Set; + } + else + { + /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ + USARTx->CR3 &= CR3_IREN_Reset; + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) + * @arg USART_FLAG_LBD: LIN Break detection flag + * @arg USART_FLAG_TXE: Transmit data register empty flag + * @arg USART_FLAG_TC: Transmission Complete flag + * @arg USART_FLAG_RXNE: Receive data register not empty flag + * @arg USART_FLAG_IDLE: Idle Line detection flag + * @arg USART_FLAG_ORE: OverRun Error flag + * @arg USART_FLAG_NE: Noise Error flag + * @arg USART_FLAG_FE: Framing Error flag + * @arg USART_FLAG_PE: Parity Error flag + * @retval The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4 and UART5 */ + if (USART_FLAG == USART_FLAG_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). + * @arg USART_FLAG_LBD: LIN Break detection flag. + * @arg USART_FLAG_TC: Transmission Complete flag. + * @arg USART_FLAG_RXNE: Receive data register not empty flag. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_SR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DR register + * (USART_SendData()). + * @retval None + */ +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + /* The CTS flag is not available for UART4 and UART5 */ + if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + USARTx->SR = (uint16_t)~USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has occurred or not. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TXE: Tansmit Data Register empty interrupt + * @arg USART_IT_TC: Transmission complete interrupt + * @arg USART_IT_RXNE: Receive Data register not empty interrupt + * @arg USART_IT_IDLE: Idle line detection interrupt + * @arg USART_IT_ORE: OverRun Error interrupt + * @arg USART_IT_NE: Noise Error interrupt + * @arg USART_IT_FE: Framing Error interrupt + * @arg USART_IT_PE: Parity Error interrupt + * @retval The new state of USART_IT (SET or RESET). + */ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_IT(USART_IT)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + /* Get the USART register index */ + usartreg = (((uint8_t)USART_IT) >> 0x05); + /* Get the interrupt position */ + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if (usartreg == 0x01) /* The IT is in CR1 register */ + { + itmask &= USARTx->CR1; + } + else if (usartreg == 0x02) /* The IT is in CR2 register */ + { + itmask &= USARTx->CR2; + } + else /* The IT is in CR3 register */ + { + itmask &= USARTx->CR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->SR; + if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Clears the USARTxs interrupt pending bits. + * @param USARTx: Select the USART or the UART peripheral. + * This parameter can be one of the following values: + * USART1, USART2, USART3, UART4 or UART5. + * @param USART_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) + * @arg USART_IT_LBD: LIN Break detection interrupt + * @arg USART_IT_TC: Transmission complete interrupt. + * @arg USART_IT_RXNE: Receive Data register not empty interrupt. + * + * @note + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_SR register + * (USART_GetITStatus()) followed by a read operation to USART_DR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_SR register (USART_GetITStatus()) followed by a write + * operation to USART_DR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DR register + * (USART_SendData()). + * @retval None + */ +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + /* The CTS interrupt is not available for UART4 and UART5 */ + if (USART_IT == USART_IT_CTS) + { + assert_param(IS_USART_123_PERIPH(USARTx)); + } + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->SR = (uint16_t)~itmask; +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_wwdg.c b/example/libs_stm/src/stm32f10x/stm32f10x_wwdg.c new file mode 100644 index 000000000..cd4978bbe --- /dev/null +++ b/example/libs_stm/src/stm32f10x/stm32f10x_wwdg.c @@ -0,0 +1,223 @@ +/** + ****************************************************************************** + * @file stm32f10x_wwdg.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief This file provides all the WWDG firmware functions. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_wwdg.h" +#include "stm32f10x_rcc.h" + +/** @addtogroup STM32F10x_StdPeriph_Driver + * @{ + */ + +/** @defgroup WWDG + * @brief WWDG driver modules + * @{ + */ + +/** @defgroup WWDG_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Defines + * @{ + */ + +/* ----------- WWDG registers bit address in the alias region ----------- */ +#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) + +/* Alias word address of EWI bit */ +#define CFR_OFFSET (WWDG_OFFSET + 0x04) +#define EWI_BitNumber 0x09 +#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) + +/* --------------------- WWDG registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_WDGA_Set ((uint32_t)0x00000080) + +/* CFR register bit mask */ +#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/** + * @} + */ + +/** @defgroup WWDG_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Variables + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup WWDG_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler: specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 + * @retval None + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_Mask; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + * @retval None + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpreg = WWDG->CFR & CFR_W_Mask; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & (uint32_t) BIT_Mask; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + * @param None + * @retval None + */ +void WWDG_EnableIT(void) +{ + *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + * @retval None + */ +void WWDG_SetCounter(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_Mask; +} + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F. + * @retval None + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + WWDG->CR = CR_WDGA_Set | Counter; +} + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @param None + * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->SR); +} + +/** + * @brief Clears Early Wakeup interrupt flag. + * @param None + * @retval None + */ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ From a7d14c7d4e76f19901bb8dbd99bfafe9a69b5490 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 8 Nov 2011 01:13:21 +0000 Subject: [PATCH 0049/1435] Adding original source of vl factory demo It compiles, but I've got bugs preventing me from running this yet :( --- example/32vl_factory_demo/Makefile | 53 + example/32vl_factory_demo/README | 5 + example/32vl_factory_demo/main.c | 234 ++++ example/32vl_factory_demo/stm32f10x_conf.h | 76 ++ example/32vl_factory_demo/stm32f10x_it.c | 160 +++ example/32vl_factory_demo/stm32f10x_it.h | 46 + example/32vl_factory_demo/system_stm32f10x.c | 1019 ++++++++++++++++++ 7 files changed, 1593 insertions(+) create mode 100644 example/32vl_factory_demo/Makefile create mode 100644 example/32vl_factory_demo/README create mode 100644 example/32vl_factory_demo/main.c create mode 100644 example/32vl_factory_demo/stm32f10x_conf.h create mode 100644 example/32vl_factory_demo/stm32f10x_it.c create mode 100644 example/32vl_factory_demo/stm32f10x_it.h create mode 100644 example/32vl_factory_demo/system_stm32f10x.c diff --git a/example/32vl_factory_demo/Makefile b/example/32vl_factory_demo/Makefile new file mode 100644 index 000000000..81cdd56ba --- /dev/null +++ b/example/32vl_factory_demo/Makefile @@ -0,0 +1,53 @@ +# build an elf from the an3268 demonstration code +APP=32vl_factory_demo + +CC=arm-none-eabi-gcc +OBJCOPY=arm-none-eabi-objcopy + +CFLAGS=-O2 -mlittle-endian -mthumb +CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc +ifeq ($(DEBUG),1) + CFLAGS+=-g +endif + +# to run from SRAM +CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000 + +# to write to flash then run +# CFLAGS+=-Wl,-Ttext,0x08000000 -Wl,-e,0x08000000 + +PLATFORM=stm32f10x +BOARD_SUPPORT=../board_support/discovery_32vl +LIBS_STM_PATH=../libs_stm + +CFLAGS+=-I. +CFLAGS+=-I$(LIBS_STM_PATH)/inc/base +CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM) +CFLAGS+=-I$(BOARD_SUPPORT) + +LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_f10x + + +SRCS=$(wildcard *.c) +SRCS+=$(wildcard $(BOARD_SUPPORT)/*.c) + +OBJS=$(SRCS:.c=.o) + +all: $(APP).elf + +%.bin: %.elf + $(OBJCOPY) -O binary $^ $@ + +$(APP).elf: $(OBJS) + $(CC) $(CFLAGS) -o $@ $(OBJS) $(LDFLAGS) + +%.o: %.c + $(CC) $(CFLAGS) -c -o $@ $^ + +clean: + rm -rf $(OBJS) + rm -rf $(APP).* + +.PHONY: all clean diff --git a/example/32vl_factory_demo/README b/example/32vl_factory_demo/README new file mode 100644 index 000000000..28c83952d --- /dev/null +++ b/example/32vl_factory_demo/README @@ -0,0 +1,5 @@ +This source is copied from AN3268, the STM demo code for the VL discovery board. + +It was modified to add includes and things where needed, but nothing else was touched. + +Eventually, this should be usable to restore a board to virgin state. (but not yet) diff --git a/example/32vl_factory_demo/main.c b/example/32vl_factory_demo/main.c new file mode 100644 index 000000000..0043b650e --- /dev/null +++ b/example/32vl_factory_demo/main.c @@ -0,0 +1,234 @@ +/** + ****************************************************************************** + * @file Demo/src/main.c + * @author MCD Application Team + * @version V1.0.0 + * @date 09/13/2010 + * @brief Main program body + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" +#include "stm32f10x_conf.h" +#include "STM32vldiscovery.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define LSE_FAIL_FLAG 0x80 +#define LSE_PASS_FLAG 0x100 +/* Private macro -------------------------------------------------------------*/ +/* Private consts ------------------------------------------------------------*/ + +/* Private variables ---------------------------------------------------------*/ +u32 LSE_Delay = 0; +u32 count = 0; +u32 BlinkSpeed = 0; +u32 KeyState = 0; +static __IO uint32_t TimingDelay; +/* Private function prototypes -----------------------------------------------*/ +void Delay(uint32_t nTime); +void TimingDelay_Decrement(void); + +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program. + * @param None + * @retval None + */ + +int main(void) +{ + /* Enable GPIOx Clock */ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); + + /* Initialise LEDs LD3&LD4, both off */ + STM32vldiscovery_LEDInit(LED3); + STM32vldiscovery_LEDInit(LED4); + + STM32vldiscovery_LEDOff(LED3); + STM32vldiscovery_LEDOff(LED4); + + /* Initialise USER Button */ + STM32vldiscovery_PBInit(BUTTON_USER, BUTTON_MODE_GPIO); + + /* Setup SysTick Timer for 1 msec interrupts */ + if (SysTick_Config(SystemCoreClock / 1000)) + { + /* Capture error */ + while (1); + } + + /* Enable access to the backup register => LSE can be enabled */ + PWR_BackupAccessCmd(ENABLE); + + /* Enable LSE (Low Speed External Oscillation) */ + RCC_LSEConfig(RCC_LSE_ON); + + /* Check the LSE Status */ + while(1) + { + if(LSE_Delay < LSE_FAIL_FLAG) + { + /* check whether LSE is ready, with 4 seconds timeout */ + Delay (500); + LSE_Delay += 0x10; + if(RCC_GetFlagStatus(RCC_FLAG_LSERDY) != RESET) + { + /* Set flag: LSE PASS */ + LSE_Delay |= LSE_PASS_FLAG; + /* Turn Off Led4 */ + STM32vldiscovery_LEDOff(LED4); + /* Disable LSE */ + RCC_LSEConfig(RCC_LSE_OFF); + break; + } + } + + /* LSE_FAIL_FLAG = 0x80 */ + else if(LSE_Delay >= LSE_FAIL_FLAG) + { + if(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) + { + /* Set flag: LSE FAIL */ + LSE_Delay |= LSE_FAIL_FLAG; + /* Turn On Led4 */ + STM32vldiscovery_LEDOn(LED4); + } + /* Disable LSE */ + RCC_LSEConfig(RCC_LSE_OFF); + break; + } + } + + /* main while */ + while(1) + { + if(0 == STM32vldiscovery_PBGetState(BUTTON_USER)) + { + if(KeyState == 1) + { + if(0 == STM32vldiscovery_PBGetState(BUTTON_USER)) + { + /* USER Button released */ + KeyState = 0; + /* Turn Off LED4 */ + STM32vldiscovery_LEDOff(LED4); + } + } + } + else if(STM32vldiscovery_PBGetState(BUTTON_USER)) + { + if(KeyState == 0) + { + if(STM32vldiscovery_PBGetState(BUTTON_USER)) + { + /* USER Button released */ + KeyState = 1; + /* Turn ON LED4 */ + STM32vldiscovery_LEDOn(LED4); + Delay(1000); + /* Turn OFF LED4 */ + STM32vldiscovery_LEDOff(LED4); + /* BlinkSpeed: 0 -> 1 -> 2, then re-cycle */ + BlinkSpeed ++ ; + } + } + } + count++; + Delay(100); + /* BlinkSpeed: 0 */ + if(BlinkSpeed == 0) + { + if(4 == (count % 8)) + STM32vldiscovery_LEDOn(LED3); + if(0 == (count % 8)) + STM32vldiscovery_LEDOff(LED3); + } + /* BlinkSpeed: 1 */ + if(BlinkSpeed == 1) + { + if(2 == (count % 4)) + STM32vldiscovery_LEDOn(LED3); + if(0 == (count % 4)) + STM32vldiscovery_LEDOff(LED3); + } + /* BlinkSpeed: 2 */ + if(BlinkSpeed == 2) + { + if(0 == (count % 2)) + STM32vldiscovery_LEDOn(LED3); + else + STM32vldiscovery_LEDOff(LED3); + } + /* BlinkSpeed: 3 */ + else if(BlinkSpeed == 3) + BlinkSpeed = 0; + } +} + +/** + * @brief Inserts a delay time. + * @param nTime: specifies the delay time length, in milliseconds. + * @retval None + */ +void Delay(uint32_t nTime) +{ + TimingDelay = nTime; + + while(TimingDelay != 0); +} + +/** + * @brief Decrements the TimingDelay variable. + * @param None + * @retval None + */ +void TimingDelay_Decrement(void) +{ + if (TimingDelay != 0x00) + { + TimingDelay--; + } +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + /* Infinite loop */ + while (1) + { + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/32vl_factory_demo/stm32f10x_conf.h b/example/32vl_factory_demo/stm32f10x_conf.h new file mode 100644 index 000000000..706b92ed9 --- /dev/null +++ b/example/32vl_factory_demo/stm32f10x_conf.h @@ -0,0 +1,76 @@ +/** + ****************************************************************************** + * @file Demo/inc/stm32f10x_conf.h + * @author MCD Application Team + * @version V1.0.0 + * @date 09/13/2010 + * @brief Library configuration file. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_CONF_H +#define __STM32F10x_CONF_H + +/* Includes ------------------------------------------------------------------*/ +/* Uncomment the line below to enable peripheral header file inclusion */ +/* #include "stm32f10x_adc.h" */ +/* #include "stm32f10x_bkp.h" */ +/* #include "stm32f10x_can.h" */ +/* #include "stm32f10x_crc.h" */ +/* #include "stm32f10x_dac.h" */ +/* #include "stm32f10x_dbgmcu.h" */ +/* #include "stm32f10x_dma.h" */ +#include "stm32f10x_exti.h" +#include "stm32f10x_flash.h" +/* #include "stm32f10x_fsmc.h" */ +#include "stm32f10x_gpio.h" +/* #include "stm32f10x_i2c.h" */ +/* #include "stm32f10x_iwdg.h" */ +#include "stm32f10x_pwr.h" +#include "stm32f10x_rcc.h" +/* #include "stm32f10x_rtc.h" */ +/* #include "stm32f10x_sdio.h" */ +/* #include "stm32f10x_spi.h" */ +/* #include "stm32f10x_tim.h" */ +/* #include "stm32f10x_usart.h" */ +/* #include "stm32f10x_wwdg.h" */ +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ +/* #define USE_FULL_ASSERT 1 */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + +#endif /* __STM32F10x_CONF_H */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/32vl_factory_demo/stm32f10x_it.c b/example/32vl_factory_demo/stm32f10x_it.c new file mode 100644 index 000000000..c1035270e --- /dev/null +++ b/example/32vl_factory_demo/stm32f10x_it.c @@ -0,0 +1,160 @@ +/** + ****************************************************************************** + * @file Demo/src/stm32f10x_it.c + * @author MCD Application Team + * @version V1.0.0 + * @date 09/13/2010 + * @brief Main Interrupt Service Routines. + * This file provides template for all exceptions handler and peripherals + * interrupt service routine. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x_it.h" +void TimingDelay_Decrement(void); +/** @addtogroup Demo + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M3 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSV_Handler exception. + * @param None + * @retval None + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +void SysTick_Handler(void) +{ + TimingDelay_Decrement(); +} + +/******************************************************************************/ +/* STM32F10x Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_stm32f10x_xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/32vl_factory_demo/stm32f10x_it.h b/example/32vl_factory_demo/stm32f10x_it.h new file mode 100644 index 000000000..e8d2b316e --- /dev/null +++ b/example/32vl_factory_demo/stm32f10x_it.h @@ -0,0 +1,46 @@ +/** + ****************************************************************************** + * @file Demo/inc/stm32f10x_it.h + * @author MCD Team + * @version V1.0.0 + * @date 09/13/2010 + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F10x_IT_H +#define __STM32F10x_IT_H + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f10x.h" + +/* Exported types ------------------------------------------------------------*/ +extern vu32 TickValue; +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif /* __STM32F10x_IT_H */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/32vl_factory_demo/system_stm32f10x.c b/example/32vl_factory_demo/system_stm32f10x.c new file mode 100644 index 000000000..aed930ec8 --- /dev/null +++ b/example/32vl_factory_demo/system_stm32f10x.c @@ -0,0 +1,1019 @@ +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +#include "stm32f10x.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low and Medium density Value line devices an external 8MHz crystal + is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) +/* #define SYSCLK_FREQ_HSE HSE_Value */ + #define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_Value */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) +/* #define DATA_IN_ExtSRAM */ +#endif + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_24MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_36MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_Value; /*!< System Clock Frequency (Core Clock) */ +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_24MHz + static void SetSysClockTo24(void); +#elif defined SYSCLK_FREQ_36MHz + static void SetSysClockTo36(void); +#elif defined SYSCLK_FREQ_48MHz + static void SetSysClockTo48(void); +#elif defined SYSCLK_FREQ_56MHz + static void SetSysClockTo56(void); +#elif defined SYSCLK_FREQ_72MHz + static void SetSysClockTo72(void); +#endif + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * @note None + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_Value; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = HSE_Value; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_Value >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_Value / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (HSE_Value >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_Value * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_Value >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSE_Value / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_Value; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_24MHz + SetSysClockTo24(); +#elif defined SYSCLK_FREQ_36MHz + SetSysClockTo36(); +#elif defined SYSCLK_FREQ_48MHz + SetSysClockTo48(); +#elif defined SYSCLK_FREQ_56MHz + SetSysClockTo56(); +#elif defined SYSCLK_FREQ_72MHz + SetSysClockTo72(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + GPIOG->CRH = 0x44444B44; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; +} +#endif /* DATA_IN_ExtSRAM */ + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + +#ifndef STM32F10X_CL + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#else + if (HSE_Value <= 24000000) + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; + } + else + { + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + } +#endif /* STM32F10X_CL */ +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_24MHz +/** + * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo24(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 0 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; +#endif + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); + + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_36MHz +/** + * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo36(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); + + /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + +#else + /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_48MHz +/** + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo48(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL6); +#else + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_56MHz +/** + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo56(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL7); +#else + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); + +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_72MHz +/** + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 + * and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo72(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; + + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + +#ifdef STM32F10X_CL + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ + + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + + + /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | + RCC_CFGR_PLLMULL9); +#else + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | + RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); +#endif /* STM32F10X_CL */ + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ From a7c80d038f3bc0ebe3a61e76c26f4dabc25977d8 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 8 Nov 2011 01:13:50 +0000 Subject: [PATCH 0050/1435] Fix linking with new names --- example/32l_dac/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/example/32l_dac/Makefile b/example/32l_dac/Makefile index 4bd6eb454..87773ef14 100644 --- a/example/32l_dac/Makefile +++ b/example/32l_dac/Makefile @@ -20,7 +20,7 @@ CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM) -LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32l_discovery +LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_l1xx all: $(BIN_IMAGE) From b48420e3941991b9d3f646e539499327c2417a3c Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 12 Nov 2011 18:21:46 +0000 Subject: [PATCH 0051/1435] Don't refetch the chip id on every single page erase. And update some of the logging to be a bit tidier --- src/stlink-common.c | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 4286cf001..f7904c0d3 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -135,10 +135,12 @@ static int unlock_flash_if(stlink_t *sl) { if (is_flash_locked(sl)) { unlock_flash(sl); - if (is_flash_locked(sl)) + if (is_flash_locked(sl)) { + WLOG("Failed to unlock flash!\n"); return -1; + } } - + ILOG("Successfully unlocked flash\n"); return 0; } @@ -741,10 +743,16 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, s return 0; } +/** + * Erase a page of flash, assumes sl is fully populated with things like chip/core ids + * @param sl stlink context + * @param page + * @return 0 on success -ve on failure + */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) { /* page an addr in the page to erase */ - ILOG("Erasing flash page at addr: %#x\n", page); + ILOG("Erasing flash page at addr: %#x\n", page); if (sl->core_id == STM32L_CORE_ID) { #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) @@ -771,7 +779,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) val = read_uint32(sl->q_buf, 0); if (val & (1 << 0)) { - fprintf(stderr, "pecr.pelock not clear (0x%x)\n", val); + WLOG("pecr.pelock not clear (%#x)\n", val); return -1; } @@ -786,7 +794,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) val = read_uint32(sl->q_buf, 0); if (val & (1 << 1)) { - fprintf(stderr, "pecr.prglock not clear (0x%x)\n", val); + WLOG("pecr.prglock not clear (%#x)\n", val); return -1; } @@ -994,11 +1002,11 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) { size_t off; flash_loader_t fl; - ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); /* check addr range is inside the flash */ if (addr < sl->flash_base) { - WLOG("addr too low\n"); + WLOG("addr too low %#x < %#x\n", addr, sl->flash_base); return -1; } else if ((addr + len) < addr) { WLOG("addr overruns\n"); @@ -1014,6 +1022,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned return -1; } + // Make sure we've loaded the context with the chip details + stlink_core_id(sl); /* erase each page */ int page_count = 0; for (off = 0; off < len; off += sl->flash_pgsz) { @@ -1226,7 +1236,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); // FIXME This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { - fprintf(stderr, "write_buffer_to_sram() == -1\n"); + // IMPOSSIBLE! + WLOG("write_buffer_to_sram() == -1\n"); return -1; } From 2600d78b7cf1910d9d74f5b7057a7ddc6cd3fead Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 02:59:38 +0000 Subject: [PATCH 0052/1435] Start to keep an uptodate list of what's been tested in what combinations --- README | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/README b/README index 470c52a59..082a8f26c 100644 --- a/README +++ b/README @@ -119,3 +119,24 @@ Q: At some point I use GDB command `next', and it hangs. A: Sometimes when you will try to use GDB `next' command to skip a loop, it will use a rather inefficient single-stepping way of doing that. Set up a breakpoint manually in that case and do `continue'. + +Currently known working combinations of programmer and target +============================================================= + +STLink v1 (as found on the 32VL Discovery board) + +Known Working Targets: +* STM32F100xx (Medium Density VL) +* STM32F103 (according to jpa- o n##stm32 + +No information: +* everything else! + + +STLink v2 (as found on the 32L and F4 Discovery boards) +Known Working Targets: +* STM32F100xx (Medium Density VL, as on the 32VL Discovery board) +* ? + +Please report any and all known working combinations so I can update this! + From 93da0169c08cb7d81ba2b530ac93482de6ec7bc1 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 03:03:07 +0000 Subject: [PATCH 0053/1435] Remove confusing distclean/clean dichotomy in the top level, make clean cleans all stlink code. in an application level, it only cleans that application --- Makefile | 2 -- 1 file changed, 2 deletions(-) diff --git a/Makefile b/Makefile index d35b3c4f1..f24ed13b0 100644 --- a/Makefile +++ b/Makefile @@ -42,8 +42,6 @@ clean: rm -rf $(LIBRARY) rm -rf test_usb* rm -rf test_sg* - -distclean: clean $(MAKE) -C flash clean $(MAKE) -C gdbserver clean From 55dd45cb49e5a2c639d9f60d3a1de7b1a88b93c2 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 03:24:12 +0000 Subject: [PATCH 0054/1435] Note that many of these "examples" are busted --- example/README | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 example/README diff --git a/example/README b/example/README new file mode 100644 index 000000000..5d72e8282 --- /dev/null +++ b/example/README @@ -0,0 +1,6 @@ +Don't trust many of these examples yet... A lot of them are a work in +progress... + +A good source of examples is in the libopencm3 sources: http://sourceforge.net/projects/libopencm3/ + + From a76c9ccfb34acf2fdca97db1a8e087e43a43d9b0 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 03:47:47 +0000 Subject: [PATCH 0055/1435] Remove lots of dead code and superfluous trace Lots of the debug code is far too verbose for anything but usb tracing. Likewise, remove all the old scsi code that was simply ifdefd out. --- src/stlink-sg.c | 182 ++---------------------------------------------- 1 file changed, 6 insertions(+), 176 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index c4392dbfe..f9170009b 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -113,15 +113,13 @@ static void clear_cdb(struct stlink_libsg *sl) { sl->q_data_dir = Q_DATA_IN; } -// close the device, free the allocated memory - -void _stlink_sg_close(stlink_t *sl) { +/** + * Close and free any _backend_ related information... + * @param sl + */void _stlink_sg_close(stlink_t *sl) { if (sl) { -#if FINISHED_WITH_SG struct stlink_libsg *slsg = sl->backend_data; - scsi_pt_close_device(slsg->sg_fd); free(slsg); -#endif } } @@ -141,11 +139,11 @@ static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t end try++; } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); if (ret != LIBUSB_SUCCESS) { - fprintf(stderr, "%s: receiving failed: %d\n", __func__, ret); + WLOG("%s: receiving failed: %d\n", __func__, ret); return -1; } if (transferred != sizeof(csw)) { - fprintf(stderr, "%s: received unexpected amount: %d\n", __func__, transferred); + WLOG("%s: received unexpected amount: %d\n", __func__, transferred); return -1; } @@ -157,10 +155,8 @@ static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t end WLOG("status signature was invalid: %#x\n", rsig); return -1; } - DLOG("residue was= %#x\n", residue); *tag = rtag; uint8_t rstatus = csw[12]; - DLOG("rstatus = %x\n", rstatus); return rstatus; } @@ -223,11 +219,9 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint memcpy(&(c_buf[i]), cdb, cdb_length); int sending_length = STLINK_SG_SIZE; - DLOG("sending length set to: %d\n", sending_length); // send.... do { - DLOG("attempting tx...\n"); ret = libusb_bulk_transfer(handle, endpoint_out, c_buf, sending_length, &real_transferred, SG_TIMEOUT_MSEC); if (ret == LIBUSB_ERROR_PIPE) { @@ -239,7 +233,6 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint WLOG("sending failed: %d\n", ret); return -1; } - DLOG("Actually sent: %d, returning tag: %d\n", real_transferred, tag); return this_tag; } @@ -298,93 +291,6 @@ get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_ou } } - -//TODO rewrite/cleanup, save the error in sl - -#if FINISHED_WITH_SG -static void stlink_confirm_inq(stlink_t *stl, struct sg_pt_base *ptvp) { - struct stlink_libsg *sl = stl->backend_data; - const int e = sl->do_scsi_pt_err; - if (e < 0) { - fprintf(stderr, "scsi_pt error: pass through os error: %s\n", - safe_strerror(-e)); - return; - } else if (e == SCSI_PT_DO_BAD_PARAMS) { - fprintf(stderr, "scsi_pt error: bad pass through setup\n"); - return; - } else if (e == SCSI_PT_DO_TIMEOUT) { - fprintf(stderr, " pass through timeout\n"); - return; - } - const int duration = get_scsi_pt_duration_ms(ptvp); - if ((stl->verbose > 1) && (duration >= 0)) - DLOG(" duration=%d ms\n", duration); - - // XXX stlink fw sends broken residue, so ignore it and use the known q_len - // "usb-storage quirks=483:3744:r" - // forces residue to be ignored and calculated, but this causes aboard if - // data_len = 0 and by some other data_len values. - - const int resid = get_scsi_pt_resid(ptvp); - const int dsize = stl->q_len - resid; - - const int cat = get_scsi_pt_result_category(ptvp); - char buf[512]; - unsigned int slen; - - switch (cat) { - case SCSI_PT_RESULT_GOOD: - if (stl->verbose && (resid > 0)) - DLOG(" notice: requested %d bytes but " - "got %d bytes, ignore [broken] residue = %d\n", - stl->q_len, dsize, resid); - break; - case SCSI_PT_RESULT_STATUS: - if (stl->verbose) { - sg_get_scsi_status_str( - get_scsi_pt_status_response(ptvp), sizeof (buf), - buf); - DLOG(" scsi status: %s\n", buf); - } - return; - case SCSI_PT_RESULT_SENSE: - slen = get_scsi_pt_sense_len(ptvp); - if (stl->verbose) { - sg_get_sense_str("", sl->sense_buf, slen, (stl->verbose - > 1), sizeof (buf), buf); - DLOG("%s", buf); - } - if (stl->verbose && (resid > 0)) { - if ((stl->verbose) || (stl->q_len > 0)) - DLOG(" requested %d bytes but " - "got %d bytes\n", stl->q_len, dsize); - } - return; - case SCSI_PT_RESULT_TRANSPORT_ERR: - if (stl->verbose) { - get_scsi_pt_transport_err_str(ptvp, sizeof (buf), buf); - // http://tldp.org/HOWTO/SCSI-Generic-HOWTO/x291.html - // These codes potentially come from the firmware on a host adapter - // or from one of several hosts that an adapter driver controls. - // The 'host_status' field has the following values: - // [0x07] Internal error detected in the host adapter. - // This may not be fatal (and the command may have succeeded). - DLOG(" transport: %s", buf); - } - return; - case SCSI_PT_RESULT_OS_ERR: - if (stl->verbose) { - get_scsi_pt_os_err_str(ptvp, sizeof (buf), buf); - DLOG(" os: %s", buf); - } - return; - default: - fprintf(stderr, " unknown pass through result " - "category (%d)\n", cat); - } -} -#endif - /** * Just send a buffer on an endpoint, no questions asked. * Handles repeats, and time outs. Also handles reading status reports and sense @@ -401,7 +307,6 @@ int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, int real_transferred; int try; do { - DLOG("attempting tx...\n"); ret = libusb_bulk_transfer(handle, endpoint_out, cbuf, length, &real_transferred, SG_TIMEOUT_MSEC); if (ret == LIBUSB_ERROR_PIPE) { @@ -413,7 +318,6 @@ int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, WLOG("sending failed: %d\n", ret); return -1; } - DLOG("Actually sent: %d\n", real_transferred); // now, swallow up the status, so that things behave nicely... uint32_t received_tag; @@ -452,7 +356,6 @@ int stlink_q(stlink_t *sl) { int ret; if (rx_length > 0) { do { - DLOG("attempting rx\n"); ret = libusb_bulk_transfer(sg->usb_handle, sg->ep_rep, sl->q_buf, rx_length, &real_transferred, SG_TIMEOUT_MSEC); if (ret == LIBUSB_ERROR_PIPE) { @@ -493,40 +396,6 @@ int stlink_q(stlink_t *sl) { return -1; } return 0; - - - DLOG("Actually received: %d\n", real_transferred); - -#if FINISHED_WITH_SG - // Get control command descriptor of scsi structure, - // (one object per command!!) - struct sg_pt_base *ptvp = construct_scsi_pt_obj(); - if (NULL == ptvp) { - fprintf(stderr, "construct_scsi_pt_obj: out of memory\n"); - return; - } - - set_scsi_pt_cdb(ptvp, sg->cdb_cmd_blk, sizeof (sg->cdb_cmd_blk)); - - // set buffer for sense (error information) data - set_scsi_pt_sense(ptvp, sg->sense_buf, sizeof (sg->sense_buf)); - - // Set a buffer to be used for data transferred from device - if (sg->q_data_dir == Q_DATA_IN) { - //clear_buf(sl); - set_scsi_pt_data_in(ptvp, sl->q_buf, sl->q_len); - } else { - set_scsi_pt_data_out(ptvp, sl->q_buf, sl->q_len); - } - // Executes SCSI command (or at least forwards it to lower layers). - sg->do_scsi_pt_err = do_scsi_pt(ptvp, sg->sg_fd, SG_TIMEOUT_SEC, - sl->verbose); - - // check for scsi errors - stlink_confirm_inq(sl, ptvp); - // TODO recycle: clear_scsi_pt_obj(struct sg_pt_base * objp); - destruct_scsi_pt_obj(ptvp); -#endif } // TODO thinking, cleanup @@ -552,14 +421,11 @@ void stlink_stat(stlink_t *stl, char *txt) { void _stlink_sg_version(stlink_t *stl) { struct stlink_libsg *sl = stl->backend_data; - DLOG("\n*** stlink_version ***\n"); clear_cdb(sl); sl->cdb_cmd_blk[0] = STLINK_GET_VERSION; stl->q_len = 6; sl->q_addr = 0; stlink_q(stl); - // HACK use my own private version right now... - } // Get stlink mode: @@ -681,7 +547,6 @@ void _stlink_sg_reset(stlink_t *sl) { void _stlink_sg_status(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - DLOG("\n*** stlink_status ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_GETSTATUS; sl->q_len = 2; @@ -693,7 +558,6 @@ void _stlink_sg_status(stlink_t *sl) { void _stlink_sg_force_debug(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - DLOG("\n*** stlink_force_debug ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_FORCEDEBUG; sl->q_len = 2; @@ -820,7 +684,6 @@ void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { void _stlink_sg_run(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - DLOG("\n*** stlink_run ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_RUNCORE; sl->q_len = 2; @@ -935,39 +798,6 @@ void _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { stlink_print_data(sl); } -#if 0 /* not working */ - -static int write_flash_mem16 -(struct stlink* sl, uint32_t addr, uint16_t val) { - /* half word writes */ - if (addr % 2) return -1; - - /* unlock if locked */ - unlock_flash_if(sl); - - /* set flash programming chosen bit */ - set_flash_cr_pg(sl); - - write_uint16(sl->q_buf, val); - stlink_write_mem16(sl, addr, 2); - - /* wait for non business */ - wait_flash_busy(sl); - - lock_flash(sl); - - /* check the programmed value back */ - stlink_read_mem16(sl, addr, 2); - if (*(const uint16_t*) sl->q_buf != val) { - /* values differ at i * sizeof(uint16_t) */ - return -1; - } - - /* success */ - return 0; -} -#endif /* not working */ - // Exit the jtag or swd mode and enter the mass mode. void _stlink_sg_exit_debug_mode(stlink_t *stl) { From e509310406ba4db9e88ce7c0ea2aad985cb25008 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 03:52:19 +0000 Subject: [PATCH 0056/1435] Start up stlinkv1 faster. Now that we're not using sg, and we've told the kernel to ignore the device in usb-mass storage, we don't need to close and wait 5 seconds. We can just immediately issue the command to switch modes. --- src/stlink-sg.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index f9170009b..7f0badcfe 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -467,7 +467,7 @@ void _stlink_sg_enter_jtag_mode(stlink_t *sl) { } // XXX kernel driver performs reset, the device temporally disappears - +// Suspect this is no longer the case when we have ignore on? RECHECK void _stlink_sg_exit_dfu_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_exit_dfu_mode ***\n"); @@ -964,18 +964,6 @@ stlink_t* stlink_v1_open_inner(const int verbose) { DLOG("Attempting to exit DFU mode\n"); _stlink_sg_exit_dfu_mode(sl); - // exit the dfu mode -> the device is gone - DLOG("\n*** reopen the stlink device ***\n"); - delay(1000); - stlink_close(sl); - delay(5000); - - DLOG("Attempting to reopen the stlink...\n"); - sl = stlink_open(verbose); - if (sl == NULL) { - fputs("Error: could not open stlink device\n", stderr); - return NULL; - } // re-query device info (and retest) stlink_version(sl); if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { From d019d3fc4f34297a78bf8c38c5a06053b2707862 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 04:11:10 +0000 Subject: [PATCH 0057/1435] Turn down default logging level. And remove dead/duplicate code that is included in the opening of the device --- gdbserver/gdb-server.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index ce0549e7a..e7676219c 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -21,7 +21,7 @@ #include "gdb-remote.h" -#define DEFAULT_LOGGING_LEVEL 100 +#define DEFAULT_LOGGING_LEVEL 50 #define DEFAULT_GDB_LISTEN_PORT 4242 #define STRINGIFY_inner(name) #name @@ -169,17 +169,8 @@ int main(int argc, char** argv) { break; } - // ALLLL of this should move into "stlink_open_xxx" - - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { - stlink_exit_dfu_mode(sl); - } - stlink_enter_swd_mode(sl); - } - - uint32_t chip_id = stlink_chip_id(sl); - uint32_t core_id = stlink_core_id(sl); + uint32_t chip_id = sl->chip_id; + uint32_t core_id = sl->core_id; /* Fix chip_id for F4 */ if (((chip_id & 0xFFF) == 0x411) && (core_id == CORE_M4_R0)) { From dbe5391bd1354d651cda7c10be3c4b601ea4cdc9 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 04:12:29 +0000 Subject: [PATCH 0058/1435] Remove dead code and unused variables --- src/stlink-common.c | 4 ++-- src/stlink-sg.c | 8 -------- src/stlink-usb.c | 31 ------------------------------- 3 files changed, 2 insertions(+), 41 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index f7904c0d3..a853d13ad 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -314,7 +314,7 @@ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { */ int stlink_load_device_params(stlink_t *sl) { ILOG("Loading device parameters....\n"); - chip_params_t *params = NULL; + const chip_params_t *params = NULL; uint32_t chip_id = stlink_chip_id(sl); sl->chip_id = chip_id; for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { @@ -547,7 +547,7 @@ void stlink_core_stat(stlink_t *sl) { } void stlink_print_data(stlink_t * sl) { - if (sl->q_len <= 0 || sl->verbose < 2) + if (sl->q_len <= 0 || sl->verbose < UDEBUG) return; if (sl->verbose > 2) fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len); diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 7f0badcfe..b6ac4963b 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -97,14 +97,6 @@ #define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) #define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) -// Suspends execution of the calling process for -// (at least) ms milliseconds. - -static void delay(int ms) { - //fprintf(stderr, "*** wait %d ms\n", ms); - usleep(1000 * ms); -} - static void clear_cdb(struct stlink_libsg *sl) { for (size_t i = 0; i < sizeof (sl->cdb_cmd_blk); i++) sl->cdb_cmd_blk[i] = 0; diff --git a/src/stlink-usb.c b/src/stlink-usb.c index b4df70efb..58c4e1d33 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -150,33 +150,6 @@ static inline int send_only } -/* Search for a STLINK device, either any or teh one with the given PID - * Return the protocoll version - */ -static int is_stlink_device(libusb_device * dev, uint16_t pid) { - struct libusb_device_descriptor desc; - int version; - - if (libusb_get_device_descriptor(dev, &desc)) - return 0; - - if (desc.idVendor != USB_ST_VID) - return 0; - - if ((desc.idProduct != USB_STLINK_32L_PID) && - (desc.idProduct != USB_STLINK_PID )) - return 0; - - if(pid && (pid != desc.idProduct)) - return 0; - if (desc.idProduct == USB_STLINK_PID ) - version = 1; - else - version = 2; - - return version; -} - static int fill_command (stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t len) { struct stlink_libusb * const slu = sl->backend_data; @@ -580,11 +553,7 @@ stlink_t* stlink_open_usb(const int verbose) { struct stlink_libusb* slu = NULL; int error = -1; libusb_device** devs = NULL; - libusb_device* dev; - ssize_t i; - ssize_t count; int config; - char *iSerial = NULL; sl = malloc(sizeof (stlink_t)); slu = malloc(sizeof (struct stlink_libusb)); From 9ac1f0d9d69d7f30a932fcc8977d40b12a9377f6 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 04:12:49 +0000 Subject: [PATCH 0059/1435] Fix memory leaks closing v1 hardware. Thanks valgrind --- src/stlink-sg.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index b6ac4963b..062e83dbd 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -111,6 +111,8 @@ static void clear_cdb(struct stlink_libsg *sl) { */void _stlink_sg_close(stlink_t *sl) { if (sl) { struct stlink_libsg *slsg = sl->backend_data; + libusb_close(slsg->usb_handle); + libusb_exit(slsg->libusb_ctx); free(slsg); } } From 09d732d776a869d1f8cbfcb62bbed4b0a9c79a4d Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 04:14:41 +0000 Subject: [PATCH 0060/1435] Keep netbeans happy --- nbproject/Package-flash.bash | 75 +++ nbproject/configurations.xml | 1208 ++++++++++------------------------ nbproject/project.xml | 4 - 3 files changed, 411 insertions(+), 876 deletions(-) create mode 100644 nbproject/Package-flash.bash diff --git a/nbproject/Package-flash.bash b/nbproject/Package-flash.bash new file mode 100644 index 000000000..44fd0fc43 --- /dev/null +++ b/nbproject/Package-flash.bash @@ -0,0 +1,75 @@ +#!/bin/bash -x + +# +# Generated - do not edit! +# + +# Macros +TOP=`pwd` +CND_PLATFORM=GNU-Linux-x86 +CND_CONF=flash +CND_DISTDIR=dist +CND_BUILDDIR=build +NBTMPDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM}/tmp-packaging +TMPDIRNAME=tmp-packaging +OUTPUT_PATH=MissingOutputInProject +OUTPUT_BASENAME=MissingOutputInProject +PACKAGE_TOP_DIR=stlink/ + +# Functions +function checkReturnCode +{ + rc=$? + if [ $rc != 0 ] + then + exit $rc + fi +} +function makeDirectory +# $1 directory path +# $2 permission (optional) +{ + mkdir -p "$1" + checkReturnCode + if [ "$2" != "" ] + then + chmod $2 "$1" + checkReturnCode + fi +} +function copyFileToTmpDir +# $1 from-file path +# $2 to-file path +# $3 permission +{ + cp "$1" "$2" + checkReturnCode + if [ "$3" != "" ] + then + chmod $3 "$2" + checkReturnCode + fi +} + +# Setup +cd "${TOP}" +mkdir -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package +rm -rf ${NBTMPDIR} +mkdir -p ${NBTMPDIR} + +# Copy files and create directories and links +cd "${TOP}" +makeDirectory "${NBTMPDIR}/stlink" +copyFileToTmpDir "${OUTPUT_PATH}" "${NBTMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755 + + +# Generate tar file +cd "${TOP}" +rm -f ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stlink.tar +cd ${NBTMPDIR} +tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stlink.tar * +checkReturnCode + +# Cleanup +cd "${TOP}" +rm -rf ${NBTMPDIR} diff --git a/nbproject/configurations.xml b/nbproject/configurations.xml index e129c44f6..f1fcd48d1 100644 --- a/nbproject/configurations.xml +++ b/nbproject/configurations.xml @@ -7,21 +7,42 @@ - - main.c - - + + discover_board.h main.c startup_stm32l1xx_md.s system_stm32l1xx.c - + discover_board.h main.c stm32l_discovery_lcd.c stm32l_discovery_lcd.h - + + main.c + startup_stm32f10x_md_vl.S + stm32f10x_conf.h + stm32f10x_it.c + stm32f10x_it.h + system_stm32f10x.c + + + main.c + + + discover_board.h + main.c + startup_stm32l1xx_md.s + system_stm32l1xx.c + + + + STM32vldiscovery.c + STM32vldiscovery.h + + + @@ -33,71 +54,149 @@ core_cm3.h + stm32f10x.h stm32l1xx.h + system_stm32f10x.h system_stm32l1xx.h - misc.h - stm32l1xx_adc.h - stm32l1xx_comp.h - stm32l1xx_crc.h - stm32l1xx_dac.h - stm32l1xx_dbgmcu.h - stm32l1xx_dma.h - stm32l1xx_exti.h - stm32l1xx_flash.h - stm32l1xx_gpio.h - stm32l1xx_i2c.h - stm32l1xx_iwdg.h - stm32l1xx_lcd.h - stm32l1xx_pwr.h - stm32l1xx_rcc.h - stm32l1xx_rtc.h - stm32l1xx_spi.h - stm32l1xx_syscfg.h - stm32l1xx_tim.h - stm32l1xx_usart.h - stm32l1xx_wwdg.h + + misc.h + stm32f10x_adc.h + stm32f10x_bkp.h + stm32f10x_can.h + stm32f10x_cec.h + stm32f10x_crc.h + stm32f10x_dac.h + stm32f10x_dbgmcu.h + stm32f10x_dma.h + stm32f10x_exti.h + stm32f10x_flash.h + stm32f10x_fsmc.h + stm32f10x_gpio.h + stm32f10x_i2c.h + stm32f10x_iwdg.h + stm32f10x_pwr.h + stm32f10x_rcc.h + stm32f10x_rtc.h + stm32f10x_sdio.h + stm32f10x_spi.h + stm32f10x_tim.h + stm32f10x_usart.h + stm32f10x_wwdg.h + + + misc.h + stm32l1xx_adc.h + stm32l1xx_comp.h + stm32l1xx_crc.h + stm32l1xx_dac.h + stm32l1xx_dbgmcu.h + stm32l1xx_dma.h + stm32l1xx_exti.h + stm32l1xx_flash.h + stm32l1xx_gpio.h + stm32l1xx_i2c.h + stm32l1xx_iwdg.h + stm32l1xx_lcd.h + stm32l1xx_pwr.h + stm32l1xx_rcc.h + stm32l1xx_rtc.h + stm32l1xx_spi.h + stm32l1xx_syscfg.h + stm32l1xx_tim.h + stm32l1xx_usart.h + stm32l1xx_wwdg.h + - misc.c - stm32l1xx_adc.c - stm32l1xx_comp.c - stm32l1xx_crc.c - stm32l1xx_dac.c - stm32l1xx_dbgmcu.c - stm32l1xx_dma.c - stm32l1xx_exti.c - stm32l1xx_flash.c - stm32l1xx_flash_ramfunc.c - stm32l1xx_gpio.c - stm32l1xx_i2c.c - stm32l1xx_iwdg.c - stm32l1xx_lcd.c - stm32l1xx_pwr.c - stm32l1xx_rcc.c - stm32l1xx_rtc.c - stm32l1xx_spi.c - stm32l1xx_syscfg.c - stm32l1xx_tim.c - stm32l1xx_usart.c - stm32l1xx_wwdg.c + + misc.c + stm32f10x_adc.c + stm32f10x_bkp.c + stm32f10x_can.c + stm32f10x_cec.c + stm32f10x_crc.c + stm32f10x_dac.c + stm32f10x_dbgmcu.c + stm32f10x_dma.c + stm32f10x_exti.c + stm32f10x_flash.c + stm32f10x_fsmc.c + stm32f10x_gpio.c + stm32f10x_i2c.c + stm32f10x_iwdg.c + stm32f10x_pwr.c + stm32f10x_rcc.c + stm32f10x_rtc.c + stm32f10x_sdio.c + stm32f10x_spi.c + stm32f10x_tim.c + stm32f10x_usart.c + stm32f10x_wwdg.c + + + misc.c + stm32l1xx_adc.c + stm32l1xx_comp.c + stm32l1xx_crc.c + stm32l1xx_dac.c + stm32l1xx_dbgmcu.c + stm32l1xx_dma.c + stm32l1xx_exti.c + stm32l1xx_flash.c + stm32l1xx_flash_ramfunc.c + stm32l1xx_gpio.c + stm32l1xx_i2c.c + stm32l1xx_iwdg.c + stm32l1xx_lcd.c + stm32l1xx_pwr.c + stm32l1xx_rcc.c + stm32l1xx_rtc.c + stm32l1xx_spi.c + stm32l1xx_syscfg.c + stm32l1xx_tim.c + stm32l1xx_usart.c + stm32l1xx_wwdg.c + - - discover_board.h - discover_functions.c - discover_functions.h - icc_measure.c - icc_measure.h - icc_measure_Ram.c - main.c - stm32_tsl_conf.h - stm32l1xx_conf.h - stm32l1xx_it.c - stm32l1xx_it.h - stm32l_discovery_lcd.c - stm32l_discovery_lcd.h - system_stm32l1xx.c + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -154,18 +253,22 @@ ${MAKE} -f Makefile ${MAKE} -f Makefile clean gdbserver/st-util - - - . - - - DEBUG=1 - - + + + + + + - + - + - - - - - - + - + - + + + - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + . + + + DEBUG=1 + + + + + + + src + + + CONFIG_USE_LIBUSB=1 + DEBUG + + + src - CONFIG_USE_LIBSG=1 CONFIG_USE_LIBUSB=1 - - - - - - + + + + . + + + DEBUG=1 + + + - + LOCAL_SOURCES default - gdbserver + flash ${MAKE} -f Makefile ${MAKE} -f Makefile clean + + + DEBUG + + + + @@ -519,685 +631,37 @@ tool="0" flavor="0"> - - - - - - - - - - - - - - - - - - - - - - - + + + + src + + + CONFIG_USE_LIBUSB=1 + + + + + + + src + + + CONFIG_USE_LIBSG=1 + CONFIG_USE_LIBUSB=1 + + + + + + + . + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - src - - - CONFIG_USE_LIBSG=1 - CONFIG_USE_LIBUSB=1 - - - - - - - . - - - DEBUG=1 - - - - - - - - - - - LOCAL_SOURCES - default - - - - flash - ${MAKE} -f Makefile - ${MAKE} -f Makefile clean - - - - DEBUG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - src - - - CONFIG_USE_LIBSG=1 - CONFIG_USE_LIBUSB=1 - - - - - - - src - - - CONFIG_USE_LIBSG=1 - CONFIG_USE_LIBUSB=1 - - - - - - - . - - - DEBUG=1 - - - - + diff --git a/nbproject/project.xml b/nbproject/project.xml index 946c06f6f..7526e4b6b 100644 --- a/nbproject/project.xml +++ b/nbproject/project.xml @@ -17,10 +17,6 @@ Default 0 - - gdbserver - 0 - flash 0 From 93b186f15b493728d1662f4a6f96aae835962f02 Mon Sep 17 00:00:00 2001 From: jnosky Date: Mon, 14 Nov 2011 16:15:31 -0500 Subject: [PATCH 0061/1435] Removed comment about STM32F4 limitations --- README | 3 --- 1 file changed, 3 deletions(-) diff --git a/README b/README index b980bbf0c..f85c6815a 100644 --- a/README +++ b/README @@ -76,9 +76,6 @@ If you would link your executable to 0x08000000 and then do (gdb) load firmware.elf then it would be written to the memory. -STM32F4: -The flash utility supports the full 1MB address space. -The gdbserver only supports up to 64kB applications at the moment. FAQ === From 67db39b0b31dc76dcc83405f7dba28ee04f90432 Mon Sep 17 00:00:00 2001 From: jnosky Date: Mon, 14 Nov 2011 16:16:57 -0500 Subject: [PATCH 0062/1435] Changed size argument to hex Address was hex, size was decimal. Now uniform to be hex --- flash/main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/flash/main.c b/flash/main.c index 46a8ce171..f1d0b4f84 100644 --- a/flash/main.c +++ b/flash/main.c @@ -21,6 +21,7 @@ static void usage(void) { puts("stlinkv1 command line: ./flash {read|write} /dev/sgX path addr "); puts("stlinkv2 command line: ./flash {read|write} path addr "); + puts(" use hex format for addr and "); } static int get_opts(struct opts* o, int ac, char** av) @@ -46,7 +47,7 @@ static int get_opts(struct opts* o, int ac, char** av) i = 1; } - o->size = strtoul(av[i + 3], NULL, 10); + o->size = strtoul(av[i + 3], NULL, 16); } else if (strcmp(av[0], "write") == 0) { From 768a70d3213fcfcd605961a770c5446276fd1df8 Mon Sep 17 00:00:00 2001 From: jnosky Date: Mon, 14 Nov 2011 16:20:49 -0500 Subject: [PATCH 0063/1435] Added code so gdbserver can fully support the STM32F4 variable page sizes gdbserver can now upload up to 1MB projects to flash --- gdbserver/gdb-server.c | 120 ++++++++++++++++++++++++++--------------- src/stlink-common.c | 79 ++++++++++++++------------- src/stlink-common.h | 3 +- 3 files changed, 122 insertions(+), 80 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 371d779d7..b5d66dff5 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -21,9 +21,9 @@ #include "gdb-remote.h" #define FLASH_BASE 0x08000000 + +//Allways update the FLASH_PAGE before each use, by calling stlink_calculate_pagesize #define FLASH_PAGE (sl->flash_pgsz) -#define FLASH_PAGE_MASK (~((1 << 10) - 1)) -#define FLASH_SIZE (FLASH_PAGE * 128) volatile int do_exit = 0; void ctrl_c(int sig) @@ -44,19 +44,19 @@ struct chip_params { uint32_t bootrom_base, bootrom_size; } const devices[] = { { 0x410, "F1 Medium-density device", 0x1ffff7e0, - 0x20000, 0x400, 0x5000, 0x1ffff000, 0x800 }, // table 2, pm0063 + 0x20000, 0x400, 0x5000, 0x1ffff000, 0x800 }, // table 2, pm0063 { 0x411, "F2 device", 0, /* No flash size register found in the docs*/ - 0x100000, 0x20000, 0x20000, 0x1fff0000, 0x7800 }, // table 1, pm0059 + 0x100000, 0x20000, 0x20000, 0x1fff0000, 0x7800 }, // table 1, pm0059 { 0x412, "F1 Low-density device", 0x1ffff7e0, - 0x8000, 0x400, 0x2800, 0x1ffff000, 0x800 }, // table 1, pm0063 - /*No flash size register? page size is variable */ - { 0x413, "F4 device", 0x1FFF7A10, - 0x100000, 0x4000, 0x30000, 0x1fff0000, 0x7800 }, // table 1, pm0081 + 0x8000, 0x400, 0x2800, 0x1ffff000, 0x800 }, // table 1, pm0063 + /*Page size is variable */ + { 0x413, "F4 device", 0x1FFF7A10, //RM0090 error same as unique ID + 0x100000, 0x4000, 0x30000, 0x1fff0000, 0x7800 }, // table 1, pm0081 { 0x414, "F1 High-density device", 0x1ffff7e0, - 0x80000, 0x800, 0x10000, 0x1ffff000, 0x800 }, // table 3 pm0063 + 0x80000, 0x800, 0x10000, 0x1ffff000, 0x800 }, // table 3 pm0063 // This ignores the EEPROM! (and uses the page erase size, // not the sector write protection...) - { 0x416, "L1 Med-density device", 0x1FF8004C, // table 1, pm0062 + { 0x416, "L1 Med-density device", 0x1FF8004C, // table 1, pm0062 0x20000, 0x100, 0x4000, 0x1ff00000, 0x1000 }, { 0x418, "F1 Connectivity line device", 0x1ffff7e0, 0x40000, 0x800, 0x10000, 0x1fffb000, 0x4800 }, @@ -64,18 +64,19 @@ struct chip_params { 0x20000, 0x400, 0x2000, 0x1ffff000, 0x800 }, { 0x428, "F1 High-density value line device", 0x1ffff7e0, 0x80000, 0x800, 0x8000, 0x1ffff000, 0x800 }, - { 0x430, "F1 XL-density device", 0x1ffff7e0, // pm0068 + { 0x430, "F1 XL-density device", 0x1ffff7e0, // pm0068 0x100000, 0x800, 0x18000, 0x1fffe000, 0x1800 }, { 0 } }; int serve(stlink_t *sl, int port); -char* make_memory_map(const struct chip_params *params, uint32_t flash_size); +char* make_memory_map(stlink_t *sl, const struct chip_params *params, uint32_t flash_size); int main(int argc, char** argv) { stlink_t *sl = NULL; - int port = 0; + int port = 0; + uint32_t flash_size; const char * HelpStr = "\nUsage:\n" "\tst-util [Arguments]\n" @@ -209,24 +210,29 @@ int main(int argc, char** argv) { } printf("Device connected: %s\n", params->description); - printf("Device parameters: SRAM: 0x%x bytes, Flash: up to 0x%x bytes in pages of 0x%x bytes\n", - params->sram_size, params->max_flash_size, params->flash_pagesize); - - FLASH_PAGE = params->flash_pagesize; - - //sl->flash_pgsz=0x4000; - //sl->flash_size=0x100000; - - uint32_t flash_size; - stlink_read_mem32(sl, params->flash_size_reg, 4); - flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8); + if(sl->chip_id==STM32F4_CHIP_ID) { + flash_size=0x100000; //todo: RM0090 error; size register same address as unique ID + printf("Device parameters: SRAM: 0x%x bytes, Flash: up to 0x%x bytes with variable page size\n", + params->sram_size, flash_size); + } + else { + printf("Device parameters: SRAM: 0x%x bytes, Flash: up to 0x%x bytes in pages of 0x%x bytes\n", + params->sram_size, params->max_flash_size, params->flash_pagesize); + stlink_read_mem32(sl, params->flash_size_reg, 4); + flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8); + //flash_size_reg is in 1k blocks. + flash_size *= 0x400; + } - //flash_size=0x100000; + /* Init PAGE_SIZE for fixed page size devices. + * stlink_calculate_pagesize will then return this value for them. + * variable pagesize devices must allways update FLASH_PAGE before use! */ + FLASH_PAGE = params->flash_pagesize; + sl->flash_size=flash_size; - printf("Flash size is %d KiB.\n", flash_size); - // memory map is in 1k blocks. - current_memory_map = make_memory_map(params, flash_size * 0x400); + printf("Flash size is %d\n", flash_size); + current_memory_map = make_memory_map(sl, params, flash_size); while(serve(sl, port) == 0); @@ -238,6 +244,28 @@ int main(int argc, char** argv) { return 0; } +static const char* const memory_map_template_F4 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // sram + " " //Sectors 0..3 + " 0x4000" //16kB + " " + " " //Sector 4 + " 0x10000" //64kB + " " + " " //Sectors 5..11 + " 0x20000" //128kB + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + static const char* const memory_map_template = "" "" // option byte area ""; -char* make_memory_map(const struct chip_params *params, uint32_t flash_size) { +char* make_memory_map(stlink_t *sl, const struct chip_params *params, uint32_t flash_size) { /* This will be freed in serve() */ char* map = malloc(4096); map[0] = '\0'; - snprintf(map, 4096, memory_map_template, - flash_size, - params->sram_size, - flash_size, params->flash_pagesize, - params->bootrom_base, params->bootrom_size); - + if(sl->chip_id==STM32F4_CHIP_ID) { + strcpy(map, memory_map_template_F4); + } + + else { + snprintf(map, 4096, memory_map_template, + flash_size, + params->sram_size, + flash_size, params->flash_pagesize, + params->bootrom_base, params->bootrom_size); + } return map; } @@ -491,13 +524,14 @@ struct flash_block { static struct flash_block* flash_root; -static int flash_add_block(stm32_addr_t addr, unsigned length, - stlink_t *sl) { - if(addr < FLASH_BASE || addr + length > FLASH_BASE + FLASH_SIZE) { +static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { + + if(addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) { fprintf(stderr, "flash_add_block: incorrect bounds\n"); return -1; } + stlink_calculate_pagesize(sl, addr); if(addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) { fprintf(stderr, "flash_add_block: unaligned block\n"); return -1; @@ -568,18 +602,18 @@ static int flash_go(stlink_t *sl) { unsigned length = fb->length; for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += FLASH_PAGE) { + + //Update FLASH_PAGE + stlink_calculate_pagesize(sl, page); + #ifdef DEBUG printf("flash_do: page %08x\n", page); #endif - //todo:write flash already does erase so why is this here? - stlink_erase_flash_page(sl, page); - if(stlink_write_flash(sl, page, fb->data + (page - fb->addr), length > FLASH_PAGE ? FLASH_PAGE : length) < 0) goto error; - } - + } } stlink_reset(sl); diff --git a/src/stlink-common.c b/src/stlink-common.c index fcdb405ff..d55dff687 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1,4 +1,4 @@ - +#define DEBUG_FLASH 0 #include #include @@ -148,8 +148,10 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { stlink_read_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); else stlink_read_mem32(sl, FLASH_CR, sizeof (uint32_t)); - fprintf(stdout, "CR:%X\n", *(uint32_t*) sl->q_buf); - return *(uint32_t*) sl->q_buf; +#if DEBUG_FLASH + fprintf(stdout, "CR:0x%x\n", *(uint32_t*) sl->q_buf); +#endif + return *(uint32_t*) sl->q_buf; } static inline unsigned int is_flash_locked(stlink_t *sl) { @@ -281,7 +283,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { stlink_read_mem32(sl, FLASH_F4_SR, sizeof (uint32_t)); else stlink_read_mem32(sl, FLASH_SR, sizeof (uint32_t)); - //fprintf(stdout, "SR:%X\n", *(uint32_t*) sl->q_buf); + //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf); return *(uint32_t*) sl->q_buf; } @@ -323,7 +325,9 @@ static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) { uint32_t x = read_flash_cr(sl); x &= ~(0x03 << 8); x |= (n << 8); - fprintf(stdout, "PSIZ:%X %X\n", x, n); +#if DEBUG_FLASH + fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); +#endif write_uint32(sl->q_buf, x); stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); } @@ -334,7 +338,9 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { x &= ~FLASH_F4_CR_SNB_MASK; x |= (n << FLASH_F4_CR_SNB); x |= (1 << FLASH_F4_CR_SER); - fprintf(stdout, "SNB:%X %X\n", x, n); +#if DEBUG_FLASH + fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); +#endif write_uint32(sl->q_buf, x); stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); } @@ -393,7 +399,7 @@ void stlink_identify_device(stlink_t *sl) { (sl->q_buf[3] << 24); /* Fix chip_id for F4 */ if (((chip_id & 0xFFF) == 0x411) && (core_id == CORE_M4_R0)) { - printf("Fixing wrong chip_id for STM32F4 Rev A errata\n"); + //printf("Fixing wrong chip_id for STM32F4 Rev A errata\n"); chip_id = 0x413; } sl->chip_id=chip_id; @@ -816,17 +822,17 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ } -uint32_t calculate_sectorsize(stlink_t *sl, uint32_t flashaddr){ +uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ if(sl->chip_id == STM32F4_CHIP_ID) { uint32_t sector=calculate_F4_sectornum(flashaddr); - if (sector<4) return (0x4000); - else if(sector<5) return(0x10000); - else return(0x20000); + if (sector<4) sl->flash_pgsz=0x4000; + else if(sector<5) sl->flash_pgsz=0x10000; + else sl->flash_pgsz=0x20000; } - else return (sl->flash_pgsz); + return (sl->flash_pgsz); } -int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) +int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { /* page an addr in the page to erase */ @@ -841,13 +847,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) unlock_flash_if(sl); /* select the page to erase */ - //Page is passed to us as an addr, so calculate the actual page - uint32_t addr=page; - - page=calculate_F4_sectornum(addr); + // calculate the actual page from the address + uint32_t sector=calculate_F4_sectornum(flashaddr); - fprintf(stderr, "Erasing Sector:%u SectorSize:%u\n", page, calculate_sectorsize(sl, addr)); - write_flash_cr_snb(sl, page); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); + write_flash_cr_snb(sl, sector); /* start erase operation */ set_flash_cr_strt(sl); @@ -858,8 +862,9 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) /* relock the flash */ //todo: fails to program if this is in lock_flash(sl); - fprintf(stdout, "Erase Final CR:%X\n", read_flash_cr(sl)); - +#if DEBUG_FLASH + fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); +#endif } else if (sl->core_id == STM32L_CORE_ID) @@ -928,7 +933,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) /* write 0 to the first word of the page to be erased */ memset(sl->q_buf, 0, sizeof(uint32_t)); - stlink_write_mem32(sl, page, sizeof(uint32_t)); + stlink_write_mem32(sl, flashaddr, sizeof(uint32_t)); /* reset lock bits */ stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); @@ -948,7 +953,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) set_flash_cr_per(sl); /* select the page to erase */ - write_flash_ar(sl, page); + write_flash_ar(sl, flashaddr); /* start erase operation, reset by hw with bsy bit */ set_flash_cr_strt(sl); @@ -1068,7 +1073,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { } else { - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); + fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id); return -1; } @@ -1104,12 +1109,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned stlink_identify_device(sl); -#if 0 /* todo: use in debugging mode only */ - fprintf(stdout, "WriteFlash - addr:%x len:%x\n", addr, len); - fprintf(stdout, "CoreID:%X ChipID:%X\n", sl->core_id, sl->chip_id); -#endif - /* check addr range is inside the flash */ + stlink_calculate_pagesize(sl, addr); if (addr < sl->flash_base) { fprintf(stderr, "addr too low\n"); return -1; @@ -1128,14 +1129,20 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned } /* erase each page */ - for (off = 0; off < len; off += calculate_sectorsize(sl, addr + off) ) { - /* addr must be an addr inside the page */ + for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off) ) { + //addr must be an addr inside the page if (stlink_erase_flash_page(sl, addr + off) == -1) { fprintf(stderr, "erase_flash_page(0x%zx) == -1\n", addr + off); return -1; } } +#if 1 /* todo: use in debugging mode only */ + fprintf(stdout, "WriteFlash - Addr:0x%x len:0x%x\n", addr, len); + //fprintf(stdout, "CoreID:0x%x ChipID:0x%x\n", sl->core_id, sl->chip_id); +#endif + + if (sl->chip_id == STM32F4_CHIP_ID) { /* todo: check write operation */ @@ -1172,7 +1179,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned lock_flash(sl); #if 0 /* todo: debug mode */ - fprintf(stdout, "Final CR:%X\n", read_flash_cr(sl)); + fprintf(stdout, "Final CR:0x%x\n", read_flash_cr(sl)); #endif @@ -1262,7 +1269,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1); page = addr + off; - fprintf(stderr, "invalid write @%x(%x): %x != %x. retrying.\n", + fprintf(stderr, "invalid write @0x%x(0x%x): 0x%x != 0x%x. retrying.\n", page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0)); /* reset lock bits */ @@ -1343,7 +1350,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned if (aligned_size & (4 - 1)) aligned_size = (cmp_size + 4) & ~(4 - 1); - fprintf(stdout, "AlignedSize:%x\n", aligned_size); + fprintf(stdout, "AlignedSize:0x%x\n", aligned_size); stlink_read_mem32(sl, addr + off, aligned_size); if (memcmp(sl->q_buf, base + off, cmp_size)) @@ -1409,7 +1416,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ } else { - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); + fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id); return -1; } @@ -1441,7 +1448,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else { - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); + fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id); return -1; } diff --git a/src/stlink-common.h b/src/stlink-common.h index 2230dca83..1d9e38781 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -243,7 +243,8 @@ extern "C" { // privates, publics, the rest.... // TODO sort what is private, and what is not - int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t page); + int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); + uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); uint16_t read_uint16(const unsigned char *c, const int pt); void stlink_core_stat(stlink_t *sl); void stlink_print_data(stlink_t *sl); From b55b75c3b98f4b80334cd8fb742e06e0ebe9b981 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 23:01:03 +0000 Subject: [PATCH 0064/1435] Remove final reference to old sg/usb compilation flags --- flash/Makefile | 1 - gdbserver/Makefile | 1 - 2 files changed, 2 deletions(-) diff --git a/flash/Makefile b/flash/Makefile index dc16b62a9..412c366e5 100644 --- a/flash/Makefile +++ b/flash/Makefile @@ -1,5 +1,4 @@ CFLAGS+=-g -CFLAGS+=-DCONFIG_USE_LIBUSB=1 CFLAGS+=-DDEBUG CFLAGS+=-std=gnu99 CFLAGS+=-Wall -Wextra diff --git a/gdbserver/Makefile b/gdbserver/Makefile index c0b927e20..c81ea52b8 100644 --- a/gdbserver/Makefile +++ b/gdbserver/Makefile @@ -2,7 +2,6 @@ PRG := st-util OBJS = gdb-remote.o gdb-server.o CFLAGS+=-g -Wall -Werror -std=gnu99 -I../src -CFLAGS+=-DCONFIG_USE_LIBUSB=1 LDFLAGS=-L.. -lstlink -lusb-1.0 all: $(PRG) From 8542b23c6e899fbb0ecc7f6de27eed8133988003 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 23:32:50 +0000 Subject: [PATCH 0065/1435] Update readme, as this is about to get messy! --- README | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/README b/README index 470c52a59..28caaf878 100644 --- a/README +++ b/README @@ -1,3 +1,11 @@ +IMPORTANT SHORT TERM NOTICE: +If you are targetting F1 devices, with either stlinkv1 or v2 hardware, you +_need_ to use karlp's libwork2 branch. + +If you are targetting F4, you _need_ to use texane's master + +If you are targetting F2 or L1, please let us know how it goes! + HOWTO ===== From fd332562a79737a73c8a7e7c66b4ebbe999829be Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 15 Nov 2011 19:56:14 +0000 Subject: [PATCH 0066/1435] Fix merge problem with flash verify for F4 The F4 code had #ifdefd out the verification, as the page/sector size can be too large to read in via a single transfer. Pull the verification out to a separate function, the flash write was getting far too large anyway. --- src/stlink-common.c | 64 +++++++++++++++++++++++++++++---------------- src/stlink-common.h | 1 + 2 files changed, 43 insertions(+), 22 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 214f6c573..3b84cc689 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1148,6 +1148,46 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { return res; } +/** + * Verify addr..addr+len is binary identical to base...base+len + * @param sl stlink context + * @param address stm device address + * @param data host side buffer to check against + * @param length how much + * @return 0 for success, -ve for failure + */ +int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) { + size_t off; + if ((sl->chip_id & 0xFFF) == STM32_CHIPID_F4) { + DLOG("(FIXME)Skipping verification for F4, not enough ram (yet)\n"); + return 0; + } + ILOG("Starting verification of write complete\n"); + for (off = 0; off < length; off += sl->flash_pgsz) { + size_t aligned_size; + + /* adjust last page size */ + size_t cmp_size = sl->flash_pgsz; + if ((off + sl->flash_pgsz) > length) + cmp_size = length - off; + + aligned_size = cmp_size; + if (aligned_size & (4 - 1)) + aligned_size = (cmp_size + 4) & ~(4 - 1); + + fprintf(stdout, "AlignedSize:%#zx\n", aligned_size); + stlink_read_mem32(sl, address + off, aligned_size); + + if (memcmp(sl->q_buf, data + off, cmp_size)) { + WLOG("Verification of flash failed at offset: %zd\n", off); + return -1; + } + } + ILOG("Flash written and verified! jolly good!\n"); + return 0; + +} + int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) { size_t off; flash_loader_t fl; @@ -1370,28 +1410,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id); return -1; } - - ILOG("Starting verification of write complete\n"); - for (off = 0; off < len; off += sl->flash_pgsz) { - size_t aligned_size; - - /* adjust last page size */ - size_t cmp_size = sl->flash_pgsz; - if ((off + sl->flash_pgsz) > len) - cmp_size = len - off; - - aligned_size = cmp_size; - if (aligned_size & (4 - 1)) - aligned_size = (cmp_size + 4) & ~(4 - 1); - - fprintf(stdout, "AlignedSize:%#zx\n", aligned_size); - stlink_read_mem32(sl, addr + off, aligned_size); - - if (memcmp(sl->q_buf, base + off, cmp_size)) - return -1; - } - ILOG("Flash written and verified! jolly good!\n"); - return 0; + + return stlink_verify_write_flash(sl, addr, base, len); } /** diff --git a/src/stlink-common.h b/src/stlink-common.h index 82967d4b5..ae02961a0 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -348,6 +348,7 @@ extern "C" { int stlink_erase_flash_mass(stlink_t* sl); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length); int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); + int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length); // PUBLIC uint32_t stlink_chip_id(stlink_t *sl); From 49569ccd6bc04e7b4bcdf974433f9201fc93a337 Mon Sep 17 00:00:00 2001 From: Fabien Le Mentec Date: Sun, 20 Nov 2011 15:54:00 -0600 Subject: [PATCH 0067/1435] [update] blink_flash makefile --- example/32l_dac/Makefile | 2 +- example/blink_flash/Makefile | 18 +++++++++++++----- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/example/32l_dac/Makefile b/example/32l_dac/Makefile index 87773ef14..6c1844169 100644 --- a/example/32l_dac/Makefile +++ b/example/32l_dac/Makefile @@ -28,7 +28,7 @@ $(BIN_IMAGE): $(EXECUTABLE) $(OBJCOPY) -O binary $^ $@ $(EXECUTABLE): main.c system_stm32l1xx.c startup_stm32l1xx_md.s - $(CC) $(CFLAGS) $^ -o $@ $(LDFLAGS) + $(CC) $(CFLAGS) $^ -o $@ $(LDFLAGS) clean: rm -rf $(EXECUTABLE) diff --git a/example/blink_flash/Makefile b/example/blink_flash/Makefile index 46117311e..1696bf5f0 100644 --- a/example/blink_flash/Makefile +++ b/example/blink_flash/Makefile @@ -19,11 +19,16 @@ CFLAGS+=-ffreestanding -nostdlib -nostdinc # to run from FLASH CFLAGS+=-Wl,-T,stm32_flash.ld +PLATFORM=stm32l1xx +LIBS_STM_PATH=../libs_stm + # stm32l_discovery lib -CFLAGS+=-I../libstm32l_discovery/inc -CFLAGS+=-I../libstm32l_discovery/inc/base -CFLAGS+=-I../libstm32l_discovery/inc/core_support -CFLAGS+=-I../libstm32l_discovery/inc/device_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/base +CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM) + +LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_l1xx all: $(BIN_IMAGE) @@ -31,10 +36,13 @@ $(BIN_IMAGE): $(EXECUTABLE) $(OBJCOPY) -O binary $^ $@ $(EXECUTABLE): main.c system_stm32l1xx.c startup_stm32l1xx_md.s - $(CC) $(CFLAGS) $^ -o $@ -L../libstm32l_discovery/build -lstm32l_discovery + $(CC) $(CFLAGS) $^ -o $@ $(LDFLAGS) clean: rm -rf $(EXECUTABLE) rm -rf $(BIN_IMAGE) +write: all + sudo ../../flash/flash write ./blink.bin 0x08000000 + .PHONY: all clean From e9586c100e33fe72e4528b21768bd155a68517e2 Mon Sep 17 00:00:00 2001 From: le mentec fabien Date: Tue, 22 Nov 2011 09:39:58 -0600 Subject: [PATCH 0068/1435] [update] apply patches from marpe@mimuw.edu.pl for flash tool: verbosity, run after programm\ --- AUTHORS | 3 ++- flash/main.c | 14 +++++++++++--- 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/AUTHORS b/AUTHORS index 105e25b6b..f60ebcaa2 100644 --- a/AUTHORS +++ b/AUTHORS @@ -11,4 +11,5 @@ nelsonjm@macpod.neta ned@bike-nomad.com csamuelson@swingpal.com bravikov@gmail.com -jnosky - codegrinder69@hotmail.com \ No newline at end of file +jnosky - codegrinder69@hotmail.com +marpe@mimuw.edu.pl diff --git a/flash/main.c b/flash/main.c index 563748923..8781941cc 100644 --- a/flash/main.c +++ b/flash/main.c @@ -80,6 +80,7 @@ int main(int ac, char** av) struct opts o; int err = -1; + o.size = 0; if (get_opts(&o, ac - 1, av + 1) == -1) { printf("invalid command line\n"); @@ -89,12 +90,14 @@ int main(int ac, char** av) if (o.devname != NULL) /* stlinkv1 */ { - sl = stlink_v1_open(100); + sl = stlink_v1_open(50); + sl->verbose = 50; if (sl == NULL) goto on_error; } else /* stlinkv2 */ { - sl = stlink_open_usb(100); + sl = stlink_open_usb(50); + sl->verbose = 50; if (sl == NULL) goto on_error; } @@ -129,7 +132,12 @@ int main(int ac, char** av) err = 0; on_error: - if (sl != NULL) stlink_close(sl); + if (sl != NULL) + { + stlink_reset(sl); + stlink_run(sl); + stlink_close(sl); + } return err; } From bd1249c224ee462ea11c63e67ff95cb48b8b28ba Mon Sep 17 00:00:00 2001 From: le mentec fabien Date: Tue, 22 Nov 2011 09:54:55 -0600 Subject: [PATCH 0069/1435] [update] apply patches from marpe@mimuw.edu.pl: strict aliasing issues, busy bit waiting --- src/stlink-common.c | 35 ++++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 3b84cc689..aafd9d29f 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -122,17 +122,17 @@ uint32_t read_uint32(const unsigned char *c, const int pt) { static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t)); - return (*(uint32_t*) sl->q_buf) & 0xff; + return read_uint32(sl->q_buf, 0) & 0xff; } static inline uint32_t read_flash_wrpr(stlink_t *sl) { stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t)); - return *(uint32_t*) sl->q_buf; + return read_uint32(sl->q_buf, 0); } static inline uint32_t read_flash_obr(stlink_t *sl) { stlink_read_mem32(sl, FLASH_OBR, sizeof (uint32_t)); - return *(uint32_t*) sl->q_buf; + return read_uint32(sl->q_buf, 0); } static inline uint32_t read_flash_cr(stlink_t *sl) { @@ -143,7 +143,7 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { #if DEBUG_FLASH fprintf(stdout, "CR:0x%x\n", *(uint32_t*) sl->q_buf); #endif - return *(uint32_t*) sl->q_buf; + return read_uint32(sl->q_buf, 0); } static inline unsigned int is_flash_locked(stlink_t *sl) { @@ -269,7 +269,7 @@ static void set_flash_cr_strt(stlink_t *sl) { static inline uint32_t read_flash_acr(stlink_t *sl) { stlink_read_mem32(sl, FLASH_ACR, sizeof (uint32_t)); - return *(uint32_t*) sl->q_buf; + return read_uint32(sl->q_buf, 0); } static inline uint32_t read_flash_sr(stlink_t *sl) { @@ -278,7 +278,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { else stlink_read_mem32(sl, FLASH_SR, sizeof (uint32_t)); //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf); - return *(uint32_t*) sl->q_buf; + return read_uint32(sl->q_buf, 0); } static inline unsigned int is_flash_busy(stlink_t *sl) { @@ -969,17 +969,36 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) write_uint32(sl->q_buf, val); stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - /* wait for sr.busy to be cleared */ +#if 0 /* fix_to_be_confirmed */ + + /* wait for sr.busy to be cleared + MP: Test shows that busy bit is not set here. Perhaps, PM0062 is + wrong and we do not need to wait here for clearing the busy bit. + TEXANE: ok, if experience says so and it works for you, we comment + it. If someone has a problem, please drop an email. + */ while (1) { stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t)); if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ; } +#endif /* fix_to_be_confirmed */ + /* write 0 to the first word of the page to be erased */ memset(sl->q_buf, 0, sizeof(uint32_t)); stlink_write_mem32(sl, flashaddr, sizeof(uint32_t)); + /* MP: It is better to wait for clearing the busy bit after issuing + page erase command, even though PM0062 recommends to wait before it. + Test shows that a few iterations is performed in the following loop + before busy bit is cleared.*/ + while (1) + { + stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t)); + if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break; + } + /* reset lock bits */ stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2); @@ -1175,7 +1194,6 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, if (aligned_size & (4 - 1)) aligned_size = (cmp_size + 4) & ~(4 - 1); - fprintf(stdout, "AlignedSize:%#zx\n", aligned_size); stlink_read_mem32(sl, address + off, aligned_size); if (memcmp(sl->q_buf, data + off, cmp_size)) { @@ -1272,7 +1290,6 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned else if (sl->core_id == STM32L_CORE_ID) { /* use fast word write. todo: half page. */ - uint32_t val; #if 0 /* todo: check write operation */ From 592276c9398aec17067731327587554cf6e2861b Mon Sep 17 00:00:00 2001 From: le mentec fabien Date: Tue, 22 Nov 2011 10:04:36 -0600 Subject: [PATCH 0070/1435] [update] apply patches from marpe@mimuw.edu.pl: stlink-sg.c unused/uninitialized variables --- src/stlink-sg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 062e83dbd..50c0db505 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -143,7 +143,7 @@ static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t end uint32_t rsig = read_uint32(csw, 0); uint32_t rtag = read_uint32(csw, 4); - uint32_t residue = read_uint32(csw, 8); + /* uint32_t residue = read_uint32(csw, 8); */ #define USB_CSW_SIGNATURE 0x53425355 // 'U' 'S' 'B' 'S' (reversed) if (rsig != USB_CSW_SIGNATURE) { WLOG("status signature was invalid: %#x\n", rsig); @@ -299,7 +299,7 @@ int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, unsigned char endpoint_in, unsigned char *cbuf, unsigned int length) { int ret; int real_transferred; - int try; + int try = 0; do { ret = libusb_bulk_transfer(handle, endpoint_out, cbuf, length, &real_transferred, SG_TIMEOUT_MSEC); From 2edd0530a6d3dfc428bedc3d9628093775673389 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sat, 10 Dec 2011 17:15:48 +0100 Subject: [PATCH 0071/1435] Only call strtoul when there is an argument that strtoul can work on --- flash/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/flash/main.c b/flash/main.c index 8781941cc..39910b636 100644 --- a/flash/main.c +++ b/flash/main.c @@ -48,8 +48,8 @@ static int get_opts(struct opts* o, int ac, char** av) o->devname = av[1]; i = 1; } - - o->size = strtoul(av[i + 3], NULL, 16); + if (ac > 3) + o->size = strtoul(av[i + 3], NULL, 16); } else if (strcmp(av[0], "write") == 0) { From bcee01d7052c208e039a241c90138448b969d2ff Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sat, 10 Dec 2011 17:17:25 +0100 Subject: [PATCH 0072/1435] Chevck first for NULL before writing anything to the alloceted structure --- flash/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/flash/main.c b/flash/main.c index 39910b636..9033b17b6 100644 --- a/flash/main.c +++ b/flash/main.c @@ -91,14 +91,14 @@ int main(int ac, char** av) if (o.devname != NULL) /* stlinkv1 */ { sl = stlink_v1_open(50); - sl->verbose = 50; if (sl == NULL) goto on_error; + sl->verbose = 50; } else /* stlinkv2 */ { sl = stlink_open_usb(50); - sl->verbose = 50; if (sl == NULL) goto on_error; + sl->verbose = 50; } if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) From c1130cc3a68f158632ce0a92d3ff61b7d6795e69 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sat, 10 Dec 2011 17:59:20 +0100 Subject: [PATCH 0073/1435] Fix memory leakage pathe with no V2 device found --- src/stlink-usb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 58c4e1d33..1320831d1 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -576,9 +576,8 @@ stlink_t* stlink_open_usb(const int verbose) { slu->usb_handle = libusb_open_device_with_vid_pid(slu->libusb_ctx, USB_ST_VID, USB_STLINK_32L_PID); if (slu->usb_handle == NULL) { // TODO - free usb context too... - free(slu); WLOG("Couldn't find any ST-Link/V2 devices"); - return NULL; + goto on_error; } if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { @@ -660,6 +659,8 @@ stlink_t* stlink_open_usb(const int verbose) { return sl; on_error: + if( slu->libusb_ctx) + libusb_exit(slu->libusb_ctx); if (sl != NULL) free(sl); if (slu != NULL) free(slu); return 0; From 48b604040a78177c9695396710d75d0194935228 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sat, 10 Dec 2011 18:08:06 +0100 Subject: [PATCH 0074/1435] Fix leakage pathes for V1 --- src/stlink-sg.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 50c0db505..394417b18 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -857,6 +857,7 @@ static stlink_t* stlink_open(const int verbose) { if (slsg->usb_handle == NULL) { WLOG("Failed to find an stlink v1 by VID:PID\n"); libusb_close(slsg->usb_handle); + libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); return NULL; @@ -871,6 +872,7 @@ static stlink_t* stlink_open(const int verbose) { if (r < 0) { WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); libusb_close(slsg->usb_handle); + libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); return NULL; @@ -883,6 +885,7 @@ static stlink_t* stlink_open(const int verbose) { /* this may fail for a previous configured device */ WLOG("libusb_get_configuration()\n"); libusb_close(slsg->usb_handle); + libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); return NULL; @@ -897,6 +900,7 @@ static stlink_t* stlink_open(const int verbose) { /* this may fail for a previous configured device */ WLOG("libusb_set_configuration() failed\n"); libusb_close(slsg->usb_handle); + libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); return NULL; @@ -906,6 +910,7 @@ static stlink_t* stlink_open(const int verbose) { if (libusb_claim_interface(slsg->usb_handle, 0)) { WLOG("libusb_claim_interface() failed\n"); libusb_close(slsg->usb_handle); + libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); return NULL; From face2e7babe4046dd931a93f74eee5cb5f9a4a53 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sat, 10 Dec 2011 18:22:51 +0100 Subject: [PATCH 0075/1435] Add explicit dependancy on the stlink archive --- flash/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/flash/Makefile b/flash/Makefile index 412c366e5..cb7dcd2c2 100644 --- a/flash/Makefile +++ b/flash/Makefile @@ -13,7 +13,7 @@ NAME=flash all: $(NAME) -$(NAME): $(OBJS) +$(NAME): $(OBJS) ../libstlink.a $(CC) $(CFLAGS) -o $(NAME) $(OBJS) $(LDFLAGS) %.o: %.c From e82da443bf0f113f7fc3cad71322a69f0db22360 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sat, 10 Dec 2011 19:01:52 +0100 Subject: [PATCH 0076/1435] Print undecode chip_id too --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index aafd9d29f..ab145104c 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -457,7 +457,7 @@ int stlink_load_device_params(stlink_t *sl) { sl->sys_base = params->bootrom_base; sl->sys_size = params->bootrom_size; - ILOG("Device connected is: %s\n", params->description); + ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); // TODO make note of variable page size here..... ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n", sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, From b1e89edb578e70e4fffa83394a24d8733e78143b Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sat, 10 Dec 2011 21:27:54 +0100 Subject: [PATCH 0077/1435] More files to ignore --- .gitignore | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.gitignore b/.gitignore index c23c60a36..8e974b74b 100644 --- a/.gitignore +++ b/.gitignore @@ -11,3 +11,7 @@ flash/flash *.log example/*/*.bin example/*/*.elf +example/*/*/*.bin +example/*/*/*/*.bin +example/*/*/*.a +example/*/*/*/*.a From 28956cf2c9f52b13245d0b6a9529f7f06c972aff Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Mon, 12 Dec 2011 15:22:19 +0100 Subject: [PATCH 0078/1435] Expose JTAG NRST --- src/stlink-common.c | 5 +++++ src/stlink-common.h | 3 +++ src/stlink-sg.c | 14 ++++++++++++++ src/stlink-usb.c | 21 +++++++++++++++++++++ 4 files changed, 43 insertions(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index ab145104c..c614677d1 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -470,6 +470,11 @@ void stlink_reset(stlink_t *sl) { sl->backend->reset(sl); } +void stlink_jtag_reset(stlink_t *sl, int value) { + DLOG("*** stlink_jtag_reset ***\n"); + sl->backend->jtag_reset(sl, value); +} + void stlink_run(stlink_t *sl) { DLOG("*** stlink_run ***\n"); sl->backend->run(sl); diff --git a/src/stlink-common.h b/src/stlink-common.h index ae02961a0..b2a4adc5b 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -70,6 +70,7 @@ extern "C" { // TODO - possible poor names... #define STLINK_SWD_ENTER 0x30 #define STLINK_SWD_READCOREID 0x32 // TBD +#define STLINK_JTAG_DRIVE_NRST 0x3c // cortex m3 technical reference manual #define CM3_REG_CPUID 0xE000ED00 @@ -267,6 +268,7 @@ extern "C" { void (*exit_dfu_mode) (stlink_t * stl); void (*core_id) (stlink_t * stl); void (*reset) (stlink_t * stl); + void (*jtag_reset) (stlink_t * stl, int value); void (*run) (stlink_t * stl); void (*status) (stlink_t * stl); void (*version) (stlink_t *sl); @@ -330,6 +332,7 @@ extern "C" { void stlink_close(stlink_t *sl); uint32_t stlink_core_id(stlink_t *sl); void stlink_reset(stlink_t *sl); + void stlink_jtag_reset(stlink_t *sl, int value); void stlink_run(stlink_t *sl); void stlink_status(stlink_t *sl); void stlink_version(stlink_t *sl); diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 394417b18..0e4504c7f 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -537,6 +537,19 @@ void _stlink_sg_reset(stlink_t *sl) { stlink_stat(sl, "core reset"); } +// Arm-core reset -> halted state. + +void _stlink_sg_jtag_reset(stlink_t *sl, int value) { + struct stlink_libsg *sg = sl->backend_data; + clear_cdb(sg); + sg->cdb_cmd_blk[1] = STLINK_JTAG_DRIVE_NRST; + sg->cdb_cmd_blk[2] = (value)?0:1; + sl->q_len = 3; + sg->q_addr = 2; + stlink_q(sl); + stlink_stat(sl, "core reset"); +} + // Arm-core status: halted or running. void _stlink_sg_status(stlink_t *sl) { @@ -820,6 +833,7 @@ stlink_backend_t _stlink_sg_backend = { _stlink_sg_exit_dfu_mode, _stlink_sg_core_id, _stlink_sg_reset, + _stlink_sg_jtag_reset, _stlink_sg_run, _stlink_sg_status, _stlink_sg_version, diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 1320831d1..678e4c42b 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -348,6 +348,26 @@ void _stlink_usb_reset(stlink_t * sl) { } +void _stlink_usb_jtag_reset(stlink_t * sl, int value) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_JTAG_DRIVE_NRST; + cmd[i++] = (value)?0:1; + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { + printf("[!] send_recv\n"); + return; + } +} + + void _stlink_usb_step(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; @@ -533,6 +553,7 @@ stlink_backend_t _stlink_usb_backend = { _stlink_usb_exit_dfu_mode, _stlink_usb_core_id, _stlink_usb_reset, + _stlink_usb_jtag_reset, _stlink_usb_run, _stlink_usb_status, _stlink_usb_version, From 3e72f0b1b3c289ec2c3e7dce5f39c350b5584dbd Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 13 Dec 2011 13:27:32 +0100 Subject: [PATCH 0079/1435] Implement and expose single 32 memory read/write --- src/stlink-common.c | 11 +++++++++++ src/stlink-common.h | 7 +++++++ src/stlink-sg.c | 30 ++++++++++++++++++++++++++++++ src/stlink-usb.c | 40 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 88 insertions(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index c614677d1..8bc2a8bf0 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -529,6 +529,17 @@ void stlink_version(stlink_t *sl) { } } +uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) { + uint32_t data = sl->backend->read_debug32(sl, addr); + DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr); + return data; +} + +void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { + DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr); + sl->backend->write_debug32(sl, addr, data); +} + void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); if (len % 4 != 0) { diff --git a/src/stlink-common.h b/src/stlink-common.h index b2a4adc5b..a9834a476 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -70,6 +70,9 @@ extern "C" { // TODO - possible poor names... #define STLINK_SWD_ENTER 0x30 #define STLINK_SWD_READCOREID 0x32 // TBD +#define STLINK_JTAG_WRITEDEBUG_32BIT 0x35 +#define STLINK_JTAG_READDEBUG_32BIT 0x36 +#define STLINK_JTAG_DRIVE_NRST 0x3c #define STLINK_JTAG_DRIVE_NRST 0x3c // cortex m3 technical reference manual @@ -272,7 +275,9 @@ extern "C" { void (*run) (stlink_t * stl); void (*status) (stlink_t * stl); void (*version) (stlink_t *sl); + uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr); void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); void (*read_all_regs) (stlink_t *sl, reg * regp); @@ -336,7 +341,9 @@ extern "C" { void stlink_run(stlink_t *sl); void stlink_status(stlink_t *sl); void stlink_version(stlink_t *sl); + uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr); void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); + void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); void stlink_read_all_regs(stlink_t *sl, reg *regp); diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 0e4504c7f..197d59b29 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -805,6 +805,34 @@ void _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { stlink_print_data(sl); } +// Write one DWORD data to memory + +void _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { + struct stlink_libsg *sg = sl->backend_data; + clear_cdb(sg); + sg->cdb_cmd_blk[1] = STLINK_JTAG_WRITEDEBUG_32BIT; + // 2-5: addr + write_uint32(sg->cdb_cmd_blk + 2, addr); + write_uint32(sg->cdb_cmd_blk + 6, data); + sl->q_len = 2; + stlink_q(sl); + +} + +// Read one DWORD data from memory + +uint32_t _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr) { + struct stlink_libsg *sg = sl->backend_data; + clear_cdb(sg); + sg->cdb_cmd_blk[1] = STLINK_JTAG_READDEBUG_32BIT; + // 2-5: addr + write_uint32(sg->cdb_cmd_blk + 2, addr); + sl->q_len = 8; + stlink_q(sl); + + return read_uint32(sl->q_buf, 4); +} + // Exit the jtag or swd mode and enter the mass mode. void _stlink_sg_exit_debug_mode(stlink_t *stl) { @@ -837,7 +865,9 @@ stlink_backend_t _stlink_sg_backend = { _stlink_sg_run, _stlink_sg_status, _stlink_sg_version, + _stlink_sg_read_debug32, _stlink_sg_read_mem32, + _stlink_sg_write_debug32, _stlink_sg_write_mem32, _stlink_sg_write_mem8, _stlink_sg_read_all_regs, diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 678e4c42b..4f8debc94 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -189,6 +189,44 @@ void _stlink_usb_version(stlink_t *sl) { } } +uint32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const rdata = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + const int rep_len = 8; + + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_JTAG_READDEBUG_32BIT; + write_uint32(&cmd[i], addr); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); + if (size == -1) { + printf("[!] send_recv\n"); + return; + } + return read_uint32(rdata, 4); +} + +void _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const rdata = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + const int rep_len = 2; + + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_JTAG_WRITEDEBUG_32BIT; + write_uint32(&cmd[i], addr); + write_uint32(&cmd[i + 4], data); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); + if (size == -1) { + printf("[!] send_recv\n"); + return; + } +} + void _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; @@ -557,7 +595,9 @@ stlink_backend_t _stlink_usb_backend = { _stlink_usb_run, _stlink_usb_status, _stlink_usb_version, + _stlink_usb_read_debug32, _stlink_usb_read_mem32, + _stlink_usb_write_debug32, _stlink_usb_write_mem32, _stlink_usb_write_mem8, _stlink_usb_read_all_regs, From 5eda4566d617fedd2a9d3020ddae06b394d08a5f Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 13 Dec 2011 17:48:54 +0100 Subject: [PATCH 0080/1435] Determine the device parameters explicit after running stlink_reset(). Otherwise a sleeping device (WFI) doesn't return the parameters. --- flash/main.c | 1 + src/stlink-sg.c | 1 - src/stlink-usb.c | 1 - 3 files changed, 1 insertion(+), 2 deletions(-) diff --git a/flash/main.c b/flash/main.c index 9033b17b6..609a6f7d3 100644 --- a/flash/main.c +++ b/flash/main.c @@ -108,6 +108,7 @@ int main(int ac, char** av) stlink_enter_swd_mode(sl); stlink_reset(sl); + stlink_load_device_params(sl); if (o.do_read == 0) /* write */ { diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 197d59b29..991bc878b 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -1025,7 +1025,6 @@ stlink_t* stlink_v1_open(const int verbose) { } // by now, it _must_ be fully open and in a useful mode.... stlink_enter_swd_mode(sl); - stlink_load_device_params(sl); ILOG("Successfully opened a stlink v1 debugger\n"); return sl; } diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 4f8debc94..f0a469511 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -702,7 +702,6 @@ stlink_t* stlink_open_usb(const int verbose) { } stlink_version(sl); - stlink_load_device_params(sl); error = 0; From 9ef6d28cb5751c0cf589136181569f585059a8bc Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 13 Dec 2011 18:41:07 +0100 Subject: [PATCH 0081/1435] Modify shutdown seqeunce. Now a F107 in sleep mode reacts on the reset pin after running stlink --- flash/main.c | 3 +-- src/stlink-common.c | 1 + src/stlink-common.h | 5 +++++ 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/flash/main.c b/flash/main.c index 609a6f7d3..106e52c29 100644 --- a/flash/main.c +++ b/flash/main.c @@ -135,8 +135,7 @@ int main(int ac, char** av) on_error: if (sl != NULL) { - stlink_reset(sl); - stlink_run(sl); + stlink_exit_debug_mode(sl); stlink_close(sl); } diff --git a/src/stlink-common.c b/src/stlink-common.c index 8bc2a8bf0..74c5bcc7c 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -359,6 +359,7 @@ void stlink_close(stlink_t *sl) { void stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); + stlink_write_debug32(sl, DHCSR, DBGKEY); sl->backend->exit_debug_mode(sl); } diff --git a/src/stlink-common.h b/src/stlink-common.h index a9834a476..a1442f366 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -112,6 +112,11 @@ extern "C" { /* using chip id for F4 ident, since core id is same as F1 */ #define STM32F4_CHIP_ID 0x413 +/* Cortex™-M3 Technical Reference Manual */ +/* Debug Halting Control and Status Register */ +#define DHCSR 0xe000edf0 +#define DBGKEY 0xa05f0000 + /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 From 03e745140d9f599801df2b779f051f7f23586b65 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 13 Dec 2011 19:56:10 +0100 Subject: [PATCH 0082/1435] Use the single WORD memory access --- src/stlink-common.c | 171 ++++++++++++++++---------------------------- 1 file changed, 62 insertions(+), 109 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 74c5bcc7c..79650ede5 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -121,29 +121,27 @@ uint32_t read_uint32(const unsigned char *c, const int pt) { } static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { - stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t)); - return read_uint32(sl->q_buf, 0) & 0xff; + return stlink_read_debug32(sl, FLASH_WRPR) & 0xff; } static inline uint32_t read_flash_wrpr(stlink_t *sl) { - stlink_read_mem32(sl, FLASH_WRPR, sizeof (uint32_t)); - return read_uint32(sl->q_buf, 0); + return stlink_read_debug32(sl, FLASH_WRPR); } static inline uint32_t read_flash_obr(stlink_t *sl) { - stlink_read_mem32(sl, FLASH_OBR, sizeof (uint32_t)); - return read_uint32(sl->q_buf, 0); + return stlink_read_debug32(sl, FLASH_OBR); } static inline uint32_t read_flash_cr(stlink_t *sl) { + uint32_t res; if(sl->chip_id==STM32F4_CHIP_ID) - stlink_read_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); + res = stlink_read_debug32(sl, FLASH_F4_CR); else - stlink_read_mem32(sl, FLASH_CR, sizeof (uint32_t)); + res = stlink_read_debug32(sl, FLASH_CR); #if DEBUG_FLASH - fprintf(stdout, "CR:0x%x\n", *(uint32_t*) sl->q_buf); + fprintf(stdout, "CR:0x%x\n", res); #endif - return read_uint32(sl->q_buf, 0); + return res; } static inline unsigned int is_flash_locked(stlink_t *sl) { @@ -161,16 +159,12 @@ static void unlock_flash(stlink_t *sl) { the FPEC block until next reset. */ if(sl->chip_id==STM32F4_CHIP_ID) { - write_uint32(sl->q_buf, FLASH_KEY1); - stlink_write_mem32(sl, FLASH_F4_KEYR, sizeof (uint32_t)); - write_uint32(sl->q_buf, FLASH_KEY2); - stlink_write_mem32(sl, FLASH_F4_KEYR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); + stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); } else { - write_uint32(sl->q_buf, FLASH_KEY1); - stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t)); - write_uint32(sl->q_buf, FLASH_KEY2); - stlink_write_mem32(sl, FLASH_KEYR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1); + stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2); } } @@ -192,14 +186,12 @@ static int unlock_flash_if(stlink_t *sl) { static void lock_flash(stlink_t *sl) { if(sl->chip_id==STM32F4_CHIP_ID) { const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_F4_CR, n); } else { /* write to 1 only. reset by hw at unlock sequence */ const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } } @@ -208,47 +200,40 @@ static void set_flash_cr_pg(stlink_t *sl) { if(sl->chip_id==STM32F4_CHIP_ID) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_CR_PG); - write_uint32(sl->q_buf, x); - stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_F4_CR, x); } else { const uint32_t n = 1 << FLASH_CR_PG; - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } } static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); - write_uint32(sl->q_buf, n); if(sl->chip_id==STM32F4_CHIP_ID) - stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_F4_CR, n); else - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } static void set_flash_cr_per(stlink_t *sl) { const uint32_t n = 1 << FLASH_CR_PER; - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } static void set_flash_cr_mer(stlink_t *sl) { const uint32_t n = 1 << FLASH_CR_MER; - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_MER); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } static void set_flash_cr_strt(stlink_t *sl) { @@ -256,29 +241,27 @@ static void set_flash_cr_strt(stlink_t *sl) { { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_F4_CR_STRT); - write_uint32(sl->q_buf, x); - stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_F4_CR, x); } else { /* assume come on the flash_cr_per path */ const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_CR, n); } } static inline uint32_t read_flash_acr(stlink_t *sl) { - stlink_read_mem32(sl, FLASH_ACR, sizeof (uint32_t)); - return read_uint32(sl->q_buf, 0); + return stlink_read_debug32(sl, FLASH_ACR); } static inline uint32_t read_flash_sr(stlink_t *sl) { + uint32_t res; if(sl->chip_id==STM32F4_CHIP_ID) - stlink_read_mem32(sl, FLASH_F4_SR, sizeof (uint32_t)); + res = stlink_read_debug32(sl, FLASH_F4_SR); else - stlink_read_mem32(sl, FLASH_SR, sizeof (uint32_t)); + res = stlink_read_debug32(sl, FLASH_SR); //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf); - return read_uint32(sl->q_buf, 0); + return res; } static inline unsigned int is_flash_busy(stlink_t *sl) { @@ -300,8 +283,7 @@ static inline unsigned int is_flash_eop(stlink_t *sl) { static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) { const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP); - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_SR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_SR, n); } static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) { @@ -311,8 +293,7 @@ static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) { } static inline void write_flash_ar(stlink_t *sl, uint32_t n) { - write_uint32(sl->q_buf, n); - stlink_write_mem32(sl, FLASH_AR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_AR, n); } static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) { @@ -322,8 +303,7 @@ static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) { #if DEBUG_FLASH fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); #endif - write_uint32(sl->q_buf, x); - stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_F4_CR, x); } @@ -335,8 +315,7 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { #if DEBUG_FLASH fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); #endif - write_uint32(sl->q_buf, x); - stlink_write_mem32(sl, FLASH_F4_CR, sizeof (uint32_t)); + stlink_write_debug32(sl, FLASH_F4_CR, x); } #if 0 /* todo */ @@ -935,14 +914,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) uint32_t val; /* disable pecr protection */ - write_uint32(sl->q_buf, 0x89abcdef); - stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t)); - write_uint32(sl->q_buf, 0x02030405); - stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); /* check pecr.pelock is cleared */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); if (val & (1 << 0)) { WLOG("pecr.pelock not clear (%#x)\n", val); @@ -950,14 +926,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } /* unlock program memory */ - write_uint32(sl->q_buf, 0x8c9daebf); - stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t)); - write_uint32(sl->q_buf, 0x13141516); - stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); /* check pecr.prglock is cleared */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); if (val & (1 << 1)) { WLOG("pecr.prglock not clear (%#x)\n", val); @@ -966,14 +939,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) /* unused: unlock the option byte block */ #if 0 - write_uint32(sl->q_buf, 0xfbead9c8); - stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t)); - write_uint32(sl->q_buf, 0x24252627); - stlink_write_mem32(sl, STM32L_FLASH_OPTKEYR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8); + stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627); /* check pecr.optlock is cleared */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); if (val & (1 << 2)) { fprintf(stderr, "pecr.prglock not clear\n"); @@ -983,8 +953,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) /* set pecr.{erase,prog} */ val |= (1 << 9) | (1 << 3); - write_uint32(sl->q_buf, val); - stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); #if 0 /* fix_to_be_confirmed */ @@ -994,33 +963,27 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) TEXANE: ok, if experience says so and it works for you, we comment it. If someone has a problem, please drop an email. */ - while (1) + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { - stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t)); - if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ; } #endif /* fix_to_be_confirmed */ /* write 0 to the first word of the page to be erased */ - memset(sl->q_buf, 0, sizeof(uint32_t)); - stlink_write_mem32(sl, flashaddr, sizeof(uint32_t)); + stlink_write_mem32(sl, flashaddr, 0); /* MP: It is better to wait for clearing the busy bit after issuing page erase command, even though PM0062 recommends to wait before it. Test shows that a few iterations is performed in the following loop before busy bit is cleared.*/ - while (1) + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { - stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t)); - if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break; } /* reset lock bits */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2); - write_uint32(sl->q_buf, val); - stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR) + | (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); } else if (sl->core_id == STM32VL_CORE_ID) { @@ -1318,28 +1281,22 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned #endif /* todo: check write operation */ /* disable pecr protection */ - write_uint32(sl->q_buf, 0x89abcdef); - stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t)); - write_uint32(sl->q_buf, 0x02030405); - stlink_write_mem32(sl, STM32L_FLASH_PEKEYR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); /* check pecr.pelock is cleared */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); if (val & (1 << 0)) { fprintf(stderr, "pecr.pelock not clear\n"); return -1; } /* unlock program memory */ - write_uint32(sl->q_buf, 0x8c9daebf); - stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t)); - write_uint32(sl->q_buf, 0x13141516); - stlink_write_mem32(sl, STM32L_FLASH_PRGKEYR, sizeof(uint32_t)); + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); /* check pecr.prglock is cleared */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); if (val & (1 << 1)) { fprintf(stderr, "pecr.prglock not clear\n"); return -1; @@ -1361,9 +1318,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned stlink_write_mem32(sl, addr + off, sizeof(uint32_t)); /* wait for sr.busy to be cleared */ - while (1) { - stlink_read_mem32(sl, STM32L_FLASH_SR, sizeof(uint32_t)); - if ((read_uint32(sl->q_buf, 0) & (1 << 0)) == 0) break ; + while (stlink_read_debug32(sl, STM32L_FLASH_SR & (1 << 0)) != 0) { } #if 0 /* todo: check redo write operation */ @@ -1391,10 +1346,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0)); /* reset lock bits */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2); - write_uint32(sl->q_buf, val); - stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR) + | (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); stlink_erase_flash_page(sl, page); @@ -1407,10 +1361,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned #endif /* todo: check redo write operation */ } /* reset lock bits */ - stlink_read_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2); - write_uint32(sl->q_buf, val); - stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR) + | (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); } else if (sl->core_id == STM32VL_CORE_ID) { ILOG("Starting Flash write for VL core id\n"); /* flash loader initialization */ From 9953efb763459b201f731f330a943536182c4f05 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 13 Dec 2011 20:35:32 +0100 Subject: [PATCH 0083/1435] Use the single word accesses in the flash inner loop too. We first swap the data, then the access routine swaps the data again, but cycles are cheep and so don't need another access function --- src/stlink-common.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 79650ede5..bec79c327 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1240,6 +1240,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned #define PROGRESS_CHUNK_SIZE 0x1000 /* write a word in program memory */ for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; if (sl->verbose >= 1) { if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) { /* show progress. writing procedure is slow @@ -1250,8 +1251,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned } } - memcpy(sl->q_buf, (const void*)(base + off), sizeof(uint32_t)); - stlink_write_mem32(sl, addr + off, sizeof(uint32_t)); + write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); + stlink_write_debug32(sl, addr + off, data); /* wait for sr.busy to be cleared */ wait_flash_busy(sl); @@ -1304,6 +1305,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned /* write a word in program memory */ for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; if (sl->verbose >= 1) { if ((off & (sl->flash_pgsz - 1)) == 0) { /* show progress. writing procedure is slow @@ -1314,8 +1316,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned } } - memcpy(sl->q_buf, (const void*)(base + off), sizeof(uint32_t)); - stlink_write_mem32(sl, addr + off, sizeof(uint32_t)); + write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); + stlink_write_mem32(sl, addr + off, data); /* wait for sr.busy to be cleared */ while (stlink_read_debug32(sl, STM32L_FLASH_SR & (1 << 0)) != 0) { @@ -1324,8 +1326,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned #if 0 /* todo: check redo write operation */ /* check written bytes. todo: should be on a per page basis. */ - stlink_read_mem32(sl, addr + off, sizeof(uint32_t)); - if (memcmp(sl->q_buf, base + off, sizeof(uint32_t))) { + data = stlink_read_debug32(sl, addr + off); + if (data == *(uint32_t*)(base + off)) { /* re erase the page and redo the write operation */ uint32_t page; uint32_t val; From 62ea3faf1e1d51823ed10ea985f3f36040e0d512 Mon Sep 17 00:00:00 2001 From: Fabien Le Mentec Date: Fri, 16 Dec 2011 14:07:17 -0600 Subject: [PATCH 0084/1435] [add] stlinkv1_macosx_driver from marco.cassinerio@gmail.com --- stlinkv1_macosx_driver/Makefile | 57 ++++++++++++++++++++++++++++++ stlinkv1_macosx_driver/README | 23 ++++++++++++ stlinkv1_macosx_driver/osx.tar.gz | Bin 0 -> 23264 bytes 3 files changed, 80 insertions(+) create mode 100644 stlinkv1_macosx_driver/Makefile create mode 100644 stlinkv1_macosx_driver/README create mode 100644 stlinkv1_macosx_driver/osx.tar.gz diff --git a/stlinkv1_macosx_driver/Makefile b/stlinkv1_macosx_driver/Makefile new file mode 100644 index 000000000..9947ff672 --- /dev/null +++ b/stlinkv1_macosx_driver/Makefile @@ -0,0 +1,57 @@ +# make ... for both stlink v1 and stlink v2 support +## +VPATH=src + +SOURCES_LIB=stlink-common.c stlink-usb.c stlink-sg.c uglylogging.c +OBJS_LIB=$(SOURCES_LIB:.c=.o) +TEST_PROGRAMS=test_usb test_sg +LDFLAGS=-L. -lstlink -lusb-1.0 + +CFLAGS+=-g +CFLAGS+=-DDEBUG=1 +CFLAGS+=-std=gnu99 +CFLAGS+=-Wall -Wextra + + +LIBRARY=libstlink.a + +all: $(LIBRARY) flash gdbserver $(TEST_PROGRAMS) + +$(LIBRARY): $(OBJS_LIB) + @echo "objs are $(OBJS_LIB)" + $(AR) -cr $@ $^ + @echo "done making library" + + +test_sg: test_sg.o $(LIBRARY) + @echo "building test_sg" + $(CC) test_sg.o $(LDFLAGS) -o $@ + +test_usb: test_usb.o $(LIBRARY) + @echo "building test_usb" + $(CC) test_usb.o $(LDFLAGS) -o $@ + @echo "done linking" + +%.o: %.c + @echo "building $^ into $@" + $(CC) $(CFLAGS) -c $^ -o $@ + @echo "done compiling" + +clean: + rm -rf $(OBJS_LIB) + rm -rf $(LIBRARY) + rm -rf test_usb* + rm -rf test_sg* + $(MAKE) -C flash clean + $(MAKE) -C gdbserver clean + +flash: + $(MAKE) -C flash + +gdbserver: + $(MAKE) -C gdbserver CONFIG_USE_LIBSG="$(CONFIG_USE_LIBSG)" + +osx_stlink_shield: + ./osx/install.sh + +.PHONY: clean all flash gdbserver diff --git a/stlinkv1_macosx_driver/README b/stlinkv1_macosx_driver/README new file mode 100644 index 000000000..23bbd860c --- /dev/null +++ b/stlinkv1_macosx_driver/README @@ -0,0 +1,23 @@ +from: marco.cassinerio@gmail.com +to: texane@gmail.com + +Hi, + +i managed to get the stlink v1 working under os x and i would like to share the solution so maybe you can +add it in your package. +The problem is that os x claims the device as scsi and libusb won't be able to connect to it. +I've created what is called a codeless driver which claims the device and has a higher priority then the +default apple mass storage driver, so the device can be accessed through libusb. + +I tested this codeless driver under OS X 10.6.8 and 10.7.2. I assume it works with any 10.6.x and 10.7.x +version as well. + +Attached to this mail you'll find the osx folder with the source code of the driver, both drivers (for +10.6.x and 10.7.x), an install.sh script and the modified Makefile, i only added a line at the end which +invoke the install.sh. + +To install the driver the user have only to do: + +sudo make osx_stlink_shield + +no reboot required. \ No newline at end of file diff --git a/stlinkv1_macosx_driver/osx.tar.gz b/stlinkv1_macosx_driver/osx.tar.gz new file mode 100644 index 0000000000000000000000000000000000000000..6e7bb275ba87719974b35d6ddb051c74b6cb914e GIT binary patch literal 23264 zcmZs>V|ZrGx-A^DW81dvj%~YR+qP}n>U3-lYNv_#Xiqk4*`8HO{LITbKC0$6rKEj^3O$5fJ@t&8?=$5ENR(fnbHU zUd_<5Nr|D6r0o!ul0U5$g_d^b4Cf0LpAiYk?~0|QOYtr2Nx_G=_*^Wmr~IY}f?Hk0 zk2$}w3-{_7kv%p zeq8lXk1y0P^*J-f!MhwFhusYm%6(je`ZoSSx#K$cVG<7;&bR_hY>ST)LJ1>^WU@#d zE{GCBy{_V!5ZXE2y=;&gBhV>f8{%o1+7B#>)47}KcK+SX<2ps3>mBG~d;C%Hd>lz# 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zzn_%jatQw;JFpYlNQwUtyQL8S>oq~jSQ_u=a^xJ3jX%;N>%cfwUPY!*q(Et1BuNC@UE^INp zRj|>o*9iJ6hI)Z;K12U?3cW(RutU&G1g8~-2>%WGaj{f?DzH8{0 zC3<#R$lZw}l(_jXKVtqjX8qsO|M>jJ8svZLb^gfu|0iAl-^2e$$^WwPzb@5|?f>Qc zPvrkY=6~b%|5SN7$baPj=lg$-Q}X<8p8x&+^1u0xn{S@{&3D}VB$?lQ$IZ`NSp2_- z%>Od^|KR`0x&MERl8yg|=YQGwFIJ^I{yR!Jg#Y)+|Hkp(&HuXmuS@kj{yR#^^S^n? jOJ4Glm%QX9FL}vJUhPrLjd4{D&t0O$h%G+`s^ literal 0 HcmV?d00001 From 8e1a1afa938a961fa401d6ab60c545cb81a52136 Mon Sep 17 00:00:00 2001 From: Fabien Le Mentec Date: Fri, 16 Dec 2011 14:07:38 -0600 Subject: [PATCH 0085/1435] [update] AUTHOR --- AUTHORS | 1 + 1 file changed, 1 insertion(+) diff --git a/AUTHORS b/AUTHORS index f60ebcaa2..8153669c7 100644 --- a/AUTHORS +++ b/AUTHORS @@ -13,3 +13,4 @@ csamuelson@swingpal.com bravikov@gmail.com jnosky - codegrinder69@hotmail.com marpe@mimuw.edu.pl +marco.cassinerio@gmail.com From 49238681e4d98a7254747a139d537ba07efcba13 Mon Sep 17 00:00:00 2001 From: Fabien Le Mentec Date: Fri, 16 Dec 2011 14:28:15 -0600 Subject: [PATCH 0086/1435] [update] stlinkv1_macosx_driver/README --- stlinkv1_macosx_driver/README | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/stlinkv1_macosx_driver/README b/stlinkv1_macosx_driver/README index 23bbd860c..adf3cca87 100644 --- a/stlinkv1_macosx_driver/README +++ b/stlinkv1_macosx_driver/README @@ -16,8 +16,10 @@ Attached to this mail you'll find the osx folder with the source code of the dri 10.6.x and 10.7.x), an install.sh script and the modified Makefile, i only added a line at the end which invoke the install.sh. -To install the driver the user have only to do: +First, unpack the osx.tar.gz contents: +tar xzvf osx.tar.gz +Then, install the driver using: sudo make osx_stlink_shield no reboot required. \ No newline at end of file From fba79be3b47738bdc8866a86c027765f1ab99a87 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sun, 18 Dec 2011 15:03:51 +0100 Subject: [PATCH 0087/1435] Page erase for STM32L needs a real write to lowest address with 0. stink_write_mem(.., ..,0) is undedined --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index bec79c327..f89159a21 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -970,7 +970,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) #endif /* fix_to_be_confirmed */ /* write 0 to the first word of the page to be erased */ - stlink_write_mem32(sl, flashaddr, 0); + stlink_write_debug32(sl, flashaddr, 0); /* MP: It is better to wait for clearing the busy bit after issuing page erase command, even though PM0062 recommends to wait before it. From 5652cee37d2742714c6cb54983718cf5891e5c80 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sun, 18 Dec 2011 15:21:26 +0100 Subject: [PATCH 0088/1435] Fix a wrong placed brace and and a not replaced stlink_write_mem32() that keep STM32L from programming --- src/stlink-common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index f89159a21..74d03f548 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1317,10 +1317,10 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned } write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); - stlink_write_mem32(sl, addr + off, data); + stlink_write_debug32(sl, addr + off, data); /* wait for sr.busy to be cleared */ - while (stlink_read_debug32(sl, STM32L_FLASH_SR & (1 << 0)) != 0) { + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { } #if 0 /* todo: check redo write operation */ From 7f0e9ada38e6e15fc8f415ba841001e74ef3e249 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sun, 18 Dec 2011 15:40:09 +0100 Subject: [PATCH 0089/1435] Replace remaining _mem32 single word accesses with _debug32 --- src/stlink-common.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 74d03f548..632c222ef 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -368,9 +368,7 @@ uint32_t stlink_core_id(stlink_t *sl) { } uint32_t stlink_chip_id(stlink_t *sl) { - stlink_read_mem32(sl, 0xE0042000, 4); - uint32_t chip_id = sl->q_buf[0] | (sl->q_buf[1] << 8) | (sl->q_buf[2] << 16) | - (sl->q_buf[3] << 24); + uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000); return chip_id; } @@ -380,8 +378,7 @@ uint32_t stlink_chip_id(stlink_t *sl) { * @param cpuid pointer to the result object */ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { - stlink_read_mem32(sl, CM3_REG_CPUID, 4); - uint32_t raw = read_uint32(sl->q_buf, 0); + uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID); cpuid->implementer_id = (raw >> 24) & 0x7f; cpuid->variant = (raw >> 20) & 0xf; cpuid->part = (raw >> 4) & 0xfff; @@ -428,8 +425,7 @@ int stlink_load_device_params(stlink_t *sl) { } else if ((chip_id & 0xFFF) == STM32_CHIPID_F4) { sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID } else { - stlink_read_mem32(sl, params->flash_size_reg, 4); - uint32_t flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8); + uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff; sl->flash_size = flash_size * 1024; } sl->flash_pgsz = params->flash_pagesize; From 6f194ad388fedf287a6200ea7efb16c4118ca4c1 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sun, 18 Dec 2011 16:34:16 +0100 Subject: [PATCH 0090/1435] Ignore NULL bytes at flash end when reading --- src/stlink-common.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index 632c222ef..fac7b685c 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -803,6 +803,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) int error = -1; size_t off; + int num_zero = 0; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -814,6 +815,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) for (off = 0; off < size; off += 1024) { size_t read_size = 1024; size_t rounded_size; + size_t index; if ((off + read_size) > size) read_size = size - off; @@ -824,12 +826,21 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) stlink_read_mem32(sl, addr + off, rounded_size); + for(index = 0; index < read_size; index ++) { + if (sl->q_buf[index] == 0) + num_zero ++; + else + num_zero = 0; + } if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) { fprintf(stderr, "write() != read_size\n"); goto on_error; } } + /* Ignore NULL Bytes at end of file */ + ftruncate(fd, size - num_zero); + /* success */ error = 0; From 379fcb3c614d540e2d854700d77c80268b207b3f Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sun, 18 Dec 2011 16:53:16 +0100 Subject: [PATCH 0091/1435] Also ignore ZEROs at end of file when writing --- src/stlink-common.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index fac7b685c..937bf8296 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1420,11 +1420,22 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ int err; + unsigned int num_zero = 0, index; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { WLOG("map_file() == -1\n"); return -1; } + for(index = 0; index < mf.len; index ++) { + if (mf.base[index] == 0) + num_zero ++; + else + num_zero = 0; + } + if(num_zero != 0) { + ILOG("Ignoring %d bytes of Zeros at end of file\n",num_zero); + mf.len -= num_zero; + } err = stlink_write_flash(sl, addr, mf.base, mf.len); unmap_file(&mf); return err; From 6ab0eb83becbe28ea3f97d52b6e5fef39145f08a Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sun, 18 Dec 2011 18:47:21 +0100 Subject: [PATCH 0092/1435] While L1 has empty flash cell erased to zero, at least F1/F4 are erased to 0xff. --- src/stlink-common.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 937bf8296..8493c4ce2 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -803,7 +803,8 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) int error = -1; size_t off; - int num_zero = 0; + int num_empty = 0; + unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -827,10 +828,10 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) stlink_read_mem32(sl, addr + off, rounded_size); for(index = 0; index < read_size; index ++) { - if (sl->q_buf[index] == 0) - num_zero ++; + if (sl->q_buf[index] == erased_pattern) + num_empty ++; else - num_zero = 0; + num_empty = 0; } if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) { fprintf(stderr, "write() != read_size\n"); @@ -839,7 +840,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) } /* Ignore NULL Bytes at end of file */ - ftruncate(fd, size - num_zero); + ftruncate(fd, size - num_empty); /* success */ error = 0; @@ -1420,21 +1421,22 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ int err; - unsigned int num_zero = 0, index; + unsigned int num_empty = 0, index; + unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { WLOG("map_file() == -1\n"); return -1; } for(index = 0; index < mf.len; index ++) { - if (mf.base[index] == 0) - num_zero ++; + if (mf.base[index] == erased_pattern) + num_empty ++; else - num_zero = 0; + num_empty = 0; } - if(num_zero != 0) { - ILOG("Ignoring %d bytes of Zeros at end of file\n",num_zero); - mf.len -= num_zero; + if(num_empty != 0) { + ILOG("Ignoring %d bytes of Zeros at end of file\n",num_empty); + mf.len -= num_empty; } err = stlink_write_flash(sl, addr, mf.base, mf.len); unmap_file(&mf); From 92cdf49e287dfb483f046cae4edc2afa4ceecaab Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sun, 18 Dec 2011 19:03:58 +0100 Subject: [PATCH 0093/1435] Clip flash read request to maximum flash size --- src/stlink-common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index 8493c4ce2..b49e21ab0 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -812,6 +812,9 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) return -1; } + if (size > sl->flash_size) + size = sl->flash_size; + /* do the copy by 1k blocks */ for (off = 0; off < size; off += 1024) { size_t read_size = 1024; From da8f7b1a6aed42b7535db1eabe64c274bbb815a2 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sun, 18 Dec 2011 19:13:46 +0100 Subject: [PATCH 0094/1435] If no read size is given, read the whole flash --- src/stlink-common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index b49e21ab0..77ab98d02 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -812,6 +812,9 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) return -1; } + if (size <1) + size = sl->flash_size; + if (size > sl->flash_size) size = sl->flash_size; From 1785fd73c58b27a5732928398aa4a528fbce96ad Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sun, 18 Dec 2011 19:24:32 +0100 Subject: [PATCH 0095/1435] Add a TODO to check for Supply Voltage before setting F4 paralleisme to 32 bits --- src/stlink-common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index 77ab98d02..5a5131424 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1245,6 +1245,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned /* First unlock the cr */ unlock_flash_if(sl); + /* TODO: Check that Voltage range is 2.7 - 3.6 V */ /* set parallelisim to 32 bit*/ write_flash_cr_psiz(sl, 2); From 82c638ed83f69e36439763c0e48074829178a24b Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sun, 18 Dec 2011 21:44:40 +0100 Subject: [PATCH 0096/1435] For gdbserver, use the same initialization sequence like for flashing --- gdbserver/gdb-server.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 6033040a3..6961cdcce 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -160,6 +160,8 @@ int main(int argc, char** argv) { break; } + stlink_reset(sl); + stlink_load_device_params(sl); printf("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); sl->verbose=0; From 7eb080490ce34e3daf6e0ab10743113acbc5a635 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sun, 18 Dec 2011 23:35:20 +0100 Subject: [PATCH 0097/1435] Move reset/load_param in the open functions, as requested by Karl --- flash/main.c | 3 --- gdbserver/gdb-server.c | 2 -- src/stlink-sg.c | 2 ++ src/stlink-usb.c | 2 ++ 4 files changed, 4 insertions(+), 5 deletions(-) diff --git a/flash/main.c b/flash/main.c index 106e52c29..d61b22bd0 100644 --- a/flash/main.c +++ b/flash/main.c @@ -107,9 +107,6 @@ int main(int ac, char** av) if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); - stlink_reset(sl); - stlink_load_device_params(sl); - if (o.do_read == 0) /* write */ { err = stlink_fwrite_flash(sl, o.filename, o.addr); diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 6961cdcce..6033040a3 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -160,8 +160,6 @@ int main(int argc, char** argv) { break; } - stlink_reset(sl); - stlink_load_device_params(sl); printf("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); sl->verbose=0; diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 991bc878b..e45fe48ed 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -985,6 +985,8 @@ stlink_t* stlink_v1_open_inner(const int verbose) { return NULL; } + stlink_reset(sl); + stlink_load_device_params(sl); stlink_version(sl); if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { ugly_log(UERROR, LOG_TAG, diff --git a/src/stlink-usb.c b/src/stlink-usb.c index f0a469511..04f0b2cbe 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -701,6 +701,8 @@ stlink_t* stlink_open_usb(const int verbose) { stlink_enter_swd_mode(sl); } + stlink_reset(sl); + stlink_load_device_params(sl); stlink_version(sl); error = 0; From 40c9d08c6072237b1fb0a8bc86668de81d9068b8 Mon Sep 17 00:00:00 2001 From: Friedrich Beckmann Date: Tue, 3 Jan 2012 23:52:44 +0100 Subject: [PATCH 0098/1435] moved the device parameter loading at the end of initialization for V1 devices- fixed the problem of non working V1 devices --- src/stlink-sg.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index e45fe48ed..3d4a9b798 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -985,8 +985,6 @@ stlink_t* stlink_v1_open_inner(const int verbose) { return NULL; } - stlink_reset(sl); - stlink_load_device_params(sl); stlink_version(sl); if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { ugly_log(UERROR, LOG_TAG, @@ -1016,6 +1014,7 @@ stlink_t* stlink_v1_open_inner(const int verbose) { "WTF? successfully opened, but unable to read version details. BROKEN!\n"); return NULL; } + return sl; } @@ -1027,6 +1026,9 @@ stlink_t* stlink_v1_open(const int verbose) { } // by now, it _must_ be fully open and in a useful mode.... stlink_enter_swd_mode(sl); + /* Now we are ready to read the parameters */ + stlink_reset(sl); + stlink_load_device_params(sl); ILOG("Successfully opened a stlink v1 debugger\n"); return sl; } From 8e5b2b51bfa4e422c43b6862db7413a7d5b14fd5 Mon Sep 17 00:00:00 2001 From: Friedrich Beckmann Date: Tue, 3 Jan 2012 23:58:01 +0100 Subject: [PATCH 0099/1435] Added the library to the list of dependencies as in flash --- gdbserver/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbserver/Makefile b/gdbserver/Makefile index c81ea52b8..8cca5726d 100644 --- a/gdbserver/Makefile +++ b/gdbserver/Makefile @@ -6,7 +6,7 @@ LDFLAGS=-L.. -lstlink -lusb-1.0 all: $(PRG) -$(PRG): $(OBJS) +$(PRG): $(OBJS) ../libstlink.a $(CC) -o $@ $^ $(LDFLAGS) clean: From 081eae3087ac42127262452aee1808aa3d0b8abc Mon Sep 17 00:00:00 2001 From: Fabien Le Mentec Date: Wed, 4 Jan 2012 00:55:47 -0600 Subject: [PATCH 0100/1435] [fix] valueless return warning --- src/stlink-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 04f0b2cbe..65d92ecab 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -203,7 +203,7 @@ uint32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr) { size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return 0; } return read_uint32(rdata, 4); } From b90309b66046e5d48467fc0433e477baa87eec67 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Fri, 13 Jan 2012 19:16:15 +0100 Subject: [PATCH 0101/1435] Less noisy output for STM32L erase/program, but still showing progess --- src/stlink-common.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 5a5131424..28be2d25e 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -893,7 +893,6 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - ILOG("Erasing flash page at addr: %#x\n", flashaddr); if (sl->chip_id == STM32F4_CHIP_ID) { /* wait for ongoing op to finish */ @@ -1234,8 +1233,11 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); return -1; } + fprintf(stdout,"\rFlash page at addr: 0x%08lx erased", addr + off); + fflush(stdout); page_count++; } + fprintf(stdout,"\n"); ILOG("Finished erasing %d pages of %d (%#x) bytes\n", page_count, sl->flash_pgsz, sl->flash_pgsz); @@ -1321,19 +1323,20 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned /* write a word in program memory */ for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; + write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); + stlink_write_debug32(sl, addr + off, data); + if (sl->verbose >= 1) { if ((off & (sl->flash_pgsz - 1)) == 0) { /* show progress. writing procedure is slow and previous errors are misleading */ const uint32_t pgnum = off / sl->flash_pgsz; const uint32_t pgcount = len / sl->flash_pgsz; - fprintf(stdout, "%u pages written out of %u\n", pgnum, pgcount); + fprintf(stdout, "\r%3u/%u pages written", pgnum, pgcount); + fflush(stdout); } } - write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); - stlink_write_debug32(sl, addr + off, data); - /* wait for sr.busy to be cleared */ while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { } @@ -1377,6 +1380,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned #endif /* todo: check redo write operation */ } + fprintf(stdout, "\n"); /* reset lock bits */ val = stlink_read_debug32(sl, STM32L_FLASH_PECR) | (1 << 0) | (1 << 1) | (1 << 2); From b50eedcdb46c7baee5479ba20ca7d326702ac5a4 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 17 Jan 2012 15:44:17 +0100 Subject: [PATCH 0102/1435] Some L1 flash address was off by 0x10, but is never used --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 28be2d25e..2d495a852 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -59,7 +59,7 @@ #define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) #define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) #define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) -#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x0c) +#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) #define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) From 72966d19122b54ce39a29c4b8a6f44170cce82c1 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 17 Jan 2012 21:17:02 +0100 Subject: [PATCH 0103/1435] write_mem8 with more than 0x40 bytes gives unexpected results --- src/stlink-common.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index 2d495a852..0c391129c 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -537,6 +537,11 @@ void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem8 ***\n"); + if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour + fprintf(stderr, "Error: Data length > 64: +%d byte.\n", + len); + return; + } sl->backend->write_mem8(sl, addr, len); } From 079148247ce01c8b2ca0f8622e3d754d1f0ed3f3 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 17 Jan 2012 21:24:01 +0100 Subject: [PATCH 0104/1435] In write_buffer_to_sram() write as much as possible with write_mem32 --- src/stlink-common.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 0c391129c..97bc3e140 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -864,8 +864,16 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) { /* write the buffer right after the loader */ - memcpy(sl->q_buf, buf, size); - stlink_write_mem8(sl, fl->buf_addr, size); + size_t chunk = size & ~0x3; + size_t rem = size & 0x3; + if (chunk) { + memcpy(sl->q_buf, buf, chunk); + stlink_write_mem32(sl, fl->buf_addr, chunk); + } + if (rem) { + memcpy(sl->q_buf, buf+chunk, rem); + stlink_write_mem8(sl, (fl->buf_addr)+chunk, rem); + } return 0; } From 9c2b7dd76b8c5da11f3789c8dc3f5226f6f5f877 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 17 Jan 2012 21:28:36 +0100 Subject: [PATCH 0105/1435] Enable half_page write for STM32L --- src/stlink-common.c | 86 +++++++++++++++++++++++++++++++++++++-------- 1 file changed, 71 insertions(+), 15 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 97bc3e140..2ecddea3d 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -61,6 +61,8 @@ #define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) #define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) #define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) +#define FLASH_L1_FPRG 10 +#define FLASH_L1_PROG 3 //STM32F4 @@ -1212,6 +1214,57 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, } +int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned num_half_pages) +{ + unsigned int count; + uint32_t val; + flash_loader_t fl; + + ILOG("Starting Half page flash write for STM32L core id\n"); + /* flash loader initialization */ + if (init_flash_loader(sl, &fl) == -1) { + WLOG("init_flash_loader() == -1\n"); + return -1; + } + /* Unlock already done */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val |= (1 << FLASH_L1_FPRG); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + + val |= (1 << FLASH_L1_PROG); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {} + +#define L1_WRITE_BLOCK_SIZE 0x80 + for (count = 0; count < num_half_pages; count ++) { + if (run_flash_loader(sl, &fl, addr + count * L1_WRITE_BLOCK_SIZE, base + count * L1_WRITE_BLOCK_SIZE, L1_WRITE_BLOCK_SIZE) == -1) { + WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * L1_WRITE_BLOCK_SIZE); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG)); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + return -1; + } + /* wait for sr.busy to be cleared */ + if (sl->verbose >= 1) { + /* show progress. writing procedure is slow + and previous errors are misleading */ + fprintf(stdout, "\r%3u/%u halfpages written", count, num_half_pages); + fflush(stdout); + } + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { + } + } + fprintf(stdout, "\n"); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val &= ~(1 << FLASH_L1_PROG); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val &= ~(1 << FLASH_L1_FPRG); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + + return 0; +} + int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) { size_t off; flash_loader_t fl; @@ -1332,24 +1385,19 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned fprintf(stderr, "pecr.prglock not clear\n"); return -1; } + if (len > L1_WRITE_BLOCK_SIZE) { + if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1){ + WLOG("\nwrite_half_pages failed == -1\n"); + return -1; + } + } - /* write a word in program memory */ - for (off = 0; off < len; off += sizeof(uint32_t)) { + /* write remainingword in program memory */ + for (off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE; off < len; off += sizeof(uint32_t)) { uint32_t data; write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); stlink_write_debug32(sl, addr + off, data); - if (sl->verbose >= 1) { - if ((off & (sl->flash_pgsz - 1)) == 0) { - /* show progress. writing procedure is slow - and previous errors are misleading */ - const uint32_t pgnum = off / sl->flash_pgsz; - const uint32_t pgcount = len / sl->flash_pgsz; - fprintf(stdout, "\r%3u/%u pages written", pgnum, pgcount); - fflush(stdout); - } - } - /* wait for sr.busy to be cleared */ while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { } @@ -1470,6 +1518,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { reg rr; + int i = 0; DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); // FIXME This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { @@ -1487,7 +1536,6 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, target, 0); /* target */ stlink_write_reg(sl, fl->buf_addr, 1); /* source */ stlink_write_reg(sl, count, 2); /* count (32 bits words) */ - stlink_write_reg(sl, 0, 3); /* output count */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ } else if (sl->core_id == STM32VL_CORE_ID) { @@ -1511,8 +1559,16 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_run(sl); /* wait until done (reaches breakpoint) */ - while (is_core_halted(sl) == 0) ; + while ((is_core_halted(sl) == 0) && (i <10000)) + { + i++; + } + if ( i > 9999) { + fprintf(stderr, "run error\n"); + return -1; + } + /* check written byte count */ if (sl->core_id == STM32L_CORE_ID) { From 587c65948ae4dcb2c3a93c331c3397f3ab22355d Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 17 Jan 2012 21:43:58 +0100 Subject: [PATCH 0106/1435] As write_buffer_to_sram() can now handles arbitrary size, use flash_pgsz chunks for writing F1 and reduce output --- src/stlink-common.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 2ecddea3d..69a68cef4 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -181,7 +181,7 @@ static int unlock_flash_if(stlink_t *sl) { return -1; } } - ILOG("Successfully unlocked flash\n"); + DLOG("Successfully unlocked flash\n"); return 0; } @@ -1454,15 +1454,11 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned return -1; } - /* write each page. above WRITE_BLOCK_SIZE fails? */ -#define WRITE_BLOCK_SIZE 0x40 int write_block_count = 0; - for (off = 0; off < len; off += WRITE_BLOCK_SIZE) { - ILOG("Writing flash block %d of size %d (%#x)\n", write_block_count, - WRITE_BLOCK_SIZE, WRITE_BLOCK_SIZE); + for (off = 0; off < len; off += sl->flash_pgsz) { /* adjust last write size */ - size_t size = WRITE_BLOCK_SIZE; - if ((off + WRITE_BLOCK_SIZE) > len) size = len - off; + size_t size = sl->flash_pgsz; + if ((off + sl->flash_pgsz) > len) size = len - off; /* unlock and set programming mode */ unlock_flash_if(sl); @@ -1473,8 +1469,14 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned return -1; } lock_flash(sl); - DLOG("Finished writing block %d\n", write_block_count++); + if (sl->verbose >= 1) { + /* show progress. writing procedure is slow + and previous errors are misleading */ + fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, len/sl->flash_pgsz); + fflush(stdout); + } } + fprintf(stdout, "\n"); } else { WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id); return -1; From bcf1030354bef0b28b9876944948cd6a46789b09 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 17 Jan 2012 21:55:10 +0100 Subject: [PATCH 0107/1435] Add dependancy from stlink.a --- gdbserver/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbserver/Makefile b/gdbserver/Makefile index c81ea52b8..4f5642450 100644 --- a/gdbserver/Makefile +++ b/gdbserver/Makefile @@ -6,7 +6,7 @@ LDFLAGS=-L.. -lstlink -lusb-1.0 all: $(PRG) -$(PRG): $(OBJS) +$(PRG): $(OBJS) ../libstlink.a $(CC) -o $@ $^ $(LDFLAGS) clean: From adaf602a5600ee53836d30f77a636ca380bfddf4 Mon Sep 17 00:00:00 2001 From: le mentec fabien Date: Wed, 18 Jan 2012 09:58:54 -0600 Subject: [PATCH 0108/1435] [fix] format warning on 32 bits --- src/stlink-common.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 69a68cef4..f7f03b918 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1299,7 +1299,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); return -1; } - fprintf(stdout,"\rFlash page at addr: 0x%08lx erased", addr + off); + fprintf(stdout,"\rFlash page at addr: 0x%08lx erased", + (unsigned long)addr + off); fflush(stdout); page_count++; } @@ -1472,7 +1473,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned if (sl->verbose >= 1) { /* show progress. writing procedure is slow and previous errors are misleading */ - fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, len/sl->flash_pgsz); + fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz); fflush(stdout); } } From 9c41193a169c1078fff70fb356c53c22224e5bb9 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 19 Jan 2012 13:47:23 +0100 Subject: [PATCH 0109/1435] Use stlink_r|w_debug32 for single word access in the gdbserver too --- gdbserver/gdb-server.c | 51 +++++++++++++----------------------------- 1 file changed, 16 insertions(+), 35 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 6033040a3..851c758a9 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -265,15 +265,13 @@ static void init_data_watchpoints(stlink_t *sl) { #endif // set trcena in debug command to turn on dwt unit - stlink_read_mem32(sl, 0xE000EDFC, 4); - sl->q_buf[3] |= 1; - stlink_write_mem32(sl, 0xE000EDFC, 4); + stlink_write_debug32(sl, 0xE000EDFC, + stlink_read_debug32(sl, 0xE000EDFC) | (1<<24)); // make sure all watchpoints are cleared - memset(sl->q_buf, 0, 4); for(int i = 0; i < DATA_WATCH_NUM; i++) { data_watches[i].fun = WATCHDISABLED; - stlink_write_mem32(sl, 0xe0001028 + i * 16, 4); + stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); } } @@ -306,25 +304,16 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr data_watches[i].mask = mask; // insert comparator address - sl->q_buf[0] = (addr & 0xff); - sl->q_buf[1] = ((addr >> 8) & 0xff); - sl->q_buf[2] = ((addr >> 16) & 0xff); - sl->q_buf[3] = ((addr >> 24) & 0xff); - - stlink_write_mem32(sl, 0xE0001020 + i * 16, 4); + stlink_write_debug32(sl, 0xE0001020 + i * 16, addr); // insert mask - memset(sl->q_buf, 0, 4); - sl->q_buf[0] = mask; - stlink_write_mem32(sl, 0xE0001024 + i * 16, 4); + stlink_write_debug32(sl, 0xE0001024 + i * 16, mask); // insert function - memset(sl->q_buf, 0, 4); - sl->q_buf[0] = wf; - stlink_write_mem32(sl, 0xE0001028 + i * 16, 4); + stlink_write_debug32(sl, 0xE0001028 + i * 16, wf); // just to make sure the matched bit is clear ! - stlink_read_mem32(sl, 0xE0001028 + i * 16, 4); + stlink_read_debug32(sl, 0xE0001028 + i * 16); return 0; } } @@ -346,9 +335,8 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) printf("delete watchpoint %d addr %x\n", i, addr); #endif - memset(sl->q_buf, 0, 4); data_watches[i].fun = WATCHDISABLED; - stlink_write_mem32(sl, 0xe0001028 + i * 16, 4); + stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); return 0; } @@ -374,15 +362,13 @@ struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM]; static void init_code_breakpoints(stlink_t *sl) { memset(sl->q_buf, 0, 4); - sl->q_buf[0] = 0x03; // KEY | ENABLE - stlink_write_mem32(sl, CM3_REG_FP_CTRL, 4); + stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/); printf("KARL - should read back as 0x03, not 60 02 00 00\n"); - stlink_read_mem32(sl, CM3_REG_FP_CTRL, 4); + stlink_read_debug32(sl, CM3_REG_FP_CTRL); - memset(sl->q_buf, 0, 4); for(int i = 0; i < CODE_BREAK_NUM; i++) { code_breaks[i].type = 0; - stlink_write_mem32(sl, CM3_REG_FP_COMP0 + i * 4, 4); + stlink_write_debug32(sl, CM3_REG_FP_COMP0 + i * 4, 0); } } @@ -416,28 +402,23 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { if(set) brk->type |= type; else brk->type &= ~type; - memset(sl->q_buf, 0, 4); - if(brk->type == 0) { #ifdef DEBUG printf("clearing hw break %d\n", id); #endif - stlink_write_mem32(sl, 0xe0002008 + id * 4, 4); + stlink_write_debug32(sl, 0xe0002008 + id * 4, 0); } else { - sl->q_buf[0] = ( brk->addr & 0xff) | 1; - sl->q_buf[1] = ((brk->addr >> 8) & 0xff); - sl->q_buf[2] = ((brk->addr >> 16) & 0xff); - sl->q_buf[3] = ((brk->addr >> 24) & 0xff) | (brk->type << 6); + uint32_t mask = (brk->addr) | 1 | (brk->type << 30); #ifdef DEBUG printf("setting hw break %d at %08x (%d)\n", id, brk->addr, brk->type); - printf("reg %02x %02x %02x %02x\n", - sl->q_buf[3], sl->q_buf[2], sl->q_buf[1], sl->q_buf[0]); + printf("reg %08x \n", + mask); #endif - stlink_write_mem32(sl, 0xe0002008 + id * 4, 4); + stlink_write_debug32(sl, 0xe0002008 + id * 4, mask); } return 0; From 16756fbe053f3e5efaf2973aebabeec201926f53 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 19 Jan 2012 13:55:00 +0100 Subject: [PATCH 0110/1435] Store the masked chip_id in the stlink structure. Should fix unexpected behaviour with L1 and F2 --- src/stlink-common.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index f7f03b918..626c86d6d 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -405,9 +405,9 @@ int stlink_load_device_params(stlink_t *sl) { chip_id = 0x413; } - sl->chip_id = chip_id; + sl->chip_id = chip_id & 0xfff; for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { - if(devices[i].chip_id == (chip_id & 0xFFF)) { + if(devices[i].chip_id == sl->chip_id) { params = &devices[i]; break; } @@ -422,9 +422,9 @@ int stlink_load_device_params(stlink_t *sl) { sl->sram_base = STM32_SRAM_BASE; // read flash size from hardware, if possible... - if ((chip_id & 0xFFF) == STM32_CHIPID_F2) { + if (sl->chip_id == STM32_CHIPID_F2) { sl->flash_size = 0; // FIXME - need to work this out some other way, just set to max possible? - } else if ((chip_id & 0xFFF) == STM32_CHIPID_F4) { + } else if (sl->chip_id == STM32_CHIPID_F4) { sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID } else { uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff; @@ -1185,7 +1185,7 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { */ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) { size_t off; - if ((sl->chip_id & 0xFFF) == STM32_CHIPID_F4) { + if (sl->chip_id == STM32_CHIPID_F4) { DLOG("(FIXME)Skipping verification for F4, not enough ram (yet)\n"); return 0; } From 4c206c3b7cb14bf29eb8ff23aa3c64e1cdab69db Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 19 Jan 2012 14:07:14 +0100 Subject: [PATCH 0111/1435] Allow to write to sram from the command line --- flash/main.c | 7 ++++++- src/stlink-common.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/flash/main.c b/flash/main.c index d61b22bd0..0f3040d37 100644 --- a/flash/main.c +++ b/flash/main.c @@ -109,7 +109,12 @@ int main(int ac, char** av) if (o.do_read == 0) /* write */ { - err = stlink_fwrite_flash(sl, o.filename, o.addr); + if ((o.addr >= sl->flash_base) && + (o.addr < sl->flash_base + sl->flash_size)) + err = stlink_fwrite_flash(sl, o.filename, o.addr); + else if ((o.addr >= sl->sram_base) && + (o.addr < sl->sram_base + sl->sram_size)) + err = stlink_fwrite_sram(sl, o.filename, o.addr); if (err == -1) { printf("stlink_fwrite_flash() == -1\n"); diff --git a/src/stlink-common.h b/src/stlink-common.h index a1442f366..155c6c003 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -363,6 +363,7 @@ extern "C" { int stlink_erase_flash_mass(stlink_t* sl); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length); int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); + int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length); // PUBLIC From 41e7c16cf2f9c6db6b4cc4d61af86a359646d6be Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 19 Jan 2012 14:17:22 +0100 Subject: [PATCH 0112/1435] When loading a file to SRAM or Flash, set the Stack pointer with the initial SP value and the Program counter with the reset value from the Vector table. Then run reset function --- src/stlink-common.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index 626c86d6d..87dfc02fb 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -799,6 +799,11 @@ int stlink_fwrite_sram /* success */ error = 0; + /* set stack*/ + stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13); + /* Set PC to the reset routine*/ + stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15); + stlink_run(sl); on_error: unmap_file(&mf); @@ -1514,6 +1519,11 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { mf.len -= num_empty; } err = stlink_write_flash(sl, addr, mf.base, mf.len); + /* set stack*/ + stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13); + /* Set PC to the reset routine*/ + stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15); + stlink_run(sl); unmap_file(&mf); return err; } From 8c36e07cbefc41751807d9e327c116d3755cc6aa Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 19 Jan 2012 14:59:02 +0100 Subject: [PATCH 0113/1435] Make stlink_erase_flash_mass device dependant and implement mass erase for L1 by consecutive page erase Allow to erase the device with the flash --- flash/main.c | 71 ++++++++++++++++++++++++++++++--------------- src/stlink-common.c | 58 +++++++++++++++++++++++------------- 2 files changed, 86 insertions(+), 43 deletions(-) diff --git a/flash/main.c b/flash/main.c index 0f3040d37..387a335a1 100644 --- a/flash/main.c +++ b/flash/main.c @@ -9,10 +9,10 @@ #include #include "stlink-common.h" - +enum st_cmds {DO_WRITE = 0, DO_READ = 1, DO_ERASE = 2}; struct opts { - unsigned int do_read; + enum st_cmds cmd; const char* devname; const char* filename; stm32_addr_t addr; @@ -22,7 +22,9 @@ struct opts static void usage(void) { puts("stlinkv1 command line: ./flash {read|write} /dev/sgX path addr "); + puts("stlinkv1 command line: ./flash /dev/sgX erase"); puts("stlinkv2 command line: ./flash {read|write} path addr "); + puts("stlinkv2 command line: ./flash erase"); puts(" use hex format for addr and "); } @@ -33,38 +35,52 @@ static int get_opts(struct opts* o, int ac, char** av) unsigned int i = 0; - if (ac < 3) return -1; + if (ac < 1) return -1; /* stlinkv2 */ o->devname = NULL; - if (strcmp(av[0], "read") == 0) + if (strcmp(av[0], "erase") == 0) { - o->do_read = 1; + o->cmd = DO_ERASE; /* stlinkv1 mode */ - if (ac == 5) + if (ac == 2) { o->devname = av[1]; i = 1; } - if (ac > 3) - o->size = strtoul(av[i + 3], NULL, 16); } - else if (strcmp(av[0], "write") == 0) - { - o->do_read = 0; - - /* stlinkv1 mode */ - if (ac == 4) - { - o->devname = av[1]; - i = 1; - } - } - else - { - return -1; + else { + if (ac < 3) return -1; + if (strcmp(av[0], "read") == 0) + { + o->cmd = DO_READ; + + /* stlinkv1 mode */ + if (ac == 5) + { + o->devname = av[1]; + i = 1; + } + if (ac > 3) + o->size = strtoul(av[i + 3], NULL, 16); + } + else if (strcmp(av[0], "write") == 0) + { + o->cmd = DO_WRITE; + + /* stlinkv1 mode */ + if (ac == 4) + { + o->devname = av[1]; + i = 1; + } + } + else + { + return -1; + } } o->filename = av[i + 1]; @@ -107,7 +123,7 @@ int main(int ac, char** av) if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); - if (o.do_read == 0) /* write */ + if (o.cmd == DO_WRITE) /* write */ { if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) @@ -121,6 +137,15 @@ int main(int ac, char** av) goto on_error; } } + else if (o.cmd == DO_ERASE) + { + err = stlink_erase_flash_mass(sl); + if (err == -1) + { + printf("stlink_fwrite_flash() == -1\n"); + goto on_error; + } + } else /* read */ { err = stlink_fread(sl, o.filename, o.addr, o.size); diff --git a/src/stlink-common.c b/src/stlink-common.c index 87dfc02fb..5cbf7febb 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1053,26 +1053,44 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - /* wait for ongoing op to finish */ - wait_flash_busy(sl); - - /* unlock if locked */ - unlock_flash_if(sl); - - /* set the mass erase bit */ - set_flash_cr_mer(sl); - - /* start erase operation, reset by hw with bsy bit */ - set_flash_cr_strt(sl); - - /* wait for completion */ - wait_flash_busy(sl); - - /* relock the flash */ - lock_flash(sl); - - /* todo: verify the erased memory */ - + if (sl->chip_id == STM32_CHIPID_F4) { + DLOG("(FIXME) Mass erase of STM32F4\n"); + } + else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { + /* erase each page */ + int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; + for (i = 0; i < num_pages; i++) { + /* addr must be an addr inside the page */ + stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz; + if (stlink_erase_flash_page(sl, addr) == -1) { + WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr); + return -1; + } + fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages); + fflush(stdout); + } + } + else { + /* wait for ongoing op to finish */ + wait_flash_busy(sl); + + /* unlock if locked */ + unlock_flash_if(sl); + + /* set the mass erase bit */ + set_flash_cr_mer(sl); + + /* start erase operation, reset by hw with bsy bit */ + set_flash_cr_strt(sl); + + /* wait for completion */ + wait_flash_busy(sl); + + /* relock the flash */ + lock_flash(sl); + + /* todo: verify the erased memory */ + } return 0; } From 0164043f9229e1c0c99789a7dcebe684a4fb6e1b Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 19 Jan 2012 15:45:51 +0100 Subject: [PATCH 0114/1435] A blank STM32L151 refused half-page writing. Fall back to half-word writing in that case. Report advance in half-word writing. Setting stack and PC give access error so automatic start fails too and hardware needs to be hard-reset to start --- src/stlink-common.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 5cbf7febb..39a714b17 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1069,6 +1069,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages); fflush(stdout); } + fprintf(stdout, "\n"); } else { /* wait for ongoing op to finish */ @@ -1242,7 +1243,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uns unsigned int count; uint32_t val; flash_loader_t fl; - + ILOG("Starting Half page flash write for STM32L core id\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { @@ -1277,7 +1278,6 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uns while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { } } - fprintf(stdout, "\n"); val = stlink_read_debug32(sl, STM32L_FLASH_PECR); val &= ~(1 << FLASH_L1_PROG); stlink_write_debug32(sl, STM32L_FLASH_PECR, val); @@ -1409,16 +1409,29 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned fprintf(stderr, "pecr.prglock not clear\n"); return -1; } + off = 0; if (len > L1_WRITE_BLOCK_SIZE) { if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1){ + /* This may happen on a blank device! */ WLOG("\nwrite_half_pages failed == -1\n"); - return -1; - } - } + } + else{ + off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE; + } + } /* write remainingword in program memory */ - for (off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE; off < len; off += sizeof(uint32_t)) { + for ( ; off < len; off += sizeof(uint32_t)) { uint32_t data; + if (off > 254) + fprintf(stdout, "\r"); + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { + fprintf(stdout, "\r%3u/%u pages written", + off/sl->flash_pgsz, len/sl->flash_pgsz); + fflush(stdout); + } + write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); stlink_write_debug32(sl, addr + off, data); @@ -1590,12 +1603,12 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_run(sl); /* wait until done (reaches breakpoint) */ - while ((is_core_halted(sl) == 0) && (i <10000)) + while ((is_core_halted(sl) == 0) && (i <1000)) { i++; } - if ( i > 9999) { + if ( i > 999) { fprintf(stderr, "run error\n"); return -1; } From d00a6a30a2e020d629df2eec46840d6af247b607 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Fri, 20 Jan 2012 17:25:01 +0100 Subject: [PATCH 0115/1435] F1 set_flash_cr_strt unconditionally set the PER bit and so mass erase didn't work --- src/stlink-common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 39a714b17..b6e4a51a5 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -246,9 +246,9 @@ static void set_flash_cr_strt(stlink_t *sl) { stlink_write_debug32(sl, FLASH_F4_CR, x); } else { - /* assume come on the flash_cr_per path */ - const uint32_t n = (1 << FLASH_CR_PER) | (1 << FLASH_CR_STRT); - stlink_write_debug32(sl, FLASH_CR, n); + stlink_write_debug32( + sl, FLASH_CR, + stlink_read_debug32(sl,FLASH_CR) |(1 << FLASH_CR_STRT) ); } } From ce813d328b6d1105af0254dafc43a1414a0dfed3 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 24 Jan 2012 13:21:47 +0100 Subject: [PATCH 0116/1435] Fix mass erase of F4 --- src/stlink-common.c | 39 ++++++++++++++++++++++++++++++--------- 1 file changed, 30 insertions(+), 9 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index b6e4a51a5..e8d324bee 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -229,13 +229,21 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { } static void set_flash_cr_mer(stlink_t *sl) { - const uint32_t n = 1 << FLASH_CR_MER; - stlink_write_debug32(sl, FLASH_CR, n); + if(sl->chip_id == STM32F4_CHIP_ID) + stlink_write_debug32(sl, FLASH_F4_CR, + stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); + else + stlink_write_debug32(sl, FLASH_CR, + stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER)); } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { - const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_MER); - stlink_write_debug32(sl, FLASH_CR, n); + if(sl->chip_id == STM32F4_CHIP_ID) + stlink_write_debug32(sl, FLASH_F4_CR, + stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); + else + stlink_write_debug32(sl, FLASH_CR, + stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER)); } static void set_flash_cr_strt(stlink_t *sl) { @@ -279,6 +287,22 @@ static void wait_flash_busy(stlink_t *sl) { ; } +static void wait_flash_busy_progress(stlink_t *sl) { + int i = 0; + fprintf(stdout, "Mass erasing"); + fflush(stdout); + while (is_flash_busy(sl)) + { + usleep(10000); + i++; + if (i % 100 == 0) { + fprintf(stdout, "."); + fflush(stdout); + } + } + fprintf(stdout, "\n"); +} + static inline unsigned int is_flash_eop(stlink_t *sl) { return read_flash_sr(sl) & (1 << FLASH_SR_EOP); } @@ -1053,10 +1077,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - if (sl->chip_id == STM32_CHIPID_F4) { - DLOG("(FIXME) Mass erase of STM32F4\n"); - } - else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { /* erase each page */ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1085,7 +1106,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { set_flash_cr_strt(sl); /* wait for completion */ - wait_flash_busy(sl); + wait_flash_busy_progress(sl); /* relock the flash */ lock_flash(sl); From a85ebd90b21ee37baa6d185dd1b5c676d768ac7c Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Fri, 27 Jan 2012 20:26:32 +0100 Subject: [PATCH 0117/1435] Fix writing to SRAM on F1. Blocksize greater 0x1800 stalls STLINKV2. V1 needs to be checked! --- src/stlink-common.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index e8d324bee..8605f8776 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -747,15 +747,21 @@ static void unmap_file(mapped_file_t * mf) { mf->len = 0; } +/* Limit the block size to compare to 0x1800 + Anything larger will stall the STLINK2 + Maybe STLINK V1 needs smaller value!*/ static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) { size_t off; + size_t n_cmp = sl->flash_pgsz; + if ( n_cmp > 0x1800) + n_cmp = 0x1800; - for (off = 0; off < mf->len; off += sl->flash_pgsz) { + for (off = 0; off < mf->len; off += n_cmp) { size_t aligned_size; /* adjust last page size */ - size_t cmp_size = sl->flash_pgsz; - if ((off + sl->flash_pgsz) > mf->len) + size_t cmp_size = n_cmp; + if ((off + n_cmp) > mf->len) cmp_size = mf->len - off; aligned_size = cmp_size; From b95e4aa8a47c4caef0e525205945bdc61c5ee2c8 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sat, 28 Jan 2012 04:46:22 +0100 Subject: [PATCH 0118/1435] CoreIF for F2/F4 is not different, use CPUID to distinguish. F4 errata seems to give wrong workaround --- src/stlink-common.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 8605f8776..03e1cce52 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -420,22 +420,23 @@ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { int stlink_load_device_params(stlink_t *sl) { ILOG("Loading device parameters....\n"); const chip_params_t *params = NULL; - sl->core_id = stlink_core_id(sl); uint32_t chip_id = stlink_chip_id(sl); - /* Fix chip_id for F4 rev A errata */ - if (((chip_id & 0xFFF) == 0x411) && (sl->core_id == CORE_M4_R0)) { - chip_id = 0x413; + sl->chip_id = chip_id & 0xfff; + /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/ + if (sl->chip_id == 0x411) { + uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00); + if((cpuid & 0xfff0) == 0xc240) + sl->chip_id = 0x413; } - sl->chip_id = chip_id & 0xfff; - for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { - if(devices[i].chip_id == sl->chip_id) { - params = &devices[i]; - break; - } - } + for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { + if(devices[i].chip_id == sl->chip_id) { + params = &devices[i]; + break; + } + } if (params == NULL) { WLOG("unknown chip id! %#x\n", chip_id); return -1; From 19b8c645402463b2303200cedda6d84f3c6c6582 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sun, 29 Jan 2012 14:21:26 +0100 Subject: [PATCH 0119/1435] Give a different error when writing to flash or ram --- flash/main.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/flash/main.c b/flash/main.c index 387a335a1..f838d9232 100644 --- a/flash/main.c +++ b/flash/main.c @@ -126,17 +126,23 @@ int main(int ac, char** av) if (o.cmd == DO_WRITE) /* write */ { if ((o.addr >= sl->flash_base) && - (o.addr < sl->flash_base + sl->flash_size)) + (o.addr < sl->flash_base + sl->flash_size)) { err = stlink_fwrite_flash(sl, o.filename, o.addr); - else if ((o.addr >= sl->sram_base) && + if (err == -1) + { + printf("stlink_fwrite_flash() == -1\n"); + goto on_error; + } + } + else if ((o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) err = stlink_fwrite_sram(sl, o.filename, o.addr); - if (err == -1) - { - printf("stlink_fwrite_flash() == -1\n"); - goto on_error; - } - } + if (err == -1) + { + printf("stlink_sram_flash() == -1\n"); + goto on_error; + } + } else if (o.cmd == DO_ERASE) { err = stlink_erase_flash_mass(sl); From a1a949fa5598c3d2e014d276e7e52aeb8d62f3e4 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Mon, 30 Jan 2012 13:32:18 +0100 Subject: [PATCH 0120/1435] Limit reading from RAM to the SRAM Size --- flash/main.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/flash/main.c b/flash/main.c index 387a335a1..249e5fddc 100644 --- a/flash/main.c +++ b/flash/main.c @@ -148,6 +148,12 @@ int main(int ac, char** av) } else /* read */ { + if ((o.addr >= sl->flash_base) && + (o.addr < sl->flash_base + sl->flash_size)) + o.size = sl->flash_size; + else if ((o.addr >= sl->sram_base) && + (o.addr < sl->sram_base + sl->sram_size)) + o.size = sl->sram_size; err = stlink_fread(sl, o.filename, o.addr, o.size); if (err == -1) { From 5e5d1fa747efd4c913fc9b64414d33a1586c99a3 Mon Sep 17 00:00:00 2001 From: Daniel O'Connor Date: Tue, 31 Jan 2012 16:49:45 +1030 Subject: [PATCH 0121/1435] Use pkg-config to find libusb CFLAGS and LDFLAGS. --- Makefile | 6 +++++- flash/Makefile | 6 +++++- gdbserver/Makefile | 6 +++++- src/stlink-sg.h | 2 +- src/stlink-usb.c | 2 +- src/stlink-usb.h | 2 +- 6 files changed, 18 insertions(+), 6 deletions(-) diff --git a/Makefile b/Makefile index 6bf02323d..4bb0608b1 100644 --- a/Makefile +++ b/Makefile @@ -5,7 +5,11 @@ VPATH=src SOURCES_LIB=stlink-common.c stlink-usb.c stlink-sg.c uglylogging.c OBJS_LIB=$(SOURCES_LIB:.c=.o) TEST_PROGRAMS=test_usb test_sg -LDFLAGS=-L. -lstlink -lusb-1.0 +LDFLAGS=-L. -lstlink + +# libusb location +LDFLAGS+=`pkg-config --libs libusb-1.0` +CFLAGS+=`pkg-config --cflags libusb-1.0` CFLAGS+=-g CFLAGS+=-DDEBUG=1 diff --git a/flash/Makefile b/flash/Makefile index cb7dcd2c2..491458717 100644 --- a/flash/Makefile +++ b/flash/Makefile @@ -4,7 +4,11 @@ CFLAGS+=-std=gnu99 CFLAGS+=-Wall -Wextra CFLAGS+=-I../src -LDFLAGS=-L.. -lstlink -lusb-1.0 +LDFLAGS=-L.. -lstlink + +# libusb location +LDFLAGS+=`pkg-config --libs libusb-1.0` +CFLAGS+=`pkg-config --cflags libusb-1.0` SRCS=main.c OBJS=$(SRCS:.c=.o) diff --git a/gdbserver/Makefile b/gdbserver/Makefile index 8cca5726d..bd5c73dbc 100644 --- a/gdbserver/Makefile +++ b/gdbserver/Makefile @@ -2,7 +2,11 @@ PRG := st-util OBJS = gdb-remote.o gdb-server.o CFLAGS+=-g -Wall -Werror -std=gnu99 -I../src -LDFLAGS=-L.. -lstlink -lusb-1.0 +LDFLAGS=-L.. -lstlink + +# libusb location +LDFLAGS+=`pkg-config --libs libusb-1.0` +CFLAGS+=`pkg-config --cflags libusb-1.0` all: $(PRG) diff --git a/src/stlink-sg.h b/src/stlink-sg.h index d4d7723b8..beecac324 100644 --- a/src/stlink-sg.h +++ b/src/stlink-sg.h @@ -12,7 +12,7 @@ extern "C" { #endif -#include +#include #include "stlink-common.h" // device access diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 65d92ecab..2a82b8837 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include "stlink-common.h" #include "stlink-usb.h" diff --git a/src/stlink-usb.h b/src/stlink-usb.h index 2f3b8cc3e..63b53695e 100644 --- a/src/stlink-usb.h +++ b/src/stlink-usb.h @@ -12,7 +12,7 @@ extern "C" { #endif -#include +#include #include "stlink-common.h" #define STLINK_SG_SIZE 31 From f38ff8f91282113b42ded9b108c05e5e329b6ffc Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 1 Feb 2012 20:55:10 +0000 Subject: [PATCH 0122/1435] Unify chipid naming convention. Flag more duplicate variables that need to be removed/combined --- gdbserver/gdb-server.c | 2 +- src/stlink-common.c | 28 ++++++++++++++-------------- src/stlink-common.h | 21 +++++++++------------ 3 files changed, 24 insertions(+), 27 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 851c758a9..89f862db0 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -219,7 +219,7 @@ char* make_memory_map(stlink_t *sl) { char* map = malloc(4096); map[0] = '\0'; - if(sl->chip_id==STM32F4_CHIP_ID) { + if(sl->chip_id==STM32_CHIPID_F4) { strcpy(map, memory_map_template_F4); } else { snprintf(map, 4096, memory_map_template, diff --git a/src/stlink-common.c b/src/stlink-common.c index 03e1cce52..65d459049 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -136,7 +136,7 @@ static inline uint32_t read_flash_obr(stlink_t *sl) { static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t res; - if(sl->chip_id==STM32F4_CHIP_ID) + if(sl->chip_id==STM32_CHIPID_F4) res = stlink_read_debug32(sl, FLASH_F4_CR); else res = stlink_read_debug32(sl, FLASH_CR); @@ -148,7 +148,7 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ - if(sl->chip_id==STM32F4_CHIP_ID) + if(sl->chip_id==STM32_CHIPID_F4) return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); else return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); @@ -160,7 +160,7 @@ static void unlock_flash(stlink_t *sl) { an invalid sequence results in a definitive lock of the FPEC block until next reset. */ - if(sl->chip_id==STM32F4_CHIP_ID) { + if(sl->chip_id==STM32_CHIPID_F4) { stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); } @@ -186,7 +186,7 @@ static int unlock_flash_if(stlink_t *sl) { } static void lock_flash(stlink_t *sl) { - if(sl->chip_id==STM32F4_CHIP_ID) { + if(sl->chip_id==STM32_CHIPID_F4) { const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); stlink_write_debug32(sl, FLASH_F4_CR, n); } @@ -199,7 +199,7 @@ static void lock_flash(stlink_t *sl) { static void set_flash_cr_pg(stlink_t *sl) { - if(sl->chip_id==STM32F4_CHIP_ID) { + if(sl->chip_id==STM32_CHIPID_F4) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_CR_PG); stlink_write_debug32(sl, FLASH_F4_CR, x); @@ -212,7 +212,7 @@ static void set_flash_cr_pg(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); - if(sl->chip_id==STM32F4_CHIP_ID) + if(sl->chip_id==STM32_CHIPID_F4) stlink_write_debug32(sl, FLASH_F4_CR, n); else stlink_write_debug32(sl, FLASH_CR, n); @@ -229,7 +229,7 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { } static void set_flash_cr_mer(stlink_t *sl) { - if(sl->chip_id == STM32F4_CHIP_ID) + if(sl->chip_id == STM32_CHIPID_F4) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); else @@ -238,7 +238,7 @@ static void set_flash_cr_mer(stlink_t *sl) { } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { - if(sl->chip_id == STM32F4_CHIP_ID) + if(sl->chip_id == STM32_CHIPID_F4) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); else @@ -247,7 +247,7 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { } static void set_flash_cr_strt(stlink_t *sl) { - if(sl->chip_id == STM32F4_CHIP_ID) + if(sl->chip_id == STM32_CHIPID_F4) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_F4_CR_STRT); @@ -266,7 +266,7 @@ static inline uint32_t read_flash_acr(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res; - if(sl->chip_id==STM32F4_CHIP_ID) + if(sl->chip_id==STM32_CHIPID_F4) res = stlink_read_debug32(sl, FLASH_F4_SR); else res = stlink_read_debug32(sl, FLASH_SR); @@ -275,7 +275,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { } static inline unsigned int is_flash_busy(stlink_t *sl) { - if(sl->chip_id==STM32F4_CHIP_ID) + if(sl->chip_id==STM32_CHIPID_F4) return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); else return read_flash_sr(sl) & (1 << FLASH_SR_BSY); @@ -927,7 +927,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ - if(sl->chip_id == STM32F4_CHIP_ID) { + if(sl->chip_id == STM32_CHIPID_F4) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector<4) sl->flash_pgsz=0x4000; else if(sector<5) sl->flash_pgsz=0x10000; @@ -944,7 +944,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - if (sl->chip_id == STM32F4_CHIP_ID) + if (sl->chip_id == STM32_CHIPID_F4) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1359,7 +1359,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned ILOG("Finished erasing %d pages of %d (%#x) bytes\n", page_count, sl->flash_pgsz, sl->flash_pgsz); - if (sl->chip_id == STM32F4_CHIP_ID) { + if (sl->chip_id == STM32_CHIPID_F4) { /* todo: check write operation */ /* First unlock the cr */ diff --git a/src/stlink-common.h b/src/stlink-common.h index 155c6c003..6fcb2194e 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -81,10 +81,18 @@ extern "C" { #define CM3_REG_FP_COMP0 0xE0002008 /* cortex core ids */ + // TODO clean this up... #define STM32VL_CORE_ID 0x1ba01477 #define STM32L_CORE_ID 0x2ba01477 #define STM32F4_CORE_ID 0x2ba01477 - +#define CORE_M3_R1 0x1BA00477 +#define CORE_M3_R2 0x4BA00477 +#define CORE_M4_R0 0x2BA01477 + +/* + * Chip IDs are explained in the appropriate programming manual for the + * DBGMCU_IDCODE register (0xE0042000) + */ // stm32 chipids, only lower 12 bits.. #define STM32_CHIPID_F1_MEDIUM 0x410 #define STM32_CHIPID_F2 0x411 @@ -101,17 +109,6 @@ extern "C" { #define STM32_FLASH_BASE 0x08000000 #define STM32_SRAM_BASE 0x20000000 -/* - * Chip IDs are explained in the appropriate programming manual for the - * DBGMCU_IDCODE register (0xE0042000) - */ -#define CORE_M3_R1 0x1BA00477 -#define CORE_M3_R2 0x4BA00477 -#define CORE_M4_R0 0x2BA01477 - -/* using chip id for F4 ident, since core id is same as F1 */ -#define STM32F4_CHIP_ID 0x413 - /* Cortex™-M3 Technical Reference Manual */ /* Debug Halting Control and Status Register */ #define DHCSR 0xe000edf0 From 7c4d7aa5593be79e6ff54df4ac7d9023ab83d810 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 1 Feb 2012 21:05:06 +0000 Subject: [PATCH 0123/1435] Use proper modifiers for size_t printing. Eliminates build warnings. --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 65d459049..d88b53e02 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1455,7 +1455,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned fprintf(stdout, "\r"); if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { - fprintf(stdout, "\r%3u/%u pages written", + fprintf(stdout, "\r%3zd/%3zd pages written", off/sl->flash_pgsz, len/sl->flash_pgsz); fflush(stdout); } From 3355fb6a080447dec33c8868ecae1d22bf392fe7 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 15 Nov 2011 01:42:47 +0000 Subject: [PATCH 0124/1435] Remove the "merge in progress" notice --- README | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/README b/README index 1eb6d2617..838484ee4 100644 --- a/README +++ b/README @@ -1,11 +1,3 @@ -IMPORTANT SHORT TERM NOTICE: -If you are targetting F1 devices, with either stlinkv1 or v2 hardware, you -_need_ to use karlp's libwork2 branch. - -If you are targetting F4, you _need_ to use texane's master - -If you are targetting F2 or L1, please let us know how it goes! - HOWTO ===== @@ -136,7 +128,7 @@ STLink v1 (as found on the 32VL Discovery board) Known Working Targets: * STM32F100xx (Medium Density VL) -* STM32F103 (according to jpa- o n##stm32 +* STM32F103 (according to jpa- on ##stm32 No information: * everything else! From ce603be2003ae67a6472b647f62b3ef2f80e0da3 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 16 Nov 2011 02:44:01 +0000 Subject: [PATCH 0125/1435] Update list of known working targets --- README | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README b/README index 838484ee4..73686a83d 100644 --- a/README +++ b/README @@ -133,11 +133,11 @@ Known Working Targets: No information: * everything else! - STLink v2 (as found on the 32L and F4 Discovery boards) Known Working Targets: * STM32F100xx (Medium Density VL, as on the 32VL Discovery board) -* ? +* STM32L1xx (STM32L Discovery board) +* STM32F407xx (STM32F4 Discovery board) Please report any and all known working combinations so I can update this! From 13035018f21c0cda27743aa4f26c543767a05cd6 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 1 Feb 2012 21:27:20 +0000 Subject: [PATCH 0126/1435] Add pkg-config to the list of requirements. --- README | 5 +++-- doc/tutorial/tutorial.pdf | Bin 96483 -> 115939 bytes doc/tutorial/tutorial.tex | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/README b/README index 73686a83d..022e191c1 100644 --- a/README +++ b/README @@ -14,8 +14,9 @@ called stlink and there are 2 versions: Common requirements ~~~~~~~~~~~~~~~~~~~ -libusb-1.0 (You probably already have this, but you'll need the +. libusb-1.0 (You probably already have this, but you'll need the development version to compile) +. pkg-config IF YOU HAVE AN STLINKv1 ~~~~~~~~~~~~~~~~~~~~~~~ @@ -128,7 +129,7 @@ STLink v1 (as found on the 32VL Discovery board) Known Working Targets: * STM32F100xx (Medium Density VL) -* STM32F103 (according to jpa- on ##stm32 +* STM32F103 (according to jpa- on ##stm32) No information: * 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z<&PLzDk3FfQX=4!0#xWKc6CLCLPCJL32?#{=c7Ui>InU-inWT4ALQuBj*Rk;h>D2_ ST+Jp4n9pZhS-E*i*#851%5JFu diff --git a/doc/tutorial/tutorial.tex b/doc/tutorial/tutorial.tex index c3615df78..2045d77da 100644 --- a/doc/tutorial/tutorial.tex +++ b/doc/tutorial/tutorial.tex @@ -60,6 +60,7 @@ \section{Installing STLINK} Before continuing, the following dependencies must be met: \begin{itemize} \item libusb-1.0 +\item pkg-config \end{itemize} \paragraph{} From 18d6fe4893d92b67f1690674a6e7482eef18a31f Mon Sep 17 00:00:00 2001 From: Fabien Le Mentec Date: Wed, 1 Feb 2012 16:05:46 -0600 Subject: [PATCH 0127/1435] Get st-util ack'ing the monitor request. Responds to monitor reset -- reset the core monitor resume -- get the core running but don't stop gdb executing commands monitor halt -- halt the core --- gdbserver/gdb-server.c | 43 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 89f862db0..94784fcdb 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -669,6 +669,49 @@ int serve(stlink_t *sl, int port) { strncpy(&reply[1], data, length); } } + } else if(!strncmp(queryName, "Rcmd,",4)) { + // Rcmd uses the wrong separator + char *separator = strstr(packet, ","), *params = ""; + if(separator == NULL) { + separator = packet + strlen(packet); + } else { + params = separator + 1; + } + + + if (!strncmp(params,"7265",4)) {// resume +#ifdef DEBUG + printf("Rcmd: resume\n"); +#endif + stlink_run(sl); + + reply = strdup("OK"); + } else if (!strncmp(params,"6861",4)) { //half + reply = strdup("OK"); + + stlink_force_debug(sl); + +#ifdef DEBUG + printf("Rcmd: halt\n"); +#endif + } else if (!strncmp(params,"7265",4)) { //reset + reply = strdup("OK"); + + stlink_force_debug(sl); + stlink_reset(sl); + init_code_breakpoints(sl); + init_data_watchpoints(sl); + +#ifdef DEBUG + printf("Rcmd: reset\n"); +#endif + } else { +#ifdef DEBUG + printf("Rcmd: %s\n", params); +#endif + + } + } if(reply == NULL) From 9153dd5c0818997d8b12fd0c12d28f64d477c94e Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 1 Feb 2012 23:54:02 +0000 Subject: [PATCH 0128/1435] Remove all project files from stlink. The project is made with Makefiles, so while the project files provided some convenience to some people, they were not in any way portable or maintained. Removing them also allows other people to keep their own versions without having to deal with shared conflicts. Updated gitignore to reflec this. --- .gitignore | 3 +- .project | 81 ---- nbproject/Package-Default.bash | 75 ---- nbproject/Package-flash.bash | 75 ---- nbproject/configurations.xml | 672 --------------------------------- nbproject/project.xml | 27 -- 6 files changed, 2 insertions(+), 931 deletions(-) delete mode 100644 .project delete mode 100644 nbproject/Package-Default.bash delete mode 100644 nbproject/Package-flash.bash delete mode 100644 nbproject/configurations.xml delete mode 100644 nbproject/project.xml diff --git a/.gitignore b/.gitignore index 8e974b74b..bc2ba52ac 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,5 @@ -/nbproject/private/ +nbproject +.project *.o *.elf doc/tutorial/*.log diff --git a/.project b/.project deleted file mode 100644 index 12a2f85eb..000000000 --- a/.project +++ /dev/null @@ -1,81 +0,0 @@ - - - stlink - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - ?children? - ?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\|| - - - ?name? - - - - org.eclipse.cdt.make.core.append_environment - true - - - org.eclipse.cdt.make.core.autoBuildTarget - all - - - org.eclipse.cdt.make.core.buildArguments - - - - org.eclipse.cdt.make.core.buildCommand - make - - - org.eclipse.cdt.make.core.cleanBuildTarget - clean - - - org.eclipse.cdt.make.core.contents - org.eclipse.cdt.make.core.activeConfigSettings - - - org.eclipse.cdt.make.core.enableAutoBuild - false - - - org.eclipse.cdt.make.core.enableCleanBuild - true - - - org.eclipse.cdt.make.core.enableFullBuild - true - - - org.eclipse.cdt.make.core.fullBuildTarget - all - - - org.eclipse.cdt.make.core.stopOnError - true - - - org.eclipse.cdt.make.core.useDefaultBuildCmd - true - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - diff --git a/nbproject/Package-Default.bash b/nbproject/Package-Default.bash deleted file mode 100644 index f6abfb43c..000000000 --- a/nbproject/Package-Default.bash +++ /dev/null @@ -1,75 +0,0 @@ -#!/bin/bash -x - -# -# Generated - do not edit! -# - -# Macros -TOP=`pwd` -CND_PLATFORM=GNU-Linux-x86 -CND_CONF=Default -CND_DISTDIR=dist -CND_BUILDDIR=build -NBTMPDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM}/tmp-packaging -TMPDIRNAME=tmp-packaging -OUTPUT_PATH=gdbserver/st-util -OUTPUT_BASENAME=st-util -PACKAGE_TOP_DIR=stlink/ - -# Functions -function checkReturnCode -{ - rc=$? - if [ $rc != 0 ] - then - exit $rc - fi -} -function makeDirectory -# $1 directory path -# $2 permission (optional) -{ - mkdir -p "$1" - checkReturnCode - if [ "$2" != "" ] - then - chmod $2 "$1" - checkReturnCode - fi -} -function copyFileToTmpDir -# $1 from-file path -# $2 to-file path -# $3 permission -{ - cp "$1" "$2" - checkReturnCode - if [ "$3" != "" ] - then - chmod $3 "$2" - checkReturnCode - fi -} - -# Setup -cd "${TOP}" -mkdir -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package -rm -rf ${NBTMPDIR} -mkdir -p ${NBTMPDIR} - -# Copy files and create directories and links -cd "${TOP}" -makeDirectory "${NBTMPDIR}/stlink/bin" -copyFileToTmpDir "${OUTPUT_PATH}" "${NBTMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755 - - -# Generate tar file -cd "${TOP}" -rm -f ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stlink.tar -cd ${NBTMPDIR} -tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stlink.tar * -checkReturnCode - -# Cleanup -cd "${TOP}" -rm -rf ${NBTMPDIR} diff --git a/nbproject/Package-flash.bash b/nbproject/Package-flash.bash deleted file mode 100644 index 44fd0fc43..000000000 --- a/nbproject/Package-flash.bash +++ /dev/null @@ -1,75 +0,0 @@ -#!/bin/bash -x - -# -# Generated - do not edit! -# - -# Macros -TOP=`pwd` -CND_PLATFORM=GNU-Linux-x86 -CND_CONF=flash -CND_DISTDIR=dist -CND_BUILDDIR=build -NBTMPDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM}/tmp-packaging -TMPDIRNAME=tmp-packaging -OUTPUT_PATH=MissingOutputInProject -OUTPUT_BASENAME=MissingOutputInProject -PACKAGE_TOP_DIR=stlink/ - -# Functions -function checkReturnCode -{ - rc=$? - if [ $rc != 0 ] - then - exit $rc - fi -} -function makeDirectory -# $1 directory path -# $2 permission (optional) -{ - mkdir -p "$1" - checkReturnCode - if [ "$2" != "" ] - then - chmod $2 "$1" - checkReturnCode - fi -} -function copyFileToTmpDir -# $1 from-file path -# $2 to-file path -# $3 permission -{ - cp "$1" "$2" - checkReturnCode - if [ "$3" != "" ] - then - chmod $3 "$2" - checkReturnCode - fi -} - -# Setup -cd "${TOP}" -mkdir -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package -rm -rf ${NBTMPDIR} -mkdir -p ${NBTMPDIR} - -# Copy files and create directories and links -cd "${TOP}" -makeDirectory "${NBTMPDIR}/stlink" -copyFileToTmpDir "${OUTPUT_PATH}" "${NBTMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755 - - -# Generate tar file -cd "${TOP}" -rm -f ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stlink.tar -cd ${NBTMPDIR} -tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/stlink.tar * -checkReturnCode - -# Cleanup -cd "${TOP}" -rm -rf ${NBTMPDIR} diff --git a/nbproject/configurations.xml b/nbproject/configurations.xml deleted file mode 100644 index f1fcd48d1..000000000 --- a/nbproject/configurations.xml +++ /dev/null @@ -1,672 +0,0 @@ - - - - - - - - - - - discover_board.h - main.c - startup_stm32l1xx_md.s - system_stm32l1xx.c - - - discover_board.h - main.c - stm32l_discovery_lcd.c - stm32l_discovery_lcd.h - - - main.c - startup_stm32f10x_md_vl.S - stm32f10x_conf.h - stm32f10x_it.c - stm32f10x_it.h - system_stm32f10x.c - - - main.c - - - discover_board.h - main.c - startup_stm32l1xx_md.s - system_stm32l1xx.c - - - - STM32vldiscovery.c - STM32vldiscovery.h - - - - - - - - stdint.h - - - core_cm3.c - core_cm3.h - - - stm32f10x.h - stm32l1xx.h - system_stm32f10x.h - system_stm32l1xx.h - - - misc.h - stm32f10x_adc.h - stm32f10x_bkp.h - stm32f10x_can.h - stm32f10x_cec.h - stm32f10x_crc.h - stm32f10x_dac.h - stm32f10x_dbgmcu.h - stm32f10x_dma.h - stm32f10x_exti.h - stm32f10x_flash.h - stm32f10x_fsmc.h - stm32f10x_gpio.h - stm32f10x_i2c.h - stm32f10x_iwdg.h - stm32f10x_pwr.h - stm32f10x_rcc.h - stm32f10x_rtc.h - stm32f10x_sdio.h - stm32f10x_spi.h - stm32f10x_tim.h - stm32f10x_usart.h - stm32f10x_wwdg.h - - - misc.h - stm32l1xx_adc.h - stm32l1xx_comp.h - stm32l1xx_crc.h - stm32l1xx_dac.h - stm32l1xx_dbgmcu.h - stm32l1xx_dma.h - stm32l1xx_exti.h - stm32l1xx_flash.h - stm32l1xx_gpio.h - stm32l1xx_i2c.h - stm32l1xx_iwdg.h - stm32l1xx_lcd.h - stm32l1xx_pwr.h - stm32l1xx_rcc.h - stm32l1xx_rtc.h - stm32l1xx_spi.h - stm32l1xx_syscfg.h - stm32l1xx_tim.h - stm32l1xx_usart.h - stm32l1xx_wwdg.h - - - - - misc.c - stm32f10x_adc.c - stm32f10x_bkp.c - stm32f10x_can.c - stm32f10x_cec.c - stm32f10x_crc.c - stm32f10x_dac.c - stm32f10x_dbgmcu.c - stm32f10x_dma.c - stm32f10x_exti.c - stm32f10x_flash.c - stm32f10x_fsmc.c - stm32f10x_gpio.c - stm32f10x_i2c.c - stm32f10x_iwdg.c - stm32f10x_pwr.c - stm32f10x_rcc.c - stm32f10x_rtc.c - stm32f10x_sdio.c - stm32f10x_spi.c - stm32f10x_tim.c - stm32f10x_usart.c - stm32f10x_wwdg.c - - - misc.c - stm32l1xx_adc.c - stm32l1xx_comp.c - stm32l1xx_crc.c - stm32l1xx_dac.c - stm32l1xx_dbgmcu.c - stm32l1xx_dma.c - stm32l1xx_exti.c - stm32l1xx_flash.c - stm32l1xx_flash_ramfunc.c - stm32l1xx_gpio.c - stm32l1xx_i2c.c - stm32l1xx_iwdg.c - stm32l1xx_lcd.c - stm32l1xx_pwr.c - stm32l1xx_rcc.c - stm32l1xx_rtc.c - stm32l1xx_spi.c - stm32l1xx_syscfg.c - stm32l1xx_tim.c - stm32l1xx_usart.c - stm32l1xx_wwdg.c - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - main.c - - - gdb-remote.c - gdb-remote.h - gdb-server.c - - - stlink-common.c - stlink-common.h - stlink-sg.c - stlink-sg.h - stlink-usb.c - stlink-usb.h - test_sg.c - test_usb.c - uglylogging.c - uglylogging.h - - - - - stlink-hw.h - - - - - - - - Makefile - - - ^(nbproject)$ - - . - - Makefile - - - - LOCAL_SOURCES - default - - - - . - ${MAKE} -f Makefile - ${MAKE} -f Makefile clean - gdbserver/st-util - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . - - - DEBUG=1 - - - - - - - src - - - CONFIG_USE_LIBUSB=1 - DEBUG - - - - - - - src - - - CONFIG_USE_LIBUSB=1 - - - - - - - . - - - DEBUG=1 - - - - - - - - - LOCAL_SOURCES - default - - - - flash - ${MAKE} -f Makefile - ${MAKE} -f Makefile clean - - - - DEBUG - - - - - - - - - - - - - - - - - - src - - - CONFIG_USE_LIBUSB=1 - - - - - - - src - - - CONFIG_USE_LIBSG=1 - CONFIG_USE_LIBUSB=1 - - - - - - - . - - - - - - - - - - - - - - diff --git a/nbproject/project.xml b/nbproject/project.xml deleted file mode 100644 index 7526e4b6b..000000000 --- a/nbproject/project.xml +++ /dev/null @@ -1,27 +0,0 @@ - - - org.netbeans.modules.cnd.makeproject - - - stlink - c - - h - UTF-8 - - - . - - - - Default - 0 - - - flash - 0 - - - - - From edea824055ff395a218a1968c1efefd3dc9d6a37 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sun, 29 Jan 2012 14:21:26 +0100 Subject: [PATCH 0129/1435] Give a different error when writing to flash or ram --- flash/main.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/flash/main.c b/flash/main.c index 249e5fddc..24287456b 100644 --- a/flash/main.c +++ b/flash/main.c @@ -126,17 +126,23 @@ int main(int ac, char** av) if (o.cmd == DO_WRITE) /* write */ { if ((o.addr >= sl->flash_base) && - (o.addr < sl->flash_base + sl->flash_size)) + (o.addr < sl->flash_base + sl->flash_size)) { err = stlink_fwrite_flash(sl, o.filename, o.addr); - else if ((o.addr >= sl->sram_base) && + if (err == -1) + { + printf("stlink_fwrite_flash() == -1\n"); + goto on_error; + } + } + else if ((o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) err = stlink_fwrite_sram(sl, o.filename, o.addr); - if (err == -1) - { - printf("stlink_fwrite_flash() == -1\n"); - goto on_error; - } - } + if (err == -1) + { + printf("stlink_sram_flash() == -1\n"); + goto on_error; + } + } else if (o.cmd == DO_ERASE) { err = stlink_erase_flash_mass(sl); From cc461e9bc984da6a462c931848e535533b9bf461 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 2 Feb 2012 22:10:13 +0100 Subject: [PATCH 0130/1435] For L1/F2/F4 we need the chip-id to distinguish, F1 needs core_id as common deniminator --- src/stlink-common.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 03e1cce52..9f1220898 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -972,7 +972,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif } - else if (sl->core_id == STM32L_CORE_ID) + else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { uint32_t val; @@ -1185,7 +1185,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { const uint8_t* loader_code; size_t loader_size; - if (sl->core_id == STM32L_CORE_ID) /* stm32l */ + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) /* stm32l */ { loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); @@ -1404,7 +1404,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned } //STM32F4END - else if (sl->core_id == STM32L_CORE_ID) { + else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { /* use fast word write. todo: half page. */ uint32_t val; @@ -1599,7 +1599,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - if (sl->core_id == STM32L_CORE_ID) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1642,7 +1642,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } /* check written byte count */ - if (sl->core_id == STM32L_CORE_ID) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; From cbd0cf0918d63753e8c35d779b4b04e1d87eb889 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 2 Feb 2012 22:20:44 +0100 Subject: [PATCH 0131/1435] For now, we can treat F2 as F4 for flashing --- src/stlink-common.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 9f1220898..c122518bb 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -136,7 +136,7 @@ static inline uint32_t read_flash_obr(stlink_t *sl) { static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t res; - if(sl->chip_id==STM32F4_CHIP_ID) + if((sl->chip_id==STM32_CHIPID_F2) ||(sl->chip_id==STM32F4_CHIP_ID)) res = stlink_read_debug32(sl, FLASH_F4_CR); else res = stlink_read_debug32(sl, FLASH_CR); @@ -148,7 +148,7 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ - if(sl->chip_id==STM32F4_CHIP_ID) + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); else return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); @@ -160,7 +160,7 @@ static void unlock_flash(stlink_t *sl) { an invalid sequence results in a definitive lock of the FPEC block until next reset. */ - if(sl->chip_id==STM32F4_CHIP_ID) { + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) { stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); } @@ -186,7 +186,7 @@ static int unlock_flash_if(stlink_t *sl) { } static void lock_flash(stlink_t *sl) { - if(sl->chip_id==STM32F4_CHIP_ID) { + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) { const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); stlink_write_debug32(sl, FLASH_F4_CR, n); } @@ -199,7 +199,7 @@ static void lock_flash(stlink_t *sl) { static void set_flash_cr_pg(stlink_t *sl) { - if(sl->chip_id==STM32F4_CHIP_ID) { + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_CR_PG); stlink_write_debug32(sl, FLASH_F4_CR, x); @@ -212,7 +212,7 @@ static void set_flash_cr_pg(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); - if(sl->chip_id==STM32F4_CHIP_ID) + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) stlink_write_debug32(sl, FLASH_F4_CR, n); else stlink_write_debug32(sl, FLASH_CR, n); @@ -229,7 +229,7 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { } static void set_flash_cr_mer(stlink_t *sl) { - if(sl->chip_id == STM32F4_CHIP_ID) + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); else @@ -238,7 +238,7 @@ static void set_flash_cr_mer(stlink_t *sl) { } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { - if(sl->chip_id == STM32F4_CHIP_ID) + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); else @@ -247,7 +247,7 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { } static void set_flash_cr_strt(stlink_t *sl) { - if(sl->chip_id == STM32F4_CHIP_ID) + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_F4_CR_STRT); @@ -266,7 +266,7 @@ static inline uint32_t read_flash_acr(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res; - if(sl->chip_id==STM32F4_CHIP_ID) + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) res = stlink_read_debug32(sl, FLASH_F4_SR); else res = stlink_read_debug32(sl, FLASH_SR); @@ -275,7 +275,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { } static inline unsigned int is_flash_busy(stlink_t *sl) { - if(sl->chip_id==STM32F4_CHIP_ID) + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); else return read_flash_sr(sl) & (1 << FLASH_SR_BSY); @@ -927,7 +927,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ - if(sl->chip_id == STM32F4_CHIP_ID) { + if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector<4) sl->flash_pgsz=0x4000; else if(sector<5) sl->flash_pgsz=0x10000; @@ -944,7 +944,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - if (sl->chip_id == STM32F4_CHIP_ID) + if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1359,7 +1359,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned ILOG("Finished erasing %d pages of %d (%#x) bytes\n", page_count, sl->flash_pgsz, sl->flash_pgsz); - if (sl->chip_id == STM32F4_CHIP_ID) { + if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32F4_CHIP_ID)) { /* todo: check write operation */ /* First unlock the cr */ From 02357a8b278a55e9428d064dbb57d893095db8b8 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 2 Feb 2012 22:36:13 +0100 Subject: [PATCH 0132/1435] Assume maximum FLASH size for F2 as for F4 (broken Flash size register) Verify F2 and F4 by using a decent block size --- src/stlink-common.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index c122518bb..294f932b2 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -448,7 +448,7 @@ int stlink_load_device_params(stlink_t *sl) { // read flash size from hardware, if possible... if (sl->chip_id == STM32_CHIPID_F2) { - sl->flash_size = 0; // FIXME - need to work this out some other way, just set to max possible? + sl->flash_size = 0x100000; /* Use maximum, User must care!*/ } else if (sl->chip_id == STM32_CHIPID_F4) { sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID } else { @@ -1237,17 +1237,13 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { */ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) { size_t off; - if (sl->chip_id == STM32_CHIPID_F4) { - DLOG("(FIXME)Skipping verification for F4, not enough ram (yet)\n"); - return 0; - } + size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz; ILOG("Starting verification of write complete\n"); - for (off = 0; off < length; off += sl->flash_pgsz) { + for (off = 0; off < length; off += cmp_size) { size_t aligned_size; /* adjust last page size */ - size_t cmp_size = sl->flash_pgsz; - if ((off + sl->flash_pgsz) > length) + if ((off + cmp_size) > length) cmp_size = length - off; aligned_size = cmp_size; From 132491480619da445b03b55fae7eeed0b1044da5 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 2 Feb 2012 22:49:33 +0100 Subject: [PATCH 0133/1435] Fix the progress indicator for F2/F4 flash writing --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 294f932b2..68b7d5049 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1377,7 +1377,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned /* show progress. writing procedure is slow and previous errors are misleading */ const uint32_t pgnum = (off / PROGRESS_CHUNK_SIZE)+1; - const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE; + const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE +1; fprintf(stdout, "Writing %ukB chunk %u out of %u\n", PROGRESS_CHUNK_SIZE/1024, pgnum, pgcount); } } From e919d94870667af422a8116b3f3a0fd0ffe16742 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sat, 4 Feb 2012 15:49:11 +0100 Subject: [PATCH 0134/1435] Report about more Chips tested --- README | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README b/README index 022e191c1..bb06f60a9 100644 --- a/README +++ b/README @@ -138,6 +138,8 @@ STLink v2 (as found on the 32L and F4 Discovery boards) Known Working Targets: * STM32F100xx (Medium Density VL, as on the 32VL Discovery board) * STM32L1xx (STM32L Discovery board) +* STM32F107RC, STM32L151RB, STM32F205RE and STM32F405RE on a custom boards + (https://github.com/UweBonnes/wiki_fuer_alex/layout/usps...) * STM32F407xx (STM32F4 Discovery board) Please report any and all known working combinations so I can update this! From c2d09105f5bc00c5d9896ebf3f2a5595005e6d64 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 7 Feb 2012 21:20:54 +0100 Subject: [PATCH 0135/1435] Remove an outdated FIXME --- src/stlink-usb.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 2a82b8837..979ba9731 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -636,7 +636,6 @@ stlink_t* stlink_open_usb(const int verbose) { slu->usb_handle = libusb_open_device_with_vid_pid(slu->libusb_ctx, USB_ST_VID, USB_STLINK_32L_PID); if (slu->usb_handle == NULL) { - // TODO - free usb context too... WLOG("Couldn't find any ST-Link/V2 devices"); goto on_error; } From 957b9c504fa6984314e0dd00958500dcf622ac9e Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 7 Feb 2012 21:43:43 +0100 Subject: [PATCH 0136/1435] Revive the V1 pathes in stlink-usb. Tested with the STM32VL Discovery. --- src/stlink-usb.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 979ba9731..8f5c6c410 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -127,8 +127,6 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, } if ((handle->protocoll == 1) && terminate) { - fprintf(stderr, "This is never used....\n"); - exit(EXIT_FAILURE); /* Read the SG reply */ unsigned char sg_buf[13]; libusb_fill_bulk_transfer @@ -157,7 +155,6 @@ static int fill_command int i = 0; memset(cmd, 0, sizeof (sl->c_buf)); if(slu->protocoll == 1) { - fprintf(stderr, "This is never used....\n"); cmd[i++] = 'U'; cmd[i++] = 'S'; cmd[i++] = 'B'; @@ -636,10 +633,14 @@ stlink_t* stlink_open_usb(const int verbose) { slu->usb_handle = libusb_open_device_with_vid_pid(slu->libusb_ctx, USB_ST_VID, USB_STLINK_32L_PID); if (slu->usb_handle == NULL) { - WLOG("Couldn't find any ST-Link/V2 devices"); - goto on_error; + slu->usb_handle = libusb_open_device_with_vid_pid(slu->libusb_ctx, USB_ST_VID, USB_STLINK_PID); + if (slu->usb_handle == NULL) { + WLOG("Couldn't find any ST-Link/V2 devices"); + goto on_error; + } + slu->protocoll = 1; } - + if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { int r; From 41c5ef21ab59dd3d8505c2471e4f1a63611e1f47 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Tue, 7 Feb 2012 21:48:46 +0100 Subject: [PATCH 0137/1435] Rename "flash" to "st-flash" --- flash/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/flash/Makefile b/flash/Makefile index 491458717..5345dcbfd 100644 --- a/flash/Makefile +++ b/flash/Makefile @@ -13,7 +13,7 @@ CFLAGS+=`pkg-config --cflags libusb-1.0` SRCS=main.c OBJS=$(SRCS:.c=.o) -NAME=flash +NAME=st-flash all: $(NAME) From b014aebd6372039bbb8214ccbc1e76b22ae5a8c2 Mon Sep 17 00:00:00 2001 From: Rob Spanton Date: Mon, 23 Apr 2012 23:19:55 +0100 Subject: [PATCH 0138/1435] Fix an unused parameter warning test_sg.c's main doesn't use its argv parameter, and so the compiler warns us this is the case. This patch stops it from warning us. --- src/test_sg.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/test_sg.c b/src/test_sg.c index 357f43665..51b0f074c 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -33,6 +33,8 @@ static void __attribute__((unused)) mark_buf(stlink_t *sl) { int main(int argc, char *argv[]) { + /* Avoid unused parameter warning */ + (void)argv; // set scpi lib debug level: 0 for no debug info, 10 for lots switch (argc) { From 087a3596c3f22599867411fafb79fdfb3f48097c Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sat, 28 Apr 2012 02:13:58 +0100 Subject: [PATCH 0139/1435] autoconfiscate --- .gitignore | 39 ++++++++++++++++++++--------------- ChangeLog | 0 Makefile | 58 ---------------------------------------------------- Makefile.am | 20 ++++++++++++++++++ NEWS | 0 autogen.sh | 11 ++++++++++ configure.ac | 29 ++++++++++++++++++++++++++ 7 files changed, 82 insertions(+), 75 deletions(-) create mode 100644 ChangeLog delete mode 100644 Makefile create mode 100644 Makefile.am create mode 100644 NEWS create mode 100755 autogen.sh create mode 100644 configure.ac diff --git a/.gitignore b/.gitignore index bc2ba52ac..c04ecfcdd 100644 --- a/.gitignore +++ b/.gitignore @@ -1,18 +1,23 @@ -nbproject -.project +COPYING +INSTALL +Makefile.in +aclocal.m4 +autom4te.cache +config.guess +config.sub +configure +depcomp +install-sh +ltmain.sh +missing +*.bz2 +*.lo *.o -*.elf -doc/tutorial/*.log -doc/tutorial/*.aux -libstlink.a -test_usb -test_sg -gdbserver/st-util -flash/flash -*.log -example/*/*.bin -example/*/*.elf -example/*/*/*.bin -example/*/*/*/*.bin -example/*/*/*.a -example/*/*/*/*.a +.libs +libtool +*.la +config.log +config.status +compile +st-flash +st-util diff --git a/ChangeLog b/ChangeLog new file mode 100644 index 000000000..e69de29bb diff --git a/Makefile b/Makefile deleted file mode 100644 index 4bb0608b1..000000000 --- a/Makefile +++ /dev/null @@ -1,58 +0,0 @@ -# make ... for both stlink v1 and stlink v2 support -## -VPATH=src - -SOURCES_LIB=stlink-common.c stlink-usb.c stlink-sg.c uglylogging.c -OBJS_LIB=$(SOURCES_LIB:.c=.o) -TEST_PROGRAMS=test_usb test_sg -LDFLAGS=-L. -lstlink - -# libusb location -LDFLAGS+=`pkg-config --libs libusb-1.0` -CFLAGS+=`pkg-config --cflags libusb-1.0` - -CFLAGS+=-g -CFLAGS+=-DDEBUG=1 -CFLAGS+=-std=gnu99 -CFLAGS+=-Wall -Wextra - - -LIBRARY=libstlink.a - -all: $(LIBRARY) flash gdbserver $(TEST_PROGRAMS) - -$(LIBRARY): $(OBJS_LIB) - @echo "objs are $(OBJS_LIB)" - $(AR) -cr $@ $^ - @echo "done making library" - - -test_sg: test_sg.o $(LIBRARY) - @echo "building test_sg" - $(CC) test_sg.o $(LDFLAGS) -o $@ - -test_usb: test_usb.o $(LIBRARY) - @echo "building test_usb" - $(CC) test_usb.o $(LDFLAGS) -o $@ - @echo "done linking" - -%.o: %.c - @echo "building $^ into $@" - $(CC) $(CFLAGS) -c $^ -o $@ - @echo "done compiling" - -clean: - rm -rf $(OBJS_LIB) - rm -rf $(LIBRARY) - rm -rf test_usb* - rm -rf test_sg* - $(MAKE) -C flash clean - $(MAKE) -C gdbserver clean - -flash: - $(MAKE) -C flash - -gdbserver: - $(MAKE) -C gdbserver CONFIG_USE_LIBSG="$(CONFIG_USE_LIBSG)" - -.PHONY: clean all flash gdbserver diff --git a/Makefile.am b/Makefile.am new file mode 100644 index 000000000..9aeec4a00 --- /dev/null +++ b/Makefile.am @@ -0,0 +1,20 @@ +# Makefile.am -- Process this file with automake to produce Makefile.in +bin_PROGRAMS = st-flash st-util + +noinst_LTLIBRARIES = libstlink.la + +st_flash_SOURCES = flash/main.c +st_util_SOURCES = gdbserver/gdb-remote.c gdbserver/gdb-remote.h gdbserver/gdb-server.c + +libstlink_la_SOURCES = src/stlink-common.c src/stlink-usb.c src/stlink-sg.c src/uglylogging.c \ + src/stlink-common.h src/stlink-usb.h src/stlink-sg.h src/uglylogging.h + +libstlink_la_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 + +st_flash_LDADD = libstlink.la +st_flash_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src + +st_util_LDADD = libstlink.la +st_util_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src + +EXTRA_DIST = autogen.sh diff --git a/NEWS b/NEWS new file mode 100644 index 000000000..e69de29bb diff --git a/autogen.sh b/autogen.sh new file mode 100755 index 000000000..3a76a1150 --- /dev/null +++ b/autogen.sh @@ -0,0 +1,11 @@ +#!/bin/sh +if test ! "x$(which libtoolize)" = "x"; then + echo "Running libtoolize" + libtoolize --copy --force --automake +else + if test ! "x$(which gintltoolize)" = "x"; then + echo "Running glibtoolize" + glibtoolize --copy --force --automake + fi +fi +autoreconf --install --force --verbose diff --git a/configure.ac b/configure.ac new file mode 100644 index 000000000..fcfb37735 --- /dev/null +++ b/configure.ac @@ -0,0 +1,29 @@ +# -*- Autoconf -*- +# Process this file with autoconf to produce a configure script. + +AC_PREREQ(2.61) +AC_INIT([stlink],[0.5.0],[davem@devkitpro.org]) +AC_CONFIG_SRCDIR([src/stlink-common.c]) + +AM_INIT_AUTOMAKE([1.10]) + + +# Checks for programs. +AC_PROG_CC +AC_PROG_INSTALL +AC_CANONICAL_HOST +AC_CANONICAL_BUILD +AC_PROG_LIBTOOL +AM_PROG_CC_C_O + +# Checks for libraries. +PKG_CHECK_MODULES(USB, libusb-1.0 >= 1.0.0,, + AC_MSG_ERROR([*** Required libusb-1.0 >= 1.0.0 not installed ***])) +AC_CHECK_LIB([usbpath],[usb_path2devnum],,,-lusb) + +LIBS="$LIBS $USB_LIBS" +CFLAGS="$CFLAGS $USB_CFLAGS" + +AC_CONFIG_FILES([Makefile]) +AC_OUTPUT + From 691e9af28da2e1178353a5c016c478e508a04f19 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sat, 28 Apr 2012 22:55:23 +0100 Subject: [PATCH 0140/1435] Changes for compiling with mingw32 add mmap & pread functions when compiling for systems that don't provide them don't use libtoolize, stick with static libraries --- Makefile.am | 29 +++++++++++++++---- autogen.sh | 9 ------ configure.ac | 11 ++++++-- src/mmap.c | 69 +++++++++++++++++++++++++++++++++++++++++++++ src/mmap.h | 62 ++++++++++++++++++++++++++++++++++++++++ src/pread.c | 42 +++++++++++++++++++++++++++ src/stlink-common.c | 3 +- src/stlink-sg.c | 2 +- src/stlink-usb.c | 12 ++++++++ 9 files changed, 218 insertions(+), 21 deletions(-) create mode 100644 src/mmap.c create mode 100644 src/mmap.h create mode 100644 src/pread.c diff --git a/Makefile.am b/Makefile.am index 9aeec4a00..28e11d5e5 100644 --- a/Makefile.am +++ b/Makefile.am @@ -1,20 +1,37 @@ # Makefile.am -- Process this file with automake to produce Makefile.in + +AUTOMAKE_OPTIONS = subdir-objects + bin_PROGRAMS = st-flash st-util -noinst_LTLIBRARIES = libstlink.la +noinst_LIBRARIES = libstlink.a st_flash_SOURCES = flash/main.c st_util_SOURCES = gdbserver/gdb-remote.c gdbserver/gdb-remote.h gdbserver/gdb-server.c -libstlink_la_SOURCES = src/stlink-common.c src/stlink-usb.c src/stlink-sg.c src/uglylogging.c \ - src/stlink-common.h src/stlink-usb.h src/stlink-sg.h src/uglylogging.h +CFILES = \ + src/stlink-common.c \ + src/stlink-usb.c \ + src/stlink-sg.c \ + src/uglylogging.c + +HFILES = \ + src/stlink-common.h \ + src/stlink-usb.h \ + src/stlink-sg.h \ + src/uglylogging.h \ + src/mmap.h -libstlink_la_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 +libstlink_a_SOURCES = $(CFILES) $(HFILES) -st_flash_LDADD = libstlink.la +libstlink_a_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 +libstlink_a_LIBADD = $(LIBOBJS) + +st_flash_LDADD = libstlink.a st_flash_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -st_util_LDADD = libstlink.la +st_util_LDADD = libstlink.a st_util_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src EXTRA_DIST = autogen.sh + diff --git a/autogen.sh b/autogen.sh index 3a76a1150..2af5ccdac 100755 --- a/autogen.sh +++ b/autogen.sh @@ -1,11 +1,2 @@ #!/bin/sh -if test ! "x$(which libtoolize)" = "x"; then - echo "Running libtoolize" - libtoolize --copy --force --automake -else - if test ! "x$(which gintltoolize)" = "x"; then - echo "Running glibtoolize" - glibtoolize --copy --force --automake - fi -fi autoreconf --install --force --verbose diff --git a/configure.ac b/configure.ac index fcfb37735..a19bba4f1 100644 --- a/configure.ac +++ b/configure.ac @@ -2,9 +2,9 @@ # Process this file with autoconf to produce a configure script. AC_PREREQ(2.61) -AC_INIT([stlink],[0.5.0],[davem@devkitpro.org]) +AC_INIT([stlink],[0.5.1],[davem@devkitpro.org]) AC_CONFIG_SRCDIR([src/stlink-common.c]) - +AC_CONFIG_LIBOBJ_DIR([src]) AM_INIT_AUTOMAKE([1.10]) @@ -13,9 +13,14 @@ AC_PROG_CC AC_PROG_INSTALL AC_CANONICAL_HOST AC_CANONICAL_BUILD -AC_PROG_LIBTOOL +AC_PROG_RANLIB +#AC_PROG_LIBTOOL AM_PROG_CC_C_O +AC_CHECK_HEADERS(sys/mman.h) +AC_CHECK_FUNCS(mmap) +AC_REPLACE_FUNCS(mmap pread) + # Checks for libraries. PKG_CHECK_MODULES(USB, libusb-1.0 >= 1.0.0,, AC_MSG_ERROR([*** Required libusb-1.0 >= 1.0.0 not installed ***])) diff --git a/src/mmap.c b/src/mmap.c new file mode 100644 index 000000000..7316389b9 --- /dev/null +++ b/src/mmap.c @@ -0,0 +1,69 @@ +/* mmap.c -- version of mmap for gold. */ + +/* Copyright 2009 Free Software Foundation, Inc. + Written by Vladimir Simonov . + + This file is part of gold. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +//#include "config.h" +//#include "ansidecl.h" + +#include +#include +#ifdef HAVE_STDLIB_H +#include +#endif + +#include "mmap.h" + +extern ssize_t pread (int, void *, size_t, off_t); + +void * +mmap (void *__addr, size_t __len, int __prot, + int __flags, int __fd, long long __offset) +{ + void *ret; + ssize_t count; + + if (__addr || (__fd != -1 && (__prot & PROT_WRITE)) + || (__flags & MAP_SHARED)) + return MAP_FAILED; + + ret = malloc (__len); + if (!ret) + return MAP_FAILED; + + if (__fd == -1) + return ret; + + count = pread (__fd, ret, __len, __offset); + if ((size_t) count != __len) + { + free (ret); + return MAP_FAILED; + } + + return ret; +} + +int +munmap (void *__addr, size_t __len) +{ + free (__addr); + return 0; +} diff --git a/src/mmap.h b/src/mmap.h new file mode 100644 index 000000000..375eafb7b --- /dev/null +++ b/src/mmap.h @@ -0,0 +1,62 @@ +/* mmap.h -- mmap family functions prototypes for gold. */ + +/* Copyright 2009 Free Software Foundation, Inc. + Written by Vladimir Simonov + + This file is part of gold. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#ifndef GOLD_MMAP_H +#define GOLD_MMAP_H + +#ifdef HAVE_SYS_MMAN_H + +#include + +/* Some BSD systems still use MAP_ANON instead of MAP_ANONYMOUS. */ + +#ifndef MAP_ANONYMOUS +# define MAP_ANONYMOUS MAP_ANON +#endif + +#else + +#define PROT_READ 0x1 +#define PROT_WRITE 0x2 + +#define MAP_SHARED 0x01 +#define MAP_PRIVATE 0x02 + +#define MAP_ANONYMOUS 0x20 + +#define MAP_FAILED ((void *) -1) +#endif /* HAVE_SYS_MMAN_H */ + +#ifndef HAVE_MMAP +#ifdef __cplusplus +extern "C" { +#endif +extern void *mmap (void *__addr, size_t __len, int __prot, + int __flags, int __fd, long long __offset); +extern int munmap (void *__addr, size_t __len); +#ifdef __cplusplus +} +#endif + +#endif /* HAVE_MMAP */ + +#endif /* GOLD_MMAP_H */ diff --git a/src/pread.c b/src/pread.c new file mode 100644 index 000000000..4ac61155c --- /dev/null +++ b/src/pread.c @@ -0,0 +1,42 @@ +/* pread.c -- version of pread for gold. */ + +/* Copyright 2006, 2007, 2009 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of gold. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +/* This file implements pread for systems which don't have it. This + file is only compiled if pread is not present on the system. This + is not an exact version of pread, as it does not preserve the + current file offset. */ + +//#include "config.h" + +#include +#include +#include + +extern ssize_t pread (int, void *, size_t, off_t); + +ssize_t +pread (int fd, void *buf, size_t count, off_t offset) +{ + if (lseek(fd, offset, SEEK_SET) != offset) + return -1; + return read(fd, buf, count); +} diff --git a/src/stlink-common.c b/src/stlink-common.c index 26b36cd24..29640fd70 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -9,8 +9,7 @@ #include #include #include -#include - +#include "mmap.h" #include "stlink-common.h" #include "uglylogging.h" diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 3d4a9b798..4cae3ee11 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -85,7 +85,7 @@ #include #include #include -#include +#include "mmap.h" #include "stlink-common.h" #include "stlink-sg.h" diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 8f5c6c410..d945f66ec 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -16,6 +16,18 @@ #define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) #define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) +#ifndef timersub +/* This is a copy from GNU C Library (GNU LGPL 2.1), sys/time.h. */ +# define timersub(a, b, result) \ + do { \ + (result)->tv_sec = (a)->tv_sec - (b)->tv_sec; \ + (result)->tv_usec = (a)->tv_usec - (b)->tv_usec; \ + if ((result)->tv_usec < 0) { \ + --(result)->tv_sec; \ + (result)->tv_usec += 1000000; \ + } \ + } while (0) +#endif enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; From 414ca992d70311ac4f47d776d4b0a2fa304317c4 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sun, 29 Apr 2012 14:09:06 +0100 Subject: [PATCH 0141/1435] update ignores for generated files --- .gitignore | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.gitignore b/.gitignore index c04ecfcdd..d1d6410ff 100644 --- a/.gitignore +++ b/.gitignore @@ -21,3 +21,8 @@ config.status compile st-flash st-util +*.deps* +*.dirstamp +*.a +Makefile +*.exe From 7ed5be296326a770bb8c66eff7f549b8b35327e2 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sun, 29 Apr 2012 14:43:46 +0100 Subject: [PATCH 0142/1435] build with mingw --- Makefile.am | 6 +- configure.ac | 7 +- gdbserver/gdb-remote.c | 6 +- gdbserver/gdb-server.c | 49 ++++---- mingw/mingw.c | 263 +++++++++++++++++++++++++++++++++++++++++ mingw/mingw.h | 61 ++++++++++ 6 files changed, 365 insertions(+), 27 deletions(-) create mode 100644 mingw/mingw.c create mode 100644 mingw/mingw.h diff --git a/Makefile.am b/Makefile.am index 28e11d5e5..a315dd726 100644 --- a/Makefile.am +++ b/Makefile.am @@ -7,7 +7,7 @@ bin_PROGRAMS = st-flash st-util noinst_LIBRARIES = libstlink.a st_flash_SOURCES = flash/main.c -st_util_SOURCES = gdbserver/gdb-remote.c gdbserver/gdb-remote.h gdbserver/gdb-server.c +st_util_SOURCES = gdbserver/gdb-remote.c gdbserver/gdb-remote.h gdbserver/gdb-server.c mingw/mingw.c mingw/mingw.h CFILES = \ src/stlink-common.c \ @@ -28,10 +28,10 @@ libstlink_a_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 libstlink_a_LIBADD = $(LIBOBJS) st_flash_LDADD = libstlink.a -st_flash_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src +st_flash_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_srcdir)/mingw st_util_LDADD = libstlink.a -st_util_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src +st_util_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_srcdir)/mingw EXTRA_DIST = autogen.sh diff --git a/configure.ac b/configure.ac index a19bba4f1..7b4d59041 100644 --- a/configure.ac +++ b/configure.ac @@ -14,10 +14,10 @@ AC_PROG_INSTALL AC_CANONICAL_HOST AC_CANONICAL_BUILD AC_PROG_RANLIB -#AC_PROG_LIBTOOL AM_PROG_CC_C_O AC_CHECK_HEADERS(sys/mman.h) +AC_CHECK_HEADERS(sys/poll.h) AC_CHECK_FUNCS(mmap) AC_REPLACE_FUNCS(mmap pread) @@ -29,6 +29,11 @@ AC_CHECK_LIB([usbpath],[usb_path2devnum],,,-lusb) LIBS="$LIBS $USB_LIBS" CFLAGS="$CFLAGS $USB_CFLAGS" +case "${host}" in + *-mingw32*) + LIBS="$LIBS -lws2_32" + ;; +esac AC_CONFIG_FILES([Makefile]) AC_OUTPUT diff --git a/gdbserver/gdb-remote.c b/gdbserver/gdb-remote.c index f6bf02d26..1b0488e32 100644 --- a/gdbserver/gdb-remote.c +++ b/gdbserver/gdb-remote.c @@ -11,7 +11,11 @@ #include #include #include +#ifdef __MINGW32__ +#include "mingw.h" +#else #include +#endif static const char hex[] = "0123456789abcdef"; @@ -24,7 +28,7 @@ int gdb_send_packet(int fd, char* data) { packet[0] = '$'; uint8_t cksum = 0; - for(int i = 0; i < strlen(data); i++) { + for(unsigned int i = 0; i < strlen(data); i++) { packet[i + 1] = data[i]; cksum += data[i]; } diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 94784fcdb..b0b43d8e2 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -12,10 +12,14 @@ #include #include #include +#ifdef __MINGW32__ +#include "mingw.h" +#else #include #include #include #include +#endif #include @@ -203,15 +207,15 @@ static const char* const memory_map_template = "" "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram 8k - " " - " 0x%x" + " " // code = sram, bootrom or flash; flash is bigger + " " // sram 8k + " " + " 0x%zx" " " " " // peripheral regs " " // cortex regs - " " // bootrom - " " // option byte area + " " // bootrom + " " // option byte area ""; char* make_memory_map(stlink_t *sl) { @@ -291,7 +295,7 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr mask++; } - if((mask != -1) && (mask < 16)) { + if((mask != (uint32_t)-1) && (mask < 16)) { for(i = 0; i < DATA_WATCH_NUM; i++) { // is this an empty slot ? if(data_watches[i].fun == WATCHDISABLED) { @@ -461,7 +465,7 @@ static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { } static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { - int fit_blocks = 0, fit_length = 0; + unsigned int fit_blocks = 0, fit_length = 0; for(struct flash_block* fb = flash_root; fb; fb = fb->next) { /* Block: ------X------Y-------- @@ -553,7 +557,8 @@ int serve(stlink_t *sl, int port) { unsigned int val = 1; setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, &val, sizeof(val)); - struct sockaddr_in serv_addr = {0}; + struct sockaddr_in serv_addr; + bzero(&serv_addr,sizeof(struct sockaddr_in)); serv_addr.sin_family = AF_INET; serv_addr.sin_addr.s_addr = inet_addr("127.0.0.1"); serv_addr.sin_port = htons(port); @@ -576,7 +581,7 @@ int serve(stlink_t *sl, int port) { printf("Listening at *:%d...\n", port); int client = accept(sock, NULL, NULL); - signal (SIGINT, SIG_DFL); + //signal (SIGINT, SIG_DFL); if(client < 0) { perror("accept"); return 1; @@ -633,17 +638,17 @@ int serve(stlink_t *sl, int port) { if(!strcmp(queryName, "Supported")) { reply = strdup("PacketSize=3fff;qXfer:memory-map:read+"); } else if(!strcmp(queryName, "Xfer")) { - char *type, *op, *s_addr, *s_length; + char *type, *op, *__s_addr, *s_length; char *tok = params; char *annex __attribute__((unused)); type = strsep(&tok, ":"); op = strsep(&tok, ":"); annex = strsep(&tok, ":"); - s_addr = strsep(&tok, ","); + __s_addr = strsep(&tok, ","); s_length = tok; - unsigned addr = strtoul(s_addr, NULL, 16), + unsigned addr = strtoul(__s_addr, NULL, 16), length = strtoul(s_length, NULL, 16); #ifdef DEBUG @@ -729,13 +734,13 @@ int serve(stlink_t *sl, int port) { cmdName++; // vCommand -> Command if(!strcmp(cmdName, "FlashErase")) { - char *s_addr, *s_length; + char *__s_addr, *s_length; char *tok = params; - s_addr = strsep(&tok, ","); + __s_addr = strsep(&tok, ","); s_length = tok; - unsigned addr = strtoul(s_addr, NULL, 16), + unsigned addr = strtoul(__s_addr, NULL, 16), length = strtoul(s_length, NULL, 16); #ifdef DEBUG @@ -749,13 +754,13 @@ int serve(stlink_t *sl, int port) { reply = strdup("OK"); } } else if(!strcmp(cmdName, "FlashWrite")) { - char *s_addr, *data; + char *__s_addr, *data; char *tok = params; - s_addr = strsep(&tok, ":"); + __s_addr = strsep(&tok, ":"); data = tok; - unsigned addr = strtoul(s_addr, NULL, 16); + unsigned addr = strtoul(__s_addr, NULL, 16); unsigned data_length = status - (data - packet); // Length of decoded data cannot be more than @@ -763,7 +768,7 @@ int serve(stlink_t *sl, int port) { // Additional byte is reserved for alignment fix. uint8_t *decoded = calloc(data_length + 1, 1); unsigned dec_index = 0; - for(int i = 0; i < data_length; i++) { + for(unsigned int i = 0; i < data_length; i++) { if(data[i] == 0x7d) { i++; decoded[dec_index++] = data[i] ^ 0x20; @@ -919,7 +924,7 @@ int serve(stlink_t *sl, int port) { count : count + 4 - (count % 4)); reply = calloc(count * 2 + 1, 1); - for(int i = 0; i < count; i++) { + for(unsigned int i = 0; i < count; i++) { reply[i * 2 + 0] = hex[sl->q_buf[i + adj_start] >> 4]; reply[i * 2 + 1] = hex[sl->q_buf[i + adj_start] & 0xf]; } @@ -935,7 +940,7 @@ int serve(stlink_t *sl, int port) { stm32_addr_t start = strtoul(s_start, NULL, 16); unsigned count = strtoul(s_count, NULL, 16); - for(int i = 0; i < count; i ++) { + for(unsigned int i = 0; i < count; i ++) { char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; uint8_t byte = strtoul(hex, NULL, 16); sl->q_buf[i] = byte; diff --git a/mingw/mingw.c b/mingw/mingw.c new file mode 100644 index 000000000..c394a160c --- /dev/null +++ b/mingw/mingw.c @@ -0,0 +1,263 @@ +#ifdef __MINGW32__ + +#include "mingw.h" + +#include +#include +#include + +int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) +{ + struct timeval timeout, *toptr; + fd_set ifds, ofds, efds, *ip, *op; + int i, rc; + + /* Set up the file-descriptor sets in ifds, ofds and efds. */ + FD_ZERO(&ifds); + FD_ZERO(&ofds); + FD_ZERO(&efds); + for (i = 0, op = ip = 0; i < nfds; ++i) { + fds[i].revents = 0; + if(fds[i].events & (POLLIN|POLLPRI)) { + ip = &ifds; + FD_SET(fds[i].fd, ip); + } + if(fds[i].events & POLLOUT) { + op = &ofds; + FD_SET(fds[i].fd, op); + } + FD_SET(fds[i].fd, &efds); + } + + /* Set up the timeval structure for the timeout parameter */ + if(timo < 0) { + toptr = 0; + } else { + toptr = &timeout; + timeout.tv_sec = timo / 1000; + timeout.tv_usec = (timo - timeout.tv_sec * 1000) * 1000; + } + +#ifdef DEBUG_POLL + printf("Entering select() sec=%ld usec=%ld ip=%lx op=%lx\n", + (long)timeout.tv_sec, (long)timeout.tv_usec, (long)ip, (long)op); +#endif + rc = select(0, ip, op, &efds, toptr); +#ifdef DEBUG_POLL + printf("Exiting select rc=%d\n", rc); +#endif + + if(rc <= 0) + return rc; + + if(rc > 0) { + for (i = 0; i < nfds; ++i) { + int fd = fds[i].fd; + if(fds[i].events & (POLLIN|POLLPRI) && FD_ISSET(fd, &ifds)) + fds[i].revents |= POLLIN; + if(fds[i].events & POLLOUT && FD_ISSET(fd, &ofds)) + fds[i].revents |= POLLOUT; + if(FD_ISSET(fd, &efds)) + /* Some error was detected ... should be some way to know. */ + fds[i].revents |= POLLHUP; +#ifdef DEBUG_POLL + printf("%d %d %d revent = %x\n", + FD_ISSET(fd, &ifds), FD_ISSET(fd, &ofds), FD_ISSET(fd, &efds), + fds[i].revents + ); +#endif + } + } + return rc; +} +static void +set_connect_errno(int winsock_err) +{ + switch(winsock_err) { + case WSAEINVAL: + case WSAEALREADY: + case WSAEWOULDBLOCK: + errno = EINPROGRESS; + break; + default: + errno = winsock_err; + break; + } +} + +static void +set_socket_errno(int winsock_err) +{ + switch(winsock_err) { + case WSAEWOULDBLOCK: + errno = EAGAIN; + break; + default: + errno = winsock_err; + break; + } +} +/* + * A wrapper around the socket() function. The purpose of this wrapper + * is to ensure that the global errno symbol is set if an error occurs, + * even if we are using winsock. + */ +SOCKET +win32_socket(int domain, int type, int protocol) +{ + SOCKET fd = socket(domain, type, protocol); + if(fd == INVALID_SOCKET) { + set_socket_errno(WSAGetLastError()); + } + return fd; +} +/* + * A wrapper around the connect() function. The purpose of this wrapper + * is to ensure that the global errno symbol is set if an error occurs, + * even if we are using winsock. + */ +int +win32_connect(SOCKET fd, struct sockaddr *addr, socklen_t addr_len) +{ + int rc = connect(fd, addr, addr_len); + assert(rc == 0 || rc == SOCKET_ERROR); + if(rc == SOCKET_ERROR) { + set_connect_errno(WSAGetLastError()); + } + return rc; +} + +/* + * A wrapper around the accept() function. The purpose of this wrapper + * is to ensure that the global errno symbol is set if an error occurs, + * even if we are using winsock. + */ +SOCKET +win32_accept(SOCKET fd, struct sockaddr *addr, socklen_t *addr_len) +{ + SOCKET newfd = accept(fd, addr, addr_len); + if(newfd == INVALID_SOCKET) { + set_socket_errno(WSAGetLastError()); + newfd = -1; + } + return newfd; +} + +/* + * A wrapper around the shutdown() function. The purpose of this wrapper + * is to ensure that the global errno symbol is set if an error occurs, + * even if we are using winsock. + */ +int +win32_shutdown(SOCKET fd, int mode) +{ + int rc = shutdown(fd, mode); + assert(rc == 0 || rc == SOCKET_ERROR); + if(rc == SOCKET_ERROR) { + set_socket_errno(WSAGetLastError()); + } + return rc; +} +int win32_close_socket(SOCKET fd) { + int rc; + + rc = closesocket(fd); + return 0; +} + + +int win32_write_socket(SOCKET fd, void *buf, int n) +{ + int rc = send(fd, buf, n, 0); + if(rc == SOCKET_ERROR) { + set_socket_errno(WSAGetLastError()); + } + return rc; +} + +int win32_read_socket(SOCKET fd, void *buf, int n) +{ + int rc = recv(fd, buf, n, 0); + if(rc == SOCKET_ERROR) { + set_socket_errno(WSAGetLastError()); + } + return rc; +} + + +char * win32_strtok_r(char *s, const char *delim, char **lasts) +{ + register char *spanp; + register int c, sc; + char *tok; + + + if (s == NULL && (s = *lasts) == NULL) + return (NULL); + + /* + * Skip (span) leading delimiters (s += strspn(s, delim), sort of). + */ +cont: + c = *s++; + for (spanp = (char *)delim; (sc = *spanp++) != 0;) { + if (c == sc) + goto cont; + } + + if (c == 0) { /* no non-delimiter characters */ + *lasts = NULL; + return (NULL); + } + tok = s - 1; + + /* + * Scan token (scan for delimiters: s += strcspn(s, delim), sort of). + * Note that delim must have one NUL; we stop if we see that, too. + */ + for (;;) { + c = *s++; + spanp = (char *)delim; + do { + if ((sc = *spanp++) == c) { + if (c == 0) + s = NULL; + else + s[-1] = 0; + *lasts = s; + return (tok); + } + } while (sc != 0); + } + /* NOTREACHED */ +} + +char *win32_strsep (char **stringp, const char *delim) +{ + register char *s; + register const char *spanp; + register int c, sc; + char *tok; + + if ((s = *stringp) == NULL) + return (NULL); + for (tok = s;;) { + c = *s++; + spanp = delim; + do { + if ((sc = *spanp++) == c) { + if (c == 0) + s = NULL; + else + s[-1] = 0; + *stringp = s; + return (tok); + } + } while (sc != 0); + } + /* NOTREACHED */ +} + +#endif + + diff --git a/mingw/mingw.h b/mingw/mingw.h new file mode 100644 index 000000000..93b3702d2 --- /dev/null +++ b/mingw/mingw.h @@ -0,0 +1,61 @@ +#ifdef __MINGW32__ + +#include + +#include + +#define ENOTCONN WSAENOTCONN +#define EWOULDBLOCK WSAEWOULDBLOCK +#define ENOBUFS WSAENOBUFS +#define ECONNRESET WSAECONNRESET +#define ESHUTDOWN WSAESHUTDOWN +#define EAFNOSUPPORT WSAEAFNOSUPPORT +#define EPROTONOSUPPORT WSAEPROTONOSUPPORT +#define EINPROGRESS WSAEINPROGRESS +#define EISCONN WSAEISCONN + +/* winsock doesn't feature poll(), so there is a version implemented + * in terms of select() in mingw.c. The following definitions + * are copied from linux man pages. A poll() macro is defined to + * call the version in mingw.c. + */ +#define POLLIN 0x0001 /* There is data to read */ +#define POLLPRI 0x0002 /* There is urgent data to read */ +#define POLLOUT 0x0004 /* Writing now will not block */ +#define POLLERR 0x0008 /* Error condition */ +#define POLLHUP 0x0010 /* Hung up */ +#define POLLNVAL 0x0020 /* Invalid request: fd not open */ +struct pollfd { + SOCKET fd; /* file descriptor */ + short events; /* requested events */ + short revents; /* returned events */ +}; +#define poll(x, y, z) win32_poll(x, y, z) + +/* These wrappers do nothing special except set the global errno variable if + * an error occurs (winsock doesn't do this by default). They set errno + * to unix-like values (i.e. WSAEWOULDBLOCK is mapped to EAGAIN), so code + * outside of this file "shouldn't" have to worry about winsock specific error + * handling. + */ +#define socket(x, y, z) win32_socket(x, y, z) +#define connect(x, y, z) win32_connect(x, y, z) +#define accept(x, y, z) win32_accept(x, y, z) +#define shutdown(x, y) win32_shutdown(x, y) + +/* Winsock uses int instead of the usual socklen_t */ +typedef int socklen_t; + +int win32_poll(struct pollfd *, unsigned int, int); +SOCKET win32_socket(int, int, int); +int win32_connect(SOCKET, struct sockaddr*, socklen_t); +SOCKET win32_accept(SOCKET, struct sockaddr*, socklen_t *); +int win32_shutdown(SOCKET, int); + +#define strtok_r(x, y, z) win32_strtok_r(x, y, z) +#define strsep(x,y) win32_strsep(x,y) + +char *win32_strtok_r(char *s, const char *delim, char **lasts); +char *win32_strsep(char **stringp, const char *delim); + +#endif From 24171a2fd824408563ee747718066505df95c42a Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sun, 29 Apr 2012 18:45:37 +0100 Subject: [PATCH 0143/1435] use correct headers --- mingw/mingw.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/mingw/mingw.h b/mingw/mingw.h index 93b3702d2..a64da570f 100644 --- a/mingw/mingw.h +++ b/mingw/mingw.h @@ -2,7 +2,8 @@ #include -#include +#define _USE_W32_SOCKETS 1 +#include #define ENOTCONN WSAENOTCONN #define EWOULDBLOCK WSAEWOULDBLOCK From 6db2766e3fce0148fa4a5a5dc2a86fbbe5931415 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sun, 29 Apr 2012 18:47:38 +0100 Subject: [PATCH 0144/1435] undefine macros for socket redirection, fix warnings --- mingw/mingw.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/mingw/mingw.c b/mingw/mingw.c index c394a160c..0cae043c1 100644 --- a/mingw/mingw.c +++ b/mingw/mingw.c @@ -2,6 +2,11 @@ #include "mingw.h" +#undef socket +#undef connect +#undef accept +#undef shutdown + #include #include #include @@ -10,7 +15,7 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { struct timeval timeout, *toptr; fd_set ifds, ofds, efds, *ip, *op; - int i, rc; + unsigned int i, rc; /* Set up the file-descriptor sets in ifds, ofds and efds. */ FD_ZERO(&ifds); @@ -51,7 +56,7 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) return rc; if(rc > 0) { - for (i = 0; i < nfds; ++i) { + for ( i = 0; i < nfds; ++i) { int fd = fds[i].fd; if(fds[i].events & (POLLIN|POLLPRI) && FD_ISSET(fd, &ifds)) fds[i].revents |= POLLIN; @@ -162,7 +167,7 @@ int win32_close_socket(SOCKET fd) { int rc; rc = closesocket(fd); - return 0; + return rc; } From 2559ab0c30b6782e67c9a0a1622c04bde9ee51f5 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sun, 29 Apr 2012 18:48:26 +0100 Subject: [PATCH 0145/1435] use WSAStartup on windows, replace bzero with memset --- gdbserver/gdb-server.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index b0b43d8e2..bd478573f 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -170,8 +170,20 @@ int main(int argc, char** argv) { current_memory_map = make_memory_map(sl); +#ifdef __MINGW32__ + WSADATA wsadata; + if (WSAStartup(MAKEWORD(2,2),&wsadata) !=0 ) { + goto winsock_error; + } +#endif + while(serve(sl, state.listen_port) == 0); +#ifdef __MINGW32__ +winsock_error: + WSACleanup(); +#endif + /* Switch back to mass storage mode before closing. */ stlink_run(sl); stlink_exit_debug_mode(sl); @@ -558,7 +570,7 @@ int serve(stlink_t *sl, int port) { setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, &val, sizeof(val)); struct sockaddr_in serv_addr; - bzero(&serv_addr,sizeof(struct sockaddr_in)); + memset(&serv_addr,0,sizeof(struct sockaddr_in)); serv_addr.sin_family = AF_INET; serv_addr.sin_addr.s_addr = inet_addr("127.0.0.1"); serv_addr.sin_port = htons(port); From c5b021c6ab9a6a7fef9f3cf0f43ff2c26cd1b9de Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sun, 29 Apr 2012 18:49:08 +0100 Subject: [PATCH 0146/1435] allow use of %zx format specifier om mingw --- configure.ac | 1 + 1 file changed, 1 insertion(+) diff --git a/configure.ac b/configure.ac index 7b4d59041..761591a6b 100644 --- a/configure.ac +++ b/configure.ac @@ -32,6 +32,7 @@ CFLAGS="$CFLAGS $USB_CFLAGS" case "${host}" in *-mingw32*) LIBS="$LIBS -lws2_32" + CPPFLAGS="-D__USE_MINGW_ANSI_STDIO=1 $CPPFLAGS" ;; esac AC_CONFIG_FILES([Makefile]) From 49bafd873992d96cd95184d45d5bd24bd657a323 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sun, 29 Apr 2012 19:30:27 +0100 Subject: [PATCH 0147/1435] wrap read/write socket functions on mingw --- mingw/mingw.c | 4 ++-- mingw/mingw.h | 14 ++++++++++---- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/mingw/mingw.c b/mingw/mingw.c index 0cae043c1..493dcbaa2 100644 --- a/mingw/mingw.c +++ b/mingw/mingw.c @@ -171,7 +171,7 @@ int win32_close_socket(SOCKET fd) { } -int win32_write_socket(SOCKET fd, void *buf, int n) +ssize_t win32_write_socket(SOCKET fd, void *buf, int n) { int rc = send(fd, buf, n, 0); if(rc == SOCKET_ERROR) { @@ -180,7 +180,7 @@ int win32_write_socket(SOCKET fd, void *buf, int n) return rc; } -int win32_read_socket(SOCKET fd, void *buf, int n) +ssize_t win32_read_socket(SOCKET fd, void *buf, int n) { int rc = recv(fd, buf, n, 0); if(rc == SOCKET_ERROR) { diff --git a/mingw/mingw.h b/mingw/mingw.h index a64da570f..28c7a82e0 100644 --- a/mingw/mingw.h +++ b/mingw/mingw.h @@ -39,10 +39,12 @@ struct pollfd { * outside of this file "shouldn't" have to worry about winsock specific error * handling. */ -#define socket(x, y, z) win32_socket(x, y, z) -#define connect(x, y, z) win32_connect(x, y, z) -#define accept(x, y, z) win32_accept(x, y, z) -#define shutdown(x, y) win32_shutdown(x, y) +#define socket(x, y, z) win32_socket(x, y, z) +#define connect(x, y, z) win32_connect(x, y, z) +#define accept(x, y, z) win32_accept(x, y, z) +#define shutdown(x, y) win32_shutdown(x, y) +#define read(x, y, z) win32_read_socket(x, y, z) +#define write(x, y, z) win32_write_socket(x, y, z) /* Winsock uses int instead of the usual socklen_t */ typedef int socklen_t; @@ -59,4 +61,8 @@ int win32_shutdown(SOCKET, int); char *win32_strtok_r(char *s, const char *delim, char **lasts); char *win32_strsep(char **stringp, const char *delim); +ssize_t win32_read_socket(SOCKET fd, void *buf, int n); +ssize_t win32_write_socket(SOCKET fd, void *buf, int n); + + #endif From c6b6f4c51d41451b613c9b1c29d40e39eaa4fce2 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sun, 29 Apr 2012 19:44:51 +0100 Subject: [PATCH 0148/1435] prototype main function properly --- example/blink/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/example/blink/main.c b/example/blink/main.c index 0a38069be..b70a136a3 100644 --- a/example/blink/main.c +++ b/example/blink/main.c @@ -1,7 +1,7 @@ /* missing type */ typedef unsigned int uint32_t; - +void main(void); /* hardware configuration */ From b61a06a8b71c68a40c9d7185a14c94079711b574 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Fri, 11 May 2012 14:11:12 -0400 Subject: [PATCH 0149/1435] Fixed issue #66 - Fixed the F4 memory map to include CCM RAM. https://github.com/texane/stlink/issues/66 --- gdbserver/gdb-server.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 94784fcdb..f6ec15bf5 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -182,7 +182,8 @@ static const char* const memory_map_template_F4 = " \"http://sourceware.org/gdb/gdb-memory-map.dtd\">" "" " " // code = sram, bootrom or flash; flash is bigger - " " // sram + " " // ccm ram + " " // sram " " //Sectors 0..3 " 0x4000" //16kB " " From d02326726a82f9c65263205f587f13ec11c7e7f0 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sun, 13 May 2012 22:54:26 +0100 Subject: [PATCH 0150/1435] fix signedness warning --- gdbserver/gdb-remote.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbserver/gdb-remote.c b/gdbserver/gdb-remote.c index 1b0488e32..edf53389b 100644 --- a/gdbserver/gdb-remote.c +++ b/gdbserver/gdb-remote.c @@ -20,7 +20,7 @@ static const char hex[] = "0123456789abcdef"; int gdb_send_packet(int fd, char* data) { - unsigned length = strlen(data) + 5; + int length = strlen(data) + 5; char* packet = malloc(length); /* '$' data (hex) '#' cksum (hex) */ memset(packet, 0, length); From 947c1409e371f5ec0dca8a851f5b681d722d6ab5 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sun, 13 May 2012 22:55:41 +0100 Subject: [PATCH 0151/1435] cast to avoid pointer warning --- gdbserver/gdb-server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index bd478573f..0d67abd0f 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -567,7 +567,7 @@ int serve(stlink_t *sl, int port) { } unsigned int val = 1; - setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, &val, sizeof(val)); + setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val)); struct sockaddr_in serv_addr; memset(&serv_addr,0,sizeof(struct sockaddr_in)); From 80d603582862ea0332dc301352655e8c086776dd Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sun, 13 May 2012 22:57:27 +0100 Subject: [PATCH 0152/1435] use sys/time.h for mingw compatiblity, use LIBUSB_CALL modifier for callback --- src/stlink-usb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index d945f66ec..580722766 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -2,7 +2,7 @@ #include #include #include -#include +#include #include #include @@ -57,7 +57,7 @@ struct trans_ctx { volatile unsigned long flags; }; -static void on_trans_done(struct libusb_transfer * trans) { +static void LIBUSB_CALL on_trans_done(struct libusb_transfer * trans) { struct trans_ctx * const ctx = trans->user_data; if (trans->status != LIBUSB_TRANSFER_COMPLETED) From 802049ed7da8ac6074120c127cf2ac096f67316a Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Mon, 14 May 2012 10:55:55 +0100 Subject: [PATCH 0153/1435] bump stlink version --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 761591a6b..866d8bbd5 100644 --- a/configure.ac +++ b/configure.ac @@ -2,7 +2,7 @@ # Process this file with autoconf to produce a configure script. AC_PREREQ(2.61) -AC_INIT([stlink],[0.5.1],[davem@devkitpro.org]) +AC_INIT([stlink],[0.5.2],[davem@devkitpro.org]) AC_CONFIG_SRCDIR([src/stlink-common.c]) AC_CONFIG_LIBOBJ_DIR([src]) AM_INIT_AUTOMAKE([1.10]) From c0eb32267c56b2eb63e6b7ecdf0d2980e158df68 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Mon, 14 May 2012 10:57:41 +0100 Subject: [PATCH 0154/1435] ignore elf files in example --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index d1d6410ff..0a705b55b 100644 --- a/.gitignore +++ b/.gitignore @@ -26,3 +26,4 @@ st-util *.a Makefile *.exe +example/blink/*.elf From 8e4efc36028140a7ac7fffd181040654a4931bd1 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Wed, 16 May 2012 22:15:38 +0100 Subject: [PATCH 0155/1435] reimplement mingw mmap --- configure.ac | 3 +-- src/mmap.c | 74 ++++++++++++++-------------------------------------- src/mmap.h | 59 ++++++++++------------------------------- src/pread.c | 42 ----------------------------- 4 files changed, 34 insertions(+), 144 deletions(-) delete mode 100644 src/pread.c diff --git a/configure.ac b/configure.ac index 866d8bbd5..f7feed2cc 100644 --- a/configure.ac +++ b/configure.ac @@ -18,8 +18,7 @@ AM_PROG_CC_C_O AC_CHECK_HEADERS(sys/mman.h) AC_CHECK_HEADERS(sys/poll.h) -AC_CHECK_FUNCS(mmap) -AC_REPLACE_FUNCS(mmap pread) +AC_REPLACE_FUNCS(mmap) # Checks for libraries. PKG_CHECK_MODULES(USB, libusb-1.0 >= 1.0.0,, diff --git a/src/mmap.c b/src/mmap.c index 7316389b9..8a0a2e361 100644 --- a/src/mmap.c +++ b/src/mmap.c @@ -1,69 +1,33 @@ -/* mmap.c -- version of mmap for gold. */ - -/* Copyright 2009 Free Software Foundation, Inc. - Written by Vladimir Simonov . - - This file is part of gold. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -//#include "config.h" -//#include "ansidecl.h" - #include #include -#ifdef HAVE_STDLIB_H #include -#endif +#include #include "mmap.h" -extern ssize_t pread (int, void *, size_t, off_t); - -void * -mmap (void *__addr, size_t __len, int __prot, - int __flags, int __fd, long long __offset) -{ - void *ret; - ssize_t count; +void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offset) { - if (__addr || (__fd != -1 && (__prot & PROT_WRITE)) - || (__flags & MAP_SHARED)) - return MAP_FAILED; + void *buf; + ssize_t count; - ret = malloc (__len); - if (!ret) - return MAP_FAILED; + if ( addr || fd == -1 || (prot & PROT_WRITE)) return MAP_FAILED; - if (__fd == -1) - return ret; + buf = malloc(len); + if ( NULL == buf ) return MAP_FAILED; - count = pread (__fd, ret, __len, __offset); - if ((size_t) count != __len) - { - free (ret); - return MAP_FAILED; - } + if (lseek(fd,offset,SEEK_SET) != offset) return MAP_FAILED; + + count = read(fd, buf, len); + + if (count != len) { + free (buf); + return MAP_FAILED; + } - return ret; + return buf; } -int -munmap (void *__addr, size_t __len) -{ - free (__addr); - return 0; +int munmap (void *addr, size_t len) { + free (addr); + return 0; } diff --git a/src/mmap.h b/src/mmap.h index 375eafb7b..bff766c4a 100644 --- a/src/mmap.h +++ b/src/mmap.h @@ -1,62 +1,31 @@ -/* mmap.h -- mmap family functions prototypes for gold. */ - -/* Copyright 2009 Free Software Foundation, Inc. - Written by Vladimir Simonov - - This file is part of gold. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -#ifndef GOLD_MMAP_H -#define GOLD_MMAP_H +#ifndef STLINK_MMAP_H +#define STLINK_MMAP_H #ifdef HAVE_SYS_MMAN_H - #include - -/* Some BSD systems still use MAP_ANON instead of MAP_ANONYMOUS. */ - -#ifndef MAP_ANONYMOUS -# define MAP_ANONYMOUS MAP_ANON -#endif - #else -#define PROT_READ 0x1 -#define PROT_WRITE 0x2 +#define PROT_READ (1<<0) +#define PROT_WRITE (1<<1) -#define MAP_SHARED 0x01 -#define MAP_PRIVATE 0x02 +#define MAP_SHARED (1<<0) +#define MAP_PRIVATE (1<<1) -#define MAP_ANONYMOUS 0x20 +#define MAP_ANONYMOUS (1<<5) -#define MAP_FAILED ((void *) -1) -#endif /* HAVE_SYS_MMAN_H */ +#define MAP_FAILED ((void *)-1) -#ifndef HAVE_MMAP #ifdef __cplusplus extern "C" { #endif -extern void *mmap (void *__addr, size_t __len, int __prot, - int __flags, int __fd, long long __offset); -extern int munmap (void *__addr, size_t __len); + +void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); +int munmap(void *addr, size_t len); + #ifdef __cplusplus } #endif -#endif /* HAVE_MMAP */ +#endif /* HAVE_SYS_MMAN_H */ -#endif /* GOLD_MMAP_H */ +#endif /* STLINK_MMAP_H */ diff --git a/src/pread.c b/src/pread.c deleted file mode 100644 index 4ac61155c..000000000 --- a/src/pread.c +++ /dev/null @@ -1,42 +0,0 @@ -/* pread.c -- version of pread for gold. */ - -/* Copyright 2006, 2007, 2009 Free Software Foundation, Inc. - Written by Ian Lance Taylor . - - This file is part of gold. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - -/* This file implements pread for systems which don't have it. This - file is only compiled if pread is not present on the system. This - is not an exact version of pread, as it does not preserve the - current file offset. */ - -//#include "config.h" - -#include -#include -#include - -extern ssize_t pread (int, void *, size_t, off_t); - -ssize_t -pread (int fd, void *buf, size_t count, off_t offset) -{ - if (lseek(fd, offset, SEEK_SET) != offset) - return -1; - return read(fd, buf, count); -} From 5bbef2f18bd36e510dcff6aab43d65203aeb3e73 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Wed, 16 May 2012 22:22:54 +0100 Subject: [PATCH 0156/1435] fix whitespace --- src/mmap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mmap.c b/src/mmap.c index 8a0a2e361..9c631da2d 100644 --- a/src/mmap.c +++ b/src/mmap.c @@ -16,9 +16,9 @@ void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offs if ( NULL == buf ) return MAP_FAILED; if (lseek(fd,offset,SEEK_SET) != offset) return MAP_FAILED; - + count = read(fd, buf, len); - + if (count != len) { free (buf); return MAP_FAILED; From 89016d1d86de485ecb1f75312f17ee3574d07f0b Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Wed, 16 May 2012 22:44:31 +0100 Subject: [PATCH 0157/1435] add COPYING to repository to avoid license confusion --- .gitignore | 1 - COPYING | 27 +++++++++++++++++++++++++++ 2 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 COPYING diff --git a/.gitignore b/.gitignore index 0a705b55b..cf2f1a448 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,3 @@ -COPYING INSTALL Makefile.in aclocal.m4 diff --git a/COPYING b/COPYING new file mode 100644 index 000000000..37b124eba --- /dev/null +++ b/COPYING @@ -0,0 +1,27 @@ +Copyright (c) 2011 The "Capt'ns Missing Link" Authors. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + + * Redistributions of source code must retain the above copyright +notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above +copyright notice, this list of conditions and the following disclaimer +in the documentation and/or other materials provided with the +distribution. + * Neither the name of Martin Capitanio nor the names of its +contributors may be used to endorse or promote products derived from +this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. From 4080a3ecbb8fcf7ac83cc53903a0b8f379cc3fc0 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Wed, 16 May 2012 23:31:07 +0100 Subject: [PATCH 0158/1435] bump version --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index f7feed2cc..1f00f3a80 100644 --- a/configure.ac +++ b/configure.ac @@ -2,7 +2,7 @@ # Process this file with autoconf to produce a configure script. AC_PREREQ(2.61) -AC_INIT([stlink],[0.5.2],[davem@devkitpro.org]) +AC_INIT([stlink],[0.5.3],[davem@devkitpro.org]) AC_CONFIG_SRCDIR([src/stlink-common.c]) AC_CONFIG_LIBOBJ_DIR([src]) AM_INIT_AUTOMAKE([1.10]) From 299c5d272f58c7cb803d6a61ca16d9551c7697e5 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Wed, 16 May 2012 23:41:42 +0100 Subject: [PATCH 0159/1435] use BSD timersub --- src/stlink-usb.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 580722766..20e5cd22e 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -16,17 +16,18 @@ #define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) #define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) -#ifndef timersub -/* This is a copy from GNU C Library (GNU LGPL 2.1), sys/time.h. */ -# define timersub(a, b, result) \ - do { \ - (result)->tv_sec = (a)->tv_sec - (b)->tv_sec; \ - (result)->tv_usec = (a)->tv_usec - (b)->tv_usec; \ - if ((result)->tv_usec < 0) { \ - --(result)->tv_sec; \ - (result)->tv_usec += 1000000; \ - } \ - } while (0) +/* code from bsd timersub.h +http://www.gnu-darwin.org/www001/src/ports/net/libevnet/work/libevnet-0.3.8/libnostd/bsd/sys/time/timersub.h.html +*/ +#if !defined timersub +#define timersub(a, b, r) do { \ + (r)->tv_sec = (a)->tv_sec - (b)->tv_sec; \ + (r)->tv_usec = (a)->tv_usec - (b)->tv_usec; \ + if ((r)->tv_usec < 0) { \ + --(r)->tv_sec; \ + (r)->tv_usec += 1000000; \ + } \ +} while (0) #endif enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; From fc85ba71f1bd1eeebbc36e69bc5d667c812784b3 Mon Sep 17 00:00:00 2001 From: Fabien Le Mentec Date: Thu, 17 May 2012 01:39:16 -0500 Subject: [PATCH 0160/1435] [ fix ] missing LIBUSB_CALL definition --- src/stlink-usb.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 20e5cd22e..72ffda177 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -58,6 +58,10 @@ struct trans_ctx { volatile unsigned long flags; }; +#ifndef LIBUSB_CALL +# define LIBUSB_CALL +#endif + static void LIBUSB_CALL on_trans_done(struct libusb_transfer * trans) { struct trans_ctx * const ctx = trans->user_data; From 105b293a1501154c69663b4fb29671a8d2cc62ec Mon Sep 17 00:00:00 2001 From: Tectu Date: Fri, 25 May 2012 17:05:44 +0200 Subject: [PATCH 0161/1435] fixed option bytes amount --- gdbserver/gdb-server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 91fb8dced..7a525d535 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -228,7 +228,7 @@ static const char* const memory_map_template = " " // peripheral regs " " // cortex regs " " // bootrom - " " // option byte area + " " // option byte area ""; char* make_memory_map(stlink_t *sl) { From a303d9fe7a698d85f87500e0ad7229a1a76d4b21 Mon Sep 17 00:00:00 2001 From: Fabien Le Mentec Date: Sat, 26 May 2012 09:48:48 -0500 Subject: [PATCH 0162/1435] [ fix ] apply jserv@0xlab.org patch, 0001-trivial-documentation-fix-for-st-util-path --- AUTHORS | 1 + README | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/AUTHORS b/AUTHORS index 8153669c7..1096c1735 100644 --- a/AUTHORS +++ b/AUTHORS @@ -14,3 +14,4 @@ bravikov@gmail.com jnosky - codegrinder69@hotmail.com marpe@mimuw.edu.pl marco.cassinerio@gmail.com +jserv@0xlab.org \ No newline at end of file diff --git a/README b/README index bb06f60a9..d99337c2a 100644 --- a/README +++ b/README @@ -37,11 +37,11 @@ You're ready to go :) To run the gdb server, do (you do not need sudo if you have set up permissions correctly): -$ make && [sudo] ./gdbserver/st-util +$ make && [sudo] ./st-util There are a few options: -./gdbserver/st-util - usage: +./st-util - usage: -h, --help Print this help -vXX, --verbose=XX specify a specific verbosity level (0..99) From 14db250dcc263ec5bcc959c31430dbde5caff868 Mon Sep 17 00:00:00 2001 From: Fabien Le Mentec Date: Sun, 3 Jun 2012 01:40:27 -0500 Subject: [PATCH 0163/1435] [ update ] F0 chip id --- src/stlink-common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index 29640fd70..3f8a7f0e5 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -394,6 +394,7 @@ uint32_t stlink_core_id(stlink_t *sl) { uint32_t stlink_chip_id(stlink_t *sl) { uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000); + if (chip_id == 0) chip_id = stlink_read_debug32(sl, 0xE000ED00); return chip_id; } From 9ccb398ab73804d9cd2eba060a7f5a42f7d76aeb Mon Sep 17 00:00:00 2001 From: Mike Szczys Date: Sun, 3 Jun 2012 10:39:34 -0500 Subject: [PATCH 0164/1435] Corrected F0 DBGMCU_IDCODE register address --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 3f8a7f0e5..f0a0c236e 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -394,7 +394,7 @@ uint32_t stlink_core_id(stlink_t *sl) { uint32_t stlink_chip_id(stlink_t *sl) { uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000); - if (chip_id == 0) chip_id = stlink_read_debug32(sl, 0xE000ED00); + if (chip_id == 0) chip_id = stlink_read_debug32(sl, 0x40015800); //Try Corex M0 DBGMCU_IDCODE register address return chip_id; } From 8975f92574d5d6476ef2d86407247a2f3a6d2e13 Mon Sep 17 00:00:00 2001 From: Mike Szczys Date: Sun, 3 Jun 2012 10:44:48 -0500 Subject: [PATCH 0165/1435] Added memory map for STM32F05xxx chips --- src/stlink-common.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/stlink-common.h b/src/stlink-common.h index 6fcb2194e..ee59094b6 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -221,6 +221,17 @@ extern "C" { .sram_size = 0x18000, .bootrom_base = 0x1fffe000, .bootrom_size = 0x1800 + }, + { + //Use this as an example for mapping future chips: + //RM0091 document was used to find these paramaters + .chip_id = 0x440, + .description = "F0 device", + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 } }; From bdb1a498df58f00c84378ff54e9077f1bfb197a7 Mon Sep 17 00:00:00 2001 From: Mike Szczys Date: Sun, 3 Jun 2012 10:47:18 -0500 Subject: [PATCH 0166/1435] Added STM32F0-Discovery board to the blink example code --- example/blink/Makefile | 5 ++++- example/blink/main.c | 20 ++++++++++++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/example/blink/Makefile b/example/blink/Makefile index cf7221da8..60fab84c8 100644 --- a/example/blink/Makefile +++ b/example/blink/Makefile @@ -12,8 +12,9 @@ DEF_CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000 CFLAGS_VL=$(DEF_CFLAGS) -mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1 CFLAGS_L=$(DEF_CFLAGS) -mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY CFLAGS_F4=$(DEF_CFLAGS) -mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1 +CFLAGS_F0=$(DEF_CFLAGS) -mcpu=cortex-m0 -DCONFIG_STM32F0_DISCOVERY=1 -all: blink_32VL.elf blink_32L.elf blink_F4.elf +all: blink_32VL.elf blink_32L.elf blink_F4.elf blink_F0.elf %.bin: %.elf $(OBJCOPY) -O binary $^ $@ @@ -24,6 +25,8 @@ blink_32L.elf: main.c $(CC) $(CFLAGS_L) $^ -o $@ blink_F4.elf: main.c $(CC) $(CFLAGS_F4) $^ -o $@ +blink_F0.elf: main.c + $(CC) $(CFLAGS_F0) $^ -o $@ clean: rm -rf *.elf diff --git a/example/blink/main.c b/example/blink/main.c index b70a136a3..26fcca029 100644 --- a/example/blink/main.c +++ b/example/blink/main.c @@ -58,6 +58,26 @@ static inline void setup_leds(void) (1 << (13 * 2)) | (1 << (14 * 2)) | (1 << (15 * 2)); } +#elif CONFIG_STM32F0_DISCOVERY + +#define GPIOC 0x48000800 /* port C */ +#define GPIOC_MODER (GPIOC + 0x00) /* port mode register */ +#define LED_PORT_ODR (GPIOC + 0x14) /* port output data register */ + +#define LED_BLUE (1 << 8) /* port C, pin 8 */ +#define LED_GREEN (1 << 9) /* port C, pin 9 */ +#define LED_ORANGE 0 +#define LED_RED 0 + +void _tmain(void) { + main(); +} +static inline void setup_leds(void) +{ + /* configure port 8 and 9 as output */ + *(volatile uint32_t*)GPIOC_MODER |= (1 << (9* 2)) | (1 << (8 * 2)); +} + #else #error "Architecture must be defined!" #endif /* otherwise, error */ From cfb1e862525f95252e367ccc38845da5a9a017af Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 7 Jun 2012 18:03:23 +0200 Subject: [PATCH 0167/1435] st-flash: Honor size, if given --- flash/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/flash/main.c b/flash/main.c index 24287456b..4716b66e1 100644 --- a/flash/main.c +++ b/flash/main.c @@ -154,10 +154,10 @@ int main(int ac, char** av) } else /* read */ { - if ((o.addr >= sl->flash_base) && + if ((o.addr >= sl->flash_base) && (o.size == 0) && (o.addr < sl->flash_base + sl->flash_size)) o.size = sl->flash_size; - else if ((o.addr >= sl->sram_base) && + else if ((o.addr >= sl->sram_base) && (o.size == 0) && (o.addr < sl->sram_base + sl->sram_size)) o.size = sl->sram_size; err = stlink_fread(sl, o.filename, o.addr, o.size); From 0e7ee109f6c37dd2f1acfdc861eb12803e96eabb Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 7 Jun 2012 18:13:43 +0200 Subject: [PATCH 0168/1435] Add \n to WLOG when no STLINK found --- src/stlink-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 72ffda177..a25f7ec55 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -652,7 +652,7 @@ stlink_t* stlink_open_usb(const int verbose) { if (slu->usb_handle == NULL) { slu->usb_handle = libusb_open_device_with_vid_pid(slu->libusb_ctx, USB_ST_VID, USB_STLINK_PID); if (slu->usb_handle == NULL) { - WLOG("Couldn't find any ST-Link/V2 devices"); + WLOG("Couldn't find any ST-Link/V2 devices\n"); goto on_error; } slu->protocoll = 1; From 8151bf5c4a443608d4fec15cf7dfe79a02cdd096 Mon Sep 17 00:00:00 2001 From: Vegard Storheil Eriksen Date: Thu, 7 Jun 2012 23:16:19 +0200 Subject: [PATCH 0169/1435] Added flash loader stub for F2/F4. --- flashloaders/stm32f4.s | 32 ++++++++++++++++++++ src/stlink-common.c | 68 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+) create mode 100644 flashloaders/stm32f4.s diff --git a/flashloaders/stm32f4.s b/flashloaders/stm32f4.s new file mode 100644 index 000000000..6cad73042 --- /dev/null +++ b/flashloaders/stm32f4.s @@ -0,0 +1,32 @@ +.global start +.syntax unified + +@ r0 = source +@ r1 = target +@ r2 = wordcount +@ r3 = flash_base +@ r4 = temp + +start: + ldr r3, flash_base +next: + cbz r2, done + ldr r4, [r0] + str r4, [r1] + +wait: + ldrh r4, [r3, #0x0e] + tst.w r4, #1 + bne wait + + add r0, #4 + add r1, #4 + sub r2, #1 + b next +done: + bkpt + +.align 2 + +flash_base: + .word 0x40023c00 diff --git a/src/stlink-common.c b/src/stlink-common.c index f0a0c236e..08bd0bb4d 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1182,6 +1182,28 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x00, 0xbe }; + static const uint8_t loader_code_stm32f4[] = { + // flashloaders/stm32f4.s + + 0x07, 0x4b, + + 0x62, 0xb1, + 0x04, 0x68, + 0x0c, 0x60, + + 0xdc, 0x89, + 0x14, 0xf0, 0x01, 0x0f, + 0xfb, 0xd1, + 0x00, 0xf1, 0x04, 0x00, + 0x01, 0xf1, 0x04, 0x01, + 0xa2, 0xf1, 0x01, 0x02, + 0xf1, 0xe7, + + 0x00, 0xbe, + + 0x00, 0x3c, 0x02, 0x40, + }; + const uint8_t* loader_code; size_t loader_size; @@ -1195,6 +1217,11 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); } + else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) + { + loader_code = loader_code_stm32f4; + loader_size = sizeof(loader_code_stm32f4); + } else { WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); @@ -1358,6 +1385,13 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) { /* todo: check write operation */ + ILOG("Starting Flash write for F2/F4\n"); + /* flash loader initialization */ + if (init_flash_loader(sl, &fl) == -1) { + WLOG("init_flash_loader() == -1\n"); + return -1; + } + /* First unlock the cr */ unlock_flash_if(sl); @@ -1368,6 +1402,20 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned /* set programming mode */ set_flash_cr_pg(sl); + for(off = 0; off < len;) { + size_t size = len - off > 0x8000 ? 0x8000 : len - off; + + printf("size: %u\n", size); + + if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { + WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); + return -1; + } + + off += size; + } + +#if 0 #define PROGRESS_CHUNK_SIZE 0x1000 /* write a word in program memory */ for (off = 0; off < len; off += sizeof(uint32_t)) { @@ -1389,6 +1437,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned wait_flash_busy(sl); } +#endif /* Relock flash */ lock_flash(sl); @@ -1618,6 +1667,17 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ + } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { + + size_t count = size / sizeof(uint32_t); + if (size % sizeof(uint32_t)) ++count; + + /* setup core */ + stlink_write_reg(sl, fl->buf_addr, 0); /* source */ + stlink_write_reg(sl, target, 1); /* target */ + stlink_write_reg(sl, count, 2); /* count (32 bits words) */ + stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ + } else { fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id); return -1; @@ -1657,6 +1717,14 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } + } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { + + stlink_read_reg(sl, 2, &rr); + if (rr.r[2] != 0) { + fprintf(stderr, "write error, count == %u\n", rr.r[2]); + return -1; + } + } else { fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id); From 75c434ef2d962cf822eaf9850bf2617a20c2c06f Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 20 Jun 2012 19:01:27 +0000 Subject: [PATCH 0170/1435] Examples have no place in stlink codebase. They should be in a standalone repository, that can focus on clean, easy to follow, well documented, well tested examples. If you just want some example binaries that you can use to test your installation is working, the libopencm3 project has various blink projects for all the STM32 Discovery boards. --- example/32l_dac/Makefile | 40 - example/32l_dac/discover_board.h | 61 - example/32l_dac/main.c | 242 - example/32l_dac/startup_stm32l1xx_md.s | 365 - example/32l_dac/stm32_flash.ld | 173 - example/32l_dac/system_stm32l1xx.c | 367 - example/32l_lcd/Makefile | 42 - example/32l_lcd/discover_board.h | 61 - example/32l_lcd/linker_stm32l.lds | 54 - example/32l_lcd/main.c | 351 - example/32l_lcd/stm32l_discovery_lcd.c | 614 -- example/32l_lcd/stm32l_discovery_lcd.h | 127 - example/32vl_factory_demo/Makefile | 53 - example/32vl_factory_demo/README | 5 - example/32vl_factory_demo/main.c | 234 - example/32vl_factory_demo/stm32f10x_conf.h | 76 - example/32vl_factory_demo/stm32f10x_it.c | 160 - example/32vl_factory_demo/stm32f10x_it.h | 46 - example/32vl_factory_demo/system_stm32f10x.c | 1019 -- example/README | 6 - example/blink/Makefile | 35 - example/blink/main.c | 114 - example/blink_flash/Makefile | 48 - example/blink_flash/discover_board.h | 61 - example/blink_flash/main.c | 197 - example/blink_flash/startup_stm32l1xx_md.s | 365 - example/blink_flash/stm32_flash.ld | 173 - example/blink_flash/system_stm32l1xx.c | 367 - example/libs_stm/README | 9 - example/libs_stm/build/Makefile | 10 - example/libs_stm/build/Makefile.common | 34 - example/libs_stm/build/Makefile.f10x | 5 - example/libs_stm/build/Makefile.l1xx | 5 - example/libs_stm/inc/base/stdint.h | 16 - example/libs_stm/inc/core_support/core_cm3.c | 784 -- example/libs_stm/inc/core_support/core_cm3.h | 1818 ---- .../libs_stm/inc/device_support/stm32f10x.h | 8227 ----------------- .../libs_stm/inc/device_support/stm32l1xx.h | 5140 ---------- .../inc/device_support/system_stm32f10x.h | 97 - .../inc/device_support/system_stm32l1xx.h | 98 - example/libs_stm/inc/stm32f10x/misc.h | 219 - .../libs_stm/inc/stm32f10x/stm32f10x_adc.h | 482 - .../libs_stm/inc/stm32f10x/stm32f10x_bkp.h | 194 - .../libs_stm/inc/stm32f10x/stm32f10x_can.h | 535 -- .../libs_stm/inc/stm32f10x/stm32f10x_cec.h | 209 - .../libs_stm/inc/stm32f10x/stm32f10x_crc.h | 93 - .../libs_stm/inc/stm32f10x/stm32f10x_dac.h | 316 - .../libs_stm/inc/stm32f10x/stm32f10x_dbgmcu.h | 118 - .../libs_stm/inc/stm32f10x/stm32f10x_dma.h | 437 - .../libs_stm/inc/stm32f10x/stm32f10x_exti.h | 183 - .../libs_stm/inc/stm32f10x/stm32f10x_flash.h | 425 - .../libs_stm/inc/stm32f10x/stm32f10x_fsmc.h | 716 -- .../libs_stm/inc/stm32f10x/stm32f10x_gpio.h | 379 - .../libs_stm/inc/stm32f10x/stm32f10x_i2c.h | 670 -- .../libs_stm/inc/stm32f10x/stm32f10x_iwdg.h | 139 - .../libs_stm/inc/stm32f10x/stm32f10x_pwr.h | 155 - .../libs_stm/inc/stm32f10x/stm32f10x_rcc.h | 726 -- .../libs_stm/inc/stm32f10x/stm32f10x_rtc.h | 134 - .../libs_stm/inc/stm32f10x/stm32f10x_sdio.h | 530 -- .../libs_stm/inc/stm32f10x/stm32f10x_spi.h | 490 - .../libs_stm/inc/stm32f10x/stm32f10x_tim.h | 1133 --- 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-nostdinc - -# to run from FLASH -CFLAGS+=-Wl,-T,stm32_flash.ld - -PLATFORM=stm32l1xx -LIBS_STM_PATH=../libs_stm - -# stm32l_discovery lib -CFLAGS+=-I$(LIBS_STM_PATH)/inc/base -CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support -CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support -CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM) - -LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_l1xx - -all: $(BIN_IMAGE) - -$(BIN_IMAGE): $(EXECUTABLE) - $(OBJCOPY) -O binary $^ $@ - -$(EXECUTABLE): main.c system_stm32l1xx.c startup_stm32l1xx_md.s - $(CC) $(CFLAGS) $^ -o $@ $(LDFLAGS) - -clean: - rm -rf $(EXECUTABLE) - rm -rf $(BIN_IMAGE) - -write: all - sudo ../../flash/flash write ./dac.bin 0x08000000 - -.PHONY: all clean write diff --git a/example/32l_dac/discover_board.h b/example/32l_dac/discover_board.h deleted file mode 100644 index d93a184aa..000000000 --- a/example/32l_dac/discover_board.h +++ /dev/null @@ -1,61 +0,0 @@ - /** - ****************************************************************************** - * @file discover_board.h - * @author Microcontroller Division - * @version V1.0.2 - * @date September-2011 - * @brief Input/Output defines - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __DISCOVER_BOARD_H -#define __DISCOVER_BOARD_H - -/* Includes ------------------------------------------------------------------*/ -/* #include "stm32l1xx.h" */ - -#define bool _Bool -#define FALSE 0 -#define TRUE !FALSE - -/* MACROs for SET, RESET or TOGGLE Output port */ - -#define GPIO_HIGH(a,b) a->BSRRL = b -#define GPIO_LOW(a,b) a->BSRRH = b -#define GPIO_TOGGLE(a,b) a->ODR ^= b - -#define USERBUTTON_GPIO_PORT GPIOA -#define USERBUTTON_GPIO_PIN GPIO_Pin_0 -#define USERBUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA - -#define LD_GPIO_PORT GPIOB -#define LD_GREEN_GPIO_PIN GPIO_Pin_7 -#define LD_BLUE_GPIO_PIN GPIO_Pin_6 -#define LD_GPIO_PORT_CLK RCC_AHBPeriph_GPIOB - -#define CTN_GPIO_PORT GPIOC -#define CTN_CNTEN_GPIO_PIN GPIO_Pin_13 -#define CTN_GPIO_CLK RCC_AHBPeriph_GPIOC - -#define WAKEUP_GPIO_PORT GPIOA - -#define IDD_MEASURE_PORT GPIOA -#define IDD_MEASURE GPIO_Pin_4 - - -#endif - - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/32l_dac/main.c b/example/32l_dac/main.c deleted file mode 100644 index 1f89d33ac..000000000 --- a/example/32l_dac/main.c +++ /dev/null @@ -1,242 +0,0 @@ -/* base headers */ -#include "stdint.h" - -/* libstm32l_discovery headers */ -#include "stm32l1xx_gpio.h" -#include "stm32l1xx_adc.h" -#include "stm32l1xx_dac.h" -#include "stm32l1xx_lcd.h" -#include "stm32l1xx_rcc.h" -#include "stm32l1xx_rtc.h" -#include "stm32l1xx_exti.h" -#include "stm32l1xx_pwr.h" -#include "stm32l1xx_flash.h" -#include "stm32l1xx_syscfg.h" -#include "stm32l1xx_dbgmcu.h" - -/* board specific macros */ -#include "discover_board.h" - - -/* hardware configuration */ - -#if CONFIG_STM32VL_DISCOVERY - -# define GPIOC 0x40011000 /* port C */ -# define GPIOC_CRH (GPIOC + 0x04) /* port configuration register high */ -# define GPIOC_ODR (GPIOC + 0x0c) /* port output data register */ - -# define LED_BLUE (1 << 8) /* port C, pin 8 */ -# define LED_GREEN (1 << 9) /* port C, pin 9 */ - -static inline void setup_leds(void) -{ - *(volatile uint32_t*)GPIOC_CRH = 0x44444411; -} - -static inline void switch_leds_on(void) -{ - *(volatile uint32_t*)GPIOC_ODR = LED_BLUE | LED_GREEN; -} - -static inline void switch_leds_off(void) -{ - *(volatile uint32_t*)GPIOC_ODR = 0; -} - -#elif CONFIG_STM32L_DISCOVERY - -# define GPIOB_MODER (GPIOB + 0x00) /* port mode register */ -# define GPIOB_ODR (GPIOB + 0x14) /* port output data register */ - -# define LED_BLUE (1 << 6) /* port B, pin 6 */ -# define LED_GREEN (1 << 7) /* port B, pin 7 */ - -static inline void setup_leds(void) -{ - /* configure port 6 and 7 as output */ - *(volatile uint32_t*)GPIOB_MODER |= (1 << (7 * 2)) | (1 << (6 * 2)); -} - -static inline void switch_leds_on(void) -{ - GPIO_HIGH(LD_GPIO_PORT, LD_GREEN_GPIO_PIN); - GPIO_HIGH(LD_GPIO_PORT, LD_BLUE_GPIO_PIN); -} - -static inline void switch_leds_off(void) -{ - GPIO_LOW(LD_GPIO_PORT, LD_GREEN_GPIO_PIN); - GPIO_LOW(LD_GPIO_PORT, LD_BLUE_GPIO_PIN); -} - -#endif /* otherwise, error */ - - -#define delay() \ -do { \ - volatile unsigned int i; \ - for (i = 0; i < 1000000; ++i) \ - __asm__ __volatile__ ("nop\n\t":::"memory"); \ -} while (0) - - -static void RCC_Configuration(void) -{ - /* HSI is 16mhz RC clock directly fed to SYSCLK (rm00038, figure 9) */ - - /* enable the HSI clock (high speed internal) */ - RCC_HSICmd(ENABLE); - - /* wail til HSI ready */ - while (RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET) - {} - - /* at startup, SYSCLK driven by MSI. set to HSI */ - RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI); - - /* set MSI to 4mhz */ - RCC_MSIRangeConfig(RCC_MSIRange_6); - - /* turn HSE off */ - RCC_HSEConfig(RCC_HSE_OFF); - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - while (1) ; - } -} - - -static void RTC_Configuration(void) -{ - /* Allow access to the RTC */ - PWR_RTCAccessCmd(ENABLE); - - /* Reset Backup Domain */ - RCC_RTCResetCmd(ENABLE); - RCC_RTCResetCmd(DISABLE); - - /* LSE Enable */ - RCC_LSEConfig(RCC_LSE_ON); - - /* Wait till LSE is ready */ - while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) - {} - - RCC_RTCCLKCmd(ENABLE); - - /* LCD Clock Source Selection */ - RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); - -} - -static void setup_dac1(void) -{ - /* see 10.2 notes */ - - static GPIO_InitTypeDef GPIO_InitStructure; - static DAC_InitTypeDef DAC_InitStructure; - - /* DAC clock path: - HSI (16mhz) -> SYSCLK -> HCLK(/1) -> PCLK1(/1) - */ - - /* set the AHB clock (HCLK) prescaler to 1 */ - RCC_HCLKConfig(RCC_SYSCLK_Div1); - - /* set the low speed APB clock (APB1, ie. PCLK1) prescaler to 1 */ - RCC_PCLK1Config(RCC_HCLK_Div1); - - /* enable DAC APB1 clock */ - /* signal connections: HSI(16mhz) -> SYSCLK -> AHB */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; /* GPIO_Pin_5 for channel 2 */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - DAC_StructInit(&DAC_InitStructure); - DAC_InitStructure.DAC_Trigger = DAC_Trigger_None; -#if 0 /* triangle waveform generation */ - DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_Triangle; - DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_TriangleAmplitude_1; -#else - DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None; - DAC_InitStructure.DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; -#endif - DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; - DAC_Init(DAC_Channel_1, &DAC_InitStructure); - - /* enable dac channel */ - DAC_Cmd(DAC_Channel_1, ENABLE); -} - -static inline void set_dac1_mv(unsigned int mv) -{ - /* mv the millivolts */ - - /* vref in millivolts */ - /* #define CONFIG_VREF 5000 */ -#define CONFIG_VREF 3000 - - /* resolution in bits */ -#define CONFIG_DAC_RES 12 - - const uint16_t n = (mv * (1 << (CONFIG_DAC_RES - 1))) / CONFIG_VREF; - DAC_SetChannel1Data(DAC_Align_12b_R, n); -} - -void main(void) -{ - static RCC_ClocksTypeDef RCC_Clocks; - static GPIO_InitTypeDef GPIO_InitStructure; - static uint16_t dac_value; - static unsigned int led_state = 0; - - /* Configure Clocks for Application need */ - RCC_Configuration(); - - /* Configure RTC Clocks */ - RTC_Configuration(); - -#if 0 - /* Set internal voltage regulator to 1.8v */ - PWR_VoltageScalingConfig(PWR_VoltageScaling_Range1); - /* Wait Until the Voltage Regulator is ready */ - while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET) ; -#endif - - /* configure gpios */ - - /* Enable GPIOs clock */ - RCC_AHBPeriphClockCmd(LD_GPIO_PORT_CLK, ENABLE); - - /* Configure the GPIO_LED pins LD3 & LD4*/ - GPIO_InitStructure.GPIO_Pin = LD_GREEN_GPIO_PIN | LD_BLUE_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_Init(LD_GPIO_PORT, &GPIO_InitStructure); - GPIO_LOW(LD_GPIO_PORT, LD_GREEN_GPIO_PIN); - GPIO_LOW(LD_GPIO_PORT, LD_BLUE_GPIO_PIN); - - setup_dac1(); - - dac_value = 0; - - while (1) - { - DAC_SetChannel1Data(DAC_Align_12b_R, dac_value & 0xfff); - dac_value += 0x10; - - if (led_state & 1) switch_leds_on(); - else switch_leds_off(); - led_state ^= 1; - - delay(); - } -} diff --git a/example/32l_dac/startup_stm32l1xx_md.s b/example/32l_dac/startup_stm32l1xx_md.s deleted file mode 100644 index 9a8389c9f..000000000 --- a/example/32l_dac/startup_stm32l1xx_md.s +++ /dev/null @@ -1,365 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32l1xx_md.s - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief STM32L1xx Ultra Low Power Medium-density Devices vector table for - * RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ******************************************************************************* - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ -/* let main do the system initialization */ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/******************************************************************************* -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_STAMP_IRQHandler - .word RTC_WKUP_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_IRQHandler - .word USB_HP_IRQHandler - .word USB_LP_IRQHandler - .word DAC_IRQHandler - .word COMP_IRQHandler - .word EXTI9_5_IRQHandler - .word LCD_IRQHandler - .word TIM9_IRQHandler - .word TIM10_IRQHandler - .word TIM11_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word USB_FS_WKUP_IRQHandler - .word TIM6_IRQHandler - .word TIM7_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32L15x ULtra Low Power Medium-density devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_STAMP_IRQHandler - .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak USB_HP_IRQHandler - .thumb_set USB_HP_IRQHandler,Default_Handler - - .weak USB_LP_IRQHandler - .thumb_set USB_LP_IRQHandler,Default_Handler - - .weak DAC_IRQHandler - .thumb_set DAC_IRQHandler,Default_Handler - - .weak COMP_IRQHandler - .thumb_set COMP_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak LCD_IRQHandler - .thumb_set LCD_IRQHandler,Default_Handler - - .weak TIM9_IRQHandler - .thumb_set TIM9_IRQHandler,Default_Handler - - .weak TIM10_IRQHandler - .thumb_set TIM10_IRQHandler,Default_Handler - - .weak TIM11_IRQHandler - .thumb_set TIM11_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak USB_FS_WKUP_IRQHandler - .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - -/******************** (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***/ - diff --git a/example/32l_dac/stm32_flash.ld b/example/32l_dac/stm32_flash.ld deleted file mode 100644 index 146b16ecc..000000000 --- a/example/32l_dac/stm32_flash.ld +++ /dev/null @@ -1,173 +0,0 @@ -/* -***************************************************************************** -** -** File : stm32_flash.ld -** -** Abstract : Linker script for STM32L152RB Device with -** 128KByte FLASH, 16KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** Environment : Atollic TrueSTUDIO(R) -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -** (c)Copyright Atollic AB. -** You may use this file as-is or modify it according to the needs of your -** project. Distribution of this file (unmodified or modified) is not -** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the -** rights to distribute the assembled, compiled & linked contents of this -** file as part of an application binary file, provided that it is built -** using the Atollic TrueSTUDIO(R) toolchain. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20004000; /* end of 16K RAM */ - -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0; /* required amount of heap */ -_Min_Stack_Size = 0x80; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K - MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K - RW_EEPROM (rw) : ORIGIN = 0x08080000, LENGTH = 32 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(.fini_array*)) - KEEP (*(SORT(.fini_array.*))) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = .; - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : AT ( _sidata ) - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(4); - } >RAM - - /* MEMORY_bank1 section, code must be located here explicitly */ - /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ - .memory_b1_text : - { - *(.mb1text) /* .mb1text sections (code) */ - *(.mb1text*) /* .mb1text* sections (code) */ - *(.mb1rodata) /* read-only data (constants) */ - *(.mb1rodata*) - } >MEMORY_B1 - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } - - .DataFlash (NOLOAD): {*(.DataFlash)} >RW_EEPROM -} diff --git a/example/32l_dac/system_stm32l1xx.c b/example/32l_dac/system_stm32l1xx.c deleted file mode 100644 index 6deab320c..000000000 --- a/example/32l_dac/system_stm32l1xx.c +++ /dev/null @@ -1,367 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l1xx.c - * @author MCD Application Team - * @version V1.0.0 - * @date 2-June-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32L1xx Ultra - * Low Medium-density devices, and is generated by the clock configuration - * tool "STM32L1xx_Clock_Configuration_V1.0.0.xls". - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32l1xx_md.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32l1xx_md.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and MSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define - * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - * System Clock Configuration - *============================================================================= - * System clock source | HSI - *----------------------------------------------------------------------------- - * SYSCLK | 16000000 Hz - *----------------------------------------------------------------------------- - * HCLK | 16000000 Hz - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 - *----------------------------------------------------------------------------- - * HSE Frequency | 8000000 Hz - *----------------------------------------------------------------------------- - * PLL DIV | Not Used - *----------------------------------------------------------------------------- - * PLL MUL | Not Used - *----------------------------------------------------------------------------- - * VDD | 3.3 V - *----------------------------------------------------------------------------- - * Vcore | 1.8 V (Range 1) - *----------------------------------------------------------------------------- - * Flash Latency | 0 WS - *----------------------------------------------------------------------------- - * Require 48MHz for USB clock | Disabled - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx_system - * @{ - */ - -/** @addtogroup STM32L1xx_System_Private_Includes - * @{ - */ - -#include "stm32l1xx.h" - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Defines - * @{ - */ -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Variables - * @{ - */ -uint32_t SystemCoreClock = 16000000; -__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; -__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /*!< Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100; - - /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t)0x88FFC00C; - - /*!< Reset HSION, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xEEFEFFFE; - - /*!< Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFF; - - /*!< Disable all interrupts */ - RCC->CIR = 0x00000000; - - /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ - SetSysClock(); - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif -} - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI - * value as defined by the MSI range. - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); - break; - case 0x04: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case 0x08: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case 0x0C: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; - plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; - pllmul = PLLMulTable[(pllmul >> 18)]; - plldiv = (plldiv >> 22) + 1; - - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - - if (pllsource == 0x00) - { - /* HSI oscillator clock selected as PLL clock entry */ - SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); - } - else - { - /* HSE selected as PLL clock entry */ - SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); - } - break; - default: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); - break; - } - /* Compute HCLK clock frequency --------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash - * settings. - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CR |= ((uint32_t)RCC_CR_HSION); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CR & RCC_CR_HSIRDY; - } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSIRDY) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* Flash 0 wait state */ - FLASH->ACR &= ~FLASH_ACR_LATENCY; - - /* Disable Prefetch Buffer */ - FLASH->ACR &= ~FLASH_ACR_PRFTEN; - - /* Disable 64-bit access */ - FLASH->ACR &= ~FLASH_ACR_ACC64; - - - /* Power enable */ - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - - /* Select the Voltage Range 1 (1.8 V) */ - PWR->CR = PWR_CR_VOS_0; - - - /* Wait Until the Voltage Regulator is ready */ - while((PWR->CSR & PWR_CSR_VOSF) != RESET) - { - } - - /* HCLK = SYSCLK /1*/ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - /* PCLK2 = HCLK /1*/ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK /1*/ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* Select HSI as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI; - - /* Wait till HSI is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI) - { - } - } - else - { - /* If HSI fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/32l_lcd/Makefile b/example/32l_lcd/Makefile deleted file mode 100644 index fdb79c304..000000000 --- a/example/32l_lcd/Makefile +++ /dev/null @@ -1,42 +0,0 @@ -ELF=lcd.elf - -CC=arm-none-eabi-gcc - -CFLAGS=-O2 -mlittle-endian -mthumb -g -CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc - -CFLAGS+=-I. - - -PLATFORM=stm32l1xx -LIBS_STM_PATH=../libs_stm - -CFLAGS+=-I$(LIBS_STM_PATH)/inc/base -CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support -CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support -CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM) - -# to run from SRAM -CFLAGS+=-Wl,-T,linker_stm32l.lds - -LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_l1xx - -SRCS=\ -main.c\ -stm32l_discovery_lcd.c - -OBJS=$(SRCS:.c=.o) - -all: $(ELF) - -$(ELF): $(OBJS) - $(CC) $(CFLAGS) -o $@ $(OBJS) $(LDFLAGS) - -%.o: %.c - $(CC) $(CFLAGS) -c -o $@ $^ - -clean: - -rm -f $(OBJS) - -rm -f $(ELF) - -.PHONY: all clean diff --git a/example/32l_lcd/discover_board.h b/example/32l_lcd/discover_board.h deleted file mode 100644 index 91617684a..000000000 --- a/example/32l_lcd/discover_board.h +++ /dev/null @@ -1,61 +0,0 @@ - /** - ****************************************************************************** - * @file discover_board.h - * @author Microcontroller Division - * @version V1.0.2 - * @date September-2011 - * @brief Input/Output defines - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __DISCOVER_BOARD_H -#define __DISCOVER_BOARD_H - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -#define bool _Bool -#define FALSE 0 -#define TRUE !FALSE - -/* MACROs for SET, RESET or TOGGLE Output port */ - -#define GPIO_HIGH(a,b) a->BSRRL = b -#define GPIO_LOW(a,b) a->BSRRH = b -#define GPIO_TOGGLE(a,b) a->ODR ^= b - -#define USERBUTTON_GPIO_PORT GPIOA -#define USERBUTTON_GPIO_PIN GPIO_Pin_0 -#define USERBUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA - -#define LD_GPIO_PORT GPIOB -#define LD_GREEN_GPIO_PIN GPIO_Pin_7 -#define LD_BLUE_GPIO_PIN GPIO_Pin_6 -#define LD_GPIO_PORT_CLK RCC_AHBPeriph_GPIOB - -#define CTN_GPIO_PORT GPIOC -#define CTN_CNTEN_GPIO_PIN GPIO_Pin_13 -#define CTN_GPIO_CLK RCC_AHBPeriph_GPIOC - -#define WAKEUP_GPIO_PORT GPIOA - -#define IDD_MEASURE_PORT GPIOA -#define IDD_MEASURE GPIO_Pin_4 - - -#endif - - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/32l_lcd/linker_stm32l.lds b/example/32l_lcd/linker_stm32l.lds deleted file mode 100644 index 58b894f03..000000000 --- a/example/32l_lcd/linker_stm32l.lds +++ /dev/null @@ -1,54 +0,0 @@ -OUTPUT_FORMAT("elf32-littlearm") -ENTRY(_main) - -MEMORY -{ - sram : ORIGIN = 0x20000000, LENGTH = 0x4000 -} - -SECTIONS -{ - .text(ORIGIN(sram)): - { - _main = .; - _ftext = .; - *(.text .stub .text.* .gnu.linkonce.t.*) - _etext = .; - } > sram - - .rodata : - { - . = ALIGN(4); - _frodata = .; - *(.rodata .rodata.* .gnu.linkonce.r.*) - *(.rodata1) - _erodata = .; - } > sram - - .data : - { - . = ALIGN(4); - _fdata = .; - *(.data .data.* .gnu.linkonce.d.*) - *(.data1) - _gp = ALIGN(16); - *(.sdata .sdata.* .gnu.linkonce.s.*) - _edata = .; - } > sram - - .bss : - { - . = ALIGN(4); - _fbss = .; - *(.dynsbss) - *(.sbss .sbss.* .gnu.linkonce.sb.*) - *(.scommon) - *(.dynbss) - *(.bss .bss.* .gnu.linkonce.b.*) - *(COMMON) - _ebss = .; - _end = .; - } > sram -} - -PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4); diff --git a/example/32l_lcd/main.c b/example/32l_lcd/main.c deleted file mode 100644 index 36d6e52d9..000000000 --- a/example/32l_lcd/main.c +++ /dev/null @@ -1,351 +0,0 @@ -/* this example is only for stm32l discover. - adapted from ST firmwares projects. - */ - -/* base headers */ -#include "stdint.h" - -/* libstm32l_discovery headers */ -#include "stm32l1xx_gpio.h" -#include "stm32l1xx_adc.h" -#include "stm32l1xx_lcd.h" -#include "stm32l1xx_rcc.h" -#include "stm32l1xx_rtc.h" -#include "stm32l1xx_exti.h" -#include "stm32l1xx_pwr.h" -#include "stm32l1xx_syscfg.h" -#include "stm32l1xx_dbgmcu.h" - -/* lcd wrapper routines header */ -#include "stm32l_discovery_lcd.h" - -/* boot mode */ - -#define CONFIG_BOOT_SRAM 1 -#define CONFIG_BOOT_FLASH 0 - - -/* gpios - refer to CD00277537.pdf, APB memory space. - refer to CD00240193.pdf, GPIO. -*/ - -#define GPIOA_MODER (GPIOA_BASE + 0x00) -#define GPIOA_ODR (GPIOA_BASE + 0x14) - -#define GPIOB_MODER (GPIOB_BASE + 0x00) -#define GPIOB_ODR (GPIOB_BASE + 0x14) - -#define GPIOC_MODER (GPIOC_BASE + 0x00) -#define GPIOC_ODR (GPIOC_BASE + 0x14) - - -/* leds */ - -#define LED_BLUE (1 << 6) /* port B, pin 6 */ -#define LED_GREEN (1 << 7) /* port B, pin 7 */ - -static inline void setup_leds(void) -{ - /* configure port 6 and 7 as output */ - *(volatile uint32_t*)GPIOB_MODER |= (1 << (7 * 2)) | (1 << (6 * 2)); -} - -static inline void switch_leds_on(void) -{ - *(volatile uint32_t*)GPIOB_ODR = LED_BLUE | LED_GREEN; -} - -static inline void switch_leds_off(void) -{ - *(volatile uint32_t*)GPIOB_ODR = 0; -} - - -#define delay() \ -do { \ - register unsigned int i; \ - for (i = 0; i < 1000000; ++i) \ - __asm__ __volatile__ ("nop\n\t":::"memory"); \ -} while (0) - - -#if CONFIG_BOOT_SRAM - -extern uint32_t _fstack; - -static inline void setup_stack(void) -{ - /* setup the stack to point to _fstack (refer to ld script) */ - - static const uint32_t fstack = (uint32_t)&_fstack; - - __asm__ __volatile__ - ( - "ldr sp, %0\n\t" - : - : "m"(fstack) - : "sp" - ); -} - -#endif /* CONFIG_BOOT_SRAM */ - - -/* application related setup */ - -static void RCC_Configuration(void) -{ - /* Enable HSI Clock */ - RCC_HSICmd(ENABLE); - - /*!< Wait till HSI is ready */ - while (RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET); - - /* Set HSI as sys clock*/ - RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI); - - /* Set MSI clock range to ~4.194MHz*/ - RCC_MSIRangeConfig(RCC_MSIRange_6); - - /* Enable the GPIOs clocks */ - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC| RCC_AHBPeriph_GPIOD| RCC_AHBPeriph_GPIOE| RCC_AHBPeriph_GPIOH, ENABLE); - - /* Enable comparator, LCD and PWR mngt clocks */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP | RCC_APB1Periph_LCD | RCC_APB1Periph_PWR,ENABLE); - - /* Enable ADC & SYSCFG clocks */ - RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1 | RCC_APB2Periph_SYSCFG , ENABLE); - - /* Allow access to the RTC */ - PWR_RTCAccessCmd(ENABLE); - - /* Reset RTC Backup Domain */ - RCC_RTCResetCmd(ENABLE); - RCC_RTCResetCmd(DISABLE); - - /* LSE Enable */ - RCC_LSEConfig(RCC_LSE_ON); - - /* Wait until LSE is ready */ - while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET); - - /* RTC Clock Source Selection */ - RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); - - /* Enable the RTC */ - RCC_RTCCLKCmd(ENABLE); - - /*Disable HSE*/ - RCC_HSEConfig(RCC_HSE_OFF); - if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET ) - { - /* Stay in infinite loop if HSE is not disabled*/ - while(1); - } -} - -static void Init_GPIOs(void) -{ -#if 0 /* fixme: GPIO_Init raises a bug in some gcc toolchains */ - - /* GPIO, EXTI and NVIC Init structure declaration */ - GPIO_InitTypeDef GPIO_InitStructure; - -#if 0 - EXTI_InitTypeDef EXTI_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; -#endif - -#if 0 - /* Configure User Button pin as input */ - GPIO_InitStructure.GPIO_Pin = USERBUTTON_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz; - GPIO_Init(USERBUTTON_GPIO_PORT, &GPIO_InitStructure); -#endif - -#if 0 - /* Select User Button pin as input source for EXTI Line */ - SYSCFG_EXTILineConfig(EXTI_PortSourceGPIOA,EXTI_PinSource0); - - /* Configure EXT1 Line 0 in interrupt mode trigged on Rising edge */ - EXTI_InitStructure.EXTI_Line = EXTI_Line0 ; // PA0 for User button AND IDD_WakeUP - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - - /* Enable and set EXTI0 Interrupt to the lowest priority */ - NVIC_InitStructure.NVIC_IRQChannel = EXTI0_IRQn ; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); -#endif - -#if 0 - /* Configure the LED_pin as output push-pull for LD3 & LD4 usage*/ - GPIO_InitStructure.GPIO_Pin = LD_GREEN_GPIO_PIN | LD_BLUE_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_Init(LD_GPIO_PORT, &GPIO_InitStructure); - - /* Force a low level on LEDs*/ - GPIO_LOW(LD_GPIO_PORT,LD_GREEN_GPIO_PIN); - GPIO_LOW(LD_GPIO_PORT,LD_BLUE_GPIO_PIN); - - /* Counter enable: GPIO set in output for enable the counter */ - GPIO_InitStructure.GPIO_Pin = CTN_CNTEN_GPIO_PIN; - GPIO_Init( CTN_GPIO_PORT, &GPIO_InitStructure); - - /* To prepare to start counter */ - GPIO_HIGH(CTN_GPIO_PORT,CTN_CNTEN_GPIO_PIN); - - /* Configure Port A LCD Output pins as alternate function */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_8 | GPIO_Pin_9 |GPIO_Pin_10 |GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_Init( GPIOA, &GPIO_InitStructure); - - /* Select LCD alternate function for Port A LCD Output pins */ - GPIO_PinAFConfig(GPIOA, GPIO_PinSource1,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOA, GPIO_PinSource2,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOA, GPIO_PinSource3,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOA, GPIO_PinSource8,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOA, GPIO_PinSource9,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOA, GPIO_PinSource10,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOA, GPIO_PinSource15,GPIO_AF_LCD) ; - - /* Configure Port B LCD Output pins as alternate function */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 \ - | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_Init( GPIOB, &GPIO_InitStructure); - - /* Select LCD alternate function for Port B LCD Output pins */ - GPIO_PinAFConfig(GPIOB, GPIO_PinSource3,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource4,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource5,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource8,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource9,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource10,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource11,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource12,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource13,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource14,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource15,GPIO_AF_LCD) ; -#endif - -#if 0 - /* Configure Port C LCD Output pins as alternate function */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 \ - | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |GPIO_Pin_11 ; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_Init( GPIOC, &GPIO_InitStructure); - - /* Select LCD alternate function for Port B LCD Output pins */ - GPIO_PinAFConfig(GPIOC, GPIO_PinSource0,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource1,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource2,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource3,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource6,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource7,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource8,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource9,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource10,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource11,GPIO_AF_LCD) ; -#endif - -#if 0 - /* Configure ADC (IDD_MEASURE) pin as Analogue */ - GPIO_InitStructure.GPIO_Pin = IDD_MEASURE ; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; - GPIO_Init( IDD_MEASURE_PORT, &GPIO_InitStructure); -#endif - -#else /* fixme */ - - /* set every port in digital output mode */ - - /* PA[1:3,8:10,15] */ - *(volatile uint32_t*)GPIOA_MODER |= - (GPIO_Mode_AF << (1 * 2)) | - (GPIO_Mode_AF << (2 * 2)) | - (GPIO_Mode_AF << (3 * 2)) | - (GPIO_Mode_AF << (8 * 2)) | - (GPIO_Mode_AF << (9 * 2)) | - (GPIO_Mode_AF << (10 * 2)) | - (GPIO_Mode_AF << (15 * 2)); - - /* PB[3:5,8:15] */ - *(volatile uint32_t*)GPIOB_MODER |= - (GPIO_Mode_AF << (3 * 2)) | - (GPIO_Mode_AF << (4 * 2)) | - (GPIO_Mode_AF << (5 * 2)) | - (GPIO_Mode_AF << (8 * 2)) | - (GPIO_Mode_AF << (9 * 2)) | - (GPIO_Mode_AF << (10 * 2)) | - (GPIO_Mode_AF << (11 * 2)) | - (GPIO_Mode_AF << (12 * 2)) | - (GPIO_Mode_AF << (13 * 2)) | - (GPIO_Mode_AF << (14 * 2)) | - (GPIO_Mode_AF << (15 * 2)); - - /* PC[0:3,6:11] */ - *(volatile uint32_t*)GPIOC_MODER |= - (GPIO_Mode_AF << (0 * 2)) | - (GPIO_Mode_AF << (1 * 2)) | - (GPIO_Mode_AF << (2 * 2)) | - (GPIO_Mode_AF << (3 * 2)) | - (GPIO_Mode_AF << (6 * 2)) | - (GPIO_Mode_AF << (7 * 2)) | - (GPIO_Mode_AF << (8 * 2)) | - (GPIO_Mode_AF << (9 * 2)) | - (GPIO_Mode_AF << (10 * 2)) | - (GPIO_Mode_AF << (11 * 2)); - -#endif /* fixme */ -} - - -/* main */ - -static void __attribute__((naked)) __attribute__((used)) main(void) -{ -#if CONFIG_BOOT_SRAM - /* do not use previsouly setup stack, if any */ - setup_stack(); -#endif /* CONFIG_BOOT_SRAM */ - - RCC_Configuration(); - - Init_GPIOs(); - - LCD_GLASS_Init(); - - setup_leds(); - - while (1) - { - /* switch_leds_on(); */ - GPIO_HIGH(LD_GPIO_PORT, LD_GREEN_GPIO_PIN); - GPIO_HIGH(LD_GPIO_PORT, LD_BLUE_GPIO_PIN); - - LCD_GLASS_Clear(); - LCD_GLASS_DisplayString("ON "); - - delay(); - - /* switch_leds_off(); */ - GPIO_LOW(LD_GPIO_PORT, LD_GREEN_GPIO_PIN); - GPIO_LOW(LD_GPIO_PORT, LD_BLUE_GPIO_PIN); - - LCD_GLASS_Clear(); - LCD_GLASS_DisplayString(" OFF"); - - delay(); - } -} diff --git a/example/32l_lcd/stm32l_discovery_lcd.c b/example/32l_lcd/stm32l_discovery_lcd.c deleted file mode 100644 index 982a5f259..000000000 --- a/example/32l_lcd/stm32l_discovery_lcd.c +++ /dev/null @@ -1,614 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l_discovery_lcd.c - * @author Microcontroller Division - * @version V1.0.0 - * @date Apri-2011 - * @brief This file includes driver for the glass LCD Module mounted on - * STM32l discovery board MB963 - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l_discovery_lcd.h" -#include "discover_board.h" -#include "stm32l1xx_lcd.h" -#include "stm32l1xx_gpio.h" -#include "stm32l1xx_rcc.h" -/* #include "main.h" */ - -/* this variable can be used for accelerate the scrolling exit when push user button */ -volatile bool KeyPressed = FALSE; - -/* LCD BAR status: We don't write directly in LCD RAM for save the bar setting */ -uint8_t t_bar[2]={0x0,0X0}; - -/* ========================================================================= - LCD MAPPING - ========================================================================= - A - _ ---------- -COL |_| |\ |J /| - F| H | K |B - _ | \ | / | -COL |_| --G-- --M-- - | /| \ | - E| Q | N |C - _ | / |P \| -DP |_| ----------- - D - - An LCD character coding is based on the following matrix: - { E , D , P , N } - { M , C , COL , DP} - { B , A , K , J } - { G , F , Q , H } - - The character 'A' for example is: - ------------------------------- -LSB { 1 , 0 , 0 , 0 } - { 1 , 1 , 0 , 0 } - { 1 , 1 , 0 , 0 } -MSB { 1 , 1 , 0 , 0 } - ------------------- - 'A' = F E 0 0 hexa - -*/ - -/* Constant table for cap characters 'A' --> 'Z' */ -const uint16_t CapLetterMap[26]= - { - /* A B C D E F G H I */ - 0xFE00,0x6714,0x1d00,0x4714,0x9d00,0x9c00,0x3f00,0xfa00,0x0014, - /* J K L M N O P Q R */ - 0x5300,0x9841,0x1900,0x5a48,0x5a09,0x5f00,0xFC00,0x5F01,0xFC01, - /* S T U V W X Y Z */ - 0xAF00,0x0414,0x5b00,0x18c0,0x5a81,0x00c9,0x0058,0x05c0 - }; - -/* Constant table for number '0' --> '9' */ -const uint16_t NumberMap[10]= - { - /* 0 1 2 3 4 5 6 7 8 9 */ - 0x5F00,0x4200,0xF500,0x6700,0xEa00,0xAF00,0xBF00,0x04600,0xFF00,0xEF00 - }; - -static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column,uint8_t* digit); - -/** - * @brief Configures the LCD GLASS relative GPIO port IOs and LCD peripheral. - * @param None - * @retval None - */ -void LCD_GLASS_Init(void) -{ - LCD_InitTypeDef LCD_InitStruct; - - - LCD_InitStruct.LCD_Prescaler = LCD_Prescaler_1; - LCD_InitStruct.LCD_Divider = LCD_Divider_31; - LCD_InitStruct.LCD_Duty = LCD_Duty_1_4; - LCD_InitStruct.LCD_Bias = LCD_Bias_1_3; - LCD_InitStruct.LCD_VoltageSource = LCD_VoltageSource_Internal; - - - /* Initialize the LCD */ - LCD_Init(&LCD_InitStruct); - - LCD_MuxSegmentCmd(ENABLE); - - /* To set contrast to mean value */ - LCD_ContrastConfig(LCD_Contrast_Level_4); - - LCD_DeadTimeConfig(LCD_DeadTime_0); - LCD_PulseOnDurationConfig(LCD_PulseOnDuration_4); - - /* Wait Until the LCD FCR register is synchronized */ - LCD_WaitForSynchro(); - - /* Enable LCD peripheral */ - LCD_Cmd(ENABLE); - - /* Wait Until the LCD is enabled */ - while(LCD_GetFlagStatus(LCD_FLAG_ENS) == RESET) - { - } - /*!< Wait Until the LCD Booster is ready */ - while(LCD_GetFlagStatus(LCD_FLAG_RDY) == RESET) - { - } - - LCD_BlinkConfig(LCD_BlinkMode_Off,LCD_BlinkFrequency_Div32); - LCD_GLASS_Clear(); -} - -/** - * @brief To initialize the LCD pins - * @caller main - * @param None - * @retval None - */ - -void LCD_GLASS_Configure_GPIO(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - -/* Enable GPIOs clock */ - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC | - RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOH, ENABLE); - - -/* Configure Output for LCD */ -/* Port A */ - GPIO_StructInit(&GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_8 | GPIO_Pin_9 |GPIO_Pin_10 |GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_Init( GPIOA, &GPIO_InitStructure); - - GPIO_PinAFConfig(GPIOA, GPIO_PinSource1,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOA, GPIO_PinSource2,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOA, GPIO_PinSource3,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOA, GPIO_PinSource8,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOA, GPIO_PinSource9,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOA, GPIO_PinSource10,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOA, GPIO_PinSource15,GPIO_AF_LCD) ; - -/* Configure Output for LCD */ -/* Port B */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_9 \ - | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_Init( GPIOB, &GPIO_InitStructure); - - GPIO_PinAFConfig(GPIOB, GPIO_PinSource3,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource4,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource5,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource8,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource9,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource10,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource11,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource12,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource13,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource14,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOB, GPIO_PinSource15,GPIO_AF_LCD) ; - -/* Configure Output for LCD */ -/* Port C*/ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 \ - | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |GPIO_Pin_11 ; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_Init( GPIOC, &GPIO_InitStructure); - - - GPIO_PinAFConfig(GPIOC, GPIO_PinSource0,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource1,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource2,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource3,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource6,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource7,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource8,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource9,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource10,GPIO_AF_LCD) ; - GPIO_PinAFConfig(GPIOC, GPIO_PinSource11,GPIO_AF_LCD) ; - -/* Disable GPIOs clock */ - RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA | RCC_AHBPeriph_GPIOB | RCC_AHBPeriph_GPIOC | - RCC_AHBPeriph_GPIOD | RCC_AHBPeriph_GPIOE | RCC_AHBPeriph_GPIOH, DISABLE); - -} - -/** - * @brief LCD contrast setting min-->max-->min by pressing user button - * @param None - * @retval None - */ - -static void Delay(uint32_t nTime) -{ - while((nTime--) != 0); -} - -void LCD_contrast() -{ - uint32_t contrast ; - - /* To get the actual contrast value in register */ - contrast = LCD->FCR & LCD_Contrast_Level_7; - - while ((GPIOC->IDR & USERBUTTON_GPIO_PIN) == 0x0) - { - contrast += LCD_Contrast_Level_1; - - if (contrast > LCD_Contrast_Level_7) - contrast=LCD_Contrast_Level_0; - - LCD_ContrastConfig(contrast); - Delay(100); - } -} - -/** - * @brief Setting bar on LCD, writes bar value in LCD frame buffer - * @param None - * @retval None - */ -void LCD_bar() -{ - - LCD->RAM[LCD_RAMRegister_4] &= 0xffff5fff; - LCD->RAM[LCD_RAMRegister_6] &= 0xffff5fff; -/* bar1 bar3 */ - LCD->RAM[LCD_RAMRegister_4] |= (uint32_t)(t_bar[0]<<12); - -/*bar0 bar2 */ - LCD->RAM[LCD_RAMRegister_6] |= (uint32_t)(t_bar[1]<<12); - -} - -/** - * @brief Converts an ascii char to the a LCD digit. - * @param c: a char to display. - * @param point: a point to add in front of char - * This parameter can be: POINT_OFF or POINT_ON - * @param column : flag indicating if a column has to be add in front - * of displayed character. - * This parameter can be: COLUMN_OFF or COLUMN_ON. - * @param digit array with segment - * @retval None - */ -static void LCD_Conv_Char_Seg(uint8_t* c,bool point,bool column, uint8_t* digit) -{ - uint16_t ch = 0 ; - uint8_t i,j; - - switch (*c) - { - case ' ' : - ch = 0x00; - break; - - case '*': - ch = star; - break; - - case 'µ' : - ch = C_UMAP; - break; - - case 'm' : - ch = C_mMap; - break; - - case 'n' : - ch = C_nMap; - break; - - case '-' : - ch = C_minus; - break; - - case '/' : - ch = C_slatch; - break; - - case '°' : - ch = C_percent_1; - break; - case '%' : - ch = C_percent_2; - break; - case 255 : - ch = C_full; - break ; - - case '0': - case '1': - case '2': - case '3': - case '4': - case '5': - case '6': - case '7': - case '8': - case '9': - ch = NumberMap[*c-0x30]; - break; - - default: - /* The character c is one letter in upper case*/ - if ( (*c < 0x5b) && (*c > 0x40) ) - { - ch = CapLetterMap[*c-'A']; - } - /* The character c is one letter in lower case*/ - if ( (*c <0x7b) && ( *c> 0x60) ) - { - ch = CapLetterMap[*c-'a']; - } - break; - } - - /* Set the digital point can be displayed if the point is on */ - if (point) - { - ch |= 0x0002; - } - - /* Set the "COL" segment in the character that can be displayed if the column is on */ - if (column) - { - ch |= 0x0020; - } - - for (i = 12,j=0 ;j<4; i-=4,j++) - { - digit[j] = (ch >> i) & 0x0f; //To isolate the less signifiant dibit - } -} - -/** - * @brief This function writes a char in the LCD frame buffer. - * @param ch: the character to display. - * @param point: a point to add in front of char - * This parameter can be: POINT_OFF or POINT_ON - * @param column: flag indicating if a column has to be add in front - * of displayed character. - * This parameter can be: COLUMN_OFF or COLUMN_ON. - * @param position: position in the LCD of the caracter to write [0:7] - * @retval None - * @par Required preconditions: The LCD should be cleared before to start the - * write operation. - */ -void LCD_GLASS_WriteChar(uint8_t* ch, bool point, bool column, uint8_t position) -{ - uint8_t digit[4]; /* Digit frame buffer */ - -/* To convert displayed character in segment in array digit */ - LCD_Conv_Char_Seg(ch,point,column,digit); - -/* TO wait LCD Ready */ - while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ; - - switch (position) - { - /* Position 1 on LCD (Digit1)*/ - case 1: - LCD->RAM[LCD_RAMRegister_0] &= 0xcffffffc; - LCD->RAM[LCD_RAMRegister_2] &= 0xcffffffc; - LCD->RAM[LCD_RAMRegister_4] &= 0xcffffffc; - LCD->RAM[LCD_RAMRegister_6] &= 0xcffffffc; - - LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 26 ) | (digit[0]& 0x03) ; // 1G 1B 1M 1E - LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 26 ) | (digit[1]& 0x03) ; // 1F 1A 1C 1D - LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 26 ) | (digit[2]& 0x03) ; // 1Q 1K 1Col 1P - LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 26 ) | (digit[3]& 0x03) ; // 1H 1J 1DP 1N - - break; - - /* Position 2 on LCD (Digit2)*/ - case 2: - LCD->RAM[LCD_RAMRegister_0] &= 0xf3ffff03; - LCD->RAM[LCD_RAMRegister_2] &= 0xf3ffff03; - LCD->RAM[LCD_RAMRegister_4] &= 0xf3ffff03; - LCD->RAM[LCD_RAMRegister_6] &= 0xf3ffff03; - - LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 24 )|((digit[0]& 0x02) << 6 )|((digit[0]& 0x01) << 2 ) ; // 2G 2B 2M 2E - LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 24 )|((digit[1]& 0x02) << 6 )|((digit[1]& 0x01) << 2 ) ; // 2F 2A 2C 2D - LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 24 )|((digit[2]& 0x02) << 6 )|((digit[2]& 0x01) << 2 ) ; // 2Q 2K 2Col 2P - LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 24 )|((digit[3]& 0x02) << 6 )|((digit[3]& 0x01) << 2 ) ; // 2H 2J 2DP 2N - - break; - - /* Position 3 on LCD (Digit3)*/ - case 3: - LCD->RAM[LCD_RAMRegister_0] &= 0xfcfffcff; - LCD->RAM[LCD_RAMRegister_2] &= 0xfcfffcff; - LCD->RAM[LCD_RAMRegister_4] &= 0xfcfffcff; - LCD->RAM[LCD_RAMRegister_6] &= 0xfcfffcff; - - LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 22 ) | ((digit[0]& 0x03) << 8 ) ; // 3G 3B 3M 3E - LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 22 ) | ((digit[1]& 0x03) << 8 ) ; // 3F 3A 3C 3D - LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 22 ) | ((digit[2]& 0x03) << 8 ) ; // 3Q 3K 3Col 3P - LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 22 ) | ((digit[3]& 0x03) << 8 ) ; // 3H 3J 3DP 3N - - break; - - /* Position 4 on LCD (Digit4)*/ - case 4: - LCD->RAM[LCD_RAMRegister_0] &= 0xffcff3ff; - LCD->RAM[LCD_RAMRegister_2] &= 0xffcff3ff; - LCD->RAM[LCD_RAMRegister_4] &= 0xffcff3ff; - LCD->RAM[LCD_RAMRegister_6] &= 0xffcff3ff; - - LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 18 ) | ((digit[0]& 0x03) << 10 ) ; // 4G 4B 4M 4E - LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 18 ) | ((digit[1]& 0x03) << 10 ) ; // 4F 4A 4C 4D - LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 18 ) | ((digit[2]& 0x03) << 10 ) ; // 4Q 4K 4Col 4P - LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 18 ) | ((digit[3]& 0x03) << 10 ) ; // 4H 4J 4DP 4N - - break; - - /* Position 5 on LCD (Digit5)*/ - case 5: - LCD->RAM[LCD_RAMRegister_0] &= 0xfff3cfff; - LCD->RAM[LCD_RAMRegister_2] &= 0xfff3cfff; - LCD->RAM[LCD_RAMRegister_4] &= 0xfff3efff; - LCD->RAM[LCD_RAMRegister_6] &= 0xfff3efff; - - LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x0c) << 16 ) | ((digit[0]& 0x03) << 12 ) ; // 5G 5B 5M 5E - LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x0c) << 16 ) | ((digit[1]& 0x03) << 12 ) ; // 5F 5A 5C 5D - LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x0c) << 16 ) | ((digit[2]& 0x01) << 12 ) ; // 5Q 5K 5P - LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x0c) << 16 ) | ((digit[3]& 0x01) << 12 ) ; // 5H 5J 5N - - break; - - /* Position 6 on LCD (Digit6)*/ - case 6: - LCD->RAM[LCD_RAMRegister_0] &= 0xfffc3fff; - LCD->RAM[LCD_RAMRegister_2] &= 0xfffc3fff; - LCD->RAM[LCD_RAMRegister_4] &= 0xfffc3fff; - LCD->RAM[LCD_RAMRegister_6] &= 0xfffc3fff; - - LCD->RAM[LCD_RAMRegister_0] |= ((digit[0]& 0x04) << 15 ) | ((digit[0]& 0x08) << 13 ) | ((digit[0]& 0x03) << 14 ) ; // 6B 6G 6M 6E - LCD->RAM[LCD_RAMRegister_2] |= ((digit[1]& 0x04) << 15 ) | ((digit[1]& 0x08) << 13 ) | ((digit[1]& 0x03) << 14 ) ; // 6A 6F 6C 6D - LCD->RAM[LCD_RAMRegister_4] |= ((digit[2]& 0x04) << 15 ) | ((digit[2]& 0x08) << 13 ) | ((digit[2]& 0x01) << 14 ) ; // 6K 6Q 6P - LCD->RAM[LCD_RAMRegister_6] |= ((digit[3]& 0x04) << 15 ) | ((digit[3]& 0x08) << 13 ) | ((digit[3]& 0x01) << 14 ) ; // 6J 6H 6N - - break; - - default: - break; - } - -/* Refresh LCD bar */ - LCD_bar(); - -/* Update the LCD display */ - LCD_UpdateDisplayRequest(); - -} - -/** - * @brief This function writes a char in the LCD RAM. - * @param ptr: Pointer to string to display on the LCD Glass. - * @retval None - */ -void LCD_GLASS_DisplayString(uint8_t* ptr) -{ - uint8_t i = 0x01; - - /* Send the string character by character on lCD */ - while ((*ptr != 0) & (i < 8)) - { - /* Display one character on LCD */ - LCD_GLASS_WriteChar(ptr, FALSE, FALSE, i); - - /* Point on the next character */ - ptr++; - - /* Increment the character counter */ - i++; - } -} - -/** - * @brief This function writes a char in the LCD RAM. - * @param ptr: Pointer to string to display on the LCD Glass. - * @retval None - * @par Required preconditions: Char is ASCCI value "Ored" with decimal point or Column flag - */ -void LCD_GLASS_DisplayStrDeci(uint16_t* ptr) -{ - uint8_t i = 0x01; - uint8_t char_tmp; - -// LCD_GLASS_Clear(); - /* Send the string character by character on lCD */ - while ((*ptr != 0) & (i < 8)) - { - char_tmp = (*ptr) & 0x00ff; - - switch ((*ptr) & 0xf000) - { - case DOT: - /* Display one character on LCD with decimal point */ - LCD_GLASS_WriteChar(&char_tmp, POINT_ON, COLUMN_OFF, i); - break; - case DOUBLE_DOT: - /* Display one character on LCD with decimal point */ - LCD_GLASS_WriteChar(&char_tmp, POINT_OFF, COLUMN_ON, i); - break; - default: - LCD_GLASS_WriteChar(&char_tmp, POINT_OFF, COLUMN_OFF, i); - break; - }/* Point on the next character */ - ptr++; - - /* Increment the character counter */ - i++; - } -} - -/** - * @brief This function Clear the whole LCD RAM. - * @param None - * @retval None - */ -void LCD_GLASS_Clear(void) -{ - uint8_t counter = 0; - - /* TO wait LCD Ready */ - while( LCD_GetFlagStatus (LCD_FLAG_UDR) != RESET) ; - - for (counter = LCD_RAMRegister_0; counter <= LCD_RAMRegister_15; counter++) - { - LCD->RAM[counter] = 0; - } - - /* Update the LCD display */ - LCD_UpdateDisplayRequest(); - -} - -/** - * @brief Display a string in scrolling mode - * @param ptr: Pointer to string to display on the LCD Glass. - * @param nScroll: Specifies how many time the message will be scrolled - * @param ScrollSpeed : Speciifes the speed of the scroll, low value gives - * higher speed - * @retval None - * @par Required preconditions: The LCD should be cleared before to start the - * write operation. - */ -void LCD_GLASS_ScrollSentence(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed) -{ - uint8_t Repetition; - uint8_t Char_Nb; - uint8_t* ptr1; - uint8_t str[7]=""; - uint8_t Str_size; - - if (ptr == 0) return; - -/* To calculate end of string */ - for (ptr1=ptr,Str_size = 0 ; *ptr1 != 0; Str_size++,ptr1++) ; - - ptr1 = ptr; - - LCD_GLASS_DisplayString(ptr); - Delay(ScrollSpeed); - -/* To shift the string for scrolling display*/ - for (Repetition=0; Repetition
© COPYRIGHT 2011 STMicroelectronics
- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __stm32l_discovery_lcd -#define __stm32l_discovery_lcd - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" -#include "discover_board.h" - -/* Define for scrolling sentences*/ -#define SCROLL_SPEED 300 -#define SCROLL_SPEED_L 600 -#define SCROLL_NUM 1 - -/* Define for character '.' */ -#define POINT_OFF FALSE -#define POINT_ON TRUE - -/* Define for caracter ":" */ -#define COLUMN_OFF FALSE -#define COLUMN_ON TRUE - -#define DOT 0x8000 /* for add decimal point in string */ -#define DOUBLE_DOT 0x4000 /* for add decimal point in string */ - - -/* ========================================================================= - LCD MAPPING - ========================================================================= - A - _ ---------- -COL |_| |\ |J /| - F| H | K |B - _ | \ | / | -COL |_| --G-- --M-- - | /| \ | - E| Q | N |C - _ | / |P \| -DP |_| ----------- - D - - An LCD character coding is based on the following matrix: - { E , D , P , N } - { M , C , COL , DP} - { B , A , K , J } - { G , F , Q , H } - - The character 'A' for example is: - ------------------------------- -LSB { 1 , 0 , 0 , 0 } - { 1 , 1 , 0 , 0 } - { 1 , 1 , 0 , 0 } -MSB { 1 , 1 , 0 , 0 } - ------------------- - 'A' = F E 0 0 hexa - -*/ -/* Macros used for set/reset bar LCD bar */ -#define BAR0_ON t_bar[1] |= 8 -#define BAR0_OFF t_bar[1] &= ~8 -#define BAR1_ON t_bar[0] |= 8 -#define BAR1_OFF t_bar[0] &= ~8 -#define BAR2_ON t_bar[1] |= 2 -#define BAR2_OFF t_bar[1] &= ~2 -#define BAR3_ON t_bar[0] |= 2 -#define BAR3_OFF t_bar[0] &= ~2 - -/* code for 'µ' character */ -#define C_UMAP 0x6084 - -/* code for 'm' character */ -#define C_mMap 0xb210 - -/* code for 'n' character */ -#define C_nMap 0x2210 - -/* constant code for '*' character */ -#define star 0xA0DD - -/* constant code for '-' character */ -#define C_minus 0xA000 - -/* constant code for '/' */ -#define C_slatch 0x00c0 - -/* constant code for ° */ -#define C_percent_1 0xec00 - -/* constant code for small o */ -#define C_percent_2 0xb300 - -#define C_full 0xffdd - -void LCD_bar(void); -void LCD_GLASS_Init(void); -void LCD_GLASS_WriteChar(uint8_t* ch, bool point, bool column,uint8_t position); -void LCD_GLASS_DisplayString(uint8_t* ptr); -void LCD_GLASS_DisplayStrDeci(uint16_t* ptr); -void LCD_GLASS_ClearChar(uint8_t position); -void LCD_GLASS_Clear(void); -void LCD_GLASS_ScrollSentence(uint8_t* ptr, uint16_t nScroll, uint16_t ScrollSpeed); -void LCD_GLASS_WriteTime(char a, uint8_t posi, bool column); -void LCD_GLASS_Configure_GPIO(void); - -#endif /* stm32l_discovery_lcd*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/32vl_factory_demo/Makefile b/example/32vl_factory_demo/Makefile deleted file mode 100644 index 81cdd56ba..000000000 --- a/example/32vl_factory_demo/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -# build an elf from the an3268 demonstration code -APP=32vl_factory_demo - -CC=arm-none-eabi-gcc -OBJCOPY=arm-none-eabi-objcopy - -CFLAGS=-O2 -mlittle-endian -mthumb -CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc -ifeq ($(DEBUG),1) - CFLAGS+=-g -endif - -# to run from SRAM -CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000 - -# to write to flash then run -# CFLAGS+=-Wl,-Ttext,0x08000000 -Wl,-e,0x08000000 - -PLATFORM=stm32f10x -BOARD_SUPPORT=../board_support/discovery_32vl -LIBS_STM_PATH=../libs_stm - -CFLAGS+=-I. -CFLAGS+=-I$(LIBS_STM_PATH)/inc/base -CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support -CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support -CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM) -CFLAGS+=-I$(BOARD_SUPPORT) - -LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_f10x - - -SRCS=$(wildcard *.c) -SRCS+=$(wildcard $(BOARD_SUPPORT)/*.c) - -OBJS=$(SRCS:.c=.o) - -all: $(APP).elf - -%.bin: %.elf - $(OBJCOPY) -O binary $^ $@ - -$(APP).elf: $(OBJS) - $(CC) $(CFLAGS) -o $@ $(OBJS) $(LDFLAGS) - -%.o: %.c - $(CC) $(CFLAGS) -c -o $@ $^ - -clean: - rm -rf $(OBJS) - rm -rf $(APP).* - -.PHONY: all clean diff --git a/example/32vl_factory_demo/README b/example/32vl_factory_demo/README deleted file mode 100644 index 28c83952d..000000000 --- a/example/32vl_factory_demo/README +++ /dev/null @@ -1,5 +0,0 @@ -This source is copied from AN3268, the STM demo code for the VL discovery board. - -It was modified to add includes and things where needed, but nothing else was touched. - -Eventually, this should be usable to restore a board to virgin state. (but not yet) diff --git a/example/32vl_factory_demo/main.c b/example/32vl_factory_demo/main.c deleted file mode 100644 index 0043b650e..000000000 --- a/example/32vl_factory_demo/main.c +++ /dev/null @@ -1,234 +0,0 @@ -/** - ****************************************************************************** - * @file Demo/src/main.c - * @author MCD Application Team - * @version V1.0.0 - * @date 09/13/2010 - * @brief Main program body - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" -#include "stm32f10x_conf.h" -#include "STM32vldiscovery.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define LSE_FAIL_FLAG 0x80 -#define LSE_PASS_FLAG 0x100 -/* Private macro -------------------------------------------------------------*/ -/* Private consts ------------------------------------------------------------*/ - -/* Private variables ---------------------------------------------------------*/ -u32 LSE_Delay = 0; -u32 count = 0; -u32 BlinkSpeed = 0; -u32 KeyState = 0; -static __IO uint32_t TimingDelay; -/* Private function prototypes -----------------------------------------------*/ -void Delay(uint32_t nTime); -void TimingDelay_Decrement(void); - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief Main program. - * @param None - * @retval None - */ - -int main(void) -{ - /* Enable GPIOx Clock */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); - - /* Initialise LEDs LD3&LD4, both off */ - STM32vldiscovery_LEDInit(LED3); - STM32vldiscovery_LEDInit(LED4); - - STM32vldiscovery_LEDOff(LED3); - STM32vldiscovery_LEDOff(LED4); - - /* Initialise USER Button */ - STM32vldiscovery_PBInit(BUTTON_USER, BUTTON_MODE_GPIO); - - /* Setup SysTick Timer for 1 msec interrupts */ - if (SysTick_Config(SystemCoreClock / 1000)) - { - /* Capture error */ - while (1); - } - - /* Enable access to the backup register => LSE can be enabled */ - PWR_BackupAccessCmd(ENABLE); - - /* Enable LSE (Low Speed External Oscillation) */ - RCC_LSEConfig(RCC_LSE_ON); - - /* Check the LSE Status */ - while(1) - { - if(LSE_Delay < LSE_FAIL_FLAG) - { - /* check whether LSE is ready, with 4 seconds timeout */ - Delay (500); - LSE_Delay += 0x10; - if(RCC_GetFlagStatus(RCC_FLAG_LSERDY) != RESET) - { - /* Set flag: LSE PASS */ - LSE_Delay |= LSE_PASS_FLAG; - /* Turn Off Led4 */ - STM32vldiscovery_LEDOff(LED4); - /* Disable LSE */ - RCC_LSEConfig(RCC_LSE_OFF); - break; - } - } - - /* LSE_FAIL_FLAG = 0x80 */ - else if(LSE_Delay >= LSE_FAIL_FLAG) - { - if(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) - { - /* Set flag: LSE FAIL */ - LSE_Delay |= LSE_FAIL_FLAG; - /* Turn On Led4 */ - STM32vldiscovery_LEDOn(LED4); - } - /* Disable LSE */ - RCC_LSEConfig(RCC_LSE_OFF); - break; - } - } - - /* main while */ - while(1) - { - if(0 == STM32vldiscovery_PBGetState(BUTTON_USER)) - { - if(KeyState == 1) - { - if(0 == STM32vldiscovery_PBGetState(BUTTON_USER)) - { - /* USER Button released */ - KeyState = 0; - /* Turn Off LED4 */ - STM32vldiscovery_LEDOff(LED4); - } - } - } - else if(STM32vldiscovery_PBGetState(BUTTON_USER)) - { - if(KeyState == 0) - { - if(STM32vldiscovery_PBGetState(BUTTON_USER)) - { - /* USER Button released */ - KeyState = 1; - /* Turn ON LED4 */ - STM32vldiscovery_LEDOn(LED4); - Delay(1000); - /* Turn OFF LED4 */ - STM32vldiscovery_LEDOff(LED4); - /* BlinkSpeed: 0 -> 1 -> 2, then re-cycle */ - BlinkSpeed ++ ; - } - } - } - count++; - Delay(100); - /* BlinkSpeed: 0 */ - if(BlinkSpeed == 0) - { - if(4 == (count % 8)) - STM32vldiscovery_LEDOn(LED3); - if(0 == (count % 8)) - STM32vldiscovery_LEDOff(LED3); - } - /* BlinkSpeed: 1 */ - if(BlinkSpeed == 1) - { - if(2 == (count % 4)) - STM32vldiscovery_LEDOn(LED3); - if(0 == (count % 4)) - STM32vldiscovery_LEDOff(LED3); - } - /* BlinkSpeed: 2 */ - if(BlinkSpeed == 2) - { - if(0 == (count % 2)) - STM32vldiscovery_LEDOn(LED3); - else - STM32vldiscovery_LEDOff(LED3); - } - /* BlinkSpeed: 3 */ - else if(BlinkSpeed == 3) - BlinkSpeed = 0; - } -} - -/** - * @brief Inserts a delay time. - * @param nTime: specifies the delay time length, in milliseconds. - * @retval None - */ -void Delay(uint32_t nTime) -{ - TimingDelay = nTime; - - while(TimingDelay != 0); -} - -/** - * @brief Decrements the TimingDelay variable. - * @param None - * @retval None - */ -void TimingDelay_Decrement(void) -{ - if (TimingDelay != 0x00) - { - TimingDelay--; - } -} - -#ifdef USE_FULL_ASSERT -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t* file, uint32_t line) -{ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - - /* Infinite loop */ - while (1) - { - } -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/32vl_factory_demo/stm32f10x_conf.h b/example/32vl_factory_demo/stm32f10x_conf.h deleted file mode 100644 index 706b92ed9..000000000 --- a/example/32vl_factory_demo/stm32f10x_conf.h +++ /dev/null @@ -1,76 +0,0 @@ -/** - ****************************************************************************** - * @file Demo/inc/stm32f10x_conf.h - * @author MCD Application Team - * @version V1.0.0 - * @date 09/13/2010 - * @brief Library configuration file. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CONF_H -#define __STM32F10x_CONF_H - -/* Includes ------------------------------------------------------------------*/ -/* Uncomment the line below to enable peripheral header file inclusion */ -/* #include "stm32f10x_adc.h" */ -/* #include "stm32f10x_bkp.h" */ -/* #include "stm32f10x_can.h" */ -/* #include "stm32f10x_crc.h" */ -/* #include "stm32f10x_dac.h" */ -/* #include "stm32f10x_dbgmcu.h" */ -/* #include "stm32f10x_dma.h" */ -#include "stm32f10x_exti.h" -#include "stm32f10x_flash.h" -/* #include "stm32f10x_fsmc.h" */ -#include "stm32f10x_gpio.h" -/* #include "stm32f10x_i2c.h" */ -/* #include "stm32f10x_iwdg.h" */ -#include "stm32f10x_pwr.h" -#include "stm32f10x_rcc.h" -/* #include "stm32f10x_rtc.h" */ -/* #include "stm32f10x_sdio.h" */ -/* #include "stm32f10x_spi.h" */ -/* #include "stm32f10x_tim.h" */ -/* #include "stm32f10x_usart.h" */ -/* #include "stm32f10x_wwdg.h" */ -#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Uncomment the line below to expanse the "assert_param" macro in the - Standard Peripheral Library drivers code */ -/* #define USE_FULL_ASSERT 1 */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT - -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - -#endif /* __STM32F10x_CONF_H */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/32vl_factory_demo/stm32f10x_it.c b/example/32vl_factory_demo/stm32f10x_it.c deleted file mode 100644 index c1035270e..000000000 --- a/example/32vl_factory_demo/stm32f10x_it.c +++ /dev/null @@ -1,160 +0,0 @@ -/** - ****************************************************************************** - * @file Demo/src/stm32f10x_it.c - * @author MCD Application Team - * @version V1.0.0 - * @date 09/13/2010 - * @brief Main Interrupt Service Routines. - * This file provides template for all exceptions handler and peripherals - * interrupt service routine. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_it.h" -void TimingDelay_Decrement(void); -/** @addtogroup Demo - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************/ -/* Cortex-M3 Processor Exceptions Handlers */ -/******************************************************************************/ - -/** - * @brief This function handles NMI exception. - * @param None - * @retval None - */ -void NMI_Handler(void) -{ -} - -/** - * @brief This function handles Hard Fault exception. - * @param None - * @retval None - */ -void HardFault_Handler(void) -{ - /* Go to infinite loop when Hard Fault exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles Memory Manage exception. - * @param None - * @retval None - */ -void MemManage_Handler(void) -{ - /* Go to infinite loop when Memory Manage exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles Bus Fault exception. - * @param None - * @retval None - */ -void BusFault_Handler(void) -{ - /* Go to infinite loop when Bus Fault exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles Usage Fault exception. - * @param None - * @retval None - */ -void UsageFault_Handler(void) -{ - /* Go to infinite loop when Usage Fault exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles SVCall exception. - * @param None - * @retval None - */ -void SVC_Handler(void) -{ -} - -/** - * @brief This function handles Debug Monitor exception. - * @param None - * @retval None - */ -void DebugMon_Handler(void) -{ -} - -/** - * @brief This function handles PendSV_Handler exception. - * @param None - * @retval None - */ -void PendSV_Handler(void) -{ -} - -/** - * @brief This function handles SysTick Handler. - * @param None - * @retval None - */ -void SysTick_Handler(void) -{ - TimingDelay_Decrement(); -} - -/******************************************************************************/ -/* STM32F10x Peripherals Interrupt Handlers */ -/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ -/* available peripheral interrupt handler's name please refer to the startup */ -/* file (startup_stm32f10x_xx.s). */ -/******************************************************************************/ - -/** - * @brief This function handles PPP interrupt request. - * @param None - * @retval None - */ -/*void PPP_IRQHandler(void) -{ -}*/ - - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/32vl_factory_demo/stm32f10x_it.h b/example/32vl_factory_demo/stm32f10x_it.h deleted file mode 100644 index e8d2b316e..000000000 --- a/example/32vl_factory_demo/stm32f10x_it.h +++ /dev/null @@ -1,46 +0,0 @@ -/** - ****************************************************************************** - * @file Demo/inc/stm32f10x_it.h - * @author MCD Team - * @version V1.0.0 - * @date 09/13/2010 - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_IT_H -#define __STM32F10x_IT_H - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/* Exported types ------------------------------------------------------------*/ -extern vu32 TickValue; -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void NMI_Handler(void); -void HardFault_Handler(void); -void MemManage_Handler(void); -void BusFault_Handler(void); -void UsageFault_Handler(void); -void SVC_Handler(void); -void DebugMon_Handler(void); -void PendSV_Handler(void); -void SysTick_Handler(void); - -#endif /* __STM32F10x_IT_H */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/32vl_factory_demo/system_stm32f10x.c b/example/32vl_factory_demo/system_stm32f10x.c deleted file mode 100644 index aed930ec8..000000000 --- a/example/32vl_factory_demo/system_stm32f10x.c +++ /dev/null @@ -1,1019 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f10x.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - ****************************************************************************** - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x_system - * @{ - */ - -/** @addtogroup STM32F10x_System_Private_Includes - * @{ - */ - -#include "stm32f10x.h" - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Defines - * @{ - */ - -/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) - frequency (after reset the HSI is used as SYSCLK source) - - IMPORTANT NOTE: - ============== - 1. After each device reset the HSI is used as System clock source. - - 2. Please make sure that the selected System clock doesn't exceed your device's - maximum frequency. - - 3. If none of the define below is enabled, the HSI is used as System clock - source. - - 4. The System clock configuration functions provided within this file assume that: - - For Low and Medium density Value line devices an external 8MHz crystal - is used to drive the System clock. - - For Low, Medium and High density devices an external 8MHz crystal is - used to drive the System clock. - - For Connectivity line devices an external 25MHz crystal is used to drive - the System clock. - If you are using different crystal you have to adapt those functions accordingly. - */ - -#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) -/* #define SYSCLK_FREQ_HSE HSE_Value */ - #define SYSCLK_FREQ_24MHz 24000000 -#else -/* #define SYSCLK_FREQ_HSE HSE_Value */ -/* #define SYSCLK_FREQ_24MHz 24000000 */ -/* #define SYSCLK_FREQ_36MHz 36000000 */ -/* #define SYSCLK_FREQ_48MHz 48000000 */ -/* #define SYSCLK_FREQ_56MHz 56000000 */ -#define SYSCLK_FREQ_72MHz 72000000 -#endif - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM3210E-EVAL board (STM32 High density and XL-density devices) as data memory */ -#if defined (STM32F10X_HD) || (defined STM32F10X_XL) -/* #define DATA_IN_ExtSRAM */ -#endif - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Variables - * @{ - */ - -/******************************************************************************* -* Clock Definitions -*******************************************************************************/ -#ifdef SYSCLK_FREQ_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_36MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ -#else /*!< HSI Selected as System Clock source */ - uint32_t SystemCoreClock = HSI_Value; /*!< System Clock Frequency (Core Clock) */ -#endif - -__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_HSE - static void SetSysClockToHSE(void); -#elif defined SYSCLK_FREQ_24MHz - static void SetSysClockTo24(void); -#elif defined SYSCLK_FREQ_36MHz - static void SetSysClockTo36(void); -#elif defined SYSCLK_FREQ_48MHz - static void SetSysClockTo48(void); -#elif defined SYSCLK_FREQ_56MHz - static void SetSysClockTo56(void); -#elif defined SYSCLK_FREQ_72MHz - static void SetSysClockTo72(void); -#endif - -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#ifndef STM32F10X_CL - RCC->CFGR &= (uint32_t)0xF8FF0000; -#else - RCC->CFGR &= (uint32_t)0xF0FF0000; -#endif /* STM32F10X_CL */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; - -#ifdef STM32F10X_CL - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEBFFFFFF; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#else - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_HD) || (defined STM32F10X_XL) - #ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); - #endif /* DATA_IN_ExtSRAM */ -#endif - - /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ - /* Configure the Flash Latency cycles and enable prefetch buffer */ - SetSysClock(); -} - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * @note None - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0; - -#ifdef STM32F10X_CL - uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) - uint32_t prediv1factor = 0; -#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL */ - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - SystemCoreClock = HSI_Value; - break; - case 0x04: /* HSE used as system clock */ - SystemCoreClock = HSE_Value; - break; - case 0x08: /* PLL used as system clock */ - - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - -#ifndef STM32F10X_CL - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_Value >> 1) * pllmull; - } - else - { - #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_Value / prediv1factor) * pllmull; - #else - /* HSE selected as PLL clock entry */ - if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) - {/* HSE oscillator clock divided by 2 */ - SystemCoreClock = (HSE_Value >> 1) * pllmull; - } - else - { - SystemCoreClock = HSE_Value * pllmull; - } - #endif - } -#else - pllmull = pllmull >> 18; - - if (pllmull != 0x0D) - { - pllmull += 2; - } - else - { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; - } - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_Value >> 1) * pllmull; - } - else - {/* PREDIV1 selected as PLL clock entry */ - - /* Get PREDIV1 clock source and division factor */ - prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - - if (prediv1source == 0) - { - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_Value / prediv1factor) * pllmull; - } - else - {/* PLL2 clock selected as PREDIV1 clock entry */ - - /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; - SystemCoreClock = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull; - } - } -#endif /* STM32F10X_CL */ - break; - - default: - SystemCoreClock = HSI_Value; - break; - } - - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_24MHz - SetSysClockTo24(); -#elif defined SYSCLK_FREQ_36MHz - SetSysClockTo36(); -#elif defined SYSCLK_FREQ_48MHz - SetSysClockTo48(); -#elif defined SYSCLK_FREQ_56MHz - SetSysClockTo56(); -#elif defined SYSCLK_FREQ_72MHz - SetSysClockTo72(); -#endif - - /* If none of the define above is enabled, the HSI is used as System clock - source (default after reset) */ -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f10x.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f10x_xx.s/.c before jump to main. - * This function configures the external SRAM mounted on STM3210E-EVAL - * board (STM32 High density devices). This SRAM will be used as program - * data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is - required, then adjust the Register Addresses */ - - /* Enable FSMC clock */ - RCC->AHBENR = 0x00000114; - - /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ - RCC->APB2ENR = 0x000001E0; - -/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ -/*---------------- SRAM Address lines configuration -------------------------*/ -/*---------------- NOE and NWE configuration --------------------------------*/ -/*---------------- NE3 configuration ----------------------------------------*/ -/*---------------- NBL0, NBL1 configuration ---------------------------------*/ - - GPIOD->CRL = 0x44BB44BB; - GPIOD->CRH = 0xBBBBBBBB; - - GPIOE->CRL = 0xB44444BB; - GPIOE->CRH = 0xBBBBBBBB; - - GPIOF->CRL = 0x44BBBBBB; - GPIOF->CRH = 0xBBBB4444; - - GPIOG->CRL = 0x44BBBBBB; - GPIOG->CRH = 0x44444B44; - -/*---------------- FSMC Configuration ---------------------------------------*/ -/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ - - FSMC_Bank1->BTCR[4] = 0x00001011; - FSMC_Bank1->BTCR[5] = 0x00000200; -} -#endif /* DATA_IN_ExtSRAM */ - -#ifdef SYSCLK_FREQ_HSE -/** - * @brief Selects HSE as System clock source and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - -#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 0 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - -#ifndef STM32F10X_CL - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#else - if (HSE_Value <= 24000000) - { - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; - } - else - { - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; - } -#endif /* STM32F10X_CL */ -#endif - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* Select HSE as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; - - /* Wait till HSE is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_24MHz -/** - * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo24(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { -#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 0 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; -#endif - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL6); - - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) - /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); -#else - /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_36MHz -/** - * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo36(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - - /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL9); - - /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - -#else - /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_48MHz -/** - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo48(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL6); -#else - /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_56MHz -/** - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo56(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 2 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL7); -#else - /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); - -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_72MHz -/** - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo72(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSEStartUp_TimeOut)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 2 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; - - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | - RCC_CFGR_PLLMULL9); -#else - /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | - RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); -#endif /* STM32F10X_CL */ - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/README b/example/README deleted file mode 100644 index 5d72e8282..000000000 --- a/example/README +++ /dev/null @@ -1,6 +0,0 @@ -Don't trust many of these examples yet... A lot of them are a work in -progress... - -A good source of examples is in the libopencm3 sources: http://sourceforge.net/projects/libopencm3/ - - diff --git a/example/blink/Makefile b/example/blink/Makefile deleted file mode 100644 index 60fab84c8..000000000 --- a/example/blink/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -CC=arm-none-eabi-gcc -OBJCOPY=arm-none-eabi-objcopy - -DEF_CFLAGS=-g -O2 -mlittle-endian -mthumb -ffreestanding -nostdlib -nostdinc - -# to run from SRAM -DEF_CFLAGS+=-Wl,-Ttext,0x20000000 -Wl,-e,0x20000000 - -# to write to flash then run -# DEF_CFLAGS+=-Wl,-Ttext,0x08000000 -Wl,-e,0x08000000 - -CFLAGS_VL=$(DEF_CFLAGS) -mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1 -CFLAGS_L=$(DEF_CFLAGS) -mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY -CFLAGS_F4=$(DEF_CFLAGS) -mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1 -CFLAGS_F0=$(DEF_CFLAGS) -mcpu=cortex-m0 -DCONFIG_STM32F0_DISCOVERY=1 - -all: blink_32VL.elf blink_32L.elf blink_F4.elf blink_F0.elf - -%.bin: %.elf - $(OBJCOPY) -O binary $^ $@ - -blink_32VL.elf: main.c - $(CC) $(CFLAGS_VL) $^ -o $@ -blink_32L.elf: main.c - $(CC) $(CFLAGS_L) $^ -o $@ -blink_F4.elf: main.c - $(CC) $(CFLAGS_F4) $^ -o $@ -blink_F0.elf: main.c - $(CC) $(CFLAGS_F0) $^ -o $@ - -clean: - rm -rf *.elf - rm -rf *.bin - -.PHONY: all clean diff --git a/example/blink/main.c b/example/blink/main.c deleted file mode 100644 index 26fcca029..000000000 --- a/example/blink/main.c +++ /dev/null @@ -1,114 +0,0 @@ -/* missing type */ - -typedef unsigned int uint32_t; -void main(void); - -/* hardware configuration */ - -#if CONFIG_STM32VL_DISCOVERY - -#define GPIOC 0x40011000 /* port C */ -#define GPIOC_CRH (GPIOC + 0x04) /* port configuration register high */ -#define LED_PORT_ODR (GPIOC + 0x0c) /* port output data register */ - -#define LED_BLUE (1 << 8) /* port C, pin 8 */ -#define LED_GREEN (1 << 9) /* port C, pin 9 */ -#define LED_ORANGE 0 -#define LED_RED 0 - -static inline void setup_leds(void) -{ - *(volatile uint32_t*)GPIOC_CRH = 0x44444411; -} - -#elif CONFIG_STM32L_DISCOVERY - -#define GPIOB 0x40020400 /* port B */ -#define GPIOB_MODER (GPIOB + 0x00) /* port mode register */ -#define LED_PORT_ODR (GPIOB + 0x14) /* port output data register */ - -#define LED_BLUE (1 << 6) /* port B, pin 6 */ -#define LED_GREEN (1 << 7) /* port B, pin 7 */ -#define LED_ORANGE 0 -#define LED_RED 0 - -static inline void setup_leds(void) -{ - /* configure port 6 and 7 as output */ - *(volatile uint32_t*)GPIOB_MODER |= (1 << (7 * 2)) | (1 << (6 * 2)); -} - -#elif CONFIG_STM32F4_DISCOVERY - -#define GPIOD 0x40020C00 /* port D */ -#define GPIOD_MODER (GPIOD + 0x00) /* port mode register */ -#define LED_PORT_ODR (GPIOD + 0x14) /* port output data register */ - -#define LED_GREEN (1 << 12) /* port D, pin 12 */ -#define LED_ORANGE (1 << 13) /* port D, pin 13 */ -#define LED_RED (1 << 14) /* port D, pin 14 */ -#define LED_BLUE (1 << 15) /* port D, pin 15 */ - -void _tmain(void) { - main(); -} -static inline void setup_leds(void) -{ - *(volatile uint32_t*)GPIOD_MODER |= (1 << (12 * 2)) | (1 << (13 * 2)) | - (1 << (13 * 2)) | (1 << (14 * 2)) | (1 << (15 * 2)); -} - -#elif CONFIG_STM32F0_DISCOVERY - -#define GPIOC 0x48000800 /* port C */ -#define GPIOC_MODER (GPIOC + 0x00) /* port mode register */ -#define LED_PORT_ODR (GPIOC + 0x14) /* port output data register */ - -#define LED_BLUE (1 << 8) /* port C, pin 8 */ -#define LED_GREEN (1 << 9) /* port C, pin 9 */ -#define LED_ORANGE 0 -#define LED_RED 0 - -void _tmain(void) { - main(); -} -static inline void setup_leds(void) -{ - /* configure port 8 and 9 as output */ - *(volatile uint32_t*)GPIOC_MODER |= (1 << (9* 2)) | (1 << (8 * 2)); -} - -#else -#error "Architecture must be defined!" -#endif /* otherwise, error */ - -static inline void switch_leds_on(void) -{ - *(volatile uint32_t*)LED_PORT_ODR = LED_BLUE | LED_GREEN | LED_ORANGE | LED_RED; -} - -static inline void switch_leds_off(void) -{ - *(volatile uint32_t*)LED_PORT_ODR = 0; -} - -#define delay() \ -do { \ - register unsigned int i; \ - for (i = 0; i < 1000000; ++i) \ - __asm__ __volatile__ ("nop\n\t":::"memory"); \ -} while (0) - -/* static void __attribute__((naked)) __attribute__((used)) main(void) */ -void main(void) -{ - setup_leds(); - - while (1) - { - switch_leds_on(); - delay(); - switch_leds_off(); - delay(); - } -} diff --git a/example/blink_flash/Makefile b/example/blink_flash/Makefile deleted file mode 100644 index 1696bf5f0..000000000 --- a/example/blink_flash/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -EXECUTABLE=blink.elf -BIN_IMAGE=blink.bin - -CC=arm-none-eabi-gcc -OBJCOPY=arm-none-eabi-objcopy - -CFLAGS=-O3 -mlittle-endian -mthumb -ifeq ($(CONFIG_STM32L_DISCOVERY), 1) - CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY=1 -else ifeq ($(CONFIG_STM32VL_DISCOVERY), 1) - CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1 -else ifeq ($(CONFIG_STM32F4_DISCOVERY), 1) - CFLAGS+=-mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1 -else -$(error "must specify CONFIG_ for board!") -endif -CFLAGS+=-ffreestanding -nostdlib -nostdinc - -# to run from FLASH -CFLAGS+=-Wl,-T,stm32_flash.ld - -PLATFORM=stm32l1xx -LIBS_STM_PATH=../libs_stm - -# stm32l_discovery lib -CFLAGS+=-I$(LIBS_STM_PATH)/inc/base -CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support -CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support -CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM) - -LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_l1xx - -all: $(BIN_IMAGE) - -$(BIN_IMAGE): $(EXECUTABLE) - $(OBJCOPY) -O binary $^ $@ - -$(EXECUTABLE): main.c system_stm32l1xx.c startup_stm32l1xx_md.s - $(CC) $(CFLAGS) $^ -o $@ $(LDFLAGS) - -clean: - rm -rf $(EXECUTABLE) - rm -rf $(BIN_IMAGE) - -write: all - sudo ../../flash/flash write ./blink.bin 0x08000000 - -.PHONY: all clean diff --git a/example/blink_flash/discover_board.h b/example/blink_flash/discover_board.h deleted file mode 100644 index d93a184aa..000000000 --- a/example/blink_flash/discover_board.h +++ /dev/null @@ -1,61 +0,0 @@ - /** - ****************************************************************************** - * @file discover_board.h - * @author Microcontroller Division - * @version V1.0.2 - * @date September-2011 - * @brief Input/Output defines - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __DISCOVER_BOARD_H -#define __DISCOVER_BOARD_H - -/* Includes ------------------------------------------------------------------*/ -/* #include "stm32l1xx.h" */ - -#define bool _Bool -#define FALSE 0 -#define TRUE !FALSE - -/* MACROs for SET, RESET or TOGGLE Output port */ - -#define GPIO_HIGH(a,b) a->BSRRL = b -#define GPIO_LOW(a,b) a->BSRRH = b -#define GPIO_TOGGLE(a,b) a->ODR ^= b - -#define USERBUTTON_GPIO_PORT GPIOA -#define USERBUTTON_GPIO_PIN GPIO_Pin_0 -#define USERBUTTON_GPIO_CLK RCC_AHBPeriph_GPIOA - -#define LD_GPIO_PORT GPIOB -#define LD_GREEN_GPIO_PIN GPIO_Pin_7 -#define LD_BLUE_GPIO_PIN GPIO_Pin_6 -#define LD_GPIO_PORT_CLK RCC_AHBPeriph_GPIOB - -#define CTN_GPIO_PORT GPIOC -#define CTN_CNTEN_GPIO_PIN GPIO_Pin_13 -#define CTN_GPIO_CLK RCC_AHBPeriph_GPIOC - -#define WAKEUP_GPIO_PORT GPIOA - -#define IDD_MEASURE_PORT GPIOA -#define IDD_MEASURE GPIO_Pin_4 - - -#endif - - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/blink_flash/main.c b/example/blink_flash/main.c deleted file mode 100644 index 4385b0971..000000000 --- a/example/blink_flash/main.c +++ /dev/null @@ -1,197 +0,0 @@ -/* base headers */ -#include "stdint.h" - -/* libstm32l_discovery headers */ -#include "stm32l1xx_gpio.h" -#include "stm32l1xx_adc.h" -#include "stm32l1xx_lcd.h" -#include "stm32l1xx_rcc.h" -#include "stm32l1xx_rtc.h" -#include "stm32l1xx_exti.h" -#include "stm32l1xx_pwr.h" -#include "stm32l1xx_flash.h" -#include "stm32l1xx_syscfg.h" -#include "stm32l1xx_dbgmcu.h" - -/* board specific macros */ -#include "discover_board.h" - - -/* hardware configuration */ - -#if CONFIG_STM32VL_DISCOVERY - -# define GPIOC 0x40011000 /* port C */ -# define GPIOC_CRH (GPIOC + 0x04) /* port configuration register high */ -# define GPIOC_ODR (GPIOC + 0x0c) /* port output data register */ - -# define LED_BLUE (1 << 8) /* port C, pin 8 */ -# define LED_GREEN (1 << 9) /* port C, pin 9 */ - -static inline void setup_leds(void) -{ - *(volatile uint32_t*)GPIOC_CRH = 0x44444411; -} - -static inline void switch_leds_on(void) -{ - *(volatile uint32_t*)GPIOC_ODR = LED_BLUE | LED_GREEN; -} - -static inline void switch_leds_off(void) -{ - *(volatile uint32_t*)GPIOC_ODR = 0; -} - -#elif CONFIG_STM32L_DISCOVERY - -# define GPIOB_MODER (GPIOB + 0x00) /* port mode register */ -# define GPIOB_ODR (GPIOB + 0x14) /* port output data register */ - -# define LED_BLUE (1 << 6) /* port B, pin 6 */ -# define LED_GREEN (1 << 7) /* port B, pin 7 */ - -static inline void setup_leds(void) -{ - /* configure port 6 and 7 as output */ - *(volatile uint32_t*)GPIOB_MODER |= (1 << (7 * 2)) | (1 << (6 * 2)); -} - -static inline void switch_leds_on(void) -{ - GPIO_HIGH(LD_GPIO_PORT, LD_GREEN_GPIO_PIN); - GPIO_HIGH(LD_GPIO_PORT, LD_BLUE_GPIO_PIN); -} - -static inline void switch_leds_off(void) -{ - GPIO_LOW(LD_GPIO_PORT, LD_GREEN_GPIO_PIN); - GPIO_LOW(LD_GPIO_PORT, LD_BLUE_GPIO_PIN); -} - -#elif CONFIG_STM32F4_DISCOVERY - -//#define GPIOD 0x40020C00 /* port D */ -# define GPIOD_MODER (GPIOD + 0x00) /* port mode register */ -# define GPIOD_ODR (GPIOD + 0x14) /* port output data register */ - -# define LED_GREEN (1 << 12) /* port B, pin 12 */ -# define LED_ORANGE (1 << 13) /* port B, pin 13 */ -# define LED_RED (1 << 14) /* port B, pin 14 */ -# define LED_BLUE (1 << 15) /* port B, pin 15 */ - -void _tmain(void) { - main(); -} -static inline void setup_leds(void) -{ - *(volatile uint32_t*)GPIOD_MODER |= (1 << (12 * 2)) | (1 << (13 * 2)) | - (1 << (13 * 2)) | (1 << (14 * 2)) | (1 << (15 * 2)); -} - - -static inline void switch_leds_on(void) -{ - *(volatile uint32_t*)GPIOD_ODR = LED_GREEN | LED_RED ; -} - -static inline void switch_leds_off(void) -{ - *(volatile uint32_t*)GPIOD_ODR = 0; -} - -#endif /* otherwise, error */ - - -#define delay() \ -do { \ - volatile unsigned int i; \ - for (i = 0; i < 1000000; ++i) \ - __asm__ __volatile__ ("nop\n\t":::"memory"); \ -} while (0) - - -static void RCC_Configuration(void) -{ - /* Enable HSI Clock */ - RCC_HSICmd(ENABLE); - - /*!< Wait till HSI is ready */ - while (RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET) - {} - - RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI); - - RCC_MSIRangeConfig(RCC_MSIRange_6); - - RCC_HSEConfig(RCC_HSE_OFF); - if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET ) - { - while(1); - } -} - - -static void RTC_Configuration(void) -{ - /* Allow access to the RTC */ - PWR_RTCAccessCmd(ENABLE); - - /* Reset Backup Domain */ - RCC_RTCResetCmd(ENABLE); - RCC_RTCResetCmd(DISABLE); - - /* LSE Enable */ - RCC_LSEConfig(RCC_LSE_ON); - - /* Wait till LSE is ready */ - while (RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) - {} - - RCC_RTCCLKCmd(ENABLE); - - /* LCD Clock Source Selection */ - RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); - -} - -void main(void) -{ - static RCC_ClocksTypeDef RCC_Clocks; - static GPIO_InitTypeDef GPIO_InitStructure; - - /* Configure Clocks for Application need */ - RCC_Configuration(); - - /* Configure RTC Clocks */ - RTC_Configuration(); - - /* Set internal voltage regulator to 1.8V */ - PWR_VoltageScalingConfig(PWR_VoltageScaling_Range1); - - /* Wait Until the Voltage Regulator is ready */ - while (PWR_GetFlagStatus(PWR_FLAG_VOS) != RESET) ; - - /* configure gpios */ - - /* Enable GPIOs clock */ - RCC_AHBPeriphClockCmd(LD_GPIO_PORT_CLK, ENABLE); - - /* Configure the GPIO_LED pins LD3 & LD4*/ - GPIO_InitStructure.GPIO_Pin = LD_GREEN_GPIO_PIN | LD_BLUE_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_Init(LD_GPIO_PORT, &GPIO_InitStructure); - GPIO_LOW(LD_GPIO_PORT, LD_GREEN_GPIO_PIN); - GPIO_LOW(LD_GPIO_PORT, LD_BLUE_GPIO_PIN); - - while (1) - { - switch_leds_on(); - delay(); - switch_leds_off(); - delay(); - } -} diff --git a/example/blink_flash/startup_stm32l1xx_md.s b/example/blink_flash/startup_stm32l1xx_md.s deleted file mode 100644 index 9a8389c9f..000000000 --- a/example/blink_flash/startup_stm32l1xx_md.s +++ /dev/null @@ -1,365 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32l1xx_md.s - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief STM32L1xx Ultra Low Power Medium-density Devices vector table for - * RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ******************************************************************************* - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ******************************************************************************* - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the clock system intitialization function.*/ -/* let main do the system initialization */ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/******************************************************************************* -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_STAMP_IRQHandler - .word RTC_WKUP_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_IRQHandler - .word USB_HP_IRQHandler - .word USB_LP_IRQHandler - .word DAC_IRQHandler - .word COMP_IRQHandler - .word EXTI9_5_IRQHandler - .word LCD_IRQHandler - .word TIM9_IRQHandler - .word TIM10_IRQHandler - .word TIM11_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word USB_FS_WKUP_IRQHandler - .word TIM6_IRQHandler - .word TIM7_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32L15x ULtra Low Power Medium-density devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_STAMP_IRQHandler - .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak USB_HP_IRQHandler - .thumb_set USB_HP_IRQHandler,Default_Handler - - .weak USB_LP_IRQHandler - .thumb_set USB_LP_IRQHandler,Default_Handler - - .weak DAC_IRQHandler - .thumb_set DAC_IRQHandler,Default_Handler - - .weak COMP_IRQHandler - .thumb_set COMP_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak LCD_IRQHandler - .thumb_set LCD_IRQHandler,Default_Handler - - .weak TIM9_IRQHandler - .thumb_set TIM9_IRQHandler,Default_Handler - - .weak TIM10_IRQHandler - .thumb_set TIM10_IRQHandler,Default_Handler - - .weak TIM11_IRQHandler - .thumb_set TIM11_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak USB_FS_WKUP_IRQHandler - .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - -/******************** (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE***/ - diff --git a/example/blink_flash/stm32_flash.ld b/example/blink_flash/stm32_flash.ld deleted file mode 100644 index 146b16ecc..000000000 --- a/example/blink_flash/stm32_flash.ld +++ /dev/null @@ -1,173 +0,0 @@ -/* -***************************************************************************** -** -** File : stm32_flash.ld -** -** Abstract : Linker script for STM32L152RB Device with -** 128KByte FLASH, 16KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** Environment : Atollic TrueSTUDIO(R) -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -** (c)Copyright Atollic AB. -** You may use this file as-is or modify it according to the needs of your -** project. Distribution of this file (unmodified or modified) is not -** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the -** rights to distribute the assembled, compiled & linked contents of this -** file as part of an application binary file, provided that it is built -** using the Atollic TrueSTUDIO(R) toolchain. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20004000; /* end of 16K RAM */ - -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0; /* required amount of heap */ -_Min_Stack_Size = 0x80; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K - MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K - RW_EEPROM (rw) : ORIGIN = 0x08080000, LENGTH = 32 -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(.fini_array*)) - KEEP (*(SORT(.fini_array.*))) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = .; - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : AT ( _sidata ) - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(4); - } >RAM - - /* MEMORY_bank1 section, code must be located here explicitly */ - /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ - .memory_b1_text : - { - *(.mb1text) /* .mb1text sections (code) */ - *(.mb1text*) /* .mb1text* sections (code) */ - *(.mb1rodata) /* read-only data (constants) */ - *(.mb1rodata*) - } >MEMORY_B1 - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } - - .DataFlash (NOLOAD): {*(.DataFlash)} >RW_EEPROM -} diff --git a/example/blink_flash/system_stm32l1xx.c b/example/blink_flash/system_stm32l1xx.c deleted file mode 100644 index 6deab320c..000000000 --- a/example/blink_flash/system_stm32l1xx.c +++ /dev/null @@ -1,367 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l1xx.c - * @author MCD Application Team - * @version V1.0.0 - * @date 2-June-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32L1xx Ultra - * Low Medium-density devices, and is generated by the clock configuration - * tool "STM32L1xx_Clock_Configuration_V1.0.0.xls". - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32l1xx_md.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32l1xx_md.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and MSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define - * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - * System Clock Configuration - *============================================================================= - * System clock source | HSI - *----------------------------------------------------------------------------- - * SYSCLK | 16000000 Hz - *----------------------------------------------------------------------------- - * HCLK | 16000000 Hz - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 - *----------------------------------------------------------------------------- - * HSE Frequency | 8000000 Hz - *----------------------------------------------------------------------------- - * PLL DIV | Not Used - *----------------------------------------------------------------------------- - * PLL MUL | Not Used - *----------------------------------------------------------------------------- - * VDD | 3.3 V - *----------------------------------------------------------------------------- - * Vcore | 1.8 V (Range 1) - *----------------------------------------------------------------------------- - * Flash Latency | 0 WS - *----------------------------------------------------------------------------- - * Require 48MHz for USB clock | Disabled - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx_system - * @{ - */ - -/** @addtogroup STM32L1xx_System_Private_Includes - * @{ - */ - -#include "stm32l1xx.h" - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Defines - * @{ - */ -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Variables - * @{ - */ -uint32_t SystemCoreClock = 16000000; -__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; -__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /*!< Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100; - - /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t)0x88FFC00C; - - /*!< Reset HSION, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xEEFEFFFE; - - /*!< Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFF; - - /*!< Disable all interrupts */ - RCC->CIR = 0x00000000; - - /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ - SetSysClock(); - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif -} - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI - * value as defined by the MSI range. - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); - break; - case 0x04: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case 0x08: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case 0x0C: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; - plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; - pllmul = PLLMulTable[(pllmul >> 18)]; - plldiv = (plldiv >> 22) + 1; - - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - - if (pllsource == 0x00) - { - /* HSI oscillator clock selected as PLL clock entry */ - SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); - } - else - { - /* HSE selected as PLL clock entry */ - SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); - } - break; - default: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); - break; - } - /* Compute HCLK clock frequency --------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash - * settings. - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSI */ - RCC->CR |= ((uint32_t)RCC_CR_HSION); - - /* Wait till HSI is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CR & RCC_CR_HSIRDY; - } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSIRDY) != RESET) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - if (HSIStatus == (uint32_t)0x01) - { - /* Flash 0 wait state */ - FLASH->ACR &= ~FLASH_ACR_LATENCY; - - /* Disable Prefetch Buffer */ - FLASH->ACR &= ~FLASH_ACR_PRFTEN; - - /* Disable 64-bit access */ - FLASH->ACR &= ~FLASH_ACR_ACC64; - - - /* Power enable */ - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - - /* Select the Voltage Range 1 (1.8 V) */ - PWR->CR = PWR_CR_VOS_0; - - - /* Wait Until the Voltage Regulator is ready */ - while((PWR->CSR & PWR_CSR_VOSF) != RESET) - { - } - - /* HCLK = SYSCLK /1*/ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - /* PCLK2 = HCLK /1*/ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK /1*/ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* Select HSI as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI; - - /* Wait till HSI is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI) - { - } - } - else - { - /* If HSI fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/README b/example/libs_stm/README deleted file mode 100644 index c3dcc4e4b..000000000 --- a/example/libs_stm/README +++ /dev/null @@ -1,9 +0,0 @@ -This directory contains the StdPeriph libraries from ST, and the CMSIS core and device -support, all from ST. - -Issues: -* No tracking of which version of which library (yet) -* Both of these define assert_param() as empty. That may not be what you - want! - - diff --git a/example/libs_stm/build/Makefile b/example/libs_stm/build/Makefile deleted file mode 100644 index d35e3d69f..000000000 --- a/example/libs_stm/build/Makefile +++ /dev/null @@ -1,10 +0,0 @@ - -all: - make -f Makefile.f10x - make -f Makefile.l1xx - -clean: - make -f Makefile.f10x clean - make -f Makefile.l1xx clean - -.PHONY: all clean diff --git a/example/libs_stm/build/Makefile.common b/example/libs_stm/build/Makefile.common deleted file mode 100644 index 954413e1b..000000000 --- a/example/libs_stm/build/Makefile.common +++ /dev/null @@ -1,34 +0,0 @@ -CC = arm-none-eabi-gcc -AR = arm-none-eabi-ar -RANLIB = arm-none-eabi-ranlib - - -INC_CORE_SUPPORT=../inc/core_support -SRC_CORE_SUPPORT=../inc/core_support -INC_DEVICE_SUPPORT=../inc/device_support -INC_PLATFORM=../inc/$(PLATFORM) -SRC_PLATFORM=../src/$(PLATFORM) - -CFLAGS += -Wall -O2 -mlittle-endian -mthumb -CFLAGS += -mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc -CFLAGS += -I$(INC_PLATFORM) -I$(INC_DEVICE_SUPPORT) -I$(INC_CORE_SUPPORT) -I../inc/base - -SRCS=$(wildcard $(SRC_PLATFORM)/*.c) -SRCS+=$(SRC_CORE_SUPPORT)/core_cm3.c - -OBJS = $(SRCS:.c=.o) - -all: $(LIB) - -$(LIB): $(OBJS) - $(AR) -r $(LIB) $(OBJS) - $(RANLIB) $(LIB) - -%.o : %.c - $(CC) $(CFLAGS) -c -o $@ $^ - -clean: - -rm -f $(OBJS) - -rm -f $(LIB) - -.PHONY: all clean diff --git a/example/libs_stm/build/Makefile.f10x b/example/libs_stm/build/Makefile.f10x deleted file mode 100644 index dfe0376ab..000000000 --- a/example/libs_stm/build/Makefile.f10x +++ /dev/null @@ -1,5 +0,0 @@ -LIB = libstm32_stdperiph_f10x.a -PLATFORM=stm32f10x -CFLAGS+= -mcpu=cortex-m3 - -include Makefile.common diff --git a/example/libs_stm/build/Makefile.l1xx b/example/libs_stm/build/Makefile.l1xx deleted file mode 100644 index 7469ff58f..000000000 --- a/example/libs_stm/build/Makefile.l1xx +++ /dev/null @@ -1,5 +0,0 @@ -LIB = libstm32_stdperiph_l1xx.a -PLATFORM=stm32l1xx -CFLAGS+=-mcpu=cortex-m3 - -include Makefile.common diff --git a/example/libs_stm/inc/base/stdint.h b/example/libs_stm/inc/base/stdint.h deleted file mode 100644 index 00d4aaf82..000000000 --- a/example/libs_stm/inc/base/stdint.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef STDINT_H_INCLUDED -# define STDINT_H_INCLUDED - - -typedef char int8_t; -typedef short int16_t; -typedef int int32_t; -typedef long long int64_t; - -typedef unsigned char uint8_t; -typedef unsigned short uint16_t; -typedef unsigned int uint32_t; -typedef unsigned long long uint64_t; - - -#endif /* ! STDINT_H_INCLUDED */ diff --git a/example/libs_stm/inc/core_support/core_cm3.c b/example/libs_stm/inc/core_support/core_cm3.c deleted file mode 100644 index 56fddc52b..000000000 --- a/example/libs_stm/inc/core_support/core_cm3.c +++ /dev/null @@ -1,784 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -__ASM void __CLREX(void) -{ - clrex -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); - __ASM("bx lr"); -} - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) __attribute__( ( naked ) ); -uint32_t __get_PSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, psp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n\t" - "BX lr \n\t" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) __attribute__( ( naked ) ); -uint32_t __get_MSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, msp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n\t" - "BX lr \n\t" : : "r" (topOfMainStack) ); -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -uint32_t __get_BASEPRI(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -uint32_t __get_FAULTMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result=0; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result=0; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif diff --git a/example/libs_stm/inc/core_support/core_cm3.h b/example/libs_stm/inc/core_support/core_cm3.h deleted file mode 100644 index 2b6b51a7d..000000000 --- a/example/libs_stm/inc/core_support/core_cm3.h +++ /dev/null @@ -1,1818 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CM3_CORE_H__ -#define __CM3_CORE_H__ - -/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration - * - * List of Lint messages which will be suppressed and not shown: - * - Error 10: \n - * register uint32_t __regBasePri __asm("basepri"); \n - * Error 10: Expecting ';' - * . - * - Error 530: \n - * return(__regBasePri); \n - * Warning 530: Symbol '__regBasePri' (line 264) not initialized - * . - * - Error 550: \n - * __regBasePri = (basePri & 0x1ff); \n - * Warning 550: Symbol '__regBasePri' (line 271) not accessed - * . - * - Error 754: \n - * uint32_t RESERVED0[24]; \n - * Info 754: local structure member '' (line 109, file ./cm3_core.h) not referenced - * . - * - Error 750: \n - * #define __CM3_CORE_H__ \n - * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced - * . - * - Error 528: \n - * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n - * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced - * . - * - Error 751: \n - * } InterruptType_Type; \n - * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced - * . - * Note: To re-enable a Message, insert a space before 'lint' * - * - */ - -/*lint -save */ -/*lint -e10 */ -/*lint -e530 */ -/*lint -e550 */ -/*lint -e754 */ -/*lint -e750 */ -/*lint -e528 */ -/*lint -e751 */ - - -/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core registers and bitfields - - Cortex-M core peripheral base address - @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -#include /* Include standard types */ - -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register - @{ -*/ - - -/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ -} NVIC_Type; -/*@}*/ /* end of group CMSIS_CM3_NVIC */ - - -/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB - memory mapped structure for System Control Block (SCB) - @{ - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@}*/ /* end of group CMSIS_CM3_SCB */ - - -/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick - memory mapped structure for SysTick - @{ - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@}*/ /* end of group CMSIS_CM3_SysTick */ - - -/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM - memory mapped structure for Instrumentation Trace Macrocell (ITM) - @{ - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ - __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ - __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ -/*@}*/ /* end of group CMSIS_CM3_ITM */ - - -/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type - memory mapped structure for Interrupt Type - @{ - */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ -#else - uint32_t RESERVED1; -#endif -} InterruptType_Type; - -/* Interrupt Controller Type Register Definitions */ -#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ -#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ -#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ - -#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ -#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ - -#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ -#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ -/*@}*/ /* end of group CMSIS_CM3_InterruptType */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU - memory mapped structure for Memory Protection Unit (MPU) - @{ - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ -#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ -#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ -#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ -#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ -#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ -#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@}*/ /* end of group CMSIS_CM3_MPU */ -#endif - - -/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug - memory mapped structure for Core Debug Register - @{ - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ -/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_register */ - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#define __enable_fault_irq __enable_fiq -#define __disable_fault_irq __disable_fiq - -#define __NOP __nop -#define __WFI __wfi -#define __WFE __wfe -#define __SEV __sev -#define __ISB() __isb(0) -#define __DSB() __dsb(0) -#define __DMB() __dmb(0) -#define __REV __rev -#define __RBIT __rbit -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) -#define __STREXB(value, ptr) __strex(value, ptr) -#define __STREXH(value, ptr) __strex(value, ptr) -#define __STREXW(value, ptr) __strex(value, ptr) - - -/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */ -/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */ -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -extern void __CLREX(void); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -#else /* (__ARMCC_VERSION >= 400000) */ - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -#define __CLREX __clrex - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#define __enable_irq __enable_interrupt /*!< global Interrupt enable */ -#define __disable_irq __disable_interrupt /*!< global Interrupt disable */ - -static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } - -#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ -static __INLINE void __WFI() { __ASM ("wfi"); } -static __INLINE void __WFE() { __ASM ("wfe"); } -static __INLINE void __SEV() { __ASM ("sev"); } -static __INLINE void __CLREX() { __ASM ("clrex"); } - -/* intrinsic void __ISB(void) */ -/* intrinsic void __DSB(void) */ -/* intrinsic void __DMB(void) */ -/* intrinsic void __set_PRIMASK(); */ -/* intrinsic void __get_PRIMASK(); */ -/* intrinsic void __set_FAULTMASK(); */ -/* intrinsic void __get_FAULTMASK(); */ -/* intrinsic uint32_t __REV(uint32_t value); */ -/* intrinsic uint32_t __REVSH(uint32_t value); */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */ -/* intrinsic unsigned long __LDREX(unsigned long *); */ - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } -static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } - -static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } -static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } - -static __INLINE void __NOP() { __ASM volatile ("nop"); } -static __INLINE void __WFI() { __ASM volatile ("wfi"); } -static __INLINE void __WFE() { __ASM volatile ("wfe"); } -static __INLINE void __SEV() { __ASM volatile ("sev"); } -static __INLINE void __ISB() { __ASM volatile ("isb"); } -static __INLINE void __DSB() { __ASM volatile ("dsb"); } -static __INLINE void __DMB() { __ASM volatile ("dmb"); } -static __INLINE void __CLREX() { __ASM volatile ("clrex"); } - - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -extern uint32_t __get_PSP(void); - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -extern void __set_PSP(uint32_t topOfProcStack); - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -extern uint32_t __get_MSP(void); - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -extern void __set_MSP(uint32_t topOfMainStack); - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -extern uint32_t __get_BASEPRI(void); - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -extern void __set_BASEPRI(uint32_t basePri); - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -extern uint32_t __get_PRIMASK(void); - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -extern void __set_PRIMASK(uint32_t priMask); - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -extern uint32_t __get_FAULTMASK(void); - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -extern void __set_FAULTMASK(uint32_t faultMask); - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -extern uint32_t __get_CONTROL(void); - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -extern void __set_CONTROL(uint32_t control); - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -extern uint32_t __REV(uint32_t value); - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -extern uint32_t __REV16(uint16_t value); - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -extern int32_t __REVSH(int16_t value); - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -extern uint32_t __RBIT(uint32_t value); - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -extern uint8_t __LDREXB(uint8_t *addr); - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -extern uint16_t __LDREXH(uint16_t *addr); - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -extern uint32_t __LDREXW(uint32_t *addr); - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -extern uint32_t __STREXB(uint8_t value, uint8_t *addr); - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -extern uint32_t __STREXH(uint16_t value, uint16_t *addr); - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -extern uint32_t __STREXW(uint32_t value, uint32_t *addr); - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - - -/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface - Core Function Interface containing: - - Core NVIC Functions - - Core SysTick Functions - - Core Reset Functions -*/ -/*@{*/ - -/* ########################## NVIC functions #################################### */ - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param PriorityGroup is priority grouping field - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - (0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Get the Priority Grouping from NVIC Interrupt Controller - * - * @return priority grouping field - * - * Get the priority grouping from NVIC Interrupt Controller. - * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn The positive number of the external interrupt to enable - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn The positive number of the external interrupt to disable - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn The number of the device specifc interrupt - * @return 1 = interrupt pending, 0 = interrupt not pending - * - * Read the pending register in NVIC and return 1 if its status is pending, - * otherwise it returns 0 - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for set pending - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for clear pending - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn The number of the interrupt for read active bit - * @return 1 = interrupt active, 0 = interrupt not active - * - * Read the active register in NVIC and returns 1 if its status is active, - * otherwise it returns 0. - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn The number of the interrupt for set priority - * @param priority The priority to set - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn The number of the interrupt for get priority - * @return The priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** - * @brief Encode the priority for an interrupt - * - * @param PriorityGroup The used priority group - * @param PreemptPriority The preemptive priority value (starting from 0) - * @param SubPriority The sub priority value (starting from 0) - * @return The encoded priority for the interrupt - * - * Encode the priority for an interrupt with the given priority group, - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The returned priority value can be used for NVIC_SetPriority(...) function - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** - * @brief Decode the priority of an interrupt - * - * @param Priority The priority for the interrupt - * @param PriorityGroup The used priority group - * @param pPreemptPriority The preemptive priority value (starting from 0) - * @param pSubPriority The sub priority value (starting from 0) - * - * Decode an interrupt priority value with the given priority group to - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The priority value can be retrieved with NVIC_GetPriority(...) function - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param ticks number of ticks between two interrupts - * @return 1 = failed, 0 = successful - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - - - - -/* ################################## Reset function ############################################ */ - -/** - * @brief Initiate a system reset request. - * - * Initiate a system reset request to reset the MCU - */ -static __INLINE void NVIC_SystemReset(void) -{ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ - - - -/* ##################################### Debug In/Output function ########################################### */ - -/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface - Core Debug Interface containing: - - Core Debug Receive / Transmit Functions - - Core Debug Defines - - Core Debug Variables -*/ -/*@{*/ - -extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** - * @brief Outputs a character via the ITM channel 0 - * - * @param ch character to output - * @return character to output - * - * The function outputs a character via the ITM channel 0. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** - * @brief Inputs a character via variable ITM_RxBuffer - * - * @return received character, -1 = no character received - * - * The function inputs a character via variable ITM_RxBuffer. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE int ITM_ReceiveChar (void) { - int ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - * @brief Check if a character via variable ITM_RxBuffer is available - * - * @return 1 = character available, 0 = no character available - * - * The function checks variable ITM_RxBuffer whether a character is available or not. - * The function returns '1' if a character is available and '0' if no character is available. - */ -static __INLINE int ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_definitions */ - -#endif /* __CM3_CORE_H__ */ - -/*lint -restore */ diff --git a/example/libs_stm/inc/device_support/stm32f10x.h b/example/libs_stm/inc/device_support/stm32f10x.h deleted file mode 100644 index 9d124002e..000000000 --- a/example/libs_stm/inc/device_support/stm32f10x.h +++ /dev/null @@ -1,8227 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F10x Connectivity line, High - * density, Medium density, Medium density Value line, Low density - * and Low density Value line and XL-density devices. - ****************************************************************************** - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x - * @{ - */ - -#ifndef __STM32F10x_H -#define __STM32F10x_H - -#ifdef __cplusplus - extern "C" { -#endif - -#define assert_param(__p) - - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) - /* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */ - /* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */ - /* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */ - /* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */ - /* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */ - #define STM32F10X_XL /*!< STM32F10X_XL: STM32 XL-density devices */ - /* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */ -#endif -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - - - Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 16 and 32 Kbytes. - - Low-density value line devices are STM32F100xx microcontrollers where the Flash - memory density ranges between 16 and 32 Kbytes. - - Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers - where the Flash memory density ranges between 64 and 128 Kbytes. - - Medium-density value line devices are STM32F100xx microcontrollers where the - Flash memory density ranges between 64 and 128 Kbytes. - - High density devices are STM32F101xx and STM32F103xx microcontrollers where - the Flash memory density ranges between 256 and 512 Kbytes. - - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where - the Flash memory density ranges between 512 and 1024 Kbytes. - - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. - */ - -#if !defined USE_STDPERIPH_DRIVER -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined HSE_VALUE - #ifdef STM32F10X_CL - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ - #else - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ - #endif /* STM32F10X_CL */ -#endif /* HSE_VALUE */ - - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ - -#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ - -/** - * @brief STM32F10x Standard Peripheral Library version number - */ -#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x03) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */ -#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */ -#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\ - | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\ - | __STM32F10X_STDPERIPH_VERSION_SUB2) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#ifdef STM32F10X_XL - #define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */ -#else - #define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */ -#endif /* STM32F10X_XL */ -#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @brief STM32F10x Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_IRQn = 2, /*!< Tamper Interrupt */ - RTC_IRQn = 3, /*!< RTC global Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - -#ifdef STM32F10X_LD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_LD */ - -#ifdef STM32F10X_LD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55 /*!< TIM7 Interrupt */ -#endif /* STM32F10X_LD_VL */ - -#ifdef STM32F10X_MD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ -#endif /* STM32F10X_MD */ - -#ifdef STM32F10X_MD_VL - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */ - TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */ - TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */ - TIM7_IRQn = 55 /*!< TIM7 Interrupt */ -#endif /* STM32F10X_MD_VL */ - -#ifdef STM32F10X_HD - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ - TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */ - TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* STM32F10X_HD */ - -#ifdef STM32F10X_XL - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - ADC3_IRQn = 47, /*!< ADC3 global Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */ -#endif /* STM32F10X_XL */ - -#ifdef STM32F10X_CL - ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ - CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */ - CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ - DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ -#endif /* STM32F10X_CL */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32f10x.h" -#include - -/** @addtogroup Exported_types - * @{ - */ - -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -#ifndef __cplusplus -typedef enum {FALSE = 0, TRUE = !FALSE} bool; -#endif - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */ -#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT -#define HSE_Value HSE_VALUE -#define HSI_Value HSI_VALUE -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SMPR1; - __IO uint32_t SMPR2; - __IO uint32_t JOFR1; - __IO uint32_t JOFR2; - __IO uint32_t JOFR3; - __IO uint32_t JOFR4; - __IO uint32_t HTR; - __IO uint32_t LTR; - __IO uint32_t SQR1; - __IO uint32_t SQR2; - __IO uint32_t SQR3; - __IO uint32_t JSQR; - __IO uint32_t JDR1; - __IO uint32_t JDR2; - __IO uint32_t JDR3; - __IO uint32_t JDR4; - __IO uint32_t DR; -} ADC_TypeDef; - -/** - * @brief Backup Registers - */ - -typedef struct -{ - uint32_t RESERVED0; - __IO uint16_t DR1; - uint16_t RESERVED1; - __IO uint16_t DR2; - uint16_t RESERVED2; - __IO uint16_t DR3; - uint16_t RESERVED3; - __IO uint16_t DR4; - uint16_t RESERVED4; - __IO uint16_t DR5; - uint16_t RESERVED5; - __IO uint16_t DR6; - uint16_t RESERVED6; - __IO uint16_t DR7; - uint16_t RESERVED7; - __IO uint16_t DR8; - uint16_t RESERVED8; - __IO uint16_t DR9; - uint16_t RESERVED9; - __IO uint16_t DR10; - uint16_t RESERVED10; - __IO uint16_t RTCCR; - uint16_t RESERVED11; - __IO uint16_t CR; - uint16_t RESERVED12; - __IO uint16_t CSR; - uint16_t RESERVED13[5]; - __IO uint16_t DR11; - uint16_t RESERVED14; - __IO uint16_t DR12; - uint16_t RESERVED15; - __IO uint16_t DR13; - uint16_t RESERVED16; - __IO uint16_t DR14; - uint16_t RESERVED17; - __IO uint16_t DR15; - uint16_t RESERVED18; - __IO uint16_t DR16; - uint16_t RESERVED19; - __IO uint16_t DR17; - uint16_t RESERVED20; - __IO uint16_t DR18; - uint16_t RESERVED21; - __IO uint16_t DR19; - uint16_t RESERVED22; - __IO uint16_t DR20; - uint16_t RESERVED23; - __IO uint16_t DR21; - uint16_t RESERVED24; - __IO uint16_t DR22; - uint16_t RESERVED25; - __IO uint16_t DR23; - uint16_t RESERVED26; - __IO uint16_t DR24; - uint16_t RESERVED27; - __IO uint16_t DR25; - uint16_t RESERVED28; - __IO uint16_t DR26; - uint16_t RESERVED29; - __IO uint16_t DR27; - uint16_t RESERVED30; - __IO uint16_t DR28; - uint16_t RESERVED31; - __IO uint16_t DR29; - uint16_t RESERVED32; - __IO uint16_t DR30; - uint16_t RESERVED33; - __IO uint16_t DR31; - uint16_t RESERVED34; - __IO uint16_t DR32; - uint16_t RESERVED35; - __IO uint16_t DR33; - uint16_t RESERVED36; - __IO uint16_t DR34; - uint16_t RESERVED37; - __IO uint16_t DR35; - uint16_t RESERVED38; - __IO uint16_t DR36; - uint16_t RESERVED39; - __IO uint16_t DR37; - uint16_t RESERVED40; - __IO uint16_t DR38; - uint16_t RESERVED41; - __IO uint16_t DR39; - uint16_t RESERVED42; - __IO uint16_t DR40; - uint16_t RESERVED43; - __IO uint16_t DR41; - uint16_t RESERVED44; - __IO uint16_t DR42; - uint16_t RESERVED45; -} BKP_TypeDef; - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; - __IO uint32_t TDTR; - __IO uint32_t TDLR; - __IO uint32_t TDHR; -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; - __IO uint32_t RDTR; - __IO uint32_t RDLR; - __IO uint32_t RDHR; -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; - __IO uint32_t FR2; -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; - __IO uint32_t MSR; - __IO uint32_t TSR; - __IO uint32_t RF0R; - __IO uint32_t RF1R; - __IO uint32_t IER; - __IO uint32_t ESR; - __IO uint32_t BTR; - uint32_t RESERVED0[88]; - CAN_TxMailBox_TypeDef sTxMailBox[3]; - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; - uint32_t RESERVED1[12]; - __IO uint32_t FMR; - __IO uint32_t FM1R; - uint32_t RESERVED2; - __IO uint32_t FS1R; - uint32_t RESERVED3; - __IO uint32_t FFA1R; - uint32_t RESERVED4; - __IO uint32_t FA1R; - uint32_t RESERVED5[8]; -#ifndef STM32F10X_CL - CAN_FilterRegister_TypeDef sFilterRegister[14]; -#else - CAN_FilterRegister_TypeDef sFilterRegister[28]; -#endif /* STM32F10X_CL */ -} CAN_TypeDef; - -/** - * @brief Consumer Electronics Control (CEC) - */ -typedef struct -{ - __IO uint32_t CFGR; - __IO uint32_t OAR; - __IO uint32_t PRES; - __IO uint32_t ESR; - __IO uint32_t CSR; - __IO uint32_t TXD; - __IO uint32_t RXD; -} CEC_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; - __IO uint8_t IDR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CR; -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t SWTRIGR; - __IO uint32_t DHR12R1; - __IO uint32_t DHR12L1; - __IO uint32_t DHR8R1; - __IO uint32_t DHR12R2; - __IO uint32_t DHR12L2; - __IO uint32_t DHR8R2; - __IO uint32_t DHR12RD; - __IO uint32_t DHR12LD; - __IO uint32_t DHR8RD; - __IO uint32_t DOR1; - __IO uint32_t DOR2; -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) - __IO uint32_t SR; -#endif -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; - __IO uint32_t CR; -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; - __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; - __IO uint32_t IFCR; -} DMA_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - uint32_t RESERVED8[567]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - uint32_t RESERVED9[9]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; - __IO uint32_t EMR; - __IO uint32_t RTSR; - __IO uint32_t FTSR; - __IO uint32_t SWIER; - __IO uint32_t PR; -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; - __IO uint32_t KEYR; - __IO uint32_t OPTKEYR; - __IO uint32_t SR; - __IO uint32_t CR; - __IO uint32_t AR; - __IO uint32_t RESERVED; - __IO uint32_t OBR; - __IO uint32_t WRPR; -#ifdef STM32F10X_XL - uint32_t RESERVED1[8]; - __IO uint32_t KEYR2; - uint32_t RESERVED2; - __IO uint32_t SR2; - __IO uint32_t CR2; - __IO uint32_t AR2; -#endif /* STM32F10X_XL */ -} FLASH_TypeDef; - -/** - * @brief Option Bytes Registers - */ - -typedef struct -{ - __IO uint16_t RDP; - __IO uint16_t USER; - __IO uint16_t Data0; - __IO uint16_t Data1; - __IO uint16_t WRP0; - __IO uint16_t WRP1; - __IO uint16_t WRP2; - __IO uint16_t WRP3; -} OB_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; - __IO uint32_t SR2; - __IO uint32_t PMEM2; - __IO uint32_t PATT2; - uint32_t RESERVED0; - __IO uint32_t ECCR2; -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; - __IO uint32_t SR3; - __IO uint32_t PMEM3; - __IO uint32_t PATT3; - uint32_t RESERVED0; - __IO uint32_t ECCR3; -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; - __IO uint32_t SR4; - __IO uint32_t PMEM4; - __IO uint32_t PATT4; - __IO uint32_t PIO4; -} FSMC_Bank4_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t CRL; - __IO uint32_t CRH; - __IO uint32_t IDR; - __IO uint32_t ODR; - __IO uint32_t BSRR; - __IO uint32_t BRR; - __IO uint32_t LCKR; -} GPIO_TypeDef; - -/** - * @brief Alternate Function I/O - */ - -typedef struct -{ - __IO uint32_t EVCR; - __IO uint32_t MAPR; - __IO uint32_t EXTICR[4]; - uint32_t RESERVED0; - __IO uint32_t MAPR2; -} AFIO_TypeDef; -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t OAR1; - uint16_t RESERVED2; - __IO uint16_t OAR2; - uint16_t RESERVED3; - __IO uint16_t DR; - uint16_t RESERVED4; - __IO uint16_t SR1; - uint16_t RESERVED5; - __IO uint16_t SR2; - uint16_t RESERVED6; - __IO uint16_t CCR; - uint16_t RESERVED7; - __IO uint16_t TRISE; - uint16_t RESERVED8; -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; - __IO uint32_t PR; - __IO uint32_t RLR; - __IO uint32_t SR; -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFGR; - __IO uint32_t CIR; - __IO uint32_t APB2RSTR; - __IO uint32_t APB1RSTR; - __IO uint32_t AHBENR; - __IO uint32_t APB2ENR; - __IO uint32_t APB1ENR; - __IO uint32_t BDCR; - __IO uint32_t CSR; - -#ifdef STM32F10X_CL - __IO uint32_t AHBRSTR; - __IO uint32_t CFGR2; -#endif /* STM32F10X_CL */ - -#if defined STM32F10X_LD_VL || defined STM32F10X_MD_VL - uint32_t RESERVED0; - __IO uint32_t CFGR2; -#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint16_t CRH; - uint16_t RESERVED0; - __IO uint16_t CRL; - uint16_t RESERVED1; - __IO uint16_t PRLH; - uint16_t RESERVED2; - __IO uint16_t PRLL; - uint16_t RESERVED3; - __IO uint16_t DIVH; - uint16_t RESERVED4; - __IO uint16_t DIVL; - uint16_t RESERVED5; - __IO uint16_t CNTH; - uint16_t RESERVED6; - __IO uint16_t CNTL; - uint16_t RESERVED7; - __IO uint16_t ALRH; - uint16_t RESERVED8; - __IO uint16_t ALRL; - uint16_t RESERVED9; -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; - __IO uint32_t CLKCR; - __IO uint32_t ARG; - __IO uint32_t CMD; - __I uint32_t RESPCMD; - __I uint32_t RESP1; - __I uint32_t RESP2; - __I uint32_t RESP3; - __I uint32_t RESP4; - __IO uint32_t DTIMER; - __IO uint32_t DLEN; - __IO uint32_t DCTRL; - __I uint32_t DCOUNT; - __I uint32_t STA; - __IO uint32_t ICR; - __IO uint32_t MASK; - uint32_t RESERVED0[2]; - __I uint32_t FIFOCNT; - uint32_t RESERVED1[13]; - __IO uint32_t FIFO; -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SR; - uint16_t RESERVED2; - __IO uint16_t DR; - uint16_t RESERVED3; - __IO uint16_t CRCPR; - uint16_t RESERVED4; - __IO uint16_t RXCRCR; - uint16_t RESERVED5; - __IO uint16_t TXCRCR; - uint16_t RESERVED6; - __IO uint16_t I2SCFGR; - uint16_t RESERVED7; - __IO uint16_t I2SPR; - uint16_t RESERVED8; -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SMCR; - uint16_t RESERVED2; - __IO uint16_t DIER; - uint16_t RESERVED3; - __IO uint16_t SR; - uint16_t RESERVED4; - __IO uint16_t EGR; - uint16_t RESERVED5; - __IO uint16_t CCMR1; - uint16_t RESERVED6; - __IO uint16_t CCMR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ARR; - uint16_t RESERVED11; - __IO uint16_t RCR; - uint16_t RESERVED12; - __IO uint16_t CCR1; - uint16_t RESERVED13; - __IO uint16_t CCR2; - uint16_t RESERVED14; - __IO uint16_t CCR3; - uint16_t RESERVED15; - __IO uint16_t CCR4; - uint16_t RESERVED16; - __IO uint16_t BDTR; - uint16_t RESERVED17; - __IO uint16_t DCR; - uint16_t RESERVED18; - __IO uint16_t DMAR; - uint16_t RESERVED19; -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; - uint16_t RESERVED0; - __IO uint16_t DR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CR1; - uint16_t RESERVED3; - __IO uint16_t CR2; - uint16_t RESERVED4; - __IO uint16_t CR3; - uint16_t RESERVED5; - __IO uint16_t GTPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFR; - __IO uint32_t SR; -} WWDG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */ -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */ - -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the bit-band region */ - -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define CEC_BASE (APB1PERIPH_BASE + 0x7800) - -#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) -#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) -#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) -#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) -#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) -#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) -#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) -#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) -#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) -#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) -#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) - -#define SDIO_BASE (PERIPH_BASE + 0x18000) - -#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) -#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) -#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) -#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) -#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) -#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) -#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) -#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) -#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) -#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) -#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) -#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) -#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) -#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) -#define RCC_BASE (AHBPERIPH_BASE + 0x1000) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /*!< Flash registers base address */ -#define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */ - -#define ETH_BASE (AHBPERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */ -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */ -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /*!< FSMC Bank2 registers base address */ -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /*!< FSMC Bank3 registers base address */ -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /*!< FSMC Bank4 registers base address */ - -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define BKP ((BKP_TypeDef *) BKP_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define CEC ((CEC_TypeDef *) CEC_BASE) -#define AFIO ((AFIO_TypeDef *) AFIO_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define TIM15 ((TIM_TypeDef *) TIM15_BASE) -#define TIM16 ((TIM_TypeDef *) TIM16_BASE) -#define TIM17 ((TIM_TypeDef *) TIM17_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* CRC calculation unit */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ - - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ - - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Power Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for PWR_CR register ********************/ -#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-Power Deepsleep */ -#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */ -#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */ -#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */ -#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */ - -#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */ -#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */ -#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */ -#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */ - -/*!< PVD level configuration */ -#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /*!< PVD level 2.2V */ -#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /*!< PVD level 2.3V */ -#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /*!< PVD level 2.4V */ -#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /*!< PVD level 2.5V */ -#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /*!< PVD level 2.6V */ -#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /*!< PVD level 2.7V */ -#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /*!< PVD level 2.8V */ -#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /*!< PVD level 2.9V */ - -#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */ - - -/******************* Bit definition for PWR_CSR register ********************/ -#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */ -#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */ -#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */ -#define PWR_CSR_EWUP ((uint16_t)0x0100) /*!< Enable WKUP pin */ - -/******************************************************************************/ -/* */ -/* Backup registers */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for BKP_DR1 register ********************/ -#define BKP_DR1_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR2 register ********************/ -#define BKP_DR2_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR3 register ********************/ -#define BKP_DR3_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR4 register ********************/ -#define BKP_DR4_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR5 register ********************/ -#define BKP_DR5_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR6 register ********************/ -#define BKP_DR6_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR7 register ********************/ -#define BKP_DR7_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR8 register ********************/ -#define BKP_DR8_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR9 register ********************/ -#define BKP_DR9_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR10 register *******************/ -#define BKP_DR10_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR11 register *******************/ -#define BKP_DR11_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR12 register *******************/ -#define BKP_DR12_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR13 register *******************/ -#define BKP_DR13_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR14 register *******************/ -#define BKP_DR14_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR15 register *******************/ -#define BKP_DR15_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR16 register *******************/ -#define BKP_DR16_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR17 register *******************/ -#define BKP_DR17_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_DR18 register ********************/ -#define BKP_DR18_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR19 register *******************/ -#define BKP_DR19_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR20 register *******************/ -#define BKP_DR20_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR21 register *******************/ -#define BKP_DR21_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR22 register *******************/ -#define BKP_DR22_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR23 register *******************/ -#define BKP_DR23_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR24 register *******************/ -#define BKP_DR24_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR25 register *******************/ -#define BKP_DR25_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR26 register *******************/ -#define BKP_DR26_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR27 register *******************/ -#define BKP_DR27_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR28 register *******************/ -#define BKP_DR28_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR29 register *******************/ -#define BKP_DR29_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR30 register *******************/ -#define BKP_DR30_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR31 register *******************/ -#define BKP_DR31_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR32 register *******************/ -#define BKP_DR32_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR33 register *******************/ -#define BKP_DR33_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR34 register *******************/ -#define BKP_DR34_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR35 register *******************/ -#define BKP_DR35_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR36 register *******************/ -#define BKP_DR36_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR37 register *******************/ -#define BKP_DR37_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR38 register *******************/ -#define BKP_DR38_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR39 register *******************/ -#define BKP_DR39_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR40 register *******************/ -#define BKP_DR40_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR41 register *******************/ -#define BKP_DR41_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/******************* Bit definition for BKP_DR42 register *******************/ -#define BKP_DR42_D ((uint16_t)0xFFFF) /*!< Backup data */ - -/****************** Bit definition for BKP_RTCCR register *******************/ -#define BKP_RTCCR_CAL ((uint16_t)0x007F) /*!< Calibration value */ -#define BKP_RTCCR_CCO ((uint16_t)0x0080) /*!< Calibration Clock Output */ -#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /*!< Alarm or Second Output Enable */ -#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /*!< Alarm or Second Output Selection */ - -/******************** Bit definition for BKP_CR register ********************/ -#define BKP_CR_TPE ((uint8_t)0x01) /*!< TAMPER pin enable */ -#define BKP_CR_TPAL ((uint8_t)0x02) /*!< TAMPER pin active level */ - -/******************* Bit definition for BKP_CSR register ********************/ -#define BKP_CSR_CTE ((uint16_t)0x0001) /*!< Clear Tamper event */ -#define BKP_CSR_CTI ((uint16_t)0x0002) /*!< Clear Tamper Interrupt */ -#define BKP_CSR_TPIE ((uint16_t)0x0004) /*!< TAMPER Pin interrupt enable */ -#define BKP_CSR_TEF ((uint16_t)0x0100) /*!< Tamper Event Flag */ -#define BKP_CSR_TIF ((uint16_t)0x0200) /*!< Tamper Interrupt Flag */ - -/******************************************************************************/ -/* */ -/* Reset and Clock Control */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for RCC_CR register ********************/ -#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */ -#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */ -#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */ -#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */ -#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */ -#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */ -#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */ -#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */ -#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */ -#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */ - -#ifdef STM32F10X_CL - #define RCC_CR_PLL2ON ((uint32_t)0x04000000) /*!< PLL2 enable */ - #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /*!< PLL2 clock ready flag */ - #define RCC_CR_PLL3ON ((uint32_t)0x10000000) /*!< PLL3 enable */ - #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /*!< PLL3 clock ready flag */ -#endif /* STM32F10X_CL */ - -/******************* Bit definition for RCC_CFGR register *******************/ -/*!< SW configuration */ -#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */ -#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */ - -/*!< SWS configuration */ -#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */ -#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */ - -/*!< HPRE configuration */ -#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */ -#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */ -#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - -#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */ -#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */ -#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */ -#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */ -#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */ -#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */ -#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */ -#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */ -#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */ - -/*!< PPRE1 configuration */ -#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */ -#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */ - -/*!< PPRE2 configuration */ -#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */ -#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */ -#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */ -#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */ - -#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */ -#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */ -#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */ -#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */ -#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */ - -/*!< ADCPPRE configuration */ -#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /*!< ADCPRE[1:0] bits (ADC prescaler) */ -#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK2 divided by 2 */ -#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK2 divided by 4 */ -#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /*!< PCLK2 divided by 6 */ -#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /*!< PCLK2 divided by 8 */ - -#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */ - -#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */ - -/*!< PLLMUL configuration */ -#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ -#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ -#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */ - -#ifdef STM32F10X_CL - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock * 4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock * 5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock * 6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock * 7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock * 8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock * 9 */ - #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /*!< PLL input clock * 6.5 */ - - #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /*!< USB OTG FS prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ - #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /*!< PLL2 clock selected as MCO source*/ - #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/ - #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */ -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ - #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ - #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ - #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ - #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ - #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ - #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ - #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ - #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ -#else - #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */ - #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */ - - #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /*!< HSE clock not divided for PLL entry */ - #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /*!< HSE clock divided by 2 for PLL entry */ - - #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */ - #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */ - #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */ - #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */ - #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */ - #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */ - #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */ - #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */ - #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */ - #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */ - #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */ - #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */ - #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */ - #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */ - #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */ - #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB Device prescaler */ - -/*!< MCO configuration */ - #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */ - #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */ - #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - - #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ - #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */ - #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */ - #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */ - #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */ -#endif /* STM32F10X_CL */ - -/*!<****************** Bit definition for RCC_CIR register ********************/ -#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */ -#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */ -#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */ -#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */ -#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */ -#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */ -#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */ -#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */ -#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */ -#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */ -#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */ -#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */ -#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */ -#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */ -#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */ -#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */ -#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */ - -#ifdef STM32F10X_CL - #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /*!< PLL2 Ready Interrupt flag */ - #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /*!< PLL3 Ready Interrupt flag */ - #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /*!< PLL2 Ready Interrupt Enable */ - #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /*!< PLL3 Ready Interrupt Enable */ - #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /*!< PLL2 Ready Interrupt Clear */ - #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /*!< PLL3 Ready Interrupt Clear */ -#endif /* STM32F10X_CL */ - -/***************** Bit definition for RCC_APB2RSTR register *****************/ -#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */ -#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */ -#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */ -#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */ -#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */ -#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) -#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */ -#endif - -#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */ -#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */ -#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) -#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */ -#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */ -#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */ -#endif - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */ - #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */ - #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */ - #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */ -#endif - -#ifdef STM32F10X_XL - #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */ - #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */ - #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */ -#endif /* STM32F10X_XL */ - -/***************** Bit definition for RCC_APB1RSTR register *****************/ -#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */ -#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */ -#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */ -#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */ -#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) -#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */ -#endif - -#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */ -#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */ - #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */ - #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */ - #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) - #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) - #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */ - #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ - #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ - #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */ - #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */ - #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */ - #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ -#endif - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) - #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */ - #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */ - #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */ - #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */ -#endif - -#ifdef STM32F10X_CL - #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */ -#endif /* STM32F10X_CL */ - -#ifdef STM32F10X_XL - #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */ - #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */ - #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */ -#endif /* STM32F10X_XL */ - -/****************** Bit definition for RCC_AHBENR register ******************/ -#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */ -#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */ -#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /*!< FLITF clock enable */ -#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /*!< CRC clock enable */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) - #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */ - #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */ -#endif - -#ifdef STM32F10X_CL - #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */ - #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /*!< ETHERNET MAC clock enable */ - #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /*!< ETHERNET MAC Tx clock enable */ - #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /*!< ETHERNET MAC Rx clock enable */ -#endif /* STM32F10X_CL */ - -/****************** Bit definition for RCC_APB2ENR register *****************/ -#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */ -#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */ -#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */ -#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */ -#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */ -#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) -#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */ -#endif - -#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */ -#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */ -#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) -#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */ -#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */ -#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */ -#endif - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_XL) - #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */ - #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */ - #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */ - #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */ -#endif - -#ifdef STM32F10X_XL - #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */ - #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */ - #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */ -#endif - -/***************** Bit definition for RCC_APB1ENR register ******************/ -#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/ -#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */ -#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */ -#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */ -#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */ - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) -#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */ -#endif - -#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */ -#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */ - -#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) - #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */ - #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */ - #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */ - #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */ -#endif /* STM32F10X_LD && STM32F10X_LD_VL */ - -#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) - #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */ -#endif - -#if defined (STM32F10X_HD) || defined (STM32F10X_CL) - #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */ - #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ - #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ - #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */ - #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */ - #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */ - #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ -#endif - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) - #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */ - #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */ - #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */ - #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */ -#endif - -#ifdef STM32F10X_CL - #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */ -#endif /* STM32F10X_CL */ - -#ifdef STM32F10X_XL - #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */ - #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */ - #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */ -#endif /* STM32F10X_XL */ - -/******************* Bit definition for RCC_BDCR register *******************/ -#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */ -#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */ -#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */ - -#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */ -#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< RTC congiguration */ -#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */ -#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */ -#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */ - -#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */ -#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */ - -/******************* Bit definition for RCC_CSR register ********************/ -#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */ -#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */ -#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */ -#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */ -#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */ -#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */ -#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */ -#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */ -#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */ - -#ifdef STM32F10X_CL -/******************* Bit definition for RCC_AHBRSTR register ****************/ - #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /*!< USB OTG FS reset */ - #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /*!< ETHERNET MAC reset */ - -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ - #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ - #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ - #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ - -/*!< PREDIV2 configuration */ - #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /*!< PREDIV2[3:0] bits */ - #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /*!< PREDIV2 input clock not divided */ - #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /*!< PREDIV2 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /*!< PREDIV2 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /*!< PREDIV2 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /*!< PREDIV2 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /*!< PREDIV2 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /*!< PREDIV2 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /*!< PREDIV2 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /*!< PREDIV2 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /*!< PREDIV2 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /*!< PREDIV2 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /*!< PREDIV2 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /*!< PREDIV2 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /*!< PREDIV2 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /*!< PREDIV2 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /*!< PREDIV2 input clock divided by 16 */ - -/*!< PLL2MUL configuration */ - #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /*!< PLL2MUL[3:0] bits */ - #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /*!< Bit 0 */ - #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /*!< PLL2 input clock * 8 */ - #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /*!< PLL2 input clock * 9 */ - #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /*!< PLL2 input clock * 10 */ - #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /*!< PLL2 input clock * 11 */ - #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /*!< PLL2 input clock * 12 */ - #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /*!< PLL2 input clock * 13 */ - #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /*!< PLL2 input clock * 14 */ - #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /*!< PLL2 input clock * 16 */ - #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /*!< PLL2 input clock * 20 */ - -/*!< PLL3MUL configuration */ - #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /*!< PLL3MUL[3:0] bits */ - #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /*!< Bit 0 */ - #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /*!< Bit 3 */ - - #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /*!< PLL3 input clock * 8 */ - #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /*!< PLL3 input clock * 9 */ - #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /*!< PLL3 input clock * 10 */ - #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /*!< PLL3 input clock * 11 */ - #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /*!< PLL3 input clock * 12 */ - #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /*!< PLL3 input clock * 13 */ - #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /*!< PLL3 input clock * 14 */ - #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /*!< PLL3 input clock * 16 */ - #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /*!< PLL3 input clock * 20 */ - - #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /*!< PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /*!< PLL2 selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /*!< HSE selected as PREDIV1 entry clock source */ - #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /*!< I2S2 entry clock source */ - #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */ -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) -/******************* Bit definition for RCC_CFGR2 register ******************/ -/*!< PREDIV1 configuration */ - #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */ - #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ - #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ - - #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */ - #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */ - #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */ - #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */ - #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */ - #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */ - #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */ - #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */ - #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */ - #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */ - #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */ - #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */ - #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */ - #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */ - #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */ - #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */ -#endif - -/******************************************************************************/ -/* */ -/* General Purpose and Alternate Function I/O */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for GPIO_CRL register *******************/ -#define GPIO_CRL_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ -#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ -#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ -#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ -#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ -#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ -#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ -#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ -#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ -#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ -#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ -#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ -#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ -#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ -#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ -#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ -#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/******************* Bit definition for GPIO_CRH register *******************/ -#define GPIO_CRH_MODE ((uint32_t)0x33333333) /*!< Port x mode bits */ - -#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ -#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /*!< Bit 1 */ - -#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ -#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ -#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ -#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ -#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ -#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ -#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ -#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /*!< Port x configuration bits */ - -#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ -#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /*!< Bit 0 */ -#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /*!< Bit 1 */ - -#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ -#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ -#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ -#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /*!< Bit 0 */ -#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ -#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ -#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /*!< Bit 0 */ -#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ -#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /*!< Bit 1 */ - -#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ -#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /*!< Bit 0 */ -#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /*!< Bit 1 */ - -/*!<****************** Bit definition for GPIO_IDR register *******************/ -#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /*!< Port input data, bit 0 */ -#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /*!< Port input data, bit 1 */ -#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /*!< Port input data, bit 2 */ -#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /*!< Port input data, bit 3 */ -#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /*!< Port input data, bit 4 */ -#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /*!< Port input data, bit 5 */ -#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /*!< Port input data, bit 6 */ -#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /*!< Port input data, bit 7 */ -#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /*!< Port input data, bit 8 */ -#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /*!< Port input data, bit 9 */ -#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /*!< Port input data, bit 10 */ -#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /*!< Port input data, bit 11 */ -#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /*!< Port input data, bit 12 */ -#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /*!< Port input data, bit 13 */ -#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /*!< Port input data, bit 14 */ -#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /*!< Port input data, bit 15 */ - -/******************* Bit definition for GPIO_ODR register *******************/ -#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /*!< Port output data, bit 0 */ -#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /*!< Port output data, bit 1 */ -#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /*!< Port output data, bit 2 */ -#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /*!< Port output data, bit 3 */ -#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /*!< Port output data, bit 4 */ -#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /*!< Port output data, bit 5 */ -#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /*!< Port output data, bit 6 */ -#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /*!< Port output data, bit 7 */ -#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /*!< Port output data, bit 8 */ -#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /*!< Port output data, bit 9 */ -#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /*!< Port output data, bit 10 */ -#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /*!< Port output data, bit 11 */ -#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /*!< Port output data, bit 12 */ -#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /*!< Port output data, bit 13 */ -#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /*!< Port output data, bit 14 */ -#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /*!< Port output data, bit 15 */ - -/****************** Bit definition for GPIO_BSRR register *******************/ -#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /*!< Port x Set bit 0 */ -#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /*!< Port x Set bit 1 */ -#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /*!< Port x Set bit 2 */ -#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /*!< Port x Set bit 3 */ -#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /*!< Port x Set bit 4 */ -#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /*!< Port x Set bit 5 */ -#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /*!< Port x Set bit 6 */ -#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /*!< Port x Set bit 7 */ -#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /*!< Port x Set bit 8 */ -#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /*!< Port x Set bit 9 */ -#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /*!< Port x Set bit 10 */ -#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /*!< Port x Set bit 11 */ -#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /*!< Port x Set bit 12 */ -#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /*!< Port x Set bit 13 */ -#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /*!< Port x Set bit 14 */ -#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /*!< Port x Set bit 15 */ - -#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /*!< Port x Reset bit 0 */ -#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /*!< Port x Reset bit 1 */ -#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /*!< Port x Reset bit 2 */ -#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /*!< Port x Reset bit 3 */ -#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /*!< Port x Reset bit 4 */ -#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /*!< Port x Reset bit 5 */ -#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /*!< Port x Reset bit 6 */ -#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /*!< Port x Reset bit 7 */ -#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /*!< Port x Reset bit 8 */ -#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /*!< Port x Reset bit 9 */ -#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /*!< Port x Reset bit 10 */ -#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /*!< Port x Reset bit 11 */ -#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /*!< Port x Reset bit 12 */ -#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /*!< Port x Reset bit 13 */ -#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /*!< Port x Reset bit 14 */ -#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /*!< Port x Reset bit 15 */ - -/******************* Bit definition for GPIO_BRR register *******************/ -#define GPIO_BRR_BR0 ((uint16_t)0x0001) /*!< Port x Reset bit 0 */ -#define GPIO_BRR_BR1 ((uint16_t)0x0002) /*!< Port x Reset bit 1 */ -#define GPIO_BRR_BR2 ((uint16_t)0x0004) /*!< Port x Reset bit 2 */ -#define GPIO_BRR_BR3 ((uint16_t)0x0008) /*!< Port x Reset bit 3 */ -#define GPIO_BRR_BR4 ((uint16_t)0x0010) /*!< Port x Reset bit 4 */ -#define GPIO_BRR_BR5 ((uint16_t)0x0020) /*!< Port x Reset bit 5 */ -#define GPIO_BRR_BR6 ((uint16_t)0x0040) /*!< Port x Reset bit 6 */ -#define GPIO_BRR_BR7 ((uint16_t)0x0080) /*!< Port x Reset bit 7 */ -#define GPIO_BRR_BR8 ((uint16_t)0x0100) /*!< Port x Reset bit 8 */ -#define GPIO_BRR_BR9 ((uint16_t)0x0200) /*!< Port x Reset bit 9 */ -#define GPIO_BRR_BR10 ((uint16_t)0x0400) /*!< Port x Reset bit 10 */ -#define GPIO_BRR_BR11 ((uint16_t)0x0800) /*!< Port x Reset bit 11 */ -#define GPIO_BRR_BR12 ((uint16_t)0x1000) /*!< Port x Reset bit 12 */ -#define GPIO_BRR_BR13 ((uint16_t)0x2000) /*!< Port x Reset bit 13 */ -#define GPIO_BRR_BR14 ((uint16_t)0x4000) /*!< Port x Reset bit 14 */ -#define GPIO_BRR_BR15 ((uint16_t)0x8000) /*!< Port x Reset bit 15 */ - -/****************** Bit definition for GPIO_LCKR register *******************/ -#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /*!< Port x Lock bit 0 */ -#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /*!< Port x Lock bit 1 */ -#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /*!< Port x Lock bit 2 */ -#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /*!< Port x Lock bit 3 */ -#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /*!< Port x Lock bit 4 */ -#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /*!< Port x Lock bit 5 */ -#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /*!< Port x Lock bit 6 */ -#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /*!< Port x Lock bit 7 */ -#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /*!< Port x Lock bit 8 */ -#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /*!< Port x Lock bit 9 */ -#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /*!< Port x Lock bit 10 */ -#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /*!< Port x Lock bit 11 */ -#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /*!< Port x Lock bit 12 */ -#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /*!< Port x Lock bit 13 */ -#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /*!< Port x Lock bit 14 */ -#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /*!< Port x Lock bit 15 */ -#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /*!< Lock key */ - -/*----------------------------------------------------------------------------*/ - -/****************** Bit definition for AFIO_EVCR register *******************/ -#define AFIO_EVCR_PIN ((uint8_t)0x0F) /*!< PIN[3:0] bits (Pin selection) */ -#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /*!< Bit 0 */ -#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /*!< Bit 1 */ -#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /*!< Bit 2 */ -#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /*!< Bit 3 */ - -/*!< PIN configuration */ -#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /*!< Pin 0 selected */ -#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /*!< Pin 1 selected */ -#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /*!< Pin 2 selected */ -#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /*!< Pin 3 selected */ -#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /*!< Pin 4 selected */ -#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /*!< Pin 5 selected */ -#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /*!< Pin 6 selected */ -#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /*!< Pin 7 selected */ -#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /*!< Pin 8 selected */ -#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /*!< Pin 9 selected */ -#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /*!< Pin 10 selected */ -#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /*!< Pin 11 selected */ -#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /*!< Pin 12 selected */ -#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /*!< Pin 13 selected */ -#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /*!< Pin 14 selected */ -#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /*!< Pin 15 selected */ - -#define AFIO_EVCR_PORT ((uint8_t)0x70) /*!< PORT[2:0] bits (Port selection) */ -#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /*!< Bit 0 */ -#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /*!< Bit 1 */ -#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /*!< Bit 2 */ - -/*!< PORT configuration */ -#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /*!< Port A selected */ -#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /*!< Port B selected */ -#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /*!< Port C selected */ -#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /*!< Port D selected */ -#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /*!< Port E selected */ - -#define AFIO_EVCR_EVOE ((uint8_t)0x80) /*!< Event Output Enable */ - -/****************** Bit definition for AFIO_MAPR register *******************/ -#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /*!< SPI1 remapping */ -#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /*!< I2C1 remapping */ -#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /*!< USART1 remapping */ -#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /*!< USART2 remapping */ - -#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ -#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /*!< Bit 1 */ - -/* USART3_REMAP configuration */ -#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ -#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ - -#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ -#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /*!< Bit 1 */ - -/*!< TIM1_REMAP configuration */ -#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ -#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ -#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ - -#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ -#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ - -/*!< TIM2_REMAP configuration */ -#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ -#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ -#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ - -#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ -#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /*!< Bit 1 */ - -/*!< TIM3_REMAP configuration */ -#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ -#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ - -#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /*!< TIM4_REMAP bit (TIM4 remapping) */ - -#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ -#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /*!< Bit 1 */ - -/*!< CAN_REMAP configuration */ -#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ -#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ -#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ - -#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ -#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /*!< TIM5 Channel4 Internal Remap */ -#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /*!< ADC 1 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /*!< ADC 1 External Trigger Regular Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /*!< ADC 2 External Trigger Injected Conversion remapping */ -#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /*!< ADC 2 External Trigger Regular Conversion remapping */ - -/*!< SWJ_CFG configuration */ -#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ -#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ -#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ -#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /*!< JTAG-DP Disabled and SW-DP Disabled */ - -#ifdef STM32F10X_CL -/*!< ETH_REMAP configuration */ - #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ - -/*!< CAN2_REMAP configuration */ - #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ - -/*!< MII_RMII_SEL configuration */ - #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ - -/*!< SPI3_REMAP configuration */ - #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /*!< SPI3_REMAP bit (SPI3 remapping) */ - -/*!< TIM2ITR1_IREMAP configuration */ - #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ - -/*!< PTP_PPS_REMAP configuration */ - #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ -#endif - -/***************** Bit definition for AFIO_EXTICR1 register *****************/ -#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */ -#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */ -#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */ -#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */ - -/*!< EXTI0 configuration */ -#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */ -#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */ -#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */ -#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */ -#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */ -#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */ -#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!< PG[0] pin */ - -/*!< EXTI1 configuration */ -#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */ -#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */ -#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */ -#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */ -#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */ -#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */ -#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!< PG[1] pin */ - -/*!< EXTI2 configuration */ -#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */ -#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */ -#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */ -#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */ -#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */ -#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */ -#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!< PG[2] pin */ - -/*!< EXTI3 configuration */ -#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */ -#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */ -#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */ -#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */ -#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */ -#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */ -#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!< PG[3] pin */ - -/***************** Bit definition for AFIO_EXTICR2 register *****************/ -#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */ -#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */ -#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */ -#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */ - -/*!< EXTI4 configuration */ -#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */ -#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */ -#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */ -#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */ -#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */ -#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */ -#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!< PG[4] pin */ - -/* EXTI5 configuration */ -#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */ -#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */ -#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */ -#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */ -#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */ -#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */ -#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!< PG[5] pin */ - -/*!< EXTI6 configuration */ -#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */ -#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */ -#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */ -#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */ -#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */ -#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */ -#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!< PG[6] pin */ - -/*!< EXTI7 configuration */ -#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */ -#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */ -#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */ -#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */ -#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */ -#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */ -#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!< PG[7] pin */ - -/***************** Bit definition for AFIO_EXTICR3 register *****************/ -#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */ -#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */ -#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */ -#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */ - -/*!< EXTI8 configuration */ -#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */ -#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */ -#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */ -#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */ -#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */ -#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */ -#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!< PG[8] pin */ - -/*!< EXTI9 configuration */ -#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */ -#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */ -#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */ -#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */ -#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */ -#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */ -#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!< PG[9] pin */ - -/*!< EXTI10 configuration */ -#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */ -#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */ -#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */ -#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */ -#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */ -#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */ -#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!< PG[10] pin */ - -/*!< EXTI11 configuration */ -#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */ -#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */ -#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */ -#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */ -#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */ -#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */ -#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!< PG[11] pin */ - -/***************** Bit definition for AFIO_EXTICR4 register *****************/ -#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */ -#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */ -#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */ -#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */ - -/* EXTI12 configuration */ -#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */ -#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */ -#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */ -#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */ -#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */ -#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */ -#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!< PG[12] pin */ - -/* EXTI13 configuration */ -#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */ -#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */ -#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */ -#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */ -#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */ -#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */ -#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!< PG[13] pin */ - -/*!< EXTI14 configuration */ -#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */ -#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */ -#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */ -#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */ -#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */ -#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */ -#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!< PG[14] pin */ - -/*!< EXTI15 configuration */ -#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */ -#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */ -#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */ -#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */ -#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */ -#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */ -#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */ -#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */ -#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */ -#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */ -#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */ -#endif - -#ifdef STM32F10X_XL -/****************** Bit definition for AFIO_MAPR2 register ******************/ -#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */ -#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */ -#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */ -#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */ -#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */ -#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */ -#endif - -/******************************************************************************/ -/* */ -/* SystemTick */ -/* */ -/******************************************************************************/ - -/***************** Bit definition for SysTick_CTRL register *****************/ -#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */ -#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */ -#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */ -#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */ - -/***************** Bit definition for SysTick_LOAD register *****************/ -#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */ - -/***************** Bit definition for SysTick_VAL register ******************/ -#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */ - -/***************** Bit definition for SysTick_CALIB register ****************/ -#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */ -#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */ -#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */ - -/******************************************************************************/ -/* */ -/* Nested Vectored Interrupt Controller */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for NVIC_ISER register *******************/ -#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */ -#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICER register *******************/ -#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */ -#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ISPR register *******************/ -#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */ -#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_ICPR register *******************/ -#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */ -#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_IABR register *******************/ -#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */ -#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */ -#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */ -#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */ -#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */ -#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */ -#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */ -#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */ -#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */ -#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */ -#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */ -#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */ -#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */ -#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */ -#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */ -#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */ -#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */ -#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */ -#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */ -#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */ -#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */ -#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */ -#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */ -#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */ -#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */ -#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */ -#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */ -#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */ -#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */ -#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */ -#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */ -#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */ -#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */ - -/****************** Bit definition for NVIC_PRI0 register *******************/ -#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */ -#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */ -#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */ -#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */ - -/****************** Bit definition for NVIC_PRI1 register *******************/ -#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */ -#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */ -#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */ -#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */ - -/****************** Bit definition for NVIC_PRI2 register *******************/ -#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */ -#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */ -#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */ -#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */ - -/****************** Bit definition for NVIC_PRI3 register *******************/ -#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */ -#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */ -#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */ -#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */ - -/****************** Bit definition for NVIC_PRI4 register *******************/ -#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */ -#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */ -#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */ -#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */ - -/****************** Bit definition for NVIC_PRI5 register *******************/ -#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */ -#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */ -#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */ -#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */ - -/****************** Bit definition for NVIC_PRI6 register *******************/ -#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */ -#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */ -#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */ -#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */ - -/****************** Bit definition for NVIC_PRI7 register *******************/ -#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */ -#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */ -#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */ -#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */ - -/****************** Bit definition for SCB_CPUID register *******************/ -#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */ -#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */ -#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */ -#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */ -#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */ - -/******************* Bit definition for SCB_ICSR register *******************/ -#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */ -#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */ -#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */ -#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */ -#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */ -#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */ -#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */ -#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */ -#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */ -#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */ - -/******************* Bit definition for SCB_VTOR register *******************/ -#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */ -#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */ - -/*!<***************** Bit definition for SCB_AIRCR register *******************/ -#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */ -#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */ -#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */ - -#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */ -#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */ -#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */ -#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */ - -/* prority group configuration */ -#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */ -#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */ -#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */ - -#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */ -#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */ - -/******************* Bit definition for SCB_SCR register ********************/ -#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */ -#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */ -#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */ - -/******************** Bit definition for SCB_CCR register *******************/ -#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */ -#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */ -#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */ -#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */ -#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */ -#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ - -/******************* Bit definition for SCB_SHPR register ********************/ -#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ -#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ -#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ -#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ - -/****************** Bit definition for SCB_SHCSR register *******************/ -#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */ -#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */ -#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */ -#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */ -#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */ -#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */ -#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */ -#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */ -#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */ -#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */ -#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */ -#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */ -#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */ -#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */ - -/******************* Bit definition for SCB_CFSR register *******************/ -/*!< MFSR */ -#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */ -#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */ -#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */ -#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */ -#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */ -/*!< BFSR */ -#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */ -#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */ -#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */ -#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */ -#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */ -#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */ -/*!< UFSR */ -#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */ -#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */ -#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */ -#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */ -#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */ -#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */ - -/******************* Bit definition for SCB_HFSR register *******************/ -#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */ -#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */ -#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */ - -/******************* Bit definition for SCB_DFSR register *******************/ -#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */ -#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */ -#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */ -#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */ -#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */ - -/******************* Bit definition for SCB_MMFAR register ******************/ -#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */ - -/******************* Bit definition for SCB_BFAR register *******************/ -#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */ - -/******************* Bit definition for SCB_afsr register *******************/ -#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */ - -/******************************************************************************/ -/* */ -/* External Interrupt/Event Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for EXTI_IMR register *******************/ -#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */ -#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */ -#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */ -#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */ -#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */ -#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */ -#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */ -#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */ -#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */ -#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */ -#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */ -#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */ -#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */ -#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */ -#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */ -#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */ -#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */ -#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */ -#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */ -#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */ - -/******************* Bit definition for EXTI_EMR register *******************/ -#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */ -#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */ -#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */ -#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */ -#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */ -#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */ -#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */ -#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */ -#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */ -#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */ -#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */ -#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */ -#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */ -#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */ -#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */ -#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */ -#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */ -#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */ -#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */ -#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */ - -/****************** Bit definition for EXTI_RTSR register *******************/ -#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */ -#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */ -#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */ -#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */ -#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */ -#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */ -#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */ -#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */ -#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */ -#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */ -#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */ -#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */ -#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */ -#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */ -#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */ -#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */ -#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */ -#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */ -#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */ -#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_FTSR register *******************/ -#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */ -#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */ -#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */ -#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */ -#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */ -#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */ -#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */ -#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */ -#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */ -#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */ -#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */ -#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */ -#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */ -#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */ -#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */ -#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */ -#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */ -#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */ -#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */ -#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */ - -/****************** Bit definition for EXTI_SWIER register ******************/ -#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */ -#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */ -#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */ -#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */ -#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */ -#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */ -#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */ -#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */ -#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */ -#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */ -#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */ -#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */ -#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */ -#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */ -#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */ -#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */ -#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */ -#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */ -#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */ -#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */ - -/******************* Bit definition for EXTI_PR register ********************/ -#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */ -#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */ -#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */ -#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */ -#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */ -#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */ -#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */ -#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */ -#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */ -#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */ -#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */ -#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */ -#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */ -#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */ -#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */ -#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */ -#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */ -#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */ -#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */ -#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */ - -/******************************************************************************/ -/* */ -/* DMA Controller */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for DMA_ISR register ********************/ -#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */ -#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */ -#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */ -#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */ -#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */ -#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */ -#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */ -#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */ -#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */ -#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */ -#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */ -#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */ -#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */ -#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */ -#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */ -#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */ -#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */ -#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */ -#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */ -#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */ -#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */ -#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */ -#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */ -#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */ -#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */ -#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */ -#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */ -#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */ - -/******************* Bit definition for DMA_IFCR register *******************/ -#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */ -#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */ -#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */ -#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */ -#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */ -#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */ -#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */ -#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */ -#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */ -#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */ -#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */ -#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */ -#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */ -#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */ -#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */ -#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */ -#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */ -#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */ -#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */ -#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */ -#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */ -#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */ -#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */ -#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */ -#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */ -#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */ -#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */ -#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */ - -/******************* Bit definition for DMA_CCR1 register *******************/ -#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/ -#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */ -#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR2 register *******************/ -#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */ -#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/******************* Bit definition for DMA_CCR3 register *******************/ -#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */ -#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */ -#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */ -#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */ -#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */ -#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */ -#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */ -#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */ - -#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */ -#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */ -#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */ - -#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */ -#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */ -#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */ - -#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */ -#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */ -#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */ - -#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */ - -/*!<****************** Bit definition for DMA_CCR4 register *******************/ -#define DMA_CCR4_EN ((uint16_t)0x0001) /*!
© COPYRIGHT 2010 STMicroelectronics
- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx - * @{ - */ - -#ifndef __STM32L1XX_H -#define __STM32L1XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -#define assert_param(__p) - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32L device used in your - application - */ - -#if !defined (STM32L1XX_MD) - #define STM32L1XX_MD /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */ -#endif -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - - - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx - microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. - - */ - -#if !defined (STM32L1XX_MD) - #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" -#endif - -#if !defined USE_STDPERIPH_DRIVER -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ - -/** - * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup - Timeout value - */ -#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ - -#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ - -/** - * @brief STM32L1xx Standard Peripheral Library version number - */ -#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32L1XX_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief STM32L1xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -#define __MPU_PRESENT 1 /*!< STM32L provides MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/*!< Interrupt Number Definition */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32L specific Interrupt Numbers ***********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ - USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ - DAC_IRQn = 21, /*!< DAC Interrupt */ - COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - LCD_IRQn = 24, /*!< LCD Interrupt */ - TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ - TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ - TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ - TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 44 /*!< TIM7 global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32l1xx.h" -#include - -/** @addtogroup Exported_types - * @{ - */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source - module. Using the 'Options for File' dialog you can simply change the - 'Code / Const' area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the - 'Options for Target' dialog. -*/ - #define __RAM_FUNC FLASH_Status - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ - #define __RAM_FUNC __ramfunc FLASH_Status - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".data")))". -*/ - #define __RAM_FUNC FLASH_Status __attribute__((section(".data"))) - -#elif defined ( __TASKING__ ) -/* TASKING Compiler - ---------------- - RAM functions are defined using a specific toolchain pragma. This pragma is - defined in the stm32l1xx_flash_ramfunc.c -*/ - #define __RAM_FUNC FLASH_Status - -#endif - -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; - __IO uint32_t CR1; - __IO uint32_t CR2; - __IO uint32_t SMPR1; - __IO uint32_t SMPR2; - __IO uint32_t SMPR3; - __IO uint32_t JOFR1; - __IO uint32_t JOFR2; - __IO uint32_t JOFR3; - __IO uint32_t JOFR4; - __IO uint32_t HTR; - __IO uint32_t LTR; - __IO uint32_t SQR1; - __IO uint32_t SQR2; - __IO uint32_t SQR3; - __IO uint32_t SQR4; - __IO uint32_t SQR5; - __IO uint32_t JSQR; - __IO uint32_t JDR1; - __IO uint32_t JDR2; - __IO uint32_t JDR3; - __IO uint32_t JDR4; - __IO uint32_t DR; -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; - __IO uint32_t CCR; -} ADC_Common_TypeDef; - - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; -} COMP_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; - __IO uint8_t IDR; - uint8_t RESERVED0; - uint16_t RESERVED1; - __IO uint32_t CR; -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t SWTRIGR; - __IO uint32_t DHR12R1; - __IO uint32_t DHR12L1; - __IO uint32_t DHR8R1; - __IO uint32_t DHR12R2; - __IO uint32_t DHR12L2; - __IO uint32_t DHR8R2; - __IO uint32_t DHR12RD; - __IO uint32_t DHR12LD; - __IO uint32_t DHR8RD; - __IO uint32_t DOR1; - __IO uint32_t DOR2; - __IO uint32_t SR; -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; - __IO uint32_t CR; - __IO uint32_t APB1FZ; - __IO uint32_t APB2FZ; -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; - __IO uint32_t CNDTR; - __IO uint32_t CPAR; - __IO uint32_t CMAR; -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; - __IO uint32_t IFCR; -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; - __IO uint32_t EMR; - __IO uint32_t RTSR; - __IO uint32_t FTSR; - __IO uint32_t SWIER; - __IO uint32_t PR; -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; - __IO uint32_t PECR; - __IO uint32_t PDKEYR; - __IO uint32_t PEKEYR; - __IO uint32_t PRGKEYR; - __IO uint32_t OPTKEYR; - __IO uint32_t SR; - __IO uint32_t OBR; - __IO uint32_t WRPR; -} FLASH_TypeDef; - -/** - * @brief Option Bytes Registers - */ - -typedef struct -{ - __IO uint32_t RDP; - __IO uint32_t USER; - __IO uint32_t WRP01; - __IO uint32_t WRP23; -} OB_TypeDef; - -/** - * @brief General Purpose IO - */ - -typedef struct -{ - __IO uint32_t MODER; - __IO uint16_t OTYPER; - uint16_t RESERVED0; - __IO uint32_t OSPEEDR; - __IO uint32_t PUPDR; - __IO uint16_t IDR; - uint16_t RESERVED1; - __IO uint16_t ODR; - uint16_t RESERVED2; - __IO uint16_t BSRRL; /* BSRR register is split to 2 * 16-bit fields BSRRL */ - __IO uint16_t BSRRH; /* BSRR register is split to 2 * 16-bit fields BSRRH */ - __IO uint32_t LCKR; - __IO uint32_t AFR[2]; -} GPIO_TypeDef; - -/** - * @brief SysTem Configuration - */ - -typedef struct -{ - __IO uint32_t MEMRMP; - __IO uint32_t PMC; - __IO uint32_t EXTICR[4]; -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t OAR1; - uint16_t RESERVED2; - __IO uint16_t OAR2; - uint16_t RESERVED3; - __IO uint16_t DR; - uint16_t RESERVED4; - __IO uint16_t SR1; - uint16_t RESERVED5; - __IO uint16_t SR2; - uint16_t RESERVED6; - __IO uint16_t CCR; - uint16_t RESERVED7; - __IO uint16_t TRISE; - uint16_t RESERVED8; -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; - __IO uint32_t PR; - __IO uint32_t RLR; - __IO uint32_t SR; -} IWDG_TypeDef; - - -/** - * @brief LCD - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t FCR; - __IO uint32_t SR; - __IO uint32_t CLR; - uint32_t RESERVED; - __IO uint32_t RAM[16]; -} LCD_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CSR; -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t ICSCR; - __IO uint32_t CFGR; - __IO uint32_t CIR; - __IO uint32_t AHBRSTR; - __IO uint32_t APB2RSTR; - __IO uint32_t APB1RSTR; - __IO uint32_t AHBENR; - __IO uint32_t APB2ENR; - __IO uint32_t APB1ENR; - __IO uint32_t AHBLPENR; - __IO uint32_t APB2LPENR; - __IO uint32_t APB1LPENR; - __IO uint32_t CSR; -} RCC_TypeDef; - -/** - * @brief Routing Interface - */ - -typedef struct -{ - __IO uint32_t ICR; - __IO uint32_t ASCR1; - __IO uint32_t ASCR2; - __IO uint32_t HYSCR1; - __IO uint32_t HYSCR2; - __IO uint32_t HYSCR3; -} RI_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; - __IO uint32_t DR; - __IO uint32_t CR; - __IO uint32_t ISR; - __IO uint32_t PRER; - __IO uint32_t WUTR; - __IO uint32_t CALIBR; - __IO uint32_t ALRMAR; - __IO uint32_t ALRMBR; - __IO uint32_t WPR; - uint32_t RESERVED1; - uint32_t RESERVED2; - __IO uint32_t TSTR; - __IO uint32_t TSDR; - uint32_t RESERVED3; - uint32_t RESERVED4; - __IO uint32_t TAFCR; - uint32_t RESERVED5; - uint32_t RESERVED6; - uint32_t RESERVED7; - __IO uint32_t BKP0R; - __IO uint32_t BKP1R; - __IO uint32_t BKP2R; - __IO uint32_t BKP3R; - __IO uint32_t BKP4R; - __IO uint32_t BKP5R; - __IO uint32_t BKP6R; - __IO uint32_t BKP7R; - __IO uint32_t BKP8R; - __IO uint32_t BKP9R; - __IO uint32_t BKP10R; - __IO uint32_t BKP11R; - __IO uint32_t BKP12R; - __IO uint32_t BKP13R; - __IO uint32_t BKP14R; - __IO uint32_t BKP15R; - __IO uint32_t BKP16R; - __IO uint32_t BKP17R; - __IO uint32_t BKP18R; - __IO uint32_t BKP19R; -} RTC_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SR; - uint16_t RESERVED2; - __IO uint16_t DR; - uint16_t RESERVED3; - __IO uint16_t CRCPR; - uint16_t RESERVED4; - __IO uint16_t RXCRCR; - uint16_t RESERVED5; - __IO uint16_t TXCRCR; - uint16_t RESERVED6; -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; - uint16_t RESERVED0; - __IO uint16_t CR2; - uint16_t RESERVED1; - __IO uint16_t SMCR; - uint16_t RESERVED2; - __IO uint16_t DIER; - uint16_t RESERVED3; - __IO uint16_t SR; - uint16_t RESERVED4; - __IO uint16_t EGR; - uint16_t RESERVED5; - __IO uint16_t CCMR1; - uint16_t RESERVED6; - __IO uint16_t CCMR2; - uint16_t RESERVED7; - __IO uint16_t CCER; - uint16_t RESERVED8; - __IO uint16_t CNT; - uint16_t RESERVED9; - __IO uint16_t PSC; - uint16_t RESERVED10; - __IO uint16_t ARR; - uint16_t RESERVED11; - uint32_t RESERVED12; - __IO uint16_t CCR1; - uint16_t RESERVED13; - __IO uint16_t CCR2; - uint16_t RESERVED14; - __IO uint16_t CCR3; - uint16_t RESERVED15; - __IO uint16_t CCR4; - uint16_t RESERVED16; - uint32_t RESERVED17; - __IO uint16_t DCR; - uint16_t RESERVED18; - __IO uint16_t DMAR; - uint16_t RESERVED19; - __IO uint16_t OR; - uint16_t RESERVED20; -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; - uint16_t RESERVED0; - __IO uint16_t DR; - uint16_t RESERVED1; - __IO uint16_t BRR; - uint16_t RESERVED2; - __IO uint16_t CR1; - uint16_t RESERVED3; - __IO uint16_t CR2; - uint16_t RESERVED4; - __IO uint16_t CR3; - uint16_t RESERVED5; - __IO uint16_t GTPR; - uint16_t RESERVED6; -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; - __IO uint32_t CFR; - __IO uint32_t SR; -} WWDG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) - -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define LCD_BASE (APB1PERIPH_BASE + 0x2400) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define COMP_BASE (APB1PERIPH_BASE + 0x7C00) -#define RI_BASE (APB1PERIPH_BASE + 0x7C04) - -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) -#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) -#define TIM9_BASE (APB2PERIPH_BASE + 0x0800) -#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00) -#define TIM11_BASE (APB2PERIPH_BASE + 0x1000) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) -#define ADC_BASE (APB2PERIPH_BASE + 0x2700) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define USART1_BASE (APB2PERIPH_BASE + 0x3800) - -#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000) -#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400) -#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800) -#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00) -#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000) -#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400) -#define CRC_BASE (AHBPERIPH_BASE + 0x3000) -#define RCC_BASE (AHBPERIPH_BASE + 0x3800) - - -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */ -#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */ - -#define DMA1_BASE (AHBPERIPH_BASE + 0x6000) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080) - - -#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */ - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define LCD ((LCD_TypeDef *) LCD_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define COMP ((COMP_TypeDef *) COMP_BASE) -#define RI ((RI_TypeDef *) RI_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) - -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) - -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) - -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) - -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers Bits Definition */ -/******************************************************************************/ -/******************************************************************************/ -/* */ -/* Analog to Digital Converter (ADC) */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */ -#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */ -#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */ -#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */ -#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */ -#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */ -#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */ -#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */ -#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */ - -/******************* Bit definition for ADC_CR1 register ********************/ -#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ -#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */ -#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */ -#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */ -#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */ -#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */ -#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */ -#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */ -#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */ - -#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */ -#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */ -#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */ -#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */ - -#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */ -#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */ - -#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */ -#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */ - -#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */ -#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */ - -#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */ - -/******************* Bit definition for ADC_CR2 register ********************/ -#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */ -#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */ - -#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */ -#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */ -#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */ -#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */ - -#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */ -#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */ -#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */ -#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */ - -#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */ -#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */ -#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */ - -#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */ -#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */ - -#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */ -#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */ -#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */ - -#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ -#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */ -#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */ - -#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */ - -/****************** Bit definition for ADC_SMPR1 register *******************/ -#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */ -#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */ -#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */ -#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */ -#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */ -#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */ -#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_SMPR2 register *******************/ -#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */ -#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */ -#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */ -#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */ -#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */ -#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */ -#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */ -#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */ -#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */ -#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */ - -/****************** Bit definition for ADC_SMPR3 register *******************/ -#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */ -#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */ -#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */ -#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */ -#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */ -#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */ -#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */ -#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */ -#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */ -#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */ -#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */ -#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */ -#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */ -#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */ -#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */ -#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */ - -#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */ -#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */ -#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */ -#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */ - - -/****************** Bit definition for ADC_JOFR1 register *******************/ -#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */ - -/****************** Bit definition for ADC_JOFR2 register *******************/ -#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */ - -/****************** Bit definition for ADC_JOFR3 register *******************/ -#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */ - -/****************** Bit definition for ADC_JOFR4 register *******************/ -#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */ - -/******************* Bit definition for ADC_HTR register ********************/ -#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */ - -/******************* Bit definition for ADC_LTR register ********************/ -#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */ - -/******************* Bit definition for ADC_SQR1 register *******************/ -#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */ -#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */ -#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */ -#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */ -#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */ - -/******************* Bit definition for ADC_SQR2 register *******************/ -#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */ -#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */ -#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */ -#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */ -#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */ -#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */ -#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_SQR3 register *******************/ -#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */ -#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */ -#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */ -#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */ -#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */ -#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */ -#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_SQR4 register *******************/ -#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */ -#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */ -#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */ -#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */ -#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */ -#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */ -#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - -/******************* Bit definition for ADC_SQR5 register *******************/ -#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */ -#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */ -#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */ -#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */ -#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */ -#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */ -#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */ -#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */ -#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */ - -#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */ -#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */ -#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */ -#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */ -#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */ -#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */ - - -/******************* Bit definition for ADC_JSQR register *******************/ -#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */ -#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */ -#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */ -#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */ -#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */ -#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */ -#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */ -#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */ -#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */ -#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */ -#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */ -#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */ -#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */ -#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */ - -#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */ -#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */ -#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */ -#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */ -#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */ -#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */ - -#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */ -#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */ -#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */ - -/******************* Bit definition for ADC_JDR1 register *******************/ -#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR2 register *******************/ -#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR3 register *******************/ -#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ - -/******************* Bit definition for ADC_JDR4 register *******************/ -#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */ - -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */ - - -/******************* Bit definition for ADC_CSR register ********************/ -#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */ -#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */ -#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */ -#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */ -#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */ -#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */ -#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */ - -/******************* Bit definition for ADC_CCR register ********************/ -#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/ -#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */ -#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */ -#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */ - -/******************************************************************************/ -/* */ -/* Analog Comparators (COMP) */ -/* */ -/******************************************************************************/ - -/****************** Bit definition for COMP_CSR register ********************/ -#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */ -#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */ -#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */ -#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */ - -#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */ -#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */ - -#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */ -#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */ - -#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */ -#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */ - -#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */ -#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */ -#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */ -#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */ - -#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */ -#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */ -#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */ -#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */ - -/******************************************************************************/ -/* */ -/* CRC calculation unit (CRC) */ -/* */ -/******************************************************************************/ - -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */ - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */ - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */ - -/******************************************************************************/ -/* */ -/* Digital to Analog Converter (DAC) */ -/* */ -/******************************************************************************/ - -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!
© COPYRIGHT 2010 STMicroelectronics
- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F10X_H -#define __SYSTEM_STM32F10X_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F10x_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F10x_System_Exported_types - * @{ - */ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F10X_H */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/device_support/system_stm32l1xx.h b/example/libs_stm/inc/device_support/system_stm32l1xx.h deleted file mode 100644 index 6ad7303cd..000000000 --- a/example/libs_stm/inc/device_support/system_stm32l1xx.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l1xx.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L1XX_H -#define __SYSTEM_STM32L1XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L1xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L1xx_System_Exported_types - * @{ - */ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L1XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/misc.h b/example/libs_stm/inc/stm32f10x/misc.h deleted file mode 100644 index 95c9541d3..000000000 --- a/example/libs_stm/inc/stm32f10x/misc.h +++ /dev/null @@ -1,219 +0,0 @@ -/** - ****************************************************************************** - * @file misc.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MISC_H -#define __MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/** @defgroup MISC_Exported_Types - * @{ - */ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be a value of @ref IRQn_Type - (For the complete STM32 Devices IRQ Channels list, please - refer to stm32f10x.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup NVIC_Priority_Table - * @{ - */ - -/** -@code - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - ============================================================================================================================ - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ============================================================================================================================ - NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ============================================================================================================================ -@endcode -*/ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup Vector_Table_Base - * @{ - */ - -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup Preemption_Priority_Group - * @{ - */ - -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) - -/** - * @} - */ - -/** @defgroup SysTick_clock_source - * @{ - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Exported_Functions - * @{ - */ - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_adc.h b/example/libs_stm/inc/stm32f10x/stm32f10x_adc.h deleted file mode 100644 index 401241c4c..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_adc.h +++ /dev/null @@ -1,482 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_adc.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the ADC firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_ADC_H -#define __STM32F10x_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/** @defgroup ADC_Exported_Types - * @{ - */ - -/** - * @brief ADC Init structure definition - */ - -typedef struct -{ - uint32_t ADC_Mode; /*!< Configures the ADC to operate in independent or - dual mode. - This parameter can be a value of @ref ADC_mode */ - - FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in - Scan (multichannels) or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ - - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint8_t ADC_NbrOfChannel; /*!< Specifies the number of ADC channels that will be converted - using the sequencer for regular channel group. - This parameter must range from 1 to 16. */ -}ADC_InitTypeDef; -/** - * @} - */ - -/** @defgroup ADC_Exported_Constants - * @{ - */ - -#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC2) || \ - ((PERIPH) == ADC3)) - -#define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC3)) - -/** @defgroup ADC_mode - * @{ - */ - -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) -#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) -#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) -#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) -#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) -#define ADC_Mode_RegSimult ((uint32_t)0x00060000) -#define ADC_Mode_FastInterl ((uint32_t)0x00070000) -#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) -#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) - -#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ - ((MODE) == ADC_Mode_RegInjecSimult) || \ - ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \ - ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \ - ((MODE) == ADC_Mode_InjecSimult) || \ - ((MODE) == ADC_Mode_RegSimult) || \ - ((MODE) == ADC_Mode_FastInterl) || \ - ((MODE) == ADC_Mode_SlowInterl) || \ - ((MODE) == ADC_Mode_AlterTrig)) -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion - * @{ - */ - -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) /*!< For ADC1 and ADC2 */ - -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) /*!< For ADC1, ADC2 and ADC3 */ - -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) /*!< For ADC3 only */ -#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) /*!< For ADC3 only */ - -#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_None) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3)) -/** - * @} - */ - -/** @defgroup ADC_data_align - * @{ - */ - -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - -/** @defgroup ADC_channels - * @{ - */ - -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) - -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ - ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ - ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ - ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ - ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ - ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ - ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ - ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ - ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17)) -/** - * @} - */ - -/** @defgroup ADC_sampling_time - * @{ - */ - -#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) -#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) -#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) -#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) -#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) -#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) -#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) -#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \ - ((TIME) == ADC_SampleTime_7Cycles5) || \ - ((TIME) == ADC_SampleTime_13Cycles5) || \ - ((TIME) == ADC_SampleTime_28Cycles5) || \ - ((TIME) == ADC_SampleTime_41Cycles5) || \ - ((TIME) == ADC_SampleTime_55Cycles5) || \ - ((TIME) == ADC_SampleTime_71Cycles5) || \ - ((TIME) == ADC_SampleTime_239Cycles5)) -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion - * @{ - */ - -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) /*!< For ADC1 and ADC2 */ -#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) /*!< For ADC1 and ADC2 */ - -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /*!< For ADC1, ADC2 and ADC3 */ -#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) /*!< For ADC1, ADC2 and ADC3 */ - -#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) /*!< For ADC3 only */ -#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) /*!< For ADC3 only */ - -#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4)) -/** - * @} - */ - -/** @defgroup ADC_injected_channel_selection - * @{ - */ - -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) -#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ - ((CHANNEL) == ADC_InjectedChannel_2) || \ - ((CHANNEL) == ADC_InjectedChannel_3) || \ - ((CHANNEL) == ADC_InjectedChannel_4)) -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ - -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) - -#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_None)) -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition - * @{ - */ - -#define ADC_IT_EOC ((uint16_t)0x0220) -#define ADC_IT_AWD ((uint16_t)0x0140) -#define ADC_IT_JEOC ((uint16_t)0x0480) - -#define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00)) - -#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ - ((IT) == ADC_IT_JEOC)) -/** - * @} - */ - -/** @defgroup ADC_flags_definition - * @{ - */ - -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) -#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00)) -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ - ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ - ((FLAG) == ADC_FLAG_STRT)) -/** - * @} - */ - -/** @defgroup ADC_thresholds - * @{ - */ - -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_offset - * @{ - */ - -#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_length - * @{ - */ - -#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) - -/** - * @} - */ - -/** @defgroup ADC_injected_rank - * @{ - */ - -#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) - -/** - * @} - */ - - -/** @defgroup ADC_regular_length - * @{ - */ - -#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) -/** - * @} - */ - -/** @defgroup ADC_regular_rank - * @{ - */ - -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) - -/** - * @} - */ - -/** @defgroup ADC_regular_discontinuous_mode_number - * @{ - */ - -#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions - * @{ - */ - -void ADC_DeInit(ADC_TypeDef* ADCx); -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); -void ADC_ResetCalibration(ADC_TypeDef* ADCx); -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); -void ADC_StartCalibration(ADC_TypeDef* ADCx); -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); -void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); -uint32_t ADC_GetDualModeConversionValue(void); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_bkp.h b/example/libs_stm/inc/stm32f10x/stm32f10x_bkp.h deleted file mode 100644 index 45c4e3500..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_bkp.h +++ /dev/null @@ -1,194 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_bkp.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the BKP firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_BKP_H -#define __STM32F10x_BKP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup BKP - * @{ - */ - -/** @defgroup BKP_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Constants - * @{ - */ - -/** @defgroup Tamper_Pin_active_level - * @{ - */ - -#define BKP_TamperPinLevel_High ((uint16_t)0x0000) -#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) -#define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ - ((LEVEL) == BKP_TamperPinLevel_Low)) -/** - * @} - */ - -/** @defgroup RTC_output_source_to_output_on_the_Tamper_pin - * @{ - */ - -#define BKP_RTCOutputSource_None ((uint16_t)0x0000) -#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) -#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) -#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) -#define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ - ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ - ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ - ((SOURCE) == BKP_RTCOutputSource_Second)) -/** - * @} - */ - -/** @defgroup Data_Backup_Register - * @{ - */ - -#define BKP_DR1 ((uint16_t)0x0004) -#define BKP_DR2 ((uint16_t)0x0008) -#define BKP_DR3 ((uint16_t)0x000C) -#define BKP_DR4 ((uint16_t)0x0010) -#define BKP_DR5 ((uint16_t)0x0014) -#define BKP_DR6 ((uint16_t)0x0018) -#define BKP_DR7 ((uint16_t)0x001C) -#define BKP_DR8 ((uint16_t)0x0020) -#define BKP_DR9 ((uint16_t)0x0024) -#define BKP_DR10 ((uint16_t)0x0028) -#define BKP_DR11 ((uint16_t)0x0040) -#define BKP_DR12 ((uint16_t)0x0044) -#define BKP_DR13 ((uint16_t)0x0048) -#define BKP_DR14 ((uint16_t)0x004C) -#define BKP_DR15 ((uint16_t)0x0050) -#define BKP_DR16 ((uint16_t)0x0054) -#define BKP_DR17 ((uint16_t)0x0058) -#define BKP_DR18 ((uint16_t)0x005C) -#define BKP_DR19 ((uint16_t)0x0060) -#define BKP_DR20 ((uint16_t)0x0064) -#define BKP_DR21 ((uint16_t)0x0068) -#define BKP_DR22 ((uint16_t)0x006C) -#define BKP_DR23 ((uint16_t)0x0070) -#define BKP_DR24 ((uint16_t)0x0074) -#define BKP_DR25 ((uint16_t)0x0078) -#define BKP_DR26 ((uint16_t)0x007C) -#define BKP_DR27 ((uint16_t)0x0080) -#define BKP_DR28 ((uint16_t)0x0084) -#define BKP_DR29 ((uint16_t)0x0088) -#define BKP_DR30 ((uint16_t)0x008C) -#define BKP_DR31 ((uint16_t)0x0090) -#define BKP_DR32 ((uint16_t)0x0094) -#define BKP_DR33 ((uint16_t)0x0098) -#define BKP_DR34 ((uint16_t)0x009C) -#define BKP_DR35 ((uint16_t)0x00A0) -#define BKP_DR36 ((uint16_t)0x00A4) -#define BKP_DR37 ((uint16_t)0x00A8) -#define BKP_DR38 ((uint16_t)0x00AC) -#define BKP_DR39 ((uint16_t)0x00B0) -#define BKP_DR40 ((uint16_t)0x00B4) -#define BKP_DR41 ((uint16_t)0x00B8) -#define BKP_DR42 ((uint16_t)0x00BC) - -#define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ - ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ - ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ - ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ - ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ - ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ - ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ - ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ - ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ - ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ - ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ - ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ - ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ - ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) - -#define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Exported_Functions - * @{ - */ - -void BKP_DeInit(void); -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); -void BKP_TamperPinCmd(FunctionalState NewState); -void BKP_ITConfig(FunctionalState NewState); -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); -FlagStatus BKP_GetFlagStatus(void); -void BKP_ClearFlag(void); -ITStatus BKP_GetITStatus(void); -void BKP_ClearITPendingBit(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_BKP_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_can.h b/example/libs_stm/inc/stm32f10x/stm32f10x_can.h deleted file mode 100644 index d9ae0676f..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_can.h +++ /dev/null @@ -1,535 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_can.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the CAN firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CAN_H -#define __STM32F10x_CAN_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CAN - * @{ - */ - -/** @defgroup CAN_Exported_Types - * @{ - */ - -#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ - ((PERIPH) == CAN2)) - -/** - * @brief CAN init structure definition - */ - -typedef struct -{ - uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. It ranges from 1 to 1024. */ - - uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta the CAN hardware - is allowed to lengthen or shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit Segment 1. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_NART; /*!< Enable or disable the no-automatic retransmission mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_InitTypeDef; - -/** - * @brief CAN filter init structure definition - */ - -typedef struct -{ - uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ - - uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint8_t CAN_FilterScale; /*!< Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_FilterInitTypeDef; - -/** - * @brief CAN Tx message structure definition - */ - -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. - This parameter can be a value of @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. - This parameter can be a value of @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be transmitted. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */ -} CanTxMsg; - -/** - * @brief CAN Rx message structure definition - */ - -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that will be received. - This parameter can be a value of @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 0xFF. */ - - uint8_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. - This parameter can be a value between 0 to 0xFF */ -} CanRxMsg; - -/** - * @} - */ - -/** @defgroup CAN_Exported_Constants - * @{ - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ - -#define CANINITFAILED ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CANINITOK ((uint8_t)0x01) /*!< CAN initialization failed */ - -/** - * @} - */ - -/** @defgroup CAN_operating_mode - * @{ - */ - -#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ -#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ -#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ -#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| \ - ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack)) -/** - * @} - */ - -/** @defgroup CAN_synchronisation_jump_width - * @{ - */ - -#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ - ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_1 - * @{ - */ - -#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ -#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ -#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ -#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ -#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ -#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ -#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ -#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ -#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_2 - * @{ - */ - -#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) - -/** - * @} - */ - -/** @defgroup CAN_clock_prescaler - * @{ - */ - -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) - -/** - * @} - */ - -/** @defgroup CAN_filter_number - * @{ - */ -#ifndef STM32F10X_CL - #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 13) -#else - #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup CAN_filter_mode - * @{ - */ - -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< id/mask mode */ -#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ - -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ - ((MODE) == CAN_FilterMode_IdList)) -/** - * @} - */ - -/** @defgroup CAN_filter_scale - * @{ - */ - -#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ - -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ - ((SCALE) == CAN_FilterScale_32bit)) - -/** - * @} - */ - -/** @defgroup CAN_filter_FIFO - * @{ - */ - -#define CAN_FilterFIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FilterFIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ - ((FIFO) == CAN_FilterFIFO1)) - -/** - * @} - */ - -/** @defgroup Start_bank_filter_for_slave_CAN - * @{ - */ -#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) -/** - * @} - */ - -/** @defgroup CAN_Tx - * @{ - */ - -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) - -/** - * @} - */ - -/** @defgroup CAN_identifier_type - * @{ - */ - -#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */ -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || ((IDTYPE) == CAN_ID_EXT)) - -/** - * @} - */ - -/** @defgroup CAN_remote_transmission_request - * @{ - */ - -#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */ -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) - -/** - * @} - */ - -/** @defgroup CAN_transmit_constants - * @{ - */ - -#define CANTXFAILED ((uint8_t)0x00) /*!< CAN transmission failed */ -#define CANTXOK ((uint8_t)0x01) /*!< CAN transmission succeeded */ -#define CANTXPENDING ((uint8_t)0x02) /*!< CAN transmission pending */ -#define CAN_NO_MB ((uint8_t)0x04) /*!< CAN cell did not provide an empty mailbox */ - -/** - * @} - */ - -/** @defgroup CAN_receive_FIFO_number_constants - * @{ - */ - -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO1 used to receive */ - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) - -/** - * @} - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ - -#define CANSLEEPFAILED ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ -#define CANSLEEPOK ((uint8_t)0x01) /*!< CAN entered the sleep mode */ - -/** - * @} - */ - -/** @defgroup CAN_wake_up_constants - * @{ - */ - -#define CANWAKEUPFAILED ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ -#define CANWAKEUPOK ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ - -/** - * @} - */ - -/** @defgroup CAN_flags - * @{ - */ - -#define CAN_FLAG_EWG ((uint32_t)0x00000001) /*!< Error Warning Flag */ -#define CAN_FLAG_EPV ((uint32_t)0x00000002) /*!< Error Passive Flag */ -#define CAN_FLAG_BOF ((uint32_t)0x00000004) /*!< Bus-Off Flag */ - -#define IS_CAN_FLAG(FLAG) (((FLAG) == CAN_FLAG_EWG) || ((FLAG) == CAN_FLAG_EPV) ||\ - ((FLAG) == CAN_FLAG_BOF)) - -/** - * @} - */ - -/** @defgroup CAN_interrupts - * @{ - */ - -#define CAN_IT_RQCP0 ((uint32_t)0x00000005) /*!< Request completed mailbox 0 */ -#define CAN_IT_RQCP1 ((uint32_t)0x00000006) /*!< Request completed mailbox 1 */ -#define CAN_IT_RQCP2 ((uint32_t)0x00000007) /*!< Request completed mailbox 2 */ -#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty */ -#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending */ -#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full */ -#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun */ -#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending */ -#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full */ -#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun */ -#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning */ -#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive */ -#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off */ -#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code */ -#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error */ -#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up */ -#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep */ - -#define IS_CAN_ITConfig(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ - ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ - ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -#define IS_CAN_ITStatus(IT) (((IT) == CAN_IT_RQCP0) || ((IT) == CAN_IT_RQCP1) ||\ - ((IT) == CAN_IT_RQCP2) || ((IT) == CAN_IT_FF0) ||\ - ((IT) == CAN_IT_FOV0) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup CAN_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions - * @{ - */ - -void CAN_DeInit(CAN_TypeDef* CANx); -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); -void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); -uint8_t CAN_Sleep(CAN_TypeDef* CANx); -uint8_t CAN_WakeUp(CAN_TypeDef* CANx); -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_CAN_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_cec.h b/example/libs_stm/inc/stm32f10x/stm32f10x_cec.h deleted file mode 100644 index 233a0944f..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_cec.h +++ /dev/null @@ -1,209 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_cec.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the CEC firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CEC_H -#define __STM32F10x_CEC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CEC - * @{ - */ - - -/** @defgroup CEC_Exported_Types - * @{ - */ - -/** - * @brief CEC Init structure definition - */ -typedef struct -{ - uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. - This parameter can be a value of @ref CEC_BitTiming_Mode */ - uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. - This parameter can be a value of @ref CEC_BitPeriod_Mode */ -}CEC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup CEC_Exported_Constants - * @{ - */ - -/** @defgroup CEC_BitTiming_Mode - * @{ - */ -#define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ -#define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ - -#define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ - ((MODE) == CEC_BitTimingErrFreeMode)) -/** - * @} - */ - -/** @defgroup CEC_BitPeriod_Mode - * @{ - */ -#define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ -#define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ - -#define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ - ((MODE) == CEC_BitPeriodFlexibleMode)) -/** - * @} - */ - - -/** @defgroup CEC_interrupts_definition - * @{ - */ -#define CEC_IT_TERR CEC_CSR_TERR -#define CEC_IT_TBTRF CEC_CSR_TBTRF -#define CEC_IT_RERR CEC_CSR_RERR -#define CEC_IT_RBTF CEC_CSR_RBTF -#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ - ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) -/** - * @} - */ - - -/** @defgroup CEC_Own_Addres - * @{ - */ -#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) -/** - * @} - */ - -/** @defgroup CEC_Prescaler - * @{ - */ -#define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) - -/** - * @} - */ - -/** @defgroup CEC_flags_definition - * @{ - */ - -/** - * @brief ESR register flags - */ -#define CEC_FLAG_BTE ((uint32_t)0x10010000) -#define CEC_FLAG_BPE ((uint32_t)0x10020000) -#define CEC_FLAG_RBTFE ((uint32_t)0x10040000) -#define CEC_FLAG_SBE ((uint32_t)0x10080000) -#define CEC_FLAG_ACKE ((uint32_t)0x10100000) -#define CEC_FLAG_LINE ((uint32_t)0x10200000) -#define CEC_FLAG_TBTFE ((uint32_t)0x10400000) - -/** - * @brief CSR register flags - */ -#define CEC_FLAG_TEOM ((uint32_t)0x00000002) -#define CEC_FLAG_TERR ((uint32_t)0x00000004) -#define CEC_FLAG_TBTRF ((uint32_t)0x00000008) -#define CEC_FLAG_RSOM ((uint32_t)0x00000010) -#define CEC_FLAG_REOM ((uint32_t)0x00000020) -#define CEC_FLAG_RERR ((uint32_t)0x00000040) -#define CEC_FLAG_RBTF ((uint32_t)0x00000080) - -#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) - -#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ - ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ - ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ - ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ - ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ - ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ - ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup CEC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CEC_Exported_Functions - * @{ - */ -void CEC_DeInit(void); -void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); -void CEC_Cmd(FunctionalState NewState); -void CEC_ITConfig(FunctionalState NewState); -void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); -void CEC_SetPrescaler(uint16_t CEC_Prescaler); -void CEC_SendDataByte(uint8_t Data); -uint8_t CEC_ReceiveDataByte(void); -void CEC_StartOfMessage(void); -void CEC_EndOfMessageCmd(FunctionalState NewState); -FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); -void CEC_ClearFlag(uint32_t CEC_FLAG); -ITStatus CEC_GetITStatus(uint8_t CEC_IT); -void CEC_ClearITPendingBit(uint16_t CEC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_CEC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_crc.h b/example/libs_stm/inc/stm32f10x/stm32f10x_crc.h deleted file mode 100644 index f7b2678c3..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_crc.h +++ /dev/null @@ -1,93 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_crc.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the CRC firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_CRC_H -#define __STM32F10x_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/** @defgroup CRC_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Exported_Functions - * @{ - */ - -void CRC_ResetDR(void); -uint32_t CRC_CalcCRC(uint32_t Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); -void CRC_SetIDRegister(uint8_t IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_CRC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_dac.h b/example/libs_stm/inc/stm32f10x/stm32f10x_dac.h deleted file mode 100644 index 16afbce49..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_dac.h +++ /dev/null @@ -1,316 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dac.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the DAC firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_DAC_H -#define __STM32F10x_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/** @defgroup DAC_Exported_Types - * @{ - */ - -/** - * @brief DAC Init structure definition - */ - -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_InitTypeDef; - -/** - * @} - */ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -/** @defgroup DAC_trigger_selection - * @{ - */ - -#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel - only in High-density devices*/ -#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel - only in Connectivity line, Medium-density and Low-density Value Line devices */ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel - only in Medium-density and Low-density Value Line devices*/ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ - ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ - ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ - ((TRIGGER) == DAC_Trigger_Software)) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ - ((WAVE) == DAC_WaveGeneration_Noise) || \ - ((WAVE) == DAC_WaveGeneration_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_lfsrunmask_triangleamplitude - * @{ - */ - -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ - ((VALUE) == DAC_TriangleAmplitude_1) || \ - ((VALUE) == DAC_TriangleAmplitude_3) || \ - ((VALUE) == DAC_TriangleAmplitude_7) || \ - ((VALUE) == DAC_TriangleAmplitude_15) || \ - ((VALUE) == DAC_TriangleAmplitude_31) || \ - ((VALUE) == DAC_TriangleAmplitude_63) || \ - ((VALUE) == DAC_TriangleAmplitude_127) || \ - ((VALUE) == DAC_TriangleAmplitude_255) || \ - ((VALUE) == DAC_TriangleAmplitude_511) || \ - ((VALUE) == DAC_TriangleAmplitude_1023) || \ - ((VALUE) == DAC_TriangleAmplitude_2047) || \ - ((VALUE) == DAC_TriangleAmplitude_4095)) -/** - * @} - */ - -/** @defgroup DAC_output_buffer - * @{ - */ - -#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) -#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ - ((STATE) == DAC_OutputBuffer_Disable)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ - -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ - ((CHANNEL) == DAC_Channel_2)) -/** - * @} - */ - -/** @defgroup DAC_data_alignement - * @{ - */ - -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ - ((ALIGN) == DAC_Align_12b_L) || \ - ((ALIGN) == DAC_Align_8b_R)) -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ - ((WAVE) == DAC_Wave_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_data - * @{ - */ - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -/** - * @} - */ -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) -/** @defgroup DAC_interrupts_definition - * @{ - */ - -#define DAC_IT_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) - -/** - * @} - */ - -/** @defgroup DAC_flags_definition - * @{ - */ - -#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) - -/** - * @} - */ -#endif - -/** - * @} - */ - -/** @defgroup DAC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions - * @{ - */ - -void DAC_DeInit(void); -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); -#endif -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_DAC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_dbgmcu.h b/example/libs_stm/inc/stm32f10x/stm32f10x_dbgmcu.h deleted file mode 100644 index 5a78f7355..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_dbgmcu.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dbgmcu.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the DBGMCU - * firmware library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_DBGMCU_H -#define __STM32F10x_DBGMCU_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DBGMCU - * @{ - */ - -/** @defgroup DBGMCU_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Exported_Constants - * @{ - */ - -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) -#define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) -#define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) -#define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) -#define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) -#define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) -#define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) -#define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) -#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) -#define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) -#define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) -#define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) -#define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) -#define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) -#define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) -#define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) -#define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) -#define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) - -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup DBGMCU_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Exported_Functions - * @{ - */ - -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_DBGMCU_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_dma.h b/example/libs_stm/inc/stm32f10x/stm32f10x_dma.h deleted file mode 100644 index 35769abc6..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_dma.h +++ /dev/null @@ -1,437 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dma.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the DMA firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_DMA_H -#define __STM32F10x_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/** @defgroup DMA_Exported_Types - * @{ - */ - -/** - * @brief DMA Init structure definition - */ - -typedef struct -{ - uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ - - uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ - - uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_circular_normal_mode. - @note: The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. - This parameter can be a value of @ref DMA_memory_to_memory */ -}DMA_InitTypeDef; - -/** - * @} - */ - -/** @defgroup DMA_Exported_Constants - * @{ - */ - -#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ - ((PERIPH) == DMA1_Channel2) || \ - ((PERIPH) == DMA1_Channel3) || \ - ((PERIPH) == DMA1_Channel4) || \ - ((PERIPH) == DMA1_Channel5) || \ - ((PERIPH) == DMA1_Channel6) || \ - ((PERIPH) == DMA1_Channel7) || \ - ((PERIPH) == DMA2_Channel1) || \ - ((PERIPH) == DMA2_Channel2) || \ - ((PERIPH) == DMA2_Channel3) || \ - ((PERIPH) == DMA2_Channel4) || \ - ((PERIPH) == DMA2_Channel5)) - -/** @defgroup DMA_data_transfer_direction - * @{ - */ - -#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) -#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ - ((DIR) == DMA_DIR_PeripheralSRC)) -/** - * @} - */ - -/** @defgroup DMA_peripheral_incremented_mode - * @{ - */ - -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ - ((STATE) == DMA_PeripheralInc_Disable)) -/** - * @} - */ - -/** @defgroup DMA_memory_incremented_mode - * @{ - */ - -#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ - ((STATE) == DMA_MemoryInc_Disable)) -/** - * @} - */ - -/** @defgroup DMA_peripheral_data_size - * @{ - */ - -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ - ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ - ((SIZE) == DMA_PeripheralDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_memory_data_size - * @{ - */ - -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ - ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ - ((SIZE) == DMA_MemoryDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_circular_normal_mode - * @{ - */ - -#define DMA_Mode_Circular ((uint32_t)0x00000020) -#define DMA_Mode_Normal ((uint32_t)0x00000000) -#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) -/** - * @} - */ - -/** @defgroup DMA_priority_level - * @{ - */ - -#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) -#define DMA_Priority_High ((uint32_t)0x00002000) -#define DMA_Priority_Medium ((uint32_t)0x00001000) -#define DMA_Priority_Low ((uint32_t)0x00000000) -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ - ((PRIORITY) == DMA_Priority_High) || \ - ((PRIORITY) == DMA_Priority_Medium) || \ - ((PRIORITY) == DMA_Priority_Low)) -/** - * @} - */ - -/** @defgroup DMA_memory_to_memory - * @{ - */ - -#define DMA_M2M_Enable ((uint32_t)0x00004000) -#define DMA_M2M_Disable ((uint32_t)0x00000000) -#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) - -/** - * @} - */ - -/** @defgroup DMA_interrupts_definition - * @{ - */ - -#define DMA_IT_TC ((uint32_t)0x00000002) -#define DMA_IT_HT ((uint32_t)0x00000004) -#define DMA_IT_TE ((uint32_t)0x00000008) -#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) - -#define DMA1_IT_GL1 ((uint32_t)0x00000001) -#define DMA1_IT_TC1 ((uint32_t)0x00000002) -#define DMA1_IT_HT1 ((uint32_t)0x00000004) -#define DMA1_IT_TE1 ((uint32_t)0x00000008) -#define DMA1_IT_GL2 ((uint32_t)0x00000010) -#define DMA1_IT_TC2 ((uint32_t)0x00000020) -#define DMA1_IT_HT2 ((uint32_t)0x00000040) -#define DMA1_IT_TE2 ((uint32_t)0x00000080) -#define DMA1_IT_GL3 ((uint32_t)0x00000100) -#define DMA1_IT_TC3 ((uint32_t)0x00000200) -#define DMA1_IT_HT3 ((uint32_t)0x00000400) -#define DMA1_IT_TE3 ((uint32_t)0x00000800) -#define DMA1_IT_GL4 ((uint32_t)0x00001000) -#define DMA1_IT_TC4 ((uint32_t)0x00002000) -#define DMA1_IT_HT4 ((uint32_t)0x00004000) -#define DMA1_IT_TE4 ((uint32_t)0x00008000) -#define DMA1_IT_GL5 ((uint32_t)0x00010000) -#define DMA1_IT_TC5 ((uint32_t)0x00020000) -#define DMA1_IT_HT5 ((uint32_t)0x00040000) -#define DMA1_IT_TE5 ((uint32_t)0x00080000) -#define DMA1_IT_GL6 ((uint32_t)0x00100000) -#define DMA1_IT_TC6 ((uint32_t)0x00200000) -#define DMA1_IT_HT6 ((uint32_t)0x00400000) -#define DMA1_IT_TE6 ((uint32_t)0x00800000) -#define DMA1_IT_GL7 ((uint32_t)0x01000000) -#define DMA1_IT_TC7 ((uint32_t)0x02000000) -#define DMA1_IT_HT7 ((uint32_t)0x04000000) -#define DMA1_IT_TE7 ((uint32_t)0x08000000) - -#define DMA2_IT_GL1 ((uint32_t)0x10000001) -#define DMA2_IT_TC1 ((uint32_t)0x10000002) -#define DMA2_IT_HT1 ((uint32_t)0x10000004) -#define DMA2_IT_TE1 ((uint32_t)0x10000008) -#define DMA2_IT_GL2 ((uint32_t)0x10000010) -#define DMA2_IT_TC2 ((uint32_t)0x10000020) -#define DMA2_IT_HT2 ((uint32_t)0x10000040) -#define DMA2_IT_TE2 ((uint32_t)0x10000080) -#define DMA2_IT_GL3 ((uint32_t)0x10000100) -#define DMA2_IT_TC3 ((uint32_t)0x10000200) -#define DMA2_IT_HT3 ((uint32_t)0x10000400) -#define DMA2_IT_TE3 ((uint32_t)0x10000800) -#define DMA2_IT_GL4 ((uint32_t)0x10001000) -#define DMA2_IT_TC4 ((uint32_t)0x10002000) -#define DMA2_IT_HT4 ((uint32_t)0x10004000) -#define DMA2_IT_TE4 ((uint32_t)0x10008000) -#define DMA2_IT_GL5 ((uint32_t)0x10010000) -#define DMA2_IT_TC5 ((uint32_t)0x10020000) -#define DMA2_IT_HT5 ((uint32_t)0x10040000) -#define DMA2_IT_TE5 ((uint32_t)0x10080000) - -#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00)) - -#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ - ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ - ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ - ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ - ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ - ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ - ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ - ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ - ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ - ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ - ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ - ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ - ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ - ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \ - ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \ - ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \ - ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \ - ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \ - ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \ - ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \ - ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \ - ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \ - ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \ - ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5)) - -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ -#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) - -#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) -#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) -#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) -#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) -#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) -#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) -#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) -#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) -#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) -#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) -#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) -#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) -#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) -#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) -#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) -#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) -#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) -#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) -#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) -#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) - -#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00)) - -#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ - ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ - ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ - ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ - ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ - ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ - ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ - ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ - ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ - ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ - ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ - ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ - ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ - ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \ - ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \ - ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \ - ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \ - ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \ - ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \ - ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \ - ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \ - ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \ - ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \ - ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5)) -/** - * @} - */ - -/** @defgroup DMA_Buffer_Size - * @{ - */ - -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup DMA_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions - * @{ - */ - -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); -FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); -void DMA_ClearFlag(uint32_t DMA_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMA_IT); -void DMA_ClearITPendingBit(uint32_t DMA_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_DMA_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_exti.h b/example/libs_stm/inc/stm32f10x/stm32f10x_exti.h deleted file mode 100644 index e5f1c5a06..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_exti.h +++ /dev/null @@ -1,183 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_exti.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the EXTI firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_EXTI_H -#define __STM32F10x_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/** @defgroup EXTI_Exported_Types - * @{ - */ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS - Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ - -#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) - - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Functions - * @{ - */ - -void EXTI_DeInit(void); -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_EXTI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_flash.h b/example/libs_stm/inc/stm32f10x/stm32f10x_flash.h deleted file mode 100644 index 71943013d..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_flash.h +++ /dev/null @@ -1,425 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_flash.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_FLASH_H -#define __STM32F10x_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/** @defgroup FLASH_Exported_Types - * @{ - */ - -/** - * @brief FLASH Status - */ - -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PG, - FLASH_ERROR_WRP, - FLASH_COMPLETE, - FLASH_TIMEOUT -}FLASH_Status; - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup Flash_Latency - * @{ - */ - -#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint32_t)0x00000002) /*!< FLASH Two Latency cycles */ -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2)) -/** - * @} - */ - -/** @defgroup Half_Cycle_Enable_Disable - * @{ - */ - -#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /*!< FLASH Half Cycle Enable */ -#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /*!< FLASH Half Cycle Disable */ -#define IS_FLASH_HALFCYCLEACCESS_STATE(STATE) (((STATE) == FLASH_HalfCycleAccess_Enable) || \ - ((STATE) == FLASH_HalfCycleAccess_Disable)) -/** - * @} - */ - -/** @defgroup Prefetch_Buffer_Enable_Disable - * @{ - */ - -#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /*!< FLASH Prefetch Buffer Enable */ -#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /*!< FLASH Prefetch Buffer Disable */ -#define IS_FLASH_PREFETCHBUFFER_STATE(STATE) (((STATE) == FLASH_PrefetchBuffer_Enable) || \ - ((STATE) == FLASH_PrefetchBuffer_Disable)) -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ - -/* Values to be used with STM32 Low and Medium density devices */ -#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /*!< STM32 Low and Medium density devices: Write protection of page 0 to 3 */ -#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /*!< STM32 Low and Medium density devices: Write protection of page 4 to 7 */ -#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /*!< STM32 Low and Medium density devices: Write protection of page 8 to 11 */ -#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /*!< STM32 Low and Medium density devices: Write protection of page 12 to 15 */ -#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /*!< STM32 Low and Medium density devices: Write protection of page 16 to 19 */ -#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /*!< STM32 Low and Medium density devices: Write protection of page 20 to 23 */ -#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /*!< STM32 Low and Medium density devices: Write protection of page 24 to 27 */ -#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /*!< STM32 Low and Medium density devices: Write protection of page 28 to 31 */ - -/* Values to be used with STM32 Medium-density devices */ -#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /*!< STM32 Medium-density devices: Write protection of page 32 to 35 */ -#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /*!< STM32 Medium-density devices: Write protection of page 36 to 39 */ -#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /*!< STM32 Medium-density devices: Write protection of page 40 to 43 */ -#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /*!< STM32 Medium-density devices: Write protection of page 44 to 47 */ -#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /*!< STM32 Medium-density devices: Write protection of page 48 to 51 */ -#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /*!< STM32 Medium-density devices: Write protection of page 52 to 55 */ -#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /*!< STM32 Medium-density devices: Write protection of page 56 to 59 */ -#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /*!< STM32 Medium-density devices: Write protection of page 60 to 63 */ -#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /*!< STM32 Medium-density devices: Write protection of page 64 to 67 */ -#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /*!< STM32 Medium-density devices: Write protection of page 68 to 71 */ -#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /*!< STM32 Medium-density devices: Write protection of page 72 to 75 */ -#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /*!< STM32 Medium-density devices: Write protection of page 76 to 79 */ -#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /*!< STM32 Medium-density devices: Write protection of page 80 to 83 */ -#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /*!< STM32 Medium-density devices: Write protection of page 84 to 87 */ -#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /*!< STM32 Medium-density devices: Write protection of page 88 to 91 */ -#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /*!< STM32 Medium-density devices: Write protection of page 92 to 95 */ -#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /*!< STM32 Medium-density devices: Write protection of page 96 to 99 */ -#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /*!< STM32 Medium-density devices: Write protection of page 100 to 103 */ -#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /*!< STM32 Medium-density devices: Write protection of page 104 to 107 */ -#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /*!< STM32 Medium-density devices: Write protection of page 108 to 111 */ -#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /*!< STM32 Medium-density devices: Write protection of page 112 to 115 */ -#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /*!< STM32 Medium-density devices: Write protection of page 115 to 119 */ -#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /*!< STM32 Medium-density devices: Write protection of page 120 to 123 */ -#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 124 to 127 */ - -/* Values to be used with STM32 High-density and STM32F10X Connectivity line devices */ -#define FLASH_WRProt_Pages0to1 ((uint32_t)0x00000001) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 0 to 1 */ -#define FLASH_WRProt_Pages2to3 ((uint32_t)0x00000002) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 2 to 3 */ -#define FLASH_WRProt_Pages4to5 ((uint32_t)0x00000004) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 4 to 5 */ -#define FLASH_WRProt_Pages6to7 ((uint32_t)0x00000008) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 6 to 7 */ -#define FLASH_WRProt_Pages8to9 ((uint32_t)0x00000010) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 8 to 9 */ -#define FLASH_WRProt_Pages10to11 ((uint32_t)0x00000020) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 10 to 11 */ -#define FLASH_WRProt_Pages12to13 ((uint32_t)0x00000040) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 12 to 13 */ -#define FLASH_WRProt_Pages14to15 ((uint32_t)0x00000080) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 14 to 15 */ -#define FLASH_WRProt_Pages16to17 ((uint32_t)0x00000100) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 16 to 17 */ -#define FLASH_WRProt_Pages18to19 ((uint32_t)0x00000200) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 18 to 19 */ -#define FLASH_WRProt_Pages20to21 ((uint32_t)0x00000400) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 20 to 21 */ -#define FLASH_WRProt_Pages22to23 ((uint32_t)0x00000800) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 22 to 23 */ -#define FLASH_WRProt_Pages24to25 ((uint32_t)0x00001000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 24 to 25 */ -#define FLASH_WRProt_Pages26to27 ((uint32_t)0x00002000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 26 to 27 */ -#define FLASH_WRProt_Pages28to29 ((uint32_t)0x00004000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 28 to 29 */ -#define FLASH_WRProt_Pages30to31 ((uint32_t)0x00008000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 30 to 31 */ -#define FLASH_WRProt_Pages32to33 ((uint32_t)0x00010000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 32 to 33 */ -#define FLASH_WRProt_Pages34to35 ((uint32_t)0x00020000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 34 to 35 */ -#define FLASH_WRProt_Pages36to37 ((uint32_t)0x00040000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 36 to 37 */ -#define FLASH_WRProt_Pages38to39 ((uint32_t)0x00080000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 38 to 39 */ -#define FLASH_WRProt_Pages40to41 ((uint32_t)0x00100000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 40 to 41 */ -#define FLASH_WRProt_Pages42to43 ((uint32_t)0x00200000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 42 to 43 */ -#define FLASH_WRProt_Pages44to45 ((uint32_t)0x00400000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 44 to 45 */ -#define FLASH_WRProt_Pages46to47 ((uint32_t)0x00800000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 46 to 47 */ -#define FLASH_WRProt_Pages48to49 ((uint32_t)0x01000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 48 to 49 */ -#define FLASH_WRProt_Pages50to51 ((uint32_t)0x02000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 50 to 51 */ -#define FLASH_WRProt_Pages52to53 ((uint32_t)0x04000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 52 to 53 */ -#define FLASH_WRProt_Pages54to55 ((uint32_t)0x08000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 54 to 55 */ -#define FLASH_WRProt_Pages56to57 ((uint32_t)0x10000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 56 to 57 */ -#define FLASH_WRProt_Pages58to59 ((uint32_t)0x20000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 58 to 59 */ -#define FLASH_WRProt_Pages60to61 ((uint32_t)0x40000000) /*!< STM32 High-density, XL-density and Connectivity line devices: - Write protection of page 60 to 61 */ -#define FLASH_WRProt_Pages62to127 ((uint32_t)0x80000000) /*!< STM32 Connectivity line devices: Write protection of page 62 to 127 */ -#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /*!< STM32 Medium-density devices: Write protection of page 62 to 255 */ -#define FLASH_WRProt_Pages62to511 ((uint32_t)0x80000000) /*!< STM32 XL-density devices: Write protection of page 62 to 511 */ - -#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Pages */ - -#define IS_FLASH_WRPROT_PAGE(PAGE) (((PAGE) != 0x00000000)) - -#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) - -#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_IWatchdog - * @{ - */ - -#define OB_IWDG_SW ((uint16_t)0x0001) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint16_t)0x0000) /*!< Hardware IWDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STOP - * @{ - */ - -#define OB_STOP_NoRST ((uint16_t)0x0002) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STDBY - * @{ - */ - -#define OB_STDBY_NoRST ((uint16_t)0x0004) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint16_t)0x0000) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) - -#ifdef STM32F10X_XL -/** - * @} - */ -/** @defgroup FLASH_Boot - * @{ - */ -#define FLASH_BOOT_Bank1 ((uint16_t)0x0000) /*!< At startup, if boot pins are set in boot from user Flash position - and this parameter is selected the device will boot from Bank1(Default) */ -#define FLASH_BOOT_Bank2 ((uint16_t)0x0001) /*!< At startup, if boot pins are set in boot from user Flash position - and this parameter is selected the device will boot from Bank 2 or Bank 1, - depending on the activation of the bank */ -#define IS_FLASH_BOOT(BOOT) (((BOOT) == FLASH_BOOT_Bank1) || ((BOOT) == FLASH_BOOT_Bank2)) -#endif -/** - * @} - */ -/** @defgroup FLASH_Interrupts - * @{ - */ -#ifdef STM32F10X_XL -#define FLASH_IT_BANK2_ERROR ((uint32_t)0x80000400) /*!< FPEC BANK2 error interrupt source */ -#define FLASH_IT_BANK2_EOP ((uint32_t)0x80001000) /*!< End of FLASH BANK2 Operation Interrupt source */ - -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ - -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC BANK1 error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH BANK1 Operation Interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0x7FFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) -#else -#define FLASH_IT_ERROR ((uint32_t)0x00000400) /*!< FPEC error interrupt source */ -#define FLASH_IT_EOP ((uint32_t)0x00001000) /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /*!< FPEC BANK1 error interrupt source */ -#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /*!< End of FLASH BANK1 Operation Interrupt source */ - -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000))) -#endif - -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ -#ifdef STM32F10X_XL -#define FLASH_FLAG_BANK2_BSY ((uint32_t)0x80000001) /*!< FLASH BANK2 Busy flag */ -#define FLASH_FLAG_BANK2_EOP ((uint32_t)0x80000020) /*!< FLASH BANK2 End of Operation flag */ -#define FLASH_FLAG_BANK2_PGERR ((uint32_t)0x80000004) /*!< FLASH BANK2 Program error flag */ -#define FLASH_FLAG_BANK2_WRPRTERR ((uint32_t)0x80000010) /*!< FLASH BANK2 Write protected error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ - -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0x7FFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ - ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_OPTERR)|| \ - ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ - ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_BANK2_BSY) || ((FLAG) == FLASH_FLAG_BANK2_EOP) || \ - ((FLAG) == FLASH_FLAG_BANK2_PGERR) || ((FLAG) == FLASH_FLAG_BANK2_WRPRTERR)) -#else -#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /*!< FLASH Busy flag */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /*!< FLASH Program error flag */ -#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /*!< FLASH Option Byte error flag */ - -#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /*!< FLASH BANK1 Busy flag*/ -#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /*!< FLASH BANK1 End of Operation flag */ -#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /*!< FLASH BANK1 Program error flag */ -#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /*!< FLASH BANK1 Write protected error flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCA) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ - ((FLAG) == FLASH_FLAG_PGERR) || ((FLAG) == FLASH_FLAG_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_BANK1_BSY) || ((FLAG) == FLASH_FLAG_BANK1_EOP) || \ - ((FLAG) == FLASH_FLAG_BANK1_PGERR) || ((FLAG) == FLASH_FLAG_BANK1_WRPRTERR) || \ - ((FLAG) == FLASH_FLAG_OPTERR)) -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions - * @{ - */ - -/*------------ Functions used for all STM32F10x devices -----*/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess); -void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer); -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_EraseAllPages(void); -FLASH_Status FLASH_EraseOptionBytes(void); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); -uint32_t FLASH_GetUserOptionByte(void); -uint32_t FLASH_GetWriteProtectionOptionByte(void); -FlagStatus FLASH_GetReadOutProtectionStatus(void); -FlagStatus FLASH_GetPrefetchBufferStatus(void); -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); - -/*------------ New function used for all STM32F10x devices -----*/ -void FLASH_UnlockBank1(void); -void FLASH_LockBank1(void); -FLASH_Status FLASH_EraseAllBank1Pages(void); -FLASH_Status FLASH_GetBank1Status(void); -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); - -#ifdef STM32F10X_XL -/*---- New Functions used only with STM32F10x_XL density devices -----*/ -void FLASH_UnlockBank2(void); -void FLASH_LockBank2(void); -FLASH_Status FLASH_EraseAllBank2Pages(void); -FLASH_Status FLASH_GetBank2Status(void); -FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout); -FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_FLASH_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_fsmc.h b/example/libs_stm/inc/stm32f10x/stm32f10x_fsmc.h deleted file mode 100644 index 944f077ed..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_fsmc.h +++ /dev/null @@ -1,716 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_fsmc.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the FSMC firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_FSMC_H -#define __STM32F10x_FSMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FSMC - * @{ - */ - -/** @defgroup FSMC_Exported_Types - * @{ - */ - -/** - * @brief Timing parameters For NOR/SRAM Banks - */ - -typedef struct -{ - uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between 0 and 0xF. - @note: It is not used with synchronous NOR Flash memories. */ - - uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between 0 and 0xF. - @note: It is not used with synchronous NOR Flash memories.*/ - - uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between 0 and 0xFF. - @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - - uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between 0 and 0xF. - @note: It is only used for multiplexed NOR Flash memories. */ - - uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. - This parameter can be a value between 1 and 0xF. - @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - - uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The value of this parameter depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is dont care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between 0 and 0xF in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ -}FSMC_NORSRAMTimingInitTypeDef; - -/** - * @brief FSMC NOR/SRAM Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ - - uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the databus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ - - uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory bank. - This parameter can be a value of @ref FSMC_Memory_Type */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_Data_Width */ - - uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ - - uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ - - uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode */ - - uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ - - uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ - - uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ - - uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ - - uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ -}FSMC_NORSRAMInitTypeDef; - -/** - * @brief Timing parameters For FSMC NAND and PCCARD Banks - */ - -typedef struct -{ - uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND-Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between 0 and 0xFF.*/ - - uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND-Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command deassertion - for NAND-Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - databus is kept in HiZ after the start of a NAND-Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ -}FSMC_NAND_PCCARDTimingInitTypeDef; - -/** - * @brief FSMC NAND Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ - - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FSMC_Data_Width */ - - uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ - - uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ -}FSMC_NANDInitTypeDef; - -/** - * @brief FSMC PCCARD Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ -}FSMC_PCCARDInitTypeDef; - -/** - * @} - */ - -/** @defgroup FSMC_Exported_Constants - * @{ - */ - -/** @defgroup FSMC_NORSRAM_Bank - * @{ - */ -#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) -#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) -#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) -#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup FSMC_NAND_Bank - * @{ - */ -#define FSMC_Bank2_NAND ((uint32_t)0x00000010) -#define FSMC_Bank3_NAND ((uint32_t)0x00000100) -/** - * @} - */ - -/** @defgroup FSMC_PCCARD_Bank - * @{ - */ -#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) -/** - * @} - */ - -#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ - ((BANK) == FSMC_Bank1_NORSRAM2) || \ - ((BANK) == FSMC_Bank1_NORSRAM3) || \ - ((BANK) == FSMC_Bank1_NORSRAM4)) - -#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND)) - -#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -/** @defgroup NOR_SRAM_Controller - * @{ - */ - -/** @defgroup FSMC_Data_Address_Bus_Multiplexing - * @{ - */ - -#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) -#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) -#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ - ((MUX) == FSMC_DataAddressMux_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Memory_Type - * @{ - */ - -#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) -#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) -#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) -#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ - ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ - ((MEMORY) == FSMC_MemoryType_NOR)) - -/** - * @} - */ - -/** @defgroup FSMC_Data_Width - * @{ - */ - -#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) -#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ - ((WIDTH) == FSMC_MemoryDataWidth_16b)) - -/** - * @} - */ - -/** @defgroup FSMC_Burst_Access_Mode - * @{ - */ - -#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) -#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) -#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ - ((STATE) == FSMC_BurstAccessMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal_Polarity - * @{ - */ - -#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) -#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) -#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ - ((POLARITY) == FSMC_WaitSignalPolarity_High)) - -/** - * @} - */ - -/** @defgroup FSMC_Wrap_Mode - * @{ - */ - -#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) -#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) -#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ - ((MODE) == FSMC_WrapMode_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Timing - * @{ - */ - -#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) -#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ - ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) - -/** - * @} - */ - -/** @defgroup FSMC_Write_Operation - * @{ - */ - -#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) -#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) -#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ - ((OPERATION) == FSMC_WriteOperation_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal - * @{ - */ - -#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) -#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) -#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ - ((SIGNAL) == FSMC_WaitSignal_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Extended_Mode - * @{ - */ - -#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) -#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) - -#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ - ((MODE) == FSMC_ExtendedMode_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_Write_Burst - * @{ - */ - -#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) -#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) -#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ - ((BURST) == FSMC_WriteBurst_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Address_Setup_Time - * @{ - */ - -#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Address_Hold_Time - * @{ - */ - -#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Data_Setup_Time - * @{ - */ - -#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) - -/** - * @} - */ - -/** @defgroup FSMC_Bus_Turn_around_Duration - * @{ - */ - -#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_CLK_Division - * @{ - */ - -#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Data_Latency - * @{ - */ - -#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) - -/** - * @} - */ - -/** @defgroup FSMC_Access_Mode - * @{ - */ - -#define FSMC_AccessMode_A ((uint32_t)0x00000000) -#define FSMC_AccessMode_B ((uint32_t)0x10000000) -#define FSMC_AccessMode_C ((uint32_t)0x20000000) -#define FSMC_AccessMode_D ((uint32_t)0x30000000) -#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ - ((MODE) == FSMC_AccessMode_B) || \ - ((MODE) == FSMC_AccessMode_C) || \ - ((MODE) == FSMC_AccessMode_D)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup NAND_PCCARD_Controller - * @{ - */ - -/** @defgroup FSMC_Wait_feature - * @{ - */ - -#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) -#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) -#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ - ((FEATURE) == FSMC_Waitfeature_Enable)) - -/** - * @} - */ - - -/** @defgroup FSMC_ECC - * @{ - */ - -#define FSMC_ECC_Disable ((uint32_t)0x00000000) -#define FSMC_ECC_Enable ((uint32_t)0x00000040) -#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ - ((STATE) == FSMC_ECC_Enable)) - -/** - * @} - */ - -/** @defgroup FSMC_ECC_Page_Size - * @{ - */ - -#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) -#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) -#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) -#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) -#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) -#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) -#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_8192Bytes)) - -/** - * @} - */ - -/** @defgroup FSMC_TCLR_Setup_Time - * @{ - */ - -#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_TAR_Setup_Time - * @{ - */ - -#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Setup_Time - * @{ - */ - -#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Wait_Setup_Time - * @{ - */ - -#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Hold_Setup_Time - * @{ - */ - -#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_HiZ_Setup_Time - * @{ - */ - -#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) - -/** - * @} - */ - -/** @defgroup FSMC_Interrupt_sources - * @{ - */ - -#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) -#define FSMC_IT_Level ((uint32_t)0x00000010) -#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) -#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ - ((IT) == FSMC_IT_Level) || \ - ((IT) == FSMC_IT_FallingEdge)) -/** - * @} - */ - -/** @defgroup FSMC_Flags - * @{ - */ - -#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) -#define FSMC_FLAG_Level ((uint32_t)0x00000002) -#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) -#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) -#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ - ((FLAG) == FSMC_FLAG_Level) || \ - ((FLAG) == FSMC_FLAG_FallingEdge) || \ - ((FLAG) == FSMC_FLAG_FEMPT)) - -#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FSMC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Exported_Functions - * @{ - */ - -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); -void FSMC_NANDDeInit(uint32_t FSMC_Bank); -void FSMC_PCCARDDeInit(void); -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_PCCARDCmd(FunctionalState NewState); -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); -uint32_t FSMC_GetECC(uint32_t FSMC_Bank); -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_FSMC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_gpio.h b/example/libs_stm/inc/stm32f10x/stm32f10x_gpio.h deleted file mode 100644 index aff7a5c1d..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_gpio.h +++ /dev/null @@ -1,379 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_gpio.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the GPIO - * firmware library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_GPIO_H -#define __STM32F10x_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/** @defgroup GPIO_Exported_Types - * @{ - */ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF) || \ - ((PERIPH) == GPIOG)) - -/** - * @brief Output Maximum frequency selection - */ - -typedef enum -{ - GPIO_Speed_10MHz = 1, - GPIO_Speed_2MHz, - GPIO_Speed_50MHz -}GPIOSpeed_TypeDef; -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_10MHz) || ((SPEED) == GPIO_Speed_2MHz) || \ - ((SPEED) == GPIO_Speed_50MHz)) - -/** - * @brief Configuration Mode enumeration - */ - -typedef enum -{ GPIO_Mode_AIN = 0x0, - GPIO_Mode_IN_FLOATING = 0x04, - GPIO_Mode_IPD = 0x28, - GPIO_Mode_IPU = 0x48, - GPIO_Mode_Out_OD = 0x14, - GPIO_Mode_Out_PP = 0x10, - GPIO_Mode_AF_OD = 0x1C, - GPIO_Mode_AF_PP = 0x18 -}GPIOMode_TypeDef; - -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_AIN) || ((MODE) == GPIO_Mode_IN_FLOATING) || \ - ((MODE) == GPIO_Mode_IPD) || ((MODE) == GPIO_Mode_IPU) || \ - ((MODE) == GPIO_Mode_Out_OD) || ((MODE) == GPIO_Mode_Out_PP) || \ - ((MODE) == GPIO_Mode_AF_OD) || ((MODE) == GPIO_Mode_AF_PP)) - -/** - * @brief GPIO Init structure definition - */ - -typedef struct -{ - uint16_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ -}GPIO_InitTypeDef; - - -/** - * @brief Bit_SET and Bit_RESET enumeration - */ - -typedef enum -{ Bit_RESET = 0, - Bit_SET -}BitAction; - -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ - -#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ - -#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) - -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) - -/** - * @} - */ - -/** @defgroup GPIO_Remap_define - * @{ - */ - -#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Alternate Function mapping */ -#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /*!< I2C1 Alternate Function mapping */ -#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /*!< USART1 Alternate Function mapping */ -#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /*!< USART2 Alternate Function mapping */ -#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /*!< USART3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /*!< USART3 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /*!< TIM1 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /*!< TIM1 Full Alternate Function mapping */ -#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /*!< TIM2 Partial1 Alternate Function mapping */ -#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /*!< TIM2 Partial2 Alternate Function mapping */ -#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /*!< TIM2 Full Alternate Function mapping */ -#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /*!< TIM3 Partial Alternate Function mapping */ -#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /*!< TIM3 Full Alternate Function mapping */ -#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /*!< TIM4 Alternate Function mapping */ -#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /*!< CAN1 Alternate Function mapping */ -#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /*!< CAN1 Alternate Function mapping */ -#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /*!< PD01 Alternate Function mapping */ -#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /*!< LSI connected to TIM5 Channel4 input capture for calibration */ -#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /*!< ADC1 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /*!< ADC1 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /*!< ADC2 External Trigger Injected Conversion remapping */ -#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /*!< ADC2 External Trigger Regular Conversion remapping */ -#define GPIO_Remap_ETH ((uint32_t)0x00200020) /*!< Ethernet remapping (only for Connectivity line devices) */ -#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /*!< CAN2 remapping (only for Connectivity line devices) */ -#define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /*!< Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ -#define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /*!< JTAG-DP Disabled and SW-DP Enabled */ -#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /*!< Full SWJ Disabled (JTAG-DP + SW-DP) */ -#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /*!< SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ -#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /*!< Ethernet PTP output or USB OTG SOF (Start of Frame) connected - to TIM2 Internal Trigger 1 for calibration - (only for Connectivity line devices) */ -#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /*!< Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ - -#define GPIO_Remap_TIM15 ((uint32_t)0x80000001) /*!< TIM15 Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_TIM16 ((uint32_t)0x80000002) /*!< TIM16 Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_TIM17 ((uint32_t)0x80000004) /*!< TIM17 Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_CEC ((uint32_t)0x80000008) /*!< CEC Alternate Function mapping (only for Value line devices) */ -#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /*!< TIM1 DMA requests mapping (only for Value line devices) */ - -#define GPIO_Remap_TIM9 ((uint32_t)0x80000020) /*!< TIM9 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM10 ((uint32_t)0x80000040) /*!< TIM10 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM11 ((uint32_t)0x80000080) /*!< TIM11 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM13 ((uint32_t)0x80000100) /*!< TIM13 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_TIM14 ((uint32_t)0x80000200) /*!< TIM14 Alternate Function mapping (only for XL-density devices) */ -#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /*!< FSMC_NADV Alternate Function mapping (only for XL-density devices) */ - - -#define IS_GPIO_REMAP(REMAP) (((REMAP) == GPIO_Remap_SPI1) || ((REMAP) == GPIO_Remap_I2C1) || \ - ((REMAP) == GPIO_Remap_USART1) || ((REMAP) == GPIO_Remap_USART2) || \ - ((REMAP) == GPIO_PartialRemap_USART3) || ((REMAP) == GPIO_FullRemap_USART3) || \ - ((REMAP) == GPIO_PartialRemap_TIM1) || ((REMAP) == GPIO_FullRemap_TIM1) || \ - ((REMAP) == GPIO_PartialRemap1_TIM2) || ((REMAP) == GPIO_PartialRemap2_TIM2) || \ - ((REMAP) == GPIO_FullRemap_TIM2) || ((REMAP) == GPIO_PartialRemap_TIM3) || \ - ((REMAP) == GPIO_FullRemap_TIM3) || ((REMAP) == GPIO_Remap_TIM4) || \ - ((REMAP) == GPIO_Remap1_CAN1) || ((REMAP) == GPIO_Remap2_CAN1) || \ - ((REMAP) == GPIO_Remap_PD01) || ((REMAP) == GPIO_Remap_TIM5CH4_LSI) || \ - ((REMAP) == GPIO_Remap_ADC1_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC1_ETRGREG) || \ - ((REMAP) == GPIO_Remap_ADC2_ETRGINJ) ||((REMAP) == GPIO_Remap_ADC2_ETRGREG) || \ - ((REMAP) == GPIO_Remap_ETH) ||((REMAP) == GPIO_Remap_CAN2) || \ - ((REMAP) == GPIO_Remap_SWJ_NoJTRST) || ((REMAP) == GPIO_Remap_SWJ_JTAGDisable) || \ - ((REMAP) == GPIO_Remap_SWJ_Disable)|| ((REMAP) == GPIO_Remap_SPI3) || \ - ((REMAP) == GPIO_Remap_TIM2ITR1_PTP_SOF) || ((REMAP) == GPIO_Remap_PTP_PPS) || \ - ((REMAP) == GPIO_Remap_TIM15) || ((REMAP) == GPIO_Remap_TIM16) || \ - ((REMAP) == GPIO_Remap_TIM17) || ((REMAP) == GPIO_Remap_CEC) || \ - ((REMAP) == GPIO_Remap_TIM1_DMA) || ((REMAP) == GPIO_Remap_TIM9) || \ - ((REMAP) == GPIO_Remap_TIM10) || ((REMAP) == GPIO_Remap_TIM11) || \ - ((REMAP) == GPIO_Remap_TIM13) || ((REMAP) == GPIO_Remap_TIM14) || \ - ((REMAP) == GPIO_Remap_FSMC_NADV)) - -/** - * @} - */ - -/** @defgroup GPIO_Port_Sources - * @{ - */ - -#define GPIO_PortSourceGPIOA ((uint8_t)0x00) -#define GPIO_PortSourceGPIOB ((uint8_t)0x01) -#define GPIO_PortSourceGPIOC ((uint8_t)0x02) -#define GPIO_PortSourceGPIOD ((uint8_t)0x03) -#define GPIO_PortSourceGPIOE ((uint8_t)0x04) -#define GPIO_PortSourceGPIOF ((uint8_t)0x05) -#define GPIO_PortSourceGPIOG ((uint8_t)0x06) -#define IS_GPIO_EVENTOUT_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOE)) - -#define IS_GPIO_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == GPIO_PortSourceGPIOA) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOB) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOC) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOD) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOE) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOF) || \ - ((PORTSOURCE) == GPIO_PortSourceGPIOG)) - -/** - * @} - */ - -/** @defgroup GPIO_Pin_sources - * @{ - */ - -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) - -/** - * @} - */ - -/** @defgroup Ethernet_Media_Interface - * @{ - */ -#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) -#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) - -#define IS_GPIO_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == GPIO_ETH_MediaInterface_MII) || \ - ((INTERFACE) == GPIO_ETH_MediaInterface_RMII)) - -/** - * @} - */ -/** - * @} - */ - -/** @defgroup GPIO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions - * @{ - */ - -void GPIO_DeInit(GPIO_TypeDef* GPIOx); -void GPIO_AFIODeInit(void); -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_EventOutputCmd(FunctionalState NewState); -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_GPIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_i2c.h b/example/libs_stm/inc/stm32f10x/stm32f10x_i2c.h deleted file mode 100644 index d9c9346bc..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_i2c.h +++ /dev/null @@ -1,670 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_i2c.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the I2C firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_I2C_H -#define __STM32F10x_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/** @defgroup I2C_Exported_Types - * @{ - */ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -}I2C_InitTypeDef; - -/** - * @} - */ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2)) -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_duty_cycle_in_fast_mode - * @{ - */ - -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ - ((CYCLE) == I2C_DutyCycle_2)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) -#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ - ((STATE) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_DR ((uint8_t)0x10) -#define I2C_Register_SR1 ((uint8_t)0x14) -#define I2C_Register_SR2 ((uint8_t)0x18) -#define I2C_Register_CCR ((uint8_t)0x1C) -#define I2C_Register_TRISE ((uint8_t)0x20) -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_DR) || \ - ((REGISTER) == I2C_Register_SR1) || \ - ((REGISTER) == I2C_Register_SR2) || \ - ((REGISTER) == I2C_Register_CCR) || \ - ((REGISTER) == I2C_Register_TRISE)) -/** - * @} - */ - -/** @defgroup I2C_SMBus_alert_pin_level - * @{ - */ - -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) -#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ - ((ALERT) == I2C_SMBusAlert_High)) -/** - * @} - */ - -/** @defgroup I2C_PEC_position - * @{ - */ - -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ - ((POSITION) == I2C_PECPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ - ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ - ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ - ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -/** - * @brief SR2 register flags - */ - -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/** - * @brief SR1 register flags - */ - -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ - ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ - ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ - ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ - ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ - ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ - ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ - ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_SB)) -/** - * @} - */ - -/** @defgroup I2C_Events - * @{ - */ - -/*======================================== - - I2C Master Events (Events grouped in order of communication) - ==========================================*/ -/** - * @brief Communication start - * - * After sending the START condition (I2C_GenerateSTART() function) the master - * has to wait for this event. It means that the Start condition has been correctly - * released on the I2C bus (the bus is free, no other devices is communicating). - * - */ -/* --EV5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/** - * @brief Address Acknowledge - * - * After checking on EV5 (start condition correctly released on the bus), the - * master sends the address of the slave(s) with which it will communicate - * (I2C_Send7bitAddress() function, it also determines the direction of the communication: - * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will - * be set: - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (just after generating the START - * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() - * function). Then master should wait on EV9. It means that the 10-bit addressing - * header has been correctly sent on the bus. Then master should send the second part of - * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master - * should wait for event EV6. - * - */ - -/* --EV6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/* --EV9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/** - * @brief Communication events - * - * If a communication is established (START condition generated and slave address - * acknowledged) then the master has to check on one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EV7 then to read - * the data received from the slave (I2C_ReceiveData() function). - * - * 2) Master Transmitter mode: The master has to send data (I2C_SendData() - * function) then to wait on event EV8 or EV8_2. - * These two events are similar: - * - EV8 means that the data has been written in the data register and is - * being shifted out. - * - EV8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EV8 is sufficient for the application. - * Using EV8_2 leads to a slower communication but ensure more reliable test. - * EV8_2 is also more suitable than EV8 for testing on the last data transmission - * (before Stop condition generation). - * - * @note In case the user software does not guarantee that this event EV7 is - * managed before the current byte end of transfer, then user may check on EV7 - * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Master RECEIVER mode -----------------------------*/ -/* --EV7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master TRANSMITTER mode --------------------------*/ -/* --EV8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* --EV8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - - -/*======================================== - - I2C Slave Events (Events grouped in order of communication) - ==========================================*/ - -/** - * @brief Communication start events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a Start condition on the bus (generated by master - * device) followed by the peripheral address. The peripheral generates an ACK - * condition on the bus (if the acknowledge feature is enabled through function - * I2C_AcknowledgeConfig()) and the events listed above are set : - * - * 1) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * 2) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * 3) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* --EV1 (all the events below are variants of EV1) */ -/* 1) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* 2) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* 3) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/** - * @brief Communication events - * - * Wait on one of these events when EV1 has already been checked and: - * - * - Slave RECEIVER mode: - * - EV2: When the application is expecting a data byte to be received. - * - EV4: When the application is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EV3: When a byte has been transmitted by the slave and the application is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be - * used when the user software doesn't guarantee the EV3 is managed before the - * current byte end of tranfer. - * - EV3_2: When the master sends a NACK in order to tell slave that data transmission - * shall end (before sending the STOP condition). In this case slave has to stop sending - * data bytes and expect a Stop condition on the bus. - * - * @note In case the user software does not guarantee that the event EV2 is - * managed before the current byte end of transfer, then user may check on EV2 - * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Slave RECEIVER mode --------------------------*/ -/* --EV2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* --EV4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave TRANSMITTER mode -----------------------*/ -/* --EV3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/* --EV3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - -/*=========================== End of Events Description ==========================================*/ - -#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ - ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ - ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) -/** - * @} - */ - -/** @defgroup I2C_clock_speed - * @{ - */ - -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup I2C_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions - * @{ - */ - -void I2C_DeInit(I2C_TypeDef* I2Cx); -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); - -/** - * @brief - **************************************************************************************** - * - * I2C State Monitoring Functions - * - **************************************************************************************** - * This I2C driver provides three different ways for I2C state monitoring - * depending on the application requirements and constraints: - * - * - * 1) Basic state monitoring: - * Using I2C_CheckEvent() function: - * It compares the status registers (SR1 and SR2) content to a given event - * (can be the combination of one or more flags). - * It returns SUCCESS if the current status includes the given flags - * and returns ERROR if one or more flags are missing in the current status. - * - When to use: - * - This function is suitable for most applications as well as for startup - * activity since the events are fully described in the product reference manual - * (RM0008). - * - It is also suitable for users who need to define their own events. - * - Limitations: - * - If an error occurs (ie. error flags are set besides to the monitored flags), - * the I2C_CheckEvent() function may return SUCCESS despite the communication - * hold or corrupted real state. - * In this case, it is advised to use error interrupts to monitor the error - * events and handle them in the interrupt IRQ handler. - * - * @note - * For error management, it is advised to use the following functions: - * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs. - * Where x is the peripheral instance (I2C1, I2C2 ...) - * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() - * in order to determine which error occured. - * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - * and/or I2C_GenerateStop() in order to clear the error flag and source, - * and return to correct communication status. - * - * - * 2) Advanced state monitoring: - * Using the function I2C_GetLastEvent() which returns the image of both status - * registers in a single word (uint32_t) (Status Register 2 value is shifted left - * by 16 bits and concatenated to Status Register 1). - * - When to use: - * - This function is suitable for the same applications above but it allows to - * overcome the limitations of I2C_GetFlagStatus() function (see below). - * The returned value could be compared to events already defined in the - * library (stm32f10x_i2c.h) or to custom values defined by user. - * - This function is suitable when multiple flags are monitored at the same time. - * - At the opposite of I2C_CheckEvent() function, this function allows user to - * choose when an event is accepted (when all events flags are set and no - * other flags are set or just when the needed flags are set like - * I2C_CheckEvent() function). - * - Limitations: - * - User may need to define his own events. - * - Same remark concerning the error management is applicable for this - * function if user decides to check only regular communication flags (and - * ignores error flags). - * - * - * 3) Flag-based state monitoring: - * Using the function I2C_GetFlagStatus() which simply returns the status of - * one single flag (ie. I2C_FLAG_RXNE ...). - * - When to use: - * - This function could be used for specific applications or in debug phase. - * - It is suitable when only one flag checking is needed (most I2C events - * are monitored through multiple flags). - * - Limitations: - * - When calling this function, the Status register is accessed. Some flags are - * cleared when the status register is accessed. So checking the status - * of one Flag, may clear other ones. - * - Function may need to be called twice or more in order to monitor one - * single event. - * - */ - -/** - * - * 1) Basic state monitoring - ******************************************************************************* - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/** - * - * 2) Advanced state monitoring - ******************************************************************************* - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/** - * - * 3) Flag-based state monitoring - ******************************************************************************* - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -/** - * - ******************************************************************************* - */ - -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_I2C_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_iwdg.h b/example/libs_stm/inc/stm32f10x/stm32f10x_iwdg.h deleted file mode 100644 index f9a26bf18..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_iwdg.h +++ /dev/null @@ -1,139 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_iwdg.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the IWDG - * firmware library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_IWDG_H -#define __STM32F10x_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup IWDG - * @{ - */ - -/** @defgroup IWDG_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Constants - * @{ - */ - -/** @defgroup IWDG_WriteAccess - * @{ - */ - -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) -#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ - ((ACCESS) == IWDG_WriteAccess_Disable)) -/** - * @} - */ - -/** @defgroup IWDG_prescaler - * @{ - */ - -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) -#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ - ((PRESCALER) == IWDG_Prescaler_8) || \ - ((PRESCALER) == IWDG_Prescaler_16) || \ - ((PRESCALER) == IWDG_Prescaler_32) || \ - ((PRESCALER) == IWDG_Prescaler_64) || \ - ((PRESCALER) == IWDG_Prescaler_128)|| \ - ((PRESCALER) == IWDG_Prescaler_256)) -/** - * @} - */ - -/** @defgroup IWDG_Flag - * @{ - */ - -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) -#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) -#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Exported_Functions - * @{ - */ - -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); -void IWDG_Enable(void); -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_IWDG_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_pwr.h b/example/libs_stm/inc/stm32f10x/stm32f10x_pwr.h deleted file mode 100644 index ce168da23..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_pwr.h +++ /dev/null @@ -1,155 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_pwr.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_PWR_H -#define __STM32F10x_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/** @defgroup PWR_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PVD_detection_level - * @{ - */ - -#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) -#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) -#define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) -#define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) -#define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) -#define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) -#define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) -#define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ - ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ - ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ - ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) -/** - * @} - */ - -/** @defgroup Regulator_state_is_STOP_mode - * @{ - */ - -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower ((uint32_t)0x00000001) -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ - ((REGULATOR) == PWR_Regulator_LowPower)) -/** - * @} - */ - -/** @defgroup STOP_mode_entry - * @{ - */ - -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) - -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ - -#define PWR_FLAG_WU ((uint32_t)0x00000001) -#define PWR_FLAG_SB ((uint32_t)0x00000002) -#define PWR_FLAG_PVDO ((uint32_t)0x00000004) -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO)) - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions - * @{ - */ - -void PWR_DeInit(void); -void PWR_BackupAccessCmd(FunctionalState NewState); -void PWR_PVDCmd(FunctionalState NewState); -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_WakeUpPinCmd(FunctionalState NewState); -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_PWR_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_rcc.h b/example/libs_stm/inc/stm32f10x/stm32f10x_rcc.h deleted file mode 100644 index 19afe3e45..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_rcc.h +++ /dev/null @@ -1,726 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rcc.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the RCC firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_RCC_H -#define __STM32F10x_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/** @defgroup RCC_Exported_Types - * @{ - */ - -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ - uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ -}RCC_ClocksTypeDef; - -/** - * @} - */ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup HSE_configuration - * @{ - */ - -#define RCC_HSE_OFF ((uint32_t)0x00000000) -#define RCC_HSE_ON ((uint32_t)0x00010000) -#define RCC_HSE_Bypass ((uint32_t)0x00040000) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) - -/** - * @} - */ - -/** @defgroup PLL_entry_clock_source - * @{ - */ - -#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) - -#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_CL) - #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) - #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) - #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ - ((SOURCE) == RCC_PLLSource_HSE_Div2)) -#else - #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) - #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ - ((SOURCE) == RCC_PLLSource_PREDIV1)) -#endif /* STM32F10X_CL */ - -/** - * @} - */ - -/** @defgroup PLL_multiplication_factor - * @{ - */ -#ifndef STM32F10X_CL - #define RCC_PLLMul_2 ((uint32_t)0x00000000) - #define RCC_PLLMul_3 ((uint32_t)0x00040000) - #define RCC_PLLMul_4 ((uint32_t)0x00080000) - #define RCC_PLLMul_5 ((uint32_t)0x000C0000) - #define RCC_PLLMul_6 ((uint32_t)0x00100000) - #define RCC_PLLMul_7 ((uint32_t)0x00140000) - #define RCC_PLLMul_8 ((uint32_t)0x00180000) - #define RCC_PLLMul_9 ((uint32_t)0x001C0000) - #define RCC_PLLMul_10 ((uint32_t)0x00200000) - #define RCC_PLLMul_11 ((uint32_t)0x00240000) - #define RCC_PLLMul_12 ((uint32_t)0x00280000) - #define RCC_PLLMul_13 ((uint32_t)0x002C0000) - #define RCC_PLLMul_14 ((uint32_t)0x00300000) - #define RCC_PLLMul_15 ((uint32_t)0x00340000) - #define RCC_PLLMul_16 ((uint32_t)0x00380000) - #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ - ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ - ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ - ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ - ((MUL) == RCC_PLLMul_16)) - -#else - #define RCC_PLLMul_4 ((uint32_t)0x00080000) - #define RCC_PLLMul_5 ((uint32_t)0x000C0000) - #define RCC_PLLMul_6 ((uint32_t)0x00100000) - #define RCC_PLLMul_7 ((uint32_t)0x00140000) - #define RCC_PLLMul_8 ((uint32_t)0x00180000) - #define RCC_PLLMul_9 ((uint32_t)0x001C0000) - #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) - - #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ - ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ - ((MUL) == RCC_PLLMul_6_5)) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup PREDIV1_division_factor - * @{ - */ -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) - #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) - #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) - #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) - #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) - #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) - #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) - #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) - #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) - #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) - #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) - #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) - #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) - #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) - #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) - #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) - #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) - - #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ - ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ - ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ - ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ - ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ - ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ - ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ - ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) -#endif -/** - * @} - */ - - -/** @defgroup PREDIV1_clock_source - * @{ - */ -#ifdef STM32F10X_CL -/* PREDIV1 clock source (for STM32 connectivity line devices) */ - #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) - #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) - - #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ - ((SOURCE) == RCC_PREDIV1_Source_PLL2)) -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) -/* PREDIV1 clock source (for STM32 Value line devices) */ - #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) - - #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) -#endif -/** - * @} - */ - -#ifdef STM32F10X_CL -/** @defgroup PREDIV2_division_factor - * @{ - */ - - #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) - #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) - #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) - #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) - #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) - #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) - #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) - #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) - #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) - #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) - #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) - #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) - #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) - #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) - #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) - #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) - - #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ - ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ - ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ - ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ - ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ - ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ - ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ - ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) -/** - * @} - */ - - -/** @defgroup PLL2_multiplication_factor - * @{ - */ - - #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) - #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) - #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) - #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) - #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) - #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) - #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) - #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) - #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) - - #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ - ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ - ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ - ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ - ((MUL) == RCC_PLL2Mul_20)) -/** - * @} - */ - - -/** @defgroup PLL3_multiplication_factor - * @{ - */ - - #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) - #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) - #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) - #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) - #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) - #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) - #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) - #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) - #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) - - #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ - ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ - ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ - ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ - ((MUL) == RCC_PLL3Mul_20)) -/** - * @} - */ - -#endif /* STM32F10X_CL */ - - -/** @defgroup System_clock_source - * @{ - */ - -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup AHB_clock_source - * @{ - */ - -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup APB1_APB2_clock_source - * @{ - */ - -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00000400) -#define RCC_HCLK_Div4 ((uint32_t)0x00000500) -#define RCC_HCLK_Div8 ((uint32_t)0x00000600) -#define RCC_HCLK_Div16 ((uint32_t)0x00000700) -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_Interrupt_source - * @{ - */ - -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_CSS ((uint8_t)0x80) - -#ifndef STM32F10X_CL - #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) - #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) - #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) -#else - #define RCC_IT_PLL2RDY ((uint8_t)0x20) - #define RCC_IT_PLL3RDY ((uint8_t)0x40) - #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) - #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ - ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) - #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) -#endif /* STM32F10X_CL */ - - -/** - * @} - */ - -#ifndef STM32F10X_CL -/** @defgroup USB_Device_clock_source - * @{ - */ - - #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) - #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) - - #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ - ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) -/** - * @} - */ -#else -/** @defgroup USB_OTG_FS_clock_source - * @{ - */ - #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) - #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) - - #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ - ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) -/** - * @} - */ -#endif /* STM32F10X_CL */ - - -#ifdef STM32F10X_CL -/** @defgroup I2S2_clock_source - * @{ - */ - #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) - #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) - - #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ - ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) -/** - * @} - */ - -/** @defgroup I2S3_clock_source - * @{ - */ - #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) - #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) - - #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ - ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) -/** - * @} - */ -#endif /* STM32F10X_CL */ - - -/** @defgroup ADC_clock_source - * @{ - */ - -#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) -#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) -#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) -#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) -#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ - ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) -/** - * @} - */ - -/** @defgroup LSE_configuration - * @{ - */ - -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RTC_clock_source - * @{ - */ - -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) -/** - * @} - */ - -/** @defgroup AHB_peripheral - * @{ - */ - -#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) -#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) -#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) -#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) -#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) - -#ifndef STM32F10X_CL - #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) - #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) - #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) -#else - #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) - #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) - #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) - #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) - - #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) - #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) -#endif /* STM32F10X_CL */ -/** - * @} - */ - -/** @defgroup APB2_peripheral - * @{ - */ - -#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) -#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) -#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) -#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) -#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) -#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) -#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) -#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) -#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) -#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) -#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) -#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) -#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) -#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) -#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) - -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup APB1_peripheral - * @{ - */ - -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) -#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) -#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_USB ((uint32_t)0x00800000) -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) - -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup Clock_source_to_output_on_MCO_pin - * @{ - */ - -#define RCC_MCO_NoClock ((uint8_t)0x00) -#define RCC_MCO_SYSCLK ((uint8_t)0x04) -#define RCC_MCO_HSI ((uint8_t)0x05) -#define RCC_MCO_HSE ((uint8_t)0x06) -#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) - -#ifndef STM32F10X_CL - #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ - ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ - ((MCO) == RCC_MCO_PLLCLK_Div2)) -#else - #define RCC_MCO_PLL2CLK ((uint8_t)0x08) - #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) - #define RCC_MCO_XT1 ((uint8_t)0x0A) - #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) - - #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ - ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ - ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ - ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ - ((MCO) == RCC_MCO_PLL3CLK)) -#endif /* STM32F10X_CL */ - -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ - -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) - -#ifndef STM32F10X_CL - #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ - ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ - ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ - ((FLAG) == RCC_FLAG_LPWRRST)) -#else - #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) - #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) - #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ - ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ - ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ - ((FLAG) == RCC_FLAG_LPWRRST)) -#endif /* STM32F10X_CL */ - -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RCC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions - * @{ - */ - -void RCC_DeInit(void); -void RCC_HSEConfig(uint32_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); -void RCC_PLLCmd(FunctionalState NewState); - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) - void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); -#endif - -#ifdef STM32F10X_CL - void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); - void RCC_PLL2Config(uint32_t RCC_PLL2Mul); - void RCC_PLL2Cmd(FunctionalState NewState); - void RCC_PLL3Config(uint32_t RCC_PLL3Mul); - void RCC_PLL3Cmd(FunctionalState NewState); -#endif /* STM32F10X_CL */ - -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); - -#ifndef STM32F10X_CL - void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); -#else - void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); -#endif /* STM32F10X_CL */ - -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); - -#ifdef STM32F10X_CL - void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); - void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); -#endif /* STM32F10X_CL */ - -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); - -#ifdef STM32F10X_CL -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -#endif /* STM32F10X_CL */ - -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCOConfig(uint8_t RCC_MCO); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_RCC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_rtc.h b/example/libs_stm/inc/stm32f10x/stm32f10x_rtc.h deleted file mode 100644 index 833f2fea1..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_rtc.h +++ /dev/null @@ -1,134 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rtc.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_RTC_H -#define __STM32F10x_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/** @defgroup RTC_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - -/** @defgroup RTC_interrupts_define - * @{ - */ - -#define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ -#define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ -#define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ -#define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ - ((IT) == RTC_IT_SEC)) -/** - * @} - */ - -/** @defgroup RTC_interrupts_flags - * @{ - */ - -#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ -#define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ -#define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ -#define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ -#define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ -#define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ - ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ - ((FLAG) == RTC_FLAG_SEC)) -#define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions - * @{ - */ - -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); -void RTC_EnterConfigMode(void); -void RTC_ExitConfigMode(void); -uint32_t RTC_GetCounter(void); -void RTC_SetCounter(uint32_t CounterValue); -void RTC_SetPrescaler(uint32_t PrescalerValue); -void RTC_SetAlarm(uint32_t AlarmValue); -uint32_t RTC_GetDivider(void); -void RTC_WaitForLastTask(void); -void RTC_WaitForSynchro(void); -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); -void RTC_ClearFlag(uint16_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint16_t RTC_IT); -void RTC_ClearITPendingBit(uint16_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_RTC_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_sdio.h b/example/libs_stm/inc/stm32f10x/stm32f10x_sdio.h deleted file mode 100644 index a6c62cd8b..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_sdio.h +++ /dev/null @@ -1,530 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_sdio.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the SDIO firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_SDIO_H -#define __STM32F10x_SDIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SDIO - * @{ - */ - -/** @defgroup SDIO_Exported_Types - * @{ - */ - -typedef struct -{ - uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SDIO_Clock_Edge */ - - uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is - enabled or disabled. - This parameter can be a value of @ref SDIO_Clock_Bypass */ - - uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or - disabled when the bus is idle. - This parameter can be a value of @ref SDIO_Clock_Power_Save */ - - uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. - This parameter can be a value of @ref SDIO_Bus_Wide */ - - uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ - - uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. - This parameter can be a value between 0x00 and 0xFF. */ - -} SDIO_InitTypeDef; - -typedef struct -{ - uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent - to a card as part of a command message. If a command - contains an argument, it must be loaded into this register - before writing the command to the command register */ - - uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ - - uint32_t SDIO_Response; /*!< Specifies the SDIO response type. - This parameter can be a value of @ref SDIO_Response_Type */ - - uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. - This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ - - uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_CPSM_State */ -} SDIO_CmdInitTypeDef; - -typedef struct -{ - uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ - - uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ - - uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. - This parameter can be a value of @ref SDIO_Data_Block_Size */ - - uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer - is a read or write. - This parameter can be a value of @ref SDIO_Transfer_Direction */ - - uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDIO_Transfer_Type */ - - uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_DPSM_State */ -} SDIO_DataInitTypeDef; - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Constants - * @{ - */ - -/** @defgroup SDIO_Clock_Edge - * @{ - */ - -#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) -#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) -#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ - ((EDGE) == SDIO_ClockEdge_Falling)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Bypass - * @{ - */ - -#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) -#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ - ((BYPASS) == SDIO_ClockBypass_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Power_Save - * @{ - */ - -#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) -#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) -#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ - ((SAVE) == SDIO_ClockPowerSave_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Bus_Wide - * @{ - */ - -#define SDIO_BusWide_1b ((uint32_t)0x00000000) -#define SDIO_BusWide_4b ((uint32_t)0x00000800) -#define SDIO_BusWide_8b ((uint32_t)0x00001000) -#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ - ((WIDE) == SDIO_BusWide_8b)) - -/** - * @} - */ - -/** @defgroup SDIO_Hardware_Flow_Control - * @{ - */ - -#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) -#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) -#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ - ((CONTROL) == SDIO_HardwareFlowControl_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Power_State - * @{ - */ - -#define SDIO_PowerState_OFF ((uint32_t)0x00000000) -#define SDIO_PowerState_ON ((uint32_t)0x00000003) -#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) -/** - * @} - */ - - -/** @defgroup SDIO_Interrupt_soucres - * @{ - */ - -#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) -#define SDIO_IT_CMDREND ((uint32_t)0x00000040) -#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) -#define SDIO_IT_DATAEND ((uint32_t)0x00000100) -#define SDIO_IT_STBITERR ((uint32_t)0x00000200) -#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) -#define SDIO_IT_CMDACT ((uint32_t)0x00000800) -#define SDIO_IT_TXACT ((uint32_t)0x00001000) -#define SDIO_IT_RXACT ((uint32_t)0x00002000) -#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) -#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) -#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) -#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) -/** - * @} - */ - -/** @defgroup SDIO_Command_Index - * @{ - */ - -#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) -/** - * @} - */ - -/** @defgroup SDIO_Response_Type - * @{ - */ - -#define SDIO_Response_No ((uint32_t)0x00000000) -#define SDIO_Response_Short ((uint32_t)0x00000040) -#define SDIO_Response_Long ((uint32_t)0x000000C0) -#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ - ((RESPONSE) == SDIO_Response_Short) || \ - ((RESPONSE) == SDIO_Response_Long)) -/** - * @} - */ - -/** @defgroup SDIO_Wait_Interrupt_State - * @{ - */ - -#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ -#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ -#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ -#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ - ((WAIT) == SDIO_Wait_Pend)) -/** - * @} - */ - -/** @defgroup SDIO_CPSM_State - * @{ - */ - -#define SDIO_CPSM_Disable ((uint32_t)0x00000000) -#define SDIO_CPSM_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Response_Registers - * @{ - */ - -#define SDIO_RESP1 ((uint32_t)0x00000000) -#define SDIO_RESP2 ((uint32_t)0x00000004) -#define SDIO_RESP3 ((uint32_t)0x00000008) -#define SDIO_RESP4 ((uint32_t)0x0000000C) -#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ - ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) -/** - * @} - */ - -/** @defgroup SDIO_Data_Length - * @{ - */ - -#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) -/** - * @} - */ - -/** @defgroup SDIO_Data_Block_Size - * @{ - */ - -#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) -#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) -#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) -#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) -#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) -#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) -#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) -#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) -#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) -#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) -#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) -#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) -#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) -#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) -#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) -#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ - ((SIZE) == SDIO_DataBlockSize_2b) || \ - ((SIZE) == SDIO_DataBlockSize_4b) || \ - ((SIZE) == SDIO_DataBlockSize_8b) || \ - ((SIZE) == SDIO_DataBlockSize_16b) || \ - ((SIZE) == SDIO_DataBlockSize_32b) || \ - ((SIZE) == SDIO_DataBlockSize_64b) || \ - ((SIZE) == SDIO_DataBlockSize_128b) || \ - ((SIZE) == SDIO_DataBlockSize_256b) || \ - ((SIZE) == SDIO_DataBlockSize_512b) || \ - ((SIZE) == SDIO_DataBlockSize_1024b) || \ - ((SIZE) == SDIO_DataBlockSize_2048b) || \ - ((SIZE) == SDIO_DataBlockSize_4096b) || \ - ((SIZE) == SDIO_DataBlockSize_8192b) || \ - ((SIZE) == SDIO_DataBlockSize_16384b)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Direction - * @{ - */ - -#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) -#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) -#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ - ((DIR) == SDIO_TransferDir_ToSDIO)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Type - * @{ - */ - -#define SDIO_TransferMode_Block ((uint32_t)0x00000000) -#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) -#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ - ((MODE) == SDIO_TransferMode_Block)) -/** - * @} - */ - -/** @defgroup SDIO_DPSM_State - * @{ - */ - -#define SDIO_DPSM_Disable ((uint32_t)0x00000000) -#define SDIO_DPSM_Enable ((uint32_t)0x00000001) -#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Flags - * @{ - */ - -#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) -#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) -#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) -#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) -#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) -#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) -#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) -#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) -#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) -#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) -#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) -#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) -#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_TXUNDERR) || \ - ((FLAG) == SDIO_FLAG_RXOVERR) || \ - ((FLAG) == SDIO_FLAG_CMDREND) || \ - ((FLAG) == SDIO_FLAG_CMDSENT) || \ - ((FLAG) == SDIO_FLAG_DATAEND) || \ - ((FLAG) == SDIO_FLAG_STBITERR) || \ - ((FLAG) == SDIO_FLAG_DBCKEND) || \ - ((FLAG) == SDIO_FLAG_CMDACT) || \ - ((FLAG) == SDIO_FLAG_TXACT) || \ - ((FLAG) == SDIO_FLAG_RXACT) || \ - ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOF) || \ - ((FLAG) == SDIO_FLAG_RXFIFOF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOE) || \ - ((FLAG) == SDIO_FLAG_TXDAVL) || \ - ((FLAG) == SDIO_FLAG_RXDAVL) || \ - ((FLAG) == SDIO_FLAG_SDIOIT) || \ - ((FLAG) == SDIO_FLAG_CEATAEND)) - -#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) - -#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ - ((IT) == SDIO_IT_DCRCFAIL) || \ - ((IT) == SDIO_IT_CTIMEOUT) || \ - ((IT) == SDIO_IT_DTIMEOUT) || \ - ((IT) == SDIO_IT_TXUNDERR) || \ - ((IT) == SDIO_IT_RXOVERR) || \ - ((IT) == SDIO_IT_CMDREND) || \ - ((IT) == SDIO_IT_CMDSENT) || \ - ((IT) == SDIO_IT_DATAEND) || \ - ((IT) == SDIO_IT_STBITERR) || \ - ((IT) == SDIO_IT_DBCKEND) || \ - ((IT) == SDIO_IT_CMDACT) || \ - ((IT) == SDIO_IT_TXACT) || \ - ((IT) == SDIO_IT_RXACT) || \ - ((IT) == SDIO_IT_TXFIFOHE) || \ - ((IT) == SDIO_IT_RXFIFOHF) || \ - ((IT) == SDIO_IT_TXFIFOF) || \ - ((IT) == SDIO_IT_RXFIFOF) || \ - ((IT) == SDIO_IT_TXFIFOE) || \ - ((IT) == SDIO_IT_RXFIFOE) || \ - ((IT) == SDIO_IT_TXDAVL) || \ - ((IT) == SDIO_IT_RXDAVL) || \ - ((IT) == SDIO_IT_SDIOIT) || \ - ((IT) == SDIO_IT_CEATAEND)) - -#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup SDIO_Read_Wait_Mode - * @{ - */ - -#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) -#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) -#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ - ((MODE) == SDIO_ReadWaitMode_DATA2)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Exported_Functions - * @{ - */ - -void SDIO_DeInit(void); -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_ClockCmd(FunctionalState NewState); -void SDIO_SetPowerState(uint32_t SDIO_PowerState); -uint32_t SDIO_GetPowerState(void); -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); -void SDIO_DMACmd(FunctionalState NewState); -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); -uint8_t SDIO_GetCommandResponse(void); -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -uint32_t SDIO_GetDataCounter(void); -uint32_t SDIO_ReadData(void); -void SDIO_WriteData(uint32_t Data); -uint32_t SDIO_GetFIFOCount(void); -void SDIO_StartSDIOReadWait(FunctionalState NewState); -void SDIO_StopSDIOReadWait(FunctionalState NewState); -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); -void SDIO_SetSDIOOperation(FunctionalState NewState); -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); -void SDIO_CommandCompletionCmd(FunctionalState NewState); -void SDIO_CEATAITCmd(FunctionalState NewState); -void SDIO_SendCEATACmd(FunctionalState NewState); -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); -void SDIO_ClearFlag(uint32_t SDIO_FLAG); -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); -void SDIO_ClearITPendingBit(uint32_t SDIO_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_SDIO_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_spi.h b/example/libs_stm/inc/stm32f10x/stm32f10x_spi.h deleted file mode 100644 index 920c82697..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_spi.h +++ /dev/null @@ -1,490 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_spi.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the SPI firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_SPI_H -#define __STM32F10x_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/** @defgroup SPI_Exported_Types - * @{ - */ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler. - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - - uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/** - * @} - */ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ - ((DATASIZE) == SPI_DataSize_8b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx) || \ - ((MODE) == I2S_Mode_MasterRx) ) -/** - * @} - */ - -/** @defgroup I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) -#define IS_I2S_AUDIO_FREQ(FREQ) (((FREQ) == I2S_AudioFreq_96k) || \ - ((FREQ) == I2S_AudioFreq_48k) || \ - ((FREQ) == I2S_AudioFreq_44k) || \ - ((FREQ) == I2S_AudioFreq_32k) || \ - ((FREQ) == I2S_AudioFreq_22k) || \ - ((FREQ) == I2S_AudioFreq_16k) || \ - ((FREQ) == I2S_AudioFreq_11k) || \ - ((FREQ) == I2S_AudioFreq_8k) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) -#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_NSS_internal_software_mangement - * @{ - */ - -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) -#define I2S_IT_UDR ((uint8_t)0x53) -#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ - ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) -/** - * @} - */ - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) -#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SPI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Exported_Functions - * @{ - */ - -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_SPI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_tim.h b/example/libs_stm/inc/stm32f10x/stm32f10x_tim.h deleted file mode 100644 index 500c195d2..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_tim.h +++ /dev/null @@ -1,1133 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_tim.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the TIM firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_TIM_H -#define __STM32F10x_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/** @defgroup TIM_Exported_Types - * @{ - */ - -/** - * @brief TIM Time Base Init structure definition - * @note This sturcture is used with all TIMx except for TIM6 and TIM7. - */ - -typedef struct -{ - uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/** - * @brief TIM Output Compare Init structure definition - */ - -typedef struct -{ - uint16_t TIM_OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_state */ - - uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_state - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -typedef struct -{ - - uint16_t TIM_Channel; /*!< Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/** - * @brief BDTR structure definition - * @note This sturcture is used only with TIM1 and TIM8. - */ - -typedef struct -{ - - uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref Lock_level */ - - uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/** @defgroup TIM_Exported_constants - * @{ - */ - -#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10)|| \ - ((PERIPH) == TIM11)|| \ - ((PERIPH) == TIM12)|| \ - ((PERIPH) == TIM13)|| \ - ((PERIPH) == TIM14)|| \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST1: TIM 1 and 8 */ -#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM8)) - -/* LIST2: TIM 1, 8, 15 16 and 17 */ -#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ -#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8)) - -/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */ -#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ -#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15)) - -/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */ -#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM12)|| \ - ((PERIPH) == TIM15)) - -/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */ -#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM12)|| \ - ((PERIPH) == TIM15)) - -/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ -#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10)|| \ - ((PERIPH) == TIM11)|| \ - ((PERIPH) == TIM12)|| \ - ((PERIPH) == TIM13)|| \ - ((PERIPH) == TIM14)|| \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */ -#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM15)|| \ - ((PERIPH) == TIM16)|| \ - ((PERIPH) == TIM17)) - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes - * @{ - */ - -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2)) -#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_ForcedAction_Active) || \ - ((MODE) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode - * @{ - */ - -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ - ((MODE) == TIM_OPMode_Repetitive)) -/** - * @} - */ - -/** @defgroup TIM_Channel - * @{ - */ - -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) -#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3) || \ - ((CHANNEL) == TIM_Channel_4)) -#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2)) -#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Division_CKD - * @{ - */ - -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) -#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ - ((DIV) == TIM_CKD_DIV2) || \ - ((DIV) == TIM_CKD_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode - * @{ - */ - -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ - ((MODE) == TIM_CounterMode_Down) || \ - ((MODE) == TIM_CounterMode_CenterAligned1) || \ - ((MODE) == TIM_CounterMode_CenterAligned2) || \ - ((MODE) == TIM_CounterMode_CenterAligned3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity - * @{ - */ - -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ - ((POLARITY) == TIM_OCPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity - * @{ - */ - -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ - ((POLARITY) == TIM_OCNPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_state - * @{ - */ - -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ - ((STATE) == TIM_OutputState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_state - * @{ - */ - -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ - ((STATE) == TIM_OutputNState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_state - * @{ - */ - -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) -#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ - ((CCX) == TIM_CCx_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_N_state - * @{ - */ - -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) -#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ - ((CCXN) == TIM_CCxN_Disable)) -/** - * @} - */ - -/** @defgroup Break_Input_enable_disable - * @{ - */ - -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ - ((STATE) == TIM_Break_Disable)) -/** - * @} - */ - -/** @defgroup Break_Polarity - * @{ - */ - -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ - ((POLARITY) == TIM_BreakPolarity_High)) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset - * @{ - */ - -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ - ((STATE) == TIM_AutomaticOutput_Disable)) -/** - * @} - */ - -/** @defgroup Lock_level - * @{ - */ - -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ - ((LEVEL) == TIM_LOCKLevel_1) || \ - ((LEVEL) == TIM_LOCKLevel_2) || \ - ((LEVEL) == TIM_LOCKLevel_3)) -/** - * @} - */ - -/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state - * @{ - */ - -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ - ((STATE) == TIM_OSSIState_Disable)) -/** - * @} - */ - -/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state - * @{ - */ - -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ - ((STATE) == TIM_OSSRState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State - * @{ - */ - -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ - ((STATE) == TIM_OCIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State - * @{ - */ - -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ - ((STATE) == TIM_OCNIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity - * @{ - */ - -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection - * @{ - */ - -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ - ((SELECTION) == TIM_ICSelection_IndirectTI) || \ - ((SELECTION) == TIM_ICSelection_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler - * @{ - */ - -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_interrupt_sources - * @{ - */ - -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) -#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_COM) || \ - ((IT) == TIM_IT_Trigger) || \ - ((IT) == TIM_IT_Break)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address - * @{ - */ - -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_RCR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_BDTR) || \ - ((BASE) == TIM_DMABase_DCR)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length - * @{ - */ - -#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \ - ((LENGTH) == TIM_DMABurstLength_2Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_3Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_4Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_5Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_6Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_7Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_8Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_9Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_10Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_11Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_12Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_13Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_14Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_15Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_16Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_17Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_18Bytes)) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources - * @{ - */ - -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Prescaler - * @{ - */ - -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) -#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Internal_Trigger_Selection - * @{ - */ - -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) -/** - * @} - */ - -/** @defgroup TIM_TIx_External_Clock_Source - * @{ - */ - -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) -#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ - ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ - ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Polarity - * @{ - */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) -#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ - ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) -/** - * @} - */ - -/** @defgroup TIM_Prescaler_Reload_Mode - * @{ - */ - -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) -#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ - ((RELOAD) == TIM_PSCReloadMode_Immediate)) -/** - * @} - */ - -/** @defgroup TIM_Forced_Action - * @{ - */ - -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) -#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ - ((ACTION) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode - * @{ - */ - -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ - ((MODE) == TIM_EncoderMode_TI2) || \ - ((MODE) == TIM_EncoderMode_TI12)) -/** - * @} - */ - - -/** @defgroup TIM_Event_Source - * @{ - */ - -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_Update_Source - * @{ - */ - -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ -#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ - ((SOURCE) == TIM_UpdateSource_Regular)) -/** - * @} - */ - -/** @defgroup TIM_Ouput_Compare_Preload_State - * @{ - */ - -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) -#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ - ((STATE) == TIM_OCPreload_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Ouput_Compare_Fast_State - * @{ - */ - -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) -#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ - ((STATE) == TIM_OCFast_Disable)) - -/** - * @} - */ - -/** @defgroup TIM_Ouput_Compare_Clear_State - * @{ - */ - -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) -#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ - ((STATE) == TIM_OCClear_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Output_Source - * @{ - */ - -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ - ((SOURCE) == TIM_TRGOSource_Enable) || \ - ((SOURCE) == TIM_TRGOSource_Update) || \ - ((SOURCE) == TIM_TRGOSource_OC1) || \ - ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC4Ref)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode - * @{ - */ - -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ - ((MODE) == TIM_SlaveMode_Gated) || \ - ((MODE) == TIM_SlaveMode_Trigger) || \ - ((MODE) == TIM_SlaveMode_External1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode - * @{ - */ - -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ - ((STATE) == TIM_MasterSlaveMode_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Flags - * @{ - */ - -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) -#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_Trigger) || \ - ((FLAG) == TIM_FLAG_Break) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) - - -#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value - * @{ - */ - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Filter - * @{ - */ - -#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions - * @{ - */ - -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); -uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); -uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F10x_TIM_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_usart.h b/example/libs_stm/inc/stm32f10x/stm32f10x_usart.h deleted file mode 100644 index b79855a1d..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_usart.h +++ /dev/null @@ -1,411 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_usart.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_USART_H -#define __STM32F10x_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/** @defgroup USART_Exported_Types - * @{ - */ - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ - - uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - - uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/** - * @} - */ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4) || \ - ((PERIPH) == UART5)) - -#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3)) - -#define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4)) -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_0_5) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) -#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @{ - */ - -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE ((uint16_t)0x0360) -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) -#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ - -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) -#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ - (((LENGTH) == USART_LINBreakDetectLength_10b) || \ - ((LENGTH) == USART_LINBreakDetectLength_11b)) -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ - -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) - -#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) -#define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\ - ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ - || ((USART_FLAG) != USART_FLAG_CTS)) -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) -#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup USART_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Exported_Functions - * @{ - */ - -void USART_DeInit(USART_TypeDef* USARTx); -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); -void USART_SendBreak(USART_TypeDef* USARTx); -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_USART_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32f10x/stm32f10x_wwdg.h b/example/libs_stm/inc/stm32f10x/stm32f10x_wwdg.h deleted file mode 100644 index fe238cdb9..000000000 --- a/example/libs_stm/inc/stm32f10x/stm32f10x_wwdg.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_wwdg.h - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file contains all the functions prototypes for the WWDG firmware - * library. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F10x_WWDG_H -#define __STM32F10x_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ - -/** @defgroup WWDG_Exported_Types - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Exported_Constants - * @{ - */ - -/** @defgroup WWDG_Prescaler - * @{ - */ - -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) -#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ - ((PRESCALER) == WWDG_Prescaler_2) || \ - ((PRESCALER) == WWDG_Prescaler_4) || \ - ((PRESCALER) == WWDG_Prescaler_8)) -#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) -#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup WWDG_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup WWDG_Exported_Functions - * @{ - */ - -void WWDG_DeInit(void); -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); -void WWDG_Enable(uint8_t Counter); -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F10x_WWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/misc.h b/example/libs_stm/inc/stm32l1xx/misc.h deleted file mode 100644 index cc551902f..000000000 --- a/example/libs_stm/inc/stm32l1xx/misc.h +++ /dev/null @@ -1,196 +0,0 @@ -/** - ****************************************************************************** - * @file misc.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MISC_H -#define __MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be a value of @ref IRQn_Type - (For the complete STM32 Devices IRQ Channels list, please - refer to stm32l1xx.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/** - * -@verbatim - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - ============================================================================================================================ - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ============================================================================================================================ - NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ============================================================================================================================ -@endverbatim -*/ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup Vector_Table_Base - * @{ - */ - -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup Preemption_Priority_Group - * @{ - */ - -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0001FFFF) - -/** - * @} - */ - -/** @defgroup SysTick_clock_source - * @{ - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_adc.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_adc.h deleted file mode 100644 index a7b882d01..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_adc.h +++ /dev/null @@ -1,606 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_adc.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the ADC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_ADC_H -#define __STM32L1xx_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief ADC Init structure definition - */ - -typedef struct -{ - uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion. - This parameter can be a value of @ref ADC_Resolution */ - - FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in - Scan (multichannel) or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - - FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in - Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - - uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the - trigger of a regular group. This parameter can be a value - of @ref ADC_external_trigger_edge_for_regular_channels_conversion */ - - uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog - to digital conversion of regular channels. This parameter - can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ - - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right. - This parameter can be a value of @ref ADC_data_align */ - - uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done - using the sequencer for regular channel group. - This parameter must range from 1 to 27. */ -}ADC_InitTypeDef; - -typedef struct -{ - uint32_t ADC_Prescaler; /*!< Selects the ADC prescaler. - This parameter can be a value - of @ref ADC_Prescaler */ -}ADC_CommonInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants - * @{ - */ -#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1) -#define IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1) - -/** @defgroup ADC_Power_down_during_Idle_and_or_Delay_phase - * @{ - */ -#define ADC_PowerDown_Delay ((uint32_t)0x00010000) -#define ADC_PowerDown_Idle ((uint32_t)0x00020000) -#define ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000) - -#define IS_ADC_POWER_DOWN(DWON) (((DWON) == ADC_PowerDown_Delay) || \ - ((DWON) == ADC_PowerDown_Idle) || \ - ((DWON) == ADC_PowerDown_Idle_Delay)) -/** - * @} - */ - - -/** @defgroup ADC_Prescaler - * @{ - */ -#define ADC_Prescaler_Div1 ((uint32_t)0x00000000) -#define ADC_Prescaler_Div2 ((uint32_t)0x00010000) -#define ADC_Prescaler_Div4 ((uint32_t)0x00020000) - -#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div1) || \ - ((PRESCALER) == ADC_Prescaler_Div2) || \ - ((PRESCALER) == ADC_Prescaler_Div4)) -/** - * @} - */ - - - -/** @defgroup ADC_resolution - * @{ - */ -#define ADC_Resolution_12b ((uint32_t)0x00000000) -#define ADC_Resolution_10b ((uint32_t)0x01000000) -#define ADC_Resolution_8b ((uint32_t)0x02000000) -#define ADC_Resolution_6b ((uint32_t)0x03000000) - -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ - ((RESOLUTION) == ADC_Resolution_10b) || \ - ((RESOLUTION) == ADC_Resolution_8b) || \ - ((RESOLUTION) == ADC_Resolution_6b)) - -/** - * @} - */ - -/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion - * @{ - */ -#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) -#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) -#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) - -#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) -/** - * @} - */ - -/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion - * @{ - */ - -/* TIM2 */ -#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000) -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) -#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) - -/* TIM3 */ -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) -#define ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000) -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000) - -/* TIM4 */ -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000) -#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000) - -/* TIM6 */ -#define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000) - -/* TIM9 */ -#define ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000) - -/* EXTI */ -#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) - -#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T9_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) -/** - * @} - */ - -/** @defgroup ADC_data_align - * @{ - */ - -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) - -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - -/** @defgroup ADC_channels - * @{ - */ - -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) -#define ADC_Channel_18 ((uint8_t)0x12) -#define ADC_Channel_19 ((uint8_t)0x13) -#define ADC_Channel_20 ((uint8_t)0x14) -#define ADC_Channel_21 ((uint8_t)0x15) -#define ADC_Channel_22 ((uint8_t)0x16) -#define ADC_Channel_23 ((uint8_t)0x17) -#define ADC_Channel_24 ((uint8_t)0x18) -#define ADC_Channel_25 ((uint8_t)0x19) - -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) - - - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \ - ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \ - ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \ - ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \ - ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \ - ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \ - ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \ - ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \ - ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17) || \ - ((CHANNEL) == ADC_Channel_18) || ((CHANNEL) == ADC_Channel_19) || \ - ((CHANNEL) == ADC_Channel_20) || ((CHANNEL) == ADC_Channel_21) || \ - ((CHANNEL) == ADC_Channel_22) || ((CHANNEL) == ADC_Channel_23) || \ - ((CHANNEL) == ADC_Channel_24) || ((CHANNEL) == ADC_Channel_25) ) -/** - * @} - */ - -/** @defgroup ADC_sampling_times - * @{ - */ - -#define ADC_SampleTime_4Cycles ((uint8_t)0x00) -#define ADC_SampleTime_9Cycles ((uint8_t)0x01) -#define ADC_SampleTime_16Cycles ((uint8_t)0x02) -#define ADC_SampleTime_24Cycles ((uint8_t)0x03) -#define ADC_SampleTime_48Cycles ((uint8_t)0x04) -#define ADC_SampleTime_96Cycles ((uint8_t)0x05) -#define ADC_SampleTime_192Cycles ((uint8_t)0x06) -#define ADC_SampleTime_384Cycles ((uint8_t)0x07) - -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_4Cycles) || \ - ((TIME) == ADC_SampleTime_9Cycles) || \ - ((TIME) == ADC_SampleTime_16Cycles) || \ - ((TIME) == ADC_SampleTime_24Cycles) || \ - ((TIME) == ADC_SampleTime_48Cycles) || \ - ((TIME) == ADC_SampleTime_96Cycles) || \ - ((TIME) == ADC_SampleTime_192Cycles) || \ - ((TIME) == ADC_SampleTime_384Cycles)) -/** - * @} - */ - -/** @defgroup ADC_Delay_length - * @{ - */ - -#define ADC_DelayLength_None ((uint8_t)0x00) -#define ADC_DelayLength_Freeze ((uint8_t)0x10) -#define ADC_DelayLength_7Cycles ((uint8_t)0x20) -#define ADC_DelayLength_15Cycles ((uint8_t)0x30) -#define ADC_DelayLength_31Cycles ((uint8_t)0x40) -#define ADC_DelayLength_63Cycles ((uint8_t)0x50) -#define ADC_DelayLength_127Cycles ((uint8_t)0x60) -#define ADC_DelayLength_255Cycles ((uint8_t)0x70) - -#define IS_ADC_DELAY_LENGTH(LENGTH) (((LENGTH) == ADC_DelayLength_None) || \ - ((LENGTH) == ADC_DelayLength_Freeze) || \ - ((LENGTH) == ADC_DelayLength_7Cycles) || \ - ((LENGTH) == ADC_DelayLength_15Cycles) || \ - ((LENGTH) == ADC_DelayLength_31Cycles) || \ - ((LENGTH) == ADC_DelayLength_63Cycles) || \ - ((LENGTH) == ADC_DelayLength_127Cycles) || \ - ((LENGTH) == ADC_DelayLength_255Cycles)) - -/** - * @} - */ - -/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion - * @{ - */ -#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) -#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) -#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) - -#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) -/** - * @} - */ - - -/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion - * @{ - */ - - -/* TIM2 */ -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000) -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000) - -/* TIM3 */ -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000) - -/* TIM4 */ -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000) -#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) -#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) -#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) - -/* TIM7 */ -#define ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000) - -/* TIM9 */ -#define ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000) - -/* TIM10 */ -#define ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000) - -/* EXTI */ -#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) - -#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) -/** - * @} - */ - -/** @defgroup ADC_injected_channel_selection - * @{ - */ -#define ADC_InjectedChannel_1 ((uint8_t)0x18) -#define ADC_InjectedChannel_2 ((uint8_t)0x1C) -#define ADC_InjectedChannel_3 ((uint8_t)0x20) -#define ADC_InjectedChannel_4 ((uint8_t)0x24) - -#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ - ((CHANNEL) == ADC_InjectedChannel_2) || \ - ((CHANNEL) == ADC_InjectedChannel_3) || \ - ((CHANNEL) == ADC_InjectedChannel_4)) -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ - -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) - -#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_None)) -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition - * @{ - */ - -#define ADC_IT_AWD ((uint16_t)0x0106) -#define ADC_IT_EOC ((uint16_t)0x0205) -#define ADC_IT_JEOC ((uint16_t)0x0407) -#define ADC_IT_OVR ((uint16_t)0x201A) - -#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_EOC) || \ - ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) -/** - * @} - */ - -/** @defgroup ADC_flags_definition - * @{ - */ - -#define ADC_FLAG_AWD ((uint16_t)0x0001) -#define ADC_FLAG_EOC ((uint16_t)0x0002) -#define ADC_FLAG_JEOC ((uint16_t)0x0004) -#define ADC_FLAG_JSTRT ((uint16_t)0x0008) -#define ADC_FLAG_STRT ((uint16_t)0x0010) -#define ADC_FLAG_OVR ((uint16_t)0x0020) -#define ADC_FLAG_ADONS ((uint16_t)0x0040) -#define ADC_FLAG_RCNR ((uint16_t)0x0100) -#define ADC_FLAG_JCNR ((uint16_t)0x0200) - -#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00)) - -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \ - ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \ - ((FLAG) == ADC_FLAG_STRT) || ((FLAG)== ADC_FLAG_OVR) || \ - ((FLAG) == ADC_FLAG_ADONS) || ((FLAG)== ADC_FLAG_RCNR) || \ - ((FLAG) == ADC_FLAG_JCNR)) -/** - * @} - */ - -/** @defgroup ADC_thresholds - * @{ - */ - -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_offset - * @{ - */ - -#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) - -/** - * @} - */ - -/** @defgroup ADC_injected_length - * @{ - */ - -#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) - -/** - * @} - */ - -/** @defgroup ADC_injected_rank - * @{ - */ - -#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) - -/** - * @} - */ - -/** @defgroup ADC_regular_length - * @{ - */ - -#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 27)) - -/** - * @} - */ - -/** @defgroup ADC_regular_rank - * @{ - */ - -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x1B)) - -/** - * @} - */ - -/** @defgroup ADC_regular_discontinuous_mode_number - * @{ - */ - -#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the ADC configuration to the default reset state *****/ -void ADC_DeInit(ADC_TypeDef* ADCx); - -/* Initialization and Configuration functions *********************************/ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -/* Power saving functions *****************************************************/ -void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState); -void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength); - -/* Analog Watchdog configuration functions ************************************/ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); - -/* Temperature Sensor & Vrefint (Voltage Reference internal) management function */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState); - -/* Regular Channels Configuration functions ***********************************/ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_SoftwareStartConv(ADC_TypeDef* ADCx); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); -void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); - -/* Regular Channels DMA Configuration functions *******************************/ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -/* Injected channels Configuration functions **********************************/ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); -void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); - -/* Interrupts and flags management functions **********************************/ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32L1xx_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_comp.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_comp.h deleted file mode 100644 index 1fcc9f923..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_comp.h +++ /dev/null @@ -1,180 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_comp.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the COMP firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_COMP_H -#define __STM32L1xx_COMP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup COMP - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief COMP Init structure definition - */ - -typedef struct -{ - uint32_t COMP_Speed; /*!< Defines the speed of comparator 2. - This parameter can be a value of @ref COMP_Speed */ - uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator 2. - This parameter can be a value of @ref COMP_InvertingInput */ - uint32_t COMP_OutputSelect; /*!< Selects the output redirection of the comparator 2. - This parameter can be a value of @ref COMP_OutputSelect */ - -}COMP_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup COMP_Exported_Constants - * @{ - */ - -#define COMP_OutputLevel_High ((uint32_t)0x00000001) -#define COMP_OutputLevel_Low ((uint32_t)0x00000000) - -/** @defgroup COMP_Selection - * @{ - */ - -#define COMP_Selection_COMP1 ((uint32_t)0x00000001) -#define COMP_Selection_COMP2 ((uint32_t)0x00000002) - -#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \ - ((PERIPH) == COMP_Selection_COMP2)) - -/** - * @} - */ - -/** @defgroup COMP_InvertingInput - * @{ - */ - -#define COMP_InvertingInput_None ((uint32_t)0x00000000) /* COMP2 is disabled when this parameter is selected */ -#define COMP_InvertingInput_IO ((uint32_t)0x00040000) -#define COMP_InvertingInput_VREFINT ((uint32_t)0x00080000) -#define COMP_InvertingInput_3_4VREFINT ((uint32_t)0x000C0000) -#define COMP_InvertingInput_1_2VREFINT ((uint32_t)0x00100000) -#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00140000) -#define COMP_InvertingInput_DAC1 ((uint32_t)0x00180000) -#define COMP_InvertingInput_DAC2 ((uint32_t)0x001C0000) - -#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_None) || \ - ((INPUT) == COMP_InvertingInput_IO) || \ - ((INPUT) == COMP_InvertingInput_VREFINT) || \ - ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \ - ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \ - ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \ - ((INPUT) == COMP_InvertingInput_DAC1) || \ - ((INPUT) == COMP_InvertingInput_DAC2)) -/** - * @} - */ - -/** @defgroup COMP_OutputSelect - * @{ - */ - -#define COMP_OutputSelect_TIM2IC4 ((uint32_t)0x00000000) -#define COMP_OutputSelect_TIM2OCREFCLR ((uint32_t)0x00200000) -#define COMP_OutputSelect_TIM3IC4 ((uint32_t)0x00400000) -#define COMP_OutputSelect_TIM3OCREFCLR ((uint32_t)0x00600000) -#define COMP_OutputSelect_TIM4IC4 ((uint32_t)0x00800000) -#define COMP_OutputSelect_TIM4OCREFCLR ((uint32_t)0x00A00000) -#define COMP_OutputSelect_TIM10IC1 ((uint32_t)0x00C00000) -#define COMP_OutputSelect_None ((uint32_t)0x00E00000) - -#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC4) || \ - ((OUTPUT) == COMP_OutputSelect_TIM2OCREFCLR) || \ - ((OUTPUT) == COMP_OutputSelect_TIM3IC4) || \ - ((OUTPUT) == COMP_OutputSelect_TIM3OCREFCLR) || \ - ((OUTPUT) == COMP_OutputSelect_TIM4IC4) || \ - ((OUTPUT) == COMP_OutputSelect_TIM4OCREFCLR) || \ - ((OUTPUT) == COMP_OutputSelect_TIM10IC1) || \ - ((OUTPUT) == COMP_OutputSelect_None)) -/** - * @} - */ - -/** @defgroup COMP_Speed - * @{ - */ - -#define COMP_Speed_Slow ((uint32_t)0x00000000) -#define COMP_Speed_Fast ((uint32_t)0x00001000) - -#define IS_COMP_SPEED(SPEED) (((SPEED) == COMP_Speed_Slow) || \ - ((SPEED) == COMP_Speed_Fast)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the COMP configuration to the default reset state ****/ -void COMP_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void COMP_Init(COMP_InitTypeDef* COMP_InitStruct); -void COMP_Cmd(FunctionalState NewState); -uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection); - -/* Window mode control function ***********************************************/ -void COMP_WindowCmd(FunctionalState NewState); - -/* Internal Reference Voltage (VREFINT) output function ***********************/ -void COMP_VrefintOutputCmd(FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32L1xx_COMP_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_crc.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_crc.h deleted file mode 100644 index 6c999fabd..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_crc.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_crc.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the CRC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_CRC_H -#define __STM32L1xx_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRC_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void CRC_ResetDR(void); -uint32_t CRC_CalcCRC(uint32_t Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); -void CRC_SetIDRegister(uint8_t IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_CRC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_dac.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_dac.h deleted file mode 100644 index 2ebe5e104..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_dac.h +++ /dev/null @@ -1,299 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_dac.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the DAC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_DAC_H -#define __STM32L1xx_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DAC Init structure definition - */ - -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -/** @defgroup DAC_trigger_selection - * @{ - */ - -#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T9_TRGO ((uint32_t)0x0000001C) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ - ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T9_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ - ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ - ((TRIGGER) == DAC_Trigger_Software)) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ - ((WAVE) == DAC_WaveGeneration_Noise) || \ - ((WAVE) == DAC_WaveGeneration_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_lfsrunmask_triangleamplitude - * @{ - */ - -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ - ((VALUE) == DAC_TriangleAmplitude_1) || \ - ((VALUE) == DAC_TriangleAmplitude_3) || \ - ((VALUE) == DAC_TriangleAmplitude_7) || \ - ((VALUE) == DAC_TriangleAmplitude_15) || \ - ((VALUE) == DAC_TriangleAmplitude_31) || \ - ((VALUE) == DAC_TriangleAmplitude_63) || \ - ((VALUE) == DAC_TriangleAmplitude_127) || \ - ((VALUE) == DAC_TriangleAmplitude_255) || \ - ((VALUE) == DAC_TriangleAmplitude_511) || \ - ((VALUE) == DAC_TriangleAmplitude_1023) || \ - ((VALUE) == DAC_TriangleAmplitude_2047) || \ - ((VALUE) == DAC_TriangleAmplitude_4095)) -/** - * @} - */ - -/** @defgroup DAC_output_buffer - * @{ - */ - -#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) -#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ - ((STATE) == DAC_OutputBuffer_Disable)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ - -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ - ((CHANNEL) == DAC_Channel_2)) -/** - * @} - */ - -/** @defgroup DAC_data_alignment - * @{ - */ - -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ - ((ALIGN) == DAC_Align_12b_L) || \ - ((ALIGN) == DAC_Align_8b_R)) -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ - ((WAVE) == DAC_Wave_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_data - * @{ - */ - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) - -/** - * @} - */ - -/** @defgroup DAC_interrupts_definition - * @{ - */ - -#define DAC_IT_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) - -/** - * @} - */ - - -/** @defgroup DAC_flags_definition - * @{ - */ - -#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) - -#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the DAC configuration to the default reset state *****/ -void DAC_DeInit(void); - -/* DAC channels configuration: trigger, output buffer, data format functions */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); - -/* DMA management functions ***************************************************/ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32L1xx_DAC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_dbgmcu.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_dbgmcu.h deleted file mode 100644 index 8b8aed1d2..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_dbgmcu.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_dbgmcu.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the DBGMCU - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_DBGMCU_H -#define __STM32L1xx_DBGMCU_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DBGMCU - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DBGMCU_Exported_Constants - * @{ - */ - -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004) -#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010) -#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020) -#define DBGMCU_RTC_STOP ((uint32_t)0x00000400) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) -#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFF9FE3C8) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM9_STOP ((uint32_t)0x00000004) -#define DBGMCU_TIM10_STOP ((uint32_t)0x00000008) -#define DBGMCU_TIM11_STOP ((uint32_t)0x00000010) -#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE3) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_DBGMCU_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_dma.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_dma.h deleted file mode 100644 index 4925c929a..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_dma.h +++ /dev/null @@ -1,363 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_dma.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the DMA firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_DMA_H -#define __STM32L1xx_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DMA Init structure definition - */ - -typedef struct -{ - uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */ - - uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */ - - uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_circular_normal_mode. - @note: The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer. - This parameter can be a value of @ref DMA_memory_to_memory */ -}DMA_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants - * @{ - */ - -#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ - ((PERIPH) == DMA1_Channel2) || \ - ((PERIPH) == DMA1_Channel3) || \ - ((PERIPH) == DMA1_Channel4) || \ - ((PERIPH) == DMA1_Channel5) || \ - ((PERIPH) == DMA1_Channel6) || \ - ((PERIPH) == DMA1_Channel7)) - -/** @defgroup DMA_data_transfer_direction - * @{ - */ - -#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) -#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) -#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \ - ((DIR) == DMA_DIR_PeripheralSRC)) -/** - * @} - */ - -/** @defgroup DMA_peripheral_incremented_mode - * @{ - */ - -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ - ((STATE) == DMA_PeripheralInc_Disable)) -/** - * @} - */ - -/** @defgroup DMA_memory_incremented_mode - * @{ - */ - -#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ - ((STATE) == DMA_MemoryInc_Disable)) -/** - * @} - */ - -/** @defgroup DMA_peripheral_data_size - * @{ - */ - -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ - ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ - ((SIZE) == DMA_PeripheralDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_memory_data_size - * @{ - */ - -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ - ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ - ((SIZE) == DMA_MemoryDataSize_Word)) -/** - * @} - */ - -/** @defgroup DMA_circular_normal_mode - * @{ - */ - -#define DMA_Mode_Circular ((uint32_t)0x00000020) -#define DMA_Mode_Normal ((uint32_t)0x00000000) -#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal)) -/** - * @} - */ - -/** @defgroup DMA_priority_level - * @{ - */ - -#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) -#define DMA_Priority_High ((uint32_t)0x00002000) -#define DMA_Priority_Medium ((uint32_t)0x00001000) -#define DMA_Priority_Low ((uint32_t)0x00000000) -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ - ((PRIORITY) == DMA_Priority_High) || \ - ((PRIORITY) == DMA_Priority_Medium) || \ - ((PRIORITY) == DMA_Priority_Low)) -/** - * @} - */ - -/** @defgroup DMA_memory_to_memory - * @{ - */ - -#define DMA_M2M_Enable ((uint32_t)0x00004000) -#define DMA_M2M_Disable ((uint32_t)0x00000000) -#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable)) - -/** - * @} - */ - -/** @defgroup DMA_interrupts_definition - * @{ - */ - -#define DMA_IT_TC ((uint32_t)0x00000002) -#define DMA_IT_HT ((uint32_t)0x00000004) -#define DMA_IT_TE ((uint32_t)0x00000008) -#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) - -#define DMA1_IT_GL1 ((uint32_t)0x00000001) -#define DMA1_IT_TC1 ((uint32_t)0x00000002) -#define DMA1_IT_HT1 ((uint32_t)0x00000004) -#define DMA1_IT_TE1 ((uint32_t)0x00000008) -#define DMA1_IT_GL2 ((uint32_t)0x00000010) -#define DMA1_IT_TC2 ((uint32_t)0x00000020) -#define DMA1_IT_HT2 ((uint32_t)0x00000040) -#define DMA1_IT_TE2 ((uint32_t)0x00000080) -#define DMA1_IT_GL3 ((uint32_t)0x00000100) -#define DMA1_IT_TC3 ((uint32_t)0x00000200) -#define DMA1_IT_HT3 ((uint32_t)0x00000400) -#define DMA1_IT_TE3 ((uint32_t)0x00000800) -#define DMA1_IT_GL4 ((uint32_t)0x00001000) -#define DMA1_IT_TC4 ((uint32_t)0x00002000) -#define DMA1_IT_HT4 ((uint32_t)0x00004000) -#define DMA1_IT_TE4 ((uint32_t)0x00008000) -#define DMA1_IT_GL5 ((uint32_t)0x00010000) -#define DMA1_IT_TC5 ((uint32_t)0x00020000) -#define DMA1_IT_HT5 ((uint32_t)0x00040000) -#define DMA1_IT_TE5 ((uint32_t)0x00080000) -#define DMA1_IT_GL6 ((uint32_t)0x00100000) -#define DMA1_IT_TC6 ((uint32_t)0x00200000) -#define DMA1_IT_HT6 ((uint32_t)0x00400000) -#define DMA1_IT_TE6 ((uint32_t)0x00800000) -#define DMA1_IT_GL7 ((uint32_t)0x01000000) -#define DMA1_IT_TC7 ((uint32_t)0x02000000) -#define DMA1_IT_HT7 ((uint32_t)0x04000000) -#define DMA1_IT_TE7 ((uint32_t)0x08000000) - -#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xF0000000) == 0x00) && ((IT) != 0x00)) - -#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \ - ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \ - ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \ - ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \ - ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \ - ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \ - ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \ - ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \ - ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \ - ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \ - ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \ - ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \ - ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \ - ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7)) - -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ -#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) -#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) -#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) -#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) -#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) -#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) -#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) -#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) -#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) -#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) -#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) -#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) -#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) -#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) -#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) -#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) -#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) -#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) -#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) -#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) -#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) -#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) -#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) -#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) -#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) -#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) -#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) -#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) - -#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xF0000000) == 0x00) && ((FLAG) != 0x00)) - -#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \ - ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \ - ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \ - ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \ - ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \ - ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \ - ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \ - ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \ - ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \ - ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \ - ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \ - ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \ - ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \ - ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7)) -/** - * @} - */ - -/** @defgroup DMA_Buffer_Size - * @{ - */ - -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the DMA configuration to the default reset state *****/ -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); - -/* Initialization and Configuration functions *********************************/ -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); - -/* Data Counter functions *****************************************************/ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); - -/* Interrupts and flags management functions **********************************/ -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); -FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); -void DMA_ClearFlag(uint32_t DMA_FLAG); -ITStatus DMA_GetITStatus(uint32_t DMA_IT); -void DMA_ClearITPendingBit(uint32_t DMA_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32L1xx_DMA_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_exti.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_exti.h deleted file mode 100644 index 1c2b6f2bd..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_exti.h +++ /dev/null @@ -1,190 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_exti.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the EXTI firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_EXTI_H -#define __STM32L1xx_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16 - Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x00020000) /*!< External interrupt line 17 - Connected to the RTC Alarm - event */ -#define EXTI_Line18 ((uint32_t)0x00040000) /*!< External interrupt line 18 - Connected to the USB Device - FS Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x00080000) /*!< External interrupt line 19 - Connected to the RTC Tamper - and Time Stamp events */ -#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 - Connected to the RTC Wakeup - event */ -#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 - Connected to the Comparator 1 - event */ - -#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 - Connected to the Comparator 2 - event */ - -#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00)) - -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ - ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \ - ((LINE) == EXTI_Line22)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Function used to set the EXTI configuration to the default reset state *****/ -void EXTI_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); - -/* Interrupts and flags management functions **********************************/ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_EXTI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_flash.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_flash.h deleted file mode 100644 index 0e0a6c63a..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_flash.h +++ /dev/null @@ -1,354 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_flash.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_FLASH_H -#define __STM32L1xx_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief FLASH Status - */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_WRP, - FLASH_ERROR_PROGRAM, - FLASH_COMPLETE, - FLASH_TIMEOUT -}FLASH_Status; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup FLASH_Latency - * @{ - */ -#define FLASH_Latency_0 ((uint8_t)0x00) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint8_t)0x01) /*!< FLASH One Latency cycle */ - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1)) -/** - * @} - */ - -/** @defgroup FLASH_Interrupts - * @{ - */ - -#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */ -#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000))) -/** - * @} - */ - -/** @defgroup FLASH_Address - * @{ - */ - -#define IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08080FFF)) -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ - - -#define OB_WRP_Pages0to15 ((uint32_t)0x00000001) /* Write protection of Sector0 */ -#define OB_WRP_Pages16to31 ((uint32_t)0x00000002) /* Write protection of Sector1 */ -#define OB_WRP_Pages32to47 ((uint32_t)0x00000004) /* Write protection of Sector2 */ -#define OB_WRP_Pages48to63 ((uint32_t)0x00000008) /* Write protection of Sector3 */ -#define OB_WRP_Pages64to79 ((uint32_t)0x00000010) /* Write protection of Sector4 */ -#define OB_WRP_Pages80to95 ((uint32_t)0x00000020) /* Write protection of Sector5 */ -#define OB_WRP_Pages96to111 ((uint32_t)0x00000040) /* Write protection of Sector6 */ -#define OB_WRP_Pages112to127 ((uint32_t)0x00000080) /* Write protection of Sector7 */ -#define OB_WRP_Pages128to143 ((uint32_t)0x00000100) /* Write protection of Sector8 */ -#define OB_WRP_Pages144to159 ((uint32_t)0x00000200) /* Write protection of Sector9 */ -#define OB_WRP_Pages160to175 ((uint32_t)0x00000400) /* Write protection of Sector10 */ -#define OB_WRP_Pages176to191 ((uint32_t)0x00000800) /* Write protection of Sector11 */ -#define OB_WRP_Pages192to207 ((uint32_t)0x00001000) /* Write protection of Sector12 */ -#define OB_WRP_Pages208to223 ((uint32_t)0x00002000) /* Write protection of Sector13 */ -#define OB_WRP_Pages224to239 ((uint32_t)0x00004000) /* Write protection of Sector14 */ -#define OB_WRP_Pages240to255 ((uint32_t)0x00008000) /* Write protection of Sector15 */ -#define OB_WRP_Pages256to271 ((uint32_t)0x00010000) /* Write protection of Sector16 */ -#define OB_WRP_Pages272to287 ((uint32_t)0x00020000) /* Write protection of Sector17 */ -#define OB_WRP_Pages288to303 ((uint32_t)0x00040000) /* Write protection of Sector18 */ -#define OB_WRP_Pages304to319 ((uint32_t)0x00080000) /* Write protection of Sector19 */ -#define OB_WRP_Pages320to335 ((uint32_t)0x00100000) /* Write protection of Sector20 */ -#define OB_WRP_Pages336to351 ((uint32_t)0x00200000) /* Write protection of Sector21 */ -#define OB_WRP_Pages352to367 ((uint32_t)0x00400000) /* Write protection of Sector22 */ -#define OB_WRP_Pages368to383 ((uint32_t)0x00800000) /* Write protection of Sector23 */ -#define OB_WRP_Pages384to399 ((uint32_t)0x01000000) /* Write protection of Sector24 */ -#define OB_WRP_Pages400to415 ((uint32_t)0x02000000) /* Write protection of Sector25 */ -#define OB_WRP_Pages416to431 ((uint32_t)0x04000000) /* Write protection of Sector26 */ -#define OB_WRP_Pages432to447 ((uint32_t)0x08000000) /* Write protection of Sector27 */ -#define OB_WRP_Pages448to463 ((uint32_t)0x10000000) /* Write protection of Sector28 */ -#define OB_WRP_Pages464to479 ((uint32_t)0x20000000) /* Write protection of Sector29 */ -#define OB_WRP_Pages480to495 ((uint32_t)0x40000000) /* Write protection of Sector30 */ -#define OB_WRP_Pages496to511 ((uint32_t)0x80000000) /* Write protection of Sector31 */ - -#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */ - -#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_Read_Protection - * @{ - */ - -/** - * @brief Read Protection Level - */ -#define OB_RDP_Level_0 ((uint8_t)0xAA) -#define OB_RDP_Level_1 ((uint8_t)0xBB) -/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 - it's no more possible to go back to level 1 or 0 */ - -#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ - ((LEVEL) == OB_RDP_Level_1))/*||\ - ((LEVEL) == OB_RDP_Level_2))*/ -/** - * @} - */ - -/** @defgroup Option_Bytes_IWatchdog - * @{ - */ - -#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */ -#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STOP - * @{ - */ - -#define OB_STOP_NoRST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_nRST_STDBY - * @{ - */ - -#define OB_STDBY_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) - -/** - * @} - */ - -/** @defgroup Option_Bytes_BOR_Level - * @{ - */ - -#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD - power supply reaches the PDR(Power Down Reset) threshold (1.5V) */ -#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */ -#define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */ -#define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */ -#define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */ -#define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */ - -#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_OFF) || \ - ((LEVEL) == OB_BOR_LEVEL1) || \ - ((LEVEL) == OB_BOR_LEVEL2) || \ - ((LEVEL) == OB_BOR_LEVEL3) || \ - ((LEVEL) == OB_BOR_LEVEL4) || \ - ((LEVEL) == OB_BOR_LEVEL5)) - -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ - -#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ -#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */ -#define FLASH_FLAG_ENDHV FLASH_SR_ENHV /*!< FLASH End of High Voltage flag */ -#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */ -#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ -#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ -#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */ - -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFF0FD) == 0x00000000) && ((FLAG) != 0x00000000)) - -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \ - ((FLAG) == FLASH_FLAG_ENDHV) || ((FLAG) == FLASH_FLAG_READY ) || \ - ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR ) || \ - ((FLAG) == FLASH_FLAG_SIZERR) || ((FLAG) == FLASH_FLAG_OPTVERR)) -/** - * @} - */ - -/** @defgroup FLASH_Keys - * @{ - */ - -#define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */ -#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1 - to unlock the RUN_PD bit in FLASH_ACR */ - -#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */ -#define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2 - to unlock the write access to the FLASH_PECR register and - data EEPROM */ - -#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */ -#define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2 - to unlock the program memory */ - -#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */ -#define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to - unlock the write access to the option byte block */ -/** - * @} - */ - -/** @defgroup Timeout_definition - * @{ - */ -#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x8000) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/** - * @brief FLASH memory functions that can be executed from FLASH. - */ -/* FLASH Interface configuration functions ************************************/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_PrefetchBufferCmd(FunctionalState NewState); -void FLASH_ReadAccess64Cmd(FunctionalState NewState); -void FLASH_SLEEPPowerDownCmd(FunctionalState NewState); - -/* FLASH Memory Programming functions *****************************************/ -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_ErasePage(uint32_t Page_Address); -FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data); - -/* DATA EEPROM Programming functions ******************************************/ -void DATA_EEPROM_Unlock(void); -void DATA_EEPROM_Lock(void); -void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState); -FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address); -FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data); -FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data); -FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data); - -/* Option Bytes Programming functions *****************************************/ -void FLASH_OB_Unlock(void); -void FLASH_OB_Lock(void); -void FLASH_OB_Launch(void); -FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); -FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP); -FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); -FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR); -uint8_t FLASH_OB_GetUser(void); -uint32_t FLASH_OB_GetWRP(void); -FlagStatus FLASH_OB_GetRDP(void); -uint8_t FLASH_OB_GetBOR(void); - -/* Interrupts and flags management functions **********************************/ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); - -/** - * @brief FLASH memory functions that should be executed from internal SRAM. - * These functions are defined inside the "stm32l1xx_flash_ramfunc.c" - * file. - */ -FLASH_Status FLASH_RUNPowerDownCmd(FunctionalState NewState); -FLASH_Status FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer); -FLASH_Status DATA_EEPROM_EraseDoubleWord(uint32_t Address); -FLASH_Status DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_FLASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_gpio.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_gpio.h deleted file mode 100644 index 6e1a1dd1d..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_gpio.h +++ /dev/null @@ -1,364 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_gpio.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the GPIO - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_GPIO_H -#define __STM32L1xx_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOH)) - -/** @defgroup Configuration_Mode_enumeration - * @{ - */ -typedef enum -{ - GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ - GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ - GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ - GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ -}GPIOMode_TypeDef; -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ - ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) -/** - * @} - */ - -/** @defgroup Output_type_enumeration - * @{ - */ -typedef enum -{ GPIO_OType_PP = 0x00, - GPIO_OType_OD = 0x01 -}GPIOOType_TypeDef; -#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) - -/** - * @} - */ - -/** @defgroup Output_Maximum_frequency_enumeration - * @{ - */ -typedef enum -{ - GPIO_Speed_400KHz = 0x00, /*!< Very Low Speed */ - GPIO_Speed_2MHz = 0x01, /*!< Low Speed */ - GPIO_Speed_10MHz = 0x02, /*!< Medium Speed */ - GPIO_Speed_40MHz = 0x03 /*!< High Speed */ -}GPIOSpeed_TypeDef; -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_400KHz) || ((SPEED) == GPIO_Speed_2MHz) || \ - ((SPEED) == GPIO_Speed_10MHz)|| ((SPEED) == GPIO_Speed_40MHz)) -/** - * @} - */ - -/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration - * @{ - */ -typedef enum -{ GPIO_PuPd_NOPULL = 0x00, - GPIO_PuPd_UP = 0x01, - GPIO_PuPd_DOWN = 0x02 -}GPIOPuPd_TypeDef; -#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ - ((PUPD) == GPIO_PuPd_DOWN)) -/** - * @} - */ - -/** @defgroup Bit_SET_and_Bit_RESET_enumeration - * @{ - */ -typedef enum -{ Bit_RESET = 0, - Bit_SET -}BitAction; -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) - -/** - * @} - */ - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIOOType_TypeDef */ - - GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIOPuPd_TypeDef */ -}GPIO_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ - -#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00) -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) -/** - * @} - */ - -/** @defgroup GPIO_Pin_sources - * @{ - */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) -/** - * @} - */ - -/** @defgroup GPIO_Alternat_function_selection_define - * @{ - */ - -/** - * @brief AF 0 selection - */ -#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /*!< RTC 50/60 Hz Alternate Function mapping */ -#define GPIO_AF_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ -#define GPIO_AF_RTC_AF1 ((uint8_t)0x00) /*!< RTC_AF1 Alternate Function mapping */ -#define GPIO_AF_WKUP ((uint8_t)0x00) /*!< Wakeup (WKUP1, WKUP2 and WKUP3) Alternate Function mapping */ -#define GPIO_AF_SWJ ((uint8_t)0x00) /*!< SWJ (SW and JTAG) Alternate Function mapping */ -#define GPIO_AF_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ -/** - * @brief AF 2 selection - */ -#define GPIO_AF_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */ -#define GPIO_AF_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */ -/** - * @brief AF 3 selection - */ -#define GPIO_AF_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */ -#define GPIO_AF_TIM10 ((uint8_t)0x03) /*!< TIM10 Alternate Function mapping */ -#define GPIO_AF_TIM11 ((uint8_t)0x03) /*!< TIM11 Alternate Function mapping */ -/** - * @brief AF 4 selection - */ -#define GPIO_AF_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ -#define GPIO_AF_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */ -/** - * @brief AF 5 selection - */ -#define GPIO_AF_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */ -#define GPIO_AF_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */ -/** - * @brief AF 7 selection - */ -#define GPIO_AF_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ -#define GPIO_AF_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */ -#define GPIO_AF_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */ -/** - * @brief AF 10 selection - */ -#define GPIO_AF_USB ((uint8_t)0xA) /*!< USB Full speed device Alternate Function mapping */ -/** - * @brief AF 11 selection - */ -#define GPIO_AF_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */ -/** - * @brief AF 14 selection - */ -#define GPIO_AF_RI ((uint8_t)0x0E) /*!< RI Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_MCO) || \ - ((AF) == GPIO_AF_RTC_AF1) || ((AF) == GPIO_AF_WKUP) || \ - ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ - ((AF) == GPIO_AF_TIM2) || ((AF)== GPIO_AF_TIM3) || \ - ((AF) == GPIO_AF_TIM4) || ((AF)== GPIO_AF_TIM9) || \ - ((AF) == GPIO_AF_TIM10) || ((AF)== GPIO_AF_TIM11) || \ - ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ - ((AF) == GPIO_AF_SPI1) || ((AF) == GPIO_AF_SPI2) || \ - ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ - ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_USB) || \ - ((AF) == GPIO_AF_LCD) || ((AF) == GPIO_AF_RI) || \ - ((AF) == GPIO_AF_EVENTOUT)) - -/** - * @} - */ - -/** @defgroup GPIO_Legacy - * @{ - */ - -#define GPIO_Mode_AIN GPIO_Mode_AN - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the GPIO configuration to the default reset state ****/ -void GPIO_DeInit(GPIO_TypeDef* GPIOx); - -/* Initialization and Configuration functions *********************************/ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Read and Write functions **********************************************/ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); - -/* GPIO Alternate functions configuration functions ***************************/ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32L1xx_GPIO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_i2c.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_i2c.h deleted file mode 100644 index 15b5c5464..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_i2c.h +++ /dev/null @@ -1,688 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_i2c.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the I2C firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_I2C_H -#define __STM32L1xx_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -}I2C_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2)) -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_duty_cycle_in_fast_mode - * @{ - */ - -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ - ((CYCLE) == I2C_DutyCycle_2)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) -#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ - ((STATE) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_DR ((uint8_t)0x10) -#define I2C_Register_SR1 ((uint8_t)0x14) -#define I2C_Register_SR2 ((uint8_t)0x18) -#define I2C_Register_CCR ((uint8_t)0x1C) -#define I2C_Register_TRISE ((uint8_t)0x20) -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_DR) || \ - ((REGISTER) == I2C_Register_SR1) || \ - ((REGISTER) == I2C_Register_SR2) || \ - ((REGISTER) == I2C_Register_CCR) || \ - ((REGISTER) == I2C_Register_TRISE)) -/** - * @} - */ - -/** @defgroup I2C_SMBus_alert_pin_level - * @{ - */ - -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) -#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ - ((ALERT) == I2C_SMBusAlert_High)) -/** - * @} - */ - -/** @defgroup I2C_PEC_position - * @{ - */ - -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ - ((POSITION) == I2C_PECPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ - ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ - ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ - ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -/** - * @brief SR2 register flags - */ - -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/** - * @brief SR1 register flags - */ - -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ - ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ - ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ - ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ - ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ - ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ - ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ - ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_SB)) -/** - * @} - */ - -/** @defgroup I2C_Events - * @{ - */ - -/** - =============================================================================== - I2C Master Events (Events grouped in order of communication) - =============================================================================== - */ - -/** - * @brief Communication start - * - * After sending the START condition (I2C_GenerateSTART() function) the master - * has to wait for this event. It means that the Start condition has been correctly - * released on the I2C bus (the bus is free, no other devices is communicating). - * - */ -/* --EV5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/** - * @brief Address Acknowledge - * - * After checking on EV5 (start condition correctly released on the bus), the - * master sends the address of the slave(s) with which it will communicate - * (I2C_Send7bitAddress() function, it also determines the direction of the communication: - * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will - * be set: - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (just after generating the START - * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() - * function). Then master should wait on EV9. It means that the 10-bit addressing - * header has been correctly sent on the bus. Then master should send the second part of - * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master - * should wait for event EV6. - * - */ - -/* --EV6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/* --EV9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/** - * @brief Communication events - * - * If a communication is established (START condition generated and slave address - * acknowledged) then the master has to check on one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EV7 then to read - * the data received from the slave (I2C_ReceiveData() function). - * - * 2) Master Transmitter mode: The master has to send data (I2C_SendData() - * function) then to wait on event EV8 or EV8_2. - * These two events are similar: - * - EV8 means that the data has been written in the data register and is - * being shifted out. - * - EV8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EV8 is sufficient for the application. - * Using EV8_2 leads to a slower communication but ensure more reliable test. - * EV8_2 is also more suitable than EV8 for testing on the last data transmission - * (before Stop condition generation). - * - * @note In case the user software does not guarantee that this event EV7 is - * managed before the current byte end of transfer, then user may check on EV7 - * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Master RECEIVER mode -----------------------------*/ -/* --EV7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master TRANSMITTER mode --------------------------*/ -/* --EV8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* --EV8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - - -/** - =============================================================================== - I2C Slave Events (Events grouped in order of communication) - =============================================================================== - */ - - -/** - * @brief Communication start events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a Start condition on the bus (generated by master - * device) followed by the peripheral address. The peripheral generates an ACK - * condition on the bus (if the acknowledge feature is enabled through function - * I2C_AcknowledgeConfig()) and the events listed above are set : - * - * 1) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * 2) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * 3) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* --EV1 (all the events below are variants of EV1) */ -/* 1) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* 2) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* 3) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/** - * @brief Communication events - * - * Wait on one of these events when EV1 has already been checked and: - * - * - Slave RECEIVER mode: - * - EV2: When the application is expecting a data byte to be received. - * - EV4: When the application is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EV3: When a byte has been transmitted by the slave and the application is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be - * used when the user software doesn't guarantee the EV3 is managed before the - * current byte end of transfer. - * - EV3_2: When the master sends a NACK in order to tell slave that data transmission - * shall end (before sending the STOP condition). In this case slave has to stop sending - * data bytes and expect a Stop condition on the bus. - * - * @note In case the user software does not guarantee that the event EV2 is - * managed before the current byte end of transfer, then user may check on EV2 - * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Slave RECEIVER mode --------------------------*/ -/* --EV2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* --EV4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave TRANSMITTER mode -----------------------*/ -/* --EV3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/* --EV3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - -/** - =============================================================================== - End of Events Description - =============================================================================== - */ - -#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ - ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ - ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) -/** - * @} - */ - -/** @defgroup I2C_clock_speed - * @{ - */ - -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the I2C configuration to the default reset state *****/ -void I2C_DeInit(I2C_TypeDef* I2Cx); - -/* Initialization and Configuration functions *********************************/ -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); - -/* Data transfers functions ***************************************************/ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); - -/* PEC management functions ***************************************************/ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); - -/* DMA transfers management functions *****************************************/ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - - -/* Interrupts, events and flags management functions **************************/ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); - -/** - * @brief - * -@verbatim - =============================================================================== - I2C State Monitoring Functions - =============================================================================== - This I2C driver provides three different ways for I2C state monitoring - depending on the application requirements and constraints: - - - 1. Basic state monitoring (Using I2C_CheckEvent() function) - ----------------------------------------------------------- - It compares the status registers (SR1 and SR2) content to a given event - (can be the combination of one or more flags). - It returns SUCCESS if the current status includes the given flags - and returns ERROR if one or more flags are missing in the current status. - - - When to use - - This function is suitable for most applications as well as for startup - activity since the events are fully described in the product reference - manual (RM0038). - - It is also suitable for users who need to define their own events. - - - Limitations - - If an error occurs (ie. error flags are set besides to the monitored - flags), the I2C_CheckEvent() function may return SUCCESS despite - the communication hold or corrupted real state. - In this case, it is advised to use error interrupts to monitor - the error events and handle them in the interrupt IRQ handler. - - @note - For error management, it is advised to use the following functions: - - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - Where x is the peripheral instance (I2C1, I2C2 ...) - - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the - I2Cx_ER_IRQHandler() function in order to determine which error occurred. - - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - and/or I2C_GenerateStop() in order to clear the error flag and source - and return to correct communciation status. - - - 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) - -------------------------------------------------------------------- - Using the function I2C_GetLastEvent() which returns the image of both status - registers in a single word (uint32_t) (Status Register 2 value is shifted left - by 16 bits and concatenated to Status Register 1). - - - When to use - - This function is suitable for the same applications above but it - allows to overcome the mentioned limitation of I2C_GetFlagStatus() - function. - - The returned value could be compared to events already defined in - the library (stm32l1xx_i2c.h) or to custom values defined by user. - This function is suitable when multiple flags are monitored at the - same time. - - At the opposite of I2C_CheckEvent() function, this function allows - user to choose when an event is accepted (when all events flags are - set and no other flags are set or just when the needed flags are set - like I2C_CheckEvent() function. - - - Limitations - - User may need to define his own events. - - Same remark concerning the error management is applicable for this - function if user decides to check only regular communication flags - (and ignores error flags). - - - 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) - ----------------------------------------------------------------------- - - Using the function I2C_GetFlagStatus() which simply returns the status of - one single flag (ie. I2C_FLAG_RXNE ...). - - - When to use - - This function could be used for specific applications or in debug - phase. - - It is suitable when only one flag checking is needed (most I2C - events are monitored through multiple flags). - - Limitations: - - When calling this function, the Status register is accessed. - Some flags are cleared when the status register is accessed. - So checking the status of one Flag, may clear other ones. - - Function may need to be called twice or more in order to monitor - one single event. - - For detailed description of Events, please refer to section I2C_Events in - stm32l1xx_i2c.h file. - -@endverbatim - * - */ - -/** - =============================================================================== - 1. Basic state monitoring - =============================================================================== - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/** - =============================================================================== - 2. Advanced state monitoring - =============================================================================== - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/** - =============================================================================== - 3. Flag-based state monitoring - =============================================================================== - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - - -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32L1xx_I2C_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_iwdg.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_iwdg.h deleted file mode 100644 index 00b768e3f..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_iwdg.h +++ /dev/null @@ -1,128 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_iwdg.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the IWDG - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_IWDG_H -#define __STM32L1xx_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup IWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup IWDG_Exported_Constants - * @{ - */ - -/** @defgroup IWDG_WriteAccess - * @{ - */ - -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) -#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ - ((ACCESS) == IWDG_WriteAccess_Disable)) -/** - * @} - */ - -/** @defgroup IWDG_prescaler - * @{ - */ - -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) -#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ - ((PRESCALER) == IWDG_Prescaler_8) || \ - ((PRESCALER) == IWDG_Prescaler_16) || \ - ((PRESCALER) == IWDG_Prescaler_32) || \ - ((PRESCALER) == IWDG_Prescaler_64) || \ - ((PRESCALER) == IWDG_Prescaler_128)|| \ - ((PRESCALER) == IWDG_Prescaler_256)) -/** - * @} - */ - -/** @defgroup IWDG_Flag - * @{ - */ - -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) -#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) -#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Prescaler and Counter configuration functions ******************************/ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); - -/* IWDG activation function ***************************************************/ -void IWDG_Enable(void); - -/* Flag management function ***************************************************/ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_IWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_lcd.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_lcd.h deleted file mode 100644 index 4944c8361..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_lcd.h +++ /dev/null @@ -1,446 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_lcd.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the LCD firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_LCD_H -#define __STM32L1xx_LCD_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup LCD - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief LCD Init structure definition - */ - -typedef struct -{ - uint32_t LCD_Prescaler; /*!< Configures the LCD Prescaler. - This parameter can be one value of @ref LCD_Prescaler */ - uint32_t LCD_Divider; /*!< Configures the LCD Divider. - This parameter can be one value of @ref LCD_Divider */ - uint32_t LCD_Duty; /*!< Configures the LCD Duty. - This parameter can be one value of @ref LCD_Duty */ - uint32_t LCD_Bias; /*!< Configures the LCD Bias. - This parameter can be one value of @ref LCD_Bias */ - uint32_t LCD_VoltageSource; /*!< Selects the LCD Voltage source. - This parameter can be one value of @ref LCD_Voltage_Source */ -}LCD_InitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup LCD_Exported_Constants - * @{ - */ - -/** @defgroup LCD_Prescaler - * @{ - */ - -#define LCD_Prescaler_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */ -#define LCD_Prescaler_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */ -#define LCD_Prescaler_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */ -#define LCD_Prescaler_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */ -#define LCD_Prescaler_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */ -#define LCD_Prescaler_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */ -#define LCD_Prescaler_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */ -#define LCD_Prescaler_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */ -#define LCD_Prescaler_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */ -#define LCD_Prescaler_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */ -#define LCD_Prescaler_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */ -#define LCD_Prescaler_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */ -#define LCD_Prescaler_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */ -#define LCD_Prescaler_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */ -#define LCD_Prescaler_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */ -#define LCD_Prescaler_32768 ((uint32_t)0x03C00000) /*!< CLKPS = LCDCLK/32768 */ - -#define IS_LCD_PRESCALER(PRESCALER) (((PRESCALER) == LCD_Prescaler_1) || \ - ((PRESCALER) == LCD_Prescaler_2) || \ - ((PRESCALER) == LCD_Prescaler_4) || \ - ((PRESCALER) == LCD_Prescaler_8) || \ - ((PRESCALER) == LCD_Prescaler_16) || \ - ((PRESCALER) == LCD_Prescaler_32) || \ - ((PRESCALER) == LCD_Prescaler_64) || \ - ((PRESCALER) == LCD_Prescaler_128) || \ - ((PRESCALER) == LCD_Prescaler_256) || \ - ((PRESCALER) == LCD_Prescaler_512) || \ - ((PRESCALER) == LCD_Prescaler_1024) || \ - ((PRESCALER) == LCD_Prescaler_2048) || \ - ((PRESCALER) == LCD_Prescaler_4096) || \ - ((PRESCALER) == LCD_Prescaler_8192) || \ - ((PRESCALER) == LCD_Prescaler_16384) || \ - ((PRESCALER) == LCD_Prescaler_32768)) - -/** - * @} - */ - -/** @defgroup LCD_Divider - * @{ - */ - -#define LCD_Divider_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */ -#define LCD_Divider_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */ -#define LCD_Divider_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */ -#define LCD_Divider_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */ -#define LCD_Divider_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */ -#define LCD_Divider_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */ -#define LCD_Divider_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */ -#define LCD_Divider_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */ -#define LCD_Divider_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */ -#define LCD_Divider_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */ -#define LCD_Divider_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */ -#define LCD_Divider_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */ -#define LCD_Divider_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */ -#define LCD_Divider_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */ -#define LCD_Divider_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */ -#define LCD_Divider_31 ((uint32_t)0x003C0000) /*!< LCD frequency = CLKPS/31 */ - -#define IS_LCD_DIVIDER(DIVIDER) (((DIVIDER) == LCD_Divider_16) || \ - ((DIVIDER) == LCD_Divider_17) || \ - ((DIVIDER) == LCD_Divider_18) || \ - ((DIVIDER) == LCD_Divider_19) || \ - ((DIVIDER) == LCD_Divider_20) || \ - ((DIVIDER) == LCD_Divider_21) || \ - ((DIVIDER) == LCD_Divider_22) || \ - ((DIVIDER) == LCD_Divider_23) || \ - ((DIVIDER) == LCD_Divider_24) || \ - ((DIVIDER) == LCD_Divider_25) || \ - ((DIVIDER) == LCD_Divider_26) || \ - ((DIVIDER) == LCD_Divider_27) || \ - ((DIVIDER) == LCD_Divider_28) || \ - ((DIVIDER) == LCD_Divider_29) || \ - ((DIVIDER) == LCD_Divider_30) || \ - ((DIVIDER) == LCD_Divider_31)) - -/** - * @} - */ - - -/** @defgroup LCD_Duty - * @{ - */ - -#define LCD_Duty_Static ((uint32_t)0x00000000) /*!< Static duty */ -#define LCD_Duty_1_2 ((uint32_t)0x00000004) /*!< 1/2 duty */ -#define LCD_Duty_1_3 ((uint32_t)0x00000008) /*!< 1/3 duty */ -#define LCD_Duty_1_4 ((uint32_t)0x0000000C) /*!< 1/4 duty */ -#define LCD_Duty_1_8 ((uint32_t)0x00000010) /*!< 1/4 duty */ - -#define IS_LCD_DUTY(DUTY) (((DUTY) == LCD_Duty_Static) || \ - ((DUTY) == LCD_Duty_1_2) || \ - ((DUTY) == LCD_Duty_1_3) || \ - ((DUTY) == LCD_Duty_1_4) || \ - ((DUTY) == LCD_Duty_1_8)) - -/** - * @} - */ - - -/** @defgroup LCD_Bias - * @{ - */ - -#define LCD_Bias_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */ -#define LCD_Bias_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */ -#define LCD_Bias_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */ - -#define IS_LCD_BIAS(BIAS) (((BIAS) == LCD_Bias_1_4) || \ - ((BIAS) == LCD_Bias_1_2) || \ - ((BIAS) == LCD_Bias_1_3)) -/** - * @} - */ - -/** @defgroup LCD_Voltage_Source - * @{ - */ - -#define LCD_VoltageSource_Internal ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */ -#define LCD_VoltageSource_External LCD_CR_VSEL /*!< External voltage source for the LCD */ - -#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VoltageSource_Internal) || \ - ((SOURCE) == LCD_VoltageSource_External)) - -/** - * @} - */ - -/** @defgroup LCD_Interrupts - * @{ - */ -#define LCD_IT_SOF LCD_FCR_SOFIE -#define LCD_IT_UDD LCD_FCR_UDDIE - -#define IS_LCD_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF5) == 0x00) && ((IT) != 0x00)) - -#define IS_LCD_GET_IT(IT) (((IT) == LCD_IT_SOF) || ((IT) == LCD_IT_UDD)) - -/** - * @} - */ - -/** @defgroup LCD_PulseOnDuration - * @{ - */ - -#define LCD_PulseOnDuration_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */ -#define LCD_PulseOnDuration_1 ((uint32_t)0x00000010) /*!< Pulse ON duration = 1/CK_PS */ -#define LCD_PulseOnDuration_2 ((uint32_t)0x00000020) /*!< Pulse ON duration = 2/CK_PS */ -#define LCD_PulseOnDuration_3 ((uint32_t)0x00000030) /*!< Pulse ON duration = 3/CK_PS */ -#define LCD_PulseOnDuration_4 ((uint32_t)0x00000040) /*!< Pulse ON duration = 4/CK_PS */ -#define LCD_PulseOnDuration_5 ((uint32_t)0x00000050) /*!< Pulse ON duration = 5/CK_PS */ -#define LCD_PulseOnDuration_6 ((uint32_t)0x00000060) /*!< Pulse ON duration = 6/CK_PS */ -#define LCD_PulseOnDuration_7 ((uint32_t)0x00000070) /*!< Pulse ON duration = 7/CK_PS */ - -#define IS_LCD_PULSE_ON_DURATION(DURATION) (((DURATION) == LCD_PulseOnDuration_0) || \ - ((DURATION) == LCD_PulseOnDuration_1) || \ - ((DURATION) == LCD_PulseOnDuration_2) || \ - ((DURATION) == LCD_PulseOnDuration_3) || \ - ((DURATION) == LCD_PulseOnDuration_4) || \ - ((DURATION) == LCD_PulseOnDuration_5) || \ - ((DURATION) == LCD_PulseOnDuration_6) || \ - ((DURATION) == LCD_PulseOnDuration_7)) -/** - * @} - */ - - -/** @defgroup LCD_DeadTime - * @{ - */ - -#define LCD_DeadTime_0 ((uint32_t)0x00000000) /*!< No dead Time */ -#define LCD_DeadTime_1 ((uint32_t)0x00000080) /*!< One Phase between different couple of Frame */ -#define LCD_DeadTime_2 ((uint32_t)0x00000100) /*!< Two Phase between different couple of Frame */ -#define LCD_DeadTime_3 ((uint32_t)0x00000180) /*!< Three Phase between different couple of Frame */ -#define LCD_DeadTime_4 ((uint32_t)0x00000200) /*!< Four Phase between different couple of Frame */ -#define LCD_DeadTime_5 ((uint32_t)0x00000280) /*!< Five Phase between different couple of Frame */ -#define LCD_DeadTime_6 ((uint32_t)0x00000300) /*!< Six Phase between different couple of Frame */ -#define LCD_DeadTime_7 ((uint32_t)0x00000380) /*!< Seven Phase between different couple of Frame */ - -#define IS_LCD_DEAD_TIME(TIME) (((TIME) == LCD_DeadTime_0) || \ - ((TIME) == LCD_DeadTime_1) || \ - ((TIME) == LCD_DeadTime_2) || \ - ((TIME) == LCD_DeadTime_3) || \ - ((TIME) == LCD_DeadTime_4) || \ - ((TIME) == LCD_DeadTime_5) || \ - ((TIME) == LCD_DeadTime_6) || \ - ((TIME) == LCD_DeadTime_7)) -/** - * @} - */ - -/** @defgroup LCD_BlinkMode - * @{ - */ - -#define LCD_BlinkMode_Off ((uint32_t)0x00000000) /*!< Blink disabled */ -#define LCD_BlinkMode_SEG0_COM0 ((uint32_t)0x00010000) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */ -#define LCD_BlinkMode_SEG0_AllCOM ((uint32_t)0x00020000) /*!< Blink enabled on SEG[0], all COM (up to - 8 pixels according to the programmed duty) */ -#define LCD_BlinkMode_AllSEG_AllCOM ((uint32_t)0x00030000) /*!< Blink enabled on all SEG and all COM (all pixels) */ - -#define IS_LCD_BLINK_MODE(MODE) (((MODE) == LCD_BlinkMode_Off) || \ - ((MODE) == LCD_BlinkMode_SEG0_COM0) || \ - ((MODE) == LCD_BlinkMode_SEG0_AllCOM) || \ - ((MODE) == LCD_BlinkMode_AllSEG_AllCOM)) -/** - * @} - */ - -/** @defgroup LCD_BlinkFrequency - * @{ - */ - -#define LCD_BlinkFrequency_Div8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */ -#define LCD_BlinkFrequency_Div16 ((uint32_t)0x00002000) /*!< The Blink frequency = fLCD/16 */ -#define LCD_BlinkFrequency_Div32 ((uint32_t)0x00004000) /*!< The Blink frequency = fLCD/32 */ -#define LCD_BlinkFrequency_Div64 ((uint32_t)0x00006000) /*!< The Blink frequency = fLCD/64 */ -#define LCD_BlinkFrequency_Div128 ((uint32_t)0x00008000) /*!< The Blink frequency = fLCD/128 */ -#define LCD_BlinkFrequency_Div256 ((uint32_t)0x0000A000) /*!< The Blink frequency = fLCD/256 */ -#define LCD_BlinkFrequency_Div512 ((uint32_t)0x0000C000) /*!< The Blink frequency = fLCD/512 */ -#define LCD_BlinkFrequency_Div1024 ((uint32_t)0x0000E000) /*!< The Blink frequency = fLCD/1024 */ - -#define IS_LCD_BLINK_FREQUENCY(FREQUENCY) (((FREQUENCY) == LCD_BlinkFrequency_Div8) || \ - ((FREQUENCY) == LCD_BlinkFrequency_Div16) || \ - ((FREQUENCY) == LCD_BlinkFrequency_Div32) || \ - ((FREQUENCY) == LCD_BlinkFrequency_Div64) || \ - ((FREQUENCY) == LCD_BlinkFrequency_Div128) || \ - ((FREQUENCY) == LCD_BlinkFrequency_Div256) || \ - ((FREQUENCY) == LCD_BlinkFrequency_Div512) || \ - ((FREQUENCY) == LCD_BlinkFrequency_Div1024)) -/** - * @} - */ - -/** @defgroup LCD_Contrast - * @{ - */ - -#define LCD_Contrast_Level_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */ -#define LCD_Contrast_Level_1 ((uint32_t)0x00000400) /*!< Maximum Voltage = 2.73V */ -#define LCD_Contrast_Level_2 ((uint32_t)0x00000800) /*!< Maximum Voltage = 2.86V */ -#define LCD_Contrast_Level_3 ((uint32_t)0x00000C00) /*!< Maximum Voltage = 2.99V */ -#define LCD_Contrast_Level_4 ((uint32_t)0x00001000) /*!< Maximum Voltage = 3.12V */ -#define LCD_Contrast_Level_5 ((uint32_t)0x00001400) /*!< Maximum Voltage = 3.25V */ -#define LCD_Contrast_Level_6 ((uint32_t)0x00001800) /*!< Maximum Voltage = 3.38V */ -#define LCD_Contrast_Level_7 ((uint32_t)0x00001C00) /*!< Maximum Voltage = 3.51V */ - -#define IS_LCD_CONTRAST(CONTRAST) (((CONTRAST) == LCD_Contrast_Level_0) || \ - ((CONTRAST) == LCD_Contrast_Level_1) || \ - ((CONTRAST) == LCD_Contrast_Level_2) || \ - ((CONTRAST) == LCD_Contrast_Level_3) || \ - ((CONTRAST) == LCD_Contrast_Level_4) || \ - ((CONTRAST) == LCD_Contrast_Level_5) || \ - ((CONTRAST) == LCD_Contrast_Level_6) || \ - ((CONTRAST) == LCD_Contrast_Level_7)) -/** - * @} - */ - -/** @defgroup LCD_Flag - * @{ - */ - -#define LCD_FLAG_ENS LCD_SR_ENS -#define LCD_FLAG_SOF LCD_SR_SOF -#define LCD_FLAG_UDR LCD_SR_UDR -#define LCD_FLAG_UDD LCD_SR_UDD -#define LCD_FLAG_RDY LCD_SR_RDY -#define LCD_FLAG_FCRSF LCD_SR_FCRSR - -#define IS_LCD_GET_FLAG(FLAG) (((FLAG) == LCD_FLAG_ENS) || ((FLAG) == LCD_FLAG_SOF) || \ - ((FLAG) == LCD_FLAG_UDR) || ((FLAG) == LCD_FLAG_UDD) || \ - ((FLAG) == LCD_FLAG_RDY) || ((FLAG) == LCD_FLAG_FCRSF)) - -#define IS_LCD_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF5) == 0x00) && ((FLAG) != 0x00)) -/** - * @} - */ - -/** @defgroup LCD_RAMRegister - * @{ - */ - -#define LCD_RAMRegister_0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */ -#define LCD_RAMRegister_1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */ -#define LCD_RAMRegister_2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */ -#define LCD_RAMRegister_3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */ -#define LCD_RAMRegister_4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */ -#define LCD_RAMRegister_5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */ -#define LCD_RAMRegister_6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */ -#define LCD_RAMRegister_7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */ -#define LCD_RAMRegister_8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */ -#define LCD_RAMRegister_9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */ -#define LCD_RAMRegister_10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */ -#define LCD_RAMRegister_11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */ -#define LCD_RAMRegister_12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */ -#define LCD_RAMRegister_13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */ -#define LCD_RAMRegister_14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */ -#define LCD_RAMRegister_15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */ - -#define IS_LCD_RAM_REGISTER(REGISTER) (((REGISTER) == LCD_RAMRegister_0) || \ - ((REGISTER) == LCD_RAMRegister_1) || \ - ((REGISTER) == LCD_RAMRegister_2) || \ - ((REGISTER) == LCD_RAMRegister_3) || \ - ((REGISTER) == LCD_RAMRegister_4) || \ - ((REGISTER) == LCD_RAMRegister_5) || \ - ((REGISTER) == LCD_RAMRegister_6) || \ - ((REGISTER) == LCD_RAMRegister_7) || \ - ((REGISTER) == LCD_RAMRegister_8) || \ - ((REGISTER) == LCD_RAMRegister_9) || \ - ((REGISTER) == LCD_RAMRegister_10) || \ - ((REGISTER) == LCD_RAMRegister_11) || \ - ((REGISTER) == LCD_RAMRegister_12) || \ - ((REGISTER) == LCD_RAMRegister_13) || \ - ((REGISTER) == LCD_RAMRegister_14) || \ - ((REGISTER) == LCD_RAMRegister_15)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the LCD configuration to the default reset state *****/ -void LCD_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void LCD_Init(LCD_InitTypeDef* LCD_InitStruct); -void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct); -void LCD_Cmd(FunctionalState NewState); -void LCD_WaitForSynchro(void); -void LCD_HighDriveCmd(FunctionalState NewState); -void LCD_MuxSegmentCmd(FunctionalState NewState); -void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration); -void LCD_DeadTimeConfig(uint32_t LCD_DeadTime); -void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency); -void LCD_ContrastConfig(uint32_t LCD_Contrast); - -/* LCD RAM memory write functions *********************************************/ -void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data); -void LCD_UpdateDisplayRequest(void); - -/* Interrupts and flags management functions **********************************/ -void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState); -FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG); -void LCD_ClearFlag(uint32_t LCD_FLAG); -ITStatus LCD_GetITStatus(uint32_t LCD_IT); -void LCD_ClearITPendingBit(uint32_t LCD_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_LCD_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_pwr.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_pwr.h deleted file mode 100644 index ae2adb74a..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_pwr.h +++ /dev/null @@ -1,207 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_pwr.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_PWR_H -#define __STM32L1xx_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PVD_detection_level - * @{ - */ - -#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 /* External input analog voltage - (Compare internally to VREFINT) */ -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ - ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ - ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ - ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) -/** - * @} - */ - -/** @defgroup WakeUp_Pins - * @{ - */ - -#define PWR_WakeUpPin_1 ((uint32_t)0x00000000) -#define PWR_WakeUpPin_2 ((uint32_t)0x00000004) -#define PWR_WakeUpPin_3 ((uint32_t)0x00000008) -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \ - ((PIN) == PWR_WakeUpPin_2) || \ - ((PIN) == PWR_WakeUpPin_3)) -/** - * @} - */ - - -/** @defgroup Voltage_Scaling_Ranges - * @{ - */ - -#define PWR_VoltageScaling_Range1 PWR_CR_VOS_0 -#define PWR_VoltageScaling_Range2 PWR_CR_VOS_1 -#define PWR_VoltageScaling_Range3 PWR_CR_VOS - -#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_VoltageScaling_Range1) || \ - ((RANGE) == PWR_VoltageScaling_Range2) || \ - ((RANGE) == PWR_VoltageScaling_Range3)) -/** - * @} - */ - -/** @defgroup Regulator_state_is_Sleep_STOP_mode - * @{ - */ - -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower PWR_CR_LPSDSR -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ - ((REGULATOR) == PWR_Regulator_LowPower)) -/** - * @} - */ - -/** @defgroup SLEEP_mode_entry - * @{ - */ - -#define PWR_SLEEPEntry_WFI ((uint8_t)0x01) -#define PWR_SLEEPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE)) - -/** - * @} - */ - -/** @defgroup STOP_mode_entry - * @{ - */ - -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) - -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ - -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO -#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF -#define PWR_FLAG_VOS PWR_CSR_VOSF -#define PWR_FLAG_REGLP PWR_CSR_REGLPF - -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \ - ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP)) - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the PWR configuration to the default reset state ******/ -void PWR_DeInit(void); - -/* RTC Domain Access function *************************************************/ -void PWR_RTCAccessCmd(FunctionalState NewState); - -/* PVD configuration functions ************************************************/ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_PVDCmd(FunctionalState NewState); - -/* WakeUp pins configuration functions ****************************************/ -void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState); - -/* Ultra Low Power mode configuration functions *******************************/ -void PWR_FastWakeUpCmd(FunctionalState NewState); -void PWR_UltraLowPowerCmd(FunctionalState NewState); - -/* Voltage Scaling configuration functions ************************************/ -void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling); - -/* Low Power modes configuration functions ************************************/ -void PWR_EnterLowPowerRunMode(FunctionalState NewState); -void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry); -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); - -/* Flags management functions *************************************************/ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_PWR_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_rcc.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_rcc.h deleted file mode 100644 index d73c2aa1d..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_rcc.h +++ /dev/null @@ -1,468 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_rcc.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the RCC - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_RCC_H -#define __STM32L1xx_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -typedef struct -{ - uint32_t SYSCLK_Frequency; - uint32_t HCLK_Frequency; - uint32_t PCLK1_Frequency; - uint32_t PCLK2_Frequency; -}RCC_ClocksTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup HSE_configuration - * @{ - */ - -#define RCC_HSE_OFF ((uint8_t)0x00) -#define RCC_HSE_ON ((uint8_t)0x01) -#define RCC_HSE_Bypass ((uint8_t)0x05) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) - -/** - * @} - */ - -/** @defgroup MSI_Clock_Range - * @{ - */ - -#define RCC_MSIRange_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */ -#define RCC_MSIRange_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */ -#define RCC_MSIRange_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */ -#define RCC_MSIRange_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */ -#define RCC_MSIRange_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */ -#define RCC_MSIRange_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */ -#define RCC_MSIRange_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */ - -#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_0) || \ - ((RANGE) == RCC_MSIRange_1) || \ - ((RANGE) == RCC_MSIRange_2) || \ - ((RANGE) == RCC_MSIRange_3) || \ - ((RANGE) == RCC_MSIRange_4) || \ - ((RANGE) == RCC_MSIRange_5) || \ - ((RANGE) == RCC_MSIRange_6)) - -/** - * @} - */ - -/** @defgroup PLL_Clock_Source - * @{ - */ - -#define RCC_PLLSource_HSI ((uint8_t)0x00) -#define RCC_PLLSource_HSE ((uint8_t)0x01) - -#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ - ((SOURCE) == RCC_PLLSource_HSE)) -/** - * @} - */ - -/** @defgroup PLL_Multiplication_Factor - * @{ - */ - -#define RCC_PLLMul_3 ((uint8_t)0x00) -#define RCC_PLLMul_4 ((uint8_t)0x04) -#define RCC_PLLMul_6 ((uint8_t)0x08) -#define RCC_PLLMul_8 ((uint8_t)0x0C) -#define RCC_PLLMul_12 ((uint8_t)0x10) -#define RCC_PLLMul_16 ((uint8_t)0x14) -#define RCC_PLLMul_24 ((uint8_t)0x18) -#define RCC_PLLMul_32 ((uint8_t)0x1C) -#define RCC_PLLMul_48 ((uint8_t)0x20) - - -#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \ - ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \ - ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \ - ((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \ - ((MUL) == RCC_PLLMul_48)) -/** - * @} - */ - -/** @defgroup PLL_Divider_Factor - * @{ - */ - -#define RCC_PLLDiv_2 ((uint8_t)0x40) -#define RCC_PLLDiv_3 ((uint8_t)0x80) -#define RCC_PLLDiv_4 ((uint8_t)0xC0) - - -#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \ - ((DIV) == RCC_PLLDiv_4)) -/** - * @} - */ - -/** @defgroup System_Clock_Source - * @{ - */ - -#define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI -#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI -#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE -#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup AHB_Clock_Source - * @{ - */ - -#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1 -#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2 -#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4 -#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8 -#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16 -#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64 -#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128 -#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256 -#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512 -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup APB1_APB2_Clock_Source - * @{ - */ - -#define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1 -#define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2 -#define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4 -#define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8 -#define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16 -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - - -/** @defgroup RCC_Interrupt_Source - * @{ - */ - -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_MSIRDY ((uint8_t)0x20) -#define RCC_IT_CSS ((uint8_t)0x80) - -#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) - -#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \ - ((IT) == RCC_IT_CSS)) - -#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) - -/** - * @} - */ - -/** @defgroup LSE_Configuration - * @{ - */ - -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x05) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RTC_Clock_Source - * @{ - */ - -#define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE -#define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI -#define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE -#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0) -#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1) -#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE) -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div16)) -/** - * @} - */ - -/** @defgroup AHB_Peripherals - * @{ - */ - -#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN -#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN -#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN -#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN -#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN -#define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN -#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN -#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN -#define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN -#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN - -#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEFF6FC0) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xFEFE6FC0) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup APB2_Peripherals - * @{ - */ - -#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN -#define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN -#define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN -#define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN -#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN -#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN -#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN - -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFADE2) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup APB1_Peripherals - * @{ - */ - -#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN -#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN -#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN -#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN -#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN -#define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN -#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN -#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN -#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN -#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN -#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN -#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN -#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN -#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN -#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN -#define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN - -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F19B5C8) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup MCO_Clock_Source - * @{ - */ - -#define RCC_MCOSource_NoClock ((uint8_t)0x00) -#define RCC_MCOSource_SYSCLK ((uint8_t)0x01) -#define RCC_MCOSource_HSI ((uint8_t)0x02) -#define RCC_MCOSource_MSI ((uint8_t)0x03) -#define RCC_MCOSource_HSE ((uint8_t)0x04) -#define RCC_MCOSource_PLLCLK ((uint8_t)0x05) -#define RCC_MCOSource_LSI ((uint8_t)0x06) -#define RCC_MCOSource_LSE ((uint8_t)0x07) - -#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \ - ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_MSI) || \ - ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK) || \ - ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE)) -/** - * @} - */ - -/** @defgroup MCO_Output_Divider - * @{ - */ - -#define RCC_MCODiv_1 ((uint8_t)0x00) -#define RCC_MCODiv_2 ((uint8_t)0x10) -#define RCC_MCODiv_4 ((uint8_t)0x20) -#define RCC_MCODiv_8 ((uint8_t)0x30) -#define RCC_MCODiv_16 ((uint8_t)0x40) - -#define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \ - ((DIV) == RCC_MCODiv_4) || ((DIV) == RCC_MCODiv_8) || \ - ((DIV) == RCC_MCODiv_16)) -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ - -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_MSIRDY ((uint8_t)0x29) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_LSERDY ((uint8_t)0x49) -#define RCC_FLAG_LSIRDY ((uint8_t)0x41) -#define RCC_FLAG_OBLRST ((uint8_t)0x59) -#define RCC_FLAG_PINRST ((uint8_t)0x5A) -#define RCC_FLAG_PORRST ((uint8_t)0x5B) -#define RCC_FLAG_SFTRST ((uint8_t)0x5C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x5D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x5E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x5F) - -#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \ - ((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \ - ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ - ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ - ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ - ((FLAG) == RCC_FLAG_WWDGRST)) - -#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the RCC clock configuration to the default reset state */ -void RCC_DeInit(void); - -/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ -void RCC_HSEConfig(uint8_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_MSIRangeConfig(uint32_t RCC_MSIRange); -void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue); -void RCC_MSICmd(FunctionalState NewState); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); -void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv); - -/* System, AHB and APB busses clocks configuration functions ******************/ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); - -/* Peripheral clocks configuration functions **********************************/ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_RTCResetCmd(FunctionalState NewState); - -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); - -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); - -void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_RCC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_rtc.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_rtc.h deleted file mode 100644 index 65979deda..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_rtc.h +++ /dev/null @@ -1,611 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_rtc.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_RTC_H -#define __STM32L1xx_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief RTC Init structures definition - */ -typedef struct -{ - uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be set to a value lower than 0x7F */ - - uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be set to a value lower than 0x1FFF */ -}RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. - This parameter must be set to a value in the 0-12 range - if the RTC_HourFormat_12 is selected or 0-23 range if - the RTC_HourFormat_24 is selected. */ - - uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ -}RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint32_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint32_t RTC_Month; /*!< Specifies the RTC Date Month. - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t RTC_Date; /*!< Specifies the RTC Date. - This parameter must be set to a value in the 1-31 range. */ - - uint8_t RTC_Year; /*!< Specifies the RTC Date Year. - This parameter must be set to a value in the 0-99 range. */ -}RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ - - uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - - uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - This parameter must be set to a value in the 1-31 range - if the Alarm Date is selected. - This parameter can be a value of @ref RTC_WeekDay_Definitions - if the Alarm WeekDay is selected. */ -}RTC_AlarmTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - - -/** @defgroup RTC_Hour_Formats - * @{ - */ -#define RTC_HourFormat_24 ((uint32_t)0x00000000) -#define RTC_HourFormat_12 ((uint32_t)0x00000040) -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ - ((FORMAT) == RTC_HourFormat_24)) -/** - * @} - */ - -/** @defgroup RTC_Asynchronous_Predivider - * @{ - */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) - -/** - * @} - */ - - -/** @defgroup RTC_Synchronous_Predivider - * @{ - */ -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FFF) - -/** - * @} - */ - -/** @defgroup RTC_Time_Definitions - * @{ - */ -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) - -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions - * @{ - */ -#define RTC_H12_AM ((uint8_t)0x00) -#define RTC_H12_PM ((uint8_t)0x40) -#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) - -/** - * @} - */ - -/** @defgroup RTC_Year_Date_Definitions - * @{ - */ -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) - -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions - * @{ - */ -#define RTC_Month_January ((uint32_t)0x00000001) -#define RTC_Month_February ((uint32_t)0x00000002) -#define RTC_Month_March ((uint32_t)0x00000003) -#define RTC_Month_April ((uint32_t)0x00000004) -#define RTC_Month_May ((uint32_t)0x00000005) -#define RTC_Month_June ((uint32_t)0x00000006) -#define RTC_Month_July ((uint32_t)0x00000007) -#define RTC_Month_August ((uint32_t)0x00000008) -#define RTC_Month_September ((uint32_t)0x00000009) -#define RTC_Month_October ((uint32_t)0x00000010) -#define RTC_Month_November ((uint32_t)0x00000011) -#define RTC_Month_December ((uint32_t)0x00000012) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) - -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions - * @{ - */ - -#define RTC_Weekday_Monday ((uint32_t)0x00000001) -#define RTC_Weekday_Tuesday ((uint32_t)0x00000002) -#define RTC_Weekday_Wednesday ((uint32_t)0x00000003) -#define RTC_Weekday_Thursday ((uint32_t)0x00000004) -#define RTC_Weekday_Friday ((uint32_t)0x00000005) -#define RTC_Weekday_Saturday ((uint32_t)0x00000006) -#define RTC_Weekday_Sunday ((uint32_t)0x00000007) -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) -/** - * @} - */ - - -/** @defgroup RTC_Alarm_Definitions - * @{ - */ -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmDateWeekDay_Definitions - * @{ - */ -#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) -#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ - ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmMask_Definitions - * @{ - */ -#define RTC_AlarmMask_None ((uint32_t)0x00000000) -#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) -#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) -#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) -#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) -#define RTC_AlarmMask_All ((uint32_t)0x80808080) -#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions - * @{ - */ -#define RTC_Alarm_A ((uint32_t)0x00000100) -#define RTC_Alarm_B ((uint32_t)0x00000200) -#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) -#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Wakeup_Timer_Definitions - * @{ - */ -#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) -#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) -#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) -#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) -#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) -#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) -/** - * @} - */ - -/** @defgroup RTC_Time_Stamp_Edges_definitions - * @{ - */ -#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) -#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) -#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ - ((EDGE) == RTC_TimeStampEdge_Falling)) -/** - * @} - */ - -/** @defgroup RTC_Output_selection_Definitions - * @{ - */ -#define RTC_Output_Disable ((uint32_t)0x00000000) -#define RTC_Output_AlarmA ((uint32_t)0x00200000) -#define RTC_Output_AlarmB ((uint32_t)0x00400000) -#define RTC_Output_WakeUp ((uint32_t)0x00600000) - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ - ((OUTPUT) == RTC_Output_AlarmA) || \ - ((OUTPUT) == RTC_Output_AlarmB) || \ - ((OUTPUT) == RTC_Output_WakeUp)) - -/** - * @} - */ - -/** @defgroup RTC_Output_Polarity_Definitions - * @{ - */ -#define RTC_OutputPolarity_High ((uint32_t)0x00000000) -#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ - ((POL) == RTC_OutputPolarity_Low)) -/** - * @} - */ - - -/** @defgroup RTC_Digital_Calibration_Definitions - * @{ - */ -#define RTC_CalibSign_Positive ((uint32_t)0x00000000) -#define RTC_CalibSign_Negative ((uint32_t)0x00000080) -#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ - ((SIGN) == RTC_CalibSign_Negative)) -#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) - -/** - * @} - */ - - -/** @defgroup RTC_DayLightSaving_Definitions - * @{ - */ -#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) -#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ - ((SAVE) == RTC_DayLightSaving_ADD1H)) - -#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) -#define RTC_StoreOperation_Set ((uint32_t)0x00040000) -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ - ((OPERATION) == RTC_StoreOperation_Set)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Trigger_Definitions - * @{ - */ -#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) -#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_FallingEdge)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pins_Definitions - * @{ - */ -#define RTC_Tamper_1 RTC_TAFCR_TAMP1E -#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1)) - -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT - * @{ - */ -#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) -#define RTC_OutputType_PushPull ((uint32_t)0x00040000) -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ - ((TYPE) == RTC_OutputType_PushPull)) - -/** - * @} - */ - -/** @defgroup RTC_Backup_Registers_Definitions - * @{ - */ - -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ - ((BKP) == RTC_BKP_DR1) || \ - ((BKP) == RTC_BKP_DR2) || \ - ((BKP) == RTC_BKP_DR3) || \ - ((BKP) == RTC_BKP_DR4) || \ - ((BKP) == RTC_BKP_DR5) || \ - ((BKP) == RTC_BKP_DR6) || \ - ((BKP) == RTC_BKP_DR7) || \ - ((BKP) == RTC_BKP_DR8) || \ - ((BKP) == RTC_BKP_DR9) || \ - ((BKP) == RTC_BKP_DR10) || \ - ((BKP) == RTC_BKP_DR11) || \ - ((BKP) == RTC_BKP_DR12) || \ - ((BKP) == RTC_BKP_DR13) || \ - ((BKP) == RTC_BKP_DR14) || \ - ((BKP) == RTC_BKP_DR15) || \ - ((BKP) == RTC_BKP_DR16) || \ - ((BKP) == RTC_BKP_DR17) || \ - ((BKP) == RTC_BKP_DR18) || \ - ((BKP) == RTC_BKP_DR19)) -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions - * @{ - */ -#define RTC_Format_BIN ((uint32_t)0x000000000) -#define RTC_Format_BCD ((uint32_t)0x000000001) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) - -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions - * @{ - */ -#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) -#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) -#define RTC_FLAG_TSF ((uint32_t)0x00000800) -#define RTC_FLAG_WUTF ((uint32_t)0x00000400) -#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) -#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) -#define RTC_FLAG_INITF ((uint32_t)0x00000040) -#define RTC_FLAG_RSF ((uint32_t)0x00000020) -#define RTC_FLAG_INITS ((uint32_t)0x00000010) -#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) -#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) -#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ - ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ - ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ - ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ - ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ - ((FLAG) == RTC_FLAG_TAMP1F)) -#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFC0DF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions - * @{ - */ -#define RTC_IT_TS ((uint32_t)0x00008000) -#define RTC_IT_WUT ((uint32_t)0x00004000) -#define RTC_IT_ALRB ((uint32_t)0x00002000) -#define RTC_IT_ALRA ((uint32_t)0x00001000) -#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)0x00020000) - -#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ - ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ - ((IT) == RTC_IT_TAMP1)) -#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the RTC configuration to the default reset state *****/ -ErrorStatus RTC_DeInit(void); - - -/* Initialization and Configuration functions *********************************/ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); -void RTC_WriteProtectionCmd(FunctionalState NewState); -ErrorStatus RTC_EnterInitMode(void); -void RTC_ExitInitMode(void); -ErrorStatus RTC_WaitForSynchro(void); -ErrorStatus RTC_RefClockCmd(FunctionalState NewState); - -/* Time and Date configuration functions **************************************/ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); - -/* Alarms (Alarm A and Alarm B) configuration functions **********************/ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); - -/* WakeUp Timer configuration functions ***************************************/ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); -uint32_t RTC_GetWakeUpCounter(void); -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); - -/* Daylight Saving configuration functions ************************************/ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); -uint32_t RTC_GetStoreOperation(void); - -/* Output pin Configuration function ******************************************/ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); - -/* Digital Calibration configuration functions ********************************/ -ErrorStatus RTC_DigitalCalibConfig(uint32_t RTC_CalibSign, uint32_t Value); -ErrorStatus RTC_DigitalCalibCmd(FunctionalState NewState); -void RTC_CalibOutputCmd(FunctionalState NewState); - -/* TimeStamp configuration functions ******************************************/ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct); - - -/* Tampers configuration functions ********************************************/ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); - -/* Backup Data Registers configuration functions ******************************/ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); - -/* Output Type Config configuration functions *********************************/ -void RTC_OutputTypeConfig(uint32_t RTC_OutputType); - - -/* Interrupts and flags management functions **********************************/ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); -void RTC_ClearFlag(uint32_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint32_t RTC_IT); -void RTC_ClearITPendingBit(uint32_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32L1xx_RTC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_spi.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_spi.h deleted file mode 100644 index 335bec493..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_spi.h +++ /dev/null @@ -1,379 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_spi.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the SPI - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_SPI_H -#define __STM32L1xx_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be any combination of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. - This parameter can be any combination of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be any combination of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be any combination of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be any combination of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be any combination of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be any combination of @ref SPI_BaudRate_Prescaler. - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be any combination of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2)) - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ - ((DATASIZE) == SPI_DataSize_8b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) -#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ - -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) - -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) - -#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) - -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ - ((IT) == SPI_I2S_IT_OVR)) -/** - * @} - */ - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) -#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** @defgroup SPI_I2S_Legacy - * @{ - */ - -#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx -#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx -#define SPI_IT_TXE SPI_I2S_IT_TXE -#define SPI_IT_RXNE SPI_I2S_IT_RXNE -#define SPI_IT_ERR SPI_I2S_IT_ERR -#define SPI_IT_OVR SPI_I2S_IT_OVR -#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE -#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE -#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR -#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY -#define SPI_DeInit SPI_I2S_DeInit -#define SPI_ITConfig SPI_I2S_ITConfig -#define SPI_DMACmd SPI_I2S_DMACmd -#define SPI_SendData SPI_I2S_SendData -#define SPI_ReceiveData SPI_I2S_ReceiveData -#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus -#define SPI_ClearFlag SPI_I2S_ClearFlag -#define SPI_GetITStatus SPI_I2S_GetITStatus -#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the SPI configuration to the default reset state *****/ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); - -/* Initialization and Configuration functions *********************************/ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); - -/* Hardware CRC Calculation functions *****************************************/ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); - -/* DMA transfers management functions *****************************************/ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32L1xx_SPI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_syscfg.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_syscfg.h deleted file mode 100644 index 4b9229665..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_syscfg.h +++ /dev/null @@ -1,387 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_syscfg.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the SYSCFG - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/*!< Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_SYSCFG_H -#define __STM32L1xx_SYSCFG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/*!< Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SYSCFG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SYSCFG_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_Port_Sources - * @{ - */ -#define EXTI_PortSourceGPIOA ((uint8_t)0x00) -#define EXTI_PortSourceGPIOB ((uint8_t)0x01) -#define EXTI_PortSourceGPIOC ((uint8_t)0x02) -#define EXTI_PortSourceGPIOD ((uint8_t)0x03) -#define EXTI_PortSourceGPIOE ((uint8_t)0x04) -#define EXTI_PortSourceGPIOH ((uint8_t)0x05) - -#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOH)) -/** - * @} - */ - -/** @defgroup EXTI_Pin_sources - * @{ - */ -#define EXTI_PinSource0 ((uint8_t)0x00) -#define EXTI_PinSource1 ((uint8_t)0x01) -#define EXTI_PinSource2 ((uint8_t)0x02) -#define EXTI_PinSource3 ((uint8_t)0x03) -#define EXTI_PinSource4 ((uint8_t)0x04) -#define EXTI_PinSource5 ((uint8_t)0x05) -#define EXTI_PinSource6 ((uint8_t)0x06) -#define EXTI_PinSource7 ((uint8_t)0x07) -#define EXTI_PinSource8 ((uint8_t)0x08) -#define EXTI_PinSource9 ((uint8_t)0x09) -#define EXTI_PinSource10 ((uint8_t)0x0A) -#define EXTI_PinSource11 ((uint8_t)0x0B) -#define EXTI_PinSource12 ((uint8_t)0x0C) -#define EXTI_PinSource13 ((uint8_t)0x0D) -#define EXTI_PinSource14 ((uint8_t)0x0E) -#define EXTI_PinSource15 ((uint8_t)0x0F) -#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ - ((PINSOURCE) == EXTI_PinSource1) || \ - ((PINSOURCE) == EXTI_PinSource2) || \ - ((PINSOURCE) == EXTI_PinSource3) || \ - ((PINSOURCE) == EXTI_PinSource4) || \ - ((PINSOURCE) == EXTI_PinSource5) || \ - ((PINSOURCE) == EXTI_PinSource6) || \ - ((PINSOURCE) == EXTI_PinSource7) || \ - ((PINSOURCE) == EXTI_PinSource8) || \ - ((PINSOURCE) == EXTI_PinSource9) || \ - ((PINSOURCE) == EXTI_PinSource10) || \ - ((PINSOURCE) == EXTI_PinSource11) || \ - ((PINSOURCE) == EXTI_PinSource12) || \ - ((PINSOURCE) == EXTI_PinSource13) || \ - ((PINSOURCE) == EXTI_PinSource14) || \ - ((PINSOURCE) == EXTI_PinSource15)) -/** - * @} - */ - -/** @defgroup SYSCFG_Memory_Remap_Config - * @{ - */ -#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) -#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) -#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) - -#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM)) - -/** - * @} - */ - -/** @defgroup RI_Resistor - * @{ - */ - -#define RI_Resistor_10KPU COMP_CSR_10KPU -#define RI_Resistor_400KPU COMP_CSR_400KPU -#define RI_Resistor_10KPD COMP_CSR_10KPD -#define RI_Resistor_400KPD COMP_CSR_400KPD - -#define IS_RI_RESISTOR(RESISTOR) (((RESISTOR) == COMP_CSR_10KPU) || \ - ((RESISTOR) == COMP_CSR_400KPU) || \ - ((RESISTOR) == COMP_CSR_10KPD) || \ - ((RESISTOR) == COMP_CSR_400KPD)) - -/** - * @} - */ - -/** @defgroup RI_InputCapture - * @{ - */ - -#define RI_InputCapture_IC1 RI_ICR_IC1 /*!< Input Capture 1 */ -#define RI_InputCapture_IC2 RI_ICR_IC2 /*!< Input Capture 2 */ -#define RI_InputCapture_IC3 RI_ICR_IC3 /*!< Input Capture 3 */ -#define RI_InputCapture_IC4 RI_ICR_IC4 /*!< Input Capture 4 */ - -#define IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00)) -/** - * @} - */ - -/** @defgroup TIM_Select - * @{ - */ - -#define TIM_Select_None ((uint32_t)0x00000000) /*!< None selected */ -#define TIM_Select_TIM2 ((uint32_t)0x00010000) /*!< Timer 2 selected */ -#define TIM_Select_TIM3 ((uint32_t)0x00020000) /*!< Timer 3 selected */ -#define TIM_Select_TIM4 ((uint32_t)0x00030000) /*!< Timer 4 selected */ - -#define IS_RI_TIM(TIM) (((TIM) == TIM_Select_None) || \ - ((TIM) == TIM_Select_TIM2) || \ - ((TIM) == TIM_Select_TIM3) || \ - ((TIM) == TIM_Select_TIM4)) - -/** - * @} - */ - -/** @defgroup RI_InputCaptureRouting - * @{ - */ - /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ -#define RI_InputCaptureRouting_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */ -#define RI_InputCaptureRouting_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */ -#define RI_InputCaptureRouting_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */ -#define RI_InputCaptureRouting_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */ -#define RI_InputCaptureRouting_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */ -#define RI_InputCaptureRouting_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */ -#define RI_InputCaptureRouting_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */ -#define RI_InputCaptureRouting_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */ -#define RI_InputCaptureRouting_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */ -#define RI_InputCaptureRouting_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */ -#define RI_InputCaptureRouting_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */ -#define RI_InputCaptureRouting_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */ -#define RI_InputCaptureRouting_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */ -#define RI_InputCaptureRouting_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */ -#define RI_InputCaptureRouting_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */ -#define RI_InputCaptureRouting_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */ - -#define IS_RI_INPUTCAPTURE_ROUTING(ROUTING) (((ROUTING) == RI_InputCaptureRouting_0) || \ - ((ROUTING) == RI_InputCaptureRouting_1) || \ - ((ROUTING) == RI_InputCaptureRouting_2) || \ - ((ROUTING) == RI_InputCaptureRouting_3) || \ - ((ROUTING) == RI_InputCaptureRouting_4) || \ - ((ROUTING) == RI_InputCaptureRouting_5) || \ - ((ROUTING) == RI_InputCaptureRouting_6) || \ - ((ROUTING) == RI_InputCaptureRouting_7) || \ - ((ROUTING) == RI_InputCaptureRouting_8) || \ - ((ROUTING) == RI_InputCaptureRouting_9) || \ - ((ROUTING) == RI_InputCaptureRouting_10) || \ - ((ROUTING) == RI_InputCaptureRouting_11) || \ - ((ROUTING) == RI_InputCaptureRouting_12) || \ - ((ROUTING) == RI_InputCaptureRouting_13) || \ - ((ROUTING) == RI_InputCaptureRouting_14) || \ - ((ROUTING) == RI_InputCaptureRouting_15)) - -/** - * @} - */ - -/** @defgroup RI_IOSwitch - * @{ - */ - -/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */ -#define RI_IOSwitch_CH0 ((uint32_t)0x80000001) -#define RI_IOSwitch_CH1 ((uint32_t)0x80000002) -#define RI_IOSwitch_CH2 ((uint32_t)0x80000004) -#define RI_IOSwitch_CH3 ((uint32_t)0x80000008) -#define RI_IOSwitch_CH4 ((uint32_t)0x80000010) -#define RI_IOSwitch_CH5 ((uint32_t)0x80000020) -#define RI_IOSwitch_CH6 ((uint32_t)0x80000040) -#define RI_IOSwitch_CH7 ((uint32_t)0x80000080) -#define RI_IOSwitch_CH8 ((uint32_t)0x80000100) -#define RI_IOSwitch_CH9 ((uint32_t)0x80000200) -#define RI_IOSwitch_CH10 ((uint32_t)0x80000400) -#define RI_IOSwitch_CH11 ((uint32_t)0x80000800) -#define RI_IOSwitch_CH12 ((uint32_t)0x80001000) -#define RI_IOSwitch_CH13 ((uint32_t)0x80002000) -#define RI_IOSwitch_CH14 ((uint32_t)0x80004000) -#define RI_IOSwitch_CH15 ((uint32_t)0x80008000) -#define RI_IOSwitch_CH18 ((uint32_t)0x80040000) -#define RI_IOSwitch_CH19 ((uint32_t)0x80080000) -#define RI_IOSwitch_CH20 ((uint32_t)0x80100000) -#define RI_IOSwitch_CH21 ((uint32_t)0x80200000) -#define RI_IOSwitch_CH22 ((uint32_t)0x80400000) -#define RI_IOSwitch_CH23 ((uint32_t)0x80800000) -#define RI_IOSwitch_CH24 ((uint32_t)0x81000000) -#define RI_IOSwitch_CH25 ((uint32_t)0x82000000) -#define RI_IOSwitch_VCOMP ((uint32_t)0x84000000) /* VCOMP is an internal switch used to connect - selected channel to COMP1 non inverting input */ - -/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */ -#define RI_IOSwitch_GR10_1 ((uint32_t)0x00000001) -#define RI_IOSwitch_GR10_2 ((uint32_t)0x00000002) -#define RI_IOSwitch_GR10_3 ((uint32_t)0x00000004) -#define RI_IOSwitch_GR10_4 ((uint32_t)0x00000008) -#define RI_IOSwitch_GR6_1 ((uint32_t)0x00000010) -#define RI_IOSwitch_GR6_2 ((uint32_t)0x00000020) -#define RI_IOSwitch_GR5_1 ((uint32_t)0x00000040) -#define RI_IOSwitch_GR5_2 ((uint32_t)0x00000080) -#define RI_IOSwitch_GR5_3 ((uint32_t)0x00000100) -#define RI_IOSwitch_GR4_1 ((uint32_t)0x00000200) -#define RI_IOSwitch_GR4_2 ((uint32_t)0x00000400) -#define RI_IOSwitch_GR4_3 ((uint32_t)0x00000800) - -#define IS_RI_IOSWITCH(IOSWITCH) (((IOSWITCH) == RI_IOSwitch_CH0) || \ - ((IOSWITCH) == RI_IOSwitch_CH1) || \ - ((IOSWITCH) == RI_IOSwitch_CH2) || \ - ((IOSWITCH) == RI_IOSwitch_CH3) || \ - ((IOSWITCH) == RI_IOSwitch_CH4) || \ - ((IOSWITCH) == RI_IOSwitch_CH5) || \ - ((IOSWITCH) == RI_IOSwitch_CH6) || \ - ((IOSWITCH) == RI_IOSwitch_CH7) || \ - ((IOSWITCH) == RI_IOSwitch_CH8) || \ - ((IOSWITCH) == RI_IOSwitch_CH9) || \ - ((IOSWITCH) == RI_IOSwitch_CH10) || \ - ((IOSWITCH) == RI_IOSwitch_CH11) || \ - ((IOSWITCH) == RI_IOSwitch_CH12) || \ - ((IOSWITCH) == RI_IOSwitch_CH13) || \ - ((IOSWITCH) == RI_IOSwitch_CH14) || \ - ((IOSWITCH) == RI_IOSwitch_CH15) || \ - ((IOSWITCH) == RI_IOSwitch_CH18) || \ - ((IOSWITCH) == RI_IOSwitch_CH19) || \ - ((IOSWITCH) == RI_IOSwitch_CH20) || \ - ((IOSWITCH) == RI_IOSwitch_CH21) || \ - ((IOSWITCH) == RI_IOSwitch_CH22) || \ - ((IOSWITCH) == RI_IOSwitch_CH23) || \ - ((IOSWITCH) == RI_IOSwitch_CH24) || \ - ((IOSWITCH) == RI_IOSwitch_CH25) || \ - ((IOSWITCH) == RI_IOSwitch_VCOMP) || \ - ((IOSWITCH) == RI_IOSwitch_GR10_1) || \ - ((IOSWITCH) == RI_IOSwitch_GR10_2) || \ - ((IOSWITCH) == RI_IOSwitch_GR10_3) || \ - ((IOSWITCH) == RI_IOSwitch_GR10_4) || \ - ((IOSWITCH) == RI_IOSwitch_GR6_1) || \ - ((IOSWITCH) == RI_IOSwitch_GR6_2) || \ - ((IOSWITCH) == RI_IOSwitch_GR5_1) || \ - ((IOSWITCH) == RI_IOSwitch_GR5_2) || \ - ((IOSWITCH) == RI_IOSwitch_GR5_3) || \ - ((IOSWITCH) == RI_IOSwitch_GR4_1) || \ - ((IOSWITCH) == RI_IOSwitch_GR4_2) || \ - ((IOSWITCH) == RI_IOSwitch_GR4_3)) - -/** - * @} - */ - -/** @defgroup RI_Port - * @{ - */ - -#define RI_PortA ((uint8_t)0x01) /*!< GPIOA selected */ -#define RI_PortB ((uint8_t)0x02) /*!< GPIOB selected */ -#define RI_PortC ((uint8_t)0x03) /*!< GPIOC selected */ -#define RI_PortD ((uint8_t)0x04) /*!< GPIOD selected */ -#define RI_PortE ((uint8_t)0x05) /*!< GPIOE selected */ - -#define IS_RI_PORT(PORT) (((PORT) == RI_PortA) || \ - ((PORT) == RI_PortB) || \ - ((PORT) == RI_PortC) || \ - ((PORT) == RI_PortD) || \ - ((PORT) == RI_PortE)) -/** - * @} - */ - -/** @defgroup RI_Pin define - * @{ - */ -#define RI_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ -#define RI_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ -#define RI_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ -#define RI_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ -#define RI_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ -#define RI_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ -#define RI_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ -#define RI_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ -#define RI_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ -#define RI_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ -#define RI_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ -#define RI_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ -#define RI_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ -#define RI_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ -#define RI_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ -#define RI_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ -#define RI_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ - -#define IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the RTC configuration to the default reset state *****/ -void SYSCFG_DeInit(void); -void SYSCFG_RIDeInit(void); - -/* SYSCFG Initialization and Configuration functions **************************/ -void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); -void SYSCFG_USBPuCmd(FunctionalState NewState); -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); - -/* RI Initialization and Configuration functions ******************************/ -void SYSCFG_RITIMSelect(uint32_t TIM_Select); -void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting); -void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState); -void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState); -void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState); -void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin, - FunctionalState NewState); -#ifdef __cplusplus -} -#endif - -#endif /*__STM32L1xx_SYSCFG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_tim.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_tim.h deleted file mode 100644 index a67ef9ac1..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_tim.h +++ /dev/null @@ -1,907 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_tim.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the TIM firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_TIM_H -#define __STM32L1xx_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief TIM Time Base Init structure definition - * @note This structure is used with all TIMx except for TIM6 and TIM7. - */ - -typedef struct -{ - uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - -} TIM_TimeBaseInitTypeDef; - -/** - * @brief TIM Output Compare Init structure definition - */ - -typedef struct -{ - uint16_t TIM_OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_state */ - - uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - -} TIM_OCInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -typedef struct -{ - - uint16_t TIM_Channel; /*!< Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup TIM_Exported_constants - * @{ - */ - -#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10) || \ - ((PERIPH) == TIM11)) - -/* LIST1: TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11 */ -#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10) || \ - ((PERIPH) == TIM11)) - -/* LIST3: TIM2, TIM3 and TIM4 */ -#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4)) - -/* LIST2: TIM2, TIM3, TIM4 and TIM9 */ -#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) ||\ - ((PERIPH) == TIM9)) - -/* LIST5: TIM2, TIM3, TIM4, TIM6, TIM7 and TIM9 */ -#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) ||\ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) ||\ - ((PERIPH) == TIM9)) - -/* LIST4: TIM2, TIM3, TIM4, TIM6 and TIM7 */ -#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) ||\ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7)) - -/* LIST6: TIM9, TIM10 and TIM11 */ -#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10) ||\ - ((PERIPH) == TIM11)) - - - -/** @defgroup TIM_Output_Compare_and_PWM_modes - * @{ - */ - -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2)) -#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_ForcedAction_Active) || \ - ((MODE) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode - * @{ - */ - -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ - ((MODE) == TIM_OPMode_Repetitive)) -/** - * @} - */ - -/** @defgroup TIM_Channel - * @{ - */ - -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3) || \ - ((CHANNEL) == TIM_Channel_4)) - -#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2)) - -/** - * @} - */ - -/** @defgroup TIM_Clock_Division_CKD - * @{ - */ - -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) -#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ - ((DIV) == TIM_CKD_DIV2) || \ - ((DIV) == TIM_CKD_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode - * @{ - */ - -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ - ((MODE) == TIM_CounterMode_Down) || \ - ((MODE) == TIM_CounterMode_CenterAligned1) || \ - ((MODE) == TIM_CounterMode_CenterAligned2) || \ - ((MODE) == TIM_CounterMode_CenterAligned3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity - * @{ - */ - -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ - ((POLARITY) == TIM_OCPolarity_Low)) -/** - * @} - */ - - -/** @defgroup TIM_Output_Compare_state - * @{ - */ - -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ - ((STATE) == TIM_OutputState_Enable)) -/** - * @} - */ - - -/** @defgroup TIM_Capture_Compare_state - * @{ - */ - -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) -#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ - ((CCX) == TIM_CCx_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity - * @{ - */ - -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)|| \ - ((POLARITY) == TIM_ICPolarity_BothEdge)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection - * @{ - */ - -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ - ((SELECTION) == TIM_ICSelection_IndirectTI) || \ - ((SELECTION) == TIM_ICSelection_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler - * @{ - */ - -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_interrupt_sources - * @{ - */ - -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_Trigger)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address - * @{ - */ - -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_DCR ((uint16_t)0x0012) -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_DCR)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length - * @{ - */ - -#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \ - ((LENGTH) == TIM_DMABurstLength_2Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_3Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_4Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_5Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_6Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_7Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_8Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_9Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_10Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_11Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_12Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_13Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_14Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_15Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_16Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_17Bytes) || \ - ((LENGTH) == TIM_DMABurstLength_18Bytes)) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources - * @{ - */ - -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Prescaler - * @{ - */ - -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) -#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Internal_Trigger_Selection - * @{ - */ - -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) -/** - * @} - */ - -/** @defgroup TIM_TIx_External_Clock_Source - * @{ - */ - -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Polarity - * @{ - */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) -#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ - ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) -/** - * @} - */ - -/** @defgroup TIM_Prescaler_Reload_Mode - * @{ - */ - -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) -#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ - ((RELOAD) == TIM_PSCReloadMode_Immediate)) -/** - * @} - */ - -/** @defgroup TIM_Forced_Action - * @{ - */ - -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) -#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ - ((ACTION) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode - * @{ - */ - -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ - ((MODE) == TIM_EncoderMode_TI2) || \ - ((MODE) == TIM_EncoderMode_TI12)) -/** - * @} - */ - - -/** @defgroup TIM_Event_Source - * @{ - */ - -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_Update_Source - * @{ - */ - -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ -#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ - ((SOURCE) == TIM_UpdateSource_Regular)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Preload_State - * @{ - */ - -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) -#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ - ((STATE) == TIM_OCPreload_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Fast_State - * @{ - */ - -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) -#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ - ((STATE) == TIM_OCFast_Disable)) - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Clear_State - * @{ - */ - -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) -#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ - ((STATE) == TIM_OCClear_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Output_Source - * @{ - */ - -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ - ((SOURCE) == TIM_TRGOSource_Enable) || \ - ((SOURCE) == TIM_TRGOSource_Update) || \ - ((SOURCE) == TIM_TRGOSource_OC1) || \ - ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC4Ref)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode - * @{ - */ - -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ - ((MODE) == TIM_SlaveMode_Gated) || \ - ((MODE) == TIM_SlaveMode_Trigger) || \ - ((MODE) == TIM_SlaveMode_External1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode - * @{ - */ - -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ - ((STATE) == TIM_MasterSlaveMode_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Flags - * @{ - */ - -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) -#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_Trigger) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) -#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value - * @{ - */ - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Filter - * @{ - */ - -#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_OCReferenceClear - * @{ - */ -#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008) -#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000) -#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \ - ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) - -/** - * @} - */ - -/** @defgroup TIM_Remap - * @{ - */ - -#define TIM9_GPIO ((uint16_t)0x0000) -#define TIM9_LSE ((uint16_t)0x0001) - -#define TIM10_GPIO ((uint16_t)0x0000) -#define TIM10_LSI ((uint16_t)0x0001) -#define TIM10_LSE ((uint16_t)0x0002) -#define TIM10_RTC ((uint16_t)0x0003) - -#define TIM11_GPIO ((uint16_t)0x0000) -#define TIM11_MSI ((uint16_t)0x0001) -#define TIM11_HSE_RTC ((uint16_t)0x0002) - -#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM9_GPIO)||\ - ((TIM_REMAP) == TIM9_LSE)||\ - ((TIM_REMAP) == TIM10_GPIO)||\ - ((TIM_REMAP) == TIM10_LSI)||\ - ((TIM_REMAP) == TIM10_LSE)||\ - ((TIM_REMAP) == TIM10_RTC)||\ - ((TIM_REMAP) == TIM11_GPIO)||\ - ((TIM_REMAP) == TIM11_MSI)||\ - ((TIM_REMAP) == TIM11_HSE_RTC)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* TimeBase management ********************************************************/ -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Output Compare management **************************************************/ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); - -/* Input Capture management ***************************************************/ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); - -/* Interrupts, DMA and flags management ***************************************/ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Clocks management **********************************************************/ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); - - -/* Synchronization management *************************************************/ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - -/* Specific interface management **********************************************/ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Specific remapping management **********************************************/ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); - - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32L1xx_TIM_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_usart.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_usart.h deleted file mode 100644 index a5bc386d6..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_usart.h +++ /dev/null @@ -1,403 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_usart.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_USART_H -#define __STM32L1xx_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ - - uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - - uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3)) - -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_0_5) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) -#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @{ - */ - -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE ((uint16_t)0x0360) -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) -#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ - -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) -#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ - (((LENGTH) == USART_LINBreakDetectLength_10b) || \ - ((LENGTH) == USART_LINBreakDetectLength_11b)) -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ - -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) - -#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901)) -#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the USART configuration to the default reset state ***/ -void USART_DeInit(USART_TypeDef* USARTx); - -/* Initialization and Configuration functions *********************************/ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); - -/* Multi-Processor Communication functions ************************************/ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* LIN mode functions *********************************************************/ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SendBreak(USART_TypeDef* USARTx); - -/* Half-duplex mode function **************************************************/ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Smartcard mode functions ***************************************************/ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); - -/* IrDA mode functions ********************************************************/ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* DMA transfers management functions *****************************************/ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_USART_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/inc/stm32l1xx/stm32l1xx_wwdg.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_wwdg.h deleted file mode 100644 index d00e42ac1..000000000 --- a/example/libs_stm/inc/stm32l1xx/stm32l1xx_wwdg.h +++ /dev/null @@ -1,104 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_wwdg.h - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file contains all the functions prototypes for the WWDG - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_WWDG_H -#define __STM32L1xx_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Constants - * @{ - */ - -/** @defgroup WWDG_Prescaler - * @{ - */ - -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) -#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ - ((PRESCALER) == WWDG_Prescaler_2) || \ - ((PRESCALER) == WWDG_Prescaler_4) || \ - ((PRESCALER) == WWDG_Prescaler_8)) -#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) -#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Function used to set the WWDG configuration to the default reset state ****/ -void WWDG_DeInit(void); - -/* Prescaler, Refresh window and Counter configuration functions **************/ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); - -/* WWDG activation functions **************************************************/ -void WWDG_Enable(uint8_t Counter); - -/* Interrupts and flags management functions **********************************/ -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_WWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/Release_Notes_for_STM32F10x_StdPeriph_Driver.html b/example/libs_stm/src/stm32f10x/Release_Notes_for_STM32F10x_StdPeriph_Driver.html deleted file mode 100644 index 018141b98..000000000 --- a/example/libs_stm/src/stm32f10x/Release_Notes_for_STM32F10x_StdPeriph_Driver.html +++ /dev/null @@ -1,203 +0,0 @@ - - - - - - -Release Notes for STM32F10x Standard Peripherals Library Drivers - - - - - -
-


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Back to Release page
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Release -Notes for STM32F10x Standard Peripherals Library Drivers -(StdPeriph_Driver)

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Copyright 2010 STMicroelectronics

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Contents

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  1. STM32F10x Standard Peripherals Library -Drivers update History
    2. -
  2. License
    3. -
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STM32F10x Standard -Peripherals Library Drivers  update History

3.3.0 -- 04/16/2010

-
  1. General
-
  • Add support for STM32F10x XL-density devices.
  • I2C driver: events description and management enhancement.
-
  1. STM32F10x_StdPeriph_Driver
-
  • stm32f10x_dbgmcu.h/.c
    • DBGMCU_Config() function: add new values DBGMCU_TIMx_STOP (x: 9..14) for DBGMCU_Periph parameter.
  • stm32f10x_flash.h/.c: -updated to support Bank2 of XL-density devices (up to 1MByte of Flash -memory). For more details, refer to the description provided within -stm32f10x_flash.c file.
  • stm32f10x_gpio.h/.c
    • GPIO_PinRemapConfig() function: add new values for GPIO_Remap parameter, to support new remap for FSMC_NADV pin and TIM9..11,13,14.
  • stm32f10x_i2c.h/.c: I2C events description and management enhancement.
    • I2C_CheckEvent() -function: updated to check whether the last event contains the -I2C_EVENT  (instead of check whether the last event is equal to -I2C_EVENT)
    • Add -detailed description of I2C events and how to manage them using the -functions provided by this driver. For more information, refer to -stm32f10x_i2c.h and stm32f10x_i2c.c files.
  • stm32f10x_rcc.h/.c: updated to support TIM9..TIM14 APB clock and reset configuration
  • stm32f10x_tim.h/.c: updated to support new Timers TIM9..TIM14.
  • stm32f10x_sdio.h: 
    • SDIO_SetSDIOReadWaitMode() function: correct values of SDIO_ReadWaitMode parameter
      change
        -#define -SDIO_ReadWaitMode_CLK               -  ((uint32_t)0x00000000)
        #define -SDIO_ReadWaitMode_DATA2             -((uint32_t)0x00000001)
      by
        #define -SDIO_ReadWaitMode_CLK               -  ((uint32_t)0x00000001)
        #define -SDIO_ReadWaitMode_DATA2             -((uint32_t)0x00000000)
-

3.2.0 -- 03/01/2010

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    -
  1. General
    2. -
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    - -
  • Add support -for STM32 Low-density Value line (STM32F100x4/6) and -Medium-density Value line (STM32F100x8/B) devices.
    • -
  • Almost -peripherals drivers were updated to support Value -line devices features
    • -
  • Drivers limitations fix and enhancements.
    • - -
-
    -
  1. STM32F10x_StdPeriph_Driver
    2. -
-
    -
  • Add new -firmware driver for CEC peripheral: stm32f10x_cec.h and stm32f10x_cec.c
    • -
  • Timers drivers stm32f10x_tim.h/.c: add support for new General Purpose Timers: TIM15, TIM16 and TIM17.
    • -
  • RCC driver: add support for new Value peripherals: HDMI-CEC, TIM15, TIM16 and TIM17.
    • -
  • GPIO driver: add new remap parameters for TIM1, TIM15, TIM16, TIM17 and HDMI-CEC: GPIO_Remap_TIM1_DMA, GPIO_Remap_TIM15, GPIO_Remap_TIM16, GPIO_Remap_TIM17, GPIO_Remap_CEC.
    • -
  • USART -driver: add support for Oversampling by 8 mode and onebit method. 2 -functions has been added: USART_OverSampling8Cmd() and -USART_OneBitMethodCmd().
    -
    • -
  • DAC -driver: add new functions handling the DAC under run feature: -DAC_ITConfig(), DAC_GetFlagStatus(), DAC_ClearFlag(), DAC_GetITStatus() -and DAC_ClearITPendingBit().
    • -
  • DBGMCU driver: add new parameters for TIM15, TIM16 and TIM17: DBGMCU_TIM15_STOP, DBGMCU_TIM16_STOP, DBGMCU_TIM17_STOP.
    -
    • -
  • FLASH -driver: the FLASH_EraseOptionBytes() function updated. This is now just -erasing the option bytes without modifying the RDP status either -enabled or disabled.
    • -
  • PWR -driver: the PWR_EnterSTOPMode() function updated. When woken up from -STOP mode, this function resets again the SLEEPDEEP bit in the -Cortex-M3 System Control register to allow Sleep mode entering.
    • - - -
-

License

-

The -enclosed firmware and all the related documentation are not covered by -a License Agreement, if you need such License you can contact your -local STMicroelectronics office.

-

THE -PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO -SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR -ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY -CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY -CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH -THEIR PRODUCTS.

-

 

-
-
-

For -complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers -visit www.st.com/STM32

-
-

-
-
-

 

-
- \ No newline at end of file diff --git a/example/libs_stm/src/stm32f10x/misc.c b/example/libs_stm/src/stm32f10x/misc.c deleted file mode 100644 index b8349fab9..000000000 --- a/example/libs_stm/src/stm32f10x/misc.c +++ /dev/null @@ -1,223 +0,0 @@ -/** - ****************************************************************************** - * @file misc.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "misc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/** @defgroup MISC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_Defines - * @{ - */ - -#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) -/** - * @} - */ - -/** @defgroup MISC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup MISC_Private_Functions - * @{ - */ - -/** - * @brief Configures the priority grouping: pre-emption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ - SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; -} - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); - assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; - tmppre = (0x4 - tmppriority); - tmpsub = tmpsub >> tmppriority; - - tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; - tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; - tmppriority = tmppriority << 0x04; - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values: - * @arg NVIC_VectTab_RAM - * @arg NVIC_VectTab_FLASH - * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) -{ - /* Check the parameters */ - assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); - assert_param(IS_NVIC_OFFSET(Offset)); - - SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND - * @arg NVIC_LP_SLEEPDEEP - * @arg NVIC_LP_SLEEPONEXIT - * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Configures the SysTick clock source. - * @param SysTick_CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_adc.c b/example/libs_stm/src/stm32f10x/stm32f10x_adc.c deleted file mode 100644 index a027f3304..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_adc.c +++ /dev/null @@ -1,1306 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_adc.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the ADC firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_adc.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/** @defgroup ADC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Defines - * @{ - */ - -/* ADC DISCNUM mask */ -#define CR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) - -/* ADC DISCEN mask */ -#define CR1_DISCEN_Set ((uint32_t)0x00000800) -#define CR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) - -/* ADC JAUTO mask */ -#define CR1_JAUTO_Set ((uint32_t)0x00000400) -#define CR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) - -/* ADC JDISCEN mask */ -#define CR1_JDISCEN_Set ((uint32_t)0x00001000) -#define CR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) - -/* ADC AWDCH mask */ -#define CR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) - -/* CR1 register Mask */ -#define CR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) - -/* ADC ADON mask */ -#define CR2_ADON_Set ((uint32_t)0x00000001) -#define CR2_ADON_Reset ((uint32_t)0xFFFFFFFE) - -/* ADC DMA mask */ -#define CR2_DMA_Set ((uint32_t)0x00000100) -#define CR2_DMA_Reset ((uint32_t)0xFFFFFEFF) - -/* ADC RSTCAL mask */ -#define CR2_RSTCAL_Set ((uint32_t)0x00000008) - -/* ADC CAL mask */ -#define CR2_CAL_Set ((uint32_t)0x00000004) - -/* ADC SWSTART mask */ -#define CR2_SWSTART_Set ((uint32_t)0x00400000) - -/* ADC EXTTRIG mask */ -#define CR2_EXTTRIG_Set ((uint32_t)0x00100000) -#define CR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) - -/* ADC Software start mask */ -#define CR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) -#define CR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) - -/* ADC JEXTSEL mask */ -#define CR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) - -/* ADC JEXTTRIG mask */ -#define CR2_JEXTTRIG_Set ((uint32_t)0x00008000) -#define CR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) - -/* ADC JSWSTART mask */ -#define CR2_JSWSTART_Set ((uint32_t)0x00200000) - -/* ADC injected software start mask */ -#define CR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) -#define CR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) - -/* ADC TSPD mask */ -#define CR2_TSVREFE_Set ((uint32_t)0x00800000) -#define CR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) - -/* CR2 register Mask */ -#define CR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) - -/* ADC SQx mask */ -#define SQR3_SQ_Set ((uint32_t)0x0000001F) -#define SQR2_SQ_Set ((uint32_t)0x0000001F) -#define SQR1_SQ_Set ((uint32_t)0x0000001F) - -/* SQR1 register Mask */ -#define SQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define JSQR_JSQ_Set ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define JSQR_JL_Set ((uint32_t)0x00300000) -#define JSQR_JL_Reset ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SMPR1_SMP_Set ((uint32_t)0x00000007) -#define SMPR2_SMP_Set ((uint32_t)0x00000007) - -/* ADC JDRx registers offset */ -#define JDR_Offset ((uint8_t)0x28) - -/* ADC1 DR register base address */ -#define DR_ADDRESS ((uint32_t)0x4001244C) - -/** - * @} - */ - -/** @defgroup ADC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the ADCx peripheral registers to their default reset values. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_DeInit(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - if (ADCx == ADC1) - { - /* Enable ADC1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); - /* Release ADC1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); - } - else if (ADCx == ADC2) - { - /* Enable ADC2 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); - /* Release ADC2 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); - } - else - { - if (ADCx == ADC3) - { - /* Enable ADC3 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, ENABLE); - /* Release ADC3 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC3, DISABLE); - } - } -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel)); - - /*---------------------------- ADCx CR1 Configuration -----------------*/ - /* Get the ADCx CR1 value */ - tmpreg1 = ADCx->CR1; - /* Clear DUALMOD and SCAN bits */ - tmpreg1 &= CR1_CLEAR_Mask; - /* Configure ADCx: Dual mode and scan conversion mode */ - /* Set DUALMOD bits according to ADC_Mode value */ - /* Set SCAN bit according to ADC_ScanConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); - /* Write to ADCx CR1 */ - ADCx->CR1 = tmpreg1; - - /*---------------------------- ADCx CR2 Configuration -----------------*/ - /* Get the ADCx CR2 value */ - tmpreg1 = ADCx->CR2; - /* Clear CONT, ALIGN and EXTSEL bits */ - tmpreg1 &= CR2_CLEAR_Mask; - /* Configure ADCx: external trigger event and continuous conversion mode */ - /* Set ALIGN bit according to ADC_DataAlign value */ - /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ - /* Set CONT bit according to ADC_ContinuousConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - /* Write to ADCx CR2 */ - ADCx->CR2 = tmpreg1; - - /*---------------------------- ADCx SQR1 Configuration -----------------*/ - /* Get the ADCx SQR1 value */ - tmpreg1 = ADCx->SQR1; - /* Clear L bits */ - tmpreg1 &= SQR1_CLEAR_Mask; - /* Configure ADCx: regular channel sequence length */ - /* Set L bits according to ADC_NbrOfChannel value */ - tmpreg2 |= (uint8_t) (ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); - tmpreg1 |= (uint32_t)tmpreg2 << 20; - /* Write to ADCx SQR1 */ - ADCx->SQR1 = tmpreg1; -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @param ADC_InitStruct : pointer to an ADC_InitTypeDef structure which will be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Reset ADC init structure parameters values */ - /* Initialize the ADC_Mode member */ - ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; - /* initialize the ADC_ScanConvMode member */ - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - /* Initialize the ADC_ContinuousConvMode member */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - /* Initialize the ADC_ExternalTrigConv member */ - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - /* Initialize the ADC_DataAlign member */ - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - /* Initialize the ADC_NbrOfChannel member */ - ADC_InitStruct->ADC_NbrOfChannel = 1; -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ADON bit to wake up the ADC from power down mode */ - ADCx->CR2 |= CR2_ADON_Set; - } - else - { - /* Disable the selected ADC peripheral */ - ADCx->CR2 &= CR2_ADON_Reset; - } -} - -/** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1 or 3 to select the ADC peripheral. - * Note: ADC2 hasn't a DMA capability. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_DMA_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CR2 |= CR2_DMA_Set; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CR2 &= CR2_DMA_Reset; - } -} - -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)ADC_IT; - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->CR1 |= itmask; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->CR1 &= (~(uint32_t)itmask); - } -} - -/** - * @brief Resets the selected ADC calibration registers. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_ResetCalibration(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Resets the selected ADC calibartion registers */ - ADCx->CR2 |= CR2_RSTCAL_Set; -} - -/** - * @brief Gets the selected ADC reset calibration registers status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC reset calibration registers (SET or RESET). - */ -FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of RSTCAL bit */ - if ((ADCx->CR2 & CR2_RSTCAL_Set) != (uint32_t)RESET) - { - /* RSTCAL bit is set */ - bitstatus = SET; - } - else - { - /* RSTCAL bit is reset */ - bitstatus = RESET; - } - /* Return the RSTCAL bit status */ - return bitstatus; -} - -/** - * @brief Starts the selected ADC calibration process. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_StartCalibration(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Enable the selected ADC calibration process */ - ADCx->CR2 |= CR2_CAL_Set; -} - -/** - * @brief Gets the selected ADC calibration status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC calibration (SET or RESET). - */ -FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of CAL bit */ - if ((ADCx->CR2 & CR2_CAL_Set) != (uint32_t)RESET) - { - /* CAL bit is set: calibration on going */ - bitstatus = SET; - } - else - { - /* CAL bit is reset: end of calibration */ - bitstatus = RESET; - } - /* Return the CAL bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the selected ADC software start conversion . - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC software start conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion on external event and start the selected - ADC conversion */ - ADCx->CR2 |= CR2_EXTTRIG_SWSTART_Set; - } - else - { - /* Disable the selected ADC conversion on external event and stop the selected - ADC conversion */ - ADCx->CR2 &= CR2_EXTTRIG_SWSTART_Reset; - } -} - -/** - * @brief Gets the selected ADC Software start conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of SWSTART bit */ - if ((ADCx->CR2 & CR2_SWSTART_Set) != (uint32_t)RESET) - { - /* SWSTART bit is set */ - bitstatus = SET; - } - else - { - /* SWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the SWSTART bit status */ - return bitstatus; -} - -/** - * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Number: specifies the discontinuous mode regular channel - * count value. This number must be between 1 and 8. - * @retval None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); - /* Get the old register value */ - tmpreg1 = ADCx->CR1; - /* Clear the old discontinuous mode channel count */ - tmpreg1 &= CR1_DISCNUM_Reset; - /* Set the discontinuous mode channel count */ - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - /* Store the new register value */ - ADCx->CR1 = tmpreg1; -} - -/** - * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode - * on regular group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC regular discontinuous mode */ - ADCx->CR1 |= CR1_DISCEN_Set; - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - ADCx->CR1 &= CR1_DISCEN_Reset; - } -} - -/** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @param Rank: The rank in the regular group sequencer. This parameter must be between 1 to 16. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles - * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles - * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles - * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles - * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles - * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles - * @retval None - */ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_REGULAR_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_Set << (3 * (ADC_Channel - 10)); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* For Rank 1 to 6 */ - if (Rank < 7) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR3; - /* Calculate the mask to clear */ - tmpreg2 = SQR3_SQ_Set << (5 * (Rank - 1)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR3 = tmpreg1; - } - /* For Rank 7 to 12 */ - else if (Rank < 13) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR2; - /* Calculate the mask to clear */ - tmpreg2 = SQR2_SQ_Set << (5 * (Rank - 7)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR2 = tmpreg1; - } - /* For Rank 13 to 16 */ - else - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR1; - /* Calculate the mask to clear */ - tmpreg2 = SQR1_SQ_Set << (5 * (Rank - 13)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR1 = tmpreg1; - } -} - -/** - * @brief Enables or disables the ADCx conversion through external trigger. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC external trigger start of conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion on external event */ - ADCx->CR2 |= CR2_EXTTRIG_Set; - } - else - { - /* Disable the selected ADC conversion on external event */ - ADCx->CR2 &= CR2_EXTTRIG_Reset; - } -} - -/** - * @brief Returns the last ADCx conversion result data for regular channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. - * @retval The Data conversion value. - */ -uint32_t ADC_GetDualModeConversionValue(void) -{ - /* Return the dual mode conversion value */ - return (*(__IO uint32_t *) DR_ADDRESS); -} - -/** - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC auto injected conversion - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - ADCx->CR1 |= CR1_JAUTO_Set; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - ADCx->CR1 &= CR1_JAUTO_Reset; - } -} - -/** - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode - * on injected group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - ADCx->CR1 |= CR1_JDISCEN_Set; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - ADCx->CR1 &= CR1_JDISCEN_Reset; - } -} - -/** - * @brief Configures the ADCx external trigger for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected (for ADC1, ADC2 and ADC3) - * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected (for ADC1, ADC2 and ADC3) - * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4: External interrupt line 15 or Timer8 - * capture compare4 event selected (for ADC1 and ADC2) - * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected (for ADC3 only) - * @arg ADC_ExternalTrigInjecConv_None: Injected conversion started by software and not - * by external trigger (for ADC1, ADC2 and ADC3) - * @retval None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); - /* Get the old register value */ - tmpreg = ADCx->CR2; - /* Clear the old external event selection for injected group */ - tmpreg &= CR2_JEXTSEL_Reset; - /* Set the external event selection for injected group */ - tmpreg |= ADC_ExternalTrigInjecConv; - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Enables or disables the ADCx injected channels conversion through - * external trigger - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC external trigger start of - * injected conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC external event selection for injected group */ - ADCx->CR2 |= CR2_JEXTTRIG_Set; - } - else - { - /* Disable the selected ADC external event selection for injected group */ - ADCx->CR2 &= CR2_JEXTTRIG_Reset; - } -} - -/** - * @brief Enables or disables the selected ADC start of the injected - * channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC software start injected conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC conversion for injected group on external event and start the selected - ADC injected conversion */ - ADCx->CR2 |= CR2_JEXTTRIG_JSWSTART_Set; - } - else - { - /* Disable the selected ADC conversion on external event for injected group and stop the selected - ADC injected conversion */ - ADCx->CR2 &= CR2_JEXTTRIG_JSWSTART_Reset; - } -} - -/** - * @brief Gets the selected ADC Software start injected conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start injected conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Check the status of JSWSTART bit */ - if ((ADCx->CR2 & CR2_JSWSTART_Set) != (uint32_t)RESET) - { - /* JSWSTART bit is set */ - bitstatus = SET; - } - else - { - /* JSWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the JSWSTART bit status */ - return bitstatus; -} - -/** - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @param Rank: The rank in the injected group sequencer. This parameter must be between 1 and 4. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_1Cycles5: Sample time equal to 1.5 cycles - * @arg ADC_SampleTime_7Cycles5: Sample time equal to 7.5 cycles - * @arg ADC_SampleTime_13Cycles5: Sample time equal to 13.5 cycles - * @arg ADC_SampleTime_28Cycles5: Sample time equal to 28.5 cycles - * @arg ADC_SampleTime_41Cycles5: Sample time equal to 41.5 cycles - * @arg ADC_SampleTime_55Cycles5: Sample time equal to 55.5 cycles - * @arg ADC_SampleTime_71Cycles5: Sample time equal to 71.5 cycles - * @arg ADC_SampleTime_239Cycles5: Sample time equal to 239.5 cycles - * @retval None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_INJECTED_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_17 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10)); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel); - /* Clear the old channel sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new channel sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* Rank configuration */ - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Get JL value: Number = JL+1 */ - tmpreg3 = (tmpreg1 & JSQR_JL_Set)>> 20; - /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = JSQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Clear the old JSQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Set the JSQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Configures the sequencer length for injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Length: The sequencer length. - * This parameter must be a number between 1 to 4. - * @retval None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_LENGTH(Length)); - - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Clear the old injected sequnence lenght JL bits */ - tmpreg1 &= JSQR_JL_Reset; - /* Set the injected sequnence lenght JL bits */ - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Set the injected channels conversion value offset - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the ADC injected channel to set its offset. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @param Offset: the offset value for the selected ADC injected channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - assert_param(IS_ADC_OFFSET(Offset)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - /* Set the selected injected channel data offset */ - *(__IO uint32_t *) tmp = (uint32_t)Offset; -} - -/** - * @brief Returns the ADC injected channel conversion result - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the converted ADC injected channel. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @retval The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + JDR_Offset; - - /* Returns the selected injected channel conversion data value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -/** - * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel - * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel - * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel - * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel - * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel - * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels - * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); - /* Get the old register value */ - tmpreg = ADCx->CR1; - /* Clear AWDEN, AWDENJ and AWDSGL bits */ - tmpreg &= CR1_AWDMode_Reset; - /* Set the analog watchdog enable mode */ - tmpreg |= ADC_AnalogWatchdog; - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - /* Set the ADCx high threshold */ - ADCx->HTR = HighThreshold; - /* Set the ADCx low threshold */ - ADCx->LTR = LowThreshold; -} - -/** - * @brief Configures the analog watchdog guarded single channel - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - /* Get the old register value */ - tmpreg = ADCx->CR1; - /* Clear the Analog watchdog channel select bits */ - tmpreg &= CR1_AWDCH_Reset; - /* Set the Analog watchdog channel */ - tmpreg |= ADC_Channel; - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Enables or disables the temperature sensor and Vrefint channel. - * @param NewState: new state of the temperature sensor. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the temperature sensor and Vrefint channel*/ - ADC1->CR2 |= CR2_TSVREFE_Set; - } - else - { - /* Disable the temperature sensor and Vrefint channel*/ - ADC1->CR2 &= CR2_TSVREFE_Reset; - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - /* Check the status of the specified ADC flag */ - if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - /* Clear the selected ADC flags */ - ADCx->SR = ~(uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = ADC_IT >> 8; - /* Get the ADC_IT enable bit status */ - enablestatus = (ADCx->CR1 & (uint8_t)ADC_IT) ; - /* Check the status of the specified ADC interrupt */ - if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) - { - /* ADC_IT is set */ - bitstatus = SET; - } - else - { - /* ADC_IT is reset */ - bitstatus = RESET; - } - /* Return the ADC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the ADCxs interrupt pending bits. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)(ADC_IT >> 8); - /* Clear the selected ADC interrupt pending bits */ - ADCx->SR = ~(uint32_t)itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_bkp.c b/example/libs_stm/src/stm32f10x/stm32f10x_bkp.c deleted file mode 100644 index de065648f..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_bkp.c +++ /dev/null @@ -1,311 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_bkp.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the BKP firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_bkp.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup BKP - * @brief BKP driver modules - * @{ - */ - -/** @defgroup BKP_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_Defines - * @{ - */ - -/* ------------ BKP registers bit address in the alias region --------------- */ -#define BKP_OFFSET (BKP_BASE - PERIPH_BASE) - -/* --- CR Register ----*/ - -/* Alias word address of TPAL bit */ -#define CR_OFFSET (BKP_OFFSET + 0x30) -#define TPAL_BitNumber 0x01 -#define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) - -/* Alias word address of TPE bit */ -#define TPE_BitNumber 0x00 -#define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of TPIE bit */ -#define CSR_OFFSET (BKP_OFFSET + 0x34) -#define TPIE_BitNumber 0x02 -#define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) - -/* Alias word address of TIF bit */ -#define TIF_BitNumber 0x09 -#define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) - -/* Alias word address of TEF bit */ -#define TEF_BitNumber 0x08 -#define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) - -/* ---------------------- BKP registers bit mask ------------------------ */ - -/* RTCCR register bit mask */ -#define RTCCR_CAL_Mask ((uint16_t)0xFF80) -#define RTCCR_Mask ((uint16_t)0xFC7F) - -/* CSR register bit mask */ -#define CSR_CTE_Set ((uint16_t)0x0001) -#define CSR_CTI_Set ((uint16_t)0x0002) - -/** - * @} - */ - - -/** @defgroup BKP_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup BKP_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the BKP peripheral registers to their default reset values. - * @param None - * @retval None - */ -void BKP_DeInit(void) -{ - RCC_BackupResetCmd(ENABLE); - RCC_BackupResetCmd(DISABLE); -} - -/** - * @brief Configures the Tamper Pin active level. - * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. - * This parameter can be one of the following values: - * @arg BKP_TamperPinLevel_High: Tamper pin active on high level - * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level - * @retval None - */ -void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) -{ - /* Check the parameters */ - assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); - *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; -} - -/** - * @brief Enables or disables the Tamper Pin activation. - * @param NewState: new state of the Tamper Pin activation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void BKP_TamperPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Tamper Pin Interrupt. - * @param NewState: new state of the Tamper Pin Interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void BKP_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; -} - -/** - * @brief Select the RTC output source to output on the Tamper pin. - * @param BKP_RTCOutputSource: specifies the RTC output source. - * This parameter can be one of the following values: - * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. - * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency - * divided by 64 on the Tamper pin. - * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on - * the Tamper pin. - * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on - * the Tamper pin. - * @retval None - */ -void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) -{ - uint16_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); - tmpreg = BKP->RTCCR; - /* Clear CCO, ASOE and ASOS bits */ - tmpreg &= RTCCR_Mask; - - /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ - tmpreg |= BKP_RTCOutputSource; - /* Store the new value */ - BKP->RTCCR = tmpreg; -} - -/** - * @brief Sets RTC Clock Calibration value. - * @param CalibrationValue: specifies the RTC Clock Calibration value. - * This parameter must be a number between 0 and 0x7F. - * @retval None - */ -void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) -{ - uint16_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); - tmpreg = BKP->RTCCR; - /* Clear CAL[6:0] bits */ - tmpreg &= RTCCR_CAL_Mask; - /* Set CAL[6:0] bits according to CalibrationValue value */ - tmpreg |= CalibrationValue; - /* Store the new value */ - BKP->RTCCR = tmpreg; -} - -/** - * @brief Writes user data to the specified Data Backup Register. - * @param BKP_DR: specifies the Data Backup Register. - * This parameter can be BKP_DRx where x:[1, 42] - * @param Data: data to write - * @retval None - */ -void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_BKP_DR(BKP_DR)); - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Reads data from the specified Data Backup Register. - * @param BKP_DR: specifies the Data Backup Register. - * This parameter can be BKP_DRx where x:[1, 42] - * @retval The content of the specified Data Backup Register - */ -uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_BKP_DR(BKP_DR)); - - tmp = (uint32_t)BKP_BASE; - tmp += BKP_DR; - - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Checks whether the Tamper Pin Event flag is set or not. - * @param None - * @retval The new state of the Tamper Pin Event flag (SET or RESET). - */ -FlagStatus BKP_GetFlagStatus(void) -{ - return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); -} - -/** - * @brief Clears Tamper Pin Event pending flag. - * @param None - * @retval None - */ -void BKP_ClearFlag(void) -{ - /* Set CTE bit to clear Tamper Pin Event flag */ - BKP->CSR |= CSR_CTE_Set; -} - -/** - * @brief Checks whether the Tamper Pin Interrupt has occurred or not. - * @param None - * @retval The new state of the Tamper Pin Interrupt (SET or RESET). - */ -ITStatus BKP_GetITStatus(void) -{ - return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); -} - -/** - * @brief Clears Tamper Pin Interrupt pending bit. - * @param None - * @retval None - */ -void BKP_ClearITPendingBit(void) -{ - /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ - BKP->CSR |= CSR_CTI_Set; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_can.c b/example/libs_stm/src/stm32f10x/stm32f10x_can.c deleted file mode 100644 index 537f333ba..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_can.c +++ /dev/null @@ -1,990 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_can.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the CAN firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_can.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CAN - * @brief CAN driver modules - * @{ - */ - -/** @defgroup CAN_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_Defines - * @{ - */ - -/* CAN Master Control Register bits */ -#define MCR_INRQ ((uint32_t)0x00000001) /* Initialization request */ -#define MCR_SLEEP ((uint32_t)0x00000002) /* Sleep mode request */ -#define MCR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO priority */ -#define MCR_RFLM ((uint32_t)0x00000008) /* Receive FIFO locked mode */ -#define MCR_NART ((uint32_t)0x00000010) /* No automatic retransmission */ -#define MCR_AWUM ((uint32_t)0x00000020) /* Automatic wake up mode */ -#define MCR_ABOM ((uint32_t)0x00000040) /* Automatic bus-off management */ -#define MCR_TTCM ((uint32_t)0x00000080) /* time triggered communication */ -#define MCR_RESET ((uint32_t)0x00008000) /* time triggered communication */ -#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ - -/* CAN Master Status Register bits */ -#define MSR_INAK ((uint32_t)0x00000001) /* Initialization acknowledge */ -#define MSR_WKUI ((uint32_t)0x00000008) /* Wake-up interrupt */ -#define MSR_SLAKI ((uint32_t)0x00000010) /* Sleep acknowledge interrupt */ - -/* CAN Transmit Status Register bits */ -#define TSR_RQCP0 ((uint32_t)0x00000001) /* Request completed mailbox0 */ -#define TSR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of mailbox0 */ -#define TSR_ABRQ0 ((uint32_t)0x00000080) /* Abort request for mailbox0 */ -#define TSR_RQCP1 ((uint32_t)0x00000100) /* Request completed mailbox1 */ -#define TSR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of mailbox1 */ -#define TSR_ABRQ1 ((uint32_t)0x00008000) /* Abort request for mailbox1 */ -#define TSR_RQCP2 ((uint32_t)0x00010000) /* Request completed mailbox2 */ -#define TSR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of mailbox2 */ -#define TSR_ABRQ2 ((uint32_t)0x00800000) /* Abort request for mailbox2 */ -#define TSR_TME0 ((uint32_t)0x04000000) /* Transmit mailbox 0 empty */ -#define TSR_TME1 ((uint32_t)0x08000000) /* Transmit mailbox 1 empty */ -#define TSR_TME2 ((uint32_t)0x10000000) /* Transmit mailbox 2 empty */ - -/* CAN Receive FIFO 0 Register bits */ -#define RF0R_FULL0 ((uint32_t)0x00000008) /* FIFO 0 full */ -#define RF0R_FOVR0 ((uint32_t)0x00000010) /* FIFO 0 overrun */ -#define RF0R_RFOM0 ((uint32_t)0x00000020) /* Release FIFO 0 output mailbox */ - -/* CAN Receive FIFO 1 Register bits */ -#define RF1R_FULL1 ((uint32_t)0x00000008) /* FIFO 1 full */ -#define RF1R_FOVR1 ((uint32_t)0x00000010) /* FIFO 1 overrun */ -#define RF1R_RFOM1 ((uint32_t)0x00000020) /* Release FIFO 1 output mailbox */ - -/* CAN Error Status Register bits */ -#define ESR_EWGF ((uint32_t)0x00000001) /* Error warning flag */ -#define ESR_EPVF ((uint32_t)0x00000002) /* Error passive flag */ -#define ESR_BOFF ((uint32_t)0x00000004) /* Bus-off flag */ - -/* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ - -/* CAN Filter Master Register bits */ -#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ - -/* Time out for INAK bit */ -#define INAK_TimeOut ((uint32_t)0x0000FFFF) - -/* Time out for SLAK bit */ -#define SLAK_TimeOut ((uint32_t)0x0000FFFF) - -/** - * @} - */ - -/** @defgroup CAN_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup CAN_Private_FunctionPrototypes - * @{ - */ - -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); - -/** - * @} - */ - -/** @defgroup CAN_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the CAN peripheral registers to their default reset values. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval None. - */ -void CAN_DeInit(CAN_TypeDef* CANx) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - if (CANx == CAN1) - { - /* Enable CAN1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); - /* Release CAN1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); - } - else - { - /* Enable CAN2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); - /* Release CAN2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); - } -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that - * contains the configuration information for the CAN peripheral. - * @retval Constant indicates initialization succeed which will be - * CANINITFAILED or CANINITOK. - */ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) -{ - uint8_t InitStatus = CANINITFAILED; - uint32_t wait_ack = 0x00000000; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); - assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); - assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); - assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); - assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); - assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); - - /* exit from sleep mode */ - CANx->MCR &= ~MCR_SLEEP; - - /* Request initialisation */ - CANx->MCR |= MCR_INRQ ; - - /* Wait the acknowledge */ - while (((CANx->MSR & MSR_INAK) != MSR_INAK) && (wait_ack != INAK_TimeOut)) - { - wait_ack++; - } - - /* ...and check acknowledged */ - if ((CANx->MSR & MSR_INAK) != MSR_INAK) - { - InitStatus = CANINITFAILED; - } - else - { - /* Set the time triggered communication mode */ - if (CAN_InitStruct->CAN_TTCM == ENABLE) - { - CANx->MCR |= MCR_TTCM; - } - else - { - CANx->MCR &= ~MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (CAN_InitStruct->CAN_ABOM == ENABLE) - { - CANx->MCR |= MCR_ABOM; - } - else - { - CANx->MCR &= ~MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (CAN_InitStruct->CAN_AWUM == ENABLE) - { - CANx->MCR |= MCR_AWUM; - } - else - { - CANx->MCR &= ~MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (CAN_InitStruct->CAN_NART == ENABLE) - { - CANx->MCR |= MCR_NART; - } - else - { - CANx->MCR &= ~MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (CAN_InitStruct->CAN_RFLM == ENABLE) - { - CANx->MCR |= MCR_RFLM; - } - else - { - CANx->MCR &= ~MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (CAN_InitStruct->CAN_TXFP == ENABLE) - { - CANx->MCR |= MCR_TXFP; - } - else - { - CANx->MCR &= ~MCR_TXFP; - } - - /* Set the bit timing register */ - CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | - ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); - - /* Request leave initialisation */ - CANx->MCR &= ~MCR_INRQ; - - /* Wait the acknowledge */ - wait_ack = 0x00; - - while (((CANx->MSR & MSR_INAK) == MSR_INAK) && (wait_ack != INAK_TimeOut)) - { - wait_ack++; - } - - /* ...and check acknowledged */ - if ((CANx->MSR & MSR_INAK) == MSR_INAK) - { - InitStatus = CANINITFAILED; - } - else - { - InitStatus = CANINITOK ; - } - } - - /* At this step, return the status of initialization */ - return InitStatus; -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_FilterInitStruct. - * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef - * structure that contains the configuration information. - * @retval None. - */ -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); - - filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber; - - /* Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; - - /* Filter Scale */ - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - /* 32-bit scale for the filter */ - CAN1->FS1R |= filter_number_bit_pos; - /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - - /* Filter Mode */ - if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter FIFO assignment */ - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0) - { - /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1) - { - /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter activation */ - if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CAN1->FA1R |= filter_number_bit_pos; - } - - /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Fills each CAN_InitStruct member with its default value. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which - * will be initialized. - * @retval None. - */ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ - /* Reset CAN init structure parameters values */ - /* Initialize the time triggered communication mode */ - CAN_InitStruct->CAN_TTCM = DISABLE; - /* Initialize the automatic bus-off management */ - CAN_InitStruct->CAN_ABOM = DISABLE; - /* Initialize the automatic wake-up mode */ - CAN_InitStruct->CAN_AWUM = DISABLE; - /* Initialize the no automatic retransmission */ - CAN_InitStruct->CAN_NART = DISABLE; - /* Initialize the receive FIFO locked mode */ - CAN_InitStruct->CAN_RFLM = DISABLE; - /* Initialize the transmit FIFO priority */ - CAN_InitStruct->CAN_TXFP = DISABLE; - /* Initialize the CAN_Mode member */ - CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; - /* Initialize the CAN_SJW member */ - CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; - /* Initialize the CAN_BS1 member */ - CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; - /* Initialize the CAN_BS2 member */ - CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; - /* Initialize the CAN_Prescaler member */ - CAN_InitStruct->CAN_Prescaler = 1; -} - -/** - * @brief Select the start bank filter for slave CAN. - * @note This function applies only to STM32 Connectivity line devices. - * @param CAN_BankNumber: Select the start slave bank filter from 1..27. - * @retval None. - */ -void CAN_SlaveStartBank(uint8_t CAN_BankNumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); - /* enter Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - /* Select the start slave bank */ - CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; - CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; - /* Leave Initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Enables or disables the specified CAN interrupts. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. - * This parameter can be: CAN_IT_TME, CAN_IT_FMP0, CAN_IT_FF0, - * CAN_IT_FOV0, CAN_IT_FMP1, CAN_IT_FF1, - * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, - * CAN_IT_LEC, CAN_IT_ERR, CAN_IT_WKU or - * CAN_IT_SLK. - * @param NewState: new state of the CAN interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_ITConfig(CAN_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CAN interrupt */ - CANx->IER |= CAN_IT; - } - else - { - /* Disable the selected CAN interrupt */ - CANx->IER &= ~CAN_IT; - } -} - -/** - * @brief Initiates the transmission of a message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param TxMessage: pointer to a structure which contains CAN Id, CAN - * DLC and CAN datas. - * @retval The number of the mailbox that is used for transmission - * or CAN_NO_MB if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) -{ - uint8_t transmit_mailbox = 0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); - assert_param(IS_CAN_RTR(TxMessage->RTR)); - assert_param(IS_CAN_DLC(TxMessage->DLC)); - - /* Select one empty transmit mailbox */ - if ((CANx->TSR&TSR_TME0) == TSR_TME0) - { - transmit_mailbox = 0; - } - else if ((CANx->TSR&TSR_TME1) == TSR_TME1) - { - transmit_mailbox = 1; - } - else if ((CANx->TSR&TSR_TME2) == TSR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_NO_MB; - } - - if (transmit_mailbox != CAN_NO_MB) - { - /* Set up the Id */ - CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(TxMessage->StdId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | TxMessage->RTR); - } - else - { - assert_param(IS_CAN_EXTID(TxMessage->ExtId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId<<3) | TxMessage->IDE | - TxMessage->RTR); - } - - - /* Set up the DLC */ - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; - - /* Set up the data field */ - CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - /* Request transmission */ - CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; - } - return transmit_mailbox; -} - -/** - * @brief Checks the transmission of a message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param TransmitMailbox: the number of the mailbox that is used for transmission. - * @retval CANTXOK if the CAN driver transmits the message, CANTXFAILED in an other case. - */ -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) -{ - /* RQCP, TXOK and TME bits */ - uint8_t state = 0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); - switch (TransmitMailbox) - { - case (0): state |= (uint8_t)((CANx->TSR & TSR_RQCP0) << 2); - state |= (uint8_t)((CANx->TSR & TSR_TXOK0) >> 0); - state |= (uint8_t)((CANx->TSR & TSR_TME0) >> 26); - break; - case (1): state |= (uint8_t)((CANx->TSR & TSR_RQCP1) >> 6); - state |= (uint8_t)((CANx->TSR & TSR_TXOK1) >> 8); - state |= (uint8_t)((CANx->TSR & TSR_TME1) >> 27); - break; - case (2): state |= (uint8_t)((CANx->TSR & TSR_RQCP2) >> 14); - state |= (uint8_t)((CANx->TSR & TSR_TXOK2) >> 16); - state |= (uint8_t)((CANx->TSR & TSR_TME2) >> 28); - break; - default: - state = CANTXFAILED; - break; - } - switch (state) - { - /* transmit pending */ - case (0x0): state = CANTXPENDING; - break; - /* transmit failed */ - case (0x5): state = CANTXFAILED; - break; - /* transmit succedeed */ - case (0x7): state = CANTXOK; - break; - default: - state = CANTXFAILED; - break; - } - return state; -} - -/** - * @brief Cancels a transmit request. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param Mailbox: Mailbox number. - * @retval None. - */ -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); - /* abort transmission */ - switch (Mailbox) - { - case (0): CANx->TSR |= TSR_ABRQ0; - break; - case (1): CANx->TSR |= TSR_ABRQ1; - break; - case (2): CANx->TSR |= TSR_ABRQ2; - break; - default: - break; - } -} - -/** - * @brief Releases a FIFO. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. - * @retval None. - */ -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R = RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R = RF1R_RFOM1; - } -} - -/** - * @brief Returns the number of pending messages. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval NbMessage which is the number of pending message. - */ -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - uint8_t message_pending=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - if (FIFONumber == CAN_FIFO0) - { - message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); - } - else if (FIFONumber == CAN_FIFO1) - { - message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); - } - else - { - message_pending = 0; - } - return message_pending; -} - -/** - * @brief Receives a message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @param RxMessage: pointer to a structure receive message which - * contains CAN Id, CAN DLC, CAN datas and FMI number. - * @retval None. - */ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Get the Id */ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; - if (RxMessage->IDE == CAN_ID_STD) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - CAN_FIFORelease(CANx, FIFONumber); -} - -/** - * @brief Enables or disables the DBG Freeze for CAN. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: new state of the CAN peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Debug Freeze */ - CANx->MCR |= MCR_DBF; - } - else - { - /* Disable Debug Freeze */ - CANx->MCR &= ~MCR_DBF; - } -} - -/** - * @brief Enters the low power mode. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CANSLEEPOK if sleep entered, CANSLEEPFAILED in an other case. - */ -uint8_t CAN_Sleep(CAN_TypeDef* CANx) -{ - uint8_t sleepstatus = CANSLEEPFAILED; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Request Sleep mode */ - CANx->MCR = (((CANx->MCR) & (uint32_t)(~MCR_INRQ)) | MCR_SLEEP); - - /* Sleep mode status */ - if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) - { - /* Sleep mode not entered */ - sleepstatus = CANSLEEPOK; - } - /* At this step, sleep mode status */ - return (uint8_t)sleepstatus; -} - -/** - * @brief Wakes the CAN up. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CANWAKEUPOK if sleep mode left, CANWAKEUPFAILED in an other case. - */ -uint8_t CAN_WakeUp(CAN_TypeDef* CANx) -{ - uint32_t wait_slak = SLAK_TimeOut ; - uint8_t wakeupstatus = CANWAKEUPFAILED; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Wake up request */ - CANx->MCR &= ~MCR_SLEEP; - - /* Sleep mode status */ - while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) - { - wait_slak--; - } - if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) - { - /* Sleep mode exited */ - wakeupstatus = CANWAKEUPOK; - } - /* At this step, sleep mode status */ - return (uint8_t)wakeupstatus; -} - -/** - * @brief Checks whether the specified CAN flag is set or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to check. - * This parameter can be: CAN_FLAG_EWG, CAN_FLAG_EPV or CAN_FLAG_BOF. - * @retval The new state of CAN_FLAG (SET or RESET). - */ -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FLAG(CAN_FLAG)); - /* Check the status of the specified CAN flag */ - if ((CANx->ESR & CAN_FLAG) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - /* Return the CAN_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CAN's pending flags. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to clear. - * @retval None. - */ -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FLAG(CAN_FLAG)); - /* Clear the selected CAN flags */ - CANx->ESR &= ~CAN_FLAG; -} - -/** - * @brief Checks whether the specified CAN interrupt has occurred or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt source to check. - * This parameter can be: CAN_IT_RQCP0, CAN_IT_RQCP1, CAN_IT_RQCP2, - * CAN_IT_FF0, CAN_IT_FOV0, CAN_IT_FF1, - * CAN_IT_FOV1, CAN_IT_EWG, CAN_IT_EPV, - * CAN_IT_BOF, CAN_IT_WKU or CAN_IT_SLK. - * @retval The new state of CAN_IT (SET or RESET). - */ -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - ITStatus pendingbitstatus = RESET; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_ITStatus(CAN_IT)); - switch (CAN_IT) - { - case CAN_IT_RQCP0: - pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP0); - break; - case CAN_IT_RQCP1: - pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP1); - break; - case CAN_IT_RQCP2: - pendingbitstatus = CheckITStatus(CANx->TSR, TSR_RQCP2); - break; - case CAN_IT_FF0: - pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FULL0); - break; - case CAN_IT_FOV0: - pendingbitstatus = CheckITStatus(CANx->RF0R, RF0R_FOVR0); - break; - case CAN_IT_FF1: - pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FULL1); - break; - case CAN_IT_FOV1: - pendingbitstatus = CheckITStatus(CANx->RF1R, RF1R_FOVR1); - break; - case CAN_IT_EWG: - pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EWGF); - break; - case CAN_IT_EPV: - pendingbitstatus = CheckITStatus(CANx->ESR, ESR_EPVF); - break; - case CAN_IT_BOF: - pendingbitstatus = CheckITStatus(CANx->ESR, ESR_BOFF); - break; - case CAN_IT_SLK: - pendingbitstatus = CheckITStatus(CANx->MSR, MSR_SLAKI); - break; - case CAN_IT_WKU: - pendingbitstatus = CheckITStatus(CANx->MSR, MSR_WKUI); - break; - default : - pendingbitstatus = RESET; - break; - } - /* Return the CAN_IT status */ - return pendingbitstatus; -} - -/** - * @brief Clears the CANs interrupt pending bits. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the interrupt pending bit to clear. - * @retval None. - */ -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_ITStatus(CAN_IT)); - switch (CAN_IT) - { - case CAN_IT_RQCP0: - CANx->TSR = TSR_RQCP0; /* rc_w1*/ - break; - case CAN_IT_RQCP1: - CANx->TSR = TSR_RQCP1; /* rc_w1*/ - break; - case CAN_IT_RQCP2: - CANx->TSR = TSR_RQCP2; /* rc_w1*/ - break; - case CAN_IT_FF0: - CANx->RF0R = RF0R_FULL0; /* rc_w1*/ - break; - case CAN_IT_FOV0: - CANx->RF0R = RF0R_FOVR0; /* rc_w1*/ - break; - case CAN_IT_FF1: - CANx->RF1R = RF1R_FULL1; /* rc_w1*/ - break; - case CAN_IT_FOV1: - CANx->RF1R = RF1R_FOVR1; /* rc_w1*/ - break; - case CAN_IT_EWG: - CANx->ESR &= ~ ESR_EWGF; /* rw */ - break; - case CAN_IT_EPV: - CANx->ESR &= ~ ESR_EPVF; /* rw */ - break; - case CAN_IT_BOF: - CANx->ESR &= ~ ESR_BOFF; /* rw */ - break; - case CAN_IT_WKU: - CANx->MSR = MSR_WKUI; /* rc_w1*/ - break; - case CAN_IT_SLK: - CANx->MSR = MSR_SLAKI; /* rc_w1*/ - break; - default : - break; - } -} - -/** - * @brief Checks whether the CAN interrupt has occurred or not. - * @param CAN_Reg: specifies the CAN interrupt register to check. - * @param It_Bit: specifies the interrupt source bit to check. - * @retval The new state of the CAN Interrupt (SET or RESET). - */ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) -{ - ITStatus pendingbitstatus = RESET; - - if ((CAN_Reg & It_Bit) != (uint32_t)RESET) - { - /* CAN_IT is set */ - pendingbitstatus = SET; - } - else - { - /* CAN_IT is reset */ - pendingbitstatus = RESET; - } - return pendingbitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_cec.c b/example/libs_stm/src/stm32f10x/stm32f10x_cec.c deleted file mode 100644 index 4ae244569..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_cec.c +++ /dev/null @@ -1,432 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_cec.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the CEC firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_cec.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CEC - * @brief CEC driver modules - * @{ - */ - -/** @defgroup CEC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Defines - * @{ - */ - -/* ------------ CEC registers bit address in the alias region ----------- */ -#define CEC_OFFSET (CEC_BASE - PERIPH_BASE) - -/* --- CFGR Register ---*/ - -/* Alias word address of PE bit */ -#define CFGR_OFFSET (CEC_OFFSET + 0x00) -#define PE_BitNumber 0x00 -#define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) - -/* Alias word address of IE bit */ -#define IE_BitNumber 0x01 -#define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of TSOM bit */ -#define CSR_OFFSET (CEC_OFFSET + 0x10) -#define TSOM_BitNumber 0x00 -#define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) - -/* Alias word address of TEOM bit */ -#define TEOM_BitNumber 0x01 -#define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) - -#define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Macros - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Variables - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - - -/** @defgroup CEC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the CEC peripheral registers to their default reset - * values. - * @param None - * @retval None - */ -void CEC_DeInit(void) -{ - /* Enable CEC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); - /* Release CEC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); -} - - -/** - * @brief Initializes the CEC peripheral according to the specified - * parameters in the CEC_InitStruct. - * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that - * contains the configuration information for the specified - * CEC peripheral. - * @retval None - */ -void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); - assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); - - /*---------------------------- CEC CFGR Configuration -----------------*/ - /* Get the CEC CFGR value */ - tmpreg = CEC->CFGR; - - /* Clear BTEM and BPEM bits */ - tmpreg &= CFGR_CLEAR_Mask; - - /* Configure CEC: Bit Timing Error and Bit Period Error */ - tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); - - /* Write to CEC CFGR register*/ - CEC->CFGR = tmpreg; - -} - -/** - * @brief Enables or disables the specified CEC peripheral. - * @param NewState: new state of the CEC peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CEC_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; - - if(NewState == DISABLE) - { - /* Wait until the PE bit is cleared by hardware (Idle Line detected) */ - while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) - { - } - } -} - -/** - * @brief Enables or disables the CEC interrupt. - * @param NewState: new state of the CEC interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CEC_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; -} - -/** - * @brief Defines the Own Address of the CEC device. - * @param CEC_OwnAddress: The CEC own address - * @retval None - */ -void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) -{ - /* Check the parameters */ - assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); - - /* Set the CEC own address */ - CEC->OAR = CEC_OwnAddress; -} - -/** - * @brief Sets the CEC prescaler value. - * @param CEC_Prescaler: CEC prescaler new value - * @retval None - */ -void CEC_SetPrescaler(uint16_t CEC_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); - - /* Set the Prescaler value*/ - CEC->PRES = CEC_Prescaler; -} - -/** - * @brief Transmits single data through the CEC peripheral. - * @param Data: the data to transmit. - * @retval None - */ -void CEC_SendDataByte(uint8_t Data) -{ - /* Transmit Data */ - CEC->TXD = Data ; -} - - -/** - * @brief Returns the most recent received data by the CEC peripheral. - * @param None - * @retval The received data. - */ -uint8_t CEC_ReceiveDataByte(void) -{ - /* Receive Data */ - return (uint8_t)(CEC->RXD); -} - -/** - * @brief Starts a new message. - * @param None - * @retval None - */ -void CEC_StartOfMessage(void) -{ - /* Starts of new message */ - *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; -} - -/** - * @brief Transmits message with or without an EOM bit. - * @param NewState: new state of the CEC Tx End Of Message. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CEC_EndOfMessageCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* The data byte will be transmitted with or without an EOM bit*/ - *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; -} - -/** - * @brief Gets the CEC flag status - * @param CEC_FLAG: specifies the CEC flag to check. - * This parameter can be one of the following values: - * @arg CEC_FLAG_BTE: Bit Timing Error - * @arg CEC_FLAG_BPE: Bit Period Error - * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error - * @arg CEC_FLAG_SBE: Start Bit Error - * @arg CEC_FLAG_ACKE: Block Acknowledge Error - * @arg CEC_FLAG_LINE: Line Error - * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error - * @arg CEC_FLAG_TEOM: Tx End Of Message - * @arg CEC_FLAG_TERR: Tx Error - * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished - * @arg CEC_FLAG_RSOM: Rx Start Of Message - * @arg CEC_FLAG_REOM: Rx End Of Message - * @arg CEC_FLAG_RERR: Rx Error - * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished - * @retval The new state of CEC_FLAG (SET or RESET) - */ -FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t cecreg = 0, cecbase = 0; - - /* Check the parameters */ - assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); - - /* Get the CEC peripheral base address */ - cecbase = (uint32_t)(CEC_BASE); - - /* Read flag register index */ - cecreg = CEC_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - CEC_FLAG &= FLAG_Mask; - - if(cecreg != 0) - { - /* Flag in CEC ESR Register */ - CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); - - /* Get the CEC ESR register address */ - cecbase += 0xC; - } - else - { - /* Get the CEC CSR register address */ - cecbase += 0x10; - } - - if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) - { - /* CEC_FLAG is set */ - bitstatus = SET; - } - else - { - /* CEC_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the CEC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CEC's pending flags. - * @param CEC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg CEC_FLAG_TERR: Tx Error - * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished - * @arg CEC_FLAG_RSOM: Rx Start Of Message - * @arg CEC_FLAG_REOM: Rx End Of Message - * @arg CEC_FLAG_RERR: Rx Error - * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished - * @retval None - */ -void CEC_ClearFlag(uint32_t CEC_FLAG) -{ - uint32_t tmp = 0x0; - - /* Check the parameters */ - assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); - - tmp = CEC->CSR & 0x2; - - /* Clear the selected CEC flags */ - CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); -} - -/** - * @brief Checks whether the specified CEC interrupt has occurred or not. - * @param CEC_IT: specifies the CEC interrupt source to check. - * This parameter can be one of the following values: - * @arg CEC_IT_TERR: Tx Error - * @arg CEC_IT_TBTF: Tx Block Transfer Finished - * @arg CEC_IT_RERR: Rx Error - * @arg CEC_IT_RBTF: Rx Block Transfer Finished - * @retval The new state of CEC_IT (SET or RESET). - */ -ITStatus CEC_GetITStatus(uint8_t CEC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_CEC_GET_IT(CEC_IT)); - - /* Get the CEC IT enable bit status */ - enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; - - /* Check the status of the specified CEC interrupt */ - if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) - { - /* CEC_IT is set */ - bitstatus = SET; - } - else - { - /* CEC_IT is reset */ - bitstatus = RESET; - } - /* Return the CEC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the CEC's interrupt pending bits. - * @param CEC_IT: specifies the CEC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg CEC_IT_TERR: Tx Error - * @arg CEC_IT_TBTF: Tx Block Transfer Finished - * @arg CEC_IT_RERR: Rx Error - * @arg CEC_IT_RBTF: Rx Block Transfer Finished - * @retval None - */ -void CEC_ClearITPendingBit(uint16_t CEC_IT) -{ - uint32_t tmp = 0x0; - - /* Check the parameters */ - assert_param(IS_CEC_GET_IT(CEC_IT)); - - tmp = CEC->CSR & 0x2; - - /* Clear the selected CEC interrupt pending bits */ - CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_crc.c b/example/libs_stm/src/stm32f10x/stm32f10x_crc.c deleted file mode 100644 index c9291f4c4..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_crc.c +++ /dev/null @@ -1,163 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_crc.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the CRC firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_crc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRC - * @brief CRC driver modules - * @{ - */ - -/** @defgroup CRC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Defines - * @{ - */ - -/* CR register bit mask */ - -#define CR_RESET_Set ((uint32_t)0x00000001) - -/** - * @} - */ - -/** @defgroup CRC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup CRC_Private_Functions - * @{ - */ - -/** - * @brief Resets the CRC Data register (DR). - * @param None - * @retval None - */ -void CRC_ResetDR(void) -{ - /* Reset CRC generator */ - CRC->CR = CR_RESET_Set; -} - -/** - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * @param Data: data word(32-bit) to compute its CRC - * @retval 32-bit CRC - */ -uint32_t CRC_CalcCRC(uint32_t Data) -{ - CRC->DR = Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed - * @retval 32-bit CRC - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DR = pBuffer[index]; - } - return (CRC->DR); -} - -/** - * @brief Returns the current CRC value. - * @param None - * @retval 32-bit CRC - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DR); -} - -/** - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param IDValue: 8-bit value to be stored in the ID register - * @retval None - */ -void CRC_SetIDRegister(uint8_t IDValue) -{ - CRC->IDR = IDValue; -} - -/** - * @brief Returns the 8-bit data stored in the Independent Data(ID) register - * @param None - * @retval 8-bit value of the ID register - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDR); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_dac.c b/example/libs_stm/src/stm32f10x/stm32f10x_dac.c deleted file mode 100644 index e20b4a933..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_dac.c +++ /dev/null @@ -1,579 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dac.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the DAC firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dac.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/** @defgroup DAC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Defines - * @{ - */ - -/* DAC EN mask */ -#define CR_EN_Set ((uint32_t)0x00000001) - -/* DAC DMAEN mask */ -#define CR_DMAEN_Set ((uint32_t)0x00001000) - -/* CR register Mask */ -#define CR_CLEAR_Mask ((uint32_t)0x00000FFE) - -/* DAC SWTRIG mask */ -#define SWTRIGR_SWTRIG_Set ((uint32_t)0x00000001) - -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_Set ((uint32_t)0x00000003) -#define DUAL_SWTRIG_Reset ((uint32_t)0xFFFFFFFC) - -/* DHR registers offsets */ -#define DHR12R1_Offset ((uint32_t)0x00000008) -#define DHR12R2_Offset ((uint32_t)0x00000014) -#define DHR12RD_Offset ((uint32_t)0x00000020) - -/* DOR register offset */ -#define DOR_Offset ((uint32_t)0x0000002C) -/** - * @} - */ - -/** @defgroup DAC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void DAC_DeInit(void) -{ - /* Enable DAC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); - /* Release DAC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); -} - -/** - * @brief Initializes the DAC peripheral according to the specified - * parameters in the DAC_InitStruct. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that - * contains the configuration information for the specified DAC channel. - * @retval None - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); - assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); -/*---------------------------- DAC CR Configuration --------------------------*/ - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(CR_CLEAR_Mask << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, wave genration, - mask/amplitude for wave genration */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set WAVEx bits according to DAC_WaveGeneration value */ - /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << DAC_Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; -} - -/** - * @brief Fills each DAC_InitStruct member with its default value. - * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) -{ -/*--------------- Reset DAC init structure parameters values -----------------*/ - /* Initialize the DAC_Trigger member */ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - /* Initialize the DAC_WaveGeneration member */ - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - /* Initialize the DAC_OutputBuffer member */ - DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -/** - * @brief Enables or disables the specified DAC channel. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DAC channel */ - DAC->CR |= CR_EN_Set << DAC_Channel; - } - else - { - /* Disable the selected DAC channel */ - DAC->CR &= ~(CR_EN_Set << DAC_Channel); - } -} -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) -/** - * @brief Enables or disables the specified DAC interrupts. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @param NewState: new state of the specified DAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_DAC_IT(DAC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC interrupts */ - DAC->CR |= (DAC_IT << DAC_Channel); - } - else - { - /* Disable the selected DAC interrupts */ - DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); - } -} -#endif - -/** - * @brief Enables or disables the specified DAC channel DMA request. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DAC channel DMA request */ - DAC->CR |= CR_DMAEN_Set << DAC_Channel; - } - else - { - /* Disable the selected DAC channel DMA request */ - DAC->CR &= ~(CR_DMAEN_Set << DAC_Channel); - } -} - -/** - * @brief Enables or disables the selected DAC channel software trigger. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable software trigger for the selected DAC channel */ - DAC->SWTRIGR |= SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4); - } - else - { - /* Disable software trigger for the selected DAC channel */ - DAC->SWTRIGR &= ~(SWTRIGR_SWTRIG_Set << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enables or disables simultaneously the two DAC channels software - * triggers. - * @param NewState: new state of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable software trigger for both DAC channels */ - DAC->SWTRIGR |= DUAL_SWTRIG_Set ; - } - else - { - /* Disable software trigger for both DAC channels */ - DAC->SWTRIGR &= DUAL_SWTRIG_Reset; - } -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_Wave: Specifies the wave type to enable or disable. - * This parameter can be one of the following values: - * @arg DAC_Wave_Noise: noise wave generation - * @arg DAC_Wave_Triangle: triangle wave generation - * @param NewState: new state of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_WAVE(DAC_Wave)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected wave generation for the selected DAC channel */ - DAC->CR |= DAC_Wave << DAC_Channel; - } - else - { - /* Disable the selected wave generation for the selected DAC channel */ - DAC->CR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: Specifies the data alignement for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignement selected - * @arg DAC_Align_12b_L: 12bit left data alignement selected - * @arg DAC_Align_12b_R: 12bit right data alignement selected - * @param Data : Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R1_Offset + DAC_Align; - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Set the specified data holding register value for DAC channel2. - * @param DAC_Align: Specifies the data alignement for DAC channel2. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignement selected - * @arg DAC_Align_12b_L: 12bit left data alignement selected - * @arg DAC_Align_12b_R: 12bit right data alignement selected - * @param Data : Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R2_Offset + DAC_Align; - - /* Set the DAC channel2 selected data holding register */ - *(__IO uint32_t *)tmp = Data; -} - -/** - * @brief Set the specified data holding register value for dual channel - * DAC. - * @param DAC_Align: Specifies the data alignement for dual channel DAC. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignement selected - * @arg DAC_Align_12b_L: 12bit left data alignement selected - * @arg DAC_Align_12b_R: 12bit right data alignement selected - * @param Data2: Data for DAC Channel2 to be loaded in the selected data - * holding register. - * @param Data1: Data for DAC Channel1 to be loaded in the selected data - * holding register. - * @retval None - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12RD_Offset + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; -} - -/** - * @brief Returns the last data output value of the selected DAC cahnnel. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - - tmp = (uint32_t) DAC_BASE ; - tmp += DOR_Offset + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) -/** - * @brief Checks whether the specified DAC flag is set or not. - * @param DAC_Channel: thee selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to check. - * This parameter can be only of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @retval The new state of DAC_FLAG (SET or RESET). - */ -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Check the status of the specified DAC flag */ - if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) - { - /* DAC_FLAG is set */ - bitstatus = SET; - } - else - { - /* DAC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DAC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channelx's pending flags. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to clear. - * This parameter can be of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @retval None - */ -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Clear the selected DAC flags */ - DAC->SR = (DAC_FLAG << DAC_Channel); -} - -/** - * @brief Checks whether the specified DAC interrupt has occurred or not. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt source to check. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @retval The new state of DAC_IT (SET or RESET). - */ -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Get the DAC_IT enable bit status */ - enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; - - /* Check the status of the specified DAC interrupt */ - if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) - { - /* DAC_IT is set */ - bitstatus = SET; - } - else - { - /* DAC_IT is reset */ - bitstatus = RESET; - } - /* Return the DAC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channelxs interrupt pending bits. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt pending bit to clear. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @retval None - */ -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Clear the selected DAC interrupt pending bits */ - DAC->SR = (DAC_IT << DAC_Channel); -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_dbgmcu.c b/example/libs_stm/src/stm32f10x/stm32f10x_dbgmcu.c deleted file mode 100644 index 6cfceba07..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_dbgmcu.c +++ /dev/null @@ -1,161 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dbgmcu.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the DBGMCU firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dbgmcu.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DBGMCU - * @brief DBGMCU driver modules - * @{ - */ - -/** @defgroup DBGMCU_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Defines - * @{ - */ - -#define IDCODE_DEVID_Mask ((uint32_t)0x00000FFF) -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DBGMCU_Private_Functions - * @{ - */ - -/** - * @brief Returns the device revision identifier. - * @param None - * @retval Device revision identifier - */ -uint32_t DBGMCU_GetREVID(void) -{ - return(DBGMCU->IDCODE >> 16); -} - -/** - * @brief Returns the device identifier. - * @param None - * @retval Device identifier - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return(DBGMCU->IDCODE & IDCODE_DEVID_Mask); -} - -/** - * @brief Configures the specified peripheral and low power mode behavior - * when the MCU under Debug mode. - * @param DBGMCU_Periph: specifies the peripheral and low power mode. - * This parameter can be any combination of the following values: - * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode - * @arg DBGMCU_STOP: Keep debugger connection during STOP mode - * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode - * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted - * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted - * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted - * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted - * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted - * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted - * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted - * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted - * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted - * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted - * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted - * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted - * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted - * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted - * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted - * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted - * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted - * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted - * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted - * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted - * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted - * @param NewState: new state of the specified peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->CR |= DBGMCU_Periph; - } - else - { - DBGMCU->CR &= ~DBGMCU_Periph; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_dma.c b/example/libs_stm/src/stm32f10x/stm32f10x_dma.c deleted file mode 100644 index aa890c6a6..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_dma.c +++ /dev/null @@ -1,693 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_dma.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the DMA firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_dma.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/** @defgroup DMA_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup DMA_Private_Defines - * @{ - */ - -/* DMA ENABLE mask */ -#define CCR_ENABLE_Set ((uint32_t)0x00000001) -#define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE) - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F) -#define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0) -#define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00) -#define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000) -#define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000) -#define DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000) -#define DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000) - -/* DMA2 Channelx interrupt pending bit masks */ -#define DMA2_Channel1_IT_Mask ((uint32_t)0x0000000F) -#define DMA2_Channel2_IT_Mask ((uint32_t)0x000000F0) -#define DMA2_Channel3_IT_Mask ((uint32_t)0x00000F00) -#define DMA2_Channel4_IT_Mask ((uint32_t)0x0000F000) -#define DMA2_Channel5_IT_Mask ((uint32_t)0x000F0000) - -/* DMA2 FLAG mask */ -#define FLAG_Mask ((uint32_t)0x10000000) - -/* DMA registers Masks */ -#define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) - -/** - * @} - */ - -/** @defgroup DMA_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the DMAy Channelx registers to their default reset - * values. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @retval None - */ -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= CCR_ENABLE_Reset; - /* Reset DMAy Channelx control register */ - DMAy_Channelx->CCR = 0; - - /* Reset DMAy Channelx remaining bytes register */ - DMAy_Channelx->CNDTR = 0; - - /* Reset DMAy Channelx peripheral address register */ - DMAy_Channelx->CPAR = 0; - - /* Reset DMAy Channelx memory address register */ - DMAy_Channelx->CMAR = 0; - - if (DMAy_Channelx == DMA1_Channel1) - { - /* Reset interrupt pending bits for DMA1 Channel1 */ - DMA1->IFCR |= DMA1_Channel1_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel2) - { - /* Reset interrupt pending bits for DMA1 Channel2 */ - DMA1->IFCR |= DMA1_Channel2_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel3) - { - /* Reset interrupt pending bits for DMA1 Channel3 */ - DMA1->IFCR |= DMA1_Channel3_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel4) - { - /* Reset interrupt pending bits for DMA1 Channel4 */ - DMA1->IFCR |= DMA1_Channel4_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel5) - { - /* Reset interrupt pending bits for DMA1 Channel5 */ - DMA1->IFCR |= DMA1_Channel5_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel6) - { - /* Reset interrupt pending bits for DMA1 Channel6 */ - DMA1->IFCR |= DMA1_Channel6_IT_Mask; - } - else if (DMAy_Channelx == DMA1_Channel7) - { - /* Reset interrupt pending bits for DMA1 Channel7 */ - DMA1->IFCR |= DMA1_Channel7_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel1) - { - /* Reset interrupt pending bits for DMA2 Channel1 */ - DMA2->IFCR |= DMA2_Channel1_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel2) - { - /* Reset interrupt pending bits for DMA2 Channel2 */ - DMA2->IFCR |= DMA2_Channel2_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel3) - { - /* Reset interrupt pending bits for DMA2 Channel3 */ - DMA2->IFCR |= DMA2_Channel3_IT_Mask; - } - else if (DMAy_Channelx == DMA2_Channel4) - { - /* Reset interrupt pending bits for DMA2 Channel4 */ - DMA2->IFCR |= DMA2_Channel4_IT_Mask; - } - else - { - if (DMAy_Channelx == DMA2_Channel5) - { - /* Reset interrupt pending bits for DMA2 Channel5 */ - DMA2->IFCR |= DMA2_Channel5_IT_Mask; - } - } -} - -/** - * @brief Initializes the DMAy Channelx according to the specified - * parameters in the DMA_InitStruct. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that - * contains the configuration information for the specified DMA Channel. - * @retval None - */ -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); - assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); - assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); - assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); - assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); - -/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ - /* Get the DMAy_Channelx CCR value */ - tmpreg = DMAy_Channelx->CCR; - /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmpreg &= CCR_CLEAR_Mask; - /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ - /* Set DIR bit according to DMA_DIR value */ - /* Set CIRC bit according to DMA_Mode value */ - /* Set PINC bit according to DMA_PeripheralInc value */ - /* Set MINC bit according to DMA_MemoryInc value */ - /* Set PSIZE bits according to DMA_PeripheralDataSize value */ - /* Set MSIZE bits according to DMA_MemoryDataSize value */ - /* Set PL bits according to DMA_Priority value */ - /* Set the MEM2MEM bit according to DMA_M2M value */ - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - /* Write to DMAy Channelx CCR */ - DMAy_Channelx->CCR = tmpreg; - -/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; - -/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ - /* Write to DMAy Channelx CPAR */ - DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; - -/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ - /* Write to DMAy Channelx CMAR */ - DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ -/*-------------- Reset DMA init structure parameters values ------------------*/ - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - /* Initialize the DMA_MemoryBaseAddr member */ - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - /* Initialize the DMA_MemoryInc member */ - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - /* Initialize the DMA_Priority member */ - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - /* Initialize the DMA_M2M member */ - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/** - * @brief Enables or disables the specified DMAy Channelx. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param NewState: new state of the DMAy Channelx. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMAy Channelx */ - DMAy_Channelx->CCR |= CCR_ENABLE_Set; - } - else - { - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= CCR_ENABLE_Reset; - } -} - -/** - * @brief Enables or disables the specified DMAy Channelx interrupts. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @param DMA_IT: specifies the DMA interrupts sources to be enabled - * or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @param NewState: new state of the specified DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_CONFIG_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected DMA interrupts */ - DMAy_Channelx->CCR |= DMA_IT; - } - else - { - /* Disable the selected DMA interrupts */ - DMAy_Channelx->CCR &= ~DMA_IT; - } -} - -/** - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and - * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. - * @retval The number of remaining data units in the current DMAy Channelx - * transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - /* Return the number of remaining data units for DMAy Channelx */ - return ((uint16_t)(DMAy_Channelx->CNDTR)); -} - -/** - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * @param DMA_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. - * @retval The new state of DMA_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); - - /* Calculate the used DMA */ - if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - /* Get DMA2 ISR register value */ - tmpreg = DMA2->ISR ; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR ; - } - - /* Check the status of the specified DMA flag */ - if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) - { - /* DMA_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMA_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the DMA_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx's pending flags. - * @param DMA_FLAG: specifies the flag to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. - * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. - * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. - * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. - * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. - * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. - * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. - * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. - * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. - * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. - * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. - * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. - * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. - * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. - * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. - * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. - * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. - * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. - * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. - * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. - * @retval None - */ -void DMA_ClearFlag(uint32_t DMA_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); - /* Calculate the used DMA */ - - if ((DMA_FLAG & FLAG_Mask) != (uint32_t)RESET) - { - /* Clear the selected DMA flags */ - DMA2->IFCR = DMA_FLAG; - } - else - { - /* Clear the selected DMA flags */ - DMA1->IFCR = DMA_FLAG; - } -} - -/** - * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. - * @param DMA_IT: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. - * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. - * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. - * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. - * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. - * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. - * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. - * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. - * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. - * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. - * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. - * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. - * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. - * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. - * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. - * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. - * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. - * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. - * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. - * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. - * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. - * @retval The new state of DMA_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMA_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_DMA_GET_IT(DMA_IT)); - - /* Calculate the used DMA */ - if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET) - { - /* Get DMA2 ISR register value */ - tmpreg = DMA2->ISR ; - } - else - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR ; - } - - /* Check the status of the specified DMA interrupt */ - if ((tmpreg & DMA_IT) != (uint32_t)RESET) - { - /* DMA_IT is set */ - bitstatus = SET; - } - else - { - /* DMA_IT is reset */ - bitstatus = RESET; - } - /* Return the DMA_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelxs interrupt pending bits. - * @param DMA_IT: specifies the DMA interrupt pending bit to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. - * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. - * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. - * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. - * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. - * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. - * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. - * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. - * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. - * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. - * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. - * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. - * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. - * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. - * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. - * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. - * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. - * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. - * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. - * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. - * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. - * @retval None - */ -void DMA_ClearITPendingBit(uint32_t DMA_IT) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_IT(DMA_IT)); - - /* Calculate the used DMA */ - if ((DMA_IT & FLAG_Mask) != (uint32_t)RESET) - { - /* Clear the selected DMA interrupt pending bits */ - DMA2->IFCR = DMA_IT; - } - else - { - /* Clear the selected DMA interrupt pending bits */ - DMA1->IFCR = DMA_IT; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_exti.c b/example/libs_stm/src/stm32f10x/stm32f10x_exti.c deleted file mode 100644 index eae3253ea..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_exti.c +++ /dev/null @@ -1,268 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_exti.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the EXTI firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_exti.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/** @defgroup EXTI_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Defines - * @{ - */ - -#define EXTI_LineNone ((uint32_t)0x00000) /* No interrupt selected */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - EXTI->IMR = 0x00000000; - EXTI->EMR = 0x00000000; - EXTI->RTSR = 0x00000000; - EXTI->FTSR = 0x00000000; - EXTI->PR = 0x000FFFFF; -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - - tmp = (uint32_t)EXTI_BASE; - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; - - tmp += EXTI_InitStruct->EXTI_Mode; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; - - /* Select the trigger for the selected external interrupts */ - if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - /* Rising Falling edge */ - EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - - /* Disable the selected external lines */ - *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LineNone; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/** - * @brief Generates a Software interrupt. - * @param EXTI_Line: specifies the EXTI lines to be enabled or disabled. - * This parameter can be any combination of EXTI_Linex where x can be (0..19). - * @retval None - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->SWIER |= EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param EXTI_Line: specifies the EXTI line flag to check. - * This parameter can be: - * @arg EXTI_Linex: External interrupt line x where x(0..19) - * @retval The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTIs line pending flags. - * @param EXTI_Line: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..19). - * @retval None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_Line: specifies the EXTI line to check. - * This parameter can be: - * @arg EXTI_Linex: External interrupt line x where x(0..19) - * @retval The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - enablestatus = EXTI->IMR & EXTI_Line; - if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTIs line pending bits. - * @param EXTI_Line: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..19). - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_flash.c b/example/libs_stm/src/stm32f10x/stm32f10x_flash.c deleted file mode 100644 index 3475e6a37..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_flash.c +++ /dev/null @@ -1,1735 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_flash.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the FLASH firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_flash.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/** @defgroup FLASH_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_Defines - * @{ - */ - -/* Flash Access Control Register bits */ -#define ACR_LATENCY_Mask ((uint32_t)0x00000038) -#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7) -#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF) - -/* Flash Access Control Register bits */ -#define ACR_PRFTBS_Mask ((uint32_t)0x00000020) - -/* Flash Control Register bits */ -#define CR_PG_Set ((uint32_t)0x00000001) -#define CR_PG_Reset ((uint32_t)0x00001FFE) -#define CR_PER_Set ((uint32_t)0x00000002) -#define CR_PER_Reset ((uint32_t)0x00001FFD) -#define CR_MER_Set ((uint32_t)0x00000004) -#define CR_MER_Reset ((uint32_t)0x00001FFB) -#define CR_OPTPG_Set ((uint32_t)0x00000010) -#define CR_OPTPG_Reset ((uint32_t)0x00001FEF) -#define CR_OPTER_Set ((uint32_t)0x00000020) -#define CR_OPTER_Reset ((uint32_t)0x00001FDF) -#define CR_STRT_Set ((uint32_t)0x00000040) -#define CR_LOCK_Set ((uint32_t)0x00000080) - -/* FLASH Mask */ -#define RDPRT_Mask ((uint32_t)0x00000002) -#define WRP0_Mask ((uint32_t)0x000000FF) -#define WRP1_Mask ((uint32_t)0x0000FF00) -#define WRP2_Mask ((uint32_t)0x00FF0000) -#define WRP3_Mask ((uint32_t)0xFF000000) -#define OB_USER_BFB2 ((uint16_t)0x0008) - -/* FLASH Keys */ -#define RDP_Key ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) - -/* FLASH BANK address */ -#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) - -/* Delay definition */ -#define EraseTimeout ((uint32_t)0x000B0000) -#define ProgramTimeout ((uint32_t)0x00002000) -/** - * @} - */ - -/** @defgroup FLASH_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** -@code - - This driver provides functions to configure and program the Flash memory of all STM32F10x devices, - including the latest STM32F10x_XL density devices. - - STM32F10x_XL devices feature up to 1 Mbyte with dual bank architecture for read-while-write (RWW) capability: - - bank1: fixed size of 512 Kbytes (256 pages of 2Kbytes each) - - bank2: up to 512 Kbytes (up to 256 pages of 2Kbytes each) - While other STM32F10x devices features only one bank with memory up to 512 Kbytes. - - In version V3.3.0, some functions were updated and new ones were added to support - STM32F10x_XL devices. Thus some functions manages all devices, while other are - dedicated for XL devices only. - - The table below presents the list of available functions depending on the used STM32F10x devices. - - *************************************************** - * Legacy functions used for all STM32F10x devices * - *************************************************** - +----------------------------------------------------------------------------------------------------------------------------------+ - | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | - | | devices | devices | | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_SetLatency | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_HalfCycleAccessCmd | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_PrefetchBufferCmd | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_Unlock | Yes | Yes | - For STM32F10X_XL devices: unlock Bank1 and Bank2. | - | | | | - For other devices: unlock Bank1 and it is equivalent | - | | | | to FLASH_UnlockBank1 function. | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_Lock | Yes | Yes | - For STM32F10X_XL devices: lock Bank1 and Bank2. | - | | | | - For other devices: lock Bank1 and it is equivalent | - | | | | to FLASH_LockBank1 function. | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ErasePage | Yes | Yes | - For STM32F10x_XL devices: erase a page in Bank1 and Bank2 | - | | | | - For other devices: erase a page in Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_EraseAllPages | Yes | Yes | - For STM32F10x_XL devices: erase all pages in Bank1 and Bank2 | - | | | | - For other devices: erase all pages in Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_EraseOptionBytes | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ProgramWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ProgramHalfWord | Yes | Yes | Updated to program up to 1MByte (depending on the used device) | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ProgramOptionByteData | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_EnableWriteProtection | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ReadOutProtection | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_UserOptionByteConfig | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetUserOptionByte | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetWriteProtectionOptionByte | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetReadOutProtectionStatus | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetPrefetchBufferStatus | Yes | Yes | No change | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ITConfig | Yes | Yes | - For STM32F10x_XL devices: enable Bank1 and Bank2's interrupts| - | | | | - For other devices: enable Bank1's interrupts | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetFlagStatus | Yes | Yes | - For STM32F10x_XL devices: return Bank1 and Bank2's flag status| - | | | | - For other devices: return Bank1's flag status | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_ClearFlag | Yes | Yes | - For STM32F10x_XL devices: clear Bank1 and Bank2's flag | - | | | | - For other devices: clear Bank1's flag | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_GetStatus | Yes | Yes | - Return the status of Bank1 (for all devices) | - | | | | equivalent to FLASH_GetBank1Status function | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_WaitForLastOperation | Yes | Yes | - Wait for Bank1 last operation (for all devices) | - | | | | equivalent to: FLASH_WaitForLastBank1Operation function | - +----------------------------------------------------------------------------------------------------------------------------------+ - - ************************************************************************************************************************ - * New functions used for all STM32F10x devices to manage Bank1: * - * - These functions are mainly useful for STM32F10x_XL density devices, to have separate control for Bank1 and bank2 * - * - For other devices, these functions are optional (covered by functions listed above) * - ************************************************************************************************************************ - +----------------------------------------------------------------------------------------------------------------------------------+ - | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | - | | devices | devices | | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_UnlockBank1 | Yes | Yes | - Unlock Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_LockBank1 | Yes | Yes | - Lock Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_EraseAllBank1Pages | Yes | Yes | - Erase all pages in Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_GetBank1Status | Yes | Yes | - Return the status of Bank1 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_WaitForLastBank1Operation | Yes | Yes | - Wait for Bank1 last operation | - +----------------------------------------------------------------------------------------------------------------------------------+ - - ***************************************************************************** - * New Functions used only with STM32F10x_XL density devices to manage Bank2 * - ***************************************************************************** - +----------------------------------------------------------------------------------------------------------------------------------+ - | Functions prototypes |STM32F10x_XL|Other STM32F10x| Comments | - | | devices | devices | | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_UnlockBank2 | Yes | No | - Unlock Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - |FLASH_LockBank2 | Yes | No | - Lock Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_EraseAllBank2Pages | Yes | No | - Erase all pages in Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_GetBank2Status | Yes | No | - Return the status of Bank2 | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_WaitForLastBank2Operation | Yes | No | - Wait for Bank2 last operation | - |----------------------------------------------------------------------------------------------------------------------------------| - | FLASH_BootConfig | Yes | No | - Configure to boot from Bank1 or Bank2 | - +----------------------------------------------------------------------------------------------------------------------------------+ -@endcode -*/ - - -/** - * @brief Sets the code latency value. - * @note This function can be used for all STM32F10x devices. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @arg FLASH_Latency_2: FLASH Two Latency cycles - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Read the ACR register */ - tmpreg = FLASH->ACR; - - /* Sets the Latency value */ - tmpreg &= ACR_LATENCY_Mask; - tmpreg |= FLASH_Latency; - - /* Write the ACR register */ - FLASH->ACR = tmpreg; -} - -/** - * @brief Enables or disables the Half cycle flash access. - * @note This function can be used for all STM32F10x devices. - * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode. - * This parameter can be one of the following values: - * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable - * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable - * @retval None - */ -void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess) -{ - /* Check the parameters */ - assert_param(IS_FLASH_HALFCYCLEACCESS_STATE(FLASH_HalfCycleAccess)); - - /* Enable or disable the Half cycle access */ - FLASH->ACR &= ACR_HLFCYA_Mask; - FLASH->ACR |= FLASH_HalfCycleAccess; -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @note This function can be used for all STM32F10x devices. - * @param FLASH_PrefetchBuffer: specifies the Prefetch buffer status. - * This parameter can be one of the following values: - * @arg FLASH_PrefetchBuffer_Enable: FLASH Prefetch Buffer Enable - * @arg FLASH_PrefetchBuffer_Disable: FLASH Prefetch Buffer Disable - * @retval None - */ -void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer) -{ - /* Check the parameters */ - assert_param(IS_FLASH_PREFETCHBUFFER_STATE(FLASH_PrefetchBuffer)); - - /* Enable or disable the Prefetch Buffer */ - FLASH->ACR &= ACR_PRFTBE_Mask; - FLASH->ACR |= FLASH_PrefetchBuffer; -} - -/** - * @brief Unlocks the FLASH Program Erase Controller. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function unlocks Bank1 and Bank2. - * - For all other devices it unlocks Bank1 and it is equivalent - * to FLASH_UnlockBank1 function.. - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - -#ifdef STM32F10X_XL - /* Authorize the FPEC of Bank2 Access */ - FLASH->KEYR2 = FLASH_KEY1; - FLASH->KEYR2 = FLASH_KEY2; -#endif /* STM32F10X_XL */ -} -/** - * @brief Unlocks the FLASH Bank1 Program Erase Controller. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function unlocks Bank1. - * - For all other devices it unlocks Bank1 and it is - * equivalent to FLASH_Unlock function. - * @param None - * @retval None - */ -void FLASH_UnlockBank1(void) -{ - /* Authorize the FPEC of Bank1 Access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; -} - -#ifdef STM32F10X_XL -/** - * @brief Unlocks the FLASH Bank2 Program Erase Controller. - * @note This function can be used only for STM32F10X_XL density devices. - * @param None - * @retval None - */ -void FLASH_UnlockBank2(void) -{ - /* Authorize the FPEC of Bank2 Access */ - FLASH->KEYR2 = FLASH_KEY1; - FLASH->KEYR2 = FLASH_KEY2; - -} -#endif /* STM32F10X_XL */ - -/** - * @brief Locks the FLASH Program Erase Controller. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function Locks Bank1 and Bank2. - * - For all other devices it Locks Bank1 and it is equivalent - * to FLASH_LockBank1 function. - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ - FLASH->CR |= CR_LOCK_Set; - -#ifdef STM32F10X_XL - /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ - FLASH->CR2 |= CR_LOCK_Set; -#endif /* STM32F10X_XL */ -} - -/** - * @brief Locks the FLASH Bank1 Program Erase Controller. - * @note this function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function Locks Bank1. - * - For all other devices it Locks Bank1 and it is equivalent - * to FLASH_Lock function. - * @param None - * @retval None - */ -void FLASH_LockBank1(void) -{ - /* Set the Lock Bit to lock the FPEC and the CR of Bank1 */ - FLASH->CR |= CR_LOCK_Set; -} - -#ifdef STM32F10X_XL -/** - * @brief Locks the FLASH Bank2 Program Erase Controller. - * @note This function can be used only for STM32F10X_XL density devices. - * @param None - * @retval None - */ -void FLASH_LockBank2(void) -{ - /* Set the Lock Bit to lock the FPEC and the CR of Bank2 */ - FLASH->CR2 |= CR_LOCK_Set; -} -#endif /* STM32F10X_XL */ - -/** - * @brief Erases a specified FLASH page. - * @note This function can be used for all STM32F10x devices. - * @param Page_Address: The page address to be erased. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Page_Address)); - -#ifdef STM32F10X_XL - if(Page_Address < FLASH_BANK1_END_ADDRESS) - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the page */ - FLASH->CR|= CR_PER_Set; - FLASH->AR = Page_Address; - FLASH->CR|= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the erase operation is completed, disable the PER Bit */ - FLASH->CR &= CR_PER_Reset; - } - } - } - else - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the page */ - FLASH->CR2|= CR_PER_Set; - FLASH->AR2 = Page_Address; - FLASH->CR2|= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the erase operation is completed, disable the PER Bit */ - FLASH->CR2 &= CR_PER_Reset; - } - } - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the page */ - FLASH->CR|= CR_PER_Set; - FLASH->AR = Page_Address; - FLASH->CR|= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the erase operation is completed, disable the PER Bit */ - FLASH->CR &= CR_PER_Reset; - } - } -#endif /* STM32F10X_XL */ - - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH pages. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllPages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - -#ifdef STM32F10X_XL - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= CR_MER_Set; - FLASH->CR |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= CR_MER_Reset; - } - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR2 |= CR_MER_Set; - FLASH->CR2 |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR2 &= CR_MER_Reset; - } - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= CR_MER_Set; - FLASH->CR |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= CR_MER_Reset; - } - } -#endif /* STM32F10X_XL */ - - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all Bank1 FLASH pages. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices this function erases all Bank1 pages. - * - For all other devices it erases all Bank1 pages and it is equivalent - * to FLASH_EraseAllPages function. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllBank1Pages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR |= CR_MER_Set; - FLASH->CR |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(EraseTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= CR_MER_Reset; - } - } - /* Return the Erase Status */ - return status; -} - -#ifdef STM32F10X_XL -/** - * @brief Erases all Bank2 FLASH pages. - * @note This function can be used only for STM32F10x_XL density devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseAllBank2Pages(void) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all pages */ - FLASH->CR2 |= CR_MER_Set; - FLASH->CR2 |= CR_STRT_Set; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(EraseTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR2 &= CR_MER_Reset; - } - } - /* Return the Erase Status */ - return status; -} -#endif /* STM32F10X_XL */ - -/** - * @brief Erases the FLASH option bytes. - * @note This functions erases all option bytes except the Read protection (RDP). - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EraseOptionBytes(void) -{ - uint16_t rdptmp = RDP_Key; - - FLASH_Status status = FLASH_COMPLETE; - - /* Get the actual read protection Option Byte value */ - if(FLASH_GetReadOutProtectionStatus() != RESET) - { - rdptmp = 0x00; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* if the previous operation is completed, proceed to erase the option bytes */ - FLASH->CR |= CR_OPTER_Set; - FLASH->CR |= CR_STRT_Set; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - /* Restore the last read protection Option Byte value */ - OB->RDP = (uint16_t)rdptmp; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - else - { - if (status != FLASH_TIMEOUT) - { - /* Disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - } - /* Return the erase status */ - return status; -} - -/** - * @brief Programs a word at a specified address. - * @note This function can be used for all STM32F10x devices. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - -#ifdef STM32F10X_XL - if(Address < FLASH_BANK1_END_ADDRESS - 2) - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - else - { - if (status != FLASH_TIMEOUT) - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - } - } - else if(Address == (FLASH_BANK1_END_ADDRESS - 1)) - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - else - { - if (status != FLASH_TIMEOUT) - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - FLASH->CR2 |= CR_PG_Set; - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - } - else - { - if (status != FLASH_TIMEOUT) - { - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - } - } - else - { - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR2 |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - } - else - { - if (status != FLASH_TIMEOUT) - { - /* Disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - } - } - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new first - half word */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = (uint16_t)Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new second - half word */ - tmp = Address + 2; - - *(__IO uint16_t*) tmp = Data >> 16; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status != FLASH_TIMEOUT) - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - else - { - if (status != FLASH_TIMEOUT) - { - /* Disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - } -#endif /* STM32F10X_XL */ - - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word at a specified address. - * @note This function can be used for all STM32F10x devices. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - -#ifdef STM32F10X_XL - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(Address < FLASH_BANK1_END_ADDRESS) - { - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank1Operation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } - } - else - { - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR2 |= CR_PG_Set; - - *(__IO uint16_t*)Address = Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastBank2Operation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR2 &= CR_PG_Reset; - } - } - } -#else - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR |= CR_PG_Set; - - *(__IO uint16_t*)Address = Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= CR_PG_Reset; - } - } -#endif /* STM32F10X_XL */ - - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word at a specified Option Byte Data address. - * @note This function can be used for all STM32F10x devices. - * @param Address: specifies the address to be programmed. - * This parameter can be 0x1FFFF804 or 0x1FFFF806. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_OB_DATA_ADDRESS(Address)); - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - /* Enables the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the Option Byte Data Program Status */ - return status; -} - -/** - * @brief Write protects the desired pages - * @note This function can be used for all STM32F10x devices. - * @param FLASH_Pages: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg For @b STM32_Low-density_devices: value between FLASH_WRProt_Pages0to3 and FLASH_WRProt_Pages28to31 - * @arg For @b STM32_Medium-density_devices: value between FLASH_WRProt_Pages0to3 - * and FLASH_WRProt_Pages124to127 - * @arg For @b STM32_High-density_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to255 - * @arg For @b STM32_Connectivity_line_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to127 - * @arg For @b STM32_XL-density_devices: value between FLASH_WRProt_Pages0to1 and - * FLASH_WRProt_Pages60to61 or FLASH_WRProt_Pages62to511 - * @arg FLASH_WRProt_AllPages - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages) -{ - uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; - - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_WRPROT_PAGE(FLASH_Pages)); - - FLASH_Pages = (uint32_t)(~FLASH_Pages); - WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask); - WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8); - WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16); - WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Authorizes the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - FLASH->CR |= CR_OPTPG_Set; - if(WRP0_Data != 0xFF) - { - OB->WRP0 = WRP0_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF)) - { - OB->WRP1 = WRP1_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF)) - { - OB->WRP2 = WRP2_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - - if((status == FLASH_COMPLETE)&& (WRP3_Data != 0xFF)) - { - OB->WRP3 = WRP3_Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - } - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the write protection operation Status */ - return status; -} - -/** - * @brief Enables or disables the read out protection. - * @note If the user has already programmed the other option bytes before calling - * this function, he must re-program them since this function erases all option bytes. - * @note This function can be used for all STM32F10x devices. - * @param Newstate: new state of the ReadOut Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* Authorizes the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - FLASH->CR |= CR_OPTER_Set; - FLASH->CR |= CR_STRT_Set; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - if(status == FLASH_COMPLETE) - { - /* if the erase operation is completed, disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - if(NewState != DISABLE) - { - OB->RDP = 0x00; - } - else - { - OB->RDP = RDP_Key; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(EraseTimeout); - - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - else - { - if(status != FLASH_TIMEOUT) - { - /* Disable the OPTER Bit */ - FLASH->CR &= CR_OPTER_Reset; - } - } - } - /* Return the protection operation Status */ - return status; -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @note This function can be used for all STM32F10x devices. - * @param OB_IWDG: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - - OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8))); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the Option Byte program Status */ - return status; -} - -#ifdef STM32F10X_XL -/** - * @brief Configures to boot from Bank1 or Bank2. - * @note This function can be used only for STM32F10x_XL density devices. - * @param FLASH_BOOT: select the FLASH Bank to boot from. - * This parameter can be one of the following values: - * @arg FLASH_BOOT_Bank1: At startup, if boot pins are set in boot from user Flash - * position and this parameter is selected the device will boot from Bank1(Default). - * @arg FLASH_BOOT_Bank2: At startup, if boot pins are set in boot from user Flash - * position and this parameter is selected the device will boot from Bank2 or Bank1, - * depending on the activation of the bank. The active banks are checked in - * the following order: Bank2, followed by Bank1. - * The active bank is recognized by the value programmed at the base address - * of the respective bank (corresponding to the initial stack pointer value - * in the interrupt vector table). - * For more information, please refer to AN2606 from www.st.com. - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_BootConfig(uint16_t FLASH_BOOT) -{ - FLASH_Status status = FLASH_COMPLETE; - assert_param(IS_FLASH_BOOT(FLASH_BOOT)); - /* Authorize the small information block programming */ - FLASH->OPTKEYR = FLASH_KEY1; - FLASH->OPTKEYR = FLASH_KEY2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - - if(status == FLASH_COMPLETE) - { - /* Enable the Option Bytes Programming operation */ - FLASH->CR |= CR_OPTPG_Set; - - if(FLASH_BOOT == FLASH_BOOT_Bank1) - { - OB->USER |= OB_USER_BFB2; - } - else - { - OB->USER &= (uint16_t)(~(uint16_t)(OB_USER_BFB2)); - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(ProgramTimeout); - if(status != FLASH_TIMEOUT) - { - /* if the program operation is completed, disable the OPTPG Bit */ - FLASH->CR &= CR_OPTPG_Reset; - } - } - /* Return the Option Byte program Status */ - return status; -} -#endif /* STM32F10X_XL */ - -/** - * @brief Returns the FLASH User Option Bytes values. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -uint32_t FLASH_GetUserOptionByte(void) -{ - /* Return the User Option Byte */ - return (uint32_t)(FLASH->OBR >> 2); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes Register value. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval The FLASH Write Protection Option Bytes Register value - */ -uint32_t FLASH_GetWriteProtectionOptionByte(void) -{ - /* Return the Falsh write protection Register value */ - return (uint32_t)(FLASH->WRPR); -} - -/** - * @brief Checks whether the FLASH Read Out Protection Status is set or not. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_GetReadOutProtectionStatus(void) -{ - FlagStatus readoutstatus = RESET; - if ((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) - { - readoutstatus = SET; - } - else - { - readoutstatus = RESET; - } - return readoutstatus; -} - -/** - * @brief Checks whether the FLASH Prefetch Buffer status is set or not. - * @note This function can be used for all STM32F10x devices. - * @param None - * @retval FLASH Prefetch Buffer Status (SET or RESET). - */ -FlagStatus FLASH_GetPrefetchBufferStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((FLASH->ACR & ACR_PRFTBS_Mask) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Enables or disables the specified FLASH interrupts. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices, enables or disables the specified FLASH interrupts - for Bank1 and Bank2. - * - For other devices it enables or disables the specified FLASH interrupts for Bank1. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_ERROR: FLASH Error Interrupt - * @arg FLASH_IT_EOP: FLASH end of operation Interrupt - * @param NewState: new state of the specified Flash interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ -#ifdef STM32F10X_XL - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if((FLASH_IT & 0x80000000) != 0x0) - { - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF); - } - else - { - /* Disable the interrupt sources */ - FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF); - } - } - else - { - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } - } -#else - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } -#endif /* STM32F10X_XL */ -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices, this function checks whether the specified - * Bank1 or Bank2 flag is set or not. - * - For other devices, it checks whether the specified Bank1 flag is - * set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_BSY: FLASH Busy flag - * @arg FLASH_FLAG_PGERR: FLASH Program error flag - * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPTERR: FLASH Option Byte error flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - -#ifdef STM32F10X_XL - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH_FLAG & 0x80000000) != 0x0) - { - if((FLASH->SR2 & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - } -#else - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)) ; - if(FLASH_FLAG == FLASH_FLAG_OPTERR) - { - if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } - else - { - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - } -#endif /* STM32F10X_XL */ - - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASHs pending flags. - * @note This function can be used for all STM32F10x devices. - * - For STM32F10X_XL devices, this function clears Bank1 or Bank2s pending flags - * - For other devices, it clears Bank1s pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_PGERR: FLASH Program error flag - * @arg FLASH_FLAG_WRPRTERR: FLASH Write protected error flag - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @retval None - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ -#ifdef STM32F10X_XL - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; - - if((FLASH_FLAG & 0x80000000) != 0x0) - { - /* Clear the flags */ - FLASH->SR2 = FLASH_FLAG; - } - else - { - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; - } - -#else - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)) ; - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -#endif /* STM32F10X_XL */ -} - -/** - * @brief Returns the FLASH Status. - * @note This function can be used for all STM32F10x devices, it is equivalent - * to FLASH_GetBank1Status function. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_PGERR) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->SR & FLASH_FLAG_WRPRTERR) != 0 ) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - /* Return the Flash Status */ - return flashstatus; -} - -/** - * @brief Returns the FLASH Bank1 Status. - * @note This function can be used for all STM32F10x devices, it is equivalent - * to FLASH_GetStatus function. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE - */ -FLASH_Status FLASH_GetBank1Status(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_BANK1_PGERR) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->SR & FLASH_FLAG_BANK1_WRPRTERR) != 0 ) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - /* Return the Flash Status */ - return flashstatus; -} - -#ifdef STM32F10X_XL -/** - * @brief Returns the FLASH Bank2 Status. - * @note This function can be used for STM32F10x_XL density devices. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, - * FLASH_ERROR_WRP or FLASH_COMPLETE - */ -FLASH_Status FLASH_GetBank2Status(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0) - { - flashstatus = FLASH_ERROR_PG; - } - else - { - if((FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 ) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - /* Return the Flash Status */ - return flashstatus; -} -#endif /* STM32F10X_XL */ -/** - * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. - * @note This function can be used for all STM32F10x devices, - * it is equivalent to FLASH_WaitForLastBank1Operation. - * - For STM32F10X_XL devices this function waits for a Bank1 Flash operation - * to complete or a TIMEOUT to occur. - * - For all other devices it waits for a Flash operation to complete - * or a TIMEOUT to occur. - * @param Timeout: FLASH progamming Timeout - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the Flash Status */ - status = FLASH_GetBank1Status(); - /* Wait for a Flash operation to complete or a TIMEOUT to occur */ - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} - -/** - * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. - * @note This function can be used for all STM32F10x devices, - * it is equivalent to FLASH_WaitForLastOperation. - * @param Timeout: FLASH progamming Timeout - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the Flash Status */ - status = FLASH_GetBank1Status(); - /* Wait for a Flash operation to complete or a TIMEOUT to occur */ - while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) - { - status = FLASH_GetBank1Status(); - Timeout--; - } - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} - -#ifdef STM32F10X_XL -/** - * @brief Waits for a Flash operation on Bank2 to complete or a TIMEOUT to occur. - * @note This function can be used only for STM32F10x_XL density devices. - * @param Timeout: FLASH progamming Timeout - * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, - * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the Flash Status */ - status = FLASH_GetBank2Status(); - /* Wait for a Flash operation to complete or a TIMEOUT to occur */ - while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00)) - { - status = FLASH_GetBank2Status(); - Timeout--; - } - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} -#endif /* STM32F10X_XL */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_fsmc.c b/example/libs_stm/src/stm32f10x/stm32f10x_fsmc.c deleted file mode 100644 index d04221942..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_fsmc.c +++ /dev/null @@ -1,858 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_fsmc.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the FSMC firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_fsmc.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup FSMC - * @brief FSMC driver modules - * @{ - */ - -/** @defgroup FSMC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup FSMC_Private_Defines - * @{ - */ - -/* --------------------- FSMC registers bit mask ---------------------------- */ - -/* FSMC BCRx Mask */ -#define BCR_MBKEN_Set ((uint32_t)0x00000001) -#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) -#define BCR_FACCEN_Set ((uint32_t)0x00000040) - -/* FSMC PCRx Mask */ -#define PCR_PBKEN_Set ((uint32_t)0x00000004) -#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) -#define PCR_ECCEN_Set ((uint32_t)0x00000040) -#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) -#define PCR_MemoryType_NAND ((uint32_t)0x00000008) -/** - * @} - */ - -/** @defgroup FSMC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup FSMC_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default - * reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @retval None - */ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - - /* FSMC_Bank1_NORSRAM1 */ - if(FSMC_Bank == FSMC_Bank1_NORSRAM1) - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; - } - /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ - else - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; - } - FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; - FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; -} - -/** - * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval None - */ -void FSMC_NANDDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Set the FSMC_Bank2 registers to their reset values */ - FSMC_Bank2->PCR2 = 0x00000018; - FSMC_Bank2->SR2 = 0x00000040; - FSMC_Bank2->PMEM2 = 0xFCFCFCFC; - FSMC_Bank2->PATT2 = 0xFCFCFCFC; - } - /* FSMC_Bank3_NAND */ - else - { - /* Set the FSMC_Bank3 registers to their reset values */ - FSMC_Bank3->PCR3 = 0x00000018; - FSMC_Bank3->SR3 = 0x00000040; - FSMC_Bank3->PMEM3 = 0xFCFCFCFC; - FSMC_Bank3->PATT3 = 0xFCFCFCFC; - } -} - -/** - * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. - * @param None - * @retval None - */ -void FSMC_PCCARDDeInit(void) -{ - /* Set the FSMC_Bank4 registers to their reset values */ - FSMC_Bank4->PCR4 = 0x00000018; - FSMC_Bank4->SR4 = 0x00000000; - FSMC_Bank4->PMEM4 = 0xFCFCFCFC; - FSMC_Bank4->PATT4 = 0xFCFCFCFC; - FSMC_Bank4->PIO4 = 0xFCFCFCFC; -} - -/** - * @brief Initializes the FSMC NOR/SRAM Banks according to the specified - * parameters in the FSMC_NORSRAMInitStruct. - * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef - * structure that contains the configuration information for - * the FSMC NOR/SRAM specified Banks. - * @retval None - */ -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); - assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); - assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); - assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); - assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); - assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); - assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); - assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); - assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); - assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); - assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); - assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); - - /* Bank1 NOR/SRAM control register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | - FSMC_NORSRAMInitStruct->FSMC_MemoryType | - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | - FSMC_NORSRAMInitStruct->FSMC_WrapMode | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | - FSMC_NORSRAMInitStruct->FSMC_WriteOperation | - FSMC_NORSRAMInitStruct->FSMC_WaitSignal | - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | - FSMC_NORSRAMInitStruct->FSMC_WriteBurst; - if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) - { - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; - } - /* Bank1 NOR/SRAM timing register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; - - - /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ - if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) - { - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; - } - else - { - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; - } -} - -/** - * @brief Initializes the FSMC NAND Banks according to the specified - * parameters in the FSMC_NANDInitStruct. - * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef - * structure that contains the configuration information for the FSMC NAND specified Banks. - * @retval None - */ -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - - /* Check the parameters */ - assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); - assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); - assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); - assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); - assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); - assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); - assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ - tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | - PCR_MemoryType_NAND | - FSMC_NANDInitStruct->FSMC_MemoryDataWidth | - FSMC_NANDInitStruct->FSMC_ECC | - FSMC_NANDInitStruct->FSMC_ECCPageSize | - (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| - (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); - - /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ - tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ - tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - /* FSMC_Bank2_NAND registers configuration */ - FSMC_Bank2->PCR2 = tmppcr; - FSMC_Bank2->PMEM2 = tmppmem; - FSMC_Bank2->PATT2 = tmppatt; - } - else - { - /* FSMC_Bank3_NAND registers configuration */ - FSMC_Bank3->PCR3 = tmppcr; - FSMC_Bank3->PMEM3 = tmppmem; - FSMC_Bank3->PATT3 = tmppatt; - } -} - -/** - * @brief Initializes the FSMC PCCARD Bank according to the specified - * parameters in the FSMC_PCCARDInitStruct. - * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef - * structure that contains the configuration information for the FSMC PCCARD Bank. - * @retval None - */ -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); - assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ - FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | - FSMC_MemoryDataWidth_16b | - (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | - (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); - - /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ - FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ - FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ - FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); -} - -/** - * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. - * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Reset NOR/SRAM Init structure parameters values */ - FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; - FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; - FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; -} - -/** - * @brief Fills each FSMC_NANDInitStruct member with its default value. - * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - /* Reset NAND Init structure parameters values */ - FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; - FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; - FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; - FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Fills each FSMC_PCCARDInitStruct member with its default value. - * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef - * structure which will be initialized. - * @retval None - */ -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Reset PCCARD Init structure parameters values */ - FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the specified NOR/SRAM Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; - } - else - { - /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; - } -} - -/** - * @brief Enables or disables the specified NAND Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; - } - else - { - FSMC_Bank3->PCR3 |= PCR_PBKEN_Set; - } - } - else - { - /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; - } - else - { - FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset; - } - } -} - -/** - * @brief Enables or disables the PCCARD Memory Bank. - * @param NewState: new state of the PCCARD Memory Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_PCCARDCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 |= PCR_PBKEN_Set; - } - else - { - /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset; - } -} - -/** - * @brief Enables or disables the FSMC NAND ECC feature. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC NAND ECC feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; - } - else - { - FSMC_Bank3->PCR3 |= PCR_ECCEN_Set; - } - } - else - { - /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; - } - else - { - FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset; - } - } -} - -/** - * @brief Returns the error correction code register value. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval The Error Correction Code (ECC) value. - */ -uint32_t FSMC_GetECC(uint32_t FSMC_Bank) -{ - uint32_t eccval = 0x00000000; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Get the ECCR2 register value */ - eccval = FSMC_Bank2->ECCR2; - } - else - { - /* Get the ECCR3 register value */ - eccval = FSMC_Bank3->ECCR3; - } - /* Return the error correction code value */ - return(eccval); -} - -/** - * @brief Enables or disables the specified FSMC interrupts. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @param NewState: new state of the specified FSMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) -{ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 |= FSMC_IT; - } - } - else - { - /* Disable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - - FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; - } - } -} - -/** - * @brief Checks whether the specified FSMC flag is set or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. - * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. - * @retval The new state of FSMC_FLAG (SET or RESET). - */ -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpsr = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - /* Get the flag status */ - if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the FSMCs pending flags. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising egde detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling egde detection Flag. - * @retval None - */ -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~FSMC_FLAG; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~FSMC_FLAG; - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~FSMC_FLAG; - } -} - -/** - * @brief Checks whether the specified FSMC interrupt has occurred or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt source to check. - * This parameter can be one of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval The new state of FSMC_IT (SET or RESET). - */ -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - itstatus = tmpsr & FSMC_IT; - - itenable = tmpsr & (FSMC_IT >> 3); - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the FSMCs interrupt pending bits. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval None - */ -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_gpio.c b/example/libs_stm/src/stm32f10x/stm32f10x_gpio.c deleted file mode 100644 index 0978e986e..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_gpio.c +++ /dev/null @@ -1,642 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_gpio.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the GPIO firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_gpio.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/** @defgroup GPIO_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_Defines - * @{ - */ - -/* ------------ RCC registers bit address in the alias region ----------------*/ -#define AFIO_OFFSET (AFIO_BASE - PERIPH_BASE) - -/* --- EVENTCR Register -----*/ - -/* Alias word address of EVOE bit */ -#define EVCR_OFFSET (AFIO_OFFSET + 0x00) -#define EVOE_BitNumber ((uint8_t)0x07) -#define EVCR_EVOE_BB (PERIPH_BB_BASE + (EVCR_OFFSET * 32) + (EVOE_BitNumber * 4)) - - -/* --- MAPR Register ---*/ -/* Alias word address of MII_RMII_SEL bit */ -#define MAPR_OFFSET (AFIO_OFFSET + 0x04) -#define MII_RMII_SEL_BitNumber ((u8)0x17) -#define MAPR_MII_RMII_SEL_BB (PERIPH_BB_BASE + (MAPR_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) - - -#define EVCR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) -#define LSB_MASK ((uint16_t)0xFFFF) -#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) -#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) -#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) -#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) -/** - * @} - */ - -/** @defgroup GPIO_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if (GPIOx == GPIOA) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); - } - else if (GPIOx == GPIOB) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); - } - else if (GPIOx == GPIOC) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); - } - else if (GPIOx == GPIOD) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); - } - else if (GPIOx == GPIOE) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); - } - else if (GPIOx == GPIOF) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); - } - else - { - if (GPIOx == GPIOG) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); - } - } -} - -/** - * @brief Deinitializes the Alternate Functions (remap, event control - * and EXTI configuration) registers to their default reset values. - * @param None - * @retval None - */ -void GPIO_AFIODeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified - * parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO peripheral. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; - uint32_t tmpreg = 0x00, pinmask = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - -/*---------------------------- GPIO Mode Configuration -----------------------*/ - currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); - if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) - { - /* Check the parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - /* Output mode */ - currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; - } -/*---------------------------- GPIO CRL Configuration ------------------------*/ - /* Configure the eight low port pins */ - if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) - { - tmpreg = GPIOx->CRL; - for (pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - if (currentpin == pos) - { - pos = pinpos << 2; - /* Clear the corresponding low control register bits */ - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - /* Write the mode configuration in the corresponding bits */ - tmpreg |= (currentmode << pos); - /* Reset the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BRR = (((uint32_t)0x01) << pinpos); - } - else - { - /* Set the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSRR = (((uint32_t)0x01) << pinpos); - } - } - } - } - GPIOx->CRL = tmpreg; - } -/*---------------------------- GPIO CRH Configuration ------------------------*/ - /* Configure the eight high port pins */ - if (GPIO_InitStruct->GPIO_Pin > 0x00FF) - { - tmpreg = GPIOx->CRH; - for (pinpos = 0x00; pinpos < 0x08; pinpos++) - { - pos = (((uint32_t)0x01) << (pinpos + 0x08)); - /* Get the port pins position */ - currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); - if (currentpin == pos) - { - pos = pinpos << 2; - /* Clear the corresponding high control register bits */ - pinmask = ((uint32_t)0x0F) << pos; - tmpreg &= ~pinmask; - /* Write the mode configuration in the corresponding bits */ - tmpreg |= (currentmode << pos); - /* Reset the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) - { - GPIOx->BRR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - /* Set the corresponding ODR bit */ - if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) - { - GPIOx->BSRR = (((uint32_t)0x01) << (pinpos + 0x08)); - } - } - } - GPIOx->CRH = tmpreg; - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; -} - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO input data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval GPIO input data port value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRR = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BRR = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enum values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRR = GPIO_Pin; - } - else - { - GPIOx->BRR = GPIO_Pin; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param PortVal: specifies the value to be written to the port output data register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; -} - -/** - * @brief Selects the GPIO pin used as Event output. - * @param GPIO_PortSource: selects the GPIO port to be used as source - * for Event output. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). - * @param GPIO_PinSource: specifies the pin for the Event output. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @retval None - */ -void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_EVENTOUT_PORT_SOURCE(GPIO_PortSource)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - - tmpreg = AFIO->EVCR; - /* Clear the PORT[6:4] and PIN[3:0] bits */ - tmpreg &= EVCR_PORTPINCONFIG_MASK; - tmpreg |= (uint32_t)GPIO_PortSource << 0x04; - tmpreg |= GPIO_PinSource; - AFIO->EVCR = tmpreg; -} - -/** - * @brief Enables or disables the Event Output. - * @param NewState: new state of the Event output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void GPIO_EventOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) EVCR_EVOE_BB = (uint32_t)NewState; -} - -/** - * @brief Changes the mapping of the specified pin. - * @param GPIO_Remap: selects the pin to remap. - * This parameter can be one of the following values: - * @arg GPIO_Remap_SPI1 - * @arg GPIO_Remap_I2C1 - * @arg GPIO_Remap_USART1 - * @arg GPIO_Remap_USART2 - * @arg GPIO_PartialRemap_USART3 - * @arg GPIO_FullRemap_USART3 - * @arg GPIO_PartialRemap_TIM1 - * @arg GPIO_FullRemap_TIM1 - * @arg GPIO_PartialRemap1_TIM2 - * @arg GPIO_PartialRemap2_TIM2 - * @arg GPIO_FullRemap_TIM2 - * @arg GPIO_PartialRemap_TIM3 - * @arg GPIO_FullRemap_TIM3 - * @arg GPIO_Remap_TIM4 - * @arg GPIO_Remap1_CAN1 - * @arg GPIO_Remap2_CAN1 - * @arg GPIO_Remap_PD01 - * @arg GPIO_Remap_TIM5CH4_LSI - * @arg GPIO_Remap_ADC1_ETRGINJ - * @arg GPIO_Remap_ADC1_ETRGREG - * @arg GPIO_Remap_ADC2_ETRGINJ - * @arg GPIO_Remap_ADC2_ETRGREG - * @arg GPIO_Remap_ETH - * @arg GPIO_Remap_CAN2 - * @arg GPIO_Remap_SWJ_NoJTRST - * @arg GPIO_Remap_SWJ_JTAGDisable - * @arg GPIO_Remap_SWJ_Disable - * @arg GPIO_Remap_SPI3 - * @arg GPIO_Remap_TIM2ITR1_PTP_SOF - * @arg GPIO_Remap_PTP_PPS - * @arg GPIO_Remap_TIM15 - * @arg GPIO_Remap_TIM16 - * @arg GPIO_Remap_TIM17 - * @arg GPIO_Remap_CEC - * @arg GPIO_Remap_TIM1_DMA - * @arg GPIO_Remap_TIM9 - * @arg GPIO_Remap_TIM10 - * @arg GPIO_Remap_TIM11 - * @arg GPIO_Remap_TIM13 - * @arg GPIO_Remap_TIM14 - * @arg GPIO_Remap_FSMC_NADV - * @note If the GPIO_Remap_TIM2ITR1_PTP_SOF is enabled the TIM2 ITR1 is connected - * to Ethernet PTP output. When Reset TIM2 ITR1 is connected to USB OTG SOF output. - * @param NewState: new state of the port pin remapping. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) -{ - uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_REMAP(GPIO_Remap)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - tmpreg = AFIO->MAPR2; - } - else - { - tmpreg = AFIO->MAPR; - } - - tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; - tmp = GPIO_Remap & LSB_MASK; - - if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) - { - tmpreg &= DBGAFR_SWJCFG_MASK; - AFIO->MAPR &= DBGAFR_SWJCFG_MASK; - } - else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) - { - tmp1 = ((uint32_t)0x03) << tmpmask; - tmpreg &= ~tmp1; - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - else - { - tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10)); - tmpreg |= ~DBGAFR_SWJCFG_MASK; - } - - if (NewState != DISABLE) - { - tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10)); - } - - if((GPIO_Remap & 0x80000000) == 0x80000000) - { - AFIO->MAPR2 = tmpreg; - } - else - { - AFIO->MAPR = tmpreg; - } -} - -/** - * @brief Selects the GPIO pin used as EXTI Line. - * @param GPIO_PortSource: selects the GPIO port to be used as source for EXTI lines. - * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). - * @param GPIO_PinSource: specifies the EXTI line to be configured. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @retval None - */ -void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) -{ - uint32_t tmp = 0x00; - /* Check the parameters */ - assert_param(IS_GPIO_EXTI_PORT_SOURCE(GPIO_PortSource)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - - tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); - AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; - AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); -} - -/** - * @brief Selects the Ethernet media interface. - * @note This function applies only to STM32 Connectivity line devices. - * @param GPIO_ETH_MediaInterface: specifies the Media Interface mode. - * This parameter can be one of the following values: - * @arg GPIO_ETH_MediaInterface_MII: MII mode - * @arg GPIO_ETH_MediaInterface_RMII: RMII mode - * @retval None - */ -void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) -{ - assert_param(IS_GPIO_ETH_MEDIA_INTERFACE(GPIO_ETH_MediaInterface)); - - /* Configure MII_RMII selection bit */ - *(__IO uint32_t *) MAPR_MII_RMII_SEL_BB = GPIO_ETH_MediaInterface; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_i2c.c b/example/libs_stm/src/stm32f10x/stm32f10x_i2c.c deleted file mode 100644 index 32545f5ed..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_i2c.c +++ /dev/null @@ -1,1285 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_i2c.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the I2C firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_i2c.h" -#include "stm32f10x_rcc.h" - - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/** @defgroup I2C_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_Defines - * @{ - */ - -/* I2C SPE mask */ -#define CR1_PE_Set ((uint16_t)0x0001) -#define CR1_PE_Reset ((uint16_t)0xFFFE) - -/* I2C START mask */ -#define CR1_START_Set ((uint16_t)0x0100) -#define CR1_START_Reset ((uint16_t)0xFEFF) - -/* I2C STOP mask */ -#define CR1_STOP_Set ((uint16_t)0x0200) -#define CR1_STOP_Reset ((uint16_t)0xFDFF) - -/* I2C ACK mask */ -#define CR1_ACK_Set ((uint16_t)0x0400) -#define CR1_ACK_Reset ((uint16_t)0xFBFF) - -/* I2C ENGC mask */ -#define CR1_ENGC_Set ((uint16_t)0x0040) -#define CR1_ENGC_Reset ((uint16_t)0xFFBF) - -/* I2C SWRST mask */ -#define CR1_SWRST_Set ((uint16_t)0x8000) -#define CR1_SWRST_Reset ((uint16_t)0x7FFF) - -/* I2C PEC mask */ -#define CR1_PEC_Set ((uint16_t)0x1000) -#define CR1_PEC_Reset ((uint16_t)0xEFFF) - -/* I2C ENPEC mask */ -#define CR1_ENPEC_Set ((uint16_t)0x0020) -#define CR1_ENPEC_Reset ((uint16_t)0xFFDF) - -/* I2C ENARP mask */ -#define CR1_ENARP_Set ((uint16_t)0x0010) -#define CR1_ENARP_Reset ((uint16_t)0xFFEF) - -/* I2C NOSTRETCH mask */ -#define CR1_NOSTRETCH_Set ((uint16_t)0x0080) -#define CR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) - -/* I2C registers Masks */ -#define CR1_CLEAR_Mask ((uint16_t)0xFBF5) - -/* I2C DMAEN mask */ -#define CR2_DMAEN_Set ((uint16_t)0x0800) -#define CR2_DMAEN_Reset ((uint16_t)0xF7FF) - -/* I2C LAST mask */ -#define CR2_LAST_Set ((uint16_t)0x1000) -#define CR2_LAST_Reset ((uint16_t)0xEFFF) - -/* I2C FREQ mask */ -#define CR2_FREQ_Reset ((uint16_t)0xFFC0) - -/* I2C ADD0 mask */ -#define OAR1_ADD0_Set ((uint16_t)0x0001) -#define OAR1_ADD0_Reset ((uint16_t)0xFFFE) - -/* I2C ENDUAL mask */ -#define OAR2_ENDUAL_Set ((uint16_t)0x0001) -#define OAR2_ENDUAL_Reset ((uint16_t)0xFFFE) - -/* I2C ADD2 mask */ -#define OAR2_ADD2_Reset ((uint16_t)0xFF01) - -/* I2C F/S mask */ -#define CCR_FS_Set ((uint16_t)0x8000) - -/* I2C CCR mask */ -#define CCR_CCR_Set ((uint16_t)0x0FFF) - -/* I2C FLAG mask */ -#define FLAG_Mask ((uint32_t)0x00FFFFFF) - -/* I2C Interrupt Enable mask */ -#define ITEN_Mask ((uint32_t)0x07000000) - -/** - * @} - */ - -/** @defgroup I2C_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup I2C_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the I2Cx peripheral registers to their default reset values. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval None - */ -void I2C_DeInit(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - if (I2Cx == I2C1) - { - /* Enable I2C1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); - /* Release I2C1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); - } - else - { - /* Enable I2C2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); - /* Release I2C2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); - } -} - -/** - * @brief Initializes the I2Cx peripheral according to the specified - * parameters in the I2C_InitStruct. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that - * contains the configuration information for the specified I2C peripheral. - * @retval None - */ -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct) -{ - uint16_t tmpreg = 0, freqrange = 0; - uint16_t result = 0x04; - uint32_t pclk1 = 8000000; - RCC_ClocksTypeDef rcc_clocks; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->I2C_ClockSpeed)); - assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); - assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); - assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); - assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); - -/*---------------------------- I2Cx CR2 Configuration ------------------------*/ - /* Get the I2Cx CR2 value */ - tmpreg = I2Cx->CR2; - /* Clear frequency FREQ[5:0] bits */ - tmpreg &= CR2_FREQ_Reset; - /* Get pclk1 frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - /* Set frequency bits depending on pclk1 value */ - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - /* Write to I2Cx CR2 */ - I2Cx->CR2 = tmpreg; - -/*---------------------------- I2Cx CCR Configuration ------------------------*/ - /* Disable the selected I2C peripheral to configure TRISE */ - I2Cx->CR1 &= CR1_PE_Reset; - /* Reset tmpreg value */ - /* Clear F/S, DUTY and CCR[11:0] bits */ - tmpreg = 0; - - /* Configure speed in standard mode */ - if (I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - /* Standard mode speed calculate */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - /* Test if CCR value is under 0x4*/ - if (result < 0x04) - { - /* Set minimum allowed value */ - result = 0x04; - } - /* Set speed value for standard mode */ - tmpreg |= result; - /* Set Maximum Rise Time for standard mode */ - I2Cx->TRISE = freqrange + 1; - } - /* Configure speed in fast mode */ - else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ - { - if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - /* Fast mode speed calculate: Tlow/Thigh = 2 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ - { - /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - /* Set DUTY bit */ - result |= I2C_DutyCycle_16_9; - } - - /* Test if CCR value is under 0x1*/ - if ((result & CCR_CCR_Set) == 0) - { - /* Set minimum allowed value */ - result |= (uint16_t)0x0001; - } - /* Set speed value and set F/S bit for fast mode */ - tmpreg |= (uint16_t)(result | CCR_FS_Set); - /* Set Maximum Rise Time for fast mode */ - I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - /* Write to I2Cx CCR */ - I2Cx->CCR = tmpreg; - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= CR1_PE_Set; - -/*---------------------------- I2Cx CR1 Configuration ------------------------*/ - /* Get the I2Cx CR1 value */ - tmpreg = I2Cx->CR1; - /* Clear ACK, SMBTYPE and SMBUS bits */ - tmpreg &= CR1_CLEAR_Mask; - /* Configure I2Cx: mode and acknowledgement */ - /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ - /* Set ACK bit according to I2C_Ack value */ - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - /* Write to I2Cx CR1 */ - I2Cx->CR1 = tmpreg; - -/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ - /* Set I2Cx Own Address1 and acknowledged address */ - I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ -/*---------------- Reset I2C init structure parameters values ----------------*/ - /* initialize the I2C_ClockSpeed member */ - I2C_InitStruct->I2C_ClockSpeed = 5000; - /* Initialize the I2C_Mode member */ - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - /* Initialize the I2C_DutyCycle member */ - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStruct->I2C_OwnAddress1 = 0; - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - /* Initialize the I2C_AcknowledgedAddress member */ - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/** - * @brief Enables or disables the specified I2C peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= CR1_PE_Set; - } - else - { - /* Disable the selected I2C peripheral */ - I2Cx->CR1 &= CR1_PE_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C DMA requests. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C DMA requests */ - I2Cx->CR2 |= CR2_DMAEN_Set; - } - else - { - /* Disable the selected I2C DMA requests */ - I2Cx->CR2 &= CR2_DMAEN_Reset; - } -} - -/** - * @brief Specifies if the next DMA transfer will be the last one. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Next DMA transfer is the last transfer */ - I2Cx->CR2 |= CR2_LAST_Set; - } - else - { - /* Next DMA transfer is not the last transfer */ - I2Cx->CR2 &= CR2_LAST_Reset; - } -} - -/** - * @brief Generates I2Cx communication START condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a START condition */ - I2Cx->CR1 |= CR1_START_Set; - } - else - { - /* Disable the START condition generation */ - I2Cx->CR1 &= CR1_START_Reset; - } -} - -/** - * @brief Generates I2Cx communication STOP condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a STOP condition */ - I2Cx->CR1 |= CR1_STOP_Set; - } - else - { - /* Disable the STOP condition generation */ - I2Cx->CR1 &= CR1_STOP_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C acknowledge feature. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C Acknowledgement. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the acknowledgement */ - I2Cx->CR1 |= CR1_ACK_Set; - } - else - { - /* Disable the acknowledgement */ - I2Cx->CR1 &= CR1_ACK_Reset; - } -} - -/** - * @brief Configures the specified I2C own address2. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the 7bit I2C own address2. - * @retval None. - */ -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Get the old register value */ - tmpreg = I2Cx->OAR2; - - /* Reset I2Cx Own address2 bit [7:1] */ - tmpreg &= OAR2_ADD2_Reset; - - /* Set I2Cx Own address2 */ - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - - /* Store the new register value */ - I2Cx->OAR2 = tmpreg; -} - -/** - * @brief Enables or disables the specified I2C dual addressing mode. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C dual addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable dual addressing mode */ - I2Cx->OAR2 |= OAR2_ENDUAL_Set; - } - else - { - /* Disable dual addressing mode */ - I2Cx->OAR2 &= OAR2_ENDUAL_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C general call feature. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C General call. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable generall call */ - I2Cx->CR1 |= CR1_ENGC_Set; - } - else - { - /* Disable generall call */ - I2Cx->CR1 &= CR1_ENGC_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C interrupts. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_IT_BUF: Buffer interrupt mask - * @arg I2C_IT_EVT: Event interrupt mask - * @arg I2C_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_CONFIG_IT(I2C_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupts */ - I2Cx->CR2 |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupts */ - I2Cx->CR2 &= (uint16_t)~I2C_IT; - } -} - -/** - * @brief Sends a data byte through the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Data: Byte to be transmitted.. - * @retval None - */ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Write in the DR register the data to be sent */ - I2Cx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the data in the DR register */ - return (uint8_t)I2Cx->DR; -} - -/** - * @brief Transmits the address byte to select the slave device. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the slave address which will be transmitted - * @param I2C_Direction: specifies whether the I2C device will be a - * Transmitter or a Receiver. This parameter can be one of the following values - * @arg I2C_Direction_Transmitter: Transmitter mode - * @arg I2C_Direction_Receiver: Receiver mode - * @retval None. - */ -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction != I2C_Direction_Transmitter) - { - /* Set the address bit0 for read */ - Address |= OAR1_ADD0_Set; - } - else - { - /* Reset the address bit0 for write */ - Address &= OAR1_ADD0_Reset; - } - /* Send the address */ - I2Cx->DR = Address; -} - -/** - * @brief Reads the specified I2C register and returns its value. - * @param I2C_Register: specifies the register to read. - * This parameter can be one of the following values: - * @arg I2C_Register_CR1: CR1 register. - * @arg I2C_Register_CR2: CR2 register. - * @arg I2C_Register_OAR1: OAR1 register. - * @arg I2C_Register_OAR2: OAR2 register. - * @arg I2C_Register_DR: DR register. - * @arg I2C_Register_SR1: SR1 register. - * @arg I2C_Register_SR2: SR2 register. - * @arg I2C_Register_CCR: CCR register. - * @arg I2C_Register_TRISE: TRISE register. - * @retval The value of the read register. - */ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_REGISTER(I2C_Register)); - - tmp = (uint32_t) I2Cx; - tmp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Enables or disables the specified I2C software reset. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C software reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Peripheral under reset */ - I2Cx->CR1 |= CR1_SWRST_Set; - } - else - { - /* Peripheral not under reset */ - I2Cx->CR1 &= CR1_SWRST_Reset; - } -} - -/** - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_SMBusAlert: specifies SMBAlert pin level. - * This parameter can be one of the following values: - * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low - * @arg I2C_SMBusAlert_High: SMBAlert pin driven high - * @retval None - */ -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); - if (I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - /* Drive the SMBusAlert pin Low */ - I2Cx->CR1 |= I2C_SMBusAlert_Low; - } - else - { - /* Drive the SMBusAlert pin High */ - I2Cx->CR1 &= I2C_SMBusAlert_High; - } -} - -/** - * @brief Enables or disables the specified I2C PEC transfer. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C PEC transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC transmission */ - I2Cx->CR1 |= CR1_PEC_Set; - } - else - { - /* Disable the selected I2C PEC transmission */ - I2Cx->CR1 &= CR1_PEC_Reset; - } -} - -/** - * @brief Selects the specified I2C PEC position. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_PECPosition: specifies the PEC position. - * This parameter can be one of the following values: - * @arg I2C_PECPosition_Next: indicates that the next byte is PEC - * @arg I2C_PECPosition_Current: indicates that current byte is PEC - * @retval None - */ -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); - if (I2C_PECPosition == I2C_PECPosition_Next) - { - /* Next byte in shift register is PEC */ - I2Cx->CR1 |= I2C_PECPosition_Next; - } - else - { - /* Current byte in shift register is PEC */ - I2Cx->CR1 &= I2C_PECPosition_Current; - } -} - -/** - * @brief Enables or disables the PEC value calculation of the transfered bytes. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC calculation */ - I2Cx->CR1 |= CR1_ENPEC_Set; - } - else - { - /* Disable the selected I2C PEC calculation */ - I2Cx->CR1 &= CR1_ENPEC_Reset; - } -} - -/** - * @brief Returns the PEC value for the specified I2C. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the selected I2C PEC value */ - return ((I2Cx->SR2) >> 8); -} - -/** - * @brief Enables or disables the specified I2C ARP. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx ARP. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C ARP */ - I2Cx->CR1 |= CR1_ENARP_Set; - } - else - { - /* Disable the selected I2C ARP */ - I2Cx->CR1 &= CR1_ENARP_Reset; - } -} - -/** - * @brief Enables or disables the specified I2C Clock stretching. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState == DISABLE) - { - /* Enable the selected I2C Clock stretching */ - I2Cx->CR1 |= CR1_NOSTRETCH_Set; - } - else - { - /* Disable the selected I2C Clock stretching */ - I2Cx->CR1 &= CR1_NOSTRETCH_Reset; - } -} - -/** - * @brief Selects the specified I2C fast mode duty cycle. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_DutyCycle: specifies the fast mode duty cycle. - * This parameter can be one of the following values: - * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 - * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 - * @retval None - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); - if (I2C_DutyCycle != I2C_DutyCycle_16_9) - { - /* I2C fast mode Tlow/Thigh=2 */ - I2Cx->CCR &= I2C_DutyCycle_2; - } - else - { - /* I2C fast mode Tlow/Thigh=16/9 */ - I2Cx->CCR |= I2C_DutyCycle_16_9; - } -} - - - -/** - * @brief - **************************************************************************************** - * - * I2C State Monitoring Functions - * - **************************************************************************************** - * This I2C driver provides three different ways for I2C state monitoring - * depending on the application requirements and constraints: - * - * - * 1) Basic state monitoring: - * Using I2C_CheckEvent() function: - * It compares the status registers (SR1 and SR2) content to a given event - * (can be the combination of one or more flags). - * It returns SUCCESS if the current status includes the given flags - * and returns ERROR if one or more flags are missing in the current status. - * - When to use: - * - This function is suitable for most applciations as well as for startup - * activity since the events are fully described in the product reference manual - * (RM0008). - * - It is also suitable for users who need to define their own events. - * - Limitations: - * - If an error occurs (ie. error flags are set besides to the monitored flags), - * the I2C_CheckEvent() function may return SUCCESS despite the communication - * hold or corrupted real state. - * In this case, it is advised to use error interrupts to monitor the error - * events and handle them in the interrupt IRQ handler. - * - * @note - * For error management, it is advised to use the following functions: - * - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - * - I2Cx_ER_IRQHandler() which is called when the error interurpt occurs. - * Where x is the peripheral instance (I2C1, I2C2 ...) - * - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into I2Cx_ER_IRQHandler() - * in order to determine which error occured. - * - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - * and/or I2C_GenerateStop() in order to clear the error flag and source, - * and return to correct communication status. - * - * - * 2) Advanced state monitoring: - * Using the function I2C_GetLastEvent() which returns the image of both status - * registers in a single word (uint32_t) (Status Register 2 value is shifted left - * by 16 bits and concatenated to Status Register 1). - * - When to use: - * - This function is suitable for the same applications above but it allows to - * overcome the mentionned limitation of I2C_GetFlagStatus() function. - * The returned value could be compared to events already defined in the - * library (stm32f10x_i2c.h) or to custom values defiend by user. - * - This function is suitable when multiple flags are monitored at the same time. - * - At the opposite of I2C_CheckEvent() function, this function allows user to - * choose when an event is accepted (when all events flags are set and no - * other flags are set or just when the needed flags are set like - * I2C_CheckEvent() function). - * - Limitations: - * - User may need to define his own events. - * - Same remark concerning the error management is applicable for this - * function if user decides to check only regular communication flags (and - * ignores error flags). - * - * - * 3) Flag-based state monitoring: - * Using the function I2C_GetFlagStatus() which simply returns the status of - * one single flag (ie. I2C_FLAG_RXNE ...). - * - When to use: - * - This function could be used for specific applications or in debug phase. - * - It is suitable when only one flag checking is needed (most I2C events - * are monitored through multiple flags). - * - Limitations: - * - When calling this function, the Status register is accessed. Some flags are - * cleared when the status register is accessed. So checking the status - * of one Flag, may clear other ones. - * - Function may need to be called twice or more in order to monitor one - * single event. - * - * For detailed description of Events, please refer to section I2C_Events in - * stm32f10x_i2c.h file. - * - */ - -/** - * - * 1) Basic state monitoring - ******************************************************************************* - */ - -/** - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_EVENT: specifies the event to be checked. - * This parameter can be one of the following values: - * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2 - * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3 - * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2 - * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 - * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 - * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 - * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6 - * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2 - * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 - * - * @note: For detailed description of Events, please refer to section - * I2C_Events in stm32f10x_i2c.h file. - * - * @retval An ErrorStatus enumuration value: - * - SUCCESS: Last event is equal to the I2C_EVENT - * - ERROR: Last event is different from the I2C_EVENT - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_EVENT(I2C_EVENT)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_Mask; - - /* Check whether the last event contains the I2C_EVENT */ - if ((lastevent & I2C_EVENT) == I2C_EVENT) - { - /* SUCCESS: last event is equal to I2C_EVENT */ - status = SUCCESS; - } - else - { - /* ERROR: last event is different from I2C_EVENT */ - status = ERROR; - } - /* Return status */ - return status; -} - -/** - * - * 2) Advanced state monitoring - ******************************************************************************* - */ - -/** - * @brief Returns the last I2Cx Event. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * - * @note: For detailed description of Events, please refer to section - * I2C_Events in stm32f10x_i2c.h file. - * - * @retval The last event - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_Mask; - - /* Return status */ - return lastevent; -} - -/** - * - * 3) Flag-based state monitoring - ******************************************************************************* - */ - -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) - * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) - * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) - * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) - * @arg I2C_FLAG_TRA: Transmitter/Receiver flag - * @arg I2C_FLAG_BUSY: Bus busy flag - * @arg I2C_FLAG_MSL: Master/Slave flag - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) - * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag - * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) - * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) ADSL - * Address matched flag (Slave mode)ENDAD - * @arg I2C_FLAG_SB: Start bit flag (Master mode) - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - /* Get the I2Cx peripheral base address */ - i2cxbase = (uint32_t)I2Cx; - - /* Read flag register index */ - i2creg = I2C_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - I2C_FLAG &= FLAG_Mask; - - if(i2creg != 0) - { - /* Get the I2Cx SR1 register address */ - i2cxbase += 0x14; - } - else - { - /* Flag in I2Cx SR2 Register */ - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - /* Get the I2Cx SR2 register address */ - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - /* I2C_FLAG is set */ - bitstatus = SET; - } - else - { - /* I2C_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the I2C_FLAG status */ - return bitstatus; -} - - - -/** - * @brief Clears the I2Cx's pending flags. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * - * @note - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR - * register (I2C_SendData()). - * @retval None - */ -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); - /* Get the I2C flag position */ - flagpos = I2C_FLAG & FLAG_Mask; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @brief Checks whether the specified I2C interrupt has occurred or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert flag - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_IT_PECERR: PEC error in reception flag - * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure flag - * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_IT_BERR: Bus error flag - * @arg I2C_IT_TXE: Data register empty flag (Transmitter) - * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag - * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) - * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_IT_BTF: Byte transfer finished flag - * @arg I2C_IT_ADDR: Address sent flag (Master mode) ADSL - * Address matched flag (Slave mode)ENDAD - * @arg I2C_IT_SB: Start bit flag (Master mode) - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_IT(I2C_IT)); - - /* Check if the interrupt source is enabled or not */ - enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CR2)) ; - - /* Get bit[23:0] of the flag */ - I2C_IT &= FLAG_Mask; - - /* Check the status of the specified I2C flag */ - if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - /* I2C_IT is set */ - bitstatus = SET; - } - else - { - /* I2C_IT is reset */ - bitstatus = RESET; - } - /* Return the I2C_IT status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cxs interrupt pending bits. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert interrupt - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt - * @arg I2C_IT_PECERR: PEC error in reception interrupt - * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure interrupt - * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) - * @arg I2C_IT_BERR: Bus error interrupt - * - * @note - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DR register (I2C_SendData()). - * @retval None - */ -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_IT(I2C_IT)); - /* Get the I2C flag position */ - flagpos = I2C_IT & FLAG_Mask; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_iwdg.c b/example/libs_stm/src/stm32f10x/stm32f10x_iwdg.c deleted file mode 100644 index 58ab061c3..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_iwdg.c +++ /dev/null @@ -1,189 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_iwdg.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the IWDG firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_iwdg.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup IWDG - * @brief IWDG driver modules - * @{ - */ - -/** @defgroup IWDG_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_Defines - * @{ - */ - -/* ---------------------- IWDG registers bit mask ----------------------------*/ - -/* KR register bit mask */ -#define KR_KEY_Reload ((uint16_t)0xAAAA) -#define KR_KEY_Enable ((uint16_t)0xCCCC) - -/** - * @} - */ - -/** @defgroup IWDG_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup IWDG_Private_Functions - * @{ - */ - -/** - * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. - * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. - * This parameter can be one of the following values: - * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers - * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers - * @retval None - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); - IWDG->KR = IWDG_WriteAccess; -} - -/** - * @brief Sets IWDG Prescaler value. - * @param IWDG_Prescaler: specifies the IWDG Prescaler value. - * This parameter can be one of the following values: - * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 - * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 - * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 - * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 - * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 - * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 - * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 - * @retval None - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); - IWDG->PR = IWDG_Prescaler; -} - -/** - * @brief Sets IWDG Reload value. - * @param Reload: specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * @retval None - */ -void IWDG_SetReload(uint16_t Reload) -{ - /* Check the parameters */ - assert_param(IS_IWDG_RELOAD(Reload)); - IWDG->RLR = Reload; -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_ReloadCounter(void) -{ - IWDG->KR = KR_KEY_Reload; -} - -/** - * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_Enable(void) -{ - IWDG->KR = KR_KEY_Enable; -} - -/** - * @brief Checks whether the specified IWDG flag is set or not. - * @param IWDG_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Prescaler Value Update on going - * @arg IWDG_FLAG_RVU: Reload Value Update on going - * @retval The new state of IWDG_FLAG (SET or RESET). - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_IWDG_FLAG(IWDG_FLAG)); - if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_pwr.c b/example/libs_stm/src/stm32f10x/stm32f10x_pwr.c deleted file mode 100644 index a017ac681..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_pwr.c +++ /dev/null @@ -1,316 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_pwr.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the PWR firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_pwr.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup PWR - * @brief PWR driver modules - * @{ - */ - -/** @defgroup PWR_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_Defines - * @{ - */ - -/* --------- PWR registers bit address in the alias region ---------- */ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of DBP bit */ -#define CR_OFFSET (PWR_OFFSET + 0x00) -#define DBP_BitNumber 0x08 -#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) - -/* Alias word address of PVDE bit */ -#define PVDE_BitNumber 0x04 -#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of EWUP bit */ -#define CSR_OFFSET (PWR_OFFSET + 0x04) -#define EWUP_BitNumber 0x08 -#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) - -/* ------------------ PWR registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_PDDS_Set ((uint32_t)0x00000002) -#define CR_DS_Mask ((uint32_t)0xFFFFFFFC) -#define CR_CWUF_Set ((uint32_t)0x00000004) -#define CR_PLS_Mask ((uint32_t)0xFFFFFF1F) - -/* --------- Cortex System Control register bit mask ---------------- */ - -/* Cortex System Control register address */ -#define SCB_SysCtrl ((uint32_t)0xE000ED10) - -/* SLEEPDEEP bit mask */ -#define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004) -#define SysCtrl_SLEEPDEEP_Reset ((uint32_t)0xFFFFFFFB) - -/** - * @} - */ - -/** @defgroup PWR_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/** - * @brief Enables or disables access to the RTC and backup registers. - * @param NewState: new state of the access to the RTC and backup registers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Power Voltage Detector(PVD). - * @param NewState: new state of the PVD. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param PWR_PVDLevel: specifies the PVD detection level - * This parameter can be one of the following values: - * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V - * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V - * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V - * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V - * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V - * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V - * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V - * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V - * @retval None - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); - tmpreg = PWR->CR; - /* Clear PLS[7:5] bits */ - tmpreg &= CR_PLS_Mask; - /* Set PLS[7:5] bits according to PWR_PVDLevel value */ - tmpreg |= PWR_PVDLevel; - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; -} - -/** - * @brief Enters STOP mode. - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_Regulator_ON: STOP mode with regulator ON - * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDS bits */ - tmpreg &= CR_DS_Mask; - /* Set LPDS bit according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - /* Store the new value */ - PWR->CR = tmpreg; - /* Set SLEEPDEEP bit of Cortex System Control Register */ - *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - *(__IO uint32_t *) SCB_SysCtrl &= SysCtrl_SLEEPDEEP_Reset; -} - -/** - * @brief Enters STANDBY mode. - * @param None - * @retval None - */ -void PWR_EnterSTANDBYMode(void) -{ - /* Clear Wake-up flag */ - PWR->CR |= CR_CWUF_Set; - /* Select STANDBY mode */ - PWR->CR |= CR_PDDS_Set; - /* Set SLEEPDEEP bit of Cortex System Control Register */ - *(__IO uint32_t *) SCB_SysCtrl |= SysCtrl_SLEEPDEEP_Set; -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM ) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @arg PWR_FLAG_PVDO: PVD Output - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the PWR's pending flags. - * @param PWR_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @retval None - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - - PWR->CR |= PWR_FLAG << 2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_rcc.c b/example/libs_stm/src/stm32f10x/stm32f10x_rcc.c deleted file mode 100644 index 0fb0d58a0..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_rcc.c +++ /dev/null @@ -1,1477 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rcc.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the RCC firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/** @defgroup RCC_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Defines - * @{ - */ - -/* ------------ RCC registers bit address in the alias region ----------- */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of HSION bit */ -#define CR_OFFSET (RCC_OFFSET + 0x00) -#define HSION_BitNumber 0x00 -#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) - -/* Alias word address of PLLON bit */ -#define PLLON_BitNumber 0x18 -#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) - -#ifdef STM32F10X_CL - /* Alias word address of PLL2ON bit */ - #define PLL2ON_BitNumber 0x1A - #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4)) - - /* Alias word address of PLL3ON bit */ - #define PLL3ON_BitNumber 0x1C - #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* Alias word address of CSSON bit */ -#define CSSON_BitNumber 0x13 -#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) - -/* --- CFGR Register ---*/ - -/* Alias word address of USBPRE bit */ -#define CFGR_OFFSET (RCC_OFFSET + 0x04) - -#ifndef STM32F10X_CL - #define USBPRE_BitNumber 0x16 - #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) -#else - #define OTGFSPRE_BitNumber 0x16 - #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* --- BDCR Register ---*/ - -/* Alias word address of RTCEN bit */ -#define BDCR_OFFSET (RCC_OFFSET + 0x20) -#define RTCEN_BitNumber 0x0F -#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) - -/* Alias word address of BDRST bit */ -#define BDRST_BitNumber 0x10 -#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of LSION bit */ -#define CSR_OFFSET (RCC_OFFSET + 0x24) -#define LSION_BitNumber 0x00 -#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) - -#ifdef STM32F10X_CL -/* --- CFGR2 Register ---*/ - - /* Alias word address of I2S2SRC bit */ - #define CFGR2_OFFSET (RCC_OFFSET + 0x2C) - #define I2S2SRC_BitNumber 0x11 - #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4)) - - /* Alias word address of I2S3SRC bit */ - #define I2S3SRC_BitNumber 0x12 - #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4)) -#endif /* STM32F10X_CL */ - -/* ---------------------- RCC registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) -#define CR_HSEBYP_Set ((uint32_t)0x00040000) -#define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) -#define CR_HSEON_Set ((uint32_t)0x00010000) -#define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) - -/* CFGR register bit mask */ -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) - #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF) -#else - #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) -#endif /* STM32F10X_CL */ - -#define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) -#define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) -#define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) -#define CFGR_SWS_Mask ((uint32_t)0x0000000C) -#define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) -#define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) -#define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) -#define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) -#define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) -#define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) -#define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) -#define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) -#define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) - -/* CSR register bit mask */ -#define CSR_RMVF_Set ((uint32_t)0x01000000) - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) -/* CFGR2 register bit mask */ - #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) - #define CFGR2_PREDIV1 ((uint32_t)0x0000000F) -#endif -#ifdef STM32F10X_CL - #define CFGR2_PREDIV2 ((uint32_t)0x000000F0) - #define CFGR2_PLL2MUL ((uint32_t)0x00000F00) - #define CFGR2_PLL3MUL ((uint32_t)0x0000F000) -#endif /* STM32F10X_CL */ - -/* RCC Flag Mask */ -#define FLAG_Mask ((uint8_t)0x1F) - -#ifndef HSI_Value -/* Typical Value of the HSI in Hz */ - #define HSI_Value ((uint32_t)8000000) -#endif /* HSI_Value */ - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) - -/* CFGR register byte 4 (Bits[31:24]) base address */ -#define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) - -/* BDCR register base address */ -#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) - -#ifndef HSEStartUp_TimeOut -/* Time out for HSE start up */ - #define HSEStartUp_TimeOut ((uint16_t)0x0500) -#endif /* HSEStartUp_TimeOut */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Variables - * @{ - */ - -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; - -/** - * @} - */ - -/** @defgroup RCC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#ifndef STM32F10X_CL - RCC->CFGR &= (uint32_t)0xF8FF0000; -#else - RCC->CFGR &= (uint32_t)0xF0FF0000; -#endif /* STM32F10X_CL */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; - -#ifdef STM32F10X_CL - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEBFFFFFF; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#else - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; -#endif /* STM32F10X_CL */ - -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note HSE can not be stopped if it is used directly or through the PLL as system clock. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: HSE oscillator OFF - * @arg RCC_HSE_ON: HSE oscillator ON - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint32_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - /* Reset HSEON bit */ - RCC->CR &= CR_HSEON_Reset; - /* Reset HSEBYP bit */ - RCC->CR &= CR_HSEBYP_Reset; - /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */ - switch(RCC_HSE) - { - case RCC_HSE_ON: - /* Set HSEON bit */ - RCC->CR |= CR_HSEON_Set; - break; - - case RCC_HSE_Bypass: - /* Set HSEBYP and HSEON bits */ - RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set; - break; - - default: - break; - } -} - -/** - * @brief Waits for HSE start-up. - * @param None - * @retval An ErrorStatus enumuration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - ErrorStatus status = ERROR; - FlagStatus HSEStatus = RESET; - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSEStartUp_TimeOut) && (HSEStatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @param HSICalibrationValue: specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); - tmpreg = RCC->CR; - /* Clear HSITRIM[4:0] bits */ - tmpreg &= CR_HSITRIM_Mask; - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note HSI can not be stopped if it is used directly or through the PLL as system clock. - * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the PLL clock source and multiplication factor. - * @note This function must be used only when the PLL is disabled. - * @param RCC_PLLSource: specifies the PLL entry clock source. - * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices, - * this parameter can be one of the following values: - * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry - * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry - * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry - * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry - * @param RCC_PLLMul: specifies the PLL multiplication factor. - * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5} - * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16] - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); - - tmpreg = RCC->CFGR; - /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ - tmpreg &= CFGR_PLL_Mask; - /* Set the PLL configuration bits */ - tmpreg |= RCC_PLLSource | RCC_PLLMul; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Enables or disables the PLL. - * @note The PLL can not be disabled if it is used as system clock. - * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; -} - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_CL) -/** - * @brief Configures the PREDIV1 division factor. - * @note - * - This function must be used only when the PLL is disabled. - * - This function applies only to STM32 Connectivity line and Value line - * devices. - * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source. - * This parameter can be one of the following values: - * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock - * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock - * @note - * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE - * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor. - * This parameter can be RCC_PREDIV1_Divx where x:[1,16] - * @retval None - */ -void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source)); - assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div)); - - tmpreg = RCC->CFGR2; - /* Clear PREDIV1[3:0] and PREDIV1SRC bits */ - tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); - /* Set the PREDIV1 clock source and division factor */ - tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} -#endif - -#ifdef STM32F10X_CL -/** - * @brief Configures the PREDIV2 division factor. - * @note - * - This function must be used only when both PLL2 and PLL3 are disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor. - * This parameter can be RCC_PREDIV2_Divx where x:[1,16] - * @retval None - */ -void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div)); - - tmpreg = RCC->CFGR2; - /* Clear PREDIV2[3:0] bits */ - tmpreg &= ~CFGR2_PREDIV2; - /* Set the PREDIV2 division factor */ - tmpreg |= RCC_PREDIV2_Div; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - -/** - * @brief Configures the PLL2 multiplication factor. - * @note - * - This function must be used only when the PLL2 is disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor. - * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20} - * @retval None - */ -void RCC_PLL2Config(uint32_t RCC_PLL2Mul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul)); - - tmpreg = RCC->CFGR2; - /* Clear PLL2Mul[3:0] bits */ - tmpreg &= ~CFGR2_PLL2MUL; - /* Set the PLL2 configuration bits */ - tmpreg |= RCC_PLL2Mul; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - - -/** - * @brief Enables or disables the PLL2. - * @note - * - The PLL2 can not be disabled if it is used indirectly as system clock - * (i.e. it is used as PLL clock entry that is used as System clock). - * - This function applies only to STM32 Connectivity line devices. - * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLL2Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState; -} - - -/** - * @brief Configures the PLL3 multiplication factor. - * @note - * - This function must be used only when the PLL3 is disabled. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor. - * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20} - * @retval None - */ -void RCC_PLL3Config(uint32_t RCC_PLL3Mul) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul)); - - tmpreg = RCC->CFGR2; - /* Clear PLL3Mul[3:0] bits */ - tmpreg &= ~CFGR2_PLL3MUL; - /* Set the PLL3 configuration bits */ - tmpreg |= RCC_PLL3Mul; - /* Store the new value */ - RCC->CFGR2 = tmpreg; -} - - -/** - * @brief Enables or disables the PLL3. - * @note This function applies only to STM32 Connectivity line devices. - * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLL3Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the system clock (SYSCLK). - * @param RCC_SYSCLKSource: specifies the clock source used as system clock. - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - tmpreg = RCC->CFGR; - /* Clear SW[1:0] bits */ - tmpreg &= CFGR_SW_Mask; - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can - * be one of the following: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - tmpreg = RCC->CFGR; - /* Clear HPRE[3:0] bits */ - tmpreg &= CFGR_HPRE_Reset_Mask; - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB1 clock = HCLK - * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - tmpreg = RCC->CFGR; - /* Clear PPRE1[2:0] bits */ - tmpreg &= CFGR_PPRE1_Reset_Mask; - /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB2 clock = HCLK - * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - tmpreg = RCC->CFGR; - /* Clear PPRE2[2:0] bits */ - tmpreg &= CFGR_PPRE2_Reset_Mask; - /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK << 3; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Enables or disables the specified RCC interrupts. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -#ifndef STM32F10X_CL -/** - * @brief Configures the USB clock (USBCLK). - * @param RCC_USBCLKSource: specifies the USB clock source. This clock is - * derived from the PLL output. - * This parameter can be one of the following values: - * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB - * clock source - * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source - * @retval None - */ -void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource)); - - *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource; -} -#else -/** - * @brief Configures the USB OTG FS clock (OTGFSCLK). - * This function applies only to STM32 Connectivity line devices. - * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source. - * This clock is derived from the PLL output. - * This parameter can be one of the following values: - * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source - * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source - * @retval None - */ -void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource)); - - *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the ADC clock (ADCCLK). - * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from - * the APB2 clock (PCLK2). - * This parameter can be one of the following values: - * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2 - * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4 - * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6 - * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8 - * @retval None - */ -void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_ADCCLK(RCC_PCLK2)); - tmpreg = RCC->CFGR; - /* Clear ADCPRE[1:0] bits */ - tmpreg &= CFGR_ADCPRE_Reset_Mask; - /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */ - tmpreg |= RCC_PCLK2; - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -#ifdef STM32F10X_CL -/** - * @brief Configures the I2S2 clock source(I2S2CLK). - * @note - * - This function must be called before enabling I2S2 APB clock. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_I2S2CLKSource: specifies the I2S2 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry - * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry - * @retval None - */ -void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource)); - - *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource; -} - -/** - * @brief Configures the I2S3 clock source(I2S2CLK). - * @note - * - This function must be called before enabling I2S3 APB clock. - * - This function applies only to STM32 Connectivity line devices. - * @param RCC_I2S3CLKSource: specifies the I2S3 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry - * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry - * @retval None - */ -void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource)); - - *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource; -} -#endif /* STM32F10X_CL */ - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: LSE oscillator OFF - * @arg RCC_LSE_ON: LSE oscillator ON - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - /* Reset LSEBYP bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ - switch(RCC_LSE) - { - case RCC_LSE_ON: - /* Set LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; - break; - - case RCC_LSE_Bypass: - /* Set LSEBYP and LSEON bits */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - - default: - break; - } -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note Once the RTC clock is selected it cant be changed unless the Backup domain is reset. - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - /* Select the RTC clock source */ - RCC->BDCR |= RCC_RTCCLKSource; -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; -} - -/** - * @brief Returns the frequencies of different on chip clocks. - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; - -#ifdef STM32F10X_CL - uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) - uint32_t prediv1factor = 0; -#endif - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & CFGR_SWS_Mask; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSI_Value; - break; - case 0x04: /* HSE used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSE_Value; - break; - case 0x08: /* PLL used as system clock */ - - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & CFGR_PLLMull_Mask; - pllsource = RCC->CFGR & CFGR_PLLSRC_Mask; - -#ifndef STM32F10X_CL - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull; - } - else - { - #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) - prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull; - #else - /* HSE selected as PLL clock entry */ - if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET) - {/* HSE oscillator clock divided by 2 */ - RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull; - } - else - { - RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull; - } - #endif - } -#else - pllmull = pllmull >> 18; - - if (pllmull != 0x0D) - { - pllmull += 2; - } - else - { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; - } - - if (pllsource == 0x00) - {/* HSI oscillator clock divided by 2 selected as PLL clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull; - } - else - {/* PREDIV1 selected as PLL clock entry */ - - /* Get PREDIV1 clock source and division factor */ - prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1; - - if (prediv1source == 0) - { /* HSE oscillator clock selected as PREDIV1 clock entry */ - RCC_Clocks->SYSCLK_Frequency = (HSE_Value / prediv1factor) * pllmull; - } - else - {/* PLL2 clock selected as PREDIV1 clock entry */ - - /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; - RCC_Clocks->SYSCLK_Frequency = (((HSE_Value / prediv2factor) * pll2mull) / prediv1factor) * pllmull; - } - } -#endif /* STM32F10X_CL */ - break; - - default: - RCC_Clocks->SYSCLK_Frequency = HSI_Value; - break; - } - - /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ - /* Get HCLK prescaler */ - tmp = RCC->CFGR & CFGR_HPRE_Set_Mask; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - /* Get PCLK1 prescaler */ - tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask; - tmp = tmp >> 8; - presc = APBAHBPrescTable[tmp]; - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - /* Get PCLK2 prescaler */ - tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask; - tmp = tmp >> 11; - presc = APBAHBPrescTable[tmp]; - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - /* Get ADCCLK prescaler */ - tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask; - tmp = tmp >> 14; - presc = ADCPrescTable[tmp]; - /* ADCCLK clock frequency */ - RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; -} - -/** - * @brief Enables or disables the AHB peripheral clock. - * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values: - * @arg RCC_AHBPeriph_DMA1 - * @arg RCC_AHBPeriph_DMA2 - * @arg RCC_AHBPeriph_SRAM - * @arg RCC_AHBPeriph_FLITF - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_OTG_FS - * @arg RCC_AHBPeriph_ETH_MAC - * @arg RCC_AHBPeriph_ETH_MAC_Tx - * @arg RCC_AHBPeriph_ETH_MAC_Rx - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values: - * @arg RCC_AHBPeriph_DMA1 - * @arg RCC_AHBPeriph_DMA2 - * @arg RCC_AHBPeriph_SRAM - * @arg RCC_AHBPeriph_FLITF - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_FSMC - * @arg RCC_AHBPeriph_SDIO - * - * @note SRAM and FLITF clock can be disabled only during sleep mode. - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBENR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, - * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, - * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, - * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, - * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, - * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, - * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, - * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, - * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, - * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, - * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, - * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, - * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, - * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -#ifdef STM32F10X_CL -/** - * @brief Forces or releases AHB peripheral reset. - * @note This function applies only to STM32 Connectivity line devices. - * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_OTG_FS - * @arg RCC_AHBPeriph_ETH_MAC - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBRSTR |= RCC_AHBPeriph; - } - else - { - RCC->AHBRSTR &= ~RCC_AHBPeriph; - } -} -#endif /* STM32F10X_CL */ - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, - * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, - * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, - * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, - * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, - * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, - * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11 - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, - * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, - * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, - * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, - * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, - * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, - * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, - * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases the Backup domain reset. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Clock Security System. - * @param NewState: new state of the Clock Security System.. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the clock source to output on MCO pin. - * @param RCC_MCO: specifies the clock source to output. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_MCO_NoClock: No clock selected - * @arg RCC_MCO_SYSCLK: System clock selected - * @arg RCC_MCO_HSI: HSI oscillator clock selected - * @arg RCC_MCO_HSE: HSE oscillator clock selected - * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected - * @arg RCC_MCO_PLL2CLK: PLL2 clock selected - * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected - * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected - * @arg RCC_MCO_PLL3CLK: PLL3 clock selected - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_MCO_NoClock: No clock selected - * @arg RCC_MCO_SYSCLK: System clock selected - * @arg RCC_MCO_HSI: HSI oscillator clock selected - * @arg RCC_MCO_HSE: HSE oscillator clock selected - * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected - * - * @retval None - */ -void RCC_MCOConfig(uint8_t RCC_MCO) -{ - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCO)); - - /* Perform Byte access to MCO bits to select the MCO source */ - *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO; -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready - * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - if (tmp == 1) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 2) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_Mask; - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= CSR_RMVF_Set; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * - * For @b STM32_Connectivity_line_devices, this parameter can be one of the - * following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * For @b other_STM32_devices, this parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCCs interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * - * For @b STM32_Connectivity_line_devices, this parameter can be any combination - * of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt - * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * - * For @b other_STM32_devices, this parameter can be any combination of the - * following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_rtc.c b/example/libs_stm/src/stm32f10x/stm32f10x_rtc.c deleted file mode 100644 index 2720124bd..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_rtc.c +++ /dev/null @@ -1,341 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_rtc.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the RTC firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_rtc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup RTC - * @brief RTC driver modules - * @{ - */ - -/** @defgroup RTC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup RTC_Private_Defines - * @{ - */ - -#define CRL_CNF_Set ((uint16_t)0x0010) /*!< Configuration Flag Enable Mask */ -#define CRL_CNF_Reset ((uint16_t)0xFFEF) /*!< Configuration Flag Disable Mask */ -#define RTC_LSB_Mask ((uint32_t)0x0000FFFF) /*!< RTC LSB Mask */ -#define PRLH_MSB_Mask ((uint32_t)0x000F0000) /*!< RTC Prescaler MSB Mask */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup RTC_Private_Functions - * @{ - */ - -/** - * @brief Enables or disables the specified RTC interrupts. - * @param RTC_IT: specifies the RTC interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_OW: Overflow interrupt - * @arg RTC_IT_ALR: Alarm interrupt - * @arg RTC_IT_SEC: Second interrupt - * @param NewState: new state of the specified RTC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_IT(RTC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RTC->CRH |= RTC_IT; - } - else - { - RTC->CRH &= (uint16_t)~RTC_IT; - } -} - -/** - * @brief Enters the RTC configuration mode. - * @param None - * @retval None - */ -void RTC_EnterConfigMode(void) -{ - /* Set the CNF flag to enter in the Configuration Mode */ - RTC->CRL |= CRL_CNF_Set; -} - -/** - * @brief Exits from the RTC configuration mode. - * @param None - * @retval None - */ -void RTC_ExitConfigMode(void) -{ - /* Reset the CNF flag to exit from the Configuration Mode */ - RTC->CRL &= CRL_CNF_Reset; -} - -/** - * @brief Gets the RTC counter value. - * @param None - * @retval RTC counter value. - */ -uint32_t RTC_GetCounter(void) -{ - uint16_t tmp = 0; - tmp = RTC->CNTL; - return (((uint32_t)RTC->CNTH << 16 ) | tmp) ; -} - -/** - * @brief Sets the RTC counter value. - * @param CounterValue: RTC counter new value. - * @retval None - */ -void RTC_SetCounter(uint32_t CounterValue) -{ - RTC_EnterConfigMode(); - /* Set RTC COUNTER MSB word */ - RTC->CNTH = CounterValue >> 16; - /* Set RTC COUNTER LSB word */ - RTC->CNTL = (CounterValue & RTC_LSB_Mask); - RTC_ExitConfigMode(); -} - -/** - * @brief Sets the RTC prescaler value. - * @param PrescalerValue: RTC prescaler new value. - * @retval None - */ -void RTC_SetPrescaler(uint32_t PrescalerValue) -{ - /* Check the parameters */ - assert_param(IS_RTC_PRESCALER(PrescalerValue)); - - RTC_EnterConfigMode(); - /* Set RTC PRESCALER MSB word */ - RTC->PRLH = (PrescalerValue & PRLH_MSB_Mask) >> 16; - /* Set RTC PRESCALER LSB word */ - RTC->PRLL = (PrescalerValue & RTC_LSB_Mask); - RTC_ExitConfigMode(); -} - -/** - * @brief Sets the RTC alarm value. - * @param AlarmValue: RTC alarm new value. - * @retval None - */ -void RTC_SetAlarm(uint32_t AlarmValue) -{ - RTC_EnterConfigMode(); - /* Set the ALARM MSB word */ - RTC->ALRH = AlarmValue >> 16; - /* Set the ALARM LSB word */ - RTC->ALRL = (AlarmValue & RTC_LSB_Mask); - RTC_ExitConfigMode(); -} - -/** - * @brief Gets the RTC divider value. - * @param None - * @retval RTC Divider value. - */ -uint32_t RTC_GetDivider(void) -{ - uint32_t tmp = 0x00; - tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; - tmp |= RTC->DIVL; - return tmp; -} - -/** - * @brief Waits until last write operation on RTC registers has finished. - * @note This function must be called before any write to RTC registers. - * @param None - * @retval None - */ -void RTC_WaitForLastTask(void) -{ - /* Loop until RTOFF flag is set */ - while ((RTC->CRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) - { - } -} - -/** - * @brief Waits until the RTC registers (RTC_CNT, RTC_ALR and RTC_PRL) - * are synchronized with RTC APB clock. - * @note This function must be called before any read operation after an APB reset - * or an APB clock stop. - * @param None - * @retval None - */ -void RTC_WaitForSynchro(void) -{ - /* Clear RSF flag */ - RTC->CRL &= (uint16_t)~RTC_FLAG_RSF; - /* Loop until RSF flag is set */ - while ((RTC->CRL & RTC_FLAG_RSF) == (uint16_t)RESET) - { - } -} - -/** - * @brief Checks whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifies the flag to check. - * This parameter can be one the following values: - * @arg RTC_FLAG_RTOFF: RTC Operation OFF flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_OW: Overflow flag - * @arg RTC_FLAG_ALR: Alarm flag - * @arg RTC_FLAG_SEC: Second flag - * @retval The new state of RTC_FLAG (SET or RESET). - */ -FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); - - if ((RTC->CRL & RTC_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTCs pending flags. - * @param RTC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_RSF: Registers Synchronized flag. This flag is cleared only after - * an APB reset or an APB Clock stop. - * @arg RTC_FLAG_OW: Overflow flag - * @arg RTC_FLAG_ALR: Alarm flag - * @arg RTC_FLAG_SEC: Second flag - * @retval None - */ -void RTC_ClearFlag(uint16_t RTC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - - /* Clear the coressponding RTC flag */ - RTC->CRL &= (uint16_t)~RTC_FLAG; -} - -/** - * @brief Checks whether the specified RTC interrupt has occured or not. - * @param RTC_IT: specifies the RTC interrupts sources to check. - * This parameter can be one of the following values: - * @arg RTC_IT_OW: Overflow interrupt - * @arg RTC_IT_ALR: Alarm interrupt - * @arg RTC_IT_SEC: Second interrupt - * @retval The new state of the RTC_IT (SET or RESET). - */ -ITStatus RTC_GetITStatus(uint16_t RTC_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RTC_GET_IT(RTC_IT)); - - bitstatus = (ITStatus)(RTC->CRL & RTC_IT); - if (((RTC->CRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTCs interrupt pending bits. - * @param RTC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_IT_OW: Overflow interrupt - * @arg RTC_IT_ALR: Alarm interrupt - * @arg RTC_IT_SEC: Second interrupt - * @retval None - */ -void RTC_ClearITPendingBit(uint16_t RTC_IT) -{ - /* Check the parameters */ - assert_param(IS_RTC_IT(RTC_IT)); - - /* Clear the coressponding RTC pending bit */ - RTC->CRL &= (uint16_t)~RTC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_sdio.c b/example/libs_stm/src/stm32f10x/stm32f10x_sdio.c deleted file mode 100644 index 9d4a3763d..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_sdio.c +++ /dev/null @@ -1,798 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_sdio.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the SDIO firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_sdio.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup SDIO - * @brief SDIO driver modules - * @{ - */ - -/** @defgroup SDIO_Private_TypesDefinitions - * @{ - */ - -/* ------------ SDIO registers bit address in the alias region ----------- */ -#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) - -/* --- CLKCR Register ---*/ - -/* Alias word address of CLKEN bit */ -#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) -#define CLKEN_BitNumber 0x08 -#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) - -/* --- CMD Register ---*/ - -/* Alias word address of SDIOSUSPEND bit */ -#define CMD_OFFSET (SDIO_OFFSET + 0x0C) -#define SDIOSUSPEND_BitNumber 0x0B -#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) - -/* Alias word address of ENCMDCOMPL bit */ -#define ENCMDCOMPL_BitNumber 0x0C -#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) - -/* Alias word address of NIEN bit */ -#define NIEN_BitNumber 0x0D -#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) - -/* Alias word address of ATACMD bit */ -#define ATACMD_BitNumber 0x0E -#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) - -/* --- DCTRL Register ---*/ - -/* Alias word address of DMAEN bit */ -#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) -#define DMAEN_BitNumber 0x03 -#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) - -/* Alias word address of RWSTART bit */ -#define RWSTART_BitNumber 0x08 -#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) - -/* Alias word address of RWSTOP bit */ -#define RWSTOP_BitNumber 0x09 -#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) - -/* Alias word address of RWMOD bit */ -#define RWMOD_BitNumber 0x0A -#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) - -/* Alias word address of SDIOEN bit */ -#define SDIOEN_BitNumber 0x0B -#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) - -/* ---------------------- SDIO registers bit mask ------------------------ */ - -/* --- CLKCR Register ---*/ - -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) - -/* --- PWRCTRL Register ---*/ - -/* SDIO PWRCTRL Mask */ -#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) - -/* --- DCTRL Register ---*/ - -/* SDIO DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) - -/* --- CMD Register ---*/ - -/* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) - -/* SDIO RESP Registers Address */ -#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) - -/** - * @} - */ - -/** @defgroup SDIO_Private_Defines - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup SDIO_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the SDIO peripheral registers to their default reset values. - * @param None - * @retval None - */ -void SDIO_DeInit(void) -{ - SDIO->POWER = 0x00000000; - SDIO->CLKCR = 0x00000000; - SDIO->ARG = 0x00000000; - SDIO->CMD = 0x00000000; - SDIO->DTIMER = 0x00000000; - SDIO->DLEN = 0x00000000; - SDIO->DCTRL = 0x00000000; - SDIO->ICR = 0x00C007FF; - SDIO->MASK = 0x00000000; -} - -/** - * @brief Initializes the SDIO peripheral according to the specified - * parameters in the SDIO_InitStruct. - * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure - * that contains the configuration information for the SDIO peripheral. - * @retval None - */ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); - assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); - assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); - assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); - assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); - -/*---------------------------- SDIO CLKCR Configuration ------------------------*/ - /* Get the SDIO CLKCR value */ - tmpreg = SDIO->CLKCR; - - /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ - tmpreg &= CLKCR_CLEAR_MASK; - - /* Set CLKDIV bits according to SDIO_ClockDiv value */ - /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ - /* Set BYPASS bit according to SDIO_ClockBypass value */ - /* Set WIDBUS bits according to SDIO_BusWide value */ - /* Set NEGEDGE bits according to SDIO_ClockEdge value */ - /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ - tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | - SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | - SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); - - /* Write to SDIO CLKCR */ - SDIO->CLKCR = tmpreg; -} - -/** - * @brief Fills each SDIO_InitStruct member with its default value. - * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) -{ - /* SDIO_InitStruct members default value */ - SDIO_InitStruct->SDIO_ClockDiv = 0x00; - SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; -} - -/** - * @brief Enables or disables the SDIO Clock. - * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ClockCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; -} - -/** - * @brief Sets the power status of the controller. - * @param SDIO_PowerState: new state of the Power state. - * This parameter can be one of the following values: - * @arg SDIO_PowerState_OFF - * @arg SDIO_PowerState_ON - * @retval None - */ -void SDIO_SetPowerState(uint32_t SDIO_PowerState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); - - SDIO->POWER &= PWR_PWRCTRL_MASK; - SDIO->POWER |= SDIO_PowerState; -} - -/** - * @brief Gets the power status of the controller. - * @param None - * @retval Power status of the controller. The returned value can - * be one of the following: - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDIO_GetPowerState(void) -{ - return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); -} - -/** - * @brief Enables or disables the SDIO interrupts. - * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @param NewState: new state of the specified SDIO interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_IT(SDIO_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the SDIO interrupts */ - SDIO->MASK |= SDIO_IT; - } - else - { - /* Disable the SDIO interrupts */ - SDIO->MASK &= ~SDIO_IT; - } -} - -/** - * @brief Enables or disables the SDIO DMA request. - * @param NewState: new state of the selected SDIO DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; -} - -/** - * @brief Initializes the SDIO Command according to the specified - * parameters in the SDIO_CmdInitStruct and send the command. - * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef - * structure that contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); - assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); - assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); - assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); - -/*---------------------------- SDIO ARG Configuration ------------------------*/ - /* Set the SDIO Argument value */ - SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; - -/*---------------------------- SDIO CMD Configuration ------------------------*/ - /* Get the SDIO CMD value */ - tmpreg = SDIO->CMD; - /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ - tmpreg &= CMD_CLEAR_MASK; - /* Set CMDINDEX bits according to SDIO_CmdIndex value */ - /* Set WAITRESP bits according to SDIO_Response value */ - /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ - /* Set CPSMEN bits according to SDIO_CPSM value */ - tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response - | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; - - /* Write to SDIO CMD */ - SDIO->CMD = tmpreg; -} - -/** - * @brief Fills each SDIO_CmdInitStruct member with its default value. - * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef - * structure which will be initialized. - * @retval None - */ -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) -{ - /* SDIO_CmdInitStruct members default value */ - SDIO_CmdInitStruct->SDIO_Argument = 0x00; - SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; - SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; -} - -/** - * @brief Returns command index of last command for which response received. - * @param None - * @retval Returns the command index of the last command response received. - */ -uint8_t SDIO_GetCommandResponse(void) -{ - return (uint8_t)(SDIO->RESPCMD); -} - -/** - * @brief Returns response received from the card for the last command. - * @param SDIO_RESP: Specifies the SDIO response register. - * This parameter can be one of the following values: - * @arg SDIO_RESP1: Response Register 1 - * @arg SDIO_RESP2: Response Register 2 - * @arg SDIO_RESP3: Response Register 3 - * @arg SDIO_RESP4: Response Register 4 - * @retval The Corresponding response register value. - */ -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_RESP(SDIO_RESP)); - - tmp = SDIO_RESP_ADDR + SDIO_RESP; - - return (*(__IO uint32_t *) tmp); -} - -/** - * @brief Initializes the SDIO data path according to the specified - * parameters in the SDIO_DataInitStruct. - * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that - * contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); - assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); - assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); - assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); - assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); - -/*---------------------------- SDIO DTIMER Configuration ---------------------*/ - /* Set the SDIO Data TimeOut value */ - SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; - -/*---------------------------- SDIO DLEN Configuration -----------------------*/ - /* Set the SDIO DataLength value */ - SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; - -/*---------------------------- SDIO DCTRL Configuration ----------------------*/ - /* Get the SDIO DCTRL value */ - tmpreg = SDIO->DCTRL; - /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ - tmpreg &= DCTRL_CLEAR_MASK; - /* Set DEN bit according to SDIO_DPSM value */ - /* Set DTMODE bit according to SDIO_TransferMode value */ - /* Set DTDIR bit according to SDIO_TransferDir value */ - /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ - tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir - | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; - - /* Write to SDIO DCTRL */ - SDIO->DCTRL = tmpreg; -} - -/** - * @brief Fills each SDIO_DataInitStruct member with its default value. - * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - /* SDIO_DataInitStruct members default value */ - SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; - SDIO_DataInitStruct->SDIO_DataLength = 0x00; - SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; - SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; -} - -/** - * @brief Returns number of remaining data bytes to be transferred. - * @param None - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDIO_GetDataCounter(void) -{ - return SDIO->DCOUNT; -} - -/** - * @brief Read one data word from Rx FIFO. - * @param None - * @retval Data received - */ -uint32_t SDIO_ReadData(void) -{ - return SDIO->FIFO; -} - -/** - * @brief Write one data word to Tx FIFO. - * @param Data: 32-bit data word to write. - * @retval None - */ -void SDIO_WriteData(uint32_t Data) -{ - SDIO->FIFO = Data; -} - -/** - * @brief Returns the number of words left to be written to or read from FIFO. - * @param None - * @retval Remaining number of words. - */ -uint32_t SDIO_GetFIFOCount(void) -{ - return SDIO->FIFOCNT; -} - -/** - * @brief Starts the SD I/O Read Wait operation. - * @param NewState: new state of the Start SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StartSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; -} - -/** - * @brief Stops the SD I/O Read Wait operation. - * @param NewState: new state of the Stop SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StopSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; -} - -/** - * @brief Sets one of the two options of inserting read wait interval. - * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. - * This parametre can be: - * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK - * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 - * @retval None - */ -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) -{ - /* Check the parameters */ - assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); - - *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; -} - -/** - * @brief Enables or disables the SD I/O Mode Operation. - * @param NewState: new state of SDIO specific operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SetSDIOOperation(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the SD I/O Mode suspend command sending. - * @param NewState: new state of the SD I/O Mode suspend command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the command completion signal. - * @param NewState: new state of command completion signal. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CommandCompletionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the CE-ATA interrupt. - * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CEATAITCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); -} - -/** - * @brief Sends CE-ATA command (CMD61). - * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendCEATACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; -} - -/** - * @brief Checks whether the specified SDIO flag is set or not. - * @param SDIO_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide - * bus mode. - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_CMDACT: Command transfer in progress - * @arg SDIO_FLAG_TXACT: Data transmit in progress - * @arg SDIO_FLAG_RXACT: Data receive in progress - * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full - * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval The new state of SDIO_FLAG (SET or RESET). - */ -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_FLAG(SDIO_FLAG)); - - if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's pending flags. - * @param SDIO_FLAG: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide - * bus mode - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearFlag(uint32_t SDIO_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); - - SDIO->ICR = SDIO_FLAG; -} - -/** - * @brief Checks whether the specified SDIO interrupt has occurred or not. - * @param SDIO_IT: specifies the SDIO interrupt source to check. - * This parameter can be one of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval The new state of SDIO_IT (SET or RESET). - */ -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_GET_IT(SDIO_IT)); - if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIOs interrupt pending bits. - * @param SDIO_IT: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearITPendingBit(uint32_t SDIO_IT) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); - - SDIO->ICR = SDIO_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_spi.c b/example/libs_stm/src/stm32f10x/stm32f10x_spi.c deleted file mode 100644 index b1ff419d9..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_spi.c +++ /dev/null @@ -1,907 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_spi.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the SPI firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_spi.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/** @defgroup SPI_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - - -/** @defgroup SPI_Private_Defines - * @{ - */ - -/* SPI SPE mask */ -#define CR1_SPE_Set ((uint16_t)0x0040) -#define CR1_SPE_Reset ((uint16_t)0xFFBF) - -/* I2S I2SE mask */ -#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) -#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) - -/* SPI CRCNext mask */ -#define CR1_CRCNext_Set ((uint16_t)0x1000) - -/* SPI CRCEN mask */ -#define CR1_CRCEN_Set ((uint16_t)0x2000) -#define CR1_CRCEN_Reset ((uint16_t)0xDFFF) - -/* SPI SSOE mask */ -#define CR2_SSOE_Set ((uint16_t)0x0004) -#define CR2_SSOE_Reset ((uint16_t)0xFFFB) - -/* SPI registers Masks */ -#define CR1_CLEAR_Mask ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) - -/* SPI or I2S mode selection masks */ -#define SPI_Mode_Select ((uint16_t)0xF7FF) -#define I2S_Mode_Select ((uint16_t)0x0800) - -/* I2S clock source selection masks */ -#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) -#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) -#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) -#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) - -/** - * @} - */ - -/** @defgroup SPI_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values (Affects also the I2Ss). - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else - { - if (SPIx == SPI3) - { - /* Enable SPI3 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - /* Release SPI3 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - } - } -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - -/*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_Mask; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/salve mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - SPIx->I2SCFGR &= SPI_Mode_Select; - -/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral - * (configured in I2S mode). - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * @note - * The function calculates the optimal prescaler needed to obtain the most - * accurate audio frequency (depending on the I2S clock source, the PLL values - * and the product configuration). But in case the prescaler value is greater - * than 511, the default value (0x02) will be configured instead. * - * @retval None - */ -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0; - RCC_ClocksTypeDef RCC_Clocks; - uint32_t sourceclock = 0; - - /* Check the I2S parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; - SPIx->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = SPIx->I2SCFGR; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) */ - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* Get the I2S clock source mask depending on the peripheral number */ - if(((uint32_t)SPIx) == SPI2_BASE) - { - /* The mask is relative to I2S2 */ - tmp = I2S2_CLOCK_SRC; - } - else - { - /* The mask is relative to I2S3 */ - tmp = I2S3_CLOCK_SRC; - } - - /* Check the I2S clock source configuration depending on the Device: - Only Connectivity line devices have the PLL3 VCO clock */ -#ifdef STM32F10X_CL - if((RCC->CFGR2 & tmp) != 0) - { - /* Get the configuration bits of RCC PLL3 multiplier */ - tmp = (uint32_t)((RCC->CFGR2 & I2S_MUL_MASK) >> 12); - - /* Get the value of the PLL3 multiplier */ - if((tmp > 5) && (tmp < 15)) - { - /* Multplier is between 8 and 14 (value 15 is forbidden) */ - tmp += 2; - } - else - { - if (tmp == 15) - { - /* Multiplier is 20 */ - tmp = 20; - } - } - /* Get the PREDIV2 value */ - sourceclock = (uint32_t)(((RCC->CFGR2 & I2S_DIV_MASK) >> 4) + 1); - - /* Calculate the Source Clock frequency based on PLL3 and PREDIV2 values */ - sourceclock = (uint32_t) ((HSE_Value / sourceclock) * tmp * 2); - } - else - { - /* I2S Clock source is System clock: Get System Clock frequency */ - RCC_GetClocksFreq(&RCC_Clocks); - - /* Get the source clock value: based on System Clock value */ - sourceclock = RCC_Clocks.SYSCLK_Frequency; - } -#else /* STM32F10X_HD */ - /* I2S Clock source is System clock: Get System Clock frequency */ - RCC_GetClocksFreq(&RCC_Clocks); - - /* Get the source clock value: based on System Clock value */ - sourceclock = RCC_Clocks.SYSCLK_Frequency; -#endif /* STM32F10X_CL */ - - /* Compute the Real divider depending on the MCLK output state with a flaoting point */ - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - /* MCLK output is enabled */ - tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - /* Remove the flaoting point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /* Write to SPIx I2SPR register the computed value */ - SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - SPIx->I2SCFGR = tmpreg; -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Fills each I2S_InitStruct member with its default value. - * @param I2S_InitStruct : pointer to a I2S_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) -{ -/*--------------- Reset I2S init structure parameters values -----------------*/ - /* Initialize the I2S_Mode member */ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - - /* Initialize the I2S_Standard member */ - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - - /* Initialize the I2S_DataFormat member */ - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - - /* Initialize the I2S_MCLKOutput member */ - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - - /* Initialize the I2S_AudioFreq member */ - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - - /* Initialize the I2S_CPOL member */ - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= CR1_SPE_Set; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= CR1_SPE_Reset; - } -} - -/** - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; - } - else - { - /* Disable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; - } -} - -/** - * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI/I2S interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI/I2S IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI/I2S interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI/I2S interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_DMAReq: specifies the SPI/I2S DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI/I2S DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); - if (NewState != DISABLE) - { - /* Enable the selected SPI/I2S DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI/I2S DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param Data : Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Write in the DR register the data to be sent */ - SPIx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the data in the DR register */ - return SPIx->DR; -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= CR2_SSOE_Set; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= CR2_SSOE_Reset; - } -} - -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_DataSize: specifies the SPI data size. - * This parameter can be one of the following values: - * @arg SPI_DataSize_16b: Set data frame format to 16bit - * @arg SPI_DataSize_8b: Set data frame format to 8bit - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATASIZE(SPI_DataSize)); - /* Clear DFF bit */ - SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; - /* Set new DFF bit value */ - SPIx->CR1 |= SPI_DataSize; -} - -/** - * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= CR1_CRCNext_Set; -} - -/** - * @brief Enables or disables the CRC value calculation of the transfered bytes. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= CR1_CRCEN_Set; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= CR1_CRCEN_Reset; - } -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @brief Selects the data transfer direction in bi-directional mode for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_Direction: specifies the data transfer direction in bi-directional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Checks whether the specified SPI/I2S flag is set or not. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_FLAG: specifies the SPI/I2S flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_FLAG_MODF: Mode Fault flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - /* Check the status of the specified SPI/I2S flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @note - * - OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * - UDR (UnderRun error) flag is cleared by a read operation to - * SPI_SR register (SPI_I2S_GetFlagStatus()). - * - MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * - 2 or 3 in I2S mode - * @param SPI_I2S_IT: specifies the SPI/I2S interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg SPI_IT_MODF: Mode Fault interrupt. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * @arg I2S_IT_UDR: Underrun Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI/I2S IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI/I2S IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI/I2S interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * @param SPIx: where x can be - * - 1, 2 or 3 in SPI mode - * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. - * This function clears only CRCERR intetrrupt pending bit. - * @note - * - OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). - * - UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_SR register (SPI_I2S_GetITStatus()). - * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable - * the SPI). - * @retval None - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ - SPIx->SR = (uint16_t)~itpos; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_tim.c b/example/libs_stm/src/stm32f10x/stm32f10x_tim.c deleted file mode 100644 index c626dca35..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_tim.c +++ /dev/null @@ -1,2834 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_tim.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the TIM firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_tim.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup TIM - * @brief TIM driver modules - * @{ - */ - -/** @defgroup TIM_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Defines - * @{ - */ - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define SMCR_ETR_Mask ((uint16_t)0x00FF) -#define CCMR_Offset ((uint16_t)0x0018) -#define CCER_CCE_Set ((uint16_t)0x0001) -#define CCER_CCNE_Set ((uint16_t)0x0004) - -/** - * @} - */ - -/** @defgroup TIM_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_FunctionPrototypes - * @{ - */ - -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -/** - * @} - */ - -/** @defgroup TIM_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @retval None - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - if (TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if (TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if (TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if (TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } - else if (TIMx == TIM5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); - } - else if (TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } - else if (TIMx == TIM7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); - } - else if (TIMx == TIM8) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); - } - else if (TIMx == TIM9) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); - } - else if (TIMx == TIM10) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); - } - else if (TIMx == TIM11) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); - } - else if (TIMx == TIM12) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); - } - else if (TIMx == TIM13) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); - } - else if (TIMx == TIM14) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); - } - else if (TIMx == TIM15) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); - } - else if (TIMx == TIM16) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); - } - else - { - if (TIMx == TIM17) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); - } - } -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef - * structure that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); - - tmpcr1 = TIMx->CR1; - - if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| - (TIMx == TIM4) || (TIMx == TIM5)) - { - /* Select the Counter Mode */ - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - if((TIMx != TIM6) && (TIMx != TIM7)) - { - /* Set the clock division */ - tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler and the Repetition counter - values immediately */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| - (TIMx == TIM16)|| (TIMx == TIM17)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); - /* Set the Output N Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); - /* Set the Output N State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - - /* Reset the Ouput Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); - - /* Set the Output Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select - * the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - - /* Reset the Ouput Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); - - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - /* Reset the Ouput Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Ouput Compare IDLE State */ - tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* TI3 Configuration */ - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* TI4 Configuration */ - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Configures the: Break feature, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable). - * @param TIMx: where x can be 1 or 8 to select the TIM - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval None - */ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); - assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); - assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); - assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); - assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); - /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef - * structure which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which - * will be initialized. - * @retval None - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_CEN; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); - } -} - -/** - * @brief Enables or disables the TIM peripheral Main Outputs. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral. - * @param NewState: new state of the TIM peripheral Main Outputs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TIM Main Output */ - TIMx->BDTR |= TIM_BDTR_MOE; - } - else - { - /* Disable the TIM Main Output */ - TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); - } -} - -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. - * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * @note - * - TIM6 and TIM7 can only generate an update interrupt. - * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, - * TIM_IT_CC2 or TIM_IT_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx->DIER |= TIM_IT; - } - else - { - /* Disable the Interrupt sources */ - TIMx->DIER &= (uint16_t)~TIM_IT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * @note - * - TIM6 and TIM7 can only generate an update event. - * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Configures the TIMxs DMA interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select - * the TIM peripheral. - * @param TIM_DMABase: DMA Base address. - * This parameter can be one of the following values: - * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, - * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, - * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, - * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, - * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, - * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, - * TIM_DMABase_DCR. - * @param TIM_DMABurstLength: DMA Burst length. - * This parameter can be one value between: - * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes. - * @retval None - */ -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); - assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); - /* Set the DMA Base and the DMA Burst Length */ - TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; -} - -/** - * @brief Enables or disables the TIMxs DMA Requests. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 - * to select the TIM peripheral. - * @param TIM_DMASource: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg TIM_DMA_Update: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_Trigger: TIM Trigger DMA source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST9_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA sources */ - TIMx->DIER |= TIM_DMASource; - } - else - { - /* Disable the DMA sources */ - TIMx->DIER &= (uint16_t)~TIM_DMASource; - } -} - -/** - * @brief Configures the TIMx interrnal Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 - * to select the TIM peripheral. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ITRSource: Trigger source. - * This parameter can be one of the following values: - * @param TIM_TS_ITR0: Internal Trigger 0 - * @param TIM_TS_ITR1: Internal Trigger 1 - * @param TIM_TS_ITR2: Internal Trigger 2 - * @param TIM_TS_ITR3: Internal Trigger 3 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter : specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the SMS Bits */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - /* Select the Trigger selection : ETRF */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); - tmpsmcr |= TIM_TS_ETRF; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - /* Enable the External clock mode2 */ - TIMx->SMCR |= TIM_SMCR_ECE; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - tmpsmcr = TIMx->SMCR; - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_Mask; - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - tmpcr1 = TIMx->CR1; - /* Reset the CMS and DIR Bits */ - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parmeter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parmeter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Set the encoder Mode */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); - tmpsmcr |= TIM_EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); - tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P))); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1M Bits */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2M Bits */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); - /* Configure The Forced output Mode */ - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC1M Bits */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC2M Bits */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); - /* Configure The Forced output Mode */ - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= TIM_CR1_ARPE; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); - } -} - -/** - * @brief Selects the TIM peripheral Commutation event. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the COM Bit */ - TIMx->CR2 |= TIM_CR2_CCUS; - } - else - { - /* Reset the COM Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); - } -} - -/** - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select - * the TIM peripheral. - * @param NewState: new state of the Capture Compare DMA source - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCDS Bit */ - TIMx->CR2 |= TIM_CR2_CCDS; - } - else - { - /* Reset the CCDS Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); - } -} - -/** - * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 - * to select the TIMx peripheral - * @param NewState: new state of the Capture Compare Preload Control bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCPC Bit */ - TIMx->CR2 |= TIM_CR2_CCPC; - } - else - { - /* Reset the CCPC Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); - } -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1PE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select - * the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2PE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3PE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4PE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1FE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select - * the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2FE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3FE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4FE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF1 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1CE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= TIM_OCClear; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF2 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2CE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF3 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3CE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= TIM_OCClear; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF4 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4CE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC1P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); - tmpccer |= TIM_OCPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 1N polarity. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC1N Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC1NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); - tmpccer |= TIM_OCNPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC2P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 2N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC2N Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC2NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC3P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 3N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC3N Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC3NP Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - tmpccer = TIMx->CCER; - /* Set or Reset the CC4P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parmeter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = CCER_CCE_Set << TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t)~ tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parmeter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. - * @retval None - */ -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCXN(TIM_CCxN)); - - tmp = CCER_CCNE_Set << TIM_Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= (uint16_t) ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} - -/** - * @brief Selects the TIM Ouput Compare Mode. - * @note This function disables the selected channel before changing the Ouput - * Compare Mode. - * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parmeter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This paramter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_Offset; - - tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= TIM_CR1_UDIS; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. - * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= TIM_CR1_URS; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); - } -} - -/** - * @brief Enables or disables the TIMxs Hall sensor interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= TIM_CR2_TI1S; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); - } -} - -/** - * @brief Selects the TIMxs One Pulse Mode. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - /* Reset the OPM Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This paramter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). - * - * - For all TIMx except TIM6 and TIM7 - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs (TRGO). - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST7_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This paramter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes - * the counter and triggers an update of the registers. - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - /* Reset the SMS Bits */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); - /* Select the Slave Mode */ - TIMx->SMCR |= TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This paramter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO). - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - /* Reset the MSM Bit */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Clock Division value. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select - * the TIM peripheral. - * @param TIM_CKD: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CKD_DIV1: TDTS = Tck_tim - * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim - * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - assert_param(IS_TIM_CKD_DIV(TIM_CKD)); - /* Reset the CKD Bits */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); - /* Set the CKD value */ - TIMx->CR1 |= TIM_CKD; -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @retval Capture Compare 1 Register value. - */ -uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST8_PERIPH(TIMx)); - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @retval Capture Compare 2 Register value. - */ -uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 3 Register value. - */ -uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 4 Register value. - */ -uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @retval Counter Register value. - */ -uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @retval Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Checks whether the specified TIM flag is set or not. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * @note - * - TIM6 and TIM7 can have only one update flag. - * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, - * TIM_FLAG_CC2 or TIM_FLAG_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. - * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval The new state of TIM_FLAG (SET or RESET). - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); - - if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's pending flags. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * @note - * - TIM6 and TIM7 can have only one update flag. - * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, - * TIM_FLAG_CC2 or TIM_FLAG_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. - * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval None - */ -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); - - /* Clear the flags */ - TIMx->SR = (uint16_t)~TIM_FLAG; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_IT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * @note - * - TIM6 and TIM7 can generate only an update interrupt. - * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, - * TIM_IT_CC2 or TIM_IT_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_IT(TIM_IT)); - - itstatus = TIMx->SR & TIM_IT; - - itenable = TIMx->DIER & TIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. - * @param TIM_IT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM1 update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * @note - * - TIM6 and TIM7 can generate only an update interrupt. - * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, - * TIM_IT_CC2 or TIM_IT_Trigger. - * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. - * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. - * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. - * @retval None - */ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - /* Clear the IT pending Bit */ - TIMx->SR = (uint16_t)~TIM_IT; -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - /* Select the Input and set the filter */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - /* Select the Input and set the filter */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_usart.c b/example/libs_stm/src/stm32f10x/stm32f10x_usart.c deleted file mode 100644 index fa0733e89..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_usart.c +++ /dev/null @@ -1,1054 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_usart.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the USART firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_usart.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup USART - * @brief USART driver modules - * @{ - */ - -/** @defgroup USART_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Defines - * @{ - */ - -#define CR1_UE_Set ((uint16_t)0x2000) /*!< USART Enable Mask */ -#define CR1_UE_Reset ((uint16_t)0xDFFF) /*!< USART Disable Mask */ - -#define CR1_WAKE_Mask ((uint16_t)0xF7FF) /*!< USART WakeUp Method Mask */ - -#define CR1_RWU_Set ((uint16_t)0x0002) /*!< USART mute mode Enable Mask */ -#define CR1_RWU_Reset ((uint16_t)0xFFFD) /*!< USART mute mode Enable Mask */ -#define CR1_SBK_Set ((uint16_t)0x0001) /*!< USART Break Character send Mask */ -#define CR1_CLEAR_Mask ((uint16_t)0xE9F3) /*!< USART CR1 Mask */ -#define CR2_Address_Mask ((uint16_t)0xFFF0) /*!< USART address Mask */ - -#define CR2_LINEN_Set ((uint16_t)0x4000) /*!< USART LIN Enable Mask */ -#define CR2_LINEN_Reset ((uint16_t)0xBFFF) /*!< USART LIN Disable Mask */ - -#define CR2_LBDL_Mask ((uint16_t)0xFFDF) /*!< USART LIN Break detection Mask */ -#define CR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /*!< USART CR2 STOP Bits Mask */ -#define CR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /*!< USART CR2 Clock Mask */ - -#define CR3_SCEN_Set ((uint16_t)0x0020) /*!< USART SC Enable Mask */ -#define CR3_SCEN_Reset ((uint16_t)0xFFDF) /*!< USART SC Disable Mask */ - -#define CR3_NACK_Set ((uint16_t)0x0010) /*!< USART SC NACK Enable Mask */ -#define CR3_NACK_Reset ((uint16_t)0xFFEF) /*!< USART SC NACK Disable Mask */ - -#define CR3_HDSEL_Set ((uint16_t)0x0008) /*!< USART Half-Duplex Enable Mask */ -#define CR3_HDSEL_Reset ((uint16_t)0xFFF7) /*!< USART Half-Duplex Disable Mask */ - -#define CR3_IRLP_Mask ((uint16_t)0xFFFB) /*!< USART IrDA LowPower mode Mask */ -#define CR3_CLEAR_Mask ((uint16_t)0xFCFF) /*!< USART CR3 Mask */ - -#define CR3_IREN_Set ((uint16_t)0x0002) /*!< USART IrDA Enable Mask */ -#define CR3_IREN_Reset ((uint16_t)0xFFFD) /*!< USART IrDA Disable Mask */ -#define GTPR_LSB_Mask ((uint16_t)0x00FF) /*!< Guard Time Register LSB Mask */ -#define GTPR_MSB_Mask ((uint16_t)0xFF00) /*!< Guard Time Register MSB Mask */ -#define IT_Mask ((uint16_t)0x001F) /*!< USART Interrupt Mask */ - -/* USART OverSampling-8 Mask */ -#define CR1_OVER8_Set ((u16)0x8000) /* USART OVER8 mode Enable Mask */ -#define CR1_OVER8_Reset ((u16)0x7FFF) /* USART OVER8 mode Disable Mask */ - -/* USART One Bit Sampling Mask */ -#define CR3_ONEBITE_Set ((u16)0x0800) /* USART ONEBITE mode Enable Mask */ -#define CR3_ONEBITE_Reset ((u16)0xF7FF) /* USART ONEBITE mode Disable Mask */ - -/** - * @} - */ - -/** @defgroup USART_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: USART1, USART2, USART3, UART4 or UART5. - * @retval None - */ -void USART_DeInit(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - if (USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if (USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if (USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if (USARTx == UART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - } - else - { - if (USARTx == UART5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); - } - } -} - -/** - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * that contains the configuration information for the specified USART peripheral. - * @retval None - */ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - uint32_t usartxbase = 0; - RCC_ClocksTypeDef RCC_ClocksStatus; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - /* The hardware flow control is available only for USART1, USART2 and USART3 */ - if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear STOP[13:12] bits */ - tmpreg &= CR2_STOP_CLEAR_Mask; - /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ - /* Set STOP[13:12] bits according to USART_StopBits value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; - -/*---------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = USARTx->CR1; - /* Clear M, PCE, PS, TE and RE bits */ - tmpreg &= CR1_CLEAR_Mask; - /* Configure the USART Word Length, Parity and mode ----------------------- */ - /* Set the M bits according to USART_WordLength value */ - /* Set PCE and PS bits according to USART_Parity value */ - /* Set TE and RE bits according to USART_Mode value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - /* Write to USART CR1 */ - USARTx->CR1 = (uint16_t)tmpreg; - -/*---------------------------- USART CR3 Configuration -----------------------*/ - tmpreg = USARTx->CR3; - /* Clear CTSE and RTSE bits */ - tmpreg &= CR3_CLEAR_Mask; - /* Configure the USART HFC -------------------------------------------------*/ - /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - /* Write to USART CR3 */ - USARTx->CR3 = (uint16_t)tmpreg; - -/*---------------------------- USART BRR Configuration -----------------------*/ - /* Configure the USART Baud Rate -------------------------------------------*/ - RCC_GetClocksFreq(&RCC_ClocksStatus); - if (usartxbase == USART1_BASE) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - /* Determine the integer part */ - if ((USARTx->CR1 & CR1_OVER8_Set) != 0) - { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ - { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - /* Determine the fractional part */ - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - /* Implement the fractional part in the register */ - if ((USARTx->CR1 & CR1_OVER8_Set) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - /* Write to USART BRR */ - USARTx->BRR = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_InitStruct member with its default value. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. - * @retval None - */ -void USART_StructInit(USART_InitTypeDef* USART_InitStruct) -{ - /* USART_InitStruct members default value */ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No ; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/** - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * @note The Smart Card mode is not available for UART4 and UART5. - * @retval None - */ -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear CLKEN, CPOL, CPHA and LBCL bits */ - tmpreg &= CR2_CLOCK_CLEAR_Mask; - /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ - /* Set CLKEN bit according to USART_Clock value */ - /* Set CPOL bit according to USART_CPOL value */ - /* Set CPHA bit according to USART_CPHA value */ - /* Set LBCL bit according to USART_LastBit value */ - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_ClockInitStruct member with its default value. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure which will be initialized. - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - /* USART_ClockInitStruct members default value */ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/** - * @brief Enables or disables the specified USART peripheral. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART by setting the UE bit in the CR1 register */ - USARTx->CR1 |= CR1_UE_Set; - } - else - { - /* Disable the selected USART by clearing the UE bit in the CR1 register */ - USARTx->CR1 &= CR1_UE_Reset; - } -} - -/** - * @brief Enables or disables the specified USART interrupts. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param NewState: new state of the specified USARTx interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CONFIG_IT(USART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - - /* Get the interrupt position */ - itpos = USART_IT & IT_Mask; - itmask = (((uint32_t)0x01) << itpos); - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - usartxbase += 0x0C; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - usartxbase += 0x10; - } - else /* The IT is in CR3 register */ - { - usartxbase += 0x14; - } - if (NewState != DISABLE) - { - *(__IO uint32_t*)usartxbase |= itmask; - } - else - { - *(__IO uint32_t*)usartxbase &= ~itmask; - } -} - -/** - * @brief Enables or disables the USARTs DMA interface. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3 or UART4. - * @param USART_DMAReq: specifies the DMA request. - * This parameter can be any combination of the following values: - * @arg USART_DMAReq_Tx: USART DMA transmit request - * @arg USART_DMAReq_Rx: USART DMA receive request - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @note The DMA mode is not available for UART5. - * @retval None - */ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_1234_PERIPH(USARTx)); - assert_param(IS_USART_DMAREQ(USART_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the DMA transfer for selected requests by setting the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 |= USART_DMAReq; - } - else - { - /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 &= (uint16_t)~USART_DMAReq; - } -} - -/** - * @brief Sets the address of the USART node. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_ADDRESS(USART_Address)); - - /* Clear the USART address */ - USARTx->CR2 &= CR2_Address_Mask; - /* Set the USART address node */ - USARTx->CR2 |= USART_Address; -} - -/** - * @brief Selects the USART WakeUp method. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_WakeUp: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - * @retval None - */ -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_WAKEUP(USART_WakeUp)); - - USARTx->CR1 &= CR1_WAKE_Mask; - USARTx->CR1 |= USART_WakeUp; -} - -/** - * @brief Determines if the USART is in mute mode or not. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - USARTx->CR1 |= CR1_RWU_Set; - } - else - { - /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - USARTx->CR1 &= CR1_RWU_Reset; - } -} - -/** - * @brief Sets the USART LIN Break detection length. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_LINBreakDetectLength: specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg USART_LINBreakDetectLength_10b: 10-bit break detection - * @arg USART_LINBreakDetectLength_11b: 11-bit break detection - * @retval None - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); - - USARTx->CR2 &= CR2_LBDL_Mask; - USARTx->CR2 |= USART_LINBreakDetectLength; -} - -/** - * @brief Enables or disables the USARTs LIN mode. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART LIN mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - USARTx->CR2 |= CR2_LINEN_Set; - } - else - { - /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ - USARTx->CR2 &= CR2_LINEN_Reset; - } -} - -/** - * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param Data: the data to transmit. - * @retval None - */ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DATA(Data)); - - /* Transmit Data */ - USARTx->DR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @retval The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Receive Data */ - return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); -} - -/** - * @brief Transmits break characters. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @retval None - */ -void USART_SendBreak(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Send break characters */ - USARTx->CR1 |= CR1_SBK_Set; -} - -/** - * @brief Sets the specified USART guard time. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @param USART_GuardTime: specifies the guard time. - * @note The guard time bits are not available for UART4 and UART5. - * @retval None - */ -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - - /* Clear the USART Guard time */ - USARTx->GTPR &= GTPR_LSB_Mask; - /* Set the USART guard time */ - USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/** - * @brief Sets the system clock prescaler. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_Prescaler: specifies the prescaler clock. - * @note The function is used for IrDA mode with UART4 and UART5. - * @retval None - */ -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART prescaler */ - USARTx->GTPR &= GTPR_MSB_Mask; - /* Set the USART prescaler */ - USARTx->GTPR |= USART_Prescaler; -} - -/** - * @brief Enables or disables the USARTs Smart Card mode. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @note The Smart Card mode is not available for UART4 and UART5. - * @retval None - */ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - USARTx->CR3 |= CR3_SCEN_Set; - } - else - { - /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ - USARTx->CR3 &= CR3_SCEN_Reset; - } -} - -/** - * @brief Enables or disables NACK transmission. - * @param USARTx: where x can be 1, 2 or 3 to select the USART peripheral. - * @param NewState: new state of the NACK transmission. - * This parameter can be: ENABLE or DISABLE. - * @note The Smart Card mode is not available for UART4 and UART5. - * @retval None - */ -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_123_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ - USARTx->CR3 |= CR3_NACK_Set; - } - else - { - /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ - USARTx->CR3 &= CR3_NACK_Reset; - } -} - -/** - * @brief Enables or disables the USARTs Half Duplex communication. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART Communication. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - USARTx->CR3 |= CR3_HDSEL_Set; - } - else - { - /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - USARTx->CR3 &= CR3_HDSEL_Reset; - } -} - - -/** - * @brief Enables or disables the USART's 8x oversampling mode. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART one bit sampling methode. - * This parameter can be: ENABLE or DISABLE. - * @note - * This function has to be called before calling USART_Init() - * function in order to have correct baudrate Divider value. - * @retval None - */ -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ - USARTx->CR1 |= CR1_OVER8_Set; - } - else - { - /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ - USARTx->CR1 &= CR1_OVER8_Reset; - } -} - -/** - * @brief Enables or disables the USART's one bit sampling methode. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the USART one bit sampling methode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ - USARTx->CR3 |= CR3_ONEBITE_Set; - } - else - { - /* Disable tthe one bit method by clearing the ONEBITE bit in the CR3 register */ - USARTx->CR3 &= CR3_ONEBITE_Reset; - } -} - -/** - * @brief Configures the USARTs IrDA interface. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IrDAMode: specifies the IrDA mode. - * This parameter can be one of the following values: - * @arg USART_IrDAMode_LowPower - * @arg USART_IrDAMode_Normal - * @retval None - */ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); - - USARTx->CR3 &= CR3_IRLP_Mask; - USARTx->CR3 |= USART_IrDAMode; -} - -/** - * @brief Enables or disables the USARTs IrDA interface. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param NewState: new state of the IrDA mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - USARTx->CR3 |= CR3_IREN_Set; - } - else - { - /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ - USARTx->CR3 &= CR3_IREN_Reset; - } -} - -/** - * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TXE: Transmit data register empty flag - * @arg USART_FLAG_TC: Transmission Complete flag - * @arg USART_FLAG_RXNE: Receive data register not empty flag - * @arg USART_FLAG_IDLE: Idle Line detection flag - * @arg USART_FLAG_ORE: OverRun Error flag - * @arg USART_FLAG_NE: Noise Error flag - * @arg USART_FLAG_FE: Framing Error flag - * @arg USART_FLAG_PE: Parity Error flag - * @retval The new state of USART_FLAG (SET or RESET). - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_FLAG(USART_FLAG)); - /* The CTS flag is not available for UART4 and UART5 */ - if (USART_FLAG == USART_FLAG_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the USARTx's pending flags. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). - * @arg USART_FLAG_LBD: LIN Break detection flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * - * @note - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DR register (USART_ReceiveData()). - * - RXNE flag can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * - TC flag can be also cleared by software sequence: a read operation to - * USART_SR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DR register (USART_SendData()). - * - TXE flag is cleared only by a write to the USART_DR register - * (USART_SendData()). - * @retval None - */ -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - /* The CTS flag is not available for UART4 and UART5 */ - if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - USARTx->SR = (uint16_t)~USART_FLAG; -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IT: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ORE: OverRun Error interrupt - * @arg USART_IT_NE: Noise Error interrupt - * @arg USART_IT_FE: Framing Error interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @retval The new state of USART_IT (SET or RESET). - */ -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_GET_IT(USART_IT)); - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - /* Get the interrupt position */ - itmask = USART_IT & IT_Mask; - itmask = (uint32_t)0x01 << itmask; - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - itmask &= USARTx->CR1; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - itmask &= USARTx->CR2; - } - else /* The IT is in CR3 register */ - { - itmask &= USARTx->CR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->SR; - if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Clears the USARTxs interrupt pending bits. - * @param USARTx: Select the USART or the UART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3, UART4 or UART5. - * @param USART_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * - * @note - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_SR register - * (USART_GetITStatus()) followed by a read operation to USART_DR register - * (USART_ReceiveData()). - * - RXNE pending bit can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * - TC pending bit can be also cleared by software sequence: a read - * operation to USART_SR register (USART_GetITStatus()) followed by a write - * operation to USART_DR register (USART_SendData()). - * - TXE pending bit is cleared only by a write to the USART_DR register - * (USART_SendData()). - * @retval None - */ -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_IT(USART_IT)); - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_123_PERIPH(USARTx)); - } - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->SR = (uint16_t)~itmask; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32f10x/stm32f10x_wwdg.c b/example/libs_stm/src/stm32f10x/stm32f10x_wwdg.c deleted file mode 100644 index cd4978bbe..000000000 --- a/example/libs_stm/src/stm32f10x/stm32f10x_wwdg.c +++ /dev/null @@ -1,223 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f10x_wwdg.c - * @author MCD Application Team - * @version V3.3.0 - * @date 04/16/2010 - * @brief This file provides all the WWDG firmware functions. - ****************************************************************************** - * @copy - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f10x_wwdg.h" -#include "stm32f10x_rcc.h" - -/** @addtogroup STM32F10x_StdPeriph_Driver - * @{ - */ - -/** @defgroup WWDG - * @brief WWDG driver modules - * @{ - */ - -/** @defgroup WWDG_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_Defines - * @{ - */ - -/* ----------- WWDG registers bit address in the alias region ----------- */ -#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) - -/* Alias word address of EWI bit */ -#define CFR_OFFSET (WWDG_OFFSET + 0x04) -#define EWI_BitNumber 0x09 -#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) - -/* --------------------- WWDG registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_WDGA_Set ((uint32_t)0x00000080) - -/* CFR register bit mask */ -#define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) -#define CFR_W_Mask ((uint32_t)0xFFFFFF80) -#define BIT_Mask ((uint8_t)0x7F) - -/** - * @} - */ - -/** @defgroup WWDG_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup WWDG_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the WWDG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/** - * @brief Sets the WWDG Prescaler. - * @param WWDG_Prescaler: specifies the WWDG Prescaler. - * This parameter can be one of the following values: - * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 - * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 - * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 - * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 - * @retval None - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); - /* Clear WDGTB[1:0] bits */ - tmpreg = WWDG->CFR & CFR_WDGTB_Mask; - /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ - tmpreg |= WWDG_Prescaler; - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Sets the WWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * This parameter value must be lower than 0x80. - * @retval None - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); - /* Clear W[6:0] bits */ - - tmpreg = WWDG->CFR & CFR_W_Mask; - - /* Set W[6:0] bits according to WindowValue value */ - tmpreg |= WindowValue & (uint32_t) BIT_Mask; - - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Enables the WWDG Early Wakeup interrupt(EWI). - * @param None - * @retval None - */ -void WWDG_EnableIT(void) -{ - *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; -} - -/** - * @brief Sets the WWDG counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F. - * @retval None - */ -void WWDG_SetCounter(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to T[6:0] bits to configure the counter value, no need to do - a read-modify-write; writing a 0 to WDGA bit does nothing */ - WWDG->CR = Counter & BIT_Mask; -} - -/** - * @brief Enables WWDG and load the counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F. - * @retval None - */ -void WWDG_Enable(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - WWDG->CR = CR_WDGA_Set | Counter; -} - -/** - * @brief Checks whether the Early Wakeup interrupt flag is set or not. - * @param None - * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - return (FlagStatus)(WWDG->SR); -} - -/** - * @brief Clears Early Wakeup interrupt flag. - * @param None - * @retval None - */ -void WWDG_ClearFlag(void) -{ - WWDG->SR = (uint32_t)RESET; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/misc.c b/example/libs_stm/src/stm32l1xx/misc.c deleted file mode 100644 index 3b7a0009e..000000000 --- a/example/libs_stm/src/stm32l1xx/misc.c +++ /dev/null @@ -1,249 +0,0 @@ -/** - ****************************************************************************** - * @file misc.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "misc.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup MISC_Private_Functions - * @{ - */ -/** - * -@verbatim - ******************************************************************************* - Interrupts configuration functions - ******************************************************************************* - - This section provide functions allowing to configure the NVIC interrupts (IRQ). - The Cortex-M3 exceptions are managed by CMSIS functions. - - 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() function - according to the following table. - - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - ============================================================================================================================ - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ============================================================================================================================ - NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ============================================================================================================================ - - - 2. Enable and Configure the priority of the selected IRQ Channels. - -@note When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt, - the IRQ priority will be managed only by subpriority. - The sub-priority is only used to sort pending exception priorities, - and does not affect active exceptions. - -@note Lower priority values gives higher priority. - -@note Priority Order: - 1. Lowest Preemption priority - 2. Lowest Subpriority - 3. Lowest hardware priority (IRQn position) - -@endverbatim -*/ - -/** - * @brief Configures the priority grouping: pre-emption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @note When NVIC_PriorityGroup_0 is selected, it will no be any nested - * interrupt. This interrupts priority is managed only with subpriority. - * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ - SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; -} - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); - assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; - tmppre = (0x4 - tmppriority); - tmpsub = tmpsub >> tmppriority; - - tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; - tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; - tmppriority = tmppriority << 0x04; - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values: - * @arg NVIC_VectTab_RAM - * @arg NVIC_VectTab_FLASH - * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) -{ - /* Check the parameters */ - assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); - assert_param(IS_NVIC_OFFSET(Offset)); - - SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND - * @arg NVIC_LP_SLEEPDEEP - * @arg NVIC_LP_SLEEPONEXIT - * @param NewState: new state of LP condition. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Configures the SysTick clock source. - * @param SysTick_CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_adc.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_adc.c deleted file mode 100644 index fec303234..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_adc.c +++ /dev/null @@ -1,1803 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_adc.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) peripheral: - * - Initialization and Configuration - * - Power saving - * - Analog Watchdog configuration - * - Temperature Sensor & Vrefint (Voltage Reference internal) management - * - Regular Channels Configuration - * - Regular Channels DMA Configuration - * - Injected channels Configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * - Configure the ADC Prescaler, conversion resolution and data - * alignment using the ADC_Init() function. - * - Activate the ADC peripheral using ADC_Cmd() function. - * - * Regular channels group configuration - * ==================================== - * - To configure the ADC regular channels group features, use - * ADC_Init() and ADC_RegularChannelConfig() functions. - * - To activate the continuous mode, use the ADC_continuousModeCmd() - * function. - * - To configurate and activate the Discontinuous mode, use the - * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. - * - To read the ADC converted values, use the ADC_GetConversionValue() - * function. - * - * DMA for Regular channels group features configuration - * ====================================================== - * - To enable the DMA mode for regular channels group, use the - * ADC_DMACmd() function. - * - To enable the generation of DMA requests continuously at the end - * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() - * function. - - * Injected channels group configuration - * ===================================== - * - To configure the ADC Injected channels group features, use - * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() - * functions. - * - To activate the continuous mode, use the ADC_continuousModeCmd() - * function. - * - To activate the Injected Discontinuous mode, use the - * ADC_InjectedDiscModeCmd() function. - * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() - * function. - * - To read the ADC converted values, use the ADC_GetInjectedConversionValue() - * function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_adc.h" -#include "stm32l1xx_rcc.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ADC DISCNUM mask */ -#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) - -/* ADC AWDCH mask */ -#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF) - -/* CR1 register Mask */ -#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) - -/* ADC DELAY mask */ -#define CR2_DELS_RESET ((uint32_t)0xFFFFFF0F) - -/* ADC JEXTEN mask */ -#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC JEXTSEL mask */ -#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF) - -/* CR2 register Mask */ -#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD) - -/* ADC SQx mask */ -#define SQR5_SQ_SET ((uint32_t)0x0000001F) -#define SQR4_SQ_SET ((uint32_t)0x0000001F) -#define SQR3_SQ_SET ((uint32_t)0x0000001F) -#define SQR2_SQ_SET ((uint32_t)0x0000001F) -#define SQR1_SQ_SET ((uint32_t)0x0000001F) - -/* ADC L Mask */ -#define SQR1_L_RESET ((uint32_t)0xFE0FFFFF) - -/* ADC JSQx mask */ -#define JSQR_JSQ_SET ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define JSQR_JL_SET ((uint32_t)0x00300000) -#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SMPR1_SMP_SET ((uint32_t)0x00000007) -#define SMPR2_SMP_SET ((uint32_t)0x00000007) -#define SMPR3_SMP_SET ((uint32_t)0x00000007) - -/* ADC JDRx registers offset */ -#define JDR_OFFSET ((uint8_t)0x30) - -/* ADC CCR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0xFFFCFFFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** @defgroup ADC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to: - - Initialize and configure the ADC Prescaler - - ADC Conversion Resolution (12bit..6bit) - - Scan Conversion Mode (multichannels or one channel) for regular group - - ADC Continuous Conversion Mode (Continuous or Single conversion) for regular group - - External trigger Edge and source of regular group, - - Converted data alignment (left or right) - - The number of ADC conversions that will be done using the sequencer for regular channel group - - Enable or disable the ADC peripheral - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes ADC1 peripheral registers to their default reset values. - * @param None - * @retval None - */ -void ADC_DeInit(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Enable ADC1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); - /* Release ADC1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @note This function is used to configure the global features of the ADC ( - * Resolution and Data Alignment), however, the rest of the configuration - * parameters are specific to the regular channels group (scan mode - * activation, continuous mode activation, External trigger source and - * edge, number of conversion in the regular channels group sequencer). - * @param ADCx: where x can be 1 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); - assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion)); - - /*---------------------------- ADCx CR1 Configuration -----------------*/ - /* Get the ADCx CR1 value */ - tmpreg1 = ADCx->CR1; - /* Clear RES and SCAN bits */ - tmpreg1 &= CR1_CLEAR_MASK; - /* Configure ADCx: scan conversion mode and resolution */ - /* Set SCAN bit according to ADC_ScanConvMode value */ - /* Set RES bit according to ADC_Resolution value */ - tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | ADC_InitStruct->ADC_Resolution); - /* Write to ADCx CR1 */ - ADCx->CR1 = tmpreg1; - - /*---------------------------- ADCx CR2 Configuration -----------------*/ - /* Get the ADCx CR2 value */ - tmpreg1 = ADCx->CR2; - /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */ - tmpreg1 &= CR2_CLEAR_MASK; - /* Configure ADCx: external trigger event and edge, data alignment and continuous conversion mode */ - /* Set ALIGN bit according to ADC_DataAlign value */ - /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ - /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ - /* Set CONT bit according to ADC_ContinuousConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | - ADC_InitStruct->ADC_ExternalTrigConvEdge | ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - /* Write to ADCx CR2 */ - ADCx->CR2 = tmpreg1; - - /*---------------------------- ADCx SQR1 Configuration -----------------*/ - /* Get the ADCx SQR1 value */ - tmpreg1 = ADCx->SQR1; - /* Clear L bits */ - tmpreg1 &= SQR1_L_RESET; - /* Configure ADCx: regular channel sequence length */ - /* Set L bits according to ADC_NbrOfConversion value */ - tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1); - tmpreg1 |= ((uint32_t)tmpreg2 << 20); - /* Write to ADCx SQR1 */ - ADCx->SQR1 = tmpreg1; -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @note This function is used to initialize the global features of the ADC ( - * Resolution and Data Alignment), however, the rest of the configuration - * parameters are specific to the regular channels group (scan mode - * activation, continuous mode activation, External trigger source and - * edge, number of conversion in the regular channels group sequencer). - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Reset ADC init structure parameters values */ - /* Initialize the ADC_Resolution member */ - ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; - - /* Initialize the ADC_ScanConvMode member */ - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - - /* Initialize the ADC_ContinuousConvMode member */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - - /* Initialize the ADC_ExternalTrigConvEdge member */ - ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; - - /* Initialize the ADC_ExternalTrigConv member */ - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T2_CC2; - - /* Initialize the ADC_DataAlign member */ - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - - /* Initialize the ADC_NbrOfConversion member */ - ADC_InitStruct->ADC_NbrOfConversion = 1; -} - -/** - * @brief Initializes the ADCs peripherals according to the specified parameters - * in the ADC_CommonInitStruct. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * that contains the configuration information (Prescaler) for ADC1 peripheral. - * @retval None - */ -void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler)); - - /*---------------------------- ADC CCR Configuration -----------------*/ - /* Get the ADC CCR value */ - tmpreg = ADC->CCR; - - /* Clear ADCPRE bit */ - tmpreg &= CR_CLEAR_MASK; - - /* Configure ADCx: ADC prescaler according to ADC_Prescaler */ - tmpreg |= (uint32_t)(ADC_CommonInitStruct->ADC_Prescaler); - - /* Write to ADC CCR */ - ADC->CCR = tmpreg; -} - -/** - * @brief Fills each ADC_CommonInitStruct member with its default value. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * which will be initialized. - * @retval None - */ -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - /* Reset ADC init structure parameters values */ - /* Initialize the ADC_Prescaler member */ - ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div1; - -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the ADON bit to wake up the ADC from power down mode */ - ADCx->CR2 |= (uint32_t)ADC_CR2_ADON; - } - else - { - /* Disable the selected ADC peripheral */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON); - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group2 Power saving functions - * @brief Power saving functions - * -@verbatim - =============================================================================== - Power saving functions - =============================================================================== - - This section provides functions allowing to reduce power consumption. - The two function must be combined to get the maximal benefits: - When the ADC frequency is higher than the CPU one, it is recommended to - 1. Insert a freeze delay : - ==> using ADC_DelaySelectionConfig(ADC1, ADC_DelayLength_Freeze); - 2. Enable the power down in Idle and Delay phases : - ==> using ADC_PowerDownCmd(ADC1, ADC_PowerDown_Idle_Delay, ENABLE); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the ADC Power Down during Delay and/or Idle phase. - * @note ADC power-on and power-off can be managed by hardware to cut the - * consumption when the ADC is not converting. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_PowerDown: The ADC power down configuration. - * This parameter can be one of the following values: - * @arg ADC_PowerDown_Delay: ADC is powered down during delay phase - * @arg ADC_PowerDown_Idle: ADC is powered down during Idle phase - * @arg ADC_PowerDown_Idle_Delay: ADC is powered down during Delay and Idle phases - * @note The ADC can be powered down: - * - During the hardware delay insertion (using the ADC_PowerDown_Delay - * parameter) - * => The ADC is powered up again at the end of the delay. - * - During the ADC is waiting for a trigger event ( using the - * ADC_PowerDown_Idle parameter) - * => The ADC is powered up at the next trigger event. - * - During the hardware delay insertion or the ADC is waiting for a - * trigger event (using the ADC_PowerDown_Idle_Delay parameter) - * => The ADC is powered up only at the end of the delay and at the - * next trigger event. - * @param NewState: new state of the ADCx power down. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_POWER_DOWN(ADC_PowerDown)); - - if (NewState != DISABLE) - { - /* Enable the ADC power-down during Delay and/or Idle phase */ - ADCx->CR1 |= ADC_PowerDown; - } - else - { - /* Disable The ADC power-down during Delay and/or Idle phase */ - ADCx->CR1 &= (uint32_t)~ADC_PowerDown; - } -} - -/** - * @brief Defines the length of the delay which is applied after a conversion - * or a sequence of conversion. - * @note When the CPU clock is not fast enough to manage the data rate, a - * Hardware delay can be introduced between ADC conversions to reduce - * this data rate. - * @note The Hardware delay is inserted after : - * - each regular conversion - * - after each sequence of injected conversions - * @note No Hardware delay is inserted between conversions of different groups. - * @note When the hardware delay is not enough, the Freeze Delay Mode can be - * selected and a new conversion can start only if all the previous data - * of the same group have been treated: - * - for a regular conversion: once the ADC conversion data register has - * been read (using ADC_GetConversionValue() function) or if the EOC - * Flag has been cleared (using ADC_ClearFlag() function). - * - for an injected conversion: when the JEOC bit has been cleared - * (using ADC_ClearFlag() function). - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_DelayLength: The length of delay which is applied after a - * conversion or a sequence of conversion. - * This parameter can be one of the following values: - * @arg ADC_DelayLength_None: No delay - * @arg ADC_DelayLength_Freeze: Delay until the converted data has been read. - * @arg ADC_DelayLength_7Cycles: Delay length equal to 7 APB clock cycles - * @arg ADC_DelayLength_15Cycles: Delay length equal to 15 APB clock cycles - * @arg ADC_DelayLength_31Cycles: Delay length equal to 31 APB clock cycles - * @arg ADC_DelayLength_63Cycles: Delay length equal to 63 APB clock cycles - * @arg ADC_DelayLength_127Cycles: Delay length equal to 127 APB clock cycles - * @arg ADC_DelayLength_255Cycles: Delay length equal to 255 APB clock cycles - * @retval None - */ -void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_DELAY_LENGTH(ADC_DelayLength)); - - /* Get the old register value */ - tmpreg = ADCx->CR2; - /* Clear the old delay length */ - tmpreg &= CR2_DELS_RESET; - /* Set the delay length */ - tmpreg |= ADC_DelayLength; - /* Store the new register value */ - ADCx->CR2 = tmpreg; - -} - -/** - * @} - */ - -/** @defgroup ADC_Group3 Analog Watchdog configuration functions - * @brief Analog Watchdog configuration functions - * -@verbatim - =============================================================================== - Analog Watchdog configuration functions - =============================================================================== - - This section provides functions allowing to configure the Analog Watchdog - (AWD) feature in the ADC. - - A typical configuration Analog Watchdog is done following these steps : - 1. the ADC guarded channel(s) is (are) selected using the - ADC_AnalogWatchdogSingleChannelConfig() function. - 2. The Analog watchdog lower and higher threshold are configured using the - ADC_AnalogWatchdogThresholdsConfig() function. - 3. The Analog watchdog is enabled and configured to enable the check, on one - or more channels, using the ADC_AnalogWatchdogCmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the analog watchdog on single/all regular - * or injected channels - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single - * regular channel - * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single - * injected channel - * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a - * single regular or injected channel - * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular - * channel - * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected - * channel - * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all - * regular and injected channels - * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); - - /* Get the old register value */ - tmpreg = ADCx->CR1; - /* Clear AWDEN, JAWDEN and AWDSGL bits */ - tmpreg &= CR1_AWDMODE_RESET; - /* Set the analog watchdog enable mode */ - tmpreg |= ADC_AnalogWatchdog; - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - - /* Set the ADCx high threshold */ - ADCx->HTR = HighThreshold; - /* Set the ADCx low threshold */ - ADCx->LTR = LowThreshold; -} - -/** - * @brief Configures the analog watchdog guarded single channel - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @arg ADC_Channel_19: ADC Channel19 selected - * @arg ADC_Channel_20: ADC Channel20 selected - * @arg ADC_Channel_21: ADC Channel21 selected - * @arg ADC_Channel_22: ADC Channel22 selected - * @arg ADC_Channel_23: ADC Channel23 selected - * @arg ADC_Channel_24: ADC Channel24 selected - * @arg ADC_Channel_25: ADC Channel25 selected - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - - /* Get the old register value */ - tmpreg = ADCx->CR1; - /* Clear the Analog watchdog channel select bits */ - tmpreg &= CR1_AWDCH_RESET; - /* Set the Analog watchdog channel */ - tmpreg |= ADC_Channel; - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @} - */ - -/** @defgroup ADC_Group4 Temperature Sensor & Vrefint (Voltage Reference internal) management function - * @brief Temperature Sensor & Vrefint (Voltage Reference internal) management function - * -@verbatim - =============================================================================== - Temperature Sensor & Vrefint (Voltage Reference internal) management function - =============================================================================== - - This section provides a function allowing to enable/ disable the internal - connections between the ADC and the Temperature Sensor and the Vrefint source. - - A typical configuration to get the Temperature sensor and Vrefint channels - voltages or is done following these steps : - 1. Enable the internal connection of Temperature sensor and Vrefint sources - with the ADC channels using ADC_TempSensorVrefintCmd() function. - 2. select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using - ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions - 3. Get the voltage values, using ADC_GetConversionValue() or - ADC_GetInjectedConversionValue(). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the temperature sensor and Vrefint channel. - * @param NewState: new state of the temperature sensor and Vref int channels. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the temperature sensor and Vrefint channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; - } - else - { - /* Disable the temperature sensor and Vrefint channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group5 Regular Channels Configuration functions - * @brief Regular Channels Configuration functions - * -@verbatim - =============================================================================== - Regular Channels Configuration functions - =============================================================================== - - This section provides functions allowing to manage the ADC regular channels, - it is composed of 2 sub sections : - - 1. Configuration and management functions for regular channels: This subsection - provides functions allowing to configure the ADC regular channels : - - Configure the rank in the regular group sequencer for each channel - - Configure the sampling time for each channel - - select the conversion Trigger for regular channels - - select the desired EOC event behavior configuration - - Activate the continuous Mode (*) - - Activate the Discontinuous Mode - Please Note that the following features for regular channels are configurated - using the ADC_Init() function : - - scan mode activation - - continuous mode activation (**) - - External trigger source - - External trigger edge - - number of conversion in the regular channels group sequencer. - - @note : (*) and (**) are performing the same configuration - - 2. Get the conversion data: This subsection provides an important function in - the ADC peripheral since it returns the converted data of the current - regular channel. When the Conversion value is read, the EOC Flag is - automatically cleared. - -@endverbatim - * @{ - */ - -/** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sampling time. - * @param ADCx: where x can be 1 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @arg ADC_Channel_19: ADC Channel19 selected - * @arg ADC_Channel_20: ADC Channel20 selected - * @arg ADC_Channel_21: ADC Channel21 selected - * @arg ADC_Channel_22: ADC Channel22 selected - * @arg ADC_Channel_23: ADC Channel23 selected - * @arg ADC_Channel_24: ADC Channel24 selected - * @arg ADC_Channel_25: ADC Channel25 selected - * @param Rank: The rank in the regular group sequencer. This parameter - * must be between 1 to 26. - * @param ADC_SampleTime: The sample time value to be set for the selected - * channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles - * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles - * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles - * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles - * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles - * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles - * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles - * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles - * @retval None - */ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_REGULAR_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - - /* if ADC_Channel_20 ... ADC_Channel_25 is selected */ - if (ADC_Channel > ADC_Channel_19) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20)); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20)); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - - /* if ADC_Channel_10 ... ADC_Channel_19 is selected */ - else if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10)); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR3; - /* Calculate the mask to clear */ - tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR3 = tmpreg1; - } - /* For Rank 1 to 6 */ - if (Rank < 7) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR5; - /* Calculate the mask to clear */ - tmpreg2 = SQR5_SQ_SET << (5 * (Rank - 1)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR5 = tmpreg1; - } - /* For Rank 7 to 12 */ - else if (Rank < 13) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR4; - /* Calculate the mask to clear */ - tmpreg2 = SQR4_SQ_SET << (5 * (Rank - 7)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR4 = tmpreg1; - } - /* For Rank 13 to 18 */ - else if (Rank < 19) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR3; - /* Calculate the mask to clear */ - tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 13)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR3 = tmpreg1; - } - - /* For Rank 19 to 24 */ - else if (Rank < 25) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR2; - /* Calculate the mask to clear */ - tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 19)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 19)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR2 = tmpreg1; - } - - /* For Rank 25 to 27 */ - else - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR1; - /* Calculate the mask to clear */ - tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 25)); - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 25)); - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SQR1 = tmpreg1; - } -} - -/** - * @brief Enables the selected ADC software start conversion of the regular channels. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @retval None - */ -void ADC_SoftwareStartConv(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Enable the selected ADC conversion for regular group */ - ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART; -} - -/** - * @brief Gets the selected ADC Software start regular conversion Status. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @retval The new state of ADC software start conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of SWSTART bit */ - if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET) - { - /* SWSTART bit is set */ - bitstatus = SET; - } - else - { - /* SWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the SWSTART bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the EOC on each regular channel conversion - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the selected ADC EOC flag rising - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC EOC rising on each regular channel conversion */ - ADCx->CR2 |= ADC_CR2_EOCS; - } - else - { - /* Disable the selected ADC EOC rising on each regular channel conversion */ - ADCx->CR2 &= (uint32_t)~ADC_CR2_EOCS; - } -} - -/** - * @brief Enables or disables the ADC continuous conversion mode - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the selected ADC continuous conversion mode - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC continuous conversion mode */ - ADCx->CR2 |= (uint32_t)ADC_CR2_CONT; - } - else - { - /* Disable the selected ADC continuous conversion mode */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT); - } -} - -/** - * @brief Configures the discontinuous mode for the selected ADC regular - * group channel. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param Number: specifies the discontinuous mode regular channel count value. - * This number must be between 1 and 8. - * @retval None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); - - /* Get the old register value */ - tmpreg1 = ADCx->CR1; - /* Clear the old discontinuous mode channel count */ - tmpreg1 &= CR1_DISCNUM_RESET; - /* Set the discontinuous mode channel count */ - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - /* Store the new register value */ - ADCx->CR1 = tmpreg1; -} - -/** - * @brief Enables or disables the discontinuous mode on regular group - * channel for the specified ADC - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the selected ADC discontinuous mode on regular - * group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC regular discontinuous mode */ - ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN; - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN); - } -} - -/** - * @brief Returns the last ADCx conversion result data for regular channel. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @} - */ - -/** @defgroup ADC_Group6 Regular Channels DMA Configuration functions - * @brief Regular Channels DMA Configuration functions - * -@verbatim - =============================================================================== - Regular Channels DMA Configuration functions - =============================================================================== - - This section provides functions allowing to configure the DMA for ADC regular - channels. - Since converted regular channel values are stored into a unique data register, - it is useful to use DMA for conversion of more than one regular channel. This - avoids the loss of the data already stored in the ADC Data register. - - When the DMA mode is enabled (using the ADC_DMACmd() function), after each - conversion of a regular channel, a DMA request is generated. - - Depending on the "DMA disable selection" configuration (using the - ADC_DMARequestAfterLastTransferCmd() function), at the end of the last DMA - transfer, two possibilities are allowed: - - No new DMA request is issued to the DMA controller (feature DISABLED) - - Requests can continue to be generated (feature ENABLED). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_DMA_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CR2 |= (uint32_t)ADC_CR2_DMA; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA); - } -} - - -/** - * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the selected ADC EOC flag rising - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADCx->CR2 |= ADC_CR2_DDS; - } - else - { - /* Disable the selected ADC DMA request after last transfer */ - ADCx->CR2 &= (uint32_t)~ADC_CR2_DDS; - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group7 Injected channels Configuration functions - * @brief Injected channels Configuration functions - * -@verbatim - =============================================================================== - Injected channels Configuration functions - =============================================================================== - - This section provide functions allowing to configure the ADC Injected channels, - it is composed of 2 sub sections : - - 1. Configuration functions for Injected channels: This subsection provides - functions allowing to configure the ADC injected channels : - - Configure the rank in the injected group sequencer for each channel - - Configure the sampling time for each channel - - Activate the Auto injected Mode - - Activate the Discontinuous Mode - - scan mode activation - - External/software trigger source - - External trigger edge - - injected channels sequencer. - - 2. Get the Specified Injected channel conversion data: This subsection - provides an important function in the ADC peripheral since it returns the - converted data of the specific injected channel. - -@endverbatim - * @{ - */ - -/** - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @arg ADC_Channel_19: ADC Channel19 selected - * @arg ADC_Channel_20: ADC Channel20 selected - * @arg ADC_Channel_21: ADC Channel21 selected - * @arg ADC_Channel_22: ADC Channel22 selected - * @arg ADC_Channel_23: ADC Channel23 selected - * @arg ADC_Channel_24: ADC Channel24 selected - * @arg ADC_Channel_25: ADC Channel25 selected - * @param Rank: The rank in the injected group sequencer. This parameter - * must be between 1 to 4. - * @param ADC_SampleTime: The sample time value to be set for the selected - * channel. This parameter can be one of the following values: - * @arg ADC_SampleTime_4Cycles: Sample time equal to 4 cycles - * @arg ADC_SampleTime_9Cycles: Sample time equal to 9 cycles - * @arg ADC_SampleTime_16Cycles: Sample time equal to 16 cycles - * @arg ADC_SampleTime_24Cycles: Sample time equal to 24 cycles - * @arg ADC_SampleTime_48Cycles: Sample time equal to 48 cycles - * @arg ADC_SampleTime_96Cycles: Sample time equal to 96 cycles - * @arg ADC_SampleTime_192Cycles: Sample time equal to 192 cycles - * @arg ADC_SampleTime_384Cycles: Sample time equal to 384 cycles - * @retval None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_INJECTED_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - - /* if ADC_Channel_20 ... ADC_Channel_25 is selected */ - if (ADC_Channel > ADC_Channel_19) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 20)); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 20)); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - - /* if ADC_Channel_10 ... ADC_Channel_19 is selected */ - else if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_SET << (3 * (ADC_Channel - 10)); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR3; - /* Calculate the mask to clear */ - tmpreg2 = SMPR3_SMP_SET << (3 * ADC_Channel); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR3 = tmpreg1; - } - - /* Rank configuration */ - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Get JL value: Number = JL+1 */ - tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20; - /* Calculate the mask to clear: ((Rank-1)+(4- (JL+1))) */ - tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Clear the old JSQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set: ((Rank-1)+(4- (JL+1))) */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Set the JSQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Configures the sequencer length for injected channels - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param Length: The sequencer length. - * This parameter must be a number between 1 to 4. - * @retval None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_LENGTH(Length)); - - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Clear the old injected sequence length JL bits */ - tmpreg1 &= JSQR_JL_RESET; - /* Set the injected sequence length JL bits */ - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Set the injected channels conversion value offset - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_InjectedChannel: the ADC injected channel to set its offset. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @param Offset: the offset value for the selected ADC injected channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - assert_param(IS_ADC_OFFSET(Offset)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - /* Set the selected injected channel data offset */ - *(__IO uint32_t *) tmp = (uint32_t)Offset; -} - -/** - * @brief Configures the ADCx external trigger for injected channels conversion. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected - * conversion. This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConv_T9_CC1: Timer9 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T9_TRGO: Timer9 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected - * @arg ADC_ExternalTrigInjecConv_T10_CC1: Timer10 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T7_TRGO: Timer7 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected - * @retval None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); - - /* Get the old register value */ - tmpreg = ADCx->CR2; - /* Clear the old external event selection for injected group */ - tmpreg &= CR2_JEXTSEL_RESET; - /* Set the external event selection for injected group */ - tmpreg |= ADC_ExternalTrigInjecConv; - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Configures the ADCx external trigger edge for injected channels conversion. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger - * edge to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigConvEdge_None: external trigger disabled for - * injected conversion - * @arg ADC_ExternalTrigConvEdge_Rising: detection on rising edge - * @arg ADC_ExternalTrigConvEdge_Falling: detection on falling edge - * @arg ADC_External ADC_ExternalTrigConvEdge_RisingFalling: detection on - * both rising and falling edge - * @retval None - */ -void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge)); - - /* Get the old register value */ - tmpreg = ADCx->CR2; - /* Clear the old external trigger edge for injected group */ - tmpreg &= CR2_JEXTEN_RESET; - /* Set the new external trigger edge for injected group */ - tmpreg |= ADC_ExternalTrigInjecConvEdge; - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Enables the selected ADC software start conversion of the injected - * channels. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @retval None - */ -void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Enable the selected ADC conversion for injected group */ - ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART; -} - -/** - * @brief Gets the selected ADC Software start injected conversion Status. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @retval The new state of ADC software start injected conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of JSWSTART bit */ - if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) - { - /* JSWSTART bit is set */ - bitstatus = SET; - } - else - { - /* JSWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the JSWSTART bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the selected ADC auto injected - * conversion. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO); - } -} - -/** - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param NewState: new state of the selected ADC discontinuous mode - * on injected group channel. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN); - } -} - -/** - * @brief Returns the ADC injected channel conversion result - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_InjectedChannel: the converted ADC injected channel. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @retval The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + JDR_OFFSET; - - /* Returns the selected injected channel conversion data value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -/** - * @} - */ - -/** @defgroup ADC_Group8 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the ADC Interrupts and get - the status and clear flags and Interrupts pending bits. - - The ADC provide 4 Interrupts sources and 9 Flags which can be divided into 3 groups: - - I. Flags and Interrupts for ADC regular channels - ================================================= - Flags : - ---------- - 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost - - 2. ADC_FLAG_EOC : Regular channel end of conversion+ to indicate (depending - on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of : - ==> a regular CHANNEL conversion - ==> sequence of regular GROUP conversions . - - 3. ADC_FLAG_STRT: Regular channel start+ to indicate when regular CHANNEL - conversion starts. - - 4. ADC_FLAG_RCNR: Regular channel not ready+ to indicate if a new regular - conversion can be launched - - Interrupts : - ------------ - 1. ADC_IT_OVR - 2. ADC_IT_EOC - - - II. Flags and Interrupts for ADC Injected channels - ================================================= - Flags : - ---------- - 1. ADC_FLAG_JEOC : Injected channel end of conversion+ to indicate at - the end of injected GROUP conversion - - 2. ADC_FLAG_JSTRT: Injected channel start+ to indicate hardware when - injected GROUP conversion starts. - - 3. ADC_FLAG_JCNR: Injected channel not ready+ to indicate if a new - injected conversion can be launched. - - Interrupts : - ------------ - 1. ADC_IT_JEOC - - III. General Flags and Interrupts for the ADC - ================================================= - Flags : - ---------- - 1. ADC_FLAG_AWD: Analog watchdog+ to indicate if the converted voltage - crosses the programmed thresholds values. - - 2. ADC_FLAG_ADONS: ADC ON status+ to indicate if the ADC is ready to convert. - - Interrupts : - ------------ - 1. ADC_IT_AWD - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt - * @arg ADC_IT_AWD: Analog watchdog interrupt - * @arg ADC_IT_JEOC: End of injected conversion interrupt - * @arg ADC_IT_OVR: overrun interrupt - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint32_t itmask = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_IT(ADC_IT)); - - /* Get the ADC IT index */ - itmask = (uint8_t)ADC_IT; - itmask = (uint32_t)0x01 << itmask; - - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->CR1 |= itmask; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->CR1 &= (~(uint32_t)itmask); - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @arg ADC_FLAG_OVR: Overrun flag - * @arg ADC_FLAG_ADONS: ADC ON status - * @arg ADC_FLAG_RCNR: Regular channel not ready - * @arg ADC_FLAG_JCNR: Injected channel not ready - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - - /* Check the status of the specified ADC flag */ - if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @arg ADC_FLAG_OVR: overrun flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - - /* Clear the selected ADC flags */ - ADCx->SR = ~(uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt - * @arg ADC_IT_AWD: Analog watchdog interrupt - * @arg ADC_IT_JEOC: End of injected conversion interrupt - * @arg ADC_IT_OVR: Overrun interrupt - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - - /* Get the ADC IT index */ - itmask = (uint32_t)((uint32_t)ADC_IT >> 8); - - /* Get the ADC_IT enable bit status */ - enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)); - - /* Check the status of the specified ADC interrupt */ - if (((uint32_t)(ADCx->SR & (uint32_t)itmask) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - /* ADC_IT is set */ - bitstatus = SET; - } - else - { - /* ADC_IT is reset */ - bitstatus = RESET; - } - /* Return the ADC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the ADCxs interrupt pending bits. - * @param ADCx: where x can be 1 to select the ADC1 peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt - * @arg ADC_IT_AWD: Analog watchdog interrupt - * @arg ADC_IT_JEOC: End of injected conversion interrupt - * @arg ADC_IT_OVR: Overrun interrupt - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - - /* Get the ADC IT index */ - itmask = (uint8_t)(ADC_IT >> 8); - - /* Clear the selected ADC interrupt pending bits */ - ADCx->SR = ~(uint32_t)itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_comp.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_comp.c deleted file mode 100644 index 289a536aa..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_comp.c +++ /dev/null @@ -1,356 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_comp.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the comparators (COMP1 and COMP2) peripheral: - * - Comparators configuration - * - Window mode control - * - Internal Reference Voltage (VREFINT) output - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * The device integrates two analog comparators COMP1 and COMP2: - * - COMP1 is a fixed threshold (VREFINT) that shares the non inverting - * input with the ADC channels. - * - * - COMP2 is a rail-to-rail comparator whose the inverting input - * can be selected among: DAC_OUT1, DAC_OUT2, 1/4 VREFINT, - * 1/2 VERFINT, 3/4 VREFINT, VREFINT, PB3 and whose the output - * can be redirected to embedded timers: TIM2, TIM3, TIM4, TIM10 - * - * - The two comparators COMP1 and COMP2 can be combined in window - * mode. - * - * @note - * 1- Comparator APB clock must be enabled to get write access - * to comparator register using - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE); - * - * 2- COMP1 comparator and ADC can't be used at the same time since - * they share the same ADC switch matrix (analog switches). - * - * 3- When an I/O is used as comparator input, the corresponding GPIO - * registers should be configured in analog mode. - * - * 4- Comparators outputs (CMP1OUT and CMP2OUT) are not mapped on - * GPIO pin. They are only internal. - * To get the comparator output level, use COMP_GetOutputLevel() - * - * 5- COMP1 and COMP2 outputs are internally connected to EXTI Line 21 - * and EXTI Line 22 respectively. - * Interrupts can be used by configuring the EXTI Line using the - * EXTI peripheral driver. - * - * 6- After enabling the comparator (COMP1 or COMP2), user should wait - * for start-up time (tSTART) to get right output levels. - * Please refer to product datasheet for more information on tSTART. - * - * 7- Comparators cannot be used to exit the device from Sleep or Stop - * mode when the internal reference voltage is switched off using - * the PWR_UltraLowPowerCmd() function (ULP bit in the PWR_CR register). - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_comp.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup COMP - * @brief COMP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup COMP_Private_Functions - * @{ - */ - -/** @defgroup COMP_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes COMP peripheral registers to their default reset values. - * @param None - * @retval None - */ -void COMP_DeInit(void) -{ - COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP->CSR to reset value */ -} - -/** - * @brief Initializes the COMP2 peripheral according to the specified parameters - * in the COMP_InitStruct: - * - COMP_InvertingInput specify the inverting input of COMP2 - * - COMP_OutputSelect connect the output of COMP2 to selected timer - * input (Input capture / Output Compare Reference Clear) - * - COMP_Speed configures COMP2 speed for optimum speed/consumption ratio - * @note This function configures only COMP2. - * @note COMP2 comparator is enabled as soon as the INSEL[2:0] bits are - * different from "000". - * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains - * the configuration information for the specified COMP peripheral. - * @retval None - */ -void COMP_Init(COMP_InitTypeDef* COMP_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput)); - assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_OutputSelect)); - assert_param(IS_COMP_SPEED(COMP_InitStruct->COMP_Speed)); - - /*!< Get the COMP CSR value */ - tmpreg = COMP->CSR; - - /*!< Clear the INSEL[2:0], OUTSEL[1:0] and SPEED bits */ - tmpreg &= (uint32_t) (~(uint32_t) (COMP_CSR_OUTSEL | COMP_CSR_INSEL | COMP_CSR_SPEED)); - - /*!< Configure COMP: speed, inversion input selection and output redirection */ - /*!< Set SPEED bit according to COMP_InitStruct->COMP_Speed value */ - /*!< Set INSEL bits according to COMP_InitStruct->COMP_InvertingInput value */ - /*!< Set OUTSEL bits according to COMP_InitStruct->COMP_OutputSelect value */ - tmpreg |= (uint32_t)((COMP_InitStruct->COMP_Speed | COMP_InitStruct->COMP_InvertingInput - | COMP_InitStruct->COMP_OutputSelect)); - - /*!< The COMP2 comparator is enabled as soon as the INSEL[2:0] bits value are - different from "000" */ - /*!< Write to COMP_CSR register */ - COMP->CSR = tmpreg; -} - -/** - * @brief Enable or disable the COMP1 peripheral. - * After enabling COMP1, the following functions should be called to - * connect the selected GPIO input to COMP1 non inverting input: - * - Enable switch control mode using SYSCFG_RISwitchControlModeCmd() - * - Close VCOMP switch using SYSCFG_RIIOSwitchConfig() - * - Close the I/O switch number n corresponding to the I/O - * using SYSCFG_RIIOSwitchConfig() - * @param NewState: new state of the COMP1 peripheral. - * This parameter can be: ENABLE or DISABLE. - * @note This function enables/disables only the COMP1. - * @retval None - */ -void COMP_Cmd(FunctionalState NewState) -{ - /* Check the parameter */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the COMP1 */ - COMP->CSR |= (uint32_t) COMP_CSR_CMP1EN; - } - else - { - /* Disable the COMP1 */ - COMP->CSR &= (uint32_t)(~COMP_CSR_CMP1EN); - } -} - -/** - * @brief Return the output level (high or low) of the selected comparator: - * - Comparator output is low when the non-inverting input is at a lower - * voltage than the inverting input - * - Comparator output is high when the non-inverting input is at a higher - * voltage than the inverting input - * @note Comparators outputs aren't available on GPIO (outputs levels are - * only internal). The COMP1 and COMP2 outputs are connected internally - * to the EXTI Line 21 and Line 22 respectively. - * @param COMP_Selection: the selected comparator. - * This parameter can be one of the following values: - * @arg COMP_Selection_COMP1: COMP1 selected - * @arg COMP_Selection_COMP2: COMP2 selected - * @retval Returns the selected comparator output level. - */ -uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection) -{ - uint8_t compout = 0x0; - - /* Check the parameters */ - assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); - - /* Check if Comparator 1 is selected */ - if(COMP_Selection == COMP_Selection_COMP1) - { - /* Check if comparator 1 output level is high */ - if((COMP->CSR & COMP_CSR_CMP1OUT) != (uint8_t) RESET) - { - /* Get Comparator 1 output level */ - compout = (uint8_t) COMP_OutputLevel_High; - } - /* comparator 1 output level is low */ - else - { - /* Get Comparator 1 output level */ - compout = (uint8_t) COMP_OutputLevel_Low; - } - } - /* Comparator 2 is selected */ - else - { - /* Check if comparator 2 output level is high */ - if((COMP->CSR & COMP_CSR_CMP2OUT) != (uint8_t) RESET) - { - /* Get Comparator output level */ - compout = (uint8_t) COMP_OutputLevel_High; - } - /* comparator 2 output level is low */ - else - { - /* Get Comparator 2 output level */ - compout = (uint8_t) COMP_OutputLevel_Low; - } - } - /* Return the comparator output level */ - return (uint8_t)(compout); -} - -/** - * @} - */ - -/** @defgroup COMP_Group2 Window mode control function - * @brief Window mode control function - * -@verbatim - =============================================================================== - Window mode control function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the window mode. - * In window mode: - * - COMP1 inverting input is fixed to VREFINT defining the first - * threshold - * - COMP2 inverting input is configurable (DAC_OUT1, DAC_OUT2, VREFINT - * sub-multiples, PB3) defining the second threshold - * - COMP1 and COMP2 non inverting inputs are connected together. - * @note In window mode, only the Group 6 (PB4 or PB5) can be used as - * non-inverting inputs. - * param NewState: new state of the window mode. - * This parameter can be ENABLE or DISABLE. - * @retval None - */ -void COMP_WindowCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the window mode */ - COMP->CSR |= (uint32_t) COMP_CSR_WNDWE; - } - else - { - /* Disable the window mode */ - COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWE); - } -} - -/** - * @} - */ - -/** @defgroup COMP_Group3 Internal Reference Voltage output function - * @brief Internal Reference Voltage (VREFINT) output function - * -@verbatim - =============================================================================== - Internal Reference Voltage (VREFINT) output function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the output of internal reference voltage (VREFINT). - * The VREFINT output can be routed to any I/O in group 3: CH8 (PB0) or - * CH9 (PB1). - * To correctly use this function, the SYSCFG_RIIOSwitchConfig() function - * should be called after. - * @param NewState: new state of the Vrefint output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void COMP_VrefintOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the output of internal reference voltage */ - COMP->CSR |= (uint32_t) COMP_CSR_VREFOUTEN; - } - else - { - /* Disable the output of internal reference voltage */ - COMP->CSR &= (uint32_t) (~COMP_CSR_VREFOUTEN); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_crc.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_crc.c deleted file mode 100644 index 0a8836824..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_crc.c +++ /dev/null @@ -1,127 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_crc.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides all the CRC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_crc.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRC - * @brief CRC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRC_Private_Functions - * @{ - */ - -/** - * @brief Resets the CRC Data register (DR). - * @param None - * @retval None - */ -void CRC_ResetDR(void) -{ - /* Reset CRC generator */ - CRC->CR = CRC_CR_RESET; -} - -/** - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * @param Data: data word(32-bit) to compute its CRC - * @retval 32-bit CRC - */ -uint32_t CRC_CalcCRC(uint32_t Data) -{ - CRC->DR = Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed - * @retval 32-bit CRC - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DR = pBuffer[index]; - } - return (CRC->DR); -} - -/** - * @brief Returns the current CRC value. - * @param None - * @retval 32-bit CRC - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DR); -} - -/** - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param IDValue: 8-bit value to be stored in the ID register - * @retval None - */ -void CRC_SetIDRegister(uint8_t IDValue) -{ - CRC->IDR = IDValue; -} - -/** - * @brief Returns the 8-bit data stored in the Independent Data(ID) register - * @param None - * @retval 8-bit value of the ID register - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDR); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_dac.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_dac.c deleted file mode 100644 index dcc59c9b0..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_dac.c +++ /dev/null @@ -1,690 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_dac.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the Digital-to-Analog Converter (DAC) peripheral: - * - DAC channels configuration: trigger, output buffer, data format - * - DMA management - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * DAC Peripheral features - * =================================================================== - * The device integrates two 12-bit Digital Analog Converters that can - * be used independently or simultaneously (dual mode): - * 1- DAC channel1 with DAC_OUT1 (PA4) as output - * 1- DAC channel2 with DAC_OUT2 (PA5) as output - * - * Digital to Analog conversion can be non-triggered using DAC_Trigger_None - * and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using - * DAC_SetChannel1Data()/DAC_SetChannel2Data. - * - * Digital to Analog conversion can be triggered by: - * 1- External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. - * The used pin (GPIOx_Pin9) must be configured in input mode. - * - * 2- Timers TRGO: TIM2, TIM4, TIM6, TIM7 and TIM9 - * (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...) - * The timer TRGO event should be selected using TIM_SelectOutputTrigger() - * - * 3- Software using DAC_Trigger_Software - * - * Each DAC channel integrates an output buffer that can be used to - * reduce the output impedance, and to drive external loads directly - * without having to add an external operational amplifier. - * To enable, the output buffer use - * DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; - * - * Refer to the device datasheet for more details about output impedance - * value with and without output buffer. - * - * Both DAC channels can be used to generate - * 1- Noise wave using DAC_WaveGeneration_Noise - * 2- Triangle wave using DAC_WaveGeneration_Triangle - * - * Wave generation can be disabled using DAC_WaveGeneration_None - * - * The DAC data format can be: - * 1- 8-bit right alignment using DAC_Align_8b_R - * 2- 12-bit left alignment using DAC_Align_12b_L - * 3- 12-bit right alignment using DAC_Align_12b_R - * - * The analog output voltage on each DAC channel pin is determined - * by the following equation: DAC_OUTx = VREF+ * DOR / 4095 - * with DOR is the Data Output Register - * VEF+ is the input voltage reference (refer to the device datasheet) - * e.g. To set DAC_OUT1 to 0.7V, use - * DAC_SetChannel1Data(DAC_Align_12b_R, 868); - * Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V - * - * A DMA1 request can be generated when an external trigger (but not - * a software trigger) occurs if DMA1 requests are enabled using - * DAC_DMACmd() - * DMA1 requests are mapped as following: - * 1- DAC channel1 is mapped on DMA1 channel3 which must be already - * configured - * 2- DAC channel2 is mapped on DMA1 channel4 which must be already - * configured - * - * =================================================================== - * How to use this driver - * =================================================================== - * - DAC APB clock must be enabled to get write access to DAC - * registers using - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE) - * - Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. - * - Configure the DAC channel using DAC_Init() - * - Enable the DAC channel using DAC_Cmd() - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_dac.h" -#include "stm32l1xx_rcc.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* CR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) - -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) -#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) - -/* DHR registers offsets */ -#define DHR12R1_OFFSET ((uint32_t)0x00000008) -#define DHR12R2_OFFSET ((uint32_t)0x00000014) -#define DHR12RD_OFFSET ((uint32_t)0x00000020) - -/* DOR register offset */ -#define DOR_OFFSET ((uint32_t)0x0000002C) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** @defgroup DAC_Group1 DAC channels configuration - * @brief DAC channels configuration: trigger, output buffer, data format - * -@verbatim - =============================================================================== - DAC channels configuration: trigger, output buffer, data format - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void DAC_DeInit(void) -{ - /* Enable DAC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); - /* Release DAC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); -} - -/** - * @brief Initializes the DAC peripheral according to the specified - * parameters in the DAC_InitStruct. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that - * contains the configuration information for the specified DAC channel. - * DAC_Trigger selects the trigger source: EXTI Line 9, TIM2, TIM4.... - * DAC_WaveGeneration selects the waveform to be generated: noise, triangle - * DAC_LFSRUnmask_TriangleAmplitude - * defines the LFSR when noise waveform is selected by DAC_WaveGeneration - * or defines the amplitude of the triangle waveform when it is - * selected by DAC_WaveGeneration - * DAC_OutputBuffer enables/disables the output buffer on DAC_OUTx - * @retval None - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); - assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); - -/*---------------------------- DAC CR Configuration --------------------------*/ - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, wave generation, - mask/amplitude for wave generation */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set WAVEx bits according to DAC_WaveGeneration value */ - /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << DAC_Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; -} - -/** - * @brief Fills each DAC_InitStruct member with its default value. - * @param DAC_InitStruct : pointer to a DAC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) -{ -/*--------------- Reset DAC init structure parameters values -----------------*/ - /* Initialize the DAC_Trigger member */ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - /* Initialize the DAC_WaveGeneration member */ - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - /* Initialize the DAC_OutputBuffer member */ - DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -/** - * @brief Enables or disables the specified DAC channel. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @note When the DAC channel is enabled the trigger source can no more - * be modified. - * @retval None - */ -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel */ - DAC->CR |= (DAC_CR_EN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel */ - DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); - } -} - -/** - * @brief Enables or disables the selected DAC channel software trigger. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for the selected DAC channel */ - DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); - } - else - { - /* Disable software trigger for the selected DAC channel */ - DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enables or disables simultaneously the two DAC channels software - * triggers. - * @param NewState: new state of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for both DAC channels */ - DAC->SWTRIGR |= DUAL_SWTRIG_SET; - } - else - { - /* Disable software trigger for both DAC channels */ - DAC->SWTRIGR &= DUAL_SWTRIG_RESET; - } -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_Wave: Specifies the wave type to enable or disable. - * This parameter can be one of the following values: - * @arg DAC_Wave_Noise: noise wave generation - * @arg DAC_Wave_Triangle: triangle wave generation - * @param NewState: new state of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @note - * @retval None - */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_WAVE(DAC_Wave)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected wave generation for the selected DAC channel */ - DAC->CR |= DAC_Wave << DAC_Channel; - } - else - { - /* Disable the selected wave generation for the selected DAC channel */ - DAC->CR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: Specifies the data alignment for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data : Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R1_OFFSET + DAC_Align; - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Set the specified data holding register value for DAC channel2. - * @param DAC_Align: Specifies the data alignment for DAC channel2. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data : Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R2_OFFSET + DAC_Align; - - /* Set the DAC channel2 selected data holding register */ - *(__IO uint32_t *)tmp = Data; -} - -/** - * @brief Set the specified data holding register value for dual channel DAC. - * @param DAC_Align: Specifies the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data2: Data for DAC Channel2 to be loaded in the selected data - * holding register. - * @param Data1: Data for DAC Channel1 to be loaded in the selected data - * holding register. - * @note In dual mode, a unique register access is required to write in both - * DAC channels at the same time. - * @retval None - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12RD_OFFSET + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; -} - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - - tmp = (uint32_t) DAC_BASE ; - tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} - -/** - * @} - */ - -/** @defgroup DAC_Group2 DMA management functions - * @brief DMA management functions - * -@verbatim - =============================================================================== - DMA management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC channel DMA request. - * When enabled DMA1 is generated when an external trigger (EXTI Line9, - * TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which - * must be already configured. - * @retval None - */ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel DMA request */ - DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel DMA request */ - DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); - } -} - -/** - * @} - */ - -/** @defgroup DAC_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC interrupts. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before - * the acknowledgement for the first external trigger is received (first request). - * @param NewState: new state of the specified DAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_DAC_IT(DAC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC interrupts */ - DAC->CR |= (DAC_IT << DAC_Channel); - } - else - { - /* Disable the selected DAC interrupts */ - DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); - } -} - -/** - * @brief Checks whether the specified DAC flag is set or not. - * @param DAC_Channel: thee selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to check. - * This parameter can be only of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @note The DMA underrun occurs when a second external trigger arrives before - * the acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_FLAG (SET or RESET). - */ -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Check the status of the specified DAC flag */ - if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) - { - /* DAC_FLAG is set */ - bitstatus = SET; - } - else - { - /* DAC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DAC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's pending flags. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to clear. - * This parameter can be of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @retval None - */ -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Clear the selected DAC flags */ - DAC->SR = (DAC_FLAG << DAC_Channel); -} - -/** - * @brief Checks whether the specified DAC interrupt has occurred or not. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt source to check. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before - * the acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_IT (SET or RESET). - */ -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Get the DAC_IT enable bit status */ - enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; - - /* Check the status of the specified DAC interrupt */ - if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) - { - /* DAC_IT is set */ - bitstatus = SET; - } - else - { - /* DAC_IT is reset */ - bitstatus = RESET; - } - /* Return the DAC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channels interrupt pending bits. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt pending bit to clear. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @retval None - */ -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Clear the selected DAC interrupt pending bits */ - DAC->SR = (DAC_IT << DAC_Channel); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_dbgmcu.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_dbgmcu.c deleted file mode 100644 index f6b5712b0..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_dbgmcu.c +++ /dev/null @@ -1,170 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_dbgmcu.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides all the DBGMCU firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_dbgmcu.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DBGMCU - * @brief DBGMCU driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DBGMCU_Private_Functions - * @{ - */ - -/** - * @brief Returns the device revision identifier. - * @param None - * @retval Device revision identifier - */ -uint32_t DBGMCU_GetREVID(void) -{ - return(DBGMCU->IDCODE >> 16); -} - -/** - * @brief Returns the device identifier. - * @param None - * @retval Device identifier - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); -} - -/** - * @brief Configures low power mode behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the low power mode. - * This parameter can be any combination of the following values: - * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode - * @arg DBGMCU_STOP: Keep debugger connection during STOP mode - * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode - * @param NewState: new state of the specified low power mode in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->CR |= DBGMCU_Periph; - } - else - { - DBGMCU->CR &= ~DBGMCU_Periph; - } -} - - -/** - * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB1 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted - * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted - * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted - * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted - * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted - * @arg DBGMCU_RTC_STOP: RTC Wakeup counter stopped when Core is halted - * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted - * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted - * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is - * halted - * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is - * halted - * @param NewState: new state of the specified APB1 peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB1FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB1FZ &= ~DBGMCU_Periph; - } -} - -/** - * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB2 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted - * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted - * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted - * @param NewState: new state of the specified APB2 peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB2FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB2FZ &= ~DBGMCU_Periph; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_dma.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_dma.c deleted file mode 100644 index 749f6db49..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_dma.c +++ /dev/null @@ -1,752 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_dma.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access controller (DMA): - * - Initialization and Configuration - * - Data Counter - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The DMA controller clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) - * function for DMA1 or using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) - * function for DMA2. - * - * 2. Enable and configure the peripheral to be connected to the DMA channel - * (except for internal SRAM / FLASH memories: no initialization is - * necessary). - * - * 3. For a given Channel, program the Source and Destination addresses, - * the transfer Direction, the Buffer Size, the Peripheral and Memory - * Incrementation mode and Data Size, the Circular or Normal mode, - * the channel transfer Priority and the Memory-to-Memory transfer - * mode (if needed) using the DMA_Init() function. - * - * 4. Enable the NVIC and the corresponding interrupt(s) using the function - * DMA_ITConfig() if you need to use DMA interrupts. - * - * 5. Enable the DMA channel using the DMA_Cmd() function. - * - * 6. Activate the needed channel Request using PPP_DMACmd() function for - * any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) - * The function allowing this operation is provided in each PPP peripheral - * driver (ie. SPI_DMACmd for SPI peripheral). - * - * 7. Optionally, you can configure the number of data to be transferred - * when the channel is disabled (ie. after each Transfer Complete event - * or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). - * And you can get the number of remaining data to be transferred using - * the function DMA_GetCurrDataCounter() at run time (when the DMA channel is - * enabled and running). - * - * 8. To control DMA events you can use one of the following - * two methods: - * a- Check on DMA channel flags using the function DMA_GetFlagStatus(). - * b- Use DMA interrupts through the function DMA_ITConfig() at initialization - * phase and DMA_GetITStatus() function into interrupt routines in - * communication phase. - * After checking on a flag you should clear it using DMA_ClearFlag() - * function. And after checking on an interrupt event you should - * clear it using DMA_ClearITPendingBit() function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_dma.h" -#include "stm32l1xx_rcc.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* DMA1 Channelx interrupt pending bit masks */ -#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) -#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) -#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) -#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) -#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) -#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) -#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) - -/* DMA FLAG mask */ -#define FLAG_MASK ((uint32_t)0x10000000) - -/* DMA registers Masks */ -#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/** @defgroup DMA_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This subsection provides functions allowing to initialize the DMA channel source - and destination addresses, incrementation and data sizes, transfer direction, - buffer size, circular/normal mode selection, memory-to-memory mode selection - and channel priority value. - - The DMA_Init() function follows the DMA configuration procedures as described in - reference manual (RM0038). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DMAy Channelx registers to their default reset - * values. - * @param DMAy_Channelx: where y can be 1 to select the DMA and - * x can be 1 to 7 for DMA1 to select the DMA Channel. - * @retval None - */ -void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); - - /* Reset DMAy Channelx control register */ - DMAy_Channelx->CCR = 0; - - /* Reset DMAy Channelx remaining bytes register */ - DMAy_Channelx->CNDTR = 0; - - /* Reset DMAy Channelx peripheral address register */ - DMAy_Channelx->CPAR = 0; - - /* Reset DMAy Channelx memory address register */ - DMAy_Channelx->CMAR = 0; - - if (DMAy_Channelx == DMA1_Channel1) - { - /* Reset interrupt pending bits for DMA1 Channel1 */ - DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel2) - { - /* Reset interrupt pending bits for DMA1 Channel2 */ - DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel3) - { - /* Reset interrupt pending bits for DMA1 Channel3 */ - DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel4) - { - /* Reset interrupt pending bits for DMA1 Channel4 */ - DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel5) - { - /* Reset interrupt pending bits for DMA1 Channel5 */ - DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK; - } - else if (DMAy_Channelx == DMA1_Channel6) - { - /* Reset interrupt pending bits for DMA1 Channel6 */ - DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK; - } - else - { - if (DMAy_Channelx == DMA1_Channel7) - { - /* Reset interrupt pending bits for DMA1 Channel7 */ - DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK; - } - } -} - -/** - * @brief Initializes the DMAy Channelx according to the specified - * parameters in the DMA_InitStruct. - * @param DMAy_Channelx: where y can be 1 to select the DMA and - * x can be 1 to 7 for DMA1 to select the DMA Channel. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that - * contains the configuration information for the specified DMA Channel. - * @retval None - */ -void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); - assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); - assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); - assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); - assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); - -/*--------------------------- DMAy Channelx CCR Configuration -----------------*/ - /* Get the DMAy_Channelx CCR value */ - tmpreg = DMAy_Channelx->CCR; - /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmpreg &= CCR_CLEAR_MASK; - /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ - /* Set DIR bit according to DMA_DIR value */ - /* Set CIRC bit according to DMA_Mode value */ - /* Set PINC bit according to DMA_PeripheralInc value */ - /* Set MINC bit according to DMA_MemoryInc value */ - /* Set PSIZE bits according to DMA_PeripheralDataSize value */ - /* Set MSIZE bits according to DMA_MemoryDataSize value */ - /* Set PL bits according to DMA_Priority value */ - /* Set the MEM2MEM bit according to DMA_M2M value */ - tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; - - /* Write to DMAy Channelx CCR */ - DMAy_Channelx->CCR = tmpreg; - -/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; - -/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ - /* Write to DMAy Channelx CPAR */ - DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; - -/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ - /* Write to DMAy Channelx CMAR */ - DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ -/*-------------- Reset DMA init structure parameters values ------------------*/ - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - /* Initialize the DMA_MemoryBaseAddr member */ - DMA_InitStruct->DMA_MemoryBaseAddr = 0; - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - /* Initialize the DMA_MemoryInc member */ - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - /* Initialize the DMA_Priority member */ - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - /* Initialize the DMA_M2M member */ - DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; -} - -/** - * @brief Enables or disables the specified DMAy Channelx. - * @param DMAy_Channelx: where y can be 1 to select the DMA and - * x can be 1 to 7 for DMA1 to select the DMA Channel. - * @param NewState: new state of the DMAy Channelx. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMAy Channelx */ - DMAy_Channelx->CCR |= DMA_CCR1_EN; - } - else - { - /* Disable the selected DMAy Channelx */ - DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); - } -} - -/** - * @} - */ - -/** @defgroup DMA_Group2 Data Counter functions - * @brief Data Counter functions - * -@verbatim - =============================================================================== - Data Counter functions - =============================================================================== - - This subsection provides function allowing to configure and read the buffer size - (number of data to be transferred). - - The DMA data counter can be written only when the DMA channel is disabled - (ie. after transfer complete event). - - The following function can be used to write the Channel data counter value: - - void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); - -@note It is advised to use this function rather than DMA_Init() in situations where - only the Data buffer needs to be reloaded. - - The DMA data counter can be read to indicate the number of remaining transfers for - the relative DMA channel. This counter is decremented at the end of each data - transfer and when the transfer is complete: - - If Normal mode is selected: the counter is set to 0. - - If Circular mode is selected: the counter is reloaded with the initial value - (configured before enabling the DMA channel) - - The following function can be used to read the Channel data counter value: - - uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); - -@endverbatim - * @{ - */ - -/** - * @brief Sets the number of data units in the current DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 to select the DMA and - * x can be 1 to 7 for DMA1 to select the DMA Channel. - * @param DataNumber: The number of data units in the current DMAy Channelx - * transfer. - * @note This function can only be used when the DMAy_Channelx is disabled. - * @retval None. - */ -void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - -/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ - /* Write to DMAy Channelx CNDTR */ - DMAy_Channelx->CNDTR = DataNumber; -} - -/** - * @brief Returns the number of remaining data units in the current - * DMAy Channelx transfer. - * @param DMAy_Channelx: where y can be 1 to select the DMA and - * x can be 1 to 7 for DMA1 to select the DMA Channel. - * @retval The number of remaining data units in the current DMAy Channelx - * transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - /* Return the number of remaining data units for DMAy Channelx */ - return ((uint16_t)(DMAy_Channelx->CNDTR)); -} - -/** - * @} - */ - -/** @defgroup DMA_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This subsection provides functions allowing to configure the DMA Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage the - DMA controller events: Polling mode or Interrupt mode. - - Polling Mode - ============= - Each DMA channel can be managed through 4 event Flags: - (y : DMA Controller number - x : DMA channel number ) - 1. DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred - 2. DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occured - 3. DMAy_FLAG_TEx : to indicate that a Transfer Error occured. - 4. DMAy_FLAG_GLx : to indicate that at least one of the events described - above occured. - -@note Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the - same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). - - In this Mode it is advised to use the following functions: - - FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); - - void DMA_ClearFlag(uint32_t DMA_FLAG); - - Interrupt Mode - =============== - Each DMA channel can be managed through 4 Interrupts: - - Interrupt Source - ---------------- - 1. DMA_IT_TC: specifies the interrupt source for the Transfer Complete event. - 2. DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete event. - 3. DMA_IT_TE : specifies the interrupt source for the transfer errors event. - 4. DMA_IT_GL : to indicate that at least one of the interrupts described - above occurred. - -@note Clearing DMA_IT_GL interrupt results in clearing all other interrupts of the - same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE). - - In this Mode it is advised to use the following functions: - - void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); - - ITStatus DMA_GetITStatus(uint32_t DMA_IT); - - void DMA_ClearITPendingBit(uint32_t DMA_IT); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DMAy Channelx interrupts. - * @param DMAy_Channelx: where y can be 1 to select the DMA and - * x can be 1 to 7 for DMA1 to select the DMA Channel. - * @param DMA_IT: specifies the DMA interrupts sources to be enabled - * or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @param NewState: new state of the specified DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); - assert_param(IS_DMA_CONFIG_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMA interrupts */ - DMAy_Channelx->CCR |= DMA_IT; - } - else - { - /* Disable the selected DMA interrupts */ - DMAy_Channelx->CCR &= ~DMA_IT; - } -} - -/** - * @brief Checks whether the specified DMAy Channelx flag is set or not. - * @param DMA_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * - * @note - * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags - * relative to the same channel is set (Transfer Complete, Half-transfer - * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or - * DMAy_FLAG_TEx). - * - * @retval The new state of DMA_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); - - /* Calculate the used DMA */ - if ((DMA_FLAG & FLAG_MASK) == (uint32_t)RESET) - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR ; - } - - /* Check the status of the specified DMA flag */ - if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) - { - /* DMA_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMA_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the DMA_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelx's pending flags. - * @param DMA_FLAG: specifies the flag to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. - * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. - * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. - * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. - * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. - * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. - * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. - * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. - * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. - * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. - * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. - * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. - * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. - * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. - * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. - * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. - * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. - * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. - * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. - * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. - * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. - * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. - * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. - * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. - * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. - * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. - * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. - * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. - * - * @note - * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags - * relative to the same channel (Transfer Complete, Half-transfer Complete and - * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). - * - * @retval None - */ -void DMA_ClearFlag(uint32_t DMA_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); - - if ((DMA_FLAG & FLAG_MASK) == (uint32_t)RESET) - { - /* Clear the selected DMA flags */ - DMA1->IFCR = DMA_FLAG; - } -} - -/** - * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. - * @param DMA_IT: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. - * - * @note - * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other - * interrupts relative to the same channel is set (Transfer Complete, - * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, - * DMAy_IT_HTx or DMAy_IT_TEx). - * - * @retval The new state of DMA_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(uint32_t DMA_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_GET_IT(DMA_IT)); - - /* Calculate the used DMA */ - if ((DMA_IT & FLAG_MASK) == (uint32_t)RESET) - { - /* Get DMA1 ISR register value */ - tmpreg = DMA1->ISR ; - } - - /* Check the status of the specified DMA interrupt */ - if ((tmpreg & DMA_IT) != (uint32_t)RESET) - { - /* DMA_IT is set */ - bitstatus = SET; - } - else - { - /* DMA_IT is reset */ - bitstatus = RESET; - } - /* Return the DMA_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Channelxs interrupt pending bits. - * @param DMA_IT: specifies the DMA interrupt pending bit to clear. - * This parameter can be any combination (for the same DMA) of the following values: - * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. - * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. - * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. - * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. - * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. - * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. - * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. - * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. - * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. - * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. - * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. - * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. - * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. - * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. - * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. - * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. - * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. - * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. - * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. - * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. - * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. - * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. - * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. - * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. - * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. - * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. - * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. - * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. - * - * @note - * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other - * interrupts relative to the same channel (Transfer Complete, Half-transfer - * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and - * DMAy_IT_TEx). - * - * @retval None - */ -void DMA_ClearITPendingBit(uint32_t DMA_IT) -{ - /* Check the parameters */ - assert_param(IS_DMA_CLEAR_IT(DMA_IT)); - - /* Calculate the used DMA */ - if ((DMA_IT & FLAG_MASK) == (uint32_t)RESET) - { - /* Clear the selected DMA interrupt pending bits */ - DMA1->IFCR = DMA_IT; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_exti.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_exti.c deleted file mode 100644 index 008f62e8f..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_exti.c +++ /dev/null @@ -1,313 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_exti.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the EXTI peripheral: - * - Initialization and Configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * EXTI features - * =================================================================== - * - * External interrupt/event lines are mapped as following: - * 1- All available GPIO pins are connected to the 16 external - * interrupt/event lines from EXTI0 to EXTI15. - * 2- EXTI line 16 is connected to the PVD output - * 3- EXTI line 17 is connected to the RTC Alarm event - * 4- EXTI line 18 is connected to the USB Device FS wakeup event - * 5- EXTI line 19 is connected to the RTC Tamper and TimeStamp events - * 6- EXTI line 20 is connected to the RTC Wakeup event - * 7- EXTI line 21 is connected to the Comparator 1 wakeup event - * 8- EXTI line 22 is connected to the Comparator 2 wakeup event - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * In order to use an I/O pin as an external interrupt source, follow - * steps below: - * 1- Configure the I/O in input mode using GPIO_Init() - * 2- Select the input source pin for the EXTI line using - * SYSCFG_EXTILineConfig() - * 3- Select the mode(interrupt, event) and configure the trigger - * selection (Rising, falling or both) using EXTI_Init() - * 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init() - * - *@note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx - * registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_exti.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** @defgroup EXTI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - EXTI->IMR = 0x00000000; - EXTI->EMR = 0x00000000; - EXTI->RTSR = 0x00000000; - EXTI->FTSR = 0x00000000; - EXTI->PR = 0x007FFFFF; -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * EXTI_Line specifies the EXTI line (EXTI0....EXTI22) - * EXTI_Mode specifies which EXTI line is used as interrupt or an event - * EXTI_Trigger selects the trigger. When the trigger occurs, interrupt - * pending bit will be set - * EXTI_LineCmd controls (Enable/Disable) the EXTI line - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - - tmp = (uint32_t)EXTI_BASE; - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; - - tmp += EXTI_InitStruct->EXTI_Mode; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; - - /* Select the trigger for the selected external interrupts */ - if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - /* Rising Falling edge */ - EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - - /* Disable the selected external lines */ - *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param EXTI_Line: specifies the EXTI line on which the software interrupt - * will be generated. - * This parameter can be any combination of EXTI_Linex where x can be (0..22). - * @retval None - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->SWIER |= EXTI_Line; -} - -/** - * @} - */ - -/** @defgroup EXTI_Group2 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param EXTI_Line: specifies the EXTI line flag to check. - * This parameter can be: - * @arg EXTI_Linex: External interrupt line x where x(0..22) - * @retval The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTIs line pending flags. - * @param EXTI_Line: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..22). - * @retval None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_Line: specifies the EXTI line to check. - * This parameter can be: - * @arg EXTI_Linex: External interrupt line x where x(0..22) - * @retval The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - enablestatus = EXTI->IMR & EXTI_Line; - if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTIs line pending bits. - * @param EXTI_Line: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..22). - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_flash.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_flash.c deleted file mode 100644 index 2fa60a7bc..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_flash.c +++ /dev/null @@ -1,1335 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_flash.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides all the Flash firmware functions. These functions - * can be executed from Internal FLASH or Internal SRAM memories. - * The functions that should be called from SRAM are defined inside - * the "stm32l1xx_flash_ramfunc.c" file. - * This file provides firmware functions to manage the following - * functionalities of the FLASH peripheral: - * - FLASH Interface configuration - * - FLASH Memory Programming - * - DATA EEPROM Programming - * - Option Bytes Programming - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * This driver provides functions to configure and program the Flash - * memory of all STM32L1xx devices - * These functions are split in 5 groups - * - * 1. FLASH Interface configuration functions: this group includes - * the management of following features: - * - Set the latency - * - Enable/Disable the prefetch buffer - * - Enable/Disable the 64 bit Read Access - * - Enable/Disable the RUN PowerDown mode - * - Enable/Disable the SLEEP PowerDown mode - * - * 2. FLASH Memory Programming functions: this group includes all - * needed functions to erase and program the main memory: - * - Lock and Unlock the Flash interface. - * - Erase function: Erase Page. - * - Program functions: Fast Word and Half Page(should be - * executed from internal SRAM). - * - * 3. DATA EEPROM Programming functions: this group includes all - * needed functions to erase and program the DATA EEPROM memory: - * - Lock and Unlock the DATA EEPROM interface. - * - Erase function: Erase Word, erase Double Word (should be - * executed from internal SRAM). - * - Program functions: Fast Program Byte, Fast Program Half-Word, - * FastProgramWord, Program Byte, Program Half-Word, - * Program Word and Program Double-Word (should be executed - * from internal SRAM). - * - * 4. FLASH Option Bytes Programming functions: this group includes - * all needed functions to: - * - Lock and Unlock the Flash Option bytes. - * - Set/Reset the write protection - * - Set the Read protection Level - * - Set the BOR level - * - Program the user option Bytes - * - Launch the Option Bytes loader - * - Get the Write protection - * - Get the read protection status - * - Get the BOR level - * - Get the user option bytes - * - * 5. FLASH Interrupts and flag management functions: this group - * includes all needed functions to: - * - Enable/Disable the flash interrupt sources - * - Get flags status - * - Clear flags - * - Get Flash operation status - * - Wait for last flash operation - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_flash.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* FLASH Mask */ -#define RDPRT_MASK ((uint32_t)0x00000002) -#define WRP01_MASK ((uint32_t)0x0000FFFF) -#define WRP23_MASK ((uint32_t)0xFFFF0000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** @defgroup FLASH_Group1 FLASH Interface configuration functions - * @brief FLASH Interface configuration functions - * -@verbatim - =============================================================================== - FLASH Interface configuration functions - =============================================================================== - - FLASH_Interface configuration_Functions, includes the following functions: - - void FLASH_SetLatency(uint32_t FLASH_Latency): - To correctly read data from Flash memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. - ---------------------------------------------------------------- - | Wait states | HCLK clock frequency (MHz) | - | |------------------------------------------------| - | (Latency) | voltage range | voltage range | - | | 1.65 V - 3.6 V | 2.0 V - 3.6 V | - | |----------------|---------------|---------------| - | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V | - |-------------- |----------------|---------------|---------------| - |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 | - |---------------|----------------|---------------|---------------| - |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| - ---------------------------------------------------------------- - - - void FLASH_PrefetchBufferCmd(FunctionalState NewState); - - void FLASH_ReadAccess64Cmd(FunctionalState NewState); - - void FLASH_RUNPowerDownCmd(FunctionalState NewState); - - void FLASH_SLEEPPowerDownCmd(FunctionalState NewState); - - void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); - - Here below the allowed configuration of Latency, 64Bit access and prefetch buffer - -------------------------------------------------------------------------------- - | | ACC64 = 0 | ACC64 = 1 | - | Latency |----------------|---------------|---------------|---------------| - | | PRFTEN = 0 | PRFTEN = 1 | PRFTEN = 0 | PRFTEN = 1 | - |---------------|----------------|---------------|---------------|---------------| - |0WS(1CPU cycle)| YES | NO | YES | YES | - |---------------|----------------|---------------|---------------|---------------| - |1WS(2CPU cycle)| NO | NO | YES | YES | - -------------------------------------------------------------------------------- - All these functions don't need the unlock sequence. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the code latency value. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Read the ACR register */ - tmpreg = FLASH->ACR; - - /* Sets the Latency value */ - tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY)); - tmpreg |= FLASH_Latency; - - /* Write the ACR register */ - FLASH->ACR = tmpreg; -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @param NewState: new state of the FLASH prefetch buffer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_PrefetchBufferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_PRFTEN; - } - else - { - FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTEN)); - } -} - -/** - * @brief Enables or disables read access to flash by 64 bits. - * @param NewState: new state of the FLASH read access mode. - * This parameter can be: ENABLE or DISABLE. - * @note - If this bit is set, the Read access 64 bit is used. - * - If this bit is reset, the Read access 32 bit is used. - * @note - This bit cannot be written at the same time as the LATENCY and - * PRFTEN bits. - * - To reset this bit, the LATENCY should be zero wait state and the - * prefetch off. - * @retval None - */ -void FLASH_ReadAccess64Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_ACC64; - } - else - { - FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_ACC64)); - } -} - -/** - * @brief Enable or disable the power down mode during Sleep mode. - * @note This function is used to power down the FLASH when the system is in SLEEP LP mode. - * @param NewState: new state of the power down mode during sleep mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_SLEEPPowerDownCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the SLEEP_PD bit to put Flash in power down mode during sleep mode */ - FLASH->ACR |= FLASH_ACR_SLEEP_PD; - } - else - { - /* Clear the SLEEP_PD bit in to put Flash in idle mode during sleep mode */ - FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_SLEEP_PD)); - } -} - -/** - * @} - */ - -/** @defgroup FLASH_Group2 FLASH Memory Programming functions - * @brief FLASH Memory Programming functions - * -@verbatim - =============================================================================== - FLASH Memory Programming functions - =============================================================================== - - The FLASH Memory Programming functions, includes the following functions: - - void FLASH_Unlock(void); - - void FLASH_Lock(void); - - FLASH_Status FLASH_ErasePage(uint32_t Page_Address); - - FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data); - - Any operation of erase or program should follow these steps: - - 1. Call the FLASH_Unlock() function to enable the flash control register and - program memory access - - 2. Call the desired function to erase page or program data - - 3. Call the FLASH_Lock() to disable the flash program memory access - (recommended to protect the FLASH memory against possible unwanted operation) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the FLASH control register and program memory access. - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - if((FLASH->PECR & FLASH_PECR_PRGLOCK) != RESET) - { - /* Unlocking the data memory and FLASH_PECR register access */ - DATA_EEPROM_Unlock(); - - /* Unlocking the program memory access */ - FLASH->PRGKEYR = FLASH_PRGKEY1; - FLASH->PRGKEYR = FLASH_PRGKEY2; - } -} - -/** - * @brief Locks the Program memory access. - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the PRGLOCK Bit to lock the program memory access */ - FLASH->PECR |= FLASH_PECR_PRGLOCK; -} - -/** - * @brief Erases a specified page in program memory. - * @note - To correctly run this function, the FLASH_Unlock() function - * must be called before. - * - Call the FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param Page_Address: The page address in program memory to be erased. - * @note A Page is erased in the Program memory only if the address to load - * is the start address of a page (multiple of 256 bytes). - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_ErasePage(uint32_t Page_Address) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to erase the page */ - - /* Set the ERASE bit */ - FLASH->PECR |= FLASH_PECR_ERASE; - - /* Set PROG bit */ - FLASH->PECR |= FLASH_PECR_PROG; - - /* Write 00000000h to the first word of the program page to erase */ - *(__IO uint32_t *)Page_Address = 0x00000000; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* If the erase operation is completed, disable the ERASE and PROG bits */ - FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG); - FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE); - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Programs a word at a specified address in program memory. - * @note - To correctly run this function, the FLASH_Unlock() function - * must be called before. - * - Call the FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to program the new word */ - *(__IO uint32_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - /* Return the Write Status */ - return status; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group3 DATA EEPROM Programming functions - * @brief DATA EEPROM Programming functions - * -@verbatim - =============================================================================== - DATA EEPROM Programming functions - =============================================================================== - - The DATA_EEPROM Programming_Functions, includes the following functions: - - void DATA_EEPROM_Unlock(void); - - void DATA_EEPROM_Lock(void); - - FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address); - - FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data); - - FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data); - - FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data); - - FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data); - - FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data); - - FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data); - - Any operation of erase or program should follow these steps: - - 1. Call the DATA_EEPROM_Unlock() function to enable the data EEPROM access - and Flash program erase control register access. - - 2. Call the desired function to erase or program data - - 3. Call the DATA_EEPROM_Lock() to disable the data EEPROM access - and Flash program erase control register access(recommended - to protect the DATA_EEPROM against possible unwanted operation) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the data memory and FLASH_PECR register access. - * @param None - * @retval None - */ -void DATA_EEPROM_Unlock(void) -{ - if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) - { - /* Unlocking the Data memory and FLASH_PECR register access*/ - FLASH->PEKEYR = FLASH_PEKEY1; - FLASH->PEKEYR = FLASH_PEKEY2; - } -} - -/** - * @brief Locks the Data memory and FLASH_PECR register access. - * @param None - * @retval None - */ -void DATA_EEPROM_Lock(void) -{ - /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */ - FLASH->PECR |= FLASH_PECR_PELOCK; -} - -/** - * @brief Enables or disables DATA EEPROM fixed Time programming (2*Tprog). - * @param NewState: new state of the DATA EEPROM fixed Time programming mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->PECR |= (uint32_t)FLASH_PECR_FTDW; - } - else - { - FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW)); - } -} - -/** - * @brief Erase a word in data memory. - * @param Address: specifies the address to be erased - * @note1 - A data memory word is erased in the data memory only if the address - * to load is the start address of a word (multiple of a word). - * @note2 - To correctly run this function, the DATA_EEPROM_Unlock() function - * must be called before. - * - Call the DATA_EEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation) - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Write "00000000h" to valid address in the data memory" */ - *(__IO uint32_t *) Address = 0x00000000; - } - - /* Return the erase status */ - return status; -} - -/** - * @brief Write a Byte at a specified address in data memory. - * @note - To correctly run this function, the DATA_EEPROM_Unlock() function - * must be called before. - * - Call the DATA_EEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation) - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @note This function assumes that the is data word is already erased. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t tmp = 0, tmpaddr = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Clear the FTDW bit */ - FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW)); - - if(Data != (uint8_t)0x00) - { - /* If the previous operation is completed, proceed to write the new Data */ - *(__IO uint8_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - else - { - tmpaddr = Address & 0xFFFFFFFC; - tmp = * (__IO uint32_t *) tmpaddr; - tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3))); - tmp &= ~tmpaddr; - status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC); - status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); - } - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Writes a half word at a specified address in data memory. - * @note - To correctly run this function, the DATA_EEPROM_Unlock() function - * must be called before. - * - Call the DATA_EEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation) - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @note This function assumes that the is data word is already erased. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t tmp = 0, tmpaddr = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Clear the FTDW bit */ - FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW)); - - if(Data != (uint16_t)0x0000) - { - /* If the previous operation is completed, proceed to write the new data */ - *(__IO uint16_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - else - { - if((Address & 0x3) != 0x3) - { - tmpaddr = Address & 0xFFFFFFFC; - tmp = * (__IO uint32_t *) tmpaddr; - tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3))); - tmp &= ~tmpaddr; - status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC); - status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); - } - else - { - DATA_EEPROM_FastProgramByte(Address, 0x00); - DATA_EEPROM_FastProgramByte(Address + 1, 0x00); - } - } - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Programs a word at a specified address in data memory. - * @note - To correctly run this function, the DATA_EEPROM_Unlock() function - * must be called before. - * - Call the DATA_EEPROM_Lock() to the data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation) - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @note This function assumes that the is data word is already erased. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Clear the FTDW bit */ - FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW)); - - /* If the previous operation is completed, proceed to program the new data */ - *(__IO uint32_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Write a Byte at a specified address in data memory without erase. - * @note - To correctly run this function, the DATA_EEPROM_Unlock() function - * must be called before. - * - Call the DATA_EEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation) - * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before - * this function to configure the Fixed Time Programming. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t tmp = 0, tmpaddr = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - if(Data != (uint8_t) 0x00) - { - *(__IO uint8_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - } - else - { - tmpaddr = Address & 0xFFFFFFFC; - tmp = * (__IO uint32_t *) tmpaddr; - tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3))); - tmp &= ~tmpaddr; - status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC); - status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); - } - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Writes a half word at a specified address in data memory without erase. - * @note - To correctly run this function, the DATA_EEPROM_Unlock() function - * must be called before. - * - Call the DATA_EEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation) - * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before - * this function to configure the Fixed Time Programming - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t tmp = 0, tmpaddr = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - if(Data != (uint16_t)0x0000) - { - *(__IO uint16_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - else - { - if((Address & 0x3) != 0x3) - { - tmpaddr = Address & 0xFFFFFFFC; - tmp = * (__IO uint32_t *) tmpaddr; - tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3))); - tmp &= ~tmpaddr; - status = DATA_EEPROM_EraseWord(Address & 0xFFFFFFFC); - status = DATA_EEPROM_FastProgramWord((Address & 0xFFFFFFFC), tmp); - } - else - { - DATA_EEPROM_FastProgramByte(Address, 0x00); - DATA_EEPROM_FastProgramByte(Address + 1, 0x00); - } - } - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Programs a word at a specified address in data memory without erase. - * @note - To correctly run this function, the DATA_EEPROM_Unlock() function - * must be called before. - * - Call the DATA_EEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation) - * @note The function DATA_EEPROM_FixedTimeProgramCmd() can be called before - * this function to configure the Fixed Time Programming. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - *(__IO uint32_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - /* Return the Write Status */ - return status; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group4 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - =============================================================================== - Option Bytes Programming functions - =============================================================================== - - The FLASH_Option Bytes Programming_functions, includes the following functions: - - void FLASH_OB_Unlock(void); - - void FLASH_OB_Lock(void); - - void FLASH_OB_Launch(void); - - FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); - - FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP); - - FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); - - FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR); - - uint8_t FLASH_OB_GetUser(void); - - uint32_t FLASH_OB_GetWRP(void); - - FlagStatus FLASH_OB_GetRDP(void); - - uint8_t FLASH_OB_GetBOR(void); - - Any operation of erase or program should follow these steps: - - 1. Call the FLASH_OB_Unlock() function to enable the Flash option control register access - - 2. Call one or several functions to program the desired option bytes - - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable - the desired sector write protection - - void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level - - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure - the user option Bytes: IWDG, STOP and the Standby. - - void FLASH_OB_BORConfig(uint8_t OB_BOR) => to Set the BOR level - - FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) => to program the OTP bytes - - 3. Once all needed option bytes to be programmed are correctly written, call the - FLASH_OB_Launch(void) function to launch the Option Bytes programming process. - - 4. Call the FLASH_OB_Lock() to disable the Flash option control register access (recommended - to protect the option Bytes against possible unwanted operations) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the option bytes block access. - * @param None - * @retval None - */ -void FLASH_OB_Unlock(void) -{ - if((FLASH->PECR & FLASH_PECR_OPTLOCK) != RESET) - { - /* Unlocking the data memory and FLASH_PECR register access */ - DATA_EEPROM_Unlock(); - - /* Unlocking the option bytes block access */ - FLASH->OPTKEYR = FLASH_OPTKEY1; - FLASH->OPTKEYR = FLASH_OPTKEY2; - } -} - -/** - * @brief Locks the option bytes block access. - * @param None - * @retval None - */ -void FLASH_OB_Lock(void) -{ - /* Set the OPTLOCK Bit to lock the option bytes block access */ - FLASH->PECR |= FLASH_PECR_OPTLOCK; -} - -/** - * @brief Launch the option byte loading. - * @param None - * @retval None - */ -void FLASH_OB_Launch(void) -{ - /* Set the OBL_Launch bit to lauch the option byte loading */ - FLASH->PECR |= FLASH_PECR_OBL_LAUNCH; -} - -/** - * @brief Write protects the desired pages - * @note - To correctly run this function, the FLASH_OB_Unlock() function - * must be called before. - * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param OB_WRP: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg value between OB_WRP_Pages0to15 and OB_WRP_Pages496to511 - * @arg OB_WRP_AllPages - * @param NewState: new state of the specified FLASH Pages Wtite protection. - * This parameter can be: ENABLE or DISABLE. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) -{ - uint32_t WRP01_Data = 0, WRP23_Data = 0; - - FLASH_Status status = FLASH_COMPLETE; - uint32_t tmp1 = 0, tmp2 = 0; - - /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - if (NewState != DISABLE) - { - WRP01_Data = (uint16_t)(((OB_WRP & WRP01_MASK) | OB->WRP01)); - WRP23_Data = (uint16_t)((((OB_WRP & WRP23_MASK)>>16 | OB->WRP23))); - tmp1 = (uint32_t)(~(WRP01_Data) << 16)|(WRP01_Data); - OB->WRP01 = tmp1; - - tmp2 = (uint32_t)(~(WRP23_Data) << 16)|(WRP23_Data); - OB->WRP23 = tmp2; - } - - else - { - WRP01_Data = (uint16_t)(~OB_WRP & (WRP01_MASK & OB->WRP01)); - WRP23_Data = (uint16_t)((((~OB_WRP & WRP23_MASK)>>16 & OB->WRP23))); - - tmp1 = (uint32_t)((~WRP01_Data) << 16)|(WRP01_Data); - OB->WRP01 = tmp1; - - tmp2 = (uint32_t)((~WRP23_Data) << 16)|(WRP23_Data); - OB->WRP23 = tmp2; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - } - - /* Return the write protection operation Status */ - return status; -} - -/** - * @brief Enables or disables the read out protection. - * @note - To correctly run this function, the FLASH_OB_Unlock() function - * must be called before. - * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param FLASH_ReadProtection_Level: specifies the read protection level. - * This parameter can be: - * @arg OB_RDP_Level_0: No protection - * @arg OB_RDP_Level_1: Read protection of the memory - * @arg OB_RDP_Level_2: Chip protection - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) -{ - FLASH_Status status = FLASH_COMPLETE; - uint8_t tmp1 = 0; - uint32_t tmp2 = 0; - - /* Check the parameters */ - assert_param(IS_OB_RDP(OB_RDP)); - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* calculate the option byte to write */ - tmp1 = (uint8_t)(~(OB_RDP )); - tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)OB_RDP)); - - if(status == FLASH_COMPLETE) - { - /* program read protection level */ - OB->RDP = tmp2; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Return the Read protection operation Status */ - return status; -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @note - To correctly run this function, the FLASH_OB_Unlock() function - * must be called before. - * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param OB_IWDG: Selects the WDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software WDG selected - * @arg OB_IWDG_HW: Hardware WDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t tmp = 0, tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Get the User Option byte register */ - tmp1 = (FLASH->OBR & 0x000F0000) >> 16; - - /* Calculate the user option byte to write */ - tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << ((uint32_t)0x10)); - tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Write the User Option Byte */ - OB->USER = tmp; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Programs the FLASH brownout reset threshold level Option Byte. - * @note - To correctly run this function, the FLASH_OB_Unlock() function - * must be called before. - * - Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes - * (recommended to protect the FLASH memory against possible unwanted operation) - * @param OB_BOR: Selects the brownout reset threshold level - * This parameter can be one of the following values: - * @arg OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD - * power supply reaches the PDR(Power Down Reset) threshold (1.5V) - * @arg OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply - * @arg OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply - * @arg OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply - * @arg OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply - * @arg OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR) -{ - FLASH_Status status = FLASH_COMPLETE; - uint32_t tmp = 0, tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_OB_BOR_LEVEL(OB_BOR)); - - /* Get the User Option byte register */ - tmp1 = (FLASH->OBR & 0x00700000) >> 16; - - /* Calculate the option byte to write */ - tmp = (uint32_t)~(OB_BOR | tmp1)<<16; - tmp |= (OB_BOR | tmp1); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* Write the BOR Option Byte */ - OB->USER = tmp; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* Return the Option Byte program Status */ - return status; -} - -/** - * @brief Returns the FLASH User Option Bytes values. - * @param None - * @retval The FLASH User Option Bytes . - */ -uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return (uint8_t)(FLASH->OBR >> 20); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes value. - * @param None - * @retval The FLASH Write Protection Option Bytes value - */ -uint32_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return (uint32_t)(FLASH->WRPR); -} - -/** - * @brief Checks whether the FLASH Read out Protection Status is set or not. - * @param None - * @retval FLASH ReadOut Protection Status(SET or RESET) - */ -FlagStatus FLASH_OB_GetRDP(void) -{ - FlagStatus readstatus = RESET; - - if ((uint8_t)(FLASH->OBR) != (uint8_t)OB_RDP_Level_0) - { - readstatus = SET; - } - else - { - readstatus = RESET; - } - return readstatus; -} - -/** - * @brief Returns the FLASH BOR level. - * @param None - * @retval The FLASH User Option Bytes . - */ -uint8_t FLASH_OB_GetBOR(void) -{ - /* Return the BOR level */ - return (uint8_t)((FLASH->OBR & (uint32_t)0x000F0000) >> 16); -} - -/** - * @} - */ - -/** @defgroup FLASH_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FLASH interrupts. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or - * disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: FLASH end of programming Interrupt - * @arg FLASH_IT_ERR: FLASH Error Interrupt - * @retval None - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->PECR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->PECR &= ~(uint32_t)FLASH_IT; - } -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode - * @arg FLASH_FLAG_ENDHV: FLASH End of high voltage flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH size error flag - * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); - - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASHs pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH size error flag - * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag - * @retval None - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -} - -/** - * @brief Returns the FLASH Status. - * @param None - * @retval FLASH Status: The returned value can be: - * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status FLASHstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - FLASHstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00) - { - FLASHstatus = FLASH_ERROR_WRP; - } - else - { - if((FLASH->SR & (uint32_t)0xFEF0) != (uint32_t)0x00) - { - FLASHstatus = FLASH_ERROR_PROGRAM; - } - else - { - FLASHstatus = FLASH_COMPLETE; - } - } - } - /* Return the FLASH Status */ - return FLASHstatus; -} - - -/** - * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur. - * @param Timeout: FLASH programming Timeout - * @retval FLASH Status: The returned value can be: FLASH_BUSY, - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the FLASH Status */ - status = FLASH_GetStatus(); - - /* Wait for a FLASH operation to complete or a TIMEOUT to occur */ - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = FLASH_GetStatus(); - Timeout--; - } - - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - - /** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_flash_ramfunc.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_flash_ramfunc.c deleted file mode 100644 index aefaf96c4..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_flash_ramfunc.c +++ /dev/null @@ -1,385 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_flash_ramfunc.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides all the Flash firmware functions which should be - * executed from the internal SRAM. This file should be placed in - * internal SRAM. - * Other FLASH memory functions that can be used from the FLASH are - * defined in the "stm32l1xx_flash.c" file. - * @verbatim - * - * ARM Compiler - * ------------ - * RAM functions are defined using the toolchain options. - * Functions that are be executed in RAM should reside in a separate - * source module. Using the 'Options for File' dialog you can simply change - * the 'Code / Const' area of a module to a memory space in physical RAM. - * Available memory areas are declared in the 'Target' tab of the - * 'Options for Target' dialog. - * - * ICCARM Compiler - * --------------- - * RAM functions are defined using a specific toolchain keyword "__ramfunc". - * - * GNU Compiler - * ------------ - * RAM functions are defined using a specific toolchain attribute - * "__attribute__((section(".data")))". - * - * TASKING Compiler - * ---------------- - * RAM functions are defined using a specific toolchain pragma. This - * pragma is defined inside this file. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_flash.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static __RAM_FUNC GetStatus(void); -static __RAM_FUNC WaitForLastOperation(uint32_t Timeout); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** @addtogroup FLASH_Group1 - * -@verbatim -@endverbatim - * @{ - */ -#if defined ( __TASKING__ ) -#pragma section_code_init on -#endif - -/** - * @brief Enable or disable the power down mode during RUN mode. - * @note: This function can be used only when the user code is running from Internal SRAM - * @param NewState: new state of the power down mode during RUN mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -__RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - if (NewState != DISABLE) - { - /* Unlock the RUN_PD bit */ - FLASH->PDKEYR = FLASH_PDKEY1; - FLASH->PDKEYR = FLASH_PDKEY2; - - /* Set the RUN_PD bit in FLASH_ACR register to put Flash in power down mode */ - FLASH->ACR |= (uint32_t)FLASH_ACR_RUN_PD; - - if((FLASH->ACR & FLASH_ACR_RUN_PD) != FLASH_ACR_RUN_PD) - { - status = FLASH_ERROR_PROGRAM; - } - } - else - { - /* Clear the RUN_PD bit in FLASH_ACR register to put Flash in idle mode */ - FLASH->ACR &= (uint32_t)(~(uint32_t)FLASH_ACR_RUN_PD); - } - - /* Return the Write Status */ - return status; -} - -/** - * @} - */ - -/** @addtogroup FLASH_Group2 - * -@verbatim -@endverbatim - * @{ - */ - -/** - * @brief Programs a half page in program memory. - * @param Address: specifies the address to be written. - * @param pBuffer: pointer to the buffer containing the data to be written to - * the half page. - * @note - To correctly run this function, the FLASH_Unlock() function - * must be called before. - * - Call the FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @note Half page write is possible only from SRAM. - * @note If there are more than 32 words to write, after 32 words another - * Half Page programming operation starts and has to be finished. - * @note A half page is written to the program memory only if the first - * address to load is the start address of a half page (multiple of 128 - * bytes) and the 31 remaining words to load are in the same half page. - * @note During the Program memory half page write all read operations are - * forbidden (this includes DMA read operations and debugger read - * operations such as breakpoints, periodic updates, etc.) - * @note If a PGAERR is set during a Program memory half page write, the - * complete write operation is aborted. Software should then reset the - * FPRG and PROG/DATA bits and restart the write operation from the - * beginning. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -__RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer) -{ - uint32_t count = 0; - - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new - half page */ - FLASH->PECR |= FLASH_PECR_FPRG; - FLASH->PECR |= FLASH_PECR_PROG; - - /* Write one half page directly with 32 different words */ - while(count < 32) - { - *(__IO uint32_t*) (Address + (4 * count)) = *(pBuffer++); - count ++; - } - /* Wait for last operation to be completed */ - status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* if the write operation is completed, disable the PROG and FPRG bits */ - FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG); - FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG); - } - /* Return the Write Status */ - return status; -} - -/** - * @} - */ - -/** @addtogroup FLASH_Group3 - * -@verbatim -@endverbatim - * @{ - */ - -/** - * @brief Erase a double word in data memory. - * @param Address: specifies the address to be erased - * @note - To correctly run this function, the DATA_EEPROM_Unlock() function - * must be called before. - * - Call the DATA_EEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation) - * @note Data memory double word erase is possible only from SRAM. - * @note A double word is erased to the data memory only if the first address - * to load is the start address of a double word (multiple of 8 bytes) - * @note During the Data memory double word erase, all read operations are - * forbidden (this includes DMA read operations and debugger read - * operations such as breakpoints, periodic updates, etc.) - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ - -__RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to erase the next double word */ - /* Set the ERASE bit */ - FLASH->PECR |= FLASH_PECR_ERASE; - - /* Set DATA bit */ - FLASH->PECR |= FLASH_PECR_DATA; - - /* Write 00000000h to the 2 words to erase */ - *(__IO uint64_t *)Address = 0x00000000; - - /* Wait for last operation to be completed */ - status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* If the erase operation is completed, disable the ERASE and DATA bits */ - FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE); - FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA); - } - /* Return the erase status */ - return status; -} - -/** - * @brief Write a double word in data memory without erase. - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @note - To correctly run this function, the DATA_EEPROM_Unlock() function - * must be called before. - * - Call the DATA_EEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation) - * @note Data memory double word write is possible only from SRAM. - * @note A data memory double word is written to the data memory only if the - * first address to load is the start address of a double word (multiple - * of double word). - * @note During the Data memory double word write, all read operations are - * forbidden (this includes DMA read operations and debugger read - * operations such as breakpoints, periodic updates, etc.) - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -__RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - if(status == FLASH_COMPLETE) - { - /* If the previous operation is completed, proceed to program the new data*/ - FLASH->PECR |= FLASH_PECR_FPRG; - FLASH->PECR |= FLASH_PECR_DATA; - - /* Write the 2 words */ - *(__IO uint32_t *)Address = (uint32_t) Data; - Address += 4; - *(__IO uint32_t *)Address = (uint32_t) (Data >> 32); - - /* Wait for last operation to be completed */ - status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); - - /* If the write operation is completed, disable the FPRG and DATA bits */ - FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG); - FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA); - } - /* Return the Write Status */ - return status; -} - -/** - * @} - */ - -/** - * @brief Returns the FLASH Status. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE - */ -static __RAM_FUNC GetStatus(void) -{ - FLASH_Status FLASHstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - FLASHstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00) - { - FLASHstatus = FLASH_ERROR_WRP; - } - else - { - if((FLASH->SR & (uint32_t)0xFEF0) != (uint32_t)0x00) - { - FLASHstatus = FLASH_ERROR_PROGRAM; - } - else - { - FLASHstatus = FLASH_COMPLETE; - } - } - } - /* Return the FLASH Status */ - return FLASHstatus; -} - -/** - * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur. - * @param Timeout: FLASH programming Timeout - * @retval FLASH Status: The returned value can be: FLASH_BUSY, - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or - * FLASH_TIMEOUT. - */ -static __RAM_FUNC WaitForLastOperation(uint32_t Timeout) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check for the FLASH Status */ - status = GetStatus(); - - /* Wait for a FLASH operation to complete or a TIMEOUT to occur */ - while((status == FLASH_BUSY) && (Timeout != 0x00)) - { - status = GetStatus(); - Timeout--; - } - - if(Timeout == 0x00 ) - { - status = FLASH_TIMEOUT; - } - /* Return the operation status */ - return status; -} - -#if defined ( __TASKING__ ) -#pragma section_code_init restore -#endif - -/** - * @} - */ - - /** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_gpio.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_gpio.c deleted file mode 100644 index ad2db4fe0..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_gpio.c +++ /dev/null @@ -1,546 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_gpio.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the GPIO peripheral: - * - Initialization and Configuration - * - GPIO Read and Write - * - GPIO Alternate functions configuration - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd() - * - * 2. Configure the GPIO pin(s) using GPIO_Init() - * Four possible configuration are available for each pin: - * - Input: Floating, Pull-up, Pull-down. - * - Output: Push-Pull (Pull-up, Pull-down or no Pull) - * Open Drain (Pull-up, Pull-down or no Pull). - * In output mode, the speed is configurable: Very Low, Low, - * Medium or High. - * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) - * Open Drain (Pull-up, Pull-down or no Pull). - * - Analog: required mode when a pin is to be used as ADC channel, - * DAC output or comparator input. - * - * 3- Peripherals alternate function: - * - For ADC, DAC and comparators, configure the desired pin in - * analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN - * - For other peripherals (TIM, USART...): - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function mode using - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() - * - * 5. To set/reset the level of a pin configured in output mode use - * GPIO_SetBits()/GPIO_ResetBits() - * - * 6. During and just after reset, the alternate functions are not - * active and the GPIO pins are configured in input floating mode - * (except JTAG pins). - * - * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as - * general-purpose (PC14 and PC15, respectively) when the LSE - * oscillator is off. The LSE has priority over the GPIO function. - * - * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as - * general-purpose PH0 and PH1, respectively, when the HSE - * oscillator is off. The HSE has priority over the GPIO function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_gpio.h" -#include "stm32l1xx_rcc.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** @defgroup GPIO_Group1 Initialization and Configuration - * @brief Initialization and Configuration - * -@verbatim - =============================================================================== - Initialization and Configuration - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the GPIOx peripheral registers to their default reset - * values. - * By default, The GPIO pins are configured in input floating mode - * (except JTAG pins). - * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if(GPIOx == GPIOA) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE); - } - else if(GPIOx == GPIOB) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE); - } - else if(GPIOx == GPIOC) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE); - } - else if(GPIOx == GPIOD) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE); - } - else if(GPIOx == GPIOE) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE); - } - else - { - if(GPIOx == GPIOH) - { - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, ENABLE); - RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, DISABLE); - } - } -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified - * parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that - * contains the configuration information for the specified GPIO - * peripheral. - * GPIO_Pin: selects the pin to be configured: GPIO_Pin_0 -> GPIO_Pin_15 - * GPIO_Mode: selects the mode of the pin: - * - Input mode: GPIO_Mode_IN - * - Output mode: GPIO_Mode_OUT - * - Alternate Function mode: GPIO_Mode_AF - * - Analog mode: GPIO_Mode_AN - * GPIO_Speed: selects the speed of the pin if configured in Output: - * - Very Low: GPIO_Speed_400KHz - * - Low: GPIO_Speed_2MHz - * - Medium: GPIO_Speed_10MHz - * - High: GPIO_Speed_40MHz - * GPIO_OType: selects the Output type (if the selected mode is output): - * - Push-pull: GPIO_OType_PP - * - Open Drain: GPIO_OType_OD - * GPIO_PuPd: configures the Pull-up/Pull-down resistor on the pin: - * - pull-up: GPIO_PuPd_UP - * - pull-down: GPIO_PuPd_DOWN - * - Neither pull-up nor Pull-down: GPIO_PuPd_NOPULL - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); - - /* -------------------------Configure the port pins---------------- */ - /*-- GPIO Mode Configuration --*/ - for (pinpos = 0x00; pinpos < 0x10; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if (currentpin == pos) - { - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); - - GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); - - if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) - { - /* Check Speed mode parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - - /* Speed mode configuration */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); - GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); - - /*Check Output mode parameters */ - assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); - - /* Output mode configuration */ - GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; - GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); - } - - /* Pull-up Pull down resistor configuration */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); - GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); - } - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_400KHz; - GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * The configuration of the locked GPIO pins can no longer be modified - * until the next reset. - * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group2 GPIO Read and Write - * @brief GPIO Read and Write - * -@verbatim - =============================================================================== - GPIO Read and Write - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO input data port. - * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. - * @retval GPIO input data port value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. - * @param GPIO_Pin: Specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRL = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRH = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enum values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRRL = GPIO_Pin; - } - else - { - GPIOx->BSRRH = GPIO_Pin ; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. - * @param PortVal: specifies the value to be written to the port output data - * register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions - * @brief GPIO Alternate functions configuration functions - * -@verbatim - =============================================================================== - GPIO Alternate functions configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Changes the mapping of the specified pin. - * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. - * @param GPIO_PinSource: specifies the pin for the Alternate function. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @param GPIO_AFSelection: selects the pin to used as Alternat function. - * This parameter can be one of the following values: - * @arg GPIO_AF_RTC_50Hz: RTC 50/60 Hz synchronization - * @arg GPIO_AF_MCO: Microcontroller clock output - * @arg GPIO_AF_RTC_AF1: Time stamp, Tamper, Alarm A out, Alarm B out, - * 512 Hz clock output (with an LSE oscillator of 32.768 kHz) - * @arg GPIO_AF_WKUP: wakeup - * @arg GPIO_AF_SWJ: SWJ (SW and JTAG) - * @arg GPIO_AF_TRACE - * @arg GPIO_AF_TIM2 - * @arg GPIO_AF_TIM3 - * @arg GPIO_AF_TIM4 - * @arg GPIO_AF_TIM9 - * @arg GPIO_AF_TIM10 - * @arg GPIO_AF_TIM11 - * @arg GPIO_AF_I2C1 - * @arg GPIO_AF_I2C2 - * @arg GPIO_AF_SPI1 - * @arg GPIO_AF_SPI2 - * @arg GPIO_AF_USART1 - * @arg GPIO_AF_USART2 - * @arg GPIO_AF_USART3 - * @arg GPIO_AF_USB - * @arg GPIO_AF_LCD - * @arg GPIO_AF_RI - * @arg GPIO_AF_EVENTOUT: Cortex-M3 EVENTOUT signal - * @note: The pin should already been configured in Alternate Function mode(AF) - * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * @note: Please refer to the Alternate function mapping table in the device - * datasheet for the detailed mapping of the system and peripherals - * alternate function I/O pins. - * @note: EVENTOUT is not mapped on PH0, PH1 and PH2. - * @retval None - */ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) -{ - uint32_t temp = 0x00; - uint32_t temp_2 = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - assert_param(IS_GPIO_AF(GPIO_AF)); - - temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; - GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_i2c.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_i2c.c deleted file mode 100644 index 763fe88b7..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_i2c.c +++ /dev/null @@ -1,1333 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_i2c.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the Inter-integrated circuit (I2C) - * - Initialization and Configuration - * - Data transfers - * - PEC management - * - DMA transfers management - * - Interrupts, events and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE) - * function for I2C1 or I2C2. - * - * 2. Enable SDA, SCL and SMBA (when used) GPIO clocks using - * RCC_AHBPeriphClockCmd() function. - * - * 3. Peripherals alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged - * Address using the I2C_Init() function. - * - * 5. Optionally you can enable/configure the following parameters without - * re-initialization (i.e there is no need to call again I2C_Init() function): - * - Enable the acknowledge feature using I2C_AcknowledgeConfig() function - * - Enable the dual addressing mode using I2C_DualAddressCmd() function - * - Enable the general call using the I2C_GeneralCallCmd() function - * - Enable the clock stretching using I2C_StretchClockCmd() function - * - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig() - * function - * - Enable the PEC Calculation using I2C_CalculatePEC() function - * - For SMBus Mode: - * - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function - * - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function - * - * 6. Enable the NVIC and the corresponding interrupt using the function - * I2C_ITConfig() if you need to use interrupt mode. - * - * 7. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using I2C_DMACmd() or - I2C_DMALastTransferCmd() function - * - * 8. Enable the I2C using the I2C_Cmd() function. - * - * 9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the - * transfers. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_i2c.h" -#include "stm32l1xx_rcc.h" - - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed)); - assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); - assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); - assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); - assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); - -/*---------------------------- I2Cx CR2 Configuration ------------------------*/ - /* Get the I2Cx CR2 value */ - tmpreg = I2Cx->CR2; - /* Clear frequency FREQ[5:0] bits */ - tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ); - /* Get pclk1 frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - /* Set frequency bits depending on pclk1 value */ - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - /* Write to I2Cx CR2 */ - I2Cx->CR2 = tmpreg; - -/*---------------------------- I2Cx CCR Configuration ------------------------*/ - /* Disable the selected I2C peripheral to configure TRISE */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); - /* Reset tmpreg value */ - /* Clear F/S, DUTY and CCR[11:0] bits */ - tmpreg = 0; - - /* Configure speed in standard mode */ - if (I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - /* Standard mode speed calculate */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - /* Test if CCR value is under 0x4*/ - if (result < 0x04) - { - /* Set minimum allowed value */ - result = 0x04; - } - /* Set speed value for standard mode */ - tmpreg |= result; - /* Set Maximum Rise Time for standard mode */ - I2Cx->TRISE = freqrange + 1; - } - /* Configure speed in fast mode */ - /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral - input clock) must be a multiple of 10 MHz */ - else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ - { - if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - /* Fast mode speed calculate: Tlow/Thigh = 2 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ - { - /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - /* Set DUTY bit */ - result |= I2C_DutyCycle_16_9; - } - - /* Test if CCR value is under 0x1*/ - if ((result & I2C_CCR_CCR) == 0) - { - /* Set minimum allowed value */ - result |= (uint16_t)0x0001; - } - /* Set speed value and set F/S bit for fast mode */ - tmpreg |= (uint16_t)(result | I2C_CCR_FS); - /* Set Maximum Rise Time for fast mode */ - I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - /* Write to I2Cx CCR */ - I2Cx->CCR = tmpreg; - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - -/*---------------------------- I2Cx CR1 Configuration ------------------------*/ - /* Get the I2Cx CR1 value */ - tmpreg = I2Cx->CR1; - /* Clear ACK, SMBTYPE and SMBUS bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure I2Cx: mode and acknowledgement */ - /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ - /* Set ACK bit according to I2C_Ack value */ - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - /* Write to I2Cx CR1 */ - I2Cx->CR1 = tmpreg; - -/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ - /* Set I2Cx Own Address1 and acknowledged address */ - I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ -/*---------------- Reset I2C init structure parameters values ----------------*/ - /* initialize the I2C_ClockSpeed member */ - I2C_InitStruct->I2C_ClockSpeed = 5000; - /* Initialize the I2C_Mode member */ - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - /* Initialize the I2C_DutyCycle member */ - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStruct->I2C_OwnAddress1 = 0; - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - /* Initialize the I2C_AcknowledgedAddress member */ - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/** - * @brief Enables or disables the specified I2C peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - } - else - { - /* Disable the selected I2C peripheral */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); - } -} - -/** - * @brief Generates I2Cx communication START condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a START condition */ - I2Cx->CR1 |= I2C_CR1_START; - } - else - { - /* Disable the START condition generation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START); - } -} - -/** - * @brief Generates I2Cx communication STOP condition. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a STOP condition */ - I2Cx->CR1 |= I2C_CR1_STOP; - } - else - { - /* Disable the STOP condition generation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP); - } -} - -/** - * @brief Enables or disables the specified I2C acknowledge feature. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C Acknowledgement. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the acknowledgement */ - I2Cx->CR1 |= I2C_CR1_ACK; - } - else - { - /* Disable the acknowledgement */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK); - } -} - -/** - * @brief Configures the specified I2C own address2. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the 7bit I2C own address2. - * @retval None. - */ -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Get the old register value */ - tmpreg = I2Cx->OAR2; - - /* Reset I2Cx Own address2 bit [7:1] */ - tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2); - - /* Set I2Cx Own address2 */ - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - - /* Store the new register value */ - I2Cx->OAR2 = tmpreg; -} - -/** - * @brief Enables or disables the specified I2C dual addressing mode. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C dual addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable dual addressing mode */ - I2Cx->OAR2 |= I2C_OAR2_ENDUAL; - } - else - { - /* Disable dual addressing mode */ - I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL); - } -} - -/** - * @brief Enables or disables the specified I2C general call feature. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C General call. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable generall call */ - I2Cx->CR1 |= I2C_CR1_ENGC; - } - else - { - /* Disable generall call */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC); - } -} - -/** - * @brief Enables or disables the specified I2C software reset. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C software reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Peripheral under reset */ - I2Cx->CR1 |= I2C_CR1_SWRST; - } - else - { - /* Peripheral not under reset */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST); - } -} - -/** - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_SMBusAlert: specifies SMBAlert pin level. - * This parameter can be one of the following values: - * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low - * @arg I2C_SMBusAlert_High: SMBAlert pin driven high - * @retval None - */ -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); - if (I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - /* Drive the SMBusAlert pin Low */ - I2Cx->CR1 |= I2C_SMBusAlert_Low; - } - else - { - /* Drive the SMBusAlert pin High */ - I2Cx->CR1 &= I2C_SMBusAlert_High; - } -} - -/** - * @brief Enables or disables the specified I2C ARP. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx ARP. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C ARP */ - I2Cx->CR1 |= I2C_CR1_ENARP; - } - else - { - /* Disable the selected I2C ARP */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP); - } -} - -/** - * @brief Enables or disables the specified I2C Clock stretching. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState == DISABLE) - { - /* Enable the selected I2C Clock stretching */ - I2Cx->CR1 |= I2C_CR1_NOSTRETCH; - } - else - { - /* Disable the selected I2C Clock stretching */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH); - } -} - -/** - * @brief Selects the specified I2C fast mode duty cycle. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_DutyCycle: specifies the fast mode duty cycle. - * This parameter can be one of the following values: - * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 - * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 - * @retval None - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); - if (I2C_DutyCycle != I2C_DutyCycle_16_9) - { - /* I2C fast mode Tlow/Thigh=2 */ - I2Cx->CCR &= I2C_DutyCycle_2; - } - else - { - /* I2C fast mode Tlow/Thigh=16/9 */ - I2Cx->CCR |= I2C_DutyCycle_16_9; - } -} - -/** - * @brief Transmits the address byte to select the slave device. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Address: specifies the slave address which will be transmitted - * @param I2C_Direction: specifies whether the I2C device will be a - * Transmitter or a Receiver. This parameter can be one of the following values - * @arg I2C_Direction_Transmitter: Transmitter mode - * @arg I2C_Direction_Receiver: Receiver mode - * @retval None. - */ -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction != I2C_Direction_Transmitter) - { - /* Set the address bit0 for read */ - Address |= I2C_OAR1_ADD0; - } - else - { - /* Reset the address bit0 for write */ - Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0); - } - /* Send the address */ - I2Cx->DR = Address; -} - -/** - * @} - */ - -/** @defgroup I2C_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - Data transfers functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Sends a data byte through the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param Data: Byte to be transmitted.. - * @retval None - */ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Write in the DR register the data to be sent */ - I2Cx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the I2Cx peripheral. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the data in the DR register */ - return (uint8_t)I2Cx->DR; -} - -/** - * @} - */ - -/** @defgroup I2C_Group3 PEC management functions - * @brief PEC management functions - * -@verbatim - =============================================================================== - PEC management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified I2C PEC transfer. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C PEC transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC transmission */ - I2Cx->CR1 |= I2C_CR1_PEC; - } - else - { - /* Disable the selected I2C PEC transmission */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC); - } -} - -/** - * @brief Selects the specified I2C PEC position. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_PECPosition: specifies the PEC position. - * This parameter can be one of the following values: - * @arg I2C_PECPosition_Next: indicates that the next byte is PEC - * @arg I2C_PECPosition_Current: indicates that current byte is PEC - * @retval None - */ -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); - if (I2C_PECPosition == I2C_PECPosition_Next) - { - /* Next byte in shift register is PEC */ - I2Cx->CR1 |= I2C_PECPosition_Next; - } - else - { - /* Current byte in shift register is PEC */ - I2Cx->CR1 &= I2C_PECPosition_Current; - } -} - -/** - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC calculation */ - I2Cx->CR1 |= I2C_CR1_ENPEC; - } - else - { - /* Disable the selected I2C PEC calculation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC); - } -} - -/** - * @brief Returns the PEC value for the specified I2C. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @retval The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the selected I2C PEC value */ - return ((I2Cx->SR2) >> 8); -} - -/** - * @} - */ - -/** @defgroup I2C_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - This section provides functions allowing to configure the I2C DMA channels - requests. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified I2C DMA requests. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C DMA requests */ - I2Cx->CR2 |= I2C_CR2_DMAEN; - } - else - { - /* Disable the selected I2C DMA requests */ - I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN); - } -} - -/** - * @brief Specifies that the next DMA transfer is the last one. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Next DMA transfer is the last transfer */ - I2Cx->CR2 |= I2C_CR2_LAST; - } - else - { - /* Next DMA transfer is not the last transfer */ - I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST); - } -} - -/** - * @} - */ - -/** @defgroup I2C_Group5 Interrupts events and flags management functions - * @brief Interrupts, events and flags management functions - * -@verbatim - =============================================================================== - Interrupts, events and flags management functions - =============================================================================== - This section provides functions allowing to configure the I2C Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - =============================================================================== - I2C State Monitoring Functions - =============================================================================== - This I2C driver provides three different ways for I2C state monitoring - depending on the application requirements and constraints: - - - 1. Basic state monitoring (Using I2C_CheckEvent() function) - ----------------------------------------------------------- - It compares the status registers (SR1 and SR2) content to a given event - (can be the combination of one or more flags). - It returns SUCCESS if the current status includes the given flags - and returns ERROR if one or more flags are missing in the current status. - - - When to use - - This function is suitable for most applications as well as for startup - activity since the events are fully described in the product reference - manual (RM0038). - - It is also suitable for users who need to define their own events. - - - Limitations - - If an error occurs (ie. error flags are set besides to the monitored - flags), the I2C_CheckEvent() function may return SUCCESS despite - the communication hold or corrupted real state. - In this case, it is advised to use error interrupts to monitor - the error events and handle them in the interrupt IRQ handler. - - @note - For error management, it is advised to use the following functions: - - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - Where x is the peripheral instance (I2C1, I2C2 ...) - - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the - I2Cx_ER_IRQHandler() function in order to determine which error occurred. - - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - and/or I2C_GenerateStop() in order to clear the error flag and source - and return to correct communication status. - - - 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) - -------------------------------------------------------------------- - Using the function I2C_GetLastEvent() which returns the image of both status - registers in a single word (uint32_t) (Status Register 2 value is shifted left - by 16 bits and concatenated to Status Register 1). - - - When to use - - This function is suitable for the same applications above but it - allows to overcome the mentioned limitation of I2C_GetFlagStatus() - function. - - The returned value could be compared to events already defined in - the library (stm32l1xx_i2c.h) or to custom values defined by user. - This function is suitable when multiple flags are monitored at the - same time. - - At the opposite of I2C_CheckEvent() function, this function allows - user to choose when an event is accepted (when all events flags are - set and no other flags are set or just when the needed flags are set - like I2C_CheckEvent() function. - - - Limitations - - User may need to define his own events. - - Same remark concerning the error management is applicable for this - function if user decides to check only regular communication flags - (and ignores error flags). - - - 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) - ----------------------------------------------------------------------- - - Using the function I2C_GetFlagStatus() which simply returns the status of - one single flag (ie. I2C_FLAG_RXNE ...). - - - When to use - - This function could be used for specific applications or in debug - phase. - - It is suitable when only one flag checking is needed (most I2C - events are monitored through multiple flags). - - Limitations: - - When calling this function, the Status register is accessed. - Some flags are cleared when the status register is accessed. - So checking the status of one Flag, may clear other ones. - - Function may need to be called twice or more in order to monitor - one single event. - - For detailed description of Events, please refer to section I2C_Events in - stm32l1xx_i2c.h file. - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified I2C register and returns its value. - * @param I2C_Register: specifies the register to read. - * This parameter can be one of the following values: - * @arg I2C_Register_CR1: CR1 register. - * @arg I2C_Register_CR2: CR2 register. - * @arg I2C_Register_OAR1: OAR1 register. - * @arg I2C_Register_OAR2: OAR2 register. - * @arg I2C_Register_DR: DR register. - * @arg I2C_Register_SR1: SR1 register. - * @arg I2C_Register_SR2: SR2 register. - * @arg I2C_Register_CCR: CCR register. - * @arg I2C_Register_TRISE: TRISE register. - * @retval The value of the read register. - */ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_REGISTER(I2C_Register)); - - tmp = (uint32_t) I2Cx; - tmp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Enables or disables the specified I2C interrupts. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_IT_BUF: Buffer interrupt mask - * @arg I2C_IT_EVT: Event interrupt mask - * @arg I2C_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_CONFIG_IT(I2C_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupts */ - I2Cx->CR2 |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupts */ - I2Cx->CR2 &= (uint16_t)~I2C_IT; - } -} - -/** - =============================================================================== - 1. Basic state monitoring - =============================================================================== - */ - -/** - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_EVENT: specifies the event to be checked. - * This parameter can be one of the following values: - * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED : EV1 - * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED : EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) : EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) : EV2 - * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED : EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) : EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) : EV3 - * @arg I2C_EVENT_SLAVE_ACK_FAILURE : EV3_2 - * @arg I2C_EVENT_SLAVE_STOP_DETECTED : EV4 - * @arg I2C_EVENT_MASTER_MODE_SELECT : EV5 - * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED : EV6 - * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED : EV6 - * @arg I2C_EVENT_MASTER_BYTE_RECEIVED : EV7 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING : EV8 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED : EV8_2 - * @arg I2C_EVENT_MASTER_MODE_ADDRESS10 : EV9 - * - * @note: For detailed description of Events, please refer to section - * I2C_Events in stm32l1xx_i2c.h file. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Last event is equal to the I2C_EVENT - * - ERROR: Last event is different from the I2C_EVENT - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_EVENT(I2C_EVENT)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_MASK; - - /* Check whether the last event contains the I2C_EVENT */ - if ((lastevent & I2C_EVENT) == I2C_EVENT) - { - /* SUCCESS: last event is equal to I2C_EVENT */ - status = SUCCESS; - } - else - { - /* ERROR: last event is different from I2C_EVENT */ - status = ERROR; - } - /* Return status */ - return status; -} - -/** - =============================================================================== - 2. Advanced state monitoring - =============================================================================== - */ - -/** - * @brief Returns the last I2Cx Event. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * - * @note: For detailed description of Events, please refer to section - * I2C_Events in stm32l1xx_i2c.h file. - * - * @retval The last event - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_MASK; - - /* Return status */ - return lastevent; -} - -/** - =============================================================================== - 3. Flag-based state monitoring - =============================================================================== - */ - -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) - * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) - * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) - * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) - * @arg I2C_FLAG_TRA: Transmitter/Receiver flag - * @arg I2C_FLAG_BUSY: Bus busy flag - * @arg I2C_FLAG_MSL: Master/Slave flag - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) - * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag - * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) - * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) ADSL - * Address matched flag (Slave mode)ENDAD - * @arg I2C_FLAG_SB: Start bit flag (Master mode) - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - /* Get the I2Cx peripheral base address */ - i2cxbase = (uint32_t)I2Cx; - - /* Read flag register index */ - i2creg = I2C_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - I2C_FLAG &= FLAG_MASK; - - if(i2creg != 0) - { - /* Get the I2Cx SR1 register address */ - i2cxbase += 0x14; - } - else - { - /* Flag in I2Cx SR2 Register */ - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - /* Get the I2Cx SR2 register address */ - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - /* I2C_FLAG is set */ - bitstatus = SET; - } - else - { - /* I2C_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the I2C_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's pending flags. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * - * @note - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR - * register (I2C_SendData()). - * @retval None - */ -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); - /* Get the I2C flag position */ - flagpos = I2C_FLAG & FLAG_MASK; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @brief Checks whether the specified I2C interrupt has occurred or not. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert flag - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_IT_PECERR: PEC error in reception flag - * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure flag - * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_IT_BERR: Bus error flag - * @arg I2C_IT_TXE: Data register empty flag (Transmitter) - * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag - * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) - * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_IT_BTF: Byte transfer finished flag - * @arg I2C_IT_ADDR: Address sent flag (Master mode) ADSL - * Address matched flag (Slave mode)ENDAD - * @arg I2C_IT_SB: Start bit flag (Master mode) - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_IT(I2C_IT)); - - /* Check if the interrupt source is enabled or not */ - enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ; - - /* Get bit[23:0] of the flag */ - I2C_IT &= FLAG_MASK; - - /* Check the status of the specified I2C flag */ - if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - /* I2C_IT is set */ - bitstatus = SET; - } - else - { - /* I2C_IT is reset */ - bitstatus = RESET; - } - /* Return the I2C_IT status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cxs interrupt pending bits. - * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert interrupt - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt - * @arg I2C_IT_PECERR: PEC error in reception interrupt - * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure interrupt - * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) - * @arg I2C_IT_BERR: Bus error interrupt - * - * @note - * - STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * - ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DR register. - * - BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * - ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * - SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DR register (I2C_SendData()). - * @retval None - */ -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_IT(I2C_IT)); - /* Get the I2C flag position */ - flagpos = I2C_IT & FLAG_MASK; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ - - - diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_iwdg.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_iwdg.c deleted file mode 100644 index d9e1028c3..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_iwdg.c +++ /dev/null @@ -1,263 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_iwdg.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the Independent watchdog (IWDG) peripheral: - * - Prescaler and Counter configuration - * - IWDG activation - * - Flag management - * - * @verbatim - * - * =================================================================== - * IWDG features - * =================================================================== - * - * The IWDG can be started by either software or hardware (configurable - * through option byte). - * - * The IWDG is clocked by its own dedicated low-speed clock (LSI) and - * thus stays active even if the main clock fails. - * Once the IWDG is started, the LSI is forced ON and cannot be disabled - * (LSI cannot be disabled too), and the counter starts counting down from - * the reset value of 0xFFF. When it reaches the end of count value (0x000) - * a system reset is generated. - * The IWDG counter should be reloaded at regular intervals to prevent - * an MCU reset. - * - * The IWDG is implemented in the VDD voltage domain that is still functional - * in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY) - * - * IWDGRST flag in RCC_CSR register can be used to inform when a IWDG - * reset occurs - * - * Min-max timeout value @37KHz (LSI): ~108us / ~28.3s - * The IWDG timeout may vary due to LSI frequency dispersion. STM32L1xx - * devices provide the capability to measure the LSI frequency (LSI clock - * connected internally to TIM10 CH1 input capture). The measured value - * can be used to have an IWDG timeout with an acceptable accuracy. - * For more information, please refer to the STM32L1xx Reference manual - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable write access to IWDG_PR and IWDG_RLR registers using - * IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function - * - * 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function - * - * 3. Configure the IWDG counter value using IWDG_SetReload() function. - * This value will be loaded in the IWDG counter each time the counter - * is reloaded, then the IWDG will start counting down from this value. - * - * 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used - * in software mode (no need to enable the LSI, it will be enabled - * by hardware) - * - * 5. Then the application program must reload the IWDG counter at regular - * intervals during normal operation to prevent an MCU reset, using - * IWDG_ReloadCounter() function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_iwdg.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup IWDG - * @brief IWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ---------------------- IWDG registers bit mask ----------------------------*/ -/* KR register bit mask */ -#define KR_KEY_RELOAD ((uint16_t)0xAAAA) -#define KR_KEY_ENABLE ((uint16_t)0xCCCC) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup IWDG_Private_Functions - * @{ - */ - -/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions - * @brief Prescaler and Counter configuration functions - * -@verbatim - =============================================================================== - Prescaler and Counter configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. - * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. - * This parameter can be one of the following values: - * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers - * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers - * @retval None - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); - IWDG->KR = IWDG_WriteAccess; -} - -/** - * @brief Sets IWDG Prescaler value. - * @param IWDG_Prescaler: specifies the IWDG Prescaler value. - * This parameter can be one of the following values: - * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 - * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 - * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 - * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 - * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 - * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 - * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 - * @retval None - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); - IWDG->PR = IWDG_Prescaler; -} - -/** - * @brief Sets IWDG Reload value. - * @param Reload: specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * @retval None - */ -void IWDG_SetReload(uint16_t Reload) -{ - /* Check the parameters */ - assert_param(IS_IWDG_RELOAD(Reload)); - IWDG->RLR = Reload; -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_ReloadCounter(void) -{ - IWDG->KR = KR_KEY_RELOAD; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group2 IWDG activation function - * @brief IWDG activation function - * -@verbatim - =============================================================================== - IWDG activation function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_Enable(void) -{ - IWDG->KR = KR_KEY_ENABLE; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group3 Flag management function - * @brief Flag management function - * -@verbatim - =============================================================================== - Flag management function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified IWDG flag is set or not. - * @param IWDG_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Prescaler Value Update on going - * @arg IWDG_FLAG_RVU: Reload Value Update on going - * @retval The new state of IWDG_FLAG (SET or RESET). - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_IWDG_FLAG(IWDG_FLAG)); - if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_lcd.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_lcd.c deleted file mode 100644 index 9116b6881..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_lcd.c +++ /dev/null @@ -1,637 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_lcd.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the LCD controller (LCD) peripheral: - * - Initialization and configuration - * - LCD RAM memory write - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * LCD Clock - * =================================================================== - * LCDCLK is the same as RTCCLK. - * To configure the RTCCLK/LCDCLK, proceed as follows: - * - Enable the Power Controller (PWR) APB1 interface clock using the - * RCC_APB1PeriphClockCmd() function. - * - Enable access to RTC domain using the PWR_RTCAccessCmd() function. - * - Select the RTC clock source using the RCC_RTCCLKConfig() function. - * - * The frequency generator allows you to achieve various LCD frame rates - * starting from an LCD input clock frequency (LCDCLK) which can vary - * from 32 kHz up to 1 MHz. - * - * =================================================================== - * LCD and low power modes - * =================================================================== - * The LCD still active during STOP mode. - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable LCD clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_LCD, ENABLE) function - * - * 2. Configure the LCD prescaler, divider, duty, bias and voltage source - * using LCD_Init() function - * - * 3. Optionally you can enable/configure: - * - LCD High Drive using the LCD_HighDriveCmd() function - * - LCD High Drive using the LCD_MuxSegmentCmd() function - * - LCD Pulse ON Duration using the LCD_PulseOnDurationConfig() function - * - LCD Dead Time using the LCD_DeadTimeConfig() function - * - The LCD Blink mode and frequency using the LCD_BlinkConfig() function - * - The LCD Contrast using the LCD_ContrastConfig() function - * - * 4. Call the LCD_WaitForSynchro() function to wait for LCD_FCR register - * synchronization. - * - * 5. Call the LCD_Cmd() to enable the LCD controller - * - * 6. Wait until the LCD Controller status is enabled and the step-up - * converter is ready using the LCD_GetFlagStatus() and - * LCD_FLAG_ENS and LCD_FLAG_RDY flags. - * - * 7. Write to the LCD RAM memory using the LCD_Write() function. - * - * 8. Request an update display using the LCD_UpdateDisplayRequest() - * function. - * - * 9. Wait until the update display is finished by checking the UDD - * flag status using the LCD_GetFlagStatus(LCD_FLAG_UDD) - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_lcd.h" -#include "stm32l1xx_rcc.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup LCD - * @brief LCD driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ------------ LCD registers bit address in the alias region --------------- */ -#define LCD_OFFSET (LCD_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of LCDEN bit */ -#define CR_OFFSET (LCD_OFFSET + 0x00) -#define LCDEN_BitNumber 0x00 -#define CR_LCDEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LCDEN_BitNumber * 4)) - -/* Alias word address of MUX_SEG bit */ -#define MUX_SEG_BitNumber 0x07 -#define CR_MUX_SEG_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MUX_SEG_BitNumber * 4)) - - -/* --- FCR Register ---*/ - -/* Alias word address of HD bit */ -#define FCR_OFFSET (LCD_OFFSET + 0x04) -#define HD_BitNumber 0x00 -#define FCR_HD_BB (PERIPH_BB_BASE + (FCR_OFFSET * 32) + (HD_BitNumber * 4)) - -/* --- SR Register ---*/ - -/* Alias word address of UDR bit */ -#define SR_OFFSET (LCD_OFFSET + 0x08) -#define UDR_BitNumber 0x02 -#define SR_UDR_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (UDR_BitNumber * 4)) - -#define FCR_MASK ((uint32_t)0xFC03FFFF) /* LCD FCR Mask */ -#define CR_MASK ((uint32_t)0xFFFFFF81) /* LCD CR Mask */ -#define PON_MASK ((uint32_t)0xFFFFFF8F) /* LCD PON Mask */ -#define DEAD_MASK ((uint32_t)0xFFFFFC7F) /* LCD DEAD Mask */ -#define BLINK_MASK ((uint32_t)0xFFFC1FFF) /* LCD BLINK Mask */ -#define CONTRAST_MASK ((uint32_t)0xFFFFE3FF) /* LCD CONTRAST Mask */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup LCD_Private_Functions - * @{ - */ - -/** @defgroup LCD_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the LCD peripheral registers to their default reset - * values. - * @param None - * @retval None - */ -void LCD_DeInit(void) -{ - /* Enable LCD reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, ENABLE); - /* Release LCD from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, DISABLE); -} - -/** - * @brief Initializes the LCD peripheral according to the specified parameters - * in the LCD_InitStruct. - * @note This function can be used only when the LCD is disabled. - * @param LCD_InitStruct: pointer to a LCD_InitTypeDef structure that contains - * the configuration information for the specified LCD peripheral. - * @retval None - */ -void LCD_Init(LCD_InitTypeDef* LCD_InitStruct) -{ - /* Check function parameters */ - assert_param(IS_LCD_PRESCALER(LCD_InitStruct->LCD_Prescaler)); - assert_param(IS_LCD_DIVIDER(LCD_InitStruct->LCD_Divider)); - assert_param(IS_LCD_DUTY(LCD_InitStruct->LCD_Duty)); - assert_param(IS_LCD_BIAS(LCD_InitStruct->LCD_Bias)); - assert_param(IS_LCD_VOLTAGE_SOURCE(LCD_InitStruct->LCD_VoltageSource)); - - LCD->FCR &= (uint32_t)FCR_MASK; - LCD->FCR |= (uint32_t)(LCD_InitStruct->LCD_Prescaler | LCD_InitStruct->LCD_Divider); - - LCD_WaitForSynchro(); - - LCD->CR &= (uint32_t)CR_MASK; - LCD->CR |= (uint32_t)(LCD_InitStruct->LCD_Duty | LCD_InitStruct->LCD_Bias | \ - LCD_InitStruct->LCD_VoltageSource); - -} - -/** - * @brief Fills each LCD_InitStruct member with its default value. - * @param LCD_InitStruct: pointer to a LCD_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct) -{ -/*--------------- Reset LCD init structure parameters values -----------------*/ - LCD_InitStruct->LCD_Prescaler = LCD_Prescaler_1; /*!< Initialize the LCD_Prescaler member */ - - LCD_InitStruct->LCD_Divider = LCD_Divider_16; /*!< Initialize the LCD_Divider member */ - - LCD_InitStruct->LCD_Duty = LCD_Duty_Static; /*!< Initialize the LCD_Duty member */ - - LCD_InitStruct->LCD_Bias = LCD_Bias_1_4; /*!< Initialize the LCD_Bias member */ - - LCD_InitStruct->LCD_VoltageSource = LCD_VoltageSource_Internal; /*!< Initialize the LCD_VoltageSource member */ -} - -/** - * @brief Enables or disables the LCD Controller. - * @param NewState: new state of the LCD peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void LCD_Cmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_LCDEN_BB = (uint32_t)NewState; -} - -/** - * @brief Waits until the LCD FCR register is synchronized in the LCDCLK domain. - * This function must be called after any write operation to LCD_FCR register. - * @param None - * @retval None - */ -void LCD_WaitForSynchro(void) -{ - /* Loop until FCRSF flag is set */ - while ((LCD->SR & LCD_FLAG_FCRSF) == (uint32_t)RESET) - { - } -} - -/** - * @brief Enables or disables the low resistance divider. Displays with high - * internal resistance may need a longer drive time to achieve - * satisfactory contrast. This function is useful in this case if some - * additional power consumption can be tolerated. - * @note When this mode is enabled, the PulseOn Duration (PON) have to be - * programmed to 1/CK_PS (LCD_PulseOnDuration_1). - * @param NewState: new state of the low resistance divider. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void LCD_HighDriveCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) FCR_HD_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Mux Segment. - * @note This function can be used only when the LCD is disabled. - * @param NewState: new state of the Mux Segment. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void LCD_MuxSegmentCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_MUX_SEG_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the LCD pulses on duration. - * @param LCD_PulseOnDuration: specifies the LCD pulse on duration in terms of - * CK_PS (prescaled LCD clock period) pulses. - * This parameter can be one of the following values: - * @arg LCD_PulseOnDuration_0: 0 pulse - * @arg LCD_PulseOnDuration_1: Pulse ON duration = 1/CK_PS - * @arg LCD_PulseOnDuration_2: Pulse ON duration = 2/CK_PS - * @arg LCD_PulseOnDuration_3: Pulse ON duration = 3/CK_PS - * @arg LCD_PulseOnDuration_4: Pulse ON duration = 4/CK_PS - * @arg LCD_PulseOnDuration_5: Pulse ON duration = 5/CK_PS - * @arg LCD_PulseOnDuration_6: Pulse ON duration = 6/CK_PS - * @arg LCD_PulseOnDuration_7: Pulse ON duration = 7/CK_PS - * @retval None - */ -void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration) -{ - /* Check the parameters */ - assert_param(IS_LCD_PULSE_ON_DURATION(LCD_PulseOnDuration)); - - LCD->FCR &= (uint32_t)PON_MASK; - LCD->FCR |= (uint32_t)(LCD_PulseOnDuration); -} - -/** - * @brief Configures the LCD dead time. - * @param LCD_DeadTime: specifies the LCD dead time. - * This parameter can be one of the following values: - * @arg LCD_DeadTime_0: No dead Time - * @arg LCD_DeadTime_1: One Phase between different couple of Frame - * @arg LCD_DeadTime_2: Two Phase between different couple of Frame - * @arg LCD_DeadTime_3: Three Phase between different couple of Frame - * @arg LCD_DeadTime_4: Four Phase between different couple of Frame - * @arg LCD_DeadTime_5: Five Phase between different couple of Frame - * @arg LCD_DeadTime_6: Six Phase between different couple of Frame - * @arg LCD_DeadTime_7: Seven Phase between different couple of Frame - * @retval None - */ -void LCD_DeadTimeConfig(uint32_t LCD_DeadTime) -{ - /* Check the parameters */ - assert_param(IS_LCD_DEAD_TIME(LCD_DeadTime)); - - LCD->FCR &= (uint32_t)DEAD_MASK; - LCD->FCR |= (uint32_t)(LCD_DeadTime); -} - -/** - * @brief Configures the LCD Blink mode and Blink frequency. - * @param LCD_BlinkMode: specifies the LCD blink mode. - * This parameter can be one of the following values: - * @arg LCD_BlinkMode_Off: Blink disabled - * @arg LCD_BlinkMode_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel) - * @arg LCD_BlinkMode_SEG0_AllCOM: Blink enabled on SEG[0], all COM (up to 8 - * pixels according to the programmed duty) - * @arg LCD_BlinkMode_AllSEG_AllCOM: Blink enabled on all SEG and all COM - * (all pixels) - * @param LCD_BlinkFrequency: specifies the LCD blink frequency. - * This parameter can be one of the following values: - * @arg LCD_BlinkFrequency_Div8: The Blink frequency = fLcd/8 - * @arg LCD_BlinkFrequency_Div16: The Blink frequency = fLcd/16 - * @arg LCD_BlinkFrequency_Div32: The Blink frequency = fLcd/32 - * @arg LCD_BlinkFrequency_Div64: The Blink frequency = fLcd/64 - * @arg LCD_BlinkFrequency_Div128: The Blink frequency = fLcd/128 - * @arg LCD_BlinkFrequency_Div256: The Blink frequency = fLcd/256 - * @arg LCD_BlinkFrequency_Div512: The Blink frequency = fLcd/512 - * @arg LCD_BlinkFrequency_Div1024: The Blink frequency = fLcd/1024 - * @retval None - */ -void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency) -{ - /* Check the parameters */ - assert_param(IS_LCD_BLINK_MODE(LCD_BlinkMode)); - assert_param(IS_LCD_BLINK_FREQUENCY(LCD_BlinkFrequency)); - - LCD->FCR &= (uint32_t)BLINK_MASK; - LCD->FCR |= (uint32_t)(LCD_BlinkMode | LCD_BlinkFrequency); -} - -/** - * @brief Configures the LCD Contrast. - * @param LCD_Contrast: specifies the LCD Contrast. - * This parameter can be one of the following values: - * @arg LCD_Contrast_Level_0: Maximum Voltage = 2.60V - * @arg LCD_Contrast_Level_1: Maximum Voltage = 2.73V - * @arg LCD_Contrast_Level_2: Maximum Voltage = 2.86V - * @arg LCD_Contrast_Level_3: Maximum Voltage = 2.99V - * @arg LCD_Contrast_Level_4: Maximum Voltage = 3.12V - * @arg LCD_Contrast_Level_5: Maximum Voltage = 3.25V - * @arg LCD_Contrast_Level_6: Maximum Voltage = 3.38V - * @arg LCD_Contrast_Level_7: Maximum Voltage = 3.51V - * @retval None - */ -void LCD_ContrastConfig(uint32_t LCD_Contrast) -{ - /* Check the parameters */ - assert_param(IS_LCD_CONTRAST(LCD_Contrast)); - - LCD->FCR &= (uint32_t)CONTRAST_MASK; - LCD->FCR |= (uint32_t)(LCD_Contrast); -} - -/** - * @} - */ - -/** @defgroup LCD_Group2 LCD RAM memory write functions - * @brief LCD RAM memory write functions - * -@verbatim - =============================================================================== - LCD RAM memory write functions - =============================================================================== - - Using its double buffer memory the LCD controller ensures the coherency of the - displayed information without having to use interrupts to control LCD_RAM - modification. - The application software can access the first buffer level (LCD_RAM) through - the APB interface. Once it has modified the LCD_RAM, it sets the UDR flag in - the LCD_SR register using the LCD_UpdateDisplayRequest() function. - This UDR flag (update display request) requests the updated information to be - moved into the second buffer level (LCD_DISPLAY). - This operation is done synchronously with the frame (at the beginning of the - next frame), until the update is completed, the LCD_RAM is write protected and - the UDR flag stays high. - Once the update is completed another flag (UDD - Update Display Done) is set and - generates an interrupt if the UDDIE bit in the LCD_FCR register is set. - The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one - even frame. - The update will not occur (UDR = 1 and UDD = 0) until the display is - enabled (LCDEN = 1). - -@endverbatim - * @{ - */ - -/** - * @brief Writes a word in the specific LCD RAM. - * @param LCD_RAMRegister: specifies the LCD Contrast. - * This parameter can be one of the following values: - * @arg LCD_RAMRegister_0: LCD RAM Register 0 - * @arg LCD_RAMRegister_1: LCD RAM Register 1 - * @arg LCD_RAMRegister_2: LCD RAM Register 2 - * @arg LCD_RAMRegister_3: LCD RAM Register 3 - * @arg LCD_RAMRegister_4: LCD RAM Register 4 - * @arg LCD_RAMRegister_5: LCD RAM Register 5 - * @arg LCD_RAMRegister_6: LCD RAM Register 6 - * @arg LCD_RAMRegister_7: LCD RAM Register 7 - * @arg LCD_RAMRegister_8: LCD RAM Register 8 - * @arg LCD_RAMRegister_9: LCD RAM Register 9 - * @arg LCD_RAMRegister_10: LCD RAM Register 10 - * @arg LCD_RAMRegister_11: LCD RAM Register 11 - * @arg LCD_RAMRegister_12: LCD RAM Register 12 - * @arg LCD_RAMRegister_13: LCD RAM Register 13 - * @arg LCD_RAMRegister_14: LCD RAM Register 14 - * @arg LCD_RAMRegister_15: LCD RAM Register 15 - * @param LCD_Data: specifies LCD Data Value to be written. - * @retval None - */ -void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data) -{ - /* Check the parameters */ - assert_param(IS_LCD_RAM_REGISTER(LCD_RAMRegister)); - - /* Copy data bytes to RAM register */ - LCD->RAM[LCD_RAMRegister] = (uint32_t)LCD_Data; -} - -/** - * @brief Enables the Update Display Request. - * @note Each time software modifies the LCD_RAM it must set the UDR bit to - * transfer the updated data to the second level buffer. - * The UDR bit stays set until the end of the update and during this - * time the LCD_RAM is write protected. - * @note When the display is disabled, the update is performed for all - * LCD_DISPLAY locations. - * When the display is enabled, the update is performed only for locations - * for which commons are active (depending on DUTY). For example if - * DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated. - * @param None - * @retval None - */ -void LCD_UpdateDisplayRequest(void) -{ - *(__IO uint32_t *) SR_UDR_BB = (uint32_t)0x01; -} - -/** - * @} - */ - -/** @defgroup LCD_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified LCD interrupts. - * @param LCD_IT: specifies the LCD interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg LCD_IT_SOF: Start of Frame Interrupt - * @arg LCD_IT_UDD: Update Display Done Interrupt - * @param NewState: new state of the specified LCD interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_LCD_IT(LCD_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - LCD->FCR |= LCD_IT; - } - else - { - LCD->FCR &= (uint32_t)~LCD_IT; - } -} - -/** - * @brief Checks whether the specified LCD flag is set or not. - * @param LCD_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status. - * @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR - * goes from 0 to 1. On deactivation it reflects the real status of - * LCD so it becomes 0 at the end of the last displayed frame. - * @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at - * the beginning of a new frame, at the same time as the display data is - * updated. - * @arg LCD_FLAG_UDR: Update Display Request flag. - * @arg LCD_FLAG_UDD: Update Display Done flag. - * @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status - * of the step-up converter. - * @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. - * This flag is set by hardware each time the LCD_FCR register is updated - * in the LCDCLK domain. - * @retval The new state of LCD_FLAG (SET or RESET). - */ -FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_LCD_GET_FLAG(LCD_FLAG)); - - if ((LCD->SR & LCD_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the LCD's pending flags. - * @param LCD_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg LCD_FLAG_SOF: Start of Frame Interrupt - * @arg LCD_FLAG_UDD: Update Display Done Interrupt - * @retval None - */ -void LCD_ClearFlag(uint32_t LCD_FLAG) -{ - /* Check the parameters */ - assert_param(IS_LCD_CLEAR_FLAG(LCD_FLAG)); - - /* Clear the corresponding LCD flag */ - LCD->CLR = (uint32_t)LCD_FLAG; -} - -/** - * @brief Checks whether the specified RTC interrupt has occurred or not. - * @param RTC_IT: specifies the RTC interrupts sources to check. - * This parameter can be one of the following values: - * @arg LCD_IT_SOF: Start of Frame Interrupt - * @arg LCD_IT_UDD: Update Display Done Interrupt. - * @note If the device is in STOP mode (PCLK not provided) UDD will not - * generate an interrupt even if UDDIE = 1. - * If the display is not enabled the UDD interrupt will never occur. - * @retval The new state of the LCD_IT (SET or RESET). - */ -ITStatus LCD_GetITStatus(uint32_t LCD_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_LCD_GET_IT(LCD_IT)); - - if ((LCD->SR & LCD_IT) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - if (((LCD->FCR & LCD_IT) != (uint16_t)RESET) && (bitstatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the LCD's interrupt pending bits. - * @param LCD_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg LCD_IT_SOF: Start of Frame Interrupt - * @arg LCD_IT_UDD: Update Display Done Interrupt - * @retval None - */ -void LCD_ClearITPendingBit(uint32_t LCD_IT) -{ - /* Check the parameters */ - assert_param(IS_LCD_IT(LCD_IT)); - - /* Clear the corresponding LCD pending bit */ - LCD->CLR = (uint32_t)LCD_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_pwr.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_pwr.c deleted file mode 100644 index 09e7cc351..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_pwr.c +++ /dev/null @@ -1,829 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_pwr.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * - RTC Domain Access - * - PVD configuration - * - WakeUp pins configuration - * - Ultra Low Power mode configuration - * - Voltage Scaling configuration - * - Low Power modes configuration - * - Flags management - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_pwr.h" -#include "stm32l1xx_rcc.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup PWR - * @brief PWR driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* --------- PWR registers bit address in the alias region ---------- */ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of DBP bit */ -#define CR_OFFSET (PWR_OFFSET + 0x00) -#define DBP_BitNumber 0x08 -#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) - -/* Alias word address of PVDE bit */ -#define PVDE_BitNumber 0x04 -#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) - -/* Alias word address of ULP bit */ -#define ULP_BitNumber 0x09 -#define CR_ULP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4)) - -/* Alias word address of FWU bit */ -#define FWU_BitNumber 0x0A -#define CR_FWU_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of EWUP bit */ -#define CSR_OFFSET (PWR_OFFSET + 0x04) -#define EWUP_BitNumber 0x08 -#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) - -/* ------------------ PWR registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) -#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) -#define CR_VOS_MASK ((uint32_t)0xFFFFE7FF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** @defgroup PWR_Group1 RTC Domain Access function - * @brief RTC Domain Access function - * -@verbatim - =============================================================================== - RTC Domain Access function - =============================================================================== - - After reset, the RTC Registers (RCC CSR Register, RTC registers and RTC backup - registers) are protected against possible stray write accesses. - To enable access to RTC domain use the PWR_RTCAccessCmd(ENABLE) function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @note Before calling this function, the VOS[1:0] bits should be configured - * to "10" and the system frequency has to be configured accordingly. - * To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig() - * function. - * @note ULP and FWU bits are not reset by this function. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/** - * @brief Enables or disables access to the RTC and backup registers. - * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the - * RTC Domain Access should be kept enabled. - * @param NewState: new state of the access to the RTC and backup registers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_RTCAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group2 PVD configuration functions - * @brief PVD configuration functions - * -@verbatim - =============================================================================== - PVD configuration functions - =============================================================================== - - - The PVD is used to monitor the VDD power supply by comparing it to a threshold - selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - - The PVD can use an external input analog voltage (PVD_IN) which is compared - internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode - when PWR_PVDLevel_7 is selected (PLS[2:0] = 111). - - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the - PVD threshold. This event is internally connected to the EXTI line16 - and can generate an interrupt if enabled through the EXTI registers. - - The PVD is stopped in Standby mode. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param PWR_PVDLevel: specifies the PVD detection level - * This parameter can be one of the following values: - * @arg PWR_PVDLevel_0: PVD detection level set to 1.9V - * @arg PWR_PVDLevel_1: PVD detection level set to 2.1V - * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V - * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V - * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V - * @arg PWR_PVDLevel_5: PVD detection level set to 2.9V - * @arg PWR_PVDLevel_6: PVD detection level set to 3.1V - * @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT) - * @retval None - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); - - tmpreg = PWR->CR; - - /* Clear PLS[7:5] bits */ - tmpreg &= CR_PLS_MASK; - - /* Set PLS[7:5] bits according to PWR_PVDLevel value */ - tmpreg |= PWR_PVDLevel; - - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the Power Voltage Detector(PVD). - * @param NewState: new state of the PVD. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group3 WakeUp pins configuration functions - * @brief WakeUp pins configuration functions - * -@verbatim - =============================================================================== - WakeUp pins configuration functions - =============================================================================== - - - WakeUp pins are used to wakeup the system from Standby mode. These pins are - forced in input pull down configuration and are active on rising edges. - - There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and - WakeUp Pin 3 on PE.06. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param PWR_WakeUpPin: specifies the WakeUpPin. - * This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3. - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin)); - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - tmp = CSR_EWUP_BB + PWR_WakeUpPin; - - *(__IO uint32_t *) (tmp) = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group4 Ultra Low Power mode configuration functions - * @brief Ultra Low Power mode configuration functions - * -@verbatim - =============================================================================== - Ultra Low Power mode configuration functions - =============================================================================== - - - The internal voltage reference consumption is not negligible, in particular - in Stop and Standby mode. To reduce power consumption, use the PWR_UltraLowPowerCmd() - function (ULP bit (Ultra low power) in the PWR_CR register) to disable the - internal voltage reference. However, in this case, when exiting from the - Stop/Standby mode, the functions managed through the internal voltage reference - are not reliable during the internal voltage reference startup time (up to 3 ms). - To reduce the wakeup time, the device can exit from Stop/Standby mode without - waiting for the internal voltage reference startup time. This is performed - by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast - wakeup) in the PWR_CR register) before entering Stop/Standby mode. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the Fast WakeUp from Ultra Low Power mode. - * @param NewState: new state of the Fast WakeUp functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_FastWakeUpCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Ultra Low Power mode. - * @param NewState: new state of the Ultra Low Power mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_UltraLowPowerCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group5 Voltage Scaling configuration functions - * @brief Voltage Scaling configuration functions - * -@verbatim - =============================================================================== - Voltage Scaling configuration functions - =============================================================================== - - - The dynamic voltage scaling is a power management technique which consists in - increasing or decreasing the voltage used for the digital peripherals (VCORE), - according to the circumstances. - - Depending on the device voltage range, the maximum frequency and FLASH wait - state should be adapted accordingly: - - +------------------------------------------------------------------+ - | Wait states | HCLK clock frequency (MHz) | - | |------------------------------------------------| - | (Latency) | voltage range | voltage range | - | | 1.65 V - 3.6 V | 2.0 V - 3.6 V | - | |----------------|---------------|---------------| - | | Range 3 | Range 2 | Range 1 | - | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V | - |---------------- |----------------|---------------|---------------| - | 0WS(1CPU cycle) |0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 | - |-----------------|----------------|---------------|---------------| - | 1WS(2CPU cycle) |2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| - |-----------------|----------------|---------------|---------------| - | CPU Performance | Low | Medium | High | - |-----__----------|----------------|---------------|---------------| - |Power Performance| High | Medium | Low | - +------------------------------------------------------------------+ - - - To modify the Product voltage range, user application has to: - - Check VDD to identify which ranges are allowed (see table above) - - Check the PWR_FLAG_VOSF (Voltage Scaling update ongoing) using the PWR_GetFlagStatus() - function and wait until it is reset. - - Configure the Voltage range using the PWR_VoltageScalingConfig() function. - - - When VCORE range 1 is selected and VDD drops below 2.0 V, the application must - reconfigure the system: - - Detect that VDD drops below 2.0 V using the PVD Level 1 - - Adapt the clock frequency to the voltage range that will be selected at next step - - Select the required voltage range - - When VCORE range 2 or range 3 is selected and VDD drops below 2.0 V, no system - reconfiguration is required. - - - When VDD is above 2.0 V, any of the 3 voltage ranges can be selected - - When the voltage range is above the targeted voltage range (e.g. from range - 1 to 2): - - Adapt the clock frequency to the lower voltage range that will be selected - at next step. - - Select the required voltage range. - - When the voltage range is below the targeted voltage range (e.g. from range - 3 to 1): - - Select the required voltage range. - - Tune the clock frequency if needed. - - - When VDD is below 2.0 V, only range 2 and 3 can be selected: - - From range 2 to range 3 - - Adapt the clock frequency to voltage range 3. - - Select voltage range 3. - - From range 3 to range 2 - - Select the voltage range 2. - - Tune the clock frequency if needed. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage scaling range. - * @note During voltage scaling configuration, the system clock is stopped - * until the regulator is stabilized (VOSF = 0). This must be taken - * into account during application developement, in case a critical - * reaction time to interrupt is needed, and depending on peripheral - * used (timer, communication,...). - * - * @param PWR_VoltageScaling: specifies the voltage scaling range. - * This parameter can be: - * @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1 (VCORE = 1.8V) - * @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2 (VCORE = 1.5V) - * @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3 (VCORE = 1.2V) - * @retval None - */ -void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling)); - - tmp = PWR->CR; - - tmp &= CR_VOS_MASK; - tmp |= PWR_VoltageScaling; - - PWR->CR = tmp & 0xFFFFFFF3; - -} - -/** - * @} - */ - -/** @defgroup PWR_Group6 Low Power modes configuration functions - * @brief Low Power modes configuration functions - * -@verbatim - =============================================================================== - Low Power modes configuration functions - =============================================================================== - - The devices feature five low-power modes: - - Low power run mode: regulator in low power mode, limited clock frequency, - limited number of peripherals running. - - Sleep mode: Cortex-M3 core stopped, peripherals kept running. - - Low power sleep mode: Cortex-M3 core stopped, limited clock frequency, - limited number of peripherals running, regulator in low power mode. - - Stop mode: all clocks are stopped, regulator running, regulator in low power mode - - Standby mode: VCORE domain powered off - - Low power run mode (LP run) - =========================== - - Entry: - - Decrease the system frequency. - - The regulator is forced in low power mode using the PWR_EnterLowPowerRunMode() - function. - - Exit: - - The regulator is forced in Main regulator mode sing the PWR_EnterLowPowerRunMode() - function. - - Increase the system frequency if needed. - - Sleep mode - =========== - - Entry: - - The Sleep mode is entered by using the PWR_EnterSleepMode(PWR_Regulator_ON,) - function with regulator ON. - - Exit: - - Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - Low power sleep mode (LP sleep) - =============================== - - Entry: - - The Flash memory must be switched off by using the FLASH_SLEEPPowerDownCmd() - function. - - Decrease the system frequency. - - The regulator is forced in low power mode and the WFI or WFE instructions - are executed using the PWR_EnterSleepMode(PWR_Regulator_LowPower,) function - with regulator in LowPower. - - Exit: - - Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep LP mode. - - Stop mode - ========== - In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, - the HSI and the HSE RC oscillators are disabled. Internal SRAM and register - contents are preserved. - The voltage regulator can be configured either in normal or low-power mode. - To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature - sensor can be switched off before entering the Stop mode. They can be switched - on again by software after exiting the Stop mode using the PWR_UltraLowPowerCmd() - function. - - - Entry: - - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) - function with regulator in LowPower or with Regulator ON. - - Exit: - - Any EXTI Line (Internal or External) configured in Interrupt/Event mode. - - Standby mode - ============ - The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M3 deepsleep mode, with the voltage regulator disabled. - The VCORE domain is consequently powered off. The PLL, the MSI, the HSI - oscillator and the HSE oscillator are also switched off. SRAM and register - contents are lost except for the RTC registers, RTC backup registers and - Standby circuitry. - - The voltage regulator is OFF. - - To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature - sensor can be switched off before entering the Standby mode. They can be switched - on again by software after exiting the Standby mode using the PWR_UltraLowPowerCmd() - function. - - - Entry: - - The Standby mode is entered using the PWR_EnterSTANDBYMode() function. - - Exit: - - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, - tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - - Auto-wakeup (AWU) from low-power mode - ===================================== - The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event, a time-stamp event, or a comparator event, - without depending on an external interrupt (Auto-wakeup mode). - - - RTC auto-wakeup (AWU) from the Stop mode - ---------------------------------------- - - - To wake up from the Stop mode with an RTC alarm event, it is necessary to: - - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - - To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to: - - Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - - Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: - - Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - - - RTC auto-wakeup (AWU) from the Standby mode - ------------------------------------------- - - To wake up from the Standby mode with an RTC alarm event, it is necessary to: - - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - - To wake up from the Standby mode with an RTC Tamper or time stamp event, it - is necessary to: - - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - - Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: - - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - - - Comparator auto-wakeup (AWU) from the Stop mode - ----------------------------------------------- - - To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup - event, it is necessary to: - - Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 - to be sensitive to to the selected edges (falling, rising or falling - and rising) (Interrupt or Event modes) using the EXTI_Init() function. - - Configure the comparator to generate the event. - -@endverbatim - * @{ - */ - -/** - * @brief Enters/Exits the Low Power Run mode. - * @note Low power run mode can only be entered when VCORE is in range 2. - * In addition, the dynamic voltage scaling must not be used when Low - * power run mode is selected. Only Stop and Sleep modes with regulator - * configured in Low power mode is allowed when Low power run mode is - * selected. - * @note In Low power run mode, all I/O pins keep the same state as in Run mode. - * @param NewState: new state of the Low Power Run mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_EnterLowPowerRunMode(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - PWR->CR |= PWR_CR_LPSDSR; - PWR->CR |= PWR_CR_LPRUN; - } - else - { - PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN); - PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR); - } -} - -/** - * @brief Enters Sleep mode. - * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * @param PWR_Regulator: specifies the regulator state in Sleep mode. - * This parameter can be one of the following values: - * @arg PWR_Regulator_ON: Sleep mode with regulator ON - * @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode - * @note Low power sleep mode can only be entered when VCORE is in range 2. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Low power sleep mode. - * - * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction - * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction - * @retval None - */ -void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - - assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry)); - - /* Select the regulator state in Sleep mode ---------------------------------*/ - tmpreg = PWR->CR; - - /* Clear PDDS and LPDSR bits */ - tmpreg &= CR_DS_MASK; - - /* Set LPDSR bit according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); - - /* Select SLEEP mode entry -------------------------------------------------*/ - if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } -} - -/** - * @brief Enters STOP mode. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the MSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_Regulator_ON: STOP mode with regulator ON - * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDSR bits */ - tmpreg &= CR_DS_MASK; - - /* Set LPDSR bit according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); -} - -/** - * @brief Enters STANDBY mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, - * time-stamp, RTC Alarm out, or RTC clock calibration out. - * - WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled. - * @param None - * @retval None - */ -void PWR_EnterSTANDBYMode(void) -{ - /* Clear Wakeup flag */ - PWR->CR |= PWR_CR_CWUF; - - /* Select STANDBY mode */ - PWR->CR |= PWR_CR_PDDS; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP; - -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM ) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @} - */ - -/** @defgroup PWR_Group7 Flags management functions - * @brief Flags management functions - * -@verbatim - =============================================================================== - Flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), - * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the PWR_PVDCmd() function. - * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This - * flag indicates the state of the internal voltage reference, VREFINT. - * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for - * the internal regulator to be ready after the voltage range is changed. - * The VOSF flag indicates that the regulator has reached the voltage level - * defined with bits VOS[1:0] of PWR_CR register. - * @arg PWR_FLAG_REGLP: Regulator LP flag. This flag is set by hardware - * when the MCU is in Low power run mode. - * When the MCU exits from Low power run mode, this flag stays SET until - * the regulator is ready in main mode. A polling on this flag is - * recommended to wait for the regulator main mode. - * This flag is RESET by hardware when the regulator is ready. - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the PWR's pending flags. - * @param PWR_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @retval None - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - - PWR->CR |= PWR_FLAG << 2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_rcc.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_rcc.c deleted file mode 100644 index dbce5fa2f..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_rcc.c +++ /dev/null @@ -1,1575 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_rcc.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the Reset and clock control (RCC) peripheral: - * - Internal/external clocks, PLL, CSS and MCO configuration - * - System, AHB and APB busses clocks configuration - * - Peripheral clocks configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * RCC specific features - * =================================================================== - * - * After reset the device is running from MSI (2 MHz) with Flash 0 WS, - * all peripherals are off except internal SRAM, Flash and JTAG. - * - There is no prescaler on High speed (AHB) and Low speed (APB) busses; - * all peripherals mapped on these busses are running at MSI speed. - * - The clock for all peripherals is switched off, except the SRAM and FLASH. - * - All GPIOs are in input floating state, except the JTAG pins which - * are assigned to be used for debug purpose. - * - * Once the device started from reset, the user application has to: - * - Configure the clock source to be used to drive the System clock - * (if the application needs higher frequency/performance) - * - Configure the System clock frequency and Flash settings - * - Configure the AHB and APB busses prescalers - * - Enable the clock for the peripheral(s) to be used - * - Configure the clock source(s) for peripherals whose clocks are not - * derived from the System clock (ADC, RTC/LCD and IWDG) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_rcc.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ------------ RCC registers bit address in the alias region ----------- */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of HSION bit */ -#define CR_OFFSET (RCC_OFFSET + 0x00) -#define HSION_BitNumber 0x00 -#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) - -/* Alias word address of MSION bit */ -#define MSION_BitNumber 0x08 -#define CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4)) - -/* Alias word address of PLLON bit */ -#define PLLON_BitNumber 0x18 -#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) - -/* Alias word address of CSSON bit */ -#define CSSON_BitNumber 0x1C -#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of LSION bit */ -#define CSR_OFFSET (RCC_OFFSET + 0x34) -#define LSION_BitNumber 0x00 -#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) - -/* Alias word address of RTCEN bit */ -#define RTCEN_BitNumber 0x16 -#define CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4)) - -/* Alias word address of RTCRST bit */ -#define RTCRST_BitNumber 0x17 -#define CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4)) - - -/* ---------------------- RCC registers mask -------------------------------- */ -/* RCC Flag Mask */ -#define FLAG_MASK ((uint8_t)0x1F) - -/* CR register byte 3 (Bits[23:16]) base address */ -#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) - -/* ICSCR register byte 4 (Bits[31:24]) base address */ -#define ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807) - -/* CFGR register byte 3 (Bits[23:16]) base address */ -#define CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A) - -/* CFGR register byte 4 (Bits[31:24]) base address */ -#define CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B) - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E) - -/* CSR register byte 2 (Bits[15:8]) base address */ -#define CSR_BYTE2_ADDRESS ((uint32_t)0x40023835) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions - * @brief Internal and external clocks, PLL, CSS and MCO configuration functions - * -@verbatim - =============================================================================== - Internal/external clocks, PLL, CSS and MCO configuration functions - =============================================================================== - - This section provide functions allowing to configure the internal/external clocks, - PLL, CSS and MCO. - - 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - - 2. MSI (multi-speed internal), multispeed low power RC (65.536 KHz to 4.194 MHz) - MHz used as System clock source. - - 3. LSI (low-speed internal), 37 KHz low consumption RC used as IWDG and/or RTC - clock source. - - 4. HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - 5. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - 6. PLL (clocked by HSI or HSE), for System clock and USB (48 MHz). - - 7. CSS (Clock security system), once enable and if a HSE clock failure occurs - (HSE used directly or through PLL as System clock source), the System clock - is automatically switched to MSI and an interrupt is generated if enabled. - The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) - exception vector. - - 8. MCO (microcontroller clock output), used to output SYSCLK, HSI, MSI, HSE, PLL, - LSI or LSE clock (through a configurable prescaler) on PA8 pin. - -@endverbatim - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note - The default reset state of the clock configuration is given below: - * - MSI ON and used as system clock source (MSI range is not modified - * by this function, it keep the value configured by user application) - * - HSI, HSE and PLL OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS and MCO OFF - * - All interrupts disabled - * - However, this function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - - /* Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100; - - /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t)0x88FFC00C; - - /* Reset HSION, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xEEFEFFFE; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note - After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * - HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * - The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the Clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint8_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; - - /* Set the new HSE configuration -------------------------------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; - -} - -/** - * @brief Waits for HSE start-up. - * @note This functions waits on HSERDY flag to be set and return SUCCESS if - * this flag is set, otherwise returns ERROR if the timeout is reached - * and this flag is not set. The timeout value is defined by the constant - * HSE_STARTUP_TIMEOUT in stm32l1xx.h file. You can tailor it depending - * on the HSE crystal used in your application. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t StartUpCounter = 0; - ErrorStatus status = ERROR; - FlagStatus HSEStatus = RESET; - - /* Wait till HSE is ready and if timeout is reached exit */ - do - { - HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - StartUpCounter++; - } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal Multi Speed oscillator (MSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal MSI RC. - * Refer to the Application Note AN3300 for more details on how to - * calibrate the MSI. - * @param MSICalibrationValue: specifies the MSI calibration trimming value. - * This parameter must be a number between 0 and 0xFF. - * @retval None - */ -void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue) -{ - - /* Check the parameters */ - assert_param(IS_RCC_MSI_CALIBRATION_VALUE(MSICalibrationValue)); - - *(__IO uint8_t *) ICSCR_BYTE4_ADDRESS = MSICalibrationValue; -} - -/** - * @brief Configures the Internal Multi Speed oscillator (MSI) clock range. - * @note - After restart from Reset or wakeup from STANDBY, the MSI clock is - * around 2.097 MHz. The MSI clock does not change after wake-up from - * STOP mode. - * - The MSI clock range can be modified on the fly. - * @param RCC_MSIRange: specifies the MSI Clock range. - * This parameter must be one of the following values: - * @arg RCC_MSIRange_0: MSI clock is around 65.536 KHz - * @arg RCC_MSIRange_1: MSI clock is around 131.072 KHz - * @arg RCC_MSIRange_2: MSI clock is around 262.144 KHz - * @arg RCC_MSIRange_3: MSI clock is around 524.288 KHz - * @arg RCC_MSIRange_4: MSI clock is around 1.048 MHz - * @arg RCC_MSIRange_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) - * @arg RCC_MSIRange_6: MSI clock is around - * - * @retval None - */ -void RCC_MSIRangeConfig(uint32_t RCC_MSIRange) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_MSIRange)); - - tmpreg = RCC->ICSCR; - - /* Clear MSIRANGE[2:0] bits */ - tmpreg &= ~RCC_ICSCR_MSIRANGE; - - /* Set the MSIRANGE[2:0] bits according to RCC_MSIRange value */ - tmpreg |= (uint32_t)RCC_MSIRange; - - /* Store the new value */ - RCC->ICSCR = tmpreg; -} - -/** - * @brief Enables or disables the Internal Multi Speed oscillator (MSI). - * @note - The MSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after - * startup from Reset, wakeup from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * - MSI can not be stopped if it is used as system clock source. - * In this case, you have to select another source of the system - * clock then stop the MSI. - * - After enabling the MSI, the application software should wait on - * MSIRDY flag to be set indicating that MSI clock is stable and can - * be used as system clock source. - * @param NewState: new state of the MSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator - * clock cycles. - * @retval None - */ -void RCC_MSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_MSION_BB = (uint32_t)NewState; -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * Refer to the Application Note AN3300 for more details on how to - * calibrate the HSI. - * @param HSICalibrationValue: specifies the HSI calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue)); - - tmpreg = RCC->ICSCR; - - /* Clear HSITRIM[4:0] bits */ - tmpreg &= ~RCC_ICSCR_HSITRIM; - - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 8; - - /* Store the new value */ - RCC->ICSCR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note - After enabling the HSI, the application software should wait on - * HSIRDY flag to be set indicating that HSI clock is stable and can - * be used to clock the PLL and/or system clock. - * - HSI can not be stopped if it is used directly or through the PLL - * as system clock. In this case, you have to select another source - * of the system clock then stop the HSI. - * - The HSI is stopped by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the HSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @note - As the LSE is in the RTC domain and write access is denied to this - * domain after reset, you have to enable write access using - * PWR_RTCAccessCmd(ENABLE) function before to configure the LSE - * (to be done once after reset). - * - After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg RCC_LSE_ON: turn ON the LSE oscillator - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE_OFF; - - /* Set the new LSE configuration -------------------------------------------*/ - *(__IO uint8_t *) CSR_BYTE2_ADDRESS = RCC_LSE; -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note - After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * - LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the PLL clock source and multiplication factor. - * @note This function must be used only when the PLL is disabled. - * - * @param RCC_PLLSource: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock source - * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock source - * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as - * PLL source). - * - * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock - * This parameter can be: - * @arg RCC_PLLMul_3: PLL clock source multiplied by 3 - * @arg RCC_PLLMul_4: PLL clock source multiplied by 4 - * @arg RCC_PLLMul_6: PLL clock source multiplied by 6 - * @arg RCC_PLLMul_8: PLL clock source multiplied by 8 - * @arg RCC_PLLMul_12: PLL clock source multiplied by 12 - * @arg RCC_PLLMul_16: PLL clock source multiplied by 16 - * @arg RCC_PLLMul_24: PLL clock source multiplied by 24 - * @arg RCC_PLLMul_32: PLL clock source multiplied by 32 - * @arg RCC_PLLMul_48: PLL clock source multiplied by 48 - * @note The application software must set correctly the PLL multiplication - * factor to avoid exceeding - * - 96 MHz as PLLVCO when the product is in range 1 - * - 48 MHz as PLLVCO when the product is in range 2 - * - 24 MHz when the product is in range 3 - * @note When using the USB the PLLVCO should be 96MHz - * - * @param RCC_PLLDiv: specifies the PLL division factor. - * This parameter can be: - * @arg RCC_PLLDiv_2: PLL Clock output divided by 2 - * @arg RCC_PLLDiv_3: PLL Clock output divided by 3 - * @arg RCC_PLLDiv_4: PLL Clock output divided by 4 - * @note The application software must set correctly the output division to avoid - * exceeding 32 MHz as SYSCLK. - * - * @retval None - */ -void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_PLLMul)); - assert_param(IS_RCC_PLL_DIV(RCC_PLLDiv)); - - *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = (uint8_t)(RCC_PLLSource | ((uint8_t)(RCC_PLLMul | (uint8_t)(RCC_PLLDiv)))); -} - -/** - * @brief Enables or disables the PLL. - * @note - After enabling the PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * - The PLL can not be disabled if it is used as system clock source - * - The PLL is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the PLL. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. - * @param NewState: new state of the Clock Security System. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the clock source to output on MCO pin (PA8). - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCOSource: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCOSource_NoClock: No clock selected - * @arg RCC_MCOSource_SYSCLK: System clock selected - * @arg RCC_MCOSource_HSI: HSI oscillator clock selected - * @arg RCC_MCOSource_MSI: MSI oscillator clock selected - * @arg RCC_MCOSource_HSE: HSE oscillator clock selected - * @arg RCC_MCOSource_PLLCLK: PLL clock selected - * @arg RCC_MCOSource_LSI: LSI clock selected - * @arg RCC_MCOSource_LSE: LSE clock selected - * @param RCC_MCODiv: specifies the MCO prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCODiv_1: no division applied to MCO clock - * @arg RCC_MCODiv_2: division by 2 applied to MCO clock - * @arg RCC_MCODiv_4: division by 4 applied to MCO clock - * @arg RCC_MCODiv_8: division by 8 applied to MCO clock - * @arg RCC_MCODiv_16: division by 16 applied to MCO clock - * @retval None - */ -void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv) -{ - /* Check the parameters */ - assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource)); - assert_param(IS_RCC_MCO_DIV(RCC_MCODiv)); - - /* Select MCO clock source and prescaler */ - *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCOSource | RCC_MCODiv; -} - -/** - * @} - */ - -/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions - * @brief System, AHB and APB busses clocks configuration functions - * -@verbatim - =============================================================================== - System, AHB and APB busses clocks configuration functions - =============================================================================== - - This section provide functions allowing to configure the System, AHB, APB1 and - APB2 busses clocks. - - 1. Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable prescaler - and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO). - APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through - configurable prescalers and used to clock the peripherals mapped on these busses. - You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. - -Note: All the peripheral clocks are derived from the System clock (SYSCLK) except: -==== - The USB 48 MHz clock which is derived from the PLL VCO clock. - - The ADC clock which is always the HSI clock. A divider by 1, 2 or 4 allows - to adapt the clock frequency to the device operating conditions. - - The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC (HSE - divided by a programmable prescaler). - The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD - clock frequency. - - IWDG clock which is always the LSI clock. - - 2. The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32 MHz. - Depending on the device voltage range, the maximum frequency should be - adapted accordingly: - +----------------------------------------------------------------+ - | Wait states | HCLK clock frequency (MHz) | - | |------------------------------------------------| - | (Latency) | voltage range | voltage range | - | | 1.65 V - 3.6 V | 2.0 V - 3.6 V | - | |----------------|---------------|---------------| - | | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V | - |-------------- |----------------|---------------|---------------| - |0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 | - |---------------|----------------|---------------|---------------| - |1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32| - +----------------------------------------------------------------+ - - 3. After reset, the System clock source is the MSI (2 MHz) with 0 WS, Flash - 32-bit access is enabled and prefetch is disabled. - - It is recommended to use the following software sequences to tune the number - of wait states needed to access the Flash memory with the CPU frequency (HCLK). - - Increasing the CPU frequency (in the same voltage range) - - Program the Flash 64-bit access, using "FLASH_ReadAccess64Cmd(ENABLE)" function - - Check that 64-bit access is taken into account by reading FLASH_ACR - - Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function - - Check that the new number of WS is taken into account by reading FLASH_ACR - - Modify the CPU clock source, using "RCC_SYSCLKConfig()" function - - If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function - - Check that the new CPU clock source is taken into account by reading - the clock source status, using "RCC_GetSYSCLKSource()" function - - Decreasing the CPU frequency (in the same voltage range) - - Modify the CPU clock source, using "RCC_SYSCLKConfig()" function - - If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function - - Check that the new CPU clock source is taken into account by reading - the clock source status, using "RCC_GetSYSCLKSource()" function - - Program the new number of WS, using "FLASH_SetLatency()" function - - Check that the new number of WS is taken into account by reading FLASH_ACR - - Enable the Flash 32-bit access, using "FLASH_ReadAccess64Cmd(DISABLE)" function - - Check that 32-bit access is taken into account by reading FLASH_ACR - -@endverbatim - * @{ - */ - -/** - * @brief Configures the system clock (SYSCLK). - * @note - The MSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * - A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use RCC_GetSYSCLKSource() function to know which clock is - * currently used as system clock source. - * @param RCC_SYSCLKSource: specifies the clock source used as system clock source - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_MSI: MSI selected as system clock source - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - - tmpreg = RCC->CFGR; - - /* Clear SW[1:0] bits */ - tmpreg &= ~RCC_CFGR_SW; - - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can be one - * of the following values: - * - 0x00: MSI used as system clock - * - 0x04: HSI used as system clock - * - 0x08: HSE used as system clock - * - 0x0C: PLL used as system clock - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @note Depending on the device voltage range, the software has to set correctly - * these bits to ensure that the system frequency does not exceed the - * maximum allowed frequency (for more details refer to section above - * "CPU, AHB and APB busses clocks configuration functions") - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - - tmpreg = RCC->CFGR; - - /* Clear HPRE[3:0] bits */ - tmpreg &= ~RCC_CFGR_HPRE; - - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB1 clock = HCLK - * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE1[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE1; - - /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB2 clock = HCLK - * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE2[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE2; - - /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK << 3; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the frequencies of the System, AHB and APB busses clocks. - * @note - The frequency returned by this function is not the real frequency - * in the chip. It is calculated based on the predefined constant and - * the source selected by RCC_SYSCLKConfig(): - * - * - If SYSCLK source is MSI, function returns constant the MSI value - * as defined by the MSI range, refer to RCC_MSIRangeConfig() - * - * - If SYSCLK source is HSI, function returns constant HSI_VALUE(*) - * - * - If SYSCLK source is HSE, function returns constant HSE_VALUE(**) - * - * - If SYSCLK source is PLL, function returns constant HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue(). - * - * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * return wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, presc = 0, msirange = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13; - RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1))); - break; - case 0x04: /* HSI used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - case 0x08: /* HSE used as system clock */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - case 0x0C: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; - plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; - pllmul = PLLMulTable[(pllmul >> 18)]; - plldiv = (plldiv >> 22) + 1; - - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - - if (pllsource == 0x00) - { - /* HSI oscillator clock selected as PLL clock source */ - RCC_Clocks->SYSCLK_Frequency = (((HSI_VALUE) * pllmul) / plldiv); - } - else - { - /* HSE selected as PLL clock source */ - RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE) * pllmul) / plldiv); - } - break; - default: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13; - RCC_Clocks->SYSCLK_Frequency = (32768 * (1 << (msirange + 1))); - break; - } - /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ - /* Get HCLK prescaler */ - tmp = RCC->CFGR & RCC_CFGR_HPRE; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - - /* Get PCLK1 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE1; - tmp = tmp >> 8; - presc = APBAHBPrescTable[tmp]; - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - - /* Get PCLK2 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE2; - tmp = tmp >> 11; - presc = APBAHBPrescTable[tmp]; - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; -} - -/** - * @} - */ - -/** @defgroup RCC_Group3 Peripheral clocks configuration functions - * @brief Peripheral clocks configuration functions - * -@verbatim - =============================================================================== - Peripheral clocks configuration functions - =============================================================================== - - This section provide functions allowing to configure the Peripheral clocks. - - 1. The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC (HSE - divided by a programmable prescaler). - - 2. After restart from Reset or wakeup from STANDBY, all peripherals are off - except internal SRAM, Flash and JTAG. Before to start using a peripheral you - have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd() - , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. - - 3. To reset the peripherals configuration (to the default state after device reset) - you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and - RCC_APB1PeriphResetCmd() functions. - - 4. To further reduce power consumption in SLEEP mode the peripheral clocks can - be disabled prior to executing the WFI or WFE instructions. You can do this - using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and - RCC_APB1PeriphClockLPModeCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC and LCD clock (RTCCLK / LCDCLK). - * @note - As the RTC clock configuration bits are in the RTC domain and write - * access is denied to this domain after reset, you have to enable write - * access using PWR_RTCAccessCmd(ENABLE) function before to configure - * the RTC clock source (to be done once after reset). - * - Once the RTC clock is configured it can't be changed unless the RTC - * is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR) - * - The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK). - * - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock - * - * @note - If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * - * - The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - * - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - - if ((RCC_RTCCLKSource & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) - { - /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ - tmpreg = RCC->CR; - - /* Clear RTCPRE[1:0] bits */ - tmpreg &= ~RCC_CR_RTCPRE; - - /* Configure HSE division factor for RTC clock */ - tmpreg |= (RCC_RTCCLKSource & RCC_CR_RTCPRE); - - /* Store the new value */ - RCC->CR = tmpreg; - } - - RCC->CSR &= ~RCC_CSR_RTCSEL; - - /* Select the RTC clock source */ - RCC->CSR |= (RCC_RTCCLKSource & RCC_CSR_RTCSEL); -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock source was selected - * using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_RTCEN_BB = (uint32_t)NewState; -} - -/** - * @brief Forces or releases the RTC peripheral and associated resources reset. - * @note This function resets the RTC peripheral, RTC clock source selection - * (in RCC_CSR) and the backup registers. - * @param NewState: new state of the RTC reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_RTCRST_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the AHB peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_GPIOA - * @arg RCC_AHBPeriph_GPIOB - * @arg RCC_AHBPeriph_GPIOC - * @arg RCC_AHBPeriph_GPIOD - * @arg RCC_AHBPeriph_GPIOE - * @arg RCC_AHBPeriph_GPIOH - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) - * @arg RCC_AHBPeriph_DMA1 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBENR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_SYSCFG - * @arg RCC_APB2Periph_TIM9 - * @arg RCC_APB2Periph_TIM10 - * @arg RCC_APB2Periph_TIM11 - * @arg RCC_APB2Periph_ADC1 - * @arg RCC_APB2Periph_SPI1 - * @arg RCC_APB2Periph_USART1 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2 - * @arg RCC_APB1Periph_TIM3 - * @arg RCC_APB1Periph_TIM4 - * @arg RCC_APB1Periph_TIM6 - * @arg RCC_APB1Periph_TIM7 - * @arg RCC_APB1Periph_LCD - * @arg RCC_APB1Periph_WWDG - * @arg RCC_APB1Periph_SPI2 - * @arg RCC_APB1Periph_USART2 - * @arg RCC_APB1Periph_USART3 - * @arg RCC_APB1Periph_I2C1 - * @arg RCC_APB1Periph_I2C2 - * @arg RCC_APB1Periph_USB - * @arg RCC_APB1Periph_PWR - * @arg RCC_APB1Periph_DAC - * @arg RCC_APB1Periph_COMP - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases AHB peripheral reset. - * @param RCC_AHBPeriph: specifies the AHB peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_GPIOA - * @arg RCC_AHBPeriph_GPIOB - * @arg RCC_AHBPeriph_GPIOC - * @arg RCC_AHBPeriph_GPIOD - * @arg RCC_AHBPeriph_GPIOE - * @arg RCC_AHBPeriph_GPIOH - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) - * @arg RCC_AHBPeriph_DMA1 - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBRSTR |= RCC_AHBPeriph; - } - else - { - RCC->AHBRSTR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_SYSCFG - * @arg RCC_APB2Periph_TIM9 - * @arg RCC_APB2Periph_TIM10 - * @arg RCC_APB2Periph_TIM11 - * @arg RCC_APB2Periph_ADC1 - * @arg RCC_APB2Periph_SPI1 - * @arg RCC_APB2Periph_USART1 - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2 - * @arg RCC_APB1Periph_TIM3 - * @arg RCC_APB1Periph_TIM4 - * @arg RCC_APB1Periph_TIM6 - * @arg RCC_APB1Periph_TIM7 - * @arg RCC_APB1Periph_LCD - * @arg RCC_APB1Periph_WWDG - * @arg RCC_APB1Periph_SPI2 - * @arg RCC_APB1Periph_USART2 - * @arg RCC_APB1Periph_USART3 - * @arg RCC_APB1Periph_I2C1 - * @arg RCC_APB1Periph_I2C2 - * @arg RCC_APB1Periph_USB - * @arg RCC_APB1Periph_PWR - * @arg RCC_APB1Periph_DAC - * @arg RCC_APB1Periph_COMP - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Enables or disables the AHB peripheral clock during SLEEP mode. - * @note - Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * - After wakeup from SLEEP mode, the peripheral clock is enabled again. - * - By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHBPeriph_GPIOA - * @arg RCC_AHBPeriph_GPIOB - * @arg RCC_AHBPeriph_GPIOC - * @arg RCC_AHBPeriph_GPIOD - * @arg RCC_AHBPeriph_GPIOE - * @arg RCC_AHBPeriph_GPIOH - * @arg RCC_AHBPeriph_CRC - * @arg RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode) - * @arg RCC_AHBPeriph_SRAM - * @arg RCC_AHBPeriph_DMA1 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB_LPMODE_PERIPH(RCC_AHBPeriph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHBLPENR |= RCC_AHBPeriph; - } - else - { - RCC->AHBLPENR &= ~RCC_AHBPeriph; - } -} - -/** - * @brief Enables or disables the APB2 peripheral clock during SLEEP mode. - * @note - Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * - After wakeup from SLEEP mode, the peripheral clock is enabled again. - * - By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_SYSCFG - * @arg RCC_APB2Periph_TIM9 - * @arg RCC_APB2Periph_TIM10 - * @arg RCC_APB2Periph_TIM11 - * @arg RCC_APB2Periph_ADC1 - * @arg RCC_APB2Periph_SPI1 - * @arg RCC_APB2Periph_USART1 - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2LPENR |= RCC_APB2Periph; - } - else - { - RCC->APB2LPENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the APB1 peripheral clock during SLEEP mode. - * @note - Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * - After wakeup from SLEEP mode, the peripheral clock is enabled again. - * - By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2 - * @arg RCC_APB1Periph_TIM3 - * @arg RCC_APB1Periph_TIM4 - * @arg RCC_APB1Periph_TIM6 - * @arg RCC_APB1Periph_TIM7 - * @arg RCC_APB1Periph_LCD - * @arg RCC_APB1Periph_WWDG - * @arg RCC_APB1Periph_SPI2 - * @arg RCC_APB1Periph_USART2 - * @arg RCC_APB1Periph_USART3 - * @arg RCC_APB1Periph_I2C1 - * @arg RCC_APB1Periph_I2C2 - * @arg RCC_APB1Periph_USB - * @arg RCC_APB1Periph_PWR - * @arg RCC_APB1Periph_DAC - * @arg RCC_APB1Periph_COMP - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1LPENR |= RCC_APB1Periph; - } - else - { - RCC->APB1LPENR &= ~RCC_APB1Periph; - } -} - -/** - * @} - */ - -/** @defgroup RCC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RCC interrupts. - * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled - * and if the HSE clock fails, the CSS interrupt occurs and an NMI is - * automatically generated. The NMI will be executed indefinitely, and - * since NMI has higher priority than any other IRQ (and main program) - * the application will be stacked in the NMI ISR unless the CSS interrupt - * pending bit is cleared. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_MSIRDY: MSI ready interrupt - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: PLL clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - - if (tmp == 1) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else /* The flag to check is in CSR register (tmp == 2) */ - { - statusreg = RCC->CSR; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_MASK; - - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, - * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= RCC_CSR_RMVF; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_MSIRDY: MSI ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC's interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_MSIRDY: MSI ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_rtc.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_rtc.c deleted file mode 100644 index fbcf67997..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_rtc.c +++ /dev/null @@ -1,2138 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_rtc.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the Real-Time Clock (RTC) peripheral: - * - Initialization - * - Calendar (Time and Date) configuration - * - Alarms (Alarm A and Alarm B) configuration - * - WakeUp Timer configuration - * - Daylight Saving configuration - * - Output pin Configuration - * - Digital Calibration configuration - * - TimeStamp configuration - * - Tampers configuration - * - Backup Data Registers configuration - * - Output Type Config configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * RTC Domain Reset - * =================================================================== - * After power-on reset, the RTC domain (RTC clock source configuration, - * RTC registers and RTC Backup data registers) is reset. You can also - * reset this domain by software using the RCC_RTCResetCmd() function. - * - * =================================================================== - * RTC Operating Condition - * =================================================================== - * As long as the supply voltage remains in the operating range, - * the RTC never stops, regardless of the device status (Run mode, - * low power modes or under reset). - * - * =================================================================== - * RTC Domain Access - * =================================================================== - * After reset, the RTC domain (RTC clock source configuration, - * RTC registers and RTC Backup data registers) are protected against - * possible stray write accesses. - * To enable access to the RTC Domain and RTC registers, proceed as follows: - * - Enable the Power Controller (PWR) APB1 interface clock using the - * RCC_APB1PeriphClockCmd() function. - * - Enable access to RTC domain using the PWR_RTCAccessCmd() function. - * - Select the RTC clock source using the RCC_RTCCLKConfig() function. - * - Enable RTC Clock using the RCC_RTCCLKCmd() function. - * - * =================================================================== - * RTC Driver: how to use it - * =================================================================== - * - Enable the RTC domain access (see description in the section above) - * - Configure the RTC Prescaler (Asynchronous and Synchronous) and - * RTC hour format using the RTC_Init() function. - * - * Time and Date configuration - * =========================== - * - To configure the RTC Calendar (Time and Date) use the RTC_SetTime() - * and RTC_SetDate() functions. - * - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() - * functions. - * - Use the RTC_DayLightSavingConfig() function to add or sub one - * hour to the RTC Calendar. - * - * Alarm configuration - * =================== - * - To configure the RTC Alarm use the RTC_SetAlarm() function. - * - Enable the selected RTC Alarm using the RTC_AlarmCmd() function - * - To read the RTC Alarm, use the RTC_GetAlarm() function. - * - * RTC Wakeup configuration - * ======================== - * - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() - * function. - * - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() - * function - * - Enable the RTC WakeUp using the RTC_WakeUpCmd() function - * - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() - * function. - * - * Outputs configuration - * ===================== - * The RTC has 2 different outputs: - * - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B - * and WaKeUp signals. - * To output the selected RTC signal on RTC_AF1 pin, use the - * RTC_OutputConfig() function. - * - AFO_CALIB: this output is used to manage the RTC Clock divided - * by 64 (512Hz) signal. - * To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd() - * function. - * - * Digital Calibration configuration - * ================================= - * - Configure the RTC Digital Calibration Value and the corresponding - * sign using the RTC_DigitalCalibConfig() function. - * - Enable the RTC Digital Calibration using the RTC_DigitalCalibCmd() - * function - * - * TimeStamp configuration - * ======================= - * - Configure the RTC_AF1 trigger and enables the RTC TimeStamp - * using the RTC_TimeStampCmd() function. - * - To read the RTC TimeStamp Time and Date register, use the - * RTC_GetTimeStamp() function. - * - * Tamper configuration - * ==================== - * - Configure the RTC Tamper trigger using the RTC_TamperConfig() - * function. - * - Enable the RTC Tamper using the RTC_TamperCmd() function. - * - * Backup Data Registers configuration - * =================================== - * - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() - * function. - * - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() - * function. - * - * =================================================================== - * RTC and low power modes - * =================================================================== - * The MCU can be woken up from a low power mode by an RTC alternate - * function. - * The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - * RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - * These RTC alternate functions can wake up the system from the Stop - * and Standby lowpower modes. - * The system can also wake up from low power modes without depending - * on an external interrupt (Auto-wakeup mode), by using the RTC alarm - * or the RTC wakeup events. - * The RTC provides a programmable time base for waking up from the - * Stop or Standby mode at regular intervals. - * Wakeup from STOP and Standby modes is possible only when the RTC - * clock source is LSE or LSI. - * - * =================================================================== - * Selection of RTC_AF1 alternate functions - * =================================================================== - * The RTC_AF1 pin (PC13) can be used for the following purposes: - * - Wakeup pin 2 (WKUP2) using the PWR_WakeUpPinCmd() function. - * - AFO_ALARM output - * - AFO_CALIB output - * - AFI_TAMPER - * - AFI_TIMESTAMP - * - * +------------------------------------------------------------------------------------------+ - * | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2 |ALARMOUTTYPE | - * | configuration | ENABLED | ENABLED | ENABLED | ENABLED |ENABLED | AFO_ALARM | - * | and function | | | | | |Configuration | - * |-----------------|----------|----------|-----------|--------------|--------|--------------| - * | Alarm out | | | | | Don't | | - * | output OD | 1 | 0 |Don't care | Don't care | care | 0 | - * |-----------------|----------|----------|-----------|--------------|--------|--------------| - * | Alarm out | | | | | Don't | | - * | output PP | 1 | 0 |Don't care | Don't care | care | 1 | - * |-----------------|----------|----------|-----------|--------------|--------|--------------| - * | Calibration out | | | | | Don't | | - * | output PP | 0 | 1 |Don't care | Don't care | care | Don't care | - * |-----------------|----------|----------|-----------|--------------|--------|--------------| - * | TAMPER input | | | | | Don't | | - * | floating | 0 | 0 | 1 | 0 | care | Don't care | - * |-----------------|----------|----------|-----------|--------------|--------|--------------| - * | TIMESTAMP and | | | | | Don't | | - * | TAMPER input | 0 | 0 | 1 | 1 | care | Don't care | - * | floating | | | | | | | - * |-----------------|----------|----------|-----------|--------------|--------|--------------| - * | TIMESTAMP input | | | | | Don't | | - * | floating | 0 | 0 | 0 | 1 | care | Don't care | - * |-----------------|----------|----------|-----------|--------------|--------|--------------| - * | Wakeup Pin 2 | 0 | 0 | 0 | 0 | 1 | Don't care | - * |-----------------|----------|----------|-----------|--------------|--------|--------------| - * | Standard GPIO | 0 | 0 | 0 | 0 | 0 | Don't care | - * +------------------------------------------------------------------------------------------+ - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_rtc.h" -#include "stm32l1xx_rcc.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RTC - * @brief RTC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ - RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ - RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ - RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F )) - -#define INITMODE_TIMEOUT ((uint32_t) 0x00002000) -#define SYNCHRO_TIMEOUT ((uint32_t) 0x00001000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static uint8_t RTC_ByteToBcd2(uint8_t Value); -static uint8_t RTC_Bcd2ToByte(uint8_t Value); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RTC_Private_Functions - * @{ - */ - -/** @defgroup RTC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This section provide functions allowing to initialize and configure the RTC - Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers - Write protection, enter and exit the RTC initialization mode, RTC registers - synchronization check and reference clock detection enable. - - 1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is - split into 2 programmable prescalers to minimize power consumption. - - A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. - - When both prescalers are used, it is recommended to configure the asynchronous - prescaler to a high value to minimize consumption. - - 2. All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - - 3. To Configure the RTC Calendar, user application should enter initialization - mode. In this mode, the calendar counter is stopped and its value can be - updated. When the initialization sequence is complete, the calendar restarts - counting after 4 RTCCLK cycles. - - 4. To read the calendar through the shadow registers after Calendar initialization, - calendar update or after wakeup from low power modes the software must first - clear the RSF flag. The software must then wait until it is set again before - reading the calendar, which means that the calendar registers have been - correctly copied into the RTC_TR and RTC_DR shadow registers. - The RTC_WaitForSynchro() function implements the above software sequence - (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the RTC registers to their default reset values. - * @note This function doesn't reset the RTC Clock source and RTC Backup Data - * registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are deinitialized - * - ERROR: RTC registers are not deinitialized - */ -ErrorStatus RTC_DeInit(void) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - RTC->TR = (uint32_t)0x00000000; - RTC->DR = (uint32_t)0x00002101; - /* Reset All CR bits except CR[2:0] */ - RTC->CR &= (uint32_t)0x00000007; - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - /* Reset all RTC CR register bits */ - RTC->CR &= (uint32_t)0x00000000; - RTC->WUTR = (uint32_t)0x0000FFFF; - RTC->PRER = (uint32_t)0x007F00FF; - RTC->CALIBR = (uint32_t)0x00000000; - RTC->ALRMAR = (uint32_t)0x00000000; - RTC->ALRMBR = (uint32_t)0x00000000; - - /* Reset ISR register and exit initialization mode */ - RTC->ISR = (uint32_t)0x00000000; - - /* Reset Tamper and alternate functions configuration register */ - RTC->TAFCR = 0x00000000; - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Initializes the RTC registers according to the specified parameters - * in RTC_InitStruct. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains - * the configuration information for the RTC peripheral. - * @note The RTC Prescaler register is write protected and can be written in - * initialization mode only. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are initialized - * - ERROR: RTC registers are not initialized - */ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Clear RTC CR FMT Bit */ - RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); - /* Set RTC_CR register */ - RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); - - /* Configure the RTC PRER */ - RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); - RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_InitStruct member with its default value. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) -{ - /* Initialize the RTC_HourFormat member */ - RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; - - /* Initialize the RTC_AsynchPrediv member */ - RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; - - /* Initialize the RTC_SynchPrediv member */ - RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; -} - -/** - * @brief Enables or disables the RTC registers write protection. - * @note All the RTC registers are write protected except for RTC_ISR[13:8], - * RTC_TAFCR and RTC_BKPxR. - * @note Writing a wrong key reactivates the write protection. - * @note The protection mechanism is not affected by system reset. - * @param NewState: new state of the write protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_WriteProtectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - } - else - { - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - } -} - -/** - * @brief Enters the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC is in Init mode - * - ERROR: RTC is not in Init mode - */ -ErrorStatus RTC_EnterInitMode(void) -{ - __IO uint32_t initcounter = 0x00; - ErrorStatus status = ERROR; - uint32_t initstatus = 0x00; - - /* Check if the Initialization mode is set */ - if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - /* Set the Initialization mode */ - RTC->ISR = (uint32_t)RTC_INIT_MASK; - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - do - { - initstatus = RTC->ISR & RTC_ISR_INITF; - initcounter++; - } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_INITF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - } - else - { - status = SUCCESS; - } - - return (status); -} - -/** - * @brief Exits the RTC Initialization mode. - * @note When the initialization sequence is complete, the calendar restarts - * counting after 4 RTCCLK cycles. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval None - */ -void RTC_ExitInitMode(void) -{ - /* Exit Initialization mode */ - RTC->ISR &= (uint32_t)~RTC_ISR_INIT; -} - -/** - * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are synchronised - * - ERROR: RTC registers are not synchronised - */ -ErrorStatus RTC_WaitForSynchro(void) -{ - __IO uint32_t synchrocounter = 0; - ErrorStatus status = ERROR; - uint32_t synchrostatus = 0x00; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear RSF flag */ - RTC->ISR &= (uint32_t)RTC_RSF_MASK; - - /* Wait the registers to be synchronised */ - do - { - synchrostatus = RTC->ISR & RTC_ISR_RSF; - synchrocounter++; - } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_RSF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (status); -} - -/** - * @brief Enables or disables the RTC reference clock detection. - * @param NewState: new state of the RTC reference clock. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC reference clock detection is enabled - * - ERROR: RTC reference clock detection is disabled - */ -ErrorStatus RTC_RefClockCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the RTC reference clock detection */ - RTC->CR |= RTC_CR_REFCKON; - } - else - { - /* Disable the RTC reference clock detection */ - RTC->CR &= ~RTC_CR_REFCKON; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @} - */ - -/** @defgroup RTC_Group2 Time and Date configuration functions - * @brief Time and Date configuration functions - * -@verbatim - =============================================================================== - Time and Date configuration functions - =============================================================================== - - This section provide functions allowing to program and read the RTC Calendar - (Time and Date). - -@endverbatim - * @{ - */ - -/** - * @brief Set the RTC current time. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains - * the time configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Time register is configured - * - ERROR: RTC Time register is not configured - */ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ - ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); - } - else - { - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ - (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_TR register */ - RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_TimeStruct member with its default value - * (Time = 00h:00min:00sec). - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) -{ - /* Time = 00h:00min:00sec */ - RTC_TimeStruct->RTC_H12 = RTC_H12_AM; - RTC_TimeStruct->RTC_Hours = 0; - RTC_TimeStruct->RTC_Minutes = 0; - RTC_TimeStruct->RTC_Seconds = 0; -} - -/** - * @brief Get the RTC current Time. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contain the returned current time configuration. - * @retval None - */ -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); - RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); - } -} - -/** - * @brief Set the RTC current date. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains - * the date configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Date register is configured - * - ERROR: RTC Date register is not configured - */ -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) - { - RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; - } - if (RTC_Format == RTC_Format_BIN) - { - assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); - assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); - assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - assert_param(IS_RTC_MONTH(tmpreg)); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - assert_param(IS_RTC_DATE(tmpreg)); - } - assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ - (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_DateStruct->RTC_Date) | \ - (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ - ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_DR register */ - RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_DateStruct member with its default value - * (Monday, January 01 xx00). - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) -{ - /* Monday, January 01 xx00 */ - RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; - RTC_DateStruct->RTC_Date = 1; - RTC_DateStruct->RTC_Month = RTC_Month_January; - RTC_DateStruct->RTC_Year = 0; -} - -/** - * @brief Get the RTC current date. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will - * contain the returned current date configuration. - * @retval None - */ -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); - RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); - RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay); - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group3 Alarms configuration functions - * @brief Alarms (Alarm A and Alarm B) configuration functions - * -@verbatim - =============================================================================== - Alarms (Alarm A and Alarm B) configuration functions - =============================================================================== - - This section provide functions allowing to program and read the RTC Alarms. - -@endverbatim - * @{ - */ - -/** - * @brief Set the specified RTC Alarm. - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the RTC_AlarmCmd(DISABLE)). - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that - * contains the alarm configuration parameters. - * @retval None - */ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm register */ - if (RTC_Alarm == RTC_Alarm_A) - { - RTC->ALRMAR = (uint32_t)tmpreg; - } - else - { - RTC->ALRMBR = (uint32_t)tmpreg; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Fills each RTC_AlarmStruct member with its default value - * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = - * all fields are masked). - * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which - * will be initialized. - * @retval None - */ -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - /* Alarm Time Settings : Time = 00h:00mn:00sec */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; - - /* Alarm Date Settings : Date = 1st day of the month */ - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; - RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; - - /* Alarm Masks Settings : Mask = all fields are not masked */ - RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; -} - -/** - * @brief Get the RTC Alarm value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will - * contains the output alarm configuration values. - * @retval None - */ -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - - /* Get the RTC_ALRMxR register */ - if (RTC_Alarm == RTC_Alarm_A) - { - tmpreg = (uint32_t)(RTC->ALRMAR); - } - else - { - tmpreg = (uint32_t)(RTC->ALRMBR); - } - - /* Fill the structure with the read parameters */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ - RTC_ALRMAR_HU)) >> 16); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ - RTC_ALRMAR_MNU)) >> 8); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ - RTC_ALRMAR_SU)); - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); - - if (RTC_Format == RTC_Format_BIN) - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Hours); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Minutes); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Seconds); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - } -} - -/** - * @brief Enables or disables the specified RTC Alarm. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be any combination of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param NewState: new state of the specified alarm. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Alarm is enabled/disabled - * - ERROR: RTC Alarm is not enabled/disabled - */ -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) -{ - __IO uint32_t alarmcounter = 0x00; - uint32_t alarmstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm state */ - if (NewState != DISABLE) - { - RTC->CR |= (uint32_t)RTC_Alarm; - - status = SUCCESS; - } - else - { - /* Disable the Alarm in RTC_CR register */ - RTC->CR &= (uint32_t)~RTC_Alarm; - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - do - { - alarmstatus = RTC->ISR & (RTC_Alarm >> 8); - alarmcounter++; - } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); - - if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @} - */ - -/** @defgroup RTC_Group4 WakeUp Timer configuration functions - * @brief WakeUp Timer configuration functions - * -@verbatim - =============================================================================== - WakeUp Timer configuration functions - =============================================================================== - - This section provide functions allowing to program and read the RTC WakeUp. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC Wakeup clock source. - * @note The WakeUp Clock source can only be changed when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpClock: Wakeup Clock source. - * This parameter can be one of the following values: - * @arg RTC_WakeUpClock_RTCCLK_Div16 - * @arg RTC_WakeUpClock_RTCCLK_Div8 - * @arg RTC_WakeUpClock_RTCCLK_Div4 - * @arg RTC_WakeUpClock_RTCCLK_Div2 - * @arg RTC_WakeUpClock_CK_SPRE_16bits - * @arg RTC_WakeUpClock_CK_SPRE_17bits - * @retval None - */ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the Wakeup Timer clock source bits in CR register */ - RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - RTC->CR |= (uint32_t)RTC_WakeUpClock; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the RTC Wakeup counter. - * @note The RTC WakeUp counter can only be written when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpCounter: specifies the WakeUp counter. - * This parameter can be a value from 0x0000 to 0xFFFF. - * @retval None - */ -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Wakeup Timer counter */ - RTC->WUTR = (uint32_t)RTC_WakeUpCounter; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC WakeUp timer counter value. - * @param None - * @retval The RTC WakeUp Counter value. - */ -uint32_t RTC_GetWakeUpCounter(void) -{ - /* Get the counter value */ - return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT)); -} - -/** - * @brief Enables or Disables the RTC WakeUp timer. - * @param NewState: new state of the WakeUp timer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the Wakeup Timer */ - RTC->CR |= (uint32_t)RTC_CR_WUTE; - status = SUCCESS; - } - else - { - /* Disable the Wakeup Timer */ - RTC->CR &= (uint32_t)~RTC_CR_WUTE; - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @} - */ - -/** @defgroup RTC_Group5 Daylight Saving configuration functions - * @brief Daylight Saving configuration functions - * -@verbatim - =============================================================================== - Daylight Saving configuration functions - =============================================================================== - - This section provide functions allowing to configure the RTC DayLight Saving. - -@endverbatim - * @{ - */ - -/** - * @brief Adds or substract one hour from the current time. - * @param RTC_DayLightSaveOperation: the value of hour adjustment. - * This parameter can be one of the following values: - * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) - * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) - * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit - * in CR register to store the operation. - * This parameter can be one of the following values: - * @arg RTC_StoreOperation_Reset - * @arg RTC_StoreOperation_Set - * @retval None - */ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) -{ - /* Check the parameters */ - assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_BCK); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC Day Light Saving stored operation. - * @param None - * @retval RTC Day Light Saving stored operation. - * - RTC_StoreOperation_Reset - * - RTC_StoreOperation_Set - */ -uint32_t RTC_GetStoreOperation(void) -{ - return (RTC->CR & RTC_CR_BCK); -} - -/** - * @} - */ - -/** @defgroup RTC_Group6 Output pin Configuration function - * @brief Output pin Configuration function - * -@verbatim - =============================================================================== - Output pin Configuration function - =============================================================================== - - This section provide functions allowing to configure the RTC Output source. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC output source (AFO_ALARM). - * @param RTC_Output: Specifies which signal will be routed to the RTC output. - * This parameter can be one of the following values: - * @arg RTC_Output_Disable: No output selected - * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output - * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output - * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output - * @param RTC_OutputPolarity: Specifies the polarity of the output signal. - * This parameter can be one of the following: - * @arg RTC_OutputPolarity_High: The output pin is high when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @arg RTC_OutputPolarity_Low: The output pin is low when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @retval None - */ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT(RTC_Output)); - assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); - - /* Configure the output selection and polarity */ - RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** @defgroup RTC_Group7 Digital Calibration configuration functions - * @brief Digital Calibration configuration functions - * -@verbatim - =============================================================================== - Digital Calibration configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the digital calibration parameters. - * @param RTC_CalibSign: specifies the sign of the calibration value. - * This parameter can be one of the following values: - * @arg RTC_CalibSign_Positive: The value sign is positive - * @arg RTC_CalibSign_Negative: The value sign is negative - * @param Value: value of calibration expressed in ppm (coded on 5 bits) - * - This value should be between 0 and 63 when using negative sign - * with a 2-ppm step. - * - This value should be between 0 and 126 when using positive sign - * with a 4-ppm step. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC digital calibration are initialized - * - ERROR: RTC digital calibration are not initialized - */ -ErrorStatus RTC_DigitalCalibConfig(uint32_t RTC_CalibSign, uint32_t Value) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign)); - assert_param(IS_RTC_CALIB_VALUE(Value)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the calibration value */ - RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value); - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or disables the digital calibration process. - * @param NewState: new state of the digital calibration. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC digital calibration are enabled/disabled - * - ERROR: RTC digital calibration are not enabled/disabled - */ -ErrorStatus RTC_DigitalCalibCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the Digital Calibration */ - RTC->CR |= (uint32_t)RTC_CR_DCE; - } - else - { - /* Disable the Digital Calibration */ - RTC->CR &= (uint32_t)~RTC_CR_DCE; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or disables the RTC clock to be output through the relative - * pin. - * @param NewState: new state of the digital calibration Output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_CalibOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the RTC clock output */ - RTC->CR |= (uint32_t)RTC_CR_COE; - } - else - { - /* Disable the RTC clock output */ - RTC->CR &= (uint32_t)~RTC_CR_COE; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - - -/** @defgroup RTC_Group8 TimeStamp configuration functions - * @brief TimeStamp configuration functions - * -@verbatim - =============================================================================== - TimeStamp configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or Disables the RTC TimeStamp functionality with the - * specified time stamp pin stimulating edge. - * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following: - * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising - * edge of the related pin. - * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the - * falling edge of the related pin. - * @param NewState: new state of the TimeStamp. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Get the new configuration */ - if (NewState != DISABLE) - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); - } - else - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Time Stamp TSEDGE and Enable bits */ - RTC->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Get the RTC TimeStamp value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contains the TimeStamp time values. - * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will - * contains the TimeStamp date values. - * @retval None - */ -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct) -{ - uint32_t tmptime = 0, tmpdate = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the TimeStamp time and date registers values */ - tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); - - /* Fill the Date structure fields with the read parameters */ - RTC_StampDateStruct->RTC_Year = 0; - RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the Time structure parameters to Binary format */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); - - /* Convert the Date structure parameters to Binary format */ - RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); - RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group9 Tampers configuration functions - * @brief Tampers configuration functions - * -@verbatim - =============================================================================== - Tampers configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the select Tamper pin edge. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1. - * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that - * stimulates tamper event. - * This parameter can be one of the following values: - * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. - * @retval None - */ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); - - if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); - } - else - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); - } -} - -/** - * @brief Enables or Disables the Tamper detection. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1. - * @param NewState: new state of the tamper pin. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_Tamper; - } - else - { - /* Disable the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_Tamper; - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group10 Backup Data Registers configuration functions - * @brief Backup Data Registers configuration functions - * -@verbatim - =============================================================================== - Backup Data Registers configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Writes a data in a specified RTC Backup data register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None - */ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval None - */ -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} - -/** - * @} - */ - -/** @defgroup RTC_Group11 Output Type Config configuration functions - * @brief Output Type Config configuration functions - * -@verbatim - =============================================================================== - Output Type Config configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC Output Pin mode. - * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. - * This parameter can be one of the following values: - * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in - * Open Drain mode. - * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in - * Push Pull mode. - * @retval None - */ -void RTC_OutputTypeConfig(uint32_t RTC_OutputType) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); - RTC->TAFCR |= (uint32_t)(RTC_OutputType); -} - -/** - * @} - */ - -/** @defgroup RTC_Group12 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - All RTC interrupts are connected to the EXTI controller. - - - To enable the RTC Alarm interrupt, the following sequence is required: - - Configure and enable the EXTI Line 17 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using - the RTC_SetAlarm() and RTC_AlarmCmd() functions. - - - To enable the RTC Wakeup interrupt, the following sequence is required: - - Configure and enable the EXTI Line 20 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to generate the RTC wakeup timer event using the - RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - - - To enable the RTC Tamper interrupt, the following sequence is required: - - Configure and enable the EXTI Line 19 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to detect the RTC tamper event using the - RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. - - - To enable the RTC TimeStamp interrupt, the following sequence is required: - - Configure and enable the EXTI Line 19 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to detect the RTC time-stamp event using the - RTC_TimeStampCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RTC interrupts. - * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt mask - * @arg RTC_IT_WUT: WakeUp Timer interrupt mask - * @arg RTC_IT_ALRB: Alarm B interrupt mask - * @arg RTC_IT_ALRA: Alarm A interrupt mask - * @arg RTC_IT_TAMP: Tamper event interrupt mask - * @param NewState: new state of the specified RTC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_CONFIG_IT(RTC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); - } - else - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Checks whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_INITF: Initialization mode flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_INITS: Registers Configured flag - * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag - * @arg RTC_FLAG_ALRBWF: Alarm B Write flag - * @arg RTC_FLAG_ALRAWF: Alarm A write flag - * @retval The new state of RTC_FLAG (SET or RESET). - */ -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); - - /* Get all the flags */ - tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); - - /* Return the status of the flag */ - if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's pending flags. - * @param RTC_FLAG: specifies the RTC flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @retval None - */ -void RTC_ClearFlag(uint32_t RTC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - - /* Clear the Flags in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Checks whether the specified RTC interrupt has occurred or not. - * @param RTC_IT: specifies the RTC interrupt source to check. - * This parameter can be one of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper 1 event interrupt - * @retval The new state of RTC_IT (SET or RESET). - */ -ITStatus RTC_GetITStatus(uint32_t RTC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_IT(RTC_IT)); - - /* Get the TAMPER Interrupt enable bit and pending bit */ - tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); - - /* Get the Interrupt enable Status */ - enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15))); - - /* Get the Interrupt pending bit */ - tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); - - /* Get the status of the Interrupt */ - if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's interrupt pending bits. - * @param RTC_IT: specifies the RTC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper 1 event interrupt - * @retval None - */ -void RTC_ClearITPendingBit(uint32_t RTC_IT) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_IT(RTC_IT)); - - /* Get the RTC_ISR Interrupt pending bits mask */ - tmpreg = (uint32_t)(RTC_IT >> 4); - - /* Clear the interrupt pending bits in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @} - */ - -/** - * @brief Converts a 2 digit decimal to BCD format. - * @param Value: Byte to be converted. - * @retval Converted byte - */ -static uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint8_t bcdhigh = 0; - - while (Value >= 10) - { - bcdhigh++; - Value -= 10; - } - - return ((uint8_t)(bcdhigh << 4) | Value); -} - -/** - * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted. - * @retval Converted word - */ -static uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint8_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_spi.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_spi.c deleted file mode 100644 index bf8ce5fba..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_spi.c +++ /dev/null @@ -1,884 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_spi.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the Serial peripheral interface (SPI): - * - Initialization and Configuration - * - Data transfers functions - * - Hardware CRC Calculation - * - DMA transfers management - * - Interrupts and flags management - * - * @verbatim - * - * The I2S feature is not implemented in STM32L1xx Ultra Low Power - * Medium-density devices and will be supported in future products. - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) - * function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) - * function for SPI2. - * - * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHBPeriphClockCmd() - * function. - * - * 3. Peripherals alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave - * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - * function. - * - * 5. Enable the NVIC and the corresponding interrupt using the function - * SPI_ITConfig() if you need to use interrupt mode. - * - * 6. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using SPI_I2S_DMACmd() function - * - * 7. Enable the SPI using the SPI_Cmd() function. - * - * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode. - * - * 9. Optionally you can enable/configure the following parameters without - * re-initialization (i.e there is no need to call again SPI_Init() function): - * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) - * is programmed as Data direction parameter using the SPI_Init() function - * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx - * using the SPI_BiDirectionalLineConfig() function. - * - When SPI_NSS_Soft is selected as Slave Select Management parameter - * using the SPI_Init() function it can be possible to manage the - * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. - * - Reconfigure the data size using the SPI_DataSizeConfig() function - * - Enable or disable the SS output using the SPI_SSOutputCmd() function - * - * 10. To use the CRC Hardware calculation feature refer to the Peripheral - * CRC hardware Calculation subsection. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_spi.h" -#include "stm32l1xx_rcc.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* SPI registers Masks */ -#define CR1_CLEAR_MASK ((uint16_t)0x3040) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** @defgroup SPI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This section provides a set of functions allowing to initialize the SPI Direction, - SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud - Rate Prescaler, SPI First Bit and SPI CRC Polynomial. - - The SPI_Init() function follows the SPI configuration procedures for Master mode - and Slave mode (details for these procedures are available in reference manual - (RM0038)). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SPIx peripheral registers to their default - * reset values. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else - { - if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - } -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - -/*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/salve mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - -/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct : pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= SPI_CR1_SPE; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); - } -} - -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param SPI_DataSize: specifies the SPI data size. - * This parameter can be one of the following values: - * @arg SPI_DataSize_16b: Set data frame format to 16bit - * @arg SPI_DataSize_8b: Set data frame format to 8bit - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATASIZE(SPI_DataSize)); - /* Clear DFF bit */ - SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; - /* Set new DFF bit value */ - SPIx->CR1 |= SPI_DataSize; -} - -/** - * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); - } -} - -/** - * @} - */ - -/** @defgroup SPI_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - Data transfers functions - =============================================================================== - - This section provides a set of functions allowing to manage the SPI data transfers - - In reception, data are received and then stored into an internal Rx buffer while - In transmission, data are first stored into an internal Tx buffer before being - transmitted. - - The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() - function and returns the Rx buffered value. Whereas a write access to the SPI_DR - can be done using SPI_I2S_SendData() function and stores the written data into - Tx buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the most recent received data by the SPIx peripheral. - * @param SPIx: where x can be 1 or 2 in SPI mode. - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the data in the DR register */ - return SPIx->DR; -} - -/** - * @brief Transmits a Data through the SPIx peripheral. - * @param SPIx: where x can be 1 or 2 in SPI mode. - * @param Data: Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Write in the DR register the data to be sent */ - SPIx->DR = Data; -} - -/** - * @} - */ - -/** @defgroup SPI_Group3 Hardware CRC Calculation functions - * @brief Hardware CRC Calculation functions - * -@verbatim - =============================================================================== - Hardware CRC Calculation functions - =============================================================================== - - This section provides a set of functions allowing to manage the SPI CRC hardware - calculation - - SPI communication using CRC is possible through the following procedure: - 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, - Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function. - 2. Enable the CRC calculation using the SPI_CalculateCRC() function. - 3. Enable the SPI using the SPI_Cmd() function - 4. Before writing the last data to the TX buffer, set the CRCNext bit using the - SPI_TransmitCRC() function to indicate that after transmission of the last - data, the CRC should be transmitted. - 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT - bit is reset. The CRC is also received and compared against the SPI_RXCRCR - value. - If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt - can be generated when the SPI_I2S_IT_ERR interrupt is enabled. - -Note: ------ - - It is advised to don't read the calculate CRC values during the communication. - - - When the SPI is in slave mode, be careful to enable CRC calculation only - when the clock is stable, that is, when the clock is in the steady state. - If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive - to the SCK slave input clock as soon as CRCEN is set, and this, whatever - the value of the SPE bit. - - - With high bitrate frequencies, be careful when transmitting the CRC. - As the number of used CPU cycles has to be as low as possible in the CRC - transfer phase, it is forbidden to call software functions in the CRC - transmission sequence to avoid errors in the last data and CRC reception. - In fact, CRCNEXT bit has to be written before the end of the transmission/reception - of the last data. - - - For high bit rate frequencies, it is advised to use the DMA mode to avoid the - degradation of the SPI speed performance due to CPU accesses impacting the - SPI bandwidth. - - - When the STM32L15xxx are configured as slaves and the NSS hardware mode is - used, the NSS pin needs to be kept low between the data phase and the CRC - phase. - - - When the SPI is configured in slave mode with the CRC feature enabled, CRC - calculation takes place even if a high level is applied on the NSS pin. - This may happen for example in case of a multislave environment where the - communication master addresses slaves alternately. - - - Between a slave deselection (high level on NSS) and a new slave selection - (low level on NSS), the CRC value should be cleared on both master and slave - sides in order to resynchronize the master and slave for their respective - CRC calculation. - - To clear the CRC, follow the procedure below: - 1. Disable SPI using the SPI_Cmd() function - 2. Disable the CRC calculation using the SPI_CalculateCRC() function. - 3. Enable the CRC calculation using the SPI_CalculateCRC() function. - 4. Enable SPI using the SPI_Cmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= SPI_CR1_CRCEN; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); - } -} - -/** - * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= SPI_CR1_CRCNEXT; -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1 or 2 to select the SPI peripheral. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @} - */ - -/** @defgroup SPI_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SPIx DMA interface. - * @param SPIx: where x can be 1 or 2 in SPI mode - * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @} - */ - -/** @defgroup SPI_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides a set of functions allowing to configure the SPI Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - Polling Mode - ============= - In Polling Mode, the SPI communication can be managed by 6 flags: - 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register - 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register - 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. - 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur - 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur - 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur - -Note: Do not use the BSY flag to handle each data transmission or reception. ------ It is better to use the TXE and RXNE flags instead. - - In this Mode it is advised to use the following functions: - - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - Interrupt Mode - =============== - In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources - and 5 pending bits: - Pending Bits: - ------------- - 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register - 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register - 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur - 4. SPI_IT_MODF : to indicate if a Mode Fault error occur - 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur - - Interrupt Source: - ----------------- - 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty - interrupt. - 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. - - In this Mode it is advised to use the following functions: - - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); - - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - DMA Mode - ======== - In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: - 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request - 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request - - In this Mode it is advised to use the following function: - - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified SPI interrupts. - * @param SPIx: where x can be 1 or 2 in SPI mode - * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Checks whether the specified SPI flag is set or not. - * @param SPIx: where x can be 1 or 2 in SPI mode - * @param SPI_I2S_FLAG: specifies the SPI flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_I2S_FLAG_MODF: Mode Fault flag. - * @arg SPI_I2S_FLAG_CRCERR: CRC Error flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - - /* Check the status of the specified SPI flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: where x can be 1 or 2 in SPI mode - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @note - * - OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * - MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPI interrupt has occurred or not. - * @param SPIx: where x can be - * - 1 or 2 in SPI mode - * @param SPI_I2S_IT: specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg SPI_I2S_IT_MODF: Mode Fault interrupt. - * @arg SPI_I2S_IT_CRCERR: CRC Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S_IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI_I2S_IT IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * @param SPIx: where x can be - * - 1 or 2 in SPI mode - * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. - * This function clears only CRCERR interrupt pending bit. - * @note - * - OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). - * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable - * the SPI). - * @retval None - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ - SPIx->SR = (uint16_t)~itpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_syscfg.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_syscfg.c deleted file mode 100644 index b59f8e86e..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_syscfg.c +++ /dev/null @@ -1,561 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_syscfg.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the SYSCFG and RI peripherals: - * - SYSCFG Initialization and Configuration - * - RI Initialization and Configuration - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * This driver provides functions for: - * - * 1. Remapping the memory accessible in the code area using - * SYSCFG_MemoryRemapConfig() - * 2. Manage the EXTI lines connection to the GPIOs using - * SYSCFG_EXTILineConfig(). - * 3. Routing of I/Os toward the input captures of timers (TIM2, TIM3 and TIM4). - * 4. Input routing of COMP1 and COMP2 - * 5. Routing of internal reference voltage VREFINT to PB0 and PB1. - * - * 6. The RI registers can be accessed only when the comparator - * APB interface clock is enabled. - * To enable comparator clock use: - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE); - * - * Following functions uses RI registers: - * - SYSCFG_RIDeInit() - * - SYSCFG_RITIMSelect() - * - SYSCFG_RITIMInputCaptureConfig() - * - SYSCFG_RIResistorConfig() - * - SYSCFG_RIIOSwitchConfig() - * - SYSCFG_RISwitchControlModeCmd() - * - SYSCFG_RIHysteresisConfig() - * - * 7- The SYSCFG registers can be accessed only when the SYSCFG - * interface APB clock is enabled. - * To enable SYSCFG APB clock use: - * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - * - * Following functions uses SYSCFG registers: - * - SYSCFG_MemoryRemapConfig() - * - SYSCFG_USBPuCmd() - * - SYSCFG_EXTILineConfig() - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_syscfg.h" -#include "stm32l1xx_rcc.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SYSCFG - * @brief SYSCFG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define TIM_SELECT_MASK ((uint32_t)0xFFFCFFFF) /*!< TIM select mask */ -#define IC_ROUTING_MASK ((uint32_t)0x0000000F) /*!< Input Capture routing mask */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SYSCFG_Private_Functions - * @{ - */ - -/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions - * @brief SYSCFG Initialization and Configuration functions - * -@verbatim - =============================================================================== - SYSCFG Initialization and Configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SYSCFG registers to their default reset values. - * @param None - * @retval None - * @ Note: MEMRMP bits are not reset by APB2 reset. - */ -void SYSCFG_DeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE); -} - -/** - * @brief Deinitializes the RI registers to their default reset values. - * @param None - * @retval None - */ -void SYSCFG_RIDeInit(void) -{ - RI->ICR = ((uint32_t)0x00000000); /*!< Set RI->ICR to reset value */ - RI->ASCR1 = ((uint32_t)0x00000000); /*!< Set RI->ASCR1 to reset value */ - RI->ASCR2 = ((uint32_t)0x00000000); /*!< Set RI->ASCR2 to reset value */ - RI->HYSCR1 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR1 to reset value */ - RI->HYSCR2 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR2 to reset value */ - RI->HYSCR3 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR3 to reset value */ -} - -/** - * @brief Changes the mapping of the specified memory. - * @param SYSCFG_Memory: selects the memory remapping. - * This parameter can be one of the following values: - * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000 - * @retval None - */ -void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap)); - SYSCFG->MEMRMP = SYSCFG_MemoryRemap; -} - -/** - * @brief Control the internal pull-up on USB DP line. - * @param NewState: New state of the internal pull-up on USB DP line. - * This parameter can be ENABLE: Connect internal pull-up on USB DP line. - * or DISABLE: Disconnect internal pull-up on USB DP line. - * @retval None - */ -void SYSCFG_USBPuCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Connect internal pull-up on USB DP line */ - SYSCFG->PMC |= (uint32_t) SYSCFG_PMC_USB_PU; - } - else - { - /* Disconnect internal pull-up on USB DP line */ - SYSCFG->PMC &= (uint32_t)(~SYSCFG_PMC_USB_PU); - } -} - -/** - * @brief Selects the GPIO pin used as EXTI Line. - * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source - * for EXTI lines where x can be (A, B, C, D, E or H). - * @param EXTI_PinSourcex: specifies the EXTI line to be configured. - * This parameter can be EXTI_PinSourcex where x can be (0..15) - * @retval None - */ -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) -{ - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); - assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); - - tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); -} - -/** - * @} - */ - -/** @defgroup SYSCFG_Group2 RI Initialization and Configuration functions - * @brief RI Initialization and Configuration functions - * -@verbatim - =============================================================================== - RI Initialization and Configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the routing interface to select which Timer to be routed. - * @note Routing capability can be applied only on one of the three timers - * (TIM2, TIM3 or TIM4) at a time. - * @param TIM_Select: Timer select. - * This parameter can be one of the following values: - * @arg TIM_Select_None: No timer selected and default Timer mapping is enabled. - * @arg TIM_Select_TIM2: Timer 2 Input Captures to be routed. - * @arg TIM_Select_TIM3: Timer 3 Input Captures to be routed. - * @arg TIM_Select_TIM4: Timer 4 Input Captures to be routed. - * @retval None. - */ -void SYSCFG_RITIMSelect(uint32_t TIM_Select) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RI_TIM(TIM_Select)); - - /* Get the old register value */ - tmpreg = RI->ICR; - - /* Clear the TIMx select bits */ - tmpreg &= TIM_SELECT_MASK; - - /* Select the Timer */ - tmpreg |= (TIM_Select); - - /* Write to RI->ICR register */ - RI->ICR = tmpreg; -} - -/** - * @brief Configures the routing interface to map Input Capture 1, 2, 3 or 4 - * to a selected I/O pin. - * @param RI_InputCapture selects which input capture to be routed. - * This parameter can be one (or combination) of the following parameters: - * @arg RI_InputCapture_IC1: Input capture 1 is selected. - * @arg RI_InputCapture_IC2: Input capture 2 is selected. - * @arg RI_InputCapture_IC3: Input capture 3 is selected. - * @arg RI_InputCapture_IC4: Input capture 4 is selected. - * @param RI_InputCaptureRouting: selects which pin to be routed to Input Capture. - * This parameter can be one of the following values: - * @arg RI_InputCaptureRouting_0 to RI_InputCaptureRouting_15 - * e.g. - * SYSCFG_RITIMSelect(TIM_Select_TIM2) - * SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_IC1, RI_InputCaptureRouting_1) - * allows routing of Input capture IC1 of TIM2 to PA4. - * For details about correspondence between RI_InputCaptureRouting_x - * and I/O pins refer to the parameters' description in the header file - * or refer to the product reference manual. - * @note Input capture selection bits are not reset by this function. - * To reset input capture selection bits, use SYSCFG_RIDeInit() function. - * @note The I/O should be configured in alternate function mode (AF14) using - * GPIO_PinAFConfig() function. - * @retval None. - */ -void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RI_INPUTCAPTURE(RI_InputCapture)); - assert_param(IS_RI_INPUTCAPTURE_ROUTING(RI_InputCaptureRouting)); - - /* Get the old register value */ - tmpreg = RI->ICR; - - /* Select input captures to be routed */ - tmpreg |= (RI_InputCapture); - - if((RI_InputCapture & RI_InputCapture_IC1) == RI_InputCapture_IC1) - { - /* Clear the input capture select bits */ - tmpreg &= (uint32_t)(~IC_ROUTING_MASK); - - /* Set RI_InputCaptureRouting bits */ - tmpreg |= (uint32_t)( RI_InputCaptureRouting); - } - - if((RI_InputCapture & RI_InputCapture_IC2) == RI_InputCapture_IC2) - { - /* Clear the input capture select bits */ - tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 4)); - - /* Set RI_InputCaptureRouting bits */ - tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 4)); - } - - if((RI_InputCapture & RI_InputCapture_IC3) == RI_InputCapture_IC3) - { - /* Clear the input capture select bits */ - tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 8)); - - /* Set RI_InputCaptureRouting bits */ - tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 8)); - } - - if((RI_InputCapture & RI_InputCapture_IC4) == RI_InputCapture_IC4) - { - /* Clear the input capture select bits */ - tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 12)); - - /* Set RI_InputCaptureRouting bits */ - tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 12)); - } - - /* Write to RI->ICR register */ - RI->ICR = tmpreg; -} -/** - * @brief Configures the Pull-up and Pull-down Resistors - * @param RI_Resistor selects the resistor to connect. - * This parameter can be one of the following values: - * @arg RI_Resistor_10KPU: 10K pull-up resistor - * @arg RI_Resistor_400KPU: 400K pull-up resistor - * @arg RI_Resistor_10KPD: 10K pull-down resistor - * @arg RI_Resistor_400KPD: 400K pull-down resistor - * @param NewState: New state of the analog switch associated to the selected - * resistor. - * This parameter can be: - * ENABLE so the selected resistor is connected - * or DISABLE so the selected resistor is disconnected - * @note To avoid extra power consumption, only one resistor should be enabled - * at a time. - * @retval None - */ -void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RI_RESISTOR(RI_Resistor)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the resistor */ - COMP->CSR |= (uint32_t) RI_Resistor; - } - else - { - /* Disable the Resistor */ - COMP->CSR &= (uint32_t) (~RI_Resistor); - } -} - -/** - * @brief Close or Open the routing interface Input Output switches. - * @param RI_IOSwitch: selects the I/O analog switch number. - * This parameter can be one of the following values: - * @arg RI_IOSwitch_CH0 --> RI_IOSwitch_CH15 - * @arg RI_IOSwitch_CH18 --> RI_IOSwitch_CH25 - * @arg RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4 - * @arg RI_IOSwitch_GR6_1 --> RI_IOSwitch_GR6_2 - * @arg RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3 - * @arg RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_3 - * @arg RI_IOSwitch_VCOMP - * @param NewState: New state of the analog switch. - * This parameter can be - * ENABLE so the Input Output switch is closed - * or DISABLE so the Input Output switch is open - * @retval None - */ -void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState) -{ - uint32_t ioswitchmask = 0; - - /* Check the parameters */ - assert_param(IS_RI_IOSWITCH(RI_IOSwitch)); - - /* Read Analog switch register index */ - ioswitchmask = RI_IOSwitch >> 31; - - /* Get Bits[30:0] of the IO switch */ - RI_IOSwitch &= 0x7FFFFFFF; - - - if (NewState != DISABLE) - { - if (ioswitchmask != 0) - { - /* Close the analog switches */ - RI->ASCR1 |= RI_IOSwitch; - } - else - { - /* Open the analog switches */ - RI->ASCR2 |= RI_IOSwitch; - } - } - else - { - if (ioswitchmask != 0) - { - /* Close the analog switches */ - RI->ASCR1 &= (~ (uint32_t)RI_IOSwitch); - } - else - { - /* Open the analog switches */ - RI->ASCR2 &= (~ (uint32_t)RI_IOSwitch); - } - } -} - -/** - * @brief Enable or disable the switch control mode. - * @param NewState: New state of the switch control mode. This parameter can - * be ENABLE: ADC analog switches closed if the corresponding - * I/O switch is also closed. - * When using COMP1 switch control mode must be enabled. - * or DISABLE: ADC analog switches open or controlled by the ADC interface. - * When using the ADC for acquisition switch control mode - * must be disabled. - * @note COMP1 comparator and ADC cannot be used at the same time since - * they share the ADC switch matrix. - * @retval None - */ -void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Switch control mode */ - RI->ASCR1 |= (uint32_t) RI_ASCR1_SCM; - } - else - { - /* Disable the Switch control mode */ - RI->ASCR1 &= (uint32_t)(~RI_ASCR1_SCM); - } -} - -/** - * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A..E - * When the I/Os are programmed in input mode by standard I/O port - * registers, the Schmitt trigger and the hysteresis are enabled by default. - * When hysteresis is disabled, it is possible to read the - * corresponding port with a trigger level of VDDIO/2. - * @param RI_Port: selects the GPIO Port. - * This parameter can be one of the following values: - * @arg RI_PortA : Port A is selected - * @arg RI_PortB : Port B is selected - * @arg RI_PortC : Port C is selected - * @arg RI_PortD : Port D is selected - * @arg RI_PortE : Port E is selected - * @param RI_Pin : Selects the pin(s) on which to enable or disable hysteresis. - * This parameter can any value from RI_Pin_x where x can be (0..15) or RI_Pin_All. - * @param NewState new state of the Hysteresis. - * This parameter can be: - * ENABLE so the Hysteresis is on - * or DISABLE so the Hysteresis is off - * @retval None - */ -void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin, - FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RI_PORT(RI_Port)); - assert_param(IS_RI_PIN(RI_Pin)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(RI_Port == RI_PortA) - { - if (NewState != DISABLE) - { - /* Hysteresis on */ - RI->HYSCR1 &= (uint32_t)~((uint32_t)RI_Pin); - } - else - { - /* Hysteresis off */ - RI->HYSCR1 |= (uint32_t) RI_Pin; - } - } - - else if(RI_Port == RI_PortB) - { - - if (NewState != DISABLE) - { - /* Hysteresis on */ - RI->HYSCR1 &= (uint32_t) (~((uint32_t)RI_Pin) << 16); - } - else - { - /* Hysteresis off */ - RI->HYSCR1 |= (uint32_t) ((uint32_t)(RI_Pin) << 16); - } - } - - else if(RI_Port == RI_PortC) - { - - if (NewState != DISABLE) - { - /* Hysteresis on */ - RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin)); - } - else - { - /* Hysteresis off */ - RI->HYSCR2 |= (uint32_t) (RI_Pin ); - } - } - else if(RI_Port == RI_PortD) - { - if (NewState != DISABLE) - { - /* Hysteresis on */ - RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin) << 16); - } - else - { - /* Hysteresis off */ - RI->HYSCR2 |= (uint32_t) ((uint32_t)(RI_Pin) << 16); - - } - } - else /* RI_Port == RI_PortE */ - { - if (NewState != DISABLE) - { - /* Hysteresis on */ - RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin)); - } - else - { - /* Hysteresis off */ - RI->HYSCR3 |= (uint32_t) (RI_Pin ); - } - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_tim.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_tim.c deleted file mode 100644 index d7ed2308b..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_tim.c +++ /dev/null @@ -1,2832 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_tim.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the TIM peripheral: - * - TimeBase management - * - Output Compare management - * - Input Capture management - * - Interrupts, DMA and flags management - * - Clocks management - * - Synchronization management - * - Specific interface management - * - Specific remapping management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * This driver provides functions to configure and program the TIM - * of all STM32L1xx devices - * These functions are split in 8 groups: - * - * 1. TIM TimeBase management: this group includes all needed functions - * to configure the TM Timebase unit: - * - Set/Get Prescaler - * - Set/Get Autoreload - * - Counter modes configuration - * - Set Clock division - * - Select the One Pulse mode - * - Update Request Configuration - * - Update Disable Configuration - * - Auto-Preload Configuration - * - Enable/Disable the counter - * - * 2. TIM Output Compare management: this group includes all needed - * functions to configure the Capture/Compare unit used in Output - * compare mode: - * - Configure each channel, independently, in Output Compare mode - * - Select the output compare modes - * - Select the Polarities of each channel - * - Set/Get the Capture/Compare register values - * - Select the Output Compare Fast mode - * - Select the Output Compare Forced mode - * - Output Compare-Preload Configuration - * - Clear Output Compare Reference - * - Select the OCREF Clear signal - * - Enable/Disable the Capture/Compare Channels - * - * 3. TIM Input Capture management: this group includes all needed - * functions to configure the Capture/Compare unit used in - * Input Capture mode: - * - Configure each channel in input capture mode - * - Configure Channel1/2 in PWM Input mode - * - Set the Input Capture Prescaler - * - Get the Capture/Compare values - * - * 4. TIM interrupts, DMA and flags management - * - Enable/Disable interrupt sources - * - Get flags status - * - Clear flags/ Pending bits - * - Enable/Disable DMA requests - * - Configure DMA burst mode - * - Select CaptureCompare DMA request - * - * 5. TIM clocks management: this group includes all needed functions - * to configure the clock controller unit: - * - Select internal/External clock - * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx - * - * 6. TIM synchronization management: this group includes all needed - * functions to configure the Synchronization unit: - * - Select Input Trigger - * - Select Output Trigger - * - Select Master Slave Mode - * - ETR Configuration when used as external trigger - * - * 7. TIM specific interface management, this group includes all - * needed functions to use the specific TIM interface: - * - Encoder Interface Configuration - * - Select Hall Sensor - * - * 8. TIM specific remapping management includes the Remapping - * configuration of specific timers - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_tim.h" -#include "stm32l1xx_rcc.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup TIM - * @brief TIM driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define SMCR_ETR_MASK ((uint16_t)0x00FF) -#define CCMR_OFFSET ((uint16_t)0x0018) -#define CCER_CCE_SET ((uint16_t)0x0001) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup TIM_Private_Functions - * @{ - */ - -/** @defgroup TIM_Group1 TimeBase management functions - * @brief TimeBase management functions - * -@verbatim - =============================================================================== - TimeBase management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in Timing(Time base) Mode - =================================================================== - To use the Timer in Timing(Time base) mode, the following steps are mandatory: - - 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - 2. Fill the TIM_TimeBaseInitStruct with the desired parameters. - - 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit - with the corresponding configuration - - 4. Enable the NVIC if you need to generate the update interrupt. - - 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) - - 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - Note1: All other functions can be used seperatly to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @retval None - * - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - if (TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if (TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if (TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } - - else if (TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } - else if (TIMx == TIM7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); - } - - else if (TIMx == TIM9) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); - } - else if (TIMx == TIM10) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); - } - else - { - if (TIMx == TIM11) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); - } - } - -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef - * structure that contains the configuration information for - * the specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); - - tmpcr1 = TIMx->CR1; - - if(((TIMx) == TIM2) || ((TIMx) == TIM3) || ((TIMx) == TIM4)) - { - /* Select the Counter Mode */ - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - if(((TIMx) != TIM6) && ((TIMx) != TIM7)) - { - /* Set the clock division */ - tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - /* Generate an update event to reload the Prescaler value immediatly */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef - * structure which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - - tmpcr1 = TIMx->CR1; - /* Reset the CMS and DIR Bits */ - tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @retval Counter Register value. - */ -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @retval Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= TIM_CR1_UDIS; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. - * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= TIM_CR1_URS; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); - } -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= TIM_CR1_ARPE; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); - } -} - -/** - * @brief Selects the TIMxs One Pulse Mode. - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - - /* Reset the OPM Bit */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - -/** - * @brief Sets the TIMx Clock Division value. - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @param TIM_CKD: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CKD_DIV1: TDTS = Tck_tim - * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim - * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CKD_DIV(TIM_CKD)); - - /* Reset the CKD Bits */ - TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); - /* Set the CKD value */ - TIMx->CR1 |= TIM_CKD; -} - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_CEN; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); - } -} - -/** - * @} - */ - -/** @defgroup TIM_Group2 Output Compare management functions - * @brief Output Compare management functions - * -@verbatim - =============================================================================== - Output Compare management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in Output Compare Mode - =================================================================== - To use the Timer in Output Compare mode, the following steps are mandatory: - - 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - 2. Configure the TIM pins by configuring the corresponding GPIO pins - - 2. Configure the Time base unit as described in the first part of this driver, if needed, - else the Timer will run with the default configuration: - - Autoreload value = 0xFFFF - - Prescaler value = 0x0000 - - Counter mode = Up counting - - Clock Division = TIM_CKD_DIV1 - - 3. Fill the TIM_OCInitStruct with the desired parameters including: - - The TIM Output Compare mode: TIM_OCMode - - TIM Output State: TIM_OutputState - - TIM Pulse value: TIM_Pulse - - TIM Output Compare Polarity : TIM_OCPolarity - - 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the - corresponding configuration - - 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - Note1: All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - - Note2: In case of PWM mode, this function is mandatory: - TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); - - Note3: If the corresponding interrupt or DMA request are needed, the user should: - 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). - 2. Enable the corresponding interrupt (or DMA request) using the function - TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIMx Channel1 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); - - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); - - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified - * parameters in the TIM_OCInitStruct. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 2: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x0000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; -} - -/** - * @brief Selects the TIM Output Compare Mode. - * @note This function disables the selected channel before changing the Output - * Compare Mode. - * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This parameter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_OFFSET; - - tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1M Bits */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM - * peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2M Bits */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); - /* Configure The Forced output Mode */ - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC1M Bits */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC2M Bits */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); - /* Configure The Forced output Mode */ - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1PE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2PE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3PE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4PE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1FE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2FE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3FE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4FE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF1 signal on an external event - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC1CE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= TIM_OCClear; - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF2 signal on an external event - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - /* Reset the OC2CE Bit */ - tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF3 signal on an external event - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC3CE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= TIM_OCClear; - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF4 signal on an external event - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - /* Reset the OC4CE Bit */ - tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC1P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); - tmpccer |= TIM_OCPolarity; - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC2P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC3P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parmeter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - /* Set or Reset the CC4P Bit */ - tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Selects the OCReference Clear source. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_OCReferenceClear: specifies the OCReference Clear source. - * This parameter can be one of the following values: - * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF. - * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. - * @retval None - */ -void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear)); - - /* Set the TIM_OCReferenceClear source */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS); - TIMx->SMCR |= TIM_OCReferenceClear; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = CCER_CCE_SET << TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t)~ tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/** - * @} - */ - -/** @defgroup TIM_Group3 Input Capture management functions - * @brief Input Capture management functions - * -@verbatim - =============================================================================== - Input Capture management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in Input Capture Mode - =================================================================== - To use the Timer in Input Capture mode, the following steps are mandatory: - - 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - 2. Configure the TIM pins by configuring the corresponding GPIO pins - - 2. Configure the Time base unit as described in the first part of this driver, if needed, - else the Timer will run with the default configuration: - - Autoreload value = 0xFFFF - - Prescaler value = 0x0000 - - Counter mode = Up counting - - Clock Division = TIM_CKD_DIV1 - - 3. Fill the TIM_ICInitStruct with the desired parameters including: - - TIM Channel: TIM_Channel - - TIM Input Capture polarity: TIM_ICPolarity - - TIM Input Capture selection: TIM_ICSelection - - TIM Input Capture Prescaler: TIM_ICPrescaler - - TIM Input CApture filter value: TIM_ICFilter - - 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the - corresponding configuration and to measure only frequency or duty cycle of the input signal, - or, - Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the - corresponding configuration and to measure the frequency and the duty cycle of the input signal - - 5. Enable the NVIC or the DMA to read the measured frequency. - - 6. Enable the corresponding interrupt (or DMA request) to read the Captured value, - using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - - 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - 8. Use TIM_GetCapturex(TIMx); to read the captured value. - - Note1: All other functions can be used seperatly to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct. - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - /* TI3 Configuration */ - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI4 Configuration */ - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct : pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Configures the TIM peripheral according to the specified - * parameters in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure - * that contains the configuration information for the specified TIM - * peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @retval Capture Compare 1 Register value. - - */ -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @retval Capture Compare 2 Register value. - - */ -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @retval Capture Compare 3 Register value. - */ -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @retval Capture Compare 4 Register value. - */ -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @} - */ - -/** @defgroup TIM_Group4 Interrupts DMA and flags management functions - * @brief Interrupts, DMA and flags management functions - * -@verbatim - =============================================================================== - Interrupts, DMA and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx: where x can be 2 to 11 to select the TIMx peripheral. - * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @note - * - TIM6 and TIM7 can only generate an update interrupt. - * - TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger can not be used with TIM10 and TIM11 - * - TIM_IT_CC3, TIM_IT_CC4 can not be used with TIM9. - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx->DIER |= TIM_IT; - } - else - { - /* Disable the Interrupt sources */ - TIMx->DIER &= (uint16_t)~TIM_IT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @note - * - TIM6 and TIM7 can only generate an update event. - * - TIM9 can only generate an update event, Capture Compare 1 event, - * Capture Compare 2 event and TIM_EventSource_Trigger. - * - TIM10 and TIM11 can only generate an update event and Capture Compare 1 event. - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Checks whether the specified TIM flag is set or not. - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * @note - * - TIM6 and TIM7 can have only one update flag. - * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger, - * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags - * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 or TIM_FLAG_CC1OF flags - * @retval The new state of TIM_FLAG (SET or RESET). - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); - - if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's pending flags. - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag - * @note - * - TIM6 and TIM7 can have only one update flag. - * - TIM9 can have only update flag, TIM_FLAG_CC1, TIM_FLAG_CC2 and TIM_FLAG_Trigger flags - * TIM_FLAG_CC1OF or TIM_FLAG_CC2OF flags - * - TIM10 and TIM11 can have only update flag, TIM_FLAG_CC1 - * or TIM_FLAG_CC1OF flags - * @retval None - */ -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); - - /* Clear the flags */ - TIMx->SR = (uint16_t)~TIM_FLAG; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @param TIM_IT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @note - * - TIM6 and TIM7 can generate only an update interrupt. - * - TIM9 can have only update interrupt, TIM_FLAG_CC1 or TIM_FLAG_CC2, - * interrupt and TIM_IT_Trigger interrupt. - * - TIM10 and TIM11 can have only update interrupt or TIM_FLAG_CC1 - * interrupt - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_IT(TIM_IT)); - - itstatus = TIMx->SR & TIM_IT; - - itenable = TIMx->DIER & TIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx: where x can be 2 to 11 to select the TIM peripheral. - * @param TIM_IT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @note - * - TIM6 and TIM7 can generate only an update interrupt. - * - TIM9 can have only update interrupt, TIM_IT_CC1 or TIM_IT_CC2, - * and TIM_IT_Trigger interrupt. - * - TIM10 and TIM11 can have only update interrupt or TIM_IT_CC1 - * interrupt - * @retval None - */ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - - /* Clear the IT pending Bit */ - TIMx->SR = (uint16_t)~TIM_IT; -} - -/** - * @brief Configures the TIMxs DMA interface. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_DMABase: DMA Base address. - * This parameter can be one of the following values: - * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, - * TIM_DMABase_DIER, TIM_DMABase_SR, TIM_DMABase_EGR, - * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, - * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, - * TIM_DMABase_CCR1, TIM_DMABase_CCR2, TIM_DMABase_CCR3, - * TIM_DMABase_CCR4, TIM_DMABase_DCR. - * @param TIM_DMABurstLength: DMA Burst length. - * This parameter can be one value between: - * TIM_DMABurstLength_1Byte and TIM_DMABurstLength_18Bytes. - * @retval None - */ -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); - assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); - /* Set the DMA Base and the DMA Burst Length */ - TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; -} - -/** - * @brief Enables or disables the TIMxs DMA Requests. - * @param TIMx: where x can be 2, 3, 4, 6 or 7 to select the TIM peripheral. - * @param TIM_DMASource: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg TIM_DMA_Update: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_Trigger: TIM Trigger DMA source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA sources */ - TIMx->DIER |= TIM_DMASource; - } - else - { - /* Disable the DMA sources */ - TIMx->DIER &= (uint16_t)~TIM_DMASource; - } -} - -/** - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param NewState: new state of the Capture Compare DMA source - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the CCDS Bit */ - TIMx->CR2 |= TIM_CR2_CCDS; - } - else - { - /* Reset the CCDS Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); - } -} - -/** - * @} - */ - -/** @defgroup TIM_Group5 Clocks management functions - * @brief Clocks management functions - * -@verbatim - =============================================================================== - Clocks management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx internal Clock - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @param TIM_ITRSource: Trigger source. - * This parameter can be one of the following values: - * @param TIM_TS_ITR0: Internal Trigger 0 - * @param TIM_TS_ITR1: Internal Trigger 1 - * @param TIM_TS_ITR2: Internal Trigger 2 - * @param TIM_TS_ITR3: Internal Trigger 3 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter : specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the SMS Bits */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - /* Select the Trigger selection : ETRF */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); - tmpsmcr |= TIM_TS_ETRF; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - /* Enable the External clock mode2 */ - TIMx->SMCR |= TIM_SMCR_ECE; -} - -/** - * @} - */ - -/** @defgroup TIM_Group6 Synchronization management functions - * @brief Synchronization management functions - * -@verbatim - =============================================================================== - Synchronization management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in synchronization Mode - =================================================================== - Case of two/several Timers - ************************** - 1. Configure the Master Timers using the following functions: - - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); - - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); - 2. Configure the Slave Timers using the following functions: - - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - - Case of Timers and external trigger(ETR pin) - ******************************************** - 1. Configure the Etrenal trigger using this function: - - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - 2. Configure the Slave Timers using the following functions: - - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - -@endverbatim - * @{ - */ - -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 2, 3, 4, 6, 7 or 9 to select the TIM peripheral. - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This paramter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). - * - * - For all TIMx except TIM6 and TIM7 - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs (TRGO). - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). - - * - For all TIMx except TIM6, TIM7, TIM10 and TIM11 - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). - - * - For TIM2, TIM3 and TIM4 - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This paramter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes - * the counter and triggers an update of the registers. - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - - /* Reset the SMS Bits */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); - /* Select the Slave Mode */ - TIMx->SMCR |= TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This paramter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO). - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - - /* Reset the MSM Bit */ - TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - tmpsmcr = TIMx->SMCR; - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_MASK; - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @} - */ - -/** @defgroup TIM_Group7 Specific interface management functions - * @brief Specific interface management functions - * -@verbatim - =============================================================================== - Specific interface management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parmeter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parmeter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Set the encoder Mode */ - tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); - tmpsmcr |= TIM_EncoderMode; - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); - tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P))); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIMxs Hall sensor interface. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= TIM_CR2_TI1S; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); - } -} - -/** - * @} - */ - -/** @defgroup TIM_Group8 Specific remapping management function - * @brief Specific remapping management function - * -@verbatim - =============================================================================== - Specific remapping management function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIM9, TIM10 and TIM11 Remapping input Capabilities. - * @param TIMx: where x can be 9, 10 or 11 to select the TIM peripheral. - * @param TIM_Remap: specifies the TIM input remapping source. - * This parameter can be one of the following values: - * @arg TIM9_GPIO: TIM9 Channel 1 is connected to dedicated Timer pin(default) - * @arg TIM9_LSE: TIM9 Channel 1 is connected to LSE clock. - * @arg TIM10_GPIO: TIM10 Channel 1 is connected to dedicated Timer pin(default) - * @arg TIM10_LSI: TIM10 Channel 1 is connected to LSI clock. - * @arg TIM10_LSE: TIM10 Channel 1 is connected to LSE clock. - * @arg TIM10_RTC: TIM10 Channel 1 is connected to RTC Output event. - * @arg TIM11_GPIO: TIM11 Channel 1 is connected to dedicated Timer pin(default) - * @arg TIM11_MSI: TIM11 Channel 1 is connected to MSI clock. - * @arg TIM11_HSE_RTC: TIM11 Channel 1 is connected to HSE_RTC clock. - * @retval None - */ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_REMAP(TIM_Remap)); - - /* Set the Timer remapping configuration */ - TIMx->OR = TIM_Remap; -} - -/** - * @} - */ - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 2, 3, 4, 9, 10 or 11 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - /* Select the Input and set the filter */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 2, 3, 4 or 9 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - /* Select the Input and set the filter */ - tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx: where x can be 2, 3 or 4 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - /* Select the Input and set the filter */ - tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP)); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_usart.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_usart.c deleted file mode 100644 index 3da7fe801..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_usart.c +++ /dev/null @@ -1,1432 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_usart.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the Universal synchronous asynchronous receiver - * transmitter (USART): - * - Initialization and Configuration - * - Data transfers - * - Multi-Processor Communication - * - LIN mode - * - Half-duplex mode - * - Smartcard mode - * - IrDA mode - * - DMA transfers management - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) - * function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) - * function for USART2 and USART3. - * - * 2. According to the USART mode, enable the GPIO clocks using - * RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS, - * or and SCLK). - * - * 3. Peripherals alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware - * flow control and Mode(Receiver/Transmitter) using the SPI_Init() - * function. - * - * 5. For synchronous mode, enable the clock and program the polarity, - * phase and last bit using the USART_ClockInit() function. - * - * 5. Enable the NVIC and the corresponding interrupt using the function - * USART_ITConfig() if you need to use interrupt mode. - * - * 6. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using USART_DMACmd() function - * - * 7. Enable the USART using the USART_Cmd() function. - * - * 8. Enable the DMA using the DMA_Cmd() function, when using DMA mode. - * - * Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections - * for more details - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_usart.h" -#include "stm32l1xx_rcc.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup USART - * @brief USART driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */ -#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \ - USART_CR1_PS | USART_CR1_TE | \ - USART_CR1_RE)) - -/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */ -#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ - USART_CR2_CPHA | USART_CR2_LBCL)) - -/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */ -#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE)) - -/*!< USART Interrupts mask */ -#define IT_MASK ((uint16_t)0x001F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup USART_Private_Functions - * @{ - */ - -/** @defgroup USART_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - - For the asynchronous mode only these parameters can be configured: - - Baud Rate - - Word Length - - Stop Bit - - Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - - Hardware flow control - - Receiver/transmitter modes - - The USART_Init() function follows the USART asynchronous configuration procedure - (details for the procedure are available in reference manual (RM0038)). - - - For the synchronous mode in addition to the asynchronous mode parameters these - parameters should be also configured: - - USART Clock Enabled - - USART polarity - - USART phase - - USART LastBit - - These parameters can be configured using the USART_ClockInit() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: USART1, USART2 or USART3. - * @retval None - */ -void USART_DeInit(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - if (USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if (USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else - { - if (USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - } -} - -/** - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * that contains the configuration information for the specified USART peripheral. - * @retval None - */ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - RCC_ClocksTypeDef RCC_ClocksStatus; - - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear STOP[13:12] bits */ - tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); - - /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/ - /* Set STOP[13:12] bits according to USART_StopBits value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; - -/*---------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = USARTx->CR1; - /* Clear M, PCE, PS, TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); - - /* Configure the USART Word Length, Parity and mode ----------------------- */ - /* Set the M bits according to USART_WordLength value */ - /* Set PCE and PS bits according to USART_Parity value */ - /* Set TE and RE bits according to USART_Mode value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - - /* Write to USART CR1 */ - USARTx->CR1 = (uint16_t)tmpreg; - -/*---------------------------- USART CR3 Configuration -----------------------*/ - tmpreg = USARTx->CR3; - /* Clear CTSE and RTSE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); - - /* Configure the USART HFC -------------------------------------------------*/ - /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - - /* Write to USART CR3 */ - USARTx->CR3 = (uint16_t)tmpreg; - -/*---------------------------- USART BRR Configuration -----------------------*/ - /* Configure the USART Baud Rate -------------------------------------------*/ - RCC_GetClocksFreq(&RCC_ClocksStatus); - if (USARTx == USART1) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - /* Determine the integer part */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ - { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - /* Determine the fractional part */ - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - /* Implement the fractional part in the register */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */ - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - /* Write to USART BRR */ - USARTx->BRR = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_InitStruct member with its default value. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure - * which will be initialized. - * @retval None - */ -void USART_StructInit(USART_InitTypeDef* USART_InitStruct) -{ - /* USART_InitStruct members default value */ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No ; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/** - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * @param USARTx: where x can be 1, 2, 3 to select the USART peripheral. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure that contains the configuration information for the specified - * USART peripheral. - * @retval None - */ -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear CLKEN, CPOL, CPHA and LBCL bits */ - tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); - /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ - /* Set CLKEN bit according to USART_Clock value */ - /* Set CPOL bit according to USART_CPOL value */ - /* Set CPHA bit according to USART_CPHA value */ - /* Set LBCL bit according to USART_LastBit value */ - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_ClockInitStruct member with its default value. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef - * structure which will be initialized. - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - /* USART_ClockInitStruct members default value */ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/** - * @brief Enables or disables the specified USART peripheral. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART by setting the UE bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_UE; - } - else - { - /* Disable the selected USART by clearing the UE bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE); - } -} - -/** - * @brief Sets the system clock prescaler. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param USART_Prescaler: specifies the prescaler clock. - * @retval None - */ -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART prescaler */ - USARTx->GTPR &= USART_GTPR_GT; - /* Set the USART prescaler */ - USARTx->GTPR |= USART_Prescaler; -} - -/** - * @brief Enables or disables the USART's 8x oversampling mode. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3. - * @param NewState: new state of the USART 8x oversampling mode. - * This parameter can be: ENABLE or DISABLE. - * - * @note - * This function has to be called before calling USART_Init() - * function in order to have correct baudrate Divider value. - * @retval : None - */ -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_OVER8; - } - else - { - /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8); - } -} - -/** - * @brief Enables or disables the USART's one bit sampling method. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2, USART3. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @retval : None - */ -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_ONEBIT; - } - else - { - /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - Data transfers functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART data - transfers. - - During an USART reception, data shifts in least significant bit first through - the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) - between the internal bus and the received shift register. - - When a transmission is taking place, a write instruction to the USART_DR register - stores the data in the TDR register and which is copied in the shift register - at the end of the current transmission. - - The read access of the USART_DR register can be done using the USART_ReceiveData() - function and returns the RDR buffered value. Whereas a write access to the USART_DR - can be done using USART_SendData() function and stores the written data into - TDR buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param Data: the data to transmit. - * @retval None - */ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DATA(Data)); - - /* Transmit Data */ - USARTx->DR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @retval The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Receive Data */ - return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); -} - -/** - * @} - */ - -/** @defgroup USART_Group3 MultiProcessor Communication functions - * @brief Multi-Processor Communication functions - * -@verbatim - =============================================================================== - Multi-Processor Communication functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - multiprocessor communication. - - For instance one of the USARTs can be the master, its TX output is connected to - the RX input of the other USART. The others are slaves, their respective TX outputs - are logically ANDed together and connected to the RX input of the master. - - USART multiprocessor communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter - or Mode receiver and hardware flow control values using the USART_Init() - function. - 2. Configures the USART address using the USART_SetAddress() function. - 3. Configures the wake up methode (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) - using USART_WakeUpConfig() function only for the slaves. - 4. Enable the USART using the USART_Cmd() function. - 5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. - - The USART Slave exit from mute mode when receive the wake up condition. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the address of the USART node. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_ADDRESS(USART_Address)); - - /* Clear the USART address */ - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD); - /* Set the USART address node */ - USARTx->CR2 |= USART_Address; -} - -/** - * @brief Determines if the USART is in mute mode or not. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param NewState: new state of the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_RWU; - } - else - { - /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU); - } -} -/** - * @brief Selects the USART WakeUp method. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param USART_WakeUp: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - * @retval None - */ -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_WAKEUP(USART_WakeUp)); - - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE); - USARTx->CR1 |= USART_WakeUp; -} - -/** - * @} - */ - -/** @defgroup USART_Group4 LIN mode functions - * @brief LIN mode functions - * -@verbatim - =============================================================================== - LIN mode functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART LIN - Mode communication. - - In LIN mode, 8-bit data format with 1 stop bit is required in accordance with - the LIN standard. - - Only this LIN Feature is supported by the USART IP: - - LIN Master Synchronous Break send capability and LIN slave break detection - capability : 13-bit break generation and 10/11 bit break detection - - - USART LIN Master transmitter communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - 2. Enable the USART using the USART_Cmd() function. - 3. Enable the LIN mode using the USART_LINCmd() function. - 4. Send the break character using USART_SendBreak() function. - - USART LIN Master receiver communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - 2. Enable the USART using the USART_Cmd() function. - 3. Configures the break detection length using the USART_LINBreakDetectLengthConfig() - function. - 4. Enable the LIN mode using the USART_LINCmd() function. - -Note: ----- - 1. In LIN mode, the following bits must be kept cleared: - - CLKEN in the USART_CR2 register, - - STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the USART LIN Break detection length. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param USART_LINBreakDetectLength: specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg USART_LINBreakDetectLength_10b: 10-bit break detection - * @arg USART_LINBreakDetectLength_11b: 11-bit break detection - * @retval None - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); - - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL); - USARTx->CR2 |= USART_LINBreakDetectLength; -} - -/** - * @brief Enables or disables the USARTs LIN mode. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param NewState: new state of the USART LIN mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - USARTx->CR2 |= USART_CR2_LINEN; - } - else - { - /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN); - } -} - -/** - * @brief Transmits break characters. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @retval None - */ -void USART_SendBreak(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Send break characters */ - USARTx->CR1 |= USART_CR1_SBK; -} - -/** - * @} - */ - -/** @defgroup USART_Group5 Halfduplex mode function - * @brief Half-duplex mode function - * -@verbatim - =============================================================================== - Half-duplex mode function - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - Half-duplex communication. - - The USART can be configured to follow a single-wire half-duplex protocol where - the TX and RX lines are internally connected. - - USART Half duplex communication is possible through the following procedure: - 1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter - or Mode receiver and hardware flow control values using the USART_Init() - function. - 2. Configures the USART address using the USART_SetAddress() function. - 3. Enable the USART using the USART_Cmd() function. - 4. Enable the half duplex mode using USART_HalfDuplexCmd() function. - -Note: ----- - 1. The RX pin is no longer used - 2. In Half-duplex mode the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register. - - SCEN and IREN bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USARTs Half Duplex communication. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param NewState: new state of the USART Communication. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_HDSEL; - } - else - { - /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL); - } -} - -/** - * @} - */ - - -/** @defgroup USART_Group6 Smartcard mode functions - * @brief Smartcard mode functions - * -@verbatim - =============================================================================== - Smartcard mode functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - Smartcard communication. - - The Smartcard interface is designed to support asynchronous protocol Smartcards as - defined in the ISO 7816-3 standard. - - The USART can provide a clock to the smartcard through the SCLK output. - In smartcard mode, SCLK is not associated to the communication but is simply derived - from the internal peripheral input clock through a 5-bit prescaler. - - Smartcard communication is possible through the following procedure: - 1. Configures the Smartcard Prsecaler using the USART_SetPrescaler() function. - 2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function. - 3. Program the USART clock using the USART_ClockInit() function as following: - - USART Clock enabled - - USART CPOL Low - - USART CPHA on first edge - - USART Last Bit Clock Enabled - 4. Program the Smartcard interface using the USART_Init() function as following: - - Word Length = 9 Bits - - 1.5 Stop Bit - - Even parity - - BaudRate = 12096 baud - - Hardware flow control disabled (RTS and CTS signals) - - Tx and Rx enabled - 5. Optionally you can enable the parity error interrupt using the USART_ITConfig() - function - 6. Enable the USART using the USART_Cmd() function. - 7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function. - 8. Enable the Smartcard interface using the USART_SmartCardCmd() function. - - Please refer to the ISO 7816-3 specification for more details. - -Note: ------ - 1. It is also possible to choose 0.5 stop bit for receiving but it is recommended - to use 1.5 stop bits for both transmitting and receiving to avoid switching - between the two configurations. - 2. In smartcard mode, the following bits must be kept cleared: - - LINEN bit in the USART_CR2 register. - - HDSEL and IREN bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the specified USART guard time. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param USART_GuardTime: specifies the guard time. - * @retval None - */ -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART Guard time */ - USARTx->GTPR &= USART_GTPR_PSC; - /* Set the USART guard time */ - USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/** - * @brief Enables or disables the USARTs Smart Card mode. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_SCEN; - } - else - { - /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN); - } -} - -/** - * @brief Enables or disables NACK transmission. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param NewState: new state of the NACK transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_NACK; - } - else - { - /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group7 IrDA mode functions - * @brief IrDA mode functions - * -@verbatim - =============================================================================== - IrDA mode functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - IrDA communication. - - IrDA is a half duplex communication protocol. If the Transmitter is busy, any data - on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver - is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. - While receiving data, transmission should be avoided as the data to be transmitted - could be corrupted. - - IrDA communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver - modes and hardware flow control values using the USART_Init() function. - 2. Enable the USART using the USART_Cmd() function. - 3. Configures the IrDA pulse width by configuring the prescaler using - the USART_SetPrescaler() function. - 4. Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode - using the USART_IrDAConfig() function. - 5. Enable the IrDA using the USART_IrDACmd() function. - -Note: ------ - 1. A pulse of width less than two and greater than one PSC period(s) may or may - not be rejected. - 2. The receiver set up time should be managed by software. The IrDA physical layer - specification specifies a minimum of 10 ms delay between transmission and - reception (IrDA is a half duplex protocol). - 3. In IrDA mode, the following bits must be kept cleared: - - LINEN, STOP and CLKEN bits in the USART_CR2 register. - - SCEN and HDSEL bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the USARTs IrDA interface. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param USART_IrDAMode: specifies the IrDA mode. - * This parameter can be one of the following values: - * @arg USART_IrDAMode_LowPower - * @arg USART_IrDAMode_Normal - * @retval None - */ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); - - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP); - USARTx->CR3 |= USART_IrDAMode; -} - -/** - * @brief Enables or disables the USARTs IrDA interface. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param NewState: new state of the IrDA mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_IREN; - } - else - { - /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group8 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USARTs DMA interface. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param USART_DMAReq: specifies the DMA request. - * This parameter can be any combination of the following values: - * @arg USART_DMAReq_Tx: USART DMA transmit request - * @arg USART_DMAReq_Rx: USART DMA receive request - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DMAREQ(USART_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA transfer for selected requests by setting the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 |= USART_DMAReq; - } - else - { - /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 &= (uint16_t)~USART_DMAReq; - } -} - -/** - * @} - */ - -/** @defgroup USART_Group9 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This subsection provides a set of functions allowing to configure the USART - Interrupts sources, DMA channels requests and check or clear the flags or - pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - Polling Mode - ============= - In Polling Mode, the SPI communication can be managed by 10 flags: - 1. USART_FLAG_TXE : to indicate the status of the transmit buffer register - 2. USART_FLAG_RXNE : to indicate the status of the receive buffer register - 3. USART_FLAG_TC : to indicate the status of the transmit operation - 4. USART_FLAG_IDLE : to indicate the status of the Idle Line - 5. USART_FLAG_CTS : to indicate the status of the nCTS input - 6. USART_FLAG_LBD : to indicate the status of the LIN break detection - 7. USART_FLAG_NE : to indicate if a noise error occur - 8. USART_FLAG_FE : to indicate if a frame error occur - 9. USART_FLAG_PE : to indicate if a parity error occur - 10. USART_FLAG_ORE : to indicate if an Overrun error occur - - In this Mode it is advised to use the following functions: - - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); - - void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); - - Interrupt Mode - =============== - In Interrupt Mode, the USART communication can be managed by 8 interrupt sources - and 10 pending bits: - - Pending Bits: - ------------- - 1. USART_IT_TXE : to indicate the status of the transmit buffer register - 2. USART_IT_RXNE : to indicate the status of the receive buffer register - 3. USART_IT_TC : to indicate the status of the transmit operation - 4. USART_IT_IDLE : to indicate the status of the Idle Line - 5. USART_IT_CTS : to indicate the status of the nCTS input - 6. USART_IT_LBD : to indicate the status of the LIN break detection - 7. USART_IT_NE : to indicate if a noise error occur - 8. USART_IT_FE : to indicate if a frame error occur - 9. USART_IT_PE : to indicate if a parity error occur - 10. USART_IT_ORE : to indicate if an Overrun error occur - - Interrupt Source: - ----------------- - 1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty - interrupt. - 2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - 3. USART_IT_TC : specifies the interrupt source for the Transmit complete - interrupt. - 4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. - 5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt. - 6. USART_IT_LBD : specifies the interrupt source for the LIN break detection - interrupt. - 7. USART_IT_PE : specifies the interrupt source for theparity error interrupt. - 8. USART_IT_ERR : specifies the interrupt source for the errors interrupt. - - Note: Some parameters are coded in order to use them as interrupt source or - ---- as pending bits. - - In this Mode it is advised to use the following functions: - - void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); - - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); - - void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - - DMA Mode - ======== - In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: - 1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request - 2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request - - In this Mode it is advised to use the following function: - - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified USART interrupts. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param NewState: new state of the specified USARTx interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CONFIG_IT(USART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - - /* Get the interrupt position */ - itpos = USART_IT & IT_MASK; - itmask = (((uint32_t)0x01) << itpos); - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - usartxbase += 0x0C; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - usartxbase += 0x10; - } - else /* The IT is in CR3 register */ - { - usartxbase += 0x14; - } - if (NewState != DISABLE) - { - *(__IO uint32_t*)usartxbase |= itmask; - } - else - { - *(__IO uint32_t*)usartxbase &= ~itmask; - } -} - -/** - * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param USART_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_CTS: CTS Change flag - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TXE: Transmit data register empty flag - * @arg USART_FLAG_TC: Transmission Complete flag - * @arg USART_FLAG_RXNE: Receive data register not empty flag - * @arg USART_FLAG_IDLE: Idle Line detection flag - * @arg USART_FLAG_ORE: OverRun Error flag - * @arg USART_FLAG_NE: Noise Error flag - * @arg USART_FLAG_FE: Framing Error flag - * @arg USART_FLAG_PE: Parity Error flag - * @retval The new state of USART_FLAG (SET or RESET). - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_FLAG(USART_FLAG)); - - if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the USARTx's pending flags. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param USART_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_CTS: CTS Change flag. - * @arg USART_FLAG_LBD: LIN Break detection flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * - * @note - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DR register (USART_ReceiveData()). - * - RXNE flag can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * - TC flag can be also cleared by software sequence: a read operation to - * USART_SR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DR register (USART_SendData()). - * - TXE flag is cleared only by a write to the USART_DR register - * (USART_SendData()). - * @retval None - */ -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - - USARTx->SR = (uint16_t)~USART_FLAG; -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param USART_IT: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Tansmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ORE: OverRun Error interrupt - * @arg USART_IT_NE: Noise Error interrupt - * @arg USART_IT_FE: Framing Error interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @retval The new state of USART_IT (SET or RESET). - */ -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_GET_IT(USART_IT)); - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - /* Get the interrupt position */ - itmask = USART_IT & IT_MASK; - itmask = (uint32_t)0x01 << itmask; - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - itmask &= USARTx->CR1; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - itmask &= USARTx->CR2; - } - else /* The IT is in CR3 register */ - { - itmask &= USARTx->CR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->SR; - if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Clears the USARTxs interrupt pending bits. - * @param USARTx: Select the USART peripheral. - * This parameter can be one of the following values: - * USART1, USART2 or USART3. - * @param USART_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * - * @note - * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_SR register - * (USART_GetITStatus()) followed by a read operation to USART_DR register - * (USART_ReceiveData()). - * - RXNE pending bit can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * - TC pending bit can be also cleared by software sequence: a read - * operation to USART_SR register (USART_GetITStatus()) followed by a write - * operation to USART_DR register (USART_SendData()). - * - TXE pending bit is cleared only by a write to the USART_DR register - * (USART_SendData()). - * @retval None - */ -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_IT(USART_IT)); - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->SR = (uint16_t)~itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/libs_stm/src/stm32l1xx/stm32l1xx_wwdg.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_wwdg.c deleted file mode 100644 index 9a815d440..000000000 --- a/example/libs_stm/src/stm32l1xx/stm32l1xx_wwdg.c +++ /dev/null @@ -1,307 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_wwdg.c - * @author MCD Application Team - * @version V1.0.0 - * @date 31-December-2010 - * @brief This file provides firmware functions to manage the following - * functionalities of the Window watchdog (WWDG) peripheral: - * - Prescaler, Refresh window and Counter configuration - * - WWDG activation - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * WWDG features - * =================================================================== - * - * Once enabled the WWDG generates a system reset on expiry of a programmed - * time period, unless the program refreshes the counter (downcounter) - * before to reach 0x3F value (i.e. a reset is generated when the counter - * value rolls over from 0x40 to 0x3F). - * An MCU reset is also generated if the counter value is refreshed - * before the counter has reached the refresh window value. This - * implies that the counter must be refreshed in a limited window. - * - * Once enabled the WWDG cannot be disabled except by a system reset. - * - * WWDGRST flag in RCC_CSR register can be used to inform when a WWDG - * reset occurs. - * - * The WWDG counter input clock is derived from the APB clock divided - * by a programmable prescaler. - * - * WWDG counter clock = PCLK1 / Prescaler - * WWDG timeout = (WWDG counter clock) * (counter value) - * - * Min-max timeout value @32MHz (PCLK1): ~128us / ~65.6ms - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function - * - * 2. Configure the WWDG prescaler using WWDG_SetPrescaler() function - * - * 3. Configure the WWDG refresh window using WWDG_SetWindowValue() function - * - * 4. Set the WWDG counter value and start it using WWDG_Enable() function. - * When the WWDG is enabled the counter value should be configured to - * a value greater than 0x40 to prevent generating an immediate reset. - * - * 5. Optionally you can enable the Early wakeup interrupt which is - * generated when the counter reach 0x40. - * Once enabled this interrupt cannot be disabled except by a system reset. - * - * 6. Then the application program must refresh the WWDG counter at regular - * intervals during normal operation to prevent an MCU reset, using - * WWDG_SetCounter() function. This operation must occur only when - * the counter value is lower than the refresh window value, - * programmed using WWDG_SetWindowValue(). - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2010 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_wwdg.h" -#include "stm32l1xx_rcc.h" - -/** @addtogroup STM32L1xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup WWDG - * @brief WWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ----------- WWDG registers bit address in the alias region ----------- */ -#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) - -/* Alias word address of EWI bit */ -#define CFR_OFFSET (WWDG_OFFSET + 0x04) -#define EWI_BitNumber 0x09 -#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) - -/* --------------------- WWDG registers bit mask ------------------------ */ - -/* CFR register bit mask */ -#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) -#define CFR_W_MASK ((uint32_t)0xFFFFFF80) -#define BIT_MASK ((uint8_t)0x7F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup WWDG_Private_Functions - * @{ - */ - -/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions - * @brief Prescaler, Refresh window and Counter configuration functions - * -@verbatim - =============================================================================== - Prescaler, Refresh window and Counter configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the WWDG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/** - * @brief Sets the WWDG Prescaler. - * @param WWDG_Prescaler: specifies the WWDG Prescaler. - * This parameter can be one of the following values: - * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 - * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 - * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 - * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 - * @retval None - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); - /* Clear WDGTB[1:0] bits */ - tmpreg = WWDG->CFR & CFR_WDGTB_MASK; - /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ - tmpreg |= WWDG_Prescaler; - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Sets the WWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * This parameter value must be lower than 0x80. - * @retval None - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); - /* Clear W[6:0] bits */ - - tmpreg = WWDG->CFR & CFR_W_MASK; - - /* Set W[6:0] bits according to WindowValue value */ - tmpreg |= WindowValue & (uint32_t) BIT_MASK; - - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Enables the WWDG Early Wakeup interrupt(EWI). - * @note Once enabled this interrupt cannot be disabled except by a system reset. - * @param None - * @retval None - */ -void WWDG_EnableIT(void) -{ - *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; -} - -/** - * @brief Sets the WWDG counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent generating - * an immediate reset) - * @retval None - */ -void WWDG_SetCounter(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to T[6:0] bits to configure the counter value, no need to do - a read-modify-write; writing a 0 to WDGA bit does nothing */ - WWDG->CR = Counter & BIT_MASK; -} - -/** - * @} - */ - -/** @defgroup WWDG_Group2 WWDG activation functions - * @brief WWDG activation functions - * -@verbatim - =============================================================================== - WWDG activation functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables WWDG and load the counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent generating - * an immediate reset) - * @retval None - */ -void WWDG_Enable(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - WWDG->CR = WWDG_CR_WDGA | Counter; -} - -/** - * @} - */ - -/** @defgroup WWDG_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the Early Wakeup interrupt flag is set or not. - * @param None - * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((WWDG->SR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears Early Wakeup interrupt flag. - * @param None - * @retval None - */ -void WWDG_ClearFlag(void) -{ - WWDG->SR = (uint32_t)RESET; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/IO_Toggle/Makefile b/example/stm32f4/Projects/IO_Toggle/Makefile deleted file mode 100644 index ef8860af4..000000000 --- a/example/stm32f4/Projects/IO_Toggle/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -EXECUTABLE=IO_Toggle.elf -BIN_IMAGE=IO_Toggle.bin - -CC=arm-none-eabi-gcc -OBJCOPY=arm-none-eabi-objcopy - -CFLAGS=-g -O2 -mlittle-endian -mthumb -CFLAGS+=-mcpu=cortex-m4 -CFLAGS+=-ffreestanding -nostdlib - -# to run from FLASH -CFLAGS+=-Wl,-T,stm32_flash.ld - -# stm32f4_discovery lib -CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc -CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc/device_support -CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc/core_support - -all: $(BIN_IMAGE) - -$(BIN_IMAGE): $(EXECUTABLE) - $(OBJCOPY) -O binary $^ $@ - -$(EXECUTABLE): main.c system_stm32f4xx.c startup_stm32f4xx.s stm32f4xx_it.c - $(CC) $(CFLAGS) $^ -o $@ -L../../STM32F4xx_StdPeriph_Driver/build -lSTM32F4xx_StdPeriph_Driver - -clean: - rm -rf $(EXECUTABLE) - rm -rf $(BIN_IMAGE) - -.PHONY: all clean diff --git a/example/stm32f4/Projects/IO_Toggle/main.c b/example/stm32f4/Projects/IO_Toggle/main.c deleted file mode 100644 index 152c64b9c..000000000 --- a/example/stm32f4/Projects/IO_Toggle/main.c +++ /dev/null @@ -1,142 +0,0 @@ -/** - ****************************************************************************** - * @file IO_Toggle/main.c - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief Main program body - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4_discovery.h" -#include "stm32f4xx_conf.h" - -/** @addtogroup STM32F4_Discovery_Peripheral_Examples - * @{ - */ - -/** @addtogroup IO_Toggle - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -GPIO_InitTypeDef GPIO_InitStructure; - -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -void Delay(__IO uint32_t nCount); -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief Main program - * @param None - * @retval None - */ -int main(void) -{ - /*!< At this stage the microcontroller clock setting is already configured, - this is done through SystemInit() function which is called from startup - file (startup_stm32f4xx.s) before to branch to application main. - To reconfigure the default setting of SystemInit() function, refer to - system_stm32f4xx.c file - */ - - /* GPIOD Periph clock enable */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE); - - /* Configure PD12, PD13, PD14 and PD15 in output pushpull mode */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13| GPIO_Pin_14| GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - while (1) - { - /* PD12 to be toggled */ - GPIO_SetBits(GPIOD, GPIO_Pin_12); - - /* Insert delay */ - Delay(0x3FFFFF); - - /* PD13 to be toggled */ - GPIO_SetBits(GPIOD, GPIO_Pin_13); - - /* Insert delay */ - Delay(0x3FFFFF); - - /* PD14 to be toggled */ - GPIO_SetBits(GPIOD, GPIO_Pin_14); - - /* Insert delay */ - Delay(0x3FFFFF); - - /* PD15 to be toggled */ - GPIO_SetBits(GPIOD, GPIO_Pin_15); - - /* Insert delay */ - Delay(0x7FFFFF); - - GPIO_ResetBits(GPIOD, GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14|GPIO_Pin_15); - - /* Insert delay */ - Delay(0xFFFFFF); - } -} - -/** - * @brief Delay Function. - * @param nCount:specifies the Delay time length. - * @retval None - */ -void Delay(__IO uint32_t nCount) -{ - while(nCount--) - { - } -} - -#ifdef USE_FULL_ASSERT - -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t* file, uint32_t line) -{ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - - /* Infinite loop */ - while (1) - { - } -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/IO_Toggle/readme.txt b/example/stm32f4/Projects/IO_Toggle/readme.txt deleted file mode 100644 index fda5b2ef2..000000000 --- a/example/stm32f4/Projects/IO_Toggle/readme.txt +++ /dev/null @@ -1,91 +0,0 @@ -/** - @page GPIO_IOToggle GPIO IO Toggle example - - @verbatim - ******************** (C) COPYRIGHT 2011 STMicroelectronics ******************* - * @file IO_Toggle/readme.txt - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief Description of the GPIO IO Toggle example. - ****************************************************************************** - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - ****************************************************************************** - @endverbatim - -@par Example Description - -This example describes how to toggle the GPIO pins connected on AHB bus. - -PD12, PD13, PD14 and PD15 (configured in output pushpull mode) toggles in a forever loop. - - Set PD12, PD13, PD14 and PD15 by setting corresponding bits in BSRRL register - - Reset PD12, PD13, PD14 and PD15 by setting corresponding bits in BSRRH register - -In this example, HCLK is configured at 168 MHz. - -@par Directory contents - - - IO_Toggle/stm32f4xx_conf.h Library Configuration file - - IO_Toggle/stm32f4xx_it.c Interrupt handlers - - IO_Toggle/stm32f4xx_it.h Interrupt handlers header file - - IO_Toggle/main.c Main program - - IO_Toggle/system_stm32f4xx.c STM32F4xx system source file - -@par Hardware and Software environment - - - This example runs on STM32F4xx Devices Revision A. - - - This example has been tested with STM32F4-Discovery (MB997) RevA and can be - easily tailored to any other development board - - - STM32F4-Discovery - - LED4, LED3, LED5 and LED6 are connected respectively to PD.12, PD.13, PD.14 and PD.15. - - -@par How to use it ? - -In order to make the program work, you must do the following : - - + EWARM - - Open the IO_Toggle.eww workspace - - Rebuild all files: Project->Rebuild all - - Load project image: Project->Debug - - Run program: Debug->Go(F5) - - + MDK-ARM - - Open the IO_Toggle.uvproj project - - Rebuild all files: Project->Rebuild all target files - - Load project image: Debug->Start/Stop Debug Session - - Run program: Debug->Run (F5) - - + TASKING - - Open TASKING toolchain. - - Click on File->Import, select General->'Existing Projects into Workspace' - and then click "Next". - - Browse to TASKING workspace directory and select the project "IO_Toggle" - - Rebuild all project files: Select the project in the "Project explorer" - window then click on Project->build project menu. - - Run program: Select the project in the "Project explorer" window then click - Run->Debug (F11) - - + TrueSTUDIO - - Open the TrueSTUDIO toolchain. - - Click on File->Switch Workspace->Other and browse to TrueSTUDIO workspace - directory. - - Click on File->Import, select General->'Existing Projects into Workspace' - and then click "Next". - - Browse to the TrueSTUDIO workspace directory and select the project "IO_Toggle" - - Rebuild all project files: Select the project in the "Project explorer" - window then click on Project->build project menu. - - Run program: Select the project in the "Project explorer" window then click - Run->Debug (F11) - - - - *

© COPYRIGHT 2011 STMicroelectronics

- */ diff --git a/example/stm32f4/Projects/IO_Toggle/startup_stm32f4xx.s b/example/stm32f4/Projects/IO_Toggle/startup_stm32f4xx.s deleted file mode 100644 index ce5360f3c..000000000 --- a/example/stm32f4/Projects/IO_Toggle/startup_stm32f4xx.s +++ /dev/null @@ -1,509 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f4xx.s - * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 - * @brief STM32F4xx Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system and the external SRAM mounted on - * STM324xG-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FSMC_IRQHandler /* FSMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word CRYP_IRQHandler /* CRYP crypto */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - .word FPU_IRQHandler /* FPU */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak CRYP_IRQHandler - .thumb_set CRYP_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/IO_Toggle/stm32_flash.ld b/example/stm32f4/Projects/IO_Toggle/stm32_flash.ld deleted file mode 100644 index 1a0b4b860..000000000 --- a/example/stm32f4/Projects/IO_Toggle/stm32_flash.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* -***************************************************************************** -** -** File : stm32_flash.ld -** -** Abstract : Linker script for STM32F407VG Device with -** 1024KByte FLASH, 192KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** Environment : Atollic TrueSTUDIO(R) -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -** (c)Copyright Atollic AB. -** You may use this file as-is or modify it according to the needs of your -** project. Distribution of this file (unmodified or modified) is not -** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the -** rights to distribute the assembled, compiled & linked contents of this -** file as part of an application binary file, provided that it is built -** using the Atollic TrueSTUDIO(R) toolchain. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x20020000; /* end of 128K RAM on AHB bus*/ - -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 192K - MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(.fini_array*)) - KEEP (*(SORT(.fini_array.*))) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = .; - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : AT ( _sidata ) - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(4); - } >RAM - - /* MEMORY_bank1 section, code must be located here explicitly */ - /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ - .memory_b1_text : - { - *(.mb1text) /* .mb1text sections (code) */ - *(.mb1text*) /* .mb1text* sections (code) */ - *(.mb1rodata) /* read-only data (constants) */ - *(.mb1rodata*) - } >MEMORY_B1 - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/example/stm32f4/Projects/IO_Toggle/stm32f4_discovery.h b/example/stm32f4/Projects/IO_Toggle/stm32f4_discovery.h deleted file mode 100644 index c6fec4221..000000000 --- a/example/stm32f4/Projects/IO_Toggle/stm32f4_discovery.h +++ /dev/null @@ -1,158 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4_discovery.h - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief This file contains definitions for STM32F4-Discovery Kit's Leds and - * push-button hardware resources. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4_DISCOVERY_H -#define __STM32F4_DISCOVERY_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ - #include "stm32f4xx.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL - * @{ - */ - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Types - * @{ - */ -typedef enum -{ - LED4 = 0, - LED3 = 1, - LED5 = 2, - LED6 = 3 -} Led_TypeDef; - -typedef enum -{ - BUTTON_USER = 0, -} Button_TypeDef; - -typedef enum -{ - BUTTON_MODE_GPIO = 0, - BUTTON_MODE_EXTI = 1 -} ButtonMode_TypeDef; -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_LED - * @{ - */ -#define LEDn 4 - -#define LED4_PIN GPIO_Pin_12 -#define LED4_GPIO_PORT GPIOD -#define LED4_GPIO_CLK RCC_AHB1Periph_GPIOD - -#define LED3_PIN GPIO_Pin_13 -#define LED3_GPIO_PORT GPIOD -#define LED3_GPIO_CLK RCC_AHB1Periph_GPIOD - -#define LED5_PIN GPIO_Pin_14 -#define LED5_GPIO_PORT GPIOD -#define LED5_GPIO_CLK RCC_AHB1Periph_GPIOD - -#define LED6_PIN GPIO_Pin_15 -#define LED6_GPIO_PORT GPIOD -#define LED6_GPIO_CLK RCC_AHB1Periph_GPIOD -/** - * @} - */ - -/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_BUTTON - * @{ - */ -#define BUTTONn 1 - -/** - * @brief Wakeup push-button - */ -#define USER_BUTTON_PIN GPIO_Pin_0 -#define USER_BUTTON_GPIO_PORT GPIOA -#define USER_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOA -#define USER_BUTTON_EXTI_LINE EXTI_Line0 -#define USER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA -#define USER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0 -#define USER_BUTTON_EXTI_IRQn EXTI0_IRQn -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Functions - * @{ - */ -void STM_EVAL_LEDInit(Led_TypeDef Led); -void STM_EVAL_LEDOn(Led_TypeDef Led); -void STM_EVAL_LEDOff(Led_TypeDef Led); -void STM_EVAL_LEDToggle(Led_TypeDef Led); -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode); -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4_DISCOVERY_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/IO_Toggle/stm32f4xx_conf.h b/example/stm32f4/Projects/IO_Toggle/stm32f4xx_conf.h deleted file mode 100644 index abd159f6b..000000000 --- a/example/stm32f4/Projects/IO_Toggle/stm32f4xx_conf.h +++ /dev/null @@ -1,94 +0,0 @@ -/** - ****************************************************************************** - * @file IO_Toggle/stm32f4xx_conf.h - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief Library configuration file. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_CONF_H -#define __STM32F4xx_CONF_H - -#if defined (HSE_VALUE) -/* Redefine the HSE value; it's equal to 8 MHz on the STM32F4-DISCOVERY Kit */ - #undef HSE_VALUE - #define HSE_VALUE ((uint32_t)8000000) -#endif /* HSE_VALUE */ - -/* Includes ------------------------------------------------------------------*/ -/* Uncomment the line below to enable peripheral header file inclusion */ -#include "stm32f4xx_adc.h" -#include "stm32f4xx_can.h" -#include "stm32f4xx_crc.h" -#include "stm32f4xx_cryp.h" -#include "stm32f4xx_dac.h" -#include "stm32f4xx_dbgmcu.h" -#include "stm32f4xx_dcmi.h" -#include "stm32f4xx_dma.h" -#include "stm32f4xx_exti.h" -#include "stm32f4xx_flash.h" -#include "stm32f4xx_fsmc.h" -#include "stm32f4xx_hash.h" -#include "stm32f4xx_gpio.h" -#include "stm32f4xx_i2c.h" -#include "stm32f4xx_iwdg.h" -#include "stm32f4xx_pwr.h" -#include "stm32f4xx_rcc.h" -#include "stm32f4xx_rng.h" -#include "stm32f4xx_rtc.h" -#include "stm32f4xx_sdio.h" -#include "stm32f4xx_spi.h" -#include "stm32f4xx_syscfg.h" -#include "stm32f4xx_tim.h" -#include "stm32f4xx_usart.h" -#include "stm32f4xx_wwdg.h" -#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* If an external clock source is used, then the value of the following define - should be set to the value of the external clock source, else, if no external - clock is used, keep this define commented */ -/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ - - -/* Uncomment the line below to expanse the "assert_param" macro in the - Standard Peripheral Library drivers code */ -/* #define USE_FULL_ASSERT 1 */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT - -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - -#endif /* __STM32F4xx_CONF_H */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/IO_Toggle/stm32f4xx_it.c b/example/stm32f4/Projects/IO_Toggle/stm32f4xx_it.c deleted file mode 100644 index ceac51ac4..000000000 --- a/example/stm32f4/Projects/IO_Toggle/stm32f4xx_it.c +++ /dev/null @@ -1,167 +0,0 @@ -/** - ****************************************************************************** - * @file IO_Toggle/stm32f4xx_it.c - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief Main Interrupt Service Routines. - * This file provides template for all exceptions handler and - * peripherals interrupt service routine. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_it.h" - -/** @addtogroup STM32F4_Discovery_Peripheral_Examples - * @{ - */ - -/** @addtogroup IO_Toggle - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/******************************************************************************/ -/* Cortex-M4 Processor Exceptions Handlers */ -/******************************************************************************/ - -/** - * @brief This function handles NMI exception. - * @param None - * @retval None - */ -void NMI_Handler(void) -{ -} - -/** - * @brief This function handles Hard Fault exception. - * @param None - * @retval None - */ -void HardFault_Handler(void) -{ - /* Go to infinite loop when Hard Fault exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles Memory Manage exception. - * @param None - * @retval None - */ -void MemManage_Handler(void) -{ - /* Go to infinite loop when Memory Manage exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles Bus Fault exception. - * @param None - * @retval None - */ -void BusFault_Handler(void) -{ - /* Go to infinite loop when Bus Fault exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles Usage Fault exception. - * @param None - * @retval None - */ -void UsageFault_Handler(void) -{ - /* Go to infinite loop when Usage Fault exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles SVCall exception. - * @param None - * @retval None - */ -void SVC_Handler(void) -{ -} - -/** - * @brief This function handles Debug Monitor exception. - * @param None - * @retval None - */ -void DebugMon_Handler(void) -{ -} - -/** - * @brief This function handles PendSVC exception. - * @param None - * @retval None - */ -void PendSV_Handler(void) -{ -} - -/** - * @brief This function handles SysTick Handler. - * @param None - * @retval None - */ -void SysTick_Handler(void) -{ -} - -/******************************************************************************/ -/* STM32F4xx Peripherals Interrupt Handlers */ -/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ -/* available peripheral interrupt handler's name please refer to the startup */ -/* file (startup_stm32f4xx.s). */ -/******************************************************************************/ - -/** - * @brief This function handles PPP interrupt request. - * @param None - * @retval None - */ -/*void PPP_IRQHandler(void) -{ -}*/ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/IO_Toggle/stm32f4xx_it.h b/example/stm32f4/Projects/IO_Toggle/stm32f4xx_it.h deleted file mode 100644 index 74f17c9cc..000000000 --- a/example/stm32f4/Projects/IO_Toggle/stm32f4xx_it.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - ****************************************************************************** - * @file GPIO/IOToggle/stm32f4xx_it.h - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_IT_H -#define __STM32F4xx_IT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void NMI_Handler(void); -void HardFault_Handler(void); -void MemManage_Handler(void); -void BusFault_Handler(void); -void UsageFault_Handler(void); -void SVC_Handler(void); -void DebugMon_Handler(void); -void PendSV_Handler(void); -void SysTick_Handler(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_IT_H */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/IO_Toggle/system_stm32f4xx.c b/example/stm32f4/Projects/IO_Toggle/system_stm32f4xx.c deleted file mode 100644 index b058084b6..000000000 --- a/example/stm32f4/Projects/IO_Toggle/system_stm32f4xx.c +++ /dev/null @@ -1,545 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f4xx.c - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32F4xx devices, - * and is generated by the clock configuration tool - * stm32f4xx_Clock_Configuration_V1.0.0.xls - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f4xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 8 MHz, refer to "HSE_VALUE" define - * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - *============================================================================= - * Supported STM32F4xx device revision | Rev A - *----------------------------------------------------------------------------- - * System Clock source | PLL (HSE) - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 168000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 168000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 4 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 2 - *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | 8000000 - *----------------------------------------------------------------------------- - * PLL_M | 8 - *----------------------------------------------------------------------------- - * PLL_N | 336 - *----------------------------------------------------------------------------- - * PLL_P | 2 - *----------------------------------------------------------------------------- - * PLL_Q | 7 - *----------------------------------------------------------------------------- - * PLLI2S_N | NA - *----------------------------------------------------------------------------- - * PLLI2S_R | NA - *----------------------------------------------------------------------------- - * I2S input clock | NA - *----------------------------------------------------------------------------- - * VDD(V) | 3.3 - *----------------------------------------------------------------------------- - * High Performance mode | Enabled - *----------------------------------------------------------------------------- - * Flash Latency(WS) | 5 - *----------------------------------------------------------------------------- - * Prefetch Buffer | OFF - *----------------------------------------------------------------------------- - * Instruction cache | ON - *----------------------------------------------------------------------------- - * Data cache | ON - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Enabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** @addtogroup STM32F4xx_System_Private_Includes - * @{ - */ - -#include "stm32f4xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Defines - * @{ - */ - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM324xG_EVAL board as data memory */ -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ -#define PLL_M 8 -#define PLL_N 336 - -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 2 - -/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ -#define PLL_Q 7 - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Variables - * @{ - */ - - uint32_t SystemCoreClock = 168000000; - - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable high performance mode, System frequency up to 168 MHz */ - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - PWR->CR |= PWR_CR_PMODE; - - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till the main PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } - -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f4xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f4xx.s before jump to main. - * This function configures the external SRAM mounted on STM324xG_EVAL board - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+------------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+------------------+ - | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | - | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | - | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | - | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | - | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | - | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | - | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | - | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+ - | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 | - | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 | - | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+ - | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 | - | | PE15 <-> FSMC_D12 | - +-------------------+--------------------+ -*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR = 0x00000078; - - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00cc00cc; - GPIOD->AFR[1] = 0xcc0ccccc; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xaaaa0a0a; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xffff0f0f; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xc00cc0cc; - GPIOE->AFR[1] = 0xcccccccc; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xaaaa828a; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xffffc3cf; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00cccccc; - GPIOF->AFR[1] = 0xcccc0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xaa000aaa; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xff000fff; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00cccccc; - GPIOG->AFR[1] = 0x000000c0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00080aaa; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000c0fff; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FSMC Configuration ------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHB3ENR = 0x00000001; - - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001015; - FSMC_Bank1->BTCR[3] = 0x00010603;//0x00010400; - FSMC_Bank1E->BWTR[2] = 0x0fffffff; -/* - Bank1_SRAM2 is configured as follow: - - p.FSMC_AddressSetupTime = 3;//0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 6;//4; - p.FSMC_BusTurnAroundDuration = 1; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; -*/ - -} -#endif /* DATA_IN_ExtSRAM */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/Projects/discovery_demo/Makefile b/example/stm32f4/Projects/discovery_demo/Makefile deleted file mode 100644 index 01a2d860e..000000000 --- a/example/stm32f4/Projects/discovery_demo/Makefile +++ /dev/null @@ -1,61 +0,0 @@ -EXECUTABLE=STM32F4-Discovery_Demo.elf -BIN_IMAGE=STM32F4-Discovery_Demo.bin - -CC=arm-none-eabi-gcc -OBJCOPY=arm-none-eabi-objcopy - -CFLAGS=-g -O2 -mlittle-endian -mthumb -CFLAGS+=-mcpu=cortex-m4 -CFLAGS+=-ffreestanding -nostdlib - -#usb_conf.h -CFLAGS+=-DUSE_USB_OTG_FS=1 - -# to run from FLASH -CFLAGS+=-Wl,-T,stm32_flash.ld - -CFLAGS+=-I./ - -# stm32f4_discovery lib -CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc -CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc/device_support -CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc/core_support - -#STM32_USB_Device_Library -CFLAGS+=-I../../STM32_USB_Device_Library/Class/hid/inc -CFLAGS+=-I../../STM32_USB_Device_Library/Core/inc - -#STM32_USB_OTG_Driver -CFLAGS+=-I../../STM32_USB_OTG_Driver/inc - -#STM32F4xx_StdPeriph_Driver\inc -CFLAGS+=-I../../STM32F4xx_StdPeriph_Driver/inc - -#Utilities -CFLAGS+=-I../../Utilities/STM32F4-Discovery - -all: $(BIN_IMAGE) - -$(BIN_IMAGE): $(EXECUTABLE) - $(OBJCOPY) -O binary $^ $@ - -$(EXECUTABLE): main.c selftest.c system_stm32f4xx.c startup_stm32f4xx.s stm32f4xx_it.c \ - usb_bsp.c usbd_desc.c usbd_usr.c usb_core.c \ - ../../Utilities/STM32F4-Discovery/stm32f4_discovery.c \ - ../../Utilities/STM32F4-Discovery/stm32f4_discovery_audio_codec.c \ - ../../Utilities/STM32F4-Discovery/stm32f4_discovery_lis302dl.c \ - ../../STM32_USB_OTG_Driver/src/usb_dcd_int.c \ - ../../STM32_USB_OTG_Driver/src/usb_dcd.c \ - ../../STM32_USB_Device_Library/Core/src/usbd_core.c \ - ../../STM32_USB_Device_Library/Core/src/usbd_req.c \ - ../../STM32_USB_Device_Library/Core/src/usbd_ioreq.c \ - ../../STM32_USB_Device_Library/Class/hid/src/usbd_hid_core.c \ - - - $(CC) $(CFLAGS) $^ -o $@ -L../../STM32F4xx_StdPeriph_Driver/build -lSTM32F4xx_StdPeriph_Driver -L../../STM32F_USB_OTG_Driver/build - -clean: - rm -rf $(EXECUTABLE) - rm -rf $(BIN_IMAGE) - -.PHONY: all clean diff --git a/example/stm32f4/Projects/discovery_demo/Release_Notes.html b/example/stm32f4/Projects/discovery_demo/Release_Notes.html deleted file mode 100644 index 304ad5d9f..000000000 --- a/example/stm32f4/Projects/discovery_demo/Release_Notes.html +++ /dev/null @@ -1,151 +0,0 @@ - - - - - - - - - - - - - - - - Release Notes for STM32F4-Discovery Board Demonstration firmware - - - - - - - - - - -
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Release -Notes for STM32F4-Discovery Board Demonstration firmware

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Copyright -2011 STMicroelectronics

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Contents

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  1. STM32F4-Discovery Board Demonstration firmware update History
    2. -
  2. License
    3. -
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STM32F4-Discovery Board Demonstration firmware update History

For more information on the STM32F4-Discovery board visit www.st.com/stm32f4-discovery.

V1.0.0 / 19-September-2011

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Main -Changes

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  • First official version of the STM32F4-Discovery Board Demonstration firmware

License

-

The -enclosed firmware and all the related documentation are not covered by -a License Agreement, if you need such License you can contact your -local STMicroelectronics office.

- - THE -PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO -SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR -ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY -CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY -CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH -THEIR PRODUCTS. - -
-
-

For -complete documentation on STMicroelectronics Microcontrollers visit www.st.com

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- - \ No newline at end of file diff --git a/example/stm32f4/Projects/discovery_demo/main.c b/example/stm32f4/Projects/discovery_demo/main.c deleted file mode 100644 index 761e761a3..000000000 --- a/example/stm32f4/Projects/discovery_demo/main.c +++ /dev/null @@ -1,508 +0,0 @@ -/** - ****************************************************************************** - * @file main.c - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief Main program body - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -#include "usbd_hid_core.h" -#include "usbd_usr.h" -#include "usbd_desc.h" - -//Library config for this project!!!!!!!!!!! -#include "stm32f4xx_conf.h" - -/** @addtogroup STM32F4-Discovery_Demo - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define TESTRESULT_ADDRESS 0x080FFFFC -#define ALLTEST_PASS 0x00000000 -#define ALLTEST_FAIL 0x55555555 - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment = 4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN USB_OTG_CORE_HANDLE USB_OTG_dev __ALIGN_END; - -uint16_t PrescalerValue = 0; - -__IO uint32_t TimingDelay; -__IO uint8_t DemoEnterCondition = 0x00; -__IO uint8_t UserButtonPressed = 0x00; -LIS302DL_InitTypeDef LIS302DL_InitStruct; -LIS302DL_FilterConfigTypeDef LIS302DL_FilterStruct; -__IO int8_t X_Offset, Y_Offset, Z_Offset = 0x00; -uint8_t Buffer[6]; - -/* Private function prototypes -----------------------------------------------*/ -static uint32_t Demo_USBConfig(void); -static void TIM4_Config(void); -static void Demo_Exec(void); - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief Main program. - * @param None - * @retval None - */ -int main(void) -{ - RCC_ClocksTypeDef RCC_Clocks; - - /* Initialize LEDs and User_Button on STM32F4-Discovery --------------------*/ - STM_EVAL_PBInit(BUTTON_USER, BUTTON_MODE_EXTI); - - STM_EVAL_LEDInit(LED4); - STM_EVAL_LEDInit(LED3); - STM_EVAL_LEDInit(LED5); - STM_EVAL_LEDInit(LED6); - - /* SysTick end of count event each 10ms */ - RCC_GetClocksFreq(&RCC_Clocks); - SysTick_Config(RCC_Clocks.HCLK_Frequency / 100); - - if (STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET) - { - /* Turn on LEDs available on STM32F4-Discovery ---------------------------*/ - STM_EVAL_LEDOn(LED4); - STM_EVAL_LEDOn(LED3); - STM_EVAL_LEDOn(LED5); - STM_EVAL_LEDOn(LED6); - - if ((*(__IO uint32_t*) TESTRESULT_ADDRESS) == ALLTEST_PASS) - { - TimingDelay = 300; - /* Waiting User Button is pressed or Test Program condition verified */ - while ((STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)&&(TimingDelay != 0x00)) - {} - } - else - { - /* Waiting User Button is Released or TimeOut*/ - TimingDelay = 300; - while ((STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET)&&(TimingDelay != 0x00)) - {} - if (STM_EVAL_PBGetState(BUTTON_USER) == Bit_RESET) - { - TimingDelay = 0x00; - } - } - if (TimingDelay == 0x00) - { - /* Turn off LEDs available on STM32F4-Discovery ------------------------*/ - STM_EVAL_LEDOff(LED4); - STM_EVAL_LEDOff(LED3); - STM_EVAL_LEDOff(LED5); - STM_EVAL_LEDOff(LED6); - - /* Waiting User Button is released */ - while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET) - {} - - /* Unlocks the FLASH control register access */ - FLASH_Unlock(); - - /* Move discovery kit to detect negative and positive acceleration values - on X, Y and Z axis */ - Accelerometer_MEMS_Test(); - - /* USB Hardware connection */ - USB_Test(); - - /* Audio Hardware connection */ - Audio_Test(); - - /* Microphone MEMS Hardware connection */ - Microphone_MEMS_Test(); - - /* Write PASS code at last word in the flash memory */ - FLASH_ProgramWord(TESTRESULT_ADDRESS, ALLTEST_PASS); - - while(1) - { - /* Toggle Green LED: signaling the End of the Test program */ - STM_EVAL_LEDToggle(LED4); - Delay(10); - } - } - else - { - Demo_Exec(); - } - } - else - { - Demo_Exec(); - } -} - -/** - * @brief Execute the demo application. - * @param None - * @retval None - */ -static void Demo_Exec(void) -{ - RCC_ClocksTypeDef RCC_Clocks; - uint8_t togglecounter = 0x00; - - while(1) - { - DemoEnterCondition = 0x00; - - /* Reset UserButton_Pressed variable */ - UserButtonPressed = 0x00; - - /* Initialize LEDs to be managed by GPIO */ - STM_EVAL_LEDInit(LED4); - STM_EVAL_LEDInit(LED3); - STM_EVAL_LEDInit(LED5); - STM_EVAL_LEDInit(LED6); - - /* SysTick end of count event each 10ms */ - RCC_GetClocksFreq(&RCC_Clocks); - SysTick_Config(RCC_Clocks.HCLK_Frequency / 100); - - /* Turn OFF all LEDs */ - STM_EVAL_LEDOff(LED4); - STM_EVAL_LEDOff(LED3); - STM_EVAL_LEDOff(LED5); - STM_EVAL_LEDOff(LED6); - - /* Waiting User Button is pressed */ - while (UserButtonPressed == 0x00) - { - /* Toggle LED4 */ - STM_EVAL_LEDToggle(LED4); - Delay(10); - /* Toggle LED4 */ - STM_EVAL_LEDToggle(LED3); - Delay(10); - /* Toggle LED4 */ - STM_EVAL_LEDToggle(LED5); - Delay(10); - /* Toggle LED4 */ - STM_EVAL_LEDToggle(LED6); - Delay(10); - togglecounter ++; - if (togglecounter == 0x10) - { - togglecounter = 0x00; - while (togglecounter < 0x10) - { - STM_EVAL_LEDToggle(LED4); - STM_EVAL_LEDToggle(LED3); - STM_EVAL_LEDToggle(LED5); - STM_EVAL_LEDToggle(LED6); - Delay(10); - togglecounter ++; - } - togglecounter = 0x00; - } - } - - /* Waiting User Button is Released */ - while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET) - {} - UserButtonPressed = 0x00; - - /* TIM4 channels configuration */ - TIM4_Config(); - - /* Disable all Timer4 channels */ - TIM_CCxCmd(TIM4, TIM_Channel_1, DISABLE); - TIM_CCxCmd(TIM4, TIM_Channel_2, DISABLE); - TIM_CCxCmd(TIM4, TIM_Channel_3, DISABLE); - TIM_CCxCmd(TIM4, TIM_Channel_4, DISABLE); - - /* MEMS configuration */ - LIS302DL_InitStruct.Power_Mode = LIS302DL_LOWPOWERMODE_ACTIVE; - LIS302DL_InitStruct.Output_DataRate = LIS302DL_DATARATE_100; - LIS302DL_InitStruct.Axes_Enable = LIS302DL_XYZ_ENABLE; - LIS302DL_InitStruct.Full_Scale = LIS302DL_FULLSCALE_2_3; - LIS302DL_InitStruct.Self_Test = LIS302DL_SELFTEST_NORMAL; - LIS302DL_Init(&LIS302DL_InitStruct); - - /* Required delay for the MEMS Accelerometre: Turn-on time = 3/Output data Rate - = 3/100 = 30ms */ - Delay(30); - - DemoEnterCondition = 0x01; - /* MEMS High Pass Filter configuration */ - LIS302DL_FilterStruct.HighPassFilter_Data_Selection = LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER; - LIS302DL_FilterStruct.HighPassFilter_CutOff_Frequency = LIS302DL_HIGHPASSFILTER_LEVEL_1; - LIS302DL_FilterStruct.HighPassFilter_Interrupt = LIS302DL_HIGHPASSFILTERINTERRUPT_1_2; - LIS302DL_FilterConfig(&LIS302DL_FilterStruct); - - LIS302DL_Read(Buffer, LIS302DL_OUT_X_ADDR, 6); - X_Offset = Buffer[0]; - Y_Offset = Buffer[2]; - Z_Offset = Buffer[4]; - - /* USB configuration */ - Demo_USBConfig(); - - /* Waiting User Button is pressed */ - while (UserButtonPressed == 0x00) - {} - - /* Waiting User Button is Released */ - while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET) - {} - - /* Disable SPI1 used to drive the MEMS accelerometre */ - SPI_Cmd(LIS302DL_SPI, DISABLE); - - /* Disconnect the USB device */ - DCD_DevDisconnect(&USB_OTG_dev); - USB_OTG_StopDevice(&USB_OTG_dev); - } -} - -/** - * @brief Initializes the USB for the demonstration application. - * @param None - * @retval None - */ -static uint32_t Demo_USBConfig(void) -{ - USBD_Init(&USB_OTG_dev, - USB_OTG_FS_CORE_ID, - &USR_desc, - &USBD_HID_cb, - &USR_cb); - - return 0; -} - -/** - * @brief Configures the TIM Peripheral. - * @param None - * @retval None - */ -static void TIM4_Config(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - TIM_OCInitTypeDef TIM_OCInitStructure; - TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; - - /* --------------------------- System Clocks Configuration -----------------*/ - /* TIM4 clock enable */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE); - - /* GPIOD clock enable */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE); - - /*-------------------------- GPIO Configuration ----------------------------*/ - /* GPIOD Configuration: Pins 12, 13, 14 and 15 in output push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /* Connect TIM4 pins to AF2 */ - GPIO_PinAFConfig(GPIOD, GPIO_PinSource12, GPIO_AF_TIM4); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource13, GPIO_AF_TIM4); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_TIM4); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_TIM4); - - /* ----------------------------------------------------------------------- - TIM4 Configuration: Output Compare Timing Mode: - - In this example TIM4 input clock (TIM4CLK) is set to 2 * APB1 clock (PCLK1), - since APB1 prescaler is different from 1 (APB1 Prescaler = 4, see system_stm32f4xx.c file). - TIM4CLK = 2 * PCLK1 - PCLK1 = HCLK / 4 - => TIM4CLK = 2*(HCLK / 4) = HCLK/2 = SystemCoreClock/2 - - To get TIM4 counter clock at 2 KHz, the prescaler is computed as follows: - Prescaler = (TIM4CLK / TIM1 counter clock) - 1 - Prescaler = (168 MHz/(2 * 2 KHz)) - 1 = 41999 - - To get TIM4 output clock at 1 Hz, the period (ARR)) is computed as follows: - ARR = (TIM4 counter clock / TIM4 output clock) - 1 - = 1999 - - TIM4 Channel1 duty cycle = (TIM4_CCR1/ TIM4_ARR)* 100 = 50% - TIM4 Channel2 duty cycle = (TIM4_CCR2/ TIM4_ARR)* 100 = 50% - TIM4 Channel3 duty cycle = (TIM4_CCR3/ TIM4_ARR)* 100 = 50% - TIM4 Channel4 duty cycle = (TIM4_CCR4/ TIM4_ARR)* 100 = 50% - - ==> TIM4_CCRx = TIM4_ARR/2 = 1000 (where x = 1, 2, 3 and 4). - - Note: - SystemCoreClock variable holds HCLK frequency and is defined in system_stm32f4xx.c file. - Each time the core clock (HCLK) changes, user had to call SystemCoreClockUpdate() - function to update SystemCoreClock variable value. Otherwise, any configuration - based on this variable will be incorrect. - ----------------------------------------------------------------------- */ - - - /* Compute the prescaler value */ - PrescalerValue = (uint16_t) ((SystemCoreClock /2) / 2000) - 1; - - /* Time base configuration */ - TIM_TimeBaseStructure.TIM_Period = TIM_ARR; - TIM_TimeBaseStructure.TIM_Prescaler = PrescalerValue; - TIM_TimeBaseStructure.TIM_ClockDivision = 0; - TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure); - - /* Enable TIM4 Preload register on ARR */ - TIM_ARRPreloadConfig(TIM4, ENABLE); - - /* TIM PWM1 Mode configuration: Channel */ - TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1; - TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; - TIM_OCInitStructure.TIM_Pulse = TIM_CCR; - TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High; - - /* Output Compare PWM1 Mode configuration: Channel1 */ - TIM_OC1Init(TIM4, &TIM_OCInitStructure); - TIM_CCxCmd(TIM4, TIM_Channel_1, DISABLE); - - TIM_OC1PreloadConfig(TIM4, TIM_OCPreload_Enable); - - /* Output Compare PWM1 Mode configuration: Channel2 */ - TIM_OC2Init(TIM4, &TIM_OCInitStructure); - TIM_CCxCmd(TIM4, TIM_Channel_2, DISABLE); - - TIM_OC2PreloadConfig(TIM4, TIM_OCPreload_Enable); - - /* Output Compare PWM1 Mode configuration: Channel3 */ - TIM_OC3Init(TIM4, &TIM_OCInitStructure); - TIM_CCxCmd(TIM4, TIM_Channel_3, DISABLE); - - TIM_OC3PreloadConfig(TIM4, TIM_OCPreload_Enable); - - /* Output Compare PWM1 Mode configuration: Channel4 */ - TIM_OC4Init(TIM4, &TIM_OCInitStructure); - TIM_CCxCmd(TIM4, TIM_Channel_4, DISABLE); - - TIM_OC4PreloadConfig(TIM4, TIM_OCPreload_Enable); - - /* TIM4 enable counter */ - TIM_Cmd(TIM4, ENABLE); -} - -/** - * @brief Inserts a delay time. - * @param nTime: specifies the delay time length, in 10 ms. - * @retval None - */ -void Delay(__IO uint32_t nTime) -{ - TimingDelay = nTime; - - while(TimingDelay != 0); -} - -/** - * @brief Decrements the TimingDelay variable. - * @param None - * @retval None - */ -void TimingDelay_Decrement(void) -{ - if (TimingDelay != 0x00) - { - TimingDelay--; - } -} - -/** - * @brief This function handles the test program fail. - * @param None - * @retval None - */ -void Fail_Handler(void) -{ - /* Erase last sector */ - FLASH_EraseSector(FLASH_Sector_11, VoltageRange_3); - /* Write FAIL code at last word in the flash memory */ - FLASH_ProgramWord(TESTRESULT_ADDRESS, ALLTEST_FAIL); - - while(1) - { - /* Toggle Red LED */ - STM_EVAL_LEDToggle(LED5); - Delay(5); - } -} - -/** - * @brief MEMS accelerometre management of the timeout situation. - * @param None. - * @retval None. - */ -uint32_t LIS302DL_TIMEOUT_UserCallback(void) -{ - /* MEMS Accelerometer Timeout error occured during Test program execution */ - if (DemoEnterCondition == 0x00) - { - /* Timeout error occured for SPI TXE/RXNE flags waiting loops.*/ - Fail_Handler(); - } - /* MEMS Accelerometer Timeout error occured during Demo execution */ - else - { - while (1) - { - } - } - return 0; -} - -#ifdef USE_FULL_ASSERT - -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t* file, uint32_t line) -{ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - - /* Infinite loop */ - while (1) - { - } -} -#endif - -/** - * @} - */ - - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/discovery_demo/main.h b/example/stm32f4/Projects/discovery_demo/main.h deleted file mode 100644 index cc19bb4d0..000000000 --- a/example/stm32f4/Projects/discovery_demo/main.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - ****************************************************************************** - * @file main.h - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief Header for main.c module - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4_DISCOVERY_DEMO_H -#define __STM32F4_DISCOVERY_DEMO_H - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4_discovery.h" -#include "stm32f4_discovery_audio_codec.h" -#include "stm32f4_discovery_lis302dl.h" -#include "selftest.h" -#include - - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* TIM2 Autoreload and Capture Compare register values */ -#define TIM_ARR (uint16_t)1999 -#define TIM_CCR (uint16_t)1000 - -/* MEMS Microphone SPI Interface */ -#define SPI_SCK_PIN GPIO_Pin_10 -#define SPI_SCK_GPIO_PORT GPIOB -#define SPI_SCK_GPIO_CLK RCC_AHB1Periph_GPIOB -#define SPI_SCK_SOURCE GPIO_PinSource10 -#define SPI_SCK_AF GPIO_AF_SPI2 - -#define SPI_MOSI_PIN GPIO_Pin_3 -#define SPI_MOSI_GPIO_PORT GPIOC -#define SPI_MOSI_GPIO_CLK RCC_AHB1Periph_GPIOC -#define SPI_MOSI_SOURCE GPIO_PinSource3 -#define SPI_MOSI_AF GPIO_AF_SPI2 - -/* Exported macro ------------------------------------------------------------*/ -#define ABS(x) (x < 0) ? (-x) : x -#define MAX(a,b) (a < b) ? (b) : a -/* Exported functions ------------------------------------------------------- */ -void TimingDelay_Decrement(void); -void Delay(__IO uint32_t nTime); -void Fail_Handler(void); -#endif /* __STM32F4_DISCOVERY_DEMO_H */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/discovery_demo/selftest.c b/example/stm32f4/Projects/discovery_demo/selftest.c deleted file mode 100644 index 7183ffa2c..000000000 --- a/example/stm32f4/Projects/discovery_demo/selftest.c +++ /dev/null @@ -1,808 +0,0 @@ -/** - ****************************************************************************** - * @file selftest.c - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief This file provides the hardware tests - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- */ - -/* Includes ------------------------------------------------------------------*/ -#include "selftest.h" - -//Library config for this project!!!!!!!!!!! -#include "stm32f4xx_conf.h" - - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define MEMS_PASSCONDITION 15 -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Init Structure definition */ -RCC_ClocksTypeDef RCC_Clocks; -ADC_InitTypeDef ADC_InitStructure; -ADC_CommonInitTypeDef ADC_CommonInitStructure; - -__IO uint16_t ConvData1, ConvData2; -__IO uint16_t counter0 = 0, counter1 = 0, Idx = 0; -uint8_t ADC_Channel[2] = {ADC_Channel_2, ADC_Channel_3}; -uint8_t DACTest = 0; -uint8_t GPIO_Pin [2] = {GPIO_Pin_2, GPIO_Pin_3}; - -uint16_t count = 0, count1 = 24, Left_Right = 0; -const int16_t sinebuf[48] = {0, 4276, 8480, 12539, 16383, 19947, 23169, 25995, - 28377, 30272, 31650, 32486, 32767, 32486, 31650, 30272, - 28377, 25995, 23169, 19947, 16383, 12539, 8480, 4276, - 0, -4276, -8480, -12539, -16383, -19947, -23169, -25995, - -28377, -30272, -31650, -32486, -32767, -32486, -31650, -30272, - -28377, -25995, -23169, -19947, -16383, -12539, -8480, -4276 - }; -extern __IO uint32_t TimingDelay; - -extern LIS302DL_InitTypeDef LIS302DL_InitStruct; -extern LIS302DL_FilterConfigTypeDef LIS302DL_FilterStruct; - -extern __IO int8_t X_Offset, Y_Offset, Z_Offset; -extern uint8_t Buffer[6]; -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** - * @brief Test MEMS Hardware. - * The main objectif of this test is to check the hardware connection of the - * MEMS peripheral. - * @param None - * @retval None - */ -void Accelerometer_MEMS_Test(void) -{ - uint8_t temp, memsteststatus = 0x00; - uint8_t xdata, ydata = 0; - - /* MEMS configuration ------------------------------------------------------*/ - /* Set configuration of LIS302DL*/ - LIS302DL_InitStruct.Power_Mode = LIS302DL_LOWPOWERMODE_ACTIVE; - LIS302DL_InitStruct.Output_DataRate = LIS302DL_DATARATE_100; - LIS302DL_InitStruct.Axes_Enable = LIS302DL_X_ENABLE | LIS302DL_Y_ENABLE; - LIS302DL_InitStruct.Full_Scale = LIS302DL_FULLSCALE_2_3; - LIS302DL_InitStruct.Self_Test = LIS302DL_SELFTEST_NORMAL; - LIS302DL_Init(&LIS302DL_InitStruct); - - /* Set configuration of Internal High Pass Filter of LIS302DL*/ - LIS302DL_FilterStruct.HighPassFilter_Data_Selection = LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER; - LIS302DL_FilterStruct.HighPassFilter_CutOff_Frequency = LIS302DL_HIGHPASSFILTER_LEVEL_1; - LIS302DL_FilterStruct.HighPassFilter_Interrupt = LIS302DL_HIGHPASSFILTERINTERRUPT_1_2; - LIS302DL_FilterConfig(&LIS302DL_FilterStruct); - - /* Required delay for the MEMS Accelerometre: Turn-on time = 3/Output data Rate - = 3/100 = 30ms */ - Delay(30); - - /* Read WHO_AM_I register */ - LIS302DL_Read(&temp, LIS302DL_WHO_AM_I_ADDR, 1); - - /* Check device identification register, this register should contains - the device identifier that for LIS302DL is set to 0x3B */ - if (temp != 0x3B) - { - Fail_Handler(); - } - - TimingDelay = 500; - /* Wait until detecting all MEMS direction or timeout */ - while((memsteststatus == 0x00)&&(TimingDelay != 0x00)) - { - LIS302DL_Read(Buffer, LIS302DL_OUT_X_ADDR, 4); - xdata = ABS((int8_t)(Buffer[0])); - ydata = ABS((int8_t)(Buffer[2])); - /* Check test PASS condition */ - if ((xdata > MEMS_PASSCONDITION) || (ydata > MEMS_PASSCONDITION)) - { - /* MEMS Test PASS */ - memsteststatus = 0x01; - } - } - - /* MEMS test status: PASS */ - if(memsteststatus != 0x00) - { - /* Turn Green LED ON: signaling MEMS Test PASS */ - STM_EVAL_LEDOn(LED4); - - /* Waiting User Button is pressed */ - while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_RESET) - {} - - /* Waiting User Button is Released */ - while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_SET) - {} - - /* Turn Green LED OFF: signaling the end of MEMS Test and switching to - the next Sub Test */ - STM_EVAL_LEDOff(LED4); - } - /* MEMS test status: Timeout occurs */ - else - { - Fail_Handler(); - } -} - -/** - * @brief Test USB Hardware. - * The main objectif of this test is to check the hardware connection of the - * Audio and USB peripheral. - * @param None - * @retval None - */ -void USB_Test(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /******************************** USB Test **********************************/ - - /*----------------- Part1: without cables connected ------------------------*/ - - /* GPIOA, GPIOC and GPIOD clock enable */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | \ - RCC_AHB1Periph_GPIOD, ENABLE); - - /* GPIOD Configuration: Pins 5 in output push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /* Turn LED8 ON using PD5 */ - GPIO_ResetBits(GPIOD, GPIO_Pin_5); - - /* GPIOC Configuration: Pin 0 in output push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - /* GPIOA Configuration: Pin 9 in input pull-up */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* Turn LED7 ON using PC0 (5v) */ - GPIO_ResetBits(GPIOC, GPIO_Pin_0); - - /* Waiting delay 10ms */ - Delay(1); - - if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_9) == Bit_RESET) - { - Fail_Handler(); - } - - /* GPIOA Configuration: Pins 10 in output push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* Waiting delay 10ms */ - Delay(1); - - /* Check the ID level without cable connected */ - if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_10) == Bit_RESET) - { - Fail_Handler(); - } - - /* Turn LED7 OFF using PC0 */ - GPIO_SetBits(GPIOC, GPIO_Pin_0); - - /* GPIOA Configuration: Pins 11, 12 in input pull-up */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* GPIOA Configuration: Pin 9 in output push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_ResetBits(GPIOA, GPIO_Pin_9); - - /* Waiting delay 10ms */ - Delay(1); - - /* Check PA11 and PA12 level without cable connected */ - if ((GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_11) == Bit_RESET) || \ - (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_12) == Bit_RESET)) - { - Fail_Handler(); - } - - /* GPIOA Configuration: Pins 12 in input pull-up */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* GPIOA Configuration: Pin 11 in output push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_ResetBits(GPIOA, GPIO_Pin_11); - - /* Waiting delay 10ms */ - Delay(1); - - /* Check PA12 level without cable connected */ - if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_12) == Bit_RESET) - { - Fail_Handler(); - } - - /* GPIOA Configuration: Pins 11 in input pull-up */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* GPIOA Configuration: Pin 12 in output push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_ResetBits(GPIOA, GPIO_Pin_12); - - /* Waiting delay 10ms */ - Delay(1); - - /* Check PA12 level without cable connected */ - if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_11) == Bit_RESET) - { - Fail_Handler(); - } - - /* GPIOA Configuration: Pins 9 in output push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* Turn LED7 ON using PA9 */ - GPIO_SetBits(GPIOA, GPIO_Pin_9); - - /* Turn Green LED ON: signaling Audio USB Test part1 PASS */ - STM_EVAL_LEDOn(LED4); - - /* Waiting User Button is pressed */ - while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_RESET) - {} - - /* Waiting User Button is Released */ - while (STM_EVAL_PBGetState(BUTTON_USER) != Bit_RESET) - {} - - /* Turn Green LED OFF: signaling the end of Audio USB Test part1 and switching to - the part2 */ - STM_EVAL_LEDOff(LED4); - - /* Turn LED7 OFF using PA9 */ - GPIO_ResetBits(GPIOA, GPIO_Pin_9); - - /* Turn LED8 OFF using PD5 */ - GPIO_SetBits(GPIOD, GPIO_Pin_5); - - /*--------------- Part2: with Audio USB cables connected ------------------*/ - - /*********************************** USB Test *******************************/ - /* Check the ID level with cable connected */ - if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_10) != Bit_RESET) - { - Fail_Handler(); - } - - /* GPIOA Configuration: Pins 11, 12 in input pull-down */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* GPIOA Configuration: Pin 9 in output push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_SetBits(GPIOA, GPIO_Pin_9); - - /* Waiting delay 10ms */ - Delay(1); - - /* Check PA11 and PA12 level with cable connected */ - if ((GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_11) == Bit_RESET) || \ - (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_12) == Bit_RESET)) - { - Fail_Handler(); - } - - /* GPIOA Configuration: Pins 9, 12 in input pull-down */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_12; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* GPIOA Configuration: Pin 11 in output push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_SetBits(GPIOA, GPIO_Pin_11); - - /* Waiting delay 10ms */ - Delay(1); - - /* Check PA9 and PA12 level with cable connected */ - if ((GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_9) == Bit_RESET)|| \ - (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_12) == Bit_RESET)) - { - Fail_Handler(); - } - - /* GPIOA Configuration: Pins 9, 11 in input pull-down */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9 | GPIO_Pin_11; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* GPIOA Configuration: Pin 12 in output push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_SetBits(GPIOA, GPIO_Pin_12); - - /* Waiting delay 10ms */ - Delay(1); - - /* Check PA9 and PA12 level with cable connected */ - if ((GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_9) == Bit_RESET)|| \ - (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_11) == Bit_RESET)) - { - Fail_Handler(); - } - - /* GPIOA Configuration: Pins 11, 12 in input pull-down */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* GPIOA Configuration: Pin 9 in output push-pull */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* Turn LED7 OFF using PA9 */ - GPIO_ResetBits(GPIOA, GPIO_Pin_9); -} - -/** - * @brief Test Audio Hardware. - * The main objectif of this test is to check the hardware connection of the - * Audio peripheral. - * @param None - * @retval None - */ -void Audio_Test(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - uint8_t audioteststatus = 0x00; - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC2, ENABLE); - - /* Set the current audio interface: I2S or DAC */ - EVAL_AUDIO_SetAudioInterface(AUDIO_INTERFACE_I2S); - - /* Initialize the Audio codec and all related peripherals (I2S, I2C, IOs...) */ - if (EVAL_AUDIO_Init(OUTPUT_DEVICE_HEADPHONE, 87, I2S_AudioFreq_48k) !=0) - { - Fail_Handler(); - } - /* I2S code to be exectued under the I2S interrupt */ - DACTest = 0; - - /* ADC Common Init */ - ADC_CommonInitStructure.ADC_Mode = ADC_Mode_Independent; - ADC_CommonInitStructure.ADC_Prescaler = ADC_Prescaler_Div8; - ADC_CommonInitStructure.ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; - ADC_CommonInitStructure.ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_20Cycles; - ADC_CommonInit(&ADC_CommonInitStructure); - - /* ADC peripherals Init */ - ADC_StructInit(&ADC_InitStructure); - ADC_InitStructure.ADC_Resolution = ADC_Resolution_8b; - ADC_InitStructure.ADC_ScanConvMode = DISABLE; - ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; - ADC_InitStructure.ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; - ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; - ADC_InitStructure.ADC_NbrOfConversion = 1; - ADC_Init(ADC1, &ADC_InitStructure); - - ADC_Init(ADC2, &ADC_InitStructure); - - /* Configure ADC Channels pin as analog input */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 ; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - counter1 = 0; - counter0 = 0; - audioteststatus = 0; - /* ADCperipheral[PerIdx] Regular Channel Config */ - ADC_RegularChannelConfig(ADC1, ADC_Channel_2, 1, ADC_SampleTime_56Cycles); - /* ADCperipheral[PerIdx] Regular Channel Config */ - ADC_RegularChannelConfig(ADC2, ADC_Channel_3, 1, ADC_SampleTime_56Cycles); - /* Enable ADC1 */ - ADC_Cmd(ADC1, ENABLE); - ADC_Cmd(ADC2, ENABLE); - - TimingDelay = 500; - /* Wait until detecting 500 data*/ - while((audioteststatus == 0)&&(TimingDelay != 0)) - { - ADC_SoftwareStartConv(ADC1); - while(ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC) == RESET); - ConvData1 = ADC_GetConversionValue(ADC1); - - ADC_SoftwareStartConv(ADC2); - while(ADC_GetFlagStatus(ADC2, ADC_FLAG_EOC) == RESET); - ConvData2 = ADC_GetConversionValue(ADC2); - - /* 1.75V equals to 150 */ - if ((ConvData1 > 150) && (ConvData2 < 10) && (counter1 != 500)) - { - counter1 ++; - } - if ((ConvData1 < 10) && (ConvData2 > 150) && (counter0 != 500)) - { - counter0 ++; - } - if((counter1 == 500) && (counter0 == 500)) - { - audioteststatus = 1; - } - } - - /* Disable ADC Peripherals */ - ADC_Cmd(ADC1, DISABLE); - ADC_Cmd(ADC2, DISABLE); - - /* Audio test status: FAIL */ - if(audioteststatus == 0) - { - Fail_Handler(); - } - - EVAL_AUDIO_DeInit(); - EVAL_AUDIO_SetAudioInterface(AUDIO_INTERFACE_DAC); - /* Initialize the Audio codec and all related peripherals (I2S, I2C, IOs...) */ - if (EVAL_AUDIO_Init(OUTPUT_DEVICE_HEADPHONE, 100, I2S_AudioFreq_48k) !=0) - { - Fail_Handler(); - } - - /* DAC code to be exectued under the I2S interrupt */ - DACTest = 1; - counter1 = 0; - counter0 = 0; - audioteststatus = 0; - - /* Enable ADC1 */ - ADC_Cmd(ADC1, ENABLE); - ADC_Cmd(ADC2, ENABLE); - - TimingDelay = 500; - /* Wait until detecting 50 data*/ - while((audioteststatus == 0)&&(TimingDelay != 0)) - { - - ADC_SoftwareStartConv(ADC1); - while(ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC) == RESET); - - ConvData1 = ADC_GetConversionValue(ADC1); - - ADC_SoftwareStartConv(ADC2); - while(ADC_GetFlagStatus(ADC2, ADC_FLAG_EOC) == RESET); - - ConvData2 = ADC_GetConversionValue(ADC2); - - /* 2.0V equals to 170 */ - if ((ConvData1 > 170) && (ConvData2 > 170) &&(counter1 != 500)) - { - counter1 ++; - } - if ((ConvData1 < 10) && (ConvData2 < 10) && (counter0 != 500)) - { - counter0 ++; - } - if((counter1 == 500) && (counter0 == 500)) - { - audioteststatus = 1; - } - } - - /* Audio test status: FAIL */ - if(audioteststatus == 0x00) - { - Fail_Handler(); - } - - /* Turn Green LED ON: signaling Audio USB Test part2 PASS */ - STM_EVAL_LEDOn(LED4); - - /* Waiting User_Button pressed */ - while (STM_EVAL_PBGetState(BUTTON_USER) == Bit_RESET) - {} - - /* Turn Green LED OFF: signaling the end of Audio USB Test part2 */ - STM_EVAL_LEDOff(LED4); -} - -/** - * @brief Test Micophone MEMS Hardware. - * The main objectif of this test is to check the hardware connection of the - * Microphone MEMS peripheral. - * @param None - * @retval None - */ -void Microphone_MEMS_Test(void) -{ - uint16_t data = 0x00; - uint8_t index = 0x00; - I2S_InitTypeDef I2S_InitStructure; - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable the SPI clock */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE); - - /* Enable GPIO clocks */ - RCC_AHB1PeriphClockCmd(SPI_SCK_GPIO_CLK | SPI_MOSI_GPIO_CLK, ENABLE); - - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; - - /* SPI SCK pin configuration */ - GPIO_InitStructure.GPIO_Pin = SPI_SCK_PIN; - GPIO_Init(SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /* Connect SPI pins to AF5 */ - GPIO_PinAFConfig(SPI_SCK_GPIO_PORT, SPI_SCK_SOURCE, SPI_SCK_AF); - - /* SPI MOSI pin configuration */ - GPIO_InitStructure.GPIO_Pin = SPI_MOSI_PIN; - GPIO_Init(SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - GPIO_PinAFConfig(SPI_MOSI_GPIO_PORT, SPI_MOSI_SOURCE, SPI_MOSI_AF); - - /* I2S configuration -------------------------------------------------------*/ - SPI_I2S_DeInit(SPI2); - I2S_InitStructure.I2S_AudioFreq = 64000; - I2S_InitStructure.I2S_Standard = I2S_Standard_MSB; - I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b; - I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low; - I2S_InitStructure.I2S_Mode = I2S_Mode_MasterRx; - I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable; - /* Initialize the I2S peripheral with the structure above */ - I2S_Init(SPI2, &I2S_InitStructure); - - /* Enable the I2S peripheral */ - I2S_Cmd(SPI2, ENABLE); - - /* Waiting until MEMS microphone ready : Wake-up Time */ - Delay(10); - - TimingDelay = 500; - /* Wait until detect the click on the MEMS microphone or TimeOut delay*/ - while((index < 30) && (TimingDelay != 0x00)) - { - /* Waiting RXNE Flag or TimeOut delay */ - while((SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_RXNE) == RESET)&& (TimingDelay != 0x00)) - {} - data = SPI_I2S_ReceiveData(SPI2); - if (data == 0xFFFF) - { - index++; - } - } - - /* MEMS microphone test status: Timeout occurs */ - if(index != 30) - { - Fail_Handler(); - } -} - -/*-------------------------------- - Callbacks implementation: - the callbacks prototypes are defined in the stm324xg_eval_audio_codec.h file - and their implementation should be done in the user code if they are needed. - Below some examples of callback implementations. - --------------------------------------------------------*/ -/** - * @brief Calculates the remaining file size and new position of the pointer. - * @param None - * @retval None - */ -void EVAL_AUDIO_TransferComplete_CallBack(uint32_t pBuffer, uint32_t Size) -{ - /* Calculate the remaining audio data in the file and the new size - for the DMA transfer. If the Audio files size is less than the DMA max - data transfer size, so there is no calculation to be done, just restart - from the beginning of the file ... */ - /* Check if the end of file has been reached */ - -} - -/** - * @brief Manages the DMA Half Transfer complete interrupt. - * @param None - * @retval None - */ -void EVAL_AUDIO_HalfTransfer_CallBack(uint32_t pBuffer, uint32_t Size) -{ -#ifdef AUDIO_MAL_MODE_CIRCULAR - - /* Display message on the LCD screen */ - LCD_DisplayStringLine(Line8, " 1/2 Buffer Reached "); - -#endif /* AUDIO_MAL_MODE_CIRCULAR */ - - /* Generally this interrupt routine is used to load the buffer when - a streaming scheme is used: When first Half buffer is already transferred load - the new data to the first half of buffer while DMA is transferring data from - the second half. And when Transfer complete occurs, load the second half of - the buffer while the DMA is transferring from the first half ... */ - /* - ........... - */ -} -/** - * @brief Get next data sample callback - * @param None - * @retval Next data sample to be sent - */ -uint16_t EVAL_AUDIO_GetSampleCallBack(void) -{ - uint16_t data = 0; - - if (DACTest == 0) - { - if (Left_Right==0) - { - /* Get the next sample to be sent */ - data = sinebuf[count++]; - - if (count == 48) - { - count = 0x00; - } - Left_Right = 1; - } - else - { - /* Get the next sample to be sent */ - data = sinebuf[count1++]; - - if (count1 == 48) - { - count1 = 0x00; - } - Left_Right = 0; - } - } - else - { - /* Get the next sample to be sent */ - data = 32768 + sinebuf[count++]; - - if (count == 48) - { - count = 0x00; - } - } - return data; -} - - -/** - * @brief Manages the DMA FIFO error interrupt. - * @param None - * @retval None - */ -void EVAL_AUDIO_Error_CallBack(void* pData) -{ - /* Stop the program with an infinite loop */ - while (1) - {} - - /* could also generate a system reset to recover from the error */ - /* .... */ -} - -#ifndef USE_DEFAULT_TIMEOUT_CALLBACK -/** - * @brief Basic management of the timeout situation. - * @param None. - * @retval None. - */ -uint32_t Codec_TIMEOUT_UserCallback(void) -{ - /* Block communication and all processes */ - while (1) - { - } -} -#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */ -/*----------------------------------------------------------------------------*/ - - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/discovery_demo/selftest.h b/example/stm32f4/Projects/discovery_demo/selftest.h deleted file mode 100644 index feef3de5c..000000000 --- a/example/stm32f4/Projects/discovery_demo/selftest.h +++ /dev/null @@ -1,41 +0,0 @@ -/** - ****************************************************************************** - * @file selftest.h - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief Header for selftest.c module - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __SELFTEST_H -#define __SELFTEST_H - -/* Includes ------------------------------------------------------------------*/ -#include -#include "main.h" -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void Audio_Test(void); -void Accelerometer_MEMS_Test(void); -void USB_Test(void); -void Microphone_MEMS_Test(void); - -#endif /* __SELFTEST_H */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/discovery_demo/startup_stm32f4xx.s b/example/stm32f4/Projects/discovery_demo/startup_stm32f4xx.s deleted file mode 100644 index ce5360f3c..000000000 --- a/example/stm32f4/Projects/discovery_demo/startup_stm32f4xx.s +++ /dev/null @@ -1,509 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f4xx.s - * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 - * @brief STM32F4xx Devices vector table for RIDE7 toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system and the external SRAM mounted on - * STM324xG-EVAL board to be used as data memory (optional, - * to be enabled by user) - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FSMC_IRQHandler /* FSMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word CRYP_IRQHandler /* CRYP crypto */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - .word FPU_IRQHandler /* FPU */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak CRYP_IRQHandler - .thumb_set CRYP_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/discovery_demo/stm32_flash.ld b/example/stm32f4/Projects/discovery_demo/stm32_flash.ld deleted file mode 100644 index ee842a775..000000000 --- a/example/stm32f4/Projects/discovery_demo/stm32_flash.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* -***************************************************************************** -** -** File : stm32_flash.ld -** -** Abstract : Linker script for STM32F207IG Device with -** 1024KByte FLASH, 112KByte RAM -** -** Set heap size, stack size and stack location according -** to application requirements. -** -** Set memory bank area and size if external memory is used. -** -** Target : STMicroelectronics STM32 -** -** Environment : Atollic TrueSTUDIO(R) -** -** Distribution: The file is distributed as is, without any warranty -** of any kind. -** -** (c)Copyright Atollic AB. -** You may use this file as-is or modify it according to the needs of your -** project. Distribution of this file (unmodified or modified) is not -** permitted. Atollic AB permit registered Atollic TrueSTUDIO(R) users the -** rights to distribute the assembled, compiled & linked contents of this -** file as part of an application binary file, provided that it is built -** using the Atollic TrueSTUDIO(R) toolchain. -** -***************************************************************************** -*/ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = 0x2001c000; /* end of 112K RAM */ - -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Specify the memory areas */ -MEMORY -{ - FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 112K - MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K -} - -/* Define output sections */ -SECTIONS -{ - /* The startup code goes first into FLASH */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data goes into FLASH */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - - .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH - .ARM : { - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - } >FLASH - - .preinit_array : - { - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - } >FLASH - .init_array : - { - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - } >FLASH - .fini_array : - { - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(.fini_array*)) - KEEP (*(SORT(.fini_array.*))) - PROVIDE_HIDDEN (__fini_array_end = .); - } >FLASH - - /* used by the startup to initialize data */ - _sidata = .; - - /* Initialized data sections goes into RAM, load LMA copy after code */ - .data : AT ( _sidata ) - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - } >RAM - - /* Uninitialized data section */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough RAM left */ - ._user_heap_stack : - { - . = ALIGN(4); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(4); - } >RAM - - /* MEMORY_bank1 section, code must be located here explicitly */ - /* Example: extern int foo(void) __attribute__ ((section (".mb1text"))); */ - .memory_b1_text : - { - *(.mb1text) /* .mb1text sections (code) */ - *(.mb1text*) /* .mb1text* sections (code) */ - *(.mb1rodata) /* read-only data (constants) */ - *(.mb1rodata*) - } >MEMORY_B1 - - /* Remove information from the standard libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/example/stm32f4/Projects/discovery_demo/stm32f4xx_conf.h b/example/stm32f4/Projects/discovery_demo/stm32f4xx_conf.h deleted file mode 100644 index 74447a8f8..000000000 --- a/example/stm32f4/Projects/discovery_demo/stm32f4xx_conf.h +++ /dev/null @@ -1,94 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_conf.h - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief Library configuration file. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_CONF_H -#define __STM32F4xx_CONF_H - -#if defined (HSE_VALUE) -/* Redefine the HSE value; it's equal to 8 MHz on the STM32F4-DISCOVERY Kit */ - #undef HSE_VALUE - #define HSE_VALUE ((uint32_t)8000000) -#endif /* HSE_VALUE */ - -/* Includes ------------------------------------------------------------------*/ -/* Uncomment the line below to enable peripheral header file inclusion */ -#include "stm32f4xx_adc.h" -#include "stm32f4xx_can.h" -#include "stm32f4xx_crc.h" -#include "stm32f4xx_cryp.h" -#include "stm32f4xx_dac.h" -#include "stm32f4xx_dbgmcu.h" -#include "stm32f4xx_dcmi.h" -#include "stm32f4xx_dma.h" -#include "stm32f4xx_exti.h" -#include "stm32f4xx_flash.h" -#include "stm32f4xx_fsmc.h" -#include "stm32f4xx_hash.h" -#include "stm32f4xx_gpio.h" -#include "stm32f4xx_i2c.h" -#include "stm32f4xx_iwdg.h" -#include "stm32f4xx_pwr.h" -#include "stm32f4xx_rcc.h" -#include "stm32f4xx_rng.h" -#include "stm32f4xx_rtc.h" -#include "stm32f4xx_sdio.h" -#include "stm32f4xx_spi.h" -#include "stm32f4xx_syscfg.h" -#include "stm32f4xx_tim.h" -#include "stm32f4xx_usart.h" -#include "stm32f4xx_wwdg.h" -#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* If an external clock source is used, then the value of the following define - should be set to the value of the external clock source, else, if no external - clock is used, keep this define commented */ -/*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */ - - -/* Uncomment the line below to expanse the "assert_param" macro in the - Standard Peripheral Library drivers code */ -/* #define USE_FULL_ASSERT 1 */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT - -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - -#endif /* __STM32F4xx_CONF_H */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/discovery_demo/stm32f4xx_it.c b/example/stm32f4/Projects/discovery_demo/stm32f4xx_it.c deleted file mode 100644 index cee2c2492..000000000 --- a/example/stm32f4/Projects/discovery_demo/stm32f4xx_it.c +++ /dev/null @@ -1,320 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_it.c - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief Main Interrupt Service Routines. - * This file provides all exceptions handler and peripherals interrupt - * service routine. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_it.h" -#include "main.h" -#include "usb_core.h" -#include "usbd_core.h" -#include "stm32f4_discovery.h" -#include "usbd_hid_core.h" - -//Library config for this project!!!!!!!!!!! -#include "stm32f4xx_conf.h" - - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define CURSOR_STEP 7 - -extern uint8_t Buffer[6]; -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -extern __IO uint8_t DemoEnterCondition; -uint8_t Counter = 0x00; -extern int8_t X_Offset; -extern int8_t Y_Offset; -extern __IO uint8_t UserButtonPressed; -__IO uint8_t TempAcceleration = 0; -/* Private function prototypes -----------------------------------------------*/ -extern USB_OTG_CORE_HANDLE USB_OTG_dev; -static uint8_t *USBD_HID_GetPos (void); -extern uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); - -/******************************************************************************/ -/* Cortex-M3 Processor Exceptions Handlers */ -/******************************************************************************/ - -/** - * @brief This function handles NMI exception. - * @param None - * @retval None - */ -void NMI_Handler(void) -{ -} - -/** - * @brief This function handles Hard Fault exception. - * @param None - * @retval None - */ -void HardFault_Handler(void) -{ - /* Go to infinite loop when Hard Fault exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles Memory Manage exception. - * @param None - * @retval None - */ -void MemManage_Handler(void) -{ - /* Go to infinite loop when Memory Manage exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles Bus Fault exception. - * @param None - * @retval None - */ -void BusFault_Handler(void) -{ - /* Go to infinite loop when Bus Fault exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles Usage Fault exception. - * @param None - * @retval None - */ -void UsageFault_Handler(void) -{ - /* Go to infinite loop when Usage Fault exception occurs */ - while (1) - { - } -} - -/** - * @brief This function handles SVCall exception. - * @param None - * @retval None - */ -void SVC_Handler(void) -{ -} - -/** - * @brief This function handles Debug Monitor exception. - * @param None - * @retval None - */ -void DebugMon_Handler(void) -{ -} - -/** - * @brief This function handles PendSVC exception. - * @param None - * @retval None - */ -void PendSV_Handler(void) -{ -} - -/** - * @brief This function handles SysTick Handler. - * @param None - * @retval None - */ -void SysTick_Handler(void) -{ - uint8_t *buf; - uint8_t temp1, temp2 = 0x00; - - if (DemoEnterCondition == 0x00) - { - TimingDelay_Decrement(); - } - else - { - buf = USBD_HID_GetPos(); - if((buf[1] != 0) ||(buf[2] != 0)) - { - USBD_HID_SendReport (&USB_OTG_dev, - buf, - 4); - } - Counter ++; - if (Counter == 10) - { - Buffer[0] = 0; - Buffer[2] = 0; - /* Disable All TIM4 Capture Compare Channels */ - TIM_CCxCmd(TIM4, TIM_Channel_1, DISABLE); - TIM_CCxCmd(TIM4, TIM_Channel_2, DISABLE); - TIM_CCxCmd(TIM4, TIM_Channel_3, DISABLE); - TIM_CCxCmd(TIM4, TIM_Channel_4, DISABLE); - - LIS302DL_Read(Buffer, LIS302DL_OUT_X_ADDR, 6); - /* Remove the offsets values from data */ - Buffer[0] -= X_Offset; - Buffer[2] -= Y_Offset; - /* Update autoreload and capture compare registers value*/ - temp1 = ABS((int8_t)(Buffer[0])); - temp2 = ABS((int8_t)(Buffer[2])); - TempAcceleration = MAX(temp1, temp2); - - if(TempAcceleration != 0) - { - if ((int8_t)Buffer[0] < -2) - { - /* Enable TIM4 Capture Compare Channel 4 */ - TIM_CCxCmd(TIM4, TIM_Channel_4, ENABLE); - /* Sets the TIM4 Capture Compare4 Register value */ - TIM_SetCompare4(TIM4, TIM_CCR/TempAcceleration); - } - if ((int8_t)Buffer[0] > 2) - { - /* Enable TIM4 Capture Compare Channel 2 */ - TIM_CCxCmd(TIM4, TIM_Channel_2, ENABLE); - /* Sets the TIM4 Capture Compare2 Register value */ - TIM_SetCompare2(TIM4, TIM_CCR/TempAcceleration); - } - if ((int8_t)Buffer[2] > 2) - { - /* Enable TIM4 Capture Compare Channel 1 */ - TIM_CCxCmd(TIM4, TIM_Channel_1, ENABLE); - /* Sets the TIM4 Capture Compare1 Register value */ - TIM_SetCompare1(TIM4, TIM_CCR/TempAcceleration); - } - if ((int8_t)Buffer[2] < -2) - { - /* Enable TIM4 Capture Compare Channel 3 */ - TIM_CCxCmd(TIM4, TIM_Channel_3, ENABLE); - /* Sets the TIM4 Capture Compare3 Register value */ - TIM_SetCompare3(TIM4, TIM_CCR/TempAcceleration); - } - /* Time base configuration */ - TIM_SetAutoreload(TIM4, TIM_ARR/TempAcceleration); - } - Counter = 0x00; - } - } - -} - -/******************************************************************************/ -/* STM32Fxxx Peripherals Interrupt Handlers */ -/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ -/* available peripheral interrupt handler's name please refer to the startup */ -/* file (startup_stm32fxxx.s). */ -/******************************************************************************/ - -/** - * @brief This function handles PPP interrupt request. - * @param None - * @retval None - */ -/*void PPP_IRQHandler(void) -{ -}*/ - -/** - * @brief This function handles EXTI0_IRQ Handler. - * @param None - * @retval None - */ -void EXTI0_IRQHandler(void) -{ - UserButtonPressed = 0x01; - - /* Clear the EXTI line pending bit */ - EXTI_ClearITPendingBit(USER_BUTTON_EXTI_LINE); -} - -/** - * @brief This function handles EXTI15_10_IRQ Handler. - * @param None - * @retval None - */ -void OTG_FS_WKUP_IRQHandler(void) -{ - if(USB_OTG_dev.cfg.low_power) - { - /* Reset SLEEPDEEP and SLEEPONEXIT bits */ - SCB->SCR &= (uint32_t)~((uint32_t)(SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk)); - - /* After wake-up from sleep mode, reconfigure the system clock */ - SystemInit(); - USB_OTG_UngateClock(&USB_OTG_dev); - } - EXTI_ClearITPendingBit(EXTI_Line18); -} - -/** - * @brief This function handles OTG_HS Handler. - * @param None - * @retval None - */ -void OTG_FS_IRQHandler(void) -{ - USBD_OTG_ISR_Handler (&USB_OTG_dev); -} - -/** -* @brief USBD_HID_GetPos -* @param None -* @retval Pointer to report -*/ -static uint8_t *USBD_HID_GetPos (void) -{ - static uint8_t HID_Buffer[4] = {0}; - - HID_Buffer[1] = 0; - HID_Buffer[2] = 0; - /* LEFT Direction */ - if(((int8_t)Buffer[2]) < -2) - { - HID_Buffer[1] += CURSOR_STEP; - } - /* RIGHT Direction */ - if(((int8_t)Buffer[2]) > 2) - { - HID_Buffer[1] -= CURSOR_STEP; - } - /* UP Direction */ - if(((int8_t)Buffer[0]) < -2) - { - HID_Buffer[2] += CURSOR_STEP; - } - /* DOWN Direction */ - if(((int8_t)Buffer[0]) > 2) - { - HID_Buffer[2] -= CURSOR_STEP; - } - - return HID_Buffer; -} -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/discovery_demo/stm32f4xx_it.h b/example/stm32f4/Projects/discovery_demo/stm32f4xx_it.h deleted file mode 100644 index 4ae766cf4..000000000 --- a/example/stm32f4/Projects/discovery_demo/stm32f4xx_it.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_it.h - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_IT_H -#define __STM32F4xx_IT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -void NMI_Handler(void); -void HardFault_Handler(void); -void MemManage_Handler(void); -void BusFault_Handler(void); -void UsageFault_Handler(void); -void SVC_Handler(void); -void DebugMon_Handler(void); -void PendSV_Handler(void); -void SysTick_Handler(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_IT_H */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/discovery_demo/system_stm32f4xx.c b/example/stm32f4/Projects/discovery_demo/system_stm32f4xx.c deleted file mode 100644 index fbb195cc4..000000000 --- a/example/stm32f4/Projects/discovery_demo/system_stm32f4xx.c +++ /dev/null @@ -1,566 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f4xx.c - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32F4xx devices, - * and is generated by the clock configuration tool - * stm32f4xx_Clock_Configuration_V1.0.0.xls - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f4xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 8 MHz, refer to "HSE_VALUE" define - * in "stm32f4xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - *============================================================================= - * Supported STM32F4xx device revision | Rev A - *----------------------------------------------------------------------------- - * System Clock source | PLL (HSE) - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 168000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 168000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 4 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 2 - *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | 8000000 - *----------------------------------------------------------------------------- - * PLL_M | 8 - *----------------------------------------------------------------------------- - * PLL_N | 336 - *----------------------------------------------------------------------------- - * PLL_P | 2 - *----------------------------------------------------------------------------- - * PLL_Q | 7 - *----------------------------------------------------------------------------- - * PLLI2S_N | 192 - *----------------------------------------------------------------------------- - * PLLI2S_R | 5 - *----------------------------------------------------------------------------- - * I2S input clock(Hz) | 38400000 - *----------------------------------------------------------------------------- - * VDD(V) | 3.3 - *----------------------------------------------------------------------------- - * High Performance mode | Enabled - *----------------------------------------------------------------------------- - * Flash Latency(WS) | 5 - *----------------------------------------------------------------------------- - * Prefetch Buffer | OFF - *----------------------------------------------------------------------------- - * Instruction cache | ON - *----------------------------------------------------------------------------- - * Data cache | ON - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Enabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** @addtogroup STM32F4xx_System_Private_Includes - * @{ - */ - -#include "stm32f4xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Defines - * @{ - */ - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM324xG_EVAL board as data memory */ -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ -#define PLL_M 8 -#define PLL_N 336 - -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 2 - -/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ -#define PLL_Q 7 - -/* PLLI2S_VCO = (HSE_VALUE Or HSI_VALUE / PLL_M) * PLLI2S_N - I2SCLK = PLLI2S_VCO / PLLI2S_R */ -#define PLLI2S_N 192 -#define PLLI2S_R 5 - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Variables - * @{ - */ - - uint32_t SystemCoreClock = 168000000; - - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable high performance mode, System frequency up to 168 MHz */ - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - PWR->CR |= PWR_CR_PMODE; - - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till the main PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS; - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } - -/******************************************************************************/ -/* I2S clock configuration */ -/******************************************************************************/ - /* PLLI2S clock used as I2S clock source */ - RCC->CFGR &= ~RCC_CFGR_I2SSRC; - - /* Configure PLLI2S */ - RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28); - - /* Enable PLLI2S */ - RCC->CR |= ((uint32_t)RCC_CR_PLLI2SON); - - /* Wait till PLLI2S is ready */ - while((RCC->CR & RCC_CR_PLLI2SRDY) == 0) - { - } -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f4xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f4xx.s before jump to main. - * This function configures the external SRAM mounted on STM324xG_EVAL board - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+------------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+------------------+ - | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | - | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | - | PD4 <-> FSMC_NOE | PE3 <-> FSMC_A19 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | - | PD5 <-> FSMC_NWE | PE4 <-> FSMC_A20 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | - | PD8 <-> FSMC_D13 | PE7 <-> FSMC_D4 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | - | PD9 <-> FSMC_D14 | PE8 <-> FSMC_D5 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | - | PD10 <-> FSMC_D15 | PE9 <-> FSMC_D6 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | - | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7 | PF13 <-> FSMC_A7 |------------------+ - | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8 | PF14 <-> FSMC_A8 | - | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9 | PF15 <-> FSMC_A9 | - | PD14 <-> FSMC_D0 | PE13 <-> FSMC_D10 |------------------+ - | PD15 <-> FSMC_D1 | PE14 <-> FSMC_D11 | - | | PE15 <-> FSMC_D12 | - +-------------------+--------------------+ -*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR = 0x00000078; - - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00cc00cc; - GPIOD->AFR[1] = 0xcc0ccccc; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xaaaa0a0a; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xffff0f0f; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xc00cc0cc; - GPIOE->AFR[1] = 0xcccccccc; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xaaaa828a; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xffffc3cf; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00cccccc; - GPIOF->AFR[1] = 0xcccc0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xaa000aaa; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xff000fff; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00cccccc; - GPIOG->AFR[1] = 0x000000c0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00080aaa; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000c0fff; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FSMC Configuration ------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHB3ENR = 0x00000001; - - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001015; - FSMC_Bank1->BTCR[3] = 0x00010603;//0x00010400; - FSMC_Bank1E->BWTR[2] = 0x0fffffff; -/* - Bank1_SRAM2 is configured as follow: - - p.FSMC_AddressSetupTime = 3;//0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 6;//4; - p.FSMC_BusTurnAroundDuration = 1; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; -*/ - -} -#endif /* DATA_IN_ExtSRAM */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/Projects/discovery_demo/usb_bsp.c b/example/stm32f4/Projects/discovery_demo/usb_bsp.c deleted file mode 100644 index 6861d65b4..000000000 --- a/example/stm32f4/Projects/discovery_demo/usb_bsp.c +++ /dev/null @@ -1,382 +0,0 @@ -/** - ****************************************************************************** - * @file usb_bsp.c - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief This file is responsible to offer board support package and is - * configurable by user. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_bsp.h" -#include "usbd_conf.h" -#include "stm32f4_discovery.h" - -//Library config for this project!!!!!!!!!!! -#include "stm32f4xx_conf.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY -* @{ -*/ - -/** @defgroup USB_BSP -* @brief This file is responsible to offer board support package -* @{ -*/ - -/** @defgroup USB_BSP_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_BSP_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - - - -/** @defgroup USB_BSP_Private_Macros -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USBH_BSP_Private_Variables -* @{ -*/ - -/** -* @} -*/ - -/** @defgroup USBH_BSP_Private_FunctionPrototypes -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USB_BSP_Private_Functions -* @{ -*/ - - -/** -* @brief USB_OTG_BSP_Init -* Initilizes BSP configurations -* @param None -* @retval None -*/ - -void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev) -{ - GPIO_InitTypeDef GPIO_InitStructure; - -#ifndef USE_ULPI_PHY -#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT - EXTI_InitTypeDef EXTI_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; -#endif -#endif - - - #ifdef USE_USB_OTG_FS - - RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOA , ENABLE); - - /* Configure SOF VBUS ID DM DP Pins */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | - GPIO_Pin_9 | - GPIO_Pin_11 | - GPIO_Pin_12; - - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - GPIO_PinAFConfig(GPIOA,GPIO_PinSource8,GPIO_AF_OTG1_FS) ; - GPIO_PinAFConfig(GPIOA,GPIO_PinSource9,GPIO_AF_OTG1_FS) ; - GPIO_PinAFConfig(GPIOA,GPIO_PinSource11,GPIO_AF_OTG1_FS) ; - GPIO_PinAFConfig(GPIOA,GPIO_PinSource12,GPIO_AF_OTG1_FS) ; - - /* this for ID line debug */ - - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP ; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_Init(GPIOA, &GPIO_InitStructure); - GPIO_PinAFConfig(GPIOA,GPIO_PinSource10,GPIO_AF_OTG1_FS) ; - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_OTG_FS, ENABLE) ; - #else // USE_USB_OTG_HS - - #ifdef USE_ULPI_PHY // ULPI - RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | - RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOH | - RCC_AHB1Periph_GPIOI, ENABLE); - - - GPIO_PinAFConfig(GPIOA,GPIO_PinSource3, GPIO_AF_OTG2_HS) ; // D0 - GPIO_PinAFConfig(GPIOA,GPIO_PinSource5, GPIO_AF_OTG2_HS) ; // CLK - GPIO_PinAFConfig(GPIOB,GPIO_PinSource0, GPIO_AF_OTG2_HS) ; // D1 - GPIO_PinAFConfig(GPIOB,GPIO_PinSource1, GPIO_AF_OTG2_HS) ; // D2 - GPIO_PinAFConfig(GPIOB,GPIO_PinSource5, GPIO_AF_OTG2_HS) ; // D7 - GPIO_PinAFConfig(GPIOB,GPIO_PinSource10,GPIO_AF_OTG2_HS) ; // D3 - GPIO_PinAFConfig(GPIOB,GPIO_PinSource11,GPIO_AF_OTG2_HS) ; // D4 - GPIO_PinAFConfig(GPIOB,GPIO_PinSource12,GPIO_AF_OTG2_HS) ; // D5 - GPIO_PinAFConfig(GPIOB,GPIO_PinSource13,GPIO_AF_OTG2_HS) ; // D6 - GPIO_PinAFConfig(GPIOH,GPIO_PinSource4, GPIO_AF_OTG2_HS) ; // NXT - GPIO_PinAFConfig(GPIOI,GPIO_PinSource11,GPIO_AF_OTG2_HS) ; // DIR - GPIO_PinAFConfig(GPIOC,GPIO_PinSource0, GPIO_AF_OTG2_HS) ; // STP - - // CLK - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 ; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - // D0 - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 ; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - - - // D1 D2 D3 D4 D5 D6 D7 - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | - GPIO_Pin_5 | GPIO_Pin_10 | - GPIO_Pin_11| GPIO_Pin_12 | - GPIO_Pin_13 ; - - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL ; - GPIO_Init(GPIOB, &GPIO_InitStructure); - - - // STP - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 ; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - //NXT - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_Init(GPIOH, &GPIO_InitStructure); - - - //DIR - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 ; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_Init(GPIOI, &GPIO_InitStructure); - - - RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_OTG_HS | - RCC_AHB1Periph_OTG_HS_ULPI, ENABLE) ; - - #else - #ifdef USE_I2C_PHY - RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_GPIOB , ENABLE); - /* Configure RESET INTN SCL SDA (Phy/I2C) Pins */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | - GPIO_Pin_1 | - GPIO_Pin_10 | - GPIO_Pin_11; - - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_Init(GPIOB, &GPIO_InitStructure); - - GPIO_PinAFConfig(GPIOB,GPIO_PinSource0,GPIO_AF_OTG2_FS) ; - GPIO_PinAFConfig(GPIOB,GPIO_PinSource1,GPIO_AF_OTG2_FS) ; - GPIO_PinAFConfig(GPIOB,GPIO_PinSource10,GPIO_AF_OTG2_FS) ; - GPIO_PinAFConfig(GPIOB,GPIO_PinSource11,GPIO_AF_OTG2_FS); - RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_OTG_HS, ENABLE) ; - - #else - - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB , ENABLE); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12 | - GPIO_Pin_13 | - GPIO_Pin_14 | - GPIO_Pin_15; - - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_Init(GPIOB, &GPIO_InitStructure); - - GPIO_PinAFConfig(GPIOB,GPIO_PinSource12, GPIO_AF_OTG2_FS) ; - GPIO_PinAFConfig(GPIOB,GPIO_PinSource13,GPIO_AF_OTG2_FS) ; - GPIO_PinAFConfig(GPIOB,GPIO_PinSource14,GPIO_AF_OTG2_FS) ; - GPIO_PinAFConfig(GPIOB,GPIO_PinSource15,GPIO_AF_OTG2_FS) ; - RCC_AHB1PeriphClockCmd( RCC_AHB1Periph_OTG_HS, ENABLE) ; - #endif - #endif // USE_ULPI_PHY - - #endif //USB_OTG_HS - - - /* enable the PWR clock */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - - /* Configure the Key button in EXTI mode */ - STM_EVAL_PBInit(BUTTON_USER, BUTTON_MODE_EXTI); - -#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT - EXTI_ClearITPendingBit(EXTI_Line18); - - EXTI_InitStructure.EXTI_Line = EXTI_Line18; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - - EXTI_ClearITPendingBit(EXTI_Line18); - - NVIC_InitStructure.NVIC_IRQChannel = OTG_FS_WKUP_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - - EXTI_ClearITPendingBit(EXTI_Line18); -#endif - -#ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT - EXTI_ClearITPendingBit(EXTI_Line20); - - EXTI_InitStructure.EXTI_Line = EXTI_Line20; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - - EXTI_ClearITPendingBit(EXTI_Line20); - - NVIC_InitStructure.NVIC_IRQChannel = OTG_HS_WKUP_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - - EXTI_ClearITPendingBit(EXTI_Line20); -#endif - - EXTI_ClearITPendingBit(USER_BUTTON_EXTI_LINE); -} -/** -* @brief USB_OTG_BSP_EnableInterrupt -* Enabele USB Global interrupt -* @param None -* @retval None -*/ -void USB_OTG_BSP_EnableInterrupt(USB_OTG_CORE_HANDLE *pdev) -{ - NVIC_InitTypeDef NVIC_InitStructure; - - NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); -#ifdef USE_USB_OTG_HS - NVIC_InitStructure.NVIC_IRQChannel = OTG_HS_IRQn; -#else - NVIC_InitStructure.NVIC_IRQChannel = OTG_FS_IRQn; -#endif - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); - NVIC_InitStructure.NVIC_IRQChannel = OTG_HS_EP1_OUT_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 2; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - - NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); - NVIC_InitStructure.NVIC_IRQChannel = OTG_HS_EP1_IN_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); -#endif -} -/** -* @brief USB_OTG_BSP_uDelay -* This function provides delay time in micro sec -* @param usec : Value of delay required in micro sec -* @retval None -*/ -void USB_OTG_BSP_uDelay (const uint32_t usec) -{ - uint32_t count = 0; - const uint32_t utime = (120 * usec / 7); - do - { - if ( ++count > utime ) - { - return ; - } - } - while (1); -} - - -/** -* @brief USB_OTG_BSP_mDelay -* This function provides delay time in milli sec -* @param msec : Value of delay required in milli sec -* @retval None -*/ -void USB_OTG_BSP_mDelay (const uint32_t msec) -{ - USB_OTG_BSP_uDelay(msec * 1000); -} -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/discovery_demo/usb_conf.h b/example/stm32f4/Projects/discovery_demo/usb_conf.h deleted file mode 100644 index eeb2f79de..000000000 --- a/example/stm32f4/Projects/discovery_demo/usb_conf.h +++ /dev/null @@ -1,252 +0,0 @@ -/** - ****************************************************************************** - * @file usb_conf.h - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief General low level driver configuration - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_CONF__H__ -#define __USB_CONF__H__ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_CONF - * @brief USB low level driver configuration file - * @{ - */ - -/** @defgroup USB_CONF_Exported_Defines - * @{ - */ - -/* USB Core and PHY interface configuration. - Tip: To avoid modifying these defines each time you need to change the USB - configuration, you can declare the needed define in your toolchain - compiler preprocessor. - */ -#ifndef USE_USB_OTG_FS - //#define USE_USB_OTG_FS -#endif /* USE_USB_OTG_FS */ - -#ifdef USE_USB_OTG_FS - #define USB_OTG_FS_CORE -#endif - -/******************************************************************************* -* FIFO Size Configuration in Device mode -* -* (i) Receive data FIFO size = RAM for setup packets + -* OUT endpoint control information + -* data OUT packets + miscellaneous -* Space = ONE 32-bits words -* --> RAM for setup packets = 10 spaces -* (n is the nbr of CTRL EPs the device core supports) -* --> OUT EP CTRL info = 1 space -* (one space for status information written to the FIFO along with each -* received packet) -* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces -* (MINIMUM to receive packets) -* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces -* (if high-bandwidth EP is enabled or multiple isochronous EPs) -* --> miscellaneous = 1 space per OUT EP -* (one space for transfer complete status information also pushed to the -* FIFO with each endpoint's last packet) -* -* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for -* that particular IN EP. More space allocated in the IN EP Tx FIFO results -* in a better performance on the USB and can hide latencies on the AHB. -* -* (iii) TXn min size = 16 words. (n : Transmit FIFO index) -* (iv) When a TxFIFO is not used, the Configuration should be as follows: -* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) -* --> Txm can use the space allocated for Txn. -* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) -* --> Txn should be configured with the minimum space of 16 words -* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top -* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. -*******************************************************************************/ - - - -/****************** USB OTG FS CONFIGURATION **********************************/ -#ifdef USB_OTG_FS_CORE - #define RX_FIFO_FS_SIZE 128 - #define TX0_FIFO_FS_SIZE 64 - #define TX1_FIFO_FS_SIZE 128 - #define TX2_FIFO_FS_SIZE 0 - #define TX3_FIFO_FS_SIZE 0 - - //#define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT - //#define USB_OTG_FS_SOF_OUTPUT_ENABLED -#endif - -/****************** USB OTG MODE CONFIGURATION ********************************/ - -//#define USE_HOST_MODE -#define USE_DEVICE_MODE -//#define USE_OTG_MODE - - -#ifndef USB_OTG_FS_CORE - #ifndef USB_OTG_HS_CORE - #error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined" - #endif -#endif - - -#ifndef USE_DEVICE_MODE - #ifndef USE_HOST_MODE - #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" - #endif -#endif - -#ifndef USE_USB_OTG_HS - #ifndef USE_USB_OTG_FS - #error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined" - #endif -#else //USE_USB_OTG_HS - #ifndef USE_ULPI_PHY - #ifndef USE_EMBEDDED_PHY - #ifndef USE_I2C_PHY - #error "USE_ULPI_PHY or USE_EMBEDDED_PHY or USE_I2C_PHY should be defined" - #endif - #endif - #endif -#endif - -/****************** C Compilers dependant keywords ****************************/ -/* In HS mode and when the DMA is used, all variables and data structures dealing - with the DMA during the transaction process should be 4-bytes aligned */ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined (__GNUC__) /* GNU Compiler */ - #define __ALIGN_END __attribute__ ((aligned (4))) - #define __ALIGN_BEGIN - #else - #define __ALIGN_END - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #elif defined (__TASKING__) /* TASKING Compiler */ - #define __ALIGN_BEGIN __align(4) - #endif /* __CC_ARM */ - #endif /* __GNUC__ */ -#else - #define __ALIGN_BEGIN - #define __ALIGN_END -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -/* __packed keyword used to decrease the data type alignment to 1-byte */ -#if defined (__CC_ARM) /* ARM Compiler */ - #define __packed __packed -#elif defined (__ICCARM__) /* IAR Compiler */ - #define __packed __packed -#elif defined ( __GNUC__ ) /* GNU Compiler */ - #define __packed __attribute__ ((__packed__)) -#elif defined (__TASKING__) /* TASKING Compiler */ - #define __packed __unaligned -#endif /* __CC_ARM */ - -/****************** C Compilers dependant keywords ****************************/ -/* In HS mode and when the DMA is used, all variables and data structures dealing - with the DMA during the transaction process should be 4-bytes aligned */ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined (__GNUC__) /* GNU Compiler */ - #define __ALIGN_END __attribute__ ((aligned (4))) - #define __ALIGN_BEGIN - #else - #define __ALIGN_END - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #elif defined (__TASKING__) /* TASKING Compiler */ - #define __ALIGN_BEGIN __align(4) - #endif /* __CC_ARM */ - #endif /* __GNUC__ */ -#else - #define __ALIGN_BEGIN - #define __ALIGN_END -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -/* __packed keyword used to decrease the data type alignment to 1-byte */ -#if defined (__CC_ARM) /* ARM Compiler */ - #define __packed __packed -#elif defined (__ICCARM__) /* IAR Compiler */ - #define __packed __packed -#elif defined ( __GNUC__ ) /* GNU Compiler */ - #define __packed __attribute__ ((__packed__)) -#elif defined (__TASKING__) /* TASKING Compiler */ - #define __packed __unaligned -#endif /* __CC_ARM */ - - -/** - * @} - */ - - -/** @defgroup USB_CONF_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_CONF_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CONF_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CONF_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif //__USB_CONF__H__ - - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/Projects/discovery_demo/usb_core.c b/example/stm32f4/Projects/discovery_demo/usb_core.c deleted file mode 100644 index 74e432ac2..000000000 --- a/example/stm32f4/Projects/discovery_demo/usb_core.c +++ /dev/null @@ -1,2187 +0,0 @@ -/** - ****************************************************************************** - * @file usb_core.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief USB-OTG Core Layer - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" -#include "usb_bsp.h" - - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_CORE -* @brief This file includes the USB-OTG Core Layer -* @{ -*/ - - -/** @defgroup USB_CORE_Private_Defines -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USB_CORE_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_FunctionPrototypes -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_Functions -* @{ -*/ - -/** -* @brief USB_OTG_EnableCommonInt -* Initializes the commmon interrupts, used in both device and modes -* @param pdev : Selected device -* @retval None -*/ -static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef int_mask; - - int_mask.d32 = 0; - /* Clear any pending USB_OTG Interrupts */ -#ifndef USE_OTG_MODE - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GOTGINT, 0xFFFFFFFF); -#endif - /* Clear any pending interrupts */ - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF); - /* Enable the interrupts in the INTMSK */ - int_mask.b.wkupintr = 1; - int_mask.b.usbsuspend = 1; - -#ifdef USE_OTG_MODE - int_mask.b.otgintr = 1; - int_mask.b.sessreqintr = 1; - int_mask.b.conidstschng = 1; -#endif - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32); -} - -/** -* @brief USB_OTG_CoreReset : Soft reset of the core -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - __IO USB_OTG_GRSTCTL_TypeDef greset; - uint32_t count = 0; - - greset.d32 = 0; - /* Wait for AHB master IDLE state. */ - do - { - USB_OTG_BSP_uDelay(3); - greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - return USB_OTG_OK; - } - } - while (greset.b.ahbidle == 0); - /* Core Soft Reset */ - count = 0; - greset.b.csftrst = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRSTCTL, greset.d32 ); - do - { - greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - break; - } - } - while (greset.b.csftrst == 1); - /* Wait for 3 PHY Clocks*/ - USB_OTG_BSP_uDelay(3); - return status; -} - -/** -* @brief USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated -* with the EP -* @param pdev : Selected device -* @param src : source pointer -* @param ch_ep_num : end point number -* @param bytes : No. of bytes -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, - uint8_t *src, - uint8_t ch_ep_num, - uint16_t len) -{ - USB_OTG_STS status = USB_OTG_OK; - if (pdev->cfg.dma_enable == 0) - { - uint32_t count32b= 0 , i= 0; - __IO uint32_t *fifo; - - count32b = (len + 3) / 4; - fifo = pdev->regs.DFIFO[ch_ep_num]; - for (i = 0; i < count32b; i++, src+=4) - { - USB_OTG_WRITE_REG32( fifo, *((__packed uint32_t *)src) ); - } - } - return status; -} - - -/** -* @brief USB_OTG_ReadPacket : Reads a packet from the Rx FIFO -* @param pdev : Selected device -* @param dest : Destination Pointer -* @param bytes : No. of bytes -* @retval None -*/ -void *USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev, - uint8_t *dest, - uint16_t len) -{ - uint32_t i=0; - uint32_t count32b = (len + 3) / 4; - - __IO uint32_t *fifo = pdev->regs.DFIFO[0]; - - for ( i = 0; i < count32b; i++, dest += 4 ) - { - *(__packed uint32_t *)dest = USB_OTG_READ_REG32(fifo); - - } - return ((void *)dest); -} - -/** -* @brief USB_OTG_SelectCore -* Initialize core registers address. -* @param pdev : Selected device -* @param coreID : USB OTG Core ID -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID) -{ - uint32_t i , baseAddress = 0; - USB_OTG_STS status = USB_OTG_OK; - - pdev->cfg.dma_enable = 0; - - /* at startup the core is in FS mode */ - pdev->cfg.speed = USB_OTG_SPEED_FULL; - pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; - - /* initialize device cfg following its address */ - if (coreID == USB_OTG_FS_CORE_ID) - { - baseAddress = USB_OTG_FS_BASE_ADDR; - pdev->cfg.coreID = USB_OTG_FS_CORE_ID; - pdev->cfg.host_channels = 8 ; - pdev->cfg.dev_endpoints = 4 ; - pdev->cfg.TotalFifoSize = 320; /* in 32-bits */ - pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; - -#ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED - pdev->cfg.Sof_output = 1; -#endif - -#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT - pdev->cfg.low_power = 1; -#endif - } - else if (coreID == USB_OTG_HS_CORE_ID) - { - baseAddress = USB_OTG_HS_BASE_ADDR; - pdev->cfg.coreID = USB_OTG_HS_CORE_ID; - pdev->cfg.host_channels = 12 ; - pdev->cfg.dev_endpoints = 6 ; - pdev->cfg.TotalFifoSize = 1280;/* in 32-bits */ - -#ifdef USB_OTG_ULPI_PHY_ENABLED - pdev->cfg.phy_itface = USB_OTG_ULPI_PHY; -#else - #ifdef USB_OTG_EMBEDDED_PHY_ENABLED - pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; - #else - #ifdef USB_OTG_I2C_PHY_ENABLED - pdev->cfg.phy_itface = USB_OTG_I2C_PHY; - #endif - #endif -#endif - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - pdev->cfg.dma_enable = 1; -#endif - -#ifdef USB_OTG_HS_SOF_OUTPUT_ENABLED - pdev->cfg.Sof_output = 1; -#endif - -#ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT - pdev->cfg.low_power = 1; -#endif - - } - - pdev->regs.GREGS = (USB_OTG_GREGS *)(baseAddress + \ - USB_OTG_CORE_GLOBAL_REGS_OFFSET); - pdev->regs.DREGS = (USB_OTG_DREGS *) (baseAddress + \ - USB_OTG_DEV_GLOBAL_REG_OFFSET); - - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - pdev->regs.INEP_REGS[i] = (USB_OTG_INEPREGS *) \ - (baseAddress + USB_OTG_DEV_IN_EP_REG_OFFSET + \ - (i * USB_OTG_EP_REG_OFFSET)); - pdev->regs.OUTEP_REGS[i] = (USB_OTG_OUTEPREGS *) \ - (baseAddress + USB_OTG_DEV_OUT_EP_REG_OFFSET + \ - (i * USB_OTG_EP_REG_OFFSET)); - } - pdev->regs.HREGS = (USB_OTG_HREGS *)(baseAddress + \ - USB_OTG_HOST_GLOBAL_REG_OFFSET); - pdev->regs.HPRT0 = (uint32_t *)(baseAddress + USB_OTG_HOST_PORT_REGS_OFFSET); - - for (i = 0; i < pdev->cfg.host_channels; i++) - { - pdev->regs.HC_REGS[i] = (USB_OTG_HC_REGS *)(baseAddress + \ - USB_OTG_HOST_CHAN_REGS_OFFSET + \ - (i * USB_OTG_CHAN_REGS_OFFSET)); - } - for (i = 0; i < pdev->cfg.host_channels; i++) - { - pdev->regs.DFIFO[i] = (uint32_t *)(baseAddress + USB_OTG_DATA_FIFO_OFFSET +\ - (i * USB_OTG_DATA_FIFO_SIZE)); - } - pdev->regs.PCGCCTL = (uint32_t *)(baseAddress + USB_OTG_PCGCCTL_OFFSET); - - return status; -} - - -/** -* @brief USB_OTG_CoreInit -* Initializes the USB_OTG controller registers and prepares the core -* device mode or host mode operation. -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GUSBCFG_TypeDef usbcfg; - USB_OTG_GCCFG_TypeDef gccfg; - USB_OTG_GI2CCTL_TypeDef i2cctl; - USB_OTG_GAHBCFG_TypeDef ahbcfg; - - usbcfg.d32 = 0; - gccfg.d32 = 0; - ahbcfg.d32 = 0; - - - - if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) - { - gccfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GCCFG); - gccfg.b.pwdn = 0; - - if (pdev->cfg.Sof_output) - { - gccfg.b.sofouten = 1; - } - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); - - /* Init The ULPI Interface */ - usbcfg.d32 = 0; - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - - usbcfg.b.physel = 0; /* HS Interface */ -#ifdef USB_OTG_INTERNAL_VBUS_ENABLED - usbcfg.b.ulpi_ext_vbus_drv = 0; /* Use internal VBUS */ -#else - #ifdef USB_OTG_EXTERNAL_VBUS_ENABLED - usbcfg.b.ulpi_ext_vbus_drv = 1; /* Use external VBUS */ - #endif -#endif - usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */ - usbcfg.b.ulpi_utmi_sel = 1; /* ULPI seleInterfacect */ - - usbcfg.b.phyif = 0; /* 8 bits */ - usbcfg.b.ddrsel = 0; /* single data rate */ - - usbcfg.b.ulpi_fsls = 0; - usbcfg.b.ulpi_clk_sus_m = 0; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - - /* Reset after a PHY select */ - USB_OTG_CoreReset(pdev); - - if(pdev->cfg.dma_enable == 1) - { - - ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ - ahbcfg.b.dmaenable = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); - - } - } - else /* FS interface (embedded Phy or I2C Phy) */ - { - - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);; - usbcfg.b.physel = 1; /* FS Interface */ - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - /* Reset after a PHY select and set Host mode */ - USB_OTG_CoreReset(pdev); - /* Enable the I2C interface and deactivate the power down*/ - gccfg.d32 = 0; - gccfg.b.pwdn = 1; - - if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY) - { - gccfg.b.i2cifen = 1; - } - gccfg.b.vbussensingA = 1 ; - gccfg.b.vbussensingB = 1 ; -#ifndef VBUS_SENSING_ENABLED - gccfg.b.disablevbussensing = 1; -#endif - - if(pdev->cfg.Sof_output) - { - gccfg.b.sofouten = 1; - } - - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); - USB_OTG_BSP_mDelay(20); - /* Program GUSBCFG.OtgUtmifsSel to I2C*/ - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - - if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY) - { - usbcfg.b.otgutmifssel = 1; - } - - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - - if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY) - { - /*Program GI2CCTL.I2CEn*/ - i2cctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GI2CCTL); - i2cctl.b.i2cdevaddr = 1; - i2cctl.b.i2cen = 0; - i2cctl.b.dat_se0 = 1; - i2cctl.b.addr = 0x2D; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GI2CCTL, i2cctl.d32); - - USB_OTG_BSP_mDelay(200); - - i2cctl.b.i2cen = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GI2CCTL, i2cctl.d32); - USB_OTG_BSP_mDelay(200); - } - } - /* case the HS core is working in FS mode */ - if(pdev->cfg.dma_enable == 1) - { - - ahbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GAHBCFG); - ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ - ahbcfg.b.dmaenable = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); - - } - /* initialize OTG features */ -#ifdef USE_OTG_MODE - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - usbcfg.b.hnpcap = 1; - usbcfg.b.srpcap = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - USB_OTG_EnableCommonInt(pdev); -#endif - return status; -} -/** -* @brief USB_OTG_EnableGlobalInt -* Enables the controller's Global Int in the AHB Config reg -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GAHBCFG_TypeDef ahbcfg; - - ahbcfg.d32 = 0; - ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, 0, ahbcfg.d32); - return status; -} - - -/** -* @brief USB_OTG_DisableGlobalInt -* Enables the controller's Global Int in the AHB Config reg -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GAHBCFG_TypeDef ahbcfg; - ahbcfg.d32 = 0; - ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32, 0); - return status; -} - - -/** -* @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO -* @param pdev : Selected device -* @param num : FO num -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num ) -{ - USB_OTG_STS status = USB_OTG_OK; - __IO USB_OTG_GRSTCTL_TypeDef greset; - - uint32_t count = 0; - greset.d32 = 0; - greset.b.txfflsh = 1; - greset.b.txfnum = num; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 ); - do - { - greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - break; - } - } - while (greset.b.txfflsh == 1); - /* Wait for 3 PHY Clocks*/ - USB_OTG_BSP_uDelay(3); - return status; -} - - -/** -* @brief USB_OTG_FlushRxFifo : Flush a Rx FIFO -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_FlushRxFifo( USB_OTG_CORE_HANDLE *pdev ) -{ - USB_OTG_STS status = USB_OTG_OK; - __IO USB_OTG_GRSTCTL_TypeDef greset; - uint32_t count = 0; - - greset.d32 = 0; - greset.b.rxfflsh = 1; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 ); - do - { - greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - break; - } - } - while (greset.b.rxfflsh == 1); - /* Wait for 3 PHY Clocks*/ - USB_OTG_BSP_uDelay(3); - return status; -} - - -/** -* @brief USB_OTG_SetCurrentMode : Set ID line -* @param pdev : Selected device -* @param mode : (Host/device) -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev , uint8_t mode) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GUSBCFG_TypeDef usbcfg; - - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - - usbcfg.b.force_host = 0; - usbcfg.b.force_dev = 0; - - if ( mode == HOST_MODE) - { - usbcfg.b.force_host = 1; - } - else if ( mode == DEVICE_MODE) - { - usbcfg.b.force_dev = 1; - } - - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - USB_OTG_BSP_mDelay(50); - return status; -} - - -/** -* @brief USB_OTG_GetMode : Get current mode -* @param pdev : Selected device -* @retval current mode -*/ -uint32_t USB_OTG_GetMode(USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS ) & 0x1); -} - - -/** -* @brief USB_OTG_IsDeviceMode : Check if it is device mode -* @param pdev : Selected device -* @retval num_in_ep -*/ -uint8_t USB_OTG_IsDeviceMode(USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_GetMode(pdev) != HOST_MODE); -} - - -/** -* @brief USB_OTG_IsHostMode : Check if it is host mode -* @param pdev : Selected device -* @retval num_in_ep -*/ -uint8_t USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_GetMode(pdev) == HOST_MODE); -} - - -/** -* @brief USB_OTG_ReadCoreItr : returns the Core Interrupt register -* @param pdev : Selected device -* @retval Status -*/ -uint32_t USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t v = 0; - v = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS); - v &= USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK); - return v; -} - - -/** -* @brief USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register -* @param pdev : Selected device -* @retval Status -*/ -uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32 (&pdev->regs.GREGS->GOTGINT)); -} - -#ifdef USE_HOST_MODE -/** -* @brief USB_OTG_CoreInitHost : Initializes USB_OTG controller for host mode -* @param pdev : Selected device -* @retval status -*/ -USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_FSIZ_TypeDef nptxfifosize; - USB_OTG_FSIZ_TypeDef ptxfifosize; - USB_OTG_HCFG_TypeDef hcfg; - -#ifdef USE_OTG_MODE - USB_OTG_OTGCTL_TypeDef gotgctl; -#endif - - uint32_t i = 0; - - nptxfifosize.d32 = 0; - ptxfifosize.d32 = 0; -#ifdef USE_OTG_MODE - gotgctl.d32 = 0; -#endif - hcfg.d32 = 0; - - - /* configure charge pump IO */ - USB_OTG_BSP_ConfigVBUS(pdev); - - /* Restart the Phy Clock */ - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); - - /* Initialize Host Configuration Register */ - USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); /* in init phase */ - - hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); - hcfg.b.fslssupp = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); - - /* Configure data FIFO sizes */ - /* Rx FIFO */ -#ifdef USB_OTG_FS_CORE - if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID) - { - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); - nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; - nptxfifosize.b.depth = TXH_NP_FS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); - - ptxfifosize.b.startaddr = RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ; - ptxfifosize.b.depth = TXH_P_FS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); - } -#endif -#ifdef USB_OTG_HS_CORE - if (pdev->cfg.coreID == USB_OTG_HS_CORE_ID) - { - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); - nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; - nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); - - ptxfifosize.b.startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ; - ptxfifosize.b.depth = TXH_P_HS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); - } -#endif - -#ifdef USE_OTG_MODE - /* Clear Host Set HNP Enable in the USB_OTG Control Register */ - gotgctl.b.hstsethnpen = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0); -#endif - - /* Make sure the FIFOs are flushed. */ - USB_OTG_FlushTxFifo(pdev, 0x10 ); /* all Tx FIFOs */ - USB_OTG_FlushRxFifo(pdev); - - - /* Clear all pending HC Interrupts */ - for (i = 0; i < pdev->cfg.host_channels; i++) - { - USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF ); - USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCGINTMSK, 0 ); - } -#ifndef USE_OTG_MODE - USB_OTG_DriveVbus(pdev, 1); -#endif - - USB_OTG_EnableHostInt(pdev); - return status; -} - -/** -* @brief USB_OTG_IsEvenFrame -* This function returns the frame number for sof packet -* @param pdev : Selected device -* @retval Frame number -*/ -uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) -{ - return !(USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0x1); -} - -/** -* @brief USB_OTG_DriveVbus : set/reset vbus -* @param pdev : Selected device -* @param state : VBUS state -* @retval None -*/ -void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state) -{ - USB_OTG_HPRT0_TypeDef hprt0; - - hprt0.d32 = 0; - - /* enable disable the external charge pump */ - USB_OTG_BSP_DriveVBUS(pdev, state); - - /* Turn on the Host port power. */ - hprt0.d32 = USB_OTG_ReadHPRT0(pdev); - if ((hprt0.b.prtpwr == 0 ) && (state == 1 )) - { - hprt0.b.prtpwr = 1; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - } - if ((hprt0.b.prtpwr == 1 ) && (state == 0 )) - { - hprt0.b.prtpwr = 0; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - } - - USB_OTG_BSP_mDelay(200); -} -/** -* @brief USB_OTG_EnableHostInt: Enables the Host mode interrupts -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EnableHostInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GINTMSK_TypeDef intmsk; - intmsk.d32 = 0; - /* Disable all interrupts. */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTMSK, 0); - - /* Clear any pending interrupts. */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF); - - /* Enable the common interrupts */ - USB_OTG_EnableCommonInt(pdev); - - if (pdev->cfg.dma_enable == 0) - { - intmsk.b.rxstsqlvl = 1; - } - intmsk.b.portintr = 1; - intmsk.b.hcintr = 1; - intmsk.b.disconnect = 1; - intmsk.b.sofintr = 1; - intmsk.b.incomplisoout = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); - return status; -} - -/** -* @brief USB_OTG_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the -* HCFG register on the PHY type -* @param pdev : Selected device -* @param freq : clock frequency -* @retval None -*/ -void USB_OTG_InitFSLSPClkSel(USB_OTG_CORE_HANDLE *pdev , uint8_t freq) -{ - USB_OTG_HCFG_TypeDef hcfg; - - hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); - hcfg.b.fslspclksel = freq; - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); -} - - -/** -* @brief USB_OTG_ReadHPRT0 : Reads HPRT0 to modify later -* @param pdev : Selected device -* @retval HPRT0 value -*/ -uint32_t USB_OTG_ReadHPRT0(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef hprt0; - - hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); - hprt0.b.prtena = 0; - hprt0.b.prtconndet = 0; - hprt0.b.prtenchng = 0; - hprt0.b.prtovrcurrchng = 0; - return hprt0.d32; -} - - -/** -* @brief USB_OTG_ReadHostAllChannels_intr : Register PCD Callbacks -* @param pdev : Selected device -* @retval Status -*/ -uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32 (&pdev->regs.HREGS->HAINT)); -} - - -/** -* @brief USB_OTG_ResetPort : Reset Host Port -* @param pdev : Selected device -* @retval status -* @note : (1)The application must wait at least 10 ms (+ 10 ms security) -* before clearing the reset bit. -*/ -uint32_t USB_OTG_ResetPort(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef hprt0; - - hprt0.d32 = USB_OTG_ReadHPRT0(pdev); - hprt0.b.prtrst = 1; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - USB_OTG_BSP_mDelay (10); /* See Note #1 */ - hprt0.b.prtrst = 0; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - USB_OTG_BSP_mDelay (20); - return 1; -} - - -/** -* @brief USB_OTG_HC_Init : Prepares a host channel for transferring packets -* @param pdev : Selected device -* @param hc_num : channel number -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - uint32_t intr_enable = 0; - USB_OTG_HCGINTMSK_TypeDef hcintmsk; - USB_OTG_GINTMSK_TypeDef gintmsk; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCINTn_TypeDef hcint; - - - gintmsk.d32 = 0; - hcintmsk.d32 = 0; - hcchar.d32 = 0; - - /* Clear old interrupt conditions for this host channel. */ - hcint.d32 = 0xFFFFFFFF; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINT, hcint.d32); - - /* Enable channel interrupts required for this transfer. */ - hcintmsk.d32 = 0; - - if (pdev->cfg.dma_enable == 1) - { - hcintmsk.b.ahberr = 1; - } - - switch (pdev->host.hc[hc_num].ep_type) - { - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - hcintmsk.b.xfercompl = 1; - hcintmsk.b.stall = 1; - hcintmsk.b.xacterr = 1; - hcintmsk.b.datatglerr = 1; - hcintmsk.b.nak = 1; - if (pdev->host.hc[hc_num].ep_is_in) - { - hcintmsk.b.bblerr = 1; - } - else - { - hcintmsk.b.nyet = 1; - if (pdev->host.hc[hc_num].do_ping) - { - hcintmsk.b.ack = 1; - } - } - break; - case EP_TYPE_INTR: - hcintmsk.b.xfercompl = 1; - hcintmsk.b.nak = 1; - hcintmsk.b.stall = 1; - hcintmsk.b.xacterr = 1; - hcintmsk.b.datatglerr = 1; - hcintmsk.b.frmovrun = 1; - - if (pdev->host.hc[hc_num].ep_is_in) - { - hcintmsk.b.bblerr = 1; - } - - break; - case EP_TYPE_ISOC: - hcintmsk.b.xfercompl = 1; - hcintmsk.b.frmovrun = 1; - hcintmsk.b.ack = 1; - - if (pdev->host.hc[hc_num].ep_is_in) - { - hcintmsk.b.xacterr = 1; - hcintmsk.b.bblerr = 1; - } - break; - } - - - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, hcintmsk.d32); - - - /* Enable the top level host channel interrupt. */ - intr_enable = (1 << hc_num); - USB_OTG_MODIFY_REG32(&pdev->regs.HREGS->HAINTMSK, 0, intr_enable); - - /* Make sure host channel interrupts are enabled. */ - gintmsk.b.hcintr = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, gintmsk.d32); - - /* Program the HCCHAR register */ - hcchar.d32 = 0; - hcchar.b.devaddr = pdev->host.hc[hc_num].dev_addr; - hcchar.b.epnum = pdev->host.hc[hc_num].ep_num; - hcchar.b.epdir = pdev->host.hc[hc_num].ep_is_in; - hcchar.b.lspddev = (pdev->host.hc[hc_num].speed == HPRT0_PRTSPD_LOW_SPEED); - hcchar.b.eptype = pdev->host.hc[hc_num].ep_type; - hcchar.b.mps = pdev->host.hc[hc_num].max_packet; - if (pdev->host.hc[hc_num].ep_type == HCCHAR_INTR) - { - hcchar.b.oddfrm = 1; - } - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; -} - - -/** -* @brief USB_OTG_HC_StartXfer : Start transfer -* @param pdev : Selected device -* @param hc_num : channel number -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCTSIZn_TypeDef hctsiz; - USB_OTG_HNPTXSTS_TypeDef hnptxsts; - USB_OTG_HPTXSTS_TypeDef hptxsts; - USB_OTG_GINTMSK_TypeDef intmsk; - uint16_t len_words = 0; - - uint16_t num_packets; - uint16_t max_hc_pkt_count; - - max_hc_pkt_count = 256; - hctsiz.d32 = 0; - hcchar.d32 = 0; - intmsk.d32 = 0; - - /* Compute the expected number of packets associated to the transfer */ - if (pdev->host.hc[hc_num].xfer_len > 0) - { - num_packets = (pdev->host.hc[hc_num].xfer_len + \ - pdev->host.hc[hc_num].max_packet - 1) / pdev->host.hc[hc_num].max_packet; - - if (num_packets > max_hc_pkt_count) - { - num_packets = max_hc_pkt_count; - pdev->host.hc[hc_num].xfer_len = num_packets * \ - pdev->host.hc[hc_num].max_packet; - } - } - else - { - num_packets = 1; - } - if (pdev->host.hc[hc_num].ep_is_in) - { - pdev->host.hc[hc_num].xfer_len = num_packets * \ - pdev->host.hc[hc_num].max_packet; - } - /* Initialize the HCTSIZn register */ - hctsiz.b.xfersize = pdev->host.hc[hc_num].xfer_len; - hctsiz.b.pktcnt = num_packets; - hctsiz.b.pid = pdev->host.hc[hc_num].data_pid; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCDMA, (unsigned int)pdev->host.hc[hc_num].xfer_buff); - } - - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); - hcchar.b.oddfrm = USB_OTG_IsEvenFrame(pdev); - - /* Set host channel enable */ - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - - if (pdev->cfg.dma_enable == 0) /* Slave mode */ - { - if((pdev->host.hc[hc_num].ep_is_in == 0) && - (pdev->host.hc[hc_num].xfer_len > 0)) - { - switch(pdev->host.hc[hc_num].ep_type) - { - /* Non periodic transfer */ - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4; - - /* check if there is enough space in FIFO space */ - if(len_words > hnptxsts.b.nptxfspcavail) - { - /* need to process data in nptxfempty interrupt */ - intmsk.b.nptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); - } - - break; - /* Periodic transfer */ - case EP_TYPE_INTR: - case EP_TYPE_ISOC: - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4; - /* check if there is enough space in FIFO space */ - if(len_words > hptxsts.b.ptxfspcavail) /* split the transfer */ - { - /* need to process data in ptxfempty interrupt */ - intmsk.b.ptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); - } - break; - - default: - break; - } - - /* Write packet into the Tx FIFO. */ - USB_OTG_WritePacket(pdev, - pdev->host.hc[hc_num].xfer_buff , - hc_num, pdev->host.hc[hc_num].xfer_len); - } - } - return status; -} - - -/** -* @brief USB_OTG_HC_Halt : Halt channel -* @param pdev : Selected device -* @param hc_num : channel number -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_HC_Halt(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_HNPTXSTS_TypeDef nptxsts; - USB_OTG_HPTXSTS_TypeDef hptxsts; - USB_OTG_HCCHAR_TypeDef hcchar; - - nptxsts.d32 = 0; - hptxsts.d32 = 0; - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); - hcchar.b.chen = 1; - hcchar.b.chdis = 1; - - /* Check for space in the request queue to issue the halt. */ - if (hcchar.b.eptype == HCCHAR_CTRL || hcchar.b.eptype == HCCHAR_BULK) - { - nptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - if (nptxsts.b.nptxqspcavail == 0) - { - hcchar.b.chen = 0; - } - } - else - { - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - if (hptxsts.b.ptxqspcavail == 0) - { - hcchar.b.chen = 0; - } - } - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; -} - -/** -* @brief Issue a ping token -* @param None -* @retval : None -*/ -USB_OTG_STS USB_OTG_HC_DoPing(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCTSIZn_TypeDef hctsiz; - - hctsiz.d32 = 0; - hctsiz.b.dopng = 1; - hctsiz.b.pktcnt = 1; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; -} - -/** -* @brief Stop the device and clean up fifo's -* @param None -* @retval : None -*/ -void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HCCHAR_TypeDef hcchar; - uint32_t i; - - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINTMSK , 0); - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINT, 0xFFFFFFFF); - /* Flush out any leftover queued requests. */ - - for (i = 0; i < pdev->cfg.host_channels; i++) - { - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR); - hcchar.b.chen = 0; - hcchar.b.chdis = 1; - hcchar.b.epdir = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[i]->HCCHAR, hcchar.d32); - } - - /* Flush the FIFO */ - USB_OTG_FlushRxFifo(pdev); - USB_OTG_FlushTxFifo(pdev , 0x10 ); -} -#endif -#ifdef USE_DEVICE_MODE -/* PCD Core Layer */ - -/** -* @brief USB_OTG_InitDevSpeed :Initializes the DevSpd field of DCFG register -* depending the PHY type and the enumeration speed of the device. -* @param pdev : Selected device -* @retval : None -*/ -void USB_OTG_InitDevSpeed(USB_OTG_CORE_HANDLE *pdev , uint8_t speed) -{ - USB_OTG_DCFG_TypeDef dcfg; - - dcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCFG); - dcfg.b.devspd = speed; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCFG, dcfg.d32); -} - - -/** -* @brief USB_OTG_CoreInitDev : Initializes the USB_OTG controller registers -* for device mode -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - uint32_t i; - USB_OTG_DCFG_TypeDef dcfg; - USB_OTG_FSIZ_TypeDef nptxfifosize; - USB_OTG_FSIZ_TypeDef txfifosize; - USB_OTG_DIEPMSK_TypeDef msk; - USB_OTG_DTHRCTL_TypeDef dthrctl; - - depctl.d32 = 0; - dcfg.d32 = 0; - nptxfifosize.d32 = 0; - txfifosize.d32 = 0; - msk.d32 = 0; - - /* Restart the Phy Clock */ - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); - /* Device configuration register */ - dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG); - dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32 ); - -#ifdef USB_OTG_FS_CORE - if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID ) - { - - /* Set Full speed phy */ - USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_FULL); - - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); - - /* EP0 TX*/ - nptxfifosize.b.depth = TX0_FIFO_FS_SIZE; - nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); - - - /* EP1 TX*/ - txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; - txfifosize.b.depth = TX1_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); - - - /* EP2 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX2_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); - - - /* EP3 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX3_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); - } -#endif -#ifdef USB_OTG_HS_CORE - if(pdev->cfg.coreID == USB_OTG_HS_CORE_ID ) - { - - /* Set High speed phy */ - - if(pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) - { - USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH); - } - else /* set High speed phy in Full speed mode */ - { - USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH_IN_FULL); - } - - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); - - /* EP0 TX*/ - nptxfifosize.b.depth = TX0_FIFO_HS_SIZE; - nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); - - - /* EP1 TX*/ - txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; - txfifosize.b.depth = TX1_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); - - - /* EP2 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX2_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); - - - /* EP3 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX3_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); - - /* EP4 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX4_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[3], txfifosize.d32 ); - - - /* EP5 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX5_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[4], txfifosize.d32 ); - } -#endif - /* Flush the FIFOs */ - USB_OTG_FlushTxFifo(pdev , 0x10); /* all Tx FIFOs */ - USB_OTG_FlushRxFifo(pdev); - /* Clear all pending Device Interrupts */ - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); - - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[i]->DIEPCTL); - if (depctl.b.epena) - { - depctl.d32 = 0; - depctl.b.epdis = 1; - depctl.b.snak = 1; - } - else - { - depctl.d32 = 0; - } - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPCTL, depctl.d32); - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPTSIZ, 0); - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); - } - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - USB_OTG_DEPCTL_TypeDef depctl; - depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPCTL); - if (depctl.b.epena) - { - depctl.d32 = 0; - depctl.b.epdis = 1; - depctl.b.snak = 1; - } - else - { - depctl.d32 = 0; - } - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPCTL, depctl.d32); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPTSIZ, 0); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); - } - msk.d32 = 0; - msk.b.txfifoundrn = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPMSK, msk.d32, msk.d32); - - if (pdev->cfg.dma_enable == 1) - { - dthrctl.d32 = 0; - dthrctl.b.non_iso_thr_en = 1; - dthrctl.b.iso_thr_en = 1; - dthrctl.b.tx_thr_len = 64; - dthrctl.b.rx_thr_en = 1; - dthrctl.b.rx_thr_len = 64; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DTHRCTL, dthrctl.d32); - } - USB_OTG_EnableDevInt(pdev); - return status; -} - - -/** -* @brief USB_OTG_EnableDevInt : Enables the Device mode interrupts -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EnableDevInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GINTMSK_TypeDef intmsk; - - intmsk.d32 = 0; - - /* Disable all interrupts. */ - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, 0); - /* Clear any pending interrupts */ - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF); - /* Enable the common interrupts */ - USB_OTG_EnableCommonInt(pdev); - - if (pdev->cfg.dma_enable == 0) - { - intmsk.b.rxstsqlvl = 1; - } - - /* Enable interrupts matching to the Device mode ONLY */ - intmsk.b.usbsuspend = 1; - intmsk.b.usbreset = 1; - intmsk.b.enumdone = 1; - intmsk.b.inepintr = 1; - intmsk.b.outepintr = 1; - intmsk.b.sofintr = 1; - - intmsk.b.incomplisoin = 1; - intmsk.b.incomplisoout = 1; -#ifdef VBUS_SENSING_ENABLED - intmsk.b.sessreqintr = 1; - intmsk.b.otgintr = 1; -#endif - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); - return status; -} - - -/** -* @brief USB_OTG_GetDeviceSpeed -* Get the device speed from the device status register -* @param None -* @retval status -*/ -enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DSTS_TypeDef dsts; - enum USB_OTG_SPEED speed = USB_SPEED_UNKNOWN; - - - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - switch (dsts.b.enumspd) - { - case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: - speed = USB_SPEED_HIGH; - break; - case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: - case DSTS_ENUMSPD_FS_PHY_48MHZ: - speed = USB_SPEED_FULL; - break; - - case DSTS_ENUMSPD_LS_PHY_6MHZ: - speed = USB_SPEED_LOW; - break; - } - - return speed; -} -/** -* @brief enables EP0 OUT to receive SETUP packets and configures EP0 -* for transmitting packets -* @param None -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EP0Activate(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DSTS_TypeDef dsts; - USB_OTG_DEPCTL_TypeDef diepctl; - USB_OTG_DCTL_TypeDef dctl; - - dctl.d32 = 0; - /* Read the Device Status and Endpoint 0 Control registers */ - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - diepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL); - /* Set the MPS of the IN EP based on the enumeration speed */ - switch (dsts.b.enumspd) - { - case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: - case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: - case DSTS_ENUMSPD_FS_PHY_48MHZ: - diepctl.b.mps = DEP0CTL_MPS_64; - break; - case DSTS_ENUMSPD_LS_PHY_6MHZ: - diepctl.b.mps = DEP0CTL_MPS_8; - break; - } - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL, diepctl.d32); - dctl.b.cgnpinnak = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, dctl.d32); - return status; -} - - -/** -* @brief USB_OTG_EPActivate : Activates an EP -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPActivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DAINT_TypeDef daintmsk; - __IO uint32_t *addr; - - - depctl.d32 = 0; - daintmsk.d32 = 0; - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL; - daintmsk.ep.in = 1 << ep->num; - } - else - { - addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL; - daintmsk.ep.out = 1 << ep->num; - } - /* If the EP is already active don't change the EP Control - * register. */ - depctl.d32 = USB_OTG_READ_REG32(addr); - if (!depctl.b.usbactep) - { - depctl.b.mps = ep->maxpacket; - depctl.b.eptype = ep->type; - depctl.b.txfnum = ep->tx_fifo_num; - depctl.b.setd0pid = 1; - depctl.b.usbactep = 1; - USB_OTG_WRITE_REG32(addr, depctl.d32); - } - /* Enable the Interrupt for this EP */ -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID)) - { - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, 0, daintmsk.d32); - } - else -#endif - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, 0, daintmsk.d32); - return status; -} - - -/** -* @brief USB_OTG_EPDeactivate : Deactivates an EP -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DAINT_TypeDef daintmsk; - __IO uint32_t *addr; - - depctl.d32 = 0; - daintmsk.d32 = 0; - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL; - daintmsk.ep.in = 1 << ep->num; - } - else - { - addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL; - daintmsk.ep.out = 1 << ep->num; - } - depctl.b.usbactep = 0; - USB_OTG_WRITE_REG32(addr, depctl.d32); - /* Disable the Interrupt for this EP */ - -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID)) - { - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, daintmsk.d32, 0); - } - else -#endif - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, daintmsk.d32, 0); - return status; -} - - -/** -* @brief USB_OTG_EPStartXfer : Handle the setup for data xfer for an EP and -* starts the xfer -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DEPXFRSIZ_TypeDef deptsiz; - USB_OTG_DSTS_TypeDef dsts; - uint32_t fifoemptymsk = 0; - - depctl.d32 = 0; - deptsiz.d32 = 0; - /* IN endpoint */ - if (ep->is_in == 1) - { - depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPCTL)); - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ)); - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = 0; - deptsiz.b.pktcnt = 1; - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - deptsiz.b.xfersize = ep->xfer_len; - deptsiz.b.pktcnt = (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; - - if (ep->type == EP_TYPE_ISOC) - { - deptsiz.b.mc = 1; - } - } - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ, deptsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); - } - else - { - if (ep->type != EP_TYPE_ISOC) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - fifoemptymsk = 1 << ep->num; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk); - } - } - } - - - if (ep->type == EP_TYPE_ISOC) - { - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - if (((dsts.b.soffn)&0x1) == 0) - { - depctl.b.setd1pid = 1; - } - else - { - depctl.b.setd0pid = 1; - } - } - - /* EP enable, IN data in FIFO */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPCTL, depctl.d32); - - if (ep->type == EP_TYPE_ISOC) - { - USB_OTG_WritePacket(pdev, ep->xfer_buff, ep->num, ep->xfer_len); - } - } - else - { - /* OUT endpoint */ - depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL)); - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ)); - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - else - { - deptsiz.b.pktcnt = (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket; - deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; - } - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr); - } - - if (ep->type == EP_TYPE_ISOC) - { - if (ep->even_odd_frame) - { - depctl.b.setd1pid = 1; - } - else - { - depctl.b.setd0pid = 1; - } - } - /* EP enable */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL, depctl.d32); - } - return status; -} - - -/** -* @brief USB_OTG_EP0StartXfer : Handle the setup for a data xfer for EP0 and -* starts the xfer -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DEP0XFRSIZ_TypeDef deptsiz; - USB_OTG_INEPREGS *in_regs; - uint32_t fifoemptymsk = 0; - - depctl.d32 = 0; - deptsiz.d32 = 0; - /* IN endpoint */ - if (ep->is_in == 1) - { - in_regs = pdev->regs.INEP_REGS[0]; - depctl.d32 = USB_OTG_READ_REG32(&in_regs->DIEPCTL); - deptsiz.d32 = USB_OTG_READ_REG32(&in_regs->DIEPTSIZ); - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = 0; - deptsiz.b.pktcnt = 1; - - } - else - { - if (ep->xfer_len > ep->maxpacket) - { - ep->xfer_len = ep->maxpacket; - deptsiz.b.xfersize = ep->maxpacket; - } - else - { - deptsiz.b.xfersize = ep->xfer_len; - } - deptsiz.b.pktcnt = 1; - } - USB_OTG_WRITE_REG32(&in_regs->DIEPTSIZ, deptsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); - } - - /* EP enable, IN data in FIFO */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32(&in_regs->DIEPCTL, depctl.d32); - - - - if (pdev->cfg.dma_enable == 0) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - { - fifoemptymsk |= 1 << ep->num; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk); - } - } - } - } - else - { - /* OUT endpoint */ - depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - deptsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ); - /* Program the transfer size and packet count as follows: - * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) - * pktcnt = N */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - else - { - ep->xfer_len = ep->maxpacket; - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32); - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr); - } - /* EP enable */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32 (&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL), depctl.d32); - - } - return status; -} - - -/** -* @brief USB_OTG_EPSetStall : Set the EP STALL -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPSetStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - - depctl.d32 = 0; - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - /* set the disable and stall bits */ - if (depctl.b.epena) - { - depctl.b.epdis = 1; - } - depctl.b.stall = 1; - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); - } - else - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - /* set the stall bit */ - depctl.b.stall = 1; - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); - } - return status; -} - - -/** -* @brief Clear the EP STALL -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPClearStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - - depctl.d32 = 0; - - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - } - else - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - } - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - /* clear the stall bits */ - depctl.b.stall = 0; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) - { - depctl.b.setd0pid = 1; /* DATA0 */ - } - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); - return status; -} - - -/** -* @brief USB_OTG_ReadDevAllOutEp_itr : returns OUT endpoint interrupt bits -* @param pdev : Selected device -* @retval OUT endpoint interrupt bits -*/ -uint32_t USB_OTG_ReadDevAllOutEp_itr(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t v; - v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT); - v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK); - return ((v & 0xffff0000) >> 16); -} - - -/** -* @brief USB_OTG_ReadDevOutEP_itr : returns Device OUT EP Interrupt register -* @param pdev : Selected device -* @param ep : end point number -* @retval Device OUT EP Interrupt register -*/ -uint32_t USB_OTG_ReadDevOutEP_itr(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - uint32_t v; - v = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT); - v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOEPMSK); - return v; -} - - -/** -* @brief USB_OTG_ReadDevAllInEPItr : Get int status register -* @param pdev : Selected device -* @retval int status register -*/ -uint32_t USB_OTG_ReadDevAllInEPItr(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t v; - v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT); - v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK); - return (v & 0xffff); -} - -/** -* @brief configures EPO to receive SETUP packets -* @param None -* @retval : None -*/ -void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DEP0XFRSIZ_TypeDef doeptsize0; - doeptsize0.d32 = 0; - doeptsize0.b.supcnt = 3; - doeptsize0.b.pktcnt = 1; - doeptsize0.b.xfersize = 8 * 3; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPTSIZ, doeptsize0.d32 ); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_DEPCTL_TypeDef doepctl; - doepctl.d32 = 0; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPDMA, - (uint32_t)&pdev->dev.setup_packet); - - /* EP enable */ - doepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPCTL); - doepctl.b.epena = 1; - doepctl.d32 = 0x80008000; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPCTL, doepctl.d32); - } -} - -/** -* @brief USB_OTG_RemoteWakeup : active remote wakeup signalling -* @param None -* @retval : None -*/ -void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_DCTL_TypeDef dctl; - USB_OTG_DSTS_TypeDef dsts; - USB_OTG_PCGCCTL_TypeDef power; - - if (pdev->dev.DevRemoteWakeup) - { - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - if(dsts.b.suspsts == 1) - { - if(pdev->cfg.low_power) - { - /* un-gate USB Core clock */ - power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL); - power.b.gatehclk = 0; - power.b.stoppclk = 0; - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - } - /* active Remote wakeup signaling */ - dctl.d32 = 0; - dctl.b.rmtwkupsig = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, 0, dctl.d32); - USB_OTG_BSP_mDelay(5); - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 ); - } - } -} - - -/** -* @brief USB_OTG_UngateClock : active USB Core clock -* @param None -* @retval : None -*/ -void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev) -{ - if(pdev->cfg.low_power) - { - - USB_OTG_DSTS_TypeDef dsts; - USB_OTG_PCGCCTL_TypeDef power; - - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - if(dsts.b.suspsts == 1) - { - /* un-gate USB Core clock */ - power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL); - power.b.gatehclk = 0; - power.b.stoppclk = 0; - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - - } - } -} - -/** -* @brief Stop the device and clean up fifo's -* @param None -* @retval : None -*/ -void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t i; - - pdev->dev.device_status = 1; - - for (i = 0; i < pdev->cfg.dev_endpoints ; i++) - { - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); - } - - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - - /* Flush the FIFO */ - USB_OTG_FlushRxFifo(pdev); - USB_OTG_FlushTxFifo(pdev , 0x10 ); -} - -/** -* @brief returns the EP Status -* @param pdev : Selected device -* ep : endpoint structure -* @retval : EP status -*/ - -uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep) -{ - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - uint32_t Status = 0; - - depctl.d32 = 0; - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (depctl.b.stall == 1) - Status = USB_OTG_EP_TX_STALL; - else if (depctl.b.naksts == 1) - Status = USB_OTG_EP_TX_NAK; - else - Status = USB_OTG_EP_TX_VALID; - - } - else - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - if (depctl.b.stall == 1) - Status = USB_OTG_EP_RX_STALL; - else if (depctl.b.naksts == 1) - Status = USB_OTG_EP_RX_NAK; - else - Status = USB_OTG_EP_RX_VALID; - } - - /* Return the current status */ - return Status; -} - -/** -* @brief Set the EP Status -* @param pdev : Selected device -* Status : new Status -* ep : EP structure -* @retval : None -*/ -void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status) -{ - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - - depctl.d32 = 0; - - /* Process for IN endpoint */ - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (Status == USB_OTG_EP_TX_STALL) - { - USB_OTG_EPSetStall(pdev, ep); return; - } - else if (Status == USB_OTG_EP_TX_NAK) - depctl.b.snak = 1; - else if (Status == USB_OTG_EP_TX_VALID) - { - if (depctl.b.stall == 1) - { - ep->even_odd_frame = 0; - USB_OTG_EPClearStall(pdev, ep); - return; - } - depctl.b.cnak = 1; - depctl.b.usbactep = 1; - depctl.b.epena = 1; - } - else if (Status == USB_OTG_EP_TX_DIS) - depctl.b.usbactep = 0; - } - else /* Process for OUT endpoint */ - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (Status == USB_OTG_EP_RX_STALL) { - depctl.b.stall = 1; - } - else if (Status == USB_OTG_EP_RX_NAK) - depctl.b.snak = 1; - else if (Status == USB_OTG_EP_RX_VALID) - { - if (depctl.b.stall == 1) - { - ep->even_odd_frame = 0; - USB_OTG_EPClearStall(pdev, ep); - return; - } - depctl.b.cnak = 1; - depctl.b.usbactep = 1; - depctl.b.epena = 1; - } - else if (Status == USB_OTG_EP_RX_DIS) - { - depctl.b.usbactep = 0; - } - } - - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); -} - -#endif -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/discovery_demo/usb_core.h b/example/stm32f4/Projects/discovery_demo/usb_core.h deleted file mode 100644 index 82a09e15c..000000000 --- a/example/stm32f4/Projects/discovery_demo/usb_core.h +++ /dev/null @@ -1,408 +0,0 @@ -/** - ****************************************************************************** - * @file usb_core.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Header of the Core Layer - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_CORE_H__ -#define __USB_CORE_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" -#include "usb_regs.h" -#include "usb_defines.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_CORE - * @brief usb otg driver core layer - * @{ - */ - - -/** @defgroup USB_CORE_Exported_Defines - * @{ - */ - -#define USB_OTG_EP0_IDLE 0 -#define USB_OTG_EP0_SETUP 1 -#define USB_OTG_EP0_DATA_IN 2 -#define USB_OTG_EP0_DATA_OUT 3 -#define USB_OTG_EP0_STATUS_IN 4 -#define USB_OTG_EP0_STATUS_OUT 5 -#define USB_OTG_EP0_STALL 6 - -#define USB_OTG_EP_TX_DIS 0x0000 -#define USB_OTG_EP_TX_STALL 0x0010 -#define USB_OTG_EP_TX_NAK 0x0020 -#define USB_OTG_EP_TX_VALID 0x0030 - -#define USB_OTG_EP_RX_DIS 0x0000 -#define USB_OTG_EP_RX_STALL 0x1000 -#define USB_OTG_EP_RX_NAK 0x2000 -#define USB_OTG_EP_RX_VALID 0x3000 -/** - * @} - */ -#define MAX_DATA_LENGTH 0xFF - -/** @defgroup USB_CORE_Exported_Types - * @{ - */ - - -typedef enum { - USB_OTG_OK = 0, - USB_OTG_FAIL -}USB_OTG_STS; - -typedef enum { - HC_IDLE = 0, - HC_XFRC, - HC_HALTED, - HC_NAK, - HC_NYET, - HC_STALL, - HC_XACTERR, - HC_BBLERR, - HC_DATATGLERR, -}HC_STATUS; - -typedef enum { - URB_IDLE = 0, - URB_DONE, - URB_NOTREADY, - URB_ERROR, - URB_STALL -}URB_STATE; - -typedef enum { - CTRL_START = 0, - CTRL_XFRC, - CTRL_HALTED, - CTRL_NAK, - CTRL_STALL, - CTRL_XACTERR, - CTRL_BBLERR, - CTRL_DATATGLERR, - CTRL_FAIL -}CTRL_STATUS; - - -typedef struct USB_OTG_hc -{ - uint8_t dev_addr ; - uint8_t ep_num; - uint8_t ep_is_in; - uint8_t speed; - uint8_t do_ping; - uint8_t ep_type; - uint16_t max_packet; - uint8_t data_pid; - uint8_t *xfer_buff; - uint32_t xfer_len; - uint32_t xfer_count; - uint8_t toggle_in; - uint8_t toggle_out; - uint32_t dma_addr; -} -USB_OTG_HC , *PUSB_OTG_HC; - -typedef struct USB_OTG_ep -{ - uint8_t num; - uint8_t is_in; - uint8_t is_stall; - uint8_t type; - uint8_t data_pid_start; - uint8_t even_odd_frame; - uint16_t tx_fifo_num; - uint32_t maxpacket; - /* transaction level variables*/ - uint8_t *xfer_buff; - uint32_t dma_addr; - uint32_t xfer_len; - uint32_t xfer_count; - /* Transfer level variables*/ - uint32_t rem_data_len; - uint32_t total_data_len; - uint32_t ctl_data_len; - -} - -USB_OTG_EP , *PUSB_OTG_EP; - - - -typedef struct USB_OTG_core_cfg -{ - uint8_t host_channels; - uint8_t dev_endpoints; - uint8_t speed; - uint8_t dma_enable; - uint16_t mps; - uint16_t TotalFifoSize; - uint8_t phy_itface; - uint8_t Sof_output; - uint8_t low_power; - uint8_t coreID; - -} -USB_OTG_CORE_CFGS, *PUSB_OTG_CORE_CFGS; - - - -typedef struct usb_setup_req { - - uint8_t bmRequest; - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; -} USB_SETUP_REQ; - -typedef struct _Device_TypeDef -{ - uint8_t *(*GetDeviceDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetLangIDStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetManufacturerStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetProductStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetSerialStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetConfigurationStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length); -} USBD_DEVICE, *pUSBD_DEVICE; - -typedef struct USB_OTG_hPort -{ - void (*Disconnect) (void *phost); - void (*Connect) (void *phost); - uint8_t ConnStatus; - uint8_t DisconnStatus; - uint8_t ConnHandled; - uint8_t DisconnHandled; -} USB_OTG_hPort_TypeDef; - -typedef struct _Device_cb -{ - uint8_t (*Init) (void *pdev , uint8_t cfgidx); - uint8_t (*DeInit) (void *pdev , uint8_t cfgidx); - /* Control Endpoints*/ - uint8_t (*Setup) (void *pdev , USB_SETUP_REQ *req); - uint8_t (*EP0_TxSent) (void *pdev ); - uint8_t (*EP0_RxReady) (void *pdev ); - /* Class Specific Endpoints*/ - uint8_t (*DataIn) (void *pdev , uint8_t epnum); - uint8_t (*DataOut) (void *pdev , uint8_t epnum); - uint8_t (*SOF) (void *pdev); - uint8_t (*IsoINIncomplete) (void *pdev); - uint8_t (*IsoOUTIncomplete) (void *pdev); - - uint8_t *(*GetConfigDescriptor)( uint8_t speed , uint16_t *length); -#ifdef USB_OTG_HS_CORE - uint8_t *(*GetOtherConfigDescriptor)( uint8_t speed , uint16_t *length); -#endif - -#ifdef USB_SUPPORT_USER_STRING_DESC - uint8_t *(*GetUsrStrDescriptor)( uint8_t speed ,uint8_t index, uint16_t *length); -#endif - -} USBD_Class_cb_TypeDef; - - - -typedef struct _USBD_USR_PROP -{ - void (*Init)(void); - void (*DeviceReset)(uint8_t speed); - void (*DeviceConfigured)(void); - void (*DeviceSuspended)(void); - void (*DeviceResumed)(void); - - void (*DeviceConnected)(void); - void (*DeviceDisconnected)(void); - -} -USBD_Usr_cb_TypeDef; - -typedef struct _DCD -{ - uint8_t device_config; - uint8_t device_state; - uint8_t device_status; - uint8_t device_address; - uint32_t DevRemoteWakeup; - USB_OTG_EP in_ep [USB_OTG_MAX_TX_FIFOS]; - USB_OTG_EP out_ep [USB_OTG_MAX_TX_FIFOS]; - uint8_t setup_packet [8*3]; - USBD_Class_cb_TypeDef *class_cb; - USBD_Usr_cb_TypeDef *usr_cb; - USBD_DEVICE *usr_device; - uint8_t *pConfig_descriptor; - } -DCD_DEV , *DCD_PDEV; - - -typedef struct _HCD -{ - uint8_t Rx_Buffer [MAX_DATA_LENGTH]; - __IO uint32_t ConnSts; - __IO uint32_t ErrCnt[USB_OTG_MAX_TX_FIFOS]; - __IO uint32_t XferCnt[USB_OTG_MAX_TX_FIFOS]; - __IO HC_STATUS HC_Status[USB_OTG_MAX_TX_FIFOS]; - __IO URB_STATE URB_State[USB_OTG_MAX_TX_FIFOS]; - USB_OTG_HC hc [USB_OTG_MAX_TX_FIFOS]; - uint16_t channel [USB_OTG_MAX_TX_FIFOS]; - USB_OTG_hPort_TypeDef *port_cb; -} -HCD_DEV , *USB_OTG_USBH_PDEV; - - -typedef struct _OTG -{ - uint8_t OTG_State; - uint8_t OTG_PrevState; - uint8_t OTG_Mode; -} -OTG_DEV , *USB_OTG_USBO_PDEV; - -typedef struct USB_OTG_handle -{ - USB_OTG_CORE_CFGS cfg; - USB_OTG_CORE_REGS regs; -#ifdef USE_DEVICE_MODE - DCD_DEV dev; -#endif -#ifdef USE_HOST_MODE - HCD_DEV host; -#endif -#ifdef USE_OTG_MODE - OTG_DEV otg; -#endif -} -USB_OTG_CORE_HANDLE , *PUSB_OTG_CORE_HANDLE; - -/** - * @} - */ - - -/** @defgroup USB_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_FunctionsPrototype - * @{ - */ - - -USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID); -USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev); -void* USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev , - uint8_t *dest, - uint16_t len); -USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev , - uint8_t *src, - uint8_t ch_ep_num, - uint16_t len); -USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num); -USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev); - -uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev); -uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev); -uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_PhyInit (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev, - uint8_t mode); - -/*********************** HOST APIs ********************************************/ -#ifdef USE_HOST_MODE -USB_OTG_STS USB_OTG_CoreInitHost (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EnableHostInt (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); -USB_OTG_STS USB_OTG_HC_Halt (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); -USB_OTG_STS USB_OTG_HC_StartXfer (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); -USB_OTG_STS USB_OTG_HC_DoPing (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num); -uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ResetPort (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadHPRT0 (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state); -void USB_OTG_InitFSLSPClkSel (USB_OTG_CORE_HANDLE *pdev ,uint8_t freq); -uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) ; -void USB_OTG_StopHost (USB_OTG_CORE_HANDLE *pdev); -#endif -/********************* DEVICE APIs ********************************************/ -#ifdef USE_DEVICE_MODE -USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EnableDevInt (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev); -enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EP0Activate (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EPActivate (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPStartXfer (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPSetStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPClearStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -uint32_t USB_OTG_ReadDevAllOutEp_itr (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadDevOutEP_itr (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); -uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_InitDevSpeed (USB_OTG_CORE_HANDLE *pdev , uint8_t speed); -uint8_t USBH_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status); -uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep); -#endif -/** - * @} - */ - -#endif /* __USB_CORE_H__ */ - - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/Projects/discovery_demo/usbd_conf.h b/example/stm32f4/Projects/discovery_demo/usbd_conf.h deleted file mode 100644 index 3ff02b665..000000000 --- a/example/stm32f4/Projects/discovery_demo/usbd_conf.h +++ /dev/null @@ -1,93 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_conf.h - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief USB Device configuration file - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CONF__H__ -#define __USBD_CONF__H__ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4_discovery.h" - -/** @defgroup USB_CONF_Exported_Defines - * @{ - */ - - -#define USBD_CFG_MAX_NUM 1 -#define USBD_ITF_MAX_NUM 1 - -#define USB_MAX_STR_DESC_SIZ 64 - - - -#define USBD_DYNAMIC_DESCRIPTOR_CHANGE_ENABLED - -/** @defgroup USB_String_Descriptors - * @{ - */ - - -/** @defgroup USB_HID_Class_Layer_Parameter - * @{ - */ -#define HID_IN_EP 0x81 -#define HID_OUT_EP 0x01 - -#define HID_IN_PACKET 4 -#define HID_OUT_PACKET 4 - -/** - * @} - */ -/** @defgroup USB_CONF_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_CONF_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CONF_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CONF_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif //__USBD_CONF__H__ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/Projects/discovery_demo/usbd_desc.c b/example/stm32f4/Projects/discovery_demo/usbd_desc.c deleted file mode 100644 index ff9b6701b..000000000 --- a/example/stm32f4/Projects/discovery_demo/usbd_desc.c +++ /dev/null @@ -1,313 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_desc.c - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief This file provides the USBD descriptors and string formating method. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" -#include "usbd_desc.h" -#include "usbd_req.h" -#include "usbd_conf.h" -#include "usb_regs.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_DESC - * @brief USBD descriptors module - * @{ - */ - -/** @defgroup USBD_DESC_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_DESC_Private_Defines - * @{ - */ - -#define USBD_VID 0x0483 -#define USBD_PID 0x5710 - -#define USBD_LANGID_STRING 0x409 -#define USBD_MANUFACTURER_STRING "STMicroelectronics" - -#define USBD_PRODUCT_HS_STRING "Joystick in HS mode" -#define USBD_SERIALNUMBER_HS_STRING "00000000011B" - -#define USBD_PRODUCT_FS_STRING "Joystick in FS Mode" -#define USBD_SERIALNUMBER_FS_STRING "00000000011C" - -#define USBD_CONFIGURATION_HS_STRING "HID Config" -#define USBD_INTERFACE_HS_STRING "HID Interface" - -#define USBD_CONFIGURATION_FS_STRING "HID Config" -#define USBD_INTERFACE_FS_STRING "HID Interface" -/** - * @} - */ - - -/** @defgroup USBD_DESC_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_DESC_Private_Variables - * @{ - */ - -USBD_DEVICE USR_desc = -{ - USBD_USR_DeviceDescriptor, - USBD_USR_LangIDStrDescriptor, - USBD_USR_ManufacturerStrDescriptor, - USBD_USR_ProductStrDescriptor, - USBD_USR_SerialStrDescriptor, - USBD_USR_ConfigStrDescriptor, - USBD_USR_InterfaceStrDescriptor, - -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN uint8_t USBD_DeviceDesc[USB_SIZ_DEVICE_DESC] __ALIGN_END = - { - 0x12, /*bLength */ - USB_DEVICE_DESCRIPTOR_TYPE, /*bDescriptorType*/ - 0x00, /*bcdUSB */ - 0x02, - 0x00, /*bDeviceClass*/ - 0x00, /*bDeviceSubClass*/ - 0x00, /*bDeviceProtocol*/ - USB_OTG_MAX_EP0_SIZE, /*bMaxPacketSize*/ - LOBYTE(USBD_VID), /*idVendor*/ - HIBYTE(USBD_VID), /*idVendor*/ - LOBYTE(USBD_PID), /*idVendor*/ - HIBYTE(USBD_PID), /*idVendor*/ - 0x00, /*bcdDevice rel. 2.00*/ - 0x02, - USBD_IDX_MFC_STR, /*Index of manufacturer string*/ - USBD_IDX_PRODUCT_STR, /*Index of product string*/ - USBD_IDX_SERIAL_STR, /*Index of serial number string*/ - USBD_CFG_MAX_NUM /*bNumConfigurations*/ - } ; /* USB_DeviceDescriptor */ - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] __ALIGN_END = -{ - USB_LEN_DEV_QUALIFIER_DESC, - USB_DESC_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x01, - 0x00, -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB Standard Device Descriptor */ -__ALIGN_BEGIN uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID] __ALIGN_END = -{ - USB_SIZ_STRING_LANGID, - USB_DESC_TYPE_STRING, - LOBYTE(USBD_LANGID_STRING), - HIBYTE(USBD_LANGID_STRING), -}; -/** - * @} - */ - - -/** @defgroup USBD_DESC_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_DESC_Private_Functions - * @{ - */ - -/** -* @brief USBD_USR_DeviceDescriptor -* return the device descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length) -{ - *length = sizeof(USBD_DeviceDesc); - return USBD_DeviceDesc; -} - -/** -* @brief USBD_USR_LangIDStrDescriptor -* return the LangID string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length) -{ - *length = sizeof(USBD_LangIDDesc); - return USBD_LangIDDesc; -} - - -/** -* @brief USBD_USR_ProductStrDescriptor -* return the product string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_ProductStrDescriptor( uint8_t speed , uint16_t *length) -{ - - - if(speed == 0) - { - USBD_GetString (USBD_PRODUCT_HS_STRING, USBD_StrDesc, length); - } - else - { - USBD_GetString (USBD_PRODUCT_FS_STRING, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - -/** -* @brief USBD_USR_ManufacturerStrDescriptor -* return the manufacturer string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_ManufacturerStrDescriptor( uint8_t speed , uint16_t *length) -{ - USBD_GetString (USBD_MANUFACTURER_STRING, USBD_StrDesc, length); - return USBD_StrDesc; -} - -/** -* @brief USBD_USR_SerialStrDescriptor -* return the serial number string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length) -{ - if(speed == USB_OTG_SPEED_HIGH) - { - USBD_GetString (USBD_SERIALNUMBER_HS_STRING, USBD_StrDesc, length); - } - else - { - USBD_GetString (USBD_SERIALNUMBER_FS_STRING, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - -/** -* @brief USBD_USR_ConfigStrDescriptor -* return the configuration string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length) -{ - if(speed == USB_OTG_SPEED_HIGH) - { - USBD_GetString (USBD_CONFIGURATION_HS_STRING, USBD_StrDesc, length); - } - else - { - USBD_GetString (USBD_CONFIGURATION_FS_STRING, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - - -/** -* @brief USBD_USR_InterfaceStrDescriptor -* return the interface string descriptor -* @param speed : current device speed -* @param length : pointer to data length variable -* @retval pointer to descriptor buffer -*/ -uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length) -{ - if(speed == 0) - { - USBD_GetString (USBD_INTERFACE_HS_STRING, USBD_StrDesc, length); - } - else - { - USBD_GetString (USBD_INTERFACE_FS_STRING, USBD_StrDesc, length); - } - return USBD_StrDesc; -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/Projects/discovery_demo/usbd_desc.h b/example/stm32f4/Projects/discovery_demo/usbd_desc.h deleted file mode 100644 index ed999dc62..000000000 --- a/example/stm32f4/Projects/discovery_demo/usbd_desc.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_desc.h - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief header file for the usbd_desc.c file - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USB_DESC_H -#define __USB_DESC_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USB_DESC - * @brief general defines for the usb device library file - * @{ - */ - -/** @defgroup USB_DESC_Exported_Defines - * @{ - */ -#define USB_DEVICE_DESCRIPTOR_TYPE 0x01 -#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02 -#define USB_STRING_DESCRIPTOR_TYPE 0x03 -#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04 -#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05 -#define USB_SIZ_DEVICE_DESC 18 -#define USB_SIZ_STRING_LANGID 4 - -/** - * @} - */ - - -/** @defgroup USBD_DESC_Exported_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_DESC_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_Variables - * @{ - */ -extern uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC]; -extern uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ]; -extern uint8_t USBD_OtherSpeedCfgDesc[USB_LEN_CFG_DESC]; -extern uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC]; -extern uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID]; -extern USBD_DEVICE USR_desc; -/** - * @} - */ - -/** @defgroup USBD_DESC_Exported_FunctionsPrototype - * @{ - */ - - -uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_ManufacturerStrDescriptor ( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_ProductStrDescriptor ( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length); -uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length); - -#ifdef USB_SUPPORT_USER_STRING_DESC -uint8_t * USBD_USR_USRStringDesc (uint8_t speed, uint8_t idx , uint16_t *length); -#endif /* USB_SUPPORT_USER_STRING_DESC */ - -/** - * @} - */ - -#endif /* __USBD_DESC_H */ - -/** - * @} - */ - -/** -* @} -*/ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Projects/discovery_demo/usbd_usr.c b/example/stm32f4/Projects/discovery_demo/usbd_usr.c deleted file mode 100644 index 6ebd1579d..000000000 --- a/example/stm32f4/Projects/discovery_demo/usbd_usr.c +++ /dev/null @@ -1,238 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_usr.c - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief This file includes the user application layer - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_usr.h" -#include "usbd_ioreq.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY -* @{ -*/ - -/** @defgroup USBD_USR -* @brief This file includes the user application layer -* @{ -*/ - -/** @defgroup USBD_USR_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBD_USR_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBD_USR_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBD_USR_Private_Variables -* @{ -*/ - -USBD_Usr_cb_TypeDef USR_cb = -{ - USBD_USR_Init, - USBD_USR_DeviceReset, - USBD_USR_DeviceConfigured, - USBD_USR_DeviceSuspended, - USBD_USR_DeviceResumed, - - USBD_USR_DeviceConnected, - USBD_USR_DeviceDisconnected, - - -}; - - - -/** -* @} -*/ - -/** @defgroup USBD_USR_Private_Constants -* @{ -*/ - -/** -* @} -*/ - - - -/** @defgroup USBD_USR_Private_FunctionPrototypes -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBD_USR_Private_Functions -* @{ -*/ - -/** -* @brief USBD_USR_Init -* Displays the message on LCD for host lib initialization -* @param None -* @retval None -*/ -void USBD_USR_Init(void) -{ - /* Setup SysTick Timer for 40 msec interrupts - This interrupt is used to probe the joystick */ - if (SysTick_Config(SystemCoreClock / 24)) - { - /* Capture error */ - while (1); - } -} - -/** -* @brief USBD_USR_DeviceReset -* Displays the message on LCD on device Reset Event -* @param speed : device speed -* @retval None -*/ -void USBD_USR_DeviceReset(uint8_t speed ) -{ - switch (speed) - { - case USB_OTG_SPEED_HIGH: - break; - - case USB_OTG_SPEED_FULL: - break; - default: - break; - - } -} - - -/** -* @brief USBD_USR_DeviceConfigured -* Displays the message on LCD on device configuration Event -* @param None -* @retval Staus -*/ -void USBD_USR_DeviceConfigured (void) -{ -} - - -/** -* @brief USBD_USR_DeviceConnected -* Displays the message on LCD on device connection Event -* @param None -* @retval Staus -*/ -void USBD_USR_DeviceConnected (void) -{ -} - - -/** -* @brief USBD_USR_DeviceDisonnected -* Displays the message on LCD on device disconnection Event -* @param None -* @retval Staus -*/ -void USBD_USR_DeviceDisconnected (void) -{ -} - -/** -* @brief USBD_USR_DeviceSuspended -* Displays the message on LCD on device suspend Event -* @param None -* @retval None -*/ -void USBD_USR_DeviceSuspended(void) -{ - /* Users can do their application actions here for the USB-Reset */ -} - - -/** -* @brief USBD_USR_DeviceResumed -* Displays the message on LCD on device resume Event -* @param None -* @retval None -*/ -void USBD_USR_DeviceResumed(void) -{ - /* Users can do their application actions here for the USB-Reset */ -} - -/** -* @} -*/ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/build/Makefile b/example/stm32f4/STM32F4xx_StdPeriph_Driver/build/Makefile deleted file mode 100644 index 1506b0ed3..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/build/Makefile +++ /dev/null @@ -1,60 +0,0 @@ -LIB = libSTM32F4xx_StdPeriph_Driver.a - -CC = arm-none-eabi-gcc -AR = arm-none-eabi-ar -RANLIB = arm-none-eabi-ranlib - -CFLAGS = -Wall -O2 -mlittle-endian -mthumb -CFLAGS += -mcpu=cortex-m4 -ffreestanding -nostdlib -CFLAGS += -I../inc -I../inc/device_support -I../inc/core_support - -SRCS = \ -../src/misc.c \ -../src/stm32f4xx_adc.c \ -../src/stm32f4xx_can.c \ -../src/stm32f4xx_crc.c \ -../src/stm32f4xx_cryp_aes.c \ -../src/stm32f4xx_cryp_des.c \ -../src/stm32f4xx_cryp_tdes.c \ -../src/stm32f4xx_cryp_des.c \ -../src/stm32f4xx_dac.c \ -../src/stm32f4xx_dbgmcu.c \ -../src/stm32f4xx_dcmi.c \ -../src/stm32f4xx_dma.c \ -../src/stm32f4xx_exti.c \ -../src/stm32f4xx_flash.c \ -../src/stm32f4xx_fsmc.c \ -../src/stm32f4xx_gpio.c \ -../src/stm32f4xx_hash_md5.c \ -../src/stm32f4xx_hash_sha1.c \ -../src/stm32f4xx_hash.c \ -../src/stm32f4xx_i2c.c \ -../src/stm32f4xx_iwdg.c \ -../src/stm32f4xx_pwr.c \ -../src/stm32f4xx_rcc.c \ -../src/stm32f4xx_rng.c \ -../src/stm32f4xx_rtc.c \ -../src/stm32f4xx_sdio.c \ -../src/stm32f4xx_spi.c \ -../src/stm32f4xx_syscfg.c \ -../src/stm32f4xx_tim.c \ -../src/stm32f4xx_usart.c \ -../src/stm32f4xx_wwdg.c \ -#../inc/core_support/core_cm4.c - -OBJS = $(SRCS:.c=.o) - -all: $(LIB) - -$(LIB): $(OBJS) - $(AR) -r $(LIB) $(OBJS) - $(RANLIB) $(LIB) - -%.o : %.c - $(CC) $(CFLAGS) -c -o $@ $^ - -clean: - -rm -f $(OBJS) - -rm -f $(LIB) - -.PHONY: all clean diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/arm_common_tables.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/arm_common_tables.h deleted file mode 100644 index 7245c4f12..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/arm_common_tables.h +++ /dev/null @@ -1,35 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 11. November 2010 -* $Revision: V1.0.2 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern uint16_t armBitRevTable[256]; -extern q15_t armRecipTableQ15[64]; -extern q31_t armRecipTableQ31[64]; -extern const q31_t realCoefAQ31[1024]; -extern const q31_t realCoefBQ31[1024]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/arm_math.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/arm_math.h deleted file mode 100644 index ffa03b6fd..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/arm_math.h +++ /dev/null @@ -1,7051 +0,0 @@ -/* ---------------------------------------------------------------------- - * Copyright (C) 2010 ARM Limited. All rights reserved. - * - * $Date: 15. July 2011 - * $Revision: V1.0.10 - * - * Project: CMSIS DSP Library - * Title: arm_math.h - * - * Description: Public header file for CMSIS DSP Library - * - * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 - * - * Version 1.0.10 2011/7/15 - * Big Endian support added and Merged M0 and M3/M4 Source code. - * - * Version 1.0.3 2010/11/29 - * Re-organized the CMSIS folders and updated documentation. - * - * Version 1.0.2 2010/11/11 - * Documentation updated. - * - * Version 1.0.1 2010/10/05 - * Production release and review comments incorporated. - * - * Version 1.0.0 2010/09/20 - * Production release and review comments incorporated. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of modules each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Processor Support - * - * The library is completely written in C and is fully CMSIS compliant. - * High performance is achieved through maximum use of Cortex-M4 intrinsics. - * - * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor, - * with the DSP intrinsics being emulated through software. - * - * - * Toolchain Support - * - * The library has been developed and tested with MDK-ARM version 4.21. - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Using the Library - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 depending on the target processor in the application. - * - * Examples - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Building the Library - * - * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\DSP_Lib\Source\ARM folder. - * - arm_cortexM0b_math.uvproj - * - arm_cortexM0l_math.uvproj - * - arm_cortexM3b_math.uvproj - * - arm_cortexM3l_math.uvproj - * - arm_cortexM4b_math.uvproj - * - arm_cortexM4l_math.uvproj - * - arm_cortexM4bf_math.uvproj - * - arm_cortexM4lf_math.uvproj - * - * Each library project have differant pre-processor macros. - * - * ARM_MATH_CMx: - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target. - * - * ARM_MATH_BIG_ENDIAN: - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * ARM_MATH_MATRIX_CHECK: - * Define macro for checking on the input and output sizes of matrices - * - * ARM_MATH_ROUNDING: - * Define macro for rounding on support functions - * - * __FPU_PRESENT: - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - * - * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above. - * - * Copyright Notice - * - * Copyright (C) 2010 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the #define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" -#else -#include "ARMCM4.h" -#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" - #include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#define PI 3.14159265358979f - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x800000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#define __SIMD32(addr) (*(int32_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -#if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif - -#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) - - static __INLINE uint32_t __CLZ(q31_t data); - - - static __INLINE uint32_t __CLZ(q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return(count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0) - - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0 */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (char) x; - s = (char) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (char) x; - s = (char) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t)(((short) x * (short) (y >> 16)) - - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t)(((short) x * (short) (y >> 16)) + - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) y)) + - ((short) x * (short) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - - -#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t *pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t *pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t *pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - #ifdef ARM_MATH_CM0 - q15_t A1; - q15_t A2; - #else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ - #endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; - float32_t x1; - float32_t xSpacing; - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - - /** - * @brief Processing function for the Q15 CFFT/CIFFT. - * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Initialization function for the Q15 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Processing function for the Q31 CFFT/CIFFT. - * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Initialization function for the Q31 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Processing function for the floating-point CFFT/CIFFT. - * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Initialization function for the floating-point CFFT/CIFFT. - * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - - - /*---------------------------------------------------------------------- - * Internal functions prototypes FFT function - ----------------------------------------------------------------------*/ - - /** - * @brief Core function for the floating-point CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to the twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_f32( - float32_t * pSrc, - uint16_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier); - - /** - * @brief Core function for the floating-point CIFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @param[in] onebyfftLen value of 1/fftLen. - * @return none. - */ - - void arm_radix4_butterfly_inverse_f32( - float32_t * pSrc, - uint16_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier, - float32_t onebyfftLen); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftSize length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. - * @param[in] *pBitRevTab points to the bit reversal table. - * @return none. - */ - - void arm_bitreversal_f32( - float32_t *pSrc, - uint16_t fftSize, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Core function for the Q31 CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_q31( - q31_t *pSrc, - uint32_t fftLen, - q31_t *pCoef, - uint32_t twidCoefModifier); - - /** - * @brief Core function for the Q31 CIFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_inverse_q31( - q31_t * pSrc, - uint32_t fftLen, - q31_t * pCoef, - uint32_t twidCoefModifier); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table - * @param[in] *pBitRevTab points to bit reversal table. - * @return none. - */ - - void arm_bitreversal_q31( - q31_t * pSrc, - uint32_t fftLen, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Core function for the Q15 CFFT butterfly process. - * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef16 points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_q15( - q15_t *pSrc16, - uint32_t fftLen, - q15_t *pCoef16, - uint32_t twidCoefModifier); - - /** - * @brief Core function for the Q15 CIFFT butterfly process. - * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef16 points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_inverse_q15( - q15_t *pSrc16, - uint32_t fftLen, - q15_t *pCoef16, - uint32_t twidCoefModifier); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table - * @param[in] *pBitRevTab points to bit reversal table. - * @return none. - */ - - void arm_bitreversal_q15( - q15_t * pSrc, - uint32_t fftLen, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - /** - * @brief Processing function for the Q15 RFFT/RIFFT. - * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Initialization function for the Q15 RFFT/RIFFT. - * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Processing function for the Q31 RFFT/RIFFT. - * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Initialization function for the Q31 RFFT/RIFFT. - * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. - * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Initialization function for the floating-point RFFT/RIFFT. - * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. - * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Processing function for the floating-point RFFT/RIFFT. - * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t *pkCoeffs, - float32_t *pvCoeffs, - float32_t *pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t *pkCoeffs, - q31_t *pvCoeffs, - q31_t *pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t *pkCoeffs, - q15_t *pvCoeffs, - q15_t *pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t *pCoeffs, - q31_t *pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t *pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t *pSinVal, - float32_t *pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t *pSinVal, - q31_t *pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - - /* Implementation of PID controller */ - - #ifdef ARM_MATH_CM0 - - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0 )* in ; - - #else - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - #endif - - #ifdef ARM_MATH_CM0 - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0] ; - acc += (q31_t) S->A2 * S->state[1] ; - - #else - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc); - - #endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (x - S->x1) / xSpacing; - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if(i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues-1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i +1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData, - q31_t x, uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - static __INLINE arm_status arm_sqrt_f32( - float32_t in, float32_t *pOut) - { - if(in > 0) - { - -// #if __FPU_USED - #if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); - #else - *pOut = sqrtf(in); - #endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, q31_t *pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, q15_t *pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1)) - { - return(0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex-1) * S->numCols ; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex-1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - - - - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - - -/** - * - * End of file. - */ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cm0.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cm0.h deleted file mode 100644 index 9d7a19f9a..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cm0.h +++ /dev/null @@ -1,665 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - - -/** \mainpage CMSIS Cortex-M0 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks */ -#endif - -#include /*!< standard types definitions */ -#include "core_cmInstr.h" /*!< Core Instruction Access */ -#include "core_cmFunc.h" /*!< Core Function Access */ - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP - and not via processor. Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cm3.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cm3.c deleted file mode 100644 index fcff0d133..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cm3.c +++ /dev/null @@ -1,784 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V1.30 - * @date 30. October 2009 - * - * @note - * Copyright (C) 2009 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ################### Compiler specific Intrinsics ########################### */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__ARMCC_VERSION < 400000) - -/** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -__ASM void __CLREX(void) -{ - clrex -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} - -/** - * @brief Return the Control Register value - * - * @return Control value - * - * Return the content of the control register - */ -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} - -#endif /* __ARMCC_VERSION */ - - - -#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#pragma diag_suppress=Pe940 - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); - __ASM("bx lr"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit values) - */ -uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); - __ASM("bx lr"); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); - __ASM("bx lr"); -} - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -uint32_t __get_PSP(void) __attribute__( ( naked ) ); -uint32_t __get_PSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, psp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); -void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n\t" - "BX lr \n\t" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -uint32_t __get_MSP(void) __attribute__( ( naked ) ); -uint32_t __get_MSP(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, msp\n\t" - "MOV r0, %0 \n\t" - "BX lr \n\t" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); -void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n\t" - "BX lr \n\t" : : "r" (topOfMainStack) ); -} - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -uint32_t __get_BASEPRI(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -uint32_t __get_FAULTMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** - * @brief Reverse byte order in integer value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in unsigned short value - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -uint32_t __RBIT(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result=0; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result=0; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cm3.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cm3.h deleted file mode 100644 index 1c688181a..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cm3.h +++ /dev/null @@ -1,1236 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - - -/** \mainpage CMSIS Cortex-M3 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks */ -#endif - -#include /*!< standard types definitions */ -#include "core_cmInstr.h" /*!< Core Instruction Access */ -#include "core_cmFunc.h" /*!< Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB - Type definitions for the Cortex-M System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM CMSIS ITM - Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ -#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU CMSIS MPU - Type definitions for the Cortex-M Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Type definitions for the Cortex-M Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/** \brief Set Priority Grouping - - This function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - This function gets the priority grouping from NVIC Interrupt Controller. - Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - - \return Priority grouping field - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - This function reads the active register in NVIC and returns the active bit. - \param [in] IRQn Number of the interrupt for get active - \return 0 Interrupt status is not active - \return 1 Interrupt status is active - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - This function encodes the priority for an interrupt with the given priority group, - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The returned priority value can be used for NVIC_SetPriority(...) function - - \param [in] PriorityGroup Used priority group - \param [in] PreemptPriority Preemptive priority value (starting from 0) - \param [in] SubPriority Sub priority value (starting from 0) - \return Encoded priority for the interrupt - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - This function decodes an interrupt priority value with the given priority group to - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The priority value can be retrieved with NVIC_GetPriority(...) function - - \param [in] Priority Priority value - \param [in] PriorityGroup Used priority group - \param [out] pPreemptPriority Preemptive priority value (starting from 0) - \param [out] pSubPriority Sub priority value (starting from 0) - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** \brief ITM Send Character - - This function transmits a character via the ITM channel 0. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \param [in] ch Character to transmit - \return Character to transmit - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - This function inputs a character via external variable ITM_RxBuffer. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \return Received character - \return -1 No character received - */ -static __INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - This function checks external variable ITM_RxBuffer whether a character is available or not. - It returns '1' if a character is available and '0' if no character is available. - - \return 0 No character available - \return 1 Character available - */ -static __INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cm4.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cm4.h deleted file mode 100644 index bf022ba67..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cm4.h +++ /dev/null @@ -1,1378 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - - -/** \mainpage CMSIS Cortex-M4 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - Cortex-M SIMD instructions - - The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks to define __FPU_USED */ - #define __FPU_USED 0 -#endif - -#include /*!< standard types definitions */ -#include /*!< Core Instruction Access */ -#include /*!< Core Function Access */ -#include /*!< Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB - Type definitions for the Cortex-M System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM CMSIS ITM - Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ -#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU CMSIS MPU - Type definitions for the Cortex-M Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU CMSIS FPU - Type definitions for the Cortex-M Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Type definitions for the Cortex-M Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/** \brief Set Priority Grouping - - This function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - This function gets the priority grouping from NVIC Interrupt Controller. - Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - - \return Priority grouping field - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - This function reads the active register in NVIC and returns the active bit. - \param [in] IRQn Number of the interrupt for get active - \return 0 Interrupt status is not active - \return 1 Interrupt status is active - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - This function encodes the priority for an interrupt with the given priority group, - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The returned priority value can be used for NVIC_SetPriority(...) function - - \param [in] PriorityGroup Used priority group - \param [in] PreemptPriority Preemptive priority value (starting from 0) - \param [in] SubPriority Sub priority value (starting from 0) - \return Encoded priority for the interrupt - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - This function decodes an interrupt priority value with the given priority group to - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The priority value can be retrieved with NVIC_GetPriority(...) function - - \param [in] Priority Priority value - \param [in] PriorityGroup Used priority group - \param [out] pPreemptPriority Preemptive priority value (starting from 0) - \param [out] pSubPriority Sub priority value (starting from 0) - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** \brief ITM Send Character - - This function transmits a character via the ITM channel 0. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \param [in] ch Character to transmit - \return Character to transmit - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - This function inputs a character via external variable ITM_RxBuffer. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \return Received character - \return -1 No character received - */ -static __INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - This function checks external variable ITM_RxBuffer whether a character is available or not. - It returns '1' if a character is available and '0' if no character is available. - - \return 0 No character available - \return 1 Character available - */ -static __INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cm4_simd.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cm4_simd.h deleted file mode 100644 index e7b676522..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cm4_simd.h +++ /dev/null @@ -1,701 +0,0 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2010-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - -/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/ -/* intrinsic __SADD8 see intrinsics.h */ -/* intrinsic __QADD8 see intrinsics.h */ -/* intrinsic __SHADD8 see intrinsics.h */ -/* intrinsic __UADD8 see intrinsics.h */ -/* intrinsic __UQADD8 see intrinsics.h */ -/* intrinsic __UHADD8 see intrinsics.h */ -/* intrinsic __SSUB8 see intrinsics.h */ -/* intrinsic __QSUB8 see intrinsics.h */ -/* intrinsic __SHSUB8 see intrinsics.h */ -/* intrinsic __USUB8 see intrinsics.h */ -/* intrinsic __UQSUB8 see intrinsics.h */ -/* intrinsic __UHSUB8 see intrinsics.h */ -/* intrinsic __SADD16 see intrinsics.h */ -/* intrinsic __QADD16 see intrinsics.h */ -/* intrinsic __SHADD16 see intrinsics.h */ -/* intrinsic __UADD16 see intrinsics.h */ -/* intrinsic __UQADD16 see intrinsics.h */ -/* intrinsic __UHADD16 see intrinsics.h */ -/* intrinsic __SSUB16 see intrinsics.h */ -/* intrinsic __QSUB16 see intrinsics.h */ -/* intrinsic __SHSUB16 see intrinsics.h */ -/* intrinsic __USUB16 see intrinsics.h */ -/* intrinsic __UQSUB16 see intrinsics.h */ -/* intrinsic __UHSUB16 see intrinsics.h */ -/* intrinsic __SASX see intrinsics.h */ -/* intrinsic __QASX see intrinsics.h */ -/* intrinsic __SHASX see intrinsics.h */ -/* intrinsic __UASX see intrinsics.h */ -/* intrinsic __UQASX see intrinsics.h */ -/* intrinsic __UHASX see intrinsics.h */ -/* intrinsic __SSAX see intrinsics.h */ -/* intrinsic __QSAX see intrinsics.h */ -/* intrinsic __SHSAX see intrinsics.h */ -/* intrinsic __USAX see intrinsics.h */ -/* intrinsic __UQSAX see intrinsics.h */ -/* intrinsic __UHSAX see intrinsics.h */ -/* intrinsic __USAD8 see intrinsics.h */ -/* intrinsic __USADA8 see intrinsics.h */ -/* intrinsic __SSAT16 see intrinsics.h */ -/* intrinsic __USAT16 see intrinsics.h */ -/* intrinsic __UXTB16 see intrinsics.h */ -/* intrinsic __SXTB16 see intrinsics.h */ -/* intrinsic __UXTAB16 see intrinsics.h */ -/* intrinsic __SXTAB16 see intrinsics.h */ -/* intrinsic __SMUAD see intrinsics.h */ -/* intrinsic __SMUADX see intrinsics.h */ -/* intrinsic __SMLAD see intrinsics.h */ -/* intrinsic __SMLADX see intrinsics.h */ -/* intrinsic __SMLALD see intrinsics.h */ -/* intrinsic __SMLALDX see intrinsics.h */ -/* intrinsic __SMUSD see intrinsics.h */ -/* intrinsic __SMUSDX see intrinsics.h */ -/* intrinsic __SMLSD see intrinsics.h */ -/* intrinsic __SMLSDX see intrinsics.h */ -/* intrinsic __SMLSLD see intrinsics.h */ -/* intrinsic __SMLSLDX see intrinsics.h */ -/* intrinsic __SEL see intrinsics.h */ -/* intrinsic __QADD see intrinsics.h */ -/* intrinsic __QSUB see intrinsics.h */ -/* intrinsic __PKHBT see intrinsics.h */ -/* intrinsic __PKHTB see intrinsics.h */ - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLALD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLALDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLSLD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLSLDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -/* not yet supported */ -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CORE_CM4_SIMD_H */ - -#ifdef __cplusplus -} -#endif diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cmFunc.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cmFunc.h deleted file mode 100644 index 88819f9dd..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cmFunc.h +++ /dev/null @@ -1,609 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V2.10 - * @date 26. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -static __INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -static __INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -static __INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cmInstr.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cmInstr.h deleted file mode 100644 index 78d2ef80b..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/core_support/core_cmInstr.h +++ /dev/null @@ -1,585 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -static __INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -static __INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/device_support/stm32f4_discovery.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/device_support/stm32f4_discovery.h deleted file mode 100644 index c6fec4221..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/device_support/stm32f4_discovery.h +++ /dev/null @@ -1,158 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4_discovery.h - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief This file contains definitions for STM32F4-Discovery Kit's Leds and - * push-button hardware resources. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4_DISCOVERY_H -#define __STM32F4_DISCOVERY_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ - #include "stm32f4xx.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL - * @{ - */ - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Types - * @{ - */ -typedef enum -{ - LED4 = 0, - LED3 = 1, - LED5 = 2, - LED6 = 3 -} Led_TypeDef; - -typedef enum -{ - BUTTON_USER = 0, -} Button_TypeDef; - -typedef enum -{ - BUTTON_MODE_GPIO = 0, - BUTTON_MODE_EXTI = 1 -} ButtonMode_TypeDef; -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_LED - * @{ - */ -#define LEDn 4 - -#define LED4_PIN GPIO_Pin_12 -#define LED4_GPIO_PORT GPIOD -#define LED4_GPIO_CLK RCC_AHB1Periph_GPIOD - -#define LED3_PIN GPIO_Pin_13 -#define LED3_GPIO_PORT GPIOD -#define LED3_GPIO_CLK RCC_AHB1Periph_GPIOD - -#define LED5_PIN GPIO_Pin_14 -#define LED5_GPIO_PORT GPIOD -#define LED5_GPIO_CLK RCC_AHB1Periph_GPIOD - -#define LED6_PIN GPIO_Pin_15 -#define LED6_GPIO_PORT GPIOD -#define LED6_GPIO_CLK RCC_AHB1Periph_GPIOD -/** - * @} - */ - -/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_BUTTON - * @{ - */ -#define BUTTONn 1 - -/** - * @brief Wakeup push-button - */ -#define USER_BUTTON_PIN GPIO_Pin_0 -#define USER_BUTTON_GPIO_PORT GPIOA -#define USER_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOA -#define USER_BUTTON_EXTI_LINE EXTI_Line0 -#define USER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA -#define USER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0 -#define USER_BUTTON_EXTI_IRQn EXTI0_IRQn -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Functions - * @{ - */ -void STM_EVAL_LEDInit(Led_TypeDef Led); -void STM_EVAL_LEDOn(Led_TypeDef Led); -void STM_EVAL_LEDOff(Led_TypeDef Led); -void STM_EVAL_LEDToggle(Led_TypeDef Led); -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode); -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4_DISCOVERY_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/device_support/stm32f4xx.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/device_support/stm32f4xx.h deleted file mode 100644 index db5d1e470..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/device_support/stm32f4xx.h +++ /dev/null @@ -1,7017 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx.h - * @author MCD Application Team - * @version V1.0.0 - * @date 30-September-2011 - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F4xx devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripherals drivers in application code(i.e. - * code will be based on direct access to peripherals registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripherals registers hardware - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx - * @{ - */ - -#ifndef __STM32F4xx_H -#define __STM32F4xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -#ifdef USE_FULL_ASSERT - -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0) -#endif /* USE_FULL_ASSERT */ - - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F4XX) - #define STM32F4XX -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (STM32F4XX) - #error "Please select first the target STM32F4XX device used in your application (in stm32f4xx.h file)" -#endif - -#if !defined (USE_STDPERIPH_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ - -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ -#endif /* HSE_STARTUP_TIMEOUT */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief STM32F4XX Standard Peripherals Library version number V1.0.0 - */ -#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ -#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F4XX_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ - -/** - * @brief STM32F4XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ - DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ - DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ - DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - FPU_IRQn = 81 /*!< FPU global interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ -#include "system_stm32f4xx.h" -#include - -/** @addtogroup Exported_types - * @{ - */ -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - AND triple modes, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA stream x configuration register */ - __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ - __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ -} DMA_Stream_TypeDef; - -typedef struct -{ - __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ - __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ - __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ - __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ -} DMA_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - __IO uint32_t RESERVED8; - __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - __IO uint32_t DMARSWTR; - uint32_t RESERVED10[8]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ -} FLASH_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ - __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ -} GPIO_TypeDef; - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ - uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ - uint32_t RESERVED2; /*!< Reserved, 0x3C */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ - uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ - __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ - __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ - __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ - uint32_t RESERVED4; /*!< Reserved, 0x5C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ - uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - uint16_t RESERVED11; /*!< Reserved, 0x46 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ - uint16_t RESERVED14; /*!< Reserved, 0x52 */ -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief Crypto Processor - */ - -typedef struct -{ - __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ - __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ - __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ - __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ - __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ - __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ - __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ - __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ - __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ - __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ - __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ - __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ - __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ - __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ - __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ - __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ - __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ - __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ -} CRYP_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ - __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ - __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ - __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ - __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ - uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ - __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ -} HASH_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ -#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ -#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ -#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ -#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ - -#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ -#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ -#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ - -/* Legacy defines */ -#define SRAM_BASE SRAM1_BASE -#define SRAM_BB_BASE SRAM1_BB_BASE - - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) - -/*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300) -#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) - -/*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -/*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) -#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) -#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) - -/*!< FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) - -/* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t )0xE0042000) - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) -#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) -#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) -#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) -#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) -#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) -#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) -#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) -#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) -#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) -#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) -#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) -#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) -#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define CRYP ((CRYP_TypeDef *) CRYP_BASE) -#define HASH ((HASH_TypeDef *) HASH_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!
© COPYRIGHT 2011 STMicroelectronics
- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F4XX_H -#define __SYSTEM_STM32F4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F4xx_System_Exported_types - * @{ - */ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/misc.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/misc.h deleted file mode 100644 index 8030e67dd..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/misc.h +++ /dev/null @@ -1,172 +0,0 @@ -/** - ****************************************************************************** - * @file misc.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MISC_H -#define __MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be an enumerator of @ref IRQn_Type - enumeration (For the complete STM32 Devices IRQ Channels - list, please refer to stm32f4xx.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table - A lower priority value indicates a higher priority */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table - A lower priority value indicates a higher priority */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup MISC_Vector_Table_Base - * @{ - */ - -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup MISC_System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup MISC_Preemption_Priority_Group - * @{ - */ - -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) - -/** - * @} - */ - -/** @defgroup MISC_SysTick_clock_source - * @{ - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h deleted file mode 100644 index a4a0986da..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h +++ /dev/null @@ -1,643 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_adc.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the ADC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_ADC_H -#define __STM32F4xx_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief ADC Init structure definition - */ -typedef struct -{ - uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. - This parameter can be a value of @ref ADC_resolution */ - FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion - is performed in Scan (multichannels) - or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion - is performed in Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and - enable the trigger of a regular group. - This parameter can be a value of - @ref ADC_external_trigger_edge_for_regular_channels_conversion */ - uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger - the start of conversion of a regular group. - This parameter can be a value of - @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */ - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment - is left or right. This parameter can be - a value of @ref ADC_data_align */ - uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions - that will be done using the sequencer for - regular channel group. - This parameter must range from 1 to 16. */ -}ADC_InitTypeDef; - -/** - * @brief ADC Common Init structure definition - */ -typedef struct -{ - uint32_t ADC_Mode; /*!< Configures the ADC to operate in - independent or multi mode. - This parameter can be a value of @ref ADC_Common_mode */ - uint32_t ADC_Prescaler; /*!< Select the frequency of the clock - to the ADC. The clock is common for all the ADCs. - This parameter can be a value of @ref ADC_Prescaler */ - uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access - mode for multi ADC mode. - This parameter can be a value of - @ref ADC_Direct_memory_access_mode_for_multi_mode */ - uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. - This parameter can be a value of - @ref ADC_delay_between_2_sampling_phases */ - -}ADC_CommonInitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants - * @{ - */ -#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC2) || \ - ((PERIPH) == ADC3)) - -/** @defgroup ADC_Common_mode - * @{ - */ -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) -#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) -#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) -#define ADC_DualMode_RegSimult ((uint32_t)0x00000006) -#define ADC_DualMode_Interl ((uint32_t)0x00000007) -#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) -#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) -#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) -#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) -#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) -#define ADC_TripleMode_Interl ((uint32_t)0x00000017) -#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) -#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ - ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ - ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_DualMode_InjecSimult) || \ - ((MODE) == ADC_DualMode_RegSimult) || \ - ((MODE) == ADC_DualMode_Interl) || \ - ((MODE) == ADC_DualMode_AlterTrig) || \ - ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ - ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_TripleMode_InjecSimult) || \ - ((MODE) == ADC_TripleMode_RegSimult) || \ - ((MODE) == ADC_TripleMode_Interl) || \ - ((MODE) == ADC_TripleMode_AlterTrig)) -/** - * @} - */ - - -/** @defgroup ADC_Prescaler - * @{ - */ -#define ADC_Prescaler_Div2 ((uint32_t)0x00000000) -#define ADC_Prescaler_Div4 ((uint32_t)0x00010000) -#define ADC_Prescaler_Div6 ((uint32_t)0x00020000) -#define ADC_Prescaler_Div8 ((uint32_t)0x00030000) -#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \ - ((PRESCALER) == ADC_Prescaler_Div4) || \ - ((PRESCALER) == ADC_Prescaler_Div6) || \ - ((PRESCALER) == ADC_Prescaler_Div8)) -/** - * @} - */ - - -/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode - * @{ - */ -#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ -#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ -#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ -#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ -#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ - ((MODE) == ADC_DMAAccessMode_1) || \ - ((MODE) == ADC_DMAAccessMode_2) || \ - ((MODE) == ADC_DMAAccessMode_3)) - -/** - * @} - */ - - -/** @defgroup ADC_delay_between_2_sampling_phases - * @{ - */ -#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) -#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) -#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) -#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) -#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) -#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) -#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) -#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) -#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) -#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) -#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) -#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) -#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) -#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) -#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) -#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) -#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) - -/** - * @} - */ - - -/** @defgroup ADC_resolution - * @{ - */ -#define ADC_Resolution_12b ((uint32_t)0x00000000) -#define ADC_Resolution_10b ((uint32_t)0x01000000) -#define ADC_Resolution_8b ((uint32_t)0x02000000) -#define ADC_Resolution_6b ((uint32_t)0x03000000) -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ - ((RESOLUTION) == ADC_Resolution_10b) || \ - ((RESOLUTION) == ADC_Resolution_8b) || \ - ((RESOLUTION) == ADC_Resolution_6b)) - -/** - * @} - */ - - -/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion - * @{ - */ -#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) -#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) -#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) -#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) -/** - * @} - */ - - -/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion - * @{ - */ -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) -#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) -#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) -#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) -#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) -#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) -#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) -#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) -#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) -#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) -#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) -/** - * @} - */ - - -/** @defgroup ADC_data_align - * @{ - */ -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - - -/** @defgroup ADC_channels - * @{ - */ -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) -#define ADC_Channel_18 ((uint8_t)0x12) - -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) -#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \ - ((CHANNEL) == ADC_Channel_1) || \ - ((CHANNEL) == ADC_Channel_2) || \ - ((CHANNEL) == ADC_Channel_3) || \ - ((CHANNEL) == ADC_Channel_4) || \ - ((CHANNEL) == ADC_Channel_5) || \ - ((CHANNEL) == ADC_Channel_6) || \ - ((CHANNEL) == ADC_Channel_7) || \ - ((CHANNEL) == ADC_Channel_8) || \ - ((CHANNEL) == ADC_Channel_9) || \ - ((CHANNEL) == ADC_Channel_10) || \ - ((CHANNEL) == ADC_Channel_11) || \ - ((CHANNEL) == ADC_Channel_12) || \ - ((CHANNEL) == ADC_Channel_13) || \ - ((CHANNEL) == ADC_Channel_14) || \ - ((CHANNEL) == ADC_Channel_15) || \ - ((CHANNEL) == ADC_Channel_16) || \ - ((CHANNEL) == ADC_Channel_17) || \ - ((CHANNEL) == ADC_Channel_18)) -/** - * @} - */ - - -/** @defgroup ADC_sampling_times - * @{ - */ -#define ADC_SampleTime_3Cycles ((uint8_t)0x00) -#define ADC_SampleTime_15Cycles ((uint8_t)0x01) -#define ADC_SampleTime_28Cycles ((uint8_t)0x02) -#define ADC_SampleTime_56Cycles ((uint8_t)0x03) -#define ADC_SampleTime_84Cycles ((uint8_t)0x04) -#define ADC_SampleTime_112Cycles ((uint8_t)0x05) -#define ADC_SampleTime_144Cycles ((uint8_t)0x06) -#define ADC_SampleTime_480Cycles ((uint8_t)0x07) -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \ - ((TIME) == ADC_SampleTime_15Cycles) || \ - ((TIME) == ADC_SampleTime_28Cycles) || \ - ((TIME) == ADC_SampleTime_56Cycles) || \ - ((TIME) == ADC_SampleTime_84Cycles) || \ - ((TIME) == ADC_SampleTime_112Cycles) || \ - ((TIME) == ADC_SampleTime_144Cycles) || \ - ((TIME) == ADC_SampleTime_480Cycles)) -/** - * @} - */ - - -/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion - * @{ - */ -#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) -#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) -#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) -#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) - -/** - * @} - */ - - -/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion - * @{ - */ -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) -#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) -#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) -#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) -#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) -#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) -#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) -#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) -#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) -#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) -#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) -/** - * @} - */ - - -/** @defgroup ADC_injected_channel_selection - * @{ - */ -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) -#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ - ((CHANNEL) == ADC_InjectedChannel_2) || \ - ((CHANNEL) == ADC_InjectedChannel_3) || \ - ((CHANNEL) == ADC_InjectedChannel_4)) -/** - * @} - */ - - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) -#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_None)) -/** - * @} - */ - - -/** @defgroup ADC_interrupts_definition - * @{ - */ -#define ADC_IT_EOC ((uint16_t)0x0205) -#define ADC_IT_AWD ((uint16_t)0x0106) -#define ADC_IT_JEOC ((uint16_t)0x0407) -#define ADC_IT_OVR ((uint16_t)0x201A) -#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ - ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) -/** - * @} - */ - - -/** @defgroup ADC_flags_definition - * @{ - */ -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) -#define ADC_FLAG_OVR ((uint8_t)0x20) - -#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \ - ((FLAG) == ADC_FLAG_EOC) || \ - ((FLAG) == ADC_FLAG_JEOC) || \ - ((FLAG)== ADC_FLAG_JSTRT) || \ - ((FLAG) == ADC_FLAG_STRT) || \ - ((FLAG)== ADC_FLAG_OVR)) -/** - * @} - */ - - -/** @defgroup ADC_thresholds - * @{ - */ -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) -/** - * @} - */ - - -/** @defgroup ADC_injected_offset - * @{ - */ -#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) -/** - * @} - */ - - -/** @defgroup ADC_injected_length - * @{ - */ -#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) -/** - * @} - */ - - -/** @defgroup ADC_injected_rank - * @{ - */ -#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) -/** - * @} - */ - - -/** @defgroup ADC_regular_length - * @{ - */ -#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) -/** - * @} - */ - - -/** @defgroup ADC_regular_rank - * @{ - */ -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) -/** - * @} - */ - - -/** @defgroup ADC_regular_discontinuous_mode_number - * @{ - */ -#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the ADC configuration to the default reset state *****/ -void ADC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -/* Analog Watchdog configuration functions ************************************/ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); - -/* Temperature Sensor, Vrefint and VBAT management functions ******************/ -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -void ADC_VBATCmd(FunctionalState NewState); - -/* Regular Channels Configuration functions ***********************************/ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_SoftwareStartConv(ADC_TypeDef* ADCx); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); -void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); -uint32_t ADC_GetMultiModeConversionValue(void); - -/* Regular Channels DMA Configuration functions *******************************/ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState); - -/* Injected channels Configuration functions **********************************/ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); -void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); - -/* Interrupts and flags management functions **********************************/ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h deleted file mode 100644 index 3cb8da0d5..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h +++ /dev/null @@ -1,638 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_can.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the CAN firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_CAN_H -#define __STM32F4xx_CAN_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CAN - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ - ((PERIPH) == CAN2)) - -/** - * @brief CAN init structure definition - */ -typedef struct -{ - uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. - It ranges from 1 to 1024. */ - - uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit - Segment 1. This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_InitTypeDef; - -/** - * @brief CAN filter init structure definition - */ -typedef struct -{ - uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ - - uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint8_t CAN_FilterScale; /*!< Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_FilterInitTypeDef; - -/** - * @brief CAN Tx message structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be transmitted. This parameter can be a value - of @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the message that will - be transmitted. This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be - transmitted. This parameter can be a value between - 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 - to 0xFF. */ -} CanTxMsg; - -/** - * @brief CAN Rx message structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be received. This parameter can be a value of - @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to - 0xFF. */ - - uint8_t FMI; /*!< Specifies the index of the filter the message stored in - the mailbox passes through. This parameter can be a - value between 0 to 0xFF */ -} CanRxMsg; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CAN_Exported_Constants - * @{ - */ - -/** @defgroup CAN_InitStatus - * @{ - */ - -#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ - - -/* Legacy defines */ -#define CANINITFAILED CAN_InitStatus_Failed -#define CANINITOK CAN_InitStatus_Success -/** - * @} - */ - -/** @defgroup CAN_operating_mode - * @{ - */ - -#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ -#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ -#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ -#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ - ((MODE) == CAN_Mode_LoopBack)|| \ - ((MODE) == CAN_Mode_Silent) || \ - ((MODE) == CAN_Mode_Silent_LoopBack)) -/** - * @} - */ - - - /** - * @defgroup CAN_operating_mode - * @{ - */ -#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ -#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ -#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ - - -#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ - ((MODE) == CAN_OperatingMode_Normal)|| \ - ((MODE) == CAN_OperatingMode_Sleep)) -/** - * @} - */ - -/** - * @defgroup CAN_operating_mode_status - * @{ - */ - -#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ -#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ -/** - * @} - */ - -/** @defgroup CAN_synchronisation_jump_width - * @{ - */ -#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ - ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_1 - * @{ - */ -#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ -#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ -#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ -#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ -#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ -#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ -#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ -#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ -#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_2 - * @{ - */ -#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) -/** - * @} - */ - -/** @defgroup CAN_clock_prescaler - * @{ - */ -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) -/** - * @} - */ - -/** @defgroup CAN_filter_number - * @{ - */ -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) -/** - * @} - */ - -/** @defgroup CAN_filter_mode - * @{ - */ -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ -#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ - -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ - ((MODE) == CAN_FilterMode_IdList)) -/** - * @} - */ - -/** @defgroup CAN_filter_scale - * @{ - */ -#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ - -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ - ((SCALE) == CAN_FilterScale_32bit)) -/** - * @} - */ - -/** @defgroup CAN_filter_FIFO - * @{ - */ -#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ - ((FIFO) == CAN_FilterFIFO1)) - -/* Legacy defines */ -#define CAN_FilterFIFO0 CAN_Filter_FIFO0 -#define CAN_FilterFIFO1 CAN_Filter_FIFO1 -/** - * @} - */ - -/** @defgroup CAN_Start_bank_filter_for_slave_CAN - * @{ - */ -#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) -/** - * @} - */ - -/** @defgroup CAN_Tx - * @{ - */ -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) -/** - * @} - */ - -/** @defgroup CAN_identifier_type - * @{ - */ -#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ - ((IDTYPE) == CAN_Id_Extended)) - -/* Legacy defines */ -#define CAN_ID_STD CAN_Id_Standard -#define CAN_ID_EXT CAN_Id_Extended -/** - * @} - */ - -/** @defgroup CAN_remote_transmission_request - * @{ - */ -#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) - -/* Legacy defines */ -#define CAN_RTR_DATA CAN_RTR_Data -#define CAN_RTR_REMOTE CAN_RTR_Remote -/** - * @} - */ - -/** @defgroup CAN_transmit_constants - * @{ - */ -#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ -#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ -#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ -#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide - an empty mailbox */ -/* Legacy defines */ -#define CANTXFAILED CAN_TxStatus_Failed -#define CANTXOK CAN_TxStatus_Ok -#define CANTXPENDING CAN_TxStatus_Pending -#define CAN_NO_MB CAN_TxStatus_NoMailBox -/** - * @} - */ - -/** @defgroup CAN_receive_FIFO_number_constants - * @{ - */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) -/** - * @} - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ -#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ -#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ - -/* Legacy defines */ -#define CANSLEEPFAILED CAN_Sleep_Failed -#define CANSLEEPOK CAN_Sleep_Ok -/** - * @} - */ - -/** @defgroup CAN_wake_up_constants - * @{ - */ -#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ -#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ - -/* Legacy defines */ -#define CANWAKEUPFAILED CAN_WakeUp_Failed -#define CANWAKEUPOK CAN_WakeUp_Ok -/** - * @} - */ - -/** - * @defgroup CAN_Error_Code_constants - * @{ - */ -#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ -#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ -#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ -#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ -#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ -#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ -#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ -#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ -/** - * @} - */ - -/** @defgroup CAN_flags - * @{ - */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with - CAN_GetFlagStatus() function. */ - -/* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ - -/* Receive Flags */ -#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ -#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ -#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ - -/* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ - -/* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ -#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ -#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ -#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ - -#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ - ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ - ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ - ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_SLAK )) - -#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ - ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) -/** - * @} - */ - - -/** @defgroup CAN_interrupts - * @{ - */ -#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ - -/* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ -#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ -#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ -#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ -#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ -#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ - -/* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ -#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ - -/* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ -#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ -#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ -#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ -#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ - -/* Flags named as Interrupts : kept only for FW compatibility */ -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME - - -#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ - ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ - ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ - ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the CAN configuration to the default reset state *****/ -void CAN_DeInit(CAN_TypeDef* CANx); - -/* Initialization and Configuration functions *********************************/ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); -void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); - -/* CAN Frames Transmission functions ******************************************/ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); - -/* CAN Frames Reception functions *********************************************/ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); - -/* Operation modes functions **************************************************/ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); -uint8_t CAN_Sleep(CAN_TypeDef* CANx); -uint8_t CAN_WakeUp(CAN_TypeDef* CANx); - -/* CAN Bus Error management functions *****************************************/ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); - -/* Interrupts and flags management functions **********************************/ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_CAN_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h deleted file mode 100644 index 56b2bb26a..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_crc.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the CRC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_CRC_H -#define __STM32F4xx_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRC_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void CRC_ResetDR(void); -uint32_t CRC_CalcCRC(uint32_t Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); -void CRC_SetIDRegister(uint8_t IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_CRC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h deleted file mode 100644 index ebcc8fbab..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h +++ /dev/null @@ -1,338 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_cryp.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the Cryptographic - * processor(CRYP) firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_CRYP_H -#define __STM32F4xx_CRYP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRYP - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief CRYP Init structure definition - */ -typedef struct -{ - uint16_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a - value of @ref CRYP_Algorithm_Direction */ - uint16_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, - AES-CBC, AES-CTR, AES-Key. This parameter can be - a value of @ref CRYP_Algorithm_Mode */ - uint16_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit-string. - This parameter can be a value of @ref CRYP_Data_Type */ - uint16_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit - key length. This parameter can be a value of - @ref CRYP_Key_Size_for_AES_only */ -}CRYP_InitTypeDef; - -/** - * @brief CRYP Key(s) structure definition - */ -typedef struct -{ - uint32_t CRYP_Key0Left; /*!< Key 0 Left */ - uint32_t CRYP_Key0Right; /*!< Key 0 Right */ - uint32_t CRYP_Key1Left; /*!< Key 1 left */ - uint32_t CRYP_Key1Right; /*!< Key 1 Right */ - uint32_t CRYP_Key2Left; /*!< Key 2 left */ - uint32_t CRYP_Key2Right; /*!< Key 2 Right */ - uint32_t CRYP_Key3Left; /*!< Key 3 left */ - uint32_t CRYP_Key3Right; /*!< Key 3 Right */ -}CRYP_KeyInitTypeDef; -/** - * @brief CRYP Initialization Vectors (IV) structure definition - */ -typedef struct -{ - uint32_t CRYP_IV0Left; /*!< Init Vector 0 Left */ - uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */ - uint32_t CRYP_IV1Left; /*!< Init Vector 1 left */ - uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */ -}CRYP_IVInitTypeDef; - -/** - * @brief CRYP context swapping structure definition - */ -typedef struct -{ - /*!< Configuration */ - uint32_t CR_bits9to2; - /*!< KEY */ - uint32_t CRYP_IV0LR; - uint32_t CRYP_IV0RR; - uint32_t CRYP_IV1LR; - uint32_t CRYP_IV1RR; - /*!< IV */ - uint32_t CRYP_K0LR; - uint32_t CRYP_K0RR; - uint32_t CRYP_K1LR; - uint32_t CRYP_K1RR; - uint32_t CRYP_K2LR; - uint32_t CRYP_K2RR; - uint32_t CRYP_K3LR; - uint32_t CRYP_K3RR; -}CRYP_Context; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRYP_Exported_Constants - * @{ - */ - -/** @defgroup CRYP_Algorithm_Direction - * @{ - */ -#define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000) -#define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004) -#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \ - ((ALGODIR) == CRYP_AlgoDir_Decrypt)) - -/** - * @} - */ - -/** @defgroup CRYP_Algorithm_Mode - * @{ - */ - -/*!< TDES Modes */ -#define CRYP_AlgoMode_TDES_ECB ((uint16_t)0x0000) -#define CRYP_AlgoMode_TDES_CBC ((uint16_t)0x0008) - -/*!< DES Modes */ -#define CRYP_AlgoMode_DES_ECB ((uint16_t)0x0010) -#define CRYP_AlgoMode_DES_CBC ((uint16_t)0x0018) - -/*!< AES Modes */ -#define CRYP_AlgoMode_AES_ECB ((uint16_t)0x0020) -#define CRYP_AlgoMode_AES_CBC ((uint16_t)0x0028) -#define CRYP_AlgoMode_AES_CTR ((uint16_t)0x0030) -#define CRYP_AlgoMode_AES_Key ((uint16_t)0x0038) - -#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \ - ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \ - ((ALGOMODE) == CRYP_AlgoMode_DES_ECB)|| \ - ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_Key)) -/** - * @} - */ - -/** @defgroup CRYP_Data_Type - * @{ - */ -#define CRYP_DataType_32b ((uint16_t)0x0000) -#define CRYP_DataType_16b ((uint16_t)0x0040) -#define CRYP_DataType_8b ((uint16_t)0x0080) -#define CRYP_DataType_1b ((uint16_t)0x00C0) -#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \ - ((DATATYPE) == CRYP_DataType_16b)|| \ - ((DATATYPE) == CRYP_DataType_8b)|| \ - ((DATATYPE) == CRYP_DataType_1b)) -/** - * @} - */ - -/** @defgroup CRYP_Key_Size_for_AES_only - * @{ - */ -#define CRYP_KeySize_128b ((uint16_t)0x0000) -#define CRYP_KeySize_192b ((uint16_t)0x0100) -#define CRYP_KeySize_256b ((uint16_t)0x0200) -#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \ - ((KEYSIZE) == CRYP_KeySize_192b)|| \ - ((KEYSIZE) == CRYP_KeySize_256b)) -/** - * @} - */ - -/** @defgroup CRYP_flags_definition - * @{ - */ -#define CRYP_FLAG_BUSY ((uint8_t)0x10) /*!< The CRYP core is currently - processing a block of data - or a key preparation (for - AES decryption). */ -#define CRYP_FLAG_IFEM ((uint8_t)0x01) /*!< Input Fifo Empty */ -#define CRYP_FLAG_IFNF ((uint8_t)0x02) /*!< Input Fifo is Not Full */ -#define CRYP_FLAG_INRIS ((uint8_t)0x22) /*!< Raw interrupt pending */ -#define CRYP_FLAG_OFNE ((uint8_t)0x04) /*!< Input Fifo service raw - interrupt status */ -#define CRYP_FLAG_OFFU ((uint8_t)0x08) /*!< Output Fifo is Full */ -#define CRYP_FLAG_OUTRIS ((uint8_t)0x21) /*!< Output Fifo service raw - interrupt status */ - -#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \ - ((FLAG) == CRYP_FLAG_IFNF) || \ - ((FLAG) == CRYP_FLAG_OFNE) || \ - ((FLAG) == CRYP_FLAG_OFFU) || \ - ((FLAG) == CRYP_FLAG_BUSY) || \ - ((FLAG) == CRYP_FLAG_OUTRIS)|| \ - ((FLAG) == CRYP_FLAG_INRIS)) -/** - * @} - */ - -/** @defgroup CRYP_interrupts_definition - * @{ - */ -#define CRYP_IT_INI ((uint8_t)0x01) /*!< IN Fifo Interrupt */ -#define CRYP_IT_OUTI ((uint8_t)0x02) /*!< OUT Fifo Interrupt */ -#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) -#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI)) - -/** - * @} - */ - -/** @defgroup CRYP_Encryption_Decryption_modes_definition - * @{ - */ -#define MODE_ENCRYPT ((uint8_t)0x01) -#define MODE_DECRYPT ((uint8_t)0x00) - -/** - * @} - */ - -/** @defgroup CRYP_DMA_transfer_requests - * @{ - */ -#define CRYP_DMAReq_DataIN ((uint8_t)0x01) -#define CRYP_DMAReq_DataOUT ((uint8_t)0x02) -#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the CRYP configuration to the default reset state ****/ -void CRYP_DeInit(void); - -/* CRYP Initialization and Configuration functions ****************************/ -void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct); -void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct); -void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); -void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); -void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); -void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); -void CRYP_Cmd(FunctionalState NewState); - -/* CRYP Data processing functions *********************************************/ -void CRYP_DataIn(uint32_t Data); -uint32_t CRYP_DataOut(void); -void CRYP_FIFOFlush(void); - -/* CRYP Context swapping functions ********************************************/ -ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, - CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); -void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore); - -/* CRYP's DMA interface function **********************************************/ -void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState); -ITStatus CRYP_GetITStatus(uint8_t CRYP_IT); -FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG); - -/* High Level AES functions **************************************************/ -ErrorStatus CRYP_AES_ECB(uint8_t Mode, - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_AES_CBC(uint8_t Mode, - uint8_t InitVectors[16], - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_AES_CTR(uint8_t Mode, - uint8_t InitVectors[16], - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -/* High Level TDES functions **************************************************/ -ErrorStatus CRYP_TDES_ECB(uint8_t Mode, - uint8_t Key[24], - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_TDES_CBC(uint8_t Mode, - uint8_t Key[24], - uint8_t InitVectors[8], - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -/* High Level DES functions **************************************************/ -ErrorStatus CRYP_DES_ECB(uint8_t Mode, - uint8_t Key[8], - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_DES_CBC(uint8_t Mode, - uint8_t Key[8], - uint8_t InitVectors[8], - uint8_t *Input,uint32_t Ilength, - uint8_t *Output); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_CRYP_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h deleted file mode 100644 index 0f706e905..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h +++ /dev/null @@ -1,298 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dac.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the DAC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DAC_H -#define __STM32F4xx_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DAC Init structure definition - */ - -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -/** @defgroup DAC_trigger_selection - * @{ - */ - -#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ - -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ - ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ - ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ - ((TRIGGER) == DAC_Trigger_Software)) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ - ((WAVE) == DAC_WaveGeneration_Noise) || \ - ((WAVE) == DAC_WaveGeneration_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_lfsrunmask_triangleamplitude - * @{ - */ - -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ - ((VALUE) == DAC_TriangleAmplitude_1) || \ - ((VALUE) == DAC_TriangleAmplitude_3) || \ - ((VALUE) == DAC_TriangleAmplitude_7) || \ - ((VALUE) == DAC_TriangleAmplitude_15) || \ - ((VALUE) == DAC_TriangleAmplitude_31) || \ - ((VALUE) == DAC_TriangleAmplitude_63) || \ - ((VALUE) == DAC_TriangleAmplitude_127) || \ - ((VALUE) == DAC_TriangleAmplitude_255) || \ - ((VALUE) == DAC_TriangleAmplitude_511) || \ - ((VALUE) == DAC_TriangleAmplitude_1023) || \ - ((VALUE) == DAC_TriangleAmplitude_2047) || \ - ((VALUE) == DAC_TriangleAmplitude_4095)) -/** - * @} - */ - -/** @defgroup DAC_output_buffer - * @{ - */ - -#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) -#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ - ((STATE) == DAC_OutputBuffer_Disable)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ - -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ - ((CHANNEL) == DAC_Channel_2)) -/** - * @} - */ - -/** @defgroup DAC_data_alignement - * @{ - */ - -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ - ((ALIGN) == DAC_Align_12b_L) || \ - ((ALIGN) == DAC_Align_8b_R)) -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ - ((WAVE) == DAC_Wave_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_data - * @{ - */ - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -/** - * @} - */ - -/** @defgroup DAC_interrupts_definition - * @{ - */ -#define DAC_IT_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) - -/** - * @} - */ - -/** @defgroup DAC_flags_definition - * @{ - */ - -#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DAC configuration to the default reset state *****/ -void DAC_DeInit(void); - -/* DAC channels configuration: trigger, output buffer, data format functions */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); - -/* DMA management functions ***************************************************/ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_DAC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h deleted file mode 100644 index 4a64d8850..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dbgmcu.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the DBGMCU firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DBGMCU_H -#define __STM32F4xx_DBGMCU_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DBGMCU - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DBGMCU_Exported_Constants - * @{ - */ -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004) -#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008) -#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010) -#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020) -#define DBGMCU_TIM12_STOP ((uint32_t)0x00000040) -#define DBGMCU_TIM13_STOP ((uint32_t)0x00000080) -#define DBGMCU_TIM14_STOP ((uint32_t)0x00000100) -#define DBGMCU_RTC_STOP ((uint32_t)0x00000400) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) -#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) -#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000) -#define DBGMCU_CAN2_STOP ((uint32_t)0x04000000) -#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001) -#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002) -#define DBGMCU_TIM9_STOP ((uint32_t)0x00010000) -#define DBGMCU_TIM10_STOP ((uint32_t)0x00020000) -#define DBGMCU_TIM11_STOP ((uint32_t)0x00040000) -#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_DBGMCU_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h deleted file mode 100644 index d78e66751..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h +++ /dev/null @@ -1,306 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dcmi.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the DCMI firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DCMI_H -#define __STM32F4xx_DCMI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DCMI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** - * @brief DCMI Init structure definition - */ -typedef struct -{ - uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot. - This parameter can be a value of @ref DCMI_Capture_Mode */ - - uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. - This parameter can be a value of @ref DCMI_Synchronization_Mode */ - - uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. - This parameter can be a value of @ref DCMI_PIXCK_Polarity */ - - uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_VSYNC_Polarity */ - - uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_HSYNC_Polarity */ - - uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. - This parameter can be a value of @ref DCMI_Capture_Rate */ - - uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. - This parameter can be a value of @ref DCMI_Extended_Data_Mode */ -} DCMI_InitTypeDef; - -/** - * @brief DCMI CROP Init structure definition - */ -typedef struct -{ - uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture - will start. This parameter can be a value between 0x00 and 0x1FFF */ - - uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture. - This parameter can be a value between 0x00 and 0x3FFF */ - - uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point. - This parameter can be a value between 0x00 and 0x3FFF */ - - uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting - point on the same line. - This parameter can be a value between 0x00 and 0x3FFF */ -} DCMI_CROPInitTypeDef; - -/** - * @brief DCMI Embedded Synchronisation CODE Init structure definition - */ -typedef struct -{ - uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ - uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */ - uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */ - uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ -} DCMI_CodesInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DCMI_Exported_Constants - * @{ - */ - -/** @defgroup DCMI_Capture_Mode - * @{ - */ -#define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously - into the destination memory through the DMA */ -#define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of - frame and then transfers a single frame through the DMA */ -#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \ - ((MODE) == DCMI_CaptureMode_SnapShot)) -/** - * @} - */ - - -/** @defgroup DCMI_Synchronization_Mode - * @{ - */ -#define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop) - is synchronized with the HSYNC/VSYNC signals */ -#define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with - synchronization codes embedded in the data flow */ -#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \ - ((MODE) == DCMI_SynchroMode_Embedded)) -/** - * @} - */ - - -/** @defgroup DCMI_PIXCK_Polarity - * @{ - */ -#define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */ -#define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */ -#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \ - ((POLARITY) == DCMI_PCKPolarity_Rising)) -/** - * @} - */ - - -/** @defgroup DCMI_VSYNC_Polarity - * @{ - */ -#define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */ -#define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */ -#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \ - ((POLARITY) == DCMI_VSPolarity_High)) -/** - * @} - */ - - -/** @defgroup DCMI_HSYNC_Polarity - * @{ - */ -#define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */ -#define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */ -#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \ - ((POLARITY) == DCMI_HSPolarity_High)) -/** - * @} - */ - - -/** @defgroup DCMI_Capture_Rate - * @{ - */ -#define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */ -#define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */ -#define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */ -#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \ - ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\ - ((RATE) == DCMI_CaptureRate_1of4_Frame)) -/** - * @} - */ - - -/** @defgroup DCMI_Extended_Data_Mode - * @{ - */ -#define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */ -#define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */ -#define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */ -#define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */ -#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \ - ((DATA) == DCMI_ExtendedDataMode_10b) ||\ - ((DATA) == DCMI_ExtendedDataMode_12b) ||\ - ((DATA) == DCMI_ExtendedDataMode_14b)) -/** - * @} - */ - - -/** @defgroup DCMI_interrupt_sources - * @{ - */ -#define DCMI_IT_FRAME ((uint16_t)0x0001) -#define DCMI_IT_OVF ((uint16_t)0x0002) -#define DCMI_IT_ERR ((uint16_t)0x0004) -#define DCMI_IT_VSYNC ((uint16_t)0x0008) -#define DCMI_IT_LINE ((uint16_t)0x0010) -#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000)) -#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \ - ((IT) == DCMI_IT_OVF) || \ - ((IT) == DCMI_IT_ERR) || \ - ((IT) == DCMI_IT_VSYNC) || \ - ((IT) == DCMI_IT_LINE)) -/** - * @} - */ - - -/** @defgroup DCMI_Flags - * @{ - */ -/** - * @brief DCMI SR register - */ -#define DCMI_FLAG_HSYNC ((uint16_t)0x2001) -#define DCMI_FLAG_VSYNC ((uint16_t)0x2002) -#define DCMI_FLAG_FNE ((uint16_t)0x2004) -/** - * @brief DCMI RISR register - */ -#define DCMI_FLAG_FRAMERI ((uint16_t)0x0001) -#define DCMI_FLAG_OVFRI ((uint16_t)0x0002) -#define DCMI_FLAG_ERRRI ((uint16_t)0x0004) -#define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008) -#define DCMI_FLAG_LINERI ((uint16_t)0x0010) -/** - * @brief DCMI MISR register - */ -#define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001) -#define DCMI_FLAG_OVFMI ((uint16_t)0x1002) -#define DCMI_FLAG_ERRMI ((uint16_t)0x1004) -#define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008) -#define DCMI_FLAG_LINEMI ((uint16_t)0x1010) -#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \ - ((FLAG) == DCMI_FLAG_VSYNC) || \ - ((FLAG) == DCMI_FLAG_FNE) || \ - ((FLAG) == DCMI_FLAG_FRAMERI) || \ - ((FLAG) == DCMI_FLAG_OVFRI) || \ - ((FLAG) == DCMI_FLAG_ERRRI) || \ - ((FLAG) == DCMI_FLAG_VSYNCRI) || \ - ((FLAG) == DCMI_FLAG_LINERI) || \ - ((FLAG) == DCMI_FLAG_FRAMEMI) || \ - ((FLAG) == DCMI_FLAG_OVFMI) || \ - ((FLAG) == DCMI_FLAG_ERRMI) || \ - ((FLAG) == DCMI_FLAG_VSYNCMI) || \ - ((FLAG) == DCMI_FLAG_LINEMI)) - -#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DCMI configuration to the default reset state ****/ -void DCMI_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct); -void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct); -void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct); -void DCMI_CROPCmd(FunctionalState NewState); -void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct); -void DCMI_JPEGCmd(FunctionalState NewState); - -/* Image capture functions ****************************************************/ -void DCMI_Cmd(FunctionalState NewState); -void DCMI_CaptureCmd(FunctionalState NewState); -uint32_t DCMI_ReadData(void); - -/* Interrupts and flags management functions **********************************/ -void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState); -FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG); -void DCMI_ClearFlag(uint16_t DCMI_FLAG); -ITStatus DCMI_GetITStatus(uint16_t DCMI_IT); -void DCMI_ClearITPendingBit(uint16_t DCMI_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_DCMI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h deleted file mode 100644 index 9d5d68bfb..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h +++ /dev/null @@ -1,603 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dma.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the DMA firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DMA_H -#define __STM32F4xx_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DMA Init structure definition - */ - -typedef struct -{ - uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream. - This parameter can be a value of @ref DMA_channel */ - - uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */ - - uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx. - This memory is the default memory used when double buffer mode is - not enabled. */ - - uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx. - This parameter can be a value of @ref DMA_circular_normal_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Stream */ - - uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream. - This parameter can be a value of @ref DMA_fifo_direct_mode - @note The Direct mode (FIFO mode disabled) cannot be used if the - memory-to-memory data transfer is configured on the selected Stream */ - - uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level. - This parameter can be a value of @ref DMA_fifo_threshold_level */ - - uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. - It specifies the amount of data to be transferred in a single non interruptable - transaction. This parameter can be a value of @ref DMA_memory_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ - - uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. - It specifies the amount of data to be transferred in a single non interruptable - transaction. This parameter can be a value of @ref DMA_peripheral_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ -}DMA_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants - * @{ - */ - -#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \ - ((PERIPH) == DMA1_Stream1) || \ - ((PERIPH) == DMA1_Stream2) || \ - ((PERIPH) == DMA1_Stream3) || \ - ((PERIPH) == DMA1_Stream4) || \ - ((PERIPH) == DMA1_Stream5) || \ - ((PERIPH) == DMA1_Stream6) || \ - ((PERIPH) == DMA1_Stream7) || \ - ((PERIPH) == DMA2_Stream0) || \ - ((PERIPH) == DMA2_Stream1) || \ - ((PERIPH) == DMA2_Stream2) || \ - ((PERIPH) == DMA2_Stream3) || \ - ((PERIPH) == DMA2_Stream4) || \ - ((PERIPH) == DMA2_Stream5) || \ - ((PERIPH) == DMA2_Stream6) || \ - ((PERIPH) == DMA2_Stream7)) - -#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \ - ((CONTROLLER) == DMA2)) - -/** @defgroup DMA_channel - * @{ - */ -#define DMA_Channel_0 ((uint32_t)0x00000000) -#define DMA_Channel_1 ((uint32_t)0x02000000) -#define DMA_Channel_2 ((uint32_t)0x04000000) -#define DMA_Channel_3 ((uint32_t)0x06000000) -#define DMA_Channel_4 ((uint32_t)0x08000000) -#define DMA_Channel_5 ((uint32_t)0x0A000000) -#define DMA_Channel_6 ((uint32_t)0x0C000000) -#define DMA_Channel_7 ((uint32_t)0x0E000000) - -#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \ - ((CHANNEL) == DMA_Channel_1) || \ - ((CHANNEL) == DMA_Channel_2) || \ - ((CHANNEL) == DMA_Channel_3) || \ - ((CHANNEL) == DMA_Channel_4) || \ - ((CHANNEL) == DMA_Channel_5) || \ - ((CHANNEL) == DMA_Channel_6) || \ - ((CHANNEL) == DMA_Channel_7)) -/** - * @} - */ - - -/** @defgroup DMA_data_transfer_direction - * @{ - */ -#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000) -#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) -#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080) - -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \ - ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \ - ((DIRECTION) == DMA_DIR_MemoryToMemory)) -/** - * @} - */ - - -/** @defgroup DMA_data_buffer_size - * @{ - */ -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_incremented_mode - * @{ - */ -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ - ((STATE) == DMA_PeripheralInc_Disable)) -/** - * @} - */ - - -/** @defgroup DMA_memory_incremented_mode - * @{ - */ -#define DMA_MemoryInc_Enable ((uint32_t)0x00000400) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ - ((STATE) == DMA_MemoryInc_Disable)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_data_size - * @{ - */ -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000) - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ - ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ - ((SIZE) == DMA_PeripheralDataSize_Word)) -/** - * @} - */ - - -/** @defgroup DMA_memory_data_size - * @{ - */ -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000) - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ - ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ - ((SIZE) == DMA_MemoryDataSize_Word )) -/** - * @} - */ - - -/** @defgroup DMA_circular_normal_mode - * @{ - */ -#define DMA_Mode_Normal ((uint32_t)0x00000000) -#define DMA_Mode_Circular ((uint32_t)0x00000100) - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \ - ((MODE) == DMA_Mode_Circular)) -/** - * @} - */ - - -/** @defgroup DMA_priority_level - * @{ - */ -#define DMA_Priority_Low ((uint32_t)0x00000000) -#define DMA_Priority_Medium ((uint32_t)0x00010000) -#define DMA_Priority_High ((uint32_t)0x00020000) -#define DMA_Priority_VeryHigh ((uint32_t)0x00030000) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \ - ((PRIORITY) == DMA_Priority_Medium) || \ - ((PRIORITY) == DMA_Priority_High) || \ - ((PRIORITY) == DMA_Priority_VeryHigh)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_direct_mode - * @{ - */ -#define DMA_FIFOMode_Disable ((uint32_t)0x00000000) -#define DMA_FIFOMode_Enable ((uint32_t)0x00000004) - -#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \ - ((STATE) == DMA_FIFOMode_Enable)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_threshold_level - * @{ - */ -#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000) -#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) -#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002) -#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003) - -#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \ - ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \ - ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \ - ((THRESHOLD) == DMA_FIFOThreshold_Full)) -/** - * @} - */ - - -/** @defgroup DMA_memory_burst - * @{ - */ -#define DMA_MemoryBurst_Single ((uint32_t)0x00000000) -#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) -#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000) -#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000) - -#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \ - ((BURST) == DMA_MemoryBurst_INC4) || \ - ((BURST) == DMA_MemoryBurst_INC8) || \ - ((BURST) == DMA_MemoryBurst_INC16)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_burst - * @{ - */ -#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000) -#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) -#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000) -#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000) - -#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \ - ((BURST) == DMA_PeripheralBurst_INC4) || \ - ((BURST) == DMA_PeripheralBurst_INC8) || \ - ((BURST) == DMA_PeripheralBurst_INC16)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_status_level - * @{ - */ -#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3) -#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3) -#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) -#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3) -#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3) -#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3) - -#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \ - ((STATUS) == DMA_FIFOStatus_HalfFull) || \ - ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \ - ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \ - ((STATUS) == DMA_FIFOStatus_Full) || \ - ((STATUS) == DMA_FIFOStatus_Empty)) -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ -#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001) -#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004) -#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008) -#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010) -#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020) -#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040) -#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100) -#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200) -#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400) -#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800) -#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000) -#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000) -#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000) -#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000) -#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000) -#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000) -#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000) -#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000) -#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000) -#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000) -#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001) -#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004) -#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008) -#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010) -#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020) -#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040) -#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100) -#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200) -#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400) -#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800) -#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000) -#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000) -#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000) -#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000) -#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000) -#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000) -#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000) -#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000) -#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000) -#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) - -#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ - (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00)) - -#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \ - ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ - ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \ - ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \ - ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \ - ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \ - ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \ - ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \ - ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \ - ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \ - ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \ - ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \ - ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \ - ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \ - ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \ - ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \ - ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \ - ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \ - ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \ - ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7)) -/** - * @} - */ - - -/** @defgroup DMA_interrupt_enable_definitions - * @{ - */ -#define DMA_IT_TC ((uint32_t)0x00000010) -#define DMA_IT_HT ((uint32_t)0x00000008) -#define DMA_IT_TE ((uint32_t)0x00000004) -#define DMA_IT_DME ((uint32_t)0x00000002) -#define DMA_IT_FE ((uint32_t)0x00000080) - -#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - - -/** @defgroup DMA_interrupts_definitions - * @{ - */ -#define DMA_IT_FEIF0 ((uint32_t)0x90000001) -#define DMA_IT_DMEIF0 ((uint32_t)0x10001004) -#define DMA_IT_TEIF0 ((uint32_t)0x10002008) -#define DMA_IT_HTIF0 ((uint32_t)0x10004010) -#define DMA_IT_TCIF0 ((uint32_t)0x10008020) -#define DMA_IT_FEIF1 ((uint32_t)0x90000040) -#define DMA_IT_DMEIF1 ((uint32_t)0x10001100) -#define DMA_IT_TEIF1 ((uint32_t)0x10002200) -#define DMA_IT_HTIF1 ((uint32_t)0x10004400) -#define DMA_IT_TCIF1 ((uint32_t)0x10008800) -#define DMA_IT_FEIF2 ((uint32_t)0x90010000) -#define DMA_IT_DMEIF2 ((uint32_t)0x10041000) -#define DMA_IT_TEIF2 ((uint32_t)0x10082000) -#define DMA_IT_HTIF2 ((uint32_t)0x10104000) -#define DMA_IT_TCIF2 ((uint32_t)0x10208000) -#define DMA_IT_FEIF3 ((uint32_t)0x90400000) -#define DMA_IT_DMEIF3 ((uint32_t)0x11001000) -#define DMA_IT_TEIF3 ((uint32_t)0x12002000) -#define DMA_IT_HTIF3 ((uint32_t)0x14004000) -#define DMA_IT_TCIF3 ((uint32_t)0x18008000) -#define DMA_IT_FEIF4 ((uint32_t)0xA0000001) -#define DMA_IT_DMEIF4 ((uint32_t)0x20001004) -#define DMA_IT_TEIF4 ((uint32_t)0x20002008) -#define DMA_IT_HTIF4 ((uint32_t)0x20004010) -#define DMA_IT_TCIF4 ((uint32_t)0x20008020) -#define DMA_IT_FEIF5 ((uint32_t)0xA0000040) -#define DMA_IT_DMEIF5 ((uint32_t)0x20001100) -#define DMA_IT_TEIF5 ((uint32_t)0x20002200) -#define DMA_IT_HTIF5 ((uint32_t)0x20004400) -#define DMA_IT_TCIF5 ((uint32_t)0x20008800) -#define DMA_IT_FEIF6 ((uint32_t)0xA0010000) -#define DMA_IT_DMEIF6 ((uint32_t)0x20041000) -#define DMA_IT_TEIF6 ((uint32_t)0x20082000) -#define DMA_IT_HTIF6 ((uint32_t)0x20104000) -#define DMA_IT_TCIF6 ((uint32_t)0x20208000) -#define DMA_IT_FEIF7 ((uint32_t)0xA0400000) -#define DMA_IT_DMEIF7 ((uint32_t)0x21001000) -#define DMA_IT_TEIF7 ((uint32_t)0x22002000) -#define DMA_IT_HTIF7 ((uint32_t)0x24004000) -#define DMA_IT_TCIF7 ((uint32_t)0x28008000) - -#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \ - (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \ - (((IT) & 0x40820082) == 0x00)) - -#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \ - ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \ - ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \ - ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \ - ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \ - ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \ - ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \ - ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \ - ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \ - ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \ - ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \ - ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \ - ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \ - ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \ - ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \ - ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \ - ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \ - ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \ - ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \ - ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_increment_offset - * @{ - */ -#define DMA_PINCOS_Psize ((uint32_t)0x00000000) -#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000) - -#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \ - ((SIZE) == DMA_PINCOS_WordAligned)) -/** - * @} - */ - - -/** @defgroup DMA_flow_controller_definitions - * @{ - */ -#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000) -#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020) - -#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \ - ((CTRL) == DMA_FlowCtrl_Peripheral)) -/** - * @} - */ - - -/** @defgroup DMA_memory_targets_definitions - * @{ - */ -#define DMA_Memory_0 ((uint32_t)0x00000000) -#define DMA_Memory_1 ((uint32_t)0x00080000) - -#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DMA configuration to the default reset state *****/ -void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Initialization and Configuration functions *********************************/ -void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); - -/* Optional Configuration functions *******************************************/ -void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos); -void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl); - -/* Data Counter functions *****************************************************/ -void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); -uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Double Buffer mode functions ***********************************************/ -void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory); -void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); -void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget); -uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Interrupts and flags management functions **********************************/ -FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); -uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); -FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); -void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); -void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); -ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); -void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_DMA_H */ - -/** - * @} - */ - -/** - * @} - */ - - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h deleted file mode 100644 index e35a1c065..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h +++ /dev/null @@ -1,177 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_exti.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the EXTI firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_EXTI_H -#define __STM32F4xx_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination value of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTITrigger_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ -#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ -#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ -#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ - -#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00)) - -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ - ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\ - ((LINE) == EXTI_Line22)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the EXTI configuration to the default reset state *****/ -void EXTI_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); - -/* Interrupts and flags management functions **********************************/ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_EXTI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h deleted file mode 100644 index 63b9a17ed..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h +++ /dev/null @@ -1,334 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_flash.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_FLASH_H -#define __STM32F4xx_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** - * @brief FLASH Status - */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PGS, - FLASH_ERROR_PGP, - FLASH_ERROR_PGA, - FLASH_ERROR_WRP, - FLASH_ERROR_PROGRAM, - FLASH_ERROR_OPERATION, - FLASH_COMPLETE -}FLASH_Status; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup Flash_Latency - * @{ - */ -#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ -#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ -#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ -#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ -#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ -#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2) || \ - ((LATENCY) == FLASH_Latency_3) || \ - ((LATENCY) == FLASH_Latency_4) || \ - ((LATENCY) == FLASH_Latency_5) || \ - ((LATENCY) == FLASH_Latency_6) || \ - ((LATENCY) == FLASH_Latency_7)) -/** - * @} - */ - -/** @defgroup FLASH_Voltage_Range - * @{ - */ -#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ -#define VoltageRange_2 ((uint8_t)0x01) /*!= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ -#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ -#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ -#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ -#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ -#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ -#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ -#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ -#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ -#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ -#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ -#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ -#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ -#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ - -#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_Read_Protection - * @{ - */ -#define OB_RDP_Level_0 ((uint8_t)0xAA) -#define OB_RDP_Level_1 ((uint8_t)0x55) -/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 - it's no more possible to go back to level 1 or 0 */ -#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ - ((LEVEL) == OB_RDP_Level_1))/*||\ - ((LEVEL) == OB_RDP_Level_2))*/ -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_IWatchdog - * @{ - */ -#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_nRST_STOP - * @{ - */ -#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) -/** - * @} - */ - - -/** @defgroup FLASH_Option_Bytes_nRST_STDBY - * @{ - */ -#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) -/** - * @} - */ - -/** @defgroup FLASH_BOR_Reset_Level - * @{ - */ -#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ -#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ -#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ -#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ -#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ - ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) -/** - * @} - */ - -/** @defgroup FLASH_Interrupts - * @{ - */ -#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000)) -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ -#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ -#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ -#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ -#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ - ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ - ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ - ((FLAG) == FLASH_FLAG_BSY)) -/** - * @} - */ - -/** @defgroup FLASH_Program_Parallelism - * @{ - */ -#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) -#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100) -#define FLASH_PSIZE_WORD ((uint32_t)0x00000200) -#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300) -#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) -/** - * @} - */ - -/** @defgroup FLASH_Keys - * @{ - */ -#define RDP_KEY ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) -#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) -#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) -/** - * @} - */ - -/** - * @brief ACR register byte 0 (Bits[8:0]) base address - */ -#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) -/** - * @brief OPTCR register byte 3 (Bits[24:16]) base address - */ -#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) -#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) -#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* FLASH Interface configuration functions ************************************/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_PrefetchBufferCmd(FunctionalState NewState); -void FLASH_InstructionCacheCmd(FunctionalState NewState); -void FLASH_DataCacheCmd(FunctionalState NewState); -void FLASH_InstructionCacheReset(void); -void FLASH_DataCacheReset(void); - -/* FLASH Memory Programming functions *****************************************/ -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); -FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); -FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); - -/* Option Bytes Programming functions *****************************************/ -void FLASH_OB_Unlock(void); -void FLASH_OB_Lock(void); -void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); -void FLASH_OB_RDPConfig(uint8_t OB_RDP); -void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); -void FLASH_OB_BORConfig(uint8_t OB_BOR); -FLASH_Status FLASH_OB_Launch(void); -uint8_t FLASH_OB_GetUser(void); -uint16_t FLASH_OB_GetWRP(void); -FlagStatus FLASH_OB_GetRDP(void); -uint8_t FLASH_OB_GetBOR(void); - -/* Interrupts and flags management functions **********************************/ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_FLASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h deleted file mode 100644 index 839f8dedd..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h +++ /dev/null @@ -1,669 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_fsmc.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the FSMC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_FSMC_H -#define __STM32F4xx_FSMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FSMC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief Timing parameters For NOR/SRAM Banks - */ -typedef struct -{ - uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between 0 and 0xF. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between 0 and 0xF. - @note This parameter is not used with synchronous NOR Flash memories.*/ - - uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between 0 and 0xFF. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - - uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between 0 and 0xF. - @note This parameter is only used for multiplexed NOR Flash memories. */ - - uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. - This parameter can be a value between 1 and 0xF. - @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - - uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The parameter value depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between 0 and 0xF in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ -}FSMC_NORSRAMTimingInitTypeDef; - -/** - * @brief FSMC NOR/SRAM Init structure definition - */ -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ - - uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the databus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ - - uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory bank. - This parameter can be a value of @ref FSMC_Memory_Type */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_Data_Width */ - - uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ - - uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FSMC_AsynchronousWait */ - - uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ - - uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode */ - - uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ - - uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ - - uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ - - uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ - - uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ -}FSMC_NORSRAMInitTypeDef; - -/** - * @brief Timing parameters For FSMC NAND and PCCARD Banks - */ -typedef struct -{ - uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND-Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between 0 and 0xFF.*/ - - uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND-Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command deassertion - for NAND-Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - databus is kept in HiZ after the start of a NAND-Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ -}FSMC_NAND_PCCARDTimingInitTypeDef; - -/** - * @brief FSMC NAND Init structure definition - */ -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ - - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FSMC_Data_Width */ - - uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ - - uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ -}FSMC_NANDInitTypeDef; - -/** - * @brief FSMC PCCARD Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ -}FSMC_PCCARDInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FSMC_Exported_Constants - * @{ - */ - -/** @defgroup FSMC_NORSRAM_Bank - * @{ - */ -#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) -#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) -#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) -#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup FSMC_NAND_Bank - * @{ - */ -#define FSMC_Bank2_NAND ((uint32_t)0x00000010) -#define FSMC_Bank3_NAND ((uint32_t)0x00000100) -/** - * @} - */ - -/** @defgroup FSMC_PCCARD_Bank - * @{ - */ -#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) -/** - * @} - */ - -#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ - ((BANK) == FSMC_Bank1_NORSRAM2) || \ - ((BANK) == FSMC_Bank1_NORSRAM3) || \ - ((BANK) == FSMC_Bank1_NORSRAM4)) - -#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND)) - -#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -/** @defgroup FSMC_NOR_SRAM_Controller - * @{ - */ - -/** @defgroup FSMC_Data_Address_Bus_Multiplexing - * @{ - */ - -#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) -#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) -#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ - ((MUX) == FSMC_DataAddressMux_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Memory_Type - * @{ - */ - -#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) -#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) -#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) -#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ - ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ - ((MEMORY) == FSMC_MemoryType_NOR)) -/** - * @} - */ - -/** @defgroup FSMC_Data_Width - * @{ - */ - -#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) -#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ - ((WIDTH) == FSMC_MemoryDataWidth_16b)) -/** - * @} - */ - -/** @defgroup FSMC_Burst_Access_Mode - * @{ - */ - -#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) -#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) -#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ - ((STATE) == FSMC_BurstAccessMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_AsynchronousWait - * @{ - */ -#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) -#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) -#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ - ((STATE) == FSMC_AsynchronousWait_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal_Polarity - * @{ - */ -#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) -#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) -#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ - ((POLARITY) == FSMC_WaitSignalPolarity_High)) -/** - * @} - */ - -/** @defgroup FSMC_Wrap_Mode - * @{ - */ -#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) -#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) -#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ - ((MODE) == FSMC_WrapMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Timing - * @{ - */ -#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) -#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ - ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) -/** - * @} - */ - -/** @defgroup FSMC_Write_Operation - * @{ - */ -#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) -#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) -#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ - ((OPERATION) == FSMC_WriteOperation_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal - * @{ - */ -#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) -#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) -#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ - ((SIGNAL) == FSMC_WaitSignal_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Extended_Mode - * @{ - */ -#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) -#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) - -#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ - ((MODE) == FSMC_ExtendedMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Write_Burst - * @{ - */ - -#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) -#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) -#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ - ((BURST) == FSMC_WriteBurst_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Address_Setup_Time - * @{ - */ -#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Address_Hold_Time - * @{ - */ -#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Data_Setup_Time - * @{ - */ -#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) -/** - * @} - */ - -/** @defgroup FSMC_Bus_Turn_around_Duration - * @{ - */ -#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_CLK_Division - * @{ - */ -#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Data_Latency - * @{ - */ -#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Access_Mode - * @{ - */ -#define FSMC_AccessMode_A ((uint32_t)0x00000000) -#define FSMC_AccessMode_B ((uint32_t)0x10000000) -#define FSMC_AccessMode_C ((uint32_t)0x20000000) -#define FSMC_AccessMode_D ((uint32_t)0x30000000) -#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ - ((MODE) == FSMC_AccessMode_B) || \ - ((MODE) == FSMC_AccessMode_C) || \ - ((MODE) == FSMC_AccessMode_D)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FSMC_NAND_PCCARD_Controller - * @{ - */ - -/** @defgroup FSMC_Wait_feature - * @{ - */ -#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) -#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) -#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ - ((FEATURE) == FSMC_Waitfeature_Enable)) -/** - * @} - */ - - -/** @defgroup FSMC_ECC - * @{ - */ -#define FSMC_ECC_Disable ((uint32_t)0x00000000) -#define FSMC_ECC_Enable ((uint32_t)0x00000040) -#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ - ((STATE) == FSMC_ECC_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_ECC_Page_Size - * @{ - */ -#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) -#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) -#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) -#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) -#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) -#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) -#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_8192Bytes)) -/** - * @} - */ - -/** @defgroup FSMC_TCLR_Setup_Time - * @{ - */ -#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_TAR_Setup_Time - * @{ - */ -#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Setup_Time - * @{ - */ -#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Setup_Time - * @{ - */ -#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Hold_Setup_Time - * @{ - */ -#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_HiZ_Setup_Time - * @{ - */ -#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Interrupt_sources - * @{ - */ -#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) -#define FSMC_IT_Level ((uint32_t)0x00000010) -#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) -#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ - ((IT) == FSMC_IT_Level) || \ - ((IT) == FSMC_IT_FallingEdge)) -/** - * @} - */ - -/** @defgroup FSMC_Flags - * @{ - */ -#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) -#define FSMC_FLAG_Level ((uint32_t)0x00000002) -#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) -#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) -#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ - ((FLAG) == FSMC_FLAG_Level) || \ - ((FLAG) == FSMC_FLAG_FallingEdge) || \ - ((FLAG) == FSMC_FLAG_FEMPT)) - -#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* NOR/SRAM Controller functions **********************************************/ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); - -/* NAND Controller functions **************************************************/ -void FSMC_NANDDeInit(uint32_t FSMC_Bank); -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); -uint32_t FSMC_GetECC(uint32_t FSMC_Bank); - -/* PCCARD Controller functions ************************************************/ -void FSMC_PCCARDDeInit(void); -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_PCCARDCmd(FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_FSMC_H */ -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h deleted file mode 100644 index 05b90744f..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h +++ /dev/null @@ -1,406 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_gpio.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the GPIO firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_GPIO_H -#define __STM32F4xx_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF) || \ - ((PERIPH) == GPIOG) || \ - ((PERIPH) == GPIOH) || \ - ((PERIPH) == GPIOI)) - -/** - * @brief GPIO Configuration Mode enumeration - */ -typedef enum -{ - GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ - GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ - GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ - GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ -}GPIOMode_TypeDef; -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ - ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) - -/** - * @brief GPIO Output type enumeration - */ -typedef enum -{ - GPIO_OType_PP = 0x00, - GPIO_OType_OD = 0x01 -}GPIOOType_TypeDef; -#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) - - -/** - * @brief GPIO Output Maximum frequency enumeration - */ -typedef enum -{ - GPIO_Speed_2MHz = 0x00, /*!< Low speed */ - GPIO_Speed_25MHz = 0x01, /*!< Medium speed */ - GPIO_Speed_50MHz = 0x02, /*!< Fast speed */ - GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */ -}GPIOSpeed_TypeDef; -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \ - ((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz)) - -/** - * @brief GPIO Configuration PullUp PullDown enumeration - */ -typedef enum -{ - GPIO_PuPd_NOPULL = 0x00, - GPIO_PuPd_UP = 0x01, - GPIO_PuPd_DOWN = 0x02 -}GPIOPuPd_TypeDef; -#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ - ((PUPD) == GPIO_PuPd_DOWN)) - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -}BitAction; -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) - - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIOOType_TypeDef */ - - GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIOPuPd_TypeDef */ -}GPIO_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ - -#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) -/** - * @} - */ - - -/** @defgroup GPIO_Pin_sources - * @{ - */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) -/** - * @} - */ - -/** @defgroup GPIO_Alternat_function_selection_define - * @{ - */ -/** - * @brief AF 0 selection - */ -#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#define GPIO_AF_I2S3ext ((uint8_t)0x07) /* I2S3ext Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ -#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ -#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ - ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ - ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ - ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ - ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ - ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ - ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ - ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ - ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ - ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ - ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ - ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ - ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ - ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \ - ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \ - ((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT)) -/** - * @} - */ - -/** @defgroup GPIO_Legacy - * @{ - */ - -#define GPIO_Mode_AIN GPIO_Mode_AN - -#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS -#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS -#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the GPIO configuration to the default reset state ****/ -void GPIO_DeInit(GPIO_TypeDef* GPIOx); - -/* Initialization and Configuration functions *********************************/ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Read and Write functions **********************************************/ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Alternate functions configuration function ****************************/ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_GPIO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h deleted file mode 100644 index 7cf571753..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h +++ /dev/null @@ -1,244 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hash.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the HASH - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HASH_H -#define __STM32F4xx_HASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup HASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HASH Init structure definition - */ -typedef struct -{ - uint32_t HASH_AlgoSelection; /*!< SHA-1 or MD5. This parameter can be a value - of @ref HASH_Algo_Selection */ - uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value - of @ref HASH_processor_Algorithm_Mode */ - uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or - bit-string. This parameter can be a value of - @ref HASH_Data_Type */ - uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter - can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */ -}HASH_InitTypeDef; - -/** - * @brief HASH message digest result structure definition - */ -typedef struct -{ - uint32_t Data[5]; /*!< Message digest result : 5x 32bit words for SHA1 or - 4x 32bit words for MD5 */ -} HASH_MsgDigest; - -/** - * @brief HASH context swapping structure definition - */ -typedef struct -{ - uint32_t HASH_IMR; - uint32_t HASH_STR; - uint32_t HASH_CR; - uint32_t HASH_CSR[51]; -}HASH_Context; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HASH_Exported_Constants - * @{ - */ - -/** @defgroup HASH_Algo_Selection - * @{ - */ -#define HASH_AlgoSelection_SHA1 ((uint16_t)0x0000) /*!< HASH function is SHA1 */ -#define HASH_AlgoSelection_MD5 ((uint16_t)0x0080) /*!< HASH function is MD5 */ - -#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \ - ((ALGOSELECTION) == HASH_AlgoSelection_MD5)) -/** - * @} - */ - -/** @defgroup HASH_processor_Algorithm_Mode - * @{ - */ -#define HASH_AlgoMode_HASH ((uint16_t)0x0000) /*!< Algorithm is HASH */ -#define HASH_AlgoMode_HMAC ((uint16_t)0x0040) /*!< Algorithm is HMAC */ - -#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \ - ((ALGOMODE) == HASH_AlgoMode_HMAC)) -/** - * @} - */ - -/** @defgroup HASH_Data_Type - * @{ - */ -#define HASH_DataType_32b ((uint16_t)0x0000) -#define HASH_DataType_16b ((uint16_t)0x0010) -#define HASH_DataType_8b ((uint16_t)0x0020) -#define HASH_DataType_1b ((uint16_t)0x0030) - -#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \ - ((DATATYPE) == HASH_DataType_16b)|| \ - ((DATATYPE) == HASH_DataType_8b)|| \ - ((DATATYPE) == HASH_DataType_1b)) -/** - * @} - */ - -/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode - * @{ - */ -#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */ -#define HASH_HMACKeyType_LongKey ((uint32_t)0x00010000) /*!< HMAC Key is > 64 bytes */ - -#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \ - ((KEYTYPE) == HASH_HMACKeyType_LongKey)) -/** - * @} - */ - -/** @defgroup Number_of_valid_bits_in_last_word_of_the_message - * @{ - */ -#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F) - -/** - * @} - */ - -/** @defgroup HASH_interrupts_definition - * @{ - */ -#define HASH_IT_DINI ((uint8_t)0x01) /*!< A new block can be entered into the input buffer (DIN)*/ -#define HASH_IT_DCI ((uint8_t)0x02) /*!< Digest calculation complete */ - -#define IS_HASH_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) -#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI)) - -/** - * @} - */ - -/** @defgroup HASH_flags_definition - * @{ - */ -#define HASH_FLAG_DINIS ((uint16_t)0x0001) /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer.*/ -#define HASH_FLAG_DCIS ((uint16_t)0x0002) /*!< Digest calculation complete */ -#define HASH_FLAG_DMAS ((uint16_t)0x0004) /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ -#define HASH_FLAG_BUSY ((uint16_t)0x0008) /*!< The hash core is Busy : processing a block of data */ -#define HASH_FLAG_DINNE ((uint16_t)0x1000) /*!< DIN not empty : The input buffer contains at least one word of data */ - -#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \ - ((FLAG) == HASH_FLAG_DCIS) || \ - ((FLAG) == HASH_FLAG_DMAS) || \ - ((FLAG) == HASH_FLAG_BUSY) || \ - ((FLAG) == HASH_FLAG_DINNE)) - -#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \ - ((FLAG) == HASH_FLAG_DCIS)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the HASH configuration to the default reset state ****/ -void HASH_DeInit(void); - -/* HASH Configuration function ************************************************/ -void HASH_Init(HASH_InitTypeDef* HASH_InitStruct); -void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct); -void HASH_Reset(void); - -/* HASH Message Digest generation functions ***********************************/ -void HASH_DataIn(uint32_t Data); -uint8_t HASH_GetInFIFOWordsNbr(void); -void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber); -void HASH_StartDigest(void); -void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest); - -/* HASH Context swapping functions ********************************************/ -void HASH_SaveContext(HASH_Context* HASH_ContextSave); -void HASH_RestoreContext(HASH_Context* HASH_ContextRestore); - -/* HASH's DMA interface function **********************************************/ -void HASH_DMACmd(FunctionalState NewState); - -/* HASH Interrupts and flags management functions *****************************/ -void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState); -FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG); -void HASH_ClearFlag(uint16_t HASH_FLAG); -ITStatus HASH_GetITStatus(uint8_t HASH_IT); -void HASH_ClearITPendingBit(uint8_t HASH_IT); - -/* High Level SHA1 functions **************************************************/ -ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]); -ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, - uint8_t *Input, uint32_t Ilen, - uint8_t Output[20]); - -/* High Level MD5 functions ***************************************************/ -ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]); -ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, - uint8_t *Input, uint32_t Ilen, - uint8_t Output[16]); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_HASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h deleted file mode 100644 index ffba64cd5..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h +++ /dev/null @@ -1,692 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_i2c.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the I2C firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_I2C_H -#define __STM32F4xx_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -}I2C_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2) || \ - ((PERIPH) == I2C3)) -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_duty_cycle_in_fast_mode - * @{ - */ - -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ - ((CYCLE) == I2C_DutyCycle_2)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) -#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ - ((STATE) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_DR ((uint8_t)0x10) -#define I2C_Register_SR1 ((uint8_t)0x14) -#define I2C_Register_SR2 ((uint8_t)0x18) -#define I2C_Register_CCR ((uint8_t)0x1C) -#define I2C_Register_TRISE ((uint8_t)0x20) -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_DR) || \ - ((REGISTER) == I2C_Register_SR1) || \ - ((REGISTER) == I2C_Register_SR2) || \ - ((REGISTER) == I2C_Register_CCR) || \ - ((REGISTER) == I2C_Register_TRISE)) -/** - * @} - */ - -/** @defgroup I2C_NACK_position - * @{ - */ - -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ - ((POSITION) == I2C_NACKPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_SMBus_alert_pin_level - * @{ - */ - -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) -#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ - ((ALERT) == I2C_SMBusAlert_High)) -/** - * @} - */ - -/** @defgroup I2C_PEC_position - * @{ - */ - -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ - ((POSITION) == I2C_PECPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ - ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ - ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ - ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -/** - * @brief SR2 register flags - */ - -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/** - * @brief SR1 register flags - */ - -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ - ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ - ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ - ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ - ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ - ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ - ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ - ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_SB)) -/** - * @} - */ - -/** @defgroup I2C_Events - * @{ - */ - -/** - =============================================================================== - I2C Master Events (Events grouped in order of communication) - =============================================================================== - */ - -/** - * @brief Communication start - * - * After sending the START condition (I2C_GenerateSTART() function) the master - * has to wait for this event. It means that the Start condition has been correctly - * released on the I2C bus (the bus is free, no other devices is communicating). - * - */ -/* --EV5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/** - * @brief Address Acknowledge - * - * After checking on EV5 (start condition correctly released on the bus), the - * master sends the address of the slave(s) with which it will communicate - * (I2C_Send7bitAddress() function, it also determines the direction of the communication: - * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will - * be set: - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (just after generating the START - * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() - * function). Then master should wait on EV9. It means that the 10-bit addressing - * header has been correctly sent on the bus. Then master should send the second part of - * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master - * should wait for event EV6. - * - */ - -/* --EV6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/* --EV9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/** - * @brief Communication events - * - * If a communication is established (START condition generated and slave address - * acknowledged) then the master has to check on one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EV7 then to read - * the data received from the slave (I2C_ReceiveData() function). - * - * 2) Master Transmitter mode: The master has to send data (I2C_SendData() - * function) then to wait on event EV8 or EV8_2. - * These two events are similar: - * - EV8 means that the data has been written in the data register and is - * being shifted out. - * - EV8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EV8 is sufficient for the application. - * Using EV8_2 leads to a slower communication but ensure more reliable test. - * EV8_2 is also more suitable than EV8 for testing on the last data transmission - * (before Stop condition generation). - * - * @note In case the user software does not guarantee that this event EV7 is - * managed before the current byte end of transfer, then user may check on EV7 - * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Master RECEIVER mode -----------------------------*/ -/* --EV7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master TRANSMITTER mode --------------------------*/ -/* --EV8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* --EV8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - - -/** - =============================================================================== - I2C Slave Events (Events grouped in order of communication) - =============================================================================== - */ - - -/** - * @brief Communication start events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a Start condition on the bus (generated by master - * device) followed by the peripheral address. The peripheral generates an ACK - * condition on the bus (if the acknowledge feature is enabled through function - * I2C_AcknowledgeConfig()) and the events listed above are set : - * - * 1) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * 2) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * 3) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* --EV1 (all the events below are variants of EV1) */ -/* 1) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* 2) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* 3) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/** - * @brief Communication events - * - * Wait on one of these events when EV1 has already been checked and: - * - * - Slave RECEIVER mode: - * - EV2: When the application is expecting a data byte to be received. - * - EV4: When the application is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EV3: When a byte has been transmitted by the slave and the application is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be - * used when the user software doesn't guarantee the EV3 is managed before the - * current byte end of transfer. - * - EV3_2: When the master sends a NACK in order to tell slave that data transmission - * shall end (before sending the STOP condition). In this case slave has to stop sending - * data bytes and expect a Stop condition on the bus. - * - * @note In case the user software does not guarantee that the event EV2 is - * managed before the current byte end of transfer, then user may check on EV2 - * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Slave RECEIVER mode --------------------------*/ -/* --EV2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* --EV4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave TRANSMITTER mode -----------------------*/ -/* --EV3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/* --EV3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - -/* - =============================================================================== - End of Events Description - =============================================================================== - */ - -#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ - ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ - ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) -/** - * @} - */ - -/** @defgroup I2C_clock_speed - * @{ - */ - -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the I2C configuration to the default reset state *****/ -void I2C_DeInit(I2C_TypeDef* I2Cx); - -/* Initialization and Configuration functions *********************************/ -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); - -/* PEC management functions ***************************************************/ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); - -/* DMA transfers management functions *****************************************/ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - -/* Interrupts, events and flags management functions **************************/ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); - -/* - =============================================================================== - I2C State Monitoring Functions - =============================================================================== - This I2C driver provides three different ways for I2C state monitoring - depending on the application requirements and constraints: - - - 1. Basic state monitoring (Using I2C_CheckEvent() function) - ----------------------------------------------------------- - It compares the status registers (SR1 and SR2) content to a given event - (can be the combination of one or more flags). - It returns SUCCESS if the current status includes the given flags - and returns ERROR if one or more flags are missing in the current status. - - - When to use - - This function is suitable for most applications as well as for startup - activity since the events are fully described in the product reference - manual (RM0090). - - It is also suitable for users who need to define their own events. - - - Limitations - - If an error occurs (ie. error flags are set besides to the monitored - flags), the I2C_CheckEvent() function may return SUCCESS despite - the communication hold or corrupted real state. - In this case, it is advised to use error interrupts to monitor - the error events and handle them in the interrupt IRQ handler. - - Note - For error management, it is advised to use the following functions: - - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - Where x is the peripheral instance (I2C1, I2C2 ...) - - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the - I2Cx_ER_IRQHandler() function in order to determine which error occurred. - - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - and/or I2C_GenerateStop() in order to clear the error flag and source - and return to correct communication status. - - - 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) - -------------------------------------------------------------------- - Using the function I2C_GetLastEvent() which returns the image of both status - registers in a single word (uint32_t) (Status Register 2 value is shifted left - by 16 bits and concatenated to Status Register 1). - - - When to use - - This function is suitable for the same applications above but it - allows to overcome the mentioned limitation of I2C_GetFlagStatus() - function. - - The returned value could be compared to events already defined in - this file or to custom values defined by user. - This function is suitable when multiple flags are monitored at the - same time. - - At the opposite of I2C_CheckEvent() function, this function allows - user to choose when an event is accepted (when all events flags are - set and no other flags are set or just when the needed flags are set - like I2C_CheckEvent() function. - - - Limitations - - User may need to define his own events. - - Same remark concerning the error management is applicable for this - function if user decides to check only regular communication flags - (and ignores error flags). - - - 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) - ----------------------------------------------------------------------- - - Using the function I2C_GetFlagStatus() which simply returns the status of - one single flag (ie. I2C_FLAG_RXNE ...). - - - When to use - - This function could be used for specific applications or in debug - phase. - - It is suitable when only one flag checking is needed (most I2C - events are monitored through multiple flags). - - Limitations: - - When calling this function, the Status register is accessed. - Some flags are cleared when the status register is accessed. - So checking the status of one Flag, may clear other ones. - - Function may need to be called twice or more in order to monitor - one single event. - */ - -/* - =============================================================================== - 1. Basic state monitoring - =============================================================================== - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/* - =============================================================================== - 2. Advanced state monitoring - =============================================================================== - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/* - =============================================================================== - 3. Flag-based state monitoring - =============================================================================== - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - - -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_I2C_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h deleted file mode 100644 index 3b034304f..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_iwdg.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the IWDG - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_IWDG_H -#define __STM32F4xx_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup IWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup IWDG_Exported_Constants - * @{ - */ - -/** @defgroup IWDG_WriteAccess - * @{ - */ -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) -#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ - ((ACCESS) == IWDG_WriteAccess_Disable)) -/** - * @} - */ - -/** @defgroup IWDG_prescaler - * @{ - */ -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) -#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ - ((PRESCALER) == IWDG_Prescaler_8) || \ - ((PRESCALER) == IWDG_Prescaler_16) || \ - ((PRESCALER) == IWDG_Prescaler_32) || \ - ((PRESCALER) == IWDG_Prescaler_64) || \ - ((PRESCALER) == IWDG_Prescaler_128)|| \ - ((PRESCALER) == IWDG_Prescaler_256)) -/** - * @} - */ - -/** @defgroup IWDG_Flag - * @{ - */ -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) -#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) -#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Prescaler and Counter configuration functions ******************************/ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); - -/* IWDG activation function ***************************************************/ -void IWDG_Enable(void); - -/* Flag management function ***************************************************/ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_IWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h deleted file mode 100644 index bf25ef2e5..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h +++ /dev/null @@ -1,163 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_pwr.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_PWR_H -#define __STM32F4xx_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PWR_PVD_detection_level - * @{ - */ - -#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 - -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ - ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ - ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ - ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) -/** - * @} - */ - - -/** @defgroup PWR_Regulator_state_in_STOP_mode - * @{ - */ - -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower PWR_CR_LPDS -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ - ((REGULATOR) == PWR_Regulator_LowPower)) -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry - * @{ - */ - -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) - -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ - -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO -#define PWR_FLAG_BRR PWR_CSR_BRR -#define PWR_FLAG_REGRDY PWR_CSR_REGRDY - -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \ - ((FLAG) == PWR_FLAG_REGRDY)) - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the PWR configuration to the default reset state ******/ -void PWR_DeInit(void); - -/* Backup Domain Access function **********************************************/ -void PWR_BackupAccessCmd(FunctionalState NewState); - -/* PVD configuration functions ************************************************/ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_PVDCmd(FunctionalState NewState); - -/* WakeUp pins configuration functions ****************************************/ -void PWR_WakeUpPinCmd(FunctionalState NewState); - -/* Backup Regulator configuration functions ***********************************/ -void PWR_BackupRegulatorCmd(FunctionalState NewState); - -/* Performance Mode and FLASH Power Down configuration functions **************/ -void PWR_HighPerformanceModeCmd(FunctionalState NewState); -void PWR_FlashPowerDownCmd(FunctionalState NewState); - -/* Low Power modes configuration functions ************************************/ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); - -/* Flags management functions *************************************************/ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_PWR_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h deleted file mode 100644 index 914408afb..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h +++ /dev/null @@ -1,509 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rcc.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the RCC firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_RCC_H -#define __STM32F4xx_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ -}RCC_ClocksTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup RCC_HSE_configuration - * @{ - */ -#define RCC_HSE_OFF ((uint8_t)0x00) -#define RCC_HSE_ON ((uint8_t)0x01) -#define RCC_HSE_Bypass ((uint8_t)0x05) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source - * @{ - */ -#define RCC_PLLSource_HSI ((uint32_t)0x00000000) -#define RCC_PLLSource_HSE ((uint32_t)0x00400000) -#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ - ((SOURCE) == RCC_PLLSource_HSE)) -#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) -#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) -#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) - -#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source - * @{ - */ -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source - * @{ - */ -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source - * @{ - */ -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00001000) -#define RCC_HCLK_Div4 ((uint32_t)0x00001400) -#define RCC_HCLK_Div8 ((uint32_t)0x00001800) -#define RCC_HCLK_Div16 ((uint32_t)0x00001C00) -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_Interrupt_Source - * @{ - */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) -#define RCC_IT_CSS ((uint8_t)0x80) -#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) -#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ - ((IT) == RCC_IT_PLLI2SRDY)) -#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration - * @{ - */ -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source - * @{ - */ -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) -#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) -#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) -#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) -#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) -#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) -#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) -#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) -#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) -#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) -#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) -#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) -#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) -#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) -#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) -#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) -#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) -#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) -#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) -#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) -#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) -#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) -#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) -#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) -#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) -#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) -#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) -#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) -#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) -#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) -/** - * @} - */ - -/** @defgroup RCC_I2S_Clock_Source - * @{ - */ -#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) -#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) - -#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) -/** - * @} - */ - -/** @defgroup RCC_AHB1_Peripherals - * @{ - */ -#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) -#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) -#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) -#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) -#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) -#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) -#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) -#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) -#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) -#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) -#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) -#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) -#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) -#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) -#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) -#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) -#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) -#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) -#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) -#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) -#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) -#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) -#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x819BEE00) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_AHB2_Peripherals - * @{ - */ -#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) -#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) -#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) -#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) -#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) -#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_AHB3_Peripherals - * @{ - */ -#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) -#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripherals - * @{ - */ -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) -#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) -#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripherals - * @{ - */ -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) -#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) -#define RCC_APB2Periph_ADC ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) -#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) -#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) -#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) -#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_MCO1_Clock_Source_Prescaler - * @{ - */ -#define RCC_MCO1Source_HSI ((uint32_t)0x00000000) -#define RCC_MCO1Source_LSE ((uint32_t)0x00200000) -#define RCC_MCO1Source_HSE ((uint32_t)0x00400000) -#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) -#define RCC_MCO1Div_1 ((uint32_t)0x00000000) -#define RCC_MCO1Div_2 ((uint32_t)0x04000000) -#define RCC_MCO1Div_3 ((uint32_t)0x05000000) -#define RCC_MCO1Div_4 ((uint32_t)0x06000000) -#define RCC_MCO1Div_5 ((uint32_t)0x07000000) -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ - ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) - -#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ - ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ - ((DIV) == RCC_MCO1Div_5)) -/** - * @} - */ - -/** @defgroup RCC_MCO2_Clock_Source_Prescaler - * @{ - */ -#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) -#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) -#define RCC_MCO2Source_HSE ((uint32_t)0x80000000) -#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) -#define RCC_MCO2Div_1 ((uint32_t)0x00000000) -#define RCC_MCO2Div_2 ((uint32_t)0x20000000) -#define RCC_MCO2Div_3 ((uint32_t)0x28000000) -#define RCC_MCO2Div_4 ((uint32_t)0x30000000) -#define RCC_MCO2Div_5 ((uint32_t)0x38000000) -#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ - ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) - -#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ - ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ - ((DIV) == RCC_MCO2Div_5)) -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_BORRST ((uint8_t)0x79) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) -#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ - ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ - ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ - ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ - ((FLAG) == RCC_FLAG_PLLI2SRDY)) -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RCC clock configuration to the default reset state */ -void RCC_DeInit(void); - -/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ -void RCC_HSEConfig(uint8_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); - -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); -void RCC_PLLI2SCmd(FunctionalState NewState); - -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); -void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); - -/* System, AHB and APB busses clocks configuration functions ******************/ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); - -/* Peripheral clocks configuration functions **********************************/ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); - -void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_RCC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h deleted file mode 100644 index 63f9185fc..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rng.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the Random - * Number Generator(RNG) firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_RNG_H -#define __STM32F4xx_RNG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RNG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RNG_Exported_Constants - * @{ - */ - -/** @defgroup RNG_flags_definition - * @{ - */ -#define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */ -#define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */ -#define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */ - -#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \ - ((RNG_FLAG) == RNG_FLAG_CECS) || \ - ((RNG_FLAG) == RNG_FLAG_SECS)) -#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \ - ((RNG_FLAG) == RNG_FLAG_SECS)) -/** - * @} - */ - -/** @defgroup RNG_interrupts_definition - * @{ - */ -#define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */ -#define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */ - -#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00)) -#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RNG configuration to the default reset state *****/ -void RNG_DeInit(void); - -/* Configuration function *****************************************************/ -void RNG_Cmd(FunctionalState NewState); - -/* Get 32 bit Random number function ******************************************/ -uint32_t RNG_GetRandomNumber(void); - -/* Interrupts and flags management functions **********************************/ -void RNG_ITConfig(FunctionalState NewState); -FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); -void RNG_ClearFlag(uint8_t RNG_FLAG); -ITStatus RNG_GetITStatus(uint8_t RNG_IT); -void RNG_ClearITPendingBit(uint8_t RNG_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_RNG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h deleted file mode 100644 index 9daafc7bd..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h +++ /dev/null @@ -1,875 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rtc.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_RTC_H -#define __STM32F4xx_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief RTC Init structures definition - */ -typedef struct -{ - uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be set to a value lower than 0x7F */ - - uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be set to a value lower than 0x7FFF */ -}RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. - This parameter must be set to a value in the 0-12 range - if the RTC_HourFormat_12 is selected or 0-23 range if - the RTC_HourFormat_24 is selected. */ - - uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ -}RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format). - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t RTC_Date; /*!< Specifies the RTC Date. - This parameter must be set to a value in the 1-31 range. */ - - uint8_t RTC_Year; /*!< Specifies the RTC Date Year. - This parameter must be set to a value in the 0-99 range. */ -}RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ - - uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - - uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - If the Alarm Date is selected, this parameter - must be set to a value in the 1-31 range. - If the Alarm WeekDay is selected, this - parameter can be a value of @ref RTC_WeekDay_Definitions */ -}RTC_AlarmTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - - -/** @defgroup RTC_Hour_Formats - * @{ - */ -#define RTC_HourFormat_24 ((uint32_t)0x00000000) -#define RTC_HourFormat_12 ((uint32_t)0x00000040) -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ - ((FORMAT) == RTC_HourFormat_24)) -/** - * @} - */ - -/** @defgroup RTC_Asynchronous_Predivider - * @{ - */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) - -/** - * @} - */ - - -/** @defgroup RTC_Synchronous_Predivider - * @{ - */ -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF) - -/** - * @} - */ - -/** @defgroup RTC_Time_Definitions - * @{ - */ -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) - -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions - * @{ - */ -#define RTC_H12_AM ((uint8_t)0x00) -#define RTC_H12_PM ((uint8_t)0x40) -#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) - -/** - * @} - */ - -/** @defgroup RTC_Year_Date_Definitions - * @{ - */ -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) - -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions - * @{ - */ - -/* Coded in BCD format */ -#define RTC_Month_January ((uint8_t)0x01) -#define RTC_Month_February ((uint8_t)0x02) -#define RTC_Month_March ((uint8_t)0x03) -#define RTC_Month_April ((uint8_t)0x04) -#define RTC_Month_May ((uint8_t)0x05) -#define RTC_Month_June ((uint8_t)0x06) -#define RTC_Month_July ((uint8_t)0x07) -#define RTC_Month_August ((uint8_t)0x08) -#define RTC_Month_September ((uint8_t)0x09) -#define RTC_Month_October ((uint8_t)0x10) -#define RTC_Month_November ((uint8_t)0x11) -#define RTC_Month_December ((uint8_t)0x12) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) - -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions - * @{ - */ - -#define RTC_Weekday_Monday ((uint8_t)0x01) -#define RTC_Weekday_Tuesday ((uint8_t)0x02) -#define RTC_Weekday_Wednesday ((uint8_t)0x03) -#define RTC_Weekday_Thursday ((uint8_t)0x04) -#define RTC_Weekday_Friday ((uint8_t)0x05) -#define RTC_Weekday_Saturday ((uint8_t)0x06) -#define RTC_Weekday_Sunday ((uint8_t)0x07) -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) -/** - * @} - */ - - -/** @defgroup RTC_Alarm_Definitions - * @{ - */ -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmDateWeekDay_Definitions - * @{ - */ -#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) -#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ - ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmMask_Definitions - * @{ - */ -#define RTC_AlarmMask_None ((uint32_t)0x00000000) -#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) -#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) -#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) -#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) -#define RTC_AlarmMask_All ((uint32_t)0x80808080) -#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions - * @{ - */ -#define RTC_Alarm_A ((uint32_t)0x00000100) -#define RTC_Alarm_B ((uint32_t)0x00000200) -#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) -#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) - -/** - * @} - */ - - /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions - * @{ - */ -#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm - comparison.Only SS[11:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm - comparison.Only SS[13:0] are compared */ -#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match - to activate alarm. */ -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14) || \ - ((MASK) == RTC_AlarmSubSecondMask_None)) -/** - * @} - */ - -/** @defgroup RTC_Alarm_Sub_Seconds_Value - * @{ - */ - -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) - -/** - * @} - */ - -/** @defgroup RTC_Wakeup_Timer_Definitions - * @{ - */ -#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) -#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) -#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) -#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) -#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) -#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) -/** - * @} - */ - -/** @defgroup RTC_Time_Stamp_Edges_definitions - * @{ - */ -#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) -#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) -#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ - ((EDGE) == RTC_TimeStampEdge_Falling)) -/** - * @} - */ - -/** @defgroup RTC_Output_selection_Definitions - * @{ - */ -#define RTC_Output_Disable ((uint32_t)0x00000000) -#define RTC_Output_AlarmA ((uint32_t)0x00200000) -#define RTC_Output_AlarmB ((uint32_t)0x00400000) -#define RTC_Output_WakeUp ((uint32_t)0x00600000) - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ - ((OUTPUT) == RTC_Output_AlarmA) || \ - ((OUTPUT) == RTC_Output_AlarmB) || \ - ((OUTPUT) == RTC_Output_WakeUp)) - -/** - * @} - */ - -/** @defgroup RTC_Output_Polarity_Definitions - * @{ - */ -#define RTC_OutputPolarity_High ((uint32_t)0x00000000) -#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ - ((POL) == RTC_OutputPolarity_Low)) -/** - * @} - */ - - -/** @defgroup RTC_Digital_Calibration_Definitions - * @{ - */ -#define RTC_CalibSign_Positive ((uint32_t)0x00000000) -#define RTC_CalibSign_Negative ((uint32_t)0x00000080) -#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ - ((SIGN) == RTC_CalibSign_Negative)) -#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) - -/** - * @} - */ - - /** @defgroup RTC_Calib_Output_selection_Definitions - * @{ - */ -#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) -#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000) -#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \ - ((OUTPUT) == RTC_CalibOutput_1Hz)) -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_period_Definitions - * @{ - */ -#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 8s, else 2exp18 RTCCLK seconds */ -#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \ - ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \ - ((PERIOD) == RTC_SmoothCalibPeriod_8sec)) - -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions - * @{ - */ -#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0]. - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0]. */ -#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \ - ((PLUS) == RTC_SmoothCalibPlusPulses_Reset)) - -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions - * @{ - */ -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) - -/** - * @} - */ - -/** @defgroup RTC_DayLightSaving_Definitions - * @{ - */ -#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) -#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ - ((SAVE) == RTC_DayLightSaving_ADD1H)) - -#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) -#define RTC_StoreOperation_Set ((uint32_t)0x00040000) -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ - ((OPERATION) == RTC_StoreOperation_Set)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Trigger_Definitions - * @{ - */ -#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) -#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) -#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) -#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001) -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ - ((TRIGGER) == RTC_TamperTrigger_HighLevel)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Filter_Definitions - * @{ - */ -#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ - -#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 - consecutive samples at the active leve. */ -#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ - ((FILTER) == RTC_TamperFilter_2Sample) || \ - ((FILTER) == RTC_TamperFilter_4Sample) || \ - ((FILTER) == RTC_TamperFilter_8Sample)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions - * @{ - */ -#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ -#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) - -/** - * @} - */ - - /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions - * @{ - */ -#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ - -#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pins_Definitions - * @{ - */ -#define RTC_Tamper_1 RTC_TAFCR_TAMP1E -#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pin_Selection - * @{ - */ -#define RTC_TamperPin_PC13 ((uint32_t)0x00000000) -#define RTC_TamperPin_PI8 ((uint32_t)0x00010000) -#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \ - ((PIN) == RTC_TamperPin_PI8)) -/** - * @} - */ - -/** @defgroup RTC_TimeStamp_Pin_Selection - * @{ - */ -#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000) -#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000) -#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \ - ((PIN) == RTC_TimeStampPin_PI8)) -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT - * @{ - */ -#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) -#define RTC_OutputType_PushPull ((uint32_t)0x00040000) -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ - ((TYPE) == RTC_OutputType_PushPull)) - -/** - * @} - */ - -/** @defgroup RTC_Add_1_Second_Parameter_Definitions - * @{ - */ -#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000) -#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000) -#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \ - ((SEL) == RTC_ShiftAdd1S_Set)) -/** - * @} - */ - -/** @defgroup RTC_Substract_Fraction_Of_Second_Value - * @{ - */ -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) - -/** - * @} - */ - -/** @defgroup RTC_Backup_Registers_Definitions - * @{ - */ - -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ - ((BKP) == RTC_BKP_DR1) || \ - ((BKP) == RTC_BKP_DR2) || \ - ((BKP) == RTC_BKP_DR3) || \ - ((BKP) == RTC_BKP_DR4) || \ - ((BKP) == RTC_BKP_DR5) || \ - ((BKP) == RTC_BKP_DR6) || \ - ((BKP) == RTC_BKP_DR7) || \ - ((BKP) == RTC_BKP_DR8) || \ - ((BKP) == RTC_BKP_DR9) || \ - ((BKP) == RTC_BKP_DR10) || \ - ((BKP) == RTC_BKP_DR11) || \ - ((BKP) == RTC_BKP_DR12) || \ - ((BKP) == RTC_BKP_DR13) || \ - ((BKP) == RTC_BKP_DR14) || \ - ((BKP) == RTC_BKP_DR15) || \ - ((BKP) == RTC_BKP_DR16) || \ - ((BKP) == RTC_BKP_DR17) || \ - ((BKP) == RTC_BKP_DR18) || \ - ((BKP) == RTC_BKP_DR19)) -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions - * @{ - */ -#define RTC_Format_BIN ((uint32_t)0x000000000) -#define RTC_Format_BCD ((uint32_t)0x000000001) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) - -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions - * @{ - */ -#define RTC_FLAG_RECALPF ((uint32_t)0x00010000) -#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) -#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) -#define RTC_FLAG_TSF ((uint32_t)0x00000800) -#define RTC_FLAG_WUTF ((uint32_t)0x00000400) -#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) -#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) -#define RTC_FLAG_INITF ((uint32_t)0x00000040) -#define RTC_FLAG_RSF ((uint32_t)0x00000020) -#define RTC_FLAG_INITS ((uint32_t)0x00000010) -#define RTC_FLAG_SHPF ((uint32_t)0x00000008) -#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) -#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) -#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ - ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ - ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ - ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ - ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ - ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \ - ((FLAG) == RTC_FLAG_SHPF)) -#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET)) -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions - * @{ - */ -#define RTC_IT_TS ((uint32_t)0x00008000) -#define RTC_IT_WUT ((uint32_t)0x00004000) -#define RTC_IT_ALRB ((uint32_t)0x00002000) -#define RTC_IT_ALRA ((uint32_t)0x00001000) -#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)0x00020000) - -#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ - ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ - ((IT) == RTC_IT_TAMP1)) -#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Legacy - * @{ - */ -#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig -#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RTC configuration to the default reset state *****/ -ErrorStatus RTC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); -void RTC_WriteProtectionCmd(FunctionalState NewState); -ErrorStatus RTC_EnterInitMode(void); -void RTC_ExitInitMode(void); -ErrorStatus RTC_WaitForSynchro(void); -ErrorStatus RTC_RefClockCmd(FunctionalState NewState); -void RTC_BypassShadowCmd(FunctionalState NewState); - -/* Time and Date configuration functions **************************************/ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -uint32_t RTC_GetSubSecond(void); -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); - -/* Alarms (Alarm A and Alarm B) configuration functions **********************/ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); -void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask); -uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); - -/* WakeUp Timer configuration functions ***************************************/ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); -uint32_t RTC_GetWakeUpCounter(void); -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); - -/* Daylight Saving configuration functions ************************************/ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); -uint32_t RTC_GetStoreOperation(void); - -/* Output pin Configuration function ******************************************/ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); - -/* Digital Calibration configuration functions *********************************/ -ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value); -ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState); -void RTC_CalibOutputCmd(FunctionalState NewState); -void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput); -ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, - uint32_t RTC_SmoothCalibPlusPulses, - uint32_t RTC_SmouthCalibMinusPulsesValue); - -/* TimeStamp configuration functions ******************************************/ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct); -uint32_t RTC_GetTimeStampSubSecond(void); - -/* Tampers configuration functions ********************************************/ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); -void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); -void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); -void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); -void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); -void RTC_TamperPullUpCmd(FunctionalState NewState); - -/* Backup Data Registers configuration functions ******************************/ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); - -/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - functions ******************************************************************/ -void RTC_TamperPinSelection(uint32_t RTC_TamperPin); -void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin); -void RTC_OutputTypeConfig(uint32_t RTC_OutputType); - -/* RTC_Shift_control_synchonisation_functions *********************************/ -ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); - -/* Interrupts and flags management functions **********************************/ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); -void RTC_ClearFlag(uint32_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint32_t RTC_IT); -void RTC_ClearITPendingBit(uint32_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_RTC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h deleted file mode 100644 index aa1bff688..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h +++ /dev/null @@ -1,530 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_sdio.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the SDIO firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_SDIO_H -#define __STM32F4xx_SDIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SDIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -typedef struct -{ - uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SDIO_Clock_Edge */ - - uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is - enabled or disabled. - This parameter can be a value of @ref SDIO_Clock_Bypass */ - - uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or - disabled when the bus is idle. - This parameter can be a value of @ref SDIO_Clock_Power_Save */ - - uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. - This parameter can be a value of @ref SDIO_Bus_Wide */ - - uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ - - uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. - This parameter can be a value between 0x00 and 0xFF. */ - -} SDIO_InitTypeDef; - -typedef struct -{ - uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent - to a card as part of a command message. If a command - contains an argument, it must be loaded into this register - before writing the command to the command register */ - - uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ - - uint32_t SDIO_Response; /*!< Specifies the SDIO response type. - This parameter can be a value of @ref SDIO_Response_Type */ - - uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. - This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ - - uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_CPSM_State */ -} SDIO_CmdInitTypeDef; - -typedef struct -{ - uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ - - uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ - - uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. - This parameter can be a value of @ref SDIO_Data_Block_Size */ - - uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer - is a read or write. - This parameter can be a value of @ref SDIO_Transfer_Direction */ - - uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDIO_Transfer_Type */ - - uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_DPSM_State */ -} SDIO_DataInitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SDIO_Exported_Constants - * @{ - */ - -/** @defgroup SDIO_Clock_Edge - * @{ - */ - -#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) -#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) -#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ - ((EDGE) == SDIO_ClockEdge_Falling)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Bypass - * @{ - */ - -#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) -#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ - ((BYPASS) == SDIO_ClockBypass_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Power_Save - * @{ - */ - -#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) -#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) -#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ - ((SAVE) == SDIO_ClockPowerSave_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Bus_Wide - * @{ - */ - -#define SDIO_BusWide_1b ((uint32_t)0x00000000) -#define SDIO_BusWide_4b ((uint32_t)0x00000800) -#define SDIO_BusWide_8b ((uint32_t)0x00001000) -#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ - ((WIDE) == SDIO_BusWide_8b)) - -/** - * @} - */ - -/** @defgroup SDIO_Hardware_Flow_Control - * @{ - */ - -#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) -#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) -#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ - ((CONTROL) == SDIO_HardwareFlowControl_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Power_State - * @{ - */ - -#define SDIO_PowerState_OFF ((uint32_t)0x00000000) -#define SDIO_PowerState_ON ((uint32_t)0x00000003) -#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) -/** - * @} - */ - - -/** @defgroup SDIO_Interrupt_sources - * @{ - */ - -#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) -#define SDIO_IT_CMDREND ((uint32_t)0x00000040) -#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) -#define SDIO_IT_DATAEND ((uint32_t)0x00000100) -#define SDIO_IT_STBITERR ((uint32_t)0x00000200) -#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) -#define SDIO_IT_CMDACT ((uint32_t)0x00000800) -#define SDIO_IT_TXACT ((uint32_t)0x00001000) -#define SDIO_IT_RXACT ((uint32_t)0x00002000) -#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) -#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) -#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) -#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) -/** - * @} - */ - -/** @defgroup SDIO_Command_Index - * @{ - */ - -#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) -/** - * @} - */ - -/** @defgroup SDIO_Response_Type - * @{ - */ - -#define SDIO_Response_No ((uint32_t)0x00000000) -#define SDIO_Response_Short ((uint32_t)0x00000040) -#define SDIO_Response_Long ((uint32_t)0x000000C0) -#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ - ((RESPONSE) == SDIO_Response_Short) || \ - ((RESPONSE) == SDIO_Response_Long)) -/** - * @} - */ - -/** @defgroup SDIO_Wait_Interrupt_State - * @{ - */ - -#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ -#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ -#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ -#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ - ((WAIT) == SDIO_Wait_Pend)) -/** - * @} - */ - -/** @defgroup SDIO_CPSM_State - * @{ - */ - -#define SDIO_CPSM_Disable ((uint32_t)0x00000000) -#define SDIO_CPSM_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Response_Registers - * @{ - */ - -#define SDIO_RESP1 ((uint32_t)0x00000000) -#define SDIO_RESP2 ((uint32_t)0x00000004) -#define SDIO_RESP3 ((uint32_t)0x00000008) -#define SDIO_RESP4 ((uint32_t)0x0000000C) -#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ - ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) -/** - * @} - */ - -/** @defgroup SDIO_Data_Length - * @{ - */ - -#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) -/** - * @} - */ - -/** @defgroup SDIO_Data_Block_Size - * @{ - */ - -#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) -#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) -#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) -#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) -#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) -#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) -#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) -#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) -#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) -#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) -#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) -#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) -#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) -#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) -#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) -#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ - ((SIZE) == SDIO_DataBlockSize_2b) || \ - ((SIZE) == SDIO_DataBlockSize_4b) || \ - ((SIZE) == SDIO_DataBlockSize_8b) || \ - ((SIZE) == SDIO_DataBlockSize_16b) || \ - ((SIZE) == SDIO_DataBlockSize_32b) || \ - ((SIZE) == SDIO_DataBlockSize_64b) || \ - ((SIZE) == SDIO_DataBlockSize_128b) || \ - ((SIZE) == SDIO_DataBlockSize_256b) || \ - ((SIZE) == SDIO_DataBlockSize_512b) || \ - ((SIZE) == SDIO_DataBlockSize_1024b) || \ - ((SIZE) == SDIO_DataBlockSize_2048b) || \ - ((SIZE) == SDIO_DataBlockSize_4096b) || \ - ((SIZE) == SDIO_DataBlockSize_8192b) || \ - ((SIZE) == SDIO_DataBlockSize_16384b)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Direction - * @{ - */ - -#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) -#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) -#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ - ((DIR) == SDIO_TransferDir_ToSDIO)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Type - * @{ - */ - -#define SDIO_TransferMode_Block ((uint32_t)0x00000000) -#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) -#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ - ((MODE) == SDIO_TransferMode_Block)) -/** - * @} - */ - -/** @defgroup SDIO_DPSM_State - * @{ - */ - -#define SDIO_DPSM_Disable ((uint32_t)0x00000000) -#define SDIO_DPSM_Enable ((uint32_t)0x00000001) -#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Flags - * @{ - */ - -#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) -#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) -#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) -#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) -#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) -#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) -#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) -#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) -#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) -#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) -#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) -#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) -#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_TXUNDERR) || \ - ((FLAG) == SDIO_FLAG_RXOVERR) || \ - ((FLAG) == SDIO_FLAG_CMDREND) || \ - ((FLAG) == SDIO_FLAG_CMDSENT) || \ - ((FLAG) == SDIO_FLAG_DATAEND) || \ - ((FLAG) == SDIO_FLAG_STBITERR) || \ - ((FLAG) == SDIO_FLAG_DBCKEND) || \ - ((FLAG) == SDIO_FLAG_CMDACT) || \ - ((FLAG) == SDIO_FLAG_TXACT) || \ - ((FLAG) == SDIO_FLAG_RXACT) || \ - ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOF) || \ - ((FLAG) == SDIO_FLAG_RXFIFOF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOE) || \ - ((FLAG) == SDIO_FLAG_TXDAVL) || \ - ((FLAG) == SDIO_FLAG_RXDAVL) || \ - ((FLAG) == SDIO_FLAG_SDIOIT) || \ - ((FLAG) == SDIO_FLAG_CEATAEND)) - -#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) - -#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ - ((IT) == SDIO_IT_DCRCFAIL) || \ - ((IT) == SDIO_IT_CTIMEOUT) || \ - ((IT) == SDIO_IT_DTIMEOUT) || \ - ((IT) == SDIO_IT_TXUNDERR) || \ - ((IT) == SDIO_IT_RXOVERR) || \ - ((IT) == SDIO_IT_CMDREND) || \ - ((IT) == SDIO_IT_CMDSENT) || \ - ((IT) == SDIO_IT_DATAEND) || \ - ((IT) == SDIO_IT_STBITERR) || \ - ((IT) == SDIO_IT_DBCKEND) || \ - ((IT) == SDIO_IT_CMDACT) || \ - ((IT) == SDIO_IT_TXACT) || \ - ((IT) == SDIO_IT_RXACT) || \ - ((IT) == SDIO_IT_TXFIFOHE) || \ - ((IT) == SDIO_IT_RXFIFOHF) || \ - ((IT) == SDIO_IT_TXFIFOF) || \ - ((IT) == SDIO_IT_RXFIFOF) || \ - ((IT) == SDIO_IT_TXFIFOE) || \ - ((IT) == SDIO_IT_RXFIFOE) || \ - ((IT) == SDIO_IT_TXDAVL) || \ - ((IT) == SDIO_IT_RXDAVL) || \ - ((IT) == SDIO_IT_SDIOIT) || \ - ((IT) == SDIO_IT_CEATAEND)) - -#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup SDIO_Read_Wait_Mode - * @{ - */ - -#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000) -#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001) -#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ - ((MODE) == SDIO_ReadWaitMode_DATA2)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/* Function used to set the SDIO configuration to the default reset state ****/ -void SDIO_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_ClockCmd(FunctionalState NewState); -void SDIO_SetPowerState(uint32_t SDIO_PowerState); -uint32_t SDIO_GetPowerState(void); - -/* Command path state machine (CPSM) management functions *********************/ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); -uint8_t SDIO_GetCommandResponse(void); -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); - -/* Data path state machine (DPSM) management functions ************************/ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -uint32_t SDIO_GetDataCounter(void); -uint32_t SDIO_ReadData(void); -void SDIO_WriteData(uint32_t Data); -uint32_t SDIO_GetFIFOCount(void); - -/* SDIO IO Cards mode management functions ************************************/ -void SDIO_StartSDIOReadWait(FunctionalState NewState); -void SDIO_StopSDIOReadWait(FunctionalState NewState); -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); -void SDIO_SetSDIOOperation(FunctionalState NewState); -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); - -/* CE-ATA mode management functions *******************************************/ -void SDIO_CommandCompletionCmd(FunctionalState NewState); -void SDIO_CEATAITCmd(FunctionalState NewState); -void SDIO_SendCEATACmd(FunctionalState NewState); - -/* DMA transfers management functions *****************************************/ -void SDIO_DMACmd(FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); -void SDIO_ClearFlag(uint32_t SDIO_FLAG); -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); -void SDIO_ClearITPendingBit(uint32_t SDIO_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_SDIO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h deleted file mode 100644 index db43fb3f3..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h +++ /dev/null @@ -1,537 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_spi.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the SPI - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_SPI_H -#define __STM32F4xx_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - - uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3) || \ - ((PERIPH) == I2S2ext) || \ - ((PERIPH) == I2S3ext)) - -#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3) || \ - ((PERIPH) == I2S2ext) || \ - ((PERIPH) == I2S3ext)) - -#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \ - ((PERIPH) == I2S2ext)) - - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ - ((DATASIZE) == SPI_DataSize_8b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx)|| \ - ((MODE) == I2S_Mode_MasterRx)) -/** - * @} - */ - - -/** @defgroup SPI_I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup SPI_I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ - ((FREQ) <= I2S_AudioFreq_192k)) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) -#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ - -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define I2S_IT_UDR ((uint8_t)0x53) -#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58) - -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) - -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) - -#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) - -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ - ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\ - ((IT) == SPI_I2S_IT_TIFRFE)) -/** - * @} - */ - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) -#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100) - -#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ - ((FLAG) == SPI_I2S_FLAG_TIFRFE)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** @defgroup SPI_I2S_Legacy - * @{ - */ - -#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx -#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx -#define SPI_IT_TXE SPI_I2S_IT_TXE -#define SPI_IT_RXNE SPI_I2S_IT_RXNE -#define SPI_IT_ERR SPI_I2S_IT_ERR -#define SPI_IT_OVR SPI_I2S_IT_OVR -#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE -#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE -#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR -#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY -#define SPI_DeInit SPI_I2S_DeInit -#define SPI_ITConfig SPI_I2S_ITConfig -#define SPI_DMACmd SPI_I2S_DMACmd -#define SPI_SendData SPI_I2S_SendData -#define SPI_ReceiveData SPI_I2S_ReceiveData -#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus -#define SPI_ClearFlag SPI_I2S_ClearFlag -#define SPI_GetITStatus SPI_I2S_GetITStatus -#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the SPI configuration to the default reset state *****/ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); - -/* Initialization and Configuration functions *********************************/ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - -void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct); - -/* Data transfers functions ***************************************************/ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); - -/* Hardware CRC Calculation functions *****************************************/ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); - -/* DMA transfers management functions *****************************************/ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_SPI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h deleted file mode 100644 index 80b66ff84..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h +++ /dev/null @@ -1,173 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_syscfg.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the SYSCFG firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_SYSCFG_H -#define __STM32F4xx_SYSCFG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SYSCFG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SYSCFG_Exported_Constants - * @{ - */ - -/** @defgroup SYSCFG_EXTI_Port_Sources - * @{ - */ -#define EXTI_PortSourceGPIOA ((uint8_t)0x00) -#define EXTI_PortSourceGPIOB ((uint8_t)0x01) -#define EXTI_PortSourceGPIOC ((uint8_t)0x02) -#define EXTI_PortSourceGPIOD ((uint8_t)0x03) -#define EXTI_PortSourceGPIOE ((uint8_t)0x04) -#define EXTI_PortSourceGPIOF ((uint8_t)0x05) -#define EXTI_PortSourceGPIOG ((uint8_t)0x06) -#define EXTI_PortSourceGPIOH ((uint8_t)0x07) -#define EXTI_PortSourceGPIOI ((uint8_t)0x08) - -#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOI)) -/** - * @} - */ - - -/** @defgroup SYSCFG_EXTI_Pin_Sources - * @{ - */ -#define EXTI_PinSource0 ((uint8_t)0x00) -#define EXTI_PinSource1 ((uint8_t)0x01) -#define EXTI_PinSource2 ((uint8_t)0x02) -#define EXTI_PinSource3 ((uint8_t)0x03) -#define EXTI_PinSource4 ((uint8_t)0x04) -#define EXTI_PinSource5 ((uint8_t)0x05) -#define EXTI_PinSource6 ((uint8_t)0x06) -#define EXTI_PinSource7 ((uint8_t)0x07) -#define EXTI_PinSource8 ((uint8_t)0x08) -#define EXTI_PinSource9 ((uint8_t)0x09) -#define EXTI_PinSource10 ((uint8_t)0x0A) -#define EXTI_PinSource11 ((uint8_t)0x0B) -#define EXTI_PinSource12 ((uint8_t)0x0C) -#define EXTI_PinSource13 ((uint8_t)0x0D) -#define EXTI_PinSource14 ((uint8_t)0x0E) -#define EXTI_PinSource15 ((uint8_t)0x0F) -#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ - ((PINSOURCE) == EXTI_PinSource1) || \ - ((PINSOURCE) == EXTI_PinSource2) || \ - ((PINSOURCE) == EXTI_PinSource3) || \ - ((PINSOURCE) == EXTI_PinSource4) || \ - ((PINSOURCE) == EXTI_PinSource5) || \ - ((PINSOURCE) == EXTI_PinSource6) || \ - ((PINSOURCE) == EXTI_PinSource7) || \ - ((PINSOURCE) == EXTI_PinSource8) || \ - ((PINSOURCE) == EXTI_PinSource9) || \ - ((PINSOURCE) == EXTI_PinSource10) || \ - ((PINSOURCE) == EXTI_PinSource11) || \ - ((PINSOURCE) == EXTI_PinSource12) || \ - ((PINSOURCE) == EXTI_PinSource13) || \ - ((PINSOURCE) == EXTI_PinSource14) || \ - ((PINSOURCE) == EXTI_PinSource15)) -/** - * @} - */ - - -/** @defgroup SYSCFG_Memory_Remap_Config - * @{ - */ -#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) -#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) -#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02) -#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) - -#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ - ((REMAP) == SYSCFG_MemoryRemap_FSMC)) -/** - * @} - */ - - -/** @defgroup SYSCFG_ETHERNET_Media_Interface - * @{ - */ -#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) -#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) - -#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \ - ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void SYSCFG_DeInit(void); -void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); -void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); -void SYSCFG_CompensationCellCmd(FunctionalState NewState); -FlagStatus SYSCFG_GetCompensationCellStatus(void); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_SYSCFG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h deleted file mode 100644 index 9bc8b698a..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h +++ /dev/null @@ -1,1144 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_tim.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the TIM firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_TIM_H -#define __STM32F4xx_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief TIM Time Base Init structure definition - * @note This structure is used with all TIMx except for TIM6 and TIM7. - */ - -typedef struct -{ - uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/** - * @brief TIM Output Compare Init structure definition - */ - -typedef struct -{ - uint16_t TIM_OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_State */ - - uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -typedef struct -{ - - uint16_t TIM_Channel; /*!< Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/** - * @brief BDTR structure definition - * @note This structure is used only with TIM1 and TIM8. - */ - -typedef struct -{ - - uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref TIM_Lock_level */ - - uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref TIM_Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup TIM_Exported_constants - * @{ - */ - -#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10) || \ - ((PERIPH) == TIM11) || \ - ((PERIPH) == TIM12) || \ - (((PERIPH) == TIM13) || \ - ((PERIPH) == TIM14))) -/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ -#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10) || \ - ((PERIPH) == TIM11) || \ - ((PERIPH) == TIM12) || \ - ((PERIPH) == TIM13) || \ - ((PERIPH) == TIM14)) - -/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */ -#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM12)) -/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */ -#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8)) -/* LIST4: TIM1 and TIM8 */ -#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM8)) -/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ -#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8)) -/* LIST6: TIM2, TIM5 and TIM11 */ -#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \ - ((TIMx) == TIM5) || \ - ((TIMx) == TIM11)) - -/** @defgroup TIM_Output_Compare_and_PWM_modes - * @{ - */ - -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2)) -#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_ForcedAction_Active) || \ - ((MODE) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode - * @{ - */ - -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ - ((MODE) == TIM_OPMode_Repetitive)) -/** - * @} - */ - -/** @defgroup TIM_Channel - * @{ - */ - -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3) || \ - ((CHANNEL) == TIM_Channel_4)) - -#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2)) -#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Division_CKD - * @{ - */ - -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) -#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ - ((DIV) == TIM_CKD_DIV2) || \ - ((DIV) == TIM_CKD_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode - * @{ - */ - -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ - ((MODE) == TIM_CounterMode_Down) || \ - ((MODE) == TIM_CounterMode_CenterAligned1) || \ - ((MODE) == TIM_CounterMode_CenterAligned2) || \ - ((MODE) == TIM_CounterMode_CenterAligned3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity - * @{ - */ - -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ - ((POLARITY) == TIM_OCPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity - * @{ - */ - -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ - ((POLARITY) == TIM_OCNPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State - * @{ - */ - -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ - ((STATE) == TIM_OutputState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_State - * @{ - */ - -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ - ((STATE) == TIM_OutputNState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_State - * @{ - */ - -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) -#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ - ((CCX) == TIM_CCx_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_N_State - * @{ - */ - -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) -#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ - ((CCXN) == TIM_CCxN_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable - * @{ - */ - -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ - ((STATE) == TIM_Break_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity - * @{ - */ - -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ - ((POLARITY) == TIM_BreakPolarity_High)) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset - * @{ - */ - -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ - ((STATE) == TIM_AutomaticOutput_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Lock_level - * @{ - */ - -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ - ((LEVEL) == TIM_LOCKLevel_1) || \ - ((LEVEL) == TIM_LOCKLevel_2) || \ - ((LEVEL) == TIM_LOCKLevel_3)) -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state - * @{ - */ - -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ - ((STATE) == TIM_OSSIState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state - * @{ - */ - -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ - ((STATE) == TIM_OSSRState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State - * @{ - */ - -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ - ((STATE) == TIM_OCIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State - * @{ - */ - -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ - ((STATE) == TIM_OCNIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity - * @{ - */ - -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)|| \ - ((POLARITY) == TIM_ICPolarity_BothEdge)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection - * @{ - */ - -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ - ((SELECTION) == TIM_ICSelection_IndirectTI) || \ - ((SELECTION) == TIM_ICSelection_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler - * @{ - */ - -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_interrupt_sources - * @{ - */ - -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) -#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_COM) || \ - ((IT) == TIM_IT_Trigger) || \ - ((IT) == TIM_IT_Break)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address - * @{ - */ - -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) -#define TIM_DMABase_OR ((uint16_t)0x0013) -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_RCR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_BDTR) || \ - ((BASE) == TIM_DMABase_DCR) || \ - ((BASE) == TIM_DMABase_OR)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length - * @{ - */ - -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources - * @{ - */ - -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Prescaler - * @{ - */ - -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) -#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Internal_Trigger_Selection - * @{ - */ - -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) -/** - * @} - */ - -/** @defgroup TIM_TIx_External_Clock_Source - * @{ - */ - -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Polarity - * @{ - */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) -#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ - ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) -/** - * @} - */ - -/** @defgroup TIM_Prescaler_Reload_Mode - * @{ - */ - -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) -#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ - ((RELOAD) == TIM_PSCReloadMode_Immediate)) -/** - * @} - */ - -/** @defgroup TIM_Forced_Action - * @{ - */ - -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) -#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ - ((ACTION) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode - * @{ - */ - -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ - ((MODE) == TIM_EncoderMode_TI2) || \ - ((MODE) == TIM_EncoderMode_TI12)) -/** - * @} - */ - - -/** @defgroup TIM_Event_Source - * @{ - */ - -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_Update_Source - * @{ - */ - -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ -#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ - ((SOURCE) == TIM_UpdateSource_Regular)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Preload_State - * @{ - */ - -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) -#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ - ((STATE) == TIM_OCPreload_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Fast_State - * @{ - */ - -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) -#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ - ((STATE) == TIM_OCFast_Disable)) - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Clear_State - * @{ - */ - -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) -#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ - ((STATE) == TIM_OCClear_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Output_Source - * @{ - */ - -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ - ((SOURCE) == TIM_TRGOSource_Enable) || \ - ((SOURCE) == TIM_TRGOSource_Update) || \ - ((SOURCE) == TIM_TRGOSource_OC1) || \ - ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC4Ref)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode - * @{ - */ - -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ - ((MODE) == TIM_SlaveMode_Gated) || \ - ((MODE) == TIM_SlaveMode_Trigger) || \ - ((MODE) == TIM_SlaveMode_External1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode - * @{ - */ - -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ - ((STATE) == TIM_MasterSlaveMode_Disable)) -/** - * @} - */ -/** @defgroup TIM_Remap - * @{ - */ - -#define TIM2_TIM8_TRGO ((uint16_t)0x0000) -#define TIM2_ETH_PTP ((uint16_t)0x0400) -#define TIM2_USBFS_SOF ((uint16_t)0x0800) -#define TIM2_USBHS_SOF ((uint16_t)0x0C00) - -#define TIM5_GPIO ((uint16_t)0x0000) -#define TIM5_LSI ((uint16_t)0x0040) -#define TIM5_LSE ((uint16_t)0x0080) -#define TIM5_RTC ((uint16_t)0x00C0) - -#define TIM11_GPIO ((uint16_t)0x0000) -#define TIM11_HSE ((uint16_t)0x0002) - -#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\ - ((TIM_REMAP) == TIM2_ETH_PTP)||\ - ((TIM_REMAP) == TIM2_USBFS_SOF)||\ - ((TIM_REMAP) == TIM2_USBHS_SOF)||\ - ((TIM_REMAP) == TIM5_GPIO)||\ - ((TIM_REMAP) == TIM5_LSI)||\ - ((TIM_REMAP) == TIM5_LSE)||\ - ((TIM_REMAP) == TIM5_RTC)||\ - ((TIM_REMAP) == TIM11_GPIO)||\ - ((TIM_REMAP) == TIM11_HSE)) - -/** - * @} - */ -/** @defgroup TIM_Flags - * @{ - */ - -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) -#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_Trigger) || \ - ((FLAG) == TIM_FLAG_Break) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) - -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value - * @{ - */ - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Filter - * @{ - */ - -#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_Legacy - * @{ - */ - -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* TimeBase management ********************************************************/ -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Output Compare management **************************************************/ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); - -/* Input Capture management ***************************************************/ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); - -/* Advanced-control timers (TIM1 and TIM8) specific features ******************/ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Interrupts, DMA and flags management ***************************************/ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Clocks management **********************************************************/ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); - -/* Synchronization management *************************************************/ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - -/* Specific interface management **********************************************/ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Specific remapping management **********************************************/ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_TIM_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h deleted file mode 100644 index b7d84071e..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h +++ /dev/null @@ -1,412 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_usart.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_USART_H -#define __STM32F4xx_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 - Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ - - uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - - uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4) || \ - ((PERIPH) == UART5) || \ - ((PERIPH) == USART6)) - -#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == USART6)) - -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_0_5) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) -#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @{ - */ - -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE ((uint16_t)0x0360) -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) -#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ - -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) -#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ - (((LENGTH) == USART_LINBreakDetectLength_10b) || \ - ((LENGTH) == USART_LINBreakDetectLength_11b)) -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ - -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) - -#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001)) -#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the USART configuration to the default reset state ***/ -void USART_DeInit(USART_TypeDef* USARTx); - -/* Initialization and Configuration functions *********************************/ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); - -/* Multi-Processor Communication functions ************************************/ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* LIN mode functions *********************************************************/ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SendBreak(USART_TypeDef* USARTx); - -/* Half-duplex mode function **************************************************/ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Smartcard mode functions ***************************************************/ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); - -/* IrDA mode functions ********************************************************/ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* DMA transfers management functions *****************************************/ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_USART_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h b/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h deleted file mode 100644 index 22b3e0de8..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h +++ /dev/null @@ -1,105 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_wwdg.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file contains all the functions prototypes for the WWDG firmware - * library. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_WWDG_H -#define __STM32F4xx_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Constants - * @{ - */ - -/** @defgroup WWDG_Prescaler - * @{ - */ - -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) -#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ - ((PRESCALER) == WWDG_Prescaler_2) || \ - ((PRESCALER) == WWDG_Prescaler_4) || \ - ((PRESCALER) == WWDG_Prescaler_8)) -#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) -#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the WWDG configuration to the default reset state ****/ -void WWDG_DeInit(void); - -/* Prescaler, Refresh window and Counter configuration functions **************/ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); - -/* WWDG activation function ***************************************************/ -void WWDG_Enable(uint8_t Counter); - -/* Interrupts and flags management functions **********************************/ -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_WWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/misc.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/misc.c deleted file mode 100644 index 4df41bfe8..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/misc.c +++ /dev/null @@ -1,243 +0,0 @@ -/** - ****************************************************************************** - * @file misc.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - * - * @verbatim - * - * =================================================================== - * How to configure Interrupts using driver - * =================================================================== - * - * This section provide functions allowing to configure the NVIC interrupts (IRQ). - * The Cortex-M4 exceptions are managed by CMSIS functions. - * - * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() - * function according to the following table. - - * The table below gives the allowed values of the pre-emption priority and subpriority according - * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - * ========================================================================================================================== - * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - * ========================================================================================================================== - * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - * | | | 4 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - * | | | 3 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - * | | | 2 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - * | | | 1 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - * | | | 0 bits for subpriority - * ========================================================================================================================== - * - * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() - * - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * - * @note IRQ priority order (sorted by highest to lowest priority): - * - Lowest pre-emption priority - * - Lowest subpriority - * - Lowest hardware priority (IRQ number) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "misc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup MISC_Private_Functions - * @{ - */ - -/** - * @brief Configures the priority grouping: pre-emption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ - SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; -} - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); - assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; - tmppre = (0x4 - tmppriority); - tmpsub = tmpsub >> tmppriority; - - tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; - tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); - - tmppriority = tmppriority << 0x04; - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values: - * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. - * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. - * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) -{ - /* Check the parameters */ - assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); - assert_param(IS_NVIC_OFFSET(Offset)); - - SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. - * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. - * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. - * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Configures the SysTick clock source. - * @param SysTick_CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c deleted file mode 100644 index 96e13d5d4..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c +++ /dev/null @@ -1,1742 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_adc.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) peripheral: - * - Initialization and Configuration (in addition to ADC multi mode - * selection) - * - Analog Watchdog configuration - * - Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT - * management - * - Regular Channels Configuration - * - Regular Channels DMA Configuration - * - Injected channels Configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - - * 1. Enable the ADC interface clock using - * RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); - * - * 2. ADC pins configuration - * - Enable the clock for the ADC GPIOs using the following function: - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - Configure these ADC pins in analog mode using GPIO_Init(); - * - * 3. Configure the ADC Prescaler, conversion resolution and data - * alignment using the ADC_Init() function. - * 4. Activate the ADC peripheral using ADC_Cmd() function. - * - * Regular channels group configuration - * ==================================== - * - To configure the ADC regular channels group features, use - * ADC_Init() and ADC_RegularChannelConfig() functions. - * - To activate the continuous mode, use the ADC_continuousModeCmd() - * function. - * - To configurate and activate the Discontinuous mode, use the - * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. - * - To read the ADC converted values, use the ADC_GetConversionValue() - * function. - * - * Multi mode ADCs Regular channels configuration - * =============================================== - * - Refer to "Regular channels group configuration" description to - * configure the ADC1, ADC2 and ADC3 regular channels. - * - Select the Multi mode ADC regular channels features (dual or - * triple mode) using ADC_CommonInit() function and configure - * the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() - * functions. - * - Read the ADCs converted values using the - * ADC_GetMultiModeConversionValue() function. - * - * DMA for Regular channels group features configuration - * ====================================================== - * - To enable the DMA mode for regular channels group, use the - * ADC_DMACmd() function. - * - To enable the generation of DMA requests continuously at the end - * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() - * function. - * - * Injected channels group configuration - * ===================================== - * - To configure the ADC Injected channels group features, use - * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() - * functions. - * - To activate the continuous mode, use the ADC_continuousModeCmd() - * function. - * - To activate the Injected Discontinuous mode, use the - * ADC_InjectedDiscModeCmd() function. - * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() - * function. - * - To read the ADC converted values, use the ADC_GetInjectedConversionValue() - * function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_adc.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ADC DISCNUM mask */ -#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) - -/* ADC AWDCH mask */ -#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF) - -/* CR1 register Mask */ -#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) - -/* ADC EXTEN mask */ -#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF) - -/* ADC JEXTEN mask */ -#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC JEXTSEL mask */ -#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF) - -/* CR2 register Mask */ -#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD) - -/* ADC SQx mask */ -#define SQR3_SQ_SET ((uint32_t)0x0000001F) -#define SQR2_SQ_SET ((uint32_t)0x0000001F) -#define SQR1_SQ_SET ((uint32_t)0x0000001F) - -/* ADC L Mask */ -#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define JSQR_JSQ_SET ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define JSQR_JL_SET ((uint32_t)0x00300000) -#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SMPR1_SMP_SET ((uint32_t)0x00000007) -#define SMPR2_SMP_SET ((uint32_t)0x00000007) - -/* ADC JDRx registers offset */ -#define JDR_OFFSET ((uint8_t)0x28) - -/* ADC CDR register base address */ -#define CDR_ADDRESS ((uint32_t)0x40012308) - -/* ADC CCR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** @defgroup ADC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to: - - Initialize and configure the ADC Prescaler - - ADC Conversion Resolution (12bit..6bit) - - Scan Conversion Mode (multichannels or one channel) for regular group - - ADC Continuous Conversion Mode (Continuous or Single conversion) for - regular group - - External trigger Edge and source of regular group, - - Converted data alignment (left or right) - - The number of ADC conversions that will be done using the sequencer for - regular channel group - - Multi ADC mode selection - - Direct memory access mode selection for multi ADC mode - - Delay between 2 sampling phases (used in dual or triple interleaved modes) - - Enable or disable the ADC peripheral - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes all ADCs peripherals registers to their default reset - * values. - * @param None - * @retval None - */ -void ADC_DeInit(void) -{ - /* Enable all ADCs reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE); - - /* Release all ADCs from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE); -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @note This function is used to configure the global features of the ADC ( - * Resolution and Data Alignment), however, the rest of the configuration - * parameters are specific to the regular channels group (scan mode - * activation, continuous mode activation, External trigger source and - * edge, number of conversion in the regular channels group sequencer). - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); - assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion)); - - /*---------------------------- ADCx CR1 Configuration -----------------*/ - /* Get the ADCx CR1 value */ - tmpreg1 = ADCx->CR1; - - /* Clear RES and SCAN bits */ - tmpreg1 &= CR1_CLEAR_MASK; - - /* Configure ADCx: scan conversion mode and resolution */ - /* Set SCAN bit according to ADC_ScanConvMode value */ - /* Set RES bit according to ADC_Resolution value */ - tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \ - ADC_InitStruct->ADC_Resolution); - /* Write to ADCx CR1 */ - ADCx->CR1 = tmpreg1; - /*---------------------------- ADCx CR2 Configuration -----------------*/ - /* Get the ADCx CR2 value */ - tmpreg1 = ADCx->CR2; - - /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */ - tmpreg1 &= CR2_CLEAR_MASK; - - /* Configure ADCx: external trigger event and edge, data alignment and - continuous conversion mode */ - /* Set ALIGN bit according to ADC_DataAlign value */ - /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ - /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ - /* Set CONT bit according to ADC_ContinuousConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \ - ADC_InitStruct->ADC_ExternalTrigConv | - ADC_InitStruct->ADC_ExternalTrigConvEdge | \ - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - - /* Write to ADCx CR2 */ - ADCx->CR2 = tmpreg1; - /*---------------------------- ADCx SQR1 Configuration -----------------*/ - /* Get the ADCx SQR1 value */ - tmpreg1 = ADCx->SQR1; - - /* Clear L bits */ - tmpreg1 &= SQR1_L_RESET; - - /* Configure ADCx: regular channel sequence length */ - /* Set L bits according to ADC_NbrOfConversion value */ - tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1); - tmpreg1 |= ((uint32_t)tmpreg2 << 20); - - /* Write to ADCx SQR1 */ - ADCx->SQR1 = tmpreg1; -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @note This function is used to initialize the global features of the ADC ( - * Resolution and Data Alignment), however, the rest of the configuration - * parameters are specific to the regular channels group (scan mode - * activation, continuous mode activation, External trigger source and - * edge, number of conversion in the regular channels group sequencer). - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Initialize the ADC_Mode member */ - ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; - - /* initialize the ADC_ScanConvMode member */ - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - - /* Initialize the ADC_ContinuousConvMode member */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - - /* Initialize the ADC_ExternalTrigConvEdge member */ - ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; - - /* Initialize the ADC_ExternalTrigConv member */ - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - - /* Initialize the ADC_DataAlign member */ - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - - /* Initialize the ADC_NbrOfConversion member */ - ADC_InitStruct->ADC_NbrOfConversion = 1; -} - -/** - * @brief Initializes the ADCs peripherals according to the specified parameters - * in the ADC_CommonInitStruct. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * that contains the configuration information for All ADCs peripherals. - * @retval None - */ -void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - uint32_t tmpreg1 = 0; - /* Check the parameters */ - assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode)); - assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler)); - assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode)); - assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay)); - /*---------------------------- ADC CCR Configuration -----------------*/ - /* Get the ADC CCR value */ - tmpreg1 = ADC->CCR; - - /* Clear MULTI, DELAY, DMA and ADCPRE bits */ - tmpreg1 &= CR_CLEAR_MASK; - - /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler, - and DMA access mode for multimode */ - /* Set MULTI bits according to ADC_Mode value */ - /* Set ADCPRE bits according to ADC_Prescaler value */ - /* Set DMA bits according to ADC_DMAAccessMode value */ - /* Set DELAY bits according to ADC_TwoSamplingDelay value */ - tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | - ADC_CommonInitStruct->ADC_Prescaler | - ADC_CommonInitStruct->ADC_DMAAccessMode | - ADC_CommonInitStruct->ADC_TwoSamplingDelay); - - /* Write to ADC CCR */ - ADC->CCR = tmpreg1; -} - -/** - * @brief Fills each ADC_CommonInitStruct member with its default value. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * which will be initialized. - * @retval None - */ -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - /* Initialize the ADC_Mode member */ - ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent; - - /* initialize the ADC_Prescaler member */ - ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2; - - /* Initialize the ADC_DMAAccessMode member */ - ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; - - /* Initialize the ADC_TwoSamplingDelay member */ - ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ADON bit to wake up the ADC from power down mode */ - ADCx->CR2 |= (uint32_t)ADC_CR2_ADON; - } - else - { - /* Disable the selected ADC peripheral */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON); - } -} -/** - * @} - */ - -/** @defgroup ADC_Group2 Analog Watchdog configuration functions - * @brief Analog Watchdog configuration functions - * -@verbatim - =============================================================================== - Analog Watchdog configuration functions - =============================================================================== - - This section provides functions allowing to configure the Analog Watchdog - (AWD) feature in the ADC. - - A typical configuration Analog Watchdog is done following these steps : - 1. the ADC guarded channel(s) is (are) selected using the - ADC_AnalogWatchdogSingleChannelConfig() function. - 2. The Analog watchdog lower and higher threshold are configured using the - ADC_AnalogWatchdogThresholdsConfig() function. - 3. The Analog watchdog is enabled and configured to enable the check, on one - or more channels, using the ADC_AnalogWatchdogCmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the analog watchdog on single/all regular or - * injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel - * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel - * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel - * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel - * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel - * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels - * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); - - /* Get the old register value */ - tmpreg = ADCx->CR1; - - /* Clear AWDEN, JAWDEN and AWDSGL bits */ - tmpreg &= CR1_AWDMode_RESET; - - /* Set the analog watchdog enable mode */ - tmpreg |= ADC_AnalogWatchdog; - - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12-bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12-bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - - /* Set the ADCx high threshold */ - ADCx->HTR = HighThreshold; - - /* Set the ADCx low threshold */ - ADCx->LTR = LowThreshold; -} - -/** - * @brief Configures the analog watchdog guarded single channel - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - - /* Get the old register value */ - tmpreg = ADCx->CR1; - - /* Clear the Analog watchdog channel select bits */ - tmpreg &= CR1_AWDCH_RESET; - - /* Set the Analog watchdog channel */ - tmpreg |= ADC_Channel; - - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} -/** - * @} - */ - -/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal) - * and VBAT (Voltage BATtery) management functions - * @brief Temperature Sensor, Vrefint and VBAT management functions - * -@verbatim - =============================================================================== - Temperature Sensor, Vrefint and VBAT management functions - =============================================================================== - - This section provides functions allowing to enable/ disable the internal - connections between the ADC and the Temperature Sensor, the Vrefint and the - Vbat sources. - - A typical configuration to get the Temperature sensor and Vrefint channels - voltages is done following these steps : - 1. Enable the internal connection of Temperature sensor and Vrefint sources - with the ADC channels using ADC_TempSensorVrefintCmd() function. - 2. Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using - ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions - 3. Get the voltage values, using ADC_GetConversionValue() or - ADC_GetInjectedConversionValue(). - - A typical configuration to get the VBAT channel voltage is done following - these steps : - 1. Enable the internal connection of VBAT source with the ADC channel using - ADC_VBATCmd() function. - 2. Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or - ADC_InjectedChannelConfig() functions - 3. Get the voltage value, using ADC_GetConversionValue() or - ADC_GetInjectedConversionValue(). - -@endverbatim - * @{ - */ - - -/** - * @brief Enables or disables the temperature sensor and Vrefint channels. - * @param NewState: new state of the temperature sensor and Vrefint channels. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the temperature sensor and Vrefint channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; - } - else - { - /* Disable the temperature sensor and Vrefint channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); - } -} - -/** - * @brief Enables or disables the VBAT (Voltage Battery) channel. - * @param NewState: new state of the VBAT channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_VBATCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the VBAT channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_VBATE; - } - else - { - /* Disable the VBAT channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE); - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group4 Regular Channels Configuration functions - * @brief Regular Channels Configuration functions - * -@verbatim - =============================================================================== - Regular Channels Configuration functions - =============================================================================== - - This section provides functions allowing to manage the ADC's regular channels, - it is composed of 2 sub sections : - - 1. Configuration and management functions for regular channels: This subsection - provides functions allowing to configure the ADC regular channels : - - Configure the rank in the regular group sequencer for each channel - - Configure the sampling time for each channel - - select the conversion Trigger for regular channels - - select the desired EOC event behavior configuration - - Activate the continuous Mode (*) - - Activate the Discontinuous Mode - Please Note that the following features for regular channels are configurated - using the ADC_Init() function : - - scan mode activation - - continuous mode activation (**) - - External trigger source - - External trigger edge - - number of conversion in the regular channels group sequencer. - - @note (*) and (**) are performing the same configuration - - 2. Get the conversion data: This subsection provides an important function in - the ADC peripheral since it returns the converted data of the current - regular channel. When the Conversion value is read, the EOC Flag is - automatically cleared. - - @note For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions - results data (in the selected multi mode) can be returned in the same - time using ADC_GetMultiModeConversionValue() function. - - -@endverbatim - * @{ - */ -/** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Rank: The rank in the regular group sequencer. - * This parameter must be between 1 to 16. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles - * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles - * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles - * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles - * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles - * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles - * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles - * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles - * @retval None - */ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_REGULAR_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10)); - - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); - - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* For Rank 1 to 6 */ - if (Rank < 7) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR3; - - /* Calculate the mask to clear */ - tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR3 = tmpreg1; - } - /* For Rank 7 to 12 */ - else if (Rank < 13) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR2; - - /* Calculate the mask to clear */ - tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR2 = tmpreg1; - } - /* For Rank 13 to 16 */ - else - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR1; - - /* Calculate the mask to clear */ - tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR1 = tmpreg1; - } -} - -/** - * @brief Enables the selected ADC software start conversion of the regular channels. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_SoftwareStartConv(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Enable the selected ADC conversion for regular group */ - ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART; -} - -/** - * @brief Gets the selected ADC Software start regular conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of SWSTART bit */ - if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) - { - /* SWSTART bit is set */ - bitstatus = SET; - } - else - { - /* SWSTART bit is reset */ - bitstatus = RESET; - } - - /* Return the SWSTART bit status */ - return bitstatus; -} - - -/** - * @brief Enables or disables the EOC on each regular channel conversion - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC EOC flag rising - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC EOC rising on each regular channel conversion */ - ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS; - } - else - { - /* Disable the selected ADC EOC rising on each regular channel conversion */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS); - } -} - -/** - * @brief Enables or disables the ADC continuous conversion mode - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC continuous conversion mode - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC continuous conversion mode */ - ADCx->CR2 |= (uint32_t)ADC_CR2_CONT; - } - else - { - /* Disable the selected ADC continuous conversion mode */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT); - } -} - -/** - * @brief Configures the discontinuous mode for the selected ADC regular group - * channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Number: specifies the discontinuous mode regular channel count value. - * This number must be between 1 and 8. - * @retval None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); - - /* Get the old register value */ - tmpreg1 = ADCx->CR1; - - /* Clear the old discontinuous mode channel count */ - tmpreg1 &= CR1_DISCNUM_RESET; - - /* Set the discontinuous mode channel count */ - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - - /* Store the new register value */ - ADCx->CR1 = tmpreg1; -} - -/** - * @brief Enables or disables the discontinuous mode on regular group channel - * for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode on - * regular group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC regular discontinuous mode */ - ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN; - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN); - } -} - -/** - * @brief Returns the last ADCx conversion result data for regular channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results - * data in the selected multi mode. - * @param None - * @retval The Data conversion value. - * @note In dual mode, the value returned by this function is as following - * Data[15:0] : these bits contain the regular data of ADC1. - * Data[31:16]: these bits contain the regular data of ADC2. - * @note In triple mode, the value returned by this function is as following - * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. - * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3. - */ -uint32_t ADC_GetMultiModeConversionValue(void) -{ - /* Return the multi mode conversion value */ - return (*(__IO uint32_t *) CDR_ADDRESS); -} -/** - * @} - */ - -/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions - * @brief Regular Channels DMA Configuration functions - * -@verbatim - =============================================================================== - Regular Channels DMA Configuration functions - =============================================================================== - - This section provides functions allowing to configure the DMA for ADC regular - channels. - Since converted regular channel values are stored into a unique data register, - it is useful to use DMA for conversion of more than one regular channel. This - avoids the loss of the data already stored in the ADC Data register. - - When the DMA mode is enabled (using the ADC_DMACmd() function), after each - conversion of a regular channel, a DMA request is generated. - - Depending on the "DMA disable selection for Independent ADC mode" - configuration (using the ADC_DMARequestAfterLastTransferCmd() function), - at the end of the last DMA transfer, two possibilities are allowed: - - No new DMA request is issued to the DMA controller (feature DISABLED) - - Requests can continue to be generated (feature ENABLED). - - Depending on the "DMA disable selection for multi ADC mode" configuration - (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), - at the end of the last DMA transfer, two possibilities are allowed: - - No new DMA request is issued to the DMA controller (feature DISABLED) - - Requests can continue to be generated (feature ENABLED). - -@endverbatim - * @{ - */ - - /** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CR2 |= (uint32_t)ADC_CR2_DMA; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA); - } -} - -/** - * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC DMA request after last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADCx->CR2 |= (uint32_t)ADC_CR2_DDS; - } - else - { - /* Disable the selected ADC DMA request after last transfer */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS); - } -} - -/** - * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode - * @param NewState: new state of the selected ADC DMA request after last transfer. - * This parameter can be: ENABLE or DISABLE. - * @note if Enabled, DMA requests are issued as long as data are converted and - * DMA mode for multi ADC mode (selected using ADC_CommonInit() function - * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is - * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3. - * @retval None - */ -void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADC->CCR |= (uint32_t)ADC_CCR_DDS; - } - else - { - /* Disable the selected ADC DMA request after last transfer */ - ADC->CCR &= (uint32_t)(~ADC_CCR_DDS); - } -} -/** - * @} - */ - -/** @defgroup ADC_Group6 Injected channels Configuration functions - * @brief Injected channels Configuration functions - * -@verbatim - =============================================================================== - Injected channels Configuration functions - =============================================================================== - - This section provide functions allowing to configure the ADC Injected channels, - it is composed of 2 sub sections : - - 1. Configuration functions for Injected channels: This subsection provides - functions allowing to configure the ADC injected channels : - - Configure the rank in the injected group sequencer for each channel - - Configure the sampling time for each channel - - Activate the Auto injected Mode - - Activate the Discontinuous Mode - - scan mode activation - - External/software trigger source - - External trigger edge - - injected channels sequencer. - - 2. Get the Specified Injected channel conversion data: This subsection - provides an important function in the ADC peripheral since it returns the - converted data of the specific injected channel. - -@endverbatim - * @{ - */ -/** - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Rank: The rank in the injected group sequencer. - * This parameter must be between 1 to 4. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles - * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles - * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles - * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles - * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles - * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles - * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles - * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles - * @retval None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_INJECTED_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10)); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* Rank configuration */ - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Get JL value: Number = JL+1 */ - tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20; - /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Clear the old JSQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Set the JSQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Configures the sequencer length for injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Length: The sequencer length. - * This parameter must be a number between 1 to 4. - * @retval None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_LENGTH(Length)); - - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - - /* Clear the old injected sequence length JL bits */ - tmpreg1 &= JSQR_JL_RESET; - - /* Set the injected sequence length JL bits */ - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Set the injected channels conversion value offset - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the ADC injected channel to set its offset. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @param Offset: the offset value for the selected ADC injected channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - assert_param(IS_ADC_OFFSET(Offset)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - /* Set the selected injected channel data offset */ - *(__IO uint32_t *) tmp = (uint32_t)Offset; -} - - /** - * @brief Configures the ADCx external trigger for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected - * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected - * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected - * @retval None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); - - /* Get the old register value */ - tmpreg = ADCx->CR2; - - /* Clear the old external event selection for injected group */ - tmpreg &= CR2_JEXTSEL_RESET; - - /* Set the external event selection for injected group */ - tmpreg |= ADC_ExternalTrigInjecConv; - - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Configures the ADCx external trigger edge for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge - * to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for - * injected conversion - * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge - * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge - * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising - * and falling edge - * @retval None - */ -void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge)); - /* Get the old register value */ - tmpreg = ADCx->CR2; - /* Clear the old external trigger edge for injected group */ - tmpreg &= CR2_JEXTEN_RESET; - /* Set the new external trigger edge for injected group */ - tmpreg |= ADC_ExternalTrigInjecConvEdge; - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Enables the selected ADC software start conversion of the injected channels. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Enable the selected ADC conversion for injected group */ - ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART; -} - -/** - * @brief Gets the selected ADC Software start injected conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start injected conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of JSWSTART bit */ - if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) - { - /* JSWSTART bit is set */ - bitstatus = SET; - } - else - { - /* JSWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the JSWSTART bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC auto injected conversion - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO); - } -} - -/** - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode on injected - * group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN); - } -} - -/** - * @brief Returns the ADC injected channel conversion result - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the converted ADC injected channel. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @retval The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + JDR_OFFSET; - - /* Returns the selected injected channel conversion data value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} -/** - * @} - */ - -/** @defgroup ADC_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the ADC Interrupts and - to get the status and clear flags and Interrupts pending bits. - - Each ADC provides 4 Interrupts sources and 6 Flags which can be divided into - 3 groups: - - I. Flags and Interrupts for ADC regular channels - ================================================= - Flags : - ---------- - 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost - - 2. ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate (depending - on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of: - ==> a regular CHANNEL conversion - ==> sequence of regular GROUP conversions . - - 3. ADC_FLAG_STRT: Regular channel start ==> to indicate when regular CHANNEL - conversion starts. - - Interrupts : - ------------ - 1. ADC_IT_OVR : specifies the interrupt source for Overrun detection event. - 2. ADC_IT_EOC : specifies the interrupt source for Regular channel end of - conversion event. - - - II. Flags and Interrupts for ADC Injected channels - ================================================= - Flags : - ---------- - 1. ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate at - the end of injected GROUP conversion - - 2. ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when - injected GROUP conversion starts. - - Interrupts : - ------------ - 1. ADC_IT_JEOC : specifies the interrupt source for Injected channel end of - conversion event. - - III. General Flags and Interrupts for the ADC - ================================================= - Flags : - ---------- - 1. ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage - crosses the programmed thresholds values. - - Interrupts : - ------------ - 1. ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. - - - The user should identify which mode will be used in his application to manage - the ADC controller events: Polling mode or Interrupt mode. - - In the Polling Mode it is advised to use the following functions: - - ADC_GetFlagStatus() : to check if flags events occur. - - ADC_ClearFlag() : to clear the flags events. - - In the Interrupt Mode it is advised to use the following functions: - - ADC_ITConfig() : to enable or disable the interrupt source. - - ADC_GetITStatus() : to check if Interrupt occurs. - - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt enable - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint32_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_IT(ADC_IT)); - - /* Get the ADC IT index */ - itmask = (uint8_t)ADC_IT; - itmask = (uint32_t)0x01 << itmask; - - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->CR1 |= itmask; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->CR1 &= (~(uint32_t)itmask); - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @arg ADC_FLAG_OVR: Overrun flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - - /* Check the status of the specified ADC flag */ - if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @arg ADC_FLAG_OVR: Overrun flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - - /* Clear the selected ADC flags */ - ADCx->SR = ~(uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt mask - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - - /* Get the ADC IT index */ - itmask = ADC_IT >> 8; - - /* Get the ADC_IT enable bit status */ - enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ; - - /* Check the status of the specified ADC interrupt */ - if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) - { - /* ADC_IT is set */ - bitstatus = SET; - } - else - { - /* ADC_IT is reset */ - bitstatus = RESET; - } - /* Return the ADC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's interrupt pending bits. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt mask - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)(ADC_IT >> 8); - /* Clear the selected ADC interrupt pending bits */ - ADCx->SR = ~(uint32_t)itmask; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c deleted file mode 100644 index 4fdfe1236..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c +++ /dev/null @@ -1,1698 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_can.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the Controller area network (CAN) peripheral: - * - Initialization and Configuration - * - CAN Frames Transmission - * - CAN Frames Reception - * - Operation modes switch - * - Error management - * - Interrupts and flags - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - - * 1. Enable the CAN controller interface clock using - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 - * and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2 - * @note In case you are using CAN2 only, you have to enable the CAN1 clock. - * - * 2. CAN pins configuration - * - Enable the clock for the CAN GPIOs using the following function: - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - Connect the involved CAN pins to AF9 using the following function - * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); - * - Configure these CAN pins in alternate function mode by calling - * the function GPIO_Init(); - * - * 3. Initialise and configure the CAN using CAN_Init() and - * CAN_FilterInit() functions. - * - * 4. Transmit the desired CAN frame using CAN_Transmit() function. - * - * 5. Check the transmission of a CAN frame using CAN_TransmitStatus() - * function. - * - * 6. Cancel the transmission of a CAN frame using CAN_CancelTransmit() - * function. - * - * 7. Receive a CAN frame using CAN_Recieve() function. - * - * 8. Release the receive FIFOs using CAN_FIFORelease() function. - * - * 9. Return the number of pending received frames using - * CAN_MessagePending() function. - * - * 10. To control CAN events you can use one of the following two methods: - * - Check on CAN flags using the CAN_GetFlagStatus() function. - * - Use CAN interrupts through the function CAN_ITConfig() at - * initialization phase and CAN_GetITStatus() function into - * interrupt routines to check if the event has occurred or not. - * After checking on a flag you should clear it using CAN_ClearFlag() - * function. And after checking on an interrupt event you should - * clear it using CAN_ClearITPendingBit() function. - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_can.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CAN - * @brief CAN driver modules - * @{ - */ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* CAN Master Control Register bits */ -#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ - -/* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ - -/* CAN Filter Master Register bits */ -#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ - -/* Time out for INAK bit */ -#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) -/* Time out for SLAK bit */ -#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) - -/* Flags in TSR register */ -#define CAN_FLAGS_TSR ((uint32_t)0x08000000) -/* Flags in RF1R register */ -#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) -/* Flags in RF0R register */ -#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) -/* Flags in MSR register */ -#define CAN_FLAGS_MSR ((uint32_t)0x01000000) -/* Flags in ESR register */ -#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) - -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - -#define CAN_MODE_MASK ((uint32_t) 0x00000003) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); - -/** @defgroup CAN_Private_Functions - * @{ - */ - -/** @defgroup CAN_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to - - Initialize the CAN peripherals : Prescaler, operating mode, the maximum number - of time quanta to perform resynchronization, the number of time quanta in - Bit Segment 1 and 2 and many other modes. - Refer to @ref CAN_InitTypeDef for more details. - - Configures the CAN reception filter. - - Select the start bank filter for slave CAN. - - Enables or disables the Debug Freeze mode for CAN - - Enables or disables the CAN Time Trigger Operation communication mode - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the CAN peripheral registers to their default reset values. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval None. - */ -void CAN_DeInit(CAN_TypeDef* CANx) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - if (CANx == CAN1) - { - /* Enable CAN1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); - /* Release CAN1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); - } - else - { - /* Enable CAN2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); - /* Release CAN2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); - } -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains - * the configuration information for the CAN peripheral. - * @retval Constant indicates initialization succeed which will be - * CAN_InitStatus_Failed or CAN_InitStatus_Success. - */ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) -{ - uint8_t InitStatus = CAN_InitStatus_Failed; - uint32_t wait_ack = 0x00000000; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); - assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); - assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); - assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); - assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); - assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); - - /* Exit from sleep mode */ - CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - - /* Request initialisation */ - CANx->MCR |= CAN_MCR_INRQ ; - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* Check acknowledge */ - if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - /* Set the time triggered communication mode */ - if (CAN_InitStruct->CAN_TTCM == ENABLE) - { - CANx->MCR |= CAN_MCR_TTCM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (CAN_InitStruct->CAN_ABOM == ENABLE) - { - CANx->MCR |= CAN_MCR_ABOM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (CAN_InitStruct->CAN_AWUM == ENABLE) - { - CANx->MCR |= CAN_MCR_AWUM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (CAN_InitStruct->CAN_NART == ENABLE) - { - CANx->MCR |= CAN_MCR_NART; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (CAN_InitStruct->CAN_RFLM == ENABLE) - { - CANx->MCR |= CAN_MCR_RFLM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (CAN_InitStruct->CAN_TXFP == ENABLE) - { - CANx->MCR |= CAN_MCR_TXFP; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ - ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ - ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ - ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); - - /* Request leave initialisation */ - CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Wait the acknowledge */ - wait_ack = 0; - - while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* ...and check acknowledged */ - if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - InitStatus = CAN_InitStatus_Success ; - } - } - - /* At this step, return the status of initialization */ - return InitStatus; -} - -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that - * contains the configuration information. - * @retval None - */ -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); - - filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; - - /* Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; - - /* Filter Scale */ - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - /* 32-bit scale for the filter */ - CAN1->FS1R |= filter_number_bit_pos; - /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - - /* Filter Mode */ - if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter FIFO assignment */ - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) - { - /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) - { - /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter activation */ - if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CAN1->FA1R |= filter_number_bit_pos; - } - - /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Fills each CAN_InitStruct member with its default value. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized. - * @retval None - */ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ - /* Reset CAN init structure parameters values */ - - /* Initialize the time triggered communication mode */ - CAN_InitStruct->CAN_TTCM = DISABLE; - - /* Initialize the automatic bus-off management */ - CAN_InitStruct->CAN_ABOM = DISABLE; - - /* Initialize the automatic wake-up mode */ - CAN_InitStruct->CAN_AWUM = DISABLE; - - /* Initialize the no automatic retransmission */ - CAN_InitStruct->CAN_NART = DISABLE; - - /* Initialize the receive FIFO locked mode */ - CAN_InitStruct->CAN_RFLM = DISABLE; - - /* Initialize the transmit FIFO priority */ - CAN_InitStruct->CAN_TXFP = DISABLE; - - /* Initialize the CAN_Mode member */ - CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; - - /* Initialize the CAN_SJW member */ - CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; - - /* Initialize the CAN_BS1 member */ - CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; - - /* Initialize the CAN_BS2 member */ - CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; - - /* Initialize the CAN_Prescaler member */ - CAN_InitStruct->CAN_Prescaler = 1; -} - -/** - * @brief Select the start bank filter for slave CAN. - * @param CAN_BankNumber: Select the start slave bank filter from 1..27. - * @retval None - */ -void CAN_SlaveStartBank(uint8_t CAN_BankNumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); - - /* Enter Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Select the start slave bank */ - CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; - CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; - - /* Leave Initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Enables or disables the DBG Freeze for CAN. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFOs can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @retval None - */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Debug Freeze */ - CANx->MCR |= MCR_DBF; - } - else - { - /* Disable Debug Freeze */ - CANx->MCR &= ~MCR_DBF; - } -} - - -/** - * @brief Enables or disables the CAN Time TriggerOperation communication mode. - * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be - * sent over the CAN bus. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE. - * When enabled, Time stamp (TIME[15:0]) value is sent in the last two - * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] - * in data byte 7. - * @retval None - */ -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TTCM mode */ - CANx->MCR |= CAN_MCR_TTCM; - - /* Set TGT bits */ - CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); - } - else - { - /* Disable the TTCM mode */ - CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); - - /* Reset TGT bits */ - CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); - } -} -/** - * @} - */ - - -/** @defgroup CAN_Group2 CAN Frames Transmission functions - * @brief CAN Frames Transmission functions - * -@verbatim - =============================================================================== - CAN Frames Transmission functions - =============================================================================== - This section provides functions allowing to - - Initiate and transmit a CAN frame message (if there is an empty mailbox). - - Check the transmission status of a CAN Frame - - Cancel a transmit request - -@endverbatim - * @{ - */ - -/** - * @brief Initiates and transmits a CAN frame message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. - * @retval The number of the mailbox that is used for transmission or - * CAN_TxStatus_NoMailBox if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) -{ - uint8_t transmit_mailbox = 0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); - assert_param(IS_CAN_RTR(TxMessage->RTR)); - assert_param(IS_CAN_DLC(TxMessage->DLC)); - - /* Select one empty transmit mailbox */ - if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmit_mailbox = 0; - } - else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmit_mailbox = 1; - } - else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_TxStatus_NoMailBox; - } - - if (transmit_mailbox != CAN_TxStatus_NoMailBox) - { - /* Set up the Id */ - CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_Id_Standard) - { - assert_param(IS_CAN_STDID(TxMessage->StdId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ - TxMessage->RTR); - } - else - { - assert_param(IS_CAN_EXTID(TxMessage->ExtId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ - TxMessage->IDE | \ - TxMessage->RTR); - } - - /* Set up the DLC */ - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; - - /* Set up the data field */ - CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - /* Request transmission */ - CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; - } - return transmit_mailbox; -} - -/** - * @brief Checks the transmission status of a CAN Frame. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param TransmitMailbox: the number of the mailbox that is used for transmission. - * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, - * CAN_TxStatus_Failed in an other case. - */ -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) -{ - uint32_t state = 0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); - - switch (TransmitMailbox) - { - case (CAN_TXMAILBOX_0): - state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); - break; - case (CAN_TXMAILBOX_1): - state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); - break; - case (CAN_TXMAILBOX_2): - state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); - break; - default: - state = CAN_TxStatus_Failed; - break; - } - switch (state) - { - /* transmit pending */ - case (0x0): state = CAN_TxStatus_Pending; - break; - /* transmit failed */ - case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; - break; - /* transmit succeeded */ - case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; - break; - default: state = CAN_TxStatus_Failed; - break; - } - return (uint8_t) state; -} - -/** - * @brief Cancels a transmit request. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param Mailbox: Mailbox number. - * @retval None - */ -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); - /* abort transmission */ - switch (Mailbox) - { - case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; - break; - case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; - break; - case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; - break; - default: - break; - } -} -/** - * @} - */ - - -/** @defgroup CAN_Group3 CAN Frames Reception functions - * @brief CAN Frames Reception functions - * -@verbatim - =============================================================================== - CAN Frames Reception functions - =============================================================================== - This section provides functions allowing to - - Receive a correct CAN frame - - Release a specified receive FIFO (2 FIFOs are available) - - Return the number of the pending received CAN frames - -@endverbatim - * @{ - */ - -/** - * @brief Receives a correct CAN frame. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @param RxMessage: pointer to a structure receive frame which contains CAN Id, - * CAN DLC, CAN data and FMI number. - * @retval None - */ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Get the Id */ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; - if (RxMessage->IDE == CAN_Id_Standard) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Releases the specified receive FIFO. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. - * @retval None - */ -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Returns the number of pending received messages. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval NbMessage : which is the number of pending message. - */ -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - uint8_t message_pending=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - if (FIFONumber == CAN_FIFO0) - { - message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); - } - else if (FIFONumber == CAN_FIFO1) - { - message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); - } - else - { - message_pending = 0; - } - return message_pending; -} -/** - * @} - */ - - -/** @defgroup CAN_Group4 CAN Operation modes functions - * @brief CAN Operation modes functions - * -@verbatim - =============================================================================== - CAN Operation modes functions - =============================================================================== - This section provides functions allowing to select the CAN Operation modes - - sleep mode - - normal mode - - initialization mode - -@endverbatim - * @{ - */ - - -/** - * @brief Selects the CAN Operation mode. - * @param CAN_OperatingMode: CAN Operating Mode. - * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration. - * @retval status of the requested mode which can be - * - CAN_ModeStatus_Failed: CAN failed entering the specific mode - * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode - */ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) -{ - uint8_t status = CAN_ModeStatus_Failed; - - /* Timeout for INAK or also for SLAK bits*/ - uint32_t timeout = INAK_TIMEOUT; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); - - if (CAN_OperatingMode == CAN_OperatingMode_Initialization) - { - /* Request initialisation */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Normal) - { - /* Request leave initialisation and sleep mode and enter Normal mode */ - CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != 0) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) - { - /* Request Sleep mode */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else - { - status = CAN_ModeStatus_Failed; - } - - return (uint8_t) status; -} - -/** - * @brief Enters the Sleep (low power) mode. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise. - */ -uint8_t CAN_Sleep(CAN_TypeDef* CANx) -{ - uint8_t sleepstatus = CAN_Sleep_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Request Sleep mode */ - CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) - { - /* Sleep mode not entered */ - sleepstatus = CAN_Sleep_Ok; - } - /* return sleep mode status */ - return (uint8_t)sleepstatus; -} - -/** - * @brief Wakes up the CAN peripheral from sleep mode . - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise. - */ -uint8_t CAN_WakeUp(CAN_TypeDef* CANx) -{ - uint32_t wait_slak = SLAK_TIMEOUT; - uint8_t wakeupstatus = CAN_WakeUp_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Wake up request */ - CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; - - /* Sleep mode status */ - while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) - { - wait_slak--; - } - if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) - { - /* wake up done : Sleep mode exited */ - wakeupstatus = CAN_WakeUp_Ok; - } - /* return wakeup status */ - return (uint8_t)wakeupstatus; -} -/** - * @} - */ - - -/** @defgroup CAN_Group5 CAN Bus Error management functions - * @brief CAN Bus Error management functions - * -@verbatim - =============================================================================== - CAN Bus Error management functions - =============================================================================== - This section provides functions allowing to - - Return the CANx's last error code (LEC) - - Return the CANx Receive Error Counter (REC) - - Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). - - @note If TEC is greater than 255, The CAN is in bus-off state. - @note if REC or TEC are greater than 96, an Error warning flag occurs. - @note if REC or TEC are greater than 127, an Error Passive Flag occurs. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the CANx's last error code (LEC). - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval Error code: - * - CAN_ERRORCODE_NoErr: No Error - * - CAN_ERRORCODE_StuffErr: Stuff Error - * - CAN_ERRORCODE_FormErr: Form Error - * - CAN_ERRORCODE_ACKErr : Acknowledgment Error - * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error - * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error - * - CAN_ERRORCODE_CRCErr: CRC Error - * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error - */ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) -{ - uint8_t errorcode=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the error code*/ - errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); - - /* Return the error code*/ - return errorcode; -} - -/** - * @brief Returns the CANx Receive Error Counter (REC). - * @note In case of an error during reception, this counter is incremented - * by 1 or by 8 depending on the error condition as defined by the CAN - * standard. After every successful reception, the counter is - * decremented by 1 or reset to 120 if its value was higher than 128. - * When the counter value exceeds 127, the CAN controller enters the - * error passive state. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CAN Receive Error Counter. - */ -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the Receive Error Counter*/ - counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); - - /* Return the Receive Error Counter*/ - return counter; -} - - -/** - * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval LSB of the 9-bit CAN Transmit Error Counter. - */ -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); - - /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - return counter; -} -/** - * @} - */ - -/** @defgroup CAN_Group6 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the CAN Interrupts and - to get the status and clear flags and Interrupts pending bits. - - The CAN provides 14 Interrupts sources and 15 Flags: - - =============== - Flags : - =============== - The 15 flags can be divided on 4 groups: - - A. Transmit Flags - ----------------------- - CAN_FLAG_RQCP0, - CAN_FLAG_RQCP1, - CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags - Set when when the last request (transmit or abort) has - been performed. - - B. Receive Flags - ----------------------- - - CAN_FLAG_FMP0, - CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags - set to signal that messages are pending in the receive - FIFO. - These Flags are cleared only by hardware. - - CAN_FLAG_FF0, - CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags - set when three messages are stored in the selected - FIFO. - - CAN_FLAG_FOV0 - CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags - set when a new message has been received and passed - the filter while the FIFO was full. - - C. Operating Mode Flags - ----------------------- - CAN_FLAG_WKU : Wake up Flag - set to signal that a SOF bit has been detected while - the CAN hardware was in Sleep mode. - - CAN_FLAG_SLAK : Sleep acknowledge Flag - Set to signal that the CAN has entered Sleep Mode. - - D. Error Flags - ----------------------- - CAN_FLAG_EWG : Error Warning Flag - Set when the warning limit has been reached (Receive - Error Counter or Transmit Error Counter greater than 96). - This Flag is cleared only by hardware. - - CAN_FLAG_EPV : Error Passive Flag - Set when the Error Passive limit has been reached - (Receive Error Counter or Transmit Error Counter - greater than 127). - This Flag is cleared only by hardware. - - CAN_FLAG_BOF : Bus-Off Flag - set when CAN enters the bus-off state. The bus-off - state is entered on TEC overflow, greater than 255. - This Flag is cleared only by hardware. - - CAN_FLAG_LEC : Last error code Flag - set If a message has been transferred (reception or - transmission) with error, and the error code is hold. - - =============== - Interrupts : - =============== - The 14 interrupts can be divided on 4 groups: - - A. Transmit interrupt - ----------------------- - CAN_IT_TME : Transmit mailbox empty Interrupt - if enabled, this interrupt source is pending when - no transmit request are pending for Tx mailboxes. - - B. Receive Interrupts - ----------------------- - CAN_IT_FMP0, - CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts - if enabled, these interrupt sources are pending when - messages are pending in the receive FIFO. - The corresponding interrupt pending bits are cleared - only by hardware. - - CAN_IT_FF0, - CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts - if enabled, these interrupt sources are pending when - three messages are stored in the selected FIFO. - - CAN_IT_FOV0, - CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts - if enabled, these interrupt sources are pending when - a new message has been received and passed the filter - while the FIFO was full. - - C. Operating Mode Interrupts - ------------------------------- - CAN_IT_WKU : Wake-up Interrupt - if enabled, this interrupt source is pending when - a SOF bit has been detected while the CAN hardware was - in Sleep mode. - - CAN_IT_SLK : Sleep acknowledge Interrupt - if enabled, this interrupt source is pending when - the CAN has entered Sleep Mode. - - D. Error Interrupts - ----------------------- - CAN_IT_EWG : Error warning Interrupt - if enabled, this interrupt source is pending when - the warning limit has been reached (Receive Error - Counter or Transmit Error Counter=96). - - CAN_IT_EPV : Error passive Interrupt - if enabled, this interrupt source is pending when - the Error Passive limit has been reached (Receive - Error Counter or Transmit Error Counter>127). - - CAN_IT_BOF : Bus-off Interrupt - if enabled, this interrupt source is pending when - CAN enters the bus-off state. The bus-off state is - entered on TEC overflow, greater than 255. - This Flag is cleared only by hardware. - - CAN_IT_LEC : Last error code Interrupt - if enabled, this interrupt source is pending when - a message has been transferred (reception or - transmission) with error, and the error code is hold. - - CAN_IT_ERR : Error Interrupt - if enabled, this interrupt source is pending when - an error condition is pending. - - - Managing the CAN controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the CAN controller events: Polling mode or Interrupt mode. - - 1. In the Polling Mode it is advised to use the following functions: - - CAN_GetFlagStatus() : to check if flags events occur. - - CAN_ClearFlag() : to clear the flags events. - - - - 2. In the Interrupt Mode it is advised to use the following functions: - - CAN_ITConfig() : to enable or disable the interrupt source. - - CAN_GetITStatus() : to check if Interrupt occurs. - - CAN_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). - @note This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts - pending bits since there are cleared only by hardware. - -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified CANx interrupts. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @param NewState: new state of the CAN interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CANx interrupt */ - CANx->IER |= CAN_IT; - } - else - { - /* Disable the selected CANx interrupt */ - CANx->IER &= ~CAN_IT; - } -} -/** - * @brief Checks whether the specified CAN flag is set or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag - * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag - * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @arg CAN_FLAG_LEC: Last error code Flag - * @retval The new state of CAN_FLAG (SET or RESET). - */ -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); - - - if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ - { - /* Check the status of the specified CAN flag */ - if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - /* Return the CAN_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CAN's pending flags. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag - * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag - * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_LEC: Last error code Flag - * @retval None - */ -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - uint32_t flagtmp=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); - - if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ - { - /* Clear the selected CAN flags */ - CANx->ESR = (uint32_t)RESET; - } - else /* MSR or TSR or RF0R or RF1R */ - { - flagtmp = CAN_FLAG & 0x000FFFFF; - - if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF0R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF1R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) - { - /* Transmit Flags */ - CANx->TSR = (uint32_t)(flagtmp); - } - else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ - { - /* Operating mode Flags */ - CANx->MSR = (uint32_t)(flagtmp); - } - } -} - -/** - * @brief Checks whether the specified CANx interrupt has occurred or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @retval The current state of CAN_IT (SET or RESET). - */ -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - ITStatus itstatus = RESET; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - - /* check the interrupt enable bit */ - if((CANx->IER & CAN_IT) != RESET) - { - /* in case the Interrupt is enabled, .... */ - switch (CAN_IT) - { - case CAN_IT_TME: - /* Check CAN_TSR_RQCPx bits */ - itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); - break; - case CAN_IT_FMP0: - /* Check CAN_RF0R_FMP0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); - break; - case CAN_IT_FF0: - /* Check CAN_RF0R_FULL0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); - break; - case CAN_IT_FOV0: - /* Check CAN_RF0R_FOVR0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); - break; - case CAN_IT_FMP1: - /* Check CAN_RF1R_FMP1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); - break; - case CAN_IT_FF1: - /* Check CAN_RF1R_FULL1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); - break; - case CAN_IT_FOV1: - /* Check CAN_RF1R_FOVR1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); - break; - case CAN_IT_WKU: - /* Check CAN_MSR_WKUI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); - break; - case CAN_IT_SLK: - /* Check CAN_MSR_SLAKI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); - break; - case CAN_IT_EWG: - /* Check CAN_ESR_EWGF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); - break; - case CAN_IT_EPV: - /* Check CAN_ESR_EPVF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); - break; - case CAN_IT_BOF: - /* Check CAN_ESR_BOFF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); - break; - case CAN_IT_LEC: - /* Check CAN_ESR_LEC bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); - break; - case CAN_IT_ERR: - /* Check CAN_MSR_ERRI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); - break; - default: - /* in case of error, return RESET */ - itstatus = RESET; - break; - } - } - else - { - /* in case the Interrupt is not enabled, return RESET */ - itstatus = RESET; - } - - /* Return the CAN_IT status */ - return itstatus; -} - -/** - * @brief Clears the CANx's interrupt pending bits. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @retval None - */ -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_IT(CAN_IT)); - - switch (CAN_IT) - { - case CAN_IT_TME: - /* Clear CAN_TSR_RQCPx (rc_w1)*/ - CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; - break; - case CAN_IT_FF0: - /* Clear CAN_RF0R_FULL0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FULL0; - break; - case CAN_IT_FOV0: - /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FOVR0; - break; - case CAN_IT_FF1: - /* Clear CAN_RF1R_FULL1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FULL1; - break; - case CAN_IT_FOV1: - /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FOVR1; - break; - case CAN_IT_WKU: - /* Clear CAN_MSR_WKUI (rc_w1)*/ - CANx->MSR = CAN_MSR_WKUI; - break; - case CAN_IT_SLK: - /* Clear CAN_MSR_SLAKI (rc_w1)*/ - CANx->MSR = CAN_MSR_SLAKI; - break; - case CAN_IT_EWG: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_EPV: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_BOF: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_LEC: - /* Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - break; - case CAN_IT_ERR: - /*Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/ - break; - default: - break; - } -} - /** - * @} - */ - -/** - * @brief Checks whether the CAN interrupt has occurred or not. - * @param CAN_Reg: specifies the CAN interrupt register to check. - * @param It_Bit: specifies the interrupt source bit to check. - * @retval The new state of the CAN Interrupt (SET or RESET). - */ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) -{ - ITStatus pendingbitstatus = RESET; - - if ((CAN_Reg & It_Bit) != (uint32_t)RESET) - { - /* CAN_IT is set */ - pendingbitstatus = SET; - } - else - { - /* CAN_IT is reset */ - pendingbitstatus = RESET; - } - return pendingbitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c deleted file mode 100644 index 5c2733074..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c +++ /dev/null @@ -1,127 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_crc.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides all the CRC firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_crc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRC - * @brief CRC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRC_Private_Functions - * @{ - */ - -/** - * @brief Resets the CRC Data register (DR). - * @param None - * @retval None - */ -void CRC_ResetDR(void) -{ - /* Reset CRC generator */ - CRC->CR = CRC_CR_RESET; -} - -/** - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * @param Data: data word(32-bit) to compute its CRC - * @retval 32-bit CRC - */ -uint32_t CRC_CalcCRC(uint32_t Data) -{ - CRC->DR = Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed - * @retval 32-bit CRC - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DR = pBuffer[index]; - } - return (CRC->DR); -} - -/** - * @brief Returns the current CRC value. - * @param None - * @retval 32-bit CRC - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DR); -} - -/** - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param IDValue: 8-bit value to be stored in the ID register - * @retval None - */ -void CRC_SetIDRegister(uint8_t IDValue) -{ - CRC->IDR = IDValue; -} - -/** - * @brief Returns the 8-bit data stored in the Independent Data(ID) register - * @param None - * @retval 8-bit value of the ID register - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDR); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c deleted file mode 100644 index 8ba35d3ad..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c +++ /dev/null @@ -1,850 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_cryp.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the Cryptographic processor (CRYP) peripheral: - * - Initialization and Configuration functions - * - Data treatment functions - * - Context swapping functions - * - DMA interface function - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable the CRYP controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. - * - * 2. Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if - * needed CRYP_IVInit(). - * - * 3. Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function. - * - * 4. Enable the CRYP controller using the CRYP_Cmd() function. - * - * 5. If using DMA for Data input and output transfer, - * Activate the needed DMA Requests using CRYP_DMACmd() function - - * 6. If DMA is not used for data transfer, use CRYP_DataIn() and - * CRYP_DataOut() functions to enter data to IN FIFO and get result - * from OUT FIFO. - * - * 7. To control CRYP events you can use one of the following - * two methods: - * - Check on CRYP flags using the CRYP_GetFlagStatus() function. - * - Use CRYP interrupts through the function CRYP_ITConfig() at - * initialization phase and CRYP_GetITStatus() function into - * interrupt routines in processing phase. - * - * 8. Save and restore Cryptographic processor context using - * CRYP_SaveContext() and CRYP_RestoreContext() functions. - * - * - * =================================================================== - * Procedure to perform an encryption or a decryption - * =================================================================== - * - * Initialization - * =============== - * 1. Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and - * CRYP_IVInit functions: - * - Configure the key size (128-, 192- or 256-bit, in the AES only) - * - Enter the symmetric key - * - Configure the data type - * - In case of decryption in AES-ECB or AES-CBC, you must prepare - * the key: configure the key preparation mode. Then Enable the CRYP - * peripheral using CRYP_Cmd() function: the BUSY flag is set. - * Wait until BUSY flag is reset : the key is prepared for decryption - * - Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the - * AES in ECB/CBC/CTR) - * - Configure the direction (encryption/decryption). - * - Write the initialization vectors (in CBC or CTR modes only) - * - * 2. Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function - * - * - * Basic Processing mode (polling mode) - * ==================================== - * 1. Enable the cryptographic processor using CRYP_Cmd() function. - * - * 2. Write the first blocks in the input FIFO (2 to 8 words) using - * CRYP_DataIn() function. - * - * 3. Repeat the following sequence until the complete message has been - * processed: - * - * a) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() - * function), then read the OUT-FIFO using CRYP_DataOut() function - * (1 block or until the FIFO is empty) - * - * b) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() - * function then write the IN FIFO using CRYP_DataIn() function - * (1 block or until the FIFO is full) - * - * 4. At the end of the processing, CRYP_FLAG_BUSY flag will be reset and - * both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is - * reset). You can disable the peripheral using CRYP_Cmd() function. - * - * Interrupts Processing mode - * =========================== - * In this mode, Processing is done when the data are transferred by the - * CPU during interrupts. - * - * 1. Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using - * CRYP_ITConfig() function. - * - * 2. Enable the cryptographic processor using CRYP_Cmd() function. - * - * 3. In the CRYP_IT_INI interrupt handler : load the input message into the - * IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a - * time, or load data until the IN FIFO is full. When the last word of - * the message has been entered into the IN FIFO, disable the CRYP_IT_INI - * interrupt (using CRYP_ITConfig() function). - * - * 4. In the CRYP_IT_OUTI interrupt handler : read the output message from - * the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or - * 4 words) at a time or read data until the FIFO is empty. - * When the last word has been read, INIM=0, BUSY=0 and both FIFOs are - * empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). - * You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() - * function) and you can disable the peripheral using CRYP_Cmd() function. - * - * DMA Processing mode - * ==================== - * In this mode, Processing is done when the DMA is used to transfer the - * data from/to the memory. - * - * 1. Configure the DMA controller to transfer the input data from the - * memory using DMA_Init() function. - * The transfer length is the length of the message. - * As message padding is not managed by the peripheral, the message - * length must be an entire number of blocks. The data are transferred - * in burst mode. The burst length is 4 words in the AES and 2 or 4 - * words in the DES/TDES. The DMA should be configured to set an - * interrupt on transfer completion of the output data to indicate that - * the processing is finished. - * Refer to DMA peripheral driver for more details. - * - * 2. Enable the cryptographic processor using CRYP_Cmd() function. - * Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT - * using CRYP_DMACmd() function. - * - * 3. All the transfers and processing are managed by the DMA and the - * cryptographic processor. The DMA transfer complete interrupt indicates - * that the processing is complete. Both FIFOs are normally empty and - * CRYP_FLAG_BUSY flag is reset. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_cryp.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define FLAG_MASK ((uint8_t)0x20) -#define MAX_TIMEOUT ((uint16_t)0xFFFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to - - Initialize the cryptographic Processor using CRYP_Init() function - - Encrypt or Decrypt - - mode : TDES-ECB, TDES-CBC, - DES-ECB, DES-CBC, - AES-ECB, AES-CBC, AES-CTR, AES-Key - - DataType : 32-bit data, 16-bit data, bit data or bit-string - - Key Size (only in AES modes) - - Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function - - Configure the Initialization Vectors(IV) for CBC and CTR modes using - CRYP_IVInit() function. - - Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function. - - Enable or disable the CRYP Processor using CRYP_Cmd() function - - -@endverbatim - * @{ - */ -/** - * @brief Deinitializes the CRYP peripheral registers to their default reset values - * @param None - * @retval None - */ -void CRYP_DeInit(void) -{ - /* Enable CRYP reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE); - - /* Release CRYP from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE); -} - -/** - * @brief Initializes the CRYP peripheral according to the specified parameters - * in the CRYP_InitStruct. - * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains - * the configuration information for the CRYP peripheral. - * @retval None - */ -void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct) -{ - /* Check the parameters */ - assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode)); - assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType)); - assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir)); - - /* Select Algorithm mode*/ - CRYP->CR &= ~CRYP_CR_ALGOMODE; - CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode; - - /* Select dataType */ - CRYP->CR &= ~CRYP_CR_DATATYPE; - CRYP->CR |= CRYP_InitStruct->CRYP_DataType; - - /* select Key size (used only with AES algorithm) */ - if ((CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_ECB) || - (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CBC) || - (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CTR) || - (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_Key)) - { - assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize)); - CRYP->CR &= ~CRYP_CR_KEYSIZE; - CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be - configured once the key has - been prepared */ - } - - /* Select data Direction */ - CRYP->CR &= ~CRYP_CR_ALGODIR; - CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir; -} - -/** - * @brief Fills each CRYP_InitStruct member with its default value. - * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct) -{ - /* Initialize the CRYP_AlgoDir member */ - CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - - /* initialize the CRYP_AlgoMode member */ - CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; - - /* initialize the CRYP_DataType member */ - CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b; - - /* Initialize the CRYP_KeySize member */ - CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b; -} - -/** - * @brief Initializes the CRYP Keys according to the specified parameters in - * the CRYP_KeyInitStruct. - * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that - * contains the configuration information for the CRYP Keys. - * @retval None - */ -void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) -{ - /* Key Initialisation */ - CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; - CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; - CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; - CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; - CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; - CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; - CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; - CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; -} - -/** - * @brief Fills each CRYP_KeyInitStruct member with its default value. - * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure - * which will be initialized. - * @retval None - */ -void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) -{ - CRYP_KeyInitStruct->CRYP_Key0Left = 0; - CRYP_KeyInitStruct->CRYP_Key0Right = 0; - CRYP_KeyInitStruct->CRYP_Key1Left = 0; - CRYP_KeyInitStruct->CRYP_Key1Right = 0; - CRYP_KeyInitStruct->CRYP_Key2Left = 0; - CRYP_KeyInitStruct->CRYP_Key2Right = 0; - CRYP_KeyInitStruct->CRYP_Key3Left = 0; - CRYP_KeyInitStruct->CRYP_Key3Right = 0; -} -/** - * @brief Initializes the CRYP Initialization Vectors(IV) according to the - * specified parameters in the CRYP_IVInitStruct. - * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains - * the configuration information for the CRYP Initialization Vectors(IV). - * @retval None - */ -void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) -{ - CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left; - CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right; - CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left; - CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right; -} - -/** - * @brief Fills each CRYP_IVInitStruct member with its default value. - * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization - * Vectors(IV) structure which will be initialized. - * @retval None - */ -void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) -{ - CRYP_IVInitStruct->CRYP_IV0Left = 0; - CRYP_IVInitStruct->CRYP_IV0Right = 0; - CRYP_IVInitStruct->CRYP_IV1Left = 0; - CRYP_IVInitStruct->CRYP_IV1Right = 0; -} - -/** - * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the - * FIFOs are reset) - * @note The FIFOs must be flushed only when BUSY flag is reset. - * @param None - * @retval None - */ -void CRYP_FIFOFlush(void) -{ - /* Reset the read and write pointers of the FIFOs */ - CRYP->CR |= CRYP_CR_FFLUSH; -} - -/** - * @brief Enables or disables the CRYP peripheral. - * @param NewState: new state of the CRYP peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRYP_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Cryptographic processor */ - CRYP->CR |= CRYP_CR_CRYPEN; - } - else - { - /* Disable the Cryptographic processor */ - CRYP->CR &= ~CRYP_CR_CRYPEN; - } -} -/** - * @} - */ - -/** @defgroup CRYP_Group2 CRYP Data processing functions - * @brief CRYP Data processing functions - * -@verbatim - =============================================================================== - CRYP Data processing functions - =============================================================================== - This section provides functions allowing the encryption and decryption - operations: - - Enter data to be treated in the IN FIFO : using CRYP_DataIn() function. - - Get the data result from the OUT FIFO : using CRYP_DataOut() function. - -@endverbatim - * @{ - */ - -/** - * @brief Writes data in the Data Input register (DIN). - * @note After the DIN register has been read once or several times, - * the FIFO must be flushed (using CRYP_FIFOFlush() function). - * @param Data: data to write in Data Input register - * @retval None - */ -void CRYP_DataIn(uint32_t Data) -{ - CRYP->DR = Data; -} - -/** - * @brief Returns the last data entered into the output FIFO. - * @param None - * @retval Last data entered into the output FIFO. - */ -uint32_t CRYP_DataOut(void) -{ - return CRYP->DOUT; -} -/** - * @} - */ - -/** @defgroup CRYP_Group3 Context swapping functions - * @brief Context swapping functions - * -@verbatim - =============================================================================== - Context swapping functions - =============================================================================== - - This section provides functions allowing to save and store CRYP Context - - It is possible to interrupt an encryption/ decryption/ key generation process - to perform another processing with a higher priority, and to complete the - interrupted process later on, when the higher-priority task is complete. To do - so, the context of the interrupted task must be saved from the CRYP registers - to memory, and then be restored from memory to the CRYP registers. - - 1. To save the current context, use CRYP_SaveContext() function - 2. To restore the saved context, use CRYP_RestoreContext() function - - -@endverbatim - * @{ - */ - -/** - * @brief Saves the CRYP peripheral Context. - * @note This function stops DMA transfer before to save the context. After - * restoring the context, you have to enable the DMA again (if the DMA - * was previously used). - * @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains - * the repository for current context. - * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that - * contains the configuration information for the CRYP Keys. - * @retval None - */ -ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, - CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) -{ - __IO uint32_t timeout = 0; - uint32_t ckeckmask = 0, bitstatus; - ErrorStatus status = ERROR; - - /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */ - CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN; - - /* Wait until both the IN and OUT FIFOs are empty - (IFEM=1 and OFNE=0 in the CRYP_SR register) and the - BUSY bit is cleared. */ - - if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */ - { - ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ; - } - else /* AES or DES */ - { - ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE; - } - - do - { - bitstatus = CRYP->SR & ckeckmask; - timeout++; - } - while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM)); - - if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM) - { - status = ERROR; - } - else - { - /* Stop DMA transfers on the OUT FIFO by - - writing the DOEN bit to 0 in the CRYP_DMACR register - - and clear the CRYPEN bit. */ - - CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN; - CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN; - - /* Save the current configuration (bits [9:2] in the CRYP_CR register) */ - CRYP_ContextSave->CR_bits9to2 = CRYP->CR & (CRYP_CR_KEYSIZE | - CRYP_CR_DATATYPE | - CRYP_CR_ALGOMODE | - CRYP_CR_ALGODIR); - - /* and, if not in ECB mode, the initialization vectors. */ - CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR; - CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR; - CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR; - CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR; - - /* save The key value */ - CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; - CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; - CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; - CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; - CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; - CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; - CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; - CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; - - /* When needed, save the DMA status (pointers for IN and OUT messages, - number of remaining bytes, etc.) */ - - status = SUCCESS; - } - - return status; -} - -/** - * @brief Restores the CRYP peripheral Context. - * @note Since teh DMA transfer is stopped in CRYP_SaveContext() function, - * after restoring the context, you have to enable the DMA again (if the - * DMA was previously used). - * @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains - * the repository for saved context. - * @note The data that were saved during context saving must be rewrited into - * the IN FIFO. - * @retval None - */ -void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore) -{ - - /* Configure the processor with the saved configuration */ - CRYP->CR = CRYP_ContextRestore->CR_bits9to2; - - /* restore The key value */ - CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; - CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR; - CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR; - CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR; - CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR; - CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR; - CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR; - CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR; - - /* and the initialization vectors. */ - CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR; - CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR; - CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR; - CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR; - - /* Enable the cryptographic processor */ - CRYP->CR |= CRYP_CR_CRYPEN; -} -/** - * @} - */ - -/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function - * @brief CRYP's DMA interface Configuration function - * -@verbatim - =============================================================================== - CRYP's DMA interface Configuration function - =============================================================================== - - This section provides functions allowing to configure the DMA interface for - CRYP data input and output transfer. - - When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be - transferred: - - From memory to the CRYP IN FIFO using the DMA peripheral by enabling - the CRYP_DMAReq_DataIN request. - - From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling - the CRYP_DMAReq_DataOUT request. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the CRYP DMA interface. - * @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer - * @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer - * @param NewState: new state of the selected CRYP DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CRYP DMA request */ - CRYP->DMACR |= CRYP_DMAReq; - } - else - { - /* Disable the selected CRYP DMA request */ - CRYP->DMACR &= (uint8_t)~CRYP_DMAReq; - } -} -/** - * @} - */ - -/** @defgroup CRYP_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the CRYP Interrupts and - to get the status and Interrupts pending bits. - - The CRYP provides 2 Interrupts sources and 7 Flags: - - Flags : - ------- - - 1. CRYP_FLAG_IFEM : Set when Input FIFO is empty. - This Flag is cleared only by hardware. - - 2. CRYP_FLAG_IFNF : Set when Input FIFO is not full. - This Flag is cleared only by hardware. - - - 3. CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending - it gives the raw interrupt state prior to masking - of the input FIFO service interrupt. - This Flag is cleared only by hardware. - - 4. CRYP_FLAG_OFNE : Set when Output FIFO not empty. - This Flag is cleared only by hardware. - - 5. CRYP_FLAG_OFFU : Set when Output FIFO is full. - This Flag is cleared only by hardware. - - 6. CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending - it gives the raw interrupt state prior to masking - of the output FIFO service interrupt. - This Flag is cleared only by hardware. - - 7. CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a - block of data or a key preparation (for AES - decryption). - This Flag is cleared only by hardware. - To clear it, the CRYP core must be disabled and the - last processing has completed. - - Interrupts : - ------------ - - 1. CRYP_IT_INI : The input FIFO service interrupt is asserted when there - are less than 4 words in the input FIFO. - This interrupt is associated to CRYP_FLAG_INRIS flag. - - @note This interrupt is cleared by performing write operations - to the input FIFO until it holds 4 or more words. The - input FIFO service interrupt INMIS is enabled with the - CRYP enable bit. Consequently, when CRYP is disabled, the - INMIS signal is low even if the input FIFO is empty. - - - - 2. CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there - is one or more (32-bit word) data items in the output FIFO. - This interrupt is associated to CRYP_FLAG_OUTRIS flag. - - @note This interrupt is cleared by reading data from the output - FIFO until there is no valid (32-bit) word left (that is, - the interrupt follows the state of the OFNE (output FIFO - not empty) flag). - - - Managing the CRYP controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the CRYP controller events: Polling mode or Interrupt mode. - - 1. In the Polling Mode it is advised to use the following functions: - - CRYP_GetFlagStatus() : to check if flags events occur. - - @note The CRYPT flags do not need to be cleared since they are cleared as - soon as the associated event are reset. - - - 2. In the Interrupt Mode it is advised to use the following functions: - - CRYP_ITConfig() : to enable or disable the interrupt source. - - CRYP_GetITStatus() : to check if Interrupt occurs. - - @note The CRYPT interrupts have no pending bits, the interrupt is cleared as - soon as the associated event is reset. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified CRYP interrupts. - * @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg CRYP_IT_INI: Input FIFO interrupt - * @arg CRYP_IT_OUTI: Output FIFO interrupt - * @param NewState: new state of the specified CRYP interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CRYP_CONFIG_IT(CRYP_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CRYP interrupt */ - CRYP->IMSCR |= CRYP_IT; - } - else - { - /* Disable the selected CRYP interrupt */ - CRYP->IMSCR &= (uint8_t)~CRYP_IT; - } -} - -/** - * @brief Checks whether the specified CRYP interrupt has occurred or not. - * @note This function checks the status of the masked interrupt (i.e the - * interrupt should be previously enabled). - * @param CRYP_IT: specifies the CRYP (masked) interrupt source to check. - * This parameter can be one of the following values: - * @arg CRYP_IT_INI: Input FIFO interrupt - * @arg CRYP_IT_OUTI: Output FIFO interrupt - * @retval The new state of CRYP_IT (SET or RESET). - */ -ITStatus CRYP_GetITStatus(uint8_t CRYP_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_CRYP_GET_IT(CRYP_IT)); - - /* Check the status of the specified CRYP interrupt */ - if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET) - { - /* CRYP_IT is set */ - bitstatus = SET; - } - else - { - /* CRYP_IT is reset */ - bitstatus = RESET; - } - /* Return the CRYP_IT status */ - return bitstatus; -} - -/** - * @brief Checks whether the specified CRYP flag is set or not. - * @param CRYP_FLAG: specifies the CRYP flag to check. - * This parameter can be one of the following values: - * @arg CRYP_FLAG_IFEM: Input FIFO Empty flag. - * @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag. - * @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag. - * @arg CRYP_FLAG_OFFU: Output FIFO Full flag. - * @arg CRYP_FLAG_BUSY: Busy flag. - * @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag. - * @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag. - * @retval The new state of CRYP_FLAG (SET or RESET). - */ -FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tempreg = 0; - - /* Check the parameters */ - assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG)); - - /* check if the FLAG is in RISR register */ - if ((CRYP_FLAG & FLAG_MASK) != 0x00) - { - tempreg = CRYP->RISR; - } - else /* The FLAG is in SR register */ - { - tempreg = CRYP->SR; - } - - - /* Check the status of the specified CRYP flag */ - if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET) - { - /* CRYP_FLAG is set */ - bitstatus = SET; - } - else - { - /* CRYP_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the CRYP_FLAG status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c deleted file mode 100644 index 00b9fe175..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c +++ /dev/null @@ -1,638 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_cryp_aes.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides high level functions to encrypt and decrypt an - * input message using AES in ECB/CBC/CTR modes. - * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP - * peripheral. - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The CRYP controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. - * - * 2. Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() - * function. - * - * 3. Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() - * function. - * - * 4. Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() - * function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_cryp.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define AESBUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group6 High Level AES functions - * @brief High Level AES functions - * -@verbatim - =============================================================================== - High Level AES functions - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Encrypt and decrypt using AES in ECB Mode - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Key: Key used for AES algorithm. - * @param Keysize: length of the Key, must be a 128, 192 or 256. - * @param Input: pointer to the Input buffer. - * @param Ilength: length of the Input buffer, must be a multiple of 16. - * @param Output: pointer to the returned buffer. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize, - uint8_t* Input, uint32_t Ilength, uint8_t* Output) -{ - CRYP_InitTypeDef AES_CRYP_InitStructure; - CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t i = 0; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure); - - switch(Keysize) - { - case 128: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - case 192: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b; - AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - case 256: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b; - AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - default: - break; - } - - /*------------------ AES Decryption ------------------*/ - if(Mode == MODE_DECRYPT) /* AES decryption */ - { - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Crypto Init for Key preparation for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b; - CRYP_Init(&AES_CRYP_InitStructure); - - /* Key Initialisation */ - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - /* wait until the Busy flag is RESET */ - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - else - { - /* Crypto Init for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - } - } - /*------------------ AES Encryption ------------------*/ - else /* AES encryption */ - { - - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* Crypto Init for Encryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - } - - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&AES_CRYP_InitStructure); - - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - for(i=0; ((i
© COPYRIGHT 2011 STMicroelectronics
- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_cryp.h" - - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define DESBUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group8 High Level DES functions - * @brief High Level DES functions - * -@verbatim - =============================================================================== - High Level DES functions - =============================================================================== -@endverbatim - * @{ - */ - -/** - * @brief Encrypt and decrypt using DES in ECB Mode - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Key: Key used for DES algorithm. - * @param Ilength: length of the Input buffer, must be a multiple of 8. - * @param Input: pointer to the Input buffer. - * @param Output: pointer to the returned buffer. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, - uint32_t Ilength, uint8_t *Output) -{ - CRYP_InitTypeDef DES_CRYP_InitStructure; - CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t i = 0; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure); - - /* Crypto Init for Encryption process */ - if( Mode == MODE_ENCRYPT ) /* DES encryption */ - { - DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - } - else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */ - { - DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - } - - DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB; - DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&DES_CRYP_InitStructure); - - /* Key Initialisation */ - DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - CRYP_KeyInit(& DES_CRYP_KeyInitStructure); - - /* Flush IN/OUT FIFO */ - CRYP_FIFOFlush(); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - for(i=0; ((i
© COPYRIGHT 2011 STMicroelectronics
- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_cryp.h" - - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define TDESBUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group7 High Level TDES functions - * @brief High Level TDES functions - * -@verbatim - =============================================================================== - High Level TDES functions - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Encrypt and decrypt using TDES in ECB Mode - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Key: Key used for TDES algorithm. - * @param Ilength: length of the Input buffer, must be a multiple of 8. - * @param Input: pointer to the Input buffer. - * @param Output: pointer to the returned buffer. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, - uint32_t Ilength, uint8_t *Output) -{ - CRYP_InitTypeDef TDES_CRYP_InitStructure; - CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t i = 0; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure); - - /* Crypto Init for Encryption process */ - if(Mode == MODE_ENCRYPT) /* TDES encryption */ - { - TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - } - else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */ - { - TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - } - - TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; - TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&TDES_CRYP_InitStructure); - - /* Key Initialisation */ - TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - CRYP_KeyInit(& TDES_CRYP_KeyInitStructure); - - /* Flush IN/OUT FIFO */ - CRYP_FIFOFlush(); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - for(i=0; ((i
© COPYRIGHT 2011 STMicroelectronics
- ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dac.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* CR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) - -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) -#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) - -/* DHR registers offsets */ -#define DHR12R1_OFFSET ((uint32_t)0x00000008) -#define DHR12R2_OFFSET ((uint32_t)0x00000014) -#define DHR12RD_OFFSET ((uint32_t)0x00000020) - -/* DOR register offset */ -#define DOR_OFFSET ((uint32_t)0x0000002C) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** @defgroup DAC_Group1 DAC channels configuration - * @brief DAC channels configuration: trigger, output buffer, data format - * -@verbatim - =============================================================================== - DAC channels configuration: trigger, output buffer, data format - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void DAC_DeInit(void) -{ - /* Enable DAC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); - /* Release DAC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); -} - -/** - * @brief Initializes the DAC peripheral according to the specified parameters - * in the DAC_InitStruct. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains - * the configuration information for the specified DAC channel. - * @retval None - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); - assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); - -/*---------------------------- DAC CR Configuration --------------------------*/ - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, - wave generation, mask/amplitude for wave generation */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set WAVEx bits according to DAC_WaveGeneration value */ - /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \ - DAC_InitStruct->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << DAC_Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; -} - -/** - * @brief Fills each DAC_InitStruct member with its default value. - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) -{ -/*--------------- Reset DAC init structure parameters values -----------------*/ - /* Initialize the DAC_Trigger member */ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - /* Initialize the DAC_WaveGeneration member */ - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - /* Initialize the DAC_OutputBuffer member */ - DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -/** - * @brief Enables or disables the specified DAC channel. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @note When the DAC channel is enabled the trigger source can no more be modified. - * @retval None - */ -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel */ - DAC->CR |= (DAC_CR_EN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel */ - DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); - } -} - -/** - * @brief Enables or disables the selected DAC channel software trigger. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for the selected DAC channel */ - DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); - } - else - { - /* Disable software trigger for the selected DAC channel */ - DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enables or disables simultaneously the two DAC channels software triggers. - * @param NewState: new state of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for both DAC channels */ - DAC->SWTRIGR |= DUAL_SWTRIG_SET; - } - else - { - /* Disable software trigger for both DAC channels */ - DAC->SWTRIGR &= DUAL_SWTRIG_RESET; - } -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_Wave: specifies the wave type to enable or disable. - * This parameter can be one of the following values: - * @arg DAC_Wave_Noise: noise wave generation - * @arg DAC_Wave_Triangle: triangle wave generation - * @param NewState: new state of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_WAVE(DAC_Wave)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected wave generation for the selected DAC channel */ - DAC->CR |= DAC_Wave << DAC_Channel; - } - else - { - /* Disable the selected wave generation for the selected DAC channel */ - DAC->CR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: Specifies the data alignment for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R1_OFFSET + DAC_Align; - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Set the specified data holding register value for DAC channel2. - * @param DAC_Align: Specifies the data alignment for DAC channel2. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R2_OFFSET + DAC_Align; - - /* Set the DAC channel2 selected data holding register */ - *(__IO uint32_t *)tmp = Data; -} - -/** - * @brief Set the specified data holding register value for dual channel DAC. - * @param DAC_Align: Specifies the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register. - * @note In dual mode, a unique register access is required to write in both - * DAC channels at the same time. - * @retval None - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12RD_OFFSET + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; -} - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - - tmp = (uint32_t) DAC_BASE ; - tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} -/** - * @} - */ - -/** @defgroup DAC_Group2 DMA management functions - * @brief DMA management functions - * -@verbatim - =============================================================================== - DMA management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC channel DMA request. - * @note When enabled DMA1 is generated when an external trigger (EXTI Line9, - * TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be - * already configured. - * @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be - * already configured. - * @retval None - */ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel DMA request */ - DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel DMA request */ - DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); - } -} -/** - * @} - */ - -/** @defgroup DAC_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC interrupts. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @param NewState: new state of the specified DAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_DAC_IT(DAC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC interrupts */ - DAC->CR |= (DAC_IT << DAC_Channel); - } - else - { - /* Disable the selected DAC interrupts */ - DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); - } -} - -/** - * @brief Checks whether the specified DAC flag is set or not. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to check. - * This parameter can be only of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_FLAG (SET or RESET). - */ -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Check the status of the specified DAC flag */ - if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) - { - /* DAC_FLAG is set */ - bitstatus = SET; - } - else - { - /* DAC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DAC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's pending flags. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to clear. - * This parameter can be of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval None - */ -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Clear the selected DAC flags */ - DAC->SR = (DAC_FLAG << DAC_Channel); -} - -/** - * @brief Checks whether the specified DAC interrupt has occurred or not. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt source to check. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_IT (SET or RESET). - */ -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Get the DAC_IT enable bit status */ - enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; - - /* Check the status of the specified DAC interrupt */ - if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) - { - /* DAC_IT is set */ - bitstatus = SET; - } - else - { - /* DAC_IT is reset */ - bitstatus = RESET; - } - /* Return the DAC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's interrupt pending bits. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt pending bit to clear. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval None - */ -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Clear the selected DAC interrupt pending bits */ - DAC->SR = (DAC_IT << DAC_Channel); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c deleted file mode 100644 index a89e1de3a..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c +++ /dev/null @@ -1,174 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dbgmcu.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides all the DBGMCU firmware functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dbgmcu.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DBGMCU - * @brief DBGMCU driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DBGMCU_Private_Functions - * @{ - */ - -/** - * @brief Returns the device revision identifier. - * @param None - * @retval Device revision identifier - */ -uint32_t DBGMCU_GetREVID(void) -{ - return(DBGMCU->IDCODE >> 16); -} - -/** - * @brief Returns the device identifier. - * @param None - * @retval Device identifier - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); -} - -/** - * @brief Configures low power mode behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the low power mode. - * This parameter can be any combination of the following values: - * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode - * @arg DBGMCU_STOP: Keep debugger connection during STOP mode - * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode - * @param NewState: new state of the specified low power mode in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - DBGMCU->CR |= DBGMCU_Periph; - } - else - { - DBGMCU->CR &= ~DBGMCU_Periph; - } -} - -/** - * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB1 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted - * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted - * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted - * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted - * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted - * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted - * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted - * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted - * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted - * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted. - * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted - * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted - * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted - * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB1FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB1FZ &= ~DBGMCU_Periph; - } -} - -/** - * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB2 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted - * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted - * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted - * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted - * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted - * @param NewState: new state of the specified peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB2FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB2FZ &= ~DBGMCU_Periph; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c deleted file mode 100644 index 5e76501c6..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c +++ /dev/null @@ -1,534 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dcmi.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the DCMI peripheral: - * - Initialization and Configuration - * - Image capture functions - * - Interrupts and flags management - * - * @verbatim - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * The sequence below describes how to use this driver to capture image - * from a camera module connected to the DCMI Interface. - * This sequence does not take into account the configuration of the - * camera module, which should be made before to configure and enable - * the DCMI to capture images. - * - * 1. Enable the clock for the DCMI and associated GPIOs using the following functions: - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - * 2. DCMI pins configuration - * - Connect the involved DCMI pins to AF13 using the following function - * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); - * - Configure these DCMI pins in alternate function mode by calling the function - * GPIO_Init(); - * - * 3. Declare a DCMI_InitTypeDef structure, for example: - * DCMI_InitTypeDef DCMI_InitStructure; - * and fill the DCMI_InitStructure variable with the allowed values - * of the structure member. - * - * 4. Initialize the DCMI interface by calling the function - * DCMI_Init(&DCMI_InitStructure); - * - * 5. Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR - * register to the destination memory buffer. - * - * 6. Enable DCMI interface using the function - * DCMI_Cmd(ENABLE); - * - * 7. Start the image capture using the function - * DCMI_CaptureCmd(ENABLE); - * - * 8. At this stage the DCMI interface waits for the first start of frame, - * then a DMA request is generated continuously/once (depending on the - * mode used, Continuous/Snapshot) to transfer the received data into - * the destination memory. - * - * @note If you need to capture only a rectangular window from the received - * image, you have to use the DCMI_CROPConfig() function to configure - * the coordinates and size of the window to be captured, then enable - * the Crop feature using DCMI_CROPCmd(ENABLE); - * In this case, the Crop configuration should be made before to enable - * and start the DCMI interface. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dcmi.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DCMI - * @brief DCMI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DCMI_Private_Functions - * @{ - */ - -/** @defgroup DCMI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DCMI registers to their default reset values. - * @param None - * @retval None - */ -void DCMI_DeInit(void) -{ - DCMI->CR = 0x0; - DCMI->IER = 0x0; - DCMI->ICR = 0x1F; - DCMI->ESCR = 0x0; - DCMI->ESUR = 0x0; - DCMI->CWSTRTR = 0x0; - DCMI->CWSIZER = 0x0; -} - -/** - * @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct. - * @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains - * the configuration information for the DCMI. - * @retval None - */ -void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct) -{ - uint32_t temp = 0x0; - - /* Check the parameters */ - assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode)); - assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode)); - assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity)); - assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity)); - assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity)); - assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate)); - assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode)); - - /* The DCMI configuration registers should be programmed correctly before - enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */ - DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE); - - /* Reset the old DCMI configuration */ - temp = DCMI->CR; - - temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL | - DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 | - DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1); - - /* Sets the new configuration of the DCMI peripheral */ - temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode | - DCMI_InitStruct->DCMI_SynchroMode | - DCMI_InitStruct->DCMI_PCKPolarity | - DCMI_InitStruct->DCMI_VSPolarity | - DCMI_InitStruct->DCMI_HSPolarity | - DCMI_InitStruct->DCMI_CaptureRate | - DCMI_InitStruct->DCMI_ExtendedDataMode); - - DCMI->CR = temp; -} - -/** - * @brief Fills each DCMI_InitStruct member with its default value. - * @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct) -{ - /* Set the default configuration */ - DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous; - DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware; - DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling; - DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low; - DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low; - DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame; - DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b; -} - -/** - * @brief Initializes the DCMI peripheral CROP mode according to the specified - * parameters in the DCMI_CROPInitStruct. - * @note This function should be called before to enable and start the DCMI interface. - * @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that - * contains the configuration information for the DCMI peripheral CROP mode. - * @retval None - */ -void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct) -{ - /* Sets the CROP window coordinates */ - DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount | - ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16)); - - /* Sets the CROP window size */ - DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount | - ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16)); -} - -/** - * @brief Enables or disables the DCMI Crop feature. - * @note This function should be called before to enable and start the DCMI interface. - * @param NewState: new state of the DCMI Crop feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_CROPCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI Crop feature */ - DCMI->CR |= (uint32_t)DCMI_CR_CROP; - } - else - { - /* Disable the DCMI Crop feature */ - DCMI->CR &= ~(uint32_t)DCMI_CR_CROP; - } -} - -/** - * @brief Sets the embedded synchronization codes - * @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that - * contains the embedded synchronization codes for the DCMI peripheral. - * @retval None - */ -void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct) -{ - DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode | - ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)| - ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)| - ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24)); -} - -/** - * @brief Enables or disables the DCMI JPEG format. - * @note The Crop and Embedded Synchronization features cannot be used in this mode. - * @param NewState: new state of the DCMI JPEG format. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_JPEGCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI JPEG format */ - DCMI->CR |= (uint32_t)DCMI_CR_JPEG; - } - else - { - /* Disable the DCMI JPEG format */ - DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG; - } -} -/** - * @} - */ - -/** @defgroup DCMI_Group2 Image capture functions - * @brief Image capture functions - * -@verbatim - =============================================================================== - Image capture functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the DCMI interface. - * @param NewState: new state of the DCMI interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI by setting ENABLE bit */ - DCMI->CR |= (uint32_t)DCMI_CR_ENABLE; - } - else - { - /* Disable the DCMI by clearing ENABLE bit */ - DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE; - } -} - -/** - * @brief Enables or disables the DCMI Capture. - * @param NewState: new state of the DCMI capture. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_CaptureCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI Capture */ - DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE; - } - else - { - /* Disable the DCMI Capture */ - DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE; - } -} - -/** - * @brief Reads the data stored in the DR register. - * @param None - * @retval Data register value - */ -uint32_t DCMI_ReadData(void) -{ - return DCMI->DR; -} -/** - * @} - */ - -/** @defgroup DCMI_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the DCMI interface interrupts. - * @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @param NewState: new state of the specified DCMI interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DCMI_CONFIG_IT(DCMI_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - DCMI->IER |= DCMI_IT; - } - else - { - /* Disable the Interrupt sources */ - DCMI->IER &= (uint16_t)(~DCMI_IT); - } -} - -/** - * @brief Checks whether the DCMI interface flag is set or not. - * @param DCMI_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask - * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask - * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask - * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask - * @arg DCMI_FLAG_LINERI: Line Raw flag mask - * @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask - * @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask - * @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask - * @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask - * @arg DCMI_FLAG_LINEMI: Line Masked flag mask - * @arg DCMI_FLAG_HSYNC: HSYNC flag mask - * @arg DCMI_FLAG_VSYNC: VSYNC flag mask - * @arg DCMI_FLAG_FNE: Fifo not empty flag mask - * @retval The new state of DCMI_FLAG (SET or RESET). - */ -FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t dcmireg, tempreg = 0; - - /* Check the parameters */ - assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG)); - - /* Get the DCMI register index */ - dcmireg = (((uint16_t)DCMI_FLAG) >> 12); - - if (dcmireg == 0x01) /* The FLAG is in RISR register */ - { - tempreg= DCMI->RISR; - } - else if (dcmireg == 0x02) /* The FLAG is in SR register */ - { - tempreg = DCMI->SR; - } - else /* The FLAG is in MISR register */ - { - tempreg = DCMI->MISR; - } - - if ((tempreg & DCMI_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the DCMI_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DCMI's pending flags. - * @param DCMI_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask - * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask - * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask - * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask - * @arg DCMI_FLAG_LINERI: Line Raw flag mask - * @retval None - */ -void DCMI_ClearFlag(uint16_t DCMI_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG)); - - /* Clear the flag by writing in the ICR register 1 in the corresponding - Flag position*/ - - DCMI->ICR = DCMI_FLAG; -} - -/** - * @brief Checks whether the DCMI interrupt has occurred or not. - * @param DCMI_IT: specifies the DCMI interrupt source to check. - * This parameter can be one of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @retval The new state of DCMI_IT (SET or RESET). - */ -ITStatus DCMI_GetITStatus(uint16_t DCMI_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itstatus = 0; - - /* Check the parameters */ - assert_param(IS_DCMI_GET_IT(DCMI_IT)); - - itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */ - - if ((itstatus != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the DCMI's interrupt pending bits. - * @param DCMI_IT: specifies the DCMI interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @retval None - */ -void DCMI_ClearITPendingBit(uint16_t DCMI_IT) -{ - /* Clear the interrupt pending Bit by writing in the ICR register 1 in the - corresponding pending Bit position*/ - - DCMI->ICR = DCMI_IT; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c deleted file mode 100644 index 92a3692d1..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c +++ /dev/null @@ -1,1283 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dma.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access controller (DMA): - * - Initialization and Configuration - * - Data Counter - * - Double Buffer mode configuration and command - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE) - * function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE) - * function for DMA2. - * - * 2. Enable and configure the peripheral to be connected to the DMA Stream - * (except for internal SRAM / FLASH memories: no initialization is - * necessary). - * - * 3. For a given Stream, program the required configuration through following parameters: - * Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination - * data formats, Circular or Normal mode, Stream Priority level, Source and Destination - * Incrementation mode, FIFO mode and its Threshold (if needed), Burst mode for Source and/or - * Destination (if needed) using the DMA_Init() function. - * To avoid filling un-nesecessary fields, you can call DMA_StructInit() function - * to initialize a given structure with default values (reset values), the modify - * only necessary fields (ie. Source and Destination addresses, Transfer size and Data Formats). - * - * 4. Enable the NVIC and the corresponding interrupt(s) using the function - * DMA_ITConfig() if you need to use DMA interrupts. - * - * 5. Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring - * the second Memory address and the first Memory to be used through the function - * DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function - * DMA_DoubleBufferModeCmd(). These operations must be done before step 6. - * - * 6. Enable the DMA stream using the DMA_Cmd() function. - * - * 7. Activate the needed Stream Request using PPP_DMACmd() function for - * any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) - * The function allowing this operation is provided in each PPP peripheral - * driver (ie. SPI_DMACmd for SPI peripheral). - * Once the Stream is enabled, it is not possible to modify its configuration - * unless the stream is stopped and disabled. - * After enabling the Stream, it is advised to monitor the EN bit status using - * the function DMA_GetCmdStatus(). In case of configuration errors or bus errors - * this bit will remain reset and all transfers on this Stream will remain on hold. - * - * 8. Optionally, you can configure the number of data to be transferred - * when the Stream is disabled (ie. after each Transfer Complete event - * or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). - * And you can get the number of remaining data to be transferred using - * the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is - * enabled and running). - * - * 9. To control DMA events you can use one of the following - * two methods: - * a- Check on DMA Stream flags using the function DMA_GetFlagStatus(). - * b- Use DMA interrupts through the function DMA_ITConfig() at initialization - * phase and DMA_GetITStatus() function into interrupt routines in - * communication phase. - * After checking on a flag you should clear it using DMA_ClearFlag() - * function. And after checking on an interrupt event you should - * clear it using DMA_ClearITPendingBit() function. - * - * 10. Optionally, if Circular mode and Double Buffer mode are enabled, you can modify - * the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that - * the Memory Address to be modified is not the one currently in use by DMA Stream. - * This condition can be monitored using the function DMA_GetCurrentMemoryTarget(). - * - * 11. Optionally, Pause-Resume operations may be performed: - * The DMA_Cmd() function may be used to perform Pause-Resume operation. When a - * transfer is ongoing, calling this function to disable the Stream will cause the - * transfer to be paused. All configuration registers and the number of remaining - * data will be preserved. When calling again this function to re-enable the Stream, - * the transfer will be resumed from the point where it was paused. - * - * @note Memory-to-Memory transfer is possible by setting the address of the memory into - * the Peripheral registers. In this mode, Circular mode and Double Buffer mode - * are not allowed. - * - * @note The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is - * possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set - * Half-Word data size for the peripheral to access its data register and set Word data size - * for the Memory to gain in access time. Each two Half-words will be packed and written in - * a single access to a Word in the Memory). - * - * @note When FIFO is disabled, it is not allowed to configure different Data Sizes for Source - * and Destination. In this case the Peripheral Data Size will be applied to both Source - * and Destination. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dma.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Masks Definition */ -#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \ - DMA_SxCR_TEIE | DMA_SxCR_DMEIE) - -#define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \ - DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \ - DMA_LISR_TCIF0) - -#define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6) -#define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16) -#define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22) -#define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000) -#define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C -#define HIGH_ISR_MASK (uint32_t)0x20000000 -#define RESERVED_MASK (uint32_t)0x0F7D0F7D - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/** @defgroup DMA_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This subsection provides functions allowing to initialize the DMA Stream source - and destination addresses, incrementation and data sizes, transfer direction, - buffer size, circular/normal mode selection, memory-to-memory mode selection - and Stream priority value. - - The DMA_Init() function follows the DMA configuration procedures as described in - reference manual (RM0090) except the first point: waiting on EN bit to be reset. - This condition should be checked by user application using the function DMA_GetCmdStatus() - before calling the DMA_Init() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitialize the DMAy Streamx registers to their default reset values. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval None - */ -void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Disable the selected DMAy Streamx */ - DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN); - - /* Reset DMAy Streamx control register */ - DMAy_Streamx->CR = 0; - - /* Reset DMAy Streamx Number of Data to Transfer register */ - DMAy_Streamx->NDTR = 0; - - /* Reset DMAy Streamx peripheral address register */ - DMAy_Streamx->PAR = 0; - - /* Reset DMAy Streamx memory 0 address register */ - DMAy_Streamx->M0AR = 0; - - /* Reset DMAy Streamx memory 1 address register */ - DMAy_Streamx->M1AR = 0; - - /* Reset DMAy Streamx FIFO control register */ - DMAy_Streamx->FCR = (uint32_t)0x00000021; - - /* Reset interrupt pending bits for the selected stream */ - if (DMAy_Streamx == DMA1_Stream0) - { - /* Reset interrupt pending bits for DMA1 Stream0 */ - DMA1->LIFCR = DMA_Stream0_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream1) - { - /* Reset interrupt pending bits for DMA1 Stream1 */ - DMA1->LIFCR = DMA_Stream1_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream2) - { - /* Reset interrupt pending bits for DMA1 Stream2 */ - DMA1->LIFCR = DMA_Stream2_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream3) - { - /* Reset interrupt pending bits for DMA1 Stream3 */ - DMA1->LIFCR = DMA_Stream3_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream4) - { - /* Reset interrupt pending bits for DMA1 Stream4 */ - DMA1->HIFCR = DMA_Stream4_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream5) - { - /* Reset interrupt pending bits for DMA1 Stream5 */ - DMA1->HIFCR = DMA_Stream5_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream6) - { - /* Reset interrupt pending bits for DMA1 Stream6 */ - DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream7) - { - /* Reset interrupt pending bits for DMA1 Stream7 */ - DMA1->HIFCR = DMA_Stream7_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream0) - { - /* Reset interrupt pending bits for DMA2 Stream0 */ - DMA2->LIFCR = DMA_Stream0_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream1) - { - /* Reset interrupt pending bits for DMA2 Stream1 */ - DMA2->LIFCR = DMA_Stream1_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream2) - { - /* Reset interrupt pending bits for DMA2 Stream2 */ - DMA2->LIFCR = DMA_Stream2_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream3) - { - /* Reset interrupt pending bits for DMA2 Stream3 */ - DMA2->LIFCR = DMA_Stream3_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream4) - { - /* Reset interrupt pending bits for DMA2 Stream4 */ - DMA2->HIFCR = DMA_Stream4_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream5) - { - /* Reset interrupt pending bits for DMA2 Stream5 */ - DMA2->HIFCR = DMA_Stream5_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream6) - { - /* Reset interrupt pending bits for DMA2 Stream6 */ - DMA2->HIFCR = DMA_Stream6_IT_MASK; - } - else - { - if (DMAy_Streamx == DMA2_Stream7) - { - /* Reset interrupt pending bits for DMA2 Stream7 */ - DMA2->HIFCR = DMA_Stream7_IT_MASK; - } - } -} - -/** - * @brief Initializes the DMAy Streamx according to the specified parameters in - * the DMA_InitStruct structure. - * @note Before calling this function, it is recommended to check that the Stream - * is actually disabled using the function DMA_GetCmdStatus(). - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval None - */ -void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel)); - assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR)); - assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); - assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); - assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); - assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode)); - assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold)); - assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst)); - assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst)); - - /*------------------------- DMAy Streamx CR Configuration ------------------*/ - /* Get the DMAy_Streamx CR value */ - tmpreg = DMAy_Streamx->CR; - - /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ - DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ - DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ - DMA_SxCR_DIR)); - - /* Configure DMAy Streamx: */ - /* Set CHSEL bits according to DMA_CHSEL value */ - /* Set DIR bits according to DMA_DIR value */ - /* Set PINC bit according to DMA_PeripheralInc value */ - /* Set MINC bit according to DMA_MemoryInc value */ - /* Set PSIZE bits according to DMA_PeripheralDataSize value */ - /* Set MSIZE bits according to DMA_MemoryDataSize value */ - /* Set CIRC bit according to DMA_Mode value */ - /* Set PL bits according to DMA_Priority value */ - /* Set MBURST bits according to DMA_MemoryBurst value */ - /* Set PBURST bits according to DMA_PeripheralBurst value */ - tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority | - DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst; - - /* Write to DMAy Streamx CR register */ - DMAy_Streamx->CR = tmpreg; - - /*------------------------- DMAy Streamx FCR Configuration -----------------*/ - /* Get the DMAy_Streamx FCR value */ - tmpreg = DMAy_Streamx->FCR; - - /* Clear DMDIS and FTH bits */ - tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); - - /* Configure DMAy Streamx FIFO: - Set DMDIS bits according to DMA_FIFOMode value - Set FTH bits according to DMA_FIFOThreshold value */ - tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold; - - /* Write to DMAy Streamx CR */ - DMAy_Streamx->FCR = tmpreg; - - /*------------------------- DMAy Streamx NDTR Configuration ----------------*/ - /* Write to DMAy Streamx NDTR register */ - DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize; - - /*------------------------- DMAy Streamx PAR Configuration -----------------*/ - /* Write to DMAy Streamx PAR */ - DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr; - - /*------------------------- DMAy Streamx M0AR Configuration ----------------*/ - /* Write to DMAy Streamx M0AR */ - DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ - /*-------------- Reset DMA init structure parameters values ----------------*/ - /* Initialize the DMA_Channel member */ - DMA_InitStruct->DMA_Channel = 0; - - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - - /* Initialize the DMA_Memory0BaseAddr member */ - DMA_InitStruct->DMA_Memory0BaseAddr = 0; - - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory; - - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - - /* Initialize the DMA_MemoryInc member */ - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - - /* Initialize the DMA_Priority member */ - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - - /* Initialize the DMA_FIFOMode member */ - DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable; - - /* Initialize the DMA_FIFOThreshold member */ - DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; - - /* Initialize the DMA_MemoryBurst member */ - DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single; - - /* Initialize the DMA_PeripheralBurst member */ - DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single; -} - -/** - * @brief Enables or disables the specified DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param NewState: new state of the DMAy Streamx. - * This parameter can be: ENABLE or DISABLE. - * - * @note This function may be used to perform Pause-Resume operation. When a - * transfer is ongoing, calling this function to disable the Stream will - * cause the transfer to be paused. All configuration registers and the - * number of remaining data will be preserved. When calling again this - * function to re-enable the Stream, the transfer will be resumed from - * the point where it was paused. - * - * @note After configuring the DMA Stream (DMA_Init() function) and enabling the - * stream, it is recommended to check (or wait until) the DMA Stream is - * effectively enabled. A Stream may remain disabled if a configuration - * parameter is wrong. - * After disabling a DMA Stream, it is also recommended to check (or wait - * until) the DMA Stream is effectively disabled. If a Stream is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Stream will be effectively disabled only after the transfer of - * this single data is finished. - * - * @retval None - */ -void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMAy Streamx by setting EN bit */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN; - } - else - { - /* Disable the selected DMAy Streamx by clearing EN bit */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN; - } -} - -/** - * @brief Configures, when the PINC (Peripheral Increment address mode) bit is - * set, if the peripheral address should be incremented with the data - * size (configured with PSIZE bits) or by a fixed offset equal to 4 - * (32-bit aligned addresses). - * - * @note This function has no effect if the Peripheral Increment mode is disabled. - * - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_Pincos: specifies the Peripheral increment offset size. - * This parameter can be one of the following values: - * @arg DMA_PINCOS_Psize: Peripheral address increment is done - * accordingly to PSIZE parameter. - * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is - * fixed to 4 (32-bit aligned addresses). - * @retval None - */ -void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos)); - - /* Check the needed Peripheral increment offset */ - if(DMA_Pincos != DMA_PINCOS_Psize) - { - /* Configure DMA_SxCR_PINCOS bit with the input parameter */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS; - } - else - { - /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS; - } -} - -/** - * @brief Configures, when the DMAy Streamx is disabled, the flow controller for - * the next transactions (Peripheral or Memory). - * - * @note Before enabling this feature, check if the used peripheral supports - * the Flow Controller mode or not. - * - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FlowCtrl: specifies the DMA flow controller. - * This parameter can be one of the following values: - * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is - * the DMA controller. - * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller - * is the peripheral. - * @retval None - */ -void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl)); - - /* Check the needed flow controller */ - if(DMA_FlowCtrl != DMA_FlowCtrl_Memory) - { - /* Configure DMA_SxCR_PFCTRL bit with the input parameter */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL; - } - else - { - /* Clear the PFCTRL bit: Memory is the flow controller */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL; - } -} -/** - * @} - */ - -/** @defgroup DMA_Group2 Data Counter functions - * @brief Data Counter functions - * -@verbatim - =============================================================================== - Data Counter functions - =============================================================================== - - This subsection provides function allowing to configure and read the buffer size - (number of data to be transferred). - - The DMA data counter can be written only when the DMA Stream is disabled - (ie. after transfer complete event). - - The following function can be used to write the Stream data counter value: - - void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); - -@note It is advised to use this function rather than DMA_Init() in situations where - only the Data buffer needs to be reloaded. - -@note If the Source and Destination Data Sizes are different, then the value written in - data counter, expressing the number of transfers, is relative to the number of - transfers from the Peripheral point of view. - ie. If Memory data size is Word, Peripheral data size is Half-Words, then the value - to be configured in the data counter is the number of Half-Words to be transferred - from/to the peripheral. - - The DMA data counter can be read to indicate the number of remaining transfers for - the relative DMA Stream. This counter is decremented at the end of each data - transfer and when the transfer is complete: - - If Normal mode is selected: the counter is set to 0. - - If Circular mode is selected: the counter is reloaded with the initial value - (configured before enabling the DMA Stream) - - The following function can be used to read the Stream data counter value: - - uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); - -@endverbatim - * @{ - */ - -/** - * @brief Writes the number of data units to be transferred on the DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param Counter: Number of data units to be transferred (from 0 to 65535) - * Number of data items depends only on the Peripheral data format. - * - * @note If Peripheral data format is Bytes: number of data units is equal - * to total number of bytes to be transferred. - * - * @note If Peripheral data format is Half-Word: number of data units is - * equal to total number of bytes to be transferred / 2. - * - * @note If Peripheral data format is Word: number of data units is equal - * to total number of bytes to be transferred / 4. - * - * @note In Memory-to-Memory transfer mode, the memory buffer pointed by - * DMAy_SxPAR register is considered as Peripheral. - * - * @retval The number of remaining data units in the current DMAy Streamx transfer. - */ -void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Write the number of data units to be transferred */ - DMAy_Streamx->NDTR = (uint16_t)Counter; -} - -/** - * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The number of remaining data units in the current DMAy Streamx transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Return the number of remaining data units for DMAy Streamx */ - return ((uint16_t)(DMAy_Streamx->NDTR)); -} -/** - * @} - */ - -/** @defgroup DMA_Group3 Double Buffer mode functions - * @brief Double Buffer mode functions - * -@verbatim - =============================================================================== - Double Buffer mode functions - =============================================================================== - - This subsection provides function allowing to configure and control the double - buffer mode parameters. - - The Double Buffer mode can be used only when Circular mode is enabled. - The Double Buffer mode cannot be used when transferring data from Memory to Memory. - - The Double Buffer mode allows to set two different Memory addresses from/to which - the DMA controller will access alternatively (after completing transfer to/from target - memory 0, it will start transfer to/from target memory 1). - This allows to reduce software overhead for double buffering and reduce the CPU - access time. - - Two functions must be called before calling the DMA_Init() function: - - void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory); - - void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); - - DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address and the first - Memory target from/to which the transfer will start after enabling the DMA Stream. - Then DMA_DoubleBufferModeCmd() must be called to enable the Double Buffer mode (or disable - it when it should not be used). - - - Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is - stopped) to modify on of the target Memories addresses or to check wich Memory target is currently - used: - - void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget); - - uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); - - DMA_MemoryTargetConfig() can be called to modify the base address of one of the two target Memories. - The Memory of which the base address will be modified must not be currently be used by the DMA Stream - (ie. if the DMA Stream is currently transferring from Memory 1 then you can only modify base address - of target Memory 0 and vice versa). - To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which - returns the index of the Memory target currently in use by the DMA Stream. - -@endverbatim - * @{ - */ - -/** - * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode - * and the current memory target. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param Memory1BaseAddr: the base address of the second buffer (Memory 1) - * @param DMA_CurrentMemory: specifies which memory will be first buffer for - * the transactions when the Stream will be enabled. - * This parameter can be one of the following values: - * @arg DMA_Memory_0: Memory 0 is the current buffer. - * @arg DMA_Memory_1: Memory 1 is the current buffer. - * - * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init(). - * - * @retval None - */ -void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory)); - - if (DMA_CurrentMemory != DMA_Memory_0) - { - /* Set Memory 1 as current memory address */ - DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT); - } - else - { - /* Set Memory 0 as current memory address */ - DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT); - } - - /* Write to DMAy Streamx M1AR */ - DMAy_Streamx->M1AR = Memory1BaseAddr; -} - -/** - * @brief Enables or disables the double buffer mode for the selected DMA stream. - * @note This function can be called only when the DMA Stream is disabled. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param NewState: new state of the DMAy Streamx double buffer mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Configure the Double Buffer mode */ - if (NewState != DISABLE) - { - /* Enable the Double buffer mode */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM; - } - else - { - /* Disable the Double buffer mode */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM; - } -} - -/** - * @brief Configures the Memory address for the next buffer transfer in double - * buffer mode (for dynamic use). This function can be called when the - * DMA Stream is enabled and when the transfer is ongoing. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param MemoryBaseAddr: The base address of the target memory buffer - * @param DMA_MemoryTarget: Next memory target to be used. - * This parameter can be one of the following values: - * @arg DMA_Memory_0: To use the memory address 0 - * @arg DMA_Memory_1: To use the memory address 1 - * - * @note It is not allowed to modify the Base Address of a target Memory when - * this target is involved in the current transfer. ie. If the DMA Stream - * is currently transferring to/from Memory 1, then it not possible to - * modify Base address of Memory 1, but it is possible to modify Base - * address of Memory 0. - * To know which Memory is currently used, you can use the function - * DMA_GetCurrentMemoryTarget(). - * - * @retval None - */ -void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget)); - - /* Check the Memory target to be configured */ - if (DMA_MemoryTarget != DMA_Memory_0) - { - /* Write to DMAy Streamx M1AR */ - DMAy_Streamx->M1AR = MemoryBaseAddr; - } - else - { - /* Write to DMAy Streamx M0AR */ - DMAy_Streamx->M0AR = MemoryBaseAddr; - } -} - -/** - * @brief Returns the current memory target used by double buffer transfer. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The memory target number: 0 for Memory0 or 1 for Memory1. - */ -uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Get the current memory target */ - if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0) - { - /* Current memory buffer used is Memory 1 */ - tmp = 1; - } - else - { - /* Current memory buffer used is Memory 0 */ - tmp = 0; - } - return tmp; -} -/** - * @} - */ - -/** @defgroup DMA_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This subsection provides functions allowing to - - Check the DMA enable status - - Check the FIFO status - - Configure the DMA Interrupts sources and check or clear the flags or pending bits status. - - 1. DMA Enable status: - After configuring the DMA Stream (DMA_Init() function) and enabling the stream, - it is recommended to check (or wait until) the DMA Stream is effectively enabled. - A Stream may remain disabled if a configuration parameter is wrong. - After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA - Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, - the current data will be transferred and the Stream will be effectively disabled only after - this data transfer completion. - To monitor this state it is possible to use the following function: - - FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); - - 2. FIFO Status: - It is possible to monitor the FIFO status when a transfer is ongoing using the following - function: - - uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); - - 3. DMA Interrupts and Flags: - The user should identify which mode will be used in his application to manage the - DMA controller events: Polling mode or Interrupt mode. - - Polling Mode - ============= - Each DMA stream can be managed through 4 event Flags: - (x : DMA Stream number ) - 1. DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred. - 2. DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred. - 3. DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred. - 4. DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred. - 5. DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred . - - In this Mode it is advised to use the following functions: - - FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); - - void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); - - Interrupt Mode - =============== - Each DMA Stream can be managed through 4 Interrupts: - - Interrupt Source - ---------------- - 1. DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event. - 2. DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event. - 3. DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event. - 4. DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event. - 5. DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event. - - In this Mode it is advised to use the following functions: - - void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); - - ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - - void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - -@endverbatim - * @{ - */ - -/** - * @brief Returns the status of EN bit for the specified DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * - * @note After configuring the DMA Stream (DMA_Init() function) and enabling - * the stream, it is recommended to check (or wait until) the DMA Stream - * is effectively enabled. A Stream may remain disabled if a configuration - * parameter is wrong. - * After disabling a DMA Stream, it is also recommended to check (or wait - * until) the DMA Stream is effectively disabled. If a Stream is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Stream will be effectively disabled only after the transfer - * of this single data is finished. - * - * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). - */ -FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx) -{ - FunctionalState state = DISABLE; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0) - { - /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */ - state = ENABLE; - } - else - { - /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and - all transfers are complete) */ - state = DISABLE; - } - return state; -} - -/** - * @brief Returns the current DMAy Streamx FIFO filled level. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The FIFO filling state. - * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full - * and not empty. - * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. - * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. - * - DMA_FIFOStatus_Empty: when FIFO is empty - * - DMA_FIFOStatus_Full: when FIFO is full - */ -uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Get the FIFO level bits */ - tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS)); - - return tmpreg; -} - -/** - * @brief Checks whether the specified DMAy Streamx flag is set or not. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag - * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag - * @arg DMA_FLAG_TEIFx: Streamx transfer error flag - * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag - * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag - * Where x can be 0 to 7 to select the DMA Stream. - * @retval The new state of DMA_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) -{ - FlagStatus bitstatus = RESET; - DMA_TypeDef* DMAy; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if the flag is in HISR or LISR */ - if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Get DMAy HISR register value */ - tmpreg = DMAy->HISR; - } - else - { - /* Get DMAy LISR register value */ - tmpreg = DMAy->LISR; - } - - /* Mask the reserved bits */ - tmpreg &= (uint32_t)RESERVED_MASK; - - /* Check the status of the specified DMA flag */ - if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) - { - /* DMA_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMA_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the DMA_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Streamx's pending flags. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag - * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag - * @arg DMA_FLAG_TEIFx: Streamx transfer error flag - * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag - * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag - * Where x can be 0 to 7 to select the DMA Stream. - * @retval None - */ -void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) -{ - DMA_TypeDef* DMAy; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if LIFCR or HIFCR register is targeted */ - if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Set DMAy HIFCR register clear flag bits */ - DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); - } - else - { - /* Set DMAy LIFCR register clear flag bits */ - DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); - } -} - -/** - * @brief Enables or disables the specified DMAy Streamx interrupts. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @arg DMA_IT_FE: FIFO error interrupt mask - * @param NewState: new state of the specified DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CONFIG_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Check if the DMA_IT parameter contains a FIFO interrupt */ - if ((DMA_IT & DMA_IT_FE) != 0) - { - if (NewState != DISABLE) - { - /* Enable the selected DMA FIFO interrupts */ - DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE; - } - else - { - /* Disable the selected DMA FIFO interrupts */ - DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE; - } - } - - /* Check if the DMA_IT parameter contains a Transfer interrupt */ - if (DMA_IT != DMA_IT_FE) - { - if (NewState != DISABLE) - { - /* Enable the selected DMA transfer interrupts */ - DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); - } - else - { - /* Disable the selected DMA transfer interrupts */ - DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); - } - } -} - -/** - * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt - * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt - * @arg DMA_IT_TEIFx: Streamx transfer error interrupt - * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt - * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt - * Where x can be 0 to 7 to select the DMA Stream. - * @retval The new state of DMA_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) -{ - ITStatus bitstatus = RESET; - DMA_TypeDef* DMAy; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_GET_IT(DMA_IT)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if the interrupt enable bit is in the CR or FCR register */ - if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET) - { - /* Get the interrupt enable position mask in CR register */ - tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK); - - /* Check the enable bit in CR register */ - enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg); - } - else - { - /* Check the enable bit in FCR register */ - enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); - } - - /* Check if the interrupt pending flag is in LISR or HISR */ - if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Get DMAy HISR register value */ - tmpreg = DMAy->HISR ; - } - else - { - /* Get DMAy LISR register value */ - tmpreg = DMAy->LISR ; - } - - /* mask all reserved bits */ - tmpreg &= (uint32_t)RESERVED_MASK; - - /* Check the status of the specified DMA interrupt */ - if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - /* DMA_IT is set */ - bitstatus = SET; - } - else - { - /* DMA_IT is reset */ - bitstatus = RESET; - } - - /* Return the DMA_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Streamx's interrupt pending bits. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt - * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt - * @arg DMA_IT_TEIFx: Streamx transfer error interrupt - * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt - * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt - * Where x can be 0 to 7 to select the DMA Stream. - * @retval None - */ -void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) -{ - DMA_TypeDef* DMAy; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CLEAR_IT(DMA_IT)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if LIFCR or HIFCR register is targeted */ - if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Set DMAy HIFCR register clear interrupt bits */ - DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); - } - else - { - /* Set DMAy LIFCR register clear interrupt bits */ - DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c deleted file mode 100644 index bcb597139..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c +++ /dev/null @@ -1,306 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_exti.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the EXTI peripheral: - * - Initialization and Configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * EXTI features - * =================================================================== - * - * External interrupt/event lines are mapped as following: - * 1- All available GPIO pins are connected to the 16 external - * interrupt/event lines from EXTI0 to EXTI15. - * 2- EXTI line 16 is connected to the PVD Output - * 3- EXTI line 17 is connected to the RTC Alarm event - * 4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event - * 5- EXTI line 19 is connected to the Ethernet Wakeup event - * 6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event - * 7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events - * 8- EXTI line 22 is connected to the RTC Wakeup event - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * In order to use an I/O pin as an external interrupt source, follow - * steps below: - * 1- Configure the I/O in input mode using GPIO_Init() - * 2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig() - * 3- Select the mode(interrupt, event) and configure the trigger - * selection (Rising, falling or both) using EXTI_Init() - * 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init() - * - * @note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx - * registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_exti.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** @defgroup EXTI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - EXTI->IMR = 0x00000000; - EXTI->EMR = 0x00000000; - EXTI->RTSR = 0x00000000; - EXTI->FTSR = 0x00000000; - EXTI->PR = 0x007FFFFF; -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - - tmp = (uint32_t)EXTI_BASE; - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; - - tmp += EXTI_InitStruct->EXTI_Mode; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; - - /* Select the trigger for the selected external interrupts */ - if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - /* Rising Falling edge */ - EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - - /* Disable the selected external lines */ - *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param EXTI_Line: specifies the EXTI line on which the software interrupt - * will be generated. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->SWIER |= EXTI_Line; -} - -/** - * @} - */ - -/** @defgroup EXTI_Group2 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param EXTI_Line: specifies the EXTI line flag to check. - * This parameter can be EXTI_Linex where x can be(0..22) - * @retval The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending flags. - * @param EXTI_Line: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_Line: specifies the EXTI line to check. - * This parameter can be EXTI_Linex where x can be(0..22) - * @retval The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - enablestatus = EXTI->IMR & EXTI_Line; - if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending bits. - * @param EXTI_Line: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c deleted file mode 100644 index a3bce02ec..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c +++ /dev/null @@ -1,1054 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_flash.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the FLASH peripheral: - * - FLASH Interface configuration - * - FLASH Memory Programming - * - Option Bytes Programming - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * This driver provides functions to configure and program the FLASH - * memory of all STM32F4xx devices. - * These functions are split in 4 groups: - * - * 1. FLASH Interface configuration functions: this group includes the - * management of the following features: - * - Set the latency - * - Enable/Disable the prefetch buffer - * - Enable/Disable the Instruction cache and the Data cache - * - Reset the Instruction cache and the Data cache - * - * 2. FLASH Memory Programming functions: this group includes all needed - * functions to erase and program the main memory: - * - Lock and Unlock the FLASH interface - * - Erase function: Erase sector, erase all sectors - * - Program functions: byte, half word, word and double word - * - * 3. Option Bytes Programming functions: this group includes all needed - * functions to manage the Option Bytes: - * - Set/Reset the write protection - * - Set the Read protection Level - * - Set the BOR level - * - Program the user Option Bytes - * - Launch the Option Bytes loader - * - * 4. Interrupts and flags management functions: this group - * includes all needed functions to: - * - Enable/Disable the FLASH interrupt sources - * - Get flags status - * - Clear flags - * - Get FLASH operation status - * - Wait for last FLASH operation - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_flash.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define SECTOR_MASK ((uint32_t)0xFFFFFF07) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** @defgroup FLASH_Group1 FLASH Interface configuration functions - * @brief FLASH Interface configuration functions - * - -@verbatim - =============================================================================== - FLASH Interface configuration functions - =============================================================================== - - This group includes the following functions: - - void FLASH_SetLatency(uint32_t FLASH_Latency) - To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 | - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 | - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120| - |***************|****************|****************|*****************|*****************|*****************************+ - | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V | - |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| - |Max Parallelism| x32 | x16 | x8 | x64 | - |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| - |PSIZE[1:0] | 10 | 01 | 00 | 11 | - +-------------------------------------------------------------------------------------------------------------------+ - - - void FLASH_PrefetchBufferCmd(FunctionalState NewState) - - void FLASH_InstructionCacheCmd(FunctionalState NewState) - - void FLASH_DataCacheCmd(FunctionalState NewState) - - void FLASH_InstructionCacheReset(void) - - void FLASH_DataCacheReset(void) - - The unlock sequence is not needed for these functions. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the code latency value. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @arg FLASH_Latency_2: FLASH Two Latency cycles - * @arg FLASH_Latency_3: FLASH Three Latency cycles - * @arg FLASH_Latency_4: FLASH Four Latency cycles - * @arg FLASH_Latency_5: FLASH Five Latency cycles - * @arg FLASH_Latency_6: FLASH Six Latency cycles - * @arg FLASH_Latency_7: FLASH Seven Latency cycles - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */ - *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency; -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @param NewState: new state of the Prefetch Buffer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_PrefetchBufferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Enable or disable the Prefetch Buffer */ - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_PRFTEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_PRFTEN); - } -} - -/** - * @brief Enables or disables the Instruction Cache feature. - * @param NewState: new state of the Instruction Cache. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_InstructionCacheCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_ICEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_ICEN); - } -} - -/** - * @brief Enables or disables the Data Cache feature. - * @param NewState: new state of the Data Cache. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_DataCacheCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_DCEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_DCEN); - } -} - -/** - * @brief Resets the Instruction Cache. - * @note This function must be used only when the Instruction Cache is disabled. - * @param None - * @retval None - */ -void FLASH_InstructionCacheReset(void) -{ - FLASH->ACR |= FLASH_ACR_ICRST; -} - -/** - * @brief Resets the Data Cache. - * @note This function must be used only when the Data Cache is disabled. - * @param None - * @retval None - */ -void FLASH_DataCacheReset(void) -{ - FLASH->ACR |= FLASH_ACR_DCRST; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group2 FLASH Memory Programming functions - * @brief FLASH Memory Programming functions - * -@verbatim - =============================================================================== - FLASH Memory Programming functions - =============================================================================== - - This group includes the following functions: - - void FLASH_Unlock(void) - - void FLASH_Lock(void) - - FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) - - FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) - - FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) - - FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) - - FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) - - FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) - - Any operation of erase or program should follow these steps: - 1. Call the FLASH_Unlock() function to enable the FLASH control register access - - 2. Call the desired function to erase sector(s) or program data - - 3. Call the FLASH_Lock() function to disable the FLASH control register access - (recommended to protect the FLASH memory against possible unwanted operation) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the FLASH control register access - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - if((FLASH->CR & FLASH_CR_LOCK) != RESET) - { - /* Authorize the FLASH Registers access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - } -} - -/** - * @brief Locks the FLASH control register access - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH Registers access */ - FLASH->CR |= FLASH_CR_LOCK; -} - -/** - * @brief Erases a specified FLASH Sector. - * - * @param FLASH_Sector: The Sector number to be erased. - * This parameter can be a value between FLASH_Sector_0 and FLASH_Sector_11 - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_SECTOR(FLASH_Sector)); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the sector */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR &= SECTOR_MASK; - FLASH->CR |= FLASH_CR_SER | FLASH_Sector; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the SER Bit */ - FLASH->CR &= (~FLASH_CR_SER); - FLASH->CR &= SECTOR_MASK; - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH Sectors. - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all sectors */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_CR_MER); - - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Programs a double word (64-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V and an External Vpp is present. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint64_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a word (32-bit) at a specified address. - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @note This function must be used when the device voltage range is from 2.7V to 3.6V. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint32_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word (16-bit) at a specified address. - * @note This function must be used when the device voltage range is from 2.1V to 3.6V. - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_HALF_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a byte (8-bit) at a specified address. - * @note This function can be used within all the device supply voltage ranges. - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_BYTE; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint8_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - - /* Return the Program Status */ - return status; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group3 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - =============================================================================== - Option Bytes Programming functions - =============================================================================== - - This group includes the following functions: - - void FLASH_OB_Unlock(void) - - void FLASH_OB_Lock(void) - - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) - - void FLASH_OB_RDPConfig(uint8_t OB_RDP) - - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) - - void FLASH_OB_BORConfig(uint8_t OB_BOR) - - FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) - - FLASH_Status FLASH_OB_Launch(void) - - uint32_t FLASH_OB_GetUser(void) - - uint8_t FLASH_OB_GetWRP(void) - - uint8_t FLASH_OB_GetRDP(void) - - uint8_t FLASH_OB_GetBOR(void) - - Any operation of erase or program should follow these steps: - 1. Call the FLASH_OB_Unlock() function to enable the FLASH option control register access - - 2. Call one or several functions to program the desired Option Bytes: - - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable - the desired sector write protection - - void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level - - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure - the user Option Bytes. - - void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level - - 3. Once all needed Option Bytes to be programmed are correctly written, call the - FLASH_OB_Launch() function to launch the Option Bytes programming process. - - @note When changing the IWDG mode from HW to SW or from SW to HW, a system - reset is needed to make the change effective. - - 4. Call the FLASH_OB_Lock() function to disable the FLASH option control register - access (recommended to protect the Option Bytes against possible unwanted operations) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the FLASH Option Control Registers access. - * @param None - * @retval None - */ -void FLASH_OB_Unlock(void) -{ - if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) - { - /* Authorizes the Option Byte register programming */ - FLASH->OPTKEYR = FLASH_OPT_KEY1; - FLASH->OPTKEYR = FLASH_OPT_KEY2; - } -} - -/** - * @brief Locks the FLASH Option Control Registers access. - * @param None - * @retval None - */ -void FLASH_OB_Lock(void) -{ - /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ - FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; -} - -/** - * @brief Enables or disables the write protection of the desired sectors - * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11 - * @arg OB_WRP_Sector_All - * @param Newstate: new state of the Write Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - if(NewState != DISABLE) - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP); - } - else - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP; - } - } -} - -/** - * @brief Sets the read protection level. - * @param OB_RDP: specifies the read protection level. - * This parameter can be one of the following values: - * @arg OB_RDP_Level_0: No protection - * @arg OB_RDP_Level_1: Read protection of the memory - * @arg OB_RDP_Level_2: Full chip protection - * - * !!!Warning!!! When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * - * @retval None - */ -void FLASH_OB_RDPConfig(uint8_t OB_RDP) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_RDP(OB_RDP)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP; - - } -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param OB_IWDG: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval None - */ -void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) -{ - uint8_t optiontmp = 0xFF; - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); - - /* Update User Option Byte */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); - } -} - -/** - * @brief Sets the BOR Level. - * @param OB_BOR: specifies the Option Bytes BOR Reset Level. - * This parameter can be one of the following values: - * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V - * @retval None - */ -void FLASH_OB_BORConfig(uint8_t OB_BOR) -{ - /* Check the parameters */ - assert_param(IS_OB_BOR(OB_BOR)); - - /* Set the BOR Level */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR; - -} - -/** - * @brief Launch the option byte loading. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_OB_Launch(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Set the OPTSTRT bit in OPTCR register */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - return status; -} - -/** - * @brief Returns the FLASH User Option Bytes values. - * @param None - * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return (uint8_t)(FLASH->OPTCR >> 5); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes value. - * @param None - * @retval The FLASH Write Protection Option Bytes value - */ -uint16_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH Read Protection level. - * @param None - * @retval FLASH ReadOut Protection Status: - * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set - * - RESET, when OB_RDP_Level_0 is set - */ -FlagStatus FLASH_OB_GetRDP(void) -{ - FlagStatus readstatus = RESET; - - if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0)) - { - readstatus = SET; - } - else - { - readstatus = RESET; - } - return readstatus; -} - -/** - * @brief Returns the FLASH BOR level. - * @param None - * @retval The FLASH BOR level: - * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V - */ -uint8_t FLASH_OB_GetBOR(void) -{ - /* Return the FLASH BOR level */ - return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C); -} - -/** - * @} - */ - -/** @defgroup FLASH_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FLASH interrupts. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_ERR: FLASH Error Interrupt - * @arg FLASH_IT_EOP: FLASH end of operation Interrupt - * @retval None - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag - * @arg FLASH_FLAG_BSY: FLASH Busy flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); - - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASH's pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag - * @retval None - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -} - -/** - * @brief Returns the FLASH Status. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_PROGRAM; - } - else - { - if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_OPERATION; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - } - /* Return the FLASH Status */ - return flashstatus; -} - -/** - * @brief Waits for a FLASH operation to complete. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastOperation(void) -{ - __IO FLASH_Status status = FLASH_COMPLETE; - - /* Check for the FLASH Status */ - status = FLASH_GetStatus(); - - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - while(status == FLASH_BUSY) - { - status = FLASH_GetStatus(); - } - /* Return the operation status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c deleted file mode 100644 index 788e627aa..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c +++ /dev/null @@ -1,982 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_fsmc.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the FSMC peripheral: - * - Interface with SRAM, PSRAM, NOR and OneNAND memories - * - Interface with NAND memories - * - Interface with 16-bit PC Card compatible memories - * - Interrupts and flags management - * - ****************************************************************************** - - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_fsmc.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FSMC - * @brief FSMC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* --------------------- FSMC registers bit mask ---------------------------- */ -/* FSMC BCRx Mask */ -#define BCR_MBKEN_SET ((uint32_t)0x00000001) -#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) -#define BCR_FACCEN_SET ((uint32_t)0x00000040) - -/* FSMC PCRx Mask */ -#define PCR_PBKEN_SET ((uint32_t)0x00000004) -#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) -#define PCR_ECCEN_SET ((uint32_t)0x00000040) -#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) -#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FSMC_Private_Functions - * @{ - */ - -/** @defgroup FSMC_Group1 NOR/SRAM Controller functions - * @brief NOR/SRAM Controller functions - * -@verbatim - =============================================================================== - NOR/SRAM Controller functions - =============================================================================== - - The following sequence should be followed to configure the FSMC to interface with - SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: - - 1. Enable the clock for the FSMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - 2. FSMC pins configuration - - Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - - Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - 3. Declare a FSMC_NORSRAMInitTypeDef structure, for example: - FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; - and fill the FSMC_NORSRAMInitStructure variable with the allowed values of - the structure member. - - 4. Initialize the NOR/SRAM Controller by calling the function - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - - 5. Then enable the NOR/SRAM Bank, for example: - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); - - 6. At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default - * reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @retval None - */ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - - /* FSMC_Bank1_NORSRAM1 */ - if(FSMC_Bank == FSMC_Bank1_NORSRAM1) - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; - } - /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ - else - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; - } - FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; - FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; -} - -/** - * @brief Initializes the FSMC NOR/SRAM Banks according to the specified - * parameters in the FSMC_NORSRAMInitStruct. - * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure - * that contains the configuration information for the FSMC NOR/SRAM - * specified Banks. - * @retval None - */ -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); - assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); - assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); - assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); - assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); - assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); - assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); - assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); - assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); - assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); - assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); - assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); - assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); - - /* Bank1 NOR/SRAM control register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | - FSMC_NORSRAMInitStruct->FSMC_MemoryType | - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | - FSMC_NORSRAMInitStruct->FSMC_WrapMode | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | - FSMC_NORSRAMInitStruct->FSMC_WriteOperation | - FSMC_NORSRAMInitStruct->FSMC_WaitSignal | - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | - FSMC_NORSRAMInitStruct->FSMC_WriteBurst; - if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) - { - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET; - } - /* Bank1 NOR/SRAM timing register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; - - - /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ - if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) - { - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; - } - else - { - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; - } -} - -/** - * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. - * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Reset NOR/SRAM Init structure parameters values */ - FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; - FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; - FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; -} - -/** - * @brief Enables or disables the specified NOR/SRAM Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET; - } - else - { - /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET; - } -} -/** - * @} - */ - -/** @defgroup FSMC_Group2 NAND Controller functions - * @brief NAND Controller functions - * -@verbatim - =============================================================================== - NAND Controller functions - =============================================================================== - - The following sequence should be followed to configure the FSMC to interface with - 8-bit or 16-bit NAND memory connected to the NAND Bank: - - 1. Enable the clock for the FSMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - 2. FSMC pins configuration - - Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - - Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - 3. Declare a FSMC_NANDInitTypeDef structure, for example: - FSMC_NANDInitTypeDef FSMC_NANDInitStructure; - and fill the FSMC_NANDInitStructure variable with the allowed values of - the structure member. - - 4. Initialize the NAND Controller by calling the function - FSMC_NANDInit(&FSMC_NANDInitStructure); - - 5. Then enable the NAND Bank, for example: - FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE); - - 6. At this stage you can read/write from/to the memory connected to the NAND Bank. - -@note To enable the Error Correction Code (ECC), you have to use the function - FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE); - and to get the current ECC value you have to use the function - ECCval = FSMC_GetECC(FSMC_Bank3_NAND); - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval None - */ -void FSMC_NANDDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Set the FSMC_Bank2 registers to their reset values */ - FSMC_Bank2->PCR2 = 0x00000018; - FSMC_Bank2->SR2 = 0x00000040; - FSMC_Bank2->PMEM2 = 0xFCFCFCFC; - FSMC_Bank2->PATT2 = 0xFCFCFCFC; - } - /* FSMC_Bank3_NAND */ - else - { - /* Set the FSMC_Bank3 registers to their reset values */ - FSMC_Bank3->PCR3 = 0x00000018; - FSMC_Bank3->SR3 = 0x00000040; - FSMC_Bank3->PMEM3 = 0xFCFCFCFC; - FSMC_Bank3->PATT3 = 0xFCFCFCFC; - } -} - -/** - * @brief Initializes the FSMC NAND Banks according to the specified parameters - * in the FSMC_NANDInitStruct. - * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that - * contains the configuration information for the FSMC NAND specified Banks. - * @retval None - */ -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - - /* Check the parameters */ - assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); - assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); - assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); - assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); - assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); - assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); - assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ - tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | - PCR_MEMORYTYPE_NAND | - FSMC_NANDInitStruct->FSMC_MemoryDataWidth | - FSMC_NANDInitStruct->FSMC_ECC | - FSMC_NANDInitStruct->FSMC_ECCPageSize | - (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| - (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); - - /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ - tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ - tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - /* FSMC_Bank2_NAND registers configuration */ - FSMC_Bank2->PCR2 = tmppcr; - FSMC_Bank2->PMEM2 = tmppmem; - FSMC_Bank2->PATT2 = tmppatt; - } - else - { - /* FSMC_Bank3_NAND registers configuration */ - FSMC_Bank3->PCR3 = tmppcr; - FSMC_Bank3->PMEM3 = tmppmem; - FSMC_Bank3->PATT3 = tmppatt; - } -} - - -/** - * @brief Fills each FSMC_NANDInitStruct member with its default value. - * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which - * will be initialized. - * @retval None - */ -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - /* Reset NAND Init structure parameters values */ - FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; - FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; - FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; - FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the specified NAND Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_PBKEN_SET; - } - else - { - FSMC_Bank3->PCR3 |= PCR_PBKEN_SET; - } - } - else - { - /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET; - } - else - { - FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET; - } - } -} -/** - * @brief Enables or disables the FSMC NAND ECC feature. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC NAND ECC feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_ECCEN_SET; - } - else - { - FSMC_Bank3->PCR3 |= PCR_ECCEN_SET; - } - } - else - { - /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET; - } - else - { - FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET; - } - } -} - -/** - * @brief Returns the error correction code register value. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval The Error Correction Code (ECC) value. - */ -uint32_t FSMC_GetECC(uint32_t FSMC_Bank) -{ - uint32_t eccval = 0x00000000; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Get the ECCR2 register value */ - eccval = FSMC_Bank2->ECCR2; - } - else - { - /* Get the ECCR3 register value */ - eccval = FSMC_Bank3->ECCR3; - } - /* Return the error correction code value */ - return(eccval); -} -/** - * @} - */ - -/** @defgroup FSMC_Group3 PCCARD Controller functions - * @brief PCCARD Controller functions - * -@verbatim - =============================================================================== - PCCARD Controller functions - =============================================================================== - - The following sequence should be followed to configure the FSMC to interface with - 16-bit PC Card compatible memory connected to the PCCARD Bank: - - 1. Enable the clock for the FSMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - 2. FSMC pins configuration - - Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - - Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - 3. Declare a FSMC_PCCARDInitTypeDef structure, for example: - FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure; - and fill the FSMC_PCCARDInitStructure variable with the allowed values of - the structure member. - - 4. Initialize the PCCARD Controller by calling the function - FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); - - 5. Then enable the PCCARD Bank: - FSMC_PCCARDCmd(ENABLE); - - 6. At this stage you can read/write from/to the memory connected to the PCCARD Bank. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. - * @param None - * @retval None - */ -void FSMC_PCCARDDeInit(void) -{ - /* Set the FSMC_Bank4 registers to their reset values */ - FSMC_Bank4->PCR4 = 0x00000018; - FSMC_Bank4->SR4 = 0x00000000; - FSMC_Bank4->PMEM4 = 0xFCFCFCFC; - FSMC_Bank4->PATT4 = 0xFCFCFCFC; - FSMC_Bank4->PIO4 = 0xFCFCFCFC; -} - -/** - * @brief Initializes the FSMC PCCARD Bank according to the specified parameters - * in the FSMC_PCCARDInitStruct. - * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure - * that contains the configuration information for the FSMC PCCARD Bank. - * @retval None - */ -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); - assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ - FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | - FSMC_MemoryDataWidth_16b | - (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | - (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); - - /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ - FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ - FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ - FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); -} - -/** - * @brief Fills each FSMC_PCCARDInitStruct member with its default value. - * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Reset PCCARD Init structure parameters values */ - FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the PCCARD Memory Bank. - * @param NewState: new state of the PCCARD Memory Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_PCCARDCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 |= PCR_PBKEN_SET; - } - else - { - /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET; - } -} -/** - * @} - */ - -/** @defgroup FSMC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FSMC interrupts. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @param NewState: new state of the specified FSMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) -{ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 |= FSMC_IT; - } - } - else - { - /* Disable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - - FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; - } - } -} - -/** - * @brief Checks whether the specified FSMC flag is set or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. - * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. - * @retval The new state of FSMC_FLAG (SET or RESET). - */ -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpsr = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - /* Get the flag status */ - if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the FSMC's pending flags. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. - * @retval None - */ -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~FSMC_FLAG; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~FSMC_FLAG; - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~FSMC_FLAG; - } -} - -/** - * @brief Checks whether the specified FSMC interrupt has occurred or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt source to check. - * This parameter can be one of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval The new state of FSMC_IT (SET or RESET). - */ -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - itstatus = tmpsr & FSMC_IT; - - itenable = tmpsr & (FSMC_IT >> 3); - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the FSMC's interrupt pending bits. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval None - */ -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c deleted file mode 100644 index c3a60439a..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c +++ /dev/null @@ -1,561 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_gpio.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the GPIO peripheral: - * - Initialization and Configuration - * - GPIO Read and Write - * - GPIO Alternate functions configuration - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable the GPIO AHB clock using the following function - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - * 2. Configure the GPIO pin(s) using GPIO_Init() - * Four possible configuration are available for each pin: - * - Input: Floating, Pull-up, Pull-down. - * - Output: Push-Pull (Pull-up, Pull-down or no Pull) - * Open Drain (Pull-up, Pull-down or no Pull). - * In output mode, the speed is configurable: 2 MHz, 25 MHz, - * 50 MHz or 100 MHz. - * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) - * Open Drain (Pull-up, Pull-down or no Pull). - * - Analog: required mode when a pin is to be used as ADC channel - * or DAC output. - * - * 3- Peripherals alternate function: - * - For ADC and DAC, configure the desired pin in analog mode using - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; - * - For other peripherals (TIM, USART...): - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function mode using - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() - * - * 5. To set/reset the level of a pin configured in output mode use - * GPIO_SetBits()/GPIO_ResetBits() - * - * 6. During and just after reset, the alternate functions are not - * active and the GPIO pins are configured in input floating mode - * (except JTAG pins). - * - * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as - * general-purpose (PC14 and PC15, respectively) when the LSE - * oscillator is off. The LSE has priority over the GPIO function. - * - * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as - * general-purpose PH0 and PH1, respectively, when the HSE - * oscillator is off. The HSE has priority over the GPIO function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_gpio.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** @defgroup GPIO_Group1 Initialization and Configuration - * @brief Initialization and Configuration - * -@verbatim - =============================================================================== - Initialization and Configuration - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the GPIOx peripheral registers to their default reset values. - * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if (GPIOx == GPIOA) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE); - } - else if (GPIOx == GPIOB) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE); - } - else if (GPIOx == GPIOC) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE); - } - else if (GPIOx == GPIOD) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE); - } - else if (GPIOx == GPIOE) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE); - } - else if (GPIOx == GPIOF) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE); - } - else if (GPIOx == GPIOG) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE); - } - else if (GPIOx == GPIOH) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); - } - else - { - if (GPIOx == GPIOI) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); - } - } -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); - - /* -------------------------Configure the port pins---------------- */ - /*-- GPIO Mode Configuration --*/ - for (pinpos = 0x00; pinpos < 0x10; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if (currentpin == pos) - { - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); - GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); - - if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) - { - /* Check Speed mode parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - - /* Speed mode configuration */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); - GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); - - /* Check Output mode parameters */ - assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); - - /* Output mode configuration*/ - GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; - GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); - } - - /* Pull-up Pull down resistor configuration*/ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); - GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); - } - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next reset. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be locked. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group2 GPIO Read and Write - * @brief GPIO Read and Write - * -@verbatim - =============================================================================== - GPIO Read and Write - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO input data port. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @retval GPIO input data port value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRL = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRH = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enum values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRRL = GPIO_Pin; - } - else - { - GPIOx->BSRRH = GPIO_Pin ; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param PortVal: specifies the value to be written to the port output data register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @brief Toggles the specified GPIO pins.. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: Specifies the pins to be toggled. - * @retval None - */ -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR ^= GPIO_Pin; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function - * @brief GPIO Alternate functions configuration function - * -@verbatim - =============================================================================== - GPIO Alternate functions configuration function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Changes the mapping of the specified pin. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_PinSource: specifies the pin for the Alternate function. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @param GPIO_AFSelection: selects the pin to used as Alternate function. - * This parameter can be one of the following values: - * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) - * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) - * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) - * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) - * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset) - * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1 - * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1 - * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2 - * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2 - * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2 - * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3 - * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3 - * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3 - * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3 - * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4 - * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4 - * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 - * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 - * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 - * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 - * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7 - * @arg GPIO_AF_USART1: Connect USART1 pins to AF7 - * @arg GPIO_AF_USART2: Connect USART2 pins to AF7 - * @arg GPIO_AF_USART3: Connect USART3 pins to AF7 - * @arg GPIO_AF_UART4: Connect UART4 pins to AF8 - * @arg GPIO_AF_UART5: Connect UART5 pins to AF8 - * @arg GPIO_AF_USART6: Connect USART6 pins to AF8 - * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 - * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 - * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 - * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9 - * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9 - * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 - * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 - * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 - * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 - * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 - * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 - * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 - * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 - * @retval None - */ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) -{ - uint32_t temp = 0x00; - uint32_t temp_2 = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - assert_param(IS_GPIO_AF(GPIO_AF)); - - temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; - GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c deleted file mode 100644 index 3d8df299a..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c +++ /dev/null @@ -1,700 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hash.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the HASH / HMAC Processor (HASH) peripheral: - * - Initialization and Configuration functions - * - Message Digest generation functions - * - context swapping functions - * - DMA interface function - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * HASH operation : - * ---------------- - * 1. Enable the HASH controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function. - * - * 2. Initialise the HASH using HASH_Init() function. - * - * 3 . Reset the HASH processor core, so that the HASH will be ready - * to compute he message digest of a new message by using - * HASH_Reset() function. - * - * 4. Enable the HASH controller using the HASH_Cmd() function. - * - * 5. if using DMA for Data input transfer, Activate the DMA Request - * using HASH_DMACmd() function - * - * 6. if DMA is not used for data transfer, use HASH_DataIn() function - * to enter data to IN FIFO. - * - * - * 7. Configure the Number of valid bits in last word of the message - * using HASH_SetLastWordValidBitsNbr() function. - * - * 8. if the message length is not an exact multiple of 512 bits, - * then the function HASH_StartDigest() must be called to - * launch the computation of the final digest. - * - * 9. Once computed, the digest can be read using HASH_GetDigest() - * function. - * - * 10. To control HASH events you can use one of the following - * two methods: - * a- Check on HASH flags using the HASH_GetFlagStatus() function. - * b- Use HASH interrupts through the function HASH_ITConfig() at - * initialization phase and HASH_GetITStatus() function into - * interrupt routines in hashing phase. - * After checking on a flag you should clear it using HASH_ClearFlag() - * function. And after checking on an interrupt event you should - * clear it using HASH_ClearITPendingBit() function. - * - * 11. Save and restore hash processor context using - * HASH_SaveContext() and HASH_RestoreContext() functions. - * - * - * - * HMAC operation : - * ---------------- - * The HMAC algorithm is used for message authentication, by - * irreversibly binding the message being processed to a key chosen - * by the user. - * For HMAC specifications, refer to "HMAC: keyed-hashing for message - * authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997" - * - * Basically, the HMAC algorithm consists of two nested hash operations: - * HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)] - * where: - * - "pad" is a sequence of zeroes needed to extend the key to the - * length of the underlying hash function data block (that is - * 512 bits for both the SHA-1 and MD5 hash algorithms) - * - "|" represents the concatenation operator - * - * - * To compute the HMAC, four different phases are required: - * - * 1. Initialise the HASH using HASH_Init() function to do HMAC - * operation. - * - * 2. The key (to be used for the inner hash function) is then given - * to the core. This operation follows the same mechanism as the - * one used to send the message in the hash operation (that is, - * by HASH_DataIn() function and, finally, - * HASH_StartDigest() function. - * - * 3. Once the last word has been entered and computation has started, - * the hash processor elaborates the key. It is then ready to - * accept the message text using the same mechanism as the one - * used to send the message in the hash operation. - * - * 4. After the first hash round, the hash processor returns "ready" - * to indicate that it is ready to receive the key to be used for - * the outer hash function (normally, this key is the same as the - * one used for the inner hash function). When the last word of - * the key is entered and computation starts, the HMAC result is - * made available using HASH_GetDigest() function. - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hash.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup HASH - * @brief HASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HASH_Private_Functions - * @{ - */ - -/** @defgroup HASH_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to - - Initialize the HASH peripheral - - Configure the HASH Processor - - MD5/SHA1, - - HASH/HMAC, - - datatype - - HMAC Key (if mode = HMAC) - - Reset the HASH Processor - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the HASH peripheral registers to their default reset values - * @param None - * @retval None - */ -void HASH_DeInit(void) -{ - /* Enable HASH reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE); - /* Release HASH from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE); -} - -/** - * @brief Initializes the HASH peripheral according to the specified parameters - * in the HASH_InitStruct structure. - * @note the hash processor is reset when calling this function so that the - * HASH will be ready to compute the message digest of a new message. - * There is no need to call HASH_Reset() function. - * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains - * the configuration information for the HASH peripheral. - * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only - * if the algorithm mode is HMAC. - * @retval None - */ -void HASH_Init(HASH_InitTypeDef* HASH_InitStruct) -{ - /* Check the parameters */ - assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection)); - assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType)); - assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode)); - - /* Configure the Algorithm used, algorithm mode and the datatype */ - HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE); - HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \ - HASH_InitStruct->HASH_DataType | \ - HASH_InitStruct->HASH_AlgoMode); - - /* if algorithm mode is HMAC, set the Key */ - if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC) - { - assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType)); - HASH->CR &= ~HASH_CR_LKEY; - HASH->CR |= HASH_InitStruct->HASH_HMACKeyType; - } - - /* Reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_CR_INIT; -} - -/** - * @brief Fills each HASH_InitStruct member with its default value. - * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will - * be initialized. - * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1, - * Data type selected is 32b and HMAC Key Type is short key. - * @retval None - */ -void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct) -{ - /* Initialize the HASH_AlgoSelection member */ - HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1; - - /* Initialize the HASH_AlgoMode member */ - HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH; - - /* Initialize the HASH_DataType member */ - HASH_InitStruct->HASH_DataType = HASH_DataType_32b; - - /* Initialize the HASH_HMACKeyType member */ - HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; -} - -/** - * @brief Resets the HASH processor core, so that the HASH will be ready - * to compute the message digest of a new message. - * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation - * completion interrupt status) bit corresponding to HASH_IT_DCI - * interrupt and HASH_FLAG_DCIS flag. - * @param None - * @retval None - */ -void HASH_Reset(void) -{ - /* Reset the HASH processor core */ - HASH->CR |= HASH_CR_INIT; -} -/** - * @} - */ - -/** @defgroup HASH_Group2 Message Digest generation functions - * @brief Message Digest generation functions - * -@verbatim - =============================================================================== - Message Digest generation functions - =============================================================================== - This section provides functions allowing the generation of message digest: - - Push data in the IN FIFO : using HASH_DataIn() - - Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr() - - set the last word valid bits number using HASH_SetLastWordValidBitsNbr() - - start digest calculation : using HASH_StartDigest() - - Get the Digest message : using HASH_GetDigest() - -@endverbatim - * @{ - */ - - -/** - * @brief Configure the Number of valid bits in last word of the message - * @param ValidNumber: Number of valid bits in last word of the message. - * This parameter must be a number between 0 and 0x1F. - * - 0x00: All 32 bits of the last data written are valid - * - 0x01: Only bit [0] of the last data written is valid - * - 0x02: Only bits[1:0] of the last data written are valid - * - 0x03: Only bits[2:0] of the last data written are valid - * - ... - * - 0x1F: Only bits[30:0] of the last data written are valid - * @note The Number of valid bits must be set before to start the message - * digest competition (in Hash and HMAC) and key treatment(in HMAC). - * @retval None - */ -void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber) -{ - /* Check the parameters */ - assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber)); - - /* Configure the Number of valid bits in last word of the message */ - HASH->STR &= ~(HASH_STR_NBW); - HASH->STR |= ValidNumber; -} - -/** - * @brief Writes data in the Data Input FIFO - * @param Data: new data of the message to be processed. - * @retval None - */ -void HASH_DataIn(uint32_t Data) -{ - /* Write in the DIN register a new data */ - HASH->DIN = Data; -} - -/** - * @brief Returns the number of words already pushed into the IN FIFO. - * @param None - * @retval The value of words already pushed into the IN FIFO. - */ -uint8_t HASH_GetInFIFOWordsNbr(void) -{ - /* Return the value of NBW bits */ - return ((HASH->CR & HASH_CR_NBW) >> 8); -} - -/** - * @brief Provides the message digest result. - * @note In MD5 mode, Data[4] filed of HASH_MsgDigest structure is not used - * and is read as zero. - * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will - * hold the message digest result - * @retval None - */ -void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest) -{ - /* Get the data field */ - HASH_MessageDigest->Data[0] = HASH->HR[0]; - HASH_MessageDigest->Data[1] = HASH->HR[1]; - HASH_MessageDigest->Data[2] = HASH->HR[2]; - HASH_MessageDigest->Data[3] = HASH->HR[3]; - HASH_MessageDigest->Data[4] = HASH->HR[4]; -} - -/** - * @brief Starts the message padding and calculation of the final message - * @param None - * @retval None - */ -void HASH_StartDigest(void) -{ - /* Start the Digest calculation */ - HASH->STR |= HASH_STR_DCAL; -} -/** - * @} - */ - -/** @defgroup HASH_Group3 Context swapping functions - * @brief Context swapping functions - * -@verbatim - =============================================================================== - Context swapping functions - =============================================================================== - - This section provides functions allowing to save and store HASH Context - - It is possible to interrupt a HASH/HMAC process to perform another processing - with a higher priority, and to complete the interrupted process later on, when - the higher priority task is complete. To do so, the context of the interrupted - task must be saved from the HASH registers to memory, and then be restored - from memory to the HASH registers. - - 1. To save the current context, use HASH_SaveContext() function - 2. To restore the saved context, use HASH_RestoreContext() function - - -@endverbatim - * @{ - */ - -/** - * @brief Save the Hash peripheral Context. - * @note The context can be saved only when no block is currently being - * processed. So user must wait for DINIS = 1 (the last block has been - * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not - * full and no processing is ongoing). - * @param HASH_ContextSave: pointer to a HASH_Context structure that contains - * the repository for current context. - * @retval None - */ -void HASH_SaveContext(HASH_Context* HASH_ContextSave) -{ - uint8_t i = 0; - - /* save context registers */ - HASH_ContextSave->HASH_IMR = HASH->IMR; - HASH_ContextSave->HASH_STR = HASH->STR; - HASH_ContextSave->HASH_CR = HASH->CR; - for(i=0; i<=50;i++) - { - HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i]; - } -} - -/** - * @brief Restore the Hash peripheral Context. - * @note After calling this function, user can restart the processing from the - * point where it has been interrupted. - * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains - * the repository for saved context. - * @retval None - */ -void HASH_RestoreContext(HASH_Context* HASH_ContextRestore) -{ - uint8_t i = 0; - - /* restore context registers */ - HASH->IMR = HASH_ContextRestore->HASH_IMR; - HASH->STR = HASH_ContextRestore->HASH_STR; - HASH->CR = HASH_ContextRestore->HASH_CR; - - /* Initialize the hash processor */ - HASH->CR |= HASH_CR_INIT; - - /* continue restoring context registers */ - for(i=0; i<=50;i++) - { - HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i]; - } -} -/** - * @} - */ - -/** @defgroup HASH_Group4 HASH's DMA interface Configuration function - * @brief HASH's DMA interface Configuration function - * -@verbatim - =============================================================================== - HASH's DMA interface Configuration function - =============================================================================== - - This section provides functions allowing to configure the DMA interface for - HASH/ HMAC data input transfer. - - When the DMA mode is enabled (using the HASH_DMACmd() function), data can be - sent to the IN FIFO using the DMA peripheral. - - - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the HASH DMA interface. - * @note The DMA is disabled by hardware after the end of transfer. - * @param NewState: new state of the selected HASH DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void HASH_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the HASH DMA request */ - HASH->CR |= HASH_CR_DMAE; - } - else - { - /* Disable the HASH DMA request */ - HASH->CR &= ~HASH_CR_DMAE; - } -} -/** - * @} - */ - -/** @defgroup HASH_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the HASH Interrupts and - to get the status and clear flags and Interrupts pending bits. - - The HASH provides 2 Interrupts sources and 5 Flags: - - Flags : - ---------- - 1. HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO - which means that a new block (512 bit) can be entered - into the input buffer. - - 2. HASH_FLAG_DCIS : set when Digest calculation is complete - - 3. HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or - a transfer is ongoing. - This Flag is cleared only by hardware. - - 4. HASH_FLAG_BUSY : set when The hash core is processing a block of data - This Flag is cleared only by hardware. - - 5. HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that - the Data IN FIFO contains at least one word of data. - This Flag is cleared only by hardware. - - Interrupts : - ------------ - - 1. HASH_IT_DINI : if enabled, this interrupt source is pending when 16 - locations are free in the Data IN FIFO which means that - a new block (512 bit) can be entered into the input buffer. - This interrupt source is cleared using - HASH_ClearITPendingBit(HASH_IT_DINI) function. - - 2. HASH_IT_DCI : if enabled, this interrupt source is pending when Digest - calculation is complete. - This interrupt source is cleared using - HASH_ClearITPendingBit(HASH_IT_DCI) function. - - Managing the HASH controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the HASH controller events: Polling mode or Interrupt mode. - - 1. In the Polling Mode it is advised to use the following functions: - - HASH_GetFlagStatus() : to check if flags events occur. - - HASH_ClearFlag() : to clear the flags events. - - 2. In the Interrupt Mode it is advised to use the following functions: - - HASH_ITConfig() : to enable or disable the interrupt source. - - HASH_GetITStatus() : to check if Interrupt occurs. - - HASH_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified HASH interrupts. - * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg HASH_IT_DINI: Data Input interrupt - * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt - * @param NewState: new state of the specified HASH interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_HASH_IT(HASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected HASH interrupt */ - HASH->IMR |= HASH_IT; - } - else - { - /* Disable the selected HASH interrupt */ - HASH->IMR &= (uint8_t) ~HASH_IT; - } -} - -/** - * @brief Checks whether the specified HASH flag is set or not. - * @param HASH_FLAG: specifies the HASH flag to check. - * This parameter can be one of the following values: - * @arg HASH_FLAG_DINIS: Data input interrupt status flag - * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag - * @arg HASH_FLAG_BUSY: Busy flag - * @arg HASH_FLAG_DMAS: DMAS Status flag - * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag - * @retval The new state of HASH_FLAG (SET or RESET) - */ -FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tempreg = 0; - - /* Check the parameters */ - assert_param(IS_HASH_GET_FLAG(HASH_FLAG)); - - /* check if the FLAG is in CR register */ - if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint16_t)RESET ) - { - tempreg = HASH->CR; - } - else /* The FLAG is in SR register */ - { - tempreg = HASH->SR; - } - - /* Check the status of the specified HASH flag */ - if ((tempreg & HASH_FLAG) != (uint16_t)RESET) - { - /* HASH is set */ - bitstatus = SET; - } - else - { - /* HASH_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the HASH_FLAG status */ - return bitstatus; -} -/** - * @brief Clears the HASH flags. - * @param HASH_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg HASH_FLAG_DINIS: Data Input Flag - * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag - * @retval None - */ -void HASH_ClearFlag(uint16_t HASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG)); - - /* Clear the selected HASH flags */ - HASH->SR = ~(uint32_t)HASH_FLAG; -} -/** - * @brief Checks whether the specified HASH interrupt has occurred or not. - * @param HASH_IT: specifies the HASH interrupt source to check. - * This parameter can be one of the following values: - * @arg HASH_IT_DINI: Data Input interrupt - * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt - * @retval The new state of HASH_IT (SET or RESET). - */ -ITStatus HASH_GetITStatus(uint8_t HASH_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_HASH_GET_IT(HASH_IT)); - - - /* Check the status of the specified HASH interrupt */ - tmpreg = HASH->SR; - - if (((HASH->IMR & tmpreg) & HASH_IT) != RESET) - { - /* HASH_IT is set */ - bitstatus = SET; - } - else - { - /* HASH_IT is reset */ - bitstatus = RESET; - } - /* Return the HASH_IT status */ - return bitstatus; -} - -/** - * @brief Clears the HASH interrupt pending bit(s). - * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear. - * This parameter can be any combination of the following values: - * @arg HASH_IT_DINI: Data Input interrupt - * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt - * @retval None - */ -void HASH_ClearITPendingBit(uint8_t HASH_IT) -{ - /* Check the parameters */ - assert_param(IS_HASH_IT(HASH_IT)); - - /* Clear the selected HASH interrupt pending bit */ - HASH->SR = (uint8_t)~HASH_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c deleted file mode 100644 index 2a61fafd5..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c +++ /dev/null @@ -1,314 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hash_md5.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides high level functions to compute the HASH MD5 and - * HMAC MD5 Digest of an input message. - * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH - * peripheral. - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The HASH controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function. - * - * 2. Calculate the HASH MD5 Digest using HASH_MD5() function. - * - * 3. Calculate the HMAC MD5 Digest using HMAC_MD5() function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hash.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup HASH - * @brief HASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HASH_Private_Functions - * @{ - */ - -/** @defgroup HASH_Group7 High Level MD5 functions - * @brief High Level MD5 Hash and HMAC functions - * -@verbatim - =============================================================================== - High Level MD5 Hash and HMAC functions - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Compute the HASH MD5 digest. - * @param Input: pointer to the Input buffer to be treated. - * @param Ilen: length of the Input buffer. - * @param Output: the returned digest - * @retval An ErrorStatus enumeration value: - * - SUCCESS: digest computation done - * - ERROR: digest computation failed - */ -ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]) -{ - HASH_InitTypeDef MD5_HASH_InitStructure; - HASH_MsgDigest MD5_MessageDigest; - __IO uint16_t nbvalidbitsdata = 0; - uint32_t i = 0; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - - - /* Number of valid bits in last word of the Input data */ - nbvalidbitsdata = 8 * (Ilen % 4); - - /* HASH peripheral initialization */ - HASH_DeInit(); - - /* HASH Configuration */ - MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5; - MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; - MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; - HASH_Init(&MD5_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the data */ - HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); - - /* Write the Input block in the IN FIFO */ - for(i=0; i 64) - { - /* HMAC long Key */ - MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; - } - else - { - /* HMAC short Key */ - MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; - } - HASH_Init(&MD5_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the Key */ - HASH_SetLastWordValidBitsNbr(nbvalidbitskey); - - /* Write the Key */ - for(i=0; i
© COPYRIGHT 2011 STMicroelectronics
- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hash.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup HASH - * @brief HASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HASH_Private_Functions - * @{ - */ - -/** @defgroup HASH_Group6 High Level SHA1 functions - * @brief High Level SHA1 Hash and HMAC functions - * -@verbatim - =============================================================================== - High Level SHA1 Hash and HMAC functions - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Compute the HASH SHA1 digest. - * @param Input: pointer to the Input buffer to be treated. - * @param Ilen: length of the Input buffer. - * @param Output: the returned digest - * @retval An ErrorStatus enumeration value: - * - SUCCESS: digest computation done - * - ERROR: digest computation failed - */ -ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]) -{ - HASH_InitTypeDef SHA1_HASH_InitStructure; - HASH_MsgDigest SHA1_MessageDigest; - __IO uint16_t nbvalidbitsdata = 0; - uint32_t i = 0; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - - /* Number of valid bits in last word of the Input data */ - nbvalidbitsdata = 8 * (Ilen % 4); - - /* HASH peripheral initialization */ - HASH_DeInit(); - - /* HASH Configuration */ - SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1; - SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; - SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; - HASH_Init(&SHA1_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the data */ - HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); - - /* Write the Input block in the IN FIFO */ - for(i=0; i 64) - { - /* HMAC long Key */ - SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; - } - else - { - /* HMAC short Key */ - SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; - } - HASH_Init(&SHA1_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the Key */ - HASH_SetLastWordValidBitsNbr(nbvalidbitskey); - - /* Write the Key */ - for(i=0; iGPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * Recommended configuration is Push-Pull, Pull-up, Open-Drain. - * Add an external pull up if necessary (typically 4.7 KOhm). - * - * 4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged - * Address using the I2C_Init() function. - * - * 5. Optionally you can enable/configure the following parameters without - * re-initialization (i.e there is no need to call again I2C_Init() function): - * - Enable the acknowledge feature using I2C_AcknowledgeConfig() function - * - Enable the dual addressing mode using I2C_DualAddressCmd() function - * - Enable the general call using the I2C_GeneralCallCmd() function - * - Enable the clock stretching using I2C_StretchClockCmd() function - * - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig() - * function. - * - Configure the NACK position for Master Receiver mode in case of - * 2 bytes reception using the function I2C_NACKPositionConfig(). - * - Enable the PEC Calculation using I2C_CalculatePEC() function - * - For SMBus Mode: - * - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function - * - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function - * - * 6. Enable the NVIC and the corresponding interrupt using the function - * I2C_ITConfig() if you need to use interrupt mode. - * - * 7. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using I2C_DMACmd() or - * I2C_DMALastTransferCmd() function. - * @note When using DMA mode, I2C interrupts may be used at the same time to - * control the communication flow (Start/Stop/Ack... events and errors). - * - * 8. Enable the I2C using the I2C_Cmd() function. - * - * 9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the - * transfers. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_i2c.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed)); - assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); - assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); - assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); - assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); - -/*---------------------------- I2Cx CR2 Configuration ------------------------*/ - /* Get the I2Cx CR2 value */ - tmpreg = I2Cx->CR2; - /* Clear frequency FREQ[5:0] bits */ - tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ); - /* Get pclk1 frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - /* Set frequency bits depending on pclk1 value */ - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - /* Write to I2Cx CR2 */ - I2Cx->CR2 = tmpreg; - -/*---------------------------- I2Cx CCR Configuration ------------------------*/ - /* Disable the selected I2C peripheral to configure TRISE */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); - /* Reset tmpreg value */ - /* Clear F/S, DUTY and CCR[11:0] bits */ - tmpreg = 0; - - /* Configure speed in standard mode */ - if (I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - /* Standard mode speed calculate */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - /* Test if CCR value is under 0x4*/ - if (result < 0x04) - { - /* Set minimum allowed value */ - result = 0x04; - } - /* Set speed value for standard mode */ - tmpreg |= result; - /* Set Maximum Rise Time for standard mode */ - I2Cx->TRISE = freqrange + 1; - } - /* Configure speed in fast mode */ - /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral - input clock) must be a multiple of 10 MHz */ - else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ - { - if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - /* Fast mode speed calculate: Tlow/Thigh = 2 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ - { - /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - /* Set DUTY bit */ - result |= I2C_DutyCycle_16_9; - } - - /* Test if CCR value is under 0x1*/ - if ((result & I2C_CCR_CCR) == 0) - { - /* Set minimum allowed value */ - result |= (uint16_t)0x0001; - } - /* Set speed value and set F/S bit for fast mode */ - tmpreg |= (uint16_t)(result | I2C_CCR_FS); - /* Set Maximum Rise Time for fast mode */ - I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - /* Write to I2Cx CCR */ - I2Cx->CCR = tmpreg; - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - -/*---------------------------- I2Cx CR1 Configuration ------------------------*/ - /* Get the I2Cx CR1 value */ - tmpreg = I2Cx->CR1; - /* Clear ACK, SMBTYPE and SMBUS bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure I2Cx: mode and acknowledgement */ - /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ - /* Set ACK bit according to I2C_Ack value */ - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - /* Write to I2Cx CR1 */ - I2Cx->CR1 = tmpreg; - -/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ - /* Set I2Cx Own Address1 and acknowledged address */ - I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ -/*---------------- Reset I2C init structure parameters values ----------------*/ - /* initialize the I2C_ClockSpeed member */ - I2C_InitStruct->I2C_ClockSpeed = 5000; - /* Initialize the I2C_Mode member */ - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - /* Initialize the I2C_DutyCycle member */ - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStruct->I2C_OwnAddress1 = 0; - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - /* Initialize the I2C_AcknowledgedAddress member */ - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/** - * @brief Enables or disables the specified I2C peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - } - else - { - /* Disable the selected I2C peripheral */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); - } -} - -/** - * @brief Generates I2Cx communication START condition. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a START condition */ - I2Cx->CR1 |= I2C_CR1_START; - } - else - { - /* Disable the START condition generation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START); - } -} - -/** - * @brief Generates I2Cx communication STOP condition. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a STOP condition */ - I2Cx->CR1 |= I2C_CR1_STOP; - } - else - { - /* Disable the STOP condition generation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP); - } -} - -/** - * @brief Transmits the address byte to select the slave device. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Address: specifies the slave address which will be transmitted - * @param I2C_Direction: specifies whether the I2C device will be a Transmitter - * or a Receiver. - * This parameter can be one of the following values - * @arg I2C_Direction_Transmitter: Transmitter mode - * @arg I2C_Direction_Receiver: Receiver mode - * @retval None. - */ -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction != I2C_Direction_Transmitter) - { - /* Set the address bit0 for read */ - Address |= I2C_OAR1_ADD0; - } - else - { - /* Reset the address bit0 for write */ - Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0); - } - /* Send the address */ - I2Cx->DR = Address; -} - -/** - * @brief Enables or disables the specified I2C acknowledge feature. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C Acknowledgement. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the acknowledgement */ - I2Cx->CR1 |= I2C_CR1_ACK; - } - else - { - /* Disable the acknowledgement */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK); - } -} - -/** - * @brief Configures the specified I2C own address2. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Address: specifies the 7bit I2C own address2. - * @retval None. - */ -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Get the old register value */ - tmpreg = I2Cx->OAR2; - - /* Reset I2Cx Own address2 bit [7:1] */ - tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2); - - /* Set I2Cx Own address2 */ - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - - /* Store the new register value */ - I2Cx->OAR2 = tmpreg; -} - -/** - * @brief Enables or disables the specified I2C dual addressing mode. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C dual addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable dual addressing mode */ - I2Cx->OAR2 |= I2C_OAR2_ENDUAL; - } - else - { - /* Disable dual addressing mode */ - I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL); - } -} - -/** - * @brief Enables or disables the specified I2C general call feature. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C General call. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable generall call */ - I2Cx->CR1 |= I2C_CR1_ENGC; - } - else - { - /* Disable generall call */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC); - } -} - -/** - * @brief Enables or disables the specified I2C software reset. - * @note When software reset is enabled, the I2C IOs are released (this can - * be useful to recover from bus errors). - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C software reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Peripheral under reset */ - I2Cx->CR1 |= I2C_CR1_SWRST; - } - else - { - /* Peripheral not under reset */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST); - } -} - -/** - * @brief Enables or disables the specified I2C Clock stretching. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState == DISABLE) - { - /* Enable the selected I2C Clock stretching */ - I2Cx->CR1 |= I2C_CR1_NOSTRETCH; - } - else - { - /* Disable the selected I2C Clock stretching */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH); - } -} - -/** - * @brief Selects the specified I2C fast mode duty cycle. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_DutyCycle: specifies the fast mode duty cycle. - * This parameter can be one of the following values: - * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 - * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 - * @retval None - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); - if (I2C_DutyCycle != I2C_DutyCycle_16_9) - { - /* I2C fast mode Tlow/Thigh=2 */ - I2Cx->CCR &= I2C_DutyCycle_2; - } - else - { - /* I2C fast mode Tlow/Thigh=16/9 */ - I2Cx->CCR |= I2C_DutyCycle_16_9; - } -} - -/** - * @brief Selects the specified I2C NACK position in master receiver mode. - * @note This function is useful in I2C Master Receiver mode when the number - * of data to be received is equal to 2. In this case, this function - * should be called (with parameter I2C_NACKPosition_Next) before data - * reception starts,as described in the 2-byte reception procedure - * recommended in Reference Manual in Section: Master receiver. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_NACKPosition: specifies the NACK position. - * This parameter can be one of the following values: - * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last - * received byte. - * @arg I2C_NACKPosition_Current: indicates that current byte is the last - * received byte. - * - * @note This function configures the same bit (POS) as I2C_PECPositionConfig() - * but is intended to be used in I2C mode while I2C_PECPositionConfig() - * is intended to used in SMBUS mode. - * - * @retval None - */ -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); - - /* Check the input parameter */ - if (I2C_NACKPosition == I2C_NACKPosition_Next) - { - /* Next byte in shift register is the last received byte */ - I2Cx->CR1 |= I2C_NACKPosition_Next; - } - else - { - /* Current byte in shift register is the last received byte */ - I2Cx->CR1 &= I2C_NACKPosition_Current; - } -} - -/** - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_SMBusAlert: specifies SMBAlert pin level. - * This parameter can be one of the following values: - * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low - * @arg I2C_SMBusAlert_High: SMBAlert pin driven high - * @retval None - */ -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); - if (I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - /* Drive the SMBusAlert pin Low */ - I2Cx->CR1 |= I2C_SMBusAlert_Low; - } - else - { - /* Drive the SMBusAlert pin High */ - I2Cx->CR1 &= I2C_SMBusAlert_High; - } -} - -/** - * @brief Enables or disables the specified I2C ARP. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx ARP. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C ARP */ - I2Cx->CR1 |= I2C_CR1_ENARP; - } - else - { - /* Disable the selected I2C ARP */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP); - } -} -/** - * @} - */ - -/** @defgroup I2C_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - Data transfers functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Sends a data byte through the I2Cx peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Data: Byte to be transmitted.. - * @retval None - */ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Write in the DR register the data to be sent */ - I2Cx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the I2Cx peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the data in the DR register */ - return (uint8_t)I2Cx->DR; -} - -/** - * @} - */ - -/** @defgroup I2C_Group3 PEC management functions - * @brief PEC management functions - * -@verbatim - =============================================================================== - PEC management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified I2C PEC transfer. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C PEC transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC transmission */ - I2Cx->CR1 |= I2C_CR1_PEC; - } - else - { - /* Disable the selected I2C PEC transmission */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC); - } -} - -/** - * @brief Selects the specified I2C PEC position. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_PECPosition: specifies the PEC position. - * This parameter can be one of the following values: - * @arg I2C_PECPosition_Next: indicates that the next byte is PEC - * @arg I2C_PECPosition_Current: indicates that current byte is PEC - * - * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() - * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() - * is intended to used in I2C mode. - * - * @retval None - */ -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); - if (I2C_PECPosition == I2C_PECPosition_Next) - { - /* Next byte in shift register is PEC */ - I2Cx->CR1 |= I2C_PECPosition_Next; - } - else - { - /* Current byte in shift register is PEC */ - I2Cx->CR1 &= I2C_PECPosition_Current; - } -} - -/** - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC calculation */ - I2Cx->CR1 |= I2C_CR1_ENPEC; - } - else - { - /* Disable the selected I2C PEC calculation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC); - } -} - -/** - * @brief Returns the PEC value for the specified I2C. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @retval The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the selected I2C PEC value */ - return ((I2Cx->SR2) >> 8); -} - -/** - * @} - */ - -/** @defgroup I2C_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - This section provides functions allowing to configure the I2C DMA channels - requests. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified I2C DMA requests. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C DMA requests */ - I2Cx->CR2 |= I2C_CR2_DMAEN; - } - else - { - /* Disable the selected I2C DMA requests */ - I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN); - } -} - -/** - * @brief Specifies that the next DMA transfer is the last one. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Next DMA transfer is the last transfer */ - I2Cx->CR2 |= I2C_CR2_LAST; - } - else - { - /* Next DMA transfer is not the last transfer */ - I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST); - } -} - -/** - * @} - */ - -/** @defgroup I2C_Group5 Interrupts events and flags management functions - * @brief Interrupts, events and flags management functions - * -@verbatim - =============================================================================== - Interrupts, events and flags management functions - =============================================================================== - This section provides functions allowing to configure the I2C Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - =============================================================================== - I2C State Monitoring Functions - =============================================================================== - This I2C driver provides three different ways for I2C state monitoring - depending on the application requirements and constraints: - - - 1. Basic state monitoring (Using I2C_CheckEvent() function) - ----------------------------------------------------------- - It compares the status registers (SR1 and SR2) content to a given event - (can be the combination of one or more flags). - It returns SUCCESS if the current status includes the given flags - and returns ERROR if one or more flags are missing in the current status. - - - When to use - - This function is suitable for most applications as well as for startup - activity since the events are fully described in the product reference - manual (RM0090). - - It is also suitable for users who need to define their own events. - - - Limitations - - If an error occurs (ie. error flags are set besides to the monitored - flags), the I2C_CheckEvent() function may return SUCCESS despite - the communication hold or corrupted real state. - In this case, it is advised to use error interrupts to monitor - the error events and handle them in the interrupt IRQ handler. - - @note - For error management, it is advised to use the following functions: - - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - Where x is the peripheral instance (I2C1, I2C2 ...) - - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the - I2Cx_ER_IRQHandler() function in order to determine which error occurred. - - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - and/or I2C_GenerateStop() in order to clear the error flag and source - and return to correct communication status. - - - 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) - -------------------------------------------------------------------- - Using the function I2C_GetLastEvent() which returns the image of both status - registers in a single word (uint32_t) (Status Register 2 value is shifted left - by 16 bits and concatenated to Status Register 1). - - - When to use - - This function is suitable for the same applications above but it - allows to overcome the mentioned limitation of I2C_GetFlagStatus() - function. - - The returned value could be compared to events already defined in - the library (stm32f4xx_i2c.h) or to custom values defined by user. - This function is suitable when multiple flags are monitored at the - same time. - - At the opposite of I2C_CheckEvent() function, this function allows - user to choose when an event is accepted (when all events flags are - set and no other flags are set or just when the needed flags are set - like I2C_CheckEvent() function. - - - Limitations - - User may need to define his own events. - - Same remark concerning the error management is applicable for this - function if user decides to check only regular communication flags - (and ignores error flags). - - - 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) - ----------------------------------------------------------------------- - - Using the function I2C_GetFlagStatus() which simply returns the status of - one single flag (ie. I2C_FLAG_RXNE ...). - - - When to use - - This function could be used for specific applications or in debug - phase. - - It is suitable when only one flag checking is needed (most I2C - events are monitored through multiple flags). - - Limitations: - - When calling this function, the Status register is accessed. - Some flags are cleared when the status register is accessed. - So checking the status of one Flag, may clear other ones. - - Function may need to be called twice or more in order to monitor - one single event. - - For detailed description of Events, please refer to section I2C_Events in - stm32f4xx_i2c.h file. - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified I2C register and returns its value. - * @param I2C_Register: specifies the register to read. - * This parameter can be one of the following values: - * @arg I2C_Register_CR1: CR1 register. - * @arg I2C_Register_CR2: CR2 register. - * @arg I2C_Register_OAR1: OAR1 register. - * @arg I2C_Register_OAR2: OAR2 register. - * @arg I2C_Register_DR: DR register. - * @arg I2C_Register_SR1: SR1 register. - * @arg I2C_Register_SR2: SR2 register. - * @arg I2C_Register_CCR: CCR register. - * @arg I2C_Register_TRISE: TRISE register. - * @retval The value of the read register. - */ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_REGISTER(I2C_Register)); - - tmp = (uint32_t) I2Cx; - tmp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Enables or disables the specified I2C interrupts. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_IT_BUF: Buffer interrupt mask - * @arg I2C_IT_EVT: Event interrupt mask - * @arg I2C_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_CONFIG_IT(I2C_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupts */ - I2Cx->CR2 |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupts */ - I2Cx->CR2 &= (uint16_t)~I2C_IT; - } -} - -/* - =============================================================================== - 1. Basic state monitoring - =============================================================================== - */ - -/** - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_EVENT: specifies the event to be checked. - * This parameter can be one of the following values: - * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2 - * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3 - * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2 - * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4 - * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5 - * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6 - * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6 - * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2 - * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9 - * - * @note For detailed description of Events, please refer to section I2C_Events - * in stm32f4xx_i2c.h file. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Last event is equal to the I2C_EVENT - * - ERROR: Last event is different from the I2C_EVENT - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_EVENT(I2C_EVENT)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_MASK; - - /* Check whether the last event contains the I2C_EVENT */ - if ((lastevent & I2C_EVENT) == I2C_EVENT) - { - /* SUCCESS: last event is equal to I2C_EVENT */ - status = SUCCESS; - } - else - { - /* ERROR: last event is different from I2C_EVENT */ - status = ERROR; - } - /* Return status */ - return status; -} - -/* - =============================================================================== - 2. Advanced state monitoring - =============================================================================== - */ - -/** - * @brief Returns the last I2Cx Event. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * - * @note For detailed description of Events, please refer to section I2C_Events - * in stm32f4xx_i2c.h file. - * - * @retval The last event - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_MASK; - - /* Return status */ - return lastevent; -} - -/* - =============================================================================== - 3. Flag-based state monitoring - =============================================================================== - */ - -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) - * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) - * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) - * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) - * @arg I2C_FLAG_TRA: Transmitter/Receiver flag - * @arg I2C_FLAG_BUSY: Bus busy flag - * @arg I2C_FLAG_MSL: Master/Slave flag - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) - * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag - * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) - * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDAD" - * @arg I2C_FLAG_SB: Start bit flag (Master mode) - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - /* Get the I2Cx peripheral base address */ - i2cxbase = (uint32_t)I2Cx; - - /* Read flag register index */ - i2creg = I2C_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - I2C_FLAG &= FLAG_MASK; - - if(i2creg != 0) - { - /* Get the I2Cx SR1 register address */ - i2cxbase += 0x14; - } - else - { - /* Flag in I2Cx SR2 Register */ - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - /* Get the I2Cx SR2 register address */ - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - /* I2C_FLAG is set */ - bitstatus = SET; - } - else - { - /* I2C_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the I2C_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's pending flags. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * - * @note STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * @note ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DR register. - * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * @note ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR - * register (I2C_SendData()). - * - * @retval None - */ -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); - /* Get the I2C flag position */ - flagpos = I2C_FLAG & FLAG_MASK; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @brief Checks whether the specified I2C interrupt has occurred or not. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert flag - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_IT_PECERR: PEC error in reception flag - * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure flag - * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_IT_BERR: Bus error flag - * @arg I2C_IT_TXE: Data register empty flag (Transmitter) - * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag - * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) - * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_IT_BTF: Byte transfer finished flag - * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDAD" - * @arg I2C_IT_SB: Start bit flag (Master mode) - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_IT(I2C_IT)); - - /* Check if the interrupt source is enabled or not */ - enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ; - - /* Get bit[23:0] of the flag */ - I2C_IT &= FLAG_MASK; - - /* Check the status of the specified I2C flag */ - if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - /* I2C_IT is set */ - bitstatus = SET; - } - else - { - /* I2C_IT is reset */ - bitstatus = RESET; - } - /* Return the I2C_IT status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's interrupt pending bits. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert interrupt - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt - * @arg I2C_IT_PECERR: PEC error in reception interrupt - * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure interrupt - * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) - * @arg I2C_IT_BERR: Bus error interrupt - * - * @note STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * @note ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DR register. - * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * @note ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * @note SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DR register (I2C_SendData()). - * @retval None - */ -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_IT(I2C_IT)); - - /* Get the I2C flag position */ - flagpos = I2C_IT & FLAG_MASK; - - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c deleted file mode 100644 index 30c9658c1..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c +++ /dev/null @@ -1,263 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_iwdg.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the Independent watchdog (IWDG) peripheral: - * - Prescaler and Counter configuration - * - IWDG activation - * - Flag management - * - * @verbatim - * - * =================================================================== - * IWDG features - * =================================================================== - * - * The IWDG can be started by either software or hardware (configurable - * through option byte). - * - * The IWDG is clocked by its own dedicated low-speed clock (LSI) and - * thus stays active even if the main clock fails. - * Once the IWDG is started, the LSI is forced ON and cannot be disabled - * (LSI cannot be disabled too), and the counter starts counting down from - * the reset value of 0xFFF. When it reaches the end of count value (0x000) - * a system reset is generated. - * The IWDG counter should be reloaded at regular intervals to prevent - * an MCU reset. - * - * The IWDG is implemented in the VDD voltage domain that is still functional - * in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). - * - * IWDGRST flag in RCC_CSR register can be used to inform when a IWDG - * reset occurs. - * - * Min-max timeout value @32KHz (LSI): ~125us / ~32.7s - * The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx - * devices provide the capability to measure the LSI frequency (LSI clock - * connected internally to TIM5 CH4 input capture). The measured value - * can be used to have an IWDG timeout with an acceptable accuracy. - * For more information, please refer to the STM32F4xx Reference manual - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable write access to IWDG_PR and IWDG_RLR registers using - * IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function - * - * 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function - * - * 3. Configure the IWDG counter value using IWDG_SetReload() function. - * This value will be loaded in the IWDG counter each time the counter - * is reloaded, then the IWDG will start counting down from this value. - * - * 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used - * in software mode (no need to enable the LSI, it will be enabled - * by hardware) - * - * 5. Then the application program must reload the IWDG counter at regular - * intervals during normal operation to prevent an MCU reset, using - * IWDG_ReloadCounter() function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_iwdg.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup IWDG - * @brief IWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* KR register bit mask */ -#define KR_KEY_RELOAD ((uint16_t)0xAAAA) -#define KR_KEY_ENABLE ((uint16_t)0xCCCC) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup IWDG_Private_Functions - * @{ - */ - -/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions - * @brief Prescaler and Counter configuration functions - * -@verbatim - =============================================================================== - Prescaler and Counter configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. - * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. - * This parameter can be one of the following values: - * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers - * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers - * @retval None - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); - IWDG->KR = IWDG_WriteAccess; -} - -/** - * @brief Sets IWDG Prescaler value. - * @param IWDG_Prescaler: specifies the IWDG Prescaler value. - * This parameter can be one of the following values: - * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 - * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 - * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 - * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 - * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 - * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 - * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 - * @retval None - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); - IWDG->PR = IWDG_Prescaler; -} - -/** - * @brief Sets IWDG Reload value. - * @param Reload: specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * @retval None - */ -void IWDG_SetReload(uint16_t Reload) -{ - /* Check the parameters */ - assert_param(IS_IWDG_RELOAD(Reload)); - IWDG->RLR = Reload; -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_ReloadCounter(void) -{ - IWDG->KR = KR_KEY_RELOAD; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group2 IWDG activation function - * @brief IWDG activation function - * -@verbatim - =============================================================================== - IWDG activation function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_Enable(void) -{ - IWDG->KR = KR_KEY_ENABLE; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group3 Flag management function - * @brief Flag management function - * -@verbatim - =============================================================================== - Flag management function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified IWDG flag is set or not. - * @param IWDG_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Prescaler Value Update on going - * @arg IWDG_FLAG_RVU: Reload Value Update on going - * @retval The new state of IWDG_FLAG (SET or RESET). - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_IWDG_FLAG(IWDG_FLAG)); - if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c deleted file mode 100644 index ff16e2d82..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c +++ /dev/null @@ -1,638 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_pwr.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * - Backup Domain Access - * - PVD configuration - * - WakeUp pin configuration - * - Backup Regulator configuration - * - Performance Mode and FLASH Power Down configuration functions - * - Low Power modes configuration - * - Flags management - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_pwr.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup PWR - * @brief PWR driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* --------- PWR registers bit address in the alias region ---------- */ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of DBP bit */ -#define CR_OFFSET (PWR_OFFSET + 0x00) -#define DBP_BitNumber 0x08 -#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) - -/* Alias word address of PVDE bit */ -#define PVDE_BitNumber 0x04 -#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) - -/* Alias word address of FPDS bit */ -#define FPDS_BitNumber 0x09 -#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4)) - -/* Alias word address of PMODE bit */ -#define PMODE_BitNumber 0x0E -#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4)) - - -/* --- CSR Register ---*/ - -/* Alias word address of EWUP bit */ -#define CSR_OFFSET (PWR_OFFSET + 0x04) -#define EWUP_BitNumber 0x08 -#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) - -/* Alias word address of BRE bit */ -#define BRE_BitNumber 0x09 -#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4)) - -/* ------------------ PWR registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) -#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** @defgroup PWR_Group1 Backup Domain Access function - * @brief Backup Domain Access function - * -@verbatim - =============================================================================== - Backup Domain Access function - =============================================================================== - - After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - - Enable the Power Controller (PWR) APB1 interface clock using the - RCC_APB1PeriphClockCmd() function. - - Enable access to RTC domain using the PWR_BackupAccessCmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/** - * @brief Enables or disables access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @param NewState: new state of the access to the backup domain. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group2 PVD configuration functions - * @brief PVD configuration functions - * -@verbatim - =============================================================================== - PVD configuration functions - =============================================================================== - - - The PVD is used to monitor the VDD power supply by comparing it to a threshold - selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the - PVD threshold. This event is internally connected to the EXTI line16 - and can generate an interrupt if enabled through the EXTI registers. - - The PVD is stopped in Standby mode. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param PWR_PVDLevel: specifies the PVD detection level - * This parameter can be one of the following values: - * @arg PWR_PVDLevel_0: PVD detection level set to 2.0V - * @arg PWR_PVDLevel_1: PVD detection level set to 2.2V - * @arg PWR_PVDLevel_2: PVD detection level set to 2.3V - * @arg PWR_PVDLevel_3: PVD detection level set to 2.5V - * @arg PWR_PVDLevel_4: PVD detection level set to 2.7V - * @arg PWR_PVDLevel_5: PVD detection level set to 2.8V - * @arg PWR_PVDLevel_6: PVD detection level set to 2.9V - * @arg PWR_PVDLevel_7: PVD detection level set to 3.0V - * @note Refer to the electrical characteristics of you device datasheet for more details. - * @retval None - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); - - tmpreg = PWR->CR; - - /* Clear PLS[7:5] bits */ - tmpreg &= CR_PLS_MASK; - - /* Set PLS[7:5] bits according to PWR_PVDLevel value */ - tmpreg |= PWR_PVDLevel; - - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the Power Voltage Detector(PVD). - * @param NewState: new state of the PVD. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group3 WakeUp pin configuration functions - * @brief WakeUp pin configuration functions - * -@verbatim - =============================================================================== - WakeUp pin configuration functions - =============================================================================== - - - WakeUp pin is used to wakeup the system from Standby mode. This pin is - forced in input pull down configuration and is active on rising edges. - - There is only one WakeUp pin: WakeUp Pin 1 on PA.00. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group4 Backup Regulator configuration functions - * @brief Backup Regulator configuration functions - * -@verbatim - =============================================================================== - Backup Regulator configuration functions - =============================================================================== - - - The backup domain includes 4 Kbytes of backup SRAM accessible only from the - CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained - even in Standby or VBAT mode when the low power backup regulator is enabled. - It can be considered as an internal EEPROM when VBAT is always present. - You can use the PWR_BackupRegulatorCmd() function to enable the low power - backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is - ready or not. - - - When the backup domain is supplied by VDD (analog switch connected to VDD) - the backup SRAM is powered from VDD which replaces the VBAT power supply to - save battery life. - - - The backup SRAM is not mass erased by an tamper event. It is read protected - to prevent confidential data, such as cryptographic private key, from being - accessed. The backup SRAM can be erased only through the Flash interface when - a protection level change from level 1 to level 0 is requested. - Refer to the description of Read protection (RDP) in the Flash programming manual. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the Backup Regulator. - * @param NewState: new state of the Backup Regulator. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupRegulatorCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group5 Performance Mode and FLASH Power Down configuration functions - * @brief Performance Mode and FLASH Power Down configuration functions - * -@verbatim - =============================================================================== - Performance Mode and FLASH Power Down configuration functions - =============================================================================== - - - By setting the PMODE bit in the PWR_CR register by using the PWR_HighPerformanceModeCmd() - function, the high performance mode is selected and the high voltage regulator - minimum value should be around 1.2V. - When reset, the low performance mode is selected and the low voltage regulator - minimum value should be around 1.08V. - - - By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd() - function, the Flash memory also enters power down mode when the device enters - Stop mode. When the Flash memory is in power down mode, an additional startup - delay is incurred when waking up from Stop mode. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the high performance mode. - * @param NewState: new state of the performance mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_HighPerformanceModeCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PMODE_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Flash Power Down in STOP mode. - * @param NewState: new state of the Flash power mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_FlashPowerDownCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group6 Low Power modes configuration functions - * @brief Low Power modes configuration functions - * -@verbatim - =============================================================================== - Low Power modes configuration functions - =============================================================================== - - The devices feature 3 low-power modes: - - Sleep mode: Cortex-M4 core stopped, peripherals kept running. - - Stop mode: all clocks are stopped, regulator running, regulator in low power mode - - Standby mode: 1.2V domain powered off. - - Sleep mode - =========== - - Entry: - - The Sleep mode is entered by using the __WFI() or __WFE() functions. - - Exit: - - Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - Stop mode - ========== - In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, - and the HSE RC oscillators are disabled. Internal SRAM and register contents - are preserved. - The voltage regulator can be configured either in normal or low-power mode. - To minimize the consumption In Stop mode, FLASH can be powered off before - entering the Stop mode. It can be switched on again by software after exiting - the Stop mode using the PWR_FlashPowerDownCmd() function. - - - Entry: - - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) - function with regulator in LowPower or with Regulator ON. - - Exit: - - Any EXTI Line (Internal or External) configured in Interrupt/Event mode. - - Standby mode - ============ - The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. - The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and - the HSE oscillator are also switched off. SRAM and register contents are lost - except for the RTC registers, RTC backup registers, backup SRAM and Standby - circuitry. - - The voltage regulator is OFF. - - - Entry: - - The Standby mode is entered using the PWR_EnterSTANDBYMode() function. - - Exit: - - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, - tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - - Auto-wakeup (AWU) from low-power mode - ===================================== - The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event, a time-stamp event, or a comparator event, - without depending on an external interrupt (Auto-wakeup mode). - - - RTC auto-wakeup (AWU) from the Stop mode - ---------------------------------------- - - - To wake up from the Stop mode with an RTC alarm event, it is necessary to: - - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - - To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to: - - Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - - Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: - - Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - - - RTC auto-wakeup (AWU) from the Standby mode - ------------------------------------------- - - To wake up from the Standby mode with an RTC alarm event, it is necessary to: - - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - - To wake up from the Standby mode with an RTC Tamper or time stamp event, it - is necessary to: - - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - - Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: - - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Enters STOP mode. - * - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_Regulator_ON: STOP mode with regulator ON - * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDSR bits */ - tmpreg &= CR_DS_MASK; - - /* Set LPDSR bit according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enters STANDBY mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC - * Alarm out, or RTC clock calibration out. - * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. - * - WKUP pin 1 (PA0) if enabled. - * @param None - * @retval None - */ -void PWR_EnterSTANDBYMode(void) -{ - /* Clear Wakeup flag */ - PWR->CR |= PWR_CR_CWUF; - - /* Select STANDBY mode */ - PWR->CR |= PWR_CR_PDDS; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM ) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @} - */ - -/** @defgroup PWR_Group7 Flags management functions - * @brief Flags management functions - * -@verbatim - =============================================================================== - Flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received from the WKUP pin or from the RTC alarm (Alarm A - * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. - * An additional wakeup event is detected if the WKUP pin is enabled - * (by setting the EWUP bit) when the WKUP pin level is already high. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset - * when the device wakes up from Standby mode or by a system reset - * or power reset. - * @arg PWR_FLAG_REGRDY: Main regulator ready flag. - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the PWR's pending flags. - * @param PWR_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @retval None - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - - PWR->CR |= PWR_FLAG << 2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c deleted file mode 100644 index 7bd4a983a..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c +++ /dev/null @@ -1,1811 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rcc.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the Reset and clock control (RCC) peripheral: - * - Internal/external clocks, PLL, CSS and MCO configuration - * - System, AHB and APB busses clocks configuration - * - Peripheral clocks configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * RCC specific features - * =================================================================== - * - * After reset the device is running from Internal High Speed oscillator - * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache - * and I-Cache are disabled, and all peripherals are off except internal - * SRAM, Flash and JTAG. - * - There is no prescaler on High speed (AHB) and Low speed (APB) busses; - * all peripherals mapped on these busses are running at HSI speed. - * - The clock for all peripherals is switched off, except the SRAM and FLASH. - * - All GPIOs are in input floating state, except the JTAG pins which - * are assigned to be used for debug purpose. - * - * Once the device started from reset, the user application has to: - * - Configure the clock source to be used to drive the System clock - * (if the application needs higher frequency/performance) - * - Configure the System clock frequency and Flash settings - * - Configure the AHB and APB busses prescalers - * - Enable the clock for the peripheral(s) to be used - * - Configure the clock source(s) for peripherals which clocks are not - * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ------------ RCC registers bit address in the alias region ----------- */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -/* --- CR Register ---*/ -/* Alias word address of HSION bit */ -#define CR_OFFSET (RCC_OFFSET + 0x00) -#define HSION_BitNumber 0x00 -#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) -/* Alias word address of CSSON bit */ -#define CSSON_BitNumber 0x13 -#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) -/* Alias word address of PLLON bit */ -#define PLLON_BitNumber 0x18 -#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) -/* Alias word address of PLLI2SON bit */ -#define PLLI2SON_BitNumber 0x1A -#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) - -/* --- CFGR Register ---*/ -/* Alias word address of I2SSRC bit */ -#define CFGR_OFFSET (RCC_OFFSET + 0x08) -#define I2SSRC_BitNumber 0x17 -#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) - -/* --- BDCR Register ---*/ -/* Alias word address of RTCEN bit */ -#define BDCR_OFFSET (RCC_OFFSET + 0x70) -#define RTCEN_BitNumber 0x0F -#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) -/* Alias word address of BDRST bit */ -#define BDRST_BitNumber 0x10 -#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) -/* --- CSR Register ---*/ -/* Alias word address of LSION bit */ -#define CSR_OFFSET (RCC_OFFSET + 0x74) -#define LSION_BitNumber 0x00 -#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) -/* ---------------------- RCC registers bit mask ------------------------ */ -/* CFGR register bit mask */ -#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) -#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) - -/* RCC Flag Mask */ -#define FLAG_MASK ((uint8_t)0x1F) - -/* CR register byte 3 (Bits[23:16]) base address */ -#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) - -/* BDCR register base address */ -#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions - * @brief Internal and external clocks, PLL, CSS and MCO configuration functions - * -@verbatim - =============================================================================== - Internal/external clocks, PLL, CSS and MCO configuration functions - =============================================================================== - - This section provide functions allowing to configure the internal/external clocks, - PLLs, CSS and MCO pins. - - 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - - 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC - clock source. - - 3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - 4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - 5. PLL (clocked by HSI or HSE), featuring two different output clocks: - - The first output is used to generate the high speed system clock (up to 120 MHz) - - The second output is used to generate the clock for the USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). - - 6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve - high-quality audio performance on the I2S interface. - - 7. CSS (Clock security system), once enable and if a HSE clock failure occurs - (HSE used directly or through PLL as System clock source), the System clock - is automatically switched to HSI and an interrupt is generated if enabled. - The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) - exception vector. - - 8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL - clock (through a configurable prescaler) on PA8 pin. - - 9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S - clock (through a configurable prescaler) on PC9 pin. - -@endverbatim - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE, PLL and PLLI2S OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO1 and MCO2 OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the Clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint8_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; - - /* Set the new HSE configuration -------------------------------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; -} - -/** - * @brief Waits for HSE start-up. - * @note This functions waits on HSERDY flag to be set and return SUCCESS if - * this flag is set, otherwise returns ERROR if the timeout is reached - * and this flag is not set. The timeout value is defined by the constant - * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending - * on the HSE crystal used in your application. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t startupcounter = 0; - ErrorStatus status = ERROR; - FlagStatus hsestatus = RESET; - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - startupcounter++; - } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param HSICalibrationValue: specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); - - tmpreg = RCC->CR; - - /* Clear HSITRIM[4:0] bits */ - tmpreg &= ~RCC_CR_HSITRIM; - - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wakeup from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * @param NewState: new state of the HSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg RCC_LSE_ON: turn ON the LSE oscillator - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - - /* Reset LSEBYP bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - - /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ - switch (RCC_LSE) - { - case RCC_LSE_ON: - /* Set LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; - break; - case RCC_LSE_Bypass: - /* Set LSEBYP and LSEON bits */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - default: - break; - } -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param RCC_PLLSource: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * - * @param PLLM: specifies the division factor for PLL VCO input clock - * This parameter must be a number between 0 and 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * - * @param PLLN: specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLP: specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note You have to set the PLLP parameter correctly to not exceed 120 MHz on - * the System clock frequency. - * - * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks - * This parameter must be a number between 4 and 15. - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - * - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(PLLM)); - assert_param(IS_RCC_PLLN_VALUE(PLLN)); - assert_param(IS_RCC_PLLP_VALUE(PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); - - RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | - (PLLQ << 24); -} - -/** - * @brief Enables or disables the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL can not be disabled if it is used as system clock source - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note PLLI2S is available only in Silicon RevisionB and RevisionY. - * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLI2SR: specifies the division factor for I2S clock - * This parameter must be a number between 2 and 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * - * @retval None - */ -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); - assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); - - RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28); -} - -/** - * @brief Enables or disables the PLLI2S. - * @note PLLI2S is available only in RevisionB and RevisionY - * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLI2SCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. - * @param NewState: new state of the Clock Security System. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the clock source to output on MCO1 pin(PA8). - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCO1Source: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source - * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source - * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source - * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source - * @param RCC_MCO1Div: specifies the MCO1 prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCO1Div_1: no division applied to MCO1 clock - * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock - * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock - * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock - * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock - * @retval None - */ -void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source)); - assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); - - tmpreg = RCC->CFGR; - - /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */ - tmpreg &= CFGR_MCO1_RESET_MASK; - - /* Select MCO1 clock source and prescaler */ - tmpreg |= RCC_MCO1Source | RCC_MCO1Div; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Selects the clock source to output on MCO2 pin(PC9). - * @note PC9 should be configured in alternate function mode. - * @param RCC_MCO2Source: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source - * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source - * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source - * @param RCC_MCO2Div: specifies the MCO2 prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCO2Div_1: no division applied to MCO2 clock - * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock - * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock - * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock - * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock - * @retval None - */ -void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source)); - assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div)); - - tmpreg = RCC->CFGR; - - /* Clear MCO2 and MCO2PRE[2:0] bits */ - tmpreg &= CFGR_MCO2_RESET_MASK; - - /* Select MCO2 clock source and prescaler */ - tmpreg |= RCC_MCO2Source | RCC_MCO2Div; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @} - */ - -/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions - * @brief System, AHB and APB busses clocks configuration functions - * -@verbatim - =============================================================================== - System, AHB and APB busses clocks configuration functions - =============================================================================== - - This section provide functions allowing to configure the System, AHB, APB1 and - APB2 busses clocks. - - 1. Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable prescaler - and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). - APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through - configurable prescalers and used to clock the peripherals mapped on these busses. - You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. - -@note All the peripheral clocks are derived from the System clock (SYSCLK) except: - - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or - from an external clock mapped on the I2S_CKIN pin. - You have to use RCC_I2SCLKConfig() function to configure this clock. - - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() - functions to configure this clock. - - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz - to work correctly, while the SDIO require a frequency equal or lower than - to 48. This clock is derived of the main PLL through PLLQ divider. - - IWDG clock which is always the LSI clock. - - 2. The maximum frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz. - Depending on the device voltage range, the maximum frequency should be - adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 | - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 | - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120| - +-------------------------------------------------------------------------------------+ - - -@endverbatim - * @{ - */ - -/** - * @brief Configures the system clock (SYSCLK). - * @note The HSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use RCC_GetSYSCLKSource() function to know which clock is - * currently used as system clock source. - * @param RCC_SYSCLKSource: specifies the clock source used as system clock. - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - - tmpreg = RCC->CFGR; - - /* Clear SW[1:0] bits */ - tmpreg &= ~RCC_CFGR_SW; - - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @note Depending on the device voltage range, the software has to set correctly - * these bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above - * "CPU, AHB and APB busses clocks configuration functions") - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - - tmpreg = RCC->CFGR; - - /* Clear HPRE[3:0] bits */ - tmpreg &= ~RCC_CFGR_HPRE; - - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - - -/** - * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB1 clock = HCLK - * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE1[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE1; - - /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB2 clock = HCLK - * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE2[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE2; - - /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK << 3; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, - * PCLK1 and PCLK2. - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function - * must be called to update the structure's field. Otherwise, any - * configuration based on this function will be incorrect. - * - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLP - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; - break; - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ - - /* Get HCLK prescaler */ - tmp = RCC->CFGR & RCC_CFGR_HPRE; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - - /* Get PCLK1 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE1; - tmp = tmp >> 10; - presc = APBAHBPrescTable[tmp]; - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - - /* Get PCLK2 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE2; - tmp = tmp >> 13; - presc = APBAHBPrescTable[tmp]; - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; -} - -/** - * @} - */ - -/** @defgroup RCC_Group3 Peripheral clocks configuration functions - * @brief Peripheral clocks configuration functions - * -@verbatim - =============================================================================== - Peripheral clocks configuration functions - =============================================================================== - - This section provide functions allowing to configure the Peripheral clocks. - - 1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31. - - 2. After restart from Reset or wakeup from STANDBY, all peripherals are off - except internal SRAM, Flash and JTAG. Before to start using a peripheral you - have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd() - , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. - - 3. To reset the peripherals configuration (to the default state after device reset) - you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and - RCC_APB1PeriphResetCmd() functions. - - 4. To further reduce power consumption in SLEEP mode the peripheral clocks can - be disabled prior to executing the WFI or WFE instructions. You can do this - using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and - RCC_APB1PeriphClockLPModeCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using PWR_BackupAccessCmd(ENABLE) function before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the - * Backup domain is reset using RCC_BackupResetCmd() function, or by - * a Power On Reset (POR). - * - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected - * as RTC clock, where x:[2,31] - * - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - * - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - - if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300) - { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ - tmpreg = RCC->CFGR; - - /* Clear RTCPRE[4:0] bits */ - tmpreg &= ~RCC_CFGR_RTCPRE; - - /* Configure HSE division factor for RTC clock */ - tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF); - - /* Store the new value */ - RCC->CFGR = tmpreg; - } - - /* Select the RTC clock source */ - RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF); -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock source was selected - * using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; -} - -/** - * @brief Forces or releases the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the I2S clock source (I2SCLK). - * - * @note This function must be called before enabling the I2S APB clock. - * @note This function applies only to Silicon RevisionB and RevisionY. - * - * @param RCC_I2SCLKSource: specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source - * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin - * used as I2S clock source - * @retval None - */ -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); - - *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; -} - -/** - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock - * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock - * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph)); - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB1ENR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1ENR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Enables or disables the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB2ENR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2ENR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Enables or disables the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: RCC_AHB3Periph_FSMC - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB3ENR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3ENR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases AHB1 peripheral reset. - * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB1RSTR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1RSTR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Forces or releases AHB2 peripheral reset. - * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB2RSTR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2RSTR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Forces or releases AHB3 peripheral reset. - * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. - * This parameter must be: RCC_AHB3Periph_FSMC - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB3RSTR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3RSTR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock - * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock - * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB1LPENR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1LPENR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB2LPENR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2LPENR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: RCC_AHB3Periph_FSMC - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB3LPENR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3LPENR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1LPENR |= RCC_APB1Periph; - } - else - { - RCC->APB1LPENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2LPENR |= RCC_APB2Periph; - } - else - { - RCC->APB2LPENR &= ~RCC_APB2Periph; - } -} - -/** - * @} - */ - -/** @defgroup RCC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RCC interrupts. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: main PLL clock ready - * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - if (tmp == 1) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 2) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_MASK; - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= RCC_CSR_RMVF; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC's interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c deleted file mode 100644 index 51817dcc0..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c +++ /dev/null @@ -1,399 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rng.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the Random Number Generator (RNG) peripheral: - * - Initialization and Configuration - * - Get 32 bit Random number - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The RNG controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function. - * - * 2. Activate the RNG peripheral using RNG_Cmd() function. - * - * 3. Wait until the 32 bit Random number Generator contains a valid - * random data (using polling/interrupt mode). For more details, - * refer to "Interrupts and flags management functions" module - * description. - * - * 4. Get the 32 bit Random number using RNG_GetRandomNumber() function - * - * 5. To get another 32 bit Random number, go to step 3. - * - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_rng.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RNG - * @brief RNG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RNG_Private_Functions - * @{ - */ - -/** @defgroup RNG_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to - - Initialize the RNG peripheral - - Enable or disable the RNG peripheral - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the RNG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void RNG_DeInit(void) -{ - /* Enable RNG reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE); - - /* Release RNG from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE); -} - -/** - * @brief Enables or disables the RNG peripheral. - * @param NewState: new state of the RNG peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RNG_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the RNG */ - RNG->CR |= RNG_CR_RNGEN; - } - else - { - /* Disable the RNG */ - RNG->CR &= ~RNG_CR_RNGEN; - } -} -/** - * @} - */ - -/** @defgroup RNG_Group2 Get 32 bit Random number function - * @brief Get 32 bit Random number function - * - -@verbatim - =============================================================================== - Get 32 bit Random number function - =============================================================================== - This section provides a function allowing to get the 32 bit Random number - - @note Before to call this function you have to wait till DRDY flag is set, - using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. - -@endverbatim - * @{ - */ - - -/** - * @brief Returns a 32-bit random number. - * - * @note Before to call this function you have to wait till DRDY (data ready) - * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. - * @note Each time the the Random number data is read (using RNG_GetRandomNumber() - * function), the RNG_FLAG_DRDY flag is automatically cleared. - * @note In the case of a seed error, the generation of random numbers is - * interrupted for as long as the SECS bit is '1'. If a number is - * available in the RNG_DR register, it must not be used because it may - * not have enough entropy. In this case, it is recommended to clear the - * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable - * and enable the RNG peripheral (using RNG_Cmd() function) to - * reinitialize and restart the RNG. - * @note In the case of a clock error, the RNG is no more able to generate - * random numbers because the PLL48CLK clock is not correct. User have - * to check that the clock controller is correctly configured to provide - * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) - * function) . The clock error has no impact on the previously generated - * random numbers, and the RNG_DR register contents can be used. - * - * @param None - * @retval 32-bit random number. - */ -uint32_t RNG_GetRandomNumber(void) -{ - /* Return the 32 bit random number from the DR register */ - return RNG->DR; -} - - -/** - * @} - */ - -/** @defgroup RNG_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the RNG Interrupts and - to get the status and clear flags and Interrupts pending bits. - - The RNG provides 3 Interrupts sources and 3 Flags: - - Flags : - ---------- - 1. RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid - random data. it is cleared by reading the valid data - (using RNG_GetRandomNumber() function). - - 2. RNG_FLAG_CECS : In the case of a seed error detection. - - 3. RNG_FLAG_SECS : In the case of a clock error detection. - - - Interrupts : - ------------ - if enabled, an RNG interrupt is pending : - - 1. In the case of the RNG_DR register contains valid random data. - This interrupt source is cleared once the RNG_DR register has been read - (using RNG_GetRandomNumber() function) until a new valid value is - computed. - - or - 2. In the case of a seed error : One of the following faulty sequences has - been detected: - - More than 64 consecutive bits at the same value (0 or 1) - - More than 32 consecutive alternance of 0 and 1 (0101010101...01) - This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI) - function. - - or - 3. In the case of a clock error : the PLL48CLK (RNG peripheral clock source) - was not correctly detected (fPLL48CLK< fHCLK/16). - This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_CEI) - function. - @note In this case, User have to check that the clock controller is - correctly configured to provide the RNG clock. - - Managing the RNG controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the RNG controller events: Polling mode or Interrupt mode. - - 1. In the Polling Mode it is advised to use the following functions: - - RNG_GetFlagStatus() : to check if flags events occur. - - RNG_ClearFlag() : to clear the flags events. - - @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only - by reading the Random number data. - - 2. In the Interrupt Mode it is advised to use the following functions: - - RNG_ITConfig() : to enable or disable the interrupt source. - - RNG_GetITStatus() : to check if Interrupt occurs. - - RNG_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the RNG interrupt. - * @note The RNG provides 3 interrupt sources, - * - Computed data is ready event (DRDY), and - * - Seed error Interrupt (SEI) and - * - Clock error Interrupt (CEI), - * all these interrupts sources are enabled by setting the IE bit in - * CR register. However, each interrupt have its specific status bit - * (see RNG_GetITStatus() function) and clear bit except the DRDY event - * (see RNG_ClearITPendingBit() function). - * @param NewState: new state of the RNG interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RNG_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the RNG interrupt */ - RNG->CR |= RNG_CR_IE; - } - else - { - /* Disable the RNG interrupt */ - RNG->CR &= ~RNG_CR_IE; - } -} - -/** - * @brief Checks whether the specified RNG flag is set or not. - * @param RNG_FLAG: specifies the RNG flag to check. - * This parameter can be one of the following values: - * @arg RNG_FLAG_DRDY: Data Ready flag. - * @arg RNG_FLAG_CECS: Clock Error Current flag. - * @arg RNG_FLAG_SECS: Seed Error Current flag. - * @retval The new state of RNG_FLAG (SET or RESET). - */ -FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RNG_GET_FLAG(RNG_FLAG)); - - /* Check the status of the specified RNG flag */ - if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET) - { - /* RNG_FLAG is set */ - bitstatus = SET; - } - else - { - /* RNG_FLAG is reset */ - bitstatus = RESET; - } - /* Return the RNG_FLAG status */ - return bitstatus; -} - - -/** - * @brief Clears the RNG flags. - * @param RNG_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg RNG_FLAG_CECS: Clock Error Current flag. - * @arg RNG_FLAG_SECS: Seed Error Current flag. - * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. - * This flag is cleared only by reading the Random number data (using - * RNG_GetRandomNumber() function). - * @retval None - */ -void RNG_ClearFlag(uint8_t RNG_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG)); - /* Clear the selected RNG flags */ - RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); -} - -/** - * @brief Checks whether the specified RNG interrupt has occurred or not. - * @param RNG_IT: specifies the RNG interrupt source to check. - * This parameter can be one of the following values: - * @arg RNG_IT_CEI: Clock Error Interrupt. - * @arg RNG_IT_SEI: Seed Error Interrupt. - * @retval The new state of RNG_IT (SET or RESET). - */ -ITStatus RNG_GetITStatus(uint8_t RNG_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RNG_GET_IT(RNG_IT)); - - /* Check the status of the specified RNG interrupt */ - if ((RNG->SR & RNG_IT) != (uint8_t)RESET) - { - /* RNG_IT is set */ - bitstatus = SET; - } - else - { - /* RNG_IT is reset */ - bitstatus = RESET; - } - /* Return the RNG_IT status */ - return bitstatus; -} - - -/** - * @brief Clears the RNG interrupt pending bit(s). - * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear. - * This parameter can be any combination of the following values: - * @arg RNG_IT_CEI: Clock Error Interrupt. - * @arg RNG_IT_SEI: Seed Error Interrupt. - * @retval None - */ -void RNG_ClearITPendingBit(uint8_t RNG_IT) -{ - /* Check the parameters */ - assert_param(IS_RNG_IT(RNG_IT)); - - /* Clear the selected RNG interrupt pending bit */ - RNG->SR = (uint8_t)~RNG_IT; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c deleted file mode 100644 index 53b9ca1ac..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c +++ /dev/null @@ -1,2733 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rtc.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the Real-Time Clock (RTC) peripheral: - * - Initialization - * - Calendar (Time and Date) configuration - * - Alarms (Alarm A and Alarm B) configuration - * - WakeUp Timer configuration - * - Daylight Saving configuration - * - Output pin Configuration - * - Coarse digital Calibration configuration - * - Smooth digital Calibration configuration - * - TimeStamp configuration - * - Tampers configuration - * - Backup Data Registers configuration - * - Shift control synchronisation - * - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * Backup Domain Operating Condition - * =================================================================== - * The real-time clock (RTC), the RTC backup registers, and the backup - * SRAM (BKP SRAM) can be powered from the VBAT voltage when the main - * VDD supply is powered off. - * To retain the content of the RTC backup registers, backup SRAM, - * and supply the RTC when VDD is turned off, VBAT pin can be connected - * to an optional standby voltage supplied by a battery or by another - * source. - * - * To allow the RTC to operate even when the main digital supply (VDD) - * is turned off, the VBAT pin powers the following blocks: - * 1 - The RTC - * 2 - The LSE oscillator - * 3 - The backup SRAM when the low power backup regulator is enabled - * 4 - PC13 to PC15 I/Os, plus PI8 I/O (when available) - * - * When the backup domain is supplied by VDD (analog switch connected - * to VDD), the following functions are available: - * 1 - PC14 and PC15 can be used as either GPIO or LSE pins - * 2 - PC13 can be used as a GPIO or as the RTC_AF1 pin - * 3 - PI8 can be used as a GPIO or as the RTC_AF2 pin - * - * When the backup domain is supplied by VBAT (analog switch connected - * to VBAT because VDD is not present), the following functions are available: - * 1 - PC14 and PC15 can be used as LSE pins only - * 2 - PC13 can be used as the RTC_AF1 pin - * 3 - PI8 can be used as the RTC_AF2 pin - * - * =================================================================== - * Backup Domain Reset - * =================================================================== - * The backup domain reset sets all RTC registers and the RCC_BDCR - * register to their reset values. The BKPSRAM is not affected by this - * reset. The only way of resetting the BKPSRAM is through the Flash - * interface by requesting a protection level change from 1 to 0. - * A backup domain reset is generated when one of the following events - * occurs: - * 1 - Software reset, triggered by setting the BDRST bit in the - * RCC Backup domain control register (RCC_BDCR). You can use the - * RCC_BackupResetCmd(). - * 2 - VDD or VBAT power on, if both supplies have previously been - * powered off. - * - * =================================================================== - * Backup Domain Access - * =================================================================== - * After reset, the backup domain (RTC registers, RTC backup data - * registers and backup SRAM) is protected against possible unwanted - * write accesses. - * To enable access to the RTC Domain and RTC registers, proceed as follows: - * - Enable the Power Controller (PWR) APB1 interface clock using the - * RCC_APB1PeriphClockCmd() function. - * - Enable access to RTC domain using the PWR_BackupAccessCmd() function. - * - Select the RTC clock source using the RCC_RTCCLKConfig() function. - * - Enable RTC Clock using the RCC_RTCCLKCmd() function. - * - * =================================================================== - * RTC Driver: how to use it - * =================================================================== - * - Enable the RTC domain access (see description in the section above) - * - Configure the RTC Prescaler (Asynchronous and Synchronous) and - * RTC hour format using the RTC_Init() function. - * - * Time and Date configuration - * =========================== - * - To configure the RTC Calendar (Time and Date) use the RTC_SetTime() - * and RTC_SetDate() functions. - * - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() - * functions. - * - Use the RTC_DayLightSavingConfig() function to add or sub one - * hour to the RTC Calendar. - * - * Alarm configuration - * =================== - * - To configure the RTC Alarm use the RTC_SetAlarm() function. - * - Enable the selected RTC Alarm using the RTC_AlarmCmd() function - * - To read the RTC Alarm, use the RTC_GetAlarm() function. - * - To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function. - * - * RTC Wakeup configuration - * ======================== - * - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() - * function. - * - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() - * function - * - Enable the RTC WakeUp using the RTC_WakeUpCmd() function - * - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() - * function. - * - * Outputs configuration - * ===================== - * The RTC has 2 different outputs: - * - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B - * and WaKeUp signals. - * To output the selected RTC signal on RTC_AF1 pin, use the - * RTC_OutputConfig() function. - * - AFO_CALIB: this output is 512Hz signal or 1Hz . - * To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd() - * function. - * - * Smooth digital Calibration configuration - * ================================= - * - Configure the RTC Original Digital Calibration Value and the corresponding - * calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() - * function. - * - * Coarse digital Calibration configuration - * ================================= - * - Configure the RTC Coarse Calibration Value and the corresponding - * sign using the RTC_CoarseCalibConfig() function. - * - Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() - * function - * - * TimeStamp configuration - * ======================= - * - Configure the RTC_AF1 trigger and enables the RTC TimeStamp - * using the RTC_TimeStampCmd() function. - * - To read the RTC TimeStamp Time and Date register, use the - * RTC_GetTimeStamp() function. - * - To read the RTC TimeStamp SubSecond register, use the - * RTC_GetTimeStampSubSecond() function. - * - The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13) - * or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in - * RTC_TAFCR register. You can use the RTC_TamperPinSelection() - * function to select the corresponding pin. - * - * Tamper configuration - * ==================== - * - Enable the RTC Tamper using the RTC_TamperCmd() function. - * - Configure the Tamper filter count using RTC_TamperFilterConfig() - * function. - * - Configure the RTC Tamper trigger Edge or Level according to the Tamper - * filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function. - * - Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig() - * function. - * - Configure the Tamper precharge or discharge duration using - * RTC_TamperPinsPrechargeDuration() function. - * - Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function. - * - Enable the Time stamp on Tamper detection event using - * RTC_TSOnTamperDetecCmd() function. - * - The TIMESTAMP alternate function can be mapped to either RTC_AF1 - * or RTC_AF2 depending on the value of the TSINSEL bit in the - * RTC_TAFCR register. You can use the RTC_TimeStampPinSelection() - * function to select the corresponding pin. - * - * Backup Data Registers configuration - * =================================== - * - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() - * function. - * - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() - * function. - * - * =================================================================== - * RTC and low power modes - * =================================================================== - * The MCU can be woken up from a low power mode by an RTC alternate - * function. - * The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - * RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - * These RTC alternate functions can wake up the system from the Stop - * and Standby lowpower modes. - * The system can also wake up from low power modes without depending - * on an external interrupt (Auto-wakeup mode), by using the RTC alarm - * or the RTC wakeup events. - * The RTC provides a programmable time base for waking up from the - * Stop or Standby mode at regular intervals. - * Wakeup from STOP and Standby modes is possible only when the RTC - * clock source is LSE or LSI. - * - * =================================================================== - * Selection of RTC_AF1 alternate functions - * =================================================================== - * The RTC_AF1 pin (PC13) can be used for the following purposes: - * - AFO_ALARM output - * - AFO_CALIB output - * - AFI_TAMPER - * - AFI_TIMESTAMP - * - * +-------------------------------------------------------------------------------------------------------------+ - * | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | - * | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | - * | and function | | | | | selection | selection |Configuration | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Alarm out | | | | | Don't | Don't | | - * | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Alarm out | | | | | Don't | Don't | | - * | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Calibration out | | | | | Don't | Don't | | - * | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | TAMPER input | | | | | | Don't | | - * | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP and | | | | | | | | - * | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care | - * | floating | | | | | | | | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP input | | | | | Don't | | | - * | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care | - * +-------------------------------------------------------------------------------------------------------------+ - * - * - * =================================================================== - * Selection of RTC_AF2 alternate functions - * =================================================================== - * The RTC_AF2 pin (PI8) can be used for the following purposes: - * - AFI_TAMPER - * - AFI_TIMESTAMP - * - * +---------------------------------------------------------------------------------------+ - * | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | - * | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | - * | and function | | | selection | selection |Configuration | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | TAMPER input | | | | Don't | | - * | floating | 1 | 0 | 1 | care | Don't care | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP and | | | | | | - * | TAMPER input | 1 | 1 | 1 | 1 | Don't care | - * | floating | | | | | | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP input | | | Don't | | | - * | floating | 0 | 1 | care | 1 | Don't care | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care | - * +---------------------------------------------------------------------------------------+ - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_rtc.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RTC - * @brief RTC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ - RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ - RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ - RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F )) - -#define INITMODE_TIMEOUT ((uint32_t) 0x00010000) -#define SYNCHRO_TIMEOUT ((uint32_t) 0x00020000) -#define RECALPF_TIMEOUT ((uint32_t) 0x00020000) -#define SHPF_TIMEOUT ((uint32_t) 0x00001000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static uint8_t RTC_ByteToBcd2(uint8_t Value); -static uint8_t RTC_Bcd2ToByte(uint8_t Value); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RTC_Private_Functions - * @{ - */ - -/** @defgroup RTC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This section provide functions allowing to initialize and configure the RTC - Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers - Write protection, enter and exit the RTC initialization mode, RTC registers - synchronization check and reference clock detection enable. - - 1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is - split into 2 programmable prescalers to minimize power consumption. - - A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. - - When both prescalers are used, it is recommended to configure the asynchronous - prescaler to a high value to minimize consumption. - - 2. All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - - 3. To Configure the RTC Calendar, user application should enter initialization - mode. In this mode, the calendar counter is stopped and its value can be - updated. When the initialization sequence is complete, the calendar restarts - counting after 4 RTCCLK cycles. - - 4. To read the calendar through the shadow registers after Calendar initialization, - calendar update or after wakeup from low power modes the software must first - clear the RSF flag. The software must then wait until it is set again before - reading the calendar, which means that the calendar registers have been - correctly copied into the RTC_TR and RTC_DR shadow registers. - The RTC_WaitForSynchro() function implements the above software sequence - (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the RTC registers to their default reset values. - * @note This function doesn't reset the RTC Clock source and RTC Backup Data - * registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are deinitialized - * - ERROR: RTC registers are not deinitialized - */ -ErrorStatus RTC_DeInit(void) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - RTC->TR = (uint32_t)0x00000000; - RTC->DR = (uint32_t)0x00002101; - /* Reset All CR bits except CR[2:0] */ - RTC->CR &= (uint32_t)0x00000007; - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - /* Reset all RTC CR register bits */ - RTC->CR &= (uint32_t)0x00000000; - RTC->WUTR = (uint32_t)0x0000FFFF; - RTC->PRER = (uint32_t)0x007F00FF; - RTC->CALIBR = (uint32_t)0x00000000; - RTC->ALRMAR = (uint32_t)0x00000000; - RTC->ALRMBR = (uint32_t)0x00000000; - - /* Reset ISR register and exit initialization mode */ - RTC->ISR = (uint32_t)0x00000000; - - /* Reset Tamper and alternate functions configuration register */ - RTC->TAFCR = 0x00000000; - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Initializes the RTC registers according to the specified parameters - * in RTC_InitStruct. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains - * the configuration information for the RTC peripheral. - * @note The RTC Prescaler register is write protected and can be written in - * initialization mode only. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are initialized - * - ERROR: RTC registers are not initialized - */ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Clear RTC CR FMT Bit */ - RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); - /* Set RTC_CR register */ - RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); - - /* Configure the RTC PRER */ - RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); - RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_InitStruct member with its default value. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) -{ - /* Initialize the RTC_HourFormat member */ - RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; - - /* Initialize the RTC_AsynchPrediv member */ - RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; - - /* Initialize the RTC_SynchPrediv member */ - RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; -} - -/** - * @brief Enables or disables the RTC registers write protection. - * @note All the RTC registers are write protected except for RTC_ISR[13:8], - * RTC_TAFCR and RTC_BKPxR. - * @note Writing a wrong key reactivates the write protection. - * @note The protection mechanism is not affected by system reset. - * @param NewState: new state of the write protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_WriteProtectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - } - else - { - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - } -} - -/** - * @brief Enters the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC is in Init mode - * - ERROR: RTC is not in Init mode - */ -ErrorStatus RTC_EnterInitMode(void) -{ - __IO uint32_t initcounter = 0x00; - ErrorStatus status = ERROR; - uint32_t initstatus = 0x00; - - /* Check if the Initialization mode is set */ - if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - /* Set the Initialization mode */ - RTC->ISR = (uint32_t)RTC_INIT_MASK; - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - do - { - initstatus = RTC->ISR & RTC_ISR_INITF; - initcounter++; - } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_INITF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - } - else - { - status = SUCCESS; - } - - return (status); -} - -/** - * @brief Exits the RTC Initialization mode. - * @note When the initialization sequence is complete, the calendar restarts - * counting after 4 RTCCLK cycles. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval None - */ -void RTC_ExitInitMode(void) -{ - /* Exit Initialization mode */ - RTC->ISR &= (uint32_t)~RTC_ISR_INIT; -} - -/** - * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are synchronised - * - ERROR: RTC registers are not synchronised - */ -ErrorStatus RTC_WaitForSynchro(void) -{ - __IO uint32_t synchrocounter = 0; - ErrorStatus status = ERROR; - uint32_t synchrostatus = 0x00; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear RSF flag */ - RTC->ISR &= (uint32_t)RTC_RSF_MASK; - - /* Wait the registers to be synchronised */ - do - { - synchrostatus = RTC->ISR & RTC_ISR_RSF; - synchrocounter++; - } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_RSF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (status); -} - -/** - * @brief Enables or disables the RTC reference clock detection. - * @param NewState: new state of the RTC reference clock. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC reference clock detection is enabled - * - ERROR: RTC reference clock detection is disabled - */ -ErrorStatus RTC_RefClockCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the RTC reference clock detection */ - RTC->CR |= RTC_CR_REFCKON; - } - else - { - /* Disable the RTC reference clock detection */ - RTC->CR &= ~RTC_CR_REFCKON; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or Disables the Bypass Shadow feature. - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @param NewState: new state of the Bypass Shadow feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None -*/ -void RTC_BypassShadowCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Set the BYPSHAD bit */ - RTC->CR |= (uint8_t)RTC_CR_BYPSHAD; - } - else - { - /* Reset the BYPSHAD bit */ - RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** @defgroup RTC_Group2 Time and Date configuration functions - * @brief Time and Date configuration functions - * -@verbatim - =============================================================================== - Time and Date configuration functions - =============================================================================== - - This section provide functions allowing to program and read the RTC Calendar - (Time and Date). - -@endverbatim - * @{ - */ - -/** - * @brief Set the RTC current time. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains - * the time configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Time register is configured - * - ERROR: RTC Time register is not configured - */ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ - ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); - } - else - { - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ - (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_TR register */ - RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_TimeStruct member with its default value - * (Time = 00h:00min:00sec). - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) -{ - /* Time = 00h:00min:00sec */ - RTC_TimeStruct->RTC_H12 = RTC_H12_AM; - RTC_TimeStruct->RTC_Hours = 0; - RTC_TimeStruct->RTC_Minutes = 0; - RTC_TimeStruct->RTC_Seconds = 0; -} - -/** - * @brief Get the RTC current Time. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contain the returned current time configuration. - * @retval None - */ -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); - RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); - } -} - -/** - * @brief Gets the RTC current Calendar Subseconds value. - * @note This function freeze the Time and Date registers after reading the - * SSR register. - * @param None - * @retval RTC current Calendar Subseconds value. - */ -uint32_t RTC_GetSubSecond(void) -{ - uint32_t tmpreg = 0; - - /* Get subseconds values from the correspondent registers*/ - tmpreg = (uint32_t)(RTC->SSR); - - /* Read DR register to unfroze calendar registers */ - (void) (RTC->DR); - - return (tmpreg); -} - -/** - * @brief Set the RTC current date. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains - * the date configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Date register is configured - * - ERROR: RTC Date register is not configured - */ -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) - { - RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; - } - if (RTC_Format == RTC_Format_BIN) - { - assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); - assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); - assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - assert_param(IS_RTC_MONTH(tmpreg)); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - assert_param(IS_RTC_DATE(tmpreg)); - } - assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ - (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_DateStruct->RTC_Date) | \ - (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ - ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_DR register */ - RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_DateStruct member with its default value - * (Monday, January 01 xx00). - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) -{ - /* Monday, January 01 xx00 */ - RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; - RTC_DateStruct->RTC_Date = 1; - RTC_DateStruct->RTC_Month = RTC_Month_January; - RTC_DateStruct->RTC_Year = 0; -} - -/** - * @brief Get the RTC current date. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will - * contain the returned current date configuration. - * @retval None - */ -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); - RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); - RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay); - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group3 Alarms configuration functions - * @brief Alarms (Alarm A and Alarm B) configuration functions - * -@verbatim - =============================================================================== - Alarms (Alarm A and Alarm B) configuration functions - =============================================================================== - - This section provide functions allowing to program and read the RTC Alarms. - -@endverbatim - * @{ - */ - -/** - * @brief Set the specified RTC Alarm. - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the RTC_AlarmCmd(DISABLE)). - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that - * contains the alarm configuration parameters. - * @retval None - */ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm register */ - if (RTC_Alarm == RTC_Alarm_A) - { - RTC->ALRMAR = (uint32_t)tmpreg; - } - else - { - RTC->ALRMBR = (uint32_t)tmpreg; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Fills each RTC_AlarmStruct member with its default value - * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = - * all fields are masked). - * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which - * will be initialized. - * @retval None - */ -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - /* Alarm Time Settings : Time = 00h:00mn:00sec */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; - - /* Alarm Date Settings : Date = 1st day of the month */ - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; - RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; - - /* Alarm Masks Settings : Mask = all fields are not masked */ - RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; -} - -/** - * @brief Get the RTC Alarm value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will - * contains the output alarm configuration values. - * @retval None - */ -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - - /* Get the RTC_ALRMxR register */ - if (RTC_Alarm == RTC_Alarm_A) - { - tmpreg = (uint32_t)(RTC->ALRMAR); - } - else - { - tmpreg = (uint32_t)(RTC->ALRMBR); - } - - /* Fill the structure with the read parameters */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ - RTC_ALRMAR_HU)) >> 16); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ - RTC_ALRMAR_MNU)) >> 8); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ - RTC_ALRMAR_SU)); - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); - - if (RTC_Format == RTC_Format_BIN) - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Hours); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Minutes); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Seconds); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - } -} - -/** - * @brief Enables or disables the specified RTC Alarm. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be any combination of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param NewState: new state of the specified alarm. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Alarm is enabled/disabled - * - ERROR: RTC Alarm is not enabled/disabled - */ -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) -{ - __IO uint32_t alarmcounter = 0x00; - uint32_t alarmstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm state */ - if (NewState != DISABLE) - { - RTC->CR |= (uint32_t)RTC_Alarm; - - status = SUCCESS; - } - else - { - /* Disable the Alarm in RTC_CR register */ - RTC->CR &= (uint32_t)~RTC_Alarm; - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - do - { - alarmstatus = RTC->ISR & (RTC_Alarm >> 8); - alarmcounter++; - } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); - - if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Configure the RTC AlarmA/B Subseconds value and mask.* - * @note This function is performed only when the Alarm is disabled. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmSubSecondValue: specifies the Subseconds value. - * This parameter can be a value from 0 to 0x00007FFF. - * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask. - * This parameter can be any combination of the following values: - * @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked. - * There is no comparison on sub seconds for Alarm. - * @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison. - * Only SS[0] is compared - * @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison. - * Only SS[1:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison. - * Only SS[2:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison. - * Only SS[3:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison. - * Only SS[4:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison. - * Only SS[5:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison. - * Only SS[6:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison. - * Only SS[7:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison. - * Only SS[8:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. - * Only SS[9:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. - * Only SS[10:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. - * Only SS[11:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. - * Only SS[12:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14 : SS[14] is don't care in Alarm comparison. - * Only SS[13:0] are compared - * @arg RTC_AlarmSubSecondMask_None : SS[14:0] are compared and must match - * to activate alarm - * @retval None - */ -void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm A or Alarm B SubSecond registers */ - tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask); - - if (RTC_Alarm == RTC_Alarm_A) - { - /* Configure the AlarmA SubSecond register */ - RTC->ALRMASSR = tmpreg; - } - else - { - /* Configure the Alarm B SubSecond register */ - RTC->ALRMBSSR = tmpreg; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - -} - -/** - * @brief Gets the RTC Alarm Subseconds value. - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param None - * @retval RTC Alarm Subseconds value. - */ -uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) -{ - uint32_t tmpreg = 0; - - /* Get the RTC_ALRMxR register */ - if (RTC_Alarm == RTC_Alarm_A) - { - tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS); - } - else - { - tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS); - } - - return (tmpreg); -} - -/** - * @} - */ - -/** @defgroup RTC_Group4 WakeUp Timer configuration functions - * @brief WakeUp Timer configuration functions - * -@verbatim - =============================================================================== - WakeUp Timer configuration functions - =============================================================================== - - This section provide functions allowing to program and read the RTC WakeUp. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC Wakeup clock source. - * @note The WakeUp Clock source can only be changed when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpClock: Wakeup Clock source. - * This parameter can be one of the following values: - * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16 - * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8 - * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4 - * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2 - * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE - * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE - * @retval None - */ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the Wakeup Timer clock source bits in CR register */ - RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - RTC->CR |= (uint32_t)RTC_WakeUpClock; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the RTC Wakeup counter. - * @note The RTC WakeUp counter can only be written when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpCounter: specifies the WakeUp counter. - * This parameter can be a value from 0x0000 to 0xFFFF. - * @retval None - */ -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Wakeup Timer counter */ - RTC->WUTR = (uint32_t)RTC_WakeUpCounter; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC WakeUp timer counter value. - * @param None - * @retval The RTC WakeUp Counter value. - */ -uint32_t RTC_GetWakeUpCounter(void) -{ - /* Get the counter value */ - return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT)); -} - -/** - * @brief Enables or Disables the RTC WakeUp timer. - * @param NewState: new state of the WakeUp timer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the Wakeup Timer */ - RTC->CR |= (uint32_t)RTC_CR_WUTE; - status = SUCCESS; - } - else - { - /* Disable the Wakeup Timer */ - RTC->CR &= (uint32_t)~RTC_CR_WUTE; - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @} - */ - -/** @defgroup RTC_Group5 Daylight Saving configuration functions - * @brief Daylight Saving configuration functions - * -@verbatim - =============================================================================== - Daylight Saving configuration functions - =============================================================================== - - This section provide functions allowing to configure the RTC DayLight Saving. - -@endverbatim - * @{ - */ - -/** - * @brief Adds or substract one hour from the current time. - * @param RTC_DayLightSaveOperation: the value of hour adjustment. - * This parameter can be one of the following values: - * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) - * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) - * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit - * in CR register to store the operation. - * This parameter can be one of the following values: - * @arg RTC_StoreOperation_Reset: BCK Bit Reset - * @arg RTC_StoreOperation_Set: BCK Bit Set - * @retval None - */ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) -{ - /* Check the parameters */ - assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_BCK); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC Day Light Saving stored operation. - * @param None - * @retval RTC Day Light Saving stored operation. - * - RTC_StoreOperation_Reset - * - RTC_StoreOperation_Set - */ -uint32_t RTC_GetStoreOperation(void) -{ - return (RTC->CR & RTC_CR_BCK); -} - -/** - * @} - */ - -/** @defgroup RTC_Group6 Output pin Configuration function - * @brief Output pin Configuration function - * -@verbatim - =============================================================================== - Output pin Configuration function - =============================================================================== - - This section provide functions allowing to configure the RTC Output source. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC output source (AFO_ALARM). - * @param RTC_Output: Specifies which signal will be routed to the RTC output. - * This parameter can be one of the following values: - * @arg RTC_Output_Disable: No output selected - * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output - * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output - * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output - * @param RTC_OutputPolarity: Specifies the polarity of the output signal. - * This parameter can be one of the following: - * @arg RTC_OutputPolarity_High: The output pin is high when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @arg RTC_OutputPolarity_Low: The output pin is low when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @retval None - */ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT(RTC_Output)); - assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); - - /* Configure the output selection and polarity */ - RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** @defgroup RTC_Group7 Digital Calibration configuration functions - * @brief Coarse Calibration configuration functions - * -@verbatim - =============================================================================== - Digital Calibration configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Coarse calibration parameters. - * @param RTC_CalibSign: specifies the sign of the coarse calibration value. - * This parameter can be one of the following values: - * @arg RTC_CalibSign_Positive: The value sign is positive - * @arg RTC_CalibSign_Negative: The value sign is negative - * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits). - * - * @note This Calibration value should be between 0 and 63 when using negative - * sign with a 2-ppm step. - * - * @note This Calibration value should be between 0 and 126 when using positive - * sign with a 4-ppm step. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Coarse calibration are initialized - * - ERROR: RTC Coarse calibration are not initialized - */ -ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign)); - assert_param(IS_RTC_CALIB_VALUE(Value)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the coarse calibration value */ - RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value); - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or disables the Coarse calibration process. - * @param NewState: new state of the Coarse calibration. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Coarse calibration are enabled/disabled - * - ERROR: RTC Coarse calibration are not enabled/disabled - */ -ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the Coarse Calibration */ - RTC->CR |= (uint32_t)RTC_CR_DCE; - } - else - { - /* Disable the Coarse Calibration */ - RTC->CR &= (uint32_t)~RTC_CR_DCE; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or disables the RTC clock to be output through the relative pin. - * @param NewState: new state of the digital calibration Output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_CalibOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the RTC clock output */ - RTC->CR |= (uint32_t)RTC_CR_COE; - } - else - { - /* Disable the RTC clock output */ - RTC->CR &= (uint32_t)~RTC_CR_COE; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param RTC_CalibOutput : Select the Calibration output Selection . - * This parameter can be one of the following values: - * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. - * @arg RTC_CalibOutput_1Hz : A signal has a regular waveform at 1Hz. - * @retval None -*/ -void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput) -{ - /* Check the parameters */ - assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /*clear flags before config*/ - RTC->CR &= (uint32_t)~(RTC_CR_COSEL); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)RTC_CalibOutput; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the Smooth Calibration Settings. - * @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period. - * This parameter can be can be one of the following values: - * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration periode is 32s. - * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration periode is 16s. - * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion periode is 8s. - * @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit. - * This parameter can be one of the following values: - * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses. - * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added. - * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. - * This parameter can be one any value from 0 to 0x000001FF. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Calib registers are configured - * - ERROR: RTC Calib registers are not configured -*/ -ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, - uint32_t RTC_SmoothCalibPlusPulses, - uint32_t RTC_SmouthCalibMinusPulsesValue) -{ - ErrorStatus status = ERROR; - uint32_t recalpfcount = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod)); - assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* check if a calibration is pending*/ - if ((RTC->ISR & RTC_ISR_RECALPF) != RESET) - { - /* wait until the Calibration is completed*/ - while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) - { - recalpfcount++; - } - } - - /* check if the calibration pending is completed or if there is no calibration operation at all*/ - if ((RTC->ISR & RTC_ISR_RECALPF) == RESET) - { - /* Configure the Smooth calibration settings */ - RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue); - - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (ErrorStatus)(status); -} - -/** - * @} - */ - - -/** @defgroup RTC_Group8 TimeStamp configuration functions - * @brief TimeStamp configuration functions - * -@verbatim - =============================================================================== - TimeStamp configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or Disables the RTC TimeStamp functionality with the - * specified time stamp pin stimulating edge. - * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following: - * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising - * edge of the related pin. - * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the - * falling edge of the related pin. - * @param NewState: new state of the TimeStamp. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Get the new configuration */ - if (NewState != DISABLE) - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); - } - else - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Time Stamp TSEDGE and Enable bits */ - RTC->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Get the RTC TimeStamp value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contains the TimeStamp time values. - * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will - * contains the TimeStamp date values. - * @retval None - */ -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct) -{ - uint32_t tmptime = 0, tmpdate = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the TimeStamp time and date registers values */ - tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); - - /* Fill the Date structure fields with the read parameters */ - RTC_StampDateStruct->RTC_Year = 0; - RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the Time structure parameters to Binary format */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); - - /* Convert the Date structure parameters to Binary format */ - RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); - RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); - } -} - -/** - * @brief Get the RTC timestamp Subseconds value. - * @param None - * @retval RTC current timestamp Subseconds value. - */ -uint32_t RTC_GetTimeStampSubSecond(void) -{ - /* Get timestamp subseconds values from the correspondent registers */ - return (uint32_t)(RTC->TSSSR); -} - -/** - * @} - */ - -/** @defgroup RTC_Group9 Tampers configuration functions - * @brief Tampers configuration functions - * -@verbatim - =============================================================================== - Tampers configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the select Tamper pin edge. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1. - * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that - * stimulates tamper event. - * This parameter can be one of the following values: - * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. - * @retval None - */ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); - - if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); - } - else - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); - } -} - -/** - * @brief Enables or Disables the Tamper detection. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1. - * @param NewState: new state of the tamper pin. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_Tamper; - } - else - { - /* Disable the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_Tamper; - } -} - -/** - * @brief Configures the Tampers Filter. - * @param RTC_TamperFilter: Specifies the tampers filter. - * This parameter can be one of the following values: - * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. - * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive - * samples at the active level - * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive - * samples at the active level - * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive - * samples at the active level - * @retval None - */ -void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); - - /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperFilter; -} - -/** - * @brief Configures the Tampers Sampling Frequency. - * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. - * This parameter can be one of the following values: - * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 32768 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 16384 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 8192 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 4096 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 2048 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 1024 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 512 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 256 - * @retval None - */ -void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); - - /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq; -} - -/** - * @brief Configures the Tampers Pins input Precharge Duration. - * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input - * Precharge Duration. - * This parameter can be one of the following values: - * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle - * @retval None - */ -void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); - - /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration; -} - -/** - * @brief Enables or Disables the TimeStamp on Tamper Detection Event. - * @note The timestamp is valid even the TSE bit in tamper control register - * is reset. - * @param NewState: new state of the timestamp on tamper event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Save timestamp on tamper detection event */ - RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS; - } - else - { - /* Tamper detection does not cause a timestamp to be saved */ - RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; - } -} - -/** - * @brief Enables or Disables the Precharge of Tamper pin. - * @param NewState: new state of tamper pull up. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperPullUpCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable precharge of the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; - } - else - { - /* Disable precharge of the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group10 Backup Data Registers configuration functions - * @brief Backup Data Registers configuration functions - * -@verbatim - =============================================================================== - Backup Data Registers configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Writes a data in a specified RTC Backup data register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None - */ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval None - */ -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} - -/** - * @} - */ - -/** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions - * @brief RTC Tamper and TimeStamp Pins Selection and Output Type Config - * configuration functions - * -@verbatim - =============================================================================== - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Selects the RTC Tamper Pin. - * @param RTC_TamperPin: specifies the RTC Tamper Pin. - * This parameter can be one of the following values: - * @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin. - * @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin. - * @retval None - */ -void RTC_TamperPinSelection(uint32_t RTC_TamperPin) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL); - RTC->TAFCR |= (uint32_t)(RTC_TamperPin); -} - -/** - * @brief Selects the RTC TimeStamp Pin. - * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. - * This parameter can be one of the following values: - * @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin. - * @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin. - * @retval None - */ -void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin) -{ - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL); - RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin); -} - -/** - * @brief Configures the RTC Output Pin mode. - * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. - * This parameter can be one of the following values: - * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in - * Open Drain mode. - * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in - * Push Pull mode. - * @retval None - */ -void RTC_OutputTypeConfig(uint32_t RTC_OutputType) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); - RTC->TAFCR |= (uint32_t)(RTC_OutputType); -} - -/** - * @} - */ - -/** @defgroup RTC_Group12 Shift control synchronisation functions - * @brief Shift control synchronisation functions - * -@verbatim - =============================================================================== - Shift control synchronisation functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register - * @param RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar. - * This parameter can be one of the following values : - * @arg RTC_ShiftAdd1S_Set : Add one second to the clock calendar. - * @arg RTC_ShiftAdd1S_Reset: No effect. - * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute. - * This parameter can be one any value from 0 to 0x7FFF. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Shift registers are configured - * - ERROR: RTC Shift registers are not configured -*/ -ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) -{ - ErrorStatus status = ERROR; - uint32_t shpfcount = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Check if a Shift is pending*/ - if ((RTC->ISR & RTC_ISR_SHPF) != RESET) - { - /* Wait until the shift is completed*/ - while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) - { - shpfcount++; - } - } - - /* Check if the Shift pending is completed or if there is no Shift operation at all*/ - if ((RTC->ISR & RTC_ISR_SHPF) == RESET) - { - /* check if the reference clock detection is disabled */ - if((RTC->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = ERROR; - } - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (ErrorStatus)(status); -} - -/** - * @} - */ - -/** @defgroup RTC_Group13 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - All RTC interrupts are connected to the EXTI controller. - - - To enable the RTC Alarm interrupt, the following sequence is required: - - Configure and enable the EXTI Line 17 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using - the RTC_SetAlarm() and RTC_AlarmCmd() functions. - - - To enable the RTC Wakeup interrupt, the following sequence is required: - - Configure and enable the EXTI Line 22 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to generate the RTC wakeup timer event using the - RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - - - To enable the RTC Tamper interrupt, the following sequence is required: - - Configure and enable the EXTI Line 21 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to detect the RTC tamper event using the - RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. - - - To enable the RTC TimeStamp interrupt, the following sequence is required: - - Configure and enable the EXTI Line 21 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to detect the RTC time-stamp event using the - RTC_TimeStampCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RTC interrupts. - * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt mask - * @arg RTC_IT_WUT: WakeUp Timer interrupt mask - * @arg RTC_IT_ALRB: Alarm B interrupt mask - * @arg RTC_IT_ALRA: Alarm A interrupt mask - * @arg RTC_IT_TAMP: Tamper event interrupt mask - * @param NewState: new state of the specified RTC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_CONFIG_IT(RTC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); - } - else - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Checks whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_INITF: Initialization mode flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_INITS: Registers Configured flag - * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag - * @arg RTC_FLAG_ALRBWF: Alarm B Write flag - * @arg RTC_FLAG_ALRAWF: Alarm A write flag - * @retval The new state of RTC_FLAG (SET or RESET). - */ -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); - - /* Get all the flags */ - tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); - - /* Return the status of the flag */ - if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's pending flags. - * @param RTC_FLAG: specifies the RTC flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @retval None - */ -void RTC_ClearFlag(uint32_t RTC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - - /* Clear the Flags in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Checks whether the specified RTC interrupt has occurred or not. - * @param RTC_IT: specifies the RTC interrupt source to check. - * This parameter can be one of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper 1 event interrupt - * @retval The new state of RTC_IT (SET or RESET). - */ -ITStatus RTC_GetITStatus(uint32_t RTC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_IT(RTC_IT)); - - /* Get the TAMPER Interrupt enable bit and pending bit */ - tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); - - /* Get the Interrupt enable Status */ - enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15))); - - /* Get the Interrupt pending bit */ - tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); - - /* Get the status of the Interrupt */ - if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's interrupt pending bits. - * @param RTC_IT: specifies the RTC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper 1 event interrupt - * @retval None - */ -void RTC_ClearITPendingBit(uint32_t RTC_IT) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_IT(RTC_IT)); - - /* Get the RTC_ISR Interrupt pending bits mask */ - tmpreg = (uint32_t)(RTC_IT >> 4); - - /* Clear the interrupt pending bits in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @} - */ - -/** - * @brief Converts a 2 digit decimal to BCD format. - * @param Value: Byte to be converted. - * @retval Converted byte - */ -static uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint8_t bcdhigh = 0; - - while (Value >= 10) - { - bcdhigh++; - Value -= 10; - } - - return ((uint8_t)(bcdhigh << 4) | Value); -} - -/** - * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted. - * @retval Converted word - */ -static uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint8_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c deleted file mode 100644 index 9984cea30..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c +++ /dev/null @@ -1,1004 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_sdio.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the Secure digital input/output interface (SDIO) - * peripheral: - * - Initialization and Configuration - * - Command path state machine (CPSM) management - * - Data path state machine (DPSM) management - * - SDIO IO Cards mode management - * - CE-ATA mode management - * - DMA transfers management - * - Interrupts and flags management - * - * @verbatim - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output - * of PLL (PLL48CLK). Before to start working with SDIO peripheral - * make sure that the PLL is well configured. - * The SDIO peripheral uses two clock signals: - * - SDIO adapter clock (SDIOCLK = 48 MHz) - * - APB2 bus clock (PCLK2) - * PCLK2 and SDIO_CK clock frequencies must respect the following condition: - * Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) - * - * 2. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). - * - * 3. According to the SDIO mode, enable the GPIO clocks using - * RCC_AHB1PeriphClockCmd() function. - * The I/O can be one of the following configurations: - * - 1-bit data length: SDIO_CMD, SDIO_CK and D0. - * - 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. - * - 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0]. - * - * 4. Peripheral's alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 5. Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, - * hardware, flow control and the Clock Divider using the SDIO_Init() - * function. - * - * 6. Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) - * function. - * - * 7. Enable the clock using the SDIO_ClockCmd() function. - * - * 8. Enable the NVIC and the corresponding interrupt using the function - * SDIO_ITConfig() if you need to use interrupt mode. - * - * 9. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using SDIO_DMACmd() function - * - * 10. Enable the DMA using the DMA_Cmd() function, when using DMA mode. - * - * 11. To control the CPSM (Command Path State Machine) and send - * commands to the card use the SDIO_SendCommand(), - * SDIO_GetCommandResponse() and SDIO_GetResponse() functions. - * First, user has to fill the command structure (pointer to - * SDIO_CmdInitTypeDef) according to the selected command to be sent. - * The parameters that should be filled are: - * - Command Argument - * - Command Index - * - Command Response type - * - Command Wait - * - CPSM Status (Enable or Disable) - * - * To check if the command is well received, read the SDIO_CMDRESP - * register using the SDIO_GetCommandResponse(). - * The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the - * SDIO_GetResponse() function. - * - * 12. To control the DPSM (Data Path State Machine) and send/receive - * data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), - * SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions. - * - * Read Operations - * --------------- - * a) First, user has to fill the data structure (pointer to - * SDIO_DataInitTypeDef) according to the selected data type to - * be received. - * The parameters that should be filled are: - * - Data TimeOut - * - Data Length - * - Data Block size - * - Data Transfer direction: should be from card (To SDIO) - * - Data Transfer mode - * - DPSM Status (Enable or Disable) - * - * b) Configure the SDIO resources to receive the data from the card - * according to selected transfer mode (Refer to Step 8, 9 and 10). - * - * c) Send the selected Read command (refer to step 11). - * - * d) Use the SDIO flags/interrupts to check the transfer status. - * - * Write Operations - * --------------- - * a) First, user has to fill the data structure (pointer to - * SDIO_DataInitTypeDef) according to the selected data type to - * be received. - * The parameters that should be filled are: - * - Data TimeOut - * - Data Length - * - Data Block size - * - Data Transfer direction: should be to card (To CARD) - * - Data Transfer mode - * - DPSM Status (Enable or Disable) - * - * b) Configure the SDIO resources to send the data to the card - * according to selected transfer mode (Refer to Step 8, 9 and 10). - * - * c) Send the selected Write command (refer to step 11). - * - * d) Use the SDIO flags/interrupts to check the transfer status. - * - * - * @endverbatim - * - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_sdio.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SDIO - * @brief SDIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ------------ SDIO registers bit address in the alias region ----------- */ -#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) - -/* --- CLKCR Register ---*/ -/* Alias word address of CLKEN bit */ -#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) -#define CLKEN_BitNumber 0x08 -#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) - -/* --- CMD Register ---*/ -/* Alias word address of SDIOSUSPEND bit */ -#define CMD_OFFSET (SDIO_OFFSET + 0x0C) -#define SDIOSUSPEND_BitNumber 0x0B -#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) - -/* Alias word address of ENCMDCOMPL bit */ -#define ENCMDCOMPL_BitNumber 0x0C -#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) - -/* Alias word address of NIEN bit */ -#define NIEN_BitNumber 0x0D -#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) - -/* Alias word address of ATACMD bit */ -#define ATACMD_BitNumber 0x0E -#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) - -/* --- DCTRL Register ---*/ -/* Alias word address of DMAEN bit */ -#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) -#define DMAEN_BitNumber 0x03 -#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) - -/* Alias word address of RWSTART bit */ -#define RWSTART_BitNumber 0x08 -#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) - -/* Alias word address of RWSTOP bit */ -#define RWSTOP_BitNumber 0x09 -#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) - -/* Alias word address of RWMOD bit */ -#define RWMOD_BitNumber 0x0A -#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) - -/* Alias word address of SDIOEN bit */ -#define SDIOEN_BitNumber 0x0B -#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) - -/* ---------------------- SDIO registers bit mask ------------------------ */ -/* --- CLKCR Register ---*/ -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) - -/* --- PWRCTRL Register ---*/ -/* SDIO PWRCTRL Mask */ -#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) - -/* --- DCTRL Register ---*/ -/* SDIO DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) - -/* --- CMD Register ---*/ -/* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) - -/* SDIO RESP Registers Address */ -#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SDIO_Private_Functions - * @{ - */ - -/** @defgroup SDIO_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SDIO peripheral registers to their default reset values. - * @param None - * @retval None - */ -void SDIO_DeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE); -} - -/** - * @brief Initializes the SDIO peripheral according to the specified - * parameters in the SDIO_InitStruct. - * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure - * that contains the configuration information for the SDIO peripheral. - * @retval None - */ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); - assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); - assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); - assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); - assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); - -/*---------------------------- SDIO CLKCR Configuration ------------------------*/ - /* Get the SDIO CLKCR value */ - tmpreg = SDIO->CLKCR; - - /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ - tmpreg &= CLKCR_CLEAR_MASK; - - /* Set CLKDIV bits according to SDIO_ClockDiv value */ - /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ - /* Set BYPASS bit according to SDIO_ClockBypass value */ - /* Set WIDBUS bits according to SDIO_BusWide value */ - /* Set NEGEDGE bits according to SDIO_ClockEdge value */ - /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ - tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | - SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | - SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); - - /* Write to SDIO CLKCR */ - SDIO->CLKCR = tmpreg; -} - -/** - * @brief Fills each SDIO_InitStruct member with its default value. - * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) -{ - /* SDIO_InitStruct members default value */ - SDIO_InitStruct->SDIO_ClockDiv = 0x00; - SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; -} - -/** - * @brief Enables or disables the SDIO Clock. - * @param NewState: new state of the SDIO Clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ClockCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; -} - -/** - * @brief Sets the power status of the controller. - * @param SDIO_PowerState: new state of the Power state. - * This parameter can be one of the following values: - * @arg SDIO_PowerState_OFF: SDIO Power OFF - * @arg SDIO_PowerState_ON: SDIO Power ON - * @retval None - */ -void SDIO_SetPowerState(uint32_t SDIO_PowerState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); - - SDIO->POWER = SDIO_PowerState; -} - -/** - * @brief Gets the power status of the controller. - * @param None - * @retval Power status of the controller. The returned value can be one of the - * following values: - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDIO_GetPowerState(void) -{ - return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); -} - -/** - * @} - */ - -/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions - * @brief Command path state machine (CPSM) management functions - * -@verbatim - =============================================================================== - Command path state machine (CPSM) management functions - =============================================================================== - - This section provide functions allowing to program and read the Command path - state machine (CPSM). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SDIO Command according to the specified - * parameters in the SDIO_CmdInitStruct and send the command. - * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef - * structure that contains the configuration information for the SDIO - * command. - * @retval None - */ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); - assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); - assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); - assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); - -/*---------------------------- SDIO ARG Configuration ------------------------*/ - /* Set the SDIO Argument value */ - SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; - -/*---------------------------- SDIO CMD Configuration ------------------------*/ - /* Get the SDIO CMD value */ - tmpreg = SDIO->CMD; - /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ - tmpreg &= CMD_CLEAR_MASK; - /* Set CMDINDEX bits according to SDIO_CmdIndex value */ - /* Set WAITRESP bits according to SDIO_Response value */ - /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ - /* Set CPSMEN bits according to SDIO_CPSM value */ - tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response - | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; - - /* Write to SDIO CMD */ - SDIO->CMD = tmpreg; -} - -/** - * @brief Fills each SDIO_CmdInitStruct member with its default value. - * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef - * structure which will be initialized. - * @retval None - */ -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) -{ - /* SDIO_CmdInitStruct members default value */ - SDIO_CmdInitStruct->SDIO_Argument = 0x00; - SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; - SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; -} - -/** - * @brief Returns command index of last command for which response received. - * @param None - * @retval Returns the command index of the last command response received. - */ -uint8_t SDIO_GetCommandResponse(void) -{ - return (uint8_t)(SDIO->RESPCMD); -} - -/** - * @brief Returns response received from the card for the last command. - * @param SDIO_RESP: Specifies the SDIO response register. - * This parameter can be one of the following values: - * @arg SDIO_RESP1: Response Register 1 - * @arg SDIO_RESP2: Response Register 2 - * @arg SDIO_RESP3: Response Register 3 - * @arg SDIO_RESP4: Response Register 4 - * @retval The Corresponding response register value. - */ -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_RESP(SDIO_RESP)); - - tmp = SDIO_RESP_ADDR + SDIO_RESP; - - return (*(__IO uint32_t *) tmp); -} - -/** - * @} - */ - -/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions - * @brief Data path state machine (DPSM) management functions - * -@verbatim - =============================================================================== - Data path state machine (DPSM) management functions - =============================================================================== - - This section provide functions allowing to program and read the Data path - state machine (DPSM). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SDIO data path according to the specified - * parameters in the SDIO_DataInitStruct. - * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure - * that contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); - assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); - assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); - assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); - assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); - -/*---------------------------- SDIO DTIMER Configuration ---------------------*/ - /* Set the SDIO Data TimeOut value */ - SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; - -/*---------------------------- SDIO DLEN Configuration -----------------------*/ - /* Set the SDIO DataLength value */ - SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; - -/*---------------------------- SDIO DCTRL Configuration ----------------------*/ - /* Get the SDIO DCTRL value */ - tmpreg = SDIO->DCTRL; - /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ - tmpreg &= DCTRL_CLEAR_MASK; - /* Set DEN bit according to SDIO_DPSM value */ - /* Set DTMODE bit according to SDIO_TransferMode value */ - /* Set DTDIR bit according to SDIO_TransferDir value */ - /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ - tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir - | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; - - /* Write to SDIO DCTRL */ - SDIO->DCTRL = tmpreg; -} - -/** - * @brief Fills each SDIO_DataInitStruct member with its default value. - * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure - * which will be initialized. - * @retval None - */ -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - /* SDIO_DataInitStruct members default value */ - SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; - SDIO_DataInitStruct->SDIO_DataLength = 0x00; - SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; - SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; -} - -/** - * @brief Returns number of remaining data bytes to be transferred. - * @param None - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDIO_GetDataCounter(void) -{ - return SDIO->DCOUNT; -} - -/** - * @brief Read one data word from Rx FIFO. - * @param None - * @retval Data received - */ -uint32_t SDIO_ReadData(void) -{ - return SDIO->FIFO; -} - -/** - * @brief Write one data word to Tx FIFO. - * @param Data: 32-bit data word to write. - * @retval None - */ -void SDIO_WriteData(uint32_t Data) -{ - SDIO->FIFO = Data; -} - -/** - * @brief Returns the number of words left to be written to or read from FIFO. - * @param None - * @retval Remaining number of words. - */ -uint32_t SDIO_GetFIFOCount(void) -{ - return SDIO->FIFOCNT; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions - * @brief SDIO IO Cards mode management functions - * -@verbatim - =============================================================================== - SDIO IO Cards mode management functions - =============================================================================== - - This section provide functions allowing to program and read the SDIO IO Cards. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the SD I/O Read Wait operation. - * @param NewState: new state of the Start SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StartSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; -} - -/** - * @brief Stops the SD I/O Read Wait operation. - * @param NewState: new state of the Stop SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StopSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; -} - -/** - * @brief Sets one of the two options of inserting read wait interval. - * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. - * This parameter can be: - * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK - * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 - * @retval None - */ -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) -{ - /* Check the parameters */ - assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); - - *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; -} - -/** - * @brief Enables or disables the SD I/O Mode Operation. - * @param NewState: new state of SDIO specific operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SetSDIOOperation(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the SD I/O Mode suspend command sending. - * @param NewState: new state of the SD I/O Mode suspend command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group5 CE-ATA mode management functions - * @brief CE-ATA mode management functions - * -@verbatim - =============================================================================== - CE-ATA mode management functions - =============================================================================== - - This section provide functions allowing to program and read the CE-ATA card. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the command completion signal. - * @param NewState: new state of command completion signal. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CommandCompletionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the CE-ATA interrupt. - * @param NewState: new state of CE-ATA interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CEATAITCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); -} - -/** - * @brief Sends CE-ATA command (CMD61). - * @param NewState: new state of CE-ATA command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendCEATACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group6 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - - This section provide functions allowing to program SDIO DMA transfer. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SDIO DMA request. - * @param NewState: new state of the selected SDIO DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SDIO interrupts. - * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @param NewState: new state of the specified SDIO interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_IT(SDIO_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the SDIO interrupts */ - SDIO->MASK |= SDIO_IT; - } - else - { - /* Disable the SDIO interrupts */ - SDIO->MASK &= ~SDIO_IT; - } -} - -/** - * @brief Checks whether the specified SDIO flag is set or not. - * @param SDIO_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_CMDACT: Command transfer in progress - * @arg SDIO_FLAG_TXACT: Data transmit in progress - * @arg SDIO_FLAG_RXACT: Data receive in progress - * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full - * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval The new state of SDIO_FLAG (SET or RESET). - */ -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_FLAG(SDIO_FLAG)); - - if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's pending flags. - * @param SDIO_FLAG: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearFlag(uint32_t SDIO_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); - - SDIO->ICR = SDIO_FLAG; -} - -/** - * @brief Checks whether the specified SDIO interrupt has occurred or not. - * @param SDIO_IT: specifies the SDIO interrupt source to check. - * This parameter can be one of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval The new state of SDIO_IT (SET or RESET). - */ -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_GET_IT(SDIO_IT)); - if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's interrupt pending bits. - * @param SDIO_IT: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearITPendingBit(uint32_t SDIO_IT) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); - - SDIO->ICR = SDIO_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c deleted file mode 100644 index 5f478d192..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c +++ /dev/null @@ -1,1290 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_spi.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the Serial peripheral interface (SPI): - * - Initialization and Configuration - * - Data transfers functions - * - Hardware CRC Calculation - * - DMA transfers management - * - Interrupts and flags management - * - * @verbatim - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * 1. Enable peripheral clock using the following functions - * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 - * RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3. - * - * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() - * function. - * In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO - * clock should also be enabled. - * - * 3. Peripherals alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * In I2S mode, if an external clock source is used then the I2S CKIN pin - * should be also configured in Alternate function Push-pull pull-up mode. - * - * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave - * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - * function. - * In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio - * frequency and Polarity using I2S_Init() function. - * For I2S mode, make sure that either: - * - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), - * RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY). - * or - * - External clock source is configured using the function - * RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant - * I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. - * - * 5. Enable the NVIC and the corresponding interrupt using the function - * SPI_ITConfig() if you need to use interrupt mode. - * - * 6. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using SPI_I2S_DMACmd() function - * - * 7. Enable the SPI using the SPI_Cmd() function or enable the I2S using - * I2S_Cmd(). - * - * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode. - * - * 9. Optionally, you can enable/configure the following parameters without - * re-initialization (i.e there is no need to call again SPI_Init() function): - * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) - * is programmed as Data direction parameter using the SPI_Init() function - * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx - * using the SPI_BiDirectionalLineConfig() function. - * - When SPI_NSS_Soft is selected as Slave Select Management parameter - * using the SPI_Init() function it can be possible to manage the - * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. - * - Reconfigure the data size using the SPI_DataSizeConfig() function - * - Enable or disable the SS output using the SPI_SSOutputCmd() function - * - * 10. To use the CRC Hardware calculation feature refer to the Peripheral - * CRC hardware Calculation subsection. - * - * - * It is possible to use SPI in I2S full duplex mode, in this case, each SPI - * peripheral is able to manage sending and receiving data simultaneously - * using two data lines. Each SPI peripheral has an extended block called I2Sxext - * (ie. I2S2ext for SPI2 and I2S3ext for SPI3). - * The extension block is not a full SPI IP, it is used only as I2S slave to - * implement full duplex mode. The extension block uses the same clock sources - * as its master. - * To configure I2S full duplex you have to: - * - * 1. Configure SPIx in I2S mode (I2S_Init() function) as described above. - * - * 2. Call the I2S_FullDuplexConfig() function using the same strucutre passed to - * I2S_Init() function. - * - * 3. Call I2S_Cmd() for SPIx then for its extended block. - * - * 4. To configure interrupts or DMA requests and to get/clear flag status, - * use I2Sxext instance for the extension block. - * - * Functions that can be called with I2Sxext instances are: - * I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), - * SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(), - * SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit(). - * - * Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx): - * - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE); - * I2S_StructInit(&I2SInitStruct); - * I2SInitStruct.Mode = I2S_Mode_MasterTx; - * I2S_Init(SPI3, &I2SInitStruct); - * I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct) - * I2S_Cmd(SPI3, ENABLE); - * I2S_Cmd(SPI3ext, ENABLE); - * ... - * while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) - * {} - * SPI_I2S_SendData(SPI3, txdata[i]); - * ... - * while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET) - * {} - * rxdata[i] = SPI_I2S_ReceiveData(I2S3ext); - * ... - * - * - * - * @note This driver supports only the I2S clock scheme available in Silicon - * RevisionB and RevisionY. - * - * @note In I2S mode: if an external clock is used as source clock for the I2S, - * then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should - * be enabled and set to the value of the source clock frequency (in Hz). - * - * @note In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() - * just after calling the function SPI_Init(). - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_spi.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* SPI registers Masks */ -#define CR1_CLEAR_MASK ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) - -/* RCC PLLs masks */ -#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000) -#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0) - -#define SPI_CR2_FRF ((uint16_t)0x0010) -#define SPI_SR_TIFRFE ((uint16_t)0x0100) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** @defgroup SPI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This section provides a set of functions allowing to initialize the SPI Direction, - SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud - Rate Prescaler, SPI First Bit and SPI CRC Polynomial. - - The SPI_Init() function follows the SPI configuration procedures for Master mode - and Slave mode (details for these procedures are available in reference manual - (RM0090)). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitialize the SPIx peripheral registers to their default reset values. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * - * @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are deinitialized - * when the relative I2S peripheral is deinitialized (the extended block's clock - * is managed by the I2S peripheral clock). - * - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else - { - if (SPIx == SPI3) - { - /* Enable SPI3 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - /* Release SPI3 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - } - } -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - -/*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/salve mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); -/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode). - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * - * @note The function calculates the optimal prescaler needed to obtain the most - * accurate audio frequency (depending on the I2S clock source, the PLL values - * and the product configuration). But in case the prescaler value is greater - * than 511, the default value (0x02) will be configured instead. - * - * @note if an external clock is used as source clock for the I2S, then the define - * I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set - * to the value of the the source clock frequency (in Hz). - * - * @retval None - */ -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0, i2sclk = 0; -#ifndef I2S_EXTERNAL_CLOCK_VAL - uint32_t pllm = 0, plln = 0, pllr = 0; -#endif /* I2S_EXTERNAL_CLOCK_VAL */ - - /* Check the I2S parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; - SPIx->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = SPIx->I2SCFGR; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) *******************/ - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* Get I2S source Clock frequency (only in Silicon RevisionB and RevisionY) */ - - /* If an external I2S clock has to be used, this define should be set - in the project configuration or in the stm32f4xx_conf.h file */ - #ifdef I2S_EXTERNAL_CLOCK_VAL - /* Set external clock as I2S clock source */ - if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0) - { - RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC; - } - - /* Set the I2S clock to the external clock value */ - i2sclk = I2S_EXTERNAL_CLOCK_VAL; - - #else /* There is no define for External I2S clock source */ - /* Set PLLI2S as I2S clock source */ - if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0) - { - RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC; - } - - /* Get the PLLI2SN value */ - plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \ - (RCC_PLLI2SCFGR_PLLI2SN >> 6)); - - /* Get the PLLI2SR value */ - pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \ - (RCC_PLLI2SCFGR_PLLI2SR >> 28)); - - /* Get the PLLM value */ - pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - - /* Get the I2S source clock value */ - i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); - #endif /* I2S_EXTERNAL_CLOCK_VAL */ - - /* Compute the Real divider depending on the MCLK output state, with a floating point */ - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - /* MCLK output is enabled */ - tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - /* Remove the flatting point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /* Write to SPIx I2SPR register the computed value */ - SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - SPIx->I2SCFGR = tmpreg; -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Fills each I2S_InitStruct member with its default value. - * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) -{ -/*--------------- Reset I2S init structure parameters values -----------------*/ - /* Initialize the I2S_Mode member */ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - - /* Initialize the I2S_Standard member */ - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - - /* Initialize the I2S_DataFormat member */ - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - - /* Initialize the I2S_MCLKOutput member */ - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - - /* Initialize the I2S_AudioFreq member */ - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - - /* Initialize the I2S_CPOL member */ - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= SPI_CR1_SPE; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); - } -} - -/** - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (or I2Sxext - * for full duplex mode). - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_23_PERIPH_EXT(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; - } - else - { - /* Disable the selected SPI peripheral in I2S mode */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); - } -} - -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_DataSize: specifies the SPI data size. - * This parameter can be one of the following values: - * @arg SPI_DataSize_16b: Set data frame format to 16bit - * @arg SPI_DataSize_8b: Set data frame format to 8bit - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATASIZE(SPI_DataSize)); - /* Clear DFF bit */ - SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; - /* Set new DFF bit value */ - SPIx->CR1 |= SPI_DataSize; -} - -/** - * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); - } -} - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * - * @note This function can be called only after the SPI_Init() function has - * been called. - * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA - * are not taken into consideration and are configured by hardware - * respectively to the TI mode requirements. - * - * @param SPIx: where x can be 1, 2 or 3 - * @param NewState: new state of the selected SPI TI communication mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TI mode for the selected SPI peripheral */ - SPIx->CR2 |= SPI_CR2_FRF; - } - else - { - /* Disable the TI mode for the selected SPI peripheral */ - SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF; - } -} - -/** - * @brief Configures the full duplex mode for the I2Sx peripheral using its - * extension I2Sxext according to the specified parameters in the - * I2S_InitStruct. - * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block. - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified I2S peripheral - * extension. - * - * @note The structure pointed by I2S_InitStruct parameter should be the same - * used for the master I2S peripheral. In this case, if the master is - * configured as transmitter, the slave will be receiver and vice versa. - * Or you can force a different mode by modifying the field I2S_Mode to the - * value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration. - * - * @note The I2S full duplex extension can be configured in slave mode only. - * - * @retval None - */ -void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, tmp = 0; - - /* Check the I2S parameters */ - assert_param(IS_I2S_EXT_PERIPH(I2Sxext)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK; - I2Sxext->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = I2Sxext->I2SCFGR; - - /* Get the mode to be configured for the extended I2S */ - if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) - { - tmp = I2S_Mode_SlaveRx; - } - else - { - if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx)) - { - tmp = I2S_Mode_SlaveTx; - } - } - - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - I2Sxext->I2SCFGR = tmpreg; -} - -/** - * @} - */ - -/** @defgroup SPI_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - Data transfers functions - =============================================================================== - - This section provides a set of functions allowing to manage the SPI data transfers - - In reception, data are received and then stored into an internal Rx buffer while - In transmission, data are first stored into an internal Tx buffer before being - transmitted. - - The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() - function and returns the Rx buffered value. Whereas a write access to the SPI_DR - can be done using SPI_I2S_SendData() function and stores the written data into - Tx buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - - /* Return the data in the DR register */ - return SPIx->DR; -} - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param Data: Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - - /* Write in the DR register the data to be sent */ - SPIx->DR = Data; -} - -/** - * @} - */ - -/** @defgroup SPI_Group3 Hardware CRC Calculation functions - * @brief Hardware CRC Calculation functions - * -@verbatim - =============================================================================== - Hardware CRC Calculation functions - =============================================================================== - - This section provides a set of functions allowing to manage the SPI CRC hardware - calculation - - SPI communication using CRC is possible through the following procedure: - 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, - Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function. - 2. Enable the CRC calculation using the SPI_CalculateCRC() function. - 3. Enable the SPI using the SPI_Cmd() function - 4. Before writing the last data to the TX buffer, set the CRCNext bit using the - SPI_TransmitCRC() function to indicate that after transmission of the last - data, the CRC should be transmitted. - 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT - bit is reset. The CRC is also received and compared against the SPI_RXCRCR - value. - If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt - can be generated when the SPI_I2S_IT_ERR interrupt is enabled. - -@note It is advised not to read the calculated CRC values during the communication. - -@note When the SPI is in slave mode, be careful to enable CRC calculation only - when the clock is stable, that is, when the clock is in the steady state. - If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive - to the SCK slave input clock as soon as CRCEN is set, and this, whatever - the value of the SPE bit. - -@note With high bitrate frequencies, be careful when transmitting the CRC. - As the number of used CPU cycles has to be as low as possible in the CRC - transfer phase, it is forbidden to call software functions in the CRC - transmission sequence to avoid errors in the last data and CRC reception. - In fact, CRCNEXT bit has to be written before the end of the transmission/reception - of the last data. - -@note For high bit rate frequencies, it is advised to use the DMA mode to avoid the - degradation of the SPI speed performance due to CPU accesses impacting the - SPI bandwidth. - -@note When the STM32F4xx is configured as slave and the NSS hardware mode is - used, the NSS pin needs to be kept low between the data phase and the CRC - phase. - -@note When the SPI is configured in slave mode with the CRC feature enabled, CRC - calculation takes place even if a high level is applied on the NSS pin. - This may happen for example in case of a multi-slave environment where the - communication master addresses slaves alternately. - -@note Between a slave de-selection (high level on NSS) and a new slave selection - (low level on NSS), the CRC value should be cleared on both master and slave - sides in order to resynchronize the master and slave for their respective - CRC calculation. - -@note To clear the CRC, follow the procedure below: - 1. Disable SPI using the SPI_Cmd() function - 2. Disable the CRC calculation using the SPI_CalculateCRC() function. - 3. Enable the CRC calculation using the SPI_CalculateCRC() function. - 4. Enable SPI using the SPI_Cmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= SPI_CR1_CRCEN; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); - } -} - -/** - * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= SPI_CR1_CRCNEXT; -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @} - */ - -/** @defgroup SPI_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @} - */ - -/** @defgroup SPI_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides a set of functions allowing to configure the SPI Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - Polling Mode - ============= - In Polling Mode, the SPI/I2S communication can be managed by 9 flags: - 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register - 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register - 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. - 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur - 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur - 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur - 7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. - 8. I2S_FLAG_UDR: to indicate an Underrun error occurs. - 9. I2S_FLAG_CHSIDE: to indicate Channel Side. - -@note Do not use the BSY flag to handle each data transmission or reception. It is - better to use the TXE and RXNE flags instead. - - In this Mode it is advised to use the following functions: - - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - Interrupt Mode - =============== - In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources - and 7 pending bits: - Pending Bits: - ------------- - 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register - 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register - 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) - 4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) - 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur - 6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). - 7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only). - - Interrupt Source: - ----------------- - 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty - interrupt. - 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. - - In this Mode it is advised to use the following functions: - - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); - - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - DMA Mode - ======== - In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: - 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request - 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request - - In this Mode it is advised to use the following function: - - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Checks whether the specified SPIx/I2Sx flag is set or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_FLAG_MODF: Mode Fault flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * @arg SPI_I2S_FLAG_TIFRFE: Format Error. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - - /* Check the status of the specified SPI flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * - * @note OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note UDR (UnderRun error) flag is cleared by a read operation to - * SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg SPI_IT_MODF: Mode Fault interrupt. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * @arg I2S_IT_UDR: Underrun interrupt. - * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S_IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI_I2S_IT IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. - * This function clears only CRCERR interrupt pending bit. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * - * @note OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). - * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_SR register (SPI_I2S_GetITStatus()). - * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable - * the SPI). - * @retval None - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ - SPIx->SR = (uint16_t)~itpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c deleted file mode 100644 index 0aa22b42f..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c +++ /dev/null @@ -1,204 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_syscfg.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the SYSCFG peripheral. - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * This driver provides functions for: - * - * 1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig() - * - * 2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig() - * - * 3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig() - * - * @note SYSCFG APB clock must be enabled to get write access to SYSCFG registers, - * using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_syscfg.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SYSCFG - * @brief SYSCFG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ------------ RCC registers bit address in the alias region ----------- */ -#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) -/* --- PMC Register ---*/ -/* Alias word address of MII_RMII_SEL bit */ -#define PMC_OFFSET (SYSCFG_OFFSET + 0x04) -#define MII_RMII_SEL_BitNumber ((uint8_t)0x17) -#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) - -/* --- CMPCR Register ---*/ -/* Alias word address of CMP_PD bit */ -#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) -#define CMP_PD_BitNumber ((uint8_t)0x00) -#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SYSCFG_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the Alternate Functions (remap and EXTI configuration) - * registers to their default reset values. - * @param None - * @retval None - */ -void SYSCFG_DeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE); -} - -/** - * @brief Changes the mapping of the specified pin. - * @param SYSCFG_Memory: selects the memory remapping. - * This parameter can be one of the following values: - * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000 - * - * @note In remap mode, the FSMC addressing is fixed to the remap address area only - * (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) and FSMC control registers are not - * accessible. The FSMC remap function must be disabled to allows addressing - * other memory devices through the FSMC and/or to access FSMC control - * registers. - * - * @retval None - */ -void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap)); - - SYSCFG->MEMRMP = SYSCFG_MemoryRemap; -} - -/** - * @brief Selects the GPIO pin used as EXTI Line. - * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for - * EXTI lines where x can be (A..I). - * @param EXTI_PinSourcex: specifies the EXTI line to be configured. - * This parameter can be EXTI_PinSourcex where x can be (0..15, except - * for EXTI_PortSourceGPIOI x can be (0..11). - * @retval None - */ -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) -{ - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); - assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); - - tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); -} - -/** - * @brief Selects the ETHERNET media interface - * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. - * This parameter can be one of the following values: - * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected - * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected - * @retval None - */ -void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) -{ - assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); - /* Configure MII_RMII selection bit */ - *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; -} - -/** - * @brief Enables or disables the I/O Compensation Cell. - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V. - * @param NewState: new state of the I/O Compensation Cell. - * This parameter can be one of the following values: - * @arg ENABLE: I/O compensation cell enabled - * @arg DISABLE: I/O compensation cell power-down mode - * @retval None - */ -void SYSCFG_CompensationCellCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState; -} - -/** - * @brief Checks whether the I/O Compensation Cell ready flag is set or not. - * @param None - * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET) - */ -FlagStatus SYSCFG_GetCompensationCellStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c deleted file mode 100644 index 711a66df7..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c +++ /dev/null @@ -1,3349 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_tim.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the TIM peripheral: - * - TimeBase management - * - Output Compare management - * - Input Capture management - * - Advanced-control timers (TIM1 and TIM8) specific features - * - Interrupts, DMA and flags management - * - Clocks management - * - Synchronization management - * - Specific interface management - * - Specific remapping management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * This driver provides functions to configure and program the TIM - * of all STM32F4xx devices. - * These functions are split in 9 groups: - * - * 1. TIM TimeBase management: this group includes all needed functions - * to configure the TM Timebase unit: - * - Set/Get Prescaler - * - Set/Get Autoreload - * - Counter modes configuration - * - Set Clock division - * - Select the One Pulse mode - * - Update Request Configuration - * - Update Disable Configuration - * - Auto-Preload Configuration - * - Enable/Disable the counter - * - * 2. TIM Output Compare management: this group includes all needed - * functions to configure the Capture/Compare unit used in Output - * compare mode: - * - Configure each channel, independently, in Output Compare mode - * - Select the output compare modes - * - Select the Polarities of each channel - * - Set/Get the Capture/Compare register values - * - Select the Output Compare Fast mode - * - Select the Output Compare Forced mode - * - Output Compare-Preload Configuration - * - Clear Output Compare Reference - * - Select the OCREF Clear signal - * - Enable/Disable the Capture/Compare Channels - * - * 3. TIM Input Capture management: this group includes all needed - * functions to configure the Capture/Compare unit used in - * Input Capture mode: - * - Configure each channel in input capture mode - * - Configure Channel1/2 in PWM Input mode - * - Set the Input Capture Prescaler - * - Get the Capture/Compare values - * - * 4. Advanced-control timers (TIM1 and TIM8) specific features - * - Configures the Break input, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable) - * - Enable/Disable the TIM peripheral Main Outputs - * - Select the Commutation event - * - Set/Reset the Capture Compare Preload Control bit - * - * 5. TIM interrupts, DMA and flags management - * - Enable/Disable interrupt sources - * - Get flags status - * - Clear flags/ Pending bits - * - Enable/Disable DMA requests - * - Configure DMA burst mode - * - Select CaptureCompare DMA request - * - * 6. TIM clocks management: this group includes all needed functions - * to configure the clock controller unit: - * - Select internal/External clock - * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx - * - * 7. TIM synchronization management: this group includes all needed - * functions to configure the Synchronization unit: - * - Select Input Trigger - * - Select Output Trigger - * - Select Master Slave Mode - * - ETR Configuration when used as external trigger - * - * 8. TIM specific interface management, this group includes all - * needed functions to use the specific TIM interface: - * - Encoder Interface Configuration - * - Select Hall Sensor - * - * 9. TIM specific remapping management includes the Remapping - * configuration of specific timers - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_tim.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup TIM - * @brief TIM driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define SMCR_ETR_MASK ((uint16_t)0x00FF) -#define CCMR_OFFSET ((uint16_t)0x0018) -#define CCER_CCE_SET ((uint16_t)0x0001) -#define CCER_CCNE_SET ((uint16_t)0x0004) -#define CCMR_OC13M_MASK ((uint16_t)0xFF8F) -#define CCMR_OC24M_MASK ((uint16_t)0x8FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup TIM_Private_Functions - * @{ - */ - -/** @defgroup TIM_Group1 TimeBase management functions - * @brief TimeBase management functions - * -@verbatim - =============================================================================== - TimeBase management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in Timing(Time base) Mode - =================================================================== - To use the Timer in Timing(Time base) mode, the following steps are mandatory: - - 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - 2. Fill the TIM_TimeBaseInitStruct with the desired parameters. - - 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit - with the corresponding configuration - - 4. Enable the NVIC if you need to generate the update interrupt. - - 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) - - 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - Note1: All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval None - - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - if (TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if (TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if (TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if (TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } - else if (TIMx == TIM5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); - } - else if (TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } - else if (TIMx == TIM7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); - } - else if (TIMx == TIM8) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); - } - else if (TIMx == TIM9) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); - } - else if (TIMx == TIM10) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); - } - else if (TIMx == TIM11) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); - } - else if (TIMx == TIM12) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); - } - else if (TIMx == TIM13) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); - } - else - { - if (TIMx == TIM14) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); - } - } -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); - - tmpcr1 = TIMx->CR1; - - if((TIMx == TIM1) || (TIMx == TIM8)|| - (TIMx == TIM2) || (TIMx == TIM3)|| - (TIMx == TIM4) || (TIMx == TIM5)) - { - /* Select the Counter Mode */ - tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - if((TIMx != TIM6) && (TIMx != TIM7)) - { - /* Set the clock division */ - tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if ((TIMx == TIM1) || (TIMx == TIM8)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediatly */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef - * structure which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - - tmpcr1 = TIMx->CR1; - - /* Reset the CMS and DIR Bits */ - tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS); - - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval Counter Register value - */ -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= TIM_CR1_UDIS; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS; - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Regular: Source of update is the counter - * overflow/underflow or the setting of UG bit, or an update - * generation through the slave mode controller. - * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= TIM_CR1_URS; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_URS; - } -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= TIM_CR1_ARPE; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE; - } -} - -/** - * @brief Selects the TIMx's One Pulse Mode. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - - /* Reset the OPM Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - -/** - * @brief Sets the TIMx Clock Division value. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_CKD: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CKD_DIV1: TDTS = Tck_tim - * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim - * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CKD_DIV(TIM_CKD)); - - /* Reset the CKD Bits */ - TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD); - - /* Set the CKD value */ - TIMx->CR1 |= TIM_CKD; -} - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_CEN; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group2 Output Compare management functions - * @brief Output Compare management functions - * -@verbatim - =============================================================================== - Output Compare management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in Output Compare Mode - =================================================================== - To use the Timer in Output Compare mode, the following steps are mandatory: - - 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - 2. Configure the TIM pins by configuring the corresponding GPIO pins - - 2. Configure the Time base unit as described in the first part of this driver, - if needed, else the Timer will run with the default configuration: - - Autoreload value = 0xFFFF - - Prescaler value = 0x0000 - - Counter mode = Up counting - - Clock Division = TIM_CKD_DIV1 - - 3. Fill the TIM_OCInitStruct with the desired parameters including: - - The TIM Output Compare mode: TIM_OCMode - - TIM Output State: TIM_OutputState - - TIM Pulse value: TIM_Pulse - - TIM Output Compare Polarity : TIM_OCPolarity - - 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the - corresponding configuration - - 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - Note1: All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - - Note2: In case of PWM mode, this function is mandatory: - TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); - - Note3: If the corresponding interrupt or DMA request are needed, the user should: - 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). - 2. Enable the corresponding interrupt (or DMA request) using the function - TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIMx Channel1 according to the specified parameters in - * the TIM_OCInitStruct. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M; - tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NE; - - /* Set the Output N State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS1; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M; - tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NE; - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS2; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M; - tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NE; - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS3; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M; - tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Output Compare IDLE State */ - tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x00000000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/** - * @brief Selects the TIM Output Compare Mode. - * @note This function disables the selected channel before changing the Output - * Compare Mode. If needed, user has to enable this channel using - * TIM_CCxCmd() and TIM_CCxNCmd() functions. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This parameter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_OFFSET; - - tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1M Bits */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M; - - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2M Bits */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M; - - /* Configure The Forced output Mode */ - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC1M Bits */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M; - - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC2M Bits */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M; - - /* Configure The Forced output Mode */ - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1PE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2PE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3PE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4PE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1FE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE; - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2FE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3FE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE; - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4FE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF1 signal on an external event - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1CE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= TIM_OCClear; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF2 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2CE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF3 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3CE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= TIM_OCClear; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF4 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4CE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC1P Bit */ - tmpccer &= (uint16_t)(~TIM_CCER_CC1P); - tmpccer |= TIM_OCPolarity; - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 1N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC1N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC1NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NP; - tmpccer |= TIM_OCNPolarity; - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC2P Bit */ - tmpccer &= (uint16_t)(~TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 2N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC2N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC2NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NP; - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC3P Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC3P; - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 3N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC3N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC3NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NP; - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC4P Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC4P; - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = CCER_CCE_SET << TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t)~ tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. - * @retval None - */ -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCXN(TIM_CCxN)); - - tmp = CCER_CCNE_SET << TIM_Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= (uint16_t) ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} -/** - * @} - */ - -/** @defgroup TIM_Group3 Input Capture management functions - * @brief Input Capture management functions - * -@verbatim - =============================================================================== - Input Capture management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in Input Capture Mode - =================================================================== - To use the Timer in Input Capture mode, the following steps are mandatory: - - 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - 2. Configure the TIM pins by configuring the corresponding GPIO pins - - 2. Configure the Time base unit as described in the first part of this driver, - if needed, else the Timer will run with the default configuration: - - Autoreload value = 0xFFFF - - Prescaler value = 0x0000 - - Counter mode = Up counting - - Clock Division = TIM_CKD_DIV1 - - 3. Fill the TIM_ICInitStruct with the desired parameters including: - - TIM Channel: TIM_Channel - - TIM Input Capture polarity: TIM_ICPolarity - - TIM Input Capture selection: TIM_ICSelection - - TIM Input Capture Prescaler: TIM_ICPrescaler - - TIM Input CApture filter value: TIM_ICFilter - - 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the - corresponding configuration and to measure only frequency or duty cycle of the input signal, - or, - Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the - corresponding configuration and to measure the frequency and the duty cycle of the input signal - - 5. Enable the NVIC or the DMA to read the measured frequency. - - 6. Enable the corresponding interrupt (or DMA request) to read the Captured value, - using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - - 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - 8. Use TIM_GetCapturex(TIMx); to read the captured value. - - Note1: All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM peripheral according to the specified parameters - * in the TIM_ICInitStruct. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - /* TI3 Configuration */ - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI4 Configuration */ - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Configures the TIM peripheral according to the specified parameters - * in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @retval Capture Compare 1 Register value. - */ -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @retval Capture Compare 2 Register value. - */ -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 3 Register value. - */ -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 4 Register value. - */ -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); -} -/** - * @} - */ - -/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features - * @brief Advanced-control timers (TIM1 and TIM8) specific features - * -@verbatim - =============================================================================== - Advanced-control timers (TIM1 and TIM8) specific features - =============================================================================== - - =================================================================== - TIM Driver: how to use the Break feature - =================================================================== - After configuring the Timer channel(s) in the appropriate Output Compare mode: - - 1. Fill the TIM_BDTRInitStruct with the desired parameters for the Timer - Break Polarity, dead time, Lock level, the OSSI/OSSR State and the - AOE(automatic output enable). - - 2. Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer - - 3. Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) - - 4. Once the break even occurs, the Timer's output signals are put in reset - state or in a known state (according to the configuration made in - TIM_BDTRConfig() function). - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param TIMx: where x can be 1 or 8 to select the TIM - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval None - */ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); - assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); - assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); - assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); - assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/** - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which - * will be initialized. - * @retval None - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/** - * @brief Enables or disables the TIM peripheral Main Outputs. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. - * @param NewState: new state of the TIM peripheral Main Outputs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Main Output */ - TIMx->BDTR |= TIM_BDTR_MOE; - } - else - { - /* Disable the TIM Main Output */ - TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE; - } -} - -/** - * @brief Selects the TIM peripheral Commutation event. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the COM Bit */ - TIMx->CR2 |= TIM_CR2_CCUS; - } - else - { - /* Reset the COM Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS; - } -} - -/** - * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Capture Compare Preload Control bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCPC Bit */ - TIMx->CR2 |= TIM_CR2_CCPC; - } - else - { - /* Reset the CCPC Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group5 Interrupts DMA and flags management functions - * @brief Interrupts, DMA and flags management functions - * -@verbatim - =============================================================================== - Interrupts, DMA and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. - * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used - * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, - * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. - * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can - * be used: TIM_IT_Update or TIM_IT_CC1 - * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 - * - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx->DIER |= TIM_IT; - } - else - { - /* Disable the Interrupt sources */ - TIMx->DIER &= (uint16_t)~TIM_IT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * - * @note TIM6 and TIM7 can only generate an update event. - * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Checks whether the specified TIM flag is set or not. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * - * @retval The new state of TIM_FLAG (SET or RESET). - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); - - - if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's pending flags. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Clear the flags */ - TIMx->SR = (uint16_t)~TIM_FLAG; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_IT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_IT(TIM_IT)); - - itstatus = TIMx->SR & TIM_IT; - - itenable = TIMx->DIER & TIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_IT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM1 update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Clear the IT pending Bit */ - TIMx->SR = (uint16_t)~TIM_IT; -} - -/** - * @brief Configures the TIMx's DMA interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_DMABase: DMA Base address. - * This parameter can be one of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM1_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_RCR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_BDTR - * @arg TIM_DMABase_DCR - * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval None - */ -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); - assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); - - /* Set the DMA Base and the DMA Burst Length */ - TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; -} - -/** - * @brief Enables or disables the TIMx's DMA Requests. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. - * @param TIM_DMASource: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg TIM_DMA_Update: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_Trigger: TIM Trigger DMA source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA sources */ - TIMx->DIER |= TIM_DMASource; - } - else - { - /* Disable the DMA sources */ - TIMx->DIER &= (uint16_t)~TIM_DMASource; - } -} - -/** - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param NewState: new state of the Capture Compare DMA source - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the CCDS Bit */ - TIMx->CR2 |= TIM_CR2_CCDS; - } - else - { - /* Reset the CCDS Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group6 Clocks management functions - * @brief Clocks management functions - * -@verbatim - =============================================================================== - Clocks management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx internal Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_InputTriggerSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter: specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Reset the SMS Bits */ - tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; - - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - - /* Select the Trigger selection : ETRF */ - tmpsmcr &= (uint16_t)~TIM_SMCR_TS; - tmpsmcr |= TIM_TS_ETRF; - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Enable the External clock mode2 */ - TIMx->SMCR |= TIM_SMCR_ECE; -} -/** - * @} - */ - -/** @defgroup TIM_Group7 Synchronization management functions - * @brief Synchronization management functions - * -@verbatim - =============================================================================== - Synchronization management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in synchronization Mode - =================================================================== - Case of two/several Timers - ************************** - 1. Configure the Master Timers using the following functions: - - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); - - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); - 2. Configure the Slave Timers using the following functions: - - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - - Case of Timers and external trigger(ETR pin) - ******************************************** - 1. Configure the External trigger using this function: - - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - 2. Configure the Slave Timers using the following functions: - - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - -@endverbatim - * @{ - */ - -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Reset the TS Bits */ - tmpsmcr &= (uint16_t)~TIM_SMCR_TS; - - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. - * - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This parameter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO) - * - * - For all TIMx except TIM6 and TIM7 - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs(TRGO) - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO) - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS; - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize - * the counter and triggers an update of the registers - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - - /* Reset the SMS Bits */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; - - /* Select the Slave Mode */ - TIMx->SMCR |= TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO) - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - - /* Reset the MSM Bit */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM; - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_MASK; - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @} - */ - -/** @defgroup TIM_Group8 Specific interface management functions - * @brief Specific interface management functions - * -@verbatim - =============================================================================== - Specific interface management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Set the encoder Mode */ - tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; - tmpsmcr |= TIM_EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S); - tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIMx's Hall sensor interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= TIM_CR2_TI1S; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group9 Specific remapping management function - * @brief Specific remapping management function - * -@verbatim - =============================================================================== - Specific remapping management function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. - * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral. - * @param TIM_Remap: specifies the TIM input remapping source. - * This parameter can be one of the following values: - * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) - * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output. - * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. - * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. - * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock. - * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock. - * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. - * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock - * (HSE divided by a programmable prescaler) - * @retval None - */ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_REMAP(TIM_Remap)); - - /* Set the Timer remapping configuration */ - TIMx->OR = TIM_Remap; -} -/** - * @} - */ - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input and set the filter */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - - /* Select the Input and set the filter */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - - /* Select the Input and set the filter */ - tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - - /* Select the Input and set the filter */ - tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c deleted file mode 100644 index 6ae03e00f..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c +++ /dev/null @@ -1,1462 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_usart.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the Universal synchronous asynchronous receiver - * transmitter (USART): - * - Initialization and Configuration - * - Data transfers - * - Multi-Processor Communication - * - LIN mode - * - Half-duplex mode - * - Smartcard mode - * - IrDA mode - * - DMA transfers management - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable peripheral clock using the follwoing functions - * RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, UART4 or UART5. - * - * 2. According to the USART mode, enable the GPIO clocks using - * RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, - * or/and SCLK). - * - * 3. Peripheral's alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware - * flow control and Mode(Receiver/Transmitter) using the USART_Init() - * function. - * - * 5. For synchronous mode, enable the clock and program the polarity, - * phase and last bit using the USART_ClockInit() function. - * - * 5. Enable the NVIC and the corresponding interrupt using the function - * USART_ITConfig() if you need to use interrupt mode. - * - * 6. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using USART_DMACmd() function - * - * 7. Enable the USART using the USART_Cmd() function. - * - * 8. Enable the DMA using the DMA_Cmd() function, when using DMA mode. - * - * Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections - * for more details - * - * In order to reach higher communication baudrates, it is possible to - * enable the oversampling by 8 mode using the function USART_OverSampling8Cmd(). - * This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd()) - * and before calling the function USART_Init(). - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_usart.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup USART - * @brief USART driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */ -#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \ - USART_CR1_PS | USART_CR1_TE | \ - USART_CR1_RE)) - -/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */ -#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ - USART_CR2_CPHA | USART_CR2_LBCL)) - -/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */ -#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE)) - -/*!< USART Interrupts mask */ -#define IT_MASK ((uint16_t)0x001F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup USART_Private_Functions - * @{ - */ - -/** @defgroup USART_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - - For the asynchronous mode only these parameters can be configured: - - Baud Rate - - Word Length - - Stop Bit - - Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - - Hardware flow control - - Receiver/transmitter modes - - The USART_Init() function follows the USART asynchronous configuration procedure - (details for the procedure are available in reference manual (RM0090)). - - - For the synchronous mode in addition to the asynchronous mode parameters these - parameters should be also configured: - - USART Clock Enabled - - USART polarity - - USART phase - - USART LastBit - - These parameters can be configured using the USART_ClockInit() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @retval None - */ -void USART_DeInit(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - if (USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if (USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if (USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if (USARTx == UART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - } - else if (USARTx == UART5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); - } - else - { - if (USARTx == USART6) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); - } - } -} - -/** - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains - * the configuration information for the specified USART peripheral. - * @retval None - */ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - RCC_ClocksTypeDef RCC_ClocksStatus; - - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - - /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ - if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - - /* Clear STOP[13:12] bits */ - tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); - - /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit : - Set STOP[13:12] bits according to USART_StopBits value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; - -/*---------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = USARTx->CR1; - - /* Clear M, PCE, PS, TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); - - /* Configure the USART Word Length, Parity and mode: - Set the M bits according to USART_WordLength value - Set PCE and PS bits according to USART_Parity value - Set TE and RE bits according to USART_Mode value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - - /* Write to USART CR1 */ - USARTx->CR1 = (uint16_t)tmpreg; - -/*---------------------------- USART CR3 Configuration -----------------------*/ - tmpreg = USARTx->CR3; - - /* Clear CTSE and RTSE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); - - /* Configure the USART HFC : - Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - - /* Write to USART CR3 */ - USARTx->CR3 = (uint16_t)tmpreg; - -/*---------------------------- USART BRR Configuration -----------------------*/ - /* Configure the USART Baud Rate */ - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if ((USARTx == USART1) || (USARTx == USART6)) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - /* Determine the integer part */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ - { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - /* Determine the fractional part */ - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - /* Implement the fractional part in the register */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - /* Write to USART BRR register */ - USARTx->BRR = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_InitStruct member with its default value. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void USART_StructInit(USART_InitTypeDef* USART_InitStruct) -{ - /* USART_InitStruct members default value */ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No ; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/** - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that - * contains the configuration information for the specified USART peripheral. - * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. - * @retval None - */ -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear CLKEN, CPOL, CPHA and LBCL bits */ - tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); - /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ - /* Set CLKEN bit according to USART_Clock value */ - /* Set CPOL bit according to USART_CPOL value */ - /* Set CPHA bit according to USART_CPHA value */ - /* Set LBCL bit according to USART_LastBit value */ - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_ClockInitStruct member with its default value. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure - * which will be initialized. - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - /* USART_ClockInitStruct members default value */ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/** - * @brief Enables or disables the specified USART peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART by setting the UE bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_UE; - } - else - { - /* Disable the selected USART by clearing the UE bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE); - } -} - -/** - * @brief Sets the system clock prescaler. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_Prescaler: specifies the prescaler clock. - * @note The function is used for IrDA mode with UART4 and UART5. - * @retval None - */ -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART prescaler */ - USARTx->GTPR &= USART_GTPR_GT; - /* Set the USART prescaler */ - USARTx->GTPR |= USART_Prescaler; -} - -/** - * @brief Enables or disables the USART's 8x oversampling mode. - * @note This function has to be called before calling USART_Init() function - * in order to have correct baudrate Divider value. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART 8x oversampling mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_OVER8; - } - else - { - /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8); - } -} - -/** - * @brief Enables or disables the USART's one bit sampling method. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_ONEBIT; - } - else - { - /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - Data transfers functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART data - transfers. - - During an USART reception, data shifts in least significant bit first through - the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) - between the internal bus and the received shift register. - - When a transmission is taking place, a write instruction to the USART_DR register - stores the data in the TDR register and which is copied in the shift register - at the end of the current transmission. - - The read access of the USART_DR register can be done using the USART_ReceiveData() - function and returns the RDR buffered value. Whereas a write access to the USART_DR - can be done using USART_SendData() function and stores the written data into - TDR buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param Data: the data to transmit. - * @retval None - */ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DATA(Data)); - - /* Transmit Data */ - USARTx->DR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @retval The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Receive Data */ - return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); -} - -/** - * @} - */ - -/** @defgroup USART_Group3 MultiProcessor Communication functions - * @brief Multi-Processor Communication functions - * -@verbatim - =============================================================================== - Multi-Processor Communication functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - multiprocessor communication. - - For instance one of the USARTs can be the master, its TX output is connected to - the RX input of the other USART. The others are slaves, their respective TX outputs - are logically ANDed together and connected to the RX input of the master. - - USART multiprocessor communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter - or Mode receiver and hardware flow control values using the USART_Init() - function. - 2. Configures the USART address using the USART_SetAddress() function. - 3. Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) - using USART_WakeUpConfig() function only for the slaves. - 4. Enable the USART using the USART_Cmd() function. - 5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. - - The USART Slave exit from mute mode when receive the wake up condition. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the address of the USART node. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_ADDRESS(USART_Address)); - - /* Clear the USART address */ - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD); - /* Set the USART address node */ - USARTx->CR2 |= USART_Address; -} - -/** - * @brief Determines if the USART is in mute mode or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_RWU; - } - else - { - /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU); - } -} -/** - * @brief Selects the USART WakeUp method. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_WakeUp: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - * @retval None - */ -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_WAKEUP(USART_WakeUp)); - - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE); - USARTx->CR1 |= USART_WakeUp; -} - -/** - * @} - */ - -/** @defgroup USART_Group4 LIN mode functions - * @brief LIN mode functions - * -@verbatim - =============================================================================== - LIN mode functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART LIN - Mode communication. - - In LIN mode, 8-bit data format with 1 stop bit is required in accordance with - the LIN standard. - - Only this LIN Feature is supported by the USART IP: - - LIN Master Synchronous Break send capability and LIN slave break detection - capability : 13-bit break generation and 10/11 bit break detection - - - USART LIN Master transmitter communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - 2. Enable the USART using the USART_Cmd() function. - 3. Enable the LIN mode using the USART_LINCmd() function. - 4. Send the break character using USART_SendBreak() function. - - USART LIN Master receiver communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - 2. Enable the USART using the USART_Cmd() function. - 3. Configures the break detection length using the USART_LINBreakDetectLengthConfig() - function. - 4. Enable the LIN mode using the USART_LINCmd() function. - - -@note In LIN mode, the following bits must be kept cleared: - - CLKEN in the USART_CR2 register, - - STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the USART LIN Break detection length. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_LINBreakDetectLength: specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg USART_LINBreakDetectLength_10b: 10-bit break detection - * @arg USART_LINBreakDetectLength_11b: 11-bit break detection - * @retval None - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); - - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL); - USARTx->CR2 |= USART_LINBreakDetectLength; -} - -/** - * @brief Enables or disables the USART's LIN mode. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART LIN mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - USARTx->CR2 |= USART_CR2_LINEN; - } - else - { - /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN); - } -} - -/** - * @brief Transmits break characters. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @retval None - */ -void USART_SendBreak(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Send break characters */ - USARTx->CR1 |= USART_CR1_SBK; -} - -/** - * @} - */ - -/** @defgroup USART_Group5 Halfduplex mode function - * @brief Half-duplex mode function - * -@verbatim - =============================================================================== - Half-duplex mode function - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - Half-duplex communication. - - The USART can be configured to follow a single-wire half-duplex protocol where - the TX and RX lines are internally connected. - - USART Half duplex communication is possible through the following procedure: - 1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter - or Mode receiver and hardware flow control values using the USART_Init() - function. - 2. Configures the USART address using the USART_SetAddress() function. - 3. Enable the USART using the USART_Cmd() function. - 4. Enable the half duplex mode using USART_HalfDuplexCmd() function. - - -@note The RX pin is no longer used -@note In Half-duplex mode the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register. - - SCEN and IREN bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's Half Duplex communication. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART Communication. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_HDSEL; - } - else - { - /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL); - } -} - -/** - * @} - */ - - -/** @defgroup USART_Group6 Smartcard mode functions - * @brief Smartcard mode functions - * -@verbatim - =============================================================================== - Smartcard mode functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - Smartcard communication. - - The Smartcard interface is designed to support asynchronous protocol Smartcards as - defined in the ISO 7816-3 standard. - - The USART can provide a clock to the smartcard through the SCLK output. - In smartcard mode, SCLK is not associated to the communication but is simply derived - from the internal peripheral input clock through a 5-bit prescaler. - - Smartcard communication is possible through the following procedure: - 1. Configures the Smartcard Prescaler using the USART_SetPrescaler() function. - 2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function. - 3. Program the USART clock using the USART_ClockInit() function as following: - - USART Clock enabled - - USART CPOL Low - - USART CPHA on first edge - - USART Last Bit Clock Enabled - 4. Program the Smartcard interface using the USART_Init() function as following: - - Word Length = 9 Bits - - 1.5 Stop Bit - - Even parity - - BaudRate = 12096 baud - - Hardware flow control disabled (RTS and CTS signals) - - Tx and Rx enabled - 5. Optionally you can enable the parity error interrupt using the USART_ITConfig() - function - 6. Enable the USART using the USART_Cmd() function. - 7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function. - 8. Enable the Smartcard interface using the USART_SmartCardCmd() function. - - Please refer to the ISO 7816-3 specification for more details. - - -@note It is also possible to choose 0.5 stop bit for receiving but it is recommended - to use 1.5 stop bits for both transmitting and receiving to avoid switching - between the two configurations. -@note In smartcard mode, the following bits must be kept cleared: - - LINEN bit in the USART_CR2 register. - - HDSEL and IREN bits in the USART_CR3 register. -@note Smartcard mode is available on USART peripherals only (not available on UART4 - and UART5 peripherals). - -@endverbatim - * @{ - */ - -/** - * @brief Sets the specified USART guard time. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param USART_GuardTime: specifies the guard time. - * @retval None - */ -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - - /* Clear the USART Guard time */ - USARTx->GTPR &= USART_GTPR_PSC; - /* Set the USART guard time */ - USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/** - * @brief Enables or disables the USART's Smart Card mode. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_SCEN; - } - else - { - /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN); - } -} - -/** - * @brief Enables or disables NACK transmission. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the NACK transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_NACK; - } - else - { - /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group7 IrDA mode functions - * @brief IrDA mode functions - * -@verbatim - =============================================================================== - IrDA mode functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - IrDA communication. - - IrDA is a half duplex communication protocol. If the Transmitter is busy, any data - on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver - is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. - While receiving data, transmission should be avoided as the data to be transmitted - could be corrupted. - - IrDA communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver - modes and hardware flow control values using the USART_Init() function. - 2. Enable the USART using the USART_Cmd() function. - 3. Configures the IrDA pulse width by configuring the prescaler using - the USART_SetPrescaler() function. - 4. Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode - using the USART_IrDAConfig() function. - 5. Enable the IrDA using the USART_IrDACmd() function. - -@note A pulse of width less than two and greater than one PSC period(s) may or may - not be rejected. -@note The receiver set up time should be managed by software. The IrDA physical layer - specification specifies a minimum of 10 ms delay between transmission and - reception (IrDA is a half duplex protocol). -@note In IrDA mode, the following bits must be kept cleared: - - LINEN, STOP and CLKEN bits in the USART_CR2 register. - - SCEN and HDSEL bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the USART's IrDA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_IrDAMode: specifies the IrDA mode. - * This parameter can be one of the following values: - * @arg USART_IrDAMode_LowPower - * @arg USART_IrDAMode_Normal - * @retval None - */ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); - - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP); - USARTx->CR3 |= USART_IrDAMode; -} - -/** - * @brief Enables or disables the USART's IrDA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the IrDA mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_IREN; - } - else - { - /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group8 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's DMA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_DMAReq: specifies the DMA request. - * This parameter can be any combination of the following values: - * @arg USART_DMAReq_Tx: USART DMA transmit request - * @arg USART_DMAReq_Rx: USART DMA receive request - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DMAREQ(USART_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA transfer for selected requests by setting the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 |= USART_DMAReq; - } - else - { - /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 &= (uint16_t)~USART_DMAReq; - } -} - -/** - * @} - */ - -/** @defgroup USART_Group9 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This subsection provides a set of functions allowing to configure the USART - Interrupts sources, DMA channels requests and check or clear the flags or - pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - Polling Mode - ============= - In Polling Mode, the SPI communication can be managed by 10 flags: - 1. USART_FLAG_TXE : to indicate the status of the transmit buffer register - 2. USART_FLAG_RXNE : to indicate the status of the receive buffer register - 3. USART_FLAG_TC : to indicate the status of the transmit operation - 4. USART_FLAG_IDLE : to indicate the status of the Idle Line - 5. USART_FLAG_CTS : to indicate the status of the nCTS input - 6. USART_FLAG_LBD : to indicate the status of the LIN break detection - 7. USART_FLAG_NE : to indicate if a noise error occur - 8. USART_FLAG_FE : to indicate if a frame error occur - 9. USART_FLAG_PE : to indicate if a parity error occur - 10. USART_FLAG_ORE : to indicate if an Overrun error occur - - In this Mode it is advised to use the following functions: - - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); - - void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); - - Interrupt Mode - =============== - In Interrupt Mode, the USART communication can be managed by 8 interrupt sources - and 10 pending bits: - - Pending Bits: - ------------- - 1. USART_IT_TXE : to indicate the status of the transmit buffer register - 2. USART_IT_RXNE : to indicate the status of the receive buffer register - 3. USART_IT_TC : to indicate the status of the transmit operation - 4. USART_IT_IDLE : to indicate the status of the Idle Line - 5. USART_IT_CTS : to indicate the status of the nCTS input - 6. USART_IT_LBD : to indicate the status of the LIN break detection - 7. USART_IT_NE : to indicate if a noise error occur - 8. USART_IT_FE : to indicate if a frame error occur - 9. USART_IT_PE : to indicate if a parity error occur - 10. USART_IT_ORE : to indicate if an Overrun error occur - - Interrupt Source: - ----------------- - 1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty - interrupt. - 2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - 3. USART_IT_TC : specifies the interrupt source for the Transmit complete - interrupt. - 4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. - 5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt. - 6. USART_IT_LBD : specifies the interrupt source for the LIN break detection - interrupt. - 7. USART_IT_PE : specifies the interrupt source for the parity error interrupt. - 8. USART_IT_ERR : specifies the interrupt source for the errors interrupt. - -@note Some parameters are coded in order to use them as interrupt source or as pending bits. - - In this Mode it is advised to use the following functions: - - void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); - - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); - - void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - - DMA Mode - ======== - In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: - 1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request - 2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request - - In this Mode it is advised to use the following function: - - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified USART interrupts. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param NewState: new state of the specified USARTx interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CONFIG_IT(USART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - - /* Get the interrupt position */ - itpos = USART_IT & IT_MASK; - itmask = (((uint32_t)0x01) << itpos); - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - usartxbase += 0x0C; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - usartxbase += 0x10; - } - else /* The IT is in CR3 register */ - { - usartxbase += 0x14; - } - if (NewState != DISABLE) - { - *(__IO uint32_t*)usartxbase |= itmask; - } - else - { - *(__IO uint32_t*)usartxbase &= ~itmask; - } -} - -/** - * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TXE: Transmit data register empty flag - * @arg USART_FLAG_TC: Transmission Complete flag - * @arg USART_FLAG_RXNE: Receive data register not empty flag - * @arg USART_FLAG_IDLE: Idle Line detection flag - * @arg USART_FLAG_ORE: OverRun Error flag - * @arg USART_FLAG_NE: Noise Error flag - * @arg USART_FLAG_FE: Framing Error flag - * @arg USART_FLAG_PE: Parity Error flag - * @retval The new state of USART_FLAG (SET or RESET). - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_FLAG(USART_FLAG)); - - /* The CTS flag is not available for UART4 and UART5 */ - if (USART_FLAG == USART_FLAG_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the USARTx's pending flags. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). - * @arg USART_FLAG_LBD: LIN Break detection flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DR register (USART_ReceiveData()). - * @note RXNE flag can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * @note TC flag can be also cleared by software sequence: a read operation to - * USART_SR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DR register (USART_SendData()). - * @note TXE flag is cleared only by a write to the USART_DR register - * (USART_SendData()). - * - * @retval None - */ -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - - /* The CTS flag is not available for UART4 and UART5 */ - if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - USARTx->SR = (uint16_t)~USART_FLAG; -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ORE: OverRun Error interrupt - * @arg USART_IT_NE: Noise Error interrupt - * @arg USART_IT_FE: Framing Error interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @retval The new state of USART_IT (SET or RESET). - */ -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_GET_IT(USART_IT)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - /* Get the interrupt position */ - itmask = USART_IT & IT_MASK; - itmask = (uint32_t)0x01 << itmask; - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - itmask &= USARTx->CR1; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - itmask &= USARTx->CR2; - } - else /* The IT is in CR3 register */ - { - itmask &= USARTx->CR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->SR; - if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Clears the USARTx's interrupt pending bits. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_SR register - * (USART_GetITStatus()) followed by a read operation to USART_DR register - * (USART_ReceiveData()). - * @note RXNE pending bit can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * @note TC pending bit can be also cleared by software sequence: a read - * operation to USART_SR register (USART_GetITStatus()) followed by a write - * operation to USART_DR register (USART_SendData()). - * @note TXE pending bit is cleared only by a write to the USART_DR register - * (USART_SendData()). - * - * @retval None - */ -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_IT(USART_IT)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->SR = (uint16_t)~itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c b/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c deleted file mode 100644 index 3491c6d88..000000000 --- a/example/stm32f4/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c +++ /dev/null @@ -1,303 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_wwdg.c - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 25-August-2011 - * @brief This file provides firmware functions to manage the following - * functionalities of the Window watchdog (WWDG) peripheral: - * - Prescaler, Refresh window and Counter configuration - * - WWDG activation - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * WWDG features - * =================================================================== - * - * Once enabled the WWDG generates a system reset on expiry of a programmed - * time period, unless the program refreshes the counter (downcounter) - * before to reach 0x3F value (i.e. a reset is generated when the counter - * value rolls over from 0x40 to 0x3F). - * An MCU reset is also generated if the counter value is refreshed - * before the counter has reached the refresh window value. This - * implies that the counter must be refreshed in a limited window. - * - * Once enabled the WWDG cannot be disabled except by a system reset. - * - * WWDGRST flag in RCC_CSR register can be used to inform when a WWDG - * reset occurs. - * - * The WWDG counter input clock is derived from the APB clock divided - * by a programmable prescaler. - * - * WWDG counter clock = PCLK1 / Prescaler - * WWDG timeout = (WWDG counter clock) * (counter value) - * - * Min-max timeout value @30 MHz(PCLK1): ~136.5 us / ~69.9 ms - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function - * - * 2. Configure the WWDG prescaler using WWDG_SetPrescaler() function - * - * 3. Configure the WWDG refresh window using WWDG_SetWindowValue() function - * - * 4. Set the WWDG counter value and start it using WWDG_Enable() function. - * When the WWDG is enabled the counter value should be configured to - * a value greater than 0x40 to prevent generating an immediate reset. - * - * 5. Optionally you can enable the Early wakeup interrupt which is - * generated when the counter reach 0x40. - * Once enabled this interrupt cannot be disabled except by a system reset. - * - * 6. Then the application program must refresh the WWDG counter at regular - * intervals during normal operation to prevent an MCU reset, using - * WWDG_SetCounter() function. This operation must occur only when - * the counter value is lower than the refresh window value, - * programmed using WWDG_SetWindowValue(). - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_wwdg.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup WWDG - * @brief WWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ----------- WWDG registers bit address in the alias region ----------- */ -#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) -/* Alias word address of EWI bit */ -#define CFR_OFFSET (WWDG_OFFSET + 0x04) -#define EWI_BitNumber 0x09 -#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) - -/* --------------------- WWDG registers bit mask ------------------------ */ -/* CFR register bit mask */ -#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) -#define CFR_W_MASK ((uint32_t)0xFFFFFF80) -#define BIT_MASK ((uint8_t)0x7F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup WWDG_Private_Functions - * @{ - */ - -/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions - * @brief Prescaler, Refresh window and Counter configuration functions - * -@verbatim - =============================================================================== - Prescaler, Refresh window and Counter configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the WWDG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/** - * @brief Sets the WWDG Prescaler. - * @param WWDG_Prescaler: specifies the WWDG Prescaler. - * This parameter can be one of the following values: - * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 - * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 - * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 - * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 - * @retval None - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); - /* Clear WDGTB[1:0] bits */ - tmpreg = WWDG->CFR & CFR_WDGTB_MASK; - /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ - tmpreg |= WWDG_Prescaler; - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Sets the WWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * This parameter value must be lower than 0x80. - * @retval None - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); - /* Clear W[6:0] bits */ - - tmpreg = WWDG->CFR & CFR_W_MASK; - - /* Set W[6:0] bits according to WindowValue value */ - tmpreg |= WindowValue & (uint32_t) BIT_MASK; - - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Enables the WWDG Early Wakeup interrupt(EWI). - * @note Once enabled this interrupt cannot be disabled except by a system reset. - * @param None - * @retval None - */ -void WWDG_EnableIT(void) -{ - *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; -} - -/** - * @brief Sets the WWDG counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent generating - * an immediate reset) - * @retval None - */ -void WWDG_SetCounter(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to T[6:0] bits to configure the counter value, no need to do - a read-modify-write; writing a 0 to WDGA bit does nothing */ - WWDG->CR = Counter & BIT_MASK; -} -/** - * @} - */ - -/** @defgroup WWDG_Group2 WWDG activation functions - * @brief WWDG activation functions - * -@verbatim - =============================================================================== - WWDG activation function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables WWDG and load the counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent generating - * an immediate reset) - * @retval None - */ -void WWDG_Enable(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - WWDG->CR = WWDG_CR_WDGA | Counter; -} -/** - * @} - */ - -/** @defgroup WWDG_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the Early Wakeup interrupt flag is set or not. - * @param None - * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((WWDG->SR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears Early Wakeup interrupt flag. - * @param None - * @retval None - */ -void WWDG_ClearFlag(void) -{ - WWDG->SR = (uint32_t)RESET; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h b/example/stm32f4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h deleted file mode 100644 index f58ff0601..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h +++ /dev/null @@ -1,158 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_audio_core.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief header file for the usbd_audio_core.c file. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#ifndef __USB_AUDIO_CORE_H_ -#define __USB_AUDIO_CORE_H_ - -#include "usbd_ioreq.h" -#include "usbd_req.h" -#include "usbd_desc.h" - - - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup usbd_audio - * @brief This file is the Header file for USBD_audio.c - * @{ - */ - - -/** @defgroup usbd_audio_Exported_Defines - * @{ - */ - -/* AudioFreq * DataSize (2 bytes) * NumChannels (Stereo: 2) */ -#define AUDIO_OUT_PACKET (uint32_t)(((USBD_AUDIO_FREQ * 2 * 2) /1000)) - -/* Number of sub-packets in the audio transfer buffer. You can modify this value but always make sure - that it is an even number and higher than 3 */ -#define OUT_PACKET_NUM 4 -/* Total size of the audio transfer buffer */ -#define TOTAL_OUT_BUF_SIZE ((uint32_t)(AUDIO_OUT_PACKET * OUT_PACKET_NUM)) - -#define AUDIO_CONFIG_DESC_SIZE 109 -#define AUDIO_INTERFACE_DESC_SIZE 9 -#define USB_AUDIO_DESC_SIZ 0x09 -#define AUDIO_STANDARD_ENDPOINT_DESC_SIZE 0x09 -#define AUDIO_STREAMING_ENDPOINT_DESC_SIZE 0x07 - -#define AUDIO_DESCRIPTOR_TYPE 0x21 -#define USB_DEVICE_CLASS_AUDIO 0x01 -#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01 -#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02 -#define AUDIO_PROTOCOL_UNDEFINED 0x00 -#define AUDIO_STREAMING_GENERAL 0x01 -#define AUDIO_STREAMING_FORMAT_TYPE 0x02 - -/* Audio Descriptor Types */ -#define AUDIO_INTERFACE_DESCRIPTOR_TYPE 0x24 -#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE 0x25 - -/* Audio Control Interface Descriptor Subtypes */ -#define AUDIO_CONTROL_HEADER 0x01 -#define AUDIO_CONTROL_INPUT_TERMINAL 0x02 -#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03 -#define AUDIO_CONTROL_FEATURE_UNIT 0x06 - -#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0C -#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09 -#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07 - -#define AUDIO_CONTROL_MUTE 0x0001 - -#define AUDIO_FORMAT_TYPE_I 0x01 -#define AUDIO_FORMAT_TYPE_III 0x03 - -#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01 -#define AUDIO_ENDPOINT_GENERAL 0x01 - -#define AUDIO_REQ_GET_CUR 0x81 -#define AUDIO_REQ_SET_CUR 0x01 - -#define AUDIO_OUT_STREAMING_CTRL 0x02 - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ -typedef struct _Audio_Fops -{ - uint8_t (*Init) (uint32_t AudioFreq, uint32_t Volume, uint32_t options); - uint8_t (*DeInit) (uint32_t options); - uint8_t (*AudioCmd) (uint8_t* pbuf, uint32_t size, uint8_t cmd); - uint8_t (*VolumeCtl) (uint8_t vol); - uint8_t (*MuteCtl) (uint8_t cmd); - uint8_t (*PeriodicTC) (uint8_t cmd); - uint8_t (*GetState) (void); -}AUDIO_FOPS_TypeDef; -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ -#define AUDIO_PACKET_SZE(frq) (uint8_t)(((frq * 2 * 2)/1000) & 0xFF), \ - (uint8_t)((((frq * 2 * 2)/1000) >> 8) & 0xFF) -#define SAMPLE_FREQ(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16)) -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern USBD_Class_cb_TypeDef AUDIO_cb; - -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -/** - * @} - */ - -#endif // __USB_AUDIO_CORE_H_ -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_out_if.h b/example/stm32f4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_out_if.h deleted file mode 100644 index a6b53fa83..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_out_if.h +++ /dev/null @@ -1,117 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_audio_out_if.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief header file for the usbd_audio_out_if.c file. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#ifndef __USB_AUDIO_OUT_IF_H_ -#define __USB_AUDIO_OUT_IF_H_ - -#ifdef STM32F2XX - #include "stm322xg_usb_audio_codec.h" -#elif defined(STM32F10X_CL) - #include "stm3210c_usb_audio_codec.h" -#endif /* STM32F2XX */ - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup usbd_audio - * @brief This file is the Header file for USBD_audio.c - * @{ - */ - - -/** @defgroup usbd_audio_Exported_Defines - * @{ - */ -/* Audio Commands enmueration */ -typedef enum -{ - AUDIO_CMD_PLAY = 1, - AUDIO_CMD_PAUSE, - AUDIO_CMD_STOP, -}AUDIO_CMD_TypeDef; - -/* Mute commands */ -#define AUDIO_MUTE 0x01 -#define AUDIO_UNMUTE 0x00 - -/* Functions return value */ -#define AUDIO_OK 0x00 -#define AUDIO_FAIL 0xFF - -/* Audio Machine States */ -#define AUDIO_STATE_INACTIVE 0x00 -#define AUDIO_STATE_ACTIVE 0x01 -#define AUDIO_STATE_PLAYING 0x02 -#define AUDIO_STATE_PAUSED 0x03 -#define AUDIO_STATE_STOPPED 0x04 -#define AUDIO_STATE_ERROR 0x05 - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern AUDIO_FOPS_TypeDef AUDIO_OUT_fops; - -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -/** - * @} - */ - -#endif /* __USB_AUDIO_OUT_IF_H_ */ -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/audio/src/usbd_audio_core.c b/example/stm32f4/STM32_USB_Device_Library/Class/audio/src/usbd_audio_core.c deleted file mode 100644 index b26f574a3..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/audio/src/usbd_audio_core.c +++ /dev/null @@ -1,665 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_audio_core.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief This file provides the high layer firmware functions to manage the - * following functionalities of the USB Audio Class: - * - Initialization and Configuration of high and low layer - * - Enumeration as Audio Streaming Device - * - Audio Streaming data transfer - * - AudioControl requests management - * - Error management - * - * @verbatim - * - * =================================================================== - * Audio Class Driver Description - * =================================================================== - * This driver manages the Audio Class 1.0 following the "USB Device Class Definition for - * Audio Devices V1.0 Mar 18, 98". - * This driver implements the following aspects of the specification: - * - Device descriptor management - * - Configuration descriptor management - * - Standard AC Interface Descriptor management - * - 1 Audio Streaming Interface (with single channel, PCM, Stereo mode) - * - 1 Audio Streaming Endpoint - * - 1 Audio Terminal Input (1 channel) - * - Audio Class-Specific AC Interfaces - * - Audio Class-Specific AS Interfaces - * - AudioControl Requests: only SET_CUR and GET_CUR requests are supported (for Mute) - * - Audio Feature Unit (limited to Mute control) - * - Audio Synchronization type: Asynchronous - * - Single fixed audio sampling rate (configurable in usbd_conf.h file) - * - * @note - * The Audio Class 1.0 is based on USB Specification 1.0 and thus supports only - * Low and Full speed modes and does not allow High Speed transfers. - * Please refer to "USB Device Class Definition for Audio Devices V1.0 Mar 18, 98" - * for more details. - * - * These aspects may be enriched or modified for a specific user application. - * - * This driver doesn't implement the following aspects of the specification - * (but it is possible to manage these features with some modifications on this driver): - * - AudioControl Endpoint management - * - AudioControl requsests other than SET_CUR and GET_CUR - * - Abstraction layer for AudioControl requests (only Mute functionality is managed) - * - Audio Synchronization type: Adaptive - * - Audio Compression modules and interfaces - * - MIDI interfaces and modules - * - Mixer/Selector/Processing/Extension Units (Feature unit is limited to Mute control) - * - Any other application-specific modules - * - Multiple and Variable audio sampling rates - * - Out Streaming Endpoint/Interface (microphone) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#include "usbd_audio_core.h" -#include "usbd_audio_out_if.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup usbd_audio - * @brief usbd core module - * @{ - */ - -/** @defgroup usbd_audio_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_audio_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_audio_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_audio_Private_FunctionPrototypes - * @{ - */ - -/********************************************* - AUDIO Device library callbacks - *********************************************/ -static uint8_t usbd_audio_Init (void *pdev, uint8_t cfgidx); -static uint8_t usbd_audio_DeInit (void *pdev, uint8_t cfgidx); -static uint8_t usbd_audio_Setup (void *pdev, USB_SETUP_REQ *req); -static uint8_t usbd_audio_EP0_RxReady(void *pdev); -static uint8_t usbd_audio_DataIn (void *pdev, uint8_t epnum); -static uint8_t usbd_audio_DataOut (void *pdev, uint8_t epnum); -static uint8_t usbd_audio_SOF (void *pdev); -static uint8_t usbd_audio_OUT_Incplt (void *pdev); - -/********************************************* - AUDIO Requests management functions - *********************************************/ -static void AUDIO_Req_GetCurrent(void *pdev, USB_SETUP_REQ *req); -static void AUDIO_Req_SetCurrent(void *pdev, USB_SETUP_REQ *req); -static uint8_t *USBD_audio_GetCfgDesc (uint8_t speed, uint16_t *length); -/** - * @} - */ - -/** @defgroup usbd_audio_Private_Variables - * @{ - */ -/* Main Buffer for Audio Data Out transfers and its relative pointers */ -uint8_t IsocOutBuff [TOTAL_OUT_BUF_SIZE * 2]; -uint8_t* IsocOutWrPtr = IsocOutBuff; -uint8_t* IsocOutRdPtr = IsocOutBuff; - -/* Main Buffer for Audio Control Rrequests transfers and its relative variables */ -uint8_t AudioCtl[64]; -uint8_t AudioCtlCmd = 0; -uint32_t AudioCtlLen = 0; -uint8_t AudioCtlUnit = 0; - -static uint32_t PlayFlag = 0; - -static __IO uint32_t usbd_audio_AltSet = 0; -static uint8_t usbd_audio_CfgDesc[AUDIO_CONFIG_DESC_SIZE]; - -/* AUDIO interface class callbacks structure */ -USBD_Class_cb_TypeDef AUDIO_cb = -{ - usbd_audio_Init, - usbd_audio_DeInit, - usbd_audio_Setup, - NULL, /* EP0_TxSent */ - usbd_audio_EP0_RxReady, - usbd_audio_DataIn, - usbd_audio_DataOut, - usbd_audio_SOF, - NULL, - usbd_audio_OUT_Incplt, - USBD_audio_GetCfgDesc, -#ifdef USB_OTG_HS_CORE - USBD_audio_GetCfgDesc, /* use same config as per FS */ -#endif -}; - -/* USB AUDIO device Configuration Descriptor */ -static uint8_t usbd_audio_CfgDesc[AUDIO_CONFIG_DESC_SIZE] = -{ - /* Configuration 1 */ - 0x09, /* bLength */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */ - LOBYTE(AUDIO_CONFIG_DESC_SIZE), /* wTotalLength 109 bytes*/ - HIBYTE(AUDIO_CONFIG_DESC_SIZE), - 0x02, /* bNumInterfaces */ - 0x01, /* bConfigurationValue */ - 0x00, /* iConfiguration */ - 0xC0, /* bmAttributes BUS Powred*/ - 0x32, /* bMaxPower = 100 mA*/ - /* 09 byte*/ - - /* USB Speaker Standard interface descriptor */ - AUDIO_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - 0x00, /* bInterfaceNumber */ - 0x00, /* bAlternateSetting */ - 0x00, /* bNumEndpoints */ - USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ - AUDIO_SUBCLASS_AUDIOCONTROL, /* bInterfaceSubClass */ - AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ - 0x00, /* iInterface */ - /* 09 byte*/ - - /* USB Speaker Class-specific AC Interface Descriptor */ - AUDIO_INTERFACE_DESC_SIZE, /* bLength */ - AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_CONTROL_HEADER, /* bDescriptorSubtype */ - 0x00, /* 1.00 */ /* bcdADC */ - 0x01, - 0x27, /* wTotalLength = 39*/ - 0x00, - 0x01, /* bInCollection */ - 0x01, /* baInterfaceNr */ - /* 09 byte*/ - - /* USB Speaker Input Terminal Descriptor */ - AUDIO_INPUT_TERMINAL_DESC_SIZE, /* bLength */ - AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_CONTROL_INPUT_TERMINAL, /* bDescriptorSubtype */ - 0x01, /* bTerminalID */ - 0x01, /* wTerminalType AUDIO_TERMINAL_USB_STREAMING 0x0101 */ - 0x01, - 0x00, /* bAssocTerminal */ - 0x01, /* bNrChannels */ - 0x00, /* wChannelConfig 0x0000 Mono */ - 0x00, - 0x00, /* iChannelNames */ - 0x00, /* iTerminal */ - /* 12 byte*/ - - /* USB Speaker Audio Feature Unit Descriptor */ - 0x09, /* bLength */ - AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_CONTROL_FEATURE_UNIT, /* bDescriptorSubtype */ - AUDIO_OUT_STREAMING_CTRL, /* bUnitID */ - 0x01, /* bSourceID */ - 0x01, /* bControlSize */ - AUDIO_CONTROL_MUTE, /* bmaControls(0) */ - 0x00, /* bmaControls(1) */ - 0x00, /* iTerminal */ - /* 09 byte*/ - - /*USB Speaker Output Terminal Descriptor */ - 0x09, /* bLength */ - AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_CONTROL_OUTPUT_TERMINAL, /* bDescriptorSubtype */ - 0x03, /* bTerminalID */ - 0x01, /* wTerminalType 0x0301*/ - 0x03, - 0x00, /* bAssocTerminal */ - 0x02, /* bSourceID */ - 0x00, /* iTerminal */ - /* 09 byte*/ - - /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Zero Bandwith */ - /* Interface 1, Alternate Setting 0 */ - AUDIO_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - 0x01, /* bInterfaceNumber */ - 0x00, /* bAlternateSetting */ - 0x00, /* bNumEndpoints */ - USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ - AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ - AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ - 0x00, /* iInterface */ - /* 09 byte*/ - - /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Operational */ - /* Interface 1, Alternate Setting 1 */ - AUDIO_INTERFACE_DESC_SIZE, /* bLength */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - 0x01, /* bInterfaceNumber */ - 0x01, /* bAlternateSetting */ - 0x01, /* bNumEndpoints */ - USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ - AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ - AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ - 0x00, /* iInterface */ - /* 09 byte*/ - - /* USB Speaker Audio Streaming Interface Descriptor */ - AUDIO_STREAMING_INTERFACE_DESC_SIZE, /* bLength */ - AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ - 0x01, /* bTerminalLink */ - 0x01, /* bDelay */ - 0x01, /* wFormatTag AUDIO_FORMAT_PCM 0x0001*/ - 0x00, - /* 07 byte*/ - - /* USB Speaker Audio Type III Format Interface Descriptor */ - 0x0B, /* bLength */ - AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ - AUDIO_FORMAT_TYPE_III, /* bFormatType */ - 0x02, /* bNrChannels */ - 0x02, /* bSubFrameSize : 2 Bytes per frame (16bits) */ - 16, /* bBitResolution (16-bits per sample) */ - 0x01, /* bSamFreqType only one frequency supported */ - SAMPLE_FREQ(USBD_AUDIO_FREQ), /* Audio sampling frequency coded on 3 bytes */ - /* 11 byte*/ - - /* Endpoint 1 - Standard Descriptor */ - AUDIO_STANDARD_ENDPOINT_DESC_SIZE, /* bLength */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_OUT_EP, /* bEndpointAddress 1 out endpoint*/ - USB_ENDPOINT_TYPE_ISOCHRONOUS, /* bmAttributes */ - AUDIO_PACKET_SZE(USBD_AUDIO_FREQ), /* wMaxPacketSize in Bytes (Freq(Samples)*2(Stereo)*2(HalfWord)) */ - 0x01, /* bInterval */ - 0x00, /* bRefresh */ - 0x00, /* bSynchAddress */ - /* 09 byte*/ - - /* Endpoint - Audio Streaming Descriptor*/ - AUDIO_STREAMING_ENDPOINT_DESC_SIZE, /* bLength */ - AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ - AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ - 0x00, /* bmAttributes */ - 0x00, /* bLockDelayUnits */ - 0x00, /* wLockDelay */ - 0x00, - /* 07 byte*/ -} ; - -/** - * @} - */ - -/** @defgroup usbd_audio_Private_Functions - * @{ - */ - -/** -* @brief usbd_audio_Init -* Initilaizes the AUDIO interface. -* @param pdev: device instance -* @param cfgidx: Configuration index -* @retval status -*/ -static uint8_t usbd_audio_Init (void *pdev, - uint8_t cfgidx) -{ - /* Open EP OUT */ - DCD_EP_Open(pdev, - AUDIO_OUT_EP, - AUDIO_OUT_PACKET, - USB_OTG_EP_ISOC); - - /* Initialize the Audio output Hardware layer */ - if (AUDIO_OUT_fops.Init(USBD_AUDIO_FREQ, DEFAULT_VOLUME, 0) != USBD_OK) - { - return USBD_FAIL; - } - - /* Prepare Out endpoint to receive audio data */ - DCD_EP_PrepareRx(pdev, - AUDIO_OUT_EP, - (uint8_t*)IsocOutBuff, - AUDIO_OUT_PACKET); - - return USBD_OK; -} - -/** -* @brief usbd_audio_Init -* DeInitializes the AUDIO layer. -* @param pdev: device instance -* @param cfgidx: Configuration index -* @retval status -*/ -static uint8_t usbd_audio_DeInit (void *pdev, - uint8_t cfgidx) -{ - DCD_EP_Close (pdev , AUDIO_OUT_EP); - - /* DeInitialize the Audio output Hardware layer */ - if (AUDIO_OUT_fops.DeInit(0) != USBD_OK) - { - return USBD_FAIL; - } - - return USBD_OK; -} - -/** - * @brief usbd_audio_Setup - * Handles the Audio control request parsing. - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t usbd_audio_Setup (void *pdev, - USB_SETUP_REQ *req) -{ - uint16_t len; - uint8_t *pbuf; - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - /* AUDIO Class Requests -------------------------------*/ - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) - { - case AUDIO_REQ_GET_CUR: - AUDIO_Req_GetCurrent(pdev, req); - break; - - case AUDIO_REQ_SET_CUR: - AUDIO_Req_SetCurrent(pdev, req); - break; - - default: - USBD_CtlError (pdev, req); - return USBD_FAIL; - } - break; - - /* Standard Requests -------------------------------*/ - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - if( (req->wValue >> 8) == AUDIO_DESCRIPTOR_TYPE) - { -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - pbuf = usbd_audio_Desc; -#else - pbuf = usbd_audio_CfgDesc + 18; -#endif - len = MIN(USB_AUDIO_DESC_SIZ , req->wLength); - } - - USBD_CtlSendData (pdev, - pbuf, - len); - break; - - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - (uint8_t *)&usbd_audio_AltSet, - 1); - break; - - case USB_REQ_SET_INTERFACE : - if ((uint8_t)(req->wValue) < AUDIO_TOTAL_IF_NUM) - { - usbd_audio_AltSet = (uint8_t)(req->wValue); - } - else - { - /* Call the error management function (command will be nacked */ - USBD_CtlError (pdev, req); - } - break; - } - } - return USBD_OK; -} - -/** - * @brief usbd_audio_EP0_RxReady - * Handles audio control requests data. - * @param pdev: device device instance - * @retval status - */ -static uint8_t usbd_audio_EP0_RxReady (void *pdev) -{ - /* Check if an AudioControl request has been issued */ - if (AudioCtlCmd == AUDIO_REQ_SET_CUR) - {/* In this driver, to simplify code, only SET_CUR request is managed */ - /* Check for which addressed unit the AudioControl request has been issued */ - if (AudioCtlUnit == AUDIO_OUT_STREAMING_CTRL) - {/* In this driver, to simplify code, only one unit is manage */ - /* Call the audio interface mute function */ - AUDIO_OUT_fops.MuteCtl(AudioCtl[0]); - - /* Reset the AudioCtlCmd variable to prevent re-entering this function */ - AudioCtlCmd = 0; - AudioCtlLen = 0; - } - } - - return USBD_OK; -} - -/** - * @brief usbd_audio_DataIn - * Handles the audio IN data stage. - * @param pdev: instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t usbd_audio_DataIn (void *pdev, uint8_t epnum) -{ - return USBD_OK; -} - -/** - * @brief usbd_audio_DataOut - * Handles the Audio Out data stage. - * @param pdev: instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t usbd_audio_DataOut (void *pdev, uint8_t epnum) -{ - if (epnum == AUDIO_OUT_EP) - { - /* Increment the Buffer pointer or roll it back when all buffers are full */ - if (IsocOutWrPtr >= (IsocOutBuff + (AUDIO_OUT_PACKET * OUT_PACKET_NUM))) - {/* All buffers are full: roll back */ - IsocOutWrPtr = IsocOutBuff; - } - else - {/* Increment the buffer pointer */ - IsocOutWrPtr += AUDIO_OUT_PACKET; - } - - /* Toggle the frame index */ - ((USB_OTG_CORE_HANDLE*)pdev)->dev.out_ep[epnum].even_odd_frame = - (((USB_OTG_CORE_HANDLE*)pdev)->dev.out_ep[epnum].even_odd_frame)? 0:1; - - /* Prepare Out endpoint to receive next audio packet */ - DCD_EP_PrepareRx(pdev, - AUDIO_OUT_EP, - (uint8_t*)(IsocOutWrPtr), - AUDIO_OUT_PACKET); - - /* Trigger the start of streaming only when half buffer is full */ - if ((PlayFlag == 0) && (IsocOutWrPtr >= (IsocOutBuff + ((AUDIO_OUT_PACKET * OUT_PACKET_NUM) / 2)))) - { - /* Enable start of Streaming */ - PlayFlag = 1; - } - } - - return USBD_OK; -} - -/** - * @brief usbd_audio_SOF - * Handles the SOF event (data buffer update and synchronization). - * @param pdev: instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t usbd_audio_SOF (void *pdev) -{ - /* Check if there are available data in stream buffer. - In this function, a single variable (PlayFlag) is used to avoid software delays. - The play operation must be executed as soon as possible after the SOF detection. */ - if (PlayFlag) - { - /* Start playing received packet */ - AUDIO_OUT_fops.AudioCmd((uint8_t*)(IsocOutRdPtr), /* Samples buffer pointer */ - AUDIO_OUT_PACKET, /* Number of samples in Bytes */ - AUDIO_CMD_PLAY); /* Command to be processed */ - - /* Increment the Buffer pointer or roll it back when all buffers all full */ - if (IsocOutRdPtr >= (IsocOutBuff + (AUDIO_OUT_PACKET * OUT_PACKET_NUM))) - {/* Roll back to the start of buffer */ - IsocOutRdPtr = IsocOutBuff; - } - else - {/* Increment to the next sub-buffer */ - IsocOutRdPtr += AUDIO_OUT_PACKET; - } - - /* If all available buffers have been consumed, stop playing */ - if (IsocOutRdPtr == IsocOutWrPtr) - { - /* Pause the audio stream */ - AUDIO_OUT_fops.AudioCmd((uint8_t*)(IsocOutBuff), /* Samples buffer pointer */ - AUDIO_OUT_PACKET, /* Number of samples in Bytes */ - AUDIO_CMD_PAUSE); /* Command to be processed */ - - /* Stop entering play loop */ - PlayFlag = 0; - - /* Reset buffer pointers */ - IsocOutRdPtr = IsocOutBuff; - IsocOutWrPtr = IsocOutBuff; - } - } - - return USBD_OK; -} - -/** - * @brief usbd_audio_OUT_Incplt - * Handles the iso out incomplete event. - * @param pdev: instance - * @retval status - */ -static uint8_t usbd_audio_OUT_Incplt (void *pdev) -{ - return USBD_OK; -} - -/****************************************************************************** - AUDIO Class requests management -******************************************************************************/ -/** - * @brief AUDIO_Req_GetCurrent - * Handles the GET_CUR Audio control request. - * @param pdev: instance - * @param req: setup class request - * @retval status - */ -static void AUDIO_Req_GetCurrent(void *pdev, USB_SETUP_REQ *req) -{ - /* Send the current mute state */ - USBD_CtlSendData (pdev, - AudioCtl, - req->wLength); -} - -/** - * @brief AUDIO_Req_SetCurrent - * Handles the SET_CUR Audio control request. - * @param pdev: instance - * @param req: setup class request - * @retval status - */ -static void AUDIO_Req_SetCurrent(void *pdev, USB_SETUP_REQ *req) -{ - if (req->wLength) - { - /* Prepare the reception of the buffer over EP0 */ - USBD_CtlPrepareRx (pdev, - AudioCtl, - req->wLength); - - /* Set the global variables indicating current request and its length - to the function usbd_audio_EP0_RxReady() which will process the request */ - AudioCtlCmd = AUDIO_REQ_SET_CUR; /* Set the request value */ - AudioCtlLen = req->wLength; /* Set the request data length */ - AudioCtlUnit = HIBYTE(req->wIndex); /* Set the request target unit */ - } -} - -/** - * @brief USBD_audio_GetCfgDesc - * Returns configuration descriptor. - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_audio_GetCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (usbd_audio_CfgDesc); - return usbd_audio_CfgDesc; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/audio/src/usbd_audio_out_if.c b/example/stm32f4/STM32_USB_Device_Library/Class/audio/src/usbd_audio_out_if.c deleted file mode 100644 index 21d98394f..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/audio/src/usbd_audio_out_if.c +++ /dev/null @@ -1,318 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_audio_out_if.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief This file provides the Audio Out (palyback) interface API. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_audio_core.h" -#include "usbd_audio_out_if.h" - - - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup usbd_audio_out_if - * @brief usbd out interface module - * @{ - */ - -/** @defgroup usbd_audio_out_if_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_audio_out_if_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_audio_out_if_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_audio_out_if_Private_FunctionPrototypes - * @{ - */ -static uint8_t Init (uint32_t AudioFreq, uint32_t Volume, uint32_t options); -static uint8_t DeInit (uint32_t options); -static uint8_t AudioCmd (uint8_t* pbuf, uint32_t size, uint8_t cmd); -static uint8_t VolumeCtl (uint8_t vol); -static uint8_t MuteCtl (uint8_t cmd); -static uint8_t PeriodicTC (uint8_t cmd); -static uint8_t GetState (void); - -/** - * @} - */ - -/** @defgroup usbd_audio_out_if_Private_Variables - * @{ - */ -AUDIO_FOPS_TypeDef AUDIO_OUT_fops = -{ - Init, - DeInit, - AudioCmd, - VolumeCtl, - MuteCtl, - PeriodicTC, - GetState -}; - -static uint8_t AudioState = AUDIO_STATE_INACTIVE; - -/** - * @} - */ - -/** @defgroup usbd_audio_out_if_Private_Functions - * @{ - */ - -/** - * @brief Init - * Initialize and configures all required resources for audio play function. - * @param AudioFreq: Statrtup audio frequency. - * @param Volume: Startup volume to be set. - * @param options: specific options passed to low layer function. - * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. - */ -static uint8_t Init (uint32_t AudioFreq, - uint32_t Volume, - uint32_t options) -{ - static uint32_t Initialized = 0; - - /* Check if the low layer has already been initialized */ - if (Initialized == 0) - { - /* Call low layer function */ - if (EVAL_AUDIO_Init(OUTPUT_DEVICE_AUTO, Volume, AudioFreq) != 0) - { - AudioState = AUDIO_STATE_ERROR; - return AUDIO_FAIL; - } - - /* Set the Initialization flag to prevent reinitializing the interface again */ - Initialized = 1; - } - - /* Update the Audio state machine */ - AudioState = AUDIO_STATE_ACTIVE; - - return AUDIO_OK; -} - -/** - * @brief DeInit - * Free all resources used by low layer and stops audio-play function. - * @param options: options passed to low layer function. - * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. - */ -static uint8_t DeInit (uint32_t options) -{ - /* Update the Audio state machine */ - AudioState = AUDIO_STATE_INACTIVE; - - return AUDIO_OK; -} - -/** - * @brief AudioCmd - * Play, Stop, Pause or Resume current file. - * @param pbuf: address from which file shoud be played. - * @param size: size of the current buffer/file. - * @param cmd: command to be executed, can be AUDIO_CMD_PLAY , AUDIO_CMD_PAUSE, - * AUDIO_CMD_RESUME or AUDIO_CMD_STOP. - * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. - */ -static uint8_t AudioCmd(uint8_t* pbuf, - uint32_t size, - uint8_t cmd) -{ - /* Check the current state */ - if ((AudioState == AUDIO_STATE_INACTIVE) || (AudioState == AUDIO_STATE_ERROR)) - { - AudioState = AUDIO_STATE_ERROR; - return AUDIO_FAIL; - } - - switch (cmd) - { - /* Process the PLAY command ----------------------------*/ - case AUDIO_CMD_PLAY: - /* If current state is Active or Stopped */ - if ((AudioState == AUDIO_STATE_ACTIVE) || \ - (AudioState == AUDIO_STATE_STOPPED) || \ - (AudioState == AUDIO_STATE_PLAYING)) - { - Audio_MAL_Play((uint32_t)pbuf, (size/2)); - AudioState = AUDIO_STATE_PLAYING; - return AUDIO_OK; - } - /* If current state is Paused */ - else if (AudioState == AUDIO_STATE_PAUSED) - { - if (EVAL_AUDIO_PauseResume(AUDIO_RESUME, (uint32_t)pbuf, (size/2)) != 0) - { - AudioState = AUDIO_STATE_ERROR; - return AUDIO_FAIL; - } - else - { - AudioState = AUDIO_STATE_PLAYING; - return AUDIO_OK; - } - } - else /* Not allowed command */ - { - return AUDIO_FAIL; - } - - /* Process the STOP command ----------------------------*/ - case AUDIO_CMD_STOP: - if (AudioState != AUDIO_STATE_PLAYING) - { - /* Unsupported command */ - return AUDIO_FAIL; - } - else if (EVAL_AUDIO_Stop(CODEC_PDWN_SW) != 0) - { - AudioState = AUDIO_STATE_ERROR; - return AUDIO_FAIL; - } - else - { - AudioState = AUDIO_STATE_STOPPED; - return AUDIO_OK; - } - - /* Process the PAUSE command ---------------------------*/ - case AUDIO_CMD_PAUSE: - if (AudioState != AUDIO_STATE_PLAYING) - { - /* Unsupported command */ - return AUDIO_FAIL; - } - else if (EVAL_AUDIO_PauseResume(AUDIO_PAUSE, (uint32_t)pbuf, (size/2)) != 0) - { - AudioState = AUDIO_STATE_ERROR; - return AUDIO_FAIL; - } - else - { - AudioState = AUDIO_STATE_PAUSED; - return AUDIO_OK; - } - - /* Unsupported command ---------------------------------*/ - default: - return AUDIO_FAIL; - } -} - -/** - * @brief VolumeCtl - * Set the volume level in % - * @param vol: volume level to be set in % (from 0% to 100%) - * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. - */ -static uint8_t VolumeCtl (uint8_t vol) -{ - /* Call low layer volume setting function */ - if (EVAL_AUDIO_VolumeCtl(vol) != 0) - { - AudioState = AUDIO_STATE_ERROR; - return AUDIO_FAIL; - } - - return AUDIO_OK; -} - -/** - * @brief MuteCtl - * Mute or Unmute the audio current output - * @param cmd: can be 0 to unmute, or 1 to mute. - * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. - */ -static uint8_t MuteCtl (uint8_t cmd) -{ - /* Call low layer mute setting function */ - if (EVAL_AUDIO_Mute(cmd) != 0) - { - AudioState = AUDIO_STATE_ERROR; - return AUDIO_FAIL; - } - - return AUDIO_OK; -} - -/** - * @brief - * - * @param - * @param - * @retval AUDIO_OK if all operations succeed, AUDIO_FAIL else. - */ -static uint8_t PeriodicTC (uint8_t cmd) -{ - - - return AUDIO_OK; -} - - -/** - * @brief GetState - * Return the current state of the audio machine - * @param None - * @retval Current State. - */ -static uint8_t GetState (void) -{ - return AudioState; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h b/example/stm32f4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h deleted file mode 100644 index 926f42e13..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h +++ /dev/null @@ -1,137 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_cdc_core.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief header file for the usbd_cdc_core.c file. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#ifndef __USB_CDC_CORE_H_ -#define __USB_CDC_CORE_H_ - -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup usbd_cdc - * @brief This file is the Header file for USBD_cdc.c - * @{ - */ - - -/** @defgroup usbd_cdc_Exported_Defines - * @{ - */ -#define USB_CDC_CONFIG_DESC_SIZ (67) -#define USB_CDC_DESC_SIZ (67-9) - -#define CDC_DESCRIPTOR_TYPE 0x21 - -#define DEVICE_CLASS_CDC 0x02 -#define DEVICE_SUBCLASS_CDC 0x00 - - -#define USB_DEVICE_DESCRIPTOR_TYPE 0x01 -#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02 -#define USB_STRING_DESCRIPTOR_TYPE 0x03 -#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04 -#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05 - -#define STANDARD_ENDPOINT_DESC_SIZE 0x09 - -#define CDC_DATA_IN_PACKET_SIZE *(uint16_t *)(((USB_OTG_CORE_HANDLE *)pdev)->dev.pConfig_descriptor + 57) - -#define CDC_DATA_OUT_PACKET_SIZE *(uint16_t *)(((USB_OTG_CORE_HANDLE *)pdev)->dev.pConfig_descriptor + 64) - -/*---------------------------------------------------------------------*/ -/* CDC definitions */ -/*---------------------------------------------------------------------*/ - -/**************************************************/ -/* CDC Requests */ -/**************************************************/ -#define SEND_ENCAPSULATED_COMMAND 0x00 -#define GET_ENCAPSULATED_RESPONSE 0x01 -#define SET_COMM_FEATURE 0x02 -#define GET_COMM_FEATURE 0x03 -#define CLEAR_COMM_FEATURE 0x04 -#define SET_LINE_CODING 0x20 -#define GET_LINE_CODING 0x21 -#define SET_CONTROL_LINE_STATE 0x22 -#define SEND_BREAK 0x23 -#define NO_CMD 0xFF - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ -typedef struct _CDC_IF_PROP -{ - uint16_t (*pIf_Init) (void); - uint16_t (*pIf_DeInit) (void); - uint16_t (*pIf_Ctrl) (uint32_t Cmd, uint8_t* Buf, uint32_t Len); - uint16_t (*pIf_DataTx) (uint8_t* Buf, uint32_t Len); - uint16_t (*pIf_DataRx) (uint8_t* Buf, uint32_t Len); -} -CDC_IF_Prop_TypeDef; -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern USBD_Class_cb_TypeDef USBD_CDC_cb; -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -/** - * @} - */ - -#endif // __USB_CDC_CORE_H_ -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_if_template.h b/example/stm32f4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_if_template.h deleted file mode 100644 index 1a12508e6..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_if_template.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_cdc_if_template.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief Header for dfu_mal.c file. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CDC_IF_TEMPLATE_H -#define __USBD_CDC_IF_TEMPLATE_H - -/* Includes ------------------------------------------------------------------*/ -#ifdef STM32F2XX - #include "stm32f2xx.h" -#elif defined(STM32F10X_CL) - #include "stm32f10x.h" -#endif /* STM32F2XX */ - -#include "usbd_conf.h" -#include "usbd_cdc_core.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -extern CDC_IF_Prop_TypeDef TEMPLATE_fops; - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -#endif /* __USBD_CDC_IF_TEMPLATE_H */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c b/example/stm32f4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c deleted file mode 100644 index 8d1f15d32..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c +++ /dev/null @@ -1,811 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_cdc_core.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief This file provides the high layer firmware functions to manage the - * following functionalities of the USB CDC Class: - * - Initialization and Configuration of high and low layer - * - Enumeration as CDC Device (and enumeration for each implemented memory interface) - * - OUT/IN data transfer - * - Command IN transfer (class requests management) - * - Error management - * - * @verbatim - * - * =================================================================== - * CDC Class Driver Description - * =================================================================== - * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices - * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus - * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007" - * This driver implements the following aspects of the specification: - * - Device descriptor management - * - Configuration descriptor management - * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN) - * - Requests management (as described in section 6.2 in specification) - * - Abstract Control Model compliant - * - Union Functional collection (using 1 IN endpoint for control) - * - Data interface class - - * @note - * For the Abstract Control Model, this core allows only transmitting the requests to - * lower layer dispatcher (ie. usbd_cdc_vcp.c/.h) which should manage each request and - * perform relative actions. - * - * These aspects may be enriched or modified for a specific user application. - * - * This driver doesn't implement the following aspects of the specification - * (but it is possible to manage these features with some modifications on this driver): - * - Any class-specific aspect relative to communication classes should be managed by user application. - * - All communication classes other than PSTN are not managed - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_cdc_core.h" -#include "usbd_desc.h" -#include "usbd_req.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup usbd_cdc - * @brief usbd core module - * @{ - */ - -/** @defgroup usbd_cdc_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_cdc_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_cdc_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_cdc_Private_FunctionPrototypes - * @{ - */ - -/********************************************* - CDC Device library callbacks - *********************************************/ -static uint8_t usbd_cdc_Init (void *pdev, uint8_t cfgidx); -static uint8_t usbd_cdc_DeInit (void *pdev, uint8_t cfgidx); -static uint8_t usbd_cdc_Setup (void *pdev, USB_SETUP_REQ *req); -static uint8_t usbd_cdc_EP0_RxReady (void *pdev); -static uint8_t usbd_cdc_DataIn (void *pdev, uint8_t epnum); -static uint8_t usbd_cdc_DataOut (void *pdev, uint8_t epnum); -static uint8_t usbd_cdc_SOF (void *pdev); - -/********************************************* - CDC specific management functions - *********************************************/ -static void Handle_USBAsynchXfer (void *pdev); -static uint8_t *USBD_cdc_GetCfgDesc (uint8_t speed, uint16_t *length); -#ifdef USE_USB_OTG_HS -static uint8_t *USBD_cdc_GetOtherCfgDesc (uint8_t speed, uint16_t *length); -#endif -/** - * @} - */ - -/** @defgroup usbd_cdc_Private_Variables - * @{ - */ -extern CDC_IF_Prop_TypeDef APP_FOPS; -extern uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC]; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t usbd_cdc_CfgDesc [USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t usbd_cdc_OtherCfgDesc [USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static __IO uint32_t usbd_cdc_AltSet __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t USB_Rx_Buffer [CDC_DATA_MAX_PACKET_SIZE] __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t APP_Rx_Buffer [APP_RX_DATA_SIZE] __ALIGN_END ; - - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t CmdBuff[CDC_CMD_PACKET_SZE] __ALIGN_END ; - -uint32_t APP_Rx_ptr_in = 0; -uint32_t APP_Rx_ptr_out = 0; -uint32_t APP_Rx_length = 0; - -uint8_t USB_Tx_State = 0; - -static uint32_t cdcCmd = 0xFF; -static uint32_t cdcLen = 0; - -/* CDC interface class callbacks structure */ -USBD_Class_cb_TypeDef USBD_CDC_cb = -{ - usbd_cdc_Init, - usbd_cdc_DeInit, - usbd_cdc_Setup, - NULL, /* EP0_TxSent, */ - usbd_cdc_EP0_RxReady, - usbd_cdc_DataIn, - usbd_cdc_DataOut, - usbd_cdc_SOF, - NULL, - NULL, - USBD_cdc_GetCfgDesc, -#ifdef USE_USB_OTG_HS - USBD_cdc_GetOtherCfgDesc, /* use same cobfig as per FS */ -#endif /* USE_USB_OTG_HS */ -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB CDC device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t usbd_cdc_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - /*Configuration Descriptor*/ - 0x09, /* bLength: Configuration Descriptor size */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ - USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */ - 0x00, - 0x02, /* bNumInterfaces: 2 interface */ - 0x01, /* bConfigurationValue: Configuration value */ - 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ - 0xC0, /* bmAttributes: self powered */ - 0x32, /* MaxPower 0 mA */ - - /*---------------------------------------------------------------------------*/ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SZE), -#ifdef USE_USB_OTG_HS - 0x10, /* bInterval: */ -#else - 0xFF, /* bInterval: */ -#endif /* USE_USB_OTG_HS */ - - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_MAX_PACKET_SIZE), - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */ - HIBYTE(CDC_DATA_MAX_PACKET_SIZE), - 0x00 /* bInterval: ignore for Bulk transfer */ -} ; - -#ifdef USE_USB_OTG_HS -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t usbd_cdc_OtherCfgDesc[USB_CDC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, - USB_CDC_CONFIG_DESC_SIZ, - 0x00, - 0x02, /* bNumInterfaces: 2 interfaces */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ - - /*Interface Descriptor */ - 0x09, /* bLength: Interface Descriptor size */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */ - /* Interface descriptor type */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x01, /* bNumEndpoints: One endpoints used */ - 0x02, /* bInterfaceClass: Communication Interface Class */ - 0x02, /* bInterfaceSubClass: Abstract Control Model */ - 0x01, /* bInterfaceProtocol: Common AT commands */ - 0x00, /* iInterface: */ - - /*Header Functional Descriptor*/ - 0x05, /* bLength: Endpoint Descriptor size */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x00, /* bDescriptorSubtype: Header Func Desc */ - 0x10, /* bcdCDC: spec release number */ - 0x01, - - /*Call Management Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x01, /* bDescriptorSubtype: Call Management Func Desc */ - 0x00, /* bmCapabilities: D0+D1 */ - 0x01, /* bDataInterface: 1 */ - - /*ACM Functional Descriptor*/ - 0x04, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ - 0x02, /* bmCapabilities */ - - /*Union Functional Descriptor*/ - 0x05, /* bFunctionLength */ - 0x24, /* bDescriptorType: CS_INTERFACE */ - 0x06, /* bDescriptorSubtype: Union func desc */ - 0x00, /* bMasterInterface: Communication class interface */ - 0x01, /* bSlaveInterface0: Data Class Interface */ - - /*Endpoint 2 Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ - CDC_CMD_EP, /* bEndpointAddress */ - 0x03, /* bmAttributes: Interrupt */ - LOBYTE(CDC_CMD_PACKET_SZE), /* wMaxPacketSize: */ - HIBYTE(CDC_CMD_PACKET_SZE), - 0xFF, /* bInterval: */ - - /*---------------------------------------------------------------------------*/ - - /*Data class interface descriptor*/ - 0x09, /* bLength: Endpoint Descriptor size */ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */ - 0x01, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints: Two endpoints used */ - 0x0A, /* bInterfaceClass: CDC */ - 0x00, /* bInterfaceSubClass: */ - 0x00, /* bInterfaceProtocol: */ - 0x00, /* iInterface: */ - - /*Endpoint OUT Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ - CDC_OUT_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00, /* bInterval: ignore for Bulk transfer */ - - /*Endpoint IN Descriptor*/ - 0x07, /* bLength: Endpoint Descriptor size */ - USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */ - CDC_IN_EP, /* bEndpointAddress */ - 0x02, /* bmAttributes: Bulk */ - 0x40, /* wMaxPacketSize: */ - 0x00, - 0x00 /* bInterval */ -}; -#endif /* USE_USB_OTG_HS */ - -/** - * @} - */ - -/** @defgroup usbd_cdc_Private_Functions - * @{ - */ - -/** - * @brief usbd_cdc_Init - * Initilaize the CDC interface - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t usbd_cdc_Init (void *pdev, - uint8_t cfgidx) -{ - uint8_t *pbuf; - - /* Open EP IN */ - DCD_EP_Open(pdev, - CDC_IN_EP, - CDC_DATA_IN_PACKET_SIZE, - USB_OTG_EP_BULK); - - /* Open EP OUT */ - DCD_EP_Open(pdev, - CDC_OUT_EP, - CDC_DATA_OUT_PACKET_SIZE, - USB_OTG_EP_BULK); - - /* Open Command IN EP */ - DCD_EP_Open(pdev, - CDC_CMD_EP, - CDC_CMD_PACKET_SZE, - USB_OTG_EP_INT); - - pbuf = (uint8_t *)USBD_DeviceDesc; - pbuf[4] = DEVICE_CLASS_CDC; - pbuf[5] = DEVICE_SUBCLASS_CDC; - - /* Initialize the Interface physical components */ - APP_FOPS.pIf_Init(); - - /* Prepare Out endpoint to receive next packet */ - DCD_EP_PrepareRx(pdev, - CDC_OUT_EP, - (uint8_t*)(USB_Rx_Buffer), - CDC_DATA_OUT_PACKET_SIZE); - - return USBD_OK; -} - -/** - * @brief usbd_cdc_Init - * DeInitialize the CDC layer - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t usbd_cdc_DeInit (void *pdev, - uint8_t cfgidx) -{ - /* Open EP IN */ - DCD_EP_Close(pdev, - CDC_IN_EP); - - /* Open EP OUT */ - DCD_EP_Close(pdev, - CDC_OUT_EP); - - /* Open Command IN EP */ - DCD_EP_Close(pdev, - CDC_CMD_EP); - - /* Restore default state of the Interface physical components */ - APP_FOPS.pIf_DeInit(); - - return USBD_OK; -} - -/** - * @brief usbd_cdc_Setup - * Handle the CDC specific requests - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t usbd_cdc_Setup (void *pdev, - USB_SETUP_REQ *req) -{ - uint16_t len; - uint8_t *pbuf; - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - /* CDC Class Requests -------------------------------*/ - case USB_REQ_TYPE_CLASS : - /* Check if the request is a data setup packet */ - if (req->wLength) - { - /* Check if the request is Device-to-Host */ - if (req->bmRequest & 0x80) - { - /* Get the data to be sent to Host from interface layer */ - APP_FOPS.pIf_Ctrl(req->bRequest, CmdBuff, req->wLength); - - /* Send the data to the host */ - USBD_CtlSendData (pdev, - CmdBuff, - req->wLength); - } - else /* Host-to-Device requeset */ - { - /* Set the value of the current command to be processed */ - cdcCmd = req->bRequest; - cdcLen = req->wLength; - - /* Prepare the reception of the buffer over EP0 - Next step: the received data will be managed in usbd_cdc_EP0_TxSent() - function. */ - USBD_CtlPrepareRx (pdev, - CmdBuff, - req->wLength); - } - } - else /* No Data request */ - { - /* Transfer the command to the interface layer */ - APP_FOPS.pIf_Ctrl(req->bRequest, NULL, 0); - } - - return USBD_OK; - - default: - USBD_CtlError (pdev, req); - return USBD_FAIL; - - - - /* Standard Requests -------------------------------*/ - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - if( (req->wValue >> 8) == CDC_DESCRIPTOR_TYPE) - { -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - pbuf = usbd_cdc_Desc; -#else - pbuf = usbd_cdc_CfgDesc + 9 + (9 * USBD_ITF_MAX_NUM); -#endif - len = MIN(USB_CDC_DESC_SIZ , req->wLength); - } - - USBD_CtlSendData (pdev, - pbuf, - len); - break; - - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - (uint8_t *)&usbd_cdc_AltSet, - 1); - break; - - case USB_REQ_SET_INTERFACE : - if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM) - { - usbd_cdc_AltSet = (uint8_t)(req->wValue); - } - else - { - /* Call the error management function (command will be nacked */ - USBD_CtlError (pdev, req); - } - break; - } - } - return USBD_OK; -} - -/** - * @brief usbd_cdc_EP0_RxReady - * Data received on control endpoint - * @param pdev: device device instance - * @retval status - */ -static uint8_t usbd_cdc_EP0_RxReady (void *pdev) -{ - if (cdcCmd != NO_CMD) - { - /* Process the data */ - APP_FOPS.pIf_Ctrl(cdcCmd, CmdBuff, cdcLen); - - /* Reset the command variable to default value */ - cdcCmd = NO_CMD; - } - - return USBD_OK; -} - -/** - * @brief usbd_audio_DataIn - * Data sent on non-control IN endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t usbd_cdc_DataIn (void *pdev, uint8_t epnum) -{ - uint16_t USB_Tx_ptr; - uint16_t USB_Tx_length; - - if (USB_Tx_State == 1) - { - if (APP_Rx_length == 0) - { - USB_Tx_State = 0; - } - else - { - if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE){ - USB_Tx_ptr = APP_Rx_ptr_out; - USB_Tx_length = CDC_DATA_IN_PACKET_SIZE; - - APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE; - APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE; - } - else - { - USB_Tx_ptr = APP_Rx_ptr_out; - USB_Tx_length = APP_Rx_length; - - APP_Rx_ptr_out += APP_Rx_length; - APP_Rx_length = 0; - } - - /* Prepare the available data buffer to be sent on IN endpoint */ - DCD_EP_Tx (pdev, - CDC_IN_EP, - (uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr], - USB_Tx_length); - } - } - - return USBD_OK; -} - -/** - * @brief usbd_audio_DataOut - * Data received on non-control Out endpoint - * @param pdev: device instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t usbd_cdc_DataOut (void *pdev, uint8_t epnum) -{ - uint16_t USB_Rx_Cnt; - - /* Get the received data buffer and update the counter */ - USB_Rx_Cnt = ((USB_OTG_CORE_HANDLE*)pdev)->dev.out_ep[epnum].xfer_count; - - /* USB data will be immediately processed, this allow next USB traffic being - NAKed till the end of the application Xfer */ - APP_FOPS.pIf_DataRx(USB_Rx_Buffer, USB_Rx_Cnt); - - /* Prepare Out endpoint to receive next packet */ - DCD_EP_PrepareRx(pdev, - CDC_OUT_EP, - (uint8_t*)(USB_Rx_Buffer), - CDC_DATA_OUT_PACKET_SIZE); - - return USBD_OK; -} - -/** - * @brief usbd_audio_SOF - * Start Of Frame event management - * @param pdev: instance - * @param epnum: endpoint number - * @retval status - */ -static uint8_t usbd_cdc_SOF (void *pdev) -{ - static uint32_t FrameCount = 0; - - if (FrameCount++ == CDC_IN_FRAME_INTERVAL) - { - /* Reset the frame counter */ - FrameCount = 0; - - /* Check the data to be sent through IN pipe */ - Handle_USBAsynchXfer(pdev); - } - - return USBD_OK; -} - -/** - * @brief Handle_USBAsynchXfer - * Send data to USB - * @param pdev: instance - * @retval None - */ -static void Handle_USBAsynchXfer (void *pdev) -{ - uint16_t USB_Tx_ptr; - uint16_t USB_Tx_length; - - if(USB_Tx_State != 1) - { - if (APP_Rx_ptr_out == APP_RX_DATA_SIZE) - { - APP_Rx_ptr_out = 0; - } - - if(APP_Rx_ptr_out == APP_Rx_ptr_in) - { - USB_Tx_State = 0; - return; - } - - if(APP_Rx_ptr_out > APP_Rx_ptr_in) /* rollback */ - { - APP_Rx_length = APP_RX_DATA_SIZE - APP_Rx_ptr_out; - - } - else - { - APP_Rx_length = APP_Rx_ptr_in - APP_Rx_ptr_out; - - } -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - APP_Rx_length &= ~0x03; -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - - if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE) - { - USB_Tx_ptr = APP_Rx_ptr_out; - USB_Tx_length = CDC_DATA_IN_PACKET_SIZE; - - APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE; - APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE; - } - else - { - USB_Tx_ptr = APP_Rx_ptr_out; - USB_Tx_length = APP_Rx_length; - - APP_Rx_ptr_out += APP_Rx_length; - APP_Rx_length = 0; - } - USB_Tx_State = 1; - - DCD_EP_Tx (pdev, - CDC_IN_EP, - (uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr], - USB_Tx_length); - } - -} - -/** - * @brief USBD_cdc_GetCfgDesc - * Return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_cdc_GetCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (usbd_cdc_CfgDesc); - return usbd_cdc_CfgDesc; -} - -/** - * @brief USBD_cdc_GetCfgDesc - * Return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -#ifdef USE_USB_OTG_HS -static uint8_t *USBD_cdc_GetOtherCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (usbd_cdc_OtherCfgDesc); - return usbd_cdc_OtherCfgDesc; -} -#endif -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_if_template.c b/example/stm32f4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_if_template.c deleted file mode 100644 index 406f30a22..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_if_template.c +++ /dev/null @@ -1,202 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_cdc_if_template.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief Generic media access Layer. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED -#pragma data_alignment = 4 -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_cdc_if_template.h" -#include "stm32_eval.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* These are external variables imported from CDC core to be used for IN - transfer management. */ -extern uint8_t APP_Rx_Buffer []; /* Write CDC received data in this buffer. - These data will be sent over USB IN endpoint - in the CDC core functions. */ -extern uint32_t APP_Rx_ptr_in; /* Increment this pointer or roll it back to - start address when writing received data - in the buffer APP_Rx_Buffer. */ - -/* Private function prototypes -----------------------------------------------*/ -static uint16_t TEMPLATE_Init (void); -static uint16_t TEMPLATE_DeInit (void); -static uint16_t TEMPLATE_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len); -static uint16_t TEMPLATE_DataTx (uint8_t* Buf, uint32_t Len); -static uint16_t TEMPLATE_DataRx (uint8_t* Buf, uint32_t Len); - -CDC_IF_Prop_TypeDef TEMPLATE_fops = -{ - TEMPLATE_Init, - TEMPLATE_DeInit, - TEMPLATE_Ctrl, - TEMPLATE_DataTx, - TEMPLATE_DataRx -}; - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief TEMPLATE_Init - * Initializes the CDC media low layer - * @param None - * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL - */ -static uint16_t TEMPLATE_Init(void) -{ - /* - Add your initialization code here - */ - return USBD_OK; -} - -/** - * @brief TEMPLATE_DeInit - * DeInitializes the CDC media low layer - * @param None - * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL - */ -static uint16_t TEMPLATE_DeInit(void) -{ - /* - Add your deinitialization code here - */ - return USBD_OK; -} - - -/** - * @brief TEMPLATE_Ctrl - * Manage the CDC class requests - * @param Cmd: Command code - * @param Buf: Buffer containing command data (request parameters) - * @param Len: Number of data to be sent (in bytes) - * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL - */ -static uint16_t TEMPLATE_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len) -{ - switch (Cmd) - { - case SEND_ENCAPSULATED_COMMAND: - /* Add your code here */ - break; - - case GET_ENCAPSULATED_RESPONSE: - /* Add your code here */ - break; - - case SET_COMM_FEATURE: - /* Add your code here */ - break; - - case GET_COMM_FEATURE: - /* Add your code here */ - break; - - case CLEAR_COMM_FEATURE: - /* Add your code here */ - break; - - case SET_LINE_CODING: - /* Add your code here */ - break; - - case GET_LINE_CODING: - /* Add your code here */ - break; - - case SET_CONTROL_LINE_STATE: - /* Add your code here */ - break; - - case SEND_BREAK: - /* Add your code here */ - break; - - default: - break; - } - - return USBD_OK; -} - -/** - * @brief TEMPLATE_DataTx - * CDC received data to be send over USB IN endpoint are managed in - * this function. - * @param Buf: Buffer of data to be sent - * @param Len: Number of data to be sent (in bytes) - * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL - */ -static uint16_t TEMPLATE_DataTx (uint8_t* Buf, uint32_t Len) -{ - - /* Get the data to be sent */ - for (i = 0; i < Len; i++) - { - /* APP_Rx_Buffer[APP_Rx_ptr_in] = XXX_ReceiveData(XXX); */ - } - - /* Increment the in pointer */ - APP_Rx_ptr_in++; - - /* To avoid buffer overflow */ - if(APP_Rx_ptr_in == APP_RX_DATA_SIZE) - { - APP_Rx_ptr_in = 0; - } - - return USBD_OK; -} - -/** - * @brief TEMPLATE_DataRx - * Data received over USB OUT endpoint are sent over CDC interface - * through this function. - * - * @note - * This function will block any OUT packet reception on USB endpoint - * untill exiting this function. If you exit this function before transfer - * is complete on CDC interface (ie. using DMA controller) it will result - * in receiving more data while previous ones are still not sent. - * - * @param Buf: Buffer of data to be received - * @param Len: Number of data received (in bytes) - * @retval Result of the opeartion: USBD_OK if all operations are OK else USBD_FAIL - */ -static uint16_t TEMPLATE_DataRx (uint8_t* Buf, uint32_t Len) -{ - uint32_t i; - - /* Send the received buffer */ - for (i = 0; i < Len; i++) - { - /* XXXX_SendData(XXXX, *(Buf + i) ); */ - } - - return USBD_OK; -} - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_core.h b/example/stm32f4/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_core.h deleted file mode 100644 index aadffb148..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_core.h +++ /dev/null @@ -1,187 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_dfu_core.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief header file for the usbd_dfu_core.c file. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#ifndef __USB_DFU_CORE_H_ -#define __USB_DFU_CORE_H_ - -#include "usbd_ioreq.h" -#include "usbd_dfu_mal.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup usbd_dfu - * @brief This file is the Header file for USBD_dfu.c - * @{ - */ - - -/** @defgroup usbd_dfu_Exported_Defines - * @{ - */ -#define USB_DFU_CONFIG_DESC_SIZ (18 + (9 * USBD_ITF_MAX_NUM)) -#define USB_DFU_DESC_SIZ 9 - -#define DFU_DESCRIPTOR_TYPE 0x21 - - -/*---------------------------------------------------------------------*/ -/* DFU definitions */ -/*---------------------------------------------------------------------*/ - - - -/**************************************************/ -/* DFU Requests DFU states */ -/**************************************************/ - - -#define STATE_appIDLE 0 -#define STATE_appDETACH 1 -#define STATE_dfuIDLE 2 -#define STATE_dfuDNLOAD_SYNC 3 -#define STATE_dfuDNBUSY 4 -#define STATE_dfuDNLOAD_IDLE 5 -#define STATE_dfuMANIFEST_SYNC 6 -#define STATE_dfuMANIFEST 7 -#define STATE_dfuMANIFEST_WAIT_RESET 8 -#define STATE_dfuUPLOAD_IDLE 9 -#define STATE_dfuERROR 10 - -/**************************************************/ -/* DFU Requests DFU status */ -/**************************************************/ - -#define STATUS_OK 0x00 -#define STATUS_ERRTARGET 0x01 -#define STATUS_ERRFILE 0x02 -#define STATUS_ERRWRITE 0x03 -#define STATUS_ERRERASE 0x04 -#define STATUS_ERRCHECK_ERASED 0x05 -#define STATUS_ERRPROG 0x06 -#define STATUS_ERRVERIFY 0x07 -#define STATUS_ERRADDRESS 0x08 -#define STATUS_ERRNOTDONE 0x09 -#define STATUS_ERRFIRMWARE 0x0A -#define STATUS_ERRVENDOR 0x0B -#define STATUS_ERRUSBR 0x0C -#define STATUS_ERRPOR 0x0D -#define STATUS_ERRUNKNOWN 0x0E -#define STATUS_ERRSTALLEDPKT 0x0F - -/**************************************************/ -/* DFU Requests DFU states Manifestation State */ -/**************************************************/ - -#define Manifest_complete 0x00 -#define Manifest_In_Progress 0x01 - - -/**************************************************/ -/* Special Commands with Download Request */ -/**************************************************/ - -#define CMD_GETCOMMANDS 0x00 -#define CMD_SETADDRESSPOINTER 0x21 -#define CMD_ERASE 0x41 - -/**************************************************/ -/* Other defines */ -/**************************************************/ -/* Bit Detach capable = bit 3 in bmAttributes field */ -#define DFU_DETACH_MASK (uint8_t)(1 << 4) -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ -/**************************************************/ -/* DFU Requests */ -/**************************************************/ - -typedef enum _DFU_REQUESTS { - DFU_DETACH = 0, - DFU_DNLOAD = 1, - DFU_UPLOAD, - DFU_GETSTATUS, - DFU_CLRSTATUS, - DFU_GETSTATE, - DFU_ABORT -} DFU_REQUESTS; - -typedef void (*pFunction)(void); -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ -/********** Descriptor of DFU interface 0 Alternate setting n ****************/ -#define USBD_DFU_IF_DESC(n) 0x09, /* bLength: Interface Descriptor size */ \ - USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ - 0x00, /* bInterfaceNumber: Number of Interface */ \ - (n), /* bAlternateSetting: Alternate setting */ \ - 0x00, /* bNumEndpoints*/ \ - 0xFE, /* bInterfaceClass: Application Specific Class Code */ \ - 0x01, /* bInterfaceSubClass : Device Firmware Upgrade Code */ \ - 0x02, /* nInterfaceProtocol: DFU mode protocol */ \ - USBD_IDX_INTERFACE_STR + (n) + 1 /* iInterface: Index of string descriptor */ \ - /* 18 */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern USBD_Class_cb_TypeDef DFU_cb; -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -/** - * @} - */ - -#endif // __USB_DFU_CORE_H_ -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_mal.h b/example/stm32f4/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_mal.h deleted file mode 100644 index 9ed095b73..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_mal.h +++ /dev/null @@ -1,79 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_dfu_mal.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief Header for usbd_dfu_mal.c file. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __DFU_MAL_H -#define __DFU_MAL_H - -/* Includes ------------------------------------------------------------------*/ -#ifdef STM32F2XX - #include "stm32f2xx.h" -#elif defined(STM32F10X_CL) - #include "stm32f10x.h" -#endif /* STM32F2XX */ - -#include "usbd_conf.h" -#include "usbd_dfu_core.h" - -/* Exported types ------------------------------------------------------------*/ -typedef struct _DFU_MAL_PROP -{ - const uint8_t* pStrDesc; - uint16_t (*pMAL_Init) (void); - uint16_t (*pMAL_DeInit) (void); - uint16_t (*pMAL_Erase) (uint32_t Add); - uint16_t (*pMAL_Write) (uint32_t Add, uint32_t Len); - uint8_t *(*pMAL_Read) (uint32_t Add, uint32_t Len); - uint16_t (*pMAL_CheckAdd) (uint32_t Add); - const uint32_t EraseTiming; - const uint32_t WriteTiming; -} -DFU_MAL_Prop_TypeDef; - - -/* Exported constants --------------------------------------------------------*/ -#define MAL_OK 0 -#define MAL_FAIL 1 - -/* utils macro ---------------------------------------------------------------*/ -#define _1st_BYTE(x) (uint8_t)((x)&0xFF) /* 1st addressing cycle */ -#define _2nd_BYTE(x) (uint8_t)(((x)&0xFF00)>>8) /* 2nd addressing cycle */ -#define _3rd_BYTE(x) (uint8_t)(((x)&0xFF0000)>>16) /* 3rd addressing cycle */ -#define _4th_BYTE(x) (uint8_t)(((x)&0xFF000000)>>24) /* 4th addressing cycle */ - -/* Exported macro ------------------------------------------------------------*/ -#define SET_POLLING_TIMING(x) buffer[1] = _1st_BYTE(x);\ - buffer[2] = _2nd_BYTE(x);\ - buffer[3] = _3rd_BYTE(x); - -/* Exported functions ------------------------------------------------------- */ - -uint16_t MAL_Init (void); -uint16_t MAL_DeInit (void); -uint16_t MAL_Erase (uint32_t SectorAddress); -uint16_t MAL_Write (uint32_t SectorAddress, uint32_t DataLength); -uint8_t *MAL_Read (uint32_t SectorAddress, uint32_t DataLength); -uint16_t MAL_GetStatus(uint32_t SectorAddress ,uint8_t Cmd, uint8_t *buffer); - -extern uint8_t MAL_Buffer[XFERSIZE]; /* RAM Buffer for Downloaded Data */ -#endif /* __DFU_MAL_H */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/inc/usbd_flash_if.h b/example/stm32f4/STM32_USB_Device_Library/Class/dfu/inc/usbd_flash_if.h deleted file mode 100644 index 07e49dfb2..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/inc/usbd_flash_if.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_flash_if.h - * @author MCD Application Team - * @version V1.0.0RC1 - * @date 18-March-2011 - * @brief Header for usbd_flash_if.c file. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __FLASH_IF_MAL_H -#define __FLASH_IF_MAL_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_dfu_mal.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -#define FLASH_START_ADD 0x08000000 - -#ifdef STM32F2XX - #define FLASH_END_ADD 0x08100000 - #define FLASH_IF_STRING "@Internal Flash /0x08000000/03*016Ka,01*016Kg,01*064Kg,07*128Kg" -#elif defined(STM32F10X_CL) - #define FLASH_END_ADD 0x08040000 - #define FLASH_IF_STRING "@Internal Flash /0x08000000/06*002Ka,122*002Kg" -#endif /* STM32F2XX */ - - -extern DFU_MAL_Prop_TypeDef DFU_Flash_cb; - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __FLASH_IF_MAL_H */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/inc/usbd_mem_if_template.h b/example/stm32f4/STM32_USB_Device_Library/Class/dfu/inc/usbd_mem_if_template.h deleted file mode 100644 index d1e0dda9a..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/inc/usbd_mem_if_template.h +++ /dev/null @@ -1,46 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_mem_if_template.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief Header for usbd_mem_if_template.c file. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MEM_IF_MAL_H -#define __MEM_IF_MAL_H - -/* Includes ------------------------------------------------------------------*/ -#ifdef STM32F2XX - #include "stm32f2xx.h" -#endif /* STM32F2XX */ -#include "usbd_dfu_mal.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -#define MEM_START_ADD 0x00000000 /* Dummy start address */ -#define MEM_END_ADD (uint32_t)(MEM_START_ADD + (5 * 1024)) /* Dummy Size = 5KB */ - -#define MEM_IF_STRING "@Dummy Memory /0x00000000/01*002Kg,03*001Kg" - -extern DFU_MAL_Prop_TypeDef DFU_Mem_cb; - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __MEM_IF_MAL_H */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/inc/usbd_otp_if.h b/example/stm32f4/STM32_USB_Device_Library/Class/dfu/inc/usbd_otp_if.h deleted file mode 100644 index ef7e06101..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/inc/usbd_otp_if.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_otp_if.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief Header for usbd_otp_if.c file. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __OTP_IF_MAL_H -#define __OTP_IF_MAL_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_dfu_mal.h" - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -#define OTP_START_ADD 0x1FFF7800 -#define OTP_END_ADD (uint32_t)(OTP_START_ADD + 528) - -#define OTP_IF_STRING "@OTP Area /0x1FFF7800/01*512 g,01*016 g" - -extern DFU_MAL_Prop_TypeDef DFU_Otp_cb; - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -#endif /* __OTP_IF_MAL_H */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_core.c b/example/stm32f4/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_core.c deleted file mode 100644 index 316031672..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_core.c +++ /dev/null @@ -1,1046 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_dfu_core.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief This file provides the high layer firmware functions to manage the - * following functionalities of the USB DFU Class: - * - Initialization and Configuration of high and low layer - * - Enumeration as DFU Device (and enumeration for each implemented memory interface) - * - Transfers to/from memory interfaces - * - Easy-to-customize "plug-in-like" modules for adding/removing memory interfaces. - * - Error management - * - * @verbatim - * - * =================================================================== - * DFU Class Driver Description - * =================================================================== - * This driver manages the DFU class V1.1 following the "Device Class Specification for - * Device Firmware Upgrade Version 1.1 Aug 5, 2004". - * This driver implements the following aspects of the specification: - * - Device descriptor management - * - Configuration descriptor management - * - Enumeration as DFU device (in DFU mode only) - * - Requests management (supporting ST DFU sub-protocol) - * - Memory operations management (Download/Upload/Erase/Detach/GetState/GetStatus) - * - DFU state machine implementation. - * - * @note - * ST DFU sub-protocol is compliant with DFU protocol and use sub-requests to manage - * memory addressing, commands processing, specific memories operations (ie. Erase) ... - * As required by the DFU specification, only endpoint 0 is used in this application. - * Other endpoints and functions may be added to the application (ie. DFU ...) - * - * These aspects may be enriched or modified for a specific user application. - * - * This driver doesn't implement the following aspects of the specification - * (but it is possible to manage these features with some modifications on this driver): - * - Manifestation Tolerant mode - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_dfu_core.h" -#include "usbd_desc.h" -#include "usbd_req.h" -#include "usb_bsp.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup usbd_dfu - * @brief usbd core module - * @{ - */ - -/** @defgroup usbd_dfu_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_dfu_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_dfu_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup usbd_dfu_Private_FunctionPrototypes - * @{ - */ - -/********************************************* - DFU Device library callbacks - *********************************************/ -static uint8_t usbd_dfu_Init (void *pdev, - uint8_t cfgidx); - -static uint8_t usbd_dfu_DeInit (void *pdev, - uint8_t cfgidx); - -static uint8_t usbd_dfu_Setup (void *pdev, - USB_SETUP_REQ *req); - -static uint8_t EP0_TxSent (void *pdev); - -static uint8_t EP0_RxReady (void *pdev); - - -static uint8_t *USBD_DFU_GetCfgDesc (uint8_t speed, - uint16_t *length); - - -#ifdef USB_OTG_HS_CORE -static uint8_t *USBD_DFU_GetOtherCfgDesc (uint8_t speed, - uint16_t *length); -#endif - -static uint8_t* USBD_DFU_GetUsrStringDesc (uint8_t speed, - uint8_t index , - uint16_t *length); - -/********************************************* - DFU Requests management functions - *********************************************/ -static void DFU_Req_DETACH (void *pdev, - USB_SETUP_REQ *req); - -static void DFU_Req_DNLOAD (void *pdev, - USB_SETUP_REQ *req); - -static void DFU_Req_UPLOAD (void *pdev, - USB_SETUP_REQ *req); - -static void DFU_Req_GETSTATUS (void *pdev); - -static void DFU_Req_CLRSTATUS (void *pdev); - -static void DFU_Req_GETSTATE (void *pdev); - -static void DFU_Req_ABORT (void *pdev); - -static void DFU_LeaveDFUMode (void *pdev); - -/** - * @} - */ - -/** @defgroup usbd_dfu_Private_Variables - * @{ - */ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t usbd_dfu_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END ; - - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t usbd_dfu_OtherCfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END ; - -/* The list of Interface String descriptor pointers is defined in usbd_dfu_mal.c - file. This list can be updated whenever a memory has to be added or removed */ -extern const uint8_t* usbd_dfu_StringDesc[]; - -/* State Machine variables */ -uint8_t DeviceState; -uint8_t DeviceStatus[6]; -uint32_t Manifest_State = Manifest_complete; -/* Data Management variables */ -static uint32_t wBlockNum = 0, wlength = 0; -static uint32_t Pointer = APP_DEFAULT_ADD; /* Base Address to Erase, Program or Read */ -static __IO uint32_t usbd_dfu_AltSet = 0; - -extern uint8_t MAL_Buffer[]; - -/* DFU interface class callbacks structure */ -USBD_Class_cb_TypeDef DFU_cb = -{ - usbd_dfu_Init, - usbd_dfu_DeInit, - usbd_dfu_Setup, - EP0_TxSent, - EP0_RxReady, - NULL, /* DataIn, */ - NULL, /* DataOut, */ - NULL, /*SOF */ - NULL, - NULL, - USBD_DFU_GetCfgDesc, -#ifdef USB_OTG_HS_CORE - USBD_DFU_GetOtherCfgDesc, /* use same cobfig as per FS */ -#endif - USBD_DFU_GetUsrStringDesc, -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB DFU device Configuration Descriptor */ -__ALIGN_BEGIN uint8_t usbd_dfu_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuation Descriptor size */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ - USB_DFU_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ - 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x02, /*iConfiguration: Index of string descriptor describing the configuration*/ - 0xC0, /*bmAttributes: bus powered and Supprts Remote Wakeup */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ - /* 09 */ - - /********** Descriptor of DFU interface 0 Alternate setting 0 **************/ - USBD_DFU_IF_DESC(0), /* This interface is mandatory for all devices */ - -#if (USBD_ITF_MAX_NUM > 1) - /********** Descriptor of DFU interface 0 Alternate setting 1 **************/ - USBD_DFU_IF_DESC(1), -#endif /* (USBD_ITF_MAX_NUM > 1) */ - -#if (USBD_ITF_MAX_NUM > 2) - /********** Descriptor of DFU interface 0 Alternate setting 2 **************/ - USBD_DFU_IF_DESC(2), -#endif /* (USBD_ITF_MAX_NUM > 2) */ - -#if (USBD_ITF_MAX_NUM > 3) - /********** Descriptor of DFU interface 0 Alternate setting 3 **************/ - USBD_DFU_IF_DESC(3), -#endif /* (USBD_ITF_MAX_NUM > 3) */ - -#if (USBD_ITF_MAX_NUM > 4) - /********** Descriptor of DFU interface 0 Alternate setting 4 **************/ - USBD_DFU_IF_DESC(4), -#endif /* (USBD_ITF_MAX_NUM > 4) */ - -#if (USBD_ITF_MAX_NUM > 5) - /********** Descriptor of DFU interface 0 Alternate setting 5 **************/ - USBD_DFU_IF_DESC(5), -#endif /* (USBD_ITF_MAX_NUM > 5) */ - -#if (USBD_ITF_MAX_NUM > 6) -#error "ERROR: usbd_dfu_core.c: Modify the file to support more descriptors!" -#endif /* (USBD_ITF_MAX_NUM > 6) */ - - /******************** DFU Functional Descriptor********************/ - 0x09, /*blength = 9 Bytes*/ - DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/ - 0x0B, /*bmAttribute - bitCanDnload = 1 (bit 0) - bitCanUpload = 1 (bit 1) - bitManifestationTolerant = 0 (bit 2) - bitWillDetach = 1 (bit 3) - Reserved (bit4-6) - bitAcceleratedST = 0 (bit 7)*/ - 0xFF, /*DetachTimeOut= 255 ms*/ - 0x00, - /*WARNING: In DMA mode the multiple MPS packets feature is still not supported - ==> In this case, when using DMA XFERSIZE should be set to 64 in usbd_conf.h */ - TRANSFER_SIZE_BYTES(XFERSIZE), /* TransferSize = 1024 Byte*/ - 0x1A, /* bcdDFUVersion*/ - 0x01 - /***********************************************************/ - /* 9*/ -} ; - -#ifdef USE_USB_OTG_HS -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -__ALIGN_BEGIN uint8_t usbd_dfu_OtherCfgDesc[USB_DFU_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_DFU_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ - 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x02, /*iConfiguration: Index of string descriptor describing the configuration*/ - 0xC0, /*bmAttributes: bus powered and Supprts Remote Wakeup */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ - /* 09 */ - - /********** Descriptor of DFU interface 0 Alternate setting 0 **************/ - USBD_DFU_IF_DESC(0), /* This interface is mandatory for all devices */ - -#if (USBD_ITF_MAX_NUM > 1) - /********** Descriptor of DFU interface 0 Alternate setting 1 **************/ - USBD_DFU_IF_DESC(1), -#endif /* (USBD_ITF_MAX_NUM > 1) */ - -#if (USBD_ITF_MAX_NUM > 2) - /********** Descriptor of DFU interface 0 Alternate setting 2 **************/ - USBD_DFU_IF_DESC(2), -#endif /* (USBD_ITF_MAX_NUM > 2) */ - -#if (USBD_ITF_MAX_NUM > 3) - /********** Descriptor of DFU interface 0 Alternate setting 3 **************/ - USBD_DFU_IF_DESC(3), -#endif /* (USBD_ITF_MAX_NUM > 3) */ - -#if (USBD_ITF_MAX_NUM > 4) - /********** Descriptor of DFU interface 0 Alternate setting 4 **************/ - USBD_DFU_IF_DESC(4), -#endif /* (USBD_ITF_MAX_NUM > 4) */ - -#if (USBD_ITF_MAX_NUM > 5) - /********** Descriptor of DFU interface 0 Alternate setting 5 **************/ - USBD_DFU_IF_DESC(5), -#endif /* (USBD_ITF_MAX_NUM > 5) */ - -#if (USBD_ITF_MAX_NUM > 6) -#error "ERROR: usbd_dfu_core.c: Modify the file to support more descriptors!" -#endif /* (USBD_ITF_MAX_NUM > 6) */ - - /******************** DFU Functional Descriptor********************/ - 0x09, /*blength = 9 Bytes*/ - DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/ - 0x0B, /*bmAttribute - bitCanDnload = 1 (bit 0) - bitCanUpload = 1 (bit 1) - bitManifestationTolerant = 0 (bit 2) - bitWillDetach = 1 (bit 3) - Reserved (bit4-6) - bitAcceleratedST = 0 (bit 7)*/ - 0xFF, /*DetachTimeOut= 255 ms*/ - 0x00, - /*WARNING: In DMA mode the multiple MPS packets feature is still not supported - ==> In this case, when using DMA XFERSIZE should be set to 64 in usbd_conf.h */ - TRANSFER_SIZE_BYTES(XFERSIZE), /* TransferSize = 1024 Byte*/ - 0x1A, /* bcdDFUVersion*/ - 0x01 - /***********************************************************/ - /* 9*/ -}; -#endif /* USE_USB_OTG_HS */ - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif - -__ALIGN_BEGIN static uint8_t usbd_dfu_Desc[USB_DFU_DESC_SIZ] __ALIGN_END = -{ - 0x09, /*blength = 9 Bytes*/ - DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/ - 0x0B, /*bmAttribute - bitCanDnload = 1 (bit 0) - bitCanUpload = 1 (bit 1) - bitManifestationTolerant = 0 (bit 2) - bitWillDetach = 1 (bit 3) - Reserved (bit4-6) - bitAcceleratedST = 0 (bit 7)*/ - 0xFF, /*DetachTimeOut= 255 ms*/ - 0x00, - /*WARNING: In DMA mode the multiple MPS packets feature is still not supported - ==> In this case, when using DMA XFERSIZE should be set to 64 in usbd_conf.h */ - TRANSFER_SIZE_BYTES(XFERSIZE), /* TransferSize = 1024 Byte*/ - 0x1A, /* bcdDFUVersion*/ - 0x01 -}; -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -/** - * @} - */ - -/** @defgroup usbd_dfu_Private_Functions - * @{ - */ - -/** - * @brief usbd_dfu_Init - * Initializes the DFU interface. - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t usbd_dfu_Init (void *pdev, - uint8_t cfgidx) -{ - /* Initilialize the MAL(Media Access Layer) */ - MAL_Init(); - - /* Initialize the state of the DFU interface */ - DeviceState = STATE_dfuIDLE; - DeviceStatus[0] = STATUS_OK; - DeviceStatus[4] = DeviceState; - - return USBD_OK; -} - -/** - * @brief usbd_dfu_Init - * De-initializes the DFU layer. - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t usbd_dfu_DeInit (void *pdev, - uint8_t cfgidx) -{ - /* Restore default state */ - DeviceState = STATE_dfuIDLE; - DeviceStatus[0] = STATUS_OK; - DeviceStatus[4] = DeviceState; - wBlockNum = 0; - wlength = 0; - - /* DeInitilialize the MAL(Media Access Layer) */ - MAL_DeInit(); - - return USBD_OK; -} - -/** - * @brief usbd_dfu_Setup - * Handles the DFU request parsing. - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t usbd_dfu_Setup (void *pdev, - USB_SETUP_REQ *req) -{ - uint16_t len = 0; - uint8_t *pbuf = NULL; - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - /* DFU Class Requests -------------------------------*/ - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) - { - case DFU_DNLOAD: - DFU_Req_DNLOAD(pdev, req); - break; - - case DFU_UPLOAD: - DFU_Req_UPLOAD(pdev, req); - break; - - case DFU_GETSTATUS: - DFU_Req_GETSTATUS(pdev); - break; - - case DFU_CLRSTATUS: - DFU_Req_CLRSTATUS(pdev); - break; - - case DFU_GETSTATE: - DFU_Req_GETSTATE(pdev); - break; - - case DFU_ABORT: - DFU_Req_ABORT(pdev); - break; - - case DFU_DETACH: - DFU_Req_DETACH(pdev, req); - break; - - default: - USBD_CtlError (pdev, req); - return USBD_FAIL; - } - break; - - /* Standard Requests -------------------------------*/ - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - if( (req->wValue >> 8) == DFU_DESCRIPTOR_TYPE) - { -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - pbuf = usbd_dfu_Desc; -#else - pbuf = usbd_dfu_CfgDesc + 9 + (9 * USBD_ITF_MAX_NUM); -#endif - len = MIN(USB_DFU_DESC_SIZ , req->wLength); - } - - USBD_CtlSendData (pdev, - pbuf, - len); - break; - - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - (uint8_t *)&usbd_dfu_AltSet, - 1); - break; - - case USB_REQ_SET_INTERFACE : - if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM) - { - usbd_dfu_AltSet = (uint8_t)(req->wValue); - } - else - { - /* Call the error management function (command will be nacked */ - USBD_CtlError (pdev, req); - } - break; - } - } - return USBD_OK; -} - -/** - * @brief EP0_TxSent - * Handles the DFU control endpoint data IN stage. - * @param pdev: device instance - * @retval status - */ -static uint8_t EP0_TxSent (void *pdev) -{ - uint32_t Addr; - USB_SETUP_REQ req; - - if (DeviceState == STATE_dfuDNBUSY) - { - /* Decode the Special Command*/ - if (wBlockNum == 0) - { - if ((MAL_Buffer[0] == CMD_GETCOMMANDS) && (wlength == 1)) - {} - else if (( MAL_Buffer[0] == CMD_SETADDRESSPOINTER ) && (wlength == 5)) - { - Pointer = MAL_Buffer[1]; - Pointer += MAL_Buffer[2] << 8; - Pointer += MAL_Buffer[3] << 16; - Pointer += MAL_Buffer[4] << 24; - } - else if (( MAL_Buffer[0] == CMD_ERASE ) && (wlength == 5)) - { - Pointer = MAL_Buffer[1]; - Pointer += MAL_Buffer[2] << 8; - Pointer += MAL_Buffer[3] << 16; - Pointer += MAL_Buffer[4] << 24; - MAL_Erase(Pointer); - } - else - { - /* Reset the global length and block number */ - wlength = 0; - wBlockNum = 0; - /* Call the error management function (command will be nacked) */ - req.bmRequest = 0; - req.wLength = 1; - USBD_CtlError (pdev, &req); - } - } - /* Regular Download Command */ - else if (wBlockNum > 1) - { - /* Decode the required address */ - Addr = ((wBlockNum - 2) * XFERSIZE) + Pointer; - - /* Preform the write operation */ - MAL_Write(Addr, wlength); - } - /* Reset the global lenght and block number */ - wlength = 0; - wBlockNum = 0; - - /* Update the state machine */ - DeviceState = STATE_dfuDNLOAD_SYNC; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - return USBD_OK; - } - else if (DeviceState == STATE_dfuMANIFEST)/* Manifestation in progress*/ - { - /* Start leaving DFU mode */ - DFU_LeaveDFUMode(pdev); - } - - return USBD_OK; -} - -/** - * @brief EP0_RxReady - * Handles the DFU control endpoint data OUT stage. - * @param pdev: device instance - * @retval status - */ -static uint8_t EP0_RxReady (void *pdev) -{ - return USBD_OK; -} - - -/****************************************************************************** - DFU Class requests management -******************************************************************************/ -/** - * @brief DFU_Req_DETACH - * Handles the DFU DETACH request. - * @param pdev: device instance - * @param req: pointer to the request structure. - * @retval None. - */ -static void DFU_Req_DETACH(void *pdev, USB_SETUP_REQ *req) -{ - if (DeviceState == STATE_dfuIDLE || DeviceState == STATE_dfuDNLOAD_SYNC - || DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuMANIFEST_SYNC - || DeviceState == STATE_dfuUPLOAD_IDLE ) - { - /* Update the state machine */ - DeviceState = STATE_dfuIDLE; - DeviceStatus[0] = STATUS_OK; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/ - DeviceStatus[4] = DeviceState; - DeviceStatus[5] = 0; /*iString*/ - wBlockNum = 0; - wlength = 0; - } - - /* Check the detach capability in the DFU functional descriptor */ - if ((usbd_dfu_CfgDesc[12 + (9 * USBD_ITF_MAX_NUM)]) & DFU_DETACH_MASK) - { - /* Perform an Attach-Detach operation on USB bus */ - DCD_DevDisconnect (pdev); - DCD_DevConnect (pdev); - } - else - { - /* Wait for the period of time specified in Detach request */ - USB_OTG_BSP_mDelay (req->wValue); - } -} - -/** - * @brief DFU_Req_DNLOAD - * Handles the DFU DNLOAD request. - * @param pdev: device instance - * @param req: pointer to the request structure - * @retval None - */ -static void DFU_Req_DNLOAD(void *pdev, USB_SETUP_REQ *req) -{ - /* Data setup request */ - if (req->wLength > 0) - { - if ((DeviceState == STATE_dfuIDLE) || (DeviceState == STATE_dfuDNLOAD_IDLE)) - { - /* Update the global length and block number */ - wBlockNum = req->wValue; - wlength = req->wLength; - - /* Update the state machine */ - DeviceState = STATE_dfuDNLOAD_SYNC; - DeviceStatus[4] = DeviceState; - - /* Prepare the reception of the buffer over EP0 */ - USBD_CtlPrepareRx (pdev, - (uint8_t*)MAL_Buffer, - wlength); - } - /* Unsupported state */ - else - { - /* Call the error management function (command will be nacked */ - USBD_CtlError (pdev, req); - } - } - /* 0 Data DNLOAD request */ - else - { - /* End of DNLOAD operation*/ - if (DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuIDLE ) - { - Manifest_State = Manifest_In_Progress; - DeviceState = STATE_dfuMANIFEST_SYNC; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - DeviceStatus[4] = DeviceState; - } - else - { - /* Call the error management function (command will be nacked */ - USBD_CtlError (pdev, req); - } - } -} - -/** - * @brief DFU_Req_UPLOAD - * Handles the DFU UPLOAD request. - * @param pdev: instance - * @param req: pointer to the request structure - * @retval status - */ -static void DFU_Req_UPLOAD(void *pdev, USB_SETUP_REQ *req) -{ - uint8_t *Phy_Addr = NULL; - uint32_t Addr = 0; - - /* Data setup request */ - if (req->wLength > 0) - { - if ((DeviceState == STATE_dfuIDLE) || (DeviceState == STATE_dfuUPLOAD_IDLE)) - { - /* Update the global langth and block number */ - wBlockNum = req->wValue; - wlength = req->wLength; - - /* DFU Get Command */ - if (wBlockNum == 0) - { - /* Update the state machine */ - DeviceState = (wlength > 3)? STATE_dfuIDLE:STATE_dfuUPLOAD_IDLE; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - - /* Store the values of all supported commands */ - MAL_Buffer[0] = CMD_GETCOMMANDS; - MAL_Buffer[1] = CMD_SETADDRESSPOINTER; - MAL_Buffer[2] = CMD_ERASE; - - /* Send the status data over EP0 */ - USBD_CtlSendData (pdev, - (uint8_t *)(&(MAL_Buffer[0])), - 3); - } - else if (wBlockNum > 1) - { - DeviceState = STATE_dfuUPLOAD_IDLE ; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - Addr = ((wBlockNum - 2) * XFERSIZE) + Pointer; /* Change is Accelerated*/ - - /* Return the physical address where data are stored */ - Phy_Addr = MAL_Read(Addr, wlength); - - /* Send the status data over EP0 */ - USBD_CtlSendData (pdev, - Phy_Addr, - wlength); - } - else /* unsupported wBlockNum */ - { - DeviceState = STATUS_ERRSTALLEDPKT; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - - /* Call the error management function (command will be nacked */ - USBD_CtlError (pdev, req); - } - } - /* Unsupported state */ - else - { - wlength = 0; - wBlockNum = 0; - /* Call the error management function (command will be nacked */ - USBD_CtlError (pdev, req); - } - } - /* No Data setup request */ - else - { - DeviceState = STATE_dfuIDLE; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - DeviceStatus[4] = DeviceState; - } -} - -/** - * @brief DFU_Req_GETSTATUS - * Handles the DFU GETSTATUS request. - * @param pdev: instance - * @retval status - */ -static void DFU_Req_GETSTATUS(void *pdev) -{ - switch (DeviceState) - { - case STATE_dfuDNLOAD_SYNC: - if (wlength != 0) - { - DeviceState = STATE_dfuDNBUSY; - DeviceStatus[4] = DeviceState; - if ((wBlockNum == 0) && (MAL_Buffer[0] == CMD_ERASE)) - { - MAL_GetStatus(Pointer, 0, DeviceStatus); - } - else - { - MAL_GetStatus(Pointer, 1, DeviceStatus); - } - } - else /* (wlength==0)*/ - { - DeviceState = STATE_dfuDNLOAD_IDLE; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - } - break; - - case STATE_dfuMANIFEST_SYNC : - if (Manifest_State == Manifest_In_Progress) - { - DeviceState = STATE_dfuMANIFEST; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 1; /*bwPollTimeout = 1ms*/ - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - //break; - } - else if ((Manifest_State == Manifest_complete) && \ - ((usbd_dfu_CfgDesc[(11 + (9 * USBD_ITF_MAX_NUM))]) & 0x04)) - { - DeviceState = STATE_dfuIDLE; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - //break; - } - break; - - default : - break; - } - - /* Send the status data over EP0 */ - USBD_CtlSendData (pdev, - (uint8_t *)(&(DeviceStatus[0])), - 6); -} - -/** - * @brief DFU_Req_CLRSTATUS - * Handles the DFU CLRSTATUS request. - * @param pdev: device instance - * @retval status - */ -static void DFU_Req_CLRSTATUS(void *pdev) -{ - if (DeviceState == STATE_dfuERROR) - { - DeviceState = STATE_dfuIDLE; - DeviceStatus[0] = STATUS_OK;/*bStatus*/ - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/ - DeviceStatus[4] = DeviceState;/*bState*/ - DeviceStatus[5] = 0;/*iString*/ - } - else - { /*State Error*/ - DeviceState = STATE_dfuERROR; - DeviceStatus[0] = STATUS_ERRUNKNOWN;/*bStatus*/ - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/ - DeviceStatus[4] = DeviceState;/*bState*/ - DeviceStatus[5] = 0;/*iString*/ - } -} - -/** - * @brief DFU_Req_GETSTATE - * Handles the DFU GETSTATE request. - * @param pdev: device instance - * @retval None - */ -static void DFU_Req_GETSTATE(void *pdev) -{ - /* Return the current state of the DFU interface */ - USBD_CtlSendData (pdev, - &DeviceState, - 1); -} - -/** - * @brief DFU_Req_ABORT - * Handles the DFU ABORT request. - * @param pdev: device instance - * @retval None - */ -static void DFU_Req_ABORT(void *pdev) -{ - if (DeviceState == STATE_dfuIDLE || DeviceState == STATE_dfuDNLOAD_SYNC - || DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuMANIFEST_SYNC - || DeviceState == STATE_dfuUPLOAD_IDLE ) - { - DeviceState = STATE_dfuIDLE; - DeviceStatus[0] = STATUS_OK; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/ - DeviceStatus[4] = DeviceState; - DeviceStatus[5] = 0; /*iString*/ - wBlockNum = 0; - wlength = 0; - } -} - -/** - * @brief DFU_LeaveDFUMode - * Handles the sub-protocol DFU leave DFU mode request (leaves DFU mode - * and resets device to jump to user loaded code). - * @param pdev: device instance - * @retval None - */ -void DFU_LeaveDFUMode(void *pdev) -{ - Manifest_State = Manifest_complete; - - if ((usbd_dfu_CfgDesc[(11 + (9 * USBD_ITF_MAX_NUM))]) & 0x04) - { - DeviceState = STATE_dfuMANIFEST_SYNC; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - return; - } - else - { - DeviceState = STATE_dfuMANIFEST_WAIT_RESET; - DeviceStatus[4] = DeviceState; - DeviceStatus[1] = 0; - DeviceStatus[2] = 0; - DeviceStatus[3] = 0; - - /* Disconnect the USB device */ - DCD_DevDisconnect (pdev); - - /* DeInitilialize the MAL(Media Access Layer) */ - MAL_DeInit(); - - /* Generate system reset to allow jumping to the user code */ - NVIC_SystemReset(); - - /* This instruction will not be reached (system reset) */ - return; - } -} - -/** - * @brief USBD_DFU_GetCfgDesc - * Returns configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_DFU_GetCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (usbd_dfu_CfgDesc); - return usbd_dfu_CfgDesc; -} - -#ifdef USB_OTG_HS_CORE -/** - * @brief USBD_DFU_GetOtherCfgDesc - * Returns other speed configuration descriptor. - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_DFU_GetOtherCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (usbd_dfu_OtherCfgDesc); - return usbd_dfu_OtherCfgDesc; -} -#endif - -/** - * @brief USBD_DFU_GetUsrStringDesc - * Manages the transfer of memory interfaces string descriptors. - * @param speed : current device speed - * @param index: desciptor index - * @param length : pointer data length - * @retval pointer to the descriptor table or NULL if the descriptor is not supported. - */ -static uint8_t* USBD_DFU_GetUsrStringDesc (uint8_t speed, uint8_t index , uint16_t *length) -{ - /* Check if the requested string interface is supported */ - if (index <= (USBD_IDX_INTERFACE_STR + USBD_ITF_MAX_NUM)) - { - - - USBD_GetString ((uint8_t *)usbd_dfu_StringDesc[index - USBD_IDX_INTERFACE_STR - 1], USBD_StrDesc, length); - return USBD_StrDesc; - } - /* Not supported Interface Descriptor index */ - else - { - return NULL; - } -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_mal.c b/example/stm32f4/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_mal.c deleted file mode 100644 index 3d301e93c..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_mal.c +++ /dev/null @@ -1,281 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_dfu_mal.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief Generic media access Layer. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_dfu_mal.h" - -#include "usbd_flash_if.h" - -#ifdef DFU_MAL_SUPPORT_OTP - #include "usbd_otp_if.h" -#endif - -#ifdef DFU_MAL_SUPPORT_MEM - #include "usbd_mem_if_template.h" -#endif - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Global Memories callback and string descriptors reference tables. - To add a new memory, modify the value of MAX_USED_MEDIA in usbd_dfu_mal.h - and add the pointer to the callback structure in this table. - Then add the pointer to the memory string descriptor in usbd_dfu_StringDesc table. - No other operation is required. */ -DFU_MAL_Prop_TypeDef* tMALTab[MAX_USED_MEDIA] = { - &DFU_Flash_cb -#ifdef DFU_MAL_SUPPORT_OTP - , &DFU_Otp_cb -#endif -#ifdef DFU_MAL_SUPPORT_MEM - , &DFU_Mem_cb -#endif -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -__ALIGN_BEGIN const uint8_t* usbd_dfu_StringDesc[MAX_USED_MEDIA] __ALIGN_END = { - FLASH_IF_STRING -#ifdef DFU_MAL_SUPPORT_OTP - , OTP_IF_STRING -#endif -#ifdef DFU_MAL_SUPPORT_MEM - , MEM_IF_STRING -#endif -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* RAM Buffer for Downloaded Data */ -__ALIGN_BEGIN uint8_t MAL_Buffer[XFERSIZE] __ALIGN_END ; - -/* Private function prototypes -----------------------------------------------*/ -static uint8_t MAL_CheckAdd (uint32_t Add); -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief MAL_Init - * Initializes the Media on the STM32 - * @param None - * @retval Result of the opeartion (MAL_OK in all cases) - */ -uint16_t MAL_Init(void) -{ - uint32_t memIdx = 0; - - /* Init all supported memories */ - for(memIdx = 0; memIdx < MAX_USED_MEDIA; memIdx++) - { - /* If the check addres is positive, exit with the memory index */ - if (tMALTab[memIdx]->pMAL_Init != NULL) - { - tMALTab[memIdx]->pMAL_Init(); - } - } - - return MAL_OK; -} - -/** - * @brief MAL_DeInit - * DeInitializes the Media on the STM32 - * @param None - * @retval Result of the opeartion (MAL_OK in all cases) - */ -uint16_t MAL_DeInit(void) -{ - uint32_t memIdx = 0; - - /* Init all supported memories */ - for(memIdx = 0; memIdx < MAX_USED_MEDIA; memIdx++) - { - /* Check if the command is supported */ - if (tMALTab[memIdx]->pMAL_DeInit != NULL) - { - tMALTab[memIdx]->pMAL_DeInit(); - } - } - - return MAL_OK; -} - -/** - * @brief MAL_Erase - * Erase a sector of memory. - * @param Add: Sector address/code - * @retval Result of the opeartion: MAL_OK if all operations are OK else MAL_FAIL - */ -uint16_t MAL_Erase(uint32_t Add) -{ - uint32_t memIdx = MAL_CheckAdd(Add); - - /* Check if the area is protected */ - if (DFU_MAL_IS_PROTECTED_AREA(Add)) - { - return MAL_FAIL; - } - - if (memIdx < MAX_USED_MEDIA) - { - /* Check if the command is supported */ - if (tMALTab[memIdx]->pMAL_Erase != NULL) - { - return tMALTab[memIdx]->pMAL_Erase(Add); - } - else - { - return MAL_FAIL; - } - } - else - { - return MAL_FAIL; - } -} - -/** - * @brief MAL_Write - * Write sectors of memory. - * @param Add: Sector address/code - * @param Len: Number of data to be written (in bytes) - * @retval Result of the opeartion: MAL_OK if all operations are OK else MAL_FAIL - */ -uint16_t MAL_Write (uint32_t Add, uint32_t Len) -{ - uint32_t memIdx = MAL_CheckAdd(Add); - - /* Check if the area is protected */ - if (DFU_MAL_IS_PROTECTED_AREA(Add)) - { - return MAL_FAIL; - } - - if (memIdx < MAX_USED_MEDIA) - { - /* Check if the command is supported */ - if (tMALTab[memIdx]->pMAL_Write != NULL) - { - return tMALTab[memIdx]->pMAL_Write(Add, Len); - } - else - { - return MAL_FAIL; - } - } - else - { - return MAL_FAIL; - } -} - -/** - * @brief MAL_Read - * Read sectors of memory. - * @param Add: Sector address/code - * @param Len: Number of data to be written (in bytes) - * @retval Buffer pointer - */ -uint8_t *MAL_Read (uint32_t Add, uint32_t Len) -{ - uint32_t memIdx = MAL_CheckAdd(Add); - - if (memIdx < MAX_USED_MEDIA) - { - /* Check if the command is supported */ - if (tMALTab[memIdx]->pMAL_Read != NULL) - { - return tMALTab[memIdx]->pMAL_Read(Add, Len); - } - else - { - return MAL_Buffer; - } - } - else - { - return MAL_Buffer; - } -} - -/** - * @brief MAL_GetStatus - * Get the status of a given memory. - * @param Add: Sector address/code (allow to determine which memory will be addressed) - * @param Cmd: 0 for erase and 1 for write - * @param buffer: pointer to the buffer where the status data will be stored. - * @retval Buffer pointer - */ -uint16_t MAL_GetStatus(uint32_t Add , uint8_t Cmd, uint8_t *buffer) -{ - uint32_t memIdx = MAL_CheckAdd(Add); - - if (memIdx < MAX_USED_MEDIA) - { - if (Cmd & 0x01) - { - SET_POLLING_TIMING(tMALTab[memIdx]->EraseTiming); - } - else - { - SET_POLLING_TIMING(tMALTab[memIdx]->WriteTiming); - } - - return MAL_OK; - } - else - { - return MAL_FAIL; - } -} - -/** - * @brief MAL_CheckAdd - * Determine which memory should be managed. - * @param Add: Sector address/code (allow to determine which memory will be addressed) - * @retval Index of the addressed memory. - */ -static uint8_t MAL_CheckAdd(uint32_t Add) -{ - uint32_t memIdx = 0; - - /* Check with all supported memories */ - for(memIdx = 0; memIdx < MAX_USED_MEDIA; memIdx++) - { - /* If the check addres is positive, exit with the memory index */ - if (tMALTab[memIdx]->pMAL_CheckAdd(Add) == MAL_OK) - { - return memIdx; - } - } - /* If no memory found, return MAX_USED_MEDIA */ - return (MAX_USED_MEDIA); -} - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/src/usbd_flash_if.c b/example/stm32f4/STM32_USB_Device_Library/Class/dfu/src/usbd_flash_if.c deleted file mode 100644 index d5604d837..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/src/usbd_flash_if.c +++ /dev/null @@ -1,221 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_flash_if.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief Specific media access Layer for internal flash. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_flash_if.h" -#include "usbd_dfu_mal.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ - -/* Private function prototypes -----------------------------------------------*/ -uint16_t FLASH_If_Init(void); -uint16_t FLASH_If_Erase (uint32_t Add); -uint16_t FLASH_If_Write (uint32_t Add, uint32_t Len); -uint8_t *FLASH_If_Read (uint32_t Add, uint32_t Len); -uint16_t FLASH_If_DeInit(void); -uint16_t FLASH_If_CheckAdd(uint32_t Add); - - -/* Private variables ---------------------------------------------------------*/ -DFU_MAL_Prop_TypeDef DFU_Flash_cb = - { - FLASH_IF_STRING, - FLASH_If_Init, - FLASH_If_DeInit, - FLASH_If_Erase, - FLASH_If_Write, - FLASH_If_Read, - FLASH_If_CheckAdd, - 50, /* Erase Time in ms */ - 50 /* Programming Time in ms */ - }; - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief FLASH_If_Init - * Memory initialization routine. - * @param None - * @retval MAL_OK if operation is successeful, MAL_FAIL else. - */ -uint16_t FLASH_If_Init(void) -{ - /* Unlock the internal flash */ - FLASH_Unlock(); - - return MAL_OK; -} - -/** - * @brief FLASH_If_DeInit - * Memory deinitialization routine. - * @param None - * @retval MAL_OK if operation is successeful, MAL_FAIL else. - */ -uint16_t FLASH_If_DeInit(void) -{ - /* Lock the internal flash */ - FLASH_Lock(); - - return MAL_OK; -} - -/******************************************************************************* -* Function Name : FLASH_If_Erase -* Description : Erase sector -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -uint16_t FLASH_If_Erase(uint32_t Add) -{ -#ifdef STM32F2XX - /* Check which sector has to be erased */ - if (Add < 0x08004000) - { - FLASH_EraseSector(FLASH_Sector_0, VoltageRange_3); - } - else if (Add < 0x08008000) - { - FLASH_EraseSector(FLASH_Sector_1, VoltageRange_3); - } - else if (Add < 0x0800C000) - { - FLASH_EraseSector(FLASH_Sector_2, VoltageRange_3); - } - else if (Add < 0x08010000) - { - FLASH_EraseSector(FLASH_Sector_3, VoltageRange_3); - } - else if (Add < 0x08020000) - { - FLASH_EraseSector(FLASH_Sector_4, VoltageRange_3); - } - else if (Add < 0x08040000) - { - FLASH_EraseSector(FLASH_Sector_5, VoltageRange_3); - } - else if (Add < 0x08060000) - { - FLASH_EraseSector(FLASH_Sector_6, VoltageRange_3); - } - else if (Add < 0x08080000) - { - FLASH_EraseSector(FLASH_Sector_7, VoltageRange_3); - } - else if (Add < 0x080A0000) - { - FLASH_EraseSector(FLASH_Sector_8, VoltageRange_3); - } - else if (Add < 0x080C0000) - { - FLASH_EraseSector(FLASH_Sector_9, VoltageRange_3); - } - else if (Add < 0x080E0000) - { - FLASH_EraseSector(FLASH_Sector_10, VoltageRange_3); - } - else if (Add < 0x08100000) - { - FLASH_EraseSector(FLASH_Sector_11, VoltageRange_3); - } - else - { - return MAL_FAIL; - } -#elif defined(STM32F10X_CL) - /* Call the standard Flash erase function */ - FLASH_ErasePage(Add); -#endif /* STM32F2XX */ - - return MAL_OK; -} - -/** - * @brief FLASH_If_Write - * Memory write routine. - * @param Add: Address to be written to. - * @param Len: Number of data to be written (in bytes). - * @retval MAL_OK if operation is successeful, MAL_FAIL else. - */ -uint16_t FLASH_If_Write(uint32_t Add, uint32_t Len) -{ - uint32_t idx = 0; - - if (Len & 0x3) /* Not an aligned data */ - { - for (idx = Len; idx < ((Len & 0xFFFC) + 4); idx++) - { - MAL_Buffer[idx] = 0xFF; - } - } - - /* Data received are Word multiple */ - for (idx = 0; idx < Len; idx = idx + 4) - { - FLASH_ProgramWord(Add, *(uint32_t *)(MAL_Buffer + idx)); - Add += 4; - } - return MAL_OK; -} - -/** - * @brief FLASH_If_Read - * Memory read routine. - * @param Add: Address to be read from. - * @param Len: Number of data to be read (in bytes). - * @retval Pointer to the phyisical address where data should be read. - */ -uint8_t *FLASH_If_Read (uint32_t Add, uint32_t Len) -{ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - uint32_t idx = 0; - for (idx = 0; idx < Len; idx += 4) - { - *(uint32_t*)(MAL_Buffer + idx) = *(uint32_t *)(Add + idx); - } - return (uint8_t*)(MAL_Buffer); -#else - return (uint8_t *)(Add); -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -} - -/** - * @brief FLASH_If_CheckAdd - * Check if the address is an allowed address for this memory. - * @param Add: Address to be checked. - * @param Len: Number of data to be read (in bytes). - * @retval MAL_OK if the address is allowed, MAL_FAIL else. - */ -uint16_t FLASH_If_CheckAdd(uint32_t Add) -{ - if ((Add >= FLASH_START_ADD) && (Add < FLASH_END_ADD)) - { - return MAL_OK; - } - else - { - return MAL_FAIL; - } -} -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/src/usbd_mem_if_template.c b/example/stm32f4/STM32_USB_Device_Library/Class/dfu/src/usbd_mem_if_template.c deleted file mode 100644 index 4295e40ff..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/src/usbd_mem_if_template.c +++ /dev/null @@ -1,133 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_mem_if_template.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief Specific media access Layer for a template memory. This file is - provided as template example showing how to implement a new memory - interface based on pre-defined API. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_mem_if_template.h" -#include "usbd_dfu_mal.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ - -/* Private function prototypes -----------------------------------------------*/ -uint16_t MEM_If_Init(void); -uint16_t MEM_If_Erase (uint32_t Add); -uint16_t MEM_If_Write (uint32_t Add, uint32_t Len); -uint8_t *MEM_If_Read (uint32_t Add, uint32_t Len); -uint16_t MEM_If_DeInit(void); -uint16_t MEM_If_CheckAdd(uint32_t Add); - - -/* Private variables ---------------------------------------------------------*/ -DFU_MAL_Prop_TypeDef DFU_Mem_cb = - { - MEM_IF_STRING, - MEM_If_Init, - MEM_If_DeInit, - MEM_If_Erase, - MEM_If_Write, - MEM_If_Read, - MEM_If_CheckAdd, - 10, /* Erase Time in ms */ - 10 /* Programming Time in ms */ - }; - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief MEM_If_Init - * Memory initialization routine. - * @param None - * @retval MAL_OK if operation is successeful, MAL_FAIL else. - */ -uint16_t MEM_If_Init(void) -{ - return MAL_OK; -} - -/** - * @brief MEM_If_DeInit - * Memory deinitialization routine. - * @param None - * @retval MAL_OK if operation is successeful, MAL_FAIL else. - */ -uint16_t MEM_If_DeInit(void) -{ - return MAL_OK; -} - -/** - * @brief MEM_If_Erase - * Erase sector. - * @param Add: Address of sector to be erased. - * @retval MAL_OK if operation is successeful, MAL_FAIL else. - */ -uint16_t MEM_If_Erase(uint32_t Add) -{ - return MAL_OK; -} - -/** - * @brief MEM_If_Write - * Memory write routine. - * @param Add: Address to be written to. - * @param Len: Number of data to be written (in bytes). - * @retval MAL_OK if operation is successeful, MAL_FAIL else. - */ -uint16_t MEM_If_Write(uint32_t Add, uint32_t Len) -{ - return MAL_OK; -} - -/** - * @brief MEM_If_Read - * Memory read routine. - * @param Add: Address to be read from. - * @param Len: Number of data to be read (in bytes). - * @retval Pointer to the phyisical address where data should be read. - */ -uint8_t *MEM_If_Read (uint32_t Add, uint32_t Len) -{ - /* Return a valid address to avoid HardFault */ - return (uint8_t*)(MAL_Buffer); -} - -/** - * @brief MEM_If_CheckAdd - * Check if the address is an allowed address for this memory. - * @param Add: Address to be checked. - * @param Len: Number of data to be read (in bytes). - * @retval MAL_OK if the address is allowed, MAL_FAIL else. - */ -uint16_t MEM_If_CheckAdd(uint32_t Add) -{ - if ((Add >= MEM_START_ADD) && (Add < MEM_END_ADD)) - { - return MAL_OK; - } - else - { - return MAL_FAIL; - } -} -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/src/usbd_otp_if.c b/example/stm32f4/STM32_USB_Device_Library/Class/dfu/src/usbd_otp_if.c deleted file mode 100644 index 5970c0ea3..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/dfu/src/usbd_otp_if.c +++ /dev/null @@ -1,120 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_otp_if.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief Specific media access Layer for OTP (One Time Programming) memory. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_otp_if.h" -#include "usbd_dfu_mal.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ - -/* Private function prototypes -----------------------------------------------*/ -uint16_t OTP_If_Write (uint32_t Add, uint32_t Len); -uint8_t *OTP_If_Read (uint32_t Add, uint32_t Len); -uint16_t OTP_If_DeInit(void); -uint16_t OTP_If_CheckAdd(uint32_t Add); - - -/* Private variables ---------------------------------------------------------*/ -DFU_MAL_Prop_TypeDef DFU_Otp_cb = - { - OTP_IF_STRING, - NULL, /* Init not supported*/ - NULL, /* DeInit not supported */ - NULL, /* Erase not supported */ - OTP_If_Write, - OTP_If_Read, - OTP_If_CheckAdd, - 1, /* Erase Time in ms */ - 10 /* Programming Time in ms */ - }; - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief OTP_If_Write - * Memory write routine. - * @param Add: Address to be written to. - * @param Len: Number of data to be written (in bytes). - * @retval MAL_OK if operation is successeful, MAL_FAIL else. - */ -uint16_t OTP_If_Write(uint32_t Add, uint32_t Len) -{ - uint32_t idx = 0; - - if (Len & 0x3) /* Not an aligned data */ - { - for (idx = Len; idx < ((Len & 0xFFFC) + 4); idx++) - { - MAL_Buffer[idx] = 0xFF; - } - } - - /* Data received are Word multiple */ - for (idx = 0; idx < Len; idx = idx + 4) - { - FLASH_ProgramWord(Add, *(uint32_t *)(MAL_Buffer + idx)); - Add += 4; - } - return MAL_OK; -} - -/** - * @brief OTP_If_Read - * Memory read routine. - * @param Add: Address to be read from. - * @param Len: Number of data to be read (in bytes). - * @retval Pointer to the phyisical address where data should be read. - */ -uint8_t *OTP_If_Read (uint32_t Add, uint32_t Len) -{ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - uint32_t idx = 0; - for (idx = 0; idx < Len; idx += 4) - { - *(uint32_t*)(MAL_Buffer + idx) = *(uint32_t *)(Add + idx); - } - return (uint8_t*)(MAL_Buffer); -#else - return (uint8_t*)(Add); -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -} - -/** - * @brief OTP_If_CheckAdd - * Check if the address is an allowed address for this memory. - * @param Add: Address to be checked. - * @param Len: Number of data to be read (in bytes). - * @retval MAL_OK if the address is allowed, MAL_FAIL else. - */ -uint16_t OTP_If_CheckAdd(uint32_t Add) -{ - if ((Add >= OTP_START_ADD) && (Add < OTP_END_ADD)) - { - return MAL_OK; - } - else - { - return MAL_FAIL; - } -} -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/hid/inc/usbd_hid_core.h b/example/stm32f4/STM32_USB_Device_Library/Class/hid/inc/usbd_hid_core.h deleted file mode 100644 index d93fc77d6..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/hid/inc/usbd_hid_core.h +++ /dev/null @@ -1,110 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_hid_core.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief header file for the usbd_hid_core.c file. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ - -#ifndef __USB_HID_CORE_H_ -#define __USB_HID_CORE_H_ - -#include "usbd_ioreq.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_HID - * @brief This file is the Header file for USBD_msc.c - * @{ - */ - - -/** @defgroup USBD_HID_Exported_Defines - * @{ - */ -#define USB_HID_CONFIG_DESC_SIZ 34 -#define USB_HID_DESC_SIZ 9 -#define HID_MOUSE_REPORT_DESC_SIZE 74 - -#define HID_DESCRIPTOR_TYPE 0x21 -#define HID_REPORT_DESC 0x22 - - -#define HID_REQ_SET_PROTOCOL 0x0B -#define HID_REQ_GET_PROTOCOL 0x03 - -#define HID_REQ_SET_IDLE 0x0A -#define HID_REQ_GET_IDLE 0x02 - -#define HID_REQ_SET_REPORT 0x09 -#define HID_REQ_GET_REPORT 0x01 -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -extern USBD_Class_cb_TypeDef USBD_HID_cb; -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Functions - * @{ - */ -uint8_t USBD_HID_SendReport (USB_OTG_CORE_HANDLE *pdev, - uint8_t *report, - uint16_t len); -/** - * @} - */ - -#endif // __USB_HID_CORE_H_ -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/hid/src/usbd_hid_core.c b/example/stm32f4/STM32_USB_Device_Library/Class/hid/src/usbd_hid_core.c deleted file mode 100644 index a56c5ed49..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/hid/src/usbd_hid_core.c +++ /dev/null @@ -1,460 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_hid_core.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief This file provides the HID core functions. - * - * @verbatim - * - * =================================================================== - * HID Class Description - * =================================================================== - * This module manages the HID class V1.11 following the "Device Class Definition - * for Human Interface Devices (HID) Version 1.11 Jun 27, 2001". - * This driver implements the following aspects of the specification: - * - The Boot Interface Subclass - * - The Mouse protocol - * - Usage Page : Generic Desktop - * - Usage : Joystick) - * - Collection : Application - * - * @note In HS mode and when the DMA is used, all variables and data structures - * dealing with the DMA during the transaction process should be 32-bit aligned. - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_hid_core.h" -#include "usbd_desc.h" -#include "usbd_req.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_HID - * @brief usbd core module - * @{ - */ - -/** @defgroup USBD_HID_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_HID_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_HID_Private_Macros - * @{ - */ -/** - * @} - */ - - - - -/** @defgroup USBD_HID_Private_FunctionPrototypes - * @{ - */ - - -static uint8_t USBD_HID_Init (void *pdev, - uint8_t cfgidx); - -static uint8_t USBD_HID_DeInit (void *pdev, - uint8_t cfgidx); - -static uint8_t USBD_HID_Setup (void *pdev, - USB_SETUP_REQ *req); - -static uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length); - -static uint8_t USBD_HID_DataIn (void *pdev, uint8_t epnum); -/** - * @} - */ - -/** @defgroup USBD_HID_Private_Variables - * @{ - */ - -USBD_Class_cb_TypeDef USBD_HID_cb = -{ - USBD_HID_Init, - USBD_HID_DeInit, - USBD_HID_Setup, - NULL, /*EP0_TxSent*/ - NULL, /*EP0_RxReady*/ - USBD_HID_DataIn, /*DataIn*/ - NULL, /*DataOut*/ - NULL, /*SOF */ - NULL, - NULL, - USBD_HID_GetCfgDesc, -#ifdef USB_OTG_HS_CORE - USBD_HID_GetCfgDesc, /* use same config as per FS */ -#endif -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint32_t USBD_HID_AltSet __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint32_t USBD_HID_Protocol __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint32_t USBD_HID_IdleState __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB HID device Configuration Descriptor */ -__ALIGN_BEGIN static uint8_t USBD_HID_CfgDesc[USB_HID_CONFIG_DESC_SIZ] __ALIGN_END = -{ - 0x09, /* bLength: Configuration Descriptor size */ - USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */ - USB_HID_CONFIG_DESC_SIZ, - /* wTotalLength: Bytes returned */ - 0x00, - 0x01, /*bNumInterfaces: 1 interface*/ - 0x01, /*bConfigurationValue: Configuration value*/ - 0x00, /*iConfiguration: Index of string descriptor describing - the configuration*/ - 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */ - 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/ - - /************** Descriptor of Joystick Mouse interface ****************/ - /* 09 */ - 0x09, /*bLength: Interface Descriptor size*/ - USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/ - 0x00, /*bInterfaceNumber: Number of Interface*/ - 0x00, /*bAlternateSetting: Alternate setting*/ - 0x01, /*bNumEndpoints*/ - 0x03, /*bInterfaceClass: HID*/ - 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/ - 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/ - 0, /*iInterface: Index of string descriptor*/ - /******************** Descriptor of Joystick Mouse HID ********************/ - /* 18 */ - 0x09, /*bLength: HID Descriptor size*/ - HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/ - 0x11, /*bcdHID: HID Class Spec release number*/ - 0x01, - 0x00, /*bCountryCode: Hardware target country*/ - 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/ - 0x22, /*bDescriptorType*/ - HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/ - 0x00, - /******************** Descriptor of Mouse endpoint ********************/ - /* 27 */ - 0x07, /*bLength: Endpoint Descriptor size*/ - USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/ - - HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/ - 0x03, /*bmAttributes: Interrupt endpoint*/ - HID_IN_PACKET, /*wMaxPacketSize: 4 Byte max */ - 0x00, - 0x0A, /*bInterval: Polling Interval (10 ms)*/ - /* 34 */ -} ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] __ALIGN_END = -{ - 0x05, 0x01, - 0x09, 0x02, - 0xA1, 0x01, - 0x09, 0x01, - - 0xA1, 0x00, - 0x05, 0x09, - 0x19, 0x01, - 0x29, 0x03, - - 0x15, 0x00, - 0x25, 0x01, - 0x95, 0x03, - 0x75, 0x01, - - 0x81, 0x02, - 0x95, 0x01, - 0x75, 0x05, - 0x81, 0x01, - - 0x05, 0x01, - 0x09, 0x30, - 0x09, 0x31, - 0x09, 0x38, - - 0x15, 0x81, - 0x25, 0x7F, - 0x75, 0x08, - 0x95, 0x03, - - 0x81, 0x06, - 0xC0, 0x09, - 0x3c, 0x05, - 0xff, 0x09, - - 0x01, 0x15, - 0x00, 0x25, - 0x01, 0x75, - 0x01, 0x95, - - 0x02, 0xb1, - 0x22, 0x75, - 0x06, 0x95, - 0x01, 0xb1, - - 0x01, 0xc0 -}; - -/** - * @} - */ - -/** @defgroup USBD_HID_Private_Functions - * @{ - */ - -/** - * @brief USBD_HID_Init - * Initialize the HID interface - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_HID_Init (void *pdev, - uint8_t cfgidx) -{ - - /* Open EP IN */ - DCD_EP_Open(pdev, - HID_IN_EP, - HID_IN_PACKET, - USB_OTG_EP_INT); - - /* Open EP OUT */ - DCD_EP_Open(pdev, - HID_OUT_EP, - HID_OUT_PACKET, - USB_OTG_EP_INT); - - return USBD_OK; -} - -/** - * @brief USBD_HID_Init - * DeInitialize the HID layer - * @param pdev: device instance - * @param cfgidx: Configuration index - * @retval status - */ -static uint8_t USBD_HID_DeInit (void *pdev, - uint8_t cfgidx) -{ - /* Close HID EPs */ - DCD_EP_Close (pdev , HID_IN_EP); - DCD_EP_Close (pdev , HID_OUT_EP); - - - return USBD_OK; -} - -/** - * @brief USBD_HID_Setup - * Handle the HID specific requests - * @param pdev: instance - * @param req: usb requests - * @retval status - */ -static uint8_t USBD_HID_Setup (void *pdev, - USB_SETUP_REQ *req) -{ - uint16_t len = 0; - uint8_t *pbuf = NULL; - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) - { - - - case HID_REQ_SET_PROTOCOL: - USBD_HID_Protocol = (uint8_t)(req->wValue); - break; - - case HID_REQ_GET_PROTOCOL: - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_HID_Protocol, - 1); - break; - - case HID_REQ_SET_IDLE: - USBD_HID_IdleState = (uint8_t)(req->wValue >> 8); - break; - - case HID_REQ_GET_IDLE: - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_HID_IdleState, - 1); - break; - - default: - USBD_CtlError (pdev, req); - return USBD_FAIL; - } - break; - - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - if( req->wValue >> 8 == HID_REPORT_DESC) - { - len = MIN(HID_MOUSE_REPORT_DESC_SIZE , req->wLength); - pbuf = HID_MOUSE_ReportDesc; - } - else if( req->wValue >> 8 == HID_DESCRIPTOR_TYPE) - { - -//#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED -// pbuf = USBD_HID_Desc; -//#else - pbuf = USBD_HID_CfgDesc + 0x12; -//#endif - len = MIN(USB_HID_DESC_SIZ , req->wLength); - } - - USBD_CtlSendData (pdev, - pbuf, - len); - - break; - - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_HID_AltSet, - 1); - break; - - case USB_REQ_SET_INTERFACE : - USBD_HID_AltSet = (uint8_t)(req->wValue); - break; - } - } - return USBD_OK; -} - -/** - * @brief USBD_HID_SendReport - * Send HID Report - * @param pdev: device instance - * @param buff: pointer to report - * @retval status - */ -uint8_t USBD_HID_SendReport (USB_OTG_CORE_HANDLE *pdev, - uint8_t *report, - uint16_t len) -{ - if (pdev->dev.device_status == USB_OTG_CONFIGURED ) - { - DCD_EP_Tx (pdev, HID_IN_EP, report, len); - } - return USBD_OK; -} - -/** - * @brief USBD_HID_GetCfgDesc - * return configuration descriptor - * @param speed : current device speed - * @param length : pointer data length - * @retval pointer to descriptor buffer - */ -static uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (USBD_HID_CfgDesc); - return USBD_HID_CfgDesc; -} - -/** - * @brief USBD_HID_DataIn - * handle data IN Stage - * @param pdev: device instance - * @param epnum: endpoint index - * @retval status - */ -static uint8_t USBD_HID_DataIn (void *pdev, - uint8_t epnum) -{ - - /* Ensure that the FIFO is empty before a new transfer, this condition could - be caused by a new transfer before the end of the previous transfer */ - DCD_EP_Flush(pdev, HID_IN_EP); - return USBD_OK; -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_bot.h b/example/stm32f4/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_bot.h deleted file mode 100644 index 64b6d262c..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_bot.h +++ /dev/null @@ -1,147 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_bot.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief header for the usbd_msc_bot.c file - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#include "usbd_core.h" - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_MSC_BOT_H -#define __USBD_MSC_BOT_H - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup MSC_BOT - * @brief This file is the Header file for usbd_bot.c - * @{ - */ - - -/** @defgroup USBD_CORE_Exported_Defines - * @{ - */ -#define BOT_IDLE 0 /* Idle state */ -#define BOT_DATA_OUT 1 /* Data Out state */ -#define BOT_DATA_IN 2 /* Data In state */ -#define BOT_LAST_DATA_IN 3 /* Last Data In Last */ -#define BOT_SEND_DATA 4 /* Send Immediate data */ - -#define BOT_CBW_SIGNATURE 0x43425355 -#define BOT_CSW_SIGNATURE 0x53425355 -#define BOT_CBW_LENGTH 31 -#define BOT_CSW_LENGTH 13 - -/* CSW Status Definitions */ -#define CSW_CMD_PASSED 0x00 -#define CSW_CMD_FAILED 0x01 -#define CSW_PHASE_ERROR 0x02 - -/* BOT Status */ -#define BOT_STATE_NORMAL 0 -#define BOT_STATE_RECOVERY 1 -#define BOT_STATE_ERROR 2 - - -#define DIR_IN 0 -#define DIR_OUT 1 -#define BOTH_DIR 2 - -/** - * @} - */ - -/** @defgroup MSC_CORE_Private_TypesDefinitions - * @{ - */ - -typedef struct _MSC_BOT_CBW -{ - uint32_t dSignature; - uint32_t dTag; - uint32_t dDataLength; - uint8_t bmFlags; - uint8_t bLUN; - uint8_t bCBLength; - uint8_t CB[16]; -} -MSC_BOT_CBW_TypeDef; - - -typedef struct _MSC_BOT_CSW -{ - uint32_t dSignature; - uint32_t dTag; - uint32_t dDataResidue; - uint8_t bStatus; -} -MSC_BOT_CSW_TypeDef; - -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_Types - * @{ - */ - -extern uint8_t MSC_BOT_Data[]; -extern uint16_t MSC_BOT_DataLen; -extern uint8_t MSC_BOT_State; -extern uint8_t MSC_BOT_BurstMode; -extern MSC_BOT_CBW_TypeDef MSC_BOT_cbw; -extern MSC_BOT_CSW_TypeDef MSC_BOT_csw; -/** - * @} - */ -/** @defgroup USBD_CORE_Exported_FunctionsPrototypes - * @{ - */ -void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev); -void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev); -void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev); -void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); - -void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); - -void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev, - uint8_t CSW_Status); - -void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -/** - * @} - */ - -#endif /* __USBD_MSC_BOT_H */ -/** - * @} - */ - -/** -* @} -*/ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_core.h b/example/stm32f4/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_core.h deleted file mode 100644 index be1d401e2..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_core.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_core.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief header for the usbd_msc_core.c file - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef _USB_MSC_CORE_H_ -#define _USB_MSC_CORE_H_ - -#include "usbd_ioreq.h" - -/** @addtogroup USBD_MSC_BOT - * @{ - */ - -/** @defgroup USBD_MSC - * @brief This file is the Header file for USBD_msc.c - * @{ - */ - - -/** @defgroup USBD_BOT_Exported_Defines - * @{ - */ - - -#define BOT_GET_MAX_LUN 0xFE -#define BOT_RESET 0xFF -#define USB_MSC_CONFIG_DESC_SIZ 32 - -#define MSC_EPIN_SIZE *(uint16_t *)(((USB_OTG_CORE_HANDLE *)pdev)->dev.pConfig_descriptor + 22) - -#define MSC_EPOUT_SIZE *(uint16_t *)(((USB_OTG_CORE_HANDLE *)pdev)->dev.pConfig_descriptor + 29) - -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Types - * @{ - */ - -extern USBD_Class_cb_TypeDef USBD_MSC_cb; -/** - * @} - */ - -/** - * @} - */ -#endif // _USB_MSC_CORE_H_ -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_data.h b/example/stm32f4/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_data.h deleted file mode 100644 index e0a677f88..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_data.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_data.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief header for the usbd_msc_data.c file - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef _USBD_MSC_DATA_H_ -#define _USBD_MSC_DATA_H_ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_conf.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USB_INFO - * @brief general defines for the usb device library file - * @{ - */ - -/** @defgroup USB_INFO_Exported_Defines - * @{ - */ -#define MODE_SENSE6_LEN 8 -#define MODE_SENSE10_LEN 8 -#define LENGTH_INQUIRY_PAGE00 7 -#define LENGTH_FORMAT_CAPACITIES 20 - -/** - * @} - */ - - -/** @defgroup USBD_INFO_Exported_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_INFO_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_INFO_Exported_Variables - * @{ - */ -extern const uint8_t MSC_Page00_Inquiry_Data[]; -extern const uint8_t MSC_Mode_Sense6_data[]; -extern const uint8_t MSC_Mode_Sense10_data[] ; - -/** - * @} - */ - -/** @defgroup USBD_INFO_Exported_FunctionsPrototype - * @{ - */ - -/** - * @} - */ - -#endif /* _USBD_MSC_DATA_H_ */ - -/** - * @} - */ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_mem.h b/example/stm32f4/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_mem.h deleted file mode 100644 index 811e9ee8b..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_mem.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_mem.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief header for the STORAGE DISK file file - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USBD_MEM_H -#define __USBD_MEM_H -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_MEM - * @brief header file for the storage disk file - * @{ - */ - -/** @defgroup USBD_MEM_Exported_Defines - * @{ - */ -#define USBD_STD_INQUIRY_LENGTH 36 -/** - * @} - */ - - -/** @defgroup USBD_MEM_Exported_TypesDefinitions - * @{ - */ - -typedef struct _USBD_STORAGE -{ - int8_t (* Init) (uint8_t lun); - int8_t (* GetCapacity) (uint8_t lun, uint32_t *block_num, uint32_t *block_size); - int8_t (* IsReady) (uint8_t lun); - int8_t (* IsWriteProtected) (uint8_t lun); - int8_t (* Read) (uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); - int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len); - int8_t (* GetMaxLun)(void); - int8_t *pInquiry; - -}USBD_STORAGE_cb_TypeDef; -/** - * @} - */ - - - -/** @defgroup USBD_MEM_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_MEM_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_MEM_Exported_FunctionsPrototype - * @{ - */ -extern USBD_STORAGE_cb_TypeDef *USBD_STORAGE_fops; -/** - * @} - */ - -#endif /* __USBD_MEM_H */ -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_scsi.h b/example/stm32f4/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_scsi.h deleted file mode 100644 index 5ba83ad1d..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_scsi.h +++ /dev/null @@ -1,189 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_scsi.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief header for the usbd_msc_scsi.c file - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_MSC_SCSI_H -#define __USBD_MSC_SCSI_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_SCSI - * @brief header file for the storage disk file - * @{ - */ - -/** @defgroup USBD_SCSI_Exported_Defines - * @{ - */ - -#define SENSE_LIST_DEEPTH 4 - -/* SCSI Commands */ -#define SCSI_FORMAT_UNIT 0x04 -#define SCSI_INQUIRY 0x12 -#define SCSI_MODE_SELECT6 0x15 -#define SCSI_MODE_SELECT10 0x55 -#define SCSI_MODE_SENSE6 0x1A -#define SCSI_MODE_SENSE10 0x5A -#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1E -#define SCSI_READ6 0x08 -#define SCSI_READ10 0x28 -#define SCSI_READ12 0xA8 -#define SCSI_READ16 0x88 - -#define SCSI_READ_CAPACITY10 0x25 -#define SCSI_READ_CAPACITY16 0x9E - -#define SCSI_REQUEST_SENSE 0x03 -#define SCSI_START_STOP_UNIT 0x1B -#define SCSI_TEST_UNIT_READY 0x00 -#define SCSI_WRITE6 0x0A -#define SCSI_WRITE10 0x2A -#define SCSI_WRITE12 0xAA -#define SCSI_WRITE16 0x8A - -#define SCSI_VERIFY10 0x2F -#define SCSI_VERIFY12 0xAF -#define SCSI_VERIFY16 0x8F - -#define SCSI_SEND_DIAGNOSTIC 0x1D -#define SCSI_READ_FORMAT_CAPACITIES 0x23 - -#define NO_SENSE 0 -#define RECOVERED_ERROR 1 -#define NOT_READY 2 -#define MEDIUM_ERROR 3 -#define HARDWARE_ERROR 4 -#define ILLEGAL_REQUEST 5 -#define UNIT_ATTENTION 6 -#define DATA_PROTECT 7 -#define BLANK_CHECK 8 -#define VENDOR_SPECIFIC 9 -#define COPY_ABORTED 10 -#define ABORTED_COMMAND 11 -#define VOLUME_OVERFLOW 13 -#define MISCOMPARE 14 - - -#define INVALID_CDB 0x20 -#define INVALID_FIELED_IN_COMMAND 0x24 -#define PARAMETER_LIST_LENGTH_ERROR 0x1A -#define INVALID_FIELD_IN_PARAMETER_LIST 0x26 -#define ADDRESS_OUT_OF_RANGE 0x21 -#define MEDIUM_NOT_PRESENT 0x3A -#define MEDIUM_HAVE_CHANGED 0x28 -#define WRITE_PROTECTED 0x27 -#define UNRECOVERED_READ_ERROR 0x11 -#define WRITE_FAULT 0x03 - -#define READ_FORMAT_CAPACITY_DATA_LEN 0x0C -#define READ_CAPACITY10_DATA_LEN 0x08 -#define MODE_SENSE10_DATA_LEN 0x08 -#define MODE_SENSE6_DATA_LEN 0x04 -#define REQUEST_SENSE_DATA_LEN 0x12 -#define STANDARD_INQUIRY_DATA_LEN 0x24 -#define BLKVFY 0x04 - -extern uint8_t Page00_Inquiry_Data[]; -extern uint8_t Standard_Inquiry_Data[]; -extern uint8_t Standard_Inquiry_Data2[]; -extern uint8_t Mode_Sense6_data[]; -extern uint8_t Mode_Sense10_data[]; -extern uint8_t Scsi_Sense_Data[]; -extern uint8_t ReadCapacity10_Data[]; -extern uint8_t ReadFormatCapacity_Data []; -/** - * @} - */ - - -/** @defgroup USBD_SCSI_Exported_TypesDefinitions - * @{ - */ - -typedef struct _SENSE_ITEM { - char Skey; - union { - struct _ASCs { - char ASC; - char ASCQ; - }b; - unsigned int ASC; - char *pData; - } w; -} SCSI_Sense_TypeDef; -/** - * @} - */ - -/** @defgroup USBD_SCSI_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_SCSI_Exported_Variables - * @{ - */ -extern SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; -extern uint8_t SCSI_Sense_Head; -extern uint8_t SCSI_Sense_Tail; - -/** - * @} - */ -/** @defgroup USBD_SCSI_Exported_FunctionsPrototype - * @{ - */ -int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev, - uint8_t lun, - uint8_t *cmd); - -void SCSI_SenseCode(uint8_t lun, - uint8_t sKey, - uint8_t ASC); - -/** - * @} - */ - -#endif /* __USBD_MSC_SCSI_H */ -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c b/example/stm32f4/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c deleted file mode 100644 index 01c88ddda..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c +++ /dev/null @@ -1,393 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_bot.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief This file provides all the BOT protocol core functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_bot.h" -#include "usbd_msc_scsi.h" -#include "usbd_ioreq.h" -#include "usbd_msc_mem.h" -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup MSC_BOT - * @brief BOT protocol module - * @{ - */ - -/** @defgroup MSC_BOT_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Variables - * @{ - */ -uint16_t MSC_BOT_DataLen; -uint8_t MSC_BOT_State; -uint8_t MSC_BOT_Status; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET] __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN MSC_BOT_CBW_TypeDef MSC_BOT_cbw __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN MSC_BOT_CSW_TypeDef MSC_BOT_csw __ALIGN_END ; -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_FunctionPrototypes - * @{ - */ -static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev); - -static void MSC_BOT_SendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t* pbuf, - uint16_t len); - -static void MSC_BOT_Abort(USB_OTG_CORE_HANDLE *pdev); -/** - * @} - */ - - -/** @defgroup MSC_BOT_Private_Functions - * @{ - */ - - - -/** -* @brief MSC_BOT_Init -* Initialize the BOT Process -* @param pdev: device instance -* @retval None -*/ -void MSC_BOT_Init (USB_OTG_CORE_HANDLE *pdev) -{ - MSC_BOT_State = BOT_IDLE; - MSC_BOT_Status = BOT_STATE_NORMAL; - USBD_STORAGE_fops->Init(0); - - DCD_EP_Flush(pdev, MSC_OUT_EP); - DCD_EP_Flush(pdev, MSC_IN_EP); - /* Prapare EP to Receive First BOT Cmd */ - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); -} - -/** -* @brief MSC_BOT_Reset -* Reset the BOT Machine -* @param pdev: device instance -* @retval None -*/ -void MSC_BOT_Reset (USB_OTG_CORE_HANDLE *pdev) -{ - MSC_BOT_State = BOT_IDLE; - MSC_BOT_Status = BOT_STATE_RECOVERY; - /* Prapare EP to Receive First BOT Cmd */ - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); -} - -/** -* @brief MSC_BOT_DeInit -* Uninitialize the BOT Machine -* @param pdev: device instance -* @retval None -*/ -void MSC_BOT_DeInit (USB_OTG_CORE_HANDLE *pdev) -{ - MSC_BOT_State = BOT_IDLE; -} - -/** -* @brief MSC_BOT_DataIn -* Handle BOT IN data stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval None -*/ -void MSC_BOT_DataIn (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum) -{ - - switch (MSC_BOT_State) - { - case BOT_DATA_IN: - if(SCSI_ProcessCmd(pdev, - MSC_BOT_cbw.bLUN, - &MSC_BOT_cbw.CB[0]) < 0) - { - MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); - } - break; - - case BOT_SEND_DATA: - case BOT_LAST_DATA_IN: - MSC_BOT_SendCSW (pdev, CSW_CMD_PASSED); - - break; - - default: - break; - } -} -/** -* @brief MSC_BOT_DataOut -* Proccess MSC OUT data -* @param pdev: device instance -* @param epnum: endpoint index -* @retval None -*/ -void MSC_BOT_DataOut (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum) -{ - switch (MSC_BOT_State) - { - case BOT_IDLE: - MSC_BOT_CBW_Decode(pdev); - break; - - case BOT_DATA_OUT: - - if(SCSI_ProcessCmd(pdev, - MSC_BOT_cbw.bLUN, - &MSC_BOT_cbw.CB[0]) < 0) - { - MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); - } - - break; - - default: - break; - } - -} - -/** -* @brief MSC_BOT_CBW_Decode -* Decode the CBW command and set the BOT state machine accordingtly -* @param pdev: device instance -* @retval None -*/ -static void MSC_BOT_CBW_Decode (USB_OTG_CORE_HANDLE *pdev) -{ - - MSC_BOT_csw.dTag = MSC_BOT_cbw.dTag; - MSC_BOT_csw.dDataResidue = MSC_BOT_cbw.dDataLength; - - if ((USBD_GetRxCount (pdev ,MSC_OUT_EP) != BOT_CBW_LENGTH) || - (MSC_BOT_cbw.dSignature != BOT_CBW_SIGNATURE)|| - (MSC_BOT_cbw.bLUN > 1) || - (MSC_BOT_cbw.bCBLength < 1) || - (MSC_BOT_cbw.bCBLength > 16)) - { - - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - MSC_BOT_Status = BOT_STATE_ERROR; - MSC_BOT_Abort(pdev); - - } - else - { - if(SCSI_ProcessCmd(pdev, - MSC_BOT_cbw.bLUN, - &MSC_BOT_cbw.CB[0]) < 0) - { - MSC_BOT_Abort(pdev); - } - /*Burst xfer handled internally*/ - else if ((MSC_BOT_State != BOT_DATA_IN) && - (MSC_BOT_State != BOT_DATA_OUT) && - (MSC_BOT_State != BOT_LAST_DATA_IN)) - { - if (MSC_BOT_DataLen > 0) - { - MSC_BOT_SendData(pdev, - MSC_BOT_Data, - MSC_BOT_DataLen); - } - else if (MSC_BOT_DataLen == 0) - { - MSC_BOT_SendCSW (pdev, - CSW_CMD_PASSED); - } - } - } -} - -/** -* @brief MSC_BOT_SendData -* Send the requested data -* @param pdev: device instance -* @param buf: pointer to data buffer -* @param len: Data Length -* @retval None -*/ -static void MSC_BOT_SendData(USB_OTG_CORE_HANDLE *pdev, - uint8_t* buf, - uint16_t len) -{ - - len = MIN (MSC_BOT_cbw.dDataLength, len); - MSC_BOT_csw.dDataResidue -= len; - MSC_BOT_csw.bStatus = CSW_CMD_PASSED; - MSC_BOT_State = BOT_SEND_DATA; - - DCD_EP_Tx (pdev, MSC_IN_EP, buf, len); -} - -/** -* @brief MSC_BOT_SendCSW -* Send the Command Status Wrapper -* @param pdev: device instance -* @param status : CSW status -* @retval None -*/ -void MSC_BOT_SendCSW (USB_OTG_CORE_HANDLE *pdev, - uint8_t CSW_Status) -{ - MSC_BOT_csw.dSignature = BOT_CSW_SIGNATURE; - MSC_BOT_csw.bStatus = CSW_Status; - MSC_BOT_State = BOT_IDLE; - - DCD_EP_Tx (pdev, - MSC_IN_EP, - (uint8_t *)&MSC_BOT_csw, - BOT_CSW_LENGTH); - - /* Prapare EP to Receive next Cmd */ - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); - -} - -/** -* @brief MSC_BOT_Abort -* Abort the current transfer -* @param pdev: device instance -* @retval status -*/ - -static void MSC_BOT_Abort (USB_OTG_CORE_HANDLE *pdev) -{ - - if ((MSC_BOT_cbw.bmFlags == 0) && - (MSC_BOT_cbw.dDataLength != 0) && - (MSC_BOT_Status == BOT_STATE_NORMAL) ) - { - DCD_EP_Stall(pdev, MSC_OUT_EP ); - } - DCD_EP_Stall(pdev, MSC_IN_EP); - - if(MSC_BOT_Status == BOT_STATE_ERROR) - { - DCD_EP_PrepareRx (pdev, - MSC_OUT_EP, - (uint8_t *)&MSC_BOT_cbw, - BOT_CBW_LENGTH); - } -} - -/** -* @brief MSC_BOT_CplClrFeature -* Complete the clear feature request -* @param pdev: device instance -* @param epnum: endpoint index -* @retval None -*/ - -void MSC_BOT_CplClrFeature (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - if(MSC_BOT_Status == BOT_STATE_ERROR )/* Bad CBW Signature */ - { - DCD_EP_Stall(pdev, MSC_IN_EP); - MSC_BOT_Status = BOT_STATE_NORMAL; - } - else if(((epnum & 0x80) == 0x80) && ( MSC_BOT_Status != BOT_STATE_RECOVERY)) - { - MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED); - } - -} -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c b/example/stm32f4/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c deleted file mode 100644 index cf03ef4de..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c +++ /dev/null @@ -1,490 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_core.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief This file provides all the MSC core functions. - * - * @verbatim - * - * =================================================================== - * MSC Class Description - * =================================================================== - * This module manages the MSC class V1.0 following the "Universal - * Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0 - * Sep. 31, 1999". - * This driver implements the following aspects of the specification: - * - Bulk-Only Transport protocol - * - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3)) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_mem.h" -#include "usbd_msc_core.h" -#include "usbd_msc_bot.h" -#include "usbd_req.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup MSC_CORE - * @brief Mass storage core module - * @{ - */ - -/** @defgroup MSC_CORE_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_CORE_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup MSC_CORE_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_CORE_Private_FunctionPrototypes - * @{ - */ -uint8_t USBD_MSC_Init (void *pdev, - uint8_t cfgidx); - -uint8_t USBD_MSC_DeInit (void *pdev, - uint8_t cfgidx); - -uint8_t USBD_MSC_Setup (void *pdev, - USB_SETUP_REQ *req); - -uint8_t USBD_MSC_DataIn (void *pdev, - uint8_t epnum); - - -uint8_t USBD_MSC_DataOut (void *pdev, - uint8_t epnum); - -uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, - uint16_t *length); - -#ifdef USB_OTG_HS_CORE -uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed, - uint16_t *length); -#endif - - -uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ]; - - - - -/** - * @} - */ - - -/** @defgroup MSC_CORE_Private_Variables - * @{ - */ - - -USBD_Class_cb_TypeDef USBD_MSC_cb = -{ - USBD_MSC_Init, - USBD_MSC_DeInit, - USBD_MSC_Setup, - NULL, /*EP0_TxSent*/ - NULL, /*EP0_RxReady*/ - USBD_MSC_DataIn, - USBD_MSC_DataOut, - NULL, /*SOF */ - NULL, - NULL, - USBD_MSC_GetCfgDesc, -#ifdef USB_OTG_HS_CORE - USBD_MSC_GetOtherCfgDesc, -#endif -}; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -/* USB Mass storage device Configuration Descriptor */ -/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */ -__ALIGN_BEGIN uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */ - USB_MSC_CONFIG_DESC_SIZ, - - 0x00, - 0x01, /* bNumInterfaces: 1 interface */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ - - /******************** Mass Storage interface ********************/ - 0x09, /* bLength: Interface Descriptor size */ - 0x04, /* bDescriptorType: */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints*/ - 0x08, /* bInterfaceClass: MSC Class */ - 0x06, /* bInterfaceSubClass : SCSI transparent*/ - 0x50, /* nInterfaceProtocol */ - 0x05, /* iInterface: */ - /******************** Mass Storage Endpoints ********************/ - 0x07, /*Endpoint descriptor length = 7*/ - 0x05, /*Endpoint descriptor type */ - MSC_IN_EP, /*Endpoint address (IN, address 1) */ - 0x02, /*Bulk endpoint type */ - LOBYTE(MSC_MAX_PACKET), - HIBYTE(MSC_MAX_PACKET), - 0x00, /*Polling interval in milliseconds */ - - 0x07, /*Endpoint descriptor length = 7 */ - 0x05, /*Endpoint descriptor type */ - MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ - 0x02, /*Bulk endpoint type */ - LOBYTE(MSC_MAX_PACKET), - HIBYTE(MSC_MAX_PACKET), - 0x00 /*Polling interval in milliseconds*/ -}; -#ifdef USB_OTG_HS_CORE - #ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif - #endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t USBD_MSC_OtherCfgDesc[USB_MSC_CONFIG_DESC_SIZ] __ALIGN_END = -{ - - 0x09, /* bLength: Configuation Descriptor size */ - USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION, - USB_MSC_CONFIG_DESC_SIZ, - - 0x00, - 0x01, /* bNumInterfaces: 1 interface */ - 0x01, /* bConfigurationValue: */ - 0x04, /* iConfiguration: */ - 0xC0, /* bmAttributes: */ - 0x32, /* MaxPower 100 mA */ - - /******************** Mass Storage interface ********************/ - 0x09, /* bLength: Interface Descriptor size */ - 0x04, /* bDescriptorType: */ - 0x00, /* bInterfaceNumber: Number of Interface */ - 0x00, /* bAlternateSetting: Alternate setting */ - 0x02, /* bNumEndpoints*/ - 0x08, /* bInterfaceClass: MSC Class */ - 0x06, /* bInterfaceSubClass : SCSI transparent command set*/ - 0x50, /* nInterfaceProtocol */ - 0x05, /* iInterface: */ - /******************** Mass Storage Endpoints ********************/ - 0x07, /*Endpoint descriptor length = 7*/ - 0x05, /*Endpoint descriptor type */ - MSC_IN_EP, /*Endpoint address (IN, address 1) */ - 0x02, /*Bulk endpoint type */ - 0x40, - 0x00, - 0x00, /*Polling interval in milliseconds */ - - 0x07, /*Endpoint descriptor length = 7 */ - 0x05, /*Endpoint descriptor type */ - MSC_OUT_EP, /*Endpoint address (OUT, address 1) */ - 0x02, /*Bulk endpoint type */ - 0x40, - 0x00, - 0x00 /*Polling interval in milliseconds*/ -}; -#endif - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint8_t USBD_MSC_MaxLun __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN static uint8_t USBD_MSC_AltSet __ALIGN_END = 0; - -/** - * @} - */ - - -/** @defgroup MSC_CORE_Private_Functions - * @{ - */ - -/** -* @brief USBD_MSC_Init -* Initialize the mass storage configuration -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status -*/ -uint8_t USBD_MSC_Init (void *pdev, - uint8_t cfgidx) -{ - USBD_MSC_DeInit(pdev , cfgidx ); - - /* Open EP IN */ - DCD_EP_Open(pdev, - MSC_IN_EP, - MSC_EPIN_SIZE, - USB_OTG_EP_BULK); - - /* Open EP OUT */ - DCD_EP_Open(pdev, - MSC_OUT_EP, - MSC_EPOUT_SIZE, - USB_OTG_EP_BULK); - - /* Init the BOT layer */ - MSC_BOT_Init(pdev); - - return USBD_OK; -} - -/** -* @brief USBD_MSC_DeInit -* DeInitilaize the mass storage configuration -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status -*/ -uint8_t USBD_MSC_DeInit (void *pdev, - uint8_t cfgidx) -{ - /* Close MSC EPs */ - DCD_EP_Close (pdev , MSC_IN_EP); - DCD_EP_Close (pdev , MSC_OUT_EP); - - /* Un Init the BOT layer */ - MSC_BOT_DeInit(pdev); - return USBD_OK; -} -/** -* @brief USBD_MSC_Setup -* Handle the MSC specific requests -* @param pdev: device instance -* @param req: USB request -* @retval status -*/ -uint8_t USBD_MSC_Setup (void *pdev, USB_SETUP_REQ *req) -{ - - switch (req->bmRequest & USB_REQ_TYPE_MASK) - { - - /* Class request */ - case USB_REQ_TYPE_CLASS : - switch (req->bRequest) - { - case BOT_GET_MAX_LUN : - - if((req->wValue == 0) && - (req->wLength == 1) && - ((req->bmRequest & 0x80) == 0x80)) - { - USBD_MSC_MaxLun = USBD_STORAGE_fops->GetMaxLun(); - if(USBD_MSC_MaxLun > 0) - { - USBD_CtlSendData (pdev, - &USBD_MSC_MaxLun, - 1); - } - else - { - USBD_CtlError(pdev , req); - return USBD_FAIL; - - } - } - else - { - USBD_CtlError(pdev , req); - return USBD_FAIL; - } - break; - - case BOT_RESET : - if((req->wValue == 0) && - (req->wLength == 0) && - ((req->bmRequest & 0x80) != 0x80)) - { - MSC_BOT_Reset(pdev); - } - else - { - USBD_CtlError(pdev , req); - return USBD_FAIL; - } - break; - - default: - USBD_CtlError(pdev , req); - return USBD_FAIL; - } - break; - /* Interface & Endpoint request */ - case USB_REQ_TYPE_STANDARD: - switch (req->bRequest) - { - case USB_REQ_GET_INTERFACE : - USBD_CtlSendData (pdev, - &USBD_MSC_AltSet, - 1); - break; - - case USB_REQ_SET_INTERFACE : - USBD_MSC_AltSet = (uint8_t)(req->wValue); - break; - - case USB_REQ_CLEAR_FEATURE: - - /* Flush the FIFO and Clear the stall status */ - DCD_EP_Flush(pdev, (uint8_t)req->wIndex); - - /* Re-activate the EP */ - DCD_EP_Close (pdev , (uint8_t)req->wIndex); - if((((uint8_t)req->wIndex) & 0x80) == 0x80) - { - DCD_EP_Open(pdev, - ((uint8_t)req->wIndex), - MSC_EPIN_SIZE, - USB_OTG_EP_BULK); - } - else - { - DCD_EP_Open(pdev, - ((uint8_t)req->wIndex), - MSC_EPOUT_SIZE, - USB_OTG_EP_BULK); - } - - /* Handle BOT error */ - MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex); - break; - - } - break; - - default: - break; - } - return USBD_OK; -} - -/** -* @brief USBD_MSC_DataIn -* handle data IN Stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -uint8_t USBD_MSC_DataIn (void *pdev, - uint8_t epnum) -{ - MSC_BOT_DataIn(pdev , epnum); - return USBD_OK; -} - -/** -* @brief USBD_MSC_DataOut -* handle data OUT Stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -uint8_t USBD_MSC_DataOut (void *pdev, - uint8_t epnum) -{ - MSC_BOT_DataOut(pdev , epnum); - return USBD_OK; -} - -/** -* @brief USBD_MSC_GetCfgDesc -* return configuration descriptor -* @param speed : current device speed -* @param length : pointer data length -* @retval pointer to descriptor buffer -*/ -uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, uint16_t *length) -{ - *length = sizeof (USBD_MSC_CfgDesc); - return USBD_MSC_CfgDesc; -} - -/** -* @brief USBD_MSC_GetOtherCfgDesc -* return other speed configuration descriptor -* @param speed : current device speed -* @param length : pointer data length -* @retval pointer to descriptor buffer -*/ -#ifdef USB_OTG_HS_CORE -uint8_t *USBD_MSC_GetOtherCfgDesc (uint8_t speed, - uint16_t *length) -{ - *length = sizeof (USBD_MSC_OtherCfgDesc); - return USBD_MSC_OtherCfgDesc; -} -#endif -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/msc/src/usbd_msc_data.c b/example/stm32f4/STM32_USB_Device_Library/Class/msc/src/usbd_msc_data.c deleted file mode 100644 index b5b0f2db5..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/msc/src/usbd_msc_data.c +++ /dev/null @@ -1,128 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_data.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief This file provides all the vital inquiry pages and sense data. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_data.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup MSC_DATA - * @brief Mass storage info/data module - * @{ - */ - -/** @defgroup MSC_DATA_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Variables - * @{ - */ - - -/* USB Mass storage Page 0 Inquiry Data */ -const uint8_t MSC_Page00_Inquiry_Data[] = {//7 - 0x00, - 0x00, - 0x00, - (LENGTH_INQUIRY_PAGE00 - 4), - 0x00, - 0x80, - 0x83 -}; -/* USB Mass storage sense 6 Data */ -const uint8_t MSC_Mode_Sense6_data[] = { - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 -}; -/* USB Mass storage sense 10 Data */ -const uint8_t MSC_Mode_Sense10_data[] = { - 0x00, - 0x06, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00, - 0x00 -}; -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_DATA_Private_Functions - * @{ - */ - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/msc/src/usbd_msc_scsi.c b/example/stm32f4/STM32_USB_Device_Library/Class/msc/src/usbd_msc_scsi.c deleted file mode 100644 index 8cff583bd..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/msc/src/usbd_msc_scsi.c +++ /dev/null @@ -1,722 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_msc_scsi.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief This file provides all the USBD SCSI layer functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_bot.h" -#include "usbd_msc_scsi.h" -#include "usbd_msc_mem.h" -#include "usbd_msc_data.h" - - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup MSC_SCSI - * @brief Mass storage SCSI layer module - * @{ - */ - -/** @defgroup MSC_SCSI_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Variables - * @{ - */ - -SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH]; -uint8_t SCSI_Sense_Head; -uint8_t SCSI_Sense_Tail; - -uint32_t SCSI_blk_size; -uint32_t SCSI_blk_nbr; - -uint32_t SCSI_blk_addr; -uint32_t SCSI_blk_len; - -USB_OTG_CORE_HANDLE *cdev; -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_FunctionPrototypes - * @{ - */ -static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params); -static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params); -static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params); -static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params); -static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params); -static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params); -static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params); -static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params); -static int8_t SCSI_Write10(uint8_t lun , uint8_t *params); -static int8_t SCSI_Read10(uint8_t lun , uint8_t *params); -static int8_t SCSI_Verify10(uint8_t lun, uint8_t *params); -static int8_t SCSI_CheckAddressRange (uint8_t lun , - uint32_t blk_offset , - uint16_t blk_nbr); -static int8_t SCSI_ProcessRead (uint8_t lun); - -static int8_t SCSI_ProcessWrite (uint8_t lun); -/** - * @} - */ - - -/** @defgroup MSC_SCSI_Private_Functions - * @{ - */ - - -/** -* @brief SCSI_ProcessCmd -* Process SCSI commands -* @param pdev: device instance -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -int8_t SCSI_ProcessCmd(USB_OTG_CORE_HANDLE *pdev, - uint8_t lun, - uint8_t *params) -{ - cdev = pdev; - - switch (params[0]) - { - case SCSI_TEST_UNIT_READY: - return SCSI_TestUnitReady(lun, params); - - case SCSI_REQUEST_SENSE: - return SCSI_RequestSense (lun, params); - case SCSI_INQUIRY: - return SCSI_Inquiry(lun, params); - - case SCSI_START_STOP_UNIT: - return SCSI_StartStopUnit(lun, params); - - case SCSI_ALLOW_MEDIUM_REMOVAL: - return SCSI_StartStopUnit(lun, params); - - case SCSI_MODE_SENSE6: - return SCSI_ModeSense6 (lun, params); - - case SCSI_MODE_SENSE10: - return SCSI_ModeSense10 (lun, params); - - case SCSI_READ_FORMAT_CAPACITIES: - return SCSI_ReadFormatCapacity(lun, params); - - case SCSI_READ_CAPACITY10: - return SCSI_ReadCapacity10(lun, params); - - case SCSI_READ10: - return SCSI_Read10(lun, params); - - case SCSI_WRITE10: - return SCSI_Write10(lun, params); - - case SCSI_VERIFY10: - return SCSI_Verify10(lun, params); - - default: - SCSI_SenseCode(lun, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } -} - - -/** -* @brief SCSI_TestUnitReady -* Process SCSI Test Unit Ready Command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params) -{ - - /* case 9 : Hi > D0 */ - if (MSC_BOT_cbw.dDataLength != 0) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - if(USBD_STORAGE_fops->IsReady(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - MSC_BOT_DataLen = 0; - return 0; -} - -/** -* @brief SCSI_Inquiry -* Process Inquiry command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params) -{ - uint8_t* pPage; - uint16_t len; - - if (params[1] & 0x01)/*Evpd is set*/ - { - pPage = (uint8_t *)MSC_Page00_Inquiry_Data; - len = LENGTH_INQUIRY_PAGE00; - } - else - { - - pPage = (uint8_t *)&USBD_STORAGE_fops->pInquiry[lun * USBD_STD_INQUIRY_LENGTH]; - len = pPage[4] + 5; - - if (params[4] <= len) - { - len = params[4]; - } - } - MSC_BOT_DataLen = len; - - while (len) - { - len--; - MSC_BOT_Data[len] = pPage[len]; - } - return 0; -} - -/** -* @brief SCSI_ReadCapacity10 -* Process Read Capacity 10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params) -{ - - if(USBD_STORAGE_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - else - { - - MSC_BOT_Data[0] = (uint8_t)(SCSI_blk_nbr - 1 >> 24); - MSC_BOT_Data[1] = (uint8_t)(SCSI_blk_nbr - 1 >> 16); - MSC_BOT_Data[2] = (uint8_t)(SCSI_blk_nbr - 1 >> 8); - MSC_BOT_Data[3] = (uint8_t)(SCSI_blk_nbr - 1); - - MSC_BOT_Data[4] = (uint8_t)(SCSI_blk_size >> 24); - MSC_BOT_Data[5] = (uint8_t)(SCSI_blk_size >> 16); - MSC_BOT_Data[6] = (uint8_t)(SCSI_blk_size >> 8); - MSC_BOT_Data[7] = (uint8_t)(SCSI_blk_size); - - MSC_BOT_DataLen = 8; - return 0; - } -} -/** -* @brief SCSI_ReadFormatCapacity -* Process Read Format Capacity command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params) -{ - - uint32_t blk_size; - uint32_t blk_nbr; - uint16_t i; - - for(i=0 ; i < 12 ; i++) - { - MSC_BOT_Data[i] = 0; - } - - if(USBD_STORAGE_fops->GetCapacity(lun, &blk_nbr, &blk_size) != 0) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - else - { - MSC_BOT_Data[3] = 0x08; - MSC_BOT_Data[4] = (uint8_t)(blk_nbr - 1 >> 24); - MSC_BOT_Data[5] = (uint8_t)(blk_nbr - 1 >> 16); - MSC_BOT_Data[6] = (uint8_t)(blk_nbr - 1 >> 8); - MSC_BOT_Data[7] = (uint8_t)(blk_nbr - 1); - - MSC_BOT_Data[8] = 0x02; - MSC_BOT_Data[9] = (uint8_t)(blk_size >> 16); - MSC_BOT_Data[10] = (uint8_t)(blk_size >> 8); - MSC_BOT_Data[11] = (uint8_t)(blk_size); - - MSC_BOT_DataLen = 12; - return 0; - } -} -/** -* @brief SCSI_ModeSense6 -* Process Mode Sense6 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params) -{ - - uint16_t len = 8 ; - MSC_BOT_DataLen = len; - - while (len) - { - len--; - MSC_BOT_Data[len] = MSC_Mode_Sense6_data[len]; - } - return 0; -} - -/** -* @brief SCSI_ModeSense10 -* Process Mode Sense10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params) -{ - uint16_t len = 8; - - MSC_BOT_DataLen = len; - - while (len) - { - len--; - MSC_BOT_Data[len] = MSC_Mode_Sense10_data[len]; - } - return 0; -} - -/** -* @brief SCSI_RequestSense -* Process Request Sense command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ - -static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params) -{ - uint8_t i; - - for(i=0 ; i < REQUEST_SENSE_DATA_LEN ; i++) - { - MSC_BOT_Data[i] = 0; - } - - MSC_BOT_Data[0] = 0x70; - MSC_BOT_Data[7] = REQUEST_SENSE_DATA_LEN - 6; - - if((SCSI_Sense_Head != SCSI_Sense_Tail)) { - - MSC_BOT_Data[2] = SCSI_Sense[SCSI_Sense_Head].Skey; - MSC_BOT_Data[12] = SCSI_Sense[SCSI_Sense_Head].w.b.ASCQ; - MSC_BOT_Data[13] = SCSI_Sense[SCSI_Sense_Head].w.b.ASC; - SCSI_Sense_Head++; - - if (SCSI_Sense_Head == SENSE_LIST_DEEPTH) - { - SCSI_Sense_Head = 0; - } - } - MSC_BOT_DataLen = REQUEST_SENSE_DATA_LEN; - - if (params[4] <= REQUEST_SENSE_DATA_LEN) - { - MSC_BOT_DataLen = params[4]; - } - return 0; -} - -/** -* @brief SCSI_SenseCode -* Load the last error code in the error list -* @param lun: Logical unit number -* @param sKey: Sense Key -* @param ASC: Additional Sense Key -* @retval none - -*/ -void SCSI_SenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC) -{ - SCSI_Sense[SCSI_Sense_Tail].Skey = sKey; - SCSI_Sense[SCSI_Sense_Tail].w.ASC = ASC << 8; - SCSI_Sense_Tail++; - if (SCSI_Sense_Tail == SENSE_LIST_DEEPTH) - { - SCSI_Sense_Tail = 0; - } -} -/** -* @brief SCSI_StartStopUnit -* Process Start Stop Unit command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params) -{ - MSC_BOT_DataLen = 0; - return 0; -} - -/** -* @brief SCSI_Read10 -* Process Read10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ -static int8_t SCSI_Read10(uint8_t lun , uint8_t *params) -{ - if(MSC_BOT_State == BOT_IDLE) /* Idle */ - { - - /* case 10 : Ho <> Di */ - - if ((MSC_BOT_cbw.bmFlags & 0x80) != 0x80) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - if(USBD_STORAGE_fops->IsReady(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - - SCSI_blk_addr = (params[2] << 24) | \ - (params[3] << 16) | \ - (params[4] << 8) | \ - params[5]; - - SCSI_blk_len = (params[7] << 8) | \ - params[8]; - - - - if( SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) - { - return -1; /* error */ - } - - MSC_BOT_State = BOT_DATA_IN; - SCSI_blk_addr *= SCSI_blk_size; - SCSI_blk_len *= SCSI_blk_size; - - /* cases 4,5 : Hi <> Dn */ - if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - } - MSC_BOT_DataLen = MSC_MEDIA_PACKET; - - return SCSI_ProcessRead(lun); -} - -/** -* @brief SCSI_Write10 -* Process Write10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ - -static int8_t SCSI_Write10 (uint8_t lun , uint8_t *params) -{ - if (MSC_BOT_State == BOT_IDLE) /* Idle */ - { - - /* case 8 : Hi <> Do */ - - if ((MSC_BOT_cbw.bmFlags & 0x80) == 0x80) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - /* Check whether Media is ready */ - if(USBD_STORAGE_fops->IsReady(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - MEDIUM_NOT_PRESENT); - return -1; - } - - /* Check If media is write-protected */ - if(USBD_STORAGE_fops->IsWriteProtected(lun) !=0 ) - { - SCSI_SenseCode(lun, - NOT_READY, - WRITE_PROTECTED); - return -1; - } - - - SCSI_blk_addr = (params[2] << 24) | \ - (params[3] << 16) | \ - (params[4] << 8) | \ - params[5]; - SCSI_blk_len = (params[7] << 8) | \ - params[8]; - - /* check if LBA address is in the right range */ - if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) - { - return -1; /* error */ - } - - SCSI_blk_addr *= SCSI_blk_size; - SCSI_blk_len *= SCSI_blk_size; - - /* cases 3,11,13 : Hn,Ho <> D0 */ - if (MSC_BOT_cbw.dDataLength != SCSI_blk_len) - { - SCSI_SenseCode(MSC_BOT_cbw.bLUN, - ILLEGAL_REQUEST, - INVALID_CDB); - return -1; - } - - /* Prepare EP to receive first data packet */ - MSC_BOT_State = BOT_DATA_OUT; - DCD_EP_PrepareRx (cdev, - MSC_OUT_EP, - MSC_BOT_Data, - MIN (SCSI_blk_len, MSC_MEDIA_PACKET)); - } - else /* Write Process ongoing */ - { - return SCSI_ProcessWrite(lun); - } - return 0; -} - - -/** -* @brief SCSI_Verify10 -* Process Verify10 command -* @param lun: Logical unit number -* @param params: Command parameters -* @retval status -*/ - -static int8_t SCSI_Verify10(uint8_t lun , uint8_t *params){ - if ((params[1]& 0x02) == 0x02) - { - SCSI_SenseCode (lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND); - return -1; /* Error, Verify Mode Not supported*/ - } - - if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0) - { - return -1; /* error */ - } - MSC_BOT_DataLen = 0; - return 0; -} - -/** -* @brief SCSI_CheckAddressRange -* Check address range -* @param lun: Logical unit number -* @param blk_offset: first block address -* @param blk_nbr: number of block to be processed -* @retval status -*/ -static int8_t SCSI_CheckAddressRange (uint8_t lun , uint32_t blk_offset , uint16_t blk_nbr) -{ - - if ((blk_offset + blk_nbr) > SCSI_blk_nbr ) - { - SCSI_SenseCode(lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE); - return -1; - } - return 0; -} - -/** -* @brief SCSI_ProcessRead -* Handle Read Process -* @param lun: Logical unit number -* @retval status -*/ -static int8_t SCSI_ProcessRead (uint8_t lun) -{ - uint32_t len; - - len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET); - - if( USBD_STORAGE_fops->Read(lun , - MSC_BOT_Data, - SCSI_blk_addr / SCSI_blk_size, - len / SCSI_blk_size) < 0) - { - - SCSI_SenseCode(lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR); - return -1; - } - - - DCD_EP_Tx (cdev, - MSC_IN_EP, - MSC_BOT_Data, - len); - - - SCSI_blk_addr += len; - SCSI_blk_len -= len; - - /* case 6 : Hi = Di */ - MSC_BOT_csw.dDataResidue -= len; - - if (SCSI_blk_len == 0) - { - MSC_BOT_State = BOT_LAST_DATA_IN; - } - return 0; -} - -/** -* @brief SCSI_ProcessWrite -* Handle Write Process -* @param lun: Logical unit number -* @retval status -*/ - -static int8_t SCSI_ProcessWrite (uint8_t lun) -{ - uint32_t len; - - len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET); - - if(USBD_STORAGE_fops->Write(lun , - MSC_BOT_Data, - SCSI_blk_addr / SCSI_blk_size, - len / SCSI_blk_size) < 0) - { - SCSI_SenseCode(lun, HARDWARE_ERROR, WRITE_FAULT); - return -1; - } - - - SCSI_blk_addr += len; - SCSI_blk_len -= len; - - /* case 12 : Ho = Do */ - MSC_BOT_csw.dDataResidue -= len; - - if (SCSI_blk_len == 0) - { - MSC_BOT_SendCSW (cdev, CSW_CMD_PASSED); - } - else - { - /* Prapare EP to Receive next packet */ - DCD_EP_PrepareRx (cdev, - MSC_OUT_EP, - MSC_BOT_Data, - MIN (SCSI_blk_len, MSC_MEDIA_PACKET)); - } - - return 0; -} -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Class/msc/src/usbd_storage_template.c b/example/stm32f4/STM32_USB_Device_Library/Class/msc/src/usbd_storage_template.c deleted file mode 100644 index 927e9dd45..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Class/msc/src/usbd_storage_template.c +++ /dev/null @@ -1,179 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_storage_template.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief Memory management layer - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_msc_mem.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Extern function prototypes ------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -#define STORAGE_LUN_NBR 1 - -int8_t STORAGE_Init (uint8_t lun); - -int8_t STORAGE_GetCapacity (uint8_t lun, - uint32_t *block_num, - uint16_t *block_size); - -int8_t STORAGE_IsReady (uint8_t lun); - -int8_t STORAGE_IsWriteProtected (uint8_t lun); - -int8_t STORAGE_Read (uint8_t lun, - uint8_t *buf, - uint32_t blk_addr, - uint16_t blk_len); - -int8_t STORAGE_Write (uint8_t lun, - uint8_t *buf, - uint32_t blk_addr, - uint16_t blk_len); - -int8_t STORAGE_GetMaxLun (void); - -/* USB Mass storage Standard Inquiry Data */ -const int8_t STORAGE_Inquirydata[] = {//36 - - /* LUN 0 */ - 0x00, - 0x80, - 0x02, - 0x02, - (USBD_STD_INQUIRY_LENGTH - 5), - 0x00, - 0x00, - 0x00, - 'S', 'T', 'M', ' ', ' ', ' ', ' ', ' ', /* Manufacturer : 8 bytes */ - 'P', 'r', 'o', 'd', 'u', 't', ' ', ' ', /* Product : 16 Bytes */ - ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', - '0', '.', '0' ,'1', /* Version : 4 Bytes */ -}; - -USBD_STORAGE_cb_TypeDef USBD_MICRO_SDIO_fops = -{ - STORAGE_Init, - STORAGE_GetCapacity, - STORAGE_IsReady, - STORAGE_IsWriteProtected, - STORAGE_Read, - STORAGE_Write, - STORAGE_GetMaxLun, - STORAGE_Inquirydata, - -}; - -USBD_STORAGE_cb_TypeDef *USBD_STORAGE_fops = &USBD_MICRO_SDIO_fops; -/******************************************************************************* -* Function Name : Read_Memory -* Description : Handle the Read operation from the microSD card. -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -int8_t STORAGE_Init (uint8_t lun) -{ - return (0); -} - -/******************************************************************************* -* Function Name : Read_Memory -* Description : Handle the Read operation from the STORAGE card. -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -int8_t STORAGE_GetCapacity (uint8_t lun, uint32_t *block_num, uint16_t *block_size) -{ - return (0); -} - -/******************************************************************************* -* Function Name : Read_Memory -* Description : Handle the Read operation from the STORAGE card. -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -int8_t STORAGE_IsReady (uint8_t lun) -{ - return (0); -} - -/******************************************************************************* -* Function Name : Read_Memory -* Description : Handle the Read operation from the STORAGE card. -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -int8_t STORAGE_IsWriteProtected (uint8_t lun) -{ - return 0; -} - -/******************************************************************************* -* Function Name : Read_Memory -* Description : Handle the Read operation from the STORAGE card. -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -int8_t STORAGE_Read (uint8_t lun, - uint8_t *buf, - uint32_t blk_addr, - uint16_t blk_len) -{ - return 0; -} -/******************************************************************************* -* Function Name : Write_Memory -* Description : Handle the Write operation to the STORAGE card. -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -int8_t STORAGE_Write (uint8_t lun, - uint8_t *buf, - uint32_t blk_addr, - uint16_t blk_len) -{ - return (0); -} -/******************************************************************************* -* Function Name : Write_Memory -* Description : Handle the Write operation to the STORAGE card. -* Input : None. -* Output : None. -* Return : None. -*******************************************************************************/ -int8_t STORAGE_GetMaxLun (void) -{ - return (STORAGE_LUN_NBR - 1); -} - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_conf_template.h b/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_conf_template.h deleted file mode 100644 index 34cd39d11..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_conf_template.h +++ /dev/null @@ -1,78 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_conf_template.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief usb device configuration template file - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CONF__H__ -#define __USBD_CONF__H__ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - - - -/** @defgroup USB_CONF_Exported_Defines - * @{ - */ -#define USE_USB_OTG_HS - -#define USBD_CFG_MAX_NUM 1 -#define USB_MAX_STR_DESC_SIZ 64 -#define USBD_EP0_MAX_PACKET_SIZE 64 - -/** - * @} - */ - - -/** @defgroup USB_CONF_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_CONF_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CONF_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CONF_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif //__USBD_CONF__H__ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_core.h b/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_core.h deleted file mode 100644 index fb20acf63..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_core.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_core.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief Header file for usbd_core.c - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_CORE_H -#define __USBD_CORE_H - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd.h" -#include "usbd_def.h" -#include "usbd_conf.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_CORE - * @brief This file is the Header file for usbd_core.c file - * @{ - */ - - -/** @defgroup USBD_CORE_Exported_Defines - * @{ - */ - -typedef enum { - USBD_OK = 0, - USBD_BUSY, - USBD_FAIL, -}USBD_Status; -/** - * @} - */ - - -/** @defgroup USBD_CORE_Exported_TypesDefinitions - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_CORE_Exported_FunctionsPrototype - * @{ - */ -void USBD_Init(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID, - USBD_DEVICE *pDevice, - USBD_Class_cb_TypeDef *class_cb, - USBD_Usr_cb_TypeDef *usr_cb); - -USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev); - -USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx); - -USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx); - -/** - * @} - */ - -#endif /* __USBD_CORE_H */ - -/** - * @} - */ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - - diff --git a/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_def.h b/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_def.h deleted file mode 100644 index a8c86710d..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_def.h +++ /dev/null @@ -1,149 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_def.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief general defines for the usb device library - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USBD_DEF_H -#define __USBD_DEF_H -/* Includes ------------------------------------------------------------------*/ -#include "usbd_conf.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USB_DEF - * @brief general defines for the usb device library file - * @{ - */ - -/** @defgroup USB_DEF_Exported_Defines - * @{ - */ - -#ifndef NULL -#define NULL 0 -#endif - -#define USB_LEN_DEV_QUALIFIER_DESC 0x0A -#define USB_LEN_DEV_DESC 0x12 -#define USB_LEN_CFG_DESC 0x09 -#define USB_LEN_IF_DESC 0x09 -#define USB_LEN_EP_DESC 0x07 -#define USB_LEN_OTG_DESC 0x03 - -#define USBD_IDX_LANGID_STR 0x00 -#define USBD_IDX_MFC_STR 0x01 -#define USBD_IDX_PRODUCT_STR 0x02 -#define USBD_IDX_SERIAL_STR 0x03 -#define USBD_IDX_CONFIG_STR 0x04 -#define USBD_IDX_INTERFACE_STR 0x05 - -#define USB_REQ_TYPE_STANDARD 0x00 -#define USB_REQ_TYPE_CLASS 0x20 -#define USB_REQ_TYPE_VENDOR 0x40 -#define USB_REQ_TYPE_MASK 0x60 - -#define USB_REQ_RECIPIENT_DEVICE 0x00 -#define USB_REQ_RECIPIENT_INTERFACE 0x01 -#define USB_REQ_RECIPIENT_ENDPOINT 0x02 -#define USB_REQ_RECIPIENT_MASK 0x03 - -#define USB_REQ_GET_STATUS 0x00 -#define USB_REQ_CLEAR_FEATURE 0x01 -#define USB_REQ_SET_FEATURE 0x03 -#define USB_REQ_SET_ADDRESS 0x05 -#define USB_REQ_GET_DESCRIPTOR 0x06 -#define USB_REQ_SET_DESCRIPTOR 0x07 -#define USB_REQ_GET_CONFIGURATION 0x08 -#define USB_REQ_SET_CONFIGURATION 0x09 -#define USB_REQ_GET_INTERFACE 0x0A -#define USB_REQ_SET_INTERFACE 0x0B -#define USB_REQ_SYNCH_FRAME 0x0C - -#define USB_DESC_TYPE_DEVICE 1 -#define USB_DESC_TYPE_CONFIGURATION 2 -#define USB_DESC_TYPE_STRING 3 -#define USB_DESC_TYPE_INTERFACE 4 -#define USB_DESC_TYPE_ENDPOINT 5 -#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 -#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 - - -#define USB_CONFIG_REMOTE_WAKEUP 2 -#define USB_CONFIG_SELF_POWERED 1 - -#define USB_FEATURE_EP_HALT 0 -#define USB_FEATURE_REMOTE_WAKEUP 1 -#define USB_FEATURE_TEST_MODE 2 - -/** - * @} - */ - - -/** @defgroup USBD_DEF_Exported_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_DEF_Exported_Macros - * @{ - */ -#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \ - (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8)) - -#define LOBYTE(x) ((uint8_t)(x & 0x00FF)) -#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8)) -/** - * @} - */ - -/** @defgroup USBD_DEF_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_DEF_Exported_FunctionsPrototype - * @{ - */ - -/** - * @} - */ - -#endif /* __USBD_DEF_H */ - -/** - * @} - */ - -/** -* @} -*/ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_ioreq.h b/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_ioreq.h deleted file mode 100644 index ca755f2bb..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_ioreq.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_ioreq.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief header file for the usbd_ioreq.c file - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USBD_IOREQ_H_ -#define __USBD_IOREQ_H_ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" -#include "usbd_core.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_IOREQ - * @brief header file for the usbd_ioreq.c file - * @{ - */ - -/** @defgroup USBD_IOREQ_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Exported_Types - * @{ - */ - - -/** - * @} - */ - - - -/** @defgroup USBD_IOREQ_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_IOREQ_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_IOREQ_Exported_FunctionsPrototype - * @{ - */ - -USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t *buf, - uint16_t len); - -USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len); - -USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev); - -USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev); - -uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev , - uint8_t epnum); - -/** - * @} - */ - -#endif /* __USBD_IOREQ_H_ */ - -/** - * @} - */ - -/** -* @} -*/ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_req.h b/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_req.h deleted file mode 100644 index 9aa9e44a3..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_req.h +++ /dev/null @@ -1,102 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_req.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief header file for the usbd_req.c file - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ - -#ifndef __USB_REQUEST_H_ -#define __USB_REQUEST_H_ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_def.h" -#include "usbd_core.h" -#include "usbd_conf.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - -/** @defgroup USBD_REQ - * @brief header file for the usbd_ioreq.c file - * @{ - */ - -/** @defgroup USBD_REQ_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Exported_Types - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBD_REQ_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_REQ_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_REQ_Exported_FunctionsPrototype - * @{ - */ - -USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); -USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); -USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req); -void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len); -/** - * @} - */ - -#endif /* __USB_REQUEST_H_ */ - -/** - * @} - */ - -/** -* @} -*/ - - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_usr.h b/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_usr.h deleted file mode 100644 index 44e7b1dd2..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Core/inc/usbd_usr.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_usr.h - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief Header file for usbd_usr.c - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBD_USR_H__ -#define __USBD_USR_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" - - -/** @addtogroup USBD_USER - * @{ - */ - -/** @addtogroup USBD_MSC_DEMO_USER_CALLBACKS - * @{ - */ - -/** @defgroup USBD_USR - * @brief This file is the Header file for usbd_usr.c - * @{ - */ - - -/** @defgroup USBD_USR_Exported_Types - * @{ - */ - -extern USBD_Usr_cb_TypeDef USR_cb; -extern USBD_Usr_cb_TypeDef USR_FS_cb; -extern USBD_Usr_cb_TypeDef USR_HS_cb; - - - -/** - * @} - */ - - - -/** @defgroup USBD_USR_Exported_Defines - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBD_USR_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBD_USR_Exported_Variables - * @{ - */ - -void USBD_USR_Init(void); -void USBD_USR_DeviceReset (uint8_t speed); -void USBD_USR_DeviceConfigured (void); -void USBD_USR_DeviceSuspended(void); -void USBD_USR_DeviceResumed(void); - -void USBD_USR_DeviceConnected(void); -void USBD_USR_DeviceDisconnected(void); - -void USBD_USR_FS_Init(void); -void USBD_USR_FS_DeviceReset (uint8_t speed); -void USBD_USR_FS_DeviceConfigured (void); -void USBD_USR_FS_DeviceSuspended(void); -void USBD_USR_FS_DeviceResumed(void); - -void USBD_USR_FS_DeviceConnected(void); -void USBD_USR_FS_DeviceDisconnected(void); - -void USBD_USR_HS_Init(void); -void USBD_USR_HS_DeviceReset (uint8_t speed); -void USBD_USR_HS_DeviceConfigured (void); -void USBD_USR_HS_DeviceSuspended(void); -void USBD_USR_HS_DeviceResumed(void); - -void USBD_USR_HS_DeviceConnected(void); -void USBD_USR_HS_DeviceDisconnected(void); - -/** - * @} - */ - -/** @defgroup USBD_USR_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - -#endif /*__USBD_USR_H__*/ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - - - diff --git a/example/stm32f4/STM32_USB_Device_Library/Core/src/usbd_core.c b/example/stm32f4/STM32_USB_Device_Library/Core/src/usbd_core.c deleted file mode 100644 index 2a51d3aef..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Core/src/usbd_core.c +++ /dev/null @@ -1,476 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_core.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief This file provides all the USBD core functions. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_core.h" -#include "usbd_req.h" -#include "usbd_ioreq.h" -#include "usb_dcd_int.h" -#include "usb_bsp.h" - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY -* @{ -*/ - - -/** @defgroup USBD_CORE -* @brief usbd core module -* @{ -*/ - -/** @defgroup USBD_CORE_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBD_CORE_Private_Defines -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USBD_CORE_Private_Macros -* @{ -*/ -/** -* @} -*/ - - - - -/** @defgroup USBD_CORE_Private_FunctionPrototypes -* @{ -*/ -static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); -static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); -static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev); -#ifdef VBUS_SENSING_ENABLED -static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev); -#endif -static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev); -static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev); -/** -* @} -*/ - -/** @defgroup USBD_CORE_Private_Variables -* @{ -*/ - - - -USBD_DCD_INT_cb_TypeDef USBD_DCD_INT_cb = -{ - USBD_DataOutStage, - USBD_DataInStage, - USBD_SetupStage, - USBD_SOF, - USBD_Reset, - USBD_Suspend, - USBD_Resume, - USBD_IsoINIncomplete, - USBD_IsoOUTIncomplete, -#ifdef VBUS_SENSING_ENABLED -USBD_DevConnected, -USBD_DevDisconnected, -#endif -}; - -USBD_DCD_INT_cb_TypeDef *USBD_DCD_INT_fops = &USBD_DCD_INT_cb; -/** -* @} -*/ - -/** @defgroup USBD_CORE_Private_Functions -* @{ -*/ - -/** -* @brief USBD_Init -* Initailizes the device stack and load the class driver -* @param pdev: device instance -* @param core_address: USB OTG core ID -* @param class_cb: Class callback structure address -* @param usr_cb: User callback structure address -* @retval None -*/ -void USBD_Init(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID, - USBD_DEVICE *pDevice, - USBD_Class_cb_TypeDef *class_cb, - USBD_Usr_cb_TypeDef *usr_cb) -{ - /* Hardware Init */ - USB_OTG_BSP_Init(pdev); - - USBD_DeInit(pdev); - - /*Register class and user callbacks */ - pdev->dev.class_cb = class_cb; - pdev->dev.usr_cb = usr_cb; - pdev->dev.usr_device = pDevice; - - /* set USB OTG core params */ - DCD_Init(pdev , coreID); - - /* Upon Init call usr callback */ - pdev->dev.usr_cb->Init(); - - /* Enable Interrupts */ - USB_OTG_BSP_EnableInterrupt(pdev); -} - -/** -* @brief USBD_DeInit -* Re-Initialize th deviuce library -* @param pdev: device instance -* @retval status: status -*/ -USBD_Status USBD_DeInit(USB_OTG_CORE_HANDLE *pdev) -{ - /* Software Init */ - - return USBD_OK; -} - -/** -* @brief USBD_SetupStage -* Handle the setup stage -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_SetupStage(USB_OTG_CORE_HANDLE *pdev) -{ - USB_SETUP_REQ req; - - USBD_ParseSetupRequest(pdev , &req); - - switch (req.bmRequest & 0x1F) - { - case USB_REQ_RECIPIENT_DEVICE: - USBD_StdDevReq (pdev, &req); - break; - - case USB_REQ_RECIPIENT_INTERFACE: - USBD_StdItfReq(pdev, &req); - break; - - case USB_REQ_RECIPIENT_ENDPOINT: - USBD_StdEPReq(pdev, &req); - break; - - default: - DCD_EP_Stall(pdev , req.bmRequest & 0x80); - break; - } - return USBD_OK; -} - -/** -* @brief USBD_DataOutStage -* Handle data out stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -static uint8_t USBD_DataOutStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - USB_OTG_EP *ep; - - if(epnum == 0) - { - ep = &pdev->dev.out_ep[0]; - if ( pdev->dev.device_state == USB_OTG_EP0_DATA_OUT) - { - if(ep->rem_data_len > ep->maxpacket) - { - ep->rem_data_len -= ep->maxpacket; - - if(pdev->cfg.dma_enable == 1) - { - /* in slave mode this, is handled by the RxSTSQLvl ISR */ - ep->xfer_buff += ep->maxpacket; - } - USBD_CtlContinueRx (pdev, - ep->xfer_buff, - MIN(ep->rem_data_len ,ep->maxpacket)); - } - else - { - if((pdev->dev.class_cb->EP0_RxReady != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->EP0_RxReady(pdev); - } - USBD_CtlSendStatus(pdev); - } - } - } - else if((pdev->dev.class_cb->DataOut != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->DataOut(pdev, epnum); - } - return USBD_OK; -} - -/** -* @brief USBD_DataInStage -* Handle data in stage -* @param pdev: device instance -* @param epnum: endpoint index -* @retval status -*/ -static uint8_t USBD_DataInStage(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - USB_OTG_EP *ep; - - if(epnum == 0) - { - ep = &pdev->dev.in_ep[0]; - if ( pdev->dev.device_state == USB_OTG_EP0_DATA_IN) - { - if(ep->rem_data_len > ep->maxpacket) - { - ep->rem_data_len -= ep->maxpacket; - if(pdev->cfg.dma_enable == 1) - { - /* in slave mode this, is handled by the TxFifoEmpty ISR */ - ep->xfer_buff += ep->maxpacket; - } - USBD_CtlContinueSendData (pdev, - ep->xfer_buff, - ep->rem_data_len); - } - else - { /* last packet is MPS multiple, so send ZLP packet */ - if((ep->total_data_len % ep->maxpacket == 0) && - (ep->total_data_len >= ep->maxpacket) && - (ep->total_data_len < ep->ctl_data_len )) - { - - USBD_CtlContinueSendData(pdev , NULL, 0); - ep->ctl_data_len = 0; - } - else - { - if((pdev->dev.class_cb->EP0_TxSent != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->EP0_TxSent(pdev); - } - USBD_CtlReceiveStatus(pdev); - } - } - } - } - else if((pdev->dev.class_cb->DataIn != NULL)&& - (pdev->dev.device_status == USB_OTG_CONFIGURED)) - { - pdev->dev.class_cb->DataIn(pdev, epnum); - } - return USBD_OK; -} - -/** -* @brief USBD_Reset -* Handle Reset event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_Reset(USB_OTG_CORE_HANDLE *pdev) -{ - /* Open EP0 OUT */ - DCD_EP_Open(pdev, - 0x00, - USB_OTG_MAX_EP0_SIZE, - EP_TYPE_CTRL); - - /* Open EP0 IN */ - DCD_EP_Open(pdev, - 0x80, - USB_OTG_MAX_EP0_SIZE, - EP_TYPE_CTRL); - - /* Upon Reset call usr call back */ - pdev->dev.device_status = USB_OTG_DEFAULT; - pdev->dev.usr_cb->DeviceReset(pdev->cfg.speed); - - return USBD_OK; -} - -/** -* @brief USBD_Resume -* Handle Resume event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_Resume(USB_OTG_CORE_HANDLE *pdev) -{ - /* Upon Resume call usr call back */ - pdev->dev.usr_cb->DeviceResumed(); - pdev->dev.device_status = USB_OTG_CONFIGURED; - return USBD_OK; -} - - -/** -* @brief USBD_Suspend -* Handle Suspend event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_Suspend(USB_OTG_CORE_HANDLE *pdev) -{ - - pdev->dev.device_status = USB_OTG_SUSPENDED; - /* Upon Resume call usr call back */ - pdev->dev.usr_cb->DeviceSuspended(); - return USBD_OK; -} - - -/** -* @brief USBD_SOF -* Handle SOF event -* @param pdev: device instance -* @retval status -*/ - -static uint8_t USBD_SOF(USB_OTG_CORE_HANDLE *pdev) -{ - if(pdev->dev.class_cb->SOF) - { - pdev->dev.class_cb->SOF(pdev); - } - return USBD_OK; -} -/** -* @brief USBD_SetCfg -* Configure device and start the interface -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status -*/ - -USBD_Status USBD_SetCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx) -{ - pdev->dev.class_cb->Init(pdev, cfgidx); - - /* Upon set config call usr call back */ - pdev->dev.usr_cb->DeviceConfigured(); - return USBD_OK; -} - -/** -* @brief USBD_ClrCfg -* Clear current configuration -* @param pdev: device instance -* @param cfgidx: configuration index -* @retval status: USBD_Status -*/ -USBD_Status USBD_ClrCfg(USB_OTG_CORE_HANDLE *pdev, uint8_t cfgidx) -{ - pdev->dev.class_cb->DeInit(pdev, cfgidx); - return USBD_OK; -} - -/** -* @brief USBD_IsoINIncomplete -* Handle iso in incomplete event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_IsoINIncomplete(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.class_cb->IsoINIncomplete(pdev); - return USBD_OK; -} - -/** -* @brief USBD_IsoOUTIncomplete -* Handle iso out incomplete event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_IsoOUTIncomplete(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.class_cb->IsoOUTIncomplete(pdev); - return USBD_OK; -} - -#ifdef VBUS_SENSING_ENABLED -/** -* @brief USBD_DevConnected -* Handle device connection event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_DevConnected(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.usr_cb->DeviceConnected(); - return USBD_OK; -} - -/** -* @brief USBD_DevDisconnected -* Handle device disconnection event -* @param pdev: device instance -* @retval status -*/ -static uint8_t USBD_DevDisconnected(USB_OTG_CORE_HANDLE *pdev) -{ - pdev->dev.usr_cb->DeviceDisconnected(); - pdev->dev.class_cb->DeInit(pdev, 0); - return USBD_OK; -} -#endif -/** -* @} -*/ - - -/** -* @} -*/ - - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c b/example/stm32f4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c deleted file mode 100644 index 6964766bd..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c +++ /dev/null @@ -1,237 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_ioreq.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief This file provides the IO requests APIs for control endpoints. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_ioreq.h" -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_IOREQ - * @brief control I/O requests module - * @{ - */ - -/** @defgroup USBD_IOREQ_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Variables - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_IOREQ_Private_Functions - * @{ - */ - -/** -* @brief USBD_CtlSendData -* send data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be sent -* @retval status -*/ -USBD_Status USBD_CtlSendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len) -{ - USBD_Status ret = USBD_OK; - - pdev->dev.in_ep[0].total_data_len = len; - pdev->dev.in_ep[0].rem_data_len = len; - pdev->dev.device_state = USB_OTG_EP0_DATA_IN; - - DCD_EP_Tx (pdev, 0, pbuf, len); - - return ret; -} - -/** -* @brief USBD_CtlContinueSendData -* continue sending data on the ctl pipe -* @param pdev: device instance -* @param buff: pointer to data buffer -* @param len: length of data to be sent -* @retval status -*/ -USBD_Status USBD_CtlContinueSendData (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len) -{ - USBD_Status ret = USBD_OK; - - DCD_EP_Tx (pdev, 0, pbuf, len); - - - return ret; -} - -/** -* @brief USBD_CtlPrepareRx -* receive data on the ctl pipe -* @param pdev: USB OTG device instance -* @param buff: pointer to data buffer -* @param len: length of data to be received -* @retval status -*/ -USBD_Status USBD_CtlPrepareRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len) -{ - USBD_Status ret = USBD_OK; - - pdev->dev.out_ep[0].total_data_len = len; - pdev->dev.out_ep[0].rem_data_len = len; - pdev->dev.device_state = USB_OTG_EP0_DATA_OUT; - - DCD_EP_PrepareRx (pdev, - 0, - pbuf, - len); - - - return ret; -} - -/** -* @brief USBD_CtlContinueRx -* continue receive data on the ctl pipe -* @param pdev: USB OTG device instance -* @param buff: pointer to data buffer -* @param len: length of data to be received -* @retval status -*/ -USBD_Status USBD_CtlContinueRx (USB_OTG_CORE_HANDLE *pdev, - uint8_t *pbuf, - uint16_t len) -{ - USBD_Status ret = USBD_OK; - - DCD_EP_PrepareRx (pdev, - 0, - pbuf, - len); - return ret; -} -/** -* @brief USBD_CtlSendStatus -* send zero lzngth packet on the ctl pipe -* @param pdev: USB OTG device instance -* @retval status -*/ -USBD_Status USBD_CtlSendStatus (USB_OTG_CORE_HANDLE *pdev) -{ - USBD_Status ret = USBD_OK; - pdev->dev.device_state = USB_OTG_EP0_STATUS_IN; - DCD_EP_Tx (pdev, - 0, - NULL, - 0); - - USB_OTG_EP0_OutStart(pdev); - - return ret; -} - -/** -* @brief USBD_CtlReceiveStatus -* receive zero lzngth packet on the ctl pipe -* @param pdev: USB OTG device instance -* @retval status -*/ -USBD_Status USBD_CtlReceiveStatus (USB_OTG_CORE_HANDLE *pdev) -{ - USBD_Status ret = USBD_OK; - pdev->dev.device_state = USB_OTG_EP0_STATUS_OUT; - DCD_EP_PrepareRx ( pdev, - 0, - NULL, - 0); - - USB_OTG_EP0_OutStart(pdev); - - return ret; -} - - -/** -* @brief USBD_GetRxCount -* returns the received data length -* @param pdev: USB OTG device instance -* epnum: endpoint index -* @retval Rx Data blength -*/ -uint16_t USBD_GetRxCount (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - return pdev->dev.out_ep[epnum].xfer_count; -} - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_Device_Library/Core/src/usbd_req.c b/example/stm32f4/STM32_USB_Device_Library/Core/src/usbd_req.c deleted file mode 100644 index f08d26c6c..000000000 --- a/example/stm32f4/STM32_USB_Device_Library/Core/src/usbd_req.c +++ /dev/null @@ -1,868 +0,0 @@ -/** - ****************************************************************************** - * @file usbd_req.c - * @author MCD Application Team - * @version V1.0.0 - * @date 22-July-2011 - * @brief This file provides the standard USB requests following chapter 9. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbd_req.h" -#include "usbd_ioreq.h" -#include "usbd_desc.h" - - -/** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY - * @{ - */ - - -/** @defgroup USBD_REQ - * @brief USB standard requests module - * @{ - */ - -/** @defgroup USBD_REQ_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Defines - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Variables - * @{ - */ - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint32_t USBD_ep_status __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint32_t USBD_default_cfg __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint32_t USBD_cfg_status __ALIGN_END = 0; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ] __ALIGN_END ; -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_FunctionPrototypes - * @{ - */ -static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req); - -static uint8_t USBD_GetLen(uint8_t *buf); -/** - * @} - */ - - -/** @defgroup USBD_REQ_Private_Functions - * @{ - */ - - -/** -* @brief USBD_StdDevReq -* Handle standard usb device requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -USBD_Status USBD_StdDevReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) -{ - USBD_Status ret = USBD_OK; - - switch (req->bRequest) - { - case USB_REQ_GET_DESCRIPTOR: - - USBD_GetDescriptor (pdev, req) ; - break; - - case USB_REQ_SET_ADDRESS: - USBD_SetAddress(pdev, req); - break; - - case USB_REQ_SET_CONFIGURATION: - USBD_SetConfig (pdev , req); - break; - - case USB_REQ_GET_CONFIGURATION: - USBD_GetConfig (pdev , req); - break; - - case USB_REQ_GET_STATUS: - USBD_GetStatus (pdev , req); - break; - - - case USB_REQ_SET_FEATURE: - USBD_SetFeature (pdev , req); - break; - - case USB_REQ_CLEAR_FEATURE: - USBD_ClrFeature (pdev , req); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - - return ret; -} - -/** -* @brief USBD_StdItfReq -* Handle standard usb interface requests -* @param pdev: USB OTG device instance -* @param req: usb request -* @retval status -*/ -USBD_Status USBD_StdItfReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) -{ - USBD_Status ret = USBD_OK; - - switch (pdev->dev.device_status) - { - case USB_OTG_CONFIGURED: - - if (LOBYTE(req->wIndex) <= USBD_ITF_MAX_NUM) - { - pdev->dev.class_cb->Setup (pdev, req); - - if((req->wLength == 0)&& (ret == USBD_OK)) - { - USBD_CtlSendStatus(pdev); - } - } - else - { - USBD_CtlError(pdev , req); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - return ret; -} - -/** -* @brief USBD_StdEPReq -* Handle standard usb endpoint requests -* @param pdev: USB OTG device instance -* @param req: usb request -* @retval status -*/ -USBD_Status USBD_StdEPReq (USB_OTG_CORE_HANDLE *pdev, USB_SETUP_REQ *req) -{ - - uint8_t ep_addr; - USBD_Status ret = USBD_OK; - - ep_addr = LOBYTE(req->wIndex); - - switch (req->bRequest) - { - - case USB_REQ_SET_FEATURE : - - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - } - break; - - case USB_OTG_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - - } - } - pdev->dev.class_cb->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - case USB_REQ_CLEAR_FEATURE : - - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - } - break; - - case USB_OTG_CONFIGURED: - if (req->wValue == USB_FEATURE_EP_HALT) - { - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_ClrStall(pdev , ep_addr); - pdev->dev.class_cb->Setup (pdev, req); - } - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - case USB_REQ_GET_STATUS: - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if ((ep_addr != 0x00) && (ep_addr != 0x80)) - { - DCD_EP_Stall(pdev , ep_addr); - } - break; - - case USB_OTG_CONFIGURED: - - - if ((ep_addr & 0x80)== 0x80) - { - if(pdev->dev.in_ep[ep_addr & 0x7F].is_stall) - { - USBD_ep_status = 0x0001; - } - else - { - USBD_ep_status = 0x0000; - } - } - else if ((ep_addr & 0x80)== 0x00) - { - if(pdev->dev.out_ep[ep_addr].is_stall) - { - USBD_ep_status = 0x0001; - } - - else - { - USBD_ep_status = 0x0000; - } - } - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_ep_status, - 2); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - break; - - default: - break; - } - return ret; -} -/** -* @brief USBD_GetDescriptor -* Handle Get Descriptor requests -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - uint16_t len; - uint8_t *pbuf; - - switch (req->wValue >> 8) - { - case USB_DESC_TYPE_DEVICE: - pbuf = pdev->dev.usr_device->GetDeviceDescriptor(pdev->cfg.speed, &len); - if ((req->wLength == 64) ||( pdev->dev.device_status == USB_OTG_DEFAULT)) - { - len = 8; - } - break; - - case USB_DESC_TYPE_CONFIGURATION: - pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len); -#ifdef USB_OTG_HS_CORE - if((pdev->cfg.speed == USB_OTG_SPEED_FULL )&& - (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY)) - { - pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len); - } -#endif - pbuf[1] = USB_DESC_TYPE_CONFIGURATION; - pdev->dev.pConfig_descriptor = pbuf; - break; - - case USB_DESC_TYPE_STRING: - switch ((uint8_t)(req->wValue)) - { - case USBD_IDX_LANGID_STR: - pbuf = pdev->dev.usr_device->GetLangIDStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_MFC_STR: - pbuf = pdev->dev.usr_device->GetManufacturerStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_PRODUCT_STR: - pbuf = pdev->dev.usr_device->GetProductStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_SERIAL_STR: - pbuf = pdev->dev.usr_device->GetSerialStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_CONFIG_STR: - pbuf = pdev->dev.usr_device->GetConfigurationStrDescriptor(pdev->cfg.speed, &len); - break; - - case USBD_IDX_INTERFACE_STR: - pbuf = pdev->dev.usr_device->GetInterfaceStrDescriptor(pdev->cfg.speed, &len); - break; - - default: -#ifdef USB_SUPPORT_USER_STRING_DESC - pbuf = pdev->dev.class_cb->GetUsrStrDescriptor(pdev->cfg.speed, (req->wValue) , &len); - break; -#else - USBD_CtlError(pdev , req); - return; -#endif /* USBD_CtlError(pdev , req); */ - } - break; - case USB_DESC_TYPE_DEVICE_QUALIFIER: -#ifdef USB_OTG_HS_CORE - if(pdev->cfg.speed == USB_OTG_SPEED_HIGH ) - { - - pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->cfg.speed, &len); - - USBD_DeviceQualifierDesc[4]= pbuf[14]; - USBD_DeviceQualifierDesc[5]= pbuf[15]; - USBD_DeviceQualifierDesc[6]= pbuf[16]; - - pbuf = USBD_DeviceQualifierDesc; - len = USB_LEN_DEV_QUALIFIER_DESC; - break; - } - else - { - USBD_CtlError(pdev , req); - return; - } -#else - USBD_CtlError(pdev , req); - return; -#endif - - case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION: -#ifdef USB_OTG_HS_CORE - - if(pdev->cfg.speed == USB_OTG_SPEED_HIGH ) - { - pbuf = (uint8_t *)pdev->dev.class_cb->GetOtherConfigDescriptor(pdev->cfg.speed, &len); - pbuf[1] = USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION; - break; - } - else - { - USBD_CtlError(pdev , req); - return; - } -#else - USBD_CtlError(pdev , req); - return; -#endif - - - default: - USBD_CtlError(pdev , req); - return; - } - - if((len != 0)&& (req->wLength != 0)) - { - - len = MIN(len , req->wLength); - - USBD_CtlSendData (pdev, - pbuf, - len); - } - -} - -/** -* @brief USBD_SetAddress -* Set device address -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetAddress(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - uint8_t dev_addr; - - if ((req->wIndex == 0) && (req->wLength == 0)) - { - dev_addr = (uint8_t)(req->wValue) & 0x7F; - - if (pdev->dev.device_status == USB_OTG_CONFIGURED) - { - USBD_CtlError(pdev , req); - } - else - { - pdev->dev.device_address = dev_addr; - DCD_EP_SetAddress(pdev, dev_addr); - USBD_CtlSendStatus(pdev); - - if (dev_addr != 0) - { - pdev->dev.device_status = USB_OTG_ADDRESSED; - } - else - { - pdev->dev.device_status = USB_OTG_DEFAULT; - } - } - } - else - { - USBD_CtlError(pdev , req); - } -} - -/** -* @brief USBD_SetConfig -* Handle Set device configuration request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - static uint8_t cfgidx; - - cfgidx = (uint8_t)(req->wValue); - - if (cfgidx > USBD_CFG_MAX_NUM ) - { - USBD_CtlError(pdev , req); - } - else - { - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - if (cfgidx) - { - pdev->dev.device_config = cfgidx; - pdev->dev.device_status = USB_OTG_CONFIGURED; - USBD_SetCfg(pdev , cfgidx); - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; - - case USB_OTG_CONFIGURED: - if (cfgidx == 0) - { - pdev->dev.device_status = USB_OTG_ADDRESSED; - pdev->dev.device_config = cfgidx; - USBD_ClrCfg(pdev , cfgidx); - USBD_CtlSendStatus(pdev); - - } - else if (cfgidx != pdev->dev.device_config) - { - /* Clear old configuration */ - USBD_ClrCfg(pdev , pdev->dev.device_config); - - /* set new configuration */ - pdev->dev.device_config = cfgidx; - USBD_SetCfg(pdev , cfgidx); - USBD_CtlSendStatus(pdev); - } - else - { - USBD_CtlSendStatus(pdev); - } - break; - - default: - USBD_CtlError(pdev , req); - break; - } - } -} - -/** -* @brief USBD_GetConfig -* Handle Get device configuration request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetConfig(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - if (req->wLength != 1) - { - USBD_CtlError(pdev , req); - } - else - { - switch (pdev->dev.device_status ) - { - case USB_OTG_ADDRESSED: - - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_default_cfg, - 1); - break; - - case USB_OTG_CONFIGURED: - - USBD_CtlSendData (pdev, - &pdev->dev.device_config, - 1); - break; - - default: - USBD_CtlError(pdev , req); - break; - } - } -} - -/** -* @brief USBD_GetStatus -* Handle Get Status request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_GetStatus(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - case USB_OTG_CONFIGURED: - - if (pdev->dev.DevRemoteWakeup) - { - USBD_cfg_status = USB_CONFIG_SELF_POWERED | USB_CONFIG_REMOTE_WAKEUP; - } - else - { - USBD_cfg_status = USB_CONFIG_SELF_POWERED; - } - - USBD_CtlSendData (pdev, - (uint8_t *)&USBD_cfg_status, - 1); - break; - - default : - USBD_CtlError(pdev , req); - break; - } -} - - -/** -* @brief USBD_SetFeature -* Handle Set device feature request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_SetFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - - USB_OTG_DCTL_TypeDef dctl; - uint8_t test_mode = 0; - - if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) - { - pdev->dev.DevRemoteWakeup = 1; - pdev->dev.class_cb->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - } - - else if ((req->wValue == USB_FEATURE_TEST_MODE) && - ((req->wIndex & 0xFF) == 0)) - { - dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); - - test_mode = req->wIndex >> 8; - switch (test_mode) - { - case 1: // TEST_J - dctl.b.tstctl = 1; - break; - - case 2: // TEST_K - dctl.b.tstctl = 2; - break; - - case 3: // TEST_SE0_NAK - dctl.b.tstctl = 3; - break; - - case 4: // TEST_PACKET - dctl.b.tstctl = 4; - break; - - case 5: // TEST_FORCE_ENABLE - dctl.b.tstctl = 5; - break; - } - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32); - USBD_CtlSendStatus(pdev); - } - -} - - -/** -* @brief USBD_ClrFeature -* Handle clear device feature request -* @param pdev: device instance -* @param req: usb request -* @retval status -*/ -static void USBD_ClrFeature(USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - switch (pdev->dev.device_status) - { - case USB_OTG_ADDRESSED: - case USB_OTG_CONFIGURED: - if (req->wValue == USB_FEATURE_REMOTE_WAKEUP) - { - pdev->dev.DevRemoteWakeup = 0; - pdev->dev.class_cb->Setup (pdev, req); - USBD_CtlSendStatus(pdev); - } - break; - - default : - USBD_CtlError(pdev , req); - break; - } -} - -/** -* @brief USBD_ParseSetupRequest -* Copy buffer into setup structure -* @param pdev: device instance -* @param req: usb request -* @retval None -*/ - -void USBD_ParseSetupRequest( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - req->bmRequest = *(uint8_t *) (pdev->dev.setup_packet); - req->bRequest = *(uint8_t *) (pdev->dev.setup_packet + 1); - req->wValue = SWAPBYTE (pdev->dev.setup_packet + 2); - req->wIndex = SWAPBYTE (pdev->dev.setup_packet + 4); - req->wLength = SWAPBYTE (pdev->dev.setup_packet + 6); - - pdev->dev.in_ep[0].ctl_data_len = req->wLength ; - pdev->dev.device_state = USB_OTG_EP0_SETUP; -} - -/** -* @brief USBD_CtlError -* Handle USB low level Error -* @param pdev: device instance -* @param req: usb request -* @retval None -*/ - -void USBD_CtlError( USB_OTG_CORE_HANDLE *pdev, - USB_SETUP_REQ *req) -{ - if((req->bmRequest & 0x80) == 0x80) - { - DCD_EP_Stall(pdev , 0x80); - } - else - { - if(req->wLength == 0) - { - DCD_EP_Stall(pdev , 0x80); - } - else - { - DCD_EP_Stall(pdev , 0); - } - } - USB_OTG_EP0_OutStart(pdev); -} - - -/** - * @brief USBD_GetString - * Convert Ascii string into unicode one - * @param desc : descriptor buffer - * @param unicode : Formatted string buffer (unicode) - * @param len : descriptor length - * @retval None - */ -void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) -{ - uint8_t idx = 0; - - if (desc != NULL) - { - *len = USBD_GetLen(desc) * 2 + 2; - unicode[idx++] = *len; - unicode[idx++] = USB_DESC_TYPE_STRING; - - while (*desc != NULL) - { - unicode[idx++] = *desc++; - unicode[idx++] = 0x00; - } - } -} - -/** - * @brief USBD_GetLen - * return the string length - * @param buf : pointer to the ascii string buffer - * @retval string length - */ -static uint8_t USBD_GetLen(uint8_t *buf) -{ - uint8_t len = 0; - - while (*buf != NULL) - { - len++; - buf++; - } - - return len; -} -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_core.h b/example/stm32f4/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_core.h deleted file mode 100644 index e6d0b79a0..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_core.h +++ /dev/null @@ -1,195 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hid_core.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief This file contains all the prototypes for the usbh_hid_core.c - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive ----------------------------------------------*/ -#ifndef __USBH_HID_CORE_H -#define __USBH_HID_CORE_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_core.h" -#include "usbh_stdreq.h" -#include "usb_bsp.h" -#include "usbh_ioreq.h" -#include "usbh_hcs.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_CLASS - * @{ - */ - -/** @addtogroup USBH_HID_CLASS - * @{ - */ - -/** @defgroup USBH_HID_CORE - * @brief This file is the Header file for USBH_HID_CORE.c - * @{ - */ - - -/** @defgroup USBH_HID_CORE_Exported_Types - * @{ - */ - - -/* States for HID State Machine */ -typedef enum -{ - HID_IDLE= 0, - HID_SEND_DATA, - HID_BUSY, - HID_GET_DATA, - HID_POLL, - HID_ERROR, -} -HID_State; - -typedef enum -{ - HID_REQ_IDLE = 0, - HID_REQ_GET_REPORT_DESC, - HID_REQ_GET_HID_DESC, - HID_REQ_SET_IDLE, - HID_REQ_SET_PROTOCOL, - HID_REQ_SET_REPORT, - -} -HID_CtlState; - -typedef struct HID_cb -{ - void (*Init) (void); - void (*Decode) (uint8_t *data); - -} HID_cb_TypeDef; - -typedef struct _HID_Report -{ - uint8_t ReportID; - uint8_t ReportType; - uint16_t UsagePage; - uint32_t Usage[2]; - uint32_t NbrUsage; - uint32_t UsageMin; - uint32_t UsageMax; - int32_t LogMin; - int32_t LogMax; - int32_t PhyMin; - int32_t PhyMax; - int32_t UnitExp; - uint32_t Unit; - uint32_t ReportSize; - uint32_t ReportCnt; - uint32_t Flag; - uint32_t PhyUsage; - uint32_t AppUsage; - uint32_t LogUsage; -} -HID_Report_TypeDef; - -/* Structure for HID process */ -typedef struct _HID_Process -{ - uint8_t buff[64]; - uint8_t hc_num_in; - uint8_t hc_num_out; - HID_State state; - uint8_t HIDIntOutEp; - uint8_t HIDIntInEp; - HID_CtlState ctl_state; - uint16_t length; - uint8_t ep_addr; - uint16_t poll; - __IO uint16_t timer; - HID_cb_TypeDef *cb; -} -HID_Machine_TypeDef; - -/** - * @} - */ - -/** @defgroup USBH_HID_CORE_Exported_Defines - * @{ - */ - -#define USB_HID_REQ_GET_REPORT 0x01 -#define USB_HID_GET_IDLE 0x02 -#define USB_HID_GET_PROTOCOL 0x03 -#define USB_HID_SET_REPORT 0x09 -#define USB_HID_SET_IDLE 0x0A -#define USB_HID_SET_PROTOCOL 0x0B -/** - * @} - */ - -/** @defgroup USBH_HID_CORE_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HID_CORE_Exported_Variables - * @{ - */ -extern USBH_Class_cb_TypeDef HID_cb; -/** - * @} - */ - -/** @defgroup USBH_HID_CORE_Exported_FunctionsPrototype - * @{ - */ - -USBH_Status USBH_Set_Report (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t reportType, - uint8_t reportId, - uint8_t reportLen, - uint8_t* reportBuff); -/** - * @} - */ - - -#endif /* __USBH_HID_CORE_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_keybd.h b/example/stm32f4/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_keybd.h deleted file mode 100644 index 08f6b9f58..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_keybd.h +++ /dev/null @@ -1,122 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hid_keybd.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief This file contains all the prototypes for the usbh_hid_keybd.c - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive -----------------------------------------------*/ -#ifndef __USBH_HID_KEYBD_H -#define __USBH_HID_KEYBD_H - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" -#include "usbh_hid_core.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_CLASS - * @{ - */ - -/** @addtogroup USBH_HID_CLASS - * @{ - */ - -/** @defgroup USBH_HID_KEYBD - * @brief This file is the Header file for USBH_HID_KEYBD.c - * @{ - */ - - -/** @defgroup USBH_HID_KEYBD_Exported_Types - * @{ - */ - - -/** - * @} - */ - -/** @defgroup USBH_HID_KEYBD_Exported_Defines - * @{ - */ -//#define QWERTY_KEYBOARD -#define AZERTY_KEYBOARD - -#define KBD_LEFT_CTRL 0x01 -#define KBD_LEFT_SHIFT 0x02 -#define KBD_LEFT_ALT 0x04 -#define KBD_LEFT_GUI 0x08 -#define KBD_RIGHT_CTRL 0x10 -#define KBD_RIGHT_SHIFT 0x20 -#define KBD_RIGHT_ALT 0x40 -#define KBD_RIGHT_GUI 0x80 - -#define KBR_MAX_NBR_PRESSED 6 - -/** - * @} - */ - -/** @defgroup USBH_HID_KEYBD_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HID_KEYBD_Exported_Variables - * @{ - */ - -extern HID_cb_TypeDef HID_KEYBRD_cb; -/** - * @} - */ - -/** @defgroup USBH_HID_KEYBD_Exported_FunctionsPrototype - * @{ - */ -void USR_KEYBRD_Init (void); -void USR_KEYBRD_ProcessData (uint8_t pbuf); -/** - * @} - */ - -#endif /* __USBH_HID_KEYBD_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_mouse.h b/example/stm32f4/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_mouse.h deleted file mode 100644 index eb2c2aeb0..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Class/HID/inc/usbh_hid_mouse.h +++ /dev/null @@ -1,114 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hid_mouse.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief This file contains all the prototypes for the usbh_hid_mouse.c - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - -/* Define to prevent recursive ----------------------------------------------*/ -#ifndef __USBH_HID_MOUSE_H -#define __USBH_HID_MOUSE_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_hid_core.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_CLASS - * @{ - */ - -/** @addtogroup USBH_HID_CLASS - * @{ - */ - -/** @defgroup USBH_HID_MOUSE - * @brief This file is the Header file for USBH_HID_MOUSE.c - * @{ - */ - - -/** @defgroup USBH_HID_MOUSE_Exported_Types - * @{ - */ -typedef struct _HID_MOUSE_Data -{ - uint8_t x; - uint8_t y; - uint8_t z; /* Not Supported */ - uint8_t button; -} -HID_MOUSE_Data_TypeDef; - -/** - * @} - */ - -/** @defgroup USBH_HID_MOUSE_Exported_Defines - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HID_MOUSE_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HID_MOUSE_Exported_Variables - * @{ - */ - -extern HID_cb_TypeDef HID_MOUSE_cb; -extern HID_MOUSE_Data_TypeDef HID_MOUSE_Data; -/** - * @} - */ - -/** @defgroup USBH_HID_MOUSE_Exported_FunctionsPrototype - * @{ - */ -void USR_MOUSE_Init (void); -void USR_MOUSE_ProcessData (HID_MOUSE_Data_TypeDef *data); -/** - * @} - */ - -#endif /* __USBH_HID_MOUSE_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_HOST_Library/Class/HID/src/usbh_hid_core.c b/example/stm32f4/STM32_USB_HOST_Library/Class/HID/src/usbh_hid_core.c deleted file mode 100644 index 53cb1969d..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Class/HID/src/usbh_hid_core.c +++ /dev/null @@ -1,640 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hid_core.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief This file is the HID Layer Handlers for USB Host HID class. - * - * @verbatim - * - * =================================================================== - * HID Class Description - * =================================================================== - * This module manages the MSC class V1.11 following the "Device Class Definition - * for Human Interface Devices (HID) Version 1.11 Jun 27, 2001". - * This driver implements the following aspects of the specification: - * - The Boot Interface Subclass - * - The Mouse and Keyboard protocols - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_hid_core.h" -#include "usbh_hid_mouse.h" -#include "usbh_hid_keybd.h" - -/** @addtogroup USBH_LIB -* @{ -*/ - -/** @addtogroup USBH_CLASS -* @{ -*/ - -/** @addtogroup USBH_HID_CLASS -* @{ -*/ - -/** @defgroup USBH_HID_CORE -* @brief This file includes HID Layer Handlers for USB Host HID class. -* @{ -*/ - -/** @defgroup USBH_HID_CORE_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_HID_CORE_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_HID_CORE_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_HID_CORE_Private_Variables -* @{ -*/ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN HID_Machine_TypeDef HID_Machine __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN HID_Report_TypeDef HID_Report __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN USB_Setup_TypeDef HID_Setup __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN USBH_HIDDesc_TypeDef HID_Desc __ALIGN_END ; - -__IO uint8_t flag = 0; -/** -* @} -*/ - - -/** @defgroup USBH_HID_CORE_Private_FunctionPrototypes -* @{ -*/ - -static USBH_Status USBH_HID_InterfaceInit (USB_OTG_CORE_HANDLE *pdev , - void *phost); - -static void USBH_ParseHIDDesc (USBH_HIDDesc_TypeDef *desc, uint8_t *buf); - -static void USBH_HID_InterfaceDeInit (USB_OTG_CORE_HANDLE *pdev , - void *phost); - -static USBH_Status USBH_HID_Handle(USB_OTG_CORE_HANDLE *pdev , - void *phost); - -static USBH_Status USBH_HID_ClassRequest(USB_OTG_CORE_HANDLE *pdev , - void *phost); - -static USBH_Status USBH_Get_HID_ReportDescriptor (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint16_t length); - -static USBH_Status USBH_Get_HID_Descriptor (USB_OTG_CORE_HANDLE *pdev,\ - USBH_HOST *phost, - uint16_t length); - -static USBH_Status USBH_Set_Idle (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t duration, - uint8_t reportId); - -static USBH_Status USBH_Set_Protocol (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t protocol); - - -USBH_Class_cb_TypeDef HID_cb = -{ - USBH_HID_InterfaceInit, - USBH_HID_InterfaceDeInit, - USBH_HID_ClassRequest, - USBH_HID_Handle -}; -/** -* @} -*/ - - -/** @defgroup USBH_HID_CORE_Private_Functions -* @{ -*/ - -/** -* @brief USBH_HID_InterfaceInit -* The function init the HID class. -* @param pdev: Selected device -* @param hdev: Selected device property -* @retval USBH_Status :Response for USB HID driver intialization -*/ -static USBH_Status USBH_HID_InterfaceInit ( USB_OTG_CORE_HANDLE *pdev, - void *phost) -{ - uint8_t maxEP; - USBH_HOST *pphost = phost; - - uint8_t num =0; - USBH_Status status = USBH_BUSY ; - HID_Machine.state = HID_ERROR; - - - if(pphost->device_prop.Itf_Desc[0].bInterfaceSubClass == HID_BOOT_CODE) - { - /*Decode Bootclass Protocl: Mouse or Keyboard*/ - if(pphost->device_prop.Itf_Desc[0].bInterfaceProtocol == HID_KEYBRD_BOOT_CODE) - { - HID_Machine.cb = &HID_KEYBRD_cb; - } - else if(pphost->device_prop.Itf_Desc[0].bInterfaceProtocol == HID_MOUSE_BOOT_CODE) - { - HID_Machine.cb = &HID_MOUSE_cb; - } - - HID_Machine.state = HID_IDLE; - HID_Machine.ctl_state = HID_REQ_IDLE; - HID_Machine.ep_addr = pphost->device_prop.Ep_Desc[0][0].bEndpointAddress; - HID_Machine.length = pphost->device_prop.Ep_Desc[0][0].wMaxPacketSize; - HID_Machine.poll = pphost->device_prop.Ep_Desc[0][0].bInterval ; - - /* Check fo available number of endpoints */ - /* Find the number of EPs in the Interface Descriptor */ - /* Choose the lower number in order not to overrun the buffer allocated */ - maxEP = ( (pphost->device_prop.Itf_Desc[0].bNumEndpoints <= USBH_MAX_NUM_ENDPOINTS) ? - pphost->device_prop.Itf_Desc[0].bNumEndpoints : - USBH_MAX_NUM_ENDPOINTS); - - - /* Decode endpoint IN and OUT address from interface descriptor */ - for (num=0; num < maxEP; num++) - { - if(pphost->device_prop.Ep_Desc[0][num].bEndpointAddress & 0x80) - { - HID_Machine.HIDIntInEp = (pphost->device_prop.Ep_Desc[0][num].bEndpointAddress); - HID_Machine.hc_num_in =\ - USBH_Alloc_Channel(pdev, - pphost->device_prop.Ep_Desc[0][num].bEndpointAddress); - - /* Open channel for IN endpoint */ - USBH_Open_Channel (pdev, - HID_Machine.hc_num_in, - pphost->device_prop.address, - pphost->device_prop.speed, - EP_TYPE_INTR, - HID_Machine.length); - } - else - { - HID_Machine.HIDIntOutEp = (pphost->device_prop.Ep_Desc[0][num].bEndpointAddress); - HID_Machine.hc_num_out =\ - USBH_Alloc_Channel(pdev, - pphost->device_prop.Ep_Desc[0][num].bEndpointAddress); - - /* Open channel for OUT endpoint */ - USBH_Open_Channel (pdev, - HID_Machine.hc_num_out, - pphost->device_prop.address, - pphost->device_prop.speed, - EP_TYPE_INTR, - HID_Machine.length); - } - - } - - flag =0; - status = USBH_OK; - } - else - { - pphost->usr_cb->USBH_USR_DeviceNotSupported(); - } - - return status; - -} - - - -/** -* @brief USBH_HID_InterfaceDeInit -* The function DeInit the Host Channels used for the HID class. -* @param pdev: Selected device -* @param hdev: Selected device property -* @retval None -*/ -void USBH_HID_InterfaceDeInit ( USB_OTG_CORE_HANDLE *pdev, - void *phost) -{ - //USBH_HOST *pphost = phost; - - if(HID_Machine.hc_num_in != 0x00) - { - USB_OTG_HC_Halt(pdev, HID_Machine.hc_num_in); - USBH_Free_Channel (pdev, HID_Machine.hc_num_in); - HID_Machine.hc_num_in = 0; /* Reset the Channel as Free */ - } - - if(HID_Machine.hc_num_out != 0x00) - { - USB_OTG_HC_Halt(pdev, HID_Machine.hc_num_out); - USBH_Free_Channel (pdev, HID_Machine.hc_num_out); - HID_Machine.hc_num_out = 0; /* Reset the Channel as Free */ - } - - flag = 0; -} - -/** -* @brief USBH_HID_ClassRequest -* The function is responsible for handling HID Class requests -* for HID class. -* @param pdev: Selected device -* @param hdev: Selected device property -* @retval USBH_Status :Response for USB Set Protocol request -*/ -static USBH_Status USBH_HID_ClassRequest(USB_OTG_CORE_HANDLE *pdev , - void *phost) -{ - USBH_HOST *pphost = phost; - - USBH_Status status = USBH_BUSY; - USBH_Status classReqStatus = USBH_BUSY; - - - /* Switch HID state machine */ - switch (HID_Machine.ctl_state) - { - case HID_IDLE: - case HID_REQ_GET_HID_DESC: - - /* Get HID Desc */ - if (USBH_Get_HID_Descriptor (pdev, pphost, USB_HID_DESC_SIZE)== USBH_OK) - { - - USBH_ParseHIDDesc(&HID_Desc, pdev->host.Rx_Buffer); - HID_Machine.ctl_state = HID_REQ_GET_REPORT_DESC; - } - - break; - case HID_REQ_GET_REPORT_DESC: - - - /* Get Report Desc */ - if (USBH_Get_HID_ReportDescriptor(pdev , pphost, HID_Desc.wItemLength) == USBH_OK) - { - HID_Machine.ctl_state = HID_REQ_SET_IDLE; - } - - break; - - case HID_REQ_SET_IDLE: - - classReqStatus = USBH_Set_Idle (pdev, pphost, 0, 0); - - /* set Idle */ - if (classReqStatus == USBH_OK) - { - HID_Machine.ctl_state = HID_REQ_SET_PROTOCOL; - } - else if(classReqStatus == USBH_NOT_SUPPORTED) - { - HID_Machine.ctl_state = HID_REQ_SET_PROTOCOL; - } - break; - - case HID_REQ_SET_PROTOCOL: - /* set protocol */ - if (USBH_Set_Protocol (pdev ,pphost, 0) == USBH_OK) - { - HID_Machine.ctl_state = HID_REQ_IDLE; - - /* all requests performed*/ - status = USBH_OK; - } - break; - - default: - break; - } - - return status; -} - - -/** -* @brief USBH_HID_Handle -* The function is for managing state machine for HID data transfers -* @param pdev: Selected device -* @param hdev: Selected device property -* @retval USBH_Status -*/ -static USBH_Status USBH_HID_Handle(USB_OTG_CORE_HANDLE *pdev , - void *phost) -{ - USBH_HOST *pphost = phost; - USBH_Status status = USBH_OK; - - switch (HID_Machine.state) - { - - case HID_IDLE: - HID_Machine.cb->Init(); - HID_Machine.state = HID_GET_DATA; - break; - - case HID_GET_DATA: - - /* Sync with start of Even Frame */ - while(USB_OTG_IsEvenFrame(pdev) == FALSE); - - USBH_InterruptReceiveData(pdev, - HID_Machine.buff, - HID_Machine.length, - HID_Machine.hc_num_in); - flag = 1; - - HID_Machine.state = HID_POLL; - HID_Machine.timer = HCD_GetCurrentFrame(pdev); - break; - - case HID_POLL: - if(( HCD_GetCurrentFrame(pdev) - HID_Machine.timer) >= HID_Machine.poll) - { - HID_Machine.state = HID_GET_DATA; - } - else if(HCD_GetURB_State(pdev , HID_Machine.hc_num_in) == URB_DONE) - { - if(flag == 1) /* handle data once */ - { - flag = 0; - HID_Machine.cb->Decode(HID_Machine.buff); - } - } - else if(HCD_GetURB_State(pdev, HID_Machine.hc_num_in) == URB_STALL) /* IN Endpoint Stalled */ - { - - /* Issue Clear Feature on interrupt IN endpoint */ - if( (USBH_ClrFeature(pdev, - pphost, - HID_Machine.ep_addr, - HID_Machine.hc_num_in)) == USBH_OK) - { - /* Change state to issue next IN token */ - HID_Machine.state = HID_GET_DATA; - - } - - } - break; - - default: - break; - } - return status; -} - - -/** -* @brief USBH_Get_HID_ReportDescriptor -* Issue report Descriptor command to the device. Once the response -* received, parse the report descriptor and update the status. -* @param pdev : Selected device -* @param Length : HID Report Descriptor Length -* @retval USBH_Status : Response for USB HID Get Report Descriptor Request -*/ -static USBH_Status USBH_Get_HID_ReportDescriptor (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint16_t length) -{ - - USBH_Status status; - - status = USBH_GetDescriptor(pdev, - phost, - USB_REQ_RECIPIENT_INTERFACE - | USB_REQ_TYPE_STANDARD, - USB_DESC_HID_REPORT, - pdev->host.Rx_Buffer, - length); - - /* HID report descriptor is available in pdev->host.Rx_Buffer. - In case of USB Boot Mode devices for In report handling , - HID report descriptor parsing is not required. - In case, for supporting Non-Boot Protocol devices and output reports, - user may parse the report descriptor*/ - - - return status; -} - -/** -* @brief USBH_Get_HID_Descriptor -* Issue HID Descriptor command to the device. Once the response -* received, parse the report descriptor and update the status. -* @param pdev : Selected device -* @param Length : HID Descriptor Length -* @retval USBH_Status : Response for USB HID Get Report Descriptor Request -*/ -static USBH_Status USBH_Get_HID_Descriptor (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint16_t length) -{ - - USBH_Status status; - - status = USBH_GetDescriptor(pdev, - phost, - USB_REQ_RECIPIENT_INTERFACE - | USB_REQ_TYPE_STANDARD, - USB_DESC_HID, - pdev->host.Rx_Buffer, - length); - - return status; -} - -/** -* @brief USBH_Set_Idle -* Set Idle State. -* @param pdev: Selected device -* @param duration: Duration for HID Idle request -* @param reportID : Targetted report ID for Set Idle request -* @retval USBH_Status : Response for USB Set Idle request -*/ -static USBH_Status USBH_Set_Idle (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t duration, - uint8_t reportId) -{ - - phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE |\ - USB_REQ_TYPE_CLASS; - - - phost->Control.setup.b.bRequest = USB_HID_SET_IDLE; - phost->Control.setup.b.wValue.w = (duration << 8 ) | reportId; - - phost->Control.setup.b.wIndex.w = 0; - phost->Control.setup.b.wLength.w = 0; - - return USBH_CtlReq(pdev, phost, 0 , 0 ); -} - - -/** -* @brief USBH_Set_Report -* Issues Set Report -* @param pdev: Selected device -* @param reportType : Report type to be sent -* @param reportID : Targetted report ID for Set Report request -* @param reportLen : Length of data report to be send -* @param reportBuff : Report Buffer -* @retval USBH_Status : Response for USB Set Idle request -*/ -USBH_Status USBH_Set_Report (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t reportType, - uint8_t reportId, - uint8_t reportLen, - uint8_t* reportBuff) -{ - - phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE |\ - USB_REQ_TYPE_CLASS; - - - phost->Control.setup.b.bRequest = USB_HID_SET_REPORT; - phost->Control.setup.b.wValue.w = (reportType << 8 ) | reportId; - - phost->Control.setup.b.wIndex.w = 0; - phost->Control.setup.b.wLength.w = reportLen; - - return USBH_CtlReq(pdev, phost, reportBuff , reportLen ); -} - - -/** -* @brief USBH_Set_Protocol -* Set protocol State. -* @param pdev: Selected device -* @param protocol : Set Protocol for HID : boot/report protocol -* @retval USBH_Status : Response for USB Set Protocol request -*/ -static USBH_Status USBH_Set_Protocol(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t protocol) -{ - - - phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_INTERFACE |\ - USB_REQ_TYPE_CLASS; - - - phost->Control.setup.b.bRequest = USB_HID_SET_PROTOCOL; - - if(protocol != 0) - { - /* Boot Protocol */ - phost->Control.setup.b.wValue.w = 0; - } - else - { - /*Report Protocol*/ - phost->Control.setup.b.wValue.w = 1; - } - - phost->Control.setup.b.wIndex.w = 0; - phost->Control.setup.b.wLength.w = 0; - - return USBH_CtlReq(pdev, phost, 0 , 0 ); - -} - -/** -* @brief USBH_ParseHIDDesc -* This function Parse the HID descriptor -* @param buf: Buffer where the source descriptor is available -* @retval None -*/ -static void USBH_ParseHIDDesc (USBH_HIDDesc_TypeDef *desc, uint8_t *buf) -{ - - desc->bLength = *(uint8_t *) (buf + 0); - desc->bDescriptorType = *(uint8_t *) (buf + 1); - desc->bcdHID = LE16 (buf + 2); - desc->bCountryCode = *(uint8_t *) (buf + 4); - desc->bNumDescriptors = *(uint8_t *) (buf + 5); - desc->bReportDescriptorType = *(uint8_t *) (buf + 6); - desc->wItemLength = LE16 (buf + 7); - -} -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - - -/** -* @} -*/ - - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_HOST_Library/Class/HID/src/usbh_hid_keybd.c b/example/stm32f4/STM32_USB_HOST_Library/Class/HID/src/usbh_hid_keybd.c deleted file mode 100644 index ae0df34d2..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Class/HID/src/usbh_hid_keybd.c +++ /dev/null @@ -1,338 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hid_keybd.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief This file is the application layer for USB Host HID Keyboard handling - * QWERTY and AZERTY Keyboard are supported as per the selection in - * usbh_hid_keybd.h - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_hid_keybd.h" - -/** @addtogroup USBH_LIB -* @{ -*/ - -/** @addtogroup USBH_CLASS -* @{ -*/ - -/** @addtogroup USBH_HID_CLASS -* @{ -*/ - -/** @defgroup USBH_HID_KEYBD -* @brief This file includes HID Layer Handlers for USB Host HID class. -* @{ -*/ - -/** @defgroup USBH_HID_KEYBD_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_HID_KEYBD_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_HID_KEYBD_Private_Macros -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USBH_HID_KEYBD_Private_FunctionPrototypes -* @{ -*/ -static void KEYBRD_Init (void); -static void KEYBRD_Decode(uint8_t *data); - -/** -* @} -*/ - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined (__CC_ARM) /*!< ARM Compiler */ - __align(4) - #elif defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #elif defined (__GNUC__) /*!< GNU Compiler */ - #pragma pack(4) - #elif defined (__TASKING__) /*!< TASKING Compiler */ - __align(4) - #endif /* __CC_ARM */ -#endif - -/** @defgroup USBH_HID_KEYBD_Private_Variables -* @{ -*/ -HID_cb_TypeDef HID_KEYBRD_cb= -{ - KEYBRD_Init, - KEYBRD_Decode -}; - -/* -******************************************************************************* -* LOCAL CONSTANTS -******************************************************************************* -*/ - -static const uint8_t HID_KEYBRD_Codes[] = { - 0, 0, 0, 0, 31, 50, 48, 33, - 19, 34, 35, 36, 24, 37, 38, 39, /* 0x00 - 0x0F */ - 52, 51, 25, 26, 17, 20, 32, 21, - 23, 49, 18, 47, 22, 46, 2, 3, /* 0x10 - 0x1F */ - 4, 5, 6, 7, 8, 9, 10, 11, - 43, 110, 15, 16, 61, 12, 13, 27, /* 0x20 - 0x2F */ - 28, 29, 42, 40, 41, 1, 53, 54, - 55, 30, 112, 113, 114, 115, 116, 117, /* 0x30 - 0x3F */ - 118, 119, 120, 121, 122, 123, 124, 125, - 126, 75, 80, 85, 76, 81, 86, 89, /* 0x40 - 0x4F */ - 79, 84, 83, 90, 95, 100, 105, 106, - 108, 93, 98, 103, 92, 97, 102, 91, /* 0x50 - 0x5F */ - 96, 101, 99, 104, 45, 129, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0x60 - 0x6F */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0x70 - 0x7F */ - 0, 0, 0, 0, 0, 107, 0, 56, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0x80 - 0x8F */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0x90 - 0x9F */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0xA0 - 0xAF */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0xB0 - 0xBF */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0xC0 - 0xCF */ - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, /* 0xD0 - 0xDF */ - 58, 44, 60, 127, 64, 57, 62, 128 /* 0xE0 - 0xE7 */ -}; - -#ifdef QWERTY_KEYBOARD -static const int8_t HID_KEYBRD_Key[] = { - '\0', '`', '1', '2', '3', '4', '5', '6', - '7', '8', '9', '0', '-', '=', '\0', '\r', - '\t', 'q', 'w', 'e', 'r', 't', 'y', 'u', - 'i', 'o', 'p', '[', ']', '\\', - '\0', 'a', 's', 'd', 'f', 'g', 'h', 'j', - 'k', 'l', ';', '\'', '\0', '\n', - '\0', '\0', 'z', 'x', 'c', 'v', 'b', 'n', - 'm', ',', '.', '/', '\0', '\0', - '\0', '\0', '\0', ' ', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '7', '4', '1', - '\0', '/', '8', '5', '2', - '0', '*', '9', '6', '3', - '.', '-', '+', '\0', '\n', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0' -}; - -static const int8_t HID_KEYBRD_ShiftKey[] = { - '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', - '_', '+', '\0', '\0', '\0', 'Q', 'W', 'E', 'R', 'T', 'Y', 'U', - 'I', 'O', 'P', '{', '}', '|', '\0', 'A', 'S', 'D', 'F', 'G', - 'H', 'J', 'K', 'L', ':', '"', '\0', '\n', '\0', '\0', 'Z', 'X', - 'C', 'V', 'B', 'N', 'M', '<', '>', '?', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' -}; - -#else - -static const int8_t HID_KEYBRD_Key[] = { - '\0', '`', '1', '2', '3', '4', '5', '6', '7', '8', '9', '0', - '-', '=', '\0', '\r', '\t', 'a', 'z', 'e', 'r', 't', 'y', 'u', - 'i', 'o', 'p', '[', ']', '\\', '\0', 'q', 's', 'd', 'f', 'g', - 'h', 'j', 'k', 'l', 'm', '\0', '\0', '\n', '\0', '\0', 'w', 'x', - 'c', 'v', 'b', 'n', ',', ';', ':', '!', '\0', '\0', '\0', '\0', - '\0', ' ', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\r', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '7', '4', '1','\0', '/', - '8', '5', '2', '0', '*', '9', '6', '3', '.', '-', '+', '\0', - '\n', '\0', '\0', '\0', '\0', '\0', '\0','\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' -}; - -static const int8_t HID_KEYBRD_ShiftKey[] = { - '\0', '~', '!', '@', '#', '$', '%', '^', '&', '*', '(', ')', '_', - '+', '\0', '\0', '\0', 'A', 'Z', 'E', 'R', 'T', 'Y', 'U', 'I', 'O', - 'P', '{', '}', '*', '\0', 'Q', 'S', 'D', 'F', 'G', 'H', 'J', 'K', - 'L', 'M', '%', '\0', '\n', '\0', '\0', 'W', 'X', 'C', 'V', 'B', 'N', - '?', '.', '/', '\0', '\0', '\0','\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', - '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0', '\0' -}; -#endif - -/** -* @} -*/ - - -/** @defgroup USBH_HID_KEYBD_Private_Functions -* @{ -*/ - - -/** -* @brief KEYBRD_Init. -* Initialize the keyboard function. -* @param None -* @retval None -*/ -static void KEYBRD_Init (void) -{ - /* Call User Init*/ - USR_KEYBRD_Init(); -} - -/** -* @brief KEYBRD_ProcessData. -* The function is to decode the pressed keys. -* @param pbuf : Pointer to the HID IN report data buffer -* @retval None -*/ - -static void KEYBRD_Decode(uint8_t *pbuf) -{ - static uint8_t shift; - static uint8_t keys[KBR_MAX_NBR_PRESSED]; - static uint8_t keys_new[KBR_MAX_NBR_PRESSED]; - static uint8_t keys_last[KBR_MAX_NBR_PRESSED]; - static uint8_t key_newest; - static uint8_t nbr_keys; - static uint8_t nbr_keys_new; - static uint8_t nbr_keys_last; - uint8_t ix; - uint8_t jx; - uint8_t error; - uint8_t output; - - nbr_keys = 0; - nbr_keys_new = 0; - nbr_keys_last = 0; - key_newest = 0x00; - - - /* Check if Shift key is pressed */ - if ((pbuf[0] == KBD_LEFT_SHIFT) || (pbuf[0] == KBD_RIGHT_SHIFT)) { - shift = TRUE; - } else { - shift = FALSE; - } - - error = FALSE; - - /* Check for the value of pressed key */ - for (ix = 2; ix < 2 + KBR_MAX_NBR_PRESSED; ix++) { - if ((pbuf[ix] == 0x01) || - (pbuf[ix] == 0x02) || - (pbuf[ix] == 0x03)) { - error = TRUE; - } - } - - if (error == TRUE) { - return; - } - - nbr_keys = 0; - nbr_keys_new = 0; - for (ix = 2; ix < 2 + KBR_MAX_NBR_PRESSED; ix++) { - if (pbuf[ix] != 0) { - keys[nbr_keys] = pbuf[ix]; - nbr_keys++; - for (jx = 0; jx < nbr_keys_last; jx++) { - if (pbuf[ix] == keys_last[jx]) { - break; - } - } - - if (jx == nbr_keys_last) { - keys_new[nbr_keys_new] = pbuf[ix]; - nbr_keys_new++; - } - } - } - - if (nbr_keys_new == 1) { - key_newest = keys_new[0]; - - if (shift == TRUE) { - output = HID_KEYBRD_ShiftKey[HID_KEYBRD_Codes[key_newest]]; - } else { - output = HID_KEYBRD_Key[HID_KEYBRD_Codes[key_newest]]; - } - - /* call user process handle */ - USR_KEYBRD_ProcessData(output); - } else { - key_newest = 0x00; - } - - - nbr_keys_last = nbr_keys; - for (ix = 0; ix < KBR_MAX_NBR_PRESSED; ix++) { - keys_last[ix] = keys[ix]; - } -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Class/HID/src/usbh_hid_mouse.c b/example/stm32f4/STM32_USB_HOST_Library/Class/HID/src/usbh_hid_mouse.c deleted file mode 100644 index f3ec2fc93..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Class/HID/src/usbh_hid_mouse.c +++ /dev/null @@ -1,155 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hid_mouse.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief This file is the application layer for USB Host HID Mouse Handling. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_hid_mouse.h" - - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_CLASS - * @{ - */ - -/** @addtogroup USBH_HID_CLASS - * @{ - */ - -/** @defgroup USBH_HID_MOUSE - * @brief This file includes HID Layer Handlers for USB Host HID class. - * @{ - */ - -/** @defgroup USBH_HID_MOUSE_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_HID_MOUSE_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_HID_MOUSE_Private_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HID_MOUSE_Private_FunctionPrototypes - * @{ - */ -static void MOUSE_Init (void); -static void MOUSE_Decode(uint8_t *data); -/** - * @} - */ - - -/** @defgroup USBH_HID_MOUSE_Private_Variables - * @{ - */ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined (__CC_ARM) /*!< ARM Compiler */ - __align(4) - #elif defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #elif defined (__GNUC__) /*!< GNU Compiler */ - #pragma pack(4) - #elif defined (__TASKING__) /*!< TASKING Compiler */ - __align(4) - #endif /* __CC_ARM */ -#endif - - -HID_MOUSE_Data_TypeDef HID_MOUSE_Data; -HID_cb_TypeDef HID_MOUSE_cb = -{ - MOUSE_Init, - MOUSE_Decode, -}; -/** - * @} - */ - - -/** @defgroup USBH_HID_MOUSE_Private_Functions - * @{ - */ - -/** -* @brief MOUSE_Init -* Init Mouse State. -* @param None -* @retval None -*/ -static void MOUSE_Init ( void) -{ - /* Call User Init*/ - USR_MOUSE_Init(); -} - -/** -* @brief MOUSE_Decode -* Decode Mouse data -* @param data : Pointer to Mouse HID data buffer -* @retval None -*/ -static void MOUSE_Decode(uint8_t *data) -{ - HID_MOUSE_Data.button = data[0]; - - HID_MOUSE_Data.x = data[1]; - HID_MOUSE_Data.y = data[2]; - - USR_MOUSE_ProcessData(&HID_MOUSE_Data); - -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_bot.h b/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_bot.h deleted file mode 100644 index 27e96598d..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_bot.h +++ /dev/null @@ -1,221 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_msc_bot.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Header file for usbh_msc_bot.c - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive ----------------------------------------------*/ -#ifndef __USBH_MSC_BOT_H__ -#define __USBH_MSC_BOT_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_stdreq.h" - - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_CLASS - * @{ - */ - -/** @addtogroup USBH_MSC_CLASS - * @{ - */ - -/** @defgroup USBH_MSC_BOT - * @brief This file is the Header file for usbh_msc_core.c - * @{ - */ - - -/** @defgroup USBH_MSC_BOT_Exported_Types - * @{ - */ - -typedef union _USBH_CBW_Block -{ - struct __CBW - { - uint32_t CBWSignature; - uint32_t CBWTag; - uint32_t CBWTransferLength; - uint8_t CBWFlags; - uint8_t CBWLUN; - uint8_t CBWLength; - uint8_t CBWCB[16]; -}field; - uint8_t CBWArray[31]; -}HostCBWPkt_TypeDef; - -typedef enum -{ - USBH_MSC_BOT_INIT_STATE = 0, - USBH_MSC_BOT_RESET, - USBH_MSC_GET_MAX_LUN, - USBH_MSC_TEST_UNIT_READY, - USBH_MSC_READ_CAPACITY10, - USBH_MSC_MODE_SENSE6, - USBH_MSC_REQUEST_SENSE, - USBH_MSC_BOT_USB_TRANSFERS, - USBH_MSC_DEFAULT_APPLI_STATE, - USBH_MSC_CTRL_ERROR_STATE, - USBH_MSC_UNRECOVERED_STATE -} -MSCState; - - -typedef struct _BOTXfer -{ -uint8_t MSCState; -uint8_t MSCStateBkp; -uint8_t MSCStateCurrent; -uint8_t CmdStateMachine; -uint8_t BOTState; -uint8_t BOTStateBkp; -uint8_t* pRxTxBuff; -uint16_t DataLength; -uint8_t BOTXferErrorCount; -uint8_t BOTXferStatus; -} USBH_BOTXfer_TypeDef; - - -typedef union _USBH_CSW_Block -{ - struct __CSW - { - uint32_t CSWSignature; - uint32_t CSWTag; - uint32_t CSWDataResidue; - uint8_t CSWStatus; - }field; - uint8_t CSWArray[13]; -}HostCSWPkt_TypeDef; - -/** - * @} - */ - - - -/** @defgroup USBH_MSC_BOT_Exported_Defines - * @{ - */ -#define USBH_MSC_SEND_CBW 1 -#define USBH_MSC_SENT_CBW 2 -#define USBH_MSC_BOT_DATAIN_STATE 3 -#define USBH_MSC_BOT_DATAOUT_STATE 4 -#define USBH_MSC_RECEIVE_CSW_STATE 5 -#define USBH_MSC_DECODE_CSW 6 -#define USBH_MSC_BOT_ERROR_IN 7 -#define USBH_MSC_BOT_ERROR_OUT 8 - - -#define USBH_MSC_BOT_CBW_SIGNATURE 0x43425355 -#define USBH_MSC_BOT_CBW_TAG 0x20304050 -#define USBH_MSC_BOT_CSW_SIGNATURE 0x53425355 -#define USBH_MSC_CSW_DATA_LENGTH 0x000D -#define USBH_MSC_BOT_CBW_PACKET_LENGTH 31 -#define USBH_MSC_CSW_LENGTH 13 -#define USBH_MSC_CSW_MAX_LENGTH 63 - -/* CSW Status Definitions */ -#define USBH_MSC_CSW_CMD_PASSED 0x00 -#define USBH_MSC_CSW_CMD_FAILED 0x01 -#define USBH_MSC_CSW_PHASE_ERROR 0x02 - -#define USBH_MSC_SEND_CSW_DISABLE 0 -#define USBH_MSC_SEND_CSW_ENABLE 1 - -#define USBH_MSC_DIR_IN 0 -#define USBH_MSC_DIR_OUT 1 -#define USBH_MSC_BOTH_DIR 2 - -//#define USBH_MSC_PAGE_LENGTH 0x40 -#define USBH_MSC_PAGE_LENGTH 512 - - -#define CBW_CB_LENGTH 16 -#define CBW_LENGTH 10 -#define CBW_LENGTH_TEST_UNIT_READY 6 - -#define USB_REQ_BOT_RESET 0xFF -#define USB_REQ_GET_MAX_LUN 0xFE - -#define MAX_BULK_STALL_COUNT_LIMIT 0x04 /* If STALL is seen on Bulk - Endpoint continously, this means - that device and Host has phase error - Hence a Reset is needed */ - -/** - * @} - */ - -/** @defgroup USBH_MSC_BOT_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_MSC_BOT_Exported_Variables - * @{ - */ -extern USBH_BOTXfer_TypeDef USBH_MSC_BOTXferParam; -extern HostCBWPkt_TypeDef USBH_MSC_CBWData; -extern HostCSWPkt_TypeDef USBH_MSC_CSWData; -/** - * @} - */ - -/** @defgroup USBH_MSC_BOT_Exported_FunctionsPrototype - * @{ - */ -void USBH_MSC_HandleBOTXfer(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost); -uint8_t USBH_MSC_DecodeCSW(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost); -void USBH_MSC_Init(USB_OTG_CORE_HANDLE *pdev); -USBH_Status USBH_MSC_BOT_Abort(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t direction); -/** - * @} - */ - -#endif //__USBH_MSC_BOT_H__ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_core.h b/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_core.h deleted file mode 100644 index 72ab4cef3..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_core.h +++ /dev/null @@ -1,141 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_msc_core.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief This file contains all the prototypes for the usbh_msc_core.c - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive ----------------------------------------------*/ -#ifndef __USBH_MSC_CORE_H -#define __USBH_MSC_CORE_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_core.h" -#include "usbh_stdreq.h" -#include "usb_bsp.h" -#include "usbh_ioreq.h" -#include "usbh_hcs.h" -#include "usbh_msc_core.h" -#include "usbh_msc_scsi.h" -#include "usbh_msc_bot.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_CLASS - * @{ - */ - -/** @addtogroup USBH_MSC_CLASS - * @{ - */ - -/** @defgroup USBH_MSC_CORE - * @brief This file is the Header file for usbh_msc_core.c - * @{ - */ - - -/** @defgroup USBH_MSC_CORE_Exported_Types - * @{ - */ - - -/* Structure for MSC process */ -typedef struct _MSC_Process -{ - uint8_t hc_num_in; - uint8_t hc_num_out; - uint8_t MSBulkOutEp; - uint8_t MSBulkInEp; - uint16_t MSBulkInEpSize; - uint16_t MSBulkOutEpSize; - uint8_t buff[USBH_MSC_MPS_SIZE]; - uint8_t maxLun; -} -MSC_Machine_TypeDef; - - -/** - * @} - */ - - - -/** @defgroup USBH_MSC_CORE_Exported_Defines - * @{ - */ - -#define USB_REQ_BOT_RESET 0xFF -#define USB_REQ_GET_MAX_LUN 0xFE - - -/** - * @} - */ - -/** @defgroup USBH_MSC_CORE_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_MSC_CORE_Exported_Variables - * @{ - */ -extern USBH_Class_cb_TypeDef USBH_MSC_cb; -extern MSC_Machine_TypeDef MSC_Machine; -extern uint8_t MSCErrorCount; - -/** - * @} - */ - -/** @defgroup USBH_MSC_CORE_Exported_FunctionsPrototype - * @{ - */ - - - -/** - * @} - */ - -#endif /* __USBH_MSC_CORE_H */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_scsi.h b/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_scsi.h deleted file mode 100644 index 3bdf4ec6d..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/inc/usbh_msc_scsi.h +++ /dev/null @@ -1,163 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_msc_scsi.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Header file for usbh_msc_scsi.c - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive ----------------------------------------------*/ -#ifndef __USBH_MSC_SCSI_H__ -#define __USBH_MSC_SCSI_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_stdreq.h" - - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_CLASS - * @{ - */ - -/** @addtogroup USBH_MSC_CLASS - * @{ - */ - -/** @defgroup USBH_MSC_SCSI - * @brief This file is the Header file for usbh_msc_scsi.c - * @{ - */ - - -/** @defgroup USBH_MSC_SCSI_Exported_Types - * @{ - */ -typedef enum { - USBH_MSC_OK = 0, - USBH_MSC_FAIL = 1, - USBH_MSC_PHASE_ERROR = 2, - USBH_MSC_BUSY = 3 -}USBH_MSC_Status_TypeDef; - -typedef enum { - CMD_UNINITIALIZED_STATE =0, - CMD_SEND_STATE, - CMD_WAIT_STATUS -} CMD_STATES_TypeDef; - - - -typedef struct __MassStorageParameter -{ - uint32_t MSCapacity; - uint32_t MSSenseKey; - uint16_t MSPageLength; - uint8_t MSBulkOutEp; - uint8_t MSBulkInEp; - uint8_t MSWriteProtect; -} MassStorageParameter_TypeDef; -/** - * @} - */ - - - -/** @defgroup USBH_MSC_SCSI_Exported_Defines - * @{ - */ - - - -#define OPCODE_TEST_UNIT_READY 0X00 -#define OPCODE_READ_CAPACITY10 0x25 -#define OPCODE_MODE_SENSE6 0x1A -#define OPCODE_READ10 0x28 -#define OPCODE_WRITE10 0x2A -#define OPCODE_REQUEST_SENSE 0x03 - -#define DESC_REQUEST_SENSE 0X00 -#define ALLOCATION_LENGTH_REQUEST_SENSE 63 -#define XFER_LEN_READ_CAPACITY10 8 -#define XFER_LEN_MODE_SENSE6 63 - -#define MASK_MODE_SENSE_WRITE_PROTECT 0x80 -#define MODE_SENSE_PAGE_CONTROL_FIELD 0x00 -#define MODE_SENSE_PAGE_CODE 0x3F -#define DISK_WRITE_PROTECTED 0x01 -/** - * @} - */ - -/** @defgroup USBH_MSC_SCSI_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup _Exported_Variables - * @{ - */ -extern MassStorageParameter_TypeDef USBH_MSC_Param; -/** - * @} - */ - -/** @defgroup USBH_MSC_SCSI_Exported_FunctionsPrototype - * @{ - */ -uint8_t USBH_MSC_TestUnitReady(USB_OTG_CORE_HANDLE *pdev); -uint8_t USBH_MSC_ReadCapacity10(USB_OTG_CORE_HANDLE *pdev); -uint8_t USBH_MSC_ModeSense6(USB_OTG_CORE_HANDLE *pdev); -uint8_t USBH_MSC_RequestSense(USB_OTG_CORE_HANDLE *pdev); -uint8_t USBH_MSC_Write10(USB_OTG_CORE_HANDLE *pdev, - uint8_t *, - uint32_t , - uint32_t ); -uint8_t USBH_MSC_Read10(USB_OTG_CORE_HANDLE *pdev, - uint8_t *, - uint32_t , - uint32_t ); -void USBH_MSC_StateMachine(USB_OTG_CORE_HANDLE *pdev); - -/** - * @} - */ - -#endif //__USBH_MSC_SCSI_H__ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/src/usbh_msc_bot.c b/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/src/usbh_msc_bot.c deleted file mode 100644 index eeb10755b..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/src/usbh_msc_bot.c +++ /dev/null @@ -1,613 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_msc_bot.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief This file includes the mass storage related functions - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_msc_core.h" -#include "usbh_msc_scsi.h" -#include "usbh_msc_bot.h" -#include "usbh_ioreq.h" -#include "usbh_def.h" -#include "usb_hcd_int.h" - - -/** @addtogroup USBH_LIB -* @{ -*/ - -/** @addtogroup USBH_CLASS -* @{ -*/ - -/** @addtogroup USBH_MSC_CLASS -* @{ -*/ - -/** @defgroup USBH_MSC_BOT -* @brief This file includes the mass storage related functions -* @{ -*/ - - -/** @defgroup USBH_MSC_BOT_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USBH_MSC_BOT_Private_Defines -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USBH_MSC_BOT_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_MSC_BOT_Private_Variables -* @{ -*/ - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN HostCBWPkt_TypeDef USBH_MSC_CBWData __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN HostCSWPkt_TypeDef USBH_MSC_CSWData __ALIGN_END ; - - -static uint32_t BOTStallErrorCount; /* Keeps count of STALL Error Cases*/ - -/** -* @} -*/ - - -/** @defgroup USBH_MSC_BOT_Private_FunctionPrototypes -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_MSC_BOT_Exported_Variables -* @{ -*/ -USBH_BOTXfer_TypeDef USBH_MSC_BOTXferParam; -/** -* @} -*/ - - -/** @defgroup USBH_MSC_BOT_Private_Functions -* @{ -*/ - - -/** -* @brief USBH_MSC_Init -* Initializes the mass storage parameters -* @param None -* @retval None -*/ -void USBH_MSC_Init(USB_OTG_CORE_HANDLE *pdev ) -{ - if(HCD_IsDeviceConnected(pdev)) - { - USBH_MSC_CBWData.field.CBWSignature = USBH_MSC_BOT_CBW_SIGNATURE; - USBH_MSC_CBWData.field.CBWTag = USBH_MSC_BOT_CBW_TAG; - USBH_MSC_CBWData.field.CBWLUN = 0; /*Only one LUN is supported*/ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - } - - BOTStallErrorCount = 0; - MSCErrorCount = 0; -} - -/** -* @brief USBH_MSC_HandleBOTXfer -* This function manages the different states of BOT transfer and -* updates the status to upper layer. -* @param None -* @retval None -* -*/ -void USBH_MSC_HandleBOTXfer (USB_OTG_CORE_HANDLE *pdev ,USBH_HOST *phost) -{ - uint8_t xferDirection, index; - static uint32_t remainingDataLength; - static uint8_t *datapointer; - static uint8_t error_direction; - USBH_Status status; - - URB_STATE URB_Status = URB_IDLE; - - if(HCD_IsDeviceConnected(pdev)) - { - - switch (USBH_MSC_BOTXferParam.BOTState) - { - case USBH_MSC_SEND_CBW: - /* send CBW */ - USBH_BulkSendData (pdev, - &USBH_MSC_CBWData.CBWArray[0], - USBH_MSC_BOT_CBW_PACKET_LENGTH , - MSC_Machine.hc_num_out); - - USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_SEND_CBW; - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SENT_CBW; - - break; - - case USBH_MSC_SENT_CBW: - URB_Status = HCD_GetURB_State(pdev , MSC_Machine.hc_num_out); - - if(URB_Status == URB_DONE) - { - BOTStallErrorCount = 0; - USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_SENT_CBW; - - /* If the CBW Pkt is sent successful, then change the state */ - xferDirection = (USBH_MSC_CBWData.field.CBWFlags & USB_REQ_DIR_MASK); - - if ( USBH_MSC_CBWData.field.CBWTransferLength != 0 ) - { - remainingDataLength = USBH_MSC_CBWData.field.CBWTransferLength ; - datapointer = USBH_MSC_BOTXferParam.pRxTxBuff; - - /* If there is Data Transfer Stage */ - if (xferDirection == USB_D2H) - { - /* Data Direction is IN */ - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_DATAIN_STATE; - } - else - { - /* Data Direction is OUT */ - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_DATAOUT_STATE; - } - } - - else - {/* If there is NO Data Transfer Stage */ - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_RECEIVE_CSW_STATE; - } - - } - else if(URB_Status == URB_NOTREADY) - { - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; - } - else if(URB_Status == URB_STALL) - { - error_direction = USBH_MSC_DIR_OUT; - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_ERROR_OUT; - } - break; - - case USBH_MSC_BOT_DATAIN_STATE: - - URB_Status = HCD_GetURB_State(pdev , MSC_Machine.hc_num_in); - /* BOT DATA IN stage */ - if((URB_Status == URB_DONE) ||(USBH_MSC_BOTXferParam.BOTStateBkp != USBH_MSC_BOT_DATAIN_STATE)) - { - BOTStallErrorCount = 0; - USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_BOT_DATAIN_STATE; - - if(remainingDataLength > USBH_MSC_MPS_SIZE) - { - USBH_BulkReceiveData (pdev, - datapointer, - USBH_MSC_MPS_SIZE , - MSC_Machine.hc_num_in); - - remainingDataLength -= USBH_MSC_MPS_SIZE; - datapointer = datapointer + USBH_MSC_MPS_SIZE; - } - else if ( remainingDataLength == 0) - { - /* If value was 0, and successful transfer, then change the state */ - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_RECEIVE_CSW_STATE; - } - else - { - USBH_BulkReceiveData (pdev, - datapointer, - remainingDataLength , - MSC_Machine.hc_num_in); - - remainingDataLength = 0; /* Reset this value and keep in same state */ - } - } - else if(URB_Status == URB_STALL) - { - /* This is Data Stage STALL Condition */ - - error_direction = USBH_MSC_DIR_IN; - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_ERROR_IN; - - /* Refer to USB Mass-Storage Class : BOT (www.usb.org) - 6.7.2 Host expects to receive data from the device - 3. On a STALL condition receiving data, then: - The host shall accept the data received. - The host shall clear the Bulk-In pipe. - 4. The host shall attempt to receive a CSW. - - USBH_MSC_BOTXferParam.BOTStateBkp is used to switch to the Original - state after the ClearFeature Command is issued. - */ - USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_RECEIVE_CSW_STATE; - - } - break; - - - case USBH_MSC_BOT_DATAOUT_STATE: - /* BOT DATA OUT stage */ - URB_Status = HCD_GetURB_State(pdev , MSC_Machine.hc_num_out); - if(URB_Status == URB_DONE) - { - BOTStallErrorCount = 0; - USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_BOT_DATAOUT_STATE; - if(remainingDataLength > USBH_MSC_MPS_SIZE) - { - USBH_BulkSendData (pdev, - datapointer, - USBH_MSC_MPS_SIZE , - MSC_Machine.hc_num_out); - datapointer = datapointer + USBH_MSC_MPS_SIZE; - remainingDataLength = remainingDataLength - USBH_MSC_MPS_SIZE; - } - else if ( remainingDataLength == 0) - { - /* If value was 0, and successful transfer, then change the state */ - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_RECEIVE_CSW_STATE; - } - else - { - USBH_BulkSendData (pdev, - datapointer, - remainingDataLength , - MSC_Machine.hc_num_out); - - remainingDataLength = 0; /* Reset this value and keep in same state */ - } - } - - else if(URB_Status == URB_NOTREADY) - { - USBH_BulkSendData (pdev, - (datapointer - USBH_MSC_MPS_SIZE), - USBH_MSC_MPS_SIZE , - MSC_Machine.hc_num_out); - } - - else if(URB_Status == URB_STALL) - { - error_direction = USBH_MSC_DIR_OUT; - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_ERROR_OUT; - - /* Refer to USB Mass-Storage Class : BOT (www.usb.org) - 6.7.3 Ho - Host expects to send data to the device - 3. On a STALL condition sending data, then: - " The host shall clear the Bulk-Out pipe. - 4. The host shall attempt to receive a CSW. - - The Above statement will do the clear the Bulk-Out pipe. - The Below statement will help in Getting the CSW. - - USBH_MSC_BOTXferParam.BOTStateBkp is used to switch to the Original - state after the ClearFeature Command is issued. - */ - - USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_RECEIVE_CSW_STATE; - - } - break; - - case USBH_MSC_RECEIVE_CSW_STATE: - /* BOT CSW stage */ - /* NOTE: We cannot reset the BOTStallErrorCount here as it may come from - the clearFeature from previous command */ - - USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_RECEIVE_CSW_STATE; - - USBH_MSC_BOTXferParam.pRxTxBuff = USBH_MSC_CSWData.CSWArray; - USBH_MSC_BOTXferParam.DataLength = USBH_MSC_CSW_MAX_LENGTH; - - for(index = USBH_MSC_CSW_LENGTH; index != 0; index--) - { - USBH_MSC_CSWData.CSWArray[index] = 0; - } - - USBH_MSC_CSWData.CSWArray[0] = 0; - - USBH_BulkReceiveData (pdev, - USBH_MSC_BOTXferParam.pRxTxBuff, - USBH_MSC_CSW_MAX_LENGTH , - MSC_Machine.hc_num_in); - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_DECODE_CSW; - - break; - - case USBH_MSC_DECODE_CSW: - URB_Status = HCD_GetURB_State(pdev , MSC_Machine.hc_num_in); - /* Decode CSW */ - if(URB_Status == URB_DONE) - { - BOTStallErrorCount = 0; - USBH_MSC_BOTXferParam.BOTStateBkp = USBH_MSC_RECEIVE_CSW_STATE; - - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateCurrent ; - - USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_DecodeCSW(pdev , phost); - } - else if(URB_Status == URB_STALL) - { - error_direction = USBH_MSC_DIR_IN; - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_ERROR_IN; - } - break; - - case USBH_MSC_BOT_ERROR_IN: - status = USBH_MSC_BOT_Abort(pdev, phost, USBH_MSC_DIR_IN); - if (status == USBH_OK) - { - /* Check if the error was due in Both the directions */ - if (error_direction == USBH_MSC_BOTH_DIR) - {/* If Both directions are Needed, Switch to OUT Direction */ - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOT_ERROR_OUT; - } - else - { - /* Switch Back to the Original State, In many cases this will be - USBH_MSC_RECEIVE_CSW_STATE state */ - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; - } - } - else if (status == USBH_UNRECOVERED_ERROR) - { - /* This means that there is a STALL Error limit, Do Reset Recovery */ - USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_PHASE_ERROR; - } - break; - - case USBH_MSC_BOT_ERROR_OUT: - status = USBH_MSC_BOT_Abort(pdev, phost, USBH_MSC_DIR_OUT); - if ( status == USBH_OK) - { /* Switch Back to the Original State */ - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_BOTXferParam.BOTStateBkp; - } - else if (status == USBH_UNRECOVERED_ERROR) - { - /* This means that there is a STALL Error limit, Do Reset Recovery */ - USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_PHASE_ERROR; - } - break; - - default: - break; - } - } -} - -/** -* @brief USBH_MSC_BOT_Abort -* This function manages the different Error handling for STALL -* @param direction : IN / OUT -* @retval None -*/ -USBH_Status USBH_MSC_BOT_Abort(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t direction) -{ - USBH_Status status; - - status = USBH_BUSY; - - switch (direction) - { - case USBH_MSC_DIR_IN : - /* send ClrFeture on Bulk IN endpoint */ - status = USBH_ClrFeature(pdev, - phost, - MSC_Machine.MSBulkInEp, - MSC_Machine.hc_num_in); - - break; - - case USBH_MSC_DIR_OUT : - /*send ClrFeature on Bulk OUT endpoint */ - status = USBH_ClrFeature(pdev, - phost, - MSC_Machine.MSBulkOutEp, - MSC_Machine.hc_num_out); - break; - - default: - break; - } - - BOTStallErrorCount++; /* Check Continous Number of times, STALL has Occured */ - if (BOTStallErrorCount > MAX_BULK_STALL_COUNT_LIMIT ) - { - status = USBH_UNRECOVERED_ERROR; - } - - return status; -} - -/** -* @brief USBH_MSC_DecodeCSW -* This function decodes the CSW received by the device and updates the -* same to upper layer. -* @param None -* @retval On success USBH_MSC_OK, on failure USBH_MSC_FAIL -* @notes -* Refer to USB Mass-Storage Class : BOT (www.usb.org) -* 6.3.1 Valid CSW Conditions : -* The host shall consider the CSW valid when: -* 1. dCSWSignature is equal to 53425355h -* 2. the CSW is 13 (Dh) bytes in length, -* 3. dCSWTag matches the dCBWTag from the corresponding CBW. -*/ - -uint8_t USBH_MSC_DecodeCSW(USB_OTG_CORE_HANDLE *pdev , USBH_HOST *phost) -{ - uint8_t status; - uint32_t dataXferCount = 0; - status = USBH_MSC_FAIL; - - if(HCD_IsDeviceConnected(pdev)) - { - /*Checking if the transfer length is diffrent than 13*/ - dataXferCount = HCD_GetXferCnt(pdev, MSC_Machine.hc_num_in); - - if(dataXferCount != USBH_MSC_CSW_LENGTH) - { - /*(4) Hi > Dn (Host expects to receive data from the device, - Device intends to transfer no data) - (5) Hi > Di (Host expects to receive data from the device, - Device intends to send data to the host) - (9) Ho > Dn (Host expects to send data to the device, - Device intends to transfer no data) - (11) Ho > Do (Host expects to send data to the device, - Device intends to receive data from the host)*/ - - - status = USBH_MSC_PHASE_ERROR; - } - else - { /* CSW length is Correct */ - - /* Check validity of the CSW Signature and CSWStatus */ - if(USBH_MSC_CSWData.field.CSWSignature == USBH_MSC_BOT_CSW_SIGNATURE) - {/* Check Condition 1. dCSWSignature is equal to 53425355h */ - - if(USBH_MSC_CSWData.field.CSWTag == USBH_MSC_CBWData.field.CBWTag) - { - /* Check Condition 3. dCSWTag matches the dCBWTag from the - corresponding CBW */ - - if(USBH_MSC_CSWData.field.CSWStatus == USBH_MSC_OK) - { - /* Refer to USB Mass-Storage Class : BOT (www.usb.org) - - Hn Host expects no data transfers - Hi Host expects to receive data from the device - Ho Host expects to send data to the device - - Dn Device intends to transfer no data - Di Device intends to send data to the host - Do Device intends to receive data from the host - - Section 6.7 - (1) Hn = Dn (Host expects no data transfers, - Device intends to transfer no data) - (6) Hi = Di (Host expects to receive data from the device, - Device intends to send data to the host) - (12) Ho = Do (Host expects to send data to the device, - Device intends to receive data from the host) - - */ - - status = USBH_MSC_OK; - } - else if(USBH_MSC_CSWData.field.CSWStatus == USBH_MSC_FAIL) - { - status = USBH_MSC_FAIL; - } - - else if(USBH_MSC_CSWData.field.CSWStatus == USBH_MSC_PHASE_ERROR) - { - /* Refer to USB Mass-Storage Class : BOT (www.usb.org) - Section 6.7 - (2) Hn < Di ( Host expects no data transfers, - Device intends to send data to the host) - (3) Hn < Do ( Host expects no data transfers, - Device intends to receive data from the host) - (7) Hi < Di ( Host expects to receive data from the device, - Device intends to send data to the host) - (8) Hi <> Do ( Host expects to receive data from the device, - Device intends to receive data from the host) - (10) Ho <> Di (Host expects to send data to the device, - Di Device intends to send data to the host) - (13) Ho < Do (Host expects to send data to the device, - Device intends to receive data from the host) - */ - - status = USBH_MSC_PHASE_ERROR; - } - } /* CSW Tag Matching is Checked */ - } /* CSW Signature Correct Checking */ - else - { - /* If the CSW Signature is not valid, We sall return the Phase Error to - Upper Layers for Reset Recovery */ - - status = USBH_MSC_PHASE_ERROR; - } - } /* CSW Length Check*/ - } - - USBH_MSC_BOTXferParam.BOTXferStatus = status; - return status; -} - - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/src/usbh_msc_core.c b/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/src/usbh_msc_core.c deleted file mode 100644 index 466399e90..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/src/usbh_msc_core.c +++ /dev/null @@ -1,559 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_msc_core.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief This file implements the MSC class driver functions - * =================================================================== - * MSC Class Description - * =================================================================== - * This module manages the MSC class V1.0 following the "Universal - * Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0 - * Sep. 31, 1999". - * This driver implements the following aspects of the specification: - * - Bulk-Only Transport protocol - * - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3)) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

-*/ - -/* Includes ------------------------------------------------------------------*/ - -#include "usbh_msc_core.h" -#include "usbh_msc_scsi.h" -#include "usbh_msc_bot.h" -#include "usbh_core.h" - - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_CLASS - * @{ - */ - -/** @addtogroup USBH_MSC_CLASS - * @{ - */ - -/** @defgroup USBH_MSC_CORE - * @brief This file includes the mass storage related functions - * @{ - */ - - -/** @defgroup USBH_MSC_CORE_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_MSC_CORE_Private_Defines - * @{ - */ -#define USBH_MSC_ERROR_RETRY_LIMIT 10 -/** - * @} - */ - -/** @defgroup USBH_MSC_CORE_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_MSC_CORE_Private_Variables - * @{ - */ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN MSC_Machine_TypeDef MSC_Machine __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN USB_Setup_TypeDef MSC_Setup __ALIGN_END ; -uint8_t MSCErrorCount = 0; - - -/** - * @} - */ - - -/** @defgroup USBH_MSC_CORE_Private_FunctionPrototypes - * @{ - */ - -static USBH_Status USBH_MSC_InterfaceInit (USB_OTG_CORE_HANDLE *pdev , - void *phost); - -static void USBH_MSC_InterfaceDeInit (USB_OTG_CORE_HANDLE *pdev , - void *phost); - -static USBH_Status USBH_MSC_Handle(USB_OTG_CORE_HANDLE *pdev , - void *phost); - -static USBH_Status USBH_MSC_ClassRequest(USB_OTG_CORE_HANDLE *pdev , - void *phost); - -static USBH_Status USBH_MSC_BOTReset(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost); -static USBH_Status USBH_MSC_GETMaxLUN(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost); - - -USBH_Class_cb_TypeDef USBH_MSC_cb = -{ - USBH_MSC_InterfaceInit, - USBH_MSC_InterfaceDeInit, - USBH_MSC_ClassRequest, - USBH_MSC_Handle, -}; - -void USBH_MSC_ErrorHandle(uint8_t status); - -/** - * @} - */ - - -/** @defgroup USBH_MSC_CORE_Exported_Variables - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBH_MSC_CORE_Private_Functions - * @{ - */ - - -/** - * @brief USBH_MSC_InterfaceInit - * Interface initialization for MSC class. - * @param pdev: Selected device - * @param hdev: Selected device property - * @retval USBH_Status : Status of class request handled. - */ -static USBH_Status USBH_MSC_InterfaceInit ( USB_OTG_CORE_HANDLE *pdev, - void *phost) -{ - USBH_HOST *pphost = phost; - - if((pphost->device_prop.Itf_Desc[0].bInterfaceClass == MSC_CLASS) && \ - (pphost->device_prop.Itf_Desc[0].bInterfaceProtocol == MSC_PROTOCOL)) - { - if(pphost->device_prop.Ep_Desc[0][0].bEndpointAddress & 0x80) - { - MSC_Machine.MSBulkInEp = (pphost->device_prop.Ep_Desc[0][0].bEndpointAddress); - MSC_Machine.MSBulkInEpSize = pphost->device_prop.Ep_Desc[0][0].wMaxPacketSize; - } - else - { - MSC_Machine.MSBulkOutEp = (pphost->device_prop.Ep_Desc[0][0].bEndpointAddress); - MSC_Machine.MSBulkOutEpSize = pphost->device_prop.Ep_Desc[0] [0].wMaxPacketSize; - } - - if(pphost->device_prop.Ep_Desc[0][1].bEndpointAddress & 0x80) - { - MSC_Machine.MSBulkInEp = (pphost->device_prop.Ep_Desc[0][1].bEndpointAddress); - MSC_Machine.MSBulkInEpSize = pphost->device_prop.Ep_Desc[0][1].wMaxPacketSize; - } - else - { - MSC_Machine.MSBulkOutEp = (pphost->device_prop.Ep_Desc[0][1].bEndpointAddress); - MSC_Machine.MSBulkOutEpSize = pphost->device_prop.Ep_Desc[0][1].wMaxPacketSize; - } - - MSC_Machine.hc_num_out = USBH_Alloc_Channel(pdev, - MSC_Machine.MSBulkOutEp); - MSC_Machine.hc_num_in = USBH_Alloc_Channel(pdev, - MSC_Machine.MSBulkInEp); - - /* Open the new channels */ - USBH_Open_Channel (pdev, - MSC_Machine.hc_num_out, - pphost->device_prop.address, - pphost->device_prop.speed, - EP_TYPE_BULK, - MSC_Machine.MSBulkOutEpSize); - - USBH_Open_Channel (pdev, - MSC_Machine.hc_num_in, - pphost->device_prop.address, - pphost->device_prop.speed, - EP_TYPE_BULK, - MSC_Machine.MSBulkInEpSize); - - } - - else - { - pphost->usr_cb->USBH_USR_DeviceNotSupported(); - } - - return USBH_OK ; - -} - - -/** - * @brief USBH_MSC_InterfaceDeInit - * De-Initialize interface by freeing host channels allocated to interface - * @param pdev: Selected device - * @param hdev: Selected device property - * @retval None - */ -void USBH_MSC_InterfaceDeInit ( USB_OTG_CORE_HANDLE *pdev, - void *phost) -{ - if ( MSC_Machine.hc_num_out) - { - USB_OTG_HC_Halt(pdev, MSC_Machine.hc_num_out); - USBH_Free_Channel (pdev, MSC_Machine.hc_num_out); - MSC_Machine.hc_num_out = 0; /* Reset the Channel as Free */ - } - - if ( MSC_Machine.hc_num_in) - { - USB_OTG_HC_Halt(pdev, MSC_Machine.hc_num_in); - USBH_Free_Channel (pdev, MSC_Machine.hc_num_in); - MSC_Machine.hc_num_in = 0; /* Reset the Channel as Free */ - } -} - -/** - * @brief USBH_MSC_ClassRequest - * This function will only initialize the MSC state machine - * @param pdev: Selected device - * @param hdev: Selected device property - * @retval USBH_Status : Status of class request handled. - */ - -static USBH_Status USBH_MSC_ClassRequest(USB_OTG_CORE_HANDLE *pdev , - void *phost) -{ - - USBH_Status status = USBH_OK ; - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_INIT_STATE; - - return status; -} - - -/** - * @brief USBH_MSC_Handle - * MSC state machine handler - * @param pdev: Selected device - * @param hdev: Selected device property - * @retval USBH_Status - */ - -static USBH_Status USBH_MSC_Handle(USB_OTG_CORE_HANDLE *pdev , - void *phost) -{ - USBH_HOST *pphost = phost; - - USBH_Status status = USBH_BUSY; - uint8_t mscStatus = USBH_MSC_BUSY; - uint8_t appliStatus = 0; - - static uint8_t maxLunExceed = FALSE; - - - if(HCD_IsDeviceConnected(pdev)) - { - switch(USBH_MSC_BOTXferParam.MSCState) - { - case USBH_MSC_BOT_INIT_STATE: - USBH_MSC_Init(pdev); - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_RESET; - break; - - case USBH_MSC_BOT_RESET: - /* Issue BOT RESET request */ - status = USBH_MSC_BOTReset(pdev, phost); - if(status == USBH_OK ) - { - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_GET_MAX_LUN; - } - - if(status == USBH_NOT_SUPPORTED ) - { - /* If the Command has failed, then we need to move to Next State, after - STALL condition is cleared by Control-Transfer */ - USBH_MSC_BOTXferParam.MSCStateBkp = USBH_MSC_GET_MAX_LUN; - - /* a Clear Feature should be issued here */ - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_CTRL_ERROR_STATE; - } - break; - - case USBH_MSC_GET_MAX_LUN: - /* Issue GetMaxLUN request */ - status = USBH_MSC_GETMaxLUN(pdev, phost); - - if(status == USBH_OK ) - { - MSC_Machine.maxLun = *(MSC_Machine.buff) ; - - /* If device has more that one logical unit then it is not supported */ - if((MSC_Machine.maxLun > 0) && (maxLunExceed == FALSE)) - { - maxLunExceed = TRUE; - pphost->usr_cb->USBH_USR_DeviceNotSupported(); - - break; - } - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_TEST_UNIT_READY; - } - - if(status == USBH_NOT_SUPPORTED ) - { - /* If the Command has failed, then we need to move to Next State, after - STALL condition is cleared by Control-Transfer */ - USBH_MSC_BOTXferParam.MSCStateBkp = USBH_MSC_TEST_UNIT_READY; - - /* a Clear Feature should be issued here */ - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_CTRL_ERROR_STATE; - } - break; - - case USBH_MSC_CTRL_ERROR_STATE: - /* Issue Clearfeature request */ - status = USBH_ClrFeature(pdev, - phost, - 0x00, - pphost->Control.hc_num_out); - if(status == USBH_OK ) - { - /* If GetMaxLun Request not support, assume Single LUN configuration */ - MSC_Machine.maxLun = 0; - - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateBkp; - } - break; - - case USBH_MSC_TEST_UNIT_READY: - /* Issue SCSI command TestUnitReady */ - mscStatus = USBH_MSC_TestUnitReady(pdev); - - if(mscStatus == USBH_MSC_OK ) - { - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_READ_CAPACITY10; - MSCErrorCount = 0; - status = USBH_OK; - } - else - { - USBH_MSC_ErrorHandle(mscStatus); - } - break; - - case USBH_MSC_READ_CAPACITY10: - /* Issue READ_CAPACITY10 SCSI command */ - mscStatus = USBH_MSC_ReadCapacity10(pdev); - if(mscStatus == USBH_MSC_OK ) - { - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_MODE_SENSE6; - MSCErrorCount = 0; - status = USBH_OK; - } - else - { - USBH_MSC_ErrorHandle(mscStatus); - } - break; - - case USBH_MSC_MODE_SENSE6: - /* Issue ModeSense6 SCSI command for detecting if device is write-protected */ - mscStatus = USBH_MSC_ModeSense6(pdev); - if(mscStatus == USBH_MSC_OK ) - { - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_DEFAULT_APPLI_STATE; - MSCErrorCount = 0; - status = USBH_OK; - } - else - { - USBH_MSC_ErrorHandle(mscStatus); - } - break; - - case USBH_MSC_REQUEST_SENSE: - /* Issue RequestSense SCSI command for retreiving error code */ - mscStatus = USBH_MSC_RequestSense(pdev); - if(mscStatus == USBH_MSC_OK ) - { - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOTXferParam.MSCStateBkp; - status = USBH_OK; - } - else - { - USBH_MSC_ErrorHandle(mscStatus); - } - break; - - case USBH_MSC_BOT_USB_TRANSFERS: - /* Process the BOT state machine */ - USBH_MSC_HandleBOTXfer(pdev , phost); - break; - - case USBH_MSC_DEFAULT_APPLI_STATE: - /* Process Application callback for MSC */ - appliStatus = pphost->usr_cb->USBH_USR_MSC_Application(); - if(appliStatus == 0) - { - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_DEFAULT_APPLI_STATE; - } - else if (appliStatus == 1) - { - /* De-init requested from application layer */ - status = USBH_APPLY_DEINIT; - } - break; - - case USBH_MSC_UNRECOVERED_STATE: - - status = USBH_UNRECOVERED_ERROR; - - break; - - default: - break; - - } - } - return status; -} - - - -/** - * @brief USBH_MSC_BOTReset - * This request is used to reset the mass storage device and its - * associated interface. This class-specific request shall ready the - * device for the next CBW from the host. - * @param pdev: Selected device - * @retval USBH_Status : Status of class request handled. - */ -static USBH_Status USBH_MSC_BOTReset(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost) -{ - - phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_TYPE_CLASS | \ - USB_REQ_RECIPIENT_INTERFACE; - - phost->Control.setup.b.bRequest = USB_REQ_BOT_RESET; - phost->Control.setup.b.wValue.w = 0; - phost->Control.setup.b.wIndex.w = 0; - phost->Control.setup.b.wLength.w = 0; - - return USBH_CtlReq(pdev, phost, 0 , 0 ); -} - - -/** - * @brief USBH_MSC_GETMaxLUN - * This request is used to reset the mass storage device and its - * associated interface. This class-specific request shall ready the - * device for the next CBW from the host. - * @param pdev: Selected device - * @retval USBH_Status : USB ctl xfer status - */ -static USBH_Status USBH_MSC_GETMaxLUN(USB_OTG_CORE_HANDLE *pdev , USBH_HOST *phost) -{ - phost->Control.setup.b.bmRequestType = USB_D2H | USB_REQ_TYPE_CLASS | \ - USB_REQ_RECIPIENT_INTERFACE; - - phost->Control.setup.b.bRequest = USB_REQ_GET_MAX_LUN; - phost->Control.setup.b.wValue.w = 0; - phost->Control.setup.b.wIndex.w = 0; - phost->Control.setup.b.wLength.w = 1; - - return USBH_CtlReq(pdev, phost, MSC_Machine.buff , 1 ); -} - -/** - * @brief USBH_MSC_ErrorHandle - * The function is for handling errors occuring during the MSC - * state machine - * @param status - * @retval None - */ - -void USBH_MSC_ErrorHandle(uint8_t status) -{ - if(status == USBH_MSC_FAIL) - { - MSCErrorCount++; - if(MSCErrorCount < USBH_MSC_ERROR_RETRY_LIMIT) - { /* Try MSC level error recovery, Issue the request Sense to get - Drive error reason */ - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_REQUEST_SENSE; - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - } - else - { - /* Error trials exceeded the limit, go to unrecovered state */ - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_UNRECOVERED_STATE; - } - } - else if(status == USBH_MSC_PHASE_ERROR) - { - /* Phase error, Go to Unrecoovered state */ - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_UNRECOVERED_STATE; - } - else if(status == USBH_MSC_BUSY) - { - /*No change in state*/ - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/src/usbh_msc_fatfs.c b/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/src/usbh_msc_fatfs.c deleted file mode 100644 index 57a3c9c0f..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/src/usbh_msc_fatfs.c +++ /dev/null @@ -1,186 +0,0 @@ - -#include "usb_conf.h" -#include "diskio.h" -#include "usbh_msc_core.h" -/*-------------------------------------------------------------------------- - -Module Private Functions and Variables - ----------------------------------------------------------------------------*/ - -static volatile DSTATUS Stat = STA_NOINIT; /* Disk status */ - -extern USB_OTG_CORE_HANDLE USB_OTG_Core; -extern USBH_HOST USB_Host; - -/*-----------------------------------------------------------------------*/ -/* Initialize Disk Drive */ -/*-----------------------------------------------------------------------*/ - -DSTATUS disk_initialize ( - BYTE drv /* Physical drive number (0) */ - ) -{ - - if(HCD_IsDeviceConnected(&USB_OTG_Core)) - { - Stat &= ~STA_NOINIT; - } - - return Stat; - - -} - - - -/*-----------------------------------------------------------------------*/ -/* Get Disk Status */ -/*-----------------------------------------------------------------------*/ - -DSTATUS disk_status ( - BYTE drv /* Physical drive number (0) */ - ) -{ - if (drv) return STA_NOINIT; /* Supports only single drive */ - return Stat; -} - - - -/*-----------------------------------------------------------------------*/ -/* Read Sector(s) */ -/*-----------------------------------------------------------------------*/ - -DRESULT disk_read ( - BYTE drv, /* Physical drive number (0) */ - BYTE *buff, /* Pointer to the data buffer to store read data */ - DWORD sector, /* Start sector number (LBA) */ - BYTE count /* Sector count (1..255) */ - ) -{ - BYTE status = USBH_MSC_OK; - - if (drv || !count) return RES_PARERR; - if (Stat & STA_NOINIT) return RES_NOTRDY; - - - if(HCD_IsDeviceConnected(&USB_OTG_Core)) - { - - do - { - status = USBH_MSC_Read10(&USB_OTG_Core, buff,sector,512); - USBH_MSC_HandleBOTXfer(&USB_OTG_Core ,&USB_Host); - - if(!HCD_IsDeviceConnected(&USB_OTG_Core)) - { - return RES_ERROR; - } - } - while(status == USBH_MSC_BUSY ); - } - - if(status == USBH_MSC_OK) - return RES_OK; - return RES_ERROR; - -} - - - -/*-----------------------------------------------------------------------*/ -/* Write Sector(s) */ -/*-----------------------------------------------------------------------*/ - -#if _READONLY == 0 -DRESULT disk_write ( - BYTE drv, /* Physical drive number (0) */ - const BYTE *buff, /* Pointer to the data to be written */ - DWORD sector, /* Start sector number (LBA) */ - BYTE count /* Sector count (1..255) */ - ) -{ - BYTE status = USBH_MSC_OK; - if (drv || !count) return RES_PARERR; - if (Stat & STA_NOINIT) return RES_NOTRDY; - if (Stat & STA_PROTECT) return RES_WRPRT; - - - if(HCD_IsDeviceConnected(&USB_OTG_Core)) - { - do - { - status = USBH_MSC_Write10(&USB_OTG_Core,(BYTE*)buff,sector,512); - USBH_MSC_HandleBOTXfer(&USB_OTG_Core, &USB_Host); - - if(!HCD_IsDeviceConnected(&USB_OTG_Core)) - { - return RES_ERROR; - } - } - - while(status == USBH_MSC_BUSY ); - - } - - if(status == USBH_MSC_OK) - return RES_OK; - return RES_ERROR; -} -#endif /* _READONLY == 0 */ - - - -/*-----------------------------------------------------------------------*/ -/* Miscellaneous Functions */ -/*-----------------------------------------------------------------------*/ - -#if _USE_IOCTL != 0 -DRESULT disk_ioctl ( - BYTE drv, /* Physical drive number (0) */ - BYTE ctrl, /* Control code */ - void *buff /* Buffer to send/receive control data */ - ) -{ - DRESULT res = RES_OK; - - if (drv) return RES_PARERR; - - res = RES_ERROR; - - if (Stat & STA_NOINIT) return RES_NOTRDY; - - switch (ctrl) { - case CTRL_SYNC : /* Make sure that no pending write process */ - - res = RES_OK; - break; - - case GET_SECTOR_COUNT : /* Get number of sectors on the disk (DWORD) */ - - *(DWORD*)buff = (DWORD) USBH_MSC_Param.MSCapacity; - res = RES_OK; - break; - - case GET_SECTOR_SIZE : /* Get R/W sector size (WORD) */ - *(WORD*)buff = 512; - res = RES_OK; - break; - - case GET_BLOCK_SIZE : /* Get erase block size in unit of sector (DWORD) */ - - *(DWORD*)buff = 512; - - break; - - - default: - res = RES_PARERR; - } - - - - return res; -} -#endif /* _USE_IOCTL != 0 */ diff --git a/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/src/usbh_msc_scsi.c b/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/src/usbh_msc_scsi.c deleted file mode 100644 index f6bb7c4c2..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Class/MSC/src/usbh_msc_scsi.c +++ /dev/null @@ -1,674 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_msc_scsi.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief This file implements the SCSI commands - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_msc_core.h" -#include "usbh_msc_scsi.h" -#include "usbh_msc_bot.h" -#include "usbh_ioreq.h" -#include "usbh_def.h" - - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_CLASS - * @{ - */ - -/** @addtogroup USBH_MSC_CLASS - * @{ - */ - -/** @defgroup USBH_MSC_SCSI - * @brief This file includes the mass storage related functions - * @{ - */ - - -/** @defgroup USBH_MSC_SCSI_Private_TypesDefinitions - * @{ - */ - -MassStorageParameter_TypeDef USBH_MSC_Param; -/** - * @} - */ - -/** @defgroup USBH_MSC_SCSI_Private_Defines - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_MSC_SCSI_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_MSC_SCSI_Private_Variables - * @{ - */ - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t USBH_DataInBuffer[512] __ALIGN_END ; - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma data_alignment=4 - #endif -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ -__ALIGN_BEGIN uint8_t USBH_DataOutBuffer[512] __ALIGN_END ; -/** - * @} - */ - - -/** @defgroup USBH_MSC_SCSI_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_MSC_SCSI_Exported_Variables - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBH_MSC_SCSI_Private_Functions - * @{ - */ - - - - -/** - * @brief USBH_MSC_TestUnitReady - * Issues 'Test unit ready' command to the device. Once the response - * received, it updates the status to upper layer. - * @param None - * @retval Status - */ -uint8_t USBH_MSC_TestUnitReady (USB_OTG_CORE_HANDLE *pdev) -{ - uint8_t index; - USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY; - - if(HCD_IsDeviceConnected(pdev)) - { - switch(USBH_MSC_BOTXferParam.CmdStateMachine) - { - case CMD_SEND_STATE: - /*Prepare the CBW and relevent field*/ - USBH_MSC_CBWData.field.CBWTransferLength = 0; /* No Data Transfer */ - USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_OUT; - USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH_TEST_UNIT_READY; - USBH_MSC_BOTXferParam.pRxTxBuff = USBH_MSC_CSWData.CSWArray; - USBH_MSC_BOTXferParam.DataLength = USBH_MSC_CSW_MAX_LENGTH; - USBH_MSC_BOTXferParam.MSCStateCurrent = USBH_MSC_TEST_UNIT_READY; - - for(index = CBW_CB_LENGTH; index != 0; index--) - { - USBH_MSC_CBWData.field.CBWCB[index] = 0x00; - } - - USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_TEST_UNIT_READY; - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW; - /* Start the transfer, then let the state - machine magage the other transactions */ - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS; - USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY; - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS; - - status = USBH_MSC_BUSY; - break; - - case CMD_WAIT_STATUS: - if(USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK) - { - /* Commands successfully sent and Response Received */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - - status = USBH_MSC_OK; - } - else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL ) - { - /* Failure Mode */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - status = USBH_MSC_FAIL; - } - - else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR ) - { - /* Failure Mode */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - status = USBH_MSC_PHASE_ERROR; - } - break; - - default: - break; - } - } - return status; -} - - -/** - * @brief USBH_MSC_ReadCapacity10 - * Issue the read capacity command to the device. Once the response - * received, it updates the status to upper layer - * @param None - * @retval Status - */ -uint8_t USBH_MSC_ReadCapacity10(USB_OTG_CORE_HANDLE *pdev) -{ - uint8_t index; - USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY; - - if(HCD_IsDeviceConnected(pdev)) - { - switch(USBH_MSC_BOTXferParam.CmdStateMachine) - { - case CMD_SEND_STATE: - /*Prepare the CBW and relevent field*/ - USBH_MSC_CBWData.field.CBWTransferLength = XFER_LEN_READ_CAPACITY10; - USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; - USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; - - USBH_MSC_BOTXferParam.pRxTxBuff = USBH_DataInBuffer; - USBH_MSC_BOTXferParam.MSCStateCurrent = USBH_MSC_READ_CAPACITY10; - - for(index = CBW_CB_LENGTH; index != 0; index--) - { - USBH_MSC_CBWData.field.CBWCB[index] = 0x00; - } - - USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_READ_CAPACITY10; - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW; - - /* Start the transfer, then let the state machine manage the other - transactions */ - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS; - USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY; - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS; - - status = USBH_MSC_BUSY; - break; - - case CMD_WAIT_STATUS: - if(USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK) - { - /*assign the capacity*/ - (((uint8_t*)&USBH_MSC_Param.MSCapacity )[3]) = USBH_DataInBuffer[0]; - (((uint8_t*)&USBH_MSC_Param.MSCapacity )[2]) = USBH_DataInBuffer[1]; - (((uint8_t*)&USBH_MSC_Param.MSCapacity )[1]) = USBH_DataInBuffer[2]; - (((uint8_t*)&USBH_MSC_Param.MSCapacity )[0]) = USBH_DataInBuffer[3]; - - /*assign the page length*/ - (((uint8_t*)&USBH_MSC_Param.MSPageLength )[1]) = USBH_DataInBuffer[6]; - (((uint8_t*)&USBH_MSC_Param.MSPageLength )[0]) = USBH_DataInBuffer[7]; - - /* Commands successfully sent and Response Received */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - status = USBH_MSC_OK; - } - else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL ) - { - /* Failure Mode */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - status = USBH_MSC_FAIL; - } - else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR ) - { - /* Failure Mode */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - status = USBH_MSC_PHASE_ERROR; - } - else - { - /* Wait for the Commands to get Completed */ - /* NO Change in state Machine */ - } - break; - - default: - break; - } - } - return status; -} - - -/** - * @brief USBH_MSC_ModeSense6 - * Issue the Mode Sense6 Command to the device. This function is used - * for reading the WriteProtect Status of the Mass-Storage device. - * @param None - * @retval Status - */ -uint8_t USBH_MSC_ModeSense6(USB_OTG_CORE_HANDLE *pdev) -{ - uint8_t index; - USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY; - - if(HCD_IsDeviceConnected(pdev)) - { - switch(USBH_MSC_BOTXferParam.CmdStateMachine) - { - case CMD_SEND_STATE: - /*Prepare the CBW and relevent field*/ - USBH_MSC_CBWData.field.CBWTransferLength = XFER_LEN_MODE_SENSE6; - USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; - USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; - - USBH_MSC_BOTXferParam.pRxTxBuff = USBH_DataInBuffer; - USBH_MSC_BOTXferParam.MSCStateCurrent = USBH_MSC_MODE_SENSE6; - - for(index = CBW_CB_LENGTH; index != 0; index--) - { - USBH_MSC_CBWData.field.CBWCB[index] = 0x00; - } - - USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_MODE_SENSE6; - USBH_MSC_CBWData.field.CBWCB[2] = MODE_SENSE_PAGE_CONTROL_FIELD | \ - MODE_SENSE_PAGE_CODE; - - USBH_MSC_CBWData.field.CBWCB[4] = XFER_LEN_MODE_SENSE6; - - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW; - - /* Start the transfer, then let the state machine manage the other - transactions */ - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS; - USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY; - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS; - - status = USBH_MSC_BUSY; - break; - - case CMD_WAIT_STATUS: - if(USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK) - { - /* Assign the Write Protect status */ - /* If WriteProtect = 0, Writing is allowed - If WriteProtect != 0, Disk is Write Protected */ - if ( USBH_DataInBuffer[2] & MASK_MODE_SENSE_WRITE_PROTECT) - { - USBH_MSC_Param.MSWriteProtect = DISK_WRITE_PROTECTED; - } - else - { - USBH_MSC_Param.MSWriteProtect = 0; - } - - /* Commands successfully sent and Response Received */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - status = USBH_MSC_OK; - } - else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL ) - { - /* Failure Mode */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - status = USBH_MSC_FAIL; - } - else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR ) - { - /* Failure Mode */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - status = USBH_MSC_PHASE_ERROR; - } - else - { - /* Wait for the Commands to get Completed */ - /* NO Change in state Machine */ - } - break; - - default: - break; - } - } - return status; -} - -/** - * @brief USBH_MSC_RequestSense - * Issues the Request Sense command to the device. Once the response - * received, it updates the status to upper layer - * @param None - * @retval Status - */ -uint8_t USBH_MSC_RequestSense(USB_OTG_CORE_HANDLE *pdev) -{ - USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY; - - uint8_t index; - - - if(HCD_IsDeviceConnected(pdev)) - { - switch(USBH_MSC_BOTXferParam.CmdStateMachine) - { - case CMD_SEND_STATE: - - /*Prepare the CBW and relevent field*/ - USBH_MSC_CBWData.field.CBWTransferLength = \ - ALLOCATION_LENGTH_REQUEST_SENSE; - USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; - USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; - - USBH_MSC_BOTXferParam.pRxTxBuff = USBH_DataInBuffer; - USBH_MSC_BOTXferParam.MSCStateBkp = USBH_MSC_BOTXferParam.MSCStateCurrent; - USBH_MSC_BOTXferParam.MSCStateCurrent = USBH_MSC_REQUEST_SENSE; - - - for(index = CBW_CB_LENGTH; index != 0; index--) - { - USBH_MSC_CBWData.field.CBWCB[index] = 0x00; - } - - USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_REQUEST_SENSE; - USBH_MSC_CBWData.field.CBWCB[1] = DESC_REQUEST_SENSE; - USBH_MSC_CBWData.field.CBWCB[4] = ALLOCATION_LENGTH_REQUEST_SENSE; - - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW; - /* Start the transfer, then let the state machine magage - the other transactions */ - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS; - USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY; - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS; - - status = USBH_MSC_BUSY; - - break; - - case CMD_WAIT_STATUS: - - if(USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK) - { - /* Get Sense data*/ - (((uint8_t*)&USBH_MSC_Param.MSSenseKey )[3]) = USBH_DataInBuffer[0]; - (((uint8_t*)&USBH_MSC_Param.MSSenseKey )[2]) = USBH_DataInBuffer[1]; - (((uint8_t*)&USBH_MSC_Param.MSSenseKey )[1]) = USBH_DataInBuffer[2]; - (((uint8_t*)&USBH_MSC_Param.MSSenseKey )[0]) = USBH_DataInBuffer[3]; - - /* Commands successfully sent and Response Received */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - status = USBH_MSC_OK; - } - else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL ) - { - /* Failure Mode */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - status = USBH_MSC_FAIL; - } - - else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR ) - { - /* Failure Mode */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - status = USBH_MSC_PHASE_ERROR; - } - - else - { - /* Wait for the Commands to get Completed */ - /* NO Change in state Machine */ - } - break; - - default: - break; - } - } - return status; -} - - -/** - * @brief USBH_MSC_Write10 - * Issue the write command to the device. Once the response received, - * it updates the status to upper layer - * @param dataBuffer : DataBuffer contains the data to write - * @param address : Address to which the data will be written - * @param nbOfbytes : NbOfbytes to be written - * @retval Status - */ -uint8_t USBH_MSC_Write10(USB_OTG_CORE_HANDLE *pdev, - uint8_t *dataBuffer, - uint32_t address, - uint32_t nbOfbytes) -{ - uint8_t index; - USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY; - uint16_t nbOfPages; - - if(HCD_IsDeviceConnected(pdev)) - { - switch(USBH_MSC_BOTXferParam.CmdStateMachine) - { - case CMD_SEND_STATE: - USBH_MSC_CBWData.field.CBWTransferLength = nbOfbytes; - USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_OUT; - USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; - USBH_MSC_BOTXferParam.pRxTxBuff = dataBuffer; - - - for(index = CBW_CB_LENGTH; index != 0; index--) - { - USBH_MSC_CBWData.field.CBWCB[index] = 0x00; - } - - USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_WRITE10; - - /*logical block address*/ - USBH_MSC_CBWData.field.CBWCB[2] = (((uint8_t*)&address)[3]) ; - USBH_MSC_CBWData.field.CBWCB[3] = (((uint8_t*)&address)[2]); - USBH_MSC_CBWData.field.CBWCB[4] = (((uint8_t*)&address)[1]); - USBH_MSC_CBWData.field.CBWCB[5] = (((uint8_t*)&address)[0]); - - /*USBH_MSC_PAGE_LENGTH = 512*/ - nbOfPages = nbOfbytes/ USBH_MSC_PAGE_LENGTH; - - /*Tranfer length */ - USBH_MSC_CBWData.field.CBWCB[7] = (((uint8_t *)&nbOfPages)[1]) ; - USBH_MSC_CBWData.field.CBWCB[8] = (((uint8_t *)&nbOfPages)[0]) ; - - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW; - /* Start the transfer, then let the state machine - magage the other transactions */ - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS; - USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY; - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS; - - status = USBH_MSC_BUSY; - - break; - - case CMD_WAIT_STATUS: - if(USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK) - { - /* Commands successfully sent and Response Received */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - status = USBH_MSC_OK; - } - else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL ) - { - /* Failure Mode */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - } - - else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR ) - { - /* Failure Mode */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - status = USBH_MSC_PHASE_ERROR; - } - break; - - default: - break; - } - } - return status; -} - -/** - * @brief USBH_MSC_Read10 - * Issue the read command to the device. Once the response received, - * it updates the status to upper layer - * @param dataBuffer : DataBuffer will contain the data to be read - * @param address : Address from which the data will be read - * @param nbOfbytes : NbOfbytes to be read - * @retval Status - */ -uint8_t USBH_MSC_Read10(USB_OTG_CORE_HANDLE *pdev, - uint8_t *dataBuffer, - uint32_t address, - uint32_t nbOfbytes) -{ - uint8_t index; - static USBH_MSC_Status_TypeDef status = USBH_MSC_BUSY; - uint16_t nbOfPages; - status = USBH_MSC_BUSY; - - if(HCD_IsDeviceConnected(pdev)) - { - switch(USBH_MSC_BOTXferParam.CmdStateMachine) - { - case CMD_SEND_STATE: - /*Prepare the CBW and relevent field*/ - USBH_MSC_CBWData.field.CBWTransferLength = nbOfbytes; - USBH_MSC_CBWData.field.CBWFlags = USB_EP_DIR_IN; - USBH_MSC_CBWData.field.CBWLength = CBW_LENGTH; - - USBH_MSC_BOTXferParam.pRxTxBuff = dataBuffer; - - for(index = CBW_CB_LENGTH; index != 0; index--) - { - USBH_MSC_CBWData.field.CBWCB[index] = 0x00; - } - - USBH_MSC_CBWData.field.CBWCB[0] = OPCODE_READ10; - - /*logical block address*/ - - USBH_MSC_CBWData.field.CBWCB[2] = (((uint8_t*)&address)[3]); - USBH_MSC_CBWData.field.CBWCB[3] = (((uint8_t*)&address)[2]); - USBH_MSC_CBWData.field.CBWCB[4] = (((uint8_t*)&address)[1]); - USBH_MSC_CBWData.field.CBWCB[5] = (((uint8_t*)&address)[0]); - - /*USBH_MSC_PAGE_LENGTH = 512*/ - nbOfPages = nbOfbytes/ USBH_MSC_PAGE_LENGTH; - - /*Tranfer length */ - USBH_MSC_CBWData.field.CBWCB[7] = (((uint8_t *)&nbOfPages)[1]) ; - USBH_MSC_CBWData.field.CBWCB[8] = (((uint8_t *)&nbOfPages)[0]) ; - - - USBH_MSC_BOTXferParam.BOTState = USBH_MSC_SEND_CBW; - /* Start the transfer, then let the state machine - magage the other transactions */ - USBH_MSC_BOTXferParam.MSCState = USBH_MSC_BOT_USB_TRANSFERS; - USBH_MSC_BOTXferParam.BOTXferStatus = USBH_MSC_BUSY; - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_WAIT_STATUS; - - status = USBH_MSC_BUSY; - - break; - - case CMD_WAIT_STATUS: - - if((USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_OK) && \ - (HCD_IsDeviceConnected(pdev))) - { - /* Commands successfully sent and Response Received */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - status = USBH_MSC_OK; - } - else if (( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_FAIL ) && \ - (HCD_IsDeviceConnected(pdev))) - { - /* Failure Mode */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - } - - else if ( USBH_MSC_BOTXferParam.BOTXferStatus == USBH_MSC_PHASE_ERROR ) - { - /* Failure Mode */ - USBH_MSC_BOTXferParam.CmdStateMachine = CMD_SEND_STATE; - status = USBH_MSC_PHASE_ERROR; - } - else - { - /* Wait for the Commands to get Completed */ - /* NO Change in state Machine */ - } - break; - - default: - break; - } - } - return status; -} - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_conf_template.h b/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_conf_template.h deleted file mode 100644 index 7e41bf8cd..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_conf_template.h +++ /dev/null @@ -1,94 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_conf_template - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief General USB Host library configuration - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USBH_CONF__H__ -#define __USBH_CONF__H__ - -/* Includes ------------------------------------------------------------------*/ -/** @addtogroup USBH_OTG_DRIVER - * @{ - */ - -/** @defgroup USBH_CONF - * @brief usb otg low level driver configuration file - * @{ - */ - -/** @defgroup USBH_CONF_Exported_Defines - * @{ - */ - -#define USBH_MAX_NUM_ENDPOINTS 2 -#define USBH_MAX_NUM_INTERFACES 2 -#ifdef USE_USB_OTG_FS -#define USBH_MSC_MPS_SIZE 0x40 -#else -#define USBH_MSC_MPS_SIZE 0x200 -#endif - -/** - * @} - */ - - -/** @defgroup USBH_CONF_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_CONF_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_CONF_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_CONF_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif //__USBH_CONF__H__ - - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_core.h b/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_core.h deleted file mode 100644 index 3a8de2c67..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_core.h +++ /dev/null @@ -1,289 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_core.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Header file for usbh_core.c - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive ----------------------------------------------*/ -#ifndef __USBH_CORE_H -#define __USBH_CORE_H - -/* Includes ------------------------------------------------------------------*/ -#include "usb_hcd.h" -#include "usbh_def.h" -#include "usbh_conf.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_CORE - * @brief This file is the Header file for usbh_core.c - * @{ - */ - - -/** @defgroup USBH_CORE_Exported_Defines - * @{ - */ - -#define MSC_CLASS 0x08 -#define HID_CLASS 0x03 -#define MSC_PROTOCOL 0x50 -#define CBI_PROTOCOL 0x01 - - -#define USBH_MAX_ERROR_COUNT 2 -#define USBH_DEVICE_ADDRESS_DEFAULT 0 -#define USBH_DEVICE_ADDRESS 1 - - -/** - * @} - */ - - -/** @defgroup USBH_CORE_Exported_Types - * @{ - */ - -typedef enum { - USBH_OK = 0, - USBH_BUSY, - USBH_FAIL, - USBH_NOT_SUPPORTED, - USBH_UNRECOVERED_ERROR, - USBH_ERROR_SPEED_UNKNOWN, - USBH_APPLY_DEINIT -}USBH_Status; - -/* Following states are used for gState */ -typedef enum { - HOST_IDLE =0, - HOST_ISSUE_CORE_RESET, - HOST_DEV_ATTACHED, - HOST_DEV_DISCONNECTED, - HOST_ISSUE_RESET, - HOST_DETECT_DEVICE_SPEED, - HOST_ENUMERATION, - HOST_CLASS_REQUEST, - HOST_CLASS, - HOST_CTRL_XFER, - HOST_USR_INPUT, - HOST_SUSPENDED, - HOST_ERROR_STATE -}HOST_State; - -/* Following states are used for EnumerationState */ -typedef enum { - ENUM_IDLE = 0, - ENUM_GET_FULL_DEV_DESC, - ENUM_SET_ADDR, - ENUM_GET_CFG_DESC, - ENUM_GET_FULL_CFG_DESC, - ENUM_GET_MFC_STRING_DESC, - ENUM_GET_PRODUCT_STRING_DESC, - ENUM_GET_SERIALNUM_STRING_DESC, - ENUM_SET_CONFIGURATION, - ENUM_DEV_CONFIGURED -} ENUM_State; - - - -/* Following states are used for CtrlXferStateMachine */ -typedef enum { - CTRL_IDLE =0, - CTRL_SETUP, - CTRL_SETUP_WAIT, - CTRL_DATA_IN, - CTRL_DATA_IN_WAIT, - CTRL_DATA_OUT, - CTRL_DATA_OUT_WAIT, - CTRL_STATUS_IN, - CTRL_STATUS_IN_WAIT, - CTRL_STATUS_OUT, - CTRL_STATUS_OUT_WAIT, - CTRL_ERROR -} -CTRL_State; - -typedef enum { - USBH_USR_NO_RESP = 0, - USBH_USR_RESP_OK = 1, -} -USBH_USR_Status; - -/* Following states are used for RequestState */ -typedef enum { - CMD_IDLE =0, - CMD_SEND, - CMD_WAIT -} CMD_State; - - - -typedef struct _Ctrl -{ - uint8_t hc_num_in; - uint8_t hc_num_out; - uint8_t ep0size; - uint8_t *buff; - uint16_t length; - uint8_t errorcount; - uint16_t timer; - CTRL_STATUS status; - USB_Setup_TypeDef setup; - CTRL_State state; - -} USBH_Ctrl_TypeDef; - - - -typedef struct _DeviceProp -{ - - uint8_t address; - uint8_t speed; - USBH_DevDesc_TypeDef Dev_Desc; - USBH_CfgDesc_TypeDef Cfg_Desc; - USBH_InterfaceDesc_TypeDef Itf_Desc[USBH_MAX_NUM_INTERFACES]; - USBH_EpDesc_TypeDef Ep_Desc[USBH_MAX_NUM_INTERFACES][USBH_MAX_NUM_ENDPOINTS]; - USBH_HIDDesc_TypeDef HID_Desc; - -}USBH_Device_TypeDef; - -typedef struct _USBH_Class_cb -{ - USBH_Status (*Init)\ - (USB_OTG_CORE_HANDLE *pdev , void *phost); - void (*DeInit)\ - (USB_OTG_CORE_HANDLE *pdev , void *phost); - USBH_Status (*Requests)\ - (USB_OTG_CORE_HANDLE *pdev , void *phost); - USBH_Status (*Machine)\ - (USB_OTG_CORE_HANDLE *pdev , void *phost); - -} USBH_Class_cb_TypeDef; - - -typedef struct _USBH_USR_PROP -{ - void (*Init)(void); /* HostLibInitialized */ - void (*DeInit)(void); /* HostLibInitialized */ - void (*DeviceAttached)(void); /* DeviceAttached */ - void (*ResetDevice)(void); - void (*DeviceDisconnected)(void); - void (*OverCurrentDetected)(void); - void (*DeviceSpeedDetected)(uint8_t DeviceSpeed); /* DeviceSpeed */ - void (*DeviceDescAvailable)(void *); /* DeviceDescriptor is available */ - void (*DeviceAddressAssigned)(void); /* Address is assigned to USB Device */ - void (*ConfigurationDescAvailable)(USBH_CfgDesc_TypeDef *, - USBH_InterfaceDesc_TypeDef *, - USBH_EpDesc_TypeDef *); - /* Configuration Descriptor available */ - void (*ManufacturerString)(void *); /* ManufacturerString*/ - void (*ProductString)(void *); /* ProductString*/ - void (*SerialNumString)(void *); /* SerialNubString*/ - void (*EnumerationDone)(void); /* Enumeration finished */ - USBH_USR_Status (*UserInput)(void); - int (*USBH_USR_MSC_Application) (void); - void (*USBH_USR_DeviceNotSupported)(void); /* Device is not supported*/ - void (*UnrecoveredError)(void); - -} -USBH_Usr_cb_TypeDef; - -typedef struct _Host_TypeDef -{ - HOST_State gState; /* Host State Machine Value */ - HOST_State gStateBkp; /* backup of previous State machine value */ - ENUM_State EnumState; /* Enumeration state Machine */ - CMD_State RequestState; - USBH_Ctrl_TypeDef Control; - - USBH_Device_TypeDef device_prop; - - USBH_Class_cb_TypeDef *class_cb; - USBH_Usr_cb_TypeDef *usr_cb; - - -} USBH_HOST, *pUSBH_HOST; - -/** - * @} - */ - - - -/** @defgroup USBH_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBH_CORE_Exported_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBH_CORE_Exported_FunctionsPrototype - * @{ - */ -void USBH_Init(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID, - USBH_HOST *phost, - USBH_Class_cb_TypeDef *class_cb, - USBH_Usr_cb_TypeDef *usr_cb); - -USBH_Status USBH_DeInit(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost); -void USBH_Process(USB_OTG_CORE_HANDLE *pdev , - USBH_HOST *phost); -void USBH_ErrorHandle(USBH_HOST *phost, - USBH_Status errType); - -/** - * @} - */ - -#endif /* __USBH_CORE_H */ -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_def.h b/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_def.h deleted file mode 100644 index 35ebeb42d..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_def.h +++ /dev/null @@ -1,280 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_def.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Definitions used in the USB host library - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_DEF - * @brief This file is includes USB descriptors - * @{ - */ - -#ifndef USBH_DEF_H -#define USBH_DEF_H - -#ifndef USBH_NULL -#define USBH_NULL ((void *)0) -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#ifndef TRUE -#define TRUE 1 -#endif - - -#define ValBit(VAR,POS) (VAR & (1 << POS)) -#define SetBit(VAR,POS) (VAR |= (1 << POS)) -#define ClrBit(VAR,POS) (VAR &= ((1 << POS)^255)) - -#define LE16(addr) (((u16)(*((u8 *)(addr))))\ - + (((u16)(*(((u8 *)(addr)) + 1))) << 8)) - -#define USB_LEN_DESC_HDR 0x02 -#define USB_LEN_DEV_DESC 0x12 -#define USB_LEN_CFG_DESC 0x09 -#define USB_LEN_IF_DESC 0x09 -#define USB_LEN_EP_DESC 0x07 -#define USB_LEN_OTG_DESC 0x03 -#define USB_LEN_SETUP_PKT 0x08 - -/* bmRequestType :D7 Data Phase Transfer Direction */ -#define USB_REQ_DIR_MASK 0x80 -#define USB_H2D 0x00 -#define USB_D2H 0x80 - -/* bmRequestType D6..5 Type */ -#define USB_REQ_TYPE_STANDARD 0x00 -#define USB_REQ_TYPE_CLASS 0x20 -#define USB_REQ_TYPE_VENDOR 0x40 -#define USB_REQ_TYPE_RESERVED 0x60 - -/* bmRequestType D4..0 Recipient */ -#define USB_REQ_RECIPIENT_DEVICE 0x00 -#define USB_REQ_RECIPIENT_INTERFACE 0x01 -#define USB_REQ_RECIPIENT_ENDPOINT 0x02 -#define USB_REQ_RECIPIENT_OTHER 0x03 - -/* Table 9-4. Standard Request Codes */ -/* bRequest , Value */ -#define USB_REQ_GET_STATUS 0x00 -#define USB_REQ_CLEAR_FEATURE 0x01 -#define USB_REQ_SET_FEATURE 0x03 -#define USB_REQ_SET_ADDRESS 0x05 -#define USB_REQ_GET_DESCRIPTOR 0x06 -#define USB_REQ_SET_DESCRIPTOR 0x07 -#define USB_REQ_GET_CONFIGURATION 0x08 -#define USB_REQ_SET_CONFIGURATION 0x09 -#define USB_REQ_GET_INTERFACE 0x0A -#define USB_REQ_SET_INTERFACE 0x0B -#define USB_REQ_SYNCH_FRAME 0x0C - -/* Table 9-5. Descriptor Types of USB Specifications */ -#define USB_DESC_TYPE_DEVICE 1 -#define USB_DESC_TYPE_CONFIGURATION 2 -#define USB_DESC_TYPE_STRING 3 -#define USB_DESC_TYPE_INTERFACE 4 -#define USB_DESC_TYPE_ENDPOINT 5 -#define USB_DESC_TYPE_DEVICE_QUALIFIER 6 -#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7 -#define USB_DESC_TYPE_INTERFACE_POWER 8 -#define USB_DESC_TYPE_HID 0x21 -#define USB_DESC_TYPE_HID_REPORT 0x22 - - -#define USB_DEVICE_DESC_SIZE 18 -#define USB_CONFIGURATION_DESC_SIZE 9 -#define USB_HID_DESC_SIZE 9 -#define USB_INTERFACE_DESC_SIZE 9 -#define USB_ENDPOINT_DESC_SIZE 7 - -/* Descriptor Type and Descriptor Index */ -/* Use the following values when calling the function USBH_GetDescriptor */ -#define USB_DESC_DEVICE ((USB_DESC_TYPE_DEVICE << 8) & 0xFF00) -#define USB_DESC_CONFIGURATION ((USB_DESC_TYPE_CONFIGURATION << 8) & 0xFF00) -#define USB_DESC_STRING ((USB_DESC_TYPE_STRING << 8) & 0xFF00) -#define USB_DESC_INTERFACE ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00) -#define USB_DESC_ENDPOINT ((USB_DESC_TYPE_INTERFACE << 8) & 0xFF00) -#define USB_DESC_DEVICE_QUALIFIER ((USB_DESC_TYPE_DEVICE_QUALIFIER << 8) & 0xFF00) -#define USB_DESC_OTHER_SPEED_CONFIGURATION ((USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION << 8) & 0xFF00) -#define USB_DESC_INTERFACE_POWER ((USB_DESC_TYPE_INTERFACE_POWER << 8) & 0xFF00) -#define USB_DESC_HID_REPORT ((USB_DESC_TYPE_HID_REPORT << 8) & 0xFF00) -#define USB_DESC_HID ((USB_DESC_TYPE_HID << 8) & 0xFF00) - - -#define USB_EP_TYPE_CTRL 0x00 -#define USB_EP_TYPE_ISOC 0x01 -#define USB_EP_TYPE_BULK 0x02 -#define USB_EP_TYPE_INTR 0x03 - -#define USB_EP_DIR_OUT 0x00 -#define USB_EP_DIR_IN 0x80 -#define USB_EP_DIR_MSK 0x80 - -/* supported classes */ -#define USB_MSC_CLASS 0x08 -#define USB_HID_CLASS 0x03 - -/* Interface Descriptor field values for HID Boot Protocol */ -#define HID_BOOT_CODE 0x01 -#define HID_KEYBRD_BOOT_CODE 0x01 -#define HID_MOUSE_BOOT_CODE 0x02 - -/* As per USB specs 9.2.6.4 :Standard request with data request timeout: 5sec - Standard request with no data stage timeout : 50ms */ -#define DATA_STAGE_TIMEOUT 5000 -#define NODATA_STAGE_TIMEOUT 50 - -/** - * @} - */ - - -#define USBH_CONFIGURATION_DESCRIPTOR_SIZE (USB_CONFIGURATION_DESC_SIZE \ - + USB_INTERFACE_DESC_SIZE\ - + (USBH_MAX_NUM_ENDPOINTS * USB_ENDPOINT_DESC_SIZE)) - - -#define CONFIG_DESC_wTOTAL_LENGTH (ConfigurationDescriptorData.ConfigDescfield.\ - ConfigurationDescriptor.wTotalLength) - - -/* This Union is copied from usb_core.h */ -typedef union -{ - uint16_t w; - struct BW - { - uint8_t msb; - uint8_t lsb; - } - bw; -} -uint16_t_uint8_t; - - -typedef union _USB_Setup -{ - uint8_t d8[8]; - - struct _SetupPkt_Struc - { - uint8_t bmRequestType; - uint8_t bRequest; - uint16_t_uint8_t wValue; - uint16_t_uint8_t wIndex; - uint16_t_uint8_t wLength; - } b; -} -USB_Setup_TypeDef; - -typedef struct _DescHeader -{ - uint8_t bLength; - uint8_t bDescriptorType; -} -USBH_DescHeader_t; - -typedef struct _DeviceDescriptor -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bcdUSB; /* USB Specification Number which device complies too */ - uint8_t bDeviceClass; - uint8_t bDeviceSubClass; - uint8_t bDeviceProtocol; - /* If equal to Zero, each interface specifies its own class - code if equal to 0xFF, the class code is vendor specified. - Otherwise field is valid Class Code.*/ - uint8_t bMaxPacketSize; - uint16_t idVendor; /* Vendor ID (Assigned by USB Org) */ - uint16_t idProduct; /* Product ID (Assigned by Manufacturer) */ - uint16_t bcdDevice; /* Device Release Number */ - uint8_t iManufacturer; /* Index of Manufacturer String Descriptor */ - uint8_t iProduct; /* Index of Product String Descriptor */ - uint8_t iSerialNumber; /* Index of Serial Number String Descriptor */ - uint8_t bNumConfigurations; /* Number of Possible Configurations */ -} -USBH_DevDesc_TypeDef; - - -typedef struct _ConfigurationDescriptor -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t wTotalLength; /* Total Length of Data Returned */ - uint8_t bNumInterfaces; /* Number of Interfaces */ - uint8_t bConfigurationValue; /* Value to use as an argument to select this configuration*/ - uint8_t iConfiguration; /*Index of String Descriptor Describing this configuration */ - uint8_t bmAttributes; /* D7 Bus Powered , D6 Self Powered, D5 Remote Wakeup , D4..0 Reserved (0)*/ - uint8_t bMaxPower; /*Maximum Power Consumption */ -} -USBH_CfgDesc_TypeDef; - - -typedef struct _HIDDescriptor -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint16_t bcdHID; /* indicates what endpoint this descriptor is describing */ - uint8_t bCountryCode; /* specifies the transfer type. */ - uint8_t bNumDescriptors; /* specifies the transfer type. */ - uint8_t bReportDescriptorType; /* Maximum Packet Size this endpoint is capable of sending or receiving */ - uint16_t wItemLength; /* is used to specify the polling interval of certain transfers. */ -} -USBH_HIDDesc_TypeDef; - - -typedef struct _InterfaceDescriptor -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bInterfaceNumber; - uint8_t bAlternateSetting; /* Value used to select alternative setting */ - uint8_t bNumEndpoints; /* Number of Endpoints used for this interface */ - uint8_t bInterfaceClass; /* Class Code (Assigned by USB Org) */ - uint8_t bInterfaceSubClass; /* Subclass Code (Assigned by USB Org) */ - uint8_t bInterfaceProtocol; /* Protocol Code */ - uint8_t iInterface; /* Index of String Descriptor Describing this interface */ - -} -USBH_InterfaceDesc_TypeDef; - - -typedef struct _EndpointDescriptor -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; /* indicates what endpoint this descriptor is describing */ - uint8_t bmAttributes; /* specifies the transfer type. */ - uint16_t wMaxPacketSize; /* Maximum Packet Size this endpoint is capable of sending or receiving */ - uint8_t bInterval; /* is used to specify the polling interval of certain transfers. */ -} -USBH_EpDesc_TypeDef; -#endif -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_hcs.h b/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_hcs.h deleted file mode 100644 index c5310b21b..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_hcs.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hcs.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Header file for usbh_hcs.c - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive ----------------------------------------------*/ -#ifndef __USBH_HCS_H -#define __USBH_HCS_H - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_core.h" - - - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_HCS - * @brief This file is the header file for usbh_hcs.c - * @{ - */ - -/** @defgroup USBH_HCS_Exported_Defines - * @{ - */ -#define HC_MAX 8 - -#define HC_OK 0x0000 -#define HC_USED 0x8000 -#define HC_ERROR 0xFFFF -#define HC_USED_MASK 0x7FFF -/** - * @} - */ - -/** @defgroup USBH_HCS_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_HCS_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HCS_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HCS_Exported_FunctionsPrototype - * @{ - */ - -uint8_t USBH_Alloc_Channel(USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr); - -uint8_t USBH_Free_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t idx); - -uint8_t USBH_DeAllocate_AllChannel (USB_OTG_CORE_HANDLE *pdev); - -uint8_t USBH_Open_Channel (USB_OTG_CORE_HANDLE *pdev, - uint8_t ch_num, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); - -uint8_t USBH_Modify_Channel (USB_OTG_CORE_HANDLE *pdev, - uint8_t hc_num, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps); -/** - * @} - */ - - - -#endif /* __USBH_HCS_H */ - - -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_ioreq.h b/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_ioreq.h deleted file mode 100644 index 4bdd43698..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_ioreq.h +++ /dev/null @@ -1,140 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_ioreq.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Header file for usbh_ioreq.c - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive ----------------------------------------------*/ -#ifndef __USBH_IOREQ_H -#define __USBH_IOREQ_H - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" -#include "usbh_core.h" -#include "usbh_def.h" - - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_IOREQ - * @brief This file is the header file for usbh_ioreq.c - * @{ - */ - - -/** @defgroup USBH_IOREQ_Exported_Defines - * @{ - */ -#define USBH_SETUP_PKT_SIZE 8 -#define USBH_EP0_EP_NUM 0 -#define USBH_MAX_PACKET_SIZE 0x40 -/** - * @} - */ - - -/** @defgroup USBH_IOREQ_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_IOREQ_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_IOREQ_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_IOREQ_Exported_FunctionsPrototype - * @{ - */ -USBH_Status USBH_CtlSendSetup ( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint8_t hc_num); - -USBH_Status USBH_CtlSendData ( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint8_t length, - uint8_t hc_num); - -USBH_Status USBH_CtlReceiveData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint8_t length, - uint8_t hc_num); - -USBH_Status USBH_BulkReceiveData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint16_t length, - uint8_t hc_num); - -USBH_Status USBH_BulkSendData ( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint16_t length, - uint8_t hc_num); - -USBH_Status USBH_InterruptReceiveData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint8_t length, - uint8_t hc_num); - -USBH_Status USBH_InterruptSendData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint8_t length, - uint8_t hc_num); - -USBH_Status USBH_CtlReq (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t *buff, - uint16_t length); -/** - * @} - */ - -#endif /* __USBH_IOREQ_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_stdreq.h b/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_stdreq.h deleted file mode 100644 index 22bf3d1da..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Core/inc/usbh_stdreq.h +++ /dev/null @@ -1,148 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_stdreq.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Header file for usbh_stdreq.c - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive ----------------------------------------------*/ -#ifndef __USBH_STDREQ_H -#define __USBH_STDREQ_H - -/* Includes ------------------------------------------------------------------*/ - -#include "usb_conf.h" -#include "usb_hcd.h" -#include "usbh_core.h" -#include "usbh_def.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_STDREQ - * @brief This file is the - * @{ - */ - - -/** @defgroup USBH_STDREQ_Exported_Defines - * @{ - */ -/*Standard Feature Selector for clear feature command*/ -#define FEATURE_SELECTOR_ENDPOINT 0X00 -#define FEATURE_SELECTOR_DEVICE 0X01 - - -#define INTERFACE_DESC_TYPE 0x04 -#define ENDPOINT_DESC_TYPE 0x05 -#define INTERFACE_DESC_SIZE 0x09 - - -#define USBH_HID_CLASS 0x03 - -/** - * @} - */ - - -/** @defgroup USBH_STDREQ_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_STDREQ_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_STDREQ_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_STDREQ_Exported_FunctionsPrototype - * @{ - */ -USBH_Status USBH_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t req_type, - uint16_t value_idx, - uint8_t* buff, - uint16_t length ); - -USBH_Status USBH_Get_DevDesc(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t length); - -USBH_Status USBH_Get_StringDesc(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t string_index, - uint8_t *buff, - uint16_t length); - -USBH_Status USBH_SetCfg(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint16_t configuration_value); - -USBH_Status USBH_Get_CfgDesc(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint16_t length); - -USBH_Status USBH_SetAddress(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t DeviceAddress); - -USBH_Status USBH_ClrFeature(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t ep_num, uint8_t hc_num); - -USBH_Status USBH_Issue_ClrFeature(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t ep_num); -/** - * @} - */ - -#endif /* __USBH_STDREQ_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Core/src/usbh_core.c b/example/stm32f4/STM32_USB_HOST_Library/Core/src/usbh_core.c deleted file mode 100644 index a15535752..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Core/src/usbh_core.c +++ /dev/null @@ -1,842 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_core.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief This file implements the functions for the core state machine process - * the enumeration and the control transfer process - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ - -#include "usbh_ioreq.h" -#include "usb_bsp.h" -#include "usbh_hcs.h" -#include "usbh_stdreq.h" -#include "usbh_core.h" - - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_CORE - * @brief TThis file handles the basic enumaration when a device is connected - * to the host. - * @{ - */ - -/** @defgroup USBH_CORE_Private_TypesDefinitions - * @{ - */ -void USBH_Disconnect (void *pdev); -void USBH_Connect (void *pdev); - -USB_OTG_hPort_TypeDef USBH_DeviceConnStatus_cb = -{ - USBH_Disconnect, - USBH_Connect, - 0, - 0, - 0, - 0 -}; -/** - * @} - */ - - -/** @defgroup USBH_CORE_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_CORE_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_CORE_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_CORE_Private_FunctionPrototypes - * @{ - */ -static USBH_Status USBH_HandleEnum(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost); -USBH_Status USBH_HandleControl (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost); - -/** - * @} - */ - - -/** @defgroup USBH_CORE_Private_Functions - * @{ - */ - - -/** - * @brief USBH_Connect - * USB Connect callback function from the Interrupt. - * @param selected device - * @retval none - */ -void USBH_Connect (void *pdev) -{ - USB_OTG_CORE_HANDLE *ppdev = pdev; - ppdev->host.port_cb->ConnStatus = 1; - ppdev->host.port_cb->ConnHandled = 0; -} - -/** - * @brief USBH_Disconnect - * USB Disconnect callback function from the Interrupt. - * @param selected device - * @retval none - */ - -void USBH_Disconnect (void *pdev) -{ - - USB_OTG_CORE_HANDLE *ppdev = pdev; - - /* Make device Not connected flag true */ - ppdev->host.port_cb->DisconnStatus = 1; - ppdev->host.port_cb->DisconnHandled = 0; -} - -/** - * @brief USBH_Init - * Host hardware and stack initializations - * @param class_cb: Class callback structure address - * @param usr_cb: User callback structure address - * @retval None - */ -void USBH_Init(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID, - USBH_HOST *phost, - USBH_Class_cb_TypeDef *class_cb, - USBH_Usr_cb_TypeDef *usr_cb) -{ - - /* Hardware Init */ - USB_OTG_BSP_Init(pdev); - - /* configure GPIO pin used for switching VBUS power */ - USB_OTG_BSP_ConfigVBUS(0); - - - /* Host de-initializations */ - USBH_DeInit(pdev, phost); - - /*Register class and user callbacks */ - phost->class_cb = class_cb; - phost->usr_cb = usr_cb; - pdev->host.port_cb = &USBH_DeviceConnStatus_cb; - - pdev->host.port_cb->ConnStatus = 0; - pdev->host.port_cb->DisconnStatus = 0; - - - /* Start the USB OTG core */ - HCD_Init(pdev , coreID); - - /* Upon Init call usr call back */ - phost->usr_cb->Init(); - - /* Enable Interrupts */ - USB_OTG_BSP_EnableInterrupt(pdev); -} - -/** - * @brief USBH_DeInit - * Re-Initialize Host - * @param None - * @retval status: USBH_Status - */ -USBH_Status USBH_DeInit(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost) -{ - /* Software Init */ - - phost->gState = HOST_IDLE; - phost->gStateBkp = HOST_IDLE; - phost->EnumState = ENUM_IDLE; - phost->RequestState = CMD_SEND; - - phost->Control.state = CTRL_SETUP; - phost->Control.ep0size = USB_OTG_MAX_EP0_SIZE; - - phost->device_prop.address = USBH_DEVICE_ADDRESS_DEFAULT; - phost->device_prop.speed = HPRT0_PRTSPD_FULL_SPEED; - - USBH_Free_Channel (pdev, phost->Control.hc_num_in); - USBH_Free_Channel (pdev, phost->Control.hc_num_out); - return USBH_OK; -} - -/** -* @brief USBH_Process -* USB Host core main state machine process -* @param None -* @retval None -*/ -void USBH_Process(USB_OTG_CORE_HANDLE *pdev , USBH_HOST *phost) -{ - volatile USBH_Status status = USBH_FAIL; - - switch (phost->gState) - { - case HOST_ISSUE_CORE_RESET : - - if ( HCD_ResetPort(pdev) == 0) - { - phost->gState = HOST_IDLE; - } - break; - - case HOST_IDLE : - - if (HCD_IsDeviceConnected(pdev)) - { - /* Wait for USB Connect Interrupt void USBH_ISR_Connected(void) */ - USBH_DeAllocate_AllChannel(pdev); - phost->gState = HOST_DEV_ATTACHED; - } - break; - - case HOST_DEV_ATTACHED : - - phost->usr_cb->DeviceAttached(); - pdev->host.port_cb->DisconnStatus = 0; - pdev->host.port_cb->ConnHandled = 1; - - phost->Control.hc_num_out = USBH_Alloc_Channel(pdev, 0x00); - phost->Control.hc_num_in = USBH_Alloc_Channel(pdev, 0x80); - - /* Reset USB Device */ - if ( HCD_ResetPort(pdev) == 0) - { - phost->usr_cb->ResetDevice(); - /* Wait for USB USBH_ISR_PrtEnDisableChange() - Host is Now ready to start the Enumeration - */ - - phost->device_prop.speed = HCD_GetCurrentSpeed(pdev); - - phost->gState = HOST_ENUMERATION; - phost->usr_cb->DeviceSpeedDetected(phost->device_prop.speed); - - /* Open Control pipes */ - USBH_Open_Channel (pdev, - phost->Control.hc_num_in, - phost->device_prop.address, - phost->device_prop.speed, - EP_TYPE_CTRL, - phost->Control.ep0size); - - /* Open Control pipes */ - USBH_Open_Channel (pdev, - phost->Control.hc_num_out, - phost->device_prop.address, - phost->device_prop.speed, - EP_TYPE_CTRL, - phost->Control.ep0size); - } - break; - - case HOST_ENUMERATION: - /* Check for enumeration status */ - if ( USBH_HandleEnum(pdev , phost) == USBH_OK) - { - /* The function shall return USBH_OK when full enumeration is complete */ - - /* user callback for end of device basic enumeration */ - phost->usr_cb->EnumerationDone(); - - phost->gState = HOST_USR_INPUT; - } - break; - - case HOST_USR_INPUT: - /*The function should return user response true to move to class state */ - if ( phost->usr_cb->UserInput() == USBH_USR_RESP_OK) - { - if((phost->class_cb->Init(pdev, phost))\ - == USBH_OK) - { - phost->gState = HOST_CLASS_REQUEST; - } - } - break; - - case HOST_CLASS_REQUEST: - /* process class standard contol requests state machine */ - status = phost->class_cb->Requests(pdev, phost); - - if(status == USBH_OK) - { - phost->gState = HOST_CLASS; - } - - else - { - USBH_ErrorHandle(phost, status); - } - - - break; - case HOST_CLASS: - /* process class state machine */ - status = phost->class_cb->Machine(pdev, phost); - USBH_ErrorHandle(phost, status); - break; - - case HOST_CTRL_XFER: - /* process control transfer state machine */ - USBH_HandleControl(pdev, phost); - break; - - case HOST_SUSPENDED: - break; - - case HOST_ERROR_STATE: - /* Re-Initilaize Host for new Enumeration */ - USBH_DeInit(pdev, phost); - phost->usr_cb->DeInit(); - phost->class_cb->DeInit(pdev, &phost->device_prop); - break; - - default : - break; - } - - /* check device disconnection event */ - if (!(HCD_IsDeviceConnected(pdev)) && - (pdev->host.port_cb->DisconnHandled == 0)) - { - /* Manage User disconnect operations*/ - phost->usr_cb->DeviceDisconnected(); - - pdev->host.port_cb->DisconnHandled = 1; /* Handle to avoid the Re-entry*/ - - /* Re-Initilaize Host for new Enumeration */ - USBH_DeInit(pdev, phost); - phost->usr_cb->DeInit(); - phost->class_cb->DeInit(pdev, &phost->device_prop); - } -} - - -/** - * @brief USBH_ErrorHandle - * This function handles the Error on Host side. - * @param errType : Type of Error or Busy/OK state - * @retval None - */ -void USBH_ErrorHandle(USBH_HOST *phost, USBH_Status errType) -{ - /* Error unrecovered or not supported device speed */ - if ( (errType == USBH_ERROR_SPEED_UNKNOWN) || - (errType == USBH_UNRECOVERED_ERROR) ) - { - phost->usr_cb->UnrecoveredError(); - phost->gState = HOST_ERROR_STATE; - } - /* USB host restart requested from application layer */ - else if(errType == USBH_APPLY_DEINIT) - { - phost->gState = HOST_ERROR_STATE; - /* user callback for initalization */ - phost->usr_cb->Init(); - } -} - - -/** - * @brief USBH_HandleEnum - * This function includes the complete enumeration process - * @param pdev: Selected device - * @retval USBH_Status - */ -static USBH_Status USBH_HandleEnum(USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost) -{ - USBH_Status Status = USBH_BUSY; - uint8_t Local_Buffer[64]; - - switch (phost->EnumState) - { - case ENUM_IDLE: - /* Get Device Desc for only 1st 8 bytes : To get EP0 MaxPacketSize */ - if ( USBH_Get_DevDesc(pdev , phost, 8) == USBH_OK) - { - phost->Control.ep0size = phost->device_prop.Dev_Desc.bMaxPacketSize; - - /* Issue Reset */ - HCD_ResetPort(pdev); - phost->EnumState = ENUM_GET_FULL_DEV_DESC; - - /* modify control channels configuration for MaxPacket size */ - USBH_Modify_Channel (pdev, - phost->Control.hc_num_out, - 0, - 0, - 0, - phost->Control.ep0size); - - USBH_Modify_Channel (pdev, - phost->Control.hc_num_in, - 0, - 0, - 0, - phost->Control.ep0size); - } - break; - - case ENUM_GET_FULL_DEV_DESC: - /* Get FULL Device Desc */ - if ( USBH_Get_DevDesc(pdev, phost, USB_DEVICE_DESC_SIZE)\ - == USBH_OK) - { - /* user callback for device descriptor available */ - phost->usr_cb->DeviceDescAvailable(&phost->device_prop.Dev_Desc); - phost->EnumState = ENUM_SET_ADDR; - } - break; - - case ENUM_SET_ADDR: - /* set address */ - if ( USBH_SetAddress(pdev, phost, USBH_DEVICE_ADDRESS) == USBH_OK) - { - phost->device_prop.address = USBH_DEVICE_ADDRESS; - - /* user callback for device address assigned */ - phost->usr_cb->DeviceAddressAssigned(); - phost->EnumState = ENUM_GET_CFG_DESC; - - /* modify control channels to update device address */ - USBH_Modify_Channel (pdev, - phost->Control.hc_num_in, - phost->device_prop.address, - 0, - 0, - 0); - - USBH_Modify_Channel (pdev, - phost->Control.hc_num_out, - phost->device_prop.address, - 0, - 0, - 0); - } - break; - - case ENUM_GET_CFG_DESC: - /* get standard configuration descriptor */ - if ( USBH_Get_CfgDesc(pdev, - phost, - USB_CONFIGURATION_DESC_SIZE) == USBH_OK) - { - phost->EnumState = ENUM_GET_FULL_CFG_DESC; - } - break; - - case ENUM_GET_FULL_CFG_DESC: - /* get FULL config descriptor (config, interface, endpoints) */ - if (USBH_Get_CfgDesc(pdev, - phost, - phost->device_prop.Cfg_Desc.wTotalLength) == USBH_OK) - { - /* User callback for configuration descriptors available */ - phost->usr_cb->ConfigurationDescAvailable(&phost->device_prop.Cfg_Desc, - phost->device_prop.Itf_Desc, - phost->device_prop.Ep_Desc[0]); - - phost->EnumState = ENUM_GET_MFC_STRING_DESC; - } - break; - - case ENUM_GET_MFC_STRING_DESC: - if (phost->device_prop.Dev_Desc.iManufacturer != 0) - { /* Check that Manufacturer String is available */ - - if ( USBH_Get_StringDesc(pdev, - phost, - phost->device_prop.Dev_Desc.iManufacturer, - Local_Buffer , - 0xff) == USBH_OK) - { - /* User callback for Manufacturing string */ - phost->usr_cb->ManufacturerString(Local_Buffer); - phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC; - } - } - else - { - phost->usr_cb->ManufacturerString("N/A"); - phost->EnumState = ENUM_GET_PRODUCT_STRING_DESC; - } - break; - - case ENUM_GET_PRODUCT_STRING_DESC: - if (phost->device_prop.Dev_Desc.iProduct != 0) - { /* Check that Product string is available */ - if ( USBH_Get_StringDesc(pdev, - phost, - phost->device_prop.Dev_Desc.iProduct, - Local_Buffer, - 0xff) == USBH_OK) - { - /* User callback for Product string */ - phost->usr_cb->ProductString(Local_Buffer); - phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC; - } - } - else - { - phost->usr_cb->ProductString("N/A"); - phost->EnumState = ENUM_GET_SERIALNUM_STRING_DESC; - } - break; - - case ENUM_GET_SERIALNUM_STRING_DESC: - if (phost->device_prop.Dev_Desc.iSerialNumber != 0) - { /* Check that Serial number string is available */ - if ( USBH_Get_StringDesc(pdev, - phost, - phost->device_prop.Dev_Desc.iSerialNumber, - Local_Buffer, - 0xff) == USBH_OK) - { - /* User callback for Serial number string */ - phost->usr_cb->SerialNumString(Local_Buffer); - phost->EnumState = ENUM_SET_CONFIGURATION; - } - } - else - { - phost->usr_cb->SerialNumString("N/A"); - phost->EnumState = ENUM_SET_CONFIGURATION; - } - break; - - case ENUM_SET_CONFIGURATION: - /* set configuration (default config) */ - if (USBH_SetCfg(pdev, - phost, - phost->device_prop.Cfg_Desc.bConfigurationValue) == USBH_OK) - { - phost->EnumState = ENUM_DEV_CONFIGURED; - } - break; - - - case ENUM_DEV_CONFIGURED: - /* user callback for enumeration done */ - Status = USBH_OK; - break; - - default: - break; - } - return Status; -} - - -/** - * @brief USBH_HandleControl - * Handles the USB control transfer state machine - * @param pdev: Selected device - * @retval Status - */ -USBH_Status USBH_HandleControl (USB_OTG_CORE_HANDLE *pdev, USBH_HOST *phost) -{ - uint8_t direction; - static uint16_t timeout = 0; - USBH_Status status = USBH_OK; - URB_STATE URB_Status = URB_IDLE; - - phost->Control.status = CTRL_START; - - - switch (phost->Control.state) - { - case CTRL_SETUP: - /* send a SETUP packet */ - USBH_CtlSendSetup (pdev, - phost->Control.setup.d8 , - phost->Control.hc_num_out); - phost->Control.state = CTRL_SETUP_WAIT; - break; - - case CTRL_SETUP_WAIT: - - URB_Status = HCD_GetURB_State(pdev , phost->Control.hc_num_out); - /* case SETUP packet sent successfully */ - if(URB_Status == URB_DONE) - { - direction = (phost->Control.setup.b.bmRequestType & USB_REQ_DIR_MASK); - - /* check if there is a data stage */ - if (phost->Control.setup.b.wLength.w != 0 ) - { - timeout = DATA_STAGE_TIMEOUT; - if (direction == USB_D2H) - { - /* Data Direction is IN */ - phost->Control.state = CTRL_DATA_IN; - } - else - { - /* Data Direction is OUT */ - phost->Control.state = CTRL_DATA_OUT; - } - } - /* No DATA stage */ - else - { - timeout = NODATA_STAGE_TIMEOUT; - - /* If there is No Data Transfer Stage */ - if (direction == USB_D2H) - { - /* Data Direction is IN */ - phost->Control.state = CTRL_STATUS_OUT; - } - else - { - /* Data Direction is OUT */ - phost->Control.state = CTRL_STATUS_IN; - } - } - /* Set the delay timer to enable timeout for data stage completion */ - phost->Control.timer = HCD_GetCurrentFrame(pdev); - } - else if(URB_Status == URB_ERROR) - { - phost->Control.state = CTRL_ERROR; - phost->Control.status = CTRL_XACTERR; - } - break; - - case CTRL_DATA_IN: - /* Issue an IN token */ - USBH_CtlReceiveData(pdev, - phost->Control.buff, - phost->Control.length, - phost->Control.hc_num_in); - - phost->Control.state = CTRL_DATA_IN_WAIT; - break; - - case CTRL_DATA_IN_WAIT: - - URB_Status = HCD_GetURB_State(pdev , phost->Control.hc_num_in); - - /* check is DATA packet transfered successfully */ - if (URB_Status == URB_DONE) - { - phost->Control.state = CTRL_STATUS_OUT; - } - - /* manage error cases*/ - if (URB_Status == URB_STALL) - { - /* In stall case, return to previous machine state*/ - phost->gState = phost->gStateBkp; - } - else if (URB_Status == URB_ERROR) - { - /* Device error */ - phost->Control.state = CTRL_ERROR; - } - else if ((HCD_GetCurrentFrame(pdev)- phost->Control.timer) > timeout) - { - /* timeout for IN transfer */ - phost->Control.state = CTRL_ERROR; - } - break; - - case CTRL_DATA_OUT: - /* Start DATA out transfer (only one DATA packet)*/ - - pdev->host.hc[phost->Control.hc_num_out].toggle_out ^= 1; - - USBH_CtlSendData (pdev, - phost->Control.buff, - phost->Control.length , - phost->Control.hc_num_out); - - phost->Control.state = CTRL_DATA_OUT_WAIT; - break; - - case CTRL_DATA_OUT_WAIT: - - URB_Status = HCD_GetURB_State(pdev , phost->Control.hc_num_out); - if (URB_Status == URB_DONE) - { /* If the Setup Pkt is sent successful, then change the state */ - phost->Control.state = CTRL_STATUS_IN; - } - - /* handle error cases */ - else if (URB_Status == URB_STALL) - { - /* In stall case, return to previous machine state*/ - phost->gState = phost->gStateBkp; - } - else if (URB_Status == URB_NOTREADY) - { - /* Nack received from device */ - phost->Control.state = CTRL_DATA_OUT; - } - else if (URB_Status == URB_ERROR) - { - /* device error */ - phost->Control.state = CTRL_ERROR; - } - break; - - - case CTRL_STATUS_IN: - /* Send 0 bytes out packet */ - USBH_CtlReceiveData (pdev, - 0, - 0, - phost->Control.hc_num_in); - - phost->Control.state = CTRL_STATUS_IN_WAIT; - - break; - - case CTRL_STATUS_IN_WAIT: - - URB_Status = HCD_GetURB_State(pdev , phost->Control.hc_num_in); - - if ( URB_Status == URB_DONE) - { /* Control transfers completed, Exit the State Machine */ - phost->gState = phost->gStateBkp; - } - - else if (URB_Status == URB_ERROR) - { - phost->Control.state = CTRL_ERROR; - } - - else if((HCD_GetCurrentFrame(pdev)\ - - phost->Control.timer) > timeout) - { - phost->Control.state = CTRL_ERROR; - } - else if(URB_Status == URB_STALL) - { - /* Control transfers completed, Exit the State Machine */ - phost->gState = phost->gStateBkp; - phost->Control.status = CTRL_STALL; - status = USBH_NOT_SUPPORTED; - } - break; - - case CTRL_STATUS_OUT: - pdev->host.hc[phost->Control.hc_num_out].toggle_out ^= 1; - USBH_CtlSendData (pdev, - 0, - 0, - phost->Control.hc_num_out); - - phost->Control.state = CTRL_STATUS_OUT_WAIT; - break; - - case CTRL_STATUS_OUT_WAIT: - - URB_Status = HCD_GetURB_State(pdev , phost->Control.hc_num_out); - if (URB_Status == URB_DONE) - { - phost->gState = phost->gStateBkp; - } - else if (URB_Status == URB_NOTREADY) - { - phost->Control.state = CTRL_STATUS_OUT; - } - else if (URB_Status == URB_ERROR) - { - phost->Control.state = CTRL_ERROR; - } - break; - - case CTRL_ERROR: - /* - After a halt condition is encountered or an error is detected by the - host, a control endpoint is allowed to recover by accepting the next Setup - PID; i.e., recovery actions via some other pipe are not required for control - endpoints. For the Default Control Pipe, a device reset will ultimately be - required to clear the halt or error condition if the next Setup PID is not - accepted. - */ - if (++ phost->Control.errorcount <= USBH_MAX_ERROR_COUNT) - { - /* Do the transmission again, starting from SETUP Packet */ - phost->Control.state = CTRL_SETUP; - } - else - { - phost->Control.status = CTRL_FAIL; - phost->gState = phost->gStateBkp; - - status = USBH_FAIL; - } - break; - - default: - break; - } - return status; -} - - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - - - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Core/src/usbh_hcs.c b/example/stm32f4/STM32_USB_HOST_Library/Core/src/usbh_hcs.c deleted file mode 100644 index c703d3998..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Core/src/usbh_hcs.c +++ /dev/null @@ -1,253 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_hcs.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief This file implements functions for opening and closing host channels - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usbh_hcs.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_HCS - * @brief This file includes opening and closing host channels - * @{ - */ - -/** @defgroup USBH_HCS_Private_Defines - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_HCS_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_HCS_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_HCS_Private_Variables - * @{ - */ - -/** - * @} - */ - - -/** @defgroup USBH_HCS_Private_FunctionPrototypes - * @{ - */ -static uint16_t USBH_GetFreeChannel (USB_OTG_CORE_HANDLE *pdev); -/** - * @} - */ - - -/** @defgroup USBH_HCS_Private_Functions - * @{ - */ - - - -/** - * @brief USBH_Open_Channel - * Open a pipe - * @param pdev : Selected device - * @param hc_num: Host channel Number - * @param dev_address: USB Device address allocated to attached device - * @param speed : USB device speed (Full/Low) - * @param ep_type: end point type (Bulk/int/ctl) - * @param mps: max pkt size - * @retval Status - */ -uint8_t USBH_Open_Channel (USB_OTG_CORE_HANDLE *pdev, - uint8_t hc_num, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) -{ - - pdev->host.hc[hc_num].ep_num = pdev->host.channel[hc_num]& 0x7F; - pdev->host.hc[hc_num].ep_is_in = (pdev->host.channel[hc_num] & 0x80 ) == 0x80; - pdev->host.hc[hc_num].dev_addr = dev_address; - pdev->host.hc[hc_num].ep_type = ep_type; - pdev->host.hc[hc_num].max_packet = mps; - pdev->host.hc[hc_num].speed = speed; - pdev->host.hc[hc_num].toggle_in = 0; - pdev->host.hc[hc_num].toggle_out = 0; - if(speed == HPRT0_PRTSPD_HIGH_SPEED) - { - pdev->host.hc[hc_num].do_ping = 1; - } - - USB_OTG_HC_Init(pdev, hc_num) ; - - return HC_OK; - -} - -/** - * @brief USBH_Modify_Channel - * Modify a pipe - * @param pdev : Selected device - * @param hc_num: Host channel Number - * @param dev_address: USB Device address allocated to attached device - * @param speed : USB device speed (Full/Low) - * @param ep_type: end point type (Bulk/int/ctl) - * @param mps: max pkt size - * @retval Status - */ -uint8_t USBH_Modify_Channel (USB_OTG_CORE_HANDLE *pdev, - uint8_t hc_num, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, - uint16_t mps) -{ - - if(dev_address != 0) - { - pdev->host.hc[hc_num].dev_addr = dev_address; - } - - if((pdev->host.hc[hc_num].max_packet != mps) && (mps != 0)) - { - pdev->host.hc[hc_num].max_packet = mps; - } - - if((pdev->host.hc[hc_num].speed != speed ) && (speed != 0 )) - { - pdev->host.hc[hc_num].speed = speed; - } - - USB_OTG_HC_Init(pdev, hc_num); - return HC_OK; - -} - -/** - * @brief USBH_Alloc_Channel - * Allocate a new channel for the pipe - * @param ep_addr: End point for which the channel to be allocated - * @retval hc_num: Host channel number - */ -uint8_t USBH_Alloc_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t ep_addr) -{ - uint16_t hc_num; - - hc_num = USBH_GetFreeChannel(pdev); - - if (hc_num != HC_ERROR) - { - pdev->host.channel[hc_num] = HC_USED | ep_addr; - } - return hc_num; -} - -/** - * @brief USBH_Free_Pipe - * Free the USB host channel - * @param idx: Channel number to be freed - * @retval Status - */ -uint8_t USBH_Free_Channel (USB_OTG_CORE_HANDLE *pdev, uint8_t idx) -{ - if(idx < HC_MAX) - { - pdev->host.channel[idx] &= HC_USED_MASK; - } - return USBH_OK; -} - - -/** - * @brief USBH_DeAllocate_AllChannel - * Free all USB host channel -* @param pdev : core instance - * @retval Status - */ -uint8_t USBH_DeAllocate_AllChannel (USB_OTG_CORE_HANDLE *pdev) -{ - uint8_t idx; - - for (idx = 2; idx < HC_MAX ; idx ++) - { - pdev->host.channel[idx] = 0; - } - return USBH_OK; -} - -/** - * @brief USBH_GetFreeChannel - * Get a free channel number for allocation to a device endpoint - * @param None - * @retval idx: Free Channel number - */ -static uint16_t USBH_GetFreeChannel (USB_OTG_CORE_HANDLE *pdev) -{ - uint8_t idx = 0; - - for (idx = 0 ; idx < HC_MAX ; idx++) - { - if ((pdev->host.channel[idx] & HC_USED) == 0) - { - return idx; - } - } - return HC_ERROR; -} - - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Core/src/usbh_ioreq.c b/example/stm32f4/STM32_USB_HOST_Library/Core/src/usbh_ioreq.c deleted file mode 100644 index a89084803..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Core/src/usbh_ioreq.c +++ /dev/null @@ -1,419 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_ioreq.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief This file handles the issuing of the USB transactions - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ - -#include "usbh_ioreq.h" - -/** @addtogroup USBH_LIB - * @{ - */ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_IOREQ - * @brief This file handles the standard protocol processing (USB v2.0) - * @{ - */ - - -/** @defgroup USBH_IOREQ_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_IOREQ_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USBH_IOREQ_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_IOREQ_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup USBH_IOREQ_Private_FunctionPrototypes - * @{ - */ -static USBH_Status USBH_SubmitSetupRequest(USBH_HOST *phost, - uint8_t* buff, - uint16_t length); - -/** - * @} - */ - - -/** @defgroup USBH_IOREQ_Private_Functions - * @{ - */ - - -/** - * @brief USBH_CtlReq - * USBH_CtlReq sends a control request and provide the status after - * completion of the request - * @param pdev: Selected device - * @param req: Setup Request Structure - * @param buff: data buffer address to store the response - * @param length: length of the response - * @retval Status - */ -USBH_Status USBH_CtlReq (USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t *buff, - uint16_t length) -{ - USBH_Status status; - URB_STATE URB_Status = URB_IDLE; - - URB_Status = HCD_GetURB_State(pdev, phost->Control.hc_num_out); - - status = USBH_BUSY; - - switch (phost->RequestState) - { - case CMD_SEND: - /* Start a SETUP transfer */ - USBH_SubmitSetupRequest(phost, buff, length); - phost->RequestState = CMD_WAIT; - status = USBH_BUSY; - break; - - case CMD_WAIT: - if (URB_Status == URB_DONE) - { - /* Commands successfully sent and Response Received */ - phost->RequestState = CMD_SEND; - status = USBH_OK; - } - else if (URB_Status == URB_ERROR) - { - /* Failure Mode */ - phost->RequestState = CMD_SEND; - status = USBH_FAIL; - } - else if (URB_Status == URB_STALL) - { - /* Commands successfully sent and Response Received */ - phost->RequestState = CMD_SEND; - status = USBH_NOT_SUPPORTED; - } - break; - - default: - break; - } - return status; -} - -/** - * @brief USBH_CtlSendSetup - * Sends the Setup Packet to the Device - * @param pdev: Selected device - * @param buff: Buffer pointer from which the Data will be send to Device - * @param hc_num: Host channel Number - * @retval Status - */ -USBH_Status USBH_CtlSendSetup ( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint8_t hc_num){ - pdev->host.hc[hc_num].ep_is_in = 0; - pdev->host.hc[hc_num].data_pid = HC_PID_SETUP; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = USBH_SETUP_PKT_SIZE; - - return (USBH_Status)HCD_SubmitRequest (pdev , hc_num); -} - - -/** - * @brief USBH_CtlSendData - * Sends a data Packet to the Device - * @param pdev: Selected device - * @param buff: Buffer pointer from which the Data will be sent to Device - * @param length: Length of the data to be sent - * @param hc_num: Host channel Number - * @retval Status - */ -USBH_Status USBH_CtlSendData ( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint8_t length, - uint8_t hc_num) -{ - pdev->host.hc[hc_num].ep_is_in = 0; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = length; - - if ( length == 0 ) - { /* For Status OUT stage, Length==0, Status Out PID = 1 */ - pdev->host.hc[hc_num].toggle_out = 1; - } - - /* Set the Data Toggle bit as per the Flag */ - if ( pdev->host.hc[hc_num].toggle_out == 0) - { /* Put the PID 0 */ - pdev->host.hc[hc_num].data_pid = HC_PID_DATA0; - } - else - { /* Put the PID 1 */ - pdev->host.hc[hc_num].data_pid = HC_PID_DATA1 ; - } - - HCD_SubmitRequest (pdev , hc_num); - - return USBH_OK; -} - - -/** - * @brief USBH_CtlReceiveData - * Receives the Device Response to the Setup Packet - * @param pdev: Selected device - * @param buff: Buffer pointer in which the response needs to be copied - * @param length: Length of the data to be received - * @param hc_num: Host channel Number - * @retval Status. - */ -USBH_Status USBH_CtlReceiveData(USB_OTG_CORE_HANDLE *pdev, - uint8_t* buff, - uint8_t length, - uint8_t hc_num) -{ - - pdev->host.hc[hc_num].ep_is_in = 1; - pdev->host.hc[hc_num].data_pid = HC_PID_DATA1; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = length; - - HCD_SubmitRequest (pdev , hc_num); - - return USBH_OK; - -} - - -/** - * @brief USBH_BulkSendData - * Sends the Bulk Packet to the device - * @param pdev: Selected device - * @param buff: Buffer pointer from which the Data will be sent to Device - * @param length: Length of the data to be sent - * @param hc_num: Host channel Number - * @retval Status - */ -USBH_Status USBH_BulkSendData ( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint16_t length, - uint8_t hc_num) -{ - pdev->host.hc[hc_num].ep_is_in = 0; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = length; - - /* Set the Data Toggle bit as per the Flag */ - if ( pdev->host.hc[hc_num].toggle_out == 0) - { /* Put the PID 0 */ - pdev->host.hc[hc_num].data_pid = HC_PID_DATA0; - } - else - { /* Put the PID 1 */ - pdev->host.hc[hc_num].data_pid = HC_PID_DATA1 ; - } - - HCD_SubmitRequest (pdev , hc_num); - return USBH_OK; -} - - -/** - * @brief USBH_BulkReceiveData - * Receives IN bulk packet from device - * @param pdev: Selected device - * @param buff: Buffer pointer in which the received data packet to be copied - * @param length: Length of the data to be received - * @param hc_num: Host channel Number - * @retval Status. - */ -USBH_Status USBH_BulkReceiveData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint16_t length, - uint8_t hc_num) -{ - pdev->host.hc[hc_num].ep_is_in = 1; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = length; - - - if( pdev->host.hc[hc_num].toggle_in == 0) - { - pdev->host.hc[hc_num].data_pid = HC_PID_DATA0; - } - else - { - pdev->host.hc[hc_num].data_pid = HC_PID_DATA1; - } - - HCD_SubmitRequest (pdev , hc_num); - return USBH_OK; -} - - -/** - * @brief USBH_InterruptReceiveData - * Receives the Device Response to the Interrupt IN token - * @param pdev: Selected device - * @param buff: Buffer pointer in which the response needs to be copied - * @param length: Length of the data to be received - * @param hc_num: Host channel Number - * @retval Status. - */ -USBH_Status USBH_InterruptReceiveData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint8_t length, - uint8_t hc_num) -{ - - pdev->host.hc[hc_num].ep_is_in = 1; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = length; - - - - if(pdev->host.hc[hc_num].toggle_in == 0) - { - pdev->host.hc[hc_num].data_pid = HC_PID_DATA0; - } - else - { - pdev->host.hc[hc_num].data_pid = HC_PID_DATA1; - } - - /* toggle DATA PID */ - pdev->host.hc[hc_num].toggle_in ^= 1; - - HCD_SubmitRequest (pdev , hc_num); - - return USBH_OK; -} - -/** - * @brief USBH_InterruptSendData - * Sends the data on Interrupt OUT Endpoint - * @param pdev: Selected device - * @param buff: Buffer pointer from where the data needs to be copied - * @param length: Length of the data to be sent - * @param hc_num: Host channel Number - * @retval Status. - */ -USBH_Status USBH_InterruptSendData( USB_OTG_CORE_HANDLE *pdev, - uint8_t *buff, - uint8_t length, - uint8_t hc_num) -{ - - pdev->host.hc[hc_num].ep_is_in = 0; - pdev->host.hc[hc_num].xfer_buff = buff; - pdev->host.hc[hc_num].xfer_len = length; - - if(pdev->host.hc[hc_num].toggle_in == 0) - { - pdev->host.hc[hc_num].data_pid = HC_PID_DATA0; - } - else - { - pdev->host.hc[hc_num].data_pid = HC_PID_DATA1; - } - - pdev->host.hc[hc_num].toggle_in ^= 1; - - HCD_SubmitRequest (pdev , hc_num); - - return USBH_OK; -} - - -/** - * @brief USBH_SubmitSetupRequest - * Start a setup transfer by changing the state-machine and - * initializing the required variables needed for the Control Transfer - * @param pdev: Selected device - * @param setup: Setup Request Structure - * @param buff: Buffer used for setup request - * @param length: Length of the data - * @retval Status. -*/ -static USBH_Status USBH_SubmitSetupRequest(USBH_HOST *phost, - uint8_t* buff, - uint16_t length) -{ - - /* Save Global State */ - phost->gStateBkp = phost->gState; - - /* Prepare the Transactions */ - phost->gState = HOST_CTRL_XFER; - phost->Control.buff = buff; - phost->Control.length = length; - phost->Control.state = CTRL_SETUP; - - return USBH_OK; -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - - diff --git a/example/stm32f4/STM32_USB_HOST_Library/Core/src/usbh_stdreq.c b/example/stm32f4/STM32_USB_HOST_Library/Core/src/usbh_stdreq.c deleted file mode 100644 index fb90c4ba7..000000000 --- a/example/stm32f4/STM32_USB_HOST_Library/Core/src/usbh_stdreq.c +++ /dev/null @@ -1,551 +0,0 @@ -/** - ****************************************************************************** - * @file usbh_stdreq.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief This file implements the standard requests for device enumeration - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ - -#include "usbh_ioreq.h" -#include "usbh_stdreq.h" - -/** @addtogroup USBH_LIB -* @{ -*/ - -/** @addtogroup USBH_LIB_CORE -* @{ -*/ - -/** @defgroup USBH_STDREQ -* @brief This file implements the standard requests for device enumeration -* @{ -*/ - - -/** @defgroup USBH_STDREQ_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_STDREQ_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USBH_STDREQ_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_STDREQ_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USBH_STDREQ_Private_FunctionPrototypes -* @{ -*/ -static void USBH_ParseDevDesc (USBH_DevDesc_TypeDef* , uint8_t *buf, uint16_t length); - -static void USBH_ParseCfgDesc (USBH_CfgDesc_TypeDef* cfg_desc, - USBH_InterfaceDesc_TypeDef* itf_desc, - USBH_EpDesc_TypeDef* ep_desc, - uint8_t *buf, - uint16_t length); -static USBH_DescHeader_t *USBH_GetNextDesc (uint8_t *pbuf, - uint16_t *ptr); - -static void USBH_ParseInterfaceDesc (USBH_InterfaceDesc_TypeDef *if_descriptor, uint8_t *buf); -static void USBH_ParseEPDesc (USBH_EpDesc_TypeDef *ep_descriptor, uint8_t *buf); - -static void USBH_ParseStringDesc (uint8_t* psrc, uint8_t* pdest, uint16_t length); -/** -* @} -*/ - - -/** @defgroup USBH_STDREQ_Private_Functions -* @{ -*/ - - -/** -* @brief USBH_Get_DevDesc -* Issue Get Device Descriptor command to the device. Once the response -* received, it parses the device descriptor and updates the status. -* @param pdev: Selected device -* @param dev_desc: Device Descriptor buffer address -* @param pdev->host.Rx_Buffer: Receive Buffer address -* @param length: Length of the descriptor -* @retval Status -*/ -USBH_Status USBH_Get_DevDesc(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t length) -{ - - USBH_Status status; - - if((status = USBH_GetDescriptor(pdev, - phost, - USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, - USB_DESC_DEVICE, - pdev->host.Rx_Buffer, - length)) == USBH_OK) - { - /* Commands successfully sent and Response Received */ - USBH_ParseDevDesc(&phost->device_prop.Dev_Desc, pdev->host.Rx_Buffer, length); - } - return status; -} - -/** -* @brief USBH_Get_CfgDesc -* Issues Configuration Descriptor to the device. Once the response -* received, it parses the configuartion descriptor and updates the -* status. -* @param pdev: Selected device -* @param cfg_desc: Configuration Descriptor address -* @param itf_desc: Interface Descriptor address -* @param ep_desc: Endpoint Descriptor address -* @param length: Length of the descriptor -* @retval Status -*/ -USBH_Status USBH_Get_CfgDesc(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint16_t length) - -{ - USBH_Status status; - - if((status = USBH_GetDescriptor(pdev, - phost, - USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, - USB_DESC_CONFIGURATION, - pdev->host.Rx_Buffer, - length)) == USBH_OK) - { - /* Commands successfully sent and Response Received */ - USBH_ParseCfgDesc (&phost->device_prop.Cfg_Desc, - phost->device_prop.Itf_Desc, - phost->device_prop.Ep_Desc[0], - pdev->host.Rx_Buffer, - length); - - } - return status; -} - - -/** -* @brief USBH_Get_StringDesc -* Issues string Descriptor command to the device. Once the response -* received, it parses the string descriptor and updates the status. -* @param pdev: Selected device -* @param string_index: String index for the descriptor -* @param buff: Buffer address for the descriptor -* @param length: Length of the descriptor -* @retval Status -*/ -USBH_Status USBH_Get_StringDesc(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t string_index, - uint8_t *buff, - uint16_t length) -{ - USBH_Status status; - - if((status = USBH_GetDescriptor(pdev, - phost, - USB_REQ_RECIPIENT_DEVICE | USB_REQ_TYPE_STANDARD, - USB_DESC_STRING | string_index, - pdev->host.Rx_Buffer, - length)) == USBH_OK) - { - /* Commands successfully sent and Response Received */ - USBH_ParseStringDesc(pdev->host.Rx_Buffer,buff, length); - } - return status; -} - -/** -* @brief USBH_GetDescriptor -* Issues Descriptor command to the device. Once the response received, -* it parses the descriptor and updates the status. -* @param pdev: Selected device -* @param req_type: Descriptor type -* @param value_idx: wValue for the GetDescriptr request -* @param buff: Buffer to store the descriptor -* @param length: Length of the descriptor -* @retval Status -*/ -USBH_Status USBH_GetDescriptor(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t req_type, - uint16_t value_idx, - uint8_t* buff, - uint16_t length ) -{ - phost->Control.setup.b.bmRequestType = USB_D2H | req_type; - phost->Control.setup.b.bRequest = USB_REQ_GET_DESCRIPTOR; - phost->Control.setup.b.wValue.w = value_idx; - - if ((value_idx & 0xff00) == USB_DESC_STRING) - { - phost->Control.setup.b.wIndex.w = 0x0409; - } - else - { - phost->Control.setup.b.wIndex.w = 0; - } - phost->Control.setup.b.wLength.w = length; - return USBH_CtlReq(pdev, phost, buff , length ); -} - -/** -* @brief USBH_SetAddress -* This command sets the address to the connected device -* @param pdev: Selected device -* @param DeviceAddress: Device address to assign -* @retval Status -*/ -USBH_Status USBH_SetAddress(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t DeviceAddress) -{ - phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE | \ - USB_REQ_TYPE_STANDARD; - - phost->Control.setup.b.bRequest = USB_REQ_SET_ADDRESS; - - phost->Control.setup.b.wValue.w = (uint16_t)DeviceAddress; - phost->Control.setup.b.wIndex.w = 0; - phost->Control.setup.b.wLength.w = 0; - - return USBH_CtlReq(pdev, phost, 0 , 0 ); -} - -/** -* @brief USBH_SetCfg -* The command sets the configuration value to the connected device -* @param pdev: Selected device -* @param cfg_idx: Configuration value -* @retval Status -*/ -USBH_Status USBH_SetCfg(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint16_t cfg_idx) -{ - - phost->Control.setup.b.bmRequestType = USB_H2D | USB_REQ_RECIPIENT_DEVICE |\ - USB_REQ_TYPE_STANDARD; - phost->Control.setup.b.bRequest = USB_REQ_SET_CONFIGURATION; - phost->Control.setup.b.wValue.w = cfg_idx; - phost->Control.setup.b.wIndex.w = 0; - phost->Control.setup.b.wLength.w = 0; - - return USBH_CtlReq(pdev, phost, 0 , 0 ); -} - -/** -* @brief USBH_ClrFeature -* This request is used to clear or disable a specific feature. - -* @param pdev: Selected device -* @param ep_num: endpoint number -* @param hc_num: Host channel number -* @retval Status -*/ -USBH_Status USBH_ClrFeature(USB_OTG_CORE_HANDLE *pdev, - USBH_HOST *phost, - uint8_t ep_num, - uint8_t hc_num) -{ - - phost->Control.setup.b.bmRequestType = USB_H2D | - USB_REQ_RECIPIENT_ENDPOINT | - USB_REQ_TYPE_STANDARD; - - phost->Control.setup.b.bRequest = USB_REQ_CLEAR_FEATURE; - phost->Control.setup.b.wValue.w = FEATURE_SELECTOR_ENDPOINT; - phost->Control.setup.b.wIndex.w = ep_num; - phost->Control.setup.b.wLength.w = 0; - - if ((ep_num & USB_REQ_DIR_MASK ) == USB_D2H) - { /* EP Type is IN */ - pdev->host.hc[hc_num].toggle_in = 0; - } - else - {/* EP Type is OUT */ - pdev->host.hc[hc_num].toggle_out = 0; - } - - return USBH_CtlReq(pdev, phost, 0 , 0 ); -} - -/** -* @brief USBH_ParseDevDesc -* This function Parses the device descriptor -* @param dev_desc: device_descriptor destinaton address -* @param buf: Buffer where the source descriptor is available -* @param length: Length of the descriptor -* @retval None -*/ -static void USBH_ParseDevDesc (USBH_DevDesc_TypeDef* dev_desc, - uint8_t *buf, - uint16_t length) -{ - dev_desc->bLength = *(uint8_t *) (buf + 0); - dev_desc->bDescriptorType = *(uint8_t *) (buf + 1); - dev_desc->bcdUSB = LE16 (buf + 2); - dev_desc->bDeviceClass = *(uint8_t *) (buf + 4); - dev_desc->bDeviceSubClass = *(uint8_t *) (buf + 5); - dev_desc->bDeviceProtocol = *(uint8_t *) (buf + 6); - dev_desc->bMaxPacketSize = *(uint8_t *) (buf + 7); - - if (length > 8) - { /* For 1st time after device connection, Host may issue only 8 bytes for - Device Descriptor Length */ - dev_desc->idVendor = LE16 (buf + 8); - dev_desc->idProduct = LE16 (buf + 10); - dev_desc->bcdDevice = LE16 (buf + 12); - dev_desc->iManufacturer = *(uint8_t *) (buf + 14); - dev_desc->iProduct = *(uint8_t *) (buf + 15); - dev_desc->iSerialNumber = *(uint8_t *) (buf + 16); - dev_desc->bNumConfigurations = *(uint8_t *) (buf + 17); - } -} - -/** -* @brief USBH_ParseCfgDesc -* This function Parses the configuration descriptor -* @param cfg_desc: Configuration Descriptor address -* @param itf_desc: Interface Descriptor address -* @param ep_desc: Endpoint Descriptor address -* @param buf: Buffer where the source descriptor is available -* @param length: Length of the descriptor -* @retval None -*/ -static void USBH_ParseCfgDesc (USBH_CfgDesc_TypeDef* cfg_desc, - USBH_InterfaceDesc_TypeDef* itf_desc, - USBH_EpDesc_TypeDef* ep_desc, - uint8_t *buf, - uint16_t length) -{ - USBH_InterfaceDesc_TypeDef *pif ; - USBH_EpDesc_TypeDef *pep; - USBH_DescHeader_t *pdesc = (USBH_DescHeader_t *)buf; - uint16_t ptr; - int8_t if_ix; - int8_t ep_ix; - - pdesc = (USBH_DescHeader_t *)buf; - - /* Parse configuration descriptor */ - cfg_desc->bLength = *(uint8_t *) (buf + 0); - cfg_desc->bDescriptorType = *(uint8_t *) (buf + 1); - cfg_desc->wTotalLength = LE16 (buf + 2); - cfg_desc->bNumInterfaces = *(uint8_t *) (buf + 4); - cfg_desc->bConfigurationValue = *(uint8_t *) (buf + 5); - cfg_desc->iConfiguration = *(uint8_t *) (buf + 6); - cfg_desc->bmAttributes = *(uint8_t *) (buf + 7); - cfg_desc->bMaxPower = *(uint8_t *) (buf + 8); - - - if (length > USB_CONFIGURATION_DESC_SIZE) - { - ptr = USB_LEN_CFG_DESC; - - if ( cfg_desc->bNumInterfaces <= USBH_MAX_NUM_INTERFACES) - { - if_ix = 0; - pif = (USBH_InterfaceDesc_TypeDef *)0; - - /* Parse Interface descriptor relative to the current configuration */ - if(cfg_desc->bNumInterfaces <= USBH_MAX_NUM_INTERFACES) - { - while (if_ix < cfg_desc->bNumInterfaces) - { - pdesc = USBH_GetNextDesc((uint8_t *)pdesc, &ptr); - if (pdesc->bDescriptorType == USB_DESC_TYPE_INTERFACE) - { - pif = &itf_desc[if_ix]; - USBH_ParseInterfaceDesc (pif, (uint8_t *)pdesc); - ep_ix = 0; - - /* Parse Ep descriptors relative to the current interface */ - if(pif->bNumEndpoints <= USBH_MAX_NUM_ENDPOINTS) - { - while (ep_ix < pif->bNumEndpoints) - { - pdesc = USBH_GetNextDesc((void* )pdesc, &ptr); - if (pdesc->bDescriptorType == USB_DESC_TYPE_ENDPOINT) - { - pep = &ep_desc[ep_ix]; - USBH_ParseEPDesc (pep, (uint8_t *)pdesc); - ep_ix++; - } - else - { - ptr += pdesc->bLength; - } - } - } - if_ix++; - } - else - { - ptr += pdesc->bLength; - } - } - } - } - } -} - - -/** -* @brief USBH_ParseInterfaceDesc -* This function Parses the interface descriptor -* @param if_descriptor : Interface descriptor destination -* @param buf: Buffer where the descriptor data is available -* @retval None -*/ -static void USBH_ParseInterfaceDesc (USBH_InterfaceDesc_TypeDef *if_descriptor, - uint8_t *buf) -{ - if_descriptor->bLength = *(uint8_t *) (buf + 0); - if_descriptor->bDescriptorType = *(uint8_t *) (buf + 1); - if_descriptor->bInterfaceNumber = *(uint8_t *) (buf + 2); - if_descriptor->bAlternateSetting = *(uint8_t *) (buf + 3); - if_descriptor->bNumEndpoints = *(uint8_t *) (buf + 4); - if_descriptor->bInterfaceClass = *(uint8_t *) (buf + 5); - if_descriptor->bInterfaceSubClass = *(uint8_t *) (buf + 6); - if_descriptor->bInterfaceProtocol = *(uint8_t *) (buf + 7); - if_descriptor->iInterface = *(uint8_t *) (buf + 8); -} - -/** -* @brief USBH_ParseEPDesc -* This function Parses the endpoint descriptor -* @param ep_descriptor: Endpoint descriptor destination address -* @param buf: Buffer where the parsed descriptor stored -* @retval None -*/ -static void USBH_ParseEPDesc (USBH_EpDesc_TypeDef *ep_descriptor, - uint8_t *buf) -{ - - ep_descriptor->bLength = *(uint8_t *) (buf + 0); - ep_descriptor->bDescriptorType = *(uint8_t *) (buf + 1); - ep_descriptor->bEndpointAddress = *(uint8_t *) (buf + 2); - ep_descriptor->bmAttributes = *(uint8_t *) (buf + 3); - ep_descriptor->wMaxPacketSize = LE16 (buf + 4); - ep_descriptor->bInterval = *(uint8_t *) (buf + 6); -} - -/** -* @brief USBH_ParseStringDesc -* This function Parses the string descriptor -* @param psrc: Source pointer containing the descriptor data -* @param pdest: Destination address pointer -* @param length: Length of the descriptor -* @retval None -*/ -static void USBH_ParseStringDesc (uint8_t* psrc, - uint8_t* pdest, - uint16_t length) -{ - uint16_t strlength; - uint16_t idx; - - /* The UNICODE string descriptor is not NULL-terminated. The string length is - computed by substracting two from the value of the first byte of the descriptor. - */ - - /* Check which is lower size, the Size of string or the length of bytes read - from the device */ - - if ( psrc[1] == USB_DESC_TYPE_STRING) - { /* Make sure the Descriptor is String Type */ - - /* psrc[0] contains Size of Descriptor, subtract 2 to get the length of string */ - strlength = ( ( (psrc[0]-2) <= length) ? (psrc[0]-2) :length); - psrc += 2; /* Adjust the offset ignoring the String Len and Descriptor type */ - - for (idx = 0; idx < strlength; idx+=2 ) - {/* Copy Only the string and ignore the UNICODE ID, hence add the src */ - *pdest = psrc[idx]; - pdest++; - } - *pdest = 0; /* mark end of string */ - } -} - -/** -* @brief USBH_GetNextDesc -* This function return the next descriptor header -* @param buf: Buffer where the cfg descriptor is available -* @param ptr: data popinter inside the cfg descriptor -* @retval next header -*/ -static USBH_DescHeader_t *USBH_GetNextDesc (uint8_t *pbuf, uint16_t *ptr) -{ - USBH_DescHeader_t *pnext; - - *ptr += ((USBH_DescHeader_t *)pbuf)->bLength; - pnext = (USBH_DescHeader_t *)((uint8_t *)pbuf + \ - ((USBH_DescHeader_t *)pbuf)->bLength); - - return(pnext); -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - - - - diff --git a/example/stm32f4/STM32_USB_OTG_Driver/Release_Notes.html b/example/stm32f4/STM32_USB_OTG_Driver/Release_Notes.html deleted file mode 100644 index 17d2a0832..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/Release_Notes.html +++ /dev/null @@ -1,941 +0,0 @@ - - - - - - - - -Release Notes for STM32F105/7xx and STM32F2xx USB OTG Driver - - - - - -
- -

 

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Back to Release page

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Release Notes for STM32F105/7xx and STM32F2xx USB OTG Driver

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Copyright - 2011 STMicroelectronics

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Contents

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  1. STM32F105/7xx and STM32F2xx USB OTG Driver update History
    2. -
  2. License
    3. -
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STM32F105/7xx and STM32F2xx USB OTG Driver  update History

V2.0.0 / 22-July-2011

Main -Changes

-
  • Second official version supporting STM32F105/7 and STM32F2xx devices
  • Rename the Library from "STM32_USB_HOST_Driver" to "STM32_USB_OTG_Driver"
  • Add support for STM32F2xx devices
  • Add support for Device and OTG modes
  • Change HCD layer to support High speed core
  • Change the Low level driver to support multi core support for Host mode
  • Add Stop mechanism for Host and Device modes
  • Change VBUS enabling method, to use the external or the internal VBUS when using the ULPI

V1.0.0 - 11/29/2010

-
  • Created 

License

-

The use of this STM32 software is governed by the terms and conditions of the License Agreement "MCD-ST Liberty SW License Agreement 20Jul2011 v0.1.pdf" available in the root of this package. 

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For - complete documentation on STM32(CORTEX M3) 32-Bit - Microcontrollers visit www.st.com/STM32

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- -
- - \ No newline at end of file diff --git a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_bsp.h b/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_bsp.h deleted file mode 100644 index 0e7c12eef..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_bsp.h +++ /dev/null @@ -1,97 +0,0 @@ -/** - ****************************************************************************** - * @file usb_bsp.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Specific api's relative to the used hardware platform - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_BSP__H__ -#define __USB_BSP__H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" -#include "stm32f4_discovery.h" - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_BSP - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_BSP_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_BSP_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_BSP_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_BSP_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_BSP_Exported_FunctionsPrototype - * @{ - */ -void BSP_Init(void); - -void USB_OTG_BSP_Init (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_BSP_uDelay (const uint32_t usec); -void USB_OTG_BSP_mDelay (const uint32_t msec); -void USB_OTG_BSP_EnableInterrupt (USB_OTG_CORE_HANDLE *pdev); -#ifdef USE_HOST_MODE -void USB_OTG_BSP_ConfigVBUS(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_BSP_DriveVBUS(USB_OTG_CORE_HANDLE *pdev,uint8_t state); -#endif -/** - * @} - */ - -#endif //__USB_BSP__H__ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_conf_template.h b/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_conf_template.h deleted file mode 100644 index 39b35529e..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_conf_template.h +++ /dev/null @@ -1,287 +0,0 @@ -/** - ****************************************************************************** - * @file usb_conf.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief general low level driver configuration - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_CONF__H__ -#define __USB_CONF__H__ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_CONF - * @brief USB low level driver configuration file - * @{ - */ - -/** @defgroup USB_CONF_Exported_Defines - * @{ - */ - -/* USB Core and PHY interface configuration. - Tip: To avoid modifying these defines each time you need to change the USB - configuration, you can declare the needed define in your toolchain - compiler preprocessor. - */ -#ifndef USE_USB_OTG_FS - //#define USE_USB_OTG_FS -#endif /* USE_USB_OTG_FS */ - -#ifndef USE_USB_OTG_HS - //#define USE_USB_OTG_HS -#endif /* USE_USB_OTG_HS */ - -#ifndef USE_ULPI_PHY - //#define USE_ULPI_PHY -#endif /* USE_ULPI_PHY */ - -#ifndef USE_EMBEDDED_PHY - //#define USE_EMBEDDED_PHY -#endif /* USE_EMBEDDED_PHY */ - -#ifndef USE_I2C_PHY - //#define USE_I2C_PHY -#endif /* USE_I2C_PHY */ - - -#ifdef USE_USB_OTG_FS - #define USB_OTG_FS_CORE -#endif - -#ifdef USE_USB_OTG_HS - #define USB_OTG_HS_CORE -#endif - -/******************************************************************************* -* FIFO Size Configuration in Device mode -* -* (i) Receive data FIFO size = RAM for setup packets + -* OUT endpoint control information + -* data OUT packets + miscellaneous -* Space = ONE 32-bits words -* --> RAM for setup packets = 10 spaces -* (n is the nbr of CTRL EPs the device core supports) -* --> OUT EP CTRL info = 1 space -* (one space for status information written to the FIFO along with each -* received packet) -* --> data OUT packets = (Largest Packet Size / 4) + 1 spaces -* (MINIMUM to receive packets) -* --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces -* (if high-bandwidth EP is enabled or multiple isochronous EPs) -* --> miscellaneous = 1 space per OUT EP -* (one space for transfer complete status information also pushed to the -* FIFO with each endpoint's last packet) -* -* (ii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for -* that particular IN EP. More space allocated in the IN EP Tx FIFO results -* in a better performance on the USB and can hide latencies on the AHB. -* -* (iii) TXn min size = 16 words. (n : Transmit FIFO index) -* (iv) When a TxFIFO is not used, the Configuration should be as follows: -* case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) -* --> Txm can use the space allocated for Txn. -* case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) -* --> Txn should be configured with the minimum space of 16 words -* (v) The FIFO is used optimally when used TxFIFOs are allocated in the top -* of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. -*******************************************************************************/ - -/******************************************************************************* -* FIFO Size Configuration in Host mode -* -* (i) Receive data FIFO size = (Largest Packet Size / 4) + 1 or -* 2x (Largest Packet Size / 4) + 1, If a -* high-bandwidth channel or multiple isochronous -* channels are enabled -* -* (ii) For the host nonperiodic Transmit FIFO is the largest maximum packet size -* for all supported nonperiodic OUT channels. Typically, a space -* corresponding to two Largest Packet Size is recommended. -* -* (iii) The minimum amount of RAM required for Host periodic Transmit FIFO is -* the largest maximum packet size for all supported periodic OUT channels. -* If there is at least one High Bandwidth Isochronous OUT endpoint, -* then the space must be at least two times the maximum packet size for -* that channel. -*******************************************************************************/ - -/****************** USB OTG HS CONFIGURATION **********************************/ -#ifdef USB_OTG_HS_CORE - #define RX_FIFO_HS_SIZE 512 - #define TX0_FIFO_HS_SIZE 512 - #define TX1_FIFO_HS_SIZE 512 - #define TX2_FIFO_HS_SIZE 0 - #define TX3_FIFO_HS_SIZE 0 - #define TX4_FIFO_HS_SIZE 0 - #define TX5_FIFO_HS_SIZE 0 - #define TXH_NP_HS_FIFOSIZ 96 - #define TXH_P_HS_FIFOSIZ 96 - - //#define USB_OTG_HS_LOW_PWR_MGMT_SUPPORT - //#define USB_OTG_HS_SOF_OUTPUT_ENABLED - - //#define USB_OTG_INTERNAL_VBUS_ENABLED - #define USB_OTG_EXTERNAL_VBUS_ENABLED - - #ifdef USE_ULPI_PHY - #define USB_OTG_ULPI_PHY_ENABLED - #endif - #ifdef USE_EMBEDDED_PHY - #define USB_OTG_EMBEDDED_PHY_ENABLED - #endif - #ifdef USE_I2C_PHY - #define USB_OTG_I2C_PHY_ENABLED - #endif - #define USB_OTG_HS_INTERNAL_DMA_ENABLED - #define USB_OTG_HS_DEDICATED_EP1_ENABLED -#endif - -/****************** USB OTG FS CONFIGURATION **********************************/ -#ifdef USB_OTG_FS_CORE - #define RX_FIFO_FS_SIZE 128 - #define TX0_FIFO_FS_SIZE 64 - #define TX1_FIFO_FS_SIZE 128 - #define TX2_FIFO_FS_SIZE 0 - #define TX3_FIFO_FS_SIZE 0 - #define TXH_NP_HS_FIFOSIZ 96 - #define TXH_P_HS_FIFOSIZ 96 - - //#define USB_OTG_FS_LOW_PWR_MGMT_SUPPORT - //#define USB_OTG_FS_SOF_OUTPUT_ENABLED -#endif - -/****************** USB OTG MODE CONFIGURATION ********************************/ -//#define USE_HOST_MODE -#define USE_DEVICE_MODE -//#define USE_OTG_MODE - - -#ifndef USB_OTG_FS_CORE - #ifndef USB_OTG_HS_CORE - #error "USB_OTG_HS_CORE or USB_OTG_FS_CORE should be defined" - #endif -#endif - - -#ifndef USE_DEVICE_MODE - #ifndef USE_HOST_MODE - #error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" - #endif -#endif - -#ifndef USE_USB_OTG_HS - #ifndef USE_USB_OTG_FS - #error "USE_USB_OTG_HS or USE_USB_OTG_FS should be defined" - #endif -#else //USE_USB_OTG_HS - #ifndef USE_ULPI_PHY - #ifndef USE_EMBEDDED_PHY - #ifndef USE_I2C_PHY - #error "USE_ULPI_PHY or USE_EMBEDDED_PHY or USE_I2C_PHY should be defined" - #endif - #endif - #endif -#endif - -/****************** C Compilers dependant keywords ****************************/ -/* In HS mode and when the DMA is used, all variables and data structures dealing - with the DMA during the transaction process should be 4-bytes aligned */ -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - #if defined (__GNUC__) /* GNU Compiler */ - #define __ALIGN_END __attribute__ ((aligned (4))) - #define __ALIGN_BEGIN - #else - #define __ALIGN_END - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #elif defined (__TASKING__) /* TASKING Compiler */ - #define __ALIGN_BEGIN __align(4) - #endif /* __CC_ARM */ - #endif /* __GNUC__ */ -#else - #define __ALIGN_BEGIN - #define __ALIGN_END -#endif /* USB_OTG_HS_INTERNAL_DMA_ENABLED */ - -/* __packed keyword used to decrease the data type alignment to 1-byte */ -#if defined (__CC_ARM) /* ARM Compiler */ - #define __packed __packed -#elif defined (__ICCARM__) /* IAR Compiler */ - #define __packed __packed -#elif defined ( __GNUC__ ) /* GNU Compiler */ - #define __packed __attribute__ ((__packed__)) -#elif defined (__TASKING__) /* TASKING Compiler */ - #define __packed __unaligned -#endif /* __CC_ARM */ - -/** - * @} - */ - - -/** @defgroup USB_CONF_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_CONF_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CONF_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CONF_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif //__USB_CONF__H__ - - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_core.h b/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_core.h deleted file mode 100644 index 82a09e15c..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_core.h +++ /dev/null @@ -1,408 +0,0 @@ -/** - ****************************************************************************** - * @file usb_core.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Header of the Core Layer - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_CORE_H__ -#define __USB_CORE_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" -#include "usb_regs.h" -#include "usb_defines.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_CORE - * @brief usb otg driver core layer - * @{ - */ - - -/** @defgroup USB_CORE_Exported_Defines - * @{ - */ - -#define USB_OTG_EP0_IDLE 0 -#define USB_OTG_EP0_SETUP 1 -#define USB_OTG_EP0_DATA_IN 2 -#define USB_OTG_EP0_DATA_OUT 3 -#define USB_OTG_EP0_STATUS_IN 4 -#define USB_OTG_EP0_STATUS_OUT 5 -#define USB_OTG_EP0_STALL 6 - -#define USB_OTG_EP_TX_DIS 0x0000 -#define USB_OTG_EP_TX_STALL 0x0010 -#define USB_OTG_EP_TX_NAK 0x0020 -#define USB_OTG_EP_TX_VALID 0x0030 - -#define USB_OTG_EP_RX_DIS 0x0000 -#define USB_OTG_EP_RX_STALL 0x1000 -#define USB_OTG_EP_RX_NAK 0x2000 -#define USB_OTG_EP_RX_VALID 0x3000 -/** - * @} - */ -#define MAX_DATA_LENGTH 0xFF - -/** @defgroup USB_CORE_Exported_Types - * @{ - */ - - -typedef enum { - USB_OTG_OK = 0, - USB_OTG_FAIL -}USB_OTG_STS; - -typedef enum { - HC_IDLE = 0, - HC_XFRC, - HC_HALTED, - HC_NAK, - HC_NYET, - HC_STALL, - HC_XACTERR, - HC_BBLERR, - HC_DATATGLERR, -}HC_STATUS; - -typedef enum { - URB_IDLE = 0, - URB_DONE, - URB_NOTREADY, - URB_ERROR, - URB_STALL -}URB_STATE; - -typedef enum { - CTRL_START = 0, - CTRL_XFRC, - CTRL_HALTED, - CTRL_NAK, - CTRL_STALL, - CTRL_XACTERR, - CTRL_BBLERR, - CTRL_DATATGLERR, - CTRL_FAIL -}CTRL_STATUS; - - -typedef struct USB_OTG_hc -{ - uint8_t dev_addr ; - uint8_t ep_num; - uint8_t ep_is_in; - uint8_t speed; - uint8_t do_ping; - uint8_t ep_type; - uint16_t max_packet; - uint8_t data_pid; - uint8_t *xfer_buff; - uint32_t xfer_len; - uint32_t xfer_count; - uint8_t toggle_in; - uint8_t toggle_out; - uint32_t dma_addr; -} -USB_OTG_HC , *PUSB_OTG_HC; - -typedef struct USB_OTG_ep -{ - uint8_t num; - uint8_t is_in; - uint8_t is_stall; - uint8_t type; - uint8_t data_pid_start; - uint8_t even_odd_frame; - uint16_t tx_fifo_num; - uint32_t maxpacket; - /* transaction level variables*/ - uint8_t *xfer_buff; - uint32_t dma_addr; - uint32_t xfer_len; - uint32_t xfer_count; - /* Transfer level variables*/ - uint32_t rem_data_len; - uint32_t total_data_len; - uint32_t ctl_data_len; - -} - -USB_OTG_EP , *PUSB_OTG_EP; - - - -typedef struct USB_OTG_core_cfg -{ - uint8_t host_channels; - uint8_t dev_endpoints; - uint8_t speed; - uint8_t dma_enable; - uint16_t mps; - uint16_t TotalFifoSize; - uint8_t phy_itface; - uint8_t Sof_output; - uint8_t low_power; - uint8_t coreID; - -} -USB_OTG_CORE_CFGS, *PUSB_OTG_CORE_CFGS; - - - -typedef struct usb_setup_req { - - uint8_t bmRequest; - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; -} USB_SETUP_REQ; - -typedef struct _Device_TypeDef -{ - uint8_t *(*GetDeviceDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetLangIDStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetManufacturerStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetProductStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetSerialStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetConfigurationStrDescriptor)( uint8_t speed , uint16_t *length); - uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length); -} USBD_DEVICE, *pUSBD_DEVICE; - -typedef struct USB_OTG_hPort -{ - void (*Disconnect) (void *phost); - void (*Connect) (void *phost); - uint8_t ConnStatus; - uint8_t DisconnStatus; - uint8_t ConnHandled; - uint8_t DisconnHandled; -} USB_OTG_hPort_TypeDef; - -typedef struct _Device_cb -{ - uint8_t (*Init) (void *pdev , uint8_t cfgidx); - uint8_t (*DeInit) (void *pdev , uint8_t cfgidx); - /* Control Endpoints*/ - uint8_t (*Setup) (void *pdev , USB_SETUP_REQ *req); - uint8_t (*EP0_TxSent) (void *pdev ); - uint8_t (*EP0_RxReady) (void *pdev ); - /* Class Specific Endpoints*/ - uint8_t (*DataIn) (void *pdev , uint8_t epnum); - uint8_t (*DataOut) (void *pdev , uint8_t epnum); - uint8_t (*SOF) (void *pdev); - uint8_t (*IsoINIncomplete) (void *pdev); - uint8_t (*IsoOUTIncomplete) (void *pdev); - - uint8_t *(*GetConfigDescriptor)( uint8_t speed , uint16_t *length); -#ifdef USB_OTG_HS_CORE - uint8_t *(*GetOtherConfigDescriptor)( uint8_t speed , uint16_t *length); -#endif - -#ifdef USB_SUPPORT_USER_STRING_DESC - uint8_t *(*GetUsrStrDescriptor)( uint8_t speed ,uint8_t index, uint16_t *length); -#endif - -} USBD_Class_cb_TypeDef; - - - -typedef struct _USBD_USR_PROP -{ - void (*Init)(void); - void (*DeviceReset)(uint8_t speed); - void (*DeviceConfigured)(void); - void (*DeviceSuspended)(void); - void (*DeviceResumed)(void); - - void (*DeviceConnected)(void); - void (*DeviceDisconnected)(void); - -} -USBD_Usr_cb_TypeDef; - -typedef struct _DCD -{ - uint8_t device_config; - uint8_t device_state; - uint8_t device_status; - uint8_t device_address; - uint32_t DevRemoteWakeup; - USB_OTG_EP in_ep [USB_OTG_MAX_TX_FIFOS]; - USB_OTG_EP out_ep [USB_OTG_MAX_TX_FIFOS]; - uint8_t setup_packet [8*3]; - USBD_Class_cb_TypeDef *class_cb; - USBD_Usr_cb_TypeDef *usr_cb; - USBD_DEVICE *usr_device; - uint8_t *pConfig_descriptor; - } -DCD_DEV , *DCD_PDEV; - - -typedef struct _HCD -{ - uint8_t Rx_Buffer [MAX_DATA_LENGTH]; - __IO uint32_t ConnSts; - __IO uint32_t ErrCnt[USB_OTG_MAX_TX_FIFOS]; - __IO uint32_t XferCnt[USB_OTG_MAX_TX_FIFOS]; - __IO HC_STATUS HC_Status[USB_OTG_MAX_TX_FIFOS]; - __IO URB_STATE URB_State[USB_OTG_MAX_TX_FIFOS]; - USB_OTG_HC hc [USB_OTG_MAX_TX_FIFOS]; - uint16_t channel [USB_OTG_MAX_TX_FIFOS]; - USB_OTG_hPort_TypeDef *port_cb; -} -HCD_DEV , *USB_OTG_USBH_PDEV; - - -typedef struct _OTG -{ - uint8_t OTG_State; - uint8_t OTG_PrevState; - uint8_t OTG_Mode; -} -OTG_DEV , *USB_OTG_USBO_PDEV; - -typedef struct USB_OTG_handle -{ - USB_OTG_CORE_CFGS cfg; - USB_OTG_CORE_REGS regs; -#ifdef USE_DEVICE_MODE - DCD_DEV dev; -#endif -#ifdef USE_HOST_MODE - HCD_DEV host; -#endif -#ifdef USE_OTG_MODE - OTG_DEV otg; -#endif -} -USB_OTG_CORE_HANDLE , *PUSB_OTG_CORE_HANDLE; - -/** - * @} - */ - - -/** @defgroup USB_CORE_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_CORE_Exported_FunctionsPrototype - * @{ - */ - - -USB_OTG_STS USB_OTG_CoreInit (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_SelectCore (USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID); -USB_OTG_STS USB_OTG_EnableGlobalInt (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev); -void* USB_OTG_ReadPacket (USB_OTG_CORE_HANDLE *pdev , - uint8_t *dest, - uint16_t len); -USB_OTG_STS USB_OTG_WritePacket (USB_OTG_CORE_HANDLE *pdev , - uint8_t *src, - uint8_t ch_ep_num, - uint16_t len); -USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num); -USB_OTG_STS USB_OTG_FlushRxFifo (USB_OTG_CORE_HANDLE *pdev); - -uint32_t USB_OTG_ReadCoreItr (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev); -uint8_t USB_OTG_IsHostMode (USB_OTG_CORE_HANDLE *pdev); -uint8_t USB_OTG_IsDeviceMode (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_GetMode (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_PhyInit (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_SetCurrentMode (USB_OTG_CORE_HANDLE *pdev, - uint8_t mode); - -/*********************** HOST APIs ********************************************/ -#ifdef USE_HOST_MODE -USB_OTG_STS USB_OTG_CoreInitHost (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EnableHostInt (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_HC_Init (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); -USB_OTG_STS USB_OTG_HC_Halt (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); -USB_OTG_STS USB_OTG_HC_StartXfer (USB_OTG_CORE_HANDLE *pdev, uint8_t hc_num); -USB_OTG_STS USB_OTG_HC_DoPing (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num); -uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ResetPort (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadHPRT0 (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state); -void USB_OTG_InitFSLSPClkSel (USB_OTG_CORE_HANDLE *pdev ,uint8_t freq); -uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) ; -void USB_OTG_StopHost (USB_OTG_CORE_HANDLE *pdev); -#endif -/********************* DEVICE APIs ********************************************/ -#ifdef USE_DEVICE_MODE -USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EnableDevInt (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev); -enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EP0Activate (USB_OTG_CORE_HANDLE *pdev); -USB_OTG_STS USB_OTG_EPActivate (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPStartXfer (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPSetStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -USB_OTG_STS USB_OTG_EPClearStall (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep); -uint32_t USB_OTG_ReadDevAllOutEp_itr (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_ReadDevOutEP_itr (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); -uint32_t USB_OTG_ReadDevAllInEPItr (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_InitDevSpeed (USB_OTG_CORE_HANDLE *pdev , uint8_t speed); -uint8_t USBH_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev); -void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status); -uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep); -#endif -/** - * @} - */ - -#endif /* __USB_CORE_H__ */ - - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_dcd.h b/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_dcd.h deleted file mode 100644 index 6bfd89939..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_dcd.h +++ /dev/null @@ -1,158 +0,0 @@ -/** - ****************************************************************************** - * @file usb_dcd.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Peripheral Driver Header file - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __DCD_H__ -#define __DCD_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" - - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_DCD -* @brief This file is the -* @{ -*/ - - -/** @defgroup USB_DCD_Exported_Defines -* @{ -*/ -#define USB_OTG_EP_CONTROL 0 -#define USB_OTG_EP_ISOC 1 -#define USB_OTG_EP_BULK 2 -#define USB_OTG_EP_INT 3 -#define USB_OTG_EP_MASK 3 - -/* Device Status */ -#define USB_OTG_DEFAULT 1 -#define USB_OTG_ADDRESSED 2 -#define USB_OTG_CONFIGURED 3 -#define USB_OTG_SUSPENDED 4 - -/** -* @} -*/ - - -/** @defgroup USB_DCD_Exported_Types -* @{ -*/ -/******************************************************************************** -Data structure type -********************************************************************************/ -typedef struct -{ - uint8_t bLength; - uint8_t bDescriptorType; - uint8_t bEndpointAddress; - uint8_t bmAttributes; - uint16_t wMaxPacketSize; - uint8_t bInterval; -} -EP_DESCRIPTOR , *PEP_DESCRIPTOR; - -/** -* @} -*/ - - -/** @defgroup USB_DCD_Exported_Macros -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USB_DCD_Exported_Variables -* @{ -*/ -/** -* @} -*/ - -/** @defgroup USB_DCD_Exported_FunctionsPrototype -* @{ -*/ -/******************************************************************************** -EXPORTED FUNCTION FROM THE USB-OTG LAYER -********************************************************************************/ -void DCD_Init(USB_OTG_CORE_HANDLE *pdev , - USB_OTG_CORE_ID_TypeDef coreID); - -void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev); -void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev); -void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, - uint8_t address); -uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev , - uint8_t ep_addr, - uint16_t ep_mps, - uint8_t ep_type); - -uint32_t DCD_EP_Close (USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr); - - -uint32_t DCD_EP_PrepareRx ( USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t buf_len); - -uint32_t DCD_EP_Tx (USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint32_t buf_len); -uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev, - uint8_t epnum); -uint32_t DCD_Handle_ISR(USB_OTG_CORE_HANDLE *pdev); - -uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev , - uint8_t epnum); - -void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , - uint8_t epnum , - uint32_t Status); - -/** -* @} -*/ - - -#endif //__DCD_H__ - - -/** -* @} -*/ - -/** -* @} -*/ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_dcd_int.h b/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_dcd_int.h deleted file mode 100644 index 9df1a4172..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_dcd_int.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - ****************************************************************************** - * @file usb_dcd_int.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Peripheral Device Interface Layer - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef USB_DCD_INT_H__ -#define USB_DCD_INT_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd.h" - - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_DCD_INT - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_DCD_INT_Exported_Defines - * @{ - */ - -typedef struct _USBD_DCD_INT -{ - uint8_t (* DataOutStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); - uint8_t (* DataInStage) (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum); - uint8_t (* SetupStage) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* SOF) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* Reset) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* Suspend) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* Resume) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* IsoINIncomplete) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* IsoOUTIncomplete) (USB_OTG_CORE_HANDLE *pdev); - - uint8_t (* DevConnected) (USB_OTG_CORE_HANDLE *pdev); - uint8_t (* DevDisconnected) (USB_OTG_CORE_HANDLE *pdev); - -}USBD_DCD_INT_cb_TypeDef; - -extern USBD_DCD_INT_cb_TypeDef *USBD_DCD_INT_fops; -/** - * @} - */ - - -/** @defgroup USB_DCD_INT_Exported_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DCD_INT_Exported_Macros - * @{ - */ - -#define CLEAR_IN_EP_INTR(epnum,intr) \ - diepint.d32=0; \ - diepint.b.intr = 1; \ - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT,diepint.d32); - -#define CLEAR_OUT_EP_INTR(epnum,intr) \ - doepint.d32=0; \ - doepint.b.intr = 1; \ - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT,doepint.d32); - -/** - * @} - */ - -/** @defgroup USB_DCD_INT_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DCD_INT_Exported_FunctionsPrototype - * @{ - */ - -uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); - -/** - * @} - */ - - -#endif // USB_DCD_INT_H__ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_defines.h b/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_defines.h deleted file mode 100644 index b119c2586..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_defines.h +++ /dev/null @@ -1,244 +0,0 @@ -/** - ****************************************************************************** - * @file usb_defines.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Header of the Core Layer - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_DEF_H__ -#define __USB_DEF_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_DEFINES - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_DEFINES_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup _CORE_DEFINES_ - * @{ - */ - -#define USB_OTG_SPEED_PARAM_HIGH 0 -#define USB_OTG_SPEED_PARAM_HIGH_IN_FULL 1 -#define USB_OTG_SPEED_PARAM_FULL 3 - -#define USB_OTG_SPEED_HIGH 0 -#define USB_OTG_SPEED_FULL 1 - -#define USB_OTG_ULPI_PHY 1 -#define USB_OTG_EMBEDDED_PHY 2 -#define USB_OTG_I2C_PHY 3 - -/** - * @} - */ - - -/** @defgroup _GLOBAL_DEFINES_ - * @{ - */ -#define GAHBCFG_TXFEMPTYLVL_EMPTY 1 -#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 -#define GAHBCFG_GLBINT_ENABLE 1 -#define GAHBCFG_INT_DMA_BURST_SINGLE 0 -#define GAHBCFG_INT_DMA_BURST_INCR 1 -#define GAHBCFG_INT_DMA_BURST_INCR4 3 -#define GAHBCFG_INT_DMA_BURST_INCR8 5 -#define GAHBCFG_INT_DMA_BURST_INCR16 7 -#define GAHBCFG_DMAENABLE 1 -#define GAHBCFG_TXFEMPTYLVL_EMPTY 1 -#define GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 -#define GRXSTS_PKTSTS_IN 2 -#define GRXSTS_PKTSTS_IN_XFER_COMP 3 -#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5 -#define GRXSTS_PKTSTS_CH_HALTED 7 -/** - * @} - */ - - -/** @defgroup _OnTheGo_DEFINES_ - * @{ - */ -#define MODE_HNP_SRP_CAPABLE 0 -#define MODE_SRP_ONLY_CAPABLE 1 -#define MODE_NO_HNP_SRP_CAPABLE 2 -#define MODE_SRP_CAPABLE_DEVICE 3 -#define MODE_NO_SRP_CAPABLE_DEVICE 4 -#define MODE_SRP_CAPABLE_HOST 5 -#define MODE_NO_SRP_CAPABLE_HOST 6 -#define A_HOST 1 -#define A_SUSPEND 2 -#define A_PERIPHERAL 3 -#define B_PERIPHERAL 4 -#define B_HOST 5 -#define DEVICE_MODE 0 -#define HOST_MODE 1 -#define OTG_MODE 2 -/** - * @} - */ - - -/** @defgroup __DEVICE_DEFINES_ - * @{ - */ -#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 -#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 -#define DSTS_ENUMSPD_LS_PHY_6MHZ 2 -#define DSTS_ENUMSPD_FS_PHY_48MHZ 3 - -#define DCFG_FRAME_INTERVAL_80 0 -#define DCFG_FRAME_INTERVAL_85 1 -#define DCFG_FRAME_INTERVAL_90 2 -#define DCFG_FRAME_INTERVAL_95 3 - -#define DEP0CTL_MPS_64 0 -#define DEP0CTL_MPS_32 1 -#define DEP0CTL_MPS_16 2 -#define DEP0CTL_MPS_8 3 - -#define EP_SPEED_LOW 0 -#define EP_SPEED_FULL 1 -#define EP_SPEED_HIGH 2 - -#define EP_TYPE_CTRL 0 -#define EP_TYPE_ISOC 1 -#define EP_TYPE_BULK 2 -#define EP_TYPE_INTR 3 -#define EP_TYPE_MSK 3 - -#define STS_GOUT_NAK 1 -#define STS_DATA_UPDT 2 -#define STS_XFER_COMP 3 -#define STS_SETUP_COMP 4 -#define STS_SETUP_UPDT 6 -/** - * @} - */ - - -/** @defgroup __HOST_DEFINES_ - * @{ - */ -#define HC_PID_DATA0 0 -#define HC_PID_DATA2 1 -#define HC_PID_DATA1 2 -#define HC_PID_SETUP 3 - -#define HPRT0_PRTSPD_HIGH_SPEED 0 -#define HPRT0_PRTSPD_FULL_SPEED 1 -#define HPRT0_PRTSPD_LOW_SPEED 2 - -#define HCFG_30_60_MHZ 0 -#define HCFG_48_MHZ 1 -#define HCFG_6_MHZ 2 - -#define HCCHAR_CTRL 0 -#define HCCHAR_ISOC 1 -#define HCCHAR_BULK 2 -#define HCCHAR_INTR 3 - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -/** - * @} - */ - - -/** @defgroup USB_DEFINES_Exported_Types - * @{ - */ - -typedef enum -{ - USB_OTG_HS_CORE_ID = 0, - USB_OTG_FS_CORE_ID = 1 -}USB_OTG_CORE_ID_TypeDef; -/** - * @} - */ - - -/** @defgroup USB_DEFINES_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DEFINES_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_DEFINES_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -/** @defgroup Internal_Macro's - * @{ - */ -#define USB_OTG_READ_REG32(reg) (*(__IO uint32_t *)reg) -#define USB_OTG_WRITE_REG32(reg,value) (*(__IO uint32_t *)reg = value) -#define USB_OTG_MODIFY_REG32(reg,clear_mask,set_mask) \ - USB_OTG_WRITE_REG32(reg, (((USB_OTG_READ_REG32(reg)) & ~clear_mask) | set_mask ) ) - -/******************************************************************************** - ENUMERATION TYPE -********************************************************************************/ -enum USB_OTG_SPEED { - USB_SPEED_UNKNOWN = 0, - USB_SPEED_LOW, - USB_SPEED_FULL, - USB_SPEED_HIGH -}; - -#endif //__USB_DEFINES__H__ - - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_hcd.h b/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_hcd.h deleted file mode 100644 index 15e8ab161..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_hcd.h +++ /dev/null @@ -1,102 +0,0 @@ -/** - ****************************************************************************** - * @file usb_hcd.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Host layer Header file - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_HCD_H__ -#define __USB_HCD_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_regs.h" -#include "usb_core.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_HCD - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_HCD_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_HCD_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_HCD_Exported_FunctionsPrototype - * @{ - */ -uint32_t HCD_Init (USB_OTG_CORE_HANDLE *pdev , - USB_OTG_CORE_ID_TypeDef coreID); -uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev , - uint8_t hc_num); -uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev , - uint8_t hc_num) ; -uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev); -uint32_t HCD_ResetPort (USB_OTG_CORE_HANDLE *pdev); -uint32_t HCD_IsDeviceConnected (USB_OTG_CORE_HANDLE *pdev); -uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev) ; -URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num); -uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num); -HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num) ; -/** - * @} - */ - -#endif //__USB_HCD_H__ - - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_hcd_int.h b/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_hcd_int.h deleted file mode 100644 index c95c59f82..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_hcd_int.h +++ /dev/null @@ -1,126 +0,0 @@ -/** - ****************************************************************************** - * @file usb_hcd_int.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Peripheral Device Interface Layer - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __HCD_INT_H__ -#define __HCD_INT_H__ - - -/* Includes ------------------------------------------------------------------*/ -#include "usb_hcd.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_HCD_INT - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_HCD_INT_Exported_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_INT_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_INT_Exported_Macros - * @{ - */ - -#define CLEAR_HC_INT(HC_REGS, intr) \ - {\ - USB_OTG_HCINTn_TypeDef hcint_clear; \ - hcint_clear.d32 = 0; \ - hcint_clear.b.intr = 1; \ - USB_OTG_WRITE_REG32(&((HC_REGS)->HCINT), hcint_clear.d32);\ - }\ - -#define MASK_HOST_INT_CHH(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \ - GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \ - GINTMSK.b.chhltd = 0; \ - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);} - -#define UNMASK_HOST_INT_CHH(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \ - GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \ - GINTMSK.b.chhltd = 1; \ - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);} - -#define MASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \ - GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \ - GINTMSK.b.ack = 0; \ - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);} - -#define UNMASK_HOST_INT_ACK(hc_num) { USB_OTG_HCGINTMSK_TypeDef GINTMSK; \ - GINTMSK.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK); \ - GINTMSK.b.ack = 1; \ - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, GINTMSK.d32);} - -/** - * @} - */ - -/** @defgroup USB_HCD_INT_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_HCD_INT_Exported_FunctionsPrototype - * @{ - */ -/* Callbacks handler */ -void ConnectCallback_Handler(USB_OTG_CORE_HANDLE *pdev); -void Disconnect_Callback_Handler(USB_OTG_CORE_HANDLE *pdev); -void Overcurrent_Callback_Handler(USB_OTG_CORE_HANDLE *pdev); -uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev); - -/** - * @} - */ - - - -#endif //__HCD_INT_H__ - - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_otg.h b/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_otg.h deleted file mode 100644 index 54d61b827..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_otg.h +++ /dev/null @@ -1,94 +0,0 @@ -/** - ****************************************************************************** - * @file usb_otg.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief OTG Core Header - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_OTG__ -#define __USB_OTG__ - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_OTG - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_OTG_Exported_Defines - * @{ - */ - - -void USB_OTG_InitiateSRP(void); -void USB_OTG_InitiateHNP(uint8_t state , uint8_t mode); -void USB_OTG_Switchback (USB_OTG_CORE_HANDLE *pdev); -uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_HANDLE *pdev); - -uint32_t STM32_USBO_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev); -/** - * @} - */ - - -/** @defgroup USB_OTG_Exported_Types - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_OTG_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_OTG_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_OTG_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif //__USB_OTG__ - - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_regs.h b/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_regs.h deleted file mode 100644 index cd71ddfaf..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/inc/usb_regs.h +++ /dev/null @@ -1,1206 +0,0 @@ -/** - ****************************************************************************** - * @file usb_regs.h - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief hardware registers - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __USB_OTG_REGS_H__ -#define __USB_OTG_REGS_H__ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_conf.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_REGS - * @brief This file is the - * @{ - */ - - -/** @defgroup USB_REGS_Exported_Defines - * @{ - */ - -#define USB_OTG_HS_BASE_ADDR 0x40040000 -#define USB_OTG_FS_BASE_ADDR 0x50000000 - -#define USB_OTG_CORE_GLOBAL_REGS_OFFSET 0x000 -#define USB_OTG_DEV_GLOBAL_REG_OFFSET 0x800 -#define USB_OTG_DEV_IN_EP_REG_OFFSET 0x900 -#define USB_OTG_EP_REG_OFFSET 0x20 -#define USB_OTG_DEV_OUT_EP_REG_OFFSET 0xB00 -#define USB_OTG_HOST_GLOBAL_REG_OFFSET 0x400 -#define USB_OTG_HOST_PORT_REGS_OFFSET 0x440 -#define USB_OTG_HOST_CHAN_REGS_OFFSET 0x500 -#define USB_OTG_CHAN_REGS_OFFSET 0x20 -#define USB_OTG_PCGCCTL_OFFSET 0xE00 -#define USB_OTG_DATA_FIFO_OFFSET 0x1000 -#define USB_OTG_DATA_FIFO_SIZE 0x1000 - - -#define USB_OTG_MAX_TX_FIFOS 15 - -#define USB_OTG_HS_MAX_PACKET_SIZE 512 -#define USB_OTG_FS_MAX_PACKET_SIZE 64 -#define USB_OTG_MAX_EP0_SIZE 64 -/** - * @} - */ - -/** @defgroup USB_REGS_Exported_Types - * @{ - */ - -/** @defgroup __USB_OTG_Core_register - * @{ - */ -typedef struct _USB_OTG_GREGS //000h -{ - __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/ - __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/ - __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/ - __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/ - __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/ - __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/ - __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/ - __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/ - __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/ - __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/ - __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/ - __IO uint32_t GI2CCTL; /* I2C Access Register 030h*/ - uint32_t Reserved34; /* PHY Vendor Control Register 034h*/ - __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/ - __IO uint32_t CID; /* User ID Register 03Ch*/ - uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/ - __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/ - __IO uint32_t DIEPTXF[USB_OTG_MAX_TX_FIFOS];/* dev Periodic Transmit FIFO */ -} -USB_OTG_GREGS; -/** - * @} - */ - - -/** @defgroup __device_Registers - * @{ - */ -typedef struct _USB_OTG_DREGS // 800h -{ - __IO uint32_t DCFG; /* dev Configuration Register 800h*/ - __IO uint32_t DCTL; /* dev Control Register 804h*/ - __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/ - uint32_t Reserved0C; /* Reserved 80Ch*/ - __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/ - __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/ - __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/ - __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/ - uint32_t Reserved20; /* Reserved 820h*/ - uint32_t Reserved9; /* Reserved 824h*/ - __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/ - __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/ - __IO uint32_t DTHRCTL; /* dev thr 830h*/ - __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/ - __IO uint32_t DEACHINT; /* dedicated EP interrupt 838h*/ - __IO uint32_t DEACHMSK; /* dedicated EP msk 83Ch*/ - uint32_t Reserved40; /* dedicated EP mask 840h*/ - __IO uint32_t DINEP1MSK; /* dedicated EP mask 844h*/ - uint32_t Reserved44[15]; /* Reserved 844-87Ch*/ - __IO uint32_t DOUTEP1MSK; /* dedicated EP msk 884h*/ -} -USB_OTG_DREGS; -/** - * @} - */ - - -/** @defgroup __IN_Endpoint-Specific_Register - * @{ - */ -typedef struct _USB_OTG_INEPREGS -{ - __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ - uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/ - __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ - __IO uint32_t DIEPDMA; /* IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ - __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ - uint32_t Reserved18; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ -} -USB_OTG_INEPREGS; -/** - * @} - */ - - -/** @defgroup __OUT_Endpoint-Specific_Registers - * @{ - */ -typedef struct _USB_OTG_OUTEPREGS -{ - __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ - __IO uint32_t DOUTEPFRM; /* dev OUT Endpoint Frame number B00h + (ep_num * 20h) + 04h*/ - __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ - uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/ - __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ - __IO uint32_t DOEPDMA; /* dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ - uint32_t Reserved18[2]; /* Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ -} -USB_OTG_OUTEPREGS; -/** - * @} - */ - - -/** @defgroup __Host_Mode_Register_Structures - * @{ - */ -typedef struct _USB_OTG_HREGS -{ - __IO uint32_t HCFG; /* Host Configuration Register 400h*/ - __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/ - __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/ - uint32_t Reserved40C; /* Reserved 40Ch*/ - __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/ - __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/ - __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/ -} -USB_OTG_HREGS; -/** - * @} - */ - - -/** @defgroup __Host_Channel_Specific_Registers - * @{ - */ -typedef struct _USB_OTG_HC_REGS -{ - __IO uint32_t HCCHAR; - __IO uint32_t HCSPLT; - __IO uint32_t HCINT; - __IO uint32_t HCGINTMSK; - __IO uint32_t HCTSIZ; - __IO uint32_t HCDMA; - uint32_t Reserved[2]; -} -USB_OTG_HC_REGS; -/** - * @} - */ - - -/** @defgroup __otg_Core_registers - * @{ - */ -typedef struct USB_OTG_core_regs //000h -{ - USB_OTG_GREGS *GREGS; - USB_OTG_DREGS *DREGS; - USB_OTG_HREGS *HREGS; - USB_OTG_INEPREGS *INEP_REGS[USB_OTG_MAX_TX_FIFOS]; - USB_OTG_OUTEPREGS *OUTEP_REGS[USB_OTG_MAX_TX_FIFOS]; - USB_OTG_HC_REGS *HC_REGS[USB_OTG_MAX_TX_FIFOS]; - __IO uint32_t *HPRT0; - __IO uint32_t *DFIFO[USB_OTG_MAX_TX_FIFOS]; - __IO uint32_t *PCGCCTL; -} -USB_OTG_CORE_REGS , *PUSB_OTG_CORE_REGS; -typedef union _USB_OTG_OTGCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t sesreqscs : - 1; -uint32_t sesreq : - 1; -uint32_t Reserved2_7 : - 6; -uint32_t hstnegscs : - 1; -uint32_t hnpreq : - 1; -uint32_t hstsethnpen : - 1; -uint32_t devhnpen : - 1; -uint32_t Reserved12_15 : - 4; -uint32_t conidsts : - 1; -uint32_t Reserved17 : - 1; -uint32_t asesvld : - 1; -uint32_t bsesvld : - 1; -uint32_t currmod : - 1; -uint32_t Reserved21_31 : - 11; - } - b; -} USB_OTG_OTGCTL_TypeDef ; -typedef union _USB_OTG_GOTGINT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t Reserved0_1 : - 2; -uint32_t sesenddet : - 1; -uint32_t Reserved3_7 : - 5; -uint32_t sesreqsucstschng : - 1; -uint32_t hstnegsucstschng : - 1; -uint32_t reserver10_16 : - 7; -uint32_t hstnegdet : - 1; -uint32_t adevtoutchng : - 1; -uint32_t debdone : - 1; -uint32_t Reserved31_20 : - 12; - } - b; -} USB_OTG_GOTGINT_TypeDef ; -typedef union _USB_OTG_GAHBCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t glblintrmsk : - 1; -uint32_t hburstlen : - 4; -uint32_t dmaenable : - 1; -uint32_t Reserved : - 1; -uint32_t nptxfemplvl_txfemplvl : - 1; -uint32_t ptxfemplvl : - 1; -uint32_t Reserved9_31 : - 23; - } - b; -} USB_OTG_GAHBCFG_TypeDef ; -typedef union _USB_OTG_GUSBCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t toutcal : - 3; -uint32_t phyif : - 1; -uint32_t ulpi_utmi_sel : - 1; -uint32_t fsintf : - 1; -uint32_t physel : - 1; -uint32_t ddrsel : - 1; -uint32_t srpcap : - 1; -uint32_t hnpcap : - 1; -uint32_t usbtrdtim : - 4; -uint32_t nptxfrwnden : - 1; -uint32_t phylpwrclksel : - 1; -uint32_t otgutmifssel : - 1; -uint32_t ulpi_fsls : - 1; -uint32_t ulpi_auto_res : - 1; -uint32_t ulpi_clk_sus_m : - 1; -uint32_t ulpi_ext_vbus_drv : - 1; -uint32_t ulpi_int_vbus_indicator : - 1; -uint32_t term_sel_dl_pulse : - 1; -uint32_t Reserved : - 6; -uint32_t force_host : - 1; -uint32_t force_dev : - 1; -uint32_t corrupt_tx : - 1; - } - b; -} USB_OTG_GUSBCFG_TypeDef ; -typedef union _USB_OTG_GRSTCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t csftrst : - 1; -uint32_t hsftrst : - 1; -uint32_t hstfrm : - 1; -uint32_t intknqflsh : - 1; -uint32_t rxfflsh : - 1; -uint32_t txfflsh : - 1; -uint32_t txfnum : - 5; -uint32_t Reserved11_29 : - 19; -uint32_t dmareq : - 1; -uint32_t ahbidle : - 1; - } - b; -} USB_OTG_GRSTCTL_TypeDef ; -typedef union _USB_OTG_GINTMSK_TypeDef -{ - uint32_t d32; - struct - { -uint32_t Reserved0 : - 1; -uint32_t modemismatch : - 1; -uint32_t otgintr : - 1; -uint32_t sofintr : - 1; -uint32_t rxstsqlvl : - 1; -uint32_t nptxfempty : - 1; -uint32_t ginnakeff : - 1; -uint32_t goutnakeff : - 1; -uint32_t Reserved8 : - 1; -uint32_t i2cintr : - 1; -uint32_t erlysuspend : - 1; -uint32_t usbsuspend : - 1; -uint32_t usbreset : - 1; -uint32_t enumdone : - 1; -uint32_t isooutdrop : - 1; -uint32_t eopframe : - 1; -uint32_t Reserved16 : - 1; -uint32_t epmismatch : - 1; -uint32_t inepintr : - 1; -uint32_t outepintr : - 1; -uint32_t incomplisoin : - 1; -uint32_t incomplisoout : - 1; -uint32_t Reserved22_23 : - 2; -uint32_t portintr : - 1; -uint32_t hcintr : - 1; -uint32_t ptxfempty : - 1; -uint32_t Reserved27 : - 1; -uint32_t conidstschng : - 1; -uint32_t disconnect : - 1; -uint32_t sessreqintr : - 1; -uint32_t wkupintr : - 1; - } - b; -} USB_OTG_GINTMSK_TypeDef ; -typedef union _USB_OTG_GINTSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t curmode : - 1; -uint32_t modemismatch : - 1; -uint32_t otgintr : - 1; -uint32_t sofintr : - 1; -uint32_t rxstsqlvl : - 1; -uint32_t nptxfempty : - 1; -uint32_t ginnakeff : - 1; -uint32_t goutnakeff : - 1; -uint32_t Reserved8 : - 1; -uint32_t i2cintr : - 1; -uint32_t erlysuspend : - 1; -uint32_t usbsuspend : - 1; -uint32_t usbreset : - 1; -uint32_t enumdone : - 1; -uint32_t isooutdrop : - 1; -uint32_t eopframe : - 1; -uint32_t intimerrx : - 1; -uint32_t epmismatch : - 1; -uint32_t inepint: - 1; -uint32_t outepintr : - 1; -uint32_t incomplisoin : - 1; -uint32_t incomplisoout : - 1; -uint32_t Reserved22_23 : - 2; -uint32_t portintr : - 1; -uint32_t hcintr : - 1; -uint32_t ptxfempty : - 1; -uint32_t Reserved27 : - 1; -uint32_t conidstschng : - 1; -uint32_t disconnect : - 1; -uint32_t sessreqintr : - 1; -uint32_t wkupintr : - 1; - } - b; -} USB_OTG_GINTSTS_TypeDef ; -typedef union _USB_OTG_DRXSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t epnum : - 4; -uint32_t bcnt : - 11; -uint32_t dpid : - 2; -uint32_t pktsts : - 4; -uint32_t fn : - 4; -uint32_t Reserved : - 7; - } - b; -} USB_OTG_DRXSTS_TypeDef ; -typedef union _USB_OTG_GRXSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t chnum : - 4; -uint32_t bcnt : - 11; -uint32_t dpid : - 2; -uint32_t pktsts : - 4; -uint32_t Reserved : - 11; - } - b; -} USB_OTG_GRXFSTS_TypeDef ; -typedef union _USB_OTG_FSIZ_TypeDef -{ - uint32_t d32; - struct - { -uint32_t startaddr : - 16; -uint32_t depth : - 16; - } - b; -} USB_OTG_FSIZ_TypeDef ; -typedef union _USB_OTG_HNPTXSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t nptxfspcavail : - 16; -uint32_t nptxqspcavail : - 8; -uint32_t nptxqtop_terminate : - 1; -uint32_t nptxqtop_timer : - 2; -uint32_t nptxqtop : - 2; -uint32_t chnum : - 2; -uint32_t Reserved : - 1; - } - b; -} USB_OTG_HNPTXSTS_TypeDef ; -typedef union _USB_OTG_DTXFSTSn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t txfspcavail : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_DTXFSTSn_TypeDef ; -typedef union _USB_OTG_GI2CCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t rwdata : - 8; -uint32_t regaddr : - 8; -uint32_t addr : - 7; -uint32_t i2cen : - 1; -uint32_t ack : - 1; -uint32_t i2csuspctl : - 1; -uint32_t i2cdevaddr : - 2; -uint32_t dat_se0: - 1; -uint32_t Reserved : - 1; -uint32_t rw : - 1; -uint32_t bsydne : - 1; - } - b; -} USB_OTG_GI2CCTL_TypeDef ; -typedef union _USB_OTG_GCCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t Reserved_in : - 16; -uint32_t pwdn : - 1; -uint32_t i2cifen : - 1; -uint32_t vbussensingA : - 1; -uint32_t vbussensingB : - 1; -uint32_t sofouten : - 1; -uint32_t disablevbussensing : - 1; -uint32_t Reserved_out : - 10; - } - b; -} USB_OTG_GCCFG_TypeDef ; - -typedef union _USB_OTG_DCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t devspd : - 2; -uint32_t nzstsouthshk : - 1; -uint32_t Reserved3 : - 1; -uint32_t devaddr : - 7; -uint32_t perfrint : - 2; -uint32_t Reserved13_17 : - 5; -uint32_t epmscnt : - 4; - } - b; -} USB_OTG_DCFG_TypeDef ; -typedef union _USB_OTG_DCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t rmtwkupsig : - 1; -uint32_t sftdiscon : - 1; -uint32_t gnpinnaksts : - 1; -uint32_t goutnaksts : - 1; -uint32_t tstctl : - 3; -uint32_t sgnpinnak : - 1; -uint32_t cgnpinnak : - 1; -uint32_t sgoutnak : - 1; -uint32_t cgoutnak : - 1; -uint32_t Reserved : - 21; - } - b; -} USB_OTG_DCTL_TypeDef ; -typedef union _USB_OTG_DSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t suspsts : - 1; -uint32_t enumspd : - 2; -uint32_t errticerr : - 1; -uint32_t Reserved4_7: - 4; -uint32_t soffn : - 14; -uint32_t Reserved22_31 : - 10; - } - b; -} USB_OTG_DSTS_TypeDef ; -typedef union _USB_OTG_DIEPINTn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t epdisabled : - 1; -uint32_t ahberr : - 1; -uint32_t timeout : - 1; -uint32_t intktxfemp : - 1; -uint32_t intknepmis : - 1; -uint32_t inepnakeff : - 1; -uint32_t emptyintr : - 1; -uint32_t txfifoundrn : - 1; -uint32_t Reserved08_31 : - 23; - } - b; -} USB_OTG_DIEPINTn_TypeDef ; -typedef union _USB_OTG_DIEPINTn_TypeDef USB_OTG_DIEPMSK_TypeDef ; -typedef union _USB_OTG_DOEPINTn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t epdisabled : - 1; -uint32_t ahberr : - 1; -uint32_t setup : - 1; -uint32_t Reserved04_31 : - 28; - } - b; -} USB_OTG_DOEPINTn_TypeDef ; -typedef union _USB_OTG_DOEPINTn_TypeDef USB_OTG_DOEPMSK_TypeDef ; - -typedef union _USB_OTG_DAINT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t in : - 16; -uint32_t out : - 16; - } - ep; -} USB_OTG_DAINT_TypeDef ; - -typedef union _USB_OTG_DTHRCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t non_iso_thr_en : - 1; -uint32_t iso_thr_en : - 1; -uint32_t tx_thr_len : - 9; -uint32_t Reserved11_15 : - 5; -uint32_t rx_thr_en : - 1; -uint32_t rx_thr_len : - 9; -uint32_t Reserved26_31 : - 6; - } - b; -} USB_OTG_DTHRCTL_TypeDef ; -typedef union _USB_OTG_DEPCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t mps : - 11; -uint32_t reserved : - 4; -uint32_t usbactep : - 1; -uint32_t dpid : - 1; -uint32_t naksts : - 1; -uint32_t eptype : - 2; -uint32_t snp : - 1; -uint32_t stall : - 1; -uint32_t txfnum : - 4; -uint32_t cnak : - 1; -uint32_t snak : - 1; -uint32_t setd0pid : - 1; -uint32_t setd1pid : - 1; -uint32_t epdis : - 1; -uint32_t epena : - 1; - } - b; -} USB_OTG_DEPCTL_TypeDef ; -typedef union _USB_OTG_DEPXFRSIZ_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfersize : - 19; -uint32_t pktcnt : - 10; -uint32_t mc : - 2; -uint32_t Reserved : - 1; - } - b; -} USB_OTG_DEPXFRSIZ_TypeDef ; -typedef union _USB_OTG_DEP0XFRSIZ_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfersize : - 7; -uint32_t Reserved7_18 : - 12; -uint32_t pktcnt : - 2; -uint32_t Reserved20_28 : - 9; -uint32_t supcnt : - 2; - uint32_t Reserved31; - } - b; -} USB_OTG_DEP0XFRSIZ_TypeDef ; -typedef union _USB_OTG_HCFG_TypeDef -{ - uint32_t d32; - struct - { -uint32_t fslspclksel : - 2; -uint32_t fslssupp : - 1; - } - b; -} USB_OTG_HCFG_TypeDef ; -typedef union _USB_OTG_HFRMINTRVL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t frint : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_HFRMINTRVL_TypeDef ; - -typedef union _USB_OTG_HFNUM_TypeDef -{ - uint32_t d32; - struct - { -uint32_t frnum : - 16; -uint32_t frrem : - 16; - } - b; -} USB_OTG_HFNUM_TypeDef ; -typedef union _USB_OTG_HPTXSTS_TypeDef -{ - uint32_t d32; - struct - { -uint32_t ptxfspcavail : - 16; -uint32_t ptxqspcavail : - 8; -uint32_t ptxqtop_terminate : - 1; -uint32_t ptxqtop_timer : - 2; -uint32_t ptxqtop : - 2; -uint32_t chnum : - 2; -uint32_t ptxqtop_odd : - 1; - } - b; -} USB_OTG_HPTXSTS_TypeDef ; -typedef union _USB_OTG_HPRT0_TypeDef -{ - uint32_t d32; - struct - { -uint32_t prtconnsts : - 1; -uint32_t prtconndet : - 1; -uint32_t prtena : - 1; -uint32_t prtenchng : - 1; -uint32_t prtovrcurract : - 1; -uint32_t prtovrcurrchng : - 1; -uint32_t prtres : - 1; -uint32_t prtsusp : - 1; -uint32_t prtrst : - 1; -uint32_t Reserved9 : - 1; -uint32_t prtlnsts : - 2; -uint32_t prtpwr : - 1; -uint32_t prttstctl : - 4; -uint32_t prtspd : - 2; -uint32_t Reserved19_31 : - 13; - } - b; -} USB_OTG_HPRT0_TypeDef ; -typedef union _USB_OTG_HAINT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t chint : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_HAINT_TypeDef ; -typedef union _USB_OTG_HAINTMSK_TypeDef -{ - uint32_t d32; - struct - { -uint32_t chint : - 16; -uint32_t Reserved : - 16; - } - b; -} USB_OTG_HAINTMSK_TypeDef ; -typedef union _USB_OTG_HCCHAR_TypeDef -{ - uint32_t d32; - struct - { -uint32_t mps : - 11; -uint32_t epnum : - 4; -uint32_t epdir : - 1; -uint32_t Reserved : - 1; -uint32_t lspddev : - 1; -uint32_t eptype : - 2; -uint32_t multicnt : - 2; -uint32_t devaddr : - 7; -uint32_t oddfrm : - 1; -uint32_t chdis : - 1; -uint32_t chen : - 1; - } - b; -} USB_OTG_HCCHAR_TypeDef ; -typedef union _USB_OTG_HCSPLT_TypeDef -{ - uint32_t d32; - struct - { -uint32_t prtaddr : - 7; -uint32_t hubaddr : - 7; -uint32_t xactpos : - 2; -uint32_t compsplt : - 1; -uint32_t Reserved : - 14; -uint32_t spltena : - 1; - } - b; -} USB_OTG_HCSPLT_TypeDef ; -typedef union _USB_OTG_HCINTn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t chhltd : - 1; -uint32_t ahberr : - 1; -uint32_t stall : - 1; -uint32_t nak : - 1; -uint32_t ack : - 1; -uint32_t nyet : - 1; -uint32_t xacterr : - 1; -uint32_t bblerr : - 1; -uint32_t frmovrun : - 1; -uint32_t datatglerr : - 1; -uint32_t Reserved : - 21; - } - b; -} USB_OTG_HCINTn_TypeDef ; -typedef union _USB_OTG_HCTSIZn_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfersize : - 19; -uint32_t pktcnt : - 10; -uint32_t pid : - 2; -uint32_t dopng : - 1; - } - b; -} USB_OTG_HCTSIZn_TypeDef ; -typedef union _USB_OTG_HCGINTMSK_TypeDef -{ - uint32_t d32; - struct - { -uint32_t xfercompl : - 1; -uint32_t chhltd : - 1; -uint32_t ahberr : - 1; -uint32_t stall : - 1; -uint32_t nak : - 1; -uint32_t ack : - 1; -uint32_t nyet : - 1; -uint32_t xacterr : - 1; -uint32_t bblerr : - 1; -uint32_t frmovrun : - 1; -uint32_t datatglerr : - 1; -uint32_t Reserved : - 21; - } - b; -} USB_OTG_HCGINTMSK_TypeDef ; -typedef union _USB_OTG_PCGCCTL_TypeDef -{ - uint32_t d32; - struct - { -uint32_t stoppclk : - 1; -uint32_t gatehclk : - 1; -uint32_t Reserved : - 30; - } - b; -} USB_OTG_PCGCCTL_TypeDef ; - -/** - * @} - */ - - -/** @defgroup USB_REGS_Exported_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_REGS_Exported_Variables - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_REGS_Exported_FunctionsPrototype - * @{ - */ -/** - * @} - */ - - -#endif //__USB_OTG_REGS_H__ - - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_OTG_Driver/src/usb_bsp_template.c b/example/stm32f4/STM32_USB_OTG_Driver/src/usb_bsp_template.c deleted file mode 100644 index c3f515bcd..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/src/usb_bsp_template.c +++ /dev/null @@ -1,200 +0,0 @@ -/** - ****************************************************************************** - * @file usb_bsp.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief This file is responsible to offer board support package and is - * configurable by user. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_bsp.h" - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_BSP - * @brief This file is responsible to offer board support package - * @{ - */ - -/** @defgroup USB_BSP_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_BSP_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - - - -/** @defgroup USB_BSP_Private_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup USBH_BSP_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup USBH_BSP_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - -/** @defgroup USB_BSP_Private_Functions - * @{ - */ - - -/** - * @brief USB_OTG_BSP_Init - * Initilizes BSP configurations - * @param None - * @retval None - */ - -void USB_OTG_BSP_Init(void) -{ - -} -/** - * @brief USB_OTG_BSP_EnableInterrupt - * Enabele USB Global interrupt - * @param None - * @retval None - */ -void USB_OTG_BSP_EnableInterrupt(void) -{ - -} - -/** - * @brief BSP_Drive_VBUS - * Drives the Vbus signal through IO - * @param speed : Full, Low - * @param state : VBUS states - * @retval None - */ - -void USB_OTG_BSP_DriveVBUS(uint32_t speed, uint8_t state) -{ - -} - -/** - * @brief USB_OTG_BSP_ConfigVBUS - * Configures the IO for the Vbus and OverCurrent - * @param Speed : Full, Low - * @retval None - */ - -void USB_OTG_BSP_ConfigVBUS(uint32_t speed) -{ - -} - -/** - * @brief USB_OTG_BSP_TimeInit - * Initialises delay unit Systick timer /Timer2 - * @param None - * @retval None - */ -void USB_OTG_BSP_TimeInit ( void ) -{ - -} - -/** - * @brief USB_OTG_BSP_uDelay - * This function provides delay time in micro sec - * @param usec : Value of delay required in micro sec - * @retval None - */ -void USB_OTG_BSP_uDelay (const uint32_t usec) -{ - - uint32_t count = 0; - const uint32_t utime = (120 * usec / 7); - do - { - if ( ++count > utime ) - { - return ; - } - } - while (1); - -} - - -/** - * @brief USB_OTG_BSP_mDelay - * This function provides delay time in milli sec - * @param msec : Value of delay required in milli sec - * @retval None - */ -void USB_OTG_BSP_mDelay (const uint32_t msec) -{ - - USB_OTG_BSP_uDelay(msec * 1000); - -} - - -/** - * @brief USB_OTG_BSP_TimerIRQ - * Time base IRQ - * @param None - * @retval None - */ - -void USB_OTG_BSP_TimerIRQ (void) -{ - -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_OTG_Driver/src/usb_core.c b/example/stm32f4/STM32_USB_OTG_Driver/src/usb_core.c deleted file mode 100644 index 74e432ac2..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/src/usb_core.c +++ /dev/null @@ -1,2187 +0,0 @@ -/** - ****************************************************************************** - * @file usb_core.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief USB-OTG Core Layer - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" -#include "usb_bsp.h" - - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_CORE -* @brief This file includes the USB-OTG Core Layer -* @{ -*/ - - -/** @defgroup USB_CORE_Private_Defines -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USB_CORE_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_FunctionPrototypes -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_CORE_Private_Functions -* @{ -*/ - -/** -* @brief USB_OTG_EnableCommonInt -* Initializes the commmon interrupts, used in both device and modes -* @param pdev : Selected device -* @retval None -*/ -static void USB_OTG_EnableCommonInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef int_mask; - - int_mask.d32 = 0; - /* Clear any pending USB_OTG Interrupts */ -#ifndef USE_OTG_MODE - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GOTGINT, 0xFFFFFFFF); -#endif - /* Clear any pending interrupts */ - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF); - /* Enable the interrupts in the INTMSK */ - int_mask.b.wkupintr = 1; - int_mask.b.usbsuspend = 1; - -#ifdef USE_OTG_MODE - int_mask.b.otgintr = 1; - int_mask.b.sessreqintr = 1; - int_mask.b.conidstschng = 1; -#endif - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32); -} - -/** -* @brief USB_OTG_CoreReset : Soft reset of the core -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -static USB_OTG_STS USB_OTG_CoreReset(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - __IO USB_OTG_GRSTCTL_TypeDef greset; - uint32_t count = 0; - - greset.d32 = 0; - /* Wait for AHB master IDLE state. */ - do - { - USB_OTG_BSP_uDelay(3); - greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - return USB_OTG_OK; - } - } - while (greset.b.ahbidle == 0); - /* Core Soft Reset */ - count = 0; - greset.b.csftrst = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRSTCTL, greset.d32 ); - do - { - greset.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - break; - } - } - while (greset.b.csftrst == 1); - /* Wait for 3 PHY Clocks*/ - USB_OTG_BSP_uDelay(3); - return status; -} - -/** -* @brief USB_OTG_WritePacket : Writes a packet into the Tx FIFO associated -* with the EP -* @param pdev : Selected device -* @param src : source pointer -* @param ch_ep_num : end point number -* @param bytes : No. of bytes -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_WritePacket(USB_OTG_CORE_HANDLE *pdev, - uint8_t *src, - uint8_t ch_ep_num, - uint16_t len) -{ - USB_OTG_STS status = USB_OTG_OK; - if (pdev->cfg.dma_enable == 0) - { - uint32_t count32b= 0 , i= 0; - __IO uint32_t *fifo; - - count32b = (len + 3) / 4; - fifo = pdev->regs.DFIFO[ch_ep_num]; - for (i = 0; i < count32b; i++, src+=4) - { - USB_OTG_WRITE_REG32( fifo, *((__packed uint32_t *)src) ); - } - } - return status; -} - - -/** -* @brief USB_OTG_ReadPacket : Reads a packet from the Rx FIFO -* @param pdev : Selected device -* @param dest : Destination Pointer -* @param bytes : No. of bytes -* @retval None -*/ -void *USB_OTG_ReadPacket(USB_OTG_CORE_HANDLE *pdev, - uint8_t *dest, - uint16_t len) -{ - uint32_t i=0; - uint32_t count32b = (len + 3) / 4; - - __IO uint32_t *fifo = pdev->regs.DFIFO[0]; - - for ( i = 0; i < count32b; i++, dest += 4 ) - { - *(__packed uint32_t *)dest = USB_OTG_READ_REG32(fifo); - - } - return ((void *)dest); -} - -/** -* @brief USB_OTG_SelectCore -* Initialize core registers address. -* @param pdev : Selected device -* @param coreID : USB OTG Core ID -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_SelectCore(USB_OTG_CORE_HANDLE *pdev, - USB_OTG_CORE_ID_TypeDef coreID) -{ - uint32_t i , baseAddress = 0; - USB_OTG_STS status = USB_OTG_OK; - - pdev->cfg.dma_enable = 0; - - /* at startup the core is in FS mode */ - pdev->cfg.speed = USB_OTG_SPEED_FULL; - pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; - - /* initialize device cfg following its address */ - if (coreID == USB_OTG_FS_CORE_ID) - { - baseAddress = USB_OTG_FS_BASE_ADDR; - pdev->cfg.coreID = USB_OTG_FS_CORE_ID; - pdev->cfg.host_channels = 8 ; - pdev->cfg.dev_endpoints = 4 ; - pdev->cfg.TotalFifoSize = 320; /* in 32-bits */ - pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; - -#ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED - pdev->cfg.Sof_output = 1; -#endif - -#ifdef USB_OTG_FS_LOW_PWR_MGMT_SUPPORT - pdev->cfg.low_power = 1; -#endif - } - else if (coreID == USB_OTG_HS_CORE_ID) - { - baseAddress = USB_OTG_HS_BASE_ADDR; - pdev->cfg.coreID = USB_OTG_HS_CORE_ID; - pdev->cfg.host_channels = 12 ; - pdev->cfg.dev_endpoints = 6 ; - pdev->cfg.TotalFifoSize = 1280;/* in 32-bits */ - -#ifdef USB_OTG_ULPI_PHY_ENABLED - pdev->cfg.phy_itface = USB_OTG_ULPI_PHY; -#else - #ifdef USB_OTG_EMBEDDED_PHY_ENABLED - pdev->cfg.phy_itface = USB_OTG_EMBEDDED_PHY; - #else - #ifdef USB_OTG_I2C_PHY_ENABLED - pdev->cfg.phy_itface = USB_OTG_I2C_PHY; - #endif - #endif -#endif - -#ifdef USB_OTG_HS_INTERNAL_DMA_ENABLED - pdev->cfg.dma_enable = 1; -#endif - -#ifdef USB_OTG_HS_SOF_OUTPUT_ENABLED - pdev->cfg.Sof_output = 1; -#endif - -#ifdef USB_OTG_HS_LOW_PWR_MGMT_SUPPORT - pdev->cfg.low_power = 1; -#endif - - } - - pdev->regs.GREGS = (USB_OTG_GREGS *)(baseAddress + \ - USB_OTG_CORE_GLOBAL_REGS_OFFSET); - pdev->regs.DREGS = (USB_OTG_DREGS *) (baseAddress + \ - USB_OTG_DEV_GLOBAL_REG_OFFSET); - - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - pdev->regs.INEP_REGS[i] = (USB_OTG_INEPREGS *) \ - (baseAddress + USB_OTG_DEV_IN_EP_REG_OFFSET + \ - (i * USB_OTG_EP_REG_OFFSET)); - pdev->regs.OUTEP_REGS[i] = (USB_OTG_OUTEPREGS *) \ - (baseAddress + USB_OTG_DEV_OUT_EP_REG_OFFSET + \ - (i * USB_OTG_EP_REG_OFFSET)); - } - pdev->regs.HREGS = (USB_OTG_HREGS *)(baseAddress + \ - USB_OTG_HOST_GLOBAL_REG_OFFSET); - pdev->regs.HPRT0 = (uint32_t *)(baseAddress + USB_OTG_HOST_PORT_REGS_OFFSET); - - for (i = 0; i < pdev->cfg.host_channels; i++) - { - pdev->regs.HC_REGS[i] = (USB_OTG_HC_REGS *)(baseAddress + \ - USB_OTG_HOST_CHAN_REGS_OFFSET + \ - (i * USB_OTG_CHAN_REGS_OFFSET)); - } - for (i = 0; i < pdev->cfg.host_channels; i++) - { - pdev->regs.DFIFO[i] = (uint32_t *)(baseAddress + USB_OTG_DATA_FIFO_OFFSET +\ - (i * USB_OTG_DATA_FIFO_SIZE)); - } - pdev->regs.PCGCCTL = (uint32_t *)(baseAddress + USB_OTG_PCGCCTL_OFFSET); - - return status; -} - - -/** -* @brief USB_OTG_CoreInit -* Initializes the USB_OTG controller registers and prepares the core -* device mode or host mode operation. -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_CoreInit(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GUSBCFG_TypeDef usbcfg; - USB_OTG_GCCFG_TypeDef gccfg; - USB_OTG_GI2CCTL_TypeDef i2cctl; - USB_OTG_GAHBCFG_TypeDef ahbcfg; - - usbcfg.d32 = 0; - gccfg.d32 = 0; - ahbcfg.d32 = 0; - - - - if (pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) - { - gccfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GCCFG); - gccfg.b.pwdn = 0; - - if (pdev->cfg.Sof_output) - { - gccfg.b.sofouten = 1; - } - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); - - /* Init The ULPI Interface */ - usbcfg.d32 = 0; - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - - usbcfg.b.physel = 0; /* HS Interface */ -#ifdef USB_OTG_INTERNAL_VBUS_ENABLED - usbcfg.b.ulpi_ext_vbus_drv = 0; /* Use internal VBUS */ -#else - #ifdef USB_OTG_EXTERNAL_VBUS_ENABLED - usbcfg.b.ulpi_ext_vbus_drv = 1; /* Use external VBUS */ - #endif -#endif - usbcfg.b.term_sel_dl_pulse = 0; /* Data line pulsing using utmi_txvalid */ - usbcfg.b.ulpi_utmi_sel = 1; /* ULPI seleInterfacect */ - - usbcfg.b.phyif = 0; /* 8 bits */ - usbcfg.b.ddrsel = 0; /* single data rate */ - - usbcfg.b.ulpi_fsls = 0; - usbcfg.b.ulpi_clk_sus_m = 0; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - - /* Reset after a PHY select */ - USB_OTG_CoreReset(pdev); - - if(pdev->cfg.dma_enable == 1) - { - - ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ - ahbcfg.b.dmaenable = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); - - } - } - else /* FS interface (embedded Phy or I2C Phy) */ - { - - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG);; - usbcfg.b.physel = 1; /* FS Interface */ - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - /* Reset after a PHY select and set Host mode */ - USB_OTG_CoreReset(pdev); - /* Enable the I2C interface and deactivate the power down*/ - gccfg.d32 = 0; - gccfg.b.pwdn = 1; - - if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY) - { - gccfg.b.i2cifen = 1; - } - gccfg.b.vbussensingA = 1 ; - gccfg.b.vbussensingB = 1 ; -#ifndef VBUS_SENSING_ENABLED - gccfg.b.disablevbussensing = 1; -#endif - - if(pdev->cfg.Sof_output) - { - gccfg.b.sofouten = 1; - } - - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GCCFG, gccfg.d32); - USB_OTG_BSP_mDelay(20); - /* Program GUSBCFG.OtgUtmifsSel to I2C*/ - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - - if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY) - { - usbcfg.b.otgutmifssel = 1; - } - - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - - if(pdev->cfg.phy_itface == USB_OTG_I2C_PHY) - { - /*Program GI2CCTL.I2CEn*/ - i2cctl.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GI2CCTL); - i2cctl.b.i2cdevaddr = 1; - i2cctl.b.i2cen = 0; - i2cctl.b.dat_se0 = 1; - i2cctl.b.addr = 0x2D; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GI2CCTL, i2cctl.d32); - - USB_OTG_BSP_mDelay(200); - - i2cctl.b.i2cen = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GI2CCTL, i2cctl.d32); - USB_OTG_BSP_mDelay(200); - } - } - /* case the HS core is working in FS mode */ - if(pdev->cfg.dma_enable == 1) - { - - ahbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GAHBCFG); - ahbcfg.b.hburstlen = 5; /* 64 x 32-bits*/ - ahbcfg.b.dmaenable = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32); - - } - /* initialize OTG features */ -#ifdef USE_OTG_MODE - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - usbcfg.b.hnpcap = 1; - usbcfg.b.srpcap = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - USB_OTG_EnableCommonInt(pdev); -#endif - return status; -} -/** -* @brief USB_OTG_EnableGlobalInt -* Enables the controller's Global Int in the AHB Config reg -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EnableGlobalInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GAHBCFG_TypeDef ahbcfg; - - ahbcfg.d32 = 0; - ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, 0, ahbcfg.d32); - return status; -} - - -/** -* @brief USB_OTG_DisableGlobalInt -* Enables the controller's Global Int in the AHB Config reg -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_DisableGlobalInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GAHBCFG_TypeDef ahbcfg; - ahbcfg.d32 = 0; - ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GAHBCFG, ahbcfg.d32, 0); - return status; -} - - -/** -* @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO -* @param pdev : Selected device -* @param num : FO num -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_FlushTxFifo (USB_OTG_CORE_HANDLE *pdev , uint32_t num ) -{ - USB_OTG_STS status = USB_OTG_OK; - __IO USB_OTG_GRSTCTL_TypeDef greset; - - uint32_t count = 0; - greset.d32 = 0; - greset.b.txfflsh = 1; - greset.b.txfnum = num; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 ); - do - { - greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - break; - } - } - while (greset.b.txfflsh == 1); - /* Wait for 3 PHY Clocks*/ - USB_OTG_BSP_uDelay(3); - return status; -} - - -/** -* @brief USB_OTG_FlushRxFifo : Flush a Rx FIFO -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_FlushRxFifo( USB_OTG_CORE_HANDLE *pdev ) -{ - USB_OTG_STS status = USB_OTG_OK; - __IO USB_OTG_GRSTCTL_TypeDef greset; - uint32_t count = 0; - - greset.d32 = 0; - greset.b.rxfflsh = 1; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GRSTCTL, greset.d32 ); - do - { - greset.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRSTCTL); - if (++count > 200000) - { - break; - } - } - while (greset.b.rxfflsh == 1); - /* Wait for 3 PHY Clocks*/ - USB_OTG_BSP_uDelay(3); - return status; -} - - -/** -* @brief USB_OTG_SetCurrentMode : Set ID line -* @param pdev : Selected device -* @param mode : (Host/device) -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_SetCurrentMode(USB_OTG_CORE_HANDLE *pdev , uint8_t mode) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GUSBCFG_TypeDef usbcfg; - - usbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - - usbcfg.b.force_host = 0; - usbcfg.b.force_dev = 0; - - if ( mode == HOST_MODE) - { - usbcfg.b.force_host = 1; - } - else if ( mode == DEVICE_MODE) - { - usbcfg.b.force_dev = 1; - } - - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, usbcfg.d32); - USB_OTG_BSP_mDelay(50); - return status; -} - - -/** -* @brief USB_OTG_GetMode : Get current mode -* @param pdev : Selected device -* @retval current mode -*/ -uint32_t USB_OTG_GetMode(USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS ) & 0x1); -} - - -/** -* @brief USB_OTG_IsDeviceMode : Check if it is device mode -* @param pdev : Selected device -* @retval num_in_ep -*/ -uint8_t USB_OTG_IsDeviceMode(USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_GetMode(pdev) != HOST_MODE); -} - - -/** -* @brief USB_OTG_IsHostMode : Check if it is host mode -* @param pdev : Selected device -* @retval num_in_ep -*/ -uint8_t USB_OTG_IsHostMode(USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_GetMode(pdev) == HOST_MODE); -} - - -/** -* @brief USB_OTG_ReadCoreItr : returns the Core Interrupt register -* @param pdev : Selected device -* @retval Status -*/ -uint32_t USB_OTG_ReadCoreItr(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t v = 0; - v = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS); - v &= USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK); - return v; -} - - -/** -* @brief USB_OTG_ReadOtgItr : returns the USB_OTG Interrupt register -* @param pdev : Selected device -* @retval Status -*/ -uint32_t USB_OTG_ReadOtgItr (USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32 (&pdev->regs.GREGS->GOTGINT)); -} - -#ifdef USE_HOST_MODE -/** -* @brief USB_OTG_CoreInitHost : Initializes USB_OTG controller for host mode -* @param pdev : Selected device -* @retval status -*/ -USB_OTG_STS USB_OTG_CoreInitHost(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_FSIZ_TypeDef nptxfifosize; - USB_OTG_FSIZ_TypeDef ptxfifosize; - USB_OTG_HCFG_TypeDef hcfg; - -#ifdef USE_OTG_MODE - USB_OTG_OTGCTL_TypeDef gotgctl; -#endif - - uint32_t i = 0; - - nptxfifosize.d32 = 0; - ptxfifosize.d32 = 0; -#ifdef USE_OTG_MODE - gotgctl.d32 = 0; -#endif - hcfg.d32 = 0; - - - /* configure charge pump IO */ - USB_OTG_BSP_ConfigVBUS(pdev); - - /* Restart the Phy Clock */ - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); - - /* Initialize Host Configuration Register */ - USB_OTG_InitFSLSPClkSel(pdev , HCFG_48_MHZ); /* in init phase */ - - hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); - hcfg.b.fslssupp = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); - - /* Configure data FIFO sizes */ - /* Rx FIFO */ -#ifdef USB_OTG_FS_CORE - if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID) - { - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); - nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; - nptxfifosize.b.depth = TXH_NP_FS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); - - ptxfifosize.b.startaddr = RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ; - ptxfifosize.b.depth = TXH_P_FS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); - } -#endif -#ifdef USB_OTG_HS_CORE - if (pdev->cfg.coreID == USB_OTG_HS_CORE_ID) - { - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); - nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; - nptxfifosize.b.depth = TXH_NP_HS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32); - - ptxfifosize.b.startaddr = RX_FIFO_HS_SIZE + TXH_NP_HS_FIFOSIZ; - ptxfifosize.b.depth = TXH_P_HS_FIFOSIZ; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->HPTXFSIZ, ptxfifosize.d32); - } -#endif - -#ifdef USE_OTG_MODE - /* Clear Host Set HNP Enable in the USB_OTG Control Register */ - gotgctl.b.hstsethnpen = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GOTGCTL, gotgctl.d32, 0); -#endif - - /* Make sure the FIFOs are flushed. */ - USB_OTG_FlushTxFifo(pdev, 0x10 ); /* all Tx FIFOs */ - USB_OTG_FlushRxFifo(pdev); - - - /* Clear all pending HC Interrupts */ - for (i = 0; i < pdev->cfg.host_channels; i++) - { - USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCINT, 0xFFFFFFFF ); - USB_OTG_WRITE_REG32( &pdev->regs.HC_REGS[i]->HCGINTMSK, 0 ); - } -#ifndef USE_OTG_MODE - USB_OTG_DriveVbus(pdev, 1); -#endif - - USB_OTG_EnableHostInt(pdev); - return status; -} - -/** -* @brief USB_OTG_IsEvenFrame -* This function returns the frame number for sof packet -* @param pdev : Selected device -* @retval Frame number -*/ -uint8_t USB_OTG_IsEvenFrame (USB_OTG_CORE_HANDLE *pdev) -{ - return !(USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0x1); -} - -/** -* @brief USB_OTG_DriveVbus : set/reset vbus -* @param pdev : Selected device -* @param state : VBUS state -* @retval None -*/ -void USB_OTG_DriveVbus (USB_OTG_CORE_HANDLE *pdev, uint8_t state) -{ - USB_OTG_HPRT0_TypeDef hprt0; - - hprt0.d32 = 0; - - /* enable disable the external charge pump */ - USB_OTG_BSP_DriveVBUS(pdev, state); - - /* Turn on the Host port power. */ - hprt0.d32 = USB_OTG_ReadHPRT0(pdev); - if ((hprt0.b.prtpwr == 0 ) && (state == 1 )) - { - hprt0.b.prtpwr = 1; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - } - if ((hprt0.b.prtpwr == 1 ) && (state == 0 )) - { - hprt0.b.prtpwr = 0; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - } - - USB_OTG_BSP_mDelay(200); -} -/** -* @brief USB_OTG_EnableHostInt: Enables the Host mode interrupts -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EnableHostInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GINTMSK_TypeDef intmsk; - intmsk.d32 = 0; - /* Disable all interrupts. */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTMSK, 0); - - /* Clear any pending interrupts. */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF); - - /* Enable the common interrupts */ - USB_OTG_EnableCommonInt(pdev); - - if (pdev->cfg.dma_enable == 0) - { - intmsk.b.rxstsqlvl = 1; - } - intmsk.b.portintr = 1; - intmsk.b.hcintr = 1; - intmsk.b.disconnect = 1; - intmsk.b.sofintr = 1; - intmsk.b.incomplisoout = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); - return status; -} - -/** -* @brief USB_OTG_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the -* HCFG register on the PHY type -* @param pdev : Selected device -* @param freq : clock frequency -* @retval None -*/ -void USB_OTG_InitFSLSPClkSel(USB_OTG_CORE_HANDLE *pdev , uint8_t freq) -{ - USB_OTG_HCFG_TypeDef hcfg; - - hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); - hcfg.b.fslspclksel = freq; - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HCFG, hcfg.d32); -} - - -/** -* @brief USB_OTG_ReadHPRT0 : Reads HPRT0 to modify later -* @param pdev : Selected device -* @retval HPRT0 value -*/ -uint32_t USB_OTG_ReadHPRT0(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef hprt0; - - hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); - hprt0.b.prtena = 0; - hprt0.b.prtconndet = 0; - hprt0.b.prtenchng = 0; - hprt0.b.prtovrcurrchng = 0; - return hprt0.d32; -} - - -/** -* @brief USB_OTG_ReadHostAllChannels_intr : Register PCD Callbacks -* @param pdev : Selected device -* @retval Status -*/ -uint32_t USB_OTG_ReadHostAllChannels_intr (USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32 (&pdev->regs.HREGS->HAINT)); -} - - -/** -* @brief USB_OTG_ResetPort : Reset Host Port -* @param pdev : Selected device -* @retval status -* @note : (1)The application must wait at least 10 ms (+ 10 ms security) -* before clearing the reset bit. -*/ -uint32_t USB_OTG_ResetPort(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef hprt0; - - hprt0.d32 = USB_OTG_ReadHPRT0(pdev); - hprt0.b.prtrst = 1; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - USB_OTG_BSP_mDelay (10); /* See Note #1 */ - hprt0.b.prtrst = 0; - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0.d32); - USB_OTG_BSP_mDelay (20); - return 1; -} - - -/** -* @brief USB_OTG_HC_Init : Prepares a host channel for transferring packets -* @param pdev : Selected device -* @param hc_num : channel number -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_HC_Init(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - uint32_t intr_enable = 0; - USB_OTG_HCGINTMSK_TypeDef hcintmsk; - USB_OTG_GINTMSK_TypeDef gintmsk; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCINTn_TypeDef hcint; - - - gintmsk.d32 = 0; - hcintmsk.d32 = 0; - hcchar.d32 = 0; - - /* Clear old interrupt conditions for this host channel. */ - hcint.d32 = 0xFFFFFFFF; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCINT, hcint.d32); - - /* Enable channel interrupts required for this transfer. */ - hcintmsk.d32 = 0; - - if (pdev->cfg.dma_enable == 1) - { - hcintmsk.b.ahberr = 1; - } - - switch (pdev->host.hc[hc_num].ep_type) - { - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - hcintmsk.b.xfercompl = 1; - hcintmsk.b.stall = 1; - hcintmsk.b.xacterr = 1; - hcintmsk.b.datatglerr = 1; - hcintmsk.b.nak = 1; - if (pdev->host.hc[hc_num].ep_is_in) - { - hcintmsk.b.bblerr = 1; - } - else - { - hcintmsk.b.nyet = 1; - if (pdev->host.hc[hc_num].do_ping) - { - hcintmsk.b.ack = 1; - } - } - break; - case EP_TYPE_INTR: - hcintmsk.b.xfercompl = 1; - hcintmsk.b.nak = 1; - hcintmsk.b.stall = 1; - hcintmsk.b.xacterr = 1; - hcintmsk.b.datatglerr = 1; - hcintmsk.b.frmovrun = 1; - - if (pdev->host.hc[hc_num].ep_is_in) - { - hcintmsk.b.bblerr = 1; - } - - break; - case EP_TYPE_ISOC: - hcintmsk.b.xfercompl = 1; - hcintmsk.b.frmovrun = 1; - hcintmsk.b.ack = 1; - - if (pdev->host.hc[hc_num].ep_is_in) - { - hcintmsk.b.xacterr = 1; - hcintmsk.b.bblerr = 1; - } - break; - } - - - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCGINTMSK, hcintmsk.d32); - - - /* Enable the top level host channel interrupt. */ - intr_enable = (1 << hc_num); - USB_OTG_MODIFY_REG32(&pdev->regs.HREGS->HAINTMSK, 0, intr_enable); - - /* Make sure host channel interrupts are enabled. */ - gintmsk.b.hcintr = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, gintmsk.d32); - - /* Program the HCCHAR register */ - hcchar.d32 = 0; - hcchar.b.devaddr = pdev->host.hc[hc_num].dev_addr; - hcchar.b.epnum = pdev->host.hc[hc_num].ep_num; - hcchar.b.epdir = pdev->host.hc[hc_num].ep_is_in; - hcchar.b.lspddev = (pdev->host.hc[hc_num].speed == HPRT0_PRTSPD_LOW_SPEED); - hcchar.b.eptype = pdev->host.hc[hc_num].ep_type; - hcchar.b.mps = pdev->host.hc[hc_num].max_packet; - if (pdev->host.hc[hc_num].ep_type == HCCHAR_INTR) - { - hcchar.b.oddfrm = 1; - } - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; -} - - -/** -* @brief USB_OTG_HC_StartXfer : Start transfer -* @param pdev : Selected device -* @param hc_num : channel number -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_HC_StartXfer(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCTSIZn_TypeDef hctsiz; - USB_OTG_HNPTXSTS_TypeDef hnptxsts; - USB_OTG_HPTXSTS_TypeDef hptxsts; - USB_OTG_GINTMSK_TypeDef intmsk; - uint16_t len_words = 0; - - uint16_t num_packets; - uint16_t max_hc_pkt_count; - - max_hc_pkt_count = 256; - hctsiz.d32 = 0; - hcchar.d32 = 0; - intmsk.d32 = 0; - - /* Compute the expected number of packets associated to the transfer */ - if (pdev->host.hc[hc_num].xfer_len > 0) - { - num_packets = (pdev->host.hc[hc_num].xfer_len + \ - pdev->host.hc[hc_num].max_packet - 1) / pdev->host.hc[hc_num].max_packet; - - if (num_packets > max_hc_pkt_count) - { - num_packets = max_hc_pkt_count; - pdev->host.hc[hc_num].xfer_len = num_packets * \ - pdev->host.hc[hc_num].max_packet; - } - } - else - { - num_packets = 1; - } - if (pdev->host.hc[hc_num].ep_is_in) - { - pdev->host.hc[hc_num].xfer_len = num_packets * \ - pdev->host.hc[hc_num].max_packet; - } - /* Initialize the HCTSIZn register */ - hctsiz.b.xfersize = pdev->host.hc[hc_num].xfer_len; - hctsiz.b.pktcnt = num_packets; - hctsiz.b.pid = pdev->host.hc[hc_num].data_pid; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCDMA, (unsigned int)pdev->host.hc[hc_num].xfer_buff); - } - - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); - hcchar.b.oddfrm = USB_OTG_IsEvenFrame(pdev); - - /* Set host channel enable */ - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - - if (pdev->cfg.dma_enable == 0) /* Slave mode */ - { - if((pdev->host.hc[hc_num].ep_is_in == 0) && - (pdev->host.hc[hc_num].xfer_len > 0)) - { - switch(pdev->host.hc[hc_num].ep_type) - { - /* Non periodic transfer */ - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4; - - /* check if there is enough space in FIFO space */ - if(len_words > hnptxsts.b.nptxfspcavail) - { - /* need to process data in nptxfempty interrupt */ - intmsk.b.nptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); - } - - break; - /* Periodic transfer */ - case EP_TYPE_INTR: - case EP_TYPE_ISOC: - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - len_words = (pdev->host.hc[hc_num].xfer_len + 3) / 4; - /* check if there is enough space in FIFO space */ - if(len_words > hptxsts.b.ptxfspcavail) /* split the transfer */ - { - /* need to process data in ptxfempty interrupt */ - intmsk.b.ptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); - } - break; - - default: - break; - } - - /* Write packet into the Tx FIFO. */ - USB_OTG_WritePacket(pdev, - pdev->host.hc[hc_num].xfer_buff , - hc_num, pdev->host.hc[hc_num].xfer_len); - } - } - return status; -} - - -/** -* @brief USB_OTG_HC_Halt : Halt channel -* @param pdev : Selected device -* @param hc_num : channel number -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_HC_Halt(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_HNPTXSTS_TypeDef nptxsts; - USB_OTG_HPTXSTS_TypeDef hptxsts; - USB_OTG_HCCHAR_TypeDef hcchar; - - nptxsts.d32 = 0; - hptxsts.d32 = 0; - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); - hcchar.b.chen = 1; - hcchar.b.chdis = 1; - - /* Check for space in the request queue to issue the halt. */ - if (hcchar.b.eptype == HCCHAR_CTRL || hcchar.b.eptype == HCCHAR_BULK) - { - nptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - if (nptxsts.b.nptxqspcavail == 0) - { - hcchar.b.chen = 0; - } - } - else - { - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - if (hptxsts.b.ptxqspcavail == 0) - { - hcchar.b.chen = 0; - } - } - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; -} - -/** -* @brief Issue a ping token -* @param None -* @retval : None -*/ -USB_OTG_STS USB_OTG_HC_DoPing(USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCTSIZn_TypeDef hctsiz; - - hctsiz.d32 = 0; - hctsiz.b.dopng = 1; - hctsiz.b.pktcnt = 1; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCTSIZ, hctsiz.d32); - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR); - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[hc_num]->HCCHAR, hcchar.d32); - return status; -} - -/** -* @brief Stop the device and clean up fifo's -* @param None -* @retval : None -*/ -void USB_OTG_StopHost(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HCCHAR_TypeDef hcchar; - uint32_t i; - - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINTMSK , 0); - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HAINT, 0xFFFFFFFF); - /* Flush out any leftover queued requests. */ - - for (i = 0; i < pdev->cfg.host_channels; i++) - { - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR); - hcchar.b.chen = 0; - hcchar.b.chdis = 1; - hcchar.b.epdir = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[i]->HCCHAR, hcchar.d32); - } - - /* Flush the FIFO */ - USB_OTG_FlushRxFifo(pdev); - USB_OTG_FlushTxFifo(pdev , 0x10 ); -} -#endif -#ifdef USE_DEVICE_MODE -/* PCD Core Layer */ - -/** -* @brief USB_OTG_InitDevSpeed :Initializes the DevSpd field of DCFG register -* depending the PHY type and the enumeration speed of the device. -* @param pdev : Selected device -* @retval : None -*/ -void USB_OTG_InitDevSpeed(USB_OTG_CORE_HANDLE *pdev , uint8_t speed) -{ - USB_OTG_DCFG_TypeDef dcfg; - - dcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCFG); - dcfg.b.devspd = speed; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCFG, dcfg.d32); -} - - -/** -* @brief USB_OTG_CoreInitDev : Initializes the USB_OTG controller registers -* for device mode -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_CoreInitDev (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - uint32_t i; - USB_OTG_DCFG_TypeDef dcfg; - USB_OTG_FSIZ_TypeDef nptxfifosize; - USB_OTG_FSIZ_TypeDef txfifosize; - USB_OTG_DIEPMSK_TypeDef msk; - USB_OTG_DTHRCTL_TypeDef dthrctl; - - depctl.d32 = 0; - dcfg.d32 = 0; - nptxfifosize.d32 = 0; - txfifosize.d32 = 0; - msk.d32 = 0; - - /* Restart the Phy Clock */ - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, 0); - /* Device configuration register */ - dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG); - dcfg.b.perfrint = DCFG_FRAME_INTERVAL_80; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32 ); - -#ifdef USB_OTG_FS_CORE - if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID ) - { - - /* Set Full speed phy */ - USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_FULL); - - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_FS_SIZE); - - /* EP0 TX*/ - nptxfifosize.b.depth = TX0_FIFO_FS_SIZE; - nptxfifosize.b.startaddr = RX_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); - - - /* EP1 TX*/ - txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; - txfifosize.b.depth = TX1_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); - - - /* EP2 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX2_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); - - - /* EP3 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX3_FIFO_FS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); - } -#endif -#ifdef USB_OTG_HS_CORE - if(pdev->cfg.coreID == USB_OTG_HS_CORE_ID ) - { - - /* Set High speed phy */ - - if(pdev->cfg.phy_itface == USB_OTG_ULPI_PHY) - { - USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH); - } - else /* set High speed phy in Full speed mode */ - { - USB_OTG_InitDevSpeed (pdev , USB_OTG_SPEED_PARAM_HIGH_IN_FULL); - } - - /* set Rx FIFO size */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GRXFSIZ, RX_FIFO_HS_SIZE); - - /* EP0 TX*/ - nptxfifosize.b.depth = TX0_FIFO_HS_SIZE; - nptxfifosize.b.startaddr = RX_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF0_HNPTXFSIZ, nptxfifosize.d32 ); - - - /* EP1 TX*/ - txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; - txfifosize.b.depth = TX1_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[0], txfifosize.d32 ); - - - /* EP2 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX2_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[1], txfifosize.d32 ); - - - /* EP3 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX3_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[2], txfifosize.d32 ); - - /* EP4 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX4_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[3], txfifosize.d32 ); - - - /* EP5 TX*/ - txfifosize.b.startaddr += txfifosize.b.depth; - txfifosize.b.depth = TX5_FIFO_HS_SIZE; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->DIEPTXF[4], txfifosize.d32 ); - } -#endif - /* Flush the FIFOs */ - USB_OTG_FlushTxFifo(pdev , 0x10); /* all Tx FIFOs */ - USB_OTG_FlushRxFifo(pdev); - /* Clear all pending Device Interrupts */ - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); - - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[i]->DIEPCTL); - if (depctl.b.epena) - { - depctl.d32 = 0; - depctl.b.epdis = 1; - depctl.b.snak = 1; - } - else - { - depctl.d32 = 0; - } - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPCTL, depctl.d32); - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPTSIZ, 0); - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); - } - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - USB_OTG_DEPCTL_TypeDef depctl; - depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[i]->DOEPCTL); - if (depctl.b.epena) - { - depctl.d32 = 0; - depctl.b.epdis = 1; - depctl.b.snak = 1; - } - else - { - depctl.d32 = 0; - } - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPCTL, depctl.d32); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPTSIZ, 0); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); - } - msk.d32 = 0; - msk.b.txfifoundrn = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPMSK, msk.d32, msk.d32); - - if (pdev->cfg.dma_enable == 1) - { - dthrctl.d32 = 0; - dthrctl.b.non_iso_thr_en = 1; - dthrctl.b.iso_thr_en = 1; - dthrctl.b.tx_thr_len = 64; - dthrctl.b.rx_thr_en = 1; - dthrctl.b.rx_thr_len = 64; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DTHRCTL, dthrctl.d32); - } - USB_OTG_EnableDevInt(pdev); - return status; -} - - -/** -* @brief USB_OTG_EnableDevInt : Enables the Device mode interrupts -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EnableDevInt(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_GINTMSK_TypeDef intmsk; - - intmsk.d32 = 0; - - /* Disable all interrupts. */ - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTMSK, 0); - /* Clear any pending interrupts */ - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, 0xFFFFFFFF); - /* Enable the common interrupts */ - USB_OTG_EnableCommonInt(pdev); - - if (pdev->cfg.dma_enable == 0) - { - intmsk.b.rxstsqlvl = 1; - } - - /* Enable interrupts matching to the Device mode ONLY */ - intmsk.b.usbsuspend = 1; - intmsk.b.usbreset = 1; - intmsk.b.enumdone = 1; - intmsk.b.inepintr = 1; - intmsk.b.outepintr = 1; - intmsk.b.sofintr = 1; - - intmsk.b.incomplisoin = 1; - intmsk.b.incomplisoout = 1; -#ifdef VBUS_SENSING_ENABLED - intmsk.b.sessreqintr = 1; - intmsk.b.otgintr = 1; -#endif - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, intmsk.d32); - return status; -} - - -/** -* @brief USB_OTG_GetDeviceSpeed -* Get the device speed from the device status register -* @param None -* @retval status -*/ -enum USB_OTG_SPEED USB_OTG_GetDeviceSpeed (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DSTS_TypeDef dsts; - enum USB_OTG_SPEED speed = USB_SPEED_UNKNOWN; - - - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - switch (dsts.b.enumspd) - { - case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: - speed = USB_SPEED_HIGH; - break; - case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: - case DSTS_ENUMSPD_FS_PHY_48MHZ: - speed = USB_SPEED_FULL; - break; - - case DSTS_ENUMSPD_LS_PHY_6MHZ: - speed = USB_SPEED_LOW; - break; - } - - return speed; -} -/** -* @brief enables EP0 OUT to receive SETUP packets and configures EP0 -* for transmitting packets -* @param None -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EP0Activate(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DSTS_TypeDef dsts; - USB_OTG_DEPCTL_TypeDef diepctl; - USB_OTG_DCTL_TypeDef dctl; - - dctl.d32 = 0; - /* Read the Device Status and Endpoint 0 Control registers */ - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - diepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL); - /* Set the MPS of the IN EP based on the enumeration speed */ - switch (dsts.b.enumspd) - { - case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: - case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: - case DSTS_ENUMSPD_FS_PHY_48MHZ: - diepctl.b.mps = DEP0CTL_MPS_64; - break; - case DSTS_ENUMSPD_LS_PHY_6MHZ: - diepctl.b.mps = DEP0CTL_MPS_8; - break; - } - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[0]->DIEPCTL, diepctl.d32); - dctl.b.cgnpinnak = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, dctl.d32); - return status; -} - - -/** -* @brief USB_OTG_EPActivate : Activates an EP -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPActivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DAINT_TypeDef daintmsk; - __IO uint32_t *addr; - - - depctl.d32 = 0; - daintmsk.d32 = 0; - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL; - daintmsk.ep.in = 1 << ep->num; - } - else - { - addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL; - daintmsk.ep.out = 1 << ep->num; - } - /* If the EP is already active don't change the EP Control - * register. */ - depctl.d32 = USB_OTG_READ_REG32(addr); - if (!depctl.b.usbactep) - { - depctl.b.mps = ep->maxpacket; - depctl.b.eptype = ep->type; - depctl.b.txfnum = ep->tx_fifo_num; - depctl.b.setd0pid = 1; - depctl.b.usbactep = 1; - USB_OTG_WRITE_REG32(addr, depctl.d32); - } - /* Enable the Interrupt for this EP */ -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID)) - { - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, 0, daintmsk.d32); - } - else -#endif - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, 0, daintmsk.d32); - return status; -} - - -/** -* @brief USB_OTG_EPDeactivate : Deactivates an EP -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPDeactivate(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DAINT_TypeDef daintmsk; - __IO uint32_t *addr; - - depctl.d32 = 0; - daintmsk.d32 = 0; - /* Read DEPCTLn register */ - if (ep->is_in == 1) - { - addr = &pdev->regs.INEP_REGS[ep->num]->DIEPCTL; - daintmsk.ep.in = 1 << ep->num; - } - else - { - addr = &pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL; - daintmsk.ep.out = 1 << ep->num; - } - depctl.b.usbactep = 0; - USB_OTG_WRITE_REG32(addr, depctl.d32); - /* Disable the Interrupt for this EP */ - -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - if((ep->num == 1)&&(pdev->cfg.coreID == USB_OTG_HS_CORE_ID)) - { - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DEACHMSK, daintmsk.d32, 0); - } - else -#endif - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DAINTMSK, daintmsk.d32, 0); - return status; -} - - -/** -* @brief USB_OTG_EPStartXfer : Handle the setup for data xfer for an EP and -* starts the xfer -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPStartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DEPXFRSIZ_TypeDef deptsiz; - USB_OTG_DSTS_TypeDef dsts; - uint32_t fifoemptymsk = 0; - - depctl.d32 = 0; - deptsiz.d32 = 0; - /* IN endpoint */ - if (ep->is_in == 1) - { - depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPCTL)); - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ)); - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = 0; - deptsiz.b.pktcnt = 1; - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - deptsiz.b.xfersize = ep->xfer_len; - deptsiz.b.pktcnt = (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; - - if (ep->type == EP_TYPE_ISOC) - { - deptsiz.b.mc = 1; - } - } - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPTSIZ, deptsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); - } - else - { - if (ep->type != EP_TYPE_ISOC) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - fifoemptymsk = 1 << ep->num; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk); - } - } - } - - - if (ep->type == EP_TYPE_ISOC) - { - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - if (((dsts.b.soffn)&0x1) == 0) - { - depctl.b.setd1pid = 1; - } - else - { - depctl.b.setd0pid = 1; - } - } - - /* EP enable, IN data in FIFO */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPCTL, depctl.d32); - - if (ep->type == EP_TYPE_ISOC) - { - USB_OTG_WritePacket(pdev, ep->xfer_buff, ep->num, ep->xfer_len); - } - } - else - { - /* OUT endpoint */ - depctl.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL)); - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ)); - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - else - { - deptsiz.b.pktcnt = (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket; - deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; - } - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr); - } - - if (ep->type == EP_TYPE_ISOC) - { - if (ep->even_odd_frame) - { - depctl.b.setd1pid = 1; - } - else - { - depctl.b.setd0pid = 1; - } - } - /* EP enable */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL, depctl.d32); - } - return status; -} - - -/** -* @brief USB_OTG_EP0StartXfer : Handle the setup for a data xfer for EP0 and -* starts the xfer -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EP0StartXfer(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - USB_OTG_DEP0XFRSIZ_TypeDef deptsiz; - USB_OTG_INEPREGS *in_regs; - uint32_t fifoemptymsk = 0; - - depctl.d32 = 0; - deptsiz.d32 = 0; - /* IN endpoint */ - if (ep->is_in == 1) - { - in_regs = pdev->regs.INEP_REGS[0]; - depctl.d32 = USB_OTG_READ_REG32(&in_regs->DIEPCTL); - deptsiz.d32 = USB_OTG_READ_REG32(&in_regs->DIEPTSIZ); - /* Zero Length Packet? */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = 0; - deptsiz.b.pktcnt = 1; - - } - else - { - if (ep->xfer_len > ep->maxpacket) - { - ep->xfer_len = ep->maxpacket; - deptsiz.b.xfersize = ep->maxpacket; - } - else - { - deptsiz.b.xfersize = ep->xfer_len; - } - deptsiz.b.pktcnt = 1; - } - USB_OTG_WRITE_REG32(&in_regs->DIEPTSIZ, deptsiz.d32); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.INEP_REGS[ep->num]->DIEPDMA, ep->dma_addr); - } - - /* EP enable, IN data in FIFO */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32(&in_regs->DIEPCTL, depctl.d32); - - - - if (pdev->cfg.dma_enable == 0) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0) - { - { - fifoemptymsk |= 1 << ep->num; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, 0, fifoemptymsk); - } - } - } - } - else - { - /* OUT endpoint */ - depctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - deptsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ); - /* Program the transfer size and packet count as follows: - * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) - * pktcnt = N */ - if (ep->xfer_len == 0) - { - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - else - { - ep->xfer_len = ep->maxpacket; - deptsiz.b.xfersize = ep->maxpacket; - deptsiz.b.pktcnt = 1; - } - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPTSIZ, deptsiz.d32); - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_WRITE_REG32(&pdev->regs.OUTEP_REGS[ep->num]->DOEPDMA, ep->dma_addr); - } - /* EP enable */ - depctl.b.cnak = 1; - depctl.b.epena = 1; - USB_OTG_WRITE_REG32 (&(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL), depctl.d32); - - } - return status; -} - - -/** -* @brief USB_OTG_EPSetStall : Set the EP STALL -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPSetStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - - depctl.d32 = 0; - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - /* set the disable and stall bits */ - if (depctl.b.epena) - { - depctl.b.epdis = 1; - } - depctl.b.stall = 1; - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); - } - else - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - /* set the stall bit */ - depctl.b.stall = 1; - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); - } - return status; -} - - -/** -* @brief Clear the EP STALL -* @param pdev : Selected device -* @retval USB_OTG_STS : status -*/ -USB_OTG_STS USB_OTG_EPClearStall(USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep) -{ - USB_OTG_STS status = USB_OTG_OK; - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - - depctl.d32 = 0; - - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - } - else - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - } - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - /* clear the stall bits */ - depctl.b.stall = 0; - if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK) - { - depctl.b.setd0pid = 1; /* DATA0 */ - } - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); - return status; -} - - -/** -* @brief USB_OTG_ReadDevAllOutEp_itr : returns OUT endpoint interrupt bits -* @param pdev : Selected device -* @retval OUT endpoint interrupt bits -*/ -uint32_t USB_OTG_ReadDevAllOutEp_itr(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t v; - v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT); - v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK); - return ((v & 0xffff0000) >> 16); -} - - -/** -* @brief USB_OTG_ReadDevOutEP_itr : returns Device OUT EP Interrupt register -* @param pdev : Selected device -* @param ep : end point number -* @retval Device OUT EP Interrupt register -*/ -uint32_t USB_OTG_ReadDevOutEP_itr(USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - uint32_t v; - v = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[epnum]->DOEPINT); - v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOEPMSK); - return v; -} - - -/** -* @brief USB_OTG_ReadDevAllInEPItr : Get int status register -* @param pdev : Selected device -* @retval int status register -*/ -uint32_t USB_OTG_ReadDevAllInEPItr(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t v; - v = USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINT); - v &= USB_OTG_READ_REG32(&pdev->regs.DREGS->DAINTMSK); - return (v & 0xffff); -} - -/** -* @brief configures EPO to receive SETUP packets -* @param None -* @retval : None -*/ -void USB_OTG_EP0_OutStart(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DEP0XFRSIZ_TypeDef doeptsize0; - doeptsize0.d32 = 0; - doeptsize0.b.supcnt = 3; - doeptsize0.b.pktcnt = 1; - doeptsize0.b.xfersize = 8 * 3; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPTSIZ, doeptsize0.d32 ); - - if (pdev->cfg.dma_enable == 1) - { - USB_OTG_DEPCTL_TypeDef doepctl; - doepctl.d32 = 0; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPDMA, - (uint32_t)&pdev->dev.setup_packet); - - /* EP enable */ - doepctl.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[0]->DOEPCTL); - doepctl.b.epena = 1; - doepctl.d32 = 0x80008000; - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[0]->DOEPCTL, doepctl.d32); - } -} - -/** -* @brief USB_OTG_RemoteWakeup : active remote wakeup signalling -* @param None -* @retval : None -*/ -void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_DCTL_TypeDef dctl; - USB_OTG_DSTS_TypeDef dsts; - USB_OTG_PCGCCTL_TypeDef power; - - if (pdev->dev.DevRemoteWakeup) - { - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - if(dsts.b.suspsts == 1) - { - if(pdev->cfg.low_power) - { - /* un-gate USB Core clock */ - power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL); - power.b.gatehclk = 0; - power.b.stoppclk = 0; - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - } - /* active Remote wakeup signaling */ - dctl.d32 = 0; - dctl.b.rmtwkupsig = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, 0, dctl.d32); - USB_OTG_BSP_mDelay(5); - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 ); - } - } -} - - -/** -* @brief USB_OTG_UngateClock : active USB Core clock -* @param None -* @retval : None -*/ -void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev) -{ - if(pdev->cfg.low_power) - { - - USB_OTG_DSTS_TypeDef dsts; - USB_OTG_PCGCCTL_TypeDef power; - - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - if(dsts.b.suspsts == 1) - { - /* un-gate USB Core clock */ - power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL); - power.b.gatehclk = 0; - power.b.stoppclk = 0; - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - - } - } -} - -/** -* @brief Stop the device and clean up fifo's -* @param None -* @retval : None -*/ -void USB_OTG_StopDevice(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t i; - - pdev->dev.device_status = 1; - - for (i = 0; i < pdev->cfg.dev_endpoints ; i++) - { - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); - } - - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, 0 ); - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - - /* Flush the FIFO */ - USB_OTG_FlushRxFifo(pdev); - USB_OTG_FlushTxFifo(pdev , 0x10 ); -} - -/** -* @brief returns the EP Status -* @param pdev : Selected device -* ep : endpoint structure -* @retval : EP status -*/ - -uint32_t USB_OTG_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,USB_OTG_EP *ep) -{ - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - uint32_t Status = 0; - - depctl.d32 = 0; - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (depctl.b.stall == 1) - Status = USB_OTG_EP_TX_STALL; - else if (depctl.b.naksts == 1) - Status = USB_OTG_EP_TX_NAK; - else - Status = USB_OTG_EP_TX_VALID; - - } - else - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - if (depctl.b.stall == 1) - Status = USB_OTG_EP_RX_STALL; - else if (depctl.b.naksts == 1) - Status = USB_OTG_EP_RX_NAK; - else - Status = USB_OTG_EP_RX_VALID; - } - - /* Return the current status */ - return Status; -} - -/** -* @brief Set the EP Status -* @param pdev : Selected device -* Status : new Status -* ep : EP structure -* @retval : None -*/ -void USB_OTG_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , USB_OTG_EP *ep , uint32_t Status) -{ - USB_OTG_DEPCTL_TypeDef depctl; - __IO uint32_t *depctl_addr; - - depctl.d32 = 0; - - /* Process for IN endpoint */ - if (ep->is_in == 1) - { - depctl_addr = &(pdev->regs.INEP_REGS[ep->num]->DIEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (Status == USB_OTG_EP_TX_STALL) - { - USB_OTG_EPSetStall(pdev, ep); return; - } - else if (Status == USB_OTG_EP_TX_NAK) - depctl.b.snak = 1; - else if (Status == USB_OTG_EP_TX_VALID) - { - if (depctl.b.stall == 1) - { - ep->even_odd_frame = 0; - USB_OTG_EPClearStall(pdev, ep); - return; - } - depctl.b.cnak = 1; - depctl.b.usbactep = 1; - depctl.b.epena = 1; - } - else if (Status == USB_OTG_EP_TX_DIS) - depctl.b.usbactep = 0; - } - else /* Process for OUT endpoint */ - { - depctl_addr = &(pdev->regs.OUTEP_REGS[ep->num]->DOEPCTL); - depctl.d32 = USB_OTG_READ_REG32(depctl_addr); - - if (Status == USB_OTG_EP_RX_STALL) { - depctl.b.stall = 1; - } - else if (Status == USB_OTG_EP_RX_NAK) - depctl.b.snak = 1; - else if (Status == USB_OTG_EP_RX_VALID) - { - if (depctl.b.stall == 1) - { - ep->even_odd_frame = 0; - USB_OTG_EPClearStall(pdev, ep); - return; - } - depctl.b.cnak = 1; - depctl.b.usbactep = 1; - depctl.b.epena = 1; - } - else if (Status == USB_OTG_EP_RX_DIS) - { - depctl.b.usbactep = 0; - } - } - - USB_OTG_WRITE_REG32(depctl_addr, depctl.d32); -} - -#endif -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_OTG_Driver/src/usb_dcd.c b/example/stm32f4/STM32_USB_OTG_Driver/src/usb_dcd.c deleted file mode 100644 index c3336cb84..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/src/usb_dcd.c +++ /dev/null @@ -1,472 +0,0 @@ -/** - ****************************************************************************** - * @file usb_dcd.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Peripheral Device Interface Layer - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd.h" -#include "usb_bsp.h" - - -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_DCD -* @brief This file is the interface between EFSL ans Host mass-storage class -* @{ -*/ - - -/** @defgroup USB_DCD_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USB_DCD_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_FunctionPrototypes -* @{ -*/ - -/** -* @} -*/ - - -/** @defgroup USB_DCD_Private_Functions -* @{ -*/ - - - -void DCD_Init(USB_OTG_CORE_HANDLE *pdev , - USB_OTG_CORE_ID_TypeDef coreID) -{ - uint32_t i; - USB_OTG_EP *ep; - - USB_OTG_SelectCore (pdev , coreID); - - pdev->dev.device_status = USB_OTG_DEFAULT; - pdev->dev.device_address = 0; - - /* Init ep structure */ - for (i = 0; i < pdev->cfg.dev_endpoints ; i++) - { - ep = &pdev->dev.in_ep[i]; - /* Init ep structure */ - ep->is_in = 1; - ep->num = i; - ep->tx_fifo_num = i; - /* Control until ep is actvated */ - ep->type = EP_TYPE_CTRL; - ep->maxpacket = USB_OTG_MAX_EP0_SIZE; - ep->xfer_buff = 0; - ep->xfer_len = 0; - } - - for (i = 0; i < pdev->cfg.dev_endpoints; i++) - { - ep = &pdev->dev.out_ep[i]; - /* Init ep structure */ - ep->is_in = 0; - ep->num = i; - ep->tx_fifo_num = i; - /* Control until ep is activated */ - ep->type = EP_TYPE_CTRL; - ep->maxpacket = USB_OTG_MAX_EP0_SIZE; - ep->xfer_buff = 0; - ep->xfer_len = 0; - } - - USB_OTG_DisableGlobalInt(pdev); - - /*Init the Core (common init.) */ - USB_OTG_CoreInit(pdev); - - - /* Force Device Mode*/ - USB_OTG_SetCurrentMode(pdev, DEVICE_MODE); - - /* Init Device */ - USB_OTG_CoreInitDev(pdev); - - - /* Enable USB Global interrupt */ - USB_OTG_EnableGlobalInt(pdev); -} - - -/** -* @brief Configure an EP -* @param pdev : Device instance -* @param epdesc : Endpoint Descriptor -* @retval : status -*/ -uint32_t DCD_EP_Open(USB_OTG_CORE_HANDLE *pdev , - uint8_t ep_addr, - uint16_t ep_mps, - uint8_t ep_type) -{ - USB_OTG_EP *ep; - - if ((ep_addr & 0x80) == 0x80) - { - ep = &pdev->dev.in_ep[ep_addr & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - - ep->is_in = (0x80 & ep_addr) != 0; - ep->maxpacket = ep_mps; - ep->type = ep_type; - if (ep->is_in) - { - /* Assign a Tx FIFO */ - ep->tx_fifo_num = ep->num; - } - /* Set initial data PID. */ - if (ep_type == USB_OTG_EP_BULK ) - { - ep->data_pid_start = 0; - } - USB_OTG_EPActivate(pdev , ep ); - return 0; -} -/** -* @brief called when an EP is disabled -* @param pdev: device instance -* @param ep_addr: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_Close(USB_OTG_CORE_HANDLE *pdev , uint8_t ep_addr) -{ - USB_OTG_EP *ep; - - if ((ep_addr&0x80) == 0x80) - { - ep = &pdev->dev.in_ep[ep_addr & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[ep_addr & 0x7F]; - } - ep->num = ep_addr & 0x7F; - ep->is_in = (0x80 & ep_addr) != 0; - USB_OTG_EPDeactivate(pdev , ep ); - return 0; -} - - -/** -* @brief DCD_EP_PrepareRx -* @param pdev: device instance -* @param ep_addr: endpoint address -* @param pbuf: pointer to Rx buffer -* @param buf_len: data length -* @retval : status -*/ -uint32_t DCD_EP_PrepareRx( USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint16_t buf_len) -{ - USB_OTG_EP *ep; - - ep = &pdev->dev.out_ep[ep_addr & 0x7F]; - - /*setup and start the Xfer */ - ep->xfer_buff = pbuf; - ep->xfer_len = buf_len; - ep->xfer_count = 0; - ep->is_in = 0; - ep->num = ep_addr & 0x7F; - - if (pdev->cfg.dma_enable == 1) - { - ep->dma_addr = (uint32_t)pbuf; - } - - if ( ep->num == 0 ) - { - USB_OTG_EP0StartXfer(pdev , ep); - } - else - { - USB_OTG_EPStartXfer(pdev, ep ); - } - return 0; -} - -/** -* @brief Transmit data over USB -* @param pdev: device instance -* @param ep_addr: endpoint address -* @param pbuf: pointer to Tx buffer -* @param buf_len: data length -* @retval : status -*/ -uint32_t DCD_EP_Tx ( USB_OTG_CORE_HANDLE *pdev, - uint8_t ep_addr, - uint8_t *pbuf, - uint32_t buf_len) -{ - USB_OTG_EP *ep; - - ep = &pdev->dev.in_ep[ep_addr & 0x7F]; - - /* Setup and start the Transfer */ - ep->is_in = 1; - ep->num = ep_addr & 0x7F; - ep->xfer_buff = pbuf; - ep->dma_addr = (uint32_t)pbuf; - ep->xfer_count = 0; - ep->xfer_len = buf_len; - - if ( ep->num == 0 ) - { - USB_OTG_EP0StartXfer(pdev , ep); - } - else - { - USB_OTG_EPStartXfer(pdev, ep ); - } - return 0; -} - - -/** -* @brief Stall an endpoint. -* @param pdev: device instance -* @param epnum: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_Stall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - USB_OTG_EP *ep; - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - ep->is_stall = 1; - ep->num = epnum & 0x7F; - ep->is_in = ((epnum & 0x80) == 0x80); - - USB_OTG_EPSetStall(pdev , ep); - return (0); -} - - -/** -* @brief Clear stall condition on endpoints. -* @param pdev: device instance -* @param epnum: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_ClrStall (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - USB_OTG_EP *ep; - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - ep->is_stall = 0; - ep->num = epnum & 0x7F; - ep->is_in = ((epnum & 0x80) == 0x80); - - USB_OTG_EPClearStall(pdev , ep); - return (0); -} - - -/** -* @brief This Function flushes the FIFOs. -* @param pdev: device instance -* @param epnum: endpoint address -* @retval : status -*/ -uint32_t DCD_EP_Flush (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum) -{ - - if ((epnum & 0x80) == 0x80) - { - USB_OTG_FlushTxFifo(pdev, epnum & 0x7F); - } - else - { - USB_OTG_FlushRxFifo(pdev); - } - - return (0); -} - - -/** -* @brief This Function set USB device address -* @param pdev: device instance -* @param address: new device address -* @retval : status -*/ -void DCD_EP_SetAddress (USB_OTG_CORE_HANDLE *pdev, uint8_t address) -{ - USB_OTG_DCFG_TypeDef dcfg; - dcfg.d32 = 0; - dcfg.b.devaddr = address; - USB_OTG_MODIFY_REG32( &pdev->regs.DREGS->DCFG, 0, dcfg.d32); -} - -/** -* @brief Connect device (enable internal pull-up) -* @param pdev: device instance -* @retval : None -*/ -void DCD_DevConnect (USB_OTG_CORE_HANDLE *pdev) -{ -#ifndef USE_OTG_MODE - USB_OTG_DCTL_TypeDef dctl; - dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); - /* Connect device */ - dctl.b.sftdiscon = 0; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32); - USB_OTG_BSP_mDelay(3); -#endif -} - - -/** -* @brief Disconnect device (disable internal pull-up) -* @param pdev: device instance -* @retval : None -*/ -void DCD_DevDisconnect (USB_OTG_CORE_HANDLE *pdev) -{ -#ifndef USE_OTG_MODE - USB_OTG_DCTL_TypeDef dctl; - dctl.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DCTL); - /* Disconnect device for 3ms */ - dctl.b.sftdiscon = 1; - USB_OTG_WRITE_REG32(&pdev->regs.DREGS->DCTL, dctl.d32); - USB_OTG_BSP_mDelay(3); -#endif -} - - -/** -* @brief returns the EP Status -* @param pdev : Selected device -* epnum : endpoint address -* @retval : EP status -*/ - -uint32_t DCD_GetEPStatus(USB_OTG_CORE_HANDLE *pdev ,uint8_t epnum) -{ - USB_OTG_EP *ep; - uint32_t Status = 0; - - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - Status = USB_OTG_GetEPStatus(pdev ,ep); - - /* Return the current status */ - return Status; -} - -/** -* @brief Set the EP Status -* @param pdev : Selected device -* Status : new Status -* epnum : EP address -* @retval : None -*/ -void DCD_SetEPStatus (USB_OTG_CORE_HANDLE *pdev , uint8_t epnum , uint32_t Status) -{ - USB_OTG_EP *ep; - - if ((0x80 & epnum) == 0x80) - { - ep = &pdev->dev.in_ep[epnum & 0x7F]; - } - else - { - ep = &pdev->dev.out_ep[epnum]; - } - - USB_OTG_SetEPStatus(pdev ,ep , Status); -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_OTG_Driver/src/usb_dcd_int.c b/example/stm32f4/STM32_USB_OTG_Driver/src/usb_dcd_int.c deleted file mode 100644 index eac902edc..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/src/usb_dcd_int.c +++ /dev/null @@ -1,886 +0,0 @@ -/** - ****************************************************************************** - * @file usb_dcd_int.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Peripheral Device interrupt subroutines - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_dcd_int.h" -/** @addtogroup USB_OTG_DRIVER -* @{ -*/ - -/** @defgroup USB_DCD_INT -* @brief This file contains the interrupt subroutines for the Device mode. -* @{ -*/ - - -/** @defgroup USB_DCD_INT_Private_Defines -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_TypesDefinitions -* @{ -*/ -/** -* @} -*/ - - - -/** @defgroup USB_DCD_INT_Private_Macros -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_Variables -* @{ -*/ -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_FunctionPrototypes -* @{ -*/ -/* static functions */ -static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum); - -/* Interrupt Handlers */ -static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev); - -static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev , uint32_t epnum); - -static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev); - -static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev); -#ifdef VBUS_SENSING_ENABLED -static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev); -#endif - -/** -* @} -*/ - - -/** @defgroup USB_DCD_INT_Private_Functions -* @{ -*/ - - -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED -/** -* @brief USBD_OTG_EP1OUT_ISR_Handler -* handles all USB Interrupts -* @param pdev: device instance -* @retval status -*/ -uint32_t USBD_OTG_EP1OUT_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_DOEPINTn_TypeDef doepint; - USB_OTG_DEPXFRSIZ_TypeDef deptsiz; - - doepint.d32 = USB_OTG_READ_REG32(&pdev->regs.OUTEP_REGS[1]->DOEPINT); - doepint.d32&= USB_OTG_READ_REG32(&pdev->regs.DREGS->DOUTEP1MSK); - - /* Transfer complete */ - if ( doepint.b.xfercompl ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(1, xfercompl); - if (pdev->cfg.dma_enable == 1) - { - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[1]->DOEPTSIZ)); - /*ToDo : handle more than one single MPS size packet */ - pdev->dev.out_ep[1].xfer_count = pdev->dev.out_ep[1].maxpacket - \ - deptsiz.b.xfersize; - } - /* Inform upper layer: data ready */ - /* RX COMPLETE */ - USBD_DCD_INT_fops->DataOutStage(pdev , 1); - - } - - /* Endpoint disable */ - if ( doepint.b.epdisabled ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(1, epdisabled); - } - /* AHB Error */ - if ( doepint.b.ahberr ) - { - CLEAR_OUT_EP_INTR(1, ahberr); - } - return 1; -} - -/** -* @brief USBD_OTG_EP1IN_ISR_Handler -* handles all USB Interrupts -* @param pdev: device instance -* @retval status -*/ -uint32_t USBD_OTG_EP1IN_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_DIEPINTn_TypeDef diepint; - uint32_t fifoemptymsk, msk, emp; - - msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DINEP1MSK); - emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK); - msk |= ((emp >> 1 ) & 0x1) << 7; - diepint.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[1]->DIEPINT) & msk; - - if ( diepint.b.xfercompl ) - { - fifoemptymsk = 0x1 << 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0); - CLEAR_IN_EP_INTR(1, xfercompl); - /* TX COMPLETE */ - USBD_DCD_INT_fops->DataInStage(pdev , 1); - } - if ( diepint.b.ahberr ) - { - CLEAR_IN_EP_INTR(1, ahberr); - } - if ( diepint.b.epdisabled ) - { - CLEAR_IN_EP_INTR(1, epdisabled); - } - if ( diepint.b.timeout ) - { - CLEAR_IN_EP_INTR(1, timeout); - } - if (diepint.b.intktxfemp) - { - CLEAR_IN_EP_INTR(1, intktxfemp); - } - if (diepint.b.intknepmis) - { - CLEAR_IN_EP_INTR(1, intknepmis); - } - if (diepint.b.inepnakeff) - { - CLEAR_IN_EP_INTR(1, inepnakeff); - } - if (diepint.b.emptyintr) - { - DCD_WriteEmptyTxFifo(pdev , 1); - CLEAR_IN_EP_INTR(1, emptyintr); - } - return 1; -} -#endif - -/** -* @brief STM32_USBF_OTG_ISR_Handler -* handles all USB Interrupts -* @param pdev: device instance -* @retval status -*/ -uint32_t USBD_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintr_status; - uint32_t retval = 0; - - if (USB_OTG_IsDeviceMode(pdev)) /* ensure that we are in device mode */ - { - gintr_status.d32 = USB_OTG_ReadCoreItr(pdev); - if (!gintr_status.d32) /* avoid spurious interrupt */ - { - return 0; - } - - if (gintr_status.b.outepintr) - { - retval |= DCD_HandleOutEP_ISR(pdev); - } - - if (gintr_status.b.inepint) - { - retval |= DCD_HandleInEP_ISR(pdev); - } - - if (gintr_status.b.modemismatch) - { - USB_OTG_GINTSTS_TypeDef gintsts; - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.modemismatch = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - } - - if (gintr_status.b.wkupintr) - { - retval |= DCD_HandleResume_ISR(pdev); - } - - if (gintr_status.b.usbsuspend) - { - retval |= DCD_HandleUSBSuspend_ISR(pdev); - } - if (gintr_status.b.sofintr) - { - retval |= DCD_HandleSof_ISR(pdev); - - } - - if (gintr_status.b.rxstsqlvl) - { - retval |= DCD_HandleRxStatusQueueLevel_ISR(pdev); - - } - - if (gintr_status.b.usbreset) - { - retval |= DCD_HandleUsbReset_ISR(pdev); - - } - if (gintr_status.b.enumdone) - { - retval |= DCD_HandleEnumDone_ISR(pdev); - } - - if (gintr_status.b.incomplisoin) - { - retval |= DCD_IsoINIncomplete_ISR(pdev); - } - - if (gintr_status.b.incomplisoout) - { - retval |= DCD_IsoOUTIncomplete_ISR(pdev); - } -#ifdef VBUS_SENSING_ENABLED - if (gintr_status.b.sessreqintr) - { - retval |= DCD_SessionRequest_ISR(pdev); - } - - if (gintr_status.b.otgintr) - { - retval |= DCD_OTG_ISR(pdev); - } -#endif - } - return retval; -} - -#ifdef VBUS_SENSING_ENABLED -/** -* @brief DCD_SessionRequest_ISR -* Indicates that the USB_OTG controller has detected a connection -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_SessionRequest_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USBD_DCD_INT_fops->DevConnected (pdev); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.sessreqintr = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} - -/** -* @brief DCD_OTG_ISR -* Indicates that the USB_OTG controller has detected an OTG event: -* used to detect the end of session i.e. disconnection -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_OTG_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_GOTGINT_TypeDef gotgint; - - gotgint.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GOTGINT); - - if (gotgint.b.sesenddet) - { - USBD_DCD_INT_fops->DevDisconnected (pdev); - } - /* Clear OTG interrupt */ - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GOTGINT, gotgint.d32); - return 1; -} -#endif -/** -* @brief DCD_HandleResume_ISR -* Indicates that the USB_OTG controller has detected a resume or -* remote Wake-up sequence -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_DCTL_TypeDef devctl; - USB_OTG_PCGCCTL_TypeDef power; - - if(pdev->cfg.low_power) - { - /* un-gate USB Core clock */ - power.d32 = USB_OTG_READ_REG32(&pdev->regs.PCGCCTL); - power.b.gatehclk = 0; - power.b.stoppclk = 0; - USB_OTG_WRITE_REG32(pdev->regs.PCGCCTL, power.d32); - } - - /* Clear the Remote Wake-up Signaling */ - devctl.d32 = 0; - devctl.b.rmtwkupsig = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, devctl.d32, 0); - - /* Inform upper layer by the Resume Event */ - USBD_DCD_INT_fops->Resume (pdev); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.wkupintr = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} - -/** -* @brief USB_OTG_HandleUSBSuspend_ISR -* Indicates that SUSPEND state has been detected on the USB -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleUSBSuspend_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_PCGCCTL_TypeDef power; - USB_OTG_DSTS_TypeDef dsts; - - USBD_DCD_INT_fops->Suspend (pdev); - - dsts.d32 = USB_OTG_READ_REG32(&pdev->regs.DREGS->DSTS); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.usbsuspend = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - if((pdev->cfg.low_power) && (dsts.b.suspsts == 1)) - { - /* switch-off the clocks */ - power.d32 = 0; - power.b.stoppclk = 1; - USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32); - - power.b.gatehclk = 1; - USB_OTG_MODIFY_REG32(pdev->regs.PCGCCTL, 0, power.d32); - - /* Request to enter Sleep mode after exit from current ISR */ - SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk | SCB_SCR_SLEEPONEXIT_Msk); - } - return 1; -} - -/** -* @brief DCD_HandleInEP_ISR -* Indicates that an IN EP has a pending Interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleInEP_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DIEPINTn_TypeDef diepint; - - uint32_t ep_intr; - uint32_t epnum = 0; - uint32_t fifoemptymsk; - diepint.d32 = 0; - ep_intr = USB_OTG_ReadDevAllInEPItr(pdev); - - while ( ep_intr ) - { - if (ep_intr&0x1) /* In ITR */ - { - diepint.d32 = DCD_ReadDevInEP(pdev , epnum); /* Get In ITR status */ - if ( diepint.b.xfercompl ) - { - fifoemptymsk = 0x1 << epnum; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DIEPEMPMSK, fifoemptymsk, 0); - CLEAR_IN_EP_INTR(epnum, xfercompl); - /* TX COMPLETE */ - USBD_DCD_INT_fops->DataInStage(pdev , epnum); - - if (pdev->cfg.dma_enable == 1) - { - if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_IN)) - { - /* prepare to rx more setup packets */ - USB_OTG_EP0_OutStart(pdev); - } - } - } - if ( diepint.b.ahberr ) - { - CLEAR_IN_EP_INTR(epnum, ahberr); - } - if ( diepint.b.timeout ) - { - CLEAR_IN_EP_INTR(epnum, timeout); - } - if (diepint.b.intktxfemp) - { - CLEAR_IN_EP_INTR(epnum, intktxfemp); - } - if (diepint.b.intknepmis) - { - CLEAR_IN_EP_INTR(epnum, intknepmis); - } - if (diepint.b.inepnakeff) - { - CLEAR_IN_EP_INTR(epnum, inepnakeff); - } - if ( diepint.b.epdisabled ) - { - CLEAR_IN_EP_INTR(epnum, epdisabled); - } - if (diepint.b.emptyintr) - { - - DCD_WriteEmptyTxFifo(pdev , epnum); - - CLEAR_IN_EP_INTR(epnum, emptyintr); - } - } - epnum++; - ep_intr >>= 1; - } - - return 1; -} - -/** -* @brief DCD_HandleOutEP_ISR -* Indicates that an OUT EP has a pending Interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleOutEP_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t ep_intr; - USB_OTG_DOEPINTn_TypeDef doepint; - USB_OTG_DEPXFRSIZ_TypeDef deptsiz; - uint32_t epnum = 0; - - doepint.d32 = 0; - - /* Read in the device interrupt bits */ - ep_intr = USB_OTG_ReadDevAllOutEp_itr(pdev); - - while ( ep_intr ) - { - if (ep_intr&0x1) - { - - doepint.d32 = USB_OTG_ReadDevOutEP_itr(pdev, epnum); - - /* Transfer complete */ - if ( doepint.b.xfercompl ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(epnum, xfercompl); - if (pdev->cfg.dma_enable == 1) - { - deptsiz.d32 = USB_OTG_READ_REG32(&(pdev->regs.OUTEP_REGS[epnum]->DOEPTSIZ)); - /*ToDo : handle more than one single MPS size packet */ - pdev->dev.out_ep[epnum].xfer_count = pdev->dev.out_ep[epnum].maxpacket - \ - deptsiz.b.xfersize; - } - /* Inform upper layer: data ready */ - /* RX COMPLETE */ - USBD_DCD_INT_fops->DataOutStage(pdev , epnum); - - if (pdev->cfg.dma_enable == 1) - { - if((epnum == 0) && (pdev->dev.device_state == USB_OTG_EP0_STATUS_OUT)) - { - /* prepare to rx more setup packets */ - USB_OTG_EP0_OutStart(pdev); - } - } - } - /* Endpoint disable */ - if ( doepint.b.epdisabled ) - { - /* Clear the bit in DOEPINTn for this interrupt */ - CLEAR_OUT_EP_INTR(epnum, epdisabled); - } - /* AHB Error */ - if ( doepint.b.ahberr ) - { - CLEAR_OUT_EP_INTR(epnum, ahberr); - } - /* Setup Phase Done (control EPs) */ - if ( doepint.b.setup ) - { - - /* inform the upper layer that a setup packet is available */ - /* SETUP COMPLETE */ - USBD_DCD_INT_fops->SetupStage(pdev); - CLEAR_OUT_EP_INTR(epnum, setup); - } - } - epnum++; - ep_intr >>= 1; - } - return 1; -} - -/** -* @brief DCD_HandleSof_ISR -* Handles the SOF Interrupts -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleSof_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef GINTSTS; - - - USBD_DCD_INT_fops->SOF(pdev); - - /* Clear interrupt */ - GINTSTS.d32 = 0; - GINTSTS.b.sofintr = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, GINTSTS.d32); - - return 1; -} - -/** -* @brief DCD_HandleRxStatusQueueLevel_ISR -* Handles the Rx Status Queue Level Interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleRxStatusQueueLevel_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef int_mask; - USB_OTG_DRXSTS_TypeDef status; - USB_OTG_EP *ep; - - /* Disable the Rx Status Queue Level interrupt */ - int_mask.d32 = 0; - int_mask.b.rxstsqlvl = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, int_mask.d32, 0); - - /* Get the Status from the top of the FIFO */ - status.d32 = USB_OTG_READ_REG32( &pdev->regs.GREGS->GRXSTSP ); - - ep = &pdev->dev.out_ep[status.b.epnum]; - - switch (status.b.pktsts) - { - case STS_GOUT_NAK: - break; - case STS_DATA_UPDT: - if (status.b.bcnt) - { - USB_OTG_ReadPacket(pdev,ep->xfer_buff, status.b.bcnt); - ep->xfer_buff += status.b.bcnt; - ep->xfer_count += status.b.bcnt; - } - break; - case STS_XFER_COMP: - break; - case STS_SETUP_COMP: - break; - case STS_SETUP_UPDT: - /* Copy the setup packet received in FIFO into the setup buffer in RAM */ - USB_OTG_ReadPacket(pdev , pdev->dev.setup_packet, 8); - ep->xfer_count += status.b.bcnt; - break; - default: - break; - } - - /* Enable the Rx Status Queue Level interrupt */ - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, 0, int_mask.d32); - - return 1; -} - -/** -* @brief DCD_WriteEmptyTxFifo -* check FIFO for the next packet to be loaded -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_WriteEmptyTxFifo(USB_OTG_CORE_HANDLE *pdev, uint32_t epnum) -{ - USB_OTG_DTXFSTSn_TypeDef txstatus; - USB_OTG_EP *ep; - uint32_t len = 0; - uint32_t len32b; - txstatus.d32 = 0; - - ep = &pdev->dev.in_ep[epnum]; - - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - - len32b = (len + 3) / 4; - txstatus.d32 = USB_OTG_READ_REG32( &pdev->regs.INEP_REGS[epnum]->DTXFSTS); - - - - while (txstatus.b.txfspcavail > len32b && - ep->xfer_count < ep->xfer_len && - ep->xfer_len != 0) - { - /* Write the FIFO */ - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - len32b = (len + 3) / 4; - - USB_OTG_WritePacket (pdev , ep->xfer_buff, epnum, len); - - ep->xfer_buff += len; - ep->xfer_count += len; - - txstatus.d32 = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DTXFSTS); - } - - return 1; -} - -/** -* @brief DCD_HandleUsbReset_ISR -* This interrupt occurs when a USB Reset is detected -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleUsbReset_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_DAINT_TypeDef daintmsk; - USB_OTG_DOEPMSK_TypeDef doepmsk; - USB_OTG_DIEPMSK_TypeDef diepmsk; - USB_OTG_DCFG_TypeDef dcfg; - USB_OTG_DCTL_TypeDef dctl; - USB_OTG_GINTSTS_TypeDef gintsts; - uint32_t i; - - dctl.d32 = 0; - daintmsk.d32 = 0; - doepmsk.d32 = 0; - diepmsk.d32 = 0; - dcfg.d32 = 0; - gintsts.d32 = 0; - - /* Clear the Remote Wake-up Signaling */ - dctl.b.rmtwkupsig = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.DREGS->DCTL, dctl.d32, 0 ); - - /* Flush the Tx FIFO */ - USB_OTG_FlushTxFifo(pdev , 0 ); - - for (i = 0; i < pdev->cfg.dev_endpoints ; i++) - { - USB_OTG_WRITE_REG32( &pdev->regs.INEP_REGS[i]->DIEPINT, 0xFF); - USB_OTG_WRITE_REG32( &pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFF); - } - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINT, 0xFFFFFFFF ); - - daintmsk.ep.in = 1; - daintmsk.ep.out = 1; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DAINTMSK, daintmsk.d32 ); - - doepmsk.b.setup = 1; - doepmsk.b.xfercompl = 1; - doepmsk.b.ahberr = 1; - doepmsk.b.epdisabled = 1; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOEPMSK, doepmsk.d32 ); -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DOUTEP1MSK, doepmsk.d32 ); -#endif - diepmsk.b.xfercompl = 1; - diepmsk.b.timeout = 1; - diepmsk.b.epdisabled = 1; - diepmsk.b.ahberr = 1; - diepmsk.b.intknepmis = 1; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DIEPMSK, diepmsk.d32 ); -#ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DINEP1MSK, diepmsk.d32 ); -#endif - /* Reset Device Address */ - dcfg.d32 = USB_OTG_READ_REG32( &pdev->regs.DREGS->DCFG); - dcfg.b.devaddr = 0; - USB_OTG_WRITE_REG32( &pdev->regs.DREGS->DCFG, dcfg.d32); - - - /* setup EP0 to receive SETUP packets */ - USB_OTG_EP0_OutStart(pdev); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.usbreset = 1; - USB_OTG_WRITE_REG32 (&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - /*Reset internal state machine */ - USBD_DCD_INT_fops->Reset(pdev); - return 1; -} - -/** -* @brief DCD_HandleEnumDone_ISR -* Read the device status register and set the device speed -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_HandleEnumDone_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_GUSBCFG_TypeDef gusbcfg; - - USB_OTG_EP0Activate(pdev); - - /* Set USB turn-around time based on device speed and PHY interface. */ - gusbcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GUSBCFG); - - /* Full or High speed */ - if ( USB_OTG_GetDeviceSpeed(pdev) == USB_SPEED_HIGH) - { - pdev->cfg.speed = USB_OTG_SPEED_HIGH; - pdev->cfg.mps = USB_OTG_HS_MAX_PACKET_SIZE ; - gusbcfg.b.usbtrdtim = 9; - } - else - { - pdev->cfg.speed = USB_OTG_SPEED_FULL; - pdev->cfg.mps = USB_OTG_FS_MAX_PACKET_SIZE ; - gusbcfg.b.usbtrdtim = 5; - } - - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GUSBCFG, gusbcfg.d32); - - /* Clear interrupt */ - gintsts.d32 = 0; - gintsts.b.enumdone = 1; - USB_OTG_WRITE_REG32( &pdev->regs.GREGS->GINTSTS, gintsts.d32 ); - return 1; -} - - -/** -* @brief DCD_IsoINIncomplete_ISR -* handle the ISO IN incomplete interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_IsoINIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - - gintsts.d32 = 0; - - USBD_DCD_INT_fops->IsoINIncomplete (pdev); - - /* Clear interrupt */ - gintsts.b.incomplisoin = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - return 1; -} - -/** -* @brief DCD_IsoOUTIncomplete_ISR -* handle the ISO OUT incomplete interrupt -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_IsoOUTIncomplete_ISR(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - - gintsts.d32 = 0; - - USBD_DCD_INT_fops->IsoOUTIncomplete (pdev); - - /* Clear interrupt */ - gintsts.b.incomplisoout = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - return 1; -} -/** -* @brief DCD_ReadDevInEP -* Reads ep flags -* @param pdev: device instance -* @retval status -*/ -static uint32_t DCD_ReadDevInEP (USB_OTG_CORE_HANDLE *pdev, uint8_t epnum) -{ - uint32_t v, msk, emp; - msk = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPMSK); - emp = USB_OTG_READ_REG32(&pdev->regs.DREGS->DIEPEMPMSK); - msk |= ((emp >> epnum) & 0x1) << 7; - v = USB_OTG_READ_REG32(&pdev->regs.INEP_REGS[epnum]->DIEPINT) & msk; - return v; -} - - - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_OTG_Driver/src/usb_hcd.c b/example/stm32f4/STM32_USB_OTG_Driver/src/usb_hcd.c deleted file mode 100644 index 689d061ae..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/src/usb_hcd.c +++ /dev/null @@ -1,256 +0,0 @@ -/** - ****************************************************************************** - * @file usb_hcd.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Host Interface Layer - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" -#include "usb_hcd.h" -#include "usb_conf.h" -#include "usb_bsp.h" - - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_HCD - * @brief This file is the interface between EFSL ans Host mass-storage class - * @{ - */ - - -/** @defgroup USB_HCD_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USB_HCD_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Private_FunctionPrototypes - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_Private_Functions - * @{ - */ - -/** - * @brief HCD_Init - * Initialize the HOST portion of the driver. - * @param pdev: Selected device - * @param base_address: OTG base address - * @retval Status - */ -uint32_t HCD_Init(USB_OTG_CORE_HANDLE *pdev , - USB_OTG_CORE_ID_TypeDef coreID) -{ - uint8_t i = 0; - pdev->host.ConnSts = 0; - - for (i= 0; i< USB_OTG_MAX_TX_FIFOS; i++) - { - pdev->host.ErrCnt[i] = 0; - pdev->host.XferCnt[i] = 0; - pdev->host.HC_Status[i] = HC_IDLE; - } - pdev->host.hc[0].max_packet = 8; - - USB_OTG_SelectCore(pdev, coreID); -#ifndef DUAL_ROLE_MODE_ENABLED - USB_OTG_DisableGlobalInt(pdev); - USB_OTG_CoreInit(pdev); - - /* Force Host Mode*/ - USB_OTG_SetCurrentMode(pdev , HOST_MODE); - USB_OTG_CoreInitHost(pdev); - USB_OTG_EnableGlobalInt(pdev); -#endif - - return 0; -} - - -/** - * @brief HCD_GetCurrentSpeed - * Get Current device Speed. - * @param pdev : Selected device - * @retval Status - */ - -uint32_t HCD_GetCurrentSpeed (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef HPRT0; - HPRT0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); - - return HPRT0.b.prtspd; -} - -/** - * @brief HCD_ResetPort - * Issues the reset command to device - * @param pdev : Selected device - * @retval Status - */ -uint32_t HCD_ResetPort(USB_OTG_CORE_HANDLE *pdev) -{ - /* - Before starting to drive a USB reset, the application waits for the OTG - interrupt triggered by the debounce done bit (DBCDNE bit in OTG_FS_GOTGINT), - which indicates that the bus is stable again after the electrical debounce - caused by the attachment of a pull-up resistor on DP (FS) or DM (LS). - */ - - USB_OTG_ResetPort(pdev); - return 0; -} - -/** - * @brief HCD_IsDeviceConnected - * Check if the device is connected. - * @param pdev : Selected device - * @retval Device connection status. 1 -> connected and 0 -> disconnected - * - */ -uint32_t HCD_IsDeviceConnected(USB_OTG_CORE_HANDLE *pdev) -{ - return (pdev->host.ConnSts); -} - -/** - * @brief HCD_GetCurrentFrame - * This function returns the frame number for sof packet - * @param pdev : Selected device - * @retval Frame number - * - */ -uint32_t HCD_GetCurrentFrame (USB_OTG_CORE_HANDLE *pdev) -{ - return (USB_OTG_READ_REG32(&pdev->regs.HREGS->HFNUM) & 0xFFFF) ; -} - -/** - * @brief HCD_GetURB_State - * This function returns the last URBstate - * @param pdev: Selected device - * @retval URB_STATE - * - */ -URB_STATE HCD_GetURB_State (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num) -{ - return pdev->host.URB_State[ch_num] ; -} - -/** - * @brief HCD_GetXferCnt - * This function returns the last URBstate - * @param pdev: Selected device - * @retval No. of data bytes transferred - * - */ -uint32_t HCD_GetXferCnt (USB_OTG_CORE_HANDLE *pdev, uint8_t ch_num) -{ - return pdev->host.XferCnt[ch_num] ; -} - - - -/** - * @brief HCD_GetHCState - * This function returns the HC Status - * @param pdev: Selected device - * @retval HC_STATUS - * - */ -HC_STATUS HCD_GetHCState (USB_OTG_CORE_HANDLE *pdev , uint8_t ch_num) -{ - return pdev->host.HC_Status[ch_num] ; -} - -/** - * @brief HCD_HC_Init - * This function prepare a HC and start a transfer - * @param pdev: Selected device - * @param hc_num: Channel number - * @retval status - */ -uint32_t HCD_HC_Init (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - return USB_OTG_HC_Init(pdev, hc_num); -} - -/** - * @brief HCD_SubmitRequest - * This function prepare a HC and start a transfer - * @param pdev: Selected device - * @param hc_num: Channel number - * @retval status - */ -uint32_t HCD_SubmitRequest (USB_OTG_CORE_HANDLE *pdev , uint8_t hc_num) -{ - - pdev->host.URB_State[hc_num] = URB_IDLE; - pdev->host.hc[hc_num].xfer_count = 0 ; - return USB_OTG_HC_StartXfer(pdev, hc_num); -} - - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/STM32_USB_OTG_Driver/src/usb_hcd_int.c b/example/stm32f4/STM32_USB_OTG_Driver/src/usb_hcd_int.c deleted file mode 100644 index bd4081fb3..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/src/usb_hcd_int.c +++ /dev/null @@ -1,832 +0,0 @@ -/** - ****************************************************************************** - * @file usb_hcd_int.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief Host driver interrupt subroutines - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_core.h" -#include "usb_defines.h" -#include "usb_hcd_int.h" - -#if defined (__CC_ARM) /*!< ARM Compiler */ - #pragma O0 -#elif defined ( __ICCARM__ ) /*!< IAR Compiler */ - #pragma O0 -#elif defined (__GNUC__) /*!< GNU Compiler */ - #pragma GCC optimize ("O0") -#elif defined (__TASKING__) /*!< TASKING Compiler */ - #pragma optimize=0 - -#endif /* __CC_ARM */ - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_HCD_INT - * @brief This file contains the interrupt subroutines for the Host mode. - * @{ - */ - - -/** @defgroup USB_HCD_INT_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_INT_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USB_HCD_INT_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_INT_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_HCD_INT_Private_FunctionPrototypes - * @{ - */ - -static uint32_t USB_OTG_USBH_handle_sof_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_port_ISR(USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , - uint32_t num); -static uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , - uint32_t num); -static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev); -static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev); - -/** - * @} - */ - - -/** @defgroup USB_HCD_INT_Private_Functions - * @{ - */ - -/** - * @brief HOST_Handle_ISR - * This function handles all USB Host Interrupts - * @param pdev: Selected device - * @retval status - */ - -uint32_t USBH_OTG_ISR_Handler (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - uint32_t retval = 0; - - gintsts.d32 = 0; - - /* Check if HOST Mode */ - if (USB_OTG_IsHostMode(pdev)) - { - gintsts.d32 = USB_OTG_ReadCoreItr(pdev); - if (!gintsts.d32) - { - return 0; - } - - if (gintsts.b.sofintr) - { - retval |= USB_OTG_USBH_handle_sof_ISR (pdev); - } - - if (gintsts.b.rxstsqlvl) - { - retval |= USB_OTG_USBH_handle_rx_qlvl_ISR (pdev); - } - - if (gintsts.b.nptxfempty) - { - retval |= USB_OTG_USBH_handle_nptxfempty_ISR (pdev); - } - - if (gintsts.b.ptxfempty) - { - retval |= USB_OTG_USBH_handle_ptxfempty_ISR (pdev); - } - - if (gintsts.b.hcintr) - { - retval |= USB_OTG_USBH_handle_hc_ISR (pdev); - } - - if (gintsts.b.portintr) - { - retval |= USB_OTG_USBH_handle_port_ISR (pdev); - } - - if (gintsts.b.disconnect) - { - retval |= USB_OTG_USBH_handle_Disconnect_ISR (pdev); - - } - - if (gintsts.b.incomplisoout) - { - retval |= USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (pdev); - } - - - } - return retval; -} - -/** - * @brief USB_OTG_USBH_handle_hc_ISR - * This function indicates that one or more host channels has a pending - * @param pdev: Selected device - * @retval status - */ -static uint32_t USB_OTG_USBH_handle_hc_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HAINT_TypeDef haint; - USB_OTG_HCCHAR_TypeDef hcchar; - uint32_t i = 0; - uint32_t retval = 0; - - /* Clear appropriate bits in HCINTn to clear the interrupt bit in - * GINTSTS */ - - haint.d32 = USB_OTG_ReadHostAllChannels_intr(pdev); - - for (i = 0; i < pdev->cfg.host_channels ; i++) - { - if (haint.b.chint & (1 << i)) - { - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[i]->HCCHAR); - - if (hcchar.b.epdir) - { - retval |= USB_OTG_USBH_handle_hc_n_In_ISR (pdev, i); - } - else - { - retval |= USB_OTG_USBH_handle_hc_n_Out_ISR (pdev, i); - } - } - } - - return retval; -} - -/** - * @brief USB_OTG_otg_hcd_handle_sof_intr - * Handles the start-of-frame interrupt in host mode. - * @param pdev: Selected device - * @retval status - */ -static uint32_t USB_OTG_USBH_handle_sof_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - - - gintsts.d32 = 0; - /* Clear interrupt */ - gintsts.b.sofintr = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - return 1; -} - -/** - * @brief USB_OTG_USBH_handle_Disconnect_ISR - * Handles disconnect event. - * @param pdev: Selected device - * @retval status - */ -static uint32_t USB_OTG_USBH_handle_Disconnect_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - - pdev->host.ConnSts = 0; - gintsts.d32 = 0; - - pdev->host.port_cb->Disconnect(pdev); - - /* Clear interrupt */ - gintsts.b.disconnect = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - return 1; -} - -/** - * @brief USB_OTG_USBH_handle_nptxfempty_ISR - * Handles non periodic tx fifo empty. - * @param pdev: Selected device - * @retval status - */ -static uint32_t USB_OTG_USBH_handle_nptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef intmsk; - USB_OTG_HNPTXSTS_TypeDef hnptxsts; - uint16_t len_words , len; - - hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - - len_words = (pdev->host.hc[hnptxsts.b.chnum].xfer_len + 3) / 4; - - while ((hnptxsts.b.nptxfspcavail > len_words)&& - (pdev->host.hc[hnptxsts.b.chnum].xfer_len != 0)) - { - - len = hnptxsts.b.nptxfspcavail * 4; - - if (len > pdev->host.hc[hnptxsts.b.chnum].xfer_len) - { - /* Last packet */ - len = pdev->host.hc[hnptxsts.b.chnum].xfer_len; - - intmsk.d32 = 0; - intmsk.b.nptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); - } - - len_words = (pdev->host.hc[hnptxsts.b.chnum].xfer_len + 3) / 4; - - USB_OTG_WritePacket (pdev , pdev->host.hc[hnptxsts.b.chnum].xfer_buff, hnptxsts.b.chnum, len); - - pdev->host.hc[hnptxsts.b.chnum].xfer_buff += len; - pdev->host.hc[hnptxsts.b.chnum].xfer_len -= len; - pdev->host.hc[hnptxsts.b.chnum].xfer_count += len; - - hnptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->HNPTXSTS); - } - - return 1; -} - -/** - * @brief USB_OTG_USBH_handle_ptxfempty_ISR - * Handles periodic tx fifo empty - * @param pdev: Selected device - * @retval status - */ -static uint32_t USB_OTG_USBH_handle_ptxfempty_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTMSK_TypeDef intmsk; - USB_OTG_HPTXSTS_TypeDef hptxsts; - uint16_t len_words , len; - - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - - len_words = (pdev->host.hc[hptxsts.b.chnum].xfer_len + 3) / 4; - - while ((hptxsts.b.ptxfspcavail > len_words)&& - (pdev->host.hc[hptxsts.b.chnum].xfer_len != 0)) - { - - len = hptxsts.b.ptxfspcavail * 4; - - if (len > pdev->host.hc[hptxsts.b.chnum].xfer_len) - { - len = pdev->host.hc[hptxsts.b.chnum].xfer_len; - /* Last packet */ - intmsk.d32 = 0; - intmsk.b.ptxfempty = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); - } - - len_words = (pdev->host.hc[hptxsts.b.chnum].xfer_len + 3) / 4; - - USB_OTG_WritePacket (pdev , pdev->host.hc[hptxsts.b.chnum].xfer_buff, hptxsts.b.chnum, len); - - pdev->host.hc[hptxsts.b.chnum].xfer_buff += len; - pdev->host.hc[hptxsts.b.chnum].xfer_len -= len; - pdev->host.hc[hptxsts.b.chnum].xfer_count += len; - - hptxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HPTXSTS); - } - - return 1; -} - -/** - * @brief USB_OTG_USBH_handle_port_ISR - * This function determines which interrupt conditions have occurred - * @param pdev: Selected device - * @retval status - */ -static uint32_t USB_OTG_USBH_handle_port_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_HPRT0_TypeDef hprt0; - USB_OTG_HPRT0_TypeDef hprt0_dup; - USB_OTG_HCFG_TypeDef hcfg; - uint32_t do_reset = 0; - uint32_t retval = 0; - - hcfg.d32 = 0; - hprt0.d32 = 0; - hprt0_dup.d32 = 0; - - hprt0.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); - hprt0_dup.d32 = USB_OTG_READ_REG32(pdev->regs.HPRT0); - - /* Clear the interrupt bits in GINTSTS */ - - hprt0_dup.b.prtena = 0; - hprt0_dup.b.prtconndet = 0; - hprt0_dup.b.prtenchng = 0; - hprt0_dup.b.prtovrcurrchng = 0; - - /* Port Connect Detected */ - if (hprt0.b.prtconndet) - { - pdev->host.port_cb->Connect(pdev); - hprt0_dup.b.prtconndet = 1; - do_reset = 1; - retval |= 1; - } - - /* Port Enable Changed */ - if (hprt0.b.prtenchng) - { - hprt0_dup.b.prtenchng = 1; - if (hprt0.b.prtena == 1) - { - pdev->host.ConnSts = 1; - - if ((hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED) || - (hprt0.b.prtspd == HPRT0_PRTSPD_FULL_SPEED)) - { - - hcfg.d32 = USB_OTG_READ_REG32(&pdev->regs.HREGS->HCFG); - - if (hprt0.b.prtspd == HPRT0_PRTSPD_LOW_SPEED) - { - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 6000 ); - if (hcfg.b.fslspclksel != HCFG_6_MHZ) - { - if(pdev->cfg.coreID == USB_OTG_FS_CORE_ID) - { - USB_OTG_InitFSLSPClkSel(pdev ,HCFG_6_MHZ ); - } - do_reset = 1; - } - } - else - { - - USB_OTG_WRITE_REG32(&pdev->regs.HREGS->HFIR, 48000 ); - if (hcfg.b.fslspclksel != HCFG_48_MHZ) - { - USB_OTG_InitFSLSPClkSel(pdev ,HCFG_48_MHZ ); - do_reset = 1; - } - } - } - else - { - do_reset = 1; - } - } - } - /* Overcurrent Change Interrupt */ - if (hprt0.b.prtovrcurrchng) - { - hprt0_dup.b.prtovrcurrchng = 1; - retval |= 1; - } - if (do_reset) - { - USB_OTG_ResetPort(pdev); - - } - /* Clear Port Interrupts */ - USB_OTG_WRITE_REG32(pdev->regs.HPRT0, hprt0_dup.d32); - - return retval; -} - -/** - * @brief USB_OTG_USBH_handle_hc_n_Out_ISR - * Handles interrupt for a specific Host Channel - * @param pdev: Selected device - * @param hc_num: Channel number - * @retval status - */ -uint32_t USB_OTG_USBH_handle_hc_n_Out_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num) -{ - - USB_OTG_HCINTn_TypeDef hcint; - USB_OTG_HCGINTMSK_TypeDef hcintmsk; - USB_OTG_HC_REGS *hcreg; - USB_OTG_HCCHAR_TypeDef hcchar; - - hcreg = pdev->regs.HC_REGS[num]; - hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT); - hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCGINTMSK); - hcint.d32 = hcint.d32 & hcintmsk.d32; - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR); - - if (hcint.b.ahberr) - { - CLEAR_HC_INT(hcreg ,ahberr); - UNMASK_HOST_INT_CHH (num); - } - else if (hcint.b.ack) - { - CLEAR_HC_INT(hcreg , ack); - } - - else if (hcint.b.xfercompl) - { - pdev->host.ErrCnt[num] = 0; - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , xfercompl); - pdev->host.HC_Status[num] = HC_XFRC; - } - - else if (hcint.b.stall) - { - CLEAR_HC_INT(hcreg , stall); - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - pdev->host.HC_Status[num] = HC_STALL; - } - - else if (hcint.b.nak) - { - pdev->host.ErrCnt[num] = 0; - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , nak); - pdev->host.HC_Status[num] = HC_NAK; - } - - else if (hcint.b.xacterr) - { - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - pdev->host.ErrCnt[num] ++; - pdev->host.HC_Status[num] = HC_XACTERR; - CLEAR_HC_INT(hcreg , xacterr); - } - else if (hcint.b.nyet) - { - pdev->host.ErrCnt[num] = 0; - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , nyet); - pdev->host.HC_Status[num] = HC_NYET; - } - else if (hcint.b.datatglerr) - { - - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , nak); - pdev->host.HC_Status[num] = HC_DATATGLERR; - - CLEAR_HC_INT(hcreg , datatglerr); - } - else if (hcint.b.chhltd) - { - MASK_HOST_INT_CHH (num); - - if(pdev->host.HC_Status[num] == HC_XFRC) - { - pdev->host.URB_State[num] = URB_DONE; - - if (hcchar.b.eptype == EP_TYPE_BULK) - { - pdev->host.hc[num].toggle_out ^= 1; - } - } - else if(pdev->host.HC_Status[num] == HC_NAK) - { - pdev->host.URB_State[num] = URB_NOTREADY; - } - else if(pdev->host.HC_Status[num] == HC_NYET) - { - if(pdev->host.hc[num].do_ping == 1) - { - USB_OTG_HC_DoPing(pdev, num); - } - pdev->host.URB_State[num] = URB_NOTREADY; - } - else if(pdev->host.HC_Status[num] == HC_STALL) - { - pdev->host.URB_State[num] = URB_STALL; - } - else if(pdev->host.HC_Status[num] == HC_XACTERR) - { - if (pdev->host.ErrCnt[num] == 3) - { - pdev->host.URB_State[num] = URB_ERROR; - pdev->host.ErrCnt[num] = 0; - } - } - CLEAR_HC_INT(hcreg , chhltd); - } - - - return 1; -} - -/** - * @brief USB_OTG_USBH_handle_hc_n_In_ISR - * Handles interrupt for a specific Host Channel - * @param pdev: Selected device - * @param hc_num: Channel number - * @retval status - */ -uint32_t USB_OTG_USBH_handle_hc_n_In_ISR (USB_OTG_CORE_HANDLE *pdev , uint32_t num) -{ - USB_OTG_HCINTn_TypeDef hcint; - USB_OTG_HCGINTMSK_TypeDef hcintmsk; - USB_OTG_HCCHAR_TypeDef hcchar; - USB_OTG_HCTSIZn_TypeDef hctsiz; - USB_OTG_HC_REGS *hcreg; - - - hcreg = pdev->regs.HC_REGS[num]; - hcint.d32 = USB_OTG_READ_REG32(&hcreg->HCINT); - hcintmsk.d32 = USB_OTG_READ_REG32(&hcreg->HCGINTMSK); - hcint.d32 = hcint.d32 & hcintmsk.d32; - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCCHAR); - hcintmsk.d32 = 0; - - - if (hcint.b.ahberr) - { - CLEAR_HC_INT(hcreg ,ahberr); - UNMASK_HOST_INT_CHH (num); - } - else if (hcint.b.ack) - { - CLEAR_HC_INT(hcreg ,ack); - } - - else if (hcint.b.stall) - { - UNMASK_HOST_INT_CHH (num); - pdev->host.HC_Status[num] = HC_STALL; - CLEAR_HC_INT(hcreg , nak); /* Clear the NAK Condition */ - CLEAR_HC_INT(hcreg , stall); /* Clear the STALL Condition */ - hcint.b.nak = 0; /* NOTE: When there is a 'stall', reset also nak, - else, the pdev->host.HC_Status = HC_STALL - will be overwritten by 'nak' in code below */ - USB_OTG_HC_Halt(pdev, num); - } - else if (hcint.b.datatglerr) - { - - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , nak); - pdev->host.HC_Status[num] = HC_DATATGLERR; - CLEAR_HC_INT(hcreg , datatglerr); - } - - if (hcint.b.frmovrun) - { - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg ,frmovrun); - } - - else if (hcint.b.xfercompl) - { - - if (pdev->cfg.dma_enable == 1) - { - hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[num]->HCTSIZ); - pdev->host.XferCnt[num] = pdev->host.hc[num].xfer_len - hctsiz.b.xfersize; - } - - pdev->host.HC_Status[num] = HC_XFRC; - pdev->host.ErrCnt [num]= 0; - CLEAR_HC_INT(hcreg , xfercompl); - - if ((hcchar.b.eptype == EP_TYPE_CTRL)|| - (hcchar.b.eptype == EP_TYPE_BULK)) - { - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , nak); - pdev->host.hc[num].toggle_in ^= 1; - - } - else if(hcchar.b.eptype == EP_TYPE_INTR) - { - hcchar.b.oddfrm = 1; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32); - pdev->host.URB_State[num] = URB_DONE; - } - - } - else if (hcint.b.chhltd) - { - MASK_HOST_INT_CHH (num); - - if(pdev->host.HC_Status[num] == HC_XFRC) - { - pdev->host.URB_State[num] = URB_DONE; - } - - else if (pdev->host.HC_Status[num] == HC_STALL) - { - pdev->host.URB_State[num] = URB_STALL; - } - - else if((pdev->host.HC_Status[num] == HC_XACTERR) || - (pdev->host.HC_Status[num] == HC_DATATGLERR)) - { - pdev->host.ErrCnt[num] = 0; - pdev->host.URB_State[num] = URB_ERROR; - - } - else if(hcchar.b.eptype == EP_TYPE_INTR) - { - pdev->host.hc[num].toggle_in ^= 1; - } - - CLEAR_HC_INT(hcreg , chhltd); - - } - else if (hcint.b.xacterr) - { - UNMASK_HOST_INT_CHH (num); - pdev->host.ErrCnt[num] ++; - pdev->host.HC_Status[num] = HC_XACTERR; - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , xacterr); - - } - else if (hcint.b.nak) - { - if(hcchar.b.eptype == EP_TYPE_INTR) - { - UNMASK_HOST_INT_CHH (num); - USB_OTG_HC_Halt(pdev, num); - CLEAR_HC_INT(hcreg , nak); - } - else if ((hcchar.b.eptype == EP_TYPE_CTRL)|| - (hcchar.b.eptype == EP_TYPE_BULK)) - { - /* re-activate the channel */ - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[num]->HCCHAR, hcchar.d32); - } - pdev->host.HC_Status[num] = HC_NAK; - } - - - return 1; - -} - -/** - * @brief USB_OTG_USBH_handle_rx_qlvl_ISR - * Handles the Rx Status Queue Level Interrupt - * @param pdev: Selected device - * @retval status - */ - -static uint32_t USB_OTG_USBH_handle_rx_qlvl_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GRXFSTS_TypeDef grxsts; - USB_OTG_GINTMSK_TypeDef intmsk; - USB_OTG_HCTSIZn_TypeDef hctsiz; - USB_OTG_HCCHAR_TypeDef hcchar; - __IO uint8_t channelnum =0; - uint32_t count; - - /* Disable the Rx Status Queue Level interrupt */ - intmsk.d32 = 0; - intmsk.b.rxstsqlvl = 1; - USB_OTG_MODIFY_REG32( &pdev->regs.GREGS->GINTMSK, intmsk.d32, 0); - - grxsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GRXSTSP); - channelnum = grxsts.b.chnum; - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR); - - switch (grxsts.b.pktsts) - { - case GRXSTS_PKTSTS_IN: - /* Read the data into the host buffer. */ - if ((grxsts.b.bcnt > 0) && (pdev->host.hc[channelnum].xfer_buff != (void *)0)) - { - - USB_OTG_ReadPacket(pdev, pdev->host.hc[channelnum].xfer_buff, grxsts.b.bcnt); - /*manage multiple Xfer */ - pdev->host.hc[grxsts.b.chnum].xfer_buff += grxsts.b.bcnt; - pdev->host.hc[grxsts.b.chnum].xfer_count += grxsts.b.bcnt; - - - count = pdev->host.hc[channelnum].xfer_count; - pdev->host.XferCnt[channelnum] = count; - - hctsiz.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[channelnum]->HCTSIZ); - if(hctsiz.b.pktcnt > 0) - { - /* re-activate the channel when more packets are expected */ - hcchar.b.chen = 1; - hcchar.b.chdis = 0; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[channelnum]->HCCHAR, hcchar.d32); - } - } - break; - - case GRXSTS_PKTSTS_IN_XFER_COMP: - - case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: - case GRXSTS_PKTSTS_CH_HALTED: - default: - break; - } - - /* Enable the Rx Status Queue Level interrupt */ - intmsk.b.rxstsqlvl = 1; - USB_OTG_MODIFY_REG32(&pdev->regs.GREGS->GINTMSK, 0, intmsk.d32); - return 1; -} - -/** - * @brief USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR - * Handles the incomplete Periodic transfer Interrupt - * @param pdev: Selected device - * @retval status - */ -static uint32_t USB_OTG_USBH_handle_IncompletePeriodicXfer_ISR (USB_OTG_CORE_HANDLE *pdev) -{ - - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_HCCHAR_TypeDef hcchar; - - - - - hcchar.d32 = USB_OTG_READ_REG32(&pdev->regs.HC_REGS[0]->HCCHAR); - hcchar.b.chen = 1; - hcchar.b.chdis = 1; - USB_OTG_WRITE_REG32(&pdev->regs.HC_REGS[0]->HCCHAR, hcchar.d32); - - gintsts.d32 = 0; - /* Clear interrupt */ - gintsts.b.incomplisoout = 1; - USB_OTG_WRITE_REG32(&pdev->regs.GREGS->GINTSTS, gintsts.d32); - - return 1; -} - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ - diff --git a/example/stm32f4/STM32_USB_OTG_Driver/src/usb_otg.c b/example/stm32f4/STM32_USB_OTG_Driver/src/usb_otg.c deleted file mode 100644 index fbb71ecb4..000000000 --- a/example/stm32f4/STM32_USB_OTG_Driver/src/usb_otg.c +++ /dev/null @@ -1,175 +0,0 @@ -/** - ****************************************************************************** - * @file usb_otg.c - * @author MCD Application Team - * @version V2.0.0 - * @date 22-July-2011 - * @brief OTG Core Layer - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "usb_defines.h" -#include "usb_regs.h" -#include "usb_core.h" -#include "usb_otg.h" - -/** @addtogroup USB_OTG_DRIVER - * @{ - */ - -/** @defgroup USB_OTG - * @brief This file is the interface between EFSL ans Host mass-storage class - * @{ - */ - - -/** @defgroup USB_OTG_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_OTG_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - - -/** @defgroup USB_OTG_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_OTG_Private_Variables - * @{ - */ -/** - * @} - */ - - -/** @defgroup USB_OTG_Private_FunctionPrototypes - * @{ - */ - -static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev); - -/** - * @} - */ - - -/** @defgroup USB_OTG_Private_Functions - * @{ - */ - - -/* OTG Interrupt Handler */ - - -/** - * @brief STM32_USBO_OTG_ISR_Handler - * - * @param None - * @retval : None - */ -uint32_t STM32_USBO_OTG_ISR_Handler(USB_OTG_CORE_HANDLE *pdev) -{ - uint32_t retval = 0; - USB_OTG_GINTSTS_TypeDef gintsts ; - gintsts.d32 = 0; - - gintsts.d32 = USB_OTG_Read_itr(pdev); - if (gintsts.d32 == 0) - { - return 0; - } - if (gintsts.b.otgintr) - { - retval |= 1;//USB_OTG_HandleOTG_ISR(pdev); - } - if (gintsts.b.conidstschng) - { - retval |= 2;//USB_OTG_HandleConnectorIDStatusChange_ISR(pdev); - } - if (gintsts.b.sessreqintr) - { - retval |= 3;//USB_OTG_HandleSessionRequest_ISR(pdev); - } - return retval; -} - - -/** - * @brief USB_OTG_Read_itr - * returns the Core Interrupt register - * @param None - * @retval : status - */ -static uint32_t USB_OTG_Read_itr(USB_OTG_CORE_HANDLE *pdev) -{ - USB_OTG_GINTSTS_TypeDef gintsts; - USB_OTG_GINTMSK_TypeDef gintmsk; - USB_OTG_GINTMSK_TypeDef gintmsk_common; - - - gintsts.d32 = 0; - gintmsk.d32 = 0; - gintmsk_common.d32 = 0; - - /* OTG interrupts */ - gintmsk_common.b.sessreqintr = 1; - gintmsk_common.b.conidstschng = 1; - gintmsk_common.b.otgintr = 1; - - gintsts.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTSTS); - gintmsk.d32 = USB_OTG_READ_REG32(&pdev->regs.GREGS->GINTMSK); - return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32); -} - - -/** - * @brief USB_OTG_GetCurrentState - * Return current OTG State - * @param None - * @retval : None - */ -uint32_t USB_OTG_GetCurrentState (USB_OTG_CORE_HANDLE *pdev) -{ - return pdev->otg.OTG_State; -} - - -/** -* @} -*/ - -/** -* @} -*/ - -/** -* @} -*/ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Utilities/STM32F4-Discovery/Release_Notes.html b/example/stm32f4/Utilities/STM32F4-Discovery/Release_Notes.html deleted file mode 100644 index 7b270b4f1..000000000 --- a/example/stm32f4/Utilities/STM32F4-Discovery/Release_Notes.html +++ /dev/null @@ -1,151 +0,0 @@ - - - - - - - - - - - - - - - - Release Notes for STM32F4-Discovery Board Drivers - - - - - - - - - - -
-


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Release -Notes for STM32F4-Discovery Board Drivers

-

Copyright -2011 STMicroelectronics

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Contents

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  1. STM32F4-Discovery Board Drivers update History
    2. -
  2. License
    3. -
- - -

STM32F4-Discovery Board Drivers update History

For more information on the STM32F4-Discovery board visit www.st.com/stm32f4-discovery.

V1.0.0 / 19-September-2011

-

Main -Changes

- -
  • First official version of the STM32F4-Discovery Board Drivers

License

-

The -enclosed firmware and all the related documentation are not covered by -a License Agreement, if you need such License you can contact your -local STMicroelectronics office.

- - THE -PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO -SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR -ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY -CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY -CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH -THEIR PRODUCTS. - -
-
-

For -complete documentation on STMicroelectronics Microcontrollers visit www.st.com

-
-

-
-
-

 

-
- - \ No newline at end of file diff --git a/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery.c b/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery.c deleted file mode 100644 index ff0d69718..000000000 --- a/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery.c +++ /dev/null @@ -1,257 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4_discovery.c - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief This file provides set of firmware functions to manage Leds and - * push-button available on STM32F4-Discovery Kit from STMicroelectronics. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4_discovery.h" - -//ADDED BY ME!!!!!!!!!!!!!!!!!!!! -#include "stm32f4xx_conf.h" - - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY - * @{ - */ - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL - * @brief This file provides set of firmware functions to manage Leds and push-button - * available on STM32F4-Discovery Kit from STMicroelectronics. - * @{ - */ - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_TypesDefinitions - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Defines - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Variables - * @{ - */ -GPIO_TypeDef* GPIO_PORT[LEDn] = {LED4_GPIO_PORT, LED3_GPIO_PORT, LED5_GPIO_PORT, - LED6_GPIO_PORT}; -const uint16_t GPIO_PIN[LEDn] = {LED4_PIN, LED3_PIN, LED5_PIN, - LED6_PIN}; -const uint32_t GPIO_CLK[LEDn] = {LED4_GPIO_CLK, LED3_GPIO_CLK, LED5_GPIO_CLK, - LED6_GPIO_CLK}; - -GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {USER_BUTTON_GPIO_PORT }; - -const uint16_t BUTTON_PIN[BUTTONn] = {USER_BUTTON_PIN }; - -const uint32_t BUTTON_CLK[BUTTONn] = {USER_BUTTON_GPIO_CLK }; - -const uint16_t BUTTON_EXTI_LINE[BUTTONn] = {USER_BUTTON_EXTI_LINE }; - -const uint8_t BUTTON_PORT_SOURCE[BUTTONn] = {USER_BUTTON_EXTI_PORT_SOURCE}; - -const uint8_t BUTTON_PIN_SOURCE[BUTTONn] = {USER_BUTTON_EXTI_PIN_SOURCE }; -const uint8_t BUTTON_IRQn[BUTTONn] = {USER_BUTTON_EXTI_IRQn }; - -NVIC_InitTypeDef NVIC_InitStructure; - -/** - * @} - */ - - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Private_Functions - * @{ - */ - -/** - * @brief Configures LED GPIO. - * @param Led: Specifies the Led to be configured. - * This parameter can be one of following parameters: - * @arg LED4 - * @arg LED3 - * @arg LED5 - * @arg LED6 - * @retval None - */ -void STM_EVAL_LEDInit(Led_TypeDef Led) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable the GPIO_LED Clock */ - RCC_AHB1PeriphClockCmd(GPIO_CLK[Led], ENABLE); - - /* Configure the GPIO_LED pin */ - GPIO_InitStructure.GPIO_Pin = GPIO_PIN[Led]; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIO_PORT[Led], &GPIO_InitStructure); -} - -/** - * @brief Turns selected LED On. - * @param Led: Specifies the Led to be set on. - * This parameter can be one of following parameters: - * @arg LED4 - * @arg LED3 - * @arg LED5 - * @arg LED6 - * @retval None - */ -void STM_EVAL_LEDOn(Led_TypeDef Led) -{ - GPIO_PORT[Led]->BSRRL = GPIO_PIN[Led]; -} - -/** - * @brief Turns selected LED Off. - * @param Led: Specifies the Led to be set off. - * This parameter can be one of following parameters: - * @arg LED4 - * @arg LED3 - * @arg LED5 - * @arg LED6 - * @retval None - */ -void STM_EVAL_LEDOff(Led_TypeDef Led) -{ - GPIO_PORT[Led]->BSRRH = GPIO_PIN[Led]; -} - -/** - * @brief Toggles the selected LED. - * @param Led: Specifies the Led to be toggled. - * This parameter can be one of following parameters: - * @arg LED4 - * @arg LED3 - * @arg LED5 - * @arg LED6 - * @retval None - */ -void STM_EVAL_LEDToggle(Led_TypeDef Led) -{ - GPIO_PORT[Led]->ODR ^= GPIO_PIN[Led]; -} - -/** - * @brief Configures Button GPIO and EXTI Line. - * @param Button: Specifies the Button to be configured. - * This parameter should be: BUTTON_USER - * @param Button_Mode: Specifies Button mode. - * This parameter can be one of following parameters: - * @arg BUTTON_MODE_GPIO: Button will be used as simple IO - * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt - * generation capability - * @retval None - */ -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode) -{ - GPIO_InitTypeDef GPIO_InitStructure; - EXTI_InitTypeDef EXTI_InitStructure; - NVIC_InitTypeDef NVIC_InitStructure; - - /* Enable the BUTTON Clock */ - RCC_AHB1PeriphClockCmd(BUTTON_CLK[Button], ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - - /* Configure Button pin as input */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Pin = BUTTON_PIN[Button]; - GPIO_Init(BUTTON_PORT[Button], &GPIO_InitStructure); - - if (Button_Mode == BUTTON_MODE_EXTI) - { - /* Connect Button EXTI Line to Button GPIO Pin */ - SYSCFG_EXTILineConfig(BUTTON_PORT_SOURCE[Button], BUTTON_PIN_SOURCE[Button]); - - /* Configure Button EXTI line */ - EXTI_InitStructure.EXTI_Line = BUTTON_EXTI_LINE[Button]; - EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising; - EXTI_InitStructure.EXTI_LineCmd = ENABLE; - EXTI_Init(&EXTI_InitStructure); - - /* Enable and set Button EXTI Interrupt to the lowest priority */ - NVIC_InitStructure.NVIC_IRQChannel = BUTTON_IRQn[Button]; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0F; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - - NVIC_Init(&NVIC_InitStructure); - } -} - -/** - * @brief Returns the selected Button state. - * @param Button: Specifies the Button to be checked. - * This parameter should be: BUTTON_USER - * @retval The Button GPIO pin value. - */ -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button) -{ - return GPIO_ReadInputDataBit(BUTTON_PORT[Button], BUTTON_PIN[Button]); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery.h b/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery.h deleted file mode 100644 index c6fec4221..000000000 --- a/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery.h +++ /dev/null @@ -1,158 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4_discovery.h - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief This file contains definitions for STM32F4-Discovery Kit's Leds and - * push-button hardware resources. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4_DISCOVERY_H -#define __STM32F4_DISCOVERY_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ - #include "stm32f4xx.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL - * @{ - */ - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Types - * @{ - */ -typedef enum -{ - LED4 = 0, - LED3 = 1, - LED5 = 2, - LED6 = 3 -} Led_TypeDef; - -typedef enum -{ - BUTTON_USER = 0, -} Button_TypeDef; - -typedef enum -{ - BUTTON_MODE_GPIO = 0, - BUTTON_MODE_EXTI = 1 -} ButtonMode_TypeDef; -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Constants - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_LED - * @{ - */ -#define LEDn 4 - -#define LED4_PIN GPIO_Pin_12 -#define LED4_GPIO_PORT GPIOD -#define LED4_GPIO_CLK RCC_AHB1Periph_GPIOD - -#define LED3_PIN GPIO_Pin_13 -#define LED3_GPIO_PORT GPIOD -#define LED3_GPIO_CLK RCC_AHB1Periph_GPIOD - -#define LED5_PIN GPIO_Pin_14 -#define LED5_GPIO_PORT GPIOD -#define LED5_GPIO_CLK RCC_AHB1Periph_GPIOD - -#define LED6_PIN GPIO_Pin_15 -#define LED6_GPIO_PORT GPIOD -#define LED6_GPIO_CLK RCC_AHB1Periph_GPIOD -/** - * @} - */ - -/** @addtogroup STM32F4_DISCOVERY_LOW_LEVEL_BUTTON - * @{ - */ -#define BUTTONn 1 - -/** - * @brief Wakeup push-button - */ -#define USER_BUTTON_PIN GPIO_Pin_0 -#define USER_BUTTON_GPIO_PORT GPIOA -#define USER_BUTTON_GPIO_CLK RCC_AHB1Periph_GPIOA -#define USER_BUTTON_EXTI_LINE EXTI_Line0 -#define USER_BUTTON_EXTI_PORT_SOURCE EXTI_PortSourceGPIOA -#define USER_BUTTON_EXTI_PIN_SOURCE EXTI_PinSource0 -#define USER_BUTTON_EXTI_IRQn EXTI0_IRQn -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Macros - * @{ - */ -/** - * @} - */ - - -/** @defgroup STM32F4_DISCOVERY_LOW_LEVEL_Exported_Functions - * @{ - */ -void STM_EVAL_LEDInit(Led_TypeDef Led); -void STM_EVAL_LEDOn(Led_TypeDef Led); -void STM_EVAL_LEDOff(Led_TypeDef Led); -void STM_EVAL_LEDToggle(Led_TypeDef Led); -void STM_EVAL_PBInit(Button_TypeDef Button, ButtonMode_TypeDef Button_Mode); -uint32_t STM_EVAL_PBGetState(Button_TypeDef Button); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4_DISCOVERY_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery_audio_codec.c b/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery_audio_codec.c deleted file mode 100644 index 0445aa571..000000000 --- a/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery_audio_codec.c +++ /dev/null @@ -1,1651 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4_discovery_audio_codec.c - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief This file includes the low layer driver for CS43L22 Audio Codec - * available on STM32F4-Discovery Kit. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/*============================================================================================================================== - User NOTES -1. How To use this driver: --------------------------- - - This driver supports STM32F4xx devices on STM32F4-Discovery Kit. - - - Configure the options in file stm32f4_discovery_audio_codec.h in the section CONFIGURATION. - Refer to the sections 2 and 3 to have more details on the possible configurations. - - - Call the function EVAL_AUDIO_Init( - OutputDevice: physical output mode (OUTPUT_DEVICE_SPEAKER, - OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_AUTO or - OUTPUT_DEVICE_BOTH) - Volume: initial volume to be set (0 is min (mute), 100 is max (100%) - AudioFreq: Audio frequency in Hz (8000, 16000, 22500, 32000 ...) - this parameter is relative to the audio file/stream type. - ) - This function configures all the hardware required for the audio application (codec, I2C, I2S, - GPIOs, DMA and interrupt if needed). This function returns 0 if configuration is OK. - if the returned value is different from 0 or the function is stuck then the communication with - the codec (try to un-plug the power or reset device in this case). - + OUTPUT_DEVICE_SPEAKER: only speaker will be set as output for the audio stream. - + OUTPUT_DEVICE_HEADPHONE: only headphones will be set as output for the audio stream. - + OUTPUT_DEVICE_AUTO: Selection of output device is made through external switch (implemented - into the audio jack on the evaluation board). When the Headphone is connected it is used - as output. When the headphone is disconnected from the audio jack, the output is - automatically switched to Speaker. - + OUTPUT_DEVICE_BOTH: both Speaker and Headphone are used as outputs for the audio stream - at the same time. - - - Call the function EVAL_AUDIO_Play( - pBuffer: pointer to the audio data file address - Size: size of the buffer to be sent in Bytes - ) - to start playing (for the first time) from the audio file/stream. - - - Call the function EVAL_AUDIO_PauseResume( - Cmd: AUDIO_PAUSE (or 0) to pause playing or AUDIO_RESUME (or - any value different from 0) to resume playing. - ) - Note. After calling EVAL_AUDIO_PauseResume() function for pause, only EVAL_AUDIO_PauseResume() should be called - for resume (it is not allowed to call EVAL_AUDIO_Play() in this case). - Note. This function should be called only when the audio file is played or paused (not stopped). - - - For each mode, you may need to implement the relative callback functions into your code. - The Callback functions are named EVAL_AUDIO_XXX_CallBack() and only their prototypes are declared in - the stm32f4_discovery_audio_codec.h file. (refer to the example for more details on the callbacks implementations) - - - To Stop playing, to modify the volume level or to mute, use the functions - EVAL_AUDIO_Stop(), EVAL_AUDIO_VolumeCtl() and EVAL_AUDIO_Mute(). - - - The driver API and the callback functions are at the end of the stm32f4_discovery_audio_codec.h file. - - - Driver architecture: - -------------------- - This driver is composed of three main layers: - o High Audio Layer: consists of the function API exported in the stm32f4_discovery_audio_codec.h file - (EVAL_AUDIO_Init(), EVAL_AUDIO_Play() ...) - o Codec Control layer: consists of the functions API controlling the audio codec (CS43L22) and - included as local functions in file stm32f4_discovery_audio_codec.c (Codec_Init(), Codec_Play() ...) - o Media Access Layer (MAL): which consists of functions allowing to access the media containing/ - providing the audio file/stream. These functions are also included as local functions into - the stm32f4_discovery_audio_codec.c file (Audio_MAL_Init(), Audio_MAL_Play() ...) - Each set of functions (layer) may be implemented independently of the others and customized when - needed. - -2. Modes description: ---------------------- - + AUDIO_MAL_MODE_NORMAL : is suitable when the audio file is in a memory location. - + AUDIO_MAL_MODE_CIRCULAR: is suitable when the audio data are read either from a - memory location or from a device at real time (double buffer could be used). - -3. DMA interrupts description: ------------------------------- - + EVAL_AUDIO_IT_TC_ENABLE: Enable this define to use the DMA end of transfer interrupt. - then, a callback should be implemented by user to perform specific actions - when the DMA has finished the transfer. - + EVAL_AUDIO_IT_HT_ENABLE: Enable this define to use the DMA end of half transfer interrupt. - then, a callback should be implemented by user to perform specific actions - when the DMA has reached the half of the buffer transfer (generally, it is useful - to load the first half of buffer while DMA is loading from the second half). - + EVAL_AUDIO_IT_ER_ENABLE: Enable this define to manage the cases of error on DMA transfer. - -4. Known Limitations: ---------------------- - 1- When using the Speaker, if the audio file quality is not high enough, the speaker output - may produce high and uncomfortable noise level. To avoid this issue, to use speaker - output properly, try to increase audio file sampling rate (typically higher than 48KHz). - This operation will lead to larger file size. - 2- Communication with the audio codec (through I2C) may be corrupted if it is interrupted by some - user interrupt routines (in this case, interrupts could be disabled just before the start of - communication then re-enabled when it is over). Note that this communication is only done at - the configuration phase (EVAL_AUDIO_Init() or EVAL_AUDIO_Stop()) and when Volume control modification is - performed (EVAL_AUDIO_VolumeCtl() or EVAL_AUDIO_Mute()). When the audio data is played, no communication is - required with the audio codec. - 3- Parsing of audio file is not implemented (in order to determine audio file properties: Mono/Stereo, Data size, - File size, Audio Frequency, Audio Data header size ...). The configuration is fixed for the given audio file. - 4- Mono audio streaming is not supported (in order to play mono audio streams, each data should be sent twice - on the I2S or should be duplicated on the source buffer. Or convert the stream in stereo before playing). - 5- Supports only 16-bit audio data size. -===============================================================================================================================*/ - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4_discovery_audio_codec.h" -//ADDED BY ME!!!!!!!!!!!!!!!!!!!! -#include "stm32f4xx_conf.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY_AUDIO_CODEC - * @brief This file includes the low layer driver for CS43L22 Audio Codec - * available on STM32F4-Discovery Kit. - * @{ - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Private_Types - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Private_Defines - * @{ - */ - -/* Mask for the bit EN of the I2S CFGR register */ -#define I2S_ENABLE_MASK 0x0400 - -/* Delay for the Codec to be correctly reset */ -#define CODEC_RESET_DELAY 0x4FFF - -/* Codec audio Standards */ -#ifdef I2S_STANDARD_PHILLIPS - #define CODEC_STANDARD 0x04 - #define I2S_STANDARD I2S_Standard_Phillips -#elif defined(I2S_STANDARD_MSB) - #define CODEC_STANDARD 0x00 - #define I2S_STANDARD I2S_Standard_MSB -#elif defined(I2S_STANDARD_LSB) - #define CODEC_STANDARD 0x08 - #define I2S_STANDARD I2S_Standard_LSB -#else - #error "Error: No audio communication standard selected !" -#endif /* I2S_STANDARD */ - -/* The 7 bits Codec address (sent through I2C interface) */ -#define CODEC_ADDRESS 0x94 /* b00100111 */ -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Private_Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Private_Variables - * @{ - */ -/* This structure is declared global because it is handled by two different functions */ -static DMA_InitTypeDef DMA_InitStructure; -DMA_InitTypeDef AUDIO_MAL_DMA_InitStructure; - -uint32_t AudioTotalSize = 0xFFFF; /* This variable holds the total size of the audio file */ -uint32_t AudioRemSize = 0xFFFF; /* This variable holds the remaining data in audio file */ -uint16_t *CurrentPos; /* This variable holds the current position of audio pointer */ - -__IO uint32_t CODECTimeout = CODEC_LONG_TIMEOUT; -__IO uint8_t OutputDev = 0; - - -__IO uint32_t CurrAudioInterface = AUDIO_INTERFACE_I2S; //AUDIO_INTERFACE_DAC -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Private_Function_Prototypes - * @{ - */ -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Private_Functions - * @{ - */ -static void Audio_MAL_IRQHandler(void); -/*----------------------------------- - Audio Codec functions - ------------------------------------------*/ -/* High Layer codec functions */ -static uint32_t Codec_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq); -static uint32_t Codec_DeInit(void); -static uint32_t Codec_Play(void); -static uint32_t Codec_PauseResume(uint32_t Cmd); -static uint32_t Codec_Stop(uint32_t Cmd); -static uint32_t Codec_VolumeCtrl(uint8_t Volume); -static uint32_t Codec_Mute(uint32_t Cmd); -/* Low layer codec functions */ -static void Codec_CtrlInterface_Init(void); -static void Codec_CtrlInterface_DeInit(void); -static void Codec_AudioInterface_Init(uint32_t AudioFreq); -static void Codec_AudioInterface_DeInit(void); -static void Codec_Reset(void); -static uint32_t Codec_WriteRegister(uint8_t RegisterAddr, uint8_t RegisterValue); -static uint32_t Codec_ReadRegister(uint8_t RegisterAddr); -static void Codec_GPIO_Init(void); -static void Codec_GPIO_DeInit(void); -static void Delay(__IO uint32_t nCount); -/*----------------------------------------------------------------------------*/ - -/*----------------------------------- - MAL (Media Access Layer) functions - ------------------------------------------*/ -/* Peripherals configuration functions */ -static void Audio_MAL_Init(void); -static void Audio_MAL_DeInit(void); -static void Audio_MAL_Play(uint32_t Addr, uint32_t Size); -static void Audio_MAL_PauseResume(uint32_t Cmd, uint32_t Addr); -static void Audio_MAL_Stop(void); -/*----------------------------------------------------------------------------*/ - - /* DMA Stream definitions */ - uint32_t AUDIO_MAL_DMA_CLOCK = AUDIO_I2S_DMA_CLOCK; - DMA_Stream_TypeDef * AUDIO_MAL_DMA_STREAM = AUDIO_I2S_DMA_STREAM ; - uint32_t AUDIO_MAL_DMA_DREG = AUDIO_I2S_DMA_DREG; - uint32_t AUDIO_MAL_DMA_CHANNEL = AUDIO_I2S_DMA_CHANNEL; - uint32_t AUDIO_MAL_DMA_IRQ = AUDIO_I2S_DMA_IRQ ; - uint32_t AUDIO_MAL_DMA_FLAG_TC = AUDIO_I2S_DMA_FLAG_TC; - uint32_t AUDIO_MAL_DMA_FLAG_HT = AUDIO_I2S_DMA_FLAG_HT; - uint32_t AUDIO_MAL_DMA_FLAG_FE = AUDIO_I2S_DMA_FLAG_FE; - uint32_t AUDIO_MAL_DMA_FLAG_TE = AUDIO_I2S_DMA_FLAG_TE; - uint32_t AUDIO_MAL_DMA_FLAG_DME = AUDIO_I2S_DMA_FLAG_DME; - -/** - * @brief Set the current audio interface (I2S or DAC). - * @param Interface: AUDIO_INTERFACE_I2S or AUDIO_INTERFACE_DAC - * @retval None - */ -void EVAL_AUDIO_SetAudioInterface(uint32_t Interface) -{ - CurrAudioInterface = Interface; - - if (CurrAudioInterface == AUDIO_INTERFACE_I2S) - { - /* DMA Stream definitions */ - AUDIO_MAL_DMA_CLOCK = AUDIO_I2S_DMA_CLOCK; - AUDIO_MAL_DMA_STREAM = AUDIO_I2S_DMA_STREAM; - AUDIO_MAL_DMA_DREG = AUDIO_I2S_DMA_DREG; - AUDIO_MAL_DMA_CHANNEL = AUDIO_I2S_DMA_CHANNEL; - AUDIO_MAL_DMA_IRQ = AUDIO_I2S_DMA_IRQ ; - AUDIO_MAL_DMA_FLAG_TC = AUDIO_I2S_DMA_FLAG_TC; - AUDIO_MAL_DMA_FLAG_HT = AUDIO_I2S_DMA_FLAG_HT; - AUDIO_MAL_DMA_FLAG_FE = AUDIO_I2S_DMA_FLAG_FE; - AUDIO_MAL_DMA_FLAG_TE = AUDIO_I2S_DMA_FLAG_TE; - AUDIO_MAL_DMA_FLAG_DME = AUDIO_I2S_DMA_FLAG_DME; - } - else if (Interface == AUDIO_INTERFACE_DAC) - { - /* DMA Stream definitions */ - AUDIO_MAL_DMA_CLOCK = AUDIO_DAC_DMA_CLOCK; - AUDIO_MAL_DMA_STREAM = AUDIO_DAC_DMA_STREAM; - AUDIO_MAL_DMA_DREG = AUDIO_DAC_DMA_DREG; - AUDIO_MAL_DMA_CHANNEL = AUDIO_DAC_DMA_CHANNEL; - AUDIO_MAL_DMA_IRQ = AUDIO_DAC_DMA_IRQ ; - AUDIO_MAL_DMA_FLAG_TC = AUDIO_DAC_DMA_FLAG_TC; - AUDIO_MAL_DMA_FLAG_HT = AUDIO_DAC_DMA_FLAG_HT; - AUDIO_MAL_DMA_FLAG_FE = AUDIO_DAC_DMA_FLAG_FE; - AUDIO_MAL_DMA_FLAG_TE = AUDIO_DAC_DMA_FLAG_TE; - AUDIO_MAL_DMA_FLAG_DME = AUDIO_DAC_DMA_FLAG_DME; - } -} - -/** - * @brief Configure the audio peripherals. - * @param OutputDevice: OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE, - * OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO . - * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max)) - * @param AudioFreq: Audio frequency used to play the audio stream. - * @retval 0 if correct communication, else wrong communication - */ -uint32_t EVAL_AUDIO_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq) -{ - /* Perform low layer Codec initialization */ - if (Codec_Init(OutputDevice, VOLUME_CONVERT(Volume), AudioFreq) != 0) - { - return 1; - } - else - { - /* I2S data transfer preparation: - Prepare the Media to be used for the audio transfer from memory to I2S peripheral */ - Audio_MAL_Init(); - - /* Return 0 when all operations are OK */ - return 0; - } -} - -/** - * @brief Deinitializes all the resources used by the codec (those initialized - * by EVAL_AUDIO_Init() function). - * @param None - * @retval 0 if correct communication, else wrong communication - */ -uint32_t EVAL_AUDIO_DeInit(void) -{ - /* DeInitialize the Media layer */ - Audio_MAL_DeInit(); - - /* DeInitialize Codec */ - Codec_DeInit(); - - return 0; -} - -/** - * @brief Starts playing audio stream from a data buffer for a determined size. - * @param pBuffer: Pointer to the buffer - * @param Size: Number of audio data BYTES. - * @retval 0 if correct communication, else wrong communication - */ -uint32_t EVAL_AUDIO_Play(uint16_t* pBuffer, uint32_t Size) -{ - /* Set the total number of data to be played (count in half-word) */ - AudioTotalSize = Size/2; - - /* Call the audio Codec Play function */ - Codec_Play(); - - /* Update the Media layer and enable it for play */ - Audio_MAL_Play((uint32_t)pBuffer, (uint32_t)(DMA_MAX(AudioTotalSize / 2))); - - /* Update the remaining number of data to be played */ - AudioRemSize = (Size/2) - DMA_MAX(AudioTotalSize); - - /* Update the current audio pointer position */ - CurrentPos = pBuffer + DMA_MAX(AudioTotalSize); - - return 0; -} - -/** - * @brief This function Pauses or Resumes the audio file stream. In case - * of using DMA, the DMA Pause feature is used. In all cases the I2S - * peripheral is disabled. - * - * @WARNING When calling EVAL_AUDIO_PauseResume() function for pause, only - * this function should be called for resume (use of EVAL_AUDIO_Play() - * function for resume could lead to unexpected behavior). - * - * @param Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different - * from 0) to resume. - * @retval 0 if correct communication, else wrong communication - */ -uint32_t EVAL_AUDIO_PauseResume(uint32_t Cmd) -{ - /* Call the Audio Codec Pause/Resume function */ - if (Codec_PauseResume(Cmd) != 0) - { - return 1; - } - else - { - /* Call the Media layer pause/resume function */ - Audio_MAL_PauseResume(Cmd, 0); - - /* Return 0 if all operations are OK */ - return 0; - } -} - -/** - * @brief Stops audio playing and Power down the Audio Codec. - * @param Option: could be one of the following parameters - * - CODEC_PDWN_SW: for software power off (by writing registers). - * Then no need to reconfigure the Codec after power on. - * - CODEC_PDWN_HW: completely shut down the codec (physically). - * Then need to reconfigure the Codec after power on. - * @retval 0 if correct communication, else wrong communication - */ -uint32_t EVAL_AUDIO_Stop(uint32_t Option) -{ - /* Call Audio Codec Stop function */ - if (Codec_Stop(Option) != 0) - { - return 1; - } - else - { - /* Call Media layer Stop function */ - Audio_MAL_Stop(); - - /* Update the remaining data number */ - AudioRemSize = AudioTotalSize; - - /* Return 0 when all operations are correctly done */ - return 0; - } -} - -/** - * @brief Controls the current audio volume level. - * @param Volume: Volume level to be set in percentage from 0% to 100% (0 for - * Mute and 100 for Max volume level). - * @retval 0 if correct communication, else wrong communication - */ -uint32_t EVAL_AUDIO_VolumeCtl(uint8_t Volume) -{ - /* Call the codec volume control function with converted volume value */ - return (Codec_VolumeCtrl(VOLUME_CONVERT(Volume))); -} - -/** - * @brief Enables or disables the MUTE mode by software - * @param Command: could be AUDIO_MUTE_ON to mute sound or AUDIO_MUTE_OFF to - * unmute the codec and restore previous volume level. - * @retval 0 if correct communication, else wrong communication - */ -uint32_t EVAL_AUDIO_Mute(uint32_t Cmd) -{ - /* Call the Codec Mute function */ - return (Codec_Mute(Cmd)); -} - -/** - * @brief This function handles main Media layer interrupt. - * @param None - * @retval 0 if correct communication, else wrong communication - */ -static void Audio_MAL_IRQHandler(void) -{ -#ifndef AUDIO_MAL_MODE_NORMAL - uint16_t *pAddr = (uint16_t *)CurrentPos; - uint32_t Size = AudioRemSize; -#endif /* AUDIO_MAL_MODE_NORMAL */ - -#ifdef AUDIO_MAL_DMA_IT_TC_EN - /* Transfer complete interrupt */ - if (DMA_GetFlagStatus(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC) != RESET) - { - #ifdef AUDIO_MAL_MODE_NORMAL - /* Check if the end of file has been reached */ - if (AudioRemSize > 0) - { - /* Wait the DMA Stream to be effectively disabled */ - while (DMA_GetCmdStatus(AUDIO_MAL_DMA_STREAM) != DISABLE) - {} - - /* Clear the Interrupt flag */ - DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC); - - /* Re-Configure the buffer address and size */ - DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) CurrentPos; - DMA_InitStructure.DMA_BufferSize = (uint32_t) (DMA_MAX(AudioRemSize)); - - /* Configure the DMA Stream with the new parameters */ - DMA_Init(AUDIO_MAL_DMA_STREAM, &DMA_InitStructure); - - /* Enable the I2S DMA Stream*/ - DMA_Cmd(AUDIO_MAL_DMA_STREAM, ENABLE); - - /* Update the current pointer position */ - CurrentPos += DMA_MAX(AudioRemSize); - - /* Update the remaining number of data to be played */ - AudioRemSize -= DMA_MAX(AudioRemSize); - } - else - { - /* Disable the I2S DMA Stream*/ - DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE); - - /* Clear the Interrupt flag */ - DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC); - - /* Manage the remaining file size and new address offset: This function - should be coded by user (its prototype is already declared in stm32f4_discovery_audio_codec.h) */ - EVAL_AUDIO_TransferComplete_CallBack((uint32_t)CurrentPos, 0); - } - - #elif defined(AUDIO_MAL_MODE_CIRCULAR) - /* Manage the remaining file size and new address offset: This function - should be coded by user (its prototype is already declared in stm32f4_discovery_audio_codec.h) */ - EVAL_AUDIO_TransferComplete_CallBack(pAddr, Size); - - /* Clear the Interrupt flag */ - DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC); - #endif /* AUDIO_MAL_MODE_NORMAL */ - } -#endif /* AUDIO_MAL_DMA_IT_TC_EN */ - -#ifdef AUDIO_MAL_DMA_IT_HT_EN - /* Half Transfer complete interrupt */ - if (DMA_GetFlagStatus(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_HT) != RESET) - { - /* Manage the remaining file size and new address offset: This function - should be coded by user (its prototype is already declared in stm32f4_discovery_audio_codec.h) */ - EVAL_AUDIO_HalfTransfer_CallBack((uint32_t)pAddr, Size); - - /* Clear the Interrupt flag */ - DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_HT); - } -#endif /* AUDIO_MAL_DMA_IT_HT_EN */ - -#ifdef AUDIO_MAL_DMA_IT_TE_EN - /* FIFO Error interrupt */ - if ((DMA_GetFlagStatus(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TE) != RESET) || \ - (DMA_GetFlagStatus(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_FE) != RESET) || \ - (DMA_GetFlagStatus(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_DME) != RESET)) - - { - /* Manage the error generated on DMA FIFO: This function - should be coded by user (its prototype is already declared in stm32f4_discovery_audio_codec.h) */ - EVAL_AUDIO_Error_CallBack((uint32_t*)&pAddr); - - /* Clear the Interrupt flag */ - DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TE | AUDIO_MAL_DMA_FLAG_FE | \ - AUDIO_MAL_DMA_FLAG_DME); - } -#endif /* AUDIO_MAL_DMA_IT_TE_EN */ -} - -/** - * @brief This function handles main I2S interrupt. - * @param None - * @retval 0 if correct communication, else wrong communication - */ -void Audio_MAL_I2S_IRQHandler(void) -{ - Audio_MAL_IRQHandler(); -} - -/** - * @brief This function handles main DAC interrupt. - * @param None - * @retval 0 if correct communication, else wrong communication - */ -void Audio_MAL_DAC_IRQHandler(void) -{ - Audio_MAL_IRQHandler(); -} - -/** - * @brief I2S interrupt management - * @param None - * @retval None - */ -void Audio_I2S_IRQHandler(void) -{ - /* Check on the I2S TXE flag */ - if (SPI_I2S_GetFlagStatus(SPI3, SPI_I2S_FLAG_TXE) != RESET) - { - if (CurrAudioInterface == AUDIO_INTERFACE_DAC) - { - /* Wirte data to the DAC interface */ - DAC_SetChannel1Data(DAC_Align_12b_L, EVAL_AUDIO_GetSampleCallBack()); - } - - /* Send dummy data on I2S to avoid the underrun condition */ - SPI_I2S_SendData(CODEC_I2S, EVAL_AUDIO_GetSampleCallBack()); - } -} -/*======================== - - CS43L22 Audio Codec Control Functions - ==============================*/ -/** - * @brief Initializes the audio codec and all related interfaces (control - * interface: I2C and audio interface: I2S) - * @param OutputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE, - * OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO . - * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max)) - * @param AudioFreq: Audio frequency used to play the audio stream. - * @retval 0 if correct communication, else wrong communication - */ -static uint32_t Codec_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq) -{ - uint32_t counter = 0; - - /* Configure the Codec related IOs */ - Codec_GPIO_Init(); - - /* Reset the Codec Registers */ - Codec_Reset(); - - /* Initialize the Control interface of the Audio Codec */ - Codec_CtrlInterface_Init(); - - /* Keep Codec powered OFF */ - counter += Codec_WriteRegister(0x02, 0x01); - - counter += Codec_WriteRegister(0x04, 0xAF); /* SPK always OFF & HP always ON */ - OutputDev = 0xAF; - - /* Clock configuration: Auto detection */ - counter += Codec_WriteRegister(0x05, 0x81); - - /* Set the Slave Mode and the audio Standard */ - counter += Codec_WriteRegister(0x06, CODEC_STANDARD); - - /* Set the Master volume */ - Codec_VolumeCtrl(Volume); - - if (CurrAudioInterface == AUDIO_INTERFACE_DAC) - { - /* Enable the PassThrough on AIN1A and AIN1B */ - counter += Codec_WriteRegister(0x08, 0x01); - counter += Codec_WriteRegister(0x09, 0x01); - - /* Route the analog input to the HP line */ - counter += Codec_WriteRegister(0x0E, 0xC0); - - /* Set the Passthough volume */ - counter += Codec_WriteRegister(0x14, 0x00); - counter += Codec_WriteRegister(0x15, 0x00); - } - - /* Power on the Codec */ - counter += Codec_WriteRegister(0x02, 0x9E); - - /* Additional configuration for the CODEC. These configurations are done to reduce - the time needed for the Codec to power off. If these configurations are removed, - then a long delay should be added between powering off the Codec and switching - off the I2S peripheral MCLK clock (which is the operating clock for Codec). - If this delay is not inserted, then the codec will not shut down properly and - it results in high noise after shut down. */ - - /* Disable the analog soft ramp */ - counter += Codec_WriteRegister(0x0A, 0x00); - if (CurrAudioInterface != AUDIO_INTERFACE_DAC) - { - /* Disable the digital soft ramp */ - counter += Codec_WriteRegister(0x0E, 0x04); - } - /* Disable the limiter attack level */ - counter += Codec_WriteRegister(0x27, 0x00); - /* Adjust Bass and Treble levels */ - counter += Codec_WriteRegister(0x1F, 0x0F); - /* Adjust PCM volume level */ - counter += Codec_WriteRegister(0x1A, 0x0A); - counter += Codec_WriteRegister(0x1B, 0x0A); - - /* Configure the I2S peripheral */ - Codec_AudioInterface_Init(AudioFreq); - - /* Return communication control value */ - return counter; -} - -/** - * @brief Restore the audio codec state to default state and free all used - * resources. - * @param None - * @retval 0 if correct communication, else wrong communication - */ -static uint32_t Codec_DeInit(void) -{ - uint32_t counter = 0; - - /* Reset the Codec Registers */ - Codec_Reset(); - - /* Keep Codec powered OFF */ - counter += Codec_WriteRegister(0x02, 0x01); - - /* Deinitialize all use GPIOs */ - Codec_GPIO_DeInit(); - - /* Disable the Codec control interface */ - Codec_CtrlInterface_DeInit(); - - /* Deinitialize the Codec audio interface (I2S) */ - Codec_AudioInterface_DeInit(); - - /* Return communication control value */ - return counter; -} - -/** - * @brief Start the audio Codec play feature. - * @note For this codec no Play options are required. - * @param None - * @retval 0 if correct communication, else wrong communication - */ -static uint32_t Codec_Play(void) -{ - /* - No actions required on Codec level for play command - */ - - /* Return communication control value */ - return 0; -} - -/** - * @brief Pauses and resumes playing on the audio codec. - * @param Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different - * from 0) to resume. - * @retval 0 if correct communication, else wrong communication - */ -static uint32_t Codec_PauseResume(uint32_t Cmd) -{ - uint32_t counter = 0; - - /* Pause the audio file playing */ - if (Cmd == AUDIO_PAUSE) - { - /* Mute the output first */ - counter += Codec_Mute(AUDIO_MUTE_ON); - - /* Put the Codec in Power save mode */ - counter += Codec_WriteRegister(0x02, 0x01); - } - else /* AUDIO_RESUME */ - { - /* Unmute the output first */ - counter += Codec_Mute(AUDIO_MUTE_OFF); - - counter += Codec_WriteRegister(0x04, OutputDev); - - /* Exit the Power save mode */ - counter += Codec_WriteRegister(0x02, 0x9E); - } - - return counter; -} - -/** - * @brief Stops audio Codec playing. It powers down the codec. - * @param CodecPdwnMode: selects the power down mode. - * - CODEC_PDWN_SW: only mutes the audio codec. When resuming from this - * mode the codec keeps the previous initialization - * (no need to re-Initialize the codec registers). - * - CODEC_PDWN_HW: Physically power down the codec. When resuming from this - * mode, the codec is set to default configuration - * (user should re-Initialize the codec in order to - * play again the audio stream). - * @retval 0 if correct communication, else wrong communication - */ -static uint32_t Codec_Stop(uint32_t CodecPdwnMode) -{ - uint32_t counter = 0; - - /* Mute the output first */ - Codec_Mute(AUDIO_MUTE_ON); - - if (CodecPdwnMode == CODEC_PDWN_SW) - { - /* Power down the DAC and the speaker (PMDAC and PMSPK bits)*/ - counter += Codec_WriteRegister(0x02, 0x9F); - } - else /* CODEC_PDWN_HW */ - { - /* Power down the DAC components */ - counter += Codec_WriteRegister(0x02, 0x9F); - - /* Wait at least 100us */ - Delay(0xFFF); - - /* Reset The pin */ - GPIO_WriteBit(AUDIO_RESET_GPIO, AUDIO_RESET_PIN, Bit_RESET); - } - - return counter; -} - -/** - * @brief Sets higher or lower the codec volume level. - * @param Volume: a byte value from 0 to 255 (refer to codec registers - * description for more details). - * @retval 0 if correct communication, else wrong communication - */ -static uint32_t Codec_VolumeCtrl(uint8_t Volume) -{ - uint32_t counter = 0; - - if (Volume > 0xE6) - { - /* Set the Master volume */ - counter += Codec_WriteRegister(0x20, Volume - 0xE7); - counter += Codec_WriteRegister(0x21, Volume - 0xE7); - } - else - { - /* Set the Master volume */ - counter += Codec_WriteRegister(0x20, Volume + 0x19); - counter += Codec_WriteRegister(0x21, Volume + 0x19); - } - - return counter; -} - -/** - * @brief Enables or disables the mute feature on the audio codec. - * @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the - * mute mode. - * @retval 0 if correct communication, else wrong communication - */ -static uint32_t Codec_Mute(uint32_t Cmd) -{ - uint32_t counter = 0; - - /* Set the Mute mode */ - if (Cmd == AUDIO_MUTE_ON) - { - counter += Codec_WriteRegister(0x04, 0xFF); - } - else /* AUDIO_MUTE_OFF Disable the Mute */ - { - counter += Codec_WriteRegister(0x04, OutputDev); - } - - return counter; -} - -/** - * @brief Resets the audio codec. It restores the default configuration of the - * codec (this function shall be called before initializing the codec). - * @note This function calls an external driver function: The IO Expander driver. - * @param None - * @retval None - */ -static void Codec_Reset(void) -{ - /* Power Down the codec */ - GPIO_WriteBit(AUDIO_RESET_GPIO, AUDIO_RESET_PIN, Bit_RESET); - - /* wait for a delay to insure registers erasing */ - Delay(CODEC_RESET_DELAY); - - /* Power on the codec */ - GPIO_WriteBit(AUDIO_RESET_GPIO, AUDIO_RESET_PIN, Bit_SET); -} - -/** - * @brief Writes a Byte to a given register into the audio codec through the - control interface (I2C) - * @param RegisterAddr: The address (location) of the register to be written. - * @param RegisterValue: the Byte value to be written into destination register. - * @retval 0 if correct communication, else wrong communication - */ -static uint32_t Codec_WriteRegister(uint8_t RegisterAddr, uint8_t RegisterValue) -{ - uint32_t result = 0; - - /*!< While the bus is busy */ - CODECTimeout = CODEC_LONG_TIMEOUT; - while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BUSY)) - { - if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); - } - - /* Start the config sequence */ - I2C_GenerateSTART(CODEC_I2C, ENABLE); - - /* Test on EV5 and clear it */ - CODECTimeout = CODEC_FLAG_TIMEOUT; - while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_MODE_SELECT)) - { - if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); - } - - /* Transmit the slave address and enable writing operation */ - I2C_Send7bitAddress(CODEC_I2C, CODEC_ADDRESS, I2C_Direction_Transmitter); - - /* Test on EV6 and clear it */ - CODECTimeout = CODEC_FLAG_TIMEOUT; - while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); - } - - /* Transmit the first address for write operation */ - I2C_SendData(CODEC_I2C, RegisterAddr); - - /* Test on EV8 and clear it */ - CODECTimeout = CODEC_FLAG_TIMEOUT; - while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_BYTE_TRANSMITTING)) - { - if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); - } - - /* Prepare the register value to be sent */ - I2C_SendData(CODEC_I2C, RegisterValue); - - /*!< Wait till all data have been physically transferred on the bus */ - CODECTimeout = CODEC_LONG_TIMEOUT; - while(!I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BTF)) - { - if((CODECTimeout--) == 0) Codec_TIMEOUT_UserCallback(); - } - - /* End the configuration sequence */ - I2C_GenerateSTOP(CODEC_I2C, ENABLE); - -#ifdef VERIFY_WRITTENDATA - /* Verify that the data has been correctly written */ - result = (Codec_ReadRegister(RegisterAddr) == RegisterValue)? 0:1; -#endif /* VERIFY_WRITTENDATA */ - - /* Return the verifying value: 0 (Passed) or 1 (Failed) */ - return result; -} - -/** - * @brief Reads and returns the value of an audio codec register through the - * control interface (I2C). - * @param RegisterAddr: Address of the register to be read. - * @retval Value of the register to be read or dummy value if the communication - * fails. - */ -static uint32_t Codec_ReadRegister(uint8_t RegisterAddr) -{ - uint32_t result = 0; - - /*!< While the bus is busy */ - CODECTimeout = CODEC_LONG_TIMEOUT; - while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BUSY)) - { - if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); - } - - /* Start the config sequence */ - I2C_GenerateSTART(CODEC_I2C, ENABLE); - - /* Test on EV5 and clear it */ - CODECTimeout = CODEC_FLAG_TIMEOUT; - while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_MODE_SELECT)) - { - if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); - } - - /* Transmit the slave address and enable writing operation */ - I2C_Send7bitAddress(CODEC_I2C, CODEC_ADDRESS, I2C_Direction_Transmitter); - - /* Test on EV6 and clear it */ - CODECTimeout = CODEC_FLAG_TIMEOUT; - while (!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED)) - { - if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); - } - - /* Transmit the register address to be read */ - I2C_SendData(CODEC_I2C, RegisterAddr); - - /* Test on EV8 and clear it */ - CODECTimeout = CODEC_FLAG_TIMEOUT; - while (I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_BTF) == RESET) - { - if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); - } - - /*!< Send START condition a second time */ - I2C_GenerateSTART(CODEC_I2C, ENABLE); - - /*!< Test on EV5 and clear it (cleared by reading SR1 then writing to DR) */ - CODECTimeout = CODEC_FLAG_TIMEOUT; - while(!I2C_CheckEvent(CODEC_I2C, I2C_EVENT_MASTER_MODE_SELECT)) - { - if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); - } - - /*!< Send Codec address for read */ - I2C_Send7bitAddress(CODEC_I2C, CODEC_ADDRESS, I2C_Direction_Receiver); - - /* Wait on ADDR flag to be set (ADDR is still not cleared at this level */ - CODECTimeout = CODEC_FLAG_TIMEOUT; - while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_ADDR) == RESET) - { - if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); - } - - /*!< Disable Acknowledgment */ - I2C_AcknowledgeConfig(CODEC_I2C, DISABLE); - - /* Clear ADDR register by reading SR1 then SR2 register (SR1 has already been read) */ - (void)CODEC_I2C->SR2; - - /*!< Send STOP Condition */ - I2C_GenerateSTOP(CODEC_I2C, ENABLE); - - /* Wait for the byte to be received */ - CODECTimeout = CODEC_FLAG_TIMEOUT; - while(I2C_GetFlagStatus(CODEC_I2C, I2C_FLAG_RXNE) == RESET) - { - if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); - } - - /*!< Read the byte received from the Codec */ - result = I2C_ReceiveData(CODEC_I2C); - - /* Wait to make sure that STOP flag has been cleared */ - CODECTimeout = CODEC_FLAG_TIMEOUT; - while(CODEC_I2C->CR1 & I2C_CR1_STOP) - { - if((CODECTimeout--) == 0) return Codec_TIMEOUT_UserCallback(); - } - - /*!< Re-Enable Acknowledgment to be ready for another reception */ - I2C_AcknowledgeConfig(CODEC_I2C, ENABLE); - - /* Clear AF flag for next communication */ - I2C_ClearFlag(CODEC_I2C, I2C_FLAG_AF); - - /* Return the byte read from Codec */ - return result; -} - -/** - * @brief Initializes the Audio Codec control interface (I2C). - * @param None - * @retval None - */ -static void Codec_CtrlInterface_Init(void) -{ - I2C_InitTypeDef I2C_InitStructure; - - /* Enable the CODEC_I2C peripheral clock */ - RCC_APB1PeriphClockCmd(CODEC_I2C_CLK, ENABLE); - - /* CODEC_I2C peripheral configuration */ - I2C_DeInit(CODEC_I2C); - I2C_InitStructure.I2C_Mode = I2C_Mode_I2C; - I2C_InitStructure.I2C_DutyCycle = I2C_DutyCycle_2; - I2C_InitStructure.I2C_OwnAddress1 = 0x33; - I2C_InitStructure.I2C_Ack = I2C_Ack_Enable; - I2C_InitStructure.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; - I2C_InitStructure.I2C_ClockSpeed = I2C_SPEED; - /* Enable the I2C peripheral */ - I2C_Cmd(CODEC_I2C, ENABLE); - I2C_Init(CODEC_I2C, &I2C_InitStructure); -} - -/** - * @brief Restore the Audio Codec control interface to its default state. - * This function doesn't de-initialize the I2C because the I2C peripheral - * may be used by other modules. - * @param None - * @retval None - */ -static void Codec_CtrlInterface_DeInit(void) -{ - /* Disable the I2C peripheral */ /* This step is not done here because - the I2C interface can be used by other modules */ - /* I2C_DeInit(CODEC_I2C); */ -} - -/** - * @brief Initializes the Audio Codec audio interface (I2S) - * @note This function assumes that the I2S input clock (through PLL_R in - * Devices RevA/Z and through dedicated PLLI2S_R in Devices RevB/Y) - * is already configured and ready to be used. - * @param AudioFreq: Audio frequency to be configured for the I2S peripheral. - * @retval None - */ -static void Codec_AudioInterface_Init(uint32_t AudioFreq) -{ - I2S_InitTypeDef I2S_InitStructure; - DAC_InitTypeDef DAC_InitStructure; - - /* Enable the CODEC_I2S peripheral clock */ - RCC_APB1PeriphClockCmd(CODEC_I2S_CLK, ENABLE); - - /* CODEC_I2S peripheral configuration */ - SPI_I2S_DeInit(CODEC_I2S); - I2S_InitStructure.I2S_AudioFreq = AudioFreq; - I2S_InitStructure.I2S_Standard = I2S_STANDARD; - I2S_InitStructure.I2S_DataFormat = I2S_DataFormat_16b; - I2S_InitStructure.I2S_CPOL = I2S_CPOL_Low; -#ifdef DAC_USE_I2S_DMA - if (CurrAudioInterface == AUDIO_INTERFACE_DAC) - { - I2S_InitStructure.I2S_Mode = I2S_Mode_MasterRx; - } - else - { -#else - I2S_InitStructure.I2S_Mode = I2S_Mode_MasterTx; -#endif -#ifdef DAC_USE_I2S_DMA - } -#endif /* DAC_USE_I2S_DMA */ -#ifdef CODEC_MCLK_ENABLED - I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Enable; -#elif defined(CODEC_MCLK_DISABLED) - I2S_InitStructure.I2S_MCLKOutput = I2S_MCLKOutput_Disable; -#else -#error "No selection for the MCLK output has been defined !" -#endif /* CODEC_MCLK_ENABLED */ - - /* Initialize the I2S peripheral with the structure above */ - I2S_Init(CODEC_I2S, &I2S_InitStructure); - - - /* Configure the DAC interface */ - if (CurrAudioInterface == AUDIO_INTERFACE_DAC) - { - /* DAC Periph clock enable */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE); - - /* DAC channel1 Configuration */ - DAC_InitStructure.DAC_Trigger = DAC_Trigger_None; - DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None; - DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; - DAC_Init(AUDIO_DAC_CHANNEL, &DAC_InitStructure); - - /* Enable DAC Channel1 */ - DAC_Cmd(AUDIO_DAC_CHANNEL, ENABLE); - } - - /* The I2S peripheral will be enabled only in the EVAL_AUDIO_Play() function - or by user functions if DMA mode not enabled */ -} - -/** - * @brief Restores the Audio Codec audio interface to its default state. - * @param None - * @retval None - */ -static void Codec_AudioInterface_DeInit(void) -{ - /* Disable the CODEC_I2S peripheral (in case it hasn't already been disabled) */ - I2S_Cmd(CODEC_I2S, DISABLE); - - /* Deinitialize the CODEC_I2S peripheral */ - SPI_I2S_DeInit(CODEC_I2S); - - /* Disable the CODEC_I2S peripheral clock */ - RCC_APB1PeriphClockCmd(CODEC_I2S_CLK, DISABLE); -} - -/** - * @brief Initializes IOs used by the Audio Codec (on the control and audio - * interfaces). - * @param None - * @retval None - */ -static void Codec_GPIO_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable Reset GPIO Clock */ - RCC_AHB1PeriphClockCmd(AUDIO_RESET_GPIO_CLK,ENABLE); - - /* Audio reset pin configuration -------------------------------------------------*/ - GPIO_InitStructure.GPIO_Pin = AUDIO_RESET_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(AUDIO_RESET_GPIO, &GPIO_InitStructure); - - /* Enable I2S and I2C GPIO clocks */ - RCC_AHB1PeriphClockCmd(CODEC_I2C_GPIO_CLOCK | CODEC_I2S_GPIO_CLOCK, ENABLE); - - /* CODEC_I2C SCL and SDA pins configuration -------------------------------------*/ - GPIO_InitStructure.GPIO_Pin = CODEC_I2C_SCL_PIN | CODEC_I2C_SDA_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(CODEC_I2C_GPIO, &GPIO_InitStructure); - /* Connect pins to I2C peripheral */ - GPIO_PinAFConfig(CODEC_I2C_GPIO, CODEC_I2S_SCL_PINSRC, CODEC_I2C_GPIO_AF); - GPIO_PinAFConfig(CODEC_I2C_GPIO, CODEC_I2S_SDA_PINSRC, CODEC_I2C_GPIO_AF); - - /* CODEC_I2S pins configuration: WS, SCK and SD pins -----------------------------*/ - GPIO_InitStructure.GPIO_Pin = CODEC_I2S_SCK_PIN | CODEC_I2S_SD_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure); - - /* Connect pins to I2S peripheral */ - GPIO_PinAFConfig(CODEC_I2S_WS_GPIO, CODEC_I2S_WS_PINSRC, CODEC_I2S_GPIO_AF); - GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SCK_PINSRC, CODEC_I2S_GPIO_AF); - - if (CurrAudioInterface != AUDIO_INTERFACE_DAC) - { - GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN ; - GPIO_Init(CODEC_I2S_WS_GPIO, &GPIO_InitStructure); - GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SD_PINSRC, CODEC_I2S_GPIO_AF); - } - else - { - /* GPIOA clock enable (to be used with DAC) */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); - - /* DAC channel 1 & 2 (DAC_OUT1 = PA.4) configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOA, &GPIO_InitStructure); - } - -#ifdef CODEC_MCLK_ENABLED - /* CODEC_I2S pins configuration: MCK pin */ - GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MCK_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(CODEC_I2S_MCK_GPIO, &GPIO_InitStructure); - /* Connect pins to I2S peripheral */ - GPIO_PinAFConfig(CODEC_I2S_MCK_GPIO, CODEC_I2S_MCK_PINSRC, CODEC_I2S_GPIO_AF); -#endif /* CODEC_MCLK_ENABLED */ -} - -/** - * @brief Restores the IOs used by the Audio Codec interface to their default state. - * @param None - * @retval None - */ -static void Codec_GPIO_DeInit(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Deinitialize all the GPIOs used by the driver */ - GPIO_InitStructure.GPIO_Pin = CODEC_I2S_SCK_PIN | CODEC_I2S_SD_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(CODEC_I2S_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = CODEC_I2S_WS_PIN ; - GPIO_Init(CODEC_I2S_WS_GPIO, &GPIO_InitStructure); - - /* Disconnect pins from I2S peripheral */ - GPIO_PinAFConfig(CODEC_I2S_WS_GPIO, CODEC_I2S_WS_PINSRC, 0x00); - GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SCK_PINSRC, 0x00); - GPIO_PinAFConfig(CODEC_I2S_GPIO, CODEC_I2S_SD_PINSRC, 0x00); - -#ifdef CODEC_MCLK_ENABLED - /* CODEC_I2S pins deinitialization: MCK pin */ - GPIO_InitStructure.GPIO_Pin = CODEC_I2S_MCK_PIN; - GPIO_Init(CODEC_I2S_MCK_GPIO, &GPIO_InitStructure); - /* Disconnect pins from I2S peripheral */ - GPIO_PinAFConfig(CODEC_I2S_MCK_GPIO, CODEC_I2S_MCK_PINSRC, CODEC_I2S_GPIO_AF); -#endif /* CODEC_MCLK_ENABLED */ -} - -/** - * @brief Inserts a delay time (not accurate timing). - * @param nCount: specifies the delay time length. - * @retval None - */ -static void Delay( __IO uint32_t nCount) -{ - for (; nCount != 0; nCount--); -} - -#ifdef USE_DEFAULT_TIMEOUT_CALLBACK -/** - * @brief Basic management of the timeout situation. - * @param None - * @retval None - */ -uint32_t Codec_TIMEOUT_UserCallback(void) -{ - /* Block communication and all processes */ - while (1) - { - } -} -#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */ -/*======================== - - Audio MAL Interface Control Functions - - ==============================*/ - -/** - * @brief Initializes and prepares the Media to perform audio data transfer - * from Media to the I2S peripheral. - * @param None - * @retval None - */ -static void Audio_MAL_Init(void) -{ - -#ifdef I2S_INTERRUPT - NVIC_InitTypeDef NVIC_InitStructure; - - NVIC_InitStructure.NVIC_IRQChannel = SPI3_IRQn; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; - NVIC_InitStructure.NVIC_IRQChannelSubPriority =0; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); - - SPI_I2S_ITConfig(SPI3, SPI_I2S_IT_TXE, ENABLE); - - I2S_Cmd(SPI3, ENABLE); -#else -#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN) - NVIC_InitTypeDef NVIC_InitStructure; -#endif - - if (CurrAudioInterface == AUDIO_INTERFACE_I2S) - { - /* Enable the DMA clock */ - RCC_AHB1PeriphClockCmd(AUDIO_MAL_DMA_CLOCK, ENABLE); - - /* Configure the DMA Stream */ - DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE); - DMA_DeInit(AUDIO_MAL_DMA_STREAM); - /* Set the parameters to be configured */ - DMA_InitStructure.DMA_Channel = AUDIO_MAL_DMA_CHANNEL; - DMA_InitStructure.DMA_PeripheralBaseAddr = AUDIO_MAL_DMA_DREG; - DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0; /* This field will be configured in play function */ - DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; - DMA_InitStructure.DMA_BufferSize = (uint32_t)0xFFFE; /* This field will be configured in play function */ - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_InitStructure.DMA_PeripheralDataSize = AUDIO_MAL_DMA_PERIPH_DATA_SIZE; - DMA_InitStructure.DMA_MemoryDataSize = AUDIO_MAL_DMA_MEM_DATA_SIZE; -#ifdef AUDIO_MAL_MODE_NORMAL - DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; -#elif defined(AUDIO_MAL_MODE_CIRCULAR) - DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; -#else -#error "AUDIO_MAL_MODE_NORMAL or AUDIO_MAL_MODE_CIRCULAR should be selected !!" -#endif /* AUDIO_MAL_MODE_NORMAL */ - DMA_InitStructure.DMA_Priority = DMA_Priority_High; - DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; - DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; - DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; - DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; - DMA_Init(AUDIO_MAL_DMA_STREAM, &DMA_InitStructure); - - /* Enable the selected DMA interrupts (selected in "stm32f4_discovery_eval_audio_codec.h" defines) */ -#ifdef AUDIO_MAL_DMA_IT_TC_EN - DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_TC, ENABLE); -#endif /* AUDIO_MAL_DMA_IT_TC_EN */ -#ifdef AUDIO_MAL_DMA_IT_HT_EN - DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_HT, ENABLE); -#endif /* AUDIO_MAL_DMA_IT_HT_EN */ -#ifdef AUDIO_MAL_DMA_IT_TE_EN - DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_TE | DMA_IT_FE | DMA_IT_DME, ENABLE); -#endif /* AUDIO_MAL_DMA_IT_TE_EN */ - -#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN) - /* I2S DMA IRQ Channel configuration */ - NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); -#endif - } - -#ifdef DAC_USE_I2S_DMA - else - { - /* Enable the DMA clock */ - RCC_AHB1PeriphClockCmd(AUDIO_MAL_DMA_CLOCK, ENABLE); - - /* Configure the DMA Stream */ - DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE); - DMA_DeInit(AUDIO_MAL_DMA_STREAM); - /* Set the parameters to be configured */ - DMA_InitStructure.DMA_Channel = AUDIO_MAL_DMA_CHANNEL; - DMA_InitStructure.DMA_PeripheralBaseAddr = AUDIO_MAL_DMA_DREG; - DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)0; /* This field will be configured in play function */ - DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral; - DMA_InitStructure.DMA_BufferSize = (uint32_t)0xFFFE; /* This field will be configured in play function */ - DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; - DMA_InitStructure.DMA_PeripheralDataSize = AUDIO_MAL_DMA_PERIPH_DATA_SIZE; - DMA_InitStructure.DMA_MemoryDataSize = AUDIO_MAL_DMA_MEM_DATA_SIZE; -#ifdef AUDIO_MAL_MODE_NORMAL - DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; -#elif defined(AUDIO_MAL_MODE_CIRCULAR) - DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; -#else -#error "AUDIO_MAL_MODE_NORMAL or AUDIO_MAL_MODE_CIRCULAR should be selected !!" -#endif /* AUDIO_MAL_MODE_NORMAL */ - DMA_InitStructure.DMA_Priority = DMA_Priority_High; - DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable; - DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full; - DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single; - DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single; - DMA_Init(AUDIO_MAL_DMA_STREAM, &DMA_InitStructure); - - /* Enable the selected DMA interrupts (selected in "stm32f4_discovery_eval_audio_codec.h" defines) */ -#ifdef AUDIO_MAL_DMA_IT_TC_EN - DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_TC, ENABLE); -#endif /* AUDIO_MAL_DMA_IT_TC_EN */ -#ifdef AUDIO_MAL_DMA_IT_HT_EN - DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_HT, ENABLE); -#endif /* AUDIO_MAL_DMA_IT_HT_EN */ -#ifdef AUDIO_MAL_DMA_IT_TE_EN - DMA_ITConfig(AUDIO_MAL_DMA_STREAM, DMA_IT_TE | DMA_IT_FE | DMA_IT_DME, ENABLE); -#endif /* AUDIO_MAL_DMA_IT_TE_EN */ - -#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN) - /* I2S DMA IRQ Channel configuration */ - NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); -#endif - } -#endif /* DAC_USE_I2S_DMA */ - - if (CurrAudioInterface == AUDIO_INTERFACE_I2S) - { - /* Enable the I2S DMA request */ - SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE); - } - else - { - /* Configure the STM32 DAC to geenrate audio analog signal */ - DAC_Config(); - -#ifndef DAC_USE_I2S_DMA - /* Enable the I2S interrupt used to write into the DAC register */ - SPI_I2S_ITConfig(SPI3, SPI_I2S_IT_TXE, ENABLE); - - /* I2S DMA IRQ Channel configuration */ - NVIC_InitStructure.NVIC_IRQChannel = CODEC_I2S_IRQ; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO; - NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&NVIC_InitStructure); -#else - /* Enable the I2S DMA request */ - SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Rx, ENABLE); -#endif /* DAC_USE_I2S_DMA */ - } -#endif -} - -/** - * @brief Restore default state of the used Media. - * @param None - * @retval None - */ -static void Audio_MAL_DeInit(void) -{ -#if defined(AUDIO_MAL_DMA_IT_TC_EN) || defined(AUDIO_MAL_DMA_IT_HT_EN) || defined(AUDIO_MAL_DMA_IT_TE_EN) - NVIC_InitTypeDef NVIC_InitStructure; - - /* Deinitialize the NVIC interrupt for the I2S DMA Stream */ - NVIC_InitStructure.NVIC_IRQChannel = AUDIO_MAL_DMA_IRQ; - NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = EVAL_AUDIO_IRQ_PREPRIO; - NVIC_InitStructure.NVIC_IRQChannelSubPriority = EVAL_AUDIO_IRQ_SUBRIO; - NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE; - NVIC_Init(&NVIC_InitStructure); -#endif - - /* Disable the DMA stream before the deinit */ - DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE); - - /* Dinitialize the DMA Stream */ - DMA_DeInit(AUDIO_MAL_DMA_STREAM); - - /* - The DMA clock is not disabled, since it can be used by other streams - */ -} - -/** - * @brief Starts playing audio stream from the audio Media. - * @param None - * @retval None - */ -static void Audio_MAL_Play(uint32_t Addr, uint32_t Size) -{ - if (CurrAudioInterface == AUDIO_INTERFACE_I2S) - { - /* Configure the buffer address and size */ - DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)Addr; - DMA_InitStructure.DMA_BufferSize = (uint32_t)Size; - - /* Configure the DMA Stream with the new parameters */ - DMA_Init(AUDIO_MAL_DMA_STREAM, &DMA_InitStructure); - - /* Enable the I2S DMA Stream*/ - DMA_Cmd(AUDIO_MAL_DMA_STREAM, ENABLE); - } -#ifndef DAC_USE_I2S_DMA - else - { - /* Configure the buffer address and size */ - DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)Addr; - DMA_InitStructure.DMA_BufferSize = (uint32_t)Size; - - /* Configure the DMA Stream with the new parameters */ - DMA_Init(AUDIO_MAL_DMA_STREAM, &DMA_InitStructure); - - /* Enable the I2S DMA Stream*/ - DMA_Cmd(AUDIO_MAL_DMA_STREAM, ENABLE); - } -#endif /* DAC_USE_I2S_DMA */ - - /* If the I2S peripheral is still not enabled, enable it */ - if ((CODEC_I2S->I2SCFGR & I2S_ENABLE_MASK) == 0) - { - I2S_Cmd(CODEC_I2S, ENABLE); - } -} - -/** - * @brief Pauses or Resumes the audio stream playing from the Media. - * @param Cmd: AUDIO_PAUSE (or 0) to pause, AUDIO_RESUME (or any value different - * from 0) to resume. - * @param Addr: Address from/at which the audio stream should resume/pause. - * @retval None - */ -static void Audio_MAL_PauseResume(uint32_t Cmd, uint32_t Addr) -{ - /* Pause the audio file playing */ - if (Cmd == AUDIO_PAUSE) - { - /* Disable the I2S DMA request */ - SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, DISABLE); - - /* Pause the I2S DMA Stream - Note. For the STM32F4xx devices, the DMA implements a pause feature, - by disabling the stream, all configuration is preserved and data - transfer is paused till the next enable of the stream. - This feature is not available on STM32F4xx devices. */ - DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE); - } - else /* AUDIO_RESUME */ - { - /* Enable the I2S DMA request */ - SPI_I2S_DMACmd(CODEC_I2S, SPI_I2S_DMAReq_Tx, ENABLE); - - /* Resume the I2S DMA Stream - Note. For the STM32F4xx devices, the DMA implements a pause feature, - by disabling the stream, all configuration is preserved and data - transfer is paused till the next enable of the stream. - This feature is not available on STM32F4xx devices. */ - DMA_Cmd(AUDIO_MAL_DMA_STREAM, ENABLE); - - /* If the I2S peripheral is still not enabled, enable it */ - if ((CODEC_I2S->I2SCFGR & I2S_ENABLE_MASK) == 0) - { - I2S_Cmd(CODEC_I2S, ENABLE); - } - } -} - -/** - * @brief Stops audio stream playing on the used Media. - * @param None - * @retval None - */ -static void Audio_MAL_Stop(void) -{ - /* Stop the Transfer on the I2S side: Stop and disable the DMA stream */ - DMA_Cmd(AUDIO_MAL_DMA_STREAM, DISABLE); - - /* Clear all the DMA flags for the next transfer */ - DMA_ClearFlag(AUDIO_MAL_DMA_STREAM, AUDIO_MAL_DMA_FLAG_TC |AUDIO_MAL_DMA_FLAG_HT | \ - AUDIO_MAL_DMA_FLAG_FE | AUDIO_MAL_DMA_FLAG_TE); - - /* - The I2S DMA requests are not disabled here. - */ - - /* In all modes, disable the I2S peripheral */ - I2S_Cmd(CODEC_I2S, DISABLE); -} - -/** - * @brief DAC Channel1 Configuration - * @param None - * @retval None - */ -void DAC_Config(void) -{ - DAC_InitTypeDef DAC_InitStructure; - GPIO_InitTypeDef GPIO_InitStructure; - - /* DMA1 clock and GPIOA clock enable (to be used with DAC) */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1 | RCC_AHB1Periph_GPIOA, ENABLE); - - /* DAC Periph clock enable */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE); - - /* DAC channel 1 & 2 (DAC_OUT1 = PA.4) configuration */ - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(GPIOA, &GPIO_InitStructure); - - /* DAC channel1 Configuration */ - DAC_InitStructure.DAC_Trigger = DAC_Trigger_None; - DAC_InitStructure.DAC_WaveGeneration = DAC_WaveGeneration_None; - DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable; - DAC_Init(AUDIO_DAC_CHANNEL, &DAC_InitStructure); - - /* Enable DAC Channel1 */ - DAC_Cmd(AUDIO_DAC_CHANNEL, ENABLE); -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery_audio_codec.h b/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery_audio_codec.h deleted file mode 100644 index 33ba0e77d..000000000 --- a/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery_audio_codec.h +++ /dev/null @@ -1,304 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4_discovery_audio_codec.h - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief This file contains all the functions prototypes for the - * stm32f4_discovery_audio_codec.c driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4_DISCOVERY_AUDIOCODEC_H -#define __STM32F4_DISCOVERY_AUDIOCODEC_H - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" -#include "stm32f4xx_gpio.h" - -/** @addtogroup Utilities - * @{ - */ - - -/** @addtogroup STM32F4_DISCOVERY - * @{ - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC - * @{ - */ - - -/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Exported_Types - * @{ - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Exported_Constants - * @{ - */ - -/*------------------------------------ - CONFIGURATION: Audio Codec Driver Configuration parameters - ----------------------------------------*/ -#define I2S_INTERRUPT -/* Audio Transfer mode (DMA, Interrupt or Polling) */ -#define AUDIO_MAL_MODE_NORMAL /* Uncomment this line to enable the audio - Transfer using DMA */ -/* #define AUDIO_MAL_MODE_CIRCULAR */ /* Uncomment this line to enable the audio - Transfer using DMA */ - -/* For the DMA modes select the interrupt that will be used */ -#define AUDIO_MAL_DMA_IT_TC_EN /* Uncomment this line to enable DMA Transfer Complete interrupt */ -/* #define AUDIO_MAL_DMA_IT_HT_EN */ /* Uncomment this line to enable DMA Half Transfer Complete interrupt */ -/* #define AUDIO_MAL_DMA_IT_TE_EN */ /* Uncomment this line to enable DMA Transfer Error interrupt */ - -/* Select the interrupt preemption priority and subpriority for the DMA interrupt */ -#define EVAL_AUDIO_IRQ_PREPRIO 0 /* Select the preemption priority level(0 is the highest) */ -#define EVAL_AUDIO_IRQ_SUBRIO 0 /* Select the sub-priority level (0 is the highest) */ - -/* Uncomment the following line to use the default Codec_TIMEOUT_UserCallback() - function implemented in stm32f4_discovery_audio_codec.c file. - Codec_TIMEOUT_UserCallback() function is called whenever a timeout condition - occurs during communication (waiting on an event that doesn't occur, bus - errors, busy devices ...). */ -/* #define USE_DEFAULT_TIMEOUT_CALLBACK */ - -/* Enable this define to use the I2S DMA for writing into DAC register */ -//#define DAC_USE_I2S_DMA -/*----------------------------------------------------------------------------*/ - -/*------------------------------------ - OPTIONAL Configuration defines parameters - ----------------------------------------*/ -/* I2C clock speed configuration (in Hz) - WARNING: - Make sure that this define is not already declared in other files (ie. - stm322xg_eval.h file). It can be used in parallel by other modules. */ -#ifndef I2C_SPEED - #define I2C_SPEED 100000 -#endif /* I2C_SPEED */ - -/* Uncomment defines below to select standard for audio communication between - Codec and I2S peripheral */ -#define I2S_STANDARD_PHILLIPS -/* #define I2S_STANDARD_MSB */ -/* #define I2S_STANDARD_LSB */ - -/* Uncomment the defines below to select if the Master clock mode should be - enabled or not */ -#define CODEC_MCLK_ENABLED -/* #deine CODEC_MCLK_DISABLED */ - -/* Uncomment this line to enable verifying data sent to codec after each write - operation */ -#define VERIFY_WRITTENDATA -/*----------------------------------------------------------------------------*/ - -/*----------------------------------- - Hardware Configuration defines parameters - -----------------------------------------*/ -/* Audio Reset Pin definition */ -#define AUDIO_RESET_GPIO_CLK RCC_AHB1Periph_GPIOD -#define AUDIO_RESET_PIN GPIO_Pin_4 -#define AUDIO_RESET_GPIO GPIOD - -/* I2S peripheral configuration defines */ -#define CODEC_I2S SPI3 -#define CODEC_I2S_CLK RCC_APB1Periph_SPI3 -#define CODEC_I2S_ADDRESS 0x40003C0C -#define CODEC_I2S_GPIO_AF GPIO_AF_SPI3 -#define CODEC_I2S_IRQ SPI3_IRQn -#define CODEC_I2S_GPIO_CLOCK (RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOA) -#define CODEC_I2S_WS_PIN GPIO_Pin_4 -#define CODEC_I2S_SCK_PIN GPIO_Pin_10 -#define CODEC_I2S_SD_PIN GPIO_Pin_12 -#define CODEC_I2S_MCK_PIN GPIO_Pin_7 -#define CODEC_I2S_WS_PINSRC GPIO_PinSource4 -#define CODEC_I2S_SCK_PINSRC GPIO_PinSource10 -#define CODEC_I2S_SD_PINSRC GPIO_PinSource12 -#define CODEC_I2S_MCK_PINSRC GPIO_PinSource7 -#define CODEC_I2S_GPIO GPIOC -#define CODEC_I2S_WS_GPIO GPIOA -#define CODEC_I2S_MCK_GPIO GPIOC -#define Audio_I2S_IRQHandler SPI3_IRQHandler - - - #define AUDIO_MAL_DMA_PERIPH_DATA_SIZE DMA_PeripheralDataSize_HalfWord - #define AUDIO_MAL_DMA_MEM_DATA_SIZE DMA_MemoryDataSize_HalfWord - #define DMA_MAX_SZE 0xFFFF - - - #define DAC_DHR12L1_ADDRESS 0x4000740C - #define DAC_DHR12R1_ADDRESS 0x40007408 - #define DAC_DHR8R1_ADDRESS 0x40007410 - #define AUDIO_DAC_CHANNEL DAC_Channel_1 - - /* I2S DMA Stream definitions */ - #define AUDIO_I2S_DMA_CLOCK RCC_AHB1Periph_DMA1 - #define AUDIO_I2S_DMA_STREAM DMA1_Stream7 - #define AUDIO_I2S_DMA_DREG CODEC_I2S_ADDRESS - #define AUDIO_I2S_DMA_CHANNEL DMA_Channel_0 - #define AUDIO_I2S_DMA_IRQ DMA1_Stream7_IRQn - #define AUDIO_I2S_DMA_FLAG_TC DMA_FLAG_TCIF7 - #define AUDIO_I2S_DMA_FLAG_HT DMA_FLAG_HTIF7 - #define AUDIO_I2S_DMA_FLAG_FE DMA_FLAG_FEIF7 - #define AUDIO_I2S_DMA_FLAG_TE DMA_FLAG_TEIF7 - #define AUDIO_I2S_DMA_FLAG_DME DMA_FLAG_DMEIF7 - - #define Audio_MAL_I2S_IRQHandler DMA1_Stream7_IRQHandler - - - /* DAC DMA Stream definitions */ - #define AUDIO_DAC_DMA_CLOCK RCC_AHB1Periph_DMA1 - #define AUDIO_DAC_DMA_STREAM DMA1_Stream0 - #define AUDIO_DAC_DMA_DREG DAC_DHR12L1_ADDRESS - #define AUDIO_DAC_DMA_CHANNEL DMA_Channel_0 - #define AUDIO_DAC_DMA_IRQ DMA1_Stream0_IRQn - #define AUDIO_DAC_DMA_FLAG_TC DMA_FLAG_TCIF0 - #define AUDIO_DAC_DMA_FLAG_HT DMA_FLAG_HTIF0 - #define AUDIO_DAC_DMA_FLAG_FE DMA_FLAG_FEIF0 - #define AUDIO_DAC_DMA_FLAG_TE DMA_FLAG_TEIF0 - #define AUDIO_DAC_DMA_FLAG_DME DMA_FLAG_DMEIF0 - - #define Audio_MAL_DAC_IRQHandler DMA1_Stream0_IRQHandler - - -/* I2C peripheral configuration defines (control interface of the audio codec) */ -#define CODEC_I2C I2C1 -#define CODEC_I2C_CLK RCC_APB1Periph_I2C1 -#define CODEC_I2C_GPIO_CLOCK RCC_AHB1Periph_GPIOB -#define CODEC_I2C_GPIO_AF GPIO_AF_I2C1 -#define CODEC_I2C_GPIO GPIOB -#define CODEC_I2C_SCL_PIN GPIO_Pin_6 -#define CODEC_I2C_SDA_PIN GPIO_Pin_9 -#define CODEC_I2S_SCL_PINSRC GPIO_PinSource6 -#define CODEC_I2S_SDA_PINSRC GPIO_PinSource9 - -/* Maximum Timeout values for flags and events waiting loops. These timeouts are - not based on accurate values, they just guarantee that the application will - not remain stuck if the I2C communication is corrupted. - You may modify these timeout values depending on CPU frequency and application - conditions (interrupts routines ...). */ -#define CODEC_FLAG_TIMEOUT ((uint32_t)0x1000) -#define CODEC_LONG_TIMEOUT ((uint32_t)(300 * CODEC_FLAG_TIMEOUT)) -/*----------------------------------------------------------------------------*/ - -/*----------------------------------- - Audio Codec User defines - -----------------------------------------*/ -/* Audio interface : I2S or DAC */ -#define AUDIO_INTERFACE_I2S 1 -#define AUDIO_INTERFACE_DAC 2 - -/* Codec output DEVICE */ -#define OUTPUT_DEVICE_SPEAKER 1 -#define OUTPUT_DEVICE_HEADPHONE 2 -#define OUTPUT_DEVICE_BOTH 3 -#define OUTPUT_DEVICE_AUTO 4 - -/* Volume Levels values */ -#define DEFAULT_VOLMIN 0x00 -#define DEFAULT_VOLMAX 0xFF -#define DEFAULT_VOLSTEP 0x04 - -#define AUDIO_PAUSE 0 -#define AUDIO_RESUME 1 - -/* Codec POWER DOWN modes */ -#define CODEC_PDWN_HW 1 -#define CODEC_PDWN_SW 2 - -/* MUTE commands */ -#define AUDIO_MUTE_ON 1 -#define AUDIO_MUTE_OFF 0 -/*----------------------------------------------------------------------------*/ -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Exported_Macros - * @{ - */ -#define VOLUME_CONVERT(x) ((Volume > 100)? 100:((uint8_t)((Volume * 255) / 100))) -#define DMA_MAX(x) (((x) <= DMA_MAX_SZE)? (x):DMA_MAX_SZE) - -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_AUDIO_CODEC_Exported_Functions - * @{ - */ -void EVAL_AUDIO_SetAudioInterface(uint32_t Interface); -uint32_t EVAL_AUDIO_Init(uint16_t OutputDevice, uint8_t Volume, uint32_t AudioFreq); -uint32_t EVAL_AUDIO_DeInit(void); -uint32_t EVAL_AUDIO_Play(uint16_t* pBuffer, uint32_t Size); -uint32_t EVAL_AUDIO_PauseResume(uint32_t Cmd); -uint32_t EVAL_AUDIO_Stop(uint32_t CodecPowerDown_Mode); -uint32_t EVAL_AUDIO_VolumeCtl(uint8_t Volume); -uint32_t EVAL_AUDIO_Mute(uint32_t Command); -void DAC_Config(void); - -/* User Callbacks: user has to implement these functions in his code if - they are needed. -----------------------------------------------------------*/ - -uint16_t EVAL_AUDIO_GetSampleCallBack(void); - -/* This function is called when the requested data has been completely transferred. - In Normal mode (when the define AUDIO_MAL_MODE_NORMAL is enabled) this function - is called at the end of the whole audio file. - In circular mode (when the define AUDIO_MAL_MODE_CIRCULAR is enabled) this - function is called at the end of the current buffer transmission. */ -void EVAL_AUDIO_TransferComplete_CallBack(uint32_t pBuffer, uint32_t Size); - -/* This function is called when half of the requested buffer has been transferred - This callback is useful in Circular mode only (when AUDIO_MAL_MODE_CIRCULAR - define is enabled)*/ -void EVAL_AUDIO_HalfTransfer_CallBack(uint32_t pBuffer, uint32_t Size); - -/* This function is called when an Interrupt due to transfer error on or peripheral - error occurs. */ -void EVAL_AUDIO_Error_CallBack(void* pData); - -/* Codec_TIMEOUT_UserCallback() function is called whenever a timeout condition - occurs during communication (waiting on an event that doesn't occur, bus - errors, busy devices ...) on the Codec control interface (I2C). - You can use the default timeout callback implementation by uncommenting the - define USE_DEFAULT_TIMEOUT_CALLBACK in stm32f4_discovery_audio_codec.h file. - Typically the user implementation of this callback should reset I2C peripheral - and re-initialize communication or in worst case reset all the application. */ -uint32_t Codec_TIMEOUT_UserCallback(void); - -#endif /* __STM32F4_DISCOVERY_AUDIOCODEC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery_lis302dl.c b/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery_lis302dl.c deleted file mode 100644 index d354dc453..000000000 --- a/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery_lis302dl.c +++ /dev/null @@ -1,504 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4_discovery_lis302dl.c - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief This file provides a set of functions needed to manage the LIS302DL - * MEMS accelerometer available on STM32F4-Discovery Kit. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4_discovery_lis302dl.h" -//ADDED BY ME!!!!!!!!!!!!!!!!!!!! -#include "stm32f4xx_conf.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY_LIS302DL - * @{ - */ - - -/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Defines - * @{ - */ -__IO uint32_t LIS302DLTimeout = LIS302DL_FLAG_TIMEOUT; - -/* Read/Write command */ -#define READWRITE_CMD ((uint8_t)0x80) -/* Multiple byte read/write command */ -#define MULTIPLEBYTE_CMD ((uint8_t)0x40) -/* Dummy Byte Send by the SPI Master device in order to generate the Clock to the Slave device */ -#define DUMMY_BYTE ((uint8_t)0x00) - -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Variables - * @{ - */ - -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_FunctionPrototypes - * @{ - */ -static uint8_t LIS302DL_SendByte(uint8_t byte); -static void LIS302DL_LowLevel_Init(void); -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_LIS302DL_Private_Functions - * @{ - */ - - -/** - * @brief Set LIS302DL Initialization. - * @param LIS302DL_Config_Struct: pointer to a LIS302DL_Config_TypeDef structure - * that contains the configuration setting for the LIS302DL. - * @retval None - */ -void LIS302DL_Init(LIS302DL_InitTypeDef *LIS302DL_InitStruct) -{ - uint8_t ctrl = 0x00; - - /* Configure the low level interface ---------------------------------------*/ - LIS302DL_LowLevel_Init(); - - /* Configure MEMS: data rate, power mode, full scale, self test and axes */ - ctrl = (uint8_t) (LIS302DL_InitStruct->Output_DataRate | LIS302DL_InitStruct->Power_Mode | \ - LIS302DL_InitStruct->Full_Scale | LIS302DL_InitStruct->Self_Test | \ - LIS302DL_InitStruct->Axes_Enable); - - /* Write value to MEMS CTRL_REG1 regsister */ - LIS302DL_Write(&ctrl, LIS302DL_CTRL_REG1_ADDR, 1); -} - -/** - * @brief Set LIS302DL Internal High Pass Filter configuration. - * @param LIS302DL_Filter_ConfigTypeDef: pointer to a LIS302DL_FilterConfig_TypeDef - * structure that contains the configuration setting for the LIS302DL Filter. - * @retval None - */ -void LIS302DL_FilterConfig(LIS302DL_FilterConfigTypeDef *LIS302DL_FilterConfigStruct) -{ - uint8_t ctrl = 0x00; - - /* Read CTRL_REG2 register */ - LIS302DL_Read(&ctrl, LIS302DL_CTRL_REG2_ADDR, 1); - - /* Clear high pass filter cut-off level, interrupt and data selection bits*/ - ctrl &= (uint8_t)~(LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER | \ - LIS302DL_HIGHPASSFILTER_LEVEL_3 | \ - LIS302DL_HIGHPASSFILTERINTERRUPT_1_2); - /* Configure MEMS high pass filter cut-off level, interrupt and data selection bits */ - ctrl |= (uint8_t)(LIS302DL_FilterConfigStruct->HighPassFilter_Data_Selection | \ - LIS302DL_FilterConfigStruct->HighPassFilter_CutOff_Frequency | \ - LIS302DL_FilterConfigStruct->HighPassFilter_Interrupt); - - /* Write value to MEMS CTRL_REG2 register */ - LIS302DL_Write(&ctrl, LIS302DL_CTRL_REG2_ADDR, 1); -} - -/** - * @brief Set LIS302DL Interrupt configuration - * @param LIS302DL_InterruptConfig_TypeDef: pointer to a LIS302DL_InterruptConfig_TypeDef - * structure that contains the configuration setting for the LIS302DL Interrupt. - * @retval None - */ -void LIS302DL_InterruptConfig(LIS302DL_InterruptConfigTypeDef *LIS302DL_IntConfigStruct) -{ - uint8_t ctrl = 0x00; - - /* Read CLICK_CFG register */ - LIS302DL_Read(&ctrl, LIS302DL_CLICK_CFG_REG_ADDR, 1); - - /* Configure latch Interrupt request, click interrupts and double click interrupts */ - ctrl = (uint8_t)(LIS302DL_IntConfigStruct->Latch_Request| \ - LIS302DL_IntConfigStruct->SingleClick_Axes | \ - LIS302DL_IntConfigStruct->DoubleClick_Axes); - - /* Write value to MEMS CLICK_CFG register */ - LIS302DL_Write(&ctrl, LIS302DL_CLICK_CFG_REG_ADDR, 1); -} - -/** - * @brief Change the lowpower mode for LIS302DL - * @param LowPowerMode: new state for the lowpower mode. - * This parameter can be one of the following values: - * @arg LIS302DL_LOWPOWERMODE_POWERDOWN: Power down mode - * @arg LIS302DL_LOWPOWERMODE_ACTIVE: Active mode - * @retval None - */ -void LIS302DL_LowpowerCmd(uint8_t LowPowerMode) -{ - uint8_t tmpreg; - - /* Read CTRL_REG1 register */ - LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1); - - /* Set new low power mode configuration */ - tmpreg &= (uint8_t)~LIS302DL_LOWPOWERMODE_ACTIVE; - tmpreg |= LowPowerMode; - - /* Write value to MEMS CTRL_REG1 regsister */ - LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1); -} - -/** - * @brief Data Rate command - * @param DataRateValue: Data rate value - * This parameter can be one of the following values: - * @arg LIS302DL_DATARATE_100: 100 Hz output data rate - * @arg LIS302DL_DATARATE_400: 400 Hz output data rate - * @retval None - */ -void LIS302DL_DataRateCmd(uint8_t DataRateValue) -{ - uint8_t tmpreg; - - /* Read CTRL_REG1 register */ - LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1); - - /* Set new Data rate configuration */ - tmpreg &= (uint8_t)~LIS302DL_DATARATE_400; - tmpreg |= DataRateValue; - - /* Write value to MEMS CTRL_REG1 regsister */ - LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1); -} - -/** - * @brief Change the Full Scale of LIS302DL - * @param FS_value: new full scale value. - * This parameter can be one of the following values: - * @arg LIS302DL_FULLSCALE_2_3: +-2.3g - * @arg LIS302DL_FULLSCALE_9_2: +-9.2g - * @retval None - */ -void LIS302DL_FullScaleCmd(uint8_t FS_value) -{ - uint8_t tmpreg; - - /* Read CTRL_REG1 register */ - LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1); - - /* Set new full scale configuration */ - tmpreg &= (uint8_t)~LIS302DL_FULLSCALE_9_2; - tmpreg |= FS_value; - - /* Write value to MEMS CTRL_REG1 regsister */ - LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG1_ADDR, 1); -} - -/** - * @brief Reboot memory content of LIS302DL - * @param None - * @retval None - */ -void LIS302DL_RebootCmd(void) -{ - uint8_t tmpreg; - /* Read CTRL_REG2 register */ - LIS302DL_Read(&tmpreg, LIS302DL_CTRL_REG2_ADDR, 1); - - /* Enable or Disable the reboot memory */ - tmpreg |= LIS302DL_BOOT_REBOOTMEMORY; - - /* Write value to MEMS CTRL_REG2 regsister */ - LIS302DL_Write(&tmpreg, LIS302DL_CTRL_REG2_ADDR, 1); -} - -/** - * @brief Writes one byte to the LIS302DL. - * @param pBuffer : pointer to the buffer containing the data to be written to the LIS302DL. - * @param WriteAddr : LIS302DL's internal address to write to. - * @param NumByteToWrite: Number of bytes to write. - * @retval None - */ -void LIS302DL_Write(uint8_t* pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite) -{ - /* Configure the MS bit: - - When 0, the address will remain unchanged in multiple read/write commands. - - When 1, the address will be auto incremented in multiple read/write commands. - */ - if(NumByteToWrite > 0x01) - { - WriteAddr |= (uint8_t)MULTIPLEBYTE_CMD; - } - /* Set chip select Low at the start of the transmission */ - LIS302DL_CS_LOW(); - - /* Send the Address of the indexed register */ - LIS302DL_SendByte(WriteAddr); - /* Send the data that will be written into the device (MSB First) */ - while(NumByteToWrite >= 0x01) - { - LIS302DL_SendByte(*pBuffer); - NumByteToWrite--; - pBuffer++; - } - - /* Set chip select High at the end of the transmission */ - LIS302DL_CS_HIGH(); -} - -/** - * @brief Reads a block of data from the LIS302DL. - * @param pBuffer : pointer to the buffer that receives the data read from the LIS302DL. - * @param ReadAddr : LIS302DL's internal address to read from. - * @param NumByteToRead : number of bytes to read from the LIS302DL. - * @retval None - */ -void LIS302DL_Read(uint8_t* pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead) -{ - if(NumByteToRead > 0x01) - { - ReadAddr |= (uint8_t)(READWRITE_CMD | MULTIPLEBYTE_CMD); - } - else - { - ReadAddr |= (uint8_t)READWRITE_CMD; - } - /* Set chip select Low at the start of the transmission */ - LIS302DL_CS_LOW(); - - /* Send the Address of the indexed register */ - LIS302DL_SendByte(ReadAddr); - - /* Receive the data that will be read from the device (MSB First) */ - while(NumByteToRead > 0x00) - { - /* Send dummy byte (0x00) to generate the SPI clock to LIS302DL (Slave device) */ - *pBuffer = LIS302DL_SendByte(DUMMY_BYTE); - NumByteToRead--; - pBuffer++; - } - - /* Set chip select High at the end of the transmission */ - LIS302DL_CS_HIGH(); -} - -/** - * @brief Read LIS302DL output register, and calculate the acceleration - * ACC[mg]=SENSITIVITY* (out_h*256+out_l)/16 (12 bit rappresentation) - * @param s16 buffer to store data - * @retval None - */ -void LIS302DL_ReadACC(int32_t* out) -{ - uint8_t buffer[6]; - uint8_t crtl, i = 0x00; - - LIS302DL_Read(&crtl, LIS302DL_CTRL_REG1_ADDR, 1); - LIS302DL_Read(buffer, LIS302DL_OUT_X_ADDR, 6); - - switch(crtl & 0x20) - { - /* FS bit = 0 ==> Sensitivity typical value = 18milligals/digit*/ - case 0x00: - for(i=0; i<0x03; i++) - { - *out =(int32_t)(LIS302DL_SENSITIVITY_2_3G * (int8_t)buffer[2*i]); - out++; - } - break; - /* FS bit = 1 ==> Sensitivity typical value = 72milligals/digit*/ - case 0x20: - for(i=0; i<0x03; i++) - { - *out =(int32_t)(LIS302DL_SENSITIVITY_9_2G * (int8_t)buffer[2*i]); - out++; - } - break; - default: - break; - } - } - -/** - * @brief Initializes the low level interface used to drive the LIS302DL - * @param None - * @retval None - */ -static void LIS302DL_LowLevel_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - SPI_InitTypeDef SPI_InitStructure; - - /* Enable the SPI periph */ - RCC_APB2PeriphClockCmd(LIS302DL_SPI_CLK, ENABLE); - - /* Enable SCK, MOSI and MISO GPIO clocks */ - RCC_AHB1PeriphClockCmd(LIS302DL_SPI_SCK_GPIO_CLK | LIS302DL_SPI_MISO_GPIO_CLK | LIS302DL_SPI_MOSI_GPIO_CLK, ENABLE); - - /* Enable CS GPIO clock */ - RCC_AHB1PeriphClockCmd(LIS302DL_SPI_CS_GPIO_CLK, ENABLE); - - /* Enable INT1 GPIO clock */ - RCC_AHB1PeriphClockCmd(LIS302DL_SPI_INT1_GPIO_CLK, ENABLE); - - /* Enable INT2 GPIO clock */ - RCC_AHB1PeriphClockCmd(LIS302DL_SPI_INT2_GPIO_CLK, ENABLE); - - GPIO_PinAFConfig(LIS302DL_SPI_SCK_GPIO_PORT, LIS302DL_SPI_SCK_SOURCE, LIS302DL_SPI_SCK_AF); - GPIO_PinAFConfig(LIS302DL_SPI_MISO_GPIO_PORT, LIS302DL_SPI_MISO_SOURCE, LIS302DL_SPI_MISO_AF); - GPIO_PinAFConfig(LIS302DL_SPI_MOSI_GPIO_PORT, LIS302DL_SPI_MOSI_SOURCE, LIS302DL_SPI_MOSI_AF); - - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - - /* SPI SCK pin configuration */ - GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_SCK_PIN; - GPIO_Init(LIS302DL_SPI_SCK_GPIO_PORT, &GPIO_InitStructure); - - /* SPI MOSI pin configuration */ - GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_MOSI_PIN; - GPIO_Init(LIS302DL_SPI_MOSI_GPIO_PORT, &GPIO_InitStructure); - - /* SPI MISO pin configuration */ - GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_MISO_PIN; - GPIO_Init(LIS302DL_SPI_MISO_GPIO_PORT, &GPIO_InitStructure); - - /* SPI configuration -------------------------------------------------------*/ - SPI_I2S_DeInit(LIS302DL_SPI); - SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; - SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; - SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; - SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; - SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_4; - SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; - SPI_InitStructure.SPI_CRCPolynomial = 7; - SPI_InitStructure.SPI_Mode = SPI_Mode_Master; - SPI_Init(LIS302DL_SPI, &SPI_InitStructure); - - /* Enable SPI1 */ - SPI_Cmd(LIS302DL_SPI, ENABLE); - - /* Configure GPIO PIN for Lis Chip select */ - GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_CS_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(LIS302DL_SPI_CS_GPIO_PORT, &GPIO_InitStructure); - - /* Deselect : Chip Select high */ - GPIO_SetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN); - - /* Configure GPIO PINs to detect Interrupts */ - GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_INT1_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(LIS302DL_SPI_INT1_GPIO_PORT, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LIS302DL_SPI_INT2_PIN; - GPIO_Init(LIS302DL_SPI_INT2_GPIO_PORT, &GPIO_InitStructure); -} - -/** - * @brief Sends a Byte through the SPI interface and return the Byte received - * from the SPI bus. - * @param Byte : Byte send. - * @retval The received byte value - */ -static uint8_t LIS302DL_SendByte(uint8_t byte) -{ - /* Loop while DR register in not emplty */ - LIS302DLTimeout = LIS302DL_FLAG_TIMEOUT; - while (SPI_I2S_GetFlagStatus(LIS302DL_SPI, SPI_I2S_FLAG_TXE) == RESET) - { - if((LIS302DLTimeout--) == 0) return LIS302DL_TIMEOUT_UserCallback(); - } - - /* Send a Byte through the SPI peripheral */ - SPI_I2S_SendData(LIS302DL_SPI, byte); - - /* Wait to receive a Byte */ - LIS302DLTimeout = LIS302DL_FLAG_TIMEOUT; - while (SPI_I2S_GetFlagStatus(LIS302DL_SPI, SPI_I2S_FLAG_RXNE) == RESET) - { - if((LIS302DLTimeout--) == 0) return LIS302DL_TIMEOUT_UserCallback(); - } - - /* Return the Byte read from the SPI bus */ - return (uint8_t)SPI_I2S_ReceiveData(LIS302DL_SPI); -} - -#ifdef USE_DEFAULT_TIMEOUT_CALLBACK -/** - * @brief Basic management of the timeout situation. - * @param None. - * @retval None. - */ -uint32_t LIS302DL_TIMEOUT_UserCallback(void) -{ - /* Block communication and all processes */ - while (1) - { - } -} -#endif /* USE_DEFAULT_TIMEOUT_CALLBACK */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery_lis302dl.h b/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery_lis302dl.h deleted file mode 100644 index b99cb8091..000000000 --- a/example/stm32f4/Utilities/STM32F4-Discovery/stm32f4_discovery_lis302dl.h +++ /dev/null @@ -1,772 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4_discovery_lis302dl.h - * @author MCD Application Team - * @version V1.0.0 - * @date 19-September-2011 - * @brief This file contains all the functions prototypes for the stm32f4_discovery_lis302dl.c - * firmware driver. - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4_DISCOVERY_LIS302DL_H -#define __STM32F4_DISCOVERY_LIS302DL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ - #include "stm32f4xx.h" - -/** @addtogroup Utilities - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY - * @{ - */ - -/** @addtogroup STM32F4_DISCOVERY_LIS302DL - * @{ - */ - - -/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Types - * @{ - */ - -/* LIS302DL struct */ -typedef struct -{ - uint8_t Power_Mode; /* Power-down/Active Mode */ - uint8_t Output_DataRate; /* OUT data rate 100 Hz / 400 Hz */ - uint8_t Axes_Enable; /* Axes enable */ - uint8_t Full_Scale; /* Full scale */ - uint8_t Self_Test; /* Self test */ -}LIS302DL_InitTypeDef; - -/* LIS302DL High Pass Filter struct */ -typedef struct -{ - uint8_t HighPassFilter_Data_Selection; /* Internal filter bypassed or data from internal filter send to output register*/ - uint8_t HighPassFilter_CutOff_Frequency; /* High pass filter cut-off frequency */ - uint8_t HighPassFilter_Interrupt; /* High pass filter enabled for Freefall/WakeUp #1 or #2 */ -}LIS302DL_FilterConfigTypeDef; - -/* LIS302DL Interrupt struct */ -typedef struct -{ - uint8_t Latch_Request; /* Latch interrupt request into CLICK_SRC register*/ - uint8_t SingleClick_Axes; /* Single Click Axes Interrupts */ - uint8_t DoubleClick_Axes; /* Double Click Axes Interrupts */ -}LIS302DL_InterruptConfigTypeDef; - -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Constants - * @{ - */ - -/* Uncomment the following line to use the default LIS302DL_TIMEOUT_UserCallback() - function implemented in stm32f4_discovery_lis302dl.c file. - LIS302DL_TIMEOUT_UserCallback() function is called whenever a timeout condition - occure during communication (waiting transmit data register empty flag(TXE) - or waiting receive data register is not empty flag (RXNE)). */ -/* #define USE_DEFAULT_TIMEOUT_CALLBACK */ - -/* Maximum Timeout values for flags waiting loops. These timeouts are not based - on accurate values, they just guarantee that the application will not remain - stuck if the SPI communication is corrupted. - You may modify these timeout values depending on CPU frequency and application - conditions (interrupts routines ...). */ -#define LIS302DL_FLAG_TIMEOUT ((uint32_t)0x1000) - -/** - * @brief LIS302DL SPI Interface pins - */ -#define LIS302DL_SPI SPI1 -#define LIS302DL_SPI_CLK RCC_APB2Periph_SPI1 - -#define LIS302DL_SPI_SCK_PIN GPIO_Pin_5 /* PA.05 */ -#define LIS302DL_SPI_SCK_GPIO_PORT GPIOA /* GPIOA */ -#define LIS302DL_SPI_SCK_GPIO_CLK RCC_AHB1Periph_GPIOA -#define LIS302DL_SPI_SCK_SOURCE GPIO_PinSource5 -#define LIS302DL_SPI_SCK_AF GPIO_AF_SPI1 - -#define LIS302DL_SPI_MISO_PIN GPIO_Pin_6 /* PA.6 */ -#define LIS302DL_SPI_MISO_GPIO_PORT GPIOA /* GPIOA */ -#define LIS302DL_SPI_MISO_GPIO_CLK RCC_AHB1Periph_GPIOA -#define LIS302DL_SPI_MISO_SOURCE GPIO_PinSource6 -#define LIS302DL_SPI_MISO_AF GPIO_AF_SPI1 - -#define LIS302DL_SPI_MOSI_PIN GPIO_Pin_7 /* PA.7 */ -#define LIS302DL_SPI_MOSI_GPIO_PORT GPIOA /* GPIOA */ -#define LIS302DL_SPI_MOSI_GPIO_CLK RCC_AHB1Periph_GPIOA -#define LIS302DL_SPI_MOSI_SOURCE GPIO_PinSource7 -#define LIS302DL_SPI_MOSI_AF GPIO_AF_SPI1 - -#define LIS302DL_SPI_CS_PIN GPIO_Pin_3 /* PE.03 */ -#define LIS302DL_SPI_CS_GPIO_PORT GPIOE /* GPIOE */ -#define LIS302DL_SPI_CS_GPIO_CLK RCC_AHB1Periph_GPIOE - -#define LIS302DL_SPI_INT1_PIN GPIO_Pin_0 /* PE.00 */ -#define LIS302DL_SPI_INT1_GPIO_PORT GPIOE /* GPIOE */ -#define LIS302DL_SPI_INT1_GPIO_CLK RCC_AHB1Periph_GPIOE -#define LIS302DL_SPI_INT1_EXTI_LINE EXTI_Line0 -#define LIS302DL_SPI_INT1_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE -#define LIS302DL_SPI_INT1_EXTI_PIN_SOURCE EXTI_PinSource0 -#define LIS302DL_SPI_INT1_EXTI_IRQn EXTI0_IRQn - -#define LIS302DL_SPI_INT2_PIN GPIO_Pin_1 /* PE.01 */ -#define LIS302DL_SPI_INT2_GPIO_PORT GPIOE /* GPIOE */ -#define LIS302DL_SPI_INT2_GPIO_CLK RCC_AHB1Periph_GPIOE -#define LIS302DL_SPI_INT2_EXTI_LINE EXTI_Line1 -#define LIS302DL_SPI_INT2_EXTI_PORT_SOURCE EXTI_PortSourceGPIOE -#define LIS302DL_SPI_INT2_EXTI_PIN_SOURCE EXTI_PinSource1 -#define LIS302DL_SPI_INT2_EXTI_IRQn EXTI1_IRQn - - -/******************************************************************************/ -/*************************** START REGISTER MAPPING **************************/ -/******************************************************************************/ - -/******************************************************************************* -* WHO_AM_I Register: Device Identification Register -* Read only register -* Default value: 0x3B -*******************************************************************************/ -#define LIS302DL_WHO_AM_I_ADDR 0x0F - -/******************************************************************************* -* CTRL_REG1 Register: Control Register 1 -* Read Write register -* Default value: 0x07 -* 7 DR: Data Rate selection. -* 0 - 100 Hz output data rate -* 1 - 400 Hz output data rate -* 6 PD: Power Down control. -* 0 - power down mode -* 1 - active mode -* 5 FS: Full Scale selection. -* 0 - Typical measurement range 2.3 -* 1 - Typical measurement range 9.2 -* 4:3 STP-STM Self Test Enable: -* STP | STM | mode -* ---------------------------- -* 0 | 0 | Normal mode -* 0 | 1 | Self Test M -* 1 | 0 | Self Test P -* 2 Zen: Z axis enable. -* 0 - Z axis disabled -* 1- Z axis enabled -* 1 Yen: Y axis enable. -* 0 - Y axis disabled -* 1- Y axis enabled -* 0 Xen: X axis enable. -* 0 - X axis disabled -* 1- X axis enabled -********************************************************************************/ -#define LIS302DL_CTRL_REG1_ADDR 0x20 - -/******************************************************************************* -* CTRL_REG2 Regsiter: Control Register 2 -* Read Write register -* Default value: 0x00 -* 7 SIM: SPI Serial Interface Mode Selection. -* 0 - 4 wire interface -* 1 - 3 wire interface -* 6 BOOT: Reboot memory content -* 0 - normal mode -* 1 - reboot memory content -* 5 Reserved -* 4 FDS: Filtered data selection. -* 0 - internal filter bypassed -* 1 - data from internal filter sent to output register -* 3 HP FF_WU2: High pass filter enabled for FreeFall/WakeUp#2. -* 0 - filter bypassed -* 1 - filter enabled -* 2 HP FF_WU1: High pass filter enabled for FreeFall/WakeUp#1. -* 0 - filter bypassed -* 1 - filter enabled -* 1:0 HP coeff2-HP coeff1 High pass filter cut-off frequency (ft) configuration. -* ft= ODR[hz]/6*HP coeff -* HP coeff2 | HP coeff1 | HP coeff -* ------------------------------------------- -* 0 | 0 | 8 -* 0 | 1 | 16 -* 1 | 0 | 32 -* 1 | 1 | 64 -* HP coeff | ft[hz] | ft[hz] | -* |ODR 100Hz | ODR 400Hz | -* -------------------------------------------- -* 00 | 2 | 8 | -* 01 | 1 | 4 | -* 10 | 0.5 | 2 | -* 11 | 0.25 | 1 | -*******************************************************************************/ -#define LIS302DL_CTRL_REG2_ADDR 0x21 - -/******************************************************************************* -* CTRL_REG3 Register: Interrupt Control Register -* Read Write register -* Default value: 0x00 -* 7 IHL active: Interrupt active high/low. -* 0 - active high -* 1 - active low -* 6 PP_OD: push-pull/open-drain. -* 0 - push-pull -* 1 - open-drain -* 5:3 I2_CFG2 - I2_CFG0 Data signal on INT2 pad control bits -* 2:0 I1_CFG2 - I1_CFG0 Data signal on INT1 pad control bits -* I1(2)_CFG2 | I1(2)_CFG1 | I1(2)_CFG0 | INT1(2) Pad -* ---------------------------------------------------------- -* 0 | 0 | 0 | GND -* 0 | 0 | 1 | FreeFall/WakeUp#1 -* 0 | 1 | 0 | FreeFall/WakeUp#2 -* 0 | 1 | 1 | FreeFall/WakeUp#1 or FreeFall/WakeUp#2 -* 1 | 0 | 0 | Data ready -* 1 | 1 | 1 | Click interrupt -*******************************************************************************/ -#define LIS302DL_CTRL_REG3_ADDR 0x22 - -/******************************************************************************* -* HP_FILTER_RESET Register: Dummy register. Reading at this address zeroes -* instantaneously the content of the internal high pass filter. If the high pass -* filter is enabled all three axes are instantaneously set to 0g. -* This allows to overcome the settling time of the high pass filter. -* Read only register -* Default value: Dummy -*******************************************************************************/ -#define LIS302DL_HP_FILTER_RESET_REG_ADDR 0x23 - -/******************************************************************************* -* STATUS_REG Register: Status Register -* Default value: 0x00 -* 7 ZYXOR: X, Y and Z axis data overrun. -* 0: no overrun has occurred -* 1: new data has overwritten the previous one before it was read -* 6 ZOR: Z axis data overrun. -* 0: no overrun has occurred -* 1: new data for Z-axis has overwritten the previous one before it was read -* 5 yOR: y axis data overrun. -* 0: no overrun has occurred -* 1: new data for y-axis has overwritten the previous one before it was read -* 4 XOR: X axis data overrun. -* 0: no overrun has occurred -* 1: new data for X-axis has overwritten the previous one before it was read -* 3 ZYXDA: X, Y and Z axis new data available -* 0: a new set of data is not yet available -* 1: a new set of data is available -* 2 ZDA: Z axis new data available. -* 0: a new set of data is not yet available -* 1: a new data for Z axis is available -* 1 YDA: Y axis new data available -* 0: a new set of data is not yet available -* 1: a new data for Y axis is available -* 0 XDA: X axis new data available -* 0: a new set of data is not yet available -* 1: a new data for X axis is available -*******************************************************************************/ -#define LIS302DL_STATUS_REG_ADDR 0x27 - -/******************************************************************************* -* OUT_X Register: X-axis output Data -* Read only register -* Default value: output -* 7:0 XD7-XD0: X-axis output Data -*******************************************************************************/ -#define LIS302DL_OUT_X_ADDR 0x29 - -/******************************************************************************* -* OUT_Y Register: Y-axis output Data -* Read only register -* Default value: output -* 7:0 YD7-YD0: Y-axis output Data -*******************************************************************************/ -#define LIS302DL_OUT_Y_ADDR 0x2B - -/******************************************************************************* -* OUT_Z Register: Z-axis output Data -* Read only register -* Default value: output -* 7:0 ZD7-ZD0: Z-axis output Data -*******************************************************************************/ -#define LIS302DL_OUT_Z_ADDR 0x2D - -/******************************************************************************* -* FF_WW_CFG_1 Register: Configuration register for Interrupt 1 source. -* Read write register -* Default value: 0x00 -* 7 AOI: AND/OR combination of Interrupt events. -* 0: OR combination of interrupt events -* 1: AND combination of interrupt events -* 6 LIR: Latch/not latch interrupt request -* 0: interrupt request not latched -* 1: interrupt request latched -* 5 ZHIE: Enable interrupt generation on Z high event. -* 0: disable interrupt request -* 1: enable interrupt request on measured accel. value higher than preset threshold -* 4 ZLIE: Enable interrupt generation on Z low event. -* 0: disable interrupt request -* 1: enable interrupt request on measured accel. value lower than preset threshold -* 3 YHIE: Enable interrupt generation on Y high event. -* 0: disable interrupt request -* 1: enable interrupt request on measured accel. value higher than preset threshold -* 2 YLIE: Enable interrupt generation on Y low event. -* 0: disable interrupt request -* 1: enable interrupt request on measured accel. value lower than preset threshold -* 1 XHIE: Enable interrupt generation on X high event. -* 0: disable interrupt request -* 1: enable interrupt request on measured accel. value higher than preset threshold -* 0 XLIE: Enable interrupt generation on X low event. -* 0: disable interrupt request -* 1: enable interrupt request on measured accel. value lower than preset threshold -*******************************************************************************/ -#define LIS302DL_FF_WU_CFG1_REG_ADDR 0x30 - -/******************************************************************************* -* FF_WU_SRC_1 Register: Interrupt 1 source register. -* Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt -* and allow the refreshment of data in the FF_WU_SRC_1 register if the latched option -* was chosen. -* Read only register -* Default value: 0x00 -* 7 Reserved -* 6 IA: Interrupt active. -* 0: no interrupt has been generated -* 1: one or more interrupts have been generated -* 5 ZH: Z high. -* 0: no interrupt -* 1: ZH event has occurred -* 4 ZL: Z low. -* 0: no interrupt -* 1: ZL event has occurred -* 3 YH: Y high. -* 0: no interrupt -* 1: YH event has occurred -* 2 YL: Y low. -* 0: no interrupt -* 1: YL event has occurred -* 1 YH: X high. -* 0: no interrupt -* 1: XH event has occurred -* 0 YL: X low. -* 0: no interrupt -* 1: XL event has occurred -*******************************************************************************/ -#define LIS302DL_FF_WU_SRC1_REG_ADDR 0x31 - -/******************************************************************************* -* FF_WU_THS_1 Register: Threshold register -* Read Write register -* Default value: 0x00 -* 7 DCRM: Reset mode selection. -* 0 - counter resetted -* 1 - counter decremented -* 6 THS6-THS0: Free-fall/wake-up threshold value. -*******************************************************************************/ -#define LIS302DL_FF_WU_THS1_REG_ADDR 0x32 - -/******************************************************************************* -* FF_WU_DURATION_1 Register: duration Register -* Read Write register -* Default value: 0x00 -* 7:0 D7-D0 Duration value. (Duration steps and maximum values depend on the ODR chosen) - ******************************************************************************/ -#define LIS302DL_FF_WU_DURATION1_REG_ADDR 0x33 - -/******************************************************************************* -* FF_WW_CFG_2 Register: Configuration register for Interrupt 2 source. -* Read write register -* Default value: 0x00 -* 7 AOI: AND/OR combination of Interrupt events. -* 0: OR combination of interrupt events -* 1: AND combination of interrupt events -* 6 LIR: Latch/not latch interrupt request -* 0: interrupt request not latched -* 1: interrupt request latched -* 5 ZHIE: Enable interrupt generation on Z high event. -* 0: disable interrupt request -* 1: enable interrupt request on measured accel. value higher than preset threshold -* 4 ZLIE: Enable interrupt generation on Z low event. -* 0: disable interrupt request -* 1: enable interrupt request on measured accel. value lower than preset threshold -* 3 YHIE: Enable interrupt generation on Y high event. -* 0: disable interrupt request -* 1: enable interrupt request on measured accel. value higher than preset threshold -* 2 YLIE: Enable interrupt generation on Y low event. -* 0: disable interrupt request -* 1: enable interrupt request on measured accel. value lower than preset threshold -* 1 XHIE: Enable interrupt generation on X high event. -* 0: disable interrupt request -* 1: enable interrupt request on measured accel. value higher than preset threshold -* 0 XLIE: Enable interrupt generation on X low event. -* 0: disable interrupt request -* 1: enable interrupt request on measured accel. value lower than preset threshold -*******************************************************************************/ -#define LIS302DL_FF_WU_CFG2_REG_ADDR 0x34 - -/******************************************************************************* -* FF_WU_SRC_2 Register: Interrupt 2 source register. -* Reading at this address clears FF_WU_SRC_2 register and the FF, WU 2 interrupt -* and allow the refreshment of data in the FF_WU_SRC_2 register if the latched option -* was chosen. -* Read only register -* Default value: 0x00 -* 7 Reserved -* 6 IA: Interrupt active. -* 0: no interrupt has been generated -* 1: one or more interrupts have been generated -* 5 ZH: Z high. -* 0: no interrupt -* 1: ZH event has occurred -* 4 ZL: Z low. -* 0: no interrupt -* 1: ZL event has occurred -* 3 YH: Y high. -* 0: no interrupt -* 1: YH event has occurred -* 2 YL: Y low. -* 0: no interrupt -* 1: YL event has occurred -* 1 YH: X high. -* 0: no interrupt -* 1: XH event has occurred -* 0 YL: X low. -* 0: no interrupt -* 1: XL event has occurred -*******************************************************************************/ -#define LIS302DL_FF_WU_SRC2_REG_ADDR 0x35 - -/******************************************************************************* -* FF_WU_THS_2 Register: Threshold register -* Read Write register -* Default value: 0x00 -* 7 DCRM: Reset mode selection. -* 0 - counter resetted -* 1 - counter decremented -* 6 THS6-THS0: Free-fall/wake-up threshold value. -*******************************************************************************/ -#define LIS302DL_FF_WU_THS2_REG_ADDR 0x36 - -/******************************************************************************* -* FF_WU_DURATION_2 Register: duration Register -* Read Write register -* Default value: 0x00 -* 7:0 D7-D0 Duration value. (Duration steps and maximum values depend on the ODR chosen) - ******************************************************************************/ -#define LIS302DL_FF_WU_DURATION2_REG_ADDR 0x37 - -/****************************************************************************** -* CLICK_CFG Register: click Register -* Read Write register -* Default value: 0x00 -* 7 Reserved -* 6 LIR: Latch Interrupt request. -* 0: interrupt request not latched -* 1: interrupt request latched -* 5 Double_Z: Enable interrupt generation on double click event on Z axis. -* 0: disable interrupt request -* 1: enable interrupt request -* 4 Single_Z: Enable interrupt generation on single click event on Z axis. -* 0: disable interrupt request -* 1: enable interrupt request -* 3 Double_Y: Enable interrupt generation on double click event on Y axis. -* 0: disable interrupt request -* 1: enable interrupt request -* 2 Single_Y: Enable interrupt generation on single click event on Y axis. -* 0: disable interrupt request -* 1: enable interrupt request -* 1 Double_X: Enable interrupt generation on double click event on X axis. -* 0: disable interrupt request -* 1: enable interrupt request -* 0 Single_y: Enable interrupt generation on single click event on X axis. -* 0: disable interrupt request -* 1: enable interrupt request - ******************************************************************************/ -#define LIS302DL_CLICK_CFG_REG_ADDR 0x38 - -/****************************************************************************** -* CLICK_SRC Register: click status Register -* Read only register -* Default value: 0x00 -* 7 Reserved -* 6 IA: Interrupt active. -* 0: no interrupt has been generated -* 1: one or more interrupts have been generated -* 5 Double_Z: Double click on Z axis event. -* 0: no interrupt -* 1: Double Z event has occurred -* 4 Single_Z: Z low. -* 0: no interrupt -* 1: Single Z event has occurred -* 3 Double_Y: Y high. -* 0: no interrupt -* 1: Double Y event has occurred -* 2 Single_Y: Y low. -* 0: no interrupt -* 1: Single Y event has occurred -* 1 Double_X: X high. -* 0: no interrupt -* 1: Double X event has occurred -* 0 Single_X: X low. -* 0: no interrupt -* 1: Single X event has occurred -*******************************************************************************/ -#define LIS302DL_CLICK_SRC_REG_ADDR 0x39 - -/******************************************************************************* -* CLICK_THSY_X Register: Click threshold Y and X register -* Read Write register -* Default value: 0x00 -* 7:4 THSy3-THSy0: Click threshold on Y axis, step 0.5g -* 3:0 THSx3-THSx0: Click threshold on X axis, step 0.5g -*******************************************************************************/ -#define LIS302DL_CLICK_THSY_X_REG_ADDR 0x3B - -/******************************************************************************* -* CLICK_THSZ Register: Click threshold Z register -* Read Write register -* Default value: 0x00 -* 7:4 Reserved -* 3:0 THSz3-THSz0: Click threshold on Z axis, step 0.5g -*******************************************************************************/ -#define LIS302DL_CLICK_THSZ_REG_ADDR 0x3C - -/******************************************************************************* -* CLICK_TimeLimit Register: Time Limit register -* Read Write register -* Default value: 0x00 -* 7:0 Dur7-Dur0: Time Limit value, step 0.5g -*******************************************************************************/ -#define LIS302DL_CLICK_TIMELIMIT_REG_ADDR 0x3D - -/******************************************************************************* -* CLICK_Latency Register: Latency register -* Read Write register -* Default value: 0x00 -* 7:0 Lat7-Lat0: Latency value, step 1msec -*******************************************************************************/ -#define LIS302DL_CLICK_LATENCY_REG_ADDR 0x3E - -/******************************************************************************* -* CLICK_Window Register: Window register -* Read Write register -* Default value: 0x00 -* 7:0 Win7-Win0: Window value, step 1msec -*******************************************************************************/ -#define LIS302DL_CLICK_WINDOW_REG_ADDR 0x3F - -/******************************************************************************/ -/**************************** END REGISTER MAPPING ***************************/ -/******************************************************************************/ - -#define LIS302DL_SENSITIVITY_2_3G 18 /* 18 mg/digit*/ -#define LIS302DL_SENSITIVITY_9_2G 72 /* 72 mg/digit*/ - -/** @defgroup Data_Rate_selection - * @{ - */ -#define LIS302DL_DATARATE_100 ((uint8_t)0x00) -#define LIS302DL_DATARATE_400 ((uint8_t)0x80) -/** - * @} - */ - -/** @defgroup Power_Mode_selection - * @{ - */ -#define LIS302DL_LOWPOWERMODE_POWERDOWN ((uint8_t)0x00) -#define LIS302DL_LOWPOWERMODE_ACTIVE ((uint8_t)0x40) -/** - * @} - */ - -/** @defgroup Full_Scale_selection - * @{ - */ -#define LIS302DL_FULLSCALE_2_3 ((uint8_t)0x00) -#define LIS302DL_FULLSCALE_9_2 ((uint8_t)0x20) -/** - * @} - */ - -/** @defgroup Self_Test_selection - * @{ - */ -#define LIS302DL_SELFTEST_NORMAL ((uint8_t)0x00) -#define LIS302DL_SELFTEST_P ((uint8_t)0x10) -#define LIS302DL_SELFTEST_M ((uint8_t)0x08) -/** - * @} - */ - -/** @defgroup Direction_XYZ_selection - * @{ - */ -#define LIS302DL_X_ENABLE ((uint8_t)0x01) -#define LIS302DL_Y_ENABLE ((uint8_t)0x02) -#define LIS302DL_Z_ENABLE ((uint8_t)0x04) -#define LIS302DL_XYZ_ENABLE ((uint8_t)0x07) -/** - * @} - */ - - /** @defgroup SPI_Serial_Interface_Mode_selection - * @{ - */ -#define LIS302DL_SERIALINTERFACE_4WIRE ((uint8_t)0x00) -#define LIS302DL_SERIALINTERFACE_3WIRE ((uint8_t)0x80) -/** - * @} - */ - - /** @defgroup Boot_Mode_selection - * @{ - */ -#define LIS302DL_BOOT_NORMALMODE ((uint8_t)0x00) -#define LIS302DL_BOOT_REBOOTMEMORY ((uint8_t)0x40) -/** - * @} - */ - - /** @defgroup Filtered_Data_Selection_Mode_selection - * @{ - */ -#define LIS302DL_FILTEREDDATASELECTION_BYPASSED ((uint8_t)0x00) -#define LIS302DL_FILTEREDDATASELECTION_OUTPUTREGISTER ((uint8_t)0x20) -/** - * @} - */ - - /** @defgroup High_Pass_Filter_Interrupt_selection - * @{ - */ -#define LIS302DL_HIGHPASSFILTERINTERRUPT_OFF ((uint8_t)0x00) -#define LIS302DL_HIGHPASSFILTERINTERRUPT_1 ((uint8_t)0x04) -#define LIS302DL_HIGHPASSFILTERINTERRUPT_2 ((uint8_t)0x08) -#define LIS302DL_HIGHPASSFILTERINTERRUPT_1_2 ((uint8_t)0x0C) -/** - * @} - */ - - /** @defgroup High_Pass_Filter_selection - * @{ - */ -#define LIS302DL_HIGHPASSFILTER_LEVEL_0 ((uint8_t)0x00) -#define LIS302DL_HIGHPASSFILTER_LEVEL_1 ((uint8_t)0x01) -#define LIS302DL_HIGHPASSFILTER_LEVEL_2 ((uint8_t)0x02) -#define LIS302DL_HIGHPASSFILTER_LEVEL_3 ((uint8_t)0x03) -/** - * @} - */ - - -/** @defgroup latch_Interrupt_Request_selection - * @{ - */ -#define LIS302DL_INTERRUPTREQUEST_NOTLATCHED ((uint8_t)0x00) -#define LIS302DL_INTERRUPTREQUEST_LATCHED ((uint8_t)0x40) -/** - * @} - */ - -/** @defgroup Click_Interrupt_XYZ_selection - * @{ - */ -#define LIS302DL_CLICKINTERRUPT_XYZ_DISABLE ((uint8_t)0x00) -#define LIS302DL_CLICKINTERRUPT_X_ENABLE ((uint8_t)0x01) -#define LIS302DL_CLICKINTERRUPT_Y_ENABLE ((uint8_t)0x04) -#define LIS302DL_CLICKINTERRUPT_Z_ENABLE ((uint8_t)0x10) -#define LIS302DL_CLICKINTERRUPT_XYZ_ENABLE ((uint8_t)0x15) -/** - * @} - */ - -/** @defgroup Double_Click_Interrupt_XYZ_selection - * @{ - */ -#define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_DISABLE ((uint8_t)0x00) -#define LIS302DL_DOUBLECLICKINTERRUPT_X_ENABLE ((uint8_t)0x02) -#define LIS302DL_DOUBLECLICKINTERRUPT_Y_ENABLE ((uint8_t)0x08) -#define LIS302DL_DOUBLECLICKINTERRUPT_Z_ENABLE ((uint8_t)0x20) -#define LIS302DL_DOUBLECLICKINTERRUPT_XYZ_ENABLE ((uint8_t)0x2A) -/** - * @} - */ -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Macros - * @{ - */ -#define LIS302DL_CS_LOW() GPIO_ResetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN) -#define LIS302DL_CS_HIGH() GPIO_SetBits(LIS302DL_SPI_CS_GPIO_PORT, LIS302DL_SPI_CS_PIN) -/** - * @} - */ - -/** @defgroup STM32F4_DISCOVERY_LIS302DL_Exported_Functions - * @{ - */ -void LIS302DL_Init(LIS302DL_InitTypeDef *LIS302DL_InitStruct); -void LIS302DL_InterruptConfig(LIS302DL_InterruptConfigTypeDef *LIS302DL_InterruptConfigStruct); -void LIS302DL_FilterConfig(LIS302DL_FilterConfigTypeDef *LIS302DL_FilterConfigStruct); -void LIS302DL_LowpowerCmd(uint8_t LowPowerMode); -void LIS302DL_FullScaleCmd(uint8_t FS_value); -void LIS302DL_DataRateCmd(uint8_t DataRateValue); -void LIS302DL_RebootCmd(void); -void LIS302DL_ReadACC(int32_t* out); -void LIS302DL_Write(uint8_t* pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite); -void LIS302DL_Read(uint8_t* pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead); - -/* USER Callbacks: This is function for which prototype only is declared in - MEMS accelerometre driver and that should be implemented into user applicaiton. */ -/* LIS302DL_TIMEOUT_UserCallback() function is called whenever a timeout condition - occure during communication (waiting transmit data register empty flag(TXE) - or waiting receive data register is not empty flag (RXNE)). - You can use the default timeout callback implementation by uncommenting the - define USE_DEFAULT_TIMEOUT_CALLBACK in stm32f4_discovery_lis302dl.h file. - Typically the user implementation of this callback should reset MEMS peripheral - and re-initialize communication or in worst case reset all the application. */ -uint32_t LIS302DL_TIMEOUT_UserCallback(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4_DISCOVERY_LIS302DL_H */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ From b48db26a32f43c9ad7755136cef88a8613ef38fd Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Wed, 20 Jun 2012 19:16:40 +0000 Subject: [PATCH 0171/1435] Update primary README with current documentation --- README | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/README b/README index d99337c2a..cd4fc5af5 100644 --- a/README +++ b/README @@ -35,8 +35,20 @@ IF YOU HAVE AN STLINKv2 You're ready to go :) -To run the gdb server, do (you do not need sudo if you have set up -permissions correctly): +COMPILING +~~~~~~~~~ +This project was converted to Autotools by a well meaning individual. The +following steps will build the project for you. + +$ ./autogen.sh +$ ./configure +$ make + +USING THE GDBSERVER +~~~~~~~~~~~~~~~~~~~ +To run the gdb server: (you do not need sudo if you have set up +permissions correctly) + $ make && [sudo] ./st-util There are a few options: @@ -52,8 +64,21 @@ There are a few options: -p 4242, --listen_port=1234 Set the gdb server listen port. (default port: 4242) -Then, in gdb: (remember, you need to run an _ARM_ gdb, not an x86 gdb) -(gdb) target remote :4242 +Then, in your project directory, someting like this... +(remember, you need to run an _ARM_ gdb, not an x86 gdb) + +$ arm-none-eabi-gdb fancyblink.elf +... +(gdb) tar extended-remote :4242 +... +(gdb) load +Loading section .text, size 0x458 lma 0x8000000 +Loading section .data, size 0x8 lma 0x8000458 +Start address 0x80001c1, load size 1120 +Transfer rate: 1 KB/sec, 560 bytes/write. +(gdb) +... +(gdb) continue Have fun! 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zh)Ey>Cj0N_Uo<`*@Lx121Oe^-Z$89q9?)Mj9sxeYw(@`S@qmE{J~*@-fQK-Ghxadq zywE=lLkI`+|0M_r0weap|5NyH7yhL2g8BY%ln0>|C_uvl`(rW$j0pd~X$W!rynlHG zLLk!rCm#7@6yb#_$_z?1dkpGP)?4Pjn@Ib&I#8&;k6(eY%zdZr*LH;n1hld{u zMtJg{bNTuIOd~=b1pG%7fIt|Z0OT*l0$_o^ln8+M|L_E%SOENIWPm_k-aq955zilr zd3X?Nf2Zkp{QsxW5H$<^E7U++w@_Y0s13N zVTdCvYR=Ax*DE6Dzu(XbPFBt|5X6Lk2GTV8!o0Eq0#Ipw35bk@G)RVrPga1RUlsxq u-~mfR`S_)HL}~v2EQU0qqS)>prfwcSZkATq2m?SMAT}eT42rTW_WuC_EK7|5 diff --git a/doc/tutorial/tutorial.tex b/doc/tutorial/tutorial.tex index 2045d77da..5860ca888 100644 --- a/doc/tutorial/tutorial.tex +++ b/doc/tutorial/tutorial.tex @@ -61,6 +61,7 @@ \section{Installing STLINK} \begin{itemize} \item libusb-1.0 \item pkg-config +\item autotools \end{itemize} \paragraph{} @@ -79,30 +80,27 @@ \section{Installing STLINK} \begin{small} \begin{lstlisting}[frame=tb] $> cd stlink.git -$> make +$> ./autogen.sh +$> ./configure +$> make \end{lstlisting} \end{small} It includes: \begin{itemize} \item a communication library (stlink.git/libstlink.a), -\item a GDB server (stlink.git/gdbserver/st-util), -\item a flash manipulation tool (stlink.git/flash/flash). +\item a GDB server (stlink.git/st-util), +\item a flash manipulation tool (stlink.git/st-flash). \end{itemize} \newpage -\section{Building and running a program in SRAM} +\section{Using the GDB server} \paragraph{} -A simple LED blinking example is provided in the example directory. It is built using:\\ -\begin{small} -\begin{lstlisting}[frame=tb] -cd stlink.git/example/blink ; -PATH=$TOOLCHAIN_PATH/bin:$PATH make -\end{lstlisting} -\end{small} -This builds three files, one for each of the Discovery boards currently -available, linked to run from SRAM. (So no risk of overwriting anything you didn't mean to) -These blink examples can safely be used to verify that: +This assumes you have got the libopencm3 project downloaded in [ocm3]. The +libopencm3 project has some good, reliable examples for each of the Discovery boards. + +Even if you don't plan on using libopencm3, the examples they provide will help you +verify that: \begin{itemize} \item Your installed toolchain is capable of compiling for cortex M3/M4 targets @@ -131,7 +129,7 @@ \section{Building and running a program in SRAM} Then, GDB can be used to interact with the kit:\\ \begin{small} \begin{lstlisting}[frame=tb] -$> $TOOLCHAIN_PATH/bin/arm-none-eabi-gdb +$> $TOOLCHAIN_PATH/bin/arm-none-eabi-gdb example_file.elf \end{lstlisting} \end{small} @@ -139,99 +137,73 @@ \section{Building and running a program in SRAM} From GDB, connect to the server using:\\ \begin{small} \begin{lstlisting}[frame=tb] -$> target extended localhost:4242 +(gdb) target extended localhost:4242 \end{lstlisting} \end{small} \paragraph{} -By default, the program was linked such that the base address is 0x20000000. From the architecture -memory map, GDB knows this address belongs to SRAM. To load the program in SRAM, simply use:\\ +GDB has memory maps for as many chips as it knows about, and will load your project +into either flash or SRAM based on how the project was linked. Linking projects +to boot from SRAM is beyond the scope of this document. + +Because of these built in memory maps, after specifying the .elf at the command line, now +we can simply "load" the target:\\ \begin{small} \begin{lstlisting}[frame=tb] -$> # Choose one as appropriate for your Discovery kit -$> load blink_32L.elf | load blink_32VL.elf | load blink_F4.elf +(gdb) load \end{lstlisting} \end{small} \paragraph{} -GDB automatically set the PC register to the correct value, 0x20000000 in this case. Then, you -can run the program using:\\ +st-util will load all sections into their appropriate addresses, and "correctly" set the PC +register. So, to run your freshly loaded program, simply "continue"\\ \begin{small} \begin{lstlisting}[frame=tb] -$> continue +(gdb) continue \end{lstlisting} \end{small} \paragraph{} -All the LEDs on the board should now be blinking in time (those leds are near the user and reset buttons). +Your program should now be running, and, if you used one of the blinking examples from +libopencm3, the LEDs on the board should be blinking for you. \newpage \section{Building and flashing a program} \paragraph{} -FLASH memory reading and writing is done by a separate tool, as shown below:\\ +If you want to simply flash binary files to arbitrary sections of memory, or +read arbitary addresses of memory out to a binary file, use the st-flash tool, +as shown below:\\ \begin{small} \begin{lstlisting}[frame=tb] -# change to the flash tool directory -$> cd stlink.git/flash ; # stlinkv1 command to read 4096 from flash into out.bin -$> ./flash read v1 out.bin 0x8000000 4096 +$> ./st-flash read v1 out.bin 0x8000000 4096 # stlinkv2 command -$> ./flash read out.bin 0x8000000 4096 +$> ./st-flash read out.bin 0x8000000 4096 # stlinkv1 command to write the file in.bin into flash -$> ./flash write v1 in.bin 0x8000000 +$> ./st-flash write v1 in.bin 0x8000000 # stlinkv2 command -$> ./flash write in.bin 0x8000000 +$> ./st-flash write in.bin 0x8000000 \end{lstlisting} \end{small} \paragraph{} -A LED blinking example is provided:\\ +Of course, you can use this instead of the gdb server, if you prefer. Just remember +to use the ".bin" image, rather than the .elf file.\\ \begin{small} \begin{lstlisting}[frame=tb] -# build the example, resulting in blink.bin -$> cd stlink.git/example/blink_flash -$> PATH=$TOOLCHAIN_PATH:$PATH make CONFIG_STM32L_DISCOVERY=1 # write blink.bin into FLASH -$> sudo ./flash write blink.bin 0x08000000 +$> [sudo] ./st-flash write fancy_blink.bin 0x08000000 \end{lstlisting} \end{small} \paragraph{} Upon reset, the board LEDs should be blinking. -\newpage -\section{Building and installing the CHIBIOS kernel} -\paragraph{} -CHIBIOS is an open source RTOS. More information can be found on the project website: -\begin{center} -http://www.chibios.org/dokuwiki/doku.php -\end{center} - -\paragraph{} -It supports several boards, including the STM32L DISCOVERY kit: -\begin{center} -http://www.chibios.org/dokuwiki/doku.php?id=chibios:articles:stm32l\_discovery -\end{center} - -\paragraph{} -The installation procedure is detailed below:\\ -\begin{small} -\begin{lstlisting}[frame=tb] -# checkout and build CHIBIOS for STM32L DISCOVERY kits -svn checkout https://chibios.svn.sourceforge.net/svnroot/chibios/trunk -cd chibios/trunk/demos/ARMCM3-STM32L152-DISCOVERY -PATH=$TOOLCHAIN_PATH:$PATH make - -# flash the image into STM32L -sudo ./flash write build/ch.bin 0x08000000 -\end{lstlisting} -\end{small} - \newpage \section{Notes} @@ -242,36 +214,7 @@ \subsection{Disassembling THUMB code in GDB} if you want to disassemble the code at 0x20000000, use:\\ \begin{small} \begin{lstlisting}[frame=tb] -$> disassemble 0x20000001 -\end{lstlisting} -\end{small} - - -\subsection{libstm32l\_discovery} -\paragraph{} -The repository includes the STM32L discovery library source code from ST original firmware packages, -available here:\\ -\begin{small} -\begin{lstlisting}[frame=tb] -http://www.st.com/internet/evalboard/product/250990.jsp#FIRMWARE -\end{lstlisting} -\end{small} - -\paragraph{} -It is built using:\\ -\begin{small} -\begin{lstlisting}[frame=tb] -$> cd stlink.git/example/libstm32l_discovery/build -$> make -\end{lstlisting} -\end{small} - -\paragraph{} -An example using the library can be built using:\\ -\begin{small} -\begin{lstlisting}[frame=tb] -$> cd stlink.git/example/lcd -$> make +(gdb) disassemble 0x20000001 \end{lstlisting} \end{small} @@ -283,6 +226,9 @@ \section{References} documentation related to the STM32L mcu \item http://www.st.com/internet/evalboard/product/250990.jsp\\ documentation related to the STM32L discovery kit +\item http://www.libopencm3.org\\ + libopencm3, a project providing a firmware library, with solid examples for Cortex + M3, M4 and M0 processors from any vendor. \end{itemize} \end{document} From 406ac425028bd0ea5f01555521ef05eee84b0825 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Thu, 3 May 2012 22:05:32 +0000 Subject: [PATCH 0173/1435] Display proper final page write count for 32L --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 08bd0bb4d..a4e2a5370 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1323,7 +1323,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uns if (sl->verbose >= 1) { /* show progress. writing procedure is slow and previous errors are misleading */ - fprintf(stdout, "\r%3u/%u halfpages written", count, num_half_pages); + fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); fflush(stdout); } while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { From 5b6eb51bd22c44fa8d9e70519b561dc64c37f6c9 Mon Sep 17 00:00:00 2001 From: Michael Sparmann Date: Tue, 3 Jul 2012 15:10:07 +0200 Subject: [PATCH 0174/1435] Fix "monitor reset" gdb command being misinterpreted as "monitor resume" by checking for the full word, not just the first two chars. --- gdbserver/gdb-server.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 7a525d535..f60aadcf4 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -163,7 +163,7 @@ int main(int argc, char** argv) { if(sl == NULL) return 1; break; } - + printf("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); sl->verbose=0; @@ -249,7 +249,7 @@ char* make_memory_map(stlink_t *sl) { } -/* +/* * DWT_COMP0 0xE0001020 * DWT_MASK0 0xE0001024 * DWT_FUNCTION0 0xE0001028 @@ -282,7 +282,7 @@ static void init_data_watchpoints(stlink_t *sl) { #endif // set trcena in debug command to turn on dwt unit - stlink_write_debug32(sl, 0xE000EDFC, + stlink_write_debug32(sl, 0xE000EDFC, stlink_read_debug32(sl, 0xE000EDFC) | (1<<24)); // make sure all watchpoints are cleared @@ -695,31 +695,31 @@ int serve(stlink_t *sl, int port) { } else { params = separator + 1; } - - if (!strncmp(params,"7265",4)) {// resume + + if (!strncmp(params,"726573756d65",12)) {// resume #ifdef DEBUG printf("Rcmd: resume\n"); #endif stlink_run(sl); reply = strdup("OK"); - } else if (!strncmp(params,"6861",4)) { //half + } else if (!strncmp(params,"68616c74",8)) { //halt reply = strdup("OK"); - + stlink_force_debug(sl); #ifdef DEBUG printf("Rcmd: halt\n"); #endif - } else if (!strncmp(params,"7265",4)) { //reset + } else if (!strncmp(params,"7265736574",10)) { //reset reply = strdup("OK"); - + stlink_force_debug(sl); stlink_reset(sl); init_code_breakpoints(sl); init_data_watchpoints(sl); - + #ifdef DEBUG printf("Rcmd: reset\n"); #endif @@ -729,7 +729,7 @@ int serve(stlink_t *sl, int port) { #endif } - + } if(reply == NULL) From e8601c816ae61ae0a5fa2a5c176c75e5dc523ac1 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Sun, 8 Jul 2012 15:49:36 -0400 Subject: [PATCH 0175/1435] Updated .gitignore to include test binaries --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index cf2f1a448..6ed8efce9 100644 --- a/.gitignore +++ b/.gitignore @@ -20,6 +20,8 @@ config.status compile st-flash st-util +test_usb +test_sg *.deps* *.dirstamp *.a From a71f48db1055dd7cbd73260e089a63e86afaebb8 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Sun, 8 Jul 2012 21:04:30 -0400 Subject: [PATCH 0176/1435] Read Cortex M4F floating point registers Since the ST-LINK does not seem to support reading these registers, I have implemented functions that will manually request these registers and add them to the reg struct. As of now, these functions are just backend and are not integrated into anything, however I have verified that they work with the STM32F407 DISCOVERY board. --- src/stlink-common.c | 17 +++++++++++++++++ src/stlink-common.h | 6 ++++++ src/stlink-usb.c | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 57 insertions(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index a4e2a5370..359d39adc 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -577,6 +577,11 @@ void stlink_read_all_regs(stlink_t *sl, reg *regp) { sl->backend->read_all_regs(sl, regp); } +void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp) { + DLOG("*** stlink_read_all_unsupported_regs ***\n"); + sl->backend->read_all_unsupported_regs(sl, regp); +} + void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { DLOG("*** stlink_write_reg\n"); sl->backend->write_reg(sl, reg, idx); @@ -594,6 +599,18 @@ void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) { sl->backend->read_reg(sl, r_idx, regp); } +void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { + DLOG("*** stlink_read_unsupported_reg\n"); + DLOG(" (%d) ***\n", r_idx); + + if (r_idx != 0x21 || r_idx < 0x40 || r_idx > 0x5f) { + fprintf(stderr, "Error: register address must be in [0x21, 0x40..0x5f]\n"); + return; + } + + sl->backend->read_unsupported_reg(sl, r_idx, regp); +} + unsigned int is_core_halted(stlink_t *sl) { /* return non zero if core is halted */ stlink_status(sl); diff --git a/src/stlink-common.h b/src/stlink-common.h index ee59094b6..c982b3df6 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -238,11 +238,13 @@ extern "C" { typedef struct { uint32_t r[16]; + uint32_t s[32]; uint32_t xpsr; uint32_t main_sp; uint32_t process_sp; uint32_t rw; uint32_t rw2; + uint32_t fpscr; } reg; typedef uint32_t stm32_addr_t; @@ -295,6 +297,8 @@ extern "C" { void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); void (*read_all_regs) (stlink_t *sl, reg * regp); void (*read_reg) (stlink_t *sl, int r_idx, reg * regp); + void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp); + void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp); void (*write_reg) (stlink_t *sl, uint32_t reg, int idx); void (*step) (stlink_t * stl); int (*current_mode) (stlink_t * stl); @@ -360,7 +364,9 @@ extern "C" { void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); void stlink_read_all_regs(stlink_t *sl, reg *regp); + void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp); void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp); + void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp); void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); void stlink_step(stlink_t *sl); int stlink_current_mode(stlink_t *sl); diff --git a/src/stlink-usb.c b/src/stlink-usb.c index a25f7ec55..397723c25 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -576,6 +576,38 @@ void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { } } +void _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { + uint32_t r; + + sl->q_buf[0] = (unsigned char) r_idx; + for (int i = 1; i < 4; i++) { + sl->q_buf[i] = 0; + } + + _stlink_usb_write_mem32(sl, 0xE000EDF4, 4); + _stlink_usb_read_mem32(sl, 0xE000EDF8, 4); + + r = read_uint32(sl->q_buf, 0); + DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); + + switch (r_idx) { + case 0x21: + regp->fpscr = r; + break; + default: + regp->s[r_idx - 0x40] = r; + break; + } +} + +void _stlink_usb_read_all_unsupported_regs(stlink_t *sl, reg *regp) { + _stlink_usb_read_unsupported_reg(sl, 0x21, regp); + + for (int i = 0; i < 32; i++) { + _stlink_usb_read_unsupported_reg(sl, 0x40+i, regp); + } +} + void _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; @@ -616,6 +648,8 @@ stlink_backend_t _stlink_usb_backend = { _stlink_usb_write_mem8, _stlink_usb_read_all_regs, _stlink_usb_read_reg, + _stlink_usb_read_all_unsupported_regs, + _stlink_usb_read_unsupported_reg, _stlink_usb_write_reg, _stlink_usb_step, _stlink_usb_current_mode, From b1e65ea367a450e8a37584cdee334562149b2a7c Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Sun, 8 Jul 2012 23:04:35 -0400 Subject: [PATCH 0177/1435] Extra registers integration with GDB The support for extra registers has been added to GDB. Now all core registers can be read from GDB. Write support has not yet been added. --- gdbserver/gdb-server.c | 99 +++++++++++++++++++++++++++++++++++++++++- src/stlink-common.c | 15 +++++-- src/stlink-common.h | 4 ++ src/stlink-usb.c | 7 +++ 4 files changed, 121 insertions(+), 4 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index f60aadcf4..789b609e1 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -192,6 +192,71 @@ int main(int argc, char** argv) { return 0; } +static const char* const target_description_F4 = + "" + "" + "" + " arm" + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + " " + ""; + static const char* const memory_map_template_F4 = "" "chip_id==STM32_CHIPID_F4) { + reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); + } + else { + reply = strdup("PacketSize=3fff;qXfer:memory-map:read+"); + } } else if(!strcmp(queryName, "Xfer")) { char *type, *op, *__s_addr, *s_length; char *tok = params; @@ -674,6 +744,9 @@ int serve(stlink_t *sl, int port) { if(!strcmp(type, "memory-map") && !strcmp(op, "read")) data = current_memory_map; + if(!strcmp(type, "features") && !strcmp(op, "read")) + data = target_description_F4; + if(data) { unsigned data_length = strlen(data); if(addr + length > data_length) @@ -881,6 +954,30 @@ int serve(stlink_t *sl, int port) { } else if(id == 0x19) { stlink_read_reg(sl, 16, ®p); myreg = htonl(regp.xpsr); + } else if(id == 0x1A) { + stlink_read_reg(sl, 17, ®p); + myreg = htonl(regp.main_sp); + } else if(id == 0x1B) { + stlink_read_reg(sl, 18, ®p); + myreg = htonl(regp.process_sp); + } else if(id == 0x1C) { + stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.control); + } else if(id == 0x1D) { + stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.faultmask); + } else if(id == 0x1E) { + stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.basepri); + } else if(id == 0x1F) { + stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.primask); + } else if(id >= 0x20 && id < 0x40) { + stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.s[id-0x20]); + } else if(id == 0x40) { + stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.fpscr); } else { reply = strdup("E00"); } diff --git a/src/stlink-common.c b/src/stlink-common.c index 359d39adc..1e9c01114 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -600,15 +600,24 @@ void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) { } void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { + int r_convert; + DLOG("*** stlink_read_unsupported_reg\n"); DLOG(" (%d) ***\n", r_idx); - if (r_idx != 0x21 || r_idx < 0x40 || r_idx > 0x5f) { - fprintf(stderr, "Error: register address must be in [0x21, 0x40..0x5f]\n"); + /* Convert to values used by DCRSR */ + if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ + r_convert = 0x14; + } else if (r_idx == 0x40) { /* FPSCR */ + r_convert = 0x21; + } else if (r_idx >= 0x20 && r_idx < 0x40) { + r_convert = 0x40 + (r_idx - 0x20); + } else { + fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); return; } - sl->backend->read_unsupported_reg(sl, r_idx, regp); + sl->backend->read_unsupported_reg(sl, r_convert, regp); } unsigned int is_core_halted(stlink_t *sl) { diff --git a/src/stlink-common.h b/src/stlink-common.h index c982b3df6..5a82e1f49 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -244,6 +244,10 @@ extern "C" { uint32_t process_sp; uint32_t rw; uint32_t rw2; + uint8_t control; + uint8_t faultmask; + uint8_t basepri; + uint8_t primask; uint32_t fpscr; } reg; diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 397723c25..fdd636b61 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -576,6 +576,7 @@ void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { } } +/* See section C1.6 of the ARMv7-M Architecture Reference Manual */ void _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { uint32_t r; @@ -591,6 +592,12 @@ void _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); switch (r_idx) { + case 0x14: + regp->primask = (uint8_t) (r & 0xFF); + regp->basepri = (uint8_t) ((r>>8) & 0xFF); + regp->faultmask = (uint8_t) ((r>>16) & 0xFF); + regp->control = (uint8_t) ((r>>24) & 0xFF); + break; case 0x21: regp->fpscr = r; break; From c6274f026b7848cf45029eccc327f8215738a743 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Mon, 9 Jul 2012 01:00:53 -0400 Subject: [PATCH 0178/1435] Write to extra (FP, etc) registers from GDB The extra registers added in my previous commit can now be modified from within GDB. Since the ST-LINK does not support accessing these registers, a workaround was used from reading an writing to them. That is, the Debug Core Register Selector Register (DCRSR) can be written with the register requested, and it will be read/written to/from the Debug Core Register Data Register (DCRDR). The standard ST-LINK memory access functions are used to make these accesses. A target descriptor XML file is sent to GDB from the server, which tells GDB which registers exist on the target. This is only supported for the STM32F4, and has only been tested on the STM32F4DISCOVERY. I tested st-util on an STM32L-DISCOVERY and my changes did not seem to interfere with its operation. --- AUTHORS | 3 ++- gdbserver/gdb-server.c | 16 +++++++++++++++ src/stlink-common.c | 21 ++++++++++++++++++++ src/stlink-common.h | 4 ++++ src/stlink-usb.c | 44 ++++++++++++++++++++++++++++++++++++++++-- 5 files changed, 85 insertions(+), 3 deletions(-) diff --git a/AUTHORS b/AUTHORS index 1096c1735..5c52c64f3 100644 --- a/AUTHORS +++ b/AUTHORS @@ -14,4 +14,5 @@ bravikov@gmail.com jnosky - codegrinder69@hotmail.com marpe@mimuw.edu.pl marco.cassinerio@gmail.com -jserv@0xlab.org \ No newline at end of file +jserv@0xlab.org +michael@pratt.im diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 789b609e1..ae06952bf 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -999,6 +999,22 @@ int serve(stlink_t *sl, int port) { stlink_write_reg(sl, ntohl(value), reg); } else if(reg == 0x19) { stlink_write_reg(sl, ntohl(value), 16); + } else if(reg == 0x1A) { + stlink_write_reg(sl, ntohl(value), 17); + } else if(reg == 0x1B) { + stlink_write_reg(sl, ntohl(value), 18); + } else if(reg == 0x1C) { + stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if(reg == 0x1D) { + stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if(reg == 0x1E) { + stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if(reg == 0x1F) { + stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if(reg >= 0x20 && reg < 0x40) { + stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if(reg == 0x40) { + stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); } else { reply = strdup("E00"); } diff --git a/src/stlink-common.c b/src/stlink-common.c index 1e9c01114..a86d98549 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -620,6 +620,27 @@ void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { sl->backend->read_unsupported_reg(sl, r_convert, regp); } +void stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) { + int r_convert; + + DLOG("*** stlink_write_unsupported_reg\n"); + DLOG(" (%d) ***\n", r_idx); + + /* Convert to values used by DCRSR */ + if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ + r_convert = r_idx; /* The backend function handles this */ + } else if (r_idx == 0x40) { /* FPSCR */ + r_convert = 0x21; + } else if (r_idx >= 0x20 && r_idx < 0x40) { + r_convert = 0x40 + (r_idx - 0x20); + } else { + fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); + return; + } + + sl->backend->write_unsupported_reg(sl, val, r_convert, regp); +} + unsigned int is_core_halted(stlink_t *sl) { /* return non zero if core is halted */ stlink_status(sl); diff --git a/src/stlink-common.h b/src/stlink-common.h index 5a82e1f49..2e30e71c3 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -112,6 +112,8 @@ extern "C" { /* Cortex™-M3 Technical Reference Manual */ /* Debug Halting Control and Status Register */ #define DHCSR 0xe000edf0 +#define DCRSR 0xe000edf4 +#define DCRDR 0xe000edf8 #define DBGKEY 0xa05f0000 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ @@ -303,6 +305,7 @@ extern "C" { void (*read_reg) (stlink_t *sl, int r_idx, reg * regp); void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp); void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp); + void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp); void (*write_reg) (stlink_t *sl, uint32_t reg, int idx); void (*step) (stlink_t * stl); int (*current_mode) (stlink_t * stl); @@ -371,6 +374,7 @@ extern "C" { void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp); void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp); void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp); + void stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp); void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); void stlink_step(stlink_t *sl); int stlink_current_mode(stlink_t *sl); diff --git a/src/stlink-usb.c b/src/stlink-usb.c index fdd636b61..277431a87 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -585,8 +585,8 @@ void _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { sl->q_buf[i] = 0; } - _stlink_usb_write_mem32(sl, 0xE000EDF4, 4); - _stlink_usb_read_mem32(sl, 0xE000EDF8, 4); + _stlink_usb_write_mem32(sl, DCRSR, 4); + _stlink_usb_read_mem32(sl, DCRDR, 4); r = read_uint32(sl->q_buf, 0); DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); @@ -608,6 +608,7 @@ void _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { } void _stlink_usb_read_all_unsupported_regs(stlink_t *sl, reg *regp) { + _stlink_usb_read_unsupported_reg(sl, 0x14, regp); _stlink_usb_read_unsupported_reg(sl, 0x21, regp); for (int i = 0; i < 32; i++) { @@ -615,6 +616,44 @@ void _stlink_usb_read_all_unsupported_regs(stlink_t *sl, reg *regp) { } } +/* See section C1.6 of the ARMv7-M Architecture Reference Manual */ +void _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) { + if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ + /* These are held in the same register */ + _stlink_usb_read_unsupported_reg(sl, 0x14, regp); + + val = (uint8_t) (val>>24); + + switch (r_idx) { + case 0x1C: /* control */ + val = (((uint32_t) val) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) regp->primask); + break; + case 0x1D: /* faultmask */ + val = (((uint32_t) regp->control) << 24) | (((uint32_t) val) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) regp->primask); + break; + case 0x1E: /* basepri */ + val = (((uint32_t) regp->control) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) val) << 8) | ((uint32_t) regp->primask); + break; + case 0x1F: /* primask */ + val = (((uint32_t) regp->control) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) val); + break; + } + + r_idx = 0x14; + } + + write_uint32(sl->q_buf, val); + + _stlink_usb_write_mem32(sl, DCRDR, 4); + + sl->q_buf[0] = (unsigned char) r_idx; + sl->q_buf[1] = 0; + sl->q_buf[2] = 0x01; + sl->q_buf[3] = 0; + + _stlink_usb_write_mem32(sl, DCRSR, 4); +} + void _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; @@ -657,6 +696,7 @@ stlink_backend_t _stlink_usb_backend = { _stlink_usb_read_reg, _stlink_usb_read_all_unsupported_regs, _stlink_usb_read_unsupported_reg, + _stlink_usb_write_unsupported_reg, _stlink_usb_write_reg, _stlink_usb_step, _stlink_usb_current_mode, From f300f74a0c3e0f66feae6a270ca8b01436ef28d9 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Mon, 9 Jul 2012 11:06:50 -0400 Subject: [PATCH 0179/1435] Fix the stlink-sg backend to leave space for new functions --- src/stlink-sg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 4cae3ee11..ae610bac7 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -872,6 +872,9 @@ stlink_backend_t _stlink_sg_backend = { _stlink_sg_write_mem8, _stlink_sg_read_all_regs, _stlink_sg_read_reg, + NULL, /* read_all_unsupported_regs */ + NULL, /* read_unsupported_regs */ + NULL, /* write_unsupported_regs */ _stlink_sg_write_reg, _stlink_sg_step, _stlink_sg_current_mode, From ca0f89c20bb090daf92e2a2498f8324947c90ea4 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Mon, 9 Jul 2012 11:08:55 -0400 Subject: [PATCH 0180/1435] Fix build warning --- src/stlink-common.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index a86d98549..e142233f7 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -936,7 +936,9 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) } /* Ignore NULL Bytes at end of file */ - ftruncate(fd, size - num_empty); + if (!ftruncate(fd, size - num_empty)) { + error = -1; + } /* success */ error = 0; @@ -1452,7 +1454,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned for(off = 0; off < len;) { size_t size = len - off > 0x8000 ? 0x8000 : len - off; - printf("size: %u\n", size); + printf("size: %zu\n", size); if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); From 684d76afa0f36d9c9cc3974f11fd42aa95e22c02 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Sun, 19 Aug 2012 12:19:25 -0400 Subject: [PATCH 0181/1435] Fix watchpoint support Setting of watchpoints was nested inside of a case statement, so it would only run for that case, even though it supports all cases. --- gdbserver/gdb-server.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index ae06952bf..e6368ea31 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -1108,13 +1108,14 @@ int serve(stlink_t *sl, int port) { wf = WATCHREAD; } else { wf = WATCHACCESS; - if(add_data_watchpoint(sl, wf, addr, len) < 0) { - reply = strdup("E00"); - } else { - reply = strdup("OK"); - break; - } } + + if(add_data_watchpoint(sl, wf, addr, len) < 0) { + reply = strdup("E00"); + } else { + reply = strdup("OK"); + break; + } } default: From e197cd8e2e71bfdfb57ee21aaba0eeb2d189b494 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thomas=20G=C3=A4rtner?= Date: Wed, 22 Aug 2012 15:33:19 +0200 Subject: [PATCH 0182/1435] Added kext for os x 10.8 I added a kext for mountain lion to osx.tar.gz and modified install.sh to use the right one or fail if no suitable kext is available. --- stlinkv1_macosx_driver/osx.tar.gz | Bin 23264 -> 23437 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/stlinkv1_macosx_driver/osx.tar.gz b/stlinkv1_macosx_driver/osx.tar.gz index 6e7bb275ba87719974b35d6ddb051c74b6cb914e..a4af6670bd8f9521f359104e1911fc91c57ad871 100644 GIT binary patch literal 23437 zcmZ^~V|ZUd*YF#=NgAWEjmCD9rm=0Sv2EM7t;T6=+qTXBKE3bfeGWdHFLSM#Su<;{ zJ>0W?Llg-IhOx;e4+eSJwVpycnm{e__%PvgctYR2lrWXrBs~oJa|>kljl|+28sR zqmNY4wq8|%^=*7u9+@6p9mTlnOkCoMDX_80^vY%PiEB{EAq0>|CQw?mlS>Csk46|D zK-p|Vi`G40r67uHX!EG0q{hISA0Jzt%y>XeyFz_C0s8XfufKR84mUq1z&3@}RGfY? zjW%op6(wOaKm~m{xA2Cvh2f3=v+q?c@VR{?Fm@vlDI49C-~46 zi3Wv}yQP=UeSyFXTqnPC-u4tl6yP2EDkyUSL~w*EsYW!RtFMXQ+~tYY#ZK59d~*ShW*^0w;_ia9h7!fnSr&NaW1Muu@~`a%$?}$jwyx` zY(={R?MbP-o>!nn#`kdHeE-leY5Y?USoD1-Vu@#%kG)Rv@xf*6iDT%B*8~99^@rWJ zao_Cv510;6tJHLvU?>VYVf-+auWQfXPOpDIBosLj)Z0gnfG^qfkB84653lyrlcf(d zGsn*lulVi)1#U#M$HNb=@ZLT@b0NHaBkfF~wgx=cMiLv4dZkCaLFf8LkZNopxC6)xo-yL?PE`%P|72a`7M1B zc(x{|`}9fm5u*W_y}UCSQOBzG0HN`YDs@Nqj`)4}{h9YO+jkISub)56WSr$#|H zJ6JpGW%QWin(w+XSWG+P1L@vAYz=%`FZ4o~l#OIk^e4GQ{64nb7rvR#So5P7kG&mP zEA#c_$Pay1`sW{C6KM5(qkl(F-(qvL#|tr4i!zDN_7MMhI+^==r=HVAa)@O*C32H; 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zzn_%jatQw;JFpYlNQwUtyQL8S>oq~jSQ_u=a^xJ3jX%;N>%cfwUPY!*q(Et1BuNC@UE^INp zRj|>o*9iJ6hI)Z;K12U?3cW(RutU&G1g8~-2>%WGaj{f?DzH8{0 zC3<#R$lZw}l(_jXKVtqjX8qsO|M>jJ8svZLb^gfu|0iAl-^2e$$^WwPzb@5|?f>Qc zPvrkY=6~b%|5SN7$baPj=lg$-Q}X<8p8x&+^1u0xn{S@{&3D}VB$?lQ$IZ`NSp2_- z%>Od^|KR`0x&MERl8yg|=YQGwFIJ^I{yR!Jg#Y)+|Hkp(&HuXmuS@kj{yR#^^S^n? jOJ4Glm%QX9FL}vJUhPrLjd4{D&t0O$h%G+`s^ From ff1a7aa50be2878bb47c83637c076a93eeef70a9 Mon Sep 17 00:00:00 2001 From: Jeff Kent Date: Wed, 19 Sep 2012 12:22:28 -0500 Subject: [PATCH 0183/1435] workaround for asserting nRST, issue "monitor jtag_reset" from gdb --- gdbserver/gdb-server.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index e6368ea31..9d27ae48a 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -784,6 +784,16 @@ int serve(stlink_t *sl, int port) { #ifdef DEBUG printf("Rcmd: halt\n"); +#endif + } else if (!strncmp(params,"6a7461675f7265736574",20)) { //jtag_reset + reply = strdup("OK"); + + stlink_jtag_reset(sl, 1); + stlink_jtag_reset(sl, 0); + stlink_force_debug(sl); + +#ifdef DEBUG + printf("Rcmd: jtag_reset\n"); #endif } else if (!strncmp(params,"7265736574",10)) { //reset reply = strdup("OK"); From 8604e0b62510564a571ce0ad0eb79bd31fb58fd9 Mon Sep 17 00:00:00 2001 From: Pekka Nikander Date: Thu, 4 Oct 2012 09:17:50 +0300 Subject: [PATCH 0184/1435] src/stlink-common.c: Fix white spaces, unify coding style --- src/stlink-common.c | 409 +++++++++++++++++++++----------------------- 1 file changed, 193 insertions(+), 216 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index e142233f7..217c01faf 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -231,7 +231,7 @@ static void set_flash_cr_mer(stlink_t *sl) { if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); - else + else stlink_write_debug32(sl, FLASH_CR, stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER)); } @@ -240,7 +240,7 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); - else + else stlink_write_debug32(sl, FLASH_CR, stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER)); } @@ -254,7 +254,7 @@ static void set_flash_cr_strt(stlink_t *sl) { } else { stlink_write_debug32( - sl, FLASH_CR, + sl, FLASH_CR, stlink_read_debug32(sl,FLASH_CR) |(1 << FLASH_CR_STRT) ); } } @@ -422,7 +422,7 @@ int stlink_load_device_params(stlink_t *sl) { const chip_params_t *params = NULL; sl->core_id = stlink_core_id(sl); uint32_t chip_id = stlink_chip_id(sl); - + sl->chip_id = chip_id & 0xfff; /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/ if (sl->chip_id == 0x411) { @@ -441,11 +441,11 @@ int stlink_load_device_params(stlink_t *sl) { WLOG("unknown chip id! %#x\n", chip_id); return -1; } - + // These are fixed... sl->flash_base = STM32_FLASH_BASE; sl->sram_base = STM32_SRAM_BASE; - + // read flash size from hardware, if possible... if (sl->chip_id == STM32_CHIPID_F2) { sl->flash_size = 0x100000; /* Use maximum, User must care!*/ @@ -459,11 +459,11 @@ int stlink_load_device_params(stlink_t *sl) { sl->sram_size = params->sram_size; sl->sys_base = params->bootrom_base; sl->sys_size = params->bootrom_size; - + ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); // TODO make note of variable page size here..... ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n", - sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, + sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, sl->flash_pgsz); return 0; } @@ -518,7 +518,7 @@ void stlink_version(stlink_t *sl) { DLOG("*** looking up stlink version\n"); sl->backend->version(sl); _parse_version(sl, &sl->version); - + DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID); DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); DLOG("stlink version = 0x%x\n", sl->version.stlink_v); @@ -993,8 +993,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) - { + if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1020,9 +1019,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif - } - else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) - { + } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { uint32_t val; @@ -1032,8 +1029,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) /* check pecr.pelock is cleared */ val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 0)) - { + if (val & (1 << 0)) { WLOG("pecr.pelock not clear (%#x)\n", val); return -1; } @@ -1044,8 +1040,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) /* check pecr.prglock is cleared */ val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 1)) - { + if (val & (1 << 1)) { WLOG("pecr.prglock not clear (%#x)\n", val); return -1; } @@ -1057,8 +1052,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) /* check pecr.optlock is cleared */ val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 2)) - { + if (val & (1 << 2)) { fprintf(stderr, "pecr.prglock not clear\n"); return -1; } @@ -1077,8 +1071,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) it. If someone has a problem, please drop an email. */ while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) - { - } + ; #endif /* fix_to_be_confirmed */ @@ -1090,16 +1083,13 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) Test shows that a few iterations is performed in the following loop before busy bit is cleared.*/ while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) - { - } + ; /* reset lock bits */ val = stlink_read_debug32(sl, STM32L_FLASH_PECR) | (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - } - else if (sl->core_id == STM32VL_CORE_ID) - { + } else if (sl->core_id == STM32VL_CORE_ID) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1120,9 +1110,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) /* relock the flash */ lock_flash(sl); - } - - else { + } else { WLOG("unknown coreid: %x\n", sl->core_id); return -1; } @@ -1133,42 +1121,41 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { - /* erase each page */ - int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; - for (i = 0; i < num_pages; i++) { - /* addr must be an addr inside the page */ - stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz; - if (stlink_erase_flash_page(sl, addr) == -1) { - WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr); - return -1; - } - fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages); - fflush(stdout); - } - fprintf(stdout, "\n"); - } - else { - /* wait for ongoing op to finish */ - wait_flash_busy(sl); - - /* unlock if locked */ - unlock_flash_if(sl); - - /* set the mass erase bit */ - set_flash_cr_mer(sl); - - /* start erase operation, reset by hw with bsy bit */ - set_flash_cr_strt(sl); - - /* wait for completion */ - wait_flash_busy_progress(sl); - - /* relock the flash */ - lock_flash(sl); - - /* todo: verify the erased memory */ - } + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { + /* erase each page */ + int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; + for (i = 0; i < num_pages; i++) { + /* addr must be an addr inside the page */ + stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz; + if (stlink_erase_flash_page(sl, addr) == -1) { + WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr); + return -1; + } + fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages); + fflush(stdout); + } + fprintf(stdout, "\n"); + } else { + /* wait for ongoing op to finish */ + wait_flash_busy(sl); + + /* unlock if locked */ + unlock_flash_if(sl); + + /* set the mass erase bit */ + set_flash_cr_mer(sl); + + /* start erase operation, reset by hw with bsy bit */ + set_flash_cr_strt(sl); + + /* wait for completion */ + wait_flash_busy_progress(sl); + + /* relock the flash */ + lock_flash(sl); + + /* todo: verify the erased memory */ + } return 0; } @@ -1212,67 +1199,60 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { static const uint8_t loader_code_stm32l[] = { - /* openocd.git/contrib/loaders/flash/stm32lx.S - r0, input, dest addr - r1, input, source addr - r2, input, word count - r3, output, word count - */ + /* openocd.git/contrib/loaders/flash/stm32lx.S + r0, input, dest addr + r1, input, source addr + r2, input, word count + r3, output, word count + */ - 0x00, 0x23, - 0x04, 0xe0, + 0x00, 0x23, + 0x04, 0xe0, - 0x51, 0xf8, 0x04, 0xcb, - 0x40, 0xf8, 0x04, 0xcb, - 0x01, 0x33, + 0x51, 0xf8, 0x04, 0xcb, + 0x40, 0xf8, 0x04, 0xcb, + 0x01, 0x33, - 0x93, 0x42, - 0xf8, 0xd3, - 0x00, 0xbe + 0x93, 0x42, + 0xf8, 0xd3, + 0x00, 0xbe }; - static const uint8_t loader_code_stm32f4[] = { - // flashloaders/stm32f4.s + static const uint8_t loader_code_stm32f4[] = { + // flashloaders/stm32f4.s - 0x07, 0x4b, + 0x07, 0x4b, - 0x62, 0xb1, - 0x04, 0x68, - 0x0c, 0x60, + 0x62, 0xb1, + 0x04, 0x68, + 0x0c, 0x60, - 0xdc, 0x89, - 0x14, 0xf0, 0x01, 0x0f, - 0xfb, 0xd1, - 0x00, 0xf1, 0x04, 0x00, - 0x01, 0xf1, 0x04, 0x01, - 0xa2, 0xf1, 0x01, 0x02, - 0xf1, 0xe7, + 0xdc, 0x89, + 0x14, 0xf0, 0x01, 0x0f, + 0xfb, 0xd1, + 0x00, 0xf1, 0x04, 0x00, + 0x01, 0xf1, 0x04, 0x01, + 0xa2, 0xf1, 0x01, 0x02, + 0xf1, 0xe7, - 0x00, 0xbe, + 0x00, 0xbe, - 0x00, 0x3c, 0x02, 0x40, - }; + 0x00, 0x3c, 0x02, 0x40, + }; const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) /* stm32l */ - { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); - } - else if (sl->core_id == STM32VL_CORE_ID) - { + } else if (sl->core_id == STM32VL_CORE_ID) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); - } - else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) - { - loader_code = loader_code_stm32f4; - loader_size = sizeof(loader_code_stm32f4); - } - else - { + } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { + loader_code = loader_code_stm32f4; + loader_size = sizeof(loader_code_stm32f4); + } else { WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); return -1; } @@ -1339,7 +1319,7 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, } int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned num_half_pages) -{ +{ unsigned int count; uint32_t val; flash_loader_t fl; @@ -1354,7 +1334,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uns val = stlink_read_debug32(sl, STM32L_FLASH_PECR); val |= (1 << FLASH_L1_FPRG); stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - + val |= (1 << FLASH_L1_PROG); stlink_write_debug32(sl, STM32L_FLASH_PECR, val); while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {} @@ -1428,18 +1408,18 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned page_count++; } fprintf(stdout,"\n"); - ILOG("Finished erasing %d pages of %d (%#x) bytes\n", + ILOG("Finished erasing %d pages of %d (%#x) bytes\n", page_count, sl->flash_pgsz, sl->flash_pgsz); if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) { /* todo: check write operation */ - ILOG("Starting Flash write for F2/F4\n"); - /* flash loader initialization */ - if (init_flash_loader(sl, &fl) == -1) { - WLOG("init_flash_loader() == -1\n"); - return -1; - } + ILOG("Starting Flash write for F2/F4\n"); + /* flash loader initialization */ + if (init_flash_loader(sl, &fl) == -1) { + WLOG("init_flash_loader() == -1\n"); + return -1; + } /* First unlock the cr */ unlock_flash_if(sl); @@ -1451,38 +1431,39 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned /* set programming mode */ set_flash_cr_pg(sl); - for(off = 0; off < len;) { - size_t size = len - off > 0x8000 ? 0x8000 : len - off; + for(off = 0; off < len;) { + size_t size = len - off > 0x8000 ? 0x8000 : len - off; - printf("size: %zu\n", size); + printf("size: %zu\n", size); - if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { - WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); - return -1; - } + if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { + WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); + return -1; + } - off += size; - } + off += size; + } #if 0 #define PROGRESS_CHUNK_SIZE 0x1000 /* write a word in program memory */ for (off = 0; off < len; off += sizeof(uint32_t)) { - uint32_t data; - if (sl->verbose >= 1) { - if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) { - /* show progress. writing procedure is slow - and previous errors are misleading */ - const uint32_t pgnum = (off / PROGRESS_CHUNK_SIZE)+1; - const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE +1; - fprintf(stdout, "Writing %ukB chunk %u out of %u\n", PROGRESS_CHUNK_SIZE/1024, pgnum, pgcount); - } - } - - write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); - stlink_write_debug32(sl, addr + off, data); - - /* wait for sr.busy to be cleared */ + uint32_t data; + if (sl->verbose >= 1) { + if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) { + /* show progress. writing procedure is slow + and previous errors are misleading */ + const uint32_t pgnum = (off / PROGRESS_CHUNK_SIZE)+1; + const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE +1; + fprintf(stdout, "Writing %ukB chunk %u out of %u\n", + PROGRESS_CHUNK_SIZE/1024, pgnum, pgcount); + } + } + + write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); + stlink_write_debug32(sl, addr + off, data); + + /* wait for sr.busy to be cleared */ wait_flash_busy(sl); } @@ -1494,8 +1475,6 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned fprintf(stdout, "Final CR:0x%x\n", read_flash_cr(sl)); #endif - - } //STM32F4END else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { @@ -1533,70 +1512,69 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned } off = 0; if (len > L1_WRITE_BLOCK_SIZE) { - if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1){ + if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1) { /* This may happen on a blank device! */ WLOG("\nwrite_half_pages failed == -1\n"); - } - else{ + } else { off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE; } } /* write remainingword in program memory */ for ( ; off < len; off += sizeof(uint32_t)) { - uint32_t data; - if (off > 254) - fprintf(stdout, "\r"); - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { - fprintf(stdout, "\r%3zd/%3zd pages written", - off/sl->flash_pgsz, len/sl->flash_pgsz); - fflush(stdout); - } + uint32_t data; + if (off > 254) + fprintf(stdout, "\r"); + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { + fprintf(stdout, "\r%3zd/%3zd pages written", + off/sl->flash_pgsz, len/sl->flash_pgsz); + fflush(stdout); + } - write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); - stlink_write_debug32(sl, addr + off, data); + write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); + stlink_write_debug32(sl, addr + off, data); - /* wait for sr.busy to be cleared */ - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { - } + /* wait for sr.busy to be cleared */ + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) + ; #if 0 /* todo: check redo write operation */ - /* check written bytes. todo: should be on a per page basis. */ - data = stlink_read_debug32(sl, addr + off); - if (data == *(uint32_t*)(base + off)) { - /* re erase the page and redo the write operation */ - uint32_t page; - uint32_t val; + /* check written bytes. todo: should be on a per page basis. */ + data = stlink_read_debug32(sl, addr + off); + if (data == *(uint32_t*)(base + off)) { + /* re erase the page and redo the write operation */ + uint32_t page; + uint32_t val; - /* fail if successive write count too low */ - if (nwrites < sl->flash_pgsz) { - fprintf(stderr, "writes operation failure count too high, aborting\n"); - return -1; - } + /* fail if successive write count too low */ + if (nwrites < sl->flash_pgsz) { + fprintf(stderr, "writes operation failure count too high, aborting\n"); + return -1; + } - nwrites = 0; + nwrites = 0; - /* assume addr aligned */ - if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1); - page = addr + off; + /* assume addr aligned */ + if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1); + page = addr + off; - fprintf(stderr, "invalid write @0x%x(0x%x): 0x%x != 0x%x. retrying.\n", - page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0)); + fprintf(stderr, "invalid write @0x%x(0x%x): 0x%x != 0x%x. retrying.\n", + page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0)); - /* reset lock bits */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR) - | (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + /* reset lock bits */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR) + | (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - stlink_erase_flash_page(sl, page); + stlink_erase_flash_page(sl, page); - goto redo_write; - } + goto redo_write; + } - /* increment successive writes counter */ - ++nwrites; + /* increment successive writes counter */ + ++nwrites; #endif /* todo: check redo write operation */ } @@ -1640,7 +1618,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id); return -1; } - + return stlink_verify_write_flash(sl, addr, base, len); } @@ -1695,49 +1673,48 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { - size_t count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) ++count; + size_t count = size / sizeof(uint32_t); + if (size % sizeof(uint32_t)) ++count; - /* setup core */ - stlink_write_reg(sl, target, 0); /* target */ - stlink_write_reg(sl, fl->buf_addr, 1); /* source */ - stlink_write_reg(sl, count, 2); /* count (32 bits words) */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ + /* setup core */ + stlink_write_reg(sl, target, 0); /* target */ + stlink_write_reg(sl, fl->buf_addr, 1); /* source */ + stlink_write_reg(sl, count, 2); /* count (32 bits words) */ + stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ } else if (sl->core_id == STM32VL_CORE_ID) { - size_t count = size / sizeof(uint16_t); - if (size % sizeof(uint16_t)) ++count; + size_t count = size / sizeof(uint16_t); + if (size % sizeof(uint16_t)) ++count; - /* setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); /* source */ - stlink_write_reg(sl, target, 1); /* target */ - stlink_write_reg(sl, count, 2); /* count (16 bits half words) */ - stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ + /* setup core */ + stlink_write_reg(sl, fl->buf_addr, 0); /* source */ + stlink_write_reg(sl, target, 1); /* target */ + stlink_write_reg(sl, count, 2); /* count (16 bits half words) */ + stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */ + stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { + } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { - size_t count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) ++count; + size_t count = size / sizeof(uint32_t); + if (size % sizeof(uint32_t)) ++count; - /* setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); /* source */ - stlink_write_reg(sl, target, 1); /* target */ - stlink_write_reg(sl, count, 2); /* count (32 bits words) */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ + /* setup core */ + stlink_write_reg(sl, fl->buf_addr, 0); /* source */ + stlink_write_reg(sl, target, 1); /* target */ + stlink_write_reg(sl, count, 2); /* count (32 bits words) */ + stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ } else { - fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id); - return -1; + fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id); + return -1; } /* run loader */ stlink_run(sl); /* wait until done (reaches breakpoint) */ - while ((is_core_halted(sl) == 0) && (i <1000)) - { + while ((is_core_halted(sl) == 0) && (i <1000)) { i++; } @@ -1745,7 +1722,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons fprintf(stderr, "run error\n"); return -1; } - + /* check written byte count */ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { From f0256c69cb3aa421f9266fd9adecbe5343036eb2 Mon Sep 17 00:00:00 2001 From: Pekka Nikander Date: Fri, 5 Oct 2012 15:30:28 +0300 Subject: [PATCH 0185/1435] src/stlink-common.[ch]: Another fix on white spaces, unifying coding style --- src/stlink-common.c | 129 +++++++++++++++++++++----------------------- src/stlink-common.h | 6 +-- 2 files changed, 64 insertions(+), 71 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 217c01faf..7e3dc1b35 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -134,23 +134,23 @@ static inline uint32_t read_flash_obr(stlink_t *sl) { } static inline uint32_t read_flash_cr(stlink_t *sl) { - uint32_t res; - if((sl->chip_id==STM32_CHIPID_F2) ||(sl->chip_id==STM32_CHIPID_F4)) - res = stlink_read_debug32(sl, FLASH_F4_CR); - else - res = stlink_read_debug32(sl, FLASH_CR); + uint32_t res; + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) + res = stlink_read_debug32(sl, FLASH_F4_CR); + else + res = stlink_read_debug32(sl, FLASH_CR); #if DEBUG_FLASH - fprintf(stdout, "CR:0x%x\n", res); + fprintf(stdout, "CR:0x%x\n", res); #endif - return res; + return res; } static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) - return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); - else - return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) + return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); + else + return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); } static void unlock_flash(stlink_t *sl) { @@ -159,14 +159,13 @@ static void unlock_flash(stlink_t *sl) { an invalid sequence results in a definitive lock of the FPEC block until next reset. */ - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) { + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) { stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); - stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); - } - else { + stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); + } else { stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1); - stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2); - } + stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2); + } } @@ -185,11 +184,10 @@ static int unlock_flash_if(stlink_t *sl) { } static void lock_flash(stlink_t *sl) { - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) { + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) { const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); stlink_write_debug32(sl, FLASH_F4_CR, n); - } - else { + } else { /* write to 1 only. reset by hw at unlock sequence */ const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK); stlink_write_debug32(sl, FLASH_CR, n); @@ -198,12 +196,11 @@ static void lock_flash(stlink_t *sl) { static void set_flash_cr_pg(stlink_t *sl) { - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) { + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_CR_PG); stlink_write_debug32(sl, FLASH_F4_CR, x); - } - else { + } else { const uint32_t n = 1 << FLASH_CR_PG; stlink_write_debug32(sl, FLASH_CR, n); } @@ -211,7 +208,7 @@ static void set_flash_cr_pg(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) stlink_write_debug32(sl, FLASH_F4_CR, n); else stlink_write_debug32(sl, FLASH_CR, n); @@ -228,7 +225,7 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { } static void set_flash_cr_mer(stlink_t *sl) { - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); else @@ -237,7 +234,7 @@ static void set_flash_cr_mer(stlink_t *sl) { } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); else @@ -246,17 +243,14 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { } static void set_flash_cr_strt(stlink_t *sl) { - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) - { - uint32_t x = read_flash_cr(sl); - x |= (1 << FLASH_F4_CR_STRT); - stlink_write_debug32(sl, FLASH_F4_CR, x); - } - else { - stlink_write_debug32( - sl, FLASH_CR, - stlink_read_debug32(sl,FLASH_CR) |(1 << FLASH_CR_STRT) ); - } + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) { + uint32_t x = read_flash_cr(sl); + x |= (1 << FLASH_F4_CR_STRT); + stlink_write_debug32(sl, FLASH_F4_CR, x); + } else { + stlink_write_debug32(sl, FLASH_CR, + stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_STRT) ); + } } static inline uint32_t read_flash_acr(stlink_t *sl) { @@ -264,20 +258,20 @@ static inline uint32_t read_flash_acr(stlink_t *sl) { } static inline uint32_t read_flash_sr(stlink_t *sl) { - uint32_t res; - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) - res = stlink_read_debug32(sl, FLASH_F4_SR); - else - res = stlink_read_debug32(sl, FLASH_SR); + uint32_t res; + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) + res = stlink_read_debug32(sl, FLASH_F4_SR); + else + res = stlink_read_debug32(sl, FLASH_SR); //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf); return res; } static inline unsigned int is_flash_busy(stlink_t *sl) { - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) - return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); - else - return read_flash_sr(sl) & (1 << FLASH_SR_BSY); + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) + return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); + else + return read_flash_sr(sl) & (1 << FLASH_SR_BSY); } static void wait_flash_busy(stlink_t *sl) { @@ -290,8 +284,7 @@ static void wait_flash_busy_progress(stlink_t *sl) { int i = 0; fprintf(stdout, "Mass erasing"); fflush(stdout); - while (is_flash_busy(sl)) - { + while (is_flash_busy(sl)) { usleep(10000); i++; if (i % 100 == 0) { @@ -427,11 +420,11 @@ int stlink_load_device_params(stlink_t *sl) { /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/ if (sl->chip_id == 0x411) { uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00); - if((cpuid & 0xfff0) == 0xc240) + if ((cpuid & 0xfff0) == 0xc240) sl->chip_id = 0x413; } - for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { + for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { if(devices[i].chip_id == sl->chip_id) { params = &devices[i]; break; @@ -894,7 +887,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) int error = -1; size_t off; int num_empty = 0; - unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff; + unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -976,7 +969,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ - if((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) { + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector<4) sl->flash_pgsz=0x4000; else if(sector<5) sl->flash_pgsz=0x10000; @@ -993,7 +986,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) { + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1244,17 +1237,17 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { size_t loader_size; if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { /* stm32l */ - loader_code = loader_code_stm32l; - loader_size = sizeof(loader_code_stm32l); + loader_code = loader_code_stm32l; + loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID) { - loader_code = loader_code_stm32vl; - loader_size = sizeof(loader_code_stm32vl); + loader_code = loader_code_stm32vl; + loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { - loader_code = loader_code_stm32f4; - loader_size = sizeof(loader_code_stm32f4); + loader_code = loader_code_stm32f4; + loader_size = sizeof(loader_code_stm32f4); } else { - WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); - return -1; + WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); + return -1; } memcpy(sl->q_buf, loader_code, loader_size); @@ -1411,7 +1404,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned ILOG("Finished erasing %d pages of %d (%#x) bytes\n", page_count, sl->flash_pgsz, sl->flash_pgsz); - if ((sl->chip_id == STM32_CHIPID_F2) ||(sl->chip_id == STM32_CHIPID_F4)) { + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) { /* todo: check write operation */ ILOG("Starting Flash write for F2/F4\n"); @@ -1743,13 +1736,13 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { + } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { - stlink_read_reg(sl, 2, &rr); - if (rr.r[2] != 0) { - fprintf(stderr, "write error, count == %u\n", rr.r[2]); - return -1; - } + stlink_read_reg(sl, 2, &rr); + if (rr.r[2] != 0) { + fprintf(stderr, "write error, count == %u\n", rr.r[2]); + return -1; + } } else { diff --git a/src/stlink-common.h b/src/stlink-common.h index 2e30e71c3..7ffdfc0cd 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -129,9 +129,9 @@ extern "C" { } chip_params_t; - // These maps are from a combination of the Programming Manuals, and - // also the Reference manuals. (flash size reg is normally in ref man) - static const chip_params_t devices[] = { +// These maps are from a combination of the Programming Manuals, and +// also the Reference manuals. (flash size reg is normally in ref man) +static const chip_params_t devices[] = { { // table 2, PM0063 .chip_id = 0x410, .description = "F1 Medium-density device", From bfc368c57e2ef2701d2100dd61f1d2f7cb30b302 Mon Sep 17 00:00:00 2001 From: Pekka Nikander Date: Fri, 5 Oct 2012 15:32:48 +0300 Subject: [PATCH 0186/1435] src/stlink-common.c: Improve error reporting --- src/stlink-common.c | 52 +++++++++++++++++++++++++-------------------- 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 7e3dc1b35..702536aed 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -18,6 +18,7 @@ #define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) #define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) #define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) +#define ELOG(format, args...) ugly_log(UERROR, LOG_TAG, format, ## args) #define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) /* todo: stm32l15xxx flash memory, pm0062 manual */ @@ -1104,7 +1105,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) /* relock the flash */ lock_flash(sl); } else { - WLOG("unknown coreid: %x\n", sl->core_id); + WLOG("unknown coreid %x, page erase failed\n", sl->core_id); return -1; } @@ -1246,7 +1247,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { loader_code = loader_code_stm32f4; loader_size = sizeof(loader_code_stm32f4); } else { - WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); + ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); return -1; } @@ -1302,7 +1303,7 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, stlink_read_mem32(sl, address + off, aligned_size); if (memcmp(sl->q_buf, data + off, cmp_size)) { - WLOG("Verification of flash failed at offset: %zd\n", off); + ELOG("Verification of flash failed at offset: %zd\n", off); return -1; } } @@ -1369,19 +1370,22 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned /* check addr range is inside the flash */ stlink_calculate_pagesize(sl, addr); if (addr < sl->flash_base) { - WLOG("addr too low %#x < %#x\n", addr, sl->flash_base); + ELOG("addr too low %#x < %#x\n", addr, sl->flash_base); return -1; } else if ((addr + len) < addr) { - WLOG("addr overruns\n"); + ELOG("addr overruns\n"); return -1; } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { - WLOG("addr too high\n"); + ELOG("addr too high\n"); return -1; - } else if ((addr & 1) || (len & 1)) { - WLOG("unaligned addr or size\n"); + } else if (addr & 1) { + ELOG("unaligned addr 0x%x\n", addr); return -1; + } else if (len & 1) { + WLOG("unaligned len 0x%x -- padding with zero\n", len); + len += 1; } else if (addr & (sl->flash_pgsz - 1)) { - WLOG("addr not a multiple of pagesize, not supported\n"); + ELOG("addr not a multiple of pagesize, not supported\n"); return -1; } @@ -1392,7 +1396,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off)) { /* addr must be an addr inside the page */ if (stlink_erase_flash_page(sl, addr + off) == -1) { - WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); + ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); return -1; } fprintf(stdout,"\rFlash page at addr: 0x%08lx erased", @@ -1410,7 +1414,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned ILOG("Starting Flash write for F2/F4\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { - WLOG("init_flash_loader() == -1\n"); + ELOG("init_flash_loader() == -1\n"); return -1; } @@ -1430,7 +1434,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned printf("size: %zu\n", size); if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { - WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); + ELOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); return -1; } @@ -1580,7 +1584,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned ILOG("Starting Flash write for VL core id\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { - WLOG("init_flash_loader() == -1\n"); + ELOG("init_flash_loader() == -1\n"); return -1; } @@ -1595,7 +1599,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned set_flash_cr_pg(sl); //DLOG("Finished setting flash cr pg, running loader!\n"); if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { - WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); + ELOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); return -1; } lock_flash(sl); @@ -1608,7 +1612,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned } fprintf(stdout, "\n"); } else { - WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); return -1; } @@ -1629,7 +1633,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { - WLOG("map_file() == -1\n"); + ELOG("map_file() == -1\n"); return -1; } for(index = 0; index < mf.len; index ++) { @@ -1660,7 +1664,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons // FIXME This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { // IMPOSSIBLE! - WLOG("write_buffer_to_sram() == -1\n"); + ELOG("write_buffer_to_sram() == -1\n"); return -1; } @@ -1699,20 +1703,22 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ } else { - fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id); + fprintf(stderr, "unknown coreid 0x%x, don't know what flash loader to use\n", sl->core_id); return -1; } /* run loader */ stlink_run(sl); +#define WAIT_ROUNDS 1000 /* wait until done (reaches breakpoint) */ - while ((is_core_halted(sl) == 0) && (i <1000)) { - i++; + for (i = 0; i < WAIT_ROUNDS; i++) { + if (is_core_halted(sl)) + break; } - if ( i > 999) { - fprintf(stderr, "run error\n"); + if (i >= WAIT_ROUNDS) { + fatal("flash loader run error\n"); return -1; } @@ -1746,7 +1752,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else { - fprintf(stderr, "unknown coreid: 0x%x\n", sl->core_id); + fprintf(stderr, "unknown coreid 0x%x, can't check written byte count\n", sl->core_id); return -1; } From e8b15c0e787c7d5fc90c35d53165fcf36afb39e3 Mon Sep 17 00:00:00 2001 From: Pekka Nikander Date: Fri, 5 Oct 2012 15:34:03 +0300 Subject: [PATCH 0187/1435] Add support for STM32F0-Discovery --- flashloaders/stm32f0.s | 32 +++++++++++++++++++++ src/stlink-common.c | 63 ++++++++++++++++++++++++++++++++++++++---- src/stlink-common.h | 2 ++ 3 files changed, 92 insertions(+), 5 deletions(-) create mode 100644 flashloaders/stm32f0.s diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s new file mode 100644 index 000000000..f35fe406e --- /dev/null +++ b/flashloaders/stm32f0.s @@ -0,0 +1,32 @@ +/* Adopted from STM AN4065 stm32f0xx_flash.c:FLASH_ProgramWord */ + +write: + ldr r4, STM32_FLASH_BASE + mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */ + mov r6, #4 /* PGERR */ +write_half_word: + ldr r3, [r4, #16] /* FLASH->CR */ + orr r3, r5 + str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */ + ldrh r3, [r0] /* r3 = *sram */ + strh r3, [r1] /* *flash = r3 */ +busy: + ldr r3, [r4, #12] /* FLASH->SR */ + tst r3, r5 /* FLASH_SR_BUSY */ + beq busy + + tst r3, r6 /* PGERR */ + bne exit + + add r0, r0, #2 /* sram += 2 */ + add r1, r1, #2 /* flash += 2 */ + sub r2, r2, #0x01 /* count-- */ + cmp r2, #0 + bne write_half_word +exit: + ldr r3, [r4, #16] /* FLASH->CR */ + bic r3, r5 + str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */ + bkpt #0x00 + +STM32_FLASH_BASE: .word 0x40022000 diff --git a/src/stlink-common.c b/src/stlink-common.c index 702536aed..03de0b8ec 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -25,6 +25,7 @@ /* stm32f FPEC flash controller interface, pm0063 manual */ // TODO - all of this needs to be abstracted out.... +// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) #define FLASH_REGS_ADDR 0x40022000 #define FLASH_REGS_SIZE 0x28 @@ -36,6 +37,7 @@ #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) +// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... #define FLASH_RDPTR_KEY 0x00a5 #define FLASH_KEY1 0x45670123 #define FLASH_KEY2 0xcdef89ab @@ -1083,7 +1085,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) val = stlink_read_debug32(sl, STM32L_FLASH_PECR) | (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - } else if (sl->core_id == STM32VL_CORE_ID) { + } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1191,6 +1193,54 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */ }; + /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ + static const uint8_t loader_code_stm32f0[] = { +#if 1 + /* + * These two NOPs here are a safety precaution, added by Pekka Nikander + * while debugging the STM32F05x support. They may not be needed, but + * there were strange problems with simpler programs, like a program + * that had just a breakpoint or a program that first moved zero to register r2 + * and then had a breakpoint. So, it appears safest to have these two nops. + * + * Feel free to remove them, if you dare, but then please do test the result + * rigorously. Also, if you remove these, it may be a good idea first to + * #if 0 them out, with a comment when these were taken out, and to remove + * these only a few months later... But YMMV. + */ + 0x00, 0x30, // nop /* add r0,#0 */ + 0x00, 0x30, // nop /* add r0,#0 */ +#endif + 0x0A, 0x4C, // ldr r4, STM32_FLASH_BASE + 0x01, 0x25, // mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */ + 0x04, 0x26, // mov r6, #4 /* PGERR */ + // write_half_word: + 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */ + 0x2B, 0x43, // orr r3, r5 + 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */ + 0x03, 0x88, // ldrh r3, [r0] /* r3 = *sram */ + 0x0B, 0x80, // strh r3, [r1] /* *flash = r3 */ + // busy: + 0xE3, 0x68, // ldr r3, [r4, #12] /* FLASH->SR */ + 0x2B, 0x42, // tst r3, r5 /* FLASH_SR_BUSY */ + 0xFC, 0xD0, // beq busy + + 0x33, 0x42, // tst r3, r6 /* PGERR */ + 0x04, 0xD1, // bne exit + + 0x02, 0x30, // add r0, r0, #2 /* sram += 2 */ + 0x02, 0x31, // add r1, r1, #2 /* flash += 2 */ + 0x01, 0x3A, // sub r2, r2, #0x01 /* count-- */ + 0x00, 0x2A, // cmp r2, #0 + 0xF0, 0xD1, // bne write_half_word + // exit: + 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */ + 0xAB, 0x43, // bic r3, r5 + 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */ + 0x00, 0xBE, // bkpt #0x00 + 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */ + }; + static const uint8_t loader_code_stm32l[] = { /* openocd.git/contrib/loaders/flash/stm32lx.S @@ -1246,6 +1296,9 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { loader_code = loader_code_stm32f4; loader_size = sizeof(loader_code_stm32f4); + } else if (sl->chip_id == STM32_CHIPID_F0) { + loader_code = loader_code_stm32f0; + loader_size = sizeof(loader_code_stm32f0); } else { ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); return -1; @@ -1580,8 +1633,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned val = stlink_read_debug32(sl, STM32L_FLASH_PECR) | (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - } else if (sl->core_id == STM32VL_CORE_ID) { - ILOG("Starting Flash write for VL core id\n"); + } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) { + ILOG("Starting Flash write for VL/F0 core id\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { ELOG("init_flash_loader() == -1\n"); @@ -1679,7 +1732,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, count, 2); /* count (32 bits words) */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - } else if (sl->core_id == STM32VL_CORE_ID) { + } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) { size_t count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; @@ -1734,7 +1787,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - } else if (sl->core_id == STM32VL_CORE_ID) { + } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { diff --git a/src/stlink-common.h b/src/stlink-common.h index 7ffdfc0cd..c5c7d407d 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -85,6 +85,7 @@ extern "C" { #define STM32VL_CORE_ID 0x1ba01477 #define STM32L_CORE_ID 0x2ba01477 #define STM32F4_CORE_ID 0x2ba01477 +#define STM32F0_CORE_ID 0xbb11477 #define CORE_M3_R1 0x1BA00477 #define CORE_M3_R2 0x4BA00477 #define CORE_M4_R0 0x2BA01477 @@ -104,6 +105,7 @@ extern "C" { #define STM32_CHIPID_F1_VL_MEDIUM 0x420 #define STM32_CHIPID_F1_VL_HIGH 0x428 #define STM32_CHIPID_F1_XL 0x430 +#define STM32_CHIPID_F0 0x440 // Constant STM32 memory map figures #define STM32_FLASH_BASE 0x08000000 From aa66f4ed87cd0d6f781440d8cd0e205eabcd425a Mon Sep 17 00:00:00 2001 From: "Wojciech A. Koszek" Date: Sat, 3 Nov 2012 23:20:17 -0700 Subject: [PATCH 0188/1435] Bring the support for STM32 F3 Discovery board (ARM Techcon 2012) Support was tested by attaching USB cable to USB ST-LINK USB port, starting ./st-util Which resulted in proper device recognition: 2012-11-03T23:11:25 INFO src/stlink-common.c: Device connected is: F3 device, id 0x10016422 2012-11-03T23:11:25 INFO src/stlink-common.c: SRAM size: 0xa000 bytes (40 KiB), Flash: 0x40000 bytes (256 KiB) in pages of 2048 bytes Chip ID is 00000422, Core ID is 2ba01477. Then from GDB, after "target remove localhost:4242", I tested reads: x/w 0x20000000 And writes: set {int}0x20000000 1 And ELF loading: (gdb) load main Loading section .text, size 0x10 lma 0x20000000 Start address 0x20000000, load size 16 Transfer rate: 410 bytes/sec, 16 bytes/write. And verified dissasembly (in my case--with Thumb mode) with objdump -d output: (gdb) set arm force-mode thumb (gdb) x/7i 0x20000000 => 0x20000000: push {r7} 0x20000002: sub sp, #12 0x20000004: add r7, sp, #0 0x20000006: ldr r3, [r7, #4] 0x20000008: add.w r3, r3, #1 0x2000000c: str r3, [r7, #4] 0x2000000e: b.n 0x20000006 --- src/stlink-common.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/stlink-common.h b/src/stlink-common.h index c5c7d407d..0330e624b 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -208,6 +208,17 @@ static const chip_params_t devices[] = { .bootrom_base = 0x1ffff000, .bootrom_size = 0x800 }, + { + // This is STK32F303VCT6 device from STM32 F3 Discovery board. + // Support based on DM00043574.pdf (RM0316) document. + .chip_id = 0x422, + .description = "F3 device", + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, { .chip_id = 0x428, .description = "F1 High-density value line device", From 79429149716d1fa2107b47cbcfde232db4a20747 Mon Sep 17 00:00:00 2001 From: lementec Date: Thu, 15 Nov 2012 17:37:00 +0100 Subject: [PATCH 0189/1435] [ merge ] STM32_CHIPIP_F3 patch from Geoffrey Brown --- src/stlink-common.c | 10 +++++----- src/stlink-common.h | 2 ++ 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 03de0b8ec..66006f083 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1085,7 +1085,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) val = stlink_read_debug32(sl, STM32L_FLASH_PECR) | (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) { + } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1290,7 +1290,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); - } else if (sl->core_id == STM32VL_CORE_ID) { + } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { @@ -1633,7 +1633,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned val = stlink_read_debug32(sl, STM32L_FLASH_PECR) | (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) { + } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3) { ILOG("Starting Flash write for VL/F0 core id\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { @@ -1732,7 +1732,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, count, 2); /* count (32 bits words) */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) { + } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3) { size_t count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; @@ -1787,7 +1787,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID) { + } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { diff --git a/src/stlink-common.h b/src/stlink-common.h index 0330e624b..6f451f5b8 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -84,6 +84,7 @@ extern "C" { // TODO clean this up... #define STM32VL_CORE_ID 0x1ba01477 #define STM32L_CORE_ID 0x2ba01477 +#define STM32F3_CORE_ID 0x2ba01477 #define STM32F4_CORE_ID 0x2ba01477 #define STM32F0_CORE_ID 0xbb11477 #define CORE_M3_R1 0x1BA00477 @@ -98,6 +99,7 @@ extern "C" { #define STM32_CHIPID_F1_MEDIUM 0x410 #define STM32_CHIPID_F2 0x411 #define STM32_CHIPID_F1_LOW 0x412 +#define STM32_CHIPID_F3 0x422 #define STM32_CHIPID_F4 0x413 #define STM32_CHIPID_F1_HIGH 0x414 #define STM32_CHIPID_L1_MEDIUM 0x416 From 08872f834db4f4954490e614ca80e59fa6f95dbe Mon Sep 17 00:00:00 2001 From: Fabien Le Mentec Date: Sun, 25 Nov 2012 09:50:44 -0600 Subject: [PATCH 0190/1435] [ merge ] Andreas Seltenreich patches --- gdbserver/gdb-server.c | 35 +++++++++++++++++++++++++++++------ src/stlink-common.c | 6 +++--- 2 files changed, 32 insertions(+), 9 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 9d27ae48a..04490add6 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -1076,20 +1076,43 @@ int serve(stlink_t *sl, int port) { stm32_addr_t start = strtoul(s_start, NULL, 16); unsigned count = strtoul(s_count, NULL, 16); - for(unsigned int i = 0; i < count; i ++) { + if(start % 4) { + unsigned align_count = 4 - start % 4; + if (align_count > count) align_count = count; + for(unsigned int i = 0; i < align_count; i ++) { char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; uint8_t byte = strtoul(hex, NULL, 16); sl->q_buf[i] = byte; + } + stlink_write_mem8(sl, start, align_count); + start += align_count; + count -= align_count; + hexdata += 2*align_count; } - if((count % 4) == 0 && (start % 4) == 0) { - stlink_write_mem32(sl, start, count); - } else { - stlink_write_mem8(sl, start, count); + if(count - count % 4) { + unsigned aligned_count = count - count % 4; + + for(unsigned int i = 0; i < aligned_count; i ++) { + char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; + uint8_t byte = strtoul(hex, NULL, 16); + sl->q_buf[i] = byte; + } + stlink_write_mem32(sl, start, aligned_count); + count -= aligned_count; + start += aligned_count; + hexdata += 2*aligned_count; } + if(count) { + for(unsigned int i = 0; i < count; i ++) { + char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; + uint8_t byte = strtoul(hex, NULL, 16); + sl->q_buf[i] = byte; + } + stlink_write_mem8(sl, start, count); + } reply = strdup("OK"); - break; } diff --git a/src/stlink-common.c b/src/stlink-common.c index 66006f083..033cb5272 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -543,7 +543,7 @@ void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); if (len % 4 != 0) { fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return; + abort(); } sl->backend->write_mem32(sl, addr, len); } @@ -553,7 +553,7 @@ void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { if (len % 4 != 0) { // !!! never ever: fw gives just wrong values fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return; + abort(); } sl->backend->read_mem32(sl, addr, len); } @@ -563,7 +563,7 @@ void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour fprintf(stderr, "Error: Data length > 64: +%d byte.\n", len); - return; + abort(); } sl->backend->write_mem8(sl, addr, len); } From 7505f99b2a579534ddd69a1e4c476af4ed1e4a32 Mon Sep 17 00:00:00 2001 From: Fabien Le Mentec Date: Wed, 28 Nov 2012 12:48:50 -0600 Subject: [PATCH 0191/1435] [ merge ] patch from jgobat@gmail.com, add STM32F373 support --- src/stlink-common.c | 10 +++++----- src/stlink-common.h | 12 ++++++++++++ 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 033cb5272..1ac3d6029 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1085,7 +1085,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) val = stlink_read_debug32(sl, STM32L_FLASH_PECR) | (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3) { + } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1290,7 +1290,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); - } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3) { + } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { @@ -1633,7 +1633,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned val = stlink_read_debug32(sl, STM32L_FLASH_PECR) | (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3) { + } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { ILOG("Starting Flash write for VL/F0 core id\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { @@ -1732,7 +1732,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, count, 2); /* count (32 bits words) */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3) { + } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { size_t count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; @@ -1787,7 +1787,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3) { + } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { diff --git a/src/stlink-common.h b/src/stlink-common.h index 6f451f5b8..6496a10c2 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -100,6 +100,7 @@ extern "C" { #define STM32_CHIPID_F2 0x411 #define STM32_CHIPID_F1_LOW 0x412 #define STM32_CHIPID_F3 0x422 +#define STM32_CHIPID_F37x 0x432 #define STM32_CHIPID_F4 0x413 #define STM32_CHIPID_F1_HIGH 0x414 #define STM32_CHIPID_L1_MEDIUM 0x416 @@ -221,6 +222,17 @@ static const chip_params_t devices[] = { .bootrom_base = 0x1ffff000, .bootrom_size = 0x800 }, + { + // This is STK32F373VCT6 device from STM32 F373 eval board + // Support based on 303 above (37x and 30x have same memory map) + .chip_id = 0x432, + .description = "F3 device", + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, { .chip_id = 0x428, .description = "F1 High-density value line device", From 1c2828cc914260a57299461373bf835f90043863 Mon Sep 17 00:00:00 2001 From: Fabien Le Mentec Date: Thu, 27 Dec 2012 07:00:46 -0600 Subject: [PATCH 0192/1435] [ merge ] patch from fischermi@t-online.de, GDB server endless loop --- gdbserver/gdb-server.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 04490add6..1b5fc8401 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -650,7 +650,8 @@ int serve(stlink_t *sl, int port) { perror("listen"); return 1; } - + +start_again: stlink_force_debug(sl); stlink_reset(sl); init_code_breakpoints(sl); @@ -681,7 +682,7 @@ int serve(stlink_t *sl, int port) { int status = gdb_recv_packet(client, &packet); if(status < 0) { fprintf(stderr, "cannot recv: %d\n", status); - return 1; + goto start_again; } #ifdef DEBUG @@ -1220,7 +1221,9 @@ int serve(stlink_t *sl, int port) { int result = gdb_send_packet(client, reply); if(result != 0) { fprintf(stderr, "cannot send: %d\n", result); - return 1; + free(reply); + free(packet); + goto start_again; } free(reply); From acbfa3ad6fb9c464bfd998b2cdd01989af6a55ed Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Mon, 31 Dec 2012 23:09:30 +0000 Subject: [PATCH 0193/1435] bump version --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 1f00f3a80..daf7da20a 100644 --- a/configure.ac +++ b/configure.ac @@ -2,7 +2,7 @@ # Process this file with autoconf to produce a configure script. AC_PREREQ(2.61) -AC_INIT([stlink],[0.5.3],[davem@devkitpro.org]) +AC_INIT([stlink],[0.5.4],[davem@devkitpro.org]) AC_CONFIG_SRCDIR([src/stlink-common.c]) AC_CONFIG_LIBOBJ_DIR([src]) AM_INIT_AUTOMAKE([1.10]) From 79b413ca5b898982a79aa6673c44f9cd22f05c5b Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Mon, 31 Dec 2012 23:11:46 +0000 Subject: [PATCH 0194/1435] bump version --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index daf7da20a..df41a3dbd 100644 --- a/configure.ac +++ b/configure.ac @@ -2,7 +2,7 @@ # Process this file with autoconf to produce a configure script. AC_PREREQ(2.61) -AC_INIT([stlink],[0.5.4],[davem@devkitpro.org]) +AC_INIT([stlink],[0.5.5],[davem@devkitpro.org]) AC_CONFIG_SRCDIR([src/stlink-common.c]) AC_CONFIG_LIBOBJ_DIR([src]) AM_INIT_AUTOMAKE([1.10]) From da129b2ccdc00ff9a33c708718656935cc0efe82 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sun, 6 Jan 2013 15:33:48 +0000 Subject: [PATCH 0195/1435] fix write_flash size of len for 64bit --- src/stlink-common.c | 2 +- src/stlink-common.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 1ac3d6029..82d607089 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1415,7 +1415,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uns return 0; } -int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) { +int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { size_t off; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", diff --git a/src/stlink-common.h b/src/stlink-common.h index 6496a10c2..a2b73d93b 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -410,10 +410,10 @@ static const chip_params_t devices[] = { // unprocessed int stlink_erase_flash_mass(stlink_t* sl); - int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, unsigned length); + int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length); int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length); + int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); // PUBLIC uint32_t stlink_chip_id(stlink_t *sl); From f22b91b57a9dea96113946b810394e9fd1a524e5 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sun, 6 Jan 2013 15:34:54 +0000 Subject: [PATCH 0196/1435] file needs to be Binary for windows O_BINARY only defined on windows --- src/stlink-common.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 82d607089..2d7db142c 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -14,6 +14,10 @@ #include "stlink-common.h" #include "uglylogging.h" +#ifndef _WIN32 +#define O_BINARY 0 +#endif + #define LOG_TAG __FILE__ #define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) #define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) @@ -757,7 +761,7 @@ static int map_file(mapped_file_t* mf, const char* path) { int error = -1; struct stat st; - const int fd = open(path, O_RDONLY); + const int fd = open(path, O_RDONLY | O_BINARY); if (fd == -1) { fprintf(stderr, "open(%s) == -1\n", path); return -1; From 23884e8b42e035d35cfe0f1c969a9938516700a2 Mon Sep 17 00:00:00 2001 From: Dave Murphy Date: Sun, 6 Jan 2013 16:00:57 +0000 Subject: [PATCH 0197/1435] bump version --- configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index df41a3dbd..e8923ed36 100644 --- a/configure.ac +++ b/configure.ac @@ -2,7 +2,7 @@ # Process this file with autoconf to produce a configure script. AC_PREREQ(2.61) -AC_INIT([stlink],[0.5.5],[davem@devkitpro.org]) +AC_INIT([stlink],[0.5.6],[davem@devkitpro.org]) AC_CONFIG_SRCDIR([src/stlink-common.c]) AC_CONFIG_LIBOBJ_DIR([src]) AM_INIT_AUTOMAKE([1.10]) From 0ed390771c0ace3f048153591ec7476cc54b9392 Mon Sep 17 00:00:00 2001 From: A Sheaff Date: Wed, 9 Jan 2013 17:00:52 -0500 Subject: [PATCH 0198/1435] Clears DMA config registers for Discovery F4 board to allow flash programming. See texane/stlink issue #74. --- flash/main.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/flash/main.c b/flash/main.c index 4716b66e1..1d616ae95 100644 --- a/flash/main.c +++ b/flash/main.c @@ -123,6 +123,14 @@ int main(int ac, char** av) if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); +// Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 + memset(sl->q_buf,0,4); + for (int i=0;i<8;i++) { + stlink_write_mem32(sl,0x40026000+0x10+0x18*i,4); + stlink_write_mem32(sl,0x40026400+0x10+0x18*i,4); + stlink_write_mem32(sl,0x40026000+0x24+0x18*i,4); + stlink_write_mem32(sl,0x40026400+0x24+0x18*i,4); + } if (o.cmd == DO_WRITE) /* write */ { if ((o.addr >= sl->flash_base) && From 44445dd7b0f557bb9ff2fe22e0da17b03560c673 Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Tue, 12 Feb 2013 19:38:46 +0100 Subject: [PATCH 0199/1435] Fix byte count when doing unaligned memory read, fix issue #127 - when start is adjusted, count should also be adjusted, - then, count is rounded to the next multiple of word size. --- gdbserver/gdb-server.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 1b5fc8401..f92fc05f0 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -1056,9 +1056,9 @@ int serve(stlink_t *sl, int port) { unsigned count = strtoul(s_count, NULL, 16); unsigned adj_start = start % 4; + unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; - stlink_read_mem32(sl, start - adj_start, (count % 4 == 0) ? - count : count + 4 - (count % 4)); + stlink_read_mem32(sl, start - adj_start, count_rnd); reply = calloc(count * 2 + 1, 1); for(unsigned int i = 0; i < count; i++) { From 3569970998cb8c15acb7754c167c5f35dad70a72 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Wed, 6 Mar 2013 12:03:27 -0500 Subject: [PATCH 0200/1435] Revert "[ merge ] patch from fischermi@t-online.de, GDB server endless loop" This reverts commit 1c2828cc914260a57299461373bf835f90043863. --- gdbserver/gdb-server.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index f92fc05f0..5f0a43b68 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -650,8 +650,7 @@ int serve(stlink_t *sl, int port) { perror("listen"); return 1; } - -start_again: + stlink_force_debug(sl); stlink_reset(sl); init_code_breakpoints(sl); @@ -682,7 +681,7 @@ int serve(stlink_t *sl, int port) { int status = gdb_recv_packet(client, &packet); if(status < 0) { fprintf(stderr, "cannot recv: %d\n", status); - goto start_again; + return 1; } #ifdef DEBUG @@ -1221,9 +1220,7 @@ int serve(stlink_t *sl, int port) { int result = gdb_send_packet(client, reply); if(result != 0) { fprintf(stderr, "cannot send: %d\n", result); - free(reply); - free(packet); - goto start_again; + return 1; } free(reply); From 9bed540624ac45ff334917a51c564caa278d5833 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Wed, 6 Mar 2013 12:52:12 -0500 Subject: [PATCH 0201/1435] Add persistence support to gdb-server When started with -m, or connected with 'target extended-remote', the GDB server will not terminate upon disconnection from GDB, instead it will begin listening for conenctions again. Starting with extended-remote also has the advantage of allowing 'run' to be used to reset the target and begin again. Unfortunately, 'start' is not working properly, as it does not send a reset packet (R), so it complains when it tries to access memory before it is connected to the target. --- gdbserver/gdb-server.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 5f0a43b68..414ad8a7b 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -40,6 +40,11 @@ static const char hex[] = "0123456789abcdef"; static const char* current_memory_map = NULL; +/* Persistent mode flag. + * In persistent mode, server starts listening again + * on GDB disconnect. */ +int persistent = 0; + typedef struct _st_state_t { // things from command line, bleh int stlink_version; @@ -62,6 +67,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { {"stlink_version", required_argument, NULL, 's'}, {"stlinkv1", no_argument, NULL, '1'}, {"listen_port", required_argument, NULL, 'p'}, + {"multi", optional_argument, NULL, 'm'}, {0, 0, 0, 0}, }; const char * help_str = "%s - usage:\n\n" @@ -76,13 +82,16 @@ int parse_options(int argc, char** argv, st_state_t *st) { " -p 4242, --listen_port=1234\n" "\t\t\tSet the gdb server listen port. " "(default port: " STRINGIFY(DEFAULT_GDB_LISTEN_PORT) ")\n" + " -m, --multi\n" + "\t\t\tSet gdb server to extended mode.\n" + "\t\t\tst-util will continue listening for connections after disconnect.\n" ; int option_index = 0; int c; int q; - while ((c = getopt_long(argc, argv, "hv::d:s:1p:", long_options, &option_index)) != -1) { + while ((c = getopt_long(argc, argv, "hv::d:s:1p:m", long_options, &option_index)) != -1) { switch (c) { case 0: printf("XXXXX Shouldn't really normally come here, only if there's no corresponding option\n"); @@ -129,6 +138,9 @@ int parse_options(int argc, char** argv, st_state_t *st) { } st->listen_port = q; break; + case 'm': + persistent = 1; + break; } } @@ -177,7 +189,9 @@ int main(int argc, char** argv) { } #endif - while(serve(sl, state.listen_port) == 0); + do { + serve(sl, state.listen_port); + } while (persistent); #ifdef __MINGW32__ winsock_error: @@ -1189,6 +1203,12 @@ int serve(stlink_t *sl, int port) { * We do support that always. */ + /* + * Also, set to persistent mode + * to allow GDB disconnect. + */ + persistent = 1; + reply = strdup("OK"); break; @@ -1220,6 +1240,8 @@ int serve(stlink_t *sl, int port) { int result = gdb_send_packet(client, reply); if(result != 0) { fprintf(stderr, "cannot send: %d\n", result); + free(reply); + free(packet); return 1; } From 4d1ee4d97eb5d282833e542dfb88192240381ed4 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Wed, 6 Mar 2013 14:23:17 -0500 Subject: [PATCH 0202/1435] Move persistence flag to st_state_t It makes sense for it to be with all other state data. This meant passing the entire state struct into serve. --- gdbserver/gdb-server.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 414ad8a7b..8190e1061 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -40,11 +40,6 @@ static const char hex[] = "0123456789abcdef"; static const char* current_memory_map = NULL; -/* Persistent mode flag. - * In persistent mode, server starts listening again - * on GDB disconnect. */ -int persistent = 0; - typedef struct _st_state_t { // things from command line, bleh int stlink_version; @@ -52,10 +47,11 @@ typedef struct _st_state_t { char devicename[100]; int logging_level; int listen_port; + int persistent; } st_state_t; -int serve(stlink_t *sl, int port); +int serve(stlink_t *sl, st_state_t *st); char* make_memory_map(stlink_t *sl); @@ -139,7 +135,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { st->listen_port = q; break; case 'm': - persistent = 1; + st->persistent = 1; break; } } @@ -190,8 +186,8 @@ int main(int argc, char** argv) { #endif do { - serve(sl, state.listen_port); - } while (persistent); + serve(sl, &state); + } while (state.persistent); #ifdef __MINGW32__ winsock_error: @@ -639,7 +635,7 @@ static int flash_go(stlink_t *sl) { return error; } -int serve(stlink_t *sl, int port) { +int serve(stlink_t *sl, st_state_t *st) { int sock = socket(AF_INET, SOCK_STREAM, 0); if(sock < 0) { perror("socket"); @@ -653,7 +649,7 @@ int serve(stlink_t *sl, int port) { memset(&serv_addr,0,sizeof(struct sockaddr_in)); serv_addr.sin_family = AF_INET; serv_addr.sin_addr.s_addr = inet_addr("127.0.0.1"); - serv_addr.sin_port = htons(port); + serv_addr.sin_port = htons(st->listen_port); if(bind(sock, (struct sockaddr *) &serv_addr, sizeof(serv_addr)) < 0) { perror("bind"); @@ -670,7 +666,7 @@ int serve(stlink_t *sl, int port) { init_code_breakpoints(sl); init_data_watchpoints(sl); - printf("Listening at *:%d...\n", port); + printf("Listening at *:%d...\n", st->listen_port); int client = accept(sock, NULL, NULL); //signal (SIGINT, SIG_DFL); @@ -1207,7 +1203,7 @@ int serve(stlink_t *sl, int port) { * Also, set to persistent mode * to allow GDB disconnect. */ - persistent = 1; + st->persistent = 1; reply = strdup("OK"); From 2216d28452f5e97088fbfd4bd6f6daf187d5e53a Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Wed, 6 Mar 2013 16:15:15 -0500 Subject: [PATCH 0203/1435] Add SIGINT handler for stlink cleanup SIGINT causes st-util to immediately exit, without closing the open stlink. This leaves devices (at least the F4 Discovery) in a state where they are unable to reset. st-util could still connect and control them, but a power cycle was required before they could reset on their own. A signal handler is added for SIGINT, which performs cleanup and closing of the open stlink device, allowing it to function normally on disconnect. --- gdbserver/gdb-server.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 8190e1061..32f0d8baf 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -36,6 +36,8 @@ //Allways update the FLASH_PAGE before each use, by calling stlink_calculate_pagesize #define FLASH_PAGE (sl->flash_pgsz) +stlink_t *connected_stlink = NULL; + static const char hex[] = "0123456789abcdef"; static const char* current_memory_map = NULL; @@ -54,6 +56,16 @@ typedef struct _st_state_t { int serve(stlink_t *sl, st_state_t *st); char* make_memory_map(stlink_t *sl); +static void cleanup(int signal __attribute__((unused))) { + if (connected_stlink) { + /* Switch back to mass storage mode before closing. */ + stlink_run(connected_stlink); + stlink_exit_debug_mode(connected_stlink); + stlink_close(connected_stlink); + } + + exit(1); +} int parse_options(int argc, char** argv, st_state_t *st) { static struct option long_options[] = { @@ -172,6 +184,9 @@ int main(int argc, char** argv) { break; } + connected_stlink = sl; + signal(SIGINT, &cleanup); + printf("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); sl->verbose=0; From 69fecdca633e72547e90245d327d5d92c0488be8 Mon Sep 17 00:00:00 2001 From: Ian Griffiths <6thimage@gmail.com> Date: Wed, 20 Mar 2013 13:01:49 +0000 Subject: [PATCH 0204/1435] Added lock state check to stlink_erase_flash_page. On the STM32L152 processor, the erase fails for the first page as the lock is already disabled (with the unlocking code causing the lock to become re-enabled). This commit adds checking of the lock state and will only unlock if necessary. --- src/stlink-common.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 2d7db142c..4c662fbcf 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1023,26 +1023,30 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) uint32_t val; - /* disable pecr protection */ - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); - - /* check pecr.pelock is cleared */ + /* check if the locks are set */ val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 0)) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return -1; - } + if((val & (1<<0))||(val & (1<<1))) { + /* disable pecr protection */ + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); + + /* check pecr.pelock is cleared */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + if (val & (1 << 0)) { + WLOG("pecr.pelock not clear (%#x)\n", val); + return -1; + } - /* unlock program memory */ - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); + /* unlock program memory */ + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); - /* check pecr.prglock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 1)) { - WLOG("pecr.prglock not clear (%#x)\n", val); - return -1; + /* check pecr.prglock is cleared */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + if (val & (1 << 1)) { + WLOG("pecr.prglock not clear (%#x)\n", val); + return -1; + } } /* unused: unlock the option byte block */ From 0b2c10568773f84e06e65258359653d85cb4754e Mon Sep 17 00:00:00 2001 From: Ian Griffiths <6thimage@gmail.com> Date: Thu, 21 Mar 2013 16:28:15 +0000 Subject: [PATCH 0205/1435] Limited DMA clearing to STM32F4, removed fatal error for flash loading. Commit 0ed3907 added the clearing of DMA registers that was preventing programming (see issue #74), however it uses hardcoded addresses of the DMA registers on the STM32F4. This seems to prevent the flashing and verification on STM32L1, as the registers only partly cover the range zeroed. So the DMA clearing has been limited to the STM32F4 microcontroller. Additionally, sometimes, typically directly after erases, a 'flash loader run error' will occur that terminates the writing. This is not necessary, as the writing is successfully performed by page writing (line 1581 onwards of stlink-common.c), and so has been returned to a error message (see issue #112). There is a comment on line 1574 (added by Uwe Bonnes in commit 0164043f) that this may happen on blank devices, and so the fatal error message is the incorrect response. --- flash/main.c | 3 +++ src/stlink-common.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/flash/main.c b/flash/main.c index 1d616ae95..110c2964d 100644 --- a/flash/main.c +++ b/flash/main.c @@ -124,6 +124,8 @@ int main(int ac, char** av) stlink_enter_swd_mode(sl); // Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 + if (sl->chip_id == STM32_CHIPID_F4) + { memset(sl->q_buf,0,4); for (int i=0;i<8;i++) { stlink_write_mem32(sl,0x40026000+0x10+0x18*i,4); @@ -131,6 +133,7 @@ int main(int ac, char** av) stlink_write_mem32(sl,0x40026000+0x24+0x18*i,4); stlink_write_mem32(sl,0x40026400+0x24+0x18*i,4); } + } if (o.cmd == DO_WRITE) /* write */ { if ((o.addr >= sl->flash_base) && diff --git a/src/stlink-common.c b/src/stlink-common.c index 4c662fbcf..a60f2b670 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1779,7 +1779,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } if (i >= WAIT_ROUNDS) { - fatal("flash loader run error\n"); + ELOG("flash loader run error\n"); return -1; } From 8df5b3be5edd177ecbbc355fff976b6afba20962 Mon Sep 17 00:00:00 2001 From: Fabien Le Mentec Date: Mon, 1 Apr 2013 15:36:52 -0500 Subject: [PATCH 0206/1435] [ update ] bind gdb server on INADDR_ANY, as requested by thomas@popp.ws --- gdbserver/gdb-server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 32f0d8baf..ad7ce6570 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -663,7 +663,7 @@ int serve(stlink_t *sl, st_state_t *st) { struct sockaddr_in serv_addr; memset(&serv_addr,0,sizeof(struct sockaddr_in)); serv_addr.sin_family = AF_INET; - serv_addr.sin_addr.s_addr = inet_addr("127.0.0.1"); + serv_addr.sin_addr.s_addr = INADDR_ANY; serv_addr.sin_port = htons(st->listen_port); if(bind(sock, (struct sockaddr *) &serv_addr, sizeof(serv_addr)) < 0) { From e5772dffbf7c1e9dbe6b9d6b5a013bf3d487ce5f Mon Sep 17 00:00:00 2001 From: Jack Peel Date: Wed, 3 Apr 2013 16:43:13 -0700 Subject: [PATCH 0207/1435] Add Support for STM32L1xx Medium Plus and High density Devices Using reference RM0038 Rev 7 The flash size register moved and the values in the registers changed their meaning Note that Medium Plus and High density deives have the same device ID, but only the Medium Plus definition is used in the code (the High comes along for free) --- src/stlink-common.c | 28 +++++++++++++++++++--------- src/stlink-common.h | 11 +++++++++++ 2 files changed, 30 insertions(+), 9 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index a60f2b670..9603cb264 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -18,6 +18,7 @@ #define O_BINARY 0 #endif + #define LOG_TAG __FILE__ #define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) #define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) @@ -451,6 +452,14 @@ int stlink_load_device_params(stlink_t *sl) { sl->flash_size = 0x100000; /* Use maximum, User must care!*/ } else if (sl->chip_id == STM32_CHIPID_F4) { sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID + } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_MEDIUM_PLUS) { + uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0x1; + // 0 is 384k and 1 is 256k + if ( flash_size == 0 ) { + sl->flash_size = 384 * 1024; + } else { + sl->flash_size = 256 * 1024; + } } else { uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff; sl->flash_size = flash_size * 1024; @@ -833,6 +842,7 @@ int stlink_fwrite_sram size_t off; mapped_file_t mf = MAPPED_FILE_INITIALIZER; + if (map_file(&mf, path) == -1) { fprintf(stderr, "map_file() == -1\n"); return -1; @@ -853,7 +863,6 @@ int stlink_fwrite_sram fprintf(stderr, "unaligned addr or size\n"); goto on_error; } - /* do the copy by 1k blocks */ for (off = 0; off < mf.len; off += 1024) { size_t size = 1024; @@ -894,7 +903,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) int error = -1; size_t off; int num_empty = 0; - unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff; + unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS)?0:0xff; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -1019,7 +1028,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif - } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { + } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) { uint32_t val; @@ -1125,7 +1134,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS ) { /* erase each page */ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1295,7 +1304,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { /* stm32l */ + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS ) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { @@ -1535,7 +1544,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } //STM32F4END - else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { + else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) { /* use fast word write. todo: half page. */ uint32_t val; @@ -1691,7 +1700,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ int err; unsigned int num_empty = 0, index; - unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM)?0:0xff; + unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS)?0:0xff; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { ELOG("map_file() == -1\n"); @@ -1729,7 +1738,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1774,6 +1783,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons #define WAIT_ROUNDS 1000 /* wait until done (reaches breakpoint) */ for (i = 0; i < WAIT_ROUNDS; i++) { + usleep(10); if (is_core_halted(sl)) break; } @@ -1784,7 +1794,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } /* check written byte count */ - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; diff --git a/src/stlink-common.h b/src/stlink-common.h index a2b73d93b..f0141aa06 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -104,6 +104,8 @@ extern "C" { #define STM32_CHIPID_F4 0x413 #define STM32_CHIPID_F1_HIGH 0x414 #define STM32_CHIPID_L1_MEDIUM 0x416 +#define STM32_CHIPID_L1_MEDIUM_PLUS 0x436 +#define STM32_CHIPID_L1_HIGH 0x436 #define STM32_CHIPID_F1_CONN 0x418 #define STM32_CHIPID_F1_VL_MEDIUM 0x420 #define STM32_CHIPID_F1_VL_HIGH 0x428 @@ -193,6 +195,15 @@ static const chip_params_t devices[] = { .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000 }, + { + .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS, + .description = "L1 Medium-Plus-density device", + .flash_size_reg = 0x1ff800CC, + .flash_pagesize = 0x100, + .sram_size = 0x8000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, { .chip_id = 0x418, .description = "F1 Connectivity line device", From 55b9ecd36c35669510b70cfaac53098e8a786587 Mon Sep 17 00:00:00 2001 From: Jack Peel Date: Fri, 5 Apr 2013 09:06:26 -0700 Subject: [PATCH 0208/1435] Add support for the STM32L1 Medium density device flash size calculation In devices before "Rev X" the flash size register is 0 so we assume 128k Note that "Rev X" is a LATER revision than "Rev Y" and others that might seem like they are later! --- src/stlink-common.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index 9603cb264..05ee12cd3 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -452,6 +452,14 @@ int stlink_load_device_params(stlink_t *sl) { sl->flash_size = 0x100000; /* Use maximum, User must care!*/ } else if (sl->chip_id == STM32_CHIPID_F4) { sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID + } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { + // if the flash size is zero, we assume it is 128k, if not we calculate the real value + uint32_t flash_size = stlink_read_debug32(sl,params->flash_size_reg) & 0xffff; + if ( flash_size == 0 ) { + sl->flash_size = 128 * 1024; + } else { + sl->flash_size = flash_size * 1024; + } } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_MEDIUM_PLUS) { uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0x1; // 0 is 384k and 1 is 256k From 04c142c69b0075a2004896d7046fe78fd015a02c Mon Sep 17 00:00:00 2001 From: Jack Peel Date: Fri, 5 Apr 2013 17:55:19 -0700 Subject: [PATCH 0209/1435] Add SIGTERM signal handler to also call cleanup When stopping st-util under Eclipse as an external tool the st-util receives a SIGTERM signal, and would not return the device to usb mass storage mode. This change now calls cleanup in the SIGTERM handler too!! --- gdbserver/gdb-server.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index ad7ce6570..f9c06f983 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -67,6 +67,8 @@ static void cleanup(int signal __attribute__((unused))) { exit(1); } + + int parse_options(int argc, char** argv, st_state_t *st) { static struct option long_options[] = { {"help", no_argument, NULL, 'h'}, @@ -186,6 +188,7 @@ int main(int argc, char** argv) { connected_stlink = sl; signal(SIGINT, &cleanup); + signal(SIGTERM, &cleanup); printf("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); From 821a21482f93e65376fd99032da3f5e8db79951b Mon Sep 17 00:00:00 2001 From: Andrey Yurovsky Date: Sat, 13 Apr 2013 22:32:09 -0700 Subject: [PATCH 0210/1435] Don't use magic numbers for chip_id field The chip IDs are defined up top and those macros are used throughout the code so let's remove the magic numbers in .chip_id so that everything is using the macros. No functionality changes, just a find/replace. --- src/stlink-common.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/src/stlink-common.h b/src/stlink-common.h index f0141aa06..68f5082e4 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -140,7 +140,7 @@ extern "C" { // also the Reference manuals. (flash size reg is normally in ref man) static const chip_params_t devices[] = { { // table 2, PM0063 - .chip_id = 0x410, + .chip_id = STM32_CHIPID_F1_MEDIUM, .description = "F1 Medium-density device", .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, @@ -149,7 +149,7 @@ static const chip_params_t devices[] = { .bootrom_size = 0x800 }, { // table 1, PM0059 - .chip_id = 0x411, + .chip_id = STM32_CHIPID_F2, .description = "F2 device", .flash_size_reg = 0, /* no flash size reg found in the docs! */ .flash_pagesize = 0x20000, @@ -158,7 +158,7 @@ static const chip_params_t devices[] = { .bootrom_size = 0x7800 }, { // PM0063 - .chip_id = 0x412, + .chip_id = STM32_CHIPID_F1_LOW, .description = "F1 Low-density device", .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, @@ -167,7 +167,7 @@ static const chip_params_t devices[] = { .bootrom_size = 0x800 }, { - .chip_id = 0x413, + .chip_id = STM32_CHIPID_F4, .description = "F4 device", .flash_size_reg = 0x1FFF7A10, //RM0090 error same as unique ID .flash_pagesize = 0x4000, @@ -176,7 +176,7 @@ static const chip_params_t devices[] = { .bootrom_size = 0x7800 }, { - .chip_id = 0x414, + .chip_id = STM32_CHIPID_F1_HIGH, .description = "F1 High-density device", .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -187,7 +187,7 @@ static const chip_params_t devices[] = { { // This ignores the EEPROM! (and uses the page erase size, // not the sector write protection...) - .chip_id = 0x416, + .chip_id = STM32_CHIPID_L1_MEDIUM, .description = "L1 Med-density device", .flash_size_reg = 0x1ff8004c, .flash_pagesize = 0x100, @@ -205,7 +205,7 @@ static const chip_params_t devices[] = { .bootrom_size = 0x1000 }, { - .chip_id = 0x418, + .chip_id = STM32_CHIPID_F1_CONN, .description = "F1 Connectivity line device", .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -214,7 +214,7 @@ static const chip_params_t devices[] = { .bootrom_size = 0x4800 }, { - .chip_id = 0x420, + .chip_id = STM32_CHIPID_F1_VL_MEDIUM, .description = "F1 Medium-density Value Line device", .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, @@ -225,7 +225,7 @@ static const chip_params_t devices[] = { { // This is STK32F303VCT6 device from STM32 F3 Discovery board. // Support based on DM00043574.pdf (RM0316) document. - .chip_id = 0x422, + .chip_id = STM32_CHIPID_F3, .description = "F3 device", .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, @@ -236,7 +236,7 @@ static const chip_params_t devices[] = { { // This is STK32F373VCT6 device from STM32 F373 eval board // Support based on 303 above (37x and 30x have same memory map) - .chip_id = 0x432, + .chip_id = STM32_CHIPID_F37x, .description = "F3 device", .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, @@ -245,7 +245,7 @@ static const chip_params_t devices[] = { .bootrom_size = 0x800 }, { - .chip_id = 0x428, + .chip_id = STM32_CHIPID_F1_VL_HIGH, .description = "F1 High-density value line device", .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -254,7 +254,7 @@ static const chip_params_t devices[] = { .bootrom_size = 0x800 }, { - .chip_id = 0x430, + .chip_id = STM32_CHIPID_F1_XL, .description = "F1 XL-density device", .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -265,7 +265,7 @@ static const chip_params_t devices[] = { { //Use this as an example for mapping future chips: //RM0091 document was used to find these paramaters - .chip_id = 0x440, + .chip_id = STM32_CHIPID_F0, .description = "F0 device", .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 From 90d380e8d15ce5a7d1e4190794e212e26cbe6a2b Mon Sep 17 00:00:00 2001 From: Alexey Cherevatenko Date: Tue, 23 Apr 2013 15:17:09 +0300 Subject: [PATCH 0211/1435] Environment STLINK_DEVICE allow to choose ST_LINK --- src/stlink-usb.c | 43 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 37 insertions(+), 6 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 277431a87..825ee0aea 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -729,15 +729,46 @@ stlink_t* stlink_open_usb(const int verbose) { goto on_error; } - slu->usb_handle = libusb_open_device_with_vid_pid(slu->libusb_ctx, USB_ST_VID, USB_STLINK_32L_PID); - if (slu->usb_handle == NULL) { - slu->usb_handle = libusb_open_device_with_vid_pid(slu->libusb_ctx, USB_ST_VID, USB_STLINK_PID); - if (slu->usb_handle == NULL) { - WLOG("Couldn't find any ST-Link/V2 devices\n"); + libusb_device **list; + int cnt = libusb_get_device_list(slu->libusb_ctx, &list); + struct libusb_device_descriptor desc; + int devBus =0; + int devAddr=0; + + char *device = getenv("STLINK_DEVICE"); + if (device) { + char *c = strchr(device,':'); + if (c==NULL) { + WLOG("STLINK_DEVICE must be : format\n"); goto on_error; } - slu->protocoll = 1; + devBus=atoi(device); + *c++=0; + devAddr=atoi(c); + ILOG("bus %03d dev %03d\n",devBus, devAddr); + } + while (cnt){ + cnt--; + libusb_get_device_descriptor( list[cnt], &desc ); + if (desc.idVendor!=USB_ST_VID) continue; + if (devBus && devAddr) + if ((libusb_get_bus_number(list[cnt])!=devBus) || (libusb_get_device_address(list[cnt])!=devAddr)) continue; + if (desc.idProduct == USB_STLINK_32L_PID) break; + if (desc.idProduct == USB_STLINK_PID) slu->protocoll = 1; break; + } + + if (cnt==0){ + WLOG("Couldn't find %s ST-Link/V2 devices\n",(devBus && devAddr)?"matched":"any"); + goto on_error; + } else { + if( libusb_open(list[cnt], &slu->usb_handle) !=0){ + WLOG("Couldn't open ST-Link/V2 device %03d:%03d\n",libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); + goto on_error; + } } + + libusb_free_device_list(list, 1); + if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { int r; From 74138a7f93f3f66d03ddebe243f6b7db4a90b9a6 Mon Sep 17 00:00:00 2001 From: Andrew 'Necromant' Andrianov Date: Mon, 6 May 2013 01:50:35 +0400 Subject: [PATCH 0212/1435] Add STlink terminal draft Signed-off-by: Andrew 'Necromant' Andrianov --- Makefile.am | 10 ++- src/st-term.c | 174 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 182 insertions(+), 2 deletions(-) create mode 100644 src/st-term.c diff --git a/Makefile.am b/Makefile.am index a315dd726..9c99297ec 100644 --- a/Makefile.am +++ b/Makefile.am @@ -2,18 +2,20 @@ AUTOMAKE_OPTIONS = subdir-objects -bin_PROGRAMS = st-flash st-util +bin_PROGRAMS = st-flash st-util st-term noinst_LIBRARIES = libstlink.a st_flash_SOURCES = flash/main.c +st_term_SOURCES = src/st-term.c st_util_SOURCES = gdbserver/gdb-remote.c gdbserver/gdb-remote.h gdbserver/gdb-server.c mingw/mingw.c mingw/mingw.h CFILES = \ src/stlink-common.c \ src/stlink-usb.c \ src/stlink-sg.c \ - src/uglylogging.c + src/uglylogging.c \ + src/st-term.c HFILES = \ src/stlink-common.h \ @@ -33,5 +35,9 @@ st_flash_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_src st_util_LDADD = libstlink.a st_util_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_srcdir)/mingw +st_term_LDADD = libstlink.a +st_term_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_srcdir)/mingw + + EXTRA_DIST = autogen.sh diff --git a/src/st-term.c b/src/st-term.c new file mode 100644 index 000000000..f442d56fd --- /dev/null +++ b/src/st-term.c @@ -0,0 +1,174 @@ +#include +#include "stlink-common.h" + +#define STLINKY_MAGIC 0xDEADF00D + +struct stlinky { + stlink_t *sl; + uint32_t off; + size_t bufsize; +}; + +void dump_qbuf(stlink_t* s) +{ + printf("== 0x%x\n", *(uint32_t*)s->q_buf); +} + +/* Detects stlinky in RAM, returns handler */ +struct stlinky* stlinky_detect(stlink_t* sl) +{ + static const uint32_t sram_base = 0x20000000; + struct stlinky* st = malloc(sizeof(struct stlinky)); + st->sl = sl; + printf("sram: 0x%x bytes @ 0x%x\n", sl->sram_base, sl->sram_size); + uint32_t off; + for (off = 0; off < sl->sram_size; off += 4) { + stlink_read_mem32(sl, sram_base + off, 4); + if ( STLINKY_MAGIC== *(uint32_t*) sl->q_buf) + { + printf("stlinky detected at 0x%x\n", sram_base + off); + st->off = sram_base + off; + stlink_read_mem32(sl, st->off + 4, 4); + st->bufsize = (size_t) *(unsigned char*) sl->q_buf; + printf("stlinky buffer size 0x%zu (%hhx)\n", st->bufsize); + return st; + } + } + return NULL; +} + + +size_t stlinky_rx(struct stlinky *st, char* buffer) +{ + unsigned char tx = 0; + while(tx == 0) { + stlink_read_mem32(st->sl, st->off+4, 4); + tx = (unsigned char) st->sl->q_buf[1]; + } + size_t rs = tx + (4 - (tx % 4)); /* voodoo */ + stlink_read_mem32(st->sl, st->off+8, rs); + printf(st->sl->q_buf); + *st->sl->q_buf=0x0; + stlink_write_mem8(st->sl, st->off+5, 1); +} + + +int main(int ac, char** av) { + stlink_t* sl; + reg regs; + + /* unused */ + ac = ac; + av = av; + + sl = stlink_open_usb(10); + if (sl != NULL) { + printf("ST Link terminal :: Created by Necromant\n"); + stlink_version(sl); + + printf("mode before doing anything: %d\n", stlink_current_mode(sl)); + + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { + printf("-- exit_dfu_mode\n"); + stlink_exit_dfu_mode(sl); + } + + printf("-- enter_swd_mode\n"); + stlink_enter_swd_mode(sl); + + printf("-- mode after entering swd mode: %d\n", stlink_current_mode(sl)); + + printf("-- chip id: %#x\n", sl->chip_id); + printf("-- core_id: %#x\n", sl->core_id); + + cortex_m3_cpuid_t cpuid; + stlink_cpu_id(sl, &cpuid); + printf("cpuid:impl_id = %0#x, variant = %#x\n", cpuid.implementer_id, cpuid.variant); + printf("cpuid:part = %#x, rev = %#x\n", cpuid.part, cpuid.revision); + + stlink_reset(sl); + stlink_force_debug(sl); + stlink_run(sl); + stlink_status(sl); + /* wait for device to boot */ + + sleep(1); + + struct stlinky *st = stlinky_detect(sl); + if (st == NULL) + { + printf("stlinky magic not found in sram :("); + } + + while(1) { + stlinky_rx(st, NULL); + } + //sleep(90); + + printf("-- read_sram\n"); + // static const uint32_t sram_base = 0x8000000; + // uint32_t off; + //for (off = 0; off < 16; off += 4) + // stlink_read_mem32(sl, sram_base + off, 4); + + //printf("FP_CTRL\n"); + //stlink_read_mem32(sl, CM3_REG_FP_CTRL, 4); + + // no idea what reg this is.. */ + // stlink_read_mem32(sl, 0xe000ed90, 4); + // no idea what register this is... + // stlink_read_mem32(sl, 0xe000edf0, 4); + // offset 0xC into TIM11 register? TIMx_DIER? + // stlink_read_mem32(sl, 0x4001100c, 4); */ + + /* Test 32 bit Write */ + write_uint32(sl->q_buf,0x01234567); + stlink_write_mem32(sl,0x200000a8,4); +#if 0 + write_uint32(sl->q_buf,0x89abcdef); + stlink_write_mem32(sl,0x200000ac, 4); + stlink_read_mem32(sl, 0x200000a8, 4); + stlink_read_mem32(sl, 0x200000ac, 4); + + /* Test 8 bit write */ + write_uint32(sl->q_buf,0x01234567); + stlink_write_mem8(sl,0x200001a8,3); + write_uint32(sl->q_buf,0x89abcdef); + stlink_write_mem8(sl, 0x200001ac, 3); + stlink_read_mem32(sl, 0x200001a8, 4); + stlink_read_mem32(sl, 0x200001ac, 4); + + printf("-- status\n"); + stlink_status(sl); + + printf("-- reset\n"); + stlink_reset(sl); + stlink_force_debug(sl); + /* Test reg write*/ + stlink_write_reg(sl, 0x01234567, 3); + stlink_write_reg(sl, 0x89abcdef, 4); + stlink_write_reg(sl, 0x12345678, 15); + for (off = 0; off < 21; off += 1) + stlink_read_reg(sl, off, ®s); + + + stlink_read_all_regs(sl, ®s); + + printf("-- status\n"); + stlink_status(sl); + + printf("-- step\n"); + stlink_step(sl); + + printf("-- run\n"); + stlink_run(sl); + + printf("-- exit_debug_mode\n"); +#endif + stlink_exit_debug_mode(sl); + + stlink_close(sl); + } + + return 0; +} From d59be1f42793a92430bde44188e8b5e08febd08e Mon Sep 17 00:00:00 2001 From: Andrew 'Necromant' Andrianov Date: Mon, 6 May 2013 08:59:25 +0400 Subject: [PATCH 0213/1435] working st-term proof-of-concept. Period. Signed-off-by: Andrew 'Necromant' Andrianov --- src/st-term.c | 263 ++++++++++++++++++++++++++------------------------ 1 file changed, 138 insertions(+), 125 deletions(-) diff --git a/src/st-term.c b/src/st-term.c index f442d56fd..7f045b6e4 100644 --- a/src/st-term.c +++ b/src/st-term.c @@ -1,4 +1,13 @@ #include +/* According to POSIX.1-2001 */ +#include +#include +#include +#include +#include +#include +#include +#include #include "stlink-common.h" #define STLINKY_MAGIC 0xDEADF00D @@ -9,20 +18,16 @@ struct stlinky { size_t bufsize; }; -void dump_qbuf(stlink_t* s) -{ - printf("== 0x%x\n", *(uint32_t*)s->q_buf); -} -/* Detects stlinky in RAM, returns handler */ -struct stlinky* stlinky_detect(stlink_t* sl) +/* Detects stlinky in RAM, returns handler */ +struct stlinky* stlinky_detect(stlink_t* sl) { - static const uint32_t sram_base = 0x20000000; + static const uint32_t sram_base = 0x20000000; struct stlinky* st = malloc(sizeof(struct stlinky)); st->sl = sl; printf("sram: 0x%x bytes @ 0x%x\n", sl->sram_base, sl->sram_size); - uint32_t off; - for (off = 0; off < sl->sram_size; off += 4) { + uint32_t off; + for (off = 0; off < sl->sram_size; off += 4) { stlink_read_mem32(sl, sram_base + off, 4); if ( STLINKY_MAGIC== *(uint32_t*) sl->q_buf) { @@ -30,13 +35,19 @@ struct stlinky* stlinky_detect(stlink_t* sl) st->off = sram_base + off; stlink_read_mem32(sl, st->off + 4, 4); st->bufsize = (size_t) *(unsigned char*) sl->q_buf; - printf("stlinky buffer size 0x%zu (%hhx)\n", st->bufsize); + printf("stlinky buffer size 0x%zu\n", st->bufsize); return st; } } return NULL; } +int stlinky_canrx(struct stlinky *st) +{ + stlink_read_mem32(st->sl, st->off+4, 4); + unsigned char tx = (unsigned char) st->sl->q_buf[1]; + return (int) tx; +} size_t stlinky_rx(struct stlinky *st, char* buffer) { @@ -47,128 +58,130 @@ size_t stlinky_rx(struct stlinky *st, char* buffer) } size_t rs = tx + (4 - (tx % 4)); /* voodoo */ stlink_read_mem32(st->sl, st->off+8, rs); - printf(st->sl->q_buf); + memcpy(buffer, st->sl->q_buf, (size_t) tx); *st->sl->q_buf=0x0; stlink_write_mem8(st->sl, st->off+5, 1); + return (size_t) tx; +} + +size_t stlinky_tx(struct stlinky *st, char* buffer, size_t sz) +{ + unsigned char rx = 1; + while(rx != 0) { + stlink_read_mem32(st->sl, st->off+4, 4); + rx = (unsigned char) st->sl->q_buf[2]; + } + memcpy(st->sl->q_buf, buffer, sz); + size_t rs = sz + (4 - (sz % 4)); /* voodoo */ + stlink_write_mem32(st->sl, st->off+8+st->bufsize, rs); + *st->sl->q_buf=(unsigned char) sz; + stlink_write_mem8(st->sl, st->off+6, 1); + return (size_t) rx; } +int kbhit() +{ + struct timeval tv; + fd_set fds; + tv.tv_sec = 0; + tv.tv_usec = 0; + FD_ZERO(&fds); + FD_SET(STDIN_FILENO, &fds); //STDIN_FILENO is 0 + select(STDIN_FILENO+1, &fds, NULL, NULL, &tv); + return FD_ISSET(STDIN_FILENO, &fds); +} -int main(int ac, char** av) { - stlink_t* sl; - reg regs; - - /* unused */ - ac = ac; - av = av; - - sl = stlink_open_usb(10); - if (sl != NULL) { - printf("ST Link terminal :: Created by Necromant\n"); - stlink_version(sl); - - printf("mode before doing anything: %d\n", stlink_current_mode(sl)); - - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { - printf("-- exit_dfu_mode\n"); - stlink_exit_dfu_mode(sl); - } - - printf("-- enter_swd_mode\n"); - stlink_enter_swd_mode(sl); - - printf("-- mode after entering swd mode: %d\n", stlink_current_mode(sl)); - - printf("-- chip id: %#x\n", sl->chip_id); - printf("-- core_id: %#x\n", sl->core_id); - - cortex_m3_cpuid_t cpuid; - stlink_cpu_id(sl, &cpuid); - printf("cpuid:impl_id = %0#x, variant = %#x\n", cpuid.implementer_id, cpuid.variant); - printf("cpuid:part = %#x, rev = %#x\n", cpuid.part, cpuid.revision); - - stlink_reset(sl); - stlink_force_debug(sl); - stlink_run(sl); - stlink_status(sl); - /* wait for device to boot */ - - sleep(1); - - struct stlinky *st = stlinky_detect(sl); - if (st == NULL) +void nonblock(int state) +{ + struct termios ttystate; + + //get the terminal state + tcgetattr(STDIN_FILENO, &ttystate); + + if (state==1) + { + //turn off canonical mode + ttystate.c_lflag &= ~ICANON; + ttystate.c_lflag &= ~ECHO; + //minimum of number input read. + ttystate.c_cc[VMIN] = 1; + } + else if (state==0) { - printf("stlinky magic not found in sram :("); + //turn on canonical mode + ttystate.c_lflag |= ICANON | ECHO; } + //set the terminal attributes. + tcsetattr(STDIN_FILENO, TCSANOW, &ttystate); + +} + +static int keep_running = 1; +void cleanup(int dummy) +{ + keep_running = 0; + printf("\n\nGot a signal - terminating\n"); +} - while(1) { - stlinky_rx(st, NULL); + +int main(int ac, char** av) { + stlink_t* sl; + + /* unused */ + ac = ac; + av = av; + sl = stlink_open_usb(10); + if (sl != NULL) { + printf("ST-Linky proof-of-concept terminal :: Created by Necromant for lulz\n"); + stlink_version(sl); + stlink_enter_swd_mode(sl); + printf("chip id: %#x\n", sl->chip_id); + printf("core_id: %#x\n", sl->core_id); + + cortex_m3_cpuid_t cpuid; + stlink_cpu_id(sl, &cpuid); + printf("cpuid:impl_id = %0#x, variant = %#x\n", cpuid.implementer_id, cpuid.variant); + printf("cpuid:part = %#x, rev = %#x\n", cpuid.part, cpuid.revision); + + stlink_reset(sl); + stlink_force_debug(sl); + stlink_run(sl); + stlink_status(sl); + + /* wait for device to boot */ + /* TODO: Make timeout adjustable via command line */ + sleep(1); + + struct stlinky *st = stlinky_detect(sl); + if (st == NULL) + { + printf("stlinky magic not found in sram :("); + } + char* rxbuf = malloc(st->bufsize); + char* txbuf = malloc(st->bufsize); + size_t tmp; + nonblock(1); + int fd = fileno(stdin); + int saved_flags = fcntl(fd, F_GETFL); + fcntl(fd, F_SETFL, saved_flags & ~O_NONBLOCK); + signal(SIGINT, cleanup); + printf("Entering interactive terminal. CTRL+C to exit\n"); + while(1) { + if (stlinky_canrx(st)) { + tmp = stlinky_rx(st, rxbuf); + fwrite(rxbuf,tmp,1,stdout); + fflush(stdout); + } + if (kbhit()) { + tmp = read(fd, txbuf, st->bufsize); + stlinky_tx(st,txbuf,tmp); + } + if (!keep_running) + break; + } + nonblock(0); + stlink_exit_debug_mode(sl); + stlink_close(sl); } - //sleep(90); - - printf("-- read_sram\n"); - // static const uint32_t sram_base = 0x8000000; - // uint32_t off; - //for (off = 0; off < 16; off += 4) - // stlink_read_mem32(sl, sram_base + off, 4); - - //printf("FP_CTRL\n"); - //stlink_read_mem32(sl, CM3_REG_FP_CTRL, 4); - - // no idea what reg this is.. */ - // stlink_read_mem32(sl, 0xe000ed90, 4); - // no idea what register this is... - // stlink_read_mem32(sl, 0xe000edf0, 4); - // offset 0xC into TIM11 register? TIMx_DIER? - // stlink_read_mem32(sl, 0x4001100c, 4); */ - - /* Test 32 bit Write */ - write_uint32(sl->q_buf,0x01234567); - stlink_write_mem32(sl,0x200000a8,4); -#if 0 - write_uint32(sl->q_buf,0x89abcdef); - stlink_write_mem32(sl,0x200000ac, 4); - stlink_read_mem32(sl, 0x200000a8, 4); - stlink_read_mem32(sl, 0x200000ac, 4); - - /* Test 8 bit write */ - write_uint32(sl->q_buf,0x01234567); - stlink_write_mem8(sl,0x200001a8,3); - write_uint32(sl->q_buf,0x89abcdef); - stlink_write_mem8(sl, 0x200001ac, 3); - stlink_read_mem32(sl, 0x200001a8, 4); - stlink_read_mem32(sl, 0x200001ac, 4); - - printf("-- status\n"); - stlink_status(sl); - - printf("-- reset\n"); - stlink_reset(sl); - stlink_force_debug(sl); - /* Test reg write*/ - stlink_write_reg(sl, 0x01234567, 3); - stlink_write_reg(sl, 0x89abcdef, 4); - stlink_write_reg(sl, 0x12345678, 15); - for (off = 0; off < 21; off += 1) - stlink_read_reg(sl, off, ®s); - - - stlink_read_all_regs(sl, ®s); - - printf("-- status\n"); - stlink_status(sl); - - printf("-- step\n"); - stlink_step(sl); - - printf("-- run\n"); - stlink_run(sl); - - printf("-- exit_debug_mode\n"); -#endif - stlink_exit_debug_mode(sl); - - stlink_close(sl); - } - - return 0; + return 0; } From 32e2fceec615c973754e7f86c14f8f5b7b046323 Mon Sep 17 00:00:00 2001 From: Andrew 'Necromant' Andrianov Date: Mon, 6 May 2013 09:54:10 +0400 Subject: [PATCH 0214/1435] st-term: handle two signals and fixups Signed-off-by: Andrew 'Necromant' Andrianov --- src/st-term.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/src/st-term.c b/src/st-term.c index 7f045b6e4..f4643933c 100644 --- a/src/st-term.c +++ b/src/st-term.c @@ -35,7 +35,7 @@ struct stlinky* stlinky_detect(stlink_t* sl) st->off = sram_base + off; stlink_read_mem32(sl, st->off + 4, 4); st->bufsize = (size_t) *(unsigned char*) sl->q_buf; - printf("stlinky buffer size 0x%zu\n", st->bufsize); + printf("stlinky buffer size 0x%zu \n", st->bufsize); return st; } } @@ -117,10 +117,16 @@ void nonblock(int state) } static int keep_running = 1; +static int sigcount=0; void cleanup(int dummy) { + sigcount++; keep_running = 0; - printf("\n\nGot a signal - terminating\n"); + printf("\n\nGot a signal\n"); + if (sigcount==2) { + printf("\n\nGot a second signal - bailing out\n"); + exit(1); + } } @@ -155,7 +161,8 @@ int main(int ac, char** av) { struct stlinky *st = stlinky_detect(sl); if (st == NULL) { - printf("stlinky magic not found in sram :("); + printf("stlinky magic not found in sram :(\n"); + goto bailout; } char* rxbuf = malloc(st->bufsize); char* txbuf = malloc(st->bufsize); @@ -165,7 +172,7 @@ int main(int ac, char** av) { int saved_flags = fcntl(fd, F_GETFL); fcntl(fd, F_SETFL, saved_flags & ~O_NONBLOCK); signal(SIGINT, cleanup); - printf("Entering interactive terminal. CTRL+C to exit\n"); + printf("Entering interactive terminal. CTRL+C to exit\n\n\n"); while(1) { if (stlinky_canrx(st)) { tmp = stlinky_rx(st, rxbuf); @@ -179,6 +186,7 @@ int main(int ac, char** av) { if (!keep_running) break; } + bailout: nonblock(0); stlink_exit_debug_mode(sl); stlink_close(sl); From 4e09a06bfc9a95b3d4bd2f71ce7ebdf4bacf672a Mon Sep 17 00:00:00 2001 From: kevin Date: Tue, 7 May 2013 13:33:58 +0100 Subject: [PATCH 0215/1435] Ensure that the USB device search succeeds if the matched device is at index 0. --- src/stlink-usb.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 825ee0aea..d57458428 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -757,9 +757,9 @@ stlink_t* stlink_open_usb(const int verbose) { if (desc.idProduct == USB_STLINK_PID) slu->protocoll = 1; break; } - if (cnt==0){ - WLOG("Couldn't find %s ST-Link/V2 devices\n",(devBus && devAddr)?"matched":"any"); - goto on_error; + if (cnt < 0) { + WLOG ("Couldn't find %s ST-Link/V2 devices\n",(devBus && devAddr)?"matched":"any"); + goto on_error; } else { if( libusb_open(list[cnt], &slu->usb_handle) !=0){ WLOG("Couldn't open ST-Link/V2 device %03d:%03d\n",libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); From bffa1b5259002229fe60ad8f392b5d9e902112a3 Mon Sep 17 00:00:00 2001 From: Jonas Danielsson Date: Mon, 10 Jun 2013 11:32:01 +0200 Subject: [PATCH 0216/1435] gui: add initial gtk implementation --- gui/Makefile.am | 30 ++ gui/stlink-gui.c | 950 ++++++++++++++++++++++++++++++++++++++++++++++ gui/stlink-gui.h | 93 +++++ gui/stlink-gui.ui | 666 ++++++++++++++++++++++++++++++++ 4 files changed, 1739 insertions(+) create mode 100644 gui/Makefile.am create mode 100644 gui/stlink-gui.c create mode 100644 gui/stlink-gui.h create mode 100644 gui/stlink-gui.ui diff --git a/gui/Makefile.am b/gui/Makefile.am new file mode 100644 index 000000000..19c067278 --- /dev/null +++ b/gui/Makefile.am @@ -0,0 +1,30 @@ +bin_PROGRAMS = stlink-gui + +stlink_gui_SOURCES = \ + stlink-gui.c \ + stlink-gui.h + +stlink_gui_CPPFLAGS = \ + -I$(top_srcdir) \ + $(AM_CPPFLAGS) \ + -I$(top_builddir)/src \ + @GTK_CFLAGS@ + +stlink_gui_CFLAGS = \ + $(WARN_CFLAGS) \ + $(AM_CFLAGS) \ + -DSTLINK_UI_DIR="\"$(uidir)\"" + +stlink_gui_LDFLAGS = \ + $(AM_LDFLAGS) + +stlink_gui_LDADD = \ + $(INTLLIBS) \ + $(top_builddir)/libstlink.a \ + @GTK_LIBS@ + +uidir = $(pkgdatadir)/ui +ui_DATA = stlink-gui.ui +EXTRA_DIST = $(ui_DATA) + +-include $(top_srcdir)/git.mk diff --git a/gui/stlink-gui.c b/gui/stlink-gui.c new file mode 100644 index 000000000..756d7666c --- /dev/null +++ b/gui/stlink-gui.c @@ -0,0 +1,950 @@ +#include +#include +#include +#include + +#include "stlink-common.h" +#include "stlink-gui.h" + +#define MEM_READ_SIZE 1024 + +#ifndef G_VALUE_INIT +#define G_VALUE_INIT {0, {{0}}} +#endif + +G_DEFINE_TYPE (STlinkGUI, stlink_gui, G_TYPE_OBJECT); + +static void +stlink_gui_dispose (GObject *gobject) +{ + G_OBJECT_CLASS (stlink_gui_parent_class)->dispose (gobject); +} + +static void +stlink_gui_finalize (GObject *gobject) +{ + G_OBJECT_CLASS (stlink_gui_parent_class)->finalize (gobject); +} + +static void +stlink_gui_class_init (STlinkGUIClass *klass) +{ + GObjectClass *gobject_class = G_OBJECT_CLASS (klass); + + gobject_class->dispose = stlink_gui_dispose; + gobject_class->finalize = stlink_gui_finalize; +} + +static void +stlink_gui_init (STlinkGUI *self) +{ + self->sl = NULL; + self->filename = NULL; + + self->progress.activity_mode = FALSE; + self->progress.fraction = 0; + + self->flash_mem.memory = NULL; + self->flash_mem.size = 0; + self->flash_mem.base = 0; + + self->file_mem.memory = NULL; + self->file_mem.size = 0; + self->file_mem.base = 0; +} + +static gboolean +set_info_error_message_idle (STlinkGUI *gui) +{ + if (gui->error_message != NULL) { + gchar *markup; + + markup = g_markup_printf_escaped ("%s", gui->error_message); + gtk_label_set_markup (gui->infolabel, markup); + gtk_info_bar_set_message_type (gui->infobar, GTK_MESSAGE_ERROR); + gtk_widget_show (GTK_WIDGET (gui->infobar)); + + g_free (markup); + g_free (gui->error_message); + gui->error_message = NULL; + } + return FALSE; +} + +static void +stlink_gui_set_info_error_message (STlinkGUI *gui, const gchar *message) +{ + gui->error_message = g_strdup (message); + g_idle_add ((GSourceFunc) set_info_error_message_idle, gui); +} + +static void +stlink_gui_set_sensitivity (STlinkGUI *gui, gboolean sensitivity) +{ + gtk_widget_set_sensitive (GTK_WIDGET (gui->open_button), sensitivity); + + if (sensitivity && gui->sl) + gtk_widget_set_sensitive (GTK_WIDGET (gui->disconnect_button), sensitivity); + + if (sensitivity && !gui->sl) + gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), sensitivity); + + if (sensitivity && gui->sl && gui->filename) + gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), sensitivity); +} + +static void +mem_view_init_headers (GtkTreeView *view) +{ + GtkCellRenderer *renderer; + gint i; + + g_return_if_fail (view != NULL); + + renderer = gtk_cell_renderer_text_new (); + gtk_tree_view_insert_column_with_attributes (view, + -1, + "Address", + renderer, + "text", + 0, /* column */ + NULL); + for (i = 0; i < 4; i++) { + gchar *label; + + label = g_strdup_printf ("%X", i * 4); + renderer = gtk_cell_renderer_text_new (); + gtk_tree_view_insert_column_with_attributes (view, + -1, + label, + renderer, + "text", + (i + 1), /* column */ + NULL); + g_free (label); + } + + for (i = 0; i < 5; i++) { + GtkTreeViewColumn *column = gtk_tree_view_get_column (view, i); + gtk_tree_view_column_set_expand (column, TRUE); + } +} + +static void +mem_view_add_as_hex (GtkListStore *store, + GtkTreeIter *iter, + gint column, + guint32 value) +{ + gchar *hex_str; + + hex_str = g_strdup_printf ("0x%08X", value); + gtk_list_store_set (store, iter, column, hex_str, -1); + g_free (hex_str); +} + +static void +mem_view_add_buffer (GtkListStore *store, + GtkTreeIter *iter, + guint32 address, + guchar *buffer, + gint len) +{ + guint32 *word; + gint i, step; + gint column = 0; + + step = sizeof (*word); + + for (i = 0; i < len; i += step) { + word = (guint *) &buffer[i]; + + if (column == 0) { + /* new row */ + gtk_list_store_append (store, iter); + + /* add address */ + mem_view_add_as_hex (store, iter, column, (address + i)); + } + mem_view_add_as_hex (store, iter, (column + 1), *word); + column = (column + 1) % step; + } +} + +static guint32 +hexstr_to_guint32 (const gchar *str, GError **err) +{ + guint32 val; + gchar *end_ptr; + + val = strtoul (str, &end_ptr, 16); + if ((errno == ERANGE && val == LONG_MAX) || (errno != 0 && val == 0)) { + g_set_error (err, + g_quark_from_string ("hextou32"), + 1, + "Invalid hexstring"); + return LONG_MAX; + } + if (end_ptr == str) { + g_set_error (err, + g_quark_from_string ("hextou32"), + 2, + "Invalid hexstring"); + return LONG_MAX; + } + return val; +} + + +static void +stlink_gui_update_mem_view (STlinkGUI *gui, struct mem_t *mem, GtkTreeView *view) { + GtkListStore *store; + GtkTreeIter iter; + + store = GTK_LIST_STORE (gtk_tree_view_get_model (view)); + + mem_view_add_buffer (store, + &iter, + mem->base, + mem->memory, + mem->size); + + gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); + gtk_progress_bar_set_fraction (gui->progress.bar, 0); + stlink_gui_set_sensitivity (gui, TRUE); +} + +static gboolean +stlink_gui_update_devmem_view (STlinkGUI *gui) +{ + stlink_gui_update_mem_view (gui, &gui->flash_mem, gui->devmem_treeview); + return FALSE; +} + + +static void +stlink_gui_populate_devmem_view (STlinkGUI *gui) +{ + guint off; + stm32_addr_t addr; + + g_return_if_fail (gui != NULL); + g_return_if_fail (gui->sl != NULL); + + addr = gui->sl->flash_base; + + if (gui->flash_mem.memory) { + g_free (gui->flash_mem.memory); + } + gui->flash_mem.memory = g_malloc (gui->sl->flash_size); + gui->flash_mem.size = gui->sl->flash_size; + gui->flash_mem.base = gui->sl->flash_base; + + for (off = 0; off < gui->sl->flash_size; off += MEM_READ_SIZE) { + guint n_read = MEM_READ_SIZE; + + if (off + MEM_READ_SIZE > gui->sl->flash_size) { + n_read = gui->sl->flash_size - off; + + /* align if needed */ + if (n_read & 3) { + n_read = (n_read + 4) & ~(3); + } + } + /* reads to sl->q_buf */ + stlink_read_mem32(gui->sl, addr + off, n_read); + if (gui->sl->q_len < 0) { + stlink_gui_set_info_error_message (gui, "Failed to read memory"); + g_free (gui->flash_mem.memory); + gui->flash_mem.memory = NULL; + return; + } + memcpy (gui->flash_mem.memory + off, gui->sl->q_buf, n_read); + gui->progress.fraction = (gdouble) (off + n_read) / gui->sl->flash_size; + } + g_idle_add ((GSourceFunc) stlink_gui_update_devmem_view, gui); +} + +static gboolean +stlink_gui_update_filemem_view (STlinkGUI *gui) +{ + gchar *basename; + + basename = g_path_get_basename (gui->filename); + gtk_notebook_set_tab_label_text (gui->notebook, + GTK_WIDGET (gtk_notebook_get_nth_page (gui->notebook, 1)), + basename); + g_free (basename); + + stlink_gui_update_mem_view (gui, &gui->file_mem, gui->filemem_treeview); + + return FALSE; +} + +static gpointer +stlink_gui_populate_filemem_view (STlinkGUI *gui) +{ + guchar buffer[MEM_READ_SIZE]; + GFile *file; + GFileInfo *file_info; + GInputStream *input_stream; + gint off; + GError *err = NULL; + + g_return_val_if_fail (gui != NULL, NULL); + g_return_val_if_fail (gui->filename != NULL, NULL); + + file = g_file_new_for_path (gui->filename); + input_stream = G_INPUT_STREAM (g_file_read (file, NULL, &err)); + if (err) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + goto out; + } + + file_info = g_file_input_stream_query_info (G_FILE_INPUT_STREAM (input_stream), + G_FILE_ATTRIBUTE_STANDARD_SIZE, NULL, &err); + if (err) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + goto out_input; + } + if (gui->file_mem.memory) { + g_free (gui->file_mem.memory); + } + gui->file_mem.size = g_file_info_get_size (file_info); + gui->file_mem.memory = g_malloc (gui->file_mem.size); + + for (off = 0; off < gui->file_mem.size; off += MEM_READ_SIZE) { + guint n_read = MEM_READ_SIZE; + + if (off + MEM_READ_SIZE > gui->file_mem.size) { + n_read = gui->file_mem.size - off; + } + + if (g_input_stream_read (G_INPUT_STREAM (input_stream), + &buffer, n_read, NULL, &err) == -1) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + goto out_input; + } + memcpy (gui->file_mem.memory + off, buffer, n_read); + gui->progress.fraction = (gdouble) (off + n_read) / gui->file_mem.size; + } + g_idle_add ((GSourceFunc) stlink_gui_update_filemem_view, gui); + + out_input: + g_object_unref (input_stream); + out: + g_object_unref (file); + return NULL; +} + +static void mem_jmp (GtkTreeView *view, + GtkEntry *entry, + guint32 base_addr, + gsize size, + GError **err) +{ + GtkTreeModel *model; + guint32 jmp_addr; + GtkTreeIter iter; + + jmp_addr = hexstr_to_guint32 (gtk_entry_get_text (entry), err); + if (err && *err) { + return; + } + + if (jmp_addr < base_addr || jmp_addr > base_addr + size) { + g_set_error (err, + g_quark_from_string ("mem_jmp"), + 1, + "Invalid address"); + return; + } + + model = gtk_tree_view_get_model (view); + if (!model) { + return; + } + + if (gtk_tree_model_get_iter_first (model, &iter)) { + do { + guint32 addr; + GValue value = G_VALUE_INIT; + GError *err = NULL; + + gtk_tree_model_get_value (model, &iter, 0, &value); + if (G_VALUE_HOLDS_STRING (&value)) { + addr = hexstr_to_guint32 (g_value_get_string (&value), &err); + if (!err) { + if (addr == (jmp_addr & 0xFFFFFFF0)) { + GtkTreeSelection *selection; + GtkTreePath *path; + + selection = gtk_tree_view_get_selection (view); + path = gtk_tree_model_get_path (model, &iter); + + gtk_tree_selection_select_iter (selection, &iter); + gtk_tree_view_scroll_to_cell (view, + path, + NULL, + TRUE, + 0.0, + 0.0); + gtk_tree_path_free (path); + } + } + } + g_value_unset (&value); + } while (gtk_tree_model_iter_next (model, &iter)); + } +} + +static void +devmem_jmp_cb (GtkWidget *widget, gpointer data) +{ + STlinkGUI *gui; + GError *err = NULL; + + gui = STLINK_GUI (data); + + mem_jmp (gui->devmem_treeview, + gui->devmem_jmp_entry, + gui->sl->flash_base, + gui->sl->flash_size, + &err); + + if (err) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + } +} + +static void +filemem_jmp_cb (GtkWidget *widget, gpointer data) +{ + STlinkGUI *gui; + GError *err = NULL; + + gui = STLINK_GUI (data); + + g_return_if_fail (gui->filename != NULL); + + mem_jmp (gui->filemem_treeview, + gui->filemem_jmp_entry, + 0, + gui->file_mem.size, + &err); + + if (err) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + } +} + +static gchar * +dev_format_chip_id (guint32 chip_id) +{ + gint i; + + for (i = 0; i < sizeof (devices) / sizeof (devices[0]); i++) { + if (chip_id == devices[i].chip_id) { + return g_strdup (devices[i].description); + } + } + return g_strdup_printf ("0x%x", chip_id); +} + +static gchar * +dev_format_mem_size (gsize flash_size) +{ + return g_strdup_printf ("%u kB", flash_size / 1024); +} + + +static void +stlink_gui_set_connected (STlinkGUI *gui) +{ + gchar *tmp_str; + GtkListStore *store; + GtkTreeIter iter; + + gtk_statusbar_push (gui->statusbar, + gtk_statusbar_get_context_id (gui->statusbar, "conn"), + "Connected"); + + gtk_widget_set_sensitive (GTK_WIDGET (gui->device_frame), TRUE); + gtk_widget_set_sensitive (GTK_WIDGET (gui->devmem_box), TRUE); + gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), FALSE); + + if (gui->filename) { + gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), TRUE); + } + + tmp_str = dev_format_chip_id (gui->sl->chip_id); + gtk_label_set_text (gui->chip_id_label, tmp_str); + g_free (tmp_str); + + tmp_str = g_strdup_printf ("0x%x", gui->sl->core_id); + gtk_label_set_text (gui->core_id_label, tmp_str); + g_free (tmp_str); + + tmp_str = dev_format_mem_size (gui->sl->flash_size); + gtk_label_set_text (gui->flash_size_label, tmp_str); + g_free (tmp_str); + + tmp_str = dev_format_mem_size (gui->sl->sram_size); + gtk_label_set_text (gui->ram_size_label, tmp_str); + g_free (tmp_str); + + tmp_str = g_strdup_printf ("0x%08X", gui->sl->flash_base); + gtk_entry_set_text (gui->devmem_jmp_entry, tmp_str); + gtk_editable_set_editable (GTK_EDITABLE (gui->devmem_jmp_entry), TRUE); + g_free (tmp_str); + + store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->devmem_treeview)); + if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) { + gtk_list_store_clear (store); + } + + stlink_gui_set_sensitivity (gui, FALSE); + gtk_notebook_set_current_page (gui->notebook, PAGE_DEVMEM); + gtk_widget_show (GTK_WIDGET (gui->progress.bar)); + gtk_progress_bar_set_text (gui->progress.bar, "Reading memory"); + + g_thread_new ("devmem", (GThreadFunc) stlink_gui_populate_devmem_view, gui); +} + +static void +connect_button_cb (GtkWidget *widget, gpointer data) +{ + STlinkGUI *gui; + gint i; + + gui = STLINK_GUI (data); + + if (gui->sl != NULL) + return; + + /* try version 1 then version 2 */ + gui->sl = stlink_v1_open(0); + if (gui->sl == NULL) { + gui->sl = stlink_open_usb(0); + } + if (gui->sl == NULL) { + stlink_gui_set_info_error_message (gui, "Failed to connect to STLink."); return; + } + + /* code below taken from flash/main.c, refactoring might be in order */ + if (stlink_current_mode(gui->sl) == STLINK_DEV_DFU_MODE) + stlink_exit_dfu_mode(gui->sl); + + if (stlink_current_mode(gui->sl) != STLINK_DEV_DEBUG_MODE) + stlink_enter_swd_mode(gui->sl); + + /* Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 */ + if (gui->sl->chip_id == STM32_CHIPID_F4) { + memset(gui->sl->q_buf, 0, 4); + for (i = 0; i < 8; i++) { + stlink_write_mem32(gui->sl, 0x40026000 + 0x10 + 0x18 * i, 4); + stlink_write_mem32(gui->sl, 0x40026400 + 0x10 + 0x18 * i, 4); + stlink_write_mem32(gui->sl, 0x40026000 + 0x24 + 0x18 * i, 4); + stlink_write_mem32(gui->sl, 0x40026400 + 0x24 + 0x18 * i, 4); + } + } + stlink_gui_set_connected (gui); +} + +static void stlink_gui_set_disconnected (STlinkGUI *gui) +{ + gtk_statusbar_push (gui->statusbar, + gtk_statusbar_get_context_id (gui->statusbar, "conn"), + "Disconnected"); + + gtk_widget_set_sensitive (GTK_WIDGET (gui->device_frame), FALSE); + gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), FALSE); + gtk_widget_set_sensitive (GTK_WIDGET (gui->disconnect_button), FALSE); + gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), TRUE); +} + +static void +disconnect_button_cb (GtkWidget *widget, gpointer data) +{ + STlinkGUI *gui; + + gui = STLINK_GUI (data); + + if (gui->sl != NULL) { + stlink_exit_debug_mode(gui->sl); + stlink_close(gui->sl); + gui->sl = NULL; + } + stlink_gui_set_disconnected (gui); +} + + +static void +stlink_gui_open_file (STlinkGUI *gui) +{ + GtkWidget *dialog; + GtkListStore *store; + GtkTreeIter iter; + + dialog = gtk_file_chooser_dialog_new ("Open file", + gui->window, + GTK_FILE_CHOOSER_ACTION_OPEN, + GTK_STOCK_CANCEL, GTK_RESPONSE_CANCEL, + GTK_STOCK_OPEN, GTK_RESPONSE_ACCEPT, + NULL); + + if (gtk_dialog_run (GTK_DIALOG (dialog)) == GTK_RESPONSE_ACCEPT) { + gui->filename = + gtk_file_chooser_get_filename (GTK_FILE_CHOOSER (dialog)); + + store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->filemem_treeview)); + if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) { + gtk_list_store_clear (store); + } + + stlink_gui_set_sensitivity (gui, FALSE); + gtk_notebook_set_current_page (gui->notebook, PAGE_FILEMEM); + gtk_widget_show (GTK_WIDGET (gui->progress.bar)); + gtk_progress_bar_set_text (gui->progress.bar, "Reading file"); + g_thread_new ("file", (GThreadFunc) stlink_gui_populate_filemem_view, gui); + } + gtk_widget_destroy (dialog); +} + +static void +open_button_cb (GtkWidget *widget, gpointer data) +{ + STlinkGUI *gui; + + gui = STLINK_GUI (data); + + stlink_gui_open_file (gui); +} + +static gboolean +stlink_gui_write_flash_update (STlinkGUI *gui) +{ + stlink_gui_set_sensitivity (gui, TRUE); + gui->progress.activity_mode = FALSE; + gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); + + return FALSE; +} + +static void +stlink_gui_write_flash (STlinkGUI *gui) +{ + g_return_if_fail (gui->sl != NULL); + g_return_if_fail (gui->filename != NULL); + + if (stlink_fwrite_flash(gui->sl, gui->filename, gui->sl->flash_base) < 0) { + stlink_gui_set_info_error_message (gui, "Failed to write to flash"); + } + + g_idle_add ((GSourceFunc) stlink_gui_write_flash_update, gui); +} + +static void +flash_button_cb (GtkWidget *widget, gpointer data) +{ + STlinkGUI *gui; + gchar *tmp_str; + guint32 address; + gint result; + GError *err = NULL; + + gui = STLINK_GUI (data); + g_return_if_fail (gui->sl != NULL); + + if (!g_strcmp0 (gtk_entry_get_text (gui->flash_dialog_entry), "")) { + tmp_str = g_strdup_printf ("0x%08X", gui->sl->flash_base); + gtk_entry_set_text (gui->flash_dialog_entry, tmp_str); + g_free (tmp_str); + } + + result = gtk_dialog_run (gui->flash_dialog); + if (result == GTK_RESPONSE_OK) { + address = hexstr_to_guint32 (gtk_entry_get_text (gui->flash_dialog_entry), + &err); + if (err) { + stlink_gui_set_info_error_message (gui, err->message); + } else { + if (address > gui->sl->flash_base + gui->sl->flash_size || + address < gui->sl->flash_base) { + stlink_gui_set_info_error_message (gui, "Invalid address"); + } + else if (address + gui->file_mem.size > + gui->sl->flash_base + gui->sl->flash_size) { + stlink_gui_set_info_error_message (gui, "Binary overwrites flash"); + } else { + stlink_gui_set_sensitivity (gui, FALSE); + gtk_progress_bar_set_text (gui->progress.bar, + "Writing to flash"); + gui->progress.activity_mode = TRUE; + gtk_widget_show (GTK_WIDGET (gui->progress.bar)); + g_thread_new ("flash", + (GThreadFunc) stlink_gui_write_flash, gui); + } + } + } +} + +static gboolean +progress_pulse_timeout (STlinkGUI *gui) { + if (gui->progress.activity_mode) { + gtk_progress_bar_pulse (gui->progress.bar); + } else { + gtk_progress_bar_set_fraction (gui->progress.bar, gui->progress.fraction); + } + return TRUE; +} + +static void +notebook_switch_page_cb (GtkNotebook *notebook, + GtkWidget *widget, + guint page_num, + gpointer data) +{ + STlinkGUI *gui; + + gui = STLINK_GUI (data); + + if (page_num == 1) { + if (gui->filename == NULL) { + stlink_gui_open_file (gui); + } + } +} + +static void +dnd_received_cb (GtkWidget *widget, + GdkDragContext *context, + gint x, + gint y, + GtkSelectionData *selection_data, + guint target_type, + guint time, + gpointer data) +{ + GFile *file_uri; + gchar **file_list; + const guchar *file_data; + STlinkGUI *gui = STLINK_GUI (data); + GtkListStore *store; + GtkTreeIter iter; + + if (selection_data != NULL && + gtk_selection_data_get_length (selection_data) > 0) { + switch (target_type) { + case TARGET_FILENAME: + + if (gui->filename) { + g_free (gui->filename); + } + + file_data = gtk_selection_data_get_data (selection_data); + file_list = g_strsplit ((gchar *)file_data, "\r\n", 0); + + file_uri = g_file_new_for_uri (file_list[0]); + gui->filename = g_file_get_path (file_uri); + + g_strfreev (file_list); + g_object_unref (file_uri); + + + store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->devmem_treeview)); + if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) { + gtk_list_store_clear (store); + } + + stlink_gui_set_sensitivity (gui, FALSE); + gtk_notebook_set_current_page (gui->notebook, PAGE_FILEMEM); + gtk_widget_show (GTK_WIDGET (gui->progress.bar)); + gtk_progress_bar_set_text (gui->progress.bar, "Reading file"); + g_thread_new ("file", (GThreadFunc) stlink_gui_populate_filemem_view, gui); + break; + } + } + gtk_drag_finish (context, + TRUE, + gdk_drag_context_get_suggested_action (context) == GDK_ACTION_MOVE, + time); +} + +void +stlink_gui_init_dnd (STlinkGUI *gui) +{ + GtkTargetEntry target_list[] = { + { "text/uri-list", 0, TARGET_FILENAME }, + }; + + gtk_drag_dest_set (GTK_WIDGET (gui->window), + GTK_DEST_DEFAULT_ALL, + target_list, + G_N_ELEMENTS (target_list), + GDK_ACTION_COPY); + + g_signal_connect (gui->window, "drag-data-received", + G_CALLBACK (dnd_received_cb), gui); +} + +static void +stlink_gui_build_ui (STlinkGUI *gui) { + GtkBuilder *builder; + GtkListStore *devmem_store; + GtkListStore *filemem_store; + + builder = gtk_builder_new (); + if (!gtk_builder_add_from_file (builder, STLINK_UI_DIR "/stlink-gui.ui", NULL)) { + /* woot */ + } + + gui->window = GTK_WINDOW (gtk_builder_get_object (builder, "window")); + g_signal_connect (G_OBJECT (gui->window), "destroy", + G_CALLBACK (gtk_main_quit), NULL); + + /* set up toolutton clicked callbacks */ + gui->open_button = + GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "open_button")); + g_signal_connect (G_OBJECT (gui->open_button), "clicked", + G_CALLBACK (open_button_cb), gui); + + gui->connect_button = + GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "connect_button")); + g_signal_connect (G_OBJECT (gui->connect_button), "clicked", + G_CALLBACK (connect_button_cb), gui); + + gui->disconnect_button = + GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "disconnect_button")); + g_signal_connect (G_OBJECT (gui->disconnect_button), "clicked", + G_CALLBACK (disconnect_button_cb), gui); + + gui->flash_button = + GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "flash_button")); + g_signal_connect (G_OBJECT (gui->flash_button), "clicked", + G_CALLBACK (flash_button_cb), gui); + + gui->devmem_treeview = + GTK_TREE_VIEW (gtk_builder_get_object (builder, "devmem_treeview")); + gtk_tree_view_set_rules_hint (gui->devmem_treeview, TRUE); + mem_view_init_headers (gui->devmem_treeview); + devmem_store = gtk_list_store_new (5, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING); + gtk_tree_view_set_model (gui->devmem_treeview, GTK_TREE_MODEL (devmem_store)); + g_object_unref (devmem_store); + + gui->filemem_treeview = + GTK_TREE_VIEW (gtk_builder_get_object (builder, "filemem_treeview")); + gtk_tree_view_set_rules_hint (gui->filemem_treeview, TRUE); + mem_view_init_headers (gui->filemem_treeview); + filemem_store = gtk_list_store_new (5, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING); + gtk_tree_view_set_model (gui->filemem_treeview, GTK_TREE_MODEL (filemem_store)); + g_object_unref (filemem_store); + + gui->core_id_label = + GTK_LABEL (gtk_builder_get_object (builder, "core_id_value")); + + gui->chip_id_label = + GTK_LABEL (gtk_builder_get_object (builder, "chip_id_value")); + + gui->flash_size_label = + GTK_LABEL (gtk_builder_get_object (builder, "flash_size_value")); + + gui->ram_size_label = + GTK_LABEL (gtk_builder_get_object (builder, "ram_size_value")); + + gui->device_frame = + GTK_FRAME (gtk_builder_get_object (builder, "device_frame")); + + gui->notebook = + GTK_NOTEBOOK (gtk_builder_get_object (builder, "mem_notebook")); + g_signal_connect (gui->notebook, "switch-page", + G_CALLBACK (notebook_switch_page_cb), gui); + + gui->devmem_box = + GTK_BOX (gtk_builder_get_object (builder, "devmem_box")); + + gui->filemem_box = + GTK_BOX (gtk_builder_get_object (builder, "filemem_box")); + + gui->devmem_jmp_entry = + GTK_ENTRY (gtk_builder_get_object (builder, "devmem_jmp_entry")); + g_signal_connect (gui->devmem_jmp_entry, "activate", + G_CALLBACK (devmem_jmp_cb), gui); + + gui->filemem_jmp_entry = + GTK_ENTRY (gtk_builder_get_object (builder, "filemem_jmp_entry")); + g_signal_connect (gui->filemem_jmp_entry, "activate", + G_CALLBACK (filemem_jmp_cb), gui); + gtk_editable_set_editable (GTK_EDITABLE (gui->filemem_jmp_entry), TRUE); + + gui->progress.bar = + GTK_PROGRESS_BAR (gtk_builder_get_object (builder, "progressbar")); + gtk_progress_bar_set_show_text (gui->progress.bar, TRUE); + gui->progress.timer = g_timeout_add (100, + (GSourceFunc) progress_pulse_timeout, + gui); + + gui->statusbar = + GTK_STATUSBAR (gtk_builder_get_object (builder, "statusbar")); + + gui->infobar = + GTK_INFO_BAR (gtk_builder_get_object (builder, "infobar")); + gtk_info_bar_add_button (gui->infobar, GTK_STOCK_OK, GTK_RESPONSE_OK); + gui->infolabel = GTK_LABEL (gtk_label_new ("")); + gtk_container_add (GTK_CONTAINER (gtk_info_bar_get_content_area (gui->infobar)), + GTK_WIDGET (gui->infolabel)); + g_signal_connect (gui->infobar, "response", G_CALLBACK (gtk_widget_hide), NULL); + + /* flash dialog */ + gui->flash_dialog = + GTK_DIALOG (gtk_builder_get_object (builder, "flash_dialog")); + g_signal_connect_swapped (gui->flash_dialog, "response", + G_CALLBACK (gtk_widget_hide), gui->flash_dialog); + + gui->flash_dialog_ok = + GTK_BUTTON (gtk_builder_get_object (builder, "flash_dialog_ok_button")); + + gui->flash_dialog_cancel = + GTK_BUTTON (gtk_builder_get_object (builder, "flash_dialog_cancel_button")); + + gui->flash_dialog_entry = + GTK_ENTRY (gtk_builder_get_object (builder, "flash_dialog_entry")); + + /* make it so */ + gtk_widget_show_all (GTK_WIDGET (gui->window)); + gtk_widget_hide (GTK_WIDGET (gui->infobar)); + gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); + + stlink_gui_set_disconnected (gui); +} + +int +main (int argc, char **argv) +{ + STlinkGUI *gui; + + gtk_init (&argc, &argv); + + gui = g_object_new (STLINK_TYPE_GUI, NULL); + stlink_gui_build_ui (gui); + stlink_gui_init_dnd (gui); + + gtk_main (); + + return 0; +} diff --git a/gui/stlink-gui.h b/gui/stlink-gui.h new file mode 100644 index 000000000..a91c869ac --- /dev/null +++ b/gui/stlink-gui.h @@ -0,0 +1,93 @@ + +#ifndef __STLINK_GUI_H__ +#define __STLINK_GUI_H__ + +#include + +#define STLINK_TYPE_GUI (stlink_gui_get_type ()) +#define STLINK_GUI(obj) (G_TYPE_CHECK_INSTANCE_CAST ((obj), STLINK_TYPE_GUI, STlinkGUI)) +#define STLINK_IS_GUI(obj) (G_TYPE_CHECK_INSTANCE_TYPE ((obj), STLINK_TYPE_GUI)) +#define STLINK_GUI_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST ((klass), STLINK_TYPE_GUI, STlinkGUIClass)) +#define STLINK_IS_GUI_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE ((klass), STLINK_TYPE_GUI)) +#define STLINK_GUI_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS ((obj), STLINK_TYPE_GUI, STlinkGUIlass)) +#define STLINK_GUI_GET_PRIVATE(obj) (G_TYPE_INSTANCE_GET_PRIVATE ((obj), STLINK_TYPE_GUI, STlinkGUIPrivate)) + +typedef struct _STlinkGUI STlinkGUI; +typedef struct _STlinkGUIClass STlinkGUIClass; +typedef struct _STlinkGUIPrivate STlinkGUIPrivate; + +enum stlink_gui_pages_t { + PAGE_DEVMEM, + PAGE_FILEMEM +}; + +enum stlink_gui_dnd_targets_t { + TARGET_FILENAME, + TARGET_ROOTWIN +}; + +struct progress_t { + GtkProgressBar *bar; + guint timer; + gboolean activity_mode; + gdouble fraction; +}; + +struct mem_t { + guchar *memory; + gsize size; + guint32 base; +}; + +struct _STlinkGUI +{ + GObject parent_instance; + + /*< private >*/ + GtkWindow *window; + GtkTreeView *devmem_treeview; + GtkTreeView *filemem_treeview; + GtkSpinner *spinner; + GtkStatusbar *statusbar; + GtkInfoBar *infobar; + GtkLabel *infolabel; + GtkNotebook *notebook; + GtkFrame *device_frame; + GtkLabel *chip_id_label; + GtkLabel *core_id_label; + GtkLabel *flash_size_label; + GtkLabel *ram_size_label; + GtkBox *devmem_box; + GtkEntry *devmem_jmp_entry; + GtkBox *filemem_box; + GtkEntry *filemem_jmp_entry; + GtkToolButton *connect_button; + GtkToolButton *disconnect_button; + GtkToolButton *flash_button; + GtkToolButton *open_button; + + /* flash dialog */ + GtkDialog *flash_dialog; + GtkButton *flash_dialog_ok; + GtkButton *flash_dialog_cancel; + GtkEntry *flash_dialog_entry; + + struct progress_t progress; + struct mem_t flash_mem; + struct mem_t file_mem; + + gchar *error_message; + gchar *filename; + stlink_t *sl; +}; + +struct _STlinkGUIClass +{ + GObjectClass parent_class; + + /* class members */ +}; + +GType stlink_gui_get_type (void); + +#endif diff --git a/gui/stlink-gui.ui b/gui/stlink-gui.ui new file mode 100644 index 000000000..193925ce1 --- /dev/null +++ b/gui/stlink-gui.ui @@ -0,0 +1,666 @@ + + + + + False + 5 + Flash device + dialog + + + False + vertical + 2 + + + False + end + + + gtk-cancel + True + False + True + True + + + False + True + 0 + + + + + gtk-ok + True + False + True + True + + + False + True + 1 + + + + + False + True + end + 0 + + + + + True + False + 5 + 5 + 5 + 5 + 5 + True + + + True + False + Address to write at: + + + 0 + 0 + 1 + 1 + + + + + True + True + • + 12 + + + 1 + 0 + 1 + 1 + + + + + False + True + 2 + + + + + + flash_dialog_cancel_button + flash_dialog_ok_button + + + + False + STlink GUI + 550 + 480 + + + True + False + vertical + + + True + False + True + + + True + False + Open + Open + True + gtk-open + + + False + True + + + + + True + False + Connect + Connect + True + gtk-connect + + + False + True + + + + + True + False + Disconnect + Disconnect + True + gtk-disconnect + + + False + True + + + + + True + False + Flash + Flash + True + gtk-media-record + + + False + True + + + + + True + False + + + True + False + start + 5 + 5 + + + + + False + True + + + + + 0 + 0 + 1 + 1 + + + + + True + False + 5 + 5 + 5 + + + True + False + 0.98999999999999999 + 4 + 4 + 1 + 0 + + + True + False + 12 + 12 + + + True + False + 2 + 6 + True + + + True + False + 1 + 1 + 0 + 0 + Chip: + + + 0 + 0 + 1 + 1 + + + + + True + False + 0 + 0 + Core: + + + 0 + 1 + 1 + 1 + + + + + True + False + 0 + 0 + Flash size: + + + 0 + 2 + 1 + 1 + + + + + True + False + 0 + 0 + True + + + 1 + 1 + 1 + 1 + + + + + True + False + 0 + 0 + 20 + + + 1 + 0 + 1 + 1 + + + + + True + False + 0 + 0 + + + 1 + 2 + 1 + 1 + + + + + True + False + 0 + 0 + Ram size: + + + 0 + 3 + 1 + 1 + + + + + True + False + 0 + 0 + + + 1 + 3 + 1 + 1 + + + + + + + + + True + False + 0.49000000953674316 + 2 + <b>Device</b> + True + + + + + 0 + 0 + 1 + 1 + + + + + 0 + 2 + 1 + 1 + + + + + True + False + 5 + 5 + 5 + vertical + 2 + + + 0 + 4 + 1 + 1 + + + + + True + False + 5 + 5 + 5 + 5 + + + True + False + vertical + + + True + False + + + True + False + start + 5 + 5 + 5 + 5 + Goto address: + + + 0 + 0 + 1 + 1 + + + + + True + True + 5 + 5 + 5 + 5 + 15 + • + 12 + + + 1 + 0 + 1 + 1 + + + + + False + True + 0 + + + + + True + False + True + in + + + True + False + True + both + + + + + + + + False + True + 1 + + + + + Device memory + + + + + True + False + Device memory + + + False + + + + + True + False + vertical + + + True + False + + + True + False + 5 + 5 + 5 + 5 + Goto address: + + + 0 + 0 + 1 + 1 + + + + + True + True + 5 + 5 + 5 + 5 + 15 + • + 12 + + + 1 + 0 + 1 + 1 + + + + + False + True + 0 + + + + + True + False + True + in + + + True + False + True + both + + + + + + + + False + True + 1 + + + + + 1 + + + + + True + False + No file + + + 1 + False + + + + + + + + + + + + + + + + + 0 + 3 + 1 + 1 + + + + + True + True + False + error + + + False + 8 + 5 + + + + + + True + True + 0 + + + + + False + 5 + vertical + 6 + end + + + + + + + + + + + + False + True + 1 + + + + + 0 + 1 + 1 + 1 + + + + + + From 688d6565fbe84cadf64cf4c8014ed5aa7299487d Mon Sep 17 00:00:00 2001 From: Jonas Danielsson Date: Mon, 10 Jun 2013 11:33:05 +0200 Subject: [PATCH 0217/1435] autoconf: add --with-gtk option to enable gui --- Makefile.am | 2 ++ configure.ac | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/Makefile.am b/Makefile.am index 9c99297ec..538db1a87 100644 --- a/Makefile.am +++ b/Makefile.am @@ -1,5 +1,7 @@ # Makefile.am -- Process this file with automake to produce Makefile.in +SUBDIRS = . $(MAYBE_GUI) + AUTOMAKE_OPTIONS = subdir-objects bin_PROGRAMS = st-flash st-util st-term diff --git a/configure.ac b/configure.ac index e8923ed36..53f827893 100644 --- a/configure.ac +++ b/configure.ac @@ -34,6 +34,17 @@ case "${host}" in CPPFLAGS="-D__USE_MINGW_ANSI_STDIO=1 $CPPFLAGS" ;; esac + +MAYBE_GUI= +AC_ARG_WITH([gtk], AS_HELP_STRING([--with-gtk], [enable GTK+ gui])) +if test "x$with_gtk" = "xyes"; then + PKG_CHECK_MODULES([GTK], [gtk+-3.0]) + PKG_CHECK_MODULES([GLIB], [glib-2.0 > 2.32.0]) + MAYBE_GUI=gui + AC_CONFIG_FILES([gui/Makefile]) +fi +AC_SUBST([MAYBE_GUI]) + AC_CONFIG_FILES([Makefile]) AC_OUTPUT From cb8e6c65f95bf7495fac9c467e7d884a28bec995 Mon Sep 17 00:00:00 2001 From: Jonas Danielsson Date: Thu, 13 Jun 2013 08:03:21 +0200 Subject: [PATCH 0218/1435] stlink-gui: add check for existence of UI file --- gui/stlink-gui.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/gui/stlink-gui.c b/gui/stlink-gui.c index 756d7666c..fde1d34ba 100644 --- a/gui/stlink-gui.c +++ b/gui/stlink-gui.c @@ -798,10 +798,15 @@ stlink_gui_build_ui (STlinkGUI *gui) { GtkBuilder *builder; GtkListStore *devmem_store; GtkListStore *filemem_store; + gchar *ui_file = STLINK_UI_DIR "/stlink-gui.ui"; + if (!g_file_test (ui_file, G_FILE_TEST_EXISTS)) { + ui_file = "stlink-gui.ui"; + } builder = gtk_builder_new (); - if (!gtk_builder_add_from_file (builder, STLINK_UI_DIR "/stlink-gui.ui", NULL)) { - /* woot */ + if (!gtk_builder_add_from_file (builder, ui_file, NULL)) { + g_printerr ("Failed to load UI file: %s\n", ui_file); + exit (1); } gui->window = GTK_WINDOW (gtk_builder_get_object (builder, "window")); From 5553cd1674ca94fc7be0377fb886dd8a54766d6c Mon Sep 17 00:00:00 2001 From: "Breton M. Saunders" Date: Fri, 14 Jun 2013 16:13:33 +0100 Subject: [PATCH 0219/1435] Added support for small f0 devices with core id 0x444 --- src/stlink-common.c | 7 +++++-- src/stlink-common.h | 14 +++++++++++++- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 05ee12cd3..ade2664fb 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1110,7 +1110,10 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) val = stlink_read_debug32(sl, STM32L_FLASH_PECR) | (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { + } else if (sl->core_id == STM32VL_CORE_ID + || sl->core_id == STM32F0_CORE_ID + || sl->chip_id == STM32_CHIPID_F3 + || sl->chip_id == STM32_CHIPID_F37x) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1321,7 +1324,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { loader_code = loader_code_stm32f4; loader_size = sizeof(loader_code_stm32f4); - } else if (sl->chip_id == STM32_CHIPID_F0) { + } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F0_SMALL) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); } else { diff --git a/src/stlink-common.h b/src/stlink-common.h index 68f5082e4..d2f274f82 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -111,6 +111,7 @@ extern "C" { #define STM32_CHIPID_F1_VL_HIGH 0x428 #define STM32_CHIPID_F1_XL 0x430 #define STM32_CHIPID_F0 0x440 +#define STM32_CHIPID_F0_SMALL 0x444 // Constant STM32 memory map figures #define STM32_FLASH_BASE 0x08000000 @@ -272,7 +273,18 @@ static const chip_params_t devices[] = { .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 - } + }, + { + //Use this as an example for mapping future chips: + //RM0091 document was used to find these paramaters + .chip_id = STM32_CHIPID_F0_SMALL, + .description = "F0 small device", + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + }, }; From 7f8750db3320c3c63be5d8b064498601b8a0dddb Mon Sep 17 00:00:00 2001 From: Andrey Yurovsky Date: Fri, 21 Jun 2013 11:59:35 -0700 Subject: [PATCH 0220/1435] add new STM32F401 parts (F4 variant) Nearly identical to STM32F403/407 but has different chip ID and RAM size: http://www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1810 --- src/stlink-common.c | 61 ++++++++++++++++++++++++++++++--------------- src/stlink-common.h | 24 +++++++++++++++++- 2 files changed, 64 insertions(+), 21 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 05ee12cd3..ed1583d5a 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -143,7 +143,8 @@ static inline uint32_t read_flash_obr(stlink_t *sl) { static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t res; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_LP)) res = stlink_read_debug32(sl, FLASH_F4_CR); else res = stlink_read_debug32(sl, FLASH_CR); @@ -155,7 +156,8 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_LP)) return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); else return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); @@ -167,7 +169,8 @@ static void unlock_flash(stlink_t *sl) { an invalid sequence results in a definitive lock of the FPEC block until next reset. */ - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) { + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_LP)) { stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); } else { @@ -192,7 +195,8 @@ static int unlock_flash_if(stlink_t *sl) { } static void lock_flash(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) { + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_LP)) { const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); stlink_write_debug32(sl, FLASH_F4_CR, n); } else { @@ -204,7 +208,8 @@ static void lock_flash(stlink_t *sl) { static void set_flash_cr_pg(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) { + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_LP)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_CR_PG); stlink_write_debug32(sl, FLASH_F4_CR, x); @@ -216,7 +221,8 @@ static void set_flash_cr_pg(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_LP)) stlink_write_debug32(sl, FLASH_F4_CR, n); else stlink_write_debug32(sl, FLASH_CR, n); @@ -233,7 +239,8 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { } static void set_flash_cr_mer(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_LP)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); else @@ -242,7 +249,8 @@ static void set_flash_cr_mer(stlink_t *sl) { } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_LP)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); else @@ -251,7 +259,8 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { } static void set_flash_cr_strt(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) { + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_LP)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_F4_CR_STRT); stlink_write_debug32(sl, FLASH_F4_CR, x); @@ -267,7 +276,8 @@ static inline uint32_t read_flash_acr(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_LP)) res = stlink_read_debug32(sl, FLASH_F4_SR); else res = stlink_read_debug32(sl, FLASH_SR); @@ -276,7 +286,8 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { } static inline unsigned int is_flash_busy(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_LP)) return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); else return read_flash_sr(sl) & (1 << FLASH_SR_BSY); @@ -450,7 +461,8 @@ int stlink_load_device_params(stlink_t *sl) { // read flash size from hardware, if possible... if (sl->chip_id == STM32_CHIPID_F2) { sl->flash_size = 0x100000; /* Use maximum, User must care!*/ - } else if (sl->chip_id == STM32_CHIPID_F4) { + } else if (sl->chip_id == STM32_CHIPID_F4 || + sl->chip_id == STM32_CHIPID_F4_LP) { sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { // if the flash size is zero, we assume it is 128k, if not we calculate the real value @@ -993,7 +1005,8 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) { + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_LP)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector<4) sl->flash_pgsz=0x4000; else if(sector<5) sl->flash_pgsz=0x10000; @@ -1010,7 +1023,8 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) { + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_LP)) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1110,7 +1124,10 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) val = stlink_read_debug32(sl, STM32L_FLASH_PECR) | (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { + } else if (sl->core_id == STM32VL_CORE_ID + || sl->core_id == STM32F0_CORE_ID + || sl->chip_id == STM32_CHIPID_F3 + || sl->chip_id == STM32_CHIPID_F37x) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1318,10 +1335,11 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); - } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { + } else if (sl->chip_id == STM32_CHIPID_F2 || + sl->chip_id == STM32_CHIPID_F4 || sl->chip_id == STM32_CHIPID_F4_LP) { loader_code = loader_code_stm32f4; loader_size = sizeof(loader_code_stm32f4); - } else if (sl->chip_id == STM32_CHIPID_F0) { + } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F0_SMALL) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); } else { @@ -1486,7 +1504,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t ILOG("Finished erasing %d pages of %d (%#x) bytes\n", page_count, sl->flash_pgsz, sl->flash_pgsz); - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4)) { + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_LP)) { /* todo: check write operation */ ILOG("Starting Flash write for F2/F4\n"); @@ -1769,7 +1788,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { + } else if (sl->chip_id == STM32_CHIPID_F2 || + sl->chip_id == STM32_CHIPID_F4 || sl->chip_id == STM32_CHIPID_F4_LP) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1821,7 +1841,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4) { + } else if (sl->chip_id == STM32_CHIPID_F2 || + sl->chip_id == STM32_CHIPID_F4 || sl->chip_id == STM32_CHIPID_F4_LP) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { diff --git a/src/stlink-common.h b/src/stlink-common.h index 68f5082e4..8b1be82c8 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -102,6 +102,7 @@ extern "C" { #define STM32_CHIPID_F3 0x422 #define STM32_CHIPID_F37x 0x432 #define STM32_CHIPID_F4 0x413 +#define STM32_CHIPID_F4_LP 0x423 #define STM32_CHIPID_F1_HIGH 0x414 #define STM32_CHIPID_L1_MEDIUM 0x416 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x436 @@ -111,6 +112,7 @@ extern "C" { #define STM32_CHIPID_F1_VL_HIGH 0x428 #define STM32_CHIPID_F1_XL 0x430 #define STM32_CHIPID_F0 0x440 +#define STM32_CHIPID_F0_SMALL 0x444 // Constant STM32 memory map figures #define STM32_FLASH_BASE 0x08000000 @@ -175,6 +177,15 @@ static const chip_params_t devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800 }, + { + .chip_id = STM32_CHIPID_F4_LP, + .description = "F4 device (low power)", + .flash_size_reg = 0x1FFF7A10, + .flash_pagesize = 0x4000, + .sram_size = 0x10000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, { .chip_id = STM32_CHIPID_F1_HIGH, .description = "F1 High-density device", @@ -272,7 +283,18 @@ static const chip_params_t devices[] = { .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 - } + }, + { + //Use this as an example for mapping future chips: + //RM0091 document was used to find these paramaters + .chip_id = STM32_CHIPID_F0_SMALL, + .description = "F0 small device", + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + }, }; From ff1e88398c0de2084b13196a422101224fed2779 Mon Sep 17 00:00:00 2001 From: Burns Date: Fri, 21 Jun 2013 17:36:15 -0400 Subject: [PATCH 0221/1435] Support for STM32L1 medium-plus chips with chip id 0x427 -Changed the STM32L1 "medium plus" (id 0x436) support to be called HIGH. -Added the device id 0x427 and call it medium plus. -Gave the loader more time so it stopped timing out and thinking it failed. -Added st-term to .gitignore Note: ST seems to call some chips with 436 medium plus and some high. It seemed easier to name 436 high and 427 medium plus. --- .gitignore | 1 + src/stlink-common.c | 30 +++++++++++++++++++----------- src/stlink-common.h | 22 +++++++++++++++++++--- 3 files changed, 39 insertions(+), 14 deletions(-) diff --git a/.gitignore b/.gitignore index 6ed8efce9..d7df95e81 100644 --- a/.gitignore +++ b/.gitignore @@ -20,6 +20,7 @@ config.status compile st-flash st-util +st-term test_usb test_sg *.deps* diff --git a/src/stlink-common.c b/src/stlink-common.c index ade2664fb..2b208bc54 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -452,7 +452,7 @@ int stlink_load_device_params(stlink_t *sl) { sl->flash_size = 0x100000; /* Use maximum, User must care!*/ } else if (sl->chip_id == STM32_CHIPID_F4) { sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID - } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM) { + } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) { // if the flash size is zero, we assume it is 128k, if not we calculate the real value uint32_t flash_size = stlink_read_debug32(sl,params->flash_size_reg) & 0xffff; if ( flash_size == 0 ) { @@ -460,7 +460,7 @@ int stlink_load_device_params(stlink_t *sl) { } else { sl->flash_size = flash_size * 1024; } - } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_MEDIUM_PLUS) { + } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_HIGH) { uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0x1; // 0 is 384k and 1 is 256k if ( flash_size == 0 ) { @@ -911,7 +911,8 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) int error = -1; size_t off; int num_empty = 0; - unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS)?0:0xff; + unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS + || sl->chip_id == STM32_CHIPID_L1_HIGH) ? 0:0xff; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -1036,7 +1037,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif - } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) { + } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS + || sl->chip_id == STM32_CHIPID_L1_HIGH) { uint32_t val; @@ -1145,7 +1147,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS ) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS + || sl->chip_id == STM32_CHIPID_L1_HIGH) { /* erase each page */ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1315,7 +1318,8 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS ) { /* stm32l */ + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS + || sl->chip_id == STM32_CHIPID_L1_HIGH ) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { @@ -1555,7 +1559,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } //STM32F4END - else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) { + else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS + || sl->chip_id == STM32_CHIPID_L1_HIGH ) { /* use fast word write. todo: half page. */ uint32_t val; @@ -1711,7 +1716,8 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ int err; unsigned int num_empty = 0, index; - unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS)?0:0xff; + unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS + || sl->chip_id == STM32_CHIPID_L1_HIGH )?0:0xff; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { ELOG("map_file() == -1\n"); @@ -1749,7 +1755,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS + || sl->chip_id == STM32_CHIPID_L1_HIGH ) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1791,7 +1798,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons /* run loader */ stlink_run(sl); -#define WAIT_ROUNDS 1000 +#define WAIT_ROUNDS 10000 /* wait until done (reaches breakpoint) */ for (i = 0; i < WAIT_ROUNDS; i++) { usleep(10); @@ -1805,7 +1812,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } /* check written byte count */ - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS + || sl->chip_id == STM32_CHIPID_L1_HIGH ) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; diff --git a/src/stlink-common.h b/src/stlink-common.h index d2f274f82..7553224cd 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -104,7 +104,13 @@ extern "C" { #define STM32_CHIPID_F4 0x413 #define STM32_CHIPID_F1_HIGH 0x414 #define STM32_CHIPID_L1_MEDIUM 0x416 -#define STM32_CHIPID_L1_MEDIUM_PLUS 0x436 +#define STM32_CHIPID_L1_MEDIUM_PLUS 0x427 +/* + * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus" + * and some that are called "High". 0x427 is assigned to the other "Medium- + * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and + * 0x436 HIGH. + */ #define STM32_CHIPID_L1_HIGH 0x436 #define STM32_CHIPID_F1_CONN 0x418 #define STM32_CHIPID_F1_VL_MEDIUM 0x420 @@ -199,12 +205,22 @@ static const chip_params_t devices[] = { { .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS, .description = "L1 Medium-Plus-density device", - .flash_size_reg = 0x1ff800CC, + .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, - .sram_size = 0x8000, + .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/ .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000 }, + { + .chip_id = STM32_CHIPID_L1_HIGH, + .description = "L1 High-density device", + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/ + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { .chip_id = STM32_CHIPID_F1_CONN, .description = "F1 Connectivity line device", From 328dfd24fae56531d2df21ce2dfc781aefcc46c5 Mon Sep 17 00:00:00 2001 From: "Breton M. Saunders" Date: Tue, 9 Jul 2013 16:02:07 +0100 Subject: [PATCH 0222/1435] Added proper reset support; now asserts nrst and then performs sysreset. --- src/stlink-common.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index 23bea5836..b0de0ab34 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -499,6 +499,11 @@ int stlink_load_device_params(stlink_t *sl) { void stlink_reset(stlink_t *sl) { DLOG("*** stlink_reset ***\n"); + // Step 1: assert jtag reset + sl->backend->jtag_reset(sl, 1); + // Step 2: deassert jtag reset + sl->backend->jtag_reset(sl, 0); + // Step 3: perform the sysreset command sl->backend->reset(sl); } From f14323195cdc6b9c547c42de174ee127c66dead7 Mon Sep 17 00:00:00 2001 From: lementec Date: Thu, 18 Jul 2013 17:42:59 +0200 Subject: [PATCH 0223/1435] jtag reset introduced in 57d068097eb57aa7ee985ddb1edea90a5d6d5d8a breaks things --- src/stlink-common.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index b0de0ab34..23bea5836 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -499,11 +499,6 @@ int stlink_load_device_params(stlink_t *sl) { void stlink_reset(stlink_t *sl) { DLOG("*** stlink_reset ***\n"); - // Step 1: assert jtag reset - sl->backend->jtag_reset(sl, 1); - // Step 2: deassert jtag reset - sl->backend->jtag_reset(sl, 0); - // Step 3: perform the sysreset command sl->backend->reset(sl); } From 36cd837fc9382c8ccc5da2a562c261f2a47a9736 Mon Sep 17 00:00:00 2001 From: JohannesTaelman Date: Tue, 13 Aug 2013 15:37:44 +0200 Subject: [PATCH 0224/1435] fixed USB VID/PID detection bug When a USB device with same VID but different PID is found, it got selected as STLINK device. --- src/stlink-usb.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index d57458428..9895da855 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -754,7 +754,10 @@ stlink_t* stlink_open_usb(const int verbose) { if (devBus && devAddr) if ((libusb_get_bus_number(list[cnt])!=devBus) || (libusb_get_device_address(list[cnt])!=devAddr)) continue; if (desc.idProduct == USB_STLINK_32L_PID) break; - if (desc.idProduct == USB_STLINK_PID) slu->protocoll = 1; break; + if (desc.idProduct == USB_STLINK_PID) { + slu->protocoll = 1; + break; + } } if (cnt < 0) { From 596fb35916ef2f1da8b817fa4b6e365e71c0fc5a Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Wed, 6 Mar 2013 15:24:15 -0500 Subject: [PATCH 0225/1435] Add option to not reset board on connect '-n' in st-util will cause it to skip the reset step, and thus allow you to begin debugging at whatever point the code may currently be at. Adding this feature required changing the stlink_open functions to accept a reset flag that tells them whether or not to reset after connecting. Skipping reset does not seem to have any adverse effects on stlink usb devices. Unfortunately, I have to stlink v1 devices to test. --- flash/main.c | 4 ++-- gdbserver/gdb-server.c | 34 +++++++++++++++++++++++++--------- src/st-term.c | 2 +- src/stlink-sg.c | 6 ++++-- src/stlink-sg.h | 2 +- src/stlink-usb.c | 6 ++++-- src/stlink-usb.h | 2 +- src/test_sg.c | 2 +- src/test_usb.c | 2 +- 9 files changed, 40 insertions(+), 20 deletions(-) diff --git a/flash/main.c b/flash/main.c index 110c2964d..980af63be 100644 --- a/flash/main.c +++ b/flash/main.c @@ -106,13 +106,13 @@ int main(int ac, char** av) if (o.devname != NULL) /* stlinkv1 */ { - sl = stlink_v1_open(50); + sl = stlink_v1_open(50, 1); if (sl == NULL) goto on_error; sl->verbose = 50; } else /* stlinkv2 */ { - sl = stlink_open_usb(50); + sl = stlink_open_usb(50, 1); if (sl == NULL) goto on_error; sl->verbose = 50; } diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index f9c06f983..d0a6a02d7 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -50,6 +50,7 @@ typedef struct _st_state_t { int logging_level; int listen_port; int persistent; + int reset; } st_state_t; @@ -78,6 +79,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { {"stlinkv1", no_argument, NULL, '1'}, {"listen_port", required_argument, NULL, 'p'}, {"multi", optional_argument, NULL, 'm'}, + {"no-reset", optional_argument, NULL, 'n'}, {0, 0, 0, 0}, }; const char * help_str = "%s - usage:\n\n" @@ -95,13 +97,15 @@ int parse_options(int argc, char** argv, st_state_t *st) { " -m, --multi\n" "\t\t\tSet gdb server to extended mode.\n" "\t\t\tst-util will continue listening for connections after disconnect.\n" + " -n, --no-reset\n" + "\t\t\tDo not reset board on connection.\n" ; int option_index = 0; int c; int q; - while ((c = getopt_long(argc, argv, "hv::d:s:1p:m", long_options, &option_index)) != -1) { + while ((c = getopt_long(argc, argv, "hv::d:s:1p:mn", long_options, &option_index)) != -1) { switch (c) { case 0: printf("XXXXX Shouldn't really normally come here, only if there's no corresponding option\n"); @@ -151,6 +155,9 @@ int parse_options(int argc, char** argv, st_state_t *st) { case 'm': st->persistent = 1; break; + case 'n': + st->reset = 0; + break; } } @@ -174,14 +181,15 @@ int main(int argc, char** argv) { state.stlink_version = 2; state.logging_level = DEFAULT_LOGGING_LEVEL; state.listen_port = DEFAULT_GDB_LISTEN_PORT; + state.reset = 1; /* By default, reset board */ parse_options(argc, argv, &state); switch (state.stlink_version) { case 2: - sl = stlink_open_usb(state.logging_level); + sl = stlink_open_usb(state.logging_level, 0); if(sl == NULL) return 1; break; case 1: - sl = stlink_v1_open(state.logging_level); + sl = stlink_v1_open(state.logging_level, 0); if(sl == NULL) return 1; break; } @@ -190,6 +198,10 @@ int main(int argc, char** argv) { signal(SIGINT, &cleanup); signal(SIGTERM, &cleanup); + if (state.reset) { + stlink_reset(sl); + } + printf("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); sl->verbose=0; @@ -205,6 +217,9 @@ int main(int argc, char** argv) { do { serve(sl, &state); + + /* Continue */ + stlink_run(sl); } while (state.persistent); #ifdef __MINGW32__ @@ -213,7 +228,6 @@ int main(int argc, char** argv) { #endif /* Switch back to mass storage mode before closing. */ - stlink_run(sl); stlink_exit_debug_mode(sl); stlink_close(sl); @@ -679,11 +693,6 @@ int serve(stlink_t *sl, st_state_t *st) { return 1; } - stlink_force_debug(sl); - stlink_reset(sl); - init_code_breakpoints(sl); - init_data_watchpoints(sl); - printf("Listening at *:%d...\n", st->listen_port); int client = accept(sock, NULL, NULL); @@ -695,6 +704,13 @@ int serve(stlink_t *sl, st_state_t *st) { close(sock); + stlink_force_debug(sl); + if (st->reset) { + stlink_reset(sl); + } + init_code_breakpoints(sl); + init_data_watchpoints(sl); + printf("GDB connected.\n"); /* diff --git a/src/st-term.c b/src/st-term.c index f4643933c..9be3263af 100644 --- a/src/st-term.c +++ b/src/st-term.c @@ -136,7 +136,7 @@ int main(int ac, char** av) { /* unused */ ac = ac; av = av; - sl = stlink_open_usb(10); + sl = stlink_open_usb(10, 1); if (sl != NULL) { printf("ST-Linky proof-of-concept terminal :: Created by Necromant for lulz\n"); stlink_version(sl); diff --git a/src/stlink-sg.c b/src/stlink-sg.c index ae610bac7..be1f7526b 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -1021,7 +1021,7 @@ stlink_t* stlink_v1_open_inner(const int verbose) { return sl; } -stlink_t* stlink_v1_open(const int verbose) { +stlink_t* stlink_v1_open(const int verbose, int reset) { stlink_t *sl = stlink_v1_open_inner(verbose); if (sl == NULL) { fputs("Error: could not open stlink device\n", stderr); @@ -1030,7 +1030,9 @@ stlink_t* stlink_v1_open(const int verbose) { // by now, it _must_ be fully open and in a useful mode.... stlink_enter_swd_mode(sl); /* Now we are ready to read the parameters */ - stlink_reset(sl); + if (reset) { + stlink_reset(sl); + } stlink_load_device_params(sl); ILOG("Successfully opened a stlink v1 debugger\n"); return sl; diff --git a/src/stlink-sg.h b/src/stlink-sg.h index beecac324..f8871db99 100644 --- a/src/stlink-sg.h +++ b/src/stlink-sg.h @@ -63,7 +63,7 @@ extern "C" { reg reg; }; - stlink_t* stlink_v1_open(const int verbose); + stlink_t* stlink_v1_open(const int verbose, int reset); #ifdef __cplusplus } diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 9895da855..858361c66 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -704,7 +704,7 @@ stlink_backend_t _stlink_usb_backend = { }; -stlink_t* stlink_open_usb(const int verbose) { +stlink_t* stlink_open_usb(const int verbose, int reset) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; int error = -1; @@ -833,7 +833,9 @@ stlink_t* stlink_open_usb(const int verbose) { stlink_enter_swd_mode(sl); } - stlink_reset(sl); + if (reset) { + stlink_reset(sl); + } stlink_load_device_params(sl); stlink_version(sl); diff --git a/src/stlink-usb.h b/src/stlink-usb.h index 63b53695e..f433193c8 100644 --- a/src/stlink-usb.h +++ b/src/stlink-usb.h @@ -30,7 +30,7 @@ extern "C" { unsigned int cmd_len; }; - stlink_t* stlink_open_usb(const int verbose); + stlink_t* stlink_open_usb(const int verbose, int reset); #ifdef __cplusplus diff --git a/src/test_sg.c b/src/test_sg.c index 51b0f074c..bc16a1c7c 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -52,7 +52,7 @@ int main(int argc, char *argv[]) { break; } - stlink_t *sl = stlink_v1_open(99); + stlink_t *sl = stlink_v1_open(99, 1); if (sl == NULL) return EXIT_FAILURE; diff --git a/src/test_usb.c b/src/test_usb.c index be4981db0..5e8806d29 100644 --- a/src/test_usb.c +++ b/src/test_usb.c @@ -10,7 +10,7 @@ int main(int ac, char** av) { ac = ac; av = av; - sl = stlink_open_usb(10); + sl = stlink_open_usb(10, 1); if (sl != NULL) { printf("-- version\n"); stlink_version(sl); From 77f85f32097975a2511fecac39b789dac6f0d4f7 Mon Sep 17 00:00:00 2001 From: Vadim Kaushan Date: Sat, 24 Aug 2013 13:40:03 +0400 Subject: [PATCH 0226/1435] Update list of known working targets --- README | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/README b/README index cd4fc5af5..d717dc22a 100644 --- a/README +++ b/README @@ -163,8 +163,9 @@ STLink v2 (as found on the 32L and F4 Discovery boards) Known Working Targets: * STM32F100xx (Medium Density VL, as on the 32VL Discovery board) * STM32L1xx (STM32L Discovery board) -* STM32F107RC, STM32L151RB, STM32F205RE and STM32F405RE on a custom boards +* STM32F103VC, STM32F107RC, STM32L151RB, STM32F205RE and STM32F405RE on custom boards (https://github.com/UweBonnes/wiki_fuer_alex/layout/usps...) +* STM32F303xx (STM32F3 Discovery board) * STM32F407xx (STM32F4 Discovery board) Please report any and all known working combinations so I can update this! From 00eb8b959d3207dffd8e15eeec6550b65b057a35 Mon Sep 17 00:00:00 2001 From: texane Date: Sat, 31 Aug 2013 22:04:21 -0500 Subject: [PATCH 0227/1435] [ fix ] 0001-stlink-gui-Follow-new-stlink_open-usage, fix from Jim Huang --- gui/stlink-gui.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gui/stlink-gui.c b/gui/stlink-gui.c index fde1d34ba..3646c3a4f 100644 --- a/gui/stlink-gui.c +++ b/gui/stlink-gui.c @@ -528,9 +528,9 @@ connect_button_cb (GtkWidget *widget, gpointer data) return; /* try version 1 then version 2 */ - gui->sl = stlink_v1_open(0); + gui->sl = stlink_v1_open(0, 1); if (gui->sl == NULL) { - gui->sl = stlink_open_usb(0); + gui->sl = stlink_open_usb(0, 1); } if (gui->sl == NULL) { stlink_gui_set_info_error_message (gui, "Failed to connect to STLink."); return; From 0a6c0903c65439cfeb0aabee31521662d1e61a0e Mon Sep 17 00:00:00 2001 From: texane Date: Sat, 31 Aug 2013 22:09:05 -0500 Subject: [PATCH 0228/1435] [ fix ] missing exit prototype, include stdlib.h --- src/st-term.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/st-term.c b/src/st-term.c index 9be3263af..346cca58f 100644 --- a/src/st-term.c +++ b/src/st-term.c @@ -1,4 +1,5 @@ #include +#include /* According to POSIX.1-2001 */ #include #include From 57700499f1ae4ec327eaf36fe957244002b461db Mon Sep 17 00:00:00 2001 From: Maxime Vincent Date: Sun, 1 Sep 2013 09:23:19 +0200 Subject: [PATCH 0229/1435] Fixed the DEBUG switch in gdb-server.c --- gdbserver/gdb-server.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index d0a6a02d7..13c5d1641 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -384,7 +384,7 @@ struct code_hw_watchpoint { struct code_hw_watchpoint data_watches[DATA_WATCH_NUM]; static void init_data_watchpoints(stlink_t *sl) { - #ifdef DEBUG + #if DEBUG printf("init watchpoints\n"); #endif @@ -419,7 +419,7 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr for(i = 0; i < DATA_WATCH_NUM; i++) { // is this an empty slot ? if(data_watches[i].fun == WATCHDISABLED) { - #ifdef DEBUG + #if DEBUG printf("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len); #endif @@ -443,7 +443,7 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr } } - #ifdef DEBUG + #if DEBUG printf("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len); #endif return -1; @@ -455,7 +455,7 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) for(i = 0 ; i < DATA_WATCH_NUM; i++) { if((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) { - #ifdef DEBUG + #if DEBUG printf("delete watchpoint %d addr %x\n", i, addr); #endif @@ -466,7 +466,7 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) } } - #ifdef DEBUG + #if DEBUG printf("failure: delete watchpoint addr %x\n", addr); #endif @@ -527,7 +527,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { else brk->type &= ~type; if(brk->type == 0) { - #ifdef DEBUG + #if DEBUG printf("clearing hw break %d\n", id); #endif @@ -535,7 +535,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { } else { uint32_t mask = (brk->addr) | 1 | (brk->type << 30); - #ifdef DEBUG + #if DEBUG printf("setting hw break %d at %08x (%d)\n", id, brk->addr, brk->type); printf("reg %08x \n", @@ -631,7 +631,7 @@ static int flash_go(stlink_t *sl) { stlink_reset(sl); for(struct flash_block* fb = flash_root; fb; fb = fb->next) { - #ifdef DEBUG + #if DEBUG printf("flash_do: block %08x -> %04x\n", fb->addr, fb->length); #endif @@ -641,7 +641,7 @@ static int flash_go(stlink_t *sl) { //Update FLASH_PAGE stlink_calculate_pagesize(sl, page); - #ifdef DEBUG + #if DEBUG printf("flash_do: page %08x\n", page); #endif @@ -728,7 +728,7 @@ int serve(stlink_t *sl, st_state_t *st) { return 1; } - #ifdef DEBUG + #if DEBUG printf("recv: %s\n", packet); #endif @@ -753,7 +753,7 @@ int serve(stlink_t *sl, st_state_t *st) { char* queryName = calloc(queryNameLength + 1, 1); strncpy(queryName, &packet[1], queryNameLength); - #ifdef DEBUG + #if DEBUG printf("query: %s;%s\n", queryName, params); #endif @@ -778,7 +778,7 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned addr = strtoul(__s_addr, NULL, 16), length = strtoul(s_length, NULL, 16); - #ifdef DEBUG + #if DEBUG printf("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", type, op, annex, addr, length); #endif @@ -815,7 +815,7 @@ int serve(stlink_t *sl, st_state_t *st) { if (!strncmp(params,"726573756d65",12)) {// resume -#ifdef DEBUG +#if DEBUG printf("Rcmd: resume\n"); #endif stlink_run(sl); @@ -826,7 +826,7 @@ int serve(stlink_t *sl, st_state_t *st) { stlink_force_debug(sl); -#ifdef DEBUG +#if DEBUG printf("Rcmd: halt\n"); #endif } else if (!strncmp(params,"6a7461675f7265736574",20)) { //jtag_reset @@ -836,7 +836,7 @@ int serve(stlink_t *sl, st_state_t *st) { stlink_jtag_reset(sl, 0); stlink_force_debug(sl); -#ifdef DEBUG +#if DEBUG printf("Rcmd: jtag_reset\n"); #endif } else if (!strncmp(params,"7265736574",10)) { //reset @@ -847,11 +847,11 @@ int serve(stlink_t *sl, st_state_t *st) { init_code_breakpoints(sl); init_data_watchpoints(sl); -#ifdef DEBUG +#if DEBUG printf("Rcmd: reset\n"); #endif } else { -#ifdef DEBUG +#if DEBUG printf("Rcmd: %s\n", params); #endif @@ -883,7 +883,7 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned addr = strtoul(__s_addr, NULL, 16), length = strtoul(s_length, NULL, 16); - #ifdef DEBUG + #if DEBUG printf("FlashErase: addr:%08x,len:%04x\n", addr, length); #endif @@ -921,7 +921,7 @@ int serve(stlink_t *sl, st_state_t *st) { if(dec_index % 2 != 0) dec_index++; - #ifdef DEBUG + #if DEBUG printf("binary packet %d -> %d\n", data_length, dec_index); #endif @@ -1263,7 +1263,7 @@ int serve(stlink_t *sl, st_state_t *st) { } if(reply) { - #ifdef DEBUG + #if DEBUG printf("send: %s\n", reply); #endif From e19054a4b36068329211cf5069ed92b06be66d8c Mon Sep 17 00:00:00 2001 From: Andrew 'Necromant' Andrianov Date: Sun, 29 Sep 2013 16:22:07 +0400 Subject: [PATCH 0230/1435] Add st-info utility Signed-off-by: Andrew 'Necromant' Andrianov --- Makefile.am | 9 ++++-- src/st-info.c | 88 +++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 95 insertions(+), 2 deletions(-) create mode 100644 src/st-info.c diff --git a/Makefile.am b/Makefile.am index 538db1a87..ab3201f03 100644 --- a/Makefile.am +++ b/Makefile.am @@ -4,12 +4,13 @@ SUBDIRS = . $(MAYBE_GUI) AUTOMAKE_OPTIONS = subdir-objects -bin_PROGRAMS = st-flash st-util st-term +bin_PROGRAMS = st-flash st-util st-term st-info noinst_LIBRARIES = libstlink.a st_flash_SOURCES = flash/main.c st_term_SOURCES = src/st-term.c +st_info_SOURCES = src/st-info.c st_util_SOURCES = gdbserver/gdb-remote.c gdbserver/gdb-remote.h gdbserver/gdb-server.c mingw/mingw.c mingw/mingw.h CFILES = \ @@ -17,7 +18,8 @@ CFILES = \ src/stlink-usb.c \ src/stlink-sg.c \ src/uglylogging.c \ - src/st-term.c + src/st-term.c \ + src/st-info.c HFILES = \ src/stlink-common.h \ @@ -40,6 +42,9 @@ st_util_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_srcd st_term_LDADD = libstlink.a st_term_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_srcdir)/mingw +st_info_LDADD = libstlink.a +st_info_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_srcdir)/mingw + EXTRA_DIST = autogen.sh diff --git a/src/st-info.c b/src/st-info.c new file mode 100644 index 000000000..6b251bce2 --- /dev/null +++ b/src/st-info.c @@ -0,0 +1,88 @@ +/* simple wrapper around the stlink_flash_write function */ + +// TODO - this should be done as just a simple flag to the st-util command line... + + +#include +#include +#include +#include +#include "stlink-common.h" + +static void usage(void) +{ + puts("st-info --flash"); + puts("st-info --sram"); + puts("st-info --descr"); + puts("st-info --pagesize"); + puts("st-info --chipid"); +} + +static int print_data(stlink_t* sl, int ac, char** av) +{ + int ret = 0; + if (strcmp(av[1], "--flash") == 0) + printf("0x%lx\n", sl->flash_size); + else if (strcmp(av[1], "--sram") == 0) + printf("0x%lx\n", sl->sram_size); + else if (strcmp(av[1], "--pagesize") == 0) + printf("0x%lx\n", sl->flash_pgsz); + else if (strcmp(av[1], "--chipid") == 0) + printf("0x%.4x\n", sl->chip_id); + else if (strcmp(av[1], "--descr")==0) { + const chip_params_t *params = NULL; + for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { + if(devices[i].chip_id == sl->chip_id) { + params = &devices[i]; + break; + } + } + if (params == NULL) { + return -1; + } + printf("%s\n", params->description); + } +} + + +stlink_t* open_sl() +{ + stlink_t* sl; + sl = stlink_v1_open(0, 1); + if (sl == NULL) + sl = stlink_open_usb(0, 1); + return sl; +} + + +int main(int ac, char** av) +{ + stlink_t* sl = NULL; + int err = -1; + if (ac < 2) { + usage(); + return -1; + } + + sl = open_sl(); + + if (sl == NULL) { + return -1; + } + sl->verbose=0; + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) + stlink_exit_dfu_mode(sl); + + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) + stlink_enter_swd_mode(sl); + + err = print_data(sl, ac, av); + + if (sl != NULL) + { + stlink_exit_debug_mode(sl); + stlink_close(sl); + } + + return err; +} From e886396e0e0ee27f8df2182f4d1a96bf59efedfb Mon Sep 17 00:00:00 2001 From: htk Date: Mon, 30 Sep 2013 01:51:26 +0200 Subject: [PATCH 0231/1435] Support for reading target voltage --- gdbserver/gdb-server.c | 6 ++++++ src/stlink-common.c | 16 ++++++++++++++++ src/stlink-common.h | 3 +++ src/stlink-sg.c | 3 ++- src/stlink-usb.c | 31 ++++++++++++++++++++++++++++++- 5 files changed, 57 insertions(+), 2 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 13c5d1641..bf1478122 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -172,6 +172,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { int main(int argc, char** argv) { + uint32_t voltage; stlink_t *sl = NULL; @@ -204,6 +205,11 @@ int main(int argc, char** argv) { printf("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); + voltage = stlink_target_voltage(sl); + if (voltage != -1) { + printf("Target voltage is %d mV.\n", voltage); + } + sl->verbose=0; current_memory_map = make_memory_map(sl); diff --git a/src/stlink-common.c b/src/stlink-common.c index 23bea5836..9613080ba 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -561,6 +561,22 @@ void stlink_version(stlink_t *sl) { } } +int stlink_target_voltage(stlink_t *sl) { + int voltage = -1; + DLOG("*** reading target voltage\n"); + if (sl->backend->target_voltage != NULL) { + voltage = sl->backend->target_voltage(sl); + if (voltage != -1) { + DLOG("target voltage = %ldmV\n", voltage); + } else { + DLOG("error reading target voltage\n"); + } + } else { + DLOG("reading voltage not supported by backend\n"); + } + return voltage; +} + uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) { uint32_t data = sl->backend->read_debug32(sl, addr); DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr); diff --git a/src/stlink-common.h b/src/stlink-common.h index c17019568..0ac4f12e0 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -34,6 +34,7 @@ extern "C" { #define STLINK_GET_VERSION 0xf1 #define STLINK_GET_CURRENT_MODE 0xf5 +#define STLINK_GET_TARGET_VOLTAGE 0xF7 #define STLINK_DEBUG_COMMAND 0xF2 #define STLINK_DFU_COMMAND 0xF3 @@ -386,6 +387,7 @@ static const chip_params_t devices[] = { void (*step) (stlink_t * stl); int (*current_mode) (stlink_t * stl); void (*force_debug) (stlink_t *sl); + uint32_t (*target_voltage) (stlink_t *sl); } stlink_backend_t; struct _stlink { @@ -455,6 +457,7 @@ static const chip_params_t devices[] = { void stlink_step(stlink_t *sl); int stlink_current_mode(stlink_t *sl); void stlink_force_debug(stlink_t *sl); + int stlink_target_voltage(stlink_t *sl); // unprocessed diff --git a/src/stlink-sg.c b/src/stlink-sg.c index be1f7526b..53e93cce0 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -878,7 +878,8 @@ stlink_backend_t _stlink_sg_backend = { _stlink_sg_write_reg, _stlink_sg_step, _stlink_sg_current_mode, - _stlink_sg_force_debug + _stlink_sg_force_debug, + NULL }; static stlink_t* stlink_open(const int verbose) { diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 858361c66..fa2bd7e08 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -203,6 +203,34 @@ void _stlink_usb_version(stlink_t *sl) { } } +int _stlink_usb_target_voltage(stlink_t *sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const rdata = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + uint32_t rep_len = 8; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + uint32_t factor, reading; + int voltage; + + cmd[i++] = STLINK_GET_TARGET_VOLTAGE; + + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); + if (size == -1) { + printf("[!] send_recv\n"); + return -1; + } else if (size != 8) { + printf("[!] wrong length\n"); + return -1; + } + + factor = (rdata[3] << 24) | (rdata[2] << 16) | (rdata[1] << 8) | (rdata[0] << 0); + reading = (rdata[7] << 24) | (rdata[6] << 16) | (rdata[5] << 8) | (rdata[4] << 0); + voltage = 2400 * reading / factor; + + return voltage; +} + uint32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const rdata = sl->q_buf; @@ -700,7 +728,8 @@ stlink_backend_t _stlink_usb_backend = { _stlink_usb_write_reg, _stlink_usb_step, _stlink_usb_current_mode, - _stlink_usb_force_debug + _stlink_usb_force_debug, + _stlink_usb_target_voltage }; From a13e75a25a322a9115f59cb753686ec9a2c7b6f7 Mon Sep 17 00:00:00 2001 From: texane Date: Mon, 30 Sep 2013 09:15:47 -0500 Subject: [PATCH 0232/1435] [ fix ] st-info warnings --- src/st-info.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/st-info.c b/src/st-info.c index 6b251bce2..e28a4f12c 100644 --- a/src/st-info.c +++ b/src/st-info.c @@ -18,7 +18,7 @@ static void usage(void) puts("st-info --chipid"); } -static int print_data(stlink_t* sl, int ac, char** av) +static int print_data(stlink_t* sl, char** av) { int ret = 0; if (strcmp(av[1], "--flash") == 0) @@ -42,10 +42,11 @@ static int print_data(stlink_t* sl, int ac, char** av) } printf("%s\n", params->description); } + return ret; } -stlink_t* open_sl() +stlink_t* open_sl(void) { stlink_t* sl; sl = stlink_v1_open(0, 1); @@ -76,7 +77,7 @@ int main(int ac, char** av) if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); - err = print_data(sl, ac, av); + err = print_data(sl, av); if (sl != NULL) { From f15ef16aea0304d008ad689ef7d10fa1b40cfc90 Mon Sep 17 00:00:00 2001 From: texane Date: Mon, 14 Oct 2013 18:07:46 -0500 Subject: [PATCH 0233/1435] [ patch from Uwe Bonnes ] determine flash size for more devices --- src/stlink-common.c | 21 ++++++--------------- src/stlink-common.h | 6 +++--- 2 files changed, 9 insertions(+), 18 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 9613080ba..a08da392c 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -434,6 +434,7 @@ int stlink_load_device_params(stlink_t *sl) { const chip_params_t *params = NULL; sl->core_id = stlink_core_id(sl); uint32_t chip_id = stlink_chip_id(sl); + uint32_t flash_size; sl->chip_id = chip_id & 0xfff; /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/ @@ -457,23 +458,14 @@ int stlink_load_device_params(stlink_t *sl) { // These are fixed... sl->flash_base = STM32_FLASH_BASE; sl->sram_base = STM32_SRAM_BASE; + flash_size = stlink_read_debug32(sl,(params->flash_size_reg) & ~3); + if (params->flash_size_reg & 2) + flash_size = flash_size >>16; + flash_size = flash_size & 0xffff; - // read flash size from hardware, if possible... - if (sl->chip_id == STM32_CHIPID_F2) { - sl->flash_size = 0x100000; /* Use maximum, User must care!*/ - } else if (sl->chip_id == STM32_CHIPID_F4 || - sl->chip_id == STM32_CHIPID_F4_LP) { - sl->flash_size = 0x100000; //todo: RM0090 error; size register same address as unique ID - } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) { - // if the flash size is zero, we assume it is 128k, if not we calculate the real value - uint32_t flash_size = stlink_read_debug32(sl,params->flash_size_reg) & 0xffff; - if ( flash_size == 0 ) { + if ((sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) && ( flash_size == 0 )) { sl->flash_size = 128 * 1024; - } else { - sl->flash_size = flash_size * 1024; - } } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_HIGH) { - uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0x1; // 0 is 384k and 1 is 256k if ( flash_size == 0 ) { sl->flash_size = 384 * 1024; @@ -481,7 +473,6 @@ int stlink_load_device_params(stlink_t *sl) { sl->flash_size = 256 * 1024; } } else { - uint32_t flash_size = stlink_read_debug32(sl, params->flash_size_reg) & 0xffff; sl->flash_size = flash_size * 1024; } sl->flash_pgsz = params->flash_pagesize; diff --git a/src/stlink-common.h b/src/stlink-common.h index 0ac4f12e0..5d300941e 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -160,7 +160,7 @@ static const chip_params_t devices[] = { { // table 1, PM0059 .chip_id = STM32_CHIPID_F2, .description = "F2 device", - .flash_size_reg = 0, /* no flash size reg found in the docs! */ + .flash_size_reg = 0x1ff7a22, /* RM0033 sind Rev 4*/ .flash_pagesize = 0x20000, .sram_size = 0x20000, .bootrom_base = 0x1fff0000, @@ -178,7 +178,7 @@ static const chip_params_t devices[] = { { .chip_id = STM32_CHIPID_F4, .description = "F4 device", - .flash_size_reg = 0x1FFF7A10, //RM0090 error same as unique ID + .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, .sram_size = 0x30000, .bootrom_base = 0x1fff0000, @@ -187,7 +187,7 @@ static const chip_params_t devices[] = { { .chip_id = STM32_CHIPID_F4_LP, .description = "F4 device (low power)", - .flash_size_reg = 0x1FFF7A10, + .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x10000, .bootrom_base = 0x1fff0000, From e40741e8275d722ebda534525089853ae5369e86 Mon Sep 17 00:00:00 2001 From: texane Date: Mon, 14 Oct 2013 18:08:42 -0500 Subject: [PATCH 0234/1435] [ patch from Uwe Bonnes ] add STM32F42x and F43x-parts (bank handling not yet supported) --- src/stlink-common.c | 40 ++++++++++++++++++++-------------------- src/stlink-common.h | 10 ++++++++++ 2 files changed, 30 insertions(+), 20 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index a08da392c..b7645fe88 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -144,7 +144,7 @@ static inline uint32_t read_flash_obr(stlink_t *sl) { static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t res; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) res = stlink_read_debug32(sl, FLASH_F4_CR); else res = stlink_read_debug32(sl, FLASH_CR); @@ -157,7 +157,7 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); else return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); @@ -170,7 +170,7 @@ static void unlock_flash(stlink_t *sl) { the FPEC block until next reset. */ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); } else { @@ -196,7 +196,7 @@ static int unlock_flash_if(stlink_t *sl) { static void lock_flash(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); stlink_write_debug32(sl, FLASH_F4_CR, n); } else { @@ -209,7 +209,7 @@ static void lock_flash(stlink_t *sl) { static void set_flash_cr_pg(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_CR_PG); stlink_write_debug32(sl, FLASH_F4_CR, x); @@ -222,7 +222,7 @@ static void set_flash_cr_pg(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) stlink_write_debug32(sl, FLASH_F4_CR, n); else stlink_write_debug32(sl, FLASH_CR, n); @@ -240,7 +240,7 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { static void set_flash_cr_mer(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); else @@ -250,7 +250,7 @@ static void set_flash_cr_mer(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); else @@ -260,7 +260,7 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { static void set_flash_cr_strt(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_F4_CR_STRT); stlink_write_debug32(sl, FLASH_F4_CR, x); @@ -277,7 +277,7 @@ static inline uint32_t read_flash_acr(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) res = stlink_read_debug32(sl, FLASH_F4_SR); else res = stlink_read_debug32(sl, FLASH_SR); @@ -287,7 +287,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { static inline unsigned int is_flash_busy(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); else return read_flash_sr(sl) & (1 << FLASH_SR_BSY); @@ -1014,7 +1014,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector<4) sl->flash_pgsz=0x4000; else if(sector<5) sl->flash_pgsz=0x10000; @@ -1032,7 +1032,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1346,8 +1346,8 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); - } else if (sl->chip_id == STM32_CHIPID_F2 || - sl->chip_id == STM32_CHIPID_F4 || sl->chip_id == STM32_CHIPID_F4_LP) { + } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD){ loader_code = loader_code_stm32f4; loader_size = sizeof(loader_code_stm32f4); } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F0_SMALL) { @@ -1516,7 +1516,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t page_count, sl->flash_pgsz, sl->flash_pgsz); if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_LP)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { /* todo: check write operation */ ILOG("Starting Flash write for F2/F4\n"); @@ -1802,8 +1802,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - } else if (sl->chip_id == STM32_CHIPID_F2 || - sl->chip_id == STM32_CHIPID_F4 || sl->chip_id == STM32_CHIPID_F4_LP) { + } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1856,8 +1856,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - } else if (sl->chip_id == STM32_CHIPID_F2 || - sl->chip_id == STM32_CHIPID_F4 || sl->chip_id == STM32_CHIPID_F4_LP) { + } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { diff --git a/src/stlink-common.h b/src/stlink-common.h index 5d300941e..edf8c6733 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -103,6 +103,7 @@ extern "C" { #define STM32_CHIPID_F3 0x422 #define STM32_CHIPID_F37x 0x432 #define STM32_CHIPID_F4 0x413 +#define STM32_CHIPID_F4_HD 0x419 #define STM32_CHIPID_F4_LP 0x423 #define STM32_CHIPID_F1_HIGH 0x414 #define STM32_CHIPID_L1_MEDIUM 0x416 @@ -184,6 +185,15 @@ static const chip_params_t devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800 }, + { + .chip_id = STM32_CHIPID_F4_HD, + .description = "F42x and F43x device", + .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ + .flash_pagesize = 0x4000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, { .chip_id = STM32_CHIPID_F4_LP, .description = "F4 device (low power)", From c2e22f961dd6ea3e44774131f781d6da230f313a Mon Sep 17 00:00:00 2001 From: Chris Hiszpanski Date: Wed, 23 Oct 2013 22:59:32 -0700 Subject: [PATCH 0235/1435] Fixes issue #161 --- flash/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/flash/main.c b/flash/main.c index 980af63be..8f3a149ba 100644 --- a/flash/main.c +++ b/flash/main.c @@ -146,7 +146,7 @@ int main(int ac, char** av) } } else if ((o.addr >= sl->sram_base) && - (o.addr < sl->sram_base + sl->sram_size)) + (o.addr < sl->sram_base + sl->sram_size)) { err = stlink_fwrite_sram(sl, o.filename, o.addr); if (err == -1) { @@ -154,7 +154,7 @@ int main(int ac, char** av) goto on_error; } } - else if (o.cmd == DO_ERASE) + } else if (o.cmd == DO_ERASE) { err = stlink_erase_flash_mass(sl); if (err == -1) From 5851dee3cd95d7b0276caa22b9d2992c8b1147fa Mon Sep 17 00:00:00 2001 From: Olivier Gay Date: Sun, 27 Oct 2013 15:19:29 +0100 Subject: [PATCH 0236/1435] Fix build issues with MinGW Remove st-term from the list of the targets for MinGW. st-term uses termios and would require a rewrite to have it compile on MinGW. Also remove cleanup signal handlers in gdb-server for MinGW to compile. --- Makefile.am | 9 ++++++++- configure.ac | 4 ++++ gdbserver/gdb-server.c | 4 ++++ 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/Makefile.am b/Makefile.am index ab3201f03..2ddbf475d 100644 --- a/Makefile.am +++ b/Makefile.am @@ -4,7 +4,11 @@ SUBDIRS = . $(MAYBE_GUI) AUTOMAKE_OPTIONS = subdir-objects +if MINGW +bin_PROGRAMS = st-flash st-util st-info +else bin_PROGRAMS = st-flash st-util st-term st-info +endif noinst_LIBRARIES = libstlink.a @@ -18,9 +22,12 @@ CFILES = \ src/stlink-usb.c \ src/stlink-sg.c \ src/uglylogging.c \ - src/st-term.c \ src/st-info.c +if !MINGW +CFILES += src/st-term.c +endif + HFILES = \ src/stlink-common.h \ src/stlink-usb.h \ diff --git a/configure.ac b/configure.ac index 53f827893..f1357b121 100644 --- a/configure.ac +++ b/configure.ac @@ -32,7 +32,11 @@ case "${host}" in *-mingw32*) LIBS="$LIBS -lws2_32" CPPFLAGS="-D__USE_MINGW_ANSI_STDIO=1 $CPPFLAGS" + AC_DEFINE_UNQUOTED(MINGW,1,[This is a MinGW system]) + AM_CONDITIONAL(MINGW, true) ;; + *) + AM_CONDITIONAL(MINGW, false) esac MAYBE_GUI= diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index bf1478122..a6de1b20d 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -57,6 +57,7 @@ typedef struct _st_state_t { int serve(stlink_t *sl, st_state_t *st); char* make_memory_map(stlink_t *sl); +#ifndef __MINGW32__ static void cleanup(int signal __attribute__((unused))) { if (connected_stlink) { /* Switch back to mass storage mode before closing. */ @@ -67,6 +68,7 @@ static void cleanup(int signal __attribute__((unused))) { exit(1); } +#endif @@ -196,8 +198,10 @@ int main(int argc, char** argv) { } connected_stlink = sl; +#ifndef __MINGW32__ signal(SIGINT, &cleanup); signal(SIGTERM, &cleanup); +#endif if (state.reset) { stlink_reset(sl); From c02a84641cb7da10e84af0093420dc1502313465 Mon Sep 17 00:00:00 2001 From: Olivier Gay Date: Sun, 27 Oct 2013 16:17:08 +0100 Subject: [PATCH 0237/1435] Restore gdb-server cleanup handlers for MinGW There were removed in my previous commit 5851dee due to compilation errors. It actually appears these signals are supported in MinGW but there was an include error for MinGW, this commit fixes it. --- gdbserver/gdb-server.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index a6de1b20d..69eadda49 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -18,7 +19,6 @@ #include #include #include -#include #endif #include @@ -57,7 +57,6 @@ typedef struct _st_state_t { int serve(stlink_t *sl, st_state_t *st); char* make_memory_map(stlink_t *sl); -#ifndef __MINGW32__ static void cleanup(int signal __attribute__((unused))) { if (connected_stlink) { /* Switch back to mass storage mode before closing. */ @@ -68,7 +67,6 @@ static void cleanup(int signal __attribute__((unused))) { exit(1); } -#endif @@ -198,10 +196,8 @@ int main(int argc, char** argv) { } connected_stlink = sl; -#ifndef __MINGW32__ signal(SIGINT, &cleanup); signal(SIGTERM, &cleanup); -#endif if (state.reset) { stlink_reset(sl); From 3652f98a5d6c8bbe4707c5764b10e5bb9a13c370 Mon Sep 17 00:00:00 2001 From: Olivier Gay Date: Sun, 27 Oct 2013 17:05:13 +0100 Subject: [PATCH 0238/1435] Fix all compilation warnings --- gdbserver/gdb-server.c | 2 +- src/st-term.c | 10 ++++++++-- src/stlink-common.h | 2 +- src/stlink-usb.c | 2 +- 4 files changed, 11 insertions(+), 5 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 69eadda49..7e8bb685a 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -172,7 +172,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { int main(int argc, char** argv) { - uint32_t voltage; + int32_t voltage; stlink_t *sl = NULL; diff --git a/src/st-term.c b/src/st-term.c index 346cca58f..bbf7ea37e 100644 --- a/src/st-term.c +++ b/src/st-term.c @@ -13,6 +13,11 @@ #define STLINKY_MAGIC 0xDEADF00D +#define READ_UINT32_LE(buf) ((uint32_t) ( buf[0] \ + | buf[1] << 8 \ + | buf[2] << 16 \ + | buf[3] << 24)) + struct stlinky { stlink_t *sl; uint32_t off; @@ -26,11 +31,11 @@ struct stlinky* stlinky_detect(stlink_t* sl) static const uint32_t sram_base = 0x20000000; struct stlinky* st = malloc(sizeof(struct stlinky)); st->sl = sl; - printf("sram: 0x%x bytes @ 0x%x\n", sl->sram_base, sl->sram_size); + printf("sram: 0x%x bytes @ 0x%zx\n", sl->sram_base, sl->sram_size); uint32_t off; for (off = 0; off < sl->sram_size; off += 4) { stlink_read_mem32(sl, sram_base + off, 4); - if ( STLINKY_MAGIC== *(uint32_t*) sl->q_buf) + if (STLINKY_MAGIC == READ_UINT32_LE(sl->q_buf)) { printf("stlinky detected at 0x%x\n", sram_base + off); st->off = sram_base + off; @@ -121,6 +126,7 @@ static int keep_running = 1; static int sigcount=0; void cleanup(int dummy) { + (void) dummy; sigcount++; keep_running = 0; printf("\n\nGot a signal\n"); diff --git a/src/stlink-common.h b/src/stlink-common.h index edf8c6733..579622892 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -397,7 +397,7 @@ static const chip_params_t devices[] = { void (*step) (stlink_t * stl); int (*current_mode) (stlink_t * stl); void (*force_debug) (stlink_t *sl); - uint32_t (*target_voltage) (stlink_t *sl); + int32_t (*target_voltage) (stlink_t *sl); } stlink_backend_t; struct _stlink { diff --git a/src/stlink-usb.c b/src/stlink-usb.c index fa2bd7e08..ec4053ac7 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -203,7 +203,7 @@ void _stlink_usb_version(stlink_t *sl) { } } -int _stlink_usb_target_voltage(stlink_t *sl) { +int32_t _stlink_usb_target_voltage(stlink_t *sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const rdata = sl->q_buf; unsigned char* const cmd = sl->c_buf; From c9ebf53474b1b1f0ca28d33982b2a01122698bfd Mon Sep 17 00:00:00 2001 From: Chris Dew Date: Mon, 28 Oct 2013 15:09:49 +0000 Subject: [PATCH 0239/1435] Added STM32F429I-DISCO --- README | 1 + 1 file changed, 1 insertion(+) diff --git a/README b/README index d717dc22a..cc0fb66ab 100644 --- a/README +++ b/README @@ -167,6 +167,7 @@ Known Working Targets: (https://github.com/UweBonnes/wiki_fuer_alex/layout/usps...) * STM32F303xx (STM32F3 Discovery board) * STM32F407xx (STM32F4 Discovery board) +* STM32F429I-DISCO (STM32F4 Discovery board with LCD) Please report any and all known working combinations so I can update this! From da7aebfdf6c90002c92a2f82384bb79e71b4907a Mon Sep 17 00:00:00 2001 From: texane Date: Tue, 29 Oct 2013 16:13:56 -0500 Subject: [PATCH 0240/1435] [ update ] README, STM32F439VIT6 working as reported by Pawel Kraszewski --- README | 1 + 1 file changed, 1 insertion(+) diff --git a/README b/README index cc0fb66ab..963ccd4a9 100644 --- a/README +++ b/README @@ -168,6 +168,7 @@ Known Working Targets: * STM32F303xx (STM32F3 Discovery board) * STM32F407xx (STM32F4 Discovery board) * STM32F429I-DISCO (STM32F4 Discovery board with LCD) +* STM32F439VIT6 (discovery board reseated CPU) Please report any and all known working combinations so I can update this! From fcdee3bc6dcc31a514ea60f256b92f99d35e225a Mon Sep 17 00:00:00 2001 From: Dan Hepler Date: Wed, 30 Oct 2013 13:14:09 -0700 Subject: [PATCH 0241/1435] Added known working targets STM32L151CB and STM32L152RB. --- README | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README b/README index 963ccd4a9..01751a7cf 100644 --- a/README +++ b/README @@ -169,6 +169,8 @@ Known Working Targets: * STM32F407xx (STM32F4 Discovery board) * STM32F429I-DISCO (STM32F4 Discovery board with LCD) * STM32F439VIT6 (discovery board reseated CPU) +* STM32L151CB (custom board) +* STM32L152RB (STM32L-Discovery board, custom board) Please report any and all known working combinations so I can update this! From 99e8194f7f1b098aa301b66ad75e8c6a3a2b6804 Mon Sep 17 00:00:00 2001 From: Jim Paris Date: Thu, 31 Oct 2013 18:02:55 -0400 Subject: [PATCH 0242/1435] Add --reset option to trigger a reset both before and after flashing. --- flash/main.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/flash/main.c b/flash/main.c index 8f3a149ba..014b627e9 100644 --- a/flash/main.c +++ b/flash/main.c @@ -17,13 +17,14 @@ struct opts const char* filename; stm32_addr_t addr; size_t size; + int reset; }; static void usage(void) { - puts("stlinkv1 command line: ./flash {read|write} /dev/sgX path addr "); + puts("stlinkv1 command line: ./flash [--reset] {read|write} /dev/sgX path addr "); puts("stlinkv1 command line: ./flash /dev/sgX erase"); - puts("stlinkv2 command line: ./flash {read|write} path addr "); + puts("stlinkv2 command line: ./flash [--reset] {read|write} path addr "); puts("stlinkv2 command line: ./flash erase"); puts(" use hex format for addr and "); } @@ -37,6 +38,17 @@ static int get_opts(struct opts* o, int ac, char** av) if (ac < 1) return -1; + if (strcmp(av[0], "--reset") == 0) + { + o->reset = 1; + ac--; + av++; + } + else + { + o->reset = 0; + } + /* stlinkv2 */ o->devname = NULL; @@ -123,6 +135,9 @@ int main(int ac, char** av) if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); + if (o.reset) + stlink_reset(sl); + // Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 if (sl->chip_id == STM32_CHIPID_F4) { @@ -179,6 +194,9 @@ int main(int ac, char** av) } } + if (o.reset) + stlink_reset(sl); + /* success */ err = 0; From badeef227a1705d9ecb5521266b88065b8b59795 Mon Sep 17 00:00:00 2001 From: Onno Kortmann Date: Fri, 6 Dec 2013 20:30:01 -0800 Subject: [PATCH 0243/1435] Properly detect and warn if multiple stlinky magic bytes are detected Stlinky can silently fail if its magic bytes are present anywhere else in the SRAM. This change makes st-term detect all stlinky structures, warn about multiple occurences and will use the last one detected. --- src/st-term.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/st-term.c b/src/st-term.c index bbf7ea37e..a6a97fc1c 100644 --- a/src/st-term.c +++ b/src/st-term.c @@ -30,6 +30,7 @@ struct stlinky* stlinky_detect(stlink_t* sl) { static const uint32_t sram_base = 0x20000000; struct stlinky* st = malloc(sizeof(struct stlinky)); + int multiple=0; st->sl = sl; printf("sram: 0x%x bytes @ 0x%zx\n", sl->sram_base, sl->sram_size); uint32_t off; @@ -37,14 +38,22 @@ struct stlinky* stlinky_detect(stlink_t* sl) stlink_read_mem32(sl, sram_base + off, 4); if (STLINKY_MAGIC == READ_UINT32_LE(sl->q_buf)) { + if (multiple > 0) + printf("WARNING: another "); printf("stlinky detected at 0x%x\n", sram_base + off); st->off = sram_base + off; stlink_read_mem32(sl, st->off + 4, 4); st->bufsize = (size_t) *(unsigned char*) sl->q_buf; printf("stlinky buffer size 0x%zu \n", st->bufsize); - return st; + multiple++; } } + if (multiple > 0) { + if (multiple > 1) { + printf("Using last stlinky structure detected\n"); + } + return st; + } return NULL; } From 93c070d84c00bf3f6fa75d41ddacbdd0bb757f5a Mon Sep 17 00:00:00 2001 From: Rene Hopf Date: Wed, 11 Dec 2013 20:31:37 +0100 Subject: [PATCH 0244/1435] st-term magic byte via commandline argument --- .gitignore | 1 + src/st-term.c | 22 ++++++++++++++++------ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/.gitignore b/.gitignore index d7df95e81..090257037 100644 --- a/.gitignore +++ b/.gitignore @@ -21,6 +21,7 @@ compile st-flash st-util st-term +st-info test_usb test_sg *.deps* diff --git a/src/st-term.c b/src/st-term.c index a6a97fc1c..4f2f9f77c 100644 --- a/src/st-term.c +++ b/src/st-term.c @@ -39,7 +39,7 @@ struct stlinky* stlinky_detect(stlink_t* sl) if (STLINKY_MAGIC == READ_UINT32_LE(sl->q_buf)) { if (multiple > 0) - printf("WARNING: another "); + printf("WARNING: another "); printf("stlinky detected at 0x%x\n", sram_base + off); st->off = sram_base + off; stlink_read_mem32(sl, st->off + 4, 4); @@ -148,10 +148,8 @@ void cleanup(int dummy) int main(int ac, char** av) { stlink_t* sl; - - /* unused */ - ac = ac; - av = av; + struct stlinky *st; + sl = stlink_open_usb(10, 1); if (sl != NULL) { printf("ST-Linky proof-of-concept terminal :: Created by Necromant for lulz\n"); @@ -174,7 +172,19 @@ int main(int ac, char** av) { /* TODO: Make timeout adjustable via command line */ sleep(1); - struct stlinky *st = stlinky_detect(sl); + if(ac == 1){ + st = stlinky_detect(sl); + }else if(ac == 2){ + st = malloc(sizeof(struct stlinky)); + st->sl = sl; + st->off = (int)strtol(av[1], NULL, 16); + printf("using stlinky at 0x%x\n", st->off); + stlink_read_mem32(sl, st->off + 4, 4); + st->bufsize = (size_t) *(unsigned char*) sl->q_buf; + printf("stlinky buffer size 0x%zu \n", st->bufsize); + }else{ + goto bailout; + } if (st == NULL) { printf("stlinky magic not found in sram :(\n"); From 9bb1a0c3d73f400cb4874a6bd17bf4b03b88bd74 Mon Sep 17 00:00:00 2001 From: texane Date: Wed, 11 Dec 2013 22:48:40 -0600 Subject: [PATCH 0245/1435] [ fix ] ident typo --- src/st-term.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/st-term.c b/src/st-term.c index 4f2f9f77c..7f18425db 100644 --- a/src/st-term.c +++ b/src/st-term.c @@ -38,8 +38,7 @@ struct stlinky* stlinky_detect(stlink_t* sl) stlink_read_mem32(sl, sram_base + off, 4); if (STLINKY_MAGIC == READ_UINT32_LE(sl->q_buf)) { - if (multiple > 0) - printf("WARNING: another "); + if (multiple > 0) printf("WARNING: another "); printf("stlinky detected at 0x%x\n", sram_base + off); st->off = sram_base + off; stlink_read_mem32(sl, st->off + 4, 4); From 3c6d6293dd7a5d2ca70f441582b1042834dc7d66 Mon Sep 17 00:00:00 2001 From: Jan Sarenik Date: Wed, 18 Dec 2013 09:24:51 +0100 Subject: [PATCH 0246/1435] stlinkv1_macosx_driver: add Mavericks The diff was as easy as adding a new select option for 10.9 version in install.sh, and a little patch fixing com.apple.kpi.libkern version string. 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+sigset_t sig_mask; + struct stlinky { stlink_t *sl; uint32_t off; size_t bufsize; }; +void nonblock(int state); + +static void cleanup(int signal __attribute__((unused))) { + if (sl) { + /* Switch back to mass storage mode before closing. */ + stlink_run(sl); + stlink_exit_debug_mode(sl); + stlink_close(sl); + } + + printf("\n"); + nonblock(0); + exit(1); +} + +void sig_init() { + sigemptyset(&sig_mask); + sigaddset(&sig_mask, SIGINT); + sigaddset(&sig_mask, SIGTERM); + signal(SIGINT, &cleanup); + signal(SIGTERM, &cleanup); + sigprocmask(SIG_BLOCK, &sig_mask, NULL); +} + +void sig_process() { + sigset_t pending; + sigpending(&pending); + if (sigismember(&pending, SIGINT) || sigismember(&pending, SIGTERM)) { + sigprocmask(SIG_UNBLOCK, &sig_mask, NULL); + sigsuspend(&pending); + sigprocmask(SIG_BLOCK, &sig_mask, NULL); + } +} /* Detects stlinky in RAM, returns handler */ struct stlinky* stlinky_detect(stlink_t* sl) @@ -35,6 +71,7 @@ struct stlinky* stlinky_detect(stlink_t* sl) printf("sram: 0x%x bytes @ 0x%zx\n", sl->sram_base, sl->sram_size); uint32_t off; for (off = 0; off < sl->sram_size; off += 4) { + if (off % 1024 == 0) sig_process(); stlink_read_mem32(sl, sram_base + off, 4); if (STLINKY_MAGIC == READ_UINT32_LE(sl->q_buf)) { @@ -130,25 +167,11 @@ void nonblock(int state) } -static int keep_running = 1; -static int sigcount=0; -void cleanup(int dummy) -{ - (void) dummy; - sigcount++; - keep_running = 0; - printf("\n\nGot a signal\n"); - if (sigcount==2) { - printf("\n\nGot a second signal - bailing out\n"); - exit(1); - } -} - - int main(int ac, char** av) { - stlink_t* sl; struct stlinky *st; + sig_init(); + sl = stlink_open_usb(10, 1); if (sl != NULL) { printf("ST-Linky proof-of-concept terminal :: Created by Necromant for lulz\n"); @@ -182,12 +205,12 @@ int main(int ac, char** av) { st->bufsize = (size_t) *(unsigned char*) sl->q_buf; printf("stlinky buffer size 0x%zu \n", st->bufsize); }else{ - goto bailout; + cleanup(0); } if (st == NULL) { printf("stlinky magic not found in sram :(\n"); - goto bailout; + cleanup(0); } char* rxbuf = malloc(st->bufsize); char* txbuf = malloc(st->bufsize); @@ -196,9 +219,9 @@ int main(int ac, char** av) { int fd = fileno(stdin); int saved_flags = fcntl(fd, F_GETFL); fcntl(fd, F_SETFL, saved_flags & ~O_NONBLOCK); - signal(SIGINT, cleanup); printf("Entering interactive terminal. CTRL+C to exit\n\n\n"); while(1) { + sig_process(); if (stlinky_canrx(st)) { tmp = stlinky_rx(st, rxbuf); fwrite(rxbuf,tmp,1,stdout); @@ -208,13 +231,7 @@ int main(int ac, char** av) { tmp = read(fd, txbuf, st->bufsize); stlinky_tx(st,txbuf,tmp); } - if (!keep_running) - break; } - bailout: - nonblock(0); - stlink_exit_debug_mode(sl); - stlink_close(sl); } return 0; } From 2e6ba2093588536214edd0da0cf09eaa9a9da014 Mon Sep 17 00:00:00 2001 From: Jonas Norling Date: Wed, 22 Jan 2014 21:48:35 +0100 Subject: [PATCH 0248/1435] Correct address for STM32F2 flash size register There was a typo in the flash size register address for STM32F2. Change to correct address. Verified against STM32F207 reference manual (RM0033 Rev 5 section 33.2), and an STM32F217 chip. --- src/stlink-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.h b/src/stlink-common.h index 579622892..ee16d5a63 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -161,7 +161,7 @@ static const chip_params_t devices[] = { { // table 1, PM0059 .chip_id = STM32_CHIPID_F2, .description = "F2 device", - .flash_size_reg = 0x1ff7a22, /* RM0033 sind Rev 4*/ + .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/ .flash_pagesize = 0x20000, .sram_size = 0x20000, .bootrom_base = 0x1fff0000, From a4ff7ba1f4c81a3bfbf4eb284233f65b713d502b Mon Sep 17 00:00:00 2001 From: Jonas Norling Date: Wed, 22 Jan 2014 22:10:52 +0100 Subject: [PATCH 0249/1435] Remove unsupported --device option to st-util Setting the STLINK device with -d hasn't worked for some time, but the STLINK_DEVICE environment variable works instead. Remove the option, update documentation and help text. --- README | 20 ++++++++++++++------ gdbserver/gdb-server.c | 24 ++++++++---------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/README b/README index 01751a7cf..853c51826 100644 --- a/README +++ b/README @@ -55,14 +55,22 @@ There are a few options: ./st-util - usage: - -h, --help Print this help - -vXX, --verbose=XX specify a specific verbosity level (0..99) - -v, --verbose specify generally verbose logging + -h, --help Print this help + -vXX, --verbose=XX Specify a specific verbosity level (0..99) + -v, --verbose Specify generally verbose logging -s X, --stlink_version=X - Choose what version of stlink to use, (defaults to 2) - -1, --stlinkv1 Force stlink version 1 + Choose what version of stlink to use, (defaults to 2) + -1, --stlinkv1 Force stlink version 1 -p 4242, --listen_port=1234 - Set the gdb server listen port. (default port: 4242) + Set the gdb server listen port. (default port: 4242) + -m, --multi + Set gdb server to extended mode. + st-util will continue listening for connections after disconnect. + -n, --no-reset + Do not reset board on connection. + +The STLINKv2 device to use can be specified in the environment +variable STLINK_DEVICE on the format :. Then, in your project directory, someting like this... (remember, you need to run an _ARM_ gdb, not an x86 gdb) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 7e8bb685a..13902ee03 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -45,10 +45,8 @@ static const char* current_memory_map = NULL; typedef struct _st_state_t { // things from command line, bleh int stlink_version; - // "/dev/serial/by-id/usb-FTDI_TTL232R-3V3_FTE531X6-if00-port0" is only 58 chars - char devicename[100]; int logging_level; - int listen_port; + int listen_port; int persistent; int reset; } st_state_t; @@ -74,7 +72,6 @@ int parse_options(int argc, char** argv, st_state_t *st) { static struct option long_options[] = { {"help", no_argument, NULL, 'h'}, {"verbose", optional_argument, NULL, 'v'}, - {"device", required_argument, NULL, 'd'}, {"stlink_version", required_argument, NULL, 's'}, {"stlinkv1", no_argument, NULL, '1'}, {"listen_port", required_argument, NULL, 'p'}, @@ -84,10 +81,8 @@ int parse_options(int argc, char** argv, st_state_t *st) { }; const char * help_str = "%s - usage:\n\n" " -h, --help\t\tPrint this help\n" - " -vXX, --verbose=XX\tspecify a specific verbosity level (0..99)\n" - " -v, --verbose\tspecify generally verbose logging\n" - " -d , --device=/dev/stlink2_1\n" - "\t\t\tWhere is your stlink device connected?\n" + " -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n" + " -v, --verbose\t\tSpecify generally verbose logging\n" " -s X, --stlink_version=X\n" "\t\t\tChoose what version of stlink to use, (defaults to 2)\n" " -1, --stlinkv1\tForce stlink version 1\n" @@ -99,13 +94,17 @@ int parse_options(int argc, char** argv, st_state_t *st) { "\t\t\tst-util will continue listening for connections after disconnect.\n" " -n, --no-reset\n" "\t\t\tDo not reset board on connection.\n" + "\n" + "The STLINKv2 device to use can be specified in the environment\n" + "variable STLINK_DEVICE on the format :.\n" + "\n" ; int option_index = 0; int c; int q; - while ((c = getopt_long(argc, argv, "hv::d:s:1p:mn", long_options, &option_index)) != -1) { + while ((c = getopt_long(argc, argv, "hv::s:1p:mn", long_options, &option_index)) != -1) { switch (c) { case 0: printf("XXXXX Shouldn't really normally come here, only if there's no corresponding option\n"); @@ -125,13 +124,6 @@ int parse_options(int argc, char** argv, st_state_t *st) { } else { st->logging_level = DEFAULT_LOGGING_LEVEL; } - break; - case 'd': - if (strlen(optarg) > sizeof (st->devicename)) { - fprintf(stderr, "device name too long: %zd\n", strlen(optarg)); - } else { - strcpy(st->devicename, optarg); - } break; case '1': st->stlink_version = 1; From cd9dbe4b061902a15413c4f3d14ea0a4e90f9510 Mon Sep 17 00:00:00 2001 From: texane Date: Sat, 25 Jan 2014 08:07:57 -0600 Subject: [PATCH 0250/1435] [ add ] INSTALL.mingw using dandev37 comments --- INSTALL.mingw | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 INSTALL.mingw diff --git a/INSTALL.mingw b/INSTALL.mingw new file mode 100644 index 000000000..5cd8cca11 --- /dev/null +++ b/INSTALL.mingw @@ -0,0 +1,41 @@ +from dandev37: + +Here's a step by step from a clean install to successfully setup MinGW and build +libusb-1.0 and stlink for MS Windows. Hopefully this helps someone. + +1. Install MinGW and MSYS to C:\MinGW with the graphical installer from +http://sourceforge.net/projects/mingw/files/Installer/mingw-get-setup.exe/download +and add these packages: +mingw32-base +mingw-developer-toolkit + +2. Add C:\MinGW\bin to your path. + +3. Create the C:\MinGW\msys\1.0\etc\fstab file to mount C:\MinGW as /mingw as per +http://www.mingw.org/wiki/MSYS: + +#Win32_Path Mount_Point +c:/mingw /mingw + +4. Download these three glib, pkg-config, pkg-config-dev archives and extract +contents to C:\MinGW +http://win32builder.gnome.org/packages/3.6/glib_2.34.3-1_win32.zip +http://win32builder.gnome.org/packages/3.6/pkg-config_0.28-1_win32.zip +http://win32builder.gnome.org/packages/3.6/pkg-config-dev_0.28-1_win32.zip + +5. Download latest libusb-1.0 source from git://git.libusb.org/libusb.git and +build (prefix as per http://www.mingw.org/wiki/MSYS) + +./autogen.sh +./configure --prefix=/mingw +make +make install + +6. Repeat for stlink source from https://github.com/texane/stlink + +./autogen.sh +./configure --prefix=/mingw +make +make install + +7. Enjoy the fruits of the stlink developers. From bc49ed608e0fdfde92dbfd0b462456c8269f2faa Mon Sep 17 00:00:00 2001 From: texane Date: Sun, 26 Jan 2014 11:39:59 -0600 Subject: [PATCH 0251/1435] [ update ] INSTALL.mingw using Vanya comments --- INSTALL.mingw | 1 + 1 file changed, 1 insertion(+) diff --git a/INSTALL.mingw b/INSTALL.mingw index 5cd8cca11..56220101e 100644 --- a/INSTALL.mingw +++ b/INSTALL.mingw @@ -10,6 +10,7 @@ mingw32-base mingw-developer-toolkit 2. Add C:\MinGW\bin to your path. +Note: a user reports she had to use c:\MinGW\msys\1.0\bin 3. Create the C:\MinGW\msys\1.0\etc\fstab file to mount C:\MinGW as /mingw as per http://www.mingw.org/wiki/MSYS: From 5dcd45d8a48aaead2a2d1d1b9c36ab14f507628b Mon Sep 17 00:00:00 2001 From: Jim Paris Date: Fri, 31 Jan 2014 16:26:35 -0500 Subject: [PATCH 0252/1435] When ignoring the end of a file, make sure we don't ignore partial words. Consider a 128-byte write to the chip. If the last 2 bytes are considered "empty", then len is adjusted to 126, and run_flash_loader will only copy 126 bytes to RAM. However, run_flash_loader then proceeds to round up to 32 words (128 bytes) when flashing, which has the effect of clobbering those last two "empty" bytes with junk data. --- src/stlink-common.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index b7645fe88..b942dea06 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1752,8 +1752,10 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { else num_empty = 0; } + /* Round down to words */ + num_empty -= (num_empty & 3); if(num_empty != 0) { - ILOG("Ignoring %d bytes of Zeros at end of file\n",num_empty); + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); mf.len -= num_empty; } err = stlink_write_flash(sl, addr, mf.base, mf.len); From fdcb50e0de9eedd99d7f1c501f7c0d8d9c32f876 Mon Sep 17 00:00:00 2001 From: Jens Hoffmann Date: Thu, 20 Feb 2014 13:28:04 +0100 Subject: [PATCH 0253/1435] Added support for ST nucleo devices. Nucleo boards using the same endpoint for IN and OUT (1). This patch fix it. --- 49-stlinkv2-1.rules | 12 ++++++++++++ src/stlink-common.h | 21 +++++++++++---------- src/stlink-usb.c | 9 +++++++-- 3 files changed, 30 insertions(+), 12 deletions(-) create mode 100644 49-stlinkv2-1.rules diff --git a/49-stlinkv2-1.rules b/49-stlinkv2-1.rules new file mode 100644 index 000000000..a5a79b91c --- /dev/null +++ b/49-stlinkv2-1.rules @@ -0,0 +1,12 @@ +# stm32 nucleo boards, with onboard st/linkv2-1 +# ie, STM32F0, STM32F4. +# STM32VL has st/linkv1, which is quite different + +SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ + MODE:="0666", \ + SYMLINK+="stlinkv2-1_%n" + +# If you share your linux system with other users, or just don't like the +# idea of write permission for everybody, you can replace MODE:="0666" with +# OWNER:="yourusername" to create the device owned by you, or with +# GROUP:="somegroupname" and mange access using standard unix groups. diff --git a/src/stlink-common.h b/src/stlink-common.h index ee16d5a63..400560408 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -1,7 +1,7 @@ -/* +/* * File: stlink-common.h * Bulk import from stlink-hw.h - * + * * This should contain all the common top level stlink interfaces, regardless * of how the backend does the work.... */ @@ -24,6 +24,7 @@ extern "C" { #define USB_ST_VID 0x0483 #define USB_STLINK_PID 0x3744 #define USB_STLINK_32L_PID 0x3748 +#define USB_STLINK_NUCLEO_PID 0x374b // STLINK_DEBUG_RESETSYS, etc: #define STLINK_OK 0x80 @@ -67,7 +68,7 @@ extern "C" { #define STLINK_DEBUG_WRITEDEBUGREG 0x0f #define STLINK_DEBUG_ENTER_SWD 0xa3 #define STLINK_DEBUG_ENTER_JTAG 0x00 - + // TODO - possible poor names... #define STLINK_SWD_ENTER 0x30 #define STLINK_SWD_READCOREID 0x32 // TBD @@ -144,8 +145,8 @@ extern "C" { uint32_t sram_size; uint32_t bootrom_base, bootrom_size; } chip_params_t; - - + + // These maps are from a combination of the Programming Manuals, and // also the Reference manuals. (flash size reg is normally in ref man) static const chip_params_t devices[] = { @@ -324,7 +325,7 @@ static const chip_params_t devices[] = { }, }; - + typedef struct { uint32_t r[16]; uint32_t s[32]; @@ -341,7 +342,7 @@ static const chip_params_t devices[] = { } reg; typedef uint32_t stm32_addr_t; - + typedef struct _cortex_m3_cpuid_ { uint16_t implementer_id; uint16_t variant; @@ -431,7 +432,7 @@ static const chip_params_t devices[] = { #define STM32L_SRAM_SIZE (16 * 1024) stm32_addr_t sram_base; size_t sram_size; - + // bootloader stm32_addr_t sys_base; size_t sys_size; @@ -476,7 +477,7 @@ static const chip_params_t devices[] = { int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); - + // PUBLIC uint32_t stlink_chip_id(stlink_t *sl); void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); @@ -502,7 +503,7 @@ static const chip_params_t devices[] = { #include "stlink-sg.h" -#include "stlink-usb.h" +#include "stlink-usb.h" diff --git a/src/stlink-usb.c b/src/stlink-usb.c index ec4053ac7..fe841833d 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -782,7 +782,7 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { if (desc.idVendor!=USB_ST_VID) continue; if (devBus && devAddr) if ((libusb_get_bus_number(list[cnt])!=devBus) || (libusb_get_device_address(list[cnt])!=devAddr)) continue; - if (desc.idProduct == USB_STLINK_32L_PID) break; + if ( (desc.idProduct == USB_STLINK_32L_PID) || (desc.idProduct == USB_STLINK_NUCLEO_PID) ) break; if (desc.idProduct == USB_STLINK_PID) { slu->protocoll = 1; break; @@ -843,9 +843,14 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { WLOG("libusb_alloc_transfer failed\n"); goto on_libusb_error; } + // TODO - could use the scanning techniq from stm8 code here... slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; - slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; + if (desc.idProduct == USB_STLINK_NUCLEO_PID) { + slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; + } else { + slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; + } slu->sg_transfer_idx = 0; // TODO - never used at the moment, always CMD_SIZE From 83e9f70dd83d2f14f7297f1968724edc778589e5 Mon Sep 17 00:00:00 2001 From: Jens Hoffmann Date: Fri, 21 Feb 2014 15:12:16 +0100 Subject: [PATCH 0254/1435] Added STM32F401RE chip id. Nucleo F401RE board got 512K flash and 96K sram. This commit adds device definition for this controller. --- src/stlink-common.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/stlink-common.h b/src/stlink-common.h index 400560408..8430fc55d 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -106,6 +106,7 @@ extern "C" { #define STM32_CHIPID_F4 0x413 #define STM32_CHIPID_F4_HD 0x419 #define STM32_CHIPID_F4_LP 0x423 +#define STM32_CHIPID_F4_DE 0x433 #define STM32_CHIPID_F1_HIGH 0x414 #define STM32_CHIPID_L1_MEDIUM 0x416 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427 @@ -204,6 +205,15 @@ static const chip_params_t devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800 }, + { + .chip_id = STM32_CHIPID_F4_DE, + .description = "F4 device (Dynamic Efficency)", + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, { .chip_id = STM32_CHIPID_F1_HIGH, .description = "F1 High-density device", From 746d0201a7f753b20078b1e6d293b81d3b7d0822 Mon Sep 17 00:00:00 2001 From: dandev37 Date: Fri, 28 Feb 2014 12:23:51 -0800 Subject: [PATCH 0255/1435] Update MinGW instructions for USB 3.0 hub support. Report libusb_open() error code to the user. --- INSTALL.mingw | 6 ++++-- src/stlink-usb.c | 35 ++++++++++++++++++----------------- 2 files changed, 22 insertions(+), 19 deletions(-) diff --git a/INSTALL.mingw b/INSTALL.mingw index 56220101e..c8df0fd70 100644 --- a/INSTALL.mingw +++ b/INSTALL.mingw @@ -24,8 +24,10 @@ http://win32builder.gnome.org/packages/3.6/glib_2.34.3-1_win32.zip http://win32builder.gnome.org/packages/3.6/pkg-config_0.28-1_win32.zip http://win32builder.gnome.org/packages/3.6/pkg-config-dev_0.28-1_win32.zip -5. Download latest libusb-1.0 source from git://git.libusb.org/libusb.git and -build (prefix as per http://www.mingw.org/wiki/MSYS) +5. Download latest libusb-1.0 source from +https://github.com/libusb/libusb (newer repo, includes USB 3.0 hub support) +OR the old git://git.libusb.org/libusb.git (original repo, NO USB 3.0 support) +and build (prefix as per http://www.mingw.org/wiki/MSYS) ./autogen.sh ./configure --prefix=/mingw diff --git a/src/stlink-usb.c b/src/stlink-usb.c index fe841833d..8e910bcf2 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -150,7 +150,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, (handle->rep_trans, handle->usb_handle, handle->ep_rep, sg_buf, 13, NULL, NULL, 0); res = submit_wait(handle, handle->rep_trans); - /* The STLink doesn't seem to evaluate the sequence number */ + /* The STLink doesn't seem to evaluate the sequence number */ handle->sg_transfer_idx++; if (res ) return -1; } @@ -766,18 +766,18 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { char *device = getenv("STLINK_DEVICE"); if (device) { - char *c = strchr(device,':'); - if (c==NULL) { - WLOG("STLINK_DEVICE must be : format\n"); - goto on_error; - } - devBus=atoi(device); - *c++=0; - devAddr=atoi(c); - ILOG("bus %03d dev %03d\n",devBus, devAddr); + char *c = strchr(device,':'); + if (c==NULL) { + WLOG("STLINK_DEVICE must be : format\n"); + goto on_error; + } + devBus=atoi(device); + *c++=0; + devAddr=atoi(c); + ILOG("bus %03d dev %03d\n",devBus, devAddr); } while (cnt){ - cnt--; + cnt--; libusb_get_device_descriptor( list[cnt], &desc ); if (desc.idVendor!=USB_ST_VID) continue; if (devBus && devAddr) @@ -790,13 +790,14 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { } if (cnt < 0) { - WLOG ("Couldn't find %s ST-Link/V2 devices\n",(devBus && devAddr)?"matched":"any"); - goto on_error; + WLOG ("Couldn't find %s ST-Link/V2 devices\n",(devBus && devAddr)?"matched":"any"); + goto on_error; } else { - if( libusb_open(list[cnt], &slu->usb_handle) !=0){ - WLOG("Couldn't open ST-Link/V2 device %03d:%03d\n",libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); - goto on_error; - } + int error = libusb_open(list[cnt], &slu->usb_handle); + if( error !=0 ) { + WLOG("Error %d opening ST-Link/V2 device %03d:%03d\n", error, libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); + goto on_error; + } } libusb_free_device_list(list, 1); From 71d0958873abc358aff8e4874b0d2e2f8e083040 Mon Sep 17 00:00:00 2001 From: tekaikko Date: Wed, 5 Mar 2014 15:19:49 +0100 Subject: [PATCH 0256/1435] Update stlink-common.h Adding support for STM32F07x CAN connectivity devices --- src/stlink-common.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/stlink-common.h b/src/stlink-common.h index 8430fc55d..b70ba9e15 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -123,6 +123,7 @@ extern "C" { #define STM32_CHIPID_F1_XL 0x430 #define STM32_CHIPID_F0 0x440 #define STM32_CHIPID_F0_SMALL 0x444 +#define STM32_CHIPID_F0_CAN 0x448 // Constant STM32 memory map figures #define STM32_FLASH_BASE 0x08000000 @@ -311,6 +312,17 @@ static const chip_params_t devices[] = { .bootrom_base = 0x1fffe000, .bootrom_size = 0x1800 }, + { + //Use this as an example for mapping future chips: + //RM0091 document was used to find these paramaters + .chip_id = STM32_CHIPID_F0_CAN, + .description = "F07x device", + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 + .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 + .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2 + }, { //Use this as an example for mapping future chips: //RM0091 document was used to find these paramaters From 2121354caf99360d90f59961f3bea168dd144cce Mon Sep 17 00:00:00 2001 From: tekaikko Date: Wed, 5 Mar 2014 15:21:03 +0100 Subject: [PATCH 0257/1435] Update stlink-common.c Adding support for STM32F07x CAN connectivity devices --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index b942dea06..c7cc24a6c 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1350,7 +1350,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD){ loader_code = loader_code_stm32f4; loader_size = sizeof(loader_code_stm32f4); - } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F0_SMALL) { + } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); } else { From 0b88c379c32e8b1567c1afbfdf102e7265fa5813 Mon Sep 17 00:00:00 2001 From: tekaikko Date: Wed, 5 Mar 2014 15:22:34 +0100 Subject: [PATCH 0258/1435] Update stlink-common.c fix typo --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index c7cc24a6c..bf9f389f8 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1350,7 +1350,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD){ loader_code = loader_code_stm32f4; loader_size = sizeof(loader_code_stm32f4); - } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL) { + } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); } else { From 94c7ac86dcb2a18ab4b2b60309892f6102a53205 Mon Sep 17 00:00:00 2001 From: Sean Simmons Date: Sat, 8 Mar 2014 11:21:16 -0500 Subject: [PATCH 0259/1435] * Improved support for STM32L152RE - flash/ram sizes, now correct, flash programming works. * Cleaned up checking of FP_CTRL register in gdb-server.c * Added source code for stm32lx.s flashloader - just for reference. --- flashloaders/stm32lx.s | 63 ++++++++++++++++++++++++++++++++++++++++++ gdbserver/gdb-server.c | 11 ++++++-- src/st-term.c | 2 +- src/stlink-common.c | 16 +++++------ src/stlink-common.h | 11 +++++++- 5 files changed, 91 insertions(+), 12 deletions(-) create mode 100644 flashloaders/stm32lx.s diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s new file mode 100644 index 000000000..6e8ccb089 --- /dev/null +++ b/flashloaders/stm32lx.s @@ -0,0 +1,63 @@ +/*************************************************************************** + * Copyright (C) 2010 by Spencer Oliver * + * spen@spen-soft.co.uk * + * * + * Copyright (C) 2011 Øyvind Harboe * + * oyvind.harboe@zylin.com * + * * + * Copyright (C) 2011 Clement Burin des Roziers * + * clement.burin-des-roziers@hikob.com * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ + + +// Build : arm-eabi-gcc -c stm32lx.S + .text + .syntax unified + .cpu cortex-m3 + .thumb + .thumb_func + .global write + +/* + r0 - destination address + r1 - source address + r2 - count +*/ + + // Set 0 to r3 + movs r3, #0 + // Go to compare + b.n test_done + +write_word: + // Load one word from address in r0, increment by 4 + ldr.w ip, [r1], #4 + // Store the word to address in r1, increment by 4 + str.w ip, [r0], #4 + // Increment r3 + adds r3, #1 + +test_done: + // Compare r3 and r2 + cmp r3, r2 + // Loop if not zero + bcc.n write_word + + // Set breakpoint to exit + bkpt #0x00 + diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 13902ee03..459d1012b 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -472,6 +472,7 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) } #define CODE_BREAK_NUM 6 +#define CODE_LIT_NUM 2 #define CODE_BREAK_LOW 0x01 #define CODE_BREAK_HIGH 0x02 @@ -485,8 +486,14 @@ struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM]; static void init_code_breakpoints(stlink_t *sl) { memset(sl->q_buf, 0, 4); stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/); - printf("KARL - should read back as 0x03, not 60 02 00 00\n"); - stlink_read_debug32(sl, CM3_REG_FP_CTRL); + unsigned int val = stlink_read_debug32(sl, CM3_REG_FP_CTRL); + if (((val & 3) != 1) || + ((((val >> 8) & 0x70) | ((val >> 4) & 0xf)) != CODE_BREAK_NUM) || + (((val >> 8) & 0xf) != CODE_LIT_NUM)){ + fprintf(stderr, "[FP_CTRL] = 0x%08x expecting 0x%08x\n", val, + ((CODE_BREAK_NUM & 0x70) << 8) | (CODE_LIT_NUM << 8) | ((CODE_BREAK_NUM & 0xf) << 4) | 1); + } + for(int i = 0; i < CODE_BREAK_NUM; i++) { code_breaks[i].type = 0; diff --git a/src/st-term.c b/src/st-term.c index 241518e7a..6881f6218 100644 --- a/src/st-term.c +++ b/src/st-term.c @@ -168,7 +168,7 @@ void nonblock(int state) } int main(int ac, char** av) { - struct stlinky *st; + struct stlinky *st=NULL; sig_init(); diff --git a/src/stlink-common.c b/src/stlink-common.c index bf9f389f8..86eca084f 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -931,7 +931,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) size_t off; int num_empty = 0; unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH) ? 0:0xff; + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -1059,7 +1059,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { uint32_t val; @@ -1169,7 +1169,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) int stlink_erase_flash_mass(stlink_t *sl) { if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { /* erase each page */ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1340,7 +1340,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { size_t loader_size; if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH ) { /* stm32l */ + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { @@ -1583,7 +1583,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } //STM32F4END else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH ) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { /* use fast word write. todo: half page. */ uint32_t val; @@ -1740,7 +1740,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { int err; unsigned int num_empty = 0, index; unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH )?0:0xff; + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE )?0:0xff; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { ELOG("map_file() == -1\n"); @@ -1781,7 +1781,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH ) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1839,7 +1839,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons /* check written byte count */ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH ) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; diff --git a/src/stlink-common.h b/src/stlink-common.h index b70ba9e15..cce4d9f3e 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -117,6 +117,7 @@ extern "C" { * 0x436 HIGH. */ #define STM32_CHIPID_L1_HIGH 0x436 +#define STM32_CHIPID_L152_RE 0x437 #define STM32_CHIPID_F1_CONN 0x418 #define STM32_CHIPID_F1_VL_MEDIUM 0x420 #define STM32_CHIPID_F1_VL_HIGH 0x428 @@ -253,7 +254,15 @@ static const chip_params_t devices[] = { .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000 }, - + { + .chip_id = STM32_CHIPID_L152_RE, + .description = "L152RE", + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/ + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, { .chip_id = STM32_CHIPID_F1_CONN, .description = "F1 Connectivity line device", From 9b1c00452a251fe516dd0248fbdf05990d217710 Mon Sep 17 00:00:00 2001 From: Pete Date: Mon, 10 Mar 2014 14:32:09 -0400 Subject: [PATCH 0260/1435] Fix segv if only --reset option given We didn't recheck that there are enough parameters after shifting the --reset option off the list. --- flash/main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/flash/main.c b/flash/main.c index 014b627e9..d550eeeed 100644 --- a/flash/main.c +++ b/flash/main.c @@ -48,6 +48,8 @@ static int get_opts(struct opts* o, int ac, char** av) { o->reset = 0; } + + if (ac < 1) return -1; /* stlinkv2 */ o->devname = NULL; From 4531918c9706cbe4a9eadeb3112a0136e21db0c7 Mon Sep 17 00:00:00 2001 From: texane Date: Thu, 13 Mar 2014 07:28:40 -0500 Subject: [PATCH 0261/1435] [ update ] flash support for the STM32F401XX (installed on the nucleo F4 boards) --- src/stlink-common.c | 50 ++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 86eca084f..0d11a63eb 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -143,7 +143,7 @@ static inline uint32_t read_flash_obr(stlink_t *sl) { static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t res; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) res = stlink_read_debug32(sl, FLASH_F4_CR); else @@ -156,7 +156,7 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); else @@ -169,7 +169,7 @@ static void unlock_flash(stlink_t *sl) { an invalid sequence results in a definitive lock of the FPEC block until next reset. */ - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); @@ -195,7 +195,7 @@ static int unlock_flash_if(stlink_t *sl) { } static void lock_flash(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); stlink_write_debug32(sl, FLASH_F4_CR, n); @@ -208,7 +208,7 @@ static void lock_flash(stlink_t *sl) { static void set_flash_cr_pg(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_CR_PG); @@ -221,7 +221,7 @@ static void set_flash_cr_pg(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) stlink_write_debug32(sl, FLASH_F4_CR, n); else @@ -239,7 +239,7 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { } static void set_flash_cr_mer(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); @@ -249,7 +249,7 @@ static void set_flash_cr_mer(stlink_t *sl) { } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); @@ -259,7 +259,7 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { } static void set_flash_cr_strt(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_F4_CR_STRT); @@ -276,7 +276,7 @@ static inline uint32_t read_flash_acr(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) res = stlink_read_debug32(sl, FLASH_F4_SR); else @@ -286,7 +286,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { } static inline unsigned int is_flash_busy(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); else @@ -931,7 +931,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) size_t off; int num_empty = 0; unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; + || sl->chip_id == STM32_CHIPID_L1_HIGH) ? 0:0xff; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -1013,7 +1013,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector<4) sl->flash_pgsz=0x4000; @@ -1031,7 +1031,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1059,7 +1059,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { + || sl->chip_id == STM32_CHIPID_L1_HIGH) { uint32_t val; @@ -1169,7 +1169,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) int stlink_erase_flash_mass(stlink_t *sl) { if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { + || sl->chip_id == STM32_CHIPID_L1_HIGH) { /* erase each page */ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1340,13 +1340,13 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { size_t loader_size; if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { /* stm32l */ + || sl->chip_id == STM32_CHIPID_L1_HIGH ) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); - } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || + } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD){ loader_code = loader_code_stm32f4; loader_size = sizeof(loader_code_stm32f4); @@ -1515,7 +1515,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t ILOG("Finished erasing %d pages of %d (%#x) bytes\n", page_count, sl->flash_pgsz, sl->flash_pgsz); - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { /* todo: check write operation */ @@ -1583,7 +1583,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } //STM32F4END else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { + || sl->chip_id == STM32_CHIPID_L1_HIGH ) { /* use fast word write. todo: half page. */ uint32_t val; @@ -1740,7 +1740,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { int err; unsigned int num_empty = 0, index; unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE )?0:0xff; + || sl->chip_id == STM32_CHIPID_L1_HIGH )?0:0xff; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { ELOG("map_file() == -1\n"); @@ -1781,7 +1781,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { + || sl->chip_id == STM32_CHIPID_L1_HIGH ) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1804,7 +1804,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || + } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD) { size_t count = size / sizeof(uint32_t); @@ -1839,7 +1839,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons /* check written byte count */ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { + || sl->chip_id == STM32_CHIPID_L1_HIGH ) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1858,7 +1858,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || + } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD) { stlink_read_reg(sl, 2, &rr); From 5e9b096c9c6755449d729e5b7c3d95b4ae5eb27d Mon Sep 17 00:00:00 2001 From: texane Date: Sun, 16 Mar 2014 14:36:52 -0500 Subject: [PATCH 0262/1435] [ fix ] fix STM32L152RE broken by previous commit --- src/stlink-common.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 0d11a63eb..545434b4e 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -931,7 +931,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) size_t off; int num_empty = 0; unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH) ? 0:0xff; + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -1059,7 +1059,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { uint32_t val; @@ -1169,7 +1169,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) int stlink_erase_flash_mass(stlink_t *sl) { if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { /* erase each page */ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1340,7 +1340,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { size_t loader_size; if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH ) { /* stm32l */ + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { @@ -1583,7 +1583,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } //STM32F4END else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH ) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { /* use fast word write. todo: half page. */ uint32_t val; @@ -1740,7 +1740,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { int err; unsigned int num_empty = 0, index; unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH )?0:0xff; + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE )?0:0xff; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { ELOG("map_file() == -1\n"); @@ -1781,7 +1781,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH ) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1839,7 +1839,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons /* check written byte count */ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH ) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; From 75be8af5477810871bdc2d03dff1f00d33309b11 Mon Sep 17 00:00:00 2001 From: "Theodore A. Roth" Date: Tue, 15 Apr 2014 09:46:26 -0600 Subject: [PATCH 0263/1435] Quell compiler warning. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Building on a 32-bit linux system was generating the following: src/st-info.c: In function ‘print_data’: src/st-info.c:25:3: warning: format ‘%lx’ expects argument of type \ ‘long unsigned int’, but argument 2 has type ‘size_t’ [-Wformat] src/st-info.c:27:3: warning: format ‘%lx’ expects argument of type \ ‘long unsigned int’, but argument 2 has type ‘size_t’ [-Wformat] src/st-info.c:29:3: warning: format ‘%lx’ expects argument of type \ ‘long unsigned int’, but argument 2 has type ‘size_t’ [-Wformat] Using '%zx' eliminates the warning in a platform agnostic way. --- src/st-info.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/st-info.c b/src/st-info.c index e28a4f12c..28f3fb823 100644 --- a/src/st-info.c +++ b/src/st-info.c @@ -22,11 +22,11 @@ static int print_data(stlink_t* sl, char** av) { int ret = 0; if (strcmp(av[1], "--flash") == 0) - printf("0x%lx\n", sl->flash_size); + printf("0x%zx\n", sl->flash_size); else if (strcmp(av[1], "--sram") == 0) - printf("0x%lx\n", sl->sram_size); + printf("0x%zx\n", sl->sram_size); else if (strcmp(av[1], "--pagesize") == 0) - printf("0x%lx\n", sl->flash_pgsz); + printf("0x%zx\n", sl->flash_pgsz); else if (strcmp(av[1], "--chipid") == 0) printf("0x%.4x\n", sl->chip_id); else if (strcmp(av[1], "--descr")==0) { From 8f96d26a522d870a50f7cb58a7e4a709dcb0dac6 Mon Sep 17 00:00:00 2001 From: fhars Date: Wed, 16 Apr 2014 10:41:33 +0200 Subject: [PATCH 0264/1435] Update README This board uses a ST-Link/V2-1 interface. I don't know what differences there are between v2 and v2-1, but they seem to be small enough that first tests worked as expected. --- README | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/README b/README index 853c51826..3d25ae34c 100644 --- a/README +++ b/README @@ -180,5 +180,8 @@ Known Working Targets: * STM32L151CB (custom board) * STM32L152RB (STM32L-Discovery board, custom board) -Please report any and all known working combinations so I can update this! +STLink v2-1 (as found on the Nucleo boards) +Known Working Targets: +* STM32F401xx (STM32 Nucleo-F401RE board) +Please report any and all known working combinations so I can update this! From 788d2df7723e9da3a0369365f56830ab9541e9c7 Mon Sep 17 00:00:00 2001 From: Olivier Croquette Date: Mon, 19 May 2014 10:35:24 +0200 Subject: [PATCH 0265/1435] Include signal.h to define SIGINT Fix build error with MinGW --- gdbserver/gdb-server.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 459d1012b..a3ed335ad 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #ifdef __MINGW32__ From bf3d7a0dddb6db7e12f711c7ad8c0ebcf30d64fe Mon Sep 17 00:00:00 2001 From: orangeudav Date: Mon, 26 May 2014 01:36:59 +0400 Subject: [PATCH 0266/1435] Fix OS X's version detecting --- stlinkv1_macosx_driver/README | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/stlinkv1_macosx_driver/README b/stlinkv1_macosx_driver/README index adf3cca87..7b47f410f 100644 --- a/stlinkv1_macosx_driver/README +++ b/stlinkv1_macosx_driver/README @@ -22,4 +22,11 @@ tar xzvf osx.tar.gz Then, install the driver using: sudo make osx_stlink_shield -no reboot required. \ No newline at end of file +no reboot required. + +P.S. If error `OS X version not supported` occurs. For the latest versions of Mac OS X you may need to change the `osx/install.sh` as follows: +``` +< ISOSXLION=$(sw_vers -productVersion) +--- +> ISOSXLION=$(sw_vers -productVersion | sed -e 's:.[[:digit:]]*$::') +``` From 2dbf4970f021f2e36163c630e74ce56ffd24f7c0 Mon Sep 17 00:00:00 2001 From: Stany MARCEL Date: Wed, 4 Jun 2014 00:13:46 +0200 Subject: [PATCH 0267/1435] Correct gui build when builddir is not srcdir --- gui/Makefile.am | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gui/Makefile.am b/gui/Makefile.am index 19c067278..97b780e43 100644 --- a/gui/Makefile.am +++ b/gui/Makefile.am @@ -7,7 +7,7 @@ stlink_gui_SOURCES = \ stlink_gui_CPPFLAGS = \ -I$(top_srcdir) \ $(AM_CPPFLAGS) \ - -I$(top_builddir)/src \ + -I$(top_srcdir)/src \ @GTK_CFLAGS@ stlink_gui_CFLAGS = \ From 0d1521c4abfafeba4daab5adf92d9081f70c75db Mon Sep 17 00:00:00 2001 From: Viacheslav Dobromyslov Date: Fri, 20 Jun 2014 21:11:09 +1100 Subject: [PATCH 0268/1435] udev rules initialization and STM32F0Discovery Added udev rules initialization. Added STM32F0Discovery board to the supported boards list. --- README | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README b/README index 3d25ae34c..c0ccc7b73 100644 --- a/README +++ b/README @@ -113,6 +113,7 @@ For convenience, you may install udev rules file, 49-stlinkv*.rules, located in the root of repository. You will need to copy it to /etc/udev/rules.d, and then either reboot or execute $ udevadm control --reload-rules +$ udevadm trigger Udev will now create a /dev/stlinkv2_XX or /dev/stlinkv1_XX file, with the appropriate permissions. This is currently all the device is for, (only one stlink of each version is supported at @@ -169,6 +170,7 @@ No information: STLink v2 (as found on the 32L and F4 Discovery boards) Known Working Targets: +* STM32F0Discovery (STM32F0 Discovery board) * STM32F100xx (Medium Density VL, as on the 32VL Discovery board) * STM32L1xx (STM32L Discovery board) * STM32F103VC, STM32F107RC, STM32L151RB, STM32F205RE and STM32F405RE on custom boards From 95834ef5ed5e2ada7d420404f1ff98cb6bcc543c Mon Sep 17 00:00:00 2001 From: sneuf Date: Tue, 1 Jul 2014 16:42:27 +0200 Subject: [PATCH 0269/1435] Add F3 small devices (F301, F302) with ID 0x439 - Add F3 small devices (F301, F302) with MCU device ID code 0x439 - Sort supported devices by MCU device ID code --- src/stlink-common.h | 63 +++++++++++++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 20 deletions(-) diff --git a/src/stlink-common.h b/src/stlink-common.h index cce4d9f3e..1bedbf497 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -98,33 +98,46 @@ extern "C" { * DBGMCU_IDCODE register (0xE0042000) */ // stm32 chipids, only lower 12 bits.. -#define STM32_CHIPID_F1_MEDIUM 0x410 -#define STM32_CHIPID_F2 0x411 -#define STM32_CHIPID_F1_LOW 0x412 -#define STM32_CHIPID_F3 0x422 -#define STM32_CHIPID_F37x 0x432 -#define STM32_CHIPID_F4 0x413 -#define STM32_CHIPID_F4_HD 0x419 -#define STM32_CHIPID_F4_LP 0x423 -#define STM32_CHIPID_F4_DE 0x433 -#define STM32_CHIPID_F1_HIGH 0x414 -#define STM32_CHIPID_L1_MEDIUM 0x416 +#define STM32_CHIPID_F1_MEDIUM 0x410 +#define STM32_CHIPID_F2 0x411 +#define STM32_CHIPID_F1_LOW 0x412 +#define STM32_CHIPID_F4 0x413 +#define STM32_CHIPID_F1_HIGH 0x414 + +#define STM32_CHIPID_L1_MEDIUM 0x416 + +#define STM32_CHIPID_F1_CONN 0x418 +#define STM32_CHIPID_F4_HD 0x419 +#define STM32_CHIPID_F1_VL_MEDIUM 0x420 + +#define STM32_CHIPID_F3 0x422 +#define STM32_CHIPID_F4_LP 0x423 + #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427 +#define STM32_CHIPID_F1_VL_HIGH 0x428 + +#define STM32_CHIPID_F1_XL 0x430 + +#define STM32_CHIPID_F37x 0x432 +#define STM32_CHIPID_F4_DE 0x433 + +#define STM32_CHIPID_L1_HIGH 0x436 +#define STM32_CHIPID_L152_RE 0x437 + + +#define STM32_CHIPID_F3_SMALL 0x439 +#define STM32_CHIPID_F0 0x440 + +#define STM32_CHIPID_F0_SMALL 0x444 + +#define STM32_CHIPID_F0_CAN 0x448 + /* * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus" * and some that are called "High". 0x427 is assigned to the other "Medium- * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and * 0x436 HIGH. */ -#define STM32_CHIPID_L1_HIGH 0x436 -#define STM32_CHIPID_L152_RE 0x437 -#define STM32_CHIPID_F1_CONN 0x418 -#define STM32_CHIPID_F1_VL_MEDIUM 0x420 -#define STM32_CHIPID_F1_VL_HIGH 0x428 -#define STM32_CHIPID_F1_XL 0x430 -#define STM32_CHIPID_F0 0x440 -#define STM32_CHIPID_F0_SMALL 0x444 -#define STM32_CHIPID_F0_CAN 0x448 // Constant STM32 memory map figures #define STM32_FLASH_BASE 0x08000000 @@ -354,6 +367,16 @@ static const chip_params_t devices[] = { .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 }, + { + // STM32F30x + .chip_id = STM32_CHIPID_F3_SMALL, + .description = "F3 small device", + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1fffd800, + .bootrom_size = 0x2000 + }, }; From 3b443dc1c8690ee4b45f477cd83165dca700e60a Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Wed, 9 Jul 2014 22:31:11 -0700 Subject: [PATCH 0270/1435] Reindent all source files The indentation of various st-link source files is highly inconsistent. Reindent all source files to 4 space indentions for consistency. I went with 4 space indentations, as it was the most common style. --- flash/main.c | 340 +++---- flashloaders/stm32f0.s | 46 +- flashloaders/stm32f4.s | 26 +- flashloaders/stm32lx.s | 51 +- gdbserver/gdb-remote.c | 248 +++-- gdbserver/gdb-server.c | 1944 ++++++++++++++++++++-------------------- gui/stlink-gui.c | 1332 +++++++++++++-------------- gui/stlink-gui.h | 102 +-- mingw/mingw.c | 198 ++-- src/mmap.c | 28 +- src/mmap.h | 4 +- src/st-info.c | 118 +-- src/st-term.c | 352 ++++---- src/stlink-common.c | 538 +++++------ src/stlink-common.h | 335 ++++--- src/stlink-sg.c | 363 ++++---- src/stlink-sg.h | 10 +- src/stlink-usb.c | 104 +-- src/stlink-usb.h | 6 +- src/test_sg.c | 288 +++--- src/test_usb.c | 10 +- src/uglylogging.c | 52 +- src/uglylogging.h | 4 +- 23 files changed, 3247 insertions(+), 3252 deletions(-) diff --git a/flash/main.c b/flash/main.c index d550eeeed..8f5b351de 100644 --- a/flash/main.c +++ b/flash/main.c @@ -12,12 +12,12 @@ enum st_cmds {DO_WRITE = 0, DO_READ = 1, DO_ERASE = 2}; struct opts { - enum st_cmds cmd; - const char* devname; - const char* filename; - stm32_addr_t addr; - size_t size; - int reset; + enum st_cmds cmd; + const char* devname; + const char* filename; + stm32_addr_t addr; + size_t size; + int reset; }; static void usage(void) @@ -31,183 +31,183 @@ static void usage(void) static int get_opts(struct opts* o, int ac, char** av) { - /* stlinkv1 command line: ./flash {read|write} /dev/sgX path addr */ - /* stlinkv2 command line: ./flash {read|write} path addr */ - - unsigned int i = 0; - - if (ac < 1) return -1; - - if (strcmp(av[0], "--reset") == 0) - { - o->reset = 1; - ac--; - av++; - } - else - { - o->reset = 0; - } - - if (ac < 1) return -1; - - /* stlinkv2 */ - o->devname = NULL; - - if (strcmp(av[0], "erase") == 0) - { - o->cmd = DO_ERASE; - - /* stlinkv1 mode */ - if (ac == 2) + /* stlinkv1 command line: ./flash {read|write} /dev/sgX path addr */ + /* stlinkv2 command line: ./flash {read|write} path addr */ + + unsigned int i = 0; + + if (ac < 1) return -1; + + if (strcmp(av[0], "--reset") == 0) + { + o->reset = 1; + ac--; + av++; + } + else { - o->devname = av[1]; - i = 1; + o->reset = 0; } - } - else { - if (ac < 3) return -1; - if (strcmp(av[0], "read") == 0) - { - o->cmd = DO_READ; - - /* stlinkv1 mode */ - if (ac == 5) - { - o->devname = av[1]; - i = 1; - } - if (ac > 3) - o->size = strtoul(av[i + 3], NULL, 16); - } - else if (strcmp(av[0], "write") == 0) - { - o->cmd = DO_WRITE; - - /* stlinkv1 mode */ - if (ac == 4) - { - o->devname = av[1]; - i = 1; - } - } - else - { - return -1; - } - } - - o->filename = av[i + 1]; - o->addr = strtoul(av[i + 2], NULL, 16); - - return 0; -} + + if (ac < 1) return -1; + + /* stlinkv2 */ + o->devname = NULL; + + if (strcmp(av[0], "erase") == 0) + { + o->cmd = DO_ERASE; + + /* stlinkv1 mode */ + if (ac == 2) + { + o->devname = av[1]; + i = 1; + } + } + else { + if (ac < 3) return -1; + if (strcmp(av[0], "read") == 0) + { + o->cmd = DO_READ; + + /* stlinkv1 mode */ + if (ac == 5) + { + o->devname = av[1]; + i = 1; + } + if (ac > 3) + o->size = strtoul(av[i + 3], NULL, 16); + } + else if (strcmp(av[0], "write") == 0) + { + o->cmd = DO_WRITE; + + /* stlinkv1 mode */ + if (ac == 4) + { + o->devname = av[1]; + i = 1; + } + } + else + { + return -1; + } + } + + o->filename = av[i + 1]; + o->addr = strtoul(av[i + 2], NULL, 16); + + return 0; +} int main(int ac, char** av) { - stlink_t* sl = NULL; - struct opts o; - int err = -1; - - o.size = 0; - if (get_opts(&o, ac - 1, av + 1) == -1) - { - printf("invalid command line\n"); - usage(); - goto on_error; - } - - if (o.devname != NULL) /* stlinkv1 */ - { - sl = stlink_v1_open(50, 1); - if (sl == NULL) goto on_error; - sl->verbose = 50; - } - else /* stlinkv2 */ - { - sl = stlink_open_usb(50, 1); - if (sl == NULL) goto on_error; - sl->verbose = 50; - } - - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) - stlink_exit_dfu_mode(sl); - - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) - stlink_enter_swd_mode(sl); - - if (o.reset) - stlink_reset(sl); - -// Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 - if (sl->chip_id == STM32_CHIPID_F4) - { - memset(sl->q_buf,0,4); - for (int i=0;i<8;i++) { - stlink_write_mem32(sl,0x40026000+0x10+0x18*i,4); - stlink_write_mem32(sl,0x40026400+0x10+0x18*i,4); - stlink_write_mem32(sl,0x40026000+0x24+0x18*i,4); - stlink_write_mem32(sl,0x40026400+0x24+0x18*i,4); - } - } - if (o.cmd == DO_WRITE) /* write */ - { - if ((o.addr >= sl->flash_base) && - (o.addr < sl->flash_base + sl->flash_size)) { - err = stlink_fwrite_flash(sl, o.filename, o.addr); - if (err == -1) - { - printf("stlink_fwrite_flash() == -1\n"); - goto on_error; - } + stlink_t* sl = NULL; + struct opts o; + int err = -1; + + o.size = 0; + if (get_opts(&o, ac - 1, av + 1) == -1) + { + printf("invalid command line\n"); + usage(); + goto on_error; } - else if ((o.addr >= sl->sram_base) && - (o.addr < sl->sram_base + sl->sram_size)) { - err = stlink_fwrite_sram(sl, o.filename, o.addr); - if (err == -1) - { - printf("stlink_sram_flash() == -1\n"); - goto on_error; - } - } - } else if (o.cmd == DO_ERASE) - { - err = stlink_erase_flash_mass(sl); - if (err == -1) + + if (o.devname != NULL) /* stlinkv1 */ { - printf("stlink_fwrite_flash() == -1\n"); - goto on_error; + sl = stlink_v1_open(50, 1); + if (sl == NULL) goto on_error; + sl->verbose = 50; } - } - else /* read */ - { - if ((o.addr >= sl->flash_base) && (o.size == 0) && - (o.addr < sl->flash_base + sl->flash_size)) - o.size = sl->flash_size; - else if ((o.addr >= sl->sram_base) && (o.size == 0) && - (o.addr < sl->sram_base + sl->sram_size)) - o.size = sl->sram_size; - err = stlink_fread(sl, o.filename, o.addr, o.size); - if (err == -1) + else /* stlinkv2 */ { - printf("stlink_fread() == -1\n"); - goto on_error; + sl = stlink_open_usb(50, 1); + if (sl == NULL) goto on_error; + sl->verbose = 50; } - } - if (o.reset) - stlink_reset(sl); + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) + stlink_exit_dfu_mode(sl); - /* success */ - err = 0; + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) + stlink_enter_swd_mode(sl); - on_error: - if (sl != NULL) - { - stlink_exit_debug_mode(sl); - stlink_close(sl); - } + if (o.reset) + stlink_reset(sl); + + // Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 + if (sl->chip_id == STM32_CHIPID_F4) + { + memset(sl->q_buf,0,4); + for (int i=0;i<8;i++) { + stlink_write_mem32(sl,0x40026000+0x10+0x18*i,4); + stlink_write_mem32(sl,0x40026400+0x10+0x18*i,4); + stlink_write_mem32(sl,0x40026000+0x24+0x18*i,4); + stlink_write_mem32(sl,0x40026400+0x24+0x18*i,4); + } + } + if (o.cmd == DO_WRITE) /* write */ + { + if ((o.addr >= sl->flash_base) && + (o.addr < sl->flash_base + sl->flash_size)) { + err = stlink_fwrite_flash(sl, o.filename, o.addr); + if (err == -1) + { + printf("stlink_fwrite_flash() == -1\n"); + goto on_error; + } + } + else if ((o.addr >= sl->sram_base) && + (o.addr < sl->sram_base + sl->sram_size)) { + err = stlink_fwrite_sram(sl, o.filename, o.addr); + if (err == -1) + { + printf("stlink_sram_flash() == -1\n"); + goto on_error; + } + } + } else if (o.cmd == DO_ERASE) + { + err = stlink_erase_flash_mass(sl); + if (err == -1) + { + printf("stlink_fwrite_flash() == -1\n"); + goto on_error; + } + } + else /* read */ + { + if ((o.addr >= sl->flash_base) && (o.size == 0) && + (o.addr < sl->flash_base + sl->flash_size)) + o.size = sl->flash_size; + else if ((o.addr >= sl->sram_base) && (o.size == 0) && + (o.addr < sl->sram_base + sl->sram_size)) + o.size = sl->sram_size; + err = stlink_fread(sl, o.filename, o.addr, o.size); + if (err == -1) + { + printf("stlink_fread() == -1\n"); + goto on_error; + } + } + + if (o.reset) + stlink_reset(sl); + + /* success */ + err = 0; + +on_error: + if (sl != NULL) + { + stlink_exit_debug_mode(sl); + stlink_close(sl); + } - return err; + return err; } diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s index f35fe406e..fe12f90f3 100644 --- a/flashloaders/stm32f0.s +++ b/flashloaders/stm32f0.s @@ -1,32 +1,32 @@ /* Adopted from STM AN4065 stm32f0xx_flash.c:FLASH_ProgramWord */ -write: - ldr r4, STM32_FLASH_BASE - mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */ - mov r6, #4 /* PGERR */ +write: + ldr r4, STM32_FLASH_BASE + mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */ + mov r6, #4 /* PGERR */ write_half_word: - ldr r3, [r4, #16] /* FLASH->CR */ - orr r3, r5 - str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */ - ldrh r3, [r0] /* r3 = *sram */ - strh r3, [r1] /* *flash = r3 */ + ldr r3, [r4, #16] /* FLASH->CR */ + orr r3, r5 + str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */ + ldrh r3, [r0] /* r3 = *sram */ + strh r3, [r1] /* *flash = r3 */ busy: - ldr r3, [r4, #12] /* FLASH->SR */ - tst r3, r5 /* FLASH_SR_BUSY */ - beq busy + ldr r3, [r4, #12] /* FLASH->SR */ + tst r3, r5 /* FLASH_SR_BUSY */ + beq busy - tst r3, r6 /* PGERR */ - bne exit + tst r3, r6 /* PGERR */ + bne exit - add r0, r0, #2 /* sram += 2 */ - add r1, r1, #2 /* flash += 2 */ - sub r2, r2, #0x01 /* count-- */ - cmp r2, #0 - bne write_half_word + add r0, r0, #2 /* sram += 2 */ + add r1, r1, #2 /* flash += 2 */ + sub r2, r2, #0x01 /* count-- */ + cmp r2, #0 + bne write_half_word exit: - ldr r3, [r4, #16] /* FLASH->CR */ - bic r3, r5 - str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */ - bkpt #0x00 + ldr r3, [r4, #16] /* FLASH->CR */ + bic r3, r5 + str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */ + bkpt #0x00 STM32_FLASH_BASE: .word 0x40022000 diff --git a/flashloaders/stm32f4.s b/flashloaders/stm32f4.s index 6cad73042..21f5a8f7f 100644 --- a/flashloaders/stm32f4.s +++ b/flashloaders/stm32f4.s @@ -8,23 +8,23 @@ @ r4 = temp start: - ldr r3, flash_base + ldr r3, flash_base next: - cbz r2, done - ldr r4, [r0] - str r4, [r1] + cbz r2, done + ldr r4, [r0] + str r4, [r1] wait: - ldrh r4, [r3, #0x0e] - tst.w r4, #1 - bne wait - - add r0, #4 - add r1, #4 - sub r2, #1 - b next + ldrh r4, [r3, #0x0e] + tst.w r4, #1 + bne wait + + add r0, #4 + add r1, #4 + sub r2, #1 + b next done: - bkpt + bkpt .align 2 diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s index 6e8ccb089..799d1345c 100644 --- a/flashloaders/stm32lx.s +++ b/flashloaders/stm32lx.s @@ -26,38 +26,37 @@ // Build : arm-eabi-gcc -c stm32lx.S - .text - .syntax unified - .cpu cortex-m3 - .thumb - .thumb_func - .global write + .text + .syntax unified + .cpu cortex-m3 + .thumb + .thumb_func + .global write /* - r0 - destination address - r1 - source address - r2 - count + r0 - destination address + r1 - source address + r2 - count */ - // Set 0 to r3 - movs r3, #0 - // Go to compare - b.n test_done + // Set 0 to r3 + movs r3, #0 + // Go to compare + b.n test_done write_word: - // Load one word from address in r0, increment by 4 - ldr.w ip, [r1], #4 - // Store the word to address in r1, increment by 4 - str.w ip, [r0], #4 - // Increment r3 - adds r3, #1 + // Load one word from address in r0, increment by 4 + ldr.w ip, [r1], #4 + // Store the word to address in r1, increment by 4 + str.w ip, [r0], #4 + // Increment r3 + adds r3, #1 test_done: - // Compare r3 and r2 - cmp r3, r2 - // Loop if not zero - bcc.n write_word - - // Set breakpoint to exit - bkpt #0x00 + // Compare r3 and r2 + cmp r3, r2 + // Loop if not zero + bcc.n write_word + // Set breakpoint to exit + bkpt #0x00 diff --git a/gdbserver/gdb-remote.c b/gdbserver/gdb-remote.c index edf53389b..a9eef3333 100644 --- a/gdbserver/gdb-remote.c +++ b/gdbserver/gdb-remote.c @@ -1,10 +1,8 @@ -/* -*- tab-width:8 -*- */ - /* - Copyright (C) 2011 Peter Zotov - Use of this source code is governed by a BSD-style - license that can be found in the LICENSE file. -*/ + * Copyright (C) 2011 Peter Zotov + * Use of this source code is governed by a BSD-style + * license that can be found in the LICENSE file. + */ #include #include @@ -20,141 +18,141 @@ static const char hex[] = "0123456789abcdef"; int gdb_send_packet(int fd, char* data) { - int length = strlen(data) + 5; - char* packet = malloc(length); /* '$' data (hex) '#' cksum (hex) */ - - memset(packet, 0, length); - - packet[0] = '$'; - - uint8_t cksum = 0; - for(unsigned int i = 0; i < strlen(data); i++) { - packet[i + 1] = data[i]; - cksum += data[i]; - } - - packet[length - 4] = '#'; - packet[length - 3] = hex[cksum >> 4]; - packet[length - 2] = hex[cksum & 0xf]; - - while(1) { - if(write(fd, packet, length) != length) { - free(packet); - return -2; - } - - char ack; - if(read(fd, &ack, 1) != 1) { - free(packet); - return -2; - } - - if(ack == '+') { - free(packet); - return 0; - } - } + int length = strlen(data) + 5; + char* packet = malloc(length); /* '$' data (hex) '#' cksum (hex) */ + + memset(packet, 0, length); + + packet[0] = '$'; + + uint8_t cksum = 0; + for(unsigned int i = 0; i < strlen(data); i++) { + packet[i + 1] = data[i]; + cksum += data[i]; + } + + packet[length - 4] = '#'; + packet[length - 3] = hex[cksum >> 4]; + packet[length - 2] = hex[cksum & 0xf]; + + while(1) { + if(write(fd, packet, length) != length) { + free(packet); + return -2; + } + + char ack; + if(read(fd, &ack, 1) != 1) { + free(packet); + return -2; + } + + if(ack == '+') { + free(packet); + return 0; + } + } } #define ALLOC_STEP 1024 int gdb_recv_packet(int fd, char** buffer) { - unsigned packet_size = ALLOC_STEP + 1, packet_idx = 0; - uint8_t cksum = 0; - char recv_cksum[3] = {0}; - char* packet_buffer = malloc(packet_size); - unsigned state; + unsigned packet_size = ALLOC_STEP + 1, packet_idx = 0; + uint8_t cksum = 0; + char recv_cksum[3] = {0}; + char* packet_buffer = malloc(packet_size); + unsigned state; start: - state = 0; - /* - * 0: waiting $ - * 1: data, waiting # - * 2: cksum 1 - * 3: cksum 2 - * 4: fin - */ - - char c; - while(state != 4) { - if(read(fd, &c, 1) != 1) { - return -2; - } - - switch(state) { - case 0: - if(c != '$') { - // ignore - } else { - state = 1; - } - break; - - case 1: - if(c == '#') { - state = 2; - } else { - packet_buffer[packet_idx++] = c; - cksum += c; - - if(packet_idx == packet_size) { - packet_size += ALLOC_STEP; - packet_buffer = realloc(packet_buffer, packet_size); - } - } - break; - - case 2: - recv_cksum[0] = c; - state = 3; - break; - - case 3: - recv_cksum[1] = c; - state = 4; - break; - } - } - - uint8_t recv_cksum_int = strtoul(recv_cksum, NULL, 16); - if(recv_cksum_int != cksum) { - char nack = '-'; - if(write(fd, &nack, 1) != 1) { - return -2; - } - - goto start; - } else { - char ack = '+'; - if(write(fd, &ack, 1) != 1) { - return -2; - } - } - - packet_buffer[packet_idx] = 0; - *buffer = packet_buffer; - - return packet_idx; + state = 0; + /* + * 0: waiting $ + * 1: data, waiting # + * 2: cksum 1 + * 3: cksum 2 + * 4: fin + */ + + char c; + while(state != 4) { + if(read(fd, &c, 1) != 1) { + return -2; + } + + switch(state) { + case 0: + if(c != '$') { + // ignore + } else { + state = 1; + } + break; + + case 1: + if(c == '#') { + state = 2; + } else { + packet_buffer[packet_idx++] = c; + cksum += c; + + if(packet_idx == packet_size) { + packet_size += ALLOC_STEP; + packet_buffer = realloc(packet_buffer, packet_size); + } + } + break; + + case 2: + recv_cksum[0] = c; + state = 3; + break; + + case 3: + recv_cksum[1] = c; + state = 4; + break; + } + } + + uint8_t recv_cksum_int = strtoul(recv_cksum, NULL, 16); + if(recv_cksum_int != cksum) { + char nack = '-'; + if(write(fd, &nack, 1) != 1) { + return -2; + } + + goto start; + } else { + char ack = '+'; + if(write(fd, &ack, 1) != 1) { + return -2; + } + } + + packet_buffer[packet_idx] = 0; + *buffer = packet_buffer; + + return packet_idx; } // Here we skip any characters which are not \x03, GDB interrupt. // As we use the mode with ACK, in a (very unlikely) situation of a packet // lost because of this skipping, it will be resent anyway. int gdb_check_for_interrupt(int fd) { - struct pollfd pfd; - pfd.fd = fd; - pfd.events = POLLIN; + struct pollfd pfd; + pfd.fd = fd; + pfd.events = POLLIN; - if(poll(&pfd, 1, 0) != 0) { - char c; + if(poll(&pfd, 1, 0) != 0) { + char c; - if(read(fd, &c, 1) != 1) - return -2; + if(read(fd, &c, 1) != 1) + return -2; - if(c == '\x03') // ^C - return 1; - } + if(c == '\x03') // ^C + return 1; + } - return 0; + return 0; } diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index a3ed335ad..71ab44016 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -1,10 +1,9 @@ -/* -*- tab-width:8 -*- */ #define DEBUG 0 /* - Copyright (C) 2011 Peter Zotov - Use of this source code is governed by a BSD-style - license that can be found in the LICENSE file. -*/ + * Copyright (C) 2011 Peter Zotov + * Use of this source code is governed by a BSD-style + * license that can be found in the LICENSE file. + */ #include #include @@ -75,31 +74,31 @@ int parse_options(int argc, char** argv, st_state_t *st) { {"verbose", optional_argument, NULL, 'v'}, {"stlink_version", required_argument, NULL, 's'}, {"stlinkv1", no_argument, NULL, '1'}, - {"listen_port", required_argument, NULL, 'p'}, - {"multi", optional_argument, NULL, 'm'}, - {"no-reset", optional_argument, NULL, 'n'}, + {"listen_port", required_argument, NULL, 'p'}, + {"multi", optional_argument, NULL, 'm'}, + {"no-reset", optional_argument, NULL, 'n'}, {0, 0, 0, 0}, }; - const char * help_str = "%s - usage:\n\n" - " -h, --help\t\tPrint this help\n" - " -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n" - " -v, --verbose\t\tSpecify generally verbose logging\n" - " -s X, --stlink_version=X\n" - "\t\t\tChoose what version of stlink to use, (defaults to 2)\n" - " -1, --stlinkv1\tForce stlink version 1\n" - " -p 4242, --listen_port=1234\n" - "\t\t\tSet the gdb server listen port. " - "(default port: " STRINGIFY(DEFAULT_GDB_LISTEN_PORT) ")\n" - " -m, --multi\n" - "\t\t\tSet gdb server to extended mode.\n" - "\t\t\tst-util will continue listening for connections after disconnect.\n" - " -n, --no-reset\n" - "\t\t\tDo not reset board on connection.\n" - "\n" - "The STLINKv2 device to use can be specified in the environment\n" - "variable STLINK_DEVICE on the format :.\n" - "\n" - ; + const char * help_str = "%s - usage:\n\n" + " -h, --help\t\tPrint this help\n" + " -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n" + " -v, --verbose\t\tSpecify generally verbose logging\n" + " -s X, --stlink_version=X\n" + "\t\t\tChoose what version of stlink to use, (defaults to 2)\n" + " -1, --stlinkv1\tForce stlink version 1\n" + " -p 4242, --listen_port=1234\n" + "\t\t\tSet the gdb server listen port. " + "(default port: " STRINGIFY(DEFAULT_GDB_LISTEN_PORT) ")\n" + " -m, --multi\n" + "\t\t\tSet gdb server to extended mode.\n" + "\t\t\tst-util will continue listening for connections after disconnect.\n" + " -n, --no-reset\n" + "\t\t\tDo not reset board on connection.\n" + "\n" + "The STLINKv2 device to use can be specified in the environment\n" + "variable STLINK_DEVICE on the format :.\n" + "\n" + ; int option_index = 0; @@ -107,50 +106,50 @@ int parse_options(int argc, char** argv, st_state_t *st) { int q; while ((c = getopt_long(argc, argv, "hv::s:1p:mn", long_options, &option_index)) != -1) { switch (c) { - case 0: - printf("XXXXX Shouldn't really normally come here, only if there's no corresponding option\n"); - printf("option %s", long_options[option_index].name); - if (optarg) { - printf(" with arg %s", optarg); - } - printf("\n"); - break; - case 'h': - printf(help_str, argv[0]); - exit(EXIT_SUCCESS); - break; - case 'v': - if (optarg) { - st->logging_level = atoi(optarg); - } else { - st->logging_level = DEFAULT_LOGGING_LEVEL; - } - break; - case '1': - st->stlink_version = 1; - break; - case 's': - sscanf(optarg, "%i", &q); - if (q < 0 || q > 2) { - fprintf(stderr, "stlink version %d unknown!\n", q); - exit(EXIT_FAILURE); - } - st->stlink_version = q; - break; - case 'p': - sscanf(optarg, "%i", &q); - if (q < 0) { - fprintf(stderr, "Can't use a negative port to listen on: %d\n", q); - exit(EXIT_FAILURE); - } - st->listen_port = q; - break; - case 'm': - st->persistent = 1; - break; - case 'n': - st->reset = 0; - break; + case 0: + printf("XXXXX Shouldn't really normally come here, only if there's no corresponding option\n"); + printf("option %s", long_options[option_index].name); + if (optarg) { + printf(" with arg %s", optarg); + } + printf("\n"); + break; + case 'h': + printf(help_str, argv[0]); + exit(EXIT_SUCCESS); + break; + case 'v': + if (optarg) { + st->logging_level = atoi(optarg); + } else { + st->logging_level = DEFAULT_LOGGING_LEVEL; + } + break; + case '1': + st->stlink_version = 1; + break; + case 's': + sscanf(optarg, "%i", &q); + if (q < 0 || q > 2) { + fprintf(stderr, "stlink version %d unknown!\n", q); + exit(EXIT_FAILURE); + } + st->stlink_version = q; + break; + case 'p': + sscanf(optarg, "%i", &q); + if (q < 0) { + fprintf(stderr, "Can't use a negative port to listen on: %d\n", q); + exit(EXIT_FAILURE); + } + st->listen_port = q; + break; + case 'm': + st->persistent = 1; + break; + case 'n': + st->reset = 0; + break; } } @@ -165,27 +164,27 @@ int parse_options(int argc, char** argv, st_state_t *st) { int main(int argc, char** argv) { - int32_t voltage; - - stlink_t *sl = NULL; - - st_state_t state; - memset(&state, 0, sizeof(state)); - // set defaults... - state.stlink_version = 2; - state.logging_level = DEFAULT_LOGGING_LEVEL; - state.listen_port = DEFAULT_GDB_LISTEN_PORT; - state.reset = 1; /* By default, reset board */ - parse_options(argc, argv, &state); - switch (state.stlink_version) { - case 2: - sl = stlink_open_usb(state.logging_level, 0); - if(sl == NULL) return 1; - break; - case 1: - sl = stlink_v1_open(state.logging_level, 0); - if(sl == NULL) return 1; - break; + int32_t voltage; + + stlink_t *sl = NULL; + + st_state_t state; + memset(&state, 0, sizeof(state)); + // set defaults... + state.stlink_version = 2; + state.logging_level = DEFAULT_LOGGING_LEVEL; + state.listen_port = DEFAULT_GDB_LISTEN_PORT; + state.reset = 1; /* By default, reset board */ + parse_options(argc, argv, &state); + switch (state.stlink_version) { + case 2: + sl = stlink_open_usb(state.logging_level, 0); + if(sl == NULL) return 1; + break; + case 1: + sl = stlink_v1_open(state.logging_level, 0); + if(sl == NULL) return 1; + break; } connected_stlink = sl; @@ -193,44 +192,44 @@ int main(int argc, char** argv) { signal(SIGTERM, &cleanup); if (state.reset) { - stlink_reset(sl); + stlink_reset(sl); } - printf("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); + printf("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); - voltage = stlink_target_voltage(sl); - if (voltage != -1) { - printf("Target voltage is %d mV.\n", voltage); - } + voltage = stlink_target_voltage(sl); + if (voltage != -1) { + printf("Target voltage is %d mV.\n", voltage); + } - sl->verbose=0; + sl->verbose=0; - current_memory_map = make_memory_map(sl); + current_memory_map = make_memory_map(sl); #ifdef __MINGW32__ - WSADATA wsadata; - if (WSAStartup(MAKEWORD(2,2),&wsadata) !=0 ) { - goto winsock_error; - } + WSADATA wsadata; + if (WSAStartup(MAKEWORD(2,2),&wsadata) !=0 ) { + goto winsock_error; + } #endif - do { - serve(sl, &state); + do { + serve(sl, &state); - /* Continue */ - stlink_run(sl); - } while (state.persistent); + /* Continue */ + stlink_run(sl); + } while (state.persistent); #ifdef __MINGW32__ winsock_error: - WSACleanup(); + WSACleanup(); #endif - /* Switch back to mass storage mode before closing. */ - stlink_exit_debug_mode(sl); - stlink_close(sl); + /* Switch back to mass storage mode before closing. */ + stlink_exit_debug_mode(sl); + stlink_close(sl); - return 0; + return 0; } static const char* const target_description_F4 = @@ -299,59 +298,59 @@ static const char* const target_description_F4 = ""; static const char* const memory_map_template_F4 = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // ccm ram - " " // sram - " " //Sectors 0..3 - " 0x4000" //16kB - " " - " " //Sector 4 - " 0x10000" //64kB - " " - " " //Sectors 5..11 - " 0x20000" //128kB - " " - " " // peripheral regs - " " // cortex regs - " " // bootrom - " " // option byte area - ""; + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // ccm ram + " " // sram + " " //Sectors 0..3 + " 0x4000" //16kB + " " + " " //Sector 4 + " 0x10000" //64kB + " " + " " //Sectors 5..11 + " 0x20000" //128kB + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // option byte area + ""; static const char* const memory_map_template = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram 8k - " " - " 0x%zx" - " " - " " // peripheral regs - " " // cortex regs - " " // bootrom - " " // option byte area - ""; + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // sram 8k + " " + " 0x%zx" + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // option byte area + ""; char* make_memory_map(stlink_t *sl) { - /* This will be freed in serve() */ - char* map = malloc(4096); - map[0] = '\0'; + /* This will be freed in serve() */ + char* map = malloc(4096); + map[0] = '\0'; - if(sl->chip_id==STM32_CHIPID_F4) { - strcpy(map, memory_map_template_F4); + if(sl->chip_id==STM32_CHIPID_F4) { + strcpy(map, memory_map_template_F4); } else { snprintf(map, 4096, memory_map_template, - sl->flash_size, - sl->sram_size, - sl->flash_size, sl->flash_pgsz, - sl->sys_base, sl->sys_size); + sl->flash_size, + sl->sram_size, + sl->flash_size, sl->flash_pgsz, + sl->sys_base, sl->sys_size); } - return map; + return map; } @@ -375,101 +374,101 @@ char* make_memory_map(stlink_t *sl) { enum watchfun { WATCHDISABLED = 0, WATCHREAD = 5, WATCHWRITE = 6, WATCHACCESS = 7 }; struct code_hw_watchpoint { - stm32_addr_t addr; - uint8_t mask; - enum watchfun fun; + stm32_addr_t addr; + uint8_t mask; + enum watchfun fun; }; struct code_hw_watchpoint data_watches[DATA_WATCH_NUM]; static void init_data_watchpoints(stlink_t *sl) { - #if DEBUG - printf("init watchpoints\n"); - #endif - - // set trcena in debug command to turn on dwt unit - stlink_write_debug32(sl, 0xE000EDFC, - stlink_read_debug32(sl, 0xE000EDFC) | (1<<24)); - - // make sure all watchpoints are cleared - for(int i = 0; i < DATA_WATCH_NUM; i++) { - data_watches[i].fun = WATCHDISABLED; - stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); - } +#if DEBUG + printf("init watchpoints\n"); +#endif + + // set trcena in debug command to turn on dwt unit + stlink_write_debug32(sl, 0xE000EDFC, + stlink_read_debug32(sl, 0xE000EDFC) | (1<<24)); + + // make sure all watchpoints are cleared + for(int i = 0; i < DATA_WATCH_NUM; i++) { + data_watches[i].fun = WATCHDISABLED; + stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); + } } static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len) { - int i = 0; - uint32_t mask; - - // computer mask - // find a free watchpoint - // configure - - mask = -1; - i = len; - while(i) { - i >>= 1; - mask++; - } - - if((mask != (uint32_t)-1) && (mask < 16)) { - for(i = 0; i < DATA_WATCH_NUM; i++) { - // is this an empty slot ? - if(data_watches[i].fun == WATCHDISABLED) { - #if DEBUG - printf("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len); - #endif - - data_watches[i].fun = wf; - data_watches[i].addr = addr; - data_watches[i].mask = mask; - - // insert comparator address - stlink_write_debug32(sl, 0xE0001020 + i * 16, addr); - - // insert mask - stlink_write_debug32(sl, 0xE0001024 + i * 16, mask); - - // insert function - stlink_write_debug32(sl, 0xE0001028 + i * 16, wf); - - // just to make sure the matched bit is clear ! - stlink_read_debug32(sl, 0xE0001028 + i * 16); - return 0; - } - } - } - - #if DEBUG - printf("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len); - #endif - return -1; + int i = 0; + uint32_t mask; + + // computer mask + // find a free watchpoint + // configure + + mask = -1; + i = len; + while(i) { + i >>= 1; + mask++; + } + + if((mask != (uint32_t)-1) && (mask < 16)) { + for(i = 0; i < DATA_WATCH_NUM; i++) { + // is this an empty slot ? + if(data_watches[i].fun == WATCHDISABLED) { +#if DEBUG + printf("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len); +#endif + + data_watches[i].fun = wf; + data_watches[i].addr = addr; + data_watches[i].mask = mask; + + // insert comparator address + stlink_write_debug32(sl, 0xE0001020 + i * 16, addr); + + // insert mask + stlink_write_debug32(sl, 0xE0001024 + i * 16, mask); + + // insert function + stlink_write_debug32(sl, 0xE0001028 + i * 16, wf); + + // just to make sure the matched bit is clear ! + stlink_read_debug32(sl, 0xE0001028 + i * 16); + return 0; + } + } + } + +#if DEBUG + printf("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len); +#endif + return -1; } static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { - int i; + int i; - for(i = 0 ; i < DATA_WATCH_NUM; i++) { - if((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) { - #if DEBUG - printf("delete watchpoint %d addr %x\n", i, addr); - #endif + for(i = 0 ; i < DATA_WATCH_NUM; i++) { + if((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) { +#if DEBUG + printf("delete watchpoint %d addr %x\n", i, addr); +#endif - data_watches[i].fun = WATCHDISABLED; - stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); + data_watches[i].fun = WATCHDISABLED; + stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); - return 0; - } - } + return 0; + } + } - #if DEBUG - printf("failure: delete watchpoint addr %x\n", addr); - #endif +#if DEBUG + printf("failure: delete watchpoint addr %x\n", addr); +#endif - return -1; + return -1; } #define CODE_BREAK_NUM 6 @@ -478,814 +477,813 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) #define CODE_BREAK_HIGH 0x02 struct code_hw_breakpoint { - stm32_addr_t addr; - int type; + stm32_addr_t addr; + int type; }; struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM]; static void init_code_breakpoints(stlink_t *sl) { - memset(sl->q_buf, 0, 4); - stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/); - unsigned int val = stlink_read_debug32(sl, CM3_REG_FP_CTRL); - if (((val & 3) != 1) || + memset(sl->q_buf, 0, 4); + stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/); + unsigned int val = stlink_read_debug32(sl, CM3_REG_FP_CTRL); + if (((val & 3) != 1) || ((((val >> 8) & 0x70) | ((val >> 4) & 0xf)) != CODE_BREAK_NUM) || (((val >> 8) & 0xf) != CODE_LIT_NUM)){ - fprintf(stderr, "[FP_CTRL] = 0x%08x expecting 0x%08x\n", val, - ((CODE_BREAK_NUM & 0x70) << 8) | (CODE_LIT_NUM << 8) | ((CODE_BREAK_NUM & 0xf) << 4) | 1); - } - + fprintf(stderr, "[FP_CTRL] = 0x%08x expecting 0x%08x\n", val, + ((CODE_BREAK_NUM & 0x70) << 8) | (CODE_LIT_NUM << 8) | ((CODE_BREAK_NUM & 0xf) << 4) | 1); + } + - for(int i = 0; i < CODE_BREAK_NUM; i++) { - code_breaks[i].type = 0; - stlink_write_debug32(sl, CM3_REG_FP_COMP0 + i * 4, 0); - } + for(int i = 0; i < CODE_BREAK_NUM; i++) { + code_breaks[i].type = 0; + stlink_write_debug32(sl, CM3_REG_FP_COMP0 + i * 4, 0); + } } static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { - stm32_addr_t fpb_addr = addr & ~0x3; - int type = addr & 0x2 ? CODE_BREAK_HIGH : CODE_BREAK_LOW; - - if(addr & 1) { - fprintf(stderr, "update_code_breakpoint: unaligned address %08x\n", addr); - return -1; - } - - int id = -1; - for(int i = 0; i < CODE_BREAK_NUM; i++) { - if(fpb_addr == code_breaks[i].addr || - (set && code_breaks[i].type == 0)) { - id = i; - break; - } - } - - if(id == -1) { - if(set) return -1; // Free slot not found - else return 0; // Breakpoint is already removed - } - - struct code_hw_breakpoint* brk = &code_breaks[id]; - - brk->addr = fpb_addr; - - if(set) brk->type |= type; - else brk->type &= ~type; - - if(brk->type == 0) { - #if DEBUG - printf("clearing hw break %d\n", id); - #endif - - stlink_write_debug32(sl, 0xe0002008 + id * 4, 0); - } else { - uint32_t mask = (brk->addr) | 1 | (brk->type << 30); - - #if DEBUG - printf("setting hw break %d at %08x (%d)\n", - id, brk->addr, brk->type); - printf("reg %08x \n", - mask); - #endif - - stlink_write_debug32(sl, 0xe0002008 + id * 4, mask); - } - - return 0; + stm32_addr_t fpb_addr = addr & ~0x3; + int type = addr & 0x2 ? CODE_BREAK_HIGH : CODE_BREAK_LOW; + + if(addr & 1) { + fprintf(stderr, "update_code_breakpoint: unaligned address %08x\n", addr); + return -1; + } + + int id = -1; + for(int i = 0; i < CODE_BREAK_NUM; i++) { + if(fpb_addr == code_breaks[i].addr || + (set && code_breaks[i].type == 0)) { + id = i; + break; + } + } + + if(id == -1) { + if(set) return -1; // Free slot not found + else return 0; // Breakpoint is already removed + } + + struct code_hw_breakpoint* brk = &code_breaks[id]; + + brk->addr = fpb_addr; + + if(set) brk->type |= type; + else brk->type &= ~type; + + if(brk->type == 0) { +#if DEBUG + printf("clearing hw break %d\n", id); +#endif + + stlink_write_debug32(sl, 0xe0002008 + id * 4, 0); + } else { + uint32_t mask = (brk->addr) | 1 | (brk->type << 30); + +#if DEBUG + printf("setting hw break %d at %08x (%d)\n", + id, brk->addr, brk->type); + printf("reg %08x \n", + mask); +#endif + + stlink_write_debug32(sl, 0xe0002008 + id * 4, mask); + } + + return 0; } struct flash_block { - stm32_addr_t addr; - unsigned length; - uint8_t* data; + stm32_addr_t addr; + unsigned length; + uint8_t* data; - struct flash_block* next; + struct flash_block* next; }; static struct flash_block* flash_root; static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { - if(addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) { - fprintf(stderr, "flash_add_block: incorrect bounds\n"); - return -1; - } + if(addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) { + fprintf(stderr, "flash_add_block: incorrect bounds\n"); + return -1; + } - stlink_calculate_pagesize(sl, addr); - if(addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) { - fprintf(stderr, "flash_add_block: unaligned block\n"); - return -1; - } + stlink_calculate_pagesize(sl, addr); + if(addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) { + fprintf(stderr, "flash_add_block: unaligned block\n"); + return -1; + } - struct flash_block* new = malloc(sizeof(struct flash_block)); - new->next = flash_root; + struct flash_block* new = malloc(sizeof(struct flash_block)); + new->next = flash_root; - new->addr = addr; - new->length = length; - new->data = calloc(length, 1); + new->addr = addr; + new->length = length; + new->data = calloc(length, 1); - flash_root = new; + flash_root = new; - return 0; + return 0; } static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { - unsigned int fit_blocks = 0, fit_length = 0; - - for(struct flash_block* fb = flash_root; fb; fb = fb->next) { - /* Block: ------X------Y-------- - * Data: a-----b - * a--b - * a-----------b - * Block intersects with data, if: - * a < Y && b > x - */ - - unsigned X = fb->addr, Y = fb->addr + fb->length; - unsigned a = addr, b = addr + length; - if(a < Y && b > X) { - // from start of the block - unsigned start = (a > X ? a : X) - X; - unsigned end = (b > Y ? Y : b) - X; - - memcpy(fb->data + start, data, end - start); - - fit_blocks++; - fit_length += end - start; - } - } - - if(fit_blocks == 0) { - fprintf(stderr, "Unfit data block %08x -> %04x\n", addr, length); - return -1; - } - - if(fit_length != length) { - fprintf(stderr, "warning: data block %08x -> %04x truncated to %04x\n", - addr, length, fit_length); - fprintf(stderr, "(this is not an error, just a GDB glitch)\n"); - } - - return 0; + unsigned int fit_blocks = 0, fit_length = 0; + + for(struct flash_block* fb = flash_root; fb; fb = fb->next) { + /* Block: ------X------Y-------- + * Data: a-----b + * a--b + * a-----------b + * Block intersects with data, if: + * a < Y && b > x + */ + + unsigned X = fb->addr, Y = fb->addr + fb->length; + unsigned a = addr, b = addr + length; + if(a < Y && b > X) { + // from start of the block + unsigned start = (a > X ? a : X) - X; + unsigned end = (b > Y ? Y : b) - X; + + memcpy(fb->data + start, data, end - start); + + fit_blocks++; + fit_length += end - start; + } + } + + if(fit_blocks == 0) { + fprintf(stderr, "Unfit data block %08x -> %04x\n", addr, length); + return -1; + } + + if(fit_length != length) { + fprintf(stderr, "warning: data block %08x -> %04x truncated to %04x\n", + addr, length, fit_length); + fprintf(stderr, "(this is not an error, just a GDB glitch)\n"); + } + + return 0; } static int flash_go(stlink_t *sl) { - int error = -1; + int error = -1; - // Some kinds of clock settings do not allow writing to flash. - stlink_reset(sl); + // Some kinds of clock settings do not allow writing to flash. + stlink_reset(sl); - for(struct flash_block* fb = flash_root; fb; fb = fb->next) { - #if DEBUG - printf("flash_do: block %08x -> %04x\n", fb->addr, fb->length); - #endif + for(struct flash_block* fb = flash_root; fb; fb = fb->next) { +#if DEBUG + printf("flash_do: block %08x -> %04x\n", fb->addr, fb->length); +#endif - unsigned length = fb->length; - for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += FLASH_PAGE) { + unsigned length = fb->length; + for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += FLASH_PAGE) { - //Update FLASH_PAGE - stlink_calculate_pagesize(sl, page); + //Update FLASH_PAGE + stlink_calculate_pagesize(sl, page); - #if DEBUG - printf("flash_do: page %08x\n", page); - #endif +#if DEBUG + printf("flash_do: page %08x\n", page); +#endif - if(stlink_write_flash(sl, page, fb->data + (page - fb->addr), - length > FLASH_PAGE ? FLASH_PAGE : length) < 0) - goto error; - } - } + if(stlink_write_flash(sl, page, fb->data + (page - fb->addr), + length > FLASH_PAGE ? FLASH_PAGE : length) < 0) + goto error; + } + } - stlink_reset(sl); + stlink_reset(sl); - error = 0; + error = 0; error: - for(struct flash_block* fb = flash_root, *next; fb; fb = next) { - next = fb->next; - free(fb->data); - free(fb); - } + for(struct flash_block* fb = flash_root, *next; fb; fb = next) { + next = fb->next; + free(fb->data); + free(fb); + } - flash_root = NULL; + flash_root = NULL; - return error; + return error; } int serve(stlink_t *sl, st_state_t *st) { - int sock = socket(AF_INET, SOCK_STREAM, 0); - if(sock < 0) { - perror("socket"); - return 1; - } - - unsigned int val = 1; - setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val)); - - struct sockaddr_in serv_addr; - memset(&serv_addr,0,sizeof(struct sockaddr_in)); - serv_addr.sin_family = AF_INET; - serv_addr.sin_addr.s_addr = INADDR_ANY; - serv_addr.sin_port = htons(st->listen_port); - - if(bind(sock, (struct sockaddr *) &serv_addr, sizeof(serv_addr)) < 0) { - perror("bind"); - return 1; - } - - if(listen(sock, 5) < 0) { - perror("listen"); - return 1; - } - - printf("Listening at *:%d...\n", st->listen_port); - - int client = accept(sock, NULL, NULL); - //signal (SIGINT, SIG_DFL); - if(client < 0) { - perror("accept"); - return 1; - } - - close(sock); - - stlink_force_debug(sl); - if (st->reset) { - stlink_reset(sl); + int sock = socket(AF_INET, SOCK_STREAM, 0); + if(sock < 0) { + perror("socket"); + return 1; + } + + unsigned int val = 1; + setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val)); + + struct sockaddr_in serv_addr; + memset(&serv_addr,0,sizeof(struct sockaddr_in)); + serv_addr.sin_family = AF_INET; + serv_addr.sin_addr.s_addr = INADDR_ANY; + serv_addr.sin_port = htons(st->listen_port); + + if(bind(sock, (struct sockaddr *) &serv_addr, sizeof(serv_addr)) < 0) { + perror("bind"); + return 1; + } + + if(listen(sock, 5) < 0) { + perror("listen"); + return 1; + } + + printf("Listening at *:%d...\n", st->listen_port); + + int client = accept(sock, NULL, NULL); + //signal (SIGINT, SIG_DFL); + if(client < 0) { + perror("accept"); + return 1; + } + + close(sock); + + stlink_force_debug(sl); + if (st->reset) { + stlink_reset(sl); } - init_code_breakpoints(sl); - init_data_watchpoints(sl); - - printf("GDB connected.\n"); - - /* - * To allow resetting the chip from GDB it is required to - * emulate attaching and detaching to target. - */ - unsigned int attached = 1; - - while(1) { - char* packet; - - int status = gdb_recv_packet(client, &packet); - if(status < 0) { - fprintf(stderr, "cannot recv: %d\n", status); - return 1; - } - - #if DEBUG - printf("recv: %s\n", packet); - #endif - - char* reply = NULL; - reg regp; - - switch(packet[0]) { - case 'q': { - if(packet[1] == 'P' || packet[1] == 'C' || packet[1] == 'L') { - reply = strdup(""); - break; - } - - char *separator = strstr(packet, ":"), *params = ""; - if(separator == NULL) { - separator = packet + strlen(packet); - } else { - params = separator + 1; - } - - unsigned queryNameLength = (separator - &packet[1]); - char* queryName = calloc(queryNameLength + 1, 1); - strncpy(queryName, &packet[1], queryNameLength); - - #if DEBUG - printf("query: %s;%s\n", queryName, params); - #endif - - if(!strcmp(queryName, "Supported")) { - if(sl->chip_id==STM32_CHIPID_F4) { - reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); + init_code_breakpoints(sl); + init_data_watchpoints(sl); + + printf("GDB connected.\n"); + + /* + * To allow resetting the chip from GDB it is required to + * emulate attaching and detaching to target. + */ + unsigned int attached = 1; + + while(1) { + char* packet; + + int status = gdb_recv_packet(client, &packet); + if(status < 0) { + fprintf(stderr, "cannot recv: %d\n", status); + return 1; + } + +#if DEBUG + printf("recv: %s\n", packet); +#endif + + char* reply = NULL; + reg regp; + + switch(packet[0]) { + case 'q': { + if(packet[1] == 'P' || packet[1] == 'C' || packet[1] == 'L') { + reply = strdup(""); + break; } - else { - reply = strdup("PacketSize=3fff;qXfer:memory-map:read+"); + + char *separator = strstr(packet, ":"), *params = ""; + if(separator == NULL) { + separator = packet + strlen(packet); + } else { + params = separator + 1; } - } else if(!strcmp(queryName, "Xfer")) { - char *type, *op, *__s_addr, *s_length; - char *tok = params; - char *annex __attribute__((unused)); - - type = strsep(&tok, ":"); - op = strsep(&tok, ":"); - annex = strsep(&tok, ":"); - __s_addr = strsep(&tok, ","); - s_length = tok; - - unsigned addr = strtoul(__s_addr, NULL, 16), - length = strtoul(s_length, NULL, 16); - - #if DEBUG - printf("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", - type, op, annex, addr, length); - #endif - - const char* data = NULL; - - if(!strcmp(type, "memory-map") && !strcmp(op, "read")) - data = current_memory_map; - - if(!strcmp(type, "features") && !strcmp(op, "read")) - data = target_description_F4; - - if(data) { - unsigned data_length = strlen(data); - if(addr + length > data_length) - length = data_length - addr; - - if(length == 0) { - reply = strdup("l"); - } else { - reply = calloc(length + 2, 1); - reply[0] = 'm'; - strncpy(&reply[1], data, length); - } - } - } else if(!strncmp(queryName, "Rcmd,",4)) { - // Rcmd uses the wrong separator - char *separator = strstr(packet, ","), *params = ""; - if(separator == NULL) { - separator = packet + strlen(packet); - } else { - params = separator + 1; - } - - - if (!strncmp(params,"726573756d65",12)) {// resume + + unsigned queryNameLength = (separator - &packet[1]); + char* queryName = calloc(queryNameLength + 1, 1); + strncpy(queryName, &packet[1], queryNameLength); + +#if DEBUG + printf("query: %s;%s\n", queryName, params); +#endif + + if(!strcmp(queryName, "Supported")) { + if(sl->chip_id==STM32_CHIPID_F4) { + reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); + } + else { + reply = strdup("PacketSize=3fff;qXfer:memory-map:read+"); + } + } else if(!strcmp(queryName, "Xfer")) { + char *type, *op, *__s_addr, *s_length; + char *tok = params; + char *annex __attribute__((unused)); + + type = strsep(&tok, ":"); + op = strsep(&tok, ":"); + annex = strsep(&tok, ":"); + __s_addr = strsep(&tok, ","); + s_length = tok; + + unsigned addr = strtoul(__s_addr, NULL, 16), + length = strtoul(s_length, NULL, 16); + +#if DEBUG + printf("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", + type, op, annex, addr, length); +#endif + + const char* data = NULL; + + if(!strcmp(type, "memory-map") && !strcmp(op, "read")) + data = current_memory_map; + + if(!strcmp(type, "features") && !strcmp(op, "read")) + data = target_description_F4; + + if(data) { + unsigned data_length = strlen(data); + if(addr + length > data_length) + length = data_length - addr; + + if(length == 0) { + reply = strdup("l"); + } else { + reply = calloc(length + 2, 1); + reply[0] = 'm'; + strncpy(&reply[1], data, length); + } + } + } else if(!strncmp(queryName, "Rcmd,",4)) { + // Rcmd uses the wrong separator + char *separator = strstr(packet, ","), *params = ""; + if(separator == NULL) { + separator = packet + strlen(packet); + } else { + params = separator + 1; + } + + + if (!strncmp(params,"726573756d65",12)) {// resume #if DEBUG - printf("Rcmd: resume\n"); + printf("Rcmd: resume\n"); #endif - stlink_run(sl); + stlink_run(sl); + + reply = strdup("OK"); + } else if (!strncmp(params,"68616c74",8)) { //halt + reply = strdup("OK"); - reply = strdup("OK"); - } else if (!strncmp(params,"68616c74",8)) { //halt - reply = strdup("OK"); + stlink_force_debug(sl); - stlink_force_debug(sl); +#if DEBUG + printf("Rcmd: halt\n"); +#endif + } else if (!strncmp(params,"6a7461675f7265736574",20)) { //jtag_reset + reply = strdup("OK"); + + stlink_jtag_reset(sl, 1); + stlink_jtag_reset(sl, 0); + stlink_force_debug(sl); #if DEBUG - printf("Rcmd: halt\n"); + printf("Rcmd: jtag_reset\n"); #endif - } else if (!strncmp(params,"6a7461675f7265736574",20)) { //jtag_reset - reply = strdup("OK"); + } else if (!strncmp(params,"7265736574",10)) { //reset + reply = strdup("OK"); - stlink_jtag_reset(sl, 1); - stlink_jtag_reset(sl, 0); - stlink_force_debug(sl); + stlink_force_debug(sl); + stlink_reset(sl); + init_code_breakpoints(sl); + init_data_watchpoints(sl); #if DEBUG - printf("Rcmd: jtag_reset\n"); + printf("Rcmd: reset\n"); +#endif + } else { +#if DEBUG + printf("Rcmd: %s\n", params); #endif - } else if (!strncmp(params,"7265736574",10)) { //reset - reply = strdup("OK"); - stlink_force_debug(sl); - stlink_reset(sl); - init_code_breakpoints(sl); - init_data_watchpoints(sl); + } + + } + + if(reply == NULL) + reply = strdup(""); + + free(queryName); + + break; + } + + case 'v': { + char *params = NULL; + char *cmdName = strtok_r(packet, ":;", ¶ms); + + cmdName++; // vCommand -> Command + + if(!strcmp(cmdName, "FlashErase")) { + char *__s_addr, *s_length; + char *tok = params; + + __s_addr = strsep(&tok, ","); + s_length = tok; + + unsigned addr = strtoul(__s_addr, NULL, 16), + length = strtoul(s_length, NULL, 16); #if DEBUG - printf("Rcmd: reset\n"); + printf("FlashErase: addr:%08x,len:%04x\n", + addr, length); #endif - } else { + + if(flash_add_block(addr, length, sl) < 0) { + reply = strdup("E00"); + } else { + reply = strdup("OK"); + } + } else if(!strcmp(cmdName, "FlashWrite")) { + char *__s_addr, *data; + char *tok = params; + + __s_addr = strsep(&tok, ":"); + data = tok; + + unsigned addr = strtoul(__s_addr, NULL, 16); + unsigned data_length = status - (data - packet); + + // Length of decoded data cannot be more than + // encoded, as escapes are removed. + // Additional byte is reserved for alignment fix. + uint8_t *decoded = calloc(data_length + 1, 1); + unsigned dec_index = 0; + for(unsigned int i = 0; i < data_length; i++) { + if(data[i] == 0x7d) { + i++; + decoded[dec_index++] = data[i] ^ 0x20; + } else { + decoded[dec_index++] = data[i]; + } + } + + // Fix alignment + if(dec_index % 2 != 0) + dec_index++; + #if DEBUG - printf("Rcmd: %s\n", params); + printf("binary packet %d -> %d\n", data_length, dec_index); #endif - } - - } - - if(reply == NULL) - reply = strdup(""); - - free(queryName); - - break; - } - - case 'v': { - char *params = NULL; - char *cmdName = strtok_r(packet, ":;", ¶ms); - - cmdName++; // vCommand -> Command - - if(!strcmp(cmdName, "FlashErase")) { - char *__s_addr, *s_length; - char *tok = params; - - __s_addr = strsep(&tok, ","); - s_length = tok; - - unsigned addr = strtoul(__s_addr, NULL, 16), - length = strtoul(s_length, NULL, 16); - - #if DEBUG - printf("FlashErase: addr:%08x,len:%04x\n", - addr, length); - #endif - - if(flash_add_block(addr, length, sl) < 0) { - reply = strdup("E00"); - } else { - reply = strdup("OK"); - } - } else if(!strcmp(cmdName, "FlashWrite")) { - char *__s_addr, *data; - char *tok = params; - - __s_addr = strsep(&tok, ":"); - data = tok; - - unsigned addr = strtoul(__s_addr, NULL, 16); - unsigned data_length = status - (data - packet); - - // Length of decoded data cannot be more than - // encoded, as escapes are removed. - // Additional byte is reserved for alignment fix. - uint8_t *decoded = calloc(data_length + 1, 1); - unsigned dec_index = 0; - for(unsigned int i = 0; i < data_length; i++) { - if(data[i] == 0x7d) { - i++; - decoded[dec_index++] = data[i] ^ 0x20; - } else { - decoded[dec_index++] = data[i]; - } - } - - // Fix alignment - if(dec_index % 2 != 0) - dec_index++; - - #if DEBUG - printf("binary packet %d -> %d\n", data_length, dec_index); - #endif - - if(flash_populate(addr, decoded, dec_index) < 0) { - reply = strdup("E00"); - } else { - reply = strdup("OK"); - } - } else if(!strcmp(cmdName, "FlashDone")) { - if(flash_go(sl) < 0) { - reply = strdup("E00"); - } else { - reply = strdup("OK"); - } - } else if(!strcmp(cmdName, "Kill")) { - attached = 0; - - reply = strdup("OK"); - } - - if(reply == NULL) - reply = strdup(""); - - break; - } - - case 'c': - stlink_run(sl); - - while(1) { - int status = gdb_check_for_interrupt(client); - if(status < 0) { - fprintf(stderr, "cannot check for int: %d\n", status); - return 1; - } - - if(status == 1) { - stlink_force_debug(sl); - break; - } - - stlink_status(sl); - if(sl->core_stat == STLINK_CORE_HALTED) { - break; - } - - usleep(100000); - } - - reply = strdup("S05"); // TRAP - break; - - case 's': - stlink_step(sl); - - reply = strdup("S05"); // TRAP - break; - - case '?': - if(attached) { - reply = strdup("S05"); // TRAP - } else { - /* Stub shall reply OK if not attached. */ - reply = strdup("OK"); - } - break; - - case 'g': - stlink_read_all_regs(sl, ®p); - - reply = calloc(8 * 16 + 1, 1); - for(int i = 0; i < 16; i++) - sprintf(&reply[i * 8], "%08x", htonl(regp.r[i])); - - break; - - case 'p': { - unsigned id = strtoul(&packet[1], NULL, 16); - unsigned myreg = 0xDEADDEAD; - - if(id < 16) { - stlink_read_reg(sl, id, ®p); - myreg = htonl(regp.r[id]); - } else if(id == 0x19) { - stlink_read_reg(sl, 16, ®p); - myreg = htonl(regp.xpsr); - } else if(id == 0x1A) { - stlink_read_reg(sl, 17, ®p); - myreg = htonl(regp.main_sp); - } else if(id == 0x1B) { - stlink_read_reg(sl, 18, ®p); - myreg = htonl(regp.process_sp); - } else if(id == 0x1C) { - stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.control); - } else if(id == 0x1D) { - stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.faultmask); - } else if(id == 0x1E) { - stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.basepri); - } else if(id == 0x1F) { - stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.primask); - } else if(id >= 0x20 && id < 0x40) { - stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.s[id-0x20]); - } else if(id == 0x40) { - stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.fpscr); - } else { - reply = strdup("E00"); - } - - reply = calloc(8 + 1, 1); - sprintf(reply, "%08x", myreg); - - break; - } - - case 'P': { - char* s_reg = &packet[1]; - char* s_value = strstr(&packet[1], "=") + 1; - - unsigned reg = strtoul(s_reg, NULL, 16); - unsigned value = strtoul(s_value, NULL, 16); - - if(reg < 16) { - stlink_write_reg(sl, ntohl(value), reg); - } else if(reg == 0x19) { - stlink_write_reg(sl, ntohl(value), 16); - } else if(reg == 0x1A) { - stlink_write_reg(sl, ntohl(value), 17); - } else if(reg == 0x1B) { - stlink_write_reg(sl, ntohl(value), 18); - } else if(reg == 0x1C) { - stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if(reg == 0x1D) { - stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if(reg == 0x1E) { - stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if(reg == 0x1F) { - stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if(reg >= 0x20 && reg < 0x40) { - stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if(reg == 0x40) { - stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else { - reply = strdup("E00"); - } - - if(!reply) { - reply = strdup("OK"); - } - - break; - } - - case 'G': - for(int i = 0; i < 16; i++) { - char str[9] = {0}; - strncpy(str, &packet[1 + i * 8], 8); - uint32_t reg = strtoul(str, NULL, 16); - stlink_write_reg(sl, ntohl(reg), i); - } - - reply = strdup("OK"); - break; - - case 'm': { - char* s_start = &packet[1]; - char* s_count = strstr(&packet[1], ",") + 1; - - stm32_addr_t start = strtoul(s_start, NULL, 16); - unsigned count = strtoul(s_count, NULL, 16); - - unsigned adj_start = start % 4; - unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; - - stlink_read_mem32(sl, start - adj_start, count_rnd); - - reply = calloc(count * 2 + 1, 1); - for(unsigned int i = 0; i < count; i++) { - reply[i * 2 + 0] = hex[sl->q_buf[i + adj_start] >> 4]; - reply[i * 2 + 1] = hex[sl->q_buf[i + adj_start] & 0xf]; - } - - break; - } - - case 'M': { - char* s_start = &packet[1]; - char* s_count = strstr(&packet[1], ",") + 1; - char* hexdata = strstr(packet, ":") + 1; - - stm32_addr_t start = strtoul(s_start, NULL, 16); - unsigned count = strtoul(s_count, NULL, 16); - - if(start % 4) { - unsigned align_count = 4 - start % 4; - if (align_count > count) align_count = count; - for(unsigned int i = 0; i < align_count; i ++) { - char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; - uint8_t byte = strtoul(hex, NULL, 16); - sl->q_buf[i] = byte; - } - stlink_write_mem8(sl, start, align_count); - start += align_count; - count -= align_count; - hexdata += 2*align_count; - } - - if(count - count % 4) { - unsigned aligned_count = count - count % 4; - - for(unsigned int i = 0; i < aligned_count; i ++) { - char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; - uint8_t byte = strtoul(hex, NULL, 16); - sl->q_buf[i] = byte; - } - stlink_write_mem32(sl, start, aligned_count); - count -= aligned_count; - start += aligned_count; - hexdata += 2*aligned_count; - } - - if(count) { - for(unsigned int i = 0; i < count; i ++) { - char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; - uint8_t byte = strtoul(hex, NULL, 16); - sl->q_buf[i] = byte; - } - stlink_write_mem8(sl, start, count); - } - reply = strdup("OK"); - break; - } - - case 'Z': { - char *endptr; - stm32_addr_t addr = strtoul(&packet[3], &endptr, 16); - stm32_addr_t len = strtoul(&endptr[1], NULL, 16); - - switch (packet[1]) { - case '1': - if(update_code_breakpoint(sl, addr, 1) < 0) { - reply = strdup("E00"); - } else { - reply = strdup("OK"); - } - break; - - case '2': // insert write watchpoint - case '3': // insert read watchpoint - case '4': // insert access watchpoint - { - enum watchfun wf; - if(packet[1] == '2') { - wf = WATCHWRITE; - } else if(packet[1] == '3') { - wf = WATCHREAD; - } else { - wf = WATCHACCESS; - } - - if(add_data_watchpoint(sl, wf, addr, len) < 0) { + if(flash_populate(addr, decoded, dec_index) < 0) { + reply = strdup("E00"); + } else { + reply = strdup("OK"); + } + } else if(!strcmp(cmdName, "FlashDone")) { + if(flash_go(sl) < 0) { reply = strdup("E00"); } else { reply = strdup("OK"); + } + } else if(!strcmp(cmdName, "Kill")) { + attached = 0; + + reply = strdup("OK"); + } + + if(reply == NULL) + reply = strdup(""); + + break; + } + + case 'c': + stlink_run(sl); + + while(1) { + int status = gdb_check_for_interrupt(client); + if(status < 0) { + fprintf(stderr, "cannot check for int: %d\n", status); + return 1; + } + + if(status == 1) { + stlink_force_debug(sl); + break; + } + + stlink_status(sl); + if(sl->core_stat == STLINK_CORE_HALTED) { + break; + } + + usleep(100000); + } + + reply = strdup("S05"); // TRAP + break; + + case 's': + stlink_step(sl); + + reply = strdup("S05"); // TRAP + break; + + case '?': + if(attached) { + reply = strdup("S05"); // TRAP + } else { + /* Stub shall reply OK if not attached. */ + reply = strdup("OK"); + } + break; + + case 'g': + stlink_read_all_regs(sl, ®p); + + reply = calloc(8 * 16 + 1, 1); + for(int i = 0; i < 16; i++) + sprintf(&reply[i * 8], "%08x", htonl(regp.r[i])); + + break; + + case 'p': { + unsigned id = strtoul(&packet[1], NULL, 16); + unsigned myreg = 0xDEADDEAD; + + if(id < 16) { + stlink_read_reg(sl, id, ®p); + myreg = htonl(regp.r[id]); + } else if(id == 0x19) { + stlink_read_reg(sl, 16, ®p); + myreg = htonl(regp.xpsr); + } else if(id == 0x1A) { + stlink_read_reg(sl, 17, ®p); + myreg = htonl(regp.main_sp); + } else if(id == 0x1B) { + stlink_read_reg(sl, 18, ®p); + myreg = htonl(regp.process_sp); + } else if(id == 0x1C) { + stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.control); + } else if(id == 0x1D) { + stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.faultmask); + } else if(id == 0x1E) { + stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.basepri); + } else if(id == 0x1F) { + stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.primask); + } else if(id >= 0x20 && id < 0x40) { + stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.s[id-0x20]); + } else if(id == 0x40) { + stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.fpscr); + } else { + reply = strdup("E00"); + } + + reply = calloc(8 + 1, 1); + sprintf(reply, "%08x", myreg); + + break; + } + + case 'P': { + char* s_reg = &packet[1]; + char* s_value = strstr(&packet[1], "=") + 1; + + unsigned reg = strtoul(s_reg, NULL, 16); + unsigned value = strtoul(s_value, NULL, 16); + + if(reg < 16) { + stlink_write_reg(sl, ntohl(value), reg); + } else if(reg == 0x19) { + stlink_write_reg(sl, ntohl(value), 16); + } else if(reg == 0x1A) { + stlink_write_reg(sl, ntohl(value), 17); + } else if(reg == 0x1B) { + stlink_write_reg(sl, ntohl(value), 18); + } else if(reg == 0x1C) { + stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if(reg == 0x1D) { + stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if(reg == 0x1E) { + stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if(reg == 0x1F) { + stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if(reg >= 0x20 && reg < 0x40) { + stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if(reg == 0x40) { + stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else { + reply = strdup("E00"); + } + + if(!reply) { + reply = strdup("OK"); + } + + break; + } + + case 'G': + for(int i = 0; i < 16; i++) { + char str[9] = {0}; + strncpy(str, &packet[1 + i * 8], 8); + uint32_t reg = strtoul(str, NULL, 16); + stlink_write_reg(sl, ntohl(reg), i); + } + + reply = strdup("OK"); + break; + + case 'm': { + char* s_start = &packet[1]; + char* s_count = strstr(&packet[1], ",") + 1; + + stm32_addr_t start = strtoul(s_start, NULL, 16); + unsigned count = strtoul(s_count, NULL, 16); + + unsigned adj_start = start % 4; + unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; + + stlink_read_mem32(sl, start - adj_start, count_rnd); + + reply = calloc(count * 2 + 1, 1); + for(unsigned int i = 0; i < count; i++) { + reply[i * 2 + 0] = hex[sl->q_buf[i + adj_start] >> 4]; + reply[i * 2 + 1] = hex[sl->q_buf[i + adj_start] & 0xf]; + } + + break; + } + + case 'M': { + char* s_start = &packet[1]; + char* s_count = strstr(&packet[1], ",") + 1; + char* hexdata = strstr(packet, ":") + 1; + + stm32_addr_t start = strtoul(s_start, NULL, 16); + unsigned count = strtoul(s_count, NULL, 16); + + if(start % 4) { + unsigned align_count = 4 - start % 4; + if (align_count > count) align_count = count; + for(unsigned int i = 0; i < align_count; i ++) { + char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; + uint8_t byte = strtoul(hex, NULL, 16); + sl->q_buf[i] = byte; + } + stlink_write_mem8(sl, start, align_count); + start += align_count; + count -= align_count; + hexdata += 2*align_count; + } + + if(count - count % 4) { + unsigned aligned_count = count - count % 4; + + for(unsigned int i = 0; i < aligned_count; i ++) { + char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; + uint8_t byte = strtoul(hex, NULL, 16); + sl->q_buf[i] = byte; + } + stlink_write_mem32(sl, start, aligned_count); + count -= aligned_count; + start += aligned_count; + hexdata += 2*aligned_count; + } + + if(count) { + for(unsigned int i = 0; i < count; i ++) { + char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; + uint8_t byte = strtoul(hex, NULL, 16); + sl->q_buf[i] = byte; + } + stlink_write_mem8(sl, start, count); + } + reply = strdup("OK"); + break; + } + + case 'Z': { + char *endptr; + stm32_addr_t addr = strtoul(&packet[3], &endptr, 16); + stm32_addr_t len = strtoul(&endptr[1], NULL, 16); + + switch (packet[1]) { + case '1': + if(update_code_breakpoint(sl, addr, 1) < 0) { + reply = strdup("E00"); + } else { + reply = strdup("OK"); + } break; + + case '2': // insert write watchpoint + case '3': // insert read watchpoint + case '4': { // insert access watchpoint + enum watchfun wf; + if(packet[1] == '2') { + wf = WATCHWRITE; + } else if(packet[1] == '3') { + wf = WATCHREAD; + } else { + wf = WATCHACCESS; + } + + if(add_data_watchpoint(sl, wf, addr, len) < 0) { + reply = strdup("E00"); + } else { + reply = strdup("OK"); + break; + } } - } - - default: - reply = strdup(""); - } - break; - } - case 'z': { - char *endptr; - stm32_addr_t addr = strtoul(&packet[3], &endptr, 16); - //stm32_addr_t len = strtoul(&endptr[1], NULL, 16); - - switch (packet[1]) { - case '1': // remove breakpoint - update_code_breakpoint(sl, addr, 0); - reply = strdup("OK"); - break; - - case '2' : // remove write watchpoint - case '3' : // remove read watchpoint - case '4' : // remove access watchpoint - if(delete_data_watchpoint(sl, addr) < 0) { - reply = strdup("E00"); - } else { - reply = strdup("OK"); - break; - } - - default: - reply = strdup(""); - } - break; - } - - case '!': { - /* - * Enter extended mode which allows restarting. - * We do support that always. - */ - - /* - * Also, set to persistent mode - * to allow GDB disconnect. - */ - st->persistent = 1; - - reply = strdup("OK"); - - break; - } - - case 'R': { - /* Reset the core. */ - - stlink_reset(sl); - init_code_breakpoints(sl); - init_data_watchpoints(sl); - - attached = 1; - - reply = strdup("OK"); - - break; - } - - default: - reply = strdup(""); - } - - if(reply) { - #if DEBUG - printf("send: %s\n", reply); - #endif - - int result = gdb_send_packet(client, reply); - if(result != 0) { - fprintf(stderr, "cannot send: %d\n", result); - free(reply); - free(packet); - return 1; - } - - free(reply); - } - - free(packet); - } - - return 0; + + default: + reply = strdup(""); + } + break; + } + case 'z': { + char *endptr; + stm32_addr_t addr = strtoul(&packet[3], &endptr, 16); + //stm32_addr_t len = strtoul(&endptr[1], NULL, 16); + + switch (packet[1]) { + case '1': // remove breakpoint + update_code_breakpoint(sl, addr, 0); + reply = strdup("OK"); + break; + + case '2' : // remove write watchpoint + case '3' : // remove read watchpoint + case '4' : // remove access watchpoint + if(delete_data_watchpoint(sl, addr) < 0) { + reply = strdup("E00"); + } else { + reply = strdup("OK"); + break; + } + + default: + reply = strdup(""); + } + break; + } + + case '!': { + /* + * Enter extended mode which allows restarting. + * We do support that always. + */ + + /* + * Also, set to persistent mode + * to allow GDB disconnect. + */ + st->persistent = 1; + + reply = strdup("OK"); + + break; + } + + case 'R': { + /* Reset the core. */ + + stlink_reset(sl); + init_code_breakpoints(sl); + init_data_watchpoints(sl); + + attached = 1; + + reply = strdup("OK"); + + break; + } + + default: + reply = strdup(""); + } + + if(reply) { +#if DEBUG + printf("send: %s\n", reply); +#endif + + int result = gdb_send_packet(client, reply); + if(result != 0) { + fprintf(stderr, "cannot send: %d\n", result); + free(reply); + free(packet); + return 1; + } + + free(reply); + } + + free(packet); + } + + return 0; } diff --git a/gui/stlink-gui.c b/gui/stlink-gui.c index 3646c3a4f..f60e92db0 100644 --- a/gui/stlink-gui.c +++ b/gui/stlink-gui.c @@ -17,117 +17,117 @@ G_DEFINE_TYPE (STlinkGUI, stlink_gui, G_TYPE_OBJECT); static void stlink_gui_dispose (GObject *gobject) { - G_OBJECT_CLASS (stlink_gui_parent_class)->dispose (gobject); + G_OBJECT_CLASS (stlink_gui_parent_class)->dispose (gobject); } static void stlink_gui_finalize (GObject *gobject) { - G_OBJECT_CLASS (stlink_gui_parent_class)->finalize (gobject); + G_OBJECT_CLASS (stlink_gui_parent_class)->finalize (gobject); } static void stlink_gui_class_init (STlinkGUIClass *klass) { - GObjectClass *gobject_class = G_OBJECT_CLASS (klass); + GObjectClass *gobject_class = G_OBJECT_CLASS (klass); - gobject_class->dispose = stlink_gui_dispose; - gobject_class->finalize = stlink_gui_finalize; + gobject_class->dispose = stlink_gui_dispose; + gobject_class->finalize = stlink_gui_finalize; } static void stlink_gui_init (STlinkGUI *self) { - self->sl = NULL; - self->filename = NULL; + self->sl = NULL; + self->filename = NULL; - self->progress.activity_mode = FALSE; - self->progress.fraction = 0; + self->progress.activity_mode = FALSE; + self->progress.fraction = 0; - self->flash_mem.memory = NULL; - self->flash_mem.size = 0; - self->flash_mem.base = 0; + self->flash_mem.memory = NULL; + self->flash_mem.size = 0; + self->flash_mem.base = 0; - self->file_mem.memory = NULL; - self->file_mem.size = 0; - self->file_mem.base = 0; + self->file_mem.memory = NULL; + self->file_mem.size = 0; + self->file_mem.base = 0; } static gboolean set_info_error_message_idle (STlinkGUI *gui) { - if (gui->error_message != NULL) { - gchar *markup; + if (gui->error_message != NULL) { + gchar *markup; - markup = g_markup_printf_escaped ("%s", gui->error_message); - gtk_label_set_markup (gui->infolabel, markup); - gtk_info_bar_set_message_type (gui->infobar, GTK_MESSAGE_ERROR); - gtk_widget_show (GTK_WIDGET (gui->infobar)); + markup = g_markup_printf_escaped ("%s", gui->error_message); + gtk_label_set_markup (gui->infolabel, markup); + gtk_info_bar_set_message_type (gui->infobar, GTK_MESSAGE_ERROR); + gtk_widget_show (GTK_WIDGET (gui->infobar)); - g_free (markup); - g_free (gui->error_message); - gui->error_message = NULL; - } - return FALSE; + g_free (markup); + g_free (gui->error_message); + gui->error_message = NULL; + } + return FALSE; } static void stlink_gui_set_info_error_message (STlinkGUI *gui, const gchar *message) { - gui->error_message = g_strdup (message); - g_idle_add ((GSourceFunc) set_info_error_message_idle, gui); + gui->error_message = g_strdup (message); + g_idle_add ((GSourceFunc) set_info_error_message_idle, gui); } static void stlink_gui_set_sensitivity (STlinkGUI *gui, gboolean sensitivity) { - gtk_widget_set_sensitive (GTK_WIDGET (gui->open_button), sensitivity); + gtk_widget_set_sensitive (GTK_WIDGET (gui->open_button), sensitivity); - if (sensitivity && gui->sl) - gtk_widget_set_sensitive (GTK_WIDGET (gui->disconnect_button), sensitivity); + if (sensitivity && gui->sl) + gtk_widget_set_sensitive (GTK_WIDGET (gui->disconnect_button), sensitivity); - if (sensitivity && !gui->sl) - gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), sensitivity); + if (sensitivity && !gui->sl) + gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), sensitivity); - if (sensitivity && gui->sl && gui->filename) - gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), sensitivity); + if (sensitivity && gui->sl && gui->filename) + gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), sensitivity); } static void mem_view_init_headers (GtkTreeView *view) { - GtkCellRenderer *renderer; - gint i; - - g_return_if_fail (view != NULL); - - renderer = gtk_cell_renderer_text_new (); - gtk_tree_view_insert_column_with_attributes (view, - -1, - "Address", - renderer, - "text", - 0, /* column */ - NULL); - for (i = 0; i < 4; i++) { - gchar *label; - - label = g_strdup_printf ("%X", i * 4); - renderer = gtk_cell_renderer_text_new (); - gtk_tree_view_insert_column_with_attributes (view, - -1, - label, - renderer, - "text", - (i + 1), /* column */ - NULL); - g_free (label); - } - - for (i = 0; i < 5; i++) { - GtkTreeViewColumn *column = gtk_tree_view_get_column (view, i); - gtk_tree_view_column_set_expand (column, TRUE); - } + GtkCellRenderer *renderer; + gint i; + + g_return_if_fail (view != NULL); + + renderer = gtk_cell_renderer_text_new (); + gtk_tree_view_insert_column_with_attributes (view, + -1, + "Address", + renderer, + "text", + 0, /* column */ + NULL); + for (i = 0; i < 4; i++) { + gchar *label; + + label = g_strdup_printf ("%X", i * 4); + renderer = gtk_cell_renderer_text_new (); + gtk_tree_view_insert_column_with_attributes (view, + -1, + label, + renderer, + "text", + (i + 1), /* column */ + NULL); + g_free (label); + } + + for (i = 0; i < 5; i++) { + GtkTreeViewColumn *column = gtk_tree_view_get_column (view, i); + gtk_tree_view_column_set_expand (column, TRUE); + } } static void @@ -136,11 +136,11 @@ mem_view_add_as_hex (GtkListStore *store, gint column, guint32 value) { - gchar *hex_str; + gchar *hex_str; - hex_str = g_strdup_printf ("0x%08X", value); - gtk_list_store_set (store, iter, column, hex_str, -1); - g_free (hex_str); + hex_str = g_strdup_printf ("0x%08X", value); + gtk_list_store_set (store, iter, column, hex_str, -1); + g_free (hex_str); } static void @@ -150,194 +150,194 @@ mem_view_add_buffer (GtkListStore *store, guchar *buffer, gint len) { - guint32 *word; - gint i, step; - gint column = 0; + guint32 *word; + gint i, step; + gint column = 0; - step = sizeof (*word); + step = sizeof (*word); - for (i = 0; i < len; i += step) { - word = (guint *) &buffer[i]; + for (i = 0; i < len; i += step) { + word = (guint *) &buffer[i]; - if (column == 0) { - /* new row */ - gtk_list_store_append (store, iter); + if (column == 0) { + /* new row */ + gtk_list_store_append (store, iter); - /* add address */ - mem_view_add_as_hex (store, iter, column, (address + i)); - } - mem_view_add_as_hex (store, iter, (column + 1), *word); - column = (column + 1) % step; - } + /* add address */ + mem_view_add_as_hex (store, iter, column, (address + i)); + } + mem_view_add_as_hex (store, iter, (column + 1), *word); + column = (column + 1) % step; + } } static guint32 hexstr_to_guint32 (const gchar *str, GError **err) { - guint32 val; - gchar *end_ptr; + guint32 val; + gchar *end_ptr; - val = strtoul (str, &end_ptr, 16); - if ((errno == ERANGE && val == LONG_MAX) || (errno != 0 && val == 0)) { - g_set_error (err, - g_quark_from_string ("hextou32"), - 1, - "Invalid hexstring"); - return LONG_MAX; - } - if (end_ptr == str) { - g_set_error (err, - g_quark_from_string ("hextou32"), - 2, - "Invalid hexstring"); - return LONG_MAX; - } - return val; + val = strtoul (str, &end_ptr, 16); + if ((errno == ERANGE && val == LONG_MAX) || (errno != 0 && val == 0)) { + g_set_error (err, + g_quark_from_string ("hextou32"), + 1, + "Invalid hexstring"); + return LONG_MAX; + } + if (end_ptr == str) { + g_set_error (err, + g_quark_from_string ("hextou32"), + 2, + "Invalid hexstring"); + return LONG_MAX; + } + return val; } static void stlink_gui_update_mem_view (STlinkGUI *gui, struct mem_t *mem, GtkTreeView *view) { - GtkListStore *store; - GtkTreeIter iter; + GtkListStore *store; + GtkTreeIter iter; - store = GTK_LIST_STORE (gtk_tree_view_get_model (view)); + store = GTK_LIST_STORE (gtk_tree_view_get_model (view)); - mem_view_add_buffer (store, - &iter, - mem->base, - mem->memory, - mem->size); + mem_view_add_buffer (store, + &iter, + mem->base, + mem->memory, + mem->size); - gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); - gtk_progress_bar_set_fraction (gui->progress.bar, 0); - stlink_gui_set_sensitivity (gui, TRUE); + gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); + gtk_progress_bar_set_fraction (gui->progress.bar, 0); + stlink_gui_set_sensitivity (gui, TRUE); } static gboolean stlink_gui_update_devmem_view (STlinkGUI *gui) { - stlink_gui_update_mem_view (gui, &gui->flash_mem, gui->devmem_treeview); - return FALSE; + stlink_gui_update_mem_view (gui, &gui->flash_mem, gui->devmem_treeview); + return FALSE; } static void stlink_gui_populate_devmem_view (STlinkGUI *gui) { - guint off; - stm32_addr_t addr; - - g_return_if_fail (gui != NULL); - g_return_if_fail (gui->sl != NULL); - - addr = gui->sl->flash_base; - - if (gui->flash_mem.memory) { - g_free (gui->flash_mem.memory); - } - gui->flash_mem.memory = g_malloc (gui->sl->flash_size); - gui->flash_mem.size = gui->sl->flash_size; - gui->flash_mem.base = gui->sl->flash_base; - - for (off = 0; off < gui->sl->flash_size; off += MEM_READ_SIZE) { - guint n_read = MEM_READ_SIZE; - - if (off + MEM_READ_SIZE > gui->sl->flash_size) { - n_read = gui->sl->flash_size - off; - - /* align if needed */ - if (n_read & 3) { - n_read = (n_read + 4) & ~(3); - } - } - /* reads to sl->q_buf */ - stlink_read_mem32(gui->sl, addr + off, n_read); - if (gui->sl->q_len < 0) { - stlink_gui_set_info_error_message (gui, "Failed to read memory"); - g_free (gui->flash_mem.memory); - gui->flash_mem.memory = NULL; - return; - } - memcpy (gui->flash_mem.memory + off, gui->sl->q_buf, n_read); - gui->progress.fraction = (gdouble) (off + n_read) / gui->sl->flash_size; - } - g_idle_add ((GSourceFunc) stlink_gui_update_devmem_view, gui); + guint off; + stm32_addr_t addr; + + g_return_if_fail (gui != NULL); + g_return_if_fail (gui->sl != NULL); + + addr = gui->sl->flash_base; + + if (gui->flash_mem.memory) { + g_free (gui->flash_mem.memory); + } + gui->flash_mem.memory = g_malloc (gui->sl->flash_size); + gui->flash_mem.size = gui->sl->flash_size; + gui->flash_mem.base = gui->sl->flash_base; + + for (off = 0; off < gui->sl->flash_size; off += MEM_READ_SIZE) { + guint n_read = MEM_READ_SIZE; + + if (off + MEM_READ_SIZE > gui->sl->flash_size) { + n_read = gui->sl->flash_size - off; + + /* align if needed */ + if (n_read & 3) { + n_read = (n_read + 4) & ~(3); + } + } + /* reads to sl->q_buf */ + stlink_read_mem32(gui->sl, addr + off, n_read); + if (gui->sl->q_len < 0) { + stlink_gui_set_info_error_message (gui, "Failed to read memory"); + g_free (gui->flash_mem.memory); + gui->flash_mem.memory = NULL; + return; + } + memcpy (gui->flash_mem.memory + off, gui->sl->q_buf, n_read); + gui->progress.fraction = (gdouble) (off + n_read) / gui->sl->flash_size; + } + g_idle_add ((GSourceFunc) stlink_gui_update_devmem_view, gui); } static gboolean stlink_gui_update_filemem_view (STlinkGUI *gui) { - gchar *basename; + gchar *basename; - basename = g_path_get_basename (gui->filename); - gtk_notebook_set_tab_label_text (gui->notebook, - GTK_WIDGET (gtk_notebook_get_nth_page (gui->notebook, 1)), - basename); - g_free (basename); + basename = g_path_get_basename (gui->filename); + gtk_notebook_set_tab_label_text (gui->notebook, + GTK_WIDGET (gtk_notebook_get_nth_page (gui->notebook, 1)), + basename); + g_free (basename); - stlink_gui_update_mem_view (gui, &gui->file_mem, gui->filemem_treeview); + stlink_gui_update_mem_view (gui, &gui->file_mem, gui->filemem_treeview); - return FALSE; + return FALSE; } static gpointer stlink_gui_populate_filemem_view (STlinkGUI *gui) { - guchar buffer[MEM_READ_SIZE]; - GFile *file; - GFileInfo *file_info; - GInputStream *input_stream; - gint off; - GError *err = NULL; - - g_return_val_if_fail (gui != NULL, NULL); - g_return_val_if_fail (gui->filename != NULL, NULL); - - file = g_file_new_for_path (gui->filename); - input_stream = G_INPUT_STREAM (g_file_read (file, NULL, &err)); - if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); - goto out; - } - - file_info = g_file_input_stream_query_info (G_FILE_INPUT_STREAM (input_stream), - G_FILE_ATTRIBUTE_STANDARD_SIZE, NULL, &err); - if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); - goto out_input; - } - if (gui->file_mem.memory) { - g_free (gui->file_mem.memory); - } - gui->file_mem.size = g_file_info_get_size (file_info); - gui->file_mem.memory = g_malloc (gui->file_mem.size); - - for (off = 0; off < gui->file_mem.size; off += MEM_READ_SIZE) { - guint n_read = MEM_READ_SIZE; - - if (off + MEM_READ_SIZE > gui->file_mem.size) { - n_read = gui->file_mem.size - off; - } - - if (g_input_stream_read (G_INPUT_STREAM (input_stream), - &buffer, n_read, NULL, &err) == -1) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); - goto out_input; - } - memcpy (gui->file_mem.memory + off, buffer, n_read); - gui->progress.fraction = (gdouble) (off + n_read) / gui->file_mem.size; - } - g_idle_add ((GSourceFunc) stlink_gui_update_filemem_view, gui); - - out_input: - g_object_unref (input_stream); - out: - g_object_unref (file); - return NULL; + guchar buffer[MEM_READ_SIZE]; + GFile *file; + GFileInfo *file_info; + GInputStream *input_stream; + gint off; + GError *err = NULL; + + g_return_val_if_fail (gui != NULL, NULL); + g_return_val_if_fail (gui->filename != NULL, NULL); + + file = g_file_new_for_path (gui->filename); + input_stream = G_INPUT_STREAM (g_file_read (file, NULL, &err)); + if (err) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + goto out; + } + + file_info = g_file_input_stream_query_info (G_FILE_INPUT_STREAM (input_stream), + G_FILE_ATTRIBUTE_STANDARD_SIZE, NULL, &err); + if (err) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + goto out_input; + } + if (gui->file_mem.memory) { + g_free (gui->file_mem.memory); + } + gui->file_mem.size = g_file_info_get_size (file_info); + gui->file_mem.memory = g_malloc (gui->file_mem.size); + + for (off = 0; off < gui->file_mem.size; off += MEM_READ_SIZE) { + guint n_read = MEM_READ_SIZE; + + if (off + MEM_READ_SIZE > gui->file_mem.size) { + n_read = gui->file_mem.size - off; + } + + if (g_input_stream_read (G_INPUT_STREAM (input_stream), + &buffer, n_read, NULL, &err) == -1) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + goto out_input; + } + memcpy (gui->file_mem.memory + off, buffer, n_read); + gui->progress.fraction = (gdouble) (off + n_read) / gui->file_mem.size; + } + g_idle_add ((GSourceFunc) stlink_gui_update_filemem_view, gui); + +out_input: + g_object_unref (input_stream); +out: + g_object_unref (file); + return NULL; } static void mem_jmp (GtkTreeView *view, @@ -346,362 +346,362 @@ static void mem_jmp (GtkTreeView *view, gsize size, GError **err) { - GtkTreeModel *model; - guint32 jmp_addr; - GtkTreeIter iter; - - jmp_addr = hexstr_to_guint32 (gtk_entry_get_text (entry), err); - if (err && *err) { - return; - } - - if (jmp_addr < base_addr || jmp_addr > base_addr + size) { - g_set_error (err, - g_quark_from_string ("mem_jmp"), - 1, - "Invalid address"); - return; - } - - model = gtk_tree_view_get_model (view); - if (!model) { - return; - } - - if (gtk_tree_model_get_iter_first (model, &iter)) { - do { - guint32 addr; - GValue value = G_VALUE_INIT; - GError *err = NULL; - - gtk_tree_model_get_value (model, &iter, 0, &value); - if (G_VALUE_HOLDS_STRING (&value)) { - addr = hexstr_to_guint32 (g_value_get_string (&value), &err); - if (!err) { - if (addr == (jmp_addr & 0xFFFFFFF0)) { - GtkTreeSelection *selection; - GtkTreePath *path; - - selection = gtk_tree_view_get_selection (view); - path = gtk_tree_model_get_path (model, &iter); - - gtk_tree_selection_select_iter (selection, &iter); - gtk_tree_view_scroll_to_cell (view, - path, - NULL, - TRUE, - 0.0, - 0.0); - gtk_tree_path_free (path); - } - } - } - g_value_unset (&value); - } while (gtk_tree_model_iter_next (model, &iter)); - } + GtkTreeModel *model; + guint32 jmp_addr; + GtkTreeIter iter; + + jmp_addr = hexstr_to_guint32 (gtk_entry_get_text (entry), err); + if (err && *err) { + return; + } + + if (jmp_addr < base_addr || jmp_addr > base_addr + size) { + g_set_error (err, + g_quark_from_string ("mem_jmp"), + 1, + "Invalid address"); + return; + } + + model = gtk_tree_view_get_model (view); + if (!model) { + return; + } + + if (gtk_tree_model_get_iter_first (model, &iter)) { + do { + guint32 addr; + GValue value = G_VALUE_INIT; + GError *err = NULL; + + gtk_tree_model_get_value (model, &iter, 0, &value); + if (G_VALUE_HOLDS_STRING (&value)) { + addr = hexstr_to_guint32 (g_value_get_string (&value), &err); + if (!err) { + if (addr == (jmp_addr & 0xFFFFFFF0)) { + GtkTreeSelection *selection; + GtkTreePath *path; + + selection = gtk_tree_view_get_selection (view); + path = gtk_tree_model_get_path (model, &iter); + + gtk_tree_selection_select_iter (selection, &iter); + gtk_tree_view_scroll_to_cell (view, + path, + NULL, + TRUE, + 0.0, + 0.0); + gtk_tree_path_free (path); + } + } + } + g_value_unset (&value); + } while (gtk_tree_model_iter_next (model, &iter)); + } } static void devmem_jmp_cb (GtkWidget *widget, gpointer data) { - STlinkGUI *gui; - GError *err = NULL; + STlinkGUI *gui; + GError *err = NULL; - gui = STLINK_GUI (data); + gui = STLINK_GUI (data); - mem_jmp (gui->devmem_treeview, - gui->devmem_jmp_entry, - gui->sl->flash_base, - gui->sl->flash_size, - &err); + mem_jmp (gui->devmem_treeview, + gui->devmem_jmp_entry, + gui->sl->flash_base, + gui->sl->flash_size, + &err); - if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); - } + if (err) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + } } static void filemem_jmp_cb (GtkWidget *widget, gpointer data) { - STlinkGUI *gui; - GError *err = NULL; + STlinkGUI *gui; + GError *err = NULL; - gui = STLINK_GUI (data); + gui = STLINK_GUI (data); - g_return_if_fail (gui->filename != NULL); + g_return_if_fail (gui->filename != NULL); - mem_jmp (gui->filemem_treeview, - gui->filemem_jmp_entry, - 0, - gui->file_mem.size, - &err); + mem_jmp (gui->filemem_treeview, + gui->filemem_jmp_entry, + 0, + gui->file_mem.size, + &err); - if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); - } + if (err) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + } } static gchar * dev_format_chip_id (guint32 chip_id) { - gint i; + gint i; - for (i = 0; i < sizeof (devices) / sizeof (devices[0]); i++) { - if (chip_id == devices[i].chip_id) { - return g_strdup (devices[i].description); - } - } - return g_strdup_printf ("0x%x", chip_id); + for (i = 0; i < sizeof (devices) / sizeof (devices[0]); i++) { + if (chip_id == devices[i].chip_id) { + return g_strdup (devices[i].description); + } + } + return g_strdup_printf ("0x%x", chip_id); } static gchar * dev_format_mem_size (gsize flash_size) { - return g_strdup_printf ("%u kB", flash_size / 1024); + return g_strdup_printf ("%u kB", flash_size / 1024); } static void stlink_gui_set_connected (STlinkGUI *gui) { - gchar *tmp_str; - GtkListStore *store; - GtkTreeIter iter; + gchar *tmp_str; + GtkListStore *store; + GtkTreeIter iter; - gtk_statusbar_push (gui->statusbar, - gtk_statusbar_get_context_id (gui->statusbar, "conn"), - "Connected"); + gtk_statusbar_push (gui->statusbar, + gtk_statusbar_get_context_id (gui->statusbar, "conn"), + "Connected"); - gtk_widget_set_sensitive (GTK_WIDGET (gui->device_frame), TRUE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->devmem_box), TRUE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), FALSE); + gtk_widget_set_sensitive (GTK_WIDGET (gui->device_frame), TRUE); + gtk_widget_set_sensitive (GTK_WIDGET (gui->devmem_box), TRUE); + gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), FALSE); - if (gui->filename) { - gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), TRUE); - } + if (gui->filename) { + gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), TRUE); + } - tmp_str = dev_format_chip_id (gui->sl->chip_id); - gtk_label_set_text (gui->chip_id_label, tmp_str); - g_free (tmp_str); + tmp_str = dev_format_chip_id (gui->sl->chip_id); + gtk_label_set_text (gui->chip_id_label, tmp_str); + g_free (tmp_str); - tmp_str = g_strdup_printf ("0x%x", gui->sl->core_id); - gtk_label_set_text (gui->core_id_label, tmp_str); - g_free (tmp_str); + tmp_str = g_strdup_printf ("0x%x", gui->sl->core_id); + gtk_label_set_text (gui->core_id_label, tmp_str); + g_free (tmp_str); - tmp_str = dev_format_mem_size (gui->sl->flash_size); - gtk_label_set_text (gui->flash_size_label, tmp_str); - g_free (tmp_str); + tmp_str = dev_format_mem_size (gui->sl->flash_size); + gtk_label_set_text (gui->flash_size_label, tmp_str); + g_free (tmp_str); - tmp_str = dev_format_mem_size (gui->sl->sram_size); - gtk_label_set_text (gui->ram_size_label, tmp_str); - g_free (tmp_str); + tmp_str = dev_format_mem_size (gui->sl->sram_size); + gtk_label_set_text (gui->ram_size_label, tmp_str); + g_free (tmp_str); - tmp_str = g_strdup_printf ("0x%08X", gui->sl->flash_base); - gtk_entry_set_text (gui->devmem_jmp_entry, tmp_str); - gtk_editable_set_editable (GTK_EDITABLE (gui->devmem_jmp_entry), TRUE); - g_free (tmp_str); + tmp_str = g_strdup_printf ("0x%08X", gui->sl->flash_base); + gtk_entry_set_text (gui->devmem_jmp_entry, tmp_str); + gtk_editable_set_editable (GTK_EDITABLE (gui->devmem_jmp_entry), TRUE); + g_free (tmp_str); - store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->devmem_treeview)); - if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) { - gtk_list_store_clear (store); - } + store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->devmem_treeview)); + if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) { + gtk_list_store_clear (store); + } - stlink_gui_set_sensitivity (gui, FALSE); - gtk_notebook_set_current_page (gui->notebook, PAGE_DEVMEM); - gtk_widget_show (GTK_WIDGET (gui->progress.bar)); - gtk_progress_bar_set_text (gui->progress.bar, "Reading memory"); + stlink_gui_set_sensitivity (gui, FALSE); + gtk_notebook_set_current_page (gui->notebook, PAGE_DEVMEM); + gtk_widget_show (GTK_WIDGET (gui->progress.bar)); + gtk_progress_bar_set_text (gui->progress.bar, "Reading memory"); - g_thread_new ("devmem", (GThreadFunc) stlink_gui_populate_devmem_view, gui); + g_thread_new ("devmem", (GThreadFunc) stlink_gui_populate_devmem_view, gui); } static void connect_button_cb (GtkWidget *widget, gpointer data) { - STlinkGUI *gui; - gint i; + STlinkGUI *gui; + gint i; - gui = STLINK_GUI (data); + gui = STLINK_GUI (data); - if (gui->sl != NULL) - return; + if (gui->sl != NULL) + return; - /* try version 1 then version 2 */ - gui->sl = stlink_v1_open(0, 1); - if (gui->sl == NULL) { - gui->sl = stlink_open_usb(0, 1); - } - if (gui->sl == NULL) { - stlink_gui_set_info_error_message (gui, "Failed to connect to STLink."); return; - } + /* try version 1 then version 2 */ + gui->sl = stlink_v1_open(0, 1); + if (gui->sl == NULL) { + gui->sl = stlink_open_usb(0, 1); + } + if (gui->sl == NULL) { + stlink_gui_set_info_error_message (gui, "Failed to connect to STLink."); return; + } - /* code below taken from flash/main.c, refactoring might be in order */ - if (stlink_current_mode(gui->sl) == STLINK_DEV_DFU_MODE) - stlink_exit_dfu_mode(gui->sl); + /* code below taken from flash/main.c, refactoring might be in order */ + if (stlink_current_mode(gui->sl) == STLINK_DEV_DFU_MODE) + stlink_exit_dfu_mode(gui->sl); - if (stlink_current_mode(gui->sl) != STLINK_DEV_DEBUG_MODE) - stlink_enter_swd_mode(gui->sl); + if (stlink_current_mode(gui->sl) != STLINK_DEV_DEBUG_MODE) + stlink_enter_swd_mode(gui->sl); - /* Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 */ - if (gui->sl->chip_id == STM32_CHIPID_F4) { - memset(gui->sl->q_buf, 0, 4); - for (i = 0; i < 8; i++) { - stlink_write_mem32(gui->sl, 0x40026000 + 0x10 + 0x18 * i, 4); - stlink_write_mem32(gui->sl, 0x40026400 + 0x10 + 0x18 * i, 4); - stlink_write_mem32(gui->sl, 0x40026000 + 0x24 + 0x18 * i, 4); - stlink_write_mem32(gui->sl, 0x40026400 + 0x24 + 0x18 * i, 4); - } - } - stlink_gui_set_connected (gui); + /* Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 */ + if (gui->sl->chip_id == STM32_CHIPID_F4) { + memset(gui->sl->q_buf, 0, 4); + for (i = 0; i < 8; i++) { + stlink_write_mem32(gui->sl, 0x40026000 + 0x10 + 0x18 * i, 4); + stlink_write_mem32(gui->sl, 0x40026400 + 0x10 + 0x18 * i, 4); + stlink_write_mem32(gui->sl, 0x40026000 + 0x24 + 0x18 * i, 4); + stlink_write_mem32(gui->sl, 0x40026400 + 0x24 + 0x18 * i, 4); + } + } + stlink_gui_set_connected (gui); } static void stlink_gui_set_disconnected (STlinkGUI *gui) { - gtk_statusbar_push (gui->statusbar, - gtk_statusbar_get_context_id (gui->statusbar, "conn"), - "Disconnected"); + gtk_statusbar_push (gui->statusbar, + gtk_statusbar_get_context_id (gui->statusbar, "conn"), + "Disconnected"); - gtk_widget_set_sensitive (GTK_WIDGET (gui->device_frame), FALSE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), FALSE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->disconnect_button), FALSE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), TRUE); + gtk_widget_set_sensitive (GTK_WIDGET (gui->device_frame), FALSE); + gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), FALSE); + gtk_widget_set_sensitive (GTK_WIDGET (gui->disconnect_button), FALSE); + gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), TRUE); } static void disconnect_button_cb (GtkWidget *widget, gpointer data) { - STlinkGUI *gui; + STlinkGUI *gui; - gui = STLINK_GUI (data); + gui = STLINK_GUI (data); - if (gui->sl != NULL) { - stlink_exit_debug_mode(gui->sl); - stlink_close(gui->sl); - gui->sl = NULL; - } - stlink_gui_set_disconnected (gui); + if (gui->sl != NULL) { + stlink_exit_debug_mode(gui->sl); + stlink_close(gui->sl); + gui->sl = NULL; + } + stlink_gui_set_disconnected (gui); } static void stlink_gui_open_file (STlinkGUI *gui) { - GtkWidget *dialog; - GtkListStore *store; - GtkTreeIter iter; + GtkWidget *dialog; + GtkListStore *store; + GtkTreeIter iter; - dialog = gtk_file_chooser_dialog_new ("Open file", - gui->window, - GTK_FILE_CHOOSER_ACTION_OPEN, - GTK_STOCK_CANCEL, GTK_RESPONSE_CANCEL, - GTK_STOCK_OPEN, GTK_RESPONSE_ACCEPT, - NULL); + dialog = gtk_file_chooser_dialog_new ("Open file", + gui->window, + GTK_FILE_CHOOSER_ACTION_OPEN, + GTK_STOCK_CANCEL, GTK_RESPONSE_CANCEL, + GTK_STOCK_OPEN, GTK_RESPONSE_ACCEPT, + NULL); - if (gtk_dialog_run (GTK_DIALOG (dialog)) == GTK_RESPONSE_ACCEPT) { - gui->filename = - gtk_file_chooser_get_filename (GTK_FILE_CHOOSER (dialog)); + if (gtk_dialog_run (GTK_DIALOG (dialog)) == GTK_RESPONSE_ACCEPT) { + gui->filename = + gtk_file_chooser_get_filename (GTK_FILE_CHOOSER (dialog)); - store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->filemem_treeview)); - if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) { - gtk_list_store_clear (store); - } + store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->filemem_treeview)); + if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) { + gtk_list_store_clear (store); + } - stlink_gui_set_sensitivity (gui, FALSE); - gtk_notebook_set_current_page (gui->notebook, PAGE_FILEMEM); - gtk_widget_show (GTK_WIDGET (gui->progress.bar)); - gtk_progress_bar_set_text (gui->progress.bar, "Reading file"); - g_thread_new ("file", (GThreadFunc) stlink_gui_populate_filemem_view, gui); - } - gtk_widget_destroy (dialog); + stlink_gui_set_sensitivity (gui, FALSE); + gtk_notebook_set_current_page (gui->notebook, PAGE_FILEMEM); + gtk_widget_show (GTK_WIDGET (gui->progress.bar)); + gtk_progress_bar_set_text (gui->progress.bar, "Reading file"); + g_thread_new ("file", (GThreadFunc) stlink_gui_populate_filemem_view, gui); + } + gtk_widget_destroy (dialog); } static void open_button_cb (GtkWidget *widget, gpointer data) { - STlinkGUI *gui; + STlinkGUI *gui; - gui = STLINK_GUI (data); + gui = STLINK_GUI (data); - stlink_gui_open_file (gui); + stlink_gui_open_file (gui); } static gboolean stlink_gui_write_flash_update (STlinkGUI *gui) { - stlink_gui_set_sensitivity (gui, TRUE); - gui->progress.activity_mode = FALSE; - gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); + stlink_gui_set_sensitivity (gui, TRUE); + gui->progress.activity_mode = FALSE; + gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); - return FALSE; + return FALSE; } static void stlink_gui_write_flash (STlinkGUI *gui) { - g_return_if_fail (gui->sl != NULL); - g_return_if_fail (gui->filename != NULL); + g_return_if_fail (gui->sl != NULL); + g_return_if_fail (gui->filename != NULL); - if (stlink_fwrite_flash(gui->sl, gui->filename, gui->sl->flash_base) < 0) { - stlink_gui_set_info_error_message (gui, "Failed to write to flash"); - } + if (stlink_fwrite_flash(gui->sl, gui->filename, gui->sl->flash_base) < 0) { + stlink_gui_set_info_error_message (gui, "Failed to write to flash"); + } - g_idle_add ((GSourceFunc) stlink_gui_write_flash_update, gui); + g_idle_add ((GSourceFunc) stlink_gui_write_flash_update, gui); } static void flash_button_cb (GtkWidget *widget, gpointer data) { - STlinkGUI *gui; - gchar *tmp_str; - guint32 address; - gint result; - GError *err = NULL; - - gui = STLINK_GUI (data); - g_return_if_fail (gui->sl != NULL); - - if (!g_strcmp0 (gtk_entry_get_text (gui->flash_dialog_entry), "")) { - tmp_str = g_strdup_printf ("0x%08X", gui->sl->flash_base); - gtk_entry_set_text (gui->flash_dialog_entry, tmp_str); - g_free (tmp_str); - } - - result = gtk_dialog_run (gui->flash_dialog); - if (result == GTK_RESPONSE_OK) { - address = hexstr_to_guint32 (gtk_entry_get_text (gui->flash_dialog_entry), - &err); - if (err) { - stlink_gui_set_info_error_message (gui, err->message); - } else { - if (address > gui->sl->flash_base + gui->sl->flash_size || - address < gui->sl->flash_base) { - stlink_gui_set_info_error_message (gui, "Invalid address"); - } - else if (address + gui->file_mem.size > - gui->sl->flash_base + gui->sl->flash_size) { - stlink_gui_set_info_error_message (gui, "Binary overwrites flash"); - } else { - stlink_gui_set_sensitivity (gui, FALSE); - gtk_progress_bar_set_text (gui->progress.bar, - "Writing to flash"); - gui->progress.activity_mode = TRUE; - gtk_widget_show (GTK_WIDGET (gui->progress.bar)); - g_thread_new ("flash", - (GThreadFunc) stlink_gui_write_flash, gui); - } - } - } + STlinkGUI *gui; + gchar *tmp_str; + guint32 address; + gint result; + GError *err = NULL; + + gui = STLINK_GUI (data); + g_return_if_fail (gui->sl != NULL); + + if (!g_strcmp0 (gtk_entry_get_text (gui->flash_dialog_entry), "")) { + tmp_str = g_strdup_printf ("0x%08X", gui->sl->flash_base); + gtk_entry_set_text (gui->flash_dialog_entry, tmp_str); + g_free (tmp_str); + } + + result = gtk_dialog_run (gui->flash_dialog); + if (result == GTK_RESPONSE_OK) { + address = hexstr_to_guint32 (gtk_entry_get_text (gui->flash_dialog_entry), + &err); + if (err) { + stlink_gui_set_info_error_message (gui, err->message); + } else { + if (address > gui->sl->flash_base + gui->sl->flash_size || + address < gui->sl->flash_base) { + stlink_gui_set_info_error_message (gui, "Invalid address"); + } + else if (address + gui->file_mem.size > + gui->sl->flash_base + gui->sl->flash_size) { + stlink_gui_set_info_error_message (gui, "Binary overwrites flash"); + } else { + stlink_gui_set_sensitivity (gui, FALSE); + gtk_progress_bar_set_text (gui->progress.bar, + "Writing to flash"); + gui->progress.activity_mode = TRUE; + gtk_widget_show (GTK_WIDGET (gui->progress.bar)); + g_thread_new ("flash", + (GThreadFunc) stlink_gui_write_flash, gui); + } + } + } } static gboolean progress_pulse_timeout (STlinkGUI *gui) { - if (gui->progress.activity_mode) { - gtk_progress_bar_pulse (gui->progress.bar); - } else { - gtk_progress_bar_set_fraction (gui->progress.bar, gui->progress.fraction); - } - return TRUE; + if (gui->progress.activity_mode) { + gtk_progress_bar_pulse (gui->progress.bar); + } else { + gtk_progress_bar_set_fraction (gui->progress.bar, gui->progress.fraction); + } + return TRUE; } static void @@ -710,15 +710,15 @@ notebook_switch_page_cb (GtkNotebook *notebook, guint page_num, gpointer data) { - STlinkGUI *gui; + STlinkGUI *gui; - gui = STLINK_GUI (data); + gui = STLINK_GUI (data); - if (page_num == 1) { - if (gui->filename == NULL) { - stlink_gui_open_file (gui); - } - } + if (page_num == 1) { + if (gui->filename == NULL) { + stlink_gui_open_file (gui); + } + } } static void @@ -731,225 +731,225 @@ dnd_received_cb (GtkWidget *widget, guint time, gpointer data) { - GFile *file_uri; - gchar **file_list; - const guchar *file_data; - STlinkGUI *gui = STLINK_GUI (data); - GtkListStore *store; - GtkTreeIter iter; + GFile *file_uri; + gchar **file_list; + const guchar *file_data; + STlinkGUI *gui = STLINK_GUI (data); + GtkListStore *store; + GtkTreeIter iter; - if (selection_data != NULL && - gtk_selection_data_get_length (selection_data) > 0) { - switch (target_type) { - case TARGET_FILENAME: + if (selection_data != NULL && + gtk_selection_data_get_length (selection_data) > 0) { + switch (target_type) { + case TARGET_FILENAME: - if (gui->filename) { - g_free (gui->filename); - } + if (gui->filename) { + g_free (gui->filename); + } - file_data = gtk_selection_data_get_data (selection_data); - file_list = g_strsplit ((gchar *)file_data, "\r\n", 0); + file_data = gtk_selection_data_get_data (selection_data); + file_list = g_strsplit ((gchar *)file_data, "\r\n", 0); - file_uri = g_file_new_for_uri (file_list[0]); - gui->filename = g_file_get_path (file_uri); + file_uri = g_file_new_for_uri (file_list[0]); + gui->filename = g_file_get_path (file_uri); - g_strfreev (file_list); - g_object_unref (file_uri); + g_strfreev (file_list); + g_object_unref (file_uri); - store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->devmem_treeview)); - if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) { - gtk_list_store_clear (store); - } + store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->devmem_treeview)); + if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) { + gtk_list_store_clear (store); + } - stlink_gui_set_sensitivity (gui, FALSE); - gtk_notebook_set_current_page (gui->notebook, PAGE_FILEMEM); - gtk_widget_show (GTK_WIDGET (gui->progress.bar)); - gtk_progress_bar_set_text (gui->progress.bar, "Reading file"); - g_thread_new ("file", (GThreadFunc) stlink_gui_populate_filemem_view, gui); - break; - } - } - gtk_drag_finish (context, - TRUE, - gdk_drag_context_get_suggested_action (context) == GDK_ACTION_MOVE, - time); + stlink_gui_set_sensitivity (gui, FALSE); + gtk_notebook_set_current_page (gui->notebook, PAGE_FILEMEM); + gtk_widget_show (GTK_WIDGET (gui->progress.bar)); + gtk_progress_bar_set_text (gui->progress.bar, "Reading file"); + g_thread_new ("file", (GThreadFunc) stlink_gui_populate_filemem_view, gui); + break; + } + } + gtk_drag_finish (context, + TRUE, + gdk_drag_context_get_suggested_action (context) == GDK_ACTION_MOVE, + time); } void stlink_gui_init_dnd (STlinkGUI *gui) { - GtkTargetEntry target_list[] = { - { "text/uri-list", 0, TARGET_FILENAME }, - }; + GtkTargetEntry target_list[] = { + { "text/uri-list", 0, TARGET_FILENAME }, + }; - gtk_drag_dest_set (GTK_WIDGET (gui->window), - GTK_DEST_DEFAULT_ALL, - target_list, - G_N_ELEMENTS (target_list), - GDK_ACTION_COPY); + gtk_drag_dest_set (GTK_WIDGET (gui->window), + GTK_DEST_DEFAULT_ALL, + target_list, + G_N_ELEMENTS (target_list), + GDK_ACTION_COPY); - g_signal_connect (gui->window, "drag-data-received", - G_CALLBACK (dnd_received_cb), gui); + g_signal_connect (gui->window, "drag-data-received", + G_CALLBACK (dnd_received_cb), gui); } static void stlink_gui_build_ui (STlinkGUI *gui) { - GtkBuilder *builder; - GtkListStore *devmem_store; - GtkListStore *filemem_store; - gchar *ui_file = STLINK_UI_DIR "/stlink-gui.ui"; - - if (!g_file_test (ui_file, G_FILE_TEST_EXISTS)) { - ui_file = "stlink-gui.ui"; - } - builder = gtk_builder_new (); - if (!gtk_builder_add_from_file (builder, ui_file, NULL)) { - g_printerr ("Failed to load UI file: %s\n", ui_file); - exit (1); - } - - gui->window = GTK_WINDOW (gtk_builder_get_object (builder, "window")); - g_signal_connect (G_OBJECT (gui->window), "destroy", - G_CALLBACK (gtk_main_quit), NULL); - - /* set up toolutton clicked callbacks */ - gui->open_button = - GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "open_button")); - g_signal_connect (G_OBJECT (gui->open_button), "clicked", - G_CALLBACK (open_button_cb), gui); - - gui->connect_button = - GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "connect_button")); - g_signal_connect (G_OBJECT (gui->connect_button), "clicked", - G_CALLBACK (connect_button_cb), gui); - - gui->disconnect_button = - GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "disconnect_button")); - g_signal_connect (G_OBJECT (gui->disconnect_button), "clicked", - G_CALLBACK (disconnect_button_cb), gui); - - gui->flash_button = - GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "flash_button")); - g_signal_connect (G_OBJECT (gui->flash_button), "clicked", - G_CALLBACK (flash_button_cb), gui); - - gui->devmem_treeview = - GTK_TREE_VIEW (gtk_builder_get_object (builder, "devmem_treeview")); - gtk_tree_view_set_rules_hint (gui->devmem_treeview, TRUE); - mem_view_init_headers (gui->devmem_treeview); - devmem_store = gtk_list_store_new (5, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING); - gtk_tree_view_set_model (gui->devmem_treeview, GTK_TREE_MODEL (devmem_store)); - g_object_unref (devmem_store); - - gui->filemem_treeview = - GTK_TREE_VIEW (gtk_builder_get_object (builder, "filemem_treeview")); - gtk_tree_view_set_rules_hint (gui->filemem_treeview, TRUE); - mem_view_init_headers (gui->filemem_treeview); - filemem_store = gtk_list_store_new (5, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING); - gtk_tree_view_set_model (gui->filemem_treeview, GTK_TREE_MODEL (filemem_store)); - g_object_unref (filemem_store); - - gui->core_id_label = - GTK_LABEL (gtk_builder_get_object (builder, "core_id_value")); - - gui->chip_id_label = - GTK_LABEL (gtk_builder_get_object (builder, "chip_id_value")); - - gui->flash_size_label = - GTK_LABEL (gtk_builder_get_object (builder, "flash_size_value")); - - gui->ram_size_label = - GTK_LABEL (gtk_builder_get_object (builder, "ram_size_value")); - - gui->device_frame = - GTK_FRAME (gtk_builder_get_object (builder, "device_frame")); - - gui->notebook = - GTK_NOTEBOOK (gtk_builder_get_object (builder, "mem_notebook")); - g_signal_connect (gui->notebook, "switch-page", - G_CALLBACK (notebook_switch_page_cb), gui); - - gui->devmem_box = - GTK_BOX (gtk_builder_get_object (builder, "devmem_box")); - - gui->filemem_box = - GTK_BOX (gtk_builder_get_object (builder, "filemem_box")); - - gui->devmem_jmp_entry = - GTK_ENTRY (gtk_builder_get_object (builder, "devmem_jmp_entry")); - g_signal_connect (gui->devmem_jmp_entry, "activate", - G_CALLBACK (devmem_jmp_cb), gui); - - gui->filemem_jmp_entry = - GTK_ENTRY (gtk_builder_get_object (builder, "filemem_jmp_entry")); - g_signal_connect (gui->filemem_jmp_entry, "activate", - G_CALLBACK (filemem_jmp_cb), gui); - gtk_editable_set_editable (GTK_EDITABLE (gui->filemem_jmp_entry), TRUE); - - gui->progress.bar = - GTK_PROGRESS_BAR (gtk_builder_get_object (builder, "progressbar")); - gtk_progress_bar_set_show_text (gui->progress.bar, TRUE); - gui->progress.timer = g_timeout_add (100, - (GSourceFunc) progress_pulse_timeout, - gui); - - gui->statusbar = - GTK_STATUSBAR (gtk_builder_get_object (builder, "statusbar")); - - gui->infobar = - GTK_INFO_BAR (gtk_builder_get_object (builder, "infobar")); - gtk_info_bar_add_button (gui->infobar, GTK_STOCK_OK, GTK_RESPONSE_OK); - gui->infolabel = GTK_LABEL (gtk_label_new ("")); - gtk_container_add (GTK_CONTAINER (gtk_info_bar_get_content_area (gui->infobar)), - GTK_WIDGET (gui->infolabel)); - g_signal_connect (gui->infobar, "response", G_CALLBACK (gtk_widget_hide), NULL); - - /* flash dialog */ - gui->flash_dialog = - GTK_DIALOG (gtk_builder_get_object (builder, "flash_dialog")); - g_signal_connect_swapped (gui->flash_dialog, "response", - G_CALLBACK (gtk_widget_hide), gui->flash_dialog); - - gui->flash_dialog_ok = - GTK_BUTTON (gtk_builder_get_object (builder, "flash_dialog_ok_button")); - - gui->flash_dialog_cancel = - GTK_BUTTON (gtk_builder_get_object (builder, "flash_dialog_cancel_button")); - - gui->flash_dialog_entry = - GTK_ENTRY (gtk_builder_get_object (builder, "flash_dialog_entry")); - - /* make it so */ - gtk_widget_show_all (GTK_WIDGET (gui->window)); - gtk_widget_hide (GTK_WIDGET (gui->infobar)); - gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); - - stlink_gui_set_disconnected (gui); + GtkBuilder *builder; + GtkListStore *devmem_store; + GtkListStore *filemem_store; + gchar *ui_file = STLINK_UI_DIR "/stlink-gui.ui"; + + if (!g_file_test (ui_file, G_FILE_TEST_EXISTS)) { + ui_file = "stlink-gui.ui"; + } + builder = gtk_builder_new (); + if (!gtk_builder_add_from_file (builder, ui_file, NULL)) { + g_printerr ("Failed to load UI file: %s\n", ui_file); + exit (1); + } + + gui->window = GTK_WINDOW (gtk_builder_get_object (builder, "window")); + g_signal_connect (G_OBJECT (gui->window), "destroy", + G_CALLBACK (gtk_main_quit), NULL); + + /* set up toolutton clicked callbacks */ + gui->open_button = + GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "open_button")); + g_signal_connect (G_OBJECT (gui->open_button), "clicked", + G_CALLBACK (open_button_cb), gui); + + gui->connect_button = + GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "connect_button")); + g_signal_connect (G_OBJECT (gui->connect_button), "clicked", + G_CALLBACK (connect_button_cb), gui); + + gui->disconnect_button = + GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "disconnect_button")); + g_signal_connect (G_OBJECT (gui->disconnect_button), "clicked", + G_CALLBACK (disconnect_button_cb), gui); + + gui->flash_button = + GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "flash_button")); + g_signal_connect (G_OBJECT (gui->flash_button), "clicked", + G_CALLBACK (flash_button_cb), gui); + + gui->devmem_treeview = + GTK_TREE_VIEW (gtk_builder_get_object (builder, "devmem_treeview")); + gtk_tree_view_set_rules_hint (gui->devmem_treeview, TRUE); + mem_view_init_headers (gui->devmem_treeview); + devmem_store = gtk_list_store_new (5, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING); + gtk_tree_view_set_model (gui->devmem_treeview, GTK_TREE_MODEL (devmem_store)); + g_object_unref (devmem_store); + + gui->filemem_treeview = + GTK_TREE_VIEW (gtk_builder_get_object (builder, "filemem_treeview")); + gtk_tree_view_set_rules_hint (gui->filemem_treeview, TRUE); + mem_view_init_headers (gui->filemem_treeview); + filemem_store = gtk_list_store_new (5, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING); + gtk_tree_view_set_model (gui->filemem_treeview, GTK_TREE_MODEL (filemem_store)); + g_object_unref (filemem_store); + + gui->core_id_label = + GTK_LABEL (gtk_builder_get_object (builder, "core_id_value")); + + gui->chip_id_label = + GTK_LABEL (gtk_builder_get_object (builder, "chip_id_value")); + + gui->flash_size_label = + GTK_LABEL (gtk_builder_get_object (builder, "flash_size_value")); + + gui->ram_size_label = + GTK_LABEL (gtk_builder_get_object (builder, "ram_size_value")); + + gui->device_frame = + GTK_FRAME (gtk_builder_get_object (builder, "device_frame")); + + gui->notebook = + GTK_NOTEBOOK (gtk_builder_get_object (builder, "mem_notebook")); + g_signal_connect (gui->notebook, "switch-page", + G_CALLBACK (notebook_switch_page_cb), gui); + + gui->devmem_box = + GTK_BOX (gtk_builder_get_object (builder, "devmem_box")); + + gui->filemem_box = + GTK_BOX (gtk_builder_get_object (builder, "filemem_box")); + + gui->devmem_jmp_entry = + GTK_ENTRY (gtk_builder_get_object (builder, "devmem_jmp_entry")); + g_signal_connect (gui->devmem_jmp_entry, "activate", + G_CALLBACK (devmem_jmp_cb), gui); + + gui->filemem_jmp_entry = + GTK_ENTRY (gtk_builder_get_object (builder, "filemem_jmp_entry")); + g_signal_connect (gui->filemem_jmp_entry, "activate", + G_CALLBACK (filemem_jmp_cb), gui); + gtk_editable_set_editable (GTK_EDITABLE (gui->filemem_jmp_entry), TRUE); + + gui->progress.bar = + GTK_PROGRESS_BAR (gtk_builder_get_object (builder, "progressbar")); + gtk_progress_bar_set_show_text (gui->progress.bar, TRUE); + gui->progress.timer = g_timeout_add (100, + (GSourceFunc) progress_pulse_timeout, + gui); + + gui->statusbar = + GTK_STATUSBAR (gtk_builder_get_object (builder, "statusbar")); + + gui->infobar = + GTK_INFO_BAR (gtk_builder_get_object (builder, "infobar")); + gtk_info_bar_add_button (gui->infobar, GTK_STOCK_OK, GTK_RESPONSE_OK); + gui->infolabel = GTK_LABEL (gtk_label_new ("")); + gtk_container_add (GTK_CONTAINER (gtk_info_bar_get_content_area (gui->infobar)), + GTK_WIDGET (gui->infolabel)); + g_signal_connect (gui->infobar, "response", G_CALLBACK (gtk_widget_hide), NULL); + + /* flash dialog */ + gui->flash_dialog = + GTK_DIALOG (gtk_builder_get_object (builder, "flash_dialog")); + g_signal_connect_swapped (gui->flash_dialog, "response", + G_CALLBACK (gtk_widget_hide), gui->flash_dialog); + + gui->flash_dialog_ok = + GTK_BUTTON (gtk_builder_get_object (builder, "flash_dialog_ok_button")); + + gui->flash_dialog_cancel = + GTK_BUTTON (gtk_builder_get_object (builder, "flash_dialog_cancel_button")); + + gui->flash_dialog_entry = + GTK_ENTRY (gtk_builder_get_object (builder, "flash_dialog_entry")); + + /* make it so */ + gtk_widget_show_all (GTK_WIDGET (gui->window)); + gtk_widget_hide (GTK_WIDGET (gui->infobar)); + gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); + + stlink_gui_set_disconnected (gui); } int main (int argc, char **argv) { - STlinkGUI *gui; + STlinkGUI *gui; - gtk_init (&argc, &argv); + gtk_init (&argc, &argv); - gui = g_object_new (STLINK_TYPE_GUI, NULL); - stlink_gui_build_ui (gui); - stlink_gui_init_dnd (gui); + gui = g_object_new (STLINK_TYPE_GUI, NULL); + stlink_gui_build_ui (gui); + stlink_gui_init_dnd (gui); - gtk_main (); + gtk_main (); - return 0; + return 0; } diff --git a/gui/stlink-gui.h b/gui/stlink-gui.h index a91c869ac..0c90648a4 100644 --- a/gui/stlink-gui.h +++ b/gui/stlink-gui.h @@ -17,75 +17,75 @@ typedef struct _STlinkGUIClass STlinkGUIClass; typedef struct _STlinkGUIPrivate STlinkGUIPrivate; enum stlink_gui_pages_t { - PAGE_DEVMEM, - PAGE_FILEMEM + PAGE_DEVMEM, + PAGE_FILEMEM }; enum stlink_gui_dnd_targets_t { - TARGET_FILENAME, - TARGET_ROOTWIN + TARGET_FILENAME, + TARGET_ROOTWIN }; struct progress_t { - GtkProgressBar *bar; - guint timer; - gboolean activity_mode; - gdouble fraction; + GtkProgressBar *bar; + guint timer; + gboolean activity_mode; + gdouble fraction; }; struct mem_t { - guchar *memory; - gsize size; - guint32 base; + guchar *memory; + gsize size; + guint32 base; }; struct _STlinkGUI { - GObject parent_instance; - - /*< private >*/ - GtkWindow *window; - GtkTreeView *devmem_treeview; - GtkTreeView *filemem_treeview; - GtkSpinner *spinner; - GtkStatusbar *statusbar; - GtkInfoBar *infobar; - GtkLabel *infolabel; - GtkNotebook *notebook; - GtkFrame *device_frame; - GtkLabel *chip_id_label; - GtkLabel *core_id_label; - GtkLabel *flash_size_label; - GtkLabel *ram_size_label; - GtkBox *devmem_box; - GtkEntry *devmem_jmp_entry; - GtkBox *filemem_box; - GtkEntry *filemem_jmp_entry; - GtkToolButton *connect_button; - GtkToolButton *disconnect_button; - GtkToolButton *flash_button; - GtkToolButton *open_button; - - /* flash dialog */ - GtkDialog *flash_dialog; - GtkButton *flash_dialog_ok; - GtkButton *flash_dialog_cancel; - GtkEntry *flash_dialog_entry; - - struct progress_t progress; - struct mem_t flash_mem; - struct mem_t file_mem; - - gchar *error_message; - gchar *filename; - stlink_t *sl; + GObject parent_instance; + + /*< private >*/ + GtkWindow *window; + GtkTreeView *devmem_treeview; + GtkTreeView *filemem_treeview; + GtkSpinner *spinner; + GtkStatusbar *statusbar; + GtkInfoBar *infobar; + GtkLabel *infolabel; + GtkNotebook *notebook; + GtkFrame *device_frame; + GtkLabel *chip_id_label; + GtkLabel *core_id_label; + GtkLabel *flash_size_label; + GtkLabel *ram_size_label; + GtkBox *devmem_box; + GtkEntry *devmem_jmp_entry; + GtkBox *filemem_box; + GtkEntry *filemem_jmp_entry; + GtkToolButton *connect_button; + GtkToolButton *disconnect_button; + GtkToolButton *flash_button; + GtkToolButton *open_button; + + /* flash dialog */ + GtkDialog *flash_dialog; + GtkButton *flash_dialog_ok; + GtkButton *flash_dialog_cancel; + GtkEntry *flash_dialog_entry; + + struct progress_t progress; + struct mem_t flash_mem; + struct mem_t file_mem; + + gchar *error_message; + gchar *filename; + stlink_t *sl; }; struct _STlinkGUIClass { - GObjectClass parent_class; + GObjectClass parent_class; - /* class members */ + /* class members */ }; GType stlink_gui_get_type (void); diff --git a/mingw/mingw.c b/mingw/mingw.c index 493dcbaa2..266a87c64 100644 --- a/mingw/mingw.c +++ b/mingw/mingw.c @@ -22,30 +22,30 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) FD_ZERO(&ofds); FD_ZERO(&efds); for (i = 0, op = ip = 0; i < nfds; ++i) { - fds[i].revents = 0; - if(fds[i].events & (POLLIN|POLLPRI)) { - ip = &ifds; - FD_SET(fds[i].fd, ip); - } - if(fds[i].events & POLLOUT) { - op = &ofds; - FD_SET(fds[i].fd, op); - } - FD_SET(fds[i].fd, &efds); + fds[i].revents = 0; + if(fds[i].events & (POLLIN|POLLPRI)) { + ip = &ifds; + FD_SET(fds[i].fd, ip); + } + if(fds[i].events & POLLOUT) { + op = &ofds; + FD_SET(fds[i].fd, op); + } + FD_SET(fds[i].fd, &efds); } /* Set up the timeval structure for the timeout parameter */ if(timo < 0) { - toptr = 0; + toptr = 0; } else { - toptr = &timeout; - timeout.tv_sec = timo / 1000; - timeout.tv_usec = (timo - timeout.tv_sec * 1000) * 1000; + toptr = &timeout; + timeout.tv_sec = timo / 1000; + timeout.tv_usec = (timo - timeout.tv_sec * 1000) * 1000; } #ifdef DEBUG_POLL printf("Entering select() sec=%ld usec=%ld ip=%lx op=%lx\n", - (long)timeout.tv_sec, (long)timeout.tv_usec, (long)ip, (long)op); + (long)timeout.tv_sec, (long)timeout.tv_usec, (long)ip, (long)op); #endif rc = select(0, ip, op, &efds, toptr); #ifdef DEBUG_POLL @@ -53,23 +53,23 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) #endif if(rc <= 0) - return rc; + return rc; if(rc > 0) { for ( i = 0; i < nfds; ++i) { int fd = fds[i].fd; - if(fds[i].events & (POLLIN|POLLPRI) && FD_ISSET(fd, &ifds)) - fds[i].revents |= POLLIN; - if(fds[i].events & POLLOUT && FD_ISSET(fd, &ofds)) - fds[i].revents |= POLLOUT; - if(FD_ISSET(fd, &efds)) - /* Some error was detected ... should be some way to know. */ - fds[i].revents |= POLLHUP; + if(fds[i].events & (POLLIN|POLLPRI) && FD_ISSET(fd, &ifds)) + fds[i].revents |= POLLIN; + if(fds[i].events & POLLOUT && FD_ISSET(fd, &ofds)) + fds[i].revents |= POLLOUT; + if(FD_ISSET(fd, &efds)) + /* Some error was detected ... should be some way to know. */ + fds[i].revents |= POLLHUP; #ifdef DEBUG_POLL - printf("%d %d %d revent = %x\n", - FD_ISSET(fd, &ifds), FD_ISSET(fd, &ofds), FD_ISSET(fd, &efds), - fds[i].revents - ); + printf("%d %d %d revent = %x\n", + FD_ISSET(fd, &ifds), FD_ISSET(fd, &ofds), FD_ISSET(fd, &efds), + fds[i].revents + ); #endif } } @@ -79,14 +79,14 @@ static void set_connect_errno(int winsock_err) { switch(winsock_err) { - case WSAEINVAL: - case WSAEALREADY: - case WSAEWOULDBLOCK: - errno = EINPROGRESS; - break; - default: - errno = winsock_err; - break; + case WSAEINVAL: + case WSAEALREADY: + case WSAEWOULDBLOCK: + errno = EINPROGRESS; + break; + default: + errno = winsock_err; + break; } } @@ -94,12 +94,12 @@ static void set_socket_errno(int winsock_err) { switch(winsock_err) { - case WSAEWOULDBLOCK: - errno = EAGAIN; - break; - default: - errno = winsock_err; - break; + case WSAEWOULDBLOCK: + errno = EAGAIN; + break; + default: + errno = winsock_err; + break; } } /* @@ -192,75 +192,75 @@ ssize_t win32_read_socket(SOCKET fd, void *buf, int n) char * win32_strtok_r(char *s, const char *delim, char **lasts) { - register char *spanp; - register int c, sc; - char *tok; + register char *spanp; + register int c, sc; + char *tok; - if (s == NULL && (s = *lasts) == NULL) - return (NULL); + if (s == NULL && (s = *lasts) == NULL) + return (NULL); - /* - * Skip (span) leading delimiters (s += strspn(s, delim), sort of). - */ + /* + * Skip (span) leading delimiters (s += strspn(s, delim), sort of). + */ cont: - c = *s++; - for (spanp = (char *)delim; (sc = *spanp++) != 0;) { - if (c == sc) - goto cont; - } + c = *s++; + for (spanp = (char *)delim; (sc = *spanp++) != 0;) { + if (c == sc) + goto cont; + } - if (c == 0) { /* no non-delimiter characters */ - *lasts = NULL; - return (NULL); - } - tok = s - 1; + if (c == 0) { /* no non-delimiter characters */ + *lasts = NULL; + return (NULL); + } + tok = s - 1; - /* - * Scan token (scan for delimiters: s += strcspn(s, delim), sort of). - * Note that delim must have one NUL; we stop if we see that, too. - */ - for (;;) { - c = *s++; - spanp = (char *)delim; - do { - if ((sc = *spanp++) == c) { - if (c == 0) - s = NULL; - else - s[-1] = 0; - *lasts = s; - return (tok); - } - } while (sc != 0); - } - /* NOTREACHED */ + /* + * Scan token (scan for delimiters: s += strcspn(s, delim), sort of). + * Note that delim must have one NUL; we stop if we see that, too. + */ + for (;;) { + c = *s++; + spanp = (char *)delim; + do { + if ((sc = *spanp++) == c) { + if (c == 0) + s = NULL; + else + s[-1] = 0; + *lasts = s; + return (tok); + } + } while (sc != 0); + } + /* NOTREACHED */ } char *win32_strsep (char **stringp, const char *delim) { - register char *s; - register const char *spanp; - register int c, sc; - char *tok; + register char *s; + register const char *spanp; + register int c, sc; + char *tok; - if ((s = *stringp) == NULL) - return (NULL); - for (tok = s;;) { - c = *s++; - spanp = delim; - do { - if ((sc = *spanp++) == c) { - if (c == 0) - s = NULL; - else - s[-1] = 0; - *stringp = s; - return (tok); - } - } while (sc != 0); - } - /* NOTREACHED */ + if ((s = *stringp) == NULL) + return (NULL); + for (tok = s;;) { + c = *s++; + spanp = delim; + do { + if ((sc = *spanp++) == c) { + if (c == 0) + s = NULL; + else + s[-1] = 0; + *stringp = s; + return (tok); + } + } while (sc != 0); + } + /* NOTREACHED */ } #endif diff --git a/src/mmap.c b/src/mmap.c index 9c631da2d..c5794da91 100644 --- a/src/mmap.c +++ b/src/mmap.c @@ -7,27 +7,27 @@ void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offset) { - void *buf; - ssize_t count; + void *buf; + ssize_t count; - if ( addr || fd == -1 || (prot & PROT_WRITE)) return MAP_FAILED; + if ( addr || fd == -1 || (prot & PROT_WRITE)) return MAP_FAILED; - buf = malloc(len); - if ( NULL == buf ) return MAP_FAILED; + buf = malloc(len); + if ( NULL == buf ) return MAP_FAILED; - if (lseek(fd,offset,SEEK_SET) != offset) return MAP_FAILED; + if (lseek(fd,offset,SEEK_SET) != offset) return MAP_FAILED; - count = read(fd, buf, len); + count = read(fd, buf, len); - if (count != len) { - free (buf); - return MAP_FAILED; - } + if (count != len) { + free (buf); + return MAP_FAILED; + } - return buf; + return buf; } int munmap (void *addr, size_t len) { - free (addr); - return 0; + free (addr); + return 0; } diff --git a/src/mmap.h b/src/mmap.h index bff766c4a..71de819fa 100644 --- a/src/mmap.h +++ b/src/mmap.h @@ -19,8 +19,8 @@ extern "C" { #endif -void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); -int munmap(void *addr, size_t len); + void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); + int munmap(void *addr, size_t len); #ifdef __cplusplus } diff --git a/src/st-info.c b/src/st-info.c index 28f3fb823..6fe2f8d7a 100644 --- a/src/st-info.c +++ b/src/st-info.c @@ -11,79 +11,79 @@ static void usage(void) { - puts("st-info --flash"); - puts("st-info --sram"); - puts("st-info --descr"); - puts("st-info --pagesize"); - puts("st-info --chipid"); + puts("st-info --flash"); + puts("st-info --sram"); + puts("st-info --descr"); + puts("st-info --pagesize"); + puts("st-info --chipid"); } static int print_data(stlink_t* sl, char** av) { - int ret = 0; - if (strcmp(av[1], "--flash") == 0) - printf("0x%zx\n", sl->flash_size); - else if (strcmp(av[1], "--sram") == 0) - printf("0x%zx\n", sl->sram_size); - else if (strcmp(av[1], "--pagesize") == 0) - printf("0x%zx\n", sl->flash_pgsz); - else if (strcmp(av[1], "--chipid") == 0) - printf("0x%.4x\n", sl->chip_id); - else if (strcmp(av[1], "--descr")==0) { - const chip_params_t *params = NULL; - for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { - if(devices[i].chip_id == sl->chip_id) { - params = &devices[i]; - break; - } - } - if (params == NULL) { - return -1; - } - printf("%s\n", params->description); - } - return ret; -} + int ret = 0; + if (strcmp(av[1], "--flash") == 0) + printf("0x%zx\n", sl->flash_size); + else if (strcmp(av[1], "--sram") == 0) + printf("0x%zx\n", sl->sram_size); + else if (strcmp(av[1], "--pagesize") == 0) + printf("0x%zx\n", sl->flash_pgsz); + else if (strcmp(av[1], "--chipid") == 0) + printf("0x%.4x\n", sl->chip_id); + else if (strcmp(av[1], "--descr")==0) { + const chip_params_t *params = NULL; + for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { + if(devices[i].chip_id == sl->chip_id) { + params = &devices[i]; + break; + } + } + if (params == NULL) { + return -1; + } + printf("%s\n", params->description); + } + return ret; +} -stlink_t* open_sl(void) +stlink_t* open_sl(void) { - stlink_t* sl; - sl = stlink_v1_open(0, 1); - if (sl == NULL) - sl = stlink_open_usb(0, 1); - return sl; + stlink_t* sl; + sl = stlink_v1_open(0, 1); + if (sl == NULL) + sl = stlink_open_usb(0, 1); + return sl; } int main(int ac, char** av) { - stlink_t* sl = NULL; - int err = -1; - if (ac < 2) { - usage(); - return -1; - } + stlink_t* sl = NULL; + int err = -1; + if (ac < 2) { + usage(); + return -1; + } + + sl = open_sl(); + + if (sl == NULL) { + return -1; + } + sl->verbose=0; + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) + stlink_exit_dfu_mode(sl); - sl = open_sl(); - - if (sl == NULL) { - return -1; - } - sl->verbose=0; - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) - stlink_exit_dfu_mode(sl); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) + stlink_enter_swd_mode(sl); - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) - stlink_enter_swd_mode(sl); + err = print_data(sl, av); - err = print_data(sl, av); - - if (sl != NULL) - { - stlink_exit_debug_mode(sl); - stlink_close(sl); - } + if (sl != NULL) + { + stlink_exit_debug_mode(sl); + stlink_close(sl); + } - return err; + return err; } diff --git a/src/st-term.c b/src/st-term.c index 6881f6218..8350cfffc 100644 --- a/src/st-term.c +++ b/src/st-term.c @@ -13,225 +13,225 @@ #define STLINKY_MAGIC 0xDEADF00D -#define READ_UINT32_LE(buf) ((uint32_t) ( buf[0] \ - | buf[1] << 8 \ - | buf[2] << 16 \ - | buf[3] << 24)) +#define READ_UINT32_LE(buf) ((uint32_t) ( buf[0] \ + | buf[1] << 8 \ + | buf[2] << 16 \ + | buf[3] << 24)) static stlink_t* sl; sigset_t sig_mask; struct stlinky { - stlink_t *sl; - uint32_t off; - size_t bufsize; + stlink_t *sl; + uint32_t off; + size_t bufsize; }; void nonblock(int state); static void cleanup(int signal __attribute__((unused))) { - if (sl) { - /* Switch back to mass storage mode before closing. */ - stlink_run(sl); - stlink_exit_debug_mode(sl); - stlink_close(sl); - } - - printf("\n"); - nonblock(0); - exit(1); + if (sl) { + /* Switch back to mass storage mode before closing. */ + stlink_run(sl); + stlink_exit_debug_mode(sl); + stlink_close(sl); + } + + printf("\n"); + nonblock(0); + exit(1); } void sig_init() { - sigemptyset(&sig_mask); - sigaddset(&sig_mask, SIGINT); - sigaddset(&sig_mask, SIGTERM); - signal(SIGINT, &cleanup); - signal(SIGTERM, &cleanup); - sigprocmask(SIG_BLOCK, &sig_mask, NULL); + sigemptyset(&sig_mask); + sigaddset(&sig_mask, SIGINT); + sigaddset(&sig_mask, SIGTERM); + signal(SIGINT, &cleanup); + signal(SIGTERM, &cleanup); + sigprocmask(SIG_BLOCK, &sig_mask, NULL); } void sig_process() { - sigset_t pending; - sigpending(&pending); - if (sigismember(&pending, SIGINT) || sigismember(&pending, SIGTERM)) { - sigprocmask(SIG_UNBLOCK, &sig_mask, NULL); - sigsuspend(&pending); - sigprocmask(SIG_BLOCK, &sig_mask, NULL); - } + sigset_t pending; + sigpending(&pending); + if (sigismember(&pending, SIGINT) || sigismember(&pending, SIGTERM)) { + sigprocmask(SIG_UNBLOCK, &sig_mask, NULL); + sigsuspend(&pending); + sigprocmask(SIG_BLOCK, &sig_mask, NULL); + } } /* Detects stlinky in RAM, returns handler */ struct stlinky* stlinky_detect(stlink_t* sl) { - static const uint32_t sram_base = 0x20000000; - struct stlinky* st = malloc(sizeof(struct stlinky)); - int multiple=0; - st->sl = sl; - printf("sram: 0x%x bytes @ 0x%zx\n", sl->sram_base, sl->sram_size); - uint32_t off; - for (off = 0; off < sl->sram_size; off += 4) { - if (off % 1024 == 0) sig_process(); - stlink_read_mem32(sl, sram_base + off, 4); - if (STLINKY_MAGIC == READ_UINT32_LE(sl->q_buf)) - { - if (multiple > 0) printf("WARNING: another "); - printf("stlinky detected at 0x%x\n", sram_base + off); - st->off = sram_base + off; - stlink_read_mem32(sl, st->off + 4, 4); - st->bufsize = (size_t) *(unsigned char*) sl->q_buf; - printf("stlinky buffer size 0x%zu \n", st->bufsize); - multiple++; - } - } - if (multiple > 0) { - if (multiple > 1) { - printf("Using last stlinky structure detected\n"); - } - return st; - } - return NULL; + static const uint32_t sram_base = 0x20000000; + struct stlinky* st = malloc(sizeof(struct stlinky)); + int multiple=0; + st->sl = sl; + printf("sram: 0x%x bytes @ 0x%zx\n", sl->sram_base, sl->sram_size); + uint32_t off; + for (off = 0; off < sl->sram_size; off += 4) { + if (off % 1024 == 0) sig_process(); + stlink_read_mem32(sl, sram_base + off, 4); + if (STLINKY_MAGIC == READ_UINT32_LE(sl->q_buf)) + { + if (multiple > 0) printf("WARNING: another "); + printf("stlinky detected at 0x%x\n", sram_base + off); + st->off = sram_base + off; + stlink_read_mem32(sl, st->off + 4, 4); + st->bufsize = (size_t) *(unsigned char*) sl->q_buf; + printf("stlinky buffer size 0x%zu \n", st->bufsize); + multiple++; + } + } + if (multiple > 0) { + if (multiple > 1) { + printf("Using last stlinky structure detected\n"); + } + return st; + } + return NULL; } int stlinky_canrx(struct stlinky *st) { - stlink_read_mem32(st->sl, st->off+4, 4); - unsigned char tx = (unsigned char) st->sl->q_buf[1]; - return (int) tx; + stlink_read_mem32(st->sl, st->off+4, 4); + unsigned char tx = (unsigned char) st->sl->q_buf[1]; + return (int) tx; } size_t stlinky_rx(struct stlinky *st, char* buffer) { - unsigned char tx = 0; - while(tx == 0) { - stlink_read_mem32(st->sl, st->off+4, 4); - tx = (unsigned char) st->sl->q_buf[1]; - } - size_t rs = tx + (4 - (tx % 4)); /* voodoo */ - stlink_read_mem32(st->sl, st->off+8, rs); - memcpy(buffer, st->sl->q_buf, (size_t) tx); - *st->sl->q_buf=0x0; - stlink_write_mem8(st->sl, st->off+5, 1); - return (size_t) tx; + unsigned char tx = 0; + while(tx == 0) { + stlink_read_mem32(st->sl, st->off+4, 4); + tx = (unsigned char) st->sl->q_buf[1]; + } + size_t rs = tx + (4 - (tx % 4)); /* voodoo */ + stlink_read_mem32(st->sl, st->off+8, rs); + memcpy(buffer, st->sl->q_buf, (size_t) tx); + *st->sl->q_buf=0x0; + stlink_write_mem8(st->sl, st->off+5, 1); + return (size_t) tx; } size_t stlinky_tx(struct stlinky *st, char* buffer, size_t sz) { - unsigned char rx = 1; - while(rx != 0) { - stlink_read_mem32(st->sl, st->off+4, 4); - rx = (unsigned char) st->sl->q_buf[2]; - } - memcpy(st->sl->q_buf, buffer, sz); - size_t rs = sz + (4 - (sz % 4)); /* voodoo */ - stlink_write_mem32(st->sl, st->off+8+st->bufsize, rs); - *st->sl->q_buf=(unsigned char) sz; - stlink_write_mem8(st->sl, st->off+6, 1); - return (size_t) rx; + unsigned char rx = 1; + while(rx != 0) { + stlink_read_mem32(st->sl, st->off+4, 4); + rx = (unsigned char) st->sl->q_buf[2]; + } + memcpy(st->sl->q_buf, buffer, sz); + size_t rs = sz + (4 - (sz % 4)); /* voodoo */ + stlink_write_mem32(st->sl, st->off+8+st->bufsize, rs); + *st->sl->q_buf=(unsigned char) sz; + stlink_write_mem8(st->sl, st->off+6, 1); + return (size_t) rx; } int kbhit() { - struct timeval tv; - fd_set fds; - tv.tv_sec = 0; - tv.tv_usec = 0; - FD_ZERO(&fds); - FD_SET(STDIN_FILENO, &fds); //STDIN_FILENO is 0 - select(STDIN_FILENO+1, &fds, NULL, NULL, &tv); - return FD_ISSET(STDIN_FILENO, &fds); + struct timeval tv; + fd_set fds; + tv.tv_sec = 0; + tv.tv_usec = 0; + FD_ZERO(&fds); + FD_SET(STDIN_FILENO, &fds); //STDIN_FILENO is 0 + select(STDIN_FILENO+1, &fds, NULL, NULL, &tv); + return FD_ISSET(STDIN_FILENO, &fds); } void nonblock(int state) { - struct termios ttystate; - - //get the terminal state - tcgetattr(STDIN_FILENO, &ttystate); - - if (state==1) - { - //turn off canonical mode - ttystate.c_lflag &= ~ICANON; - ttystate.c_lflag &= ~ECHO; - //minimum of number input read. - ttystate.c_cc[VMIN] = 1; - } - else if (state==0) - { - //turn on canonical mode - ttystate.c_lflag |= ICANON | ECHO; - } - //set the terminal attributes. - tcsetattr(STDIN_FILENO, TCSANOW, &ttystate); + struct termios ttystate; + + //get the terminal state + tcgetattr(STDIN_FILENO, &ttystate); + + if (state==1) + { + //turn off canonical mode + ttystate.c_lflag &= ~ICANON; + ttystate.c_lflag &= ~ECHO; + //minimum of number input read. + ttystate.c_cc[VMIN] = 1; + } + else if (state==0) + { + //turn on canonical mode + ttystate.c_lflag |= ICANON | ECHO; + } + //set the terminal attributes. + tcsetattr(STDIN_FILENO, TCSANOW, &ttystate); } int main(int ac, char** av) { - struct stlinky *st=NULL; - - sig_init(); - - sl = stlink_open_usb(10, 1); - if (sl != NULL) { - printf("ST-Linky proof-of-concept terminal :: Created by Necromant for lulz\n"); - stlink_version(sl); - stlink_enter_swd_mode(sl); - printf("chip id: %#x\n", sl->chip_id); - printf("core_id: %#x\n", sl->core_id); - - cortex_m3_cpuid_t cpuid; - stlink_cpu_id(sl, &cpuid); - printf("cpuid:impl_id = %0#x, variant = %#x\n", cpuid.implementer_id, cpuid.variant); - printf("cpuid:part = %#x, rev = %#x\n", cpuid.part, cpuid.revision); - - stlink_reset(sl); - stlink_force_debug(sl); - stlink_run(sl); - stlink_status(sl); - - /* wait for device to boot */ - /* TODO: Make timeout adjustable via command line */ - sleep(1); - - if(ac == 1){ - st = stlinky_detect(sl); - }else if(ac == 2){ - st = malloc(sizeof(struct stlinky)); - st->sl = sl; - st->off = (int)strtol(av[1], NULL, 16); - printf("using stlinky at 0x%x\n", st->off); - stlink_read_mem32(sl, st->off + 4, 4); - st->bufsize = (size_t) *(unsigned char*) sl->q_buf; - printf("stlinky buffer size 0x%zu \n", st->bufsize); - }else{ - cleanup(0); - } - if (st == NULL) - { - printf("stlinky magic not found in sram :(\n"); - cleanup(0); - } - char* rxbuf = malloc(st->bufsize); - char* txbuf = malloc(st->bufsize); - size_t tmp; - nonblock(1); - int fd = fileno(stdin); - int saved_flags = fcntl(fd, F_GETFL); - fcntl(fd, F_SETFL, saved_flags & ~O_NONBLOCK); - printf("Entering interactive terminal. CTRL+C to exit\n\n\n"); - while(1) { - sig_process(); - if (stlinky_canrx(st)) { - tmp = stlinky_rx(st, rxbuf); - fwrite(rxbuf,tmp,1,stdout); - fflush(stdout); - } - if (kbhit()) { - tmp = read(fd, txbuf, st->bufsize); - stlinky_tx(st,txbuf,tmp); - } - } - } - return 0; + struct stlinky *st=NULL; + + sig_init(); + + sl = stlink_open_usb(10, 1); + if (sl != NULL) { + printf("ST-Linky proof-of-concept terminal :: Created by Necromant for lulz\n"); + stlink_version(sl); + stlink_enter_swd_mode(sl); + printf("chip id: %#x\n", sl->chip_id); + printf("core_id: %#x\n", sl->core_id); + + cortex_m3_cpuid_t cpuid; + stlink_cpu_id(sl, &cpuid); + printf("cpuid:impl_id = %0#x, variant = %#x\n", cpuid.implementer_id, cpuid.variant); + printf("cpuid:part = %#x, rev = %#x\n", cpuid.part, cpuid.revision); + + stlink_reset(sl); + stlink_force_debug(sl); + stlink_run(sl); + stlink_status(sl); + + /* wait for device to boot */ + /* TODO: Make timeout adjustable via command line */ + sleep(1); + + if(ac == 1){ + st = stlinky_detect(sl); + }else if(ac == 2){ + st = malloc(sizeof(struct stlinky)); + st->sl = sl; + st->off = (int)strtol(av[1], NULL, 16); + printf("using stlinky at 0x%x\n", st->off); + stlink_read_mem32(sl, st->off + 4, 4); + st->bufsize = (size_t) *(unsigned char*) sl->q_buf; + printf("stlinky buffer size 0x%zu \n", st->bufsize); + }else{ + cleanup(0); + } + if (st == NULL) + { + printf("stlinky magic not found in sram :(\n"); + cleanup(0); + } + char* rxbuf = malloc(st->bufsize); + char* txbuf = malloc(st->bufsize); + size_t tmp; + nonblock(1); + int fd = fileno(stdin); + int saved_flags = fcntl(fd, F_GETFL); + fcntl(fd, F_SETFL, saved_flags & ~O_NONBLOCK); + printf("Entering interactive terminal. CTRL+C to exit\n\n\n"); + while(1) { + sig_process(); + if (stlinky_canrx(st)) { + tmp = stlinky_rx(st, rxbuf); + fwrite(rxbuf,tmp,1,stdout); + fflush(stdout); + } + if (kbhit()) { + tmp = read(fd, txbuf, st->bufsize); + stlinky_tx(st,txbuf,tmp); + } + } + } + return 0; } diff --git a/src/stlink-common.c b/src/stlink-common.c index 545434b4e..ce1306b12 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -144,7 +144,7 @@ static inline uint32_t read_flash_obr(stlink_t *sl) { static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t res; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) res = stlink_read_debug32(sl, FLASH_F4_CR); else res = stlink_read_debug32(sl, FLASH_CR); @@ -157,7 +157,7 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); else return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); @@ -168,13 +168,13 @@ static void unlock_flash(stlink_t *sl) { 2 key values are written to the FLASH_KEYR register. an invalid sequence results in a definitive lock of the FPEC block until next reset. - */ + */ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { - stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { + stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); } else { - stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1); + stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2); } @@ -196,9 +196,9 @@ static int unlock_flash_if(stlink_t *sl) { static void lock_flash(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { - const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); - stlink_write_debug32(sl, FLASH_F4_CR, n); + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { + const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); + stlink_write_debug32(sl, FLASH_F4_CR, n); } else { /* write to 1 only. reset by hw at unlock sequence */ const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK); @@ -209,10 +209,10 @@ static void lock_flash(stlink_t *sl) { static void set_flash_cr_pg(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { - uint32_t x = read_flash_cr(sl); - x |= (1 << FLASH_CR_PG); - stlink_write_debug32(sl, FLASH_F4_CR, x); + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { + uint32_t x = read_flash_cr(sl); + x |= (1 << FLASH_CR_PG); + stlink_write_debug32(sl, FLASH_F4_CR, x); } else { const uint32_t n = 1 << FLASH_CR_PG; stlink_write_debug32(sl, FLASH_CR, n); @@ -222,8 +222,8 @@ static void set_flash_cr_pg(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) - stlink_write_debug32(sl, FLASH_F4_CR, n); + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) + stlink_write_debug32(sl, FLASH_F4_CR, n); else stlink_write_debug32(sl, FLASH_CR, n); } @@ -240,33 +240,33 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { static void set_flash_cr_mer(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) stlink_write_debug32(sl, FLASH_F4_CR, - stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); + stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); else stlink_write_debug32(sl, FLASH_CR, - stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER)); + stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER)); } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) stlink_write_debug32(sl, FLASH_F4_CR, - stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); + stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); else stlink_write_debug32(sl, FLASH_CR, - stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER)); + stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER)); } static void set_flash_cr_strt(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_F4_CR_STRT); stlink_write_debug32(sl, FLASH_F4_CR, x); } else { stlink_write_debug32(sl, FLASH_CR, - stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_STRT) ); + stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_STRT) ); } } @@ -277,7 +277,7 @@ static inline uint32_t read_flash_acr(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) res = stlink_read_debug32(sl, FLASH_F4_SR); else res = stlink_read_debug32(sl, FLASH_SR); @@ -287,7 +287,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { static inline unsigned int is_flash_busy(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); else return read_flash_sr(sl) & (1 << FLASH_SR_BSY); @@ -464,7 +464,7 @@ int stlink_load_device_params(stlink_t *sl) { flash_size = flash_size & 0xffff; if ((sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) && ( flash_size == 0 )) { - sl->flash_size = 128 * 1024; + sl->flash_size = 128 * 1024; } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_HIGH) { // 0 is 384k and 1 is 256k if ( flash_size == 0 ) { @@ -483,8 +483,8 @@ int stlink_load_device_params(stlink_t *sl) { ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); // TODO make note of variable page size here..... ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n", - sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, - sl->flash_pgsz); + sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, + sl->flash_pgsz); return 0; } @@ -557,11 +557,11 @@ int stlink_target_voltage(stlink_t *sl) { DLOG("*** reading target voltage\n"); if (sl->backend->target_voltage != NULL) { voltage = sl->backend->target_voltage(sl); - if (voltage != -1) { + if (voltage != -1) { DLOG("target voltage = %ldmV\n", voltage); - } else { + } else { DLOG("error reading target voltage\n"); - } + } } else { DLOG("reading voltage not supported by backend\n"); } @@ -691,15 +691,15 @@ void stlink_step(stlink_t *sl) { int stlink_current_mode(stlink_t *sl) { int mode = sl->backend->current_mode(sl); switch (mode) { - case STLINK_DEV_DFU_MODE: - DLOG("stlink current mode: dfu\n"); - return mode; - case STLINK_DEV_DEBUG_MODE: - DLOG("stlink current mode: debug (jtag or swd)\n"); - return mode; - case STLINK_DEV_MASS_MODE: - DLOG("stlink current mode: mass\n"); - return mode; + case STLINK_DEV_DFU_MODE: + DLOG("stlink current mode: dfu\n"); + return mode; + case STLINK_DEV_DEBUG_MODE: + DLOG("stlink current mode: debug (jtag or swd)\n"); + return mode; + case STLINK_DEV_MASS_MODE: + DLOG("stlink current mode: mass\n"); + return mode; } DLOG("stlink mode: unknown!\n"); return STLINK_DEV_UNKNOWN_MODE; @@ -750,17 +750,17 @@ void stlink_core_stat(stlink_t *sl) { return; switch (sl->q_buf[0]) { - case STLINK_CORE_RUNNING: - sl->core_stat = STLINK_CORE_RUNNING; - DLOG(" core status: running\n"); - return; - case STLINK_CORE_HALTED: - sl->core_stat = STLINK_CORE_HALTED; - DLOG(" core status: halted\n"); - return; - default: - sl->core_stat = STLINK_CORE_STAT_UNKNOWN; - fprintf(stderr, " core status: unknown\n"); + case STLINK_CORE_RUNNING: + sl->core_stat = STLINK_CORE_RUNNING; + DLOG(" core status: running\n"); + return; + case STLINK_CORE_HALTED: + sl->core_stat = STLINK_CORE_HALTED; + DLOG(" core status: halted\n"); + return; + default: + sl->core_stat = STLINK_CORE_STAT_UNKNOWN; + fprintf(stderr, " core status: unknown\n"); } } @@ -773,11 +773,11 @@ void stlink_print_data(stlink_t * sl) { for (int i = 0; i < sl->q_len; i++) { if (i % 16 == 0) { /* - if (sl->q_data_dir == Q_DATA_OUT) - fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); - else - fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); - */ + if (sl->q_data_dir == Q_DATA_OUT) + fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); + else + fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); + */ } fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]); } @@ -931,7 +931,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) size_t off; int num_empty = 0; unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -940,32 +940,32 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) } if (size <1) - size = sl->flash_size; + size = sl->flash_size; if (size > sl->flash_size) - size = sl->flash_size; + size = sl->flash_size; /* do the copy by 1k blocks */ for (off = 0; off < size; off += 1024) { size_t read_size = 1024; - size_t rounded_size; - size_t index; + size_t rounded_size; + size_t index; if ((off + read_size) > size) - read_size = size - off; + read_size = size - off; /* round size if needed */ - rounded_size = read_size; + rounded_size = read_size; if (rounded_size & 3) - rounded_size = (rounded_size + 4) & ~(3); + rounded_size = (rounded_size + 4) & ~(3); stlink_read_mem32(sl, addr + off, rounded_size); - for(index = 0; index < read_size; index ++) { - if (sl->q_buf[index] == erased_pattern) - num_empty ++; - else - num_empty = 0; - } + for(index = 0; index < read_size; index ++) { + if (sl->q_buf[index] == erased_pattern) + num_empty ++; + else + num_empty = 0; + } if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) { fprintf(stderr, "write() != read_size\n"); goto on_error; @@ -1013,14 +1013,14 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { - uint32_t sector=calculate_F4_sectornum(flashaddr); - if (sector<4) sl->flash_pgsz=0x4000; - else if(sector<5) sl->flash_pgsz=0x10000; - else sl->flash_pgsz=0x20000; - } - return (sl->flash_pgsz); + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { + uint32_t sector=calculate_F4_sectornum(flashaddr); + if (sector<4) sl->flash_pgsz=0x4000; + else if(sector<5) sl->flash_pgsz=0x10000; + else sl->flash_pgsz=0x20000; + } + return (sl->flash_pgsz); } /** @@ -1032,144 +1032,144 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { - /* wait for ongoing op to finish */ - wait_flash_busy(sl); + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { + /* wait for ongoing op to finish */ + wait_flash_busy(sl); - /* unlock if locked */ - unlock_flash_if(sl); + /* unlock if locked */ + unlock_flash_if(sl); - /* select the page to erase */ - // calculate the actual page from the address - uint32_t sector=calculate_F4_sectornum(flashaddr); + /* select the page to erase */ + // calculate the actual page from the address + uint32_t sector=calculate_F4_sectornum(flashaddr); - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); - write_flash_cr_snb(sl, sector); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); + write_flash_cr_snb(sl, sector); - /* start erase operation */ - set_flash_cr_strt(sl); + /* start erase operation */ + set_flash_cr_strt(sl); - /* wait for completion */ - wait_flash_busy(sl); + /* wait for completion */ + wait_flash_busy(sl); - /* relock the flash */ - //todo: fails to program if this is in - lock_flash(sl); + /* relock the flash */ + //todo: fails to program if this is in + lock_flash(sl); #if DEBUG_FLASH - fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); + fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif - } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { + } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { - uint32_t val; + uint32_t val; - /* check if the locks are set */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if((val & (1<<0))||(val & (1<<1))) { - /* disable pecr protection */ - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); - - /* check pecr.pelock is cleared */ + /* check if the locks are set */ val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 0)) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return -1; - } + if((val & (1<<0))||(val & (1<<1))) { + /* disable pecr protection */ + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); - /* unlock program memory */ - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); + /* check pecr.pelock is cleared */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + if (val & (1 << 0)) { + WLOG("pecr.pelock not clear (%#x)\n", val); + return -1; + } - /* check pecr.prglock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 1)) { - WLOG("pecr.prglock not clear (%#x)\n", val); - return -1; + /* unlock program memory */ + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); + + /* check pecr.prglock is cleared */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + if (val & (1 << 1)) { + WLOG("pecr.prglock not clear (%#x)\n", val); + return -1; + } } - } - /* unused: unlock the option byte block */ + /* unused: unlock the option byte block */ #if 0 - stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8); - stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627); + stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8); + stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627); - /* check pecr.optlock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 2)) { - fprintf(stderr, "pecr.prglock not clear\n"); - return -1; - } + /* check pecr.optlock is cleared */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + if (val & (1 << 2)) { + fprintf(stderr, "pecr.prglock not clear\n"); + return -1; + } #endif - /* set pecr.{erase,prog} */ - val |= (1 << 9) | (1 << 3); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + /* set pecr.{erase,prog} */ + val |= (1 << 9) | (1 << 3); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); #if 0 /* fix_to_be_confirmed */ - /* wait for sr.busy to be cleared - MP: Test shows that busy bit is not set here. Perhaps, PM0062 is - wrong and we do not need to wait here for clearing the busy bit. - TEXANE: ok, if experience says so and it works for you, we comment - it. If someone has a problem, please drop an email. - */ - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) - ; + /* wait for sr.busy to be cleared + * MP: Test shows that busy bit is not set here. Perhaps, PM0062 is + * wrong and we do not need to wait here for clearing the busy bit. + * TEXANE: ok, if experience says so and it works for you, we comment + * it. If someone has a problem, please drop an email. + */ + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) + ; #endif /* fix_to_be_confirmed */ - /* write 0 to the first word of the page to be erased */ - stlink_write_debug32(sl, flashaddr, 0); - - /* MP: It is better to wait for clearing the busy bit after issuing - page erase command, even though PM0062 recommends to wait before it. - Test shows that a few iterations is performed in the following loop - before busy bit is cleared.*/ - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) - ; - - /* reset lock bits */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR) - | (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - } else if (sl->core_id == STM32VL_CORE_ID - || sl->core_id == STM32F0_CORE_ID - || sl->chip_id == STM32_CHIPID_F3 - || sl->chip_id == STM32_CHIPID_F37x) { - /* wait for ongoing op to finish */ - wait_flash_busy(sl); + /* write 0 to the first word of the page to be erased */ + stlink_write_debug32(sl, flashaddr, 0); + + /* MP: It is better to wait for clearing the busy bit after issuing + page erase command, even though PM0062 recommends to wait before it. + Test shows that a few iterations is performed in the following loop + before busy bit is cleared.*/ + while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) + ; + + /* reset lock bits */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR) + | (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + } else if (sl->core_id == STM32VL_CORE_ID + || sl->core_id == STM32F0_CORE_ID + || sl->chip_id == STM32_CHIPID_F3 + || sl->chip_id == STM32_CHIPID_F37x) { + /* wait for ongoing op to finish */ + wait_flash_busy(sl); - /* unlock if locked */ - unlock_flash_if(sl); + /* unlock if locked */ + unlock_flash_if(sl); - /* set the page erase bit */ - set_flash_cr_per(sl); + /* set the page erase bit */ + set_flash_cr_per(sl); - /* select the page to erase */ - write_flash_ar(sl, flashaddr); + /* select the page to erase */ + write_flash_ar(sl, flashaddr); - /* start erase operation, reset by hw with bsy bit */ - set_flash_cr_strt(sl); + /* start erase operation, reset by hw with bsy bit */ + set_flash_cr_strt(sl); - /* wait for completion */ - wait_flash_busy(sl); + /* wait for completion */ + wait_flash_busy(sl); - /* relock the flash */ - lock_flash(sl); - } else { - WLOG("unknown coreid %x, page erase failed\n", sl->core_id); - return -1; - } + /* relock the flash */ + lock_flash(sl); + } else { + WLOG("unknown coreid %x, page erase failed\n", sl->core_id); + return -1; + } - /* todo: verify the erased page */ + /* todo: verify the erased page */ - return 0; + return 0; } int stlink_erase_flash_mass(stlink_t *sl) { if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { /* erase each page */ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1266,13 +1266,13 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x0A, 0x4C, // ldr r4, STM32_FLASH_BASE 0x01, 0x25, // mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */ 0x04, 0x26, // mov r6, #4 /* PGERR */ - // write_half_word: + // write_half_word: 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */ 0x2B, 0x43, // orr r3, r5 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */ 0x03, 0x88, // ldrh r3, [r0] /* r3 = *sram */ 0x0B, 0x80, // strh r3, [r1] /* *flash = r3 */ - // busy: + // busy: 0xE3, 0x68, // ldr r3, [r4, #12] /* FLASH->SR */ 0x2B, 0x42, // tst r3, r5 /* FLASH_SR_BUSY */ 0xFC, 0xD0, // beq busy @@ -1285,7 +1285,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x01, 0x3A, // sub r2, r2, #0x01 /* count-- */ 0x00, 0x2A, // cmp r2, #0 0xF0, 0xD1, // bne write_half_word - // exit: + // exit: 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */ 0xAB, 0x43, // bic r3, r5 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */ @@ -1300,7 +1300,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { r1, input, source addr r2, input, word count r3, output, word count - */ + */ 0x00, 0x23, 0x04, 0xe0, @@ -1340,14 +1340,14 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { size_t loader_size; if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { /* stm32l */ + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD){ + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD){ loader_code = loader_code_stm32f4; loader_size = sizeof(loader_code_stm32f4); } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL) { @@ -1473,7 +1473,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t size_t off; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", - len, len, addr, addr); + len, len, addr, addr); /* check addr range is inside the flash */ stlink_calculate_pagesize(sl, addr); if (addr < sl->flash_base) { @@ -1507,17 +1507,17 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t return -1; } fprintf(stdout,"\rFlash page at addr: 0x%08lx erased", - (unsigned long)addr + off); + (unsigned long)addr + off); fflush(stdout); page_count++; } fprintf(stdout,"\n"); ILOG("Finished erasing %d pages of %d (%#x) bytes\n", - page_count, sl->flash_pgsz, sl->flash_pgsz); + page_count, sl->flash_pgsz, sl->flash_pgsz); if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { - /* todo: check write operation */ + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { + /* todo: check write operation */ ILOG("Starting Flash write for F2/F4\n"); /* flash loader initialization */ @@ -1526,15 +1526,15 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t return -1; } - /* First unlock the cr */ - unlock_flash_if(sl); + /* First unlock the cr */ + unlock_flash_if(sl); - /* TODO: Check that Voltage range is 2.7 - 3.6 V */ - /* set parallelisim to 32 bit*/ - write_flash_cr_psiz(sl, 2); + /* TODO: Check that Voltage range is 2.7 - 3.6 V */ + /* set parallelisim to 32 bit*/ + write_flash_cr_psiz(sl, 2); - /* set programming mode */ - set_flash_cr_pg(sl); + /* set programming mode */ + set_flash_cr_pg(sl); for(off = 0; off < len;) { size_t size = len - off > 0x8000 ? 0x8000 : len - off; @@ -1551,8 +1551,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t #if 0 #define PROGRESS_CHUNK_SIZE 0x1000 - /* write a word in program memory */ - for (off = 0; off < len; off += sizeof(uint32_t)) { + /* write a word in program memory */ + for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; if (sl->verbose >= 1) { if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) { @@ -1569,65 +1569,65 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t stlink_write_debug32(sl, addr + off, data); /* wait for sr.busy to be cleared */ - wait_flash_busy(sl); + wait_flash_busy(sl); - } + } #endif - /* Relock flash */ - lock_flash(sl); + /* Relock flash */ + lock_flash(sl); #if 0 /* todo: debug mode */ - fprintf(stdout, "Final CR:0x%x\n", read_flash_cr(sl)); + fprintf(stdout, "Final CR:0x%x\n", read_flash_cr(sl)); #endif } //STM32F4END else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { - /* use fast word write. todo: half page. */ - uint32_t val; + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { + /* use fast word write. todo: half page. */ + uint32_t val; #if 0 /* todo: check write operation */ - uint32_t nwrites = sl->flash_pgsz; + uint32_t nwrites = sl->flash_pgsz; - redo_write: +redo_write: #endif /* todo: check write operation */ - /* disable pecr protection */ - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); - - /* check pecr.pelock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 0)) { - fprintf(stderr, "pecr.pelock not clear\n"); - return -1; - } - - /* unlock program memory */ - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); - - /* check pecr.prglock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 1)) { - fprintf(stderr, "pecr.prglock not clear\n"); - return -1; - } - off = 0; + /* disable pecr protection */ + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); + stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); + + /* check pecr.pelock is cleared */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + if (val & (1 << 0)) { + fprintf(stderr, "pecr.pelock not clear\n"); + return -1; + } + + /* unlock program memory */ + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); + stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); + + /* check pecr.prglock is cleared */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + if (val & (1 << 1)) { + fprintf(stderr, "pecr.prglock not clear\n"); + return -1; + } + off = 0; if (len > L1_WRITE_BLOCK_SIZE) { if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1) { - /* This may happen on a blank device! */ + /* This may happen on a blank device! */ WLOG("\nwrite_half_pages failed == -1\n"); - } else { - off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE; - } - } + } else { + off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE; + } + } - /* write remainingword in program memory */ - for ( ; off < len; off += sizeof(uint32_t)) { + /* write remainingword in program memory */ + for ( ; off < len; off += sizeof(uint32_t)) { uint32_t data; if (off > 254) fprintf(stdout, "\r"); @@ -1683,12 +1683,12 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t ++nwrites; #endif /* todo: check redo write operation */ - } + } fprintf(stdout, "\n"); - /* reset lock bits */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR) - | (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + /* reset lock bits */ + val = stlink_read_debug32(sl, STM32L_FLASH_PECR) + | (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, STM32L_FLASH_PECR, val); } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { ILOG("Starting Flash write for VL/F0 core id\n"); /* flash loader initialization */ @@ -1715,7 +1715,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t if (sl->verbose >= 1) { /* show progress. writing procedure is slow and previous errors are misleading */ - fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz); + fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz); fflush(stdout); } } @@ -1740,23 +1740,23 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { int err; unsigned int num_empty = 0, index; unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE )?0:0xff; + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE )?0:0xff; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { ELOG("map_file() == -1\n"); return -1; } for(index = 0; index < mf.len; index ++) { - if (mf.base[index] == erased_pattern) - num_empty ++; - else - num_empty = 0; + if (mf.base[index] == erased_pattern) + num_empty ++; + else + num_empty = 0; } /* Round down to words */ num_empty -= (num_empty & 3); if(num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); - mf.len -= num_empty; + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); + mf.len -= num_empty; } err = stlink_write_flash(sl, addr, mf.base, mf.len); /* set stack*/ @@ -1781,7 +1781,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1805,7 +1805,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD) { + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1839,27 +1839,27 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons /* check written byte count */ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { - size_t count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) ++count; + size_t count = size / sizeof(uint32_t); + if (size % sizeof(uint32_t)) ++count; - stlink_read_reg(sl, 3, &rr); - if (rr.r[3] != count) { - fprintf(stderr, "write error, count == %u\n", rr.r[3]); - return -1; - } + stlink_read_reg(sl, 3, &rr); + if (rr.r[3] != count) { + fprintf(stderr, "write error, count == %u\n", rr.r[3]); + return -1; + } } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { - stlink_read_reg(sl, 2, &rr); - if (rr.r[2] != 0) { - fprintf(stderr, "write error, count == %u\n", rr.r[2]); - return -1; - } + stlink_read_reg(sl, 2, &rr); + if (rr.r[2] != 0) { + fprintf(stderr, "write error, count == %u\n", rr.r[2]); + return -1; + } } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD) { + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { @@ -1869,8 +1869,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else { - fprintf(stderr, "unknown coreid 0x%x, can't check written byte count\n", sl->core_id); - return -1; + fprintf(stderr, "unknown coreid 0x%x, can't check written byte count\n", sl->core_id); + return -1; } diff --git a/src/stlink-common.h b/src/stlink-common.h index 1bedbf497..898b2a59a 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -7,7 +7,7 @@ */ #ifndef STLINK_COMMON_H -#define STLINK_COMMON_H +#define STLINK_COMMON_H #ifdef __cplusplus extern "C" { @@ -77,12 +77,12 @@ extern "C" { #define STLINK_JTAG_DRIVE_NRST 0x3c #define STLINK_JTAG_DRIVE_NRST 0x3c -// cortex m3 technical reference manual + // cortex m3 technical reference manual #define CM3_REG_CPUID 0xE000ED00 #define CM3_REG_FP_CTRL 0xE0002000 #define CM3_REG_FP_COMP0 0xE0002008 -/* cortex core ids */ + /* cortex core ids */ // TODO clean this up... #define STM32VL_CORE_ID 0x1ba01477 #define STM32L_CORE_ID 0x2ba01477 @@ -93,11 +93,11 @@ extern "C" { #define CORE_M3_R2 0x4BA00477 #define CORE_M4_R0 0x2BA01477 -/* - * Chip IDs are explained in the appropriate programming manual for the - * DBGMCU_IDCODE register (0xE0042000) - */ -// stm32 chipids, only lower 12 bits.. + /* + * Chip IDs are explained in the appropriate programming manual for the + * DBGMCU_IDCODE register (0xE0042000) + */ + // stm32 chipids, only lower 12 bits.. #define STM32_CHIPID_F1_MEDIUM 0x410 #define STM32_CHIPID_F2 0x411 #define STM32_CHIPID_F1_LOW 0x412 @@ -132,252 +132,252 @@ extern "C" { #define STM32_CHIPID_F0_CAN 0x448 -/* - * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus" - * and some that are called "High". 0x427 is assigned to the other "Medium- - * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and - * 0x436 HIGH. - */ + /* + * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus" + * and some that are called "High". 0x427 is assigned to the other "Medium- + * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and + * 0x436 HIGH. + */ -// Constant STM32 memory map figures + // Constant STM32 memory map figures #define STM32_FLASH_BASE 0x08000000 #define STM32_SRAM_BASE 0x20000000 -/* Cortex™-M3 Technical Reference Manual */ -/* Debug Halting Control and Status Register */ + /* Cortex™-M3 Technical Reference Manual */ + /* Debug Halting Control and Status Register */ #define DHCSR 0xe000edf0 #define DCRSR 0xe000edf4 #define DCRDR 0xe000edf8 #define DBGKEY 0xa05f0000 -/* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ + /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 typedef struct chip_params_ { - uint32_t chip_id; - char* description; + uint32_t chip_id; + char* description; uint32_t flash_size_reg; - uint32_t flash_pagesize; - uint32_t sram_size; - uint32_t bootrom_base, bootrom_size; + uint32_t flash_pagesize; + uint32_t sram_size; + uint32_t bootrom_base, bootrom_size; } chip_params_t; -// These maps are from a combination of the Programming Manuals, and -// also the Reference manuals. (flash size reg is normally in ref man) -static const chip_params_t devices[] = { + // These maps are from a combination of the Programming Manuals, and + // also the Reference manuals. (flash size reg is normally in ref man) + static const chip_params_t devices[] = { { // table 2, PM0063 .chip_id = STM32_CHIPID_F1_MEDIUM, .description = "F1 Medium-density device", .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x5000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .flash_pagesize = 0x400, + .sram_size = 0x5000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 }, { // table 1, PM0059 .chip_id = STM32_CHIPID_F2, - .description = "F2 device", - .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/ - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .description = "F2 device", + .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/ + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 }, { // PM0063 .chip_id = STM32_CHIPID_F1_LOW, - .description = "F1 Low-density device", - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2800, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .description = "F1 Low-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2800, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 }, { .chip_id = STM32_CHIPID_F4, - .description = "F4 device", - .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ - .flash_pagesize = 0x4000, - .sram_size = 0x30000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .description = "F4 device", + .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ + .flash_pagesize = 0x4000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 }, { .chip_id = STM32_CHIPID_F4_HD, - .description = "F42x and F43x device", - .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ - .flash_pagesize = 0x4000, - .sram_size = 0x30000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .description = "F42x and F43x device", + .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ + .flash_pagesize = 0x4000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 }, { .chip_id = STM32_CHIPID_F4_LP, - .description = "F4 device (low power)", - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .description = "F4 device (low power)", + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x10000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 }, { .chip_id = STM32_CHIPID_F4_DE, - .description = "F4 device (Dynamic Efficency)", - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .description = "F4 device (Dynamic Efficency)", + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 }, { .chip_id = STM32_CHIPID_F1_HIGH, - .description = "F1 High-density device", - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .description = "F1 High-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 }, { - // This ignores the EEPROM! (and uses the page erase size, - // not the sector write protection...) + // This ignores the EEPROM! (and uses the page erase size, + // not the sector write protection...) .chip_id = STM32_CHIPID_L1_MEDIUM, - .description = "L1 Med-density device", - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x4000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 + .description = "L1 Med-density device", + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x4000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 }, { .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS, - .description = "L1 Medium-Plus-density device", - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/ - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 + .description = "L1 Medium-Plus-density device", + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/ + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 }, { .chip_id = STM32_CHIPID_L1_HIGH, - .description = "L1 High-density device", - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/ - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 + .description = "L1 High-density device", + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/ + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 }, { .chip_id = STM32_CHIPID_L152_RE, - .description = "L152RE", - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/ - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 + .description = "L152RE", + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/ + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 }, { .chip_id = STM32_CHIPID_F1_CONN, - .description = "F1 Connectivity line device", - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1fffb000, - .bootrom_size = 0x4800 + .description = "F1 Connectivity line device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1fffb000, + .bootrom_size = 0x4800 }, { .chip_id = STM32_CHIPID_F1_VL_MEDIUM, - .description = "F1 Medium-density Value Line device", - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .description = "F1 Medium-density Value Line device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 }, { - // This is STK32F303VCT6 device from STM32 F3 Discovery board. - // Support based on DM00043574.pdf (RM0316) document. + // This is STK32F303VCT6 device from STM32 F3 Discovery board. + // Support based on DM00043574.pdf (RM0316) document. .chip_id = STM32_CHIPID_F3, - .description = "F3 device", - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .description = "F3 device", + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 }, { - // This is STK32F373VCT6 device from STM32 F373 eval board - // Support based on 303 above (37x and 30x have same memory map) + // This is STK32F373VCT6 device from STM32 F373 eval board + // Support based on 303 above (37x and 30x have same memory map) .chip_id = STM32_CHIPID_F37x, - .description = "F3 device", - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .description = "F3 device", + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 }, { .chip_id = STM32_CHIPID_F1_VL_HIGH, - .description = "F1 High-density value line device", - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x8000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .description = "F1 High-density value line device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x8000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 }, { .chip_id = STM32_CHIPID_F1_XL, - .description = "F1 XL-density device", - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x18000, - .bootrom_base = 0x1fffe000, - .bootrom_size = 0x1800 + .description = "F1 XL-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x18000, + .bootrom_base = 0x1fffe000, + .bootrom_size = 0x1800 }, - { - //Use this as an example for mapping future chips: - //RM0091 document was used to find these paramaters + { + //Use this as an example for mapping future chips: + //RM0091 document was used to find these paramaters .chip_id = STM32_CHIPID_F0_CAN, - .description = "F07x device", - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 - .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2 + .description = "F07x device", + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 + .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 + .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2 }, { //Use this as an example for mapping future chips: //RM0091 document was used to find these paramaters .chip_id = STM32_CHIPID_F0, - .description = "F0 device", - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + .description = "F0 device", + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 }, { //Use this as an example for mapping future chips: //RM0091 document was used to find these paramaters .chip_id = STM32_CHIPID_F0_SMALL, - .description = "F0 small device", - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + .description = "F0 small device", + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 }, { - // STM32F30x + // STM32F30x .chip_id = STM32_CHIPID_F3_SMALL, - .description = "F3 small device", - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000 + .description = "F3 small device", + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1fffd800, + .bootrom_size = 0x2000 }, - }; + }; typedef struct { @@ -566,4 +566,3 @@ static const chip_params_t devices[] = { #endif #endif /* STLINK_COMMON_H */ - diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 53e93cce0..1aefe6135 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -1,77 +1,77 @@ /* - Copyright (c) 2010 "Capt'ns Missing Link" Authors. All rights reserved. - Use of this source code is governed by a BSD-style - license that can be found in the LICENSE file. - - A linux stlink access demo. The purpose of this file is to mitigate the usual - "reinventing the wheel" force by incompatible licenses and give you an idea, - how to access the stlink device. That doesn't mean you should be a free-loader - and not contribute your improvements to this code. - - Author: Martin Capitanio - The stlink related constants kindly provided by Oliver Spencer (OpenOCD) - for use in a GPL compatible license. - - Tested compatibility: linux, gcc >= 4.3.3 - - The communication is based on standard USB mass storage device - BOT (Bulk Only Transfer) - - Endpoint 1: BULK_IN, 64 bytes max - - Endpoint 2: BULK_OUT, 64 bytes max - - All CBW transfers are ordered with the LSB (byte 0) first (little endian). - Any command must be answered before sending the next command. - Each USB transfer must complete in less than 1s. - - SB Device Class Definition for Mass Storage Devices: - www.usb.org/developers/devclass_docs/usbmassbulk_10.pdf - - dt - Data Transfer (IN/OUT) - CBW - Command Block Wrapper - CSW - Command Status Wrapper - RFU - Reserved for Future Use - - Originally, this driver used scsi pass through commands, which required the - usb-storage module to be loaded, providing the /dev/sgX links. The USB mass - storage implementation on the STLinkv1 is however terribly broken, and it can - take many minutes for the kernel to give up. - - However, in Nov 2011, the scsi pass through was replaced by raw libusb, so - instead of having to let usb-storage struggle with the device, and also greatly - limiting the portability of the driver, you can now tell usb-storage to simply - ignore this device completely. - - usb-storage.quirks - http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob_plain;f=Documentation/kernel-parameters.txt - Each entry has the form VID:PID:Flags where VID and PID are Vendor and Product - ID values (4-digit hex numbers) and Flags is a set of characters, each corresponding - to a common usb-storage quirk flag as follows: - - a = SANE_SENSE (collect more than 18 bytes of sense data); - b = BAD_SENSE (don't collect more than 18 bytes of sense data); - c = FIX_CAPACITY (decrease the reported device capacity by one sector); - h = CAPACITY_HEURISTICS (decrease the reported device capacity by one sector if the number is odd); - i = IGNORE_DEVICE (don't bind to this device); - l = NOT_LOCKABLE (don't try to lock and unlock ejectable media); - m = MAX_SECTORS_64 (don't transfer more than 64 sectors = 32 KB at a time); - o = CAPACITY_OK (accept the capacity reported by the device); - r = IGNORE_RESIDUE (the device reports bogus residue values); - s = SINGLE_LUN (the device has only one Logical Unit); - w = NO_WP_DETECT (don't test whether the medium is write-protected). - - Example: quirks=0419:aaf5:rl,0421:0433:rc - http://permalink.gmane.org/gmane.linux.usb.general/35053 - - For the stlinkv1, you just want the following - - modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i - - Equivalently, you can add a line saying - - options usb-storage quirks=483:3744:i - - to your /etc/modprobe.conf or /etc/modprobe.d/local.conf (or add the "quirks=..." - part to an existing options line for usb-storage). + * Copyright (c) 2010 "Capt'ns Missing Link" Authors. All rights reserved. + * Use of this source code is governed by a BSD-style + * license that can be found in the LICENSE file. + * + * A linux stlink access demo. The purpose of this file is to mitigate the usual + * "reinventing the wheel" force by incompatible licenses and give you an idea, + * how to access the stlink device. That doesn't mean you should be a free-loader + * and not contribute your improvements to this code. + * + * Author: Martin Capitanio + * The stlink related constants kindly provided by Oliver Spencer (OpenOCD) + * for use in a GPL compatible license. + * + * Tested compatibility: linux, gcc >= 4.3.3 + * + * The communication is based on standard USB mass storage device + * BOT (Bulk Only Transfer) + * - Endpoint 1: BULK_IN, 64 bytes max + * - Endpoint 2: BULK_OUT, 64 bytes max + * + * All CBW transfers are ordered with the LSB (byte 0) first (little endian). + * Any command must be answered before sending the next command. + * Each USB transfer must complete in less than 1s. + * + * SB Device Class Definition for Mass Storage Devices: + * www.usb.org/developers/devclass_docs/usbmassbulk_10.pdf + * + * dt - Data Transfer (IN/OUT) + * CBW - Command Block Wrapper + * CSW - Command Status Wrapper + * RFU - Reserved for Future Use + * + * Originally, this driver used scsi pass through commands, which required the + * usb-storage module to be loaded, providing the /dev/sgX links. The USB mass + * storage implementation on the STLinkv1 is however terribly broken, and it can + * take many minutes for the kernel to give up. + * + * However, in Nov 2011, the scsi pass through was replaced by raw libusb, so + * instead of having to let usb-storage struggle with the device, and also greatly + * limiting the portability of the driver, you can now tell usb-storage to simply + * ignore this device completely. + * + * usb-storage.quirks + * http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob_plain;f=Documentation/kernel-parameters.txt + * Each entry has the form VID:PID:Flags where VID and PID are Vendor and Product + * ID values (4-digit hex numbers) and Flags is a set of characters, each corresponding + * to a common usb-storage quirk flag as follows: + * + * a = SANE_SENSE (collect more than 18 bytes of sense data); + * b = BAD_SENSE (don't collect more than 18 bytes of sense data); + * c = FIX_CAPACITY (decrease the reported device capacity by one sector); + * h = CAPACITY_HEURISTICS (decrease the reported device capacity by one sector if the number is odd); + * i = IGNORE_DEVICE (don't bind to this device); + * l = NOT_LOCKABLE (don't try to lock and unlock ejectable media); + * m = MAX_SECTORS_64 (don't transfer more than 64 sectors = 32 KB at a time); + * o = CAPACITY_OK (accept the capacity reported by the device); + * r = IGNORE_RESIDUE (the device reports bogus residue values); + * s = SINGLE_LUN (the device has only one Logical Unit); + * w = NO_WP_DETECT (don't test whether the medium is write-protected). + * + * Example: quirks=0419:aaf5:rl,0421:0433:rc + * http://permalink.gmane.org/gmane.linux.usb.general/35053 + * + * For the stlinkv1, you just want the following + * + * modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i + * + * Equivalently, you can add a line saying + * + * options usb-storage quirks=483:3744:i + * + * to your /etc/modprobe.conf or /etc/modprobe.d/local.conf (or add the "quirks=..." + * part to an existing options line for usb-storage). */ @@ -108,7 +108,8 @@ static void clear_cdb(struct stlink_libsg *sl) { /** * Close and free any _backend_ related information... * @param sl - */void _stlink_sg_close(stlink_t *sl) { + */ +void _stlink_sg_close(stlink_t *sl) { if (sl) { struct stlink_libsg *slsg = sl->backend_data; libusb_close(slsg->usb_handle); @@ -126,7 +127,7 @@ static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t end int try = 0; do { ret = libusb_bulk_transfer(handle, endpoint, (unsigned char *)&csw, sizeof(csw), - &transferred, SG_TIMEOUT_MSEC); + &transferred, SG_TIMEOUT_MSEC); if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(handle, endpoint); } @@ -175,11 +176,11 @@ static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { * @param lun * @param flags * @param expected_rx_size - * @return + * @return */ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, - uint8_t *cdb, uint8_t cdb_length, - uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { + uint8_t *cdb, uint8_t cdb_length, + uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { DLOG("Sending usb m-s cmd: cdblen:%d, rxsize=%d\n", cdb_length, expected_rx_size); dump_CDB_command(cdb, cdb_length); @@ -211,13 +212,13 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint // Now the actual CDB request assert(cdb_length <= CDB_SL); memcpy(&(c_buf[i]), cdb, cdb_length); - + int sending_length = STLINK_SG_SIZE; - + // send.... do { ret = libusb_bulk_transfer(handle, endpoint_out, c_buf, sending_length, - &real_transferred, SG_TIMEOUT_MSEC); + &real_transferred, SG_TIMEOUT_MSEC); if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(handle, endpoint_out); } @@ -237,7 +238,7 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint * @param endpoint_in * @param endpoint_out */ -static void + static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_out) { DLOG("Fetching sense...\n"); @@ -248,7 +249,7 @@ get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_ou cdb[0] = REQUEST_SENSE; cdb[4] = REQUEST_SENSE_LENGTH; uint32_t tag = send_usb_mass_storage_command(handle, endpoint_out, cdb, sizeof(cdb), 0, - LIBUSB_ENDPOINT_IN, REQUEST_SENSE_LENGTH); + LIBUSB_ENDPOINT_IN, REQUEST_SENSE_LENGTH); if (tag == 0) { WLOG("refusing to send request sense with tag 0\n"); return; @@ -259,7 +260,7 @@ get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_ou int try = 0; do { ret = libusb_bulk_transfer(handle, endpoint_in, sense, sizeof(sense), - &transferred, SG_TIMEOUT_MSEC); + &transferred, SG_TIMEOUT_MSEC); if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(handle, endpoint_in); } @@ -289,20 +290,20 @@ get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_ou * Just send a buffer on an endpoint, no questions asked. * Handles repeats, and time outs. Also handles reading status reports and sense * @param handle libusb device * - * @param endpoint_out sends - * @param endpoint_in used to read status reports back in + * @param endpoint_out sends + * @param endpoint_in used to read status reports back in * @param cbuf what to send * @param length how much to send * @return number of bytes actually sent, or -1 for failures. */ int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, - unsigned char endpoint_in, unsigned char *cbuf, unsigned int length) { + unsigned char endpoint_in, unsigned char *cbuf, unsigned int length) { int ret; int real_transferred; int try = 0; do { ret = libusb_bulk_transfer(handle, endpoint_out, cbuf, length, - &real_transferred, SG_TIMEOUT_MSEC); + &real_transferred, SG_TIMEOUT_MSEC); if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(handle, endpoint_out); } @@ -312,7 +313,7 @@ int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, WLOG("sending failed: %d\n", ret); return -1; } - + // now, swallow up the status, so that things behave nicely... uint32_t received_tag; // -ve is for my errors, 0 is good, +ve is libusb sense status bytes @@ -328,7 +329,7 @@ int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, get_sense(handle, endpoint_in, endpoint_out); return -1; } - + return real_transferred; } @@ -338,10 +339,10 @@ int stlink_q(stlink_t *sl) { //uint8_t cdb_len = 6; // FIXME varies!!! uint8_t cdb_len = 10; // FIXME varies!!! uint8_t lun = 0; // always zero... - uint32_t tag = send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, - sg->cdb_cmd_blk, cdb_len, lun, LIBUSB_ENDPOINT_IN, sl->q_len); - - + uint32_t tag = send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, + sg->cdb_cmd_blk, cdb_len, lun, LIBUSB_ENDPOINT_IN, sl->q_len); + + // now wait for our response... // length copied from stlink-usb... int rx_length = sl->q_len; @@ -350,8 +351,8 @@ int stlink_q(stlink_t *sl) { int ret; if (rx_length > 0) { do { - ret = libusb_bulk_transfer(sg->usb_handle, sg->ep_rep, sl->q_buf, rx_length, - &real_transferred, SG_TIMEOUT_MSEC); + ret = libusb_bulk_transfer(sg->usb_handle, sg->ep_rep, sl->q_buf, rx_length, + &real_transferred, SG_TIMEOUT_MSEC); if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(sg->usb_handle, sg->ep_req); } @@ -401,14 +402,14 @@ void stlink_stat(stlink_t *stl, char *txt) { stlink_print_data(stl); switch (stl->q_buf[0]) { - case STLINK_OK: - DLOG(" %s: ok\n", txt); - return; - case STLINK_FALSE: - DLOG(" %s: false\n", txt); - return; - default: - DLOG(" %s: unknown\n", txt); + case STLINK_OK: + DLOG(" %s: ok\n", txt); + return; + case STLINK_FALSE: + DLOG(" %s: false\n", txt); + return; + default: + DLOG(" %s: unknown\n", txt); } } @@ -471,48 +472,48 @@ void _stlink_sg_exit_dfu_mode(stlink_t *sl) { sl->q_len = 0; // ?? stlink_q(sl); /* - [135121.844564] sd 19:0:0:0: [sdb] Unhandled error code - [135121.844569] sd 19:0:0:0: [sdb] Result: hostbyte=DID_ERROR driverbyte=DRIVER_OK - [135121.844574] sd 19:0:0:0: [sdb] CDB: Read(10): 28 00 00 00 10 00 00 00 08 00 - [135121.844584] end_request: I/O error, dev sdb, sector 4096 - [135121.844590] Buffer I/O error on device sdb, logical block 512 - [135130.122567] usb 6-1: reset full speed USB device using uhci_hcd and address 7 - [135130.274551] usb 6-1: device firmware changed - [135130.274618] usb 6-1: USB disconnect, address 7 - [135130.275186] VFS: busy inodes on changed media or resized disk sdb - [135130.275424] VFS: busy inodes on changed media or resized disk sdb - [135130.286758] VFS: busy inodes on changed media or resized disk sdb - [135130.292796] VFS: busy inodes on changed media or resized disk sdb - [135130.301481] VFS: busy inodes on changed media or resized disk sdb - [135130.304316] VFS: busy inodes on changed media or resized disk sdb - [135130.431113] usb 6-1: new full speed USB device using uhci_hcd and address 8 - [135130.629444] usb-storage 6-1:1.0: Quirks match for vid 0483 pid 3744: 102a1 - [135130.629492] scsi20 : usb-storage 6-1:1.0 - [135131.625600] scsi 20:0:0:0: Direct-Access STM32 PQ: 0 ANSI: 0 - [135131.627010] sd 20:0:0:0: Attached scsi generic sg2 type 0 - [135131.633603] sd 20:0:0:0: [sdb] 64000 512-byte logical blocks: (32.7 MB/31.2 MiB) - [135131.633613] sd 20:0:0:0: [sdb] Assuming Write Enabled - [135131.633620] sd 20:0:0:0: [sdb] Assuming drive cache: write through - [135131.640584] sd 20:0:0:0: [sdb] Assuming Write Enabled - [135131.640592] sd 20:0:0:0: [sdb] Assuming drive cache: write through - [135131.640609] sdb: - [135131.652634] sd 20:0:0:0: [sdb] Assuming Write Enabled - [135131.652639] sd 20:0:0:0: [sdb] Assuming drive cache: write through - [135131.652645] sd 20:0:0:0: [sdb] Attached SCSI removable disk - [135131.671536] sd 20:0:0:0: [sdb] Result: hostbyte=DID_OK driverbyte=DRIVER_SENSE - [135131.671548] sd 20:0:0:0: [sdb] Sense Key : Illegal Request [current] - [135131.671553] sd 20:0:0:0: [sdb] Add. Sense: Logical block address out of range - [135131.671560] sd 20:0:0:0: [sdb] CDB: Read(10): 28 00 00 00 f9 80 00 00 08 00 - [135131.671570] end_request: I/O error, dev sdb, sector 63872 - [135131.671575] Buffer I/O error on device sdb, logical block 7984 - [135131.678527] sd 20:0:0:0: [sdb] Result: hostbyte=DID_OK driverbyte=DRIVER_SENSE - [135131.678532] sd 20:0:0:0: [sdb] Sense Key : Illegal Request [current] - [135131.678537] sd 20:0:0:0: [sdb] Add. Sense: Logical block address out of range - [135131.678542] sd 20:0:0:0: [sdb] CDB: Read(10): 28 00 00 00 f9 80 00 00 08 00 - [135131.678551] end_request: I/O error, dev sdb, sector 63872 - ... - [135131.853565] end_request: I/O error, dev sdb, sector 4096 - */ + [135121.844564] sd 19:0:0:0: [sdb] Unhandled error code + [135121.844569] sd 19:0:0:0: [sdb] Result: hostbyte=DID_ERROR driverbyte=DRIVER_OK + [135121.844574] sd 19:0:0:0: [sdb] CDB: Read(10): 28 00 00 00 10 00 00 00 08 00 + [135121.844584] end_request: I/O error, dev sdb, sector 4096 + [135121.844590] Buffer I/O error on device sdb, logical block 512 + [135130.122567] usb 6-1: reset full speed USB device using uhci_hcd and address 7 + [135130.274551] usb 6-1: device firmware changed + [135130.274618] usb 6-1: USB disconnect, address 7 + [135130.275186] VFS: busy inodes on changed media or resized disk sdb + [135130.275424] VFS: busy inodes on changed media or resized disk sdb + [135130.286758] VFS: busy inodes on changed media or resized disk sdb + [135130.292796] VFS: busy inodes on changed media or resized disk sdb + [135130.301481] VFS: busy inodes on changed media or resized disk sdb + [135130.304316] VFS: busy inodes on changed media or resized disk sdb + [135130.431113] usb 6-1: new full speed USB device using uhci_hcd and address 8 + [135130.629444] usb-storage 6-1:1.0: Quirks match for vid 0483 pid 3744: 102a1 + [135130.629492] scsi20 : usb-storage 6-1:1.0 + [135131.625600] scsi 20:0:0:0: Direct-Access STM32 PQ: 0 ANSI: 0 + [135131.627010] sd 20:0:0:0: Attached scsi generic sg2 type 0 + [135131.633603] sd 20:0:0:0: [sdb] 64000 512-byte logical blocks: (32.7 MB/31.2 MiB) + [135131.633613] sd 20:0:0:0: [sdb] Assuming Write Enabled + [135131.633620] sd 20:0:0:0: [sdb] Assuming drive cache: write through + [135131.640584] sd 20:0:0:0: [sdb] Assuming Write Enabled + [135131.640592] sd 20:0:0:0: [sdb] Assuming drive cache: write through + [135131.640609] sdb: + [135131.652634] sd 20:0:0:0: [sdb] Assuming Write Enabled + [135131.652639] sd 20:0:0:0: [sdb] Assuming drive cache: write through + [135131.652645] sd 20:0:0:0: [sdb] Attached SCSI removable disk + [135131.671536] sd 20:0:0:0: [sdb] Result: hostbyte=DID_OK driverbyte=DRIVER_SENSE + [135131.671548] sd 20:0:0:0: [sdb] Sense Key : Illegal Request [current] + [135131.671553] sd 20:0:0:0: [sdb] Add. Sense: Logical block address out of range + [135131.671560] sd 20:0:0:0: [sdb] CDB: Read(10): 28 00 00 00 f9 80 00 00 08 00 + [135131.671570] end_request: I/O error, dev sdb, sector 63872 + [135131.671575] Buffer I/O error on device sdb, logical block 7984 + [135131.678527] sd 20:0:0:0: [sdb] Result: hostbyte=DID_OK driverbyte=DRIVER_SENSE + [135131.678532] sd 20:0:0:0: [sdb] Sense Key : Illegal Request [current] + [135131.678537] sd 20:0:0:0: [sdb] Add. Sense: Logical block address out of range + [135131.678542] sd 20:0:0:0: [sdb] CDB: Read(10): 28 00 00 00 f9 80 00 00 08 00 + [135131.678551] end_request: I/O error, dev sdb, sector 63872 + ... + [135131.853565] end_request: I/O error, dev sdb, sector 4096 + */ } void _stlink_sg_core_id(stlink_t *sl) { @@ -586,7 +587,7 @@ void _stlink_sg_read_all_regs(stlink_t *sl, reg *regp) { stlink_print_data(sl); // TODO - most of this should be re-extracted up.... - + // 0-3 | 4-7 | ... | 60-63 | 64-67 | 68-71 | 72-75 | 76-79 | 80-83 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 for (int i = 0; i < 16; i++) { @@ -630,23 +631,23 @@ void _stlink_sg_read_reg(stlink_t *sl, int r_idx, reg *regp) { DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); switch (r_idx) { - case 16: - regp->xpsr = r; - break; - case 17: - regp->main_sp = r; - break; - case 18: - regp->process_sp = r; - break; - case 19: - regp->rw = r; //XXX ?(primask, basemask etc.) - break; - case 20: - regp->rw2 = r; //XXX ?(primask, basemask etc.) - break; - default: - regp->r[r_idx] = r; + case 16: + regp->xpsr = r; + break; + case 17: + regp->main_sp = r; + break; + case 18: + regp->process_sp = r; + break; + case 19: + regp->rw = r; //XXX ?(primask, basemask etc.) + break; + case 20: + regp->rw2 = r; //XXX ?(primask, basemask etc.) + break; + default: + regp->r[r_idx] = r; } } @@ -883,7 +884,7 @@ stlink_backend_t _stlink_sg_backend = { }; static stlink_t* stlink_open(const int verbose) { - + stlink_t *sl = malloc(sizeof (stlink_t)); memset(sl, 0, sizeof(stlink_t)); struct stlink_libsg *slsg = malloc(sizeof (struct stlink_libsg)); @@ -891,16 +892,16 @@ static stlink_t* stlink_open(const int verbose) { WLOG("Couldn't malloc stlink and stlink_sg structures out of memory!\n"); return NULL; } - + if (libusb_init(&(slsg->libusb_ctx))) { WLOG("failed to init libusb context, wrong version of libraries?\n"); free(sl); free(slsg); return NULL; } - + libusb_set_debug(slsg->libusb_ctx, 3); - + slsg->usb_handle = libusb_open_device_with_vid_pid(slsg->libusb_ctx, USB_ST_VID, USB_STLINK_PID); if (slsg->usb_handle == NULL) { WLOG("Failed to find an stlink v1 by VID:PID\n"); @@ -910,10 +911,10 @@ static stlink_t* stlink_open(const int verbose) { free(slsg); return NULL; } - - // TODO + + // TODO // Could read the interface config descriptor, and assert lots of the assumptions - + // assumption: numInterfaces is always 1... if (libusb_kernel_driver_active(slsg->usb_handle, 0) == 1) { int r = libusb_detach_kernel_driver(slsg->usb_handle, 0); @@ -939,7 +940,7 @@ static stlink_t* stlink_open(const int verbose) { return NULL; } - + // assumption: bConfigurationValue is always 1 if (config != 1) { WLOG("Your stlink got into a real weird configuration, trying to fix it!\n"); @@ -967,9 +968,9 @@ static stlink_t* stlink_open(const int verbose) { // assumption: endpoint config is fixed mang. really. slsg->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; slsg->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; - + DLOG("Successfully opened stlinkv1 by libusb :)\n"); - + sl->verbose = verbose; sl->backend_data = slsg; sl->backend = &_stlink_sg_backend; @@ -991,15 +992,15 @@ stlink_t* stlink_v1_open_inner(const int verbose) { stlink_version(sl); if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { - ugly_log(UERROR, LOG_TAG, - "WTF? successfully opened, but unable to read version details. BROKEN!\n"); + ugly_log(UERROR, LOG_TAG, + "WTF? successfully opened, but unable to read version details. BROKEN!\n"); return NULL; } DLOG("Reading current mode...\n"); switch (stlink_current_mode(sl)) { case STLINK_DEV_MASS_MODE: - return sl; + return sl; case STLINK_DEV_DEBUG_MODE: // TODO go to mass? return sl; @@ -1010,12 +1011,12 @@ stlink_t* stlink_v1_open_inner(const int verbose) { DLOG("Attempting to exit DFU mode\n"); _stlink_sg_exit_dfu_mode(sl); - + // re-query device info (and retest) stlink_version(sl); if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { - ugly_log(UERROR, LOG_TAG, - "WTF? successfully opened, but unable to read version details. BROKEN!\n"); + ugly_log(UERROR, LOG_TAG, + "WTF? successfully opened, but unable to read version details. BROKEN!\n"); return NULL; } @@ -1029,7 +1030,7 @@ stlink_t* stlink_v1_open(const int verbose, int reset) { return NULL; } // by now, it _must_ be fully open and in a useful mode.... - stlink_enter_swd_mode(sl); + stlink_enter_swd_mode(sl); /* Now we are ready to read the parameters */ if (reset) { stlink_reset(sl); diff --git a/src/stlink-sg.h b/src/stlink-sg.h index f8871db99..7c0202851 100644 --- a/src/stlink-sg.h +++ b/src/stlink-sg.h @@ -1,4 +1,4 @@ -/* +/* * File: stlink-sg.h * Author: karl * @@ -11,11 +11,11 @@ #ifdef __cplusplus extern "C" { #endif - + #include #include "stlink-common.h" - - // device access + + // device access #define RDWR 0 #define RO 1 #define SG_TIMEOUT_SEC 1 // actually 1 is about 2 sec @@ -46,7 +46,7 @@ extern "C" { libusb_device_handle *usb_handle; unsigned ep_rep; unsigned ep_req; - + int sg_fd; int do_scsi_pt_err; diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 8e910bcf2..23ff19176 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -16,17 +16,17 @@ #define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) #define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) -/* code from bsd timersub.h +/* code from bsd timersub.h http://www.gnu-darwin.org/www001/src/ports/net/libevnet/work/libevnet-0.3.8/libnostd/bsd/sys/time/timersub.h.html */ #if !defined timersub #define timersub(a, b, r) do { \ - (r)->tv_sec = (a)->tv_sec - (b)->tv_sec; \ - (r)->tv_usec = (a)->tv_usec - (b)->tv_usec; \ - if ((r)->tv_usec < 0) { \ - --(r)->tv_sec; \ - (r)->tv_usec += 1000000; \ - } \ + (r)->tv_sec = (a)->tv_sec - (b)->tv_sec; \ + (r)->tv_usec = (a)->tv_usec - (b)->tv_usec; \ + if ((r)->tv_usec < 0) { \ + --(r)->tv_sec; \ + (r)->tv_usec += 1000000; \ + } \ } while (0) #endif @@ -135,14 +135,14 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, if (rxsize != 0) { /* read the response */ - + libusb_fill_bulk_transfer(handle->rep_trans, handle->usb_handle, - handle->ep_rep, rxbuf, rxsize, NULL, NULL, 0); - + handle->ep_rep, rxbuf, rxsize, NULL, NULL, 0); + if (submit_wait(handle, handle->rep_trans)) return -1; res = handle->rep_trans->actual_length; } - + if ((handle->protocoll == 1) && terminate) { /* Read the SG reply */ unsigned char sg_buf[13]; @@ -237,7 +237,7 @@ uint32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr) { unsigned char* const cmd = sl->c_buf; ssize_t size; const int rep_len = 8; - + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_JTAG_READDEBUG_32BIT; @@ -256,7 +256,7 @@ void _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { unsigned char* const cmd = sl->c_buf; ssize_t size; const int rep_len = 2; - + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_JTAG_WRITEDEBUG_32BIT; @@ -306,7 +306,7 @@ int _stlink_usb_current_mode(stlink_t * sl) { ssize_t size; int rep_len = 2; int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - + cmd[i++] = STLINK_GET_CURRENT_MODE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { @@ -582,7 +582,7 @@ void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { stlink_print_data(sl); r = read_uint32(sl->q_buf, 0); DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); - + switch (r_idx) { case 16: regp->xpsr = r; @@ -620,18 +620,18 @@ void _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); switch (r_idx) { - case 0x14: - regp->primask = (uint8_t) (r & 0xFF); - regp->basepri = (uint8_t) ((r>>8) & 0xFF); - regp->faultmask = (uint8_t) ((r>>16) & 0xFF); - regp->control = (uint8_t) ((r>>24) & 0xFF); - break; - case 0x21: - regp->fpscr = r; - break; - default: - regp->s[r_idx - 0x40] = r; - break; + case 0x14: + regp->primask = (uint8_t) (r & 0xFF); + regp->basepri = (uint8_t) ((r>>8) & 0xFF); + regp->faultmask = (uint8_t) ((r>>16) & 0xFF); + regp->control = (uint8_t) ((r>>24) & 0xFF); + break; + case 0x21: + regp->fpscr = r; + break; + default: + regp->s[r_idx - 0x40] = r; + break; } } @@ -653,18 +653,18 @@ void _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, re val = (uint8_t) (val>>24); switch (r_idx) { - case 0x1C: /* control */ - val = (((uint32_t) val) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) regp->primask); - break; - case 0x1D: /* faultmask */ - val = (((uint32_t) regp->control) << 24) | (((uint32_t) val) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) regp->primask); - break; - case 0x1E: /* basepri */ - val = (((uint32_t) regp->control) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) val) << 8) | ((uint32_t) regp->primask); - break; - case 0x1F: /* primask */ - val = (((uint32_t) regp->control) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) val); - break; + case 0x1C: /* control */ + val = (((uint32_t) val) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) regp->primask); + break; + case 0x1D: /* faultmask */ + val = (((uint32_t) regp->control) << 24) | (((uint32_t) val) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) regp->primask); + break; + case 0x1E: /* basepri */ + val = (((uint32_t) regp->control) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) val) << 8) | ((uint32_t) regp->primask); + break; + case 0x1F: /* primask */ + val = (((uint32_t) regp->control) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) val); + break; } r_idx = 0x14; @@ -750,20 +750,20 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { ugly_init(verbose); sl->backend = &_stlink_usb_backend; sl->backend_data = slu; - + sl->core_stat = STLINK_CORE_STAT_UNKNOWN; if (libusb_init(&(slu->libusb_ctx))) { WLOG("failed to init libusb context, wrong version of libraries?\n"); goto on_error; } - + libusb_device **list; int cnt = libusb_get_device_list(slu->libusb_ctx, &list); struct libusb_device_descriptor desc; int devBus =0; int devAddr=0; - + char *device = getenv("STLINK_DEVICE"); if (device) { char *c = strchr(device,':'); @@ -788,7 +788,7 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { break; } } - + if (cnt < 0) { WLOG ("Couldn't find %s ST-Link/V2 devices\n",(devBus && devAddr)?"matched":"any"); goto on_error; @@ -799,13 +799,13 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { goto on_error; } } - + libusb_free_device_list(list, 1); - + if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { int r; - + r = libusb_detach_kernel_driver(slu->usb_handle, 0); if (r<0) { WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); @@ -848,9 +848,9 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { // TODO - could use the scanning techniq from stm8 code here... slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; if (desc.idProduct == USB_STLINK_NUCLEO_PID) { - slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; + slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; } else { - slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; + slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; } slu->sg_transfer_idx = 0; @@ -860,12 +860,12 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { /* success */ if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { - ILOG("-- exit_dfu_mode\n"); - stlink_exit_dfu_mode(sl); + ILOG("-- exit_dfu_mode\n"); + stlink_exit_dfu_mode(sl); } if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { - stlink_enter_swd_mode(sl); + stlink_enter_swd_mode(sl); } if (reset) { @@ -891,7 +891,7 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { on_error: if( slu->libusb_ctx) - libusb_exit(slu->libusb_ctx); + libusb_exit(slu->libusb_ctx); if (sl != NULL) free(sl); if (slu != NULL) free(slu); return 0; diff --git a/src/stlink-usb.h b/src/stlink-usb.h index f433193c8..58b60e430 100644 --- a/src/stlink-usb.h +++ b/src/stlink-usb.h @@ -1,4 +1,4 @@ -/* +/* * File: stlink-usb.h * Author: karl * @@ -14,7 +14,7 @@ extern "C" { #include #include "stlink-common.h" - + #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 @@ -29,7 +29,7 @@ extern "C" { unsigned int sg_transfer_idx; unsigned int cmd_len; }; - + stlink_t* stlink_open_usb(const int verbose, int reset); diff --git a/src/test_sg.c b/src/test_sg.c index bc16a1c7c..dea6ffb21 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -33,196 +33,196 @@ static void __attribute__((unused)) mark_buf(stlink_t *sl) { int main(int argc, char *argv[]) { - /* Avoid unused parameter warning */ - (void)argv; - // set scpi lib debug level: 0 for no debug info, 10 for lots - - switch (argc) { - case 1: - fputs( - "\nUsage: stlink-access-test [anything at all] ...\n" - "\n*** Notice: The stlink firmware violates the USB standard.\n" - "*** Because we just use libusb, we can just tell the kernel's\n" - "*** driver to simply ignore the device...\n" - "*** Unplug the stlink and execute once as root:\n" - "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n", - stderr); - return EXIT_FAILURE; - default: + /* Avoid unused parameter warning */ + (void)argv; + // set scpi lib debug level: 0 for no debug info, 10 for lots + + switch (argc) { + case 1: + fputs( + "\nUsage: stlink-access-test [anything at all] ...\n" + "\n*** Notice: The stlink firmware violates the USB standard.\n" + "*** Because we just use libusb, we can just tell the kernel's\n" + "*** driver to simply ignore the device...\n" + "*** Unplug the stlink and execute once as root:\n" + "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n", + stderr); + return EXIT_FAILURE; + default: break; - } - - stlink_t *sl = stlink_v1_open(99, 1); - if (sl == NULL) - return EXIT_FAILURE; - - // we are in mass mode, go to swd - stlink_enter_swd_mode(sl); - stlink_current_mode(sl); - stlink_core_id(sl); - //---------------------------------------------------------------------- - - stlink_status(sl); - //stlink_force_debug(sl); - stlink_reset(sl); - stlink_status(sl); - // core system control block - stlink_read_mem32(sl, 0xe000ed00, 4); - DLOG("cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231\n", read_uint32(sl->q_buf, 0)); - // no MPU - stlink_read_mem32(sl, 0xe000ed90, 4); - DLOG("mpu type register: MPU_TYPER = got 0x%08x expect 0x0\n", read_uint32(sl->q_buf, 0)); + } + + stlink_t *sl = stlink_v1_open(99, 1); + if (sl == NULL) + return EXIT_FAILURE; + + // we are in mass mode, go to swd + stlink_enter_swd_mode(sl); + stlink_current_mode(sl); + stlink_core_id(sl); + //---------------------------------------------------------------------- + + stlink_status(sl); + //stlink_force_debug(sl); + stlink_reset(sl); + stlink_status(sl); + // core system control block + stlink_read_mem32(sl, 0xe000ed00, 4); + DLOG("cpu id base register: SCB_CPUID = got 0x%08x expect 0x411fc231\n", read_uint32(sl->q_buf, 0)); + // no MPU + stlink_read_mem32(sl, 0xe000ed90, 4); + DLOG("mpu type register: MPU_TYPER = got 0x%08x expect 0x0\n", read_uint32(sl->q_buf, 0)); #if 0 - stlink_read_mem32(sl, 0xe000edf0, 4); - DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0)); + stlink_read_mem32(sl, 0xe000edf0, 4); + DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0)); - stlink_read_mem32(sl, 0x4001100c, 4); - DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); + stlink_read_mem32(sl, 0x4001100c, 4); + DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); #endif #if 0 - // happy new year 2011: let blink all the leds - // see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs" + // happy new year 2011: let blink all the leds + // see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs" #define GPIOC 0x40011000 // port C #define GPIOC_CRH (GPIOC + 0x04) // port configuration register high #define GPIOC_ODR (GPIOC + 0x0c) // port output data register #define LED_BLUE (1<<8) // pin 8 #define LED_GREEN (1<<9) // pin 9 - stlink_read_mem32(sl, GPIOC_CRH, 4); - uint32_t io_conf = read_uint32(sl->q_buf, 0); - DLOG("GPIOC_CRH = 0x%08x\n", io_conf); - - // set: general purpose output push-pull, output mode, max speed 10 MHz. - write_uint32(sl->q_buf, 0x44444411); - stlink_write_mem32(sl, GPIOC_CRH, 4); - - memset(sl->q_buf, 0, sizeof(sl->q_buf)); - for (int i = 0; i < 100; i++) { - write_uint32(sl->q_buf, LED_BLUE | LED_GREEN); - stlink_write_mem32(sl, GPIOC_ODR, 4); - /* stlink_read_mem32(sl, 0x4001100c, 4); */ - /* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */ - usleep(100 * 1000); - - memset(sl->q_buf, 0, sizeof(sl->q_buf)); - stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo + stlink_read_mem32(sl, GPIOC_CRH, 4); + uint32_t io_conf = read_uint32(sl->q_buf, 0); + DLOG("GPIOC_CRH = 0x%08x\n", io_conf); + + // set: general purpose output push-pull, output mode, max speed 10 MHz. + write_uint32(sl->q_buf, 0x44444411); + stlink_write_mem32(sl, GPIOC_CRH, 4); + + memset(sl->q_buf, 0, sizeof(sl->q_buf)); + for (int i = 0; i < 100; i++) { + write_uint32(sl->q_buf, LED_BLUE | LED_GREEN); + stlink_write_mem32(sl, GPIOC_ODR, 4); + /* stlink_read_mem32(sl, 0x4001100c, 4); */ + /* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */ usleep(100 * 1000); - } - write_uint32(sl->q_buf, io_conf); // set old state + + memset(sl->q_buf, 0, sizeof(sl->q_buf)); + stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo + usleep(100 * 1000); + } + write_uint32(sl->q_buf, io_conf); // set old state #endif #if 0 - // TODO rtfm: stlink doesn't have flash write routines - // writing to the flash area confuses the fw for the next read access - - //stlink_read_mem32(sl, 0, 1024*6); - // flash 0x08000000 128kB - fputs("++++++++++ read a flash at 0x0800 0000\n", stderr); - stlink_read_mem32(sl, 0x08000000, 1024 * 6); //max 6kB - clear_buf(sl); - stlink_read_mem32(sl, 0x08000c00, 5); - stlink_read_mem32(sl, 0x08000c00, 4); - mark_buf(sl); - stlink_write_mem32(sl, 0x08000c00, 4); - stlink_read_mem32(sl, 0x08000c00, 256); - stlink_read_mem32(sl, 0x08000c00, 256); + // TODO rtfm: stlink doesn't have flash write routines + // writing to the flash area confuses the fw for the next read access + + //stlink_read_mem32(sl, 0, 1024*6); + // flash 0x08000000 128kB + fputs("++++++++++ read a flash at 0x0800 0000\n", stderr); + stlink_read_mem32(sl, 0x08000000, 1024 * 6); //max 6kB + clear_buf(sl); + stlink_read_mem32(sl, 0x08000c00, 5); + stlink_read_mem32(sl, 0x08000c00, 4); + mark_buf(sl); + stlink_write_mem32(sl, 0x08000c00, 4); + stlink_read_mem32(sl, 0x08000c00, 256); + stlink_read_mem32(sl, 0x08000c00, 256); #endif #if 0 - // sram 0x20000000 8kB - fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); + // sram 0x20000000 8kB + fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); memset(sl->q_buf, 0, sizeof(sl->q_buf)); mark_buf(sl); - //stlink_write_mem8(sl, 0x20000000, 16); + //stlink_write_mem8(sl, 0x20000000, 16); - //stlink_write_mem8(sl, 0x20000000, 1); - //stlink_write_mem8(sl, 0x20000001, 1); - stlink_write_mem8(sl, 0x2000000b, 3); - stlink_read_mem32(sl, 0x20000000, 16); + //stlink_write_mem8(sl, 0x20000000, 1); + //stlink_write_mem8(sl, 0x20000001, 1); + stlink_write_mem8(sl, 0x2000000b, 3); + stlink_read_mem32(sl, 0x20000000, 16); #endif #if 0 - // a not aligned mem32 access doesn't work indeed - fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); + // a not aligned mem32 access doesn't work indeed + fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); memset(sl->q_buf, 0, sizeof(sl->q_buf)); - mark_buf(sl); - stlink_write_mem32(sl, 0x20000000, 1); - stlink_read_mem32(sl, 0x20000000, 16); - mark_buf(sl); - stlink_write_mem32(sl, 0x20000001, 1); - stlink_read_mem32(sl, 0x20000000, 16); - mark_buf(sl); - stlink_write_mem32(sl, 0x2000000b, 3); - stlink_read_mem32(sl, 0x20000000, 16); - - mark_buf(sl); - stlink_write_mem32(sl, 0x20000000, 17); - stlink_read_mem32(sl, 0x20000000, 32); + mark_buf(sl); + stlink_write_mem32(sl, 0x20000000, 1); + stlink_read_mem32(sl, 0x20000000, 16); + mark_buf(sl); + stlink_write_mem32(sl, 0x20000001, 1); + stlink_read_mem32(sl, 0x20000000, 16); + mark_buf(sl); + stlink_write_mem32(sl, 0x2000000b, 3); + stlink_read_mem32(sl, 0x20000000, 16); + + mark_buf(sl); + stlink_write_mem32(sl, 0x20000000, 17); + stlink_read_mem32(sl, 0x20000000, 32); #endif #if 0 - // sram 0x20000000 8kB - fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr); + // sram 0x20000000 8kB + fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr); memset(sl->q_buf, 0, sizeof(sl->q_buf)); - mark_buf(sl); - stlink_write_mem8(sl, 0x20000000, 64); - stlink_read_mem32(sl, 0x20000000, 64); - - mark_buf(sl); - stlink_write_mem32(sl, 0x20000000, 1024 * 8); //8kB - stlink_read_mem32(sl, 0x20000000, 1024 * 6); - stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2); + mark_buf(sl); + stlink_write_mem8(sl, 0x20000000, 64); + stlink_read_mem32(sl, 0x20000000, 64); + + mark_buf(sl); + stlink_write_mem32(sl, 0x20000000, 1024 * 8); //8kB + stlink_read_mem32(sl, 0x20000000, 1024 * 6); + stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2); #endif #if 1 reg regs; - stlink_read_all_regs(sl, ®s); - stlink_step(sl); - fputs("++++++++++ write r0 = 0x12345678\n", stderr); - stlink_write_reg(sl, 0x12345678, 0); - stlink_read_reg(sl, 0, ®s); - stlink_read_all_regs(sl, ®s); + stlink_read_all_regs(sl, ®s); + stlink_step(sl); + fputs("++++++++++ write r0 = 0x12345678\n", stderr); + stlink_write_reg(sl, 0x12345678, 0); + stlink_read_reg(sl, 0, ®s); + stlink_read_all_regs(sl, ®s); #endif #if 0 - stlink_run(sl); - stlink_status(sl); + stlink_run(sl); + stlink_status(sl); - stlink_force_debug(sl); - stlink_status(sl); + stlink_force_debug(sl); + stlink_status(sl); #endif #if 0 /* read the system bootloader */ - fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr); - stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size); + fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr); + stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size); #endif #if 0 /* read the flash memory */ - fputs("\n+++++++ read flash memory\n\n", stderr); - /* mark_buf(sl); */ - stlink_read_mem32(sl, 0x08000000, 4); + fputs("\n+++++++ read flash memory\n\n", stderr); + /* mark_buf(sl); */ + stlink_read_mem32(sl, 0x08000000, 4); #endif #if 0 /* flash programming */ - fputs("\n+++++++ program flash memory\n\n", stderr); - stlink_fwrite_flash(sl, "/tmp/foobar", 0x08000000); + fputs("\n+++++++ program flash memory\n\n", stderr); + stlink_fwrite_flash(sl, "/tmp/foobar", 0x08000000); #endif #if 0 /* check file contents */ - fputs("\n+++++++ check flash memory\n\n", stderr); - { - const int res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000); - printf("_____ stlink_fcheck_flash() == %d\n", res); - } + fputs("\n+++++++ check flash memory\n\n", stderr); + { + const int res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000); + printf("_____ stlink_fcheck_flash() == %d\n", res); + } #endif #if 0 - fputs("\n+++++++ sram write and execute\n\n", stderr); - stlink_fwrite_sram(sl, "/tmp/foobar", sl->sram_base); - stlink_run_at(sl, sl->sram_base); + fputs("\n+++++++ sram write and execute\n\n", stderr); + stlink_fwrite_sram(sl, "/tmp/foobar", sl->sram_base); + stlink_run_at(sl, sl->sram_base); #endif #if 0 - stlink_run(sl); - stlink_status(sl); - //---------------------------------------------------------------------- - // back to mass mode, just in case ... - stlink_exit_debug_mode(sl); - stlink_current_mode(sl); - stlink_close(sl); + stlink_run(sl); + stlink_status(sl); + //---------------------------------------------------------------------- + // back to mass mode, just in case ... + stlink_exit_debug_mode(sl); + stlink_current_mode(sl); + stlink_close(sl); #endif - //fflush(stderr); fflush(stdout); - return EXIT_SUCCESS; + //fflush(stderr); fflush(stdout); + return EXIT_SUCCESS; } diff --git a/src/test_usb.c b/src/test_usb.c index 5e8806d29..eb8e54cdd 100644 --- a/src/test_usb.c +++ b/src/test_usb.c @@ -14,7 +14,7 @@ int main(int ac, char** av) { if (sl != NULL) { printf("-- version\n"); stlink_version(sl); - + printf("mode before doing anything: %d\n", stlink_current_mode(sl)); if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { @@ -43,7 +43,7 @@ int main(int ac, char** av) { printf("FP_CTRL\n"); stlink_read_mem32(sl, CM3_REG_FP_CTRL, 4); - + // no idea what reg this is.. */ // stlink_read_mem32(sl, 0xe000ed90, 4); // no idea what register this is... @@ -58,7 +58,7 @@ int main(int ac, char** av) { stlink_write_mem32(sl,0x200000ac, 4); stlink_read_mem32(sl, 0x200000a8, 4); stlink_read_mem32(sl, 0x200000ac, 4); - + /* Test 8 bit write */ write_uint32(sl->q_buf,0x01234567); stlink_write_mem8(sl,0x200001a8,3); @@ -79,8 +79,8 @@ int main(int ac, char** av) { stlink_write_reg(sl, 0x12345678, 15); for (off = 0; off < 21; off += 1) stlink_read_reg(sl, off, ®s); - - + + stlink_read_all_regs(sl, ®s); printf("-- status\n"); diff --git a/src/uglylogging.c b/src/uglylogging.c index c6d07f89f..a04ab3391 100644 --- a/src/uglylogging.c +++ b/src/uglylogging.c @@ -1,7 +1,7 @@ -/* - * UglyLogging. Slow, yet another wheel reinvented, but enough to make the +/* + * UglyLogging. Slow, yet another wheel reinvented, but enough to make the * rest of our code pretty enough. - * + * */ #include @@ -30,29 +30,29 @@ int ugly_log(int level, const char *tag, const char *format, ...) { tt = localtime(&mytt); fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt->tm_year + 1900, tt->tm_mon + 1, tt->tm_mday, tt->tm_hour, tt->tm_min, tt->tm_sec); switch (level) { - case UDEBUG: - fprintf(stderr, "DEBUG %s: ", tag); - break; - case UINFO: - fprintf(stderr, "INFO %s: ", tag); - break; - case UWARN: - fprintf(stderr, "WARN %s: ", tag); - break; - case UERROR: - fprintf(stderr, "ERROR %s: ", tag); - break; - case UFATAL: - fprintf(stderr, "FATAL %s: ", tag); - vfprintf(stderr, format, args); - exit(EXIT_FAILURE); - // NEVER GETS HERE!!! - break; - default: - fprintf(stderr, "%d %s: ", level, tag); - break; + case UDEBUG: + fprintf(stderr, "DEBUG %s: ", tag); + break; + case UINFO: + fprintf(stderr, "INFO %s: ", tag); + break; + case UWARN: + fprintf(stderr, "WARN %s: ", tag); + break; + case UERROR: + fprintf(stderr, "ERROR %s: ", tag); + break; + case UFATAL: + fprintf(stderr, "FATAL %s: ", tag); + vfprintf(stderr, format, args); + exit(EXIT_FAILURE); + // NEVER GETS HERE!!! + break; + default: + fprintf(stderr, "%d %s: ", level, tag); + break; } - vfprintf(stderr, format, args); + vfprintf(stderr, format, args); va_end(args); return 1; -} \ No newline at end of file +} diff --git a/src/uglylogging.h b/src/uglylogging.h index fa34d460c..5122820b9 100644 --- a/src/uglylogging.h +++ b/src/uglylogging.h @@ -1,4 +1,4 @@ -/* +/* * Ugly, low performance, configurable level, logging "framework" */ @@ -8,7 +8,7 @@ #ifdef __cplusplus extern "C" { #endif - + #define UDEBUG 90 #define UINFO 50 #define UWARN 30 From ff957bd11b5193d71f54849e06fe6deb6b72d6eb Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Wed, 9 Jul 2014 22:52:07 -0700 Subject: [PATCH 0271/1435] Remove toremove/ This directory has been awaiting deletion for 3 years. It is time to go. --- toremove/stm32l/src/stlink-hw.h | 45 - toremove/stm32l_notes/USB_traces.ods | Bin 114358 -> 0 bytes toremove/stm32l_notes/break.csv | 162 - toremove/stm32l_notes/device_connection.csv | 64 - toremove/stm32l_notes/go.csv | 3076 ------------------- toremove/stm32l_notes/notes | 15 - toremove/stm32l_notes/read_memory.csv | 260 -- toremove/stm32l_notes/step_into.csv | 194 -- 8 files changed, 3816 deletions(-) delete mode 100644 toremove/stm32l/src/stlink-hw.h delete mode 100644 toremove/stm32l_notes/USB_traces.ods delete mode 100644 toremove/stm32l_notes/break.csv delete mode 100644 toremove/stm32l_notes/device_connection.csv delete mode 100644 toremove/stm32l_notes/go.csv delete mode 100644 toremove/stm32l_notes/notes delete mode 100644 toremove/stm32l_notes/read_memory.csv delete mode 100644 toremove/stm32l_notes/step_into.csv diff --git a/toremove/stm32l/src/stlink-hw.h b/toremove/stm32l/src/stlink-hw.h deleted file mode 100644 index ca558cb6d..000000000 --- a/toremove/stm32l/src/stlink-hw.h +++ /dev/null @@ -1,45 +0,0 @@ -#ifndef STLINK_HW_H_INCLUDED -# define STLINK_HW_H_INCLUDED - -// STLINK_DEBUG_RESETSYS, etc: -#define STLINK_OK 0x80 -#define STLINK_FALSE 0x81 -#define STLINK_CORE_RUNNING 0x80 -#define STLINK_CORE_HALTED 0x81 -#define STLINK_CORE_STAT_UNKNOWN -1 - -#define STLINK_GET_VERSION 0xf1 -#define STLINK_GET_CURRENT_MODE 0xf5 - -#define STLINK_DEBUG_COMMAND 0xF2 -#define STLINK_DFU_COMMAND 0xF3 -#define STLINK_DFU_EXIT 0x07 - -// STLINK_GET_CURRENT_MODE -#define STLINK_DEV_DFU_MODE 0x00 -#define STLINK_DEV_MASS_MODE 0x01 -#define STLINK_DEV_DEBUG_MODE 0x02 -#define STLINK_DEV_UNKNOWN_MODE -1 - -// jtag mode cmds -#define STLINK_DEBUG_ENTER 0x20 -#define STLINK_DEBUG_EXIT 0x21 -#define STLINK_DEBUG_READCOREID 0x22 -#define STLINK_DEBUG_GETSTATUS 0x01 -#define STLINK_DEBUG_FORCEDEBUG 0x02 -#define STLINK_DEBUG_RESETSYS 0x03 -#define STLINK_DEBUG_READALLREGS 0x04 -#define STLINK_DEBUG_READREG 0x05 -#define STLINK_DEBUG_WRITEREG 0x06 -#define STLINK_DEBUG_READMEM_32BIT 0x07 -#define STLINK_DEBUG_WRITEMEM_32BIT 0x08 -#define STLINK_DEBUG_RUNCORE 0x09 -#define STLINK_DEBUG_STEPCORE 0x0a -#define STLINK_DEBUG_SETFP 0x0b -#define STLINK_DEBUG_WRITEMEM_8BIT 0x0d -#define STLINK_DEBUG_CLEARFP 0x0e -#define STLINK_DEBUG_WRITEDEBUGREG 0x0f -#define STLINK_DEBUG_ENTER_SWD 0xa3 -#define STLINK_DEBUG_ENTER_JTAG 0x00 - -#endif /* STLINK_HW_H_INCLUDED */ diff --git a/toremove/stm32l_notes/USB_traces.ods b/toremove/stm32l_notes/USB_traces.ods deleted file mode 100644 index 607c5f955a97ff29db036938954ba112dc9aeb08..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 114358 zcmb@vc{tR4`##>jNm>+Av}+L+8nPwPT|!bxS)!0EV;}oein63T6y;H7_30wK% z!UbGWVz{fcsOye(P2Zxcu6}Uu9aud%JA#-SsTkDPnYOY;p((wcNO>_WoCyy?G$PO0 zoiftY>OSs|LEHDpQ36|M1TjveazsXjWw;!g)L%|Uhzg2;e{S+KrPT+A!sMc-CK|xM z&_(R5(W)nBkk$3|&}iGaF?>UfRuWP#pOP3mtR=7OUe|t(DCq8NJ(eM=zXMG!ESDF2 zHq$kfCg?gysxO}F==5nHbazM1w0~*ck?(-I+>V^QYOAk@()n^IB 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z<&__UEcKxf6JxvEWb`>s3EIky>wlU;e;{Ggn;(oGr~QfL0~%?HeCdj$O9wi19)(Cw zhZwb8bei0AH*A}%L>Fg_&^0s*_+vnJ$BY>EJ=IgkVP`XLv7jY~FPd7`b<#^0V)p~w z!?{KtXRVpxWPNgc9c8BR8D~wqBwD8Pc<}74nl>nyy=LT2FC8~^NC9aTxq`$U3lzWC zl}OZXJzvZVVl?>U^6o$Ki+6m-Q5-36+uLoM5Xy?YSB&?ptGPK&iq%@)LF=e|c$; z_XtD8ffFourDLfuy7;@=vZugL%f2o#w}gbThGi! zKP&#JZNeXg`THVGMEv8ynBVn&qmTboKL4(#pN5D4*Ja=s=69{%!~7E@!I8(`*HH%I zf0b(fvlV!)-UX2RC-iqC2ncXE_4hUVFOB{aT>Wze|E`IE z@Xtw-RQ&JZ{SCJMdn<4>^7p0mFRlCuzW#eV{~V3~zqIo=82f*1rT$-9`5T=5_g3KW z?C)#;Ut0NJVC}y*_D=(GRsL@?{|VlHwe#C2|BQ@q`1bc@0<`ldnEUNAzia-vjp32= h?~ADx@!#X`E>9N^y$@X$bc9S{Z({tvzflt%yn diff --git a/toremove/stm32l_notes/break.csv b/toremove/stm32l_notes/break.csv deleted file mode 100644 index ac1fadf0a..000000000 --- a/toremove/stm32l_notes/break.csv +++ /dev/null @@ -1,162 +0,0 @@ -USBlyzer Report - -Capture List - -Type,Seq,Time,Elapsed,Duration,Request,Request Details,Raw Data,I/O,C:I:E,Device Object,Device Name,Driver Name,IRP,Status -START,0001,17:45:39.429,,,,,,,,,,,, -URB,0002,17:45:39.503,73.849 ms,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0003-0002,17:45:39.505,75.843 ms,1.995 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0004,17:45:39.505,75.897 ms,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0005-0004,17:45:39.507,77.812 ms,1.916 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0006,17:45:39.707,277.851 ms,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0007-0006,17:45:39.709,279.821 ms,1.969 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0008,17:45:39.709,279.860 ms,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0009-0008,17:45:39.711,281.806 ms,1.946 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0010,17:45:39.911,481.876 ms,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0011-0010,17:45:39.913,483.827 ms,1.952 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0012,17:45:39.913,483.872 ms,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0013-0012,17:45:39.915,485.806 ms,1.934 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0014,17:45:40.115,685.865 ms,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0015-0014,17:45:40.116,687.797 ms,1.932 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0016,17:45:40.117,687.841 ms,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0017-0016,17:45:40.118,689.796 ms,1.955 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0018,17:45:40.319,889.869 ms,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0019-0018,17:45:40.320,891.792 ms,1.922 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0020,17:45:40.321,891.830 ms,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0021-0020,17:45:40.321,892.814 ms,984 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0022,17:45:40.522,1.092884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0023-0022,17:45:40.523,1.094793 s,1.909 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0024,17:45:40.524,1.094839 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0025-0024,17:45:40.525,1.096788 s,1.949 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0026,17:45:40.725,1.295894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0027-0026,17:45:40.726,1.297784 s,1.891 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0028,17:45:40.726,1.297822 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0029-0028,17:45:40.728,1.299784 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0030,17:45:40.928,1.498899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0031-0030,17:45:40.929,1.500780 s,1.881 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0032,17:45:40.929,1.500814 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0033-0032,17:45:40.931,1.502781 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0034,17:45:41.131,1.701903 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0035-0034,17:45:41.132,1.703782 s,1.879 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0036,17:45:41.132,1.703816 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0037-0036,17:45:41.134,1.705777 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0038,17:45:41.334,1.904910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0039-0038,17:45:41.335,1.906771 s,1.862 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0040,17:45:41.335,1.906805 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0041-0040,17:45:41.337,1.908771 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0042,17:45:41.537,2.107928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0043-0042,17:45:41.538,2.109777 s,1.849 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0044,17:45:41.538,2.109811 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0045-0044,17:45:41.540,2.111768 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0046,17:45:41.540,2.111800 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 03 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 35 F0 ED 00 E0 03 00 5F A0 00 00 00 00 00 00 -URB,0047-0046,17:45:41.541,2.112767 s,967 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0048,17:45:41.541,2.112791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0049-0048,17:45:41.543,2.114766 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0050,17:45:41.543,2.114793 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0051-0050,17:45:41.544,2.115767 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0052,17:45:41.544,2.115790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0053-0052,17:45:41.546,2.117768 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 03 00 03 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 03 00 03 01 -URB,0054,17:45:41.546,2.117799 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0055-0054,17:45:41.547,2.118768 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0056,17:45:41.547,2.118793 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0057-0056,17:45:41.549,2.120767 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 03 00 03 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 03 00 03 00 -URB,0058,17:45:41.549,2.120798 s,,Bulk or Interrupt Transfer,16 bytes data,F2 41 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0059-0058,17:45:41.550,2.121767 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0060,17:45:41.550,2.121792 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0061-0060,17:45:41.552,2.123768 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0062,17:45:41.552,2.123798 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 07 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0063-0062,17:45:41.553,2.124767 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0064,17:45:41.553,2.124791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0065-0064,17:45:41.555,2.126767 s,1.977 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 01 -URB,0066,17:45:41.555,2.126794 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0067-0066,17:45:41.556,2.127767 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0068,17:45:41.556,2.127791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0069-0068,17:45:41.558,2.129767 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0070,17:45:41.558,2.129794 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 08 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0071-0070,17:45:41.559,2.130767 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0072,17:45:41.559,2.130791 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,00 00 00 01 -URB,0073-0072,17:45:41.561,2.132768 s,1.977 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0074,17:45:41.561,2.132793 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0075-0074,17:45:41.563,2.134767 s,1.974 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0076,17:45:41.563,2.134790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0077-0076,17:45:41.565,2.136767 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0078,17:45:41.565,2.136798 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 28 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 08 28 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0079-0078,17:45:41.566,2.137767 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0080,17:45:41.566,2.137791 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,00 00 00 00 -URB,0081-0080,17:45:41.568,2.139766 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0082,17:45:41.568,2.139792 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0083-0082,17:45:41.570,2.141767 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0084,17:45:41.570,2.141792 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0085-0084,17:45:41.572,2.143769 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0086,17:45:41.572,2.143800 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 38 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 08 38 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0087-0086,17:45:41.573,2.144767 s,967 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0088,17:45:41.573,2.144791 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,00 00 00 00 -URB,0089-0088,17:45:41.575,2.146766 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0090,17:45:41.575,2.146791 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0091-0090,17:45:41.577,2.148766 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0092,17:45:41.577,2.148790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0093-0092,17:45:41.579,2.150766 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0094,17:45:41.579,2.150793 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 48 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 08 48 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0095-0094,17:45:41.580,2.151767 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0096,17:45:41.580,2.151790 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,00 00 00 00 -URB,0097-0096,17:45:41.582,2.153766 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0098,17:45:41.582,2.153790 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0099-0098,17:45:41.584,2.155769 s,1.979 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0100,17:45:41.584,2.155793 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0101-0100,17:45:41.586,2.157767 s,1.974 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0102,17:45:41.586,2.157797 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 58 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 08 58 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0103-0102,17:45:41.587,2.158767 s,970 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0104,17:45:41.587,2.158791 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,00 00 00 00 -URB,0105-0104,17:45:41.589,2.160766 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0106,17:45:41.589,2.160792 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0107-0106,17:45:41.591,2.162766 s,1.974 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0108,17:45:41.591,2.162791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0109-0108,17:45:41.593,2.164767 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0110,17:45:41.593,2.164801 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3A 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0111-0110,17:45:41.594,2.165766 s,965 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0112,17:45:41.594,2.165790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0113-0112,17:45:41.599,2.170766 s,4.976 ms,Bulk or Interrupt Transfer,64 bytes data,80 00 00 01 04 00 00 00...,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 04 00 00 00 00 00 00 00 3F 00 00 00 06 00 00 00 C8 14 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 88 19 00 20 6B 01 00 20 -URB,0114,17:45:41.599,2.170777 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0115-0114,17:45:41.601,2.172761 s,1.984 ms,Bulk or Interrupt Transfer,24 bytes data,A8 0A 00 20 00 00 00 21...,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),A8 0A 00 20 00 00 00 21 88 19 00 20 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0116,17:45:41.601,2.172796 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C A8 0A 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 0C A8 0A 00 20 02 00 00 00 00 00 00 00 00 00 -URB,0117-0116,17:45:41.602,2.173763 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0118,17:45:41.602,2.173789 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0119-0118,17:45:41.604,2.175766 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,01 D0,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),01 D0 -URB,0120,17:45:41.604,2.175792 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0121-0120,17:45:41.605,2.176766 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0122,17:45:41.605,2.176794 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0123-0122,17:45:41.607,2.178767 s,1.973 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0124,17:45:41.608,2.178876 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 04 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 07 04 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0125-0124,17:45:41.608,2.179765 s,889 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0126,17:45:41.608,2.179791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0127-0126,17:45:41.610,2.181767 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 00 -URB,0128,17:45:41.610,2.181793 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0129-0128,17:45:41.611,2.182766 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,0130,17:45:41.611,2.182789 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0131-0130,17:45:41.613,2.184766 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0132,17:45:41.614,2.185390 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 94 19 00 20 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 07 94 19 00 20 04 00 00 00 00 00 00 00 00 00 -URB,0133-0132,17:45:41.614,2.185766 s,376 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,0134,17:45:41.614,2.185793 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0135-0134,17:45:41.616,2.187766 s,1.972 ms,Bulk or Interrupt Transfer,4 bytes data,1D 0E 00 20,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),1D 0E 00 20 -URB,0136,17:45:41.616,2.187794 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0137-0136,17:45:41.617,2.188767 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,0138,17:45:41.617,2.188791 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0139-0138,17:45:41.619,2.190766 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0140,17:45:41.620,2.191087 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 9C 19 00 20 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 07 9C 19 00 20 04 00 00 00 00 00 00 00 00 00 -URB,0141-0140,17:45:41.620,2.191766 s,679 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,0142,17:45:41.620,2.191790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0143-0142,17:45:41.622,2.193765 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes data,83 0F 00 20,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),83 0F 00 20 -URB,0144,17:45:41.622,2.193791 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0145-0144,17:45:41.623,2.194768 s,977 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,0146,17:45:41.623,2.194792 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0147-0146,17:45:41.625,2.196767 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0148,17:45:41.626,2.197059 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 E4 19 00 20 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 07 E4 19 00 20 04 00 00 00 00 00 00 00 00 00 -URB,0149-0148,17:45:41.626,2.197765 s,706 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,0150,17:45:41.626,2.197789 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0151-0150,17:45:41.628,2.199766 s,1.977 ms,Bulk or Interrupt Transfer,4 bytes data,67 14 00 20,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),67 14 00 20 -URB,0152,17:45:41.628,2.199792 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0153-0152,17:45:41.629,2.200766 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,0154,17:45:41.629,2.200790 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0155-0154,17:45:41.631,2.202765 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 - -This report was generated by USBlyzer http://www.usblyzer.com/ diff --git a/toremove/stm32l_notes/device_connection.csv b/toremove/stm32l_notes/device_connection.csv deleted file mode 100644 index e2de02dd8..000000000 --- a/toremove/stm32l_notes/device_connection.csv +++ /dev/null @@ -1,64 +0,0 @@ -USBlyzer Report - -Capture List - -Type,Seq,Time,Elapsed,Duration,Request,Request Details,Raw Data,I/O,C:I:E,Device Object,Device Name,Driver Name,IRP,Status -START,0001,16:01:27.054,,,,,,,,,,,, -Create,0002,16:05:07.963,220.908617 s,,Create,ST-LinkUpgrade.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA8002864690h, -Create,0003-0002,16:05:07.963,220.908641 s,24 us,Create,ST-LinkUpgrade.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA8002864690h,Success -URB,0004,16:05:07.963,220.908764 s,,Bulk or Interrupt Transfer,16 bytes data,F1 80 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,,F1 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0005-0004,16:05:07.965,220.910795 s,2.032 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,Success (Success) -URB,0006,16:05:07.965,220.910876 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h, -URB,0007-0006,16:05:07.968,220.912779 s,1.903 ms,Bulk or Interrupt Transfer,6 bytes data,23 80 83 04 48 37,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,Success (Success),23 80 83 04 48 37 -URB,0008,16:05:07.968,220.912813 s,,Bulk or Interrupt Transfer,16 bytes data,F5 00 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,,F5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0009-0008,16:05:07.968,220.913777 s,965 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,Success (Success) -URB,0010,16:05:07.968,220.913800 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h, -URB,0011-0010,16:05:07.970,220.914777 s,978 us,Bulk or Interrupt Transfer,2 bytes data,00 01,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,Success (Success),00 01 -URB,0012,16:05:07.970,220.914803 s,,Bulk or Interrupt Transfer,16 bytes data,F3 08 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,,F3 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0013-0012,16:05:07.970,220.915778 s,975 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,Success (Success) -URB,0014,16:05:07.970,220.915799 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h, -URB,0015-0014,16:05:07.973,220.917778 s,1.979 ms,Bulk or Interrupt Transfer,20 bytes data,40 00 FF FF 4A 82 34 06...,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,Success (Success),40 00 FF FF 4A 82 34 06 53 FF 68 06 48 82 57 51 07 38 12 87 -URB,0016,16:05:07.973,220.917815 s,,Bulk or Interrupt Transfer,16 bytes data,F1 80 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,,F1 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0017-0016,16:05:07.973,220.918777 s,963 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA8002864690h,Success (Success) -URB,0018,16:05:07.973,220.918799 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h, -URB,0019-0018,16:05:07.975,220.920778 s,1.978 ms,Bulk or Interrupt Transfer,6 bytes data,23 80 83 04 48 37,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80027BBA50h,Success (Success),23 80 83 04 48 37 -Cleanup,0020,16:07:29.920,362.863914 s,,Cleanup,ST-LinkUpgrade.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80038D78F0h, -Cleanup,0021-0020,16:07:29.920,362.863990 s,76 us,Cleanup,ST-LinkUpgrade.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80038D78F0h,Success -Close,0022,16:07:29.920,362.863994 s,,Close,,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80038D78F0h, -Close,0023-0022,16:07:29.920,362.863998 s,4 us,Close,,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80038D78F0h,Success -Create,0024,16:07:43.292,376.235500 s,,Create,ST-LINK_gdbserver.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80067CE0D0h, -Create,0025-0024,16:07:43.292,376.235525 s,24 us,Create,ST-LINK_gdbserver.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80067CE0D0h,Success -URB,0026,16:07:43.292,376.235653 s,,Bulk or Interrupt Transfer,16 bytes data,F1 80 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,,F1 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0027-0026,16:07:43.294,376.237673 s,2.020 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,Success (Success) -URB,0028,16:07:43.294,376.237720 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h, -URB,0029-0028,16:07:43.296,376.239653 s,1.933 ms,Bulk or Interrupt Transfer,6 bytes data,23 80 83 04 48 37,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),23 80 83 04 48 37 -URB,0030,16:07:43.296,376.239690 s,,Bulk or Interrupt Transfer,16 bytes data,F5 00 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,,F5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0031-0030,16:07:43.297,376.240648 s,959 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,Success (Success) -URB,0032,16:07:43.297,376.240676 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h, -URB,0033-0032,16:07:43.299,376.242648 s,1.972 ms,Bulk or Interrupt Transfer,2 bytes data,00 01,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),00 01 -URB,0034,16:07:43.299,376.242680 s,,Bulk or Interrupt Transfer,16 bytes data,F3 07 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,,F3 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0035-0034,16:07:43.300,376.243647 s,967 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80067CE0D0h,Success (Success) -URB,0036,16:07:43.301,376.244139 s,,Bulk or Interrupt Transfer,16 bytes data,F2 30 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,,F2 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0037-0036,16:07:43.302,376.245654 s,1.515 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,Success (Success) -URB,0038,16:07:43.302,376.245686 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h, -URB,0039-0038,16:07:43.304,376.247651 s,1.965 ms,Bulk or Interrupt Transfer,2 bytes data,04 00,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),04 00 -URB,0040,16:07:43.305,376.247993 s,,Bulk or Interrupt Transfer,16 bytes data,F2 32 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,,F2 32 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0041-0040,16:07:43.305,376.248654 s,661 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,Success (Success) -URB,0042,16:07:43.305,376.248685 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h, -URB,0043-0042,16:07:43.307,376.250665 s,1.979 ms,Bulk or Interrupt Transfer,2 bytes data,04 00,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),04 00 -URB,0044,16:07:43.307,376.250708 s,,Bulk or Interrupt Transfer,16 bytes data,F5 00 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,,F5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0045-0044,16:07:43.309,376.251656 s,948 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,Success (Success) -URB,0046,16:07:43.309,376.251689 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h, -URB,0047-0046,16:07:43.310,376.253650 s,1.961 ms,Bulk or Interrupt Transfer,2 bytes data,02 00,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),02 00 -URB,0048,16:07:43.310,376.253680 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,,F2 35 F0 ED 00 E0 00 00 5F A0 00 00 00 00 00 00 -URB,0049-0048,16:07:43.311,376.254647 s,967 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,Success (Success) -URB,0050,16:07:43.311,376.254672 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h, -URB,0051-0050,16:07:43.314,376.256648 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,08 00,in,01:00:81,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80070C7170h,Success (Success),08 00 -URB,0052,16:07:43.314,376.256675 s,,Bulk or Interrupt Transfer,16 bytes data,F2 21 00 00 00 00 00 00...,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,,F2 21 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0053-0052,16:07:43.314,376.257649 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800393B2F0h,USBPDO-7,usbhub,FFFFFA80047EC010h,Success (Success) -Cleanup,0054,16:07:43.314,376.257674 s,,Cleanup,ST-LINK_gdbserver.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80047EC010h, -Cleanup,0055-0054,16:07:43.314,376.257719 s,45 us,Cleanup,ST-LINK_gdbserver.exe,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80047EC010h,Success -Close,0056,16:07:43.314,376.257722 s,,Close,,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80047EC010h, -Close,0057-0056,16:07:43.314,376.257726 s,3 us,Close,,,,,FFFFFA800373FB40h,,WinUsb,FFFFFA80047EC010h,Success - -This report was generated by USBlyzer http://www.usblyzer.com/ diff --git a/toremove/stm32l_notes/go.csv b/toremove/stm32l_notes/go.csv deleted file mode 100644 index 1ca10439d..000000000 --- a/toremove/stm32l_notes/go.csv +++ /dev/null @@ -1,3076 +0,0 @@ -USBlyzer Report - -Capture List - -Type,Seq,Time,Elapsed,Duration,Request,Request Details,Raw Data,I/O,C:I:E,Device Object,Device Name,Driver Name,IRP,Status -START,0001,17:43:38.035,,,,,,,,,,,, -URB,0002,17:44:01.236,23.201589 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 0C 40 11 00 20 02 00 00 00 00 00 00 00 00 00 -URB,0003-0002,17:44:01.238,23.203514 s,1.924 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,0004,17:44:01.238,23.203558 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0005-0004,17:44:01.240,23.205498 s,1.940 ms,Bulk or Interrupt Transfer,2 bytes data,70 47,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),70 47 -URB,0006,17:44:01.240,23.205532 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0007-0006,17:44:01.241,23.206491 s,960 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0008,17:44:01.241,23.206517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0009-0008,17:44:01.243,23.208494 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0010,17:44:01.243,23.208535 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 07 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0011-0010,17:44:01.244,23.209491 s,956 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0012,17:44:01.244,23.209515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0013-0012,17:44:01.246,23.211490 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 01 -URB,0014,17:44:01.246,23.211517 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0015-0014,17:44:01.247,23.212490 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0016,17:44:01.247,23.212515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0017-0016,17:44:01.249,23.214501 s,1.986 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0018,17:44:01.249,23.214544 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 08 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0019-0018,17:44:01.250,23.215493 s,949 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0020,17:44:01.250,23.215522 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,00 00 00 01 -URB,0021-0020,17:44:01.252,23.217580 s,2.058 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0022,17:44:01.252,23.217648 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0023-0022,17:44:01.254,23.219490 s,1.843 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0024,17:44:01.254,23.219518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0025-0024,17:44:01.256,23.221489 s,1.971 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0026,17:44:01.256,23.221519 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 28 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 08 28 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0027-0026,17:44:01.257,23.222489 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0028,17:44:01.257,23.222512 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,00 00 00 00 -URB,0029-0028,17:44:01.259,23.224489 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0030,17:44:01.259,23.224513 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0031-0030,17:44:01.261,23.226489 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0032,17:44:01.261,23.226512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0033-0032,17:44:01.263,23.228488 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0034,17:44:01.263,23.228515 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 38 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 08 38 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0035-0034,17:44:01.264,23.229489 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0036,17:44:01.264,23.229513 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,00 00 00 00 -URB,0037-0036,17:44:01.266,23.231489 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0038,17:44:01.266,23.231523 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0039-0038,17:44:01.268,23.233488 s,1.965 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0040,17:44:01.268,23.233512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0041-0040,17:44:01.270,23.235488 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0042,17:44:01.270,23.235514 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 48 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 08 48 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0043-0042,17:44:01.271,23.236487 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0044,17:44:01.271,23.236510 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,00 00 00 00 -URB,0045-0044,17:44:01.272,23.237487 s,977 us,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0046,17:44:01.272,23.237512 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0047-0046,17:44:01.273,23.238488 s,976 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0048,17:44:01.273,23.238512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0049-0048,17:44:01.275,23.240489 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0050,17:44:01.275,23.240516 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 58 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 08 58 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0051-0050,17:44:01.276,23.241489 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0052,17:44:01.276,23.241511 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,00 00 00 00 -URB,0053-0052,17:44:01.278,23.243487 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0054,17:44:01.278,23.243511 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0055-0054,17:44:01.279,23.244488 s,978 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0056,17:44:01.279,23.244513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0057-0056,17:44:01.281,23.246491 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0058,17:44:01.281,23.246535 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 01 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 35 F0 ED 00 E0 01 00 5F A0 00 00 00 00 00 00 -URB,0059-0058,17:44:01.282,23.247488 s,953 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0060,17:44:01.282,23.247512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0061-0060,17:44:01.284,23.249527 s,2.015 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0062,17:44:01.285,23.249896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0063-0062,17:44:01.285,23.250503 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0064,17:44:01.285,23.250533 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0065-0064,17:44:01.287,23.252495 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0066,17:44:01.288,23.252884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0067-0066,17:44:01.288,23.253503 s,619 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0068,17:44:01.288,23.253528 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0069-0068,17:44:01.290,23.255495 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0070,17:44:01.291,23.255892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0071-0070,17:44:01.291,23.256498 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0072,17:44:01.291,23.256526 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0073-0072,17:44:01.293,23.258496 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0074,17:44:01.294,23.258894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0075-0074,17:44:01.294,23.259494 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0076,17:44:01.294,23.259523 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0077-0076,17:44:01.296,23.261494 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0078,17:44:01.297,23.261891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0079-0078,17:44:01.297,23.262495 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0080,17:44:01.297,23.262521 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0081-0080,17:44:01.299,23.264495 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0082,17:44:01.300,23.264888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0083-0082,17:44:01.300,23.265494 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0084,17:44:01.300,23.265520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0085-0084,17:44:01.302,23.267581 s,2.061 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0086,17:44:01.303,23.267906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0087-0086,17:44:01.303,23.268497 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0088,17:44:01.303,23.268527 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0089-0088,17:44:01.305,23.270494 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0090,17:44:01.306,23.270899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0091-0090,17:44:01.306,23.271494 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0092,17:44:01.306,23.271522 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0093-0092,17:44:01.308,23.273498 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0094,17:44:01.309,23.273886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0095-0094,17:44:01.309,23.274495 s,609 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0096,17:44:01.309,23.274520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0097-0096,17:44:01.311,23.276494 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0098,17:44:01.312,23.276884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0099-0098,17:44:01.312,23.277494 s,610 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0100,17:44:01.312,23.277518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0101-0100,17:44:01.314,23.279495 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0102,17:44:01.315,23.279888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0103-0102,17:44:01.315,23.280494 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0104,17:44:01.315,23.280517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0105-0104,17:44:01.317,23.282495 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0106,17:44:01.318,23.282883 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0107-0106,17:44:01.318,23.283494 s,611 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0108,17:44:01.318,23.283517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0109-0108,17:44:01.320,23.285493 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0110,17:44:01.321,23.285893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0111-0110,17:44:01.321,23.286494 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0112,17:44:01.321,23.286520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0113-0112,17:44:01.323,23.288494 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0114,17:44:01.324,23.288887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0115-0114,17:44:01.324,23.289495 s,608 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0116,17:44:01.324,23.289519 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0117-0116,17:44:01.326,23.291494 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0118,17:44:01.327,23.291891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0119-0118,17:44:01.327,23.292493 s,602 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0120,17:44:01.327,23.292517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0121-0120,17:44:01.329,23.294494 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0122,17:44:01.330,23.294883 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0123-0122,17:44:01.330,23.295494 s,611 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0124,17:44:01.330,23.295517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0125-0124,17:44:01.332,23.297495 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0126,17:44:01.333,23.297883 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0127-0126,17:44:01.333,23.298494 s,610 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0128,17:44:01.333,23.298517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0129-0128,17:44:01.335,23.300494 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0130,17:44:01.336,23.300889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0131-0130,17:44:01.336,23.301494 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0132,17:44:01.336,23.301518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0133-0132,17:44:01.338,23.303494 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0134,17:44:01.339,23.303884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0135-0134,17:44:01.339,23.304494 s,610 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0136,17:44:01.339,23.304517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0137-0136,17:44:01.341,23.306493 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0138,17:44:01.342,23.306884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0139-0138,17:44:01.342,23.307496 s,612 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0140,17:44:01.342,23.307520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0141-0140,17:44:01.344,23.309501 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0142,17:44:01.345,23.309893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0143-0142,17:44:01.345,23.310495 s,602 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0144,17:44:01.345,23.310521 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0145-0144,17:44:01.347,23.312495 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0146,17:44:01.348,23.312884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0147-0146,17:44:01.348,23.313493 s,609 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0148,17:44:01.348,23.313517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0149-0148,17:44:01.350,23.315494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0150,17:44:01.351,23.315884 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0151-0150,17:44:01.351,23.316494 s,610 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0152,17:44:01.351,23.316517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0153-0152,17:44:01.353,23.318494 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0154,17:44:01.354,23.318886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0155-0154,17:44:01.354,23.319494 s,608 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0156,17:44:01.354,23.319518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0157-0156,17:44:01.356,23.321494 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0158,17:44:01.357,23.321890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0159-0158,17:44:01.357,23.322494 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0160,17:44:01.357,23.322517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0161-0160,17:44:01.359,23.324493 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0162,17:44:01.360,23.324886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0163-0162,17:44:01.360,23.325493 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0164,17:44:01.360,23.325517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0165-0164,17:44:01.362,23.327495 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0166,17:44:01.363,23.327887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0167-0166,17:44:01.363,23.328494 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0168,17:44:01.363,23.328517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0169-0168,17:44:01.365,23.330494 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0170,17:44:01.366,23.330888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0171-0170,17:44:01.366,23.331493 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0172,17:44:01.366,23.331518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0173-0172,17:44:01.368,23.333493 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0174,17:44:01.369,23.333885 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0175-0174,17:44:01.369,23.334497 s,612 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0176,17:44:01.369,23.334520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0177-0176,17:44:01.371,23.336494 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0178,17:44:01.372,23.336887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0179-0178,17:44:01.372,23.337493 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0180,17:44:01.372,23.337516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0181-0180,17:44:01.374,23.339494 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0182,17:44:01.375,23.339889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0183-0182,17:44:01.375,23.340492 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0184,17:44:01.375,23.340517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0185-0184,17:44:01.377,23.342494 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0186,17:44:01.378,23.342886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0187-0186,17:44:01.378,23.343493 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0188,17:44:01.378,23.343516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0189-0188,17:44:01.380,23.345494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0190,17:44:01.381,23.345888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0191-0190,17:44:01.381,23.346493 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0192,17:44:01.381,23.346516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0193-0192,17:44:01.383,23.348495 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0194,17:44:01.384,23.348887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0195-0194,17:44:01.384,23.349493 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0196,17:44:01.384,23.349516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0197-0196,17:44:01.386,23.351494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0198,17:44:01.387,23.351891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0199-0198,17:44:01.387,23.352493 s,602 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0200,17:44:01.387,23.352516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0201-0200,17:44:01.389,23.354493 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0202,17:44:01.390,23.354887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0203-0202,17:44:01.390,23.355492 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0204,17:44:01.390,23.355516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0205-0204,17:44:01.392,23.357492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0206,17:44:01.393,23.357886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0207-0206,17:44:01.393,23.358493 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0208,17:44:01.393,23.358516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0209-0208,17:44:01.395,23.360494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0210,17:44:01.396,23.360885 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0211-0210,17:44:01.396,23.361493 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0212,17:44:01.396,23.361516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0213-0212,17:44:01.398,23.363492 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0214,17:44:01.399,23.363886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0215-0214,17:44:01.399,23.364493 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0216,17:44:01.399,23.364516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0217-0216,17:44:01.401,23.366493 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0218,17:44:01.402,23.366886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0219-0218,17:44:01.402,23.367492 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0220,17:44:01.402,23.367516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0221-0220,17:44:01.404,23.369494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0222,17:44:01.405,23.369888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0223-0222,17:44:01.405,23.370492 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0224,17:44:01.405,23.370516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0225-0224,17:44:01.407,23.372492 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0226,17:44:01.408,23.372890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0227-0226,17:44:01.408,23.373492 s,602 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0228,17:44:01.408,23.373515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0229-0228,17:44:01.410,23.375494 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0230,17:44:01.411,23.375887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0231-0230,17:44:01.411,23.376492 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0232,17:44:01.411,23.376516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0233-0232,17:44:01.413,23.378492 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0234,17:44:01.414,23.378886 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0235-0234,17:44:01.414,23.379492 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0236,17:44:01.414,23.379515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0237-0236,17:44:01.416,23.381492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0238,17:44:01.417,23.381895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0239-0238,17:44:01.417,23.382503 s,607 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0240,17:44:01.417,23.382534 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0241-0240,17:44:01.419,23.384495 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0242,17:44:01.420,23.384887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0243-0242,17:44:01.420,23.385492 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0244,17:44:01.420,23.385516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0245-0244,17:44:01.422,23.387493 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0246,17:44:01.423,23.387888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0247-0246,17:44:01.423,23.388492 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0248,17:44:01.423,23.388516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0249-0248,17:44:01.425,23.390493 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0250,17:44:01.426,23.390889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0251-0250,17:44:01.426,23.391492 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0252,17:44:01.426,23.391516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0253-0252,17:44:01.428,23.393492 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0254,17:44:01.429,23.393887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0255-0254,17:44:01.429,23.394492 s,606 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0256,17:44:01.429,23.394516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0257-0256,17:44:01.431,23.396491 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0258,17:44:01.432,23.396887 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0259-0258,17:44:01.432,23.397492 s,605 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0260,17:44:01.432,23.397515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0261-0260,17:44:01.434,23.399492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0262,17:44:01.435,23.399888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0263-0262,17:44:01.435,23.400492 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0264,17:44:01.435,23.400515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0265-0264,17:44:01.437,23.402492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0266,17:44:01.438,23.402893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0267-0266,17:44:01.438,23.403492 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0268,17:44:01.438,23.403517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0269-0268,17:44:01.440,23.405492 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0270,17:44:01.441,23.405888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0271-0270,17:44:01.441,23.406492 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0272,17:44:01.441,23.406515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0273-0272,17:44:01.443,23.408491 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0274,17:44:01.444,23.408912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0275-0274,17:44:01.444,23.409490 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0276,17:44:01.444,23.409520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0277-0276,17:44:01.446,23.411489 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0278,17:44:01.447,23.411894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0279-0278,17:44:01.447,23.412492 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0280,17:44:01.447,23.412516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0281-0280,17:44:01.449,23.414492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0282,17:44:01.450,23.414888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0283-0282,17:44:01.450,23.415491 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0284,17:44:01.450,23.415515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0285-0284,17:44:01.452,23.417492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0286,17:44:01.453,23.417888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0287-0286,17:44:01.453,23.418491 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0288,17:44:01.453,23.418514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0289-0288,17:44:01.455,23.420492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0290,17:44:01.456,23.420890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0291-0290,17:44:01.456,23.421491 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0292,17:44:01.456,23.421515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0293-0292,17:44:01.458,23.423496 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0294,17:44:01.459,23.423889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0295-0294,17:44:01.459,23.424492 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0296,17:44:01.459,23.424515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0297-0296,17:44:01.461,23.426492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0298,17:44:01.462,23.426888 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0299-0298,17:44:01.462,23.427491 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0300,17:44:01.462,23.427515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0301-0300,17:44:01.464,23.429492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0302,17:44:01.465,23.429892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0303-0302,17:44:01.465,23.430491 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0304,17:44:01.465,23.430516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0305-0304,17:44:01.467,23.432491 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0306,17:44:01.468,23.432889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0307-0306,17:44:01.468,23.433491 s,602 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0308,17:44:01.468,23.433514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0309-0308,17:44:01.470,23.435492 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0310,17:44:01.471,23.435891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0311-0310,17:44:01.471,23.436491 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0312,17:44:01.471,23.436516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0313-0312,17:44:01.473,23.438493 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0314,17:44:01.474,23.438890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0315-0314,17:44:01.474,23.439491 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0316,17:44:01.474,23.439516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0317-0316,17:44:01.476,23.441492 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0318,17:44:01.477,23.441894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0319-0318,17:44:01.477,23.442492 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0320,17:44:01.477,23.442516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0321-0320,17:44:01.479,23.444490 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0322,17:44:01.480,23.444892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0323-0322,17:44:01.480,23.445491 s,599 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0324,17:44:01.480,23.445514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0325-0324,17:44:01.482,23.447492 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0326,17:44:01.483,23.447889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0327-0326,17:44:01.483,23.448490 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0328,17:44:01.483,23.448514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0329-0328,17:44:01.485,23.450491 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0330,17:44:01.486,23.450892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0331-0330,17:44:01.486,23.451490 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0332,17:44:01.486,23.451514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0333-0332,17:44:01.488,23.453491 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0334,17:44:01.489,23.453892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0335-0334,17:44:01.489,23.454492 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0336,17:44:01.489,23.454516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0337-0336,17:44:01.491,23.456490 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0338,17:44:01.492,23.456889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0339-0338,17:44:01.492,23.457494 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0340,17:44:01.492,23.457517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0341-0340,17:44:01.494,23.459491 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0342,17:44:01.495,23.459889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0343-0342,17:44:01.495,23.460490 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0344,17:44:01.495,23.460513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0345-0344,17:44:01.497,23.462490 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0346,17:44:01.498,23.462889 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0347-0346,17:44:01.498,23.463490 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0348,17:44:01.498,23.463514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0349-0348,17:44:01.500,23.465491 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0350,17:44:01.501,23.465890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0351-0350,17:44:01.501,23.466491 s,601 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0352,17:44:01.501,23.466514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0353-0352,17:44:01.503,23.468491 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0354,17:44:01.504,23.468891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0355-0354,17:44:01.504,23.469490 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0356,17:44:01.504,23.469513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0357-0356,17:44:01.506,23.471493 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0358,17:44:01.507,23.471897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0359-0358,17:44:01.507,23.472491 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0360,17:44:01.507,23.472516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0361-0360,17:44:01.509,23.474490 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0362,17:44:01.510,23.474890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0363-0362,17:44:01.510,23.475490 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0364,17:44:01.510,23.475514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0365-0364,17:44:01.512,23.477491 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0366,17:44:01.513,23.477891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0367-0366,17:44:01.513,23.478490 s,599 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0368,17:44:01.513,23.478514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0369-0368,17:44:01.515,23.480491 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0370,17:44:01.516,23.480890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0371-0370,17:44:01.516,23.481490 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0372,17:44:01.516,23.481514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0373-0372,17:44:01.518,23.483491 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0374,17:44:01.519,23.483891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0375-0374,17:44:01.519,23.484490 s,599 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0376,17:44:01.519,23.484515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0377-0376,17:44:01.521,23.486490 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0378,17:44:01.522,23.486890 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0379-0378,17:44:01.522,23.487490 s,600 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0380,17:44:01.522,23.487514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0381-0380,17:44:01.524,23.489490 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0382,17:44:01.525,23.489894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0383-0382,17:44:01.525,23.490491 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0384,17:44:01.525,23.490515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0385-0384,17:44:01.527,23.492490 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0386,17:44:01.528,23.492891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0387-0386,17:44:01.528,23.493489 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0388,17:44:01.528,23.493513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0389-0388,17:44:01.530,23.495490 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0390,17:44:01.531,23.495891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0391-0390,17:44:01.531,23.496489 s,599 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0392,17:44:01.531,23.496513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0393-0392,17:44:01.533,23.498490 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0394,17:44:01.534,23.498891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0395-0394,17:44:01.534,23.499489 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0396,17:44:01.534,23.499513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0397-0396,17:44:01.536,23.501506 s,1.992 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0398,17:44:01.537,23.501906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0399-0398,17:44:01.537,23.502503 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0400,17:44:01.537,23.502536 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0401-0400,17:44:01.539,23.504496 s,1.960 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0402,17:44:01.540,23.504897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0403-0402,17:44:01.540,23.505490 s,592 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0404,17:44:01.540,23.505514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0405-0404,17:44:01.542,23.507490 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0406,17:44:01.543,23.507891 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0407-0406,17:44:01.543,23.508489 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0408,17:44:01.543,23.508513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0409-0408,17:44:01.545,23.510491 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0410,17:44:01.546,23.510917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0411-0410,17:44:01.546,23.511487 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0412,17:44:01.546,23.511515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0413-0412,17:44:01.548,23.513484 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0414,17:44:01.549,23.513914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0415-0414,17:44:01.549,23.514487 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0416,17:44:01.549,23.514515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0417-0416,17:44:01.551,23.516490 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0418,17:44:01.552,23.516893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0419-0418,17:44:01.552,23.517489 s,596 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0420,17:44:01.552,23.517513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0421-0420,17:44:01.554,23.519493 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0422,17:44:01.555,23.519892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0423-0422,17:44:01.555,23.520491 s,598 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0424,17:44:01.555,23.520514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0425-0424,17:44:01.557,23.522490 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0426,17:44:01.558,23.522894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0427-0426,17:44:01.558,23.523489 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0428,17:44:01.558,23.523513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0429-0428,17:44:01.560,23.525489 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0430,17:44:01.561,23.525892 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0431-0430,17:44:01.561,23.526489 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0432,17:44:01.561,23.526513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0433-0432,17:44:01.563,23.528490 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0434,17:44:01.564,23.528894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0435-0434,17:44:01.564,23.529489 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0436,17:44:01.564,23.529514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0437-0436,17:44:01.566,23.531489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0438,17:44:01.567,23.531899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0439-0438,17:44:01.567,23.532489 s,590 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0440,17:44:01.567,23.532514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0441-0440,17:44:01.569,23.534489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0442,17:44:01.570,23.534893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0443-0442,17:44:01.570,23.535490 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0444,17:44:01.570,23.535513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0445-0444,17:44:01.572,23.537489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0446,17:44:01.573,23.537899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0447-0446,17:44:01.573,23.538489 s,590 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0448,17:44:01.573,23.538513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0449-0448,17:44:01.575,23.540489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0450,17:44:01.576,23.540893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0451-0450,17:44:01.576,23.541488 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0452,17:44:01.576,23.541511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0453-0452,17:44:01.578,23.543489 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0454,17:44:01.579,23.543893 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0455-0454,17:44:01.579,23.544489 s,596 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0456,17:44:01.579,23.544513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0457-0456,17:44:01.581,23.546491 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0458,17:44:01.582,23.546895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0459-0458,17:44:01.582,23.547488 s,593 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0460,17:44:01.582,23.547512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0461-0460,17:44:01.584,23.549489 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0462,17:44:01.585,23.549896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0463-0462,17:44:01.585,23.550490 s,593 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0464,17:44:01.585,23.550514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0465-0464,17:44:01.587,23.552489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0466,17:44:01.588,23.552894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0467-0466,17:44:01.588,23.553491 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0468,17:44:01.588,23.553515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0469-0468,17:44:01.590,23.555488 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0470,17:44:01.591,23.555918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8007DE2010h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0471-0470,17:44:01.591,23.556484 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8007DE2010h,Success (Success) -URB,0472,17:44:01.591,23.556512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0473-0472,17:44:01.593,23.558529 s,2.017 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0474,17:44:01.594,23.558897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0475-0474,17:44:01.594,23.559500 s,603 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0476,17:44:01.594,23.559530 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0477-0476,17:44:01.596,23.561491 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0478,17:44:01.597,23.561907 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0479-0478,17:44:01.597,23.562488 s,582 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0480,17:44:01.597,23.562513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0481-0480,17:44:01.599,23.564489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0482,17:44:01.600,23.564895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0483-0482,17:44:01.600,23.565492 s,597 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0484,17:44:01.600,23.565517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0485-0484,17:44:01.602,23.567488 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0486,17:44:01.603,23.567894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0487-0486,17:44:01.603,23.568488 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0488,17:44:01.603,23.568512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0489-0488,17:44:01.605,23.570493 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0490,17:44:01.606,23.570895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0491-0490,17:44:01.606,23.571489 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0492,17:44:01.606,23.571514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0493-0492,17:44:01.608,23.573489 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0494,17:44:01.609,23.573900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0495-0494,17:44:01.609,23.574489 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0496,17:44:01.609,23.574513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0497-0496,17:44:01.611,23.576489 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0498,17:44:01.612,23.576894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0499-0498,17:44:01.612,23.577488 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0500,17:44:01.612,23.577511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0501-0500,17:44:01.614,23.579490 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0502,17:44:01.615,23.579894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0503-0502,17:44:01.615,23.580489 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0504,17:44:01.615,23.580512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0505-0504,17:44:01.617,23.582489 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0506,17:44:01.618,23.582894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0507-0506,17:44:01.618,23.583489 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0508,17:44:01.618,23.583512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0509-0508,17:44:01.620,23.585489 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0510,17:44:01.621,23.585894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0511-0510,17:44:01.621,23.586488 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0512,17:44:01.621,23.586511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0513-0512,17:44:01.623,23.588488 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0514,17:44:01.624,23.588898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0515-0514,17:44:01.624,23.589488 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0516,17:44:01.624,23.589512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0517-0516,17:44:01.626,23.591487 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0518,17:44:01.627,23.591900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0519-0518,17:44:01.627,23.592489 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0520,17:44:01.627,23.592513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0521-0520,17:44:01.629,23.594488 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0522,17:44:01.630,23.594894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0523-0522,17:44:01.630,23.595488 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0524,17:44:01.630,23.595511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0525-0524,17:44:01.632,23.597487 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0526,17:44:01.633,23.597894 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0527-0526,17:44:01.633,23.598488 s,594 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0528,17:44:01.633,23.598512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0529-0528,17:44:01.635,23.600490 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0530,17:44:01.636,23.600905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0531-0530,17:44:01.636,23.601502 s,596 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0532,17:44:01.636,23.601530 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0533-0532,17:44:01.638,23.603487 s,1.957 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0534,17:44:01.639,23.603897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0535-0534,17:44:01.639,23.604488 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0536,17:44:01.639,23.604512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0537-0536,17:44:01.641,23.606489 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0538,17:44:01.642,23.606897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0539-0538,17:44:01.642,23.607488 s,592 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0540,17:44:01.642,23.607512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0541-0540,17:44:01.644,23.609487 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0542,17:44:01.645,23.609899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0543-0542,17:44:01.645,23.610488 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0544,17:44:01.645,23.610513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0545-0544,17:44:01.647,23.612487 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0546,17:44:01.648,23.612896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0547-0546,17:44:01.648,23.613490 s,595 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0548,17:44:01.648,23.613514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0549-0548,17:44:01.650,23.615488 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0550,17:44:01.651,23.615895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0551-0550,17:44:01.651,23.616488 s,592 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0552,17:44:01.651,23.616511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0553-0552,17:44:01.653,23.618488 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0554,17:44:01.654,23.618896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0555-0554,17:44:01.654,23.619487 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0556,17:44:01.654,23.619511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0557-0556,17:44:01.656,23.621487 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0558,17:44:01.657,23.621901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0559-0558,17:44:01.657,23.622487 s,587 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0560,17:44:01.657,23.622511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0561-0560,17:44:01.659,23.624488 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0562,17:44:01.660,23.624895 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0563-0562,17:44:01.660,23.625488 s,592 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0564,17:44:01.660,23.625511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0565-0564,17:44:01.662,23.627489 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0566,17:44:01.663,23.627896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0567-0566,17:44:01.663,23.628487 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0568,17:44:01.663,23.628510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0569-0568,17:44:01.665,23.630488 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0570,17:44:01.666,23.630898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0571-0570,17:44:01.666,23.631488 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0572,17:44:01.666,23.631512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0573-0572,17:44:01.668,23.633487 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0574,17:44:01.669,23.633896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0575-0574,17:44:01.669,23.634487 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0576,17:44:01.669,23.634511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0577-0576,17:44:01.671,23.636487 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0578,17:44:01.672,23.636896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0579-0578,17:44:01.672,23.637489 s,593 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0580,17:44:01.672,23.637512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0581-0580,17:44:01.674,23.639488 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0582,17:44:01.675,23.639897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0583-0582,17:44:01.675,23.640488 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0584,17:44:01.675,23.640511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0585-0584,17:44:01.677,23.642487 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0586,17:44:01.678,23.642896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0587-0586,17:44:01.678,23.643487 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0588,17:44:01.678,23.643510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0589-0588,17:44:01.680,23.645487 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0590,17:44:01.681,23.645896 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0591-0590,17:44:01.681,23.646487 s,590 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0592,17:44:01.681,23.646510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0593-0592,17:44:01.683,23.648487 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0594,17:44:01.684,23.648899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0595-0594,17:44:01.684,23.649487 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0596,17:44:01.684,23.649511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0597-0596,17:44:01.686,23.651487 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0598,17:44:01.687,23.651901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0599-0598,17:44:01.687,23.652487 s,585 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0600,17:44:01.687,23.652510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0601-0600,17:44:01.689,23.654489 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0602,17:44:01.690,23.654899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0603-0602,17:44:01.690,23.655490 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0604,17:44:01.690,23.655514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0605-0604,17:44:01.692,23.657487 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0606,17:44:01.693,23.657898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0607-0606,17:44:01.693,23.658488 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0608,17:44:01.693,23.658511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0609-0608,17:44:01.695,23.660486 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0610,17:44:01.696,23.660897 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0611-0610,17:44:01.696,23.661486 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0612,17:44:01.696,23.661510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0613-0612,17:44:01.698,23.663487 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0614,17:44:01.699,23.663899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0615-0614,17:44:01.699,23.664486 s,587 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0616,17:44:01.699,23.664511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0617-0616,17:44:01.701,23.666486 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0618,17:44:01.702,23.666898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0619-0618,17:44:01.702,23.667486 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0620,17:44:01.702,23.667510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0621-0620,17:44:01.704,23.669490 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0622,17:44:01.705,23.669901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0623-0622,17:44:01.705,23.670487 s,587 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0624,17:44:01.705,23.670512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0625-0624,17:44:01.707,23.672487 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0626,17:44:01.708,23.672898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0627-0626,17:44:01.708,23.673487 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0628,17:44:01.708,23.673510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0629-0628,17:44:01.710,23.675486 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0630,17:44:01.711,23.675898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0631-0630,17:44:01.711,23.676487 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0632,17:44:01.711,23.676510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0633-0632,17:44:01.713,23.678487 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0634,17:44:01.714,23.678898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0635-0634,17:44:01.714,23.679486 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0636,17:44:01.714,23.679510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0637-0636,17:44:01.716,23.681486 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0638,17:44:01.717,23.681904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0639-0638,17:44:01.717,23.682486 s,582 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0640,17:44:01.717,23.682510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0641-0640,17:44:01.719,23.684485 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0642,17:44:01.720,23.684898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0643-0642,17:44:01.720,23.685486 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0644,17:44:01.720,23.685510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0645-0644,17:44:01.722,23.687486 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0646,17:44:01.723,23.687898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0647-0646,17:44:01.723,23.688486 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0648,17:44:01.723,23.688510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0649-0648,17:44:01.725,23.690486 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0650,17:44:01.726,23.690901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0651-0650,17:44:01.726,23.691486 s,584 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0652,17:44:01.726,23.691509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0653-0652,17:44:01.728,23.693486 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0654,17:44:01.729,23.693898 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0655-0654,17:44:01.729,23.694486 s,588 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0656,17:44:01.729,23.694510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0657-0656,17:44:01.731,23.696486 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0658,17:44:01.732,23.696899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0659-0658,17:44:01.732,23.697486 s,587 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0660,17:44:01.732,23.697509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0661-0660,17:44:01.734,23.699487 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0662,17:44:01.735,23.699900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0663-0662,17:44:01.735,23.700486 s,586 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0664,17:44:01.735,23.700512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0665-0664,17:44:01.737,23.702486 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0666,17:44:01.738,23.702899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0667-0666,17:44:01.738,23.703490 s,591 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0668,17:44:01.738,23.703514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0669-0668,17:44:01.740,23.705486 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0670,17:44:01.741,23.705899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0671-0670,17:44:01.741,23.706487 s,587 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0672,17:44:01.741,23.706511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0673-0672,17:44:01.743,23.708486 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0674,17:44:01.744,23.708904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0675-0674,17:44:01.744,23.709488 s,584 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0676,17:44:01.744,23.709515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0677-0676,17:44:01.746,23.711487 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0678,17:44:01.747,23.711906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0679-0678,17:44:01.747,23.712491 s,585 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0680,17:44:01.747,23.712520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0681-0680,17:44:01.749,23.714489 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0682,17:44:01.750,23.714913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0683-0682,17:44:01.750,23.715487 s,574 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0684,17:44:01.750,23.715516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0685-0684,17:44:01.752,23.717495 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0686,17:44:01.753,23.717908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0687-0686,17:44:01.753,23.718488 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0688,17:44:01.753,23.718516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0689-0688,17:44:01.755,23.720485 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0690,17:44:01.756,23.720912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0691-0690,17:44:01.756,23.721490 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0692,17:44:01.756,23.721516 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0693-0692,17:44:01.758,23.723484 s,1.968 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0694,17:44:01.759,23.723901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0695-0694,17:44:01.759,23.724485 s,584 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0696,17:44:01.759,23.724508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0697-0696,17:44:01.761,23.726486 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0698,17:44:01.762,23.726899 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0699-0698,17:44:01.762,23.727485 s,586 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0700,17:44:01.762,23.727508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0701-0700,17:44:01.764,23.729487 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0702,17:44:01.765,23.729910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0703-0702,17:44:01.765,23.730486 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0704,17:44:01.765,23.730512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0705-0704,17:44:01.767,23.732485 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0706,17:44:01.768,23.732900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0707-0706,17:44:01.768,23.733485 s,585 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0708,17:44:01.768,23.733509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0709-0708,17:44:01.770,23.735486 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0710,17:44:01.771,23.735900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0711-0710,17:44:01.771,23.736489 s,589 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0712,17:44:01.771,23.736512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0713-0712,17:44:01.773,23.738485 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0714,17:44:01.774,23.738900 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0715-0714,17:44:01.774,23.739485 s,584 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0716,17:44:01.774,23.739508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0717-0716,17:44:01.776,23.741485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0718,17:44:01.777,23.741907 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0719-0718,17:44:01.777,23.742485 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0720,17:44:01.777,23.742509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0721-0720,17:44:01.779,23.744486 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0722,17:44:01.780,23.744906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0723-0722,17:44:01.780,23.745486 s,581 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0724,17:44:01.780,23.745512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0725-0724,17:44:01.782,23.747486 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0726,17:44:01.783,23.747908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0727-0726,17:44:01.783,23.748485 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0728,17:44:01.783,23.748511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0729-0728,17:44:01.785,23.750485 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0730,17:44:01.786,23.750906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0731-0730,17:44:01.786,23.751486 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0732,17:44:01.786,23.751510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0733-0732,17:44:01.788,23.753485 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0734,17:44:01.789,23.753901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0735-0734,17:44:01.789,23.754484 s,583 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0736,17:44:01.789,23.754507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0737-0736,17:44:01.791,23.756487 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0738,17:44:01.792,23.756901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0739-0738,17:44:01.792,23.757484 s,583 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0740,17:44:01.792,23.757508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0741-0740,17:44:01.794,23.759485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0742,17:44:01.795,23.759904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0743-0742,17:44:01.795,23.760485 s,581 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0744,17:44:01.795,23.760509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0745-0744,17:44:01.797,23.762486 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0746,17:44:01.798,23.762904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0747-0746,17:44:01.798,23.763484 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0748,17:44:01.798,23.763508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0749-0748,17:44:01.800,23.765484 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0750,17:44:01.801,23.765902 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0751-0750,17:44:01.801,23.766529 s,627 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0752,17:44:01.801,23.766553 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0753-0752,17:44:01.803,23.768492 s,1.939 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0754,17:44:01.804,23.768914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0755-0754,17:44:01.804,23.769490 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0756,17:44:01.804,23.769519 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0757-0756,17:44:01.806,23.771485 s,1.965 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0758,17:44:01.807,23.771909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0759-0758,17:44:01.807,23.772484 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0760,17:44:01.807,23.772508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0761-0760,17:44:01.809,23.774486 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0762,17:44:01.810,23.774901 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0763-0762,17:44:01.810,23.775487 s,586 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0764,17:44:01.810,23.775511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0765-0764,17:44:01.812,23.777486 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0766,17:44:01.813,23.777906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0767-0766,17:44:01.813,23.778486 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0768,17:44:01.813,23.778511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0769-0768,17:44:01.815,23.780484 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0770,17:44:01.816,23.780907 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0771-0770,17:44:01.816,23.781485 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0772,17:44:01.816,23.781508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0773-0772,17:44:01.818,23.783486 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0774,17:44:01.819,23.783904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0775-0774,17:44:01.819,23.784486 s,582 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0776,17:44:01.819,23.784509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0777-0776,17:44:01.821,23.786485 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0778,17:44:01.822,23.786902 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0779-0778,17:44:01.822,23.787483 s,581 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0780,17:44:01.822,23.787507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0781-0780,17:44:01.824,23.789485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0782,17:44:01.825,23.789906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0783-0782,17:44:01.825,23.790484 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0784,17:44:01.825,23.790509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0785-0784,17:44:01.827,23.792485 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0786,17:44:01.828,23.792902 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0787-0786,17:44:01.828,23.793484 s,582 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0788,17:44:01.828,23.793508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0789-0788,17:44:01.830,23.795484 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0790,17:44:01.831,23.795902 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0791-0790,17:44:01.831,23.796484 s,582 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0792,17:44:01.831,23.796508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0793-0792,17:44:01.833,23.798484 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0794,17:44:01.834,23.798902 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0795-0794,17:44:01.834,23.799485 s,583 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0796,17:44:01.834,23.799509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0797-0796,17:44:01.836,23.801485 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0798,17:44:01.837,23.801908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0799-0798,17:44:01.837,23.802484 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0800,17:44:01.837,23.802508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0801-0800,17:44:01.839,23.804483 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0802,17:44:01.840,23.804903 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0803-0802,17:44:01.840,23.805484 s,581 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0804,17:44:01.840,23.805507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0805-0804,17:44:01.842,23.807488 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0806,17:44:01.843,23.807910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0807-0806,17:44:01.843,23.808486 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0808,17:44:01.843,23.808511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0809-0808,17:44:01.845,23.810485 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0810,17:44:01.846,23.810909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0811-0810,17:44:01.846,23.811484 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0812,17:44:01.846,23.811508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0813-0812,17:44:01.848,23.813484 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0814,17:44:01.849,23.813904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0815-0814,17:44:01.849,23.814485 s,581 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0816,17:44:01.849,23.814508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0817-0816,17:44:01.851,23.816484 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0818,17:44:01.852,23.816905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0819-0818,17:44:01.852,23.817483 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0820,17:44:01.852,23.817508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0821-0820,17:44:01.854,23.819484 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0822,17:44:01.855,23.819903 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0823-0822,17:44:01.855,23.820483 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0824,17:44:01.855,23.820507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0825-0824,17:44:01.857,23.822484 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0826,17:44:01.858,23.822903 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0827-0826,17:44:01.858,23.823483 s,580 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0828,17:44:01.858,23.823506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0829-0828,17:44:01.860,23.825487 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0830,17:44:01.861,23.825922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0831-0830,17:44:01.861,23.826480 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0832,17:44:01.861,23.826509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0833-0832,17:44:01.863,23.828476 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0834,17:44:01.864,23.828919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0835-0834,17:44:01.864,23.829481 s,563 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0836,17:44:01.864,23.829508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0837-0836,17:44:01.866,23.831484 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0838,17:44:01.867,23.831911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0839-0838,17:44:01.867,23.832483 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0840,17:44:01.867,23.832507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0841-0840,17:44:01.869,23.834484 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0842,17:44:01.870,23.834905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0843-0842,17:44:01.870,23.835483 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0844,17:44:01.870,23.835506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0845-0844,17:44:01.872,23.837484 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0846,17:44:01.873,23.837910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0847-0846,17:44:01.873,23.838484 s,574 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0848,17:44:01.873,23.838508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0849-0848,17:44:01.875,23.840485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0850,17:44:01.876,23.840907 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0851-0850,17:44:01.876,23.841479 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0852,17:44:01.876,23.841506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0853-0852,17:44:01.878,23.843476 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0854,17:44:01.879,23.843916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0855-0854,17:44:01.879,23.844485 s,568 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0856,17:44:01.879,23.844511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0857-0856,17:44:01.881,23.846483 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0858,17:44:01.882,23.846906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0859-0858,17:44:01.882,23.847482 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0860,17:44:01.882,23.847507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0861-0860,17:44:01.884,23.849485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0862,17:44:01.885,23.849911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0863-0862,17:44:01.885,23.850482 s,571 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0864,17:44:01.885,23.850508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0865-0864,17:44:01.887,23.852483 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0866,17:44:01.888,23.852905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0867-0866,17:44:01.888,23.853482 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0868,17:44:01.888,23.853507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0869-0868,17:44:01.890,23.855484 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0870,17:44:01.891,23.855908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0871-0870,17:44:01.891,23.856483 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0872,17:44:01.891,23.856507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0873-0872,17:44:01.893,23.858485 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0874,17:44:01.894,23.858905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0875-0874,17:44:01.894,23.859483 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0876,17:44:01.894,23.859506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0877-0876,17:44:01.896,23.861483 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0878,17:44:01.897,23.861910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0879-0878,17:44:01.897,23.862483 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0880,17:44:01.897,23.862506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0881-0880,17:44:01.899,23.864482 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0882,17:44:01.900,23.864904 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0883-0882,17:44:01.900,23.865483 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0884,17:44:01.900,23.865506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0885-0884,17:44:01.902,23.867483 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0886,17:44:01.903,23.867905 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0887-0886,17:44:01.903,23.868482 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0888,17:44:01.903,23.868506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0889-0888,17:44:01.905,23.870518 s,2.013 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0890,17:44:01.906,23.870911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0891-0890,17:44:01.906,23.871488 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0892,17:44:01.906,23.871517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0893-0892,17:44:01.908,23.873487 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0894,17:44:01.909,23.873914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0895-0894,17:44:01.909,23.874486 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0896,17:44:01.909,23.874513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0897-0896,17:44:01.911,23.876488 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0898,17:44:01.912,23.876909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0899-0898,17:44:01.912,23.877482 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0900,17:44:01.912,23.877506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0901-0900,17:44:01.914,23.879483 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0902,17:44:01.915,23.879906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0903-0902,17:44:01.915,23.880482 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0904,17:44:01.915,23.880505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0905-0904,17:44:01.917,23.882483 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0906,17:44:01.918,23.882910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0907-0906,17:44:01.918,23.883483 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0908,17:44:01.918,23.883506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0909-0908,17:44:01.920,23.885483 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0910,17:44:01.921,23.885906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0911-0910,17:44:01.921,23.886482 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0912,17:44:01.921,23.886505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0913-0912,17:44:01.923,23.888483 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0914,17:44:01.924,23.888907 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0915-0914,17:44:01.924,23.889483 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0916,17:44:01.924,23.889508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0917-0916,17:44:01.926,23.891482 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0918,17:44:01.927,23.891913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0919-0918,17:44:01.927,23.892482 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0920,17:44:01.927,23.892506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0921-0920,17:44:01.929,23.894483 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0922,17:44:01.930,23.894906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0923-0922,17:44:01.930,23.895483 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0924,17:44:01.930,23.895507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0925-0924,17:44:01.932,23.897482 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0926,17:44:01.933,23.897906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0927-0926,17:44:01.933,23.898482 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0928,17:44:01.933,23.898506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0929-0928,17:44:01.935,23.900482 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0930,17:44:01.936,23.900906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0931-0930,17:44:01.936,23.901482 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0932,17:44:01.936,23.901506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0933-0932,17:44:01.938,23.903482 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0934,17:44:01.939,23.903906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0935-0934,17:44:01.939,23.904482 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0936,17:44:01.939,23.904506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0937-0936,17:44:01.941,23.906483 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0938,17:44:01.942,23.906906 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0939-0938,17:44:01.942,23.907482 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0940,17:44:01.942,23.907506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0941-0940,17:44:01.944,23.909481 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0942,17:44:01.945,23.909909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0943-0942,17:44:01.945,23.910513 s,604 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0944,17:44:01.945,23.910539 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0945-0944,17:44:01.947,23.912487 s,1.948 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0946,17:44:01.948,23.912912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0947-0946,17:44:01.948,23.913485 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0948,17:44:01.948,23.913512 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0949-0948,17:44:01.950,23.915486 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0950,17:44:01.951,23.915911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0951-0950,17:44:01.951,23.916481 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0952,17:44:01.951,23.916506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0953-0952,17:44:01.953,23.918507 s,2.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0954,17:44:01.954,23.918910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0955-0954,17:44:01.954,23.919487 s,577 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0956,17:44:01.954,23.919513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0957-0956,17:44:01.956,23.921482 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0958,17:44:01.957,23.921915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0959-0958,17:44:01.957,23.922481 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0960,17:44:01.957,23.922506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0961-0960,17:44:01.959,23.924482 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0962,17:44:01.960,23.924910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0963-0962,17:44:01.960,23.925483 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0964,17:44:01.960,23.925509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0965-0964,17:44:01.961,23.926505 s,996 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0966,17:44:01.962,23.926908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0967-0966,17:44:01.962,23.927483 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0968,17:44:01.962,23.927509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0969-0968,17:44:01.964,23.929482 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0970,17:44:01.965,23.929915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0971-0970,17:44:01.965,23.930482 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0972,17:44:01.965,23.930508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0973-0972,17:44:01.967,23.932481 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0974,17:44:01.968,23.932908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0975-0974,17:44:01.968,23.933481 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0976,17:44:01.968,23.933504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0977-0976,17:44:01.969,23.934505 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0978,17:44:01.970,23.934910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0979-0978,17:44:01.970,23.935488 s,578 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0980,17:44:01.970,23.935515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0981-0980,17:44:01.972,23.937484 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0982,17:44:01.973,23.937918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0983-0982,17:44:01.973,23.938482 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0984,17:44:01.973,23.938507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0985-0984,17:44:01.975,23.940482 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0986,17:44:01.976,23.940910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0987-0986,17:44:01.976,23.941484 s,574 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0988,17:44:01.976,23.941508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0989-0988,17:44:01.977,23.942504 s,996 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0990,17:44:01.978,23.942909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0991-0990,17:44:01.978,23.943484 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0992,17:44:01.978,23.943509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0993-0992,17:44:01.980,23.945482 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0994,17:44:01.981,23.945910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0995-0994,17:44:01.981,23.946481 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,0996,17:44:01.981,23.946505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0997-0996,17:44:01.983,23.948481 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,0998,17:44:01.984,23.948909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0999-0998,17:44:01.984,23.949481 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1000,17:44:01.984,23.949505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1001-1000,17:44:01.985,23.950503 s,998 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1002,17:44:01.986,23.950914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1003-1002,17:44:01.986,23.951485 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1004,17:44:01.986,23.951513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1005-1004,17:44:01.988,23.953482 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1006,17:44:01.989,23.953911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1007-1006,17:44:01.989,23.954481 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1008,17:44:01.989,23.954505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1009-1008,17:44:01.991,23.956480 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1010,17:44:01.992,23.956908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1011-1010,17:44:01.992,23.957484 s,576 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1012,17:44:01.992,23.957508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1013-1012,17:44:01.993,23.958504 s,996 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1014,17:44:01.994,23.958909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1015-1014,17:44:01.994,23.959485 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1016,17:44:01.994,23.959510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1017-1016,17:44:01.996,23.961481 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1018,17:44:01.997,23.961911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1019-1018,17:44:01.997,23.962481 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1020,17:44:01.997,23.962505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1021-1020,17:44:01.999,23.964481 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1022,17:44:02.000,23.964908 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1023-1022,17:44:02.000,23.965481 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1024,17:44:02.000,23.965504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1025-1024,17:44:02.001,23.966505 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1026,17:44:02.002,23.966909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1027-1026,17:44:02.002,23.967484 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1028,17:44:02.002,23.967509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1029-1028,17:44:02.004,23.969482 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1030,17:44:02.005,23.969919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1031-1030,17:44:02.005,23.970480 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1032,17:44:02.005,23.970505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1033-1032,17:44:02.007,23.972481 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1034,17:44:02.008,23.972909 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1035-1034,17:44:02.008,23.973483 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1036,17:44:02.008,23.973507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1037-1036,17:44:02.009,23.974504 s,997 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1038,17:44:02.010,23.974911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1039-1038,17:44:02.010,23.975484 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1040,17:44:02.010,23.975511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1041-1040,17:44:02.012,23.977482 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1042,17:44:02.013,23.977912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1043-1042,17:44:02.013,23.978480 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1044,17:44:02.013,23.978504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1045-1044,17:44:02.015,23.980481 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1046,17:44:02.016,23.980914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1047-1046,17:44:02.016,23.981481 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1048,17:44:02.016,23.981506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1049-1048,17:44:02.017,23.982505 s,1000 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1050,17:44:02.018,23.982911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1051-1050,17:44:02.018,23.983486 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1052,17:44:02.018,23.983513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1053-1052,17:44:02.020,23.985482 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1054,17:44:02.021,23.985915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1055-1054,17:44:02.021,23.986480 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1056,17:44:02.021,23.986505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1057-1056,17:44:02.023,23.988480 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1058,17:44:02.024,23.988911 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1059-1058,17:44:02.024,23.989483 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1060,17:44:02.024,23.989508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1061-1060,17:44:02.025,23.990504 s,996 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1062,17:44:02.026,23.990912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1063-1062,17:44:02.026,23.991487 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1064,17:44:02.026,23.991515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1065-1064,17:44:02.028,23.993482 s,1.968 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1066,17:44:02.029,23.993913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1067-1066,17:44:02.029,23.994480 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1068,17:44:02.029,23.994504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1069-1068,17:44:02.031,23.996480 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1070,17:44:02.032,23.996910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1071-1070,17:44:02.032,23.997480 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1072,17:44:02.032,23.997503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1073-1072,17:44:02.033,23.998504 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1074,17:44:02.034,23.998910 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1075-1074,17:44:02.034,23.999484 s,573 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1076,17:44:02.034,23.999510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1077-1076,17:44:02.036,24.001489 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1078,17:44:02.037,24.001970 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1079-1078,17:44:02.037,24.002479 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008264310h,Success (Success) -URB,1080,17:44:02.037,24.002521 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1081-1080,17:44:02.039,24.004477 s,1.956 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1082,17:44:02.040,24.004914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1083-1082,17:44:02.040,24.005485 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1084,17:44:02.040,24.005510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1085-1084,17:44:02.041,24.006513 s,1.003 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1086,17:44:02.042,24.006912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1087-1086,17:44:02.042,24.007486 s,574 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1088,17:44:02.042,24.007513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1089-1088,17:44:02.044,24.009483 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1090,17:44:02.045,24.009923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1091-1090,17:44:02.045,24.010480 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1092,17:44:02.045,24.010506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1093-1092,17:44:02.047,24.012481 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1094,17:44:02.048,24.012915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1095-1094,17:44:02.048,24.013481 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1096,17:44:02.048,24.013506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1097-1096,17:44:02.049,24.014511 s,1.005 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1098,17:44:02.050,24.014915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1099-1098,17:44:02.050,24.015483 s,568 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1100,17:44:02.050,24.015508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1101-1100,17:44:02.052,24.017482 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1102,17:44:02.053,24.017913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1103-1102,17:44:02.053,24.018478 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1104,17:44:02.053,24.018502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1105-1104,17:44:02.055,24.020484 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1106,17:44:02.056,24.020913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1107-1106,17:44:02.056,24.021480 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1108,17:44:02.056,24.021504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1109-1108,17:44:02.057,24.022503 s,999 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1110,17:44:02.058,24.022912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1111-1110,17:44:02.058,24.023485 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1112,17:44:02.058,24.023513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1113-1112,17:44:02.060,24.025485 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1114,17:44:02.061,24.025922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1115-1114,17:44:02.061,24.026479 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1116,17:44:02.061,24.026505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1117-1116,17:44:02.063,24.028479 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1118,17:44:02.064,24.028913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1119-1118,17:44:02.064,24.029479 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1120,17:44:02.064,24.029503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1121-1120,17:44:02.065,24.030507 s,1.003 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1122,17:44:02.066,24.030913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1123-1122,17:44:02.066,24.031483 s,571 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1124,17:44:02.066,24.031508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1125-1124,17:44:02.068,24.033482 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1126,17:44:02.069,24.033916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1127-1126,17:44:02.069,24.034480 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1128,17:44:02.069,24.034504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1129-1128,17:44:02.071,24.036483 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1130,17:44:02.072,24.036914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1131-1130,17:44:02.072,24.037479 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1132,17:44:02.072,24.037503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1133-1132,17:44:02.073,24.038504 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1134,17:44:02.074,24.038912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1135-1134,17:44:02.074,24.039481 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1136,17:44:02.074,24.039508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1137-1136,17:44:02.076,24.041483 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1138,17:44:02.077,24.041921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1139-1138,17:44:02.077,24.042479 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1140,17:44:02.077,24.042505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1141-1140,17:44:02.079,24.044478 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1142,17:44:02.080,24.044913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1143-1142,17:44:02.080,24.045479 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1144,17:44:02.080,24.045504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1145-1144,17:44:02.081,24.046502 s,999 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1146,17:44:02.082,24.046913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1147-1146,17:44:02.082,24.047481 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1148,17:44:02.082,24.047507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1149-1148,17:44:02.084,24.049479 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1150,17:44:02.085,24.049921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1151-1150,17:44:02.085,24.050478 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1152,17:44:02.085,24.050505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1153-1152,17:44:02.087,24.052479 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1154,17:44:02.088,24.052916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1155-1154,17:44:02.088,24.053479 s,563 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1156,17:44:02.088,24.053503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1157-1156,17:44:02.089,24.054503 s,999 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1158,17:44:02.090,24.054914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1159-1158,17:44:02.090,24.055484 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1160,17:44:02.090,24.055510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1161-1160,17:44:02.092,24.057479 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1162,17:44:02.093,24.057917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1163-1162,17:44:02.093,24.058478 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1164,17:44:02.093,24.058502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1165-1164,17:44:02.095,24.060479 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1166,17:44:02.096,24.060915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1167-1166,17:44:02.096,24.061479 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1168,17:44:02.096,24.061504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1169-1168,17:44:02.097,24.062502 s,998 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1170,17:44:02.098,24.062913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1171-1170,17:44:02.098,24.063482 s,569 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1172,17:44:02.098,24.063508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1173-1172,17:44:02.100,24.065480 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1174,17:44:02.101,24.065915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1175-1174,17:44:02.101,24.066478 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1176,17:44:02.101,24.066502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1177-1176,17:44:02.103,24.068479 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1178,17:44:02.104,24.068918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1179-1178,17:44:02.104,24.069479 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1180,17:44:02.104,24.069506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1181-1180,17:44:02.105,24.070506 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1182,17:44:02.106,24.070916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1183-1182,17:44:02.106,24.071486 s,570 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1184,17:44:02.106,24.071513 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1185-1184,17:44:02.108,24.073479 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1186,17:44:02.109,24.073920 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1187-1186,17:44:02.109,24.074478 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1188,17:44:02.109,24.074502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1189-1188,17:44:02.111,24.076478 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1190,17:44:02.112,24.076912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1191-1190,17:44:02.112,24.077478 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1192,17:44:02.112,24.077502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1193-1192,17:44:02.113,24.078502 s,1.000 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1194,17:44:02.114,24.078917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1195-1194,17:44:02.114,24.079482 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1196,17:44:02.114,24.079507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1197-1196,17:44:02.116,24.081480 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1198,17:44:02.117,24.081916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1199-1198,17:44:02.117,24.082479 s,563 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1200,17:44:02.117,24.082504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1201-1200,17:44:02.119,24.084478 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1202,17:44:02.120,24.084913 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1203-1202,17:44:02.120,24.085478 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1204,17:44:02.120,24.085501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1205-1204,17:44:02.121,24.086502 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1206,17:44:02.122,24.086925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1207-1206,17:44:02.122,24.087482 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1208,17:44:02.122,24.087515 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1209-1208,17:44:02.124,24.089479 s,1.964 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1210,17:44:02.125,24.089939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1211-1210,17:44:02.125,24.090481 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1212,17:44:02.125,24.090511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1213-1212,17:44:02.127,24.092478 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1214,17:44:02.128,24.092915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1215-1214,17:44:02.128,24.093479 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1216,17:44:02.128,24.093503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1217-1216,17:44:02.129,24.094510 s,1.007 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1218,17:44:02.130,24.094914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1219-1218,17:44:02.130,24.095481 s,567 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1220,17:44:02.130,24.095508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1221-1220,17:44:02.132,24.097479 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1222,17:44:02.133,24.097918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1223-1222,17:44:02.133,24.098478 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1224,17:44:02.133,24.098503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1225-1224,17:44:02.135,24.100478 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1226,17:44:02.136,24.100914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1227-1226,17:44:02.136,24.101478 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1228,17:44:02.136,24.101501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1229-1228,17:44:02.137,24.102512 s,1.011 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1230,17:44:02.138,24.102924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1231-1230,17:44:02.138,24.103484 s,559 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1232,17:44:02.138,24.103510 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1233-1232,17:44:02.140,24.105481 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1234,17:44:02.141,24.105924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1235-1234,17:44:02.141,24.106478 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1236,17:44:02.141,24.106504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1237-1236,17:44:02.143,24.108478 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1238,17:44:02.144,24.108924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1239-1238,17:44:02.144,24.109482 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1240,17:44:02.144,24.109507 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1241-1240,17:44:02.145,24.110507 s,1.000 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1242,17:44:02.146,24.110915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1243-1242,17:44:02.146,24.111480 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1244,17:44:02.146,24.111505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1245-1244,17:44:02.148,24.113480 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1246,17:44:02.149,24.113917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1247-1246,17:44:02.149,24.114477 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1248,17:44:02.149,24.114501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1249-1248,17:44:02.151,24.116478 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1250,17:44:02.152,24.116914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1251-1250,17:44:02.152,24.117478 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1252,17:44:02.152,24.117501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1253-1252,17:44:02.153,24.118501 s,1000 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1254,17:44:02.154,24.118915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1255-1254,17:44:02.154,24.119481 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1256,17:44:02.154,24.119506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1257-1256,17:44:02.156,24.121479 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1258,17:44:02.157,24.121923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1259-1258,17:44:02.157,24.122478 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1260,17:44:02.157,24.122506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1261-1260,17:44:02.159,24.124482 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1262,17:44:02.160,24.124918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1263-1262,17:44:02.160,24.125476 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1264,17:44:02.160,24.125500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1265-1264,17:44:02.161,24.126501 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1266,17:44:02.162,24.126916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1267-1266,17:44:02.162,24.127480 s,565 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1268,17:44:02.162,24.127506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1269-1268,17:44:02.164,24.129478 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1270,17:44:02.165,24.129925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1271-1270,17:44:02.165,24.130477 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1272,17:44:02.165,24.130502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1273-1272,17:44:02.167,24.132478 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1274,17:44:02.168,24.132915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1275-1274,17:44:02.168,24.133477 s,562 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1276,17:44:02.168,24.133501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1277-1276,17:44:02.169,24.134503 s,1.001 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1278,17:44:02.170,24.134916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1279-1278,17:44:02.170,24.135482 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1280,17:44:02.170,24.135508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1281-1280,17:44:02.172,24.137480 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1282,17:44:02.173,24.137939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1283-1282,17:44:02.173,24.138479 s,540 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1284,17:44:02.173,24.138508 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1285-1284,17:44:02.175,24.140477 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1286,17:44:02.176,24.140918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1287-1286,17:44:02.176,24.141476 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1288,17:44:02.176,24.141500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1289-1288,17:44:02.177,24.142502 s,1.002 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1290,17:44:02.178,24.142916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1291-1290,17:44:02.178,24.143480 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1292,17:44:02.178,24.143505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1293-1292,17:44:02.180,24.145477 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1294,17:44:02.181,24.145917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1295-1294,17:44:02.181,24.146478 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1296,17:44:02.181,24.146502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1297-1296,17:44:02.183,24.148477 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1298,17:44:02.184,24.148917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1299-1298,17:44:02.184,24.149477 s,560 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1300,17:44:02.184,24.149502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1301-1300,17:44:02.185,24.150501 s,999 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1302,17:44:02.186,24.150917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1303-1302,17:44:02.186,24.151481 s,564 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1304,17:44:02.186,24.151506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1305-1304,17:44:02.188,24.153478 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1306,17:44:02.189,24.153919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1307-1306,17:44:02.189,24.154477 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1308,17:44:02.189,24.154502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1309-1308,17:44:02.191,24.156477 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1310,17:44:02.192,24.156918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1311-1310,17:44:02.192,24.157477 s,559 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1312,17:44:02.192,24.157502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1313-1312,17:44:02.193,24.158501 s,999 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1314,17:44:02.194,24.158917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1315-1314,17:44:02.194,24.159489 s,572 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1316,17:44:02.194,24.159523 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1317-1316,17:44:02.196,24.161480 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1318,17:44:02.197,24.161929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1319-1318,17:44:02.197,24.162471 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1320,17:44:02.197,24.162494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1321-1320,17:44:02.199,24.164470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1322,17:44:02.200,24.164914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1323-1322,17:44:02.200,24.165470 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1324,17:44:02.200,24.165492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1325-1324,17:44:02.201,24.166510 s,1.018 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1326,17:44:02.202,24.166918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1327-1326,17:44:02.202,24.167473 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1328,17:44:02.202,24.167500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1329-1328,17:44:02.204,24.169485 s,1.986 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1330,17:44:02.205,24.169923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1331-1330,17:44:02.205,24.170474 s,550 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1332,17:44:02.205,24.170502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1333-1332,17:44:02.207,24.172477 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1334,17:44:02.208,24.172921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1335-1334,17:44:02.208,24.173470 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1336,17:44:02.208,24.173494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1337-1336,17:44:02.209,24.174504 s,1.009 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1338,17:44:02.210,24.174916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1339-1338,17:44:02.210,24.175474 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1340,17:44:02.210,24.175500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1341-1340,17:44:02.212,24.177474 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1342,17:44:02.213,24.177917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1343-1342,17:44:02.213,24.178470 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1344,17:44:02.213,24.178493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1345-1344,17:44:02.215,24.180469 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1346,17:44:02.216,24.180928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80085419A0h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1347-1346,17:44:02.216,24.181471 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80085419A0h,Success (Success) -URB,1348,17:44:02.216,24.181503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1349-1348,17:44:02.217,24.182498 s,994 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1350,17:44:02.218,24.182915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1351-1350,17:44:02.218,24.183472 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1352,17:44:02.218,24.183498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1353-1352,17:44:02.220,24.185472 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1354,17:44:02.221,24.185917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1355-1354,17:44:02.221,24.186471 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1356,17:44:02.221,24.186493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1357-1356,17:44:02.223,24.188469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1358,17:44:02.224,24.188916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1359-1358,17:44:02.224,24.189470 s,553 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1360,17:44:02.224,24.189494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1361-1360,17:44:02.225,24.190497 s,1.003 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1362,17:44:02.226,24.190916 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1363-1362,17:44:02.226,24.191472 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1364,17:44:02.226,24.191497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1365-1364,17:44:02.228,24.193472 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1366,17:44:02.229,24.193917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1367-1366,17:44:02.229,24.194470 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1368,17:44:02.229,24.194493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1369-1368,17:44:02.231,24.196469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1370,17:44:02.232,24.196914 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1371-1370,17:44:02.232,24.197469 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1372,17:44:02.232,24.197491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1373-1372,17:44:02.233,24.198469 s,978 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1374,17:44:02.234,24.198915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1375-1374,17:44:02.234,24.199469 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1376,17:44:02.234,24.199492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1377-1376,17:44:02.236,24.201470 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1378,17:44:02.237,24.201917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1379-1378,17:44:02.237,24.202478 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1380,17:44:02.237,24.202509 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1381-1380,17:44:02.239,24.204473 s,1.964 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1382,17:44:02.240,24.204920 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1383-1382,17:44:02.240,24.205471 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1384,17:44:02.240,24.205495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1385-1384,17:44:02.241,24.206505 s,1.010 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1386,17:44:02.242,24.206918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1387-1386,17:44:02.242,24.207493 s,575 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1388,17:44:02.242,24.207524 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1389-1388,17:44:02.244,24.209481 s,1.956 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1390,17:44:02.245,24.209930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1391-1390,17:44:02.245,24.210476 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1392,17:44:02.245,24.210503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1393-1392,17:44:02.247,24.212475 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1394,17:44:02.248,24.212919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1395-1394,17:44:02.248,24.213476 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1396,17:44:02.248,24.213499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1397-1396,17:44:02.249,24.214511 s,1.012 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1398,17:44:02.250,24.214919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1399-1398,17:44:02.250,24.215479 s,561 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1400,17:44:02.250,24.215505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1401-1400,17:44:02.252,24.217477 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1402,17:44:02.253,24.217922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1403-1402,17:44:02.253,24.218475 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1404,17:44:02.253,24.218499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1405-1404,17:44:02.255,24.220476 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1406,17:44:02.256,24.220918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1407-1406,17:44:02.256,24.221476 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1408,17:44:02.256,24.221499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1409-1408,17:44:02.257,24.222504 s,1.005 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1410,17:44:02.258,24.222924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1411-1410,17:44:02.258,24.223479 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1412,17:44:02.258,24.223505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1413-1412,17:44:02.260,24.225476 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1414,17:44:02.261,24.225921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1415-1414,17:44:02.261,24.226476 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1416,17:44:02.261,24.226500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1417-1416,17:44:02.263,24.228476 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1418,17:44:02.264,24.228922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1419-1418,17:44:02.264,24.229479 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1420,17:44:02.264,24.229506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1421-1420,17:44:02.266,24.231784 s,2.278 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1422,17:44:02.267,24.231919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1423-1422,17:44:02.267,24.232477 s,558 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1424,17:44:02.267,24.232503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1425-1424,17:44:02.269,24.234476 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1426,17:44:02.270,24.234918 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1427-1426,17:44:02.270,24.235475 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1428,17:44:02.270,24.235498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1429-1428,17:44:02.272,24.237476 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1430,17:44:02.273,24.237925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1431-1430,17:44:02.273,24.238476 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1432,17:44:02.273,24.238499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1433-1432,17:44:02.275,24.240480 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1434,17:44:02.276,24.240921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1435-1434,17:44:02.276,24.241475 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1436,17:44:02.276,24.241500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1437-1436,17:44:02.278,24.243475 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1438,17:44:02.279,24.243919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1439-1438,17:44:02.279,24.244475 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1440,17:44:02.279,24.244499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1441-1440,17:44:02.281,24.246475 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1442,17:44:02.282,24.246919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1443-1442,17:44:02.282,24.247476 s,557 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1444,17:44:02.282,24.247499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1445-1444,17:44:02.284,24.249475 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1446,17:44:02.285,24.249924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1447-1446,17:44:02.285,24.250475 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1448,17:44:02.285,24.250500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1449-1448,17:44:02.287,24.252474 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1450,17:44:02.288,24.252919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1451-1450,17:44:02.288,24.253475 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1452,17:44:02.288,24.253499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1453-1452,17:44:02.290,24.255475 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1454,17:44:02.291,24.255959 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1455-1454,17:44:02.291,24.256471 s,512 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,Success (Success) -URB,1456,17:44:02.291,24.256501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1457-1456,17:44:02.293,24.258473 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1458,17:44:02.294,24.258921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1459-1458,17:44:02.294,24.259474 s,553 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1460,17:44:02.294,24.259499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1461-1460,17:44:02.295,24.260521 s,1.022 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1462,17:44:02.296,24.260928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1463-1462,17:44:02.296,24.261476 s,548 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1464,17:44:02.296,24.261505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1465-1464,17:44:02.298,24.263476 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1466,17:44:02.299,24.263930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1467-1466,17:44:02.299,24.264476 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1468,17:44:02.299,24.264502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1469-1468,17:44:02.301,24.266475 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1470,17:44:02.302,24.266922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1471-1470,17:44:02.302,24.267474 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1472,17:44:02.302,24.267498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1473-1472,17:44:02.304,24.269475 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1474,17:44:02.305,24.269923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1475-1474,17:44:02.305,24.270475 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1476,17:44:02.305,24.270500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1477-1476,17:44:02.307,24.272476 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1478,17:44:02.308,24.272920 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1479-1478,17:44:02.308,24.273475 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1480,17:44:02.308,24.273498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1481-1480,17:44:02.310,24.275475 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1482,17:44:02.311,24.275922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1483-1482,17:44:02.311,24.276474 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1484,17:44:02.311,24.276498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1485-1484,17:44:02.313,24.278475 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1486,17:44:02.314,24.278921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1487-1486,17:44:02.314,24.279475 s,553 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1488,17:44:02.314,24.279499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1489-1488,17:44:02.316,24.281475 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1490,17:44:02.317,24.281930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1491-1490,17:44:02.317,24.282475 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1492,17:44:02.317,24.282499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1493-1492,17:44:02.319,24.284474 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1494,17:44:02.320,24.284921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1495-1494,17:44:02.320,24.285477 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1496,17:44:02.320,24.285501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1497-1496,17:44:02.322,24.287475 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1498,17:44:02.323,24.287920 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1499-1498,17:44:02.323,24.288475 s,554 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1500,17:44:02.323,24.288498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1501-1500,17:44:02.325,24.290474 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1502,17:44:02.326,24.290924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1503-1502,17:44:02.326,24.291474 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1504,17:44:02.326,24.291499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1505-1504,17:44:02.328,24.293474 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1506,17:44:02.329,24.293923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1507-1506,17:44:02.329,24.294475 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1508,17:44:02.329,24.294500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1509-1508,17:44:02.331,24.296477 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1510,17:44:02.332,24.296928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1511-1510,17:44:02.332,24.297474 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1512,17:44:02.332,24.297498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1513-1512,17:44:02.334,24.299474 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1514,17:44:02.335,24.299921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1515-1514,17:44:02.335,24.300474 s,553 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1516,17:44:02.335,24.300497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1517-1516,17:44:02.337,24.302474 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1518,17:44:02.338,24.302921 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1519-1518,17:44:02.338,24.303474 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1520,17:44:02.338,24.303497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1521-1520,17:44:02.340,24.305475 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1522,17:44:02.341,24.305925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1523-1522,17:44:02.341,24.306476 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1524,17:44:02.341,24.306503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1525-1524,17:44:02.343,24.308474 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1526,17:44:02.344,24.308940 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1527-1526,17:44:02.344,24.309470 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1528,17:44:02.344,24.309501 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1529-1528,17:44:02.346,24.311472 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1530,17:44:02.347,24.311930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1531-1530,17:44:02.347,24.312474 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1532,17:44:02.347,24.312498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1533-1532,17:44:02.349,24.314474 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1534,17:44:02.350,24.314922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1535-1534,17:44:02.350,24.315473 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1536,17:44:02.350,24.315497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1537-1536,17:44:02.352,24.317474 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1538,17:44:02.353,24.317922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1539-1538,17:44:02.353,24.318476 s,555 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1540,17:44:02.353,24.318500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1541-1540,17:44:02.355,24.320475 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1542,17:44:02.356,24.320922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1543-1542,17:44:02.356,24.321474 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1544,17:44:02.356,24.321497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1545-1544,17:44:02.358,24.323482 s,1.984 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1546,17:44:02.359,24.323937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1547-1546,17:44:02.359,24.324475 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1548,17:44:02.359,24.324504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1549-1548,17:44:02.361,24.326477 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1550,17:44:02.362,24.326932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1551-1550,17:44:02.362,24.327473 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1552,17:44:02.362,24.327498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1553-1552,17:44:02.364,24.329474 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1554,17:44:02.365,24.329925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1555-1554,17:44:02.365,24.330473 s,548 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1556,17:44:02.365,24.330498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1557-1556,17:44:02.367,24.332473 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1558,17:44:02.368,24.332922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1559-1558,17:44:02.368,24.333473 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1560,17:44:02.368,24.333497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1561-1560,17:44:02.370,24.335474 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1562,17:44:02.371,24.335922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1563-1562,17:44:02.371,24.336474 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1564,17:44:02.371,24.336498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1565-1564,17:44:02.373,24.338474 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1566,17:44:02.374,24.338922 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1567-1566,17:44:02.374,24.339474 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1568,17:44:02.374,24.339497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1569-1568,17:44:02.376,24.341473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1570,17:44:02.377,24.341929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1571-1570,17:44:02.377,24.342474 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1572,17:44:02.377,24.342497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1573-1572,17:44:02.379,24.344473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1574,17:44:02.380,24.344923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1575-1574,17:44:02.380,24.345473 s,550 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1576,17:44:02.380,24.345496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1577-1576,17:44:02.382,24.347473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1578,17:44:02.383,24.347923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1579-1578,17:44:02.383,24.348473 s,551 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1580,17:44:02.383,24.348496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1581-1580,17:44:02.385,24.350474 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1582,17:44:02.386,24.350927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1583-1582,17:44:02.386,24.351477 s,550 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1584,17:44:02.386,24.351502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1585-1584,17:44:02.388,24.353473 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1586,17:44:02.389,24.353924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1587-1586,17:44:02.389,24.354473 s,550 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1588,17:44:02.389,24.354497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1589-1588,17:44:02.391,24.356472 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1590,17:44:02.392,24.356925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1591-1590,17:44:02.392,24.357472 s,547 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1592,17:44:02.392,24.357497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1593-1592,17:44:02.394,24.359474 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1594,17:44:02.395,24.359927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1595-1594,17:44:02.395,24.360473 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1596,17:44:02.395,24.360496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1597-1596,17:44:02.397,24.362473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1598,17:44:02.398,24.362923 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1599-1598,17:44:02.398,24.363472 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1600,17:44:02.398,24.363495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1601-1600,17:44:02.400,24.365476 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1602,17:44:02.401,24.365924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1603-1602,17:44:02.401,24.366473 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1604,17:44:02.401,24.366496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1605-1604,17:44:02.403,24.368472 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1606,17:44:02.404,24.368924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1607-1606,17:44:02.404,24.369473 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1608,17:44:02.404,24.369497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1609-1608,17:44:02.406,24.371473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1610,17:44:02.407,24.371929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1611-1610,17:44:02.407,24.372472 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1612,17:44:02.407,24.372496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1613-1612,17:44:02.409,24.374473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1614,17:44:02.410,24.374924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1615-1614,17:44:02.410,24.375472 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1616,17:44:02.410,24.375496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1617-1616,17:44:02.412,24.377473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1618,17:44:02.413,24.377924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1619-1618,17:44:02.413,24.378473 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1620,17:44:02.413,24.378497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1621-1620,17:44:02.415,24.380514 s,2.018 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1622,17:44:02.416,24.380926 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1623-1622,17:44:02.416,24.381478 s,552 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1624,17:44:02.416,24.381506 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1625-1624,17:44:02.418,24.383488 s,1.982 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1626,17:44:02.419,24.383932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1627-1626,17:44:02.419,24.384475 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1628,17:44:02.419,24.384503 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1629-1628,17:44:02.421,24.386473 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1630,17:44:02.422,24.386924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1631-1630,17:44:02.422,24.387473 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1632,17:44:02.422,24.387497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1633-1632,17:44:02.424,24.389473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1634,17:44:02.425,24.389930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1635-1634,17:44:02.425,24.390472 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1636,17:44:02.425,24.390498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1637-1636,17:44:02.427,24.392473 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1638,17:44:02.428,24.392929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1639-1638,17:44:02.428,24.393473 s,544 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1640,17:44:02.428,24.393497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1641-1640,17:44:02.430,24.395472 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1642,17:44:02.431,24.395924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1643-1642,17:44:02.431,24.396472 s,548 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1644,17:44:02.431,24.396496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1645-1644,17:44:02.433,24.398473 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1646,17:44:02.434,24.398925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1647-1646,17:44:02.434,24.399473 s,549 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1648,17:44:02.434,24.399497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1649-1648,17:44:02.436,24.401473 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1650,17:44:02.437,24.401931 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1651-1650,17:44:02.437,24.402473 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1652,17:44:02.437,24.402496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1653-1652,17:44:02.439,24.404472 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1654,17:44:02.440,24.404924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1655-1654,17:44:02.440,24.405474 s,550 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1656,17:44:02.440,24.405498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1657-1656,17:44:02.442,24.407473 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1658,17:44:02.443,24.407924 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1659-1658,17:44:02.443,24.408472 s,547 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1660,17:44:02.443,24.408495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1661-1660,17:44:02.445,24.410473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1662,17:44:02.446,24.410929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1663-1662,17:44:02.446,24.411471 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1664,17:44:02.446,24.411496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1665-1664,17:44:02.448,24.413471 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1666,17:44:02.449,24.413926 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1667-1666,17:44:02.449,24.414472 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1668,17:44:02.449,24.414496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1669-1668,17:44:02.451,24.416472 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1670,17:44:02.452,24.416925 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1671-1670,17:44:02.452,24.417473 s,547 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1672,17:44:02.452,24.417496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1673-1672,17:44:02.454,24.419475 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1674,17:44:02.455,24.419927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1675-1674,17:44:02.455,24.420471 s,544 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1676,17:44:02.455,24.420495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1677-1676,17:44:02.457,24.422472 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1678,17:44:02.458,24.422930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1679-1678,17:44:02.458,24.423471 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1680,17:44:02.458,24.423495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1681-1680,17:44:02.460,24.425473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1682,17:44:02.461,24.425926 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1683-1682,17:44:02.461,24.426472 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1684,17:44:02.461,24.426496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1685-1684,17:44:02.463,24.428472 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1686,17:44:02.464,24.428927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1687-1686,17:44:02.464,24.429471 s,544 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1688,17:44:02.464,24.429495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1689-1688,17:44:02.466,24.431472 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1690,17:44:02.467,24.431932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1691-1690,17:44:02.467,24.432472 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1692,17:44:02.467,24.432496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1693-1692,17:44:02.469,24.434472 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1694,17:44:02.470,24.434926 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1695-1694,17:44:02.470,24.435471 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1696,17:44:02.470,24.435495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1697-1696,17:44:02.472,24.437471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1698,17:44:02.473,24.437932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1699-1698,17:44:02.473,24.438471 s,539 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1700,17:44:02.473,24.438495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1701-1700,17:44:02.475,24.440473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1702,17:44:02.476,24.440926 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1703-1702,17:44:02.476,24.441471 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1704,17:44:02.476,24.441494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1705-1704,17:44:02.478,24.443471 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1706,17:44:02.479,24.443927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1707-1706,17:44:02.479,24.444472 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1708,17:44:02.479,24.444495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1709-1708,17:44:02.481,24.446472 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1710,17:44:02.482,24.446927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1711-1710,17:44:02.482,24.447472 s,545 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1712,17:44:02.482,24.447495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1713-1712,17:44:02.484,24.449471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1714,17:44:02.485,24.449929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1715-1714,17:44:02.485,24.450471 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1716,17:44:02.485,24.450496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1717-1716,17:44:02.487,24.452471 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1718,17:44:02.488,24.452927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1719-1718,17:44:02.488,24.453474 s,547 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1720,17:44:02.488,24.453498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1721-1720,17:44:02.490,24.455472 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1722,17:44:02.491,24.455972 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1723-1722,17:44:02.491,24.456466 s,495 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,Success (Success) -URB,1724,17:44:02.491,24.456494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1725-1724,17:44:02.493,24.458469 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1726,17:44:02.494,24.458928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1727-1726,17:44:02.494,24.459471 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1728,17:44:02.494,24.459494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1729-1728,17:44:02.496,24.461471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1730,17:44:02.497,24.461931 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1731-1730,17:44:02.497,24.462471 s,540 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1732,17:44:02.497,24.462495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1733-1732,17:44:02.499,24.464471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1734,17:44:02.500,24.464927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1735-1734,17:44:02.500,24.465470 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1736,17:44:02.500,24.465494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1737-1736,17:44:02.502,24.467473 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1738,17:44:02.503,24.467927 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1739-1738,17:44:02.503,24.468470 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1740,17:44:02.503,24.468494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1741-1740,17:44:02.505,24.470472 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1742,17:44:02.506,24.470930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1743-1742,17:44:02.506,24.471471 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1744,17:44:02.506,24.471495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1745-1744,17:44:02.508,24.473471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1746,17:44:02.509,24.473928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1747-1746,17:44:02.509,24.474470 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1748,17:44:02.509,24.474494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1749-1748,17:44:02.511,24.476470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1750,17:44:02.512,24.476929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1751-1750,17:44:02.512,24.477471 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1752,17:44:02.512,24.477494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1753-1752,17:44:02.514,24.479471 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1754,17:44:02.515,24.479928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1755-1754,17:44:02.515,24.480470 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1756,17:44:02.515,24.480494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1757-1756,17:44:02.517,24.482471 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1758,17:44:02.518,24.482928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1759-1758,17:44:02.518,24.483470 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1760,17:44:02.518,24.483493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1761-1760,17:44:02.520,24.485470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1762,17:44:02.521,24.485928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1763-1762,17:44:02.521,24.486470 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1764,17:44:02.521,24.486494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1765-1764,17:44:02.523,24.488471 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1766,17:44:02.524,24.488929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1767-1766,17:44:02.524,24.489471 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1768,17:44:02.524,24.489494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1769-1768,17:44:02.526,24.491470 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1770,17:44:02.527,24.491932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1771-1770,17:44:02.527,24.492470 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1772,17:44:02.527,24.492494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1773-1772,17:44:02.529,24.494470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1774,17:44:02.530,24.494928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1775-1774,17:44:02.530,24.495471 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1776,17:44:02.530,24.495494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1777-1776,17:44:02.532,24.497470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1778,17:44:02.533,24.497928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1779-1778,17:44:02.533,24.498470 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1780,17:44:02.533,24.498494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1781-1780,17:44:02.535,24.500470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1782,17:44:02.536,24.500929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1783-1782,17:44:02.536,24.501485 s,556 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1784,17:44:02.536,24.501514 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1785-1784,17:44:02.538,24.503473 s,1.959 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1786,17:44:02.539,24.503932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1787-1786,17:44:02.539,24.504470 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1788,17:44:02.539,24.504494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1789-1788,17:44:02.541,24.506469 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1790,17:44:02.542,24.506928 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1791-1790,17:44:02.542,24.507470 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1792,17:44:02.542,24.507493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1793-1792,17:44:02.544,24.509470 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1794,17:44:02.545,24.509933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1795-1794,17:44:02.545,24.510470 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1796,17:44:02.545,24.510495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1797-1796,17:44:02.547,24.512470 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1798,17:44:02.548,24.512929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1799-1798,17:44:02.548,24.513470 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1800,17:44:02.548,24.513493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1801-1800,17:44:02.550,24.515470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1802,17:44:02.551,24.515929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1803-1802,17:44:02.551,24.516470 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1804,17:44:02.551,24.516493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1805-1804,17:44:02.553,24.518471 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1806,17:44:02.554,24.518929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1807-1806,17:44:02.554,24.519470 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1808,17:44:02.554,24.519493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1809-1808,17:44:02.556,24.521471 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1810,17:44:02.557,24.521934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1811-1810,17:44:02.557,24.522473 s,539 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1812,17:44:02.557,24.522497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1813-1812,17:44:02.559,24.524484 s,1.987 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1814,17:44:02.560,24.524933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1815-1814,17:44:02.560,24.525474 s,541 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1816,17:44:02.560,24.525502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1817-1816,17:44:02.562,24.527474 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1818,17:44:02.563,24.527930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1819-1818,17:44:02.563,24.528470 s,540 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1820,17:44:02.563,24.528494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1821-1820,17:44:02.565,24.530470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1822,17:44:02.566,24.530932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1823-1822,17:44:02.566,24.531469 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1824,17:44:02.566,24.531494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1825-1824,17:44:02.567,24.532523 s,1.029 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1826,17:44:02.568,24.532932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1827-1826,17:44:02.568,24.533476 s,544 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1828,17:44:02.568,24.533504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1829-1828,17:44:02.570,24.535471 s,1.968 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1830,17:44:02.571,24.535939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1831-1830,17:44:02.571,24.536470 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1832,17:44:02.571,24.536495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1833-1832,17:44:02.573,24.538471 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1834,17:44:02.574,24.538930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1835-1834,17:44:02.574,24.539472 s,542 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1836,17:44:02.574,24.539497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1837-1836,17:44:02.576,24.541470 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1838,17:44:02.577,24.541932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1839-1838,17:44:02.577,24.542469 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1840,17:44:02.577,24.542493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1841-1840,17:44:02.579,24.544470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1842,17:44:02.580,24.544930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1843-1842,17:44:02.580,24.545470 s,539 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1844,17:44:02.580,24.545493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1845-1844,17:44:02.582,24.547469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1846,17:44:02.583,24.547930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1847-1846,17:44:02.583,24.548493 s,563 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1848,17:44:02.583,24.548518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1849-1848,17:44:02.585,24.550471 s,1.954 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1850,17:44:02.586,24.550933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1851-1850,17:44:02.586,24.551470 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1852,17:44:02.586,24.551495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1853-1852,17:44:02.588,24.553473 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1854,17:44:02.589,24.553931 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1855-1854,17:44:02.589,24.554469 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1856,17:44:02.589,24.554493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1857-1856,17:44:02.591,24.556469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1858,17:44:02.592,24.556933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1859-1858,17:44:02.592,24.557468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1860,17:44:02.592,24.557492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1861-1860,17:44:02.594,24.559470 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1862,17:44:02.595,24.559931 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1863-1862,17:44:02.595,24.560469 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1864,17:44:02.595,24.560492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1865-1864,17:44:02.597,24.562470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1866,17:44:02.598,24.562931 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1867-1866,17:44:02.598,24.563468 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1868,17:44:02.598,24.563492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1869-1868,17:44:02.600,24.565469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1870,17:44:02.601,24.565930 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1871-1870,17:44:02.601,24.566470 s,540 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1872,17:44:02.601,24.566494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1873-1872,17:44:02.603,24.568469 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1874,17:44:02.604,24.568933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1875-1874,17:44:02.604,24.569468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1876,17:44:02.604,24.569492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1877-1876,17:44:02.606,24.571469 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1878,17:44:02.607,24.571932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1879-1878,17:44:02.607,24.572468 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1880,17:44:02.607,24.572492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1881-1880,17:44:02.609,24.574469 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1882,17:44:02.610,24.574934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1883-1882,17:44:02.610,24.575469 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1884,17:44:02.610,24.575493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1885-1884,17:44:02.612,24.577470 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1886,17:44:02.613,24.577932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1887-1886,17:44:02.613,24.578470 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1888,17:44:02.613,24.578493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1889-1888,17:44:02.615,24.580469 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1890,17:44:02.616,24.580934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1891-1890,17:44:02.616,24.581469 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1892,17:44:02.616,24.581492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1893-1892,17:44:02.618,24.583469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1894,17:44:02.619,24.583932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1895-1894,17:44:02.619,24.584468 s,536 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1896,17:44:02.619,24.584492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1897-1896,17:44:02.621,24.586470 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1898,17:44:02.622,24.586938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1899-1898,17:44:02.622,24.587467 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1900,17:44:02.622,24.587493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1901-1900,17:44:02.624,24.589468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1902,17:44:02.625,24.589943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1903-1902,17:44:02.625,24.590468 s,525 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1904,17:44:02.625,24.590494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1905-1904,17:44:02.627,24.592469 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1906,17:44:02.628,24.592935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1907-1906,17:44:02.628,24.593471 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1908,17:44:02.628,24.593496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1909-1908,17:44:02.630,24.595468 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1910,17:44:02.631,24.595933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1911-1910,17:44:02.631,24.596468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1912,17:44:02.631,24.596492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1913-1912,17:44:02.633,24.598468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1914,17:44:02.634,24.598933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1915-1914,17:44:02.634,24.599468 s,536 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1916,17:44:02.634,24.599492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1917-1916,17:44:02.636,24.601469 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1918,17:44:02.637,24.601933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1919-1918,17:44:02.637,24.602468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1920,17:44:02.637,24.602492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1921-1920,17:44:02.639,24.604468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1922,17:44:02.640,24.604932 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1923-1922,17:44:02.640,24.605468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1924,17:44:02.640,24.605491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1925-1924,17:44:02.642,24.607471 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1926,17:44:02.643,24.607934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1927-1926,17:44:02.643,24.608468 s,534 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1928,17:44:02.643,24.608491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1929-1928,17:44:02.645,24.610468 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1930,17:44:02.646,24.610935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1931-1930,17:44:02.646,24.611468 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1932,17:44:02.646,24.611492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1933-1932,17:44:02.648,24.613469 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1934,17:44:02.649,24.613937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1935-1934,17:44:02.649,24.614467 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1936,17:44:02.649,24.614493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1937-1936,17:44:02.651,24.616468 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1938,17:44:02.652,24.616933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1939-1938,17:44:02.652,24.617468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1940,17:44:02.652,24.617491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1941-1940,17:44:02.654,24.619468 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1942,17:44:02.655,24.619933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1943-1942,17:44:02.655,24.620467 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1944,17:44:02.655,24.620491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1945-1944,17:44:02.657,24.622468 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1946,17:44:02.658,24.622937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1947-1946,17:44:02.658,24.623468 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1948,17:44:02.658,24.623491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1949-1948,17:44:02.660,24.625467 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1950,17:44:02.661,24.625933 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1951-1950,17:44:02.661,24.626468 s,535 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1952,17:44:02.661,24.626492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1953-1952,17:44:02.663,24.628467 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1954,17:44:02.664,24.628935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1955-1954,17:44:02.664,24.629468 s,533 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1956,17:44:02.664,24.629492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1957-1956,17:44:02.666,24.631468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1958,17:44:02.667,24.631934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1959-1958,17:44:02.667,24.632468 s,534 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1960,17:44:02.667,24.632491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1961-1960,17:44:02.669,24.634469 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1962,17:44:02.670,24.634936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1963-1962,17:44:02.670,24.635467 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1964,17:44:02.670,24.635491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1965-1964,17:44:02.672,24.637468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1966,17:44:02.673,24.637940 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1967-1966,17:44:02.673,24.638468 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1968,17:44:02.673,24.638492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1969-1968,17:44:02.675,24.640468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1970,17:44:02.676,24.640934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1971-1970,17:44:02.676,24.641470 s,536 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1972,17:44:02.676,24.641493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1973-1972,17:44:02.678,24.643467 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1974,17:44:02.679,24.643934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1975-1974,17:44:02.679,24.644467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1976,17:44:02.679,24.644490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1977-1976,17:44:02.681,24.646467 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1978,17:44:02.682,24.646934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1979-1978,17:44:02.682,24.647467 s,533 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1980,17:44:02.682,24.647491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1981-1980,17:44:02.684,24.649468 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1982,17:44:02.685,24.649937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1983-1982,17:44:02.685,24.650468 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1984,17:44:02.685,24.650492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1985-1984,17:44:02.687,24.652467 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1986,17:44:02.688,24.652934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1987-1986,17:44:02.688,24.653467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1988,17:44:02.688,24.653491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1989-1988,17:44:02.690,24.655470 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1990,17:44:02.691,24.655938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1991-1990,17:44:02.691,24.656468 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1992,17:44:02.691,24.656491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1993-1992,17:44:02.693,24.658467 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1994,17:44:02.694,24.658936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1995-1994,17:44:02.694,24.659468 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,1996,17:44:02.694,24.659491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,1997-1996,17:44:02.696,24.661467 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,1998,17:44:02.697,24.661935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,1999-1998,17:44:02.697,24.662467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2000,17:44:02.697,24.662490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2001-2000,17:44:02.699,24.664467 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2002,17:44:02.700,24.664934 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2003-2002,17:44:02.700,24.665467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2004,17:44:02.700,24.665490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2005-2004,17:44:02.702,24.667469 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2006,17:44:02.703,24.667936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2007-2006,17:44:02.703,24.668467 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2008,17:44:02.703,24.668492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2009-2008,17:44:02.705,24.670468 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2010,17:44:02.706,24.670938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2011-2010,17:44:02.706,24.671467 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2012,17:44:02.706,24.671492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2013-2012,17:44:02.708,24.673467 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2014,17:44:02.709,24.673937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2015-2014,17:44:02.709,24.674467 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2016,17:44:02.709,24.674492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2017-2016,17:44:02.711,24.676467 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2018,17:44:02.712,24.676936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2019-2018,17:44:02.712,24.677466 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2020,17:44:02.712,24.677490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2021-2020,17:44:02.714,24.679468 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2022,17:44:02.715,24.679936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2023-2022,17:44:02.715,24.680466 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2024,17:44:02.715,24.680490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2025-2024,17:44:02.717,24.682467 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2026,17:44:02.718,24.682935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2027-2026,17:44:02.718,24.683467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2028,17:44:02.718,24.683490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2029-2028,17:44:02.720,24.685467 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2030,17:44:02.721,24.685935 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2031-2030,17:44:02.721,24.686467 s,532 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2032,17:44:02.721,24.686490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2033-2032,17:44:02.723,24.688470 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2034,17:44:02.724,24.688938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2035-2034,17:44:02.724,24.689481 s,543 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2036,17:44:02.724,24.689511 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2037-2036,17:44:02.726,24.691474 s,1.963 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2038,17:44:02.727,24.691937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2039-2038,17:44:02.727,24.692473 s,536 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2040,17:44:02.727,24.692498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2041-2040,17:44:02.729,24.694467 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2042,17:44:02.730,24.694936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2043-2042,17:44:02.730,24.695466 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2044,17:44:02.730,24.695491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2045-2044,17:44:02.732,24.697467 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2046,17:44:02.733,24.697936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2047-2046,17:44:02.733,24.698466 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2048,17:44:02.733,24.698490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2049-2048,17:44:02.735,24.700473 s,1.984 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2050,17:44:02.736,24.700936 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2051-2050,17:44:02.736,24.701466 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2052,17:44:02.736,24.701490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2053-2052,17:44:02.738,24.703469 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2054,17:44:02.739,24.703937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2055-2054,17:44:02.739,24.704475 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2056,17:44:02.739,24.704498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2057-2056,17:44:02.741,24.706474 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2058,17:44:02.742,24.706937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2059-2058,17:44:02.742,24.707474 s,537 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2060,17:44:02.742,24.707497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2061-2060,17:44:02.744,24.709467 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2062,17:44:02.745,24.709945 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2063-2062,17:44:02.745,24.710474 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2064,17:44:02.745,24.710500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2065-2064,17:44:02.747,24.712468 s,1.968 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2066,17:44:02.748,24.712944 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2067-2066,17:44:02.748,24.713475 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2068,17:44:02.748,24.713500 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2069-2068,17:44:02.750,24.715466 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2070,17:44:02.751,24.715937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2071-2070,17:44:02.751,24.716466 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2072,17:44:02.751,24.716490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2073-2072,17:44:02.753,24.718466 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2074,17:44:02.754,24.718937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2075-2074,17:44:02.754,24.719466 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2076,17:44:02.754,24.719491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2077-2076,17:44:02.756,24.721466 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2078,17:44:02.757,24.721937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2079-2078,17:44:02.757,24.722467 s,530 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2080,17:44:02.757,24.722491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2081-2080,17:44:02.759,24.724466 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2082,17:44:02.760,24.724937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2083-2082,17:44:02.760,24.725465 s,528 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2084,17:44:02.760,24.725489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2085-2084,17:44:02.762,24.727467 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2086,17:44:02.763,24.727937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2087-2086,17:44:02.763,24.728465 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2088,17:44:02.763,24.728489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2089-2088,17:44:02.765,24.730466 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2090,17:44:02.766,24.730941 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2091-2090,17:44:02.766,24.731465 s,525 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2092,17:44:02.766,24.731490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2093-2092,17:44:02.768,24.733466 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2094,17:44:02.769,24.733937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2095-2094,17:44:02.769,24.734466 s,529 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2096,17:44:02.769,24.734490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2097-2096,17:44:02.771,24.736465 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2098,17:44:02.772,24.736937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2099-2098,17:44:02.772,24.737468 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2100,17:44:02.772,24.737492 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2101-2100,17:44:02.774,24.739466 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2102,17:44:02.775,24.739937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2103-2102,17:44:02.775,24.740465 s,528 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2104,17:44:02.775,24.740489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2105-2104,17:44:02.777,24.742467 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2106,17:44:02.778,24.742938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2107-2106,17:44:02.778,24.743465 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2108,17:44:02.778,24.743489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2109-2108,17:44:02.780,24.745466 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2110,17:44:02.781,24.745938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2111-2110,17:44:02.781,24.746465 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2112,17:44:02.781,24.746489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2113-2112,17:44:02.783,24.748465 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2114,17:44:02.784,24.748939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2115-2114,17:44:02.784,24.749465 s,526 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2116,17:44:02.784,24.749489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2117-2116,17:44:02.786,24.751468 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2118,17:44:02.787,24.751938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2119-2118,17:44:02.787,24.752465 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2120,17:44:02.787,24.752488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2121-2120,17:44:02.789,24.754465 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2122,17:44:02.790,24.754939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2123-2122,17:44:02.790,24.755464 s,525 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2124,17:44:02.790,24.755488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2125-2124,17:44:02.792,24.757465 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2126,17:44:02.793,24.757938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2127-2126,17:44:02.793,24.758465 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2128,17:44:02.793,24.758488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2129-2128,17:44:02.795,24.760466 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2130,17:44:02.796,24.760940 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2131-2130,17:44:02.796,24.761466 s,525 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2132,17:44:02.796,24.761489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2133-2132,17:44:02.798,24.763466 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2134,17:44:02.799,24.763938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2135-2134,17:44:02.799,24.764465 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2136,17:44:02.799,24.764489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2137-2136,17:44:02.801,24.766465 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2138,17:44:02.802,24.766938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2139-2138,17:44:02.802,24.767466 s,527 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2140,17:44:02.802,24.767489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2141-2140,17:44:02.804,24.769465 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2142,17:44:02.805,24.769941 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2143-2142,17:44:02.805,24.770464 s,523 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2144,17:44:02.805,24.770489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2145-2144,17:44:02.807,24.772465 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2146,17:44:02.808,24.772940 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2147-2146,17:44:02.808,24.773464 s,524 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2148,17:44:02.808,24.773487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2149-2148,17:44:02.810,24.775466 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2150,17:44:02.811,24.775939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2151-2150,17:44:02.811,24.776465 s,526 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2152,17:44:02.811,24.776488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2153-2152,17:44:02.813,24.778466 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2154,17:44:02.814,24.778939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2155-2154,17:44:02.814,24.779464 s,525 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2156,17:44:02.814,24.779488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2157-2156,17:44:02.816,24.781465 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2158,17:44:02.817,24.781952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2159-2158,17:44:02.817,24.782476 s,524 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2160,17:44:02.817,24.782505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2161-2160,17:44:02.819,24.784463 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2162,17:44:02.820,24.784938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2163-2162,17:44:02.820,24.785458 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2164,17:44:02.820,24.785480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2165-2164,17:44:02.822,24.787457 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2166,17:44:02.823,24.787937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2167-2166,17:44:02.823,24.788458 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2168,17:44:02.823,24.788480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2169-2168,17:44:02.824,24.789461 s,980 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2170,17:44:02.825,24.789939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2171-2170,17:44:02.825,24.790459 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2172,17:44:02.825,24.790482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2173-2172,17:44:02.827,24.792457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2174,17:44:02.828,24.792937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2175-2174,17:44:02.828,24.793458 s,521 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2176,17:44:02.828,24.793481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2177-2176,17:44:02.830,24.795457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2178,17:44:02.831,24.795938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2179-2178,17:44:02.831,24.796457 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2180,17:44:02.831,24.796479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2181-2180,17:44:02.832,24.797458 s,978 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2182,17:44:02.833,24.797937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2183-2182,17:44:02.833,24.798458 s,521 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2184,17:44:02.833,24.798487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2185-2184,17:44:02.835,24.800457 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2186,17:44:02.836,24.800937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2187-2186,17:44:02.836,24.801458 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2188,17:44:02.836,24.801480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2189-2188,17:44:02.838,24.803457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2190,17:44:02.839,24.803937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2191-2190,17:44:02.839,24.804458 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2192,17:44:02.839,24.804480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2193-2192,17:44:02.840,24.805457 s,978 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2194,17:44:02.841,24.805937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2195-2194,17:44:02.841,24.806458 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2196,17:44:02.841,24.806480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2197-2196,17:44:02.843,24.808458 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2198,17:44:02.844,24.808938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2199-2198,17:44:02.844,24.809457 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2200,17:44:02.844,24.809480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2201-2200,17:44:02.846,24.811456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2202,17:44:02.847,24.811937 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2203-2202,17:44:02.847,24.812457 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2204,17:44:02.847,24.812479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2205-2204,17:44:02.848,24.813457 s,978 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2206,17:44:02.849,24.813938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2207-2206,17:44:02.849,24.814457 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2208,17:44:02.849,24.814479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2209-2208,17:44:02.851,24.816457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2210,17:44:02.852,24.816938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2211-2210,17:44:02.852,24.817457 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2212,17:44:02.852,24.817479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2213-2212,17:44:02.854,24.819457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2214,17:44:02.855,24.819938 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2215-2214,17:44:02.855,24.820457 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2216,17:44:02.855,24.820479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2217-2216,17:44:02.856,24.821457 s,978 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2218,17:44:02.857,24.821945 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2219-2218,17:44:02.857,24.822457 s,512 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2220,17:44:02.857,24.822479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2221-2220,17:44:02.859,24.824457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2222,17:44:02.860,24.824939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2223-2222,17:44:02.860,24.825457 s,518 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2224,17:44:02.860,24.825480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2225-2224,17:44:02.862,24.827457 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2226,17:44:02.863,24.827939 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2227-2226,17:44:02.863,24.828457 s,518 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2228,17:44:02.863,24.828479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2229-2228,17:44:02.864,24.829471 s,992 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2230,17:44:02.865,24.829943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2231-2230,17:44:02.865,24.830468 s,526 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2232,17:44:02.865,24.830494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2233-2232,17:44:02.867,24.832464 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2234,17:44:02.868,24.832941 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2235-2234,17:44:02.868,24.833463 s,522 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2236,17:44:02.868,24.833487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2237-2236,17:44:02.870,24.835464 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2238,17:44:02.871,24.835940 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2239-2238,17:44:02.871,24.836463 s,523 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2240,17:44:02.871,24.836487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2241-2240,17:44:02.873,24.838467 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2242,17:44:02.874,24.838942 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2243-2242,17:44:02.874,24.839464 s,522 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2244,17:44:02.874,24.839488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2245-2244,17:44:02.876,24.841464 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2246,17:44:02.877,24.841941 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2247-2246,17:44:02.877,24.842464 s,523 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2248,17:44:02.877,24.842487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2249-2248,17:44:02.879,24.844463 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2250,17:44:02.880,24.844942 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2251-2250,17:44:02.880,24.845464 s,522 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2252,17:44:02.880,24.845487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2253-2252,17:44:02.882,24.847464 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2254,17:44:02.883,24.847941 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2255-2254,17:44:02.883,24.848463 s,522 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2256,17:44:02.883,24.848487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2257-2256,17:44:02.885,24.850463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2258,17:44:02.886,24.850944 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2259-2258,17:44:02.886,24.851463 s,518 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2260,17:44:02.886,24.851487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2261-2260,17:44:02.888,24.853464 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2262,17:44:02.889,24.853946 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2263-2262,17:44:02.889,24.854464 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2264,17:44:02.889,24.854489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2265-2264,17:44:02.891,24.856463 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2266,17:44:02.892,24.856943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2267-2266,17:44:02.892,24.857463 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2268,17:44:02.892,24.857488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2269-2268,17:44:02.894,24.859463 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2270,17:44:02.895,24.859945 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2271-2270,17:44:02.895,24.860463 s,518 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2272,17:44:02.895,24.860487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2273-2272,17:44:02.897,24.862463 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2274,17:44:02.898,24.862942 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2275-2274,17:44:02.898,24.863463 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2276,17:44:02.898,24.863486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2277-2276,17:44:02.900,24.865463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2278,17:44:02.901,24.865942 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2279-2278,17:44:02.901,24.866463 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2280,17:44:02.901,24.866486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2281-2280,17:44:02.903,24.868463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2282,17:44:02.904,24.868945 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2283-2282,17:44:02.904,24.869466 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2284,17:44:02.904,24.869491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2285-2284,17:44:02.906,24.871465 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2286,17:44:02.907,24.871943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2287-2286,17:44:02.907,24.872466 s,523 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2288,17:44:02.907,24.872489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2289-2288,17:44:02.909,24.874463 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2290,17:44:02.910,24.874943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2291-2290,17:44:02.910,24.875463 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2292,17:44:02.910,24.875486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2293-2292,17:44:02.912,24.877463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2294,17:44:02.913,24.877943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2295-2294,17:44:02.913,24.878463 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2296,17:44:02.913,24.878486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2297-2296,17:44:02.915,24.880463 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2298,17:44:02.916,24.880943 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2299-2298,17:44:02.916,24.881462 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2300,17:44:02.916,24.881486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2301-2300,17:44:02.918,24.883463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2302,17:44:02.919,24.883942 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2303-2302,17:44:02.919,24.884508 s,566 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2304,17:44:02.919,24.884533 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2305-2304,17:44:02.921,24.886508 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2306,17:44:02.922,24.886959 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2307-2306,17:44:02.922,24.887468 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2308,17:44:02.922,24.887499 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2309-2308,17:44:02.924,24.889493 s,1.994 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2310,17:44:02.925,24.889959 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2311-2310,17:44:02.925,24.890469 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2312,17:44:02.925,24.890498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2313-2312,17:44:02.927,24.892498 s,2.000 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2314,17:44:02.928,24.892966 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2315-2314,17:44:02.928,24.893481 s,515 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2316,17:44:02.928,24.893517 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2317-2316,17:44:02.930,24.895471 s,1.953 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2318,17:44:02.931,24.895955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2319-2318,17:44:02.931,24.896468 s,513 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2320,17:44:02.931,24.896498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2321-2320,17:44:02.933,24.898463 s,1.965 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2322,17:44:02.934,24.899023 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2323-2322,17:44:02.934,24.899463 s,440 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2324,17:44:02.934,24.899495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2325-2324,17:44:02.936,24.901462 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2326,17:44:02.937,24.901953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2327-2326,17:44:02.937,24.902499 s,546 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2328,17:44:02.937,24.902545 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2329-2328,17:44:02.939,24.904556 s,2.011 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2330,17:44:02.940,24.904949 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2331-2330,17:44:02.940,24.905466 s,517 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2332,17:44:02.940,24.905494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2333-2332,17:44:02.942,24.907461 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2334,17:44:02.943,24.907946 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2335-2334,17:44:02.943,24.908461 s,515 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2336,17:44:02.943,24.908486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2337-2336,17:44:02.945,24.910463 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2338,17:44:02.946,24.910959 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2339-2338,17:44:02.946,24.911462 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2340,17:44:02.946,24.911491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2341-2340,17:44:02.948,24.913462 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2342,17:44:02.949,24.913948 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2343-2342,17:44:02.949,24.914462 s,514 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2344,17:44:02.949,24.914486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2345-2344,17:44:02.951,24.916462 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2346,17:44:02.952,24.916946 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2347-2346,17:44:02.952,24.917464 s,518 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2348,17:44:02.952,24.917489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2349-2348,17:44:02.954,24.919462 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2350,17:44:02.955,24.919946 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2351-2350,17:44:02.955,24.920463 s,517 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2352,17:44:02.955,24.920487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2353-2352,17:44:02.957,24.922462 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2354,17:44:02.958,24.922951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2355-2354,17:44:02.958,24.923464 s,513 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2356,17:44:02.958,24.923488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2357-2356,17:44:02.960,24.925461 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2358,17:44:02.961,24.925946 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2359-2358,17:44:02.961,24.926465 s,519 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2360,17:44:02.961,24.926489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2361-2360,17:44:02.963,24.928461 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2362,17:44:02.964,24.928949 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2363-2362,17:44:02.964,24.929469 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2364,17:44:02.964,24.929496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2365-2364,17:44:02.966,24.931462 s,1.965 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2366,17:44:02.967,24.931947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2367-2366,17:44:02.967,24.932461 s,515 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2368,17:44:02.967,24.932487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2369-2368,17:44:02.969,24.934462 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2370,17:44:02.970,24.934947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2371-2370,17:44:02.970,24.935462 s,516 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2372,17:44:02.970,24.935487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2373-2372,17:44:02.972,24.937473 s,1.986 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2374,17:44:02.973,24.938041 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2375-2374,17:44:02.973,24.938475 s,434 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2376,17:44:02.973,24.938541 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2377-2376,17:44:02.975,24.940483 s,1.942 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2378,17:44:02.976,24.941008 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2379-2378,17:44:02.976,24.941483 s,475 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2380,17:44:02.976,24.941540 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2381-2380,17:44:02.978,24.943485 s,1.945 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2382,17:44:02.979,24.943980 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2383-2382,17:44:02.979,24.944464 s,484 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2384,17:44:02.979,24.944496 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2385-2384,17:44:02.981,24.946472 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2386,17:44:02.982,24.946974 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2387-2386,17:44:02.982,24.947470 s,496 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2388,17:44:02.982,24.947518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2389-2388,17:44:02.984,24.949461 s,1.944 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2390,17:44:02.985,24.949987 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2391-2390,17:44:02.985,24.950462 s,475 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2392,17:44:02.985,24.950491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2393-2392,17:44:02.987,24.952462 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2394,17:44:02.988,24.952952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2395-2394,17:44:02.988,24.953461 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2396,17:44:02.988,24.953488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2397-2396,17:44:02.990,24.955468 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2398,17:44:02.991,24.956003 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2399-2398,17:44:02.991,24.956462 s,459 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2400,17:44:02.991,24.956494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2401-2400,17:44:02.993,24.958459 s,1.965 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2402,17:44:02.994,24.958944 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2403-2402,17:44:02.994,24.959458 s,513 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2404,17:44:02.994,24.959481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2405-2404,17:44:02.996,24.961477 s,1.996 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2406,17:44:02.997,24.962161 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2407-2406,17:44:02.997,24.962468 s,308 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096E4160h,Success (Success) -URB,2408,17:44:02.997,24.962638 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2409-2408,17:44:02.999,24.964468 s,1.830 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2410,17:44:03.000,24.964956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2411-2410,17:44:03.000,24.965487 s,531 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2412,17:44:03.000,24.965525 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2413-2412,17:44:03.002,24.967484 s,1.959 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2414,17:44:03.003,24.967949 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2415-2414,17:44:03.003,24.968469 s,520 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2416,17:44:03.003,24.968497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2417-2416,17:44:03.005,24.970464 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2418,17:44:03.006,24.970950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2419-2418,17:44:03.006,24.971462 s,511 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2420,17:44:03.006,24.971488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2421-2420,17:44:03.008,24.973462 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2422,17:44:03.009,24.973947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2423-2422,17:44:03.009,24.974461 s,514 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2424,17:44:03.009,24.974486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2425-2424,17:44:03.011,24.976462 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2426,17:44:03.012,24.976947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2427-2426,17:44:03.012,24.977461 s,515 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2428,17:44:03.012,24.977485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2429-2428,17:44:03.014,24.979475 s,1.990 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2430,17:44:03.015,24.979996 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2431-2430,17:44:03.015,24.980474 s,478 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2432,17:44:03.015,24.980708 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2433-2432,17:44:03.017,24.982459 s,1.751 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2434,17:44:03.018,24.982953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2435-2434,17:44:03.018,24.983462 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2436,17:44:03.018,24.983486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2437-2436,17:44:03.020,24.985461 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2438,17:44:03.021,24.985947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2439-2438,17:44:03.021,24.986460 s,513 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2440,17:44:03.021,24.986484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2441-2440,17:44:03.023,24.988461 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2442,17:44:03.024,24.988950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2443-2442,17:44:03.024,24.989460 s,511 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2444,17:44:03.024,24.989485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2445-2444,17:44:03.026,24.991461 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2446,17:44:03.027,24.991947 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2447-2446,17:44:03.027,24.992461 s,514 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2448,17:44:03.027,24.992484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2449-2448,17:44:03.029,24.994467 s,1.983 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2450,17:44:03.030,24.994956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2451-2450,17:44:03.030,24.995461 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2452,17:44:03.030,24.995488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2453-2452,17:44:03.032,24.997459 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2454,17:44:03.033,24.997953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2455-2454,17:44:03.033,24.998461 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2456,17:44:03.033,24.998485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2457-2456,17:44:03.035,25.000461 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2458,17:44:03.036,25.000949 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2459-2458,17:44:03.036,25.001472 s,523 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2460,17:44:03.036,25.001502 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2461-2460,17:44:03.038,25.003463 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2462,17:44:03.039,25.003954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2463-2462,17:44:03.039,25.004465 s,512 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2464,17:44:03.039,25.004495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2465-2464,17:44:03.041,25.006472 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2466,17:44:03.042,25.007032 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2467-2466,17:44:03.042,25.007461 s,428 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2468,17:44:03.042,25.007495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2469-2468,17:44:03.044,25.009462 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2470,17:44:03.045,25.009969 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2471-2470,17:44:03.045,25.010462 s,492 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2472,17:44:03.045,25.010491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2473-2472,17:44:03.047,25.012459 s,1.969 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2474,17:44:03.048,25.012950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2475-2474,17:44:03.048,25.013460 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2476,17:44:03.048,25.013485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2477-2476,17:44:03.050,25.015464 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2478,17:44:03.051,25.015967 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2479-2478,17:44:03.051,25.016460 s,494 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2480,17:44:03.051,25.016487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2481-2480,17:44:03.053,25.018462 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2482,17:44:03.054,25.018950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2483-2482,17:44:03.054,25.019459 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2484,17:44:03.054,25.019484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2485-2484,17:44:03.056,25.021460 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2486,17:44:03.057,25.021951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2487-2486,17:44:03.057,25.022460 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2488,17:44:03.057,25.022485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2489-2488,17:44:03.059,25.024461 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2490,17:44:03.060,25.024963 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2491-2490,17:44:03.060,25.025461 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2492,17:44:03.060,25.025489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2493-2492,17:44:03.062,25.027460 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2494,17:44:03.063,25.027950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2495-2494,17:44:03.063,25.028460 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2496,17:44:03.063,25.028485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2497-2496,17:44:03.065,25.030460 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2498,17:44:03.066,25.030962 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2499-2498,17:44:03.066,25.031460 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2500,17:44:03.066,25.031488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2501-2500,17:44:03.068,25.033460 s,1.971 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2502,17:44:03.069,25.033953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2503-2502,17:44:03.069,25.034459 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2504,17:44:03.069,25.034484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2505-2504,17:44:03.071,25.036459 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2506,17:44:03.072,25.036950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2507-2506,17:44:03.072,25.037460 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2508,17:44:03.072,25.037485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2509-2508,17:44:03.074,25.039466 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2510,17:44:03.075,25.039951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2511-2510,17:44:03.075,25.040463 s,512 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2512,17:44:03.075,25.040489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2513-2512,17:44:03.077,25.042464 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2514,17:44:03.078,25.042954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2515-2514,17:44:03.078,25.043464 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2516,17:44:03.078,25.043493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2517-2516,17:44:03.080,25.045471 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2518,17:44:03.081,25.045956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2519-2518,17:44:03.081,25.046482 s,526 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2520,17:44:03.081,25.046520 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2521-2520,17:44:03.083,25.048513 s,1.993 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2522,17:44:03.084,25.048960 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2523-2522,17:44:03.084,25.049488 s,528 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2524,17:44:03.084,25.049533 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2525-2524,17:44:03.086,25.051467 s,1.933 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2526,17:44:03.087,25.051951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2527-2526,17:44:03.087,25.052461 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2528,17:44:03.087,25.052486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2529-2528,17:44:03.089,25.054461 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2530,17:44:03.090,25.054950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2531-2530,17:44:03.090,25.055460 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2532,17:44:03.090,25.055484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2533-2532,17:44:03.092,25.057459 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2534,17:44:03.093,25.057950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2535-2534,17:44:03.093,25.058460 s,510 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2536,17:44:03.093,25.058484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2537-2536,17:44:03.095,25.060459 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2538,17:44:03.096,25.060950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2539-2538,17:44:03.096,25.061460 s,511 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2540,17:44:03.096,25.061484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2541-2540,17:44:03.098,25.063462 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2542,17:44:03.099,25.063950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2543-2542,17:44:03.099,25.064459 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2544,17:44:03.099,25.064483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2545-2544,17:44:03.101,25.066470 s,1.987 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2546,17:44:03.102,25.067003 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2547-2546,17:44:03.102,25.067459 s,456 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80089DFC60h,Success (Success) -URB,2548,17:44:03.102,25.067490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2549-2548,17:44:03.104,25.069485 s,1.995 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2550,17:44:03.105,25.070003 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2551-2550,17:44:03.105,25.070458 s,454 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2552,17:44:03.105,25.070489 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2553-2552,17:44:03.107,25.072462 s,1.973 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2554,17:44:03.108,25.072954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2555-2554,17:44:03.108,25.073459 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2556,17:44:03.108,25.073484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2557-2556,17:44:03.110,25.075458 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2558,17:44:03.111,25.075950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2559-2558,17:44:03.111,25.076458 s,508 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2560,17:44:03.111,25.076483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2561-2560,17:44:03.113,25.078459 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2562,17:44:03.114,25.078952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2563-2562,17:44:03.114,25.079459 s,507 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2564,17:44:03.114,25.079483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2565-2564,17:44:03.116,25.081459 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2566,17:44:03.117,25.081950 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2567-2566,17:44:03.117,25.082458 s,509 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2568,17:44:03.117,25.082482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2569-2568,17:44:03.119,25.084459 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2570,17:44:03.120,25.084952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2571-2570,17:44:03.120,25.085459 s,507 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2572,17:44:03.120,25.085483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2573-2572,17:44:03.122,25.087460 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2574,17:44:03.123,25.087951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2575-2574,17:44:03.123,25.088459 s,508 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2576,17:44:03.123,25.088483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2577-2576,17:44:03.125,25.090459 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2578,17:44:03.126,25.090954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2579-2578,17:44:03.126,25.091458 s,504 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2580,17:44:03.126,25.091483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2581-2580,17:44:03.128,25.093459 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2582,17:44:03.129,25.093951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2583-2582,17:44:03.129,25.094459 s,507 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2584,17:44:03.129,25.094482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2585-2584,17:44:03.131,25.096459 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2586,17:44:03.132,25.096951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2587-2586,17:44:03.132,25.097458 s,508 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2588,17:44:03.132,25.097482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2589-2588,17:44:03.134,25.099459 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2590,17:44:03.135,25.099954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2591-2590,17:44:03.135,25.100470 s,516 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2592,17:44:03.135,25.100505 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2593-2592,17:44:03.137,25.102463 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2594,17:44:03.138,25.102964 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2595-2594,17:44:03.138,25.103458 s,494 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2596,17:44:03.138,25.103484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2597-2596,17:44:03.140,25.105459 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2598,17:44:03.141,25.105951 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2599-2598,17:44:03.141,25.106459 s,508 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2600,17:44:03.141,25.106483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2601-2600,17:44:03.143,25.108458 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2602,17:44:03.144,25.108955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2603-2602,17:44:03.144,25.109458 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2604,17:44:03.144,25.109482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2605-2604,17:44:03.146,25.111458 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2606,17:44:03.147,25.111952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2607-2606,17:44:03.147,25.112458 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2608,17:44:03.147,25.112482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2609-2608,17:44:03.149,25.114462 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2610,17:44:03.150,25.114952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2611-2610,17:44:03.150,25.115458 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2612,17:44:03.150,25.115481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2613-2612,17:44:03.152,25.117461 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2614,17:44:03.153,25.117960 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2615-2614,17:44:03.153,25.118459 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2616,17:44:03.153,25.118486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2617-2616,17:44:03.155,25.120458 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2618,17:44:03.156,25.120953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2619-2618,17:44:03.156,25.121459 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2620,17:44:03.156,25.121482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2621-2620,17:44:03.158,25.123457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2622,17:44:03.159,25.123952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2623-2622,17:44:03.159,25.124457 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2624,17:44:03.159,25.124481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2625-2624,17:44:03.161,25.126458 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2626,17:44:03.162,25.126952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2627-2626,17:44:03.162,25.127458 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2628,17:44:03.162,25.127481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2629-2628,17:44:03.164,25.129458 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2630,17:44:03.165,25.129955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2631-2630,17:44:03.165,25.130458 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2632,17:44:03.165,25.130482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2633-2632,17:44:03.167,25.132458 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2634,17:44:03.168,25.132953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2635-2634,17:44:03.168,25.133458 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2636,17:44:03.168,25.133482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2637-2636,17:44:03.170,25.135458 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2638,17:44:03.171,25.135953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2639-2638,17:44:03.171,25.136458 s,506 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2640,17:44:03.171,25.136482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2641-2640,17:44:03.173,25.138458 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2642,17:44:03.174,25.138957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2643-2642,17:44:03.174,25.139458 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2644,17:44:03.174,25.139482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2645-2644,17:44:03.176,25.141457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2646,17:44:03.177,25.141953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2647-2646,17:44:03.177,25.142457 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2648,17:44:03.177,25.142481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2649-2648,17:44:03.179,25.144459 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2650,17:44:03.180,25.144952 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2651-2650,17:44:03.180,25.145457 s,505 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2652,17:44:03.180,25.145481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2653-2652,17:44:03.182,25.147457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2654,17:44:03.183,25.147953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2655-2654,17:44:03.183,25.148460 s,507 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2656,17:44:03.183,25.148484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2657-2656,17:44:03.185,25.150458 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2658,17:44:03.186,25.150956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2659-2658,17:44:03.186,25.151458 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2660,17:44:03.186,25.151482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2661-2660,17:44:03.188,25.153457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2662,17:44:03.189,25.153953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2663-2662,17:44:03.189,25.154457 s,504 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2664,17:44:03.189,25.154482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2665-2664,17:44:03.191,25.156457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2666,17:44:03.192,25.156953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2667-2666,17:44:03.192,25.157457 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2668,17:44:03.192,25.157480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2669-2668,17:44:03.194,25.159457 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2670,17:44:03.195,25.159953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2671-2670,17:44:03.195,25.160457 s,504 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2672,17:44:03.195,25.160480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2673-2672,17:44:03.197,25.162460 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2674,17:44:03.198,25.162953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2675-2674,17:44:03.198,25.163457 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2676,17:44:03.198,25.163480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2677-2676,17:44:03.200,25.165457 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2678,17:44:03.201,25.165953 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2679-2678,17:44:03.201,25.166457 s,504 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2680,17:44:03.201,25.166481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2681-2680,17:44:03.203,25.168457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2682,17:44:03.204,25.168956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2683-2682,17:44:03.204,25.169458 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2684,17:44:03.204,25.169482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2685-2684,17:44:03.206,25.171457 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2686,17:44:03.207,25.171955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2687-2686,17:44:03.207,25.172456 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2688,17:44:03.207,25.172480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2689-2688,17:44:03.209,25.174458 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2690,17:44:03.210,25.174954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2691-2690,17:44:03.210,25.175457 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2692,17:44:03.210,25.175482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2693-2692,17:44:03.212,25.177458 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2694,17:44:03.213,25.177957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2695-2694,17:44:03.213,25.178458 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2696,17:44:03.213,25.178481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2697-2696,17:44:03.215,25.180459 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2698,17:44:03.216,25.180956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2699-2698,17:44:03.216,25.181457 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2700,17:44:03.216,25.181481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2701-2700,17:44:03.218,25.183457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2702,17:44:03.219,25.183955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2703-2702,17:44:03.219,25.184457 s,503 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2704,17:44:03.219,25.184481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2705-2704,17:44:03.221,25.186457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2706,17:44:03.222,25.186954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2707-2706,17:44:03.222,25.187456 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2708,17:44:03.222,25.187480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2709-2708,17:44:03.224,25.189457 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2710,17:44:03.225,25.189958 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2711-2710,17:44:03.225,25.190456 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2712,17:44:03.225,25.190481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2713-2712,17:44:03.227,25.192457 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2714,17:44:03.228,25.192955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2715-2714,17:44:03.228,25.193456 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2716,17:44:03.228,25.193480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2717-2716,17:44:03.230,25.195456 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2718,17:44:03.231,25.195955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2719-2718,17:44:03.231,25.196459 s,504 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2720,17:44:03.231,25.196483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2721-2720,17:44:03.233,25.198457 s,1.974 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2722,17:44:03.234,25.198955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2723-2722,17:44:03.234,25.199457 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2724,17:44:03.234,25.199481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2725-2724,17:44:03.236,25.201456 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2726,17:44:03.237,25.201954 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2727-2726,17:44:03.237,25.202456 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2728,17:44:03.237,25.202481 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2729-2728,17:44:03.239,25.204456 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2730,17:44:03.240,25.204956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2731-2730,17:44:03.240,25.205456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2732,17:44:03.240,25.205479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2733-2732,17:44:03.242,25.207457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2734,17:44:03.243,25.207955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2735-2734,17:44:03.243,25.208456 s,501 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2736,17:44:03.243,25.208479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2737-2736,17:44:03.245,25.210459 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2738,17:44:03.246,25.210958 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2739-2738,17:44:03.246,25.211456 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2740,17:44:03.246,25.211480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2741-2740,17:44:03.248,25.213456 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2742,17:44:03.249,25.213955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2743-2742,17:44:03.249,25.214457 s,502 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2744,17:44:03.249,25.214480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2745-2744,17:44:03.251,25.216456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2746,17:44:03.252,25.216957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2747-2746,17:44:03.252,25.217456 s,499 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2748,17:44:03.252,25.217480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2749-2748,17:44:03.254,25.219456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2750,17:44:03.255,25.219955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2751-2750,17:44:03.255,25.220455 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2752,17:44:03.255,25.220479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2753-2752,17:44:03.257,25.222457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2754,17:44:03.258,25.222957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2755-2754,17:44:03.258,25.223456 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2756,17:44:03.258,25.223479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2757-2756,17:44:03.260,25.225457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2758,17:44:03.261,25.225955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2759-2758,17:44:03.261,25.226456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2760,17:44:03.261,25.226479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2761-2760,17:44:03.263,25.228456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2762,17:44:03.264,25.228957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2763-2762,17:44:03.264,25.229456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2764,17:44:03.264,25.229480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2765-2764,17:44:03.266,25.231456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2766,17:44:03.267,25.231956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2767-2766,17:44:03.267,25.232494 s,538 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2768,17:44:03.267,25.232518 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2769-2768,17:44:03.269,25.234456 s,1.938 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2770,17:44:03.270,25.234955 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2771-2770,17:44:03.270,25.235455 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2772,17:44:03.270,25.235478 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2773-2772,17:44:03.272,25.237456 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2774,17:44:03.273,25.237956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2775-2774,17:44:03.273,25.238456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2776,17:44:03.273,25.238479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2777-2776,17:44:03.275,25.240457 s,1.978 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2778,17:44:03.276,25.240956 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2779-2778,17:44:03.276,25.241456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2780,17:44:03.276,25.241479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2781-2780,17:44:03.278,25.243459 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2782,17:44:03.279,25.243965 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2783-2782,17:44:03.279,25.244458 s,492 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2784,17:44:03.279,25.244483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2785-2784,17:44:03.281,25.246455 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2786,17:44:03.282,25.246957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2787-2786,17:44:03.282,25.247456 s,500 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2788,17:44:03.282,25.247480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2789-2788,17:44:03.284,25.249456 s,1.976 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2790,17:44:03.285,25.249961 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2791-2790,17:44:03.285,25.250455 s,494 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2792,17:44:03.285,25.250480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2793-2792,17:44:03.287,25.252455 s,1.975 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2794,17:44:03.288,25.252957 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2795-2794,17:44:03.288,25.253455 s,498 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2796,17:44:03.288,25.253479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2797-2796,17:44:03.290,25.255456 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2798,17:44:03.291,25.255961 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2799-2798,17:44:03.291,25.256455 s,495 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2800,17:44:03.291,25.256479 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2801-2800,17:44:03.293,25.258459 s,1.979 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2802,17:44:03.493,25.457998 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2803-2802,17:44:03.494,25.459467 s,1.469 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2804,17:44:03.494,25.459504 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2805-2804,17:44:03.496,25.461453 s,1.949 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2806,17:44:03.696,25.661009 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2807-2806,17:44:03.696,25.661459 s,450 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2808,17:44:03.696,25.661497 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2809-2808,17:44:03.698,25.663451 s,1.954 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2810,17:44:03.898,25.863006 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2811-2810,17:44:03.899,25.864456 s,1.450 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2812,17:44:03.899,25.864490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2813-2812,17:44:03.901,25.866445 s,1.955 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2814,17:44:04.101,26.066042 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2815-2814,17:44:04.102,26.067440 s,1.397 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2816,17:44:04.102,26.067484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2817-2816,17:44:04.104,26.069440 s,1.957 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2818,17:44:04.304,26.269024 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2819-2818,17:44:04.305,26.270456 s,1.432 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2820,17:44:04.305,26.270494 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2821-2820,17:44:04.307,26.272438 s,1.944 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2822,17:44:04.507,26.472043 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2823-2822,17:44:04.508,26.473433 s,1.390 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2824,17:44:04.508,26.473470 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2825-2824,17:44:04.510,26.475432 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2826,17:44:04.710,26.675053 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2827-2826,17:44:04.711,26.676426 s,1.373 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2828,17:44:04.711,26.676465 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2829-2828,17:44:04.713,26.678449 s,1.984 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2830,17:44:04.913,26.878041 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2831-2830,17:44:04.914,26.879423 s,1.382 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2832,17:44:04.914,26.879458 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2833-2832,17:44:04.916,26.881424 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2834,17:44:05.116,27.081075 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2835-2834,17:44:05.117,27.082449 s,1.373 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2836,17:44:05.117,27.082493 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2837-2836,17:44:05.119,27.084422 s,1.929 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2838,17:44:05.319,27.284059 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2839-2838,17:44:05.319,27.284430 s,371 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2840,17:44:05.319,27.284465 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2841-2840,17:44:05.321,27.286417 s,1.952 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2842,17:44:05.521,27.486126 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2843-2842,17:44:05.522,27.487435 s,1.309 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2844,17:44:05.522,27.487488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2845-2844,17:44:05.524,27.489414 s,1.926 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2846,17:44:05.724,27.689111 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2847-2846,17:44:05.725,27.690425 s,1.314 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2848,17:44:05.725,27.690467 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2849-2848,17:44:05.727,27.692411 s,1.944 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2850,17:44:05.927,27.892084 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2851-2850,17:44:05.928,27.893411 s,1.327 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2852,17:44:05.928,27.893445 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2853-2852,17:44:05.930,27.895406 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2854,17:44:06.131,28.095131 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2855-2854,17:44:06.132,28.096402 s,1.271 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2856,17:44:06.132,28.096451 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2857-2856,17:44:06.134,28.098399 s,1.949 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2858,17:44:06.334,28.298115 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2859-2858,17:44:06.335,28.299412 s,1.297 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2860,17:44:06.335,28.299450 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2861-2860,17:44:06.337,28.301397 s,1.946 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2862,17:44:06.537,28.501282 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2863-2862,17:44:06.538,28.502510 s,1.228 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2864,17:44:06.538,28.502566 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2865-2864,17:44:06.540,28.504400 s,1.834 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2866,17:44:06.740,28.704127 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2867-2866,17:44:06.741,28.705415 s,1.288 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2868,17:44:06.741,28.705457 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2869-2868,17:44:06.743,28.707391 s,1.934 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2870,17:44:06.943,28.907119 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2871-2870,17:44:06.944,28.908393 s,1.273 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2872,17:44:06.944,28.908424 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2873-2872,17:44:06.946,28.910386 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2874,17:44:07.146,29.110143 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2875-2874,17:44:07.147,29.111401 s,1.257 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2876,17:44:07.147,29.111438 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2877-2876,17:44:07.149,29.113382 s,1.944 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2878,17:44:07.349,29.313134 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2879-2878,17:44:07.350,29.314382 s,1.248 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2880,17:44:07.350,29.314413 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2881-2880,17:44:07.352,29.316383 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2882,17:44:07.552,29.516148 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2883-2882,17:44:07.552,29.516414 s,266 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2884,17:44:07.552,29.516463 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2885-2884,17:44:07.554,29.518450 s,1.987 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2886,17:44:07.754,29.718162 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2887-2886,17:44:07.755,29.719393 s,1.231 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008618A00h,Success (Success) -URB,2888,17:44:07.755,29.719435 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2889-2888,17:44:07.757,29.721372 s,1.937 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2890,17:44:07.957,29.921162 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2891-2890,17:44:07.958,29.922380 s,1.217 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success) -URB,2892,17:44:07.958,29.922416 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2893-2892,17:44:07.960,29.924364 s,1.948 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2894,17:44:08.160,30.124182 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2895-2894,17:44:08.160,30.124382 s,200 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,Success (Success) -URB,2896,17:44:08.160,30.124421 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2897-2896,17:44:08.162,30.126362 s,1.941 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2898,17:44:08.362,30.326171 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2899-2898,17:44:08.363,30.327364 s,1.193 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,Success (Success) -URB,2900,17:44:08.363,30.327396 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2901-2900,17:44:08.365,30.329357 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2902,17:44:08.565,30.529243 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2903-2902,17:44:08.566,30.530370 s,1.128 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80090A2240h,Success (Success) -URB,2904,17:44:08.566,30.530416 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2905-2904,17:44:08.568,30.532354 s,1.939 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2906,17:44:08.768,30.732226 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2907-2906,17:44:08.769,30.733354 s,1.128 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,2908,17:44:08.769,30.733390 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2909-2908,17:44:08.771,30.735349 s,1.959 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2910,17:44:08.971,30.935204 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2911-2910,17:44:08.972,30.936358 s,1.153 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,2912,17:44:08.972,30.936394 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2913-2912,17:44:08.974,30.938344 s,1.951 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2914,17:44:09.174,31.138386 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2915-2914,17:44:09.176,31.140614 s,2.228 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2916,17:44:09.176,31.141138 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2917-2916,17:44:09.178,31.142377 s,1.239 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2918,17:44:09.378,31.342234 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2919-2918,17:44:09.379,31.343364 s,1.130 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2920,17:44:09.379,31.343409 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2921-2920,17:44:09.381,31.345338 s,1.929 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2922,17:44:09.581,31.545238 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2923-2922,17:44:09.582,31.546405 s,1.167 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2924,17:44:09.582,31.546476 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2925-2924,17:44:09.584,31.548397 s,1.921 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2926,17:44:09.784,31.748253 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2927-2926,17:44:09.785,31.749373 s,1.120 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2928,17:44:09.785,31.749432 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2929-2928,17:44:09.787,31.751333 s,1.901 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2930,17:44:09.987,31.951274 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2931-2930,17:44:09.989,31.953326 s,2.052 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2932,17:44:09.989,31.953367 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2933-2932,17:44:09.991,31.955325 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2934,17:44:10.191,32.155260 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2935-2934,17:44:10.192,32.156329 s,1.070 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2936,17:44:10.192,32.156369 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2937-2936,17:44:10.194,32.158322 s,1.953 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2938,17:44:10.394,32.358247 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2939-2938,17:44:10.395,32.359313 s,1.066 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2940,17:44:10.395,32.359348 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2941-2940,17:44:10.397,32.361314 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2942,17:44:10.597,32.561287 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2943-2942,17:44:10.599,32.563314 s,2.027 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2944,17:44:10.599,32.563356 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2945-2944,17:44:10.601,32.565313 s,1.956 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2946,17:44:10.801,32.765267 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2947-2946,17:44:10.802,32.766328 s,1.061 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2948,17:44:10.802,32.766362 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2949-2948,17:44:10.804,32.768308 s,1.946 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2950,17:44:11.004,32.968270 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2951-2950,17:44:11.006,32.970303 s,2.033 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2952,17:44:11.006,32.970338 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2953-2952,17:44:11.008,32.972304 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2954,17:44:11.208,33.172295 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2955-2954,17:44:11.210,33.174324 s,2.029 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2956,17:44:11.210,33.174368 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2957-2956,17:44:11.212,33.176304 s,1.936 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2958,17:44:11.412,33.376288 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2959-2958,17:44:11.414,33.378296 s,2.008 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2960,17:44:11.414,33.378329 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2961-2960,17:44:11.416,33.380306 s,1.977 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2962,17:44:11.616,33.580321 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2963-2962,17:44:11.618,33.582321 s,2.000 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2964,17:44:11.618,33.582364 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2965-2964,17:44:11.620,33.584295 s,1.931 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2966,17:44:11.820,33.784305 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2967-2966,17:44:11.822,33.786293 s,1.988 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2968,17:44:11.822,33.786326 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2969-2968,17:44:11.824,33.788296 s,1.970 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2970,17:44:12.024,33.988313 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2971-2970,17:44:12.026,33.990287 s,1.974 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2972,17:44:12.026,33.990323 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2973-2972,17:44:12.028,33.992287 s,1.964 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2974,17:44:12.228,34.192334 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2975-2974,17:44:12.230,34.194289 s,1.955 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2976,17:44:12.230,34.194328 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2977-2976,17:44:12.232,34.196282 s,1.954 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2978,17:44:12.432,34.396337 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2979-2978,17:44:12.433,34.398278 s,1.941 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2980,17:44:12.434,34.398314 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2981-2980,17:44:12.435,34.400277 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2982,17:44:12.636,34.600355 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2983-2982,17:44:12.637,34.602271 s,1.917 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2984,17:44:12.638,34.602318 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2985-2984,17:44:12.639,34.604272 s,1.954 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2986,17:44:12.840,34.804346 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2987-2986,17:44:12.841,34.806287 s,1.941 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2988,17:44:12.842,34.806326 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2989-2988,17:44:12.843,34.808271 s,1.945 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2990,17:44:13.043,35.007405 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2991-2990,17:44:13.044,35.009268 s,1.863 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008C93820h,Success (Success) -URB,2992,17:44:13.045,35.009318 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2993-2992,17:44:13.046,35.011270 s,1.952 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2994,17:44:13.247,35.211376 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2995-2994,17:44:13.248,35.213259 s,1.883 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,2996,17:44:13.248,35.213297 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,2997-2996,17:44:13.249,35.214282 s,985 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,2998,17:44:13.449,35.413373 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,2999-2998,17:44:13.450,35.415252 s,1.879 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,3000,17:44:13.450,35.415287 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3001-3000,17:44:13.452,35.417254 s,1.967 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3002,17:44:13.652,35.616388 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3003-3002,17:44:13.653,35.618251 s,1.864 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,3004,17:44:13.653,35.618291 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3005-3004,17:44:13.655,35.620252 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3006,17:44:13.855,35.819381 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3007-3006,17:44:13.856,35.821251 s,1.869 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,3008,17:44:13.856,35.821283 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3009-3008,17:44:13.858,35.823249 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3010,17:44:14.058,36.022442 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3011-3010,17:44:14.059,36.024267 s,1.826 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,3012,17:44:14.059,36.024319 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3013-3012,17:44:14.061,36.026260 s,1.941 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3014,17:44:14.261,36.225411 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3015-3014,17:44:14.262,36.227242 s,1.831 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,3016,17:44:14.262,36.227285 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3017-3016,17:44:14.264,36.229241 s,1.955 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3018,17:44:14.464,36.428427 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3019-3018,17:44:14.465,36.430249 s,1.822 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,3020,17:44:14.465,36.430285 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3021-3020,17:44:14.467,36.432237 s,1.952 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3022,17:44:14.667,36.631483 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3023-3022,17:44:14.668,36.633340 s,1.857 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA800897DB00h,Success (Success) -URB,3024,17:44:14.669,36.633598 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3025-3024,17:44:14.670,36.635238 s,1.640 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3026,17:44:14.870,36.834453 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3027-3026,17:44:14.871,36.836267 s,1.814 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success) -URB,3028,17:44:14.871,36.836320 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3029-3028,17:44:14.873,36.838287 s,1.968 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3030,17:44:15.073,37.037457 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3031-3030,17:44:15.074,37.039228 s,1.772 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success) -URB,3032,17:44:15.074,37.039285 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3033-3032,17:44:15.076,37.041226 s,1.942 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3034,17:44:15.276,37.240460 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3035-3034,17:44:15.277,37.242230 s,1.770 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success) -URB,3036,17:44:15.277,37.242280 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3037-3036,17:44:15.279,37.244225 s,1.945 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3038,17:44:15.479,37.443460 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3039-3038,17:44:15.480,37.445219 s,1.759 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success) -URB,3040,17:44:15.480,37.445264 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3041-3040,17:44:15.482,37.447218 s,1.954 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3042,17:44:15.682,37.646461 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3043-3042,17:44:15.683,37.648213 s,1.752 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success) -URB,3044,17:44:15.683,37.648253 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3045-3044,17:44:15.685,37.650214 s,1.961 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3046,17:44:15.885,37.849462 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3047-3046,17:44:15.886,37.851209 s,1.746 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success) -URB,3048,17:44:15.886,37.851247 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3049-3048,17:44:15.888,37.853208 s,1.962 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3050,17:44:16.088,38.052541 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3051-3050,17:44:16.089,38.054228 s,1.688 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success) -URB,3052,17:44:16.089,38.054373 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3053-3052,17:44:16.091,38.056220 s,1.847 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3054,17:44:16.291,38.255483 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3055-3054,17:44:16.292,38.257199 s,1.717 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success) -URB,3056,17:44:16.292,38.257234 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3057-3056,17:44:16.294,38.259200 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3058,17:44:16.494,38.458488 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3059-3058,17:44:16.495,38.460196 s,1.708 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success) -URB,3060,17:44:16.495,38.460231 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3061-3060,17:44:16.497,38.462220 s,1.989 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3062,17:44:16.697,38.661501 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3063-3062,17:44:16.698,38.663191 s,1.690 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success) -URB,3064,17:44:16.698,38.663232 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3065-3064,17:44:16.700,38.665190 s,1.958 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 -URB,3066,17:44:16.900,38.864494 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,3067-3066,17:44:16.901,38.866188 s,1.694 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008435C60h,Success (Success) -URB,3068,17:44:16.901,38.866223 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,3069-3068,17:44:16.903,38.868189 s,1.966 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 01 00 01 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 01 00 01 01 - -This report was generated by USBlyzer http://www.usblyzer.com/ diff --git a/toremove/stm32l_notes/notes b/toremove/stm32l_notes/notes deleted file mode 100644 index 242371e79..000000000 --- a/toremove/stm32l_notes/notes +++ /dev/null @@ -1,15 +0,0 @@ -. tools used for reversing under windows (all free or eval version) - . ST set tools package contains a working programmer (stvp) - . http://www.st.com/internet/com/SOFTWARE_RESOURCES/TOOL/TOOLSET/sttoolset.zip - . IAR latest version contains a working debugger - . http://www.iar.com/website1/1.0.1.0/68/1/ - . usblyzer to snif the corresponding usb frames - . http://www.usblyzer.com/ - -. Linux - . usb kernel module compiled with debugging enabled - . usbmon - . libusb - -. stm32l chip - . http://www.st.com/internet/mcu/product/248820.jsp \ No newline at end of file diff --git a/toremove/stm32l_notes/read_memory.csv b/toremove/stm32l_notes/read_memory.csv deleted file mode 100644 index 0d26683b4..000000000 --- a/toremove/stm32l_notes/read_memory.csv +++ /dev/null @@ -1,260 +0,0 @@ -USBlyzer Report - -Capture List - -Type,Seq,Time,Elapsed,Duration,Request,Request Details,Raw Data,I/O,C:I:E,Device Object,Device Name,Driver Name,IRP,Status -START,0001,15:09:38.756,,,,,,,,,,,, -Create,0002,15:12:32.934,174.174733 s,,Create,stvp.exe,,,,FFFFFA80074F4960h,,WinUsb,FFFFFA8006FD8320h, -Create,0003-0002,15:12:32.935,174.174759 s,26 us,Create,stvp.exe,,,,FFFFFA80074F4960h,,WinUsb,FFFFFA8006FD8320h,Success -URB,0004,15:12:32.935,174.174880 s,,Bulk or Interrupt Transfer,16 bytes data,F1 80 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F1 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0005-0004,15:12:32.936,174.176236 s,1.356 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0006,15:12:32.936,174.176269 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0007-0006,15:12:32.938,174.178222 s,1.953 ms,Bulk or Interrupt Transfer,6 bytes data,23 80 83 04 48 37,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),23 80 83 04 48 37 -URB,0008,15:12:32.938,174.178249 s,,Bulk or Interrupt Transfer,16 bytes data,F5 00 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0009-0008,15:12:32.939,174.179221 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0010,15:12:32.939,174.179239 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0011-0010,15:12:32.941,174.181221 s,1.982 ms,Bulk or Interrupt Transfer,2 bytes data,00 01,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 01 -URB,0012,15:12:32.941,174.181243 s,,Bulk or Interrupt Transfer,16 bytes data,F3 07 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F3 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0013-0012,15:12:32.942,174.182221 s,978 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0014,15:12:32.943,174.182760 s,,Bulk or Interrupt Transfer,16 bytes data,F2 30 A3 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 30 A3 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0015-0014,15:12:32.944,174.184221 s,1.462 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0016,15:12:32.944,174.184238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0017-0016,15:12:32.945,174.185221 s,982 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0018,15:12:32.945,174.185242 s,,Bulk or Interrupt Transfer,16 bytes data,F2 32 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 32 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0019-0018,15:12:32.946,174.186221 s,979 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0020,15:12:32.946,174.186239 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0021-0020,15:12:32.948,174.188221 s,1.982 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0022,15:12:32.948,174.188240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 03 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 35 F0 ED 00 E0 03 00 5F A0 00 00 00 00 00 00 -URB,0023-0022,15:12:32.949,174.189220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0024,15:12:32.949,174.189237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0025-0024,15:12:32.951,174.191221 s,1.983 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0026,15:12:32.951,174.191240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0027-0026,15:12:32.952,174.192221 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0028,15:12:32.952,174.192237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0029-0028,15:12:32.953,174.193222 s,985 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 00 03 00 03 03,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 03 00 03 03 -URB,0030,15:12:32.953,174.193242 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 03 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 35 F0 ED 00 E0 03 00 5F A0 00 00 00 00 00 00 -URB,0031-0030,15:12:32.954,174.194221 s,979 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0032,15:12:32.954,174.194239 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0033-0032,15:12:32.956,174.196221 s,1.981 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0034,15:12:32.956,174.196241 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0035-0034,15:12:32.957,174.197221 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0036,15:12:32.957,174.197240 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0037-0036,15:12:32.959,174.199220 s,1.980 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 00 03 00 03 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 03 00 03 00 -URB,0038,15:12:32.959,174.199240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 FC ED 00 E0 01 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 35 FC ED 00 E0 01 00 00 00 00 00 00 00 00 00 -URB,0039-0038,15:12:32.960,174.200220 s,979 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0040,15:12:32.960,174.200237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0041-0040,15:12:32.961,174.201221 s,984 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0042,15:12:32.961,174.201241 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 0C ED 00 E0 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 35 0C ED 00 E0 04 00 FA 05 00 00 00 00 00 00 -URB,0043-0042,15:12:32.962,174.202220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0044,15:12:32.962,174.202237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0045-0044,15:12:32.964,174.204220 s,1.983 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0046,15:12:32.964,174.204243 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 0C ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 36 0C ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0047-0046,15:12:32.965,174.205221 s,978 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0048,15:12:32.965,174.205238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0049-0048,15:12:32.967,174.207220 s,1.981 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 00 00 00 05 FA,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 00 00 05 FA -URB,0050,15:12:32.967,174.207239 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0051-0050,15:12:32.968,174.208219 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0052,15:12:32.968,174.208236 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0053-0052,15:12:32.969,174.209220 s,984 us,Bulk or Interrupt Transfer,8 bytes data,80 00 00 00 03 00 03 02,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 03 00 03 02 -URB,0054,15:12:32.969,174.209241 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0055-0054,15:12:32.970,174.210220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0056,15:12:32.970,174.210237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0057-0056,15:12:32.972,174.212221 s,1.984 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 00 03 00 03 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 03 00 03 00 -URB,0058,15:12:32.972,174.212240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 FC ED 00 E0 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 35 FC ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0059-0058,15:12:32.973,174.213220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0060,15:12:32.973,174.213237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0061-0060,15:12:32.975,174.215220 s,1.983 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0062,15:12:32.975,174.215241 s,,Bulk or Interrupt Transfer,16 bytes data,F2 31 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 31 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0063-0062,15:12:32.976,174.216220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0064,15:12:32.976,174.216238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0065-0064,15:12:32.977,174.217220 s,983 us,Bulk or Interrupt Transfer,12 bytes data,80 00 00 00 77 14 A0 2B...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 00 00 77 14 A0 2B 00 00 00 00 -URB,0066,15:12:32.977,174.217240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 20 04 E0 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 20 04 E0 04 00 00 00 00 00 00 00 00 00 -URB,0067-0066,15:12:32.978,174.218220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0068,15:12:32.978,174.218237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0069-0068,15:12:32.980,174.220220 s,1.983 ms,Bulk or Interrupt Transfer,4 bytes data,16 64 18 10,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),16 64 18 10 -URB,0070,15:12:32.980,174.220240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0071-0070,15:12:32.981,174.221220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0072,15:12:32.981,174.221237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0073-0072,15:12:32.983,174.223220 s,1.983 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0074,15:12:32.983,174.223243 s,,Bulk or Interrupt Transfer,16 bytes data,F2 34 0F 00 00 00 20 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 34 0F 00 00 00 20 00 00 00 00 00 00 00 00 00 -URB,0075-0074,15:12:32.984,174.224222 s,979 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0076,15:12:32.984,174.224239 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0077-0076,15:12:32.985,174.225220 s,981 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0078,15:12:32.985,174.225239 s,,Bulk or Interrupt Transfer,16 bytes data,F2 34 11 00 40 00 20 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 34 11 00 40 00 20 00 00 00 00 00 00 00 00 00 -URB,0079-0078,15:12:32.986,174.226221 s,981 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0080,15:12:32.986,174.226238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0081-0080,15:12:32.988,174.228225 s,1.987 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0082,15:12:32.988,174.228257 s,,Bulk or Interrupt Transfer,16 bytes data,F2 34 10 00 00 00 01 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 34 10 00 00 00 01 00 00 00 00 00 00 00 00 00 -URB,0083-0082,15:12:32.989,174.229225 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0084,15:12:32.989,174.229243 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0085-0084,15:12:32.991,174.231221 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0086,15:12:32.991,174.231244 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 00 00 00 20 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 08 00 00 00 20 04 00 00 00 00 00 00 00 00 00 -URB,0087-0086,15:12:32.992,174.232221 s,977 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0088,15:12:32.992,174.232239 s,,Bulk or Interrupt Transfer,4 bytes data,55 AA 88 00,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,55 AA 88 00 -URB,0089-0088,15:12:32.993,174.233221 s,982 us,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0090,15:12:32.993,174.233239 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0091-0090,15:12:32.994,174.234222 s,983 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0092,15:12:32.994,174.234242 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0093-0092,15:12:32.996,174.236221 s,1.979 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0094,15:12:32.996,174.236242 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 00 00 20 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 00 00 20 04 00 00 00 00 00 00 00 00 00 -URB,0095-0094,15:12:32.997,174.237221 s,979 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0096,15:12:32.997,174.237238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0097-0096,15:12:32.999,174.239222 s,1.984 ms,Bulk or Interrupt Transfer,4 bytes data,55 AA 88 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),55 AA 88 00 -URB,0098,15:12:32.999,174.239260 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0099-0098,15:12:33.000,174.240228 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0100,15:12:33.000,174.240266 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0101-0100,15:12:33.002,174.242226 s,1.960 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0102,15:12:33.002,174.242263 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 20 04 E0 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 20 04 E0 04 00 00 00 00 00 00 00 00 00 -URB,0103-0102,15:12:33.003,174.243226 s,964 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0104,15:12:33.003,174.243245 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0105-0104,15:12:33.005,174.245219 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes data,16 64 18 10,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),16 64 18 10 -URB,0106,15:12:33.005,174.245240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0107-0106,15:12:33.006,174.246220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0108,15:12:33.006,174.246237 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0109-0108,15:12:33.008,174.248219 s,1.982 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0110,15:12:33.008,174.248242 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 1C 3C 02 40 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 1C 3C 02 40 04 00 00 00 00 00 00 00 00 00 -URB,0111-0110,15:12:33.009,174.249219 s,977 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0112,15:12:33.009,174.249236 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0113-0112,15:12:33.010,174.250220 s,984 us,Bulk or Interrupt Transfer,4 bytes data,AA 00 78 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),AA 00 78 00 -URB,0114,15:12:33.010,174.250239 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0115-0114,15:12:33.011,174.251219 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0116,15:12:33.011,174.251236 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0117-0116,15:12:33.013,174.253220 s,1.983 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0118,15:12:33.013,174.253240 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 20 3C 02 40 04 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 20 3C 02 40 04 00 00 00 00 00 00 00 00 00 -URB,0119-0118,15:12:33.014,174.254220 s,980 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0120,15:12:33.014,174.254239 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0121-0120,15:12:33.016,174.256221 s,1.982 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 -URB,0122,15:12:33.016,174.256241 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0123-0122,15:12:33.017,174.257219 s,978 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0124,15:12:33.017,174.257236 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0125-0124,15:12:33.018,174.258220 s,984 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0126,15:12:33.018,174.258252 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 00 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 00 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0127-0126,15:12:33.019,174.259220 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0128,15:12:33.019,174.259241 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0129-0128,15:12:33.097,174.337240 s,77.999 ms,Bulk or Interrupt Transfer,4096 bytes data,28 06 00 20 69 58 00 08...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),28 06 00 20 69 58 00 08 91 54 00 08 93 54 00 08 95 54 00 08 97 54 00 08 99 54 00 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9B 54 00 08 9D 54 00 08 00 00 00 00 9F 54 00 08 A1 54 00 08 B1 58 00 08 B5 58 00 08 B9 58 00 08 75 56 00 08 C1 58 00 08 C5 58 00 08 27 56 00 08 CD 58 00 08 D1 58 00 08 D5 58 00 08 D9 58 00 08 DD 58 00 08 E1 58 00 08 E5 58 00 08 E9 58 00 08 ED 58 00 08 F1 58 00 08 F5 58 00 08 F9 58 00 08 FD 58 00 08 01 59 00 08 05 59 00 08 09 59 00 08 0D 59 00 08 11 59 00 08 15 59 00 08 19 59 00 08 1D 59 00 08 21 59 00 08 25 59 00 08 29 59 00 08 2D 59 00 08 31 59 00 08 35 59 00 08 39 59 00 08 3D 59 00 08 41 59 00 08 45 59 00 08 49 59 00 08 4D 59 00 08 51 59 00 08 55 59 00 08 59 59 00 08 5D 59 00 08 61 59 00 08 10 B5 84 B0 20 20 AD F8 00 00 AD F8 -URB,0130,15:12:33.097,174.337275 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0131-0130,15:12:33.099,174.339219 s,1.944 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0132,15:12:33.099,174.339238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0133-0132,15:12:33.101,174.341218 s,1.981 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0134,15:12:33.103,174.343580 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 10 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 10 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0135-0134,15:12:33.105,174.345221 s,1.641 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0136,15:12:33.105,174.345247 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0137-0136,15:12:33.183,174.423249 s,78.002 ms,Bulk or Interrupt Transfer,4096 bytes data,01 01 43 EA 81 31 11 43...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),01 01 43 EA 81 31 11 43 81 61 FF F7 CC FD 01 F0 A4 FD 31 BD 38 B5 04 46 01 25 07 E0 2B 46 00 22 11 46 20 46 FF F7 44 FE 64 1C 6D 1C 20 78 00 28 02 D0 ED B2 08 2D F1 D3 31 BD 38 B5 04 46 01 25 06 E0 00 22 11 46 00 A8 FF F7 32 FE A4 1C 6D 1C 20 88 00 28 1B D0 ED B2 08 2D 18 D2 8D F8 00 00 20 88 00 F4 70 40 B0 F5 80 4F 09 D0 B0 F5 00 4F 2B 46 E6 D1 00 22 01 21 00 A8 FF F7 19 FE E5 E7 2B 46 01 22 00 21 00 A8 FF F7 12 FE DE E7 31 BD 80 B5 04 20 01 F0 65 FD 00 28 FA D1 00 20 3F 49 02 46 02 E0 41 F8 20 20 40 1C 10 28 FA D3 BD E8 01 40 01 F0 52 BD 2D E9 F0 43 83 B0 05 46 0E 46 14 46 00 A8 07 21 01 F0 BB FD 00 2D 5E D0 28 46 00 27 02 E0 7F 1C FF B2 40 1C 01 78 00 29 F9 D1 28 46 FF F7 97 FF 20 46 00 F0 87 FB 4F F0 00 08 0A E0 20 46 00 F0 81 FB 09 F1 01 09 5F FA 89 F9 -URB,0138,15:12:33.183,174.423297 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0139-0138,15:12:33.185,174.425217 s,1.920 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0140,15:12:33.185,174.425240 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0141-0140,15:12:33.187,174.427221 s,1.981 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0142,15:12:33.189,174.428964 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 20 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 20 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0143-0142,15:12:33.190,174.430218 s,1.254 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0144,15:12:33.190,174.430240 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0145-0144,15:12:33.268,174.508249 s,78.008 ms,Bulk or Interrupt Transfer,4096 bytes data,0A 98 78 60 0C 98 F8 60...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),0A 98 78 60 0C 98 F8 60 0E 98 78 61 0D 98 38 61 FF F7 B1 FA 4F F4 00 60 00 F0 6F FE 00 20 00 F0 86 FE 00 20 00 F0 5B FE 00 20 00 F0 6D F8 FF F7 7F FD 01 20 00 F0 1D FF 01 20 00 F0 16 FE FE F7 7D FD 01 20 20 70 40 46 10 B0 BD E8 F0 81 00 00 18 ED 00 E0 00 E4 00 E0 10 E0 00 E0 34 01 00 20 00 00 02 40 00 04 02 40 00 08 02 40 00 0C 02 40 00 10 02 40 00 14 02 40 00 24 01 40 1C 38 02 40 22 02 00 20 23 02 00 20 10 B5 04 00 06 D0 01 2C 04 D0 B5 21 0F F2 00 20 FF F7 DC FB DF F8 C0 01 01 68 49 08 54 EA 41 01 01 60 10 BD 10 B5 04 00 06 D0 01 2C 04 D0 CB 21 0F F2 DC 10 FF F7 CA FB DF F8 9C 01 00 2C 01 68 03 D0 41 F0 02 01 01 60 10 BD 21 F0 02 01 01 60 10 BD 10 B5 04 00 06 D0 01 2C 04 D0 E6 21 0F F2 B0 10 FF F7 B3 FB DF F8 70 01 00 2C 01 68 03 D0 41 F0 04 01 01 60 10 BD -URB,0146,15:12:33.268,174.508317 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0147-0146,15:12:33.270,174.510218 s,1.900 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0148,15:12:33.270,174.510240 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0149-0148,15:12:33.272,174.512259 s,2.019 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0150,15:12:33.274,174.514519 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 30 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 30 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0151-0150,15:12:33.275,174.515232 s,712 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0152,15:12:33.275,174.515266 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0153-0152,15:12:33.353,174.593260 s,77.994 ms,Bulk or Interrupt Transfer,4096 bytes data,04 60 10 BD 10 B5 04 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),04 60 10 BD 10 B5 04 00 09 D0 01 2C 07 D0 05 2C 05 D0 40 F2 BD 11 0F F2 78 40 FE F7 1B FC DF F8 28 04 00 21 01 70 04 70 10 BD 10 B5 04 00 07 D0 01 2C 05 D0 40 F2 D5 11 0F F2 54 40 FE F7 0A FC DF F8 08 04 04 60 10 BD 10 B5 04 00 0B D0 01 2C 09 D0 02 2C 07 D0 03 2C 05 D0 40 F2 B7 21 0F F2 30 40 FE F7 F7 FB DF F8 E8 03 01 68 89 08 54 EA 81 01 01 60 10 BD DF F8 D8 03 00 68 00 F0 0C 00 70 47 10 B5 04 00 15 D0 80 2C 13 D0 90 2C 11 D0 A0 2C 0F D0 B0 2C 0D D0 C0 2C 0B D0 D0 2C 09 D0 E0 2C 07 D0 F0 2C 05 D0 40 F2 ED 21 0F F2 E0 30 FE F7 D0 FB DF F8 98 03 01 68 21 F0 F0 01 21 43 01 60 10 BD 10 B5 04 00 11 D0 B4 F5 80 6F 0E D0 B4 F5 A0 6F 0B D0 B4 F5 C0 6F 08 D0 B4 F5 E0 6F 05 D0 4F F4 43 71 0F F2 A8 30 FE F7 B3 FB DF F8 60 03 01 68 21 F4 E0 61 21 43 01 60 10 BD 10 B5 -URB,0154,15:12:33.353,174.593333 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0155-0154,15:12:33.355,174.595215 s,1.882 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0156,15:12:33.355,174.595238 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0157-0156,15:12:33.357,174.597214 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0158,15:12:33.359,174.599172 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 40 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 40 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0159-0158,15:12:33.360,174.600219 s,1.047 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0160,15:12:33.360,174.600245 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0161-0160,15:12:33.438,174.678234 s,77.989 ms,Bulk or Interrupt Transfer,4096 bytes data,B8 F1 04 0F 0E D0 B8 F1...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),B8 F1 04 0F 0E D0 B8 F1 05 0F 0B D0 B8 F1 06 0F 08 D0 B8 F1 07 0F 05 D0 40 F2 FF 21 0F F2 8C 10 FD F7 18 FC 07 21 14 2D 0B D3 E0 68 A5 F1 14 02 02 EB 42 02 91 40 88 43 08 FA 02 F1 08 43 E0 60 16 E0 0A 2D 0B D3 20 69 A5 F1 0A 02 02 EB 42 02 91 40 88 43 08 FA 02 F1 08 43 20 61 08 E0 60 69 05 EB 45 02 91 40 88 43 08 FA 02 F1 08 43 60 61 1F 21 07 2E 09 D2 20 6C 07 EB 87 02 91 40 88 43 05 FA 02 F1 08 43 20 64 33 E0 0D 2E 0A D2 E0 6B F2 1F 02 EB 82 02 91 40 88 43 05 FA 02 F1 08 43 E0 63 26 E0 13 2E 0B D2 A0 6B A6 F1 0D 02 02 EB 82 02 91 40 88 43 05 FA 02 F1 08 43 A0 63 18 E0 19 2E 0B D2 60 6B A6 F1 13 02 02 EB 82 02 91 40 88 43 05 FA 02 F1 08 43 60 63 0A E0 20 6B A6 F1 19 02 02 EB 82 02 91 40 88 43 05 FA 02 F1 08 43 20 63 BD E8 F0 81 10 B5 04 46 DF F8 3C 00 84 42 -URB,0162,15:12:33.438,174.678274 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0163-0162,15:12:33.440,174.680211 s,1.937 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0164,15:12:33.440,174.680231 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0165-0164,15:12:33.441,174.681211 s,980 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0166,15:12:33.443,174.682929 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 50 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 50 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0167-0166,15:12:33.443,174.683214 s,285 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0168,15:12:33.443,174.683237 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0169-0168,15:12:33.521,174.761232 s,77.994 ms,Bulk or Interrupt Transfer,4096 bytes data,41 02 08 4B 1B 68 03 EB...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),41 02 08 4B 1B 68 03 EB 42 02 52 89 96 3A 41 F2 F3 23 92 B2 9A 42 ED D3 FF 20 70 47 00 20 70 47 95 01 00 20 10 02 00 20 B8 01 00 20 24 02 00 20 30 01 00 20 F8 01 00 20 58 58 00 08 60 58 00 08 B0 01 00 20 A8 01 00 20 18 02 00 20 97 01 00 20 98 01 00 20 1A 02 00 20 1C 02 00 20 1E 02 00 20 84 58 00 08 00 01 00 08 00 02 00 00 00 00 A0 FF A0 00 20 00 00 00 60 FF 20 FF 60 00 00 00 00 00 10 B5 08 4C 00 20 20 83 01 20 00 F0 D8 F8 01 00 02 D0 20 8B 08 43 20 83 20 8B 00 28 01 D0 FF F7 61 FA 10 BD DC 01 00 20 2D E9 F8 4F 01 20 80 F3 10 88 DF F8 84 03 DF F8 84 13 02 68 0A 60 00 21 01 60 08 46 80 F3 10 88 DF F8 74 43 DF F8 74 B3 DF F8 74 63 DF F8 64 03 00 68 41 1E DF F8 5C 23 11 60 00 28 00 F0 A9 80 DF F8 60 73 38 78 40 1E 38 70 DF F8 5C 03 01 78 49 1E 01 70 C9 B2 00 29 -URB,0170,15:12:33.521,174.761271 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0171-0170,15:12:33.523,174.763211 s,1.940 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0172,15:12:33.523,174.763233 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0173-0172,15:12:33.525,174.765209 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0174,15:12:33.527,174.766919 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 60 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 60 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0175-0174,15:12:33.528,174.768211 s,1.291 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0176,15:12:33.528,174.768234 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0177-0176,15:12:33.604,174.844240 s,76.007 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0178,15:12:33.604,174.844301 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0179-0178,15:12:33.606,174.846214 s,1.913 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0180,15:12:33.606,174.846234 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0181-0180,15:12:33.608,174.848208 s,1.973 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0182,15:12:33.610,174.849977 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 70 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 70 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0183-0182,15:12:33.610,174.850213 s,236 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0184,15:12:33.610,174.850235 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0185-0184,15:12:33.687,174.927228 s,76.993 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0186,15:12:33.687,174.927268 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0187-0186,15:12:33.689,174.929206 s,1.939 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0188,15:12:33.689,174.929226 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0189-0188,15:12:33.690,174.930206 s,980 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0190,15:12:33.692,174.932148 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 80 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 80 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0191-0190,15:12:33.693,174.933211 s,1.062 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0192,15:12:33.693,174.933237 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0193-0192,15:12:33.769,175.009241 s,76.004 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0194,15:12:33.769,175.009307 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0195-0194,15:12:33.771,175.011249 s,1.942 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0196,15:12:33.771,175.011349 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0197-0196,15:12:33.773,175.013221 s,1.872 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0198,15:12:33.775,175.015272 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 90 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 90 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0199-0198,15:12:33.777,175.017218 s,1.946 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0200,15:12:33.777,175.017254 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0201-0200,15:12:33.853,175.093245 s,75.991 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0202,15:12:33.853,175.093309 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0203-0202,15:12:33.855,175.095204 s,1.895 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0204,15:12:33.855,175.095227 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0205-0204,15:12:33.857,175.097203 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0206,15:12:33.859,175.098972 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 A0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 A0 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0207-0206,15:12:33.859,175.099209 s,237 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0208,15:12:33.859,175.099233 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0209-0208,15:12:33.936,175.176223 s,76.990 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0210,15:12:33.936,175.176266 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0211-0210,15:12:33.938,175.178203 s,1.937 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0212,15:12:33.938,175.178223 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0213-0212,15:12:33.940,175.180202 s,1.979 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0214,15:12:33.942,175.181915 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 B0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 B0 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0215-0214,15:12:33.943,175.183205 s,1.291 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0216,15:12:33.943,175.183234 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0217-0216,15:12:34.019,175.259226 s,75.993 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0218,15:12:34.019,175.259275 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0219-0218,15:12:34.021,175.261201 s,1.926 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0220,15:12:34.021,175.261221 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0221-0220,15:12:34.023,175.263200 s,1.979 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0222,15:12:34.025,175.265126 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 C0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 C0 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0223-0222,15:12:34.026,175.266209 s,1.083 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0224,15:12:34.026,175.266234 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0225-0224,15:12:34.102,175.342223 s,75.989 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0226,15:12:34.102,175.342270 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0227-0226,15:12:34.104,175.344199 s,1.929 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0228,15:12:34.104,175.344219 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0229-0228,15:12:34.105,175.345202 s,983 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0230,15:12:34.107,175.346917 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 D0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 D0 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0231-0230,15:12:34.107,175.347202 s,285 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0232,15:12:34.107,175.347225 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0233-0232,15:12:34.184,175.424221 s,76.996 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0234,15:12:34.184,175.424272 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0235-0234,15:12:34.186,175.426198 s,1.926 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0236,15:12:34.186,175.426219 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0237-0236,15:12:34.188,175.428197 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0238,15:12:34.190,175.429912 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 E0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 07 00 E0 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0239-0238,15:12:34.191,175.431198 s,1.286 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0240,15:12:34.191,175.431220 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0241-0240,15:12:34.267,175.507225 s,76.005 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0242,15:12:34.267,175.507282 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0243-0242,15:12:34.269,175.509198 s,1.916 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8006FD8320h,Success (Success) -URB,0244,15:12:34.269,175.509228 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0245-0244,15:12:34.271,175.511235 s,2.007 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 -URB,0246,15:12:34.274,175.513803 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 00 F0 00 08 00 10...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8002902010h,,F2 07 00 F0 00 08 00 10 00 00 00 00 00 00 00 00 -URB,0247-0246,15:12:34.274,175.514220 s,417 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8002902010h,Success (Success) -URB,0248,15:12:34.274,175.514296 s,,Bulk or Interrupt Transfer,4096 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0249-0248,15:12:34.351,175.591234 s,76.938 ms,Bulk or Interrupt Transfer,4096 bytes data,00 00 00 00 00 00 00 00...,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0250,15:12:34.351,175.591304 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8002902010h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0251-0250,15:12:34.353,175.593195 s,1.891 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA8002902010h,Success (Success) -URB,0252,15:12:34.353,175.593216 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h, -URB,0253-0252,15:12:34.354,175.594194 s,978 us,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA800750D060h,USBPDO-10,usbhub,FFFFFA80072A3010h,Success (Success),80 00 - -This report was generated by USBlyzer http://www.usblyzer.com/ diff --git a/toremove/stm32l_notes/step_into.csv b/toremove/stm32l_notes/step_into.csv deleted file mode 100644 index a3d141f71..000000000 --- a/toremove/stm32l_notes/step_into.csv +++ /dev/null @@ -1,194 +0,0 @@ -USBlyzer Report - -Capture List - -Type,Seq,Time,Elapsed,Duration,Request,Request Details,Raw Data,I/O,C:I:E,Device Object,Device Name,Driver Name,IRP,Status -START,0001,17:41:03.981,,,,,,,,,,,, -URB,0002,17:41:09.226,5.245187 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0C 40 11 00 20 02 00 00 00 00 00 00 00 00 00 -URB,0003-0002,17:41:09.227,5.246467 s,1.280 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0004,17:41:09.227,5.246524 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0005-0004,17:41:09.229,5.248463 s,1.939 ms,Bulk or Interrupt Transfer,2 bytes data,70 47,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),70 47 -URB,0006,17:41:09.229,5.248519 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0007-0006,17:41:09.230,5.249462 s,943 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0008,17:41:09.230,5.249491 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0009-0008,17:41:09.232,5.251472 s,1.981 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0010,17:41:09.232,5.251514 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0C 40 11 00 20 02 00 00 00 00 00 00 00 00 00 -URB,0011-0010,17:41:09.233,5.252465 s,951 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0012,17:41:09.233,5.252495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0013-0012,17:41:09.235,5.254462 s,1.967 ms,Bulk or Interrupt Transfer,2 bytes data,70 47,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),70 47 -URB,0014,17:41:09.235,5.254493 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0015-0014,17:41:09.236,5.255462 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0016,17:41:09.236,5.255498 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0017-0016,17:41:09.238,5.257465 s,1.967 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0018,17:41:09.238,5.257575 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 36 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0C 36 11 00 20 02 00 00 00 00 00 00 00 00 00 -URB,0019-0018,17:41:09.239,5.258462 s,887 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0020,17:41:09.239,5.258490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0021-0020,17:41:09.241,5.260462 s,1.972 ms,Bulk or Interrupt Transfer,2 bytes data,05 4A,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),05 4A -URB,0022,17:41:09.241,5.260493 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0023-0022,17:41:09.242,5.261461 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0024,17:41:09.242,5.261486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0025-0024,17:41:09.244,5.263461 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0026,17:41:09.244,5.263495 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 07 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0027-0026,17:41:09.245,5.264470 s,975 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0028,17:41:09.245,5.264534 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0029-0028,17:41:09.247,5.266457 s,1.923 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 01 -URB,0030,17:41:09.247,5.266509 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0031-0030,17:41:09.248,5.267458 s,949 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0032,17:41:09.248,5.267484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0033-0032,17:41:09.250,5.269465 s,1.981 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0034,17:41:09.250,5.269495 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0035-0034,17:41:09.251,5.270461 s,966 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0036,17:41:09.251,5.270485 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 01 -URB,0037-0036,17:41:09.253,5.272462 s,1.977 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0038,17:41:09.253,5.272486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0039-0038,17:41:09.255,5.274460 s,1.974 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0040,17:41:09.255,5.274484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0041-0040,17:41:09.257,5.276460 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0042,17:41:09.257,5.276493 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 28 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 28 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0043-0042,17:41:09.258,5.277460 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0044,17:41:09.258,5.277485 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00 -URB,0045-0044,17:41:09.260,5.279461 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0046,17:41:09.260,5.279486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0047-0046,17:41:09.262,5.281461 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0048,17:41:09.262,5.281488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0049-0048,17:41:09.264,5.283461 s,1.972 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0050,17:41:09.264,5.283491 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 38 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 38 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0051-0050,17:41:09.265,5.284460 s,969 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0052,17:41:09.265,5.284484 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00 -URB,0053-0052,17:41:09.267,5.286461 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0054,17:41:09.267,5.286485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0055-0054,17:41:09.269,5.288460 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0056,17:41:09.269,5.288485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0057-0056,17:41:09.271,5.290460 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0058,17:41:09.271,5.290487 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 48 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 48 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0059-0058,17:41:09.272,5.291462 s,976 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0060,17:41:09.272,5.291486 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00 -URB,0061-0060,17:41:09.274,5.293460 s,1.974 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0062,17:41:09.274,5.293485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0063-0062,17:41:09.276,5.295460 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0064,17:41:09.276,5.295487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0065-0064,17:41:09.278,5.297460 s,1.973 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0066,17:41:09.278,5.297488 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 58 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 58 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0067-0066,17:41:09.279,5.298460 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0068,17:41:09.279,5.298485 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00 -URB,0069-0068,17:41:09.281,5.300460 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0070,17:41:09.281,5.300484 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0071-0070,17:41:09.283,5.302461 s,1.976 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0072,17:41:09.283,5.302485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0073-0072,17:41:09.285,5.304460 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0074,17:41:09.285,5.304502 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0C 40 11 00 20 02 00 00 00 00 00 00 00 00 00 -URB,0075-0074,17:41:09.286,5.305459 s,957 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0076,17:41:09.286,5.305483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0077-0076,17:41:09.288,5.307460 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,70 47,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),70 47 -URB,0078,17:41:09.288,5.307486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0079-0078,17:41:09.289,5.308460 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0080,17:41:09.289,5.308484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0081-0080,17:41:09.291,5.310459 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0082,17:41:09.291,5.310485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0D 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0D 40 11 00 20 02 00 00 00 00 00 00 00 00 00 -URB,0083-0082,17:41:09.292,5.311460 s,975 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0084,17:41:09.292,5.311483 s,,Bulk or Interrupt Transfer,2 bytes data,BE BE,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,BE BE -URB,0085-0084,17:41:09.294,5.313462 s,1.979 ms,Bulk or Interrupt Transfer,2 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0086,17:41:09.294,5.313486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0087-0086,17:41:09.296,5.315460 s,1.973 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0088,17:41:09.296,5.315487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0089-0088,17:41:09.298,5.317461 s,1.973 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0090,17:41:09.298,5.317488 s,,Bulk or Interrupt Transfer,16 bytes data,F2 35 F0 ED 00 E0 01 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 35 F0 ED 00 E0 01 00 5F A0 00 00 00 00 00 00 -URB,0091-0090,17:41:09.299,5.318460 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0092,17:41:09.299,5.318484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0093-0092,17:41:09.301,5.320459 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0094,17:41:09.302,5.321032 s,,Bulk or Interrupt Transfer,16 bytes data,F2 36 F0 ED 00 E0 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 36 F0 ED 00 E0 00 00 00 00 00 00 00 00 00 00 -URB,0095-0094,17:41:09.302,5.321463 s,431 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0096,17:41:09.302,5.321490 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0097-0096,17:41:09.304,5.323462 s,1.972 ms,Bulk or Interrupt Transfer,8 bytes data,80 00 00 01 03 00 03 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 03 00 03 01 -URB,0098,17:41:09.304,5.323500 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0D 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0D 40 11 00 20 02 00 00 00 00 00 00 00 00 00 -URB,0099-0098,17:41:09.305,5.324460 s,960 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0100,17:41:09.305,5.324491 s,,Bulk or Interrupt Transfer,2 bytes data,70 47,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,70 47 -URB,0101-0100,17:41:09.307,5.326459 s,1.968 ms,Bulk or Interrupt Transfer,2 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0102,17:41:09.307,5.326489 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0103-0102,17:41:09.309,5.328461 s,1.972 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0104,17:41:09.309,5.328488 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0105-0104,17:41:09.311,5.330458 s,1.971 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0106,17:41:09.311,5.330495 s,,Bulk or Interrupt Transfer,16 bytes data,F2 41 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 41 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0107-0106,17:41:09.312,5.331460 s,965 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0108,17:41:09.312,5.331487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0109-0108,17:41:09.314,5.333460 s,1.972 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0110,17:41:09.314,5.333511 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 07 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0111-0110,17:41:09.315,5.334459 s,949 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0112,17:41:09.315,5.334485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0113-0112,17:41:09.317,5.336460 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 01 -URB,0114,17:41:09.317,5.336490 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0115-0114,17:41:09.318,5.337458 s,968 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0116,17:41:09.318,5.337484 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0117-0116,17:41:09.320,5.339459 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0118,17:41:09.320,5.339487 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 FC ED 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 FC ED 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0119-0118,17:41:09.321,5.340459 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0120,17:41:09.321,5.340484 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 01,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 01 -URB,0121-0120,17:41:09.323,5.342460 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0122,17:41:09.323,5.342484 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0123-0122,17:41:09.325,5.344459 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0124,17:41:09.325,5.344483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0125-0124,17:41:09.327,5.346460 s,1.977 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0126,17:41:09.327,5.346487 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 28 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 28 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0127-0126,17:41:09.328,5.347459 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0128,17:41:09.328,5.347483 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00 -URB,0129-0128,17:41:09.330,5.349459 s,1.976 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0130,17:41:09.330,5.349484 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0131-0130,17:41:09.332,5.351459 s,1.975 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0132,17:41:09.332,5.351482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0133-0132,17:41:09.334,5.353460 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0134,17:41:09.334,5.353486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 38 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 38 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0135-0134,17:41:09.335,5.354459 s,973 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0136,17:41:09.335,5.354484 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00 -URB,0137-0136,17:41:09.337,5.356459 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0138,17:41:09.337,5.356487 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0139-0138,17:41:09.339,5.358460 s,1.972 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0140,17:41:09.339,5.358485 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0141-0140,17:41:09.341,5.360459 s,1.973 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0142,17:41:09.341,5.360486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 48 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 48 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0143-0142,17:41:09.342,5.361458 s,972 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0144,17:41:09.342,5.361483 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00 -URB,0145-0144,17:41:09.344,5.363461 s,1.979 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0146,17:41:09.344,5.363486 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0147-0146,17:41:09.346,5.365459 s,1.973 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0148,17:41:09.346,5.365483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0149-0148,17:41:09.348,5.367459 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0150,17:41:09.348,5.367485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 08 58 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 08 58 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0151-0150,17:41:09.349,5.368459 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0152,17:41:09.349,5.368483 s,,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,00 00 00 00 -URB,0153-0152,17:41:09.351,5.370458 s,1.975 ms,Bulk or Interrupt Transfer,4 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0154,17:41:09.351,5.370483 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0155-0154,17:41:09.353,5.372460 s,1.976 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0156,17:41:09.353,5.372483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0157-0156,17:41:09.355,5.374458 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0158,17:41:09.355,5.374493 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3A 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0159-0158,17:41:09.356,5.375459 s,966 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0160,17:41:09.356,5.375486 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0161-0160,17:41:09.361,5.380459 s,4.973 ms,Bulk or Interrupt Transfer,64 bytes data,80 00 00 01 00 00 00 20...,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 00 01 00 00 00 20 08 ED 00 E0 80 FF FF 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A0 19 00 20 6B 0E 00 20 -URB,0162,17:41:09.361,5.380468 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0163-0162,17:41:09.363,5.382453 s,1.984 ms,Bulk or Interrupt Transfer,24 bytes data,40 11 00 20 00 00 00 01...,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),40 11 00 20 00 00 00 01 A0 19 00 20 00 00 00 00 00 00 00 00 01 00 00 00 -URB,0164,17:41:09.363,5.382485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 0C 40 11 00 20 02 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 0C 40 11 00 20 02 00 00 00 00 00 00 00 00 00 -URB,0165-0164,17:41:09.364,5.383456 s,970 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0166,17:41:09.364,5.383480 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0167-0166,17:41:09.366,5.385458 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,70 47,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),70 47 -URB,0168,17:41:09.366,5.385484 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0169-0168,17:41:09.367,5.386458 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0170,17:41:09.367,5.386482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0171-0170,17:41:09.369,5.388460 s,1.978 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0172,17:41:09.369,5.388623 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 04 10 00 E0 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 07 04 10 00 E0 04 00 00 00 00 00 00 00 00 00 -URB,0173-0172,17:41:09.370,5.389462 s,839 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0174,17:41:09.370,5.389487 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0175-0174,17:41:09.372,5.391459 s,1.972 ms,Bulk or Interrupt Transfer,4 bytes data,00 00 00 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),00 00 00 00 -URB,0176,17:41:09.372,5.391485 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0177-0176,17:41:09.373,5.392459 s,974 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA80096BC490h,Success (Success) -URB,0178,17:41:09.373,5.392482 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0179-0178,17:41:09.375,5.394458 s,1.976 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 -URB,0180,17:41:09.386,5.405429 s,,Bulk or Interrupt Transfer,16 bytes data,F2 07 E4 19 00 20 04 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008A08C60h,,F2 07 E4 19 00 20 04 00 00 00 00 00 00 00 00 00 -URB,0181-0180,17:41:09.387,5.406464 s,1.035 ms,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008A08C60h,Success (Success) -URB,0182,17:41:09.387,5.406495 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0183-0182,17:41:09.389,5.408458 s,1.963 ms,Bulk or Interrupt Transfer,4 bytes data,67 14 00 20,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),67 14 00 20 -URB,0184,17:41:09.389,5.408487 s,,Bulk or Interrupt Transfer,16 bytes data,F2 3B 00 00 00 00 00 00...,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008A08C60h,,F2 3B 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -URB,0185-0184,17:41:09.390,5.409458 s,971 us,Bulk or Interrupt Transfer,16 bytes buffer,,out,01:00:02,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8008A08C60h,Success (Success) -URB,0186,17:41:09.390,5.409483 s,,Bulk or Interrupt Transfer,64 bytes buffer,,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h, -URB,0187-0186,17:41:09.392,5.411458 s,1.975 ms,Bulk or Interrupt Transfer,2 bytes data,80 00,in,01:00:81,FFFFFA8002E7E440h,USBPDO-12,usbhub,FFFFFA8009703010h,Success (Success),80 00 - -This report was generated by USBlyzer http://www.usblyzer.com/ From dae71f4a8e8a24753cfbcaa984fa67c84c0f7a90 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Wed, 9 Jul 2014 23:03:37 -0700 Subject: [PATCH 0272/1435] Remove unused code Remove unused #if 0'd code which has existed for years without being used. --- src/stlink-common.c | 97 +-------------------------------------------- 1 file changed, 2 insertions(+), 95 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index ce1306b12..9f7c18c97 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -355,16 +355,6 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { stlink_write_debug32(sl, FLASH_F4_CR, x); } -#if 0 /* todo */ - -static void disable_flash_read_protection(stlink_t *sl) { - /* erase the option byte area */ - /* rdp = 0x00a5; */ - /* reset */ -} -#endif /* todo */ - - // Delegates to the backends... void stlink_close(stlink_t *sl) { @@ -1089,19 +1079,6 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } } - /* unused: unlock the option byte block */ -#if 0 - stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0xfbead9c8); - stlink_write_debug32(sl, STM32L_FLASH_OPTKEYR, 0x24252627); - - /* check pecr.optlock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); - if (val & (1 << 2)) { - fprintf(stderr, "pecr.prglock not clear\n"); - return -1; - } -#endif - /* set pecr.{erase,prog} */ val |= (1 << 9) | (1 << 3); stlink_write_debug32(sl, STM32L_FLASH_PECR, val); @@ -1549,37 +1526,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t off += size; } -#if 0 -#define PROGRESS_CHUNK_SIZE 0x1000 - /* write a word in program memory */ - for (off = 0; off < len; off += sizeof(uint32_t)) { - uint32_t data; - if (sl->verbose >= 1) { - if ((off & (PROGRESS_CHUNK_SIZE - 1)) == 0) { - /* show progress. writing procedure is slow - and previous errors are misleading */ - const uint32_t pgnum = (off / PROGRESS_CHUNK_SIZE)+1; - const uint32_t pgcount = len / PROGRESS_CHUNK_SIZE +1; - fprintf(stdout, "Writing %ukB chunk %u out of %u\n", - PROGRESS_CHUNK_SIZE/1024, pgnum, pgcount); - } - } - - write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); - stlink_write_debug32(sl, addr + off, data); - - /* wait for sr.busy to be cleared */ - wait_flash_busy(sl); - - } -#endif /* Relock flash */ lock_flash(sl); -#if 0 /* todo: debug mode */ - fprintf(stdout, "Final CR:0x%x\n", read_flash_cr(sl)); -#endif - } //STM32F4END else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS @@ -1587,13 +1536,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t /* use fast word write. todo: half page. */ uint32_t val; -#if 0 /* todo: check write operation */ - - uint32_t nwrites = sl->flash_pgsz; - -redo_write: - -#endif /* todo: check write operation */ + /* todo: check write operation */ /* disable pecr protection */ stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); @@ -1645,44 +1588,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) ; -#if 0 /* todo: check redo write operation */ - - /* check written bytes. todo: should be on a per page basis. */ - data = stlink_read_debug32(sl, addr + off); - if (data == *(uint32_t*)(base + off)) { - /* re erase the page and redo the write operation */ - uint32_t page; - uint32_t val; - - /* fail if successive write count too low */ - if (nwrites < sl->flash_pgsz) { - fprintf(stderr, "writes operation failure count too high, aborting\n"); - return -1; - } - - nwrites = 0; - - /* assume addr aligned */ - if (off % sl->flash_pgsz) off &= ~(sl->flash_pgsz - 1); - page = addr + off; - - fprintf(stderr, "invalid write @0x%x(0x%x): 0x%x != 0x%x. retrying.\n", - page, addr + off, read_uint32(base + off, 0), read_uint32(sl->q_buf, 0)); - - /* reset lock bits */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR) - | (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - - stlink_erase_flash_page(sl, page); - - goto redo_write; - } - - /* increment successive writes counter */ - ++nwrites; + /* todo: check redo write operation */ -#endif /* todo: check redo write operation */ } fprintf(stdout, "\n"); /* reset lock bits */ From 3c3b02e83e358edee5e704eb61b96d7d1561ff42 Mon Sep 17 00:00:00 2001 From: Michael Pratt Date: Sat, 12 Jul 2014 13:19:41 -0700 Subject: [PATCH 0273/1435] gdbserver: use uglylogging logging Rather than putting debug printing in #ifdef blocks, use the same uglylogging framework used by core stlink code. To support this, the *LOG() macros are moved into the uglylogging.h header file, and always use the filename as the logging tag. --- gdbserver/gdb-server.c | 132 ++++++++++++++--------------------------- gdbserver/gdb-server.h | 11 ++++ src/stlink-common.c | 8 --- src/stlink-sg.c | 12 +--- src/stlink-usb.c | 6 -- src/test_sg.c | 6 -- src/uglylogging.h | 5 ++ 7 files changed, 61 insertions(+), 119 deletions(-) create mode 100644 gdbserver/gdb-server.h diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 71ab44016..37e116c89 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -1,4 +1,3 @@ -#define DEBUG 0 /* * Copyright (C) 2011 Peter Zotov * Use of this source code is governed by a BSD-style @@ -22,14 +21,10 @@ #endif #include +#include #include "gdb-remote.h" - -#define DEFAULT_LOGGING_LEVEL 50 -#define DEFAULT_GDB_LISTEN_PORT 4242 - -#define STRINGIFY_inner(name) #name -#define STRINGIFY(name) STRINGIFY_inner(name) +#include "gdb-server.h" #define FLASH_BASE 0x08000000 @@ -195,11 +190,11 @@ int main(int argc, char** argv) { stlink_reset(sl); } - printf("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); + ILOG("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); voltage = stlink_target_voltage(sl); if (voltage != -1) { - printf("Target voltage is %d mV.\n", voltage); + ILOG("Target voltage is %d mV.\n", voltage); } sl->verbose=0; @@ -382,9 +377,7 @@ struct code_hw_watchpoint { struct code_hw_watchpoint data_watches[DATA_WATCH_NUM]; static void init_data_watchpoints(stlink_t *sl) { -#if DEBUG - printf("init watchpoints\n"); -#endif + DLOG("init watchpoints\n"); // set trcena in debug command to turn on dwt unit stlink_write_debug32(sl, 0xE000EDFC, @@ -397,8 +390,8 @@ static void init_data_watchpoints(stlink_t *sl) { } } -static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len) -{ +static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, + stm32_addr_t addr, unsigned int len) { int i = 0; uint32_t mask; @@ -417,9 +410,7 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr for(i = 0; i < DATA_WATCH_NUM; i++) { // is this an empty slot ? if(data_watches[i].fun == WATCHDISABLED) { -#if DEBUG - printf("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len); -#endif + DLOG("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len); data_watches[i].fun = wf; data_watches[i].addr = addr; @@ -441,9 +432,7 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr } } -#if DEBUG - printf("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len); -#endif + DLOG("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len); return -1; } @@ -453,9 +442,7 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) for(i = 0 ; i < DATA_WATCH_NUM; i++) { if((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) { -#if DEBUG - printf("delete watchpoint %d addr %x\n", i, addr); -#endif + DLOG("delete watchpoint %d addr %x\n", i, addr); data_watches[i].fun = WATCHDISABLED; stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); @@ -464,9 +451,7 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) } } -#if DEBUG - printf("failure: delete watchpoint addr %x\n", addr); -#endif + DLOG("failure: delete watchpoint addr %x\n", addr); return -1; } @@ -490,7 +475,7 @@ static void init_code_breakpoints(stlink_t *sl) { if (((val & 3) != 1) || ((((val >> 8) & 0x70) | ((val >> 4) & 0xf)) != CODE_BREAK_NUM) || (((val >> 8) & 0xf) != CODE_LIT_NUM)){ - fprintf(stderr, "[FP_CTRL] = 0x%08x expecting 0x%08x\n", val, + ELOG("[FP_CTRL] = 0x%08x expecting 0x%08x\n", val, ((CODE_BREAK_NUM & 0x70) << 8) | (CODE_LIT_NUM << 8) | ((CODE_BREAK_NUM & 0xf) << 4) | 1); } @@ -506,7 +491,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { int type = addr & 0x2 ? CODE_BREAK_HIGH : CODE_BREAK_LOW; if(addr & 1) { - fprintf(stderr, "update_code_breakpoint: unaligned address %08x\n", addr); + ELOG("update_code_breakpoint: unaligned address %08x\n", addr); return -1; } @@ -532,20 +517,16 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { else brk->type &= ~type; if(brk->type == 0) { -#if DEBUG - printf("clearing hw break %d\n", id); -#endif + DLOG("clearing hw break %d\n", id); stlink_write_debug32(sl, 0xe0002008 + id * 4, 0); } else { uint32_t mask = (brk->addr) | 1 | (brk->type << 30); -#if DEBUG - printf("setting hw break %d at %08x (%d)\n", - id, brk->addr, brk->type); - printf("reg %08x \n", - mask); -#endif + DLOG("setting hw break %d at %08x (%d)\n", + id, brk->addr, brk->type); + DLOG("reg %08x \n", + mask); stlink_write_debug32(sl, 0xe0002008 + id * 4, mask); } @@ -567,13 +548,13 @@ static struct flash_block* flash_root; static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { if(addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) { - fprintf(stderr, "flash_add_block: incorrect bounds\n"); + ELOG("flash_add_block: incorrect bounds\n"); return -1; } stlink_calculate_pagesize(sl, addr); if(addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) { - fprintf(stderr, "flash_add_block: unaligned block\n"); + ELOG("flash_add_block: unaligned block\n"); return -1; } @@ -616,14 +597,14 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { } if(fit_blocks == 0) { - fprintf(stderr, "Unfit data block %08x -> %04x\n", addr, length); + ELOG("Unfit data block %08x -> %04x\n", addr, length); return -1; } if(fit_length != length) { - fprintf(stderr, "warning: data block %08x -> %04x truncated to %04x\n", + WLOG("data block %08x -> %04x truncated to %04x\n", addr, length, fit_length); - fprintf(stderr, "(this is not an error, just a GDB glitch)\n"); + WLOG("(this is not an error, just a GDB glitch)\n"); } return 0; @@ -636,9 +617,7 @@ static int flash_go(stlink_t *sl) { stlink_reset(sl); for(struct flash_block* fb = flash_root; fb; fb = fb->next) { -#if DEBUG - printf("flash_do: block %08x -> %04x\n", fb->addr, fb->length); -#endif + DLOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length); unsigned length = fb->length; for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += FLASH_PAGE) { @@ -646,9 +625,7 @@ static int flash_go(stlink_t *sl) { //Update FLASH_PAGE stlink_calculate_pagesize(sl, page); -#if DEBUG - printf("flash_do: page %08x\n", page); -#endif + DLOG("flash_do: page %08x\n", page); if(stlink_write_flash(sl, page, fb->data + (page - fb->addr), length > FLASH_PAGE ? FLASH_PAGE : length) < 0) @@ -698,7 +675,7 @@ int serve(stlink_t *sl, st_state_t *st) { return 1; } - printf("Listening at *:%d...\n", st->listen_port); + ILOG("Listening at *:%d...\n", st->listen_port); int client = accept(sock, NULL, NULL); //signal (SIGINT, SIG_DFL); @@ -716,7 +693,7 @@ int serve(stlink_t *sl, st_state_t *st) { init_code_breakpoints(sl); init_data_watchpoints(sl); - printf("GDB connected.\n"); + ILOG("GDB connected.\n"); /* * To allow resetting the chip from GDB it is required to @@ -729,13 +706,11 @@ int serve(stlink_t *sl, st_state_t *st) { int status = gdb_recv_packet(client, &packet); if(status < 0) { - fprintf(stderr, "cannot recv: %d\n", status); + ELOG("cannot recv: %d\n", status); return 1; } -#if DEBUG - printf("recv: %s\n", packet); -#endif + DLOG("recv: %s\n", packet); char* reply = NULL; reg regp; @@ -758,9 +733,7 @@ int serve(stlink_t *sl, st_state_t *st) { char* queryName = calloc(queryNameLength + 1, 1); strncpy(queryName, &packet[1], queryNameLength); -#if DEBUG - printf("query: %s;%s\n", queryName, params); -#endif + DLOG("query: %s;%s\n", queryName, params); if(!strcmp(queryName, "Supported")) { if(sl->chip_id==STM32_CHIPID_F4) { @@ -783,10 +756,8 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned addr = strtoul(__s_addr, NULL, 16), length = strtoul(s_length, NULL, 16); -#if DEBUG - printf("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", - type, op, annex, addr, length); -#endif + DLOG("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", + type, op, annex, addr, length); const char* data = NULL; @@ -820,9 +791,7 @@ int serve(stlink_t *sl, st_state_t *st) { if (!strncmp(params,"726573756d65",12)) {// resume -#if DEBUG - printf("Rcmd: resume\n"); -#endif + DLOG("Rcmd: resume\n"); stlink_run(sl); reply = strdup("OK"); @@ -831,9 +800,7 @@ int serve(stlink_t *sl, st_state_t *st) { stlink_force_debug(sl); -#if DEBUG - printf("Rcmd: halt\n"); -#endif + DLOG("Rcmd: halt\n"); } else if (!strncmp(params,"6a7461675f7265736574",20)) { //jtag_reset reply = strdup("OK"); @@ -841,9 +808,7 @@ int serve(stlink_t *sl, st_state_t *st) { stlink_jtag_reset(sl, 0); stlink_force_debug(sl); -#if DEBUG - printf("Rcmd: jtag_reset\n"); -#endif + DLOG("Rcmd: jtag_reset\n"); } else if (!strncmp(params,"7265736574",10)) { //reset reply = strdup("OK"); @@ -852,14 +817,9 @@ int serve(stlink_t *sl, st_state_t *st) { init_code_breakpoints(sl); init_data_watchpoints(sl); -#if DEBUG - printf("Rcmd: reset\n"); -#endif + DLOG("Rcmd: reset\n"); } else { -#if DEBUG - printf("Rcmd: %s\n", params); -#endif - + DLOG("Rcmd: %s\n", params); } } @@ -888,10 +848,8 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned addr = strtoul(__s_addr, NULL, 16), length = strtoul(s_length, NULL, 16); -#if DEBUG - printf("FlashErase: addr:%08x,len:%04x\n", - addr, length); -#endif + DLOG("FlashErase: addr:%08x,len:%04x\n", + addr, length); if(flash_add_block(addr, length, sl) < 0) { reply = strdup("E00"); @@ -926,9 +884,7 @@ int serve(stlink_t *sl, st_state_t *st) { if(dec_index % 2 != 0) dec_index++; -#if DEBUG - printf("binary packet %d -> %d\n", data_length, dec_index); -#endif + DLOG("binary packet %d -> %d\n", data_length, dec_index); if(flash_populate(addr, decoded, dec_index) < 0) { reply = strdup("E00"); @@ -959,7 +915,7 @@ int serve(stlink_t *sl, st_state_t *st) { while(1) { int status = gdb_check_for_interrupt(client); if(status < 0) { - fprintf(stderr, "cannot check for int: %d\n", status); + ELOG("cannot check for int: %d\n", status); return 1; } @@ -1267,13 +1223,11 @@ int serve(stlink_t *sl, st_state_t *st) { } if(reply) { -#if DEBUG - printf("send: %s\n", reply); -#endif + DLOG("send: %s\n", reply); int result = gdb_send_packet(client, reply); if(result != 0) { - fprintf(stderr, "cannot send: %d\n", result); + ELOG("cannot send: %d\n", result); free(reply); free(packet); return 1; diff --git a/gdbserver/gdb-server.h b/gdbserver/gdb-server.h new file mode 100644 index 000000000..8c8d47114 --- /dev/null +++ b/gdbserver/gdb-server.h @@ -0,0 +1,11 @@ +#ifndef _GDB_SERVER_H +#define _GDB_SERVER_H + +#define STRINGIFY_inner(name) #name +#define STRINGIFY(name) STRINGIFY_inner(name) + +#define DEFAULT_LOGGING_LEVEL 50 +#define DEBUG_LOGGING_LEVEL 100 +#define DEFAULT_GDB_LISTEN_PORT 4242 + +#endif diff --git a/src/stlink-common.c b/src/stlink-common.c index 9f7c18c97..4e78a1d01 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -18,14 +18,6 @@ #define O_BINARY 0 #endif - -#define LOG_TAG __FILE__ -#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) -#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) -#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) -#define ELOG(format, args...) ugly_log(UERROR, LOG_TAG, format, ## args) -#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) - /* todo: stm32l15xxx flash memory, pm0062 manual */ /* stm32f FPEC flash controller interface, pm0063 manual */ diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 1aefe6135..bfe41574c 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -91,12 +91,6 @@ #include "stlink-sg.h" #include "uglylogging.h" -#define LOG_TAG __FILE__ -#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) -#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) -#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) -#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) - static void clear_cdb(struct stlink_libsg *sl) { for (size_t i = 0; i < sizeof (sl->cdb_cmd_blk); i++) sl->cdb_cmd_blk[i] = 0; @@ -992,8 +986,7 @@ stlink_t* stlink_v1_open_inner(const int verbose) { stlink_version(sl); if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { - ugly_log(UERROR, LOG_TAG, - "WTF? successfully opened, but unable to read version details. BROKEN!\n"); + ELOG("WTF? successfully opened, but unable to read version details. BROKEN!\n"); return NULL; } @@ -1015,8 +1008,7 @@ stlink_t* stlink_v1_open_inner(const int verbose) { // re-query device info (and retest) stlink_version(sl); if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { - ugly_log(UERROR, LOG_TAG, - "WTF? successfully opened, but unable to read version details. BROKEN!\n"); + ELOG("WTF? successfully opened, but unable to read version details. BROKEN!\n"); return NULL; } diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 23ff19176..4a62d9dd5 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -10,12 +10,6 @@ #include "stlink-usb.h" #include "uglylogging.h" -#define LOG_TAG __FILE__ -#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) -#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) -#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) -#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) - /* code from bsd timersub.h http://www.gnu-darwin.org/www001/src/ports/net/libevnet/work/libevnet-0.3.8/libnostd/bsd/sys/time/timersub.h.html */ diff --git a/src/test_sg.c b/src/test_sg.c index dea6ffb21..db7eed325 100644 --- a/src/test_sg.c +++ b/src/test_sg.c @@ -10,12 +10,6 @@ #include "stlink-common.h" #include "uglylogging.h" -#define LOG_TAG __FILE__ -#define DLOG(format, args...) ugly_log(UDEBUG, LOG_TAG, format, ## args) -#define ILOG(format, args...) ugly_log(UINFO, LOG_TAG, format, ## args) -#define WLOG(format, args...) ugly_log(UWARN, LOG_TAG, format, ## args) -#define fatal(format, args...) ugly_log(UFATAL, LOG_TAG, format, ## args) - static void __attribute__((unused)) mark_buf(stlink_t *sl) { memset(sl->q_buf, 0, sizeof(sl->q_buf)); sl->q_buf[0] = 0xaa; diff --git a/src/uglylogging.h b/src/uglylogging.h index 5122820b9..7099d919c 100644 --- a/src/uglylogging.h +++ b/src/uglylogging.h @@ -18,6 +18,11 @@ extern "C" { int ugly_init(int maximum_threshold); int ugly_log(int level, const char *tag, const char *format, ...); +#define DLOG(format, args...) ugly_log(UDEBUG, __FILE__, format, ## args) +#define ILOG(format, args...) ugly_log(UINFO, __FILE__, format, ## args) +#define WLOG(format, args...) ugly_log(UWARN, __FILE__, format, ## args) +#define ELOG(format, args...) ugly_log(UERROR, __FILE__, format, ## args) +#define fatal(format, args...) ugly_log(UFATAL, __FILE__, format, ## args) #ifdef __cplusplus } From e12842b49215ce4a92007b707361d0a235002976 Mon Sep 17 00:00:00 2001 From: mux Date: Thu, 17 Jul 2014 00:46:18 +0200 Subject: [PATCH 0274/1435] Send F4 memory-map and features for STM32F429 * Fix issues #250 #196 --- gdbserver/gdb-server.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 37e116c89..5565b0b56 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -336,7 +336,7 @@ char* make_memory_map(stlink_t *sl) { char* map = malloc(4096); map[0] = '\0'; - if(sl->chip_id==STM32_CHIPID_F4) { + if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F4_HD) { strcpy(map, memory_map_template_F4); } else { snprintf(map, 4096, memory_map_template, @@ -736,7 +736,7 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("query: %s;%s\n", queryName, params); if(!strcmp(queryName, "Supported")) { - if(sl->chip_id==STM32_CHIPID_F4) { + if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F4_HD) { reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); } else { From ee68f1967aef7c70bf0dbba03095d912f05a3518 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ji=C5=99=C3=AD=20Netolick=C3=BD?= Date: Wed, 9 Jul 2014 15:13:31 +0200 Subject: [PATCH 0275/1435] Added support fo STM32L0x chip id and base params. --- src/stlink-common.h | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/src/stlink-common.h b/src/stlink-common.h index 898b2a59a..0a3c5d162 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -105,7 +105,7 @@ extern "C" { #define STM32_CHIPID_F1_HIGH 0x414 #define STM32_CHIPID_L1_MEDIUM 0x416 - +#define STM32_CHIPID_L0 0x417 #define STM32_CHIPID_F1_CONN 0x418 #define STM32_CHIPID_F4_HD 0x419 #define STM32_CHIPID_F1_VL_MEDIUM 0x420 @@ -377,7 +377,18 @@ extern "C" { .bootrom_base = 0x1fffd800, .bootrom_size = 0x2000 }, - }; + { + // STM32L0x + // RM0367,RM0377 documents was used to find these parameters + .chip_id = STM32_CHIPID_L0, + .description = "L0x3 device", + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000 + }, + }; typedef struct { From 44c645b7d74b7669b0e3988155528c2edcfbb05e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ji=C5=99=C3=AD=20Netolick=C3=BD?= Date: Fri, 1 Aug 2014 21:28:22 +0200 Subject: [PATCH 0276/1435] Add support for STM32L0x. First try to support new STM32L0x family. Tested on NUCLEO-L053R8 development board http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260001 Chid ID, read, erase and write flash works fine. --- flashloaders/stm32l0x.s | 66 ++++++++++++++++ src/stlink-common.c | 161 ++++++++++++++++++++++++++++------------ 2 files changed, 181 insertions(+), 46 deletions(-) create mode 100644 flashloaders/stm32l0x.s diff --git a/flashloaders/stm32l0x.s b/flashloaders/stm32l0x.s new file mode 100644 index 000000000..9fc44468f --- /dev/null +++ b/flashloaders/stm32l0x.s @@ -0,0 +1,66 @@ +/*************************************************************************** + * Copyright (C) 2010 by Spencer Oliver * + * spen@spen-soft.co.uk * + * * + * Copyright (C) 2011 Øyvind Harboe * + * oyvind.harboe@zylin.com * + * * + * Copyright (C) 2011 Clement Burin des Roziers * + * clement.burin-des-roziers@hikob.com * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ + + +// Build : arm-eabi-gcc -c stm32lx.S + .text + .syntax unified + .cpu cortex-m0plus + .thumb + .thumb_func + .global write + +/* + r0 - destination address + r1 - source address + r2 - count +*/ + + // Set 0 to r3 + movs r3, #0 + // Go to compare + b.n test_done + +write_word: + // Load one word from address in r0, increment by 4 + ldr r4, [r1] + // Store the word to address in r1, increment by 4 + str r4, [r0] + // Increment r3 + adds r3, #1 + adds r1, #4 + // does not matter, only first addr is important + // next 15 bytes are in sequnce RM0367 page 66 + adds r0, #4 + +test_done: + // Compare r3 and r2 + cmp r3, r2 + // Loop if not zero + bcc.n write_word + + // Set breakpoint to exit + bkpt #0x00 diff --git a/src/stlink-common.c b/src/stlink-common.c index 4e78a1d01..b2e68b2c7 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -63,6 +63,20 @@ #define FLASH_L1_FPRG 10 #define FLASH_L1_PROG 3 +//STM32L0x flash register base and offsets +//same as 32L1 above +#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define FLASH_ACR_OFF ((uint32_t) 0x00) +#define FLASH_PECR_OFF ((uint32_t) 0x04) +#define FLASH_PDKEYR_OFF ((uint32_t) 0x08) +#define FLASH_PEKEYR_OFF ((uint32_t) 0x0c) +#define FLASH_PRGKEYR_OFF ((uint32_t) 0x10) +#define FLASH_OPTKEYR_OFF ((uint32_t) 0x14) +#define FLASH_SR_OFF ((uint32_t) 0x18) +#define FLASH_OBR_OFF ((uint32_t) 0x1c) +#define FLASH_WRPR_OFF ((uint32_t) 0x20) + + //STM32F4 #define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) @@ -78,6 +92,8 @@ #define FLASH_F4_CR_SNB_MASK 0x38 #define FLASH_F4_SR_BSY 16 +#define L1_WRITE_BLOCK_SIZE 0x80 +#define L0_WRITE_BLOCK_SIZE 0x40 void write_uint32(unsigned char* buf, uint32_t ui) { if (!is_bigendian()) { // le -> le (don't swap) @@ -1041,30 +1057,37 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE + || sl->chip_id == STM32_CHIPID_L0) { uint32_t val; + uint32_t flash_regs_base; + if (sl->chip_id == STM32_CHIPID_L0) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; + } else { + flash_regs_base = STM32L_FLASH_REGS_ADDR; + } /* check if the locks are set */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); if((val & (1<<0))||(val & (1<<1))) { /* disable pecr protection */ - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405); /* check pecr.pelock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); if (val & (1 << 0)) { WLOG("pecr.pelock not clear (%#x)\n", val); return -1; } /* unlock program memory */ - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516); /* check pecr.prglock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); if (val & (1 << 1)) { WLOG("pecr.prglock not clear (%#x)\n", val); return -1; @@ -1073,8 +1096,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) /* set pecr.{erase,prog} */ val |= (1 << 9) | (1 << 3); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); #if 0 /* fix_to_be_confirmed */ /* wait for sr.busy to be cleared @@ -1095,13 +1117,13 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) page erase command, even though PM0062 recommends to wait before it. Test shows that a few iterations is performed in the following loop before busy bit is cleared.*/ - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) + while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) ; /* reset lock bits */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR) + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF) | (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 @@ -1138,7 +1160,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) int stlink_erase_flash_mass(stlink_t *sl) { if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE + || sl->chip_id == STM32_CHIPID_L0) { /* erase each page */ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1283,6 +1306,29 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x00, 0xbe }; + static const uint8_t loader_code_stm32l0[] = { + + /* + r0, input, dest addr + r1, input, source addr + r2, input, word count + r3, output, word count + */ + + 0x00, 0x23, + 0x04, 0xe0, + + 0x0c, 0x68, + 0x04, 0x66, + 0x01, 0x33, + 0x04, 0x31, + 0x04, 0x30, + + 0x93, 0x42, + 0xf8, 0xd3, + 0x00, 0xbe + }; + static const uint8_t loader_code_stm32f4[] = { // flashloaders/stm32f4.s @@ -1309,7 +1355,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { size_t loader_size; if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { /* stm32l */ + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { @@ -1322,7 +1368,10 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); - } else { + } else if (sl->chip_id == STM32_CHIPID_L0) { + loader_code = loader_code_stm32l0; + loader_size = sizeof(loader_code_stm32l0); + } else { ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); return -1; } @@ -1388,12 +1437,20 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, } -int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned num_half_pages) +int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize) { unsigned int count; + unsigned int num_half_pages = len / pagesize; uint32_t val; + uint32_t flash_regs_base; flash_loader_t fl; + if (sl->chip_id == STM32_CHIPID_L0) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; + } else { + flash_regs_base = STM32L_FLASH_REGS_ADDR; + } + ILOG("Starting Half page flash write for STM32L core id\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { @@ -1401,21 +1458,20 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uns return -1; } /* Unlock already done */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); val |= (1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); val |= (1 << FLASH_L1_PROG); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) {} + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) {} -#define L1_WRITE_BLOCK_SIZE 0x80 for (count = 0; count < num_half_pages; count ++) { - if (run_flash_loader(sl, &fl, addr + count * L1_WRITE_BLOCK_SIZE, base + count * L1_WRITE_BLOCK_SIZE, L1_WRITE_BLOCK_SIZE) == -1) { - WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * L1_WRITE_BLOCK_SIZE); - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + if (run_flash_loader(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) { + WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * pagesize); + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG)); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); return -1; } /* wait for sr.busy to be cleared */ @@ -1425,15 +1481,15 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uns fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); fflush(stdout); } - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) { + while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) { } } - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); val &= ~(1 << FLASH_L1_PROG); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); val &= ~(1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); return 0; } @@ -1524,40 +1580,51 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } //STM32F4END else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE + || sl->chip_id == STM32_CHIPID_L0) { /* use fast word write. todo: half page. */ uint32_t val; + uint32_t flash_regs_base; + uint32_t pagesize; + + if (sl->chip_id == STM32_CHIPID_L0) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; + pagesize = L0_WRITE_BLOCK_SIZE; + } else { + flash_regs_base = STM32L_FLASH_REGS_ADDR; + pagesize = L1_WRITE_BLOCK_SIZE; + } /* todo: check write operation */ /* disable pecr protection */ - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x89abcdef); - stlink_write_debug32(sl, STM32L_FLASH_PEKEYR, 0x02030405); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405); /* check pecr.pelock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); if (val & (1 << 0)) { fprintf(stderr, "pecr.pelock not clear\n"); return -1; } /* unlock program memory */ - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x8c9daebf); - stlink_write_debug32(sl, STM32L_FLASH_PRGKEYR, 0x13141516); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516); /* check pecr.prglock is cleared */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR); + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); if (val & (1 << 1)) { fprintf(stderr, "pecr.prglock not clear\n"); return -1; } off = 0; - if (len > L1_WRITE_BLOCK_SIZE) { - if (stm32l1_write_half_pages(sl, addr, base, len/L1_WRITE_BLOCK_SIZE) == -1) { + if (len > pagesize) { + if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) { /* This may happen on a blank device! */ WLOG("\nwrite_half_pages failed == -1\n"); } else { - off = (len /L1_WRITE_BLOCK_SIZE)*L1_WRITE_BLOCK_SIZE; + off = (len / pagesize)*pagesize; } } @@ -1577,7 +1644,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t stlink_write_debug32(sl, addr + off, data); /* wait for sr.busy to be cleared */ - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) + while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) ; /* todo: check redo write operation */ @@ -1585,9 +1652,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } fprintf(stdout, "\n"); /* reset lock bits */ - val = stlink_read_debug32(sl, STM32L_FLASH_PECR) + val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF) | (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, STM32L_FLASH_PECR, val); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { ILOG("Starting Flash write for VL/F0 core id\n"); /* flash loader initialization */ @@ -1680,7 +1747,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE + || sl->chip_id == STM32_CHIPID_L0) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1738,7 +1806,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons /* check written byte count */ if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE ) { + || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE + || sl->chip_id == STM32_CHIPID_L0) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; From 276be4fa42ba7a6fb6de7f8e1f8c0988de8dc708 Mon Sep 17 00:00:00 2001 From: Matteo Collina Date: Thu, 7 Aug 2014 08:39:15 +0200 Subject: [PATCH 0277/1435] Support for nucleo 411re. --- src/stlink-common.c | 34 +++++++++++++++++----------------- src/stlink-common.h | 11 +++++++++++ 2 files changed, 28 insertions(+), 17 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index b2e68b2c7..cd7979b23 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -152,7 +152,7 @@ static inline uint32_t read_flash_obr(stlink_t *sl) { static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t res; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) res = stlink_read_debug32(sl, FLASH_F4_CR); else res = stlink_read_debug32(sl, FLASH_CR); @@ -165,7 +165,7 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ) return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); else return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); @@ -178,7 +178,7 @@ static void unlock_flash(stlink_t *sl) { the FPEC block until next reset. */ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); } else { @@ -204,7 +204,7 @@ static int unlock_flash_if(stlink_t *sl) { static void lock_flash(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); stlink_write_debug32(sl, FLASH_F4_CR, n); } else { @@ -217,7 +217,7 @@ static void lock_flash(stlink_t *sl) { static void set_flash_cr_pg(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_CR_PG); stlink_write_debug32(sl, FLASH_F4_CR, x); @@ -230,7 +230,7 @@ static void set_flash_cr_pg(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) stlink_write_debug32(sl, FLASH_F4_CR, n); else stlink_write_debug32(sl, FLASH_CR, n); @@ -248,7 +248,7 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { static void set_flash_cr_mer(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); else @@ -258,7 +258,7 @@ static void set_flash_cr_mer(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); else @@ -268,7 +268,7 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { static void set_flash_cr_strt(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_F4_CR_STRT); stlink_write_debug32(sl, FLASH_F4_CR, x); @@ -285,7 +285,7 @@ static inline uint32_t read_flash_acr(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) res = stlink_read_debug32(sl, FLASH_F4_SR); else res = stlink_read_debug32(sl, FLASH_SR); @@ -295,7 +295,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { static inline unsigned int is_flash_busy(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); else return read_flash_sr(sl) & (1 << FLASH_SR_BSY); @@ -1012,7 +1012,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector<4) sl->flash_pgsz=0x4000; else if(sector<5) sl->flash_pgsz=0x10000; @@ -1030,7 +1030,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1362,7 +1362,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD){ + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE)){ loader_code = loader_code_stm32f4; loader_size = sizeof(loader_code_stm32f4); } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL) { @@ -1541,7 +1541,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t page_count, sl->flash_pgsz, sl->flash_pgsz); if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { /* todo: check write operation */ ILOG("Starting Flash write for F2/F4\n"); @@ -1772,7 +1772,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD) { + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE)) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1827,7 +1827,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD) { + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE)) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { diff --git a/src/stlink-common.h b/src/stlink-common.h index 0a3c5d162..532f7d928 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -113,6 +113,8 @@ extern "C" { #define STM32_CHIPID_F3 0x422 #define STM32_CHIPID_F4_LP 0x423 +#define STM32_CHIPID_F411RE 0x431 + #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427 #define STM32_CHIPID_F1_VL_HIGH 0x428 @@ -220,6 +222,15 @@ extern "C" { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800 }, + { + .chip_id = STM32_CHIPID_F411RE, + .description = "F4 device (low power) - stm32f411re", + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, { .chip_id = STM32_CHIPID_F4_DE, .description = "F4 device (Dynamic Efficency)", From fde9ec67435d2dad137a3d40d4ff5ce38f97b7d1 Mon Sep 17 00:00:00 2001 From: Rene Hopf Date: Wed, 13 Aug 2014 16:00:40 +0200 Subject: [PATCH 0278/1435] jtag reset --- flash/main.c | 10 +++++++--- src/stlink-usb.c | 2 +- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/flash/main.c b/flash/main.c index 8f5b351de..3e7c8143d 100644 --- a/flash/main.c +++ b/flash/main.c @@ -137,8 +137,10 @@ int main(int ac, char** av) if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); - if (o.reset) + if (o.reset){ + stlink_jtag_reset(sl,2); stlink_reset(sl); + } // Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 if (sl->chip_id == STM32_CHIPID_F4) @@ -196,8 +198,10 @@ int main(int ac, char** av) } } - if (o.reset) - stlink_reset(sl); + if (o.reset){ + stlink_jtag_reset(sl,2); + stlink_reset(sl); + } /* success */ err = 0; diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 4a62d9dd5..f6004d68c 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -432,7 +432,7 @@ void _stlink_usb_jtag_reset(stlink_t * sl, int value) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_JTAG_DRIVE_NRST; - cmd[i++] = (value)?0:1; + cmd[i++] = value; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { From 8f97b230fca22837643705449c49d82ce927ab5a Mon Sep 17 00:00:00 2001 From: Rene Hopf Date: Fri, 15 Aug 2014 10:44:24 +0200 Subject: [PATCH 0279/1435] gdb server fix, indentation --- flash/main.c | 10 +++++----- gdbserver/gdb-server.c | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/flash/main.c b/flash/main.c index 3e7c8143d..82803fe61 100644 --- a/flash/main.c +++ b/flash/main.c @@ -138,9 +138,9 @@ int main(int ac, char** av) stlink_enter_swd_mode(sl); if (o.reset){ - stlink_jtag_reset(sl,2); + stlink_jtag_reset(sl,2); stlink_reset(sl); - } + } // Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 if (sl->chip_id == STM32_CHIPID_F4) @@ -199,9 +199,9 @@ int main(int ac, char** av) } if (o.reset){ - stlink_jtag_reset(sl,2); - stlink_reset(sl); - } + stlink_jtag_reset(sl,2); + stlink_reset(sl); + } /* success */ err = 0; diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 5565b0b56..e5e754bd8 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -804,8 +804,8 @@ int serve(stlink_t *sl, st_state_t *st) { } else if (!strncmp(params,"6a7461675f7265736574",20)) { //jtag_reset reply = strdup("OK"); - stlink_jtag_reset(sl, 1); stlink_jtag_reset(sl, 0); + stlink_jtag_reset(sl, 1); stlink_force_debug(sl); DLOG("Rcmd: jtag_reset\n"); From 61fa5101e996abb3221486fbd7f71c6c0525c19a Mon Sep 17 00:00:00 2001 From: Martin Nowak Date: Wed, 20 Aug 2014 23:21:50 +0200 Subject: [PATCH 0280/1435] fix missing error msg when no suitable device is found --- src/stlink-usb.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index f6004d68c..d9faaa9f8 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -770,8 +770,7 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { devAddr=atoi(c); ILOG("bus %03d dev %03d\n",devBus, devAddr); } - while (cnt){ - cnt--; + while (cnt--){ libusb_get_device_descriptor( list[cnt], &desc ); if (desc.idVendor!=USB_ST_VID) continue; if (devBus && devAddr) From add3285b5de9f9a2d845e81c6d54d4553453eec7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lari=20Lehtom=C3=A4ki?= Date: Mon, 8 Sep 2014 18:49:11 +0300 Subject: [PATCH 0281/1435] Adds support for STM32F334 MCU --- src/stlink-common.c | 34 ++++++++++++++++++++++++++-------- src/stlink-common.h | 14 +++++++++++++- 2 files changed, 39 insertions(+), 9 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index cd7979b23..22f3655de 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1127,7 +1127,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 - || sl->chip_id == STM32_CHIPID_F37x) { + || sl->chip_id == STM32_CHIPID_F37x + || sl->chip_id == STM32_CHIPID_F334) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1358,7 +1359,8 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); - } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { + } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F37x || sl->chip_id == STM32_CHIPID_F334) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || @@ -1540,8 +1542,12 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t ILOG("Finished erasing %d pages of %d (%#x) bytes\n", page_count, sl->flash_pgsz, sl->flash_pgsz); - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { + if ((sl->chip_id == STM32_CHIPID_F2) || + (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || + (sl->chip_id == STM32_CHIPID_F4_HD) || + (sl->chip_id == STM32_CHIPID_F411RE)) { /* todo: check write operation */ ILOG("Starting Flash write for F2/F4\n"); @@ -1655,8 +1661,12 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF) | (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { - ILOG("Starting Flash write for VL/F0 core id\n"); + } else if (sl->core_id == STM32VL_CORE_ID || + sl->core_id == STM32F0_CORE_ID || + sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F334 || + sl->chip_id == STM32_CHIPID_F37x) { + ILOG("Starting Flash write for VL/F0/F3 core id\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { ELOG("init_flash_loader() == -1\n"); @@ -1759,7 +1769,11 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, count, 2); /* count (32 bits words) */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { + } else if (sl->core_id == STM32VL_CORE_ID || + sl->core_id == STM32F0_CORE_ID || + sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F37x || + sl->chip_id == STM32_CHIPID_F334) { size_t count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; @@ -1818,7 +1832,11 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || sl->chip_id == STM32_CHIPID_F37x) { + } else if (sl->core_id == STM32VL_CORE_ID || + sl->core_id == STM32F0_CORE_ID || + sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F37x || + sl->chip_id == STM32_CHIPID_F334) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { diff --git a/src/stlink-common.h b/src/stlink-common.h index 532f7d928..9f8b9cd70 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -125,7 +125,7 @@ extern "C" { #define STM32_CHIPID_L1_HIGH 0x436 #define STM32_CHIPID_L152_RE 0x437 - +#define STM32_CHIPID_F334 0x438 #define STM32_CHIPID_F3_SMALL 0x439 #define STM32_CHIPID_F0 0x440 @@ -399,6 +399,18 @@ extern "C" { .bootrom_base = 0x1ff0000, .bootrom_size = 0x1000 }, + { + // STM32F334 + // RM0364 document was used to find these parameters + .chip_id = STM32_CHIPID_F334, + .description = "F334 device", + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0x3000, + .bootrom_base = 0x1fffd800, + .bootrom_size = 0x2000 + }, + }; From b548f669672cecfa959aea66fb5663d5e76963d7 Mon Sep 17 00:00:00 2001 From: Victor Mayoral Vilches Date: Mon, 29 Sep 2014 14:26:20 -0700 Subject: [PATCH 0282/1435] Fix memory config for STM32F4 The previous memory map didn't allow to debug the whole flash memory. A new configuration has been added and should be used while working with the STM32F4Discovery. --- gdbserver/gdb-server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index e5e754bd8..6ea9baecf 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -306,7 +306,7 @@ static const char* const memory_map_template_F4 = " " //Sector 4 " 0x10000" //64kB " " - " " //Sectors 5..11 + " " //Sectors 5..11 " 0x20000" //128kB " " " " // peripheral regs From f84abb99ff48899d0667afc80d6cf66392d0a007 Mon Sep 17 00:00:00 2001 From: unknown Date: Fri, 3 Oct 2014 20:16:51 +0200 Subject: [PATCH 0283/1435] [ update ] add ST NUCLEO F030R8 as a working target in README --- README | 1 + 1 file changed, 1 insertion(+) diff --git a/README b/README index c0ccc7b73..4adb21fc6 100644 --- a/README +++ b/README @@ -185,5 +185,6 @@ Known Working Targets: STLink v2-1 (as found on the Nucleo boards) Known Working Targets: * STM32F401xx (STM32 Nucleo-F401RE board) +* STM32F030R8T6 (STM32 Nucleo-F030R8 board) Please report any and all known working combinations so I can update this! From c49ec2867804fb2a32a9cc0cc6f90cd785ff4bd2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bjo=CC=88rn=20Hauffe?= Date: Tue, 14 Oct 2014 20:58:11 +0200 Subject: [PATCH 0284/1435] add kernelextension for OS X 10.10 Yosemite --- stlinkv1_macosx_driver/README | 6 ++++++ stlinkv1_macosx_driver/osx.tar.gz | Bin 22405 -> 23580 bytes 2 files changed, 6 insertions(+) diff --git a/stlinkv1_macosx_driver/README b/stlinkv1_macosx_driver/README index 7b47f410f..0c0adba2d 100644 --- a/stlinkv1_macosx_driver/README +++ b/stlinkv1_macosx_driver/README @@ -30,3 +30,9 @@ P.S. If error `OS X version not supported` occurs. For the latest versions of Ma --- > ISOSXLION=$(sw_vers -productVersion | sed -e 's:.[[:digit:]]*$::') ``` +FOR OS X 10.10 Yosemite you must force the system to load unsigned kernelextensions +you can so this with this command + +sudo nvram boot-args="kext-dev-mode=1“ + +reboot the system! diff --git a/stlinkv1_macosx_driver/osx.tar.gz b/stlinkv1_macosx_driver/osx.tar.gz index 51a7a3248574e128d4a38b4624e7b26be8fa4a23..57bc314668c66f849b8fdcd50a5e38a430cac624 100644 GIT binary patch literal 23580 zcmZ^~V|1o5`z>DEwx-6^wr$&(+HRk^Q`@%fsohR(d#b7J=Q;Df=l93?aK2p0o$QsJ zmE2itCu?7%F>qjVE`l0hkXOB1$rQ5bWHQUkk6N!XQ>#Cx6*{J;bkKR#({N$C2{kON zsBjiN@W5@{0Dwt<6aJ5F9AjSFQ)jOH{o6Zjr-{7(jCu_VQppgxx;)l)U^OJx%+G}$b~H7vx@ zsC1JaV+)CYnb9(xB2I-@KLXtCy|R&DO-dFB1X_uK4@s1;W5R1wn*6=9LoQdLso-Bl zHMaM!@?*B2nzA8x+Lq{J#sV@96z71T(eARwFPRNX_jLL5ME=>F6R1CleF2j8>L^wLX3#<968KIOZoH!jE zHL(48y8sNsd|`jZlo`*T_DjFA{p3_&zhUp47H~_$zv=%ia5sXf{4Xq#EMnfjYKCl| zM$zO89fZAxiWKZEoElF&zz2X3-#;zM<{Hk`3+Ham9+>~Ug$;d$2mxdZ`itj`mn!}T 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If error `OS X version not supported` occurs. For the latest versions of Ma > ISOSXLION=$(sw_vers -productVersion | sed -e 's:.[[:digit:]]*$::') ``` FOR OS X 10.10 Yosemite you must force the system to load unsigned kernelextensions -you can so this with this command sudo nvram boot-args="kext-dev-mode=1“ From abe1a0f026807ad1aec26b3f1ac176fd053b661f Mon Sep 17 00:00:00 2001 From: Sven Wegener Date: Tue, 21 Oct 2014 10:04:10 +0200 Subject: [PATCH 0286/1435] SNB is wider than three bits on STM32F4 The SNB part of the FLASH_CR register is four bits wide on F4 devices and five bits wide on F4_HD devices. F4 devices have a reserved bit alongside the sector number, so just increase the bitmask to cover all five bits. Currently flashing breaks, if flahing sector eight and above before flashing lower sectors, because the highest bit is never unset. Signed-off-by: Sven Wegener --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 22f3655de..acc84169b 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -89,7 +89,7 @@ #define FLASH_F4_CR_LOCK 31 #define FLASH_F4_CR_SER 1 #define FLASH_F4_CR_SNB 3 -#define FLASH_F4_CR_SNB_MASK 0x38 +#define FLASH_F4_CR_SNB_MASK 0xf8 #define FLASH_F4_SR_BSY 16 #define L1_WRITE_BLOCK_SIZE 0x80 From 325dd000f2c7a40337180eb973234e4425f405ee Mon Sep 17 00:00:00 2001 From: lementec Date: Thu, 30 Oct 2014 14:38:36 +0100 Subject: [PATCH 0287/1435] update README, NUCLEO-F072RB as reported by kwikius --- README | 1 + 1 file changed, 1 insertion(+) diff --git a/README b/README index 4adb21fc6..6f0a1ade2 100644 --- a/README +++ b/README @@ -186,5 +186,6 @@ STLink v2-1 (as found on the Nucleo boards) Known Working Targets: * STM32F401xx (STM32 Nucleo-F401RE board) * STM32F030R8T6 (STM32 Nucleo-F030R8 board) +* STM32F072RBT6 (STM32 Nucleo-F072RB board) Please report any and all known working combinations so I can update this! From 10f07fccddb3a57568741ff847bec60e33868b6e Mon Sep 17 00:00:00 2001 From: Woodrow Douglass Date: Fri, 31 Oct 2014 10:47:34 -0400 Subject: [PATCH 0288/1435] Modify flash calculation functions to support 2MB devices in the STM32F4 series --- src/stlink-common.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index acc84169b..fca82284b 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1000,13 +1000,18 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, s } uint32_t calculate_F4_sectornum(uint32_t flashaddr){ + uint32_t offset = 0; flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address - if (flashaddr<0x4000) return (0); - else if(flashaddr<0x8000) return(1); - else if(flashaddr<0xc000) return(2); - else if(flashaddr<0x10000) return(3); - else if(flashaddr<0x20000) return(4); - else return(flashaddr/0x20000)+4; + if (flashaddr >= 0x100000) { + offset = 12; + flashaddr -= 0x100000; + } + if (flashaddr<0x4000) return (offset + 0); + else if(flashaddr<0x8000) return(offset + 1); + else if(flashaddr<0xc000) return(offset + 2); + else if(flashaddr<0x10000) return(offset + 3); + else if(flashaddr<0x20000) return(offset + 4); + else return offset + (flashaddr/0x20000) +4; } @@ -1014,6 +1019,9 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { uint32_t sector=calculate_F4_sectornum(flashaddr); + if (sector>= 12) { + sector -= 12; + } if (sector<4) sl->flash_pgsz=0x4000; else if(sector<5) sl->flash_pgsz=0x10000; else sl->flash_pgsz=0x20000; From e80d5d2359b28fe65737d4d24d0d92410ba314be Mon Sep 17 00:00:00 2001 From: Woodrow Douglass Date: Fri, 31 Oct 2014 13:54:37 -0400 Subject: [PATCH 0289/1435] use correct SNB values for high flash pages on 2mb devices. --- src/stlink-common.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index fca82284b..4d30287ad 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1050,6 +1050,10 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) uint32_t sector=calculate_F4_sectornum(flashaddr); fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); + + //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices... + if (sector >= 12) sector += 4; + write_flash_cr_snb(sl, sector); /* start erase operation */ From 3c39d6ba8033ac7777499d3795dfc4df0b463a12 Mon Sep 17 00:00:00 2001 From: lementec Date: Tue, 18 Nov 2014 10:55:41 +0100 Subject: [PATCH 0290/1435] add command line debug option to flash util --- flash/main.c | 31 +++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/flash/main.c b/flash/main.c index 82803fe61..f875692d1 100644 --- a/flash/main.c +++ b/flash/main.c @@ -9,6 +9,9 @@ #include #include "stlink-common.h" +#define DEBUG_LOG_LEVEL 100 +#define STND_LOG_LEVEL 50 + enum st_cmds {DO_WRITE = 0, DO_READ = 1, DO_ERASE = 2}; struct opts { @@ -18,14 +21,15 @@ struct opts stm32_addr_t addr; size_t size; int reset; + int log_level; }; static void usage(void) { - puts("stlinkv1 command line: ./flash [--reset] {read|write} /dev/sgX path addr "); - puts("stlinkv1 command line: ./flash /dev/sgX erase"); - puts("stlinkv2 command line: ./flash [--reset] {read|write} path addr "); - puts("stlinkv2 command line: ./flash erase"); + puts("stlinkv1 command line: ./flash [--debug] [--reset] {read|write} /dev/sgX path addr "); + puts("stlinkv1 command line: ./flash [--debug] /dev/sgX erase"); + puts("stlinkv2 command line: ./flash [--debug] [--reset] {read|write} path addr "); + puts("stlinkv2 command line: ./flash [--debug] erase"); puts(" use hex format for addr and "); } @@ -38,6 +42,17 @@ static int get_opts(struct opts* o, int ac, char** av) if (ac < 1) return -1; + if (strcmp(av[0], "--debug") == 0) + { + o->log_level = DEBUG_LOG_LEVEL; + ac--; + av++; + } + else + { + o->log_level = STND_LOG_LEVEL; + } + if (strcmp(av[0], "--reset") == 0) { o->reset = 1; @@ -120,15 +135,15 @@ int main(int ac, char** av) if (o.devname != NULL) /* stlinkv1 */ { - sl = stlink_v1_open(50, 1); + sl = stlink_v1_open(o.log_level, 1); if (sl == NULL) goto on_error; - sl->verbose = 50; + sl->verbose = o.log_level; } else /* stlinkv2 */ { - sl = stlink_open_usb(50, 1); + sl = stlink_open_usb(o.log_level, 1); if (sl == NULL) goto on_error; - sl->verbose = 50; + sl->verbose = o.log_level; } if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) From 23e03fa07428610cb67cfb2dcea720de20a3b778 Mon Sep 17 00:00:00 2001 From: lementec Date: Tue, 18 Nov 2014 11:05:51 +0100 Subject: [PATCH 0291/1435] check stlink_load_device_params --- src/stlink-usb.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index d9faaa9f8..d0baa0deb 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -864,10 +864,8 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { if (reset) { stlink_reset(sl); } - stlink_load_device_params(sl); stlink_version(sl); - - error = 0; + error = stlink_load_device_params(sl); on_libusb_error: if (devs != NULL) { @@ -887,6 +885,6 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { libusb_exit(slu->libusb_ctx); if (sl != NULL) free(sl); if (slu != NULL) free(slu); - return 0; + return NULL; } From 7d6dad8546efad7e55a82c3668cef7b49062c05e Mon Sep 17 00:00:00 2001 From: texane Date: Mon, 24 Nov 2014 16:29:09 -0600 Subject: [PATCH 0292/1435] Improve error message for not able to open --- src/stlink-usb.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index d0baa0deb..d8b6c4673 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -5,6 +5,7 @@ #include #include #include +#include #include "stlink-common.h" #include "stlink-usb.h" @@ -788,7 +789,8 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { } else { int error = libusb_open(list[cnt], &slu->usb_handle); if( error !=0 ) { - WLOG("Error %d opening ST-Link/V2 device %03d:%03d\n", error, libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); + WLOG("Error %d (%s) opening ST-Link/V2 device %03d:%03d\n", + error, strerror (errno), libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); goto on_error; } } From d04fcf5cb68161d08ff98cd9d92b0d81b9242ce2 Mon Sep 17 00:00:00 2001 From: Rene Hopf Date: Tue, 2 Dec 2014 18:33:36 +0100 Subject: [PATCH 0293/1435] Support for stm32f100 low density devices --- src/stlink-common.c | 6 ++++++ src/stlink-common.h | 10 +++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 4d30287ad..2e45d42b9 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -478,6 +478,12 @@ int stlink_load_device_params(stlink_t *sl) { sl->sys_base = params->bootrom_base; sl->sys_size = params->bootrom_size; + //medium and low devices have the same chipid. ram size depends on flash size. + //STM32F100xx datasheet Doc ID 16455 Table 2 + if(sl->chip_id == STM32_CHIPID_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){ + sl->sram_size = 0x1000; + } + ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); // TODO make note of variable page size here..... ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n", diff --git a/src/stlink-common.h b/src/stlink-common.h index 9f8b9cd70..0379753b9 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -108,7 +108,7 @@ extern "C" { #define STM32_CHIPID_L0 0x417 #define STM32_CHIPID_F1_CONN 0x418 #define STM32_CHIPID_F4_HD 0x419 -#define STM32_CHIPID_F1_VL_MEDIUM 0x420 +#define STM32_CHIPID_F1_VL_MEDIUM_LOW 0x420 #define STM32_CHIPID_F3 0x422 #define STM32_CHIPID_F4_LP 0x423 @@ -296,12 +296,12 @@ extern "C" { .bootrom_base = 0x1fffb000, .bootrom_size = 0x4800 }, - { - .chip_id = STM32_CHIPID_F1_VL_MEDIUM, - .description = "F1 Medium-density Value Line device", + {//Low and Medium density VL have same chipid. RM0041 25.6.1 + .chip_id = STM32_CHIPID_F1_VL_MEDIUM_LOW, + .description = "F1 Medium/Low-density Value Line device", .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, - .sram_size = 0x2000, + .sram_size = 0x2000,//0x1000 for low density devices .bootrom_base = 0x1ffff000, .bootrom_size = 0x800 }, From 067430469a94cb3266585db88b8fb7e8f97c8857 Mon Sep 17 00:00:00 2001 From: Stefan Misik Date: Wed, 24 Dec 2014 22:36:44 +0100 Subject: [PATCH 0294/1435] Added AHB3 Peripherals definition for STM32F4 --- gdbserver/gdb-server.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 6ea9baecf..f0e965374 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -310,6 +310,7 @@ static const char* const memory_map_template_F4 = " 0x20000" //128kB " " " " // peripheral regs + " " // AHB3 Peripherals " " // cortex regs " " // bootrom " " // option byte area From cbab4b1e34b91622ae0bd879f540a66bc0d9b9c1 Mon Sep 17 00:00:00 2001 From: texane Date: Thu, 25 Dec 2014 21:31:26 -0600 Subject: [PATCH 0295/1435] update README for STM32F103RB support --- README | 1 + 1 file changed, 1 insertion(+) diff --git a/README b/README index 6f0a1ade2..ec58e9bb2 100644 --- a/README +++ b/README @@ -187,5 +187,6 @@ Known Working Targets: * STM32F401xx (STM32 Nucleo-F401RE board) * STM32F030R8T6 (STM32 Nucleo-F030R8 board) * STM32F072RBT6 (STM32 Nucleo-F072RB board) +* STM32F103RB (STM32 Nucleo-F103RB board) Please report any and all known working combinations so I can update this! From 845d9ea7cd419d437f5a5902da2e321414791230 Mon Sep 17 00:00:00 2001 From: Nic McDonald Date: Tue, 13 Jan 2015 13:19:34 -0800 Subject: [PATCH 0296/1435] added Nucleo F334R8 to README --- README | 1 + 1 file changed, 1 insertion(+) diff --git a/README b/README index ec58e9bb2..cedbd2474 100644 --- a/README +++ b/README @@ -188,5 +188,6 @@ Known Working Targets: * STM32F030R8T6 (STM32 Nucleo-F030R8 board) * STM32F072RBT6 (STM32 Nucleo-F072RB board) * STM32F103RB (STM32 Nucleo-F103RB board) +* STM32F334R8 (STM32 Nucleo-F334R8 board) Please report any and all known working combinations so I can update this! From f68e4c201f2defeb8fa8f7812887c4509f6c4808 Mon Sep 17 00:00:00 2001 From: Nic McDonald Date: Wed, 14 Jan 2015 22:52:13 -0800 Subject: [PATCH 0297/1435] change flash to st-flash Previous commit changed binary "flash" to "st-flash" but the actual code printed help message still called it "flash". This commit changes it to "st-flash". --- flash/main.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/flash/main.c b/flash/main.c index f875692d1..f84323217 100644 --- a/flash/main.c +++ b/flash/main.c @@ -26,17 +26,17 @@ struct opts static void usage(void) { - puts("stlinkv1 command line: ./flash [--debug] [--reset] {read|write} /dev/sgX path addr "); - puts("stlinkv1 command line: ./flash [--debug] /dev/sgX erase"); - puts("stlinkv2 command line: ./flash [--debug] [--reset] {read|write} path addr "); - puts("stlinkv2 command line: ./flash [--debug] erase"); + puts("stlinkv1 command line: ./st-flash [--debug] [--reset] {read|write} /dev/sgX path addr "); + puts("stlinkv1 command line: ./st-flash [--debug] /dev/sgX erase"); + puts("stlinkv2 command line: ./st-flash [--debug] [--reset] {read|write} path addr "); + puts("stlinkv2 command line: ./st-flash [--debug] erase"); puts(" use hex format for addr and "); } static int get_opts(struct opts* o, int ac, char** av) { - /* stlinkv1 command line: ./flash {read|write} /dev/sgX path addr */ - /* stlinkv2 command line: ./flash {read|write} path addr */ + /* stlinkv1 command line: ./st-flash {read|write} /dev/sgX path addr */ + /* stlinkv2 command line: ./st-flash {read|write} path addr */ unsigned int i = 0; From 2daeabaead8c45bc8ead84c59391ece6c0bbcfac Mon Sep 17 00:00:00 2001 From: Ethan Zonca Date: Sat, 17 Jan 2015 14:24:38 -0500 Subject: [PATCH 0298/1435] Added support for flashing STM32F042 --- src/stlink-common.c | 2 +- src/stlink-common.h | 13 +++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 2e45d42b9..6e327f028 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1385,7 +1385,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE)){ loader_code = loader_code_stm32f4; loader_size = sizeof(loader_code_stm32f4); - } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL) { + } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); } else if (sl->chip_id == STM32_CHIPID_L0) { diff --git a/src/stlink-common.h b/src/stlink-common.h index 0379753b9..ca50c910c 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -132,6 +132,8 @@ extern "C" { #define STM32_CHIPID_F0_SMALL 0x444 +#define STM32_CHIPID_F04 0x445 + #define STM32_CHIPID_F0_CAN 0x448 /* @@ -367,6 +369,17 @@ extern "C" { .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 }, + { + //Use this as an example for mapping future chips: + //RM0091 document was used to find these paramaters + .chip_id = STM32_CHIPID_F04, + .description = "F04x device", + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + }, { //Use this as an example for mapping future chips: //RM0091 document was used to find these paramaters From b2dac269232543ae595e349b1c5b64b6d0cb5af6 Mon Sep 17 00:00:00 2001 From: Simon Wright Date: Fri, 23 Jan 2015 20:43:23 +0000 Subject: [PATCH 0299/1435] Extra RAM for STM32F42xx. --- gdbserver/gdb-server.c | 27 ++++++++++++++++++++++++++- src/stlink-common.h | 2 +- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 6ea9baecf..275370991 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -315,6 +315,29 @@ static const char* const memory_map_template_F4 = " " // option byte area ""; +static const char* const memory_map_template_F4_HD = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // ccm ram + " " // sram + " " //Sectors 0..3 + " 0x4000" //16kB + " " + " " //Sector 4 + " 0x10000" //64kB + " " + " " //Sectors 5..11 + " 0x20000" //128kB + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + static const char* const memory_map_template = "" "chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F4_HD) { + if(sl->chip_id==STM32_CHIPID_F4) { strcpy(map, memory_map_template_F4); + } else if(sl->chip_id==STM32_CHIPID_F4_HD) { + strcpy(map, memory_map_template_F4_HD); } else { snprintf(map, 4096, memory_map_template, sl->flash_size, diff --git a/src/stlink-common.h b/src/stlink-common.h index 9f8b9cd70..17e488dcf 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -209,7 +209,7 @@ extern "C" { .description = "F42x and F43x device", .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, - .sram_size = 0x30000, + .sram_size = 0x40000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800 }, From 5608a3e72e0968a90322ce78f57d0c1bb0af66fd Mon Sep 17 00:00:00 2001 From: texane Date: Tue, 3 Feb 2015 19:07:06 +0100 Subject: [PATCH 0300/1435] add --enable-static support to autoconf --- configure.ac | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index f1357b121..b8eb66d58 100644 --- a/configure.ac +++ b/configure.ac @@ -13,8 +13,10 @@ AC_PROG_CC AC_PROG_INSTALL AC_CANONICAL_HOST AC_CANONICAL_BUILD -AC_PROG_RANLIB AM_PROG_CC_C_O +AC_CONFIG_MACRO_DIR([m4]) + +LT_INIT AC_CHECK_HEADERS(sys/mman.h) AC_CHECK_HEADERS(sys/poll.h) @@ -49,6 +51,11 @@ if test "x$with_gtk" = "xyes"; then fi AC_SUBST([MAYBE_GUI]) +AC_ARG_ENABLE([static], AS_HELP_STRING([--enable-static], [enable binaries static linking])) +if test "x$enable_static" = "xyes"; then + LDFLAGS="$LDFLAGS -all-static" +fi + AC_CONFIG_FILES([Makefile]) AC_OUTPUT From c8240526e23278ca9e78f8ad1b9cbf2f37c3035c Mon Sep 17 00:00:00 2001 From: texane Date: Tue, 3 Feb 2015 21:47:06 +0100 Subject: [PATCH 0301/1435] revert 5608a3e, breaks on ubuntu 14.04 --- configure.ac | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/configure.ac b/configure.ac index b8eb66d58..f1357b121 100644 --- a/configure.ac +++ b/configure.ac @@ -13,10 +13,8 @@ AC_PROG_CC AC_PROG_INSTALL AC_CANONICAL_HOST AC_CANONICAL_BUILD +AC_PROG_RANLIB AM_PROG_CC_C_O -AC_CONFIG_MACRO_DIR([m4]) - -LT_INIT AC_CHECK_HEADERS(sys/mman.h) AC_CHECK_HEADERS(sys/poll.h) @@ -51,11 +49,6 @@ if test "x$with_gtk" = "xyes"; then fi AC_SUBST([MAYBE_GUI]) -AC_ARG_ENABLE([static], AS_HELP_STRING([--enable-static], [enable binaries static linking])) -if test "x$enable_static" = "xyes"; then - LDFLAGS="$LDFLAGS -all-static" -fi - AC_CONFIG_FILES([Makefile]) AC_OUTPUT From 31f0250d89bd4c1690f366e302de6972716e5951 Mon Sep 17 00:00:00 2001 From: giuseppe barba Date: Mon, 9 Feb 2015 21:54:05 +0100 Subject: [PATCH 0302/1435] Added support for flashing STM32F091 Signed-off-by: giuseppe barba --- src/stlink-common.c | 2 +- src/stlink-common.h | 11 ++++++++++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 6e327f028..3256ccd89 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1385,7 +1385,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE)){ loader_code = loader_code_stm32f4; loader_size = sizeof(loader_code_stm32f4); - } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL) { + } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); } else if (sl->chip_id == STM32_CHIPID_L0) { diff --git a/src/stlink-common.h b/src/stlink-common.h index aeeaa85a4..04a108101 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -129,7 +129,7 @@ extern "C" { #define STM32_CHIPID_F3_SMALL 0x439 #define STM32_CHIPID_F0 0x440 - +#define STM32_CHIPID_F09X 0x442 #define STM32_CHIPID_F0_SMALL 0x444 #define STM32_CHIPID_F04 0x445 @@ -369,6 +369,15 @@ extern "C" { .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 }, + { + .chip_id = STM32_CHIPID_F09X, + .description = "F09X device", + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) + .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) + .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 + .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2 + }, { //Use this as an example for mapping future chips: //RM0091 document was used to find these paramaters From 527de547088056f3bf206dc5dacb273704ff5300 Mon Sep 17 00:00:00 2001 From: Jakub Tyszkowski Date: Sat, 7 Mar 2015 18:29:38 +0100 Subject: [PATCH 0303/1435] Fix error being reported twice If 'stlink_v1_open_inner' returns NULL then 'stlink_v1_open' prints to stderr thus there is no need for the former one to print it also. This removes 'Error: could not open stlink device' being printed twice. --- src/stlink-sg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index bfe41574c..960455bab 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -980,7 +980,7 @@ stlink_t* stlink_v1_open_inner(const int verbose) { ugly_init(verbose); stlink_t *sl = stlink_open(verbose); if (sl == NULL) { - fputs("Error: could not open stlink device\n", stderr); + ELOG("Could not open stlink device\n"); return NULL; } From fc961745f5ff121e827702255872354f31f95547 Mon Sep 17 00:00:00 2001 From: Jakub Tyszkowski Date: Sat, 7 Mar 2015 18:42:16 +0100 Subject: [PATCH 0304/1435] Fix getting error message when successfully using stlinkV2 When using stlinkV2 you are constantly getting error messages from 'stlink_v1_open' when all goes well and 'stlink_open_usb' is used instead. This patch fixes this confusing behaviour and makes stlink-sg.c use logging macros consistently by removing last 'stderr' printout. It is not needed as 'stlink_v1_open_inner' is verbose enough. --- src/stlink-sg.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 960455bab..db68e2f4e 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -1017,10 +1017,9 @@ stlink_t* stlink_v1_open_inner(const int verbose) { stlink_t* stlink_v1_open(const int verbose, int reset) { stlink_t *sl = stlink_v1_open_inner(verbose); - if (sl == NULL) { - fputs("Error: could not open stlink device\n", stderr); + if (sl == NULL) return NULL; - } + // by now, it _must_ be fully open and in a useful mode.... stlink_enter_swd_mode(sl); /* Now we are ready to read the parameters */ From c6afdd500ceecf106fe177f2017bfada142f6d3a Mon Sep 17 00:00:00 2001 From: Jakub Tyszkowski Date: Sat, 7 Mar 2015 19:47:03 +0100 Subject: [PATCH 0305/1435] Remove redundant includes from stlink-sg.c Not sure why those were here. Probaly leftovers after refactoring? --- src/stlink-sg.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index db68e2f4e..b16a2edfc 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -79,13 +79,8 @@ #include #include #include -#include #include -#include -#include #include -#include -#include "mmap.h" #include "stlink-common.h" #include "stlink-sg.h" From 9b2f8930538630db8537b8c5601e8c4a9c074657 Mon Sep 17 00:00:00 2001 From: Denis Fokin Date: Sun, 15 Mar 2015 17:49:30 +0200 Subject: [PATCH 0306/1435] Properly close socket on WIN32 to allow accepting further connections --- gdbserver/gdb-server.c | 13 +++++++++++++ mingw/mingw.c | 10 ++++++---- mingw/mingw.h | 1 + 3 files changed, 20 insertions(+), 4 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index daacb85cb..b1cea5cb5 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -733,6 +733,9 @@ int serve(stlink_t *sl, st_state_t *st) { int status = gdb_recv_packet(client, &packet); if(status < 0) { ELOG("cannot recv: %d\n", status); +#ifdef __MINGW32__ + win32_close_socket(sock); +#endif return 1; } @@ -942,6 +945,9 @@ int serve(stlink_t *sl, st_state_t *st) { int status = gdb_check_for_interrupt(client); if(status < 0) { ELOG("cannot check for int: %d\n", status); +#ifdef __MINGW32__ + win32_close_socket(sock); +#endif return 1; } @@ -1256,6 +1262,9 @@ int serve(stlink_t *sl, st_state_t *st) { ELOG("cannot send: %d\n", result); free(reply); free(packet); +#ifdef __MINGW32__ + win32_close_socket(sock); +#endif return 1; } @@ -1265,5 +1274,9 @@ int serve(stlink_t *sl, st_state_t *st) { free(packet); } +#ifdef __MINGW32__ + win32_close_socket(sock); +#endif + return 0; } diff --git a/mingw/mingw.c b/mingw/mingw.c index 266a87c64..3c5d025a3 100644 --- a/mingw/mingw.c +++ b/mingw/mingw.c @@ -163,14 +163,16 @@ win32_shutdown(SOCKET fd, int mode) } return rc; } -int win32_close_socket(SOCKET fd) { - int rc; - rc = closesocket(fd); +int win32_close_socket(SOCKET fd) +{ + int rc = closesocket(fd); + if(rc == SOCKET_ERROR) { + set_socket_errno(WSAGetLastError()); + } return rc; } - ssize_t win32_write_socket(SOCKET fd, void *buf, int n) { int rc = send(fd, buf, n, 0); diff --git a/mingw/mingw.h b/mingw/mingw.h index 28c7a82e0..1fcf93da2 100644 --- a/mingw/mingw.h +++ b/mingw/mingw.h @@ -54,6 +54,7 @@ SOCKET win32_socket(int, int, int); int win32_connect(SOCKET, struct sockaddr*, socklen_t); SOCKET win32_accept(SOCKET, struct sockaddr*, socklen_t *); int win32_shutdown(SOCKET, int); +int win32_close_socket(SOCKET fd); #define strtok_r(x, y, z) win32_strtok_r(x, y, z) #define strsep(x,y) win32_strsep(x,y) From dceade1c279f2efb2607365d67cd841e5e100437 Mon Sep 17 00:00:00 2001 From: texane Date: Fri, 20 Mar 2015 17:52:25 +0100 Subject: [PATCH 0307/1435] merge request: my STM32F042 has 6k of RAM according to table 2 of the datasheet --- src/stlink-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.h b/src/stlink-common.h index 04a108101..3021691c6 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -385,7 +385,7 @@ extern "C" { .description = "F04x device", .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 }, From 39998145313394a93e0837d0903d7343fae9425d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uli=20K=C3=B6hler?= Date: Sat, 21 Mar 2015 20:07:21 +0100 Subject: [PATCH 0308/1435] Added STM32F030F4P6 to working targets --- README | 1 + 1 file changed, 1 insertion(+) diff --git a/README b/README index cedbd2474..5ed9dbf31 100644 --- a/README +++ b/README @@ -170,6 +170,7 @@ No information: STLink v2 (as found on the 32L and F4 Discovery boards) Known Working Targets: +* STM32F030F4P6 (custom board) * STM32F0Discovery (STM32F0 Discovery board) * STM32F100xx (Medium Density VL, as on the 32VL Discovery board) * STM32L1xx (STM32L Discovery board) From 9fc5f77774168f179bdbf79de7a24a82a2835e1e Mon Sep 17 00:00:00 2001 From: lementec Date: Wed, 25 Mar 2015 16:53:14 +0100 Subject: [PATCH 0309/1435] apply patch from rewolff: dont go bezurk if serve returns with error --- gdbserver/gdb-server.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index b1cea5cb5..0ddebb06f 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -209,7 +209,9 @@ int main(int argc, char** argv) { #endif do { - serve(sl, &state); + if (serve(sl, &state)) { + sleep (1); // don't go bezurk if serve returns with error + } /* Continue */ stlink_run(sl); From c72205661244e8b7711d2299175097cc02cfd7c1 Mon Sep 17 00:00:00 2001 From: texane Date: Fri, 3 Apr 2015 14:13:58 +0200 Subject: [PATCH 0310/1435] add HY-STM32 to working board set --- README | 1 + 1 file changed, 1 insertion(+) diff --git a/README b/README index 5ed9dbf31..bb46e6e8a 100644 --- a/README +++ b/README @@ -176,6 +176,7 @@ Known Working Targets: * STM32L1xx (STM32L Discovery board) * STM32F103VC, STM32F107RC, STM32L151RB, STM32F205RE and STM32F405RE on custom boards (https://github.com/UweBonnes/wiki_fuer_alex/layout/usps...) +* STM32F103VET6 (HY-STM32 board) * STM32F303xx (STM32F3 Discovery board) * STM32F407xx (STM32F4 Discovery board) * STM32F429I-DISCO (STM32F4 Discovery board with LCD) From 1b46200b12ff8764a869a7365eb8253622100fed Mon Sep 17 00:00:00 2001 From: texane Date: Sun, 5 Apr 2015 08:02:19 +0200 Subject: [PATCH 0311/1435] add Nucleo-F411RE to work board set --- README | 1 + 1 file changed, 1 insertion(+) diff --git a/README b/README index bb46e6e8a..be9245724 100644 --- a/README +++ b/README @@ -191,5 +191,6 @@ Known Working Targets: * STM32F072RBT6 (STM32 Nucleo-F072RB board) * STM32F103RB (STM32 Nucleo-F103RB board) * STM32F334R8 (STM32 Nucleo-F334R8 board) +* STM32F411RET6 (STM32 Nucleo-F411RE board) Please report any and all known working combinations so I can update this! From e73a5341028e95b5762f4d4db35c2f4b68a69cf3 Mon Sep 17 00:00:00 2001 From: texane Date: Fri, 10 Apr 2015 06:17:28 +0200 Subject: [PATCH 0312/1435] README, GDB load command issue --- README | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/README b/README index be9245724..46ce11c4c 100644 --- a/README +++ b/README @@ -156,6 +156,11 @@ A: Sometimes when you will try to use GDB `next' command to skip a loop, it will use a rather inefficient single-stepping way of doing that. Set up a breakpoint manually in that case and do `continue'. +Q: Load command does not work in GDB. + +A: Some people report XML/EXPAT is not enabled by default when compiling +GDB. Memory map parsing thus fail. Use --enable-expat. + Currently known working combinations of programmer and target ============================================================= From 3b37cbf3c6a64d672271a9ce1257fa338ed493bc Mon Sep 17 00:00:00 2001 From: Kyle Manna Date: Wed, 22 Apr 2015 18:48:27 -0700 Subject: [PATCH 0313/1435] stlink: Add STM32F303 High Density Support * STK32F303RET6 device from STM32 F3 Nucelo board --- src/stlink-common.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/stlink-common.h b/src/stlink-common.h index 3021691c6..ac267e2ba 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -134,6 +134,8 @@ extern "C" { #define STM32_CHIPID_F04 0x445 +#define STM32_CHIPID_F303_HIGH 0x446 + #define STM32_CHIPID_F0_CAN 0x448 /* @@ -432,6 +434,17 @@ extern "C" { .bootrom_base = 0x1fffd800, .bootrom_size = 0x2000 }, + { + // This is STK32F303RET6 device from STM32 F3 Nucelo board. + // Support based on DM00043574.pdf (RM0316) document rev 5. + .chip_id = STM32_CHIPID_F303_HIGH, + .description = "F303 high density device", + .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register + .flash_pagesize = 0x800, // 4.2.1 Flash memory organization + .sram_size = 0x10000, // 3.3 Embedded SRAM + .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory + .bootrom_size = 0x2000 + }, }; From 7890d4ccfbca5d0debef9e35bdeca5c22d8100d3 Mon Sep 17 00:00:00 2001 From: Kyle Manna Date: Wed, 22 Apr 2015 18:55:30 -0700 Subject: [PATCH 0314/1435] README: Add STM32 Nucleo-F303RE board * Add another to the list. Preliminary testing works. --- README | 1 + 1 file changed, 1 insertion(+) diff --git a/README b/README index 46ce11c4c..922765e1d 100644 --- a/README +++ b/README @@ -195,6 +195,7 @@ Known Working Targets: * STM32F030R8T6 (STM32 Nucleo-F030R8 board) * STM32F072RBT6 (STM32 Nucleo-F072RB board) * STM32F103RB (STM32 Nucleo-F103RB board) +* STM32F303RET6 (STM32 Nucleo-F303RE board) * STM32F334R8 (STM32 Nucleo-F334R8 board) * STM32F411RET6 (STM32 Nucleo-F411RE board) From 0c900d76a97c86bfd9b41fd0f1f5c8d3566b877c Mon Sep 17 00:00:00 2001 From: Kyle Manna Date: Thu, 23 Apr 2015 17:03:28 -0700 Subject: [PATCH 0315/1435] stlink: Add flash support for STM32F303 High Density * Add the necessary teststo use the existing flash code. Haven't verified via datasheet if it's correct. * Works for me on the STM32F303RE Nucleo. --- src/stlink-common.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 3256ccd89..4599e6aa8 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1145,6 +1145,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 + || sl->chip_id == STM32_CHIPID_F303_HIGH || sl->chip_id == STM32_CHIPID_F37x || sl->chip_id == STM32_CHIPID_F334) { /* wait for ongoing op to finish */ @@ -1377,8 +1378,11 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); - } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || - sl->chip_id == STM32_CHIPID_F37x || sl->chip_id == STM32_CHIPID_F334) { + } else if (sl->core_id == STM32VL_CORE_ID + || sl->chip_id == STM32_CHIPID_F3 + || sl->chip_id == STM32_CHIPID_F303_HIGH + || sl->chip_id == STM32_CHIPID_F37x + || sl->chip_id == STM32_CHIPID_F334) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || @@ -1682,6 +1686,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F303_HIGH || sl->chip_id == STM32_CHIPID_F334 || sl->chip_id == STM32_CHIPID_F37x) { ILOG("Starting Flash write for VL/F0/F3 core id\n"); @@ -1790,6 +1795,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F303_HIGH || sl->chip_id == STM32_CHIPID_F37x || sl->chip_id == STM32_CHIPID_F334) { @@ -1853,6 +1859,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F303_HIGH || sl->chip_id == STM32_CHIPID_F37x || sl->chip_id == STM32_CHIPID_F334) { From 8c26581f5937a9f6603d3fbcf056f8aedeed3101 Mon Sep 17 00:00:00 2001 From: Robin Kreis Date: Tue, 28 Apr 2015 22:37:01 +0200 Subject: [PATCH 0316/1435] fix typo in stm32l0x flash loader The typo caused errors when flashing an stm32l052. This commit makes stlink-common.c match flashloaders/stm32l0x.s. --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 4599e6aa8..962cddbf5 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1339,7 +1339,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x04, 0xe0, 0x0c, 0x68, - 0x04, 0x66, + 0x04, 0x60, 0x01, 0x33, 0x04, 0x31, 0x04, 0x30, From eaf4520fc0da817b3fc2f83bcd42460cb7804519 Mon Sep 17 00:00:00 2001 From: Robin Kreis Date: Wed, 29 Apr 2015 09:07:45 +0200 Subject: [PATCH 0317/1435] add some known working targets --- README | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README b/README index 922765e1d..7aa3b8b69 100644 --- a/README +++ b/README @@ -182,10 +182,12 @@ Known Working Targets: * STM32F103VC, STM32F107RC, STM32L151RB, STM32F205RE and STM32F405RE on custom boards (https://github.com/UweBonnes/wiki_fuer_alex/layout/usps...) * STM32F103VET6 (HY-STM32 board) +* STM32F105RCT6 (DecaWave EVB1000 board) * STM32F303xx (STM32F3 Discovery board) * STM32F407xx (STM32F4 Discovery board) * STM32F429I-DISCO (STM32F4 Discovery board with LCD) * STM32F439VIT6 (discovery board reseated CPU) +* STM32L052K8T6 (custom board) * STM32L151CB (custom board) * STM32L152RB (STM32L-Discovery board, custom board) From 0c11337f0211766b1ac31c2f4adb49aa2457aab0 Mon Sep 17 00:00:00 2001 From: Craig Lilley Date: Mon, 4 May 2015 23:16:31 +0100 Subject: [PATCH 0318/1435] Updated the memory map for stm32f42xxx and stm32f43xxx devices. * These devices have up to 256K of sram. * External memory accessed via the FMC controller is now accessible in GDB. --- gdbserver/gdb-server.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 0ddebb06f..5878222d8 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -325,7 +325,11 @@ static const char* const memory_map_template_F4_HD = "" " " // code = sram, bootrom or flash; flash is bigger " " // ccm ram - " " // sram + " " // sram + " " // fmc bank 1 (nor/psram/sram) + " " // fmc bank 2 & 3 (nand flash) + " " // fmc bank 4 (pc card) + " " // fmc sdram bank 1 & 2 " " //Sectors 0..3 " 0x4000" //16kB " " From af4a00a193609cf88b7d144b840d022484351568 Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Mon, 18 May 2015 16:55:32 +0200 Subject: [PATCH 0319/1435] Fix F2 memory map This enables GCC to only erase needed pages. --- gdbserver/gdb-server.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 5878222d8..393474dd3 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -345,6 +345,28 @@ static const char* const memory_map_template_F4_HD = " " // option byte area ""; +static const char* const memory_map_template_F2 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // sram + " " //Sectors 0..3 + " 0x4000" //16kB + " " + " " //Sector 4 + " 0x10000" //64kB + " " + " " //Sectors 5.. + " 0x20000" //128kB + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + static const char* const memory_map_template = "" "chip_id==STM32_CHIPID_F4_HD) { strcpy(map, memory_map_template_F4_HD); + } else if(sl->chip_id==STM32_CHIPID_F2) { + snprintf(map, 4096, memory_map_template_F2, + sl->flash_size, + sl->sram_size, + sl->flash_size - 0x20000, + sl->sys_base, sl->sys_size); } else { snprintf(map, 4096, memory_map_template, sl->flash_size, From ee62707b4a6ed146dad59123e0ab7d1522dbb558 Mon Sep 17 00:00:00 2001 From: Nicolas Schodet Date: Tue, 19 May 2015 16:30:51 +0200 Subject: [PATCH 0320/1435] Add STM32L1xx Cat.2 devices support --- src/stlink-common.c | 47 +++++++++++++++++++++++++-------------------- src/stlink-common.h | 10 ++++++++++ 2 files changed, 36 insertions(+), 21 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 962cddbf5..cbb2f255e 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -463,6 +463,8 @@ int stlink_load_device_params(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) && ( flash_size == 0 )) { sl->flash_size = 128 * 1024; + } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { + sl->flash_size = (flash_size & 0xff) * 1024; } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_HIGH) { // 0 is 384k and 1 is 256k if ( flash_size == 0 ) { @@ -934,8 +936,9 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) int error = -1; size_t off; int num_empty = 0; - unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; + unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -1074,9 +1077,9 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif - } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE - || sl->chip_id == STM32_CHIPID_L0) { + } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { uint32_t val; uint32_t flash_regs_base; @@ -1179,9 +1182,9 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE - || sl->chip_id == STM32_CHIPID_L0) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { /* erase each page */ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1374,8 +1377,9 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */ + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID @@ -1607,9 +1611,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } //STM32F4END - else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE - || sl->chip_id == STM32_CHIPID_L0) { + else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { /* use fast word write. todo: half page. */ uint32_t val; uint32_t flash_regs_base; @@ -1738,8 +1742,9 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ int err; unsigned int num_empty = 0, index; - unsigned char erased_pattern =(sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE )?0:0xff; + unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { ELOG("map_file() == -1\n"); @@ -1779,9 +1784,9 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE - || sl->chip_id == STM32_CHIPID_L0) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1843,9 +1848,9 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } /* check written byte count */ - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS - || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE - || sl->chip_id == STM32_CHIPID_L0) { + if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 + || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH + || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; diff --git a/src/stlink-common.h b/src/stlink-common.h index ac267e2ba..a25ca4384 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -117,6 +117,7 @@ extern "C" { #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427 #define STM32_CHIPID_F1_VL_HIGH 0x428 +#define STM32_CHIPID_L1_CAT2 0x429 #define STM32_CHIPID_F1_XL 0x430 @@ -264,6 +265,15 @@ extern "C" { .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000 }, + { + .chip_id = STM32_CHIPID_L1_CAT2, + .description = "L1 Cat.2 device", + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x8000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, { .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS, .description = "L1 Medium-Plus-density device", From 71535104e47f2a96ce6a87a6da0fc4519bc64d15 Mon Sep 17 00:00:00 2001 From: Andy Isaacson Date: Tue, 9 Jun 2015 11:15:28 -0700 Subject: [PATCH 0321/1435] STM32F4 8-bit support for 1.8v operation Per ST doc DM00035129.pdf "DocID022063 Rev 5", the STM32F415xx data sheet, table 40 on page 110 of the PDF, 32-bit program operation is only possible above 2.7 Volts. In order to support programming on devices running at lower voltages, this commit adds an 8-bit programming mode and the necessary tests to enable it when the reported voltage is below 2.7 Volts. --- flashloaders/stm32f4lv.s | 33 +++++++++++++++++++++++++++ src/stlink-common.c | 49 +++++++++++++++++++++++++++++++++++----- 2 files changed, 76 insertions(+), 6 deletions(-) create mode 100644 flashloaders/stm32f4lv.s diff --git a/flashloaders/stm32f4lv.s b/flashloaders/stm32f4lv.s new file mode 100644 index 000000000..f60ee8797 --- /dev/null +++ b/flashloaders/stm32f4lv.s @@ -0,0 +1,33 @@ +.global start +.syntax unified + +@ r0 = source +@ r1 = target +@ r2 = wordcount +@ r3 = flash_base +@ r4 = temp + +start: + lsls r2, r2, #2 + ldr r3, flash_base +next: + cbz r2, done + ldrb r4, [r0] + strb r4, [r1] + +wait: + ldrh r4, [r3, #0x0e] + tst.w r4, #1 + bne wait + + add r0, #1 + add r1, #1 + sub r2, #1 + b next +done: + bkpt + +.align 2 + +flash_base: + .word 0x40023c00 diff --git a/src/stlink-common.c b/src/stlink-common.c index cbb2f255e..972c9f31c 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -65,6 +65,7 @@ //STM32L0x flash register base and offsets //same as 32L1 above +// RM0090 - DM00031020.pdf #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) #define FLASH_ACR_OFF ((uint32_t) 0x00) #define FLASH_PECR_OFF ((uint32_t) 0x04) @@ -1374,6 +1375,29 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x00, 0x3c, 0x02, 0x40, }; + static const uint8_t loader_code_stm32f4_lv[] = { + // flashloaders/stm32f4lv.s + 0x92, 0x00, + + 0x08, 0x4b, + 0x62, 0xb1, + 0x04, 0x78, + 0x0c, 0x70, + + 0xdc, 0x89, + 0x14, 0xf0, 0x01, 0x0f, + 0xfb, 0xd1, + 0x00, 0xf1, 0x01, 0x00, + 0x01, 0xf1, 0x01, 0x01, + 0xa2, 0xf1, 0x01, 0x02, + 0xf1, 0xe7, + + 0x00, 0xbe, + 0x00, 0xbf, + + 0x00, 0x3c, 0x02, 0x40, + }; + const uint8_t* loader_code; size_t loader_size; @@ -1391,15 +1415,21 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE)){ - loader_code = loader_code_stm32f4; - loader_size = sizeof(loader_code_stm32f4); + int voltage = stlink_target_voltage(sl); + if (voltage > 2700) { + loader_code = loader_code_stm32f4; + loader_size = sizeof(loader_code_stm32f4); + } else { + loader_code = loader_code_stm32f4_lv; + loader_size = sizeof(loader_code_stm32f4_lv); + } } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); } else if (sl->chip_id == STM32_CHIPID_L0) { - loader_code = loader_code_stm32l0; - loader_size = sizeof(loader_code_stm32l0); - } else { + loader_code = loader_code_stm32l0; + loader_size = sizeof(loader_code_stm32l0); + } else { ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); return -1; } @@ -1588,7 +1618,14 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t /* TODO: Check that Voltage range is 2.7 - 3.6 V */ /* set parallelisim to 32 bit*/ - write_flash_cr_psiz(sl, 2); + int voltage = stlink_target_voltage(sl); + if (voltage > 2700) { + printf("enabling 32-bit flash writes\n"); + write_flash_cr_psiz(sl, 2); + } else { + printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage); + write_flash_cr_psiz(sl, 0); + } /* set programming mode */ set_flash_cr_pg(sl); From 972ed48924fc1f118939b013e0b15f0faed1f26a Mon Sep 17 00:00:00 2001 From: Pavel Kirienko Date: Fri, 17 Jul 2015 11:55:28 +0300 Subject: [PATCH 0322/1435] Basic support for F446 --- src/stlink-common.c | 51 ++++++++++++++++++++++++++++++--------------- src/stlink-common.h | 11 ++++++++++ 2 files changed, 45 insertions(+), 17 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 972c9f31c..343795aeb 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -153,7 +153,8 @@ static inline uint32_t read_flash_obr(stlink_t *sl) { static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t res; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) res = stlink_read_debug32(sl, FLASH_F4_CR); else res = stlink_read_debug32(sl, FLASH_CR); @@ -166,7 +167,8 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) ) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); else return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); @@ -179,7 +181,8 @@ static void unlock_flash(stlink_t *sl) { the FPEC block until next reset. */ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) { stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); } else { @@ -205,7 +208,8 @@ static int unlock_flash_if(stlink_t *sl) { static void lock_flash(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) { const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); stlink_write_debug32(sl, FLASH_F4_CR, n); } else { @@ -218,7 +222,8 @@ static void lock_flash(stlink_t *sl) { static void set_flash_cr_pg(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_CR_PG); stlink_write_debug32(sl, FLASH_F4_CR, x); @@ -231,7 +236,8 @@ static void set_flash_cr_pg(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) stlink_write_debug32(sl, FLASH_F4_CR, n); else stlink_write_debug32(sl, FLASH_CR, n); @@ -249,7 +255,8 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { static void set_flash_cr_mer(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); else @@ -259,7 +266,8 @@ static void set_flash_cr_mer(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); else @@ -269,7 +277,8 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { static void set_flash_cr_strt(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_F4_CR_STRT); stlink_write_debug32(sl, FLASH_F4_CR, x); @@ -286,7 +295,8 @@ static inline uint32_t read_flash_acr(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) res = stlink_read_debug32(sl, FLASH_F4_SR); else res = stlink_read_debug32(sl, FLASH_SR); @@ -296,7 +306,8 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { static inline unsigned int is_flash_busy(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); else return read_flash_sr(sl) & (1 << FLASH_SR_BSY); @@ -1027,7 +1038,8 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector>= 12) { sector -= 12; @@ -1048,7 +1060,8 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE)) { + (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1414,7 +1427,8 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE)){ + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)){ int voltage = stlink_target_voltage(sl); if (voltage > 2700) { loader_code = loader_code_stm32f4; @@ -1603,7 +1617,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || - (sl->chip_id == STM32_CHIPID_F411RE)) { + (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) { /* todo: check write operation */ ILOG("Starting Flash write for F2/F4\n"); @@ -1852,7 +1867,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE)) { + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -1912,7 +1928,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE)) { + sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || + (sl->chip_id == STM32_CHIPID_F446)) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { diff --git a/src/stlink-common.h b/src/stlink-common.h index a25ca4384..c3ac48d03 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -110,6 +110,7 @@ extern "C" { #define STM32_CHIPID_F4_HD 0x419 #define STM32_CHIPID_F1_VL_MEDIUM_LOW 0x420 +#define STM32_CHIPID_F446 0x421 #define STM32_CHIPID_F3 0x422 #define STM32_CHIPID_F4_LP 0x423 @@ -319,6 +320,16 @@ extern "C" { .bootrom_base = 0x1ffff000, .bootrom_size = 0x800 }, + { + // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. + .chip_id = STM32_CHIPID_F446, + .description = "F446 device", + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, { // This is STK32F303VCT6 device from STM32 F3 Discovery board. // Support based on DM00043574.pdf (RM0316) document. From 98a41fa9c08605ac90200b9583f171eea0e08dd2 Mon Sep 17 00:00:00 2001 From: Pavel Kirienko Date: Fri, 17 Jul 2015 12:34:37 +0300 Subject: [PATCH 0323/1435] GDN server: F446 support --- gdbserver/gdb-server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 393474dd3..a7f3c6cba 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -388,7 +388,7 @@ char* make_memory_map(stlink_t *sl) { char* map = malloc(4096); map[0] = '\0'; - if(sl->chip_id==STM32_CHIPID_F4) { + if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F446) { strcpy(map, memory_map_template_F4); } else if(sl->chip_id==STM32_CHIPID_F4_HD) { strcpy(map, memory_map_template_F4_HD); From 67fd44b8370cca4994752df8abf0e2c45fdf995d Mon Sep 17 00:00:00 2001 From: Dave Vandervies Date: Sat, 18 Jul 2015 16:25:11 -0400 Subject: [PATCH 0324/1435] Add STM32L4 to CHIPID #defines and devices[] --- src/stlink-common.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/src/stlink-common.h b/src/stlink-common.h index c3ac48d03..3fceeef62 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -103,7 +103,7 @@ extern "C" { #define STM32_CHIPID_F1_LOW 0x412 #define STM32_CHIPID_F4 0x413 #define STM32_CHIPID_F1_HIGH 0x414 - +#define STM32_CHIPID_L4 0x415 /* Seen on L4x6 (RM0351) */ #define STM32_CHIPID_L1_MEDIUM 0x416 #define STM32_CHIPID_L0 0x417 #define STM32_CHIPID_F1_CONN 0x418 @@ -466,6 +466,20 @@ extern "C" { .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory .bootrom_size = 0x2000 }, + { + // STM32L4x6 + // From RM0351. + .chip_id = STM32_CHIPID_L4, + .description = "L4 device", + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81) + // SRAM1 is "up to" 96k in the standard Cortex-M memory map; + // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000 // 28k (per bank), same source as base + }, }; From ab464492f7774ce5c005c026b68479c49c16fa8d Mon Sep 17 00:00:00 2001 From: Dave Vandervies Date: Sun, 19 Jul 2015 22:58:43 -0400 Subject: [PATCH 0325/1435] Add supprt for STM32L4 flash driver No loader yet, but we can erase! --- src/stlink-common.c | 114 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 103 insertions(+), 11 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 343795aeb..07b8d6765 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -63,6 +63,28 @@ #define FLASH_L1_FPRG 10 #define FLASH_L1_PROG 3 +//32L4 register base is at FLASH_REGS_ADDR (0x40022000) +#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) +#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) +#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) +#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) + +#define STM32L4_FLASH_SR_BSY 16 +#define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */ + +#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_PG 0 /* Program */ +#define STM32L4_FLASH_CR_PER 1 /* Page erase */ +#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ +#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ +#define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ +#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +// Page is fully specified by BKER and PNB +#define STM32L4_FLASH_CR_PAGEMASK (0x1fflu << STM32L4_FLASH_CR_PNB) + +#define STM32L4_FLASH_OPTR_DUALBANK 21 + //STM32L0x flash register base and offsets //same as 32L1 above // RM0090 - DM00031020.pdf @@ -156,6 +178,8 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || (sl->chip_id == STM32_CHIPID_F446)) res = stlink_read_debug32(sl, FLASH_F4_CR); + else if (sl->chip_id == STM32_CHIPID_L4) + res = stlink_read_debug32(sl, STM32L4_FLASH_CR); else res = stlink_read_debug32(sl, FLASH_CR); #if DEBUG_FLASH @@ -166,12 +190,16 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ + uint32_t cr = read_flash_cr(sl); + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || (sl->chip_id == STM32_CHIPID_F446)) - return read_flash_cr(sl) & (1 << FLASH_F4_CR_LOCK); + return cr & (1 << FLASH_F4_CR_LOCK); + else if (sl->chip_id == STM32_CHIPID_L4) + return cr & (1lu << STM32L4_FLASH_CR_LOCK); else - return read_flash_cr(sl) & (1 << FLASH_CR_LOCK); + return cr & (1 << FLASH_CR_LOCK); } static void unlock_flash(stlink_t *sl) { @@ -185,6 +213,9 @@ static void unlock_flash(stlink_t *sl) { (sl->chip_id == STM32_CHIPID_F446)) { stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); + } else if (sl->chip_id == STM32_CHIPID_L4) { + stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY1); + stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY2); } else { stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2); @@ -212,6 +243,9 @@ static void lock_flash(stlink_t *sl) { (sl->chip_id == STM32_CHIPID_F446)) { const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); stlink_write_debug32(sl, FLASH_F4_CR, n); + } else if (sl->chip_id == STM32_CHIPID_L4) { + const uint32_t n = read_flash_cr(sl) | (1lu << STM32L4_FLASH_CR_LOCK); + stlink_write_debug32(sl, STM32L4_FLASH_CR, n); } else { /* write to 1 only. reset by hw at unlock sequence */ const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK); @@ -227,6 +261,10 @@ static void set_flash_cr_pg(stlink_t *sl) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_CR_PG); stlink_write_debug32(sl, FLASH_F4_CR, x); + } else if (sl->chip_id == STM32_CHIPID_L4) { + uint32_t x = read_flash_cr(sl); + x |= (1 << STM32L4_FLASH_CR_PG); + stlink_write_debug32(sl, STM32L4_FLASH_CR, x); } else { const uint32_t n = 1 << FLASH_CR_PG; stlink_write_debug32(sl, FLASH_CR, n); @@ -244,8 +282,14 @@ static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { } static void set_flash_cr_per(stlink_t *sl) { - const uint32_t n = 1 << FLASH_CR_PER; - stlink_write_debug32(sl, FLASH_CR, n); + if (sl->chip_id == STM32_CHIPID_L4) { + uint32_t n = read_flash_cr(sl); + n |= (1lu << STM32L4_FLASH_CR_PER); + stlink_write_debug32(sl, STM32L4_FLASH_CR, n); + } else { + const uint32_t n = 1 << FLASH_CR_PER; + stlink_write_debug32(sl, FLASH_CR, n); + } } static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { @@ -259,6 +303,11 @@ static void set_flash_cr_mer(stlink_t *sl) { (sl->chip_id == STM32_CHIPID_F446)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); + else if (sl->chip_id == STM32_CHIPID_L4) + stlink_write_debug32(sl, STM32L4_FLASH_CR, + stlink_read_debug32(sl, STM32L4_FLASH_CR) | + (1lu << STM32L4_FLASH_CR_MER1) | + (1lu << STM32L4_FLASH_CR_MER2)); else stlink_write_debug32(sl, FLASH_CR, stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER)); @@ -282,6 +331,10 @@ static void set_flash_cr_strt(stlink_t *sl) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_F4_CR_STRT); stlink_write_debug32(sl, FLASH_F4_CR, x); + } else if (sl->chip_id == STM32_CHIPID_L4) { + uint32_t x = read_flash_cr(sl); + x |= (1lu << STM32L4_FLASH_CR_STRT); + stlink_write_debug32(sl, STM32L4_FLASH_CR, x); } else { stlink_write_debug32(sl, FLASH_CR, stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_STRT) ); @@ -298,6 +351,8 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || (sl->chip_id == STM32_CHIPID_F446)) res = stlink_read_debug32(sl, FLASH_F4_SR); + else if (sl->chip_id == STM32_CHIPID_L4) + res = stlink_read_debug32(sl, STM32L4_FLASH_SR); else res = stlink_read_debug32(sl, FLASH_SR); //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf); @@ -309,6 +364,8 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || (sl->chip_id == STM32_CHIPID_F446)) return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); + else if (sl->chip_id == STM32_CHIPID_L4) + return read_flash_sr(sl) & (1 << STM32L4_FLASH_SR_BSY); else return read_flash_sr(sl) & (1 << FLASH_SR_BSY); } @@ -375,6 +432,17 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { stlink_write_debug32(sl, FLASH_F4_CR, x); } +static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { + uint32_t x = read_flash_cr(sl); + x &=~ STM32L4_FLASH_CR_PAGEMASK; + x |= (n << STM32L4_FLASH_CR_PNB); + x |= (1lu << STM32L4_FLASH_CR_PER); +#if DEBUG_FLASH + fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, STM32L4_FLASH_CR, x); +} + // Delegates to the backends... void stlink_close(stlink_t *sl) { @@ -1036,6 +1104,23 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ } +// Returns BKER:PNB for the given page address +uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { + uint32_t bker = 0; + uint32_t flashopt = stlink_read_debug32(sl, STM32L4_FLASH_OPTR); + flashaddr -= STM32_FLASH_BASE; + if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) { + uint32_t banksize = sl->flash_size / 2; + if (flashaddr > banksize) { + flashaddr -= banksize; + bker = 0x100; + } + } + // For 1MB chips without the dual-bank option set, the page address will + // overflow into the BKER bit, which gives us the correct bank:page value. + return bker | flashaddr/sl->flash_pgsz; +} + uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || @@ -1061,7 +1146,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_L4)) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1069,15 +1154,22 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) unlock_flash_if(sl); /* select the page to erase */ - // calculate the actual page from the address - uint32_t sector=calculate_F4_sectornum(flashaddr); + if (sl->chip_id == STM32_CHIPID_L4) { + // calculate the actual bank+page from the address + uint32_t page = calculate_L4_page(sl, flashaddr); - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); + write_flash_cr_bker_pnb(sl, page); + } else { + // calculate the actual page from the address + uint32_t sector=calculate_F4_sectornum(flashaddr); + + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); - //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices... - if (sector >= 12) sector += 4; + //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices... + if (sector >= 12) sector += 4; - write_flash_cr_snb(sl, sector); + write_flash_cr_snb(sl, sector); + } /* start erase operation */ set_flash_cr_strt(sl); From 0419b8bec68b08acee490b4f0fcd35f9c7f4a496 Mon Sep 17 00:00:00 2001 From: Dave Vandervies Date: Mon, 20 Jul 2015 15:15:25 -0400 Subject: [PATCH 0326/1435] Flash loader for STM32L4 --- flashloaders/stm32l4.s | 39 +++++++++++++++++++++++++++++ src/stlink-common.c | 57 ++++++++++++++++++++++++++++++++++-------- 2 files changed, 85 insertions(+), 11 deletions(-) create mode 100644 flashloaders/stm32l4.s diff --git a/flashloaders/stm32l4.s b/flashloaders/stm32l4.s new file mode 100644 index 000000000..4b908633d --- /dev/null +++ b/flashloaders/stm32l4.s @@ -0,0 +1,39 @@ +.global start +.syntax unified + +@ Adapted from stm32f4.s +@ STM32L4's flash controller expects double-word writes, has the flash +@ controller mapped in a different location with the registers we care about +@ moved down from the base address, and has BSY moved to bit 16 of SR. +@ r0 = source +@ r1 = target +@ r2 = wordcount +@ r3 = flash_base +@ r4 = temp +@ r5 = temp + +start: + ldr r3, flash_base +next: + cbz r2, done + ldr r4, [r0] /* copy doubleword from source to target */ + ldr r5, [r0, #4] + str r4, [r1] + str r5, [r1, #4] + +wait: + ldrh r4, [r3, #0x12] /* high half of status register */ + tst r4, #1 /* BSY = bit 16 */ + bne wait + + add r0, #8 + add r1, #8 + sub r2, #2 + b next +done: + bkpt + +.align 2 + +flash_base: + .word 0x40022000 diff --git a/src/stlink-common.c b/src/stlink-common.c index 07b8d6765..37beb905f 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1503,6 +1503,25 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x00, 0x3c, 0x02, 0x40, }; + static const uint8_t loader_code_stm32l4[] = { + // flashloaders/stm32l4.s + 0x08, 0x4b, // start: ldr r3, [pc, #32] ; + 0x72, 0xb1, // next: cbz r2, + 0x04, 0x68, // ldr r4, [r0, #0] + 0x45, 0x68, // ldr r5, [r0, #4] + 0x0c, 0x60, // str r4, [r1, #0] + 0x4d, 0x60, // str r5, [r1, #4] + 0x5c, 0x8a, // wait: ldrh r4, [r3, #18] + 0x14, 0xf0, 0x01, 0x0f, // tst.w r4, #1 + 0xfb, 0xd1, // bne.n + 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8 + 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8 + 0xa2, 0xf1, 0x02, 0x02, // add.w r2, r2, #2 + 0xef, 0xe7, // b.n + 0x00, 0xbe, // done: bkpt 0x0000 + 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000 + }; + const uint8_t* loader_code; size_t loader_size; @@ -1535,6 +1554,9 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { } else if (sl->chip_id == STM32_CHIPID_L0) { loader_code = loader_code_stm32l0; loader_size = sizeof(loader_code_stm32l0); + } else if (sl->chip_id == STM32_CHIPID_L4) { + loader_code = loader_code_stm32l4; + loader_size = sizeof(loader_code_stm32l4); } else { ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); return -1; @@ -1710,10 +1732,11 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) { + (sl->chip_id == STM32_CHIPID_F446) || + (sl->chip_id == STM32_CHIPID_L4)) { /* todo: check write operation */ - ILOG("Starting Flash write for F2/F4\n"); + ILOG("Starting Flash write for F2/F4/L4\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { ELOG("init_flash_loader() == -1\n"); @@ -1724,14 +1747,23 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t unlock_flash_if(sl); /* TODO: Check that Voltage range is 2.7 - 3.6 V */ - /* set parallelisim to 32 bit*/ - int voltage = stlink_target_voltage(sl); - if (voltage > 2700) { - printf("enabling 32-bit flash writes\n"); - write_flash_cr_psiz(sl, 2); + if (sl->chip_id != STM32_CHIPID_L4) { + /* set parallelisim to 32 bit*/ + int voltage = stlink_target_voltage(sl); + if (voltage > 2700) { + printf("enabling 32-bit flash writes\n"); + write_flash_cr_psiz(sl, 2); + } else { + printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage); + write_flash_cr_psiz(sl, 0); + } } else { - printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage); - write_flash_cr_psiz(sl, 0); + /* L4 does not have a byte-write mode */ + int voltage = stlink_target_voltage(sl); + if (voltage <= 2700) { + printf("Target voltage (%d mV) too low for flash writes!\n", voltage); + return -1; + } } /* set programming mode */ @@ -1960,10 +1992,13 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_L4)) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; + if (sl->chip_id == STM32_CHIPID_L4) { + if (count % 2) ++count; + } /* setup core */ stlink_write_reg(sl, fl->buf_addr, 0); /* source */ @@ -2021,7 +2056,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_L4)) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { From bc3d61adc399f7f3c6f67e387187825769ea2a75 Mon Sep 17 00:00:00 2001 From: Dave Vandervies Date: Mon, 20 Jul 2015 15:25:48 -0400 Subject: [PATCH 0327/1435] Clear STM32L4 PER,MER,PG bits The controller doesn't clear them automatically when the operation finishes, so to avoid getting errors we need to clear them manually before we request another operation. --- src/stlink-common.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 37beb905f..8c9d4090a 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -80,6 +80,10 @@ #define STM32L4_FLASH_CR_STRT 16 /* Start command */ #define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ #define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +// Bits requesting flash operations (useful when we want to clear them) +#define STM32L4_FLASH_CR_OPBITS \ + ((1lu<chip_id == STM32_CHIPID_L4) { uint32_t x = read_flash_cr(sl); + x &=~ STM32L4_FLASH_CR_OPBITS; x |= (1 << STM32L4_FLASH_CR_PG); stlink_write_debug32(sl, STM32L4_FLASH_CR, x); } else { @@ -282,14 +287,8 @@ static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { } static void set_flash_cr_per(stlink_t *sl) { - if (sl->chip_id == STM32_CHIPID_L4) { - uint32_t n = read_flash_cr(sl); - n |= (1lu << STM32L4_FLASH_CR_PER); - stlink_write_debug32(sl, STM32L4_FLASH_CR, n); - } else { - const uint32_t n = 1 << FLASH_CR_PER; - stlink_write_debug32(sl, FLASH_CR, n); - } + const uint32_t n = 1 << FLASH_CR_PER; + stlink_write_debug32(sl, FLASH_CR, n); } static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { @@ -303,12 +302,12 @@ static void set_flash_cr_mer(stlink_t *sl) { (sl->chip_id == STM32_CHIPID_F446)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); - else if (sl->chip_id == STM32_CHIPID_L4) - stlink_write_debug32(sl, STM32L4_FLASH_CR, - stlink_read_debug32(sl, STM32L4_FLASH_CR) | - (1lu << STM32L4_FLASH_CR_MER1) | - (1lu << STM32L4_FLASH_CR_MER2)); - else + else if (sl->chip_id == STM32_CHIPID_L4) { + uint32_t x = stlink_read_debug32(sl, STM32L4_FLASH_CR); + x &=~ STM32L4_FLASH_CR_OPBITS; + x |= (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER2); + stlink_write_debug32(sl, STM32L4_FLASH_CR, x); + } else stlink_write_debug32(sl, FLASH_CR, stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER)); } @@ -434,6 +433,7 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { uint32_t x = read_flash_cr(sl); + x &=~ STM32L4_FLASH_CR_OPBITS; x &=~ STM32L4_FLASH_CR_PAGEMASK; x |= (n << STM32L4_FLASH_CR_PNB); x |= (1lu << STM32L4_FLASH_CR_PER); From 6d3f105d2a38e8805cf2f3502e88e88713907bac Mon Sep 17 00:00:00 2001 From: texane Date: Sat, 8 Aug 2015 16:03:49 +0200 Subject: [PATCH 0328/1435] FIX: "unaligned addr or size" in attempt of write the program in the RAM (#323) --- src/stlink-common.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 8c9d4090a..7bf6f7263 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -953,6 +953,7 @@ int stlink_fwrite_sram int error = -1; size_t off; + size_t len; mapped_file_t mf = MAPPED_FILE_INITIALIZER; @@ -971,16 +972,23 @@ int stlink_fwrite_sram } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { fprintf(stderr, "addr too high\n"); goto on_error; - } else if ((addr & 3) || (mf.len & 3)) { + } else if (addr & 3) { /* todo */ - fprintf(stderr, "unaligned addr or size\n"); + fprintf(stderr, "unaligned addr\n"); goto on_error; } + + len = mf.len; + + if(len & 3) { + len -= len & 3; + } + /* do the copy by 1k blocks */ - for (off = 0; off < mf.len; off += 1024) { + for (off = 0; off < len; off += 1024) { size_t size = 1024; - if ((off + size) > mf.len) - size = mf.len - off; + if ((off + size) > len) + size = len - off; memcpy(sl->q_buf, mf.base + off, size); @@ -991,6 +999,11 @@ int stlink_fwrite_sram stlink_write_mem32(sl, addr + off, size); } + if(mf.len > len) { + memcpy(sl->q_buf, mf.base + len, mf.len - len); + stlink_write_mem8(sl, addr + len, mf.len - len); + } + /* check the file ha been written */ if (check_file(sl, &mf, addr) == -1) { fprintf(stderr, "check_file() == -1\n"); From f83ed07f4512a05dcf4481c54aeae23ea522d2f1 Mon Sep 17 00:00:00 2001 From: Max Chen Date: Thu, 13 Aug 2015 14:24:09 +0800 Subject: [PATCH 0329/1435] fix can not flash STM32_F3_SMALL --- src/stlink-common.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index 7bf6f7263..3964d40e0 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1267,6 +1267,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 + || sl->chip_id == STM32_CHIPID_F3_SMALL || sl->chip_id == STM32_CHIPID_F303_HIGH || sl->chip_id == STM32_CHIPID_F37x || sl->chip_id == STM32_CHIPID_F334) { @@ -1545,6 +1546,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STM32_CHIPID_F3 + || sl->chip_id == STM32_CHIPID_F3_SMALL || sl->chip_id == STM32_CHIPID_F303_HIGH || sl->chip_id == STM32_CHIPID_F37x || sl->chip_id == STM32_CHIPID_F334) { @@ -1879,6 +1881,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F3_SMALL || sl->chip_id == STM32_CHIPID_F303_HIGH || sl->chip_id == STM32_CHIPID_F334 || sl->chip_id == STM32_CHIPID_F37x) { @@ -1989,6 +1992,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F3_SMALL || sl->chip_id == STM32_CHIPID_F303_HIGH || sl->chip_id == STM32_CHIPID_F37x || sl->chip_id == STM32_CHIPID_F334) { @@ -2057,6 +2061,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F3_SMALL || sl->chip_id == STM32_CHIPID_F303_HIGH || sl->chip_id == STM32_CHIPID_F37x || sl->chip_id == STM32_CHIPID_F334) { From 7fbd79eef39af26ba53d8117b8f80fc70b07ebd5 Mon Sep 17 00:00:00 2001 From: mlundinse Date: Thu, 13 Aug 2015 19:15:23 +0200 Subject: [PATCH 0330/1435] Added STM32F7 Support --- gdbserver/gdb-server.c | 26 +++++++++++++++++++++ src/stlink-common.c | 51 +++++++++++++++++++++++++++++------------- src/stlink-common.h | 12 ++++++++++ 3 files changed, 74 insertions(+), 15 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index a7f3c6cba..bae496d31 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -383,6 +383,30 @@ static const char* const memory_map_template = " " // option byte area ""; +static const char* const memory_map_template_F7 = + "" + "" + "" + " " // ITCM ram 16kB + " " // ITCM flash + " " // sram + " " // Sectors 0..3 + " 0x8000" // 32kB + " " + " " // Sector 4 + " 0x20000" // 128kB + " " + " " // Sectors 5..7 + " 0x40000" // 128kB + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + char* make_memory_map(stlink_t *sl) { /* This will be freed in serve() */ char* map = malloc(4096); @@ -390,6 +414,8 @@ char* make_memory_map(stlink_t *sl) { if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F446) { strcpy(map, memory_map_template_F4); + } else if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F7) { + strcpy(map, memory_map_template_F7); } else if(sl->chip_id==STM32_CHIPID_F4_HD) { strcpy(map, memory_map_template_F4_HD); } else if(sl->chip_id==STM32_CHIPID_F2) { diff --git a/src/stlink-common.c b/src/stlink-common.c index 7bf6f7263..dc24161d8 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -180,7 +180,7 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t res; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) res = stlink_read_debug32(sl, FLASH_F4_CR); else if (sl->chip_id == STM32_CHIPID_L4) res = stlink_read_debug32(sl, STM32L4_FLASH_CR); @@ -198,7 +198,7 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) return cr & (1 << FLASH_F4_CR_LOCK); else if (sl->chip_id == STM32_CHIPID_L4) return cr & (1lu << STM32L4_FLASH_CR_LOCK); @@ -214,7 +214,7 @@ static void unlock_flash(stlink_t *sl) { */ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) { stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); } else if (sl->chip_id == STM32_CHIPID_L4) { @@ -244,7 +244,7 @@ static int unlock_flash_if(stlink_t *sl) { static void lock_flash(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) { const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); stlink_write_debug32(sl, FLASH_F4_CR, n); } else if (sl->chip_id == STM32_CHIPID_L4) { @@ -261,7 +261,7 @@ static void lock_flash(stlink_t *sl) { static void set_flash_cr_pg(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_CR_PG); stlink_write_debug32(sl, FLASH_F4_CR, x); @@ -280,7 +280,7 @@ static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) stlink_write_debug32(sl, FLASH_F4_CR, n); else stlink_write_debug32(sl, FLASH_CR, n); @@ -299,7 +299,7 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { static void set_flash_cr_mer(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); else if (sl->chip_id == STM32_CHIPID_L4) { @@ -315,7 +315,7 @@ static void set_flash_cr_mer(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); else @@ -326,7 +326,7 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { static void set_flash_cr_strt(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_F4_CR_STRT); stlink_write_debug32(sl, FLASH_F4_CR, x); @@ -348,7 +348,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) res = stlink_read_debug32(sl, FLASH_F4_SR); else if (sl->chip_id == STM32_CHIPID_L4) res = stlink_read_debug32(sl, STM32L4_FLASH_SR); @@ -361,7 +361,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { static inline unsigned int is_flash_busy(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); else if (sl->chip_id == STM32_CHIPID_L4) return read_flash_sr(sl) & (1 << STM32L4_FLASH_SR_BSY); @@ -1137,7 +1137,7 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector>= 12) { sector -= 12; @@ -1159,7 +1159,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_L4)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1535,6 +1535,23 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000 }; + static const uint8_t loader_code_stm32f7[] = { + 0x08, 0x4b, + 0x72, 0xb1, + 0x04, 0x68, + 0x0c, 0x60, + 0xbf, 0xf3, 0x4f, 0x8f, // DSB Memory barrier for in order flash write + 0xdc, 0x89, + 0x14, 0xf0, 0x01, 0x0f, + 0xfb, 0xd1, + 0x00, 0xf1, 0x04, 0x00, + 0x01, 0xf1, 0x04, 0x01, + 0xa2, 0xf1, 0x01, 0x02, + 0xef, 0xe7, + 0x00, 0xbe, // bkpt #0x00 + 0x00, 0x3c, 0x02, 0x40, + }; + const uint8_t* loader_code; size_t loader_size; @@ -1561,6 +1578,9 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { loader_code = loader_code_stm32f4_lv; loader_size = sizeof(loader_code_stm32f4_lv); } + } else if (sl->chip_id == STM32_CHIPID_F7){ + loader_code = loader_code_stm32f7; + loader_size = sizeof(loader_code_stm32f7); } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); @@ -1746,6 +1766,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || (sl->chip_id == STM32_CHIPID_F446) || + (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) { /* todo: check write operation */ @@ -2005,7 +2026,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_L4)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -2069,7 +2090,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_L4)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { diff --git a/src/stlink-common.h b/src/stlink-common.h index 3fceeef62..76f977e9b 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -140,6 +140,8 @@ extern "C" { #define STM32_CHIPID_F0_CAN 0x448 +#define STM32_CHIPID_F7 0x449 + /* * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus" * and some that are called "High". 0x427 is assigned to the other "Medium- @@ -174,6 +176,16 @@ extern "C" { // These maps are from a combination of the Programming Manuals, and // also the Reference manuals. (flash size reg is normally in ref man) static const chip_params_t devices[] = { + { + //RM0385 and DS10916 document was used to find these paramaters + .chip_id = STM32_CHIPID_F7, + .description = "F7 device", + .flash_size_reg = 0x1ff0f442, // section 41.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 + .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18 + }, { // table 2, PM0063 .chip_id = STM32_CHIPID_F1_MEDIUM, .description = "F1 Medium-density device", From 21f87f56c419682072fcf64ec2f02877305eef55 Mon Sep 17 00:00:00 2001 From: mlundinse Date: Sat, 15 Aug 2015 18:56:40 +0200 Subject: [PATCH 0331/1435] Correct flash sector numbers and sizes for STM32F7 --- src/stlink-common.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index dc24161d8..53e5e9e70 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1117,6 +1117,14 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ } +uint32_t calculate_F7_sectornum(uint32_t flashaddr){ + flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address + if(flashaddr<0x20000) return(flashaddr/0x8000); + else if(flashaddr<0x40000) return(4); + else return(flashaddr/0x40000) +4; + +} + // Returns BKER:PNB for the given page address uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { uint32_t bker = 0; @@ -1137,7 +1145,7 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) { + (sl->chip_id == STM32_CHIPID_F446)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector>= 12) { sector -= 12; @@ -1146,6 +1154,12 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ else if(sector<5) sl->flash_pgsz=0x10000; else sl->flash_pgsz=0x20000; } + else if (sl->chip_id == STM32_CHIPID_F7) { + uint32_t sector=calculate_F7_sectornum(flashaddr); + if (sector<4) sl->flash_pgsz=0x8000; + else if(sector<5) sl->flash_pgsz=0x20000; + else sl->flash_pgsz=0x40000; + } return (sl->flash_pgsz); } @@ -1172,6 +1186,13 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) uint32_t page = calculate_L4_page(sl, flashaddr); write_flash_cr_bker_pnb(sl, page); + } else if (sl->chip_id == STM32_CHIPID_F7) { + // calculate the actual page from the address + uint32_t sector=calculate_F7_sectornum(flashaddr); + + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); + + write_flash_cr_snb(sl, sector); } else { // calculate the actual page from the address uint32_t sector=calculate_F4_sectornum(flashaddr); From e69a02d76093d5baa4b5cbcd028213a0516da9d6 Mon Sep 17 00:00:00 2001 From: mlundinse Date: Sat, 15 Aug 2015 19:23:53 +0200 Subject: [PATCH 0332/1435] Make sure MCU is halted before running RAM based flashloaders. --- flash/main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/flash/main.c b/flash/main.c index f84323217..2679bbbce 100644 --- a/flash/main.c +++ b/flash/main.c @@ -168,6 +168,11 @@ int main(int ac, char** av) stlink_write_mem32(sl,0x40026400+0x24+0x18*i,4); } } + + // Core must be halted to use RAM based flashloaders + stlink_force_debug(sl); + stlink_status(sl); + if (o.cmd == DO_WRITE) /* write */ { if ((o.addr >= sl->flash_base) && From 601d4d332967608ff49742942946ccb09e81a42a Mon Sep 17 00:00:00 2001 From: mlundinse Date: Sat, 15 Aug 2015 19:42:52 +0200 Subject: [PATCH 0333/1435] Make _stlink_usb_reset use hardreset --- src/stlink-common.h | 1 + src/stlink-usb.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/stlink-common.h b/src/stlink-common.h index 76f977e9b..9268da22c 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -68,6 +68,7 @@ extern "C" { #define STLINK_DEBUG_WRITEDEBUGREG 0x0f #define STLINK_DEBUG_ENTER_SWD 0xa3 #define STLINK_DEBUG_ENTER_JTAG 0x00 +#define STLINK_DEBUG_HARDRESET 0x3c // TODO - possible poor names... #define STLINK_SWD_ENTER 0x30 diff --git a/src/stlink-usb.c b/src/stlink-usb.c index d8b6c4673..47924c7be 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -413,7 +413,8 @@ void _stlink_usb_reset(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_RESETSYS; + cmd[i++] = STLINK_DEBUG_HARDRESET; + cmd[i++] = 0x2; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { From e047ef25db9745e091a519520414a24bbea42b91 Mon Sep 17 00:00:00 2001 From: Dave Vandervies Date: Wed, 12 Aug 2015 17:34:32 -0400 Subject: [PATCH 0334/1435] Correctly compute flash write size for partial pages --- gdbserver/gdb-server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index bae496d31..31f9beb00 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -705,8 +705,8 @@ static int flash_go(stlink_t *sl) { for(struct flash_block* fb = flash_root; fb; fb = fb->next) { DLOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length); - unsigned length = fb->length; for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += FLASH_PAGE) { + unsigned length = fb->length - (page - fb->addr); //Update FLASH_PAGE stlink_calculate_pagesize(sl, page); From bddf605006b85ccdf7a3ad2be5bb8bcd9b414609 Mon Sep 17 00:00:00 2001 From: bruno_dalbo Date: Mon, 17 Aug 2015 14:54:19 -0300 Subject: [PATCH 0335/1435] segmentation fault length fix --- gdbserver/gdb-server.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 0ddebb06f..d902eab7e 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -654,10 +654,12 @@ static int flash_go(stlink_t *sl) { stlink_calculate_pagesize(sl, page); DLOG("flash_do: page %08x\n", page); - + unsigned send = length > FLASH_PAGE ? FLASH_PAGE : length; if(stlink_write_flash(sl, page, fb->data + (page - fb->addr), - length > FLASH_PAGE ? FLASH_PAGE : length) < 0) + send) < 0) goto error; + length -= send; + } } From 69feeaa6003ec1450280bed7e0e9c552cdc1aa1d Mon Sep 17 00:00:00 2001 From: mlu Date: Fri, 21 Aug 2015 15:44:34 +0200 Subject: [PATCH 0336/1435] Revert "Make _stlink_usb_reset use hardreset" --- src/stlink-common.h | 1 - src/stlink-usb.c | 3 +-- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/stlink-common.h b/src/stlink-common.h index 9268da22c..76f977e9b 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -68,7 +68,6 @@ extern "C" { #define STLINK_DEBUG_WRITEDEBUGREG 0x0f #define STLINK_DEBUG_ENTER_SWD 0xa3 #define STLINK_DEBUG_ENTER_JTAG 0x00 -#define STLINK_DEBUG_HARDRESET 0x3c // TODO - possible poor names... #define STLINK_SWD_ENTER 0x30 diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 47924c7be..d8b6c4673 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -413,8 +413,7 @@ void _stlink_usb_reset(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_HARDRESET; - cmd[i++] = 0x2; + cmd[i++] = STLINK_DEBUG_RESETSYS; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { From a13aeeeff7970c18be486d1f62565768e6b43d43 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Efe=20Can=20=C4=B0=C3=A7=C3=B6z?= Date: Thu, 3 Sep 2015 11:32:12 +0300 Subject: [PATCH 0337/1435] correct error message is given upon missing pkg-config package. fixes texane/stlink#338 --- configure.ac | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configure.ac b/configure.ac index f1357b121..203cc6bd5 100644 --- a/configure.ac +++ b/configure.ac @@ -20,6 +20,11 @@ AC_CHECK_HEADERS(sys/mman.h) AC_CHECK_HEADERS(sys/poll.h) AC_REPLACE_FUNCS(mmap) +if ! hash pkg-config; then + echo "ERROR: pkg-config is needed..." + exit 1 +fi + # Checks for libraries. PKG_CHECK_MODULES(USB, libusb-1.0 >= 1.0.0,, AC_MSG_ERROR([*** Required libusb-1.0 >= 1.0.0 not installed ***])) From 768fe88e6ca721758d1d19edad429ec19a6fc8d3 Mon Sep 17 00:00:00 2001 From: mlundinse Date: Sat, 3 Oct 2015 16:36:37 +0200 Subject: [PATCH 0338/1435] Breakpoint handling for Cortex M7 --- gdbserver/gdb-server.c | 47 +++++++++++++++++++++++++++--------------- 1 file changed, 30 insertions(+), 17 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index c0166eb1e..27b801029 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -542,8 +542,9 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) return -1; } -#define CODE_BREAK_NUM 6 -#define CODE_LIT_NUM 2 +int code_break_num; +int code_lit_num; +#define CODE_BREAK_NUM_MAX 15 #define CODE_BREAK_LOW 0x01 #define CODE_BREAK_HIGH 0x02 @@ -552,37 +553,41 @@ struct code_hw_breakpoint { int type; }; -struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM]; +struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; static void init_code_breakpoints(stlink_t *sl) { memset(sl->q_buf, 0, 4); stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/); unsigned int val = stlink_read_debug32(sl, CM3_REG_FP_CTRL); - if (((val & 3) != 1) || - ((((val >> 8) & 0x70) | ((val >> 4) & 0xf)) != CODE_BREAK_NUM) || - (((val >> 8) & 0xf) != CODE_LIT_NUM)){ - ELOG("[FP_CTRL] = 0x%08x expecting 0x%08x\n", val, - ((CODE_BREAK_NUM & 0x70) << 8) | (CODE_LIT_NUM << 8) | ((CODE_BREAK_NUM & 0xf) << 4) | 1); - } + code_break_num = ((val >> 4) & 0xf); + code_lit_num = ((val >> 8) & 0xf); + ILOG("Found %i hw breakpoint registers\n", code_break_num); - for(int i = 0; i < CODE_BREAK_NUM; i++) { + for(int i = 0; i < code_break_num; i++) { code_breaks[i].type = 0; stlink_write_debug32(sl, CM3_REG_FP_COMP0 + i * 4, 0); } } static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { - stm32_addr_t fpb_addr = addr & ~0x3; - int type = addr & 0x2 ? CODE_BREAK_HIGH : CODE_BREAK_LOW; + stm32_addr_t fpb_addr; + uint32_t mask; + int type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW; if(addr & 1) { ELOG("update_code_breakpoint: unaligned address %08x\n", addr); return -1; } + if (sl->chip_id==STM32_CHIPID_F7) { + fpb_addr = addr; + } else { + fpb_addr = addr & ~0x3; + } + int id = -1; - for(int i = 0; i < CODE_BREAK_NUM; i++) { + for(int i = 0; i < code_break_num; i++) { if(fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { id = i; @@ -599,16 +604,23 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { brk->addr = fpb_addr; - if(set) brk->type |= type; - else brk->type &= ~type; + if (sl->chip_id==STM32_CHIPID_F7) { + if(set) brk->type = type; + else brk->type = 0; + + mask = (brk->addr) | 1; + } else { + if(set) brk->type |= type; + else brk->type &= ~type; + + mask = (brk->addr) | 1 | (brk->type << 30); + } if(brk->type == 0) { DLOG("clearing hw break %d\n", id); stlink_write_debug32(sl, 0xe0002008 + id * 4, 0); } else { - uint32_t mask = (brk->addr) | 1 | (brk->type << 30); - DLOG("setting hw break %d at %08x (%d)\n", id, brk->addr, brk->type); DLOG("reg %08x \n", @@ -701,6 +713,7 @@ static int flash_go(stlink_t *sl) { // Some kinds of clock settings do not allow writing to flash. stlink_reset(sl); + stlink_force_debug(sl); for(struct flash_block* fb = flash_root; fb; fb = fb->next) { DLOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length); From e37b65762dd5c9fa66ce6eac0021f31161b6528a Mon Sep 17 00:00:00 2001 From: lementec Date: Mon, 12 Oct 2015 08:07:59 +0200 Subject: [PATCH 0339/1435] README, add working target --- README | 1 + 1 file changed, 1 insertion(+) diff --git a/README b/README index 7aa3b8b69..10feb7dc2 100644 --- a/README +++ b/README @@ -200,5 +200,6 @@ Known Working Targets: * STM32F303RET6 (STM32 Nucleo-F303RE board) * STM32F334R8 (STM32 Nucleo-F334R8 board) * STM32F411RET6 (STM32 Nucleo-F411RE board) +& STM32F756NGHx (STMF7 evaluation board) Please report any and all known working combinations so I can update this! From 92bbca73b0dc128573834e6992c4bd6689e67e63 Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Fri, 23 Oct 2015 23:14:59 +0200 Subject: [PATCH 0340/1435] Add support to STM32F469/STM32F479 STM32F469 is a STM32F429 MCU with Dual-QSPI NOR support and DSI screen support. Signed-off-by: Maxime Coquelin --- src/stlink-common.c | 36 +++++++++++++++++++----------------- src/stlink-common.h | 12 ++++++++++++ 2 files changed, 31 insertions(+), 17 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 0ce67b25f..cfb1fbbaf 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -180,7 +180,7 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t res; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) res = stlink_read_debug32(sl, FLASH_F4_CR); else if (sl->chip_id == STM32_CHIPID_L4) res = stlink_read_debug32(sl, STM32L4_FLASH_CR); @@ -198,7 +198,7 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) return cr & (1 << FLASH_F4_CR_LOCK); else if (sl->chip_id == STM32_CHIPID_L4) return cr & (1lu << STM32L4_FLASH_CR_LOCK); @@ -214,7 +214,7 @@ static void unlock_flash(stlink_t *sl) { */ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); } else if (sl->chip_id == STM32_CHIPID_L4) { @@ -244,7 +244,7 @@ static int unlock_flash_if(stlink_t *sl) { static void lock_flash(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); stlink_write_debug32(sl, FLASH_F4_CR, n); } else if (sl->chip_id == STM32_CHIPID_L4) { @@ -261,7 +261,7 @@ static void lock_flash(stlink_t *sl) { static void set_flash_cr_pg(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_CR_PG); stlink_write_debug32(sl, FLASH_F4_CR, x); @@ -280,7 +280,7 @@ static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) stlink_write_debug32(sl, FLASH_F4_CR, n); else stlink_write_debug32(sl, FLASH_CR, n); @@ -299,7 +299,7 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { static void set_flash_cr_mer(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); else if (sl->chip_id == STM32_CHIPID_L4) { @@ -315,7 +315,7 @@ static void set_flash_cr_mer(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) stlink_write_debug32(sl, FLASH_F4_CR, stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); else @@ -326,7 +326,7 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { static void set_flash_cr_strt(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { uint32_t x = read_flash_cr(sl); x |= (1 << FLASH_F4_CR_STRT); stlink_write_debug32(sl, FLASH_F4_CR, x); @@ -348,7 +348,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) res = stlink_read_debug32(sl, FLASH_F4_SR); else if (sl->chip_id == STM32_CHIPID_L4) res = stlink_read_debug32(sl, STM32L4_FLASH_SR); @@ -361,7 +361,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { static inline unsigned int is_flash_busy(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7)) + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); else if (sl->chip_id == STM32_CHIPID_L4) return read_flash_sr(sl) & (1 << STM32L4_FLASH_SR_BSY); @@ -1145,7 +1145,7 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector>= 12) { sector -= 12; @@ -1173,7 +1173,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)|| (sl->chip_id == STM32_CHIPID_F4_DSI)) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1592,7 +1592,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446)){ + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)){ int voltage = stlink_target_voltage(sl); if (voltage > 2700) { loader_code = loader_code_stm32f4; @@ -1790,7 +1790,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t (sl->chip_id == STM32_CHIPID_F411RE) || (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || - (sl->chip_id == STM32_CHIPID_L4)) { + (sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_F4_DSI)) { /* todo: check write operation */ ILOG("Starting Flash write for F2/F4/L4\n"); @@ -2051,7 +2052,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -2116,7 +2117,8 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)) { + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_F4_DSI)) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { diff --git a/src/stlink-common.h b/src/stlink-common.h index 76f977e9b..a0bd64909 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -124,6 +124,9 @@ extern "C" { #define STM32_CHIPID_F37x 0x432 #define STM32_CHIPID_F4_DE 0x433 +#define STM32_CHIPID_F4_DE 0x433 + +#define STM32_CHIPID_F4_DSI 0x434 #define STM32_CHIPID_L1_HIGH 0x436 #define STM32_CHIPID_L152_RE 0x437 @@ -222,6 +225,15 @@ extern "C" { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800 }, + { + .chip_id = STM32_CHIPID_F4_DSI, + .description = "F46x and F47x device", + .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, { .chip_id = STM32_CHIPID_F4_HD, .description = "F42x and F43x device", From 323920a41e5bcb14cf7f7c0e961a1709ef245028 Mon Sep 17 00:00:00 2001 From: Rytis Karpuska Date: Mon, 9 Nov 2015 20:03:42 +0200 Subject: [PATCH 0341/1435] Implement simple non-blocking ring buffer for communication over stlink --- src/st-term.c | 144 +++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 114 insertions(+), 30 deletions(-) diff --git a/src/st-term.c b/src/st-term.c index 8350cfffc..af7b85ee1 100644 --- a/src/st-term.c +++ b/src/st-term.c @@ -11,8 +11,30 @@ #include #include "stlink-common.h" +/* STLinky structure on STM chip + +struct stlinky { + uint32_t magic; + uint32_t bufsize; + uint32_t up_tail; + uint32_t up_head; + uint32_t dw_tail; + uint32_t dw_head; + char upbuf[CONFIG_LIB_STLINKY_BSIZE]; + char dwbuf[CONFIG_LIB_STLINKY_BSIZE]; +} __attribute__ ((packed)); +*/ + + #define STLINKY_MAGIC 0xDEADF00D +#define ST_TERM_MAX_BUFF_SIZE (1024*1024) //1Mb + +#define RX_Q_OFFSET 8 +#define RX_BUFF_OFFSET 24 +#define TX_Q_OFFSET 16 +#define TX_BUFF_OFFSET(bufsize) (24 + bufsize) + #define READ_UINT32_LE(buf) ((uint32_t) ( buf[0] \ | buf[1] << 8 \ | buf[2] << 16 \ @@ -79,7 +101,7 @@ struct stlinky* stlinky_detect(stlink_t* sl) printf("stlinky detected at 0x%x\n", sram_base + off); st->off = sram_base + off; stlink_read_mem32(sl, st->off + 4, 4); - st->bufsize = (size_t) *(unsigned char*) sl->q_buf; + st->bufsize = READ_UINT32_LE(sl->q_buf); printf("stlinky buffer size 0x%zu \n", st->bufsize); multiple++; } @@ -93,41 +115,98 @@ struct stlinky* stlinky_detect(stlink_t* sl) return NULL; } -int stlinky_canrx(struct stlinky *st) +static void stlinky_read_buff(struct stlinky *st, uint32_t off, uint32_t size, char *buffer) +{ + int aligned_size; + + if (size == 0) + return; + + //Read from device with 4-byte alignment + aligned_size = (size & 0xFFFFFFFC) + 8; + stlink_read_mem32(st->sl, off & 0xFFFFFFFC, aligned_size); + + //copy to local buffer + memcpy(buffer, st->sl->q_buf + (off & 0x3), size); + + return; +} + +static void stlinky_write_buf(struct stlinky *st, uint32_t off, uint32_t size, char *buffer) { - stlink_read_mem32(st->sl, st->off+4, 4); - unsigned char tx = (unsigned char) st->sl->q_buf[1]; - return (int) tx; + memcpy(st->sl->q_buf, buffer, size); + stlink_write_mem8(st->sl, off, size); + return; } size_t stlinky_rx(struct stlinky *st, char* buffer) { - unsigned char tx = 0; - while(tx == 0) { - stlink_read_mem32(st->sl, st->off+4, 4); - tx = (unsigned char) st->sl->q_buf[1]; + //read head and tail values + uint32_t tail, head; + stlink_read_mem32(st->sl, st->off + RX_Q_OFFSET, sizeof(tail) + sizeof(head)); + memcpy(&tail, &st->sl->q_buf[0], sizeof(tail)); + memcpy(&head, &st->sl->q_buf[sizeof(tail)], sizeof(head)); + + //return if empty + if(head == tail) + return 0; + + //read data + int size_read = 0; + if(head > tail){ + stlinky_read_buff(st, st->off + RX_BUFF_OFFSET + tail, head - tail, buffer); + size_read += head - tail; + } else if(head < tail){ + stlinky_read_buff(st, st->off + RX_BUFF_OFFSET + tail, st->bufsize - tail, buffer); + size_read += st->bufsize - tail; + + stlinky_read_buff(st, st->off + RX_BUFF_OFFSET, head, buffer + size_read); + size_read += head; } - size_t rs = tx + (4 - (tx % 4)); /* voodoo */ - stlink_read_mem32(st->sl, st->off+8, rs); - memcpy(buffer, st->sl->q_buf, (size_t) tx); - *st->sl->q_buf=0x0; - stlink_write_mem8(st->sl, st->off+5, 1); - return (size_t) tx; + + //move tail + tail = (tail + size_read) % st->bufsize; + + //write tail + memcpy(st->sl->q_buf, &tail, sizeof(tail)); + stlink_write_mem32(st->sl, st->off + RX_Q_OFFSET, sizeof(tail)); + + return size_read; } -size_t stlinky_tx(struct stlinky *st, char* buffer, size_t sz) +size_t stlinky_tx(struct stlinky *st, char* buffer, size_t siz) { - unsigned char rx = 1; - while(rx != 0) { - stlink_read_mem32(st->sl, st->off+4, 4); - rx = (unsigned char) st->sl->q_buf[2]; - } - memcpy(st->sl->q_buf, buffer, sz); - size_t rs = sz + (4 - (sz % 4)); /* voodoo */ - stlink_write_mem32(st->sl, st->off+8+st->bufsize, rs); - *st->sl->q_buf=(unsigned char) sz; - stlink_write_mem8(st->sl, st->off+6, 1); - return (size_t) rx; + //read head and tail values + uint32_t tail, head; + stlink_read_mem32(st->sl, st->off + TX_Q_OFFSET, sizeof(tail) + sizeof(head)); + memcpy(&tail, &st->sl->q_buf[0], sizeof(tail)); + memcpy(&head, &st->sl->q_buf[sizeof(tail)], sizeof(head)); + + //Figure out buffer usage + int usage = head - tail; + if (usage < 0) + usage += st->bufsize; + + //check if new data will fit + if (usage + siz >= st->bufsize) + return 0; + + //copy in data (take care of possible split) + int first_chunk = head + siz >= st->bufsize ? st->bufsize - head : siz; + int second_chunk = siz - first_chunk; + + //copy data + stlinky_write_buf(st, st->off + TX_BUFF_OFFSET(st->bufsize) + head, first_chunk, buffer); + if (second_chunk > 0) + stlinky_write_buf(st, st->off + TX_BUFF_OFFSET(st->bufsize), + second_chunk, buffer + first_chunk); + + //increment head pointer + head = (head + siz) % st->bufsize; + memcpy(st->sl->q_buf, &head, sizeof(head)); + stlink_write_mem32(st->sl, st->off + TX_Q_OFFSET + sizeof(tail), sizeof(head)); + + return siz; } int kbhit() @@ -202,7 +281,7 @@ int main(int ac, char** av) { st->off = (int)strtol(av[1], NULL, 16); printf("using stlinky at 0x%x\n", st->off); stlink_read_mem32(sl, st->off + 4, 4); - st->bufsize = (size_t) *(unsigned char*) sl->q_buf; + st->bufsize = READ_UINT32_LE(sl->q_buf); printf("stlinky buffer size 0x%zu \n", st->bufsize); }else{ cleanup(0); @@ -212,6 +291,10 @@ int main(int ac, char** av) { printf("stlinky magic not found in sram :(\n"); cleanup(0); } + if (st->bufsize > ST_TERM_MAX_BUFF_SIZE){ + printf("stlinky buffer size too big\n"); + cleanup(0); + } char* rxbuf = malloc(st->bufsize); char* txbuf = malloc(st->bufsize); size_t tmp; @@ -222,8 +305,9 @@ int main(int ac, char** av) { printf("Entering interactive terminal. CTRL+C to exit\n\n\n"); while(1) { sig_process(); - if (stlinky_canrx(st)) { - tmp = stlinky_rx(st, rxbuf); + tmp = stlinky_rx(st, rxbuf); + if(tmp > 0) + { fwrite(rxbuf,tmp,1,stdout); fflush(stdout); } From d4d28e401f219aaa2941a1fe92777208a99b6e2f Mon Sep 17 00:00:00 2001 From: Josh Bialkowski Date: Mon, 16 Nov 2015 16:50:08 -0800 Subject: [PATCH 0342/1435] first stab at a cmake build --- CMakeLists.txt | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 CMakeLists.txt diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 000000000..6fbb3baf4 --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,75 @@ +cmake_minimum_required(VERSION 2.8.11) +project(stlink) + +find_package(PkgConfig) + +pkg_check_modules(libusb REQUIRED libusb-1.0) +pkg_check_modules(gtk gtk+-3.0) + +set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -std=gnu99 -Wall -Wextra") + +set(HFILES src/stlink-common.h + src/stlink-usb.h + src/stlink-sg.h + src/uglylogging.h + src/mmap.h) + +set(CFILES src/stlink-common.c + src/stlink-usb.c + src/stlink-sg.c + src/uglylogging.c + src/st-info.c) + +include_directories(${libusb_INCLUDE_DIRS}) +include_directories(src) +include_directories(mingw) + +add_library(stlink STATIC + ${HFILES} # header files for ide projects generated by cmake + ${CFILES}) +target_link_libraries(stlink ${libusb_LDFLAGS}) + +add_executable(st-flash flash/main.c) +target_link_libraries(st-flash stlink) + +add_executable(st-util gdbserver/gdb-remote.c + gdbserver/gdb-remote.h + gdbserver/gdb-server.c + gdbserver/gdb-server.h) +target_link_libraries(st-util stlink) + +install(TARGETS stlink st-flash st-util + RUNTIME DESTINATION bin + ARCHIVE DESTINATION lib) + +if(NOT ${MINGW}) + list(APPEND CFILES src/st-term.c) + add_executable(st-term src/st-term.c) + target_link_libraries(st-term stlink) + + install(TARGETS st-term + RUNTIME DESTINATION bin) +endif() + +if(gtk_FOUND) + include_directories(${gtk_INCLUDE_DIRS}) + set(GUI_SOURCES gui/stlink-gui.c + gui/stlink-gui.h) + + add_executable(stlink-gui-local ${GUI_SOURCES}) + set_target_properties(stlink-gui-local PROPERTIES + COMPILE_FLAGS -DSTLINK_UI_DIR=\\"${CMAKE_CURRENT_SOURCE_DIR}/gui\\") + target_link_libraries(stlink-gui-local stlink ${gtk_LDFLAGS}) + + set(INSTALLED_UI_DIR ${CMAKE_INSTALL_PREFIX}/share) + add_executable(stlink-gui ${GUI_SOURCES}) + set_target_properties(stlink-gui PROPERTIES + COMPILE_FLAGS -DSTLINK_UI_DIR=\\"${INSTALLED_UI_DIR}\\") + target_link_libraries(stlink-gui stlink ${gtk_LDFLAGS}) + + install(TARGETS stlink-gui + RUNTIME DESTINATION bin) + install(FILES gui/stlink-gui.ui + DESTINATION ${INSTALLED_UI_DIR}) +endif() + From deb2089e24236b24f4b2b53203210b03fcf878d1 Mon Sep 17 00:00:00 2001 From: bob Date: Thu, 19 Nov 2015 10:53:21 +0200 Subject: [PATCH 0343/1435] mingw compilation error (sleep) fixed --- mingw/mingw.h | 1 + 1 file changed, 1 insertion(+) diff --git a/mingw/mingw.h b/mingw/mingw.h index 1fcf93da2..cb333016c 100644 --- a/mingw/mingw.h +++ b/mingw/mingw.h @@ -65,5 +65,6 @@ char *win32_strsep(char **stringp, const char *delim); ssize_t win32_read_socket(SOCKET fd, void *buf, int n); ssize_t win32_write_socket(SOCKET fd, void *buf, int n); +static inline void sleep(unsigned ms) { Sleep(ms); } #endif From 308730bbadcd06353d662077db5d9713031ecec8 Mon Sep 17 00:00:00 2001 From: Josh Bialkowski Date: Thu, 19 Nov 2015 09:29:27 -0800 Subject: [PATCH 0344/1435] fix MINGW test in cmake --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 6fbb3baf4..2358898e3 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -42,7 +42,7 @@ install(TARGETS stlink st-flash st-util RUNTIME DESTINATION bin ARCHIVE DESTINATION lib) -if(NOT ${MINGW}) +if(NOT MINGW) list(APPEND CFILES src/st-term.c) add_executable(st-term src/st-term.c) target_link_libraries(st-term stlink) From 06fd9c4b700e681e04ec78f5664fd55674f94b6f Mon Sep 17 00:00:00 2001 From: Georg von Zengen Date: Mon, 7 Dec 2015 17:23:15 +0100 Subject: [PATCH 0345/1435] Added parameter to specify one stlink v2 of many This adds a parameter to the function stlink_open_usb and to the binary st-flash to specify one of multiple connected stlinks. As the identifier the iSerial of the stlink is used. If no serial is given the function and binary behave as before. --- flash/main.c | 38 +++++++++++++++++++++++++++++++++----- gdbserver/gdb-server.c | 2 +- gui/stlink-gui.c | 2 +- src/st-info.c | 2 +- src/st-term.c | 2 +- src/stlink-usb.c | 20 +++++++++++++++++--- src/stlink-usb.h | 2 +- src/test_usb.c | 2 +- 8 files changed, 56 insertions(+), 14 deletions(-) diff --git a/flash/main.c b/flash/main.c index 2679bbbce..d0d303a0d 100644 --- a/flash/main.c +++ b/flash/main.c @@ -17,6 +17,7 @@ struct opts { enum st_cmds cmd; const char* devname; + char *serial; const char* filename; stm32_addr_t addr; size_t size; @@ -26,11 +27,11 @@ struct opts static void usage(void) { - puts("stlinkv1 command line: ./st-flash [--debug] [--reset] {read|write} /dev/sgX path addr "); + puts("stlinkv1 command line: ./st-flash [--debug] [--reset] [--serial ] {read|write} /dev/sgX path addr "); puts("stlinkv1 command line: ./st-flash [--debug] /dev/sgX erase"); - puts("stlinkv2 command line: ./st-flash [--debug] [--reset] {read|write} path addr "); - puts("stlinkv2 command line: ./st-flash [--debug] erase"); - puts(" use hex format for addr and "); + puts("stlinkv2 command line: ./st-flash [--debug] [--reset] [--serial ] {read|write} path addr "); + puts("stlinkv2 command line: ./st-flash [--debug] [--serial ] erase"); + puts(" use hex format for addr, and "); } static int get_opts(struct opts* o, int ac, char** av) @@ -64,6 +65,31 @@ static int get_opts(struct opts* o, int ac, char** av) o->reset = 0; } + if (strcmp(av[0], "--serial") == 0) + { + ac--; + av++; + int i=strlen(av[0]); + if(i%2 != 0){ + puts("no valid hex value, length must be multiple of 2\n"); + return -1; + } + int j=0; + while(i>=0 && j<=13){ + char buffer[3]={0}; + memcpy(buffer,&av[0][i],2); + o->serial[12-j] = (char)strtol((const char*)buffer,NULL, 16); + j++; + i-=2; + } + ac--; + av++; + } + else + { + o->serial = NULL; + } + if (ac < 1) return -1; /* stlinkv2 */ @@ -123,6 +149,8 @@ int main(int ac, char** av) { stlink_t* sl = NULL; struct opts o; + char serial_buffer[13] = {0}; + o.serial = serial_buffer; int err = -1; o.size = 0; @@ -141,7 +169,7 @@ int main(int ac, char** av) } else /* stlinkv2 */ { - sl = stlink_open_usb(o.log_level, 1); + sl = stlink_open_usb(o.log_level, 1, o.serial); if (sl == NULL) goto on_error; sl->verbose = o.log_level; } diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 27b801029..b0245320e 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -173,7 +173,7 @@ int main(int argc, char** argv) { parse_options(argc, argv, &state); switch (state.stlink_version) { case 2: - sl = stlink_open_usb(state.logging_level, 0); + sl = stlink_open_usb(state.logging_level, 0, NULL); if(sl == NULL) return 1; break; case 1: diff --git a/gui/stlink-gui.c b/gui/stlink-gui.c index f60e92db0..93f92c462 100644 --- a/gui/stlink-gui.c +++ b/gui/stlink-gui.c @@ -530,7 +530,7 @@ connect_button_cb (GtkWidget *widget, gpointer data) /* try version 1 then version 2 */ gui->sl = stlink_v1_open(0, 1); if (gui->sl == NULL) { - gui->sl = stlink_open_usb(0, 1); + gui->sl = stlink_open_usb(0, 1, NULL); } if (gui->sl == NULL) { stlink_gui_set_info_error_message (gui, "Failed to connect to STLink."); return; diff --git a/src/st-info.c b/src/st-info.c index 6fe2f8d7a..66d9fb391 100644 --- a/src/st-info.c +++ b/src/st-info.c @@ -51,7 +51,7 @@ stlink_t* open_sl(void) stlink_t* sl; sl = stlink_v1_open(0, 1); if (sl == NULL) - sl = stlink_open_usb(0, 1); + sl = stlink_open_usb(0, 1, NULL); return sl; } diff --git a/src/st-term.c b/src/st-term.c index af7b85ee1..245ed5949 100644 --- a/src/st-term.c +++ b/src/st-term.c @@ -251,7 +251,7 @@ int main(int ac, char** av) { sig_init(); - sl = stlink_open_usb(10, 1); + sl = stlink_open_usb(10, 1, NULL); if (sl != NULL) { printf("ST-Linky proof-of-concept terminal :: Created by Necromant for lulz\n"); stlink_version(sl); diff --git a/src/stlink-usb.c b/src/stlink-usb.c index d8b6c4673..546f722ea 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -728,7 +728,7 @@ stlink_backend_t _stlink_usb_backend = { }; -stlink_t* stlink_open_usb(const int verbose, int reset) { +stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; int error = -1; @@ -747,7 +747,6 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { sl->backend_data = slu; sl->core_stat = STLINK_CORE_STAT_UNKNOWN; - if (libusb_init(&(slu->libusb_ctx))) { WLOG("failed to init libusb context, wrong version of libraries?\n"); goto on_error; @@ -776,7 +775,22 @@ stlink_t* stlink_open_usb(const int verbose, int reset) { if (desc.idVendor!=USB_ST_VID) continue; if (devBus && devAddr) if ((libusb_get_bus_number(list[cnt])!=devBus) || (libusb_get_device_address(list[cnt])!=devAddr)) continue; - if ( (desc.idProduct == USB_STLINK_32L_PID) || (desc.idProduct == USB_STLINK_NUCLEO_PID) ) break; + if ( (desc.idProduct == USB_STLINK_32L_PID) || (desc.idProduct == USB_STLINK_NUCLEO_PID) ){ + if ((p_usb_iserial != NULL)){ + unsigned char buffer[13]; + struct libusb_device_handle* handle; + libusb_open(list[cnt], &handle); + libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, buffer, 13); + libusb_close(handle); + if (memcmp(p_usb_iserial,&buffer,12) == 0){ + break; + }else{ + continue; + } + }else{ + break; + } + } if (desc.idProduct == USB_STLINK_PID) { slu->protocoll = 1; break; diff --git a/src/stlink-usb.h b/src/stlink-usb.h index 58b60e430..d7e745f51 100644 --- a/src/stlink-usb.h +++ b/src/stlink-usb.h @@ -30,7 +30,7 @@ extern "C" { unsigned int cmd_len; }; - stlink_t* stlink_open_usb(const int verbose, int reset); + stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial); #ifdef __cplusplus diff --git a/src/test_usb.c b/src/test_usb.c index eb8e54cdd..787ac12ce 100644 --- a/src/test_usb.c +++ b/src/test_usb.c @@ -10,7 +10,7 @@ int main(int ac, char** av) { ac = ac; av = av; - sl = stlink_open_usb(10, 1); + sl = stlink_open_usb(10, 1, NULL); if (sl != NULL) { printf("-- version\n"); stlink_version(sl); From 3ae69fe659bbc92a494a2c469327805c2516e99b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jean-Luc=20B=C3=A9chennec?= Date: Tue, 15 Dec 2015 15:12:55 +0100 Subject: [PATCH 0346/1435] Added STM32L053R8 Hello, checked this board with stink. It communicates without flaw with the board: ``` 2015-12-15T14:47:03 INFO src/stlink-common.c: Loading device parameters.... 2015-12-15T14:47:03 INFO src/stlink-common.c: Device connected is: L0x3 device, id 0x10086417 2015-12-15T14:47:03 INFO src/stlink-common.c: SRAM size: 0x2000 bytes (8 KiB), Flash: 0x10000 bytes (64 KiB) in pages of 128 bytes 2015-12-15T14:47:03 INFO gdbserver/gdb-server.c: Chip ID is 00000417, Core ID is 0bc11477. 2015-12-15T14:47:03 INFO gdbserver/gdb-server.c: Target voltage is 3264 mV. 2015-12-15T14:47:03 INFO gdbserver/gdb-server.c: Listening at *:4242... ``` When I launch GDB and connect to the server, I get : ``` 2015-12-15T14:51:41 ERROR gdbserver/gdb-server.c: [FP_CTRL] = 0x00000041 expecting 0x00000261 2015-12-15T14:51:41 INFO gdbserver/gdb-server.c: GDB connected. ``` on the st-util side and : ``` Cannot access memory at address 0xffffffff ``` on the GDB side Reading and writing to memory and registers works however I get ``` Cannot access memory at address 0xffffffff ``` Each time I write to the memory or to a register --- README | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/README b/README index 10feb7dc2..ac1dd0efd 100644 --- a/README +++ b/README @@ -200,6 +200,7 @@ Known Working Targets: * STM32F303RET6 (STM32 Nucleo-F303RE board) * STM32F334R8 (STM32 Nucleo-F334R8 board) * STM32F411RET6 (STM32 Nucleo-F411RE board) -& STM32F756NGHx (STMF7 evaluation board) +* STM32F756NGHx (STMF7 evaluation board) +* STM32L053R8 (STM32 Nucleo-L053R8 board) Please report any and all known working combinations so I can update this! From 177ef67b10f3d7e35cff91d470e09c9d09feec6b Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 17 Dec 2015 11:00:45 +0100 Subject: [PATCH 0347/1435] Do not send a NUL at end of packets to gdb. GDB doesn't need it and see the NUL as a junk character (visible with 'set debug remote 1'). --- gdbserver/gdb-remote.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/gdbserver/gdb-remote.c b/gdbserver/gdb-remote.c index a9eef3333..2f61b93ac 100644 --- a/gdbserver/gdb-remote.c +++ b/gdbserver/gdb-remote.c @@ -18,7 +18,8 @@ static const char hex[] = "0123456789abcdef"; int gdb_send_packet(int fd, char* data) { - int length = strlen(data) + 5; + unsigned int data_length = strlen(data); + int length = data_length + 4; char* packet = malloc(length); /* '$' data (hex) '#' cksum (hex) */ memset(packet, 0, length); @@ -26,14 +27,14 @@ int gdb_send_packet(int fd, char* data) { packet[0] = '$'; uint8_t cksum = 0; - for(unsigned int i = 0; i < strlen(data); i++) { + for(unsigned int i = 0; i < data_length; i++) { packet[i + 1] = data[i]; cksum += data[i]; } - packet[length - 4] = '#'; - packet[length - 3] = hex[cksum >> 4]; - packet[length - 2] = hex[cksum & 0xf]; + packet[length - 3] = '#'; + packet[length - 2] = hex[cksum >> 4]; + packet[length - 1] = hex[cksum & 0xf]; while(1) { if(write(fd, packet, length) != length) { From cce54ea2c71ffc7a2cc03e396c7c052f566f65a9 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Thu, 17 Dec 2015 11:05:00 +0100 Subject: [PATCH 0348/1435] stm32f7: also send features to gdb. So that 'extra' registers (msp, psp, ...) are visible to user. --- gdbserver/gdb-server.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index b0245320e..fd40fbfad 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -840,7 +840,9 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("query: %s;%s\n", queryName, params); if(!strcmp(queryName, "Supported")) { - if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F4_HD) { + if(sl->chip_id==STM32_CHIPID_F4 + || sl->chip_id==STM32_CHIPID_F4_HD + || sl->chip_id==STM32_CHIPID_F7) { reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); } else { From 54c8d2ca8b99c27761b45f35cd17f79512cb4a23 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 11 Jan 2016 15:44:17 +0100 Subject: [PATCH 0349/1435] st-util: synchronize cache for stm32f7 This patch handles the cache on the cortex-m7 stm32f7 cpu. When gdb inserts a soft breakpoint (which is the default for code in RAM), it replaces an instruction with a breakpoint instruction. But if the caches are enabled, the replacement may be made only in the D-cache. To reach the I-cache, the D-cache must be flushed and the I-cache invalidated. This implementation is coarse: it cleans the whole D-cache and invalidate the whole I-cache. It is possible to track which cache lines have to be cleaned and invalidated. --- gdbserver/gdb-server.c | 164 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index fd40fbfad..49c7e6dd4 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -49,6 +49,7 @@ typedef struct _st_state_t { int serve(stlink_t *sl, st_state_t *st); char* make_memory_map(stlink_t *sl); +static void init_cache (stlink_t *sl); static void cleanup(int signal __attribute__((unused))) { if (connected_stlink) { @@ -208,6 +209,8 @@ int main(int argc, char** argv) { } #endif + init_cache(sl); + do { if (serve(sl, &state)) { sleep (1); // don't go bezurk if serve returns with error @@ -750,6 +753,161 @@ static int flash_go(stlink_t *sl) { return error; } +#define CLIDR 0xE000ED78 +#define CTR 0xE000ED7C +#define CCSIDR 0xE000ED80 +#define CSSELR 0xE000ED84 +#define CCR 0xE000ED14 +#define CCR_DC (1 << 16) +#define CCR_IC (1 << 17) +#define DCCSW 0xE000EF6C +#define ICIALLU 0xE000EF50 + +struct cache_level_desc +{ + unsigned int nsets; + unsigned int nways; + unsigned int log2_nways; + unsigned int width; +}; + +struct cache_desc_t +{ + /* Minimal line size in bytes. */ + unsigned int dminline; + unsigned int iminline; + + /* Last level of unification (uniprocessor). */ + unsigned int louu; + + struct cache_level_desc icache[7]; + struct cache_level_desc dcache[7]; +}; + +static struct cache_desc_t cache_desc; + +/* Return the smallest R so that V <= (1 << R). Not performance critical. */ +static unsigned ceil_log2(unsigned v) +{ + unsigned res; + for (res = 0; (1 << res) < v; res++) + ; + return res; +} + +static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) +{ + unsigned int ccsidr; + unsigned int log2_nsets; + ccsidr = stlink_read_debug32(sl, CCSIDR); + desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1; + desc->nways = ((ccsidr >> 3) & 0x1ff) + 1; + desc->log2_nways = ceil_log2 (desc->nways); + log2_nsets = ceil_log2 (desc->nsets); + desc->width = 4 + (ccsidr & 7) + log2_nsets; + ILOG("%08x LineSize: %u, ways: %u, sets: %u (width: %u)\n", + ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width); +} + +static void init_cache (stlink_t *sl) { + unsigned int clidr; + unsigned int ccr; + unsigned int ctr; + int i; + + /* Assume only F7 has a cache. */ + if(sl->chip_id!=STM32_CHIPID_F7) + return; + + clidr = stlink_read_debug32(sl, CLIDR); + ccr = stlink_read_debug32(sl, CCR); + ctr = stlink_read_debug32(sl, CTR); + cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f); + cache_desc.iminline = 4 << (ctr & 0x0f); + cache_desc.louu = (clidr >> 27) & 7; + + ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n", + clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off"); + ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n", + (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7); + ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr, + cache_desc.dminline, cache_desc.iminline); + for(i = 0; i < 7; i++) + { + unsigned int ct = (clidr >> (3 * i)) & 0x07; + + cache_desc.dcache[i].width = 0; + cache_desc.icache[i].width = 0; + + if(ct == 2 || ct == 3 || ct == 4) + { + /* Data. */ + stlink_write_debug32(sl, CSSELR, i << 1); + ILOG("D-Cache L%d: ", i); + read_cache_level_desc(sl, &cache_desc.dcache[i]); + } + + if(ct == 1 || ct == 3) + { + /* Instruction. */ + stlink_write_debug32(sl, CSSELR, (i << 1) | 1); + ILOG("I-Cache L%d: ", i); + read_cache_level_desc(sl, &cache_desc.icache[i]); + } + } +} + +static void cache_flush(stlink_t *sl, unsigned ccr) { + int level; + + if (ccr & CCR_DC) + for (level = cache_desc.louu - 1; level >= 0; level--) + { + struct cache_level_desc *desc = &cache_desc.dcache[level]; + unsigned addr; + unsigned max_addr = 1 << desc->width; + unsigned way_sh = 32 - desc->log2_nways; + + /* D-cache clean by set-ways. */ + for (addr = (level << 1); addr < max_addr; addr += cache_desc.dminline) + { + unsigned int way; + + for (way = 0; way < desc->nways; way++) + stlink_write_debug32(sl, DCCSW, addr | (way << way_sh)); + } + } + + /* Invalidate all I-cache to oPU. */ + if (ccr & CCR_IC) + stlink_write_debug32(sl, ICIALLU, 0); +} + +static int cache_modified; + +static void cache_change(stm32_addr_t start, unsigned count) +{ + if (count == 0) + return; + (void)start; + cache_modified = 1; +} + +static void cache_sync(stlink_t *sl) +{ + unsigned ccr; + + if(sl->chip_id!=STM32_CHIPID_F7) + return; + if (!cache_modified) + return; + cache_modified = 0; + + ccr = stlink_read_debug32(sl, CCR); + if (ccr & (CCR_IC | CCR_DC)) + cache_flush(sl, ccr); +} + int serve(stlink_t *sl, st_state_t *st) { int sock = socket(AF_INET, SOCK_STREAM, 0); if(sock < 0) { @@ -898,6 +1056,7 @@ int serve(stlink_t *sl, st_state_t *st) { if (!strncmp(params,"726573756d65",12)) {// resume DLOG("Rcmd: resume\n"); + cache_sync(sl); stlink_run(sl); reply = strdup("OK"); @@ -1016,6 +1175,7 @@ int serve(stlink_t *sl, st_state_t *st) { } case 'c': + cache_sync(sl); stlink_run(sl); while(1) { @@ -1045,6 +1205,7 @@ int serve(stlink_t *sl, st_state_t *st) { break; case 's': + cache_sync(sl); stlink_step(sl); reply = strdup("S05"); // TRAP @@ -1199,6 +1360,7 @@ int serve(stlink_t *sl, st_state_t *st) { sl->q_buf[i] = byte; } stlink_write_mem8(sl, start, align_count); + cache_change(start, align_count); start += align_count; count -= align_count; hexdata += 2*align_count; @@ -1213,6 +1375,7 @@ int serve(stlink_t *sl, st_state_t *st) { sl->q_buf[i] = byte; } stlink_write_mem32(sl, start, aligned_count); + cache_change(start, aligned_count); count -= aligned_count; start += aligned_count; hexdata += 2*aligned_count; @@ -1225,6 +1388,7 @@ int serve(stlink_t *sl, st_state_t *st) { sl->q_buf[i] = byte; } stlink_write_mem8(sl, start, count); + cache_change(start, count); } reply = strdup("OK"); break; From 433a0eb53aad10a00b4a1513099a1c54095a84f9 Mon Sep 17 00:00:00 2001 From: Greg Meiste Date: Mon, 19 Oct 2015 09:24:40 -0500 Subject: [PATCH 0350/1435] Allow flashing of STM32L4 down to 1.71 V The STM32L4 specification specifies that VDD can be 1.71 - 3.6 V. Signed-off-by: Greg Meiste --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index cfb1fbbaf..4ad28eef3 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1818,7 +1818,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } else { /* L4 does not have a byte-write mode */ int voltage = stlink_target_voltage(sl); - if (voltage <= 2700) { + if (voltage < 1710) { printf("Target voltage (%d mV) too low for flash writes!\n", voltage); return -1; } From ff40ab6681591efa23d1068faae3417ff75d2393 Mon Sep 17 00:00:00 2001 From: Greg Meiste Date: Wed, 27 May 2015 10:12:40 -0500 Subject: [PATCH 0351/1435] Fix issue where "unknown chip id!" is seen every other time Previously when running the program, reading the chip version would fail. Running the program a second time worked. This sequence is repeated the next time st-flash/st-util is run. Giving reset 10ms to complete before trying to read the chip version resolves the issue. Signed-off-by: Greg Meiste --- src/stlink-usb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 546f722ea..0911ff7b9 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -6,6 +6,7 @@ #include #include #include +#include #include "stlink-common.h" #include "stlink-usb.h" @@ -879,6 +880,7 @@ stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { if (reset) { stlink_reset(sl); + usleep(10000); } stlink_version(sl); error = stlink_load_device_params(sl); From 2d8cb6be855d83af9dfd46601d6e08faf957a563 Mon Sep 17 00:00:00 2001 From: Greg Meiste Date: Wed, 27 May 2015 13:20:07 -0500 Subject: [PATCH 0352/1435] Add memory map for STM32L4 Signed-off-by: Greg Meiste --- gdbserver/gdb-server.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 49c7e6dd4..12c7c9f94 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -370,6 +370,25 @@ static const char* const memory_map_template_F2 = " " // option byte area ""; +static const char* const memory_map_template_L4 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM2 (32 KB) + " " // SRAM1 (96 KB) + " " + " 0x800" + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + " " // option byte area + ""; + static const char* const memory_map_template = "" "sram_size, sl->flash_size - 0x20000, sl->sys_base, sl->sys_size); + } else if(sl->chip_id==STM32_CHIPID_L4) { + snprintf(map, 4096, memory_map_template_L4, + sl->flash_size, sl->flash_size); } else { snprintf(map, 4096, memory_map_template, sl->flash_size, From ea649eb6e7cf3dbe98dc00f5a96566df9b6fdcea Mon Sep 17 00:00:00 2001 From: Greg Meiste Date: Mon, 1 Feb 2016 09:08:59 -0600 Subject: [PATCH 0353/1435] st-util: Fix for connecting to running devices Previously, even with the reset enabled, st-util would not connect to a target if it was running. This change will reset the chip when opening the connection, which allows st-util to connect successfully. Signed-off-by: Greg Meiste --- gdbserver/gdb-server.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 49c7e6dd4..1981fc5e2 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -174,11 +174,11 @@ int main(int argc, char** argv) { parse_options(argc, argv, &state); switch (state.stlink_version) { case 2: - sl = stlink_open_usb(state.logging_level, 0, NULL); + sl = stlink_open_usb(state.logging_level, state.reset, NULL); if(sl == NULL) return 1; break; case 1: - sl = stlink_v1_open(state.logging_level, 0); + sl = stlink_v1_open(state.logging_level, state.reset); if(sl == NULL) return 1; break; } From c632f855ef63a7421bf200f9979aee6ec57eb1ed Mon Sep 17 00:00:00 2001 From: "fabien.lementec" Date: Mon, 1 Feb 2016 17:02:55 +0100 Subject: [PATCH 0354/1435] fix signed unsigned comparison --- gdbserver/gdb-server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 1fe076eec..c8152118b 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -812,7 +812,7 @@ static struct cache_desc_t cache_desc; static unsigned ceil_log2(unsigned v) { unsigned res; - for (res = 0; (1 << res) < v; res++) + for (res = 0; (1U << res) < v; res++) ; return res; } From 094fe67773541cd4547a4dbf4804f51b4293597e Mon Sep 17 00:00:00 2001 From: Bruno Dal Bo Date: Wed, 3 Feb 2016 13:06:18 -0800 Subject: [PATCH 0355/1435] fix on stm32l4 to clear flash mass erase flags on CR --- src/stlink-common.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index 4ad28eef3..f2888d10b 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -435,6 +435,8 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { uint32_t x = read_flash_cr(sl); x &=~ STM32L4_FLASH_CR_OPBITS; x &=~ STM32L4_FLASH_CR_PAGEMASK; + x &= ~(1< Date: Wed, 3 Feb 2016 13:10:54 -0800 Subject: [PATCH 0356/1435] clean SR flags before programming CR --- src/stlink-common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/stlink-common.c b/src/stlink-common.c index f2888d10b..04e616762 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -432,6 +432,7 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { } static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { + stlink_write_debug32(sl, STM32L4_FLASH_SR, 0xFFFFFFFF & ~(1< Date: Mon, 15 Feb 2016 14:55:09 +0100 Subject: [PATCH 0357/1435] Added STM32F051R8T6 --- README | 1 + 1 file changed, 1 insertion(+) diff --git a/README b/README index ac1dd0efd..1f9d33cdd 100644 --- a/README +++ b/README @@ -190,6 +190,7 @@ Known Working Targets: * STM32L052K8T6 (custom board) * STM32L151CB (custom board) * STM32L152RB (STM32L-Discovery board, custom board) +* STM32F051R8T6 (STM320518-EVAL board) STLink v2-1 (as found on the Nucleo boards) Known Working Targets: From 23c79078aceff7103fa56894e1554a71ee9e308c Mon Sep 17 00:00:00 2001 From: George Talusan Date: Thu, 18 Feb 2016 22:56:27 -0500 Subject: [PATCH 0358/1435] remove empty byte truncation from stlink_fread --- src/stlink-common.c | 41 +++++++++++++---------------------------- 1 file changed, 13 insertions(+), 28 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 04e616762..f17bf72c7 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1032,9 +1032,6 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) int error = -1; size_t off; int num_empty = 0; - unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 - || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH - || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { @@ -1048,38 +1045,26 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) if (size > sl->flash_size) size = sl->flash_size; - /* do the copy by 1k blocks */ - for (off = 0; off < size; off += 1024) { - size_t read_size = 1024; - size_t rounded_size; - size_t index; - if ((off + read_size) > size) - read_size = size - off; + size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz; + for (off = 0; off < size; off += cmp_size) { + size_t aligned_size; - /* round size if needed */ - rounded_size = read_size; - if (rounded_size & 3) - rounded_size = (rounded_size + 4) & ~(3); + /* adjust last page size */ + if ((off + cmp_size) > size) + cmp_size = size - off; - stlink_read_mem32(sl, addr + off, rounded_size); + aligned_size = cmp_size; + if (aligned_size & (4 - 1)) + aligned_size = (cmp_size + 4) & ~(4 - 1); - for(index = 0; index < read_size; index ++) { - if (sl->q_buf[index] == erased_pattern) - num_empty ++; - else - num_empty = 0; - } - if (write(fd, sl->q_buf, read_size) != (ssize_t) read_size) { - fprintf(stderr, "write() != read_size\n"); + stlink_read_mem32(sl, addr + off, aligned_size); + + if (write(fd, sl->q_buf, sl->q_len) != (ssize_t) aligned_size) { + fprintf(stderr, "write() != aligned_size\n"); goto on_error; } } - /* Ignore NULL Bytes at end of file */ - if (!ftruncate(fd, size - num_empty)) { - error = -1; - } - /* success */ error = 0; From 426cdd08669f51f8d8aa5307280f59898694a30c Mon Sep 17 00:00:00 2001 From: George Talusan Date: Fri, 19 Feb 2016 00:04:44 -0500 Subject: [PATCH 0359/1435] clamp gdb memory reads to 0x1800 --- gdbserver/gdb-server.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index c8152118b..b272f4caa 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -1353,6 +1353,12 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned adj_start = start % 4; unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; + if (count_rnd > sl->flash_pgsz) + count_rnd = sl->flash_pgsz; + if (count_rnd > 0x1800) + count_rnd = 0x1800; + if (count_rnd < count) + count = count_rnd; stlink_read_mem32(sl, start - adj_start, count_rnd); From 210858549fa7f6e2dad54486027cbe5f8ff66e16 Mon Sep 17 00:00:00 2001 From: George Talusan Date: Fri, 19 Feb 2016 11:11:31 -0500 Subject: [PATCH 0360/1435] use libusb synchronous api --- src/stlink-common.c | 1 - src/stlink-usb.c | 139 ++++++-------------------------------------- src/stlink-usb.h | 2 - 3 files changed, 19 insertions(+), 123 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index f17bf72c7..90d71f31e 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1031,7 +1031,6 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) int error = -1; size_t off; - int num_empty = 0; const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); if (fd == -1) { diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 0911ff7b9..d54aea875 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -12,32 +12,12 @@ #include "stlink-usb.h" #include "uglylogging.h" -/* code from bsd timersub.h -http://www.gnu-darwin.org/www001/src/ports/net/libevnet/work/libevnet-0.3.8/libnostd/bsd/sys/time/timersub.h.html -*/ -#if !defined timersub -#define timersub(a, b, r) do { \ - (r)->tv_sec = (a)->tv_sec - (b)->tv_sec; \ - (r)->tv_usec = (a)->tv_usec - (b)->tv_usec; \ - if ((r)->tv_usec < 0) { \ - --(r)->tv_sec; \ - (r)->tv_usec += 1000000; \ - } \ -} while (0) -#endif - enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; void _stlink_usb_close(stlink_t* sl) { struct stlink_libusb * const handle = sl->backend_data; // maybe we couldn't even get the usb device? if (handle != NULL) { - if (handle->req_trans != NULL) - libusb_free_transfer(handle->req_trans); - - if (handle->rep_trans != NULL) - libusb_free_transfer(handle->rep_trans); - if (handle->usb_handle != NULL) { libusb_close(handle->usb_handle); } @@ -47,111 +27,42 @@ void _stlink_usb_close(stlink_t* sl) { } } - -struct trans_ctx { -#define TRANS_FLAGS_IS_DONE (1 << 0) -#define TRANS_FLAGS_HAS_ERROR (1 << 1) - volatile unsigned long flags; -}; - -#ifndef LIBUSB_CALL -# define LIBUSB_CALL -#endif - -static void LIBUSB_CALL on_trans_done(struct libusb_transfer * trans) { - struct trans_ctx * const ctx = trans->user_data; - - if (trans->status != LIBUSB_TRANSFER_COMPLETED) - ctx->flags |= TRANS_FLAGS_HAS_ERROR; - - ctx->flags |= TRANS_FLAGS_IS_DONE; -} - -int submit_wait(struct stlink_libusb *slu, struct libusb_transfer * trans) { - struct timeval start; - struct timeval now; - struct timeval diff; - struct trans_ctx trans_ctx; - enum libusb_error error; - - trans_ctx.flags = 0; - - /* brief intrusion inside the libusb interface */ - trans->callback = on_trans_done; - trans->user_data = &trans_ctx; - - if ((error = libusb_submit_transfer(trans))) { - printf("libusb_submit_transfer(%d)\n", error); - return -1; - } - - gettimeofday(&start, NULL); - - while (trans_ctx.flags == 0) { - struct timeval timeout; - timeout.tv_sec = 3; - timeout.tv_usec = 0; - if (libusb_handle_events_timeout(slu->libusb_ctx, &timeout)) { - printf("libusb_handle_events()\n"); - return -1; - } - - gettimeofday(&now, NULL); - timersub(&now, &start, &diff); - if (diff.tv_sec >= 3) { - printf("libusb_handle_events() timeout\n"); - return -1; - } - } - - if (trans_ctx.flags & TRANS_FLAGS_HAS_ERROR) { - printf("libusb_handle_events() | has_error\n"); - return -1; - } - - return 0; -} - ssize_t send_recv(struct stlink_libusb* handle, int terminate, unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, size_t rxsize) { /* note: txbuf and rxbuf can point to the same area */ int res = 0; - libusb_fill_bulk_transfer(handle->req_trans, handle->usb_handle, - handle->ep_req, - txbuf, txsize, - NULL, NULL, - 0 - ); - - if (submit_wait(handle, handle->req_trans)) return -1; + if (libusb_bulk_transfer(handle->usb_handle, handle->ep_req, + txbuf, + txsize, + &res, + 3000)) + return -1; - /* send_only */ if (rxsize != 0) { - - /* read the response */ - - libusb_fill_bulk_transfer(handle->rep_trans, handle->usb_handle, - handle->ep_rep, rxbuf, rxsize, NULL, NULL, 0); - - if (submit_wait(handle, handle->rep_trans)) return -1; - res = handle->rep_trans->actual_length; + if (libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, + rxbuf, + rxsize, + &res, + 3000)) + return -1; } if ((handle->protocoll == 1) && terminate) { /* Read the SG reply */ unsigned char sg_buf[13]; - libusb_fill_bulk_transfer - (handle->rep_trans, handle->usb_handle, - handle->ep_rep, sg_buf, 13, NULL, NULL, 0); - res = submit_wait(handle, handle->rep_trans); + if (libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, + sg_buf, + 13, + &res, + 3000)) + return -1; /* The STLink doesn't seem to evaluate the sequence number */ handle->sg_transfer_idx++; - if (res ) return -1; } - return handle->rep_trans->actual_length; + return res; } static inline int send_only @@ -843,18 +754,6 @@ stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { goto on_libusb_error; } - slu->req_trans = libusb_alloc_transfer(0); - if (slu->req_trans == NULL) { - WLOG("libusb_alloc_transfer failed\n"); - goto on_libusb_error; - } - - slu->rep_trans = libusb_alloc_transfer(0); - if (slu->rep_trans == NULL) { - WLOG("libusb_alloc_transfer failed\n"); - goto on_libusb_error; - } - // TODO - could use the scanning techniq from stm8 code here... slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; if (desc.idProduct == USB_STLINK_NUCLEO_PID) { diff --git a/src/stlink-usb.h b/src/stlink-usb.h index d7e745f51..938c07bcb 100644 --- a/src/stlink-usb.h +++ b/src/stlink-usb.h @@ -21,8 +21,6 @@ extern "C" { struct stlink_libusb { libusb_context* libusb_ctx; libusb_device_handle* usb_handle; - struct libusb_transfer* req_trans; - struct libusb_transfer* rep_trans; unsigned int ep_req; unsigned int ep_rep; int protocoll; From 969fa1279b98e1198aa4fc684b580d35b8f2c480 Mon Sep 17 00:00:00 2001 From: George Talusan Date: Mon, 22 Feb 2016 11:41:48 -0500 Subject: [PATCH 0361/1435] make usb backend status check work, remove some dead code --- src/stlink-usb.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index d54aea875..c4c693d2b 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -259,6 +259,7 @@ void _stlink_usb_status(stlink_t * sl) { printf("[!] send_recv\n"); return; } + sl->q_len = (size_t) size; } void _stlink_usb_force_debug(stlink_t *sl) { @@ -644,7 +645,6 @@ stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; int error = -1; - libusb_device** devs = NULL; int config; sl = malloc(sizeof (stlink_t)); @@ -785,10 +785,6 @@ stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { error = stlink_load_device_params(sl); on_libusb_error: - if (devs != NULL) { - libusb_free_device_list(devs, 1); - } - if (error == -1) { stlink_close(sl); return NULL; From 09a81132776d0be0ae563a31929eb2f33d68e8bd Mon Sep 17 00:00:00 2001 From: George Talusan Date: Mon, 22 Feb 2016 20:07:43 -0500 Subject: [PATCH 0362/1435] make st-flash clean up on sigint/term/segv, make gdb-server clean up on sigsegv. --- flash/main.c | 19 +++++++++++++++++++ gdbserver/gdb-server.c | 2 +- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/flash/main.c b/flash/main.c index d0d303a0d..284068cb5 100644 --- a/flash/main.c +++ b/flash/main.c @@ -3,6 +3,7 @@ // TODO - this should be done as just a simple flag to the st-util command line... +#include #include #include #include @@ -12,6 +13,19 @@ #define DEBUG_LOG_LEVEL 100 #define STND_LOG_LEVEL 50 +stlink_t *connected_stlink = NULL; + +static void cleanup(int signal __attribute__((unused))) { + if (connected_stlink) { + /* Switch back to mass storage mode before closing. */ + stlink_run(connected_stlink); + stlink_exit_debug_mode(connected_stlink); + stlink_close(connected_stlink); + } + + exit(1); +} + enum st_cmds {DO_WRITE = 0, DO_READ = 1, DO_ERASE = 2}; struct opts { @@ -174,6 +188,11 @@ int main(int ac, char** av) sl->verbose = o.log_level; } + connected_stlink = sl; + signal(SIGINT, &cleanup); + signal(SIGTERM, &cleanup); + signal(SIGSEGV, &cleanup); + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) stlink_exit_dfu_mode(sl); diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index b272f4caa..0c31cff18 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #ifdef __MINGW32__ @@ -186,6 +185,7 @@ int main(int argc, char** argv) { connected_stlink = sl; signal(SIGINT, &cleanup); signal(SIGTERM, &cleanup); + signal(SIGSEGV, &cleanup); if (state.reset) { stlink_reset(sl); From 60bd03a5178e338b04703783a686d9c73633ba63 Mon Sep 17 00:00:00 2001 From: George Talusan Date: Sat, 27 Feb 2016 11:41:39 -0500 Subject: [PATCH 0363/1435] be quicker about determining erased byte pattern when flashing --- gdbserver/gdb-server.c | 2 +- src/stlink-common.c | 18 ++++++++++-------- src/stlink-common.h | 2 +- 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index 0c31cff18..ef289f282 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -752,7 +752,7 @@ static int flash_go(stlink_t *sl) { DLOG("flash_do: page %08x\n", page); unsigned send = length > FLASH_PAGE ? FLASH_PAGE : length; if(stlink_write_flash(sl, page, fb->data + (page - fb->addr), - send) < 0) + send, 0) < 0) goto error; length -= send; diff --git a/src/stlink-common.c b/src/stlink-common.c index 90d71f31e..917a1e0e3 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1723,7 +1723,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin return 0; } -int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { +int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint8_t eraseonly) { size_t off; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", @@ -1769,6 +1769,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t ILOG("Finished erasing %d pages of %d (%#x) bytes\n", page_count, sl->flash_pgsz, sl->flash_pgsz); + if (eraseonly) + return 0; + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || @@ -1972,19 +1975,18 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { ELOG("map_file() == -1\n"); return -1; } - for(index = 0; index < mf.len; index ++) { - if (mf.base[index] == erased_pattern) - num_empty ++; - else - num_empty = 0; + for(index = mf.len - 1; num_empty < mf.len; index --) { + if (mf.base[index] != erased_pattern) { + break; + } + num_empty ++; } /* Round down to words */ num_empty -= (num_empty & 3); if(num_empty != 0) { ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); - mf.len -= num_empty; } - err = stlink_write_flash(sl, addr, mf.base, mf.len); + err = stlink_write_flash(sl, addr, mf.base, num_empty == mf.len? mf.len : mf.len - num_empty, num_empty == mf.len); /* set stack*/ stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13); /* Set PC to the reset routine*/ diff --git a/src/stlink-common.h b/src/stlink-common.h index a0bd64909..2751ac839 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -655,7 +655,7 @@ extern "C" { // unprocessed int stlink_erase_flash_mass(stlink_t* sl); - int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length); + int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); From 5df03b2270d6a9c0194b5abc96da2eba9ab083ff Mon Sep 17 00:00:00 2001 From: texane Date: Sat, 27 Feb 2016 19:17:19 +0100 Subject: [PATCH 0364/1435] be quicker about determining erased byte pattern when flashing, more readable code --- src/stlink-common.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 917a1e0e3..51efae43f 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1966,7 +1966,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ int err; - unsigned int num_empty = 0, index; + unsigned int num_empty, index; unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; @@ -1975,11 +1975,11 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { ELOG("map_file() == -1\n"); return -1; } - for(index = mf.len - 1; num_empty < mf.len; index --) { - if (mf.base[index] != erased_pattern) { + index = mf.len; + for(num_empty = 0; num_empty != mf.len; ++num_empty) { + if (mf.base[--index] != erased_pattern) { break; } - num_empty ++; } /* Round down to words */ num_empty -= (num_empty & 3); From 61b41b03aaafc9ca11c076127ce2c19b323ba914 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 11 Mar 2016 22:13:09 +0100 Subject: [PATCH 0365/1435] Add st-info to CMakeLists.txt --- CMakeLists.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 2358898e3..6f5be17ff 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -38,7 +38,10 @@ add_executable(st-util gdbserver/gdb-remote.c gdbserver/gdb-server.h) target_link_libraries(st-util stlink) -install(TARGETS stlink st-flash st-util +add_executable(st-info src/st-info.c) +target_link_libraries(st-info stlink) + +install(TARGETS stlink st-flash st-util st-info RUNTIME DESTINATION bin ARCHIVE DESTINATION lib) From bd272132992cf8308ad898aa2da9002a7344837d Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Thu, 10 Mar 2016 16:15:57 +0100 Subject: [PATCH 0366/1435] read_debug32: Use a pointer instead of returning the value This rework is done in order to prepare for propagating errors returned by libusb. Signed-off-by: Maxime Coquelin --- gdbserver/gdb-server.c | 24 +++--- src/stlink-common.c | 176 ++++++++++++++++++++++++----------------- src/stlink-common.h | 4 +- src/stlink-sg.c | 5 +- src/stlink-usb.c | 7 +- 5 files changed, 128 insertions(+), 88 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index ef289f282..eca6597b4 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -488,11 +488,13 @@ struct code_hw_watchpoint { struct code_hw_watchpoint data_watches[DATA_WATCH_NUM]; static void init_data_watchpoints(stlink_t *sl) { + uint32_t data; DLOG("init watchpoints\n"); + stlink_read_debug32(sl, 0xE000EDFC, &data); + data |= 1<<24; // set trcena in debug command to turn on dwt unit - stlink_write_debug32(sl, 0xE000EDFC, - stlink_read_debug32(sl, 0xE000EDFC) | (1<<24)); + stlink_write_debug32(sl, 0xE000EDFC, data); // make sure all watchpoints are cleared for(int i = 0; i < DATA_WATCH_NUM; i++) { @@ -504,7 +506,7 @@ static void init_data_watchpoints(stlink_t *sl) { static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len) { int i = 0; - uint32_t mask; + uint32_t mask, dummy; // computer mask // find a free watchpoint @@ -537,7 +539,7 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stlink_write_debug32(sl, 0xE0001028 + i * 16, wf); // just to make sure the matched bit is clear ! - stlink_read_debug32(sl, 0xE0001028 + i * 16); + stlink_read_debug32(sl, 0xE0001028 + i * 16, &dummy); return 0; } } @@ -581,9 +583,10 @@ struct code_hw_breakpoint { struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; static void init_code_breakpoints(stlink_t *sl) { + unsigned int val; memset(sl->q_buf, 0, 4); stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/); - unsigned int val = stlink_read_debug32(sl, CM3_REG_FP_CTRL); + stlink_read_debug32(sl, CM3_REG_FP_CTRL, &val); code_break_num = ((val >> 4) & 0xf); code_lit_num = ((val >> 8) & 0xf); @@ -821,7 +824,8 @@ static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) { unsigned int ccsidr; unsigned int log2_nsets; - ccsidr = stlink_read_debug32(sl, CCSIDR); + + stlink_read_debug32(sl, CCSIDR, &ccsidr); desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1; desc->nways = ((ccsidr >> 3) & 0x1ff) + 1; desc->log2_nways = ceil_log2 (desc->nways); @@ -841,9 +845,9 @@ static void init_cache (stlink_t *sl) { if(sl->chip_id!=STM32_CHIPID_F7) return; - clidr = stlink_read_debug32(sl, CLIDR); - ccr = stlink_read_debug32(sl, CCR); - ctr = stlink_read_debug32(sl, CTR); + stlink_read_debug32(sl, CLIDR, &clidr); + stlink_read_debug32(sl, CCR, &ccr); + stlink_read_debug32(sl, CTR, &ctr); cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f); cache_desc.iminline = 4 << (ctr & 0x0f); cache_desc.louu = (clidr >> 27) & 7; @@ -925,7 +929,7 @@ static void cache_sync(stlink_t *sl) return; cache_modified = 0; - ccr = stlink_read_debug32(sl, CCR); + stlink_read_debug32(sl, CCR, &ccr); if (ccr & (CCR_IC | CCR_DC)) cache_flush(sl, ccr); } diff --git a/src/stlink-common.c b/src/stlink-common.c index 51efae43f..a20f3fa4f 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -165,15 +165,21 @@ uint32_t read_uint32(const unsigned char *c, const int pt) { } static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { - return stlink_read_debug32(sl, FLASH_WRPR) & 0xff; + uint32_t rdp; + stlink_read_debug32(sl, FLASH_WRPR, &rdp); + return rdp & 0xff; } static inline uint32_t read_flash_wrpr(stlink_t *sl) { - return stlink_read_debug32(sl, FLASH_WRPR); + uint32_t wrpr; + stlink_read_debug32(sl, FLASH_WRPR, &wrpr); + return wrpr; } static inline uint32_t read_flash_obr(stlink_t *sl) { - return stlink_read_debug32(sl, FLASH_OBR); + uint32_t obr; + stlink_read_debug32(sl, FLASH_OBR, &obr); + return obr; } static inline uint32_t read_flash_cr(stlink_t *sl) { @@ -181,11 +187,11 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) - res = stlink_read_debug32(sl, FLASH_F4_CR); + stlink_read_debug32(sl, FLASH_F4_CR, &res); else if (sl->chip_id == STM32_CHIPID_L4) - res = stlink_read_debug32(sl, STM32L4_FLASH_CR); + stlink_read_debug32(sl, STM32L4_FLASH_CR, &res); else - res = stlink_read_debug32(sl, FLASH_CR); + stlink_read_debug32(sl, FLASH_CR, &res); #if DEBUG_FLASH fprintf(stdout, "CR:0x%x\n", res); #endif @@ -297,51 +303,63 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { } static void set_flash_cr_mer(stlink_t *sl) { + uint32_t val; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) - stlink_write_debug32(sl, FLASH_F4_CR, - stlink_read_debug32(sl, FLASH_F4_CR) | (1 << FLASH_CR_MER)); - else if (sl->chip_id == STM32_CHIPID_L4) { - uint32_t x = stlink_read_debug32(sl, STM32L4_FLASH_CR); - x &=~ STM32L4_FLASH_CR_OPBITS; - x |= (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER2); - stlink_write_debug32(sl, STM32L4_FLASH_CR, x); - } else - stlink_write_debug32(sl, FLASH_CR, - stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_MER)); + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { + stlink_read_debug32(sl, FLASH_F4_CR, &val); + val |= 1 << FLASH_CR_MER; + stlink_write_debug32(sl, FLASH_F4_CR, val); + } else if (sl->chip_id == STM32_CHIPID_L4) { + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val &=~ STM32L4_FLASH_CR_OPBITS; + val |= (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER2); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + } else { + stlink_read_debug32(sl, FLASH_CR, &val); + val |= 1 << FLASH_CR_MER; + stlink_write_debug32(sl, FLASH_CR, val); + } } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { + uint32_t val; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) - stlink_write_debug32(sl, FLASH_F4_CR, - stlink_read_debug32(sl, FLASH_F4_CR) & ~(1 << FLASH_CR_MER)); - else - stlink_write_debug32(sl, FLASH_CR, - stlink_read_debug32(sl, FLASH_CR) & ~(1 << FLASH_CR_MER)); + (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { + stlink_read_debug32(sl, FLASH_F4_CR, &val); + val &= ~(1 << FLASH_CR_MER); + stlink_write_debug32(sl, FLASH_F4_CR, val); + } else { + stlink_read_debug32(sl, FLASH_CR, &val); + val &= ~(1 << FLASH_CR_MER); + stlink_write_debug32(sl, FLASH_CR, val); + } } static void set_flash_cr_strt(stlink_t *sl) { + uint32_t val; if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { - uint32_t x = read_flash_cr(sl); - x |= (1 << FLASH_F4_CR_STRT); - stlink_write_debug32(sl, FLASH_F4_CR, x); + val = read_flash_cr(sl); + val |= (1 << FLASH_F4_CR_STRT); + stlink_write_debug32(sl, FLASH_F4_CR, val); } else if (sl->chip_id == STM32_CHIPID_L4) { - uint32_t x = read_flash_cr(sl); - x |= (1lu << STM32L4_FLASH_CR_STRT); - stlink_write_debug32(sl, STM32L4_FLASH_CR, x); + val = read_flash_cr(sl); + val |= (1lu << STM32L4_FLASH_CR_STRT); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); } else { - stlink_write_debug32(sl, FLASH_CR, - stlink_read_debug32(sl, FLASH_CR) | (1 << FLASH_CR_STRT) ); + stlink_read_debug32(sl, FLASH_CR, &val); + val |= 1 << FLASH_CR_STRT; + stlink_write_debug32(sl, FLASH_CR, val); } } static inline uint32_t read_flash_acr(stlink_t *sl) { - return stlink_read_debug32(sl, FLASH_ACR); + uint32_t acr; + stlink_read_debug32(sl, FLASH_ACR, &acr); + return acr; } static inline uint32_t read_flash_sr(stlink_t *sl) { @@ -349,11 +367,11 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) - res = stlink_read_debug32(sl, FLASH_F4_SR); + stlink_read_debug32(sl, FLASH_F4_SR, &res); else if (sl->chip_id == STM32_CHIPID_L4) - res = stlink_read_debug32(sl, STM32L4_FLASH_SR); + stlink_read_debug32(sl, STM32L4_FLASH_SR, &res); else - res = stlink_read_debug32(sl, FLASH_SR); + stlink_read_debug32(sl, FLASH_SR, &res); //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf); return res; } @@ -486,8 +504,10 @@ uint32_t stlink_core_id(stlink_t *sl) { } uint32_t stlink_chip_id(stlink_t *sl) { - uint32_t chip_id = stlink_read_debug32(sl, 0xE0042000); - if (chip_id == 0) chip_id = stlink_read_debug32(sl, 0x40015800); //Try Corex M0 DBGMCU_IDCODE register address + uint32_t chip_id; + stlink_read_debug32(sl, 0xE0042000, &chip_id); + if (chip_id == 0) + stlink_read_debug32(sl, 0x40015800, &chip_id); //Try Corex M0 DBGMCU_IDCODE register address return chip_id; } @@ -497,7 +517,8 @@ uint32_t stlink_chip_id(stlink_t *sl) { * @param cpuid pointer to the result object */ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { - uint32_t raw = stlink_read_debug32(sl, CM3_REG_CPUID); + uint32_t raw; + stlink_read_debug32(sl, CM3_REG_CPUID, &raw); cpuid->implementer_id = (raw >> 24) & 0x7f; cpuid->variant = (raw >> 20) & 0xf; cpuid->part = (raw >> 4) & 0xfff; @@ -520,7 +541,8 @@ int stlink_load_device_params(stlink_t *sl) { sl->chip_id = chip_id & 0xfff; /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/ if (sl->chip_id == 0x411) { - uint32_t cpuid = stlink_read_debug32(sl, 0xE000ED00); + uint32_t cpuid; + stlink_read_debug32(sl, 0xE000ED00, &cpuid); if ((cpuid & 0xfff0) == 0xc240) sl->chip_id = 0x413; } @@ -539,7 +561,7 @@ int stlink_load_device_params(stlink_t *sl) { // These are fixed... sl->flash_base = STM32_FLASH_BASE; sl->sram_base = STM32_SRAM_BASE; - flash_size = stlink_read_debug32(sl,(params->flash_size_reg) & ~3); + stlink_read_debug32(sl,(params->flash_size_reg) & ~3, &flash_size); if (params->flash_size_reg & 2) flash_size = flash_size >>16; flash_size = flash_size & 0xffff; @@ -657,10 +679,10 @@ int stlink_target_voltage(stlink_t *sl) { return voltage; } -uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr) { - uint32_t data = sl->backend->read_debug32(sl, addr); +void stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { + sl->backend->read_debug32(sl, addr, data); DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr); - return data; + return; } void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { @@ -958,6 +980,7 @@ int stlink_fwrite_sram size_t off; size_t len; mapped_file_t mf = MAPPED_FILE_INITIALIZER; + uint32_t val; if (map_file(&mf, path) == -1) { @@ -1016,9 +1039,11 @@ int stlink_fwrite_sram /* success */ error = 0; /* set stack*/ - stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13); + stlink_read_debug32(sl, addr, &val); + stlink_write_reg(sl, val, 13); /* Set PC to the reset routine*/ - stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15); + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); stlink_run(sl); on_error: @@ -1115,7 +1140,8 @@ uint32_t calculate_F7_sectornum(uint32_t flashaddr){ // Returns BKER:PNB for the given page address uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { uint32_t bker = 0; - uint32_t flashopt = stlink_read_debug32(sl, STM32L4_FLASH_OPTR); + uint32_t flashopt; + stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); flashaddr -= STM32_FLASH_BASE; if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) { uint32_t banksize = sl->flash_size / 2; @@ -1217,14 +1243,14 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } /* check if the locks are set */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); if((val & (1<<0))||(val & (1<<1))) { /* disable pecr protection */ stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef); stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405); /* check pecr.pelock is cleared */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); if (val & (1 << 0)) { WLOG("pecr.pelock not clear (%#x)\n", val); return -1; @@ -1235,7 +1261,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516); /* check pecr.prglock is cleared */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); if (val & (1 << 1)) { WLOG("pecr.prglock not clear (%#x)\n", val); return -1; @@ -1253,8 +1279,9 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) * TEXANE: ok, if experience says so and it works for you, we comment * it. If someone has a problem, please drop an email. */ - while ((stlink_read_debug32(sl, STM32L_FLASH_SR) & (1 << 0)) != 0) - ; + do { + stlink_read_debug32(sl, STM32L_FLASH_SR, &val) + } while((val & (1 << 0)) != 0); #endif /* fix_to_be_confirmed */ @@ -1265,12 +1292,13 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) page erase command, even though PM0062 recommends to wait before it. Test shows that a few iterations is performed in the following loop before busy bit is cleared.*/ - while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) - ; + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); /* reset lock bits */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF) - | (1 << 0) | (1 << 1) | (1 << 2); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID @@ -1687,18 +1715,20 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin return -1; } /* Unlock already done */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << FLASH_L1_FPRG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); val |= (1 << FLASH_L1_PROG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) {} + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); for (count = 0; count < num_half_pages; count ++) { if (run_flash_loader(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) { WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * pagesize); - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG)); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); return -1; @@ -1710,13 +1740,14 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); fflush(stdout); } - while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) { - } + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); } - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~(1 << FLASH_L1_PROG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~(1 << FLASH_L1_FPRG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); @@ -1858,7 +1889,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405); /* check pecr.pelock is cleared */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); if (val & (1 << 0)) { fprintf(stderr, "pecr.pelock not clear\n"); return -1; @@ -1869,7 +1900,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516); /* check pecr.prglock is cleared */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); if (val & (1 << 1)) { fprintf(stderr, "pecr.prglock not clear\n"); return -1; @@ -1900,16 +1931,17 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t stlink_write_debug32(sl, addr + off, data); /* wait for sr.busy to be cleared */ - while ((stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF) & (1 << 0)) != 0) - ; + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); /* todo: check redo write operation */ } fprintf(stdout, "\n"); /* reset lock bits */ - val = stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF) - | (1 << 0) | (1 << 1) | (1 << 2); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); } else if (sl->core_id == STM32VL_CORE_ID || sl->core_id == STM32F0_CORE_ID || @@ -1966,7 +1998,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ int err; - unsigned int num_empty, index; + unsigned int num_empty, index, val; unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; @@ -1988,9 +2020,11 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { } err = stlink_write_flash(sl, addr, mf.base, num_empty == mf.len? mf.len : mf.len - num_empty, num_empty == mf.len); /* set stack*/ - stlink_write_reg(sl, stlink_read_debug32(sl, addr ),13); + stlink_read_debug32(sl, addr, &val); + stlink_write_reg(sl, val, 13); /* Set PC to the reset routine*/ - stlink_write_reg(sl, stlink_read_debug32(sl, addr + 4),15); + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); stlink_run(sl); unmap_file(&mf); return err; diff --git a/src/stlink-common.h b/src/stlink-common.h index 2751ac839..b3f86768c 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -566,7 +566,7 @@ extern "C" { void (*run) (stlink_t * stl); void (*status) (stlink_t * stl); void (*version) (stlink_t *sl); - uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr); + void (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); @@ -636,7 +636,7 @@ extern "C" { void stlink_run(stlink_t *sl); void stlink_status(stlink_t *sl); void stlink_version(stlink_t *sl); - uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr); + void stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); diff --git a/src/stlink-sg.c b/src/stlink-sg.c index b16a2edfc..3fdc0bde5 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -811,7 +811,7 @@ void _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { // Read one DWORD data from memory -uint32_t _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr) { +void _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_JTAG_READDEBUG_32BIT; @@ -820,7 +820,8 @@ uint32_t _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr) { sl->q_len = 8; stlink_q(sl); - return read_uint32(sl->q_buf, 4); + *data = read_uint32(sl->q_buf, 4); + return; } // Exit the jtag or swd mode and enter the mass mode. diff --git a/src/stlink-usb.c b/src/stlink-usb.c index c4c693d2b..927e44e96 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -138,7 +138,7 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { return voltage; } -uint32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr) { +void _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const rdata = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -152,9 +152,10 @@ uint32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr) { size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return 0; + return; } - return read_uint32(rdata, 4); + *data = read_uint32(rdata, 4); + return; } void _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { From 5fcad7d2bf22c94b711f7c4423646a2ff5bafba8 Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Thu, 10 Mar 2016 16:26:48 +0100 Subject: [PATCH 0367/1435] stlink_core_id: No need to return core_id value This rework is done in order to prepare for propagating errors returned by libusb. Signed-off-by: Maxime Coquelin --- src/stlink-common.c | 6 +++--- src/stlink-common.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index a20f3fa4f..683959362 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -494,13 +494,13 @@ void stlink_exit_dfu_mode(stlink_t *sl) { sl->backend->exit_dfu_mode(sl); } -uint32_t stlink_core_id(stlink_t *sl) { +void stlink_core_id(stlink_t *sl) { DLOG("*** stlink_core_id ***\n"); sl->backend->core_id(sl); if (sl->verbose > 2) stlink_print_data(sl); DLOG("core_id = 0x%08x\n", sl->core_id); - return sl->core_id; + return; } uint32_t stlink_chip_id(stlink_t *sl) { @@ -534,7 +534,7 @@ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { int stlink_load_device_params(stlink_t *sl) { ILOG("Loading device parameters....\n"); const chip_params_t *params = NULL; - sl->core_id = stlink_core_id(sl); + stlink_core_id(sl); uint32_t chip_id = stlink_chip_id(sl); uint32_t flash_size; diff --git a/src/stlink-common.h b/src/stlink-common.h index b3f86768c..fbbb2b42e 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -630,7 +630,7 @@ extern "C" { void stlink_exit_debug_mode(stlink_t *sl); void stlink_exit_dfu_mode(stlink_t *sl); void stlink_close(stlink_t *sl); - uint32_t stlink_core_id(stlink_t *sl); + void stlink_core_id(stlink_t *sl); void stlink_reset(stlink_t *sl); void stlink_jtag_reset(stlink_t *sl, int value); void stlink_run(stlink_t *sl); From 89c3b1462b8c4b96e2071a87883aed5e030bbef9 Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Thu, 10 Mar 2016 16:39:26 +0100 Subject: [PATCH 0368/1435] stlink_target_voltage: Check for libusb error _stlink_usb_target_voltage already returns an error value. If value return is positive, this is a voltage, if negative this is an error. Check the return on callers side to inform there is an error in reading the voltage, instead of notifying of a too low voltage. Signed-off-by: Maxime Coquelin --- src/stlink-common.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 683959362..204491cf6 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1609,7 +1609,10 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)){ int voltage = stlink_target_voltage(sl); - if (voltage > 2700) { + if (voltage == -1) { + printf("Failed to read Target voltage\n"); + return voltage; + } else if (voltage > 2700) { loader_code = loader_code_stm32f4; loader_size = sizeof(loader_code_stm32f4); } else { @@ -1829,7 +1832,10 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t if (sl->chip_id != STM32_CHIPID_L4) { /* set parallelisim to 32 bit*/ int voltage = stlink_target_voltage(sl); - if (voltage > 2700) { + if (voltage == -1) { + printf("Failed to read Target voltage\n"); + return voltage; + } else if (voltage > 2700) { printf("enabling 32-bit flash writes\n"); write_flash_cr_psiz(sl, 2); } else { @@ -1839,7 +1845,10 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } else { /* L4 does not have a byte-write mode */ int voltage = stlink_target_voltage(sl); - if (voltage < 1710) { + if (voltage == -1) { + printf("Failed to read Target voltage\n"); + return voltage; + } else if (voltage < 1710) { printf("Target voltage (%d mV) too low for flash writes!\n", voltage); return -1; } From 64a48c704ff802b3a08cbdf0dd729f4a7a39ea67 Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Fri, 11 Mar 2016 11:16:41 +0100 Subject: [PATCH 0369/1435] Make the backends propagate errors As the libusb returns errors, make the backends propagates them so that callers can decide to continue or stop task execution. Signed-off-by: Maxime Coquelin --- src/stlink-common.h | 46 ++++++------ src/stlink-sg.c | 155 ++++++++++++++++++++++++++------------ src/stlink-usb.c | 178 ++++++++++++++++++++++++++++++-------------- 3 files changed, 255 insertions(+), 124 deletions(-) diff --git a/src/stlink-common.h b/src/stlink-common.h index fbbb2b42e..467b9b90a 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -556,30 +556,30 @@ extern "C" { typedef struct _stlink_backend { void (*close) (stlink_t * sl); - void (*exit_debug_mode) (stlink_t * sl); - void (*enter_swd_mode) (stlink_t * sl); - void (*enter_jtag_mode) (stlink_t * stl); - void (*exit_dfu_mode) (stlink_t * stl); - void (*core_id) (stlink_t * stl); - void (*reset) (stlink_t * stl); - void (*jtag_reset) (stlink_t * stl, int value); - void (*run) (stlink_t * stl); - void (*status) (stlink_t * stl); - void (*version) (stlink_t *sl); - void (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); - void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); - void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); - void (*read_all_regs) (stlink_t *sl, reg * regp); - void (*read_reg) (stlink_t *sl, int r_idx, reg * regp); - void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp); - void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp); - void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp); - void (*write_reg) (stlink_t *sl, uint32_t reg, int idx); - void (*step) (stlink_t * stl); + int (*exit_debug_mode) (stlink_t * sl); + int (*enter_swd_mode) (stlink_t * sl); + int (*enter_jtag_mode) (stlink_t * stl); + int (*exit_dfu_mode) (stlink_t * stl); + int (*core_id) (stlink_t * stl); + int (*reset) (stlink_t * stl); + int (*jtag_reset) (stlink_t * stl, int value); + int (*run) (stlink_t * stl); + int (*status) (stlink_t * stl); + int (*version) (stlink_t *sl); + int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); + int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); + int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); + int (*read_all_regs) (stlink_t *sl, reg * regp); + int (*read_reg) (stlink_t *sl, int r_idx, reg * regp); + int (*read_all_unsupported_regs) (stlink_t *sl, reg *regp); + int (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp); + int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp); + int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); + int (*step) (stlink_t * stl); int (*current_mode) (stlink_t * stl); - void (*force_debug) (stlink_t *sl); + int (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); } stlink_backend_t; diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 3fdc0bde5..03df7d854 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -403,13 +403,13 @@ void stlink_stat(stlink_t *stl, char *txt) { } -void _stlink_sg_version(stlink_t *stl) { +int _stlink_sg_version(stlink_t *stl) { struct stlink_libsg *sl = stl->backend_data; clear_cdb(sl); sl->cdb_cmd_blk[0] = STLINK_GET_VERSION; stl->q_len = 6; sl->q_addr = 0; - stlink_q(stl); + return stlink_q(stl); } // Get stlink mode: @@ -422,44 +422,46 @@ int _stlink_sg_current_mode(stlink_t *stl) { sl->cdb_cmd_blk[0] = STLINK_GET_CURRENT_MODE; stl->q_len = 2; sl->q_addr = 0; - stlink_q(stl); + if (stlink_q(stl)) + return -1; + return stl->q_buf[0]; } // Exit the mass mode and enter the swd debug mode. -void _stlink_sg_enter_swd_mode(stlink_t *sl) { +int _stlink_sg_enter_swd_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_ENTER; sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_SWD; sl->q_len = 0; // >0 -> aboard - stlink_q(sl); + return stlink_q(sl); } // Exit the mass mode and enter the jtag debug mode. // (jtag is disabled in the discovery's stlink firmware) -void _stlink_sg_enter_jtag_mode(stlink_t *sl) { +int _stlink_sg_enter_jtag_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_enter_jtag_mode ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_ENTER; sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_JTAG; sl->q_len = 0; - stlink_q(sl); + return stlink_q(sl); } // XXX kernel driver performs reset, the device temporally disappears // Suspect this is no longer the case when we have ignore on? RECHECK -void _stlink_sg_exit_dfu_mode(stlink_t *sl) { +int _stlink_sg_exit_dfu_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_exit_dfu_mode ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[0] = STLINK_DFU_COMMAND; sg->cdb_cmd_blk[1] = STLINK_DFU_EXIT; sl->q_len = 0; // ?? - stlink_q(sl); + return stlink_q(sl); /* [135121.844564] sd 19:0:0:0: [sdb] Unhandled error code [135121.844569] sd 19:0:0:0: [sdb] Result: hostbyte=DID_ERROR driverbyte=DRIVER_OK @@ -505,74 +507,91 @@ void _stlink_sg_exit_dfu_mode(stlink_t *sl) { */ } -void _stlink_sg_core_id(stlink_t *sl) { +int _stlink_sg_core_id(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; + int ret; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_READCOREID; sl->q_len = 4; sg->q_addr = 0; - stlink_q(sl); + ret = stlink_q(sl); + if (ret) + return ret; + sl->core_id = read_uint32(sl->q_buf, 0); + return 0; } // Arm-core reset -> halted state. -void _stlink_sg_reset(stlink_t *sl) { +int _stlink_sg_reset(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_RESETSYS; sl->q_len = 2; sg->q_addr = 0; - stlink_q(sl); + if (stlink_q(sl)) + return -1; + stlink_stat(sl, "core reset"); + return 0; } // Arm-core reset -> halted state. -void _stlink_sg_jtag_reset(stlink_t *sl, int value) { +int _stlink_sg_jtag_reset(stlink_t *sl, int value) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_JTAG_DRIVE_NRST; sg->cdb_cmd_blk[2] = (value)?0:1; sl->q_len = 3; sg->q_addr = 2; - stlink_q(sl); + if (stlink_q(sl)) + return -1; + stlink_stat(sl, "core reset"); + + return 0; } // Arm-core status: halted or running. -void _stlink_sg_status(stlink_t *sl) { +int _stlink_sg_status(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_GETSTATUS; sl->q_len = 2; sg->q_addr = 0; - stlink_q(sl); + return stlink_q(sl); } // Force the core into the debug mode -> halted state. -void _stlink_sg_force_debug(stlink_t *sl) { +int _stlink_sg_force_debug(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_FORCEDEBUG; sl->q_len = 2; sg->q_addr = 0; - stlink_q(sl); + if (stlink_q(sl)) + return -1; + stlink_stat(sl, "force debug"); + return 0; } // Read all arm-core registers. -void _stlink_sg_read_all_regs(stlink_t *sl, reg *regp) { +int _stlink_sg_read_all_regs(stlink_t *sl, reg *regp) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_READALLREGS; sl->q_len = 84; sg->q_addr = 0; - stlink_q(sl); + if (stlink_q(sl)) + return -1; + stlink_print_data(sl); // TODO - most of this should be re-extracted up.... @@ -590,27 +609,31 @@ void _stlink_sg_read_all_regs(stlink_t *sl, reg *regp) { regp->rw = read_uint32(sl->q_buf, 76); regp->rw2 = read_uint32(sl->q_buf, 80); if (sl->verbose < 2) - return; + return 0; DLOG("xpsr = 0x%08x\n", regp->xpsr); DLOG("main_sp = 0x%08x\n", regp->main_sp); DLOG("process_sp = 0x%08x\n", regp->process_sp); DLOG("rw = 0x%08x\n", regp->rw); DLOG("rw2 = 0x%08x\n", regp->rw2); + + return 0; } // Read an arm-core register, the index must be in the range 0..20. // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 -void _stlink_sg_read_reg(stlink_t *sl, int r_idx, reg *regp) { +int _stlink_sg_read_reg(stlink_t *sl, int r_idx, reg *regp) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_READREG; sg->cdb_cmd_blk[2] = r_idx; sl->q_len = 4; sg->q_addr = 0; - stlink_q(sl); + if (stlink_q(sl)) + return -1; + // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // 0-3 | 4-7 | ... | 60-63 | 64-67 | 68-71 | 72-75 | 76-79 | 80-83 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 @@ -638,13 +661,15 @@ void _stlink_sg_read_reg(stlink_t *sl, int r_idx, reg *regp) { default: regp->r[r_idx] = r; } + + return 0; } // Write an arm-core register. Index: // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 -void _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int idx) { +int _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int idx) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_WRITEREG; @@ -654,8 +679,11 @@ void _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int idx) { write_uint32(sg->cdb_cmd_blk + 3, reg); sl->q_len = 2; sg->q_addr = 0; - stlink_q(sl); + if (stlink_q(sl)) + return -1; + stlink_stat(sl, "write reg"); + return 0; } // Write a register of the debug module of the core. @@ -679,26 +707,33 @@ void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { // Force the core exit the debug mode. -void _stlink_sg_run(stlink_t *sl) { +int _stlink_sg_run(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_RUNCORE; sl->q_len = 2; sg->q_addr = 0; - stlink_q(sl); + if (stlink_q(sl)) + return -1; + stlink_stat(sl, "run core"); + + return 0; } // Step the arm-core. -void _stlink_sg_step(stlink_t *sl) { +int _stlink_sg_step(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_STEPCORE; sl->q_len = 2; sg->q_addr = 0; - stlink_q(sl); + if (stlink_q(sl)) + return -1; + stlink_stat(sl, "step core"); + return 0; } // TODO test @@ -738,7 +773,7 @@ void stlink_clr_hw_bp(stlink_t *sl, int fp_nr) { // Read a "len" bytes to the sl->q_buf from the memory, max 6kB (6144 bytes) -void _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_READMEM_32BIT; @@ -754,14 +789,19 @@ void _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { // (broken residue issue) sl->q_len = len; sg->q_addr = addr; - stlink_q(sl); + if (stlink_q(sl)) + return -1; + stlink_print_data(sl); + return 0; } // Write a "len" bytes from the sl->q_buf to the memory, max 64 Bytes. -void _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { +int _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; + int ret; + clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_WRITEMEM_8BIT; // 2-5: addr @@ -770,16 +810,27 @@ void _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint16(sg->cdb_cmd_blk + 6, len); // this sends the command... - send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); + ret = send_usb_mass_storage_command(sg->usb_handle, + sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); + if (ret == -1) + return ret; + // This sends the data... - send_usb_data_only(sg->usb_handle, sg->ep_req, sg->ep_rep, sl->q_buf, len); + ret = send_usb_data_only(sg->usb_handle, + sg->ep_req, sg->ep_rep, sl->q_buf, len); + if (ret == -1) + return ret; + stlink_print_data(sl); + return 0; } // Write a "len" bytes from the sl->q_buf to the memory, max Q_BUF_LEN bytes. -void _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; + int ret; + clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_WRITEMEM_32BIT; // 2-5: addr @@ -788,16 +839,24 @@ void _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint16(sg->cdb_cmd_blk + 6, len); // this sends the command... - send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); + ret = send_usb_mass_storage_command(sg->usb_handle, + sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); + if (ret == -1) + return ret; + // This sends the data... - send_usb_data_only(sg->usb_handle, sg->ep_req, sg->ep_rep, sl->q_buf, len); + ret = send_usb_data_only(sg->usb_handle, + sg->ep_req, sg->ep_rep, sl->q_buf, len); + if (ret == -1) + return ret; stlink_print_data(sl); + return 0; } // Write one DWORD data to memory -void _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { +int _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_JTAG_WRITEDEBUG_32BIT; @@ -805,36 +864,38 @@ void _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { write_uint32(sg->cdb_cmd_blk + 2, addr); write_uint32(sg->cdb_cmd_blk + 6, data); sl->q_len = 2; - stlink_q(sl); - + return stlink_q(sl); } // Read one DWORD data from memory -void _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { +int _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_JTAG_READDEBUG_32BIT; // 2-5: addr write_uint32(sg->cdb_cmd_blk + 2, addr); sl->q_len = 8; - stlink_q(sl); + if (stlink_q(sl)) + return -1; *data = read_uint32(sl->q_buf, 4); - return; + return 0; } // Exit the jtag or swd mode and enter the mass mode. -void _stlink_sg_exit_debug_mode(stlink_t *stl) { - +int _stlink_sg_exit_debug_mode(stlink_t *stl) +{ if (stl) { struct stlink_libsg* sl = stl->backend_data; clear_cdb(sl); sl->cdb_cmd_blk[1] = STLINK_DEBUG_EXIT; stl->q_len = 0; // >0 -> aboard - stlink_q(stl); + return stlink_q(stl); } + + return 0; } diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 927e44e96..8e52c6801 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -93,7 +93,7 @@ static int fill_command return i; } -void _stlink_usb_version(stlink_t *sl) { +int _stlink_usb_version(stlink_t *sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -106,8 +106,10 @@ void _stlink_usb_version(stlink_t *sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return size; } + + return 0; } int32_t _stlink_usb_target_voltage(stlink_t *sl) { @@ -138,7 +140,7 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { return voltage; } -void _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { +int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const rdata = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -152,13 +154,13 @@ void _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return size; } *data = read_uint32(rdata, 4); - return; + return 0; } -void _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { +int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const rdata = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -173,37 +175,54 @@ void _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return size; } + + return 0; } -void _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; + int i, ret; - int i = fill_command(sl, SG_DXFER_TO_DEV, len); + i = fill_command(sl, SG_DXFER_TO_DEV, len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_WRITEMEM_32BIT; write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); - send_only(slu, 0, cmd, slu->cmd_len); + ret = send_only(slu, 0, cmd, slu->cmd_len); + if (ret == -1) + return ret; + + ret = send_only(slu, 1, data, len); + if (ret == -1) + return ret; - send_only(slu, 1, data, len); + return 0; } -void _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { +int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; + int i, ret; - int i = fill_command(sl, SG_DXFER_TO_DEV, 0); + i = fill_command(sl, SG_DXFER_TO_DEV, 0); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_WRITEMEM_8BIT; write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); - send_only(slu, 0, cmd, slu->cmd_len); - send_only(slu, 1, data, len); + ret = send_only(slu, 0, cmd, slu->cmd_len); + if (ret == -1) + return ret; + + ret = send_only(slu, 1, data, len); + if (ret == -1) + return ret; + + return 0; } @@ -224,7 +243,7 @@ int _stlink_usb_current_mode(stlink_t * sl) { return sl->q_buf[0]; } -void _stlink_usb_core_id(stlink_t * sl) { +int _stlink_usb_core_id(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; unsigned char* const data = sl->q_buf; @@ -238,13 +257,14 @@ void _stlink_usb_core_id(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return -1; } sl->core_id = read_uint32(data, 0); + return 0; } -void _stlink_usb_status(stlink_t * sl) { +int _stlink_usb_status(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -258,12 +278,14 @@ void _stlink_usb_status(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return size; } sl->q_len = (size_t) size; + + return 0; } -void _stlink_usb_force_debug(stlink_t *sl) { +int _stlink_usb_force_debug(stlink_t *sl) { struct stlink_libusb *slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -276,11 +298,13 @@ void _stlink_usb_force_debug(stlink_t *sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return size; } + + return 0; } -void _stlink_usb_enter_swd_mode(stlink_t * sl) { +int _stlink_usb_enter_swd_mode(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; ssize_t size; @@ -294,11 +318,13 @@ void _stlink_usb_enter_swd_mode(stlink_t * sl) { size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return size; } + + return 0; } -void _stlink_usb_exit_dfu_mode(stlink_t* sl) { +int _stlink_usb_exit_dfu_mode(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; ssize_t size; @@ -310,15 +336,17 @@ void _stlink_usb_exit_dfu_mode(stlink_t* sl) { size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return size; } + + return 0; } /** * TODO - not convinced this does anything... * @param sl */ -void _stlink_usb_reset(stlink_t * sl) { +int _stlink_usb_reset(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -332,12 +360,14 @@ void _stlink_usb_reset(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return size; } + + return 0; } -void _stlink_usb_jtag_reset(stlink_t * sl, int value) { +int _stlink_usb_jtag_reset(stlink_t * sl, int value) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -352,12 +382,14 @@ void _stlink_usb_jtag_reset(stlink_t * sl, int value) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return size; } + + return 0; } -void _stlink_usb_step(stlink_t* sl) { +int _stlink_usb_step(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -371,15 +403,17 @@ void _stlink_usb_step(stlink_t* sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return size; } + + return 0; } /** * This seems to do a good job of restarting things from the beginning? * @param sl */ -void _stlink_usb_run(stlink_t* sl) { +int _stlink_usb_run(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -393,11 +427,13 @@ void _stlink_usb_run(stlink_t* sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return size; } + + return 0; } -void _stlink_usb_exit_debug_mode(stlink_t *sl) { +int _stlink_usb_exit_debug_mode(stlink_t *sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; ssize_t size; @@ -409,11 +445,13 @@ void _stlink_usb_exit_debug_mode(stlink_t *sl) { size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { printf("[!] send_only\n"); - return; + return size; } + + return 0; } -void _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -428,15 +466,16 @@ void _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, len); if (size == -1) { printf("[!] send_recv\n"); - return; + return size; } sl->q_len = (size_t) size; stlink_print_data(sl); + return 0; } -void _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) { +int _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; unsigned char* const data = sl->q_buf; @@ -449,7 +488,7 @@ void _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return size; } sl->q_len = (size_t) size; stlink_print_data(sl); @@ -461,16 +500,18 @@ void _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) { regp->rw = read_uint32(sl->q_buf, 76); regp->rw2 = read_uint32(sl->q_buf, 80); if (sl->verbose < 2) - return; + return 0; DLOG("xpsr = 0x%08x\n", read_uint32(sl->q_buf, 64)); DLOG("main_sp = 0x%08x\n", read_uint32(sl->q_buf, 68)); DLOG("process_sp = 0x%08x\n", read_uint32(sl->q_buf, 72)); DLOG("rw = 0x%08x\n", read_uint32(sl->q_buf, 76)); DLOG("rw2 = 0x%08x\n", read_uint32(sl->q_buf, 80)); + + return 0; } -void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { +int _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -485,7 +526,7 @@ void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return size; } sl->q_len = (size_t) size; stlink_print_data(sl); @@ -511,19 +552,27 @@ void _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { default: regp->r[r_idx] = r; } + + return 0; } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ -void _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { +int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { uint32_t r; + int ret; sl->q_buf[0] = (unsigned char) r_idx; for (int i = 1; i < 4; i++) { sl->q_buf[i] = 0; } - _stlink_usb_write_mem32(sl, DCRSR, 4); + ret = _stlink_usb_write_mem32(sl, DCRSR, 4); + if (ret == -1) + return ret; + _stlink_usb_read_mem32(sl, DCRDR, 4); + if (ret == -1) + return ret; r = read_uint32(sl->q_buf, 0); DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); @@ -542,22 +591,39 @@ void _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { regp->s[r_idx - 0x40] = r; break; } + + return 0; } -void _stlink_usb_read_all_unsupported_regs(stlink_t *sl, reg *regp) { - _stlink_usb_read_unsupported_reg(sl, 0x14, regp); - _stlink_usb_read_unsupported_reg(sl, 0x21, regp); +int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, reg *regp) { + int ret; + + ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); + if (ret == -1) + return ret; + + ret = _stlink_usb_read_unsupported_reg(sl, 0x21, regp); + if (ret == -1) + return ret; for (int i = 0; i < 32; i++) { - _stlink_usb_read_unsupported_reg(sl, 0x40+i, regp); + ret = _stlink_usb_read_unsupported_reg(sl, 0x40+i, regp); + if (ret == -1) + return ret; } + + return 0; } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ -void _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) { +int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) { + int ret; + if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ /* These are held in the same register */ - _stlink_usb_read_unsupported_reg(sl, 0x14, regp); + ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); + if (ret == -1) + return ret; val = (uint8_t) (val>>24); @@ -581,17 +647,19 @@ void _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, re write_uint32(sl->q_buf, val); - _stlink_usb_write_mem32(sl, DCRDR, 4); + ret = _stlink_usb_write_mem32(sl, DCRDR, 4); + if (ret == -1) + return ret; sl->q_buf[0] = (unsigned char) r_idx; sl->q_buf[1] = 0; sl->q_buf[2] = 0x01; sl->q_buf[3] = 0; - _stlink_usb_write_mem32(sl, DCRSR, 4); + return _stlink_usb_write_mem32(sl, DCRSR, 4); } -void _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { +int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -606,10 +674,12 @@ void _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return; + return size; } sl->q_len = (size_t) size; stlink_print_data(sl); + + return 0; } stlink_backend_t _stlink_usb_backend = { From 93e958f1371b4b0d5fb7171ea0f850902754ce7c Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Fri, 11 Mar 2016 15:27:56 +0100 Subject: [PATCH 0370/1435] stlink-common: Make stlink API propagate backend errors Signed-off-by: Maxime Coquelin --- src/stlink-common.c | 152 +++++++++++++++++++++++++++----------------- src/stlink-common.h | 50 +++++++-------- 2 files changed, 117 insertions(+), 85 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 204491cf6..fd9baba2d 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -472,43 +472,59 @@ void stlink_close(stlink_t *sl) { free(sl); } -void stlink_exit_debug_mode(stlink_t *sl) { +int stlink_exit_debug_mode(stlink_t *sl) { + int ret; + DLOG("*** stlink_exit_debug_mode ***\n"); - stlink_write_debug32(sl, DHCSR, DBGKEY); - sl->backend->exit_debug_mode(sl); + ret = stlink_write_debug32(sl, DHCSR, DBGKEY); + if (ret == -1) + return ret; + + return sl->backend->exit_debug_mode(sl); } -void stlink_enter_swd_mode(stlink_t *sl) { +int stlink_enter_swd_mode(stlink_t *sl) { DLOG("*** stlink_enter_swd_mode ***\n"); - sl->backend->enter_swd_mode(sl); + return sl->backend->enter_swd_mode(sl); } // Force the core into the debug mode -> halted state. -void stlink_force_debug(stlink_t *sl) { +int stlink_force_debug(stlink_t *sl) { DLOG("*** stlink_force_debug_mode ***\n"); - sl->backend->force_debug(sl); + return sl->backend->force_debug(sl); } -void stlink_exit_dfu_mode(stlink_t *sl) { +int stlink_exit_dfu_mode(stlink_t *sl) { DLOG("*** stlink_exit_dfu_mode ***\n"); - sl->backend->exit_dfu_mode(sl); + return sl->backend->exit_dfu_mode(sl); } -void stlink_core_id(stlink_t *sl) { +int stlink_core_id(stlink_t *sl) { + int ret; + DLOG("*** stlink_core_id ***\n"); - sl->backend->core_id(sl); + ret = sl->backend->core_id(sl); + if (ret == -1) { + ELOG("Failed to read core_id\n"); + return ret; + } if (sl->verbose > 2) stlink_print_data(sl); DLOG("core_id = 0x%08x\n", sl->core_id); - return; + return ret; } -uint32_t stlink_chip_id(stlink_t *sl) { - uint32_t chip_id; - stlink_read_debug32(sl, 0xE0042000, &chip_id); +int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { + int ret; + + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); + if (ret == -1) + return ret; + if (chip_id == 0) - stlink_read_debug32(sl, 0x40015800, &chip_id); //Try Corex M0 DBGMCU_IDCODE register address - return chip_id; + ret = stlink_read_debug32(sl, 0x40015800, chip_id); //Try Corex M0 DBGMCU_IDCODE register address + + return ret; } /** @@ -516,14 +532,17 @@ uint32_t stlink_chip_id(stlink_t *sl) { * @param sl stlink context * @param cpuid pointer to the result object */ -void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { +int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { uint32_t raw; - stlink_read_debug32(sl, CM3_REG_CPUID, &raw); + + if (stlink_read_debug32(sl, CM3_REG_CPUID, &raw)) + return -1; + cpuid->implementer_id = (raw >> 24) & 0x7f; cpuid->variant = (raw >> 20) & 0xf; cpuid->part = (raw >> 4) & 0xfff; cpuid->revision = raw & 0xf; - return; + return 0; } /** @@ -535,9 +554,10 @@ int stlink_load_device_params(stlink_t *sl) { ILOG("Loading device parameters....\n"); const chip_params_t *params = NULL; stlink_core_id(sl); - uint32_t chip_id = stlink_chip_id(sl); + uint32_t chip_id; uint32_t flash_size; + stlink_chip_id(sl, &chip_id); sl->chip_id = chip_id & 0xfff; /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/ if (sl->chip_id == 0x411) { @@ -599,25 +619,29 @@ int stlink_load_device_params(stlink_t *sl) { return 0; } -void stlink_reset(stlink_t *sl) { +int stlink_reset(stlink_t *sl) { DLOG("*** stlink_reset ***\n"); - sl->backend->reset(sl); + return sl->backend->reset(sl); } -void stlink_jtag_reset(stlink_t *sl, int value) { +int stlink_jtag_reset(stlink_t *sl, int value) { DLOG("*** stlink_jtag_reset ***\n"); - sl->backend->jtag_reset(sl, value); + return sl->backend->jtag_reset(sl, value); } -void stlink_run(stlink_t *sl) { +int stlink_run(stlink_t *sl) { DLOG("*** stlink_run ***\n"); - sl->backend->run(sl); + return sl->backend->run(sl); } -void stlink_status(stlink_t *sl) { +int stlink_status(stlink_t *sl) { + int ret; + DLOG("*** stlink_status ***\n"); - sl->backend->status(sl); + ret = sl->backend->status(sl); stlink_core_stat(sl); + + return ret; } /** @@ -645,9 +669,11 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { return; } -void stlink_version(stlink_t *sl) { +int stlink_version(stlink_t *sl) { DLOG("*** looking up stlink version\n"); - sl->backend->version(sl); + if (sl->backend->version(sl)) + return -1; + _parse_version(sl, &sl->version); DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID); @@ -661,6 +687,8 @@ void stlink_version(stlink_t *sl) { if (sl->version.swim_v == 0) { DLOG(" notice: the firmware doesn't support a swim interface\n"); } + + return -1; } int stlink_target_voltage(stlink_t *sl) { @@ -679,74 +707,78 @@ int stlink_target_voltage(stlink_t *sl) { return voltage; } -void stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { - sl->backend->read_debug32(sl, addr, data); - DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr); - return; +int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { + int ret; + + ret = sl->backend->read_debug32(sl, addr, data); + if (!ret) + DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr); + + return ret; } -void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { +int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr); - sl->backend->write_debug32(sl, addr, data); + return sl->backend->write_debug32(sl, addr, data); } -void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); if (len % 4 != 0) { fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); abort(); } - sl->backend->write_mem32(sl, addr, len); + return sl->backend->write_mem32(sl, addr, len); } -void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_read_mem32 ***\n"); if (len % 4 != 0) { // !!! never ever: fw gives just wrong values fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); abort(); } - sl->backend->read_mem32(sl, addr, len); + return sl->backend->read_mem32(sl, addr, len); } -void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { +int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem8 ***\n"); if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour fprintf(stderr, "Error: Data length > 64: +%d byte.\n", len); abort(); } - sl->backend->write_mem8(sl, addr, len); + return sl->backend->write_mem8(sl, addr, len); } -void stlink_read_all_regs(stlink_t *sl, reg *regp) { +int stlink_read_all_regs(stlink_t *sl, reg *regp) { DLOG("*** stlink_read_all_regs ***\n"); - sl->backend->read_all_regs(sl, regp); + return sl->backend->read_all_regs(sl, regp); } -void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp) { +int stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp) { DLOG("*** stlink_read_all_unsupported_regs ***\n"); - sl->backend->read_all_unsupported_regs(sl, regp); + return sl->backend->read_all_unsupported_regs(sl, regp); } -void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { +int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { DLOG("*** stlink_write_reg\n"); - sl->backend->write_reg(sl, reg, idx); + return sl->backend->write_reg(sl, reg, idx); } -void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) { +int stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) { DLOG("*** stlink_read_reg\n"); DLOG(" (%d) ***\n", r_idx); if (r_idx > 20 || r_idx < 0) { fprintf(stderr, "Error: register index must be in [0..20]\n"); - return; + return -1; } - sl->backend->read_reg(sl, r_idx, regp); + return sl->backend->read_reg(sl, r_idx, regp); } -void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { +int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { int r_convert; DLOG("*** stlink_read_unsupported_reg\n"); @@ -761,13 +793,13 @@ void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { r_convert = 0x40 + (r_idx - 0x20); } else { fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return; + return -1; } - sl->backend->read_unsupported_reg(sl, r_convert, regp); + return sl->backend->read_unsupported_reg(sl, r_convert, regp); } -void stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) { +int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) { int r_convert; DLOG("*** stlink_write_unsupported_reg\n"); @@ -782,10 +814,10 @@ void stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *re r_convert = 0x40 + (r_idx - 0x20); } else { fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return; + return -1; } - sl->backend->write_unsupported_reg(sl, val, r_convert, regp); + return sl->backend->write_unsupported_reg(sl, val, r_convert, regp); } unsigned int is_core_halted(stlink_t *sl) { @@ -794,9 +826,9 @@ unsigned int is_core_halted(stlink_t *sl) { return sl->q_buf[0] == STLINK_CORE_HALTED; } -void stlink_step(stlink_t *sl) { +int stlink_step(stlink_t *sl) { DLOG("*** stlink_step ***\n"); - sl->backend->step(sl); + return sl->backend->step(sl); } int stlink_current_mode(stlink_t *sl) { diff --git a/src/stlink-common.h b/src/stlink-common.h index 467b9b90a..e40886481 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -625,31 +625,31 @@ extern "C" { //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose); // delegated functions... - void stlink_enter_swd_mode(stlink_t *sl); - void stlink_enter_jtag_mode(stlink_t *sl); - void stlink_exit_debug_mode(stlink_t *sl); - void stlink_exit_dfu_mode(stlink_t *sl); + int stlink_enter_swd_mode(stlink_t *sl); + int stlink_enter_jtag_mode(stlink_t *sl); + int stlink_exit_debug_mode(stlink_t *sl); + int stlink_exit_dfu_mode(stlink_t *sl); void stlink_close(stlink_t *sl); - void stlink_core_id(stlink_t *sl); - void stlink_reset(stlink_t *sl); - void stlink_jtag_reset(stlink_t *sl, int value); - void stlink_run(stlink_t *sl); - void stlink_status(stlink_t *sl); - void stlink_version(stlink_t *sl); - void stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); - void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); - void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); - void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); - void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); - void stlink_read_all_regs(stlink_t *sl, reg *regp); - void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp); - void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp); - void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp); - void stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp); - void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); - void stlink_step(stlink_t *sl); + int stlink_core_id(stlink_t *sl); + int stlink_reset(stlink_t *sl); + int stlink_jtag_reset(stlink_t *sl, int value); + int stlink_run(stlink_t *sl); + int stlink_status(stlink_t *sl); + int stlink_version(stlink_t *sl); + int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); + int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); + int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); + int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); + int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); + int stlink_read_all_regs(stlink_t *sl, reg *regp); + int stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp); + int stlink_read_reg(stlink_t *sl, int r_idx, reg *regp); + int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp); + int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp); + int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); + int stlink_step(stlink_t *sl); int stlink_current_mode(stlink_t *sl); - void stlink_force_debug(stlink_t *sl); + int stlink_force_debug(stlink_t *sl); int stlink_target_voltage(stlink_t *sl); @@ -661,8 +661,8 @@ extern "C" { int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); // PUBLIC - uint32_t stlink_chip_id(stlink_t *sl); - void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); + int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); + int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); // privates, publics, the rest.... // TODO sort what is private, and what is not From a9f00bc5b7428ff3a2e5ea8744f726eccc2f4586 Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Fri, 11 Mar 2016 16:57:34 +0100 Subject: [PATCH 0371/1435] st-flash: Improve error handling Now that libusb errors are propagated up to stlink API, we can handle these errors. Signed-off-by: Maxime Coquelin --- flash/main.c | 64 ++++++++++++++++++++++++++++++++-------------------- 1 file changed, 40 insertions(+), 24 deletions(-) diff --git a/flash/main.c b/flash/main.c index 284068cb5..0ba429c66 100644 --- a/flash/main.c +++ b/flash/main.c @@ -172,36 +172,48 @@ int main(int ac, char** av) { printf("invalid command line\n"); usage(); - goto on_error; + return -1; } if (o.devname != NULL) /* stlinkv1 */ - { sl = stlink_v1_open(o.log_level, 1); - if (sl == NULL) goto on_error; - sl->verbose = o.log_level; - } else /* stlinkv2 */ - { sl = stlink_open_usb(o.log_level, 1, o.serial); - if (sl == NULL) goto on_error; - sl->verbose = o.log_level; - } + + if (sl == NULL) + return -1; + + sl->verbose = o.log_level; connected_stlink = sl; signal(SIGINT, &cleanup); signal(SIGTERM, &cleanup); signal(SIGSEGV, &cleanup); - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) - stlink_exit_dfu_mode(sl); + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { + if (stlink_exit_dfu_mode(sl)) { + printf("Failed to exit DFU mode\n"); + goto on_error; + } + } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) - stlink_enter_swd_mode(sl); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { + if (stlink_enter_swd_mode(sl)) { + printf("Failed to enter SWD mode\n"); + goto on_error; + } + } if (o.reset){ - stlink_jtag_reset(sl,2); - stlink_reset(sl); + if (stlink_jtag_reset(sl, 2)) { + printf("Failed to reset JTAG\n"); + goto on_error; + } + + if (stlink_reset(sl)) { + printf("Failed to reset device\n"); + goto on_error; + } } // Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 @@ -217,8 +229,15 @@ int main(int ac, char** av) } // Core must be halted to use RAM based flashloaders - stlink_force_debug(sl); - stlink_status(sl); + if (stlink_force_debug(sl)) { + printf("Failed to halt the core\n"); + goto on_error; + } + + if (stlink_status(sl)) { + printf("Failed to get Core's status\n"); + goto on_error; + } if (o.cmd == DO_WRITE) /* write */ { @@ -236,7 +255,7 @@ int main(int ac, char** av) err = stlink_fwrite_sram(sl, o.filename, o.addr); if (err == -1) { - printf("stlink_sram_flash() == -1\n"); + printf("stlink_fwrite_sram() == -1\n"); goto on_error; } } @@ -245,7 +264,7 @@ int main(int ac, char** av) err = stlink_erase_flash_mass(sl); if (err == -1) { - printf("stlink_fwrite_flash() == -1\n"); + printf("stlink_erase_flash_mass() == -1\n"); goto on_error; } } @@ -274,11 +293,8 @@ int main(int ac, char** av) err = 0; on_error: - if (sl != NULL) - { - stlink_exit_debug_mode(sl); - stlink_close(sl); - } + stlink_exit_debug_mode(sl); + stlink_close(sl); return err; } From abcd47f4216d40d1497eb4e07fc100e5979dd284 Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Fri, 11 Mar 2016 18:51:15 +0100 Subject: [PATCH 0372/1435] stlink-common: Introduce type of flash controller enum Having a type of flash information has some advantages: - Make the code easier to read - Make adding family derivatives easier (only add a new entry in header file) - Make the backends error propagation easier to implement (less places to fix) Signed-off-by: Maxime Coquelin --- src/stlink-common.c | 331 ++++++++++++++++++++------------------------ src/stlink-common.h | 42 ++++++ 2 files changed, 190 insertions(+), 183 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index fd9baba2d..f15738e7f 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -183,15 +183,17 @@ static inline uint32_t read_flash_obr(stlink_t *sl) { } static inline uint32_t read_flash_cr(stlink_t *sl) { - uint32_t res; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) ||(sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) - stlink_read_debug32(sl, FLASH_F4_CR, &res); - else if (sl->chip_id == STM32_CHIPID_L4) - stlink_read_debug32(sl, STM32L4_FLASH_CR, &res); + uint32_t reg, res; + + if (sl->flash_type == FLASH_TYPE_F4) + reg = FLASH_F4_CR; + else if (sl->flash_type == FLASH_TYPE_L4) + reg = STM32L4_FLASH_CR; else - stlink_read_debug32(sl, FLASH_CR, &res); + reg = FLASH_CR; + + stlink_read_debug32(sl, reg, &res); + #if DEBUG_FLASH fprintf(stdout, "CR:0x%x\n", res); #endif @@ -200,37 +202,34 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ - uint32_t cr = read_flash_cr(sl); + uint32_t cr_lock_shift, cr = read_flash_cr(sl); - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) - return cr & (1 << FLASH_F4_CR_LOCK); - else if (sl->chip_id == STM32_CHIPID_L4) - return cr & (1lu << STM32L4_FLASH_CR_LOCK); + if (sl->flash_type == FLASH_TYPE_F4) + cr_lock_shift = FLASH_F4_CR_LOCK; + else if (sl->flash_type == FLASH_TYPE_L4) + cr_lock_shift = STM32L4_FLASH_CR_LOCK; else - return cr & (1 << FLASH_CR_LOCK); + cr_lock_shift = FLASH_CR_LOCK; + + return cr & (1 << cr_lock_shift); } static void unlock_flash(stlink_t *sl) { + uint32_t key_reg; /* the unlock sequence consists of 2 write cycles where 2 key values are written to the FLASH_KEYR register. an invalid sequence results in a definitive lock of the FPEC block until next reset. */ - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { - stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY1); - stlink_write_debug32(sl, FLASH_F4_KEYR, FLASH_KEY2); - } else if (sl->chip_id == STM32_CHIPID_L4) { - stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY1); - stlink_write_debug32(sl, STM32L4_FLASH_KEYR, FLASH_KEY2); - } else { - stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY1); - stlink_write_debug32(sl, FLASH_KEYR, FLASH_KEY2); - } + if (sl->flash_type == FLASH_TYPE_F4) + key_reg = FLASH_F4_KEYR; + else if (sl->flash_type == FLASH_TYPE_L4) + key_reg = STM32L4_FLASH_KEYR; + else + key_reg = FLASH_KEYR; + stlink_write_debug32(sl, key_reg, FLASH_KEY1); + stlink_write_debug32(sl, key_reg, FLASH_KEY2); } static int unlock_flash_if(stlink_t *sl) { @@ -248,48 +247,56 @@ static int unlock_flash_if(stlink_t *sl) { } static void lock_flash(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { - const uint32_t n = read_flash_cr(sl) | (1 << FLASH_F4_CR_LOCK); - stlink_write_debug32(sl, FLASH_F4_CR, n); - } else if (sl->chip_id == STM32_CHIPID_L4) { - const uint32_t n = read_flash_cr(sl) | (1lu << STM32L4_FLASH_CR_LOCK); - stlink_write_debug32(sl, STM32L4_FLASH_CR, n); + uint32_t cr_lock_shift, cr_reg, n; + + if (sl->flash_type == FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; } else { - /* write to 1 only. reset by hw at unlock sequence */ - const uint32_t n = read_flash_cr(sl) | (1 << FLASH_CR_LOCK); - stlink_write_debug32(sl, FLASH_CR, n); + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; } + + n = read_flash_cr(sl) | (1 << cr_lock_shift); + stlink_write_debug32(sl, cr_reg, n); } static void set_flash_cr_pg(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { - uint32_t x = read_flash_cr(sl); - x |= (1 << FLASH_CR_PG); - stlink_write_debug32(sl, FLASH_F4_CR, x); - } else if (sl->chip_id == STM32_CHIPID_L4) { - uint32_t x = read_flash_cr(sl); - x &=~ STM32L4_FLASH_CR_OPBITS; - x |= (1 << STM32L4_FLASH_CR_PG); - stlink_write_debug32(sl, STM32L4_FLASH_CR, x); + uint32_t cr_reg, x; + + x = read_flash_cr(sl); + + if (sl->flash_type == FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + x &= ~STM32L4_FLASH_CR_OPBITS; + x |= 1 << STM32L4_FLASH_CR_PG; } else { - const uint32_t n = 1 << FLASH_CR_PG; - stlink_write_debug32(sl, FLASH_CR, n); + cr_reg = FLASH_CR; + x = 1 << FLASH_CR_PG; } + + stlink_write_debug32(sl, cr_reg, x); } static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { - const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) - stlink_write_debug32(sl, FLASH_F4_CR, n); + uint32_t cr_reg, n; + + if (sl->flash_type == FLASH_TYPE_F4) + cr_reg = FLASH_F4_CR; + else if (sl->flash_type == FLASH_TYPE_L4) + cr_reg = STM32L4_FLASH_CR; else - stlink_write_debug32(sl, FLASH_CR, n); + cr_reg = FLASH_CR; + + n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); + stlink_write_debug32(sl, cr_reg, n); } static void set_flash_cr_per(stlink_t *sl) { @@ -303,57 +310,60 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { } static void set_flash_cr_mer(stlink_t *sl) { - uint32_t val; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { - stlink_read_debug32(sl, FLASH_F4_CR, &val); - val |= 1 << FLASH_CR_MER; - stlink_write_debug32(sl, FLASH_F4_CR, val); - } else if (sl->chip_id == STM32_CHIPID_L4) { - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val &=~ STM32L4_FLASH_CR_OPBITS; - val |= (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER2); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + uint32_t val, cr_reg, cr_mer; + + if (sl->flash_type == FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_mer = 1 << FLASH_CR_MER; + } else if (sl->flash_type == FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); } else { - stlink_read_debug32(sl, FLASH_CR, &val); - val |= 1 << FLASH_CR_MER; - stlink_write_debug32(sl, FLASH_CR, val); + cr_reg = FLASH_CR; + cr_mer = 1 << FLASH_CR_MER; } + + stlink_read_debug32(sl, cr_reg, &val); + val |= cr_mer; + stlink_write_debug32(sl, cr_reg, val); } static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { - uint32_t val; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { - stlink_read_debug32(sl, FLASH_F4_CR, &val); - val &= ~(1 << FLASH_CR_MER); - stlink_write_debug32(sl, FLASH_F4_CR, val); + uint32_t val, cr_reg, cr_mer; + + if (sl->flash_type == FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_mer = 1 << FLASH_CR_MER; + } else if (sl->flash_type == FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); } else { - stlink_read_debug32(sl, FLASH_CR, &val); - val &= ~(1 << FLASH_CR_MER); - stlink_write_debug32(sl, FLASH_CR, val); + cr_reg = FLASH_CR; + cr_mer = 1 << FLASH_CR_MER; } + + stlink_read_debug32(sl, cr_reg, &val); + val &= ~cr_mer; + stlink_write_debug32(sl, cr_reg, val); } static void set_flash_cr_strt(stlink_t *sl) { - uint32_t val; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { - val = read_flash_cr(sl); - val |= (1 << FLASH_F4_CR_STRT); - stlink_write_debug32(sl, FLASH_F4_CR, val); - } else if (sl->chip_id == STM32_CHIPID_L4) { - val = read_flash_cr(sl); - val |= (1lu << STM32L4_FLASH_CR_STRT); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + uint32_t val, cr_reg, cr_strt; + + if (sl->flash_type == FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_strt = 1 << FLASH_F4_CR_STRT; + } else if (sl->flash_type == FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_strt = 1 << STM32L4_FLASH_CR_STRT; } else { - stlink_read_debug32(sl, FLASH_CR, &val); - val |= 1 << FLASH_CR_STRT; - stlink_write_debug32(sl, FLASH_CR, val); + cr_reg = FLASH_CR; + cr_strt = 1 << FLASH_CR_STRT; } + + stlink_read_debug32(sl, cr_reg, &val); + val |= cr_strt; + stlink_write_debug32(sl, cr_reg, val); } static inline uint32_t read_flash_acr(stlink_t *sl) { @@ -363,28 +373,31 @@ static inline uint32_t read_flash_acr(stlink_t *sl) { } static inline uint32_t read_flash_sr(stlink_t *sl) { - uint32_t res; - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) - stlink_read_debug32(sl, FLASH_F4_SR, &res); - else if (sl->chip_id == STM32_CHIPID_L4) - stlink_read_debug32(sl, STM32L4_FLASH_SR, &res); + uint32_t res, sr_reg; + + if (sl->flash_type == FLASH_TYPE_F4) + sr_reg = FLASH_F4_SR; + else if (sl->flash_type == FLASH_TYPE_L4) + sr_reg = STM32L4_FLASH_SR; else - stlink_read_debug32(sl, FLASH_SR, &res); - //fprintf(stdout, "SR:0x%x\n", *(uint32_t*) sl->q_buf); + sr_reg = FLASH_SR; + + stlink_read_debug32(sl, sr_reg, &res); + return res; } static inline unsigned int is_flash_busy(stlink_t *sl) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_F4_DSI)) - return read_flash_sr(sl) & (1 << FLASH_F4_SR_BSY); - else if (sl->chip_id == STM32_CHIPID_L4) - return read_flash_sr(sl) & (1 << STM32L4_FLASH_SR_BSY); + uint32_t sr_busy_shift; + + if (sl->flash_type == FLASH_TYPE_F4) + sr_busy_shift = FLASH_F4_SR_BSY; + else if (sl->flash_type == FLASH_TYPE_L4) + sr_busy_shift = STM32L4_FLASH_SR_BSY; else - return read_flash_sr(sl) & (1 << FLASH_SR_BSY); + sr_busy_shift = FLASH_SR_BSY; + + return read_flash_sr(sl) & (1 << sr_busy_shift); } static void wait_flash_busy(stlink_t *sl) { @@ -600,6 +613,7 @@ int stlink_load_device_params(stlink_t *sl) { } else { sl->flash_size = flash_size * 1024; } + sl->flash_type = params->flash_type; sl->flash_pgsz = params->flash_pagesize; sl->sram_size = params->sram_size; sl->sys_base = params->bootrom_base; @@ -1216,9 +1230,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4)|| (sl->chip_id == STM32_CHIPID_F4_DSI)) { + if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1262,9 +1274,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif - } else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 - || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH - || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { + } else if (sl->flash_type == FLASH_TYPE_L0) { uint32_t val; uint32_t flash_regs_base; @@ -1332,13 +1342,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->core_id == STM32VL_CORE_ID - || sl->core_id == STM32F0_CORE_ID - || sl->chip_id == STM32_CHIPID_F3 - || sl->chip_id == STM32_CHIPID_F3_SMALL - || sl->chip_id == STM32_CHIPID_F303_HIGH - || sl->chip_id == STM32_CHIPID_F37x - || sl->chip_id == STM32_CHIPID_F334) { + } else if (sl->flash_type == FLASH_TYPE_F0) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1370,9 +1374,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 - || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH - || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { + if (sl->flash_type == FLASH_TYPE_L0) { /* erase each page */ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1838,16 +1840,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t if (eraseonly) return 0; - if ((sl->chip_id == STM32_CHIPID_F2) || - (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || - (sl->chip_id == STM32_CHIPID_F4_HD) || - (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || - (sl->chip_id == STM32_CHIPID_F7) || - (sl->chip_id == STM32_CHIPID_L4) || - (sl->chip_id == STM32_CHIPID_F4_DSI)) { + if ((sl->flash_type == FLASH_TYPE_F4) || (sl->flash_type == FLASH_TYPE_L4)) { /* todo: check write operation */ ILOG("Starting Flash write for F2/F4/L4\n"); @@ -1907,9 +1900,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } //STM32F4END - else if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 - || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH - || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { + else if (sl->flash_type == FLASH_TYPE_L0) { /* use fast word write. todo: half page. */ uint32_t val; uint32_t flash_regs_base; @@ -1984,13 +1975,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->core_id == STM32VL_CORE_ID || - sl->core_id == STM32F0_CORE_ID || - sl->chip_id == STM32_CHIPID_F3 || - sl->chip_id == STM32_CHIPID_F3_SMALL || - sl->chip_id == STM32_CHIPID_F303_HIGH || - sl->chip_id == STM32_CHIPID_F334 || - sl->chip_id == STM32_CHIPID_F37x) { + } else if (sl->flash_type == FLASH_TYPE_F0) { ILOG("Starting Flash write for VL/F0/F3 core id\n"); /* flash loader initialization */ if (init_flash_loader(sl, &fl) == -1) { @@ -2040,14 +2025,19 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ int err; unsigned int num_empty, index, val; - unsigned char erased_pattern = (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 - || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH - || sl->chip_id == STM32_CHIPID_L152_RE) ? 0:0xff; + unsigned char erased_pattern; mapped_file_t mf = MAPPED_FILE_INITIALIZER; + if (map_file(&mf, path) == -1) { ELOG("map_file() == -1\n"); return -1; } + + if (sl->flash_type == FLASH_TYPE_L0) + erased_pattern = 0x00; + else + erased_pattern = 0xff; + index = mf.len; for(num_empty = 0; num_empty != mf.len; ++num_empty) { if (mf.base[--index] != erased_pattern) { @@ -2083,9 +2073,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 - || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH - || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { + if (sl->flash_type == FLASH_TYPE_L0) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -2096,13 +2084,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, count, 2); /* count (32 bits words) */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - } else if (sl->core_id == STM32VL_CORE_ID || - sl->core_id == STM32F0_CORE_ID || - sl->chip_id == STM32_CHIPID_F3 || - sl->chip_id == STM32_CHIPID_F3_SMALL || - sl->chip_id == STM32_CHIPID_F303_HIGH || - sl->chip_id == STM32_CHIPID_F37x || - sl->chip_id == STM32_CHIPID_F334) { + } else if (sl->flash_type == FLASH_TYPE_F0) { size_t count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; @@ -2114,10 +2096,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { - + } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; if (sl->chip_id == STM32_CHIPID_L4) { @@ -2152,10 +2131,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } /* check written byte count */ - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 - || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH - || sl->chip_id == STM32_CHIPID_L152_RE || sl->chip_id == STM32_CHIPID_L0) { - + if (sl->flash_type == FLASH_TYPE_L0) { size_t count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -2165,25 +2141,14 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - } else if (sl->core_id == STM32VL_CORE_ID || - sl->core_id == STM32F0_CORE_ID || - sl->chip_id == STM32_CHIPID_F3 || - sl->chip_id == STM32_CHIPID_F3_SMALL || - sl->chip_id == STM32_CHIPID_F303_HIGH || - sl->chip_id == STM32_CHIPID_F37x || - sl->chip_id == STM32_CHIPID_F334) { - + } else if (sl->flash_type == FLASH_TYPE_F0) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { fprintf(stderr, "write error, count == %u\n", rr.r[2]); return -1; } - } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F7) || (sl->chip_id == STM32_CHIPID_L4) || - (sl->chip_id == STM32_CHIPID_F4_DSI)) { - + } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) { stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { fprintf(stderr, "write error, count == %u\n", rr.r[2]); diff --git a/src/stlink-common.h b/src/stlink-common.h index e40886481..e7be10ff0 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -166,9 +166,17 @@ extern "C" { /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 + enum flash_type { + FLASH_TYPE_F0, + FLASH_TYPE_L0, + FLASH_TYPE_F4, + FLASH_TYPE_L4, + }; + typedef struct chip_params_ { uint32_t chip_id; char* description; + enum flash_type flash_type; uint32_t flash_size_reg; uint32_t flash_pagesize; uint32_t sram_size; @@ -183,6 +191,7 @@ extern "C" { //RM0385 and DS10916 document was used to find these paramaters .chip_id = STM32_CHIPID_F7, .description = "F7 device", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1ff0f442, // section 41.2 .flash_pagesize = 0x800, // No flash pages .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 @@ -192,6 +201,7 @@ extern "C" { { // table 2, PM0063 .chip_id = STM32_CHIPID_F1_MEDIUM, .description = "F1 Medium-density device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, .sram_size = 0x5000, @@ -201,6 +211,7 @@ extern "C" { { // table 1, PM0059 .chip_id = STM32_CHIPID_F2, .description = "F2 device", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/ .flash_pagesize = 0x20000, .sram_size = 0x20000, @@ -210,6 +221,7 @@ extern "C" { { // PM0063 .chip_id = STM32_CHIPID_F1_LOW, .description = "F1 Low-density device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, .sram_size = 0x2800, @@ -219,6 +231,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F4, .description = "F4 device", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, .sram_size = 0x30000, @@ -228,6 +241,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F4_DSI, .description = "F46x and F47x device", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, .sram_size = 0x40000, @@ -237,6 +251,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F4_HD, .description = "F42x and F43x device", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, .sram_size = 0x40000, @@ -246,6 +261,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F4_LP, .description = "F4 device (low power)", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x10000, @@ -255,6 +271,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F411RE, .description = "F4 device (low power) - stm32f411re", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x20000, @@ -264,6 +281,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F4_DE, .description = "F4 device (Dynamic Efficency)", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x18000, @@ -273,6 +291,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F1_HIGH, .description = "F1 High-density device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x10000, @@ -284,6 +303,7 @@ extern "C" { // not the sector write protection...) .chip_id = STM32_CHIPID_L1_MEDIUM, .description = "L1 Med-density device", + .flash_type = FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, .flash_pagesize = 0x100, .sram_size = 0x4000, @@ -293,6 +313,7 @@ extern "C" { { .chip_id = STM32_CHIPID_L1_CAT2, .description = "L1 Cat.2 device", + .flash_type = FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, .flash_pagesize = 0x100, .sram_size = 0x8000, @@ -302,6 +323,7 @@ extern "C" { { .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS, .description = "L1 Medium-Plus-density device", + .flash_type = FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/ @@ -311,6 +333,7 @@ extern "C" { { .chip_id = STM32_CHIPID_L1_HIGH, .description = "L1 High-density device", + .flash_type = FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/ @@ -320,6 +343,7 @@ extern "C" { { .chip_id = STM32_CHIPID_L152_RE, .description = "L152RE", + .flash_type = FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/ @@ -329,6 +353,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F1_CONN, .description = "F1 Connectivity line device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x10000, @@ -338,6 +363,7 @@ extern "C" { {//Low and Medium density VL have same chipid. RM0041 25.6.1 .chip_id = STM32_CHIPID_F1_VL_MEDIUM_LOW, .description = "F1 Medium/Low-density Value Line device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, .sram_size = 0x2000,//0x1000 for low density devices @@ -348,6 +374,7 @@ extern "C" { // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. .chip_id = STM32_CHIPID_F446, .description = "F446 device", + .flash_type = FLASH_TYPE_F4, .flash_size_reg = 0x1fff7a22, .flash_pagesize = 0x20000, .sram_size = 0x20000, @@ -359,6 +386,7 @@ extern "C" { // Support based on DM00043574.pdf (RM0316) document. .chip_id = STM32_CHIPID_F3, .description = "F3 device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0xa000, @@ -370,6 +398,7 @@ extern "C" { // Support based on 303 above (37x and 30x have same memory map) .chip_id = STM32_CHIPID_F37x, .description = "F3 device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0xa000, @@ -379,6 +408,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F1_VL_HIGH, .description = "F1 High-density value line device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x8000, @@ -388,6 +418,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F1_XL, .description = "F1 XL-density device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x18000, @@ -399,6 +430,7 @@ extern "C" { //RM0091 document was used to find these paramaters .chip_id = STM32_CHIPID_F0_CAN, .description = "F07x device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 @@ -410,6 +442,7 @@ extern "C" { //RM0091 document was used to find these paramaters .chip_id = STM32_CHIPID_F0, .description = "F0 device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 @@ -419,6 +452,7 @@ extern "C" { { .chip_id = STM32_CHIPID_F09X, .description = "F09X device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) @@ -430,6 +464,7 @@ extern "C" { //RM0091 document was used to find these paramaters .chip_id = STM32_CHIPID_F04, .description = "F04x device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 @@ -441,6 +476,7 @@ extern "C" { //RM0091 document was used to find these paramaters .chip_id = STM32_CHIPID_F0_SMALL, .description = "F0 small device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 @@ -451,6 +487,7 @@ extern "C" { // STM32F30x .chip_id = STM32_CHIPID_F3_SMALL, .description = "F3 small device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0xa000, @@ -462,6 +499,7 @@ extern "C" { // RM0367,RM0377 documents was used to find these parameters .chip_id = STM32_CHIPID_L0, .description = "L0x3 device", + .flash_type = FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, .sram_size = 0x2000, @@ -473,6 +511,7 @@ extern "C" { // RM0364 document was used to find these parameters .chip_id = STM32_CHIPID_F334, .description = "F334 device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0x3000, @@ -484,6 +523,7 @@ extern "C" { // Support based on DM00043574.pdf (RM0316) document rev 5. .chip_id = STM32_CHIPID_F303_HIGH, .description = "F303 high density device", + .flash_type = FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register .flash_pagesize = 0x800, // 4.2.1 Flash memory organization .sram_size = 0x10000, // 3.3 Embedded SRAM @@ -495,6 +535,7 @@ extern "C" { // From RM0351. .chip_id = STM32_CHIPID_L4, .description = "L4 device", + .flash_type = FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671) .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81) // SRAM1 is "up to" 96k in the standard Cortex-M memory map; @@ -605,6 +646,7 @@ extern "C" { #define STM32F4_FLASH_PGSZ 16384 #define STM32F4_FLASH_SIZE (128 * 1024 * 8) + enum flash_type flash_type; stm32_addr_t flash_base; size_t flash_size; size_t flash_pgsz; From 5693181e6be20b4a4ebca8d3c21d44cd61e753ca Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Mon, 14 Mar 2016 13:01:23 +0100 Subject: [PATCH 0373/1435] stlink-common: Simplify run_flash_loader() This patch simplifies run_flash_loader() function in preparation for error propagation from backends. Doing this, we have less call sites for stlink API. Signed-off-by: Maxime Coquelin --- src/stlink-common.c | 82 +++++++++++++++++---------------------------- 1 file changed, 30 insertions(+), 52 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index f15738e7f..5fbf57542 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -2064,7 +2064,9 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { reg rr; - int i = 0; + int target_reg, source_reg, i = 0; + size_t count; + DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); // FIXME This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { @@ -2074,46 +2076,39 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } if (sl->flash_type == FLASH_TYPE_L0) { - - size_t count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) ++count; - - /* setup core */ - stlink_write_reg(sl, target, 0); /* target */ - stlink_write_reg(sl, fl->buf_addr, 1); /* source */ - stlink_write_reg(sl, count, 2); /* count (32 bits words) */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - + count = size / sizeof(uint32_t); + if (size % sizeof(uint32_t)) + ++count; + target_reg = 0; + source_reg = 1; } else if (sl->flash_type == FLASH_TYPE_F0) { - - size_t count = size / sizeof(uint16_t); - if (size % sizeof(uint16_t)) ++count; - - /* setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); /* source */ - stlink_write_reg(sl, target, 1); /* target */ - stlink_write_reg(sl, count, 2); /* count (16 bits half words) */ - stlink_write_reg(sl, 0, 3); /* flash bank 0 (input) */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - + count = size / sizeof(uint16_t); + if (size % sizeof(uint16_t)) + ++count; + target_reg = 1; + source_reg = 0; } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) { - size_t count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) ++count; + count = size / sizeof(uint32_t); + if (size % sizeof(uint32_t)) + ++count; if (sl->chip_id == STM32_CHIPID_L4) { - if (count % 2) ++count; + if (count % 2) + ++count; } - - /* setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); /* source */ - stlink_write_reg(sl, target, 1); /* target */ - stlink_write_reg(sl, count, 2); /* count (32 bits words) */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - + target_reg = 1; + source_reg = 0; } else { fprintf(stderr, "unknown coreid 0x%x, don't know what flash loader to use\n", sl->core_id); return -1; } + /* setup core */ + stlink_write_reg(sl, fl->buf_addr, source_reg); /* source */ + stlink_write_reg(sl, target, target_reg); /* target */ + stlink_write_reg(sl, count, 2); /* count */ + stlink_write_reg(sl, 0, 3); /* flash bank 0 (input), only used on F0, but armless fopr others */ + stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ + /* run loader */ stlink_run(sl); @@ -2130,36 +2125,19 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } + stlink_read_all_regs(sl, &rr); + /* check written byte count */ if (sl->flash_type == FLASH_TYPE_L0) { - size_t count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) ++count; - - stlink_read_reg(sl, 3, &rr); if (rr.r[3] != count) { fprintf(stderr, "write error, count == %u\n", rr.r[3]); return -1; } - - } else if (sl->flash_type == FLASH_TYPE_F0) { - stlink_read_reg(sl, 2, &rr); - if (rr.r[2] != 0) { - fprintf(stderr, "write error, count == %u\n", rr.r[2]); - return -1; - } - - } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) { - stlink_read_reg(sl, 2, &rr); + } else { if (rr.r[2] != 0) { fprintf(stderr, "write error, count == %u\n", rr.r[2]); return -1; } - - } else { - - fprintf(stderr, "unknown coreid 0x%x, can't check written byte count\n", sl->core_id); - return -1; - } return 0; From 907383da8ef95fedc630cdf7cf102d44ae229200 Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Mon, 14 Mar 2016 13:32:48 +0100 Subject: [PATCH 0374/1435] stlink-common: Update STM32L0 and STM32L1 loader ABI This patch invert source and destination registers in the stm32l0 and stm32l1 loaders, so that it follows the same ABI as other stm32 loaders. Doing that, the run_flash_loader() function can be simplified a little. Signed-off-by: Maxime Coquelin --- flashloaders/stm32l0x.s | 8 ++++---- flashloaders/stm32lx.s | 8 ++++---- src/stlink-common.c | 38 +++++++++++++++----------------------- 3 files changed, 23 insertions(+), 31 deletions(-) diff --git a/flashloaders/stm32l0x.s b/flashloaders/stm32l0x.s index 9fc44468f..6c863c64a 100644 --- a/flashloaders/stm32l0x.s +++ b/flashloaders/stm32l0x.s @@ -34,8 +34,8 @@ .global write /* - r0 - destination address - r1 - source address + r0 - source address + r1 - destination address r2 - count */ @@ -46,9 +46,9 @@ write_word: // Load one word from address in r0, increment by 4 - ldr r4, [r1] + ldr r4, [r0] // Store the word to address in r1, increment by 4 - str r4, [r0] + str r4, [r1] // Increment r3 adds r3, #1 adds r1, #4 diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s index 799d1345c..764594d9c 100644 --- a/flashloaders/stm32lx.s +++ b/flashloaders/stm32lx.s @@ -34,8 +34,8 @@ .global write /* - r0 - destination address - r1 - source address + r0 - source address + r1 - destination address r2 - count */ @@ -46,9 +46,9 @@ write_word: // Load one word from address in r0, increment by 4 - ldr.w ip, [r1], #4 + ldr.w ip, [r0], #4 // Store the word to address in r1, increment by 4 - str.w ip, [r0], #4 + str.w ip, [r1], #4 // Increment r3 adds r3, #1 diff --git a/src/stlink-common.c b/src/stlink-common.c index 5fbf57542..01ce06c6f 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1501,8 +1501,8 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { static const uint8_t loader_code_stm32l[] = { /* openocd.git/contrib/loaders/flash/stm32lx.S - r0, input, dest addr - r1, input, source addr + r0, input, source addr + r1, input, dest addr r2, input, word count r3, output, word count */ @@ -1510,8 +1510,8 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x00, 0x23, 0x04, 0xe0, - 0x51, 0xf8, 0x04, 0xcb, - 0x40, 0xf8, 0x04, 0xcb, + 0x50, 0xf8, 0x04, 0xcb, + 0x41, 0xf8, 0x04, 0xcb, 0x01, 0x33, 0x93, 0x42, @@ -1522,8 +1522,8 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { static const uint8_t loader_code_stm32l0[] = { /* - r0, input, dest addr - r1, input, source addr + r0, input, source addr + r1, input, dest addr r2, input, word count r3, output, word count */ @@ -1531,8 +1531,8 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0x00, 0x23, 0x04, 0xe0, - 0x0c, 0x68, - 0x04, 0x60, + 0x04, 0x68, + 0x0c, 0x60, 0x01, 0x33, 0x04, 0x31, 0x04, 0x30, @@ -2064,7 +2064,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { reg rr; - int target_reg, source_reg, i = 0; + int i = 0; size_t count; DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); @@ -2075,19 +2075,13 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - if (sl->flash_type == FLASH_TYPE_L0) { - count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) - ++count; - target_reg = 0; - source_reg = 1; - } else if (sl->flash_type == FLASH_TYPE_F0) { + if (sl->flash_type == FLASH_TYPE_F0) { count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; - target_reg = 1; - source_reg = 0; - } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) { + } else if (sl->flash_type == FLASH_TYPE_F4 || + sl->flash_type == FLASH_TYPE_L4 || + sl->flash_type == FLASH_TYPE_L0) { count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; @@ -2095,16 +2089,14 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons if (count % 2) ++count; } - target_reg = 1; - source_reg = 0; } else { fprintf(stderr, "unknown coreid 0x%x, don't know what flash loader to use\n", sl->core_id); return -1; } /* setup core */ - stlink_write_reg(sl, fl->buf_addr, source_reg); /* source */ - stlink_write_reg(sl, target, target_reg); /* target */ + stlink_write_reg(sl, fl->buf_addr, 0); /* source */ + stlink_write_reg(sl, target, 1); /* target */ stlink_write_reg(sl, count, 2); /* count */ stlink_write_reg(sl, 0, 3); /* flash bank 0 (input), only used on F0, but armless fopr others */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ From e43a737c3c9ffe56045181b306509c942fd9998a Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Mon, 14 Mar 2016 14:22:54 +0100 Subject: [PATCH 0375/1435] stlink-common: Update STM32L0/1 loaders to return remaining count in r2 All the loaders returns remaining work count in r2, except stm32l0/1. Make these loaders behaving as the others to simplify run_flash_loader() code. Signed-off-by: Maxime Coquelin --- flashloaders/stm32l0x.s | 12 +++++------- flashloaders/stm32lx.s | 12 +++++------- src/stlink-common.c | 30 ++++++++++-------------------- 3 files changed, 20 insertions(+), 34 deletions(-) diff --git a/flashloaders/stm32l0x.s b/flashloaders/stm32l0x.s index 6c863c64a..fcbd06e39 100644 --- a/flashloaders/stm32l0x.s +++ b/flashloaders/stm32l0x.s @@ -39,26 +39,24 @@ r2 - count */ - // Set 0 to r3 - movs r3, #0 // Go to compare - b.n test_done + b test_done write_word: // Load one word from address in r0, increment by 4 ldr r4, [r0] // Store the word to address in r1, increment by 4 str r4, [r1] - // Increment r3 - adds r3, #1 + // Decrement r2 + subs r2, #1 adds r1, #4 // does not matter, only first addr is important // next 15 bytes are in sequnce RM0367 page 66 adds r0, #4 test_done: - // Compare r3 and r2 - cmp r3, r2 + // Test r2 + cmp r2, #0 // Loop if not zero bcc.n write_word diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s index 764594d9c..bb8f7c93f 100644 --- a/flashloaders/stm32lx.s +++ b/flashloaders/stm32lx.s @@ -39,22 +39,20 @@ r2 - count */ - // Set 0 to r3 - movs r3, #0 // Go to compare - b.n test_done + b test_done write_word: // Load one word from address in r0, increment by 4 ldr.w ip, [r0], #4 // Store the word to address in r1, increment by 4 str.w ip, [r1], #4 - // Increment r3 - adds r3, #1 + // Decrement r2 + subs r2, #1 test_done: - // Compare r3 and r2 - cmp r3, r2 + // Test r2 + cmp r2, #0 // Loop if not zero bcc.n write_word diff --git a/src/stlink-common.c b/src/stlink-common.c index 01ce06c6f..dce100daa 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1504,17 +1504,16 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { r0, input, source addr r1, input, dest addr r2, input, word count - r3, output, word count + r2, output, remaining word count */ - 0x00, 0x23, 0x04, 0xe0, 0x50, 0xf8, 0x04, 0xcb, 0x41, 0xf8, 0x04, 0xcb, - 0x01, 0x33, + 0x01, 0x3a, - 0x93, 0x42, + 0x00, 0x2a, 0xf8, 0xd3, 0x00, 0xbe }; @@ -1525,19 +1524,18 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { r0, input, source addr r1, input, dest addr r2, input, word count - r3, output, word count + r2, output, remaining word count */ - 0x00, 0x23, 0x04, 0xe0, 0x04, 0x68, 0x0c, 0x60, - 0x01, 0x33, + 0x01, 0x3a, 0x04, 0x31, 0x04, 0x30, - 0x93, 0x42, + 0x00, 0x2a, 0xf8, 0xd3, 0x00, 0xbe }; @@ -2117,19 +2115,11 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - stlink_read_all_regs(sl, &rr); - /* check written byte count */ - if (sl->flash_type == FLASH_TYPE_L0) { - if (rr.r[3] != count) { - fprintf(stderr, "write error, count == %u\n", rr.r[3]); - return -1; - } - } else { - if (rr.r[2] != 0) { - fprintf(stderr, "write error, count == %u\n", rr.r[2]); - return -1; - } + stlink_read_all_regs(sl, &rr); + if (rr.r[2] != 0) { + fprintf(stderr, "write error, count == %u\n", rr.r[2]); + return -1; } return 0; From d0458ee7564e99253c8a35d8b1ceba33e23e248f Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Mon, 14 Mar 2016 14:53:32 +0100 Subject: [PATCH 0376/1435] stlink-common: Fix STM32L4 loader write count to reflect 64bits granularity The stm32l4 loader expects a count of 32 bits words while its granularity is really 64 bits. This patch fixes this to simplify count calculation in run_flash_loader(). Signed-off-by: Maxime Coquelin --- flashloaders/stm32l4.s | 2 +- src/stlink-common.c | 16 +++++++--------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/flashloaders/stm32l4.s b/flashloaders/stm32l4.s index 4b908633d..6aa2be050 100644 --- a/flashloaders/stm32l4.s +++ b/flashloaders/stm32l4.s @@ -28,7 +28,7 @@ wait: add r0, #8 add r1, #8 - sub r2, #2 + sub r2, #1 b next done: bkpt diff --git a/src/stlink-common.c b/src/stlink-common.c index dce100daa..76413b4fd 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1598,7 +1598,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0xfb, 0xd1, // bne.n 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8 - 0xa2, 0xf1, 0x02, 0x02, // add.w r2, r2, #2 + 0xa2, 0xf1, 0x01, 0x02, // sub.w r2, r2, #1 0xef, 0xe7, // b.n 0x00, 0xbe, // done: bkpt 0x0000 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000 @@ -2077,16 +2077,14 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; - } else if (sl->flash_type == FLASH_TYPE_F4 || - sl->flash_type == FLASH_TYPE_L4 || - sl->flash_type == FLASH_TYPE_L0) { + } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L0) { count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; - if (sl->chip_id == STM32_CHIPID_L4) { - if (count % 2) - ++count; - } + } else if (sl->flash_type == FLASH_TYPE_L4) { + count = size / sizeof(uint64_t); + if (size % sizeof(uint64_t)) + ++count; } else { fprintf(stderr, "unknown coreid 0x%x, don't know what flash loader to use\n", sl->core_id); return -1; @@ -2116,7 +2114,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } /* check written byte count */ - stlink_read_all_regs(sl, &rr); + stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { fprintf(stderr, "write error, count == %u\n", rr.r[2]); return -1; From faa19b5280ba9f5bd0ffede853a300157a116954 Mon Sep 17 00:00:00 2001 From: Maxime Coquelin Date: Mon, 14 Mar 2016 15:09:22 +0100 Subject: [PATCH 0377/1435] stlink-common: Ensure flash type is properly declared in device params Signed-off-by: Maxime Coquelin --- src/stlink-common.c | 11 +++++++---- src/stlink-common.h | 1 + 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 76413b4fd..a1ccdfdcc 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -591,6 +591,12 @@ int stlink_load_device_params(stlink_t *sl) { return -1; } + if (params->flash_type == FLASH_TYPE_UNKNOWN) { + WLOG("Invalid flash type, please check device declaration\n"); + return -1; + } + + // These are fixed... sl->flash_base = STM32_FLASH_BASE; sl->sram_base = STM32_SRAM_BASE; @@ -2063,7 +2069,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons reg rr; int i = 0; - size_t count; + size_t count = 0; DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); // FIXME This can never return -1 @@ -2085,9 +2091,6 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons count = size / sizeof(uint64_t); if (size % sizeof(uint64_t)) ++count; - } else { - fprintf(stderr, "unknown coreid 0x%x, don't know what flash loader to use\n", sl->core_id); - return -1; } /* setup core */ diff --git a/src/stlink-common.h b/src/stlink-common.h index e7be10ff0..448d01a56 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -167,6 +167,7 @@ extern "C" { #define C_BUF_LEN 32 enum flash_type { + FLASH_TYPE_UNKNOWN = 0, FLASH_TYPE_F0, FLASH_TYPE_L0, FLASH_TYPE_F4, From 1611f5ea86513c4a866732a36ee9a80850d08f67 Mon Sep 17 00:00:00 2001 From: "fabien.lementec" Date: Wed, 16 Mar 2016 11:33:57 +0100 Subject: [PATCH 0378/1435] fix: stlink_version return code --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index a1ccdfdcc..ecd3eb4ef 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -708,7 +708,7 @@ int stlink_version(stlink_t *sl) { DLOG(" notice: the firmware doesn't support a swim interface\n"); } - return -1; + return 0; } int stlink_target_voltage(stlink_t *sl) { From 03024048eb089f0e909788fd52c1684c956f1938 Mon Sep 17 00:00:00 2001 From: texane Date: Wed, 16 Mar 2016 20:27:37 +0100 Subject: [PATCH 0379/1435] fix: chip_id now a pointer, dereference --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index ecd3eb4ef..47148614b 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -534,7 +534,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { if (ret == -1) return ret; - if (chip_id == 0) + if (*chip_id == 0) ret = stlink_read_debug32(sl, 0x40015800, chip_id); //Try Corex M0 DBGMCU_IDCODE register address return ret; From 8a190733a2fb6e70b7956c64f04ab258967d0798 Mon Sep 17 00:00:00 2001 From: texane Date: Thu, 17 Mar 2016 19:27:14 +0100 Subject: [PATCH 0380/1435] fix: FLASH_F4_CR_LOCK --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 47148614b..4ad86f8ef 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -251,7 +251,7 @@ static void lock_flash(stlink_t *sl) { if (sl->flash_type == FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; + cr_lock_shift = FLASH_F4_CR_LOCK; } else if (sl->flash_type == FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; From b05f7008e49fca23765e1b54c2741af15ad65446 Mon Sep 17 00:00:00 2001 From: Sergey Alirzaev Date: Sun, 20 Mar 2016 05:28:07 +0300 Subject: [PATCH 0381/1435] avoid reading from NULL --- src/stlink-usb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 8e52c6801..b0ee00bed 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -720,8 +720,8 @@ stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { sl = malloc(sizeof (stlink_t)); slu = malloc(sizeof (struct stlink_libusb)); - if (sl == NULL) goto on_error; - if (slu == NULL) goto on_error; + if (sl == NULL) goto on_malloc_error; + if (slu == NULL) goto on_malloc_error; memset(sl, 0, sizeof (stlink_t)); memset(slu, 0, sizeof (struct stlink_libusb)); @@ -867,6 +867,7 @@ stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { on_error: if( slu->libusb_ctx) libusb_exit(slu->libusb_ctx); +on_malloc_error: if (sl != NULL) free(sl); if (slu != NULL) free(slu); return NULL; From 85abb8c056877c773b7d1184ca77c4b40d0393bc Mon Sep 17 00:00:00 2001 From: Tobias Badertscher Date: Sat, 2 Apr 2016 15:19:27 +0200 Subject: [PATCH 0382/1435] Proper writing of page 0 of second bank for stm32l476xe. --- src/stlink-common.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 4ad86f8ef..6d126d320 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -1197,7 +1197,7 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { flashaddr -= STM32_FLASH_BASE; if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) { uint32_t banksize = sl->flash_size / 2; - if (flashaddr > banksize) { + if (flashaddr >= banksize) { flashaddr -= banksize; bker = 0x100; } @@ -1248,19 +1248,21 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); + fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, stlink_calculate_pagesize(sl, flashaddr)); + write_flash_cr_bker_pnb(sl, page); } else if (sl->chip_id == STM32_CHIPID_F7) { // calculate the actual page from the address uint32_t sector=calculate_F7_sectornum(flashaddr); - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_snb(sl, sector); } else { // calculate the actual page from the address uint32_t sector=calculate_F4_sectornum(flashaddr); - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x\n", sector, stlink_calculate_pagesize(sl, flashaddr)); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices... if (sector >= 12) sector += 4; @@ -1390,7 +1392,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr); return -1; } - fprintf(stdout,"\rFlash page at %5d/%5d erased", i, num_pages); + fprintf(stdout,"-> Flash page at %5d/%5d erased\n", i, num_pages); fflush(stdout); } fprintf(stdout, "\n"); From b0251b9956e33059b3677dc48e7c0a5986595be0 Mon Sep 17 00:00:00 2001 From: Tobias Badertscher Date: Sat, 2 Apr 2016 18:18:39 +0200 Subject: [PATCH 0383/1435] Trace the read data in stlink_read_debug32 and not the address of the variable. --- src/stlink-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 6d126d320..3a6e260d1 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -732,7 +732,7 @@ int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { ret = sl->backend->read_debug32(sl, addr, data); if (!ret) - DLOG("*** stlink_read_debug32 %x is %#x\n", data, addr); + DLOG("*** stlink_read_debug32 %x is %#x\n", *data, addr); return ret; } From 89711265a59fce69a236dc4cb2ebc7b6557a08f4 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Wed, 6 Apr 2016 14:35:57 +0200 Subject: [PATCH 0384/1435] st-probe: Initial working stlink_probe_* API and CLI tool --- AUTHORS | 1 + CMakeLists.txt | 5 +- Makefile.am | 8 ++-- src/st-probe.c | 45 +++++++++++++++++ src/stlink-common.h | 2 + src/stlink-usb.c | 114 ++++++++++++++++++++++++++++++++++++++++---- src/stlink-usb.h | 3 +- 7 files changed, 164 insertions(+), 14 deletions(-) create mode 100644 src/st-probe.c diff --git a/AUTHORS b/AUTHORS index 5c52c64f3..aae9e2963 100644 --- a/AUTHORS +++ b/AUTHORS @@ -16,3 +16,4 @@ marpe@mimuw.edu.pl marco.cassinerio@gmail.com jserv@0xlab.org michael@pratt.im +jerry.jacobs@xor-gate.org diff --git a/CMakeLists.txt b/CMakeLists.txt index 6f5be17ff..247e515a9 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -41,7 +41,10 @@ target_link_libraries(st-util stlink) add_executable(st-info src/st-info.c) target_link_libraries(st-info stlink) -install(TARGETS stlink st-flash st-util st-info +add_executable(st-probe src/st-probe.c) +target_link_libraries(st-probe stlink) + +install(TARGETS stlink st-flash st-util st-info st-probe RUNTIME DESTINATION bin ARCHIVE DESTINATION lib) diff --git a/Makefile.am b/Makefile.am index 2ddbf475d..9a0b387e2 100644 --- a/Makefile.am +++ b/Makefile.am @@ -5,9 +5,9 @@ SUBDIRS = . $(MAYBE_GUI) AUTOMAKE_OPTIONS = subdir-objects if MINGW -bin_PROGRAMS = st-flash st-util st-info +bin_PROGRAMS = st-flash st-util st-info st-probe else -bin_PROGRAMS = st-flash st-util st-term st-info +bin_PROGRAMS = st-flash st-util st-term st-info st-probe endif noinst_LIBRARIES = libstlink.a @@ -15,6 +15,7 @@ noinst_LIBRARIES = libstlink.a st_flash_SOURCES = flash/main.c st_term_SOURCES = src/st-term.c st_info_SOURCES = src/st-info.c +st_probe_SOURCES = src/st-probe.c st_util_SOURCES = gdbserver/gdb-remote.c gdbserver/gdb-remote.h gdbserver/gdb-server.c mingw/mingw.c mingw/mingw.h CFILES = \ @@ -52,6 +53,7 @@ st_term_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(t st_info_LDADD = libstlink.a st_info_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_srcdir)/mingw +st_probe_LDADD = libstlink.a +st_probe_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_srcdir)/mingw EXTRA_DIST = autogen.sh - diff --git a/src/st-probe.c b/src/st-probe.c new file mode 100644 index 000000000..f5cf3d829 --- /dev/null +++ b/src/st-probe.c @@ -0,0 +1,45 @@ +#include +#include +#include +#include +#include "stlink-common.h" + +void stlink_print_info(stlink_t *sl) +{ + const chip_params_t *params = NULL; + + for (size_t n = 0; n < sizeof(sl->serial); n++) + printf("%02x", sl->serial[n]); + printf("\n"); + + printf("\t flash: %zu (pagesize: %zu)\n", sl->flash_size, sl->flash_pgsz); + printf("\t sram: %zu\n", sl->sram_size); + printf("\tchipid: 0x%.4x\n", sl->chip_id); + + for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { + if(devices[i].chip_id == sl->chip_id) { + params = &devices[i]; + break; + } + } + + if (params) + printf("\t descr: %s\n", params->description); +} + +int main(void) +{ + stlink_t **stdevs; + size_t size; + + size = stlink_probe_usb(&stdevs); + + printf("Found %zu stlink programmers\n", size); + + for (size_t n = 0; n < size; n++) + stlink_print_info(stdevs[n]); + + stlink_probe_usb_free(&stdevs, size); + + return EXIT_SUCCESS; +} diff --git a/src/stlink-common.h b/src/stlink-common.h index 448d01a56..2b2d09b1a 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -641,6 +641,8 @@ extern "C" { uint32_t chip_id; int core_stat; + char serial[13]; + #define STM32_FLASH_PGSZ 1024 #define STM32L_FLASH_PGSZ 256 diff --git a/src/stlink-usb.c b/src/stlink-usb.c index b0ee00bed..ab555785c 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -363,7 +363,7 @@ int _stlink_usb_reset(stlink_t * sl) { return size; } - return 0; + return 0; } @@ -718,12 +718,10 @@ stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { int error = -1; int config; - sl = malloc(sizeof (stlink_t)); - slu = malloc(sizeof (struct stlink_libusb)); + sl = calloc(1, sizeof (stlink_t)); + slu = calloc(1, sizeof (struct stlink_libusb)); if (sl == NULL) goto on_malloc_error; if (slu == NULL) goto on_malloc_error; - memset(sl, 0, sizeof (stlink_t)); - memset(slu, 0, sizeof (struct stlink_libusb)); ugly_init(verbose); sl->backend = &_stlink_usb_backend; @@ -760,12 +758,11 @@ stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { if ((libusb_get_bus_number(list[cnt])!=devBus) || (libusb_get_device_address(list[cnt])!=devAddr)) continue; if ( (desc.idProduct == USB_STLINK_32L_PID) || (desc.idProduct == USB_STLINK_NUCLEO_PID) ){ if ((p_usb_iserial != NULL)){ - unsigned char buffer[13]; struct libusb_device_handle* handle; libusb_open(list[cnt], &handle); - libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, buffer, 13); + libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)sl->serial, sizeof(sl->serial)); libusb_close(handle); - if (memcmp(p_usb_iserial,&buffer,12) == 0){ + if (memcmp(p_usb_iserial,&sl->serial, sizeof(sl->serial) - 1) == 0){ break; }else{ continue; @@ -787,7 +784,7 @@ stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { int error = libusb_open(list[cnt], &slu->usb_handle); if( error !=0 ) { WLOG("Error %d (%s) opening ST-Link/V2 device %03d:%03d\n", - error, strerror (errno), libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); + error, strerror (errno), libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); goto on_error; } } @@ -873,3 +870,102 @@ stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { return NULL; } +static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { + stlink_t **_sldevs; + libusb_device *dev; + int i = 0; + size_t slcnt = 0; + size_t slcur = 0; + + /* Count stlink */ + while ((dev = devs[i++]) != NULL) { + struct libusb_device_descriptor desc; + int r = libusb_get_device_descriptor(dev, &desc); + if (r < 0) { + fprintf(stderr, "failed to get device descriptor"); + break; + } + + if (desc.idProduct != USB_STLINK_32L_PID && + desc.idProduct != USB_STLINK_NUCLEO_PID) + continue; + + slcnt++; + } + + /* Allocate list of pointers */ + _sldevs = calloc(slcnt, sizeof(stlink_t *)); + if (!_sldevs) { + *sldevs = NULL; + return 0; + } + + /* Open stlinks and attach to list */ + i = 0; + while ((dev = devs[i++]) != NULL) { + struct libusb_device_descriptor desc; + int r = libusb_get_device_descriptor(dev, &desc); + if (r < 0) { + fprintf(stderr, "failed to get device descriptor"); + break; + } + + if (desc.idProduct != USB_STLINK_32L_PID && + desc.idProduct != USB_STLINK_NUCLEO_PID) + continue; + + struct libusb_device_handle* handle; + char serial[13]; + memset(serial, 0, sizeof(serial)); + + libusb_open(dev, &handle); + libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)&serial, sizeof(serial)); + libusb_close(handle); + + stlink_t *sl = NULL; + sl = stlink_open_usb(0, 1, serial); + if (!sl) + continue; + + _sldevs[slcur] = sl; + slcur++; + } + + *sldevs = _sldevs; + return slcnt; +} + +size_t stlink_probe_usb(stlink_t **stdevs[]) { + libusb_device **devs; + stlink_t **sldevs; + + size_t slcnt = 0; + int r; + ssize_t cnt; + + r = libusb_init(NULL); + if (r < 0) + return 0; + + cnt = libusb_get_device_list(NULL, &devs); + if (cnt < 0) + return 0; + + slcnt = stlink_probe_usb_devs(devs, &sldevs); + libusb_free_device_list(devs, 1); + + libusb_exit(NULL); + + *stdevs = sldevs; + return slcnt; +} + +void stlink_probe_usb_free(stlink_t ***stdevs, size_t size) { + if (stdevs == NULL || *stdevs == NULL || size == 0) + return; + + for (size_t n = 0; n < size; n++) + stlink_close((*stdevs)[n]); + free(*stdevs); + *stdevs = NULL; +} diff --git a/src/stlink-usb.h b/src/stlink-usb.h index 938c07bcb..801cafad3 100644 --- a/src/stlink-usb.h +++ b/src/stlink-usb.h @@ -29,7 +29,8 @@ extern "C" { }; stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial); - + size_t stlink_probe_usb(stlink_t **stdevs[]); + void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); #ifdef __cplusplus } From ca08bed617efc86a7765554c14a448b731f97eb3 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 7 Apr 2016 10:01:20 +0200 Subject: [PATCH 0385/1435] travis: Initial continues integration build on linux and osx * Fixup README to render HTML from Markdown * Fixup CMakeLists.txt to have a lower working minimum version * Add .travis.yml and .travis.sh for autobuild --- .travis.sh | 12 ++++++ .travis.yml | 12 ++++++ CMakeLists.txt | 2 +- README | 108 ++++++++++++++++++++++++++++++------------------- README.md | 1 + 5 files changed, 93 insertions(+), 42 deletions(-) create mode 100755 .travis.sh create mode 100644 .travis.yml create mode 120000 README.md diff --git a/.travis.sh b/.travis.sh new file mode 100755 index 000000000..cefeed142 --- /dev/null +++ b/.travis.sh @@ -0,0 +1,12 @@ +#!/bin/bash +if [ "$TRAVIS_OS_NAME" != "osx" ]; then + sudo apt-get update -qq || true + sudo apt-get install -qq -y --no-install-recommends libusb-1.0.0-dev +else + brew install libusb +fi + +mkdir build +cd build +cmake .. +make diff --git a/.travis.yml b/.travis.yml new file mode 100644 index 000000000..b175bb670 --- /dev/null +++ b/.travis.yml @@ -0,0 +1,12 @@ +sudo: true +language: c +script: + - ./.travis.sh +matrix: + include: + - os: osx + compiler: clang + - os: linux + compiler: gcc + - os: linux + compiler: clang diff --git a/CMakeLists.txt b/CMakeLists.txt index 247e515a9..e00d1ed28 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 2.8.11) +cmake_minimum_required(VERSION 2.8.7) project(stlink) find_package(PkgConfig) diff --git a/README b/README index 1f9d33cdd..986de7002 100644 --- a/README +++ b/README @@ -1,54 +1,72 @@ -HOWTO -===== +STMicroelectronics Stlink Tools +=============================== + +[![Build Status](https://travis-ci.org/xor-gate/stlink.svg?branch=travis)](https://travis-ci.org/xor-gate/stlink) + +## HOWTO First, you have to know there are several boards supported by the software. Those boards use a chip to translate from USB to JTAG commands. The chip is called stlink and there are 2 versions: -. STLINKv1, present on STM32VL discovery kits, -. STLINKv2, present on STM32L discovery and later kits. -2 different transport layers are used: -. STLINKv1 uses SCSI passthru commands over USB, -. STLINKv2 uses raw USB commands. +* STLINKv1, present on STM32VL discovery kits, +* STLINKv2, present on STM32L discovery and later kits. + +Two different transport layers are used: -Common requirements -~~~~~~~~~~~~~~~~~~~ +* STLINKv1 uses SCSI passthru commands over USB +* STLINKv2 uses raw USB commands. + +## Common requirements . libusb-1.0 (You probably already have this, but you'll need the development version to compile) . pkg-config -IF YOU HAVE AN STLINKv1 -~~~~~~~~~~~~~~~~~~~~~~~ +## For STLINKv1 + The STLINKv1's SCSI emulation is very broken, so the best thing to do is tell your operating system to completely ignore it. Options (do one of these before you plug it in) - *) modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i -or *)1. add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf - *)2. modprobe -r usb-storage && modprobe usb-storage -or *)1. cp stlink_v1.modprobe.conf /etc/modprobe.d - *)2. modprobe -r usb-storage && modprobe usb-storage -IF YOU HAVE AN STLINKv2 -~~~~~~~~~~~~~~~~~~~~~~~ +* `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` +* or *)1. add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf +* *)2. modprobe -r usb-storage && modprobe usb-storage +* or *)1. cp stlink_v1.modprobe.conf /etc/modprobe.d +* *)2. modprobe -r usb-storage && modprobe usb-storage + +## For STLINKv2 You're ready to go :) -COMPILING -~~~~~~~~~ +## Build from sources + +### Autotools + This project was converted to Autotools by a well meaning individual. The following steps will build the project for you. +``` $ ./autogen.sh $ ./configure $ make +``` + +### CMake + +``` +$ mkdir build && cd build +$ cmake .. +$ make +``` + +## Using the gdb server -USING THE GDBSERVER -~~~~~~~~~~~~~~~~~~~ To run the gdb server: (you do not need sudo if you have set up permissions correctly) +``` $ make && [sudo] ./st-util There are a few options: @@ -68,13 +86,15 @@ There are a few options: st-util will continue listening for connections after disconnect. -n, --no-reset Do not reset board on connection. +``` The STLINKv2 device to use can be specified in the environment -variable STLINK_DEVICE on the format :. +variable STLINK_DEVICE on the format `:`. Then, in your project directory, someting like this... (remember, you need to run an _ARM_ gdb, not an x86 gdb) +``` $ arm-none-eabi-gdb fancyblink.elf ... (gdb) tar extended-remote :4242 @@ -87,50 +107,56 @@ Transfer rate: 1 KB/sec, 560 bytes/write. (gdb) ... (gdb) continue +``` Have fun! -Resetting the chip from GDB -=========================== +## Resetting the chip from GDB You may reset the chip using GDB if you want. You'll need to use `target extended-remote' command like in this session: + +``` (gdb) target extended-remote localhost:4242 Remote debugging using localhost:4242 0x080007a8 in _startup () (gdb) kill Kill the program being debugged? (y or n) y (gdb) run -Starting program: /home/whitequark/ST/apps/bally/firmware.elf +Starting program: /home/whitequark/ST/apps/bally/firmware.elf +``` Remember that you can shorten the commands. `tar ext :4242' is good enough for GDB. -Setting up udev rules -===================== +## Setting up udev rules For convenience, you may install udev rules file, 49-stlinkv*.rules, located in the root of repository. You will need to copy it to /etc/udev/rules.d, and then either reboot or execute + +``` $ udevadm control --reload-rules $ udevadm trigger +``` Udev will now create a /dev/stlinkv2_XX or /dev/stlinkv1_XX file, with the appropriate permissions. This is currently all the device is for, (only one stlink of each version is supported at any time presently) -Running programs from SRAM -========================== +## Running programs from SRAM You can run your firmware directly from SRAM if you want to. Just link it at 0x20000000 and do + +``` (gdb) load firmware.elf +``` It will be loaded, and pc will be adjusted to point to start of the code, if it is linked correctly (i.e. ELF has correct entry point). -Writing to flash -================ +## Writing to flash The GDB stub ships with a correct memory map, including the flash area. If you would link your executable to 0x08000000 and then do @@ -138,8 +164,7 @@ If you would link your executable to 0x08000000 and then do then it would be written to the memory. -FAQ -=== +## FAQ Q: My breakpoints do not work at all or only work once. @@ -161,20 +186,21 @@ Q: Load command does not work in GDB. A: Some people report XML/EXPAT is not enabled by default when compiling GDB. Memory map parsing thus fail. Use --enable-expat. -Currently known working combinations of programmer and target -============================================================= +## Currently known working combinations of programmer and target STLink v1 (as found on the 32VL Discovery board) -Known Working Targets: +Known working targets: + * STM32F100xx (Medium Density VL) * STM32F103 (according to jpa- on ##stm32) No information: + * everything else! -STLink v2 (as found on the 32L and F4 Discovery boards) -Known Working Targets: +STLink v2 (as found on the 32L and F4 Discovery boards), known working targets: + * STM32F030F4P6 (custom board) * STM32F0Discovery (STM32F0 Discovery board) * STM32F100xx (Medium Density VL, as on the 32VL Discovery board) @@ -192,8 +218,8 @@ Known Working Targets: * STM32L152RB (STM32L-Discovery board, custom board) * STM32F051R8T6 (STM320518-EVAL board) -STLink v2-1 (as found on the Nucleo boards) -Known Working Targets: +STLink v2-1 (as found on the Nucleo boards), known working targets: + * STM32F401xx (STM32 Nucleo-F401RE board) * STM32F030R8T6 (STM32 Nucleo-F030R8 board) * STM32F072RBT6 (STM32 Nucleo-F072RB board) diff --git a/README.md b/README.md new file mode 120000 index 000000000..100b93820 --- /dev/null +++ b/README.md @@ -0,0 +1 @@ +README \ No newline at end of file From 32807fb95080f3e500d2dbd64e319cc33577a658 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 7 Apr 2016 11:58:16 +0200 Subject: [PATCH 0386/1435] cmake: Add -ggdb flag when CMAKE_BUILD_TYPE=Debug, add more usefull and stricter compiler flags when supported --- CMakeLists.txt | 68 ++++++++++++++++++++++++++++++++++++++------------ 1 file changed, 52 insertions(+), 16 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 247e515a9..cae6bd139 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,12 +1,48 @@ cmake_minimum_required(VERSION 2.8.11) -project(stlink) +project(stlink C) +include(CheckCCompilerFlag) find_package(PkgConfig) pkg_check_modules(libusb REQUIRED libusb-1.0) pkg_check_modules(gtk gtk+-3.0) -set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -std=gnu99 -Wall -Wextra") +function(add_cflag_if_supported flag) + string(REPLACE "-" "_" flagclean ${flag}) + string(REPLACE "=" "_" flagclean ${flagclean}) + string(REPLACE "+" "_" flagclean ${flagclean}) + string(REPLACE "," "_" flagclean ${flagclean}) + string(TOUPPER ${flagclean} flagclean) + + check_c_compiler_flag(${flag} C_SUPPORTS${flagclean}) + + if (C_SUPPORTS${flagclean}) + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${flag}" PARENT_SCOPE) + endif() +endfunction() + +add_cflag_if_supported("-std=gnu99") +add_cflag_if_supported("-Wall") +add_cflag_if_supported("-Wextra") +add_cflag_if_supported("-Wshadow") +add_cflag_if_supported("-D_FORTIFY_SOURCE=2") +add_cflag_if_supported("-fstrict-aliasing") +add_cflag_if_supported("-Wformat") +add_cflag_if_supported("-Wformat-security") +add_cflag_if_supported("-Wmaybe-uninitialized") +add_cflag_if_supported("-Wmissing-variable-declarations") +add_cflag_if_supported("-Wshorten-64-to-32") +add_cflag_if_supported("-Wimplicit-function-declaration") +add_cflag_if_supported("-Wredundant-decls") +add_cflag_if_supported("-Wundef") + +if(${CMAKE_BUILD_TYPE} MATCHES "Debug") + include(CTest) + add_cflag_if_supported("-ggdb") + add_cflag_if_supported("-O0") +elseif() + add_cflag_if_supported("-O2") +endif() set(HFILES src/stlink-common.h src/stlink-usb.h @@ -24,34 +60,35 @@ include_directories(${libusb_INCLUDE_DIRS}) include_directories(src) include_directories(mingw) -add_library(stlink STATIC +add_library(${PROJECT_NAME} STATIC ${HFILES} # header files for ide projects generated by cmake ${CFILES}) -target_link_libraries(stlink ${libusb_LDFLAGS}) +target_link_libraries(${PROJECT_NAME} ${libusb_LDFLAGS}) add_executable(st-flash flash/main.c) -target_link_libraries(st-flash stlink) +target_link_libraries(st-flash ${PROJECT_NAME}) + +add_executable(st-info src/st-info.c) +target_link_libraries(st-info ${PROJECT_NAME}) + +add_executable(st-probe src/st-probe.c) +target_link_libraries(st-probe ${PROJECT_NAME}) add_executable(st-util gdbserver/gdb-remote.c gdbserver/gdb-remote.h gdbserver/gdb-server.c gdbserver/gdb-server.h) -target_link_libraries(st-util stlink) +target_link_libraries(st-util ${PROJECT_NAME}) -add_executable(st-info src/st-info.c) -target_link_libraries(st-info stlink) - -add_executable(st-probe src/st-probe.c) -target_link_libraries(st-probe stlink) - -install(TARGETS stlink st-flash st-util st-info st-probe +install(TARGETS ${PROJECT_NAME} st-flash st-util st-info st-probe RUNTIME DESTINATION bin - ARCHIVE DESTINATION lib) + ARCHIVE DESTINATION lib +) if(NOT MINGW) list(APPEND CFILES src/st-term.c) add_executable(st-term src/st-term.c) - target_link_libraries(st-term stlink) + target_link_libraries(st-term ${PROJECT_NAME}) install(TARGETS st-term RUNTIME DESTINATION bin) @@ -78,4 +115,3 @@ if(gtk_FOUND) install(FILES gui/stlink-gui.ui DESTINATION ${INSTALLED_UI_DIR}) endif() - From 1c32fc05b672d318578efda59371d4a426185c51 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 7 Apr 2016 12:08:05 +0200 Subject: [PATCH 0387/1435] st-probe: Fix segfault when programmer is already busy and null pointers are in the list --- src/st-probe.c | 3 +++ src/stlink-common.c | 2 ++ src/stlink-usb.c | 3 +++ 3 files changed, 8 insertions(+) diff --git a/src/st-probe.c b/src/st-probe.c index f5cf3d829..b58bb7ad6 100644 --- a/src/st-probe.c +++ b/src/st-probe.c @@ -8,6 +8,9 @@ void stlink_print_info(stlink_t *sl) { const chip_params_t *params = NULL; + if (!sl) + return; + for (size_t n = 0; n < sizeof(sl->serial); n++) printf("%02x", sl->serial[n]); printf("\n"); diff --git a/src/stlink-common.c b/src/stlink-common.c index 3a6e260d1..18c76fb86 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -481,6 +481,8 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { void stlink_close(stlink_t *sl) { DLOG("*** stlink_close ***\n"); + if (!sl) + return; sl->backend->close(sl); free(sl); } diff --git a/src/stlink-usb.c b/src/stlink-usb.c index ab555785c..8fed467ba 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -15,6 +15,9 @@ enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; void _stlink_usb_close(stlink_t* sl) { + if (!sl) + return; + struct stlink_libusb * const handle = sl->backend_data; // maybe we couldn't even get the usb device? if (handle != NULL) { From 7db660511e5a0668f244f6a2bffd8a87277bdc12 Mon Sep 17 00:00:00 2001 From: Nikolay Date: Fri, 8 Apr 2016 03:12:48 +0300 Subject: [PATCH 0388/1435] Beautify + El Capitan confirmation --- stlinkv1_macosx_driver/README | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/stlinkv1_macosx_driver/README b/stlinkv1_macosx_driver/README index 0c789489c..b789d243a 100644 --- a/stlinkv1_macosx_driver/README +++ b/stlinkv1_macosx_driver/README @@ -17,21 +17,30 @@ Attached to this mail you'll find the osx folder with the source code of the dri invoke the install.sh. First, unpack the osx.tar.gz contents: +```bash tar xzvf osx.tar.gz +``` Then, install the driver using: +```bash sudo make osx_stlink_shield +``` no reboot required. P.S. If error `OS X version not supported` occurs. For the latest versions of Mac OS X you may need to change the `osx/install.sh` as follows: -``` +```bash < ISOSXLION=$(sw_vers -productVersion) --- > ISOSXLION=$(sw_vers -productVersion | sed -e 's:.[[:digit:]]*$::') ``` + FOR OS X 10.10 Yosemite you must force the system to load unsigned kernelextensions +```bash sudo nvram boot-args="kext-dev-mode=1“ +``` reboot the system! + +(Update from another user) FOR OS X 10.11 El Capitan: the Yosemite kext works for my 10.11.4. From 438eafffd51bc90ec433a95db8edfdd2be137e0d Mon Sep 17 00:00:00 2001 From: Nikolay Date: Fri, 8 Apr 2016 03:16:59 +0300 Subject: [PATCH 0389/1435] renaming the README file to README.md --- stlinkv1_macosx_driver/{README => README.md} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename stlinkv1_macosx_driver/{README => README.md} (100%) diff --git a/stlinkv1_macosx_driver/README b/stlinkv1_macosx_driver/README.md similarity index 100% rename from stlinkv1_macosx_driver/README rename to stlinkv1_macosx_driver/README.md From 217e854010fde251321d907c0f4a3d48c1d68f87 Mon Sep 17 00:00:00 2001 From: Nikolay Date: Fri, 8 Apr 2016 03:26:30 +0300 Subject: [PATCH 0390/1435] driver README minor edits --- stlinkv1_macosx_driver/README.md | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/stlinkv1_macosx_driver/README.md b/stlinkv1_macosx_driver/README.md index b789d243a..4e6b8c6a0 100644 --- a/stlinkv1_macosx_driver/README.md +++ b/stlinkv1_macosx_driver/README.md @@ -1,4 +1,5 @@ from: marco.cassinerio@gmail.com + to: texane@gmail.com Hi, @@ -14,9 +15,9 @@ version as well. Attached to this mail you'll find the osx folder with the source code of the driver, both drivers (for 10.6.x and 10.7.x), an install.sh script and the modified Makefile, i only added a line at the end which -invoke the install.sh. +invoke the `install.sh`. -First, unpack the osx.tar.gz contents: +First, unpack the `osx.tar.gz` contents: ```bash tar xzvf osx.tar.gz ``` @@ -35,7 +36,9 @@ P.S. If error `OS X version not supported` occurs. For the latest versions of Ma > ISOSXLION=$(sw_vers -productVersion | sed -e 's:.[[:digit:]]*$::') ``` -FOR OS X 10.10 Yosemite you must force the system to load unsigned kernelextensions +### OS X 10.10 Yosemite + +For OS X 10.10 Yosemite you must force the system to load unsigned kernelextensions ```bash sudo nvram boot-args="kext-dev-mode=1“ @@ -43,4 +46,8 @@ sudo nvram boot-args="kext-dev-mode=1“ reboot the system! -(Update from another user) FOR OS X 10.11 El Capitan: the Yosemite kext works for my 10.11.4. +### OS X 10.11 El Capitan + +(Update from another user) + +For OS X 10.11 El Capitan: the Yosemite kext seems to work (tested on 10.11.04). From 2e1204175e1bbe932ce4d9962d62b8adf18aad42 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 15 Apr 2016 15:53:35 +0200 Subject: [PATCH 0391/1435] Add -fPIC compiler flag, remove st-info from libstlink.a which is already specified by the st-info tool --- CMakeLists.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 0c9e75ea7..659218f74 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -35,6 +35,7 @@ add_cflag_if_supported("-Wshorten-64-to-32") add_cflag_if_supported("-Wimplicit-function-declaration") add_cflag_if_supported("-Wredundant-decls") add_cflag_if_supported("-Wundef") +add_cflag_if_supported("-fPIC") if(${CMAKE_BUILD_TYPE} MATCHES "Debug") include(CTest) @@ -54,7 +55,7 @@ set(CFILES src/stlink-common.c src/stlink-usb.c src/stlink-sg.c src/uglylogging.c - src/st-info.c) + ) include_directories(${libusb_INCLUDE_DIRS}) include_directories(src) From a86d51b4699a07d4bfb0a2f1678b1f29c59530ec Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 15 Apr 2016 22:20:22 +0200 Subject: [PATCH 0392/1435] Fix hang when user has no libusb access because of plugdev under e.g linux. Add some better sanity checking when using libusb_open and cleanup accordingly. Fixes hang (debian 8, amd64, libusb 1.0.19): libusb: warning [add_to_flying_list] failed to arm first timerfd (errno 9) libusb: warning [libusb_close] internal signalling write failed, closing anyway --- src/stlink-usb.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 8fed467ba..36ac96872 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -877,6 +877,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { stlink_t **_sldevs; libusb_device *dev; int i = 0; + int ret = 0; size_t slcnt = 0; size_t slcur = 0; @@ -885,7 +886,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { struct libusb_device_descriptor desc; int r = libusb_get_device_descriptor(dev, &desc); if (r < 0) { - fprintf(stderr, "failed to get device descriptor"); + WLOG("failed to get libusb device descriptor\n"); break; } @@ -907,9 +908,9 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { i = 0; while ((dev = devs[i++]) != NULL) { struct libusb_device_descriptor desc; - int r = libusb_get_device_descriptor(dev, &desc); - if (r < 0) { - fprintf(stderr, "failed to get device descriptor"); + ret = libusb_get_device_descriptor(dev, &desc); + if (ret < 0) { + WLOG("failed to get libusb device descriptor\n"); break; } @@ -921,7 +922,11 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { char serial[13]; memset(serial, 0, sizeof(serial)); - libusb_open(dev, &handle); + ret = libusb_open(dev, &handle); + if (ret < 0) { + WLOG("failed to get libusb device descriptor\n"); + break; + } libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)&serial, sizeof(serial)); libusb_close(handle); @@ -934,6 +939,13 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { slcur++; } + /* Something went wrong */ + if (ret < 0) { + free(_sldevs); + *sldevs = NULL; + return 0; + } + *sldevs = _sldevs; return slcnt; } From db5f0297bf4840b85d37e3460e705f5344928a98 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 15 Apr 2016 23:09:45 +0200 Subject: [PATCH 0393/1435] * Merge st-probe tool into st-info * Fixup #318 serial print in stlink probe with trailing zeros * Refactor stlink-usb.h with some doxygen-style comments * Refactor some pieces of stlink_open_usb --- .gitignore | 1 + CMakeLists.txt | 5 +-- Makefile.am | 8 ++--- src/st-info.c | 63 +++++++++++++++++++++++++++++++------ src/st-probe.c | 48 ---------------------------- src/stlink-common.h | 3 +- src/stlink-usb.c | 76 ++++++++++++++++++++++++--------------------- src/stlink-usb.h | 27 +++++++++++----- src/uglylogging.h | 18 ++++++----- 9 files changed, 131 insertions(+), 118 deletions(-) delete mode 100644 src/st-probe.c diff --git a/.gitignore b/.gitignore index 090257037..1c8296454 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,4 @@ +build INSTALL Makefile.in aclocal.m4 diff --git a/CMakeLists.txt b/CMakeLists.txt index 659218f74..cd329bb18 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -72,16 +72,13 @@ target_link_libraries(st-flash ${PROJECT_NAME}) add_executable(st-info src/st-info.c) target_link_libraries(st-info ${PROJECT_NAME}) -add_executable(st-probe src/st-probe.c) -target_link_libraries(st-probe ${PROJECT_NAME}) - add_executable(st-util gdbserver/gdb-remote.c gdbserver/gdb-remote.h gdbserver/gdb-server.c gdbserver/gdb-server.h) target_link_libraries(st-util ${PROJECT_NAME}) -install(TARGETS ${PROJECT_NAME} st-flash st-util st-info st-probe +install(TARGETS ${PROJECT_NAME} st-flash st-util st-info RUNTIME DESTINATION bin ARCHIVE DESTINATION lib ) diff --git a/Makefile.am b/Makefile.am index 9a0b387e2..e8927bd4a 100644 --- a/Makefile.am +++ b/Makefile.am @@ -5,9 +5,9 @@ SUBDIRS = . $(MAYBE_GUI) AUTOMAKE_OPTIONS = subdir-objects if MINGW -bin_PROGRAMS = st-flash st-util st-info st-probe +bin_PROGRAMS = st-flash st-util st-info else -bin_PROGRAMS = st-flash st-util st-term st-info st-probe +bin_PROGRAMS = st-flash st-util st-term st-info endif noinst_LIBRARIES = libstlink.a @@ -15,15 +15,13 @@ noinst_LIBRARIES = libstlink.a st_flash_SOURCES = flash/main.c st_term_SOURCES = src/st-term.c st_info_SOURCES = src/st-info.c -st_probe_SOURCES = src/st-probe.c st_util_SOURCES = gdbserver/gdb-remote.c gdbserver/gdb-remote.h gdbserver/gdb-server.c mingw/mingw.c mingw/mingw.h CFILES = \ src/stlink-common.c \ src/stlink-usb.c \ src/stlink-sg.c \ - src/uglylogging.c \ - src/st-info.c + src/uglylogging.c if !MINGW CFILES += src/st-term.c diff --git a/src/st-info.c b/src/st-info.c index 66d9fb391..2cea40e5c 100644 --- a/src/st-info.c +++ b/src/st-info.c @@ -1,13 +1,9 @@ -/* simple wrapper around the stlink_flash_write function */ - -// TODO - this should be done as just a simple flag to the st-util command line... - - #include #include #include #include -#include "stlink-common.h" + +#include static void usage(void) { @@ -16,9 +12,52 @@ static void usage(void) puts("st-info --descr"); puts("st-info --pagesize"); puts("st-info --chipid"); + puts("st-info --serial"); + puts("st-info --probe"); +} + +static void stlink_print_info(stlink_t *sl) +{ + const chip_params_t *params = NULL; + + if (!sl) + return; + + for (int n = 0; n < sl->serial_size; n++) + printf("%02x", sl->serial[n]); + printf("\n"); + + printf("\t flash: %zu (pagesize: %zu)\n", sl->flash_size, sl->flash_pgsz); + printf("\t sram: %zu\n", sl->sram_size); + printf("\tchipid: 0x%.4x\n", sl->chip_id); + + for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { + if (devices[i].chip_id == sl->chip_id) { + params = &devices[i]; + break; + } + } + + if (params) + printf("\t descr: %s\n", params->description); +} + +static void stlink_probe(void) +{ + stlink_t **stdevs; + size_t size; + + size = stlink_probe_usb(&stdevs); + + printf("Found %zu stlink programmers\n", size); + + for (size_t n = 0; n < size; n++) + stlink_print_info(stdevs[n]); + + stlink_probe_usb_free(&stdevs, size); } -static int print_data(stlink_t* sl, char** av) +static int print_data(stlink_t *sl, char **av) { int ret = 0; if (strcmp(av[1], "--flash") == 0) @@ -29,7 +68,13 @@ static int print_data(stlink_t* sl, char** av) printf("0x%zx\n", sl->flash_pgsz); else if (strcmp(av[1], "--chipid") == 0) printf("0x%.4x\n", sl->chip_id); - else if (strcmp(av[1], "--descr")==0) { + else if (strcmp(av[1], "--probe") == 0) + stlink_probe(); + else if (strcmp(av[1], "--serial") == 0) { + for (int n = 0; n < sl->serial_size; n++) + printf("%02x", sl->serial[n]); + printf("\n"); + } else if (strcmp(av[1], "--descr") == 0) { const chip_params_t *params = NULL; for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { if(devices[i].chip_id == sl->chip_id) { @@ -51,7 +96,7 @@ stlink_t* open_sl(void) stlink_t* sl; sl = stlink_v1_open(0, 1); if (sl == NULL) - sl = stlink_open_usb(0, 1, NULL); + sl = stlink_open_usb(0, 1, NULL); return sl; } diff --git a/src/st-probe.c b/src/st-probe.c deleted file mode 100644 index b58bb7ad6..000000000 --- a/src/st-probe.c +++ /dev/null @@ -1,48 +0,0 @@ -#include -#include -#include -#include -#include "stlink-common.h" - -void stlink_print_info(stlink_t *sl) -{ - const chip_params_t *params = NULL; - - if (!sl) - return; - - for (size_t n = 0; n < sizeof(sl->serial); n++) - printf("%02x", sl->serial[n]); - printf("\n"); - - printf("\t flash: %zu (pagesize: %zu)\n", sl->flash_size, sl->flash_pgsz); - printf("\t sram: %zu\n", sl->sram_size); - printf("\tchipid: 0x%.4x\n", sl->chip_id); - - for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { - if(devices[i].chip_id == sl->chip_id) { - params = &devices[i]; - break; - } - } - - if (params) - printf("\t descr: %s\n", params->description); -} - -int main(void) -{ - stlink_t **stdevs; - size_t size; - - size = stlink_probe_usb(&stdevs); - - printf("Found %zu stlink programmers\n", size); - - for (size_t n = 0; n < size; n++) - stlink_print_info(stdevs[n]); - - stlink_probe_usb_free(&stdevs, size); - - return EXIT_SUCCESS; -} diff --git a/src/stlink-common.h b/src/stlink-common.h index 2b2d09b1a..e2f7b75c2 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -641,7 +641,8 @@ extern "C" { uint32_t chip_id; int core_stat; - char serial[13]; + char serial[16]; + int serial_size; #define STM32_FLASH_PGSZ 1024 #define STM32L_FLASH_PGSZ 256 diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 36ac96872..6125ec3fa 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -10,7 +10,6 @@ #include "stlink-common.h" #include "stlink-usb.h" -#include "uglylogging.h" enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; @@ -714,17 +713,19 @@ stlink_backend_t _stlink_usb_backend = { _stlink_usb_target_voltage }; - -stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16]) +{ stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; - int error = -1; + int ret = -1; int config; sl = calloc(1, sizeof (stlink_t)); slu = calloc(1, sizeof (struct stlink_libusb)); - if (sl == NULL) goto on_malloc_error; - if (slu == NULL) goto on_malloc_error; + if (sl == NULL) + goto on_malloc_error; + if (slu == NULL) + goto on_malloc_error; ugly_init(verbose); sl->backend = &_stlink_usb_backend; @@ -754,26 +755,32 @@ stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { devAddr=atoi(c); ILOG("bus %03d dev %03d\n",devBus, devAddr); } + while (cnt--){ libusb_get_device_descriptor( list[cnt], &desc ); - if (desc.idVendor!=USB_ST_VID) continue; + if (desc.idVendor != USB_ST_VID) + continue; + if (devBus && devAddr) - if ((libusb_get_bus_number(list[cnt])!=devBus) || (libusb_get_device_address(list[cnt])!=devAddr)) continue; - if ( (desc.idProduct == USB_STLINK_32L_PID) || (desc.idProduct == USB_STLINK_NUCLEO_PID) ){ - if ((p_usb_iserial != NULL)){ - struct libusb_device_handle* handle; + if ((libusb_get_bus_number(list[cnt])!=devBus) || (libusb_get_device_address(list[cnt])!=devAddr)) + continue; + + if ( (desc.idProduct == USB_STLINK_32L_PID) || (desc.idProduct == USB_STLINK_NUCLEO_PID) ) { + if ((serial != NULL)) { + struct libusb_device_handle *handle; + libusb_open(list[cnt], &handle); - libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)sl->serial, sizeof(sl->serial)); + sl->serial_size = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)sl->serial, sizeof(sl->serial)); libusb_close(handle); - if (memcmp(p_usb_iserial,&sl->serial, sizeof(sl->serial) - 1) == 0){ - break; - }else{ + if (sl->serial_size < 0) continue; - } - }else{ + else if (memcmp(serial, &sl->serial, sl->serial_size) == 0) + break; + } else { break; } } + if (desc.idProduct == USB_STLINK_PID) { slu->protocoll = 1; break; @@ -784,23 +791,20 @@ stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { WLOG ("Couldn't find %s ST-Link/V2 devices\n",(devBus && devAddr)?"matched":"any"); goto on_error; } else { - int error = libusb_open(list[cnt], &slu->usb_handle); - if( error !=0 ) { - WLOG("Error %d (%s) opening ST-Link/V2 device %03d:%03d\n", - error, strerror (errno), libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); + ret = libusb_open(list[cnt], &slu->usb_handle); + if (ret != 0) { + WLOG("Error %d (%s) opening ST-Link/V2 device %03d:%03d\n", + ret, strerror (errno), libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); goto on_error; } } libusb_free_device_list(list, 1); - if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { - int r; - - r = libusb_detach_kernel_driver(slu->usb_handle, 0); - if (r<0) { - WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); + ret = libusb_detach_kernel_driver(slu->usb_handle, 0); + if (ret < 0) { + WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-ret)); goto on_libusb_error; } } @@ -837,8 +841,6 @@ stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { // TODO - never used at the moment, always CMD_SIZE slu->cmd_len = (slu->protocoll == 1)? STLINK_SG_SIZE: STLINK_CMD_SIZE; - /* success */ - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { ILOG("-- exit_dfu_mode\n"); stlink_exit_dfu_mode(sl); @@ -852,24 +854,28 @@ stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial) { stlink_reset(sl); usleep(10000); } + stlink_version(sl); - error = stlink_load_device_params(sl); + ret = stlink_load_device_params(sl); on_libusb_error: - if (error == -1) { + if (ret == -1) { stlink_close(sl); return NULL; } - /* success */ return sl; on_error: - if( slu->libusb_ctx) + if (slu->libusb_ctx) libusb_exit(slu->libusb_ctx); + on_malloc_error: - if (sl != NULL) free(sl); - if (slu != NULL) free(slu); + if (sl != NULL) + free(sl); + if (slu != NULL) + free(slu); + return NULL; } diff --git a/src/stlink-usb.h b/src/stlink-usb.h index 801cafad3..747d54c74 100644 --- a/src/stlink-usb.h +++ b/src/stlink-usb.h @@ -6,14 +6,17 @@ */ #ifndef STLINK_USB_H -#define STLINK_USB_H - -#ifdef __cplusplus -extern "C" { -#endif +#define STLINK_USB_H +#include #include + #include "stlink-common.h" +#include "uglylogging.h" + +#ifdef __cplusplus +extern "C" { +#endif #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 @@ -28,13 +31,21 @@ extern "C" { unsigned int cmd_len; }; - stlink_t* stlink_open_usb(const int verbose, int reset, char *p_usb_iserial); + /** + * Open a stlink + * @param verbose Verbosity loglevel + * @param reset Reset stlink programmer + * @param serial Serial number to search for, when NULL the first stlink found is opened (binary format) + * @retval NULL Error while opening the stlink + * @retval !NULL Stlink found and ready to use + */ + stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16]); size_t stlink_probe_usb(stlink_t **stdevs[]); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); -#ifdef __cplusplus +#ifdef __cplusplus } #endif -#endif /* STLINK_USB_H */ +#endif /* STLINK_USB_H */ diff --git a/src/uglylogging.h b/src/uglylogging.h index 7099d919c..df816caed 100644 --- a/src/uglylogging.h +++ b/src/uglylogging.h @@ -9,14 +9,16 @@ extern "C" { #endif -#define UDEBUG 90 -#define UINFO 50 -#define UWARN 30 -#define UERROR 20 -#define UFATAL 10 - - int ugly_init(int maximum_threshold); - int ugly_log(int level, const char *tag, const char *format, ...); +enum ugly_loglevel { + UDEBUG = 90, + UINFO = 50, + UWARN = 30, + UERROR = 20, + UFATAL = 10 +}; + +int ugly_init(int maximum_threshold); +int ugly_log(int level, const char *tag, const char *format, ...); #define DLOG(format, args...) ugly_log(UDEBUG, __FILE__, format, ## args) #define ILOG(format, args...) ugly_log(UINFO, __FILE__, format, ## args) From 0e22df918ef58b06beebe9c0f73f38a3852c900b Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 15 Apr 2016 23:35:11 +0200 Subject: [PATCH 0394/1435] stlink_open_usb: Fix issue where serial is not cached when serial is not compared in search --- src/stlink-usb.c | 39 ++++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 6125ec3fa..f3f41e37a 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -756,31 +756,36 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 ILOG("bus %03d dev %03d\n",devBus, devAddr); } - while (cnt--){ + while (cnt--) { libusb_get_device_descriptor( list[cnt], &desc ); if (desc.idVendor != USB_ST_VID) continue; - if (devBus && devAddr) - if ((libusb_get_bus_number(list[cnt])!=devBus) || (libusb_get_device_address(list[cnt])!=devAddr)) + if (devBus && devAddr) { + if ((libusb_get_bus_number(list[cnt]) != devBus) + || (libusb_get_device_address(list[cnt]) != devAddr)) { continue; - - if ( (desc.idProduct == USB_STLINK_32L_PID) || (desc.idProduct == USB_STLINK_NUCLEO_PID) ) { - if ((serial != NULL)) { - struct libusb_device_handle *handle; - - libusb_open(list[cnt], &handle); - sl->serial_size = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)sl->serial, sizeof(sl->serial)); - libusb_close(handle); - if (sl->serial_size < 0) - continue; - else if (memcmp(serial, &sl->serial, sl->serial_size) == 0) - break; - } else { - break; } } + if ((desc.idProduct == USB_STLINK_32L_PID) || (desc.idProduct == USB_STLINK_NUCLEO_PID)) { + struct libusb_device_handle *handle; + + libusb_open(list[cnt], &handle); + sl->serial_size = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, + (unsigned char *)sl->serial, sizeof(sl->serial)); + libusb_close(handle); + + if (sl->serial_size < 0) + continue; + if (serial == NULL) + break; + if (memcmp(serial, &sl->serial, sl->serial_size) == 0) + break; + + continue; + } + if (desc.idProduct == USB_STLINK_PID) { slu->protocoll = 1; break; From a6b2f93661822b33de22aa533f09319850e352fe Mon Sep 17 00:00:00 2001 From: texane Date: Sun, 24 Apr 2016 09:25:51 +0200 Subject: [PATCH 0395/1435] Fix issue #399: Some Nucleo devices (L476RG) do not return a valid serial --- src/stlink-usb.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index f3f41e37a..24f976988 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -776,10 +776,12 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 (unsigned char *)sl->serial, sizeof(sl->serial)); libusb_close(handle); - if (sl->serial_size < 0) - continue; - if (serial == NULL) + if ((serial == NULL) || (*serial == 0)) break; + + if (sl->serial_size < 0) + continue; + if (memcmp(serial, &sl->serial, sl->serial_size) == 0) break; @@ -938,7 +940,9 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { WLOG("failed to get libusb device descriptor\n"); break; } - libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)&serial, sizeof(serial)); + ret = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)&serial, sizeof(serial)); + if (ret < 0) *serial = 0; + libusb_close(handle); stlink_t *sl = NULL; From 5d088bde8bae782949b3f35b39592f295f35890f Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 29 Apr 2016 09:44:22 +0200 Subject: [PATCH 0396/1435] st-info: Add support for OpenOCD hla_serial printing --- README | 2 +- src/st-info.c | 54 ++++++++++++++++++++++++++++++++++-------------- src/stlink-usb.c | 4 +++- 3 files changed, 43 insertions(+), 17 deletions(-) diff --git a/README b/README index d85fda7eb..e5a51cf5e 100644 --- a/README +++ b/README @@ -1,7 +1,7 @@ STMicroelectronics Stlink Tools =============================== -[![Build Status](https://travis-ci.org/xor-gate/stlink.svg?branch=travis)](https://travis-ci.org/xor-gate/stlink) +[![Build Status](https://travis-ci.org/texane/stlink.svg?branch=travis)](https://travis-ci.org/texane/stlink) ## HOWTO diff --git a/src/st-info.c b/src/st-info.c index 2cea40e5c..cf61bccbf 100644 --- a/src/st-info.c +++ b/src/st-info.c @@ -13,9 +13,30 @@ static void usage(void) puts("st-info --pagesize"); puts("st-info --chipid"); puts("st-info --serial"); + puts("st-info --hla-serial"); puts("st-info --probe"); } +/* Print normal or OpenOCD hla_serial with newline */ +static void stlink_print_serial(stlink_t *sl, bool openocd) +{ + const char *fmt; + + if (openocd) { + printf("\""); + fmt = "\\x%02x"; + } else { + fmt = "%02x"; + } + + for (int n = 0; n < sl->serial_size; n++) + printf(fmt, sl->serial[n]); + + if (openocd) + printf("\""); + printf("\n"); +} + static void stlink_print_info(stlink_t *sl) { const chip_params_t *params = NULL; @@ -23,13 +44,14 @@ static void stlink_print_info(stlink_t *sl) if (!sl) return; - for (int n = 0; n < sl->serial_size; n++) - printf("%02x", sl->serial[n]); - printf("\n"); + printf(" serial: "); + stlink_print_serial(sl, false); + printf("openocd: "); + stlink_print_serial(sl, true); - printf("\t flash: %zu (pagesize: %zu)\n", sl->flash_size, sl->flash_pgsz); - printf("\t sram: %zu\n", sl->sram_size); - printf("\tchipid: 0x%.4x\n", sl->chip_id); + printf(" flash: %zu (pagesize: %zu)\n", sl->flash_size, sl->flash_pgsz); + printf(" sram: %zu\n", sl->sram_size); + printf(" chipid: 0x%.4x\n", sl->chip_id); for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { if (devices[i].chip_id == sl->chip_id) { @@ -39,7 +61,7 @@ static void stlink_print_info(stlink_t *sl) } if (params) - printf("\t descr: %s\n", params->description); + printf(" descr: %s\n", params->description); } static void stlink_probe(void) @@ -59,7 +81,6 @@ static void stlink_probe(void) static int print_data(stlink_t *sl, char **av) { - int ret = 0; if (strcmp(av[1], "--flash") == 0) printf("0x%zx\n", sl->flash_size); else if (strcmp(av[1], "--sram") == 0) @@ -70,11 +91,11 @@ static int print_data(stlink_t *sl, char **av) printf("0x%.4x\n", sl->chip_id); else if (strcmp(av[1], "--probe") == 0) stlink_probe(); - else if (strcmp(av[1], "--serial") == 0) { - for (int n = 0; n < sl->serial_size; n++) - printf("%02x", sl->serial[n]); - printf("\n"); - } else if (strcmp(av[1], "--descr") == 0) { + else if (strcmp(av[1], "--serial") == 0) + stlink_print_serial(sl, false); + else if (strcmp(av[1], "--hla-serial") == 0) + stlink_print_serial(sl, true); + else if (strcmp(av[1], "--descr") == 0) { const chip_params_t *params = NULL; for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { if(devices[i].chip_id == sl->chip_id) { @@ -87,7 +108,8 @@ static int print_data(stlink_t *sl, char **av) } printf("%s\n", params->description); } - return ret; + + return 0; } @@ -115,7 +137,9 @@ int main(int ac, char** av) if (sl == NULL) { return -1; } - sl->verbose=0; + + sl->verbose = 0; + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) stlink_exit_dfu_mode(sl); diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 24f976988..e7e029880 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -940,8 +940,10 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { WLOG("failed to get libusb device descriptor\n"); break; } + ret = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)&serial, sizeof(serial)); - if (ret < 0) *serial = 0; + if (ret < 0) + *serial = NULL; libusb_close(handle); From ea6a858d955f7c1541440dbf1b4cc09aa573f917 Mon Sep 17 00:00:00 2001 From: texane Date: Sat, 30 Apr 2016 08:51:56 +0200 Subject: [PATCH 0397/1435] update README --- README | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README b/README index e5a51cf5e..b6a6de1e4 100644 --- a/README +++ b/README @@ -1,5 +1,5 @@ -STMicroelectronics Stlink Tools -=============================== +Open source version of the STMicroelectronics Stlink Tools +========================================================== [![Build Status](https://travis-ci.org/texane/stlink.svg?branch=travis)](https://travis-ci.org/texane/stlink) From c9fe1103bd2df3ee6724d4abd5e5647b0e97cf6a Mon Sep 17 00:00:00 2001 From: texane Date: Sun, 1 May 2016 09:03:10 +0200 Subject: [PATCH 0398/1435] fix: remove st_probe variables from automake --- Makefile.am | 3 --- 1 file changed, 3 deletions(-) diff --git a/Makefile.am b/Makefile.am index e8927bd4a..9afbc0f0b 100644 --- a/Makefile.am +++ b/Makefile.am @@ -51,7 +51,4 @@ st_term_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(t st_info_LDADD = libstlink.a st_info_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_srcdir)/mingw -st_probe_LDADD = libstlink.a -st_probe_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_srcdir)/mingw - EXTRA_DIST = autogen.sh From 25deee1055cdea42a4b28597f36e612bec77a2a1 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Mon, 2 May 2016 16:47:23 +0200 Subject: [PATCH 0399/1435] st-info: --probe: Due to already claimed stlink one of them was zero. Fixes #401. --- src/st-info.c | 78 +++++++++++++++++++++++++----------------------- src/stlink-usb.c | 4 +++ 2 files changed, 45 insertions(+), 37 deletions(-) diff --git a/src/st-info.c b/src/st-info.c index cf61bccbf..1671468f0 100644 --- a/src/st-info.c +++ b/src/st-info.c @@ -61,7 +61,7 @@ static void stlink_print_info(stlink_t *sl) } if (params) - printf(" descr: %s\n", params->description); + printf(" descr: %s\n", params->description); } static void stlink_probe(void) @@ -79,8 +79,40 @@ static void stlink_probe(void) stlink_probe_usb_free(&stdevs, size); } -static int print_data(stlink_t *sl, char **av) +static stlink_t *stlink_open_first(void) { + stlink_t* sl = NULL; + sl = stlink_v1_open(0, 1); + if (sl == NULL) + sl = stlink_open_usb(0, 1, NULL); + + return sl; +} + +static int print_data(char **av) +{ + stlink_t* sl = NULL; + + // Probe needs all devices unclaimed + if (strcmp(av[1], "--probe") == 0) { + stlink_probe(); + return 0; + } + + sl = stlink_open_first(); + + if (sl == NULL) { + return -1; + } + + sl->verbose = 0; + + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) + stlink_exit_dfu_mode(sl); + + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) + stlink_enter_swd_mode(sl); + if (strcmp(av[1], "--flash") == 0) printf("0x%zx\n", sl->flash_size); else if (strcmp(av[1], "--sram") == 0) @@ -89,8 +121,6 @@ static int print_data(stlink_t *sl, char **av) printf("0x%zx\n", sl->flash_pgsz); else if (strcmp(av[1], "--chipid") == 0) printf("0x%.4x\n", sl->chip_id); - else if (strcmp(av[1], "--probe") == 0) - stlink_probe(); else if (strcmp(av[1], "--serial") == 0) stlink_print_serial(sl, false); else if (strcmp(av[1], "--hla-serial") == 0) @@ -109,50 +139,24 @@ static int print_data(stlink_t *sl, char **av) printf("%s\n", params->description); } - return 0; -} - + if (sl) + { + stlink_exit_debug_mode(sl); + stlink_close(sl); + } -stlink_t* open_sl(void) -{ - stlink_t* sl; - sl = stlink_v1_open(0, 1); - if (sl == NULL) - sl = stlink_open_usb(0, 1, NULL); - return sl; + return 0; } - int main(int ac, char** av) { - stlink_t* sl = NULL; int err = -1; if (ac < 2) { usage(); return -1; } - sl = open_sl(); - - if (sl == NULL) { - return -1; - } - - sl->verbose = 0; - - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) - stlink_exit_dfu_mode(sl); - - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) - stlink_enter_swd_mode(sl); - - err = print_data(sl, av); - - if (sl != NULL) - { - stlink_exit_debug_mode(sl); - stlink_close(sl); - } + err = print_data(av); return err; } diff --git a/src/stlink-usb.c b/src/stlink-usb.c index e7e029880..4cdefd795 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -743,6 +743,10 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 int devBus =0; int devAddr=0; + /* @TODO: Reading a environment variable in a usb open function is not very nice, this + should be refactored and moved into the CLI tools, and instead of giving USB_BUS:USB_ADDR a real stlink + serial string should be passed to this function. Probably people are using this but this is very odd because + as programmer can change to multiple busses and it is better to detect them based on serial. */ char *device = getenv("STLINK_DEVICE"); if (device) { char *c = strchr(device,':'); From eae5157466e8fd2eb6508c5b5f34aa1d5fe373ea Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Mon, 2 May 2016 17:01:53 +0200 Subject: [PATCH 0400/1435] TravisCI: Add building with autotools, catches bugs early as seen by issue #403 --- .travis.sh | 14 ++++++++++---- .travis.yml | 12 ++++++++++++ README | 15 +++++++-------- 3 files changed, 29 insertions(+), 12 deletions(-) diff --git a/.travis.sh b/.travis.sh index cefeed142..6b69c638a 100755 --- a/.travis.sh +++ b/.travis.sh @@ -6,7 +6,13 @@ else brew install libusb fi -mkdir build -cd build -cmake .. -make +if [ "$BUILD_SYSTEM" == "cmake" ]; then + mkdir build + cd build + cmake .. + make +else + ./autogen.sh + ./configure + make +fi diff --git a/.travis.yml b/.travis.yml index b175bb670..5164d36c5 100644 --- a/.travis.yml +++ b/.travis.yml @@ -6,7 +6,19 @@ matrix: include: - os: osx compiler: clang + env: "BUILD_SYSTEM=cmake" + - os: osx + compiler: clang + env: "BUILD_SYSTEM=autotools" + - os: linux + compiler: gcc + env: "BUILD_SYSTEM=cmake" + - os: linux + compiler: clang + env: "BUILD_SYSTEM=cmake" - os: linux compiler: gcc + env: "BUILD_SYSTEM=autotools" - os: linux compiler: clang + env: "BUILD_SYSTEM=autotools" diff --git a/README b/README index b6a6de1e4..da7fafa32 100644 --- a/README +++ b/README @@ -1,7 +1,7 @@ Open source version of the STMicroelectronics Stlink Tools ========================================================== -[![Build Status](https://travis-ci.org/texane/stlink.svg?branch=travis)](https://travis-ci.org/texane/stlink) +[![Build Status](https://travis-ci.org/texane/stlink.svg?branch=master)](https://travis-ci.org/texane/stlink) ## HOWTO @@ -19,9 +19,8 @@ Two different transport layers are used: ## Common requirements -. libusb-1.0 (You probably already have this, but you'll need the -development version to compile) -. pkg-config +* `pkg-config` +* `libusb-1.0` (plus development headers for building, on debian based distros `libusb-1.0.0-dev` package) ## For STLINKv1 @@ -31,10 +30,10 @@ is tell your operating system to completely ignore it. Options (do one of these before you plug it in) * `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` -* or *)1. add "options usb-storage quirks=483:3744:i" to /etc/modprobe.conf -* *)2. modprobe -r usb-storage && modprobe usb-storage -* or *)1. cp stlink_v1.modprobe.conf /etc/modprobe.d -* *)2. modprobe -r usb-storage && modprobe usb-storage +* or 1. `echo "options usb-storage quirks=483:3744:i" >> /etc/modprobe.conf` +* 2. `modprobe -r usb-storage && modprobe usb-storage` +* or 1. `cp stlink_v1.modprobe.conf /etc/modprobe.d` +* 2. `modprobe -r usb-storage && modprobe usb-storage` ## For STLINKv2 From a9cfb5619c1df8d4ef1f54230227578819f82881 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Tue, 3 May 2016 21:08:19 +0200 Subject: [PATCH 0401/1435] Add github ISSUE_TEMPLATE.md --- .github/ISSUE_TEMPLATE.md | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 .github/ISSUE_TEMPLATE.md diff --git a/.github/ISSUE_TEMPLATE.md b/.github/ISSUE_TEMPLATE.md new file mode 100644 index 000000000..d06d402e5 --- /dev/null +++ b/.github/ISSUE_TEMPLATE.md @@ -0,0 +1,16 @@ +Thank you for giving feedback to the stlink project. Take some time to fill out + check boxes with a X in the following items so developers and other people can try to + to find out what is going on. And add/remove what is appropiate to your problem. + +When submitting a feature request, try to reuse the list and add/remove what is appropiate. + +- [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard +- [ ] Programmer firmware version: e.g STSW-LINK007 2.27.15 +- [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) +- [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 +- [ ] Target chip: e.g STM32F402VG + +A as-detailed description possible of the problem with debug output when available. + +Thanks you, +Stlink project maintainers From e653ca6cdf7f63dd70f748f970c1e0345bc19946 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Tue, 3 May 2016 21:09:21 +0200 Subject: [PATCH 0402/1435] ISSUE_TEMPLATE.md, fix typo --- .github/ISSUE_TEMPLATE.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/ISSUE_TEMPLATE.md b/.github/ISSUE_TEMPLATE.md index d06d402e5..861711912 100644 --- a/.github/ISSUE_TEMPLATE.md +++ b/.github/ISSUE_TEMPLATE.md @@ -12,5 +12,5 @@ When submitting a feature request, try to reuse the list and add/remove what is A as-detailed description possible of the problem with debug output when available. -Thanks you, -Stlink project maintainers +Thank you, +The stlink project maintainers From d15a2535cae3a76608fe9e7b3a7da27f409fa400 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 5 May 2016 12:52:58 +0200 Subject: [PATCH 0403/1435] CMake: Dont use pkg-config to find libusb on Mac OSX, rewrite to CMake find module (tested on homebrew only) --- CMakeLists.txt | 8 +++++--- cmake/modules/FindLibUSB.cmake | 27 +++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 3 deletions(-) create mode 100644 cmake/modules/FindLibUSB.cmake diff --git a/CMakeLists.txt b/CMakeLists.txt index cd329bb18..d26f03c8f 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,7 +4,9 @@ cmake_minimum_required(VERSION 2.8.7) include(CheckCCompilerFlag) find_package(PkgConfig) -pkg_check_modules(libusb REQUIRED libusb-1.0) +set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") + +find_package(LibUSB REQUIRED) pkg_check_modules(gtk gtk+-3.0) function(add_cflag_if_supported flag) @@ -57,14 +59,14 @@ set(CFILES src/stlink-common.c src/uglylogging.c ) -include_directories(${libusb_INCLUDE_DIRS}) +include_directories(${LIBUSB_INCLUDE_DIR}) include_directories(src) include_directories(mingw) add_library(${PROJECT_NAME} STATIC ${HFILES} # header files for ide projects generated by cmake ${CFILES}) -target_link_libraries(${PROJECT_NAME} ${libusb_LDFLAGS}) +target_link_libraries(${PROJECT_NAME} ${LIBUSB_LIBRARIES}) add_executable(st-flash flash/main.c) target_link_libraries(st-flash ${PROJECT_NAME}) diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake new file mode 100644 index 000000000..2e518a7a6 --- /dev/null +++ b/cmake/modules/FindLibUSB.cmake @@ -0,0 +1,27 @@ +# FindLibUSB.cmake - Try to find the Hiredis library +# Once done this will define +# +# LIBUSB_FOUND - System has libusb +# LIBUSB_INCLUDE_DIR - The libusb include directory +# LIBUSB_LIBRARIES - The libraries needed to use libusb +# LIBUSB_DEFINITIONS - Compiler switches required for using libusb + +FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h + HINTS + /usr + /usr/local + /opt + PATH_SUFFIXES libusb-1.0 + ) + +FIND_LIBRARY(LIBUSB_LIBRARIES NAMES usb-1.0 + HINTS + /usr + /usr/local + /opt + ) + +INCLUDE(FindPackageHandleStandardArgs) +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARIES LIBUSB_INCLUDE_DIR) + +MARK_AS_ADVANCED(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARIES) From d25244304547517f8b67e78a1fb52eaec165b18d Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 5 May 2016 12:55:58 +0200 Subject: [PATCH 0404/1435] stlink-usb: Rewrite warning libusb_claim_interface, to be more human friendly. Fixes as discussed in #303 --- src/stlink-usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 4cdefd795..98654129e 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -836,7 +836,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 } if (libusb_claim_interface(slu->usb_handle, 0)) { - WLOG("libusb_claim_interface() failed\n"); + WLOG("Stlink usb device found, but unable to claim (probably already in use?)\n"); goto on_libusb_error; } From 62fa371b421ce929b216a2265931f9c1546d1a69 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 5 May 2016 15:19:22 +0200 Subject: [PATCH 0405/1435] Add ChangeLog.md before bump to v1.2.0 --- ChangeLog | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++ ChangeLog.md | 1 + 2 files changed, 56 insertions(+) create mode 120000 ChangeLog.md diff --git a/ChangeLog b/ChangeLog index e69de29bb..00d82ee9f 100644 --- a/ChangeLog +++ b/ChangeLog @@ -0,0 +1,55 @@ +Stlink ChangeLog +================ + +v1.2.0 +====== + +Release date: 16 may 2016 + +Features added: + +* Add multiple stlink probing (`st-info --probe`, `st-info --hla-serial`) with printing serial in hex and OpenOCD `hla_serial` format (Jerry Jacobs) +* Add stlink usb probe API functions (Jerry Jacobs) +* Added parameter to specify one stlink v2 of many (Georg von Zengen) + +Changes: + +* Refactoring/fixes of flash loader (Maxime Coquelin) + +Updates and fixes: + +* Synchronize cache for stm32f7 (Tristan Gingold) +* Allow flashing of STM32L4 down to 1.71 V (Greg Meiste) +* Fix on stm32l4 to clear flash mass erase flags on CR (Bruno Dal Bo) +* Proper writing of page 0 of second bank for stm32l476xe (Tobias Badertscher) +* Trace the read data in stlink_read_debug32 and not the address of the variable (Tobias Badertscher) +* Mac OS X El Capitan platform support confirmation (Nikolay) +* Do not send a NUL at end of packets to gdb (Tristan Gingold) +* Correctly compute flash write size for partial pages (Dave Vandervies) +* _stlink_usb_reset use hardreset (mlundinse) +* Make sure MCU is halted before running RAM based flashloaders (mlundinse) +* Could not flash STM32_F3_SMALL (Max Chen) +* STM32F4 8-bit support for 1.8v operation (Andy Isaacson) +* Fix F2 memory map (Nicolas Schodet) +* Memory map for stm32f42xxx and stm32f43xxx devices (Craig Lilley) +* Stm32l0x flash loader (Robin Kreis) + +Chip support added for: + +* STM32L053R8 (Jean-Luc Béchennec) +* STM32F7 Support (mlundinse) +* Add STM32L4 to CHIPID #defines and devices[], flash driver and loaded (Dave Vandervies) +* Basic support for F446 (Pavel Kirienko) +* STM32F303 High Density +* STM32L1xx Cat.2 devices (Nicolas Schodet) + +Board support added for: + +* Nucleo-F303RE (Kyle Manna) +* Nucleo-F411RE (texane) + +Build system: + +* Travis: Initial support for Travis continues integration on Linux & Mac OS X (Jerry Jacobs) +* CMake: Document in README.md and add extra strict compiler flags (Jerry Jacobs) +* CMake: First stab at a cmake build (Josh Bialkowski) diff --git a/ChangeLog.md b/ChangeLog.md new file mode 120000 index 000000000..b0936e8d0 --- /dev/null +++ b/ChangeLog.md @@ -0,0 +1 @@ +ChangeLog \ No newline at end of file From e454fe98191095333258cfcfa813585086f669ed Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 5 May 2016 14:46:42 +0200 Subject: [PATCH 0406/1435] Reorganize files: * Header files moved into include/stlink * doc/tutorial.{pdf/tex} converted to markdown for rendering by github and easy editing * Remove `stlink-` suffix from some C source files and move into `src/tools` --- CMakeLists.txt | 47 ++-- Makefile.am | 38 +-- README.md | 1 - TODO | 11 - TODO.md | 11 + configure.ac | 2 +- doc/tutorial.md | 190 ++++++++++++++ doc/tutorial/tutorial.pdf | Bin 110584 -> 0 bytes doc/tutorial/tutorial.tex | 234 ------------------ .../modprobe.d/stlink_v1.conf | 0 .../udev/rules.d/49-stlinkv1.rules | 0 .../udev/rules.d/49-stlinkv2-1.rules | 0 .../udev/rules.d/49-stlinkv2.rules | 0 flash/Makefile | 30 --- src/stlink-common.h => include/stlink.h | 25 +- src/uglylogging.h => include/stlink/logging.h | 0 {src => include/stlink}/mmap.h | 0 src/stlink-sg.h => include/stlink/sg.h | 8 +- src/stlink-usb.h => include/stlink/usb.h | 6 +- src/{stlink-common.c => common.c} | 6 +- {gdbserver => src/gdbserver}/Makefile | 0 {gdbserver => src/gdbserver}/gdb-remote.c | 0 {gdbserver => src/gdbserver}/gdb-remote.h | 0 {gdbserver => src/gdbserver}/gdb-server.c | 4 +- {gdbserver => src/gdbserver}/gdb-server.h | 0 src/{uglylogging.c => logging.c} | 3 +- {mingw => src/mingw}/mingw.c | 0 {mingw => src/mingw}/mingw.h | 0 src/mmap.c | 2 +- src/{stlink-sg.c => sg.c} | 5 +- flash/main.c => src/tools/flash.c | 3 +- src/{st-info.c => tools/info.c} | 2 +- src/{st-term.c => tools/term.c} | 3 +- src/{stlink-usb.c => usb.c} | 3 +- src/test_sg.c => tests/stlink_sg.c | 0 src/test_usb.c => tests/stlink_usb.c | 0 36 files changed, 276 insertions(+), 358 deletions(-) delete mode 120000 README.md delete mode 100644 TODO create mode 100644 TODO.md create mode 100644 doc/tutorial.md delete mode 100644 doc/tutorial/tutorial.pdf delete mode 100644 doc/tutorial/tutorial.tex rename stlink_v1.modprobe.conf => etc/modprobe.d/stlink_v1.conf (100%) rename 49-stlinkv1.rules => etc/udev/rules.d/49-stlinkv1.rules (100%) rename 49-stlinkv2-1.rules => etc/udev/rules.d/49-stlinkv2-1.rules (100%) rename 49-stlinkv2.rules => etc/udev/rules.d/49-stlinkv2.rules (100%) delete mode 100644 flash/Makefile rename src/stlink-common.h => include/stlink.h (99%) rename src/uglylogging.h => include/stlink/logging.h (100%) rename {src => include/stlink}/mmap.h (100%) rename src/stlink-sg.h => include/stlink/sg.h (96%) rename src/stlink-usb.h => include/stlink/usb.h (93%) rename src/{stlink-common.c => common.c} (99%) rename {gdbserver => src/gdbserver}/Makefile (100%) rename {gdbserver => src/gdbserver}/gdb-remote.c (100%) rename {gdbserver => src/gdbserver}/gdb-remote.h (100%) rename {gdbserver => src/gdbserver}/gdb-server.c (99%) rename {gdbserver => src/gdbserver}/gdb-server.h (100%) rename src/{uglylogging.c => logging.c} (97%) rename {mingw => src/mingw}/mingw.c (100%) rename {mingw => src/mingw}/mingw.h (100%) rename src/{stlink-sg.c => sg.c} (99%) rename flash/main.c => src/tools/flash.c (99%) rename src/{st-info.c => tools/info.c} (99%) rename src/{st-term.c => tools/term.c} (99%) rename src/{stlink-usb.c => usb.c} (99%) rename src/test_sg.c => tests/stlink_sg.c (100%) rename src/test_usb.c => tests/stlink_usb.c (100%) diff --git a/CMakeLists.txt b/CMakeLists.txt index d26f03c8f..f75ce611d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -47,37 +47,38 @@ elseif() add_cflag_if_supported("-O2") endif() -set(HFILES src/stlink-common.h - src/stlink-usb.h - src/stlink-sg.h - src/uglylogging.h - src/mmap.h) - -set(CFILES src/stlink-common.c - src/stlink-usb.c - src/stlink-sg.c - src/uglylogging.c - ) +set(STLINK_HEADERS include/stlink.h + include/stlink/usb.h + include/stlink/sg.h + include/stlink/logging.h + include/stlink/mmap.h +) + +set(STLINK_SOURCE src/common.c + src/usb.c + src/sg.c + src/logging.c +) include_directories(${LIBUSB_INCLUDE_DIR}) -include_directories(src) -include_directories(mingw) +include_directories(include) +include_directories(src/mingw) add_library(${PROJECT_NAME} STATIC - ${HFILES} # header files for ide projects generated by cmake - ${CFILES}) + ${STLINK_HEADERS} # header files for ide projects generated by cmake + ${STLINK_SOURCE}) target_link_libraries(${PROJECT_NAME} ${LIBUSB_LIBRARIES}) -add_executable(st-flash flash/main.c) +add_executable(st-flash src/tools/flash.c) target_link_libraries(st-flash ${PROJECT_NAME}) -add_executable(st-info src/st-info.c) +add_executable(st-info src/tools/info.c) target_link_libraries(st-info ${PROJECT_NAME}) -add_executable(st-util gdbserver/gdb-remote.c - gdbserver/gdb-remote.h - gdbserver/gdb-server.c - gdbserver/gdb-server.h) +add_executable(st-util src/gdbserver/gdb-remote.c + src/gdbserver/gdb-remote.h + src/gdbserver/gdb-server.c + src/gdbserver/gdb-server.h) target_link_libraries(st-util ${PROJECT_NAME}) install(TARGETS ${PROJECT_NAME} st-flash st-util st-info @@ -86,8 +87,8 @@ install(TARGETS ${PROJECT_NAME} st-flash st-util st-info ) if(NOT MINGW) - list(APPEND CFILES src/st-term.c) - add_executable(st-term src/st-term.c) + list(APPEND STLINK_SOURCE src/tools/term.c) + add_executable(st-term src/tools/term.c) target_link_libraries(st-term ${PROJECT_NAME}) install(TARGETS st-term diff --git a/Makefile.am b/Makefile.am index 9afbc0f0b..fc95184bc 100644 --- a/Makefile.am +++ b/Makefile.am @@ -12,43 +12,43 @@ endif noinst_LIBRARIES = libstlink.a -st_flash_SOURCES = flash/main.c -st_term_SOURCES = src/st-term.c -st_info_SOURCES = src/st-info.c -st_util_SOURCES = gdbserver/gdb-remote.c gdbserver/gdb-remote.h gdbserver/gdb-server.c mingw/mingw.c mingw/mingw.h +st_flash_SOURCES = src/tools/flash.c +st_term_SOURCES = src/tools/term.c +st_info_SOURCES = src/tools/info.c +st_util_SOURCES = src/gdbserver/gdb-remote.c src/gdbserver/gdb-remote.h src/gdbserver/gdb-server.c src/mingw/mingw.c src/mingw/mingw.h CFILES = \ - src/stlink-common.c \ - src/stlink-usb.c \ - src/stlink-sg.c \ - src/uglylogging.c + src/common.c \ + src/usb.c \ + src/sg.c \ + src/logging.c if !MINGW -CFILES += src/st-term.c +CFILES += src/tools/term.c endif HFILES = \ - src/stlink-common.h \ - src/stlink-usb.h \ - src/stlink-sg.h \ - src/uglylogging.h \ - src/mmap.h + include/stlink.h \ + include/stlink/usb.h \ + include/stlink/sg.h \ + include/stlink/logging.h \ + include/stlink/mmap.h libstlink_a_SOURCES = $(CFILES) $(HFILES) -libstlink_a_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 libstlink_a_LIBADD = $(LIBOBJS) +libstlink_a_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/include st_flash_LDADD = libstlink.a -st_flash_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_srcdir)/mingw +st_flash_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/include -I$(top_srcdir)/src/mingw st_util_LDADD = libstlink.a -st_util_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_srcdir)/mingw +st_util_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/include -I$(top_srcdir)/src/mingw st_term_LDADD = libstlink.a -st_term_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_srcdir)/mingw +st_term_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/include -I$(top_srcdir)/src/mingw st_info_LDADD = libstlink.a -st_info_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/src -I$(top_srcdir)/mingw +st_info_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/include -I$(top_srcdir)/src/mingw EXTRA_DIST = autogen.sh diff --git a/README.md b/README.md deleted file mode 120000 index 100b93820..000000000 --- a/README.md +++ /dev/null @@ -1 +0,0 @@ -README \ No newline at end of file diff --git a/TODO b/TODO deleted file mode 100644 index 2b0baf62f..000000000 --- a/TODO +++ /dev/null @@ -1,11 +0,0 @@ -. flash tool - . improve flash writing, still use word fast write... too slow - -. documentation - . make README points to doc/tutorial - -. compile and test a realtime kernel, for instance: -http://www.chibios.org/dokuwiki/doku.php?id=chibios:articles:stm32l_discovery -svn checkout https://chibios.svn.sourceforge.net/svnroot/chibios/trunk ; -cd chibios/trunk/demos/ARMCM3-STM32L152-DISCOVERY ; -make ; diff --git a/TODO.md b/TODO.md new file mode 100644 index 000000000..9c5059a49 --- /dev/null +++ b/TODO.md @@ -0,0 +1,11 @@ +# flash tool + +- improve flash writing, still use word fast write... too slow + +# documentation + +- make README points to doc/tutorial + +# testing + +- compile and test a realtime kernel (e.g ChibiOS) diff --git a/configure.ac b/configure.ac index 203cc6bd5..f37471740 100644 --- a/configure.ac +++ b/configure.ac @@ -3,7 +3,7 @@ AC_PREREQ(2.61) AC_INIT([stlink],[0.5.6],[davem@devkitpro.org]) -AC_CONFIG_SRCDIR([src/stlink-common.c]) +AC_CONFIG_SRCDIR([src/common.c]) AC_CONFIG_LIBOBJ_DIR([src]) AM_INIT_AUTOMAKE([1.10]) diff --git a/doc/tutorial.md b/doc/tutorial.md new file mode 100644 index 000000000..937e2da28 --- /dev/null +++ b/doc/tutorial.md @@ -0,0 +1,190 @@ +Using STM32 discovery kits with open source tools +======== + +This guide details the use of STMicroelectronics STM32 discovery kits in an open source environment. + +Installing a GNU toolchain +========================== + +Any toolchain supporting the cortex m3 should do. You can find the +necessary to install such a toolchain here: + +``` +https://github.com/esden/summon-arm-toolchain +``` + +Details for the installation are provided in the topmost `README` file. +This documentation assumes the toolchains is installed in a +`$TOOLCHAIN_PATH`. + +Installing STLINK +================= + +STLINK is open source software to program and debug ST’s STM32 Discovery +kits. Those kits have an onboard chip that translates USB commands sent +by the host PC into JTAG/SWD commands. This chip is called STLINK, (yes, +isn’t that confusing? suggest a better name!) and comes in 2 versions +(STLINK v1 and v2). From a software point of view, those versions differ +only in the transport layer used to communicate (v1 uses SCSI passthru +commands, while v2 uses raw USB). From a user point of view, they are +identical. + + +Before continuing, the following dependencies must be met: + +- libusb-1.0 +- pkg-config +- autotools + +STLINK should run on any system meeting the above constraints. + +The STLINK software source code is retrieved using: + +``` +$> git clone https://github.com/texane/stlink stlink.git +``` + +Everything can be built from the top directory: + +``` +$> cd stlink.git +$> ./autogen.sh +$> ./configure +$> make +``` + +It includes: + +- a communication library (stlink.git/libstlink.a), +- a GDB server (stlink.git/st-util), +- a flash manipulation tool (stlink.git/st-flash). + +Using the GDB server +==================== + + +This assumes you have got the libopencm3 project downloaded in `ocm3`. +The libopencm3 project has some good, reliable examples for each of the +Discovery boards. + +Even if you don’t plan on using libopencm3, the examples they provide +will help you verify that: + +- Your installed toolchain is capable of compiling for cortex M3/M4 + targets +- stlink is functional +- Your arm-none-eabi-gdb is functional +- Your board is functional + +A GDB server must be started to interact with the STM32. Depending on +the discovery kit you are using, you must run one of the 2 commands: + +``` +# STM32VL discovery kit (onboard ST-link) +$> ./st-util --stlinkv1 + +# STM32L or STM32F4 discovery kit (onboard ST-link/V2) +$> ./st-util + +# Full help for other options (listen port, version) +$> ./st-util --help +``` + +Then, GDB can be used to interact with the kit: + +``` +$> $TOOLCHAIN_PATH/bin/arm-none-eabi-gdb example_file.elf +``` + +From GDB, connect to the server using: + +``` +(gdb) target extended localhost:4242 +``` + +GDB has memory maps for as many chips as it knows about, and will load +your project into either flash or SRAM based on how the project was +linked. Linking projects to boot from SRAM is beyond the scope of this +document. + +Because of these built in memory maps, after specifying the .elf at the +command line, now we can simply “load” the target: + +``` +(gdb) load +``` + +st-util will load all sections into their appropriate addresses, and +“correctly” set the PC register. So, to run your freshly loaded program, +simply “continue” + +``` +(gdb) continue +``` + +Your program should now be running, and, if you used one of the blinking +examples from libopencm3, the LEDs on the board should be blinking for +you. + +Building and flashing a program +=============================== + +If you want to simply flash binary files to arbitrary sections of +memory, or read arbitary addresses of memory out to a binary file, use +the st-flash tool, as shown below: + +``` + +# stlinkv1 command to read 4096 from flash into out.bin +$> ./st-flash read v1 out.bin 0x8000000 4096 + +# stlinkv2 command +$> ./st-flash read out.bin 0x8000000 4096 + +# stlinkv1 command to write the file in.bin into flash +$> ./st-flash write v1 in.bin 0x8000000 + +# stlinkv2 command +$> ./st-flash write in.bin 0x8000000 +``` + +#### + +Of course, you can use this instead of the gdb server, if you prefer. +Just remember to use the “.bin” image, rather than the .elf file. + +``` + +# write blink.bin into FLASH +$> [sudo] ./st-flash write fancy_blink.bin 0x08000000 +``` + +Upon reset, the board LEDs should be blinking. + +Notes +===== + +Disassembling THUMB code in GDB +------------------------------- + +By default, the disassemble command in GDB operates in ARM mode. The +programs running on CORTEX-M3 are compiled in THUMB mode. To correctly +disassemble them under GDB, uses an odd address. For instance, if you +want to disassemble the code at 0x20000000, use:\ + +``` +(gdb) disassemble 0x20000001 +``` + +References +========== + +- + documentation related to the STM32L mcu + +- + documentation related to the STM32L discovery kit + +- + libopencm3, a project providing a firmware library, with solid + examples for Cortex M3, M4 and M0 processors from any vendor. diff --git a/doc/tutorial/tutorial.pdf b/doc/tutorial/tutorial.pdf deleted file mode 100644 index b73396ce73035085f757c109b178fdebdd3c6515..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 110584 zcmce-1yo$g)+mg-LlOw?F5Qg=cXtgILU4Bt!QCB#I|M=k!GaT<;I09JI|TQ?k-3xm z&wTIB{oY!SwN6o|s`jq!yQ)q#rGkhUBY=q&iE?nXeG&;o!a`!LZ$`qygTyRjXl3kR zLIMPEkUab$F^id6I2hWIFpF8db}$q%d}D23h{VT-Wba^S_}UW5W!f=PP#&5T!+-CR zeib3G9goK1E4$*GV%-qxr4|R%xygk5%nr{z1uSfI-37qmk3{%yXc$)9S8KX{yPE+7 zgPE*Tcz%pgVuq>EYYGQ?e#QrJ1xs=#aFrT?@Hr_21@)3j+y^fsU2d$FPK%a5NW7IT zr&jziO`m4)%A?ch`^Hjzuxz5k%RG++=GWc+a3o4UG(Bkj)LcJ#f9%1il-jcKJgxc3 zxz^Ez3Ws^R;h@L!efTM5BN5%fXHYOkkI|(N%fQge!2MLVD4h&AhaX*-kkK}Q>JK#UmA_krU ztRJuv0PG~JcLVRL93*UiRM|+_@2g!c{oM>jMLOwwpM#Rk?wG<-rN4Pm;gVTORz1ZCQQxPWE+Ur-aWvXnx^F%CzJ zO`(F~QJ?`{G(kCFR?;w&Xq1tzi3^VcElEWn@a>Qct`%Vy>CHTIjHjZrhoY)sLr$^- zR)`=@Z(^~-Zb~84dox~}Q_+_rD2&-Kj)KR*be%;5=dJp##Fv>WNJkpP@iE1_IGd-7 z8mmU{t!iuN`$8$}6R>)5rKm@bzLcpS)@rW z7>)!oMU?fs@4rE{0P^`;ng}=C*wRxokPvSd+}f}Sd)(xkpn@ork&^c>PP6*4tIwD5 zr(+^6{%T8HziHraZ3%Fvqkl6d&WDEooiW`3|Do|ejS0v>0=TzPur&cWNdR{ies5X- zojKiE;UCEV2q3J$e;hzm6~4>0vS8G&(Vv(QZ@XOw#nNMm3JDSHquLf?Raa{2<4_A; z@k(0K*-lR#Y;U{3rV2DGQ%ZT*j9D==X0A$2V9jD;Fj^ZxtC>W6fSYLL7VN>uBmIP| zDsfcflEDxzR1$)1e_^UMl z?p*p03I4q~+EW1LJm}AuS5^lObYP_C}PZY^h=WYZ#!I}Kw_fX16RK~>#)u)u+_?A} z4-%HJ4hUru;uK`{>lB_^2)pHF2WT;4UmQ!iyF~85{}`h??j~G6*)Sc>Dgv%~#O1tx z&O!mi$Oo64=U{3!nn3dLcHygfOAcPOj{lmOfnq9+Xp?wR_7c0x6X;*s_R%OU4g*}H zhTBRc2TUfU8u@H+Is^6q!CoW@k4?HP#smca!>1qtRa@(GR&HwR%_2UB$d3_+V*~MC zXtrc0sDSsNWK*S+;$nO`I)z5+)FKATrUp~_IJso+1saSGtk{GgLfx@jy zJS$aovOW+hVAp#a%^oe)XC8e&xL98T(9I$_vALJqgzTI!T5EDdDt%+RB&4hM*x@IT zMrhv%afK`6P{dJ8`NJ$&WNGBn}3xB1xp4!w4M6m*I;%Eate{j>t`Mkzeu#+NNc>b zbKD-kZCtj=b-|`KDVKc3BaFr+98HXVsP}AtVFmVdYi#r9FMk=RtmNS`6tx+FAiq2y zDpqN-g6(HIpNT9@5g`d|U5@Lh3CFSRr_oX}HQLv9*E0j5)y3+G%zlV4#&`pMbsd(z z65sm7h8cBVC~5nt%A31uhyYP7eJRkrk?U6{1?4gIfO8Zy%U2ExrcZm+xaa@20OmP*`TDdibfq4;d6F^sa|(&sLm`GTvxZ6hPZYgdz~& z{AjLv?p77lEWY@`!aWq8tR9kSr)SojI*b21zUB;^{P?c#Og(+n_f}M?gfVY}03h*I z>Gzbze)z4uYkODG6xllJrE`xjr~Bu;xy*73y{hIhGDy{GU_E{D^lZ|%_u3orXNYKjdFPeiLQtw+~$sTXdl&XZGZRAxekLYO-NNqAci<_Cc zHDYI#1a~E_1SEee4>3uxx0PxRncB8x#(T0Q!E)0bxaxD|Re;7(hj0b2>2``2nau3Q zKpdE0W;8k8U`+>5E^8#7{R;HjyDTT%^3k3TN7J*KXD8we|1{aP9eJ&H>hQVRX@4j^ zI)zs`3a$FO%o|k@~bZQze(5R zqnR5AmX?n~A?ttDm&J8&tUbFF@*?HIIIMxBZD(zB|I*}god6F@;PX+&(9~v4_U;<2N2j)*v8rp!l$m=LrI(_#7liKb*+^SjIV61Zod8KkW=@1r=qF!M5hhw_+VUJ=jQWmw6 zu{rM{?*3THg;$Xrm54*;M9+!}<`mS@XKfJ(5vOvRczrDzKludO>YHa!kEv-;uyHPl z=q40F9U8g*MMV-HenLP(ifCNXa=L+3%v4|u(%TlB#nZPzZp7{0Jt#{>=L7`%_QE^v zw8+Uxg%k>a+4M6J&t0uETbi}h>1Dnr6UwBHZ5m^Z7FI=u8Ts>GAO^dT4_{KUb|NyG zzYYf&zBs4j4D1vesn=tGVkwM}AiFg3Y&B=p zEJk3|JdqWP0an2H`5~EoP@u=w33qk1)x2I6o=V)b2R`e~a7q%Oe~g0_GyR)pRy;kH z=8IFvO3Dw}hT^@^g%LFF9c^cVi>r2}W?uS>t8dO4Y@1G&3geUYy4B@-Hh#h6BQIVK zRStalFg5z-^`(3yrG1Wvz-_u4C0bE1u~KmncI)WyN?OL6jnNML*{OT0)0hpSae9yK zhqqUKYtOAWzZJFFHmC~L<*CFVz`E(l}(5p7&-uAxZF~YC(2~!ojapugR?3 zRdTxO+&MY&epUFEYkgZFayMD~2K+R;$T~l=4=4WAwNhx42n_{4(GvRb$|-ZYiV0ue zY$Q|X8wP9I@DDCq%=%1$%gCAc;s-V)M?aJi$HEp06G#as(nkaQ8jCmISJk2&Kb3ZS zWf1Q$tXk~88D_>1xM$PRtp+i80Wp|BTTGrwnWUh-LHKOfWssJBq3vd*M1cf`$aE3H z=UQQ$jSQ<;_?uXRz{WTw8Eg5m$g>sptXvudh{;K-DpkTKVX8jT7JC8v!99taKb11R zbtyPizh2LnJvKm70`7Vam0m)^TnW7YhX;Fv^20}c*wk))`;!yifrLRswaz%^^180t?l{^c z|Axbo{?h&%DRrP%E66%84}S`1ZkZo$5JD|~h+j)zYBaq%arU(>^1UhiPr(i1GgnZG zmJOPX8bEnG235<%`h_Cx9@^5`70*Y>Iu{4M|u~MVS=8Ii>S* zNi3akGcG44T18}2Ss9v2+m@wr@K+g|z|A)~ZjoSAMtx4xm~mh#YxhR4s~>Dst}Oal zEL6pZB=}=lPCw|HZ_Rsd`4kHnQb_z*#R!7bN7hp4hpm0WqCHvH#=E^V`I0K^Is?Lvog$+Bivw7_U!m*2WILJQf@nf(~D4aw4OSF>`b~i{aD)xx4LwKvBTg zUw-=XF4Qk^y0fzxl(yitgVtGZ_vTnZZ-K2IsV3ioeLyZp5o&6mg=RAB#SfJS)^oh% zp7yqIiwL5?C^jEiSoG7nWJaOPj%8b%wASP3Z(l@ZH{jYs&MWr9^3twON6L^;xsg3r z#MtJ(%xjTo@$17$l(9R8P4Yd^w+o%`FM)Yxu6jeB@UCqbpW&KF+Ov5W`RWR@*pshJ z7~RWT95*CSu!OpbCYkw48UG0OP)`+}`${@SAS((B21-IF>abA|I?EhMLO6o(qNJrx zB*|nD*VHq@u7E_(c>p)+jb?ImL5t1v25(v=uGDfO1)rgTeyy_&Kd6_kk|{M=nvT<} z4T%GCs2T*W`;?pebpFgT+dQr>_Qx}V;zZa*s^A4B&#nsDT(}_$O*U`G4lJG9e0vW@DiSvtEu4{_ytqqCzRP@zhviaVmZ)D? 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You can find the necessary -to install such a toolchain here:\\ -\begin{small} -\begin{lstlisting}[frame=tb] -https://github.com/esden/summon-arm-toolchain -\end{lstlisting} -\end{small} - -\paragraph{} -Details for the installation are provided in the topmost README file. -This documentation assumes the toolchains is installed in a \$TOOLCHAIN\_PATH. - - -\newpage - -\section{Installing STLINK} -\paragraph{} -STLINK is open source software to program and debug ST's STM32 Discovery kits. Those -kits have an onboard chip that translates USB commands sent by the host PC into -JTAG/SWD commands. This chip is called STLINK, (yes, isn't that confusing? suggest a better -name!) and comes in 2 versions (STLINK v1 and v2). From a software -point of view, those versions differ only in the transport layer used to communicate -(v1 uses SCSI passthru commands, while v2 uses raw USB). From a user point of view, they -are identical. - -\paragraph{} -Before continuing, the following dependencies must be met: -\begin{itemize} -\item libusb-1.0 -\item pkg-config -\item autotools -\end{itemize} - -\paragraph{} -STLINK should run on any system meeting the above constraints. - -\paragraph{} -The STLINK software source code is retrieved using:\\ -\begin{small} -\begin{lstlisting}[frame=tb] -$> git clone https://github.com/texane/stlink stlink.git -\end{lstlisting} -\end{small} - -\paragraph{} -Everything can be built from the top directory:\\ -\begin{small} -\begin{lstlisting}[frame=tb] -$> cd stlink.git -$> ./autogen.sh -$> ./configure -$> make -\end{lstlisting} -\end{small} -It includes: -\begin{itemize} -\item a communication library (stlink.git/libstlink.a), -\item a GDB server (stlink.git/st-util), -\item a flash manipulation tool (stlink.git/st-flash). -\end{itemize} - - -\newpage -\section{Using the GDB server} -\paragraph{} -This assumes you have got the libopencm3 project downloaded in [ocm3]. The -libopencm3 project has some good, reliable examples for each of the Discovery boards. - -Even if you don't plan on using libopencm3, the examples they provide will help you -verify that: - -\begin{itemize} -\item Your installed toolchain is capable of compiling for cortex M3/M4 targets -\item stlink is functional -\item Your arm-none-eabi-gdb is functional -\item Your board is functional -\end{itemize} - -\paragraph{} -A GDB server must be started to interact with the STM32. Depending on the discovery kit you -are using, you must run one of the 2 commands:\\ -\begin{small} -\begin{lstlisting}[frame=tb] -# STM32VL discovery kit (onboard ST-link) -$> ./st-util --stlinkv1 - -# STM32L or STM32F4 discovery kit (onboard ST-link/V2) -$> ./st-util - -# Full help for other options (listen port, version) -$> ./st-util --help -\end{lstlisting} -\end{small} - -\paragraph{} -Then, GDB can be used to interact with the kit:\\ -\begin{small} -\begin{lstlisting}[frame=tb] -$> $TOOLCHAIN_PATH/bin/arm-none-eabi-gdb example_file.elf -\end{lstlisting} -\end{small} - -\paragraph{} -From GDB, connect to the server using:\\ -\begin{small} -\begin{lstlisting}[frame=tb] -(gdb) target extended localhost:4242 -\end{lstlisting} -\end{small} - -\paragraph{} -GDB has memory maps for as many chips as it knows about, and will load your project -into either flash or SRAM based on how the project was linked. Linking projects -to boot from SRAM is beyond the scope of this document. - -Because of these built in memory maps, after specifying the .elf at the command line, now -we can simply "load" the target:\\ -\begin{small} -\begin{lstlisting}[frame=tb] -(gdb) load -\end{lstlisting} -\end{small} - -\paragraph{} -st-util will load all sections into their appropriate addresses, and "correctly" set the PC -register. So, to run your freshly loaded program, simply "continue"\\ -\begin{small} -\begin{lstlisting}[frame=tb] -(gdb) continue -\end{lstlisting} -\end{small} - -\paragraph{} -Your program should now be running, and, if you used one of the blinking examples from -libopencm3, the LEDs on the board should be blinking for you. - -\newpage -\section{Building and flashing a program} -\paragraph{} -If you want to simply flash binary files to arbitrary sections of memory, or -read arbitary addresses of memory out to a binary file, use the st-flash tool, -as shown below:\\ -\begin{small} -\begin{lstlisting}[frame=tb] - -# stlinkv1 command to read 4096 from flash into out.bin -$> ./st-flash read v1 out.bin 0x8000000 4096 - -# stlinkv2 command -$> ./st-flash read out.bin 0x8000000 4096 - -# stlinkv1 command to write the file in.bin into flash -$> ./st-flash write v1 in.bin 0x8000000 - -# stlinkv2 command -$> ./st-flash write in.bin 0x8000000 -\end{lstlisting} -\end{small} - -\paragraph{} -Of course, you can use this instead of the gdb server, if you prefer. Just remember -to use the ".bin" image, rather than the .elf file.\\ -\begin{small} -\begin{lstlisting}[frame=tb] - -# write blink.bin into FLASH -$> [sudo] ./st-flash write fancy_blink.bin 0x08000000 -\end{lstlisting} -\end{small} - -\paragraph{} -Upon reset, the board LEDs should be blinking. - -\newpage -\section{Notes} - -\subsection{Disassembling THUMB code in GDB} -\paragraph{} -By default, the disassemble command in GDB operates in ARM mode. The programs running on CORTEX-M3 -are compiled in THUMB mode. To correctly disassemble them under GDB, uses an odd address. For instance, -if you want to disassemble the code at 0x20000000, use:\\ -\begin{small} -\begin{lstlisting}[frame=tb] -(gdb) disassemble 0x20000001 -\end{lstlisting} -\end{small} - - -\newpage -\section{References} -\begin{itemize} -\item http://www.st.com/internet/mcu/product/248823.jsp\\ - documentation related to the STM32L mcu -\item http://www.st.com/internet/evalboard/product/250990.jsp\\ - documentation related to the STM32L discovery kit -\item http://www.libopencm3.org\\ - libopencm3, a project providing a firmware library, with solid examples for Cortex - M3, M4 and M0 processors from any vendor. -\end{itemize} - -\end{document} diff --git a/stlink_v1.modprobe.conf b/etc/modprobe.d/stlink_v1.conf similarity index 100% rename from stlink_v1.modprobe.conf rename to etc/modprobe.d/stlink_v1.conf diff --git a/49-stlinkv1.rules b/etc/udev/rules.d/49-stlinkv1.rules similarity index 100% rename from 49-stlinkv1.rules rename to etc/udev/rules.d/49-stlinkv1.rules diff --git a/49-stlinkv2-1.rules b/etc/udev/rules.d/49-stlinkv2-1.rules similarity index 100% rename from 49-stlinkv2-1.rules rename to etc/udev/rules.d/49-stlinkv2-1.rules diff --git a/49-stlinkv2.rules b/etc/udev/rules.d/49-stlinkv2.rules similarity index 100% rename from 49-stlinkv2.rules rename to etc/udev/rules.d/49-stlinkv2.rules diff --git a/flash/Makefile b/flash/Makefile deleted file mode 100644 index 5345dcbfd..000000000 --- a/flash/Makefile +++ /dev/null @@ -1,30 +0,0 @@ -CFLAGS+=-g -CFLAGS+=-DDEBUG -CFLAGS+=-std=gnu99 -CFLAGS+=-Wall -Wextra -CFLAGS+=-I../src - -LDFLAGS=-L.. -lstlink - -# libusb location -LDFLAGS+=`pkg-config --libs libusb-1.0` -CFLAGS+=`pkg-config --cflags libusb-1.0` - -SRCS=main.c -OBJS=$(SRCS:.c=.o) - -NAME=st-flash - -all: $(NAME) - -$(NAME): $(OBJS) ../libstlink.a - $(CC) $(CFLAGS) -o $(NAME) $(OBJS) $(LDFLAGS) - -%.o: %.c - $(CC) $(CFLAGS) -c $^ -o $@ - -clean: - rm -f $(OBJS) - rm -f $(NAME) - -.PHONY: clean all diff --git a/src/stlink-common.h b/include/stlink.h similarity index 99% rename from src/stlink-common.h rename to include/stlink.h index e2f7b75c2..24b4dcf6e 100644 --- a/src/stlink-common.h +++ b/include/stlink.h @@ -1,20 +1,17 @@ /* - * File: stlink-common.h - * Bulk import from stlink-hw.h + * File: stlink.h * * This should contain all the common top level stlink interfaces, regardless * of how the backend does the work.... */ +#ifndef STLINK_H +#define STLINK_H -#ifndef STLINK_COMMON_H -#define STLINK_COMMON_H +#include -#ifdef __cplusplus +#ifdef __cplusplus extern "C" { #endif - -#include - // Max data transfer size. // 6kB = max mem32_read block, 8kB sram //#define Q_BUF_LEN 96 @@ -728,15 +725,11 @@ extern "C" { int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); int stlink_load_device_params(stlink_t *sl); +#include "stlink/sg.h" +#include "stlink/usb.h" - -#include "stlink-sg.h" -#include "stlink-usb.h" - - - -#ifdef __cplusplus +#ifdef __cplusplus } #endif -#endif /* STLINK_COMMON_H */ +#endif /* STLINK_H */ diff --git a/src/uglylogging.h b/include/stlink/logging.h similarity index 100% rename from src/uglylogging.h rename to include/stlink/logging.h diff --git a/src/mmap.h b/include/stlink/mmap.h similarity index 100% rename from src/mmap.h rename to include/stlink/mmap.h diff --git a/src/stlink-sg.h b/include/stlink/sg.h similarity index 96% rename from src/stlink-sg.h rename to include/stlink/sg.h index 7c0202851..56780f4c4 100644 --- a/src/stlink-sg.h +++ b/include/stlink/sg.h @@ -1,5 +1,5 @@ /* - * File: stlink-sg.h + * File: stlink/sg.h * Author: karl * * Created on October 1, 2011, 11:29 PM @@ -8,13 +8,13 @@ #ifndef STLINK_SG_H #define STLINK_SG_H +#include +#include "stlink.h" + #ifdef __cplusplus extern "C" { #endif -#include -#include "stlink-common.h" - // device access #define RDWR 0 #define RO 1 diff --git a/src/stlink-usb.h b/include/stlink/usb.h similarity index 93% rename from src/stlink-usb.h rename to include/stlink/usb.h index 747d54c74..76ac9211f 100644 --- a/src/stlink-usb.h +++ b/include/stlink/usb.h @@ -1,5 +1,5 @@ /* - * File: stlink-usb.h + * File: stlink/usb.h * Author: karl * * Created on October 1, 2011, 11:29 PM @@ -11,8 +11,8 @@ #include #include -#include "stlink-common.h" -#include "uglylogging.h" +#include "stlink.h" +#include "stlink/logging.h" #ifdef __cplusplus extern "C" { diff --git a/src/stlink-common.c b/src/common.c similarity index 99% rename from src/stlink-common.c rename to src/common.c index 18c76fb86..3e87824f1 100644 --- a/src/stlink-common.c +++ b/src/common.c @@ -9,10 +9,10 @@ #include #include #include -#include "mmap.h" -#include "stlink-common.h" -#include "uglylogging.h" +#include "stlink.h" +#include "stlink/mmap.h" +#include "stlink/logging.h" #ifndef _WIN32 #define O_BINARY 0 diff --git a/gdbserver/Makefile b/src/gdbserver/Makefile similarity index 100% rename from gdbserver/Makefile rename to src/gdbserver/Makefile diff --git a/gdbserver/gdb-remote.c b/src/gdbserver/gdb-remote.c similarity index 100% rename from gdbserver/gdb-remote.c rename to src/gdbserver/gdb-remote.c diff --git a/gdbserver/gdb-remote.h b/src/gdbserver/gdb-remote.h similarity index 100% rename from gdbserver/gdb-remote.h rename to src/gdbserver/gdb-remote.h diff --git a/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c similarity index 99% rename from gdbserver/gdb-server.c rename to src/gdbserver/gdb-server.c index eca6597b4..666251c1b 100644 --- a/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -19,8 +19,8 @@ #include #endif -#include -#include +#include +#include #include "gdb-remote.h" #include "gdb-server.h" diff --git a/gdbserver/gdb-server.h b/src/gdbserver/gdb-server.h similarity index 100% rename from gdbserver/gdb-server.h rename to src/gdbserver/gdb-server.h diff --git a/src/uglylogging.c b/src/logging.c similarity index 97% rename from src/uglylogging.c rename to src/logging.c index a04ab3391..4969c4400 100644 --- a/src/uglylogging.c +++ b/src/logging.c @@ -3,14 +3,13 @@ * rest of our code pretty enough. * */ - #include #include #include #include #include -#include "uglylogging.h" +#include "stlink/logging.h" static int max_level; diff --git a/mingw/mingw.c b/src/mingw/mingw.c similarity index 100% rename from mingw/mingw.c rename to src/mingw/mingw.c diff --git a/mingw/mingw.h b/src/mingw/mingw.h similarity index 100% rename from mingw/mingw.h rename to src/mingw/mingw.h diff --git a/src/mmap.c b/src/mmap.c index c5794da91..bee0dcece 100644 --- a/src/mmap.c +++ b/src/mmap.c @@ -3,7 +3,7 @@ #include #include -#include "mmap.h" +#include "stlink/mmap.h" void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offset) { diff --git a/src/stlink-sg.c b/src/sg.c similarity index 99% rename from src/stlink-sg.c rename to src/sg.c index 03df7d854..40570981d 100644 --- a/src/stlink-sg.c +++ b/src/sg.c @@ -82,9 +82,8 @@ #include #include -#include "stlink-common.h" -#include "stlink-sg.h" -#include "uglylogging.h" +#include "stlink.h" +#include "stlink/logging.h" static void clear_cdb(struct stlink_libsg *sl) { for (size_t i = 0; i < sizeof (sl->cdb_cmd_blk); i++) diff --git a/flash/main.c b/src/tools/flash.c similarity index 99% rename from flash/main.c rename to src/tools/flash.c index 0ba429c66..770289ba3 100644 --- a/flash/main.c +++ b/src/tools/flash.c @@ -8,7 +8,8 @@ #include #include #include -#include "stlink-common.h" + +#include #define DEBUG_LOG_LEVEL 100 #define STND_LOG_LEVEL 50 diff --git a/src/st-info.c b/src/tools/info.c similarity index 99% rename from src/st-info.c rename to src/tools/info.c index 1671468f0..e29184e5a 100644 --- a/src/st-info.c +++ b/src/tools/info.c @@ -3,7 +3,7 @@ #include #include -#include +#include static void usage(void) { diff --git a/src/st-term.c b/src/tools/term.c similarity index 99% rename from src/st-term.c rename to src/tools/term.c index 245ed5949..9b46e2a4c 100644 --- a/src/st-term.c +++ b/src/tools/term.c @@ -9,7 +9,8 @@ #include #include #include -#include "stlink-common.h" + +#include /* STLinky structure on STM chip diff --git a/src/stlink-usb.c b/src/usb.c similarity index 99% rename from src/stlink-usb.c rename to src/usb.c index 98654129e..e8d8ec39d 100644 --- a/src/stlink-usb.c +++ b/src/usb.c @@ -8,8 +8,7 @@ #include #include -#include "stlink-common.h" -#include "stlink-usb.h" +#include "stlink.h" enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; diff --git a/src/test_sg.c b/tests/stlink_sg.c similarity index 100% rename from src/test_sg.c rename to tests/stlink_sg.c diff --git a/src/test_usb.c b/tests/stlink_usb.c similarity index 100% rename from src/test_usb.c rename to tests/stlink_usb.c From bd21ced1ab457e38e87649c3746b10f6d8d04199 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 5 May 2016 19:49:16 +0200 Subject: [PATCH 0407/1435] README.md: Recover removed symlink to README --- README.md | 1 + 1 file changed, 1 insertion(+) create mode 120000 README.md diff --git a/README.md b/README.md new file mode 120000 index 000000000..100b93820 --- /dev/null +++ b/README.md @@ -0,0 +1 @@ +README \ No newline at end of file From c267a3aaa84d2788940010f51568b99192f86436 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 5 May 2016 20:02:30 +0200 Subject: [PATCH 0408/1435] Update LICENSE with stlink contributors and notice license in README --- LICENSE | 14 ++++++++------ README | 4 ++++ 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/LICENSE b/LICENSE index 37b124eba..3d464ca1e 100644 --- a/LICENSE +++ b/LICENSE @@ -1,3 +1,5 @@ +Copyright (c) 2011 The stlink project (github.com/texane/stlink) contributors. + All rights reserved. Copyright (c) 2011 The "Capt'ns Missing Link" Authors. All rights reserved. Redistribution and use in source and binary forms, with or without @@ -5,14 +7,14 @@ modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright -notice, this list of conditions and the following disclaimer. + notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above -copyright notice, this list of conditions and the following disclaimer -in the documentation and/or other materials provided with the -distribution. + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials provided + with the distribution. * Neither the name of Martin Capitanio nor the names of its -contributors may be used to endorse or promote products derived from -this software without specific prior written permission. + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT diff --git a/README b/README index da7fafa32..90bc0849d 100644 --- a/README +++ b/README @@ -230,3 +230,7 @@ STLink v2-1 (as found on the Nucleo boards), known working targets: * STM32L053R8 (STM32 Nucleo-L053R8 board) Please report any and all known working combinations so I can update this! + +## License + +The stlink library and tools are licensed under the [BSD license](LICENSE) From e30fcd4fd0b3d71b189cf30d81a84b2231de5714 Mon Sep 17 00:00:00 2001 From: Piotr Haber Date: Thu, 24 Mar 2016 10:03:31 +0100 Subject: [PATCH 0409/1435] Add support for L0x Category 5 devices --- include/stlink.h | 13 +++++++++++++ src/common.c | 8 ++++---- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index 24b4dcf6e..c29e2a663 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -137,6 +137,7 @@ extern "C" { #define STM32_CHIPID_F04 0x445 #define STM32_CHIPID_F303_HIGH 0x446 +#define STM32_CHIPID_L0_CAT5 0x447 #define STM32_CHIPID_F0_CAN 0x448 @@ -504,6 +505,18 @@ extern "C" { .bootrom_base = 0x1ff0000, .bootrom_size = 0x1000 }, + { + // STM32L0x Category 5 + // RM0367,RM0377 documents was used to find these parameters + .chip_id = STM32_CHIPID_L0_CAT5, + .description = "L0x Category 5 device", + .flash_type = FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x5000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x2000 + }, { // STM32F334 // RM0364 document was used to find these parameters diff --git a/src/common.c b/src/common.c index 3e87824f1..a167bb6d4 100644 --- a/src/common.c +++ b/src/common.c @@ -1288,7 +1288,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) uint32_t val; uint32_t flash_regs_base; - if (sl->chip_id == STM32_CHIPID_L0) { + if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; } else { flash_regs_base = STM32L_FLASH_REGS_ADDR; @@ -1667,7 +1667,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); - } else if (sl->chip_id == STM32_CHIPID_L0) { + } else if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5) { loader_code = loader_code_stm32l0; loader_size = sizeof(loader_code_stm32l0); } else if (sl->chip_id == STM32_CHIPID_L4) { @@ -1747,7 +1747,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin uint32_t flash_regs_base; flash_loader_t fl; - if (sl->chip_id == STM32_CHIPID_L0) { + if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; } else { flash_regs_base = STM32L_FLASH_REGS_ADDR; @@ -1914,7 +1914,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t uint32_t flash_regs_base; uint32_t pagesize; - if (sl->chip_id == STM32_CHIPID_L0) { + if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; pagesize = L0_WRITE_BLOCK_SIZE; } else { From f5d6cec4c72989fe2bb8ec4f4d03cce6f4505d23 Mon Sep 17 00:00:00 2001 From: Tom de Boer Date: Fri, 6 May 2016 13:47:00 +0200 Subject: [PATCH 0410/1435] Fix for broken STML0 and STML1 Commits 907383da8ef95fedc630cdf7cf102d44ae229200 and e43a737c3c9ffe56045181b306509c942fd9998a were causing issues for people with STML0's and STML1's. This commit reverses the changes in these two commits. --- flashloaders/stm32l0x.s | 20 +++++----- flashloaders/stm32lx.s | 20 +++++----- src/common.c | 87 ++++++++++++++++++++++++----------------- 3 files changed, 74 insertions(+), 53 deletions(-) diff --git a/flashloaders/stm32l0x.s b/flashloaders/stm32l0x.s index fcbd06e39..9fc44468f 100644 --- a/flashloaders/stm32l0x.s +++ b/flashloaders/stm32l0x.s @@ -34,29 +34,31 @@ .global write /* - r0 - source address - r1 - destination address + r0 - destination address + r1 - source address r2 - count */ + // Set 0 to r3 + movs r3, #0 // Go to compare - b test_done + b.n test_done write_word: // Load one word from address in r0, increment by 4 - ldr r4, [r0] + ldr r4, [r1] // Store the word to address in r1, increment by 4 - str r4, [r1] - // Decrement r2 - subs r2, #1 + str r4, [r0] + // Increment r3 + adds r3, #1 adds r1, #4 // does not matter, only first addr is important // next 15 bytes are in sequnce RM0367 page 66 adds r0, #4 test_done: - // Test r2 - cmp r2, #0 + // Compare r3 and r2 + cmp r3, r2 // Loop if not zero bcc.n write_word diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s index bb8f7c93f..799d1345c 100644 --- a/flashloaders/stm32lx.s +++ b/flashloaders/stm32lx.s @@ -34,25 +34,27 @@ .global write /* - r0 - source address - r1 - destination address + r0 - destination address + r1 - source address r2 - count */ + // Set 0 to r3 + movs r3, #0 // Go to compare - b test_done + b.n test_done write_word: // Load one word from address in r0, increment by 4 - ldr.w ip, [r0], #4 + ldr.w ip, [r1], #4 // Store the word to address in r1, increment by 4 - str.w ip, [r1], #4 - // Decrement r2 - subs r2, #1 + str.w ip, [r0], #4 + // Increment r3 + adds r3, #1 test_done: - // Test r2 - cmp r2, #0 + // Compare r3 and r2 + cmp r3, r2 // Loop if not zero bcc.n write_word diff --git a/src/common.c b/src/common.c index a167bb6d4..7504c27ac 100644 --- a/src/common.c +++ b/src/common.c @@ -593,12 +593,6 @@ int stlink_load_device_params(stlink_t *sl) { return -1; } - if (params->flash_type == FLASH_TYPE_UNKNOWN) { - WLOG("Invalid flash type, please check device declaration\n"); - return -1; - } - - // These are fixed... sl->flash_base = STM32_FLASH_BASE; sl->sram_base = STM32_SRAM_BASE; @@ -1511,19 +1505,20 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { static const uint8_t loader_code_stm32l[] = { /* openocd.git/contrib/loaders/flash/stm32lx.S - r0, input, source addr - r1, input, dest addr + r0, input, dest addr + r1, input, source addr r2, input, word count - r2, output, remaining word count + r3, output, word count */ + 0x00, 0x23, 0x04, 0xe0, - 0x50, 0xf8, 0x04, 0xcb, - 0x41, 0xf8, 0x04, 0xcb, - 0x01, 0x3a, + 0x51, 0xf8, 0x04, 0xcb, + 0x40, 0xf8, 0x04, 0xcb, + 0x01, 0x33, - 0x00, 0x2a, + 0x93, 0x42, 0xf8, 0xd3, 0x00, 0xbe }; @@ -1531,21 +1526,22 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { static const uint8_t loader_code_stm32l0[] = { /* - r0, input, source addr - r1, input, dest addr + r0, input, dest addr + r1, input, source addr r2, input, word count - r2, output, remaining word count + r3, output, word count */ + 0x00, 0x23, 0x04, 0xe0, - 0x04, 0x68, - 0x0c, 0x60, - 0x01, 0x3a, + 0x0c, 0x68, + 0x04, 0x60, + 0x01, 0x33, 0x04, 0x31, 0x04, 0x30, - 0x00, 0x2a, + 0x93, 0x42, 0xf8, 0xd3, 0x00, 0xbe }; @@ -1608,7 +1604,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0xfb, 0xd1, // bne.n 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8 - 0xa2, 0xf1, 0x01, 0x02, // sub.w r2, r2, #1 + 0xa2, 0xf1, 0x02, 0x02, // add.w r2, r2, #2 0xef, 0xe7, // b.n 0x00, 0xbe, // done: bkpt 0x0000 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000 @@ -2072,8 +2068,8 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { reg rr; - int i = 0; - size_t count = 0; + int target_reg, source_reg, i = 0; + size_t count; DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); // FIXME This can never return -1 @@ -2083,23 +2079,36 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - if (sl->flash_type == FLASH_TYPE_F0) { + if (sl->flash_type == FLASH_TYPE_L0) { + count = size / sizeof(uint32_t); + if (size % sizeof(uint32_t)) + ++count; + target_reg = 0; + source_reg = 1; + } else if (sl->flash_type == FLASH_TYPE_F0) { count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; - } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L0) { + target_reg = 1; + source_reg = 0; + } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) { count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; - } else if (sl->flash_type == FLASH_TYPE_L4) { - count = size / sizeof(uint64_t); - if (size % sizeof(uint64_t)) - ++count; + if (sl->chip_id == STM32_CHIPID_L4) { + if (count % 2) + ++count; + } + target_reg = 1; + source_reg = 0; + } else { + fprintf(stderr, "unknown coreid 0x%x, don't know what flash loader to use\n", sl->core_id); + return -1; } /* setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); /* source */ - stlink_write_reg(sl, target, 1); /* target */ + stlink_write_reg(sl, fl->buf_addr, source_reg); /* source */ + stlink_write_reg(sl, target, target_reg); /* target */ stlink_write_reg(sl, count, 2); /* count */ stlink_write_reg(sl, 0, 3); /* flash bank 0 (input), only used on F0, but armless fopr others */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ @@ -2120,11 +2129,19 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } + stlink_read_all_regs(sl, &rr); + /* check written byte count */ - stlink_read_reg(sl, 2, &rr); - if (rr.r[2] != 0) { - fprintf(stderr, "write error, count == %u\n", rr.r[2]); - return -1; + if (sl->flash_type == FLASH_TYPE_L0) { + if (rr.r[3] != count) { + fprintf(stderr, "write error, count == %u\n", rr.r[3]); + return -1; + } + } else { + if (rr.r[2] != 0) { + fprintf(stderr, "write error, count == %u\n", rr.r[2]); + return -1; + } } return 0; From 26949364f707622f01f246c58715f65cd8bb6cdb Mon Sep 17 00:00:00 2001 From: Tom de Boer Date: Fri, 6 May 2016 13:47:00 +0200 Subject: [PATCH 0411/1435] Fixed the STM32L-problem according to @gluedig See https://github.com/texane/stlink/issues/390#issuecomment-217382832 --- flashloaders/stm32l0x.s | 20 ++++----- flashloaders/stm32lx.s | 22 +++++----- src/common.c | 92 +++++++++++++++++------------------------ 3 files changed, 57 insertions(+), 77 deletions(-) diff --git a/flashloaders/stm32l0x.s b/flashloaders/stm32l0x.s index 9fc44468f..fcbd06e39 100644 --- a/flashloaders/stm32l0x.s +++ b/flashloaders/stm32l0x.s @@ -34,31 +34,29 @@ .global write /* - r0 - destination address - r1 - source address + r0 - source address + r1 - destination address r2 - count */ - // Set 0 to r3 - movs r3, #0 // Go to compare - b.n test_done + b test_done write_word: // Load one word from address in r0, increment by 4 - ldr r4, [r1] + ldr r4, [r0] // Store the word to address in r1, increment by 4 - str r4, [r0] - // Increment r3 - adds r3, #1 + str r4, [r1] + // Decrement r2 + subs r2, #1 adds r1, #4 // does not matter, only first addr is important // next 15 bytes are in sequnce RM0367 page 66 adds r0, #4 test_done: - // Compare r3 and r2 - cmp r3, r2 + // Test r2 + cmp r2, #0 // Loop if not zero bcc.n write_word diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s index 799d1345c..f162c8827 100644 --- a/flashloaders/stm32lx.s +++ b/flashloaders/stm32lx.s @@ -34,29 +34,27 @@ .global write /* - r0 - destination address - r1 - source address + r0 - source address + r1 - destination address r2 - count */ - // Set 0 to r3 - movs r3, #0 // Go to compare - b.n test_done + b test_done write_word: // Load one word from address in r0, increment by 4 - ldr.w ip, [r1], #4 + ldr.w ip, [r0], #4 // Store the word to address in r1, increment by 4 - str.w ip, [r0], #4 - // Increment r3 - adds r3, #1 + str.w ip, [r1], #4 + // Decrement r2 + subs r2, #1 test_done: - // Compare r3 and r2 - cmp r3, r2 + // Test r2 + cmp r2, #0 // Loop if not zero - bcc.n write_word + bhi write_word // Set breakpoint to exit bkpt #0x00 diff --git a/src/common.c b/src/common.c index 7504c27ac..f8251a8c0 100644 --- a/src/common.c +++ b/src/common.c @@ -593,6 +593,12 @@ int stlink_load_device_params(stlink_t *sl) { return -1; } + if (params->flash_type == FLASH_TYPE_UNKNOWN) { + WLOG("Invalid flash type, please check device declaration\n"); + return -1; + } + + // These are fixed... sl->flash_base = STM32_FLASH_BASE; sl->sram_base = STM32_SRAM_BASE; @@ -1505,43 +1511,42 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { static const uint8_t loader_code_stm32l[] = { /* openocd.git/contrib/loaders/flash/stm32lx.S - r0, input, dest addr - r1, input, source addr + r0, input, source addr + r1, input, dest addr r2, input, word count - r3, output, word count + r2, output, remaining word count */ - 0x00, 0x23, 0x04, 0xe0, - 0x51, 0xf8, 0x04, 0xcb, - 0x40, 0xf8, 0x04, 0xcb, - 0x01, 0x33, + 0x50, 0xf8, 0x04, 0xcb, + 0x41, 0xf8, 0x04, 0xcb, + 0x01, 0x3a, - 0x93, 0x42, - 0xf8, 0xd3, - 0x00, 0xbe + 0x00, 0x2a, + 0xf8, 0xd8, + 0x00, 0xbe, + 0x00, 0x00 }; static const uint8_t loader_code_stm32l0[] = { /* - r0, input, dest addr - r1, input, source addr + r0, input, source addr + r1, input, dest addr r2, input, word count - r3, output, word count + r2, output, remaining word count */ - 0x00, 0x23, 0x04, 0xe0, - 0x0c, 0x68, - 0x04, 0x60, - 0x01, 0x33, + 0x04, 0x68, + 0x0c, 0x60, + 0x01, 0x3a, 0x04, 0x31, 0x04, 0x30, - 0x93, 0x42, + 0x00, 0x2a, 0xf8, 0xd3, 0x00, 0xbe }; @@ -1604,7 +1609,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0xfb, 0xd1, // bne.n 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8 - 0xa2, 0xf1, 0x02, 0x02, // add.w r2, r2, #2 + 0xa2, 0xf1, 0x01, 0x02, // sub.w r2, r2, #1 0xef, 0xe7, // b.n 0x00, 0xbe, // done: bkpt 0x0000 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000 @@ -2068,8 +2073,8 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { reg rr; - int target_reg, source_reg, i = 0; - size_t count; + int i = 0; + size_t count = 0; DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); // FIXME This can never return -1 @@ -2079,36 +2084,23 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - if (sl->flash_type == FLASH_TYPE_L0) { - count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) - ++count; - target_reg = 0; - source_reg = 1; - } else if (sl->flash_type == FLASH_TYPE_F0) { + if (sl->flash_type == FLASH_TYPE_F0) { count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; - target_reg = 1; - source_reg = 0; - } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) { + } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L0) { count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; - if (sl->chip_id == STM32_CHIPID_L4) { - if (count % 2) - ++count; - } - target_reg = 1; - source_reg = 0; - } else { - fprintf(stderr, "unknown coreid 0x%x, don't know what flash loader to use\n", sl->core_id); - return -1; + } else if (sl->flash_type == FLASH_TYPE_L4) { + count = size / sizeof(uint64_t); + if (size % sizeof(uint64_t)) + ++count; } /* setup core */ - stlink_write_reg(sl, fl->buf_addr, source_reg); /* source */ - stlink_write_reg(sl, target, target_reg); /* target */ + stlink_write_reg(sl, fl->buf_addr, 0); /* source */ + stlink_write_reg(sl, target, 1); /* target */ stlink_write_reg(sl, count, 2); /* count */ stlink_write_reg(sl, 0, 3); /* flash bank 0 (input), only used on F0, but armless fopr others */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ @@ -2129,19 +2121,11 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - stlink_read_all_regs(sl, &rr); - /* check written byte count */ - if (sl->flash_type == FLASH_TYPE_L0) { - if (rr.r[3] != count) { - fprintf(stderr, "write error, count == %u\n", rr.r[3]); - return -1; - } - } else { - if (rr.r[2] != 0) { - fprintf(stderr, "write error, count == %u\n", rr.r[2]); - return -1; - } + stlink_read_reg(sl, 2, &rr); + if (rr.r[2] != 0) { + fprintf(stderr, "write error, count == %u\n", rr.r[2]); + return -1; } return 0; From 17ab4bcaa88c81ba7f952f8bfed0fb3387a4eaa0 Mon Sep 17 00:00:00 2001 From: Piotr Haber Date: Mon, 9 May 2016 08:22:11 +0200 Subject: [PATCH 0412/1435] Revert "Merge pull request #407 from tomdeboer/STML1_Fix" This reverts commit a591a30f85a3e6b152f94cd5cc1eb5ae113a3517, reversing changes made to 0bb22e9ed6c2c0899fc31ee71dcbc59f1211d893. --- flashloaders/stm32l0x.s | 20 +++++----- flashloaders/stm32lx.s | 20 +++++----- src/common.c | 87 +++++++++++++++++------------------------ 3 files changed, 53 insertions(+), 74 deletions(-) diff --git a/flashloaders/stm32l0x.s b/flashloaders/stm32l0x.s index 9fc44468f..fcbd06e39 100644 --- a/flashloaders/stm32l0x.s +++ b/flashloaders/stm32l0x.s @@ -34,31 +34,29 @@ .global write /* - r0 - destination address - r1 - source address + r0 - source address + r1 - destination address r2 - count */ - // Set 0 to r3 - movs r3, #0 // Go to compare - b.n test_done + b test_done write_word: // Load one word from address in r0, increment by 4 - ldr r4, [r1] + ldr r4, [r0] // Store the word to address in r1, increment by 4 - str r4, [r0] - // Increment r3 - adds r3, #1 + str r4, [r1] + // Decrement r2 + subs r2, #1 adds r1, #4 // does not matter, only first addr is important // next 15 bytes are in sequnce RM0367 page 66 adds r0, #4 test_done: - // Compare r3 and r2 - cmp r3, r2 + // Test r2 + cmp r2, #0 // Loop if not zero bcc.n write_word diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s index 799d1345c..bb8f7c93f 100644 --- a/flashloaders/stm32lx.s +++ b/flashloaders/stm32lx.s @@ -34,27 +34,25 @@ .global write /* - r0 - destination address - r1 - source address + r0 - source address + r1 - destination address r2 - count */ - // Set 0 to r3 - movs r3, #0 // Go to compare - b.n test_done + b test_done write_word: // Load one word from address in r0, increment by 4 - ldr.w ip, [r1], #4 + ldr.w ip, [r0], #4 // Store the word to address in r1, increment by 4 - str.w ip, [r0], #4 - // Increment r3 - adds r3, #1 + str.w ip, [r1], #4 + // Decrement r2 + subs r2, #1 test_done: - // Compare r3 and r2 - cmp r3, r2 + // Test r2 + cmp r2, #0 // Loop if not zero bcc.n write_word diff --git a/src/common.c b/src/common.c index 7504c27ac..a167bb6d4 100644 --- a/src/common.c +++ b/src/common.c @@ -593,6 +593,12 @@ int stlink_load_device_params(stlink_t *sl) { return -1; } + if (params->flash_type == FLASH_TYPE_UNKNOWN) { + WLOG("Invalid flash type, please check device declaration\n"); + return -1; + } + + // These are fixed... sl->flash_base = STM32_FLASH_BASE; sl->sram_base = STM32_SRAM_BASE; @@ -1505,20 +1511,19 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { static const uint8_t loader_code_stm32l[] = { /* openocd.git/contrib/loaders/flash/stm32lx.S - r0, input, dest addr - r1, input, source addr + r0, input, source addr + r1, input, dest addr r2, input, word count - r3, output, word count + r2, output, remaining word count */ - 0x00, 0x23, 0x04, 0xe0, - 0x51, 0xf8, 0x04, 0xcb, - 0x40, 0xf8, 0x04, 0xcb, - 0x01, 0x33, + 0x50, 0xf8, 0x04, 0xcb, + 0x41, 0xf8, 0x04, 0xcb, + 0x01, 0x3a, - 0x93, 0x42, + 0x00, 0x2a, 0xf8, 0xd3, 0x00, 0xbe }; @@ -1526,22 +1531,21 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { static const uint8_t loader_code_stm32l0[] = { /* - r0, input, dest addr - r1, input, source addr + r0, input, source addr + r1, input, dest addr r2, input, word count - r3, output, word count + r2, output, remaining word count */ - 0x00, 0x23, 0x04, 0xe0, - 0x0c, 0x68, - 0x04, 0x60, - 0x01, 0x33, + 0x04, 0x68, + 0x0c, 0x60, + 0x01, 0x3a, 0x04, 0x31, 0x04, 0x30, - 0x93, 0x42, + 0x00, 0x2a, 0xf8, 0xd3, 0x00, 0xbe }; @@ -1604,7 +1608,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { 0xfb, 0xd1, // bne.n 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8 - 0xa2, 0xf1, 0x02, 0x02, // add.w r2, r2, #2 + 0xa2, 0xf1, 0x01, 0x02, // sub.w r2, r2, #1 0xef, 0xe7, // b.n 0x00, 0xbe, // done: bkpt 0x0000 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000 @@ -2068,8 +2072,8 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { reg rr; - int target_reg, source_reg, i = 0; - size_t count; + int i = 0; + size_t count = 0; DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); // FIXME This can never return -1 @@ -2079,36 +2083,23 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - if (sl->flash_type == FLASH_TYPE_L0) { - count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) - ++count; - target_reg = 0; - source_reg = 1; - } else if (sl->flash_type == FLASH_TYPE_F0) { + if (sl->flash_type == FLASH_TYPE_F0) { count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; - target_reg = 1; - source_reg = 0; - } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) { + } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L0) { count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; - if (sl->chip_id == STM32_CHIPID_L4) { - if (count % 2) - ++count; - } - target_reg = 1; - source_reg = 0; - } else { - fprintf(stderr, "unknown coreid 0x%x, don't know what flash loader to use\n", sl->core_id); - return -1; + } else if (sl->flash_type == FLASH_TYPE_L4) { + count = size / sizeof(uint64_t); + if (size % sizeof(uint64_t)) + ++count; } /* setup core */ - stlink_write_reg(sl, fl->buf_addr, source_reg); /* source */ - stlink_write_reg(sl, target, target_reg); /* target */ + stlink_write_reg(sl, fl->buf_addr, 0); /* source */ + stlink_write_reg(sl, target, 1); /* target */ stlink_write_reg(sl, count, 2); /* count */ stlink_write_reg(sl, 0, 3); /* flash bank 0 (input), only used on F0, but armless fopr others */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ @@ -2129,19 +2120,11 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons return -1; } - stlink_read_all_regs(sl, &rr); - /* check written byte count */ - if (sl->flash_type == FLASH_TYPE_L0) { - if (rr.r[3] != count) { - fprintf(stderr, "write error, count == %u\n", rr.r[3]); - return -1; - } - } else { - if (rr.r[2] != 0) { - fprintf(stderr, "write error, count == %u\n", rr.r[2]); - return -1; - } + stlink_read_reg(sl, 2, &rr); + if (rr.r[2] != 0) { + fprintf(stderr, "write error, count == %u\n", rr.r[2]); + return -1; } return 0; From 013fc429de40f3e233e7831c4a90f778d42d70a3 Mon Sep 17 00:00:00 2001 From: Piotr Haber Date: Fri, 6 May 2016 09:08:31 +0200 Subject: [PATCH 0413/1435] fix for L0 flash loader --- src/common.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/src/common.c b/src/common.c index a167bb6d4..883a04548 100644 --- a/src/common.c +++ b/src/common.c @@ -1537,17 +1537,18 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { r2, output, remaining word count */ - 0x04, 0xe0, - - 0x04, 0x68, - 0x0c, 0x60, - 0x01, 0x3a, - 0x04, 0x31, - 0x04, 0x30, - - 0x00, 0x2a, - 0xf8, 0xd3, - 0x00, 0xbe + 0x00, 0xbf, // nop /* to make loader length % 4 = 0 */ + 0x04, 0xe0, // b test_done /* Go to compare */ + //write_word + 0x04, 0x68, // ldr r4, [r0] /* Load one word from address in r0 */ + 0x0c, 0x60, // str r4, [r1] /* Store the word to address in r1 */ + 0x04, 0x30, // adds r0, #4 /* Increment r0 */ + 0x04, 0x31, // adds r1, #4 /* Increment r1 */ + 0x01, 0x3a, // subs r2, #1 /* Decrement r2 */ + //test_done: + 0x00, 0x2a, // cmp r2, #0 /* Compare r2 to 0 */ + 0xf8, 0xd8, // bhi write_word /* Loop if above 0 */ + 0x00, 0xbe // bkpt #0x00 /* Set breakpoint to exit */ }; static const uint8_t loader_code_stm32f4[] = { From d8c4e7c1bd29921c2b24703d264669b9c711bae9 Mon Sep 17 00:00:00 2001 From: Piotr Haber Date: Mon, 9 May 2016 08:45:50 +0200 Subject: [PATCH 0414/1435] merge L0 and L1 flash loader --- src/common.c | 28 +++------------------------- 1 file changed, 3 insertions(+), 25 deletions(-) diff --git a/src/common.c b/src/common.c index 883a04548..456c0b173 100644 --- a/src/common.c +++ b/src/common.c @@ -1510,27 +1510,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { static const uint8_t loader_code_stm32l[] = { - /* openocd.git/contrib/loaders/flash/stm32lx.S - r0, input, source addr - r1, input, dest addr - r2, input, word count - r2, output, remaining word count - */ - - 0x04, 0xe0, - - 0x50, 0xf8, 0x04, 0xcb, - 0x41, 0xf8, 0x04, 0xcb, - 0x01, 0x3a, - - 0x00, 0x2a, - 0xf8, 0xd3, - 0x00, 0xbe - }; - - static const uint8_t loader_code_stm32l0[] = { - - /* + /* based on openocd.git/contrib/loaders/flash/stm32lx.S r0, input, source addr r1, input, dest addr r2, input, word count @@ -1637,7 +1617,8 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH - || sl->chip_id == STM32_CHIPID_L152_RE) { /* stm32l */ + || sl->chip_id == STM32_CHIPID_L152_RE + || sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID @@ -1668,9 +1649,6 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); - } else if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5) { - loader_code = loader_code_stm32l0; - loader_size = sizeof(loader_code_stm32l0); } else if (sl->chip_id == STM32_CHIPID_L4) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); From 75ed6cfb9f461337cef2d42f14dfafb342812e44 Mon Sep 17 00:00:00 2001 From: Tom de Boer Date: Mon, 9 May 2016 10:55:57 +0200 Subject: [PATCH 0415/1435] Formatted comments and stm32lx.s --- flashloaders/stm32lx.s | 4 ++-- src/common.c | 34 ++++++++++++++-------------------- 2 files changed, 16 insertions(+), 22 deletions(-) diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s index f162c8827..10e5644bf 100644 --- a/flashloaders/stm32lx.s +++ b/flashloaders/stm32lx.s @@ -25,7 +25,7 @@ ***************************************************************************/ -// Build : arm-eabi-gcc -c stm32lx.S +// Build : arm-eabi-gcc -c stm32lx.s .text .syntax unified .cpu cortex-m3 @@ -36,7 +36,7 @@ /* r0 - source address r1 - destination address - r2 - count + r2 - output, remaining word count */ // Go to compare diff --git a/src/common.c b/src/common.c index 456c0b173..a3ffda7e4 100644 --- a/src/common.c +++ b/src/common.c @@ -1509,26 +1509,20 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { }; static const uint8_t loader_code_stm32l[] = { - - /* based on openocd.git/contrib/loaders/flash/stm32lx.S - r0, input, source addr - r1, input, dest addr - r2, input, word count - r2, output, remaining word count - */ - - 0x00, 0xbf, // nop /* to make loader length % 4 = 0 */ - 0x04, 0xe0, // b test_done /* Go to compare */ - //write_word - 0x04, 0x68, // ldr r4, [r0] /* Load one word from address in r0 */ - 0x0c, 0x60, // str r4, [r1] /* Store the word to address in r1 */ - 0x04, 0x30, // adds r0, #4 /* Increment r0 */ - 0x04, 0x31, // adds r1, #4 /* Increment r1 */ - 0x01, 0x3a, // subs r2, #1 /* Decrement r2 */ - //test_done: - 0x00, 0x2a, // cmp r2, #0 /* Compare r2 to 0 */ - 0xf8, 0xd8, // bhi write_word /* Loop if above 0 */ - 0x00, 0xbe // bkpt #0x00 /* Set breakpoint to exit */ + // flashloaders/stm32lx.s + + 0x04, 0xe0, // b test_done ; Go to compare + // write_word: + 0x04, 0x68, // ldr r4, [r0] ; Load one word from address in r0 + 0x0c, 0x60, // str r4, [r1] ; Store the word to address in r1 + 0x04, 0x30, // adds r0, #4 ; Increment r0 + 0x04, 0x31, // adds r1, #4 ; Increment r1 + 0x01, 0x3a, // subs r2, #1 ; Decrement r2 + // test_done: + 0x00, 0x2a, // cmp r2, #0 ; Compare r2 to 0 + 0xf8, 0xd8, // bhi write_word ; Loop if above 0 + 0x00, 0xbe, // bkpt #0x00 ; Set breakpoint to exit + 0x00, 0x00 }; static const uint8_t loader_code_stm32f4[] = { From 742eba2cd64fdac65275213d2b2773f8a82b5164 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Wed, 11 May 2016 07:33:41 +0200 Subject: [PATCH 0416/1435] Reorganize stlink-gui and update README, add building gui with Travis CI on linux --- .travis.sh | 8 ++++++-- CMakeLists.txt | 6 +++--- Makefile.am | 2 +- README | 3 ++- configure.ac | 16 ++++++++-------- {gui => src/tools/gui}/Makefile.am | 6 +++--- {gui => src/tools/gui}/stlink-gui.c | 2 +- {gui => src/tools/gui}/stlink-gui.h | 0 {gui => src/tools/gui}/stlink-gui.ui | 0 9 files changed, 24 insertions(+), 19 deletions(-) rename {gui => src/tools/gui}/Makefile.am (89%) rename {gui => src/tools/gui}/stlink-gui.c (99%) rename {gui => src/tools/gui}/stlink-gui.h (100%) rename {gui => src/tools/gui}/stlink-gui.ui (100%) diff --git a/.travis.sh b/.travis.sh index 6b69c638a..13d2c1dcd 100755 --- a/.travis.sh +++ b/.travis.sh @@ -1,7 +1,7 @@ #!/bin/bash if [ "$TRAVIS_OS_NAME" != "osx" ]; then sudo apt-get update -qq || true - sudo apt-get install -qq -y --no-install-recommends libusb-1.0.0-dev + sudo apt-get install -qq -y --no-install-recommends libusb-1.0.0-dev libgtk-3-dev else brew install libusb fi @@ -13,6 +13,10 @@ if [ "$BUILD_SYSTEM" == "cmake" ]; then make else ./autogen.sh - ./configure + if [ "$TRAVIS_OS_NAME" == "osx" ]; then + ./configure + else + ./configure --with-gtk-gui + fi make fi diff --git a/CMakeLists.txt b/CMakeLists.txt index f75ce611d..1c56ed49d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -97,8 +97,8 @@ endif() if(gtk_FOUND) include_directories(${gtk_INCLUDE_DIRS}) - set(GUI_SOURCES gui/stlink-gui.c - gui/stlink-gui.h) + set(GUI_SOURCES src/tools/gui/stlink-gui.c + src/tools/gui/stlink-gui.h) add_executable(stlink-gui-local ${GUI_SOURCES}) set_target_properties(stlink-gui-local PROPERTIES @@ -113,6 +113,6 @@ if(gtk_FOUND) install(TARGETS stlink-gui RUNTIME DESTINATION bin) - install(FILES gui/stlink-gui.ui + install(FILES src/tools/gui/stlink-gui.ui DESTINATION ${INSTALLED_UI_DIR}) endif() diff --git a/Makefile.am b/Makefile.am index fc95184bc..7494913ac 100644 --- a/Makefile.am +++ b/Makefile.am @@ -1,6 +1,6 @@ # Makefile.am -- Process this file with automake to produce Makefile.in -SUBDIRS = . $(MAYBE_GUI) +SUBDIRS = . $(STLINK_HAS_GUI) AUTOMAKE_OPTIONS = subdir-objects diff --git a/README b/README index 90bc0849d..89bb188c9 100644 --- a/README +++ b/README @@ -21,6 +21,7 @@ Two different transport layers are used: * `pkg-config` * `libusb-1.0` (plus development headers for building, on debian based distros `libusb-1.0.0-dev` package) +* (optional) for `stlink-gui` we need libgtk-3-dev ## For STLINKv1 @@ -48,7 +49,7 @@ following steps will build the project for you. ``` $ ./autogen.sh -$ ./configure +$ ./configure --with-gtk-gui $ make ``` diff --git a/configure.ac b/configure.ac index f37471740..7a101d55d 100644 --- a/configure.ac +++ b/configure.ac @@ -2,7 +2,7 @@ # Process this file with autoconf to produce a configure script. AC_PREREQ(2.61) -AC_INIT([stlink],[0.5.6],[davem@devkitpro.org]) +AC_INIT([stlink],[1.2.0],[davem@devkitpro.org]) AC_CONFIG_SRCDIR([src/common.c]) AC_CONFIG_LIBOBJ_DIR([src]) AM_INIT_AUTOMAKE([1.10]) @@ -44,15 +44,15 @@ case "${host}" in AM_CONDITIONAL(MINGW, false) esac -MAYBE_GUI= -AC_ARG_WITH([gtk], AS_HELP_STRING([--with-gtk], [enable GTK+ gui])) -if test "x$with_gtk" = "xyes"; then - PKG_CHECK_MODULES([GTK], [gtk+-3.0]) +STLINK_HAS_GUI= +AC_ARG_WITH([gtk_gui], AS_HELP_STRING([--with-gtk-gui], [enable GTK3+ gui])) +if test "x$with_gtk_gui" = "xyes"; then + PKG_CHECK_MODULES([GTK3], [gtk+-3.0]) PKG_CHECK_MODULES([GLIB], [glib-2.0 > 2.32.0]) - MAYBE_GUI=gui - AC_CONFIG_FILES([gui/Makefile]) + STLINK_HAS_GUI=src/tools/gui + AC_CONFIG_FILES([src/tools/gui/Makefile]) fi -AC_SUBST([MAYBE_GUI]) +AC_SUBST([STLINK_HAS_GUI]) AC_CONFIG_FILES([Makefile]) AC_OUTPUT diff --git a/gui/Makefile.am b/src/tools/gui/Makefile.am similarity index 89% rename from gui/Makefile.am rename to src/tools/gui/Makefile.am index 97b780e43..23e582fa8 100644 --- a/gui/Makefile.am +++ b/src/tools/gui/Makefile.am @@ -5,10 +5,10 @@ stlink_gui_SOURCES = \ stlink-gui.h stlink_gui_CPPFLAGS = \ - -I$(top_srcdir) \ + -I$(top_srcdir)/include \ $(AM_CPPFLAGS) \ -I$(top_srcdir)/src \ - @GTK_CFLAGS@ + @GTK3_CFLAGS@ stlink_gui_CFLAGS = \ $(WARN_CFLAGS) \ @@ -21,7 +21,7 @@ stlink_gui_LDFLAGS = \ stlink_gui_LDADD = \ $(INTLLIBS) \ $(top_builddir)/libstlink.a \ - @GTK_LIBS@ + @GTK3_LIBS@ uidir = $(pkgdatadir)/ui ui_DATA = stlink-gui.ui diff --git a/gui/stlink-gui.c b/src/tools/gui/stlink-gui.c similarity index 99% rename from gui/stlink-gui.c rename to src/tools/gui/stlink-gui.c index 93f92c462..944ad131b 100644 --- a/gui/stlink-gui.c +++ b/src/tools/gui/stlink-gui.c @@ -3,7 +3,7 @@ #include #include -#include "stlink-common.h" +#include #include "stlink-gui.h" #define MEM_READ_SIZE 1024 diff --git a/gui/stlink-gui.h b/src/tools/gui/stlink-gui.h similarity index 100% rename from gui/stlink-gui.h rename to src/tools/gui/stlink-gui.h diff --git a/gui/stlink-gui.ui b/src/tools/gui/stlink-gui.ui similarity index 100% rename from gui/stlink-gui.ui rename to src/tools/gui/stlink-gui.ui From 188496ce3d7eaa97d63f5c64c51966521ed3b453 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Wed, 11 May 2016 18:54:41 +0200 Subject: [PATCH 0417/1435] README.md: Document build dependencies, fixes #362 --- README | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/README b/README index 89bb188c9..f6ac729bc 100644 --- a/README +++ b/README @@ -19,7 +19,12 @@ Two different transport layers are used: ## Common requirements +* Debian based distros (debian, ubuntu) + * `build-essential` + * `pkg-config` +* `intltool` +* `cmake` or (`autoconf` && `automake && `autogen`) * `libusb-1.0` (plus development headers for building, on debian based distros `libusb-1.0.0-dev` package) * (optional) for `stlink-gui` we need libgtk-3-dev From c1cbc158b5dcc0eb59a99dcab9bc0535d2698925 Mon Sep 17 00:00:00 2001 From: texane Date: Wed, 11 May 2016 18:56:26 +0200 Subject: [PATCH 0418/1435] Fixing NULL to char assignment --- src/usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/usb.c b/src/usb.c index e8d8ec39d..9c04ec860 100644 --- a/src/usb.c +++ b/src/usb.c @@ -946,7 +946,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { ret = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)&serial, sizeof(serial)); if (ret < 0) - *serial = NULL; + *serial = 0; libusb_close(handle); From e83e1197af03cec838d377303eaf7dddf9e93c21 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 13 May 2016 12:16:16 +0200 Subject: [PATCH 0419/1435] Update ISSUE_TEMPLATE.md --- .github/ISSUE_TEMPLATE.md | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/.github/ISSUE_TEMPLATE.md b/.github/ISSUE_TEMPLATE.md index 861711912..932e9387f 100644 --- a/.github/ISSUE_TEMPLATE.md +++ b/.github/ISSUE_TEMPLATE.md @@ -1,3 +1,5 @@ +**NOTICE: The issue may be closed without notice when not enough information is provided!** + Thank you for giving feedback to the stlink project. Take some time to fill out check boxes with a X in the following items so developers and other people can try to to find out what is going on. And add/remove what is appropiate to your problem. @@ -8,9 +10,19 @@ When submitting a feature request, try to reuse the list and add/remove what is - [ ] Programmer firmware version: e.g STSW-LINK007 2.27.15 - [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) - [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 -- [ ] Target chip: e.g STM32F402VG +- [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` +- [ ] Target chip (and optional board): e.g STM32F402VG (STM32Fxxx Discovery) A as-detailed description possible of the problem with debug output when available. +Output: + +``` +OUTPUT/ERROR of the commandline tool(s) +``` + +Expected/description: +`short description of the expected value` + Thank you, The stlink project maintainers From 72b8e5ec87e4fa386a8e94fe68df29467d4354ce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81ron=20RADICS?= Date: Mon, 16 May 2016 03:52:46 +0200 Subject: [PATCH 0420/1435] Add L0 Category 2 device (chip id: 0x425) --- include/stlink.h | 13 +++++++++++++ src/common.c | 8 ++++---- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index c29e2a663..1ccbb8416 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -138,6 +138,7 @@ extern "C" { #define STM32_CHIPID_F303_HIGH 0x446 #define STM32_CHIPID_L0_CAT5 0x447 +#define STM32_CHIPID_L0_CAT2 0x425 #define STM32_CHIPID_F0_CAN 0x448 @@ -517,6 +518,18 @@ extern "C" { .bootrom_base = 0x1ff0000, .bootrom_size = 0x2000 }, + { + // STM32L0x Category 2 + // RM0367,RM0377 documents was used to find these parameters + .chip_id = STM32_CHIPID_L0_CAT2, + .description = "L0x Category 2 device", + .flash_type = FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000 + }, { // STM32F334 // RM0364 document was used to find these parameters diff --git a/src/common.c b/src/common.c index a3ffda7e4..24f9cd7fe 100644 --- a/src/common.c +++ b/src/common.c @@ -1288,7 +1288,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) uint32_t val; uint32_t flash_regs_base; - if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5) { + if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5 || sl->chip_id == STM32_CHIPID_L0_CAT2) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; } else { flash_regs_base = STM32L_FLASH_REGS_ADDR; @@ -1612,7 +1612,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH || sl->chip_id == STM32_CHIPID_L152_RE - || sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5) { /* stm32l */ + || sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5 || sl->chip_id == STM32_CHIPID_L0_CAT2) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID @@ -1720,7 +1720,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin uint32_t flash_regs_base; flash_loader_t fl; - if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5) { + if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5 || sl->chip_id == STM32_CHIPID_L0_CAT2) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; } else { flash_regs_base = STM32L_FLASH_REGS_ADDR; @@ -1887,7 +1887,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t uint32_t flash_regs_base; uint32_t pagesize; - if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5) { + if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5 || sl->chip_id == STM32_CHIPID_L0_CAT2) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; pagesize = L0_WRITE_BLOCK_SIZE; } else { From de1f05ce8150ae9cee92a9ddbf471b718ea81095 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Mon, 16 May 2016 10:21:04 +0200 Subject: [PATCH 0421/1435] Move chipid defines and deduplicate chipid params code --- CMakeLists.txt | 30 +-- Makefile.am | 2 + include/stlink.h | 465 +------------------------------------ include/stlink/chipid.h | 77 ++++++ src/chipid.c | 402 ++++++++++++++++++++++++++++++++ src/common.c | 68 +++--- src/gdbserver/gdb-server.c | 24 +- src/tools/flash.c | 2 +- src/tools/gui/stlink-gui.c | 14 +- src/tools/info.c | 25 +- 10 files changed, 560 insertions(+), 549 deletions(-) create mode 100644 include/stlink/chipid.h create mode 100644 src/chipid.c diff --git a/CMakeLists.txt b/CMakeLists.txt index 1c56ed49d..89bd85968 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -40,24 +40,28 @@ add_cflag_if_supported("-Wundef") add_cflag_if_supported("-fPIC") if(${CMAKE_BUILD_TYPE} MATCHES "Debug") - include(CTest) - add_cflag_if_supported("-ggdb") - add_cflag_if_supported("-O0") + include(CTest) + add_cflag_if_supported("-ggdb") + add_cflag_if_supported("-O0") elseif() - add_cflag_if_supported("-O2") + add_cflag_if_supported("-O2") endif() -set(STLINK_HEADERS include/stlink.h - include/stlink/usb.h - include/stlink/sg.h - include/stlink/logging.h - include/stlink/mmap.h +set(STLINK_HEADERS + include/stlink.h + include/stlink/usb.h + include/stlink/sg.h + include/stlink/logging.h + include/stlink/mmap.h + include/stlink/chipid.h ) -set(STLINK_SOURCE src/common.c - src/usb.c - src/sg.c - src/logging.c +set(STLINK_SOURCE + src/chipid.c + src/common.c + src/usb.c + src/sg.c + src/logging.c ) include_directories(${LIBUSB_INCLUDE_DIR}) diff --git a/Makefile.am b/Makefile.am index 7494913ac..a3114c6e4 100644 --- a/Makefile.am +++ b/Makefile.am @@ -18,6 +18,7 @@ st_info_SOURCES = src/tools/info.c st_util_SOURCES = src/gdbserver/gdb-remote.c src/gdbserver/gdb-remote.h src/gdbserver/gdb-server.c src/mingw/mingw.c src/mingw/mingw.h CFILES = \ + src/chipid.c \ src/common.c \ src/usb.c \ src/sg.c \ @@ -29,6 +30,7 @@ endif HFILES = \ include/stlink.h \ + include/stlink/chipid.h \ include/stlink/usb.h \ include/stlink/sg.h \ include/stlink/logging.h \ diff --git a/include/stlink.h b/include/stlink.h index 1ccbb8416..3941f4216 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -8,10 +8,14 @@ #define STLINK_H #include +#include #ifdef __cplusplus extern "C" { #endif + +#define STLINK_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) + // Max data transfer size. // 6kB = max mem32_read block, 8kB sram //#define Q_BUF_LEN 96 @@ -90,67 +94,6 @@ extern "C" { #define CORE_M3_R2 0x4BA00477 #define CORE_M4_R0 0x2BA01477 - /* - * Chip IDs are explained in the appropriate programming manual for the - * DBGMCU_IDCODE register (0xE0042000) - */ - // stm32 chipids, only lower 12 bits.. -#define STM32_CHIPID_F1_MEDIUM 0x410 -#define STM32_CHIPID_F2 0x411 -#define STM32_CHIPID_F1_LOW 0x412 -#define STM32_CHIPID_F4 0x413 -#define STM32_CHIPID_F1_HIGH 0x414 -#define STM32_CHIPID_L4 0x415 /* Seen on L4x6 (RM0351) */ -#define STM32_CHIPID_L1_MEDIUM 0x416 -#define STM32_CHIPID_L0 0x417 -#define STM32_CHIPID_F1_CONN 0x418 -#define STM32_CHIPID_F4_HD 0x419 -#define STM32_CHIPID_F1_VL_MEDIUM_LOW 0x420 - -#define STM32_CHIPID_F446 0x421 -#define STM32_CHIPID_F3 0x422 -#define STM32_CHIPID_F4_LP 0x423 - -#define STM32_CHIPID_F411RE 0x431 - -#define STM32_CHIPID_L1_MEDIUM_PLUS 0x427 -#define STM32_CHIPID_F1_VL_HIGH 0x428 -#define STM32_CHIPID_L1_CAT2 0x429 - -#define STM32_CHIPID_F1_XL 0x430 - -#define STM32_CHIPID_F37x 0x432 -#define STM32_CHIPID_F4_DE 0x433 -#define STM32_CHIPID_F4_DE 0x433 - -#define STM32_CHIPID_F4_DSI 0x434 - -#define STM32_CHIPID_L1_HIGH 0x436 -#define STM32_CHIPID_L152_RE 0x437 -#define STM32_CHIPID_F334 0x438 - -#define STM32_CHIPID_F3_SMALL 0x439 -#define STM32_CHIPID_F0 0x440 -#define STM32_CHIPID_F09X 0x442 -#define STM32_CHIPID_F0_SMALL 0x444 - -#define STM32_CHIPID_F04 0x445 - -#define STM32_CHIPID_F303_HIGH 0x446 -#define STM32_CHIPID_L0_CAT5 0x447 -#define STM32_CHIPID_L0_CAT2 0x425 - -#define STM32_CHIPID_F0_CAN 0x448 - -#define STM32_CHIPID_F7 0x449 - - /* - * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus" - * and some that are called "High". 0x427 is assigned to the other "Medium- - * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and - * 0x436 HIGH. - */ - // Constant STM32 memory map figures #define STM32_FLASH_BASE 0x08000000 #define STM32_SRAM_BASE 0x20000000 @@ -173,405 +116,7 @@ extern "C" { FLASH_TYPE_L4, }; - typedef struct chip_params_ { - uint32_t chip_id; - char* description; - enum flash_type flash_type; - uint32_t flash_size_reg; - uint32_t flash_pagesize; - uint32_t sram_size; - uint32_t bootrom_base, bootrom_size; - } chip_params_t; - - - // These maps are from a combination of the Programming Manuals, and - // also the Reference manuals. (flash size reg is normally in ref man) - static const chip_params_t devices[] = { - { - //RM0385 and DS10916 document was used to find these paramaters - .chip_id = STM32_CHIPID_F7, - .description = "F7 device", - .flash_type = FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 41.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18 - }, - { // table 2, PM0063 - .chip_id = STM32_CHIPID_F1_MEDIUM, - .description = "F1 Medium-density device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x5000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { // table 1, PM0059 - .chip_id = STM32_CHIPID_F2, - .description = "F2 device", - .flash_type = FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/ - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { // PM0063 - .chip_id = STM32_CHIPID_F1_LOW, - .description = "F1 Low-density device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2800, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - .chip_id = STM32_CHIPID_F4, - .description = "F4 device", - .flash_type = FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ - .flash_pagesize = 0x4000, - .sram_size = 0x30000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STM32_CHIPID_F4_DSI, - .description = "F46x and F47x device", - .flash_type = FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STM32_CHIPID_F4_HD, - .description = "F42x and F43x device", - .flash_type = FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STM32_CHIPID_F4_LP, - .description = "F4 device (low power)", - .flash_type = FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STM32_CHIPID_F411RE, - .description = "F4 device (low power) - stm32f411re", - .flash_type = FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STM32_CHIPID_F4_DE, - .description = "F4 device (Dynamic Efficency)", - .flash_type = FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STM32_CHIPID_F1_HIGH, - .description = "F1 High-density device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - // This ignores the EEPROM! (and uses the page erase size, - // not the sector write protection...) - .chip_id = STM32_CHIPID_L1_MEDIUM, - .description = "L1 Med-density device", - .flash_type = FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x4000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 - }, - { - .chip_id = STM32_CHIPID_L1_CAT2, - .description = "L1 Cat.2 device", - .flash_type = FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x8000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 - }, - { - .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS, - .description = "L1 Medium-Plus-density device", - .flash_type = FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/ - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 - }, - { - .chip_id = STM32_CHIPID_L1_HIGH, - .description = "L1 High-density device", - .flash_type = FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/ - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 - }, - { - .chip_id = STM32_CHIPID_L152_RE, - .description = "L152RE", - .flash_type = FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/ - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 - }, - { - .chip_id = STM32_CHIPID_F1_CONN, - .description = "F1 Connectivity line device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1fffb000, - .bootrom_size = 0x4800 - }, - {//Low and Medium density VL have same chipid. RM0041 25.6.1 - .chip_id = STM32_CHIPID_F1_VL_MEDIUM_LOW, - .description = "F1 Medium/Low-density Value Line device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2000,//0x1000 for low density devices - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. - .chip_id = STM32_CHIPID_F446, - .description = "F446 device", - .flash_type = FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - // This is STK32F303VCT6 device from STM32 F3 Discovery board. - // Support based on DM00043574.pdf (RM0316) document. - .chip_id = STM32_CHIPID_F3, - .description = "F3 device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - // This is STK32F373VCT6 device from STM32 F373 eval board - // Support based on 303 above (37x and 30x have same memory map) - .chip_id = STM32_CHIPID_F37x, - .description = "F3 device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - .chip_id = STM32_CHIPID_F1_VL_HIGH, - .description = "F1 High-density value line device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x8000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - .chip_id = STM32_CHIPID_F1_XL, - .description = "F1 XL-density device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x18000, - .bootrom_base = 0x1fffe000, - .bootrom_size = 0x1800 - }, - { - //Use this as an example for mapping future chips: - //RM0091 document was used to find these paramaters - .chip_id = STM32_CHIPID_F0_CAN, - .description = "F07x device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 - .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2 - }, - { - //Use this as an example for mapping future chips: - //RM0091 document was used to find these paramaters - .chip_id = STM32_CHIPID_F0, - .description = "F0 device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 - }, - { - .chip_id = STM32_CHIPID_F09X, - .description = "F09X device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) - .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) - .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 - .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2 - }, - { - //Use this as an example for mapping future chips: - //RM0091 document was used to find these paramaters - .chip_id = STM32_CHIPID_F04, - .description = "F04x device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 - }, - { - //Use this as an example for mapping future chips: - //RM0091 document was used to find these paramaters - .chip_id = STM32_CHIPID_F0_SMALL, - .description = "F0 small device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 - }, - { - // STM32F30x - .chip_id = STM32_CHIPID_F3_SMALL, - .description = "F3 small device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000 - }, - { - // STM32L0x - // RM0367,RM0377 documents was used to find these parameters - .chip_id = STM32_CHIPID_L0, - .description = "L0x3 device", - .flash_type = FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000 - }, - { - // STM32L0x Category 5 - // RM0367,RM0377 documents was used to find these parameters - .chip_id = STM32_CHIPID_L0_CAT5, - .description = "L0x Category 5 device", - .flash_type = FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x5000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x2000 - }, - { - // STM32L0x Category 2 - // RM0367,RM0377 documents was used to find these parameters - .chip_id = STM32_CHIPID_L0_CAT2, - .description = "L0x Category 2 device", - .flash_type = FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000 - }, - { - // STM32F334 - // RM0364 document was used to find these parameters - .chip_id = STM32_CHIPID_F334, - .description = "F334 device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0x3000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000 - }, - { - // This is STK32F303RET6 device from STM32 F3 Nucelo board. - // Support based on DM00043574.pdf (RM0316) document rev 5. - .chip_id = STM32_CHIPID_F303_HIGH, - .description = "F303 high density device", - .flash_type = FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register - .flash_pagesize = 0x800, // 4.2.1 Flash memory organization - .sram_size = 0x10000, // 3.3 Embedded SRAM - .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory - .bootrom_size = 0x2000 - }, - { - // STM32L4x6 - // From RM0351. - .chip_id = STM32_CHIPID_L4, - .description = "L4 device", - .flash_type = FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81) - // SRAM1 is "up to" 96k in the standard Cortex-M memory map; - // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000 // 28k (per bank), same source as base - }, - - }; - +#include "stlink/chipid.h" typedef struct { uint32_t r[16]; diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h new file mode 100644 index 000000000..48215088f --- /dev/null +++ b/include/stlink/chipid.h @@ -0,0 +1,77 @@ +#ifndef STLINK_CHIPID_H_ +#define STLINK_CHIPID_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * Chip IDs are explained in the appropriate programming manual for the + * DBGMCU_IDCODE register (0xE0042000) + * stm32 chipids, only lower 12 bits.. + */ +enum stlink_stm32_chipids { + STLINK_CHIPID_STM32_F1_MEDIUM = 0x410, + STLINK_CHIPID_STM32_F2 = 0x411, + STLINK_CHIPID_STM32_F1_LOW = 0x412, + STLINK_CHIPID_STM32_F4 = 0x413, + STLINK_CHIPID_STM32_F1_HIGH = 0x414, + STLINK_CHIPID_STM32_L4 = 0x415, + STLINK_CHIPID_STM32_L1_MEDIUM = 0x416, + STLINK_CHIPID_STM32_L0 = 0x417, + STLINK_CHIPID_STM32_F1_CONN = 0x418, + STLINK_CHIPID_STM32_F4_HD = 0x419, + STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW = 0x420, + STLINK_CHIPID_STM32_F446 = 0x421, + STLINK_CHIPID_STM32_F3 = 0x422, + STLINK_CHIPID_STM32_F4_LP = 0x423, + STLINK_CHIPID_STM32_L0_CAT2 = 0x425, + STLINK_CHIPID_STM32_L1_MEDIUM_PLUS = 0x427, + STLINK_CHIPID_STM32_F1_VL_HIGH = 0x428, + STLINK_CHIPID_STM32_L1_CAT2 = 0x429, + STLINK_CHIPID_STM32_F1_XL = 0x430, + STLINK_CHIPID_STM32_F411RE = 0x431, + STLINK_CHIPID_STM32_F37x = 0x432, + STLINK_CHIPID_STM32_F4_DE = 0x433, + STLINK_CHIPID_STM32_F4_DSI = 0x434, + /* + * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus" + * and some that are called "High". 0x427 is assigned to the other "Medium- + * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and + * 0x436 HIGH. + */ + STLINK_CHIPID_STM32_L1_HIGH = 0x436, + STLINK_CHIPID_STM32_L152_RE = 0x437, + STLINK_CHIPID_STM32_F334 = 0x438, + STLINK_CHIPID_STM32_F3_SMALL = 0x439, + STLINK_CHIPID_STM32_F0 = 0x440, + STLINK_CHIPID_STM32_F09X = 0x442, + STLINK_CHIPID_STM32_F0_SMALL = 0x444, + STLINK_CHIPID_STM32_F04 = 0x445, + STLINK_CHIPID_STM32_F303_HIGH = 0x446, + STLINK_CHIPID_STM32_L0_CAT5 = 0x447, + STLINK_CHIPID_STM32_F0_CAN = 0x448, + STLINK_CHIPID_STM32_F7 = 0x449 +}; + +/** + * Chipid parameters + */ +struct stlink_chipid_params { + uint32_t chip_id; + char *description; + enum flash_type flash_type; + uint32_t flash_size_reg; + uint32_t flash_pagesize; + uint32_t sram_size; + uint32_t bootrom_base; + uint32_t bootrom_size; +}; + +const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); + +#ifdef __cplusplus +} +#endif + +#endif /* STLINK_CHIPID_H_ */ diff --git a/src/chipid.c b/src/chipid.c new file mode 100644 index 000000000..92daeb28a --- /dev/null +++ b/src/chipid.c @@ -0,0 +1,402 @@ +#include "stlink.h" +#include "stlink/chipid.h" + +static const struct stlink_chipid_params devices[] = { + { + //RM0385 and DS10916 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F7, + .description = "F7 device", + .flash_type = FLASH_TYPE_F4, + .flash_size_reg = 0x1ff0f442, // section 41.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 + .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18 + }, + { // table 2, PM0063 + .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, + .description = "F1 Medium-density device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x5000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { // table 1, PM0059 + .chip_id = STLINK_CHIPID_STM32_F2, + .description = "F2 device", + .flash_type = FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/ + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { // PM0063 + .chip_id = STLINK_CHIPID_STM32_F1_LOW, + .description = "F1 Low-density device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2800, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F4, + .description = "F4 device", + .flash_type = FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ + .flash_pagesize = 0x4000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_DSI, + .description = "F46x and F47x device", + .flash_type = FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_HD, + .description = "F42x and F43x device", + .flash_type = FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_LP, + .description = "F4 device (low power)", + .flash_type = FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x10000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F411RE, + .description = "F4 device (low power) - stm32f411re", + .flash_type = FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_DE, + .description = "F4 device (Dynamic Efficency)", + .flash_type = FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F1_HIGH, + .description = "F1 High-density device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + // This ignores the EEPROM! (and uses the page erase size, + // not the sector write protection...) + .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM, + .description = "L1 Med-density device", + .flash_type = FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x4000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = STLINK_CHIPID_STM32_L1_CAT2, + .description = "L1 Cat.2 device", + .flash_type = FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x8000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, + .description = "L1 Medium-Plus-density device", + .flash_type = FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/ + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = STLINK_CHIPID_STM32_L1_HIGH, + .description = "L1 High-density device", + .flash_type = FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/ + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = STLINK_CHIPID_STM32_L152_RE, + .description = "L152RE", + .flash_type = FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/ + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = STLINK_CHIPID_STM32_F1_CONN, + .description = "F1 Connectivity line device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1fffb000, + .bootrom_size = 0x4800 + }, + {//Low and Medium density VL have same chipid. RM0041 25.6.1 + .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, + .description = "F1 Medium/Low-density Value Line device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2000,//0x1000 for low density devices + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. + .chip_id = STLINK_CHIPID_STM32_F446, + .description = "F446 device", + .flash_type = FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + // This is STK32F303VCT6 device from STM32 F3 Discovery board. + // Support based on DM00043574.pdf (RM0316) document. + .chip_id = STLINK_CHIPID_STM32_F3, + .description = "F3 device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + // This is STK32F373VCT6 device from STM32 F373 eval board + // Support based on 303 above (37x and 30x have same memory map) + .chip_id = STLINK_CHIPID_STM32_F37x, + .description = "F3 device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, + .description = "F1 High-density value line device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x8000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F1_XL, + .description = "F1 XL-density device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x18000, + .bootrom_base = 0x1fffe000, + .bootrom_size = 0x1800 + }, + { + //Use this as an example for mapping future chips: + //RM0091 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F0_CAN, + .description = "F07x device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 + .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 + .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2 + }, + { + //Use this as an example for mapping future chips: + //RM0091 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F0, + .description = "F0 device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + }, + { + .chip_id = STLINK_CHIPID_STM32_F09X, + .description = "F09X device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) + .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) + .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 + .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2 + }, + { + //Use this as an example for mapping future chips: + //RM0091 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F04, + .description = "F04x device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + }, + { + //Use this as an example for mapping future chips: + //RM0091 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F0_SMALL, + .description = "F0 small device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + }, + { + // STM32F30x + .chip_id = STLINK_CHIPID_STM32_F3_SMALL, + .description = "F3 small device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1fffd800, + .bootrom_size = 0x2000 + }, + { + // STM32L0x + // RM0367,RM0377 documents was used to find these parameters + .chip_id = STLINK_CHIPID_STM32_L0, + .description = "L0x3 device", + .flash_type = FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000 + }, + { + // STM32L0x Category 5 + // RM0367,RM0377 documents was used to find these parameters + .chip_id = STLINK_CHIPID_STM32_L0_CAT5, + .description = "L0x Category 5 device", + .flash_type = FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x5000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x2000 + }, + { + // STM32L0x Category 2 + // RM0367,RM0377 documents was used to find these parameters + .chip_id = STLINK_CHIPID_STM32_L0_CAT2, + .description = "L0x Category 2 device", + .flash_type = FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000 + }, + { + // STM32F334 + // RM0364 document was used to find these parameters + .chip_id = STLINK_CHIPID_STM32_F334, + .description = "F334 device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0x3000, + .bootrom_base = 0x1fffd800, + .bootrom_size = 0x2000 + }, + { + // This is STK32F303RET6 device from STM32 F3 Nucelo board. + // Support based on DM00043574.pdf (RM0316) document rev 5. + .chip_id = STLINK_CHIPID_STM32_F303_HIGH, + .description = "F303 high density device", + .flash_type = FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register + .flash_pagesize = 0x800, // 4.2.1 Flash memory organization + .sram_size = 0x10000, // 3.3 Embedded SRAM + .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory + .bootrom_size = 0x2000 + }, + { + // STM32L4x6 + // From RM0351. + .chip_id = STLINK_CHIPID_STM32_L4, + .description = "L4 device", + .flash_type = FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81) + // SRAM1 is "up to" 96k in the standard Cortex-M memory map; + // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000 // 28k (per bank), same source as base + }, + + }; + +const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) +{ + struct stlink_chipid_params *params = NULL; + + for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { + if (devices[n].chip_id == chipid) { + params = &devices[n]; + break; + } + } + + return params; +} diff --git a/src/common.c b/src/common.c index 24f9cd7fe..e975c0ae7 100644 --- a/src/common.c +++ b/src/common.c @@ -567,7 +567,7 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { */ int stlink_load_device_params(stlink_t *sl) { ILOG("Loading device parameters....\n"); - const chip_params_t *params = NULL; + struct stlink_chipid_params *params = NULL; stlink_core_id(sl); uint32_t chip_id; uint32_t flash_size; @@ -582,12 +582,7 @@ int stlink_load_device_params(stlink_t *sl) { sl->chip_id = 0x413; } - for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { - if(devices[i].chip_id == sl->chip_id) { - params = &devices[i]; - break; - } - } + params = stlink_chipid_get_params(sl->chip_id); if (params == NULL) { WLOG("unknown chip id! %#x\n", chip_id); return -1; @@ -598,7 +593,6 @@ int stlink_load_device_params(stlink_t *sl) { return -1; } - // These are fixed... sl->flash_base = STM32_FLASH_BASE; sl->sram_base = STM32_SRAM_BASE; @@ -607,11 +601,11 @@ int stlink_load_device_params(stlink_t *sl) { flash_size = flash_size >>16; flash_size = flash_size & 0xffff; - if ((sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS) && ( flash_size == 0 )) { + if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && ( flash_size == 0 )) { sl->flash_size = 128 * 1024; - } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { + } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_HIGH) { + } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_HIGH) { // 0 is 384k and 1 is 256k if ( flash_size == 0 ) { sl->flash_size = 384 * 1024; @@ -629,7 +623,7 @@ int stlink_load_device_params(stlink_t *sl) { //medium and low devices have the same chipid. ram size depends on flash size. //STM32F100xx datasheet Doc ID 16455 Table 2 - if(sl->chip_id == STM32_CHIPID_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){ + if(sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){ sl->sram_size = 0x1000; } @@ -1210,9 +1204,9 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || (sl->chip_id == STM32_CHIPID_F4_HD) || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)) { + if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || (sl->chip_id == STLINK_CHIPID_STM32_F4) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || + (sl->chip_id == STLINK_CHIPID_STM32_F446) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector>= 12) { sector -= 12; @@ -1221,7 +1215,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ else if(sector<5) sl->flash_pgsz=0x10000; else sl->flash_pgsz=0x20000; } - else if (sl->chip_id == STM32_CHIPID_F7) { + else if (sl->chip_id == STLINK_CHIPID_STM32_F7) { uint32_t sector=calculate_F7_sectornum(flashaddr); if (sector<4) sl->flash_pgsz=0x8000; else if(sector<5) sl->flash_pgsz=0x20000; @@ -1246,14 +1240,14 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) unlock_flash_if(sl); /* select the page to erase */ - if (sl->chip_id == STM32_CHIPID_L4) { + if (sl->chip_id == STLINK_CHIPID_STM32_L4) { // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STM32_CHIPID_F7) { + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7) { // calculate the actual page from the address uint32_t sector=calculate_F7_sectornum(flashaddr); @@ -1288,7 +1282,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) uint32_t val; uint32_t flash_regs_base; - if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5 || sl->chip_id == STM32_CHIPID_L0_CAT2) { + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; } else { flash_regs_base = STM32L_FLASH_REGS_ADDR; @@ -1609,23 +1603,23 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STM32_CHIPID_L1_MEDIUM || sl->chip_id == STM32_CHIPID_L1_CAT2 - || sl->chip_id == STM32_CHIPID_L1_MEDIUM_PLUS || sl->chip_id == STM32_CHIPID_L1_HIGH - || sl->chip_id == STM32_CHIPID_L152_RE - || sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5 || sl->chip_id == STM32_CHIPID_L0_CAT2) { /* stm32l */ + if (sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2 + || sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS || sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH + || sl->chip_id == STLINK_CHIPID_STM32_L152_RE + || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID - || sl->chip_id == STM32_CHIPID_F3 - || sl->chip_id == STM32_CHIPID_F3_SMALL - || sl->chip_id == STM32_CHIPID_F303_HIGH - || sl->chip_id == STM32_CHIPID_F37x - || sl->chip_id == STM32_CHIPID_F334) { + || sl->chip_id == STLINK_CHIPID_STM32_F3 + || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL + || sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH + || sl->chip_id == STLINK_CHIPID_STM32_F37x + || sl->chip_id == STLINK_CHIPID_STM32_F334) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); - } else if (sl->chip_id == STM32_CHIPID_F2 || sl->chip_id == STM32_CHIPID_F4 || (sl->chip_id == STM32_CHIPID_F4_DE) || - sl->chip_id == STM32_CHIPID_F4_LP || sl->chip_id == STM32_CHIPID_F4_HD || (sl->chip_id == STM32_CHIPID_F411RE) || - (sl->chip_id == STM32_CHIPID_F446) || (sl->chip_id == STM32_CHIPID_F4_DSI)){ + } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || sl->chip_id == STLINK_CHIPID_STM32_F4 || (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || + sl->chip_id == STLINK_CHIPID_STM32_F4_LP || sl->chip_id == STLINK_CHIPID_STM32_F4_HD || (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || + (sl->chip_id == STLINK_CHIPID_STM32_F446) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI)){ int voltage = stlink_target_voltage(sl); if (voltage == -1) { printf("Failed to read Target voltage\n"); @@ -1637,13 +1631,13 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { loader_code = loader_code_stm32f4_lv; loader_size = sizeof(loader_code_stm32f4_lv); } - } else if (sl->chip_id == STM32_CHIPID_F7){ + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7){ loader_code = loader_code_stm32f7; loader_size = sizeof(loader_code_stm32f7); - } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || sl->chip_id == STM32_CHIPID_F0_SMALL || sl->chip_id == STM32_CHIPID_F09X) { + } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || sl->chip_id == STLINK_CHIPID_STM32_F0_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F09X) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); - } else if (sl->chip_id == STM32_CHIPID_L4) { + } else if (sl->chip_id == STLINK_CHIPID_STM32_L4) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { @@ -1720,7 +1714,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin uint32_t flash_regs_base; flash_loader_t fl; - if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5 || sl->chip_id == STM32_CHIPID_L0_CAT2) { + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; } else { flash_regs_base = STM32L_FLASH_REGS_ADDR; @@ -1835,7 +1829,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t unlock_flash_if(sl); /* TODO: Check that Voltage range is 2.7 - 3.6 V */ - if (sl->chip_id != STM32_CHIPID_L4) { + if (sl->chip_id != STLINK_CHIPID_STM32_L4) { /* set parallelisim to 32 bit*/ int voltage = stlink_target_voltage(sl); if (voltage == -1) { @@ -1887,7 +1881,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t uint32_t flash_regs_base; uint32_t pagesize; - if (sl->chip_id == STM32_CHIPID_L0 || sl->chip_id == STM32_CHIPID_L0_CAT5 || sl->chip_id == STM32_CHIPID_L0_CAT2) { + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; pagesize = L0_WRITE_BLOCK_SIZE; } else { diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 666251c1b..b57a299ac 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -434,19 +434,19 @@ char* make_memory_map(stlink_t *sl) { char* map = malloc(4096); map[0] = '\0'; - if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F446) { + if(sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F446) { strcpy(map, memory_map_template_F4); - } else if(sl->chip_id==STM32_CHIPID_F4 || sl->chip_id==STM32_CHIPID_F7) { + } else if(sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F7) { strcpy(map, memory_map_template_F7); - } else if(sl->chip_id==STM32_CHIPID_F4_HD) { + } else if(sl->chip_id==STLINK_CHIPID_STM32_F4_HD) { strcpy(map, memory_map_template_F4_HD); - } else if(sl->chip_id==STM32_CHIPID_F2) { + } else if(sl->chip_id==STLINK_CHIPID_STM32_F2) { snprintf(map, 4096, memory_map_template_F2, sl->flash_size, sl->sram_size, sl->flash_size - 0x20000, sl->sys_base, sl->sys_size); - } else if(sl->chip_id==STM32_CHIPID_L4) { + } else if(sl->chip_id==STLINK_CHIPID_STM32_L4) { snprintf(map, 4096, memory_map_template_L4, sl->flash_size, sl->flash_size); } else { @@ -608,7 +608,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { return -1; } - if (sl->chip_id==STM32_CHIPID_F7) { + if (sl->chip_id==STLINK_CHIPID_STM32_F7) { fpb_addr = addr; } else { fpb_addr = addr & ~0x3; @@ -632,7 +632,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { brk->addr = fpb_addr; - if (sl->chip_id==STM32_CHIPID_F7) { + if (sl->chip_id==STLINK_CHIPID_STM32_F7) { if(set) brk->type = type; else brk->type = 0; @@ -842,7 +842,7 @@ static void init_cache (stlink_t *sl) { int i; /* Assume only F7 has a cache. */ - if(sl->chip_id!=STM32_CHIPID_F7) + if(sl->chip_id!=STLINK_CHIPID_STM32_F7) return; stlink_read_debug32(sl, CLIDR, &clidr); @@ -923,7 +923,7 @@ static void cache_sync(stlink_t *sl) { unsigned ccr; - if(sl->chip_id!=STM32_CHIPID_F7) + if(sl->chip_id!=STLINK_CHIPID_STM32_F7) return; if (!cache_modified) return; @@ -1024,9 +1024,9 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("query: %s;%s\n", queryName, params); if(!strcmp(queryName, "Supported")) { - if(sl->chip_id==STM32_CHIPID_F4 - || sl->chip_id==STM32_CHIPID_F4_HD - || sl->chip_id==STM32_CHIPID_F7) { + if(sl->chip_id==STLINK_CHIPID_STM32_F4 + || sl->chip_id==STLINK_CHIPID_STM32_F4_HD + || sl->chip_id==STLINK_CHIPID_STM32_F7) { reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); } else { diff --git a/src/tools/flash.c b/src/tools/flash.c index 770289ba3..7bebd82f9 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -218,7 +218,7 @@ int main(int ac, char** av) } // Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 - if (sl->chip_id == STM32_CHIPID_F4) + if (sl->chip_id == STLINK_CHIPID_STM32_F4) { memset(sl->q_buf,0,4); for (int i=0;i<8;i++) { diff --git a/src/tools/gui/stlink-gui.c b/src/tools/gui/stlink-gui.c index 944ad131b..fd1cdf937 100644 --- a/src/tools/gui/stlink-gui.c +++ b/src/tools/gui/stlink-gui.c @@ -446,14 +446,14 @@ filemem_jmp_cb (GtkWidget *widget, gpointer data) static gchar * dev_format_chip_id (guint32 chip_id) { + const struct stlink_chipid_params *params; gint i; - for (i = 0; i < sizeof (devices) / sizeof (devices[0]); i++) { - if (chip_id == devices[i].chip_id) { - return g_strdup (devices[i].description); - } - } - return g_strdup_printf ("0x%x", chip_id); + params = stlink_chipid_get_params(chip_id); + if (!params) + return g_strdup_printf ("0x%x", chip_id); + + return g_strdup (params->description); } static gchar * @@ -544,7 +544,7 @@ connect_button_cb (GtkWidget *widget, gpointer data) stlink_enter_swd_mode(gui->sl); /* Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 */ - if (gui->sl->chip_id == STM32_CHIPID_F4) { + if (gui->sl->chip_id == STLINK_CHIPID_STM32_F4) { memset(gui->sl->q_buf, 0, 4); for (i = 0; i < 8; i++) { stlink_write_mem32(gui->sl, 0x40026000 + 0x10 + 0x18 * i, 4); diff --git a/src/tools/info.c b/src/tools/info.c index e29184e5a..0d0b82393 100644 --- a/src/tools/info.c +++ b/src/tools/info.c @@ -39,7 +39,7 @@ static void stlink_print_serial(stlink_t *sl, bool openocd) static void stlink_print_info(stlink_t *sl) { - const chip_params_t *params = NULL; + const struct stlink_chipid_params *params = NULL; if (!sl) return; @@ -53,15 +53,9 @@ static void stlink_print_info(stlink_t *sl) printf(" sram: %zu\n", sl->sram_size); printf(" chipid: 0x%.4x\n", sl->chip_id); - for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { - if (devices[i].chip_id == sl->chip_id) { - params = &devices[i]; - break; - } - } - - if (params) - printf(" descr: %s\n", params->description); + params = stlink_chipid_get_params(sl->chip_id); + if (params) + printf(" descr: %s\n", params->description); } static void stlink_probe(void) @@ -126,16 +120,9 @@ static int print_data(char **av) else if (strcmp(av[1], "--hla-serial") == 0) stlink_print_serial(sl, true); else if (strcmp(av[1], "--descr") == 0) { - const chip_params_t *params = NULL; - for (size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { - if(devices[i].chip_id == sl->chip_id) { - params = &devices[i]; - break; - } - } - if (params == NULL) { + const struct stlink_chipid_params *params = stlink_chipid_get_params(sl->chip_id); + if (params == NULL) return -1; - } printf("%s\n", params->description); } From 0c07627c7806ceaa357552d96c9df3a2055c6c6f Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Mon, 16 May 2016 15:55:34 +0200 Subject: [PATCH 0422/1435] stlink_gui: Fix compiler warning on overflow --- src/tools/gui/stlink-gui.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/tools/gui/stlink-gui.c b/src/tools/gui/stlink-gui.c index fd1cdf937..247373e9d 100644 --- a/src/tools/gui/stlink-gui.c +++ b/src/tools/gui/stlink-gui.c @@ -1,5 +1,6 @@ #include #include +#include #include #include @@ -183,14 +184,14 @@ hexstr_to_guint32 (const gchar *str, GError **err) g_quark_from_string ("hextou32"), 1, "Invalid hexstring"); - return LONG_MAX; + return UINT32_MAX; } if (end_ptr == str) { g_set_error (err, g_quark_from_string ("hextou32"), 2, "Invalid hexstring"); - return LONG_MAX; + return UINT32_MAX; } return val; } From 7b1a571549f74f4a9c70cbcf989cdb0b93c0153a Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Tue, 17 May 2016 20:00:06 +0200 Subject: [PATCH 0423/1435] Update README Add Contributing and versioning to README --- README | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/README b/README index f6ac729bc..b7fbf12cd 100644 --- a/README +++ b/README @@ -24,7 +24,7 @@ Two different transport layers are used: * `pkg-config` * `intltool` -* `cmake` or (`autoconf` && `automake && `autogen`) +* `cmake` or (`autoconf` && `automake` && `autogen`) * `libusb-1.0` (plus development headers for building, on debian based distros `libusb-1.0.0-dev` package) * (optional) for `stlink-gui` we need libgtk-3-dev @@ -168,7 +168,6 @@ If you would link your executable to 0x08000000 and then do (gdb) load firmware.elf then it would be written to the memory. - ## FAQ Q: My breakpoints do not work at all or only work once. @@ -237,6 +236,12 @@ STLink v2-1 (as found on the Nucleo boards), known working targets: Please report any and all known working combinations so I can update this! +## Contributing and versioning + +* The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) +* When creating a pull request, please open first a issue for discussion of new features +* TODO: Enforcement of coding style (linux codestyle + checkpatch) + ## License The stlink library and tools are licensed under the [BSD license](LICENSE) From ad3978720e4b5df93ee25720afd20268405f9d22 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Tue, 17 May 2016 20:19:30 +0200 Subject: [PATCH 0424/1435] Update README Fix link to UweBonnes/wiki_fuer_alex --- README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README b/README index b7fbf12cd..8fc282bc5 100644 --- a/README +++ b/README @@ -210,7 +210,7 @@ STLink v2 (as found on the 32L and F4 Discovery boards), known working targets: * STM32F100xx (Medium Density VL, as on the 32VL Discovery board) * STM32L1xx (STM32L Discovery board) * STM32F103VC, STM32F107RC, STM32L151RB, STM32F205RE and STM32F405RE on custom boards - (https://github.com/UweBonnes/wiki_fuer_alex/layout/usps...) + from [UweBonnes/wiki_fuer_alex](https://github.com/UweBonnes/wiki_fuer_alex/tree/master/layout) * STM32F103VET6 (HY-STM32 board) * STM32F105RCT6 (DecaWave EVB1000 board) * STM32F303xx (STM32F3 Discovery board) From 9c635e419deca697ff823000aad2e39d47ec8d6c Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 19 May 2016 09:01:14 +0200 Subject: [PATCH 0425/1435] chipid: Initial support for STM32F410 --- include/stlink/chipid.h | 3 ++- src/chipid.c | 11 +++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 48215088f..351bb5537 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -51,7 +51,8 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F303_HIGH = 0x446, STLINK_CHIPID_STM32_L0_CAT5 = 0x447, STLINK_CHIPID_STM32_F0_CAN = 0x448, - STLINK_CHIPID_STM32_F7 = 0x449 + STLINK_CHIPID_STM32_F7 = 0x449, + STLINK_CHIPID_STM32_F410 = 0x458 }; /** diff --git a/src/chipid.c b/src/chipid.c index 92daeb28a..b4fd2d66a 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -196,6 +196,17 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800 }, + { + // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. + .chip_id = STLINK_CHIPID_STM32_F410, + .description = "F410 device", + .flash_type = FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x4000, + .sram_size = 0x8000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, { // This is STK32F303VCT6 device from STM32 F3 Discovery board. // Support based on DM00043574.pdf (RM0316) document. From d83d7f7392009fc30e8688b68d5c4a7a244105f6 Mon Sep 17 00:00:00 2001 From: Jean-Marie Lemetayer Date: Thu, 19 May 2016 11:03:35 +0200 Subject: [PATCH 0426/1435] Fix const warning --- src/chipid.c | 2 +- src/common.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/chipid.c b/src/chipid.c index 92daeb28a..2c92d1efc 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -389,7 +389,7 @@ static const struct stlink_chipid_params devices[] = { const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { - struct stlink_chipid_params *params = NULL; + const struct stlink_chipid_params *params = NULL; for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { if (devices[n].chip_id == chipid) { diff --git a/src/common.c b/src/common.c index e975c0ae7..e61bc53b7 100644 --- a/src/common.c +++ b/src/common.c @@ -567,7 +567,7 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { */ int stlink_load_device_params(stlink_t *sl) { ILOG("Loading device parameters....\n"); - struct stlink_chipid_params *params = NULL; + const struct stlink_chipid_params *params = NULL; stlink_core_id(sl); uint32_t chip_id; uint32_t flash_size; From 8da1467bb1e1f28f3e7cf830a48c8cc61090e0d2 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 20 May 2016 17:51:27 +0200 Subject: [PATCH 0427/1435] common.c: Add STLINK_CHIPID_STM32_F410 for correct flash loader selection --- src/common.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/common.c b/src/common.c index e61bc53b7..729c739da 100644 --- a/src/common.c +++ b/src/common.c @@ -1617,9 +1617,16 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { || sl->chip_id == STLINK_CHIPID_STM32_F334) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || sl->chip_id == STLINK_CHIPID_STM32_F4 || (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || - sl->chip_id == STLINK_CHIPID_STM32_F4_LP || sl->chip_id == STLINK_CHIPID_STM32_F4_HD || (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || - (sl->chip_id == STLINK_CHIPID_STM32_F446) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI)){ + } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || + sl->chip_id == STLINK_CHIPID_STM32_F4 || + sl->chip_id == STLINK_CHIPID_STM32_F4_DE || + sl->chip_id == STLINK_CHIPID_STM32_F4_LP || + sl->chip_id == STLINK_CHIPID_STM32_F4_HD || + sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || + sl->chip_id == STLINK_CHIPID_STM32_F410 || + sl->chip_id == STLINK_CHIPID_STM32_F411RE || + sl->chip_id == STLINK_CHIPID_STM32_F446 + ) { int voltage = stlink_target_voltage(sl); if (voltage == -1) { printf("Failed to read Target voltage\n"); From 893fa4f8da4661c8984aacc4df61237849913f3b Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 20 May 2016 18:12:41 +0200 Subject: [PATCH 0428/1435] logging.h: Add helpers so the log macros can have just one argument, needed for compilation on visual studio --- include/stlink/logging.h | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/include/stlink/logging.h b/include/stlink/logging.h index df816caed..81e5f598c 100644 --- a/include/stlink/logging.h +++ b/include/stlink/logging.h @@ -20,11 +20,18 @@ enum ugly_loglevel { int ugly_init(int maximum_threshold); int ugly_log(int level, const char *tag, const char *format, ...); -#define DLOG(format, args...) ugly_log(UDEBUG, __FILE__, format, ## args) -#define ILOG(format, args...) ugly_log(UINFO, __FILE__, format, ## args) -#define WLOG(format, args...) ugly_log(UWARN, __FILE__, format, ## args) -#define ELOG(format, args...) ugly_log(UERROR, __FILE__, format, ## args) -#define fatal(format, args...) ugly_log(UFATAL, __FILE__, format, ## args) +/** @todo we need to write this in a more generic way, for now this should compile + on visual studio (See http://stackoverflow.com/a/8673872/1836746) */ +#define DLOG_HELPER(format, ...) ugly_log(UDEBUG, __FILE__, format, __VA_ARGS__) +#define DLOG(...) DLOG_HELPER(__VA_ARGS__, "") +#define ILOG_HELPER(format, ...) ugly_log(UINFO, __FILE__, format, __VA_ARGS__) +#define ILOG(...) ILOG_HELPER(__VA_ARGS__, "") +#define WLOG_HELPER(format, ...) ugly_log(UWARN, __FILE__, format, __VA_ARGS__) +#define WLOG(...) WLOG_HELPER(__VA_ARGS__, "") +#define ELOG_HELPER(format, ...) ugly_log(UERROR, __FILE__, format, __VA_ARGS__) +#define ELOG(...) ELOG_HELPER(__VA_ARGS__, "") +#define fatal_helper(format, ...) ugly_log(UFATAL, __FILE__, format, __VA_ARGS__) +#define fatal(...) fatal_helper(__VA_ARGS__, "") #ifdef __cplusplus } From 48a8ac59e1ba7f98fe5c247f608be3cb3998e9c4 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 20 May 2016 20:03:57 +0200 Subject: [PATCH 0429/1435] Move STLINK_DEBUG_* defines into enum, move flash_loader code into seperate header and c file --- CMakeLists.txt | 2 + Makefile.am | 5 +- include/stlink.h | 36 +--- include/stlink/commands.h | 26 +++ include/stlink/flash_loader.h | 27 +++ src/common.c | 333 ++-------------------------------- src/flash_loader.c | 313 ++++++++++++++++++++++++++++++++ 7 files changed, 393 insertions(+), 349 deletions(-) create mode 100644 include/stlink/commands.h create mode 100644 include/stlink/flash_loader.h create mode 100644 src/flash_loader.c diff --git a/CMakeLists.txt b/CMakeLists.txt index 89bd85968..dab482939 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -54,6 +54,7 @@ set(STLINK_HEADERS include/stlink/logging.h include/stlink/mmap.h include/stlink/chipid.h + include/stlink/flash_loader.h ) set(STLINK_SOURCE @@ -62,6 +63,7 @@ set(STLINK_SOURCE src/usb.c src/sg.c src/logging.c + src/flash_loader.c ) include_directories(${LIBUSB_INCLUDE_DIR}) diff --git a/Makefile.am b/Makefile.am index a3114c6e4..79ce10c22 100644 --- a/Makefile.am +++ b/Makefile.am @@ -22,7 +22,8 @@ CFILES = \ src/common.c \ src/usb.c \ src/sg.c \ - src/logging.c + src/logging.c \ + src/flash_loader.c if !MINGW CFILES += src/tools/term.c @@ -32,6 +33,8 @@ HFILES = \ include/stlink.h \ include/stlink/chipid.h \ include/stlink/usb.h \ + include/stlink/flash_loader.h \ + include/stlink/commands.h \ include/stlink/sg.h \ include/stlink/logging.h \ include/stlink/mmap.h diff --git a/include/stlink.h b/include/stlink.h index 3941f4216..a20f815cb 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -49,27 +49,6 @@ extern "C" { #define STLINK_DEV_DEBUG_MODE 0x02 #define STLINK_DEV_UNKNOWN_MODE -1 - // jtag mode cmds -#define STLINK_DEBUG_ENTER 0x20 -#define STLINK_DEBUG_EXIT 0x21 -#define STLINK_DEBUG_READCOREID 0x22 -#define STLINK_DEBUG_GETSTATUS 0x01 -#define STLINK_DEBUG_FORCEDEBUG 0x02 -#define STLINK_DEBUG_RESETSYS 0x03 -#define STLINK_DEBUG_READALLREGS 0x04 -#define STLINK_DEBUG_READREG 0x05 -#define STLINK_DEBUG_WRITEREG 0x06 -#define STLINK_DEBUG_READMEM_32BIT 0x07 -#define STLINK_DEBUG_WRITEMEM_32BIT 0x08 -#define STLINK_DEBUG_RUNCORE 0x09 -#define STLINK_DEBUG_STEPCORE 0x0a -#define STLINK_DEBUG_SETFP 0x0b -#define STLINK_DEBUG_WRITEMEM_8BIT 0x0d -#define STLINK_DEBUG_CLEARFP 0x0e -#define STLINK_DEBUG_WRITEDEBUGREG 0x0f -#define STLINK_DEBUG_ENTER_SWD 0xa3 -#define STLINK_DEBUG_ENTER_JTAG 0x00 - // TODO - possible poor names... #define STLINK_SWD_ENTER 0x30 #define STLINK_SWD_READCOREID 0x32 // TBD @@ -116,8 +95,6 @@ extern "C" { FLASH_TYPE_L4, }; -#include "stlink/chipid.h" - typedef struct { uint32_t r[16]; uint32_t s[32]; @@ -135,6 +112,11 @@ extern "C" { typedef uint32_t stm32_addr_t; +typedef struct flash_loader { + stm32_addr_t loader_addr; /* loader sram adddr */ + stm32_addr_t buf_addr; /* buffer sram address */ +} flash_loader_t; + typedef struct _cortex_m3_cpuid_ { uint16_t implementer_id; uint16_t variant; @@ -150,11 +132,6 @@ extern "C" { uint32_t stlink_pid; } stlink_version_t; - typedef struct flash_loader { - stm32_addr_t loader_addr; /* loader sram adddr */ - stm32_addr_t buf_addr; /* buffer sram address */ - } flash_loader_t; - enum transport_type { TRANSPORT_TYPE_ZERO = 0, TRANSPORT_TYPE_LIBSG, @@ -298,6 +275,9 @@ extern "C" { #include "stlink/sg.h" #include "stlink/usb.h" +#include "stlink/commands.h" +#include "stlink/chipid.h" +#include "stlink/flash_loader.h" #ifdef __cplusplus } diff --git a/include/stlink/commands.h b/include/stlink/commands.h new file mode 100644 index 000000000..9ff5a8fb9 --- /dev/null +++ b/include/stlink/commands.h @@ -0,0 +1,26 @@ +#ifndef STLINK_COMMANDS_H_ +#define STLINK_COMMANDS_H_ + +enum stlink_debug_commands { + STLINK_DEBUG_ENTER_JTAG = 0x00, + STLINK_DEBUG_GETSTATUS = 0x01, + STLINK_DEBUG_FORCEDEBUG = 0x02, + STLINK_DEBUG_RESETSYS = 0x03, + STLINK_DEBUG_READALLREGS = 0x04, + STLINK_DEBUG_READREG = 0x05, + STLINK_DEBUG_WRITEREG = 0x06, + STLINK_DEBUG_READMEM_32BIT = 0x07, + STLINK_DEBUG_WRITEMEM_32BIT = 0x08, + STLINK_DEBUG_RUNCORE = 0x09, + STLINK_DEBUG_STEPCORE = 0x0a, + STLINK_DEBUG_SETFP = 0x0b, + STLINK_DEBUG_WRITEMEM_8BIT = 0x0d, + STLINK_DEBUG_CLEARFP = 0x0e, + STLINK_DEBUG_WRITEDEBUGREG = 0x0f, + STLINK_DEBUG_ENTER = 0x20, + STLINK_DEBUG_EXIT = 0x21, + STLINK_DEBUG_READCOREID = 0x22, + STLINK_DEBUG_ENTER_SWD = 0xa3 +}; + +#endif /* STLINK_COMMANDS_H_ */ diff --git a/include/stlink/flash_loader.h b/include/stlink/flash_loader.h new file mode 100644 index 000000000..95042f7b6 --- /dev/null +++ b/include/stlink/flash_loader.h @@ -0,0 +1,27 @@ +/* + * File: stlink.h + * + * This should contain all the common top level stlink interfaces, regardless + * of how the backend does the work.... + */ +#ifndef STLINK_FLASH_LOADER_H_ +#define STLINK_FLASH_LOADER_H_ + +#include +#include + +#include "stlink.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); +int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); +int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); + +#ifdef __cplusplus +} +#endif + +#endif /* STLINK_FLASH_LOADER_H_ */ diff --git a/src/common.c b/src/common.c index 729c739da..727048125 100644 --- a/src/common.c +++ b/src/common.c @@ -1416,252 +1416,6 @@ int stlink_erase_flash_mass(stlink_t *sl) { return 0; } -int init_flash_loader(stlink_t *sl, flash_loader_t* fl) { - size_t size; - - /* allocate the loader in sram */ - if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) { - WLOG("Failed to write flash loader to sram!\n"); - return -1; - } - - /* allocate a one page buffer in sram right after loader */ - fl->buf_addr = fl->loader_addr + size; - ILOG("Successfully loaded flash loader in sram\n"); - return 0; -} - -int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { - /* from openocd, contrib/loaders/flash/stm32.s */ - static const uint8_t loader_code_stm32vl[] = { - 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */ - 0x1c, 0x44, /* add r4, r3 */ - /* write_half_word: */ - 0x01, 0x23, /* movs r3, #0x01 */ - 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */ - 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */ - 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */ - /* busy: */ - 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */ - 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */ - 0xfb, 0xd0, /* beq busy */ - 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */ - 0x01, 0xd1, /* bne exit */ - 0x01, 0x3a, /* subs r2, r2, #0x01 */ - 0xf0, 0xd1, /* bne write_half_word */ - /* exit: */ - 0x00, 0xbe, /* bkpt #0x00 */ - 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */ - }; - - /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ - static const uint8_t loader_code_stm32f0[] = { -#if 1 - /* - * These two NOPs here are a safety precaution, added by Pekka Nikander - * while debugging the STM32F05x support. They may not be needed, but - * there were strange problems with simpler programs, like a program - * that had just a breakpoint or a program that first moved zero to register r2 - * and then had a breakpoint. So, it appears safest to have these two nops. - * - * Feel free to remove them, if you dare, but then please do test the result - * rigorously. Also, if you remove these, it may be a good idea first to - * #if 0 them out, with a comment when these were taken out, and to remove - * these only a few months later... But YMMV. - */ - 0x00, 0x30, // nop /* add r0,#0 */ - 0x00, 0x30, // nop /* add r0,#0 */ -#endif - 0x0A, 0x4C, // ldr r4, STM32_FLASH_BASE - 0x01, 0x25, // mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */ - 0x04, 0x26, // mov r6, #4 /* PGERR */ - // write_half_word: - 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */ - 0x2B, 0x43, // orr r3, r5 - 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */ - 0x03, 0x88, // ldrh r3, [r0] /* r3 = *sram */ - 0x0B, 0x80, // strh r3, [r1] /* *flash = r3 */ - // busy: - 0xE3, 0x68, // ldr r3, [r4, #12] /* FLASH->SR */ - 0x2B, 0x42, // tst r3, r5 /* FLASH_SR_BUSY */ - 0xFC, 0xD0, // beq busy - - 0x33, 0x42, // tst r3, r6 /* PGERR */ - 0x04, 0xD1, // bne exit - - 0x02, 0x30, // add r0, r0, #2 /* sram += 2 */ - 0x02, 0x31, // add r1, r1, #2 /* flash += 2 */ - 0x01, 0x3A, // sub r2, r2, #0x01 /* count-- */ - 0x00, 0x2A, // cmp r2, #0 - 0xF0, 0xD1, // bne write_half_word - // exit: - 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */ - 0xAB, 0x43, // bic r3, r5 - 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */ - 0x00, 0xBE, // bkpt #0x00 - 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */ - }; - - static const uint8_t loader_code_stm32l[] = { - // flashloaders/stm32lx.s - - 0x04, 0xe0, // b test_done ; Go to compare - // write_word: - 0x04, 0x68, // ldr r4, [r0] ; Load one word from address in r0 - 0x0c, 0x60, // str r4, [r1] ; Store the word to address in r1 - 0x04, 0x30, // adds r0, #4 ; Increment r0 - 0x04, 0x31, // adds r1, #4 ; Increment r1 - 0x01, 0x3a, // subs r2, #1 ; Decrement r2 - // test_done: - 0x00, 0x2a, // cmp r2, #0 ; Compare r2 to 0 - 0xf8, 0xd8, // bhi write_word ; Loop if above 0 - 0x00, 0xbe, // bkpt #0x00 ; Set breakpoint to exit - 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32f4[] = { - // flashloaders/stm32f4.s - - 0x07, 0x4b, - - 0x62, 0xb1, - 0x04, 0x68, - 0x0c, 0x60, - - 0xdc, 0x89, - 0x14, 0xf0, 0x01, 0x0f, - 0xfb, 0xd1, - 0x00, 0xf1, 0x04, 0x00, - 0x01, 0xf1, 0x04, 0x01, - 0xa2, 0xf1, 0x01, 0x02, - 0xf1, 0xe7, - - 0x00, 0xbe, - - 0x00, 0x3c, 0x02, 0x40, - }; - - static const uint8_t loader_code_stm32f4_lv[] = { - // flashloaders/stm32f4lv.s - 0x92, 0x00, - - 0x08, 0x4b, - 0x62, 0xb1, - 0x04, 0x78, - 0x0c, 0x70, - - 0xdc, 0x89, - 0x14, 0xf0, 0x01, 0x0f, - 0xfb, 0xd1, - 0x00, 0xf1, 0x01, 0x00, - 0x01, 0xf1, 0x01, 0x01, - 0xa2, 0xf1, 0x01, 0x02, - 0xf1, 0xe7, - - 0x00, 0xbe, - 0x00, 0xbf, - - 0x00, 0x3c, 0x02, 0x40, - }; - - static const uint8_t loader_code_stm32l4[] = { - // flashloaders/stm32l4.s - 0x08, 0x4b, // start: ldr r3, [pc, #32] ; - 0x72, 0xb1, // next: cbz r2, - 0x04, 0x68, // ldr r4, [r0, #0] - 0x45, 0x68, // ldr r5, [r0, #4] - 0x0c, 0x60, // str r4, [r1, #0] - 0x4d, 0x60, // str r5, [r1, #4] - 0x5c, 0x8a, // wait: ldrh r4, [r3, #18] - 0x14, 0xf0, 0x01, 0x0f, // tst.w r4, #1 - 0xfb, 0xd1, // bne.n - 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8 - 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8 - 0xa2, 0xf1, 0x01, 0x02, // sub.w r2, r2, #1 - 0xef, 0xe7, // b.n - 0x00, 0xbe, // done: bkpt 0x0000 - 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000 - }; - - static const uint8_t loader_code_stm32f7[] = { - 0x08, 0x4b, - 0x72, 0xb1, - 0x04, 0x68, - 0x0c, 0x60, - 0xbf, 0xf3, 0x4f, 0x8f, // DSB Memory barrier for in order flash write - 0xdc, 0x89, - 0x14, 0xf0, 0x01, 0x0f, - 0xfb, 0xd1, - 0x00, 0xf1, 0x04, 0x00, - 0x01, 0xf1, 0x04, 0x01, - 0xa2, 0xf1, 0x01, 0x02, - 0xef, 0xe7, - 0x00, 0xbe, // bkpt #0x00 - 0x00, 0x3c, 0x02, 0x40, - }; - - const uint8_t* loader_code; - size_t loader_size; - - if (sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2 - || sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS || sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH - || sl->chip_id == STLINK_CHIPID_STM32_L152_RE - || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */ - loader_code = loader_code_stm32l; - loader_size = sizeof(loader_code_stm32l); - } else if (sl->core_id == STM32VL_CORE_ID - || sl->chip_id == STLINK_CHIPID_STM32_F3 - || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL - || sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH - || sl->chip_id == STLINK_CHIPID_STM32_F37x - || sl->chip_id == STLINK_CHIPID_STM32_F334) { - loader_code = loader_code_stm32vl; - loader_size = sizeof(loader_code_stm32vl); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || - sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F4_DE || - sl->chip_id == STLINK_CHIPID_STM32_F4_LP || - sl->chip_id == STLINK_CHIPID_STM32_F4_HD || - sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || - sl->chip_id == STLINK_CHIPID_STM32_F410 || - sl->chip_id == STLINK_CHIPID_STM32_F411RE || - sl->chip_id == STLINK_CHIPID_STM32_F446 - ) { - int voltage = stlink_target_voltage(sl); - if (voltage == -1) { - printf("Failed to read Target voltage\n"); - return voltage; - } else if (voltage > 2700) { - loader_code = loader_code_stm32f4; - loader_size = sizeof(loader_code_stm32f4); - } else { - loader_code = loader_code_stm32f4_lv; - loader_size = sizeof(loader_code_stm32f4_lv); - } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7){ - loader_code = loader_code_stm32f7; - loader_size = sizeof(loader_code_stm32f7); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || sl->chip_id == STLINK_CHIPID_STM32_F0_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F09X) { - loader_code = loader_code_stm32f0; - loader_size = sizeof(loader_code_stm32f0); - } else if (sl->chip_id == STLINK_CHIPID_STM32_L4) { - loader_code = loader_code_stm32l4; - loader_size = sizeof(loader_code_stm32l4); - } else { - ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); - return -1; - } - - memcpy(sl->q_buf, loader_code, loader_size); - stlink_write_mem32(sl, sl->sram_base, loader_size); - - *addr = sl->sram_base; - *size = loader_size; - - /* success */ - return 0; -} - int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* check the contents of path are at addr */ @@ -1729,8 +1483,8 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin ILOG("Starting Half page flash write for STM32L core id\n"); /* flash loader initialization */ - if (init_flash_loader(sl, &fl) == -1) { - WLOG("init_flash_loader() == -1\n"); + if (stlink_flash_loader_init(sl, &fl) == -1) { + WLOG("stlink_flash_loader_init() == -1\n"); return -1; } /* Unlock already done */ @@ -1745,8 +1499,8 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin } while ((val & (1 << 0)) != 0); for (count = 0; count < num_half_pages; count ++) { - if (run_flash_loader(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) { - WLOG("l1_run_flash_loader(%#zx) failed! == -1\n", addr + count * pagesize); + if (stlink_flash_loader_run(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) { + WLOG("l1_stlink_flash_loader_run(%#zx) failed! == -1\n", addr + count * pagesize); stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG)); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); @@ -1827,8 +1581,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t ILOG("Starting Flash write for F2/F4/L4\n"); /* flash loader initialization */ - if (init_flash_loader(sl, &fl) == -1) { - ELOG("init_flash_loader() == -1\n"); + if (stlink_flash_loader_init(sl, &fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); return -1; } @@ -1869,8 +1623,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t printf("size: %zu\n", size); - if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { - ELOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); + if (stlink_flash_loader_run(sl, &fl, addr + off, base + off, size) == -1) { + ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); return -1; } @@ -1960,8 +1714,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } else if (sl->flash_type == FLASH_TYPE_F0) { ILOG("Starting Flash write for VL/F0/F3 core id\n"); /* flash loader initialization */ - if (init_flash_loader(sl, &fl) == -1) { - ELOG("init_flash_loader() == -1\n"); + if (stlink_flash_loader_init(sl, &fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); return -1; } @@ -1974,9 +1728,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t /* unlock and set programming mode */ unlock_flash_if(sl); set_flash_cr_pg(sl); - //DLOG("Finished setting flash cr pg, running loader!\n"); - if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { - ELOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); + DLOG("Finished setting flash cr pg, running loader!\n"); + if (stlink_flash_loader_run(sl, &fl, addr + off, base + off, size) == -1) { + ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); return -1; } lock_flash(sl); @@ -2042,64 +1796,3 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { unmap_file(&mf); return err; } - -int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { - - reg rr; - int i = 0; - size_t count = 0; - - DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); - // FIXME This can never return -1 - if (write_buffer_to_sram(sl, fl, buf, size) == -1) { - // IMPOSSIBLE! - ELOG("write_buffer_to_sram() == -1\n"); - return -1; - } - - if (sl->flash_type == FLASH_TYPE_F0) { - count = size / sizeof(uint16_t); - if (size % sizeof(uint16_t)) - ++count; - } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L0) { - count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) - ++count; - } else if (sl->flash_type == FLASH_TYPE_L4) { - count = size / sizeof(uint64_t); - if (size % sizeof(uint64_t)) - ++count; - } - - /* setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); /* source */ - stlink_write_reg(sl, target, 1); /* target */ - stlink_write_reg(sl, count, 2); /* count */ - stlink_write_reg(sl, 0, 3); /* flash bank 0 (input), only used on F0, but armless fopr others */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - - /* run loader */ - stlink_run(sl); - -#define WAIT_ROUNDS 10000 - /* wait until done (reaches breakpoint) */ - for (i = 0; i < WAIT_ROUNDS; i++) { - usleep(10); - if (is_core_halted(sl)) - break; - } - - if (i >= WAIT_ROUNDS) { - ELOG("flash loader run error\n"); - return -1; - } - - /* check written byte count */ - stlink_read_reg(sl, 2, &rr); - if (rr.r[2] != 0) { - fprintf(stderr, "write error, count == %u\n", rr.r[2]); - return -1; - } - - return 0; -} diff --git a/src/flash_loader.c b/src/flash_loader.c new file mode 100644 index 000000000..bf4c92f14 --- /dev/null +++ b/src/flash_loader.c @@ -0,0 +1,313 @@ +#include "stlink.h" + +/* from openocd, contrib/loaders/flash/stm32.s */ +static const uint8_t loader_code_stm32vl[] = { + 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */ + 0x1c, 0x44, /* add r4, r3 */ + /* write_half_word: */ + 0x01, 0x23, /* movs r3, #0x01 */ + 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */ + 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */ + 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */ + /* busy: */ + 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */ + 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */ + 0xfb, 0xd0, /* beq busy */ + 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */ + 0x01, 0xd1, /* bne exit */ + 0x01, 0x3a, /* subs r2, r2, #0x01 */ + 0xf0, 0xd1, /* bne write_half_word */ + /* exit: */ + 0x00, 0xbe, /* bkpt #0x00 */ + 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */ + }; + + /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ + static const uint8_t loader_code_stm32f0[] = { +#if 1 + /* + * These two NOPs here are a safety precaution, added by Pekka Nikander + * while debugging the STM32F05x support. They may not be needed, but + * there were strange problems with simpler programs, like a program + * that had just a breakpoint or a program that first moved zero to register r2 + * and then had a breakpoint. So, it appears safest to have these two nops. + * + * Feel free to remove them, if you dare, but then please do test the result + * rigorously. Also, if you remove these, it may be a good idea first to + * #if 0 them out, with a comment when these were taken out, and to remove + * these only a few months later... But YMMV. + */ + 0x00, 0x30, // nop /* add r0,#0 */ + 0x00, 0x30, // nop /* add r0,#0 */ +#endif + 0x0A, 0x4C, // ldr r4, STM32_FLASH_BASE + 0x01, 0x25, // mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */ + 0x04, 0x26, // mov r6, #4 /* PGERR */ + // write_half_word: + 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */ + 0x2B, 0x43, // orr r3, r5 + 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */ + 0x03, 0x88, // ldrh r3, [r0] /* r3 = *sram */ + 0x0B, 0x80, // strh r3, [r1] /* *flash = r3 */ + // busy: + 0xE3, 0x68, // ldr r3, [r4, #12] /* FLASH->SR */ + 0x2B, 0x42, // tst r3, r5 /* FLASH_SR_BUSY */ + 0xFC, 0xD0, // beq busy + + 0x33, 0x42, // tst r3, r6 /* PGERR */ + 0x04, 0xD1, // bne exit + + 0x02, 0x30, // add r0, r0, #2 /* sram += 2 */ + 0x02, 0x31, // add r1, r1, #2 /* flash += 2 */ + 0x01, 0x3A, // sub r2, r2, #0x01 /* count-- */ + 0x00, 0x2A, // cmp r2, #0 + 0xF0, 0xD1, // bne write_half_word + // exit: + 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */ + 0xAB, 0x43, // bic r3, r5 + 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */ + 0x00, 0xBE, // bkpt #0x00 + 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */ + }; + + static const uint8_t loader_code_stm32l[] = { + // flashloaders/stm32lx.s + + 0x04, 0xe0, // b test_done ; Go to compare + // write_word: + 0x04, 0x68, // ldr r4, [r0] ; Load one word from address in r0 + 0x0c, 0x60, // str r4, [r1] ; Store the word to address in r1 + 0x04, 0x30, // adds r0, #4 ; Increment r0 + 0x04, 0x31, // adds r1, #4 ; Increment r1 + 0x01, 0x3a, // subs r2, #1 ; Decrement r2 + // test_done: + 0x00, 0x2a, // cmp r2, #0 ; Compare r2 to 0 + 0xf8, 0xd8, // bhi write_word ; Loop if above 0 + 0x00, 0xbe, // bkpt #0x00 ; Set breakpoint to exit + 0x00, 0x00 + }; + + static const uint8_t loader_code_stm32f4[] = { + // flashloaders/stm32f4.s + + 0x07, 0x4b, + + 0x62, 0xb1, + 0x04, 0x68, + 0x0c, 0x60, + + 0xdc, 0x89, + 0x14, 0xf0, 0x01, 0x0f, + 0xfb, 0xd1, + 0x00, 0xf1, 0x04, 0x00, + 0x01, 0xf1, 0x04, 0x01, + 0xa2, 0xf1, 0x01, 0x02, + 0xf1, 0xe7, + + 0x00, 0xbe, + + 0x00, 0x3c, 0x02, 0x40, + }; + + static const uint8_t loader_code_stm32f4_lv[] = { + // flashloaders/stm32f4lv.s + 0x92, 0x00, + + 0x08, 0x4b, + 0x62, 0xb1, + 0x04, 0x78, + 0x0c, 0x70, + + 0xdc, 0x89, + 0x14, 0xf0, 0x01, 0x0f, + 0xfb, 0xd1, + 0x00, 0xf1, 0x01, 0x00, + 0x01, 0xf1, 0x01, 0x01, + 0xa2, 0xf1, 0x01, 0x02, + 0xf1, 0xe7, + + 0x00, 0xbe, + 0x00, 0xbf, + + 0x00, 0x3c, 0x02, 0x40, + }; + + static const uint8_t loader_code_stm32l4[] = { + // flashloaders/stm32l4.s + 0x08, 0x4b, // start: ldr r3, [pc, #32] ; + 0x72, 0xb1, // next: cbz r2, + 0x04, 0x68, // ldr r4, [r0, #0] + 0x45, 0x68, // ldr r5, [r0, #4] + 0x0c, 0x60, // str r4, [r1, #0] + 0x4d, 0x60, // str r5, [r1, #4] + 0x5c, 0x8a, // wait: ldrh r4, [r3, #18] + 0x14, 0xf0, 0x01, 0x0f, // tst.w r4, #1 + 0xfb, 0xd1, // bne.n + 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8 + 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8 + 0xa2, 0xf1, 0x01, 0x02, // sub.w r2, r2, #1 + 0xef, 0xe7, // b.n + 0x00, 0xbe, // done: bkpt 0x0000 + 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000 + }; + + static const uint8_t loader_code_stm32f7[] = { + 0x08, 0x4b, + 0x72, 0xb1, + 0x04, 0x68, + 0x0c, 0x60, + 0xbf, 0xf3, 0x4f, 0x8f, // DSB Memory barrier for in order flash write + 0xdc, 0x89, + 0x14, 0xf0, 0x01, 0x0f, + 0xfb, 0xd1, + 0x00, 0xf1, 0x04, 0x00, + 0x01, 0xf1, 0x04, 0x01, + 0xa2, 0xf1, 0x01, 0x02, + 0xef, 0xe7, + 0x00, 0xbe, // bkpt #0x00 + 0x00, 0x3c, 0x02, 0x40, + }; + + + +int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) +{ + size_t size; + + /* allocate the loader in sram */ + if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { + WLOG("Failed to write flash loader to sram!\n"); + return -1; + } + + /* allocate a one page buffer in sram right after loader */ + fl->buf_addr = fl->loader_addr + size; + ILOG("Successfully loaded flash loader in sram\n"); + + return 0; +} + +int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) +{ + const uint8_t* loader_code; + size_t loader_size; + + if (sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2 + || sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS || sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH + || sl->chip_id == STLINK_CHIPID_STM32_L152_RE + || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */ + loader_code = loader_code_stm32l; + loader_size = sizeof(loader_code_stm32l); + } else if (sl->core_id == STM32VL_CORE_ID + || sl->chip_id == STLINK_CHIPID_STM32_F3 + || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL + || sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH + || sl->chip_id == STLINK_CHIPID_STM32_F37x + || sl->chip_id == STLINK_CHIPID_STM32_F334) { + loader_code = loader_code_stm32vl; + loader_size = sizeof(loader_code_stm32vl); + } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || + sl->chip_id == STLINK_CHIPID_STM32_F4 || + sl->chip_id == STLINK_CHIPID_STM32_F4_DE || + sl->chip_id == STLINK_CHIPID_STM32_F4_LP || + sl->chip_id == STLINK_CHIPID_STM32_F4_HD || + sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || + sl->chip_id == STLINK_CHIPID_STM32_F410 || + sl->chip_id == STLINK_CHIPID_STM32_F411RE || + sl->chip_id == STLINK_CHIPID_STM32_F446 + ) { + int voltage = stlink_target_voltage(sl); + if (voltage == -1) { + printf("Failed to read Target voltage\n"); + return voltage; + } else if (voltage > 2700) { + loader_code = loader_code_stm32f4; + loader_size = sizeof(loader_code_stm32f4); + } else { + loader_code = loader_code_stm32f4_lv; + loader_size = sizeof(loader_code_stm32f4_lv); + } + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7){ + loader_code = loader_code_stm32f7; + loader_size = sizeof(loader_code_stm32f7); + } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || sl->chip_id == STLINK_CHIPID_STM32_F0_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F09X) { + loader_code = loader_code_stm32f0; + loader_size = sizeof(loader_code_stm32f0); + } else if (sl->chip_id == STLINK_CHIPID_STM32_L4) { + loader_code = loader_code_stm32l4; + loader_size = sizeof(loader_code_stm32l4); + } else { + ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); + return -1; + } + + memcpy(sl->q_buf, loader_code, loader_size); + stlink_write_mem32(sl, sl->sram_base, loader_size); + + *addr = sl->sram_base; + *size = loader_size; + + /* success */ + return 0; +} + +int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) +{ + reg rr; + int i = 0; + size_t count = 0; + + DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); + // FIXME This can never return -1 + if (write_buffer_to_sram(sl, fl, buf, size) == -1) { + // IMPOSSIBLE! + ELOG("write_buffer_to_sram() == -1\n"); + return -1; + } + + if (sl->flash_type == FLASH_TYPE_F0) { + count = size / sizeof(uint16_t); + if (size % sizeof(uint16_t)) + ++count; + } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L0) { + count = size / sizeof(uint32_t); + if (size % sizeof(uint32_t)) + ++count; + } else if (sl->flash_type == FLASH_TYPE_L4) { + count = size / sizeof(uint64_t); + if (size % sizeof(uint64_t)) + ++count; + } + + /* setup core */ + stlink_write_reg(sl, fl->buf_addr, 0); /* source */ + stlink_write_reg(sl, target, 1); /* target */ + stlink_write_reg(sl, count, 2); /* count */ + stlink_write_reg(sl, 0, 3); /* flash bank 0 (input), only used on F0, but armless fopr others */ + stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ + + /* run loader */ + stlink_run(sl); + +#define WAIT_ROUNDS 10000 + /* wait until done (reaches breakpoint) */ + for (i = 0; i < WAIT_ROUNDS; i++) { + usleep(10); + if (is_core_halted(sl)) + break; + } + + if (i >= WAIT_ROUNDS) { + ELOG("flash loader run error\n"); + return -1; + } + + /* check written byte count */ + stlink_read_reg(sl, 2, &rr); + if (rr.r[2] != 0) { + ELOG("write error, count == %u\n", rr.r[2]); + return -1; + } + + return 0; +} From f8d711818d020f727cdf6ca7192d43dad40604c8 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 20 May 2016 20:36:41 +0200 Subject: [PATCH 0430/1435] cmake: Search for static libusb-1.0 library on OSX and link with ObjC,CoreFoundation and IOKit frameworks --- CMakeLists.txt | 9 ++++- cmake/modules/FindLibUSB.cmake | 60 +++++++++++++++++++--------------- 2 files changed, 41 insertions(+), 28 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index dab482939..efadb5c7f 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -73,7 +73,14 @@ include_directories(src/mingw) add_library(${PROJECT_NAME} STATIC ${STLINK_HEADERS} # header files for ide projects generated by cmake ${STLINK_SOURCE}) -target_link_libraries(${PROJECT_NAME} ${LIBUSB_LIBRARIES}) +target_link_libraries(${PROJECT_NAME} ${LIBUSB_LIBRARY}) + +if (APPLE) + find_library(ObjC objc) + find_library(CoreFoundation CoreFoundation) + find_library(IOKit IOKit) + target_link_libraries(${PROJECT_NAME} ${CoreFoundation} ${IOKit} ${ObjC}) +endif() add_executable(st-flash src/tools/flash.c) target_link_libraries(st-flash ${PROJECT_NAME}) diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index 2e518a7a6..7f14ca125 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -1,27 +1,33 @@ -# FindLibUSB.cmake - Try to find the Hiredis library -# Once done this will define -# -# LIBUSB_FOUND - System has libusb -# LIBUSB_INCLUDE_DIR - The libusb include directory -# LIBUSB_LIBRARIES - The libraries needed to use libusb -# LIBUSB_DEFINITIONS - Compiler switches required for using libusb - -FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h - HINTS - /usr - /usr/local - /opt - PATH_SUFFIXES libusb-1.0 - ) - -FIND_LIBRARY(LIBUSB_LIBRARIES NAMES usb-1.0 - HINTS - /usr - /usr/local - /opt - ) - -INCLUDE(FindPackageHandleStandardArgs) -FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARIES LIBUSB_INCLUDE_DIR) - -MARK_AS_ADVANCED(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARIES) +# FindLibUSB.cmake - Try to find the Hiredis library +# Once done this will define +# +# LIBUSB_FOUND - System has libusb +# LIBUSB_INCLUDE_DIR - The libusb include directory +# LIBUSB_LIBRARY - The libraries needed to use libusb +# LIBUSB_DEFINITIONS - Compiler switches required for using libusb + +FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h + HINTS + /usr + /usr/local + /opt + PATH_SUFFIXES libusb-1.0 + ) + +if (APPLE) + set(LIBUSB_NAME libusb-1.0.a) +else() + set(LIBUSB_NAME usb-1.0) +endif() + +FIND_LIBRARY(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS + /usr + /usr/local + /opt +) + +INCLUDE(FindPackageHandleStandardArgs) +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + +MARK_AS_ADVANCED(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) From 74389ba7b840fb8be27d3eea2b04b50927491a65 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 20 May 2016 20:49:29 +0200 Subject: [PATCH 0431/1435] travis: Add gcc-5 and clang-3.8 to matrix for linux cmake builds --- .travis.sh | 6 ++++++ .travis.yml | 27 ++++++++++++++++++--------- 2 files changed, 24 insertions(+), 9 deletions(-) diff --git a/.travis.sh b/.travis.sh index 13d2c1dcd..9e28d3ca1 100755 --- a/.travis.sh +++ b/.travis.sh @@ -1,4 +1,10 @@ #!/bin/bash +echo "-- C compilers available" +ls -1 /usr/bin/gcc* +ls -1 /usr/bin/clang* +ls -1 /usr/bin/scan-build* +echo "----" + if [ "$TRAVIS_OS_NAME" != "osx" ]; then sudo apt-get update -qq || true sudo apt-get install -qq -y --no-install-recommends libusb-1.0.0-dev libgtk-3-dev diff --git a/.travis.yml b/.travis.yml index 5164d36c5..0fae3aaeb 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,24 +1,33 @@ sudo: true language: c +addons: + apt: + sources: + - llvm-toolchain-precise-3.8 + - ubuntu-toolchain-r-test + packages: + - clang-3.8 + - g++-5 + - gcc-5 script: - ./.travis.sh matrix: include: - - os: osx - compiler: clang - env: "BUILD_SYSTEM=cmake" - - os: osx + - os: linux + compiler: gcc + env: "BUILD_SYSTEM=autotools" + - os: linux compiler: clang env: "BUILD_SYSTEM=autotools" - os: linux - compiler: gcc + compiler: gcc-5 env: "BUILD_SYSTEM=cmake" - os: linux + compiler: clang-3.8 + env: "BUILD_SYSTEM=cmake" + - os: osx compiler: clang env: "BUILD_SYSTEM=cmake" - - os: linux - compiler: gcc - env: "BUILD_SYSTEM=autotools" - - os: linux + - os: osx compiler: clang env: "BUILD_SYSTEM=autotools" From e2a4fb37d4b13ad98e1349f6e57c877ef9c98e02 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 20 May 2016 23:11:43 +0200 Subject: [PATCH 0432/1435] Move USB defines into usb.h, move chip register defines into new reg.h --- include/stlink.h | 26 +++----------------------- include/stlink/reg.h | 8 ++++++++ include/stlink/usb.h | 5 +++++ src/common.c | 19 ++++++++++++------- src/flash_loader.c | 2 +- src/gdbserver/gdb-server.c | 6 +++--- src/go/main | Bin 0 -> 2777276 bytes src/sg.c | 9 ++++++--- src/usb.c | 16 ++++++++-------- 9 files changed, 46 insertions(+), 45 deletions(-) create mode 100644 include/stlink/reg.h create mode 100755 src/go/main diff --git a/include/stlink.h b/include/stlink.h index a20f815cb..3b860052f 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -9,6 +9,7 @@ #include #include +#include #ifdef __cplusplus extern "C" { @@ -21,15 +22,7 @@ extern "C" { //#define Q_BUF_LEN 96 #define Q_BUF_LEN (1024 * 100) - // st-link vendor cmd's -#define USB_ST_VID 0x0483 -#define USB_STLINK_PID 0x3744 -#define USB_STLINK_32L_PID 0x3748 -#define USB_STLINK_NUCLEO_PID 0x374b - // STLINK_DEBUG_RESETSYS, etc: -#define STLINK_OK 0x80 -#define STLINK_FALSE 0x81 #define STLINK_CORE_RUNNING 0x80 #define STLINK_CORE_HALTED 0x81 #define STLINK_CORE_STAT_UNKNOWN -1 @@ -41,7 +34,6 @@ extern "C" { #define STLINK_DEBUG_COMMAND 0xF2 #define STLINK_DFU_COMMAND 0xF3 #define STLINK_DFU_EXIT 0x07 - // enter dfu could be 0x08? // STLINK_GET_CURRENT_MODE #define STLINK_DEV_DFU_MODE 0x00 @@ -55,20 +47,10 @@ extern "C" { #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35 #define STLINK_JTAG_READDEBUG_32BIT 0x36 #define STLINK_JTAG_DRIVE_NRST 0x3c -#define STLINK_JTAG_DRIVE_NRST 0x3c - - // cortex m3 technical reference manual -#define CM3_REG_CPUID 0xE000ED00 -#define CM3_REG_FP_CTRL 0xE0002000 -#define CM3_REG_FP_COMP0 0xE0002008 /* cortex core ids */ // TODO clean this up... #define STM32VL_CORE_ID 0x1ba01477 -#define STM32L_CORE_ID 0x2ba01477 -#define STM32F3_CORE_ID 0x2ba01477 -#define STM32F4_CORE_ID 0x2ba01477 -#define STM32F0_CORE_ID 0xbb11477 #define CORE_M3_R1 0x1BA00477 #define CORE_M3_R2 0x4BA00477 #define CORE_M4_R0 0x2BA01477 @@ -251,12 +233,9 @@ typedef struct flash_loader { int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); - // PUBLIC int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); - // privates, publics, the rest.... - // TODO sort what is private, and what is not int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); uint16_t read_uint16(const unsigned char *c, const int pt); @@ -266,7 +245,7 @@ typedef struct flash_loader { uint32_t read_uint32(const unsigned char *c, const int pt); void write_uint32(unsigned char* buf, uint32_t ui); void write_uint16(unsigned char* buf, uint16_t ui); - unsigned int is_core_halted(stlink_t *sl); + bool stlink_is_core_halted(stlink_t *sl); int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size); @@ -275,6 +254,7 @@ typedef struct flash_loader { #include "stlink/sg.h" #include "stlink/usb.h" +#include "stlink/reg.h" #include "stlink/commands.h" #include "stlink/chipid.h" #include "stlink/flash_loader.h" diff --git a/include/stlink/reg.h b/include/stlink/reg.h new file mode 100644 index 000000000..c6af166d3 --- /dev/null +++ b/include/stlink/reg.h @@ -0,0 +1,8 @@ +#ifndef STLINK_REG_H_ +#define STLINK_REG_H_ + +#define STLINK_REG_CM3_CPUID 0xE000ED00 +#define STLINK_REG_CM3_FP_CTRL 0xE0002000 +#define STLINK_REG_CM3_FP_COMP0 0xE0002008 + +#endif /* STLINK_REG_H_ */ diff --git a/include/stlink/usb.h b/include/stlink/usb.h index 76ac9211f..46e7419cf 100644 --- a/include/stlink/usb.h +++ b/include/stlink/usb.h @@ -18,6 +18,11 @@ extern "C" { #endif +#define STLINK_USB_VID_ST 0x0483 +#define STLINK_USB_PID_STLINK 0x3744 +#define STLINK_USB_PID_STLINK_32L 0x3748 +#define STLINK_USB_PID_STLINK_NUCLEO 0x374b + #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 diff --git a/src/common.c b/src/common.c index 727048125..493f1b90e 100644 --- a/src/common.c +++ b/src/common.c @@ -550,7 +550,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { uint32_t raw; - if (stlink_read_debug32(sl, CM3_REG_CPUID, &raw)) + if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) return -1; cpuid->implementer_id = (raw >> 24) & 0x7f; @@ -692,7 +692,7 @@ int stlink_version(stlink_t *sl) { _parse_version(sl, &sl->version); - DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, USB_ST_VID); + DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, STLINK_USB_VID_ST); DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); DLOG("stlink version = 0x%x\n", sl->version.stlink_v); DLOG("jtag version = 0x%x\n", sl->version.jtag_v); @@ -836,10 +836,15 @@ int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *reg return sl->backend->write_unsupported_reg(sl, val, r_convert, regp); } -unsigned int is_core_halted(stlink_t *sl) { - /* return non zero if core is halted */ - stlink_status(sl); - return sl->q_buf[0] == STLINK_CORE_HALTED; +bool stlink_is_core_halted(stlink_t *sl) +{ + bool ret = false; + + stlink_status(sl); + if (sl->q_buf[0] == STLINK_CORE_HALTED) + ret = true; + + return ret; } int stlink_step(stlink_t *sl) { @@ -900,7 +905,7 @@ void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { stlink_run(sl); - while (is_core_halted(sl) == 0) + while (stlink_is_core_halted(sl)) usleep(3000000); } diff --git a/src/flash_loader.c b/src/flash_loader.c index bf4c92f14..23f235b5b 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -293,7 +293,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe /* wait until done (reaches breakpoint) */ for (i = 0; i < WAIT_ROUNDS; i++) { usleep(10); - if (is_core_halted(sl)) + if (stlink_is_core_halted(sl)) break; } diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index b57a299ac..c50e5be32 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -585,8 +585,8 @@ struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; static void init_code_breakpoints(stlink_t *sl) { unsigned int val; memset(sl->q_buf, 0, 4); - stlink_write_debug32(sl, CM3_REG_FP_CTRL, 0x03 /*KEY | ENABLE4*/); - stlink_read_debug32(sl, CM3_REG_FP_CTRL, &val); + stlink_write_debug32(sl, STLINK_REG_CM3_FP_CTRL, 0x03 /*KEY | ENABLE4*/); + stlink_read_debug32(sl, STLINK_REG_CM3_FP_CTRL, &val); code_break_num = ((val >> 4) & 0xf); code_lit_num = ((val >> 8) & 0xf); @@ -594,7 +594,7 @@ static void init_code_breakpoints(stlink_t *sl) { for(int i = 0; i < code_break_num; i++) { code_breaks[i].type = 0; - stlink_write_debug32(sl, CM3_REG_FP_COMP0 + i * 4, 0); + stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMP0 + i * 4, 0); } } diff --git a/src/go/main b/src/go/main new file mode 100755 index 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zMzvO_0IQy+U(?nYl+sL(IE@Q1@T~m?oOJ+X)%dW)`d?pE^^PAOtns|L7Vr}t{=UMb zrq+$|W|5U{jF10aH>(MRy19BV0bGqQZh(a2ZvH|{DR2tC%)#WQeI8ExXx@;5iQ|>< zL45-OrcIUdqyuBm(Ari(jSqEzX66y5vt5dmfg`x*T??JU)E;pHc^G_s zBVKld)bD}9%$X#a0g`uhPbj(H=0t--FA8vUo^~uQfY$7c!1Xj9bwh#~{|PoZ)_?1< zAP`xI72B3D5ilt@XU4BcToUDS1Lc5wK?DnmVg0kT>^W`|}=3pzk_-Au~}{e-58 zpACFApbc~>#_|}t8U7-6BGFU}<9f;*G^HOf0Wg2i<)%MKXW9SD<%f^2 z-;h9_a?d>>iAS6I8plDbgdCQ)HI(Z0j;=l(6iVD;g;9ehLAxIT=UUjb6TFfe&ueUl z*X^>NY;oQcvM@EZlvE=p6_#`{>Ix$Hi+a>pdqyHLfpI%OUCi)EiQkRO1XjF|HcmIV z3W^jt;#ncdb_cmd_blk); i++) sl->cdb_cmd_blk[i] = 0; @@ -952,7 +955,7 @@ static stlink_t* stlink_open(const int verbose) { libusb_set_debug(slsg->libusb_ctx, 3); - slsg->usb_handle = libusb_open_device_with_vid_pid(slsg->libusb_ctx, USB_ST_VID, USB_STLINK_PID); + slsg->usb_handle = libusb_open_device_with_vid_pid(slsg->libusb_ctx, STLINK_USB_VID_ST, STLINK_USB_PID_STLINK); if (slsg->usb_handle == NULL) { WLOG("Failed to find an stlink v1 by VID:PID\n"); libusb_close(slsg->usb_handle); @@ -1041,7 +1044,7 @@ stlink_t* stlink_v1_open_inner(const int verbose) { } stlink_version(sl); - if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { + if ((sl->version.st_vid != STLINK_USB_VID_ST) || (sl->version.stlink_pid != STLINK_USB_PID_STLINK)) { ELOG("WTF? successfully opened, but unable to read version details. BROKEN!\n"); return NULL; } @@ -1063,7 +1066,7 @@ stlink_t* stlink_v1_open_inner(const int verbose) { // re-query device info (and retest) stlink_version(sl); - if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { + if ((sl->version.st_vid != STLINK_USB_VID_ST) || (sl->version.stlink_pid != STLINK_USB_PID_STLINK)) { ELOG("WTF? successfully opened, but unable to read version details. BROKEN!\n"); return NULL; } diff --git a/src/usb.c b/src/usb.c index 9c04ec860..b30399835 100644 --- a/src/usb.c +++ b/src/usb.c @@ -761,7 +761,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 while (cnt--) { libusb_get_device_descriptor( list[cnt], &desc ); - if (desc.idVendor != USB_ST_VID) + if (desc.idVendor != STLINK_USB_VID_ST) continue; if (devBus && devAddr) { @@ -771,7 +771,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 } } - if ((desc.idProduct == USB_STLINK_32L_PID) || (desc.idProduct == USB_STLINK_NUCLEO_PID)) { + if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) || (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO)) { struct libusb_device_handle *handle; libusb_open(list[cnt], &handle); @@ -791,7 +791,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 continue; } - if (desc.idProduct == USB_STLINK_PID) { + if (desc.idProduct == STLINK_USB_PID_STLINK) { slu->protocoll = 1; break; } @@ -841,7 +841,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 // TODO - could use the scanning techniq from stm8 code here... slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; - if (desc.idProduct == USB_STLINK_NUCLEO_PID) { + if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO) { slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; } else { slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; @@ -906,8 +906,8 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { break; } - if (desc.idProduct != USB_STLINK_32L_PID && - desc.idProduct != USB_STLINK_NUCLEO_PID) + if (desc.idProduct != STLINK_USB_PID_STLINK_32L && + desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO) continue; slcnt++; @@ -930,8 +930,8 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { break; } - if (desc.idProduct != USB_STLINK_32L_PID && - desc.idProduct != USB_STLINK_NUCLEO_PID) + if (desc.idProduct != STLINK_USB_PID_STLINK_32L && + desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO) continue; struct libusb_device_handle* handle; From 43cbf733800129fde1fc741e0bf5e11f3edfc86e Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 20 May 2016 23:29:11 +0200 Subject: [PATCH 0433/1435] Further Refactor stlink.h into correct places and files, create backend.h --- include/stlink.h | 67 +++++-------------------------------- include/stlink/backend.h | 33 ++++++++++++++++++ include/stlink/chipid.h | 2 +- include/stlink/reg.h | 7 ++++ src/chipid.c | 72 ++++++++++++++++++++-------------------- src/common.c | 68 ++++++++++++++++++------------------- src/flash_loader.c | 6 ++-- src/usb.c | 8 ++--- 8 files changed, 126 insertions(+), 137 deletions(-) create mode 100644 include/stlink/backend.h diff --git a/include/stlink.h b/include/stlink.h index 3b860052f..72eebb70f 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -51,30 +51,20 @@ extern "C" { /* cortex core ids */ // TODO clean this up... #define STM32VL_CORE_ID 0x1ba01477 -#define CORE_M3_R1 0x1BA00477 -#define CORE_M3_R2 0x4BA00477 -#define CORE_M4_R0 0x2BA01477 // Constant STM32 memory map figures #define STM32_FLASH_BASE 0x08000000 #define STM32_SRAM_BASE 0x20000000 - /* Cortex™-M3 Technical Reference Manual */ - /* Debug Halting Control and Status Register */ -#define DHCSR 0xe000edf0 -#define DCRSR 0xe000edf4 -#define DCRDR 0xe000edf8 -#define DBGKEY 0xa05f0000 - /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 - enum flash_type { - FLASH_TYPE_UNKNOWN = 0, - FLASH_TYPE_F0, - FLASH_TYPE_L0, - FLASH_TYPE_F4, - FLASH_TYPE_L4, + enum stlink_flash_type { + STLINK_FLASH_TYPE_UNKNOWN = 0, + STLINK_FLASH_TYPE_F0, + STLINK_FLASH_TYPE_L0, + STLINK_FLASH_TYPE_F4, + STLINK_FLASH_TYPE_L4 }; typedef struct { @@ -123,34 +113,7 @@ typedef struct flash_loader { typedef struct _stlink stlink_t; - typedef struct _stlink_backend { - void (*close) (stlink_t * sl); - int (*exit_debug_mode) (stlink_t * sl); - int (*enter_swd_mode) (stlink_t * sl); - int (*enter_jtag_mode) (stlink_t * stl); - int (*exit_dfu_mode) (stlink_t * stl); - int (*core_id) (stlink_t * stl); - int (*reset) (stlink_t * stl); - int (*jtag_reset) (stlink_t * stl, int value); - int (*run) (stlink_t * stl); - int (*status) (stlink_t * stl); - int (*version) (stlink_t *sl); - int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); - int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); - int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*read_all_regs) (stlink_t *sl, reg * regp); - int (*read_reg) (stlink_t *sl, int r_idx, reg * regp); - int (*read_all_unsupported_regs) (stlink_t *sl, reg *regp); - int (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp); - int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp); - int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); - int (*step) (stlink_t * stl); - int (*current_mode) (stlink_t * stl); - int (*force_debug) (stlink_t *sl); - int32_t (*target_voltage) (stlink_t *sl); - } stlink_backend_t; +#include "stlink/backend.h" struct _stlink { struct _stlink_backend *backend; @@ -171,20 +134,12 @@ typedef struct flash_loader { char serial[16]; int serial_size; -#define STM32_FLASH_PGSZ 1024 -#define STM32L_FLASH_PGSZ 256 - -#define STM32F4_FLASH_PGSZ 16384 -#define STM32F4_FLASH_SIZE (128 * 1024 * 8) - - enum flash_type flash_type; + enum stlink_flash_type flash_type; stm32_addr_t flash_base; size_t flash_size; size_t flash_pgsz; /* sram settings */ -#define STM32_SRAM_SIZE (8 * 1024) -#define STM32L_SRAM_SIZE (16 * 1024) stm32_addr_t sram_base; size_t sram_size; @@ -195,9 +150,6 @@ typedef struct flash_loader { struct stlink_version_ version; }; - //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose); - - // delegated functions... int stlink_enter_swd_mode(stlink_t *sl); int stlink_enter_jtag_mode(stlink_t *sl); int stlink_exit_debug_mode(stlink_t *sl); @@ -225,8 +177,6 @@ typedef struct flash_loader { int stlink_force_debug(stlink_t *sl); int stlink_target_voltage(stlink_t *sl); - - // unprocessed int stlink_erase_flash_mass(stlink_t* sl); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); @@ -249,7 +199,6 @@ typedef struct flash_loader { int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size); - int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); int stlink_load_device_params(stlink_t *sl); #include "stlink/sg.h" diff --git a/include/stlink/backend.h b/include/stlink/backend.h new file mode 100644 index 000000000..20b1c7132 --- /dev/null +++ b/include/stlink/backend.h @@ -0,0 +1,33 @@ +#ifndef STLINK_BACKEND_H_ +#define STLINK_BACKEND_H_ + + typedef struct _stlink_backend { + void (*close) (stlink_t * sl); + int (*exit_debug_mode) (stlink_t * sl); + int (*enter_swd_mode) (stlink_t * sl); + int (*enter_jtag_mode) (stlink_t * stl); + int (*exit_dfu_mode) (stlink_t * stl); + int (*core_id) (stlink_t * stl); + int (*reset) (stlink_t * stl); + int (*jtag_reset) (stlink_t * stl, int value); + int (*run) (stlink_t * stl); + int (*status) (stlink_t * stl); + int (*version) (stlink_t *sl); + int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); + int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); + int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); + int (*read_all_regs) (stlink_t *sl, reg * regp); + int (*read_reg) (stlink_t *sl, int r_idx, reg * regp); + int (*read_all_unsupported_regs) (stlink_t *sl, reg *regp); + int (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp); + int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp); + int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); + int (*step) (stlink_t * stl); + int (*current_mode) (stlink_t * stl); + int (*force_debug) (stlink_t *sl); + int32_t (*target_voltage) (stlink_t *sl); + } stlink_backend_t; + +#endif /* STLINK_BACKEND_H_ */ diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 351bb5537..a5012e38f 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -61,7 +61,7 @@ enum stlink_stm32_chipids { struct stlink_chipid_params { uint32_t chip_id; char *description; - enum flash_type flash_type; + enum stlink_flash_type flash_type; uint32_t flash_size_reg; uint32_t flash_pagesize; uint32_t sram_size; diff --git a/include/stlink/reg.h b/include/stlink/reg.h index c6af166d3..917325fb6 100644 --- a/include/stlink/reg.h +++ b/include/stlink/reg.h @@ -5,4 +5,11 @@ #define STLINK_REG_CM3_FP_CTRL 0xE0002000 #define STLINK_REG_CM3_FP_COMP0 0xE0002008 +/* Cortex™-M3 Technical Reference Manual */ +/* Debug Halting Control and Status Register */ +#define STLINK_REG_DHCSR 0xe000edf0 +#define STLINK_REG_DHCSR_DBGKEY 0xa05f0000 +#define STLINK_REG_DCRSR 0xe000edf4 +#define STLINK_REG_DCRDR 0xe000edf8 + #endif /* STLINK_REG_H_ */ diff --git a/src/chipid.c b/src/chipid.c index 423fbcb1b..c3f1a9278 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -6,7 +6,7 @@ static const struct stlink_chipid_params devices[] = { //RM0385 and DS10916 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F7, .description = "F7 device", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1ff0f442, // section 41.2 .flash_pagesize = 0x800, // No flash pages .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 @@ -16,7 +16,7 @@ static const struct stlink_chipid_params devices[] = { { // table 2, PM0063 .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, .description = "F1 Medium-density device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, .sram_size = 0x5000, @@ -26,7 +26,7 @@ static const struct stlink_chipid_params devices[] = { { // table 1, PM0059 .chip_id = STLINK_CHIPID_STM32_F2, .description = "F2 device", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/ .flash_pagesize = 0x20000, .sram_size = 0x20000, @@ -36,7 +36,7 @@ static const struct stlink_chipid_params devices[] = { { // PM0063 .chip_id = STLINK_CHIPID_STM32_F1_LOW, .description = "F1 Low-density device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, .sram_size = 0x2800, @@ -46,7 +46,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F4, .description = "F4 device", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, .sram_size = 0x30000, @@ -56,7 +56,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F4_DSI, .description = "F46x and F47x device", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, .sram_size = 0x40000, @@ -66,7 +66,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F4_HD, .description = "F42x and F43x device", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, .sram_size = 0x40000, @@ -76,7 +76,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F4_LP, .description = "F4 device (low power)", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x10000, @@ -86,7 +86,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F411RE, .description = "F4 device (low power) - stm32f411re", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x20000, @@ -96,7 +96,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F4_DE, .description = "F4 device (Dynamic Efficency)", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x18000, @@ -106,7 +106,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F1_HIGH, .description = "F1 High-density device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x10000, @@ -118,7 +118,7 @@ static const struct stlink_chipid_params devices[] = { // not the sector write protection...) .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM, .description = "L1 Med-density device", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, .flash_pagesize = 0x100, .sram_size = 0x4000, @@ -128,7 +128,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_L1_CAT2, .description = "L1 Cat.2 device", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, .flash_pagesize = 0x100, .sram_size = 0x8000, @@ -138,7 +138,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, .description = "L1 Medium-Plus-density device", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/ @@ -148,7 +148,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_L1_HIGH, .description = "L1 High-density device", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/ @@ -158,7 +158,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_L152_RE, .description = "L152RE", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/ @@ -168,7 +168,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F1_CONN, .description = "F1 Connectivity line device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x10000, @@ -178,7 +178,7 @@ static const struct stlink_chipid_params devices[] = { {//Low and Medium density VL have same chipid. RM0041 25.6.1 .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, .description = "F1 Medium/Low-density Value Line device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, .sram_size = 0x2000,//0x1000 for low density devices @@ -189,7 +189,7 @@ static const struct stlink_chipid_params devices[] = { // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. .chip_id = STLINK_CHIPID_STM32_F446, .description = "F446 device", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1fff7a22, .flash_pagesize = 0x20000, .sram_size = 0x20000, @@ -200,7 +200,7 @@ static const struct stlink_chipid_params devices[] = { // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. .chip_id = STLINK_CHIPID_STM32_F410, .description = "F410 device", - .flash_type = FLASH_TYPE_F4, + .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1fff7a22, .flash_pagesize = 0x4000, .sram_size = 0x8000, @@ -212,7 +212,7 @@ static const struct stlink_chipid_params devices[] = { // Support based on DM00043574.pdf (RM0316) document. .chip_id = STLINK_CHIPID_STM32_F3, .description = "F3 device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0xa000, @@ -224,7 +224,7 @@ static const struct stlink_chipid_params devices[] = { // Support based on 303 above (37x and 30x have same memory map) .chip_id = STLINK_CHIPID_STM32_F37x, .description = "F3 device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0xa000, @@ -234,7 +234,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, .description = "F1 High-density value line device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x8000, @@ -244,7 +244,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F1_XL, .description = "F1 XL-density device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x18000, @@ -256,7 +256,7 @@ static const struct stlink_chipid_params devices[] = { //RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F0_CAN, .description = "F07x device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 @@ -268,7 +268,7 @@ static const struct stlink_chipid_params devices[] = { //RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F0, .description = "F0 device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 @@ -278,7 +278,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F09X, .description = "F09X device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) @@ -290,7 +290,7 @@ static const struct stlink_chipid_params devices[] = { //RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F04, .description = "F04x device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 @@ -302,7 +302,7 @@ static const struct stlink_chipid_params devices[] = { //RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F0_SMALL, .description = "F0 small device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 @@ -313,7 +313,7 @@ static const struct stlink_chipid_params devices[] = { // STM32F30x .chip_id = STLINK_CHIPID_STM32_F3_SMALL, .description = "F3 small device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0xa000, @@ -325,7 +325,7 @@ static const struct stlink_chipid_params devices[] = { // RM0367,RM0377 documents was used to find these parameters .chip_id = STLINK_CHIPID_STM32_L0, .description = "L0x3 device", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, .sram_size = 0x2000, @@ -337,7 +337,7 @@ static const struct stlink_chipid_params devices[] = { // RM0367,RM0377 documents was used to find these parameters .chip_id = STLINK_CHIPID_STM32_L0_CAT5, .description = "L0x Category 5 device", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, .sram_size = 0x5000, @@ -349,7 +349,7 @@ static const struct stlink_chipid_params devices[] = { // RM0367,RM0377 documents was used to find these parameters .chip_id = STLINK_CHIPID_STM32_L0_CAT2, .description = "L0x Category 2 device", - .flash_type = FLASH_TYPE_L0, + .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, .sram_size = 0x2000, @@ -361,7 +361,7 @@ static const struct stlink_chipid_params devices[] = { // RM0364 document was used to find these parameters .chip_id = STLINK_CHIPID_STM32_F334, .description = "F334 device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, .sram_size = 0x3000, @@ -373,7 +373,7 @@ static const struct stlink_chipid_params devices[] = { // Support based on DM00043574.pdf (RM0316) document rev 5. .chip_id = STLINK_CHIPID_STM32_F303_HIGH, .description = "F303 high density device", - .flash_type = FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register .flash_pagesize = 0x800, // 4.2.1 Flash memory organization .sram_size = 0x10000, // 3.3 Embedded SRAM @@ -385,7 +385,7 @@ static const struct stlink_chipid_params devices[] = { // From RM0351. .chip_id = STLINK_CHIPID_STM32_L4, .description = "L4 device", - .flash_type = FLASH_TYPE_L4, + .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671) .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81) // SRAM1 is "up to" 96k in the standard Cortex-M memory map; diff --git a/src/common.c b/src/common.c index 493f1b90e..2899f298d 100644 --- a/src/common.c +++ b/src/common.c @@ -185,9 +185,9 @@ static inline uint32_t read_flash_obr(stlink_t *sl) { static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t reg, res; - if (sl->flash_type == FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) reg = FLASH_F4_CR; - else if (sl->flash_type == FLASH_TYPE_L4) + else if (sl->flash_type == STLINK_FLASH_TYPE_L4) reg = STM32L4_FLASH_CR; else reg = FLASH_CR; @@ -204,9 +204,9 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ uint32_t cr_lock_shift, cr = read_flash_cr(sl); - if (sl->flash_type == FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) cr_lock_shift = FLASH_F4_CR_LOCK; - else if (sl->flash_type == FLASH_TYPE_L4) + else if (sl->flash_type == STLINK_FLASH_TYPE_L4) cr_lock_shift = STM32L4_FLASH_CR_LOCK; else cr_lock_shift = FLASH_CR_LOCK; @@ -221,9 +221,9 @@ static void unlock_flash(stlink_t *sl) { an invalid sequence results in a definitive lock of the FPEC block until next reset. */ - if (sl->flash_type == FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) key_reg = FLASH_F4_KEYR; - else if (sl->flash_type == FLASH_TYPE_L4) + else if (sl->flash_type == STLINK_FLASH_TYPE_L4) key_reg = STM32L4_FLASH_KEYR; else key_reg = FLASH_KEYR; @@ -249,10 +249,10 @@ static int unlock_flash_if(stlink_t *sl) { static void lock_flash(stlink_t *sl) { uint32_t cr_lock_shift, cr_reg, n; - if (sl->flash_type == FLASH_TYPE_F4) { + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == FLASH_TYPE_L4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; } else { @@ -270,10 +270,10 @@ static void set_flash_cr_pg(stlink_t *sl) { x = read_flash_cr(sl); - if (sl->flash_type == FLASH_TYPE_F4) { + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == FLASH_TYPE_L4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= 1 << STM32L4_FLASH_CR_PG; @@ -288,9 +288,9 @@ static void set_flash_cr_pg(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { uint32_t cr_reg, n; - if (sl->flash_type == FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) cr_reg = FLASH_F4_CR; - else if (sl->flash_type == FLASH_TYPE_L4) + else if (sl->flash_type == STLINK_FLASH_TYPE_L4) cr_reg = STM32L4_FLASH_CR; else cr_reg = FLASH_CR; @@ -312,10 +312,10 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { static void set_flash_cr_mer(stlink_t *sl) { uint32_t val, cr_reg, cr_mer; - if (sl->flash_type == FLASH_TYPE_F4) { + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; - } else if (sl->flash_type == FLASH_TYPE_L4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); } else { @@ -331,10 +331,10 @@ static void set_flash_cr_mer(stlink_t *sl) { static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { uint32_t val, cr_reg, cr_mer; - if (sl->flash_type == FLASH_TYPE_F4) { + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; - } else if (sl->flash_type == FLASH_TYPE_L4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); } else { @@ -350,10 +350,10 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { static void set_flash_cr_strt(stlink_t *sl) { uint32_t val, cr_reg, cr_strt; - if (sl->flash_type == FLASH_TYPE_F4) { + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == FLASH_TYPE_L4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_strt = 1 << STM32L4_FLASH_CR_STRT; } else { @@ -375,9 +375,9 @@ static inline uint32_t read_flash_acr(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res, sr_reg; - if (sl->flash_type == FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) sr_reg = FLASH_F4_SR; - else if (sl->flash_type == FLASH_TYPE_L4) + else if (sl->flash_type == STLINK_FLASH_TYPE_L4) sr_reg = STM32L4_FLASH_SR; else sr_reg = FLASH_SR; @@ -390,9 +390,9 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { static inline unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; - if (sl->flash_type == FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) sr_busy_shift = FLASH_F4_SR_BSY; - else if (sl->flash_type == FLASH_TYPE_L4) + else if (sl->flash_type == STLINK_FLASH_TYPE_L4) sr_busy_shift = STM32L4_FLASH_SR_BSY; else sr_busy_shift = FLASH_SR_BSY; @@ -491,7 +491,7 @@ int stlink_exit_debug_mode(stlink_t *sl) { int ret; DLOG("*** stlink_exit_debug_mode ***\n"); - ret = stlink_write_debug32(sl, DHCSR, DBGKEY); + ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); if (ret == -1) return ret; @@ -588,7 +588,7 @@ int stlink_load_device_params(stlink_t *sl) { return -1; } - if (params->flash_type == FLASH_TYPE_UNKNOWN) { + if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { WLOG("Invalid flash type, please check device declaration\n"); return -1; } @@ -800,7 +800,7 @@ int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { DLOG("*** stlink_read_unsupported_reg\n"); DLOG(" (%d) ***\n", r_idx); - /* Convert to values used by DCRSR */ + /* Convert to values used by STLINK_REG_DCRSR */ if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ r_convert = 0x14; } else if (r_idx == 0x40) { /* FPSCR */ @@ -821,7 +821,7 @@ int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *reg DLOG("*** stlink_write_unsupported_reg\n"); DLOG(" (%d) ***\n", r_idx); - /* Convert to values used by DCRSR */ + /* Convert to values used by STLINK_REG_DCRSR */ if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ r_convert = r_idx; /* The backend function handles this */ } else if (r_idx == 0x40) { /* FPSCR */ @@ -1237,7 +1237,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L4) { + if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_L4) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1283,7 +1283,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif - } else if (sl->flash_type == FLASH_TYPE_L0) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { uint32_t val; uint32_t flash_regs_base; @@ -1351,7 +1351,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == FLASH_TYPE_F0) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_F0) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1383,7 +1383,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - if (sl->flash_type == FLASH_TYPE_L0) { + if (sl->flash_type == STLINK_FLASH_TYPE_L0) { /* erase each page */ int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1581,7 +1581,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t if (eraseonly) return 0; - if ((sl->flash_type == FLASH_TYPE_F4) || (sl->flash_type == FLASH_TYPE_L4)) { + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_L4)) { /* todo: check write operation */ ILOG("Starting Flash write for F2/F4/L4\n"); @@ -1641,7 +1641,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } //STM32F4END - else if (sl->flash_type == FLASH_TYPE_L0) { + else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { /* use fast word write. todo: half page. */ uint32_t val; uint32_t flash_regs_base; @@ -1716,7 +1716,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == FLASH_TYPE_F0) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_F0) { ILOG("Starting Flash write for VL/F0/F3 core id\n"); /* flash loader initialization */ if (stlink_flash_loader_init(sl, &fl) == -1) { @@ -1774,7 +1774,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { return -1; } - if (sl->flash_type == FLASH_TYPE_L0) + if (sl->flash_type == STLINK_FLASH_TYPE_L0) erased_pattern = 0x00; else erased_pattern = 0xff; diff --git a/src/flash_loader.c b/src/flash_loader.c index 23f235b5b..eaba6d3c5 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -265,15 +265,15 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe return -1; } - if (sl->flash_type == FLASH_TYPE_F0) { + if (sl->flash_type == STLINK_FLASH_TYPE_F0) { count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; - } else if (sl->flash_type == FLASH_TYPE_F4 || sl->flash_type == FLASH_TYPE_L0) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_L0) { count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; - } else if (sl->flash_type == FLASH_TYPE_L4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { count = size / sizeof(uint64_t); if (size % sizeof(uint64_t)) ++count; diff --git a/src/usb.c b/src/usb.c index b30399835..3a72035ab 100644 --- a/src/usb.c +++ b/src/usb.c @@ -567,11 +567,11 @@ int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { sl->q_buf[i] = 0; } - ret = _stlink_usb_write_mem32(sl, DCRSR, 4); + ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); if (ret == -1) return ret; - _stlink_usb_read_mem32(sl, DCRDR, 4); + _stlink_usb_read_mem32(sl, STLINK_REG_DCRDR, 4); if (ret == -1) return ret; @@ -648,7 +648,7 @@ int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg write_uint32(sl->q_buf, val); - ret = _stlink_usb_write_mem32(sl, DCRDR, 4); + ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRDR, 4); if (ret == -1) return ret; @@ -657,7 +657,7 @@ int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg sl->q_buf[2] = 0x01; sl->q_buf[3] = 0; - return _stlink_usb_write_mem32(sl, DCRSR, 4); + return _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); } int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { From f6229cae508ac17799d87e4424e97f0e7818d1cc Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 21 May 2016 00:23:23 +0200 Subject: [PATCH 0434/1435] Fixup tests/usb.c to read from correct SRAM base, fixes #351 --- CMakeLists.txt | 2 ++ tests/{stlink_usb.c => usb.c} | 15 +++++++-------- 2 files changed, 9 insertions(+), 8 deletions(-) rename tests/{stlink_usb.c => usb.c} (93%) diff --git a/CMakeLists.txt b/CMakeLists.txt index efadb5c7f..d61a0aee3 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -129,3 +129,5 @@ if(gtk_FOUND) install(FILES src/tools/gui/stlink-gui.ui DESTINATION ${INSTALLED_UI_DIR}) endif() + +add_subdirectory(tests) diff --git a/tests/stlink_usb.c b/tests/usb.c similarity index 93% rename from tests/stlink_usb.c rename to tests/usb.c index 787ac12ce..1ae6442c1 100644 --- a/tests/stlink_usb.c +++ b/tests/usb.c @@ -1,15 +1,14 @@ #include -#include "stlink-common.h" +#include +int main(int ac, char** av) +{ + (void)ac; + (void)av; -int main(int ac, char** av) { stlink_t* sl; reg regs; - /* unused */ - ac = ac; - av = av; - sl = stlink_open_usb(10, 1, NULL); if (sl != NULL) { printf("-- version\n"); @@ -36,13 +35,13 @@ int main(int ac, char** av) { printf("cpuid:part = %#x, rev = %#x\n", cpuid.part, cpuid.revision); printf("-- read_sram\n"); - static const uint32_t sram_base = 0x8000000; + static const uint32_t sram_base = STM32_SRAM_BASE; uint32_t off; for (off = 0; off < 16; off += 4) stlink_read_mem32(sl, sram_base + off, 4); printf("FP_CTRL\n"); - stlink_read_mem32(sl, CM3_REG_FP_CTRL, 4); + stlink_read_mem32(sl, STLINK_REG_CM3_FP_CTRL, 4); // no idea what reg this is.. */ // stlink_read_mem32(sl, 0xe000ed90, 4); From 486cc10c7081b8c85e8b8a1c8f70a6f178768e0c Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 21 May 2016 00:28:14 +0200 Subject: [PATCH 0435/1435] Add forgotten tests/CMakeLists.txt --- src/go/main | Bin 2777276 -> 0 bytes tests/CMakeLists.txt | 9 +++++++++ 2 files changed, 9 insertions(+) delete mode 100755 src/go/main create mode 100644 tests/CMakeLists.txt diff --git a/src/go/main b/src/go/main deleted file mode 100755 index 25baad2edac802c6e79e95b5578c84591aa88783..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2777276 zcmeFad3;nw)<4_{L0cAY5FLXO3EFBvmc%ttqa6Xg(MFkZ3!8*Z!y-h|K}2vGIsw|I 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zMzvO_0IQy+U(?nYl+sL(IE@Q1@T~m?oOJ+X)%dW)`d?pE^^PAOtns|L7Vr}t{=UMb zrq+$|W|5U{jF10aH>(MRy19BV0bGqQZh(a2ZvH|{DR2tC%)#WQeI8ExXx@;5iQ|>< zL45-OrcIUdqyuBm(Ari(jSqEzX66y5vt5dmfg`x*T??JU)E;pHc^G_s zBVKld)bD}9%$X#a0g`uhPbj(H=0t--FA8vUo^~uQfY$7c!1Xj9bwh#~{|PoZ)_?1< zAP`xI72B3D5ilt@XU4BcToUDS1Lc5wK?DnmVg0kT>^W`|}=3pzk_-Au~}{e-58 zpACFApbc~>#_|}t8U7-6BGFU}<9f;*G^HOf0Wg2i<)%MKXW9SD<%f^2 z-;h9_a?d>>iAS6I8plDbgdCQ)HI(Z0j;=l(6iVD;g;9ehLAxIT=UUjb6TFfe&ueUl z*X^>NY;oQcvM@EZlvE=p6_#`{>Ix$Hi+a>pdqyHLfpI%OUCi)EiQkRO1XjF|HcmIV z3W^jt;#n Date: Thu, 26 May 2016 17:12:20 +0200 Subject: [PATCH 0436/1435] Update README Related to https://github.com/texane/stlink/issues/356 --- README | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/README b/README index 8fc282bc5..fc2231854 100644 --- a/README +++ b/README @@ -236,6 +236,21 @@ STLink v2-1 (as found on the Nucleo boards), known working targets: Please report any and all known working combinations so I can update this! +## Known bugs + +### Sometimes flashing only works after a mass erase + +There is seen a problem sometimes where a flash loader run error occurs and is resolved after mass-erase +of the flash: + +``` +2015-12-09T22:01:57 INFO src/stlink-common.c: Successfully loaded flash loader in sram +2015-12-09T22:02:18 ERROR src/stlink-common.c: flash loader run error +2015-12-09T22:02:18 ERROR src/stlink-common.c: run_flash_loader(0x8000000) failed! == -1 +``` + +Issue(s): [#356](https://github.com/texane/stlink/issues/356) + ## Contributing and versioning * The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) From 113f3e3507bdfb1a656f38e90ab0381f27f56f26 Mon Sep 17 00:00:00 2001 From: Jean-Marie Lemetayer Date: Thu, 2 Jun 2016 17:41:15 +0200 Subject: [PATCH 0437/1435] Fix multiple warnings - Replace 'typedef reg' by 'struct stlink_reg' - Prefix the 'sl' global variable with a 'g' - Rename 'j' -> 'k' and 'i' -> 'j' variables - Rename 'hex' variable into 'hextmp' - Fix unused parameter - Use a correct printf format for gsize - Use correct MAX macro - Use correct data casting - Do not use 'GTK_STOCK_*' anymore - Do not use 'gtk_tree_view_set_rules_hint' - Remove unused functions - Explicitly cast data type - Enable Werror --- CMakeLists.txt | 2 +- include/stlink.h | 14 ++++---- include/stlink/backend.h | 10 +++--- include/stlink/sg.h | 2 +- src/common.c | 62 ++++++++++++--------------------- src/flash_loader.c | 10 ++++-- src/gdbserver/gdb-remote.c | 2 +- src/gdbserver/gdb-server.c | 71 +++++++++++++++++++------------------- src/sg.c | 6 ++-- src/tools/flash.c | 22 ++++++------ src/tools/gui/stlink-gui.c | 41 +++++++++++++--------- src/tools/term.c | 54 ++++++++++++++--------------- src/usb.c | 63 ++++++++++++++++----------------- tests/usb.c | 2 +- 14 files changed, 179 insertions(+), 182 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index d61a0aee3..7846cb175 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -109,7 +109,7 @@ if(NOT MINGW) endif() if(gtk_FOUND) - include_directories(${gtk_INCLUDE_DIRS}) + include_directories(SYSTEM ${gtk_INCLUDE_DIRS}) set(GUI_SOURCES src/tools/gui/stlink-gui.c src/tools/gui/stlink-gui.h) diff --git a/include/stlink.h b/include/stlink.h index 72eebb70f..c93086219 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -67,7 +67,7 @@ extern "C" { STLINK_FLASH_TYPE_L4 }; - typedef struct { + struct stlink_reg { uint32_t r[16]; uint32_t s[32]; uint32_t xpsr; @@ -80,7 +80,7 @@ extern "C" { uint8_t basepri; uint8_t primask; uint32_t fpscr; - } reg; + }; typedef uint32_t stm32_addr_t; @@ -166,11 +166,11 @@ typedef struct flash_loader { int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); - int stlink_read_all_regs(stlink_t *sl, reg *regp); - int stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp); - int stlink_read_reg(stlink_t *sl, int r_idx, reg *regp); - int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp); - int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp); + int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); + int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); + int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); + int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); + int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, struct stlink_reg *regp); int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); int stlink_step(stlink_t *sl); int stlink_current_mode(stlink_t *sl); diff --git a/include/stlink/backend.h b/include/stlink/backend.h index 20b1c7132..d1b7648e4 100644 --- a/include/stlink/backend.h +++ b/include/stlink/backend.h @@ -18,11 +18,11 @@ int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*read_all_regs) (stlink_t *sl, reg * regp); - int (*read_reg) (stlink_t *sl, int r_idx, reg * regp); - int (*read_all_unsupported_regs) (stlink_t *sl, reg *regp); - int (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp); - int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp); + int (*read_all_regs) (stlink_t *sl, struct stlink_reg * regp); + int (*read_reg) (stlink_t *sl, int r_idx, struct stlink_reg * regp); + int (*read_all_unsupported_regs) (stlink_t *sl, struct stlink_reg *regp); + int (*read_unsupported_reg) (stlink_t *sl, int r_idx, struct stlink_reg *regp); + int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, struct stlink_reg *regp); int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); int (*step) (stlink_t * stl); int (*current_mode) (stlink_t * stl); diff --git a/include/stlink/sg.h b/include/stlink/sg.h index 56780f4c4..057f996a2 100644 --- a/include/stlink/sg.h +++ b/include/stlink/sg.h @@ -60,7 +60,7 @@ extern "C" { // obsolete, this was fed to the scsi tools unsigned char sense_buf[SENSE_BUF_LEN]; - reg reg; + struct stlink_reg reg; }; stlink_t* stlink_v1_open(const int verbose, int reset); diff --git a/src/common.c b/src/common.c index 2899f298d..90725c64b 100644 --- a/src/common.c +++ b/src/common.c @@ -170,18 +170,6 @@ static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { return rdp & 0xff; } -static inline uint32_t read_flash_wrpr(stlink_t *sl) { - uint32_t wrpr; - stlink_read_debug32(sl, FLASH_WRPR, &wrpr); - return wrpr; -} - -static inline uint32_t read_flash_obr(stlink_t *sl) { - uint32_t obr; - stlink_read_debug32(sl, FLASH_OBR, &obr); - return obr; -} - static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t reg, res; @@ -366,12 +354,6 @@ static void set_flash_cr_strt(stlink_t *sl) { stlink_write_debug32(sl, cr_reg, val); } -static inline uint32_t read_flash_acr(stlink_t *sl) { - uint32_t acr; - stlink_read_debug32(sl, FLASH_ACR, &acr); - return acr; -} - static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res, sr_reg; @@ -767,12 +749,12 @@ int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { return sl->backend->write_mem8(sl, addr, len); } -int stlink_read_all_regs(stlink_t *sl, reg *regp) { +int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("*** stlink_read_all_regs ***\n"); return sl->backend->read_all_regs(sl, regp); } -int stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp) { +int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("*** stlink_read_all_unsupported_regs ***\n"); return sl->backend->read_all_unsupported_regs(sl, regp); } @@ -782,7 +764,7 @@ int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { return sl->backend->write_reg(sl, reg, idx); } -int stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) { +int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { DLOG("*** stlink_read_reg\n"); DLOG(" (%d) ***\n", r_idx); @@ -794,7 +776,7 @@ int stlink_read_reg(stlink_t *sl, int r_idx, reg *regp) { return sl->backend->read_reg(sl, r_idx, regp); } -int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { +int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { int r_convert; DLOG("*** stlink_read_unsupported_reg\n"); @@ -815,7 +797,7 @@ int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { return sl->backend->read_unsupported_reg(sl, r_convert, regp); } -int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) { +int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct stlink_reg *regp) { int r_convert; DLOG("*** stlink_write_unsupported_reg\n"); @@ -1016,7 +998,7 @@ static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) { if (aligned_size & (4 - 1)) aligned_size = (cmp_size + 4) & ~(4 - 1); - stlink_read_mem32(sl, addr + off, aligned_size); + stlink_read_mem32(sl, addr + (uint32_t) off, aligned_size); if (memcmp(sl->q_buf, mf->base + off, cmp_size)) return -1; @@ -1075,12 +1057,12 @@ int stlink_fwrite_sram if (size & 3) size += 2; - stlink_write_mem32(sl, addr + off, size); + stlink_write_mem32(sl, addr + (uint32_t) off, size); } if(mf.len > len) { memcpy(sl->q_buf, mf.base + len, mf.len - len); - stlink_write_mem8(sl, addr + len, mf.len - len); + stlink_write_mem8(sl, addr + (uint32_t) len, mf.len - len); } /* check the file ha been written */ @@ -1134,7 +1116,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) if (aligned_size & (4 - 1)) aligned_size = (cmp_size + 4) & ~(4 - 1); - stlink_read_mem32(sl, addr + off, aligned_size); + stlink_read_mem32(sl, addr + (uint32_t) off, aligned_size); if (write(fd, sl->q_buf, sl->q_len) != (ssize_t) aligned_size) { fprintf(stderr, "write() != aligned_size\n"); @@ -1161,7 +1143,7 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, s } if (rem) { memcpy(sl->q_buf, buf+chunk, rem); - stlink_write_mem8(sl, (fl->buf_addr)+chunk, rem); + stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t) chunk, rem); } return 0; } @@ -1197,7 +1179,7 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); flashaddr -= STM32_FLASH_BASE; if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) { - uint32_t banksize = sl->flash_size / 2; + uint32_t banksize = (uint32_t) sl->flash_size / 2; if (flashaddr >= banksize) { flashaddr -= banksize; bker = 0x100; @@ -1226,7 +1208,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ else if(sector<5) sl->flash_pgsz=0x20000; else sl->flash_pgsz=0x40000; } - return (sl->flash_pgsz); + return (uint32_t) sl->flash_pgsz; } /** @@ -1385,10 +1367,10 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) int stlink_erase_flash_mass(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_L0) { /* erase each page */ - int i = 0, num_pages = sl->flash_size/sl->flash_pgsz; + int i = 0, num_pages = (int) sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { /* addr must be an addr inside the page */ - stm32_addr_t addr = sl->flash_base + i * sl->flash_pgsz; + stm32_addr_t addr = (stm32_addr_t) sl->flash_base + i * (stm32_addr_t) sl->flash_pgsz; if (stlink_erase_flash_page(sl, addr) == -1) { WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr); return -1; @@ -1460,7 +1442,7 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, if (aligned_size & (4 - 1)) aligned_size = (cmp_size + 4) & ~(4 - 1); - stlink_read_mem32(sl, address + off, aligned_size); + stlink_read_mem32(sl, address + (uint32_t) off, aligned_size); if (memcmp(sl->q_buf, data + off, cmp_size)) { ELOG("Verification of flash failed at offset: %zd\n", off); @@ -1563,9 +1545,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t stlink_core_id(sl); /* erase each page */ int page_count = 0; - for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + off)) { + for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + (uint32_t) off)) { /* addr must be an addr inside the page */ - if (stlink_erase_flash_page(sl, addr + off) == -1) { + if (stlink_erase_flash_page(sl, addr + (uint32_t) off) == -1) { ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); return -1; } @@ -1628,7 +1610,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t printf("size: %zu\n", size); - if (stlink_flash_loader_run(sl, &fl, addr + off, base + off, size) == -1) { + if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t) off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); return -1; } @@ -1701,7 +1683,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); - stlink_write_debug32(sl, addr + off, data); + stlink_write_debug32(sl, addr + (uint32_t) off, data); /* wait for sr.busy to be cleared */ do { @@ -1734,7 +1716,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t unlock_flash_if(sl); set_flash_cr_pg(sl); DLOG("Finished setting flash cr pg, running loader!\n"); - if (stlink_flash_loader_run(sl, &fl, addr + off, base + off, size) == -1) { + if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t) off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); return -1; } @@ -1779,7 +1761,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { else erased_pattern = 0xff; - index = mf.len; + index = (unsigned int) mf.len; for(num_empty = 0; num_empty != mf.len; ++num_empty) { if (mf.base[--index] != erased_pattern) { break; @@ -1790,7 +1772,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { if(num_empty != 0) { ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); } - err = stlink_write_flash(sl, addr, mf.base, num_empty == mf.len? mf.len : mf.len - num_empty, num_empty == mf.len); + err = stlink_write_flash(sl, addr, mf.base, (num_empty == mf.len) ? (uint32_t) mf.len : (uint32_t) mf.len - num_empty, num_empty == mf.len); /* set stack*/ stlink_read_debug32(sl, addr, &val); stlink_write_reg(sl, val, 13); diff --git a/src/flash_loader.c b/src/flash_loader.c index eaba6d3c5..6ea324485 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -1,5 +1,9 @@ #include "stlink.h" +#include +#include +#include + /* from openocd, contrib/loaders/flash/stm32.s */ static const uint8_t loader_code_stm32vl[] = { 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */ @@ -181,7 +185,7 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) } /* allocate a one page buffer in sram right after loader */ - fl->buf_addr = fl->loader_addr + size; + fl->buf_addr = fl->loader_addr + (uint32_t) size; ILOG("Successfully loaded flash loader in sram\n"); return 0; @@ -253,7 +257,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { - reg rr; + struct stlink_reg rr; int i = 0; size_t count = 0; @@ -282,7 +286,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe /* setup core */ stlink_write_reg(sl, fl->buf_addr, 0); /* source */ stlink_write_reg(sl, target, 1); /* target */ - stlink_write_reg(sl, count, 2); /* count */ + stlink_write_reg(sl, (uint32_t) count, 2); /* count */ stlink_write_reg(sl, 0, 3); /* flash bank 0 (input), only used on F0, but armless fopr others */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ diff --git a/src/gdbserver/gdb-remote.c b/src/gdbserver/gdb-remote.c index 2f61b93ac..73a157d34 100644 --- a/src/gdbserver/gdb-remote.c +++ b/src/gdbserver/gdb-remote.c @@ -18,7 +18,7 @@ static const char hex[] = "0123456789abcdef"; int gdb_send_packet(int fd, char* data) { - unsigned int data_length = strlen(data); + unsigned int data_length = (unsigned int) strlen(data); int length = data_length + 4; char* packet = malloc(length); /* '$' data (hex) '#' cksum (hex) */ diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index c50e5be32..5884b1e51 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -30,7 +30,7 @@ //Allways update the FLASH_PAGE before each use, by calling stlink_calculate_pagesize #define FLASH_PAGE (sl->flash_pgsz) -stlink_t *connected_stlink = NULL; +static stlink_t *connected_stlink = NULL; static const char hex[] = "0123456789abcdef"; @@ -485,7 +485,7 @@ struct code_hw_watchpoint { enum watchfun fun; }; -struct code_hw_watchpoint data_watches[DATA_WATCH_NUM]; +static struct code_hw_watchpoint data_watches[DATA_WATCH_NUM]; static void init_data_watchpoints(stlink_t *sl) { uint32_t data; @@ -569,8 +569,8 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) return -1; } -int code_break_num; -int code_lit_num; +static int code_break_num; +static int code_lit_num; #define CODE_BREAK_NUM_MAX 15 #define CODE_BREAK_LOW 0x01 #define CODE_BREAK_HIGH 0x02 @@ -580,7 +580,7 @@ struct code_hw_breakpoint { int type; }; -struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; +static struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; static void init_code_breakpoints(stlink_t *sl) { unsigned int val; @@ -753,7 +753,7 @@ static int flash_go(stlink_t *sl) { stlink_calculate_pagesize(sl, page); DLOG("flash_do: page %08x\n", page); - unsigned send = length > FLASH_PAGE ? FLASH_PAGE : length; + unsigned send = (length > FLASH_PAGE) ? (unsigned) FLASH_PAGE : length; if(stlink_write_flash(sl, page, fb->data + (page - fb->addr), send, 0) < 0) goto error; @@ -1001,7 +1001,7 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("recv: %s\n", packet); char* reply = NULL; - reg regp; + struct stlink_reg regp; switch(packet[0]) { case 'q': { @@ -1017,7 +1017,7 @@ int serve(stlink_t *sl, st_state_t *st) { params = separator + 1; } - unsigned queryNameLength = (separator - &packet[1]); + unsigned queryNameLength = (unsigned) (separator - &packet[1]); char* queryName = calloc(queryNameLength + 1, 1); strncpy(queryName, &packet[1], queryNameLength); @@ -1043,8 +1043,8 @@ int serve(stlink_t *sl, st_state_t *st) { __s_addr = strsep(&tok, ","); s_length = tok; - unsigned addr = strtoul(__s_addr, NULL, 16), - length = strtoul(s_length, NULL, 16); + unsigned addr = (unsigned) strtoul(__s_addr, NULL, 16), + length = (unsigned) strtoul(s_length, NULL, 16); DLOG("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", type, op, annex, addr, length); @@ -1058,7 +1058,7 @@ int serve(stlink_t *sl, st_state_t *st) { data = target_description_F4; if(data) { - unsigned data_length = strlen(data); + unsigned data_length = (unsigned) strlen(data); if(addr + length > data_length) length = data_length - addr; @@ -1072,7 +1072,8 @@ int serve(stlink_t *sl, st_state_t *st) { } } else if(!strncmp(queryName, "Rcmd,",4)) { // Rcmd uses the wrong separator - char *separator = strstr(packet, ","), *params = ""; + separator = strstr(packet, ","); + params = ""; if(separator == NULL) { separator = packet + strlen(packet); } else { @@ -1136,8 +1137,8 @@ int serve(stlink_t *sl, st_state_t *st) { __s_addr = strsep(&tok, ","); s_length = tok; - unsigned addr = strtoul(__s_addr, NULL, 16), - length = strtoul(s_length, NULL, 16); + unsigned addr = (unsigned) strtoul(__s_addr, NULL, 16), + length = (unsigned) strtoul(s_length, NULL, 16); DLOG("FlashErase: addr:%08x,len:%04x\n", addr, length); @@ -1154,8 +1155,8 @@ int serve(stlink_t *sl, st_state_t *st) { __s_addr = strsep(&tok, ":"); data = tok; - unsigned addr = strtoul(__s_addr, NULL, 16); - unsigned data_length = status - (data - packet); + unsigned addr = (unsigned) strtoul(__s_addr, NULL, 16); + unsigned data_length = status - (unsigned) (data - packet); // Length of decoded data cannot be more than // encoded, as escapes are removed. @@ -1205,7 +1206,7 @@ int serve(stlink_t *sl, st_state_t *st) { stlink_run(sl); while(1) { - int status = gdb_check_for_interrupt(client); + status = gdb_check_for_interrupt(client); if(status < 0) { ELOG("cannot check for int: %d\n", status); #ifdef __MINGW32__ @@ -1256,7 +1257,7 @@ int serve(stlink_t *sl, st_state_t *st) { break; case 'p': { - unsigned id = strtoul(&packet[1], NULL, 16); + unsigned id = (unsigned) strtoul(&packet[1], NULL, 16); unsigned myreg = 0xDEADDEAD; if(id < 16) { @@ -1303,8 +1304,8 @@ int serve(stlink_t *sl, st_state_t *st) { char* s_reg = &packet[1]; char* s_value = strstr(&packet[1], "=") + 1; - unsigned reg = strtoul(s_reg, NULL, 16); - unsigned value = strtoul(s_value, NULL, 16); + unsigned reg = (unsigned) strtoul(s_reg, NULL, 16); + unsigned value = (unsigned) strtoul(s_value, NULL, 16); if(reg < 16) { stlink_write_reg(sl, ntohl(value), reg); @@ -1341,7 +1342,7 @@ int serve(stlink_t *sl, st_state_t *st) { for(int i = 0; i < 16; i++) { char str[9] = {0}; strncpy(str, &packet[1 + i * 8], 8); - uint32_t reg = strtoul(str, NULL, 16); + uint32_t reg = (uint32_t) strtoul(str, NULL, 16); stlink_write_reg(sl, ntohl(reg), i); } @@ -1352,13 +1353,13 @@ int serve(stlink_t *sl, st_state_t *st) { char* s_start = &packet[1]; char* s_count = strstr(&packet[1], ",") + 1; - stm32_addr_t start = strtoul(s_start, NULL, 16); - unsigned count = strtoul(s_count, NULL, 16); + stm32_addr_t start = (stm32_addr_t) strtoul(s_start, NULL, 16); + unsigned count = (unsigned) strtoul(s_count, NULL, 16); unsigned adj_start = start % 4; unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; if (count_rnd > sl->flash_pgsz) - count_rnd = sl->flash_pgsz; + count_rnd = (unsigned) sl->flash_pgsz; if (count_rnd > 0x1800) count_rnd = 0x1800; if (count_rnd < count) @@ -1380,15 +1381,15 @@ int serve(stlink_t *sl, st_state_t *st) { char* s_count = strstr(&packet[1], ",") + 1; char* hexdata = strstr(packet, ":") + 1; - stm32_addr_t start = strtoul(s_start, NULL, 16); - unsigned count = strtoul(s_count, NULL, 16); + stm32_addr_t start = (stm32_addr_t) strtoul(s_start, NULL, 16); + unsigned count = (unsigned) strtoul(s_count, NULL, 16); if(start % 4) { unsigned align_count = 4 - start % 4; if (align_count > count) align_count = count; for(unsigned int i = 0; i < align_count; i ++) { - char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; - uint8_t byte = strtoul(hex, NULL, 16); + char hextmp[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; + uint8_t byte = strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; } stlink_write_mem8(sl, start, align_count); @@ -1402,8 +1403,8 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned aligned_count = count - count % 4; for(unsigned int i = 0; i < aligned_count; i ++) { - char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; - uint8_t byte = strtoul(hex, NULL, 16); + char hextmp[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; + uint8_t byte = strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; } stlink_write_mem32(sl, start, aligned_count); @@ -1415,8 +1416,8 @@ int serve(stlink_t *sl, st_state_t *st) { if(count) { for(unsigned int i = 0; i < count; i ++) { - char hex[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; - uint8_t byte = strtoul(hex, NULL, 16); + char hextmp[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; + uint8_t byte = strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; } stlink_write_mem8(sl, start, count); @@ -1428,8 +1429,8 @@ int serve(stlink_t *sl, st_state_t *st) { case 'Z': { char *endptr; - stm32_addr_t addr = strtoul(&packet[3], &endptr, 16); - stm32_addr_t len = strtoul(&endptr[1], NULL, 16); + stm32_addr_t addr = (stm32_addr_t) strtoul(&packet[3], &endptr, 16); + stm32_addr_t len = (stm32_addr_t) strtoul(&endptr[1], NULL, 16); switch (packet[1]) { case '1': @@ -1467,7 +1468,7 @@ int serve(stlink_t *sl, st_state_t *st) { } case 'z': { char *endptr; - stm32_addr_t addr = strtoul(&packet[3], &endptr, 16); + stm32_addr_t addr = (stm32_addr_t) strtoul(&packet[3], &endptr, 16); //stm32_addr_t len = strtoul(&endptr[1], NULL, 16); switch (packet[1]) { diff --git a/src/sg.c b/src/sg.c index 646091aac..22464bc1b 100644 --- a/src/sg.c +++ b/src/sg.c @@ -584,7 +584,7 @@ int _stlink_sg_force_debug(stlink_t *sl) { // Read all arm-core registers. -int _stlink_sg_read_all_regs(stlink_t *sl, reg *regp) { +int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -626,7 +626,7 @@ int _stlink_sg_read_all_regs(stlink_t *sl, reg *regp) { // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 -int _stlink_sg_read_reg(stlink_t *sl, int r_idx, reg *regp) { +int _stlink_sg_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_READREG; @@ -907,7 +907,7 @@ int _stlink_sg_exit_debug_mode(stlink_t *stl) // 4) the device driver is now ready for a switch to jtag/swd mode // TODO thinking, better error handling, wait until the kernel driver stops reseting the plugged-in device -stlink_backend_t _stlink_sg_backend = { +static stlink_backend_t _stlink_sg_backend = { _stlink_sg_close, _stlink_sg_exit_debug_mode, _stlink_sg_enter_swd_mode, diff --git a/src/tools/flash.c b/src/tools/flash.c index 7bebd82f9..50ad64092 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -14,7 +14,7 @@ #define DEBUG_LOG_LEVEL 100 #define STND_LOG_LEVEL 50 -stlink_t *connected_stlink = NULL; +static stlink_t *connected_stlink = NULL; static void cleanup(int signal __attribute__((unused))) { if (connected_stlink) { @@ -84,18 +84,19 @@ static int get_opts(struct opts* o, int ac, char** av) { ac--; av++; - int i=strlen(av[0]); - if(i%2 != 0){ + /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ + int j = (int) strlen(av[0]); + if(j%2 != 0){ puts("no valid hex value, length must be multiple of 2\n"); return -1; } - int j=0; - while(i>=0 && j<=13){ + int k=0; + while(j>=0 && k<=13){ char buffer[3]={0}; - memcpy(buffer,&av[0][i],2); - o->serial[12-j] = (char)strtol((const char*)buffer,NULL, 16); - j++; - i-=2; + memcpy(buffer,&av[0][j],2); + o->serial[12-k] = (char)strtol((const char*)buffer,NULL, 16); + k++; + j-=2; } ac--; av++; @@ -154,7 +155,8 @@ static int get_opts(struct opts* o, int ac, char** av) } o->filename = av[i + 1]; - o->addr = strtoul(av[i + 2], NULL, 16); + /** @todo This is a little evil as strtoul could return 0 and is of type unsigned long int */ + o->addr = (uint32_t) strtoul(av[i + 2], NULL, 16); return 0; } diff --git a/src/tools/gui/stlink-gui.c b/src/tools/gui/stlink-gui.c index 247373e9d..a56a2c34c 100644 --- a/src/tools/gui/stlink-gui.c +++ b/src/tools/gui/stlink-gui.c @@ -178,8 +178,8 @@ hexstr_to_guint32 (const gchar *str, GError **err) guint32 val; gchar *end_ptr; - val = strtoul (str, &end_ptr, 16); - if ((errno == ERANGE && val == LONG_MAX) || (errno != 0 && val == 0)) { + val = (guint32) strtoul (str, &end_ptr, 16); + if ((errno == ERANGE && val == UINT_MAX) || (errno != 0 && val == 0)) { g_set_error (err, g_quark_from_string ("hextou32"), 1, @@ -208,7 +208,7 @@ stlink_gui_update_mem_view (STlinkGUI *gui, struct mem_t *mem, GtkTreeView *view &iter, mem->base, mem->memory, - mem->size); + (gint) mem->size); gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); gtk_progress_bar_set_fraction (gui->progress.bar, 0); @@ -245,7 +245,7 @@ stlink_gui_populate_devmem_view (STlinkGUI *gui) guint n_read = MEM_READ_SIZE; if (off + MEM_READ_SIZE > gui->sl->flash_size) { - n_read = gui->sl->flash_size - off; + n_read = (guint) gui->sl->flash_size - off; /* align if needed */ if (n_read & 3) { @@ -316,11 +316,11 @@ stlink_gui_populate_filemem_view (STlinkGUI *gui) gui->file_mem.size = g_file_info_get_size (file_info); gui->file_mem.memory = g_malloc (gui->file_mem.size); - for (off = 0; off < gui->file_mem.size; off += MEM_READ_SIZE) { + for (off = 0; off < (gint) gui->file_mem.size; off += MEM_READ_SIZE) { guint n_read = MEM_READ_SIZE; - if (off + MEM_READ_SIZE > gui->file_mem.size) { - n_read = gui->file_mem.size - off; + if (off + MEM_READ_SIZE > (gint) gui->file_mem.size) { + n_read = (guint) gui->file_mem.size - off; } if (g_input_stream_read (G_INPUT_STREAM (input_stream), @@ -373,12 +373,11 @@ static void mem_jmp (GtkTreeView *view, do { guint32 addr; GValue value = G_VALUE_INIT; - GError *err = NULL; gtk_tree_model_get_value (model, &iter, 0, &value); if (G_VALUE_HOLDS_STRING (&value)) { - addr = hexstr_to_guint32 (g_value_get_string (&value), &err); - if (!err) { + addr = hexstr_to_guint32 (g_value_get_string (&value), err); + if (!*err) { if (addr == (jmp_addr & 0xFFFFFFF0)) { GtkTreeSelection *selection; GtkTreePath *path; @@ -407,6 +406,7 @@ devmem_jmp_cb (GtkWidget *widget, gpointer data) { STlinkGUI *gui; GError *err = NULL; + (void) widget; gui = STLINK_GUI (data); @@ -427,6 +427,7 @@ filemem_jmp_cb (GtkWidget *widget, gpointer data) { STlinkGUI *gui; GError *err = NULL; + (void) widget; gui = STLINK_GUI (data); @@ -448,7 +449,6 @@ static gchar * dev_format_chip_id (guint32 chip_id) { const struct stlink_chipid_params *params; - gint i; params = stlink_chipid_get_params(chip_id); if (!params) @@ -460,7 +460,7 @@ dev_format_chip_id (guint32 chip_id) static gchar * dev_format_mem_size (gsize flash_size) { - return g_strdup_printf ("%u kB", flash_size / 1024); + return g_strdup_printf ("%zu kB", flash_size / 1024); } @@ -522,6 +522,7 @@ connect_button_cb (GtkWidget *widget, gpointer data) { STlinkGUI *gui; gint i; + (void) widget; gui = STLINK_GUI (data); @@ -573,6 +574,7 @@ static void disconnect_button_cb (GtkWidget *widget, gpointer data) { STlinkGUI *gui; + (void) widget; gui = STLINK_GUI (data); @@ -595,8 +597,8 @@ stlink_gui_open_file (STlinkGUI *gui) dialog = gtk_file_chooser_dialog_new ("Open file", gui->window, GTK_FILE_CHOOSER_ACTION_OPEN, - GTK_STOCK_CANCEL, GTK_RESPONSE_CANCEL, - GTK_STOCK_OPEN, GTK_RESPONSE_ACCEPT, + "_Cancel", GTK_RESPONSE_CANCEL, + "_Open", GTK_RESPONSE_ACCEPT, NULL); if (gtk_dialog_run (GTK_DIALOG (dialog)) == GTK_RESPONSE_ACCEPT) { @@ -621,6 +623,7 @@ static void open_button_cb (GtkWidget *widget, gpointer data) { STlinkGUI *gui; + (void) widget; gui = STLINK_GUI (data); @@ -658,6 +661,7 @@ flash_button_cb (GtkWidget *widget, gpointer data) guint32 address; gint result; GError *err = NULL; + (void) widget; gui = STLINK_GUI (data); g_return_if_fail (gui->sl != NULL); @@ -712,6 +716,8 @@ notebook_switch_page_cb (GtkNotebook *notebook, gpointer data) { STlinkGUI *gui; + (void) notebook; + (void) widget; gui = STLINK_GUI (data); @@ -738,6 +744,9 @@ dnd_received_cb (GtkWidget *widget, STlinkGUI *gui = STLINK_GUI (data); GtkListStore *store; GtkTreeIter iter; + (void) widget; + (void) x; + (void) y; if (selection_data != NULL && gtk_selection_data_get_length (selection_data) > 0) { @@ -837,7 +846,6 @@ stlink_gui_build_ui (STlinkGUI *gui) { gui->devmem_treeview = GTK_TREE_VIEW (gtk_builder_get_object (builder, "devmem_treeview")); - gtk_tree_view_set_rules_hint (gui->devmem_treeview, TRUE); mem_view_init_headers (gui->devmem_treeview); devmem_store = gtk_list_store_new (5, G_TYPE_STRING, @@ -850,7 +858,6 @@ stlink_gui_build_ui (STlinkGUI *gui) { gui->filemem_treeview = GTK_TREE_VIEW (gtk_builder_get_object (builder, "filemem_treeview")); - gtk_tree_view_set_rules_hint (gui->filemem_treeview, TRUE); mem_view_init_headers (gui->filemem_treeview); filemem_store = gtk_list_store_new (5, G_TYPE_STRING, @@ -910,7 +917,7 @@ stlink_gui_build_ui (STlinkGUI *gui) { gui->infobar = GTK_INFO_BAR (gtk_builder_get_object (builder, "infobar")); - gtk_info_bar_add_button (gui->infobar, GTK_STOCK_OK, GTK_RESPONSE_OK); + gtk_info_bar_add_button (gui->infobar, "_OK", GTK_RESPONSE_OK); gui->infolabel = GTK_LABEL (gtk_label_new ("")); gtk_container_add (GTK_CONTAINER (gtk_info_bar_get_content_area (gui->infobar)), GTK_WIDGET (gui->infolabel)); diff --git a/src/tools/term.c b/src/tools/term.c index 9b46e2a4c..c07fcc70f 100644 --- a/src/tools/term.c +++ b/src/tools/term.c @@ -41,8 +41,8 @@ struct stlinky { | buf[2] << 16 \ | buf[3] << 24)) -static stlink_t* sl; -sigset_t sig_mask; +static stlink_t* gsl; +static sigset_t sig_mask; struct stlinky { stlink_t *sl; @@ -53,11 +53,11 @@ struct stlinky { void nonblock(int state); static void cleanup(int signal __attribute__((unused))) { - if (sl) { + if (gsl) { /* Switch back to mass storage mode before closing. */ - stlink_run(sl); - stlink_exit_debug_mode(sl); - stlink_close(sl); + stlink_run(gsl); + stlink_exit_debug_mode(gsl); + stlink_close(gsl); } printf("\n"); @@ -158,7 +158,7 @@ size_t stlinky_rx(struct stlinky *st, char* buffer) stlinky_read_buff(st, st->off + RX_BUFF_OFFSET + tail, head - tail, buffer); size_read += head - tail; } else if(head < tail){ - stlinky_read_buff(st, st->off + RX_BUFF_OFFSET + tail, st->bufsize - tail, buffer); + stlinky_read_buff(st, st->off + RX_BUFF_OFFSET + tail, (uint32_t) st->bufsize - tail, buffer); size_read += st->bufsize - tail; stlinky_read_buff(st, st->off + RX_BUFF_OFFSET, head, buffer + size_read); @@ -193,17 +193,17 @@ size_t stlinky_tx(struct stlinky *st, char* buffer, size_t siz) return 0; //copy in data (take care of possible split) - int first_chunk = head + siz >= st->bufsize ? st->bufsize - head : siz; - int second_chunk = siz - first_chunk; + int first_chunk = (head + siz >= st->bufsize) ? (int) st->bufsize - (int) head : (int) siz; + int second_chunk = (int) siz - first_chunk; //copy data - stlinky_write_buf(st, st->off + TX_BUFF_OFFSET(st->bufsize) + head, first_chunk, buffer); + stlinky_write_buf(st, st->off + (uint32_t) TX_BUFF_OFFSET(st->bufsize) + head, first_chunk, buffer); if (second_chunk > 0) - stlinky_write_buf(st, st->off + TX_BUFF_OFFSET(st->bufsize), + stlinky_write_buf(st, st->off + (uint32_t) TX_BUFF_OFFSET(st->bufsize), second_chunk, buffer + first_chunk); //increment head pointer - head = (head + siz) % st->bufsize; + head = (head + siz) % (uint32_t) st->bufsize; memcpy(st->sl->q_buf, &head, sizeof(head)); stlink_write_mem32(st->sl, st->off + TX_Q_OFFSET + sizeof(tail), sizeof(head)); @@ -252,37 +252,37 @@ int main(int ac, char** av) { sig_init(); - sl = stlink_open_usb(10, 1, NULL); - if (sl != NULL) { + gsl = stlink_open_usb(10, 1, NULL); + if (gsl != NULL) { printf("ST-Linky proof-of-concept terminal :: Created by Necromant for lulz\n"); - stlink_version(sl); - stlink_enter_swd_mode(sl); - printf("chip id: %#x\n", sl->chip_id); - printf("core_id: %#x\n", sl->core_id); + stlink_version(gsl); + stlink_enter_swd_mode(gsl); + printf("chip id: %#x\n", gsl->chip_id); + printf("core_id: %#x\n", gsl->core_id); cortex_m3_cpuid_t cpuid; - stlink_cpu_id(sl, &cpuid); + stlink_cpu_id(gsl, &cpuid); printf("cpuid:impl_id = %0#x, variant = %#x\n", cpuid.implementer_id, cpuid.variant); printf("cpuid:part = %#x, rev = %#x\n", cpuid.part, cpuid.revision); - stlink_reset(sl); - stlink_force_debug(sl); - stlink_run(sl); - stlink_status(sl); + stlink_reset(gsl); + stlink_force_debug(gsl); + stlink_run(gsl); + stlink_status(gsl); /* wait for device to boot */ /* TODO: Make timeout adjustable via command line */ sleep(1); if(ac == 1){ - st = stlinky_detect(sl); + st = stlinky_detect(gsl); }else if(ac == 2){ st = malloc(sizeof(struct stlinky)); - st->sl = sl; + st->sl = gsl; st->off = (int)strtol(av[1], NULL, 16); printf("using stlinky at 0x%x\n", st->off); - stlink_read_mem32(sl, st->off + 4, 4); - st->bufsize = READ_UINT32_LE(sl->q_buf); + stlink_read_mem32(gsl, st->off + 4, 4); + st->bufsize = READ_UINT32_LE(gsl->q_buf); printf("stlinky buffer size 0x%zu \n", st->bufsize); }else{ cleanup(0); diff --git a/src/usb.c b/src/usb.c index 3a72035ab..1a41d6544 100644 --- a/src/usb.c +++ b/src/usb.c @@ -36,7 +36,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, if (libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, - txsize, + (int) txsize, &res, 3000)) return -1; @@ -44,7 +44,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, if (rxsize != 0) { if (libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, - rxsize, + (int) rxsize, &res, 3000)) return -1; @@ -69,7 +69,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, static inline int send_only (struct stlink_libusb* handle, int terminate, unsigned char* txbuf, size_t txsize) { - return send_recv(handle, terminate, txbuf, txsize, NULL, 0); + return (int) send_recv(handle, terminate, txbuf, txsize, NULL, 0); } @@ -107,7 +107,7 @@ int _stlink_usb_version(stlink_t *sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return size; + return (int) size; } return 0; @@ -155,7 +155,7 @@ int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return size; + return (int) size; } *data = read_uint32(rdata, 4); return 0; @@ -176,7 +176,7 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return size; + return (int) size; } return 0; @@ -279,9 +279,9 @@ int _stlink_usb_status(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return size; + return (int) size; } - sl->q_len = (size_t) size; + sl->q_len = (int) size; return 0; } @@ -299,7 +299,7 @@ int _stlink_usb_force_debug(stlink_t *sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return size; + return (int) size; } return 0; @@ -319,7 +319,7 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { printf("[!] send_recv\n"); - return size; + return (int) size; } return 0; @@ -337,7 +337,7 @@ int _stlink_usb_exit_dfu_mode(stlink_t* sl) { size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { printf("[!] send_recv\n"); - return size; + return (int) size; } return 0; @@ -361,7 +361,7 @@ int _stlink_usb_reset(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return size; + return (int) size; } return 0; @@ -383,7 +383,7 @@ int _stlink_usb_jtag_reset(stlink_t * sl, int value) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return size; + return (int) size; } return 0; @@ -404,7 +404,7 @@ int _stlink_usb_step(stlink_t* sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return size; + return (int) size; } return 0; @@ -428,7 +428,7 @@ int _stlink_usb_run(stlink_t* sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return size; + return (int) size; } return 0; @@ -446,7 +446,7 @@ int _stlink_usb_exit_debug_mode(stlink_t *sl) { size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { printf("[!] send_only\n"); - return size; + return (int) size; } return 0; @@ -467,16 +467,16 @@ int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, len); if (size == -1) { printf("[!] send_recv\n"); - return size; + return (int) size; } - sl->q_len = (size_t) size; + sl->q_len = (int) size; stlink_print_data(sl); return 0; } -int _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) { +int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; unsigned char* const data = sl->q_buf; @@ -489,9 +489,9 @@ int _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return size; + return (int) size; } - sl->q_len = (size_t) size; + sl->q_len = (int) size; stlink_print_data(sl); for(i=0; i<16; i++) regp->r[i]= read_uint32(sl->q_buf, i*4); @@ -512,7 +512,7 @@ int _stlink_usb_read_all_regs(stlink_t *sl, reg *regp) { return 0; } -int _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { +int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -527,9 +527,9 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return size; + return (int) size; } - sl->q_len = (size_t) size; + sl->q_len = (int) size; stlink_print_data(sl); r = read_uint32(sl->q_buf, 0); DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); @@ -558,7 +558,7 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, reg *regp) { } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ -int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { +int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { uint32_t r; int ret; @@ -596,7 +596,7 @@ int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp) { return 0; } -int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, reg *regp) { +int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { int ret; ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); @@ -617,7 +617,7 @@ int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, reg *regp) { } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ -int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) { +int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct stlink_reg *regp) { int ret; if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ @@ -675,15 +675,15 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv\n"); - return size; + return (int) size; } - sl->q_len = (size_t) size; +sl->q_len = (int) size; stlink_print_data(sl); return 0; } -stlink_backend_t _stlink_usb_backend = { +static stlink_backend_t _stlink_usb_backend = { _stlink_usb_close, _stlink_usb_exit_debug_mode, _stlink_usb_enter_swd_mode, @@ -737,7 +737,8 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 } libusb_device **list; - int cnt = libusb_get_device_list(slu->libusb_ctx, &list); + /** @todo We should use ssize_t and use it as a counter if > 0. As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) */ + int cnt = (int) libusb_get_device_list(slu->libusb_ctx, &list); struct libusb_device_descriptor desc; int devBus =0; int devAddr=0; diff --git a/tests/usb.c b/tests/usb.c index 1ae6442c1..06fd73429 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -7,7 +7,7 @@ int main(int ac, char** av) (void)av; stlink_t* sl; - reg regs; + struct stlink_reg regs; sl = stlink_open_usb(10, 1, NULL); if (sl != NULL) { From 3d438166ce02689867fe599ace62be9607a69660 Mon Sep 17 00:00:00 2001 From: Greg Alexander Date: Sat, 4 Jun 2016 15:50:33 -0400 Subject: [PATCH 0438/1435] Don't read the target voltage on startup, because it crashes STM32F100. --- src/gdbserver/gdb-server.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index c50e5be32..55e0763ac 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -159,8 +159,6 @@ int parse_options(int argc, char** argv, st_state_t *st) { int main(int argc, char** argv) { - int32_t voltage; - stlink_t *sl = NULL; st_state_t state; @@ -193,11 +191,6 @@ int main(int argc, char** argv) { ILOG("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); - voltage = stlink_target_voltage(sl); - if (voltage != -1) { - ILOG("Target voltage is %d mV.\n", voltage); - } - sl->verbose=0; current_memory_map = make_memory_map(sl); From 8924c51d9eb140c35158cd7938b5cc9c2b7128af Mon Sep 17 00:00:00 2001 From: Greg Alexander Date: Sun, 5 Jun 2016 08:31:10 -0400 Subject: [PATCH 0439/1435] Provide more detailed error messages when send_recv() fails. --- src/usb.c | 67 ++++++++++++++++++++++++++++++++++--------------------- 1 file changed, 41 insertions(+), 26 deletions(-) diff --git a/src/usb.c b/src/usb.c index 1a41d6544..856185f3e 100644 --- a/src/usb.c +++ b/src/usb.c @@ -33,32 +33,47 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, unsigned char* rxbuf, size_t rxsize) { /* note: txbuf and rxbuf can point to the same area */ int res = 0; + int t; - if (libusb_bulk_transfer(handle->usb_handle, handle->ep_req, + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int) txsize, &res, - 3000)) + 3000); + if (t) { + printf("[!] send_recv send request failed: %s\n", libusb_error_name(t)); return -1; + } else if ((size_t)res != txsize) { + printf("[!] send_recv send request wrote %d bytes (instead of %d).\n", + res, txsize); + } if (rxsize != 0) { - if (libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int) rxsize, &res, - 3000)) + 3000); + if (t) { + printf("[!] send_recv read reply failed: %s\n", + libusb_error_name(t)); return -1; + } } if ((handle->protocoll == 1) && terminate) { /* Read the SG reply */ unsigned char sg_buf[13]; - if (libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, - 3000)) + 3000); + if (t) { + printf("[!] send_recv read storage failed: %s\n", + libusb_error_name(t)); return -1; + } /* The STLink doesn't seem to evaluate the sequence number */ handle->sg_transfer_idx++; } @@ -106,7 +121,7 @@ int _stlink_usb_version(stlink_t *sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_GET_VERSION\n"); return (int) size; } @@ -127,10 +142,10 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_GET_TARGET_VOLTAGE\n"); return -1; } else if (size != 8) { - printf("[!] wrong length\n"); + printf("[!] wrong length STLINK_GET_TARGET_VOLTAGE\n"); return -1; } @@ -154,7 +169,7 @@ int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { write_uint32(&cmd[i], addr); size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_JTAG_READDEBUG_32BIT\n"); return (int) size; } *data = read_uint32(rdata, 4); @@ -175,7 +190,7 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { write_uint32(&cmd[i + 4], data); size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_JTAG_WRITEDEBUG_32BIT\n"); return (int) size; } @@ -238,7 +253,7 @@ int _stlink_usb_current_mode(stlink_t * sl) { cmd[i++] = STLINK_GET_CURRENT_MODE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_GET_CURRENT_MODE\n"); return -1; } return sl->q_buf[0]; @@ -257,7 +272,7 @@ int _stlink_usb_core_id(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_DEBUG_READCOREID\n"); return -1; } @@ -278,7 +293,7 @@ int _stlink_usb_status(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_DEBUG_GETSTATUS\n"); return (int) size; } sl->q_len = (int) size; @@ -298,7 +313,7 @@ int _stlink_usb_force_debug(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_FORCEDEBUG; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_DEBUG_FORCEDEBUG\n"); return (int) size; } @@ -318,7 +333,7 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_DEBUG_ENTER\n"); return (int) size; } @@ -336,7 +351,7 @@ int _stlink_usb_exit_dfu_mode(stlink_t* sl) { size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_DFU_EXIT\n"); return (int) size; } @@ -360,7 +375,7 @@ int _stlink_usb_reset(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_DEBUG_RESETSYS\n"); return (int) size; } @@ -382,7 +397,7 @@ int _stlink_usb_jtag_reset(stlink_t * sl, int value) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_JTAG_DRIVE_NRST\n"); return (int) size; } @@ -403,7 +418,7 @@ int _stlink_usb_step(stlink_t* sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_DEBUG_STEPCORE\n"); return (int) size; } @@ -427,7 +442,7 @@ int _stlink_usb_run(stlink_t* sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_DEBUG_RUNCORE\n"); return (int) size; } @@ -445,7 +460,7 @@ int _stlink_usb_exit_debug_mode(stlink_t *sl) { size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { - printf("[!] send_only\n"); + printf("[!] send_only STLINK_DEBUG_EXIT\n"); return (int) size; } @@ -466,7 +481,7 @@ int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_DEBUG_READMEM_32BIT\n"); return (int) size; } @@ -488,7 +503,7 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { cmd[i++] = STLINK_DEBUG_READALLREGS; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_DEBUG_READALLREGS\n"); return (int) size; } sl->q_len = (int) size; @@ -526,7 +541,7 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { cmd[i++] = (uint8_t) r_idx; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_DEBUG_READREG\n"); return (int) size; } sl->q_len = (int) size; @@ -674,7 +689,7 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { write_uint32(&cmd[i], reg); size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { - printf("[!] send_recv\n"); + printf("[!] send_recv STLINK_DEBUG_WRITEREG\n"); return (int) size; } sl->q_len = (int) size; From ac43cfdfef8f3dc8d95cd31548b4786646f81c4c Mon Sep 17 00:00:00 2001 From: andrey Date: Tue, 7 Jun 2016 09:21:14 -0700 Subject: [PATCH 0440/1435] Do a JTAG reset prior to reading CPU information. This is needed when a CPU is in deep sleep mode, and its debug interface is switched off. --- src/usb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/usb.c b/src/usb.c index 856185f3e..6ec93bd56 100644 --- a/src/usb.c +++ b/src/usb.c @@ -877,6 +877,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 } if (reset) { + stlink_jtag_reset(sl, 2); stlink_reset(sl); usleep(10000); } From d67d39f237c6449a3967193ad6e286eb2cf148ad Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 10 Jun 2016 14:44:30 +0200 Subject: [PATCH 0441/1435] Update README Add notice about broken stlink firmware V2.J16.S0 on STM32 L1 Discovery board --- README | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/README b/README index fc2231854..efffa2cda 100644 --- a/README +++ b/README @@ -251,6 +251,79 @@ of the flash: Issue(s): [#356](https://github.com/texane/stlink/issues/356) +### Stlink serial corrupts after one probe + +`lsusb -v` before `st-info --probe` with STM32 L1 Discovery board. With stlink firmware `V2.J16.S0`: + +``` +Bus 001 Device 004: ID 0483:3748 STMicroelectronics ST-LINK/V2 +Device Descriptor: + bLength 18 + bDescriptorType 1 + bcdUSB 2.00 + bDeviceClass 0 (Defined at Interface level) + bDeviceSubClass 0 + bDeviceProtocol 0 + bMaxPacketSize0 64 + idVendor 0x0483 STMicroelectronics + idProduct 0x3748 ST-LINK/V2 + bcdDevice 1.00 + iManufacturer 1 STMicroelectronics + iProduct 2 STM32 STLink + iSerial 3 Pÿk^FPgRUB1^C Date: Fri, 10 Jun 2016 15:12:23 +0200 Subject: [PATCH 0442/1435] src/usb.c: Dont crash when libusb_open fails, check return value --- src/usb.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/usb.c b/src/usb.c index 856185f3e..c75476d6a 100644 --- a/src/usb.c +++ b/src/usb.c @@ -790,7 +790,10 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) || (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO)) { struct libusb_device_handle *handle; - libusb_open(list[cnt], &handle); + ret = libusb_open(list[cnt], &handle); + if (ret) + continue; + sl->serial_size = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)sl->serial, sizeof(sl->serial)); libusb_close(handle); From 3daa3f15cc5f3fe6f33f4bc33b3b61dbcc0c6ce7 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 18 Jun 2016 09:41:32 +0200 Subject: [PATCH 0443/1435] Initial support for STM32F7x7x, for nucleo-144, STM32F767ZI issue #433 --- include/stlink/chipid.h | 1 + src/chipid.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index a5012e38f..72094a733 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -52,6 +52,7 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_L0_CAT5 = 0x447, STLINK_CHIPID_STM32_F0_CAN = 0x448, STLINK_CHIPID_STM32_F7 = 0x449, + STLINK_CHIPID_STM32_F7XXXX = 0x451, STLINK_CHIPID_STM32_F410 = 0x458 }; diff --git a/src/chipid.c b/src/chipid.c index c3f1a9278..546e2384e 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -2,6 +2,17 @@ #include "stlink/chipid.h" static const struct stlink_chipid_params devices[] = { + { + //RM0410 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F7XXXX, + .description = "F76xxx device", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff0f442, // section 45.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x5C000, // "SRAM" byte size in hex from + .bootrom_base = 0x00200000, //! "System memory" starting address from + .bootrom_size = 0xEDC0 //! @todo "System memory" byte size in hex from + }, { //RM0385 and DS10916 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F7, From 1c04e4f54664836b8446d75302458331d3c45477 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 18 Jun 2016 09:46:54 +0200 Subject: [PATCH 0444/1435] TravisCI: Disable clang 3.8 builds (disabled apt repo), remove autotools --- .travis.yml | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/.travis.yml b/.travis.yml index 0fae3aaeb..3ae4a6333 100644 --- a/.travis.yml +++ b/.travis.yml @@ -3,31 +3,17 @@ language: c addons: apt: sources: - - llvm-toolchain-precise-3.8 - ubuntu-toolchain-r-test packages: - - clang-3.8 - g++-5 - gcc-5 script: - ./.travis.sh matrix: include: - - os: linux - compiler: gcc - env: "BUILD_SYSTEM=autotools" - - os: linux - compiler: clang - env: "BUILD_SYSTEM=autotools" - os: linux compiler: gcc-5 env: "BUILD_SYSTEM=cmake" - - os: linux - compiler: clang-3.8 - env: "BUILD_SYSTEM=cmake" - os: osx compiler: clang env: "BUILD_SYSTEM=cmake" - - os: osx - compiler: clang - env: "BUILD_SYSTEM=autotools" From 2563f43965a06e0fc2c7a09cd908478656076429 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 18 Jun 2016 09:49:39 +0200 Subject: [PATCH 0445/1435] TravisCI: Revert clang cmake build for linux --- .travis.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.travis.yml b/.travis.yml index 3ae4a6333..55a23fb12 100644 --- a/.travis.yml +++ b/.travis.yml @@ -7,10 +7,14 @@ addons: packages: - g++-5 - gcc-5 + - clang script: - ./.travis.sh matrix: include: + - os: linux + compiler: clang-3.8 + env: "BUILD_SYSTEM=cmake" - os: linux compiler: gcc-5 env: "BUILD_SYSTEM=cmake" From dfeb5a4e6f253a586543e7f72753ab96391dce2c Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 18 Jun 2016 19:40:27 +0200 Subject: [PATCH 0446/1435] flash_loader.c: Add STLINK_CHIPID_STM32_F7XXXX --- src/flash_loader.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/flash_loader.c b/src/flash_loader.c index 6ea324485..2e237c406 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -231,7 +231,8 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32f4_lv; loader_size = sizeof(loader_code_stm32f4_lv); } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7){ + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || + sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { loader_code = loader_code_stm32f7; loader_size = sizeof(loader_code_stm32f7); } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || sl->chip_id == STLINK_CHIPID_STM32_F0_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F09X) { From 5a06869797992f3892c276a7163dedb679a8a5ea Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 18 Jun 2016 19:53:31 +0200 Subject: [PATCH 0447/1435] Add flash loader core id and chipid for STM32F767ZI with nucleo-144 --- include/stlink.h | 1 + src/flash_loader.c | 7 ++++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index c93086219..d1bf4815c 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -51,6 +51,7 @@ extern "C" { /* cortex core ids */ // TODO clean this up... #define STM32VL_CORE_ID 0x1ba01477 +#define STM32F7_CORE_ID 0x5ba02477 // Constant STM32 memory map figures #define STM32_FLASH_BASE 0x08000000 diff --git a/src/flash_loader.c b/src/flash_loader.c index 2e237c406..eee961808 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -202,7 +202,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); - } else if (sl->core_id == STM32VL_CORE_ID + } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F3 || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH @@ -231,7 +231,8 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32f4_lv; loader_size = sizeof(loader_code_stm32f4_lv); } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || + } else if (sl->core_id == STM32F7_CORE_ID || + sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { loader_code = loader_code_stm32f7; loader_size = sizeof(loader_code_stm32f7); @@ -242,7 +243,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { - ELOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); + ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", sl->core_id, sl->chip_id); return -1; } From 72fbf6a2c828ff9dc01e4fe0d46e5edf3b0fb13a Mon Sep 17 00:00:00 2001 From: texane Date: Mon, 20 Jun 2016 20:36:51 +0200 Subject: [PATCH 0448/1435] Fix zu missing on Windows toolchains. Use unsigned int casts instead. --- src/common.c | 13 +++++++------ src/flash_loader.c | 2 +- src/tools/gui/stlink-gui.c | 2 +- src/tools/info.c | 8 +++++--- src/tools/term.c | 4 ++-- src/usb.c | 4 ++-- 6 files changed, 18 insertions(+), 15 deletions(-) diff --git a/src/common.c b/src/common.c index 90725c64b..011bc08ac 100644 --- a/src/common.c +++ b/src/common.c @@ -611,9 +611,9 @@ int stlink_load_device_params(stlink_t *sl) { ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); // TODO make note of variable page size here..... - ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n", + ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %u bytes\n", sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, - sl->flash_pgsz); + (unsigned int)sl->flash_pgsz); return 0; } @@ -1445,7 +1445,7 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, stlink_read_mem32(sl, address + (uint32_t) off, aligned_size); if (memcmp(sl->q_buf, data + off, cmp_size)) { - ELOG("Verification of flash failed at offset: %zd\n", off); + ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); return -1; } } @@ -1608,7 +1608,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t for(off = 0; off < len;) { size_t size = len - off > 0x8000 ? 0x8000 : len - off; - printf("size: %zu\n", size); + printf("size: %u\n", (unsigned int)size); if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t) off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); @@ -1677,8 +1677,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t fprintf(stdout, "\r"); if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { - fprintf(stdout, "\r%3zd/%3zd pages written", - off/sl->flash_pgsz, len/sl->flash_pgsz); + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off/sl->flash_pgsz), + (unsigned int)(len/sl->flash_pgsz)); fflush(stdout); } diff --git a/src/flash_loader.c b/src/flash_loader.c index eee961808..2939af94f 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -263,7 +263,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe int i = 0; size_t count = 0; - DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); + DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); // FIXME This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { // IMPOSSIBLE! diff --git a/src/tools/gui/stlink-gui.c b/src/tools/gui/stlink-gui.c index a56a2c34c..535f9bb33 100644 --- a/src/tools/gui/stlink-gui.c +++ b/src/tools/gui/stlink-gui.c @@ -460,7 +460,7 @@ dev_format_chip_id (guint32 chip_id) static gchar * dev_format_mem_size (gsize flash_size) { - return g_strdup_printf ("%zu kB", flash_size / 1024); + return g_strdup_printf ("%u kB", (unsigned int)(flash_size / 1024)); } diff --git a/src/tools/info.c b/src/tools/info.c index 0d0b82393..d3a315150 100644 --- a/src/tools/info.c +++ b/src/tools/info.c @@ -49,8 +49,10 @@ static void stlink_print_info(stlink_t *sl) printf("openocd: "); stlink_print_serial(sl, true); - printf(" flash: %zu (pagesize: %zu)\n", sl->flash_size, sl->flash_pgsz); - printf(" sram: %zu\n", sl->sram_size); + printf(" flash: %u (pagesize: %u)\n", + (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); + + printf(" sram: %u\n", (unsigned int)sl->sram_size); printf(" chipid: 0x%.4x\n", sl->chip_id); params = stlink_chipid_get_params(sl->chip_id); @@ -65,7 +67,7 @@ static void stlink_probe(void) size = stlink_probe_usb(&stdevs); - printf("Found %zu stlink programmers\n", size); + printf("Found %u stlink programmers\n", (unsigned int)size); for (size_t n = 0; n < size; n++) stlink_print_info(stdevs[n]); diff --git a/src/tools/term.c b/src/tools/term.c index c07fcc70f..3f3517f9e 100644 --- a/src/tools/term.c +++ b/src/tools/term.c @@ -103,7 +103,7 @@ struct stlinky* stlinky_detect(stlink_t* sl) st->off = sram_base + off; stlink_read_mem32(sl, st->off + 4, 4); st->bufsize = READ_UINT32_LE(sl->q_buf); - printf("stlinky buffer size 0x%zu \n", st->bufsize); + printf("stlinky buffer size 0x%u \n", (unsigned int)st->bufsize); multiple++; } } @@ -283,7 +283,7 @@ int main(int ac, char** av) { printf("using stlinky at 0x%x\n", st->off); stlink_read_mem32(gsl, st->off + 4, 4); st->bufsize = READ_UINT32_LE(gsl->q_buf); - printf("stlinky buffer size 0x%zu \n", st->bufsize); + printf("stlinky buffer size 0x%u \n", (unsigned int)st->bufsize); }else{ cleanup(0); } diff --git a/src/usb.c b/src/usb.c index c75476d6a..6dcd7c913 100644 --- a/src/usb.c +++ b/src/usb.c @@ -44,8 +44,8 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, printf("[!] send_recv send request failed: %s\n", libusb_error_name(t)); return -1; } else if ((size_t)res != txsize) { - printf("[!] send_recv send request wrote %d bytes (instead of %d).\n", - res, txsize); + printf("[!] send_recv send request wrote %u bytes (instead of %u).\n", + (unsigned int)res, (unsigned int)txsize); } if (rxsize != 0) { From 471e7bbbd1efe221215c221ee2a54d831b63b81a Mon Sep 17 00:00:00 2001 From: Dave Flogeras Date: Tue, 21 Jun 2016 19:29:07 -0300 Subject: [PATCH 0449/1435] Fix a regression introduced in 71535104. Since STLINK V1 cannot read voltage, and attempting to do so breaks the USB communications, this patch will revert the behaviour to just blindly doing 32-bit writes on these programmers. --- src/common.c | 26 ++++++++++++++++---------- src/flash_loader.c | 23 +++++++++++++++-------- 2 files changed, 31 insertions(+), 18 deletions(-) diff --git a/src/common.c b/src/common.c index 011bc08ac..d804a4d7f 100644 --- a/src/common.c +++ b/src/common.c @@ -1578,17 +1578,23 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t /* TODO: Check that Voltage range is 2.7 - 3.6 V */ if (sl->chip_id != STLINK_CHIPID_STM32_L4) { - /* set parallelisim to 32 bit*/ - int voltage = stlink_target_voltage(sl); - if (voltage == -1) { - printf("Failed to read Target voltage\n"); - return voltage; - } else if (voltage > 2700) { - printf("enabling 32-bit flash writes\n"); + if( sl->version.stlink_v == 1 ) { + printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes on F4 devices\n"); write_flash_cr_psiz(sl, 2); - } else { - printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage); - write_flash_cr_psiz(sl, 0); + } + else { + /* set parallelisim to 32 bit*/ + int voltage = stlink_target_voltage(sl); + if (voltage == -1) { + printf("Failed to read Target voltage\n"); + return voltage; + } else if (voltage > 2700) { + printf("enabling 32-bit flash writes\n"); + write_flash_cr_psiz(sl, 2); + } else { + printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage); + write_flash_cr_psiz(sl, 0); + } } } else { /* L4 does not have a byte-write mode */ diff --git a/src/flash_loader.c b/src/flash_loader.c index 2939af94f..e05f35ae5 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -220,16 +220,23 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_F411RE || sl->chip_id == STLINK_CHIPID_STM32_F446 ) { - int voltage = stlink_target_voltage(sl); - if (voltage == -1) { - printf("Failed to read Target voltage\n"); - return voltage; - } else if (voltage > 2700) { + if( sl->version.stlink_v == 1 ) { + printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes on F4 devices\n"); loader_code = loader_code_stm32f4; loader_size = sizeof(loader_code_stm32f4); - } else { - loader_code = loader_code_stm32f4_lv; - loader_size = sizeof(loader_code_stm32f4_lv); + } + else { + int voltage = stlink_target_voltage(sl); + if (voltage == -1) { + printf("Failed to read Target voltage\n"); + return voltage; + } else if (voltage > 2700) { + loader_code = loader_code_stm32f4; + loader_size = sizeof(loader_code_stm32f4); + } else { + loader_code = loader_code_stm32f4_lv; + loader_size = sizeof(loader_code_stm32f4_lv); + } } } else if (sl->core_id == STM32F7_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F7 || From c61f160d691fa52acd8347f7ab4ead064693aa71 Mon Sep 17 00:00:00 2001 From: Chris Date: Sat, 25 Jun 2016 13:29:39 +0800 Subject: [PATCH 0450/1435] Fix an erase error in stm32f030 device. I run into flashing error with stm32f030. With some debugging I find out that the mass erase bit was dropped when flash programming bit already set on FLASH_CR. This cause erase and write error with my stm32f030 board. Mass erase never need the programming bit. Turn off the programming bit make stlink flash stm32f030 successfully. --- src/common.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 90725c64b..9dc1c0f27 100644 --- a/src/common.c +++ b/src/common.c @@ -298,20 +298,29 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { } static void set_flash_cr_mer(stlink_t *sl) { - uint32_t val, cr_reg, cr_mer; + uint32_t val, cr_reg, cr_mer, cr_pg; if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); + cr_pg = 1 << STM32L4_FLASH_CR_PG; } else { cr_reg = FLASH_CR; cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; } stlink_read_debug32(sl, cr_reg, &val); + if (val & cr_pg) { + /* STM32F030 will drop MER bit if PG was set */ + val &= ~cr_pg; + stlink_write_debug32(sl, cr_reg, val); + } + val |= cr_mer; stlink_write_debug32(sl, cr_reg, val); } From 3de5a547270a5280e346bed1ac09f8a0badf871f Mon Sep 17 00:00:00 2001 From: Jerome Lambourg Date: Tue, 19 Jul 2016 10:46:40 +0200 Subject: [PATCH 0451/1435] Fix gdb and flash support for the STM32F769I-Disco board. --- src/common.c | 8 ++++---- src/gdbserver/gdb-server.c | 14 +++++++------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/common.c b/src/common.c index 2ebe1e624..ebc1f8e51 100644 --- a/src/common.c +++ b/src/common.c @@ -1163,7 +1163,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ if (flashaddr >= 0x100000) { offset = 12; flashaddr -= 0x100000; - } + } if (flashaddr<0x4000) return (offset + 0); else if(flashaddr<0x8000) return(offset + 1); else if(flashaddr<0xc000) return(offset + 2); @@ -1211,7 +1211,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ else if(sector<5) sl->flash_pgsz=0x10000; else sl->flash_pgsz=0x20000; } - else if (sl->chip_id == STLINK_CHIPID_STM32_F7) { + else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { uint32_t sector=calculate_F7_sectornum(flashaddr); if (sector<4) sl->flash_pgsz=0x8000; else if(sector<5) sl->flash_pgsz=0x20000; @@ -1243,7 +1243,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7) { + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { // calculate the actual page from the address uint32_t sector=calculate_F7_sectornum(flashaddr); @@ -1255,7 +1255,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) uint32_t sector=calculate_F4_sectornum(flashaddr); fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); - + //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices... if (sector >= 12) sector += 4; diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 702098d45..efe97e406 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -429,7 +429,7 @@ char* make_memory_map(stlink_t *sl) { if(sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F446) { strcpy(map, memory_map_template_F4); - } else if(sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F7) { + } else if(sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->core_id==STM32F7_CORE_ID) { strcpy(map, memory_map_template_F7); } else if(sl->chip_id==STLINK_CHIPID_STM32_F4_HD) { strcpy(map, memory_map_template_F4_HD); @@ -601,7 +601,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { return -1; } - if (sl->chip_id==STLINK_CHIPID_STM32_F7) { + if (sl->core_id==STM32F7_CORE_ID) { fpb_addr = addr; } else { fpb_addr = addr & ~0x3; @@ -625,7 +625,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { brk->addr = fpb_addr; - if (sl->chip_id==STLINK_CHIPID_STM32_F7) { + if (sl->core_id==STM32F7_CORE_ID) { if(set) brk->type = type; else brk->type = 0; @@ -751,7 +751,7 @@ static int flash_go(stlink_t *sl) { send, 0) < 0) goto error; length -= send; - + } } @@ -835,7 +835,7 @@ static void init_cache (stlink_t *sl) { int i; /* Assume only F7 has a cache. */ - if(sl->chip_id!=STLINK_CHIPID_STM32_F7) + if(sl->core_id!=STM32F7_CORE_ID) return; stlink_read_debug32(sl, CLIDR, &clidr); @@ -916,7 +916,7 @@ static void cache_sync(stlink_t *sl) { unsigned ccr; - if(sl->chip_id!=STLINK_CHIPID_STM32_F7) + if(sl->core_id!=STM32F7_CORE_ID) return; if (!cache_modified) return; @@ -1019,7 +1019,7 @@ int serve(stlink_t *sl, st_state_t *st) { if(!strcmp(queryName, "Supported")) { if(sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F4_HD - || sl->chip_id==STLINK_CHIPID_STM32_F7) { + || sl->core_id==STM32F7_CORE_ID) { reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); } else { From cb7533394a29f19a5b3df4feca79ecbbf38296db Mon Sep 17 00:00:00 2001 From: toniokroeger Date: Fri, 22 Jul 2016 18:53:15 +0200 Subject: [PATCH 0452/1435] Update udev path in README --- README | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README b/README index efffa2cda..7d6f8ef3b 100644 --- a/README +++ b/README @@ -137,7 +137,7 @@ for GDB. ## Setting up udev rules For convenience, you may install udev rules file, 49-stlinkv*.rules, located -in the root of repository. You will need to copy it to /etc/udev/rules.d, +in etc/udev/rules.d (from root of repository). You will need to copy it to /etc/udev/rules.d, and then either reboot or execute ``` From 57cf59a86930b37d0d408fc58b6f13b44c8a431a Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Wed, 3 Aug 2016 11:04:20 +0200 Subject: [PATCH 0453/1435] cmake: Add proper detection of sys/mman.h. Fixes #450 Signed-off-by: Jerry Jacobs --- CMakeLists.txt | 6 ++++++ include/stlink/mmap.h | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 7846cb175..ca46074da 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,6 +2,7 @@ project(stlink C) cmake_minimum_required(VERSION 2.8.7) include(CheckCCompilerFlag) +include(CheckIncludeFile) find_package(PkgConfig) set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") @@ -47,6 +48,11 @@ elseif() add_cflag_if_supported("-O2") endif() +CHECK_INCLUDE_FILE(sys/mman.h STLINK_HAVE_SYS_MMAN_H) +if (STLINK_HAVE_SYS_MMAN_H) + add_definitions(-DSTLINK_HAVE_SYS_MMAN_H) +endif() + set(STLINK_HEADERS include/stlink.h include/stlink/usb.h diff --git a/include/stlink/mmap.h b/include/stlink/mmap.h index 71de819fa..ab94fb7d4 100644 --- a/include/stlink/mmap.h +++ b/include/stlink/mmap.h @@ -1,7 +1,7 @@ #ifndef STLINK_MMAP_H #define STLINK_MMAP_H -#ifdef HAVE_SYS_MMAN_H +#ifdef STLINK_HAVE_SYS_MMAN_H #include #else From 9aac78d18496f3c14dda52434142c9edd08c7098 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 18 Jun 2016 16:19:09 +0200 Subject: [PATCH 0454/1435] Deprecate autotools --- .appveyor.yml | 20 ++ .travis.sh | 21 +-- .travis.yml | 14 +- .version | 1 + ACKNOWLEDGMENTS | 2 - AUTHORS | 19 -- CMakeLists.txt | 92 ++++++++- COPYING | 27 --- ChangeLog | 9 + INSTALL.mingw | 44 ----- Makefile.am | 59 ------ NEWS | 0 README | 335 --------------------------------- README.md | 253 ++++++++++++++++++++++++- TODO.md | 11 -- autogen.sh | 2 - cmake/modules/Find7Zip.cmake | 5 + cmake/modules/FindLibUSB.cmake | 61 ++++-- configure.ac | 59 ------ doc/build_mingw.md | 23 +++ doc/release.md | 10 + scripts/appveyor-mingw.sh | 21 +++ scripts/mingw64-build.bat | 12 ++ src/common.c | 2 +- src/gdbserver/gdb-remote.c | 4 +- src/gdbserver/gdb-server.c | 4 +- src/tools/gui/Makefile.am | 30 --- src/usb.c | 2 +- 28 files changed, 505 insertions(+), 637 deletions(-) create mode 100644 .appveyor.yml create mode 100644 .version delete mode 100644 ACKNOWLEDGMENTS delete mode 100644 AUTHORS delete mode 100644 COPYING delete mode 100644 INSTALL.mingw delete mode 100644 Makefile.am delete mode 100644 NEWS delete mode 100644 README mode change 120000 => 100644 README.md delete mode 100644 TODO.md delete mode 100755 autogen.sh create mode 100644 cmake/modules/Find7Zip.cmake delete mode 100644 configure.ac create mode 100644 doc/build_mingw.md create mode 100644 doc/release.md create mode 100644 scripts/appveyor-mingw.sh create mode 100644 scripts/mingw64-build.bat delete mode 100644 src/tools/gui/Makefile.am diff --git a/.appveyor.yml b/.appveyor.yml new file mode 100644 index 000000000..9e53a07bc --- /dev/null +++ b/.appveyor.yml @@ -0,0 +1,20 @@ +version: '{build}' +environment: + matrix: + - GENERATOR: "MSYS Makefiles" + ARCH: i686 # this is for 32-bit MinGW-w64 + - GENERATOR: "MSYS Makefiles" + ARCH: 64 +cache: + - i686-4.9.2-release-win32-sjlj-rt_v3-rev1.7z + - x86_64-4.9.2-release-win32-seh-rt_v3-rev1.7z +build_script: +- ps: | + mkdir build + cd build + if ($env:GENERATOR -ne "MSYS Makefiles") { + cmake .. -G"$env:GENERATOR" + cmake --build . --config Debug + } +- cmd: | + if "%GENERATOR%"=="MSYS Makefiles" (C:\MinGW\msys\1.0\bin\sh --login /c/projects/stlink/scripts/appveyor-mingw.sh) diff --git a/.travis.sh b/.travis.sh index 9e28d3ca1..9fa519dad 100755 --- a/.travis.sh +++ b/.travis.sh @@ -5,24 +5,15 @@ ls -1 /usr/bin/clang* ls -1 /usr/bin/scan-build* echo "----" -if [ "$TRAVIS_OS_NAME" != "osx" ]; then +if [ "$TRAVIS_OS_NAME" == "linux" ]; then sudo apt-get update -qq || true sudo apt-get install -qq -y --no-install-recommends libusb-1.0.0-dev libgtk-3-dev else brew install libusb fi -if [ "$BUILD_SYSTEM" == "cmake" ]; then - mkdir build - cd build - cmake .. - make -else - ./autogen.sh - if [ "$TRAVIS_OS_NAME" == "osx" ]; then - ./configure - else - ./configure --with-gtk-gui - fi - make -fi +echo "=== Building Debug" +mkdir -p build/Debug && cd build/Debug && cmake -DCMAKE_BUILD_TYPE=Debug ../../ && make && make package && cd - + +echo "=== Building Release" +mkdir -p build/Release && cd build/Release && cmake -DCMAKE_BUILD_TYPE=Release ../../ && make && make package && cd - diff --git a/.travis.yml b/.travis.yml index 55a23fb12..543c0edec 100644 --- a/.travis.yml +++ b/.travis.yml @@ -3,21 +3,25 @@ language: c addons: apt: sources: +# - llvm-toolchain-precise-3.8 - ubuntu-toolchain-r-test packages: + - clang +# - clang-3.8 - g++-5 - gcc-5 - - clang script: - ./.travis.sh matrix: include: - os: linux - compiler: clang-3.8 - env: "BUILD_SYSTEM=cmake" + compiler: clang +# - os: linux +# compiler: clang-3.8 - os: linux compiler: gcc-5 - env: "BUILD_SYSTEM=cmake" + compiler: gcc-5 +# - os: linux +# compiler: clang-3.8 - os: osx compiler: clang - env: "BUILD_SYSTEM=cmake" diff --git a/.version b/.version new file mode 100644 index 000000000..d72f26267 --- /dev/null +++ b/.version @@ -0,0 +1 @@ +2.0.0-dev diff --git a/ACKNOWLEDGMENTS b/ACKNOWLEDGMENTS deleted file mode 100644 index acd89e3ea..000000000 --- a/ACKNOWLEDGMENTS +++ /dev/null @@ -1,2 +0,0 @@ -The development team wants to acknowledge the following people: -- STMicroelectronics discovery kit team for their low cost boards and for their help in development process. \ No newline at end of file diff --git a/AUTHORS b/AUTHORS deleted file mode 100644 index aae9e2963..000000000 --- a/AUTHORS +++ /dev/null @@ -1,19 +0,0 @@ -m@capitanio.org -spen@spen-soft.co.uk -texane@gmail.com -whitequark@whitequark.org -grestm@galexander.org -karlp@tweak.net.au -h0rr0rrdrag@gmail.com -mstempin@com1.fr -bon@elektron.ikp.physik.tu-darmstadt.de -nelsonjm@macpod.neta -ned@bike-nomad.com -csamuelson@swingpal.com -bravikov@gmail.com -jnosky - codegrinder69@hotmail.com -marpe@mimuw.edu.pl -marco.cassinerio@gmail.com -jserv@0xlab.org -michael@pratt.im -jerry.jacobs@xor-gate.org diff --git a/CMakeLists.txt b/CMakeLists.txt index ca46074da..cf18e0228 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,14 +1,58 @@ -project(stlink C) cmake_minimum_required(VERSION 2.8.7) +project(stlink C) include(CheckCCompilerFlag) include(CheckIncludeFile) find_package(PkgConfig) +if (POLICY CMP0042) + # Newer cmake on MacOS should use @rpath + cmake_policy (SET CMP0042 NEW) +endif () + set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") +# Determine package version. +find_package (Git QUIET) +if (DEFINED ENV{TRAVIS_TAG} AND NOT "$ENV{TRAVIS_TAG}" STREQUAL "") + set (STLINK_PACKAGE_VERSION "$ENV{TRAVIS_TAG}") +elseif (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") + # Working off a git repo, using git versioning + + # Check if HEAD is pointing to a tag + execute_process ( + COMMAND "${GIT_EXECUTABLE}" describe --always + WORKING_DIRECTORY "${PROJECT_SOURCE_DIR}" + OUTPUT_VARIABLE STLINK_PACKAGE_VERSION + OUTPUT_STRIP_TRAILING_WHITESPACE) + + # If the sources have been changed locally, add -dirty to the version. + execute_process ( + COMMAND "${GIT_EXECUTABLE}" diff --quiet + WORKING_DIRECTORY "${PROJECT_SOURCE_DIR}" + RESULT_VARIABLE res) + + if (res EQUAL 1) + set (STLINK_PACKAGE_VERSION "${STLINK_PACKAGE_VERSION}-dirty") + endif() +elseif (EXISTS ${PROJECT_SOURCE_DIR}/.version) + # If git is not available (e.g. when building from source package) + # we can extract the package version from .version file. + file (STRINGS .version STLINK_PACKAGE_VERSION) +else () + set (STLINK_PACKAGE_VERSION "Unknown") +endif() + +if(WIN32) + find_package(7Zip REQUIRED) + message(STATUS "7Zip Location: " ${ZIP_LOCATION}) +endif() + find_package(LibUSB REQUIRED) -pkg_check_modules(gtk gtk+-3.0) +if (NOT APPLE AND NOT WIN32) + find_package(PkgConfig) + pkg_check_modules(gtk gtk+-3.0) +endif () function(add_cflag_if_supported flag) string(REPLACE "-" "_" flagclean ${flag}) @@ -38,12 +82,19 @@ add_cflag_if_supported("-Wshorten-64-to-32") add_cflag_if_supported("-Wimplicit-function-declaration") add_cflag_if_supported("-Wredundant-decls") add_cflag_if_supported("-Wundef") -add_cflag_if_supported("-fPIC") +if (NOT MSYS OR MINGW) + add_cflag_if_supported("-fPIC") +endif () + +if (CMAKE_BUILD_TYPE STREQUAL "") + set (CMAKE_BUILD_TYPE "Debug") +endif () if(${CMAKE_BUILD_TYPE} MATCHES "Debug") include(CTest) add_cflag_if_supported("-ggdb") add_cflag_if_supported("-O0") + #set (STLINK_PACKAGE_VERSION "${STLINK_PACKAGE_VERSION}-debug") elseif() add_cflag_if_supported("-O2") endif() @@ -53,6 +104,8 @@ if (STLINK_HAVE_SYS_MMAN_H) add_definitions(-DSTLINK_HAVE_SYS_MMAN_H) endif() +message("Building ${PROJECT_NAME} ${STLINK_PACKAGE_VERSION}") + set(STLINK_HEADERS include/stlink.h include/stlink/usb.h @@ -72,6 +125,10 @@ set(STLINK_SOURCE src/flash_loader.c ) +if (WIN32 OR MSYS OR MINGW) + set (STLINK_SOURCE "${STLINK_SOURCE};src/mmap.c;src/mingw/mingw.c") # TODO +endif () + include_directories(${LIBUSB_INCLUDE_DIR}) include_directories(include) include_directories(src/mingw) @@ -86,7 +143,7 @@ if (APPLE) find_library(CoreFoundation CoreFoundation) find_library(IOKit IOKit) target_link_libraries(${PROJECT_NAME} ${CoreFoundation} ${IOKit} ${ObjC}) -endif() +endif () add_executable(st-flash src/tools/flash.c) target_link_libraries(st-flash ${PROJECT_NAME}) @@ -98,7 +155,11 @@ add_executable(st-util src/gdbserver/gdb-remote.c src/gdbserver/gdb-remote.h src/gdbserver/gdb-server.c src/gdbserver/gdb-server.h) -target_link_libraries(st-util ${PROJECT_NAME}) +if (WIN32 OR MSYS OR MINGW) + target_link_libraries(st-util ${PROJECT_NAME} wsock32 ws2_32) +else () + target_link_libraries(st-util ${PROJECT_NAME}) +endif () install(TARGETS ${PROJECT_NAME} st-flash st-util st-info RUNTIME DESTINATION bin @@ -114,20 +175,22 @@ if(NOT MINGW) RUNTIME DESTINATION bin) endif() -if(gtk_FOUND) +if (NOT APPLE AND gtk_FOUND) include_directories(SYSTEM ${gtk_INCLUDE_DIRS}) set(GUI_SOURCES src/tools/gui/stlink-gui.c src/tools/gui/stlink-gui.h) + # TODO REMOVE whole stlink-gui-local target, fixup auto-search of ui file in implementation add_executable(stlink-gui-local ${GUI_SOURCES}) set_target_properties(stlink-gui-local PROPERTIES COMPILE_FLAGS -DSTLINK_UI_DIR=\\"${CMAKE_CURRENT_SOURCE_DIR}/gui\\") target_link_libraries(stlink-gui-local stlink ${gtk_LDFLAGS}) - set(INSTALLED_UI_DIR ${CMAKE_INSTALL_PREFIX}/share) + set(INSTALLED_UI_DIR share/stlink) add_executable(stlink-gui ${GUI_SOURCES}) + # TODO REMOVE, fixup auto-search of ui file in implementation set_target_properties(stlink-gui PROPERTIES - COMPILE_FLAGS -DSTLINK_UI_DIR=\\"${INSTALLED_UI_DIR}\\") + COMPILE_FLAGS -DSTLINK_UI_DIR=\\"${CMAKE_INSTALL_PREFIX}/${INSTALLED_UI_DIR}\\") target_link_libraries(stlink-gui stlink ${gtk_LDFLAGS}) install(TARGETS stlink-gui @@ -137,3 +200,16 @@ if(gtk_FOUND) endif() add_subdirectory(tests) + +set (CPACK_PACKAGE_NAME ${PROJECT_NAME}) +set (CPACK_PACKAGE_VERSION ${STLINK_PACKAGE_VERSION}) +set (CPACK_SOURCE_GENERATOR "TBZ2;ZIP") +set (CPACK_SOURCE_IGNORE_FILES "/build/;/.git/;~$;${CPACK_SOURCE_IGNORE_FILES}") +set (CPACK_SOURCE_PACKAGE_FILE_NAME "${PROJECT_NAME}-${STLINK_PACKAGE_VERSION}") +if (APPLE) + set(CPACK_GENERATOR "ZIP") + file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/osx") + set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/osx") +endif () +add_custom_target(dist COMMAND ${CMAKE_MAKE_PROGRAM} package_source) +include (CPack) diff --git a/COPYING b/COPYING deleted file mode 100644 index 37b124eba..000000000 --- a/COPYING +++ /dev/null @@ -1,27 +0,0 @@ -Copyright (c) 2011 The "Capt'ns Missing Link" Authors. All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met: - - * Redistributions of source code must retain the above copyright -notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above -copyright notice, this list of conditions and the following disclaimer -in the documentation and/or other materials provided with the -distribution. - * Neither the name of Martin Capitanio nor the names of its -contributors may be used to endorse or promote products derived from -this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/ChangeLog b/ChangeLog index 00d82ee9f..355ba08ab 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,6 +1,15 @@ Stlink ChangeLog ================ +v2.0.0 +====== + +Ongoing development + +Major changes: + +* Deprecation of autotools (autoconf, automake) + v1.2.0 ====== diff --git a/INSTALL.mingw b/INSTALL.mingw deleted file mode 100644 index c8df0fd70..000000000 --- a/INSTALL.mingw +++ /dev/null @@ -1,44 +0,0 @@ -from dandev37: - -Here's a step by step from a clean install to successfully setup MinGW and build -libusb-1.0 and stlink for MS Windows. Hopefully this helps someone. - -1. Install MinGW and MSYS to C:\MinGW with the graphical installer from -http://sourceforge.net/projects/mingw/files/Installer/mingw-get-setup.exe/download -and add these packages: -mingw32-base -mingw-developer-toolkit - -2. Add C:\MinGW\bin to your path. -Note: a user reports she had to use c:\MinGW\msys\1.0\bin - -3. Create the C:\MinGW\msys\1.0\etc\fstab file to mount C:\MinGW as /mingw as per -http://www.mingw.org/wiki/MSYS: - -#Win32_Path Mount_Point -c:/mingw /mingw - -4. Download these three glib, pkg-config, pkg-config-dev archives and extract -contents to C:\MinGW -http://win32builder.gnome.org/packages/3.6/glib_2.34.3-1_win32.zip -http://win32builder.gnome.org/packages/3.6/pkg-config_0.28-1_win32.zip -http://win32builder.gnome.org/packages/3.6/pkg-config-dev_0.28-1_win32.zip - -5. Download latest libusb-1.0 source from -https://github.com/libusb/libusb (newer repo, includes USB 3.0 hub support) -OR the old git://git.libusb.org/libusb.git (original repo, NO USB 3.0 support) -and build (prefix as per http://www.mingw.org/wiki/MSYS) - -./autogen.sh -./configure --prefix=/mingw -make -make install - -6. Repeat for stlink source from https://github.com/texane/stlink - -./autogen.sh -./configure --prefix=/mingw -make -make install - -7. Enjoy the fruits of the stlink developers. diff --git a/Makefile.am b/Makefile.am deleted file mode 100644 index 79ce10c22..000000000 --- a/Makefile.am +++ /dev/null @@ -1,59 +0,0 @@ -# Makefile.am -- Process this file with automake to produce Makefile.in - -SUBDIRS = . $(STLINK_HAS_GUI) - -AUTOMAKE_OPTIONS = subdir-objects - -if MINGW -bin_PROGRAMS = st-flash st-util st-info -else -bin_PROGRAMS = st-flash st-util st-term st-info -endif - -noinst_LIBRARIES = libstlink.a - -st_flash_SOURCES = src/tools/flash.c -st_term_SOURCES = src/tools/term.c -st_info_SOURCES = src/tools/info.c -st_util_SOURCES = src/gdbserver/gdb-remote.c src/gdbserver/gdb-remote.h src/gdbserver/gdb-server.c src/mingw/mingw.c src/mingw/mingw.h - -CFILES = \ - src/chipid.c \ - src/common.c \ - src/usb.c \ - src/sg.c \ - src/logging.c \ - src/flash_loader.c - -if !MINGW -CFILES += src/tools/term.c -endif - -HFILES = \ - include/stlink.h \ - include/stlink/chipid.h \ - include/stlink/usb.h \ - include/stlink/flash_loader.h \ - include/stlink/commands.h \ - include/stlink/sg.h \ - include/stlink/logging.h \ - include/stlink/mmap.h - -libstlink_a_SOURCES = $(CFILES) $(HFILES) - -libstlink_a_LIBADD = $(LIBOBJS) -libstlink_a_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/include - -st_flash_LDADD = libstlink.a -st_flash_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/include -I$(top_srcdir)/src/mingw - -st_util_LDADD = libstlink.a -st_util_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/include -I$(top_srcdir)/src/mingw - -st_term_LDADD = libstlink.a -st_term_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/include -I$(top_srcdir)/src/mingw - -st_info_LDADD = libstlink.a -st_info_CPPFLAGS = -std=gnu99 -Wall -Wextra -O2 -I$(top_srcdir)/include -I$(top_srcdir)/src/mingw - -EXTRA_DIST = autogen.sh diff --git a/NEWS b/NEWS deleted file mode 100644 index e69de29bb..000000000 diff --git a/README b/README deleted file mode 100644 index 7d6f8ef3b..000000000 --- a/README +++ /dev/null @@ -1,335 +0,0 @@ -Open source version of the STMicroelectronics Stlink Tools -========================================================== - -[![Build Status](https://travis-ci.org/texane/stlink.svg?branch=master)](https://travis-ci.org/texane/stlink) - -## HOWTO - -First, you have to know there are several boards supported by the software. -Those boards use a chip to translate from USB to JTAG commands. The chip is -called stlink and there are 2 versions: - -* STLINKv1, present on STM32VL discovery kits, -* STLINKv2, present on STM32L discovery and later kits. - -Two different transport layers are used: - -* STLINKv1 uses SCSI passthru commands over USB -* STLINKv2 uses raw USB commands. - -## Common requirements - -* Debian based distros (debian, ubuntu) - * `build-essential` - -* `pkg-config` -* `intltool` -* `cmake` or (`autoconf` && `automake` && `autogen`) -* `libusb-1.0` (plus development headers for building, on debian based distros `libusb-1.0.0-dev` package) -* (optional) for `stlink-gui` we need libgtk-3-dev - -## For STLINKv1 - -The STLINKv1's SCSI emulation is very broken, so the best thing to do -is tell your operating system to completely ignore it. - -Options (do one of these before you plug it in) - -* `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` -* or 1. `echo "options usb-storage quirks=483:3744:i" >> /etc/modprobe.conf` -* 2. `modprobe -r usb-storage && modprobe usb-storage` -* or 1. `cp stlink_v1.modprobe.conf /etc/modprobe.d` -* 2. `modprobe -r usb-storage && modprobe usb-storage` - -## For STLINKv2 - -You're ready to go :) - -## Build from sources - -### Autotools - -This project was converted to Autotools by a well meaning individual. The -following steps will build the project for you. - -``` -$ ./autogen.sh -$ ./configure --with-gtk-gui -$ make -``` - -### CMake - -``` -$ mkdir build && cd build -$ cmake -DCMAKE_BUILD_TYPE=Debug .. -$ make -``` - -## Using the gdb server - -To run the gdb server: (you do not need sudo if you have set up -permissions correctly) - -``` -$ make && [sudo] ./st-util - -There are a few options: - -./st-util - usage: - - -h, --help Print this help - -vXX, --verbose=XX Specify a specific verbosity level (0..99) - -v, --verbose Specify generally verbose logging - -s X, --stlink_version=X - Choose what version of stlink to use, (defaults to 2) - -1, --stlinkv1 Force stlink version 1 - -p 4242, --listen_port=1234 - Set the gdb server listen port. (default port: 4242) - -m, --multi - Set gdb server to extended mode. - st-util will continue listening for connections after disconnect. - -n, --no-reset - Do not reset board on connection. -``` - -The STLINKv2 device to use can be specified in the environment -variable STLINK_DEVICE on the format `:`. - -Then, in your project directory, someting like this... -(remember, you need to run an _ARM_ gdb, not an x86 gdb) - -``` -$ arm-none-eabi-gdb fancyblink.elf -... -(gdb) tar extended-remote :4242 -... -(gdb) load -Loading section .text, size 0x458 lma 0x8000000 -Loading section .data, size 0x8 lma 0x8000458 -Start address 0x80001c1, load size 1120 -Transfer rate: 1 KB/sec, 560 bytes/write. -(gdb) -... -(gdb) continue -``` - -Have fun! - -## Resetting the chip from GDB - -You may reset the chip using GDB if you want. You'll need to use `target -extended-remote' command like in this session: - -``` -(gdb) target extended-remote localhost:4242 -Remote debugging using localhost:4242 -0x080007a8 in _startup () -(gdb) kill -Kill the program being debugged? (y or n) y -(gdb) run -Starting program: /home/whitequark/ST/apps/bally/firmware.elf -``` - -Remember that you can shorten the commands. `tar ext :4242' is good enough -for GDB. - -## Setting up udev rules - -For convenience, you may install udev rules file, 49-stlinkv*.rules, located -in etc/udev/rules.d (from root of repository). You will need to copy it to /etc/udev/rules.d, -and then either reboot or execute - -``` -$ udevadm control --reload-rules -$ udevadm trigger -``` - -Udev will now create a /dev/stlinkv2_XX or /dev/stlinkv1_XX file, with the appropriate permissions. -This is currently all the device is for, (only one stlink of each version is supported at -any time presently) - -## Running programs from SRAM - -You can run your firmware directly from SRAM if you want to. Just link -it at 0x20000000 and do - -``` -(gdb) load firmware.elf -``` - -It will be loaded, and pc will be adjusted to point to start of the -code, if it is linked correctly (i.e. ELF has correct entry point). - -## Writing to flash - -The GDB stub ships with a correct memory map, including the flash area. -If you would link your executable to 0x08000000 and then do -(gdb) load firmware.elf -then it would be written to the memory. - -## FAQ - -Q: My breakpoints do not work at all or only work once. - -A: Optimizations can cause severe instruction reordering. For example, -if you are doing something like `REG = 0x100;' in a loop, the code may -be split into two parts: loading 0x100 into some intermediate register -and moving that value to REG. When you set up a breakpoint, GDB will -hook to the first instruction, which may be called only once if there are -enough unused registers. In my experience, -O3 causes that frequently. - -Q: At some point I use GDB command `next', and it hangs. - -A: Sometimes when you will try to use GDB `next' command to skip a loop, -it will use a rather inefficient single-stepping way of doing that. -Set up a breakpoint manually in that case and do `continue'. - -Q: Load command does not work in GDB. - -A: Some people report XML/EXPAT is not enabled by default when compiling -GDB. Memory map parsing thus fail. Use --enable-expat. - -## Currently known working combinations of programmer and target - -STLink v1 (as found on the 32VL Discovery board) - -Known working targets: - -* STM32F100xx (Medium Density VL) -* STM32F103 (according to jpa- on ##stm32) - -No information: - -* everything else! - -STLink v2 (as found on the 32L and F4 Discovery boards), known working targets: - -* STM32F030F4P6 (custom board) -* STM32F0Discovery (STM32F0 Discovery board) -* STM32F100xx (Medium Density VL, as on the 32VL Discovery board) -* STM32L1xx (STM32L Discovery board) -* STM32F103VC, STM32F107RC, STM32L151RB, STM32F205RE and STM32F405RE on custom boards - from [UweBonnes/wiki_fuer_alex](https://github.com/UweBonnes/wiki_fuer_alex/tree/master/layout) -* STM32F103VET6 (HY-STM32 board) -* STM32F105RCT6 (DecaWave EVB1000 board) -* STM32F303xx (STM32F3 Discovery board) -* STM32F407xx (STM32F4 Discovery board) -* STM32F429I-DISCO (STM32F4 Discovery board with LCD) -* STM32F439VIT6 (discovery board reseated CPU) -* STM32L052K8T6 (custom board) -* STM32L151CB (custom board) -* STM32L152RB (STM32L-Discovery board, custom board) -* STM32F051R8T6 (STM320518-EVAL board) - -STLink v2-1 (as found on the Nucleo boards), known working targets: - -* STM32F401xx (STM32 Nucleo-F401RE board) -* STM32F030R8T6 (STM32 Nucleo-F030R8 board) -* STM32F072RBT6 (STM32 Nucleo-F072RB board) -* STM32F103RB (STM32 Nucleo-F103RB board) -* STM32F303RET6 (STM32 Nucleo-F303RE board) -* STM32F334R8 (STM32 Nucleo-F334R8 board) -* STM32F411RET6 (STM32 Nucleo-F411RE board) -* STM32F756NGHx (STMF7 evaluation board) -* STM32L053R8 (STM32 Nucleo-L053R8 board) - -Please report any and all known working combinations so I can update this! - -## Known bugs - -### Sometimes flashing only works after a mass erase - -There is seen a problem sometimes where a flash loader run error occurs and is resolved after mass-erase -of the flash: - -``` -2015-12-09T22:01:57 INFO src/stlink-common.c: Successfully loaded flash loader in sram -2015-12-09T22:02:18 ERROR src/stlink-common.c: flash loader run error -2015-12-09T22:02:18 ERROR src/stlink-common.c: run_flash_loader(0x8000000) failed! == -1 -``` - -Issue(s): [#356](https://github.com/texane/stlink/issues/356) - -### Stlink serial corrupts after one probe - -`lsusb -v` before `st-info --probe` with STM32 L1 Discovery board. With stlink firmware `V2.J16.S0`: - -``` -Bus 001 Device 004: ID 0483:3748 STMicroelectronics ST-LINK/V2 -Device Descriptor: - bLength 18 - bDescriptorType 1 - bcdUSB 2.00 - bDeviceClass 0 (Defined at Interface level) - bDeviceSubClass 0 - bDeviceProtocol 0 - bMaxPacketSize0 64 - idVendor 0x0483 STMicroelectronics - idProduct 0x3748 ST-LINK/V2 - bcdDevice 1.00 - iManufacturer 1 STMicroelectronics - iProduct 2 STM32 STLink - iSerial 3 Pÿk^FPgRUB1^C> /etc/modprobe.conf` +* 2. `modprobe -r usb-storage && modprobe usb-storage` +* or 1. `cp stlink_v1.modprobe.conf /etc/modprobe.d` +* 2. `modprobe -r usb-storage && modprobe usb-storage` + +## For STLINKv2 + +You're ready to go :) + +## Build from sources + +``` +$ mkdir build && cd build +$ cmake -DCMAKE_BUILD_TYPE=Debug .. +$ make +``` + +## Using the gdb server + +To run the gdb server: (you do not need sudo if you have set up +permissions correctly) + +``` +$ make && [sudo] ./st-util + +There are a few options: + +./st-util - usage: + + -h, --help Print this help + -vXX, --verbose=XX Specify a specific verbosity level (0..99) + -v, --verbose Specify generally verbose logging + -s X, --stlink_version=X + Choose what version of stlink to use, (defaults to 2) + -1, --stlinkv1 Force stlink version 1 + -p 4242, --listen_port=1234 + Set the gdb server listen port. (default port: 4242) + -m, --multi + Set gdb server to extended mode. + st-util will continue listening for connections after disconnect. + -n, --no-reset + Do not reset board on connection. +``` + +The STLINKv2 device to use can be specified in the environment +variable STLINK_DEVICE on the format `:`. + +Then, in your project directory, someting like this... +(remember, you need to run an _ARM_ gdb, not an x86 gdb) + +``` +$ arm-none-eabi-gdb fancyblink.elf +... +(gdb) tar extended-remote :4242 +... +(gdb) load +Loading section .text, size 0x458 lma 0x8000000 +Loading section .data, size 0x8 lma 0x8000458 +Start address 0x80001c1, load size 1120 +Transfer rate: 1 KB/sec, 560 bytes/write. +(gdb) +... +(gdb) continue +``` + +Have fun! + +## Resetting the chip from GDB + +You may reset the chip using GDB if you want. You'll need to use `target +extended-remote' command like in this session: + +``` +(gdb) target extended-remote localhost:4242 +Remote debugging using localhost:4242 +0x080007a8 in _startup () +(gdb) kill +Kill the program being debugged? (y or n) y +(gdb) run +Starting program: /home/whitequark/ST/apps/bally/firmware.elf +``` + +Remember that you can shorten the commands. `tar ext :4242' is good enough +for GDB. + +## Setting up udev rules + +For convenience, you may install udev rules file, 49-stlinkv*.rules, located +in the root of repository. You will need to copy it to /etc/udev/rules.d, +and then either reboot or execute + +``` +$ udevadm control --reload-rules +$ udevadm trigger +``` + +Udev will now create a /dev/stlinkv2_XX or /dev/stlinkv1_XX file, with the appropriate permissions. +This is currently all the device is for, (only one stlink of each version is supported at +any time presently) + +## Running programs from SRAM + +You can run your firmware directly from SRAM if you want to. Just link +it at 0x20000000 and do + +``` +(gdb) load firmware.elf +``` + +It will be loaded, and pc will be adjusted to point to start of the +code, if it is linked correctly (i.e. ELF has correct entry point). + +## Writing to flash + +The GDB stub ships with a correct memory map, including the flash area. +If you would link your executable to 0x08000000 and then do +(gdb) load firmware.elf +then it would be written to the memory. + +## FAQ + +Q: My breakpoints do not work at all or only work once. + +A: Optimizations can cause severe instruction reordering. For example, +if you are doing something like `REG = 0x100;' in a loop, the code may +be split into two parts: loading 0x100 into some intermediate register +and moving that value to REG. When you set up a breakpoint, GDB will +hook to the first instruction, which may be called only once if there are +enough unused registers. In my experience, -O3 causes that frequently. + +Q: At some point I use GDB command `next', and it hangs. + +A: Sometimes when you will try to use GDB `next' command to skip a loop, +it will use a rather inefficient single-stepping way of doing that. +Set up a breakpoint manually in that case and do `continue'. + +Q: Load command does not work in GDB. + +A: Some people report XML/EXPAT is not enabled by default when compiling +GDB. Memory map parsing thus fail. Use --enable-expat. + +## Currently known working combinations of programmer and target + +STLink v1 (as found on the 32VL Discovery board) + +Known working targets: + +* STM32F100xx (Medium Density VL) +* STM32F103 (according to jpa- on ##stm32) + +No information: + +* everything else! + +STLink v2 (as found on the 32L and F4 Discovery boards), known working targets: + +* STM32F030F4P6 (custom board) +* STM32F0Discovery (STM32F0 Discovery board) +* STM32F100xx (Medium Density VL, as on the 32VL Discovery board) +* STM32L1xx (STM32L Discovery board) +* STM32F103VC, STM32F107RC, STM32L151RB, STM32F205RE and STM32F405RE on custom boards + from [UweBonnes/wiki_fuer_alex](https://github.com/UweBonnes/wiki_fuer_alex/tree/master/layout) +* STM32F103VET6 (HY-STM32 board) +* STM32F105RCT6 (DecaWave EVB1000 board) +* STM32F303xx (STM32F3 Discovery board) +* STM32F407xx (STM32F4 Discovery board) +* STM32F429I-DISCO (STM32F4 Discovery board with LCD) +* STM32F439VIT6 (discovery board reseated CPU) +* STM32L052K8T6 (custom board) +* STM32L151CB (custom board) +* STM32L152RB (STM32L-Discovery board, custom board) +* STM32F051R8T6 (STM320518-EVAL board) + +STLink v2-1 (as found on the Nucleo boards), known working targets: + +* STM32F401xx (STM32 Nucleo-F401RE board) +* STM32F030R8T6 (STM32 Nucleo-F030R8 board) +* STM32F072RBT6 (STM32 Nucleo-F072RB board) +* STM32F103RB (STM32 Nucleo-F103RB board) +* STM32F303RET6 (STM32 Nucleo-F303RE board) +* STM32F334R8 (STM32 Nucleo-F334R8 board) +* STM32F411RET6 (STM32 Nucleo-F411RE board) +* STM32F756NGHx (STMF7 evaluation board) +* STM32L053R8 (STM32 Nucleo-L053R8 board) + +Please report any and all known working combinations so I can update this! + +## Known bugs + +### Sometimes flashing only works after a mass erase + +There is seen a problem sometimes where a flash loader run error occurs and is resolved after mass-erase +of the flash: + +``` +2015-12-09T22:01:57 INFO src/stlink-common.c: Successfully loaded flash loader in sram +2015-12-09T22:02:18 ERROR src/stlink-common.c: flash loader run error +2015-12-09T22:02:18 ERROR src/stlink-common.c: run_flash_loader(0x8000000) failed! == -1 +``` + +Issue(s): [#356](https://github.com/texane/stlink/issues/356) + +## Contributing and versioning + +* The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) +* When creating a pull request, please open first a issue for discussion of new features +* TODO: Enforcement of coding style (linux codestyle + checkpatch) + +## License + +The stlink library and tools are licensed under the [BSD license](LICENSE). With +some exceptions on external components. diff --git a/TODO.md b/TODO.md deleted file mode 100644 index 9c5059a49..000000000 --- a/TODO.md +++ /dev/null @@ -1,11 +0,0 @@ -# flash tool - -- improve flash writing, still use word fast write... too slow - -# documentation - -- make README points to doc/tutorial - -# testing - -- compile and test a realtime kernel (e.g ChibiOS) diff --git a/autogen.sh b/autogen.sh deleted file mode 100755 index 2af5ccdac..000000000 --- a/autogen.sh +++ /dev/null @@ -1,2 +0,0 @@ -#!/bin/sh -autoreconf --install --force --verbose diff --git a/cmake/modules/Find7Zip.cmake b/cmake/modules/Find7Zip.cmake new file mode 100644 index 000000000..c264d12f7 --- /dev/null +++ b/cmake/modules/Find7Zip.cmake @@ -0,0 +1,5 @@ +find_program(ZIP_LOCATION NAMES 7z.exe + HINTS + "C:\\Program Files\\7-Zip\\" + "C:\\Program Files (x86)\\7-Zip\\" +) diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index 7f14ca125..99e872c3e 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -6,28 +6,61 @@ # LIBUSB_LIBRARY - The libraries needed to use libusb # LIBUSB_DEFINITIONS - Compiler switches required for using libusb -FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h - HINTS - /usr - /usr/local - /opt - PATH_SUFFIXES libusb-1.0 - ) +if(WIN32 OR MINGW OR MSYS) + set(LIBUSB_WIN_VERSION "1.0.20") + set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) + set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) + set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/libusb-${LIBUSB_WIN_VERSION}) -if (APPLE) - set(LIBUSB_NAME libusb-1.0.a) -else() - set(LIBUSB_NAME usb-1.0) + if (EXISTS ${LIBUSB_WIN_ARCHIVE_PATH}) + message(STATUS "libusb archive already in build folder") + else () + message(STATUS "libusb downloading ${LIBUSB_WIN_VERSION}") + file(DOWNLOAD + https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download + ${LIBUSB_WIN_ARCHIVE_PATH} + SHOW_PROGRESS) + endif () + + execute_process(COMMAND ${ZIP_LOCATION} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o${LIBUSB_WIN_OUTPUT_FOLDER}) endif() -FIND_LIBRARY(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} +find_path(LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr /usr/local /opt + ${LIBUSB_WIN_OUTPUT_FOLDER}/include + PATH_SUFFIXES libusb-1.0 ) -INCLUDE(FindPackageHandleStandardArgs) +if (APPLE) + set(LIBUSB_NAME libusb-1.0.a) +elseif(MSYS OR MINGW) + set(LIBUSB_NAME usb-1.0) +elseif(WIN32) + set(LIBUSB_NAME libusb-1.0.lib) +else() + set(LIBUSB_NAME usb-1.0) +endif() + +if (MSYS OR MINGW) + if (CMAKE_SIZEOF_VOID_P EQUAL 8) + find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/static) + else () + find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW32/static) + endif () +else () + find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS + /usr + /usr/local + /opt) +endif () + +include(FindPackageHandleStandardArgs) FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) -MARK_AS_ADVANCED(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) +mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) diff --git a/configure.ac b/configure.ac deleted file mode 100644 index 7a101d55d..000000000 --- a/configure.ac +++ /dev/null @@ -1,59 +0,0 @@ -# -*- Autoconf -*- -# Process this file with autoconf to produce a configure script. - -AC_PREREQ(2.61) -AC_INIT([stlink],[1.2.0],[davem@devkitpro.org]) -AC_CONFIG_SRCDIR([src/common.c]) -AC_CONFIG_LIBOBJ_DIR([src]) -AM_INIT_AUTOMAKE([1.10]) - - -# Checks for programs. -AC_PROG_CC -AC_PROG_INSTALL -AC_CANONICAL_HOST -AC_CANONICAL_BUILD -AC_PROG_RANLIB -AM_PROG_CC_C_O - -AC_CHECK_HEADERS(sys/mman.h) -AC_CHECK_HEADERS(sys/poll.h) -AC_REPLACE_FUNCS(mmap) - -if ! hash pkg-config; then - echo "ERROR: pkg-config is needed..." - exit 1 -fi - -# Checks for libraries. -PKG_CHECK_MODULES(USB, libusb-1.0 >= 1.0.0,, - AC_MSG_ERROR([*** Required libusb-1.0 >= 1.0.0 not installed ***])) -AC_CHECK_LIB([usbpath],[usb_path2devnum],,,-lusb) - -LIBS="$LIBS $USB_LIBS" -CFLAGS="$CFLAGS $USB_CFLAGS" - -case "${host}" in - *-mingw32*) - LIBS="$LIBS -lws2_32" - CPPFLAGS="-D__USE_MINGW_ANSI_STDIO=1 $CPPFLAGS" - AC_DEFINE_UNQUOTED(MINGW,1,[This is a MinGW system]) - AM_CONDITIONAL(MINGW, true) - ;; - *) - AM_CONDITIONAL(MINGW, false) -esac - -STLINK_HAS_GUI= -AC_ARG_WITH([gtk_gui], AS_HELP_STRING([--with-gtk-gui], [enable GTK3+ gui])) -if test "x$with_gtk_gui" = "xyes"; then - PKG_CHECK_MODULES([GTK3], [gtk+-3.0]) - PKG_CHECK_MODULES([GLIB], [glib-2.0 > 2.32.0]) - STLINK_HAS_GUI=src/tools/gui - AC_CONFIG_FILES([src/tools/gui/Makefile]) -fi -AC_SUBST([STLINK_HAS_GUI]) - -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT - diff --git a/doc/build_mingw.md b/doc/build_mingw.md new file mode 100644 index 000000000..6327b57c6 --- /dev/null +++ b/doc/build_mingw.md @@ -0,0 +1,23 @@ +Building with MinGW under Windows +================================= + +## Prequistes + +* 7Zip +* CMake 2.8 or higher +* MinGW64 GCC toolchain (5.3.0) + +## Installation + +1. Install 7Zip from http://www.7-zip.org +2. Install CMake from https://cmake.org/download +3. Install MinGW64 from https://sourceforge.net/projects/mingw-w64 (mingw-w64-install.exe) +4. Git clone or download stlink sourcefiles zip +5. Create build folder in source + +# Building + +Check and execute `\scripts\mingw64-build.bat` + +NOTE: when installing different toolchains make sure you edit the path in the `mingw64-build.bat` + the build script uses currently `C:\Program Files\mingw-w64\x86_64-5.3.0-win32-sjlj-rt_v4-rev0\mingw64\bin` diff --git a/doc/release.md b/doc/release.md new file mode 100644 index 000000000..c2dca87b2 --- /dev/null +++ b/doc/release.md @@ -0,0 +1,10 @@ +Release +======= + +This document describes the steps takes for developers to create a release + +1. Update `.version` with semantic version: `x.x.x` +2. Update `README.md` with semantic version `x.x.x` in commits badge +2. Create and push git tag and commits `git tag x.x.x` +3. Create source tarball/zipfile with `make dist` +4. Create binary package with `make package` diff --git a/scripts/appveyor-mingw.sh b/scripts/appveyor-mingw.sh new file mode 100644 index 000000000..4842410ba --- /dev/null +++ b/scripts/appveyor-mingw.sh @@ -0,0 +1,21 @@ +#!/bin/sh +set -e +cd `dirname "$0"`/.. +if [ "$ARCH" = "i686" ]; then + f=i686-4.9.2-release-win32-sjlj-rt_v3-rev1.7z + if ! [ -e $f ]; then + curl -LsSO http://sourceforge.net/projects/mingw-w64/files/Toolchains%20targetting%20Win32/Personal%20Builds/mingw-builds/4.9.2/threads-win32/sjlj/$f + fi + 7z x $f > /dev/null + mv mingw32 /MinGW +else + f=x86_64-4.9.2-release-win32-seh-rt_v3-rev1.7z + if ! [ -e $f ]; then + curl -LsSO http://sourceforge.net/projects/mingw-w64/files/Toolchains%20targetting%20Win64/Personal%20Builds/mingw-builds/4.9.2/threads-win32/seh/$f + fi + 7z x $f > /dev/null + mv mingw64 /MinGW +fi +cd build +cmake .. -G"$GENERATOR" +cmake --build . --config RelWithDebInfo diff --git a/scripts/mingw64-build.bat b/scripts/mingw64-build.bat new file mode 100644 index 000000000..18397f0e0 --- /dev/null +++ b/scripts/mingw64-build.bat @@ -0,0 +1,12 @@ +### +# MinGW64 build helper for windows +# * Sets the correct PATH to compiler and tools +# * Generates MinGW Makefile with CMake +# * Build binaries with mingw32-make +# +# Read documentation about this file in doc/build_mingw.md +### +@echo off +set PATH=C:\Program Files (x86)\CMake\bin;C:\Program Files\CMake\bin;C:\Program Files\mingw-w64\x86_64-5.3.0-win32-sjlj-rt_v4-rev0\mingw64\bin;%PATH% +cmake -G "MinGW Makefiles" .. +mingw32-make diff --git a/src/common.c b/src/common.c index ebc1f8e51..47c6e35be 100644 --- a/src/common.c +++ b/src/common.c @@ -15,7 +15,7 @@ #include "stlink/logging.h" #ifndef _WIN32 -#define O_BINARY 0 +#define O_BINARY 0 //! @todo get rid of this OH MY (@xor-gate) #endif /* todo: stm32l15xxx flash memory, pm0062 manual */ diff --git a/src/gdbserver/gdb-remote.c b/src/gdbserver/gdb-remote.c index 73a157d34..a5d3f4c03 100644 --- a/src/gdbserver/gdb-remote.c +++ b/src/gdbserver/gdb-remote.c @@ -7,11 +7,11 @@ #include #include #include -#include #include #ifdef __MINGW32__ -#include "mingw.h" +#include #else +#include #include #endif diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index efe97e406..5a85d0f0b 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -9,11 +9,11 @@ #include #include #include -#include #include #ifdef __MINGW32__ -#include "mingw.h" +#include #else +#include #include #include #include diff --git a/src/tools/gui/Makefile.am b/src/tools/gui/Makefile.am deleted file mode 100644 index 23e582fa8..000000000 --- a/src/tools/gui/Makefile.am +++ /dev/null @@ -1,30 +0,0 @@ -bin_PROGRAMS = stlink-gui - -stlink_gui_SOURCES = \ - stlink-gui.c \ - stlink-gui.h - -stlink_gui_CPPFLAGS = \ - -I$(top_srcdir)/include \ - $(AM_CPPFLAGS) \ - -I$(top_srcdir)/src \ - @GTK3_CFLAGS@ - -stlink_gui_CFLAGS = \ - $(WARN_CFLAGS) \ - $(AM_CFLAGS) \ - -DSTLINK_UI_DIR="\"$(uidir)\"" - -stlink_gui_LDFLAGS = \ - $(AM_LDFLAGS) - -stlink_gui_LDADD = \ - $(INTLLIBS) \ - $(top_builddir)/libstlink.a \ - @GTK3_LIBS@ - -uidir = $(pkgdatadir)/ui -ui_DATA = stlink-gui.ui -EXTRA_DIST = $(ui_DATA) - --include $(top_srcdir)/git.mk diff --git a/src/usb.c b/src/usb.c index 6dcd7c913..7054fa1a4 100644 --- a/src/usb.c +++ b/src/usb.c @@ -45,7 +45,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, return -1; } else if ((size_t)res != txsize) { printf("[!] send_recv send request wrote %u bytes (instead of %u).\n", - (unsigned int)res, (unsigned int)txsize); + (unsigned int)res, (unsigned int)txsize); } if (rxsize != 0) { From a17b4079ca6128b07774873ac2bbdbc181ec5ff7 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Wed, 3 Aug 2016 20:27:30 +0200 Subject: [PATCH 0455/1435] Reorganise aux files, add sg test to CMakeLists --- .cproject | 593 ------------------------------------ .gitignore | 32 -- ChangeLog | 64 ---- ChangeLog.md | 65 +++- tests/CMakeLists.txt | 1 + tests/{stlink_sg.c => sg.c} | 12 +- 6 files changed, 66 insertions(+), 701 deletions(-) delete mode 100644 .cproject delete mode 100644 ChangeLog mode change 120000 => 100644 ChangeLog.md rename tests/{stlink_sg.c => sg.c} (95%) diff --git a/.cproject b/.cproject deleted file mode 100644 index ff034aaae..000000000 --- a/.cproject +++ /dev/null @@ -1,593 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -make -all -true -true -true - - -make -clean -true -true -true - - -make - -CONFIG_USE_LIBSG=0 -true -true -true - - -make -clean CONFIG_USE_LIBSG=0 -true -true -true - - -make -CONFIG_STM32F4_DISCOVERY=1 -true -true -true - - -make -clean CONFIG_STM32F4_DISCOVERY=1 -true -true -true - - -make - -all -true -true -true - - -make - -clean -true -true -false - - -make - -all -true -true -true - - -make - -clean -true -true -true - - -make - -all -true -true -true - - -make - -clean -true -true -true - - -make -CONFIG_STM32F4_DISCOVERY=1 -true -true -true - - -make -clean -true -true -true - - -make -CONFIG_STM32F4_DISCOVERY=1 -true -true -true - - -make -clean CONFIG_STM32F4_DISCOVERY=1 -true -true -true - - -make -CONFIG_STM32F4_DISCOVERY=1 -true -true -true - - -make -clean CONFIG_STM32F4_DISCOVERY=1 -true -true -true - - -make -CONFIGURE_USE_LIBSG=0 -true -true -true - - -make - -clean CONFIG_USE_LIBSG=0 -true -true -true - - -make - -CONFIG_STM32F4_DISCOVERY=1 -true -true -true - - -make - -clean -true -true -true - - -make -all -true -true -true - - -make -clean -true -true -true - - -make - -CONFIG_USE_LIBSG=0 -true -true -true - - -make -clean -true -true -true - - -make -all -true -true -true - - -make -clean -true -true -true - - -make -CONFIG_STM32F4_DISCOVERY=1 -true -true -true - - -make -clean CONFIG_STM32F4_DISCOVERY=1 -true -true -true - - -make -CONFIG_STM32F4_DISCOVERY=1 -true -true -true - - -make -clean CONFIG_STM32F4_DISCOVERY=1 -true -true -true - - -make - -all -true -true -true - - -make - -clean -true -true -false - - -make - -all -true -true -true - - -make - -clean -true -true -true - - -make -all -true -true -true - - -make -clean -true -true -true - - -make -all -true -true -true - - -make - -all -true -true -true - - -make - -clean -true -true -true - - -make - -CONFIG_STM32F4_DISCOVERY=1 -true -true -true - - -make - -clean CONFIG_STM32F4_DISCOVERY=1 -true -true -true - - - - - - - - - diff --git a/.gitignore b/.gitignore index 1c8296454..378eac25d 100644 --- a/.gitignore +++ b/.gitignore @@ -1,33 +1 @@ build -INSTALL -Makefile.in -aclocal.m4 -autom4te.cache -config.guess -config.sub -configure -depcomp -install-sh -ltmain.sh -missing -*.bz2 -*.lo -*.o -.libs -libtool -*.la -config.log -config.status -compile -st-flash -st-util -st-term -st-info -test_usb -test_sg -*.deps* -*.dirstamp -*.a -Makefile -*.exe -example/blink/*.elf diff --git a/ChangeLog b/ChangeLog deleted file mode 100644 index 355ba08ab..000000000 --- a/ChangeLog +++ /dev/null @@ -1,64 +0,0 @@ -Stlink ChangeLog -================ - -v2.0.0 -====== - -Ongoing development - -Major changes: - -* Deprecation of autotools (autoconf, automake) - -v1.2.0 -====== - -Release date: 16 may 2016 - -Features added: - -* Add multiple stlink probing (`st-info --probe`, `st-info --hla-serial`) with printing serial in hex and OpenOCD `hla_serial` format (Jerry Jacobs) -* Add stlink usb probe API functions (Jerry Jacobs) -* Added parameter to specify one stlink v2 of many (Georg von Zengen) - -Changes: - -* Refactoring/fixes of flash loader (Maxime Coquelin) - -Updates and fixes: - -* Synchronize cache for stm32f7 (Tristan Gingold) -* Allow flashing of STM32L4 down to 1.71 V (Greg Meiste) -* Fix on stm32l4 to clear flash mass erase flags on CR (Bruno Dal Bo) -* Proper writing of page 0 of second bank for stm32l476xe (Tobias Badertscher) -* Trace the read data in stlink_read_debug32 and not the address of the variable (Tobias Badertscher) -* Mac OS X El Capitan platform support confirmation (Nikolay) -* Do not send a NUL at end of packets to gdb (Tristan Gingold) -* Correctly compute flash write size for partial pages (Dave Vandervies) -* _stlink_usb_reset use hardreset (mlundinse) -* Make sure MCU is halted before running RAM based flashloaders (mlundinse) -* Could not flash STM32_F3_SMALL (Max Chen) -* STM32F4 8-bit support for 1.8v operation (Andy Isaacson) -* Fix F2 memory map (Nicolas Schodet) -* Memory map for stm32f42xxx and stm32f43xxx devices (Craig Lilley) -* Stm32l0x flash loader (Robin Kreis) - -Chip support added for: - -* STM32L053R8 (Jean-Luc Béchennec) -* STM32F7 Support (mlundinse) -* Add STM32L4 to CHIPID #defines and devices[], flash driver and loaded (Dave Vandervies) -* Basic support for F446 (Pavel Kirienko) -* STM32F303 High Density -* STM32L1xx Cat.2 devices (Nicolas Schodet) - -Board support added for: - -* Nucleo-F303RE (Kyle Manna) -* Nucleo-F411RE (texane) - -Build system: - -* Travis: Initial support for Travis continues integration on Linux & Mac OS X (Jerry Jacobs) -* CMake: Document in README.md and add extra strict compiler flags (Jerry Jacobs) -* CMake: First stab at a cmake build (Josh Bialkowski) diff --git a/ChangeLog.md b/ChangeLog.md deleted file mode 120000 index b0936e8d0..000000000 --- a/ChangeLog.md +++ /dev/null @@ -1 +0,0 @@ -ChangeLog \ No newline at end of file diff --git a/ChangeLog.md b/ChangeLog.md new file mode 100644 index 000000000..355ba08ab --- /dev/null +++ b/ChangeLog.md @@ -0,0 +1,64 @@ +Stlink ChangeLog +================ + +v2.0.0 +====== + +Ongoing development + +Major changes: + +* Deprecation of autotools (autoconf, automake) + +v1.2.0 +====== + +Release date: 16 may 2016 + +Features added: + +* Add multiple stlink probing (`st-info --probe`, `st-info --hla-serial`) with printing serial in hex and OpenOCD `hla_serial` format (Jerry Jacobs) +* Add stlink usb probe API functions (Jerry Jacobs) +* Added parameter to specify one stlink v2 of many (Georg von Zengen) + +Changes: + +* Refactoring/fixes of flash loader (Maxime Coquelin) + +Updates and fixes: + +* Synchronize cache for stm32f7 (Tristan Gingold) +* Allow flashing of STM32L4 down to 1.71 V (Greg Meiste) +* Fix on stm32l4 to clear flash mass erase flags on CR (Bruno Dal Bo) +* Proper writing of page 0 of second bank for stm32l476xe (Tobias Badertscher) +* Trace the read data in stlink_read_debug32 and not the address of the variable (Tobias Badertscher) +* Mac OS X El Capitan platform support confirmation (Nikolay) +* Do not send a NUL at end of packets to gdb (Tristan Gingold) +* Correctly compute flash write size for partial pages (Dave Vandervies) +* _stlink_usb_reset use hardreset (mlundinse) +* Make sure MCU is halted before running RAM based flashloaders (mlundinse) +* Could not flash STM32_F3_SMALL (Max Chen) +* STM32F4 8-bit support for 1.8v operation (Andy Isaacson) +* Fix F2 memory map (Nicolas Schodet) +* Memory map for stm32f42xxx and stm32f43xxx devices (Craig Lilley) +* Stm32l0x flash loader (Robin Kreis) + +Chip support added for: + +* STM32L053R8 (Jean-Luc Béchennec) +* STM32F7 Support (mlundinse) +* Add STM32L4 to CHIPID #defines and devices[], flash driver and loaded (Dave Vandervies) +* Basic support for F446 (Pavel Kirienko) +* STM32F303 High Density +* STM32L1xx Cat.2 devices (Nicolas Schodet) + +Board support added for: + +* Nucleo-F303RE (Kyle Manna) +* Nucleo-F411RE (texane) + +Build system: + +* Travis: Initial support for Travis continues integration on Linux & Mac OS X (Jerry Jacobs) +* CMake: Document in README.md and add extra strict compiler flags (Jerry Jacobs) +* CMake: First stab at a cmake build (Josh Bialkowski) diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 6f20fa922..5d114a608 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -1,5 +1,6 @@ set(TESTS usb + sg ) foreach(test ${TESTS}) diff --git a/tests/stlink_sg.c b/tests/sg.c similarity index 95% rename from tests/stlink_sg.c rename to tests/sg.c index db7eed325..d12f6ba43 100644 --- a/tests/stlink_sg.c +++ b/tests/sg.c @@ -7,8 +7,7 @@ #include #include #include -#include "stlink-common.h" -#include "uglylogging.h" +#include static void __attribute__((unused)) mark_buf(stlink_t *sl) { memset(sl->q_buf, 0, sizeof(sl->q_buf)); @@ -165,15 +164,6 @@ int main(int argc, char *argv[]) { stlink_read_mem32(sl, 0x20000000, 1024 * 6); stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2); #endif -#if 1 - reg regs; - stlink_read_all_regs(sl, ®s); - stlink_step(sl); - fputs("++++++++++ write r0 = 0x12345678\n", stderr); - stlink_write_reg(sl, 0x12345678, 0); - stlink_read_reg(sl, 0, ®s); - stlink_read_all_regs(sl, ®s); -#endif #if 0 stlink_run(sl); stlink_status(sl); From ee2681ecebc8b2284cab02e1dd40536dfb91fc51 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Wed, 3 Aug 2016 20:59:21 +0200 Subject: [PATCH 0456/1435] Update README.md Remove appveyor build badge --- README.md | 1 - 1 file changed, 1 deletion(-) diff --git a/README.md b/README.md index 1e47e4df4..1fef34665 100644 --- a/README.md +++ b/README.md @@ -4,7 +4,6 @@ Open source version of the STMicroelectronics Stlink Tools [![GitHub release](https://img.shields.io/github/release/texane/stlink.svg?maxAge=2592000)](https://github.com/texane/stlink/releases/latest) [![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.2.0.svg?maxAge=2592000)](https://github.com/texane/stlink/compare/1.2.0...master) [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) -[![Windows Status](https://ci.appveyor.com/api/projects/status/o659serc9m21n22n/branch/appveyor-integration?svg=true)](https://ci.appveyor.com/project/xor-gate/stlink) [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) ## HOWTO From 1f3aa3c64898fc5a3c4f470aa1e488c87dd964be Mon Sep 17 00:00:00 2001 From: Fabien Chouteau Date: Tue, 9 Aug 2016 15:53:22 +0200 Subject: [PATCH 0457/1435] Unhexify GDB monitor commands (qRcmd) It improves readability and will allow parsing of more complex monitor commands. --- src/gdbserver/gdb-server.c | 41 ++++++++++++++++++++++++++++++++------ 1 file changed, 35 insertions(+), 6 deletions(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 5a85d0f0b..b8ee66eb5 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -927,6 +927,21 @@ static void cache_sync(stlink_t *sl) cache_flush(sl, ccr); } +static size_t unhexify(const char *in, char *out, size_t out_count) +{ + size_t i; + unsigned int c; + + for (i = 0; i < out_count; i++) { + if (sscanf(in + (2 * i), "%02x", &c) != 1) { + return i; + } + out[i] = (char)c; + } + + return i; +} + int serve(stlink_t *sl, st_state_t *st) { int sock = socket(AF_INET, SOCK_STREAM, 0); if(sock < 0) { @@ -1073,20 +1088,34 @@ int serve(stlink_t *sl, st_state_t *st) { params = separator + 1; } + size_t hex_len = strlen(params); + size_t alloc_size = (hex_len / 2) + 1; + size_t cmd_len; + char *cmd = malloc(alloc_size); - if (!strncmp(params,"726573756d65",12)) {// resume + if (cmd == NULL) { + DLOG("Rcmd unhexify allocation error\n"); + break; + } + + cmd_len = unhexify(params, cmd, alloc_size - 1); + cmd[cmd_len] = 0; + + DLOG("unhexified Rcmd: '%s'\n", cmd); + + if (!strncmp(cmd, "resume", 6)) {// resume DLOG("Rcmd: resume\n"); cache_sync(sl); stlink_run(sl); reply = strdup("OK"); - } else if (!strncmp(params,"68616c74",8)) { //halt + } else if (!strncmp(cmd, "halt", 4)) { //halt reply = strdup("OK"); stlink_force_debug(sl); DLOG("Rcmd: halt\n"); - } else if (!strncmp(params,"6a7461675f7265736574",20)) { //jtag_reset + } else if (!strncmp(cmd, "jtag_reset", 10)) { //jtag_reset reply = strdup("OK"); stlink_jtag_reset(sl, 0); @@ -1094,7 +1123,7 @@ int serve(stlink_t *sl, st_state_t *st) { stlink_force_debug(sl); DLOG("Rcmd: jtag_reset\n"); - } else if (!strncmp(params,"7265736574",10)) { //reset + } else if (!strncmp(cmd, "reset", 5)) { //reset reply = strdup("OK"); stlink_force_debug(sl); @@ -1104,9 +1133,9 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("Rcmd: reset\n"); } else { - DLOG("Rcmd: %s\n", params); + DLOG("Rcmd: %s\n", cmd); } - + free(cmd); } if(reply == NULL) From 1f938b239d430d673374f2d3902341123d4d19e0 Mon Sep 17 00:00:00 2001 From: "fabien.lementec" Date: Wed, 10 Aug 2016 12:16:38 +0200 Subject: [PATCH 0458/1435] add STM32F769NI to working targets --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 1fef34665..d9388c12e 100644 --- a/README.md +++ b/README.md @@ -221,6 +221,7 @@ STLink v2-1 (as found on the Nucleo boards), known working targets: * STM32F411RET6 (STM32 Nucleo-F411RE board) * STM32F756NGHx (STMF7 evaluation board) * STM32L053R8 (STM32 Nucleo-L053R8 board) +* STM32F769NI (STM32F7 discovery board) Please report any and all known working combinations so I can update this! From d0910c66d7c98c0448e4d9a3805986519848c255 Mon Sep 17 00:00:00 2001 From: Fabien Chouteau Date: Mon, 8 Aug 2016 19:52:43 +0200 Subject: [PATCH 0459/1435] Prototype of ARM semihosting support --- CMakeLists.txt | 4 +- src/gdbserver/gdb-server.c | 91 ++++++++++++++++++++++++- src/gdbserver/semihosting.c | 128 ++++++++++++++++++++++++++++++++++++ src/gdbserver/semihosting.h | 34 ++++++++++ 4 files changed, 255 insertions(+), 2 deletions(-) create mode 100644 src/gdbserver/semihosting.c create mode 100644 src/gdbserver/semihosting.h diff --git a/CMakeLists.txt b/CMakeLists.txt index cf18e0228..fc0127dda 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -154,7 +154,9 @@ target_link_libraries(st-info ${PROJECT_NAME}) add_executable(st-util src/gdbserver/gdb-remote.c src/gdbserver/gdb-remote.h src/gdbserver/gdb-server.c - src/gdbserver/gdb-server.h) + src/gdbserver/gdb-server.h + src/gdbserver/semihosting.c + src/gdbserver/semihosting.h) if (WIN32 OR MSYS OR MINGW) target_link_libraries(st-util ${PROJECT_NAME} wsock32 ws2_32) else () diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index b8ee66eb5..53f4fd962 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -24,13 +24,18 @@ #include "gdb-remote.h" #include "gdb-server.h" +#include "semihosting.h" #define FLASH_BASE 0x08000000 +/* Semihosting doesn't have a short option, we define a value to identify it */ +#define SEMIHOSTING_OPTION 128 + //Allways update the FLASH_PAGE before each use, by calling stlink_calculate_pagesize #define FLASH_PAGE (sl->flash_pgsz) static stlink_t *connected_stlink = NULL; +bool semihosting = false; static const char hex[] = "0123456789abcdef"; @@ -72,6 +77,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { {"listen_port", required_argument, NULL, 'p'}, {"multi", optional_argument, NULL, 'm'}, {"no-reset", optional_argument, NULL, 'n'}, + {"semihosting", no_argument, NULL, SEMIHOSTING_OPTION}, {0, 0, 0, 0}, }; const char * help_str = "%s - usage:\n\n" @@ -89,6 +95,8 @@ int parse_options(int argc, char** argv, st_state_t *st) { "\t\t\tst-util will continue listening for connections after disconnect.\n" " -n, --no-reset\n" "\t\t\tDo not reset board on connection.\n" + " --semihosting\n" + "\t\t\tEnable semihosting support.\n" "\n" "The STLINKv2 device to use can be specified in the environment\n" "variable STLINK_DEVICE on the format :.\n" @@ -145,6 +153,9 @@ int parse_options(int argc, char** argv, st_state_t *st) { case 'n': st->reset = 0; break; + case SEMIHOSTING_OPTION: + semihosting = true; + break; } } @@ -591,6 +602,16 @@ static void init_code_breakpoints(stlink_t *sl) { } } +static int has_breakpoint(stm32_addr_t addr) +{ + for(int i = 0; i < code_break_num; i++) { + if (code_breaks[i].addr == addr) { + return 1; + } + } + return 0; +} + static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { stm32_addr_t fpb_addr; uint32_t mask; @@ -1132,6 +1153,28 @@ int serve(stlink_t *sl, st_state_t *st) { init_data_watchpoints(sl); DLOG("Rcmd: reset\n"); + } else if (!strncmp(cmd, "semihosting ", 12)) { + DLOG("Rcmd: got semihosting cmd '%s'", cmd); + char *arg = cmd + 12; + + /* Skip whitespaces */ + while (isspace(*arg)) { + arg++; + } + + if (!strncmp(arg, "enable", 6) + || !strncmp(arg, "1", 1)) + { + semihosting = true; + reply = strdup("OK"); + } else if (!strncmp(arg, "disable", 7) + || !strncmp(arg, "0", 1)) + { + semihosting = false; + reply = strdup("OK"); + } else { + DLOG("Rcmd: unknown semihosting arg: '%s'\n", arg); + } } else { DLOG("Rcmd: %s\n", cmd); } @@ -1244,7 +1287,53 @@ int serve(stlink_t *sl, st_state_t *st) { stlink_status(sl); if(sl->core_stat == STLINK_CORE_HALTED) { - break; + struct stlink_reg reg; + int ret; + stm32_addr_t pc; + stm32_addr_t addr; + int offset = 0; + uint16_t insn; + + if (!semihosting) { + break; + } + + stlink_read_all_regs (sl, ®); + + /* Read PC */ + pc = reg.r[15]; + + /* Compute aligned value */ + offset = pc % 4; + addr = pc - offset; + + /* Read instructions (address and length must be + * aligned). + */ + ret = stlink_read_mem32(sl, addr, (offset > 2 ? 8 : 4)); + + if (ret != 0) { + DLOG("Semihost: cannot read instructions at: " + "0x%08x\n", addr); + break; + } + + memcpy(&insn, &sl->q_buf[offset], sizeof(insn)); + + if (insn == 0xBEAB && !has_breakpoint(addr)) { + DLOG("Do semihosting...\n"); + + do_semihosting (sl, reg.r[0], reg.r[1], ®.r[0]); + + /* Jump over the break instruction */ + stlink_write_reg(sl, reg.r[15] + 2, 15); + + /* continue execution */ + cache_sync(sl); + stlink_run(sl); + } else { + break; + } } usleep(100000); diff --git a/src/gdbserver/semihosting.c b/src/gdbserver/semihosting.c new file mode 100644 index 000000000..74d5fa398 --- /dev/null +++ b/src/gdbserver/semihosting.c @@ -0,0 +1,128 @@ +#include +#include + +#include "semihosting.h" + +#include +#include + +static int mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) +{ + int offset = addr % 4; + int len = 4; + + if (sl == NULL || data == NULL) { + return -1; + } + + /* Read address and length must be aligned */ + if (stlink_read_mem32(sl, addr - offset, len) != 0) { + return -1; + } + + *data = sl->q_buf[offset]; + return 0; +} + +#ifdef UNUSED +static int mem_read_u16(stlink_t *sl, uint32_t addr, uint16_t *data) +{ + int offset = addr % 4; + int len = (offset > 2 ? 8 : 4); + + if (sl == NULL || data == NULL) { + return -1; + } + + /* Read address and length must be aligned */ + if (stlink_read_mem32(sl, addr - offset, len) != 0) { + return -1; + } + + memcpy(data, &sl->q_buf[offset], sizeof(*data)); + return 0; +} + +static int mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) +{ + int offset = addr % 4; + int len = (offset > 0 ? 8 : 4); + + if (sl == NULL || data == NULL) { + return -1; + } + + /* Read address and length must be aligned */ + if (stlink_read_mem32(sl, addr - offset, len) != 0) { + return -1; + } + + memcpy(data, &sl->q_buf[offset], sizeof(*data)); + return 0; +} +#endif + +static int mem_read(stlink_t *sl, uint32_t addr, uint8_t *data, uint16_t len) +{ + int offset = addr % 4; + int read_len = len + offset; + + if (sl == NULL || data == NULL) { + return -1; + } + + /* Align read size */ + if ((read_len % 4) != 0) { + read_len += 4 - (read_len % 4); + } + + /* Read address and length must be aligned */ + if (stlink_read_mem32(sl, addr - offset, read_len) != 0) { + return -1; + } + + memcpy(data, &sl->q_buf[offset], len); + return 0; +} + +#define WRITE0_BUFFER_SIZE 64 + +int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { + + if (sl == NULL || ret == NULL) { + return -1; + } + + switch (r0) { + case SYS_WRITEC: + { + uint8_t c; + if (mem_read_u8(sl, r1, &c) == 0) { + fprintf(stderr, "%c", c); + } + break; + } + case SYS_WRITE0: + { + uint8_t buf[WRITE0_BUFFER_SIZE]; + + while (true) { + if (mem_read(sl, r1, buf, WRITE0_BUFFER_SIZE) != 0 ) { + return -1; + } + for (int i = 0; i < WRITE0_BUFFER_SIZE; i++) { + if (buf[i] == 0) { + return 0; + } + fprintf(stderr, "%c", buf[i]); + } + r1 += WRITE0_BUFFER_SIZE; + } + break; + } + default: + fprintf(stderr, "semihosting: unsupported call 0x%#x\n", r0); + return -1; + } + return 0; +} diff --git a/src/gdbserver/semihosting.h b/src/gdbserver/semihosting.h new file mode 100644 index 000000000..392d31f7d --- /dev/null +++ b/src/gdbserver/semihosting.h @@ -0,0 +1,34 @@ +#ifndef _SEMIHOSTING_H_ +#define _SEMIHOSTING_H_ + +#include + +#define SYS_OPEN 0x01 +#define SYS_CLOSE 0x02 +#define SYS_WRITEC 0x03 +#define SYS_WRITE0 0x04 +#define SYS_WRITE 0x05 +#define SYS_READ 0x06 +#define SYS_READC 0x07 +#define SYS_ISERROR 0x08 +#define SYS_ISTTY 0x09 +#define SYS_SEEK 0x0A + +#define SYS_FLEN 0x0C +#define SYS_TMPNAM 0x0D +#define SYS_REMOVE 0x0E +#define SYS_RENAME 0x0E +#define SYS_CLOCK 0x10 +#define SYS_TIME 0x11 + +#define SYS_ERRNO 0x13 + +#define SYS_GET_CMD 0x15 +#define SYS_HEAPINFO 0x16 + +#define SYS_ELAPSED 0x30 +#define SYS_TICKFREQ 0x31 + +int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret); + +#endif /* ! _SEMIHOSTING_H_ */ From 3a1ab6e3e097a89f8cad37e68c4a1a8714f27462 Mon Sep 17 00:00:00 2001 From: Fabien Chouteau Date: Fri, 12 Aug 2016 15:54:07 +0200 Subject: [PATCH 0460/1435] Improve ARM semi-hosting support This patch adds the following operations: - SYS_OPEN - SYS_CLOSE - SYS_WRITE - SYS_READ - SYS_ERRNO - SYS_REMOVE - SYS_SEEK The use of utility functions mem_read() and mem_write() add an unnecessary memcpy() call. All buffer transfer could be done directly in the sl->q_buf data instead of using a temporary transfer buffer. However, given the relative slowness of target memory transfer, I don't think that this has a big impact on performances --- src/gdbserver/gdb-server.c | 4 +- src/gdbserver/semihosting.c | 363 +++++++++++++++++++++++++++++++++++- 2 files changed, 363 insertions(+), 4 deletions(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 53f4fd962..c6746fb7a 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -1321,10 +1321,12 @@ int serve(stlink_t *sl, st_state_t *st) { memcpy(&insn, &sl->q_buf[offset], sizeof(insn)); if (insn == 0xBEAB && !has_breakpoint(addr)) { - DLOG("Do semihosting...\n"); do_semihosting (sl, reg.r[0], reg.r[1], ®.r[0]); + /* Write return value */ + stlink_write_reg(sl, reg.r[0], 0); + /* Jump over the break instruction */ stlink_write_reg(sl, reg.r[15] + 2, 15); diff --git a/src/gdbserver/semihosting.c b/src/gdbserver/semihosting.c index 74d5fa398..4ea6ccf5c 100644 --- a/src/gdbserver/semihosting.c +++ b/src/gdbserver/semihosting.c @@ -1,5 +1,9 @@ #include #include +#include +#include +#include +#include #include "semihosting.h" @@ -62,7 +66,7 @@ static int mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) } #endif -static int mem_read(stlink_t *sl, uint32_t addr, uint8_t *data, uint16_t len) +static int mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { int offset = addr % 4; int read_len = len + offset; @@ -76,7 +80,7 @@ static int mem_read(stlink_t *sl, uint32_t addr, uint8_t *data, uint16_t len) read_len += 4 - (read_len % 4); } - /* Read address and length must be aligned */ + /* Address and length must be aligned */ if (stlink_read_mem32(sl, addr - offset, read_len) != 0) { return -1; } @@ -85,20 +89,371 @@ static int mem_read(stlink_t *sl, uint32_t addr, uint8_t *data, uint16_t len) return 0; } +static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) +{ + int offset = addr % 4; + int write_len = len + offset; + + if (sl == NULL || data == NULL) { + return -1; + } + + /* Align read size */ + if ((write_len % 4) != 0) { + write_len += 4 - (write_len % 4); + } + + memcpy(&sl->q_buf[offset], data, len); + + /* Address and length must be aligned */ + if (stlink_write_mem32(sl, addr - offset, write_len) != 0) { + return -1; + } + + return 0; +} + +/* For the SYS_WRITE0 call, we don't know the size of the null-terminated buffer + * in the target memory. Instead of reading one byte at a time, we read by + * chunks of WRITE0_BUFFER_SIZE bytes. + */ #define WRITE0_BUFFER_SIZE 64 +/* Define a maximum size for buffers transmitted by semihosting. There is no + * limit in the ARM specification but this is a safety net. + * We remove 4 byte from Q_BUF_LEN to handle alignment correction. + */ +#define MAX_BUFFER_SIZE (Q_BUF_LEN - 4) + +/* Flags for Open syscall */ + +#ifndef O_BINARY +#define O_BINARY 0 +#endif + +static int open_mode_flags[12] = { + O_RDONLY, + O_RDONLY | O_BINARY, + O_RDWR, + O_RDWR | O_BINARY, + O_WRONLY | O_CREAT | O_TRUNC, + O_WRONLY | O_CREAT | O_TRUNC | O_BINARY, + O_RDWR | O_CREAT | O_TRUNC, + O_RDWR | O_CREAT | O_TRUNC | O_BINARY, + O_WRONLY | O_CREAT | O_APPEND, + O_WRONLY | O_CREAT | O_APPEND | O_BINARY, + O_RDWR | O_CREAT | O_APPEND, + O_RDWR | O_CREAT | O_APPEND | O_BINARY +}; + +static int saved_errno = 0; + int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (sl == NULL || ret == NULL) { return -1; } + DLOG("Do semihosting R0=0x%08x R1=0x%08x\n", r0, r1); + switch (r0) { + case SYS_OPEN: + { + uint32_t args[3]; + uint32_t name_address; + uint32_t mode; + uint32_t name_len; + char *name; + + if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { + DLOG("Semihosting SYS_OPEN error: " + "cannot read args from target memory\n"); + *ret = -1; + return -1; + } + + name_address = args[0]; + mode = args[1]; + name_len = args[2]; + + if (mode > 12) { + /* Invalid mode */ + DLOG("Semihosting SYS_OPEN error: invalid mode %d\n", mode); + *ret = -1; + return -1; + } + + /* Add the trailing zero that is not counted in the length argument (see + * ARM semihosting specification) + */ + name_len += 1; + + if (name_len > MAX_BUFFER_SIZE) { + DLOG("Semihosting SYS_OPEN error: name buffer size is too big %d\n", + name_len); + *ret = -1; + return -1; + } + name = malloc(name_len); + + if (name == NULL) { + DLOG("Semihosting SYS_OPEN error: cannot allocate name buffer\n"); + *ret = -1; + return -1; + } + + if (mem_read(sl, name_address, name, name_len) != 0 ) { + free(name); + *ret = -1; + DLOG("Semihosting SYS_OPEN error: " + "cannot read name from target memory\n"); + return -1; + } + + DLOG("Semihosting: open('%s', (SH open mode)%d, 0644)\n", name, mode); + + *ret = (uint32_t)open(name, open_mode_flags[mode], 0644); + saved_errno = errno; + + DLOG("Semihosting: return %d\n", *ret); + + free(name); + break; + } + case SYS_CLOSE: + { + uint32_t args[1]; + int fd; + + if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { + DLOG("Semihosting SYS_CLOSE error: " + "cannot read args from target memory\n"); + *ret = -1; + return -1; + } + + fd = (int)args[0]; + + DLOG("Semihosting: close(%d)\n", fd); + + *ret = (uint32_t)close(fd); + saved_errno = errno; + + DLOG("Semihosting: return %d\n", *ret); + break; + } + case SYS_WRITE: + { + uint32_t args[3]; + uint32_t buffer_address; + int fd; + size_t buffer_len; + void *buffer; + + if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { + DLOG("Semihosting SYS_WRITE error: " + "cannot read args from target memory\n"); + *ret = -1; + return -1; + } + + fd = (int)args[0]; + buffer_address = args[1]; + buffer_len = (size_t)args[2]; + + if (buffer_len > MAX_BUFFER_SIZE) { + DLOG("Semihosting SYS_WRITE error: buffer size is too big %d\n", + buffer_len); + *ret = buffer_len; + return -1; + } + + buffer = malloc(buffer_len); + + if (buffer == NULL) { + DLOG("Semihosting SYS_WRITE error: cannot allocate buffer\n"); + *ret = buffer_len; + return -1; + } + + if (mem_read(sl, buffer_address, buffer, buffer_len) != 0 ) { + DLOG("Semihosting SYS_WRITE error: " + "cannot read buffer from target memory\n"); + free(buffer); + *ret = buffer_len; + return -1; + } + + DLOG("Semihosting: write(%d, target_addr:0x%08x, %zu)\n", fd, + buffer_address, buffer_len); + + *ret = (uint32_t)write(fd, buffer, buffer_len); + saved_errno = errno; + + if (*ret == (uint32_t)-1) { + *ret = buffer_len; + } else { + *ret -= buffer_len; + } + + DLOG("Semihosting: return %d\n", *ret); + free(buffer); + break; + } + case SYS_READ: + { + uint32_t args[3]; + uint32_t buffer_address; + int fd; + size_t buffer_len; + void *buffer; + + if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { + DLOG("Semihosting SYS_READ error: " + "cannot read args from target memory\n"); + *ret = -1; + return -1; + } + + fd = (int)args[0]; + buffer_address = args[1]; + buffer_len = (size_t)args[2]; + + if (buffer_len > MAX_BUFFER_SIZE) { + DLOG("Semihosting SYS_READ error: buffer size is too big %d\n", + buffer_len); + *ret = buffer_len; + return -1; + } + + buffer = malloc(buffer_len); + + if (buffer == NULL) { + DLOG("Semihosting SYS_READ error: cannot allocatebuffer\n"); + *ret = buffer_len; + return -1; + } + + DLOG("Semihosting: read(%d, target_addr:0x%08x, %zu)\n", fd, + buffer_address, buffer_len); + + *ret = (uint32_t)read(fd, buffer, buffer_len); + saved_errno = errno; + + if (*ret == (uint32_t)-1) { + *ret = buffer_len; + } else { + if (mem_write(sl, buffer_address, buffer, *ret) != 0 ) { + DLOG("Semihosting SYS_READ error: " + "cannot write buffer to target memory\n"); + free(buffer); + *ret = buffer_len; + return -1; + } else { + *ret -= buffer_len; + } + } + + DLOG("Semihosting: return %d\n", *ret); + free(buffer); + break; + } + case SYS_ERRNO: + { + *ret = (uint32_t)saved_errno; + DLOG("Semihosting: Errno return %d\n", *ret); + break; + } + case SYS_REMOVE: + { + uint32_t args[2]; + uint32_t name_address; + uint32_t name_len; + char *name; + + if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { + DLOG("Semihosting SYS_REMOVE error: " + "cannot read args from target memory\n"); + *ret = -1; + return -1; + } + + name_address = args[0]; + name_len = args[1]; + + /* Add the trailing zero that is not counted in the length argument (see + * ARM semihosting specification) + */ + name_len += 1; + + if (name_len > MAX_BUFFER_SIZE) { + DLOG("Semihosting SYS_REMOVE error: " + "name buffer size is too big %d\n", name_len); + *ret = -1; + return -1; + } + name = malloc(name_len); + + if (name == NULL) { + DLOG("Semihosting SYS_REMOVE error: cannot allocate name buffer\n"); + *ret = -1; + return -1; + } + + if (mem_read(sl, name_address, name, name_len) != 0 ) { + free(name); + *ret = -1; + DLOG("Semihosting SYS_REMOVE error: " + "cannot read name from target memory\n"); + return -1; + } + + DLOG("Semihosting: unlink('%s')\n", name); + + *ret = (uint32_t)unlink(name); + saved_errno = errno; + + DLOG("Semihosting: return %d\n", *ret); + + free(name); + break; + } + case SYS_SEEK: + { + uint32_t args[2]; + int fd; + off_t offset; + + if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { + DLOG("Semihosting SYS_SEEK error: " + "cannot read args from target memory\n"); + *ret = -1; + return -1; + } + + fd = (int)args[0]; + offset = (off_t)args[1]; + + DLOG("Semihosting: lseek(%d, %d, SEEK_SET)\n", fd, offset); + + *ret = (uint32_t)lseek(fd, offset, SEEK_SET); + saved_errno = errno; + + if (*ret != (uint32_t)-1) { + /* Success */ + *ret = 0; + } + DLOG("Semihosting: return %d\n", *ret); + break; + } case SYS_WRITEC: { uint8_t c; if (mem_read_u8(sl, r1, &c) == 0) { fprintf(stderr, "%c", c); + } else { + DLOG("Semihosting WRITEC: " + "cannot read target memory at 0x%08x\n", r1); } break; } @@ -108,6 +463,8 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { while (true) { if (mem_read(sl, r1, buf, WRITE0_BUFFER_SIZE) != 0 ) { + DLOG("Semihosting WRITE0: " + "cannot read target memory at 0x%08x\n", r1); return -1; } for (int i = 0; i < WRITE0_BUFFER_SIZE; i++) { @@ -121,7 +478,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { break; } default: - fprintf(stderr, "semihosting: unsupported call 0x%#x\n", r0); + fprintf(stderr, "semihosting: unsupported call %#x\n", r0); return -1; } return 0; From 1118f8ed498a1c0eff280d36c97a14248b91b73b Mon Sep 17 00:00:00 2001 From: Andrea Mucignat Date: Mon, 15 Aug 2016 11:11:51 -0700 Subject: [PATCH 0461/1435] Fix memory map for STM32F Also: - fixed a typo in an if statement condition in make_memory_map - cleaned up usage of '4096' in favor of const size_t sz = 4096. --- src/chipid.c | 2 +- src/gdbserver/gdb-server.c | 18 ++++++++++-------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/src/chipid.c b/src/chipid.c index 546e2384e..7f8bbd3f9 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -9,7 +9,7 @@ static const struct stlink_chipid_params devices[] = { .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1ff0f442, // section 45.2 .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x5C000, // "SRAM" byte size in hex from + .sram_size = 0x80000, // "SRAM" byte size in hex from .bootrom_base = 0x00200000, //! "System memory" starting address from .bootrom_size = 0xEDC0 //! @todo "System memory" byte size in hex from }, diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index c6746fb7a..15f837908 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -416,7 +416,7 @@ static const char* const memory_map_template_F7 = "" " " // ITCM ram 16kB " " // ITCM flash - " " // sram + " " // sram " " // Sectors 0..3 " 0x8000" // 32kB " " @@ -435,26 +435,28 @@ static const char* const memory_map_template_F7 = char* make_memory_map(stlink_t *sl) { /* This will be freed in serve() */ - char* map = malloc(4096); + const size_t sz = 4096; + char* map = malloc(sz); map[0] = '\0'; if(sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F446) { strcpy(map, memory_map_template_F4); - } else if(sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->core_id==STM32F7_CORE_ID) { - strcpy(map, memory_map_template_F7); + } else if(sl->core_id==STM32F7_CORE_ID) { + snprintf(map, sz, memory_map_template_F7, + sl->sram_size); } else if(sl->chip_id==STLINK_CHIPID_STM32_F4_HD) { strcpy(map, memory_map_template_F4_HD); } else if(sl->chip_id==STLINK_CHIPID_STM32_F2) { - snprintf(map, 4096, memory_map_template_F2, + snprintf(map, sz, memory_map_template_F2, sl->flash_size, sl->sram_size, sl->flash_size - 0x20000, sl->sys_base, sl->sys_size); } else if(sl->chip_id==STLINK_CHIPID_STM32_L4) { - snprintf(map, 4096, memory_map_template_L4, + snprintf(map, sz, memory_map_template_L4, sl->flash_size, sl->flash_size); } else { - snprintf(map, 4096, memory_map_template, + snprintf(map, sz, memory_map_template, sl->flash_size, sl->sram_size, sl->flash_size, sl->flash_pgsz, @@ -1054,7 +1056,7 @@ int serve(stlink_t *sl, st_state_t *st) { if(!strcmp(queryName, "Supported")) { if(sl->chip_id==STLINK_CHIPID_STM32_F4 - || sl->chip_id==STLINK_CHIPID_STM32_F4_HD + || sl->chip_id==STLINK_CHIPID_STM32_F4_HD || sl->core_id==STM32F7_CORE_ID) { reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); } From a35cc23525f985b6bd494a315189c326b33d29cd Mon Sep 17 00:00:00 2001 From: Andrew Andrianov Date: Sat, 9 Jul 2016 23:07:50 +0300 Subject: [PATCH 0462/1435] CMakeLists.txt: Add shared library build and debian packaging Signed-off-by: Andrew Andrianov --- CMakeLists.txt | 84 +++++++++++++++++++++++++++++++--- debian/changelog | 5 ++ debian/compat | 1 + debian/control | 34 ++++++++++++++ debian/libstlink-dev.dirs | 2 + debian/libstlink-dev.install | 3 ++ debian/libstlink.dirs | 1 + debian/libstlink.install | 1 + debian/rules | 28 ++++++++++++ debian/source/format | 1 + debian/stlink-gui.dirs | 2 + debian/stlink-gui.install | 2 + debian/stlink-tools.dirs | 2 + debian/stlink-tools.install | 1 + doc/app-example/CMakeLists.txt | 28 ++++++++++++ doc/app-example/README.md | 2 + doc/app-example/main.c | 29 ++++++++++++ pkg-config.pc.cmake | 11 +++++ scripts/run_clang_analyze.sh | 8 ++++ 19 files changed, 239 insertions(+), 6 deletions(-) create mode 100644 debian/changelog create mode 100644 debian/compat create mode 100644 debian/control create mode 100644 debian/libstlink-dev.dirs create mode 100644 debian/libstlink-dev.install create mode 100644 debian/libstlink.dirs create mode 100644 debian/libstlink.install create mode 100755 debian/rules create mode 100644 debian/source/format create mode 100644 debian/stlink-gui.dirs create mode 100644 debian/stlink-gui.install create mode 100644 debian/stlink-tools.dirs create mode 100644 debian/stlink-tools.install create mode 100644 doc/app-example/CMakeLists.txt create mode 100644 doc/app-example/README.md create mode 100644 doc/app-example/main.c create mode 100644 pkg-config.pc.cmake create mode 100755 scripts/run_clang_analyze.sh diff --git a/CMakeLists.txt b/CMakeLists.txt index fc0127dda..27aa9cd33 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,4 +1,6 @@ cmake_minimum_required(VERSION 2.8.7) +project(stlink C) +set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics Stlink Tools") project(stlink C) include(CheckCCompilerFlag) @@ -18,7 +20,6 @@ if (DEFINED ENV{TRAVIS_TAG} AND NOT "$ENV{TRAVIS_TAG}" STREQUAL "") set (STLINK_PACKAGE_VERSION "$ENV{TRAVIS_TAG}") elseif (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") # Working off a git repo, using git versioning - # Check if HEAD is pointing to a tag execute_process ( COMMAND "${GIT_EXECUTABLE}" describe --always @@ -40,9 +41,23 @@ elseif (EXISTS ${PROJECT_SOURCE_DIR}/.version) # we can extract the package version from .version file. file (STRINGS .version STLINK_PACKAGE_VERSION) else () - set (STLINK_PACKAGE_VERSION "Unknown") + set (STLINK_PACKAGE_VERSION "999.99.99-unknown") endif() +# We shall use STLINK_PACKAGE_VERSION* variables to set soversion and other stuff +# Since these numbers will appear in .so names, e.g. libstlink.so.1.2.0 +# We can't just use STLINK_PACKAGE_VERSION here +# (Well, we can, but that breaks all the existing conventions) +# We can't as well use PROJECT_VERSION* variables here, since they are managed +# by project() directive and the whole version detection relies on PROJECT_SOURCE_DIR + +string(REPLACE "." ";" STLINK_PACKAGE_VERSION_ARRAY ${STLINK_PACKAGE_VERSION}) +string(REPLACE "-" ";" STLINK_PACKAGE_VERSION_ARRAY "${STLINK_PACKAGE_VERSION_ARRAY}") +list(GET STLINK_PACKAGE_VERSION_ARRAY 0 STLINK_PACKAGE_VERSION_MAJOR) +list(GET STLINK_PACKAGE_VERSION_ARRAY 1 STLINK_PACKAGE_VERSION_MINOR) +list(GET STLINK_PACKAGE_VERSION_ARRAY 2 STLINK_PACKAGE_VERSION_PATCH) +list(GET STLINK_PACKAGE_VERSION_ARRAY 3 STLINK_PACKAGE_VERSION_TAG) + if(WIN32) find_package(7Zip REQUIRED) message(STATUS "7Zip Location: " ${ZIP_LOCATION}) @@ -133,11 +148,30 @@ include_directories(${LIBUSB_INCLUDE_DIR}) include_directories(include) include_directories(src/mingw) -add_library(${PROJECT_NAME} STATIC +set(STLINK_LIB_STATIC ${PROJECT_NAME}-static) + +add_library(${PROJECT_NAME} SHARED ${STLINK_HEADERS} # header files for ide projects generated by cmake ${STLINK_SOURCE}) target_link_libraries(${PROJECT_NAME} ${LIBUSB_LIBRARY}) +if (WIN32 OR MSYS OR MINGW) + set(STLINK_SHARED_VERSION + ${STLINK_PACKAGE_VERSION_MAJOR}.${STLINK_PACKAGE_VERSION_MINOR}) +else() + set(STLINK_SHARED_VERSION + ${STLINK_PACKAGE_VERSION_MAJOR}.${STLINK_PACKAGE_VERSION_MINOR}.${STLINK_PACKAGE_VERSION_PATCH}) +endif() + +set_target_properties(${PROJECT_NAME} PROPERTIES SOVERSION ${STLINK_PACKAGE_VERSION_MAJOR} +VERSION ${STLINK_SHARED_VERSION}) + +add_library(${STLINK_LIB_STATIC} STATIC + ${STLINK_HEADERS} # header files for ide projects generated by cmake + ${STLINK_SOURCE}) +target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY}) +set_target_properties(${STLINK_LIB_STATIC} PROPERTIES OUTPUT_NAME ${PROJECT_NAME}) + if (APPLE) find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) @@ -163,11 +197,49 @@ else () target_link_libraries(st-util ${PROJECT_NAME}) endif () -install(TARGETS ${PROJECT_NAME} st-flash st-util st-info +install(TARGETS ${PROJECT_NAME} ${STLINK_LIB_STATIC} st-flash st-util st-info RUNTIME DESTINATION bin - ARCHIVE DESTINATION lib + ARCHIVE DESTINATION lib/${CMAKE_LIBRARY_PATH} + LIBRARY DESTINATION lib/${CMAKE_LIBRARY_PATH} +) +# Now, install the development headers +file(GLOB STLINK_HEADERS + "${CMAKE_SOURCE_DIR}/include/stlink/*.h" ) +install(FILES ${CMAKE_SOURCE_DIR}/include/stlink.h + DESTINATION include/${CMAKE_LIBRARY_PATH}/stlink-${STLINK_PACKAGE_VERSION}/) + +install(FILES ${STLINK_HEADERS} + DESTINATION include/${CMAKE_LIBRARY_PATH}/stlink-${STLINK_PACKAGE_VERSION}/stlink) + +if (NOT APPLE AND NOT WIN32) + set(PKG_CONFIG_LIBDIR + "\${prefix}/lib/\${deb_host_multiarch}" + ) + set(PKG_CONFIG_INCLUDEDIR + "\${prefix}/include/\${deb_host_multiarch}/${PROJECT_NAME}-${STLINK_PACKAGE_VERSION}" + ) + set(PKG_CONFIG_LIBS + "-L\${libdir} -l:libstlink.so.${STLINK_PACKAGE_VERSION}" + ) + set(PKG_CONFIG_CFLAGS + "-I\${includedir}" + ) + + set(PKG_CONFIG_REQUIRES + "libusb-1.0" + ) + + configure_file( + "${CMAKE_CURRENT_SOURCE_DIR}/pkg-config.pc.cmake" + "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" + ) + + install(FILES "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" + DESTINATION lib/${CMAKE_LIBRARY_PATH}/pkgconfig/) +endif() + if(NOT MINGW) list(APPEND STLINK_SOURCE src/tools/term.c) add_executable(st-term src/tools/term.c) @@ -212,6 +284,6 @@ if (APPLE) set(CPACK_GENERATOR "ZIP") file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/osx") set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/osx") -endif () +endif() add_custom_target(dist COMMAND ${CMAKE_MAKE_PROGRAM} package_source) include (CPack) diff --git a/debian/changelog b/debian/changelog new file mode 100644 index 000000000..d0471cb7d --- /dev/null +++ b/debian/changelog @@ -0,0 +1,5 @@ +libstlink (1.2.1) unstable; urgency=low + + * Initial Debian-Packaged Release. + + -- Andrew 'Necromant' Andrianov Sat, 09 Jul 2016 23:16:07 +0300 diff --git a/debian/compat b/debian/compat new file mode 100644 index 000000000..ec635144f --- /dev/null +++ b/debian/compat @@ -0,0 +1 @@ +9 diff --git a/debian/control b/debian/control new file mode 100644 index 000000000..b9beac2fc --- /dev/null +++ b/debian/control @@ -0,0 +1,34 @@ +Source: libstlink +Priority: optional +Maintainer: Andrew 'Necromant' Andrianov +Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev +Standards-Version: 3.9.5 +Section: libs +Homepage: +Vcs-Git: https://github.com/texane/stlink.git +Vcs-Browser: https://github.com/texane/stlink + +Package: libstlink-dev +Section: libdevel +Architecture: any +Depends: libstlink (= ${binary:Version}), ${misc:Depends} +Description: OpenSource ST-Link tools replacement. Development headers. + This package contains development headers for libstlink. + +Package: libstlink +Architecture: any +Depends: ${shlibs:Depends}, ${misc:Depends} +Description: OpenSource ST-Link tools replacement. Shared library. + This package libstlink shared library. + +Package: stlink-tools +Section: libdevel +Architecture: any +Depends: libstlink (= ${binary:Version}), ${misc:Depends} +Description: OpenSource ST-Link tools replacement. Commandline Utilities. + +Package: stlink-gui +Section: libdevel +Architecture: any +Depends: libstlink (= ${binary:Version}), ${misc:Depends} +Description: OpenSource ST-Link tools replacement. GUI Tool. diff --git a/debian/libstlink-dev.dirs b/debian/libstlink-dev.dirs new file mode 100644 index 000000000..44188162e --- /dev/null +++ b/debian/libstlink-dev.dirs @@ -0,0 +1,2 @@ +usr/lib +usr/include diff --git a/debian/libstlink-dev.install b/debian/libstlink-dev.install new file mode 100644 index 000000000..1eff3299c --- /dev/null +++ b/debian/libstlink-dev.install @@ -0,0 +1,3 @@ +usr/include/* +usr/lib/*/lib*.a +usr/lib/*/pkgconfig/* diff --git a/debian/libstlink.dirs b/debian/libstlink.dirs new file mode 100644 index 000000000..68457717b --- /dev/null +++ b/debian/libstlink.dirs @@ -0,0 +1 @@ +usr/lib diff --git a/debian/libstlink.install b/debian/libstlink.install new file mode 100644 index 000000000..703ad8b31 --- /dev/null +++ b/debian/libstlink.install @@ -0,0 +1 @@ +usr/lib/*/lib*.so* diff --git a/debian/rules b/debian/rules new file mode 100755 index 000000000..4979b59d7 --- /dev/null +++ b/debian/rules @@ -0,0 +1,28 @@ +#!/usr/bin/make -f +# See debhelper(7) (uncomment to enable) +# output every command that modifies files on the build system. +#DH_VERBOSE = 1 + +# see EXAMPLES in dpkg-buildflags(1) and read /usr/share/dpkg/* +DPKG_EXPORT_BUILDFLAGS = 1 +include /usr/share/dpkg/default.mk + +# see FEATURE AREAS in dpkg-buildflags(1) +#export DEB_BUILD_MAINT_OPTIONS = hardening=+all + +# see ENVIRONMENT in dpkg-buildflags(1) +# package maintainers to append CFLAGS +#export DEB_CFLAGS_MAINT_APPEND = -Wall -pedantic +# package maintainers to append LDFLAGS +#export DEB_LDFLAGS_MAINT_APPEND = -Wl,--as-needed + + +# main packaging script based on dh7 syntax +%: + dh $@ + +# debmake generated override targets +# This is example for Cmake (See http://bugs.debian.org/641051 ) +override_dh_auto_configure: + dh_auto_configure -- \ + -DCMAKE_LIBRARY_PATH=$(DEB_HOST_MULTIARCH) diff --git a/debian/source/format b/debian/source/format new file mode 100644 index 000000000..89ae9db8f --- /dev/null +++ b/debian/source/format @@ -0,0 +1 @@ +3.0 (native) diff --git a/debian/stlink-gui.dirs b/debian/stlink-gui.dirs new file mode 100644 index 000000000..d080ed407 --- /dev/null +++ b/debian/stlink-gui.dirs @@ -0,0 +1,2 @@ +/usr/bin +/usr/share/ diff --git a/debian/stlink-gui.install b/debian/stlink-gui.install new file mode 100644 index 000000000..eedcd7172 --- /dev/null +++ b/debian/stlink-gui.install @@ -0,0 +1,2 @@ +/usr/bin/stlink-gui* +/usr/share/* diff --git a/debian/stlink-tools.dirs b/debian/stlink-tools.dirs new file mode 100644 index 000000000..377c76613 --- /dev/null +++ b/debian/stlink-tools.dirs @@ -0,0 +1,2 @@ +/usr/bin + diff --git a/debian/stlink-tools.install b/debian/stlink-tools.install new file mode 100644 index 000000000..4fa1125bf --- /dev/null +++ b/debian/stlink-tools.install @@ -0,0 +1 @@ +/usr/bin/st-* diff --git a/doc/app-example/CMakeLists.txt b/doc/app-example/CMakeLists.txt new file mode 100644 index 000000000..0e91bed6f --- /dev/null +++ b/doc/app-example/CMakeLists.txt @@ -0,0 +1,28 @@ +# Warning: This example assumes that you are building on a host +# with pkg-config available (e.g. linux). The logic required to +# build under windows/mingw and/or mac was intentionally omitted +# to keep this CMakeLists as small as possible + +cmake_minimum_required(VERSION 2.8) + +project(st-hello) +set(PROJECT_VERSION 0.1) +set(SRCS main.c) + +find_package(PkgConfig) +pkg_check_modules(STLINK REQUIRED stlink) + +set(CMAKE_C_FLAGS " ${STLINK_CFLAGS_OTHER} -Wall -Werror") + +include_directories( + ${STLINK_INCLUDE_DIRS} +) + +add_executable(${PROJECT_NAME} ${SRCS}) + +target_link_libraries(${PROJECT_NAME} + ${STLINK_LIBRARIES} +) + +install(TARGETS ${PROJECT_NAME} + DESTINATION bin) diff --git a/doc/app-example/README.md b/doc/app-example/README.md new file mode 100644 index 000000000..683056171 --- /dev/null +++ b/doc/app-example/README.md @@ -0,0 +1,2 @@ +This is a simple standalone application example that uses libstlink. +You can use this as a boilerplate for your own app development diff --git a/doc/app-example/main.c b/doc/app-example/main.c new file mode 100644 index 000000000..12621434a --- /dev/null +++ b/doc/app-example/main.c @@ -0,0 +1,29 @@ +#include +#include +#include + +static stlink_t *stlink_open_first(void) +{ + stlink_t* sl = NULL; + sl = stlink_v1_open(0, 1); + if (sl == NULL) + sl = stlink_open_usb(0, 1, NULL); + + return sl; +} + + +int main() +{ + stlink_t* sl = NULL; + sl = stlink_open_first(); + + if (sl == NULL) { + fprintf(stderr, "Failed to open stlink device ;(\n"); + exit(1); + } + + fprintf(stderr, "STlink device opened, that's cool!\n"); + stlink_close(sl); + return 0; +} diff --git a/pkg-config.pc.cmake b/pkg-config.pc.cmake new file mode 100644 index 000000000..4170bf84b --- /dev/null +++ b/pkg-config.pc.cmake @@ -0,0 +1,11 @@ +deb_host_multiarch=${CMAKE_LIBRARY_PATH} +Name: ${PROJECT_NAME} +Description: ${PROJECT_DESCRIPTION} +Version: ${PROJECT_VERSION} +Requires: ${PKG_CONFIG_REQUIRES} +prefix=${CMAKE_INSTALL_PREFIX} +includedir=${PKG_CONFIG_INCLUDEDIR} +libdir=${PKG_CONFIG_LIBDIR} +Libs: ${PKG_CONFIG_LIBS} +Cflags: ${PKG_CONFIG_CFLAGS} + diff --git a/scripts/run_clang_analyze.sh b/scripts/run_clang_analyze.sh new file mode 100755 index 000000000..8d5c5a988 --- /dev/null +++ b/scripts/run_clang_analyze.sh @@ -0,0 +1,8 @@ +#!/bin/bash +# Run this hacky script in project root directory to start +# clang static analysis. Adjust ccc-analyzer path if nesesary +CCC_ANALYZER=/usr/share/clang/scan-build-3.5/ccc-analyzer +mkdir -p build-clang-analyze/reports +cd build-clang-analyze +cmake -DCMAKE_C_COMPILER=${CCC_ANALYZER} $* .. +scan-build -o ./reports --keep-empty make From c37848583b633cf9cb8ff896ec620dd9b0aafc26 Mon Sep 17 00:00:00 2001 From: Anatoli Date: Tue, 6 Sep 2016 00:04:59 +0200 Subject: [PATCH 0463/1435] Implement parser of ihex --- include/stlink.h | 4 +- src/common.c | 223 ++++++++++++++++++++++++++++++++++++++++++---- src/tools/flash.c | 4 +- 3 files changed, 210 insertions(+), 21 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index d1bf4815c..86e53f060 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -180,7 +180,9 @@ typedef struct flash_loader { int stlink_erase_flash_mass(stlink_t* sl); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); - int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); + uint8_t stlink_parse_hex(const char* hex); + int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); + int stlink_fwrite_flash(stlink_t *sl, const char* path, bool is_ihex, stm32_addr_t addr); int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); diff --git a/src/common.c b/src/common.c index 47c6e35be..95bbf9ee2 100644 --- a/src/common.c +++ b/src/common.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -1753,6 +1754,173 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t return stlink_verify_write_flash(sl, addr, base, len); } +// note: length not checked +uint8_t stlink_parse_hex(const char* hex) { + uint8_t d[2]; + for(int i = 0; i < 2; ++i) { + char c = *(hex + i); + if(c >= '0' && c <= '9') d[i] = c - '0'; + else if(c >= 'A' && c <= 'F') d[i] = c - 'A' + 10; + else if(c >= 'a' && c <= 'f') d[i] = c - 'a' + 10; + else return 0; // error + } + return (d[0] << 4) | (d[1]); +} + +int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin) { + int res = 0; + *begin = UINT32_MAX; + uint8_t* data = NULL; + uint32_t end = 0; + bool eof_found = false; + + for(int scan = 0; (res == 0) && (scan < 2); ++scan) { // parse file two times - first to find memory range, second - to fill it + if(scan == 1) { + if(!eof_found) { + ELOG("No EoF recond\n"); + res = -1; + break; + } + + if(*begin >= end) { + ELOG("No data found in file\n"); + res = -1; + break; + } + + *size = (end - *begin) + 1; + data = calloc(*size, 1); // use calloc to get NULL if out of memory + if(!data) { + ELOG("Cannot allocate %d bytes\n", *size); + res = -1; + break; + } + + memset(data, erased_pattern, *size); + } + + FILE* file = fopen(path, "r"); + if(!file) { + ELOG("Cannot open file\n"); + res = -1; + break; + } + + uint32_t lba = 0; + + char line[1 + 5*2 + 255*2 + 2]; + while(fgets(line, sizeof(line), file)) { + if(line[0] == '\n' || line[0] == '\r') continue; // skip empty lines + if(line[0] != ':') { // no marker - wrong file format + ELOG("Wrong file format - no marker\n"); + res = -1; + break; + } + + size_t l = strlen(line); + while(l > 0 && (line[l-1] == '\n' || line[l-1] == '\r')) --l; // trim EoL + if((l < 11) || (l == (sizeof(line)-1))) { // line too short or long - wrong file format + ELOG("Wrong file format - wrong line length\n"); + res = -1; + break; + } + + // check sum + uint8_t chksum = 0; + for(size_t i = 1; i < l; i += 2) { + chksum += stlink_parse_hex(line + i); + } + if(chksum != 0) { + ELOG("Wrong file format - checksum mismatch\n"); + res = -1; + break; + } + + uint8_t reclen = stlink_parse_hex(line + 1); + if(((uint32_t)reclen + 5)*2 + 1 != l) { + ELOG("Wrong file format - record length mismatch\n"); + res = -1; + break; + } + + uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | ((uint16_t)stlink_parse_hex(line + 5)); + uint8_t rectype = stlink_parse_hex(line + 7); + + switch(rectype) { + case 0: // data + if(scan == 0) { + uint32_t b = lba + offset; + uint32_t e = b + reclen - 1; + if(b < *begin) *begin = b; + if(e > end) end = e; + } + else { + for(size_t i = 0; i < reclen; ++i) { + uint8_t b = stlink_parse_hex(line + 9 + i*2); + uint32_t addr = lba + offset + i; + if(addr >= *begin && addr <= end) { + data[addr - *begin] = b; + } + } + } + break; + + case 1: // EoF + eof_found = true; + break; + + case 2: // Extended Segment Address, unexpected + res = -1; + break; + + case 3: // Start Segment Address, unexpected + res = -1; + break; + + case 4: // Extended Linear Address + if(reclen == 2) { + lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | ((uint32_t)stlink_parse_hex(line + 11) << 16); + } + else { + ELOG("Wrong file format - wrong LBA length\n"); + res = -1; + } + break; + + case 5: // Start Linear Address - expected, but ignore + break; + + default: + ELOG("Wrong file format - unexpected record type %d\n", rectype); + res = -1; + } + if(res != 0) break; + } + + fclose(file); + } + + if(res == 0) { + *mem = data; + } + else { + free(data); + } + + return res; +} + +// FIXME remove +void dumpMem(uint8_t const * mem, size_t len) { + for(size_t i = 0; i < len; ++i) { + if(i > 0 && i % 16 == 0) printf("\n"); + else if(i > 0 && i % 8 == 0) printf(" "); + if(i % 16 == 0) printf("%08zx ", i); + printf("%02x ", mem[i]); + } + printf("\n"); +} + /** * Write the given binary file into flash at address "addr" * @param sl @@ -1760,35 +1928,49 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t * @param addr where to start writing * @return 0 on success, -ve on failure. */ -int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { +int stlink_fwrite_flash(stlink_t *sl, const char* path, bool is_ihex, stm32_addr_t addr) { /* write the file in flash at addr */ int err; unsigned int num_empty, index, val; unsigned char erased_pattern; mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); - return -1; - } + uint8_t * mem; + size_t size; + bool eraseonly = false; if (sl->flash_type == STLINK_FLASH_TYPE_L0) erased_pattern = 0x00; else erased_pattern = 0xff; - index = (unsigned int) mf.len; - for(num_empty = 0; num_empty != mf.len; ++num_empty) { - if (mf.base[--index] != erased_pattern) { - break; - } - } - /* Round down to words */ - num_empty -= (num_empty & 3); - if(num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); - } - err = stlink_write_flash(sl, addr, mf.base, (num_empty == mf.len) ? (uint32_t) mf.len : (uint32_t) mf.len - num_empty, num_empty == mf.len); + if(is_ihex) { + uint32_t begin; + if(0 != stlink_parse_ihex(path, 0xFF, &mem, &size, &begin)) + return -1; + addr = begin; + } + else { + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return -1; + } + + index = (unsigned int) mf.len; + for(num_empty = 0; num_empty != mf.len; ++num_empty) { + if (mf.base[--index] != erased_pattern) { + break; + } + } + /* Round down to words */ + num_empty -= (num_empty & 3); + if(num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); + } + mem = mf.base; + size = (num_empty == mf.len) ? (uint32_t) mf.len : (uint32_t) mf.len - num_empty; + eraseonly = (num_empty == mf.len); + } + err = stlink_write_flash(sl, addr, mem, size, eraseonly); /* set stack*/ stlink_read_debug32(sl, addr, &val); stlink_write_reg(sl, val, 13); @@ -1796,6 +1978,9 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { stlink_read_debug32(sl, addr + 4, &val); stlink_write_reg(sl, val, 15); stlink_run(sl); - unmap_file(&mf); + if(is_ihex) + free(mem); + else + unmap_file(&mf); return err; } diff --git a/src/tools/flash.c b/src/tools/flash.c index 50ad64092..f26472d45 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -34,6 +34,7 @@ struct opts const char* devname; char *serial; const char* filename; + bool is_ihex; stm32_addr_t addr; size_t size; int reset; @@ -157,6 +158,7 @@ static int get_opts(struct opts* o, int ac, char** av) o->filename = av[i + 1]; /** @todo This is a little evil as strtoul could return 0 and is of type unsigned long int */ o->addr = (uint32_t) strtoul(av[i + 2], NULL, 16); + o->is_ihex = (0 == strcmp(".hex", o->filename + (strlen(o->filename) - 4))); // ends with .hex return 0; } @@ -246,7 +248,7 @@ int main(int ac, char** av) { if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { - err = stlink_fwrite_flash(sl, o.filename, o.addr); + err = stlink_fwrite_flash(sl, o.filename, o.is_ihex, o.addr); if (err == -1) { printf("stlink_fwrite_flash() == -1\n"); From 7c99eb050300b76bfd64b380d7c8693476d540e2 Mon Sep 17 00:00:00 2001 From: Anatoli Date: Tue, 6 Sep 2016 22:56:54 +0200 Subject: [PATCH 0464/1435] re-desing of command line parsing for st-flash; unit-tests for it; implement read into ihex; --- CMakeLists.txt | 5 +- include/stlink.h | 9 +- include/stlink/tools/flash.h | 28 ++ src/common.c | 568 +++++++++++++++++++++-------------- src/tools/flash.c | 171 ++--------- src/tools/flash_opts.c | 156 ++++++++++ tests/CMakeLists.txt | 5 + tests/flash.c | 111 +++++++ 8 files changed, 681 insertions(+), 372 deletions(-) create mode 100644 include/stlink/tools/flash.h create mode 100644 src/tools/flash_opts.c create mode 100644 tests/flash.c diff --git a/CMakeLists.txt b/CMakeLists.txt index fc0127dda..f1ade75d8 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -145,8 +145,11 @@ if (APPLE) target_link_libraries(${PROJECT_NAME} ${CoreFoundation} ${IOKit} ${ObjC}) endif () +add_library(stflash STATIC + src/tools/flash_opts.c) +target_link_libraries(${PROJECT_NAME} ${LIBUSB_LIBRARY}) add_executable(st-flash src/tools/flash.c) -target_link_libraries(st-flash ${PROJECT_NAME}) +target_link_libraries(st-flash ${PROJECT_NAME} stflash) add_executable(st-info src/tools/info.c) target_link_libraries(st-info ${PROJECT_NAME}) diff --git a/include/stlink.h b/include/stlink.h index 86e53f060..5151cc166 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -180,9 +180,10 @@ typedef struct flash_loader { int stlink_erase_flash_mass(stlink_t* sl); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); - uint8_t stlink_parse_hex(const char* hex); - int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); - int stlink_fwrite_flash(stlink_t *sl, const char* path, bool is_ihex, stm32_addr_t addr); + int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); + uint8_t stlink_get_erased_pattern(stlink_t *sl); + int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); + int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); @@ -201,7 +202,7 @@ typedef struct flash_loader { bool stlink_is_core_halted(stlink_t *sl); int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); - int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size); + int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); int stlink_load_device_params(stlink_t *sl); #include "stlink/sg.h" diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h new file mode 100644 index 000000000..10e6ffac4 --- /dev/null +++ b/include/stlink/tools/flash.h @@ -0,0 +1,28 @@ +#ifndef STLINK_TOOLS_FLASH_H_ +#define STLINK_TOOLS_FLASH_H_ + +#include +#include + +#define DEBUG_LOG_LEVEL 100 +#define STND_LOG_LEVEL 50 + +enum flash_cmd {FLASH_CMD_NONE = 0, FLASH_CMD_WRITE = 1, FLASH_CMD_READ = 2, FLASH_CMD_ERASE = 3}; +enum flash_format {FLASH_FORMAT_BINARY = 0, FLASH_FORMAT_IHEX = 1}; +struct flash_opts +{ + enum flash_cmd cmd; + const char* devname; + uint8_t serial[16]; + const char* filename; + stm32_addr_t addr; + size_t size; + int reset; + int log_level; + enum flash_format format; +}; + +int flash_get_opts(struct flash_opts* o, int ac, char** av); + +#endif // STLINK_FLASH_H_ + diff --git a/src/common.c b/src/common.c index 95bbf9ee2..51c92bac3 100644 --- a/src/common.c +++ b/src/common.c @@ -1096,17 +1096,11 @@ int stlink_fwrite_sram return error; } -int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) { - /* read size bytes from addr to file */ +typedef bool (*save_block_fn)(void* arg, uint8_t* block, ssize_t len); - int error = -1; - size_t off; +static int stlink_read(stlink_t* sl, stm32_addr_t addr, size_t size, save_block_fn fn, void* fn_arg) { - const int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); - if (fd == -1) { - fprintf(stderr, "open(%s) == -1\n", path); - return -1; - } + int error = -1; if (size <1) size = sl->flash_size; @@ -1115,7 +1109,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) size = sl->flash_size; size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz; - for (off = 0; off < size; off += cmp_size) { + for (size_t off = 0; off < size; off += cmp_size) { size_t aligned_size; /* adjust last page size */ @@ -1128,8 +1122,7 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) stlink_read_mem32(sl, addr + (uint32_t) off, aligned_size); - if (write(fd, sl->q_buf, sl->q_len) != (ssize_t) aligned_size) { - fprintf(stderr, "write() != aligned_size\n"); + if (!fn(fn_arg, sl->q_buf, aligned_size)) { goto on_error; } } @@ -1138,6 +1131,134 @@ int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size) error = 0; on_error: + return error; +} + +struct stlink_fread_worker_arg { + int fd; +}; + +static bool stlink_fread_worker(void* arg, uint8_t* block, ssize_t len) { + struct stlink_fread_worker_arg* the_arg = (struct stlink_fread_worker_arg*)arg; + if (write(the_arg->fd, block, len) != len) { + fprintf(stderr, "write() != aligned_size\n"); + return false; + } + else { + return true; + } +} + +struct stlink_fread_ihex_worker_arg { + FILE* file; + uint32_t addr; + uint32_t lba; + uint8_t buf[16]; + uint8_t buf_pos; +}; + +static bool stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg* the_arg) { + uint32_t addr = the_arg->addr; + uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + (uint8_t)((addr & 0x00FF0000) >> 16); + if(17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", (addr & 0xFFFF0000) >> 16, (uint8_t)(0x100 - sum))) + return false; + + the_arg->lba = (addr & 0xFFFF0000); + + return true; +} + +static bool stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg* the_arg) { + uint8_t count = the_arg->buf_pos; + if(count == 0) return true; + + uint32_t addr = the_arg->addr; + + if(the_arg->lba != (addr & 0xFFFF0000)) { // segment changed + if(!stlink_fread_ihex_newsegment(the_arg)) return false; + } + + uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + (uint8_t)(addr & 0x000000FF); + if(9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) + return false; + + for(uint8_t i = 0; i < count; ++i) { + uint8_t b = the_arg->buf[i]; + sum += b; + if(2 != fprintf(the_arg->file, "%02X", b)) + return false; + } + + if(4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) + return false; + + the_arg->addr += count; + the_arg->buf_pos = 0; + + return true; +} + +static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg* the_arg, int fd, stm32_addr_t addr) { + the_arg->file = fdopen(fd, "w"); + the_arg->addr = addr; + the_arg->lba = 0; + the_arg->buf_pos = 0; + + return (the_arg->file != NULL); +} + +static bool stlink_fread_ihex_worker(void* arg, uint8_t* block, ssize_t len) { + struct stlink_fread_ihex_worker_arg* the_arg = (struct stlink_fread_ihex_worker_arg*)arg; + + for(ssize_t i = 0; i < len; ++i) { + if(the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full + if(!stlink_fread_ihex_writeline(the_arg)) return false; + } + + the_arg->buf[the_arg->buf_pos++] = block[i]; + } + + return true; +} + +static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg* the_arg) { + if(!stlink_fread_ihex_writeline(the_arg)) return false; + + // FIXME do we need the Start Linear Address? + + if(13 != fprintf(the_arg->file, ":00000001FF\r\n")) // EoF + return false; + + return (0 == fclose(the_arg->file)); +} + +int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size) { + /* read size bytes from addr to file */ + + int error; + + int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); + if (fd == -1) { + fprintf(stderr, "open(%s) == -1\n", path); + return -1; + } + + if(is_ihex) { + struct stlink_fread_ihex_worker_arg arg; + if(stlink_fread_ihex_init(&arg, fd, addr)) { + error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); + if(!stlink_fread_ihex_finalize(&arg)) + error = -1; + } + else { + error = -1; + } + } + else { + struct stlink_fread_worker_arg arg = { fd }; + error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); + } + close(fd); return error; @@ -1755,170 +1876,199 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } // note: length not checked -uint8_t stlink_parse_hex(const char* hex) { - uint8_t d[2]; - for(int i = 0; i < 2; ++i) { - char c = *(hex + i); - if(c >= '0' && c <= '9') d[i] = c - '0'; - else if(c >= 'A' && c <= 'F') d[i] = c - 'A' + 10; - else if(c >= 'a' && c <= 'f') d[i] = c - 'a' + 10; - else return 0; // error - } - return (d[0] << 4) | (d[1]); +static uint8_t stlink_parse_hex(const char* hex) { + uint8_t d[2]; + for(int i = 0; i < 2; ++i) { + char c = *(hex + i); + if(c >= '0' && c <= '9') d[i] = c - '0'; + else if(c >= 'A' && c <= 'F') d[i] = c - 'A' + 10; + else if(c >= 'a' && c <= 'f') d[i] = c - 'a' + 10; + else return 0; // error + } + return (d[0] << 4) | (d[1]); } int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin) { - int res = 0; - *begin = UINT32_MAX; - uint8_t* data = NULL; - uint32_t end = 0; - bool eof_found = false; - - for(int scan = 0; (res == 0) && (scan < 2); ++scan) { // parse file two times - first to find memory range, second - to fill it - if(scan == 1) { - if(!eof_found) { - ELOG("No EoF recond\n"); - res = -1; - break; - } - - if(*begin >= end) { - ELOG("No data found in file\n"); - res = -1; - break; - } - - *size = (end - *begin) + 1; - data = calloc(*size, 1); // use calloc to get NULL if out of memory - if(!data) { - ELOG("Cannot allocate %d bytes\n", *size); - res = -1; - break; - } - - memset(data, erased_pattern, *size); - } - - FILE* file = fopen(path, "r"); - if(!file) { - ELOG("Cannot open file\n"); - res = -1; - break; - } - - uint32_t lba = 0; - - char line[1 + 5*2 + 255*2 + 2]; - while(fgets(line, sizeof(line), file)) { - if(line[0] == '\n' || line[0] == '\r') continue; // skip empty lines - if(line[0] != ':') { // no marker - wrong file format - ELOG("Wrong file format - no marker\n"); - res = -1; - break; - } - - size_t l = strlen(line); - while(l > 0 && (line[l-1] == '\n' || line[l-1] == '\r')) --l; // trim EoL - if((l < 11) || (l == (sizeof(line)-1))) { // line too short or long - wrong file format - ELOG("Wrong file format - wrong line length\n"); - res = -1; - break; - } - - // check sum - uint8_t chksum = 0; - for(size_t i = 1; i < l; i += 2) { - chksum += stlink_parse_hex(line + i); - } - if(chksum != 0) { - ELOG("Wrong file format - checksum mismatch\n"); - res = -1; - break; - } - - uint8_t reclen = stlink_parse_hex(line + 1); - if(((uint32_t)reclen + 5)*2 + 1 != l) { - ELOG("Wrong file format - record length mismatch\n"); - res = -1; - break; - } - - uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | ((uint16_t)stlink_parse_hex(line + 5)); - uint8_t rectype = stlink_parse_hex(line + 7); - - switch(rectype) { - case 0: // data - if(scan == 0) { - uint32_t b = lba + offset; - uint32_t e = b + reclen - 1; - if(b < *begin) *begin = b; - if(e > end) end = e; - } - else { - for(size_t i = 0; i < reclen; ++i) { - uint8_t b = stlink_parse_hex(line + 9 + i*2); - uint32_t addr = lba + offset + i; - if(addr >= *begin && addr <= end) { - data[addr - *begin] = b; - } - } - } - break; - - case 1: // EoF - eof_found = true; - break; - - case 2: // Extended Segment Address, unexpected - res = -1; - break; - - case 3: // Start Segment Address, unexpected - res = -1; - break; - - case 4: // Extended Linear Address - if(reclen == 2) { - lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | ((uint32_t)stlink_parse_hex(line + 11) << 16); - } - else { - ELOG("Wrong file format - wrong LBA length\n"); - res = -1; - } - break; - - case 5: // Start Linear Address - expected, but ignore - break; - - default: - ELOG("Wrong file format - unexpected record type %d\n", rectype); - res = -1; - } - if(res != 0) break; - } - - fclose(file); - } - - if(res == 0) { - *mem = data; - } - else { - free(data); - } - - return res; -} - -// FIXME remove -void dumpMem(uint8_t const * mem, size_t len) { - for(size_t i = 0; i < len; ++i) { - if(i > 0 && i % 16 == 0) printf("\n"); - else if(i > 0 && i % 8 == 0) printf(" "); - if(i % 16 == 0) printf("%08zx ", i); - printf("%02x ", mem[i]); - } - printf("\n"); + int res = 0; + *begin = UINT32_MAX; + uint8_t* data = NULL; + uint32_t end = 0; + bool eof_found = false; + + for(int scan = 0; (res == 0) && (scan < 2); ++scan) { // parse file two times - first to find memory range, second - to fill it + if(scan == 1) { + if(!eof_found) { + ELOG("No EoF recond\n"); + res = -1; + break; + } + + if(*begin >= end) { + ELOG("No data found in file\n"); + res = -1; + break; + } + + *size = (end - *begin) + 1; + data = calloc(*size, 1); // use calloc to get NULL if out of memory + if(!data) { + ELOG("Cannot allocate %d bytes\n", *size); + res = -1; + break; + } + + memset(data, erased_pattern, *size); + } + + FILE* file = fopen(path, "r"); + if(!file) { + ELOG("Cannot open file\n"); + res = -1; + break; + } + + uint32_t lba = 0; + + char line[1 + 5*2 + 255*2 + 2]; + while(fgets(line, sizeof(line), file)) { + if(line[0] == '\n' || line[0] == '\r') continue; // skip empty lines + if(line[0] != ':') { // no marker - wrong file format + ELOG("Wrong file format - no marker\n"); + res = -1; + break; + } + + size_t l = strlen(line); + while(l > 0 && (line[l-1] == '\n' || line[l-1] == '\r')) --l; // trim EoL + if((l < 11) || (l == (sizeof(line)-1))) { // line too short or long - wrong file format + ELOG("Wrong file format - wrong line length\n"); + res = -1; + break; + } + + // check sum + uint8_t chksum = 0; + for(size_t i = 1; i < l; i += 2) { + chksum += stlink_parse_hex(line + i); + } + if(chksum != 0) { + ELOG("Wrong file format - checksum mismatch\n"); + res = -1; + break; + } + + uint8_t reclen = stlink_parse_hex(line + 1); + if(((uint32_t)reclen + 5)*2 + 1 != l) { + ELOG("Wrong file format - record length mismatch\n"); + res = -1; + break; + } + + uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | ((uint16_t)stlink_parse_hex(line + 5)); + uint8_t rectype = stlink_parse_hex(line + 7); + + switch(rectype) { + case 0: // data + if(scan == 0) { + uint32_t b = lba + offset; + uint32_t e = b + reclen - 1; + if(b < *begin) *begin = b; + if(e > end) end = e; + } + else { + for(size_t i = 0; i < reclen; ++i) { + uint8_t b = stlink_parse_hex(line + 9 + i*2); + uint32_t addr = lba + offset + i; + if(addr >= *begin && addr <= end) { + data[addr - *begin] = b; + } + } + } + break; + + case 1: // EoF + eof_found = true; + break; + + case 2: // Extended Segment Address, unexpected + res = -1; + break; + + case 3: // Start Segment Address, unexpected + res = -1; + break; + + case 4: // Extended Linear Address + if(reclen == 2) { + lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | ((uint32_t)stlink_parse_hex(line + 11) << 16); + } + else { + ELOG("Wrong file format - wrong LBA length\n"); + res = -1; + } + break; + + case 5: // Start Linear Address - expected, but ignore + break; + + default: + ELOG("Wrong file format - unexpected record type %d\n", rectype); + res = -1; + } + if(res != 0) break; + } + + fclose(file); + } + + if(res == 0) { + *mem = data; + } + else { + free(data); + } + + return res; +} + +static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { + unsigned int val; + /* set stack*/ + stlink_read_debug32(sl, addr, &val); + stlink_write_reg(sl, val, 13); + /* Set PC to the reset routine*/ + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); + stlink_run(sl); +} + +uint8_t stlink_get_erased_pattern(stlink_t *sl) { + if (sl->flash_type == STLINK_FLASH_TYPE_L0) + return 0x00; + else + return 0xff; +} + +int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr) { + /* write the block in flash at addr */ + int err; + unsigned int num_empty, index; + uint8_t erased_pattern = stlink_get_erased_pattern(sl); + + index = (unsigned int)length; + for(num_empty = 0; num_empty != length; ++num_empty) { + if (data[--index] != erased_pattern) { + break; + } + } + /* Round down to words */ + num_empty -= (num_empty & 3); + if(num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); + } + err = stlink_write_flash(sl, addr, data, (num_empty == length) ? (uint32_t) length : (uint32_t) length - num_empty, num_empty == length); + stlink_fwrite_finalize(sl, addr); + return err; } /** @@ -1928,59 +2078,31 @@ void dumpMem(uint8_t const * mem, size_t len) { * @param addr where to start writing * @return 0 on success, -ve on failure. */ -int stlink_fwrite_flash(stlink_t *sl, const char* path, bool is_ihex, stm32_addr_t addr) { +int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ int err; - unsigned int num_empty, index, val; - unsigned char erased_pattern; + unsigned int num_empty, index; + uint8_t erased_pattern = stlink_get_erased_pattern(sl); mapped_file_t mf = MAPPED_FILE_INITIALIZER; - uint8_t * mem; - size_t size; - bool eraseonly = false; - if (sl->flash_type == STLINK_FLASH_TYPE_L0) - erased_pattern = 0x00; - else - erased_pattern = 0xff; - - if(is_ihex) { - uint32_t begin; - if(0 != stlink_parse_ihex(path, 0xFF, &mem, &size, &begin)) - return -1; - addr = begin; - } - else { - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); - return -1; - } - - index = (unsigned int) mf.len; - for(num_empty = 0; num_empty != mf.len; ++num_empty) { - if (mf.base[--index] != erased_pattern) { - break; - } - } - /* Round down to words */ - num_empty -= (num_empty & 3); - if(num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); - } - mem = mf.base; - size = (num_empty == mf.len) ? (uint32_t) mf.len : (uint32_t) mf.len - num_empty; - eraseonly = (num_empty == mf.len); - } - err = stlink_write_flash(sl, addr, mem, size, eraseonly); - /* set stack*/ - stlink_read_debug32(sl, addr, &val); - stlink_write_reg(sl, val, 13); - /* Set PC to the reset routine*/ - stlink_read_debug32(sl, addr + 4, &val); - stlink_write_reg(sl, val, 15); - stlink_run(sl); - if(is_ihex) - free(mem); - else - unmap_file(&mf); + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return -1; + } + + index = (unsigned int) mf.len; + for(num_empty = 0; num_empty != mf.len; ++num_empty) { + if (mf.base[--index] != erased_pattern) { + break; + } + } + /* Round down to words */ + num_empty -= (num_empty & 3); + if(num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); + } + err = stlink_write_flash(sl, addr, mf.base, (num_empty == mf.len) ? (uint32_t) mf.len : (uint32_t) mf.len - num_empty, num_empty == mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); return err; } diff --git a/src/tools/flash.c b/src/tools/flash.c index f26472d45..676606db9 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -10,9 +10,7 @@ #include #include - -#define DEBUG_LOG_LEVEL 100 -#define STND_LOG_LEVEL 50 +#include static stlink_t *connected_stlink = NULL; @@ -27,153 +25,24 @@ static void cleanup(int signal __attribute__((unused))) { exit(1); } -enum st_cmds {DO_WRITE = 0, DO_READ = 1, DO_ERASE = 2}; -struct opts -{ - enum st_cmds cmd; - const char* devname; - char *serial; - const char* filename; - bool is_ihex; - stm32_addr_t addr; - size_t size; - int reset; - int log_level; -}; - static void usage(void) { - puts("stlinkv1 command line: ./st-flash [--debug] [--reset] [--serial ] {read|write} /dev/sgX path addr "); + puts("stlinkv1 command line: ./st-flash [--debug] [--reset] [--format ] {read|write} /dev/sgX "); puts("stlinkv1 command line: ./st-flash [--debug] /dev/sgX erase"); - puts("stlinkv2 command line: ./st-flash [--debug] [--reset] [--serial ] {read|write} path addr "); - puts("stlinkv2 command line: ./st-flash [--debug] [--serial ] erase"); - puts(" use hex format for addr, and "); -} - -static int get_opts(struct opts* o, int ac, char** av) -{ - /* stlinkv1 command line: ./st-flash {read|write} /dev/sgX path addr */ - /* stlinkv2 command line: ./st-flash {read|write} path addr */ - - unsigned int i = 0; - - if (ac < 1) return -1; - - if (strcmp(av[0], "--debug") == 0) - { - o->log_level = DEBUG_LOG_LEVEL; - ac--; - av++; - } - else - { - o->log_level = STND_LOG_LEVEL; - } - - if (strcmp(av[0], "--reset") == 0) - { - o->reset = 1; - ac--; - av++; - } - else - { - o->reset = 0; - } - - if (strcmp(av[0], "--serial") == 0) - { - ac--; - av++; - /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ - int j = (int) strlen(av[0]); - if(j%2 != 0){ - puts("no valid hex value, length must be multiple of 2\n"); - return -1; - } - int k=0; - while(j>=0 && k<=13){ - char buffer[3]={0}; - memcpy(buffer,&av[0][j],2); - o->serial[12-k] = (char)strtol((const char*)buffer,NULL, 16); - k++; - j-=2; - } - ac--; - av++; - } - else - { - o->serial = NULL; - } - - if (ac < 1) return -1; - - /* stlinkv2 */ - o->devname = NULL; - - if (strcmp(av[0], "erase") == 0) - { - o->cmd = DO_ERASE; - - /* stlinkv1 mode */ - if (ac == 2) - { - o->devname = av[1]; - i = 1; - } - } - else { - if (ac < 3) return -1; - if (strcmp(av[0], "read") == 0) - { - o->cmd = DO_READ; - - /* stlinkv1 mode */ - if (ac == 5) - { - o->devname = av[1]; - i = 1; - } - if (ac > 3) - o->size = strtoul(av[i + 3], NULL, 16); - } - else if (strcmp(av[0], "write") == 0) - { - o->cmd = DO_WRITE; - - /* stlinkv1 mode */ - if (ac == 4) - { - o->devname = av[1]; - i = 1; - } - } - else - { - return -1; - } - } - - o->filename = av[i + 1]; - /** @todo This is a little evil as strtoul could return 0 and is of type unsigned long int */ - o->addr = (uint32_t) strtoul(av[i + 2], NULL, 16); - o->is_ihex = (0 == strcmp(".hex", o->filename + (strlen(o->filename) - 4))); // ends with .hex - - return 0; + puts("stlinkv2 command line: ./st-flash [--debug] [--reset] [--serial ] [--format ] {read|write} "); + puts("stlinkv2 command line: ./st-flash [--debug] [--serial ] erase"); + puts(" Use hex format for addr, and ."); + puts(" Format may be 'binary' (default) or 'ihex', although must be specified for binary format only."); } - int main(int ac, char** av) { stlink_t* sl = NULL; - struct opts o; - char serial_buffer[13] = {0}; - o.serial = serial_buffer; + struct flash_opts o; int err = -1; o.size = 0; - if (get_opts(&o, ac - 1, av + 1) == -1) + if (flash_get_opts(&o, ac - 1, av + 1) == -1) { printf("invalid command line\n"); usage(); @@ -183,7 +52,7 @@ int main(int ac, char** av) if (o.devname != NULL) /* stlinkv1 */ sl = stlink_v1_open(o.log_level, 1); else /* stlinkv2 */ - sl = stlink_open_usb(o.log_level, 1, o.serial); + sl = stlink_open_usb(o.log_level, 1, (char *)o.serial); if (sl == NULL) return -1; @@ -244,11 +113,25 @@ int main(int ac, char** av) goto on_error; } - if (o.cmd == DO_WRITE) /* write */ + if (o.cmd == FLASH_CMD_WRITE) /* write */ { + uint8_t * mem = NULL; + size_t size = 0; + + if(o.format == FLASH_FORMAT_IHEX) { + err = stlink_parse_ihex(o.filename, stlink_get_erased_pattern(sl), &mem, &size, &o.addr); + if (err == -1) { + printf("Cannot parse %s as Intel-HEX file\n", o.filename); + goto on_error; + } + } + if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { - err = stlink_fwrite_flash(sl, o.filename, o.is_ihex, o.addr); + if(o.format == FLASH_FORMAT_IHEX) + err = stlink_mwrite_flash(sl, mem, size, o.addr); + else + err = stlink_fwrite_flash(sl, o.filename, o.addr); if (err == -1) { printf("stlink_fwrite_flash() == -1\n"); @@ -264,7 +147,7 @@ int main(int ac, char** av) goto on_error; } } - } else if (o.cmd == DO_ERASE) + } else if (o.cmd == FLASH_CMD_ERASE) { err = stlink_erase_flash_mass(sl); if (err == -1) @@ -281,7 +164,7 @@ int main(int ac, char** av) else if ((o.addr >= sl->sram_base) && (o.size == 0) && (o.addr < sl->sram_base + sl->sram_size)) o.size = sl->sram_size; - err = stlink_fread(sl, o.filename, o.addr, o.size); + err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); if (err == -1) { printf("stlink_fread() == -1\n"); diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c new file mode 100644 index 000000000..7de2ecde8 --- /dev/null +++ b/src/tools/flash_opts.c @@ -0,0 +1,156 @@ +#include + +#include +#include +#include + +static bool starts_with(const char * str, const char * prefix) { + size_t n = strlen(prefix); + if(strlen(str) < n) return false; + + return (0 == strncmp(str, prefix, n)); +} + +int flash_get_opts(struct flash_opts* o, int ac, char** av) +{ + bool serial_specified = false; + + // defaults + + memset(o, 0, sizeof(*o)); + o->log_level = STND_LOG_LEVEL; + + // options + + while(ac >= 1) { + if (strcmp(av[0], "--debug") == 0) { + o->log_level = DEBUG_LOG_LEVEL; + } + else if (strcmp(av[0], "--reset") == 0) { + o->reset = 1; + } + else if (strcmp(av[0], "--serial") == 0 || starts_with(av[0], "--serial=")) { + const char * serial; + if(strcmp(av[0], "--serial") == 0) { + ac--; + av++; + if (ac < 1) return -1; + serial = av[0]; + } + else { + serial = av[0] + strlen("--serial="); + } + + /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ + int j = (int)strlen(serial); + if(j % 2 != 0) return -1; + + for(size_t k = 0; j >= 0 && k < sizeof(o->serial); ++k, j -= 2) { + char buffer[3] = {0}; + memcpy(buffer, serial + j, 2); + o->serial[12 - k] = (uint8_t)strtol(buffer, NULL, 16); + } + + serial_specified = true; + } + else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { + const char * format; + if(strcmp(av[0], "--format") == 0) { + ac--; + av++; + if (ac < 1) return -1; + format = av[0]; + } + else { + format = av[0] + strlen("--format="); + } + + if (strcmp(format, "binary") == 0) + o->format = FLASH_FORMAT_BINARY; + else if (strcmp(format, "ihex") == 0) + o->format = FLASH_FORMAT_IHEX; + else + return -1; + } + else { + break; // non-option found + } + + ac--; + av++; + } + + // command and (optional) device name + + while(ac >= 1) { // looks like for stlinkv1 the device name and command may be swaped - check both positions in all cases + if (strcmp(av[0], "erase") == 0) { + if (o->cmd != FLASH_CMD_NONE) return -1; + o->cmd = FLASH_CMD_ERASE; + } + else if (strcmp(av[0], "read") == 0) { + if (o->cmd != FLASH_CMD_NONE) return -1; + o->cmd = FLASH_CMD_READ; + } + else if (strcmp(av[0], "write") == 0) { + if (o->cmd != FLASH_CMD_NONE) return -1; + o->cmd = FLASH_CMD_WRITE; + } + else if(starts_with(av[0], "/dev/")) { + if (o->devname) return -1; + o->devname = av[0]; + } + else { + break; + } + + ac--; + av++; + } + + char * tail; + switch(o->cmd) { + case FLASH_CMD_NONE: // no command found + return -1; + + case FLASH_CMD_ERASE: // no more arguments expected + if(ac != 0) return -1; + break; + + case FLASH_CMD_READ: // expect filename, addr and size + if (ac != 3) return -1; + + o->filename = av[0]; + o->addr = (uint32_t) strtoul(av[1], &tail, 16); + if(tail[0] != '\0') return -1; + + o->size = strtoul(av[2], &tail, 16); + if(tail[0] != '\0') return -1; + + break; + + case FLASH_CMD_WRITE: + if(o->format == FLASH_FORMAT_BINARY) { // expect filename and addr + if (ac != 2) return -1; + + o->filename = av[0]; + o->addr = (uint32_t) strtoul(av[1], &tail, 16); + if(tail[0] != '\0') return -1; + } + else if(o->format == FLASH_FORMAT_IHEX) { // expect filename + if (ac != 1) return -1; + + o->filename = av[0]; + } + else { + return -1; + } + break; + } + + // some constistence checks + + if(serial_specified && o->devname != NULL) return -1; // serial not supported for v1 + + return 0; +} + diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 5d114a608..94e3fb2c5 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -8,3 +8,8 @@ foreach(test ${TESTS}) add_dependencies(${test} ${PROJECT_NAME}) target_link_libraries(${test} ${PROJECT_NAME}) endforeach() + +add_executable(flash flash.c) +add_dependencies(flash stflash) +target_link_libraries(flash stflash) + diff --git a/tests/flash.c b/tests/flash.c new file mode 100644 index 000000000..4e089f2b8 --- /dev/null +++ b/tests/flash.c @@ -0,0 +1,111 @@ +#include +#include +#include + +#include +#include + +struct Test { + const char * cmd_line; + int res; + struct flash_opts opts; +}; + +static bool cmp_strings(const char * s1, const char * s2) { + if(s1 == NULL || s2 == NULL) return (s1 == s2); + else return (0 == strcmp(s1, s2)); +} + +static bool cmp_mem(const uint8_t * s1, const uint8_t * s2, size_t size) { + if(s1 == NULL || s2 == NULL) return (s1 == s2); + else return (0 == memcmp(s1, s2, size)); +} + +static bool execute_test(const struct Test * test) { + int ac = 0; + char* av[32]; + + // parse (tokenize) the test command line + char cmd_line[strlen(test->cmd_line)]; + strcpy(cmd_line, test->cmd_line); + + for(char * tok = strtok(cmd_line, " "); tok; tok = strtok(NULL, " ")) { + if((size_t)ac >= sizeof(av)/sizeof(av[0])) return false; + + av[ac] = tok; + ++ac; + } + + // call + struct flash_opts opts; + int res = flash_get_opts(&opts, ac, av); + + // compare results + bool ret = (res == test->res); + + if(ret && (res == 0)) { + ret &= (opts.cmd == test->opts.cmd); + ret &= cmp_strings(opts.devname, test->opts.devname); + ret &= cmp_mem(opts.serial, test->opts.serial, sizeof(opts.serial)); + ret &= cmp_strings(opts.filename, test->opts.filename); + ret &= (opts.addr == test->opts.addr); + ret &= (opts.size == test->opts.size); + ret &= (opts.reset == test->opts.reset); + ret &= (opts.log_level == test->opts.log_level); + ret &= (opts.format == test->opts.format); + } + + printf("[%s] (%d) %s\n", ret ? "OK" : "ERROR", res, test->cmd_line); + return ret; +} + +struct Test tests[] = { + { "", -1, + {} }, + { "--debug --reset read /dev/sg0 test.bin 0x80000000 0x1000", 0, + { .cmd = FLASH_CMD_READ, .devname = "/dev/sg0", .serial = {}, .filename = "test.bin", + .addr = 0x80000000, .size = 0x1000, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { "--debug --reset write /dev/sg0 test.bin 0x80000000", 0, + { .cmd = FLASH_CMD_WRITE, .devname = "/dev/sg0", .serial = {}, .filename = "test.bin", + .addr = 0x80000000, .size = 0, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { "--serial A1020304 /dev/sg0 erase", -1, + {} }, + { "/dev/sg0 erase", 0, + { .cmd = FLASH_CMD_ERASE, .devname = "/dev/sg0", .serial = {}, .filename = NULL, + .addr = 0, .size = 0, .reset = 0, .log_level = STND_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { "--debug --reset read test.bin 0x80000000 0x1000", 0, + { .cmd = FLASH_CMD_READ, .devname = NULL, .serial = {}, .filename = "test.bin", + .addr = 0x80000000, .size = 0x1000, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { "--debug --reset write test.bin 0x80000000", 0, + { .cmd = FLASH_CMD_WRITE, .devname = NULL, .serial = {}, .filename = "test.bin", + .addr = 0x80000000, .size = 0, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { "erase", 0, + { .cmd = FLASH_CMD_ERASE, .devname = NULL, .serial = {}, .filename = NULL, + .addr = 0, .size = 0, .reset = 0, .log_level = STND_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { "--debug --reset --format=ihex write test.hex", 0, + { .cmd = FLASH_CMD_WRITE, .devname = NULL, .serial = {}, .filename = "test.hex", + .addr = 0, .size = 0, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_IHEX } }, + { "--debug --reset --format=binary write test.hex", -1, + {} }, + { "--debug --reset --format=ihex write test.hex 0x80000000", -1, + {} }, + { "--debug --reset write test.hex sometext", -1, + {} }, + { "--serial A1020304 erase", 0, + { .cmd = FLASH_CMD_ERASE, .devname = NULL, .serial = "\0\0\0\0\0\0\0\0\xA1\x02\x03\x04", .filename = NULL, + .addr = 0, .size = 0, .reset = 0, .log_level = STND_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { "--serial=A1020304 erase", 0, + { .cmd = FLASH_CMD_ERASE, .devname = NULL, .serial = "\0\0\0\0\0\0\0\0\xA1\x02\x03\x04", .filename = NULL, + .addr = 0, .size = 0, .reset = 0, .log_level = STND_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, +}; + +int main() +{ + bool allOk = true; + for(size_t i = 0; i < sizeof(tests)/sizeof(tests[0]); ++i) { + if(!execute_test(&tests[i])) allOk = false; + } + + return (allOk ? 0 : 1); +} + From 6c80b8c6b652291d5ddd04c98782fc4a7b0b5b04 Mon Sep 17 00:00:00 2001 From: Anatoli Date: Tue, 6 Sep 2016 23:09:41 +0200 Subject: [PATCH 0465/1435] add write ihex to RAM --- include/stlink.h | 1 + src/common.c | 92 +++++++++++++++++++++++++++++++++++------------ src/tools/flash.c | 13 +++++-- 3 files changed, 82 insertions(+), 24 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index 5151cc166..0f032614e 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -184,6 +184,7 @@ typedef struct flash_loader { uint8_t stlink_get_erased_pattern(stlink_t *sl); int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); + int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); diff --git a/src/common.c b/src/common.c index 51c92bac3..24944132f 100644 --- a/src/common.c +++ b/src/common.c @@ -1017,16 +1017,81 @@ static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) { return 0; } -int stlink_fwrite_sram -(stlink_t * sl, const char* path, stm32_addr_t addr) { +static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { + unsigned int val; + /* set stack*/ + stlink_read_debug32(sl, addr, &val); + stlink_write_reg(sl, val, 13); + /* Set PC to the reset routine*/ + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); + stlink_run(sl); +} + +int stlink_mwrite_sram(stlink_t * sl, uint8_t* data, uint32_t length, stm32_addr_t addr) { /* write the file in sram at addr */ int error = -1; size_t off; size_t len; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - uint32_t val; + /* check addr range is inside the sram */ + if (addr < sl->sram_base) { + fprintf(stderr, "addr too low\n"); + goto on_error; + } else if ((addr + length) < addr) { + fprintf(stderr, "addr overruns\n"); + goto on_error; + } else if ((addr + length) > (sl->sram_base + sl->sram_size)) { + fprintf(stderr, "addr too high\n"); + goto on_error; + } else if (addr & 3) { + /* todo */ + fprintf(stderr, "unaligned addr\n"); + goto on_error; + } + + len = length; + + if(len & 3) { + len -= len & 3; + } + + /* do the copy by 1k blocks */ + for (off = 0; off < len; off += 1024) { + size_t size = 1024; + if ((off + size) > len) + size = len - off; + + memcpy(sl->q_buf, data + off, size); + + /* round size if needed */ + if (size & 3) + size += 2; + + stlink_write_mem32(sl, addr + (uint32_t) off, size); + } + + if(length > len) { + memcpy(sl->q_buf, data + len, length - len); + stlink_write_mem8(sl, addr + (uint32_t) len, length - len); + } + + /* success */ + error = 0; + stlink_fwrite_finalize(sl, addr); + +on_error: + return error; +} + +int stlink_fwrite_sram(stlink_t * sl, const char* path, stm32_addr_t addr) { + /* write the file in sram at addr */ + + int error = -1; + size_t off; + size_t len; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { fprintf(stderr, "map_file() == -1\n"); @@ -1083,13 +1148,7 @@ int stlink_fwrite_sram /* success */ error = 0; - /* set stack*/ - stlink_read_debug32(sl, addr, &val); - stlink_write_reg(sl, val, 13); - /* Set PC to the reset routine*/ - stlink_read_debug32(sl, addr + 4, &val); - stlink_write_reg(sl, val, 15); - stlink_run(sl); + stlink_fwrite_finalize(sl, addr); on_error: unmap_file(&mf); @@ -2031,17 +2090,6 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, return res; } -static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { - unsigned int val; - /* set stack*/ - stlink_read_debug32(sl, addr, &val); - stlink_write_reg(sl, val, 13); - /* Set PC to the reset routine*/ - stlink_read_debug32(sl, addr + 4, &val); - stlink_write_reg(sl, val, 15); - stlink_run(sl); -} - uint8_t stlink_get_erased_pattern(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_L0) return 0x00; diff --git a/src/tools/flash.c b/src/tools/flash.c index 676606db9..d619e63a1 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -40,6 +40,7 @@ int main(int ac, char** av) stlink_t* sl = NULL; struct flash_opts o; int err = -1; + uint8_t * mem = NULL; o.size = 0; if (flash_get_opts(&o, ac - 1, av + 1) == -1) @@ -115,7 +116,6 @@ int main(int ac, char** av) if (o.cmd == FLASH_CMD_WRITE) /* write */ { - uint8_t * mem = NULL; size_t size = 0; if(o.format == FLASH_FORMAT_IHEX) { @@ -140,13 +140,21 @@ int main(int ac, char** av) } else if ((o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { - err = stlink_fwrite_sram(sl, o.filename, o.addr); + if(o.format == FLASH_FORMAT_IHEX) + err = stlink_mwrite_sram(sl, mem, size, o.addr); + else + err = stlink_fwrite_sram(sl, o.filename, o.addr); if (err == -1) { printf("stlink_fwrite_sram() == -1\n"); goto on_error; } } + else { + err = -1; + printf("Unknown memory region\n"); + goto on_error; + } } else if (o.cmd == FLASH_CMD_ERASE) { err = stlink_erase_flash_mass(sl); @@ -183,6 +191,7 @@ int main(int ac, char** av) on_error: stlink_exit_debug_mode(sl); stlink_close(sl); + free(mem); return err; } From 21c970f1391830b8e3176330bb8dd32f8bd55ab9 Mon Sep 17 00:00:00 2001 From: "fabien.lementec" Date: Wed, 7 Sep 2016 07:06:43 +0200 Subject: [PATCH 0466/1435] warning, add FLASH_OPTS_INITIALIZER --- include/stlink/tools/flash.h | 4 ++++ tests/flash.c | 15 +++++---------- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index 10e6ffac4..dbc9ad881 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -22,6 +22,10 @@ struct flash_opts enum flash_format format; }; + +#define FLASH_OPTS_INITIALIZER {0, } + + int flash_get_opts(struct flash_opts* o, int ac, char** av); #endif // STLINK_FLASH_H_ diff --git a/tests/flash.c b/tests/flash.c index 4e089f2b8..27fd437f6 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -60,16 +60,14 @@ static bool execute_test(const struct Test * test) { } struct Test tests[] = { - { "", -1, - {} }, + { "", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset read /dev/sg0 test.bin 0x80000000 0x1000", 0, { .cmd = FLASH_CMD_READ, .devname = "/dev/sg0", .serial = {}, .filename = "test.bin", .addr = 0x80000000, .size = 0x1000, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, { "--debug --reset write /dev/sg0 test.bin 0x80000000", 0, { .cmd = FLASH_CMD_WRITE, .devname = "/dev/sg0", .serial = {}, .filename = "test.bin", .addr = 0x80000000, .size = 0, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, - { "--serial A1020304 /dev/sg0 erase", -1, - {} }, + { "--serial A1020304 /dev/sg0 erase", -1, FLASH_OPTS_INITIALIZER }, { "/dev/sg0 erase", 0, { .cmd = FLASH_CMD_ERASE, .devname = "/dev/sg0", .serial = {}, .filename = NULL, .addr = 0, .size = 0, .reset = 0, .log_level = STND_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, @@ -85,12 +83,9 @@ struct Test tests[] = { { "--debug --reset --format=ihex write test.hex", 0, { .cmd = FLASH_CMD_WRITE, .devname = NULL, .serial = {}, .filename = "test.hex", .addr = 0, .size = 0, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_IHEX } }, - { "--debug --reset --format=binary write test.hex", -1, - {} }, - { "--debug --reset --format=ihex write test.hex 0x80000000", -1, - {} }, - { "--debug --reset write test.hex sometext", -1, - {} }, + { "--debug --reset --format=binary write test.hex", -1, FLASH_OPTS_INITIALIZER }, + { "--debug --reset --format=ihex write test.hex 0x80000000", -1, FLASH_OPTS_INITIALIZER }, + { "--debug --reset write test.hex sometext", -1, FLASH_OPTS_INITIALIZER }, { "--serial A1020304 erase", 0, { .cmd = FLASH_CMD_ERASE, .devname = NULL, .serial = "\0\0\0\0\0\0\0\0\xA1\x02\x03\x04", .filename = NULL, .addr = 0, .size = 0, .reset = 0, .log_level = STND_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, From 1cffc453c5b9316251027da24542bf9493f6629c Mon Sep 17 00:00:00 2001 From: Christophe Levantis Date: Wed, 7 Sep 2016 11:11:45 +0100 Subject: [PATCH 0467/1435] Add memory map for stm32f401xe Trying to load a elf image on a stm32f401xe can result in a problem of flash write if a section does not start on a flash sector because the memory map given to gdb was wrong. --- src/gdbserver/gdb-server.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 15f837908..f99f3e7ce 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -433,6 +433,30 @@ static const char* const memory_map_template_F7 = " " // option byte area ""; + +static const char* const memory_map_template_F4_DE = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // sram + " " //Sectors 0..3 + " 0x4000" //16kB + " " + " " //Sector 4 + " 0x10000" //64kB + " " + " " //Sectors 5..7 + " 0x20000" //128kB + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // otp + " " // option byte area + ""; + char* make_memory_map(stlink_t *sl) { /* This will be freed in serve() */ const size_t sz = 4096; @@ -441,6 +465,8 @@ char* make_memory_map(stlink_t *sl) { if(sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F446) { strcpy(map, memory_map_template_F4); + } else if(sl->chip_id==STLINK_CHIPID_STM32_F4_DE) { + strcpy(map, memory_map_template_F4_DE); } else if(sl->core_id==STM32F7_CORE_ID) { snprintf(map, sz, memory_map_template_F7, sl->sram_size); From fca819f8f99b922f189a7c58075188d50a463725 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 8 Sep 2016 16:16:39 +0200 Subject: [PATCH 0468/1435] cmake/modules/FindLibUSB.cmake: Fix build on FreeBSD --- cmake/modules/FindLibUSB.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index 99e872c3e..ecf3cd25b 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -31,7 +31,7 @@ find_path(LIBUSB_INCLUDE_DIR NAMES libusb.h /usr/local /opt ${LIBUSB_WIN_OUTPUT_FOLDER}/include - PATH_SUFFIXES libusb-1.0 +# PATH_SUFFIXES libusb-1.0 ) if (APPLE) @@ -41,7 +41,7 @@ elseif(MSYS OR MINGW) elseif(WIN32) set(LIBUSB_NAME libusb-1.0.lib) else() - set(LIBUSB_NAME usb-1.0) + set(LIBUSB_NAME usb) endif() if (MSYS OR MINGW) From 4ad75ead7808a4275b4112f33344be91b565fc5b Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 8 Sep 2016 14:31:08 +0200 Subject: [PATCH 0469/1435] cmake/modules/FindLibUSB.cmake: Use correct FindLibUSB.cmake --- cmake/modules/FindLibUSB.cmake | 61 ++++++++++++++++++++++------------ 1 file changed, 39 insertions(+), 22 deletions(-) diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index ecf3cd25b..3b15339e4 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -1,4 +1,4 @@ -# FindLibUSB.cmake - Try to find the Hiredis library +# FindLibUSB.cmake # Once done this will define # # LIBUSB_FOUND - System has libusb @@ -6,42 +6,51 @@ # LIBUSB_LIBRARY - The libraries needed to use libusb # LIBUSB_DEFINITIONS - Compiler switches required for using libusb -if(WIN32 OR MINGW OR MSYS) - set(LIBUSB_WIN_VERSION "1.0.20") +if(WIN32 OR CMAKE_VS_PLATFORM_NAME) + set(LIBUSB_WIN_VERSION 1.0.20) set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) - set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/libusb-${LIBUSB_WIN_VERSION}) + set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/3thparty/libusb-${LIBUSB_WIN_VERSION}) - if (EXISTS ${LIBUSB_WIN_ARCHIVE_PATH}) + if(EXISTS ${LIBUSB_WIN_ARCHIVE_PATH}) message(STATUS "libusb archive already in build folder") - else () - message(STATUS "libusb downloading ${LIBUSB_WIN_VERSION}") + else() + message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download ${LIBUSB_WIN_ARCHIVE_PATH} - SHOW_PROGRESS) - endif () - + ) + endif() execute_process(COMMAND ${ZIP_LOCATION} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o${LIBUSB_WIN_OUTPUT_FOLDER}) endif() -find_path(LIBUSB_INCLUDE_DIR NAMES libusb.h +# FreeBSD +if (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") + FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h + HINTS + /usr/include + ) +else () + FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr /usr/local /opt ${LIBUSB_WIN_OUTPUT_FOLDER}/include -# PATH_SUFFIXES libusb-1.0 -) + PATH_SUFFIXES libusb-1.0 + ) +endif() + +message(STATUS "LIBUSB_INCLUDE_DIR: ${LIBUSB_INCLUDE_DIR}") if (APPLE) set(LIBUSB_NAME libusb-1.0.a) -elseif(MSYS OR MINGW) - set(LIBUSB_NAME usb-1.0) -elseif(WIN32) +elseif(WIN32 OR CMAKE_VS_PLATFORM_NAME) set(LIBUSB_NAME libusb-1.0.lib) -else() +elseif(CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") set(LIBUSB_NAME usb) +else() + set(LIBUSB_NAME usb-1.0) endif() if (MSYS OR MINGW) @@ -52,12 +61,20 @@ if (MSYS OR MINGW) find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW32/static) endif () -else () +elseif(CMAKE_VS_PLATFORM_NAME) + if (CMAKE_SIZEOF_VOID_P EQUAL 8) + find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS64/static) + else () + find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS32/static) + endif () +else() find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS - /usr - /usr/local - /opt) + HINTS + /usr + /usr/local + /opt) endif () include(FindPackageHandleStandardArgs) From bd5dd332232bd451b8fbe728a70434dac5a4d0f9 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 8 Sep 2016 16:32:32 +0200 Subject: [PATCH 0470/1435] tests: Enable make test with CTest using add_test. Remove unnecessary library building for st-flash arg parser --- CMakeLists.txt | 6 ++---- tests/CMakeLists.txt | 8 ++++---- tests/sg.c | 12 +++--------- 3 files changed, 9 insertions(+), 17 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index fcaf9ec94..c321cc48b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -179,11 +179,9 @@ if (APPLE) target_link_libraries(${PROJECT_NAME} ${CoreFoundation} ${IOKit} ${ObjC}) endif () -add_library(stflash STATIC - src/tools/flash_opts.c) target_link_libraries(${PROJECT_NAME} ${LIBUSB_LIBRARY}) -add_executable(st-flash src/tools/flash.c) -target_link_libraries(st-flash ${PROJECT_NAME} stflash) +add_executable(st-flash src/tools/flash.c src/tools/flash_opts.c) +target_link_libraries(st-flash ${PROJECT_NAME}) add_executable(st-info src/tools/info.c) target_link_libraries(st-info ${PROJECT_NAME}) diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 94e3fb2c5..fc51433bd 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -7,9 +7,9 @@ foreach(test ${TESTS}) add_executable(${test} ${test}.c) add_dependencies(${test} ${PROJECT_NAME}) target_link_libraries(${test} ${PROJECT_NAME}) + add_test(${test} ${CMAKE_CURRENT_BINARY_DIR}/${test}) endforeach() -add_executable(flash flash.c) -add_dependencies(flash stflash) -target_link_libraries(flash stflash) - +add_executable(flash flash.c "${CMAKE_SOURCE_DIR}/src/tools/flash_opts.c") +target_link_libraries(flash ${PROJECT_NAME}) +add_test(flash ${CMAKE_CURRENT_BINARY_DIR}/flash) diff --git a/tests/sg.c b/tests/sg.c index d12f6ba43..5426b6ff3 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -25,13 +25,11 @@ static void __attribute__((unused)) mark_buf(stlink_t *sl) { } -int main(int argc, char *argv[]) { +int main(void) +{ /* Avoid unused parameter warning */ - (void)argv; // set scpi lib debug level: 0 for no debug info, 10 for lots - switch (argc) { - case 1: fputs( "\nUsage: stlink-access-test [anything at all] ...\n" "\n*** Notice: The stlink firmware violates the USB standard.\n" @@ -40,14 +38,10 @@ int main(int argc, char *argv[]) { "*** Unplug the stlink and execute once as root:\n" "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n", stderr); - return EXIT_FAILURE; - default: - break; - } stlink_t *sl = stlink_v1_open(99, 1); if (sl == NULL) - return EXIT_FAILURE; + return 0; // we are in mass mode, go to swd stlink_enter_swd_mode(sl); From cc1cb00d734e4581cd142c6f0a781d6789a9eab6 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 8 Sep 2016 17:07:09 +0200 Subject: [PATCH 0471/1435] Fix variable shadow warnings (brk, signal). Disable redundant-decl flag on OpenBSD --- CMakeLists.txt | 16 +++++++++++++--- src/common.c | 14 +++++++------- src/gdbserver/gdb-server.c | 35 ++++++++++++++++++----------------- src/tools/flash.c | 4 +++- src/tools/term.c | 6 +++--- 5 files changed, 44 insertions(+), 31 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index c321cc48b..b8c13b261 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -14,6 +14,8 @@ endif () set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") +message(STATUS "Building on ${CMAKE_SYSTEM_NAME}") + # Determine package version. find_package (Git QUIET) if (DEFINED ENV{TRAVIS_TAG} AND NOT "$ENV{TRAVIS_TAG}" STREQUAL "") @@ -95,7 +97,16 @@ add_cflag_if_supported("-Wmaybe-uninitialized") add_cflag_if_supported("-Wmissing-variable-declarations") add_cflag_if_supported("-Wshorten-64-to-32") add_cflag_if_supported("-Wimplicit-function-declaration") -add_cflag_if_supported("-Wredundant-decls") + +## +# On OpenBSD the system headers suck so we need to disable redundant declaration check +# /usr/include/unistd.h:429: warning: redundant redeclaration of 'truncate' +# /usr/include/sys/types.h:218: warning: previous declaration of 'truncate' was here +## +if (NOT CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") + add_cflag_if_supported("-Wredundant-decls") +endif () + add_cflag_if_supported("-Wundef") if (NOT MSYS OR MINGW) add_cflag_if_supported("-fPIC") @@ -106,10 +117,9 @@ if (CMAKE_BUILD_TYPE STREQUAL "") endif () if(${CMAKE_BUILD_TYPE} MATCHES "Debug") - include(CTest) add_cflag_if_supported("-ggdb") add_cflag_if_supported("-O0") - #set (STLINK_PACKAGE_VERSION "${STLINK_PACKAGE_VERSION}-debug") + include(CTest) elseif() add_cflag_if_supported("-O2") endif() diff --git a/src/common.c b/src/common.c index 24944132f..74fa1043e 100644 --- a/src/common.c +++ b/src/common.c @@ -871,7 +871,7 @@ int stlink_current_mode(stlink_t *sl) { // const int i = 1; // #define is_bigendian() ( (*(char*)&i) == 0 ) -inline unsigned int is_bigendian(void) { +unsigned int is_bigendian(void) { static volatile const unsigned int i = 1; return *(volatile const char*) &i == 0; } @@ -2100,12 +2100,12 @@ uint8_t stlink_get_erased_pattern(stlink_t *sl) { int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr) { /* write the block in flash at addr */ int err; - unsigned int num_empty, index; + unsigned int num_empty, idx; uint8_t erased_pattern = stlink_get_erased_pattern(sl); - index = (unsigned int)length; + idx = (unsigned int)length; for(num_empty = 0; num_empty != length; ++num_empty) { - if (data[--index] != erased_pattern) { + if (data[--idx] != erased_pattern) { break; } } @@ -2129,7 +2129,7 @@ int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ int err; - unsigned int num_empty, index; + unsigned int num_empty, idx; uint8_t erased_pattern = stlink_get_erased_pattern(sl); mapped_file_t mf = MAPPED_FILE_INITIALIZER; @@ -2138,9 +2138,9 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { return -1; } - index = (unsigned int) mf.len; + idx = (unsigned int) mf.len; for(num_empty = 0; num_empty != mf.len; ++num_empty) { - if (mf.base[--index] != erased_pattern) { + if (mf.base[--idx] != erased_pattern) { break; } } diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index f99f3e7ce..4d52d0cba 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -3,7 +3,7 @@ * Use of this source code is governed by a BSD-style * license that can be found in the LICENSE file. */ - +#include #include #include #include @@ -55,7 +55,9 @@ int serve(stlink_t *sl, st_state_t *st); char* make_memory_map(stlink_t *sl); static void init_cache (stlink_t *sl); -static void cleanup(int signal __attribute__((unused))) { +static void cleanup(int signum) { + (void)signum; + if (connected_stlink) { /* Switch back to mass storage mode before closing. */ stlink_run(connected_stlink); @@ -670,29 +672,29 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { else return 0; // Breakpoint is already removed } - struct code_hw_breakpoint* brk = &code_breaks[id]; + struct code_hw_breakpoint* bp = &code_breaks[id]; - brk->addr = fpb_addr; + bp->addr = fpb_addr; if (sl->core_id==STM32F7_CORE_ID) { - if(set) brk->type = type; - else brk->type = 0; + if(set) bp->type = type; + else bp->type = 0; - mask = (brk->addr) | 1; + mask = (bp->addr) | 1; } else { - if(set) brk->type |= type; - else brk->type &= ~type; + if(set) bp->type |= type; + else bp->type &= ~type; - mask = (brk->addr) | 1 | (brk->type << 30); + mask = (bp->addr) | 1 | (bp->type << 30); } - if(brk->type == 0) { + if(bp->type == 0) { DLOG("clearing hw break %d\n", id); stlink_write_debug32(sl, 0xe0002008 + id * 4, 0); } else { DLOG("setting hw break %d at %08x (%d)\n", - id, brk->addr, brk->type); + id, bp->addr, bp->type); DLOG("reg %08x \n", mask); @@ -795,12 +797,11 @@ static int flash_go(stlink_t *sl) { stlink_calculate_pagesize(sl, page); DLOG("flash_do: page %08x\n", page); - unsigned send = (length > FLASH_PAGE) ? (unsigned) FLASH_PAGE : length; - if(stlink_write_flash(sl, page, fb->data + (page - fb->addr), - send, 0) < 0) + unsigned len = (length > FLASH_PAGE) ? (unsigned) FLASH_PAGE : length; + int ret = stlink_write_flash(sl, page, fb->data + (page - fb->addr), len, 0); + if (ret < 0) goto error; - length -= send; - + length -= len; } } diff --git a/src/tools/flash.c b/src/tools/flash.c index d619e63a1..2dde37d06 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -14,7 +14,9 @@ static stlink_t *connected_stlink = NULL; -static void cleanup(int signal __attribute__((unused))) { +static void cleanup(int signum) { + (void)signum; + if (connected_stlink) { /* Switch back to mass storage mode before closing. */ stlink_run(connected_stlink); diff --git a/src/tools/term.c b/src/tools/term.c index 3f3517f9e..ffbbb1a9f 100644 --- a/src/tools/term.c +++ b/src/tools/term.c @@ -1,10 +1,8 @@ #include #include -/* According to POSIX.1-2001 */ #include #include #include -#include #include #include #include @@ -52,7 +50,9 @@ struct stlinky { void nonblock(int state); -static void cleanup(int signal __attribute__((unused))) { +static void cleanup(int signum) { + (void)signum; + if (gsl) { /* Switch back to mass storage mode before closing. */ stlink_run(gsl); From 1d19a84b5fe2ba816e8671fd2ddc12ef71a78d0b Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 8 Sep 2016 15:25:24 +0200 Subject: [PATCH 0472/1435] Update README.md Add jenkins.ncrmnt.org build badge status --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index d9388c12e..3671fbf3f 100644 --- a/README.md +++ b/README.md @@ -4,6 +4,7 @@ Open source version of the STMicroelectronics Stlink Tools [![GitHub release](https://img.shields.io/github/release/texane/stlink.svg?maxAge=2592000)](https://github.com/texane/stlink/releases/latest) [![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.2.0.svg?maxAge=2592000)](https://github.com/texane/stlink/compare/1.2.0...master) [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) +[![Build Status](https://jenkins.ncrmnt.org/buildStatus/icon?job=GithubCI/stlink)](https://jenkins.ncrmnt.org/job/GithubCI/stlink) [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) ## HOWTO From 3fd0f099782506532198473b24f643a3f68d5ff9 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 8 Sep 2016 15:43:27 +0200 Subject: [PATCH 0473/1435] Remove hacky st-term (which needed special undocumented firmware from https://github.com/nekromant/antares/tree/master/src/lib/stlinky ) as we now have arm semihosting with a well defined interface --- CMakeLists.txt | 9 -- src/tools/term.c | 322 ----------------------------------------------- 2 files changed, 331 deletions(-) delete mode 100644 src/tools/term.c diff --git a/CMakeLists.txt b/CMakeLists.txt index b8c13b261..24c4f51d1 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -251,15 +251,6 @@ if (NOT APPLE AND NOT WIN32) DESTINATION lib/${CMAKE_LIBRARY_PATH}/pkgconfig/) endif() -if(NOT MINGW) - list(APPEND STLINK_SOURCE src/tools/term.c) - add_executable(st-term src/tools/term.c) - target_link_libraries(st-term ${PROJECT_NAME}) - - install(TARGETS st-term - RUNTIME DESTINATION bin) -endif() - if (NOT APPLE AND gtk_FOUND) include_directories(SYSTEM ${gtk_INCLUDE_DIRS}) set(GUI_SOURCES src/tools/gui/stlink-gui.c diff --git a/src/tools/term.c b/src/tools/term.c deleted file mode 100644 index ffbbb1a9f..000000000 --- a/src/tools/term.c +++ /dev/null @@ -1,322 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -/* STLinky structure on STM chip - -struct stlinky { - uint32_t magic; - uint32_t bufsize; - uint32_t up_tail; - uint32_t up_head; - uint32_t dw_tail; - uint32_t dw_head; - char upbuf[CONFIG_LIB_STLINKY_BSIZE]; - char dwbuf[CONFIG_LIB_STLINKY_BSIZE]; -} __attribute__ ((packed)); -*/ - - -#define STLINKY_MAGIC 0xDEADF00D - -#define ST_TERM_MAX_BUFF_SIZE (1024*1024) //1Mb - -#define RX_Q_OFFSET 8 -#define RX_BUFF_OFFSET 24 -#define TX_Q_OFFSET 16 -#define TX_BUFF_OFFSET(bufsize) (24 + bufsize) - -#define READ_UINT32_LE(buf) ((uint32_t) ( buf[0] \ - | buf[1] << 8 \ - | buf[2] << 16 \ - | buf[3] << 24)) - -static stlink_t* gsl; -static sigset_t sig_mask; - -struct stlinky { - stlink_t *sl; - uint32_t off; - size_t bufsize; -}; - -void nonblock(int state); - -static void cleanup(int signum) { - (void)signum; - - if (gsl) { - /* Switch back to mass storage mode before closing. */ - stlink_run(gsl); - stlink_exit_debug_mode(gsl); - stlink_close(gsl); - } - - printf("\n"); - nonblock(0); - exit(1); -} - -void sig_init() { - sigemptyset(&sig_mask); - sigaddset(&sig_mask, SIGINT); - sigaddset(&sig_mask, SIGTERM); - signal(SIGINT, &cleanup); - signal(SIGTERM, &cleanup); - sigprocmask(SIG_BLOCK, &sig_mask, NULL); -} - -void sig_process() { - sigset_t pending; - sigpending(&pending); - if (sigismember(&pending, SIGINT) || sigismember(&pending, SIGTERM)) { - sigprocmask(SIG_UNBLOCK, &sig_mask, NULL); - sigsuspend(&pending); - sigprocmask(SIG_BLOCK, &sig_mask, NULL); - } -} - -/* Detects stlinky in RAM, returns handler */ -struct stlinky* stlinky_detect(stlink_t* sl) -{ - static const uint32_t sram_base = 0x20000000; - struct stlinky* st = malloc(sizeof(struct stlinky)); - int multiple=0; - st->sl = sl; - printf("sram: 0x%x bytes @ 0x%zx\n", sl->sram_base, sl->sram_size); - uint32_t off; - for (off = 0; off < sl->sram_size; off += 4) { - if (off % 1024 == 0) sig_process(); - stlink_read_mem32(sl, sram_base + off, 4); - if (STLINKY_MAGIC == READ_UINT32_LE(sl->q_buf)) - { - if (multiple > 0) printf("WARNING: another "); - printf("stlinky detected at 0x%x\n", sram_base + off); - st->off = sram_base + off; - stlink_read_mem32(sl, st->off + 4, 4); - st->bufsize = READ_UINT32_LE(sl->q_buf); - printf("stlinky buffer size 0x%u \n", (unsigned int)st->bufsize); - multiple++; - } - } - if (multiple > 0) { - if (multiple > 1) { - printf("Using last stlinky structure detected\n"); - } - return st; - } - return NULL; -} - -static void stlinky_read_buff(struct stlinky *st, uint32_t off, uint32_t size, char *buffer) -{ - int aligned_size; - - if (size == 0) - return; - - //Read from device with 4-byte alignment - aligned_size = (size & 0xFFFFFFFC) + 8; - stlink_read_mem32(st->sl, off & 0xFFFFFFFC, aligned_size); - - //copy to local buffer - memcpy(buffer, st->sl->q_buf + (off & 0x3), size); - - return; -} - -static void stlinky_write_buf(struct stlinky *st, uint32_t off, uint32_t size, char *buffer) -{ - memcpy(st->sl->q_buf, buffer, size); - stlink_write_mem8(st->sl, off, size); - return; -} - -size_t stlinky_rx(struct stlinky *st, char* buffer) -{ - //read head and tail values - uint32_t tail, head; - stlink_read_mem32(st->sl, st->off + RX_Q_OFFSET, sizeof(tail) + sizeof(head)); - memcpy(&tail, &st->sl->q_buf[0], sizeof(tail)); - memcpy(&head, &st->sl->q_buf[sizeof(tail)], sizeof(head)); - - //return if empty - if(head == tail) - return 0; - - //read data - int size_read = 0; - if(head > tail){ - stlinky_read_buff(st, st->off + RX_BUFF_OFFSET + tail, head - tail, buffer); - size_read += head - tail; - } else if(head < tail){ - stlinky_read_buff(st, st->off + RX_BUFF_OFFSET + tail, (uint32_t) st->bufsize - tail, buffer); - size_read += st->bufsize - tail; - - stlinky_read_buff(st, st->off + RX_BUFF_OFFSET, head, buffer + size_read); - size_read += head; - } - - //move tail - tail = (tail + size_read) % st->bufsize; - - //write tail - memcpy(st->sl->q_buf, &tail, sizeof(tail)); - stlink_write_mem32(st->sl, st->off + RX_Q_OFFSET, sizeof(tail)); - - return size_read; -} - -size_t stlinky_tx(struct stlinky *st, char* buffer, size_t siz) -{ - //read head and tail values - uint32_t tail, head; - stlink_read_mem32(st->sl, st->off + TX_Q_OFFSET, sizeof(tail) + sizeof(head)); - memcpy(&tail, &st->sl->q_buf[0], sizeof(tail)); - memcpy(&head, &st->sl->q_buf[sizeof(tail)], sizeof(head)); - - //Figure out buffer usage - int usage = head - tail; - if (usage < 0) - usage += st->bufsize; - - //check if new data will fit - if (usage + siz >= st->bufsize) - return 0; - - //copy in data (take care of possible split) - int first_chunk = (head + siz >= st->bufsize) ? (int) st->bufsize - (int) head : (int) siz; - int second_chunk = (int) siz - first_chunk; - - //copy data - stlinky_write_buf(st, st->off + (uint32_t) TX_BUFF_OFFSET(st->bufsize) + head, first_chunk, buffer); - if (second_chunk > 0) - stlinky_write_buf(st, st->off + (uint32_t) TX_BUFF_OFFSET(st->bufsize), - second_chunk, buffer + first_chunk); - - //increment head pointer - head = (head + siz) % (uint32_t) st->bufsize; - memcpy(st->sl->q_buf, &head, sizeof(head)); - stlink_write_mem32(st->sl, st->off + TX_Q_OFFSET + sizeof(tail), sizeof(head)); - - return siz; -} - -int kbhit() -{ - struct timeval tv; - fd_set fds; - tv.tv_sec = 0; - tv.tv_usec = 0; - FD_ZERO(&fds); - FD_SET(STDIN_FILENO, &fds); //STDIN_FILENO is 0 - select(STDIN_FILENO+1, &fds, NULL, NULL, &tv); - return FD_ISSET(STDIN_FILENO, &fds); -} - -void nonblock(int state) -{ - struct termios ttystate; - - //get the terminal state - tcgetattr(STDIN_FILENO, &ttystate); - - if (state==1) - { - //turn off canonical mode - ttystate.c_lflag &= ~ICANON; - ttystate.c_lflag &= ~ECHO; - //minimum of number input read. - ttystate.c_cc[VMIN] = 1; - } - else if (state==0) - { - //turn on canonical mode - ttystate.c_lflag |= ICANON | ECHO; - } - //set the terminal attributes. - tcsetattr(STDIN_FILENO, TCSANOW, &ttystate); - -} - -int main(int ac, char** av) { - struct stlinky *st=NULL; - - sig_init(); - - gsl = stlink_open_usb(10, 1, NULL); - if (gsl != NULL) { - printf("ST-Linky proof-of-concept terminal :: Created by Necromant for lulz\n"); - stlink_version(gsl); - stlink_enter_swd_mode(gsl); - printf("chip id: %#x\n", gsl->chip_id); - printf("core_id: %#x\n", gsl->core_id); - - cortex_m3_cpuid_t cpuid; - stlink_cpu_id(gsl, &cpuid); - printf("cpuid:impl_id = %0#x, variant = %#x\n", cpuid.implementer_id, cpuid.variant); - printf("cpuid:part = %#x, rev = %#x\n", cpuid.part, cpuid.revision); - - stlink_reset(gsl); - stlink_force_debug(gsl); - stlink_run(gsl); - stlink_status(gsl); - - /* wait for device to boot */ - /* TODO: Make timeout adjustable via command line */ - sleep(1); - - if(ac == 1){ - st = stlinky_detect(gsl); - }else if(ac == 2){ - st = malloc(sizeof(struct stlinky)); - st->sl = gsl; - st->off = (int)strtol(av[1], NULL, 16); - printf("using stlinky at 0x%x\n", st->off); - stlink_read_mem32(gsl, st->off + 4, 4); - st->bufsize = READ_UINT32_LE(gsl->q_buf); - printf("stlinky buffer size 0x%u \n", (unsigned int)st->bufsize); - }else{ - cleanup(0); - } - if (st == NULL) - { - printf("stlinky magic not found in sram :(\n"); - cleanup(0); - } - if (st->bufsize > ST_TERM_MAX_BUFF_SIZE){ - printf("stlinky buffer size too big\n"); - cleanup(0); - } - char* rxbuf = malloc(st->bufsize); - char* txbuf = malloc(st->bufsize); - size_t tmp; - nonblock(1); - int fd = fileno(stdin); - int saved_flags = fcntl(fd, F_GETFL); - fcntl(fd, F_SETFL, saved_flags & ~O_NONBLOCK); - printf("Entering interactive terminal. CTRL+C to exit\n\n\n"); - while(1) { - sig_process(); - tmp = stlinky_rx(st, rxbuf); - if(tmp > 0) - { - fwrite(rxbuf,tmp,1,stdout); - fflush(stdout); - } - if (kbhit()) { - tmp = read(fd, txbuf, st->bufsize); - stlinky_tx(st,txbuf,tmp); - } - } - } - return 0; -} From 77df02bf92612520478e014ad1a6f257aade714f Mon Sep 17 00:00:00 2001 From: Andrew Andrianov Date: Wed, 14 Sep 2016 16:55:06 +0300 Subject: [PATCH 0474/1435] CMakeLists.txt: Fix linker command in generated .pc file Signed-off-by: Andrew Andrianov --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 24c4f51d1..6b6c7b306 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -232,7 +232,7 @@ if (NOT APPLE AND NOT WIN32) "\${prefix}/include/\${deb_host_multiarch}/${PROJECT_NAME}-${STLINK_PACKAGE_VERSION}" ) set(PKG_CONFIG_LIBS - "-L\${libdir} -l:libstlink.so.${STLINK_PACKAGE_VERSION}" + "-L\${libdir} -l:libstlink.so.${STLINK_PACKAGE_VERSION_MAJOR}" ) set(PKG_CONFIG_CFLAGS "-I\${includedir}" From 6dfb8bafdb95e244271cf232ed2da8dbedbad08c Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Wed, 14 Sep 2016 17:11:47 +0200 Subject: [PATCH 0475/1435] Update changelog for upcomming v1.3.0 release --- .version | 2 +- ChangeLog.md | 23 ++++++++++++++++++++--- 2 files changed, 21 insertions(+), 4 deletions(-) diff --git a/.version b/.version index d72f26267..b6bb93f7c 100644 --- a/.version +++ b/.version @@ -1 +1 @@ -2.0.0-dev +1.3.0-dev diff --git a/ChangeLog.md b/ChangeLog.md index 355ba08ab..fead8b8ec 100644 --- a/ChangeLog.md +++ b/ChangeLog.md @@ -1,14 +1,31 @@ Stlink ChangeLog ================ -v2.0.0 +v1.3.0 ====== -Ongoing development +Release date: ongoing Major changes: -* Deprecation of autotools (autoconf, automake) +* Deprecation of autotools (autoconf, automake) (Jerry Jacobs) +* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature (Jerry Jacobs) +* Add debian packaging (nekromant) +* Add intel hex file reading for `st-flash` (pull-request #459) (dev26th) + +Chip support added for: + +* STM32F410 (Jerry Jacobs) +* L0x Category 5 devices (gluedig) +* Add L0 Category 2 device (chip id: 0x425) (Áron RADICS) + +Updates and fixes: + +* Fix memory map for STM32F4 (zulusw) +* Fix STM32L-problem with flash loader (issue #390) (Tom de Boer) +* `st-util` don't read target voltage on startup as it crashes STM32F100 (probably stlink/v1) (Greg Alexander) +* Do a JTAG reset prior to reading CPU information when processor is in deep sleep (andyg24) +* Redesign of `st-flash` commandline options parsing (pull-request #459) (dev26th) v1.2.0 ====== From ddbe285dad875ea90bd663641d74a0cf8156c356 Mon Sep 17 00:00:00 2001 From: "Daniel Campoverde [alx741]" Date: Wed, 14 Sep 2016 21:58:49 -0500 Subject: [PATCH 0476/1435] Add man page installation to Cmake rules --- CMakeLists.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/CMakeLists.txt b/CMakeLists.txt index 6b6c7b306..bfa752d6b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -150,6 +150,11 @@ set(STLINK_SOURCE src/flash_loader.c ) +set(STLINK_MANPAGES + doc/man/stlink.1 +) + + if (WIN32 OR MSYS OR MINGW) set (STLINK_SOURCE "${STLINK_SOURCE};src/mmap.c;src/mingw/mingw.c") # TODO endif () @@ -224,6 +229,9 @@ install(FILES ${CMAKE_SOURCE_DIR}/include/stlink.h install(FILES ${STLINK_HEADERS} DESTINATION include/${CMAKE_LIBRARY_PATH}/stlink-${STLINK_PACKAGE_VERSION}/stlink) +install(FILES ${STLINK_MANPAGES} + DESTINATION share/man/man1) + if (NOT APPLE AND NOT WIN32) set(PKG_CONFIG_LIBDIR "\${prefix}/lib/\${deb_host_multiarch}" From b0df7049dd119a2c8cace2cd75b5084313b227c8 Mon Sep 17 00:00:00 2001 From: "Daniel Campoverde [alx741]" Date: Wed, 14 Sep 2016 22:15:53 -0500 Subject: [PATCH 0477/1435] Add st-util man page --- doc/man/.gitignore | 1 + doc/man/Makefile | 11 ++++++++ doc/man/st-util.md | 68 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 80 insertions(+) create mode 100644 doc/man/.gitignore create mode 100644 doc/man/Makefile create mode 100644 doc/man/st-util.md diff --git a/doc/man/.gitignore b/doc/man/.gitignore new file mode 100644 index 000000000..f7e585b87 --- /dev/null +++ b/doc/man/.gitignore @@ -0,0 +1 @@ +*.1 diff --git a/doc/man/Makefile b/doc/man/Makefile new file mode 100644 index 000000000..8871c6331 --- /dev/null +++ b/doc/man/Makefile @@ -0,0 +1,11 @@ +MAN1 = +MAN1 += st-util.md + +all: $(patsubst %.md, %.1, $(MAN1)) + +%.1: %.md + pandoc -s -t man $< -o $@ + tail --line=+3 $@ > tmp && mv tmp $@ + +clean: + rm *.1 diff --git a/doc/man/st-util.md b/doc/man/st-util.md new file mode 100644 index 000000000..8f015c806 --- /dev/null +++ b/doc/man/st-util.md @@ -0,0 +1,68 @@ +% ST-UTIL(1) Open Source STMicroelectronics Stlink Tools | STLINK +% +% Sep 2016 + + +# NAME +st-util - Run GDB server to interact with STM32 device + + +# SYNOPSIS +*st-util* \[\...] + + +# DESCRIPTION +Start a GDB server to interact with a STM32 device +Run the main binary of the local package (src/main.rs). + +If a port number is not specified using the **--listen_port** option, the +default **4242** port will be used. + +Stlink version 2 is used by default unless the option **--stlinkv1** is given. + +The STLINKv2 device to use can be specified in the environment +variable STLINK_DEVICE on the format :. + + +# OPTIONS + +-h, --help +: Print this message. + +-v *XX*, --verbose=XX +: Specify a specific verbosity level (0..99) + +-v, --verbose +: Specify generally verbose logging + +-s *X*, --stlink_version=X +: Choose what version of stlink to use, (defaults to 2) + +-1, --stlinkv1 +: Force stlink version 1 + +-p *4242*, --listen_port=1234 +: Set the gdb server listen port. (default port: 4242) + +-m, --multi +: Set gdb server to extended mode. st-util will continue listening for connections after disconnect. + +-n, --no-reset +: Do not reset board on connection. + + +# EXAMPLES +Run GDB server on port 4500 and connect to it + + $ st-util -p 4500 + $ gdb + (gdb) target extended-remote localhost:4500 + + +# SEE ALSO +st-flash(1), st-info(1), st-term(1) + + +# COPYRIGHT +This work is copyrighted. Stlink contributors. +See *LICENSE* file in the stlink source distribution. From d50bd3705eee029a1af7129854c4f100c98b2b36 Mon Sep 17 00:00:00 2001 From: "fabien.lementec" Date: Thu, 15 Sep 2016 08:04:12 +0200 Subject: [PATCH 0478/1435] fix: add missing st-util.1 until proper solution --- doc/man/st-util.1 | 80 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 doc/man/st-util.1 diff --git a/doc/man/st-util.1 b/doc/man/st-util.1 new file mode 100644 index 000000000..674b0dbef --- /dev/null +++ b/doc/man/st-util.1 @@ -0,0 +1,80 @@ +.PP +st-util - Run GDB server to interact with STM32 device +.SH SYNOPSIS +.PP +\f[I]st-util\f[] [...] +.SH DESCRIPTION +.PP +Start a GDB server to interact with a STM32 device Run the main binary +of the local package (src/main.rs). +.PP +If a port number is not specified using the \f[B]--listen_port\f[] +option, the default \f[B]4242\f[] port will be used. +.PP +Stlink version 2 is used by default unless the option +\f[B]--stlinkv1\f[] is given. +.PP +The STLINKv2 device to use can be specified in the environment variable +STLINK_DEVICE on the format :. +.SH OPTIONS +.TP +.B -h, --help +Print this message. +.RS +.RE +.TP +.B -v \f[I]XX\f[], --verbose=XX +Specify a specific verbosity level (0..99) +.RS +.RE +.TP +.B -v, --verbose +Specify generally verbose logging +.RS +.RE +.TP +.B -s \f[I]X\f[], --stlink_version=X +Choose what version of stlink to use, (defaults to 2) +.RS +.RE +.TP +.B -1, --stlinkv1 +Force stlink version 1 +.RS +.RE +.TP +.B -p \f[I]4242\f[], --listen_port=1234 +Set the gdb server listen port. +(default port: 4242) +.RS +.RE +.TP +.B -m, --multi +Set gdb server to extended mode. +st-util will continue listening for connections after disconnect. +.RS +.RE +.TP +.B -n, --no-reset +Do not reset board on connection. +.RS +.RE +.SH EXAMPLES +.PP +Run GDB server on port 4500 and connect to it +.IP +.nf +\f[C] +$\ st-util\ -p\ 4500 +$\ gdb +(gdb)\ target\ extended-remote\ localhost:4500 +\f[] +.fi +.SH SEE ALSO +.PP +st-flash(1), st-info(1), st-term(1) +.SH COPYRIGHT +.PP +This work is copyrighted. +Stlink contributors. +See \f[I]LICENSE\f[] file in the stlink source distribution. From c3f6fd0516503ffa56cc8e5c936eea5a1a8140ad Mon Sep 17 00:00:00 2001 From: "fabien.lementec" Date: Thu, 15 Sep 2016 08:06:34 +0200 Subject: [PATCH 0479/1435] fix: cmake, st-util.1 --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index bfa752d6b..d2e0acda8 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -151,7 +151,7 @@ set(STLINK_SOURCE ) set(STLINK_MANPAGES - doc/man/stlink.1 + doc/man/st-util.1 ) From 1ade678f9cb04898324a6b75ac7396b7b3b73ca7 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 15 Sep 2016 10:44:01 +0200 Subject: [PATCH 0480/1435] Refactor main CMakeLists.txt. Generate manpages when pandoc is present in Debug builds. Add top level Makefile --- CMakeLists.txt | 20 +- Makefile | 45 ++++ cmake/modules/pandocology.cmake | 373 ++++++++++++++++++++++++++++++++ doc/man/CMakeLists.txt | 28 +++ doc/man/Makefile | 11 - include/CMakeLists.txt | 8 + 6 files changed, 456 insertions(+), 29 deletions(-) create mode 100644 Makefile create mode 100644 cmake/modules/pandocology.cmake create mode 100644 doc/man/CMakeLists.txt delete mode 100644 doc/man/Makefile create mode 100644 include/CMakeLists.txt diff --git a/CMakeLists.txt b/CMakeLists.txt index d2e0acda8..a75bf2219 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -150,11 +150,6 @@ set(STLINK_SOURCE src/flash_loader.c ) -set(STLINK_MANPAGES - doc/man/st-util.1 -) - - if (WIN32 OR MSYS OR MINGW) set (STLINK_SOURCE "${STLINK_SOURCE};src/mmap.c;src/mingw/mingw.c") # TODO endif () @@ -218,19 +213,6 @@ install(TARGETS ${PROJECT_NAME} ${STLINK_LIB_STATIC} st-flash st-util st-info ARCHIVE DESTINATION lib/${CMAKE_LIBRARY_PATH} LIBRARY DESTINATION lib/${CMAKE_LIBRARY_PATH} ) -# Now, install the development headers -file(GLOB STLINK_HEADERS - "${CMAKE_SOURCE_DIR}/include/stlink/*.h" -) - -install(FILES ${CMAKE_SOURCE_DIR}/include/stlink.h - DESTINATION include/${CMAKE_LIBRARY_PATH}/stlink-${STLINK_PACKAGE_VERSION}/) - -install(FILES ${STLINK_HEADERS} - DESTINATION include/${CMAKE_LIBRARY_PATH}/stlink-${STLINK_PACKAGE_VERSION}/stlink) - -install(FILES ${STLINK_MANPAGES} - DESTINATION share/man/man1) if (NOT APPLE AND NOT WIN32) set(PKG_CONFIG_LIBDIR @@ -283,6 +265,8 @@ if (NOT APPLE AND gtk_FOUND) DESTINATION ${INSTALLED_UI_DIR}) endif() +add_subdirectory(include) +add_subdirectory(doc/man) add_subdirectory(tests) set (CPACK_PACKAGE_NAME ${PROJECT_NAME}) diff --git a/Makefile b/Makefile new file mode 100644 index 000000000..d93c4b181 --- /dev/null +++ b/Makefile @@ -0,0 +1,45 @@ +## +# This Makefile is used to drive building of Debug and Release +# targets of CMake +## +MAKEFLAGS += -s + +all: debug +ci: lint debug release test + +help: + @echo " release: Run a release build" + @echo " debug: Run a debug build" + @echo " lint: Lint check all source-code" + @echo " test: Build and run tests" + @echo " clean: Clean all build output" + @echo "rebuild_cache: Rebuild all CMake caches" + +rebuild_cache: build/Debug build/Release + @$(MAKE) -C build/Debug rebuild_cache + @$(MAKE) -C build/Release rebuild_cache + +debug: build/Debug + @echo "[DEBUG]" + @$(MAKE) -C build/Debug + +release: build/Release + @echo "[RELEASE]" + @$(MAKE) -C build/Release + +test: build/Debug + @$(MAKE) -C build/Debug test + +build/Debug: + @mkdir -p $@ + @cd $@ && cmake -DCMAKE_BUILD_TYPE=Debug ../../ + +build/Release: + @mkdir -p $@ + @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Release ../../ + +clean: + @echo "[CLEAN]" + @rm -Rf build + +.PHONY: clean diff --git a/cmake/modules/pandocology.cmake b/cmake/modules/pandocology.cmake new file mode 100644 index 000000000..2a49cf573 --- /dev/null +++ b/cmake/modules/pandocology.cmake @@ -0,0 +1,373 @@ +################################################################################ +## +## Provide Pandoc compilation support for the CMake build system +## +## Version: 0.0.1-dirty +## Author: Jeet Sukumatan (jeetsukumaran@gmail.com) +## Jerry Jacobs (jerry.jacobs@xor-gate.org) +## +## Copyright 2015 Jeet Sukumaran. +## Copyright 2016 Jerry Jacobs +## +## This software is released under the BSD 3-Clause License. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are +## met: +## +## 1. Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## +## 2. Redistributions in binary form must reproduce the above copyright +## notice, this list of conditions and the following disclaimer in the +## documentation and/or other materials provided with the distribution. +## +## 3. Neither the name of the copyright holder nor the names of its +## contributors may be used to endorse or promote products derived from this +## software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS +## IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +## THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +## PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +## EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +## PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +## PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +## LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +## NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +################################################################################ + +include(CMakeParseArguments) + +if(NOT EXISTS ${PANDOC_EXECUTABLE}) + #find_program(PANDOC_EXECUTABLE pandoc) + #mark_as_advanced(PANDOC_EXECUTABLE) +endif() + +############################################################################### +# Based on code from UseLATEX +# Author: Kenneth Moreland +# Copyright 2004 Sandia Corporation. +# Under the terms of Contract DE-AC04-94AL85000, there is a non-exclusive +# license for use of this work by or on behalf of the +# U.S. Government. Redistribution and use in source and binary forms, with +# or without modification, are permitted provided that this Notice and any +# statement of authorship are reproduced on all copies. + +# Adds command to copy file from the source directory to the destination +# directory: used to move source files from source directory into build +# directory before main build +function(pandocology_add_input_file source_path dest_dir dest_filelist_var) + set(dest_filelist) + file(GLOB globbed_source_paths "${source_path}") + foreach(globbed_source_path ${globbed_source_paths}) + # MESSAGE(FATAL_ERROR "${globbed_source_path}") + get_filename_component(filename ${globbed_source_path} NAME) + get_filename_component(absolute_dest_path ${dest_dir}/${filename} ABSOLUTE) + file(RELATIVE_PATH relative_dest_path ${CMAKE_CURRENT_BINARY_DIR} ${absolute_dest_path}) + list(APPEND dest_filelist ${absolute_dest_path}) + ADD_CUSTOM_COMMAND( + OUTPUT ${relative_dest_path} + COMMAND ${CMAKE_COMMAND} -E copy ${globbed_source_path} ${dest_dir}/${filename} + DEPENDS ${globbed_source_path} + ) + set(${dest_filelist_var} ${${dest_filelist_var}} ${dest_filelist} PARENT_SCOPE) + endforeach() +endfunction() + +# A version of GET_FILENAME_COMPONENT that treats extensions after the last +# period rather than the first. +function(pandocology_get_file_stemname varname filename) + SET(result) + GET_FILENAME_COMPONENT(name ${filename} NAME) + STRING(REGEX REPLACE "\\.[^.]*\$" "" result "${name}") + SET(${varname} "${result}" PARENT_SCOPE) +endfunction() + +function(pandocology_get_file_extension varname filename) + SET(result) + GET_FILENAME_COMPONENT(name ${filename} NAME) + STRING(REGEX MATCH "\\.[^.]*\$" result "${name}") + SET(${varname} "${result}" PARENT_SCOPE) +endfunction() +############################################################################### + +function(pandocology_add_input_dir source_dir dest_parent_dir dir_dest_filelist_var) + set(dir_dest_filelist) + get_filename_component(dir_name ${source_dir} NAME) + get_filename_component(absolute_dest_dir ${dest_parent_dir}/${dir_name} ABSOLUTE) + file(RELATIVE_PATH relative_dest_dir ${CMAKE_CURRENT_BINARY_DIR} ${absolute_dest_dir}) + add_custom_command( + OUTPUT ${relative_dest_dir} + COMMAND ${CMAKE_COMMAND} -E make_directory ${absolute_dest_dir} + DEPENDS ${source_dir} + ) + file(GLOB source_files "${source_dir}/*") + foreach(source_file ${source_files}) + # get_filename_component(absolute_source_path ${CMAKE_CURRENT_SOURCE_DIR}/${source_file} ABSOLUTE) + pandocology_add_input_file(${source_file} ${absolute_dest_dir} dir_dest_filelist) + endforeach() + set(${dir_dest_filelist_var} ${${dir_dest_filelist_var}} ${dir_dest_filelist} PARENT_SCOPE) +endfunction() + +function(add_to_make_clean filepath) + get_directory_property(make_clean_files ADDITIONAL_MAKE_CLEAN_FILES) + set_directory_properties(PROPERTIES ADDITIONAL_MAKE_CLEAN_FILES "${make_clean_files};${filepath}") +endfunction() + +function(disable_insource_build) + IF ( CMAKE_SOURCE_DIR STREQUAL CMAKE_BINARY_DIR AND NOT MSVC_IDE ) + MESSAGE(FATAL_ERROR "The build directory must be different from the main project source " +"directory. Please create a directory such as '${CMAKE_SOURCE_DIR}/build', " +"and run CMake from there, passing the path to this source directory as " +"the path argument. E.g.: + $ cd ${CMAKE_SOURCE_DIR} + $ mkdir build + $ cd build + $ cmake .. && make && sudo make install +This process created the file `CMakeCache.txt' and the directory `CMakeFiles'. +Please delete them: + $ rm -r CMakeFiles/ CmakeCache.txt +") + ENDIF() +endfunction() + +# This builds a document +# +# Usage: +# +# +# INCLUDE(pandocology) +# +# add_document( +# figures.tex +# SOURCES figures.md +# RESOURCE_DIRS figs +# PANDOC_DIRECTIVES -t latex +# NO_EXPORT_PRODUCT +# ) +# +# add_document( +# opus.pdf +# SOURCES opus.md +# RESOURCE_FILES opus.bib systbiol.template.latex systematic-biology.csl +# RESOURCE_DIRS figs +# PANDOC_DIRECTIVES -t latex +# --smart +# --template systbiol.template.latex +# --filter pandoc-citeproc +# --csl systematic-biology.csl +# --bibliography opus.bib +# --include-after-body=figures.tex +# DEPENDS figures.tex +# EXPORT_ARCHIVE +# ) +# +function(add_document target_name) + if (NOT PANDOC_EXECUTABLE) + message(WARNING "Pandoc not found. Install Pandoc (http://johnmacfarlane.net/pandoc/) or set cache variable PANDOC_EXECUTABLE.") + return() + endif() + + set(options EXPORT_ARCHIVE NO_EXPORT_PRODUCT EXPORT_PDF DIRECT_TEX_TO_PDF VERBOSE) + set(oneValueArgs PRODUCT_DIRECTORY) + set(multiValueArgs SOURCES RESOURCE_FILES RESOURCE_DIRS PANDOC_DIRECTIVES DEPENDS) + cmake_parse_arguments(ADD_DOCUMENT "${options}" "${oneValueArgs}" "${multiValueArgs}" ${ARGN} ) + + # this is because `make clean` will dangerously clean up source files + disable_insource_build() + + # get the stem of the target name + pandocology_get_file_stemname(target_stemname ${target_name}) + pandocology_get_file_extension(target_extension ${target_name}) + if (${ADD_DOCUMENT_EXPORT_PDF}) + if (NOT "${target_extension}" STREQUAL ".tex" AND NOT "${target_extension}" STREQUAL ".latex") + # if (NOT "${target_extension}" STREQUAL ".tex") + MESSAGE(FATAL_ERROR "Target '${target_name}': Cannot use 'EXPORT_PDF' for target of type '${target_extension}': target type must be '.tex' or '.latex'") + endif() + endif() + if (${ADD_DOCUMENT_DIRECT_TEX_TO_PDF}) + list(LENGTH ${ADD_DOCUMENT_SOURCES} SOURCE_LEN) + if (SOURCE_LEN GREATER 1) + MESSAGE(FATAL_ERROR "Target '${target_name}': Only one source can be specified when using the 'DIRECT_TEX_TO_PDF' option") + endif() + # set(ADD_DOCUMENT_SOURCES, list(GET ${ADD_DOCUMENT_SOURCES} 1)) + pandocology_get_file_stemname(source_stemname ${ADD_DOCUMENT_SOURCES}) + pandocology_get_file_extension(source_extension ${ADD_DOCUMENT_SOURCES}) + if (NOT "${source_extension}" STREQUAL ".tex" AND NOT "${source_extension}" STREQUAL ".latex") + MESSAGE(FATAL_ERROR "Target '${target_name}': Cannot use 'DIRECT_TEX_TO_PDF' for source of type '${source_extension}': source type must be '.tex' or '.latex'") + endif() + SET(check_target ${source_stemname}.pdf) + IF (NOT ${check_target} STREQUAL ${target_name}) + MESSAGE(FATAL_ERROR "Target '${target_name}': Must use target name of '${check_target}' if using 'DIRECT_TEX_TO_PDF'") + endif() + endif() + + ## set up output directory + if ("${ADD_DOCUMENT_PRODUCT_DIRECTORY}" STREQUAL "") + set(ADD_DOCUMENT_PRODUCT_DIRECTORY "product") + endif() + get_filename_component(product_directory ${CMAKE_BINARY_DIR}/${ADD_DOCUMENT_PRODUCT_DIRECTORY} ABSOLUTE) + # get_filename_component(absolute_product_path ${product_directory}/${target_name} ABSOLUTE) + + ## get primary source + set(build_sources) + foreach(input_file ${ADD_DOCUMENT_SOURCES} ) + pandocology_add_input_file(${CMAKE_CURRENT_SOURCE_DIR}/${input_file} ${CMAKE_CURRENT_BINARY_DIR} build_sources) + endforeach() + + ## get resource files + set(build_resources) + foreach(resource_file ${ADD_DOCUMENT_RESOURCE_FILES}) + pandocology_add_input_file(${CMAKE_CURRENT_SOURCE_DIR}/${resource_file} ${CMAKE_CURRENT_BINARY_DIR} build_resources) + endforeach() + + ## get resource dirs + set(exported_resources) + foreach(resource_dir ${ADD_DOCUMENT_RESOURCE_DIRS}) + pandocology_add_input_dir(${CMAKE_CURRENT_SOURCE_DIR}/${resource_dir} ${CMAKE_CURRENT_BINARY_DIR} build_resources) + if (${ADD_DOCUMENT_EXPORT_ARCHIVE}) + pandocology_add_input_dir(${CMAKE_CURRENT_SOURCE_DIR}/${resource_dir} ${product_directory} exported_resources) + endif() + endforeach() + + ## primary command + if (${ADD_DOCUMENT_DIRECT_TEX_TO_PDF}) + if (${ADD_DOCUMENT_VERBOSE}) + add_custom_command( + OUTPUT ${target_name} # note that this is in the build directory + DEPENDS ${build_sources} ${build_resources} ${ADD_DOCUMENT_DEPENDS} + # WORKING_DIRECTORY ${working_directory} + COMMAND ${CMAKE_COMMAND} -E make_directory ${product_directory} + # we produce the target in the source directory, in case other build targets require it as a source + COMMAND latexmk -gg -halt-on-error -interaction=nonstopmode -file-line-error -pdf ${build_sources} + ) + else() + add_custom_command( + OUTPUT ${target_name} # note that this is in the build directory + DEPENDS ${build_sources} ${build_resources} ${ADD_DOCUMENT_DEPENDS} + # WORKING_DIRECTORY ${working_directory} + COMMAND ${CMAKE_COMMAND} -E make_directory ${product_directory} + # we produce the target in the source directory, in case other build targets require it as a source + COMMAND latexmk -gg -halt-on-error -interaction=nonstopmode -file-line-error -pdf ${build_sources} 2>/dev/null >/dev/null || (grep --no-messages -A8 ".*:[0-9]*:.*" ${target_stemname}.log && false) + ) + endif() + add_to_make_clean(${CMAKE_CURRENT_BINARY_DIR}/${target_name}) + else() + add_custom_command( + OUTPUT ${target_name} # note that this is in the build directory + DEPENDS ${build_sources} ${build_resources} ${ADD_DOCUMENT_DEPENDS} + # WORKING_DIRECTORY ${working_directory} + COMMAND ${CMAKE_COMMAND} -E make_directory ${product_directory} + # we produce the target in the source directory, in case other build targets require it as a source + COMMAND ${PANDOC_EXECUTABLE} ${build_sources} ${ADD_DOCUMENT_PANDOC_DIRECTIVES} -o ${target_name} + ) + add_to_make_clean(${CMAKE_CURRENT_BINARY_DIR}/${target_name}) + endif() + + ## figure out what all is going to be produced by this build set, and set + ## those as dependencies of the primary target + set(primary_target_dependencies) + set(primary_target_dependencies ${primary_target_dependencies} ${CMAKE_CURRENT_BINARY_DIR}/${target_name}) + if (NOT ${ADD_DOCUMENT_NO_EXPORT_PRODUCT}) + set(primary_target_dependencies ${primary_target_dependencies} ${product_directory}/${target_name}) + endif() + if (${ADD_DOCUMENT_EXPORT_PDF}) + set(primary_target_dependencies ${primary_target_dependencies} ${CMAKE_CURRENT_BINARY_DIR}/${target_stemname}.pdf) + set(primary_target_dependencies ${primary_target_dependencies} ${product_directory}/${target_stemname}.pdf) + endif() + if (${ADD_DOCUMENT_EXPORT_ARCHIVE}) + set(primary_target_dependencies ${primary_target_dependencies} ${product_directory}/${target_stemname}.tbz) + endif() + + ## primary target + # # target cannot have same (absolute name) as dependencies: + # # http://www.cmake.org/pipermail/cmake/2011-March/043378.html + add_custom_target( + ${target_name} + ALL + DEPENDS ${primary_target_dependencies} ${ADD_DOCUMENT_DEPENDS} + ) + + # run post-pdf + if (${ADD_DOCUMENT_EXPORT_PDF}) + # get_filename_component(target_stemname ${target_name} NAME_WE) + add_custom_command( + OUTPUT ${product_directory}/${target_stemname}.pdf ${CMAKE_CURRENT_BINARY_DIR}/${target_stemname}.pdf + DEPENDS ${target_name} ${build_sources} ${build_resources} ${ADD_DOCUMENT_DEPENDS} + + # Does not work: custom template used to generate tex is ignored + # COMMAND ${PANDOC_EXECUTABLE} ${target_name} -f latex -o ${target_stemname}.pdf + + # (1) Apparently, both nonstopmode and batchmode produce an output file + # even if there was an error. This tricks latexmk into believing + # the file is actually up-to-date. + # So we use `-halt-on-error` or `-interaction=errorstopmode` + # instead. + # (2) `grep` returns a non-zero error code if the pattern is not + # found. So, in our scheme below to filter the output of + # `pdflatex`, it is precisely when there is NO error that + # grep returns a non-zero code, which fools CMake into thinking + # tex'ing failed. + # Hence the need for `| grep ...| cat` or `| grep || true`. + # But we can go better: + # latexmk .. || (grep .. && false) + # So we can have our cake and eat it too: here we want to + # re-raise the error after a successful grep if there was an + # error in `latexmk`. + # COMMAND latexmk -gg -halt-on-error -interaction=nonstopmode -file-line-error -pdf ${target_name} 2>&1 | grep -A8 ".*:[0-9]*:.*" || true + COMMAND latexmk -gg -halt-on-error -interaction=nonstopmode -file-line-error -pdf ${target_name} 2>/dev/null >/dev/null || (grep --no-messages -A8 ".*:[0-9]*:.*" ${target_stemname}.log && false) + + COMMAND ${CMAKE_COMMAND} -E copy ${target_stemname}.pdf ${product_directory} + ) + add_to_make_clean(${CMAKE_CURRENT_BINARY_DIR}/${target_stemname}.pdf) + add_to_make_clean(${product_directory}/${target_stemname}.pdf) + endif() + + ## copy products + if (NOT ${ADD_DOCUMENT_NO_EXPORT_PRODUCT}) + add_custom_command( + OUTPUT ${product_directory}/${target_name} + DEPENDS ${build_sources} ${build_resources} ${ADD_DOCUMENT_DEPENDS} + COMMAND ${CMAKE_COMMAND} -E copy ${target_name} ${product_directory} + ) + add_to_make_clean(${product_directory}/${target_name}) + endif() + + ## copy resources + if (${ADD_DOCUMENT_EXPORT_ARCHIVE}) + # get_filename_component(target_stemname ${target_name} NAME_WE) + # add_custom_command( + # TARGET ${target_name} POST_BUILD + # DEPENDS ${build_sources} ${build_resources} ${ADD_DOCUMENT_DEPENDS} + # # COMMAND cp ${build_resources} ${ADD_DOCUMENT_DEPENDS} ${product_directory} + # COMMAND ${CMAKE_COMMAND} -E tar cjf ${product_directory}/${target_stemname}.tbz ${target_name} ${build_resources} ${ADD_DOCUMENT_DEPENDS} + # ) + add_custom_command( + OUTPUT ${product_directory}/${target_stemname}.tbz + DEPENDS ${target_name} + # COMMAND cp ${build_resources} ${ADD_DOCUMENT_DEPENDS} ${product_directory} + COMMAND ${CMAKE_COMMAND} -E tar cjf ${product_directory}/${target_stemname}.tbz ${target_name} ${build_resources} ${ADD_DOCUMENT_DEPENDS} + ) + add_to_make_clean(${product_directory}/${target_stemname}.tbz) + # add_custom_target( + # ${target_stemname}.ARCHIVE + # ALL + # DEPENDS ${product_directory}/${target_stemname}.tbz + # ) + endif() + +endfunction(add_document) + +function(add_tex_document) + add_document(${ARGV} DIRECT_TEX_TO_PDF) +endfunction() + +# LEGACY SUPPORT +function(add_pandoc_document) + add_document(${ARGV}) +endfunction() + diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt new file mode 100644 index 000000000..956b76af7 --- /dev/null +++ b/doc/man/CMakeLists.txt @@ -0,0 +1,28 @@ +set(MANPAGES + st-util +) + +# Only generate manpages with pandoc in Debug builds +if(${CMAKE_BUILD_TYPE} MATCHES "Debug") + include(pandocology) + + foreach(manpage ${MANPAGES}) + add_document( + ${manpage}.1 + SOURCES ${manpage}.md + PANDOC_DIRECTIVES -s -t man + PRODUCT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + ) + + install(FILES ${CMAKE_CURRENT_BINARY_DIR}/${manpage}.1 + DESTINATION share/man/man1 + ) + endforeach() +else() + # TODO(xor-gate): we should generate a install list for Release and Debug targets + foreach(manpage ${MANPAGES}) + install(FILES ${manpage}.1 + DESTINATION share/man/man1 + ) + endforeach() +endif() diff --git a/doc/man/Makefile b/doc/man/Makefile deleted file mode 100644 index 8871c6331..000000000 --- a/doc/man/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -MAN1 = -MAN1 += st-util.md - -all: $(patsubst %.md, %.1, $(MAN1)) - -%.1: %.md - pandoc -s -t man $< -o $@ - tail --line=+3 $@ > tmp && mv tmp $@ - -clean: - rm *.1 diff --git a/include/CMakeLists.txt b/include/CMakeLists.txt new file mode 100644 index 000000000..5f603df8c --- /dev/null +++ b/include/CMakeLists.txt @@ -0,0 +1,8 @@ +file(GLOB STLINK_HEADERS + "stlink/*.h" +) + +install(FILES ${CMAKE_SOURCE_DIR}/include/stlink.h + DESTINATION include/${CMAKE_LIBRARY_PATH}) +install(FILES ${STLINK_HEADERS} + DESTINATION include/${CMAKE_LIBRARY_PATH}/stlink) From 10f965e45dbf87cc4d9d81320ab9c871055214bf Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 15 Sep 2016 10:46:13 +0200 Subject: [PATCH 0481/1435] cmake/modules/pandocology.cmake: Uncomment search of pandoc, due to previous local testing --- cmake/modules/pandocology.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmake/modules/pandocology.cmake b/cmake/modules/pandocology.cmake index 2a49cf573..f39f8d952 100644 --- a/cmake/modules/pandocology.cmake +++ b/cmake/modules/pandocology.cmake @@ -43,8 +43,8 @@ include(CMakeParseArguments) if(NOT EXISTS ${PANDOC_EXECUTABLE}) - #find_program(PANDOC_EXECUTABLE pandoc) - #mark_as_advanced(PANDOC_EXECUTABLE) + find_program(PANDOC_EXECUTABLE pandoc) + mark_as_advanced(PANDOC_EXECUTABLE) endif() ############################################################################### From c42de25204b886da7e9c8758cab56a79c4afb62e Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 15 Sep 2016 14:55:18 +0200 Subject: [PATCH 0482/1435] cmake: Fix building with MinGw64 --- CMakeLists.txt | 3 +-- cmake/modules/FindLibUSB.cmake | 5 ++++- scripts/mingw64-build.bat | 10 +--------- 3 files changed, 6 insertions(+), 12 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index a75bf2219..f4d7ef552 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,7 +2,6 @@ cmake_minimum_required(VERSION 2.8.7) project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics Stlink Tools") -project(stlink C) include(CheckCCompilerFlag) include(CheckIncludeFile) find_package(PkgConfig) @@ -108,7 +107,7 @@ if (NOT CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") endif () add_cflag_if_supported("-Wundef") -if (NOT MSYS OR MINGW) +if (NOT WIN32) add_cflag_if_supported("-fPIC") endif () diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index 3b15339e4..006ab6976 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -6,7 +6,7 @@ # LIBUSB_LIBRARY - The libraries needed to use libusb # LIBUSB_DEFINITIONS - Compiler switches required for using libusb -if(WIN32 OR CMAKE_VS_PLATFORM_NAME) +if(WIN32 OR CMAKE_VS_PLATFORM_NAME OR MINGW OR MSYS) set(LIBUSB_WIN_VERSION 1.0.20) set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) @@ -21,6 +21,7 @@ if(WIN32 OR CMAKE_VS_PLATFORM_NAME) ${LIBUSB_WIN_ARCHIVE_PATH} ) endif() + file(MAKE_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) execute_process(COMMAND ${ZIP_LOCATION} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o${LIBUSB_WIN_OUTPUT_FOLDER}) endif() @@ -45,6 +46,8 @@ message(STATUS "LIBUSB_INCLUDE_DIR: ${LIBUSB_INCLUDE_DIR}") if (APPLE) set(LIBUSB_NAME libusb-1.0.a) +elseif(MSYS OR MINGW) + set(LIBUSB_NAME usb-1.0) elseif(WIN32 OR CMAKE_VS_PLATFORM_NAME) set(LIBUSB_NAME libusb-1.0.lib) elseif(CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") diff --git a/scripts/mingw64-build.bat b/scripts/mingw64-build.bat index 18397f0e0..52c6fffb1 100644 --- a/scripts/mingw64-build.bat +++ b/scripts/mingw64-build.bat @@ -1,12 +1,4 @@ -### -# MinGW64 build helper for windows -# * Sets the correct PATH to compiler and tools -# * Generates MinGW Makefile with CMake -# * Build binaries with mingw32-make -# -# Read documentation about this file in doc/build_mingw.md -### @echo off set PATH=C:\Program Files (x86)\CMake\bin;C:\Program Files\CMake\bin;C:\Program Files\mingw-w64\x86_64-5.3.0-win32-sjlj-rt_v4-rev0\mingw64\bin;%PATH% cmake -G "MinGW Makefiles" .. -mingw32-make +mingw32-make \ No newline at end of file From 3b47efcb011af415666faf72798c2b3f97f40648 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 15 Sep 2016 15:05:00 +0200 Subject: [PATCH 0483/1435] cmake: WIN32: Fix linking with winsock --- CMakeLists.txt | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index f4d7ef552..9195e3345 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -188,7 +188,12 @@ if (APPLE) target_link_libraries(${PROJECT_NAME} ${CoreFoundation} ${IOKit} ${ObjC}) endif () -target_link_libraries(${PROJECT_NAME} ${LIBUSB_LIBRARY}) +if(WIN32 OR MSYS OR MINGW) + target_link_libraries(${PROJECT_NAME} ${LIBUSB_LIBRARY} wsock32 ws2_32) +else() + target_link_libraries(${PROJECT_NAME} ${LIBUSB_LIBRARY}) +endif() + add_executable(st-flash src/tools/flash.c src/tools/flash_opts.c) target_link_libraries(st-flash ${PROJECT_NAME}) @@ -201,11 +206,8 @@ add_executable(st-util src/gdbserver/gdb-remote.c src/gdbserver/gdb-server.h src/gdbserver/semihosting.c src/gdbserver/semihosting.h) -if (WIN32 OR MSYS OR MINGW) - target_link_libraries(st-util ${PROJECT_NAME} wsock32 ws2_32) -else () - target_link_libraries(st-util ${PROJECT_NAME}) -endif () + +target_link_libraries(st-util ${PROJECT_NAME}) install(TARGETS ${PROJECT_NAME} ${STLINK_LIB_STATIC} st-flash st-util st-info RUNTIME DESTINATION bin From c6fb84884c17a622ddc386d6a6cc4dda04d3a5d9 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 15 Sep 2016 15:20:51 +0200 Subject: [PATCH 0484/1435] appveyor: Cache libusb 7z archive between builds --- .appveyor.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.appveyor.yml b/.appveyor.yml index 9e53a07bc..0aa97effc 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -8,6 +8,7 @@ environment: cache: - i686-4.9.2-release-win32-sjlj-rt_v3-rev1.7z - x86_64-4.9.2-release-win32-seh-rt_v3-rev1.7z + - libusb-*.7z build_script: - ps: | mkdir build From 07f181c7f8998e3458dad67287aa13e9869ac60b Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 15 Sep 2016 15:25:28 +0200 Subject: [PATCH 0485/1435] appveyor: Cache libusb-1.0.20.7z instead of non-allowed wildcard --- .appveyor.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.appveyor.yml b/.appveyor.yml index 0aa97effc..10c0e935a 100644 --- a/.appveyor.yml +++ b/.appveyor.yml @@ -8,7 +8,7 @@ environment: cache: - i686-4.9.2-release-win32-sjlj-rt_v3-rev1.7z - x86_64-4.9.2-release-win32-seh-rt_v3-rev1.7z - - libusb-*.7z + - libusb-1.0.20.7z build_script: - ps: | mkdir build From 408632ad6c010aad50262500f0306613063e17e9 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 15 Sep 2016 15:26:37 +0200 Subject: [PATCH 0486/1435] Update README.md Add appveyor MinGW64 build badge from xor-gate/stlink --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 3671fbf3f..a63955235 100644 --- a/README.md +++ b/README.md @@ -5,6 +5,7 @@ Open source version of the STMicroelectronics Stlink Tools [![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.2.0.svg?maxAge=2592000)](https://github.com/texane/stlink/compare/1.2.0...master) [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) [![Build Status](https://jenkins.ncrmnt.org/buildStatus/icon?job=GithubCI/stlink)](https://jenkins.ncrmnt.org/job/GithubCI/stlink) +[![Build status](https://ci.appveyor.com/api/projects/status/wrcie05d4jmut0te?svg=true)](https://ci.appveyor.com/project/xor-gate/stlink) [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) ## HOWTO From c4d7e50c6d76c447c003c8b33bc246a9ad51bcd7 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 15 Sep 2016 15:37:43 +0200 Subject: [PATCH 0487/1435] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index a63955235..2846a53d4 100644 --- a/README.md +++ b/README.md @@ -4,7 +4,7 @@ Open source version of the STMicroelectronics Stlink Tools [![GitHub release](https://img.shields.io/github/release/texane/stlink.svg?maxAge=2592000)](https://github.com/texane/stlink/releases/latest) [![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.2.0.svg?maxAge=2592000)](https://github.com/texane/stlink/compare/1.2.0...master) [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) -[![Build Status](https://jenkins.ncrmnt.org/buildStatus/icon?job=GithubCI/stlink)](https://jenkins.ncrmnt.org/job/GithubCI/stlink) +[![Build Status](https://jenkins.ncrmnt.org/buildStatus/icon?job=GithubCI/stlink)](https://jenkins.ncrmnt.org/job/GithubCI/job/stlink/) [![Build status](https://ci.appveyor.com/api/projects/status/wrcie05d4jmut0te?svg=true)](https://ci.appveyor.com/project/xor-gate/stlink) [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) From 3268ea1250da16d682704ab2e3b9f9fef4f625bb Mon Sep 17 00:00:00 2001 From: "Daniel Campoverde [alx741]" Date: Thu, 15 Sep 2016 18:18:27 -0500 Subject: [PATCH 0488/1435] Add st-flash man page --- doc/man/CMakeLists.txt | 1 + doc/man/st-flash.md | 70 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 doc/man/st-flash.md diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 956b76af7..baf482ea8 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -1,5 +1,6 @@ set(MANPAGES st-util + st-flash ) # Only generate manpages with pandoc in Debug builds diff --git a/doc/man/st-flash.md b/doc/man/st-flash.md new file mode 100644 index 000000000..88ba5870a --- /dev/null +++ b/doc/man/st-flash.md @@ -0,0 +1,70 @@ +% ST-FLASH(1) Open Source STMicroelectronics Stlink Tools | STLINK +% +% Sep 2016 + + +# NAME +st-flash - Flash binary files to STM32 device + + +# SYNOPSIS +*st-flash* \[*OPTIONS*\] \{read|write|erase\} \[*FILE*\] \ \ + + +# DESCRIPTION +Flash binary files to arbitrary sections of memory, or read arbitrary addresses +of memory out to a binary file. + +You can use this instead of st-util(1) if you prefer, but remember to use the +**.bin** image, rather than the **.elf** file. + +Use hexadecimal format for the *ADDR* and *SIZE*. + + +# COMMANDS + +write *FILE* *ADDR* +: Write firmware *FILE* to device starting from *ADDR* + +read *FILE* *ADDR* *SIZE* +: Read firmware from device starting from *ADDR* up to *SIZE* bytes to *FILE* + +erase +: Perform a mass erasing of the device firmware + + +# OPTIONS + +--debug +: TODO + +--reset +: TODO + +--serial *iSerial* +: TODO + + +# EXAMPLES +Flash `firmware.bin` to device + + $ st-flash write firmware.bin 0x8000000 + + +Read firmware from device (4096 bytes) + + $ st-flash read firmware.bin 0x8000000 4096 + + +Erase firmware from device + + $ st-flash erase + + +# SEE ALSO +st-util(1), st-info(1), st-term(1) + + +# COPYRIGHT +This work is copyrighted. Stlink contributors. +See *LICENSE* file in the stlink source distribution. From 759f423987b89610546f55bb053db4c30c600543 Mon Sep 17 00:00:00 2001 From: "Daniel Campoverde [alx741]" Date: Thu, 15 Sep 2016 18:18:45 -0500 Subject: [PATCH 0489/1435] Add st-info man page --- doc/man/CMakeLists.txt | 1 + doc/man/st-info.md | 58 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 doc/man/st-info.md diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index baf482ea8..795b6fa8d 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -1,6 +1,7 @@ set(MANPAGES st-util st-flash + st-info ) # Only generate manpages with pandoc in Debug builds diff --git a/doc/man/st-info.md b/doc/man/st-info.md new file mode 100644 index 000000000..9cc48e9f1 --- /dev/null +++ b/doc/man/st-info.md @@ -0,0 +1,58 @@ +% ST-INFO(1) Open Source STMicroelectronics Stlink Tools | STLINK +% +% Sep 2016 + + +# NAME +st-info - Provides information about connected STLINK and STM32 devices + + +# SYNOPSIS +*st-info* \[*OPTIONS*\] + + +# DESCRIPTION +Provides information about connected STLINK programmers and STM32 devices: +Serial code, openocd, flash, sram, page size, chipid, description. + + +# OPTIONS + +--flash +: Display amount of flash memory available in the device + +--sram +: Display amount of sram memory available in device + +--descr +: Display textual description of the device + +--pagesize +: Display the page size of the device + +--chipid +: Display the chip ID of the device + +--serial +: Display the serial code of the device + +--hla-serial +: Display the hex escaped serial code of the device + +--probe +: Display the summarized information of the connected programmers and devices + + +# EXAMPLES +Display information about connected programmers and devices + + $ st-info --probe + + +# SEE ALSO +st-util(1), st-flash(1), st-term(1) + + +# COPYRIGHT +This work is copyrighted. Stlink contributors. +See *LICENSE* file in the stlink source distribution. From 3c28cf15a79b50d273fa8147b93eb7c09c770f0b Mon Sep 17 00:00:00 2001 From: "Daniel Campoverde [alx741]" Date: Thu, 15 Sep 2016 18:52:58 -0500 Subject: [PATCH 0490/1435] Add st-term man page --- doc/man/CMakeLists.txt | 1 + doc/man/st-term.md | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 doc/man/st-term.md diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 795b6fa8d..96e1734d8 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -2,6 +2,7 @@ set(MANPAGES st-util st-flash st-info + st-term ) # Only generate manpages with pandoc in Debug builds diff --git a/doc/man/st-term.md b/doc/man/st-term.md new file mode 100644 index 000000000..e9b635e5c --- /dev/null +++ b/doc/man/st-term.md @@ -0,0 +1,36 @@ +% ST-TERM(1) Open Source STMicroelectronics Stlink Tools | STLINK +% +% Sep 2016 + + +# NAME +st-term - Serial terminal interface for debugging using STLink device only + + +# SYNOPSIS +*st-term* + + +# DESCRIPTION +Provides a serial terminal that works through the STLink device, allowing to do +the kind of debugging you would do using the UART of the STM32 device without +having to connect a UART-USB serial adapter dongle. + +It works by having a magic number in sram of the MCU within a structure that +serves as IO buffer. + +The required setup consist of some code that establishes the magic number, +buffer structure and helper functions for actual data transmission between host +and MCU. + +`stlinky.h` and `stlinky.c` are available in the Antares build system libraries +source: https://github.com/nekromant/antares/tree/master/include/lib + + +# SEE ALSO +st-util(1), st-info(1), st-term(1) + + +# COPYRIGHT +This work is copyrighted. Stlink contributors. +See *LICENSE* file in the stlink source distribution. From c23732c8329a244d7b083b3af771edd8143f4000 Mon Sep 17 00:00:00 2001 From: "Daniel Campoverde [alx741]" Date: Thu, 15 Sep 2016 18:53:10 -0500 Subject: [PATCH 0491/1435] Use 'STLink' in man pages --- doc/man/st-info.md | 4 ++-- doc/man/st-util.md | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/man/st-info.md b/doc/man/st-info.md index 9cc48e9f1..34192b9d6 100644 --- a/doc/man/st-info.md +++ b/doc/man/st-info.md @@ -4,7 +4,7 @@ # NAME -st-info - Provides information about connected STLINK and STM32 devices +st-info - Provides information about connected STLink and STM32 devices # SYNOPSIS @@ -12,7 +12,7 @@ st-info - Provides information about connected STLINK and STM32 devices # DESCRIPTION -Provides information about connected STLINK programmers and STM32 devices: +Provides information about connected STLink programmers and STM32 devices: Serial code, openocd, flash, sram, page size, chipid, description. diff --git a/doc/man/st-util.md b/doc/man/st-util.md index 8f015c806..2b68a56fd 100644 --- a/doc/man/st-util.md +++ b/doc/man/st-util.md @@ -20,7 +20,7 @@ default **4242** port will be used. Stlink version 2 is used by default unless the option **--stlinkv1** is given. -The STLINKv2 device to use can be specified in the environment +The STLinkV2 device to use can be specified in the environment variable STLINK_DEVICE on the format :. From 4209e4b924165dc46a8f6c0cf4338f4d321ee08b Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 15 Sep 2016 22:29:59 +0200 Subject: [PATCH 0492/1435] cmake: Refactor into seperate files, fix project version detection when everything fails (travis) --- .travis.sh | 4 +- .travis.yml | 4 +- CMakeLists.txt | 254 ++++-------------- cmake/CFlags.cmake | 49 ++++ cmake/CPackConfig.cmake | 11 + cmake/Version.cmake | 50 ++++ cmake/modules/Find7Zip.cmake | 8 +- cmake/modules/FindLibUSB.cmake | 2 + doc/man/CMakeLists.txt | 27 +- include/CMakeLists.txt | 12 +- include/stlink.h | 1 + include/stlink/version.h.in | 9 + src/gdbserver/CMakeLists.txt | 10 + src/gdbserver/gdb-server.c | 5 +- src/logging.c | 2 +- src/tools/flash.c | 2 + src/tools/gui/CMakeLists.txt | 24 ++ src/tools/info.c | 1 + usr/lib/pkgconfig/CMakeLists.txt | 14 + .../lib/pkgconfig/pkg-config.pc.cmake | 0 20 files changed, 268 insertions(+), 221 deletions(-) create mode 100644 cmake/CFlags.cmake create mode 100644 cmake/CPackConfig.cmake create mode 100644 cmake/Version.cmake create mode 100644 include/stlink/version.h.in create mode 100644 src/gdbserver/CMakeLists.txt create mode 100644 src/tools/gui/CMakeLists.txt create mode 100644 usr/lib/pkgconfig/CMakeLists.txt rename pkg-config.pc.cmake => usr/lib/pkgconfig/pkg-config.pc.cmake (100%) diff --git a/.travis.sh b/.travis.sh index 9fa519dad..82c1fd862 100755 --- a/.travis.sh +++ b/.travis.sh @@ -13,7 +13,7 @@ else fi echo "=== Building Debug" -mkdir -p build/Debug && cd build/Debug && cmake -DCMAKE_BUILD_TYPE=Debug ../../ && make && make package && cd - +mkdir -p build/Debug && cd build/Debug && cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ && make && make package && cd - echo "=== Building Release" -mkdir -p build/Release && cd build/Release && cmake -DCMAKE_BUILD_TYPE=Release ../../ && make && make package && cd - +mkdir -p build/Release && cd build/Release && cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ && make && make package && cd - diff --git a/.travis.yml b/.travis.yml index 543c0edec..2bf170d2b 100644 --- a/.travis.yml +++ b/.travis.yml @@ -11,6 +11,9 @@ addons: - g++-5 - gcc-5 script: + - git fetch --tags + - printenv + - cmake --version - ./.travis.sh matrix: include: @@ -20,7 +23,6 @@ matrix: # compiler: clang-3.8 - os: linux compiler: gcc-5 - compiler: gcc-5 # - os: linux # compiler: clang-3.8 - os: osx diff --git a/CMakeLists.txt b/CMakeLists.txt index 9195e3345..2d5a03170 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,9 +2,7 @@ cmake_minimum_required(VERSION 2.8.7) project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics Stlink Tools") -include(CheckCCompilerFlag) include(CheckIncludeFile) -find_package(PkgConfig) if (POLICY CMP0042) # Newer cmake on MacOS should use @rpath @@ -12,123 +10,30 @@ if (POLICY CMP0042) endif () set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") +include(cmake/Version.cmake) +include(cmake/CFlags.cmake) -message(STATUS "Building on ${CMAKE_SYSTEM_NAME}") - -# Determine package version. -find_package (Git QUIET) -if (DEFINED ENV{TRAVIS_TAG} AND NOT "$ENV{TRAVIS_TAG}" STREQUAL "") - set (STLINK_PACKAGE_VERSION "$ENV{TRAVIS_TAG}") -elseif (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") - # Working off a git repo, using git versioning - # Check if HEAD is pointing to a tag - execute_process ( - COMMAND "${GIT_EXECUTABLE}" describe --always - WORKING_DIRECTORY "${PROJECT_SOURCE_DIR}" - OUTPUT_VARIABLE STLINK_PACKAGE_VERSION - OUTPUT_STRIP_TRAILING_WHITESPACE) - - # If the sources have been changed locally, add -dirty to the version. - execute_process ( - COMMAND "${GIT_EXECUTABLE}" diff --quiet - WORKING_DIRECTORY "${PROJECT_SOURCE_DIR}" - RESULT_VARIABLE res) - - if (res EQUAL 1) - set (STLINK_PACKAGE_VERSION "${STLINK_PACKAGE_VERSION}-dirty") - endif() -elseif (EXISTS ${PROJECT_SOURCE_DIR}/.version) - # If git is not available (e.g. when building from source package) - # we can extract the package version from .version file. - file (STRINGS .version STLINK_PACKAGE_VERSION) -else () - set (STLINK_PACKAGE_VERSION "999.99.99-unknown") -endif() - -# We shall use STLINK_PACKAGE_VERSION* variables to set soversion and other stuff -# Since these numbers will appear in .so names, e.g. libstlink.so.1.2.0 -# We can't just use STLINK_PACKAGE_VERSION here -# (Well, we can, but that breaks all the existing conventions) -# We can't as well use PROJECT_VERSION* variables here, since they are managed -# by project() directive and the whole version detection relies on PROJECT_SOURCE_DIR - -string(REPLACE "." ";" STLINK_PACKAGE_VERSION_ARRAY ${STLINK_PACKAGE_VERSION}) -string(REPLACE "-" ";" STLINK_PACKAGE_VERSION_ARRAY "${STLINK_PACKAGE_VERSION_ARRAY}") -list(GET STLINK_PACKAGE_VERSION_ARRAY 0 STLINK_PACKAGE_VERSION_MAJOR) -list(GET STLINK_PACKAGE_VERSION_ARRAY 1 STLINK_PACKAGE_VERSION_MINOR) -list(GET STLINK_PACKAGE_VERSION_ARRAY 2 STLINK_PACKAGE_VERSION_PATCH) -list(GET STLINK_PACKAGE_VERSION_ARRAY 3 STLINK_PACKAGE_VERSION_TAG) - -if(WIN32) - find_package(7Zip REQUIRED) - message(STATUS "7Zip Location: " ${ZIP_LOCATION}) -endif() - +### +# Dependencies +### find_package(LibUSB REQUIRED) if (NOT APPLE AND NOT WIN32) find_package(PkgConfig) pkg_check_modules(gtk gtk+-3.0) endif () -function(add_cflag_if_supported flag) - string(REPLACE "-" "_" flagclean ${flag}) - string(REPLACE "=" "_" flagclean ${flagclean}) - string(REPLACE "+" "_" flagclean ${flagclean}) - string(REPLACE "," "_" flagclean ${flagclean}) - string(TOUPPER ${flagclean} flagclean) - - check_c_compiler_flag(${flag} C_SUPPORTS${flagclean}) - - if (C_SUPPORTS${flagclean}) - set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${flag}" PARENT_SCOPE) - endif() -endfunction() - -add_cflag_if_supported("-std=gnu99") -add_cflag_if_supported("-Wall") -add_cflag_if_supported("-Wextra") -add_cflag_if_supported("-Wshadow") -add_cflag_if_supported("-D_FORTIFY_SOURCE=2") -add_cflag_if_supported("-fstrict-aliasing") -add_cflag_if_supported("-Wformat") -add_cflag_if_supported("-Wformat-security") -add_cflag_if_supported("-Wmaybe-uninitialized") -add_cflag_if_supported("-Wmissing-variable-declarations") -add_cflag_if_supported("-Wshorten-64-to-32") -add_cflag_if_supported("-Wimplicit-function-declaration") - -## -# On OpenBSD the system headers suck so we need to disable redundant declaration check -# /usr/include/unistd.h:429: warning: redundant redeclaration of 'truncate' -# /usr/include/sys/types.h:218: warning: previous declaration of 'truncate' was here -## -if (NOT CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") - add_cflag_if_supported("-Wredundant-decls") -endif () - -add_cflag_if_supported("-Wundef") -if (NOT WIN32) - add_cflag_if_supported("-fPIC") -endif () - -if (CMAKE_BUILD_TYPE STREQUAL "") - set (CMAKE_BUILD_TYPE "Debug") -endif () - -if(${CMAKE_BUILD_TYPE} MATCHES "Debug") - add_cflag_if_supported("-ggdb") - add_cflag_if_supported("-O0") - include(CTest) -elseif() - add_cflag_if_supported("-O2") -endif() - CHECK_INCLUDE_FILE(sys/mman.h STLINK_HAVE_SYS_MMAN_H) if (STLINK_HAVE_SYS_MMAN_H) add_definitions(-DSTLINK_HAVE_SYS_MMAN_H) endif() -message("Building ${PROJECT_NAME} ${STLINK_PACKAGE_VERSION}") +if (CMAKE_BUILD_TYPE STREQUAL "") + set(CMAKE_BUILD_TYPE "Debug") +endif() + +if (${CMAKE_BUILD_TYPE} MATCHES "Debug") + include(CTest) +endif() set(STLINK_HEADERS include/stlink.h @@ -155,31 +60,26 @@ endif () include_directories(${LIBUSB_INCLUDE_DIR}) include_directories(include) +include_directories(${PROJECT_BINARY_DIR}/include) include_directories(src/mingw) -set(STLINK_LIB_STATIC ${PROJECT_NAME}-static) - +# Shared library add_library(${PROJECT_NAME} SHARED - ${STLINK_HEADERS} # header files for ide projects generated by cmake - ${STLINK_SOURCE}) + ${STLINK_HEADERS} # header files for ide projects generated by cmake + ${STLINK_SOURCE} +) target_link_libraries(${PROJECT_NAME} ${LIBUSB_LIBRARY}) if (WIN32 OR MSYS OR MINGW) - set(STLINK_SHARED_VERSION - ${STLINK_PACKAGE_VERSION_MAJOR}.${STLINK_PACKAGE_VERSION_MINOR}) + set(STLINK_SHARED_VERSION ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}) else() - set(STLINK_SHARED_VERSION - ${STLINK_PACKAGE_VERSION_MAJOR}.${STLINK_PACKAGE_VERSION_MINOR}.${STLINK_PACKAGE_VERSION_PATCH}) + set(STLINK_SHARED_VERSION ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}) endif() -set_target_properties(${PROJECT_NAME} PROPERTIES SOVERSION ${STLINK_PACKAGE_VERSION_MAJOR} -VERSION ${STLINK_SHARED_VERSION}) - -add_library(${STLINK_LIB_STATIC} STATIC - ${STLINK_HEADERS} # header files for ide projects generated by cmake - ${STLINK_SOURCE}) -target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY}) -set_target_properties(${STLINK_LIB_STATIC} PROPERTIES OUTPUT_NAME ${PROJECT_NAME}) +set_target_properties(${PROJECT_NAME} + PROPERTIES SOVERSION ${PROJECT_VERSION_MAJOR} + VERSION ${STLINK_SHARED_VERSION} +) if (APPLE) find_library(ObjC objc) @@ -194,91 +94,49 @@ else() target_link_libraries(${PROJECT_NAME} ${LIBUSB_LIBRARY}) endif() -add_executable(st-flash src/tools/flash.c src/tools/flash_opts.c) -target_link_libraries(st-flash ${PROJECT_NAME}) - -add_executable(st-info src/tools/info.c) -target_link_libraries(st-info ${PROJECT_NAME}) - -add_executable(st-util src/gdbserver/gdb-remote.c - src/gdbserver/gdb-remote.h - src/gdbserver/gdb-server.c - src/gdbserver/gdb-server.h - src/gdbserver/semihosting.c - src/gdbserver/semihosting.h) - -target_link_libraries(st-util ${PROJECT_NAME}) - -install(TARGETS ${PROJECT_NAME} ${STLINK_LIB_STATIC} st-flash st-util st-info - RUNTIME DESTINATION bin - ARCHIVE DESTINATION lib/${CMAKE_LIBRARY_PATH} - LIBRARY DESTINATION lib/${CMAKE_LIBRARY_PATH} +install(TARGETS ${PROJECT_NAME} + LIBRARY DESTINATION lib/${CMAKE_LIBRARY_PATH} ) -if (NOT APPLE AND NOT WIN32) - set(PKG_CONFIG_LIBDIR - "\${prefix}/lib/\${deb_host_multiarch}" - ) - set(PKG_CONFIG_INCLUDEDIR - "\${prefix}/include/\${deb_host_multiarch}/${PROJECT_NAME}-${STLINK_PACKAGE_VERSION}" - ) - set(PKG_CONFIG_LIBS - "-L\${libdir} -l:libstlink.so.${STLINK_PACKAGE_VERSION_MAJOR}" - ) - set(PKG_CONFIG_CFLAGS - "-I\${includedir}" - ) - - set(PKG_CONFIG_REQUIRES - "libusb-1.0" - ) +### +# Static library +### +set(STLINK_LIB_STATIC ${PROJECT_NAME}-static) - configure_file( - "${CMAKE_CURRENT_SOURCE_DIR}/pkg-config.pc.cmake" - "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" - ) +add_library(${STLINK_LIB_STATIC} STATIC + ${STLINK_HEADERS} # header files for ide projects generated by cmake + ${STLINK_SOURCE} +) +target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY}) +set_target_properties(${STLINK_LIB_STATIC} PROPERTIES OUTPUT_NAME ${PROJECT_NAME}) - install(FILES "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" - DESTINATION lib/${CMAKE_LIBRARY_PATH}/pkgconfig/) -endif() +install(TARGETS ${STLINK_LIB_STATIC} + ARCHIVE DESTINATION lib/${CMAKE_LIBRARY_PATH} +) -if (NOT APPLE AND gtk_FOUND) - include_directories(SYSTEM ${gtk_INCLUDE_DIRS}) - set(GUI_SOURCES src/tools/gui/stlink-gui.c - src/tools/gui/stlink-gui.h) +### +# Tools +### +add_executable(st-flash src/tools/flash.c src/tools/flash_opts.c) +target_link_libraries(st-flash ${PROJECT_NAME}) - # TODO REMOVE whole stlink-gui-local target, fixup auto-search of ui file in implementation - add_executable(stlink-gui-local ${GUI_SOURCES}) - set_target_properties(stlink-gui-local PROPERTIES - COMPILE_FLAGS -DSTLINK_UI_DIR=\\"${CMAKE_CURRENT_SOURCE_DIR}/gui\\") - target_link_libraries(stlink-gui-local stlink ${gtk_LDFLAGS}) +add_executable(st-info src/tools/info.c) +target_link_libraries(st-info ${PROJECT_NAME}) - set(INSTALLED_UI_DIR share/stlink) - add_executable(stlink-gui ${GUI_SOURCES}) - # TODO REMOVE, fixup auto-search of ui file in implementation - set_target_properties(stlink-gui PROPERTIES - COMPILE_FLAGS -DSTLINK_UI_DIR=\\"${CMAKE_INSTALL_PREFIX}/${INSTALLED_UI_DIR}\\") - target_link_libraries(stlink-gui stlink ${gtk_LDFLAGS}) +install(TARGETS st-flash st-info + RUNTIME DESTINATION bin +) - install(TARGETS stlink-gui - RUNTIME DESTINATION bin) - install(FILES src/tools/gui/stlink-gui.ui - DESTINATION ${INSTALLED_UI_DIR}) -endif() +add_subdirectory(src/gdbserver) +add_subdirectory(src/tools/gui) +### +# Others +### +add_subdirectory(usr/lib/pkgconfig) add_subdirectory(include) add_subdirectory(doc/man) add_subdirectory(tests) -set (CPACK_PACKAGE_NAME ${PROJECT_NAME}) -set (CPACK_PACKAGE_VERSION ${STLINK_PACKAGE_VERSION}) -set (CPACK_SOURCE_GENERATOR "TBZ2;ZIP") -set (CPACK_SOURCE_IGNORE_FILES "/build/;/.git/;~$;${CPACK_SOURCE_IGNORE_FILES}") -set (CPACK_SOURCE_PACKAGE_FILE_NAME "${PROJECT_NAME}-${STLINK_PACKAGE_VERSION}") -if (APPLE) - set(CPACK_GENERATOR "ZIP") - file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/osx") - set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/osx") -endif() -add_custom_target(dist COMMAND ${CMAKE_MAKE_PROGRAM} package_source) -include (CPack) +include(cmake/CPackConfig.cmake) +include(CPack) diff --git a/cmake/CFlags.cmake b/cmake/CFlags.cmake new file mode 100644 index 000000000..b17463707 --- /dev/null +++ b/cmake/CFlags.cmake @@ -0,0 +1,49 @@ +include(CheckCCompilerFlag) + +function(add_cflag_if_supported flag) + string(REPLACE "-" "_" flagclean ${flag}) + string(REPLACE "=" "_" flagclean ${flagclean}) + string(REPLACE "+" "_" flagclean ${flagclean}) + string(REPLACE "," "_" flagclean ${flagclean}) + string(TOUPPER ${flagclean} flagclean) + + check_c_compiler_flag(${flag} C_SUPPORTS${flagclean}) + + if (C_SUPPORTS${flagclean}) + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${flag}" PARENT_SCOPE) + endif() +endfunction() + +add_cflag_if_supported("-std=gnu99") +add_cflag_if_supported("-Wall") +add_cflag_if_supported("-Wextra") +add_cflag_if_supported("-Wshadow") +add_cflag_if_supported("-D_FORTIFY_SOURCE=2") +add_cflag_if_supported("-fstrict-aliasing") +add_cflag_if_supported("-Wundef") +add_cflag_if_supported("-Wformat") +add_cflag_if_supported("-Wformat-security") +add_cflag_if_supported("-Wmaybe-uninitialized") +add_cflag_if_supported("-Wmissing-variable-declarations") +add_cflag_if_supported("-Wshorten-64-to-32") +add_cflag_if_supported("-Wimplicit-function-declaration") + +## +# On OpenBSD the system headers suck so we need to disable redundant declaration check +# /usr/include/unistd.h:429: warning: redundant redeclaration of 'truncate' +# /usr/include/sys/types.h:218: warning: previous declaration of 'truncate' was here +## +if (NOT CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") + add_cflag_if_supported("-Wredundant-decls") +endif () + +if (NOT WIN32) + add_cflag_if_supported("-fPIC") +endif () + +if(${CMAKE_BUILD_TYPE} MATCHES "Debug") + add_cflag_if_supported("-ggdb") + add_cflag_if_supported("-O0") +elseif() + add_cflag_if_supported("-O2") +endif() diff --git a/cmake/CPackConfig.cmake b/cmake/CPackConfig.cmake new file mode 100644 index 000000000..4e851efae --- /dev/null +++ b/cmake/CPackConfig.cmake @@ -0,0 +1,11 @@ +set (CPACK_PACKAGE_NAME ${PROJECT_NAME}) +set (CPACK_PACKAGE_VERSION ${PROJECT_VERSION}) +set (CPACK_SOURCE_GENERATOR "TBZ2;ZIP") +set (CPACK_SOURCE_IGNORE_FILES "/build/;/.git/;~$;${CPACK_SOURCE_IGNORE_FILES}") +set (CPACK_SOURCE_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}") +if (APPLE) + set(CPACK_GENERATOR "ZIP") + file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/osx") + set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/osx") +endif() +add_custom_target(dist COMMAND ${CMAKE_MAKE_PROGRAM} package_source) diff --git a/cmake/Version.cmake b/cmake/Version.cmake new file mode 100644 index 000000000..957e29ca4 --- /dev/null +++ b/cmake/Version.cmake @@ -0,0 +1,50 @@ +# Determine project version +# * Using Git +# * Local .version file +find_package (Git QUIET) +if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") + # Working off a git repo, using git versioning + # Check if HEAD is pointing to a tag + execute_process ( + COMMAND "${GIT_EXECUTABLE}" describe --always + WORKING_DIRECTORY "${PROJECT_SOURCE_DIR}" + OUTPUT_VARIABLE PROJECT_VERSION + OUTPUT_STRIP_TRAILING_WHITESPACE) + + # If the sources have been changed locally, add -dirty to the version. + execute_process ( + COMMAND "${GIT_EXECUTABLE}" diff --quiet + WORKING_DIRECTORY "${PROJECT_SOURCE_DIR}" + RESULT_VARIABLE res) + + if (res EQUAL 1) + set (PROJECT_VERSION "${PROJECT_VERSION}-dirty") + endif() +endif() + +string(REGEX REPLACE "^(0|[1-9][0-9]*)[.](0|[1-9][0-9]*)[.](0|[1-9][0-9]*)(-[.0-9A-Za-z-]+)?([+][.0-9A-Za-z-]+)?$" + "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) +list(LENGTH PROJECT_VERSION_LIST len) +if(len EQUAL 3) + list(GET PROJECT_VERSION_LIST 0 PROJECT_VERSION_MAJOR) + list(GET PROJECT_VERSION_LIST 1 PROJECT_VERSION_MINOR) + list(GET PROJECT_VERSION_LIST 2 PROJECT_VERSION_PATCH) +elseif(EXISTS ${PROJECT_SOURCE_DIR}/.version) + # If git is not available (e.g. when building from source package) + # we can extract the package version from .version file. + file (STRINGS .version PROJECT_VERSION) + + # TODO create function to extract semver from file or string and check if it is correct instead of copy-pasting + string(REGEX REPLACE "^(0|[1-9][0-9]*)[.](0|[1-9][0-9]*)[.](0|[1-9][0-9]*)(-[.0-9A-Za-z-]+)?([+][.0-9A-Za-z-]+)?$" + "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) + list(GET PROJECT_VERSION_LIST 0 PROJECT_VERSION_MAJOR) + list(GET PROJECT_VERSION_LIST 1 PROJECT_VERSION_MINOR) + list(GET PROJECT_VERSION_LIST 2 PROJECT_VERSION_PATCH) +else() + message(FATAL_ERROR "Unable to determine project version") +endif() + +if (${CMAKE_BUILD_TYPE} MATCHES "Debug") + message(STATUS "stlink version: ${PROJECT_VERSION}") + message(STATUS " Major ${PROJECT_VERSION_MAJOR} Minor ${PROJECT_VERSION_MINOR} Patch ${PROJECT_VERSION_PATCH}") +endif() diff --git a/cmake/modules/Find7Zip.cmake b/cmake/modules/Find7Zip.cmake index c264d12f7..3448a2856 100644 --- a/cmake/modules/Find7Zip.cmake +++ b/cmake/modules/Find7Zip.cmake @@ -1,5 +1,5 @@ -find_program(ZIP_LOCATION NAMES 7z.exe - HINTS - "C:\\Program Files\\7-Zip\\" - "C:\\Program Files (x86)\\7-Zip\\" +find_program(ZIP_EXECUTABLE NAMES 7z.exe + HINTS + "C:\\Program Files\\7-Zip\\" + "C:\\Program Files (x86)\\7-Zip\\" ) diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index 006ab6976..90aafb3a2 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -7,6 +7,8 @@ # LIBUSB_DEFINITIONS - Compiler switches required for using libusb if(WIN32 OR CMAKE_VS_PLATFORM_NAME OR MINGW OR MSYS) + find_package(7Zip REQUIRED) + set(LIBUSB_WIN_VERSION 1.0.20) set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 96e1734d8..4ea25e797 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -16,16 +16,21 @@ if(${CMAKE_BUILD_TYPE} MATCHES "Debug") PANDOC_DIRECTIVES -s -t man PRODUCT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} ) - - install(FILES ${CMAKE_CURRENT_BINARY_DIR}/${manpage}.1 - DESTINATION share/man/man1 - ) - endforeach() -else() - # TODO(xor-gate): we should generate a install list for Release and Debug targets - foreach(manpage ${MANPAGES}) - install(FILES ${manpage}.1 - DESTINATION share/man/man1 - ) endforeach() endif() + +# Install from output folder or this folder +foreach(manpage ${MANPAGES}) + if(EXISTS ${CMAKE_CURRENT_BINARY_DIR}/${manpage}.1) + set(f "${CMAKE_CURRENT_BINARY_DIR}/${manpage}.1") + elseif(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${manpage}.1") + set(f "${CMAKE_CURRENT_SOURCE_DIR}/${manpage}.1") + else() + message(AUTHOR_WARNING "Manpage ${manpage} not generated") + endif() + + if (f) + install(FILES ${f} DESTINATION ${CMAKE_INSTALL_PREFIX}/share/man/man1) + unset(f) + endif() +endforeach() diff --git a/include/CMakeLists.txt b/include/CMakeLists.txt index 5f603df8c..0b5a443c0 100644 --- a/include/CMakeLists.txt +++ b/include/CMakeLists.txt @@ -1,8 +1,14 @@ +configure_file( + "${PROJECT_SOURCE_DIR}/include/stlink/version.h.in" + "${CMAKE_BINARY_DIR}/include/stlink/version.h" +) file(GLOB STLINK_HEADERS "stlink/*.h" + "${CMAKE_BINARY_DIR}/include/stlink/*.h" ) - install(FILES ${CMAKE_SOURCE_DIR}/include/stlink.h - DESTINATION include/${CMAKE_LIBRARY_PATH}) + DESTINATION include/${CMAKE_LIBRARY_PATH} +) install(FILES ${STLINK_HEADERS} - DESTINATION include/${CMAKE_LIBRARY_PATH}/stlink) + DESTINATION include/${CMAKE_LIBRARY_PATH}/stlink +) diff --git a/include/stlink.h b/include/stlink.h index 0f032614e..674aa3b28 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -212,6 +212,7 @@ typedef struct flash_loader { #include "stlink/commands.h" #include "stlink/chipid.h" #include "stlink/flash_loader.h" +#include "stlink/version.h" #ifdef __cplusplus } diff --git a/include/stlink/version.h.in b/include/stlink/version.h.in new file mode 100644 index 000000000..4ce2a5cac --- /dev/null +++ b/include/stlink/version.h.in @@ -0,0 +1,9 @@ +#ifndef STLINK_VERSION_H_ +#define STLINK_VERSION_H_ + +#define STLINK_VERSION "@PROJECT_VERSION@" +#define STLINK_VERSION_MAJOR @PROJECT_VERSION_MAJOR@ +#define STLINK_VERSION_MINOR @PROJECT_VERSION_MINOR@ +#define STLINK_VERSION_PATCH @PROJECT_VERSION_PATCH@ + +#endif /* STLINK_VERSION_ */ diff --git a/src/gdbserver/CMakeLists.txt b/src/gdbserver/CMakeLists.txt new file mode 100644 index 000000000..c6114f6d6 --- /dev/null +++ b/src/gdbserver/CMakeLists.txt @@ -0,0 +1,10 @@ +add_executable(st-util gdb-remote.c + gdb-remote.h + gdb-server.c + gdb-server.h + semihosting.c + semihosting.h) +target_link_libraries(st-util ${PROJECT_NAME}) +install(TARGETS st-util + RUNTIME DESTINATION bin +) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 4d52d0cba..6015ed00b 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -176,12 +176,16 @@ int main(int argc, char** argv) { st_state_t state; memset(&state, 0, sizeof(state)); + + printf("st-util %s (%s)\n", STLINK_VERSION); + // set defaults... state.stlink_version = 2; state.logging_level = DEFAULT_LOGGING_LEVEL; state.listen_port = DEFAULT_GDB_LISTEN_PORT; state.reset = 1; /* By default, reset board */ parse_options(argc, argv, &state); + switch (state.stlink_version) { case 2: sl = stlink_open_usb(state.logging_level, state.reset, NULL); @@ -205,7 +209,6 @@ int main(int argc, char** argv) { ILOG("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); sl->verbose=0; - current_memory_map = make_memory_map(sl); #ifdef __MINGW32__ diff --git a/src/logging.c b/src/logging.c index 4969c4400..1f51900b5 100644 --- a/src/logging.c +++ b/src/logging.c @@ -11,7 +11,7 @@ #include "stlink/logging.h" -static int max_level; +static int max_level = UINFO; int ugly_init(int maximum_threshold) { max_level = maximum_threshold; diff --git a/src/tools/flash.c b/src/tools/flash.c index 2dde37d06..6ebfcc2fb 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -52,6 +52,8 @@ int main(int ac, char** av) return -1; } + printf("st-flash %s (%s)\n", STLINK_VERSION); + if (o.devname != NULL) /* stlinkv1 */ sl = stlink_v1_open(o.log_level, 1); else /* stlinkv2 */ diff --git a/src/tools/gui/CMakeLists.txt b/src/tools/gui/CMakeLists.txt new file mode 100644 index 000000000..e217af03a --- /dev/null +++ b/src/tools/gui/CMakeLists.txt @@ -0,0 +1,24 @@ +if (NOT gtk_FOUND) + return() +endif() + +set(GUI_SOURCES stlink-gui.c stlink-gui.h) +set(INSTALLED_UI_DIR share/stlink) + +include_directories(SYSTEM ${gtk_INCLUDE_DIRS}) + +add_executable(stlink-gui-local ${GUI_SOURCES}) +set_target_properties(stlink-gui-local PROPERTIES + COMPILE_FLAGS -DSTLINK_UI_DIR=\\"${CMAKE_CURRENT_SOURCE_DIR}/gui\\") +target_link_libraries(stlink-gui-local stlink ${gtk_LDFLAGS}) + + +add_executable(stlink-gui ${GUI_SOURCES}) +set_target_properties(stlink-gui PROPERTIES + COMPILE_FLAGS -DSTLINK_UI_DIR=\\"${CMAKE_INSTALL_PREFIX}/${INSTALLED_UI_DIR}\\") +target_link_libraries(stlink-gui stlink ${gtk_LDFLAGS}) + +install(TARGETS stlink-gui + RUNTIME DESTINATION bin) +install(FILES stlink-gui.ui + DESTINATION ${INSTALLED_UI_DIR}) diff --git a/src/tools/info.c b/src/tools/info.c index d3a315150..58e34718a 100644 --- a/src/tools/info.c +++ b/src/tools/info.c @@ -145,6 +145,7 @@ int main(int ac, char** av) return -1; } + printf("st-info %s (%s)\n", STLINK_VERSION); err = print_data(av); return err; diff --git a/usr/lib/pkgconfig/CMakeLists.txt b/usr/lib/pkgconfig/CMakeLists.txt new file mode 100644 index 000000000..5ddc500ca --- /dev/null +++ b/usr/lib/pkgconfig/CMakeLists.txt @@ -0,0 +1,14 @@ +set(PKG_CONFIG_LIBDIR "\${prefix}/lib/\${deb_host_multiarch}") +set(PKG_CONFIG_INCLUDEDIR "\${prefix}/include/\${deb_host_multiarch}/${PROJECT_NAME}-${PROJECT_VERSION}") +set(PKG_CONFIG_LIBS "-L\${libdir} -l:libstlink.so.${PROJECT_VERSION_MAJOR}") +set(PKG_CONFIG_CFLAGS "-I\${includedir}") +set(PKG_CONFIG_REQUIRES "libusb-1.0") + +configure_file( + "${CMAKE_CURRENT_SOURCE_DIR}/pkg-config.pc.cmake" + "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" +) + +install(FILES "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" + DESTINATION lib/${CMAKE_LIBRARY_PATH}/pkgconfig/ +) diff --git a/pkg-config.pc.cmake b/usr/lib/pkgconfig/pkg-config.pc.cmake similarity index 100% rename from pkg-config.pc.cmake rename to usr/lib/pkgconfig/pkg-config.pc.cmake From 6f26487f83353d607a80f1516dadaf4019989994 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sun, 18 Sep 2016 11:17:25 +0200 Subject: [PATCH 0493/1435] Add --version commandline argument flag. Fixes #470 --- doc/man/st-flash.md | 3 +++ doc/man/st-info.md | 3 +++ doc/man/st-util.md | 3 +++ src/gdbserver/gdb-server.c | 21 ++++++++++----------- src/tools/flash.c | 3 ++- src/tools/flash_opts.c | 6 +++++- src/tools/info.c | 5 ++++- 7 files changed, 30 insertions(+), 14 deletions(-) diff --git a/doc/man/st-flash.md b/doc/man/st-flash.md index 88ba5870a..981bf3cd6 100644 --- a/doc/man/st-flash.md +++ b/doc/man/st-flash.md @@ -35,6 +35,9 @@ erase # OPTIONS +--version +: Print version information + --debug : TODO diff --git a/doc/man/st-info.md b/doc/man/st-info.md index 34192b9d6..d34d5b2b0 100644 --- a/doc/man/st-info.md +++ b/doc/man/st-info.md @@ -18,6 +18,9 @@ Serial code, openocd, flash, sram, page size, chipid, description. # OPTIONS +--version +: Print version information + --flash : Display amount of flash memory available in the device diff --git a/doc/man/st-util.md b/doc/man/st-util.md index 2b68a56fd..5bd93a46b 100644 --- a/doc/man/st-util.md +++ b/doc/man/st-util.md @@ -29,6 +29,9 @@ variable STLINK_DEVICE on the format :. -h, --help : Print this message. +--version +: Print version information + -v *XX*, --verbose=XX : Specify a specific verbosity level (0..99) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 6015ed00b..339cd1130 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -35,7 +35,7 @@ #define FLASH_PAGE (sl->flash_pgsz) static stlink_t *connected_stlink = NULL; -bool semihosting = false; +static bool semihosting = false; static const char hex[] = "0123456789abcdef"; @@ -79,11 +79,13 @@ int parse_options(int argc, char** argv, st_state_t *st) { {"listen_port", required_argument, NULL, 'p'}, {"multi", optional_argument, NULL, 'm'}, {"no-reset", optional_argument, NULL, 'n'}, + {"version", no_argument, NULL, 'V'}, {"semihosting", no_argument, NULL, SEMIHOSTING_OPTION}, {0, 0, 0, 0}, }; const char * help_str = "%s - usage:\n\n" " -h, --help\t\tPrint this help\n" + " -V, --version\t\tPrint the version\n" " -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n" " -v, --verbose\t\tSpecify generally verbose logging\n" " -s X, --stlink_version=X\n" @@ -112,12 +114,6 @@ int parse_options(int argc, char** argv, st_state_t *st) { while ((c = getopt_long(argc, argv, "hv::s:1p:mn", long_options, &option_index)) != -1) { switch (c) { case 0: - printf("XXXXX Shouldn't really normally come here, only if there's no corresponding option\n"); - printf("option %s", long_options[option_index].name); - if (optarg) { - printf(" with arg %s", optarg); - } - printf("\n"); break; case 'h': printf(help_str, argv[0]); @@ -155,6 +151,9 @@ int parse_options(int argc, char** argv, st_state_t *st) { case 'n': st->reset = 0; break; + case 'V': + printf("v%s\n", STLINK_VERSION); + exit(EXIT_SUCCESS); case SEMIHOSTING_OPTION: semihosting = true; break; @@ -170,15 +169,11 @@ int parse_options(int argc, char** argv, st_state_t *st) { return 0; } - int main(int argc, char** argv) { stlink_t *sl = NULL; - st_state_t state; memset(&state, 0, sizeof(state)); - printf("st-util %s (%s)\n", STLINK_VERSION); - // set defaults... state.stlink_version = 2; state.logging_level = DEFAULT_LOGGING_LEVEL; @@ -186,6 +181,8 @@ int main(int argc, char** argv) { state.reset = 1; /* By default, reset board */ parse_options(argc, argv, &state); + printf("st-util %s\n", STLINK_VERSION); + switch (state.stlink_version) { case 2: sl = stlink_open_usb(state.logging_level, state.reset, NULL); @@ -206,6 +203,8 @@ int main(int argc, char** argv) { stlink_reset(sl); } + + ILOG("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); sl->verbose=0; diff --git a/src/tools/flash.c b/src/tools/flash.c index 6ebfcc2fb..5cedb3815 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -35,6 +35,7 @@ static void usage(void) puts("stlinkv2 command line: ./st-flash [--debug] [--serial ] erase"); puts(" Use hex format for addr, and ."); puts(" Format may be 'binary' (default) or 'ihex', although must be specified for binary format only."); + puts(" ./st-flash [--version]"); } int main(int ac, char** av) @@ -52,7 +53,7 @@ int main(int ac, char** av) return -1; } - printf("st-flash %s (%s)\n", STLINK_VERSION); + printf("st-flash %s\n", STLINK_VERSION); if (o.devname != NULL) /* stlinkv1 */ sl = stlink_v1_open(o.log_level, 1); diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index 7de2ecde8..1a0d0cd9b 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -23,7 +23,11 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) // options while(ac >= 1) { - if (strcmp(av[0], "--debug") == 0) { + if (strcmp(av[0], "--version") == 0) { + printf("v%s\n", STLINK_VERSION); + exit(EXIT_SUCCESS); + } + else if (strcmp(av[0], "--debug") == 0) { o->log_level = DEBUG_LOG_LEVEL; } else if (strcmp(av[0], "--reset") == 0) { diff --git a/src/tools/info.c b/src/tools/info.c index 58e34718a..2e3efc64d 100644 --- a/src/tools/info.c +++ b/src/tools/info.c @@ -7,6 +7,7 @@ static void usage(void) { + puts("st-info --version"); puts("st-info --flash"); puts("st-info --sram"); puts("st-info --descr"); @@ -93,6 +94,9 @@ static int print_data(char **av) if (strcmp(av[1], "--probe") == 0) { stlink_probe(); return 0; + } else if (strcmp(av[1], "--version") == 0) { + printf("v%s\n", STLINK_VERSION); + return 0; } sl = stlink_open_first(); @@ -145,7 +149,6 @@ int main(int ac, char** av) return -1; } - printf("st-info %s (%s)\n", STLINK_VERSION); err = print_data(av); return err; From 043a928d8fd2b8c8a520471c67bf28d0487e3d17 Mon Sep 17 00:00:00 2001 From: texane Date: Sun, 18 Sep 2016 16:12:10 +0200 Subject: [PATCH 0494/1435] add generated manpages --- doc/man/st-flash.1 | 88 ++++++++++++++++++++++++++++++++++++++++++++++ doc/man/st-info.1 | 76 +++++++++++++++++++++++++++++++++++++++ doc/man/st-term.1 | 32 +++++++++++++++++ doc/man/st-util.1 | 9 ++++- 4 files changed, 204 insertions(+), 1 deletion(-) create mode 100644 doc/man/st-flash.1 create mode 100644 doc/man/st-info.1 create mode 100644 doc/man/st-term.1 diff --git a/doc/man/st-flash.1 b/doc/man/st-flash.1 new file mode 100644 index 000000000..252ffcba8 --- /dev/null +++ b/doc/man/st-flash.1 @@ -0,0 +1,88 @@ +.TH ST-FLASH 1 "Sep 2016" "Open Source STMicroelectronics Stlink Tools" "STLINK" +.SH NAME +.PP +st-flash - Flash binary files to STM32 device +.SH SYNOPSIS +.PP +\f[I]st-flash\f[] [\f[I]OPTIONS\f[]] {read|write|erase} [\f[I]FILE\f[]] + +.SH DESCRIPTION +.PP +Flash binary files to arbitrary sections of memory, or read arbitrary +addresses of memory out to a binary file. +.PP +You can use this instead of st-util(1) if you prefer, but remember to +use the \f[B]\&.bin\f[] image, rather than the \f[B]\&.elf\f[] file. +.PP +Use hexadecimal format for the \f[I]ADDR\f[] and \f[I]SIZE\f[]. +.SH COMMANDS +.TP +.B write \f[I]FILE\f[] \f[I]ADDR\f[] +Write firmware \f[I]FILE\f[] to device starting from \f[I]ADDR\f[] +.RS +.RE +.TP +.B read \f[I]FILE\f[] \f[I]ADDR\f[] \f[I]SIZE\f[] +Read firmware from device starting from \f[I]ADDR\f[] up to +\f[I]SIZE\f[] bytes to \f[I]FILE\f[] +.RS +.RE +.TP +.B erase +Perform a mass erasing of the device firmware +.RS +.RE +.SH OPTIONS +.TP +.B --version +Print version information +.RS +.RE +.TP +.B --debug +TODO +.RS +.RE +.TP +.B --reset +TODO +.RS +.RE +.TP +.B --serial \f[I]iSerial\f[] +TODO +.RS +.RE +.SH EXAMPLES +.PP +Flash \f[C]firmware.bin\f[] to device +.IP +.nf +\f[C] +$\ st-flash\ write\ firmware.bin\ 0x8000000 +\f[] +.fi +.PP +Read firmware from device (4096 bytes) +.IP +.nf +\f[C] +$\ st-flash\ read\ firmware.bin\ 0x8000000\ 4096 +\f[] +.fi +.PP +Erase firmware from device +.IP +.nf +\f[C] +$\ st-flash\ erase +\f[] +.fi +.SH SEE ALSO +.PP +st-util(1), st-info(1), st-term(1) +.SH COPYRIGHT +.PP +This work is copyrighted. +Stlink contributors. +See \f[I]LICENSE\f[] file in the stlink source distribution. diff --git a/doc/man/st-info.1 b/doc/man/st-info.1 new file mode 100644 index 000000000..8576d39e4 --- /dev/null +++ b/doc/man/st-info.1 @@ -0,0 +1,76 @@ +.TH ST-INFO 1 "Sep 2016" "Open Source STMicroelectronics Stlink Tools" "STLINK" +.SH NAME +.PP +st-info - Provides information about connected STLink and STM32 devices +.SH SYNOPSIS +.PP +\f[I]st-info\f[] [\f[I]OPTIONS\f[]] +.SH DESCRIPTION +.PP +Provides information about connected STLink programmers and STM32 +devices: Serial code, openocd, flash, sram, page size, chipid, +description. +.SH OPTIONS +.TP +.B --version +Print version information +.RS +.RE +.TP +.B --flash +Display amount of flash memory available in the device +.RS +.RE +.TP +.B --sram +Display amount of sram memory available in device +.RS +.RE +.TP +.B --descr +Display textual description of the device +.RS +.RE +.TP +.B --pagesize +Display the page size of the device +.RS +.RE +.TP +.B --chipid +Display the chip ID of the device +.RS +.RE +.TP +.B --serial +Display the serial code of the device +.RS +.RE +.TP +.B --hla-serial +Display the hex escaped serial code of the device +.RS +.RE +.TP +.B --probe +Display the summarized information of the connected programmers and +devices +.RS +.RE +.SH EXAMPLES +.PP +Display information about connected programmers and devices +.IP +.nf +\f[C] +$\ st-info\ --probe +\f[] +.fi +.SH SEE ALSO +.PP +st-util(1), st-flash(1), st-term(1) +.SH COPYRIGHT +.PP +This work is copyrighted. +Stlink contributors. +See \f[I]LICENSE\f[] file in the stlink source distribution. diff --git a/doc/man/st-term.1 b/doc/man/st-term.1 new file mode 100644 index 000000000..e6512540c --- /dev/null +++ b/doc/man/st-term.1 @@ -0,0 +1,32 @@ +.TH ST-TERM 1 "Sep 2016" "Open Source STMicroelectronics Stlink Tools" "STLINK" +.SH NAME +.PP +st-term - Serial terminal interface for debugging using STLink device +only +.SH SYNOPSIS +.PP +\f[I]st-term\f[] +.SH DESCRIPTION +.PP +Provides a serial terminal that works through the STLink device, +allowing to do the kind of debugging you would do using the UART of the +STM32 device without having to connect a UART-USB serial adapter dongle. +.PP +It works by having a magic number in sram of the MCU within a structure +that serves as IO buffer. +.PP +The required setup consist of some code that establishes the magic +number, buffer structure and helper functions for actual data +transmission between host and MCU. +.PP +\f[C]stlinky.h\f[] and \f[C]stlinky.c\f[] are available in the Antares +build system libraries source: +https://github.com/nekromant/antares/tree/master/include/lib +.SH SEE ALSO +.PP +st-util(1), st-info(1), st-term(1) +.SH COPYRIGHT +.PP +This work is copyrighted. +Stlink contributors. +See \f[I]LICENSE\f[] file in the stlink source distribution. diff --git a/doc/man/st-util.1 b/doc/man/st-util.1 index 674b0dbef..8fb791221 100644 --- a/doc/man/st-util.1 +++ b/doc/man/st-util.1 @@ -1,3 +1,5 @@ +.TH ST-UTIL 1 "Sep 2016" "Open Source STMicroelectronics Stlink Tools" "STLINK" +.SH NAME .PP st-util - Run GDB server to interact with STM32 device .SH SYNOPSIS @@ -14,7 +16,7 @@ option, the default \f[B]4242\f[] port will be used. Stlink version 2 is used by default unless the option \f[B]--stlinkv1\f[] is given. .PP -The STLINKv2 device to use can be specified in the environment variable +The STLinkV2 device to use can be specified in the environment variable STLINK_DEVICE on the format :. .SH OPTIONS .TP @@ -23,6 +25,11 @@ Print this message. .RS .RE .TP +.B --version +Print version information +.RS +.RE +.TP .B -v \f[I]XX\f[], --verbose=XX Specify a specific verbosity level (0..99) .RS From e407d9e5a9cb76767dba6539c7a9cf0a7b87ea24 Mon Sep 17 00:00:00 2001 From: Denis Osterland Date: Sun, 18 Sep 2016 10:52:03 +0200 Subject: [PATCH 0495/1435] deb: Fix broken install rules. Override dh_auto_install to use *.install files as they are. The debian/*.install could contain source to destination format too, but that would be much more difficult to handle with multi-arch. Add debian copyright file. Add stlink-tools manpages. Insert homepage link. Add library dependencies to binaries. Add howto debuild to README. Install udev rules. Install modprobe config for usb module. Configure cmake with /usr prefix and compile release variant. --- Makefile | 8 ++++---- README.md | 8 ++++++++ debian/control | 6 +++--- debian/copyright | 12 ++++++++++++ debian/libstlink.install | 2 ++ debian/rules | 37 ++++++++++++++++++++++++++++++++---- debian/stlink-tools.manpages | 1 + 7 files changed, 63 insertions(+), 11 deletions(-) create mode 100644 debian/copyright create mode 100644 debian/stlink-tools.manpages diff --git a/Makefile b/Makefile index d93c4b181..fca19d603 100644 --- a/Makefile +++ b/Makefile @@ -4,7 +4,7 @@ ## MAKEFLAGS += -s -all: debug +all: release ci: lint debug release test help: @@ -27,16 +27,16 @@ release: build/Release @echo "[RELEASE]" @$(MAKE) -C build/Release -test: build/Debug +test: debug @$(MAKE) -C build/Debug test build/Debug: @mkdir -p $@ - @cd $@ && cmake -DCMAKE_BUILD_TYPE=Debug ../../ + @cd $@ && cmake -DCMAKE_BUILD_TYPE=Debug $(CMAKEFLAGS) ../../ build/Release: @mkdir -p $@ - @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Release ../../ + @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Release $(CMAKEFLAGS) ../../ clean: @echo "[CLEAN]" diff --git a/README.md b/README.md index 2846a53d4..c3345910a 100644 --- a/README.md +++ b/README.md @@ -56,6 +56,14 @@ $ cmake -DCMAKE_BUILD_TYPE=Debug .. $ make ``` +### Build Debian Package +To build debian package you need debuild. + +``` +$ git archive --prefix=$(git describe)/ HEAD | bzip2 --stdout > ../libstlink_$(sed -En -e "s/.*\((.*)\).*/\1/" -e "1,1 p" debian/changelog).orig.tar.bz2 +$ debuild -uc -us +``` + ## Using the gdb server To run the gdb server: (you do not need sudo if you have set up diff --git a/debian/control b/debian/control index b9beac2fc..41c8e87a3 100644 --- a/debian/control +++ b/debian/control @@ -4,7 +4,7 @@ Maintainer: Andrew 'Necromant' Andrianov Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 3.9.5 Section: libs -Homepage: +Homepage: https://github.com/texane/stlink Vcs-Git: https://github.com/texane/stlink.git Vcs-Browser: https://github.com/texane/stlink @@ -24,11 +24,11 @@ Description: OpenSource ST-Link tools replacement. Shared library. Package: stlink-tools Section: libdevel Architecture: any -Depends: libstlink (= ${binary:Version}), ${misc:Depends} +Depends: libstlink (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} Description: OpenSource ST-Link tools replacement. Commandline Utilities. Package: stlink-gui Section: libdevel Architecture: any -Depends: libstlink (= ${binary:Version}), ${misc:Depends} +Depends: libstlink (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} Description: OpenSource ST-Link tools replacement. GUI Tool. diff --git a/debian/copyright b/debian/copyright new file mode 100644 index 000000000..e28d7e1bb --- /dev/null +++ b/debian/copyright @@ -0,0 +1,12 @@ +Format: http://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ +Upstream-Name: libstlink +Upstream-Contact: Andrew 'Necromant' Andrianov +Source: https://github.com/texane/stlink + +Files: * +Copyright: (c) 2011 The stlink project (github.com/texane/stlink) contributors. +License: BSD-3-clause + +Files: * +Copyright: (c) 2011 The "Capt'ns Missing Link" Authors. All rights reserved. +License: BSD-3-clause diff --git a/debian/libstlink.install b/debian/libstlink.install index 703ad8b31..9f7f9316b 100644 --- a/debian/libstlink.install +++ b/debian/libstlink.install @@ -1 +1,3 @@ usr/lib/*/lib*.so* +lib/udev/rules.d/*.rules +lib/modprobe.d/*.conf diff --git a/debian/rules b/debian/rules index 4979b59d7..419ce1e4d 100755 --- a/debian/rules +++ b/debian/rules @@ -21,8 +21,37 @@ include /usr/share/dpkg/default.mk %: dh $@ -# debmake generated override targets -# This is example for Cmake (See http://bugs.debian.org/641051 ) + +OUTDIR=build/Release +ROOTDIR=debian/tmp +DSTDIR=$(ROOTDIR)/usr +BINDIR=$(DSTDIR)/bin +SHAREDIR=$(DSTDIR)/share/stlink +LIBDIR=$(DSTDIR)/lib/$(if $(DEB_TARGET_MULTIARCH),$(DEB_TARGET_MULTIARCH),$(DEB_BUILD_MULTIARCH)) +UDEVDIR=$(ROOTDIR)/lib/udev/rules.d/ +MODDIR=$(ROOTDIR)/lib/modprobe.d/ + +export CMAKEFLAGS = \ + -DCMAKE_LIBRARY_PATH=$(DEB_HOST_MULTIARCH) \ + -DCMAKE_INSTALL_PREFIX=/usr \ + + override_dh_auto_configure: - dh_auto_configure -- \ - -DCMAKE_LIBRARY_PATH=$(DEB_HOST_MULTIARCH) + +override_dh_auto_install: + install -d $(DSTDIR)/include/stlink/tools + install -d $(LIBDIR)/pkgconfig + install -d $(BINDIR) + install -d $(SHAREDIR) + install -d $(UDEVDIR) + install -d $(MODDIR) + install -m644 $(wildcard include/*.h) $(DSTDIR)/include + install -m644 $(wildcard include/stlink/*.h) $(DSTDIR)/include/stlink + install -m644 $(wildcard include/stlink/tools/*.h) $(DSTDIR)/include/stlink/tools + install -m755 $(wildcard $(OUTDIR)/st-* $(OUTDIR)/src/gdbserver/st-* $(OUTDIR)/src/tools/gui/stlink-gui*) $(BINDIR) + cp -d $(wildcard $(OUTDIR)/libstlink.*) $(LIBDIR) + install -m644 $(OUTDIR)/usr/lib/pkgconfig/stlink.pc $(LIBDIR)/pkgconfig + install -m644 src/tools/gui/stlink-gui.ui $(SHAREDIR) + install -m644 etc/udev/rules.d/*.rules $(UDEVDIR) + install -m644 etc/modprobe.d/*.conf $(MODDIR) + diff --git a/debian/stlink-tools.manpages b/debian/stlink-tools.manpages new file mode 100644 index 000000000..6a461c09e --- /dev/null +++ b/debian/stlink-tools.manpages @@ -0,0 +1 @@ +doc/man/st-*.1 From 4bf6cb387f98e4b562f8e964af1deb32f7d40be0 Mon Sep 17 00:00:00 2001 From: Dave Flogeras Date: Wed, 21 Sep 2016 11:44:38 -0300 Subject: [PATCH 0496/1435] Do not issue JTAG reset on stlink-v1 --- src/usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/usb.c b/src/usb.c index 11e8dfe44..f32b2e04c 100644 --- a/src/usb.c +++ b/src/usb.c @@ -880,7 +880,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 } if (reset) { - stlink_jtag_reset(sl, 2); + if( sl->version.stlink_v > 1 ) stlink_jtag_reset(sl, 2); stlink_reset(sl); usleep(10000); } From 823079ad4dfeaa63bd8c1e1c0fc7d055a1c09c46 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 22 Sep 2016 21:06:35 +0200 Subject: [PATCH 0497/1435] Update README.md Update badge caching --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index c3345910a..78934eee8 100644 --- a/README.md +++ b/README.md @@ -1,8 +1,8 @@ Open source version of the STMicroelectronics Stlink Tools ========================================================== -[![GitHub release](https://img.shields.io/github/release/texane/stlink.svg?maxAge=2592000)](https://github.com/texane/stlink/releases/latest) -[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.2.0.svg?maxAge=2592000)](https://github.com/texane/stlink/compare/1.2.0...master) +[![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/texane/stlink/releases/latest) +[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.2.0.svg)](https://github.com/texane/stlink/compare/1.2.0...master) [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) [![Build Status](https://jenkins.ncrmnt.org/buildStatus/icon?job=GithubCI/stlink)](https://jenkins.ncrmnt.org/job/GithubCI/job/stlink/) [![Build status](https://ci.appveyor.com/api/projects/status/wrcie05d4jmut0te?svg=true)](https://ci.appveyor.com/project/xor-gate/stlink) From ee3f7a1cf111b481b76e7c9e1dd1739daea3c273 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 24 Sep 2016 23:57:25 +0200 Subject: [PATCH 0498/1435] Update README.md Update udev rules paragraph. --- README.md | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index 78934eee8..f54764b1b 100644 --- a/README.md +++ b/README.md @@ -134,9 +134,9 @@ for GDB. ## Setting up udev rules -For convenience, you may install udev rules file, 49-stlinkv*.rules, located -in the root of repository. You will need to copy it to /etc/udev/rules.d, -and then either reboot or execute +For convenience, you may install udev rule files, located +in the `etc/udev/rules.d` directory. You will need to copy it to /etc/udev/rules.d, +and then either execute as root (or reboot your machine): ``` $ udevadm control --reload-rules @@ -144,8 +144,6 @@ $ udevadm trigger ``` Udev will now create a /dev/stlinkv2_XX or /dev/stlinkv1_XX file, with the appropriate permissions. -This is currently all the device is for, (only one stlink of each version is supported at -any time presently) ## Running programs from SRAM From 650a88aa2c9feaee482d5ed6130fea15c6d3929e Mon Sep 17 00:00:00 2001 From: Andrew Andrianov Date: Fri, 23 Sep 2016 12:54:43 +0300 Subject: [PATCH 0499/1435] debian: Remove all useless stuff from debian/rules, force cmake buildsystem The top-level makefile that was used to drive cmake broke the autodetection of the used buildsystem by debhelper. This commit fixes it and moves most of the installation stuff to CMakeLists.txt to keep debian/ folder contents to the bare minimum. Signed-off-by: Andrew Andrianov --- CMakeLists.txt | 8 ++++++++ Makefile | 4 ++++ cmake/CPackConfig.cmake | 2 ++ debian/libstlink-dev.install | 2 ++ debian/libstlink.install | 4 ++-- debian/rules | 40 +++++------------------------------- debian/stlink-gui.install | 2 +- 7 files changed, 24 insertions(+), 38 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 2d5a03170..f648843a7 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -127,6 +127,14 @@ install(TARGETS st-flash st-info RUNTIME DESTINATION bin ) +if (CMAKE_SYSTEM_NAME STREQUAL "Linux") + file(GLOB RULES_FILES etc/udev/rules.d/*.rules) + install(FILES etc/modprobe.d/stlink_v1.conf + DESTINATION /etc) + install(FILES ${RULES_FILES} + DESTINATION /lib/udev/rules.d/) +endif() + add_subdirectory(src/gdbserver) add_subdirectory(src/tools/gui) diff --git a/Makefile b/Makefile index fca19d603..2ddfceee8 100644 --- a/Makefile +++ b/Makefile @@ -27,6 +27,10 @@ release: build/Release @echo "[RELEASE]" @$(MAKE) -C build/Release +package: build/Release + @echo "[PACKAGE] Release" + @$(MAKE) -C build/Release package + test: debug @$(MAKE) -C build/Debug test diff --git a/cmake/CPackConfig.cmake b/cmake/CPackConfig.cmake index 4e851efae..1dfd376be 100644 --- a/cmake/CPackConfig.cmake +++ b/cmake/CPackConfig.cmake @@ -3,6 +3,8 @@ set (CPACK_PACKAGE_VERSION ${PROJECT_VERSION}) set (CPACK_SOURCE_GENERATOR "TBZ2;ZIP") set (CPACK_SOURCE_IGNORE_FILES "/build/;/.git/;~$;${CPACK_SOURCE_IGNORE_FILES}") set (CPACK_SOURCE_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}") +set (CPACK_SET_DESTDIR "ON") +set (CPACK_INSTALL_PREFIX "${CMAKE_BINARY_DIR}/cpack/staging") if (APPLE) set(CPACK_GENERATOR "ZIP") file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/osx") diff --git a/debian/libstlink-dev.install b/debian/libstlink-dev.install index 1eff3299c..0c3543cd9 100644 --- a/debian/libstlink-dev.install +++ b/debian/libstlink-dev.install @@ -1,3 +1,5 @@ usr/include/* usr/lib/*/lib*.a usr/lib/*/pkgconfig/* +usr/lib/*/lib*.so + diff --git a/debian/libstlink.install b/debian/libstlink.install index 9f7f9316b..08981406e 100644 --- a/debian/libstlink.install +++ b/debian/libstlink.install @@ -1,3 +1,3 @@ -usr/lib/*/lib*.so* +usr/lib/*/lib*.so.* lib/udev/rules.d/*.rules -lib/modprobe.d/*.conf +etc/modprobe.d/*.conf diff --git a/debian/rules b/debian/rules index 419ce1e4d..2b826772b 100755 --- a/debian/rules +++ b/debian/rules @@ -16,42 +16,12 @@ include /usr/share/dpkg/default.mk # package maintainers to append LDFLAGS #export DEB_LDFLAGS_MAINT_APPEND = -Wl,--as-needed - # main packaging script based on dh7 syntax %: - dh $@ - - -OUTDIR=build/Release -ROOTDIR=debian/tmp -DSTDIR=$(ROOTDIR)/usr -BINDIR=$(DSTDIR)/bin -SHAREDIR=$(DSTDIR)/share/stlink -LIBDIR=$(DSTDIR)/lib/$(if $(DEB_TARGET_MULTIARCH),$(DEB_TARGET_MULTIARCH),$(DEB_BUILD_MULTIARCH)) -UDEVDIR=$(ROOTDIR)/lib/udev/rules.d/ -MODDIR=$(ROOTDIR)/lib/modprobe.d/ - -export CMAKEFLAGS = \ - -DCMAKE_LIBRARY_PATH=$(DEB_HOST_MULTIARCH) \ - -DCMAKE_INSTALL_PREFIX=/usr \ - + dh $@ --buildsystem cmake +# debmake generated override targets +# This is example for Cmake (See http://bugs.debian.org/641051 ) override_dh_auto_configure: - -override_dh_auto_install: - install -d $(DSTDIR)/include/stlink/tools - install -d $(LIBDIR)/pkgconfig - install -d $(BINDIR) - install -d $(SHAREDIR) - install -d $(UDEVDIR) - install -d $(MODDIR) - install -m644 $(wildcard include/*.h) $(DSTDIR)/include - install -m644 $(wildcard include/stlink/*.h) $(DSTDIR)/include/stlink - install -m644 $(wildcard include/stlink/tools/*.h) $(DSTDIR)/include/stlink/tools - install -m755 $(wildcard $(OUTDIR)/st-* $(OUTDIR)/src/gdbserver/st-* $(OUTDIR)/src/tools/gui/stlink-gui*) $(BINDIR) - cp -d $(wildcard $(OUTDIR)/libstlink.*) $(LIBDIR) - install -m644 $(OUTDIR)/usr/lib/pkgconfig/stlink.pc $(LIBDIR)/pkgconfig - install -m644 src/tools/gui/stlink-gui.ui $(SHAREDIR) - install -m644 etc/udev/rules.d/*.rules $(UDEVDIR) - install -m644 etc/modprobe.d/*.conf $(MODDIR) - + dh_auto_configure -- \ + -DCMAKE_LIBRARY_PATH=$(DEB_HOST_MULTIARCH) diff --git a/debian/stlink-gui.install b/debian/stlink-gui.install index eedcd7172..d18d2cec4 100644 --- a/debian/stlink-gui.install +++ b/debian/stlink-gui.install @@ -1,2 +1,2 @@ /usr/bin/stlink-gui* -/usr/share/* +/usr/share/stlink/stlink-gui.ui From e3975598fa20d7636c6827c562bcf8424cbb98d2 Mon Sep 17 00:00:00 2001 From: Geoffrey Brown Date: Sat, 15 Oct 2016 14:33:41 -0400 Subject: [PATCH 0500/1435] stm32l432 support --- include/stlink/chipid.h | 4 ++++ src/chipid.c | 16 ++++++++++++++++ src/common.c | 6 ++++-- src/flash_loader.c | 4 +++- 4 files changed, 27 insertions(+), 3 deletions(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 72094a733..7d25fc5ef 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -34,6 +34,7 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F37x = 0x432, STLINK_CHIPID_STM32_F4_DE = 0x433, STLINK_CHIPID_STM32_F4_DSI = 0x434, + STLINK_CHIPID_STM32_L43X = 0x435, /* * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus" * and some that are called "High". 0x427 is assigned to the other "Medium- @@ -54,6 +55,9 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F7 = 0x449, STLINK_CHIPID_STM32_F7XXXX = 0x451, STLINK_CHIPID_STM32_F410 = 0x458 + + + }; /** diff --git a/src/chipid.c b/src/chipid.c index 7f8bbd3f9..8a2f5ec94 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -406,6 +406,22 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) .bootrom_size = 0x7000 // 28k (per bank), same source as base }, + { + // STLINK_CHIPID_STM32_L43X + // From RM0392. + .chip_id = STLINK_CHIPID_STM32_L43X, + .description = "L4 device", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) + .flash_pagesize = 0x800, // 2K (sec 3.2, page 74; also appears in sec 3.3.1 and tables 7-8 on pages 75-76) + // SRAM1 is "up to" 64k in the standard Cortex-M memory map; + // SRAM2 is 16k mapped at at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0xc000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000 // 28k (per bank), same source as base + }, + }; diff --git a/src/common.c b/src/common.c index 74fa1043e..e8cdf3ba9 100644 --- a/src/common.c +++ b/src/common.c @@ -1417,7 +1417,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) unlock_flash_if(sl); /* select the page to erase */ - if (sl->chip_id == STLINK_CHIPID_STM32_L4) { + if (sl->chip_id == STLINK_CHIPID_STM32_L4 || sl->chip_id == STLINK_CHIPID_STM32_L43X) { // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); @@ -1767,7 +1767,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t unlock_flash_if(sl); /* TODO: Check that Voltage range is 2.7 - 3.6 V */ - if (sl->chip_id != STLINK_CHIPID_STM32_L4) { + if ((sl->chip_id != STLINK_CHIPID_STM32_L4) && + (sl->chip_id != STLINK_CHIPID_STM32_L43X)) + { if( sl->version.stlink_v == 1 ) { printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes on F4 devices\n"); write_flash_cr_psiz(sl, 2); diff --git a/src/flash_loader.c b/src/flash_loader.c index e05f35ae5..77ebd95eb 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -246,7 +246,9 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || sl->chip_id == STLINK_CHIPID_STM32_F0_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F09X) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); - } else if (sl->chip_id == STLINK_CHIPID_STM32_L4) { + } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || + (sl->chip_id == STLINK_CHIPID_STM32_L43X)) + { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { From 97052483cf016be9a45e1af9a8feb9e0429eb8db Mon Sep 17 00:00:00 2001 From: Geoffrey Brown Date: Sat, 15 Oct 2016 14:47:30 -0400 Subject: [PATCH 0501/1435] fixed formatting, description --- include/stlink/chipid.h | 3 --- src/chipid.c | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 7d25fc5ef..18f02782c 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -55,9 +55,6 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F7 = 0x449, STLINK_CHIPID_STM32_F7XXXX = 0x451, STLINK_CHIPID_STM32_F410 = 0x458 - - - }; /** diff --git a/src/chipid.c b/src/chipid.c index 8a2f5ec94..c6bcf70bb 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -410,7 +410,7 @@ static const struct stlink_chipid_params devices[] = { // STLINK_CHIPID_STM32_L43X // From RM0392. .chip_id = STLINK_CHIPID_STM32_L43X, - .description = "L4 device", + .description = "L43x device", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) .flash_pagesize = 0x800, // 2K (sec 3.2, page 74; also appears in sec 3.3.1 and tables 7-8 on pages 75-76) From cde9cb147bb4d35d207aaa85b02043b6d5a2a524 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 22 Oct 2016 09:25:43 +0200 Subject: [PATCH 0502/1435] doc: Remove remaining st-term man page --- doc/man/CMakeLists.txt | 1 - doc/man/st-flash.md | 2 +- doc/man/st-info.md | 2 +- doc/man/st-term.1 | 32 -------------------------------- doc/man/st-term.md | 36 ------------------------------------ doc/man/st-util.md | 2 +- 6 files changed, 3 insertions(+), 72 deletions(-) delete mode 100644 doc/man/st-term.1 delete mode 100644 doc/man/st-term.md diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 4ea25e797..55b419361 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -2,7 +2,6 @@ set(MANPAGES st-util st-flash st-info - st-term ) # Only generate manpages with pandoc in Debug builds diff --git a/doc/man/st-flash.md b/doc/man/st-flash.md index 981bf3cd6..d294f05d1 100644 --- a/doc/man/st-flash.md +++ b/doc/man/st-flash.md @@ -65,7 +65,7 @@ Erase firmware from device # SEE ALSO -st-util(1), st-info(1), st-term(1) +st-util(1), st-info(1) # COPYRIGHT diff --git a/doc/man/st-info.md b/doc/man/st-info.md index d34d5b2b0..62d7c5ce1 100644 --- a/doc/man/st-info.md +++ b/doc/man/st-info.md @@ -53,7 +53,7 @@ Display information about connected programmers and devices # SEE ALSO -st-util(1), st-flash(1), st-term(1) +st-util(1), st-flash(1) # COPYRIGHT diff --git a/doc/man/st-term.1 b/doc/man/st-term.1 deleted file mode 100644 index e6512540c..000000000 --- a/doc/man/st-term.1 +++ /dev/null @@ -1,32 +0,0 @@ -.TH ST-TERM 1 "Sep 2016" "Open Source STMicroelectronics Stlink Tools" "STLINK" -.SH NAME -.PP -st-term - Serial terminal interface for debugging using STLink device -only -.SH SYNOPSIS -.PP -\f[I]st-term\f[] -.SH DESCRIPTION -.PP -Provides a serial terminal that works through the STLink device, -allowing to do the kind of debugging you would do using the UART of the -STM32 device without having to connect a UART-USB serial adapter dongle. -.PP -It works by having a magic number in sram of the MCU within a structure -that serves as IO buffer. -.PP -The required setup consist of some code that establishes the magic -number, buffer structure and helper functions for actual data -transmission between host and MCU. -.PP -\f[C]stlinky.h\f[] and \f[C]stlinky.c\f[] are available in the Antares -build system libraries source: -https://github.com/nekromant/antares/tree/master/include/lib -.SH SEE ALSO -.PP -st-util(1), st-info(1), st-term(1) -.SH COPYRIGHT -.PP -This work is copyrighted. -Stlink contributors. -See \f[I]LICENSE\f[] file in the stlink source distribution. diff --git a/doc/man/st-term.md b/doc/man/st-term.md deleted file mode 100644 index e9b635e5c..000000000 --- a/doc/man/st-term.md +++ /dev/null @@ -1,36 +0,0 @@ -% ST-TERM(1) Open Source STMicroelectronics Stlink Tools | STLINK -% -% Sep 2016 - - -# NAME -st-term - Serial terminal interface for debugging using STLink device only - - -# SYNOPSIS -*st-term* - - -# DESCRIPTION -Provides a serial terminal that works through the STLink device, allowing to do -the kind of debugging you would do using the UART of the STM32 device without -having to connect a UART-USB serial adapter dongle. - -It works by having a magic number in sram of the MCU within a structure that -serves as IO buffer. - -The required setup consist of some code that establishes the magic number, -buffer structure and helper functions for actual data transmission between host -and MCU. - -`stlinky.h` and `stlinky.c` are available in the Antares build system libraries -source: https://github.com/nekromant/antares/tree/master/include/lib - - -# SEE ALSO -st-util(1), st-info(1), st-term(1) - - -# COPYRIGHT -This work is copyrighted. Stlink contributors. -See *LICENSE* file in the stlink source distribution. diff --git a/doc/man/st-util.md b/doc/man/st-util.md index 5bd93a46b..fd744d825 100644 --- a/doc/man/st-util.md +++ b/doc/man/st-util.md @@ -63,7 +63,7 @@ Run GDB server on port 4500 and connect to it # SEE ALSO -st-flash(1), st-info(1), st-term(1) +st-flash(1), st-info(1) # COPYRIGHT From 68b0f3bddc3c4aaffe34caa6a3201029edd8ad56 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 22 Oct 2016 09:44:37 +0200 Subject: [PATCH 0503/1435] Initial work to fix cygwin builds --- CMakeLists.txt | 5 +++-- Makefile | 2 +- cmake/modules/FindLibUSB.cmake | 2 -- doc/man/CMakeLists.txt | 4 +++- 4 files changed, 7 insertions(+), 6 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index f648843a7..04717e0a6 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,7 +2,7 @@ cmake_minimum_required(VERSION 2.8.7) project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics Stlink Tools") -include(CheckIncludeFile) +option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) if (POLICY CMP0042) # Newer cmake on MacOS should use @rpath @@ -22,6 +22,7 @@ if (NOT APPLE AND NOT WIN32) pkg_check_modules(gtk gtk+-3.0) endif () +include(CheckIncludeFile) CHECK_INCLUDE_FILE(sys/mman.h STLINK_HAVE_SYS_MMAN_H) if (STLINK_HAVE_SYS_MMAN_H) add_definitions(-DSTLINK_HAVE_SYS_MMAN_H) @@ -95,7 +96,7 @@ else() endif() install(TARGETS ${PROJECT_NAME} - LIBRARY DESTINATION lib/${CMAKE_LIBRARY_PATH} + DESTINATION lib/${CMAKE_LIBRARY_PATH} ) ### diff --git a/Makefile b/Makefile index 2ddfceee8..7f81488bb 100644 --- a/Makefile +++ b/Makefile @@ -5,7 +5,7 @@ MAKEFLAGS += -s all: release -ci: lint debug release test +ci: debug release test help: @echo " release: Run a release build" diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index 90aafb3a2..45472b96e 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -44,8 +44,6 @@ else () ) endif() -message(STATUS "LIBUSB_INCLUDE_DIR: ${LIBUSB_INCLUDE_DIR}") - if (APPLE) set(LIBUSB_NAME libusb-1.0.a) elseif(MSYS OR MINGW) diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 55b419361..83bb008cf 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -5,7 +5,7 @@ set(MANPAGES ) # Only generate manpages with pandoc in Debug builds -if(${CMAKE_BUILD_TYPE} MATCHES "Debug") +if(${STLINK_GENERATE_MANPAGES}) include(pandocology) foreach(manpage ${MANPAGES}) @@ -16,6 +16,8 @@ if(${CMAKE_BUILD_TYPE} MATCHES "Debug") PRODUCT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} ) endforeach() +else() + message(STATUS "Manpage generation disabled") endif() # Install from output folder or this folder From 09b8775328bff5119e5b3179d6a592ef1ac46779 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 22 Oct 2016 09:50:12 +0200 Subject: [PATCH 0504/1435] .github/ISSUE_TEMPLATE.md: Correct typos. Fixes #503 --- .github/ISSUE_TEMPLATE.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/.github/ISSUE_TEMPLATE.md b/.github/ISSUE_TEMPLATE.md index 932e9387f..63c6c4505 100644 --- a/.github/ISSUE_TEMPLATE.md +++ b/.github/ISSUE_TEMPLATE.md @@ -2,15 +2,16 @@ Thank you for giving feedback to the stlink project. Take some time to fill out check boxes with a X in the following items so developers and other people can try to - to find out what is going on. And add/remove what is appropiate to your problem. + to find out what is going on. And add/remove what is appropriate to your problem. -When submitting a feature request, try to reuse the list and add/remove what is appropiate. +When submitting a feature request, try to reuse the list and add/remove what is appropriate. + Place a `X` between the brackets `[X]` to mark the list item. - [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard - [ ] Programmer firmware version: e.g STSW-LINK007 2.27.15 - [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) - [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 -- [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` +- [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` - [ ] Target chip (and optional board): e.g STM32F402VG (STM32Fxxx Discovery) A as-detailed description possible of the problem with debug output when available. From 9eb84d9f045a994d66a0271d4b92dd4d786552d1 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 22 Oct 2016 10:18:33 +0200 Subject: [PATCH 0505/1435] README.md: Refactor compilation and udev notes into seperate document. Fixes #486 --- README.md | 72 ++++++++++++------------------------------------ doc/compiling.md | 65 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 83 insertions(+), 54 deletions(-) create mode 100644 doc/compiling.md diff --git a/README.md b/README.md index f54764b1b..267cf765a 100644 --- a/README.md +++ b/README.md @@ -22,52 +22,27 @@ Two different transport layers are used: * STLINKv1 uses SCSI passthru commands over USB * STLINKv2 uses raw USB commands. -## Common requirements +## Installation -* Debian based distros (debian, ubuntu) - * `build-essential` +Currently there are no binaries for windows available. + It is known to compile and work with MinGW/Cygwin. -* `cmake` -* `libusb-1.0` (plus development headers for building, on debian based distros `libusb-1.0.0-dev` package) -* (optional) for `stlink-gui` we need libgtk-3-dev +For debian linux based distros there is also no package available + in the standard repositories so you need to compile yourself. -## For STLINKv1 +Arch Linux users can install from the [repository](https://www.archlinux.org/packages/community/x86_64/stlink) -The STLINKv1's SCSI emulation is very broken, so the best thing to do -is tell your operating system to completely ignore it. +FreeBSD users can install from [freshports](https://www.freshports.org/devel/stlink) -Options (do one of these before you plug it in) +**Compilation from source (advanced users)** -* `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` -* or 1. `echo "options usb-storage quirks=483:3744:i" >> /etc/modprobe.conf` -* 2. `modprobe -r usb-storage && modprobe usb-storage` -* or 1. `cp stlink_v1.modprobe.conf /etc/modprobe.d` -* 2. `modprobe -r usb-storage && modprobe usb-storage` - -## For STLINKv2 - -You're ready to go :) - -## Build from sources - -``` -$ mkdir build && cd build -$ cmake -DCMAKE_BUILD_TYPE=Debug .. -$ make -``` - -### Build Debian Package -To build debian package you need debuild. - -``` -$ git archive --prefix=$(git describe)/ HEAD | bzip2 --stdout > ../libstlink_$(sed -En -e "s/.*\((.*)\).*/\1/" -e "1,1 p" debian/changelog).orig.tar.bz2 -$ debuild -uc -us -``` +When there is no executable available for your platform or you need the latest + (possible unstable) version you need to compile yourself. This is explained in + the [compiling manual](doc/compiling.md). ## Using the gdb server -To run the gdb server: (you do not need sudo if you have set up -permissions correctly) +To run the gdb server: ``` $ make && [sudo] ./st-util @@ -92,7 +67,7 @@ There are a few options: ``` The STLINKv2 device to use can be specified in the environment -variable STLINK_DEVICE on the format `:`. +variable `STLINK_DEVICE` on the format `:`. Then, in your project directory, someting like this... (remember, you need to run an _ARM_ gdb, not an x86 gdb) @@ -112,8 +87,6 @@ Transfer rate: 1 KB/sec, 560 bytes/write. (gdb) continue ``` -Have fun! - ## Resetting the chip from GDB You may reset the chip using GDB if you want. You'll need to use `target @@ -132,19 +105,6 @@ Starting program: /home/whitequark/ST/apps/bally/firmware.elf Remember that you can shorten the commands. `tar ext :4242' is good enough for GDB. -## Setting up udev rules - -For convenience, you may install udev rule files, located -in the `etc/udev/rules.d` directory. You will need to copy it to /etc/udev/rules.d, -and then either execute as root (or reboot your machine): - -``` -$ udevadm control --reload-rules -$ udevadm trigger -``` - -Udev will now create a /dev/stlinkv2_XX or /dev/stlinkv1_XX file, with the appropriate permissions. - ## Running programs from SRAM You can run your firmware directly from SRAM if you want to. Just link @@ -160,8 +120,12 @@ code, if it is linked correctly (i.e. ELF has correct entry point). ## Writing to flash The GDB stub ships with a correct memory map, including the flash area. -If you would link your executable to 0x08000000 and then do +If you would link your executable to `0x08000000` and then do + +``` (gdb) load firmware.elf +``` + then it would be written to the memory. ## FAQ diff --git a/doc/compiling.md b/doc/compiling.md new file mode 100644 index 000000000..7021058fa --- /dev/null +++ b/doc/compiling.md @@ -0,0 +1,65 @@ +# Compiling + +## Build from sources + + + +* CMake +* C compiler (gcc, clang, mingw) +* Libusb 1.0 +* (optional) pandoc for generating manpages from markdown + +``` +$ mkdir build && cd build +$ cmake -DCMAKE_BUILD_TYPE=Debug .. +$ make +``` + +## Linux + +## Common requirements + +* Debian based distros (debian, ubuntu) + * `build-essential` +* `cmake` +* `libusb-1.0` (plus development headers for building, on debian based distros `libusb-1.0.0-dev` package) +* (optional) for `stlink-gui` we need libgtk-3-dev + +## Permissions with udev + +Make sure you install udev files which are necessary to run the tools without root + permissions. By default most distributions don't allow access to USB devices. The + udev rules create devices nodes and set the group of this to `stlink. + +The rules are located in the `etc/udev/rules.d` directory. You will need to copy it +to /etc/udev/rules.d, and then either execute as root (or reboot your machine): + +``` +$ udevadm control --reload-rules +$ udevadm trigger +``` + +Udev will now create device node files `/dev/stlinkv2_XX`, `/dev/stlinkv1_XX`. You must + make sure the `stlink` group exists and the user who is trying to access is added + to this group. + +### Note for STLINKv1 usage + +The STLINKv1's SCSI emulation is very broken, so the best thing to do +is tell your operating system to completely ignore it. + +Options (do one of these before you plug it in) + +* `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` +* or 1. `echo "options usb-storage quirks=483:3744:i" >> /etc/modprobe.conf` +* 2. `modprobe -r usb-storage && modprobe usb-storage` +* or 1. `cp stlink_v1.modprobe.conf /etc/modprobe.d` +* 2. `modprobe -r usb-storage && modprobe usb-storage` + +### Build Debian Package +To build debian package you need debuild. + +``` +$ git archive --prefix=$(git describe)/ HEAD | bzip2 --stdout > ../libstlink_$(sed -En -e "s/.*\((.*)\).*/\1/" -e "1,1 p" debian/changelog).orig.tar.bz2 +$ debuild -uc -us +``` From 7b359e2b95bbc439b18ec0a6ed8e084e8ed3ffbd Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 22 Oct 2016 10:22:44 +0200 Subject: [PATCH 0506/1435] doc/compiling.md: Add note on compiling for Mac OS X. Refs #499 --- doc/compiling.md | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index 7021058fa..7ce1bfcc5 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -2,8 +2,6 @@ ## Build from sources - - * CMake * C compiler (gcc, clang, mingw) * Libusb 1.0 @@ -63,3 +61,21 @@ To build debian package you need debuild. $ git archive --prefix=$(git describe)/ HEAD | bzip2 --stdout > ../libstlink_$(sed -En -e "s/.*\((.*)\).*/\1/" -e "1,1 p" debian/changelog).orig.tar.bz2 $ debuild -uc -us ``` + +## Mac OS X + +When compiling on a mac you need the following: + +* A compiler toolchain (XCode) +* CMake +* Libusb 1.0 + +The best way is to install [homebrew](http://brew.sh) which is a package manager + for opensource software which is missing from the Apple App Store. Then install + the dependencies: + +``` +brew install libusb cmake +``` + +Compile as described in the first section of this document. From 78e849f0100694c45bc1ca255698bdb7f7a47f88 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 22 Oct 2016 10:24:24 +0200 Subject: [PATCH 0507/1435] README.md: Add not how to install on a mac with homebrew. Refs #499 --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index 267cf765a..a404e4204 100644 --- a/README.md +++ b/README.md @@ -34,6 +34,8 @@ Arch Linux users can install from the [repository](https://www.archlinux.org/pac FreeBSD users can install from [freshports](https://www.freshports.org/devel/stlink) +Mac OS X users can install from [homebrew](http://brewformulas.org/Stlink) + **Compilation from source (advanced users)** When there is no executable available for your platform or you need the latest From 49248f598564dc81af23811201cbe2ea3bb65456 Mon Sep 17 00:00:00 2001 From: Christian Mauderer Date: Wed, 26 Oct 2016 20:40:25 +0200 Subject: [PATCH 0508/1435] Fix install locations for modprobe config and udev rules (#502) * cmake: Fix location of modprobe.d config. * cmake: Use cmake variables for install locations. This commit add the following two Cmake variables to change the install location of the udev and modprobe configuration files: - STLINK_UDEV_RULES_DIR - STLINK_MODPROBED_DIR * doc/compiling.md: Add info about new CMAKE variables. * debian: Use CMAKE variables for build. --- CMakeLists.txt | 6 ++++-- debian/rules | 3 ++- doc/compiling.md | 10 ++++++++++ 3 files changed, 16 insertions(+), 3 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 04717e0a6..4aac51c05 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,6 +1,8 @@ cmake_minimum_required(VERSION 2.8.7) project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics Stlink Tools") +set(STLINK_UDEV_RULES_DIR "/etc/udev/rules.d" CACHE PATH "Udev rules directory") +set(STLINK_MODPROBED_DIR "/etc/modprobe.d" CACHE PATH "modprobe.d directory") option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) @@ -131,9 +133,9 @@ install(TARGETS st-flash st-info if (CMAKE_SYSTEM_NAME STREQUAL "Linux") file(GLOB RULES_FILES etc/udev/rules.d/*.rules) install(FILES etc/modprobe.d/stlink_v1.conf - DESTINATION /etc) + DESTINATION ${STLINK_MODPROBED_DIR}/) install(FILES ${RULES_FILES} - DESTINATION /lib/udev/rules.d/) + DESTINATION ${STLINK_UDEV_RULES_DIR}/) endif() add_subdirectory(src/gdbserver) diff --git a/debian/rules b/debian/rules index 2b826772b..2ff7e59a8 100755 --- a/debian/rules +++ b/debian/rules @@ -24,4 +24,5 @@ include /usr/share/dpkg/default.mk # This is example for Cmake (See http://bugs.debian.org/641051 ) override_dh_auto_configure: dh_auto_configure -- \ - -DCMAKE_LIBRARY_PATH=$(DEB_HOST_MULTIARCH) + -DCMAKE_LIBRARY_PATH=$(DEB_HOST_MULTIARCH) \ + -DSTLINK_UDEV_RULES_DIR='/lib/udev/rules.d' diff --git a/doc/compiling.md b/doc/compiling.md index 7ce1bfcc5..c8a06dc86 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -79,3 +79,13 @@ brew install libusb cmake ``` Compile as described in the first section of this document. + +## Build using different directories for udev and modprobe + +To put the udev or the modprobe configuration files into a different directory +during installation you can use the following cmake options: + +``` +$ cmake -DSTLINK_UDEV_RULES_DIR="/usr/lib/udev/rules.d" \ + -DSTLINK_MODPROBED_DIR="/usr/lib/modprobe.d" .. +``` From be66bbf200c718904514b044ba84d64a36456218 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 29 Oct 2016 12:03:58 +0200 Subject: [PATCH 0509/1435] doc/compiling.md: Add note about installation and ldconfig. Fixes #478 --- doc/compiling.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/doc/compiling.md b/doc/compiling.md index c8a06dc86..ff9e178b1 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -23,6 +23,10 @@ $ make * `libusb-1.0` (plus development headers for building, on debian based distros `libusb-1.0.0-dev` package) * (optional) for `stlink-gui` we need libgtk-3-dev +### Fixing cannot open shared object file + +When installing system-wide (`sudo make install`) the dynamic library cache needs to be updated with the command `ldconfig`. + ## Permissions with udev Make sure you install udev files which are necessary to run the tools without root From 76196d22c7fe0ad96c0eb81104400e37c322285a Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 29 Oct 2016 12:08:39 +0200 Subject: [PATCH 0510/1435] doc/compilation.md: Add note for user folder or system wide installation after compilation. Fixes #497 --- doc/compiling.md | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/doc/compiling.md b/doc/compiling.md index ff9e178b1..a102be1bd 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -7,12 +7,35 @@ * Libusb 1.0 * (optional) pandoc for generating manpages from markdown +Run from the root of the source directory: + +``` +$ make release +$ make debug +``` + +The debug target should only be necessary for people who want + to modify the sources and run under a debugger. +The top level Makefile is just a handy wrapper for: + ``` $ mkdir build && cd build $ cmake -DCMAKE_BUILD_TYPE=Debug .. $ make ``` +You could install to a user folder e.g `$HOME`: + +``` +$ cd release; make install DESTDIR=$HOME +``` + +Or system wide: + +``` +$ cd release; sudo make install +``` + ## Linux ## Common requirements From 9c0583756657047176b6b319ac0b470c4d418fd3 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 29 Oct 2016 12:20:10 +0200 Subject: [PATCH 0511/1435] README.md: Add missing features --- README.md | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/README.md b/README.md index a404e4204..177cb03b3 100644 --- a/README.md +++ b/README.md @@ -199,6 +199,13 @@ STLink v2-1 (as found on the Nucleo boards), known working targets: Please report any and all known working combinations so I can update this! +## Missing features + +* Control programming speed (See [#462](https://github.com/texane/stlink/issues/462)) +* OTP area programming (See [#202](https://github.com/texane/stlink/issues/202)) +* EEPROM area programming (See [#318](https://github.com/texane/stlink/issues/218)) +* Protection bits area reading (See [#346](https://github.com/texane/stlink/issues/346)) + ## Known bugs ### Sometimes flashing only works after a mass erase From 7ab464527e210264919e67fd67c68fd2d23e9803 Mon Sep 17 00:00:00 2001 From: Georg von Zengen Date: Thu, 3 Nov 2016 22:56:33 +0100 Subject: [PATCH 0512/1435] flash: added easy way to reset the target (#505) * flash: added easy way to reset the target st-flash does now have a 'reset' command makes it easy to reset the Target * Doc: added man page entry for reset command of st-flash --- doc/man/st-flash.md | 2 ++ include/stlink/tools/flash.h | 2 +- src/tools/flash.c | 12 ++++++++++++ src/tools/flash_opts.c | 4 ++++ 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/doc/man/st-flash.md b/doc/man/st-flash.md index d294f05d1..4eacb7a07 100644 --- a/doc/man/st-flash.md +++ b/doc/man/st-flash.md @@ -32,6 +32,8 @@ read *FILE* *ADDR* *SIZE* erase : Perform a mass erasing of the device firmware +reset +: Reset the target # OPTIONS diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index dbc9ad881..bb7bd739e 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -7,7 +7,7 @@ #define DEBUG_LOG_LEVEL 100 #define STND_LOG_LEVEL 50 -enum flash_cmd {FLASH_CMD_NONE = 0, FLASH_CMD_WRITE = 1, FLASH_CMD_READ = 2, FLASH_CMD_ERASE = 3}; +enum flash_cmd {FLASH_CMD_NONE = 0, FLASH_CMD_WRITE = 1, FLASH_CMD_READ = 2, FLASH_CMD_ERASE = 3, CMD_RESET = 4}; enum flash_format {FLASH_FORMAT_BINARY = 0, FLASH_FORMAT_IHEX = 1}; struct flash_opts { diff --git a/src/tools/flash.c b/src/tools/flash.c index 5cedb3815..1b6c7a7da 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -33,6 +33,7 @@ static void usage(void) puts("stlinkv1 command line: ./st-flash [--debug] /dev/sgX erase"); puts("stlinkv2 command line: ./st-flash [--debug] [--reset] [--serial ] [--format ] {read|write} "); puts("stlinkv2 command line: ./st-flash [--debug] [--serial ] erase"); + puts("stlinkv2 command line: ./st-flash [--debug] [--serial ] reset"); puts(" Use hex format for addr, and ."); puts(" Format may be 'binary' (default) or 'ihex', although must be specified for binary format only."); puts(" ./st-flash [--version]"); @@ -168,6 +169,17 @@ int main(int ac, char** av) printf("stlink_erase_flash_mass() == -1\n"); goto on_error; } + } else if (o.cmd == CMD_RESET) + { + if (stlink_jtag_reset(sl, 2)) { + printf("Failed to reset JTAG\n"); + goto on_error; + } + + if (stlink_reset(sl)) { + printf("Failed to reset device\n"); + goto on_error; + } } else /* read */ { diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index 1a0d0cd9b..1ccf55334 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -99,6 +99,10 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) if (o->cmd != FLASH_CMD_NONE) return -1; o->cmd = FLASH_CMD_WRITE; } + else if (strcmp(av[0], "reset") == 0) { + if (o->cmd != FLASH_CMD_NONE) return -1; + o->cmd = CMD_RESET; + } else if(starts_with(av[0], "/dev/")) { if (o->devname) return -1; o->devname = av[0]; From 470fc2b309be91b7e0ee9e01bfb60128ec5ae5be Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Mon, 7 Nov 2016 11:49:16 +0200 Subject: [PATCH 0513/1435] fix cmake wrong libusb extract command for windows (fixes #511) --- cmake/modules/FindLibUSB.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index 45472b96e..84020b98b 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -24,7 +24,7 @@ if(WIN32 OR CMAKE_VS_PLATFORM_NAME OR MINGW OR MSYS) ) endif() file(MAKE_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) - execute_process(COMMAND ${ZIP_LOCATION} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o${LIBUSB_WIN_OUTPUT_FOLDER}) + execute_process(COMMAND ${ZIP_EXECUTABLE} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o${LIBUSB_WIN_OUTPUT_FOLDER}) endif() # FreeBSD From 3de5cf05619926e09e885f8980478a0c128a0f08 Mon Sep 17 00:00:00 2001 From: "fabien.lementec" Date: Tue, 22 Nov 2016 07:45:55 +0100 Subject: [PATCH 0514/1435] README.md: Add STM32F411E-DISCO --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 177cb03b3..b68731844 100644 --- a/README.md +++ b/README.md @@ -183,6 +183,7 @@ STLink v2 (as found on the 32L and F4 Discovery boards), known working targets: * STM32L151CB (custom board) * STM32L152RB (STM32L-Discovery board, custom board) * STM32F051R8T6 (STM320518-EVAL board) +* STM32F411E-DISCO (STM32F4 Discovery board with gyro, audio) STLink v2-1 (as found on the Nucleo boards), known working targets: From 0c63a2cffc7b7fca817d4c7fb896dbe696341ea3 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Mon, 5 Dec 2016 17:36:37 +0100 Subject: [PATCH 0515/1435] cmake/Version.cmake: Fix version detection when building from zipfile (non-git tree). Fixes #523 --- cmake/Version.cmake | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/cmake/Version.cmake b/cmake/Version.cmake index 957e29ca4..bb01315ab 100644 --- a/cmake/Version.cmake +++ b/cmake/Version.cmake @@ -20,15 +20,15 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") if (res EQUAL 1) set (PROJECT_VERSION "${PROJECT_VERSION}-dirty") endif() -endif() -string(REGEX REPLACE "^(0|[1-9][0-9]*)[.](0|[1-9][0-9]*)[.](0|[1-9][0-9]*)(-[.0-9A-Za-z-]+)?([+][.0-9A-Za-z-]+)?$" - "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) -list(LENGTH PROJECT_VERSION_LIST len) -if(len EQUAL 3) - list(GET PROJECT_VERSION_LIST 0 PROJECT_VERSION_MAJOR) - list(GET PROJECT_VERSION_LIST 1 PROJECT_VERSION_MINOR) - list(GET PROJECT_VERSION_LIST 2 PROJECT_VERSION_PATCH) + string(REGEX REPLACE "^(0|[1-9][0-9]*)[.](0|[1-9][0-9]*)[.](0|[1-9][0-9]*)(-[.0-9A-Za-z-]+)?([+][.0-9A-Za-z-]+)?$" + "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) + list(LENGTH PROJECT_VERSION_LIST len) + if(len EQUAL 3) + list(GET PROJECT_VERSION_LIST 0 PROJECT_VERSION_MAJOR) + list(GET PROJECT_VERSION_LIST 1 PROJECT_VERSION_MINOR) + list(GET PROJECT_VERSION_LIST 2 PROJECT_VERSION_PATCH) + endif() elseif(EXISTS ${PROJECT_SOURCE_DIR}/.version) # If git is not available (e.g. when building from source package) # we can extract the package version from .version file. @@ -44,7 +44,5 @@ else() message(FATAL_ERROR "Unable to determine project version") endif() -if (${CMAKE_BUILD_TYPE} MATCHES "Debug") - message(STATUS "stlink version: ${PROJECT_VERSION}") - message(STATUS " Major ${PROJECT_VERSION_MAJOR} Minor ${PROJECT_VERSION_MINOR} Patch ${PROJECT_VERSION_PATCH}") -endif() +message(STATUS "stlink version: ${PROJECT_VERSION}") +message(STATUS " Major ${PROJECT_VERSION_MAJOR} Minor ${PROJECT_VERSION_MINOR} Patch ${PROJECT_VERSION_PATCH}") From 0879af2edc06e66813f2bddef04bc8640f2aeb56 Mon Sep 17 00:00:00 2001 From: Greg Alexander Date: Sat, 10 Dec 2016 14:01:59 -0500 Subject: [PATCH 0516/1435] don't return stale value from gdb-server "read memory" command if the underlying transport fails, and return an error code if the gdb-server "write memory" command fails --- src/gdbserver/gdb-server.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 339cd1130..dd9f34daf 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -1509,7 +1509,10 @@ int serve(stlink_t *sl, st_state_t *st) { if (count_rnd < count) count = count_rnd; - stlink_read_mem32(sl, start - adj_start, count_rnd); + if (stlink_read_mem32(sl, start - adj_start, count_rnd) != 0) { + /* read failed somehow, don't return stale buffer */ + count = 0; + } reply = calloc(count * 2 + 1, 1); for(unsigned int i = 0; i < count; i++) { @@ -1527,6 +1530,7 @@ int serve(stlink_t *sl, st_state_t *st) { stm32_addr_t start = (stm32_addr_t) strtoul(s_start, NULL, 16); unsigned count = (unsigned) strtoul(s_count, NULL, 16); + int err = 0; if(start % 4) { unsigned align_count = 4 - start % 4; @@ -1536,7 +1540,7 @@ int serve(stlink_t *sl, st_state_t *st) { uint8_t byte = strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; } - stlink_write_mem8(sl, start, align_count); + err |= stlink_write_mem8(sl, start, align_count); cache_change(start, align_count); start += align_count; count -= align_count; @@ -1551,7 +1555,7 @@ int serve(stlink_t *sl, st_state_t *st) { uint8_t byte = strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; } - stlink_write_mem32(sl, start, aligned_count); + err |= stlink_write_mem32(sl, start, aligned_count); cache_change(start, aligned_count); count -= aligned_count; start += aligned_count; @@ -1564,10 +1568,10 @@ int serve(stlink_t *sl, st_state_t *st) { uint8_t byte = strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; } - stlink_write_mem8(sl, start, count); + err |= stlink_write_mem8(sl, start, count); cache_change(start, count); } - reply = strdup("OK"); + reply = strdup(err ? "E00" : "OK"); break; } From 98044163ab34bf5159f121d1c49ffb3550321ca0 Mon Sep 17 00:00:00 2001 From: Greg Alexander Date: Sat, 10 Dec 2016 15:45:11 -0500 Subject: [PATCH 0517/1435] Add 'k' (kill) command to gdb-server, which completely resets the connection. --- src/gdbserver/gdb-server.c | 49 ++++++++++++++++++++++++++++++-------- 1 file changed, 39 insertions(+), 10 deletions(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 339cd1130..8a808f10d 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -69,6 +69,19 @@ static void cleanup(int signum) { } +static stlink_t* do_connect(st_state_t *st) { + stlink_t *ret = NULL; + switch (st->stlink_version) { + case 2: + ret = stlink_open_usb(st->logging_level, st->reset, NULL); + break; + case 1: + ret = stlink_v1_open(st->logging_level, st->reset); + break; + } + return ret; +} + int parse_options(int argc, char** argv, st_state_t *st) { static struct option long_options[] = { @@ -183,16 +196,8 @@ int main(int argc, char** argv) { printf("st-util %s\n", STLINK_VERSION); - switch (state.stlink_version) { - case 2: - sl = stlink_open_usb(state.logging_level, state.reset, NULL); - if(sl == NULL) return 1; - break; - case 1: - sl = stlink_v1_open(state.logging_level, state.reset); - if(sl == NULL) return 1; - break; - } + sl = do_connect(&state); + if(sl == NULL) return 1; connected_stlink = sl; signal(SIGINT, &cleanup); @@ -224,6 +229,9 @@ int main(int argc, char** argv) { sleep (1); // don't go bezurk if serve returns with error } + /* in case serve() changed the connection */ + sl = connected_stlink; + /* Continue */ stlink_run(sl); } while (state.persistent); @@ -1667,6 +1675,27 @@ int serve(stlink_t *sl, st_state_t *st) { break; } + case 'k': + /* Kill request - reset the connection itself */ + stlink_run(sl); + stlink_exit_debug_mode(sl); + stlink_close(sl); + + sl = do_connect(st); + if(sl == NULL) cleanup(0); + connected_stlink = sl; + + if (st->reset) { + stlink_reset(sl); + } + stlink_force_debug(sl); + init_cache(sl); + init_code_breakpoints(sl); + init_data_watchpoints(sl); + + reply = NULL; /* no response */ + + break; default: reply = strdup(""); From c06a7737bd13556d9a4e22862766e152a1a9f37e Mon Sep 17 00:00:00 2001 From: Peter Mortensen Date: Sun, 11 Dec 2016 13:18:48 +0100 Subject: [PATCH 0518/1435] Update README.md Copy edited (e.g. ref. and ) --- README.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index b68731844..1c66d9308 100644 --- a/README.md +++ b/README.md @@ -12,7 +12,7 @@ Open source version of the STMicroelectronics Stlink Tools First, you have to know there are several boards supported by the software. Those boards use a chip to translate from USB to JTAG commands. The chip is -called stlink and there are 2 versions: +called stlink and there are two versions: * STLINKv1, present on STM32VL discovery kits, * STLINKv2, present on STM32L discovery and later kits. @@ -24,10 +24,10 @@ Two different transport layers are used: ## Installation -Currently there are no binaries for windows available. +Currently there are no binaries for Windows available. It is known to compile and work with MinGW/Cygwin. -For debian linux based distros there is also no package available +For Debian Linux based distributions there is also no package available in the standard repositories so you need to compile yourself. Arch Linux users can install from the [repository](https://www.archlinux.org/packages/community/x86_64/stlink) @@ -69,7 +69,7 @@ There are a few options: ``` The STLINKv2 device to use can be specified in the environment -variable `STLINK_DEVICE` on the format `:`. +variable `STLINK_DEVICE` in the format `:`. Then, in your project directory, someting like this... (remember, you need to run an _ARM_ gdb, not an x86 gdb) From 8efa16bdd525618999d3e6a583edeb3d7c6ba4bb Mon Sep 17 00:00:00 2001 From: texane Date: Sun, 11 Dec 2016 13:48:55 +0100 Subject: [PATCH 0519/1435] remove warning --- src/tools/flash_opts.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index 1ccf55334..46c0d853c 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -153,6 +153,8 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) return -1; } break; + + default: break ; } // some constistence checks From c44182465a7f5676dc30d4b99110919f8000a6fe Mon Sep 17 00:00:00 2001 From: jkhax0r Date: Fri, 30 Dec 2016 05:00:27 -0600 Subject: [PATCH 0520/1435] Set SWDCLK and fix jtag_reset bug (#534) * - Fixed bug where stlink_jtag_reset in stlink_open_usb() was never being called because the STLINK version was being checked before it had been initialized - Added support for stlink_set_swdclk() to adjust the SWD clock speed. For example, to set at 4Mhz, 1.8Mhz, 900Khz, etc similar to in the official ST-LINK utility. NOTE: The default when STLINK is powered appears to be 1.8Mhz (looked at scope traces) but it retains whatever was set before. * Fixed tab->space --- include/stlink.h | 19 +++++++++++++++++++ include/stlink/backend.h | 1 + src/common.c | 5 +++++ src/usb.c | 40 ++++++++++++++++++++++++++++++++++++++-- 4 files changed, 63 insertions(+), 2 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index 674aa3b28..813086e15 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -48,6 +48,8 @@ extern "C" { #define STLINK_JTAG_READDEBUG_32BIT 0x36 #define STLINK_JTAG_DRIVE_NRST 0x3c +#define STLINK_DEBUG_APIV2_SWD_SET_FREQ 0x43 + /* cortex core ids */ // TODO clean this up... #define STM32VL_CORE_ID 0x1ba01477 @@ -57,6 +59,22 @@ extern "C" { #define STM32_FLASH_BASE 0x08000000 #define STM32_SRAM_BASE 0x20000000 +// Baud rate divisors for SWDCLK +#define STLINK_SWDCLK_4MHZ_DIVISOR 0 +#define STLINK_SWDCLK_1P8MHZ_DIVISOR 1 +#define STLINK_SWDCLK_1P2MHZ_DIVISOR 2 +#define STLINK_SWDCLK_950KHZ_DIVISOR 3 +#define STLINK_SWDCLK_480KHZ_DIVISOR 7 +#define STLINK_SWDCLK_240KHZ_DIVISOR 15 +#define STLINK_SWDCLK_125KHZ_DIVISOR 31 +#define STLINK_SWDCLK_100KHZ_DIVISOR 40 +#define STLINK_SWDCLK_50KHZ_DIVISOR 79 +#define STLINK_SWDCLK_25KHZ_DIVISOR 158 +#define STLINK_SWDCLK_15KHZ_DIVISOR 265 +#define STLINK_SWDCLK_5KHZ_DIVISOR 798 + + + /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 @@ -177,6 +195,7 @@ typedef struct flash_loader { int stlink_current_mode(stlink_t *sl); int stlink_force_debug(stlink_t *sl); int stlink_target_voltage(stlink_t *sl); + int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); int stlink_erase_flash_mass(stlink_t* sl); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); diff --git a/include/stlink/backend.h b/include/stlink/backend.h index d1b7648e4..42d12d4ac 100644 --- a/include/stlink/backend.h +++ b/include/stlink/backend.h @@ -28,6 +28,7 @@ int (*current_mode) (stlink_t * stl); int (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); + int (*set_swdclk) (stlink_t * stl, uint16_t divisor); } stlink_backend_t; #endif /* STLINK_BACKEND_H_ */ diff --git a/src/common.c b/src/common.c index e8cdf3ba9..7a47ac813 100644 --- a/src/common.c +++ b/src/common.c @@ -642,6 +642,11 @@ int stlink_run(stlink_t *sl) { return sl->backend->run(sl); } +int stlink_set_swdclk(stlink_t *sl, uint16_t divisor) { + DLOG("*** set_swdclk ***\n"); + return sl->backend->set_swdclk(sl, divisor); +} + int stlink_status(stlink_t *sl) { int ret; diff --git a/src/usb.c b/src/usb.c index f32b2e04c..4b57ed98f 100644 --- a/src/usb.c +++ b/src/usb.c @@ -449,6 +449,36 @@ int _stlink_usb_run(stlink_t* sl) { return 0; } + +int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int rep_len = 2; + int i; + + // clock speed only supported by stlink/v2 and for firmware >= 22 + if (sl->version.stlink_v >= 2 && sl->version.jtag_v >= 22) { + i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_SWD_SET_FREQ; + cmd[i++] = clk_divisor & 0xFF; + cmd[i++] = (clk_divisor >> 8) & 0xFF; + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { + printf("[!] send_recv STLINK_DEBUG_APIV2_SWD_SET_FREQ\n"); + return (int) size; + } + + return 0; + } else { + return -1; + } +} + int _stlink_usb_exit_debug_mode(stlink_t *sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; @@ -724,7 +754,8 @@ static stlink_backend_t _stlink_usb_backend = { _stlink_usb_step, _stlink_usb_current_mode, _stlink_usb_force_debug, - _stlink_usb_target_voltage + _stlink_usb_target_voltage, + _stlink_usb_set_swdclk }; stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16]) @@ -878,6 +909,9 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } + + // Initialize stlink version (sl->version) + stlink_version(sl); if (reset) { if( sl->version.stlink_v > 1 ) stlink_jtag_reset(sl, 2); @@ -885,9 +919,11 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 usleep(10000); } - stlink_version(sl); ret = stlink_load_device_params(sl); + // Set the stlink clock speed (default is 1800kHz) + stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); + on_libusb_error: if (ret == -1) { stlink_close(sl); From e761a47fc405c6617d180371f1d1993564a45037 Mon Sep 17 00:00:00 2001 From: night-ghost Date: Fri, 30 Dec 2016 16:15:20 +0500 Subject: [PATCH 0521/1435] Reset flash MER bit after mass erase Otherwise all subsequent erases before turning off the power will be mass erases (#489) --- src/common.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/common.c b/src/common.c index 7a47ac813..f104a1629 100644 --- a/src/common.c +++ b/src/common.c @@ -298,7 +298,7 @@ static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { stlink_write_debug32(sl, FLASH_CR, n); } -static void set_flash_cr_mer(stlink_t *sl) { +static void set_flash_cr_mer(stlink_t *sl, bool v) { uint32_t val, cr_reg, cr_mer, cr_pg; if (sl->flash_type == STLINK_FLASH_TYPE_F4) { @@ -322,7 +322,10 @@ static void set_flash_cr_mer(stlink_t *sl) { stlink_write_debug32(sl, cr_reg, val); } - val |= cr_mer; + if(v) + val |= cr_mer; + else + val &= ~cr_mer; stlink_write_debug32(sl, cr_reg, val); } @@ -1582,7 +1585,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { unlock_flash_if(sl); /* set the mass erase bit */ - set_flash_cr_mer(sl); + set_flash_cr_mer(sl,1); /* start erase operation, reset by hw with bsy bit */ set_flash_cr_strt(sl); @@ -1593,6 +1596,9 @@ int stlink_erase_flash_mass(stlink_t *sl) { /* relock the flash */ lock_flash(sl); + /* reset the mass erase bit */ + set_flash_cr_mer(sl,0); + /* todo: verify the erased memory */ } return 0; From 980962dcedf153f55d7746f01fb8b8d216245357 Mon Sep 17 00:00:00 2001 From: texane Date: Fri, 30 Dec 2016 14:29:19 +0100 Subject: [PATCH 0522/1435] add Nucleo-L152RE board --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 1c66d9308..bf5c23831 100644 --- a/README.md +++ b/README.md @@ -197,6 +197,7 @@ STLink v2-1 (as found on the Nucleo boards), known working targets: * STM32F756NGHx (STMF7 evaluation board) * STM32L053R8 (STM32 Nucleo-L053R8 board) * STM32F769NI (STM32F7 discovery board) +* Nucleo-L152RE board Please report any and all known working combinations so I can update this! From 01b9e1682104386a0dc092f9f2481a13d599ca93 Mon Sep 17 00:00:00 2001 From: Andreas Date: Tue, 3 Jan 2017 01:00:56 +0400 Subject: [PATCH 0523/1435] Add support for STM32F412 (#538) --- include/stlink/chipid.h | 1 + src/chipid.c | 14 +++++++++++++- src/flash_loader.c | 1 + 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 18f02782c..36fb73c62 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -46,6 +46,7 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F334 = 0x438, STLINK_CHIPID_STM32_F3_SMALL = 0x439, STLINK_CHIPID_STM32_F0 = 0x440, + STLINK_CHIPID_STM32_F412 = 0x441, STLINK_CHIPID_STM32_F09X = 0x442, STLINK_CHIPID_STM32_F0_SMALL = 0x444, STLINK_CHIPID_STM32_F04 = 0x445, diff --git a/src/chipid.c b/src/chipid.c index c6bcf70bb..13307a99e 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -286,7 +286,19 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 }, - { + { + // RM0402 document was used to find these parameters + // Table 4. + .chip_id = STLINK_CHIPID_STM32_F412, + .description = "F4 device", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) + .flash_pagesize = 0x4000, // Table 5. Flash module organization ? + .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4 + }, + { .chip_id = STLINK_CHIPID_STM32_F09X, .description = "F09X device", .flash_type = STLINK_FLASH_TYPE_F0, diff --git a/src/flash_loader.c b/src/flash_loader.c index 77ebd95eb..f4d81cbab 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -218,6 +218,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || sl->chip_id == STLINK_CHIPID_STM32_F410 || sl->chip_id == STLINK_CHIPID_STM32_F411RE || + sl->chip_id == STLINK_CHIPID_STM32_F412 || sl->chip_id == STLINK_CHIPID_STM32_F446 ) { if( sl->version.stlink_v == 1 ) { From 55fddc2e55629a6d588976f087d5abbfb2f7b88f Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 5 Jan 2017 22:57:01 +0100 Subject: [PATCH 0524/1435] Update README.md Add note about windows binaries (refs #166) --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index bf5c23831..880083a68 100644 --- a/README.md +++ b/README.md @@ -24,7 +24,7 @@ Two different transport layers are used: ## Installation -Currently there are no binaries for Windows available. +Currently there are no binaries for Windows available (see issue [#166](https://github.com/texane/stlink/issues/166)). It is known to compile and work with MinGW/Cygwin. For Debian Linux based distributions there is also no package available From ba898b1c9c75800b566e8b1983ff7643e104a994 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Torstein=20Huseb=C3=B8?= Date: Mon, 9 Jan 2017 16:13:16 +0100 Subject: [PATCH 0525/1435] after 4c69cae257e317e9297f5a89eed940313b9c25c2 a compile produces the (#539) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit following warning: warning: missing initializer for field ‘set_swdclk’ of ‘stlink_backend_t {aka struct _stlink_backend}’ [-Wmissing-field-initializers] silence the warning and expand comment --- src/sg.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/sg.c b/src/sg.c index 22464bc1b..541ef5550 100644 --- a/src/sg.c +++ b/src/sg.c @@ -933,7 +933,8 @@ static stlink_backend_t _stlink_sg_backend = { _stlink_sg_step, _stlink_sg_current_mode, _stlink_sg_force_debug, - NULL + NULL, /* target_voltage */ + NULL /* set_swdclk */ }; static stlink_t* stlink_open(const int verbose) { From 0106c53821e144828a81b21b162a976302561265 Mon Sep 17 00:00:00 2001 From: GagoSoft Date: Tue, 10 Jan 2017 17:18:59 +0100 Subject: [PATCH 0526/1435] Support serial numbers in st-util and st-flash (#541) Support multiple stlink programmers by passing the serial number as a commandline argument. Fixes #318. --- src/gdbserver/gdb-server.c | 26 +++++++++++++++++++++++++- src/tools/flash_opts.c | 3 ++- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index d71d8c9a6..fddf48fcf 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -30,12 +30,15 @@ /* Semihosting doesn't have a short option, we define a value to identify it */ #define SEMIHOSTING_OPTION 128 +#define SERIAL_OPTION 127 //Allways update the FLASH_PAGE before each use, by calling stlink_calculate_pagesize #define FLASH_PAGE (sl->flash_pgsz) static stlink_t *connected_stlink = NULL; static bool semihosting = false; +static bool serial_specified = false; +static char serialnumber[28] = {0}; static const char hex[] = "0123456789abcdef"; @@ -73,7 +76,12 @@ static stlink_t* do_connect(st_state_t *st) { stlink_t *ret = NULL; switch (st->stlink_version) { case 2: - ret = stlink_open_usb(st->logging_level, st->reset, NULL); + if(serial_specified){ + ret = stlink_open_usb(st->logging_level, st->reset, serialnumber); + } + else{ + ret = stlink_open_usb(st->logging_level, st->reset, NULL); + } break; case 1: ret = stlink_v1_open(st->logging_level, st->reset); @@ -94,6 +102,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { {"no-reset", optional_argument, NULL, 'n'}, {"version", no_argument, NULL, 'V'}, {"semihosting", no_argument, NULL, SEMIHOSTING_OPTION}, + {"serial", required_argument, NULL, SERIAL_OPTION}, {0, 0, 0, 0}, }; const char * help_str = "%s - usage:\n\n" @@ -114,6 +123,8 @@ int parse_options(int argc, char** argv, st_state_t *st) { "\t\t\tDo not reset board on connection.\n" " --semihosting\n" "\t\t\tEnable semihosting support.\n" + " --serial \n" + "\t\t\tUse a specific serial number.\n" "\n" "The STLINKv2 device to use can be specified in the environment\n" "variable STLINK_DEVICE on the format :.\n" @@ -170,6 +181,19 @@ int parse_options(int argc, char** argv, st_state_t *st) { case SEMIHOSTING_OPTION: semihosting = true; break; + case SERIAL_OPTION: + printf("use serial %s\n",optarg); + /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ + int j = (int)strlen(optarg); + int length = j / 2; //the length of the destination-array + if(j % 2 != 0) return -1; + for(size_t k = 0; j >= 0 && k < sizeof(serialnumber); ++k, j -= 2) { + char buffer[3] = {0}; + memcpy(buffer, optarg + j, 2); + serialnumber[length - k] = (uint8_t)strtol(buffer, NULL, 16); + } + serial_specified = true; + break; } } diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index 46c0d853c..c98424348 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -47,12 +47,13 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ int j = (int)strlen(serial); + int length = j / 2; //the length of the destination-array if(j % 2 != 0) return -1; for(size_t k = 0; j >= 0 && k < sizeof(o->serial); ++k, j -= 2) { char buffer[3] = {0}; memcpy(buffer, serial + j, 2); - o->serial[12 - k] = (uint8_t)strtol(buffer, NULL, 16); + o->serial[length - k] = (uint8_t)strtol(buffer, NULL, 16); } serial_specified = true; From 8253cf1b882314aafb466d85b1a7c9eb6334b61f Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 14 Jan 2017 15:02:36 +0100 Subject: [PATCH 0527/1435] Add tested NUCLEO-L476RG board. Fixes #521 --- README.md | 47 +-------------------------------------- doc/tested-boards.md | 52 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 46 deletions(-) create mode 100644 doc/tested-boards.md diff --git a/README.md b/README.md index 880083a68..c22ef3651 100644 --- a/README.md +++ b/README.md @@ -154,52 +154,7 @@ GDB. Memory map parsing thus fail. Use --enable-expat. ## Currently known working combinations of programmer and target -STLink v1 (as found on the 32VL Discovery board) - -Known working targets: - -* STM32F100xx (Medium Density VL) -* STM32F103 (according to jpa- on ##stm32) - -No information: - -* everything else! - -STLink v2 (as found on the 32L and F4 Discovery boards), known working targets: - -* STM32F030F4P6 (custom board) -* STM32F0Discovery (STM32F0 Discovery board) -* STM32F100xx (Medium Density VL, as on the 32VL Discovery board) -* STM32L1xx (STM32L Discovery board) -* STM32F103VC, STM32F107RC, STM32L151RB, STM32F205RE and STM32F405RE on custom boards - from [UweBonnes/wiki_fuer_alex](https://github.com/UweBonnes/wiki_fuer_alex/tree/master/layout) -* STM32F103VET6 (HY-STM32 board) -* STM32F105RCT6 (DecaWave EVB1000 board) -* STM32F303xx (STM32F3 Discovery board) -* STM32F407xx (STM32F4 Discovery board) -* STM32F429I-DISCO (STM32F4 Discovery board with LCD) -* STM32F439VIT6 (discovery board reseated CPU) -* STM32L052K8T6 (custom board) -* STM32L151CB (custom board) -* STM32L152RB (STM32L-Discovery board, custom board) -* STM32F051R8T6 (STM320518-EVAL board) -* STM32F411E-DISCO (STM32F4 Discovery board with gyro, audio) - -STLink v2-1 (as found on the Nucleo boards), known working targets: - -* STM32F401xx (STM32 Nucleo-F401RE board) -* STM32F030R8T6 (STM32 Nucleo-F030R8 board) -* STM32F072RBT6 (STM32 Nucleo-F072RB board) -* STM32F103RB (STM32 Nucleo-F103RB board) -* STM32F303RET6 (STM32 Nucleo-F303RE board) -* STM32F334R8 (STM32 Nucleo-F334R8 board) -* STM32F411RET6 (STM32 Nucleo-F411RE board) -* STM32F756NGHx (STMF7 evaluation board) -* STM32L053R8 (STM32 Nucleo-L053R8 board) -* STM32F769NI (STM32F7 discovery board) -* Nucleo-L152RE board - -Please report any and all known working combinations so I can update this! +See [doc/tested-boards.md](doc/tested-boards.md) ## Missing features diff --git a/doc/tested-boards.md b/doc/tested-boards.md new file mode 100644 index 000000000..7c16062dd --- /dev/null +++ b/doc/tested-boards.md @@ -0,0 +1,52 @@ +Stlink tested and compatible boards +=================================== + +STLink v1 (as found on the 32VL Discovery board) + +Known working targets: + +* STM32F100xx (Medium Density VL) +* STM32F103 (according to jpa- on ##stm32) + +No information: + +* everything else! + +STLink v2 (as found on the 32L and F4 Discovery boards), known working targets: + +* STM32F030F4P6 (custom board) +* STM32F0Discovery (STM32F0 Discovery board) +* STM32F100xx (Medium Density VL, as on the 32VL Discovery board) +* STM32L1xx (STM32L Discovery board) +* STM32F103VC, STM32F107RC, STM32L151RB, STM32F205RE and STM32F405RE on custom boards + from [UweBonnes/wiki_fuer_alex](https://github.com/UweBonnes/wiki_fuer_alex/tree/master/layout) +* STM32F103VET6 (HY-STM32 board) +* STM32F105RCT6 (DecaWave EVB1000 board) +* STM32F303xx (STM32F3 Discovery board) +* STM32F407xx (STM32F4 Discovery board) +* STM32F429I-DISCO (STM32F4 Discovery board with LCD) +* STM32F439VIT6 (discovery board reseated CPU) +* STM32L052K8T6 (custom board) +* STM32L151CB (custom board) +* STM32L152RB (STM32L-Discovery board, custom board) +* STM32F051R8T6 (STM320518-EVAL board) +* STM32F411E-DISCO (STM32F4 Discovery board with gyro, audio) + +STLink v2-1 (as found on the Nucleo boards), known working targets: + +* STM32F401xx (STM32 Nucleo-F401RE board) +* STM32F030R8T6 (STM32 Nucleo-F030R8 board) +* STM32F072RBT6 (STM32 Nucleo-F072RB board) +* STM32F103RB (STM32 Nucleo-F103RB board) +* STM32F303RET6 (STM32 Nucleo-F303RE board) +* STM32F334R8 (STM32 Nucleo-F334R8 board) +* STM32F411RET6 (STM32 Nucleo-F411RE board) +* STM32F756NGHx (STMF7 evaluation board) +* STM32L053R8 (STM32 Nucleo-L053R8 board) +* STM32F769NI (STM32F7 discovery board) +* Nucleo-L152RE board +* [Nucleo-L476RG board](http://www.st.com/en/evaluation-tools/nucleo-l476rg.html) + +Please report any and all known working combinations so I can update this! + + From 2cb33d45a84179ccc0d13725c93e010e0042f866 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 14 Jan 2017 15:05:26 +0100 Subject: [PATCH 0528/1435] Add note about debhelper for compiling the debian package. Fixes #520 --- doc/compiling.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/doc/compiling.md b/doc/compiling.md index a102be1bd..3a3a38826 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -82,7 +82,8 @@ Options (do one of these before you plug it in) * 2. `modprobe -r usb-storage && modprobe usb-storage` ### Build Debian Package -To build debian package you need debuild. + +To build the debian package you need the following extra packages: `debuild debhelper`. ``` $ git archive --prefix=$(git describe)/ HEAD | bzip2 --stdout > ../libstlink_$(sed -En -e "s/.*\((.*)\).*/\1/" -e "1,1 p" debian/changelog).orig.tar.bz2 From e45451500c8eba96323a76d0a4a75b27c018589d Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 14 Jan 2017 15:08:54 +0100 Subject: [PATCH 0529/1435] README.md: Add missing feature of MCU hotplug. Refs #449 --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index c22ef3651..a6f126445 100644 --- a/README.md +++ b/README.md @@ -162,6 +162,7 @@ See [doc/tested-boards.md](doc/tested-boards.md) * OTP area programming (See [#202](https://github.com/texane/stlink/issues/202)) * EEPROM area programming (See [#318](https://github.com/texane/stlink/issues/218)) * Protection bits area reading (See [#346](https://github.com/texane/stlink/issues/346)) +* MCU hotplug (See [#449](https://github.com/texane/stlink/issues/449)) ## Known bugs From 77acc50705b6f692721f8a1b22ef684ac4143483 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 14 Jan 2017 15:48:22 +0100 Subject: [PATCH 0530/1435] README.md: Improve first-time user documentation --- README.md | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/README.md b/README.md index a6f126445..45a5de82d 100644 --- a/README.md +++ b/README.md @@ -20,15 +20,15 @@ called stlink and there are two versions: Two different transport layers are used: * STLINKv1 uses SCSI passthru commands over USB -* STLINKv2 uses raw USB commands. +* STLINKv2 and STLINKv2-1 (seen on nucleo boards) uses raw USB commands. ## Installation Currently there are no binaries for Windows available (see issue [#166](https://github.com/texane/stlink/issues/166)). - It is known to compile and work with MinGW/Cygwin. + It is known to compile and work with MinGW(64)/Cygwin environment. Building with Visual Studio is not supported because the project uses POSIX APIs and probably will never change. -For Debian Linux based distributions there is also no package available - in the standard repositories so you need to compile yourself. +For Debian Linux based distributions there is no package available + in the standard repositories so you need to install [from source](doc/compiling.md) yourself. Arch Linux users can install from the [repository](https://www.archlinux.org/packages/community/x86_64/stlink) @@ -36,7 +36,9 @@ FreeBSD users can install from [freshports](https://www.freshports.org/devel/stl Mac OS X users can install from [homebrew](http://brewformulas.org/Stlink) -**Compilation from source (advanced users)** +OpenBSD users need to install [from source](doc/compiling.md). + +## Installation from source (advanced users) When there is no executable available for your platform or you need the latest (possible unstable) version you need to compile yourself. This is explained in @@ -156,13 +158,19 @@ GDB. Memory map parsing thus fail. Use --enable-expat. See [doc/tested-boards.md](doc/tested-boards.md) -## Missing features +## Known missing features + +Some features are missing from the `texane/stlink` project and we would like you to + help us out if you want to get involved: * Control programming speed (See [#462](https://github.com/texane/stlink/issues/462)) * OTP area programming (See [#202](https://github.com/texane/stlink/issues/202)) * EEPROM area programming (See [#318](https://github.com/texane/stlink/issues/218)) * Protection bits area reading (See [#346](https://github.com/texane/stlink/issues/346)) * MCU hotplug (See [#449](https://github.com/texane/stlink/issues/449)) +* Writing options bytes (region) (See [#458](https://github.com/texane/stlink/issues/458)) +* Instrumentation Trace Macro (ITM) Cell (See [#136](https://github.com/texane/stlink/issues/136)) +* Writing external memory connected to an STM32 controller (e.g Quad SPI NOR flash) (See [#412](https://github.com/texane/stlink/issues/412)) ## Known bugs @@ -177,15 +185,14 @@ of the flash: 2015-12-09T22:02:18 ERROR src/stlink-common.c: run_flash_loader(0x8000000) failed! == -1 ``` -Issue(s): [#356](https://github.com/texane/stlink/issues/356) +Issue related to this bug: [#356](https://github.com/texane/stlink/issues/356) ## Contributing and versioning * The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) -* When creating a pull request, please open first a issue for discussion of new features -* TODO: Enforcement of coding style (linux codestyle + checkpatch) +* When creating a pull request, please open first a issue for discussion of new features. Bugfixes don't need a discussion. ## License The stlink library and tools are licensed under the [BSD license](LICENSE). With -some exceptions on external components. +some exceptions on external components (e.g flashloaders). From bf1b81b93077ae1c3eadc5d5accc47293ff7f375 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 28 Jan 2017 10:12:53 +0100 Subject: [PATCH 0531/1435] Prepare for v1.3.0 release, update ChangeLog.md --- .version | 2 +- ChangeLog.md | 36 ++++++++++++++++++++++++------------ cmake/CPackConfig.cmake | 8 ++++---- doc/compiling.md | 4 ++-- 4 files changed, 31 insertions(+), 19 deletions(-) diff --git a/.version b/.version index b6bb93f7c..f0bb29e76 100644 --- a/.version +++ b/.version @@ -1 +1 @@ -1.3.0-dev +1.3.0 diff --git a/ChangeLog.md b/ChangeLog.md index fead8b8ec..32c733b03 100644 --- a/ChangeLog.md +++ b/ChangeLog.md @@ -4,28 +4,40 @@ Stlink ChangeLog v1.3.0 ====== -Release date: ongoing +Release date: 2017-01-28 -Major changes: +Major changes and added features: -* Deprecation of autotools (autoconf, automake) (Jerry Jacobs) -* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature (Jerry Jacobs) -* Add debian packaging (nekromant) -* Add intel hex file reading for `st-flash` (pull-request #459) (dev26th) +* Deprecation of autotools (autoconf, automake) (@xor-gate) +* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#3fd0f09](https://github.com/texane/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) +* Add support for native debian packaging ([#444](https://github.com/texane/stlink/pull/444), [#485](https://github.com/texane/stlink/pull/485)) +* Add intel hex file reading for `st-flash` ([#459](https://github.com/texane/stlink/pull/541)) +* Add `--reset` command to `st-flash` ([#505](https://github.com/texane/stlink/pull/505)) +* Support serial numbers argument for `st-util` and `st-flash` for multi-programmer setups ([#541](https://github.com/texane/stlink/pull/541)) +* Add kill ('k') command to gdb-server for `st-util` ([#9804416](https://github.com/texane/stlink/commit/98044163ab34bf5159f121d1c49ffb3550321ca0)) +* Add manpages (generated with pandoc from Markdown) ([#464](https://github.com/texane/stlink/pull/464)) +* Rewrite commandline parsing for `st-flash` ([#459](https://github.com/texane/stlink/pull/459)) +* Add support for ARM semihosting to `st-util` ([#454](https://github.com/texane/stlink/pull/454), [#455](https://github.com/texane/stlink/pull/455)) Chip support added for: -* STM32F410 (Jerry Jacobs) -* L0x Category 5 devices (gluedig) -* Add L0 Category 2 device (chip id: 0x425) (Áron RADICS) +* STM32L432 ([#501](https://github.com/texane/stlink/pull/501)) +* STM32F412 ([#538](https://github.com/texane/stlink/pull/538)) +* STM32F410 ([#9c635e4](https://github.com/texane/stlink/commit/9c635e419deca697ff823000aad2e39d47ec8d6c)) +* Add memory map for STM32F401XE ([#460](https://github.com/texane/stlink/pull/460)) +* L0x Category 5 devices ([#406](https://github.com/texane/stlink/pull/406)) +* Add L0 Category 2 device (chip id: 0x425) ([#72b8e5e](https://github.com/texane/stlink/commit/72b8e5ec87e4fa386a8e94fe68df29467d4354ce)) Updates and fixes: -* Fix memory map for STM32F4 (zulusw) +* Fixed STM32F030 erase error ([#442](https://github.com/texane/stlink/pull/442)) +* Fixed Cygwin build ([#68b0f3b](https://github.com/texane/stlink/commit/68b0f3bddc3c4aaffe34caa6a3201029edd8ad56)) +* Reset flash mass erase (MER) bit after mass erase for safety ([#489](https://github.com/texane/stlink/pull/489)) +* Fix memory map for STM32F4 (@zulusw) * Fix STM32L-problem with flash loader (issue #390) (Tom de Boer) * `st-util` don't read target voltage on startup as it crashes STM32F100 (probably stlink/v1) (Greg Alexander) -* Do a JTAG reset prior to reading CPU information when processor is in deep sleep (andyg24) -* Redesign of `st-flash` commandline options parsing (pull-request #459) (dev26th) +* Do a JTAG reset prior to reading CPU information when processor is in deep sleep (@andyg24) +* Redesign of `st-flash` commandline options parsing (pull-request #459) (@dev26th) v1.2.0 ====== diff --git a/cmake/CPackConfig.cmake b/cmake/CPackConfig.cmake index 1dfd376be..fb6bb1a5c 100644 --- a/cmake/CPackConfig.cmake +++ b/cmake/CPackConfig.cmake @@ -1,13 +1,13 @@ set (CPACK_PACKAGE_NAME ${PROJECT_NAME}) set (CPACK_PACKAGE_VERSION ${PROJECT_VERSION}) -set (CPACK_SOURCE_GENERATOR "TBZ2;ZIP") -set (CPACK_SOURCE_IGNORE_FILES "/build/;/.git/;~$;${CPACK_SOURCE_IGNORE_FILES}") -set (CPACK_SOURCE_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}") set (CPACK_SET_DESTDIR "ON") set (CPACK_INSTALL_PREFIX "${CMAKE_BINARY_DIR}/cpack/staging") if (APPLE) set(CPACK_GENERATOR "ZIP") file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/osx") set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/osx") +elseif (WIN32) + set(CPACK_GENERATOR "ZIP") + file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/windows") + set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/windows") endif() -add_custom_target(dist COMMAND ${CMAKE_MAKE_PROGRAM} package_source) diff --git a/doc/compiling.md b/doc/compiling.md index 3a3a38826..5bac6144a 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -2,9 +2,9 @@ ## Build from sources -* CMake +* CMake (minimal v2.8.7) * C compiler (gcc, clang, mingw) -* Libusb 1.0 +* Libusb 1.0 (minimal v1.0.9) * (optional) pandoc for generating manpages from markdown Run from the root of the source directory: From 0f9e4990ba0cdc295875b219b354fdf42f30a9aa Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 28 Jan 2017 10:16:20 +0100 Subject: [PATCH 0532/1435] README.md: Add note about write protected flash. Fixes #545 --- README.md | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/README.md b/README.md index 45a5de82d..e0e805828 100644 --- a/README.md +++ b/README.md @@ -187,6 +187,37 @@ of the flash: Issue related to this bug: [#356](https://github.com/texane/stlink/issues/356) +### Flash size is detected as zero bytes size + +It is possible that the STM32 flash is write protected, the st-flash tool will show something like this: + +``` +st-flash write prog.bin 0x8000000 +2017-01-24T18:44:14 INFO src/stlink-common.c: Loading device parameters.... +2017-01-24T18:44:14 INFO src/stlink-common.c: Device connected is: F1 High-density device, id 0x10036414 +2017-01-24T18:44:14 INFO src/stlink-common.c: SRAM size: 0x10000 bytes (64 KiB), Flash: 0 bytes (0 KiB) in pages of 2048 bytes +``` + +As you can see, it gives out something unexpected like +``` +Flash: 0 bytes (0 KiB) in pages of 2048 bytes +``` + +``` +st-info --probe +Found 1 stlink programmers + serial: 303030303030303030303031 +openocd: "\x30\x30\x30\x30\x30\x30\x30\x30\x30\x30\x30\x31" + flash: 0 (pagesize: 2048) + sram: 65536 + chipid: 0x0414 + descr: F1 High-density device +``` + +Try to remove the write protection (probably only possible with ST Link Utility from ST itself). + +Issue related to this bug: [#545](https://github.com/texane/stlink/issues/545) + ## Contributing and versioning * The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) From e05ad17253c26ffbeb10fe576af4bb3b51094d45 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 28 Jan 2017 10:21:48 +0100 Subject: [PATCH 0533/1435] Update doc/tutorial.md with latest commandline arguments. Fixes #543. --- doc/tutorial.md | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index 937e2da28..52ed0bc9b 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -33,31 +33,30 @@ identical. Before continuing, the following dependencies must be met: - libusb-1.0 -- pkg-config -- autotools +- cmake STLINK should run on any system meeting the above constraints. The STLINK software source code is retrieved using: ``` -$> git clone https://github.com/texane/stlink stlink.git +$> git clone https://github.com/texane/stlink.git ``` Everything can be built from the top directory: ``` -$> cd stlink.git -$> ./autogen.sh -$> ./configure +$> cd stlink $> make +$> cd build/Release && make install DESTDIR=_install ``` It includes: -- a communication library (stlink.git/libstlink.a), -- a GDB server (stlink.git/st-util), -- a flash manipulation tool (stlink.git/st-flash). +- a communication library (libstlink.a), +- a GDB server (st-util), +- a flash manipulation tool (st-flash). +- a programmer and chip information tool (st-info) Using the GDB server ==================== @@ -134,20 +133,25 @@ memory, or read arbitary addresses of memory out to a binary file, use the st-flash tool, as shown below: ``` - # stlinkv1 command to read 4096 from flash into out.bin -$> ./st-flash read v1 out.bin 0x8000000 4096 +$> ./st-flash read out.bin 0x8000000 4096 # stlinkv2 command $> ./st-flash read out.bin 0x8000000 4096 # stlinkv1 command to write the file in.bin into flash -$> ./st-flash write v1 in.bin 0x8000000 +$> ./st-flash write in.bin 0x8000000 # stlinkv2 command $> ./st-flash write in.bin 0x8000000 ``` +It is also possible to write a hexfile which is more convinient: + +``` +$> ./st-flash --format ihex write myapp.hex +``` + #### Of course, you can use this instead of the gdb server, if you prefer. From 4868a62fbf8bc45d14feeadc155857fd18810a30 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 28 Jan 2017 11:30:30 +0100 Subject: [PATCH 0534/1435] Prepare for win64 static executable builds --- CMakeLists.txt | 44 ++++++++++++++++++++++++++++-------- cmake/CPackConfig.cmake | 5 ++-- doc/build_mingw.md | 23 ------------------- doc/compiling.md | 22 ++++++++++++++++++ doc/man/CMakeLists.txt | 2 +- scripts/mingw64-build.bat | 4 +++- src/gdbserver/CMakeLists.txt | 7 +++++- src/gdbserver/Makefile | 20 ---------------- tests/CMakeLists.txt | 6 ++--- 9 files changed, 72 insertions(+), 61 deletions(-) delete mode 100644 doc/build_mingw.md delete mode 100644 src/gdbserver/Makefile diff --git a/CMakeLists.txt b/CMakeLists.txt index 4aac51c05..9a3e06355 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -66,12 +66,16 @@ include_directories(include) include_directories(${PROJECT_BINARY_DIR}/include) include_directories(src/mingw) +### # Shared library -add_library(${PROJECT_NAME} SHARED +### +set(STLINK_LIB_SHARED ${PROJECT_NAME}-shared) + +add_library(${STLINK_LIB_SHARED} SHARED ${STLINK_HEADERS} # header files for ide projects generated by cmake ${STLINK_SOURCE} ) -target_link_libraries(${PROJECT_NAME} ${LIBUSB_LIBRARY}) +target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY}) if (WIN32 OR MSYS OR MINGW) set(STLINK_SHARED_VERSION ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}) @@ -79,25 +83,27 @@ else() set(STLINK_SHARED_VERSION ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}) endif() -set_target_properties(${PROJECT_NAME} +set_target_properties(${STLINK_LIB_SHARED} PROPERTIES SOVERSION ${PROJECT_VERSION_MAJOR} VERSION ${STLINK_SHARED_VERSION} ) +# Link shared library with apple OS libraries if (APPLE) find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) find_library(IOKit IOKit) - target_link_libraries(${PROJECT_NAME} ${CoreFoundation} ${IOKit} ${ObjC}) + target_link_libraries(${STLINK_LIB_SHARED} ${CoreFoundation} ${IOKit} ${ObjC}) endif () -if(WIN32 OR MSYS OR MINGW) - target_link_libraries(${PROJECT_NAME} ${LIBUSB_LIBRARY} wsock32 ws2_32) +# Link +if (WIN32 OR MSYS OR MINGW) + target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} wsock32 ws2_32) else() - target_link_libraries(${PROJECT_NAME} ${LIBUSB_LIBRARY}) + target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY}) endif() -install(TARGETS ${PROJECT_NAME} +install(TARGETS ${STLINK_LIB_SHARED} DESTINATION lib/${CMAKE_LIBRARY_PATH} ) @@ -110,7 +116,17 @@ add_library(${STLINK_LIB_STATIC} STATIC ${STLINK_HEADERS} # header files for ide projects generated by cmake ${STLINK_SOURCE} ) + target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY}) + +# Link shared library with apple OS libraries +if (APPLE) + find_library(ObjC objc) + find_library(CoreFoundation CoreFoundation) + find_library(IOKit IOKit) + target_link_libraries(${STLINK_LIB_STATIC} ${CoreFoundation} ${IOKit} ${ObjC}) +endif () + set_target_properties(${STLINK_LIB_STATIC} PROPERTIES OUTPUT_NAME ${PROJECT_NAME}) install(TARGETS ${STLINK_LIB_STATIC} @@ -121,10 +137,18 @@ install(TARGETS ${STLINK_LIB_STATIC} # Tools ### add_executable(st-flash src/tools/flash.c src/tools/flash_opts.c) -target_link_libraries(st-flash ${PROJECT_NAME}) +if (WIN32 OR APPLE) + target_link_libraries(st-flash ${STLINK_LIB_STATIC}) +else() + target_link_libraries(st-flash ${STLINK_LIB_SHARED}) +endif() add_executable(st-info src/tools/info.c) -target_link_libraries(st-info ${PROJECT_NAME}) +if (WIN32 OR APPLE) + target_link_libraries(st-info ${STLINK_LIB_STATIC}) +else() + target_link_libraries(st-info ${STLINK_LIB_SHARED}) +endif() install(TARGETS st-flash st-info RUNTIME DESTINATION bin diff --git a/cmake/CPackConfig.cmake b/cmake/CPackConfig.cmake index fb6bb1a5c..3dc2b6a3a 100644 --- a/cmake/CPackConfig.cmake +++ b/cmake/CPackConfig.cmake @@ -1,13 +1,14 @@ set (CPACK_PACKAGE_NAME ${PROJECT_NAME}) set (CPACK_PACKAGE_VERSION ${PROJECT_VERSION}) set (CPACK_SET_DESTDIR "ON") -set (CPACK_INSTALL_PREFIX "${CMAKE_BINARY_DIR}/cpack/staging") if (APPLE) set(CPACK_GENERATOR "ZIP") file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/osx") + set (CPACK_INSTALL_PREFIX "${CMAKE_BINARY_DIR}/cpack/staging") set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/osx") elseif (WIN32) set(CPACK_GENERATOR "ZIP") file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/windows") + set (CPACK_INSTALL_PREFIX "") set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/windows") -endif() +endif() \ No newline at end of file diff --git a/doc/build_mingw.md b/doc/build_mingw.md deleted file mode 100644 index 6327b57c6..000000000 --- a/doc/build_mingw.md +++ /dev/null @@ -1,23 +0,0 @@ -Building with MinGW under Windows -================================= - -## Prequistes - -* 7Zip -* CMake 2.8 or higher -* MinGW64 GCC toolchain (5.3.0) - -## Installation - -1. Install 7Zip from http://www.7-zip.org -2. Install CMake from https://cmake.org/download -3. Install MinGW64 from https://sourceforge.net/projects/mingw-w64 (mingw-w64-install.exe) -4. Git clone or download stlink sourcefiles zip -5. Create build folder in source - -# Building - -Check and execute `\scripts\mingw64-build.bat` - -NOTE: when installing different toolchains make sure you edit the path in the `mingw64-build.bat` - the build script uses currently `C:\Program Files\mingw-w64\x86_64-5.3.0-win32-sjlj-rt_v4-rev0\mingw64\bin` diff --git a/doc/compiling.md b/doc/compiling.md index 5bac6144a..30f23b63a 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -117,3 +117,25 @@ during installation you can use the following cmake options: $ cmake -DSTLINK_UDEV_RULES_DIR="/usr/lib/udev/rules.d" \ -DSTLINK_MODPROBED_DIR="/usr/lib/modprobe.d" .. ``` + +## Windows (MinGW64) + +### Prequistes + +* 7Zip +* CMake 2.8 or higher +* MinGW64 GCC toolchain (5.3.0) + +### Installation + +1. Install 7Zip from +2. Install CMake from +3. Install MinGW64 from (mingw-w64-install.exe) +4. Git clone or download stlink sourcefiles zip + +### Building + +Check and execute (in the script folder) `\scripts\mingw64-build.bat` + +NOTE: when installing different toolchains make sure you edit the path in the `mingw64-build.bat` + the build script uses currently `C:\Program Files\mingw-w64\x86_64-5.3.0-win32-sjlj-rt_v4-rev0\mingw64\bin` diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 83bb008cf..949cd2fcf 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -30,7 +30,7 @@ foreach(manpage ${MANPAGES}) message(AUTHOR_WARNING "Manpage ${manpage} not generated") endif() - if (f) + if (f AND NOT WIN32) install(FILES ${f} DESTINATION ${CMAKE_INSTALL_PREFIX}/share/man/man1) unset(f) endif() diff --git a/scripts/mingw64-build.bat b/scripts/mingw64-build.bat index 52c6fffb1..3f92ae8e0 100644 --- a/scripts/mingw64-build.bat +++ b/scripts/mingw64-build.bat @@ -1,4 +1,6 @@ @echo off set PATH=C:\Program Files (x86)\CMake\bin;C:\Program Files\CMake\bin;C:\Program Files\mingw-w64\x86_64-5.3.0-win32-sjlj-rt_v4-rev0\mingw64\bin;%PATH% cmake -G "MinGW Makefiles" .. -mingw32-make \ No newline at end of file +mingw32-make +mingw32-make install DESTDIR=_install +mingw32-make package diff --git a/src/gdbserver/CMakeLists.txt b/src/gdbserver/CMakeLists.txt index c6114f6d6..a41890c70 100644 --- a/src/gdbserver/CMakeLists.txt +++ b/src/gdbserver/CMakeLists.txt @@ -4,7 +4,12 @@ add_executable(st-util gdb-remote.c gdb-server.h semihosting.c semihosting.h) -target_link_libraries(st-util ${PROJECT_NAME}) +if (WIN32 OR APPLE) + target_link_libraries(st-util ${STLINK_LIB_STATIC}) +else() + target_link_libraries(st-util ${STLINK_LIB_SHARED}) +endif() + install(TARGETS st-util RUNTIME DESTINATION bin ) diff --git a/src/gdbserver/Makefile b/src/gdbserver/Makefile deleted file mode 100644 index bd5c73dbc..000000000 --- a/src/gdbserver/Makefile +++ /dev/null @@ -1,20 +0,0 @@ -PRG := st-util -OBJS = gdb-remote.o gdb-server.o - -CFLAGS+=-g -Wall -Werror -std=gnu99 -I../src -LDFLAGS=-L.. -lstlink - -# libusb location -LDFLAGS+=`pkg-config --libs libusb-1.0` -CFLAGS+=`pkg-config --cflags libusb-1.0` - -all: $(PRG) - -$(PRG): $(OBJS) ../libstlink.a - $(CC) -o $@ $^ $(LDFLAGS) - -clean: - rm -rf $(OBJS) - rm -rf $(PRG) - -.PHONY: clean all diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index fc51433bd..8df28ce7e 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -5,11 +5,11 @@ set(TESTS foreach(test ${TESTS}) add_executable(${test} ${test}.c) - add_dependencies(${test} ${PROJECT_NAME}) - target_link_libraries(${test} ${PROJECT_NAME}) + add_dependencies(${test} ${STLINK_LIB_STATIC}) + target_link_libraries(${test} ${STLINK_LIB_STATIC}) add_test(${test} ${CMAKE_CURRENT_BINARY_DIR}/${test}) endforeach() add_executable(flash flash.c "${CMAKE_SOURCE_DIR}/src/tools/flash_opts.c") -target_link_libraries(flash ${PROJECT_NAME}) +target_link_libraries(flash ${STLINK_LIB_STATIC}) add_test(flash ${CMAKE_CURRENT_BINARY_DIR}/flash) From 1b36565d7d94cb0198be742848e86bd28791ad01 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 28 Jan 2017 11:49:06 +0100 Subject: [PATCH 0535/1435] CMakeLists.txt: Fix last piece to compile static on windows --- CMakeLists.txt | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 9a3e06355..254751b42 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -58,7 +58,7 @@ set(STLINK_SOURCE ) if (WIN32 OR MSYS OR MINGW) - set (STLINK_SOURCE "${STLINK_SOURCE};src/mmap.c;src/mingw/mingw.c") # TODO + set (STLINK_SOURCE "${STLINK_SOURCE};src/mmap.c;src/mingw/mingw.c") endif () include_directories(${LIBUSB_INCLUDE_DIR}) @@ -94,9 +94,8 @@ if (APPLE) find_library(CoreFoundation CoreFoundation) find_library(IOKit IOKit) target_link_libraries(${STLINK_LIB_SHARED} ${CoreFoundation} ${IOKit} ${ObjC}) -endif () +endif() -# Link if (WIN32 OR MSYS OR MINGW) target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} wsock32 ws2_32) else() @@ -117,15 +116,19 @@ add_library(${STLINK_LIB_STATIC} STATIC ${STLINK_SOURCE} ) -target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY}) - # Link shared library with apple OS libraries if (APPLE) find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) find_library(IOKit IOKit) target_link_libraries(${STLINK_LIB_STATIC} ${CoreFoundation} ${IOKit} ${ObjC}) -endif () +endif() + +if (WIN32 OR MSYS OR MINGW) + target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} wsock32 ws2_32) +else() + target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY}) +endif() set_target_properties(${STLINK_LIB_STATIC} PROPERTIES OUTPUT_NAME ${PROJECT_NAME}) From ca4ff46b5a053e1660b207524c677e7de6f6ac7d Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 28 Jan 2017 11:55:48 +0100 Subject: [PATCH 0536/1435] README.md: Prepare for v1.3.0 release --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index e0e805828..3fc467abd 100644 --- a/README.md +++ b/README.md @@ -2,7 +2,7 @@ Open source version of the STMicroelectronics Stlink Tools ========================================================== [![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/texane/stlink/releases/latest) -[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.2.0.svg)](https://github.com/texane/stlink/compare/1.2.0...master) +[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.3.0.svg)](https://github.com/texane/stlink/compare/1.3.0...master) [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) [![Build Status](https://jenkins.ncrmnt.org/buildStatus/icon?job=GithubCI/stlink)](https://jenkins.ncrmnt.org/job/GithubCI/job/stlink/) [![Build status](https://ci.appveyor.com/api/projects/status/wrcie05d4jmut0te?svg=true)](https://ci.appveyor.com/project/xor-gate/stlink) From f546110bafa07185c399f2556f702a932bc63c3e Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 28 Jan 2017 12:09:37 +0100 Subject: [PATCH 0537/1435] cmake/CPackConfig.cmake: Fixup OSX zip filename --- cmake/CPackConfig.cmake | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/cmake/CPackConfig.cmake b/cmake/CPackConfig.cmake index 3dc2b6a3a..ac3cc6f7e 100644 --- a/cmake/CPackConfig.cmake +++ b/cmake/CPackConfig.cmake @@ -3,12 +3,13 @@ set (CPACK_PACKAGE_VERSION ${PROJECT_VERSION}) set (CPACK_SET_DESTDIR "ON") if (APPLE) set(CPACK_GENERATOR "ZIP") + set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-macosx-amd64") file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/osx") - set (CPACK_INSTALL_PREFIX "${CMAKE_BINARY_DIR}/cpack/staging") + set (CPACK_INSTALL_PREFIX "") set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/osx") elseif (WIN32) set(CPACK_GENERATOR "ZIP") file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/windows") set (CPACK_INSTALL_PREFIX "") set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/windows") -endif() \ No newline at end of file +endif() From ed813270e3b73feaa2e92b6f96384df31c52d49c Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 28 Jan 2017 13:08:30 +0100 Subject: [PATCH 0538/1435] README.md: Add downloads counter badge --- README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 3fc467abd..e3358c5b3 100644 --- a/README.md +++ b/README.md @@ -2,11 +2,12 @@ Open source version of the STMicroelectronics Stlink Tools ========================================================== [![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/texane/stlink/releases/latest) +[![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) [![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.3.0.svg)](https://github.com/texane/stlink/compare/1.3.0...master) +[![Downloads](https://img.shields.io/github/downloads/texane/stlink/total.svg)](https://github.com/texane/stlink/releases) [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) [![Build Status](https://jenkins.ncrmnt.org/buildStatus/icon?job=GithubCI/stlink)](https://jenkins.ncrmnt.org/job/GithubCI/job/stlink/) [![Build status](https://ci.appveyor.com/api/projects/status/wrcie05d4jmut0te?svg=true)](https://ci.appveyor.com/project/xor-gate/stlink) -[![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) ## HOWTO From eea16d762979fcfc28937c784c480c8346247a3a Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sun, 29 Jan 2017 09:20:20 +0100 Subject: [PATCH 0539/1435] Update README.md Add note for windows and mac binaries with release v1.3.0 --- README.md | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index e3358c5b3..d2bd2330b 100644 --- a/README.md +++ b/README.md @@ -25,8 +25,9 @@ Two different transport layers are used: ## Installation -Currently there are no binaries for Windows available (see issue [#166](https://github.com/texane/stlink/issues/166)). - It is known to compile and work with MinGW(64)/Cygwin environment. Building with Visual Studio is not supported because the project uses POSIX APIs and probably will never change. +Windows users can [download v1.3.0](https://github.com/texane/stlink/releases/tag/1.3.0) from the releases page. + +Mac OS X users can install from [homebrew](http://brewformulas.org/Stlink) or [download v1.3.0](https://github.com/texane/stlink/releases/tag/1.3.0) from the releases page. For Debian Linux based distributions there is no package available in the standard repositories so you need to install [from source](doc/compiling.md) yourself. @@ -35,8 +36,6 @@ Arch Linux users can install from the [repository](https://www.archlinux.org/pac FreeBSD users can install from [freshports](https://www.freshports.org/devel/stlink) -Mac OS X users can install from [homebrew](http://brewformulas.org/Stlink) - OpenBSD users need to install [from source](doc/compiling.md). ## Installation from source (advanced users) From 4f460ecab288a5f8186469c86b55142ad0ea7296 Mon Sep 17 00:00:00 2001 From: m-schwerin Date: Mon, 30 Jan 2017 01:06:25 -0500 Subject: [PATCH 0540/1435] Add support for STM32F413 target (#549) Add support for STM32F413 target. Fixes #550. --- include/stlink/chipid.h | 3 ++- src/chipid.c | 12 ++++++++++++ src/flash_loader.c | 1 + 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 36fb73c62..84aff7f80 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -55,7 +55,8 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F0_CAN = 0x448, STLINK_CHIPID_STM32_F7 = 0x449, STLINK_CHIPID_STM32_F7XXXX = 0x451, - STLINK_CHIPID_STM32_F410 = 0x458 + STLINK_CHIPID_STM32_F410 = 0x458, + STLINK_CHIPID_STM32_F413 = 0x463 }; /** diff --git a/src/chipid.c b/src/chipid.c index 13307a99e..4318db787 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -298,6 +298,18 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 .bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4 }, + { + // RM0430 DocID029473 Rev 2 document was used to find these parameters + // Figure 2, Table 4, Table 5, Section 35.2 + .chip_id = STLINK_CHIPID_STM32_F413, + .description = "F4 device", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 + .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector sizes, but 0x4000 is smallest) + .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 only says 0x40000) + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4 + }, { .chip_id = STLINK_CHIPID_STM32_F09X, .description = "F09X device", diff --git a/src/flash_loader.c b/src/flash_loader.c index f4d81cbab..0b05f4ab6 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -219,6 +219,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_F410 || sl->chip_id == STLINK_CHIPID_STM32_F411RE || sl->chip_id == STLINK_CHIPID_STM32_F412 || + sl->chip_id == STLINK_CHIPID_STM32_F413 || sl->chip_id == STLINK_CHIPID_STM32_F446 ) { if( sl->version.stlink_v == 1 ) { From e71a2417c31aeee685a1a6ea22c7b53f6fbd48f8 Mon Sep 17 00:00:00 2001 From: Bertrand Songis Date: Mon, 30 Jan 2017 23:16:36 +0100 Subject: [PATCH 0541/1435] Compilation fixes (errors / warnings) (#552) --- include/stlink/tools/flash.h | 4 +--- src/common.c | 2 +- src/gdbserver/semihosting.c | 8 ++++---- src/tools/flash.c | 4 ++-- src/tools/gui/CMakeLists.txt | 4 ++-- tests/flash.c | 2 +- 6 files changed, 11 insertions(+), 13 deletions(-) diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index bb7bd739e..6a7b05484 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -22,9 +22,7 @@ struct flash_opts enum flash_format format; }; - -#define FLASH_OPTS_INITIALIZER {0, } - +#define FLASH_OPTS_INITIALIZER {0, NULL, {}, NULL, 0, 0, 0, 0, 0 } int flash_get_opts(struct flash_opts* o, int ac, char** av); diff --git a/src/common.c b/src/common.c index f104a1629..ccbbbe248 100644 --- a/src/common.c +++ b/src/common.c @@ -2048,7 +2048,7 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, if(e > end) end = e; } else { - for(size_t i = 0; i < reclen; ++i) { + for(uint8_t i = 0; i < reclen; ++i) { uint8_t b = stlink_parse_hex(line + 9 + i*2); uint32_t addr = lba + offset + i; if(addr >= *begin && addr <= end) { diff --git a/src/gdbserver/semihosting.c b/src/gdbserver/semihosting.c index 4ea6ccf5c..4be8090f5 100644 --- a/src/gdbserver/semihosting.c +++ b/src/gdbserver/semihosting.c @@ -247,7 +247,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { uint32_t args[3]; uint32_t buffer_address; int fd; - size_t buffer_len; + uint32_t buffer_len; void *buffer; if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { @@ -259,7 +259,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { fd = (int)args[0]; buffer_address = args[1]; - buffer_len = (size_t)args[2]; + buffer_len = args[2]; if (buffer_len > MAX_BUFFER_SIZE) { DLOG("Semihosting SYS_WRITE error: buffer size is too big %d\n", @@ -305,7 +305,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { uint32_t args[3]; uint32_t buffer_address; int fd; - size_t buffer_len; + uint32_t buffer_len; void *buffer; if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { @@ -317,7 +317,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { fd = (int)args[0]; buffer_address = args[1]; - buffer_len = (size_t)args[2]; + buffer_len = args[2]; if (buffer_len > MAX_BUFFER_SIZE) { DLOG("Semihosting SYS_READ error: buffer size is too big %d\n", diff --git a/src/tools/flash.c b/src/tools/flash.c index 1b6c7a7da..f2c186e95 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -135,7 +135,7 @@ int main(int ac, char** av) if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { if(o.format == FLASH_FORMAT_IHEX) - err = stlink_mwrite_flash(sl, mem, size, o.addr); + err = stlink_mwrite_flash(sl, mem, (uint32_t)size, o.addr); else err = stlink_fwrite_flash(sl, o.filename, o.addr); if (err == -1) @@ -147,7 +147,7 @@ int main(int ac, char** av) else if ((o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { if(o.format == FLASH_FORMAT_IHEX) - err = stlink_mwrite_sram(sl, mem, size, o.addr); + err = stlink_mwrite_sram(sl, mem, (uint32_t)size, o.addr); else err = stlink_fwrite_sram(sl, o.filename, o.addr); if (err == -1) diff --git a/src/tools/gui/CMakeLists.txt b/src/tools/gui/CMakeLists.txt index e217af03a..53d1d862d 100644 --- a/src/tools/gui/CMakeLists.txt +++ b/src/tools/gui/CMakeLists.txt @@ -10,13 +10,13 @@ include_directories(SYSTEM ${gtk_INCLUDE_DIRS}) add_executable(stlink-gui-local ${GUI_SOURCES}) set_target_properties(stlink-gui-local PROPERTIES COMPILE_FLAGS -DSTLINK_UI_DIR=\\"${CMAKE_CURRENT_SOURCE_DIR}/gui\\") -target_link_libraries(stlink-gui-local stlink ${gtk_LDFLAGS}) +target_link_libraries(stlink-gui-local ${STLINK_LIB_STATIC} ${gtk_LDFLAGS}) add_executable(stlink-gui ${GUI_SOURCES}) set_target_properties(stlink-gui PROPERTIES COMPILE_FLAGS -DSTLINK_UI_DIR=\\"${CMAKE_INSTALL_PREFIX}/${INSTALLED_UI_DIR}\\") -target_link_libraries(stlink-gui stlink ${gtk_LDFLAGS}) +target_link_libraries(stlink-gui ${STLINK_LIB_STATIC} ${gtk_LDFLAGS}) install(TARGETS stlink-gui RUNTIME DESTINATION bin) diff --git a/tests/flash.c b/tests/flash.c index 27fd437f6..fd55fdfc1 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -59,7 +59,7 @@ static bool execute_test(const struct Test * test) { return ret; } -struct Test tests[] = { +static struct Test tests[] = { { "", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset read /dev/sg0 test.bin 0x80000000 0x1000", 0, { .cmd = FLASH_CMD_READ, .devname = "/dev/sg0", .serial = {}, .filename = "test.bin", From f62895b2cf3ccbbc87be1d8525e9dc51645f2516 Mon Sep 17 00:00:00 2001 From: Fabien Chouteau Date: Tue, 31 Jan 2017 07:29:44 +0100 Subject: [PATCH 0542/1435] Semihosting: Add support of SYS_READC (#546) --- src/gdbserver/semihosting.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/gdbserver/semihosting.c b/src/gdbserver/semihosting.c index 4be8090f5..34591d120 100644 --- a/src/gdbserver/semihosting.c +++ b/src/gdbserver/semihosting.c @@ -457,6 +457,12 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { } break; } + case SYS_READC: + { + uint8_t c = getchar(); + *ret = c; + break; + } case SYS_WRITE0: { uint8_t buf[WRITE0_BUFFER_SIZE]; From 7b314c954199d8b2b1439eab55925a943f9a2395 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Wed, 1 Feb 2017 19:04:09 +0100 Subject: [PATCH 0543/1435] Update README.md Remove appveyor MinGW64 build badge (broken) --- README.md | 1 - 1 file changed, 1 deletion(-) diff --git a/README.md b/README.md index d2bd2330b..bec30c119 100644 --- a/README.md +++ b/README.md @@ -7,7 +7,6 @@ Open source version of the STMicroelectronics Stlink Tools [![Downloads](https://img.shields.io/github/downloads/texane/stlink/total.svg)](https://github.com/texane/stlink/releases) [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) [![Build Status](https://jenkins.ncrmnt.org/buildStatus/icon?job=GithubCI/stlink)](https://jenkins.ncrmnt.org/job/GithubCI/job/stlink/) -[![Build status](https://ci.appveyor.com/api/projects/status/wrcie05d4jmut0te?svg=true)](https://ci.appveyor.com/project/xor-gate/stlink) ## HOWTO From cd1ba149903c57df8d24ee7d60b69af290611b89 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Wed, 1 Feb 2017 23:12:39 +0100 Subject: [PATCH 0544/1435] README.md: Add Alpine Linux for installation --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index e3358c5b3..7e4667516 100644 --- a/README.md +++ b/README.md @@ -33,6 +33,8 @@ For Debian Linux based distributions there is no package available Arch Linux users can install from the [repository](https://www.archlinux.org/packages/community/x86_64/stlink) +Alpine Linux users can install from the [repository](https://pkgs.alpinelinux.org/packages?name=stlink) + FreeBSD users can install from [freshports](https://www.freshports.org/devel/stlink) Mac OS X users can install from [homebrew](http://brewformulas.org/Stlink) From 2c0ab7f0eb6cfda5cfbdc08bb9f6760d27c2b667 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Tue, 14 Feb 2017 19:51:24 +0100 Subject: [PATCH 0545/1435] logging: Don't print absolute path to source file. Fixes #548 --- CMakeLists.txt | 5 +++++ include/stlink/logging.h | 15 ++++++++++----- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 254751b42..285b5c713 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -38,6 +38,11 @@ if (${CMAKE_BUILD_TYPE} MATCHES "Debug") include(CTest) endif() +# fixup __FILE__ absolute paths in logging module +# see: https://cmake.org/pipermail/cmake-developers/2015-January/024202.html +string(LENGTH "${CMAKE_SOURCE_DIR}/" CMAKE_SOURCE_DIR_LENGTH) +add_definitions(-DCMAKE_SOURCE_DIR_LENGTH=${CMAKE_SOURCE_DIR_LENGTH}) + set(STLINK_HEADERS include/stlink.h include/stlink/usb.h diff --git a/include/stlink/logging.h b/include/stlink/logging.h index 81e5f598c..9a98a6bc5 100644 --- a/include/stlink/logging.h +++ b/include/stlink/logging.h @@ -20,17 +20,22 @@ enum ugly_loglevel { int ugly_init(int maximum_threshold); int ugly_log(int level, const char *tag, const char *format, ...); +#ifndef CMAKE_SOURCE_DIR_LENGTH +#define CMAKE_SOURCE_DIR_LENGTH 0 +#endif +#define UGLY_LOG_FILE (__FILE__+CMAKE_SOURCE_DIR_LENGTH) + /** @todo we need to write this in a more generic way, for now this should compile on visual studio (See http://stackoverflow.com/a/8673872/1836746) */ -#define DLOG_HELPER(format, ...) ugly_log(UDEBUG, __FILE__, format, __VA_ARGS__) +#define DLOG_HELPER(format, ...) ugly_log(UDEBUG, UGLY_LOG_FILE, format, __VA_ARGS__) #define DLOG(...) DLOG_HELPER(__VA_ARGS__, "") -#define ILOG_HELPER(format, ...) ugly_log(UINFO, __FILE__, format, __VA_ARGS__) +#define ILOG_HELPER(format, ...) ugly_log(UINFO, UGLY_LOG_FILE, format, __VA_ARGS__) #define ILOG(...) ILOG_HELPER(__VA_ARGS__, "") -#define WLOG_HELPER(format, ...) ugly_log(UWARN, __FILE__, format, __VA_ARGS__) +#define WLOG_HELPER(format, ...) ugly_log(UWARN, UGLY_LOG_FILE, format, __VA_ARGS__) #define WLOG(...) WLOG_HELPER(__VA_ARGS__, "") -#define ELOG_HELPER(format, ...) ugly_log(UERROR, __FILE__, format, __VA_ARGS__) +#define ELOG_HELPER(format, ...) ugly_log(UERROR, UGLY_LOG_FILE, format, __VA_ARGS__) #define ELOG(...) ELOG_HELPER(__VA_ARGS__, "") -#define fatal_helper(format, ...) ugly_log(UFATAL, __FILE__, format, __VA_ARGS__) +#define fatal_helper(format, ...) ugly_log(UFATAL, UGLY_LOG_FILE, format, __VA_ARGS__) #define fatal(...) fatal_helper(__VA_ARGS__, "") #ifdef __cplusplus From 67eba4badb38b31d8363ef04c1da3275aa5f5342 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Tue, 14 Feb 2017 20:11:40 +0100 Subject: [PATCH 0546/1435] chipid: Add support for STM32L011 (NUCLEO-L011K4 --- include/stlink/chipid.h | 1 + src/chipid.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 84aff7f80..6a078aa1b 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -55,6 +55,7 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F0_CAN = 0x448, STLINK_CHIPID_STM32_F7 = 0x449, STLINK_CHIPID_STM32_F7XXXX = 0x451, + STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, STLINK_CHIPID_STM32_F413 = 0x463 }; diff --git a/src/chipid.c b/src/chipid.c index 4318db787..049b77979 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -445,6 +445,17 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) .bootrom_size = 0x7000 // 28k (per bank), same source as base }, + { + // STM32L011 + .chip_id = STLINK_CHIPID_STM32_L011, + .description = "L011 device", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x4000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000 + }, }; From fc4fd76a7564428289f79d88ab75b2a094882510 Mon Sep 17 00:00:00 2001 From: Joost Rijneveld Date: Mon, 20 Feb 2017 18:45:07 +0100 Subject: [PATCH 0547/1435] Fix incorrect release folder name in docs (#560) --- doc/compiling.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index 30f23b63a..296d64b17 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -27,13 +27,13 @@ $ make You could install to a user folder e.g `$HOME`: ``` -$ cd release; make install DESTDIR=$HOME +$ cd build/Release; make install DESTDIR=$HOME ``` Or system wide: ``` -$ cd release; sudo make install +$ cd build/Release; sudo make install ``` ## Linux From 28a15598c022b72448fa54aa845120d44bfcb182 Mon Sep 17 00:00:00 2001 From: Joost Rijneveld Date: Tue, 21 Feb 2017 11:03:58 +0100 Subject: [PATCH 0548/1435] Fix compilation when path includes spaces (#561) --- src/tools/gui/CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/tools/gui/CMakeLists.txt b/src/tools/gui/CMakeLists.txt index 53d1d862d..4ab9975da 100644 --- a/src/tools/gui/CMakeLists.txt +++ b/src/tools/gui/CMakeLists.txt @@ -9,13 +9,13 @@ include_directories(SYSTEM ${gtk_INCLUDE_DIRS}) add_executable(stlink-gui-local ${GUI_SOURCES}) set_target_properties(stlink-gui-local PROPERTIES - COMPILE_FLAGS -DSTLINK_UI_DIR=\\"${CMAKE_CURRENT_SOURCE_DIR}/gui\\") + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_CURRENT_SOURCE_DIR}/gui") target_link_libraries(stlink-gui-local ${STLINK_LIB_STATIC} ${gtk_LDFLAGS}) add_executable(stlink-gui ${GUI_SOURCES}) set_target_properties(stlink-gui PROPERTIES - COMPILE_FLAGS -DSTLINK_UI_DIR=\\"${CMAKE_INSTALL_PREFIX}/${INSTALLED_UI_DIR}\\") + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/${INSTALLED_UI_DIR}") target_link_libraries(stlink-gui ${STLINK_LIB_STATIC} ${gtk_LDFLAGS}) install(TARGETS stlink-gui From 6f24bde1aefde8f543861cab8c205e564cb7fb36 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 25 Feb 2017 17:45:21 +0100 Subject: [PATCH 0549/1435] Prepare for v1.3.1 bugfix release --- .version | 2 +- ChangeLog.md | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/.version b/.version index f0bb29e76..3a3cd8cc8 100644 --- a/.version +++ b/.version @@ -1 +1 @@ -1.3.0 +1.3.1 diff --git a/ChangeLog.md b/ChangeLog.md index 32c733b03..b8f5b78de 100644 --- a/ChangeLog.md +++ b/ChangeLog.md @@ -1,6 +1,24 @@ Stlink ChangeLog ================ +v1.3.1 +====== + +Release date: 2017-02-25 + +Major changes and added features: + +* Add preliminary support for STM32L011 to see it after probe (chipid `0x457`) (@xor-gate) +* Strip full paths to source files in log (commit [#2c0ab7f](https://github.com/texane/stlink/commit/2c0ab7f0eb6cfda5cfbdc08bb9f6760d27c2b667)) +* Add support for STM32F413 target ([#549](https://github.com/texane/stlink/pull/549)) +* Add support for Semihosting `SYS_READC` ([#546](https://github.com/texane/stlink/pull/546)) + +Updates and fixes: + +* Update documentation markdown files +* Compilation fixes ([#552](https://github.com/texane/stlink/pull/552)) +* Fix compilation when path includes spaces ([#561](https://github.com/texane/stlink/pull/561)) + v1.3.0 ====== From c816cb4732582996758d46bd14745087c834b51b Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 25 Feb 2017 17:50:55 +0100 Subject: [PATCH 0550/1435] README.md: Update badges to 1.3.1 release --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index eb45a8ff2..3c6f48a0d 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ Open source version of the STMicroelectronics Stlink Tools [![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/texane/stlink/releases/latest) [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) -[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.3.0.svg)](https://github.com/texane/stlink/compare/1.3.0...master) +[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.3.1.svg)](https://github.com/texane/stlink/compare/1.3.1...master) [![Downloads](https://img.shields.io/github/downloads/texane/stlink/total.svg)](https://github.com/texane/stlink/releases) [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) [![Build Status](https://jenkins.ncrmnt.org/buildStatus/icon?job=GithubCI/stlink)](https://jenkins.ncrmnt.org/job/GithubCI/job/stlink/) From 5b69f25198a1a8f34e2ee48d1ad20f79447e3d55 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Tue, 28 Feb 2017 20:09:46 +0100 Subject: [PATCH 0551/1435] cmake/CPackConfig.cmake: Allow building of debian package with CPack --- cmake/CPackConfig.cmake | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/cmake/CPackConfig.cmake b/cmake/CPackConfig.cmake index ac3cc6f7e..20768453b 100644 --- a/cmake/CPackConfig.cmake +++ b/cmake/CPackConfig.cmake @@ -12,4 +12,16 @@ elseif (WIN32) file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/windows") set (CPACK_INSTALL_PREFIX "") set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/windows") +elseif(${CMAKE_SYSTEM_NAME} STREQUAL "Linux" AND EXISTS "/etc/debian_version") + message(STATUS "Debian-based Linux OS detected") + set(CPACK_GENERATOR "DEB") + + if ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "x86_64") + set(CPACK_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${PROJECT_VERSION}-amd64" ) + endif() + + set(CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/texane/stlink") + set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Jerry Jacobs") + set(CPACK_PACKAGE_CONTACT "jerry.jacobs@xor-gate.org") + set(CPACK_DEBIAN_PACKAGE_DESCRIPTION "STM32 stlink programmer tools") endif() From 1adaedbdbc311674c9412e40ba363251171acd25 Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Wed, 1 Mar 2017 20:56:24 +0200 Subject: [PATCH 0552/1435] Update libusb to 1.0.21 under windows (#562) * fix wrong libusb extract command * update libusb to 1.0.21 under windows --- cmake/modules/FindLibUSB.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index 84020b98b..b106018d2 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -9,7 +9,7 @@ if(WIN32 OR CMAKE_VS_PLATFORM_NAME OR MINGW OR MSYS) find_package(7Zip REQUIRED) - set(LIBUSB_WIN_VERSION 1.0.20) + set(LIBUSB_WIN_VERSION 1.0.21) set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/3thparty/libusb-${LIBUSB_WIN_VERSION}) From 9d08810c68da4aa7233add53b4a570abff78df44 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Wed, 1 Mar 2017 20:08:08 +0100 Subject: [PATCH 0553/1435] Update ChangeLog.md --- ChangeLog.md | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/ChangeLog.md b/ChangeLog.md index b8f5b78de..f12d176f6 100644 --- a/ChangeLog.md +++ b/ChangeLog.md @@ -1,6 +1,15 @@ Stlink ChangeLog ================ +v1.3.2 +====== + +Release date: ongoing + +Updates and fixes: + +* Update libusb to 1.0.21 for Windows ([#562](https://github.com/texane/stlink/pull/562)) + v1.3.1 ====== From bc48e99b194dba002628a3b841fd18cb4dd2762e Mon Sep 17 00:00:00 2001 From: zulusw Date: Tue, 14 Mar 2017 10:54:02 -0700 Subject: [PATCH 0554/1435] Fixing low-voltage flashing on STM32F7 parts. (#567) * fixing low voltage flashing for STM32F7 * Refactoring duplicated code --- flashloaders/stm32f7.s | 33 +++++++++++++++ flashloaders/stm32f7lv.s | 34 +++++++++++++++ src/flash_loader.c | 90 +++++++++++++++++++++++++++++++--------- 3 files changed, 138 insertions(+), 19 deletions(-) create mode 100644 flashloaders/stm32f7.s create mode 100644 flashloaders/stm32f7lv.s diff --git a/flashloaders/stm32f7.s b/flashloaders/stm32f7.s new file mode 100644 index 000000000..0334c80a0 --- /dev/null +++ b/flashloaders/stm32f7.s @@ -0,0 +1,33 @@ +.global start +.syntax unified + +@ r0 = source +@ r1 = target +@ r2 = wordcount +@ r3 = flash_base +@ r4 = temp + +start: + ldr r3, flash_base +next: + cbz r2, done + ldr r4, [r0] + str r4, [r1] + dsb sy + +wait: + ldrh r4, [r3, #0x0e] + tst.w r4, #1 + bne wait + + add r0, #4 + add r1, #4 + sub r2, #1 + b next +done: + bkpt + +.align 2 + +flash_base: + .word 0x40023c00 diff --git a/flashloaders/stm32f7lv.s b/flashloaders/stm32f7lv.s new file mode 100644 index 000000000..650922719 --- /dev/null +++ b/flashloaders/stm32f7lv.s @@ -0,0 +1,34 @@ +.global start +.syntax unified + +@ r0 = source +@ r1 = target +@ r2 = wordcount +@ r3 = flash_base +@ r4 = temp + +start: + lsls r2, r2, #2 + ldr r3, flash_base +next: + cbz r2, done + ldrb r4, [r0] + strb r4, [r1] + dsb sy + +wait: + ldrh r4, [r3, #0x0e] + tst.w r4, #1 + bne wait + + add r0, #1 + add r1, #1 + sub r2, #1 + b next +done: + bkpt + +.align 2 + +flash_base: + .word 0x40023c00 diff --git a/src/flash_loader.c b/src/flash_loader.c index 0b05f4ab6..ed53a0c6b 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -156,6 +156,7 @@ static const uint8_t loader_code_stm32vl[] = { }; static const uint8_t loader_code_stm32f7[] = { + // flashloaders/stm32f7.s 0x08, 0x4b, 0x72, 0xb1, 0x04, 0x68, @@ -172,6 +173,30 @@ static const uint8_t loader_code_stm32vl[] = { 0x00, 0x3c, 0x02, 0x40, }; + static const uint8_t loader_code_stm32f7_lv[] = { + // flashloaders/stm32f7lv.s + 0x92, 0x00, // lsls r2, r2, #2 + 0x09, 0x4b, // ldr r3, [pc, #36] ; (0x20000028 ) + // next: + 0x72, 0xb1, // cbz r2, 24 + 0x04, 0x78, // ldrb r4, [r0, #0] + 0x0c, 0x70, // strb r4, [r1, #0] + 0xbf, 0xf3, 0x4f, 0x8f, // dsb sy + // wait: + 0xdc, 0x89, // ldrh r4, [r3, #14] + 0x14, 0xf0, 0x01, 0x0f, // tst.w r4, #1 + 0xfb, 0xd1, // bne.n e + 0x00, 0xf1, 0x01, 0x00, // add r0, r0, #1 + 0x01, 0xf1, 0x01, 0x01, // add r1, r1, #1 + 0xa2, 0xf1, 0x01, 0x02, // sub r2, r2, #1 + 0xef, 0xe7, // b next + // done: + 0x00, 0xbe, // bkpt + 0x00, 0xbf, // nop + // flash_base: + 0x00, 0x3c, 0x02, 0x40 // .word 0x40023c00 + }; + int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) @@ -191,6 +216,37 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) return 0; } +static int loader_v_dependent_assignment(stlink_t *sl, + const uint8_t **loader_code, size_t *loader_size, + const uint8_t *high_v_loader, size_t high_v_loader_size, + const uint8_t *low_v_loader, size_t low_v_loader_size) +{ + int retval = 0; + + if( sl->version.stlink_v == 1 ) { + printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes\n"); + *loader_code = high_v_loader; + *loader_size = high_v_loader_size; + } + else { + int voltage = stlink_target_voltage(sl); + if (voltage == -1) { + retval = -1; + printf("Failed to read Target voltage\n"); + } + else { + if (voltage > 2700) { + *loader_code = high_v_loader; + *loader_size = high_v_loader_size; + } else { + *loader_code = low_v_loader; + *loader_size = low_v_loader_size; + } + } + } + return retval; +} + int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { const uint8_t* loader_code; @@ -222,29 +278,25 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_F413 || sl->chip_id == STLINK_CHIPID_STM32_F446 ) { - if( sl->version.stlink_v == 1 ) { - printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes on F4 devices\n"); - loader_code = loader_code_stm32f4; - loader_size = sizeof(loader_code_stm32f4); - } - else { - int voltage = stlink_target_voltage(sl); - if (voltage == -1) { - printf("Failed to read Target voltage\n"); - return voltage; - } else if (voltage > 2700) { - loader_code = loader_code_stm32f4; - loader_size = sizeof(loader_code_stm32f4); - } else { - loader_code = loader_code_stm32f4_lv; - loader_size = sizeof(loader_code_stm32f4_lv); - } + int retval; + retval = loader_v_dependent_assignment(sl, + &loader_code, &loader_size, + loader_code_stm32f4, sizeof(loader_code_stm32f4), + loader_code_stm32f4_lv, sizeof(loader_code_stm32f4_lv)); + if (retval == -1) { + return retval; } } else if (sl->core_id == STM32F7_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { - loader_code = loader_code_stm32f7; - loader_size = sizeof(loader_code_stm32f7); + int retval; + retval = loader_v_dependent_assignment(sl, + &loader_code, &loader_size, + loader_code_stm32f7, sizeof(loader_code_stm32f7), + loader_code_stm32f7_lv, sizeof(loader_code_stm32f7_lv)); + if (retval == -1) { + return retval; + } } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || sl->chip_id == STLINK_CHIPID_STM32_F0_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F09X) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); From f73ec11abc53b6c5627456077995a6006515a5be Mon Sep 17 00:00:00 2001 From: Oliver Schneider Date: Tue, 14 Mar 2017 18:54:56 +0100 Subject: [PATCH 0555/1435] Fix stlink on mingw64 (#569) --- src/gdbserver/gdb-server.c | 24 ++++++++++++------------ src/tools/info.c | 6 +++--- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index fddf48fcf..09e80f32a 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -393,20 +393,20 @@ static const char* const memory_map_template_F2 = "" "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram + " " // code = sram, bootrom or flash; flash is bigger + " " // sram " " //Sectors 0..3 " 0x4000" //16kB " " " " //Sector 4 " 0x10000" //64kB " " - " " //Sectors 5.. + " " //Sectors 5.. " 0x20000" //128kB " " " " // peripheral regs " " // cortex regs - " " // bootrom + " " // bootrom " " // option byte area ""; @@ -415,10 +415,10 @@ static const char* const memory_map_template_L4 = "" "" - " " // code = sram, bootrom or flash; flash is bigger + " " // code = sram, bootrom or flash; flash is bigger " " // SRAM2 (32 KB) " " // SRAM1 (96 KB) - " " + " " " 0x800" " " " " // peripheral regs @@ -434,14 +434,14 @@ static const char* const memory_map_template = "" "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram 8k - " " - " 0x%zx" + " " // code = sram, bootrom or flash; flash is bigger + " " // sram 8k + " " + " 0x%x" " " " " // peripheral regs " " // cortex regs - " " // bootrom + " " // bootrom " " // option byte area ""; @@ -452,7 +452,7 @@ static const char* const memory_map_template_F7 = "" " " // ITCM ram 16kB " " // ITCM flash - " " // sram + " " // sram " " // Sectors 0..3 " 0x8000" // 32kB " " diff --git a/src/tools/info.c b/src/tools/info.c index 2e3efc64d..54e6ec87c 100644 --- a/src/tools/info.c +++ b/src/tools/info.c @@ -114,11 +114,11 @@ static int print_data(char **av) stlink_enter_swd_mode(sl); if (strcmp(av[1], "--flash") == 0) - printf("0x%zx\n", sl->flash_size); + printf("0x%x\n", sl->flash_size); else if (strcmp(av[1], "--sram") == 0) - printf("0x%zx\n", sl->sram_size); + printf("0x%x\n", sl->sram_size); else if (strcmp(av[1], "--pagesize") == 0) - printf("0x%zx\n", sl->flash_pgsz); + printf("0x%x\n", sl->flash_pgsz); else if (strcmp(av[1], "--chipid") == 0) printf("0x%.4x\n", sl->chip_id); else if (strcmp(av[1], "--serial") == 0) From 8efd3adc8ae70ecea387ec5dfea9db04c1aaf1aa Mon Sep 17 00:00:00 2001 From: thebaron06 Date: Wed, 15 Mar 2017 12:58:37 +0100 Subject: [PATCH 0556/1435] Fix possible memory leak (#571) fixes #570 --- src/usb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/usb.c b/src/usb.c index 4b57ed98f..03ac1ab3c 100644 --- a/src/usb.c +++ b/src/usb.c @@ -855,6 +855,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 if (ret != 0) { WLOG("Error %d (%s) opening ST-Link/V2 device %03d:%03d\n", ret, strerror (errno), libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); + libusb_free_device_list(list, 1); goto on_error; } } From dc9055362c88aca4dba18d0133758c649d1bcbad Mon Sep 17 00:00:00 2001 From: Zach Fredin Date: Wed, 15 Mar 2017 15:53:15 -0500 Subject: [PATCH 0557/1435] fixed support for STM32L011 (#572) --- src/chipid.c | 6 +++--- src/common.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/chipid.c b/src/chipid.c index 049b77979..15b2f563a 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -452,9 +452,9 @@ static const struct stlink_chipid_params devices[] = { .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, - .sram_size = 0x4000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000 + .sram_size = 0x2000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x2000 }, diff --git a/src/common.c b/src/common.c index ccbbbe248..c55bff54a 100644 --- a/src/common.c +++ b/src/common.c @@ -1467,7 +1467,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) uint32_t val; uint32_t flash_regs_base; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || sl->chip_id == STLINK_CHIPID_STM32_L011) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; } else { flash_regs_base = STM32L_FLASH_REGS_ADDR; @@ -1663,7 +1663,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin uint32_t flash_regs_base; flash_loader_t fl; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || sl->chip_id == STLINK_CHIPID_STM32_L011) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; } else { flash_regs_base = STM32L_FLASH_REGS_ADDR; @@ -1838,7 +1838,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t uint32_t flash_regs_base; uint32_t pagesize; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || sl->chip_id == STLINK_CHIPID_STM32_L011) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; pagesize = L0_WRITE_BLOCK_SIZE; } else { From c04df7fe61a0cab8c555ae0890744e7586c114d5 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Wed, 15 Mar 2017 22:50:38 +0100 Subject: [PATCH 0558/1435] Revert "Fix stlink on mingw64" (#573) * Revert "fixed support for STM32L011 (#572)" This reverts commit dc9055362c88aca4dba18d0133758c649d1bcbad. * Revert "Fix possible memory leak (#571)" This reverts commit 8efd3adc8ae70ecea387ec5dfea9db04c1aaf1aa. * Revert "Fix stlink on mingw64 (#569)" This reverts commit f73ec11abc53b6c5627456077995a6006515a5be. --- src/gdbserver/gdb-server.c | 24 ++++++++++++------------ src/tools/info.c | 6 +++--- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 09e80f32a..fddf48fcf 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -393,20 +393,20 @@ static const char* const memory_map_template_F2 = "" "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram + " " // code = sram, bootrom or flash; flash is bigger + " " // sram " " //Sectors 0..3 " 0x4000" //16kB " " " " //Sector 4 " 0x10000" //64kB " " - " " //Sectors 5.. + " " //Sectors 5.. " 0x20000" //128kB " " " " // peripheral regs " " // cortex regs - " " // bootrom + " " // bootrom " " // option byte area ""; @@ -415,10 +415,10 @@ static const char* const memory_map_template_L4 = "" "" - " " // code = sram, bootrom or flash; flash is bigger + " " // code = sram, bootrom or flash; flash is bigger " " // SRAM2 (32 KB) " " // SRAM1 (96 KB) - " " + " " " 0x800" " " " " // peripheral regs @@ -434,14 +434,14 @@ static const char* const memory_map_template = "" "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram 8k - " " - " 0x%x" + " " // code = sram, bootrom or flash; flash is bigger + " " // sram 8k + " " + " 0x%zx" " " " " // peripheral regs " " // cortex regs - " " // bootrom + " " // bootrom " " // option byte area ""; @@ -452,7 +452,7 @@ static const char* const memory_map_template_F7 = "" " " // ITCM ram 16kB " " // ITCM flash - " " // sram + " " // sram " " // Sectors 0..3 " 0x8000" // 32kB " " diff --git a/src/tools/info.c b/src/tools/info.c index 54e6ec87c..2e3efc64d 100644 --- a/src/tools/info.c +++ b/src/tools/info.c @@ -114,11 +114,11 @@ static int print_data(char **av) stlink_enter_swd_mode(sl); if (strcmp(av[1], "--flash") == 0) - printf("0x%x\n", sl->flash_size); + printf("0x%zx\n", sl->flash_size); else if (strcmp(av[1], "--sram") == 0) - printf("0x%x\n", sl->sram_size); + printf("0x%zx\n", sl->sram_size); else if (strcmp(av[1], "--pagesize") == 0) - printf("0x%x\n", sl->flash_pgsz); + printf("0x%zx\n", sl->flash_pgsz); else if (strcmp(av[1], "--chipid") == 0) printf("0x%.4x\n", sl->chip_id); else if (strcmp(av[1], "--serial") == 0) From 9775689196a0d6f4f29677a54deb5875c292259e Mon Sep 17 00:00:00 2001 From: Warren Gay Date: Fri, 24 Mar 2017 18:10:05 -0400 Subject: [PATCH 0559/1435] Added --flash=n[k][m] command line option to override device model (#576) * Added --flash=xxxx to st-flash command line --- doc/man/st-flash.1 | 8 ++++++++ doc/man/st-flash.md | 4 ++++ include/stlink/tools/flash.h | 3 ++- src/tools/flash.c | 10 ++++++++-- src/tools/flash_opts.c | 25 ++++++++++++++++++++++++- 5 files changed, 46 insertions(+), 4 deletions(-) diff --git a/doc/man/st-flash.1 b/doc/man/st-flash.1 index 252ffcba8..77a8bb550 100644 --- a/doc/man/st-flash.1 +++ b/doc/man/st-flash.1 @@ -53,6 +53,14 @@ TODO TODO .RS .RE +.TP +.B --flash=\f[I]size\f[] +Override the device's normal flash size, where size is the flash size in bytes. +It can be specified in decimal, octal or hexadecimal. +The size argument can optionally be followed by 'k' for KB or 'm' for MB. +Examples --flash=128k or --flash=0x080k. +.RS +.RE .SH EXAMPLES .PP Flash \f[C]firmware.bin\f[] to device diff --git a/doc/man/st-flash.md b/doc/man/st-flash.md index 4eacb7a07..d1844976c 100644 --- a/doc/man/st-flash.md +++ b/doc/man/st-flash.md @@ -49,6 +49,10 @@ reset --serial *iSerial* : TODO +--flash=fsize +: Where fsize is the size in decimal, octal, or hex followed by an optional multiplier +'k' for KB, or 'm' for MB. +Use a leading "0x" to specify hexadecimal, or a leading zero for octal. # EXAMPLES Flash `firmware.bin` to device diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index 6a7b05484..35b3a4251 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -20,9 +20,10 @@ struct flash_opts int reset; int log_level; enum flash_format format; + size_t flash_size; /* --flash=n[k][m] */ }; -#define FLASH_OPTS_INITIALIZER {0, NULL, {}, NULL, 0, 0, 0, 0, 0 } +#define FLASH_OPTS_INITIALIZER {0, NULL, {}, NULL, 0, 0, 0, 0, 0, 0 } int flash_get_opts(struct flash_opts* o, int ac, char** av); diff --git a/src/tools/flash.c b/src/tools/flash.c index f2c186e95..6fe365f88 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -29,12 +29,13 @@ static void cleanup(int signum) { static void usage(void) { - puts("stlinkv1 command line: ./st-flash [--debug] [--reset] [--format ] {read|write} /dev/sgX "); + puts("stlinkv1 command line: ./st-flash [--debug] [--reset] [--format ] [--flash=] {read|write} /dev/sgX "); puts("stlinkv1 command line: ./st-flash [--debug] /dev/sgX erase"); - puts("stlinkv2 command line: ./st-flash [--debug] [--reset] [--serial ] [--format ] {read|write} "); + puts("stlinkv2 command line: ./st-flash [--debug] [--reset] [--serial ] [--format ] [--flash=] {read|write} "); puts("stlinkv2 command line: ./st-flash [--debug] [--serial ] erase"); puts("stlinkv2 command line: ./st-flash [--debug] [--serial ] reset"); puts(" Use hex format for addr, and ."); + puts(" fsize: Use decimal, octal or hex by prefix 0xXXX for hex, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); puts(" Format may be 'binary' (default) or 'ihex', although must be specified for binary format only."); puts(" ./st-flash [--version]"); } @@ -64,6 +65,11 @@ int main(int ac, char** av) if (sl == NULL) return -1; + if ( o.flash_size != 0u && o.flash_size != sl->flash_size ) { + sl->flash_size = o.flash_size; + printf("Forcing flash size: --flash=0x%08zX\n",sl->flash_size); + } + sl->verbose = o.log_level; connected_stlink = sl; diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index c98424348..4fa39de4c 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -77,7 +77,30 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) else return -1; } - else { + else if ( starts_with(av[0], "--flash=") ) { + const char *arg = av[0] + strlen("--flash="); + char *ep = 0; + + o->flash_size = (uint32_t)strtoul(arg,&ep,0); + while ( *ep ) { + switch ( *ep++ ) { + case 0: + break; + case 'k': + case 'K': + o->flash_size *= 1024u; + break; + case 'm': + case 'M': + o->flash_size *= 1024u * 1024u; + break; + default: + fprintf(stderr,"Invalid --flash=%s\n",arg); + return -1; + } + } + } + else { break; // non-option found } From 78ced6a325b174626959baef6e3b014e72cfcf0e Mon Sep 17 00:00:00 2001 From: Oliver Schneider Date: Fri, 24 Mar 2017 23:11:09 +0100 Subject: [PATCH 0560/1435] Don't use `%zx` because it's unsupported on mingw64 (#578) * Don't use `%zx` because it's unsupported on mingw64 * Also check that no warnings happen on travis * Prefer `unsigned int` over `unsigned` * Install libusb through the travis whitelist instead of manually * Test stlink against clang and gcc through the travis "compiler" flag instead of a manual matrix * Re-add osx * Fix warning on gcc --- .travis.sh | 2 +- .travis.yml | 19 ++++------ cmake/CFlags.cmake | 3 +- src/gdbserver/gdb-server.c | 74 +++++++++++++++++++------------------- src/tools/gui/stlink-gui.c | 4 +-- src/tools/info.c | 6 ++-- 6 files changed, 52 insertions(+), 56 deletions(-) diff --git a/.travis.sh b/.travis.sh index 82c1fd862..06e95ef80 100755 --- a/.travis.sh +++ b/.travis.sh @@ -7,7 +7,7 @@ echo "----" if [ "$TRAVIS_OS_NAME" == "linux" ]; then sudo apt-get update -qq || true - sudo apt-get install -qq -y --no-install-recommends libusb-1.0.0-dev libgtk-3-dev + sudo apt-get install -qq -y --no-install-recommends libgtk-3-dev else brew install libusb fi diff --git a/.travis.yml b/.travis.yml index 2bf170d2b..25d1859f7 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,5 +1,11 @@ sudo: true language: c +compiler: + - gcc + - clang +os: + - linux + - osx addons: apt: sources: @@ -10,20 +16,9 @@ addons: # - clang-3.8 - g++-5 - gcc-5 + - libusb-1.0.0-dev script: - git fetch --tags - printenv - cmake --version - ./.travis.sh -matrix: - include: - - os: linux - compiler: clang -# - os: linux -# compiler: clang-3.8 - - os: linux - compiler: gcc-5 -# - os: linux -# compiler: clang-3.8 - - os: osx - compiler: clang diff --git a/cmake/CFlags.cmake b/cmake/CFlags.cmake index b17463707..b76856d24 100644 --- a/cmake/CFlags.cmake +++ b/cmake/CFlags.cmake @@ -44,6 +44,7 @@ endif () if(${CMAKE_BUILD_TYPE} MATCHES "Debug") add_cflag_if_supported("-ggdb") add_cflag_if_supported("-O0") -elseif() +else() add_cflag_if_supported("-O2") + add_cflag_if_supported("-Werror") endif() diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index fddf48fcf..4d4a9cfce 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -393,20 +393,20 @@ static const char* const memory_map_template_F2 = "" "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram + " " // code = sram, bootrom or flash; flash is bigger + " " // sram " " //Sectors 0..3 " 0x4000" //16kB " " " " //Sector 4 " 0x10000" //64kB " " - " " //Sectors 5.. + " " //Sectors 5.. " 0x20000" //128kB " " " " // peripheral regs " " // cortex regs - " " // bootrom + " " // bootrom " " // option byte area ""; @@ -415,10 +415,10 @@ static const char* const memory_map_template_L4 = "" "" - " " // code = sram, bootrom or flash; flash is bigger + " " // code = sram, bootrom or flash; flash is bigger " " // SRAM2 (32 KB) " " // SRAM1 (96 KB) - " " + " " " 0x800" " " " " // peripheral regs @@ -434,14 +434,14 @@ static const char* const memory_map_template = "" "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram 8k - " " - " 0x%zx" + " " // code = sram, bootrom or flash; flash is bigger + " " // sram 8k + " " + " 0x%x" " " " " // peripheral regs " " // cortex regs - " " // bootrom + " " // bootrom " " // option byte area ""; @@ -452,7 +452,7 @@ static const char* const memory_map_template_F7 = "" " " // ITCM ram 16kB " " // ITCM flash - " " // sram + " " // sram " " // Sectors 0..3 " 0x8000" // 32kB " " @@ -505,24 +505,24 @@ char* make_memory_map(stlink_t *sl) { strcpy(map, memory_map_template_F4_DE); } else if(sl->core_id==STM32F7_CORE_ID) { snprintf(map, sz, memory_map_template_F7, - sl->sram_size); + (unsigned int)sl->sram_size); } else if(sl->chip_id==STLINK_CHIPID_STM32_F4_HD) { strcpy(map, memory_map_template_F4_HD); } else if(sl->chip_id==STLINK_CHIPID_STM32_F2) { snprintf(map, sz, memory_map_template_F2, - sl->flash_size, - sl->sram_size, - sl->flash_size - 0x20000, - sl->sys_base, sl->sys_size); + (unsigned int)sl->flash_size, + (unsigned int)sl->sram_size, + (unsigned int)sl->flash_size - 0x20000, + (unsigned int)sl->sys_base, (unsigned int)sl->sys_size); } else if(sl->chip_id==STLINK_CHIPID_STM32_L4) { snprintf(map, sz, memory_map_template_L4, - sl->flash_size, sl->flash_size); + (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); } else { snprintf(map, sz, memory_map_template, - sl->flash_size, - sl->sram_size, - sl->flash_size, sl->flash_pgsz, - sl->sys_base, sl->sys_size); + (unsigned int)sl->flash_size, + (unsigned int)sl->sram_size, + (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz, + (unsigned int)sl->sys_base, (unsigned int)sl->sys_size); } return map; } @@ -831,7 +831,7 @@ static int flash_go(stlink_t *sl) { stlink_calculate_pagesize(sl, page); DLOG("flash_do: page %08x\n", page); - unsigned len = (length > FLASH_PAGE) ? (unsigned) FLASH_PAGE : length; + unsigned len = (length > FLASH_PAGE) ? (unsigned int) FLASH_PAGE : length; int ret = stlink_write_flash(sl, page, fb->data + (page - fb->addr), len, 0); if (ret < 0) goto error; @@ -1109,7 +1109,7 @@ int serve(stlink_t *sl, st_state_t *st) { params = separator + 1; } - unsigned queryNameLength = (unsigned) (separator - &packet[1]); + unsigned queryNameLength = (unsigned int) (separator - &packet[1]); char* queryName = calloc(queryNameLength + 1, 1); strncpy(queryName, &packet[1], queryNameLength); @@ -1135,8 +1135,8 @@ int serve(stlink_t *sl, st_state_t *st) { __s_addr = strsep(&tok, ","); s_length = tok; - unsigned addr = (unsigned) strtoul(__s_addr, NULL, 16), - length = (unsigned) strtoul(s_length, NULL, 16); + unsigned addr = (unsigned int) strtoul(__s_addr, NULL, 16), + length = (unsigned int) strtoul(s_length, NULL, 16); DLOG("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", type, op, annex, addr, length); @@ -1150,7 +1150,7 @@ int serve(stlink_t *sl, st_state_t *st) { data = target_description_F4; if(data) { - unsigned data_length = (unsigned) strlen(data); + unsigned data_length = (unsigned int) strlen(data); if(addr + length > data_length) length = data_length - addr; @@ -1265,8 +1265,8 @@ int serve(stlink_t *sl, st_state_t *st) { __s_addr = strsep(&tok, ","); s_length = tok; - unsigned addr = (unsigned) strtoul(__s_addr, NULL, 16), - length = (unsigned) strtoul(s_length, NULL, 16); + unsigned addr = (unsigned int) strtoul(__s_addr, NULL, 16), + length = (unsigned int) strtoul(s_length, NULL, 16); DLOG("FlashErase: addr:%08x,len:%04x\n", addr, length); @@ -1283,8 +1283,8 @@ int serve(stlink_t *sl, st_state_t *st) { __s_addr = strsep(&tok, ":"); data = tok; - unsigned addr = (unsigned) strtoul(__s_addr, NULL, 16); - unsigned data_length = status - (unsigned) (data - packet); + unsigned addr = (unsigned int) strtoul(__s_addr, NULL, 16); + unsigned data_length = status - (unsigned int) (data - packet); // Length of decoded data cannot be more than // encoded, as escapes are removed. @@ -1433,7 +1433,7 @@ int serve(stlink_t *sl, st_state_t *st) { break; case 'p': { - unsigned id = (unsigned) strtoul(&packet[1], NULL, 16); + unsigned id = (unsigned int) strtoul(&packet[1], NULL, 16); unsigned myreg = 0xDEADDEAD; if(id < 16) { @@ -1480,8 +1480,8 @@ int serve(stlink_t *sl, st_state_t *st) { char* s_reg = &packet[1]; char* s_value = strstr(&packet[1], "=") + 1; - unsigned reg = (unsigned) strtoul(s_reg, NULL, 16); - unsigned value = (unsigned) strtoul(s_value, NULL, 16); + unsigned reg = (unsigned int) strtoul(s_reg, NULL, 16); + unsigned value = (unsigned int) strtoul(s_value, NULL, 16); if(reg < 16) { stlink_write_reg(sl, ntohl(value), reg); @@ -1530,12 +1530,12 @@ int serve(stlink_t *sl, st_state_t *st) { char* s_count = strstr(&packet[1], ",") + 1; stm32_addr_t start = (stm32_addr_t) strtoul(s_start, NULL, 16); - unsigned count = (unsigned) strtoul(s_count, NULL, 16); + unsigned count = (unsigned int) strtoul(s_count, NULL, 16); unsigned adj_start = start % 4; unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; if (count_rnd > sl->flash_pgsz) - count_rnd = (unsigned) sl->flash_pgsz; + count_rnd = (unsigned int) sl->flash_pgsz; if (count_rnd > 0x1800) count_rnd = 0x1800; if (count_rnd < count) @@ -1561,7 +1561,7 @@ int serve(stlink_t *sl, st_state_t *st) { char* hexdata = strstr(packet, ":") + 1; stm32_addr_t start = (stm32_addr_t) strtoul(s_start, NULL, 16); - unsigned count = (unsigned) strtoul(s_count, NULL, 16); + unsigned count = (unsigned int) strtoul(s_count, NULL, 16); int err = 0; if(start % 4) { diff --git a/src/tools/gui/stlink-gui.c b/src/tools/gui/stlink-gui.c index 535f9bb33..d45db6ff2 100644 --- a/src/tools/gui/stlink-gui.c +++ b/src/tools/gui/stlink-gui.c @@ -735,7 +735,7 @@ dnd_received_cb (GtkWidget *widget, gint y, GtkSelectionData *selection_data, guint target_type, - guint time, + guint timestamp, gpointer data) { GFile *file_uri; @@ -783,7 +783,7 @@ dnd_received_cb (GtkWidget *widget, gtk_drag_finish (context, TRUE, gdk_drag_context_get_suggested_action (context) == GDK_ACTION_MOVE, - time); + timestamp); } void diff --git a/src/tools/info.c b/src/tools/info.c index 2e3efc64d..2ad8f2c09 100644 --- a/src/tools/info.c +++ b/src/tools/info.c @@ -114,11 +114,11 @@ static int print_data(char **av) stlink_enter_swd_mode(sl); if (strcmp(av[1], "--flash") == 0) - printf("0x%zx\n", sl->flash_size); + printf("0x%x\n", (unsigned int)sl->flash_size); else if (strcmp(av[1], "--sram") == 0) - printf("0x%zx\n", sl->sram_size); + printf("0x%x\n", (unsigned int)sl->sram_size); else if (strcmp(av[1], "--pagesize") == 0) - printf("0x%zx\n", sl->flash_pgsz); + printf("0x%x\n", (unsigned int)sl->flash_pgsz); else if (strcmp(av[1], "--chipid") == 0) printf("0x%.4x\n", sl->chip_id); else if (strcmp(av[1], "--serial") == 0) From 6902f473fc94c06c2633a9b92bd9479d65bc7108 Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Tue, 4 Apr 2017 00:05:06 +0300 Subject: [PATCH 0561/1435] fix few -Wformat warnings (#582) * fix wrong libusb extract command * update libusb to 1.0.21 under windows * fix few -Wformat warnings * add usleep realisation for win32 under mingw --- src/common.c | 4 ++-- src/mingw/mingw.c | 12 ++++++++++++ src/mingw/mingw.h | 1 + src/tools/flash.c | 2 +- 4 files changed, 16 insertions(+), 3 deletions(-) diff --git a/src/common.c b/src/common.c index c55bff54a..74b96f5da 100644 --- a/src/common.c +++ b/src/common.c @@ -1753,7 +1753,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t return -1; } fprintf(stdout,"\rFlash page at addr: 0x%08lx erased", - (unsigned long)addr + off); + (unsigned long)(addr + off)); fflush(stdout); page_count++; } @@ -1934,7 +1934,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t if (sl->verbose >= 1) { /* show progress. writing procedure is slow and previous errors are misleading */ - fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)len/sl->flash_pgsz); + fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)(len/sl->flash_pgsz)); fflush(stdout); } } diff --git a/src/mingw/mingw.c b/src/mingw/mingw.c index 3c5d025a3..ee0515972 100644 --- a/src/mingw/mingw.c +++ b/src/mingw/mingw.c @@ -265,6 +265,18 @@ char *win32_strsep (char **stringp, const char *delim) /* NOTREACHED */ } +void usleep(DWORD waitTime) +{ + LARGE_INTEGER perf_cnt, start, now; + + QueryPerformanceFrequency(&perf_cnt); + QueryPerformanceCounter(&start); + + do { + QueryPerformanceCounter((LARGE_INTEGER*) &now); + } while ((now.QuadPart - start.QuadPart) / (float)perf_cnt.QuadPart * 1000 * 1000 < waitTime); +} + #endif diff --git a/src/mingw/mingw.h b/src/mingw/mingw.h index cb333016c..242c8eb98 100644 --- a/src/mingw/mingw.h +++ b/src/mingw/mingw.h @@ -66,5 +66,6 @@ ssize_t win32_read_socket(SOCKET fd, void *buf, int n); ssize_t win32_write_socket(SOCKET fd, void *buf, int n); static inline void sleep(unsigned ms) { Sleep(ms); } +void usleep(DWORD waitTime); #endif diff --git a/src/tools/flash.c b/src/tools/flash.c index 6fe365f88..508c4aa84 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -67,7 +67,7 @@ int main(int ac, char** av) if ( o.flash_size != 0u && o.flash_size != sl->flash_size ) { sl->flash_size = o.flash_size; - printf("Forcing flash size: --flash=0x%08zX\n",sl->flash_size); + printf("Forcing flash size: --flash=0x%08X\n",(unsigned int)sl->flash_size); } sl->verbose = o.log_level; From 47ab2901b9d6d2819117775179a1d0fb8cc3df72 Mon Sep 17 00:00:00 2001 From: Karol Szuster Date: Wed, 5 Apr 2017 20:48:07 +0200 Subject: [PATCH 0562/1435] Fix installation path for shared objects (#581) On 64bit linux all shared objects should go to /usr/lib64. With this path package maintainters should be able to override library path by setting STLINK_LIBRARY_PATH. --- CMakeLists.txt | 5 +++-- usr/lib/pkgconfig/CMakeLists.txt | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 285b5c713..626ba34a6 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -3,6 +3,7 @@ project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics Stlink Tools") set(STLINK_UDEV_RULES_DIR "/etc/udev/rules.d" CACHE PATH "Udev rules directory") set(STLINK_MODPROBED_DIR "/etc/modprobe.d" CACHE PATH "modprobe.d directory") +set(STLINK_LIBRARY_PATH "lib/${CMAKE_LIBRARY_PATH}" CACHE PATH "Target lib directory") option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) @@ -108,7 +109,7 @@ else() endif() install(TARGETS ${STLINK_LIB_SHARED} - DESTINATION lib/${CMAKE_LIBRARY_PATH} + DESTINATION ${STLINK_LIBRARY_PATH} ) ### @@ -138,7 +139,7 @@ endif() set_target_properties(${STLINK_LIB_STATIC} PROPERTIES OUTPUT_NAME ${PROJECT_NAME}) install(TARGETS ${STLINK_LIB_STATIC} - ARCHIVE DESTINATION lib/${CMAKE_LIBRARY_PATH} + ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH} ) ### diff --git a/usr/lib/pkgconfig/CMakeLists.txt b/usr/lib/pkgconfig/CMakeLists.txt index 5ddc500ca..1d7bcd1dc 100644 --- a/usr/lib/pkgconfig/CMakeLists.txt +++ b/usr/lib/pkgconfig/CMakeLists.txt @@ -10,5 +10,5 @@ configure_file( ) install(FILES "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" - DESTINATION lib/${CMAKE_LIBRARY_PATH}/pkgconfig/ + DESTINATION ${STLINK_LIBRARY_PATH}/pkgconfig/ ) From eb03b7c2903307410da97b897662b24c730b1014 Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Thu, 6 Apr 2017 22:16:54 +0300 Subject: [PATCH 0563/1435] Get rid of unused defines in mingw.h (#583) * Get rid of unused defines in mingw.h --- src/mingw/mingw.h | 9 --------- src/mmap.c | 4 +++- 2 files changed, 3 insertions(+), 10 deletions(-) diff --git a/src/mingw/mingw.h b/src/mingw/mingw.h index 242c8eb98..cd1441073 100644 --- a/src/mingw/mingw.h +++ b/src/mingw/mingw.h @@ -5,15 +5,6 @@ #define _USE_W32_SOCKETS 1 #include -#define ENOTCONN WSAENOTCONN -#define EWOULDBLOCK WSAEWOULDBLOCK -#define ENOBUFS WSAENOBUFS -#define ECONNRESET WSAECONNRESET -#define ESHUTDOWN WSAESHUTDOWN -#define EAFNOSUPPORT WSAEAFNOSUPPORT -#define EPROTONOSUPPORT WSAEPROTONOSUPPORT -#define EINPROGRESS WSAEINPROGRESS -#define EISCONN WSAEISCONN /* winsock doesn't feature poll(), so there is a version implemented * in terms of select() in mingw.c. The following definitions diff --git a/src/mmap.c b/src/mmap.c index bee0dcece..cc5346f18 100644 --- a/src/mmap.c +++ b/src/mmap.c @@ -19,15 +19,17 @@ void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offs count = read(fd, buf, len); - if (count != len) { + if (count != (ssize_t)len) { free (buf); return MAP_FAILED; } return buf; + (void)flags; } int munmap (void *addr, size_t len) { free (addr); return 0; + (void)len; } From 3d24377c2878fc328fb09b67cdfbda529d209417 Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Fri, 7 Apr 2017 20:17:46 +0300 Subject: [PATCH 0564/1435] Now able build by MinGW. All warnings were fixed. (#584) * fix wrong libusb extract command * update libusb to 1.0.21 under windows * fix few -Wformat warnings * add usleep realisation for win32 * Get rid of unused defines in mimgw.h * fix format warning for mingw * Add prefix SEMIXOST_ to semihost defines. Fix redefine warnings of mingw. --- src/gdbserver/gdb-server.c | 2 +- src/gdbserver/semihosting.c | 20 +++++++-------- src/gdbserver/semihosting.h | 50 ++++++++++++++++++------------------- 3 files changed, 36 insertions(+), 36 deletions(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 4d4a9cfce..e2a70e9ea 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -1428,7 +1428,7 @@ int serve(stlink_t *sl, st_state_t *st) { reply = calloc(8 * 16 + 1, 1); for(int i = 0; i < 16; i++) - sprintf(&reply[i * 8], "%08x", htonl(regp.r[i])); + sprintf(&reply[i * 8], "%08x", (uint32_t)htonl(regp.r[i])); break; diff --git a/src/gdbserver/semihosting.c b/src/gdbserver/semihosting.c index 34591d120..312b1517e 100644 --- a/src/gdbserver/semihosting.c +++ b/src/gdbserver/semihosting.c @@ -157,7 +157,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { DLOG("Do semihosting R0=0x%08x R1=0x%08x\n", r0, r1); switch (r0) { - case SYS_OPEN: + case SEMIHOST_SYS_OPEN: { uint32_t args[3]; uint32_t name_address; @@ -220,7 +220,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { free(name); break; } - case SYS_CLOSE: + case SEMIHOST_SYS_CLOSE: { uint32_t args[1]; int fd; @@ -242,7 +242,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { DLOG("Semihosting: return %d\n", *ret); break; } - case SYS_WRITE: + case SEMIHOST_SYS_WRITE: { uint32_t args[3]; uint32_t buffer_address; @@ -300,7 +300,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { free(buffer); break; } - case SYS_READ: + case SEMIHOST_SYS_READ: { uint32_t args[3]; uint32_t buffer_address; @@ -358,13 +358,13 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { free(buffer); break; } - case SYS_ERRNO: + case SEMIHOST_SYS_ERRNO: { *ret = (uint32_t)saved_errno; DLOG("Semihosting: Errno return %d\n", *ret); break; } - case SYS_REMOVE: + case SEMIHOST_SYS_REMOVE: { uint32_t args[2]; uint32_t name_address; @@ -418,7 +418,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { free(name); break; } - case SYS_SEEK: + case SEMIHOST_SYS_SEEK: { uint32_t args[2]; int fd; @@ -446,7 +446,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { DLOG("Semihosting: return %d\n", *ret); break; } - case SYS_WRITEC: + case SEMIHOST_SYS_WRITEC: { uint8_t c; if (mem_read_u8(sl, r1, &c) == 0) { @@ -457,13 +457,13 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { } break; } - case SYS_READC: + case SEMIHOST_SYS_READC: { uint8_t c = getchar(); *ret = c; break; } - case SYS_WRITE0: + case SEMIHOST_SYS_WRITE0: { uint8_t buf[WRITE0_BUFFER_SIZE]; diff --git a/src/gdbserver/semihosting.h b/src/gdbserver/semihosting.h index 392d31f7d..8157df9df 100644 --- a/src/gdbserver/semihosting.h +++ b/src/gdbserver/semihosting.h @@ -3,31 +3,31 @@ #include -#define SYS_OPEN 0x01 -#define SYS_CLOSE 0x02 -#define SYS_WRITEC 0x03 -#define SYS_WRITE0 0x04 -#define SYS_WRITE 0x05 -#define SYS_READ 0x06 -#define SYS_READC 0x07 -#define SYS_ISERROR 0x08 -#define SYS_ISTTY 0x09 -#define SYS_SEEK 0x0A - -#define SYS_FLEN 0x0C -#define SYS_TMPNAM 0x0D -#define SYS_REMOVE 0x0E -#define SYS_RENAME 0x0E -#define SYS_CLOCK 0x10 -#define SYS_TIME 0x11 - -#define SYS_ERRNO 0x13 - -#define SYS_GET_CMD 0x15 -#define SYS_HEAPINFO 0x16 - -#define SYS_ELAPSED 0x30 -#define SYS_TICKFREQ 0x31 +#define SEMIHOST_SYS_OPEN 0x01 +#define SEMIHOST_SYS_CLOSE 0x02 +#define SEMIHOST_SYS_WRITEC 0x03 +#define SEMIHOST_SYS_WRITE0 0x04 +#define SEMIHOST_SYS_WRITE 0x05 +#define SEMIHOST_SYS_READ 0x06 +#define SEMIHOST_SYS_READC 0x07 +#define SEMIHOST_SYS_ISERROR 0x08 +#define SEMIHOST_SYS_ISTTY 0x09 +#define SEMIHOST_SYS_SEEK 0x0A + +#define SEMIHOST_SYS_FLEN 0x0C +#define SEMIHOST_SYS_TMPNAM 0x0D +#define SEMIHOST_SYS_REMOVE 0x0E +#define SEMIHOST_SYS_RENAME 0x0E +#define SEMIHOST_SYS_CLOCK 0x10 +#define SEMIHOST_SYS_TIME 0x11 + +#define SEMIHOST_SYS_ERRNO 0x13 + +#define SEMIHOST_SYS_GET_CMD 0x15 +#define SEMIHOST_SYS_HEAPINFO 0x16 + +#define SEMIHOST_SYS_ELAPSED 0x30 +#define SEMIHOST_SYS_TICKFREQ 0x31 int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret); From cc3a5705099019e01dc59f7907d0c5b1b85878d8 Mon Sep 17 00:00:00 2001 From: Martin Kaiser Date: Fri, 5 May 2017 12:16:38 +0200 Subject: [PATCH 0565/1435] skip GTK detection if we're cross-compiling (#588) It seems that stlink cannot use CMake's standard mechanism to find GTK3. Cmake's GTK3 detection supports only Unix at the moment. Therefore, stlink uses pkg-config to find GTK3. The downside of this is that Cmake's cross-compiler settings are not taken into account. Even if we're cross-compiling, CMake will find a local installation of GTK3 and compilation of the GUI fails. As a simple fix, we skip the GTK3 detection if we're cross-compiling. (In the long run, we should use a more advanced mechanism to find GTK3.) --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 626ba34a6..afa7fdeff 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -20,7 +20,7 @@ include(cmake/CFlags.cmake) # Dependencies ### find_package(LibUSB REQUIRED) -if (NOT APPLE AND NOT WIN32) +if (NOT APPLE AND NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) find_package(PkgConfig) pkg_check_modules(gtk gtk+-3.0) endif () From 5c10d4b83a4703edb492c76f1427c4a4e1a568b1 Mon Sep 17 00:00:00 2001 From: Anton Guda Date: Mon, 8 May 2017 17:00:02 +0300 Subject: [PATCH 0566/1435] Fix compilation warning for GCC 7, fixes #590 --- src/gdbserver/gdb-server.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index e2a70e9ea..223514a3c 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -1640,6 +1640,7 @@ int serve(stlink_t *sl, st_state_t *st) { break; } } + break; default: reply = strdup(""); @@ -1662,6 +1663,7 @@ int serve(stlink_t *sl, st_state_t *st) { case '4' : // remove access watchpoint if(delete_data_watchpoint(sl, addr) < 0) { reply = strdup("E00"); + break; } else { reply = strdup("OK"); break; From 0498621a46e1d2638d4a4c1771fbc84cdb9b4cdf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Mellstr=C3=B6m?= Date: Sun, 14 May 2017 12:42:14 +0200 Subject: [PATCH 0567/1435] Added support for flashing second bank on STM32F10x_XL (#592) --- include/stlink.h | 3 +- src/chipid.c | 2 +- src/common.c | 88 ++++++++++++++++++++++++++++++++++++++++++---- src/flash_loader.c | 12 +++++-- 4 files changed, 95 insertions(+), 10 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index 813086e15..ac0bfe190 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -83,7 +83,8 @@ extern "C" { STLINK_FLASH_TYPE_F0, STLINK_FLASH_TYPE_L0, STLINK_FLASH_TYPE_F4, - STLINK_FLASH_TYPE_L4 + STLINK_FLASH_TYPE_L4, + STLINK_FLASH_TYPE_F1_XL, }; struct stlink_reg { diff --git a/src/chipid.c b/src/chipid.c index 15b2f563a..808a23c52 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -255,7 +255,7 @@ static const struct stlink_chipid_params devices[] = { { .chip_id = STLINK_CHIPID_STM32_F1_XL, .description = "F1 XL-density device", - .flash_type = STLINK_FLASH_TYPE_F0, + .flash_type = STLINK_FLASH_TYPE_F1_XL, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, .sram_size = 0x18000, diff --git a/src/common.c b/src/common.c index 74b96f5da..b2a5db55f 100644 --- a/src/common.c +++ b/src/common.c @@ -35,6 +35,13 @@ #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) +// STM32F10x_XL has two flash memory banks with separate registers to control the second bank. +#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) +#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) +#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) +#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) +#define FLASH_BANK2_START_ADDR 0x08080000 + // For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... #define FLASH_RDPTR_KEY 0x00a5 #define FLASH_KEY1 0x45670123 @@ -189,6 +196,15 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { return res; } +static inline uint32_t read_flash_cr2(stlink_t *sl) { + uint32_t res; + stlink_read_debug32(sl, FLASH_CR2, &res); +#if DEBUG_FLASH + fprintf(stdout, "CR2:0x%x\n", res); +#endif + return res; +} + static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ uint32_t cr_lock_shift, cr = read_flash_cr(sl); @@ -219,6 +235,11 @@ static void unlock_flash(stlink_t *sl) { stlink_write_debug32(sl, key_reg, FLASH_KEY1); stlink_write_debug32(sl, key_reg, FLASH_KEY2); + + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + stlink_write_debug32(sl, FLASH_KEYR2, FLASH_KEY1); + stlink_write_debug32(sl, FLASH_KEYR2, FLASH_KEY2); + } } static int unlock_flash_if(stlink_t *sl) { @@ -251,6 +272,11 @@ static void lock_flash(stlink_t *sl) { n = read_flash_cr(sl) | (1 << cr_lock_shift); stlink_write_debug32(sl, cr_reg, n); + + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + n = read_flash_cr2(sl) | (1 << cr_lock_shift); + stlink_write_debug32(sl, FLASH_CR2, n); + } } @@ -293,6 +319,11 @@ static void set_flash_cr_per(stlink_t *sl) { stlink_write_debug32(sl, FLASH_CR, n); } +static void set_flash_cr2_per(stlink_t *sl) { + const uint32_t n = 1 << FLASH_CR_PER; + stlink_write_debug32(sl, FLASH_CR2, n); +} + static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_CR, n); @@ -367,6 +398,14 @@ static void set_flash_cr_strt(stlink_t *sl) { stlink_write_debug32(sl, cr_reg, val); } +static void set_flash_cr2_strt(stlink_t *sl) { + uint32_t val; + + stlink_read_debug32(sl, FLASH_CR2, &val); + val |= 1 << FLASH_CR_STRT; + stlink_write_debug32(sl, FLASH_CR2, val); +} + static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res, sr_reg; @@ -382,8 +421,15 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { return res; } +static inline uint32_t read_flash_sr2(stlink_t *sl) { + uint32_t res; + stlink_read_debug32(sl, FLASH_SR2, &res); + return res; +} + static inline unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; + unsigned int res; if (sl->flash_type == STLINK_FLASH_TYPE_F4) sr_busy_shift = FLASH_F4_SR_BSY; @@ -392,7 +438,13 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { else sr_busy_shift = FLASH_SR_BSY; - return read_flash_sr(sl) & (1 << sr_busy_shift); + res = read_flash_sr(sl) & (1 << sr_busy_shift); + + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + res |= read_flash_sr2(sl) & (1 << sr_busy_shift); + } + + return res; } static void wait_flash_busy(stlink_t *sl) { @@ -435,6 +487,10 @@ static inline void write_flash_ar(stlink_t *sl, uint32_t n) { stlink_write_debug32(sl, FLASH_AR, n); } +static inline void write_flash_ar2(stlink_t *sl, uint32_t n) { + stlink_write_debug32(sl, FLASH_AR2, n); +} + static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) { uint32_t x = read_flash_cr(sl); x &= ~(0x03 << 8); @@ -1531,7 +1587,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr < FLASH_BANK2_START_ADDR))) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1550,6 +1606,27 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) /* wait for completion */ wait_flash_busy(sl); + /* relock the flash */ + lock_flash(sl); + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr >= FLASH_BANK2_START_ADDR)) { + /* wait for ongoing op to finish */ + wait_flash_busy(sl); + + /* unlock if locked */ + unlock_flash_if(sl); + + /* set the page erase bit */ + set_flash_cr2_per(sl); + + /* select the page to erase */ + write_flash_ar2(sl, flashaddr); + + /* start erase operation, reset by hw with bsy bit */ + set_flash_cr2_strt(sl); + + /* wait for completion */ + wait_flash_busy(sl); + /* relock the flash */ lock_flash(sl); } else { @@ -1908,8 +1985,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_F0) { - ILOG("Starting Flash write for VL/F0/F3 core id\n"); + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + ILOG("Starting Flash write for VL/F0/F3/F1_XL core id\n"); /* flash loader initialization */ if (stlink_flash_loader_init(sl, &fl) == -1) { ELOG("stlink_flash_loader_init() == -1\n"); @@ -1924,8 +2001,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t /* unlock and set programming mode */ unlock_flash_if(sl); - set_flash_cr_pg(sl); - DLOG("Finished setting flash cr pg, running loader!\n"); + DLOG("Finished unlocking flash, running loader!\n"); if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t) off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); return -1; diff --git a/src/flash_loader.c b/src/flash_loader.c index ed53a0c6b..96084ab27 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -4,6 +4,9 @@ #include #include +#define FLASH_REGS_BANK2_OFS 0x40 +#define FLASH_BANK2_START_ADDR 0x08080000 + /* from openocd, contrib/loaders/flash/stm32.s */ static const uint8_t loader_code_stm32vl[] = { 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */ @@ -325,6 +328,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe struct stlink_reg rr; int i = 0; size_t count = 0; + uint32_t flash_base = 0; DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); // FIXME This can never return -1 @@ -334,7 +338,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe return -1; } - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; @@ -348,11 +352,15 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe ++count; } + if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { + flash_base = FLASH_REGS_BANK2_OFS; + } + /* setup core */ stlink_write_reg(sl, fl->buf_addr, 0); /* source */ stlink_write_reg(sl, target, 1); /* target */ stlink_write_reg(sl, (uint32_t) count, 2); /* count */ - stlink_write_reg(sl, 0, 3); /* flash bank 0 (input), only used on F0, but armless fopr others */ + stlink_write_reg(sl, flash_base, 3); /* flash register base, only used on VL/F1_XL, but harmless for others */ stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ /* run loader */ From 55c057296ad15fa6de9909206098bd4eed8f6311 Mon Sep 17 00:00:00 2001 From: Sai Kalidindi Date: Thu, 18 May 2017 04:10:22 -0700 Subject: [PATCH 0568/1435] fix flashing to 'f0 device' targets (#595) Fixes #594. Pull request #592 (0498621) accidentally deleted the call to `set_flash_cr_pg`. --- src/common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/common.c b/src/common.c index b2a5db55f..21285bbfb 100644 --- a/src/common.c +++ b/src/common.c @@ -2001,6 +2001,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t /* unlock and set programming mode */ unlock_flash_if(sl); + if (sl->flash_type != STLINK_FLASH_TYPE_F1_XL) { + set_flash_cr_pg(sl); + } DLOG("Finished unlocking flash, running loader!\n"); if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t) off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); From 79d91786f7b3fc5b461246bf5a6be3626bb06572 Mon Sep 17 00:00:00 2001 From: orinem Date: Fri, 16 Jun 2017 23:05:47 -0700 Subject: [PATCH 0569/1435] Stop the sulk with GPL2016 on Windows (#602) * Fixes for VS2017. * Added a getopt implementation. * Added a unistd.h. * Corrected closing of sockets for Windows versions. * Fixed gdbserver CMakeLists.txt to play nice with VS2017. * Fixed include of getopt.h and unistd.h for WIN32. * Added a unistd.h. * Corrected closing of sockets for Windows versions. * Fixed gdbserver CMakeLists.txt to play nice with VS2017. * Override /MD to /MT for MSVC to match libusb's builds. * MSVC settings should be if (MSVC). * Don't busy-wait for long periods in usleep(). * Dynamic link to MSVC libusb binaries. * Added Visual Studio section to compiling.md. * Added -D_CRT_NONSTDC_NO_WARNINGS to MSVC flags. * Prevented some more warnings under MSVC. --- CMakeLists.txt | 7 ++ cmake/c_flag_overrides.cmake | 7 ++ cmake/modules/FindLibUSB.cmake | 4 +- doc/compiling.md | 31 +++++ include/stlink/sg.h | 8 ++ include/stlink/tools/flash.h | 2 +- src/common.c | 3 + src/gdbserver/CMakeLists.txt | 21 +++- src/gdbserver/gdb-remote.c | 2 +- src/gdbserver/gdb-server.c | 32 +++-- src/getopt/LICENSE.txt | 24 ++++ src/getopt/README.md | 21 ++++ src/getopt/getopt.c | 206 +++++++++++++++++++++++++++++++++ src/getopt/getopt.h | 38 ++++++ src/mingw/mingw.c | 28 ++++- src/mingw/mingw.h | 21 +++- src/usb.c | 10 ++ src/win32/unistd.h | 60 ++++++++++ tests/flash.c | 21 ++-- tests/sg.c | 4 + 20 files changed, 515 insertions(+), 35 deletions(-) create mode 100644 cmake/c_flag_overrides.cmake create mode 100644 src/getopt/LICENSE.txt create mode 100644 src/getopt/README.md create mode 100644 src/getopt/getopt.c create mode 100644 src/getopt/getopt.h create mode 100644 src/win32/unistd.h diff --git a/CMakeLists.txt b/CMakeLists.txt index afa7fdeff..d0660cf05 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,4 +1,5 @@ cmake_minimum_required(VERSION 2.8.7) +set(CMAKE_USER_MAKE_RULES_OVERRIDE cmake/c_flag_overrides.cmake) project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics Stlink Tools") set(STLINK_UDEV_RULES_DIR "/etc/udev/rules.d" CACHE PATH "Udev rules directory") @@ -71,6 +72,12 @@ include_directories(${LIBUSB_INCLUDE_DIR}) include_directories(include) include_directories(${PROJECT_BINARY_DIR}/include) include_directories(src/mingw) +if (MSVC) + include_directories(src/win32) + include_directories(src/getopt) + # Use string.h rather than strings.h and disable annoying warnings + add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) +endif () ### # Shared library diff --git a/cmake/c_flag_overrides.cmake b/cmake/c_flag_overrides.cmake new file mode 100644 index 000000000..663e08175 --- /dev/null +++ b/cmake/c_flag_overrides.cmake @@ -0,0 +1,7 @@ +if(MSVC) + message(STATUS "MSVC C Flags override to /MT") + set(CMAKE_C_FLAGS_DEBUG_INIT "/D_DEBUG /MTd /Zi /Ob0 /Od /RTC1") + set(CMAKE_C_FLAGS_MINSIZEREL_INIT "/MT /O1 /Ob1 /D NDEBUG") + set(CMAKE_C_FLAGS_RELEASE_INIT "/MT /O2 /Ob2 /D NDEBUG") + set(CMAKE_C_FLAGS_RELWITHDEBINFO_INIT "/MT /Zi /O2 /Ob1 /D NDEBUG") +endif() diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index b106018d2..844f3dc54 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -67,10 +67,10 @@ if (MSYS OR MINGW) elseif(CMAKE_VS_PLATFORM_NAME) if (CMAKE_SIZEOF_VOID_P EQUAL 8) find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS64/static) + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS64/dll) else () find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS32/static) + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS32/dll) endif () else() find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} diff --git a/doc/compiling.md b/doc/compiling.md index 296d64b17..3518d1079 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -139,3 +139,34 @@ Check and execute (in the script folder) `\scripts\mingw64-build.bat NOTE: when installing different toolchains make sure you edit the path in the `mingw64-build.bat` the build script uses currently `C:\Program Files\mingw-w64\x86_64-5.3.0-win32-sjlj-rt_v4-rev0\mingw64\bin` + +## Windows (Visual Studio) + +### Prerequisites + +* 7Zip +* CMake (tested with version 3.9.0-rc2) +* Visual Studio 2017 Community (other versions will likely work but are untested; the Community edition is free for open source +development) + +### Installation + +1. Install 7Zip from +2. Install CMake from +3. Git clone or download stlink sourcefiles zip + +### Building + +These instructions are for a 32bit version. + +In a command prompt, change directory to the folder where the stlink files were cloned (or unzipped). +Make sure the build folder exists (`mkdir build` if not). +From the build folder, run cmake (`cd build; cmake ..`). + +This will create a solution (stlink.sln) in the build folder. Open it in Visual Studio, select the Solution Configuration (Debug or +Release) and build the solution normally (F7). + +NOTES: This solution will link to the dll version of libusb-1.0. To debug or run the executable, the dll version of libusb-1.0 must +be either on the path, or in the same folder as the executable. It can be copied from here: +`build\3thparty\libusb-1.0.21\MS32\dll\libusb-1.0.dll`. + diff --git a/include/stlink/sg.h b/include/stlink/sg.h index 057f996a2..e521ba217 100644 --- a/include/stlink/sg.h +++ b/include/stlink/sg.h @@ -8,7 +8,15 @@ #ifndef STLINK_SG_H #define STLINK_SG_H +#if defined(_MSC_VER) +#pragma warning(push) +#pragma warning(disable: 4200 4255 4668 4820) #include +#pragma warning(pop) +#else +#include +#endif + #include "stlink.h" #ifdef __cplusplus diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index 35b3a4251..3d1375aa2 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -23,7 +23,7 @@ struct flash_opts size_t flash_size; /* --flash=n[k][m] */ }; -#define FLASH_OPTS_INITIALIZER {0, NULL, {}, NULL, 0, 0, 0, 0, 0, 0 } +#define FLASH_OPTS_INITIALIZER {0, NULL, { 0 }, NULL, 0, 0, 0, 0, 0, 0 } int flash_get_opts(struct flash_opts* o, int ac, char** av); diff --git a/src/common.c b/src/common.c index 21285bbfb..2297eee47 100644 --- a/src/common.c +++ b/src/common.c @@ -18,6 +18,9 @@ #ifndef _WIN32 #define O_BINARY 0 //! @todo get rid of this OH MY (@xor-gate) #endif +#ifdef _MSC_VER +#define __attribute__(x) +#endif /* todo: stm32l15xxx flash memory, pm0062 manual */ diff --git a/src/gdbserver/CMakeLists.txt b/src/gdbserver/CMakeLists.txt index a41890c70..2393690ce 100644 --- a/src/gdbserver/CMakeLists.txt +++ b/src/gdbserver/CMakeLists.txt @@ -1,9 +1,18 @@ -add_executable(st-util gdb-remote.c - gdb-remote.h - gdb-server.c - gdb-server.h - semihosting.c - semihosting.h) +set(STUTIL_SOURCE + gdb-remote.c + gdb-remote.h + gdb-server.c + gdb-server.h + semihosting.c + semihosting.h) + +if (MSVC) + # We need a getopt from somewhere... + set(STUTIL_SOURCE "${STUTIL_SOURCE};../getopt/getopt.c") +endif() + +add_executable(st-util ${STUTIL_SOURCE}) + if (WIN32 OR APPLE) target_link_libraries(st-util ${STLINK_LIB_STATIC}) else() diff --git a/src/gdbserver/gdb-remote.c b/src/gdbserver/gdb-remote.c index a5d3f4c03..83c5e093a 100644 --- a/src/gdbserver/gdb-remote.c +++ b/src/gdbserver/gdb-remote.c @@ -8,7 +8,7 @@ #include #include #include -#ifdef __MINGW32__ +#if defined(__MINGW32__) || defined(_MSC_VER) #include #else #include diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 223514a3c..d7da544fa 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -10,7 +10,11 @@ #include #include #include -#ifdef __MINGW32__ +#if defined(_MSC_VER) +#include +#define __attribute__(x) +#endif +#if defined(__MINGW32__) || defined(_MSC_VER) #include #else #include @@ -239,7 +243,7 @@ int main(int argc, char** argv) { sl->verbose=0; current_memory_map = make_memory_map(sl); -#ifdef __MINGW32__ +#if defined(__MINGW32__) || defined(_MSC_VER) WSADATA wsadata; if (WSAStartup(MAKEWORD(2,2),&wsadata) !=0 ) { goto winsock_error; @@ -260,7 +264,7 @@ int main(int argc, char** argv) { stlink_run(sl); } while (state.persistent); -#ifdef __MINGW32__ +#if defined(__MINGW32__) || defined(_MSC_VER) winsock_error: WSACleanup(); #endif @@ -1061,7 +1065,11 @@ int serve(stlink_t *sl, st_state_t *st) { return 1; } - close(sock); +#if defined(__MINGW32__) || defined(_MSC_VER) + win32_close_socket(sock); +#else + close(sock); +#endif stlink_force_debug(sl); if (st->reset) { @@ -1084,8 +1092,8 @@ int serve(stlink_t *sl, st_state_t *st) { int status = gdb_recv_packet(client, &packet); if(status < 0) { ELOG("cannot recv: %d\n", status); -#ifdef __MINGW32__ - win32_close_socket(sock); +#if defined(__MINGW32__) || defined(_MSC_VER) + win32_close_socket(client); #endif return 1; } @@ -1337,8 +1345,8 @@ int serve(stlink_t *sl, st_state_t *st) { status = gdb_check_for_interrupt(client); if(status < 0) { ELOG("cannot check for int: %d\n", status); -#ifdef __MINGW32__ - win32_close_socket(sock); +#if defined(__MINGW32__) || defined(_MSC_VER) + win32_close_socket(client); #endif return 1; } @@ -1739,8 +1747,8 @@ int serve(stlink_t *sl, st_state_t *st) { ELOG("cannot send: %d\n", result); free(reply); free(packet); -#ifdef __MINGW32__ - win32_close_socket(sock); +#if defined(__MINGW32__) || defined(_MSC_VER) + win32_close_socket(client); #endif return 1; } @@ -1751,8 +1759,8 @@ int serve(stlink_t *sl, st_state_t *st) { free(packet); } -#ifdef __MINGW32__ - win32_close_socket(sock); +#if defined(__MINGW32__) || defined(_MSC_VER) + win32_close_socket(client); #endif return 0; diff --git a/src/getopt/LICENSE.txt b/src/getopt/LICENSE.txt new file mode 100644 index 000000000..340303a96 --- /dev/null +++ b/src/getopt/LICENSE.txt @@ -0,0 +1,24 @@ +Copyright (c) 2012, Kim Gräsman +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of Kim Gräsman nor the + names of contributors may be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL KIM GRÄSMAN BE LIABLE FOR ANY +DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/src/getopt/README.md b/src/getopt/README.md new file mode 100644 index 000000000..9bf81fa73 --- /dev/null +++ b/src/getopt/README.md @@ -0,0 +1,21 @@ +getopt_port +=========== + +[Kim Gräsman](http://grundlig.wordpress.com) +[@kimgr](http://twitter.com/kimgr) + +An original implementation of `getopt` and `getopt_long` with limited GNU extensions. Provided under the BSD license, to allow non-GPL projects to use `getopt`-style command-line parsing. + +So far only built with Visual C++, but has no inherently non-portable constructs. + +Intended to be embedded into your code tree -- `getopt.h` and `getopt.c` are self-contained and should work in any context. + +Comes with a reasonable unit test suite. + +See also: + + * [Full Win32 getopt port](http://www.codeproject.com/Articles/157001/Full-getopt-Port-for-Unicode-and-Multibyte-Microso) -- LGPL licensed. + * [XGetOpt](http://www.codeproject.com/Articles/1940/XGetopt-A-Unix-compatible-getopt-for-MFC-and-Win32) -- No `getopt_long` support. + * [Free Getopt](https://sourceforge.net/projects/freegetopt/) -- No `getopt_long` support. + +For license terms, see LICENSE.txt. \ No newline at end of file diff --git a/src/getopt/getopt.c b/src/getopt/getopt.c new file mode 100644 index 000000000..72dce14d6 --- /dev/null +++ b/src/getopt/getopt.c @@ -0,0 +1,206 @@ +#include "getopt.h" + +#include +#include + +#if !defined(_MSC_VER) +const int no_argument = 0; +const int required_argument = 1; +const int optional_argument = 2; +#endif + +char* optarg; +int optopt; +/* The variable optind [...] shall be initialized to 1 by the system. */ +int optind = 1; +int opterr; + +static char* optcursor = NULL; + +/* Implemented based on [1] and [2] for optional arguments. + optopt is handled FreeBSD-style, per [3]. + Other GNU and FreeBSD extensions are purely accidental. + +[1] http://pubs.opengroup.org/onlinepubs/000095399/functions/getopt.html +[2] http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html +[3] http://www.freebsd.org/cgi/man.cgi?query=getopt&sektion=3&manpath=FreeBSD+9.0-RELEASE +*/ +int getopt(int argc, char* const argv[], const char* optstring) { + int optchar = -1; + const char* optdecl = NULL; + + optarg = NULL; + opterr = 0; + optopt = 0; + + /* Unspecified, but we need it to avoid overrunning the argv bounds. */ + if (optind >= argc) + goto no_more_optchars; + + /* If, when getopt() is called argv[optind] is a null pointer, getopt() + shall return -1 without changing optind. */ + if (argv[optind] == NULL) + goto no_more_optchars; + + /* If, when getopt() is called *argv[optind] is not the character '-', + getopt() shall return -1 without changing optind. */ + if (*argv[optind] != '-') + goto no_more_optchars; + + /* If, when getopt() is called argv[optind] points to the string "-", + getopt() shall return -1 without changing optind. */ + if (strcmp(argv[optind], "-") == 0) + goto no_more_optchars; + + /* If, when getopt() is called argv[optind] points to the string "--", + getopt() shall return -1 after incrementing optind. */ + if (strcmp(argv[optind], "--") == 0) { + ++optind; + goto no_more_optchars; + } + + if (optcursor == NULL || *optcursor == '\0') + optcursor = argv[optind] + 1; + + optchar = *optcursor; + + /* FreeBSD: The variable optopt saves the last known option character + returned by getopt(). */ + optopt = optchar; + + /* The getopt() function shall return the next option character (if one is + found) from argv that matches a character in optstring, if there is + one that matches. */ + optdecl = strchr(optstring, optchar); + if (optdecl) { + /* [I]f a character is followed by a colon, the option takes an + argument. */ + if (optdecl[1] == ':') { + optarg = ++optcursor; + if (*optarg == '\0') { + /* GNU extension: Two colons mean an option takes an + optional arg; if there is text in the current argv-element + (i.e., in the same word as the option name itself, for example, + "-oarg"), then it is returned in optarg, otherwise optarg is set + to zero. */ + if (optdecl[2] != ':') { + /* If the option was the last character in the string pointed to by + an element of argv, then optarg shall contain the next element + of argv, and optind shall be incremented by 2. If the resulting + value of optind is greater than argc, this indicates a missing + option-argument, and getopt() shall return an error indication. + + Otherwise, optarg shall point to the string following the + option character in that element of argv, and optind shall be + incremented by 1. + */ + if (++optind < argc) { + optarg = argv[optind]; + } else { + /* If it detects a missing option-argument, it shall return the + colon character ( ':' ) if the first character of optstring + was a colon, or a question-mark character ( '?' ) otherwise. + */ + optarg = NULL; + optchar = (optstring[0] == ':') ? ':' : '?'; + } + } else { + optarg = NULL; + } + } + + optcursor = NULL; + } + } else { + /* If getopt() encounters an option character that is not contained in + optstring, it shall return the question-mark ( '?' ) character. */ + optchar = '?'; + } + + if (optcursor == NULL || *++optcursor == '\0') + ++optind; + + return optchar; + +no_more_optchars: + optcursor = NULL; + return -1; +} + +/* Implementation based on [1]. + +[1] http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html +*/ +int getopt_long(int argc, char* const argv[], const char* optstring, + const struct option* longopts, int* longindex) { + const struct option* o = longopts; + const struct option* match = NULL; + int num_matches = 0; + size_t argument_name_length = 0; + const char* current_argument = NULL; + int retval = -1; + + optarg = NULL; + optopt = 0; + + if (optind >= argc) + return -1; + + if (strlen(argv[optind]) < 3 || strncmp(argv[optind], "--", 2) != 0) + return getopt(argc, argv, optstring); + + /* It's an option; starts with -- and is longer than two chars. */ + current_argument = argv[optind] + 2; + argument_name_length = strcspn(current_argument, "="); + for (; o->name; ++o) { + if (strncmp(o->name, current_argument, argument_name_length) == 0) { + match = o; + ++num_matches; + } + } + + if (num_matches == 1) { + /* If longindex is not NULL, it points to a variable which is set to the + index of the long option relative to longopts. */ + if (longindex) + *longindex = (match - longopts); + + /* If flag is NULL, then getopt_long() shall return val. + Otherwise, getopt_long() returns 0, and flag shall point to a variable + which shall be set to val if the option is found, but left unchanged if + the option is not found. */ + if (match->flag) + *(match->flag) = match->val; + + retval = match->flag ? 0 : match->val; + + if (match->has_arg != no_argument) { + optarg = strchr(argv[optind], '='); + if (optarg != NULL) + ++optarg; + + if (match->has_arg == required_argument) { + /* Only scan the next argv for required arguments. Behavior is not + specified, but has been observed with Ubuntu and Mac OSX. */ + if (optarg == NULL && ++optind < argc) { + optarg = argv[optind]; + } + + if (optarg == NULL) + retval = ':'; + } + } else if (strchr(argv[optind], '=')) { + /* An argument was provided to a non-argument option. + I haven't seen this specified explicitly, but both GNU and BSD-based + implementations show this behavior. + */ + retval = '?'; + } + } else { + /* Unknown option or ambiguous match. */ + retval = '?'; + } + + ++optind; + return retval; +} diff --git a/src/getopt/getopt.h b/src/getopt/getopt.h new file mode 100644 index 000000000..bc189b9d4 --- /dev/null +++ b/src/getopt/getopt.h @@ -0,0 +1,38 @@ +#ifndef INCLUDED_GETOPT_PORT_H +#define INCLUDED_GETOPT_PORT_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#if defined(_MSC_VER) +// These may be used to initialize structures and it fails with MSVC +#define no_argument 0 +#define required_argument 1 +#define optional_argument 2 +#else +extern const int no_argument; +extern const int required_argument; +extern const int optional_argument; +#endif + +extern char* optarg; +extern int optind, opterr, optopt; + +struct option { + const char* name; + int has_arg; + int* flag; + int val; +}; + +int getopt(int argc, char* const argv[], const char* optstring); + +int getopt_long(int argc, char* const argv[], + const char* optstring, const struct option* longopts, int* longindex); + +#if defined(__cplusplus) +} +#endif + +#endif // INCLUDED_GETOPT_PORT_H diff --git a/src/mingw/mingw.c b/src/mingw/mingw.c index ee0515972..b342e7db2 100644 --- a/src/mingw/mingw.c +++ b/src/mingw/mingw.c @@ -1,4 +1,4 @@ -#ifdef __MINGW32__ +#if defined(__MINGW32__) || defined(_MSC_VER) #include "mingw.h" @@ -18,6 +18,9 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) unsigned int i, rc; /* Set up the file-descriptor sets in ifds, ofds and efds. */ +#ifdef _MSC_VER +#pragma warning(disable: 4548) +#endif FD_ZERO(&ifds); FD_ZERO(&ofds); FD_ZERO(&efds); @@ -33,6 +36,9 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) } FD_SET(fds[i].fd, &efds); } +#ifdef _MSC_VER +#pragma warning(default: 4548) +#endif /* Set up the timeval structure for the timeout parameter */ if(timo < 0) { @@ -143,7 +149,7 @@ win32_accept(SOCKET fd, struct sockaddr *addr, socklen_t *addr_len) SOCKET newfd = accept(fd, addr, addr_len); if(newfd == INVALID_SOCKET) { set_socket_errno(WSAGetLastError()); - newfd = -1; + newfd = (SOCKET)-1; } return newfd; } @@ -267,6 +273,24 @@ char *win32_strsep (char **stringp, const char *delim) void usleep(DWORD waitTime) { +#ifdef _MSC_VER + if (waitTime >= 1000) + { + // Don't do long busy-waits. + // However much it seems like the QPC code would be more accurate, + // you can and probably will lose your time slice at any point during the wait, + // so we might as well voluntarily give up the CPU with a WaitForSingleObject. + HANDLE timer; + LARGE_INTEGER dueTime; + dueTime.QuadPart = -10 * (LONGLONG)waitTime; + + timer = CreateWaitableTimer(NULL, TRUE, NULL); + SetWaitableTimer(timer, &dueTime, 0, NULL, NULL, 0); + WaitForSingleObject(timer, INFINITE); + CloseHandle(timer); + return; + } +#endif LARGE_INTEGER perf_cnt, start, now; QueryPerformanceFrequency(&perf_cnt); diff --git a/src/mingw/mingw.h b/src/mingw/mingw.h index cd1441073..4b5cf5380 100644 --- a/src/mingw/mingw.h +++ b/src/mingw/mingw.h @@ -1,16 +1,28 @@ -#ifdef __MINGW32__ - -#include +#if defined(__MINGW32__) || defined(_MSC_VER) #define _USE_W32_SOCKETS 1 -#include +#if defined(_MSC_VER) +#pragma warning(push) +#pragma warning(disable: 4255 4668 4820) +#endif + +#include +#include +#pragma comment(lib, "ws2_32.lib") +#include + +#if defined(_MSC_VER) +#pragma warning(pop) +#endif /* winsock doesn't feature poll(), so there is a version implemented * in terms of select() in mingw.c. The following definitions * are copied from linux man pages. A poll() macro is defined to * call the version in mingw.c. */ +#if !defined(_WIN32_WINNT) || (_WIN32_WINNT < 0x0600) + #define POLLIN 0x0001 /* There is data to read */ #define POLLPRI 0x0002 /* There is urgent data to read */ #define POLLOUT 0x0004 /* Writing now will not block */ @@ -22,6 +34,7 @@ struct pollfd { short events; /* requested events */ short revents; /* returned events */ }; +#endif #define poll(x, y, z) win32_poll(x, y, z) /* These wrappers do nothing special except set the global errno variable if diff --git a/src/usb.c b/src/usb.c index 03ac1ab3c..299de8740 100644 --- a/src/usb.c +++ b/src/usb.c @@ -2,9 +2,19 @@ #include #include #include +#if !defined(_MSC_VER) #include +#endif #include +#if defined(_MSC_VER) +#include +#pragma warning(push) +#pragma warning(disable: 4200 4255 4668 4820) #include +#pragma warning(pop) +#else +#include +#endif #include #include diff --git a/src/win32/unistd.h b/src/win32/unistd.h new file mode 100644 index 000000000..0b175fc07 --- /dev/null +++ b/src/win32/unistd.h @@ -0,0 +1,60 @@ +#ifndef _UNISTD_H +#define _UNISTD_H 1 + +/* This file intended to serve as a drop-in replacement for + * unistd.h on Windows + * Please add functionality as neeeded + */ + +#include +#include +#if defined(_MSC_VER) +#pragma warning(push) +#pragma warning(disable: 4820) +#endif +#include +#if defined(_MSC_VER) +#pragma warning(pop) +#endif +#include /* getopt at: https://gist.github.com/ashelly/7776712 */ +#include /* for getpid() and the exec..() family */ +#include /* for _getcwd() and _chdir() */ + +#define srandom srand +#define random rand + +/* Values for the second argument to access. + These may be OR'd together. */ +#define R_OK 4 /* Test for read permission. */ +#define W_OK 2 /* Test for write permission. */ +//#define X_OK 1 /* execute permission - unsupported in windows*/ +#define F_OK 0 /* Test for existence. */ + +#define access _access +#define dup2 _dup2 +#define execve _execve +#define ftruncate _chsize +#define unlink _unlink +#define fileno _fileno +#define getcwd _getcwd +#define chdir _chdir +#define isatty _isatty +#define lseek _lseek +/* read, write, and close are NOT being #defined here, because while there are file handle specific versions for Windows, they probably don't work for sockets. You need to look at your app and consider whether to call e.g. closesocket(). */ + +#define ssize_t int + +#define STDIN_FILENO 0 +#define STDOUT_FILENO 1 +#define STDERR_FILENO 2 +/* should be in some equivalent to */ +typedef __int8 int8_t; +typedef __int16 int16_t; +typedef __int32 int32_t; +typedef __int64 int64_t; +typedef unsigned __int8 uint8_t; +typedef unsigned __int16 uint16_t; +typedef unsigned __int32 uint32_t; +typedef unsigned __int64 uint64_t; + +#endif /* unistd.h */ diff --git a/tests/flash.c b/tests/flash.c index fd55fdfc1..6c8b8ed9b 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -4,6 +4,9 @@ #include #include +#if defined(_MSC_VER) +#include +#endif struct Test { const char * cmd_line; @@ -26,7 +29,11 @@ static bool execute_test(const struct Test * test) { char* av[32]; // parse (tokenize) the test command line +#if defined(_MSC_VER) + char *cmd_line = alloca(strlen(test->cmd_line)); +#else char cmd_line[strlen(test->cmd_line)]; +#endif strcpy(cmd_line, test->cmd_line); for(char * tok = strtok(cmd_line, " "); tok; tok = strtok(NULL, " ")) { @@ -62,26 +69,26 @@ static bool execute_test(const struct Test * test) { static struct Test tests[] = { { "", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset read /dev/sg0 test.bin 0x80000000 0x1000", 0, - { .cmd = FLASH_CMD_READ, .devname = "/dev/sg0", .serial = {}, .filename = "test.bin", + { .cmd = FLASH_CMD_READ, .devname = "/dev/sg0", .serial = { 0 }, .filename = "test.bin", .addr = 0x80000000, .size = 0x1000, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, { "--debug --reset write /dev/sg0 test.bin 0x80000000", 0, - { .cmd = FLASH_CMD_WRITE, .devname = "/dev/sg0", .serial = {}, .filename = "test.bin", + { .cmd = FLASH_CMD_WRITE, .devname = "/dev/sg0", .serial = { 0 }, .filename = "test.bin", .addr = 0x80000000, .size = 0, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, { "--serial A1020304 /dev/sg0 erase", -1, FLASH_OPTS_INITIALIZER }, { "/dev/sg0 erase", 0, - { .cmd = FLASH_CMD_ERASE, .devname = "/dev/sg0", .serial = {}, .filename = NULL, + { .cmd = FLASH_CMD_ERASE, .devname = "/dev/sg0", .serial = { 0 }, .filename = NULL, .addr = 0, .size = 0, .reset = 0, .log_level = STND_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, { "--debug --reset read test.bin 0x80000000 0x1000", 0, - { .cmd = FLASH_CMD_READ, .devname = NULL, .serial = {}, .filename = "test.bin", + { .cmd = FLASH_CMD_READ, .devname = NULL, .serial = { 0 }, .filename = "test.bin", .addr = 0x80000000, .size = 0x1000, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, { "--debug --reset write test.bin 0x80000000", 0, - { .cmd = FLASH_CMD_WRITE, .devname = NULL, .serial = {}, .filename = "test.bin", + { .cmd = FLASH_CMD_WRITE, .devname = NULL, .serial = { 0 }, .filename = "test.bin", .addr = 0x80000000, .size = 0, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, { "erase", 0, - { .cmd = FLASH_CMD_ERASE, .devname = NULL, .serial = {}, .filename = NULL, + { .cmd = FLASH_CMD_ERASE, .devname = NULL, .serial = { 0 }, .filename = NULL, .addr = 0, .size = 0, .reset = 0, .log_level = STND_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, { "--debug --reset --format=ihex write test.hex", 0, - { .cmd = FLASH_CMD_WRITE, .devname = NULL, .serial = {}, .filename = "test.hex", + { .cmd = FLASH_CMD_WRITE, .devname = NULL, .serial = { 0 }, .filename = "test.hex", .addr = 0, .size = 0, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_IHEX } }, { "--debug --reset --format=binary write test.hex", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset --format=ihex write test.hex 0x80000000", -1, FLASH_OPTS_INITIALIZER }, diff --git a/tests/sg.c b/tests/sg.c index 5426b6ff3..a014717d7 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -9,6 +9,10 @@ #include #include +#if defined(_MSC_VER) +#define __attribute__(x) +#endif + static void __attribute__((unused)) mark_buf(stlink_t *sl) { memset(sl->q_buf, 0, sizeof(sl->q_buf)); sl->q_buf[0] = 0xaa; From 438344a0da777da79d29925fe00181e8fec209fa Mon Sep 17 00:00:00 2001 From: kilroy42 Date: Sat, 17 Jun 2017 23:16:38 +0200 Subject: [PATCH 0570/1435] Fix wrong counting logline when flashing (#605) --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 2297eee47..e40f2d42a 100644 --- a/src/common.c +++ b/src/common.c @@ -2016,7 +2016,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t if (sl->verbose >= 1) { /* show progress. writing procedure is slow and previous errors are misleading */ - fprintf(stdout, "\r%3u/%lu pages written", write_block_count++, (unsigned long)(len/sl->flash_pgsz)); + fprintf(stdout, "\r%3u/%lu pages written", ++write_block_count, (unsigned long)((len+sl->flash_pgsz-1)/sl->flash_pgsz)); fflush(stdout); } } From dc8eb3e739c334440f340b39db46c8d530daa1e0 Mon Sep 17 00:00:00 2001 From: "Zhang, Chi" Date: Mon, 26 Jun 2017 16:57:14 -0500 Subject: [PATCH 0571/1435] Fix gitignore and add support for STM32L452 (#608) * update gitignore for debian * add/update support for L43x/44x/45x/46x, partially thanks to @vatsaltrivedi86, should close texane/stlink#603 --- .gitignore | 1 + debian/.gitignore | 10 ++++++++++ doc/tested-boards.md | 3 ++- include/stlink/chipid.h | 5 +++++ src/chipid.c | 24 +++++++++++++++++++----- src/flash_loader.c | 3 ++- 6 files changed, 39 insertions(+), 7 deletions(-) create mode 100644 debian/.gitignore diff --git a/.gitignore b/.gitignore index 378eac25d..89cda6de8 100644 --- a/.gitignore +++ b/.gitignore @@ -1 +1,2 @@ build +obj-* diff --git a/debian/.gitignore b/debian/.gitignore new file mode 100644 index 000000000..7624d1c9b --- /dev/null +++ b/debian/.gitignore @@ -0,0 +1,10 @@ +.debhelper +files +debhelper-build-stamp +*.log +*.substvars +libstlink-dev +libstlink +stlink-gui +stlink-tools +tmp diff --git a/doc/tested-boards.md b/doc/tested-boards.md index 7c16062dd..7087ef9fe 100644 --- a/doc/tested-boards.md +++ b/doc/tested-boards.md @@ -34,7 +34,7 @@ STLink v2 (as found on the 32L and F4 Discovery boards), known working targets: STLink v2-1 (as found on the Nucleo boards), known working targets: -* STM32F401xx (STM32 Nucleo-F401RE board) +* STM32F401xx (STM32 Nucleo-F401RE board) * STM32F030R8T6 (STM32 Nucleo-F030R8 board) * STM32F072RBT6 (STM32 Nucleo-F072RB board) * STM32F103RB (STM32 Nucleo-F103RB board) @@ -46,6 +46,7 @@ STLink v2-1 (as found on the Nucleo boards), known working targets: * STM32F769NI (STM32F7 discovery board) * Nucleo-L152RE board * [Nucleo-L476RG board](http://www.st.com/en/evaluation-tools/nucleo-l476rg.html) +* STM32L452RET6 (STM32 Nucleo-L452RE board) Please report any and all known working combinations so I can update this! diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 6a078aa1b..6a11ab823 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -34,7 +34,12 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F37x = 0x432, STLINK_CHIPID_STM32_F4_DE = 0x433, STLINK_CHIPID_STM32_F4_DSI = 0x434, + /* + * 0x435 covers STM32L43xxx and STM32L44xxx devices + * 0x462 covers STM32L45xxx and STM32L46xxx devices + */ STLINK_CHIPID_STM32_L43X = 0x435, + STLINK_CHIPID_STM32_L46X = 0x462, /* * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus" * and some that are called "High". 0x427 is assigned to the other "Medium- diff --git a/src/chipid.c b/src/chipid.c index 808a23c52..059afba1b 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -430,21 +430,35 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) .bootrom_size = 0x7000 // 28k (per bank), same source as base }, - { - // STLINK_CHIPID_STM32_L43X + { + // STLINK_CHIPID_STM32_L43X // From RM0392. - .chip_id = STLINK_CHIPID_STM32_L43X, - .description = "L43x device", + .chip_id = STLINK_CHIPID_STM32_L43X, + .description = "L43x/L44x device", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) .flash_pagesize = 0x800, // 2K (sec 3.2, page 74; also appears in sec 3.3.1 and tables 7-8 on pages 75-76) // SRAM1 is "up to" 64k in the standard Cortex-M memory map; - // SRAM2 is 16k mapped at at 0x10000000 (sec 2.3, page 73 for + // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for // sizes; table 2, page 74 for SRAM2 location) .sram_size = 0xc000, .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) .bootrom_size = 0x7000 // 28k (per bank), same source as base }, + { + // STLINK_CHIPID_STM32_L46X + // From RM0394 (updated version of RM0392?). + .chip_id = STLINK_CHIPID_STM32_L46X, + .description = "L45x/46x device", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) + .flash_pagesize = 0x800, // 2K (sec 3.2, page 73; also appears in sec 3.3.1 and tables 7 on pages 73-74) + // SRAM1 is 128k at 0x20000000; + // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, page 68, also fig 2 on page 63) + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system memory, also fig 2 on page 63) + .bootrom_size = 0x7000 // 28k (per bank), same source as base + }, { // STM32L011 .chip_id = STLINK_CHIPID_STM32_L011, diff --git a/src/flash_loader.c b/src/flash_loader.c index 96084ab27..1fc0388de 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -304,7 +304,8 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43X)) + (sl->chip_id == STLINK_CHIPID_STM32_L43X) || + (sl->chip_id == STLINK_CHIPID_STM32_L46X)) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); From bf5870050fad788822f8ad4b4c55d82722186020 Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Thu, 29 Jun 2017 22:33:31 +0300 Subject: [PATCH 0572/1435] Fix mingw build (#610) * fix compilation for mingw * add *.user to ignor --- .gitignore | 1 + CMakeLists.txt | 13 +++++++++---- src/mingw/mingw.c | 4 ++-- src/mingw/mingw.h | 6 +++++- src/usb.c | 2 +- 5 files changed, 18 insertions(+), 8 deletions(-) diff --git a/.gitignore b/.gitignore index 89cda6de8..3a3a5f38a 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,3 @@ build obj-* +*.user* diff --git a/CMakeLists.txt b/CMakeLists.txt index d0660cf05..46790de91 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -32,6 +32,11 @@ if (STLINK_HAVE_SYS_MMAN_H) add_definitions(-DSTLINK_HAVE_SYS_MMAN_H) endif() +CHECK_INCLUDE_FILE(unistd.h STLINK_HAVE_UNISTD_H) +if (STLINK_HAVE_UNISTD_H) + add_definitions(-DSTLINK_HAVE_UNISTD_H) +endif() + if (CMAKE_BUILD_TYPE STREQUAL "") set(CMAKE_BUILD_TYPE "Debug") endif() @@ -73,10 +78,10 @@ include_directories(include) include_directories(${PROJECT_BINARY_DIR}/include) include_directories(src/mingw) if (MSVC) - include_directories(src/win32) - include_directories(src/getopt) - # Use string.h rather than strings.h and disable annoying warnings - add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) + include_directories(src/win32) + include_directories(src/getopt) + # Use string.h rather than strings.h and disable annoying warnings + add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) endif () ### diff --git a/src/mingw/mingw.c b/src/mingw/mingw.c index b342e7db2..8cf289f93 100644 --- a/src/mingw/mingw.c +++ b/src/mingw/mingw.c @@ -271,9 +271,9 @@ char *win32_strsep (char **stringp, const char *delim) /* NOTREACHED */ } +#ifdef STLINK_HAVE_SYS_MMAN_H void usleep(DWORD waitTime) { -#ifdef _MSC_VER if (waitTime >= 1000) { // Don't do long busy-waits. @@ -290,7 +290,6 @@ void usleep(DWORD waitTime) CloseHandle(timer); return; } -#endif LARGE_INTEGER perf_cnt, start, now; QueryPerformanceFrequency(&perf_cnt); @@ -300,6 +299,7 @@ void usleep(DWORD waitTime) QueryPerformanceCounter((LARGE_INTEGER*) &now); } while ((now.QuadPart - start.QuadPart) / (float)perf_cnt.QuadPart * 1000 * 1000 < waitTime); } +#endif #endif diff --git a/src/mingw/mingw.h b/src/mingw/mingw.h index 4b5cf5380..dd82a8f99 100644 --- a/src/mingw/mingw.h +++ b/src/mingw/mingw.h @@ -9,7 +9,9 @@ #include #include +#if defined(_MSC_VER) #pragma comment(lib, "ws2_32.lib") +#endif #include #if defined(_MSC_VER) @@ -69,7 +71,9 @@ char *win32_strsep(char **stringp, const char *delim); ssize_t win32_read_socket(SOCKET fd, void *buf, int n); ssize_t win32_write_socket(SOCKET fd, void *buf, int n); +#ifdef STLINK_HAVE_SYS_MMAN_H static inline void sleep(unsigned ms) { Sleep(ms); } void usleep(DWORD waitTime); - #endif + +#endif //defined(__MINGW32__) || defined(_MSC_VER) diff --git a/src/usb.c b/src/usb.c index 299de8740..92a0a6ef4 100644 --- a/src/usb.c +++ b/src/usb.c @@ -6,8 +6,8 @@ #include #endif #include -#if defined(_MSC_VER) #include +#if defined(_MSC_VER) #pragma warning(push) #pragma warning(disable: 4200 4255 4668 4820) #include From 28bfddacff47bd29329a58699056bc86a31f0d8c Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Thu, 29 Jun 2017 23:42:13 +0300 Subject: [PATCH 0573/1435] use correct macros for switch usleep realisation (#611) --- src/mingw/mingw.c | 2 +- src/mingw/mingw.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mingw/mingw.c b/src/mingw/mingw.c index 8cf289f93..aee288d88 100644 --- a/src/mingw/mingw.c +++ b/src/mingw/mingw.c @@ -271,7 +271,7 @@ char *win32_strsep (char **stringp, const char *delim) /* NOTREACHED */ } -#ifdef STLINK_HAVE_SYS_MMAN_H +#ifndef STLINK_HAVE_UNISTD_H void usleep(DWORD waitTime) { if (waitTime >= 1000) diff --git a/src/mingw/mingw.h b/src/mingw/mingw.h index dd82a8f99..04907f7d6 100644 --- a/src/mingw/mingw.h +++ b/src/mingw/mingw.h @@ -71,7 +71,7 @@ char *win32_strsep(char **stringp, const char *delim); ssize_t win32_read_socket(SOCKET fd, void *buf, int n); ssize_t win32_write_socket(SOCKET fd, void *buf, int n); -#ifdef STLINK_HAVE_SYS_MMAN_H +#ifndef STLINK_HAVE_UNISTD_H static inline void sleep(unsigned ms) { Sleep(ms); } void usleep(DWORD waitTime); #endif From 773d05a3b585642d85dcc4a7454c26716e2c3e2c Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 1 Jul 2017 16:41:54 +0200 Subject: [PATCH 0574/1435] Prepare v1.4.0 release --- .version | 2 +- ChangeLog.md | 18 ++++++++++++++++-- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/.version b/.version index 3a3cd8cc8..88c5fb891 100644 --- a/.version +++ b/.version @@ -1 +1 @@ -1.3.1 +1.4.0 diff --git a/ChangeLog.md b/ChangeLog.md index f12d176f6..a6c4cca89 100644 --- a/ChangeLog.md +++ b/ChangeLog.md @@ -1,13 +1,27 @@ Stlink ChangeLog ================ -v1.3.2 +v1.4.0 ====== -Release date: ongoing +Release date: 2017-07-01 + +Major changes and added features: + +* Add support for STM32L452 target ([#608](https://github.com/texane/stlink/pull/608)) +* Initial support to compile with Microsoft Visual Studio 2017 ([#602](https://github.com/texane/stlink/pull/602)) +* Added support for flashing second bank on STM32F10x_XL ([#592](https://github.com/texane/stlink/pull/592)) +* Add support for STM32L011 target ([#572](https://github.com/texane/stlink/pull/572)) +* Allow building of debian package with CPack (@xor-gate) Updates and fixes: +* Fix compilation with GCC 7 ([#590](https://github.com/texane/stlink/pull/590)) +* Skip GTK detection if we're cross-compiling ([#588](https://github.com/texane/stlink/pull/588)) +* Fix possible memory leak ([#570](https://github.com/texane/stlink/pull/570)) +* Fix building with mingw64 ([#569](https://github.com/texane/stlink/pull/569), [#610](https://github.com/texane/stlink/pull/610)) +* Update libusb to 1.0.21 for Windows ([#562](https://github.com/texane/stlink/pull/562)) +* Fixing low-voltage flashing on STM32F7 parts. ([#567](https://github.com/texane/stlink/pull/567)) * Update libusb to 1.0.21 for Windows ([#562](https://github.com/texane/stlink/pull/562)) v1.3.1 From 5e740a8434a06ab154d0da8cc0a3e0d29399a25c Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 1 Jul 2017 16:44:47 +0200 Subject: [PATCH 0575/1435] README.md: Update version badge to v1.4.0 --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 3c6f48a0d..17a62a9f1 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ Open source version of the STMicroelectronics Stlink Tools [![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/texane/stlink/releases/latest) [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) -[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.3.1.svg)](https://github.com/texane/stlink/compare/1.3.1...master) +[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.4.0.svg)](https://github.com/texane/stlink/compare/1.4.0...master) [![Downloads](https://img.shields.io/github/downloads/texane/stlink/total.svg)](https://github.com/texane/stlink/releases) [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) [![Build Status](https://jenkins.ncrmnt.org/buildStatus/icon?job=GithubCI/stlink)](https://jenkins.ncrmnt.org/job/GithubCI/job/stlink/) From 0c84c29e590e6d038114b84dac628d755607d64c Mon Sep 17 00:00:00 2001 From: Viallard Anthony Date: Fri, 14 Jul 2017 16:19:49 +0200 Subject: [PATCH 0576/1435] Add support of STM32L496xx/4A6xx devices (#615) --- include/stlink/chipid.h | 2 ++ src/chipid.c | 14 ++++++++++++++ src/flash_loader.c | 3 ++- 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 6a11ab823..36a327c8e 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -36,9 +36,11 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F4_DSI = 0x434, /* * 0x435 covers STM32L43xxx and STM32L44xxx devices + * 0x461 covers STM32L496xx and STM32L4A6xx devices * 0x462 covers STM32L45xxx and STM32L46xxx devices */ STLINK_CHIPID_STM32_L43X = 0x435, + STLINK_CHIPID_STM32_L496X = 0x461, STLINK_CHIPID_STM32_L46X = 0x462, /* * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus" diff --git a/src/chipid.c b/src/chipid.c index 059afba1b..c84638b01 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -445,6 +445,20 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) .bootrom_size = 0x7000 // 28k (per bank), same source as base }, + { + // STLINK_CHIPID_STM32_L496X + // Support based on en.DM00083560.pdf (RM0351) document rev 5. + .chip_id = STLINK_CHIPID_STM32_L496X, + .description = "L496x/L4A6x device", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) + .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) + // SRAM1 is 256k at 0x20000000 + // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) + .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) + .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) + .bootrom_size = 0x7000 // 28k (per bank), same source as base + }, { // STLINK_CHIPID_STM32_L46X // From RM0394 (updated version of RM0392?). diff --git a/src/flash_loader.c b/src/flash_loader.c index 1fc0388de..9abda5835 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -305,7 +305,8 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_size = sizeof(loader_code_stm32f0); } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || (sl->chip_id == STLINK_CHIPID_STM32_L43X) || - (sl->chip_id == STLINK_CHIPID_STM32_L46X)) + (sl->chip_id == STLINK_CHIPID_STM32_L46X) || + (sl->chip_id == STLINK_CHIPID_STM32_L496X)) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); From 691a2d5026296fd70b51148e22c5f2d8c559d9cf Mon Sep 17 00:00:00 2001 From: rdlim Date: Sat, 15 Jul 2017 11:29:55 -0700 Subject: [PATCH 0577/1435] Fix verification of flash error for STM32L496x device (#617) (#618) There were missing chipid checks of STM32L496xx and STM32L46x devices. --- src/common.c | 11 ++++++++--- src/gdbserver/gdb-server.c | 5 ++++- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/src/common.c b/src/common.c index e40f2d42a..a55613b22 100644 --- a/src/common.c +++ b/src/common.c @@ -1484,7 +1484,10 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) unlock_flash_if(sl); /* select the page to erase */ - if (sl->chip_id == STLINK_CHIPID_STM32_L4 || sl->chip_id == STLINK_CHIPID_STM32_L43X) { + if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || + (sl->chip_id == STLINK_CHIPID_STM32_L43X) || + (sl->chip_id == STLINK_CHIPID_STM32_L46X) || + (sl->chip_id == STLINK_CHIPID_STM32_L496X)) { // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); @@ -1859,8 +1862,10 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t /* TODO: Check that Voltage range is 2.7 - 3.6 V */ if ((sl->chip_id != STLINK_CHIPID_STM32_L4) && - (sl->chip_id != STLINK_CHIPID_STM32_L43X)) - { + (sl->chip_id != STLINK_CHIPID_STM32_L43X) && + (sl->chip_id != STLINK_CHIPID_STM32_L46X) && + (sl->chip_id != STLINK_CHIPID_STM32_L496X)) { + if( sl->version.stlink_v == 1 ) { printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes on F4 devices\n"); write_flash_cr_psiz(sl, 2); diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index d7da544fa..b6776107c 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -518,7 +518,10 @@ char* make_memory_map(stlink_t *sl) { (unsigned int)sl->sram_size, (unsigned int)sl->flash_size - 0x20000, (unsigned int)sl->sys_base, (unsigned int)sl->sys_size); - } else if(sl->chip_id==STLINK_CHIPID_STM32_L4) { + } else if((sl->chip_id==STLINK_CHIPID_STM32_L4) || + (sl->chip_id==STLINK_CHIPID_STM32_L43X) || + (sl->chip_id==STLINK_CHIPID_STM32_L46X) || + (sl->chip_id==STLINK_CHIPID_STM32_L496X)) { snprintf(map, sz, memory_map_template_L4, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); } else { From 47ce70d6cfbd7c97e1ef36768afabc7bc2613e61 Mon Sep 17 00:00:00 2001 From: dflogeras Date: Thu, 27 Jul 2017 09:14:35 -0300 Subject: [PATCH 0578/1435] Add note about availability in Gentoo package manager (#622) --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index 17a62a9f1..75d421452 100644 --- a/README.md +++ b/README.md @@ -35,6 +35,8 @@ Arch Linux users can install from the [repository](https://www.archlinux.org/pac Alpine Linux users can install from the [repository](https://pkgs.alpinelinux.org/packages?name=stlink) +Gentoo Linux users can install from the official portage [repository](https://packages.gentoo.org/packages/dev-embedded/stlink) + FreeBSD users can install from [freshports](https://www.freshports.org/devel/stlink) OpenBSD users need to install [from source](doc/compiling.md). From 4e28e303b5931e12e46b9896e9c02d562af94757 Mon Sep 17 00:00:00 2001 From: yaofei zheng Date: Fri, 25 Aug 2017 03:06:21 -0500 Subject: [PATCH 0579/1435] update debian package version (#630) * update debian package version --- debian/changelog | 65 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/debian/changelog b/debian/changelog index d0471cb7d..0f3edb222 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,68 @@ +libstlink (1.4.0) unstable; urgency=low + + * Major changes and added features + - Add support for STM32L452 target (#608) + - Initial support to compile with Microsoft Visual Studio 2017 (#602) + - Added support for flashing second bank on STM32F10x_XL (#592) + - Add support for STM32L011 target (#572) + - Allow building of debian package with CPack (@xor-gate) + * Updates and fixes + - Fix compilation with GCC 7 (#590) + - Skip GTK detection if we're cross-compiling (#588) + - Fix possible memory leak (#570) + - Fix building with mingw64 (#569, #610) + - Update libusb to 1.0.21 for Windows (#562) + - Fixing low-voltage flashing on STM32F7 parts. (#567) + - Update libusb to 1.0.21 for Windows (#562) + + -- Andrew 'Necromant' Andrianov Sat, 01 Jul 2017 00:00:00 +0000 + +libstlink (1.3.1) unstable; urgency=low + + * Major changes and added features: + - Add preliminary support for STM32L011 to see it after probe (chipid 0x457) (@xor-gate) + - Strip full paths to source files in log (commit #2c0ab7f) + - Add support for STM32F413 target (#549) + - Add support for Semihosting SYS_READC (#546) + * Updates and fixes: + - Update documentation markdown files + - Compilation fixes (#552) + - Fix compilation when path includes spaces (#561) + + -- Andrew 'Necromant' Andrianov Sat, 25 Feb 2017 00:00:00 +0000 + +libstlink (1.3.0) unstable; urgency=low + + * Major changes and added features: + - Deprecation of autotools (autoconf, automake) (@xor-gate) + - Removal of undocumented st-term utility, which is now replaced by st-util ARM semihosting feature (#3fd0f09) + - Add support for native debian packaging (#444, #485) + - Add intel hex file reading for st-flash (#459) + - Add --reset command to st-flash (#505) + - Support serial numbers argument for st-util and st-flash for multi-programmer setups (#541) + - Add kill ('k') command to gdb-server for st-util (#9804416) + - Add manpages (generated with pandoc from Markdown) (#464) + - Rewrite commandline parsing for st-flash (#459) + - Add support for ARM semihosting to st-util (#454, #455) + * Chip support added for: + - STM32L432 (#501) + - STM32F412 (#538) + - STM32F410 (#9c635e4) + - Add memory map for STM32F401XE (#460) + - L0x Category 5 devices (#406) + - Add L0 Category 2 device (chip id: 0x425) (#72b8e5e) + * Updates and fixes: + - Fixed STM32F030 erase error (#442) + - Fixed Cygwin build (#68b0f3b) + - Reset flash mass erase (MER) bit after mass erase for safety (#489) + - Fix memory map for STM32F4 (@zulusw) + - Fix STM32L-problem with flash loader (issue #390) (Tom de Boer) + - st-util don't read target voltage on startup as it crashes STM32F100 (probably stlink/v1) (Greg Alexander) + - Do a JTAG reset prior to reading CPU information when processor is in deep sleep (@andyg24) + - Redesign of st-flash commandline options parsing (pull-request #459) (@dev26th) + + -- Andrew 'Necromant' Andrianov Sat, 28 Jan 2017 00:00:00 +0000 + libstlink (1.2.1) unstable; urgency=low * Initial Debian-Packaged Release. From 7b7a5c102c36d0833876c3cb57173cbac4d401f2 Mon Sep 17 00:00:00 2001 From: Lyle Cheatham Date: Sun, 27 Aug 2017 05:51:59 -0400 Subject: [PATCH 0580/1435] Minor formatting fix in FAQ section of README.md (#631) Fixup single quotes instead of back ticks --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 75d421452..7ea63280e 100644 --- a/README.md +++ b/README.md @@ -148,9 +148,9 @@ enough unused registers. In my experience, -O3 causes that frequently. Q: At some point I use GDB command `next', and it hangs. -A: Sometimes when you will try to use GDB `next' command to skip a loop, +A: Sometimes when you will try to use GDB `next` command to skip a loop, it will use a rather inefficient single-stepping way of doing that. -Set up a breakpoint manually in that case and do `continue'. +Set up a breakpoint manually in that case and do `continue`. Q: Load command does not work in GDB. From 3d8ca68dcaaeba0ed9db9a1d478c6284fe7aba8a Mon Sep 17 00:00:00 2001 From: Vasiliy Glazov Date: Thu, 7 Sep 2017 13:59:49 +0300 Subject: [PATCH 0581/1435] README.md: Added information about Fedora and RedHat/CentOS packages. (#635) --- README.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/README.md b/README.md index 7ea63280e..d062abdc6 100644 --- a/README.md +++ b/README.md @@ -35,6 +35,10 @@ Arch Linux users can install from the [repository](https://www.archlinux.org/pac Alpine Linux users can install from the [repository](https://pkgs.alpinelinux.org/packages?name=stlink) +Fedora users can install from [repository](https://src.fedoraproject.org/rpms/stlink) + +RedHat/CentOS 7 users can install from EPEL [repository](https://src.fedoraproject.org/rpms/stlink/branch/epel7) + Gentoo Linux users can install from the official portage [repository](https://packages.gentoo.org/packages/dev-embedded/stlink) FreeBSD users can install from [freshports](https://www.freshports.org/devel/stlink) From 1700e6a4712d3cfb229b3d9b6bc709ec12edc0bd Mon Sep 17 00:00:00 2001 From: Vasiliy Glazov Date: Fri, 8 Sep 2017 15:00:45 +0300 Subject: [PATCH 0582/1435] Added LIB_INSTALL_DIR to correct libs install on 64-bit systems (#636) * Added LIB_INSTALL_DIR to correct libs install on 64-bit systems * Add description for using LIB_INSTALL_DIR parameter. --- CMakeLists.txt | 3 ++- doc/compiling.md | 9 +++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 46790de91..da99b6ea7 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,7 +4,8 @@ project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics Stlink Tools") set(STLINK_UDEV_RULES_DIR "/etc/udev/rules.d" CACHE PATH "Udev rules directory") set(STLINK_MODPROBED_DIR "/etc/modprobe.d" CACHE PATH "modprobe.d directory") -set(STLINK_LIBRARY_PATH "lib/${CMAKE_LIBRARY_PATH}" CACHE PATH "Target lib directory") +set(LIB_INSTALL_DIR "lib" CACHE PATH "Main library directory") +set(STLINK_LIBRARY_PATH "${LIB_INSTALL_DIR}/${CMAKE_LIBRARY_PATH}" CACHE PATH "Target lib directory") option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) diff --git a/doc/compiling.md b/doc/compiling.md index 3518d1079..41d1fb7f9 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -118,6 +118,15 @@ $ cmake -DSTLINK_UDEV_RULES_DIR="/usr/lib/udev/rules.d" \ -DSTLINK_MODPROBED_DIR="/usr/lib/modprobe.d" .. ``` +## Build using different directory for shared libs + +To put the compiled shared libs into a different directory during installation +you can use the following cmake option: + +``` +$ cmake -DLIB_INSTALL_DIR:PATH="/usr/lib64" .. +``` + ## Windows (MinGW64) ### Prequistes From 6511a7e86185aaf3bafe0d8ae2252a83f4fb0c5b Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sat, 16 Sep 2017 20:37:42 +0200 Subject: [PATCH 0583/1435] fix write for microcontroler with RAM size less or equal to 32K (#637) --- src/common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index a55613b22..0658114d8 100644 --- a/src/common.c +++ b/src/common.c @@ -1899,8 +1899,9 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t /* set programming mode */ set_flash_cr_pg(sl); + size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; for(off = 0; off < len;) { - size_t size = len - off > 0x8000 ? 0x8000 : len - off; + size_t size = len - off > buf_size ? buf_size : len - off; printf("size: %u\n", (unsigned int)size); From 04dc7ead42f99d80696cd12496ee2299428675e7 Mon Sep 17 00:00:00 2001 From: Mateusz Krawiec Date: Fri, 29 Sep 2017 11:07:23 +0200 Subject: [PATCH 0584/1435] Fix memory map for stm32l496xx boards. (#639) --- src/gdbserver/gdb-server.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index b6776107c..f5afa73b4 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -433,6 +433,25 @@ static const char* const memory_map_template_L4 = " " // option byte area ""; +static const char* const memory_map_template_L496 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM2 (64 KB) + " " // SRAM1 (256 KB) + " " + " 0x800" + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + " " // option byte area + ""; + static const char* const memory_map_template = "" "sys_base, (unsigned int)sl->sys_size); } else if((sl->chip_id==STLINK_CHIPID_STM32_L4) || (sl->chip_id==STLINK_CHIPID_STM32_L43X) || - (sl->chip_id==STLINK_CHIPID_STM32_L46X) || - (sl->chip_id==STLINK_CHIPID_STM32_L496X)) { + (sl->chip_id==STLINK_CHIPID_STM32_L46X)) { snprintf(map, sz, memory_map_template_L4, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); + } else if(sl->chip_id==STLINK_CHIPID_STM32_L496X) { + snprintf(map, sz, memory_map_template_L496, + (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); } else { snprintf(map, sz, memory_map_template, (unsigned int)sl->flash_size, From a2a707e4f75fd8aafce3fa6095dc34206c5bb801 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?R=C3=BCdiger=20Fortanier?= Date: Tue, 10 Oct 2017 13:44:26 +0200 Subject: [PATCH 0585/1435] Add unknown chip output (#641) --- include/stlink/chipid.h | 2 ++ src/chipid.c | 11 +++++++++++ src/common.c | 3 ++- 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 36a327c8e..0e09d989f 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -11,6 +11,8 @@ extern "C" { * stm32 chipids, only lower 12 bits.. */ enum stlink_stm32_chipids { + STLINK_CHIPID_UNKNOWN = 0x000, + STLINK_CHIPID_STM32_F1_MEDIUM = 0x410, STLINK_CHIPID_STM32_F2 = 0x411, STLINK_CHIPID_STM32_F1_LOW = 0x412, diff --git a/src/chipid.c b/src/chipid.c index c84638b01..b81ff3544 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -484,6 +484,17 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1ff00000, .bootrom_size = 0x2000 }, + { + // unknown + .chip_id = STLINK_CHIPID_UNKNOWN, + .description = "unknown device", + .flash_type = STLINK_FLASH_TYPE_UNKNOWN, + .flash_size_reg = 0x0, + .flash_pagesize = 0x0, + .sram_size = 0x0, + .bootrom_base = 0x0, + .bootrom_size = 0x0 + }, }; diff --git a/src/common.c b/src/common.c index 0658114d8..b9b738203 100644 --- a/src/common.c +++ b/src/common.c @@ -644,7 +644,8 @@ int stlink_load_device_params(stlink_t *sl) { if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { WLOG("Invalid flash type, please check device declaration\n"); - return -1; + sl->flash_size = 0; + return 0; } // These are fixed... From 95b6e03ed0c0ee40256a33f04eedf702005a9d8b Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Wed, 25 Oct 2017 22:48:43 +0300 Subject: [PATCH 0586/1435] fix __FILE__ base name extraction, #628 (#648) --- CMakeLists.txt | 5 ----- include/stlink/logging.h | 6 ++---- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index da99b6ea7..d2be523bf 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -46,11 +46,6 @@ if (${CMAKE_BUILD_TYPE} MATCHES "Debug") include(CTest) endif() -# fixup __FILE__ absolute paths in logging module -# see: https://cmake.org/pipermail/cmake-developers/2015-January/024202.html -string(LENGTH "${CMAKE_SOURCE_DIR}/" CMAKE_SOURCE_DIR_LENGTH) -add_definitions(-DCMAKE_SOURCE_DIR_LENGTH=${CMAKE_SOURCE_DIR_LENGTH}) - set(STLINK_HEADERS include/stlink.h include/stlink/usb.h diff --git a/include/stlink/logging.h b/include/stlink/logging.h index 9a98a6bc5..a6632a730 100644 --- a/include/stlink/logging.h +++ b/include/stlink/logging.h @@ -20,10 +20,8 @@ enum ugly_loglevel { int ugly_init(int maximum_threshold); int ugly_log(int level, const char *tag, const char *format, ...); -#ifndef CMAKE_SOURCE_DIR_LENGTH -#define CMAKE_SOURCE_DIR_LENGTH 0 -#endif -#define UGLY_LOG_FILE (__FILE__+CMAKE_SOURCE_DIR_LENGTH) +#define UGLY_LOG_FILE (strstr(__FILE__, "/") != NULL ? \ + strrchr(__FILE__, '/') + 1 : strrchr(__FILE__, '\\') + 1) /** @todo we need to write this in a more generic way, for now this should compile on visual studio (See http://stackoverflow.com/a/8673872/1836746) */ From 19691485359afef1a256964afcbb8dcf4b733209 Mon Sep 17 00:00:00 2001 From: texane Date: Thu, 16 Nov 2017 22:46:12 +0100 Subject: [PATCH 0587/1435] STM32F72xx73xx support, from bob.feretich@rafresearch.com --- include/stlink/chipid.h | 3 ++- src/chipid.c | 11 +++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 0e09d989f..7cf5b4881 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -62,8 +62,9 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F303_HIGH = 0x446, STLINK_CHIPID_STM32_L0_CAT5 = 0x447, STLINK_CHIPID_STM32_F0_CAN = 0x448, - STLINK_CHIPID_STM32_F7 = 0x449, + STLINK_CHIPID_STM32_F7 = 0x449, /* This ID is found on the NucleoF746ZG board */ STLINK_CHIPID_STM32_F7XXXX = 0x451, + STLINK_CHIPID_STM32_F72XXX = 0x452, /* This ID is found on the NucleoF722ZE board */ STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, STLINK_CHIPID_STM32_F413 = 0x463 diff --git a/src/chipid.c b/src/chipid.c index b81ff3544..7cf83218d 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -24,6 +24,17 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18 }, + { + //RM0431 and DS document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F72XXX, + .description = "F72 device", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff07a22, // section 35.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 + .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 24 + }, { // table 2, PM0063 .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, .description = "F1 Medium-density device", From fbd55d9f1b00b84512d1144dfbbe507a3e5e10c0 Mon Sep 17 00:00:00 2001 From: Kirill Kolyshkin Date: Tue, 6 Feb 2018 05:45:57 -0800 Subject: [PATCH 0588/1435] debian/triggers: add (to run ldconfig) (#664) After installing the deb package, st-util fails to start: > $ st-util > st-util: error while loading shared libraries: libstlink-shared.so.1: > cannot open shared object file: No such file or directory The reason is, no one ran `ldconfig` upon installing the library. The solution, as per latest Debian recommendations [1], is to add an ldconfig trigger in debian/triggers, which is what this commit does. [1] https://www.debian.org/doc/debian-policy/#ldconfig Signed-off-by: Kir Kolyshkin --- debian/triggers | 1 + 1 file changed, 1 insertion(+) create mode 100644 debian/triggers diff --git a/debian/triggers b/debian/triggers new file mode 100644 index 000000000..dd8660367 --- /dev/null +++ b/debian/triggers @@ -0,0 +1 @@ +activate-noawait ldconfig From 247b7eb9ba7a96275425469c1d433868cb6d45d5 Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Thu, 15 Feb 2018 20:18:05 +0200 Subject: [PATCH 0589/1435] Try to fix #666 issue (#667) --- src/tools/gui/stlink-gui.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/tools/gui/stlink-gui.c b/src/tools/gui/stlink-gui.c index d45db6ff2..c9e68af4f 100644 --- a/src/tools/gui/stlink-gui.c +++ b/src/tools/gui/stlink-gui.c @@ -224,11 +224,14 @@ stlink_gui_update_devmem_view (STlinkGUI *gui) static void -stlink_gui_populate_devmem_view (STlinkGUI *gui) +stlink_gui_populate_devmem_view (gpointer data) { guint off; stm32_addr_t addr; + g_return_if_fail (STLINK_IS_GUI (data)); + STlinkGUI *gui = (STlinkGUI *)data; + g_return_if_fail (gui != NULL); g_return_if_fail (gui->sl != NULL); From d9a114a6411345d5e27d3458b1ec7f970dab162b Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Fri, 16 Feb 2018 14:01:08 +0200 Subject: [PATCH 0590/1435] Try to fix 666 issue (#668) * try to fix #666 issue * has fixed few function's signatures for match g_thread_new expectations. * fix check in stlink_gui_populate_filemem_view * fix gcc-8 warnings * fix g_return* for proper one --- src/tools/gui/stlink-gui.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/src/tools/gui/stlink-gui.c b/src/tools/gui/stlink-gui.c index c9e68af4f..34afb2c51 100644 --- a/src/tools/gui/stlink-gui.c +++ b/src/tools/gui/stlink-gui.c @@ -223,17 +223,18 @@ stlink_gui_update_devmem_view (STlinkGUI *gui) } -static void + +static gpointer stlink_gui_populate_devmem_view (gpointer data) { guint off; stm32_addr_t addr; - g_return_if_fail (STLINK_IS_GUI (data)); + g_return_val_if_fail (STLINK_IS_GUI (data), NULL); STlinkGUI *gui = (STlinkGUI *)data; - g_return_if_fail (gui != NULL); - g_return_if_fail (gui->sl != NULL); + g_return_val_if_fail ((gui != NULL), NULL); + g_return_val_if_fail ((gui->sl != NULL), NULL); addr = gui->sl->flash_base; @@ -261,12 +262,14 @@ stlink_gui_populate_devmem_view (gpointer data) stlink_gui_set_info_error_message (gui, "Failed to read memory"); g_free (gui->flash_mem.memory); gui->flash_mem.memory = NULL; - return; + return NULL; } memcpy (gui->flash_mem.memory + off, gui->sl->q_buf, n_read); gui->progress.fraction = (gdouble) (off + n_read) / gui->sl->flash_size; } g_idle_add ((GSourceFunc) stlink_gui_update_devmem_view, gui); + + return NULL; } static gboolean @@ -286,7 +289,7 @@ stlink_gui_update_filemem_view (STlinkGUI *gui) } static gpointer -stlink_gui_populate_filemem_view (STlinkGUI *gui) +stlink_gui_populate_filemem_view (gpointer data) { guchar buffer[MEM_READ_SIZE]; GFile *file; @@ -295,6 +298,9 @@ stlink_gui_populate_filemem_view (STlinkGUI *gui) gint off; GError *err = NULL; + g_return_val_if_fail (STLINK_IS_GUI (data), NULL); + STlinkGUI *gui = (STlinkGUI *)data; + g_return_val_if_fail (gui != NULL, NULL); g_return_val_if_fail (gui->filename != NULL, NULL); @@ -643,17 +649,21 @@ stlink_gui_write_flash_update (STlinkGUI *gui) return FALSE; } -static void -stlink_gui_write_flash (STlinkGUI *gui) +static gpointer +stlink_gui_write_flash (gpointer data) { - g_return_if_fail (gui->sl != NULL); - g_return_if_fail (gui->filename != NULL); + g_return_val_if_fail (STLINK_IS_GUI (data), NULL); + STlinkGUI *gui = (STlinkGUI *)data; + + g_return_val_if_fail ((gui->sl != NULL), NULL); + g_return_val_if_fail ((gui->filename != NULL), NULL); if (stlink_fwrite_flash(gui->sl, gui->filename, gui->sl->flash_base) < 0) { stlink_gui_set_info_error_message (gui, "Failed to write to flash"); } g_idle_add ((GSourceFunc) stlink_gui_write_flash_update, gui); + return NULL; } static void From ddf60b48998e160e94845ad732768b8d4a0ca8c2 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 16 Feb 2018 13:06:36 +0100 Subject: [PATCH 0591/1435] Update ChangeLog.md Prepare for 1.5.0 release --- ChangeLog.md | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/ChangeLog.md b/ChangeLog.md index a6c4cca89..ec397ece6 100644 --- a/ChangeLog.md +++ b/ChangeLog.md @@ -1,6 +1,24 @@ Stlink ChangeLog ================ +v1.5.0 +====== + +Release date: 2018-02-16 + +Major changes and added features: + +* STM32F72xx73xx support ([#1969148](https://github.com/texane/stlink/commit/19691485359afef1a256964afcbb8dcf4b733209)) +* Add support of STM32L496xx/4A6xx devices ([#615](https://github.com/texane/stlink/pull/615)) + +Fixes: + +* Fix memory map for stm32l496xx boards ([#639](https://github.com/texane/stlink/pull/639)) +* Fix write for microcontroler with RAM size less or equal to 32K ([#637](https://github.com/texane/stlink/pull/637)) +* Added LIB_INSTALL_DIR to correct libs install on 64-bit systems ([#636](https://github.com/texane/stlink/pull/636)) +* Fix verification of flash error for STM32L496x device ([#618](https://github.com/texane/stlink/pull/618)) +* Fix build on Fedora with GCC 8 ([#666](https://github.com/texane/stlink/pull/668)) + v1.4.0 ====== From 954a64917a2143b56841d70d7e70f3280156ce17 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Fri, 16 Feb 2018 13:08:54 +0100 Subject: [PATCH 0592/1435] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index d062abdc6..6e23356af 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ Open source version of the STMicroelectronics Stlink Tools [![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/texane/stlink/releases/latest) [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) -[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.4.0.svg)](https://github.com/texane/stlink/compare/1.4.0...master) +[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.5.0.svg)](https://github.com/texane/stlink/compare/1.4.0...master) [![Downloads](https://img.shields.io/github/downloads/texane/stlink/total.svg)](https://github.com/texane/stlink/releases) [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) [![Build Status](https://jenkins.ncrmnt.org/buildStatus/icon?job=GithubCI/stlink)](https://jenkins.ncrmnt.org/job/GithubCI/job/stlink/) From c0d759dc41d6ed4fc697f337028ea43e8c32c241 Mon Sep 17 00:00:00 2001 From: texane Date: Sun, 18 Feb 2018 08:01:58 +0100 Subject: [PATCH 0593/1435] STM32F042K6 Nucleo-32 Board reported to work, by frank@bauernoeppel.de --- doc/tested-boards.md | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/tested-boards.md b/doc/tested-boards.md index 7087ef9fe..27d09cc34 100644 --- a/doc/tested-boards.md +++ b/doc/tested-boards.md @@ -47,6 +47,7 @@ STLink v2-1 (as found on the Nucleo boards), known working targets: * Nucleo-L152RE board * [Nucleo-L476RG board](http://www.st.com/en/evaluation-tools/nucleo-l476rg.html) * STM32L452RET6 (STM32 Nucleo-L452RE board) +* STM32F042K6 (STM32 Nucleo-32 Board) Please report any and all known working combinations so I can update this! From af4d2eb510de44e99bd9894d0e29f5256f7539bb Mon Sep 17 00:00:00 2001 From: Anatol Pomozov Date: Mon, 19 Feb 2018 11:00:29 -0800 Subject: [PATCH 0594/1435] Update .version file to match release number (#670) --- .version | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.version b/.version index 88c5fb891..bc80560fa 100644 --- a/.version +++ b/.version @@ -1 +1 @@ -1.4.0 +1.5.0 From 4e27060689d22d337a6f953f3cfdb6399542947c Mon Sep 17 00:00:00 2001 From: Jared Szechy Date: Wed, 28 Feb 2018 07:23:45 -0500 Subject: [PATCH 0595/1435] Fix missing flash_loader for L011 (#675) Fixes #654 flash loader on L011 --- src/flash_loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/flash_loader.c b/src/flash_loader.c index 9abda5835..a9eafcda3 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -257,7 +257,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* if (sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2 || sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS || sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH - || sl->chip_id == STLINK_CHIPID_STM32_L152_RE + || sl->chip_id == STLINK_CHIPID_STM32_L152_RE || sl->chip_id == STLINK_CHIPID_STM32_L011 || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); From c8dbc0adb3a5788c498ab45cd04bee40ed3fd060 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 1 Mar 2018 11:40:10 +0100 Subject: [PATCH 0596/1435] doc/man: Fix reference to non-exisiting st-term tool. Fixes #676. --- doc/man/st-flash.1 | 44 ++++++++++++++++++++++++++------------------ doc/man/st-flash.md | 4 ++-- doc/man/st-info.1 | 32 ++++++++++++++++++-------------- doc/man/st-info.md | 5 ++--- doc/man/st-util.1 | 39 +++++++++++++++++++++------------------ doc/man/st-util.md | 4 ++-- 6 files changed, 71 insertions(+), 57 deletions(-) diff --git a/doc/man/st-flash.1 b/doc/man/st-flash.1 index 77a8bb550..5a36354e9 100644 --- a/doc/man/st-flash.1 +++ b/doc/man/st-flash.1 @@ -1,18 +1,21 @@ -.TH ST-FLASH 1 "Sep 2016" "Open Source STMicroelectronics Stlink Tools" "STLINK" +.\" Automatically generated by Pandoc 2.1.1 +.\" +.TH "st\-flash" "1" "Feb 2018" "Open Source STMicroelectronics Stlink Tools" "stlink" +.hy .SH NAME .PP -st-flash - Flash binary files to STM32 device +st\-flash \- Flash binary files to STM32 device .SH SYNOPSIS .PP -\f[I]st-flash\f[] [\f[I]OPTIONS\f[]] {read|write|erase} [\f[I]FILE\f[]] +\f[I]st\-flash\f[] [\f[I]OPTIONS\f[]] {read|write|erase} [\f[I]FILE\f[]] .SH DESCRIPTION .PP Flash binary files to arbitrary sections of memory, or read arbitrary addresses of memory out to a binary file. .PP -You can use this instead of st-util(1) if you prefer, but remember to -use the \f[B]\&.bin\f[] image, rather than the \f[B]\&.elf\f[] file. +You can use this instead of st\-util(1) if you prefer, but remember to +use the \f[B].bin\f[] image, rather than the \f[B].elf\f[] file. .PP Use hexadecimal format for the \f[I]ADDR\f[] and \f[I]SIZE\f[]. .SH COMMANDS @@ -32,33 +35,38 @@ Read firmware from device starting from \f[I]ADDR\f[] up to Perform a mass erasing of the device firmware .RS .RE +.TP +.B reset +Reset the target +.RS +.RE .SH OPTIONS .TP -.B --version +.B \[en]version Print version information .RS .RE .TP -.B --debug +.B \[en]debug TODO .RS .RE .TP -.B --reset +.B \[en]reset TODO .RS .RE .TP -.B --serial \f[I]iSerial\f[] +.B \[en]serial \f[I]iSerial\f[] TODO .RS .RE .TP -.B --flash=\f[I]size\f[] -Override the device's normal flash size, where size is the flash size in bytes. -It can be specified in decimal, octal or hexadecimal. -The size argument can optionally be followed by 'k' for KB or 'm' for MB. -Examples --flash=128k or --flash=0x080k. +.B \[en]flash=fsize +Where fsize is the size in decimal, octal, or hex followed by an +optional multiplier `k' for KB, or `m' for MB. +Use a leading \[lq]0x\[rq] to specify hexadecimal, or a leading zero for +octal. .RS .RE .SH EXAMPLES @@ -67,7 +75,7 @@ Flash \f[C]firmware.bin\f[] to device .IP .nf \f[C] -$\ st-flash\ write\ firmware.bin\ 0x8000000 +$\ st\-flash\ write\ firmware.bin\ 0x8000000 \f[] .fi .PP @@ -75,7 +83,7 @@ Read firmware from device (4096 bytes) .IP .nf \f[C] -$\ st-flash\ read\ firmware.bin\ 0x8000000\ 4096 +$\ st\-flash\ read\ firmware.bin\ 0x8000000\ 4096 \f[] .fi .PP @@ -83,12 +91,12 @@ Erase firmware from device .IP .nf \f[C] -$\ st-flash\ erase +$\ st\-flash\ erase \f[] .fi .SH SEE ALSO .PP -st-util(1), st-info(1), st-term(1) +st\-util(1), st\-info(1) .SH COPYRIGHT .PP This work is copyrighted. diff --git a/doc/man/st-flash.md b/doc/man/st-flash.md index d1844976c..0ac9b111f 100644 --- a/doc/man/st-flash.md +++ b/doc/man/st-flash.md @@ -1,6 +1,6 @@ -% ST-FLASH(1) Open Source STMicroelectronics Stlink Tools | STLINK +% st-flash(1) Open Source STMicroelectronics Stlink Tools | stlink % -% Sep 2016 +% Feb 2018 # NAME diff --git a/doc/man/st-info.1 b/doc/man/st-info.1 index 8576d39e4..a774d3ade 100644 --- a/doc/man/st-info.1 +++ b/doc/man/st-info.1 @@ -1,10 +1,14 @@ -.TH ST-INFO 1 "Sep 2016" "Open Source STMicroelectronics Stlink Tools" "STLINK" +.\" Automatically generated by Pandoc 2.1.1 +.\" +.TH "st\-flash" "1" "Feb 2018" "Open Source STMicroelectronics Stlink Tools" "stlink" +.hy .SH NAME .PP -st-info - Provides information about connected STLink and STM32 devices +st\-info \- Provides information about connected STLink and STM32 +devices .SH SYNOPSIS .PP -\f[I]st-info\f[] [\f[I]OPTIONS\f[]] +\f[I]st\-info\f[] [\f[I]OPTIONS\f[]] .SH DESCRIPTION .PP Provides information about connected STLink programmers and STM32 @@ -12,47 +16,47 @@ devices: Serial code, openocd, flash, sram, page size, chipid, description. .SH OPTIONS .TP -.B --version +.B \[en]version Print version information .RS .RE .TP -.B --flash +.B \[en]flash Display amount of flash memory available in the device .RS .RE .TP -.B --sram +.B \[en]sram Display amount of sram memory available in device .RS .RE .TP -.B --descr +.B \[en]descr Display textual description of the device .RS .RE .TP -.B --pagesize +.B \[en]pagesize Display the page size of the device .RS .RE .TP -.B --chipid +.B \[en]chipid Display the chip ID of the device .RS .RE .TP -.B --serial +.B \[en]serial Display the serial code of the device .RS .RE .TP -.B --hla-serial +.B \[en]hla\-serial Display the hex escaped serial code of the device .RS .RE .TP -.B --probe +.B \[en]probe Display the summarized information of the connected programmers and devices .RS @@ -63,12 +67,12 @@ Display information about connected programmers and devices .IP .nf \f[C] -$\ st-info\ --probe +$\ st\-info\ \-\-probe \f[] .fi .SH SEE ALSO .PP -st-util(1), st-flash(1), st-term(1) +st\-util(1), st\-flash(1) .SH COPYRIGHT .PP This work is copyrighted. diff --git a/doc/man/st-info.md b/doc/man/st-info.md index 62d7c5ce1..1a0773e74 100644 --- a/doc/man/st-info.md +++ b/doc/man/st-info.md @@ -1,7 +1,6 @@ -% ST-INFO(1) Open Source STMicroelectronics Stlink Tools | STLINK +% st-flash(1) Open Source STMicroelectronics Stlink Tools | stlink % -% Sep 2016 - +% Feb 2018 # NAME st-info - Provides information about connected STLink and STM32 devices diff --git a/doc/man/st-util.1 b/doc/man/st-util.1 index 8fb791221..6796bda23 100644 --- a/doc/man/st-util.1 +++ b/doc/man/st-util.1 @@ -1,68 +1,71 @@ -.TH ST-UTIL 1 "Sep 2016" "Open Source STMicroelectronics Stlink Tools" "STLINK" +.\" Automatically generated by Pandoc 2.1.1 +.\" +.TH "st\-util" "1" "Feb 2018" "Open Source STMicroelectronics Stlink Tools" "stlink" +.hy .SH NAME .PP -st-util - Run GDB server to interact with STM32 device +st\-util \- Run GDB server to interact with STM32 device .SH SYNOPSIS .PP -\f[I]st-util\f[] [...] +\f[I]st\-util\f[] [\&...] .SH DESCRIPTION .PP Start a GDB server to interact with a STM32 device Run the main binary of the local package (src/main.rs). .PP -If a port number is not specified using the \f[B]--listen_port\f[] +If a port number is not specified using the \f[B]\[en]listen_port\f[] option, the default \f[B]4242\f[] port will be used. .PP Stlink version 2 is used by default unless the option -\f[B]--stlinkv1\f[] is given. +\f[B]\[en]stlinkv1\f[] is given. .PP The STLinkV2 device to use can be specified in the environment variable STLINK_DEVICE on the format :. .SH OPTIONS .TP -.B -h, --help +.B \-h, \[en]help Print this message. .RS .RE .TP -.B --version +.B \[en]version Print version information .RS .RE .TP -.B -v \f[I]XX\f[], --verbose=XX +.B \-v \f[I]XX\f[], \[en]verbose=XX Specify a specific verbosity level (0..99) .RS .RE .TP -.B -v, --verbose +.B \-v, \[en]verbose Specify generally verbose logging .RS .RE .TP -.B -s \f[I]X\f[], --stlink_version=X +.B \-s \f[I]X\f[], \[en]stlink_version=X Choose what version of stlink to use, (defaults to 2) .RS .RE .TP -.B -1, --stlinkv1 +.B \-1, \[en]stlinkv1 Force stlink version 1 .RS .RE .TP -.B -p \f[I]4242\f[], --listen_port=1234 +.B \-p \f[I]4242\f[], \[en]listen_port=1234 Set the gdb server listen port. (default port: 4242) .RS .RE .TP -.B -m, --multi +.B \-m, \[en]multi Set gdb server to extended mode. -st-util will continue listening for connections after disconnect. +st\-util will continue listening for connections after disconnect. .RS .RE .TP -.B -n, --no-reset +.B \-n, \[en]no\-reset Do not reset board on connection. .RS .RE @@ -72,14 +75,14 @@ Run GDB server on port 4500 and connect to it .IP .nf \f[C] -$\ st-util\ -p\ 4500 +$\ st\-util\ \-p\ 4500 $\ gdb -(gdb)\ target\ extended-remote\ localhost:4500 +(gdb)\ target\ extended\-remote\ localhost:4500 \f[] .fi .SH SEE ALSO .PP -st-flash(1), st-info(1), st-term(1) +st\-flash(1), st\-info(1) .SH COPYRIGHT .PP This work is copyrighted. diff --git a/doc/man/st-util.md b/doc/man/st-util.md index fd744d825..325f84206 100644 --- a/doc/man/st-util.md +++ b/doc/man/st-util.md @@ -1,6 +1,6 @@ -% ST-UTIL(1) Open Source STMicroelectronics Stlink Tools | STLINK +% st-util(1) Open Source STMicroelectronics Stlink Tools | stlink % -% Sep 2016 +% Feb 2018 # NAME From 1f18a18a8594853c30acaae04c0569536b20e55b Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 1 Mar 2018 11:51:26 +0100 Subject: [PATCH 0597/1435] doc/man: Add semihosting parameter documentation, fix styling issue with double dashhes. Fixes #674. --- doc/man/st-flash.1 | 10 +++++----- doc/man/st-flash.md | 24 +++++++++++------------- doc/man/st-util.1 | 23 ++++++++++++++--------- doc/man/st-util.md | 31 ++++++++++++++++--------------- 4 files changed, 46 insertions(+), 42 deletions(-) diff --git a/doc/man/st-flash.1 b/doc/man/st-flash.1 index 5a36354e9..1ee272957 100644 --- a/doc/man/st-flash.1 +++ b/doc/man/st-flash.1 @@ -42,27 +42,27 @@ Reset the target .RE .SH OPTIONS .TP -.B \[en]version +.B \f[C]\-\-version\f[] Print version information .RS .RE .TP -.B \[en]debug +.B \f[C]\-\-debug\f[] TODO .RS .RE .TP -.B \[en]reset +.B \f[C]\-\-reset\f[] TODO .RS .RE .TP -.B \[en]serial \f[I]iSerial\f[] +.B \f[C]\-\-serial\f[] \f[I]iSerial\f[] TODO .RS .RE .TP -.B \[en]flash=fsize +.B \f[C]\-\-flash=fsize\f[] Where fsize is the size in decimal, octal, or hex followed by an optional multiplier `k' for KB, or `m' for MB. Use a leading \[lq]0x\[rq] to specify hexadecimal, or a leading zero for diff --git a/doc/man/st-flash.md b/doc/man/st-flash.md index 0ac9b111f..e617e4305 100644 --- a/doc/man/st-flash.md +++ b/doc/man/st-flash.md @@ -2,16 +2,16 @@ % % Feb 2018 - # NAME -st-flash - Flash binary files to STM32 device +st-flash - Flash binary files to STM32 device # SYNOPSIS -*st-flash* \[*OPTIONS*\] \{read|write|erase\} \[*FILE*\] \ \ +*st-flash* \[*OPTIONS*\] \{read|write|erase\} \[*FILE*\] \ \ # DESCRIPTION + Flash binary files to arbitrary sections of memory, or read arbitrary addresses of memory out to a binary file. @@ -20,7 +20,6 @@ You can use this instead of st-util(1) if you prefer, but remember to use the Use hexadecimal format for the *ADDR* and *SIZE*. - # COMMANDS write *FILE* *ADDR* @@ -37,43 +36,42 @@ reset # OPTIONS ---version +`--version` : Print version information ---debug +`--debug` : TODO ---reset +`--reset` : TODO ---serial *iSerial* +`--serial` *iSerial* : TODO ---flash=fsize +`--flash=fsize` : Where fsize is the size in decimal, octal, or hex followed by an optional multiplier 'k' for KB, or 'm' for MB. Use a leading "0x" to specify hexadecimal, or a leading zero for octal. # EXAMPLES + Flash `firmware.bin` to device $ st-flash write firmware.bin 0x8000000 - Read firmware from device (4096 bytes) $ st-flash read firmware.bin 0x8000000 4096 - Erase firmware from device $ st-flash erase - # SEE ALSO -st-util(1), st-info(1) +st-util(1), st-info(1) # COPYRIGHT + This work is copyrighted. Stlink contributors. See *LICENSE* file in the stlink source distribution. diff --git a/doc/man/st-util.1 b/doc/man/st-util.1 index 6796bda23..a7b2eb6cf 100644 --- a/doc/man/st-util.1 +++ b/doc/man/st-util.1 @@ -23,52 +23,57 @@ The STLinkV2 device to use can be specified in the environment variable STLINK_DEVICE on the format :. .SH OPTIONS .TP -.B \-h, \[en]help +.B \-h, \f[C]\-\-help\f[] Print this message. .RS .RE .TP -.B \[en]version +.B \f[C]\-\-version\f[] Print version information .RS .RE .TP -.B \-v \f[I]XX\f[], \[en]verbose=XX +.B \-v \f[I]XX\f[], \f[C]\-\-verbose=XX\f[] Specify a specific verbosity level (0..99) .RS .RE .TP -.B \-v, \[en]verbose +.B \-v, \f[C]\-\-verbose\f[] Specify generally verbose logging .RS .RE .TP -.B \-s \f[I]X\f[], \[en]stlink_version=X +.B \-s \f[I]X\f[], \f[C]\-\-stlink_version=X\f[] Choose what version of stlink to use, (defaults to 2) .RS .RE .TP -.B \-1, \[en]stlinkv1 +.B \-1, \f[C]\-\-stlinkv1\f[] Force stlink version 1 .RS .RE .TP -.B \-p \f[I]4242\f[], \[en]listen_port=1234 +.B \-p \f[I]4242\f[], \f[C]\-\-listen_port=1234\f[] Set the gdb server listen port. (default port: 4242) .RS .RE .TP -.B \-m, \[en]multi +.B \-m, \f[C]\-\-multi\f[] Set gdb server to extended mode. st\-util will continue listening for connections after disconnect. .RS .RE .TP -.B \-n, \[en]no\-reset +.B \-n, \f[C]\-\-no\-reset\f[] Do not reset board on connection. .RS .RE +.TP +.B \f[C]\-\-semihosting\f[] +Enable ARM Semihosting output on stdout +.RS +.RE .SH EXAMPLES .PP Run GDB server on port 4500 and connect to it diff --git a/doc/man/st-util.md b/doc/man/st-util.md index 325f84206..b141091f9 100644 --- a/doc/man/st-util.md +++ b/doc/man/st-util.md @@ -2,14 +2,13 @@ % % Feb 2018 - # NAME -st-util - Run GDB server to interact with STM32 device +st-util - Run GDB server to interact with STM32 device # SYNOPSIS -*st-util* \[\...] +*st-util* \[\...] # DESCRIPTION Start a GDB server to interact with a STM32 device @@ -23,49 +22,51 @@ Stlink version 2 is used by default unless the option **--stlinkv1** is given. The STLinkV2 device to use can be specified in the environment variable STLINK_DEVICE on the format :. - # OPTIONS --h, --help +-h, `--help` : Print this message. ---version +`--version` : Print version information --v *XX*, --verbose=XX +-v *XX*, `--verbose=XX` : Specify a specific verbosity level (0..99) --v, --verbose +-v, `--verbose` : Specify generally verbose logging --s *X*, --stlink_version=X +-s *X*, `--stlink_version=X` : Choose what version of stlink to use, (defaults to 2) --1, --stlinkv1 +-1, `--stlinkv1` : Force stlink version 1 --p *4242*, --listen_port=1234 +-p *4242*, `--listen_port=1234` : Set the gdb server listen port. (default port: 4242) --m, --multi +-m, `--multi` : Set gdb server to extended mode. st-util will continue listening for connections after disconnect. --n, --no-reset +-n, `--no-reset` : Do not reset board on connection. +`--semihosting` +: Enable ARM Semihosting output on stdout # EXAMPLES + Run GDB server on port 4500 and connect to it $ st-util -p 4500 $ gdb (gdb) target extended-remote localhost:4500 - # SEE ALSO -st-flash(1), st-info(1) +st-flash(1), st-info(1) # COPYRIGHT + This work is copyrighted. Stlink contributors. See *LICENSE* file in the stlink source distribution. From b69c1d51b03a4345c4d478ac1d8c2088002cd36a Mon Sep 17 00:00:00 2001 From: ZogFluff Date: Tue, 6 Mar 2018 12:38:44 -0800 Subject: [PATCH 0598/1435] fix serial name size mismatch with stlink_open_usb() (#680) --- src/usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/usb.c b/src/usb.c index 92a0a6ef4..dbacfee83 100644 --- a/src/usb.c +++ b/src/usb.c @@ -1002,7 +1002,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { continue; struct libusb_device_handle* handle; - char serial[13]; + char serial[16]; memset(serial, 0, sizeof(serial)); ret = libusb_open(dev, &handle); From e9fe4e51452133b1bd9a563a8f40953391bb2175 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Fri, 16 Mar 2018 15:41:07 +0000 Subject: [PATCH 0599/1435] Debian packaging, CMake and README.md fixes (#683) * Use https for debian/copyright * Update dates and fix stanzas in debian/copyright No need to have 2 stanzas for the same license * Add BSD-3-clause body in debian/copyright * Remove generated boilerplate from debian/rules * Enable compiler hardening flags in debian/rules * Fix source package name according to repo and docs * Set source package section to electronics See https://packages.debian.org/unstable/electronics/ for a full list * Add long descriptions to packages * Add gbp.conf file * Update changelog for 1.5.0 release * Remove dirs files, not needed anymore * Rename library package to match SONAME As per Debian policy, shared library packages must be named after their SONAME version. * libstlink0: break+replace libstlink since it took over its files * Remove triggers, not needed anymore debhelper tools will generate the triggers file automatically since the package name was corrected * List GPL2+ in debian/copyright for flashloaders * Do not append -shared to shared library on *NIX Only on Windows it's necessary to have different file names, on *NIX the extension is what disambiguates between a static library (.a) and a shared library (.so). * Clarify license of flashloaders in README.md Fixes #682 * List all individual authors in debian/copyright The Debian FTP masters nowadays require that all authors are listed in debian/copyright. Print the list of authors from git. * Move modprobe and udev files from shared library package to tools package Multiple versions of a shared library might be installed on the same system. Do not ship unversioned files in their packages, or they will conflict and fail to install. * stlink-tools: break+replace libstlink It took ownership of udev and modprobe files from libstlink * Fix pkgconfig include dir: remove project version The headers are installed in /usr/include/stlink without a version number. * Add libstlink1 symbols file Generated with: dpkg-gensymbols -P/tmp -v1.5.0 -V -e/tmp/libstlink.so.1.5.0 -plibstlink1 -Odebian/libstlink1.symbols * Bump Standards-Version to 4.1.3 Main changes are shared library rename and files moved, and HTTPS URLs. https://www.debian.org/doc/packaging-manuals/upgrading-checklist.txt * Add debian/watch file for notifications The Debian package tracker can automatically notify when a new version is out. --- CMakeLists.txt | 4 + README.md | 4 +- debian/changelog | 59 +++++++++++ debian/control | 49 ++++++--- debian/copyright | 174 +++++++++++++++++++++++++++++-- debian/gbp.conf | 7 ++ debian/libstlink-dev.dirs | 2 - debian/libstlink.dirs | 1 - debian/libstlink.install | 3 - debian/libstlink1.install | 1 + debian/libstlink1.symbols | 125 ++++++++++++++++++++++ debian/rules | 11 +- debian/stlink-gui.dirs | 2 - debian/stlink-tools.dirs | 2 - debian/stlink-tools.install | 2 + debian/triggers | 1 - debian/watch | 3 + usr/lib/pkgconfig/CMakeLists.txt | 2 +- 18 files changed, 407 insertions(+), 45 deletions(-) create mode 100644 debian/gbp.conf delete mode 100644 debian/libstlink-dev.dirs delete mode 100644 debian/libstlink.dirs delete mode 100644 debian/libstlink.install create mode 100644 debian/libstlink1.install create mode 100644 debian/libstlink1.symbols delete mode 100644 debian/stlink-gui.dirs delete mode 100644 debian/stlink-tools.dirs delete mode 100644 debian/triggers create mode 100644 debian/watch diff --git a/CMakeLists.txt b/CMakeLists.txt index d2be523bf..6ed84bd3e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -83,7 +83,11 @@ endif () ### # Shared library ### +if (NOT WIN32) +set(STLINK_LIB_SHARED ${PROJECT_NAME}) +else () set(STLINK_LIB_SHARED ${PROJECT_NAME}-shared) +endif() add_library(${STLINK_LIB_SHARED} SHARED ${STLINK_HEADERS} # header files for ide projects generated by cmake diff --git a/README.md b/README.md index 6e23356af..bdb2351a6 100644 --- a/README.md +++ b/README.md @@ -232,5 +232,5 @@ Issue related to this bug: [#545](https://github.com/texane/stlink/issues/545) ## License -The stlink library and tools are licensed under the [BSD license](LICENSE). With -some exceptions on external components (e.g flashloaders). +The stlink library and tools are licensed under the [BSD license](LICENSE). +The flashloaders/stm32l0x.s and flashloaders/stm32lx.s source files are licensed under the GPL-2+. diff --git a/debian/changelog b/debian/changelog index 0f3edb222..ac18fd872 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,62 @@ +stlink (1.5.0) unstable; urgency=medium + + [ Jerry Jacobs ] + * README.md: Update version badge to v1.4.0 + + [ Viallard Anthony ] + * Add support of STM32L496xx/4A6xx devices (#615) + + [ rdlim ] + * Fix verification of flash error for STM32L496x device (#617) (#618) + + [ dflogeras ] + * Add note about availability in Gentoo package manager (#622) + + [ yaofei zheng ] + * update debian package version (#630) + + [ Lyle Cheatham ] + * Minor formatting fix in FAQ section of README.md (#631) + + [ Vasiliy Glazov ] + * README.md: Added information about Fedora and RedHat/CentOS packages. + (#635) + * Added LIB_INSTALL_DIR to correct libs install on 64-bit systems (#636) + + [ Gwenhael Goavec-Merou ] + * fix write for microcontroler with RAM size less or equal to 32K (#637) + + [ Mateusz Krawiec ] + * Fix memory map for stm32l496xx boards. (#639) + + [ Rüdiger Fortanier ] + * Add unknown chip output (#641) + + [ Slyshyk Oleksiy ] + * fix __FILE__ base name extraction, #628 (#648) + + [ texane ] + * STM32F72xx73xx support, from bob.feretich@rafresearch.com + + [ Kirill Kolyshkin ] + * debian/triggers: add (to run ldconfig) (#664) + + [ Slyshyk Oleksiy ] + * Try to fix #666 issue (#667) + * Try to fix 666 issue (#668) + + [ Jerry Jacobs ] + * Update ChangeLog.md + * Update README.md + + [ texane ] + * STM32F042K6 Nucleo-32 Board reported to work, by frank@bauernoeppel.de + + [ Anatol Pomozov ] + * Update .version file to match release number (#670) + + -- Anatol Pomozov Mon, 19 Feb 2018 11:00:29 -0800 + libstlink (1.4.0) unstable; urgency=low * Major changes and added features diff --git a/debian/control b/debian/control index 41c8e87a3..e33fc757c 100644 --- a/debian/control +++ b/debian/control @@ -1,9 +1,9 @@ -Source: libstlink +Source: stlink Priority: optional Maintainer: Andrew 'Necromant' Andrianov Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev -Standards-Version: 3.9.5 -Section: libs +Standards-Version: 4.1.3 +Section: electronics Homepage: https://github.com/texane/stlink Vcs-Git: https://github.com/texane/stlink.git Vcs-Browser: https://github.com/texane/stlink @@ -11,24 +11,43 @@ Vcs-Browser: https://github.com/texane/stlink Package: libstlink-dev Section: libdevel Architecture: any -Depends: libstlink (= ${binary:Version}), ${misc:Depends} -Description: OpenSource ST-Link tools replacement. Development headers. - This package contains development headers for libstlink. +Depends: libstlink1 (= ${binary:Version}), ${misc:Depends} +Description: OpenSource ST-Link tools replacement. + Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers + STLINKv1 and STLINKv2 are supported. + . + This package contains the development files for stlink. -Package: libstlink +Package: libstlink1 +Section: libs Architecture: any Depends: ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. Shared library. - This package libstlink shared library. +Breaks: libstlink +Replaces: libstlink +Description: OpenSource ST-Link tools replacement. + Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers + STLINKv1 and STLINKv2 are supported. + . + This package contains the shared library for stlink. Package: stlink-tools -Section: libdevel Architecture: any -Depends: libstlink (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. Commandline Utilities. +Depends: libstlink1 (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} +Breaks: libstlink +Replaces: libstlink +Description: OpenSource ST-Link tools replacement. + Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers + STLINKv1 and STLINKv2 are supported. + . + This package contains commandline utilities for stlink, and modprobe and + udev rules. Package: stlink-gui -Section: libdevel Architecture: any -Depends: libstlink (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. GUI Tool. +Depends: libstlink1 (= ${binary:Version}), stlink-tools (= ${binary:Version}), + ${shlibs:Depends}, ${misc:Depends} +Description: OpenSource ST-Link tools replacement. + Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers + STLINKv1 and STLINKv2 are supported. + . + This package contains a GUI tool for stlink. diff --git a/debian/copyright b/debian/copyright index e28d7e1bb..941a4a011 100644 --- a/debian/copyright +++ b/debian/copyright @@ -1,12 +1,174 @@ -Format: http://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ -Upstream-Name: libstlink +Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ +Upstream-Name: stlink Upstream-Contact: Andrew 'Necromant' Andrianov Source: https://github.com/texane/stlink Files: * -Copyright: (c) 2011 The stlink project (github.com/texane/stlink) contributors. +Copyright: 2011-2018 agpanarin + 2011-2018 Alexey Cherevatenko + 2011-2018 Anatoli + 2011-2018 Andrea Mucignat + 2011-2018 Andrew 'Necromant' Andrianov + 2011-2018 Andrey Yurovsky + 2011-2018 Andy Isaacson + 2011-2018 Áron RADICS + 2011-2018 A Sheaff + 2011-2018 Björn Hauffe + 2011-2018 bob + 2011-2018 Breton M. Saunders + 2011-2018 Bruno Dal Bo + 2011-2018 Burns + 2011-2018 Chris Dew + 2011-2018 Chris Hiszpanski + 2011-2018 Chris Li + 2011-2018 Chris Samuelson + 2011-2018 Christophe Levantis + 2011-2018 Craig Lilley + 2011-2018 dandev37 + 2011-2018 Dan Hepler + 2011-2018 Daniel Campoverde [alx741] + 2011-2018 Daniel O'Connor + 2011-2018 Dave Flogeras + 2011-2018 Dave Murphy + 2011-2018 Dave Vandervies + 2011-2018 Denis Fokin + 2011-2018 Denis Osterland + 2011-2018 Dmitry Bravikov + 2011-2018 Efe Can İçöz + 2011-2018 Ethan Zonca + 2011-2018 Fabien Chouteau + 2011-2018 Fabien Le Mentec + 2011-2018 fhars + 2011-2018 Friedrich Beckmann + 2011-2018 Geoffrey Brown + 2011-2018 George Talusan + 2011-2018 Georg von Zengen + 2011-2018 giuseppe barba + 2011-2018 Greg Alexander + 2011-2018 Greg Meiste + 2011-2018 Hakkavélin + 2011-2018 htk + 2011-2018 Ian Griffiths <6thimage@gmail.com> + 2011-2018 Jack Peel + 2011-2018 Jakub Tyszkowski + 2011-2018 Jan Sarenik + 2011-2018 Jean-Luc Béchennec + 2011-2018 Jean-Marie Lemetayer + 2011-2018 Jeff Kent + 2011-2018 Jeffrey Nelson + 2011-2018 Jens Hoffmann + 2011-2018 Jerome Lambourg + 2011-2018 Jerry Jacobs + 2011-2018 Jim Paris + 2011-2018 Jiří Netolický + 2011-2018 jnosky + 2011-2018 jnosky + 2011-2018 JohannesTaelman + 2011-2018 Jonas Danielsson + 2011-2018 Jonas Norling + 2011-2018 Josh Bialkowski + 2011-2018 Karl Palsson + 2011-2018 kevin + 2011-2018 Kyle Manna + 2011-2018 Lari Lehtomäki + 2011-2018 le mentec fabien + 2011-2018 Martin Nowak + 2011-2018 Matteo Collina + 2011-2018 Max Chen + 2011-2018 Maxime Coquelin + 2011-2018 Maxime Vincent + 2011-2018 Michael Pratt + 2011-2018 Michael Sparmann + 2011-2018 Mike Szczys + 2011-2018 mlundinse + 2011-2018 mux + 2011-2018 Ned Konz + 2011-2018 Nic McDonald + 2011-2018 Nicolas Schodet + 2011-2018 Nikolay + 2011-2018 nullsub + 2011-2018 Olivier Croquette + 2011-2018 Olivier Gay + 2011-2018 Onno Kortmann + 2011-2018 orangeudav + 2011-2018 Pavel Kirienko + 2011-2018 Pekka Nikander + 2011-2018 Pete + 2011-2018 Peter Zotov + 2011-2018 Petteri Aimonen + 2011-2018 Piotr Haber + 2011-2018 Rene Hopf + 2011-2018 Robin Kreis + 2011-2018 Rob Spanton + 2011-2018 Rytis Karpuska + 2011-2018 Sean Simmons + 2011-2018 Sergey Alirzaev + 2011-2018 Simon Wright + 2011-2018 Stany MARCEL + 2011-2018 Stefan Misik + 2011-2018 Sven Wegener + 2011-2018 Tectu + 2011-2018 tekaikko + 2011-2018 texane + 2011-2018 Theodore A. Roth + 2011-2018 Thomas Gärtner + 2011-2018 Tobias Badertscher + 2011-2018 Tom de Boer + 2011-2018 Tristan Gingold + 2011-2018 Uli Köhler + 2011-2018 Uwe Bonnes + 2011-2018 Vadim Kaushan + 2011-2018 Vegard Storheil Eriksen + 2011-2018 Viacheslav Dobromyslov + 2011-2018 Victor Mayoral Vilches + 2011-2018 Wojciech A. Koszek + 2011-2018 Woodrow Douglass + 2011-2018 The "Capt'ns Missing Link" Authors. License: BSD-3-clause + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + . + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of Intel Corporation nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + . + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -Files: * -Copyright: (c) 2011 The "Capt'ns Missing Link" Authors. All rights reserved. -License: BSD-3-clause +Files: flashloaders/stm32l0x.s + flashloaders/stm32lx.s +Copyright: 2010 Spencer Oliver + 2011 Øyvind Harboe + 2011 Clement Burin des Roziers +License: GPL-2+ + This package is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + . + This package is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + . + You should have received a copy of the GNU General Public License + along with this program. If not, see + . + On Debian systems, the complete text of the GNU General + Public License version 2 can be found in "/usr/share/common-licenses/GPL-2". diff --git a/debian/gbp.conf b/debian/gbp.conf new file mode 100644 index 000000000..418e536e9 --- /dev/null +++ b/debian/gbp.conf @@ -0,0 +1,7 @@ +[buildpackage] +upstream-tag = %(version)s +debian-branch = debian + +[dch] +git-log = --first-parent +customizations = /usr/share/doc/git-buildpackage/examples/wrap_cl.py diff --git a/debian/libstlink-dev.dirs b/debian/libstlink-dev.dirs deleted file mode 100644 index 44188162e..000000000 --- a/debian/libstlink-dev.dirs +++ /dev/null @@ -1,2 +0,0 @@ -usr/lib -usr/include diff --git a/debian/libstlink.dirs b/debian/libstlink.dirs deleted file mode 100644 index 68457717b..000000000 --- a/debian/libstlink.dirs +++ /dev/null @@ -1 +0,0 @@ -usr/lib diff --git a/debian/libstlink.install b/debian/libstlink.install deleted file mode 100644 index 08981406e..000000000 --- a/debian/libstlink.install +++ /dev/null @@ -1,3 +0,0 @@ -usr/lib/*/lib*.so.* -lib/udev/rules.d/*.rules -etc/modprobe.d/*.conf diff --git a/debian/libstlink1.install b/debian/libstlink1.install new file mode 100644 index 000000000..3ddde5841 --- /dev/null +++ b/debian/libstlink1.install @@ -0,0 +1 @@ +usr/lib/*/lib*.so.* diff --git a/debian/libstlink1.symbols b/debian/libstlink1.symbols new file mode 100644 index 000000000..51fa9bdb1 --- /dev/null +++ b/debian/libstlink1.symbols @@ -0,0 +1,125 @@ +libstlink.so.1 libstlink1 #MINVER# + _parse_version@Base 1.5.0 + _stlink_sg_close@Base 1.5.0 + _stlink_sg_core_id@Base 1.5.0 + _stlink_sg_current_mode@Base 1.5.0 + _stlink_sg_enter_jtag_mode@Base 1.5.0 + _stlink_sg_enter_swd_mode@Base 1.5.0 + _stlink_sg_exit_debug_mode@Base 1.5.0 + _stlink_sg_exit_dfu_mode@Base 1.5.0 + _stlink_sg_force_debug@Base 1.5.0 + _stlink_sg_jtag_reset@Base 1.5.0 + _stlink_sg_read_all_regs@Base 1.5.0 + _stlink_sg_read_debug32@Base 1.5.0 + _stlink_sg_read_mem32@Base 1.5.0 + _stlink_sg_read_reg@Base 1.5.0 + _stlink_sg_reset@Base 1.5.0 + _stlink_sg_run@Base 1.5.0 + _stlink_sg_status@Base 1.5.0 + _stlink_sg_step@Base 1.5.0 + _stlink_sg_version@Base 1.5.0 + _stlink_sg_write_debug32@Base 1.5.0 + _stlink_sg_write_mem32@Base 1.5.0 + _stlink_sg_write_mem8@Base 1.5.0 + _stlink_sg_write_reg@Base 1.5.0 + _stlink_usb_close@Base 1.5.0 + _stlink_usb_core_id@Base 1.5.0 + _stlink_usb_current_mode@Base 1.5.0 + _stlink_usb_enter_swd_mode@Base 1.5.0 + _stlink_usb_exit_debug_mode@Base 1.5.0 + _stlink_usb_exit_dfu_mode@Base 1.5.0 + _stlink_usb_force_debug@Base 1.5.0 + _stlink_usb_jtag_reset@Base 1.5.0 + _stlink_usb_read_all_regs@Base 1.5.0 + _stlink_usb_read_all_unsupported_regs@Base 1.5.0 + _stlink_usb_read_debug32@Base 1.5.0 + _stlink_usb_read_mem32@Base 1.5.0 + _stlink_usb_read_reg@Base 1.5.0 + _stlink_usb_read_unsupported_reg@Base 1.5.0 + _stlink_usb_reset@Base 1.5.0 + _stlink_usb_run@Base 1.5.0 + _stlink_usb_set_swdclk@Base 1.5.0 + _stlink_usb_status@Base 1.5.0 + _stlink_usb_step@Base 1.5.0 + _stlink_usb_target_voltage@Base 1.5.0 + _stlink_usb_version@Base 1.5.0 + _stlink_usb_write_debug32@Base 1.5.0 + _stlink_usb_write_mem32@Base 1.5.0 + _stlink_usb_write_mem8@Base 1.5.0 + _stlink_usb_write_reg@Base 1.5.0 + _stlink_usb_write_unsupported_reg@Base 1.5.0 + calculate_F4_sectornum@Base 1.5.0 + calculate_F7_sectornum@Base 1.5.0 + calculate_L4_page@Base 1.5.0 + is_bigendian@Base 1.5.0 + read_uint16@Base 1.5.0 + read_uint32@Base 1.5.0 + send_recv@Base 1.5.0 + send_usb_data_only@Base 1.5.0 + send_usb_mass_storage_command@Base 1.5.0 + stlink_calculate_pagesize@Base 1.5.0 + stlink_chip_id@Base 1.5.0 + stlink_chipid_get_params@Base 1.5.0 + stlink_close@Base 1.5.0 + stlink_clr_hw_bp@Base 1.5.0 + stlink_core_id@Base 1.5.0 + stlink_core_stat@Base 1.5.0 + stlink_cpu_id@Base 1.5.0 + stlink_current_mode@Base 1.5.0 + stlink_enter_swd_mode@Base 1.5.0 + stlink_erase_flash_mass@Base 1.5.0 + stlink_erase_flash_page@Base 1.5.0 + stlink_exit_debug_mode@Base 1.5.0 + stlink_exit_dfu_mode@Base 1.5.0 + stlink_fcheck_flash@Base 1.5.0 + stlink_flash_loader_init@Base 1.5.0 + stlink_flash_loader_run@Base 1.5.0 + stlink_flash_loader_write_to_sram@Base 1.5.0 + stlink_force_debug@Base 1.5.0 + stlink_fread@Base 1.5.0 + stlink_fwrite_flash@Base 1.5.0 + stlink_fwrite_sram@Base 1.5.0 + stlink_get_erased_pattern@Base 1.5.0 + stlink_is_core_halted@Base 1.5.0 + stlink_jtag_reset@Base 1.5.0 + stlink_load_device_params@Base 1.5.0 + stlink_mwrite_flash@Base 1.5.0 + stlink_mwrite_sram@Base 1.5.0 + stlink_open_usb@Base 1.5.0 + stlink_parse_ihex@Base 1.5.0 + stlink_print_data@Base 1.5.0 + stlink_probe_usb@Base 1.5.0 + stlink_probe_usb_free@Base 1.5.0 + stlink_q@Base 1.5.0 + stlink_read_all_regs@Base 1.5.0 + stlink_read_all_unsupported_regs@Base 1.5.0 + stlink_read_debug32@Base 1.5.0 + stlink_read_mem32@Base 1.5.0 + stlink_read_reg@Base 1.5.0 + stlink_read_unsupported_reg@Base 1.5.0 + stlink_reset@Base 1.5.0 + stlink_run@Base 1.5.0 + stlink_run_at@Base 1.5.0 + stlink_set_hw_bp@Base 1.5.0 + stlink_set_swdclk@Base 1.5.0 + stlink_stat@Base 1.5.0 + stlink_status@Base 1.5.0 + stlink_step@Base 1.5.0 + stlink_target_voltage@Base 1.5.0 + stlink_v1_open@Base 1.5.0 + stlink_v1_open_inner@Base 1.5.0 + stlink_verify_write_flash@Base 1.5.0 + stlink_version@Base 1.5.0 + stlink_write_debug32@Base 1.5.0 + stlink_write_dreg@Base 1.5.0 + stlink_write_flash@Base 1.5.0 + stlink_write_mem32@Base 1.5.0 + stlink_write_mem8@Base 1.5.0 + stlink_write_reg@Base 1.5.0 + stlink_write_unsupported_reg@Base 1.5.0 + stm32l1_write_half_pages@Base 1.5.0 + ugly_init@Base 1.5.0 + ugly_log@Base 1.5.0 + write_buffer_to_sram@Base 1.5.0 + write_uint16@Base 1.5.0 + write_uint32@Base 1.5.0 diff --git a/debian/rules b/debian/rules index 2ff7e59a8..c4e9e2afd 100755 --- a/debian/rules +++ b/debian/rules @@ -8,20 +8,11 @@ DPKG_EXPORT_BUILDFLAGS = 1 include /usr/share/dpkg/default.mk # see FEATURE AREAS in dpkg-buildflags(1) -#export DEB_BUILD_MAINT_OPTIONS = hardening=+all +export DEB_BUILD_MAINT_OPTIONS = hardening=+all -# see ENVIRONMENT in dpkg-buildflags(1) -# package maintainers to append CFLAGS -#export DEB_CFLAGS_MAINT_APPEND = -Wall -pedantic -# package maintainers to append LDFLAGS -#export DEB_LDFLAGS_MAINT_APPEND = -Wl,--as-needed - -# main packaging script based on dh7 syntax %: dh $@ --buildsystem cmake -# debmake generated override targets -# This is example for Cmake (See http://bugs.debian.org/641051 ) override_dh_auto_configure: dh_auto_configure -- \ -DCMAKE_LIBRARY_PATH=$(DEB_HOST_MULTIARCH) \ diff --git a/debian/stlink-gui.dirs b/debian/stlink-gui.dirs deleted file mode 100644 index d080ed407..000000000 --- a/debian/stlink-gui.dirs +++ /dev/null @@ -1,2 +0,0 @@ -/usr/bin -/usr/share/ diff --git a/debian/stlink-tools.dirs b/debian/stlink-tools.dirs deleted file mode 100644 index 377c76613..000000000 --- a/debian/stlink-tools.dirs +++ /dev/null @@ -1,2 +0,0 @@ -/usr/bin - diff --git a/debian/stlink-tools.install b/debian/stlink-tools.install index 4fa1125bf..ca875a0e6 100644 --- a/debian/stlink-tools.install +++ b/debian/stlink-tools.install @@ -1 +1,3 @@ /usr/bin/st-* +lib/udev/rules.d/*.rules +etc/modprobe.d/*.conf diff --git a/debian/triggers b/debian/triggers deleted file mode 100644 index dd8660367..000000000 --- a/debian/triggers +++ /dev/null @@ -1 +0,0 @@ -activate-noawait ldconfig diff --git a/debian/watch b/debian/watch new file mode 100644 index 000000000..cc653ca9f --- /dev/null +++ b/debian/watch @@ -0,0 +1,3 @@ +version=3 +opts=filenamemangle=s/.+\/v?(\d\S+)\.tar\.gz/-$1\.tar\.gz/ \ + https://github.com/texane/stlink/tags .*/v?(\d\S+)\.tar\.gz diff --git a/usr/lib/pkgconfig/CMakeLists.txt b/usr/lib/pkgconfig/CMakeLists.txt index 1d7bcd1dc..a656ff623 100644 --- a/usr/lib/pkgconfig/CMakeLists.txt +++ b/usr/lib/pkgconfig/CMakeLists.txt @@ -1,5 +1,5 @@ set(PKG_CONFIG_LIBDIR "\${prefix}/lib/\${deb_host_multiarch}") -set(PKG_CONFIG_INCLUDEDIR "\${prefix}/include/\${deb_host_multiarch}/${PROJECT_NAME}-${PROJECT_VERSION}") +set(PKG_CONFIG_INCLUDEDIR "\${prefix}/include/\${deb_host_multiarch}/${PROJECT_NAME}") set(PKG_CONFIG_LIBS "-L\${libdir} -l:libstlink.so.${PROJECT_VERSION_MAJOR}") set(PKG_CONFIG_CFLAGS "-I\${includedir}") set(PKG_CONFIG_REQUIRES "libusb-1.0") From 64ef6a8a237d438ecfb3c92d92be0fba84af4e3a Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Tue, 13 Mar 2018 00:27:55 +0000 Subject: [PATCH 0600/1435] Change format to non-native, set myself as maintainer --- debian/changelog | 6 ++++++ debian/control | 6 +++--- debian/source/format | 2 +- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/debian/changelog b/debian/changelog index ac18fd872..d55b32837 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,9 @@ +stlink (1.5.0-1) UNRELEASED; urgency=medium + + * Upload to unstable. (Closes: #869421) + + -- Luca Boccassi Tue, 13 Mar 2018 00:26:52 +0000 + stlink (1.5.0) unstable; urgency=medium [ Jerry Jacobs ] diff --git a/debian/control b/debian/control index e33fc757c..db6f9e7e0 100644 --- a/debian/control +++ b/debian/control @@ -1,12 +1,12 @@ Source: stlink Priority: optional -Maintainer: Andrew 'Necromant' Andrianov +Maintainer: Luca Boccassi Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.1.3 Section: electronics Homepage: https://github.com/texane/stlink -Vcs-Git: https://github.com/texane/stlink.git -Vcs-Browser: https://github.com/texane/stlink +Vcs-Git: https://github.com/bluca/stlink.git +Vcs-Browser: https://github.com/bluca/stlink Package: libstlink-dev Section: libdevel diff --git a/debian/source/format b/debian/source/format index 89ae9db8f..163aaf8d8 100644 --- a/debian/source/format +++ b/debian/source/format @@ -1 +1 @@ -3.0 (native) +3.0 (quilt) From 848839034573498ed80e3290e119e1fcaa031dcc Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Fri, 16 Mar 2018 16:13:53 +0000 Subject: [PATCH 0601/1435] Repack tarball to remove debian/ and stlinkv1_macosx_driver/ --- debian/changelog | 2 +- debian/copyright | 5 +++++ debian/watch | 2 +- 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/debian/changelog b/debian/changelog index d55b32837..3439e586c 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,4 +1,4 @@ -stlink (1.5.0-1) UNRELEASED; urgency=medium +stlink (1.5.0+ds-1) UNRELEASED; urgency=medium * Upload to unstable. (Closes: #869421) diff --git a/debian/copyright b/debian/copyright index 941a4a011..d56807ca5 100644 --- a/debian/copyright +++ b/debian/copyright @@ -2,6 +2,11 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink Upstream-Contact: Andrew 'Necromant' Andrianov Source: https://github.com/texane/stlink +Comment: Upstream tarball has been repackaged to remove binary OSX kernel + drivers that are of unknown license and of no use to Debian. + Upstream's debian directory is also removed. +Files-Excluded: stlinkv1_macosx_driver + debian Files: * Copyright: 2011-2018 agpanarin diff --git a/debian/watch b/debian/watch index cc653ca9f..921dc8f0d 100644 --- a/debian/watch +++ b/debian/watch @@ -1,3 +1,3 @@ version=3 -opts=filenamemangle=s/.+\/v?(\d\S+)\.tar\.gz/-$1\.tar\.gz/ \ +opts=dversionmangle=s/\+ds$//,repacksuffix=+ds,filenamemangle=s/.+\/v?(\d\S+)\.tar\.gz/-$1\.tar\.gz/ \ https://github.com/texane/stlink/tags .*/v?(\d\S+)\.tar\.gz From abdf4ce070b01586d82740922e86a16bb0206ba5 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Fri, 16 Mar 2018 16:20:26 +0000 Subject: [PATCH 0602/1435] Remove breaks and replaces, not applicable to Debian --- debian/control | 4 ---- 1 file changed, 4 deletions(-) diff --git a/debian/control b/debian/control index db6f9e7e0..3427359c6 100644 --- a/debian/control +++ b/debian/control @@ -22,8 +22,6 @@ Package: libstlink1 Section: libs Architecture: any Depends: ${shlibs:Depends}, ${misc:Depends} -Breaks: libstlink -Replaces: libstlink Description: OpenSource ST-Link tools replacement. Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers STLINKv1 and STLINKv2 are supported. @@ -33,8 +31,6 @@ Description: OpenSource ST-Link tools replacement. Package: stlink-tools Architecture: any Depends: libstlink1 (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} -Breaks: libstlink -Replaces: libstlink Description: OpenSource ST-Link tools replacement. Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers STLINKv1 and STLINKv2 are supported. From ef9d527eb74231d1818ade3495f003b85bec5325 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Fri, 16 Mar 2018 16:56:19 +0000 Subject: [PATCH 0603/1435] Update changelog for 1.5.0+ds-1 release --- debian/changelog | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/debian/changelog b/debian/changelog index 3439e586c..798093c9e 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,8 +1,8 @@ -stlink (1.5.0+ds-1) UNRELEASED; urgency=medium +stlink (1.5.0+ds-1) unstable; urgency=medium * Upload to unstable. (Closes: #869421) - -- Luca Boccassi Tue, 13 Mar 2018 00:26:52 +0000 + -- Luca Boccassi Fri, 16 Mar 2018 16:56:17 +0000 stlink (1.5.0) unstable; urgency=medium From 334fde7648402ffc7c869a9bebe606826a323506 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Boudinet?= Date: Mon, 26 Mar 2018 13:11:23 +0200 Subject: [PATCH 0604/1435] gui: Adding button to export stm32 flash memory to a file (#691) --- src/tools/gui/stlink-gui.c | 53 +++++++++++++++++++++++++++++++++++++ src/tools/gui/stlink-gui.h | 2 ++ src/tools/gui/stlink-gui.ui | 14 ++++++++++ 3 files changed, 69 insertions(+) diff --git a/src/tools/gui/stlink-gui.c b/src/tools/gui/stlink-gui.c index 34afb2c51..2be97ef10 100644 --- a/src/tools/gui/stlink-gui.c +++ b/src/tools/gui/stlink-gui.c @@ -92,6 +92,8 @@ stlink_gui_set_sensitivity (STlinkGUI *gui, gboolean sensitivity) if (sensitivity && gui->sl && gui->filename) gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), sensitivity); + + gtk_widget_set_sensitive (GTK_WIDGET (gui->export_button), sensitivity && (gui->sl != NULL)); } static void @@ -575,6 +577,7 @@ static void stlink_gui_set_disconnected (STlinkGUI *gui) gtk_widget_set_sensitive (GTK_WIDGET (gui->device_frame), FALSE); gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), FALSE); + gtk_widget_set_sensitive (GTK_WIDGET (gui->export_button), FALSE); gtk_widget_set_sensitive (GTK_WIDGET (gui->disconnect_button), FALSE); gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), TRUE); } @@ -712,6 +715,51 @@ flash_button_cb (GtkWidget *widget, gpointer data) } } +int export_to_file(const char*filename, const struct mem_t flash_mem) +{ + printf("%s\n", filename); + FILE * f=fopen(filename, "w"); + if(f==NULL) + return -1; + for(gsize i=0;iwindow, + GTK_FILE_CHOOSER_ACTION_SAVE, + "_Cancel", + GTK_RESPONSE_CANCEL, + "_Open", + GTK_RESPONSE_ACCEPT, + NULL); + GtkFileChooser *chooser = GTK_FILE_CHOOSER (dialog); + gtk_file_chooser_set_do_overwrite_confirmation (chooser, TRUE); + gint res = gtk_dialog_run (GTK_DIALOG (dialog)); + if (res == GTK_RESPONSE_ACCEPT) + { + char *filename; + + filename = gtk_file_chooser_get_filename (chooser); + if(export_to_file (filename, gui->flash_mem)!=0) + stlink_gui_set_info_error_message(gui, "Failed to export flash"); + else + stlink_gui_set_info_error_message(gui, "Export successful"); + g_free (filename); + } + + gtk_widget_destroy (dialog); +} + static gboolean progress_pulse_timeout (STlinkGUI *gui) { if (gui->progress.activity_mode) { @@ -857,6 +905,11 @@ stlink_gui_build_ui (STlinkGUI *gui) { g_signal_connect (G_OBJECT (gui->flash_button), "clicked", G_CALLBACK (flash_button_cb), gui); + gui->export_button = + GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "export_button")); + g_signal_connect (G_OBJECT (gui->export_button), "clicked", + G_CALLBACK (export_button_cb), gui); + gui->devmem_treeview = GTK_TREE_VIEW (gtk_builder_get_object (builder, "devmem_treeview")); mem_view_init_headers (gui->devmem_treeview); diff --git a/src/tools/gui/stlink-gui.h b/src/tools/gui/stlink-gui.h index 0c90648a4..30c503fd3 100644 --- a/src/tools/gui/stlink-gui.h +++ b/src/tools/gui/stlink-gui.h @@ -64,6 +64,7 @@ struct _STlinkGUI GtkToolButton *connect_button; GtkToolButton *disconnect_button; GtkToolButton *flash_button; + GtkToolButton *export_button; GtkToolButton *open_button; /* flash dialog */ @@ -89,5 +90,6 @@ struct _STlinkGUIClass }; GType stlink_gui_get_type (void); +int export_to_file(const char*filename, const struct mem_t flash_mem); #endif diff --git a/src/tools/gui/stlink-gui.ui b/src/tools/gui/stlink-gui.ui index 193925ce1..aa0051b07 100644 --- a/src/tools/gui/stlink-gui.ui +++ b/src/tools/gui/stlink-gui.ui @@ -173,6 +173,20 @@ True + + + True + False + Export device memory + __glade_unnamed_9 + True + gtk-save + + + False + True + + True From 389fda244385a60fe26aac9922750b66d88add06 Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Wed, 28 Mar 2018 10:49:14 +0300 Subject: [PATCH 0605/1435] Update libusb to v1.0.22 (#695) * Will not download libusb if it found. * Checking CMAKE_LIBRARY_PATH before setting as STLINK_LIBRARY_PATH. --- CMakeLists.txt | 17 +++++++- cmake/modules/FindLibUSB.cmake | 77 +++++++++++++++++++++++----------- 2 files changed, 67 insertions(+), 27 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 6ed84bd3e..d844183d6 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -5,7 +5,17 @@ set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics Stlink To set(STLINK_UDEV_RULES_DIR "/etc/udev/rules.d" CACHE PATH "Udev rules directory") set(STLINK_MODPROBED_DIR "/etc/modprobe.d" CACHE PATH "modprobe.d directory") set(LIB_INSTALL_DIR "lib" CACHE PATH "Main library directory") -set(STLINK_LIBRARY_PATH "${LIB_INSTALL_DIR}/${CMAKE_LIBRARY_PATH}" CACHE PATH "Target lib directory") + +if(IS_DIRECTORY CMAKE_LIBRARY_PATH) +else() + set(CMAKE_LIBRARY_PATH "lib") +endif() + +if (WIN32) + set(STLINK_LIBRARY_PATH ${CMAKE_LIBRARY_PATH} CACHE PATH "Target lib directory") +else() + set(STLINK_LIBRARY_PATH "${LIB_INSTALL_DIR}/${CMAKE_LIBRARY_PATH}" CACHE PATH "Target lib directory") +endif(WIN32) option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) @@ -16,7 +26,9 @@ endif () set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") include(cmake/Version.cmake) -include(cmake/CFlags.cmake) +if(NOT MSVC) + include(cmake/CFlags.cmake) +endif() ### # Dependencies @@ -120,6 +132,7 @@ else() target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY}) endif() + install(TARGETS ${STLINK_LIB_SHARED} DESTINATION ${STLINK_LIBRARY_PATH} ) diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index 844f3dc54..e9a5944f6 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -6,27 +6,6 @@ # LIBUSB_LIBRARY - The libraries needed to use libusb # LIBUSB_DEFINITIONS - Compiler switches required for using libusb -if(WIN32 OR CMAKE_VS_PLATFORM_NAME OR MINGW OR MSYS) - find_package(7Zip REQUIRED) - - set(LIBUSB_WIN_VERSION 1.0.21) - set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) - set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) - set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/3thparty/libusb-${LIBUSB_WIN_VERSION}) - - if(EXISTS ${LIBUSB_WIN_ARCHIVE_PATH}) - message(STATUS "libusb archive already in build folder") - else() - message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") - file(DOWNLOAD - https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download - ${LIBUSB_WIN_ARCHIVE_PATH} - ) - endif() - file(MAKE_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) - execute_process(COMMAND ${ZIP_EXECUTABLE} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o${LIBUSB_WIN_OUTPUT_FOLDER}) -endif() - # FreeBSD if (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h @@ -39,7 +18,6 @@ else () /usr /usr/local /opt - ${LIBUSB_WIN_OUTPUT_FOLDER}/include PATH_SUFFIXES libusb-1.0 ) endif() @@ -48,7 +26,7 @@ if (APPLE) set(LIBUSB_NAME libusb-1.0.a) elseif(MSYS OR MINGW) set(LIBUSB_NAME usb-1.0) -elseif(WIN32 OR CMAKE_VS_PLATFORM_NAME) +elseif(MSVC) set(LIBUSB_NAME libusb-1.0.lib) elseif(CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") set(LIBUSB_NAME usb) @@ -64,10 +42,10 @@ if (MSYS OR MINGW) find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW32/static) endif () -elseif(CMAKE_VS_PLATFORM_NAME) +elseif(MSVC) if (CMAKE_SIZEOF_VOID_P EQUAL 8) find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS64/dll) + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS64/dll) else () find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS32/dll) @@ -84,3 +62,52 @@ include(FindPackageHandleStandardArgs) FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) + +if(NOT LIBUSB_FOUND) + if(WIN32 OR MSVC OR MINGW OR MSYS) + find_package(7Zip REQUIRED) + + set(LIBUSB_WIN_VERSION 1.0.22) + set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) + set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) + set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/3thparty/libusb-${LIBUSB_WIN_VERSION}) + + if(EXISTS ${LIBUSB_WIN_ARCHIVE_PATH}) + message(STATUS "libusb archive already in build folder") + else() + message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") + file(DOWNLOAD + https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download + ${LIBUSB_WIN_ARCHIVE_PATH} + ) + endif() + file(MAKE_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) + execute_process(COMMAND ${ZIP_EXECUTABLE} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o${LIBUSB_WIN_OUTPUT_FOLDER}) + + FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/include + PATH_SUFFIXES libusb-1.0 + ) + + if (MSYS OR MINGW) + if (CMAKE_SIZEOF_VOID_P EQUAL 8) + find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/static) + else () + find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW32/static) + endif () + elseif(MSVC) + if (CMAKE_SIZEOF_VOID_P EQUAL 8) + find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS64/dll) + else () + find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS32/dll) + endif () + endif () + FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + endif() +else() + message(STATUS "found USB") +endif() From 2ee6edc9ae0f3d16a43b8609e4565a30dd94d0c3 Mon Sep 17 00:00:00 2001 From: Vasiliy Glazov Date: Wed, 28 Mar 2018 10:54:40 +0300 Subject: [PATCH 0606/1435] Add desktop file for linux gtk GUI application (#688) * Add desktop file for linux * installing desktop file to /usr/../share/applications * Move desktop file to gui subdirectory. --- CMakeLists.txt | 2 ++ src/tools/gui/stlink.desktop | 9 +++++++++ 2 files changed, 11 insertions(+) create mode 100644 src/tools/gui/stlink.desktop diff --git a/CMakeLists.txt b/CMakeLists.txt index d844183d6..c4f4e217c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -194,6 +194,8 @@ if (CMAKE_SYSTEM_NAME STREQUAL "Linux") DESTINATION ${STLINK_MODPROBED_DIR}/) install(FILES ${RULES_FILES} DESTINATION ${STLINK_UDEV_RULES_DIR}/) + #desktop file for linux launcher + install(FILES src/tools/gui/stlink.desktop DESTINATION ${CMAKE_INSTALL_PREFIX}/share/applications) endif() add_subdirectory(src/gdbserver) diff --git a/src/tools/gui/stlink.desktop b/src/tools/gui/stlink.desktop new file mode 100644 index 000000000..54cb40349 --- /dev/null +++ b/src/tools/gui/stlink.desktop @@ -0,0 +1,9 @@ +[Desktop Entry] +Name=stlink +GenericName=Stlink Tools +Comment=STM32 discovery line Linux programmer +Exec=stlink-gui +Icon=stlink-gui +Terminal=false +Type=Application +Categories=Development;Electronics; From 7ec1fb78baaa3d4bd7b36cc042248e24d5f481fe Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Wed, 28 Mar 2018 11:03:38 +0300 Subject: [PATCH 0607/1435] remove exit() from lib. fix #634 (#696) * remove exit() from lib. fix #634 * remove the UFATAL loglevel completely. --- include/stlink/logging.h | 11 ++++------- src/logging.c | 6 ------ 2 files changed, 4 insertions(+), 13 deletions(-) diff --git a/include/stlink/logging.h b/include/stlink/logging.h index a6632a730..16ed948a4 100644 --- a/include/stlink/logging.h +++ b/include/stlink/logging.h @@ -10,11 +10,10 @@ extern "C" { #endif enum ugly_loglevel { - UDEBUG = 90, - UINFO = 50, - UWARN = 30, - UERROR = 20, - UFATAL = 10 + UDEBUG = 90, + UINFO = 50, + UWARN = 30, + UERROR = 20 }; int ugly_init(int maximum_threshold); @@ -33,8 +32,6 @@ int ugly_log(int level, const char *tag, const char *format, ...); #define WLOG(...) WLOG_HELPER(__VA_ARGS__, "") #define ELOG_HELPER(format, ...) ugly_log(UERROR, UGLY_LOG_FILE, format, __VA_ARGS__) #define ELOG(...) ELOG_HELPER(__VA_ARGS__, "") -#define fatal_helper(format, ...) ugly_log(UFATAL, UGLY_LOG_FILE, format, __VA_ARGS__) -#define fatal(...) fatal_helper(__VA_ARGS__, "") #ifdef __cplusplus } diff --git a/src/logging.c b/src/logging.c index 1f51900b5..b5e423a3a 100644 --- a/src/logging.c +++ b/src/logging.c @@ -41,12 +41,6 @@ int ugly_log(int level, const char *tag, const char *format, ...) { case UERROR: fprintf(stderr, "ERROR %s: ", tag); break; - case UFATAL: - fprintf(stderr, "FATAL %s: ", tag); - vfprintf(stderr, format, args); - exit(EXIT_FAILURE); - // NEVER GETS HERE!!! - break; default: fprintf(stderr, "%d %s: ", level, tag); break; From d9d17f4cfe274eadec8b5f537bcfcdbcbd44fbb4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=A9dric=20Boudinet?= Date: Wed, 28 Mar 2018 15:04:20 +0200 Subject: [PATCH 0608/1435] Icons for stlink gui (#697) * Adding icon for ui * renaming icons from stlinkgui to stlink-gui * moving icons from art to src/tools/gui/art --- CMakeLists.txt | 1 + src/tools/gui/art/stlink-gui_48.png | Bin 0 -> 2704 bytes src/tools/gui/art/stlink-gui_icon.svg | 126 ++++++++++++++++++++++++++ src/tools/gui/stlink-gui.ui | 1 + 4 files changed, 128 insertions(+) create mode 100644 src/tools/gui/art/stlink-gui_48.png create mode 100644 src/tools/gui/art/stlink-gui_icon.svg diff --git a/CMakeLists.txt b/CMakeLists.txt index c4f4e217c..a7e88b4a6 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -196,6 +196,7 @@ if (CMAKE_SYSTEM_NAME STREQUAL "Linux") DESTINATION ${STLINK_UDEV_RULES_DIR}/) #desktop file for linux launcher install(FILES src/tools/gui/stlink.desktop DESTINATION ${CMAKE_INSTALL_PREFIX}/share/applications) + install(FILES src/tools/gui/art/stlink-gui_48.png DESTINATION ${CMAKE_INSTALL_PREFIX}/share/icons/hicolor/48x48/apps RENAME stlink-gui.png) endif() add_subdirectory(src/gdbserver) diff --git a/src/tools/gui/art/stlink-gui_48.png b/src/tools/gui/art/stlink-gui_48.png new file mode 100644 index 0000000000000000000000000000000000000000..0428ffdd48abb16317afab232c3b357723149ab7 GIT binary patch literal 2704 zcmV;B3UBp^P)G0HQ$SobHKHOZ?|7+L(^9Fe z)H1thDO$T`iWg8*%(8XWa@%Un%{m>m8@1`0YvpY_pq1dNxf!OAc>zHfV3<2I^X?zO zFz?(L)N|Z@&Uw!}Gtc$=JkRfWpLc}v@^Xp)V^RVP95@iO*?g^IX&0rZr?Y9(rX~O; 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/** diff --git a/src/chipid.c b/src/chipid.c index 7cf83218d..705245f60 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -432,7 +432,7 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L4, .description = "L4 device", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81) // SRAM1 is "up to" 96k in the standard Cortex-M memory map; // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for @@ -441,6 +441,18 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) .bootrom_size = 0x7000 // 28k (per bank), same source as base }, + { + // STM32L4R9 (maybe others in the L4Rx series too) + // From DM00310109.pdf + .chip_id = STLINK_CHIPID_STM32_L4R9, + .description = "L4R9 device", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 97 + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 + .bootrom_size = 0x7000 // 28k (per bank), same source as base (pg 99) + }, { // STLINK_CHIPID_STM32_L43X // From RM0392. diff --git a/src/flash_loader.c b/src/flash_loader.c index a9eafcda3..ed96144a6 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -306,7 +306,8 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || (sl->chip_id == STLINK_CHIPID_STM32_L43X) || (sl->chip_id == STLINK_CHIPID_STM32_L46X) || - (sl->chip_id == STLINK_CHIPID_STM32_L496X)) + (sl->chip_id == STLINK_CHIPID_STM32_L4R9) || + (sl->chip_id == STLINK_CHIPID_STM32_L496X)) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); From aaf8e92075811e6b78cd7f68b636c642f27749bf Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Sun, 1 Apr 2018 20:16:49 +0300 Subject: [PATCH 0610/1435] Fix libusb function deprecation used for stlinkv1 Fixes #703 --- src/sg.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/sg.c b/src/sg.c index 541ef5550..90a144184 100644 --- a/src/sg.c +++ b/src/sg.c @@ -944,6 +944,10 @@ static stlink_t* stlink_open(const int verbose) { struct stlink_libsg *slsg = malloc(sizeof (struct stlink_libsg)); if (sl == NULL || slsg == NULL) { WLOG("Couldn't malloc stlink and stlink_sg structures out of memory!\n"); + if(sl != NULL) + free(sl); + if(slsg != NULL) + free(slsg); return NULL; } @@ -954,7 +958,11 @@ static stlink_t* stlink_open(const int verbose) { return NULL; } +#if LIBUSBX_API_VERSION < 0x01000106 libusb_set_debug(slsg->libusb_ctx, 3); +#else + libusb_set_option(slsg->libusb_ctx, LIBUSB_OPTION_LOG_LEVEL, 3); +#endif slsg->usb_handle = libusb_open_device_with_vid_pid(slsg->libusb_ctx, STLINK_USB_VID_ST, STLINK_USB_PID_STLINK); if (slsg->usb_handle == NULL) { From d76e3c7c542a115760d9bc3395c9ca90395ba3ae Mon Sep 17 00:00:00 2001 From: Johannes Date: Mon, 9 Apr 2018 20:25:14 +0200 Subject: [PATCH 0611/1435] rename STLINK_CHIPID_STM32_L4R9 to STLINK_CHIPID_STM32_L4RX (#706) --- include/stlink/chipid.h | 2 +- src/chipid.c | 10 +++++----- src/flash_loader.c | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index bf03703c7..004fa2e80 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -68,7 +68,7 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, STLINK_CHIPID_STM32_F413 = 0x463, - STLINK_CHIPID_STM32_L4R9 = 0x470 // taken from the STM32L4R9I-DISCO board + STLINK_CHIPID_STM32_L4RX = 0x470 // taken from the STM32L4R9I-DISCO board }; /** diff --git a/src/chipid.c b/src/chipid.c index 705245f60..6f93af112 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -10,8 +10,8 @@ static const struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ff0f442, // section 45.2 .flash_pagesize = 0x800, // No flash pages .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, //! "System memory" starting address from - .bootrom_size = 0xEDC0 //! @todo "System memory" byte size in hex from + .bootrom_base = 0x00200000, //! "System memory" starting address from + .bootrom_size = 0xEDC0 //! @todo "System memory" byte size in hex from }, { //RM0385 and DS10916 document was used to find these paramaters @@ -442,10 +442,10 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000 // 28k (per bank), same source as base }, { - // STM32L4R9 (maybe others in the L4Rx series too) + // STM32L4RX // From DM00310109.pdf - .chip_id = STLINK_CHIPID_STM32_L4R9, - .description = "L4R9 device", + .chip_id = STLINK_CHIPID_STM32_L4RX, + .description = "L4Rx device", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049) .flash_pagesize = 0x1000, // 4k, section 3.3, pg 97 diff --git a/src/flash_loader.c b/src/flash_loader.c index ed96144a6..599b2459a 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -219,7 +219,7 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) return 0; } -static int loader_v_dependent_assignment(stlink_t *sl, +static int loader_v_dependent_assignment(stlink_t *sl, const uint8_t **loader_code, size_t *loader_size, const uint8_t *high_v_loader, size_t high_v_loader_size, const uint8_t *low_v_loader, size_t low_v_loader_size) @@ -236,7 +236,7 @@ static int loader_v_dependent_assignment(stlink_t *sl, if (voltage == -1) { retval = -1; printf("Failed to read Target voltage\n"); - } + } else { if (voltage > 2700) { *loader_code = high_v_loader; @@ -306,7 +306,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || (sl->chip_id == STLINK_CHIPID_STM32_L43X) || (sl->chip_id == STLINK_CHIPID_STM32_L46X) || - (sl->chip_id == STLINK_CHIPID_STM32_L4R9) || + (sl->chip_id == STLINK_CHIPID_STM32_L4RX) || (sl->chip_id == STLINK_CHIPID_STM32_L496X)) { loader_code = loader_code_stm32l4; From 88935336f8f810e3524a5bb9baee30ed07af6c2e Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Mon, 16 Apr 2018 21:54:03 +0300 Subject: [PATCH 0612/1435] fix #700 (#701) * first try to fix #700 Use CMAKE_INSTALL_PREFIX for install paths * check IS_DIRECTORY LIB_INSTALL_DIR * fix incorrect VAR usage in condition * changed debian/rules according to @bluca patch --- CMakeLists.txt | 18 +++++++++++------- debian/rules | 2 +- include/CMakeLists.txt | 4 ++-- 3 files changed, 14 insertions(+), 10 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index a7e88b4a6..1d1f6f72b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,18 +4,22 @@ project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics Stlink Tools") set(STLINK_UDEV_RULES_DIR "/etc/udev/rules.d" CACHE PATH "Udev rules directory") set(STLINK_MODPROBED_DIR "/etc/modprobe.d" CACHE PATH "modprobe.d directory") -set(LIB_INSTALL_DIR "lib" CACHE PATH "Main library directory") -if(IS_DIRECTORY CMAKE_LIBRARY_PATH) +if( IS_DIRECTORY ${LIB_INSTALL_DIR}) + set(LIB_INSTALL_DIR ${LIB_INSTALL_DIR} CACHE PATH "Main library directory") + set(STLINK_LIBRARY_PATH "${LIB_INSTALL_DIR}") else() - set(CMAKE_LIBRARY_PATH "lib") + set(LIB_INSTALL_DIR "lib" CACHE PATH "Main library directory") + set(STLINK_LIBRARY_PATH "${CMAKE_INSTALL_PREFIX}/${LIB_INSTALL_DIR}" ) endif() -if (WIN32) - set(STLINK_LIBRARY_PATH ${CMAKE_LIBRARY_PATH} CACHE PATH "Target lib directory") +if( IS_DIRECTORY ${INCLUDE_INSTALL_DIR}) + set(INCLUDE_INSTALL_DIR ${INCLUDE_INSTALL_DIR} CACHE PATH "Main include directory") + set(STLINK_INCLUDE_PATH "${INCLUDE_INSTALL_DIR}" ) else() - set(STLINK_LIBRARY_PATH "${LIB_INSTALL_DIR}/${CMAKE_LIBRARY_PATH}" CACHE PATH "Target lib directory") -endif(WIN32) + set(INCLUDE_INSTALL_DIR "include" CACHE PATH "Main include directory") + set(STLINK_INCLUDE_PATH "${CMAKE_INSTALL_PREFIX}/${INCLUDE_INSTALL_DIR}") +endif() option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) diff --git a/debian/rules b/debian/rules index c4e9e2afd..e228a7087 100755 --- a/debian/rules +++ b/debian/rules @@ -15,5 +15,5 @@ export DEB_BUILD_MAINT_OPTIONS = hardening=+all override_dh_auto_configure: dh_auto_configure -- \ - -DCMAKE_LIBRARY_PATH=$(DEB_HOST_MULTIARCH) \ + -DLIB_INSTALL_DIR=/usr/lib/$(DEB_HOST_MULTIARCH) \ -DSTLINK_UDEV_RULES_DIR='/lib/udev/rules.d' diff --git a/include/CMakeLists.txt b/include/CMakeLists.txt index 0b5a443c0..a0c649532 100644 --- a/include/CMakeLists.txt +++ b/include/CMakeLists.txt @@ -7,8 +7,8 @@ file(GLOB STLINK_HEADERS "${CMAKE_BINARY_DIR}/include/stlink/*.h" ) install(FILES ${CMAKE_SOURCE_DIR}/include/stlink.h - DESTINATION include/${CMAKE_LIBRARY_PATH} + DESTINATION ${STLINK_INCLUDE_PATH} ) install(FILES ${STLINK_HEADERS} - DESTINATION include/${CMAKE_LIBRARY_PATH}/stlink + DESTINATION ${STLINK_INCLUDE_PATH}/stlink ) From b1b2a2f0a8af583bc7152a33b39fbfaeafe94aef Mon Sep 17 00:00:00 2001 From: Vasiliy Glazov Date: Tue, 17 Apr 2018 11:30:31 +0300 Subject: [PATCH 0613/1435] Disable static library installation by default (#702) * Disable static library installation by default * Added parameter for not install static lib * Rename and move to top parameter for install static libs. --- CMakeLists.txt | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 1d1f6f72b..54ddd3990 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,6 +4,7 @@ project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics Stlink Tools") set(STLINK_UDEV_RULES_DIR "/etc/udev/rules.d" CACHE PATH "Udev rules directory") set(STLINK_MODPROBED_DIR "/etc/modprobe.d" CACHE PATH "modprobe.d directory") +set(STLINK_STATIC_LIB ON CACHE BOOL "Install static lib") if( IS_DIRECTORY ${LIB_INSTALL_DIR}) set(LIB_INSTALL_DIR ${LIB_INSTALL_DIR} CACHE PATH "Main library directory") @@ -167,9 +168,11 @@ endif() set_target_properties(${STLINK_LIB_STATIC} PROPERTIES OUTPUT_NAME ${PROJECT_NAME}) -install(TARGETS ${STLINK_LIB_STATIC} - ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH} -) +if (STLINK_STATIC_LIB) + install(TARGETS ${STLINK_LIB_STATIC} + ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH} + ) +endif() ### # Tools From 0af68c0801f8413d26e70564a4adccc3f4187eae Mon Sep 17 00:00:00 2001 From: joede Date: Sat, 5 May 2018 08:01:41 +0200 Subject: [PATCH 0614/1435] Add svg icon for .desktop file (#708) * add SVG icon and .desktop file to Debian package. Renamed icon and .desktop file to package name. --- CMakeLists.txt | 3 - debian/stlink-gui.install | 2 + src/tools/gui/CMakeLists.txt | 9 + src/tools/gui/art/export-icons.sh | 38 ++++ .../art/hicolor/128x128/apps/stlink-gui.png | Bin 0 -> 7123 bytes .../gui/art/hicolor/16x16/apps/stlink-gui.png | Bin 0 -> 781 bytes .../gui/art/hicolor/22x22/apps/stlink-gui.png | Bin 0 -> 1134 bytes .../gui/art/hicolor/24x24/apps/stlink-gui.png | Bin 0 -> 1253 bytes .../art/hicolor/256x256/apps/stlink-gui.png | Bin 0 -> 14568 bytes .../gui/art/hicolor/32x32/apps/stlink-gui.png | Bin 0 -> 1756 bytes .../gui/art/hicolor/48x48/apps/stlink-gui.png | Bin 0 -> 2707 bytes .../gui/art/hicolor/64x64/apps/stlink-gui.png | Bin 0 -> 3497 bytes src/tools/gui/art/stlink-gui.png | Bin 0 -> 1756 bytes src/tools/gui/art/stlink-gui.svg | 130 ++++++++++++ src/tools/gui/art/stlink-gui.xpm | 200 ++++++++++++++++++ src/tools/gui/art/stlink-gui_icon.svg | 126 ----------- .../{stlink.desktop => stlink-gui.desktop} | 0 17 files changed, 379 insertions(+), 129 deletions(-) create mode 100755 src/tools/gui/art/export-icons.sh create mode 100644 src/tools/gui/art/hicolor/128x128/apps/stlink-gui.png create mode 100644 src/tools/gui/art/hicolor/16x16/apps/stlink-gui.png create mode 100644 src/tools/gui/art/hicolor/22x22/apps/stlink-gui.png create mode 100644 src/tools/gui/art/hicolor/24x24/apps/stlink-gui.png create mode 100644 src/tools/gui/art/hicolor/256x256/apps/stlink-gui.png create mode 100644 src/tools/gui/art/hicolor/32x32/apps/stlink-gui.png create mode 100644 src/tools/gui/art/hicolor/48x48/apps/stlink-gui.png create mode 100644 src/tools/gui/art/hicolor/64x64/apps/stlink-gui.png create mode 100644 src/tools/gui/art/stlink-gui.png create mode 100644 src/tools/gui/art/stlink-gui.svg create mode 100644 src/tools/gui/art/stlink-gui.xpm delete mode 100644 src/tools/gui/art/stlink-gui_icon.svg rename src/tools/gui/{stlink.desktop => stlink-gui.desktop} (100%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 54ddd3990..395848b0a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -201,9 +201,6 @@ if (CMAKE_SYSTEM_NAME STREQUAL "Linux") DESTINATION ${STLINK_MODPROBED_DIR}/) install(FILES ${RULES_FILES} DESTINATION ${STLINK_UDEV_RULES_DIR}/) - #desktop file for linux launcher - install(FILES src/tools/gui/stlink.desktop DESTINATION ${CMAKE_INSTALL_PREFIX}/share/applications) - install(FILES src/tools/gui/art/stlink-gui_48.png DESTINATION ${CMAKE_INSTALL_PREFIX}/share/icons/hicolor/48x48/apps RENAME stlink-gui.png) endif() add_subdirectory(src/gdbserver) diff --git a/debian/stlink-gui.install b/debian/stlink-gui.install index d18d2cec4..b419ac054 100644 --- a/debian/stlink-gui.install +++ b/debian/stlink-gui.install @@ -1,2 +1,4 @@ /usr/bin/stlink-gui* /usr/share/stlink/stlink-gui.ui +/usr/share/applications/stlink-gui.desktop +/usr/share/icons/hicolor/scalable/apps/stlink-gui.svg diff --git a/src/tools/gui/CMakeLists.txt b/src/tools/gui/CMakeLists.txt index 4ab9975da..ceb862c33 100644 --- a/src/tools/gui/CMakeLists.txt +++ b/src/tools/gui/CMakeLists.txt @@ -22,3 +22,12 @@ install(TARGETS stlink-gui RUNTIME DESTINATION bin) install(FILES stlink-gui.ui DESTINATION ${INSTALLED_UI_DIR}) +if (${CMAKE_SYSTEM_NAME} MATCHES "Linux") + # Install desktop entry + install(FILES stlink-gui.desktop + DESTINATION share/applications) + # Install icon + install(FILES art/stlink-gui.svg + DESTINATION share/icons/hicolor/scalable/apps) +endif (${CMAKE_SYSTEM_NAME} MATCHES "Linux") + diff --git a/src/tools/gui/art/export-icons.sh b/src/tools/gui/art/export-icons.sh new file mode 100755 index 000000000..9d61719b9 --- /dev/null +++ b/src/tools/gui/art/export-icons.sh @@ -0,0 +1,38 @@ +#!/bin/sh +# +# create the XPM icon and all resolutions below hicolor as PNG + +APPNAME="stlink-gui" +ORIGIN="stlink-gui_icon.svg" +OUTDIR="hicolor" + +## possible size options are --export-dpi / --export-width / --export-height +OPTS="-z --export-id-only" +ID="scalable-icon" +RESOLUTIONS="16 22 24 32 48 64 128 256" + + if ! [ -d $OUTDIR ]; then + echo "output directory missing. Create it..." + mkdir $OUTDIR + for RES in $RESOLUTIONS; do + mkdir -p $OUTDIR/${RES}x${RES}/apps + done + fi + + # create single app icon + inkscape $OPTS --export-width=32 --export-id=$ID --export-png=$APPNAME.png $ORIGIN + if [ $? != 0 ]; then exit 1; fi + convert $APPNAME.png $APPNAME.xpm + + # create all the resolutions + ALL="" + for RES in $RESOLUTIONS; do + inkscape $OPTS --export-width=$RES --export-id=$ID --export-png=$OUTDIR/${RES}x${RES}/apps/$APPNAME.png $ORIGIN + ALL="$ALL $OUTDIR/${RES}x${RES}/apps/$APPNAME.png" + done + + # this is for windows... + #echo "build Windows icon from $ALL" + #convert $ALL $APPNAME.ico + +exit 0 diff --git a/src/tools/gui/art/hicolor/128x128/apps/stlink-gui.png b/src/tools/gui/art/hicolor/128x128/apps/stlink-gui.png new file mode 100644 index 0000000000000000000000000000000000000000..c56988e305fcceb87ccdd7bb49fc48be31540a9f GIT binary patch literal 7123 zcmYjWbyQT(``#s%1{IKQ0ZCChgrz&Ad+ClPRzPZLX(S~UkdW>UX$0v`X;2!ZS?ar= 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+", c #153848", +"< c #16394D", +"1 c #1D3A4B", +"2 c #172D55", +"3 c #1C3C52", +"4 c #193A55", +"5 c #232E42", +"6 c #213145", +"7 c #2C3B46", +"8 c #24364B", +"9 c #24394B", +"0 c #2E3A4C", +"q c #333D4A", +"w c #0E3562", +"e c #003D6F", +"r c #133666", +"t c #163D65", +"y c #183B61", +"u c #12376C", +"i c #0C3A76", +"p c #17434D", +"a c #1D4049", +"s c #184455", +"d c #184851", +"f c #27404C", +"g c #2D444D", +"h c #34434F", +"j c #3C4649", +"k c #384250", +"l c #0F4463", +"z c #164265", +"x c #184261", +"c c #144964", +"v c #184A62", +"b c #144E69", +"n c #135369", +"m c #0A4177", +"M c #00417F", +"N c #0A5277", +"B c #424D55", +"V c #444E5A", +"C c #4A5059", +"Z c #4D5A5E", +"A c #4E5562", +"S c #515B63", +"D c #565E69", +"F c #58646B", +"G c #5D686F", +"H c #5D6670", +"J c #5F6D72", +"K c #656C77", +"L c #676C78", +"P c #6B737C", +"I c #063C84", +"U c #01378C", +"Y c #033295", +"T c #013E98", +"R c #0034A0", +"E c #0036A9", +"W c #003CAF", +"Q c #003CBF", +"! c #004581", +"~ c #074587", +"^ c #004C81", +"/ c #005286", +"( c #005C85", +") c #004297", +"_ c #044D91", +"` c #034B99", +"' c #025A90", +"] c #005898", +"[ c #006382", +"{ c #076988", +"} c #07758F", +"| c #02689C", +" . c #0042A3", +".. c #004CA8", +"X. c #0051A0", +"o. c #0055AB", +"O. c #005BAF", +"+. c #0045B4", +"@. c #0049B9", +"#. c #0052B6", +"$. c #0054BD", +"%. c #005ABC", +"&. c #0060A6", +"*. c #0069A6", +"=. c #0065AC", +"-. c #006FA9", +";. c #0072A6", +":. c #007DA6", +">. c #0073AF", +",. c #006EB3", +"<. c #0065B9", +"1. c #006ABF", +"2. c #0076B0", +"3. c #007EB2", +"4. c #757B83", +"5. c #0036C0", +"6. c #003AC0", +"7. c #0044C0", +"8. c #004CC0", +"9. c #0053C0", +"0. c #005BC0", +"q. c #0064C0", +"w. c #006CC0", +"e. c #0074C0", +"r. c #007CC0", +"t. c #0085A6", +"y. c #0088A6", +"u. c #0082AA", +"i. c #0093A6", +"p. c #0093AE", +"a. c #0087B8", +"s. c #008BB8", +"d. c #0090B1", +"f. c #009EBE", +"g. c #00A3BE", +"h. c #0083C0", +"j. c #008BC0", +"k. c #0093C0", +"l. c #00A2C0", +"z. c #84868A", +"x. c #858B90", +"c. c #8C8E92", +"v. c #919192", +"b. c #94989E", +"n. c #9B9C9C", +"m. c #9D9EA1", +"M. c #9FA1A3", +"N. c #A1A1A1", +"B. c #A6ABAD", +"V. c #A9A9A9", +"C. c #ADB2B4", +"Z. c #B7B7B8", +"A. c #BBBBBC", +"S. c #C2C2C3", +"D. c #C6C7C8", +"F. c #CBCCCC", +"G. c #D2D2D2", +"H. c #DBDBDB", +"J. c #E1E1E1", +"K. c #ECECEC", +"L. c #F4F4F4", +"P. c #FEFEFE", +/* pixels */ +"G.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.J.", +"N. X . X X X X X X X X . X X X X X X X X X X X X X X X X X N.", +"N.. Q 5.5.E 2 ; 0 0 0 > u T 8.i ; > ; ; > > > > - > 1 , r.1.. M.", +"N.. Q 5.Y q G.P.P.P.P.L.F.5 9.; L.P.P.P.P.P.P.P.P.P.P.h e.1.. N.", +"N.. 6.6.5 L.P.J.c.4.m.F.P.8 $.8 H.H.H.J.L.P.P.H.H.H.J.7 e.e.. N.", +"N.. 6.R L P.K.5 Y T U r 5 # 9.~ y y y = V.P.P.+ z x x z r.r.. N.", +"N.. 6.Y z.P.H.2 @.8.9.9.9...0.0.%.0.q.! V.P.P.1 e.e.e.e.r.r.. N.", +"M.. 6.W A P.P.V.k 6 r ) $.9.0.0.q.q.q.! V.P.P.1 e.e.e.r.r.3.. N.", +"M.. Q @.; F.P.P.P.P.F.4.6 ` %.0.q.q.w.! V.P.P.: e.e.r.r.r.h.. N.", +"M.. 7.7.+.2 D S.P.P.P.P.L.q O.q.q.q.q.! V.P.P.> e.r.r.r.r.h.. N.", +"N.. 7.8.8.8. .u > q m.P.P.S.m q.w.q.w.^ V.P.P.1 r.r.r.r.h.h.. N.", +"N.. 7.+. .8.9.9.9.$.w Z.P.K.3 q.w.w.w.^ V.P.P.1 r.r.r.h.h.a.. N.", +"N.. 8. .+ 5 U #.0.0.w Z.P.J.4 w.w.w.w.^ V.P.P.1 r.h.h.h.h.h.. N.", +"M.. 8. .L K.c.V q k b.P.P.x._ w.w.w.e.^ V.P.P.1 r.h.h.h.j.j.. N.", +"M.. @. .C K.P.P.P.P.P.P.A.> 1.w.w.e.e.^ V.P.P.1 h.h.h.h.j.j.. N.", +"N.. 8.$.I 4 q B H P S 7 t <.1.w.e.e.e./ & h h < h.h.j.j.j.j.. N.", +"N.. 9.9.9.0.%.%.o.X.O.q.q.w.w.e.e.e.e.r.r.r.h.h.h.h.j.j.j.k.. N.", +"N.. i i ~ 0.` i m ` w.q.w.w.e.w.e.e.r.r.r.| N N { j.j.j.k.k.. N.", +"N.o z.A.6 0.t N.Z.1 w.w.w.e.e.e.e.r.r.r.r.b n.A.1 j.j.j.k.k.. N.", +"N.o A.P.8 q.t v.V.1 w.w.w.e.e.3.r.r.r.r.h.c G.P.1 j.k.k.k.k.. N.", +"N.o A.P.9 q.M * * e w.] ^ ^ &.' z N >.h.h.b G.P.1 k.f.N [ N X M.", +"N.o A.P.8 q.t v.V.> w.3 N.v.O 4.G.A.7 ;.h.b G.P.1 s.: m.v.@ . M.", +"N.o A.P.8 q.z G.L.4 w.3 L.H.z.F x.P.J.s j.n G.P.$ : D.H.& i.. M.", +"N.o A.P.9 q.z H.P.1 e.3 L.P.7 -.l S.P.f j.b G.P.O D.G.: p.g.. M.", +"N.o A.P.9 w.z H.P.1 e.3 L.K.s r.( V.P.g s.n G.P.A.L.@ p.f.l.. N.", +"N.o A.P.9 w.t H.L.4 e.3 L.H.v h.( N.P.g j.n G.P.j P.C.p f.l.. N.", +"N.o A.P.9 w.x H.L.9 3.3 L.H.v h.( m.P.g k.n G.P.O B P.B.d g.. N.", +"N.o A.P.9 e.z G.P.4 r.s L.H.v a.( N.P.g k.n G.P.a } Z P.B.d . N.", +"N.o B H - e.c S G , r.< G S c j.[ k K # k.n Z J a g.} j J % o m.", +"N.. &.&.=.1.,.*.-.>.h.2.;.;.3.s.a.:.u.t.f.d.y.y.p.g.g.i.i.i.. m.", +"N. X X X X X X X X X X X X X X X X X X X X X X X X X X o o N.", +"J.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.V.J." +}; diff --git a/src/tools/gui/art/stlink-gui_icon.svg b/src/tools/gui/art/stlink-gui_icon.svg deleted file mode 100644 index 92f7e5f11..000000000 --- a/src/tools/gui/art/stlink-gui_icon.svg +++ /dev/null @@ -1,126 +0,0 @@ - - - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - - - ST - link - - diff --git a/src/tools/gui/stlink.desktop b/src/tools/gui/stlink-gui.desktop similarity index 100% rename from src/tools/gui/stlink.desktop rename to src/tools/gui/stlink-gui.desktop From 065a4751cb405232fdac21e2b9416324d9d56cb0 Mon Sep 17 00:00:00 2001 From: dacodas Date: Sat, 19 May 2018 09:03:02 +0300 Subject: [PATCH 0615/1435] st-util: send memory map for STM32F411RE (#709) --- src/gdbserver/gdb-server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index f5afa73b4..7bf3a275f 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -522,7 +522,7 @@ char* make_memory_map(stlink_t *sl) { char* map = malloc(sz); map[0] = '\0'; - if(sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F446) { + if(sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F446 || sl->chip_id==STLINK_CHIPID_STM32_F411RE) { strcpy(map, memory_map_template_F4); } else if(sl->chip_id==STLINK_CHIPID_STM32_F4_DE) { strcpy(map, memory_map_template_F4_DE); From 6f74f4a29ce079b991dbb41866c7ce54e6728ee0 Mon Sep 17 00:00:00 2001 From: trent Date: Thu, 31 May 2018 14:41:26 -0400 Subject: [PATCH 0616/1435] Fixed flash memory map for F72XXX chip_id (#711) --- src/common.c | 2 +- src/flash_loader.c | 8 +++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/common.c b/src/common.c index b9b738203..878eba4c1 100644 --- a/src/common.c +++ b/src/common.c @@ -1451,7 +1451,7 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || (sl->chip_id == STLINK_CHIPID_STM32_F4) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || - (sl->chip_id == STLINK_CHIPID_STM32_F446) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI)) { + (sl->chip_id == STLINK_CHIPID_STM32_F446) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || (sl->chip_id == STLINK_CHIPID_STM32_F72XXX)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector>= 12) { sector -= 12; diff --git a/src/flash_loader.c b/src/flash_loader.c index 599b2459a..7684680a7 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -289,9 +289,11 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* if (retval == -1) { return retval; } - } else if (sl->core_id == STM32F7_CORE_ID || - sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { + } else if (sl->core_id == STM32F7_CORE_ID || + sl->chip_id == STLINK_CHIPID_STM32_F7 || + sl->chip_id == STLINK_CHIPID_STM32_F7XXXX || + sl->chip_id == STLINK_CHIPID_STM32_F72XXX + ) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, From 6db0fc243ffb90aed314ef1d59811486e9214883 Mon Sep 17 00:00:00 2001 From: Timothy Lee Date: Fri, 1 Jun 2018 04:51:35 +1000 Subject: [PATCH 0617/1435] Reset through AIRCR (#540) (#712) In addition to asserting the NRST line, also request system reset through the Application Interrupt and Reset Control Register (AIRCR). --- include/stlink/reg.h | 5 +++++ src/sg.c | 5 +++++ src/usb.c | 9 ++++----- 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/include/stlink/reg.h b/include/stlink/reg.h index 917325fb6..765ac9525 100644 --- a/include/stlink/reg.h +++ b/include/stlink/reg.h @@ -12,4 +12,9 @@ #define STLINK_REG_DCRSR 0xe000edf4 #define STLINK_REG_DCRDR 0xe000edf8 +/* Application Interrupt and Reset Control Register */ +#define STLINK_REG_AIRCR 0xe000ed0c +#define STLINK_REG_AIRCR_VECTKEY 0x05fa0000 +#define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004 + #endif /* STLINK_REG_H_ */ diff --git a/src/sg.c b/src/sg.c index 90a144184..fd3e7e881 100644 --- a/src/sg.c +++ b/src/sg.c @@ -535,6 +535,11 @@ int _stlink_sg_reset(stlink_t *sl) { if (stlink_q(sl)) return -1; + // Reset through AIRCR so NRST does not need to be connected + if (stlink_write_debug32(sl, STLINK_REG_AIRCR, + STLINK_REG_AIRCR_VECTKEY | STLINK_REG_AIRCR_SYSRESETREQ)) + return -1; + stlink_stat(sl, "core reset"); return 0; } diff --git a/src/usb.c b/src/usb.c index dbacfee83..3e0596f18 100644 --- a/src/usb.c +++ b/src/usb.c @@ -368,10 +368,7 @@ int _stlink_usb_exit_dfu_mode(stlink_t* sl) { return 0; } -/** - * TODO - not convinced this does anything... - * @param sl - */ + int _stlink_usb_reset(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; @@ -389,7 +386,9 @@ int _stlink_usb_reset(stlink_t * sl) { return (int) size; } - return 0; + // Reset through AIRCR so NRST does not need to be connected + return stlink_write_debug32(sl, STLINK_REG_AIRCR, + STLINK_REG_AIRCR_VECTKEY | STLINK_REG_AIRCR_SYSRESETREQ); } From 1ec89bf7a20b060b45dbc5e1fd96b26c02c4d0a2 Mon Sep 17 00:00:00 2001 From: Anatoli Klassen Date: Wed, 27 Jun 2018 17:16:25 +0200 Subject: [PATCH 0618/1435] implement IHEX for the GUI (#718) * implement IHEX for the GUI * use already loaded file's content to write into the flash * fix clang casting --- src/tools/gui/stlink-gui.c | 114 ++++++++++++++++++++++++------------- 1 file changed, 73 insertions(+), 41 deletions(-) diff --git a/src/tools/gui/stlink-gui.c b/src/tools/gui/stlink-gui.c index 2be97ef10..c1cf26b76 100644 --- a/src/tools/gui/stlink-gui.c +++ b/src/tools/gui/stlink-gui.c @@ -306,49 +306,81 @@ stlink_gui_populate_filemem_view (gpointer data) g_return_val_if_fail (gui != NULL, NULL); g_return_val_if_fail (gui->filename != NULL, NULL); - file = g_file_new_for_path (gui->filename); - input_stream = G_INPUT_STREAM (g_file_read (file, NULL, &err)); - if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); - goto out; - } - - file_info = g_file_input_stream_query_info (G_FILE_INPUT_STREAM (input_stream), - G_FILE_ATTRIBUTE_STANDARD_SIZE, NULL, &err); - if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); - goto out_input; - } - if (gui->file_mem.memory) { - g_free (gui->file_mem.memory); - } - gui->file_mem.size = g_file_info_get_size (file_info); - gui->file_mem.memory = g_malloc (gui->file_mem.size); - - for (off = 0; off < (gint) gui->file_mem.size; off += MEM_READ_SIZE) { - guint n_read = MEM_READ_SIZE; - - if (off + MEM_READ_SIZE > (gint) gui->file_mem.size) { - n_read = (guint) gui->file_mem.size - off; - } - - if (g_input_stream_read (G_INPUT_STREAM (input_stream), - &buffer, n_read, NULL, &err) == -1) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); - goto out_input; - } - memcpy (gui->file_mem.memory + off, buffer, n_read); - gui->progress.fraction = (gdouble) (off + n_read) / gui->file_mem.size; - } - g_idle_add ((GSourceFunc) stlink_gui_update_filemem_view, gui); + if (g_str_has_suffix (gui->filename, ".hex")) { + // If the file has prefix .hex - try to interpret it as Intel-HEX. + // It's difficult to merge the world of standard functions and GLib, + // so do it simple - load whole file into buffer and copy the data + // to the destination afterwards. + // We loose meanwhile the displaying of the progress and need + // double memory. + + uint8_t* mem = NULL; + size_t size = 0; + uint32_t begin = 0; + int res = stlink_parse_ihex (gui->filename, 0, &mem, &size, &begin); + + if (res == 0) { + if (gui->file_mem.memory) { + g_free (gui->file_mem.memory); + } + gui->file_mem.size = size; + gui->file_mem.memory = g_malloc (size); + gui->file_mem.base = begin; + + memcpy (gui->file_mem.memory, mem, size); + } + else { + stlink_gui_set_info_error_message (gui, "Cannot interpret the file as Intel-HEX"); + } + + free(mem); + } + else { + file = g_file_new_for_path (gui->filename); + input_stream = G_INPUT_STREAM (g_file_read (file, NULL, &err)); + if (err) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + goto out; + } + + file_info = g_file_input_stream_query_info (G_FILE_INPUT_STREAM (input_stream), + G_FILE_ATTRIBUTE_STANDARD_SIZE, NULL, &err); + if (err) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + goto out_input; + } + if (gui->file_mem.memory) { + g_free (gui->file_mem.memory); + } + gui->file_mem.size = g_file_info_get_size (file_info); + gui->file_mem.memory = g_malloc (gui->file_mem.size); + + for (off = 0; off < (gint) gui->file_mem.size; off += MEM_READ_SIZE) { + guint n_read = MEM_READ_SIZE; + + if (off + MEM_READ_SIZE > (gint) gui->file_mem.size) { + n_read = (guint) gui->file_mem.size - off; + } + + if (g_input_stream_read (G_INPUT_STREAM (input_stream), + &buffer, n_read, NULL, &err) == -1) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + goto out_input; + } + memcpy (gui->file_mem.memory + off, buffer, n_read); + gui->progress.fraction = (gdouble) (off + n_read) / gui->file_mem.size; + } out_input: - g_object_unref (input_stream); + g_object_unref (input_stream); out: - g_object_unref (file); + g_object_unref (file); + } + + g_idle_add ((GSourceFunc) stlink_gui_update_filemem_view, gui); return NULL; } @@ -661,7 +693,7 @@ stlink_gui_write_flash (gpointer data) g_return_val_if_fail ((gui->sl != NULL), NULL); g_return_val_if_fail ((gui->filename != NULL), NULL); - if (stlink_fwrite_flash(gui->sl, gui->filename, gui->sl->flash_base) < 0) { + if (stlink_mwrite_flash(gui->sl, gui->file_mem.memory, (uint32_t)gui->file_mem.size, gui->sl->flash_base) < 0) { stlink_gui_set_info_error_message (gui, "Failed to write to flash"); } From e147a8ea3863cbfa64eb22ff6113800e3eb01261 Mon Sep 17 00:00:00 2001 From: Deomid Ryabkov Date: Sat, 7 Jul 2018 15:52:37 +0300 Subject: [PATCH 0619/1435] Proper flash page size calculation for F412 (#721) --- src/common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 878eba4c1..40a689c7e 100644 --- a/src/common.c +++ b/src/common.c @@ -1451,7 +1451,8 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || (sl->chip_id == STLINK_CHIPID_STM32_F4) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || - (sl->chip_id == STLINK_CHIPID_STM32_F446) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || (sl->chip_id == STLINK_CHIPID_STM32_F72XXX)) { + (sl->chip_id == STLINK_CHIPID_STM32_F446) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || + (sl->chip_id == STLINK_CHIPID_STM32_F412)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector>= 12) { sector -= 12; From 79306cc5d8720fd578e8102a0f5e94d39cc68ed0 Mon Sep 17 00:00:00 2001 From: Bez <9039899+fkarg@users.noreply.github.com> Date: Tue, 10 Jul 2018 19:43:48 +0200 Subject: [PATCH 0620/1435] Update tutorial.md (#722) --- doc/tutorial.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/tutorial.md b/doc/tutorial.md index 52ed0bc9b..35c607ac0 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -35,6 +35,8 @@ Before continuing, the following dependencies must be met: - libusb-1.0 - cmake +Also make sure `gtk+` version 3.0 is installed. (`sudo apt-get install gtk+-3.0` or similiar) + STLINK should run on any system meeting the above constraints. The STLINK software source code is retrieved using: From ca6ecc4cfdab84a4968fd9444378f4f445981bc7 Mon Sep 17 00:00:00 2001 From: donmr Date: Thu, 26 Jul 2018 09:42:45 -0700 Subject: [PATCH 0621/1435] semihosting: Use local variable for read_result instead of *ret, and fix calculation of *ret for EOF case (#727) --- src/gdbserver/semihosting.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/gdbserver/semihosting.c b/src/gdbserver/semihosting.c index 312b1517e..75fc6b1ef 100644 --- a/src/gdbserver/semihosting.c +++ b/src/gdbserver/semihosting.c @@ -307,6 +307,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { int fd; uint32_t buffer_len; void *buffer; + int read_result; if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { DLOG("Semihosting SYS_READ error: " @@ -337,7 +338,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { DLOG("Semihosting: read(%d, target_addr:0x%08x, %zu)\n", fd, buffer_address, buffer_len); - *ret = (uint32_t)read(fd, buffer, buffer_len); + read_result = (uint32_t)read(fd, buffer, buffer_len); saved_errno = errno; if (*ret == (uint32_t)-1) { @@ -350,7 +351,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { *ret = buffer_len; return -1; } else { - *ret -= buffer_len; + *ret = buffer_len - read_result; } } From 07a76b01ee4932130fa23dac7b8021ff915b38f0 Mon Sep 17 00:00:00 2001 From: donmr Date: Sat, 28 Jul 2018 02:45:09 -0700 Subject: [PATCH 0622/1435] Fixes to SYS_READ changes in PR #727 per review. (#729) * Use local variable for read_result instead of *ret, and fix calculation of *ret for EOF case. * Found a problem when reading an odd (%4) number of bytes at the end of a file. fread (on stm32) get them (say 3 bytes), then askes for more. do_semihosting gets a read return of 0 and tries to write that. mem_write alters the address to be aligned and overwrites then 3 bytes from the last read. This change simply tells mem_write to do nothing if len is 0. * Fix Issues from Fabien-Chouteau's review of my previous patch in isue #727. * Revert change to mem_write() so it does not confuse fixes to do_semihosting(). * Add cast to avoid warning. --- src/gdbserver/semihosting.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/gdbserver/semihosting.c b/src/gdbserver/semihosting.c index 75fc6b1ef..5fd0d669f 100644 --- a/src/gdbserver/semihosting.c +++ b/src/gdbserver/semihosting.c @@ -307,7 +307,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { int fd; uint32_t buffer_len; void *buffer; - int read_result; + ssize_t read_result; if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { DLOG("Semihosting SYS_READ error: " @@ -338,20 +338,20 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { DLOG("Semihosting: read(%d, target_addr:0x%08x, %zu)\n", fd, buffer_address, buffer_len); - read_result = (uint32_t)read(fd, buffer, buffer_len); + read_result = read(fd, buffer, buffer_len); saved_errno = errno; - if (*ret == (uint32_t)-1) { + if (read_result == (uint32_t)-1) { *ret = buffer_len; } else { - if (mem_write(sl, buffer_address, buffer, *ret) != 0 ) { + if (mem_write(sl, buffer_address, buffer, read_result) != 0 ) { DLOG("Semihosting SYS_READ error: " "cannot write buffer to target memory\n"); free(buffer); *ret = buffer_len; return -1; } else { - *ret = buffer_len - read_result; + *ret = buffer_len - (uint32_t)read_result; } } From ea98ab7bf2064f90afd32326a24c893256a19477 Mon Sep 17 00:00:00 2001 From: donmr Date: Wed, 1 Aug 2018 02:03:35 -0700 Subject: [PATCH 0623/1435] Fix to cast in changes for SYS_READ. (#731) * Remove cast of "-1" to uint32_t. It's now compared to a ssize_t and the compiler should be fine with that without any cast. --- src/gdbserver/semihosting.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gdbserver/semihosting.c b/src/gdbserver/semihosting.c index 5fd0d669f..e0249a980 100644 --- a/src/gdbserver/semihosting.c +++ b/src/gdbserver/semihosting.c @@ -341,7 +341,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { read_result = read(fd, buffer, buffer_len); saved_errno = errno; - if (read_result == (uint32_t)-1) { + if (read_result == -1) { *ret = buffer_len; } else { if (mem_write(sl, buffer_address, buffer, read_result) != 0 ) { From 27ce268a78b4850c5d786bae23315b4bca009245 Mon Sep 17 00:00:00 2001 From: donmr Date: Wed, 1 Aug 2018 02:05:31 -0700 Subject: [PATCH 0624/1435] Mem write odd (#730) * Use local variable for read_result instead of *ret, and fix calculation of *ret for EOF case. * Found a problem when reading an odd (%4) number of bytes at the end of a file. fread (on stm32) get them (say 3 bytes), then askes for more. do_semihosting gets a read return of 0 and tries to write that. mem_write alters the address to be aligned and overwrites then 3 bytes from the last read. This change simply tells mem_write to do nothing if len is 0. * Fix Issues from Fabien-Chouteau's review of my previous patch in isue #727. * Revert change to mem_write() so it does not confuse fixes to do_semihosting(). * Add cast to avoid warning. * Restore change to mem_write to return immeadiately if len == 0. Add more comments on further possible issues and ways to handle them. Using a branch to separate this change from others as it may need more discussion and go on for a while... * Remove cast of "-1" to uint32_t. It's now compared to a ssize_t and the compiler should be fine with that without any cast. --- src/gdbserver/semihosting.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/gdbserver/semihosting.c b/src/gdbserver/semihosting.c index e0249a980..b7792007f 100644 --- a/src/gdbserver/semihosting.c +++ b/src/gdbserver/semihosting.c @@ -91,6 +91,19 @@ static int mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { + // Note: this function can write more than it is asked to! + // If addr is not an even 32 bit boundary, or len is not a multiple of 4. + // + // If only 32 bit values can be written to the target, + // then this function should read the target memory at the + // start and end of the buffer where it will write more that + // the requested bytes. (perhaps reading the whole area is faster??). + // + // If 16 and 8 bit writes are available, then they could be used instead. + + // Just return when the length is zero avoiding unneeded work. + if (len == 0) return 0; + int offset = addr % 4; int write_len = len + offset; From ae717b945dea2ca46c2e3ed0c97cb4bfc4fa7252 Mon Sep 17 00:00:00 2001 From: Luc Hondareyte <26144323+lhondareyte@users.noreply.github.com> Date: Thu, 2 Aug 2018 13:00:16 +0200 Subject: [PATCH 0625/1435] FreeBSD define LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION. (#733) --- src/sg.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/sg.c b/src/sg.c index fd3e7e881..285e2bd90 100644 --- a/src/sg.c +++ b/src/sg.c @@ -963,6 +963,9 @@ static stlink_t* stlink_open(const int verbose) { return NULL; } +#if defined (__FreeBSD__) + #define LIBUSBX_API_VERSION LIBUSB_API_VERSION +#endif #if LIBUSBX_API_VERSION < 0x01000106 libusb_set_debug(slsg->libusb_ctx, 3); #else From 5edb9e1bb24d162f7ff9db57a874c40f251981a9 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 13 Sep 2018 22:14:22 +0200 Subject: [PATCH 0626/1435] Update .version --- .version | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.version b/.version index bc80560fa..26ca59460 100644 --- a/.version +++ b/.version @@ -1 +1 @@ -1.5.0 +1.5.1 From 3eab7b960ff180df5f3678def13dceb4cf7ced93 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 13 Sep 2018 22:20:46 +0200 Subject: [PATCH 0627/1435] Update ChangeLog.md --- ChangeLog.md | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/ChangeLog.md b/ChangeLog.md index ec397ece6..4602d70bd 100644 --- a/ChangeLog.md +++ b/ChangeLog.md @@ -1,6 +1,27 @@ Stlink ChangeLog ================ +v1.5.1 +====== + +Release date: 2018-09-13 + +Major changes and added features: + +* Implement intel hex support for GTK GUI +* Update libusb to 1.0.22 +* Add memory map for STM32F411RE target +* Add support for STM32L4R9 target + +Fixes: + +* FreeBSD define LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION +* Proper flash page size calculation for F412 target +* Fix flash memory map for F72xxx target +* Return correct value on EOF for Semihosting SYS_READ + +For a complete list of changes see [the milestone](https://github.com/texane/stlink/milestone/6?closed=1) + v1.5.0 ====== From 7fafee24a57c4cfa24df56383546d5c04866b512 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Thu, 13 Sep 2018 22:23:08 +0200 Subject: [PATCH 0628/1435] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index bdb2351a6..a95698bdd 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ Open source version of the STMicroelectronics Stlink Tools [![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/texane/stlink/releases/latest) [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) -[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.5.0.svg)](https://github.com/texane/stlink/compare/1.4.0...master) +[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.5.1.svg)](https://github.com/texane/stlink/compare/1.5.1...master) [![Downloads](https://img.shields.io/github/downloads/texane/stlink/total.svg)](https://github.com/texane/stlink/releases) [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) [![Build Status](https://jenkins.ncrmnt.org/buildStatus/icon?job=GithubCI/stlink)](https://jenkins.ncrmnt.org/job/GithubCI/job/stlink/) From 66e5e3ac806c7c54ba2b7f9ecb24c037c95c98be Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Fri, 28 Sep 2018 10:27:24 +0100 Subject: [PATCH 0629/1435] Mark packages as linux-any, other systems not supported. --- debian/control | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/debian/control b/debian/control index 3427359c6..da8f69203 100644 --- a/debian/control +++ b/debian/control @@ -10,7 +10,7 @@ Vcs-Browser: https://github.com/bluca/stlink Package: libstlink-dev Section: libdevel -Architecture: any +Architecture: linux-any Depends: libstlink1 (= ${binary:Version}), ${misc:Depends} Description: OpenSource ST-Link tools replacement. Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers @@ -20,7 +20,7 @@ Description: OpenSource ST-Link tools replacement. Package: libstlink1 Section: libs -Architecture: any +Architecture: linux-any Depends: ${shlibs:Depends}, ${misc:Depends} Description: OpenSource ST-Link tools replacement. Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers @@ -29,7 +29,7 @@ Description: OpenSource ST-Link tools replacement. This package contains the shared library for stlink. Package: stlink-tools -Architecture: any +Architecture: linux-any Depends: libstlink1 (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} Description: OpenSource ST-Link tools replacement. Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers @@ -39,7 +39,7 @@ Description: OpenSource ST-Link tools replacement. udev rules. Package: stlink-gui -Architecture: any +Architecture: linux-any Depends: libstlink1 (= ${binary:Version}), stlink-tools (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} Description: OpenSource ST-Link tools replacement. From acd192fea0e440ee91a643321417a7665ad7f248 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Fri, 28 Sep 2018 10:26:46 +0100 Subject: [PATCH 0630/1435] Update changelog for 1.5.1+ds-1 release --- debian/changelog | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/debian/changelog b/debian/changelog index 798093c9e..b0c877388 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,11 @@ +stlink (1.5.1+ds-1) unstable; urgency=medium + + * Merge tag 'v1.5.1' into debian. See upstream changelog for info: + https://github.com/texane/stlink/releases/tag/v1.5.1 + * Mark packages as linux-any, other systems not supported. + + -- Luca Boccassi Fri, 28 Sep 2018 10:26:39 +0100 + stlink (1.5.0+ds-1) unstable; urgency=medium * Upload to unstable. (Closes: #869421) From 8a07f1276901e71a1df7ad0e664f80e73290048d Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Fri, 28 Sep 2018 18:48:04 +0100 Subject: [PATCH 0631/1435] Mark library packages as Multi-Arch: same. --- debian/control | 2 ++ 1 file changed, 2 insertions(+) diff --git a/debian/control b/debian/control index da8f69203..1499dcf1a 100644 --- a/debian/control +++ b/debian/control @@ -11,6 +11,7 @@ Vcs-Browser: https://github.com/bluca/stlink Package: libstlink-dev Section: libdevel Architecture: linux-any +Multi-Arch: same Depends: libstlink1 (= ${binary:Version}), ${misc:Depends} Description: OpenSource ST-Link tools replacement. Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers @@ -21,6 +22,7 @@ Description: OpenSource ST-Link tools replacement. Package: libstlink1 Section: libs Architecture: linux-any +Multi-Arch: same Depends: ${shlibs:Depends}, ${misc:Depends} Description: OpenSource ST-Link tools replacement. Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers From 8c46827f543375a4edb362e893b2fa26afcbe511 Mon Sep 17 00:00:00 2001 From: Gabriel Arjones Date: Wed, 24 Oct 2018 14:33:02 -0300 Subject: [PATCH 0632/1435] Make udev rules and modprobe conf installation optional (#741) --- CMakeLists.txt | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 395848b0a..a36803ee0 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -23,6 +23,8 @@ else() endif() option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) +option(STLINK_INSTALL_UDEV_RULES "Install udev rules files" ON) +option(STLINK_INSTALL_MODPROBE_CONF "Install modprobe conf files" ON) if (POLICY CMP0042) # Newer cmake on MacOS should use @rpath @@ -196,11 +198,15 @@ install(TARGETS st-flash st-info ) if (CMAKE_SYSTEM_NAME STREQUAL "Linux") - file(GLOB RULES_FILES etc/udev/rules.d/*.rules) - install(FILES etc/modprobe.d/stlink_v1.conf - DESTINATION ${STLINK_MODPROBED_DIR}/) - install(FILES ${RULES_FILES} - DESTINATION ${STLINK_UDEV_RULES_DIR}/) + if (STLINK_INSTALL_MODPROBE_CONF) + install(FILES etc/modprobe.d/stlink_v1.conf + DESTINATION ${STLINK_MODPROBED_DIR}/) + endif() + if (STLINK_INSTALL_UDEV_RULES) + file(GLOB RULES_FILES etc/udev/rules.d/*.rules) + install(FILES ${RULES_FILES} + DESTINATION ${STLINK_UDEV_RULES_DIR}/) + endif() endif() add_subdirectory(src/gdbserver) From e059ea7a5579bc41b88bdada376cfeed5e4ca988 Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Tue, 30 Oct 2018 18:56:36 +0200 Subject: [PATCH 0633/1435] Fix case when __FILE__ don't contain "/" nor "\\". (#745) --- include/stlink/logging.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/stlink/logging.h b/include/stlink/logging.h index 16ed948a4..da5f7d19d 100644 --- a/include/stlink/logging.h +++ b/include/stlink/logging.h @@ -20,7 +20,8 @@ int ugly_init(int maximum_threshold); int ugly_log(int level, const char *tag, const char *format, ...); #define UGLY_LOG_FILE (strstr(__FILE__, "/") != NULL ? \ - strrchr(__FILE__, '/') + 1 : strrchr(__FILE__, '\\') + 1) + strrchr(__FILE__, '/') + 1 : strstr(__FILE__, "\\") != NULL ? \ + strrchr(__FILE__, '\\') + 1 : __FILE__) /** @todo we need to write this in a more generic way, for now this should compile on visual studio (See http://stackoverflow.com/a/8673872/1836746) */ From f87076fcbfbaef80edc5fc54e179a6b4a9629159 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Mon, 19 Nov 2018 20:45:50 +0100 Subject: [PATCH 0634/1435] doc/man: Fix double dash issue (fixes #746) --- doc/man/st-flash.1 | 64 ++++++++++++++++----------------------------- doc/man/st-flash.md | 10 +++---- doc/man/st-info.1 | 44 +++++++++---------------------- doc/man/st-info.md | 18 ++++++------- doc/man/st-util.1 | 60 ++++++++++++++---------------------------- doc/man/st-util.md | 20 +++++++------- 6 files changed, 80 insertions(+), 136 deletions(-) diff --git a/doc/man/st-flash.1 b/doc/man/st-flash.1 index 1ee272957..6bd206069 100644 --- a/doc/man/st-flash.1 +++ b/doc/man/st-flash.1 @@ -1,4 +1,4 @@ -.\" Automatically generated by Pandoc 2.1.1 +.\" Automatically generated by Pandoc 2.4 .\" .TH "st\-flash" "1" "Feb 2018" "Open Source STMicroelectronics Stlink Tools" "stlink" .hy @@ -7,92 +7,74 @@ st\-flash \- Flash binary files to STM32 device .SH SYNOPSIS .PP -\f[I]st\-flash\f[] [\f[I]OPTIONS\f[]] {read|write|erase} [\f[I]FILE\f[]] - +\f[I]st\-flash\f[R] [\f[I]OPTIONS\f[R]] {read|write|erase} +[\f[I]FILE\f[R]] .SH DESCRIPTION .PP Flash binary files to arbitrary sections of memory, or read arbitrary addresses of memory out to a binary file. .PP You can use this instead of st\-util(1) if you prefer, but remember to -use the \f[B].bin\f[] image, rather than the \f[B].elf\f[] file. +use the \f[B].bin\f[R] image, rather than the \f[B].elf\f[R] file. .PP -Use hexadecimal format for the \f[I]ADDR\f[] and \f[I]SIZE\f[]. +Use hexadecimal format for the \f[I]ADDR\f[R] and \f[I]SIZE\f[R]. .SH COMMANDS .TP -.B write \f[I]FILE\f[] \f[I]ADDR\f[] -Write firmware \f[I]FILE\f[] to device starting from \f[I]ADDR\f[] -.RS -.RE +.B write \f[I]FILE\f[R] \f[I]ADDR\f[R] +Write firmware \f[I]FILE\f[R] to device starting from \f[I]ADDR\f[R] .TP -.B read \f[I]FILE\f[] \f[I]ADDR\f[] \f[I]SIZE\f[] -Read firmware from device starting from \f[I]ADDR\f[] up to -\f[I]SIZE\f[] bytes to \f[I]FILE\f[] -.RS -.RE +.B read \f[I]FILE\f[R] \f[I]ADDR\f[R] \f[I]SIZE\f[R] +Read firmware from device starting from \f[I]ADDR\f[R] up to +\f[I]SIZE\f[R] bytes to \f[I]FILE\f[R] .TP .B erase Perform a mass erasing of the device firmware -.RS -.RE .TP .B reset Reset the target -.RS -.RE .SH OPTIONS .TP -.B \f[C]\-\-version\f[] +.B \-\-version Print version information -.RS -.RE .TP -.B \f[C]\-\-debug\f[] +.B \-\-debug TODO -.RS -.RE .TP -.B \f[C]\-\-reset\f[] +.B \-\-reset TODO -.RS -.RE .TP -.B \f[C]\-\-serial\f[] \f[I]iSerial\f[] +.B \-\-serial \f[I]iSerial\f[R] TODO -.RS -.RE .TP -.B \f[C]\-\-flash=fsize\f[] +.B \-\-flash=fsize Where fsize is the size in decimal, octal, or hex followed by an optional multiplier `k' for KB, or `m' for MB. Use a leading \[lq]0x\[rq] to specify hexadecimal, or a leading zero for octal. -.RS -.RE .SH EXAMPLES .PP -Flash \f[C]firmware.bin\f[] to device +Flash \f[C]firmware.bin\f[R] to device .IP .nf \f[C] -$\ st\-flash\ write\ firmware.bin\ 0x8000000 -\f[] +$ st\-flash write firmware.bin 0x8000000 +\f[R] .fi .PP Read firmware from device (4096 bytes) .IP .nf \f[C] -$\ st\-flash\ read\ firmware.bin\ 0x8000000\ 4096 -\f[] +$ st\-flash read firmware.bin 0x8000000 4096 +\f[R] .fi .PP Erase firmware from device .IP .nf \f[C] -$\ st\-flash\ erase -\f[] +$ st\-flash erase +\f[R] .fi .SH SEE ALSO .PP @@ -101,4 +83,4 @@ st\-util(1), st\-info(1) .PP This work is copyrighted. Stlink contributors. -See \f[I]LICENSE\f[] file in the stlink source distribution. +See \f[I]LICENSE\f[R] file in the stlink source distribution. diff --git a/doc/man/st-flash.md b/doc/man/st-flash.md index e617e4305..ae6c88f46 100644 --- a/doc/man/st-flash.md +++ b/doc/man/st-flash.md @@ -36,19 +36,19 @@ reset # OPTIONS -`--version` +\--version : Print version information -`--debug` +\--debug : TODO -`--reset` +\--reset : TODO -`--serial` *iSerial* +\--serial *iSerial* : TODO -`--flash=fsize` +\--flash=fsize : Where fsize is the size in decimal, octal, or hex followed by an optional multiplier 'k' for KB, or 'm' for MB. Use a leading "0x" to specify hexadecimal, or a leading zero for octal. diff --git a/doc/man/st-info.1 b/doc/man/st-info.1 index a774d3ade..a0380f851 100644 --- a/doc/man/st-info.1 +++ b/doc/man/st-info.1 @@ -1,4 +1,4 @@ -.\" Automatically generated by Pandoc 2.1.1 +.\" Automatically generated by Pandoc 2.4 .\" .TH "st\-flash" "1" "Feb 2018" "Open Source STMicroelectronics Stlink Tools" "stlink" .hy @@ -8,7 +8,7 @@ st\-info \- Provides information about connected STLink and STM32 devices .SH SYNOPSIS .PP -\f[I]st\-info\f[] [\f[I]OPTIONS\f[]] +\f[I]st\-info\f[R] [\f[I]OPTIONS\f[R]] .SH DESCRIPTION .PP Provides information about connected STLink programmers and STM32 @@ -18,57 +18,39 @@ description. .TP .B \[en]version Print version information -.RS -.RE .TP -.B \[en]flash +.B \-\-flash Display amount of flash memory available in the device -.RS -.RE .TP -.B \[en]sram +.B \-\-sram Display amount of sram memory available in device -.RS -.RE .TP -.B \[en]descr +.B \-\-descr Display textual description of the device -.RS -.RE .TP -.B \[en]pagesize +.B \-\-pagesize Display the page size of the device -.RS -.RE .TP -.B \[en]chipid +.B \-\-chipid Display the chip ID of the device -.RS -.RE .TP -.B \[en]serial +.B \-\-serial Display the serial code of the device -.RS -.RE .TP -.B \[en]hla\-serial +.B \-\-hla\-serial Display the hex escaped serial code of the device -.RS -.RE .TP -.B \[en]probe +.B \-\-probe Display the summarized information of the connected programmers and devices -.RS -.RE .SH EXAMPLES .PP Display information about connected programmers and devices .IP .nf \f[C] -$\ st\-info\ \-\-probe -\f[] +$ st\-info \-\-probe +\f[R] .fi .SH SEE ALSO .PP @@ -77,4 +59,4 @@ st\-util(1), st\-flash(1) .PP This work is copyrighted. Stlink contributors. -See \f[I]LICENSE\f[] file in the stlink source distribution. +See \f[I]LICENSE\f[R] file in the stlink source distribution. diff --git a/doc/man/st-info.md b/doc/man/st-info.md index 1a0773e74..67d9373d7 100644 --- a/doc/man/st-info.md +++ b/doc/man/st-info.md @@ -17,31 +17,31 @@ Serial code, openocd, flash, sram, page size, chipid, description. # OPTIONS ---version +\--version : Print version information ---flash +\--flash : Display amount of flash memory available in the device ---sram +\--sram : Display amount of sram memory available in device ---descr +\--descr : Display textual description of the device ---pagesize +\--pagesize : Display the page size of the device ---chipid +\--chipid : Display the chip ID of the device ---serial +\--serial : Display the serial code of the device ---hla-serial +\--hla-serial : Display the hex escaped serial code of the device ---probe +\--probe : Display the summarized information of the connected programmers and devices diff --git a/doc/man/st-util.1 b/doc/man/st-util.1 index a7b2eb6cf..9b46b4d65 100644 --- a/doc/man/st-util.1 +++ b/doc/man/st-util.1 @@ -1,4 +1,4 @@ -.\" Automatically generated by Pandoc 2.1.1 +.\" Automatically generated by Pandoc 2.4 .\" .TH "st\-util" "1" "Feb 2018" "Open Source STMicroelectronics Stlink Tools" "stlink" .hy @@ -7,83 +7,63 @@ st\-util \- Run GDB server to interact with STM32 device .SH SYNOPSIS .PP -\f[I]st\-util\f[] [\&...] +\f[I]st\-util\f[R] [\&...] .SH DESCRIPTION .PP Start a GDB server to interact with a STM32 device Run the main binary of the local package (src/main.rs). .PP -If a port number is not specified using the \f[B]\[en]listen_port\f[] -option, the default \f[B]4242\f[] port will be used. +If a port number is not specified using the \f[B]\[en]listen_port\f[R] +option, the default \f[B]4242\f[R] port will be used. .PP Stlink version 2 is used by default unless the option -\f[B]\[en]stlinkv1\f[] is given. +\f[B]\[en]stlinkv1\f[R] is given. .PP The STLinkV2 device to use can be specified in the environment variable STLINK_DEVICE on the format :. .SH OPTIONS .TP -.B \-h, \f[C]\-\-help\f[] +.B \-h, \-\-help Print this message. -.RS -.RE .TP -.B \f[C]\-\-version\f[] +.B \-\-version Print version information -.RS -.RE .TP -.B \-v \f[I]XX\f[], \f[C]\-\-verbose=XX\f[] +.B \-v \f[I]XX\f[R], \-\-verbose=XX Specify a specific verbosity level (0..99) -.RS -.RE .TP -.B \-v, \f[C]\-\-verbose\f[] +.B \-v, \-\-verbose Specify generally verbose logging -.RS -.RE .TP -.B \-s \f[I]X\f[], \f[C]\-\-stlink_version=X\f[] +.B \-s \f[I]X\f[R], \-\-stlink_version=X Choose what version of stlink to use, (defaults to 2) -.RS -.RE .TP -.B \-1, \f[C]\-\-stlinkv1\f[] +.B \-1, \-\-stlinkv1 Force stlink version 1 -.RS -.RE .TP -.B \-p \f[I]4242\f[], \f[C]\-\-listen_port=1234\f[] +.B \-p \f[I]4242\f[R], \-\-listen_port=1234 Set the gdb server listen port. (default port: 4242) -.RS -.RE .TP -.B \-m, \f[C]\-\-multi\f[] +.B \-m, \-\-multi Set gdb server to extended mode. st\-util will continue listening for connections after disconnect. -.RS -.RE .TP -.B \-n, \f[C]\-\-no\-reset\f[] +.B \-n, \-\-no\-reset Do not reset board on connection. -.RS -.RE .TP -.B \f[C]\-\-semihosting\f[] +.B \-\-semihosting Enable ARM Semihosting output on stdout -.RS -.RE .SH EXAMPLES .PP Run GDB server on port 4500 and connect to it .IP .nf \f[C] -$\ st\-util\ \-p\ 4500 -$\ gdb -(gdb)\ target\ extended\-remote\ localhost:4500 -\f[] +$ st\-util \-p 4500 +$ gdb +(gdb) target extended\-remote localhost:4500 +\f[R] .fi .SH SEE ALSO .PP @@ -92,4 +72,4 @@ st\-flash(1), st\-info(1) .PP This work is copyrighted. Stlink contributors. -See \f[I]LICENSE\f[] file in the stlink source distribution. +See \f[I]LICENSE\f[R] file in the stlink source distribution. diff --git a/doc/man/st-util.md b/doc/man/st-util.md index b141091f9..e62261213 100644 --- a/doc/man/st-util.md +++ b/doc/man/st-util.md @@ -24,34 +24,34 @@ variable STLINK_DEVICE on the format :. # OPTIONS --h, `--help` +-h, \--help : Print this message. -`--version` +\--version : Print version information --v *XX*, `--verbose=XX` +-v *XX*, \--verbose=*XX* : Specify a specific verbosity level (0..99) --v, `--verbose` +-v, \--verbose : Specify generally verbose logging --s *X*, `--stlink_version=X` +-s *X*, \--stlink_version=*X* : Choose what version of stlink to use, (defaults to 2) --1, `--stlinkv1` +-1, \--stlinkv1 : Force stlink version 1 --p *4242*, `--listen_port=1234` +-p *4242*, \--listen_port=1234 : Set the gdb server listen port. (default port: 4242) --m, `--multi` +-m, \--multi : Set gdb server to extended mode. st-util will continue listening for connections after disconnect. --n, `--no-reset` +-n, \--no-reset : Do not reset board on connection. -`--semihosting` +\--semihosting : Enable ARM Semihosting output on stdout # EXAMPLES From a201d3e5bd4a52a6e2a7f89947688f580c2b3554 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sun, 2 Dec 2018 21:25:02 +0100 Subject: [PATCH 0635/1435] Update compiling.md Fixes #748 --- doc/compiling.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/compiling.md b/doc/compiling.md index 41d1fb7f9..e613965a3 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -43,7 +43,7 @@ $ cd build/Release; sudo make install * Debian based distros (debian, ubuntu) * `build-essential` * `cmake` -* `libusb-1.0` (plus development headers for building, on debian based distros `libusb-1.0.0-dev` package) +* `libusb-1.0` (plus development headers for building, on debian based distros `libusb-1.0-0-dev` package) * (optional) for `stlink-gui` we need libgtk-3-dev ### Fixing cannot open shared object file From 0a2b7a4ff076b877155a76d5000be14a73bf524b Mon Sep 17 00:00:00 2001 From: Dave Hylands Date: Fri, 14 Dec 2018 14:31:23 -0500 Subject: [PATCH 0636/1435] Only do bank calculation on STM32L4 devices with dual banked flash (#751) * Only do bank calculatio on SRM32L4 devices with dual banked flash RM0394 covers the STM32L41xx, 42xx, 43xx, 44xx, 45xx, and 46xx. These devices are all employ single banked flash and have chip id's of 0x464 for the 41xx/42xx, 0x435 for 43xx/44xx, and 0x462 for 45xx/46xx It's also worth noting that bit 21 of the FLASH_OPTR register is marked as resevred for these chips, and isn't an indicator of dual banked flash. RM0392 covers the STM32L4x1, cpu_id 0x415 and can be dual banked. RM0351 covers the STM32L4x5/4x6, cpu_ids 0x415 & 0x461 and can be dual banked RM0432 covers the STM32L4Rx/4Sx, cpu_id 0x470 and can be dual banked. This PR modifies the calculate_L4_page functio to only factor bank calculations for the devices above which can support dual banked flash. * Converted tabs to spaces on added line --- include/stlink/chipid.h | 2 ++ src/common.c | 16 +++++++++++----- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 004fa2e80..d28527aba 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -40,10 +40,12 @@ enum stlink_stm32_chipids { * 0x435 covers STM32L43xxx and STM32L44xxx devices * 0x461 covers STM32L496xx and STM32L4A6xx devices * 0x462 covers STM32L45xxx and STM32L46xxx devices + * 0x464 covers STM32L41xxx and STM32L42xxx devices */ STLINK_CHIPID_STM32_L43X = 0x435, STLINK_CHIPID_STM32_L496X = 0x461, STLINK_CHIPID_STM32_L46X = 0x462, + STLINK_CHIPID_STM32_L41X = 0x464, /* * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus" * and some that are called "High". 0x427 is assigned to the other "Medium- diff --git a/src/common.c b/src/common.c index 40a689c7e..fa2a4607a 100644 --- a/src/common.c +++ b/src/common.c @@ -1436,13 +1436,19 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { uint32_t flashopt; stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); flashaddr -= STM32_FLASH_BASE; - if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) { - uint32_t banksize = (uint32_t) sl->flash_size / 2; - if (flashaddr >= banksize) { - flashaddr -= banksize; - bker = 0x100; + if (sl->chip_id == STLINK_CHIPID_STM32_L4 || + sl->chip_id == STLINK_CHIPID_STM32_L496X || + sl->chip_id == STLINK_CHIPID_STM32_L4RX) { + // This chip use dual banked flash + if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) { + uint32_t banksize = (uint32_t) sl->flash_size / 2; + if (flashaddr >= banksize) { + flashaddr -= banksize; + bker = 0x100; + } } } + // For 1MB chips without the dual-bank option set, the page address will // overflow into the BKER bit, which gives us the correct bank:page value. return bker | flashaddr/sl->flash_pgsz; From 358a91395d957ad626390fbbfcaec065cb49c532 Mon Sep 17 00:00:00 2001 From: Jiri Bilek Date: Fri, 21 Dec 2018 12:54:56 +0100 Subject: [PATCH 0637/1435] Add O_BINARY option to open file. (#753) See issue #752. --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index fa2a4607a..0a74bb2af 100644 --- a/src/common.c +++ b/src/common.c @@ -1364,7 +1364,7 @@ int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr int error; - int fd = open(path, O_RDWR | O_TRUNC | O_CREAT, 00700); + int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); if (fd == -1) { fprintf(stderr, "open(%s) == -1\n", path); return -1; From 7651d2116fd74c7803ea00ab1da7cf3d00faf44c Mon Sep 17 00:00:00 2001 From: Victor Lamoine Date: Thu, 3 Jan 2019 21:10:47 +0100 Subject: [PATCH 0638/1435] Add support for CS32 micro-controller (#757) --- include/stlink.h | 1 + src/flash_loader.c | 1 + 2 files changed, 2 insertions(+) diff --git a/include/stlink.h b/include/stlink.h index ac0bfe190..4d321133d 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -53,6 +53,7 @@ extern "C" { /* cortex core ids */ // TODO clean this up... #define STM32VL_CORE_ID 0x1ba01477 +#define CS32_CORE_ID 0x2ba01477 #define STM32F7_CORE_ID 0x5ba02477 // Constant STM32 memory map figures diff --git a/src/flash_loader.c b/src/flash_loader.c index 7684680a7..25c11e465 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -262,6 +262,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID + || sl->core_id == CS32_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F3 || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH From 6a9d390a729f381ecec45f212354bfe98e27790f Mon Sep 17 00:00:00 2001 From: WRansohoff Date: Sun, 13 Jan 2019 00:04:21 -0800 Subject: [PATCH 0639/1435] Update STM32F3xx chip ID that covers a few different devices. (#758) --- src/chipid.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/chipid.c b/src/chipid.c index 6f93af112..f1dbb633f 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -403,10 +403,10 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x1000 }, { - // STM32F334 - // RM0364 document was used to find these parameters + // STM32F334, STM32F303x6/8, and STM32F328 + // From RM0364 and RM0316 .chip_id = STLINK_CHIPID_STM32_F334, - .description = "F334 device", + .description = "F3xx medium density device", // (RM0316 sec 33.6.1) .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, From 0f1fc5042986b3f65ded2e1599434f7cc5a77e24 Mon Sep 17 00:00:00 2001 From: WRansohoff Date: Thu, 24 Jan 2019 12:25:25 -0800 Subject: [PATCH 0640/1435] Add preliminary support for some STM32G0 chips. (closes #759) (#760) * Add preliminary support for some STM32G0 chips. * Fix a bug in the 'which page to erase' logic. When I flashed a program with more than one page, I noticed that this logic did not un-set previously-set 'PNG' bits. So it would erase page 1, then page 3, then page 3... --- include/stlink.h | 1 + include/stlink/chipid.h | 3 +- src/chipid.c | 11 ++++ src/common.c | 118 +++++++++++++++++++++++++++++++++++++++- 4 files changed, 131 insertions(+), 2 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index 4d321133d..0f2f5bb51 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -86,6 +86,7 @@ extern "C" { STLINK_FLASH_TYPE_F4, STLINK_FLASH_TYPE_L4, STLINK_FLASH_TYPE_F1_XL, + STLINK_FLASH_TYPE_G0, }; struct stlink_reg { diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index d28527aba..dda437ce7 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -70,7 +70,8 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, STLINK_CHIPID_STM32_F413 = 0x463, - STLINK_CHIPID_STM32_L4RX = 0x470 // taken from the STM32L4R9I-DISCO board + STLINK_CHIPID_STM32_L4RX = 0x470, // taken from the STM32L4R9I-DISCO board + STLINK_CHIPID_STM32_G0X1 = 0x460 }; /** diff --git a/src/chipid.c b/src/chipid.c index f1dbb633f..4e04f00cc 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -507,6 +507,17 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1ff00000, .bootrom_size = 0x2000 }, + { + // STM32G071/081 (from RM0444) + .chip_id = STLINK_CHIPID_STM32_G0X1, + .description = "G071/G081 device", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2K (sec 3.2) + .sram_size = 0x9000, // 36K (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 // 30K (table 2) + }, { // unknown .chip_id = STLINK_CHIPID_UNKNOWN, diff --git a/src/common.c b/src/common.c index 0a74bb2af..38047d0d8 100644 --- a/src/common.c +++ b/src/common.c @@ -74,6 +74,23 @@ #define FLASH_L1_FPRG 10 #define FLASH_L1_PROG 3 +// G0 (RM0444 Table 1, sec 3.7) +#define STM32G0_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define STM32G0_FLASH_ACR (STM32G0_FLASH_REGS_ADDR + 0x00) +#define STM32G0_FLASH_KEYR (STM32G0_FLASH_REGS_ADDR + 0x08) +#define STM32G0_FLASH_OPTKEYR (STM32G0_FLASH_REGS_ADDR + 0x0c) +#define STM32G0_FLASH_SR (STM32G0_FLASH_REGS_ADDR + 0x10) +#define STM32G0_FLASH_CR (STM32G0_FLASH_REGS_ADDR + 0x14) +#define STM32G0_FLASH_ECCR (STM32G0_FLASH_REGS_ADDR + 0x18) +#define STM32G0_FLASH_OPTR (STM32G0_FLASH_REGS_ADDR + 0x20) +#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) +#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) +#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) +#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) +#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) +#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) +#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) + //32L4 register base is at FLASH_REGS_ADDR (0x40022000) #define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) #define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) @@ -1601,6 +1618,47 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + uint32_t val; + /* check if the locks are set */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + if ((val & (1<<31))) { + /* disable flash write protection. */ + stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0x45670123); + stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0xCDEF89AB); + /* check that the lock is no longer set. */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + if ((val & (1 << 31))) { + WLOG("pecr.pelock not clear (%#x)\n", val); + return -1; + } + } + /* Set PER (erase) bit. */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + val |= 0x00000002; + stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + /* Set the page to erase. */ + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. + val = ((flash_page & 0x3F) << 3) | (2); + stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + /* Set the 'start' bit. */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + val |= (1 << 16); + stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + /* Wait for 'busy' bit in FLASH_SR to clear. */ + do { + stlink_read_debug32(sl, STM32G0_FLASH_SR, &val); + } while ((val & (1 << 16)) != 0); + /* Clear PER ('erase enable') bit. */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + val &= ~(0x00000002); + stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + /* Re-lock the flash. */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + val |= 0x80000000; + stlink_write_debug32(sl, STM32G0_FLASH_CR, val); } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr < FLASH_BANK2_START_ADDR))) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1654,7 +1712,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + /* TODO: User MER bit to mass-erase G0 series. */ + if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_G0) { /* erase each page */ int i = 0, num_pages = (int) sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1925,7 +1984,64 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t lock_flash(sl); } //STM32F4END + else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + uint32_t val; + /* Unlock flash. */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + if ((val & (1<<31))) { + /* disable flash write protection. */ + stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0x45670123); + stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0xCDEF89AB); + /* check that the lock is no longer set. */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + if ((val & (1 << 31))) { + WLOG("pecr.pelock not clear (%#x)\n", val); + return -1; + } + } + /* Set PG 'allow programming' bit. */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + val |= 0x00000001; + stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + /* Write all words. */ + off = 0; + for ( ; off < len; off += sizeof(uint32_t)) { + uint32_t data; + if (off > 254) + fprintf(stdout, "\r"); + if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off/sl->flash_pgsz), + (unsigned int)(len/sl->flash_pgsz)); + fflush(stdout); + } + write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); + stlink_write_debug32(sl, addr + (uint32_t) off, data); + /* Wait for 'busy' bit in FLASH_SR to clear. */ + do { + stlink_read_debug32(sl, STM32G0_FLASH_SR, &val); + } while ((val & (1 << 16)) != 0); + } + /* Do we need a dummy write? See sec 3.3.8 of RM0444. */ + /* (Flash writes happen 2 words at a time.) */ + if ((off / sizeof(uint32_t)) % 2 != 0) { + /* Write a single word of zeros. */ + stlink_write_debug32(sl, addr + (uint32_t) off, 0); + /* Wait for 'busy' bit in FLASH_SR to clear. */ + do { + stlink_read_debug32(sl, STM32G0_FLASH_SR, &val); + } while ((val & (1 << 16)) != 0); + } + /* Reset PG bit. */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + val &= ~(0x00000001); + stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + /* Re-lock flash. */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + val |= 0x80000000; + stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { /* use fast word write. todo: half page. */ uint32_t val; From af325bb989e3072984abd905059a7790afe965b2 Mon Sep 17 00:00:00 2001 From: Thomas Cenova Date: Thu, 24 Jan 2019 15:27:08 -0500 Subject: [PATCH 0641/1435] This fixes the versioning when compiling from the repo checked out with git. (#762) --- cmake/Version.cmake | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/cmake/Version.cmake b/cmake/Version.cmake index bb01315ab..e74d775d6 100644 --- a/cmake/Version.cmake +++ b/cmake/Version.cmake @@ -6,7 +6,7 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") # Working off a git repo, using git versioning # Check if HEAD is pointing to a tag execute_process ( - COMMAND "${GIT_EXECUTABLE}" describe --always + COMMAND "${GIT_EXECUTABLE}" describe --always --tag WORKING_DIRECTORY "${PROJECT_SOURCE_DIR}" OUTPUT_VARIABLE PROJECT_VERSION OUTPUT_STRIP_TRAILING_WHITESPACE) @@ -21,6 +21,9 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") set (PROJECT_VERSION "${PROJECT_VERSION}-dirty") endif() + # strip a leading v off of the version as proceeding code expectes just the version numbering. + string(REGEX REPLACE "^v" "" PROJECT_VERSION ${PROJECT_VERSION}) + string(REGEX REPLACE "^(0|[1-9][0-9]*)[.](0|[1-9][0-9]*)[.](0|[1-9][0-9]*)(-[.0-9A-Za-z-]+)?([+][.0-9A-Za-z-]+)?$" "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) list(LENGTH PROJECT_VERSION_LIST len) From 30de1b30e7a96974ae764d0508c151eadb1addd1 Mon Sep 17 00:00:00 2001 From: Jicksaw Date: Thu, 24 Jan 2019 22:29:59 +0200 Subject: [PATCH 0642/1435] Fix "unkown chip id", piped output and st-util -v (#763) * Set SWD clock before using SWD (#107, #568 ?) * Make st-util -v print more than default * Flush output streams explicitly. Fix #665 On Win32 redirecting streams makes them buffered, therefore without flushing there would be no output before exit. Stdout and stderr are also often buffered differently, making them disordered. --- src/gdbserver/gdb-server.c | 2 +- src/logging.c | 5 +++++ src/usb.c | 6 +++--- 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 7bf3a275f..6e64dd073 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -151,7 +151,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { if (optarg) { st->logging_level = atoi(optarg); } else { - st->logging_level = DEFAULT_LOGGING_LEVEL; + st->logging_level = DEBUG_LOGGING_LEVEL; } break; case '1': diff --git a/src/logging.c b/src/logging.c index b5e423a3a..d4fb96b2e 100644 --- a/src/logging.c +++ b/src/logging.c @@ -22,6 +22,10 @@ int ugly_log(int level, const char *tag, const char *format, ...) { if (level > max_level) { return 0; } + + // Flush to maintain order of streams + fflush(stdout); + va_list args; va_start(args, format); time_t mytt = time(NULL); @@ -46,6 +50,7 @@ int ugly_log(int level, const char *tag, const char *format, ...) { break; } vfprintf(stderr, format, args); + fflush(stderr); va_end(args); return 1; } diff --git a/src/usb.c b/src/usb.c index 3e0596f18..66f065ab8 100644 --- a/src/usb.c +++ b/src/usb.c @@ -923,6 +923,9 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 // Initialize stlink version (sl->version) stlink_version(sl); + // Set the stlink clock speed (default is 1800kHz) + stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); + if (reset) { if( sl->version.stlink_v > 1 ) stlink_jtag_reset(sl, 2); stlink_reset(sl); @@ -931,9 +934,6 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 ret = stlink_load_device_params(sl); - // Set the stlink clock speed (default is 1800kHz) - stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); - on_libusb_error: if (ret == -1) { stlink_close(sl); From 8186d854bac19c530e2d392d86d9c0b5870175a1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Mellstr=C3=B6m?= Date: Sat, 9 Feb 2019 11:10:15 +0100 Subject: [PATCH 0643/1435] Add support for mass erasing second bank on STM32F10x_XL (#767) --- src/common.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/src/common.c b/src/common.c index 38047d0d8..df3837c0e 100644 --- a/src/common.c +++ b/src/common.c @@ -380,6 +380,20 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { stlink_write_debug32(sl, cr_reg, val); } +static void set_flash_cr2_mer(stlink_t *sl, bool v) { + const uint32_t cr_pg = 1 << FLASH_CR_PER; + const uint32_t cr_mer = 1 << FLASH_CR_MER; + uint32_t val; + + stlink_read_debug32(sl, FLASH_CR2, &val); + val &= ~cr_pg; + if (v) + val |= cr_mer; + else + val &= ~cr_mer; + stlink_write_debug32(sl, FLASH_CR2, val); +} + static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { uint32_t val, cr_reg, cr_mer; @@ -1740,6 +1754,14 @@ int stlink_erase_flash_mass(stlink_t *sl) { /* start erase operation, reset by hw with bsy bit */ set_flash_cr_strt(sl); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + /* set the mass erase bit in bank 2 */ + set_flash_cr2_mer(sl,1); + + /* start erase operation in bank 2 */ + set_flash_cr2_strt(sl); + } + /* wait for completion */ wait_flash_busy_progress(sl); @@ -1749,6 +1771,11 @@ int stlink_erase_flash_mass(stlink_t *sl) { /* reset the mass erase bit */ set_flash_cr_mer(sl,0); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + /* reset the mass erase bit in bank 2 */ + set_flash_cr2_mer(sl,0); + } + /* todo: verify the erased memory */ } return 0; From b9c315d990abfde3008a917e767c63d2c1c1ddf2 Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Sat, 9 Feb 2019 13:11:43 +0300 Subject: [PATCH 0644/1435] win32: move usleep definition to unistd.h (#765) --- src/gdbserver/gdb-server.c | 4 ++-- src/mingw/mingw.c | 6 ++++-- src/mingw/mingw.h | 5 ----- src/win32/unistd.h | 4 ++++ 4 files changed, 10 insertions(+), 9 deletions(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 6e64dd073..8566b792e 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -254,8 +254,8 @@ int main(int argc, char** argv) { do { if (serve(sl, &state)) { - sleep (1); // don't go bezurk if serve returns with error - } + usleep (1 * 1000); // don't go bezurk if serve returns with error + } /* in case serve() changed the connection */ sl = connected_stlink; diff --git a/src/mingw/mingw.c b/src/mingw/mingw.c index aee288d88..bfdd3dcff 100644 --- a/src/mingw/mingw.c +++ b/src/mingw/mingw.c @@ -272,7 +272,7 @@ char *win32_strsep (char **stringp, const char *delim) } #ifndef STLINK_HAVE_UNISTD_H -void usleep(DWORD waitTime) +int usleep(unsigned int waitTime) { if (waitTime >= 1000) { @@ -288,7 +288,7 @@ void usleep(DWORD waitTime) SetWaitableTimer(timer, &dueTime, 0, NULL, NULL, 0); WaitForSingleObject(timer, INFINITE); CloseHandle(timer); - return; + return 0; } LARGE_INTEGER perf_cnt, start, now; @@ -298,6 +298,8 @@ void usleep(DWORD waitTime) do { QueryPerformanceCounter((LARGE_INTEGER*) &now); } while ((now.QuadPart - start.QuadPart) / (float)perf_cnt.QuadPart * 1000 * 1000 < waitTime); + + return 0; } #endif diff --git a/src/mingw/mingw.h b/src/mingw/mingw.h index 04907f7d6..2efd1ab34 100644 --- a/src/mingw/mingw.h +++ b/src/mingw/mingw.h @@ -71,9 +71,4 @@ char *win32_strsep(char **stringp, const char *delim); ssize_t win32_read_socket(SOCKET fd, void *buf, int n); ssize_t win32_write_socket(SOCKET fd, void *buf, int n); -#ifndef STLINK_HAVE_UNISTD_H -static inline void sleep(unsigned ms) { Sleep(ms); } -void usleep(DWORD waitTime); -#endif - #endif //defined(__MINGW32__) || defined(_MSC_VER) diff --git a/src/win32/unistd.h b/src/win32/unistd.h index 0b175fc07..4c94aed34 100644 --- a/src/win32/unistd.h +++ b/src/win32/unistd.h @@ -57,4 +57,8 @@ typedef unsigned __int16 uint16_t; typedef unsigned __int32 uint32_t; typedef unsigned __int64 uint64_t; +#ifndef STLINK_HAVE_UNISTD_H +int usleep(unsigned int waitTime); +#endif + #endif /* unistd.h */ From 3295ab4e5cf05cb546856414f1d40b5deedcf219 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Tue, 12 Feb 2019 21:07:35 +0100 Subject: [PATCH 0645/1435] Revert "Add support for CS32 micro-controller (#757)" (fixes #761) This reverts commit 7651d2116fd74c7803ea00ab1da7cf3d00faf44c. --- include/stlink.h | 1 - src/flash_loader.c | 1 - 2 files changed, 2 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index 0f2f5bb51..abacd127e 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -53,7 +53,6 @@ extern "C" { /* cortex core ids */ // TODO clean this up... #define STM32VL_CORE_ID 0x1ba01477 -#define CS32_CORE_ID 0x2ba01477 #define STM32F7_CORE_ID 0x5ba02477 // Constant STM32 memory map figures diff --git a/src/flash_loader.c b/src/flash_loader.c index 25c11e465..7684680a7 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -262,7 +262,6 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID - || sl->core_id == CS32_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F3 || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH From 1165cf712713af48c61c4782ad5c9477c4574708 Mon Sep 17 00:00:00 2001 From: Povilas Kanapickas Date: Sat, 16 Feb 2019 23:38:37 +0200 Subject: [PATCH 0646/1435] gui: Fix relative path to the UI files needed by stlink-gui-local (#771) --- src/tools/gui/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/tools/gui/CMakeLists.txt b/src/tools/gui/CMakeLists.txt index ceb862c33..c619a0547 100644 --- a/src/tools/gui/CMakeLists.txt +++ b/src/tools/gui/CMakeLists.txt @@ -9,7 +9,7 @@ include_directories(SYSTEM ${gtk_INCLUDE_DIRS}) add_executable(stlink-gui-local ${GUI_SOURCES}) set_target_properties(stlink-gui-local PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_CURRENT_SOURCE_DIR}/gui") + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_CURRENT_SOURCE_DIR}") target_link_libraries(stlink-gui-local ${STLINK_LIB_STATIC} ${gtk_LDFLAGS}) From d13f946468663fb101227c3f03f271037cfc2c2c Mon Sep 17 00:00:00 2001 From: aoand Date: Thu, 7 Mar 2019 14:41:38 +0300 Subject: [PATCH 0647/1435] doc/compiling.md: fix package name "devscripts" (#775) the command 'debuild' is (and always was) part of the devscripts package --- doc/compiling.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/compiling.md b/doc/compiling.md index e613965a3..74a8a34f5 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -83,7 +83,7 @@ Options (do one of these before you plug it in) ### Build Debian Package -To build the debian package you need the following extra packages: `debuild debhelper`. +To build the debian package you need the following extra packages: `devscripts debhelper`. ``` $ git archive --prefix=$(git describe)/ HEAD | bzip2 --stdout > ../libstlink_$(sed -En -e "s/.*\((.*)\).*/\1/" -e "1,1 p" debian/changelog).orig.tar.bz2 From 522188db496db059bfa8ae90b6d8417bbc08bb51 Mon Sep 17 00:00:00 2001 From: Ronny Majani Date: Thu, 7 Mar 2019 22:42:39 +1100 Subject: [PATCH 0648/1435] Added call to clear PG bit after Writing to Flash (#773) --- src/common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index df3837c0e..dab9a33c0 100644 --- a/src/common.c +++ b/src/common.c @@ -320,7 +320,7 @@ static void set_flash_cr_pg(stlink_t *sl) { stlink_write_debug32(sl, cr_reg, x); } -static void __attribute__((unused)) clear_flash_cr_pg(stlink_t *sl) { +static void clear_flash_cr_pg(stlink_t *sl) { uint32_t cr_reg, n; if (sl->flash_type == STLINK_FLASH_TYPE_F4) @@ -2008,6 +2008,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } /* Relock flash */ + clear_flash_cr_pg(sl); lock_flash(sl); } //STM32F4END From c9e09457555cd4462549b37d57005aad4ef9e614 Mon Sep 17 00:00:00 2001 From: Cerem Cem ASLAN Date: Fri, 15 Mar 2019 13:09:06 +0300 Subject: [PATCH 0649/1435] Added howto for sending NRST signal through GDB (#776) See https://github.com/texane/stlink/issues/774 --- README.md | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index a95698bdd..e30965277 100644 --- a/README.md +++ b/README.md @@ -113,9 +113,15 @@ Kill the program being debugged? (y or n) y Starting program: /home/whitequark/ST/apps/bally/firmware.elf ``` -Remember that you can shorten the commands. `tar ext :4242' is good enough +Remember that you can shorten the commands. `tar ext :4242` is good enough for GDB. +If you need to send a hard reset signal through `NRST` pin, you can use the following command: +`` +(gdb) monitor jtag_reset +``` + + ## Running programs from SRAM You can run your firmware directly from SRAM if you want to. Just link From 18ec7e239bb3e83a7888b19d984aa4f4e8830390 Mon Sep 17 00:00:00 2001 From: Cerem Cem ASLAN Date: Fri, 15 Mar 2019 21:34:39 +0300 Subject: [PATCH 0650/1435] fix typo (#779) --- README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index e30965277..4b8ed96dd 100644 --- a/README.md +++ b/README.md @@ -117,7 +117,8 @@ Remember that you can shorten the commands. `tar ext :4242` is good enough for GDB. If you need to send a hard reset signal through `NRST` pin, you can use the following command: -`` + +``` (gdb) monitor jtag_reset ``` From c6836b4ac9ff12c97ce909bc9a5a6784e1e97437 Mon Sep 17 00:00:00 2001 From: Manuel Dipolt Date: Wed, 20 Mar 2019 14:01:11 +0100 Subject: [PATCH 0651/1435] Added support to write option bytes for the STM32G0 (#778) * poc worked, writting stm32G070 option bytes * Update README.md adjust layout * code review changes --- README.md | 8 +++ include/stlink.h | 14 ++--- include/stm32.h | 19 +++++++ src/common.c | 128 ++++++++++++++++++++++++++++++++++++++++++++++ src/tools/flash.c | 8 +++ 5 files changed, 166 insertions(+), 11 deletions(-) create mode 100644 include/stm32.h diff --git a/README.md b/README.md index 4b8ed96dd..d711d323f 100644 --- a/README.md +++ b/README.md @@ -146,6 +146,14 @@ If you would link your executable to `0x08000000` and then do then it would be written to the memory. +## Writing Option Bytes + +Example to read and write option bytes (currently writing only supported for STM32G0) +``` +./st-flash --debug --reset --format binary --flash=128k read option_bytes_dump.bin 0x1FFF7800 4 +./st-flash --debug --reset --format binary --flash=128k write option_bytes_dump.bin 0x1FFF7800 +``` + ## FAQ Q: My breakpoints do not work at all or only work once. diff --git a/include/stlink.h b/include/stlink.h index abacd127e..fedeb1bf4 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -11,6 +11,8 @@ #include #include +#include "stm32.h" + #ifdef __cplusplus extern "C" { #endif @@ -50,15 +52,6 @@ extern "C" { #define STLINK_DEBUG_APIV2_SWD_SET_FREQ 0x43 - /* cortex core ids */ - // TODO clean this up... -#define STM32VL_CORE_ID 0x1ba01477 -#define STM32F7_CORE_ID 0x5ba02477 - - // Constant STM32 memory map figures -#define STM32_FLASH_BASE 0x08000000 -#define STM32_SRAM_BASE 0x20000000 - // Baud rate divisors for SWDCLK #define STLINK_SWDCLK_4MHZ_DIVISOR 0 #define STLINK_SWDCLK_1P8MHZ_DIVISOR 1 @@ -73,8 +66,6 @@ extern "C" { #define STLINK_SWDCLK_15KHZ_DIVISOR 265 #define STLINK_SWDCLK_5KHZ_DIVISOR 798 - - /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 @@ -205,6 +196,7 @@ typedef struct flash_loader { uint8_t stlink_get_erased_pattern(stlink_t *sl); int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); + int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); diff --git a/include/stm32.h b/include/stm32.h new file mode 100644 index 000000000..f5dbe4b2d --- /dev/null +++ b/include/stm32.h @@ -0,0 +1,19 @@ +/* + * File: stm32.h + * + * STM32 specific defines + */ + +#ifndef STM32_H +#define STM32_H + +// cortex core ids +#define STM32VL_CORE_ID 0x1ba01477 +#define STM32F7_CORE_ID 0x5ba02477 + +// Constant STM32 memory map figures +#define STM32_FLASH_BASE ((uint32_t)0x08000000) +#define STM32_SRAM_BASE ((uint32_t)0x20000000) +#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) + +#endif /* STM32_H */ diff --git a/src/common.c b/src/common.c index dab9a33c0..9bb2c2c4e 100644 --- a/src/common.c +++ b/src/common.c @@ -91,6 +91,20 @@ #define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) #define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) +// GO FLASH control register +#define STM32G0_FLASH_CR_PG 0 /* Program */ +#define STM32G0_FLASH_CR_PER 1 /* Page erase */ +#define STM32G0_FLASH_CR_MER1 2 /* Mass erase */ +#define STM32G0_FLASH_CR_PNB 3 /* Page number (5 bits) */ +#define STM32G0_FLASH_CR_STRT 16 /* Start */ +#define STM32G0_FLASH_CR_OPTSTRT 17 /* Start of modification of option bytes */ +#define STM32G0_FLASH_CR_FSTPG 18 /* Fast programming */ +#define STM32G0_FLASH_CR_EOPIE 24 /* End of operation interrupt enable */ +#define STM32G0_FLASH_CR_ERRIE 25 /* Error interrupt enable */ +#define STM32G0_FLASH_CR_OBL_LAUNCH 27 /* Forces the option byte loading */ +#define STM32G0_FLASH_CR_OPTLOCK 30 /* Options Lock */ +#define STM32G0_FLASH_CR_LOCK 31 /* FLASH_CR Lock*/ + //32L4 register base is at FLASH_REGS_ADDR (0x40022000) #define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) #define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) @@ -2407,3 +2421,117 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { unmap_file(&mf); return err; } + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { + + uint32_t val; + + if(len != 4) { + ELOG("Wrong length for writting option bytes, must be 4 is %d\n", len); + return -1; + } + + // Make sure we've loaded the context with the chip details + stlink_core_id(sl); + + /* Check if chip is supported and for correct address */ + if((sl->chip_id != STLINK_CHIPID_STM32_G0X1) || (addr != STM32_G0_OPTION_BYTES_BASE)) { + ELOG("Option bytes writing is currently only supported for the STM32G0\n"); + return -1; + } + + /* Unlock flash if necessary (ref manuel page 52) */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + if ((val & (1 << STM32G0_FLASH_CR_LOCK))) { + + /* disable flash write protection. */ + stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0x45670123); + stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0xCDEF89AB); + + // check that the lock is no longer set. + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + if ((val & (1 << STM32G0_FLASH_CR_LOCK))) { + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; + } + } + + /* Unlock option bytes if necessary (ref manuel page 61) */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + if ((val & (1 << STM32G0_FLASH_CR_OPTLOCK))) { + + /* disable option byte write protection. */ + stlink_write_debug32(sl, STM32G0_FLASH_OPTKEYR, 0x08192A3B); + stlink_write_debug32(sl, STM32G0_FLASH_OPTKEYR, 0x4C5D6E7F); + + /* check that the lock is no longer set. */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + if ((val & (1 << STM32G0_FLASH_CR_OPTLOCK))) { + ELOG("Options bytes unlock failed! System reset required to be able to unlock it again!\n"); + return -1; + } + } + + /* Write options bytes */ + uint32_t data; + write_uint32((unsigned char*) &data, *(uint32_t*) (base)); + WLOG("Writing option bytes 0x%04x\n", data); + //stlink_write_debug32(sl, addr, data); + stlink_write_debug32(sl, STM32G0_FLASH_OPTR, data); + + /* Set Options Start bit */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + val |= (1 << STM32G0_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + + /* Wait for 'busy' bit in FLASH_SR to clear. */ + do { + stlink_read_debug32(sl, STM32G0_FLASH_SR, &val); + } while ((val & (1 << 16)) != 0); + + /* apply options bytes immediate */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + val |= (1 << STM32G0_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + + /* Re-lock option bytes */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + val |= (1 << STM32G0_FLASH_CR_OPTLOCK); + stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + /* Re-lock flash. */ + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + val |= (1 << STM32G0_FLASH_CR_LOCK); + stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + + return 0; +} + +/** + * Write the given binary file with option bytes + * @param sl + * @param path readable file path, should be binary image + * @param addr of the memory mapped option bytes + * @return 0 on success, -ve on failure. + */ +int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr) { + /* write the file in flash at addr */ + int err; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; + + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return -1; + } + + err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t) mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); + return err; +} diff --git a/src/tools/flash.c b/src/tools/flash.c index 508c4aa84..768e9834f 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -162,6 +162,14 @@ int main(int ac, char** av) goto on_error; } } + else if (o.addr == STM32_G0_OPTION_BYTES_BASE) { + err = stlink_fwrite_option_bytes(sl, o.filename, o.addr); + if (err == -1) + { + printf("stlink_fwrite_option_bytes() == -1\n"); + goto on_error; + } + } else { err = -1; printf("Unknown memory region\n"); From d85cd81e2e7b0938018224382f2a9485b3cdad3d Mon Sep 17 00:00:00 2001 From: William Ransohoff <> Date: Mon, 25 Mar 2019 18:45:53 -0700 Subject: [PATCH 0652/1435] Add simple read/write support for STM32WB55 chips. --- include/stlink.h | 1 + include/stlink/chipid.h | 3 +- src/chipid.c | 11 +++ src/common.c | 161 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 175 insertions(+), 1 deletion(-) diff --git a/include/stlink.h b/include/stlink.h index fedeb1bf4..d5e8270ac 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -77,6 +77,7 @@ extern "C" { STLINK_FLASH_TYPE_L4, STLINK_FLASH_TYPE_F1_XL, STLINK_FLASH_TYPE_G0, + STLINK_FLASH_TYPE_WB }; struct stlink_reg { diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index dda437ce7..a4f4be4c0 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -71,7 +71,8 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F410 = 0x458, STLINK_CHIPID_STM32_F413 = 0x463, STLINK_CHIPID_STM32_L4RX = 0x470, // taken from the STM32L4R9I-DISCO board - STLINK_CHIPID_STM32_G0X1 = 0x460 + STLINK_CHIPID_STM32_G0X1 = 0x460, + STLINK_CHIPID_STM32_WB55 = 0x495 }; /** diff --git a/src/chipid.c b/src/chipid.c index 4e04f00cc..88d727377 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -518,6 +518,17 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800 // 30K (table 2) }, + { + // STM32WB55 (from RM0434) + .chip_id = STLINK_CHIPID_STM32_WB55, + .description = "WB55 device", + .flash_type = STLINK_FLASH_TYPE_WB, + .flash_size_reg = 0x1FFF75E0, + .flash_pagesize = 0x1000, // 4K + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, // See the memory map + .bootrom_size = 0x7000 + }, { // unknown .chip_id = STLINK_CHIPID_UNKNOWN, diff --git a/src/common.c b/src/common.c index 9bb2c2c4e..867284cc2 100644 --- a/src/common.c +++ b/src/common.c @@ -105,6 +105,28 @@ #define STM32G0_FLASH_CR_OPTLOCK 30 /* Options Lock */ #define STM32G0_FLASH_CR_LOCK 31 /* FLASH_CR Lock*/ +// WB (RM0434) +#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) +#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) +#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) +#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) +#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) +#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) +#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) +#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) +#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) +#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) +#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) +#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) +#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) +#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) +#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) +#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) +#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) +#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) +#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) +#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) + //32L4 register base is at FLASH_REGS_ADDR (0x40022000) #define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) #define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) @@ -1687,6 +1709,49 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); val |= 0x80000000; stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + // TODO: So far, this looks identical to the G0 logic, and the + // core registers also have the same offsets. + uint32_t val; + /* check if the locks are set */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + if ((val & (1<<31))) { + /* disable flash write protection. */ + stlink_write_debug32(sl, STM32WB_FLASH_KEYR, 0x45670123); + stlink_write_debug32(sl, STM32WB_FLASH_KEYR, 0xCDEF89AB); + /* check that the lock is no longer set. */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + if ((val & (1 << 31))) { + WLOG("pecr.pelock not clear (%#x)\n", val); + return -1; + } + } + /* Set PER (erase) bit. */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + val |= (1 << 1); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + /* Set the page to erase. */ + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + // sec 3.10.5 - PNB[7:0] is offset by 3. PER is 0x2. + val = ((flash_page & 0xFF) << 3) | (2); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + /* Set the 'start' bit. */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + val |= (1 << 16); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + /* Wait for 'busy' bit in FLASH_SR to clear. */ + do { + stlink_read_debug32(sl, STM32WB_FLASH_SR, &val); + } while ((val & (1 << 16)) != 0); + /* Clear PER ('erase enable') bit. */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + val &= ~(1 << 1); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + /* Re-lock the flash. */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + val |= (1 << 31); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr < FLASH_BANK2_START_ADDR))) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1755,6 +1820,41 @@ int stlink_erase_flash_mass(stlink_t *sl) { fflush(stdout); } fprintf(stdout, "\n"); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + uint32_t val; + /* check if the locks are set */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + if ((val & (1<<31))) { + /* disable flash write protection. */ + stlink_write_debug32(sl, STM32WB_FLASH_KEYR, 0x45670123); + stlink_write_debug32(sl, STM32WB_FLASH_KEYR, 0xCDEF89AB); + /* check that the lock is no longer set. */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + if ((val & (1 << 31))) { + WLOG("pecr.pelock not clear (%#x)\n", val); + return -1; + } + } + /* Set MER (mass erase) bit. */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + val |= (1 << 2); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + /* Set the 'start' bit. */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + val |= (1 << 16); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + /* Wait for 'busy' bit in FLASH_SR to clear. */ + do { + stlink_read_debug32(sl, STM32WB_FLASH_SR, &val); + } while ((val & (1 << 16)) != 0); + /* Clear MER bit. */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + val &= ~(1 << 2); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + /* Re-lock the flash. */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + val |= (1 << 31); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); } else { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -2084,6 +2184,67 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t val |= 0x80000000; stlink_write_debug32(sl, STM32G0_FLASH_CR, val); } + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + fprintf(stdout, "Writing\r\n"); + fflush(stdout); + uint32_t val; + /* Unlock flash. */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + if ((val & (1 << 31))) { + /* disable flash write protection. */ + stlink_write_debug32(sl, STM32WB_FLASH_KEYR, 0x45670123); + stlink_write_debug32(sl, STM32WB_FLASH_KEYR, 0xCDEF89AB); + /* check that the lock is no longer set. */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + if ((val & (1 << 31))) { + WLOG("pecr.pelock not clear (%#x)\n", val); + return -1; + } + } + /* Set PG 'allow programming' bit. */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + val |= (1 << 0); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + /* Write all words. */ + off = 0; + fprintf(stdout, "Starting %3u page write\r\n", (unsigned int)(len/sl->flash_pgsz)); + fflush(stdout); + for ( ; off < len; off += sizeof(uint32_t)) { + uint32_t data; + if (off > 254) + fprintf(stdout, "\r"); + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off/sl->flash_pgsz), + (unsigned int)(len/sl->flash_pgsz)); + fflush(stdout); + } + write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); + stlink_write_debug32(sl, addr + (uint32_t) off, data); + /* Wait for 'busy' bit in FLASH_SR to clear. */ + do { + stlink_read_debug32(sl, STM32WB_FLASH_SR, &val); + } while ((val & (1 << 16)) != 0); + } + /* (Flash writes happen 2 words at a time.) */ + if ((off / sizeof(uint32_t)) % 2 != 0) { + /* Write a single word of zeros. */ + stlink_write_debug32(sl, addr + (uint32_t) off, 0); + /* Wait for 'busy' bit in FLASH_SR to clear. */ + do { + stlink_read_debug32(sl, STM32WB_FLASH_SR, &val); + } while ((val & (1 << 16)) != 0); + } + /* Reset PG bit. */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + val &= ~(1 << 0); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + /* Re-lock flash. */ + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + val |= (1 << 31); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { /* use fast word write. todo: half page. */ uint32_t val; From d21471650543cc9071ed3821298bcd8c35f5a603 Mon Sep 17 00:00:00 2001 From: William Ransohoff <> Date: Sun, 31 Mar 2019 09:28:45 -0700 Subject: [PATCH 0653/1435] Clean up and unify G0/WB erase/program operations. --- src/common.c | 352 +++++++++++++++++++-------------------------------- 1 file changed, 133 insertions(+), 219 deletions(-) diff --git a/src/common.c b/src/common.c index 867284cc2..b46b6ea87 100644 --- a/src/common.c +++ b/src/common.c @@ -103,7 +103,9 @@ #define STM32G0_FLASH_CR_ERRIE 25 /* Error interrupt enable */ #define STM32G0_FLASH_CR_OBL_LAUNCH 27 /* Forces the option byte loading */ #define STM32G0_FLASH_CR_OPTLOCK 30 /* Options Lock */ -#define STM32G0_FLASH_CR_LOCK 31 /* FLASH_CR Lock*/ +#define STM32G0_FLASH_CR_LOCK 31 /* FLASH_CR Lock */ +// GO FLASH status register +#define STM32G0_FLASH_SR_BSY 16 /* FLASH_SR Busy */ // WB (RM0434) #define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) @@ -127,6 +129,12 @@ #define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) #define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) +// WB Flash control register. +#define STM32WB_FLASH_CR_STRT (16) /* FLASH_CR Start */ +#define STM32WB_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ +// WB Flash status register. +#define STM32WB_FLASH_SR_BSY (16) /* FLASH_SR Busy */ + //32L4 register base is at FLASH_REGS_ADDR (0x40022000) #define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) #define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) @@ -241,6 +249,10 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { reg = FLASH_F4_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) reg = STM32L4_FLASH_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0) + reg = STM32G0_FLASH_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + reg = STM32WB_FLASH_CR; else reg = FLASH_CR; @@ -269,6 +281,10 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { cr_lock_shift = FLASH_F4_CR_LOCK; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) cr_lock_shift = STM32L4_FLASH_CR_LOCK; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0) + cr_lock_shift = STM32G0_FLASH_CR_LOCK; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + cr_lock_shift = STM32WB_FLASH_CR_LOCK; else cr_lock_shift = FLASH_CR_LOCK; @@ -286,6 +302,10 @@ static void unlock_flash(stlink_t *sl) { key_reg = FLASH_F4_KEYR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) key_reg = STM32L4_FLASH_KEYR; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0) + key_reg = STM32G0_FLASH_KEYR; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + key_reg = STM32WB_FLASH_KEYR; else key_reg = FLASH_KEYR; @@ -321,6 +341,12 @@ static void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + cr_reg = STM32G0_FLASH_CR; + cr_lock_shift = STM32G0_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_lock_shift = STM32WB_FLASH_CR_LOCK; } else { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; @@ -348,6 +374,12 @@ static void set_flash_cr_pg(stlink_t *sl) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= 1 << STM32L4_FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + cr_reg = STM32G0_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + x |= (1 << FLASH_CR_PG); } else { cr_reg = FLASH_CR; x = 1 << FLASH_CR_PG; @@ -363,6 +395,10 @@ static void clear_flash_cr_pg(stlink_t *sl) { cr_reg = FLASH_F4_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) cr_reg = STM32L4_FLASH_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0) + cr_reg = STM32G0_FLASH_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + cr_reg = STM32WB_FLASH_CR; else cr_reg = FLASH_CR; @@ -371,8 +407,18 @@ static void clear_flash_cr_pg(stlink_t *sl) { } static void set_flash_cr_per(stlink_t *sl) { - const uint32_t n = 1 << FLASH_CR_PER; - stlink_write_debug32(sl, FLASH_CR, n); + uint32_t cr_reg, val; + + if (sl->flash_type == STLINK_FLASH_TYPE_G0) + cr_reg = STM32G0_FLASH_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + cr_reg = STM32WB_FLASH_CR; + else + cr_reg = FLASH_CR; + + stlink_read_debug32(sl, cr_reg, &val); + val |= (1 << FLASH_CR_PER); + stlink_write_debug32(sl, cr_reg, val); } static void set_flash_cr2_per(stlink_t *sl) { @@ -380,9 +426,18 @@ static void set_flash_cr2_per(stlink_t *sl) { stlink_write_debug32(sl, FLASH_CR2, n); } -static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { +static void clear_flash_cr_per(stlink_t *sl) { + uint32_t cr_reg; + + if (sl->flash_type == STLINK_FLASH_TYPE_G0) + cr_reg = STM32G0_FLASH_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + cr_reg = STM32WB_FLASH_CR; + else + cr_reg = FLASH_CR; + const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER); - stlink_write_debug32(sl, FLASH_CR, n); + stlink_write_debug32(sl, cr_reg, n); } static void set_flash_cr_mer(stlink_t *sl, bool v) { @@ -396,6 +451,14 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); cr_pg = 1 << STM32L4_FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + cr_reg = STM32G0_FLASH_CR; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); } else { cr_reg = FLASH_CR; cr_mer = 1 << FLASH_CR_MER; @@ -458,6 +521,12 @@ static void set_flash_cr_strt(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_strt = 1 << STM32L4_FLASH_CR_STRT; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + cr_reg = STM32G0_FLASH_CR; + cr_strt = 1 << STM32G0_FLASH_CR_STRT; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_strt = 1 << STM32WB_FLASH_CR_STRT; } else { cr_reg = FLASH_CR; cr_strt = 1 << FLASH_CR_STRT; @@ -483,6 +552,10 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { sr_reg = FLASH_F4_SR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) sr_reg = STM32L4_FLASH_SR; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0) + sr_reg = STM32G0_FLASH_SR; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + sr_reg = STM32WB_FLASH_SR; else sr_reg = FLASH_SR; @@ -505,6 +578,10 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { sr_busy_shift = FLASH_F4_SR_BSY; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) sr_busy_shift = STM32L4_FLASH_SR_BSY; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0) + sr_busy_shift = STM32G0_FLASH_SR_BSY; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + sr_busy_shift = STM32WB_FLASH_SR_BSY; else sr_busy_shift = FLASH_SR_BSY; @@ -1668,90 +1745,39 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { - uint32_t val; - /* check if the locks are set */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - if ((val & (1<<31))) { - /* disable flash write protection. */ - stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0x45670123); - stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0xCDEF89AB); - /* check that the lock is no longer set. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - if ((val & (1 << 31))) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return -1; - } - } - /* Set PER (erase) bit. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= 0x00000002; - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); - /* Set the page to erase. */ - uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. - val = ((flash_page & 0x3F) << 3) | (2); - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); - /* Set the 'start' bit. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= (1 << 16); - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); - /* Wait for 'busy' bit in FLASH_SR to clear. */ - do { - stlink_read_debug32(sl, STM32G0_FLASH_SR, &val); - } while ((val & (1 << 16)) != 0); - /* Clear PER ('erase enable') bit. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val &= ~(0x00000002); - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); - /* Re-lock the flash. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= 0x80000000; - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - // TODO: So far, this looks identical to the G0 logic, and the - // core registers also have the same offsets. + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0) { uint32_t val; - /* check if the locks are set */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - if ((val & (1<<31))) { - /* disable flash write protection. */ - stlink_write_debug32(sl, STM32WB_FLASH_KEYR, 0x45670123); - stlink_write_debug32(sl, STM32WB_FLASH_KEYR, 0xCDEF89AB); - /* check that the lock is no longer set. */ + // Wait for any ongoing Flash operation to finish. + wait_flash_busy(sl); + // Unlock Flash if necessary. + unlock_flash_if(sl); + // Set the 'enable Flash erase' bit. + set_flash_cr_per(sl); + + // Set the page to erase. + if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - if ((val & (1 << 31))) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return -1; - } + // sec 3.10.5 - PNB[7:0] is offset by 3. + val |= ((flash_page & 0xFF) << 3); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); + stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. + val |= ((flash_page & 0x3F) << 3); + stlink_write_debug32(sl, STM32G0_FLASH_CR, val); } - /* Set PER (erase) bit. */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - val |= (1 << 1); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - /* Set the page to erase. */ - uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - // sec 3.10.5 - PNB[7:0] is offset by 3. PER is 0x2. - val = ((flash_page & 0xFF) << 3) | (2); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - /* Set the 'start' bit. */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - val |= (1 << 16); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - /* Wait for 'busy' bit in FLASH_SR to clear. */ - do { - stlink_read_debug32(sl, STM32WB_FLASH_SR, &val); - } while ((val & (1 << 16)) != 0); - /* Clear PER ('erase enable') bit. */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - val &= ~(1 << 1); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - /* Re-lock the flash. */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - val |= (1 << 31); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + + // Set the 'start operation' bit. + set_flash_cr_strt(sl); + // Wait for the 'busy' bit to clear. + wait_flash_busy(sl); + // Clear the 'enable page erase' bit. + clear_flash_cr_per(sl); + // Re-lock the flash. + lock_flash(sl); } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr < FLASH_BANK2_START_ADDR))) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1805,8 +1831,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - /* TODO: User MER bit to mass-erase G0 series. */ - if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_G0) { + /* TODO: User MER bit to mass-erase G0, WB series. */ + if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_WB) { /* erase each page */ int i = 0, num_pages = (int) sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -1820,41 +1846,6 @@ int stlink_erase_flash_mass(stlink_t *sl) { fflush(stdout); } fprintf(stdout, "\n"); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - uint32_t val; - /* check if the locks are set */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - if ((val & (1<<31))) { - /* disable flash write protection. */ - stlink_write_debug32(sl, STM32WB_FLASH_KEYR, 0x45670123); - stlink_write_debug32(sl, STM32WB_FLASH_KEYR, 0xCDEF89AB); - /* check that the lock is no longer set. */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - if ((val & (1 << 31))) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return -1; - } - } - /* Set MER (mass erase) bit. */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - val |= (1 << 2); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - /* Set the 'start' bit. */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - val |= (1 << 16); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - /* Wait for 'busy' bit in FLASH_SR to clear. */ - do { - stlink_read_debug32(sl, STM32WB_FLASH_SR, &val); - } while ((val & (1 << 16)) != 0); - /* Clear MER bit. */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - val &= ~(1 << 2); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - /* Re-lock the flash. */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - val |= (1 << 31); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); } else { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -2126,86 +2117,17 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t lock_flash(sl); } //STM32F4END - else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { - uint32_t val; - /* Unlock flash. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - if ((val & (1<<31))) { - /* disable flash write protection. */ - stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0x45670123); - stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0xCDEF89AB); - /* check that the lock is no longer set. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - if ((val & (1 << 31))) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return -1; - } - } - /* Set PG 'allow programming' bit. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= 0x00000001; - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); - /* Write all words. */ - off = 0; - for ( ; off < len; off += sizeof(uint32_t)) { - uint32_t data; - if (off > 254) - fprintf(stdout, "\r"); - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off/sl->flash_pgsz), - (unsigned int)(len/sl->flash_pgsz)); - fflush(stdout); - } - write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); - stlink_write_debug32(sl, addr + (uint32_t) off, data); - /* Wait for 'busy' bit in FLASH_SR to clear. */ - do { - stlink_read_debug32(sl, STM32G0_FLASH_SR, &val); - } while ((val & (1 << 16)) != 0); - } - /* Do we need a dummy write? See sec 3.3.8 of RM0444. */ - /* (Flash writes happen 2 words at a time.) */ - if ((off / sizeof(uint32_t)) % 2 != 0) { - /* Write a single word of zeros. */ - stlink_write_debug32(sl, addr + (uint32_t) off, 0); - /* Wait for 'busy' bit in FLASH_SR to clear. */ - do { - stlink_read_debug32(sl, STM32G0_FLASH_SR, &val); - } while ((val & (1 << 16)) != 0); - } - /* Reset PG bit. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val &= ~(0x00000001); - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); - /* Re-lock flash. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= 0x80000000; - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); - } - else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0) { fprintf(stdout, "Writing\r\n"); fflush(stdout); - uint32_t val; - /* Unlock flash. */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - if ((val & (1 << 31))) { - /* disable flash write protection. */ - stlink_write_debug32(sl, STM32WB_FLASH_KEYR, 0x45670123); - stlink_write_debug32(sl, STM32WB_FLASH_KEYR, 0xCDEF89AB); - /* check that the lock is no longer set. */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - if ((val & (1 << 31))) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return -1; - } - } - /* Set PG 'allow programming' bit. */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - val |= (1 << 0); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - /* Write all words. */ + // Wait for any ongoing operations to finish. + wait_flash_busy(sl); + // Unlock flash if necessary. + unlock_flash_if(sl); + // Set PG 'allow programming' bit. + set_flash_cr_pg(sl); + // Write all words. off = 0; fprintf(stdout, "Starting %3u page write\r\n", (unsigned int)(len/sl->flash_pgsz)); fflush(stdout); @@ -2222,28 +2144,20 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); stlink_write_debug32(sl, addr + (uint32_t) off, data); - /* Wait for 'busy' bit in FLASH_SR to clear. */ - do { - stlink_read_debug32(sl, STM32WB_FLASH_SR, &val); - } while ((val & (1 << 16)) != 0); + // Wait for 'busy' bit in FLASH_SR to clear. + wait_flash_busy(sl); } - /* (Flash writes happen 2 words at a time.) */ + // (Flash writes happen 2 words at a time.) if ((off / sizeof(uint32_t)) % 2 != 0) { - /* Write a single word of zeros. */ + // Write a single word of zeros. stlink_write_debug32(sl, addr + (uint32_t) off, 0); - /* Wait for 'busy' bit in FLASH_SR to clear. */ - do { - stlink_read_debug32(sl, STM32WB_FLASH_SR, &val); - } while ((val & (1 << 16)) != 0); + // Wait for 'busy' bit in FLASH_SR to clear. + wait_flash_busy(sl); } - /* Reset PG bit. */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - val &= ~(1 << 0); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - /* Re-lock flash. */ - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - val |= (1 << 31); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + // Reset PG bit. + clear_flash_cr_pg(sl); + // Re-lock flash. + lock_flash(sl); } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { /* use fast word write. todo: half page. */ From 4ff515ef6881cd0466004ae5673f041c9a060c58 Mon Sep 17 00:00:00 2001 From: WRansohoff Date: Sun, 31 Mar 2019 09:41:57 -0700 Subject: [PATCH 0654/1435] Add simple read/write support for STM32WB55 chips. (#786) * Add simple read/write support for STM32WB55 chips. * Clean up and unify G0/WB erase/program operations. --- include/stlink.h | 1 + include/stlink/chipid.h | 3 +- src/chipid.c | 11 ++ src/common.c | 243 ++++++++++++++++++++++++++-------------- 4 files changed, 173 insertions(+), 85 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index fedeb1bf4..d5e8270ac 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -77,6 +77,7 @@ extern "C" { STLINK_FLASH_TYPE_L4, STLINK_FLASH_TYPE_F1_XL, STLINK_FLASH_TYPE_G0, + STLINK_FLASH_TYPE_WB }; struct stlink_reg { diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index dda437ce7..a4f4be4c0 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -71,7 +71,8 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F410 = 0x458, STLINK_CHIPID_STM32_F413 = 0x463, STLINK_CHIPID_STM32_L4RX = 0x470, // taken from the STM32L4R9I-DISCO board - STLINK_CHIPID_STM32_G0X1 = 0x460 + STLINK_CHIPID_STM32_G0X1 = 0x460, + STLINK_CHIPID_STM32_WB55 = 0x495 }; /** diff --git a/src/chipid.c b/src/chipid.c index 4e04f00cc..88d727377 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -518,6 +518,17 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800 // 30K (table 2) }, + { + // STM32WB55 (from RM0434) + .chip_id = STLINK_CHIPID_STM32_WB55, + .description = "WB55 device", + .flash_type = STLINK_FLASH_TYPE_WB, + .flash_size_reg = 0x1FFF75E0, + .flash_pagesize = 0x1000, // 4K + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, // See the memory map + .bootrom_size = 0x7000 + }, { // unknown .chip_id = STLINK_CHIPID_UNKNOWN, diff --git a/src/common.c b/src/common.c index 9bb2c2c4e..b46b6ea87 100644 --- a/src/common.c +++ b/src/common.c @@ -103,7 +103,37 @@ #define STM32G0_FLASH_CR_ERRIE 25 /* Error interrupt enable */ #define STM32G0_FLASH_CR_OBL_LAUNCH 27 /* Forces the option byte loading */ #define STM32G0_FLASH_CR_OPTLOCK 30 /* Options Lock */ -#define STM32G0_FLASH_CR_LOCK 31 /* FLASH_CR Lock*/ +#define STM32G0_FLASH_CR_LOCK 31 /* FLASH_CR Lock */ +// GO FLASH status register +#define STM32G0_FLASH_SR_BSY 16 /* FLASH_SR Busy */ + +// WB (RM0434) +#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) +#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) +#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) +#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) +#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) +#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) +#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) +#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) +#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) +#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) +#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) +#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) +#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) +#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) +#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) +#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) +#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) +#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) +#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) +#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) + +// WB Flash control register. +#define STM32WB_FLASH_CR_STRT (16) /* FLASH_CR Start */ +#define STM32WB_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ +// WB Flash status register. +#define STM32WB_FLASH_SR_BSY (16) /* FLASH_SR Busy */ //32L4 register base is at FLASH_REGS_ADDR (0x40022000) #define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) @@ -219,6 +249,10 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { reg = FLASH_F4_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) reg = STM32L4_FLASH_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0) + reg = STM32G0_FLASH_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + reg = STM32WB_FLASH_CR; else reg = FLASH_CR; @@ -247,6 +281,10 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { cr_lock_shift = FLASH_F4_CR_LOCK; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) cr_lock_shift = STM32L4_FLASH_CR_LOCK; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0) + cr_lock_shift = STM32G0_FLASH_CR_LOCK; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + cr_lock_shift = STM32WB_FLASH_CR_LOCK; else cr_lock_shift = FLASH_CR_LOCK; @@ -264,6 +302,10 @@ static void unlock_flash(stlink_t *sl) { key_reg = FLASH_F4_KEYR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) key_reg = STM32L4_FLASH_KEYR; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0) + key_reg = STM32G0_FLASH_KEYR; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + key_reg = STM32WB_FLASH_KEYR; else key_reg = FLASH_KEYR; @@ -299,6 +341,12 @@ static void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + cr_reg = STM32G0_FLASH_CR; + cr_lock_shift = STM32G0_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_lock_shift = STM32WB_FLASH_CR_LOCK; } else { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; @@ -326,6 +374,12 @@ static void set_flash_cr_pg(stlink_t *sl) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= 1 << STM32L4_FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + cr_reg = STM32G0_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + x |= (1 << FLASH_CR_PG); } else { cr_reg = FLASH_CR; x = 1 << FLASH_CR_PG; @@ -341,6 +395,10 @@ static void clear_flash_cr_pg(stlink_t *sl) { cr_reg = FLASH_F4_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) cr_reg = STM32L4_FLASH_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0) + cr_reg = STM32G0_FLASH_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + cr_reg = STM32WB_FLASH_CR; else cr_reg = FLASH_CR; @@ -349,8 +407,18 @@ static void clear_flash_cr_pg(stlink_t *sl) { } static void set_flash_cr_per(stlink_t *sl) { - const uint32_t n = 1 << FLASH_CR_PER; - stlink_write_debug32(sl, FLASH_CR, n); + uint32_t cr_reg, val; + + if (sl->flash_type == STLINK_FLASH_TYPE_G0) + cr_reg = STM32G0_FLASH_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + cr_reg = STM32WB_FLASH_CR; + else + cr_reg = FLASH_CR; + + stlink_read_debug32(sl, cr_reg, &val); + val |= (1 << FLASH_CR_PER); + stlink_write_debug32(sl, cr_reg, val); } static void set_flash_cr2_per(stlink_t *sl) { @@ -358,9 +426,18 @@ static void set_flash_cr2_per(stlink_t *sl) { stlink_write_debug32(sl, FLASH_CR2, n); } -static void __attribute__((unused)) clear_flash_cr_per(stlink_t *sl) { +static void clear_flash_cr_per(stlink_t *sl) { + uint32_t cr_reg; + + if (sl->flash_type == STLINK_FLASH_TYPE_G0) + cr_reg = STM32G0_FLASH_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + cr_reg = STM32WB_FLASH_CR; + else + cr_reg = FLASH_CR; + const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER); - stlink_write_debug32(sl, FLASH_CR, n); + stlink_write_debug32(sl, cr_reg, n); } static void set_flash_cr_mer(stlink_t *sl, bool v) { @@ -374,6 +451,14 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); cr_pg = 1 << STM32L4_FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + cr_reg = STM32G0_FLASH_CR; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); } else { cr_reg = FLASH_CR; cr_mer = 1 << FLASH_CR_MER; @@ -436,6 +521,12 @@ static void set_flash_cr_strt(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_strt = 1 << STM32L4_FLASH_CR_STRT; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + cr_reg = STM32G0_FLASH_CR; + cr_strt = 1 << STM32G0_FLASH_CR_STRT; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_strt = 1 << STM32WB_FLASH_CR_STRT; } else { cr_reg = FLASH_CR; cr_strt = 1 << FLASH_CR_STRT; @@ -461,6 +552,10 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { sr_reg = FLASH_F4_SR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) sr_reg = STM32L4_FLASH_SR; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0) + sr_reg = STM32G0_FLASH_SR; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + sr_reg = STM32WB_FLASH_SR; else sr_reg = FLASH_SR; @@ -483,6 +578,10 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { sr_busy_shift = FLASH_F4_SR_BSY; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) sr_busy_shift = STM32L4_FLASH_SR_BSY; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0) + sr_busy_shift = STM32G0_FLASH_SR_BSY; + else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + sr_busy_shift = STM32WB_FLASH_SR_BSY; else sr_busy_shift = FLASH_SR_BSY; @@ -1646,47 +1745,39 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0) { uint32_t val; - /* check if the locks are set */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - if ((val & (1<<31))) { - /* disable flash write protection. */ - stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0x45670123); - stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0xCDEF89AB); - /* check that the lock is no longer set. */ + // Wait for any ongoing Flash operation to finish. + wait_flash_busy(sl); + // Unlock Flash if necessary. + unlock_flash_if(sl); + // Set the 'enable Flash erase' bit. + set_flash_cr_per(sl); + + // Set the page to erase. + if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + // sec 3.10.5 - PNB[7:0] is offset by 3. + val |= ((flash_page & 0xFF) << 3); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - if ((val & (1 << 31))) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return -1; - } + // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. + val |= ((flash_page & 0x3F) << 3); + stlink_write_debug32(sl, STM32G0_FLASH_CR, val); } - /* Set PER (erase) bit. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= 0x00000002; - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); - /* Set the page to erase. */ - uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. - val = ((flash_page & 0x3F) << 3) | (2); - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); - /* Set the 'start' bit. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= (1 << 16); - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); - /* Wait for 'busy' bit in FLASH_SR to clear. */ - do { - stlink_read_debug32(sl, STM32G0_FLASH_SR, &val); - } while ((val & (1 << 16)) != 0); - /* Clear PER ('erase enable') bit. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val &= ~(0x00000002); - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); - /* Re-lock the flash. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= 0x80000000; - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + + // Set the 'start operation' bit. + set_flash_cr_strt(sl); + // Wait for the 'busy' bit to clear. + wait_flash_busy(sl); + // Clear the 'enable page erase' bit. + clear_flash_cr_per(sl); + // Re-lock the flash. + lock_flash(sl); } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr < FLASH_BANK2_START_ADDR))) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1740,8 +1831,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - /* TODO: User MER bit to mass-erase G0 series. */ - if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_G0) { + /* TODO: User MER bit to mass-erase G0, WB series. */ + if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_WB) { /* erase each page */ int i = 0, num_pages = (int) sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -2026,27 +2117,20 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t lock_flash(sl); } //STM32F4END - else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { - uint32_t val; - /* Unlock flash. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - if ((val & (1<<31))) { - /* disable flash write protection. */ - stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0x45670123); - stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0xCDEF89AB); - /* check that the lock is no longer set. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - if ((val & (1 << 31))) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return -1; - } - } - /* Set PG 'allow programming' bit. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= 0x00000001; - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); - /* Write all words. */ + else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0) { + fprintf(stdout, "Writing\r\n"); + fflush(stdout); + // Wait for any ongoing operations to finish. + wait_flash_busy(sl); + // Unlock flash if necessary. + unlock_flash_if(sl); + // Set PG 'allow programming' bit. + set_flash_cr_pg(sl); + // Write all words. off = 0; + fprintf(stdout, "Starting %3u page write\r\n", (unsigned int)(len/sl->flash_pgsz)); + fflush(stdout); for ( ; off < len; off += sizeof(uint32_t)) { uint32_t data; if (off > 254) @@ -2060,29 +2144,20 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); stlink_write_debug32(sl, addr + (uint32_t) off, data); - /* Wait for 'busy' bit in FLASH_SR to clear. */ - do { - stlink_read_debug32(sl, STM32G0_FLASH_SR, &val); - } while ((val & (1 << 16)) != 0); + // Wait for 'busy' bit in FLASH_SR to clear. + wait_flash_busy(sl); } - /* Do we need a dummy write? See sec 3.3.8 of RM0444. */ - /* (Flash writes happen 2 words at a time.) */ + // (Flash writes happen 2 words at a time.) if ((off / sizeof(uint32_t)) % 2 != 0) { - /* Write a single word of zeros. */ + // Write a single word of zeros. stlink_write_debug32(sl, addr + (uint32_t) off, 0); - /* Wait for 'busy' bit in FLASH_SR to clear. */ - do { - stlink_read_debug32(sl, STM32G0_FLASH_SR, &val); - } while ((val & (1 << 16)) != 0); + // Wait for 'busy' bit in FLASH_SR to clear. + wait_flash_busy(sl); } - /* Reset PG bit. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val &= ~(0x00000001); - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); - /* Re-lock flash. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= 0x80000000; - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + // Reset PG bit. + clear_flash_cr_pg(sl); + // Re-lock flash. + lock_flash(sl); } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { /* use fast word write. todo: half page. */ From 224f6eee2a9044b87bffdbc746a3ecba9a07ff34 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mikl=C3=B3s=20M=C3=A1rton?= Date: Wed, 3 Apr 2019 13:00:18 +0200 Subject: [PATCH 0655/1435] Add STLink V3SET VID:PIDs to the udev rules (#789) --- etc/udev/rules.d/49-stlinkv3.rules | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 etc/udev/rules.d/49-stlinkv3.rules diff --git a/etc/udev/rules.d/49-stlinkv3.rules b/etc/udev/rules.d/49-stlinkv3.rules new file mode 100644 index 000000000..5161947a9 --- /dev/null +++ b/etc/udev/rules.d/49-stlinkv3.rules @@ -0,0 +1,29 @@ +# STLink V3SET in Dual CDC mode +SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3752", \ + MODE:="0666", \ + SYMLINK+="stlinkv3_%n" + +# STLink V3SET in Dual CDC mode +SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3753", \ + MODE:="0666", \ + SYMLINK+="stlinkv3_%n" + +# STLink V3SET +SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374d", \ + MODE:="0666", \ + SYMLINK+="stlinkv3_%n" + +# STLink V3SET +SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374e", \ + MODE:="0666", \ + SYMLINK+="stlinkv3_%n" + +# STLink V3SET in normal mode +SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374f", \ + MODE:="0666", \ + SYMLINK+="stlinkv3_%n" + +# If you share your linux system with other users, or just don't like the +# idea of write permission for everybody, you can replace MODE:="0666" with +# OWNER:="yourusername" to create the device owned by you, or with +# GROUP:="somegroupname" and mange access using standard unix groups. From feb86618fa3e45c3e15851863fce20ee14cd76d9 Mon Sep 17 00:00:00 2001 From: Kirill Zhumarin Date: Sat, 13 Apr 2019 13:07:58 +0300 Subject: [PATCH 0656/1435] Support for "STM32+Audio" v2-1 firmware (#790) * Add pid for "STM32+Audio" v2-1 firmware * Add support for "STM32+Audio" v2-1 firmware,. * Add udev rules for "STM32+Audio" firmware --- etc/udev/rules.d/49-stlinkv2-1.rules | 4 ++++ include/stlink/usb.h | 9 +++++---- src/usb.c | 8 +++++--- 3 files changed, 14 insertions(+), 7 deletions(-) diff --git a/etc/udev/rules.d/49-stlinkv2-1.rules b/etc/udev/rules.d/49-stlinkv2-1.rules index a5a79b91c..15a797a05 100644 --- a/etc/udev/rules.d/49-stlinkv2-1.rules +++ b/etc/udev/rules.d/49-stlinkv2-1.rules @@ -2,6 +2,10 @@ # ie, STM32F0, STM32F4. # STM32VL has st/linkv1, which is quite different +SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374a", \ + MODE:="0666", \ + SYMLINK+="stlinkv2-1_%n" + SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ MODE:="0666", \ SYMLINK+="stlinkv2-1_%n" diff --git a/include/stlink/usb.h b/include/stlink/usb.h index 46e7419cf..9e27db156 100644 --- a/include/stlink/usb.h +++ b/include/stlink/usb.h @@ -18,10 +18,11 @@ extern "C" { #endif -#define STLINK_USB_VID_ST 0x0483 -#define STLINK_USB_PID_STLINK 0x3744 -#define STLINK_USB_PID_STLINK_32L 0x3748 -#define STLINK_USB_PID_STLINK_NUCLEO 0x374b +#define STLINK_USB_VID_ST 0x0483 +#define STLINK_USB_PID_STLINK 0x3744 +#define STLINK_USB_PID_STLINK_32L 0x3748 +#define STLINK_USB_PID_STLINK_32L_AUDIO 0x374a +#define STLINK_USB_PID_STLINK_NUCLEO 0x374b #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 diff --git a/src/usb.c b/src/usb.c index 66f065ab8..c4d39ac5f 100644 --- a/src/usb.c +++ b/src/usb.c @@ -827,7 +827,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 } } - if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) || (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO)) { + if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) || (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO) || (desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO)) { struct libusb_device_handle *handle; ret = libusb_open(list[cnt], &handle); @@ -901,7 +901,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16 // TODO - could use the scanning techniq from stm8 code here... slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; - if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO) { + if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO || desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO) { slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; } else { slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; @@ -973,6 +973,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { } if (desc.idProduct != STLINK_USB_PID_STLINK_32L && + desc.idProduct != STLINK_USB_PID_STLINK_32L_AUDIO && desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO) continue; @@ -996,7 +997,8 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { break; } - if (desc.idProduct != STLINK_USB_PID_STLINK_32L && + if (desc.idProduct != STLINK_USB_PID_STLINK_32L && + desc.idProduct != STLINK_USB_PID_STLINK_32L_AUDIO && desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO) continue; From 2117226105187d75ce05a3a8ebed9e2a42793b17 Mon Sep 17 00:00:00 2001 From: William Ransohoff <> Date: Thu, 25 Apr 2019 22:14:23 -0700 Subject: [PATCH 0657/1435] Fix apparent issue with STM32G0 flashing. --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index b46b6ea87..63de8415c 100644 --- a/src/common.c +++ b/src/common.c @@ -1766,7 +1766,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. - val |= ((flash_page & 0x3F) << 3); + val = ((flash_page & 0x3F) << 3) | ( 1 << FLASH_CR_PER ); stlink_write_debug32(sl, STM32G0_FLASH_CR, val); } From cf677803d0fdfcb001a55ca04f8ee36a5836d3f1 Mon Sep 17 00:00:00 2001 From: WRansohoff Date: Thu, 25 Apr 2019 23:00:30 -0700 Subject: [PATCH 0658/1435] Fix apparent STM32G0 flashing issue. (#797) * Add simple read/write support for STM32WB55 chips. * Clean up and unify G0/WB erase/program operations. * Fix apparent issue with STM32G0 flashing. --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index b46b6ea87..63de8415c 100644 --- a/src/common.c +++ b/src/common.c @@ -1766,7 +1766,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. - val |= ((flash_page & 0x3F) << 3); + val = ((flash_page & 0x3F) << 3) | ( 1 << FLASH_CR_PER ); stlink_write_debug32(sl, STM32G0_FLASH_CR, val); } From 189f253ce3f9a6a39d0ebf7b2b5c23defddd757c Mon Sep 17 00:00:00 2001 From: Eli Krumholz Date: Mon, 6 May 2019 12:36:26 -0500 Subject: [PATCH 0659/1435] initial support for STM32L41X (#799) --- src/chipid.c | 14 ++++++++++++++ src/flash_loader.c | 1 + 2 files changed, 15 insertions(+) diff --git a/src/chipid.c b/src/chipid.c index 88d727377..d627849a3 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -453,6 +453,20 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 .bootrom_size = 0x7000 // 28k (per bank), same source as base (pg 99) }, + { + // STLINK_CHIPID_STM32_L41X + // From RM0394 Rev 4 and DS12469 Rev 5 + .chip_id = STLINK_CHIPID_STM32_L41X, + .description = "L41x device", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, sec 47.2, page 1586) + .flash_pagesize = 0x800, // 2K (DS12469, sec 3.4, page 17) + // SRAM1 is 32k at 0x20000000 + // SRAM2 is 8k at 0x10000000 and 0x20008000 (DS12469, sec 3.5, page 18) + .sram_size = 0xa000, // 40K (DS12469, sec 3.5, page 18) + .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) + .bootrom_size = 0x7000 // 28k, same source as base + }, { // STLINK_CHIPID_STM32_L43X // From RM0392. diff --git a/src/flash_loader.c b/src/flash_loader.c index 7684680a7..f2e636751 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -306,6 +306,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || + (sl->chip_id == STLINK_CHIPID_STM32_L41X) || (sl->chip_id == STLINK_CHIPID_STM32_L43X) || (sl->chip_id == STLINK_CHIPID_STM32_L46X) || (sl->chip_id == STLINK_CHIPID_STM32_L4RX) || From a3cb1a1569f2e0eea5e558924db8155c759cbc86 Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Sat, 11 May 2019 20:41:57 +0300 Subject: [PATCH 0660/1435] build wor windows under Debian/Ubuntu (#802) --- CMakeLists.txt | 1 + cmake/linux-mingw32.cmake | 25 +++++++++++++++++++++++++ cmake/linux-mingw64.cmake | 25 +++++++++++++++++++++++++ cmake/modules/Find7Zip.cmake | 2 +- cmake/modules/FindLibUSB.cmake | 29 ++++++++++++++++++++++++----- doc/compiling.md | 21 +++++++++++++++++++++ src/mingw/mingw.h | 2 +- 7 files changed, 98 insertions(+), 7 deletions(-) create mode 100644 cmake/linux-mingw32.cmake create mode 100644 cmake/linux-mingw64.cmake diff --git a/CMakeLists.txt b/CMakeLists.txt index a36803ee0..b0eef1189 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -86,6 +86,7 @@ set(STLINK_SOURCE if (WIN32 OR MSYS OR MINGW) set (STLINK_SOURCE "${STLINK_SOURCE};src/mmap.c;src/mingw/mingw.c") + set (STLINK_HEADERS "${STLINK_HEADERS};src/mingw/mingw.h") endif () include_directories(${LIBUSB_INCLUDE_DIR}) diff --git a/cmake/linux-mingw32.cmake b/cmake/linux-mingw32.cmake new file mode 100644 index 000000000..2044a7e22 --- /dev/null +++ b/cmake/linux-mingw32.cmake @@ -0,0 +1,25 @@ +# Sample toolchain file for building for Windows from an Debian/Ubuntu Linux system. +# +# Typical usage: +# *) install cross compiler: `sudo apt-get install mingw-w64` +# *) cd build +# *) cmake -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake .. + +set(CMAKE_SYSTEM_NAME Windows) +set(TOOLCHAIN_PREFIX i686-w64-mingw32) + +# cross compilers to use for C and C++ +set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}-gcc) +set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}-g++) +set(CMAKE_RC_COMPILER ${TOOLCHAIN_PREFIX}-windres) + +# target environment on the build host system +# set 1st to dir with the cross compiler's C/C++ headers/libs +set(CMAKE_FIND_ROOT_PATH /usr/${TOOLCHAIN_PREFIX}) + +# modify default behavior of FIND_XXX() commands to +# search for headers/libs in the target environment and +# search for programs in the build host environment +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) \ No newline at end of file diff --git a/cmake/linux-mingw64.cmake b/cmake/linux-mingw64.cmake new file mode 100644 index 000000000..db4bd70d0 --- /dev/null +++ b/cmake/linux-mingw64.cmake @@ -0,0 +1,25 @@ +# Sample toolchain file for building for Windows from an Ubuntu Linux system. +# +# Typical usage: +# *) install cross compiler: `sudo apt-get install mingw-w64` +# *) cd build +# *) cmake -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw64.cmake .. + +set(CMAKE_SYSTEM_NAME Windows) +set(TOOLCHAIN_PREFIX x86_64-w64-mingw32) + +# cross compilers to use for C and C++ +set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}-gcc) +set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}-g++) +set(CMAKE_RC_COMPILER ${TOOLCHAIN_PREFIX}-windres) + +# target environment on the build host system +# set 1st to dir with the cross compiler's C/C++ headers/libs +set(CMAKE_FIND_ROOT_PATH /usr/${TOOLCHAIN_PREFIX}) + +# modify default behavior of FIND_XXX() commands to +# search for headers/libs in the target environment and +# search for programs in the build host environment +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) \ No newline at end of file diff --git a/cmake/modules/Find7Zip.cmake b/cmake/modules/Find7Zip.cmake index 3448a2856..e4d33dfce 100644 --- a/cmake/modules/Find7Zip.cmake +++ b/cmake/modules/Find7Zip.cmake @@ -1,4 +1,4 @@ -find_program(ZIP_EXECUTABLE NAMES 7z.exe +find_program(ZIP_EXECUTABLE NAMES 7z.exe p7zip HINTS "C:\\Program Files\\7-Zip\\" "C:\\Program Files (x86)\\7-Zip\\" diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index e9a5944f6..5233e489d 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -82,28 +82,47 @@ if(NOT LIBUSB_FOUND) ) endif() file(MAKE_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) - execute_process(COMMAND ${ZIP_EXECUTABLE} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o${LIBUSB_WIN_OUTPUT_FOLDER}) + + if(${ZIP_EXECUTABLE} MATCHES "p7zip") + execute_process(COMMAND ${ZIP_EXECUTABLE} -d --keep -f ${LIBUSB_WIN_ARCHIVE_PATH} WORKING_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) + else() + execute_process(COMMAND ${ZIP_EXECUTABLE} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o${LIBUSB_WIN_OUTPUT_FOLDER}) + endif() FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/include PATH_SUFFIXES libusb-1.0 + NO_DEFAULT_PATH + NO_CMAKE_FIND_ROOT_PATH ) if (MSYS OR MINGW) if (CMAKE_SIZEOF_VOID_P EQUAL 8) find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/static) + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/static + NO_DEFAULT_PATH + NO_CMAKE_FIND_ROOT_PATH + ) else () find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW32/static) + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW32/static + NO_DEFAULT_PATH + NO_CMAKE_FIND_ROOT_PATH + ) endif () elseif(MSVC) if (CMAKE_SIZEOF_VOID_P EQUAL 8) find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS64/dll) + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS64/dll + NO_DEFAULT_PATH + NO_CMAKE_FIND_ROOT_PATH + ) else () find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS32/dll) + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS32/dll + NO_DEFAULT_PATH + NO_CMAKE_FIND_ROOT_PATH + ) endif () endif () FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) diff --git a/doc/compiling.md b/doc/compiling.md index 74a8a34f5..555dce487 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -179,3 +179,24 @@ NOTES: This solution will link to the dll version of libusb-1.0. To debug or ru be either on the path, or in the same folder as the executable. It can be copied from here: `build\3thparty\libusb-1.0.21\MS32\dll\libusb-1.0.dll`. +## Linux (MinGW64) + +### Prequistes + +* 7Zip +* CMake 2.8 or higher +* MinGW64 GCC toolchain (5.3.0) + +### Installation (Debian / Ubuntu) + +sudo apt install p7zip mingw-w64 + +### Building + +These instructions are for a 32bit version. + +```sh +cd +cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake -S . -B ./build/linux-mingw32 +cmake --build ./build/linux-mingw32 --target all +``` diff --git a/src/mingw/mingw.h b/src/mingw/mingw.h index 2efd1ab34..4fe07e611 100644 --- a/src/mingw/mingw.h +++ b/src/mingw/mingw.h @@ -8,7 +8,7 @@ #endif #include -#include +#include #if defined(_MSC_VER) #pragma comment(lib, "ws2_32.lib") #endif From d040db5585d33dc36bd8ae093c024583ef1b4f74 Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Mon, 13 May 2019 17:58:30 +0300 Subject: [PATCH 0661/1435] fixed few potential memory/resource leaks (#803) also few cppcheck warnings --- src/common.c | 14 +++--- src/gdbserver/gdb-remote.c | 15 +++++- src/gdbserver/gdb-server.c | 93 ++++++++++++++++++------------------- src/gdbserver/semihosting.c | 2 +- src/mingw/mingw.c | 3 +- src/mingw/mingw.h | 2 +- src/mmap.c | 6 ++- src/sg.c | 2 +- src/usb.c | 2 +- 9 files changed, 78 insertions(+), 61 deletions(-) diff --git a/src/common.c b/src/common.c index 63de8415c..19cfd4f87 100644 --- a/src/common.c +++ b/src/common.c @@ -288,7 +288,7 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { else cr_lock_shift = FLASH_CR_LOCK; - return cr & (1 << cr_lock_shift); + return cr & (1u << cr_lock_shift); } static void unlock_flash(stlink_t *sl) { @@ -352,11 +352,11 @@ static void lock_flash(stlink_t *sl) { cr_lock_shift = FLASH_CR_LOCK; } - n = read_flash_cr(sl) | (1 << cr_lock_shift); + n = read_flash_cr(sl) | (1u << cr_lock_shift); stlink_write_debug32(sl, cr_reg, n); if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - n = read_flash_cr2(sl) | (1 << cr_lock_shift); + n = read_flash_cr2(sl) | (1u << cr_lock_shift); stlink_write_debug32(sl, FLASH_CR2, n); } } @@ -2524,7 +2524,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui /* Unlock flash if necessary (ref manuel page 52) */ stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - if ((val & (1 << STM32G0_FLASH_CR_LOCK))) { + if ((val & (1u << STM32G0_FLASH_CR_LOCK))) { /* disable flash write protection. */ stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0x45670123); @@ -2532,7 +2532,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui // check that the lock is no longer set. stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - if ((val & (1 << STM32G0_FLASH_CR_LOCK))) { + if ((val & (1u << STM32G0_FLASH_CR_LOCK))) { ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); return -1; } @@ -2578,11 +2578,11 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui /* Re-lock option bytes */ stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= (1 << STM32G0_FLASH_CR_OPTLOCK); + val |= (1u << STM32G0_FLASH_CR_OPTLOCK); stlink_write_debug32(sl, STM32G0_FLASH_CR, val); /* Re-lock flash. */ stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= (1 << STM32G0_FLASH_CR_LOCK); + val |= (1u << STM32G0_FLASH_CR_LOCK); stlink_write_debug32(sl, STM32G0_FLASH_CR, val); return 0; diff --git a/src/gdbserver/gdb-remote.c b/src/gdbserver/gdb-remote.c index 83c5e093a..e4aad312d 100644 --- a/src/gdbserver/gdb-remote.c +++ b/src/gdbserver/gdb-remote.c @@ -64,8 +64,12 @@ int gdb_recv_packet(int fd, char** buffer) { char* packet_buffer = malloc(packet_size); unsigned state; + if(packet_buffer == NULL) + return -2; + start: state = 0; + packet_idx = 0; /* * 0: waiting $ * 1: data, waiting # @@ -77,6 +81,7 @@ int gdb_recv_packet(int fd, char** buffer) { char c; while(state != 4) { if(read(fd, &c, 1) != 1) { + free(packet_buffer); return -2; } @@ -98,7 +103,13 @@ int gdb_recv_packet(int fd, char** buffer) { if(packet_idx == packet_size) { packet_size += ALLOC_STEP; - packet_buffer = realloc(packet_buffer, packet_size); + void* p = realloc(packet_buffer, packet_size); + if(p != NULL) + packet_buffer = p; + else { + free(packet_buffer); + return -2; + } } } break; @@ -119,6 +130,7 @@ int gdb_recv_packet(int fd, char** buffer) { if(recv_cksum_int != cksum) { char nack = '-'; if(write(fd, &nack, 1) != 1) { + free(packet_buffer); return -2; } @@ -126,6 +138,7 @@ int gdb_recv_packet(int fd, char** buffer) { } else { char ack = '+'; if(write(fd, &ack, 1) != 1) { + free(packet_buffer); return -2; } } diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 8566b792e..bdfeb703d 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -14,7 +14,7 @@ #include #define __attribute__(x) #endif -#if defined(__MINGW32__) || defined(_MSC_VER) +#if defined(_WIN32) #include #else #include @@ -44,6 +44,15 @@ static bool semihosting = false; static bool serial_specified = false; static char serialnumber[28] = {0}; +#if defined(_WIN32) +#define close_socket win32_close_socket +#define IS_SOCK_VALID(__sock) ((__sock) != INVALID_SOCKET) +#else +#define close_socket close +#define SOCKET int +#define IS_SOCK_VALID(__sock) ((__sock) > 0) +#endif + static const char hex[] = "0123456789abcdef"; static const char* current_memory_map = NULL; @@ -106,7 +115,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { {"no-reset", optional_argument, NULL, 'n'}, {"version", no_argument, NULL, 'V'}, {"semihosting", no_argument, NULL, SEMIHOSTING_OPTION}, - {"serial", required_argument, NULL, SERIAL_OPTION}, + {"serial", required_argument, NULL, SERIAL_OPTION}, {0, 0, 0, 0}, }; const char * help_str = "%s - usage:\n\n" @@ -863,7 +872,6 @@ static int flash_go(stlink_t *sl) { int ret = stlink_write_flash(sl, page, fb->data + (page - fb->addr), len, 0); if (ret < 0) goto error; - length -= len; } } @@ -989,29 +997,27 @@ static void init_cache (stlink_t *sl) { } static void cache_flush(stlink_t *sl, unsigned ccr) { - int level; - - if (ccr & CCR_DC) - for (level = cache_desc.louu - 1; level >= 0; level--) - { - struct cache_level_desc *desc = &cache_desc.dcache[level]; - unsigned addr; - unsigned max_addr = 1 << desc->width; - unsigned way_sh = 32 - desc->log2_nways; - - /* D-cache clean by set-ways. */ - for (addr = (level << 1); addr < max_addr; addr += cache_desc.dminline) - { - unsigned int way; - - for (way = 0; way < desc->nways; way++) - stlink_write_debug32(sl, DCCSW, addr | (way << way_sh)); - } - } - - /* Invalidate all I-cache to oPU. */ - if (ccr & CCR_IC) - stlink_write_debug32(sl, ICIALLU, 0); + int level; + + if (ccr & CCR_DC) + for (level = cache_desc.louu - 1; level >= 0; level--) { + struct cache_level_desc *desc = &cache_desc.dcache[level]; + unsigned addr; + unsigned max_addr = 1 << desc->width; + unsigned way_sh = 32 - desc->log2_nways; + + /* D-cache clean by set-ways. */ + for (addr = (level << 1); addr < max_addr; addr += cache_desc.dminline) { + unsigned int way; + + for (way = 0; way < desc->nways; way++) + stlink_write_debug32(sl, DCCSW, addr | (way << way_sh)); + } + } + + /* Invalidate all I-cache to oPU. */ + if (ccr & CCR_IC) + stlink_write_debug32(sl, ICIALLU, 0); } static int cache_modified; @@ -1055,8 +1061,8 @@ static size_t unhexify(const char *in, char *out, size_t out_count) } int serve(stlink_t *sl, st_state_t *st) { - int sock = socket(AF_INET, SOCK_STREAM, 0); - if(sock < 0) { + SOCKET sock = socket(AF_INET, SOCK_STREAM, 0); + if(!IS_SOCK_VALID(sock)) { perror("socket"); return 1; } @@ -1072,28 +1078,27 @@ int serve(stlink_t *sl, st_state_t *st) { if(bind(sock, (struct sockaddr *) &serv_addr, sizeof(serv_addr)) < 0) { perror("bind"); + close_socket(sock); return 1; } if(listen(sock, 5) < 0) { perror("listen"); + close_socket(sock); return 1; } ILOG("Listening at *:%d...\n", st->listen_port); - int client = accept(sock, NULL, NULL); + SOCKET client = accept(sock, NULL, NULL); //signal (SIGINT, SIG_DFL); - if(client < 0) { + if(!IS_SOCK_VALID(client)) { perror("accept"); + close_socket(sock); return 1; } -#if defined(__MINGW32__) || defined(_MSC_VER) - win32_close_socket(sock); -#else - close(sock); -#endif + close_socket(sock); stlink_force_debug(sl); if (st->reset) { @@ -1116,9 +1121,7 @@ int serve(stlink_t *sl, st_state_t *st) { int status = gdb_recv_packet(client, &packet); if(status < 0) { ELOG("cannot recv: %d\n", status); -#if defined(__MINGW32__) || defined(_MSC_VER) - win32_close_socket(client); -#endif + close_socket(client); return 1; } @@ -1343,6 +1346,8 @@ int serve(stlink_t *sl, st_state_t *st) { } else { reply = strdup("OK"); } + + free(decoded); } else if(!strcmp(cmdName, "FlashDone")) { if(flash_go(sl) < 0) { reply = strdup("E00"); @@ -1369,9 +1374,7 @@ int serve(stlink_t *sl, st_state_t *st) { status = gdb_check_for_interrupt(client); if(status < 0) { ELOG("cannot check for int: %d\n", status); -#if defined(__MINGW32__) || defined(_MSC_VER) - win32_close_socket(client); -#endif + close_socket(client); return 1; } @@ -1771,9 +1774,7 @@ int serve(stlink_t *sl, st_state_t *st) { ELOG("cannot send: %d\n", result); free(reply); free(packet); -#if defined(__MINGW32__) || defined(_MSC_VER) - win32_close_socket(client); -#endif + close_socket(client); return 1; } @@ -1783,9 +1784,7 @@ int serve(stlink_t *sl, st_state_t *st) { free(packet); } -#if defined(__MINGW32__) || defined(_MSC_VER) - win32_close_socket(client); -#endif + close_socket(client); return 0; } diff --git a/src/gdbserver/semihosting.c b/src/gdbserver/semihosting.c index b7792007f..9e92cf3bd 100644 --- a/src/gdbserver/semihosting.c +++ b/src/gdbserver/semihosting.c @@ -320,7 +320,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { int fd; uint32_t buffer_len; void *buffer; - ssize_t read_result; + ssize_t read_result; if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { DLOG("Semihosting SYS_READ error: " diff --git a/src/mingw/mingw.c b/src/mingw/mingw.c index bfdd3dcff..4cb917ac4 100644 --- a/src/mingw/mingw.c +++ b/src/mingw/mingw.c @@ -15,7 +15,8 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { struct timeval timeout, *toptr; fd_set ifds, ofds, efds, *ip, *op; - unsigned int i, rc; + unsigned int i; + int rc; /* Set up the file-descriptor sets in ifds, ofds and efds. */ #ifdef _MSC_VER diff --git a/src/mingw/mingw.h b/src/mingw/mingw.h index 4fe07e611..e3a7267a9 100644 --- a/src/mingw/mingw.h +++ b/src/mingw/mingw.h @@ -60,7 +60,7 @@ SOCKET win32_socket(int, int, int); int win32_connect(SOCKET, struct sockaddr*, socklen_t); SOCKET win32_accept(SOCKET, struct sockaddr*, socklen_t *); int win32_shutdown(SOCKET, int); -int win32_close_socket(SOCKET fd); +int win32_close_socket(SOCKET fd); #define strtok_r(x, y, z) win32_strtok_r(x, y, z) #define strsep(x,y) win32_strsep(x,y) diff --git a/src/mmap.c b/src/mmap.c index cc5346f18..90ae5fc17 100644 --- a/src/mmap.c +++ b/src/mmap.c @@ -15,7 +15,11 @@ void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offs buf = malloc(len); if ( NULL == buf ) return MAP_FAILED; - if (lseek(fd,offset,SEEK_SET) != offset) return MAP_FAILED; + if (lseek(fd,offset,SEEK_SET) != offset) { + free(buf); + return MAP_FAILED; + } + count = read(fd, buf, len); diff --git a/src/sg.c b/src/sg.c index 285e2bd90..e7ff5d14e 100644 --- a/src/sg.c +++ b/src/sg.c @@ -945,7 +945,6 @@ static stlink_backend_t _stlink_sg_backend = { static stlink_t* stlink_open(const int verbose) { stlink_t *sl = malloc(sizeof (stlink_t)); - memset(sl, 0, sizeof(stlink_t)); struct stlink_libsg *slsg = malloc(sizeof (struct stlink_libsg)); if (sl == NULL || slsg == NULL) { WLOG("Couldn't malloc stlink and stlink_sg structures out of memory!\n"); @@ -955,6 +954,7 @@ static stlink_t* stlink_open(const int verbose) { free(slsg); return NULL; } + memset(sl, 0, sizeof(stlink_t)); if (libusb_init(&(slsg->libusb_ctx))) { WLOG("failed to init libusb context, wrong version of libraries?\n"); diff --git a/src/usb.c b/src/usb.c index c4d39ac5f..34586640e 100644 --- a/src/usb.c +++ b/src/usb.c @@ -625,7 +625,7 @@ int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg if (ret == -1) return ret; - _stlink_usb_read_mem32(sl, STLINK_REG_DCRDR, 4); + ret = _stlink_usb_read_mem32(sl, STLINK_REG_DCRDR, 4); if (ret == -1) return ret; From df3c2b02867db03fb82f6faaad71300398965e85 Mon Sep 17 00:00:00 2001 From: Michael DL6AKU Date: Thu, 6 Jun 2019 19:50:22 +0200 Subject: [PATCH 0662/1435] Allow for 64 Bytes serials (#809) --- include/stlink.h | 4 +++- include/stlink/tools/flash.h | 2 +- include/stlink/usb.h | 2 +- src/usb.c | 4 ++-- 4 files changed, 7 insertions(+), 5 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index d5e8270ac..96be91033 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -66,6 +66,8 @@ extern "C" { #define STLINK_SWDCLK_15KHZ_DIVISOR 265 #define STLINK_SWDCLK_5KHZ_DIVISOR 798 +#define STLINK_SERIAL_MAX_SIZE 64 + /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 @@ -144,7 +146,7 @@ typedef struct flash_loader { uint32_t chip_id; int core_stat; - char serial[16]; + char serial[STLINK_SERIAL_MAX_SIZE]; int serial_size; enum stlink_flash_type flash_type; diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index 3d1375aa2..af82198f2 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -13,7 +13,7 @@ struct flash_opts { enum flash_cmd cmd; const char* devname; - uint8_t serial[16]; + uint8_t serial[STLINK_SERIAL_MAX_SIZE]; const char* filename; stm32_addr_t addr; size_t size; diff --git a/include/stlink/usb.h b/include/stlink/usb.h index 9e27db156..621695ea4 100644 --- a/include/stlink/usb.h +++ b/include/stlink/usb.h @@ -45,7 +45,7 @@ extern "C" { * @retval NULL Error while opening the stlink * @retval !NULL Stlink found and ready to use */ - stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16]); + stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[STLINK_SERIAL_MAX_SIZE]); size_t stlink_probe_usb(stlink_t **stdevs[]); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); diff --git a/src/usb.c b/src/usb.c index 34586640e..7f5c21283 100644 --- a/src/usb.c +++ b/src/usb.c @@ -767,7 +767,7 @@ static stlink_backend_t _stlink_usb_backend = { _stlink_usb_set_swdclk }; -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[16]) +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[STLINK_SERIAL_MAX_SIZE]) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; @@ -1003,7 +1003,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { continue; struct libusb_device_handle* handle; - char serial[16]; + char serial[STLINK_SERIAL_MAX_SIZE]; memset(serial, 0, sizeof(serial)); ret = libusb_open(dev, &handle); From 84f63d25bd77d61f8feccf08dd24d0d11895ef32 Mon Sep 17 00:00:00 2001 From: Vasiliy Zasukhin <50801920+Humanoid0@users.noreply.github.com> Date: Thu, 6 Jun 2019 20:53:03 +0300 Subject: [PATCH 0663/1435] Add support for CS32F103C8T6 (#805) CS32F103C8T6 is clone of STM32F103C8T6 but with incorrect core_id number. --- src/flash_loader.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/flash_loader.c b/src/flash_loader.c index f2e636751..73db427a7 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -262,6 +262,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID + || sl->chip_id == STLINK_CHIPID_STM32_F1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_F3 || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH From 625f4cd57242c974ea9e53de801b6fd53708926f Mon Sep 17 00:00:00 2001 From: eupn <36292692+eupn@users.noreply.github.com> Date: Sun, 14 Jul 2019 16:02:42 +0700 Subject: [PATCH 0664/1435] WB55: fix flash verification error (#816) * Clear previously written page number (if any) * Remove unrelated change --- src/common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/common.c b/src/common.c index 19cfd4f87..b4741a585 100644 --- a/src/common.c +++ b/src/common.c @@ -1759,8 +1759,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) if (sl->flash_type == STLINK_FLASH_TYPE_WB) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + // sec 3.10.5 - PNB[7:0] is offset by 3. + val &= ~(0xFF << 3); // Clear previously set page number (if any) val |= ((flash_page & 0xFF) << 3); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); From 728049b244d7a7f7c2e7415af4a6a5001cbe928a Mon Sep 17 00:00:00 2001 From: Benjamin Henrion Date: Fri, 26 Jul 2019 13:19:32 +0200 Subject: [PATCH 0665/1435] Add stlink-tools link for Debian and Ubuntu Add stlink-tools link for Debian and Ubuntu --- README.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index d711d323f..285c3f751 100644 --- a/README.md +++ b/README.md @@ -28,8 +28,9 @@ Windows users can [download v1.3.0](https://github.com/texane/stlink/releases/ta Mac OS X users can install from [homebrew](http://brewformulas.org/Stlink) or [download v1.3.0](https://github.com/texane/stlink/releases/tag/1.3.0) from the releases page. -For Debian Linux based distributions there is no package available - in the standard repositories so you need to install [from source](doc/compiling.md) yourself. +Debian Linux users can install it via the ```stlink-tool``` package [repository](https://packages.debian.org/buster/stlink-tools) + +Ubuntu Linux users can install it via the ```stlink-tool``` package [repository](https://packages.ubuntu.com/cosmic/stlink-tools) Arch Linux users can install from the [repository](https://www.archlinux.org/packages/community/x86_64/stlink) From 8c8285f47e183d8e7e93bce0ce31d2f13590a701 Mon Sep 17 00:00:00 2001 From: William Ransohoff <> Date: Fri, 26 Jul 2019 20:31:24 -0700 Subject: [PATCH 0666/1435] Add support for STM32G4 series --- include/stlink.h | 1 + include/stlink/chipid.h | 2 + src/chipid.c | 13 ++- src/common.c | 197 +++++++++++++++++++++++----------------- 4 files changed, 130 insertions(+), 83 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index 96be91033..c664e2e66 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -79,6 +79,7 @@ extern "C" { STLINK_FLASH_TYPE_L4, STLINK_FLASH_TYPE_F1_XL, STLINK_FLASH_TYPE_G0, + STLINK_FLASH_TYPE_G4, STLINK_FLASH_TYPE_WB }; diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index a4f4be4c0..e9cb48167 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -72,6 +72,8 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F413 = 0x463, STLINK_CHIPID_STM32_L4RX = 0x470, // taken from the STM32L4R9I-DISCO board STLINK_CHIPID_STM32_G0X1 = 0x460, + STLINK_CHIPID_STM32_G4_CAT2 = 0x468, // See: RM 0440 s46.6.1 "MCU device ID code". + STLINK_CHIPID_STM32_G4_CAT3 = 0x469, STLINK_CHIPID_STM32_WB55 = 0x495 }; diff --git a/src/chipid.c b/src/chipid.c index d627849a3..938cc1f30 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -530,7 +530,18 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // 2K (sec 3.2) .sram_size = 0x9000, // 36K (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 // 30K (table 2) + .bootrom_size = 0x7000 // 28K (table 2) + }, + { + // STM32G431/441 (from RM0440) + .chip_id = STLINK_CHIPID_STM32_G4_CAT2, + .description = "G4 Category-2 device", + .flash_type = STLINK_FLASH_TYPE_G4, + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = 0x800, // 2K (sec 3.3.1) + .sram_size = 0x8000, // 32K (sec 2.4) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000 // 28K (table 2) }, { // STM32WB55 (from RM0434) diff --git a/src/common.c b/src/common.c index b4741a585..d253e2b24 100644 --- a/src/common.c +++ b/src/common.c @@ -74,15 +74,20 @@ #define FLASH_L1_FPRG 10 #define FLASH_L1_PROG 3 +// Flash registers common to STM32G0 and STM32G4 series. +#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define STM32Gx_FLASH_ACR (STM32G0_FLASH_REGS_ADDR + 0x00) +#define STM32Gx_FLASH_KEYR (STM32G0_FLASH_REGS_ADDR + 0x08) +#define STM32Gx_FLASH_OPTKEYR (STM32G0_FLASH_REGS_ADDR + 0x0c) +#define STM32Gx_FLASH_SR (STM32G0_FLASH_REGS_ADDR + 0x10) +#define STM32Gx_FLASH_CR (STM32G0_FLASH_REGS_ADDR + 0x14) +#define STM32Gx_FLASH_ECCR (STM32G0_FLASH_REGS_ADDR + 0x18) +#define STM32Gx_FLASH_OPTR (STM32G0_FLASH_REGS_ADDR + 0x20) + // G0 (RM0444 Table 1, sec 3.7) -#define STM32G0_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32G0_FLASH_ACR (STM32G0_FLASH_REGS_ADDR + 0x00) -#define STM32G0_FLASH_KEYR (STM32G0_FLASH_REGS_ADDR + 0x08) -#define STM32G0_FLASH_OPTKEYR (STM32G0_FLASH_REGS_ADDR + 0x0c) -#define STM32G0_FLASH_SR (STM32G0_FLASH_REGS_ADDR + 0x10) -#define STM32G0_FLASH_CR (STM32G0_FLASH_REGS_ADDR + 0x14) -#define STM32G0_FLASH_ECCR (STM32G0_FLASH_REGS_ADDR + 0x18) -#define STM32G0_FLASH_OPTR (STM32G0_FLASH_REGS_ADDR + 0x20) +// Mostly the same as G4 chips, but the notation +// varies a bit after the 'OPTR' register. +#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) #define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) #define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) #define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) @@ -91,21 +96,39 @@ #define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) #define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) -// GO FLASH control register -#define STM32G0_FLASH_CR_PG 0 /* Program */ -#define STM32G0_FLASH_CR_PER 1 /* Page erase */ -#define STM32G0_FLASH_CR_MER1 2 /* Mass erase */ -#define STM32G0_FLASH_CR_PNB 3 /* Page number (5 bits) */ -#define STM32G0_FLASH_CR_STRT 16 /* Start */ -#define STM32G0_FLASH_CR_OPTSTRT 17 /* Start of modification of option bytes */ -#define STM32G0_FLASH_CR_FSTPG 18 /* Fast programming */ -#define STM32G0_FLASH_CR_EOPIE 24 /* End of operation interrupt enable */ -#define STM32G0_FLASH_CR_ERRIE 25 /* Error interrupt enable */ -#define STM32G0_FLASH_CR_OBL_LAUNCH 27 /* Forces the option byte loading */ -#define STM32G0_FLASH_CR_OPTLOCK 30 /* Options Lock */ -#define STM32G0_FLASH_CR_LOCK 31 /* FLASH_CR Lock */ -// GO FLASH status register -#define STM32G0_FLASH_SR_BSY 16 /* FLASH_SR Busy */ +// G4 (RM0440 Table 17, sec 3.7.19) +// Mostly the same as STM32G0 chips, but there are a few extra +// registers because 'cat 3' devices can have two Flash banks. +#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) +#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) +#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) +#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) +#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) +#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) +#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) +#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) +#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) +#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) +#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) +#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) + +// G0/G4 FLASH control register +#define STM32Gx_FLASH_CR_PG (0) /* Program */ +#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ +#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ +#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ +#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ +#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define STM32Gx_FLASH_CR_STRT (16) /* Start */ +#define STM32Gx_FLASH_CR_OPTSTRT (17) /* Start of modification of option bytes */ +#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ +#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ +#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ +#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ +#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ +// G0/G4 FLASH status register +#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ // WB (RM0434) #define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) @@ -249,8 +272,8 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { reg = FLASH_F4_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) reg = STM32L4_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0) - reg = STM32G0_FLASH_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + reg = STM32Gx_FLASH_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) reg = STM32WB_FLASH_CR; else @@ -281,8 +304,8 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { cr_lock_shift = FLASH_F4_CR_LOCK; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) cr_lock_shift = STM32L4_FLASH_CR_LOCK; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0) - cr_lock_shift = STM32G0_FLASH_CR_LOCK; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) cr_lock_shift = STM32WB_FLASH_CR_LOCK; else @@ -302,8 +325,8 @@ static void unlock_flash(stlink_t *sl) { key_reg = FLASH_F4_KEYR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) key_reg = STM32L4_FLASH_KEYR; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0) - key_reg = STM32G0_FLASH_KEYR; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + key_reg = STM32Gx_FLASH_KEYR; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) key_reg = STM32WB_FLASH_KEYR; else @@ -341,9 +364,9 @@ static void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { - cr_reg = STM32G0_FLASH_CR; - cr_lock_shift = STM32G0_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; @@ -374,8 +397,8 @@ static void set_flash_cr_pg(stlink_t *sl) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= 1 << STM32L4_FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { - cr_reg = STM32G0_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; @@ -395,8 +418,8 @@ static void clear_flash_cr_pg(stlink_t *sl) { cr_reg = FLASH_F4_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) cr_reg = STM32L4_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0) - cr_reg = STM32G0_FLASH_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + cr_reg = STM32Gx_FLASH_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) cr_reg = STM32WB_FLASH_CR; else @@ -409,8 +432,8 @@ static void clear_flash_cr_pg(stlink_t *sl) { static void set_flash_cr_per(stlink_t *sl) { uint32_t cr_reg, val; - if (sl->flash_type == STLINK_FLASH_TYPE_G0) - cr_reg = STM32G0_FLASH_CR; + if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + cr_reg = STM32Gx_FLASH_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) cr_reg = STM32WB_FLASH_CR; else @@ -429,8 +452,8 @@ static void set_flash_cr2_per(stlink_t *sl) { static void clear_flash_cr_per(stlink_t *sl) { uint32_t cr_reg; - if (sl->flash_type == STLINK_FLASH_TYPE_G0) - cr_reg = STM32G0_FLASH_CR; + if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + cr_reg = STM32Gx_FLASH_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) cr_reg = STM32WB_FLASH_CR; else @@ -451,8 +474,8 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); cr_pg = 1 << STM32L4_FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { - cr_reg = STM32G0_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { @@ -521,9 +544,9 @@ static void set_flash_cr_strt(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_strt = 1 << STM32L4_FLASH_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { - cr_reg = STM32G0_FLASH_CR; - cr_strt = 1 << STM32G0_FLASH_CR_STRT; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_strt = 1 << STM32Gx_FLASH_CR_STRT; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; cr_strt = 1 << STM32WB_FLASH_CR_STRT; @@ -552,8 +575,8 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { sr_reg = FLASH_F4_SR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) sr_reg = STM32L4_FLASH_SR; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0) - sr_reg = STM32G0_FLASH_SR; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + sr_reg = STM32Gx_FLASH_SR; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) sr_reg = STM32WB_FLASH_SR; else @@ -578,8 +601,8 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { sr_busy_shift = FLASH_F4_SR_BSY; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) sr_busy_shift = STM32L4_FLASH_SR_BSY; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0) - sr_busy_shift = STM32G0_FLASH_SR_BSY; + else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + sr_busy_shift = STM32Gx_FLASH_SR_BSY; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) sr_busy_shift = STM32WB_FLASH_SR_BSY; else @@ -1746,7 +1769,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0) { + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { uint32_t val; // Wait for any ongoing Flash operation to finish. wait_flash_busy(sl); @@ -1767,10 +1791,18 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_write_debug32(sl, STM32WB_FLASH_CR, val); } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. - val = ((flash_page & 0x3F) << 3) | ( 1 << FLASH_CR_PER ); - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + val &= ~(0x3F << 3); + val |= ((flash_page & 0x3F) << 3) | ( 1 << FLASH_CR_PER ); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. + val &= ~(0x7F << 3); + val |= ((flash_page & 0x7F) << 3) | ( 1 << FLASH_CR_PER ); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); } // Set the 'start operation' bit. @@ -1834,8 +1866,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } int stlink_erase_flash_mass(stlink_t *sl) { - /* TODO: User MER bit to mass-erase G0, WB series. */ - if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_WB) { + /* TODO: User MER bit to mass-erase G0, G4, WB series. */ + if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4 || sl->flash_type == STLINK_FLASH_TYPE_WB) { /* erase each page */ int i = 0, num_pages = (int) sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -2121,7 +2153,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } //STM32F4END else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0) { + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { fprintf(stdout, "Writing\r\n"); fflush(stdout); // Wait for any ongoing operations to finish. @@ -2526,32 +2559,32 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui } /* Unlock flash if necessary (ref manuel page 52) */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - if ((val & (1u << STM32G0_FLASH_CR_LOCK))) { + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + if ((val & (1u << STM32Gx_FLASH_CR_LOCK))) { /* disable flash write protection. */ - stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0x45670123); - stlink_write_debug32(sl, STM32G0_FLASH_KEYR, 0xCDEF89AB); + stlink_write_debug32(sl, STM32Gx_FLASH_KEYR, 0x45670123); + stlink_write_debug32(sl, STM32Gx_FLASH_KEYR, 0xCDEF89AB); // check that the lock is no longer set. - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - if ((val & (1u << STM32G0_FLASH_CR_LOCK))) { + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + if ((val & (1u << STM32Gx_FLASH_CR_LOCK))) { ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); return -1; } } /* Unlock option bytes if necessary (ref manuel page 61) */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - if ((val & (1 << STM32G0_FLASH_CR_OPTLOCK))) { + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + if ((val & (1 << STM32Gx_FLASH_CR_OPTLOCK))) { /* disable option byte write protection. */ - stlink_write_debug32(sl, STM32G0_FLASH_OPTKEYR, 0x08192A3B); - stlink_write_debug32(sl, STM32G0_FLASH_OPTKEYR, 0x4C5D6E7F); + stlink_write_debug32(sl, STM32Gx_FLASH_OPTKEYR, 0x08192A3B); + stlink_write_debug32(sl, STM32Gx_FLASH_OPTKEYR, 0x4C5D6E7F); /* check that the lock is no longer set. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - if ((val & (1 << STM32G0_FLASH_CR_OPTLOCK))) { + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + if ((val & (1 << STM32Gx_FLASH_CR_OPTLOCK))) { ELOG("Options bytes unlock failed! System reset required to be able to unlock it again!\n"); return -1; } @@ -2562,31 +2595,31 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui write_uint32((unsigned char*) &data, *(uint32_t*) (base)); WLOG("Writing option bytes 0x%04x\n", data); //stlink_write_debug32(sl, addr, data); - stlink_write_debug32(sl, STM32G0_FLASH_OPTR, data); + stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); /* Set Options Start bit */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= (1 << STM32G0_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); /* Wait for 'busy' bit in FLASH_SR to clear. */ do { - stlink_read_debug32(sl, STM32G0_FLASH_SR, &val); + stlink_read_debug32(sl, STM32Gx_FLASH_SR, &val); } while ((val & (1 << 16)) != 0); /* apply options bytes immediate */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= (1 << STM32G0_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); /* Re-lock option bytes */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= (1u << STM32G0_FLASH_CR_OPTLOCK); - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1u << STM32Gx_FLASH_CR_OPTLOCK); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); /* Re-lock flash. */ - stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); - val |= (1u << STM32G0_FLASH_CR_LOCK); - stlink_write_debug32(sl, STM32G0_FLASH_CR, val); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1u << STM32Gx_FLASH_CR_LOCK); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); return 0; } From 44aab55ddc291c381b6c1ab3544cda57638511fc Mon Sep 17 00:00:00 2001 From: MFaehling <53976201+MFaehling@users.noreply.github.com> Date: Sat, 10 Aug 2019 19:46:01 +0200 Subject: [PATCH 0667/1435] Add aliased SRAM2 region in the L496 memory map The SRAM2 on the L496 devices is aliased at 0x2004000. With this change, it's possible to read the SRAM2 contents at the aliased addresses. --- src/gdbserver/gdb-server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index bdfeb703d..a874a81da 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -449,7 +449,7 @@ static const char* const memory_map_template_L496 = "" " " // code = sram, bootrom or flash; flash is bigger " " // SRAM2 (64 KB) - " " // SRAM1 (256 KB) + " " // SRAM1 + aliased SRAM2 (256+64=320 KB) " " " 0x800" " " From 156871d55efc1b53a8efceafb64318198d819252 Mon Sep 17 00:00:00 2001 From: WRR <-@-> Date: Mon, 12 Aug 2019 11:37:00 -0700 Subject: [PATCH 0668/1435] Add support for STM32G031 and STM32G041 chips. Including the 8-pin STM32G031J6 :D --- include/stlink/chipid.h | 3 ++- src/chipid.c | 13 ++++++++++++- src/common.c | 2 +- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index a4f4be4c0..9ff8c814f 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -71,7 +71,8 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F410 = 0x458, STLINK_CHIPID_STM32_F413 = 0x463, STLINK_CHIPID_STM32_L4RX = 0x470, // taken from the STM32L4R9I-DISCO board - STLINK_CHIPID_STM32_G0X1 = 0x460, + STLINK_CHIPID_STM32_G0_CAT1 = 0x466, // G031/041 + STLINK_CHIPID_STM32_G0_CAT2 = 0x460, // G071/081 STLINK_CHIPID_STM32_WB55 = 0x495 }; diff --git a/src/chipid.c b/src/chipid.c index d627849a3..7b7bc88d0 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -521,9 +521,20 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1ff00000, .bootrom_size = 0x2000 }, + { + // STM32G031/041 (from RM0444) + .chip_id = STLINK_CHIPID_STM32_G0_CAT1, + .description = "G031/G041 device", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2K (sec 3.2) + .sram_size = 0x2000, // 8K (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 // 30K (table 3) + }, { // STM32G071/081 (from RM0444) - .chip_id = STLINK_CHIPID_STM32_G0X1, + .chip_id = STLINK_CHIPID_STM32_G0_CAT2, .description = "G071/G081 device", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 diff --git a/src/common.c b/src/common.c index b4741a585..f974d77ab 100644 --- a/src/common.c +++ b/src/common.c @@ -2520,7 +2520,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui stlink_core_id(sl); /* Check if chip is supported and for correct address */ - if((sl->chip_id != STLINK_CHIPID_STM32_G0X1) || (addr != STM32_G0_OPTION_BYTES_BASE)) { + if((sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2 && sl->chip_id != STLINK_CHIPID_STM32_G0_CAT1) || (addr != STM32_G0_OPTION_BYTES_BASE)) { ELOG("Option bytes writing is currently only supported for the STM32G0\n"); return -1; } From 4909dd808ad316439a7932c1381fc195100c6cf2 Mon Sep 17 00:00:00 2001 From: Jerry Jacobs Date: Sat, 17 Aug 2019 10:42:14 +0200 Subject: [PATCH 0669/1435] README.md: Add notice of wanted project maintainer --- README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/README.md b/README.md index d711d323f..9aa7e6b4e 100644 --- a/README.md +++ b/README.md @@ -8,6 +8,8 @@ Open source version of the STMicroelectronics Stlink Tools [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) [![Build Status](https://jenkins.ncrmnt.org/buildStatus/icon?job=GithubCI/stlink)](https://jenkins.ncrmnt.org/job/GithubCI/job/stlink/) +**NOTICE: The project has currently not an active maintainer. Feel free to contribute and discus in issue [#826](https://github.com/texane/stlink/issues/826)** + ## HOWTO First, you have to know there are several boards supported by the software. From 738e48eed576d4d36aa5ea8950f2c274ddc54777 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 2 Sep 2019 14:35:35 +0200 Subject: [PATCH 0670/1435] Do not issue JTAG reset on stlink-v1 --- src/tools/flash.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/src/tools/flash.c b/src/tools/flash.c index 768e9834f..b926a8f9a 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -92,9 +92,11 @@ int main(int ac, char** av) } if (o.reset){ - if (stlink_jtag_reset(sl, 2)) { - printf("Failed to reset JTAG\n"); - goto on_error; + if (sl->version.stlink_v > 1) { + if (stlink_jtag_reset(sl, 2)) { + printf("Failed to reset JTAG\n"); + goto on_error; + } } if (stlink_reset(sl)) { @@ -185,9 +187,11 @@ int main(int ac, char** av) } } else if (o.cmd == CMD_RESET) { - if (stlink_jtag_reset(sl, 2)) { - printf("Failed to reset JTAG\n"); - goto on_error; + if (sl->version.stlink_v > 1) { + if (stlink_jtag_reset(sl, 2)) { + printf("Failed to reset JTAG\n"); + goto on_error; + } } if (stlink_reset(sl)) { @@ -212,7 +216,7 @@ int main(int ac, char** av) } if (o.reset){ - stlink_jtag_reset(sl,2); + if (sl->version.stlink_v > 1) stlink_jtag_reset(sl, 2); stlink_reset(sl); } From 32e082619506f585475d76c495b585194e68333c Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 2 Sep 2019 17:47:34 +0200 Subject: [PATCH 0671/1435] Fix flash size of stm32discovery vl --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index b4741a585..4f1a3d698 100644 --- a/src/common.c +++ b/src/common.c @@ -800,7 +800,7 @@ int stlink_load_device_params(stlink_t *sl) { flash_size = flash_size >>16; flash_size = flash_size & 0xffff; - if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && ( flash_size == 0 )) { + if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && ( flash_size == 0 )) { sl->flash_size = 128 * 1024; } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { sl->flash_size = (flash_size & 0xff) * 1024; From e56de83ec50e2e1c7f9c9f19b69c543deb2d6d21 Mon Sep 17 00:00:00 2001 From: Adrian Imboden Date: Fri, 6 Sep 2019 18:23:37 +0200 Subject: [PATCH 0672/1435] added support for writing option bytes on STM32L0 --- README.md | 2 +- include/stm32.h | 1 + src/common.c | 99 +++++++++++++++++++++++++++++++++++++++++------ src/tools/flash.c | 2 +- 4 files changed, 91 insertions(+), 13 deletions(-) diff --git a/README.md b/README.md index 9aa7e6b4e..1146cf28a 100644 --- a/README.md +++ b/README.md @@ -150,7 +150,7 @@ then it would be written to the memory. ## Writing Option Bytes -Example to read and write option bytes (currently writing only supported for STM32G0) +Example to read and write option bytes (currently writing only supported for STM32G0 and STM32L0) ``` ./st-flash --debug --reset --format binary --flash=128k read option_bytes_dump.bin 0x1FFF7800 4 ./st-flash --debug --reset --format binary --flash=128k write option_bytes_dump.bin 0x1FFF7800 diff --git a/include/stm32.h b/include/stm32.h index f5dbe4b2d..a19707bc2 100644 --- a/include/stm32.h +++ b/include/stm32.h @@ -15,5 +15,6 @@ #define STM32_FLASH_BASE ((uint32_t)0x08000000) #define STM32_SRAM_BASE ((uint32_t)0x20000000) #define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) +#define STM32_L0_CAT2_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) #endif /* STM32_H */ diff --git a/src/common.c b/src/common.c index 4f1a3d698..25900abdd 100644 --- a/src/common.c +++ b/src/common.c @@ -165,6 +165,9 @@ //same as 32L1 above // RM0090 - DM00031020.pdf #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define STM32L0_FLASH_PELOCK_BIT (1u << 0) +#define STM32L0_FLASH_OPTLOCK_BIT (1u << 2) +#define STM32L0_FLASH_OBL_LAUNCH_BIT (1u << 18) #define FLASH_ACR_OFF ((uint32_t) 0x00) #define FLASH_PECR_OFF ((uint32_t) 0x04) #define FLASH_PDKEYR_OFF ((uint32_t) 0x08) @@ -2507,7 +2510,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { * @param base option bytes to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { +static int stlink_write_option_bytes_g0x1(stlink_t *sl, uint8_t* base, uint32_t len) { uint32_t val; @@ -2516,15 +2519,6 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui return -1; } - // Make sure we've loaded the context with the chip details - stlink_core_id(sl); - - /* Check if chip is supported and for correct address */ - if((sl->chip_id != STLINK_CHIPID_STM32_G0X1) || (addr != STM32_G0_OPTION_BYTES_BASE)) { - ELOG("Option bytes writing is currently only supported for the STM32G0\n"); - return -1; - } - /* Unlock flash if necessary (ref manuel page 52) */ stlink_read_debug32(sl, STM32G0_FLASH_CR, &val); if ((val & (1u << STM32G0_FLASH_CR_LOCK))) { @@ -2561,7 +2555,6 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui uint32_t data; write_uint32((unsigned char*) &data, *(uint32_t*) (base)); WLOG("Writing option bytes 0x%04x\n", data); - //stlink_write_debug32(sl, addr, data); stlink_write_debug32(sl, STM32G0_FLASH_OPTR, data); /* Set Options Start bit */ @@ -2591,6 +2584,90 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui return 0; } + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_l0_cat2(stlink_t *sl, uint8_t* base, uint32_t len) { + + uint32_t val; + + if(len != 4) { + ELOG("Wrong length for writting option bytes, must be 4 is %d\n", len); + return -1; + } + stlink_read_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); + if (val & STM32L0_FLASH_PELOCK_BIT) { + WLOG("Unlocking flash\n"); + //Unlock data EEPROM and the FLASH_PECR register (reference page 74) + stlink_write_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PEKEYR_OFF, 0x89ABCDEF); + stlink_write_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PEKEYR_OFF, 0x02030405); + + stlink_read_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); + if (val & STM32L0_FLASH_PELOCK_BIT) { + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; + } + } + + stlink_read_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); + if ((val & (STM32L0_FLASH_OPTLOCK_BIT))) { + WLOG("Unlocking options\n"); + //Unlock the Option bytes area (reference page 76) + stlink_write_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_OPTKEYR_OFF, 0xFBEAD9C8); + stlink_write_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_OPTKEYR_OFF, 0x24252627); + + stlink_read_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); + if (val & STM32L0_FLASH_OPTLOCK_BIT) { + ELOG("Options unlock failed! System reset required to be able to unlock it again!\n"); + return -1; + } + } + + /* Write options bytes */ + uint32_t data; + write_uint32((unsigned char*) &data, *(uint32_t*) (base)); + WLOG("Writing option bytes 0x%04x\n", data); + stlink_write_debug32(sl, STM32_L0_CAT2_OPTION_BYTES_BASE, data); + + /* Reload options */ + stlink_read_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); + val |= (STM32L0_FLASH_OBL_LAUNCH_BIT); + stlink_write_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, val); + + return 0; +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { + + // Make sure we've loaded the context with the chip details + stlink_core_id(sl); + + /* Check if chip is supported and for correct address */ + if((sl->chip_id == STLINK_CHIPID_STM32_G0X1) && (addr == STM32_G0_OPTION_BYTES_BASE)) { + return stlink_write_option_bytes_g0x1(sl, base, len); + } + else if((sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) && (addr == STM32_L0_CAT2_OPTION_BYTES_BASE)) { + return stlink_write_option_bytes_l0_cat2(sl, base, len); + } + else { + ELOG("Option bytes writing is currently only supported for the STM32G0 and STM32L0\n"); + return -1; + } + +} + /** * Write the given binary file with option bytes * @param sl diff --git a/src/tools/flash.c b/src/tools/flash.c index b926a8f9a..1a02b4fb4 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -164,7 +164,7 @@ int main(int ac, char** av) goto on_error; } } - else if (o.addr == STM32_G0_OPTION_BYTES_BASE) { + else if (o.addr == STM32_G0_OPTION_BYTES_BASE || o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE) { err = stlink_fwrite_option_bytes(sl, o.filename, o.addr); if (err == -1) { From bc01701a8d58a68fe78f6823813293fb3192d46a Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 29 Sep 2019 12:42:14 +0100 Subject: [PATCH 0673/1435] Apply cross.patch to fix cross-compiling the GUI. Thanks Helmut for the patch! (Closes: #941320) Gbp-Dch: full --- debian/patches/cross.patch | 15 +++++++++++++++ debian/patches/series | 1 + 2 files changed, 16 insertions(+) create mode 100644 debian/patches/cross.patch create mode 100644 debian/patches/series diff --git a/debian/patches/cross.patch b/debian/patches/cross.patch new file mode 100644 index 000000000..92084238b --- /dev/null +++ b/debian/patches/cross.patch @@ -0,0 +1,15 @@ +Author: Helmut Grohne +Description: do not stop the GUI from being cross-compiled +Bug-Debian: 941320 +Forwarded: yes +--- a/CMakeLists.txt ++++ b/CMakeLists.txt +@@ -39,7 +39,7 @@ + # Dependencies + ### + find_package(LibUSB REQUIRED) +-if (NOT APPLE AND NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) ++if (NOT APPLE AND NOT WIN32) + find_package(PkgConfig) + pkg_check_modules(gtk gtk+-3.0) + endif () diff --git a/debian/patches/series b/debian/patches/series new file mode 100644 index 000000000..def274a02 --- /dev/null +++ b/debian/patches/series @@ -0,0 +1 @@ +cross.patch From ecfb5becd0e091000ea8dc6058a214305b1b319b Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 29 Sep 2019 12:44:22 +0100 Subject: [PATCH 0674/1435] Vcs-Git: add -b debian --- debian/control | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian/control b/debian/control index 1499dcf1a..5994ea084 100644 --- a/debian/control +++ b/debian/control @@ -5,7 +5,7 @@ Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.1.3 Section: electronics Homepage: https://github.com/texane/stlink -Vcs-Git: https://github.com/bluca/stlink.git +Vcs-Git: https://github.com/bluca/stlink.git -b debian Vcs-Browser: https://github.com/bluca/stlink Package: libstlink-dev From 52189af7a2274b7a57b4ae36454df62bf9e06b5d Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 29 Sep 2019 12:45:57 +0100 Subject: [PATCH 0675/1435] Set Rules-Requires-Root: no --- debian/control | 1 + 1 file changed, 1 insertion(+) diff --git a/debian/control b/debian/control index 5994ea084..e38a046fd 100644 --- a/debian/control +++ b/debian/control @@ -3,6 +3,7 @@ Priority: optional Maintainer: Luca Boccassi Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.1.3 +Rules-Requires-Root: no Section: electronics Homepage: https://github.com/texane/stlink Vcs-Git: https://github.com/bluca/stlink.git -b debian From 4f29ef92bf5095f3152564319a2be4bda1d1d7df Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 29 Sep 2019 12:48:53 +0100 Subject: [PATCH 0676/1435] Bump Standards-Version to 4.4.0 --- debian/control | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian/control b/debian/control index e38a046fd..c541d5bef 100644 --- a/debian/control +++ b/debian/control @@ -2,7 +2,7 @@ Source: stlink Priority: optional Maintainer: Luca Boccassi Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev -Standards-Version: 4.1.3 +Standards-Version: 4.4.0 Rules-Requires-Root: no Section: electronics Homepage: https://github.com/texane/stlink From 0b629606aaa7608656487eccf7dd55c647743e4e Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 29 Sep 2019 12:51:05 +0100 Subject: [PATCH 0677/1435] Update changelog for 1.5.1+ds-2 release --- debian/changelog | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/debian/changelog b/debian/changelog index b0c877388..5d132ca55 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,14 @@ +stlink (1.5.1+ds-2) unstable; urgency=medium + + * Mark library packages as Multi-Arch: same. + * Apply cross.patch to fix cross-compiling the GUI. Thanks Helmut for + the patch! (Closes: #941320) + * Vcs-Git: add -b debian + * Set Rules-Requires-Root: no + * Bump Standards-Version to 4.4.0 + + -- Luca Boccassi Sun, 29 Sep 2019 12:50:58 +0100 + stlink (1.5.1+ds-1) unstable; urgency=medium * Merge tag 'v1.5.1' into debian. See upstream changelog for info: From 4eec4d8cb9ace920bbce8f023c5f39dbcb35e770 Mon Sep 17 00:00:00 2001 From: orie Date: Mon, 7 Oct 2019 14:46:36 +0900 Subject: [PATCH 0678/1435] Add Option Byte Write command for STM32F2 series. --- include/stlink.h | 1 + include/stlink/tools/flash.h | 5 ++- include/stm32.h | 2 +- src/common.c | 87 +++++++++++++++++++++++++++++++++++- src/tools/flash.c | 13 ++++-- src/tools/flash_opts.c | 30 ++++++++++++- 6 files changed, 131 insertions(+), 7 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index 96be91033..50f86c11b 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -200,6 +200,7 @@ typedef struct flash_loader { int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); + int stlink_fwrite_option_bytes_32bit(stlink_t *sl,uint32_t val); int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index af82198f2..8ca1eddf9 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -9,6 +9,7 @@ enum flash_cmd {FLASH_CMD_NONE = 0, FLASH_CMD_WRITE = 1, FLASH_CMD_READ = 2, FLASH_CMD_ERASE = 3, CMD_RESET = 4}; enum flash_format {FLASH_FORMAT_BINARY = 0, FLASH_FORMAT_IHEX = 1}; +enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1,FLASH_OTP = 2, FLASH_OPTION_BYTES = 3}; struct flash_opts { enum flash_cmd cmd; @@ -20,10 +21,12 @@ struct flash_opts int reset; int log_level; enum flash_format format; + enum flash_area area; + uint32_t val; size_t flash_size; /* --flash=n[k][m] */ }; -#define FLASH_OPTS_INITIALIZER {0, NULL, { 0 }, NULL, 0, 0, 0, 0, 0, 0 } +#define FLASH_OPTS_INITIALIZER {0, NULL, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0 } int flash_get_opts(struct flash_opts* o, int ac, char** av); diff --git a/include/stm32.h b/include/stm32.h index a19707bc2..8f8e7eba1 100644 --- a/include/stm32.h +++ b/include/stm32.h @@ -16,5 +16,5 @@ #define STM32_SRAM_BASE ((uint32_t)0x20000000) #define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L0_CAT2_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) - +#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) #endif /* STM32_H */ diff --git a/src/common.c b/src/common.c index 25900abdd..bf1aba64c 100644 --- a/src/common.c +++ b/src/common.c @@ -194,6 +194,23 @@ #define FLASH_F4_CR_SNB_MASK 0xf8 #define FLASH_F4_SR_BSY 16 +//STM32F2 +#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) +#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) +#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) +#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) +#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) +#define FLASH_F2_OPT_LOCK_BIT (1u << 0) +#define FLASH_F2_CR_STRT 16 +#define FLASH_F2_CR_LOCK 31 + +#define FLASH_F2_CR_SER 1 +#define FLASH_F2_CR_SNB 3 +#define FLASH_F2_CR_SNB_MASK 0x78 +#define FLASH_F2_SR_BSY 16 + + #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 @@ -2642,6 +2659,56 @@ static int stlink_write_option_bytes_l0_cat2(stlink_t *sl, uint8_t* base, uint32 return 0; } +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f2(stlink_t *sl, uint32_t option_byte) { + uint32_t val; + + stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); + if (val & FLASH_F2_OPT_LOCK_BIT) { + WLOG("Unlocking option flash\n"); + //Unlock the FLASH_OPT_CR register (FLASH Programming manual page 15) + //https://www.st.com/resource/en/programming_manual/cd00233952.pdf + stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, 0x08192A3B); + stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, 0x4C5D6E7F); + + stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); + if (val & FLASH_F2_OPT_LOCK_BIT) { + ELOG("Option flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; + } + } + + stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); + WLOG("option bytes CR = %x\n",val); + + stlink_write_debug32(sl, FLASH_F2_OPT_CR, option_byte & 0x0FFFFFFC); + + stlink_write_debug32(sl, FLASH_F2_OPT_CR, (option_byte & 0x0FFFFFFC)|0x00000002); + + + stlink_read_debug32(sl, FLASH_F2_SR, &val); + WLOG("wait BSY flag to be 0\n"); + + while(val & 0x00010000){ + stlink_read_debug32(sl, FLASH_F2_SR, &val); + } + WLOG("BSY flag is 0\n"); + + stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); + WLOG("option bytes CR = %x\n",val); + WLOG("Option flash re-lock\n"); + stlink_write_debug32(sl, FLASH_F2_OPT_CR, val | 0x00000001); + + DLOG("STM32 F2 option bytes are written\n"); + + return 0; +} + /** * Write option bytes * @param sl @@ -2662,7 +2729,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui return stlink_write_option_bytes_l0_cat2(sl, base, len); } else { - ELOG("Option bytes writing is currently only supported for the STM32G0 and STM32L0\n"); + ELOG("Option bytes writing is currently only supported for the STM32F2, STM32G0 and STM32L0\n"); return -1; } @@ -2690,3 +2757,21 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr unmap_file(&mf); return err; } + +/** + * Write the given 32-bit value with option byte + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_fwrite_option_bytes_32bit(stlink_t *sl, uint32_t val) { + + if(sl->chip_id == STLINK_CHIPID_STM32_F2){ + return stlink_write_option_bytes_f2(sl, val); + } + else + { + ELOG("Option bytes writing is currently only supported for the STM32F2, STM32G0 and STM32L0\n"); + return -1; + } +} diff --git a/src/tools/flash.c b/src/tools/flash.c index 1a02b4fb4..91fa1c6d6 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -38,6 +38,7 @@ static void usage(void) puts(" fsize: Use decimal, octal or hex by prefix 0xXXX for hex, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); puts(" Format may be 'binary' (default) or 'ihex', although must be specified for binary format only."); puts(" ./st-flash [--version]"); + puts("example write option byte: ./st-flash --debug --reset --area=option write 0xXXXXXXXX"); } int main(int ac, char** av) @@ -131,7 +132,6 @@ int main(int ac, char** av) if (o.cmd == FLASH_CMD_WRITE) /* write */ { size_t size = 0; - if(o.format == FLASH_FORMAT_IHEX) { err = stlink_parse_ihex(o.filename, stlink_get_erased_pattern(sl), &mem, &size, &o.addr); if (err == -1) { @@ -139,7 +139,6 @@ int main(int ac, char** av) goto on_error; } } - if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { if(o.format == FLASH_FORMAT_IHEX) @@ -164,7 +163,7 @@ int main(int ac, char** av) goto on_error; } } - else if (o.addr == STM32_G0_OPTION_BYTES_BASE || o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE) { + else if (o.addr == STM32_G0_OPTION_BYTES_BASE || o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE){ err = stlink_fwrite_option_bytes(sl, o.filename, o.addr); if (err == -1) { @@ -172,6 +171,14 @@ int main(int ac, char** av) goto on_error; } } + else if (o.area == FLASH_OPTION_BYTES){ + err = stlink_fwrite_option_bytes_32bit(sl, o.val); + if (err == -1) + { + printf("stlink_fwrite_option_bytes() == -1\n"); + goto on_error; + } + } else { err = -1; printf("Unknown memory region\n"); diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index 4fa39de4c..ab066de0a 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -58,6 +58,29 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) serial_specified = true; } + else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { + const char * area; + if(strcmp(av[0], "--area") == 0) { + ac--; + av++; + if (ac < 1) return -1; + area = av[0]; + } + else { + area = av[0] + strlen("--area="); + } + if (strcmp(area, "main") == 0) + o->area = FLASH_MAIN_MEMORY; + else if (strcmp(area, "system") == 0) + o->area = FLASH_SYSTEM_MEMORY; + else if (strcmp(area, "otp") == 0) + o->area = FLASH_OTP; + else if (strcmp(area, "option") == 0) + o->area = FLASH_OPTION_BYTES; + else + return -1; + + } else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { const char * format; if(strcmp(av[0], "--format") == 0) { @@ -161,7 +184,12 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) break; case FLASH_CMD_WRITE: - if(o->format == FLASH_FORMAT_BINARY) { // expect filename and addr + if(o->area == FLASH_OPTION_BYTES){ + if(ac != 1) return -1; + + o->val = (uint32_t)strtoul(av[0], &tail, 16); + } + else if(o->format == FLASH_FORMAT_BINARY) { // expect filename and addr if (ac != 2) return -1; o->filename = av[0]; From 94aef4557071a3f6b8bf91cd3196db8527fb9f3b Mon Sep 17 00:00:00 2001 From: Orie22 Date: Mon, 7 Oct 2019 18:50:59 +0900 Subject: [PATCH 0679/1435] Add read Option-bytes command for STM32F2 series --- include/stlink.h | 1 + src/common.c | 33 +++++++++++++++++++++++++++++++++ src/tools/flash.c | 21 +++++++++++++++++---- src/tools/flash_opts.c | 1 + 4 files changed, 52 insertions(+), 4 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index 50f86c11b..0715166e5 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -222,6 +222,7 @@ typedef struct flash_loader { int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); int stlink_load_device_params(stlink_t *sl); + int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte); #include "stlink/sg.h" #include "stlink/usb.h" diff --git a/src/common.c b/src/common.c index bf1aba64c..207be3d8a 100644 --- a/src/common.c +++ b/src/common.c @@ -2709,6 +2709,39 @@ static int stlink_write_option_bytes_f2(stlink_t *sl, uint32_t option_byte) { return 0; } +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { + uint32_t val; + + stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); + if (val & FLASH_F2_OPT_LOCK_BIT) { + WLOG("Unlocking option flash\n"); + //Unlock the FLASH_OPT_CR register (FLASH Programming manual page 15) + //https://www.st.com/resource/en/programming_manual/cd00233952.pdf + stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, 0x08192A3B); + stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, 0x4C5D6E7F); + + stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); + if (val & FLASH_F2_OPT_LOCK_BIT) { + ELOG("Option flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; + } + } + + stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); + WLOG("option bytes CR = %x\n",option_byte); + + WLOG("Option flash re-lock\n"); + stlink_write_debug32(sl, FLASH_F2_OPT_CR, val | 0x00000001); + + return 0; +} + /** * Write option bytes * @param sl diff --git a/src/tools/flash.c b/src/tools/flash.c index 91fa1c6d6..8bdddc566 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -39,6 +39,7 @@ static void usage(void) puts(" Format may be 'binary' (default) or 'ihex', although must be specified for binary format only."); puts(" ./st-flash [--version]"); puts("example write option byte: ./st-flash --debug --reset --area=option write 0xXXXXXXXX"); + puts("example read option byte: ./st-flash --debug --reset --area=option read > option_byte"); } int main(int ac, char** av) @@ -208,13 +209,25 @@ int main(int ac, char** av) } else /* read */ { - if ((o.addr >= sl->flash_base) && (o.size == 0) && - (o.addr < sl->flash_base + sl->flash_size)) + if(o.area == FLASH_OPTION_BYTES){ + if(sl->chip_id == STLINK_CHIPID_STM32_F2){ + uint32_t option_byte = 0; + err = stlink_read_option_bytes_f2(sl,&option_byte); + printf("%x\n",option_byte); + }else{ + printf("This format is available for STM32F2 Only\n"); + } + } + else if ((o.addr >= sl->flash_base) && (o.size == 0) && + (o.addr < sl->flash_base + sl->flash_size)){ o.size = sl->flash_size; + err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); + } else if ((o.addr >= sl->sram_base) && (o.size == 0) && - (o.addr < sl->sram_base + sl->sram_size)) + (o.addr < sl->sram_base + sl->sram_size)){ o.size = sl->sram_size; - err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); + err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); + } if (err == -1) { printf("stlink_fread() == -1\n"); diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index ab066de0a..3f74ac057 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -172,6 +172,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) break; case FLASH_CMD_READ: // expect filename, addr and size + if((o->area == FLASH_OPTION_BYTES) &&(ac == 0)) break; if (ac != 3) return -1; o->filename = av[0]; From 4a32157143547755cab260e58d1b00f8ddaa7780 Mon Sep 17 00:00:00 2001 From: Orie22 Date: Wed, 9 Oct 2019 11:25:53 +0900 Subject: [PATCH 0680/1435] bug fix: normal read operation was not executed --- src/tools/flash.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/tools/flash.c b/src/tools/flash.c index 8bdddc566..33e1c8dc0 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -217,15 +217,15 @@ int main(int ac, char** av) }else{ printf("This format is available for STM32F2 Only\n"); } - } - else if ((o.addr >= sl->flash_base) && (o.size == 0) && - (o.addr < sl->flash_base + sl->flash_size)){ - o.size = sl->flash_size; - err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); - } - else if ((o.addr >= sl->sram_base) && (o.size == 0) && - (o.addr < sl->sram_base + sl->sram_size)){ - o.size = sl->sram_size; + }else{ + if ((o.addr >= sl->flash_base) && (o.size == 0) && + (o.addr < sl->flash_base + sl->flash_size)){ + o.size = sl->flash_size; + } + else if ((o.addr >= sl->sram_base) && (o.size == 0) && + (o.addr < sl->sram_base + sl->sram_size)){ + o.size = sl->sram_size; + } err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); } if (err == -1) From 9e44de25a8d24aae12a17b2205317c94fcded04f Mon Sep 17 00:00:00 2001 From: Brad Natelborg Date: Fri, 11 Oct 2019 13:08:34 -0400 Subject: [PATCH 0681/1435] Adding full support for STLINK CHIP ID L4RX --- src/common.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/common.c b/src/common.c index 207be3d8a..bfcbe715f 100644 --- a/src/common.c +++ b/src/common.c @@ -1659,7 +1659,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || (sl->chip_id == STLINK_CHIPID_STM32_L43X) || (sl->chip_id == STLINK_CHIPID_STM32_L46X) || - (sl->chip_id == STLINK_CHIPID_STM32_L496X)) { + (sl->chip_id == STLINK_CHIPID_STM32_L496X) || + (sl->chip_id == STLINK_CHIPID_STM32_L4RX)) { // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); @@ -1779,11 +1780,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) if (sl->flash_type == STLINK_FLASH_TYPE_WB) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - + // sec 3.10.5 - PNB[7:0] is offset by 3. val &= ~(0xFF << 3); // Clear previously set page number (if any) val |= ((flash_page & 0xFF) << 3); - + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); @@ -2086,7 +2087,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t if ((sl->chip_id != STLINK_CHIPID_STM32_L4) && (sl->chip_id != STLINK_CHIPID_STM32_L43X) && (sl->chip_id != STLINK_CHIPID_STM32_L46X) && - (sl->chip_id != STLINK_CHIPID_STM32_L496X)) { + (sl->chip_id != STLINK_CHIPID_STM32_L496X) && + (sl->chip_id != STLINK_CHIPID_STM32_L4RX)) { if( sl->version.stlink_v == 1 ) { printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes on F4 devices\n"); From 0948cd19b27b0f66e12145dbf1c911f50c31d039 Mon Sep 17 00:00:00 2001 From: Davey Struijk Date: Fri, 25 Oct 2019 14:32:36 +0200 Subject: [PATCH 0682/1435] Allow writing option bytes to STM32F4 devices --- include/stlink.h | 1 + src/common.c | 88 ++++++++++++++++++++++++++++++++++++++++++++++- src/tools/flash.c | 6 +++- 3 files changed, 93 insertions(+), 2 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index 0715166e5..5defe4e98 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -223,6 +223,7 @@ typedef struct flash_loader { int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); int stlink_load_device_params(stlink_t *sl); int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte); + int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte); #include "stlink/sg.h" #include "stlink/usb.h" diff --git a/src/common.c b/src/common.c index bfcbe715f..99bd7a842 100644 --- a/src/common.c +++ b/src/common.c @@ -187,6 +187,7 @@ #define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) #define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) #define FLASH_F4_OPT_CR (FLASH_F4_REGS_ADDR + 0x14) +#define FLASH_F4_OPT_LOCK_BIT (1u << 0) #define FLASH_F4_CR_STRT 16 #define FLASH_F4_CR_LOCK 31 #define FLASH_F4_CR_SER 1 @@ -2711,6 +2712,56 @@ static int stlink_write_option_bytes_f2(stlink_t *sl, uint32_t option_byte) { return 0; } +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f4(stlink_t *sl, uint32_t option_byte) { + uint32_t val; + + stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); + if (val & FLASH_F4_OPT_LOCK_BIT) { + WLOG("Unlocking option flash\n"); + //Unlock the FLASH_OPT_CR register (FLASH Programming manual page 15) + //https://www.st.com/resource/en/programming_manual/cd00233952.pdf + stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, 0x08192A3B); + stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, 0x4C5D6E7F); + + stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); + if (val & FLASH_F4_OPT_LOCK_BIT) { + ELOG("Option flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; + } + } + + stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); + WLOG("option bytes CR = %x\n",val); + + stlink_write_debug32(sl, FLASH_F4_OPT_CR, option_byte & 0x0FFFFFFC); + + stlink_write_debug32(sl, FLASH_F4_OPT_CR, (option_byte & 0x0FFFFFFC)|0x00000002); + + + stlink_read_debug32(sl, FLASH_F4_SR, &val); + WLOG("wait BSY flag to be 0\n"); + + while(val & 0x00010000){ + stlink_read_debug32(sl, FLASH_F4_SR, &val); + } + WLOG("BSY flag is 0\n"); + + stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); + WLOG("option bytes CR = %x\n",val); + WLOG("Option flash re-lock\n"); + stlink_write_debug32(sl, FLASH_F4_OPT_CR, val | 0x00000001); + + DLOG("STM32 F4 option bytes are written\n"); + + return 0; +} + /** * Read option bytes * @param sl @@ -2744,6 +2795,39 @@ int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { return 0; } +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { + uint32_t val; + + stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); + if (val & FLASH_F4_OPT_LOCK_BIT) { + WLOG("Unlocking option flash\n"); + //Unlock the FLASH_OPT_CR register (FLASH Programming manual page 15) + //https://www.st.com/resource/en/programming_manual/cd00233952.pdf + stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, 0x08192A3B); + stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, 0x4C5D6E7F); + + stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); + if (val & FLASH_F4_OPT_LOCK_BIT) { + ELOG("Option flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; + } + } + + stlink_read_debug32(sl, FLASH_F4_OPT_CR, option_byte); + WLOG("option bytes CR = %x\n",option_byte); + + WLOG("Option flash re-lock\n"); + stlink_write_debug32(sl, FLASH_F4_OPT_CR, val | 0x00000001); + + return 0; +} + /** * Write option bytes * @param sl @@ -2803,10 +2887,12 @@ int stlink_fwrite_option_bytes_32bit(stlink_t *sl, uint32_t val) { if(sl->chip_id == STLINK_CHIPID_STM32_F2){ return stlink_write_option_bytes_f2(sl, val); + }else if(sl->chip_id == STLINK_CHIPID_STM32_F446){ + return stlink_write_option_bytes_f4(sl, val); } else { - ELOG("Option bytes writing is currently only supported for the STM32F2, STM32G0 and STM32L0\n"); + ELOG("Option bytes writing is currently only supported for the STM32F2, STM32F4, STM32G0 and STM32L0\n"); return -1; } } diff --git a/src/tools/flash.c b/src/tools/flash.c index 33e1c8dc0..f5fd1a386 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -214,8 +214,12 @@ int main(int ac, char** av) uint32_t option_byte = 0; err = stlink_read_option_bytes_f2(sl,&option_byte); printf("%x\n",option_byte); + }else if(sl->chip_id == STLINK_CHIPID_STM32_F446){ + uint32_t option_byte = 0; + err = stlink_read_option_bytes_f4(sl,&option_byte); + printf("%x\n",option_byte); }else{ - printf("This format is available for STM32F2 Only\n"); + printf("This format is available for STM32F2 and STM32F4 Only\n"); } }else{ if ((o.addr >= sl->flash_base) && (o.size == 0) && From 302dc872f4b73f13a94ff2e9f0359c4195f6279c Mon Sep 17 00:00:00 2001 From: zx81a Date: Tue, 5 Nov 2019 10:24:22 +0100 Subject: [PATCH 0683/1435] Support for STM31L4, SM32L1 option bytes write. --- debian/rules | 2 +- include/stm32.h | 3 + src/common.c | 191 +++++++++++++++++++++++++++++++++++++++++++++- src/tools/flash.c | 2 +- 4 files changed, 194 insertions(+), 4 deletions(-) diff --git a/debian/rules b/debian/rules index e228a7087..e183fffb7 100755 --- a/debian/rules +++ b/debian/rules @@ -1,7 +1,7 @@ #!/usr/bin/make -f # See debhelper(7) (uncomment to enable) # output every command that modifies files on the build system. -#DH_VERBOSE = 1 +DH_VERBOSE = 1 # see EXAMPLES in dpkg-buildflags(1) and read /usr/share/dpkg/* DPKG_EXPORT_BUILDFLAGS = 1 diff --git a/include/stm32.h b/include/stm32.h index 8f8e7eba1..9a01baaf4 100644 --- a/include/stm32.h +++ b/include/stm32.h @@ -17,4 +17,7 @@ #define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L0_CAT2_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) #define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) +#define STM32_L496X_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) +#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) + #endif /* STM32_H */ diff --git a/src/common.c b/src/common.c index 99bd7a842..4d976f49f 100644 --- a/src/common.c +++ b/src/common.c @@ -137,6 +137,7 @@ //32L4 register base is at FLASH_REGS_ADDR (0x40022000) #define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) +#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) #define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) #define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) #define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) @@ -145,13 +146,16 @@ #define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */ #define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ #define STM32L4_FLASH_CR_PG 0 /* Program */ #define STM32L4_FLASH_CR_PER 1 /* Page erase */ #define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ #define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ #define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ #define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ #define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ // Bits requesting flash operations (useful when we want to clear them) #define STM32L4_FLASH_CR_OPBITS \ ((1lu<chip_id,addr); + /* Check if chip is supported and for correct address */ if((sl->chip_id == STLINK_CHIPID_STM32_G0X1) && (addr == STM32_G0_OPTION_BYTES_BASE)) { return stlink_write_option_bytes_g0x1(sl, base, len); @@ -2847,8 +3027,15 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui else if((sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) && (addr == STM32_L0_CAT2_OPTION_BYTES_BASE)) { return stlink_write_option_bytes_l0_cat2(sl, base, len); } + else if((sl->chip_id == STLINK_CHIPID_STM32_L496X) && (addr == STM32_L496X_OPTION_BYTES_BASE)) { + return stlink_write_option_bytes_l496x(sl, base, len); + } + else if( ( (sl->chip_id == STLINK_CHIPID_STM32_L152_RE) || (sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH) ) + && ( (addr == STM32_L1_OPTION_BYTES_BASE) || (addr == STM32_L1_OPTION_BYTES_BASE+4) ) ) { + return stlink_write_option_bytes_l1(sl, base, addr, len); + } else { - ELOG("Option bytes writing is currently only supported for the STM32F2, STM32G0 and STM32L0\n"); + ELOG("Option bytes writing is currently only supported for the STM32F2, STM32G0, STM32L496x/L4A6x, STM32L1 and STM32L0\n"); return -1; } diff --git a/src/tools/flash.c b/src/tools/flash.c index f5fd1a386..1b63b1696 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -164,7 +164,7 @@ int main(int ac, char** av) goto on_error; } } - else if (o.addr == STM32_G0_OPTION_BYTES_BASE || o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE){ + else if (o.addr == STM32_G0_OPTION_BYTES_BASE || o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE || o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE + 4){ err = stlink_fwrite_option_bytes(sl, o.filename, o.addr); if (err == -1) { From 8f6314078b6fe3221008518888474aa008cfda3d Mon Sep 17 00:00:00 2001 From: Mark Odell Date: Mon, 23 Dec 2019 14:25:37 -0500 Subject: [PATCH 0684/1435] Improved support for STM32G0xx series parts - Now properly distinguish between the smaller and larger variants - Added support for the smaller variants, 'G030, 'G031, and 'G041 - Now flashes and debugs STM32G031K8 MCU --- include/stlink/chipid.h | 3 ++- src/chipid.c | 17 ++++++++++++++--- src/common.c | 4 ++-- 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index a4f4be4c0..ae665efd3 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -71,7 +71,8 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F410 = 0x458, STLINK_CHIPID_STM32_F413 = 0x463, STLINK_CHIPID_STM32_L4RX = 0x470, // taken from the STM32L4R9I-DISCO board - STLINK_CHIPID_STM32_G0X1 = 0x460, + STLINK_CHIPID_STM32_G07X = 0x460, // Actually, 'G070 and 'G071/081 + STLINK_CHIPID_STM32_G03X = 0x466, // Actually, 'G030 and 'G031/041 STLINK_CHIPID_STM32_WB55 = 0x495 }; diff --git a/src/chipid.c b/src/chipid.c index d627849a3..2fd860223 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -522,9 +522,9 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x2000 }, { - // STM32G071/081 (from RM0444) - .chip_id = STLINK_CHIPID_STM32_G0X1, - .description = "G071/G081 device", + // STM32G071/081 (from RM0454 & RM0444) + .chip_id = STLINK_CHIPID_STM32_G07X, + .description = "G070/G071/G081 device", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2K (sec 3.2) @@ -532,6 +532,17 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800 // 30K (table 2) }, + { + // STM32G031/041 (from RM0454 & RM0444) + .chip_id = STLINK_CHIPID_STM32_G03X, + .description = "G030/G031/G041 device", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2K (sec 3.2) + .sram_size = 0x2000, // 8K (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x2000 // 8k (table 2) + }, { // STM32WB55 (from RM0434) .chip_id = STLINK_CHIPID_STM32_WB55, diff --git a/src/common.c b/src/common.c index 99bd7a842..ee65018ba 100644 --- a/src/common.c +++ b/src/common.c @@ -2535,7 +2535,7 @@ static int stlink_write_option_bytes_g0x1(stlink_t *sl, uint8_t* base, uint32_t uint32_t val; if(len != 4) { - ELOG("Wrong length for writting option bytes, must be 4 is %d\n", len); + ELOG("Wrong length for writing option bytes, must be 4 is %d\n", len); return -1; } @@ -2841,7 +2841,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui stlink_core_id(sl); /* Check if chip is supported and for correct address */ - if((sl->chip_id == STLINK_CHIPID_STM32_G0X1) && (addr == STM32_G0_OPTION_BYTES_BASE)) { + if (((sl->chip_id == STLINK_CHIPID_STM32_G07X) || (sl->chip_id == STLINK_CHIPID_STM32_G03X)) && (addr == STM32_G0_OPTION_BYTES_BASE)) { return stlink_write_option_bytes_g0x1(sl, base, len); } else if((sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) && (addr == STM32_L0_CAT2_OPTION_BYTES_BASE)) { From f070345249800a5436dbfdd9f29fbca8f00744f7 Mon Sep 17 00:00:00 2001 From: kraus Date: Sat, 4 Jan 2020 15:05:22 +0100 Subject: [PATCH 0685/1435] added several comments on the stlink software structure --- doc/developer.txt | 398 ++++++++++++++++++++++++++++++++++++++++++++++ include/stlink.h | 24 +-- src/common.c | 7 +- 3 files changed, 417 insertions(+), 12 deletions(-) create mode 100644 doc/developer.txt diff --git a/doc/developer.txt b/doc/developer.txt new file mode 100644 index 000000000..2d05b9312 --- /dev/null +++ b/doc/developer.txt @@ -0,0 +1,398 @@ + +=== Target Identification === + +The following information is available about the target: +- chip id: 0xE0042000 or 0x40015800, primary information to derive flash and sram architection +- core id: Result from the STLINK_DEBUGREADCOREID call, additionally used for flash/sram architection +- cpu id: 0xE000ED00 (CMSIS System Control Block CPU ID), not used in stlink + + +=== Backend === + +The "backend" implements the interface to the adapter hardware. +There are two backends for two different adapters: "sg" (stlink v1?) and "usb" (stlink v2?). + + + +Include stlink/backend.h + typedef struct _stlink_backend { + void (*close) (stlink_t * sl); + int (*exit_debug_mode) (stlink_t * sl); + int (*enter_swd_mode) (stlink_t * sl); + int (*enter_jtag_mode) (stlink_t * stl); + int (*exit_dfu_mode) (stlink_t * stl); + int (*core_id) (stlink_t * stl); + int (*reset) (stlink_t * stl); + int (*jtag_reset) (stlink_t * stl, int value); + int (*run) (stlink_t * stl); + int (*status) (stlink_t * stl); + int (*version) (stlink_t *sl); + int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); + int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); + int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); + int (*read_all_regs) (stlink_t *sl, struct stlink_reg * regp); + int (*read_reg) (stlink_t *sl, int r_idx, struct stlink_reg * regp); + int (*read_all_unsupported_regs) (stlink_t *sl, struct stlink_reg *regp); + int (*read_unsupported_reg) (stlink_t *sl, int r_idx, struct stlink_reg *regp); + int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, struct stlink_reg *regp); + int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); + int (*step) (stlink_t * stl); + int (*current_mode) (stlink_t * stl); + int (*force_debug) (stlink_t *sl); + int32_t (*target_voltage) (stlink_t *sl); + int (*set_swdclk) (stlink_t * stl, uint16_t divisor); + } stlink_backend_t; + +Descriptions below describe the actions of the usb.h backend: + +void (*close) (stlink_t * sl); +int (*exit_debug_mode) (stlink_t * sl); + __stlink_usb_exit_debug_mode: Send STLINK_DEBUG_EXIT + returns -1 or 0 + +int (*enter_swd_mode) (stlink_t * sl); + _stlink_usb_enter_swd_mode: Send STLINK_DEBUG_ENTER+STLINK_DEBUG_ENTER_SWD + returns -1 or 0 + +int (*enter_jtag_mode) (stlink_t * stl); + +int (*exit_dfu_mode) (stlink_t * stl); + _stlink_usb_exit_dfu_mode: Send STLINK_DFU_EXIT + returns -1 or 0 + +int (*core_id) (stlink_t * stl); + _stlink_usb_core_id: Assign the result from STLINK_DEBUG_READCOREID to stl->core_id + returns -1 or 0 + +int (*reset) (stlink_t * stl); + _stlink_usb_reset: Send STLINK_DEBUG_RESETSYS and reset via AIRCR + AIRCR is part of the CMSIS System Control Block (SCB), which is located in + the System Control Space at 0xE000ED0C + returns -1 or 0 ? + +int (*jtag_reset) (stlink_t * stl, int value); + _stlink_usb_jtag_reset: Send STLINK_JTAG_DRIVE_NRST. + "value" is sent as argument for STLINK_JTAG_DRIVE_NRST and probably contains + the status of the NRST line (0: low, 1: high). Also the value 2 is used in the software. + returns -1 or 0 + +int (*run) (stlink_t * stl); + _stlink_usb_run: Send STLINK_DEBUG_RUNCORE + returns -1 or 0 + +int (*status) (stlink_t * stl); + _stlink_usb_status: Assign the result from STLINK_DEBUG_GETSTATUS to stl->q_len + returns -1 or 0 + +int (*version) (stlink_t *sl); + _stlink_usb_version: Read version with STLINK_GET_VERSION. + Result is stored in sl->q_buf (6 bytes????) + returns -1 or 0 + +int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); + _stlink_usb_read_debug32: Send STLINK_JTAG_READDEBUG_32BIT + to read 32 bits from "addr". The result data is stored at "*data". + returns -1 or 0 + +int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + _stlink_usb_read_mem32: Use STLINK_DEBUG_READMEM_32BIT + to read "len" bytes from "addr" + Result is returned in sl->q_buf, sl->q_len returns the size of the data (should be + equal to "len"???). + returns -1 or 0 + +int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); + _stlink_usb_write_debug32: Use STLINK_JTAG_WRITEDEBUG_32BIT + to store "data" at "addr" + returns -1 or 0 + +int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + _stlink_usb_write_mem32: Use STLINK_DEBUG_WRITEMEM_32BIT to + send data stored in sl->q_buf to the target at "addr". + "len" is the size data (???? not clear whether this are bytes ) + returns -1 or 0 + +int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); + _stlink_usb_write_mem8: Use STLINK_DEBUG_WRITEMEM_8BIT to + send data stored in sl->q_buf to the target at "addr". + "len" is the size in bytes (probably). + returns -1 or 0 + +int (*read_all_regs) (stlink_t *sl, struct stlink_reg * regp); + _stlink_usb_read_all_regs: Send STLINK_DEBUG_READALLREGS to read + all register values and store them into *regp; + returns -1 or 0 + +int (*read_reg) (stlink_t *sl, int r_idx, struct stlink_reg * regp); + _stlink_usb_read_reg: Send STLINK_DEBUG_READREG to read specific register "r_idx". + The result is then stored in *regp in the correct register. + Example if "r_idx" is 18, then the result is stored in regp->process_sp + returns -1 or 0 + +int (*read_all_unsupported_regs) (stlink_t *sl, struct stlink_reg *regp); + _stlink_usb_read_all_unsupported_regs: Calls "_stlink_usb_read_unsupported_reg" + (see below) to read all registers. + returns -1 or 0 + +int (*read_unsupported_reg) (stlink_t *sl, int r_idx, struct stlink_reg *regp); + _stlink_usb_read_unsupported_reg Use DCRSR and DCRDR to access some + of the internal registers (primask, basepri, faultmask, control, fpscr). + Also will fill regp->s (???) for some specific "r_idx" values. + WARNING: Some r_idx values may lead to a out of array bound problem in C. + returns -1 or 0 + +int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, struct stlink_reg *regp); + _stlink_usb_write_unsupported_reg: + Updates one of the following registers: + primask (idx=0x1c), basepri (idx=0x1d), faultmask (idx=0x1e), control (idx=0x1f) + The new value is given as "value" as fn argument. + Corresponding values are refreshed in regp, however the old value for is kept in regp: + If basepri has to be updated (idx=0x1d), then all register values are fetched and + basepri is updated in the core, but not in *regp (BUG???). + returns -1 or 0 + +int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); + _stlink_usb_write_reg: Use STLINK_DEBUG_WRITEREG to update register "idx" + with value "reg". + returns -1 or 0 + +int (*step) (stlink_t * stl); + _stlink_usb_step: Send STLINK_DEBUG_STEPCORE + returns -1 or 0 + +int (*current_mode) (stlink_t * stl); + _stlink_usb_current_mode: Send STLINK_GET_CURRENT_MODE and return + the current mode. + returns -1 or the value for the current mode. + Modes probably are: + STLINK_DEV_DFU_MODE 0x00 + STLINK_DEV_MASS_MODE 0x01 + STLINK_DEV_DEBUG_MODE 0x02 + +int (*force_debug) (stlink_t *sl); + _stlink_usb_force_debug: Sends STLINK_DEBUG_FORCEDEBUG. No other side effects + returns -1 or 0 + +int32_t (*target_voltage) (stlink_t *sl); + _stlink_usb_target_voltage: Send STLINK_GET_TARGET_VOLTAGE + returns -1 or the target voltage. (??? dimension is not clear...) + +int (*set_swdclk) (stlink_t * stl, uint16_t divisor); + _stlink_usb_set_swdclk: Send STLINK_DEBUG_APIV2_SWD_SET_FREQ and "divisor" value + returns -1 or 0 + + +=== Other Functions === + + +Include: stlink.h + + +Prototype: void stlink_close(stlink_t *sl); +Include: inc/stlink.h +Definition: src/common.c +Description: + Calls the backend "close" procedure and frees 'sl' +Backend: "close" +Arguments: + sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() +Return: - + +Include: inc/stlink.h +Prototype: int stlink_core_id(stlink_t *sl); +Definition: src/common.c +Description: + Calls the backend "core_id", calls stlink_print_data() on higher verbose levels. + Assigns the core id returned by STLINK_DEBUGREADCOREID to sl->core_id + Only some specific core ids are used: See include/stm32.h + Usage includes the selection of the correct flash algorithm. +Backend: "core_id" +Arguments: + sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() +Return: -1 for error. 0 for success. + +Include: inc/stlink.h +Prototype: int stlink_reset(stlink_t *sl); +Definition: src/common.c +Description: + Just calls the backend "reset" procedure (reset via STLINK_DEBUG_RESETSYS + and reset via AIRCR register at 0xE000ED0C) +Backend: "reset" +Arguments: + sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() +Return: -1 for error. 0 for success. + +Include: inc/stlink.h +Prototype: int stlink_jtag_reset(stlink_t *sl, int value); +Definition: src/common.c +Description: + Just calls the backend "jtag_reset" procedure +Backend: "jtag_reset" +Arguments: + sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() + value: 0: drive low, 1: drive high, 2: ???? +Return: -1 for error. 0 for success. + + +Include: inc/stlink.h +Prototype: int stlink_run(stlink_t *sl); +Definition: src/common.c +Description: + Just calls the backend "run" procedure. +Backend: "run" +Arguments: + sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() +Return: -1 for error. 0 for success. + +Include: inc/stlink.h +Prototype: int stlink_status(stlink_t *sl); +Definition: src/common.c +Description: + Calls the backend "status" procedure and the procedure "stlink_core_stat()" to + store the status in "sl->core_stat". Possible value for "sl->core_stat" are: + STLINK_CORE_RUNNING + STLINK_CORE_HALTED + STLINK_CORE_STAT_UNKNOWN +Backend: "status" +Arguments: + sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() +Return: -1 for error. 0 for success. + + +Include: inc/stlink.h +Prototype: int stlink_version(stlink_t *sl); +Definition: src/common.c +Description: + Calls the backend "version" procedure, parses the result and puts the result into sl->version + This version probably refers to the version of the adapter. +Backend: "version" +Arguments: + sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() +Return: -1 for error. 0 for success. + + + int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); + int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); + int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); + int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); + int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); + int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); + int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); + int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); + int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); + int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, struct stlink_reg *regp); + int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); + int stlink_step(stlink_t *sl); + int stlink_current_mode(stlink_t *sl); + int stlink_force_debug(stlink_t *sl); + int stlink_target_voltage(stlink_t *sl); + int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); + + int stlink_erase_flash_mass(stlink_t* sl); + int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); + int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); + uint8_t stlink_get_erased_pattern(stlink_t *sl); + int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); + int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); + int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); + int stlink_fwrite_option_bytes_32bit(stlink_t *sl,uint32_t val); + int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); + int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); + int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); + +Include: inc/stlink.h +Prototype: int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); +Definition: src/common.c +Description: + Tries to read out the chip id via memory read from the device. + Note: sl->chip_id is NOT updated by this procedure. Instead this happens in stlink_load_device_params(): + Do not call this function, but instead call stlink_load_device_params() +Backend: - +Arguments: + sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() + chip_id: Pointer. Result is stored via this pointer. +Return: -1 for error. 0 for success. + + +Include: inc/stlink.h +Prototype: int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); +Definition: src/common.c +Description: + Reads the CPU id from STLINK_REG_CM3_CPUID (0xE000ED00, first value of + the SCB, system control block) and splits this into + cpuid->implementer_id + cpuid->variant + cpuid->part + cpuid->revision + The result is not used in the tools, but only in the usb test program. +Backend: - +Arguments: + sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() + cpuid: Pointer. Result is stored via this pointer. +Return: -1 for error. 0 for success. + + + + + int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); + uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); + uint16_t read_uint16(const unsigned char *c, const int pt); + void stlink_core_stat(stlink_t *sl); + + +Include: inc/stlink.h +Prototype: void stlink_print_data(stlink_t *sl); +Definition: src/common.c +Description: + If debug logging is enabled: Print the HEX content of the q_buf array. + q_buf will contain the result of the last "backend" command. +Backend: - +Arguments: + sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() +Return: - + + + unsigned int is_bigendian(void); + uint32_t read_uint32(const unsigned char *c, const int pt); + void write_uint32(unsigned char* buf, uint32_t ui); + void write_uint16(unsigned char* buf, uint16_t ui); + bool stlink_is_core_halted(stlink_t *sl); + int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); + int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); + int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); + + +Include: inc/stlink.h +Prototype: int stlink_load_device_params(stlink_t *sl); +Definition: src/common.c +Description: + This is one of the most important procedures. It will get all the device info + and store the results in the "sl" structure. Many other procedures will depend + on this information. + The identification is based on the stlink_chip_id() result and the flash_size register value +Backend: - +Arguments: + sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() +Return: -1 for error. 0 for success. + + int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte); + int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte); + + +Include "flash_loader.h" + +int stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); +int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); +int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); + + +Inlcude "sg.h" +stlink_t* stlink_v1_open(const int verbose, int reset); + +Include "usb.h" + +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[STLINK_SERIAL_MAX_SIZE]); +size_t stlink_probe_usb(stlink_t **stdevs[]); +void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); diff --git a/include/stlink.h b/include/stlink.h index 5defe4e98..d4170c7a7 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -142,25 +142,27 @@ typedef struct flash_loader { // transport layer verboseness: 0 for no debug info, 10 for lots int verbose; - uint32_t core_id; - uint32_t chip_id; - int core_stat; + uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID + uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram + int core_stat; // set by stlink_status(), values STLINK_CORE_xxxxx char serial[STLINK_SERIAL_MAX_SIZE]; int serial_size; - enum stlink_flash_type flash_type; - stm32_addr_t flash_base; - size_t flash_size; - size_t flash_pgsz; + enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx + stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() + size_t flash_size; // calculated by stlink_load_device_params() + size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() /* sram settings */ - stm32_addr_t sram_base; - size_t sram_size; + stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() + size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() // bootloader - stm32_addr_t sys_base; - size_t sys_size; + // sys_base and sys_size are not used by the tools, but are only there to + // download the bootloader code (see tests/sg.c) + stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() + size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() struct stlink_version_ version; }; diff --git a/src/common.c b/src/common.c index 99bd7a842..9a3098114 100644 --- a/src/common.c +++ b/src/common.c @@ -748,6 +748,8 @@ int stlink_core_id(stlink_t *sl) { return ret; } +// stlink_chip_id() is called by stlink_load_device_params() +// do not call this procedure directly. int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { int ret; @@ -801,7 +803,7 @@ int stlink_load_device_params(stlink_t *sl) { sl->chip_id = 0x413; } - params = stlink_chipid_get_params(sl->chip_id); + params = stlink_chipid_get_params(sl->chip_id); // chipid.c if (params == NULL) { WLOG("unknown chip id! %#x\n", chip_id); return -1; @@ -1134,6 +1136,9 @@ void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { usleep(3000000); } + +// this function is called by stlink_status() +// do not call stlink_core_stat() directly, always use stlink_status() void stlink_core_stat(stlink_t *sl) { if (sl->q_len <= 0) return; From 2cad920e543bace68a3176532cf6c8da8cf207b7 Mon Sep 17 00:00:00 2001 From: piccaso Date: Tue, 7 Jan 2020 17:02:34 +0100 Subject: [PATCH 0686/1435] Fix dead link in README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index c7f24c847..b0cad5618 100644 --- a/README.md +++ b/README.md @@ -32,7 +32,7 @@ Mac OS X users can install from [homebrew](http://brewformulas.org/Stlink) or [d Debian Linux users can install it via the ```stlink-tool``` package [repository](https://packages.debian.org/buster/stlink-tools) -Ubuntu Linux users can install it via the ```stlink-tool``` package [repository](https://packages.ubuntu.com/cosmic/stlink-tools) +Ubuntu Linux users can install it via the ```stlink-tool``` package [repository](https://packages.ubuntu.com/stlink-tools) Arch Linux users can install from the [repository](https://www.archlinux.org/packages/community/x86_64/stlink) From 1ec9173a902dd87a300e28dbc29931574f1d5476 Mon Sep 17 00:00:00 2001 From: "Yuriy M. Kaminskiy" Date: Wed, 29 Jan 2020 15:57:39 +0300 Subject: [PATCH 0687/1435] Fix st-flash manpage read example Size must be specified as hexdecimal number (as per both documentation and implementation) --- doc/man/st-flash.1 | 2 +- doc/man/st-flash.md | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/man/st-flash.1 b/doc/man/st-flash.1 index 6bd206069..36df7daa8 100644 --- a/doc/man/st-flash.1 +++ b/doc/man/st-flash.1 @@ -65,7 +65,7 @@ Read firmware from device (4096 bytes) .IP .nf \f[C] -$ st\-flash read firmware.bin 0x8000000 4096 +$ st\-flash read firmware.bin 0x8000000 0x1000 \f[R] .fi .PP diff --git a/doc/man/st-flash.md b/doc/man/st-flash.md index ae6c88f46..1860a8c72 100644 --- a/doc/man/st-flash.md +++ b/doc/man/st-flash.md @@ -61,7 +61,7 @@ Flash `firmware.bin` to device Read firmware from device (4096 bytes) - $ st-flash read firmware.bin 0x8000000 4096 + $ st-flash read firmware.bin 0x8000000 0x1000 Erase firmware from device From 2d8d4dce5ecb426c215839088990b34af7470641 Mon Sep 17 00:00:00 2001 From: Pierre Ducroquet Date: Fri, 14 Feb 2020 19:51:39 +0100 Subject: [PATCH 0688/1435] Fix installation by also including the stm32.h file --- include/CMakeLists.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/CMakeLists.txt b/include/CMakeLists.txt index a0c649532..a5121aee5 100644 --- a/include/CMakeLists.txt +++ b/include/CMakeLists.txt @@ -9,6 +9,9 @@ file(GLOB STLINK_HEADERS install(FILES ${CMAKE_SOURCE_DIR}/include/stlink.h DESTINATION ${STLINK_INCLUDE_PATH} ) +install(FILES ${CMAKE_SOURCE_DIR}/include/stm32.h + DESTINATION ${STLINK_INCLUDE_PATH} +) install(FILES ${STLINK_HEADERS} DESTINATION ${STLINK_INCLUDE_PATH}/stlink ) From 0f293fd6e8b2ee5804ebc6afa272e63d36d7716c Mon Sep 17 00:00:00 2001 From: Pierre Ducroquet Date: Fri, 14 Feb 2020 19:55:06 +0100 Subject: [PATCH 0689/1435] Add support for the STLink-2.1 when flash with no mass storage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since STLink 2.33.25, it is possible to flash the STLink in two modes: - STM32 Debug + VCP - STM32 Debug + Mass storage + VCP When flashed in the first mode, the device id changes, but the behaviour remains the same. This commit thus introduces support for this new device id. --- include/stlink/usb.h | 1 + src/usb.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/stlink/usb.h b/include/stlink/usb.h index 621695ea4..fd32a0731 100644 --- a/include/stlink/usb.h +++ b/include/stlink/usb.h @@ -23,6 +23,7 @@ extern "C" { #define STLINK_USB_PID_STLINK_32L 0x3748 #define STLINK_USB_PID_STLINK_32L_AUDIO 0x374a #define STLINK_USB_PID_STLINK_NUCLEO 0x374b +#define STLINK_USB_PID_STLINK_NO_UMS 0x3752 #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 diff --git a/src/usb.c b/src/usb.c index 7f5c21283..d3a541774 100644 --- a/src/usb.c +++ b/src/usb.c @@ -827,7 +827,10 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST } } - if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) || (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO) || (desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO)) { + if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) || + (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO) || + (desc.idProduct == STLINK_USB_PID_STLINK_NO_UMS) || + (desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO)) { struct libusb_device_handle *handle; ret = libusb_open(list[cnt], &handle); @@ -901,7 +904,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST // TODO - could use the scanning techniq from stm8 code here... slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; - if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO || desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO) { + if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO || desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO || desc.idProduct == STLINK_USB_PID_STLINK_NO_UMS) { slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; } else { slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; @@ -974,6 +977,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { if (desc.idProduct != STLINK_USB_PID_STLINK_32L && desc.idProduct != STLINK_USB_PID_STLINK_32L_AUDIO && + desc.idProduct != STLINK_USB_PID_STLINK_NO_UMS && desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO) continue; @@ -999,6 +1003,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { if (desc.idProduct != STLINK_USB_PID_STLINK_32L && desc.idProduct != STLINK_USB_PID_STLINK_32L_AUDIO && + desc.idProduct != STLINK_USB_PID_STLINK_NO_UMS && desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO) continue; From f45b8791f1f01457f436e11b5daf7b00f804ded2 Mon Sep 17 00:00:00 2001 From: Nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 19 Feb 2020 11:53:37 +0100 Subject: [PATCH 0690/1435] Update issue templates --- .github/ISSUE_TEMPLATE/bug_report.md | 38 +++++++++++++++++++++++ .github/ISSUE_TEMPLATE/feature_request.md | 20 ++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 .github/ISSUE_TEMPLATE/bug_report.md create mode 100644 .github/ISSUE_TEMPLATE/feature_request.md diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md new file mode 100644 index 000000000..dd84ea782 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/bug_report.md @@ -0,0 +1,38 @@ +--- +name: Bug report +about: Create a report to help us improve +title: '' +labels: '' +assignees: '' + +--- + +**Describe the bug** +A clear and concise description of what the bug is. + +**To Reproduce** +Steps to reproduce the behavior: +1. Go to '...' +2. Click on '....' +3. Scroll down to '....' +4. See error + +**Expected behavior** +A clear and concise description of what you expected to happen. + +**Screenshots** +If applicable, add screenshots to help explain your problem. + +**Desktop (please complete the following information):** + - OS: [e.g. iOS] + - Browser [e.g. chrome, safari] + - Version [e.g. 22] + +**Smartphone (please complete the following information):** + - Device: [e.g. iPhone6] + - OS: [e.g. iOS8.1] + - Browser [e.g. stock browser, safari] + - Version [e.g. 22] + +**Additional context** +Add any other context about the problem here. diff --git a/.github/ISSUE_TEMPLATE/feature_request.md b/.github/ISSUE_TEMPLATE/feature_request.md new file mode 100644 index 000000000..bbcbbe7d6 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/feature_request.md @@ -0,0 +1,20 @@ +--- +name: Feature request +about: Suggest an idea for this project +title: '' +labels: '' +assignees: '' + +--- + +**Is your feature request related to a problem? Please describe.** +A clear and concise description of what the problem is. Ex. I'm always frustrated when [...] + +**Describe the solution you'd like** +A clear and concise description of what you want to happen. + +**Describe alternatives you've considered** +A clear and concise description of any alternative solutions or features you've considered. + +**Additional context** +Add any other context or screenshots about the feature request here. From a0de0d0594b7755ae6d47dd7beaaffa45f8d8741 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 19 Feb 2020 18:33:30 +0100 Subject: [PATCH 0691/1435] Fixes #859. --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index b0cad5618..c57bdee91 100644 --- a/README.md +++ b/README.md @@ -8,7 +8,7 @@ Open source version of the STMicroelectronics Stlink Tools [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) [![Build Status](https://jenkins.ncrmnt.org/buildStatus/icon?job=GithubCI/stlink)](https://jenkins.ncrmnt.org/job/GithubCI/job/stlink/) -**NOTICE: The project has currently not an active maintainer. Feel free to contribute and discus in issue [#826](https://github.com/texane/stlink/issues/826)** +**NOTICE: The project has currently not an active maintainer. Feel free to contribute and discus in issue [#826](https://github.com/texane/stlink/issues/826)** ## HOWTO @@ -30,9 +30,9 @@ Windows users can [download v1.3.0](https://github.com/texane/stlink/releases/ta Mac OS X users can install from [homebrew](http://brewformulas.org/Stlink) or [download v1.3.0](https://github.com/texane/stlink/releases/tag/1.3.0) from the releases page. -Debian Linux users can install it via the ```stlink-tool``` package [repository](https://packages.debian.org/buster/stlink-tools) +Debian Linux users can install it via the ```stlink-tools``` package [repository](https://packages.debian.org/buster/stlink-tools) -Ubuntu Linux users can install it via the ```stlink-tool``` package [repository](https://packages.ubuntu.com/stlink-tools) +Ubuntu Linux users can install it via the ```stlink-tools``` package [repository](https://packages.ubuntu.com/stlink-tools) Arch Linux users can install from the [repository](https://www.archlinux.org/packages/community/x86_64/stlink) From 4416a24b5da7179291d64b371d8d37c7b6ce8d6f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 19 Feb 2020 21:20:10 +0100 Subject: [PATCH 0692/1435] General project update: - Updated README & CHANGELOG. - Updated issue templates. - Fixes in travis.yml --- .github/ISSUE_TEMPLATE.md | 29 -------- .github/ISSUE_TEMPLATE/bug_report.md | 70 +++++++++--------- .github/ISSUE_TEMPLATE/feature_request.md | 42 +++++++---- .github/ISSUE_TEMPLATE/support_question.md | 32 +++++++++ .travis.yml | 3 +- ChangeLog.md => CHANGELOG.md | 84 +++++++++++----------- README.md | 70 +++++++++--------- 7 files changed, 172 insertions(+), 158 deletions(-) delete mode 100644 .github/ISSUE_TEMPLATE.md create mode 100644 .github/ISSUE_TEMPLATE/support_question.md rename ChangeLog.md => CHANGELOG.md (53%) diff --git a/.github/ISSUE_TEMPLATE.md b/.github/ISSUE_TEMPLATE.md deleted file mode 100644 index 63c6c4505..000000000 --- a/.github/ISSUE_TEMPLATE.md +++ /dev/null @@ -1,29 +0,0 @@ -**NOTICE: The issue may be closed without notice when not enough information is provided!** - -Thank you for giving feedback to the stlink project. Take some time to fill out - check boxes with a X in the following items so developers and other people can try to - to find out what is going on. And add/remove what is appropriate to your problem. - -When submitting a feature request, try to reuse the list and add/remove what is appropriate. - Place a `X` between the brackets `[X]` to mark the list item. - -- [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard -- [ ] Programmer firmware version: e.g STSW-LINK007 2.27.15 -- [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) -- [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 -- [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` -- [ ] Target chip (and optional board): e.g STM32F402VG (STM32Fxxx Discovery) - -A as-detailed description possible of the problem with debug output when available. - -Output: - -``` -OUTPUT/ERROR of the commandline tool(s) -``` - -Expected/description: -`short description of the expected value` - -Thank you, -The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md index dd84ea782..821b406bc 100644 --- a/.github/ISSUE_TEMPLATE/bug_report.md +++ b/.github/ISSUE_TEMPLATE/bug_report.md @@ -1,38 +1,32 @@ ---- -name: Bug report -about: Create a report to help us improve -title: '' -labels: '' -assignees: '' - ---- - -**Describe the bug** -A clear and concise description of what the bug is. - -**To Reproduce** -Steps to reproduce the behavior: -1. Go to '...' -2. Click on '....' -3. Scroll down to '....' -4. See error - -**Expected behavior** -A clear and concise description of what you expected to happen. - -**Screenshots** -If applicable, add screenshots to help explain your problem. - -**Desktop (please complete the following information):** - - OS: [e.g. iOS] - - Browser [e.g. chrome, safari] - - Version [e.g. 22] - -**Smartphone (please complete the following information):** - - Device: [e.g. iPhone6] - - OS: [e.g. iOS8.1] - - Browser [e.g. stock browser, safari] - - Version [e.g. 22] - -**Additional context** -Add any other context about the problem here. +# Bug Report + +Thank you for giving feedback to the stlink project. + +In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out the check boxes below by setting a 'x' into the checkboxes ( [x] ) and edit each item appropriate to your specific problem. + +- [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard +- [ ] Programmer firmware version: e.g STSW-LINK007 2.27.15 +- [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) +- [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 +- [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` +- [ ] Target chip (and optional board): e.g STM32F402VG (STM32Fxxx Discovery) + +Futher we kindly ask you to describe the detected problem as detailled as possible and to add debug output if available, by using the following template: + +Commandline-Output: + +``` +OUTPUT/ERROR of the commandline tool(s) +``` + +Expected/description: + +`short description of the expected value` + + +**NOTICE: The bug report may be closed without notice when not enough information is provided!** + + +Thank you for your support. + +The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/feature_request.md b/.github/ISSUE_TEMPLATE/feature_request.md index bbcbbe7d6..bf626eb97 100644 --- a/.github/ISSUE_TEMPLATE/feature_request.md +++ b/.github/ISSUE_TEMPLATE/feature_request.md @@ -1,20 +1,32 @@ ---- -name: Feature request -about: Suggest an idea for this project -title: '' -labels: '' -assignees: '' +# Feature Request ---- +Thank you for giving feedback to the stlink project. -**Is your feature request related to a problem? Please describe.** -A clear and concise description of what the problem is. Ex. I'm always frustrated when [...] +In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out the check boxes below by setting a 'x' into the checkboxes ( [x] ) and edit each item appropriate to your specific problem. -**Describe the solution you'd like** -A clear and concise description of what you want to happen. +- [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard +- [ ] Programmer firmware version: e.g STSW-LINK007 2.27.15 +- [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) +- [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 +- [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` +- [ ] Target chip (and optional board): e.g STM32F402VG (STM32Fxxx Discovery) -**Describe alternatives you've considered** -A clear and concise description of any alternative solutions or features you've considered. +Futher we kindly ask you to describe the detected problem as detailled as possible and to add debug output if available, by using the following template: -**Additional context** -Add any other context or screenshots about the feature request here. +Commandline-Output: + +``` +OUTPUT/ERROR of the commandline tool(s) +``` + +Expected/description: + +`short description of the expected value` + + +**NOTICE: This feature request may be closed without notice when not enough information is provided!** + + +Thank you for your support. + +The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/support_question.md b/.github/ISSUE_TEMPLATE/support_question.md new file mode 100644 index 000000000..795c13a6e --- /dev/null +++ b/.github/ISSUE_TEMPLATE/support_question.md @@ -0,0 +1,32 @@ +# Support question + +Thank you for giving feedback to the stlink project. + +In order to allow developers and other contributors to help you with your question, please take some time to fill out the check boxes below by setting a 'x' into the checkboxes ( [x] ) and edit each item appropriate to your specific problem. + +- [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard +- [ ] Programmer firmware version: e.g STSW-LINK007 2.27.15 +- [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) +- [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 +- [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` +- [ ] Target chip (and optional board): e.g STM32F402VG (STM32Fxxx Discovery) + +Futher we kindly ask you to describe the detected problem as detailled as possible and to add debug output if available, by using the following template: + +Commandline-Output: + +``` +OUTPUT/ERROR of the commandline tool(s) +``` + +Expected/description: + +`short description of the expected value` + + +**NOTICE: This support question may be closed without notice when not enough information is provided!** + + +Thank you for your support. + +The stlink project maintainers diff --git a/.travis.yml b/.travis.yml index 25d1859f7..c878be799 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,4 +1,3 @@ -sudo: true language: c compiler: - gcc @@ -10,7 +9,7 @@ addons: apt: sources: # - llvm-toolchain-precise-3.8 - - ubuntu-toolchain-r-test + - sourceline: 'ppa:ubuntu-toolchain-r/test' packages: - clang # - clang-3.8 diff --git a/ChangeLog.md b/CHANGELOG.md similarity index 53% rename from ChangeLog.md rename to CHANGELOG.md index 4602d70bd..68b90c29e 100644 --- a/ChangeLog.md +++ b/CHANGELOG.md @@ -8,16 +8,16 @@ Release date: 2018-09-13 Major changes and added features: -* Implement intel hex support for GTK GUI -* Update libusb to 1.0.22 -* Add memory map for STM32F411RE target +* Implemented intel hex support for GTK GUI +* Updated libusb to 1.0.22 +* Added memory map for STM32F411RE target * Add support for STM32L4R9 target Fixes: -* FreeBSD define LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION +* FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION * Proper flash page size calculation for F412 target -* Fix flash memory map for F72xxx target +* Fixed flash memory map for F72xxx target * Return correct value on EOF for Semihosting SYS_READ For a complete list of changes see [the milestone](https://github.com/texane/stlink/milestone/6?closed=1) @@ -30,15 +30,15 @@ Release date: 2018-02-16 Major changes and added features: * STM32F72xx73xx support ([#1969148](https://github.com/texane/stlink/commit/19691485359afef1a256964afcbb8dcf4b733209)) -* Add support of STM32L496xx/4A6xx devices ([#615](https://github.com/texane/stlink/pull/615)) +* Added support of STM32L496xx/4A6xx devices ([#615](https://github.com/texane/stlink/pull/615)) Fixes: -* Fix memory map for stm32l496xx boards ([#639](https://github.com/texane/stlink/pull/639)) -* Fix write for microcontroler with RAM size less or equal to 32K ([#637](https://github.com/texane/stlink/pull/637)) +* Fixed memory map for stm32l496xx boards ([#639](https://github.com/texane/stlink/pull/639)) +* Fixed write for microcontroller with RAM size less or equal to 32K ([#637](https://github.com/texane/stlink/pull/637)) * Added LIB_INSTALL_DIR to correct libs install on 64-bit systems ([#636](https://github.com/texane/stlink/pull/636)) -* Fix verification of flash error for STM32L496x device ([#618](https://github.com/texane/stlink/pull/618)) -* Fix build on Fedora with GCC 8 ([#666](https://github.com/texane/stlink/pull/668)) +* Fixed verification of flash error for STM32L496x device ([#618](https://github.com/texane/stlink/pull/618)) +* Fixed build on Fedora with GCC 8 ([#666](https://github.com/texane/stlink/pull/668)) v1.4.0 ====== @@ -47,21 +47,21 @@ Release date: 2017-07-01 Major changes and added features: -* Add support for STM32L452 target ([#608](https://github.com/texane/stlink/pull/608)) +* Added support for STM32L452 target ([#608](https://github.com/texane/stlink/pull/608)) * Initial support to compile with Microsoft Visual Studio 2017 ([#602](https://github.com/texane/stlink/pull/602)) * Added support for flashing second bank on STM32F10x_XL ([#592](https://github.com/texane/stlink/pull/592)) -* Add support for STM32L011 target ([#572](https://github.com/texane/stlink/pull/572)) +* Added support for STM32L011 target ([#572](https://github.com/texane/stlink/pull/572)) * Allow building of debian package with CPack (@xor-gate) Updates and fixes: -* Fix compilation with GCC 7 ([#590](https://github.com/texane/stlink/pull/590)) -* Skip GTK detection if we're cross-compiling ([#588](https://github.com/texane/stlink/pull/588)) -* Fix possible memory leak ([#570](https://github.com/texane/stlink/pull/570)) -* Fix building with mingw64 ([#569](https://github.com/texane/stlink/pull/569), [#610](https://github.com/texane/stlink/pull/610)) -* Update libusb to 1.0.21 for Windows ([#562](https://github.com/texane/stlink/pull/562)) -* Fixing low-voltage flashing on STM32F7 parts. ([#567](https://github.com/texane/stlink/pull/567)) -* Update libusb to 1.0.21 for Windows ([#562](https://github.com/texane/stlink/pull/562)) +* Fixed compilation with GCC 7 ([#590](https://github.com/texane/stlink/pull/590)) +* Skipped GTK detection if we're cross-compiling ([#588](https://github.com/texane/stlink/pull/588)) +* Fixed possible memory leak ([#570](https://github.com/texane/stlink/pull/570)) +* Fixed building with mingw64 ([#569](https://github.com/texane/stlink/pull/569), [#610](https://github.com/texane/stlink/pull/610)) +* Updated libusb to 1.0.21 for Windows ([#562](https://github.com/texane/stlink/pull/562)) +* Fixed low-voltage flashing on STM32F7 parts. ([#567](https://github.com/texane/stlink/pull/567)) +* Updated libusb to 1.0.21 for Windows ([#562](https://github.com/texane/stlink/pull/562)) v1.3.1 ====== @@ -70,16 +70,16 @@ Release date: 2017-02-25 Major changes and added features: -* Add preliminary support for STM32L011 to see it after probe (chipid `0x457`) (@xor-gate) -* Strip full paths to source files in log (commit [#2c0ab7f](https://github.com/texane/stlink/commit/2c0ab7f0eb6cfda5cfbdc08bb9f6760d27c2b667)) -* Add support for STM32F413 target ([#549](https://github.com/texane/stlink/pull/549)) -* Add support for Semihosting `SYS_READC` ([#546](https://github.com/texane/stlink/pull/546)) +* Added preliminary support for STM32L011 to see it after probe (chipid `0x457`) (@xor-gate) +* Stripped full paths to source files in log (commit [#2c0ab7f](https://github.com/texane/stlink/commit/2c0ab7f0eb6cfda5cfbdc08bb9f6760d27c2b667)) +* Added support for STM32F413 target ([#549](https://github.com/texane/stlink/pull/549)) +* Added support for Semihosting `SYS_READC` ([#546](https://github.com/texane/stlink/pull/546)) Updates and fixes: -* Update documentation markdown files +* Updated documentation markdown files * Compilation fixes ([#552](https://github.com/texane/stlink/pull/552)) -* Fix compilation when path includes spaces ([#561](https://github.com/texane/stlink/pull/561)) +* Fixed compilation when path includes spaces ([#561](https://github.com/texane/stlink/pull/561)) v1.3.0 ====== @@ -90,31 +90,31 @@ Major changes and added features: * Deprecation of autotools (autoconf, automake) (@xor-gate) * Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#3fd0f09](https://github.com/texane/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) -* Add support for native debian packaging ([#444](https://github.com/texane/stlink/pull/444), [#485](https://github.com/texane/stlink/pull/485)) -* Add intel hex file reading for `st-flash` ([#459](https://github.com/texane/stlink/pull/541)) -* Add `--reset` command to `st-flash` ([#505](https://github.com/texane/stlink/pull/505)) +* Added support for native debian packaging ([#444](https://github.com/texane/stlink/pull/444), [#485](https://github.com/texane/stlink/pull/485)) +* Added intel hex file reading for `st-flash` ([#459](https://github.com/texane/stlink/pull/541)) +* Added `--reset` command to `st-flash` ([#505](https://github.com/texane/stlink/pull/505)) * Support serial numbers argument for `st-util` and `st-flash` for multi-programmer setups ([#541](https://github.com/texane/stlink/pull/541)) -* Add kill ('k') command to gdb-server for `st-util` ([#9804416](https://github.com/texane/stlink/commit/98044163ab34bf5159f121d1c49ffb3550321ca0)) -* Add manpages (generated with pandoc from Markdown) ([#464](https://github.com/texane/stlink/pull/464)) -* Rewrite commandline parsing for `st-flash` ([#459](https://github.com/texane/stlink/pull/459)) -* Add support for ARM semihosting to `st-util` ([#454](https://github.com/texane/stlink/pull/454), [#455](https://github.com/texane/stlink/pull/455)) +* Added kill ('k') command to gdb-server for `st-util` ([#9804416](https://github.com/texane/stlink/commit/98044163ab34bf5159f121d1c49ffb3550321ca0)) +* Added manpages (generated with pandoc from Markdown) ([#464](https://github.com/texane/stlink/pull/464)) +* Rewritten commandline parsing for `st-flash` ([#459](https://github.com/texane/stlink/pull/459)) +* Added support for ARM semihosting to `st-util` ([#454](https://github.com/texane/stlink/pull/454), [#455](https://github.com/texane/stlink/pull/455)) Chip support added for: * STM32L432 ([#501](https://github.com/texane/stlink/pull/501)) * STM32F412 ([#538](https://github.com/texane/stlink/pull/538)) * STM32F410 ([#9c635e4](https://github.com/texane/stlink/commit/9c635e419deca697ff823000aad2e39d47ec8d6c)) -* Add memory map for STM32F401XE ([#460](https://github.com/texane/stlink/pull/460)) +* Added memory map for STM32F401XE ([#460](https://github.com/texane/stlink/pull/460)) * L0x Category 5 devices ([#406](https://github.com/texane/stlink/pull/406)) -* Add L0 Category 2 device (chip id: 0x425) ([#72b8e5e](https://github.com/texane/stlink/commit/72b8e5ec87e4fa386a8e94fe68df29467d4354ce)) +* Added L0 Category 2 device (chip id: 0x425) ([#72b8e5e](https://github.com/texane/stlink/commit/72b8e5ec87e4fa386a8e94fe68df29467d4354ce)) Updates and fixes: * Fixed STM32F030 erase error ([#442](https://github.com/texane/stlink/pull/442)) * Fixed Cygwin build ([#68b0f3b](https://github.com/texane/stlink/commit/68b0f3bddc3c4aaffe34caa6a3201029edd8ad56)) * Reset flash mass erase (MER) bit after mass erase for safety ([#489](https://github.com/texane/stlink/pull/489)) -* Fix memory map for STM32F4 (@zulusw) -* Fix STM32L-problem with flash loader (issue #390) (Tom de Boer) +* Fixed memory map for STM32F4 (@zulusw) +* Fixed STM32L-problem with flash loader (issue #390) (Tom de Boer) * `st-util` don't read target voltage on startup as it crashes STM32F100 (probably stlink/v1) (Greg Alexander) * Do a JTAG reset prior to reading CPU information when processor is in deep sleep (@andyg24) * Redesign of `st-flash` commandline options parsing (pull-request #459) (@dev26th) @@ -122,12 +122,12 @@ Updates and fixes: v1.2.0 ====== -Release date: 16 may 2016 +Release date: 2016-05-16 Features added: -* Add multiple stlink probing (`st-info --probe`, `st-info --hla-serial`) with printing serial in hex and OpenOCD `hla_serial` format (Jerry Jacobs) -* Add stlink usb probe API functions (Jerry Jacobs) +* Added multiple stlink probing (`st-info --probe`, `st-info --hla-serial`) with printing serial in hex and OpenOCD `hla_serial` format (Jerry Jacobs) +* Added stlink usb probe API functions (Jerry Jacobs) * Added parameter to specify one stlink v2 of many (Georg von Zengen) Changes: @@ -136,7 +136,7 @@ Changes: Updates and fixes: -* Synchronize cache for stm32f7 (Tristan Gingold) +* Synchronized cache for stm32f7 (Tristan Gingold) * Allow flashing of STM32L4 down to 1.71 V (Greg Meiste) * Fix on stm32l4 to clear flash mass erase flags on CR (Bruno Dal Bo) * Proper writing of page 0 of second bank for stm32l476xe (Tobias Badertscher) @@ -148,7 +148,7 @@ Updates and fixes: * Make sure MCU is halted before running RAM based flashloaders (mlundinse) * Could not flash STM32_F3_SMALL (Max Chen) * STM32F4 8-bit support for 1.8v operation (Andy Isaacson) -* Fix F2 memory map (Nicolas Schodet) +* Fixed F2 memory map (Nicolas Schodet) * Memory map for stm32f42xxx and stm32f43xxx devices (Craig Lilley) * Stm32l0x flash loader (Robin Kreis) @@ -156,7 +156,7 @@ Chip support added for: * STM32L053R8 (Jean-Luc Béchennec) * STM32F7 Support (mlundinse) -* Add STM32L4 to CHIPID #defines and devices[], flash driver and loaded (Dave Vandervies) +* Added STM32L4 to CHIPID #defines and devices[], flash driver and loader (Dave Vandervies) * Basic support for F446 (Pavel Kirienko) * STM32F303 High Density * STM32L1xx Cat.2 devices (Nicolas Schodet) diff --git a/README.md b/README.md index c57bdee91..757412878 100644 --- a/README.md +++ b/README.md @@ -3,26 +3,29 @@ Open source version of the STMicroelectronics Stlink Tools [![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/texane/stlink/releases/latest) [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) -[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/1.5.1.svg)](https://github.com/texane/stlink/compare/1.5.1...master) +[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/v1.5.1.svg)](https://github.com/texane/stlink/releases/master) [![Downloads](https://img.shields.io/github/downloads/texane/stlink/total.svg)](https://github.com/texane/stlink/releases) + [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) -[![Build Status](https://jenkins.ncrmnt.org/buildStatus/icon?job=GithubCI/stlink)](https://jenkins.ncrmnt.org/job/GithubCI/job/stlink/) +[![macOS Status](https://img.shields.io/travis/texane/stlink/master.svg?label=osx)](https://travis-ci.org/texane/stlink) -**NOTICE: The project has currently not an active maintainer. Feel free to contribute and discus in issue [#826](https://github.com/texane/stlink/issues/826)** ## HOWTO -First, you have to know there are several boards supported by the software. -Those boards use a chip to translate from USB to JTAG commands. The chip is -called stlink and there are two versions: - -* STLINKv1, present on STM32VL discovery kits, -* STLINKv2, present on STM32L discovery and later kits. +This StLink toolset supports several so called stlink programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG. These programmer boards are available in four versions: -Two different transport layers are used: +* **STLINKv1:** + - transport layer: SCSI passthru commands over USB + - present on STM32VL discovery kits +* **STLINKv2:** + * transport layer: raw USB commands + * present on STM32L discovery and nucleo and later kits +* **STLINKv2-1:** + * transport layer: raw USB commands + * present on some STM32 nucleo boards +* **STLINKv3:** + * _currently not supported by this toolset_ -* STLINKv1 uses SCSI passthru commands over USB -* STLINKv2 and STLINKv2-1 (seen on nucleo boards) uses raw USB commands. ## Installation @@ -48,11 +51,11 @@ FreeBSD users can install from [freshports](https://www.freshports.org/devel/stl OpenBSD users need to install [from source](doc/compiling.md). + ## Installation from source (advanced users) -When there is no executable available for your platform or you need the latest - (possible unstable) version you need to compile yourself. This is explained in - the [compiling manual](doc/compiling.md). +When there is no executable available for your platform or you need the latest (possible unstable) version you need to compile yourself. This is explained in the [compiling manual](doc/compiling.md). + ## Using the gdb server @@ -101,6 +104,7 @@ Transfer rate: 1 KB/sec, 560 bytes/write. (gdb) continue ``` + ## Resetting the chip from GDB You may reset the chip using GDB if you want. You'll need to use `target @@ -138,6 +142,7 @@ it at 0x20000000 and do It will be loaded, and pc will be adjusted to point to start of the code, if it is linked correctly (i.e. ELF has correct entry point). + ## Writing to flash The GDB stub ships with a correct memory map, including the flash area. @@ -149,6 +154,7 @@ If you would link your executable to `0x08000000` and then do then it would be written to the memory. + ## Writing Option Bytes Example to read and write option bytes (currently writing only supported for STM32G0 and STM32L0) @@ -157,36 +163,34 @@ Example to read and write option bytes (currently writing only supported for STM ./st-flash --debug --reset --format binary --flash=128k write option_bytes_dump.bin 0x1FFF7800 ``` + ## FAQ Q: My breakpoints do not work at all or only work once. -A: Optimizations can cause severe instruction reordering. For example, -if you are doing something like `REG = 0x100;' in a loop, the code may -be split into two parts: loading 0x100 into some intermediate register -and moving that value to REG. When you set up a breakpoint, GDB will -hook to the first instruction, which may be called only once if there are -enough unused registers. In my experience, -O3 causes that frequently. +A: Optimizations can cause severe instruction reordering. For example, if you are doing something like `REG = 0x100;' in a loop, the code may be split into two parts: loading 0x100 into some intermediate register and moving that value to REG. When you set up a breakpoint, GDB will hook to the first instruction, which may be called only once if there are enough unused registers. In my experience, -O3 causes that frequently. Q: At some point I use GDB command `next', and it hangs. -A: Sometimes when you will try to use GDB `next` command to skip a loop, -it will use a rather inefficient single-stepping way of doing that. -Set up a breakpoint manually in that case and do `continue`. +A: Sometimes when you will try to use GDB `next` command to skip a loop, it will use a rather inefficient single-stepping way of doing that. Set up a breakpoint manually in that case and do `continue`. Q: Load command does not work in GDB. -A: Some people report XML/EXPAT is not enabled by default when compiling -GDB. Memory map parsing thus fail. Use --enable-expat. +A: Some people report XML/EXPAT is not enabled by default when compiling GDB. Memory map parsing thus fail. Use --enable-expat. + ## Currently known working combinations of programmer and target See [doc/tested-boards.md](doc/tested-boards.md) +## Changelog + +The [Changelog](CHANGELOG) for the StLink Tools. + + ## Known missing features -Some features are missing from the `texane/stlink` project and we would like you to - help us out if you want to get involved: +Some features are missing from the `texane/stlink` project and we would like you to help us out if you want to get involved: * Control programming speed (See [#462](https://github.com/texane/stlink/issues/462)) * OTP area programming (See [#202](https://github.com/texane/stlink/issues/202)) @@ -197,12 +201,11 @@ Some features are missing from the `texane/stlink` project and we would like you * Instrumentation Trace Macro (ITM) Cell (See [#136](https://github.com/texane/stlink/issues/136)) * Writing external memory connected to an STM32 controller (e.g Quad SPI NOR flash) (See [#412](https://github.com/texane/stlink/issues/412)) -## Known bugs +## Known bugs ### Sometimes flashing only works after a mass erase -There is seen a problem sometimes where a flash loader run error occurs and is resolved after mass-erase -of the flash: +There is seen a problem sometimes where a flash loader run error occurs and is resolved after mass-erase of the flash: ``` 2015-12-09T22:01:57 INFO src/stlink-common.c: Successfully loaded flash loader in sram @@ -212,6 +215,7 @@ of the flash: Issue related to this bug: [#356](https://github.com/texane/stlink/issues/356) + ### Flash size is detected as zero bytes size It is possible that the STM32 flash is write protected, the st-flash tool will show something like this: @@ -243,6 +247,7 @@ Try to remove the write protection (probably only possible with ST Link Utility Issue related to this bug: [#545](https://github.com/texane/stlink/issues/545) + ## Contributing and versioning * The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) @@ -251,4 +256,5 @@ Issue related to this bug: [#545](https://github.com/texane/stlink/issues/545) ## License The stlink library and tools are licensed under the [BSD license](LICENSE). -The flashloaders/stm32l0x.s and flashloaders/stm32lx.s source files are licensed under the GPL-2+. + +The flashloaders/stm32l0x.s and flashloaders/stm32lx.s source files are licensed under the GPLv2+. From 9970b67fa95f026ae562e3931feaabd1c3bae651 Mon Sep 17 00:00:00 2001 From: Nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 20 Feb 2020 00:24:18 +0100 Subject: [PATCH 0693/1435] Create CODE_OF_CONDUCT.md --- CODE_OF_CONDUCT.md | 76 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 CODE_OF_CONDUCT.md diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md new file mode 100644 index 000000000..b0623068a --- /dev/null +++ b/CODE_OF_CONDUCT.md @@ -0,0 +1,76 @@ +# Contributor Covenant Code of Conduct + +## Our Pledge + +In the interest of fostering an open and welcoming environment, we as +contributors and maintainers pledge to making participation in our project and +our community a harassment-free experience for everyone, regardless of age, body +size, disability, ethnicity, sex characteristics, gender identity and expression, +level of experience, education, socio-economic status, nationality, personal +appearance, race, religion, or sexual identity and orientation. + +## Our Standards + +Examples of behavior that contributes to creating a positive environment +include: + +* Using welcoming and inclusive language +* Being respectful of differing viewpoints and experiences +* Gracefully accepting constructive criticism +* Focusing on what is best for the community +* Showing empathy towards other community members + +Examples of unacceptable behavior by participants include: + +* The use of sexualized language or imagery and unwelcome sexual attention or + advances +* Trolling, insulting/derogatory comments, and personal or political attacks +* Public or private harassment +* Publishing others' private information, such as a physical or electronic + address, without explicit permission +* Other conduct which could reasonably be considered inappropriate in a + professional setting + +## Our Responsibilities + +Project maintainers are responsible for clarifying the standards of acceptable +behavior and are expected to take appropriate and fair corrective action in +response to any instances of unacceptable behavior. + +Project maintainers have the right and responsibility to remove, edit, or +reject comments, commits, code, wiki edits, issues, and other contributions +that are not aligned to this Code of Conduct, or to ban temporarily or +permanently any contributor for other behaviors that they deem inappropriate, +threatening, offensive, or harmful. + +## Scope + +This Code of Conduct applies both within project spaces and in public spaces +when an individual is representing the project or its community. Examples of +representing a project or community include using an official project e-mail +address, posting via an official social media account, or acting as an appointed +representative at an online or offline event. Representation of a project may be +further defined and clarified by project maintainers. + +## Enforcement + +Instances of abusive, harassing, or otherwise unacceptable behavior may be +reported by contacting the project team at texane@gmail.com. All +complaints will be reviewed and investigated and will result in a response that +is deemed necessary and appropriate to the circumstances. The project team is +obligated to maintain confidentiality with regard to the reporter of an incident. +Further details of specific enforcement policies may be posted separately. + +Project maintainers who do not follow or enforce the Code of Conduct in good +faith may face temporary or permanent repercussions as determined by other +members of the project's leadership. + +## Attribution + +This Code of Conduct is adapted from the [Contributor Covenant][homepage], version 1.4, +available at https://www.contributor-covenant.org/version/1/4/code-of-conduct.html + +[homepage]: https://www.contributor-covenant.org + +For answers to common questions about this code of conduct, see +https://www.contributor-covenant.org/faq From 5f1264787c16aaf47e21e3566f8d9024e28b959a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 20 Feb 2020 00:37:04 +0100 Subject: [PATCH 0694/1435] Archived page from github project wiki. --- LICENSE => LICENSE.md | 0 README.md | 6 +-- doc/wiki_old.md | 108 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 111 insertions(+), 3 deletions(-) rename LICENSE => LICENSE.md (100%) create mode 100644 doc/wiki_old.md diff --git a/LICENSE b/LICENSE.md similarity index 100% rename from LICENSE rename to LICENSE.md diff --git a/README.md b/README.md index 757412878..f1e2760c6 100644 --- a/README.md +++ b/README.md @@ -12,7 +12,7 @@ Open source version of the STMicroelectronics Stlink Tools ## HOWTO -This StLink toolset supports several so called stlink programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG. These programmer boards are available in four versions: +This stlink toolset supports several so called stlink programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG. These programmer boards are available in four versions: * **STLINKv1:** - transport layer: SCSI passthru commands over USB @@ -185,7 +185,7 @@ See [doc/tested-boards.md](doc/tested-boards.md) ## Changelog -The [Changelog](CHANGELOG) for the StLink Tools. +The [Changelog](CHANGELOG.md) for the StLink Tools. ## Known missing features @@ -255,6 +255,6 @@ Issue related to this bug: [#545](https://github.com/texane/stlink/issues/545) ## License -The stlink library and tools are licensed under the [BSD license](LICENSE). +The stlink library and tools are licensed under the [BSD license](LICENSE.md). The flashloaders/stm32l0x.s and flashloaders/stm32lx.s source files are licensed under the GPLv2+. diff --git a/doc/wiki_old.md b/doc/wiki_old.md new file mode 100644 index 000000000..81e70a277 --- /dev/null +++ b/doc/wiki_old.md @@ -0,0 +1,108 @@ +Welcome to the stlink wiki! (Archived: 2014-08-11) + +Misc: +Windows pre-compiled binaries are available at http://www.emb4fun.de/archive/stlink/index.html + +FAQ: +Q: Where can I get help? Is there a forum or maybe a mailing list? + +A: todo + +Q: How can I install stlink and flash binaries on Mac OS X ? + +A: **20140811: ** installed on Mac OS X 10.9.4 with ports method, however STlink v2 does not seem to work with libusb if you upgrade to the newest firmware !! Only older firmware on STlink v2 works. + +[https://coderwall.com/p/oznj_q](https://coderwall.com/p/oznj_q) + +`sudo port install libusb automake autoconf pkgconfig` + +`aclocal --force -I /opt/local/share/aclocal` + +`git clone https://github.com/texane/stlink.git stlink-utility` + +`cd stlink-utility` + +`./autogen.sh` + +`./configure` + +`make` + + +Then trying to flash the image with STLINK v2 : + +`./st-flash write ~/Downloads/irq.bin 0x8000000` + +> libusb_handle_events() timeout +> +> [!] send_recv + +After downgrading the firmware, flashing works +ST-Link/V2 debugger with downgraded V2.14.3 firmware: + +https://drive.google.com/folderview?id=0Bzv7UpKpOQhnbXJVVEg4VUo2M1k + +as described here: + +http://community.spark.io/t/how-to-flash-a-brand-new-freshly-soldered-stm32f103-chip/3906 + +`./st-flash write ~/Downloads/irq.bin 0x8000000` + +> 2014-08-11T23:14:52 INFO src/stlink-common.c: Loading device parameters.... +> +> 2014-08-11T23:14:52 INFO src/stlink-common.c: Device connected is: F1 Medium-density device, id 0x20036410 +> +> 2014-08-11T23:14:52 INFO src/stlink-common.c: SRAM size: 0x5000 bytes (20 KiB), Flash: 0x20000 bytes (128 KiB) in +> pages of 1024 bytes +> +> 2014-08-11T23:14:52 INFO src/stlink-common.c: Attempting to write 24904 (0x6148) bytes to stm32 address: 134217728 +> (0x8000000) +> +> Flash page at addr: 0x08006000 erased +> +> 2014-08-11T23:14:53 INFO src/stlink-common.c: Finished erasing 25 pages of 1024 (0x400) bytes +> +> 2014-08-11T23:14:53 INFO src/stlink-common.c: Starting Flash write for VL/F0 core id +> +> 2014-08-11T23:14:53 INFO src/stlink-common.c: Successfully loaded flash loader in sram 24/24 pages written +> +> 2014-08-11T23:14:54 INFO src/stlink-common.c: Starting verification of write complete +> +> 2014-08-11T23:14:54 INFO src/stlink-common.c: Flash written and verified! jolly good! + + +Installation of openOCD on Mac OS X with STlink-v2 has been successful: + +`sudo port install openocd +jlink +stlink +ft2232` + +`/opt/local/bin/openocd --version` + +> Open On-Chip Debugger 0.7.0 (2014-08-11-22:12) + +`openocd -f /opt/local/share/openocd/scripts/interface/stlink-v2.cfg -f /opt/local/share/openocd/scripts/target/stm32f1x_stlink.cfg ` + +> Open On-Chip Debugger 0.8.0 (2014-08-11-15:36) +> +> Licensed under GNU GPL v2 +> +> For bug reports, read http://openocd.sourceforge.net/doc/doxygen/bugs.html +> +> Info : This adapter doesn't support configurable speed +> +> Info : STLINK v2 JTAG v21 API v2 SWIM v4 VID 0x0483 PID 0x3748 +> +> Info : using stlink api v2 +> +> Info : Target voltage: 3.244269 +> +> Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints + +and connecting to the server through telnet yields a successful installation + +`telnet localhost 4444` + +> Connected to localhost. +> +> Escape character is '^]'. +> +> Open On-Chip Debugger From 3f9ae02d8020786f605c3f9c09d9ace9c38a7c4e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 20 Feb 2020 01:56:53 +0100 Subject: [PATCH 0695/1435] Updated CHANGELOG.md for upcoming release. --- CHANGELOG.md | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 68b90c29e..20d242a1a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,57 @@ Stlink ChangeLog ================ +v1.6.0 +====== + +Release date: 2020-02-20 + +Major changes and added features: + +* Added O_BINARY option to open file ([#753](https://github.com/texane/stlink/pull/753)) +* Added preliminary support for some STM32G0 chips ([#759](https://github.com/texane/stlink/pull/759)) ([#760](https://github.com/texane/stlink/pull/760)) +* Added support for mass erasing second bank on STM32F10x_XL ([#767](https://github.com/texane/stlink/pull/767)) +* Added call to clear PG bit after writing to flash ([#773](https://github.com/texane/stlink/pull/773)) +* Added howto for sending NRST signal through GDB ([#776](https://github.com/texane/stlink/pull/776)) +* Added support to write option bytes for the STM32G0 ([#778](https://github.com/texane/stlink/pull/778)) +* Added simple read/write support for STM32WB55 chips ([#786](https://github.com/texane/stlink/pull/786)) +* Added STLink V3SET VID:PIDs to the udev rules ([#789](https://github.com/texane/stlink/pull/789)) +* Support for "STM32+Audio" v2-1 firmware ([#790](https://github.com/texane/stlink/pull/790)) +* Initial support for STM32L41X ([#799](https://github.com/texane/stlink/pull/799)) +* Build for Windows under Debian/Ubuntu ([#802](https://github.com/texane/stlink/pull/802)) +* Allow for 64 bytes serials ([#809](https://github.com/texane/stlink/pull/809)) +* Added support to read and write option bytes for STM32F2 series (Orie22) +* Added full support for STLINK CHIP ID L4RX (Brad Natelborg) +* Added support to write option bytes to STM32F4 devices (Davey Struijk) + +Updates and fixes: + +* Make udev rules and modprobe conf installation optional ([#741](https://github.com/texane/stlink/pull/741)) +* Fixed case when __FILE__ don't contain "/" nor "\\". ([#745](https://github.com/texane/stlink/pull/745)) +* Fixed double dash issue in doc/man ([#746](https://github.com/texane/stlink/pull/746)) +* Fixed Debug error on line 123 in CMakeLists.txt (@xor-gate) +* Only do bank calculation on STM32L4 devices with dual banked flash ([#751](https://github.com/texane/stlink/pull/751)) +* Updated STM32F3xx chip ID that covers a few different devices ([#758](https://github.com/texane/stlink/pull/758)) +* Fixed versioning when compiling from the checked out git-repo ([#762](https://github.com/texane/stlink/pull/762)) +* Fixed "unkown chip id", piped output and st-util -v ([#763](https://github.com/texane/stlink/pull/763)) +* win32: move usleep definition to unistd.h ([#765](https://github.com/texane/stlink/pull/765)) +* Fixed relative path to the UI files needed by stlink-gui-local (GUI) ([#771](https://github.com/texane/stlink/pull/771)) +* Fixed package name "devscripts" in doc/compiling.md ([#775](https://github.com/texane/stlink/pull/775)) +* Fixed apparent STM32G0 flashing issue ([#797](https://github.com/texane/stlink/pull/797)) +* Fixed few potential memory/resource leaks ([#803](https://github.com/texane/stlink/pull/803)) +* Fixed flash verification error on STM32WB55RG ([#810](https://github.com/texane/stlink/pull/810)) ([#816](https://github.com/texane/stlink/pull/816)) +* Do not issue JTAG reset on stlink-v1 (Gwenhael Goavec-Merou) +* Fixed flash size of STM32 Discovery vl (Gwenhael Goavec-Merou) +* Added support for writing option bytes on STM32L0 (Adrian Imboden) +* Updated documentation on software structure ([#851](https://github.com/texane/stlink/pull/851)) + +General project updates: + +* Updated issue templates, README.md and CHANGELOG.md (Nightwalker-87) +* Added CODE_OF_CONDUCT (Nightwalker-87) +* Fixed travis build config file (Nightwalker-87) +* Archived page from github project wiki to doc/wiki_old.md (Nightwalker-87) + v1.5.1 ====== From 393310fc9925907c239f0ad7fac1e8d0565d65c0 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 20 Feb 2020 02:08:49 +0100 Subject: [PATCH 0696/1435] Release v1.6.0 --- .version | 2 +- README.md | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.version b/.version index 26ca59460..dc1e644a1 100644 --- a/.version +++ b/.version @@ -1 +1 @@ -1.5.1 +1.6.0 diff --git a/README.md b/README.md index f1e2760c6..5d98f0e7e 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ Open source version of the STMicroelectronics Stlink Tools [![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/texane/stlink/releases/latest) [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) -[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/v1.5.1.svg)](https://github.com/texane/stlink/releases/master) +[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/v1.6.0.svg)](https://github.com/texane/stlink/releases/master) [![Downloads](https://img.shields.io/github/downloads/texane/stlink/total.svg)](https://github.com/texane/stlink/releases) [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) From 1de2e4b0f8c1d1ff3805e3b5e9424008207b9575 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 20 Feb 2020 12:25:23 +0100 Subject: [PATCH 0697/1435] Added status messages to CMakeLists.txt --- CMakeLists.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index b0eef1189..90378f9ed 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -121,6 +121,10 @@ else() set(STLINK_SHARED_VERSION ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}) endif() +message(STATUS "STLINK_LIB_SHARED: ${STLINK_LIB_SHARED}") +message(STATUS "PROJECT_VERSION_MAJOR: ${PROJECT_VERSION_MAJOR}") +message(STATUS "VERSION: ${STLINK_SHARED_VERSION}") + set_target_properties(${STLINK_LIB_SHARED} PROPERTIES SOVERSION ${PROJECT_VERSION_MAJOR} VERSION ${STLINK_SHARED_VERSION} @@ -162,7 +166,7 @@ if (APPLE) find_library(IOKit IOKit) target_link_libraries(${STLINK_LIB_STATIC} ${CoreFoundation} ${IOKit} ${ObjC}) endif() - + if (WIN32 OR MSYS OR MINGW) target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} wsock32 ws2_32) else() From bc068a34b3722cbac6d108c3ecb5bd1bbb698b33 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 21 Feb 2020 00:09:51 +0100 Subject: [PATCH 0698/1435] Added support for G031/G041 chips (#825) --- include/stlink/chipid.h | 5 ++- src/chipid.c | 15 ++++++- src/common.c | 98 +++++++++++++++++++++++++++++------------ src/flash_loader.c | 65 +++++++++++++++------------ 4 files changed, 125 insertions(+), 58 deletions(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index e9cb48167..368e157a7 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -69,11 +69,12 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F72XXX = 0x452, /* This ID is found on the NucleoF722ZE board */ STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, + STLINK_CHIPID_STM32_G0_CAT2 = 0x460, // G071/081 STLINK_CHIPID_STM32_F413 = 0x463, - STLINK_CHIPID_STM32_L4RX = 0x470, // taken from the STM32L4R9I-DISCO board - STLINK_CHIPID_STM32_G0X1 = 0x460, + STLINK_CHIPID_STM32_G0_CAT1 = 0x466, // G031/041 STLINK_CHIPID_STM32_G4_CAT2 = 0x468, // See: RM 0440 s46.6.1 "MCU device ID code". STLINK_CHIPID_STM32_G4_CAT3 = 0x469, + STLINK_CHIPID_STM32_L4RX = 0x470, // taken from the STM32L4R9I-DISCO board STLINK_CHIPID_STM32_WB55 = 0x495 }; diff --git a/src/chipid.c b/src/chipid.c index 938cc1f30..ebb5a9027 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -521,16 +521,27 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1ff00000, .bootrom_size = 0x2000 }, + { + // STM32G031/041 (from RM0444) + .chip_id = STLINK_CHIPID_STM32_G0_CAT1, + .description = "G031/G041 device", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2K (sec 3.2) + .sram_size = 0x2000, // 8K (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x2000 // 8K (sec 2.2.2 table 3) + }, { // STM32G071/081 (from RM0444) - .chip_id = STLINK_CHIPID_STM32_G0X1, + .chip_id = STLINK_CHIPID_STM32_G0_CAT2, .description = "G071/G081 device", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2K (sec 3.2) .sram_size = 0x9000, // 36K (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000 // 28K (table 2) + .bootrom_size = 0x7000 // 28K (sec 2.2.2 table 2) }, { // STM32G431/441 (from RM0440) diff --git a/src/common.c b/src/common.c index e7d4dc934..bcce965aa 100644 --- a/src/common.c +++ b/src/common.c @@ -293,7 +293,8 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { reg = FLASH_F4_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) reg = STM32L4_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) reg = STM32Gx_FLASH_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) reg = STM32WB_FLASH_CR; @@ -325,7 +326,8 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { cr_lock_shift = FLASH_F4_CR_LOCK; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) cr_lock_shift = STM32L4_FLASH_CR_LOCK; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) cr_lock_shift = STM32Gx_FLASH_CR_LOCK; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) cr_lock_shift = STM32WB_FLASH_CR_LOCK; @@ -346,7 +348,8 @@ static void unlock_flash(stlink_t *sl) { key_reg = FLASH_F4_KEYR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) key_reg = STM32L4_FLASH_KEYR; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) key_reg = STM32Gx_FLASH_KEYR; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) key_reg = STM32WB_FLASH_KEYR; @@ -385,7 +388,8 @@ static void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_lock_shift = STM32Gx_FLASH_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { @@ -418,7 +422,8 @@ static void set_flash_cr_pg(stlink_t *sl) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= 1 << STM32L4_FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { @@ -439,7 +444,8 @@ static void clear_flash_cr_pg(stlink_t *sl) { cr_reg = FLASH_F4_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) cr_reg = STM32L4_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) cr_reg = STM32Gx_FLASH_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) cr_reg = STM32WB_FLASH_CR; @@ -453,7 +459,8 @@ static void clear_flash_cr_pg(stlink_t *sl) { static void set_flash_cr_per(stlink_t *sl) { uint32_t cr_reg, val; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) cr_reg = STM32Gx_FLASH_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) cr_reg = STM32WB_FLASH_CR; @@ -473,7 +480,8 @@ static void set_flash_cr2_per(stlink_t *sl) { static void clear_flash_cr_per(stlink_t *sl) { uint32_t cr_reg; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) cr_reg = STM32Gx_FLASH_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) cr_reg = STM32WB_FLASH_CR; @@ -495,7 +503,8 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); cr_pg = 1 << STM32L4_FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); @@ -565,7 +574,8 @@ static void set_flash_cr_strt(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_strt = 1 << STM32L4_FLASH_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_strt = 1 << STM32Gx_FLASH_CR_STRT; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { @@ -596,7 +606,8 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { sr_reg = FLASH_F4_SR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) sr_reg = STM32L4_FLASH_SR; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) sr_reg = STM32Gx_FLASH_SR; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) sr_reg = STM32WB_FLASH_SR; @@ -622,7 +633,8 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { sr_busy_shift = FLASH_F4_SR_BSY; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) sr_busy_shift = STM32L4_FLASH_SR_BSY; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) + else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) sr_busy_shift = STM32Gx_FLASH_SR_BSY; else if (sl->flash_type == STLINK_FLASH_TYPE_WB) sr_busy_shift = STM32WB_FLASH_SR_BSY; @@ -846,8 +858,10 @@ int stlink_load_device_params(stlink_t *sl) { flash_size = flash_size >>16; flash_size = flash_size & 0xffff; - if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && ( flash_size == 0 )) { - sl->flash_size = 128 * 1024; + if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || + sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || + sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && ( flash_size == 0 )) { + sl->flash_size = 128 * 1024; } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { sl->flash_size = (flash_size & 0xff) * 1024; } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_HIGH) { @@ -1648,9 +1662,15 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ - if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || (sl->chip_id == STLINK_CHIPID_STM32_F4) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || - (sl->chip_id == STLINK_CHIPID_STM32_F446) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || + if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || + (sl->chip_id == STLINK_CHIPID_STM32_F4) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || + (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || + (sl->chip_id == STLINK_CHIPID_STM32_F446) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || + (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || (sl->chip_id == STLINK_CHIPID_STM32_F412)) { uint32_t sector=calculate_F4_sectornum(flashaddr); if (sector>= 12) { @@ -1660,7 +1680,8 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ else if(sector<5) sl->flash_pgsz=0x10000; else sl->flash_pgsz=0x20000; } - else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { + else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || + sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { uint32_t sector=calculate_F7_sectornum(flashaddr); if (sector<4) sl->flash_pgsz=0x8000; else if(sector<5) sl->flash_pgsz=0x20000; @@ -1677,7 +1698,8 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_L4) { + if (sl->flash_type == STLINK_FLASH_TYPE_F4 || + sl->flash_type == STLINK_FLASH_TYPE_L4) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1696,7 +1718,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || + sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { // calculate the actual page from the address uint32_t sector=calculate_F7_sectornum(flashaddr); @@ -1731,7 +1754,10 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) uint32_t val; uint32_t flash_regs_base; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || sl->chip_id == STLINK_CHIPID_STM32_L011) { + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || + sl->chip_id == STLINK_CHIPID_STM32_L011) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; } else { flash_regs_base = STM32L_FLASH_REGS_ADDR; @@ -1840,7 +1866,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) clear_flash_cr_per(sl); // Re-lock the flash. lock_flash(sl); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr < FLASH_BANK2_START_ADDR))) { + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr < FLASH_BANK2_START_ADDR))) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -1894,7 +1921,10 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) int stlink_erase_flash_mass(stlink_t *sl) { /* TODO: User MER bit to mass-erase G0, G4, WB series. */ - if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4 || sl->flash_type == STLINK_FLASH_TYPE_WB) { + if (sl->flash_type == STLINK_FLASH_TYPE_L0 || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4 || + sl->flash_type == STLINK_FLASH_TYPE_WB) { /* erase each page */ int i = 0, num_pages = (int) sl->flash_size/sl->flash_pgsz; for (i = 0; i < num_pages; i++) { @@ -2007,7 +2037,10 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin uint32_t flash_regs_base; flash_loader_t fl; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || sl->chip_id == STLINK_CHIPID_STM32_L011) { + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || + sl->chip_id == STLINK_CHIPID_STM32_L011) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; } else { flash_regs_base = STM32L_FLASH_REGS_ADDR; @@ -2568,7 +2601,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_g0x1(stlink_t *sl, uint8_t* base, uint32_t len) { +static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t len) { uint32_t val; @@ -2577,6 +2610,16 @@ static int stlink_write_option_bytes_g0x1(stlink_t *sl, uint8_t* base, uint32_t return -1; } + // Make sure we've loaded the context with the chip details + stlink_core_id(sl); + + /* Check if chip is supported and for correct address */ + if(sl->chip_id != STLINK_CHIPID_STM32_G0_CAT1 && + sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2) { + ELOG("Option bytes writing is currently only supported for the STM32G0\n"); + return -1; + } + /* Unlock flash if necessary (ref manuel page 52) */ stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); if ((val & (1u << STM32Gx_FLASH_CR_LOCK))) { @@ -2880,8 +2923,9 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui stlink_core_id(sl); /* Check if chip is supported and for correct address */ - if((sl->chip_id == STLINK_CHIPID_STM32_G0X1) && (addr == STM32_G0_OPTION_BYTES_BASE)) { - return stlink_write_option_bytes_g0x1(sl, base, len); + if(((sl->chip_id == STLINK_CHIPID_STM32_G0_CAT1) || + (sl->chip_id == STLINK_CHIPID_STM32_G0_CAT2)) && (addr == STM32_G0_OPTION_BYTES_BASE)) { + return stlink_write_option_bytes_g0x(sl, base, len); } else if((sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) && (addr == STM32_L0_CAT2_OPTION_BYTES_BASE)) { return stlink_write_option_bytes_l0_cat2(sl, base, len); diff --git a/src/flash_loader.c b/src/flash_loader.c index 73db427a7..7479e05bb 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -255,32 +255,37 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2 - || sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS || sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH - || sl->chip_id == STLINK_CHIPID_STM32_L152_RE || sl->chip_id == STLINK_CHIPID_STM32_L011 - || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */ + if (sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || + sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2 || + sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS || + sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH || + sl->chip_id == STLINK_CHIPID_STM32_L152_RE || + sl->chip_id == STLINK_CHIPID_STM32_L011 || + sl->chip_id == STLINK_CHIPID_STM32_L0 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); - } else if (sl->core_id == STM32VL_CORE_ID - || sl->chip_id == STLINK_CHIPID_STM32_F1_MEDIUM - || sl->chip_id == STLINK_CHIPID_STM32_F3 - || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL - || sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH - || sl->chip_id == STLINK_CHIPID_STM32_F37x - || sl->chip_id == STLINK_CHIPID_STM32_F334) { + } else if (sl->core_id == STM32VL_CORE_ID || + sl->chip_id == STLINK_CHIPID_STM32_F1_MEDIUM || + sl->chip_id == STLINK_CHIPID_STM32_F3 || + sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL || + sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH || + sl->chip_id == STLINK_CHIPID_STM32_F37x || + sl->chip_id == STLINK_CHIPID_STM32_F334) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || - sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F4_DE || - sl->chip_id == STLINK_CHIPID_STM32_F4_LP || - sl->chip_id == STLINK_CHIPID_STM32_F4_HD || - sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || - sl->chip_id == STLINK_CHIPID_STM32_F410 || - sl->chip_id == STLINK_CHIPID_STM32_F411RE || - sl->chip_id == STLINK_CHIPID_STM32_F412 || - sl->chip_id == STLINK_CHIPID_STM32_F413 || - sl->chip_id == STLINK_CHIPID_STM32_F446 + } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || + sl->chip_id == STLINK_CHIPID_STM32_F4 || + sl->chip_id == STLINK_CHIPID_STM32_F4_DE || + sl->chip_id == STLINK_CHIPID_STM32_F4_LP || + sl->chip_id == STLINK_CHIPID_STM32_F4_HD || + sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || + sl->chip_id == STLINK_CHIPID_STM32_F410 || + sl->chip_id == STLINK_CHIPID_STM32_F411RE || + sl->chip_id == STLINK_CHIPID_STM32_F412 || + sl->chip_id == STLINK_CHIPID_STM32_F413 || + sl->chip_id == STLINK_CHIPID_STM32_F446 ) { int retval; retval = loader_v_dependent_assignment(sl, @@ -290,8 +295,8 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* if (retval == -1) { return retval; } - } else if (sl->core_id == STM32F7_CORE_ID || - sl->chip_id == STLINK_CHIPID_STM32_F7 || + } else if (sl->core_id == STM32F7_CORE_ID || + sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX || sl->chip_id == STLINK_CHIPID_STM32_F72XXX ) { @@ -303,7 +308,11 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* if (retval == -1) { return retval; } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || sl->chip_id == STLINK_CHIPID_STM32_F0_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F09X) { + } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || + sl->chip_id == STLINK_CHIPID_STM32_F04 || + sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || + sl->chip_id == STLINK_CHIPID_STM32_F0_SMALL || + sl->chip_id == STLINK_CHIPID_STM32_F09X) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || @@ -345,11 +354,13 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe return -1; } - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { count = size / sizeof(uint16_t); if (size % sizeof(uint16_t)) ++count; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4 || + sl->flash_type == STLINK_FLASH_TYPE_L0) { count = size / sizeof(uint32_t); if (size % sizeof(uint32_t)) ++count; From 6692fdc57cd087be84dbf831e85730cab58c7bf9 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 21 Feb 2020 00:50:50 +0100 Subject: [PATCH 0699/1435] Restored support for STM32-Clones -> CKS devices with Core ID 0x2ba01477 (Closes #756 #757 #761 #766 #769 #805) --- include/stm32.h | 1 + src/common.c | 5 ++++- src/flash_loader.c | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/include/stm32.h b/include/stm32.h index 8f8e7eba1..9fb3e45da 100644 --- a/include/stm32.h +++ b/include/stm32.h @@ -9,6 +9,7 @@ // cortex core ids #define STM32VL_CORE_ID 0x1ba01477 +#define CS32VL_CORE_ID 0x2ba01477 #define STM32F7_CORE_ID 0x5ba02477 // Constant STM32 memory map figures diff --git a/src/common.c b/src/common.c index bcce965aa..19155f774 100644 --- a/src/common.c +++ b/src/common.c @@ -2262,7 +2262,10 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t uint32_t flash_regs_base; uint32_t pagesize; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || sl->chip_id == STLINK_CHIPID_STM32_L011) { + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || + sl->chip_id == STLINK_CHIPID_STM32_L011) { flash_regs_base = STM32L0_FLASH_REGS_ADDR; pagesize = L0_WRITE_BLOCK_SIZE; } else { diff --git a/src/flash_loader.c b/src/flash_loader.c index 7479e05bb..1e125e926 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -267,6 +267,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || + sl->core_id == CS32VL_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_F3 || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL || From 751da606cac4882494bb6b764c2ad9619427eb48 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 21 Feb 2020 01:07:52 +0100 Subject: [PATCH 0700/1435] Merge branch 'pr-847/zx81a/master' into develop. --- debian/rules | 2 +- include/stm32.h | 3 + src/common.c | 191 +++++++++++++++++++++++++++++++++++++++++++++- src/tools/flash.c | 2 +- 4 files changed, 194 insertions(+), 4 deletions(-) diff --git a/debian/rules b/debian/rules index e228a7087..e183fffb7 100755 --- a/debian/rules +++ b/debian/rules @@ -1,7 +1,7 @@ #!/usr/bin/make -f # See debhelper(7) (uncomment to enable) # output every command that modifies files on the build system. -#DH_VERBOSE = 1 +DH_VERBOSE = 1 # see EXAMPLES in dpkg-buildflags(1) and read /usr/share/dpkg/* DPKG_EXPORT_BUILDFLAGS = 1 diff --git a/include/stm32.h b/include/stm32.h index 9fb3e45da..858d2b22a 100644 --- a/include/stm32.h +++ b/include/stm32.h @@ -18,4 +18,7 @@ #define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L0_CAT2_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) #define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) +#define STM32_L496X_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) +#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) + #endif /* STM32_H */ diff --git a/src/common.c b/src/common.c index 19155f774..73c8e51ad 100644 --- a/src/common.c +++ b/src/common.c @@ -160,6 +160,7 @@ //32L4 register base is at FLASH_REGS_ADDR (0x40022000) #define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) +#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) #define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) #define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) #define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) @@ -168,13 +169,16 @@ #define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */ #define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ #define STM32L4_FLASH_CR_PG 0 /* Program */ #define STM32L4_FLASH_CR_PER 1 /* Page erase */ #define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ #define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ #define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ #define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ #define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ // Bits requesting flash operations (useful when we want to clear them) #define STM32L4_FLASH_CR_OPBITS \ ((1lu<chip_id,addr); + /* Check if chip is supported and for correct address */ if(((sl->chip_id == STLINK_CHIPID_STM32_G0_CAT1) || (sl->chip_id == STLINK_CHIPID_STM32_G0_CAT2)) && (addr == STM32_G0_OPTION_BYTES_BASE)) { @@ -2933,8 +3113,15 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui else if((sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) && (addr == STM32_L0_CAT2_OPTION_BYTES_BASE)) { return stlink_write_option_bytes_l0_cat2(sl, base, len); } + else if((sl->chip_id == STLINK_CHIPID_STM32_L496X) && (addr == STM32_L496X_OPTION_BYTES_BASE)) { + return stlink_write_option_bytes_l496x(sl, base, len); + } + else if( ( (sl->chip_id == STLINK_CHIPID_STM32_L152_RE) || (sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH) ) + && ( (addr == STM32_L1_OPTION_BYTES_BASE) || (addr == STM32_L1_OPTION_BYTES_BASE+4) ) ) { + return stlink_write_option_bytes_l1(sl, base, addr, len); + } else { - ELOG("Option bytes writing is currently only supported for the STM32F2, STM32G0 and STM32L0\n"); + ELOG("Option bytes writing is currently only supported for the STM32F2, STM32G0, STM32L496x/L4A6x, STM32L1 and STM32L0\n"); return -1; } diff --git a/src/tools/flash.c b/src/tools/flash.c index f5fd1a386..1b63b1696 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -164,7 +164,7 @@ int main(int ac, char** av) goto on_error; } } - else if (o.addr == STM32_G0_OPTION_BYTES_BASE || o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE){ + else if (o.addr == STM32_G0_OPTION_BYTES_BASE || o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE || o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE + 4){ err = stlink_fwrite_option_bytes(sl, o.filename, o.addr); if (err == -1) { From 90997ed65b902e7f19523002feb84c43ec2d5b40 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 21 Feb 2020 02:22:19 +0100 Subject: [PATCH 0701/1435] Updated list with tested-boards. --- README.md | 2 +- doc/tested-boards.md | 56 ++++++++++++++++++++++++-------------------- 2 files changed, 31 insertions(+), 27 deletions(-) diff --git a/README.md b/README.md index 5d98f0e7e..c8955a521 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ Open source version of the STMicroelectronics Stlink Tools [![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/texane/stlink/releases/latest) [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) -[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/v1.6.0.svg)](https://github.com/texane/stlink/releases/master) +[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/v1.6.0.svg)](https://github.com/texane/stlink/releases/develop) [![Downloads](https://img.shields.io/github/downloads/texane/stlink/total.svg)](https://github.com/texane/stlink/releases) [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) diff --git a/doc/tested-boards.md b/doc/tested-boards.md index 27d09cc34..b28163a30 100644 --- a/doc/tested-boards.md +++ b/doc/tested-boards.md @@ -7,6 +7,7 @@ Known working targets: * STM32F100xx (Medium Density VL) * STM32F103 (according to jpa- on ##stm32) +* CKS32F103 (chinese STM32F103-Clone) No information: @@ -14,41 +15,44 @@ No information: STLink v2 (as found on the 32L and F4 Discovery boards), known working targets: -* STM32F030F4P6 (custom board) -* STM32F0Discovery (STM32F0 Discovery board) -* STM32F100xx (Medium Density VL, as on the 32VL Discovery board) -* STM32L1xx (STM32L Discovery board) +* STM32F0 (STM32F0 Discovery board) +* STM32F030F4P6 (custom board) +* STM32F051R8T6 (STM320518-EVAL board) +* STM32F100xx (Medium Density VL, as on the 32VL Discovery board) +* STM32F103VET6 (HY-STM32 board) +* STM32F105RCT6 (DecaWave EVB1000 board) +* STM32F303xx (STM32F3 Discovery board) +* STM32F407xx (STM32F4 Discovery board) +* STM32F411E-DISCO (STM32F4 Discovery board with gyro, audio) +* STM32F429I-DISCO (STM32F4 Discovery board with LCD) +* STM32F439VIT6 (Discovery board reseated CPU) +* STM32L052K8T6 (custom board) +* STM32L1xx (STM32L Discovery board) +* STM32L151CB (custom board) +* STM32L152RB (STM32L-Discovery board, custom board) +* STM32L496ZG (STM32-Nucleo-L496ZG board) + + * STM32F103VC, STM32F107RC, STM32L151RB, STM32F205RE and STM32F405RE on custom boards from [UweBonnes/wiki_fuer_alex](https://github.com/UweBonnes/wiki_fuer_alex/tree/master/layout) -* STM32F103VET6 (HY-STM32 board) -* STM32F105RCT6 (DecaWave EVB1000 board) -* STM32F303xx (STM32F3 Discovery board) -* STM32F407xx (STM32F4 Discovery board) -* STM32F429I-DISCO (STM32F4 Discovery board with LCD) -* STM32F439VIT6 (discovery board reseated CPU) -* STM32L052K8T6 (custom board) -* STM32L151CB (custom board) -* STM32L152RB (STM32L-Discovery board, custom board) -* STM32F051R8T6 (STM320518-EVAL board) -* STM32F411E-DISCO (STM32F4 Discovery board with gyro, audio) + STLink v2-1 (as found on the Nucleo boards), known working targets: -* STM32F401xx (STM32 Nucleo-F401RE board) * STM32F030R8T6 (STM32 Nucleo-F030R8 board) +* STM32F042K6 (STM32 Nucleo-32 Board) * STM32F072RBT6 (STM32 Nucleo-F072RB board) -* STM32F103RB (STM32 Nucleo-F103RB board) +* STM32F103RB (STM32 Nucleo-F103RB board) * STM32F303RET6 (STM32 Nucleo-F303RE board) -* STM32F334R8 (STM32 Nucleo-F334R8 board) +* STM32F334R8 (STM32 Nucleo-F334R8 board) +* STM32F401xx (STM32 Nucleo-F401RE board) * STM32F411RET6 (STM32 Nucleo-F411RE board) -* STM32F756NGHx (STMF7 evaluation board) -* STM32L053R8 (STM32 Nucleo-L053R8 board) -* STM32F769NI (STM32F7 discovery board) -* Nucleo-L152RE board -* [Nucleo-L476RG board](http://www.st.com/en/evaluation-tools/nucleo-l476rg.html) +* STM32F756NGHx (STM32F7 evaluation board) +* STM32F769NI (STM32F7 discovery board) +* STM32L053R8 (STM32 Nucleo-L053R8 board) +* STM32L152RE (STM32-Nucleo-L152RE board * STM32L452RET6 (STM32 Nucleo-L452RE board) -* STM32F042K6 (STM32 Nucleo-32 Board) - -Please report any and all known working combinations so I can update this! +* STM32L476RG (STM32 Nucleo-L476RG board) +Please report any and all known working combinations so I can update this! From 7c0ebda0b514fb4c707205259ab221bd90f4cf78 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 21 Feb 2020 02:38:56 +0100 Subject: [PATCH 0702/1435] Improved support for STM32G0xx series. Fix for (#850 #857) (identical to #825) --- src/chipid.c | 6 +++--- src/common.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/chipid.c b/src/chipid.c index ebb5a9027..df07d524f 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -522,9 +522,9 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x2000 }, { - // STM32G031/041 (from RM0444) + // STM32GG030/031/041 (from RM0444) .chip_id = STLINK_CHIPID_STM32_G0_CAT1, - .description = "G031/G041 device", + .description = "G030/G031/G041 device", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2K (sec 3.2) @@ -535,7 +535,7 @@ static const struct stlink_chipid_params devices[] = { { // STM32G071/081 (from RM0444) .chip_id = STLINK_CHIPID_STM32_G0_CAT2, - .description = "G071/G081 device", + .description = "G070/G071/G081 device", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2K (sec 3.2) diff --git a/src/common.c b/src/common.c index 73c8e51ad..018e01c4c 100644 --- a/src/common.c +++ b/src/common.c @@ -2617,7 +2617,7 @@ static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t l uint32_t val; if(len != 4) { - ELOG("Wrong length for writting option bytes, must be 4 is %d\n", len); + ELOG("Wrong length for writing option bytes, must be 4 is %d\n", len); return -1; } @@ -2811,7 +2811,7 @@ static int stlink_write_option_bytes_l1(stlink_t *sl, uint8_t* base, stm32_addr_ if( data != val ) { WLOG("Writing option bytes 0x%04x\n", data); stlink_write_debug32(sl, addr, data); - + stlink_read_debug32(sl, addr, &val); WLOG("Option bytes is 0x%08x\n",val); } @@ -2829,11 +2829,11 @@ static int stlink_write_option_bytes_l1(stlink_t *sl, uint8_t* base, stm32_addr_ if( data != val ) { WLOG("Writing 2nd option bytes 0x%04x\n", data); stlink_write_debug32(sl, addr+4, data); - + stlink_read_debug32(sl, addr+4, &val); WLOG("2nd option bytes is 0x%08x\n",val); } - } + } /* Reload options */ stlink_read_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); @@ -3116,7 +3116,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui else if((sl->chip_id == STLINK_CHIPID_STM32_L496X) && (addr == STM32_L496X_OPTION_BYTES_BASE)) { return stlink_write_option_bytes_l496x(sl, base, len); } - else if( ( (sl->chip_id == STLINK_CHIPID_STM32_L152_RE) || (sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH) ) + else if( ( (sl->chip_id == STLINK_CHIPID_STM32_L152_RE) || (sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH) ) && ( (addr == STM32_L1_OPTION_BYTES_BASE) || (addr == STM32_L1_OPTION_BYTES_BASE+4) ) ) { return stlink_write_option_bytes_l1(sl, base, addr, len); } From 5a5c3d71d7568070bc108e7501ff977ad94d653c Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Fri, 21 Feb 2020 06:53:28 +0200 Subject: [PATCH 0703/1435] --- --- src/common.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/src/common.c b/src/common.c index bef3a5e3d..018e01c4c 100644 --- a/src/common.c +++ b/src/common.c @@ -2631,15 +2631,6 @@ static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t l return -1; } - // Make sure we've loaded the context with the chip details - stlink_core_id(sl); - - /* Check if chip is supported and for correct address */ - if((sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2 && sl->chip_id != STLINK_CHIPID_STM32_G0_CAT1) || (addr != STM32_G0_OPTION_BYTES_BASE)) { - ELOG("Option bytes writing is currently only supported for the STM32G0\n"); - return -1; - } - /* Unlock flash if necessary (ref manuel page 52) */ stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); if ((val & (1u << STM32Gx_FLASH_CR_LOCK))) { From d312ca267f33ddbe055d36e8a2cf74a123de4174 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 21 Feb 2020 17:51:22 +0100 Subject: [PATCH 0704/1435] Updated CHANGELOG.md for Release v1.5.1 --- CHANGELOG.md | 32 +++++++++++++++++++++----------- 1 file changed, 21 insertions(+), 11 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 20d242a1a..f122e77ec 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -26,7 +26,7 @@ Major changes and added features: Updates and fixes: -* Make udev rules and modprobe conf installation optional ([#741](https://github.com/texane/stlink/pull/741)) +* Made udev rules and modprobe conf installation optional ([#741](https://github.com/texane/stlink/pull/741)) * Fixed case when __FILE__ don't contain "/" nor "\\". ([#745](https://github.com/texane/stlink/pull/745)) * Fixed double dash issue in doc/man ([#746](https://github.com/texane/stlink/pull/746)) * Fixed Debug error on line 123 in CMakeLists.txt (@xor-gate) @@ -59,19 +59,29 @@ Release date: 2018-09-13 Major changes and added features: -* Implemented intel hex support for GTK GUI -* Updated libusb to 1.0.22 -* Added memory map for STM32F411RE target -* Add support for STM32L4R9 target +* Added button to export stm32 flash memory to a file ([#691](https://github.com/texane/stlink/pull/691)) +* Updated libusb to 1.0.22 ([#695](https://github.com/texane/stlink/pull/695)) +* Added desktop file for linux ([#688](https://github.com/texane/stlink/pull/688)) +* Added icons for stlink GUI ([#697](https://github.com/texane/stlink/pull/697)) +* Added support for STM32L4R9 target ([#694](https://github.com/texane/stlink/pull/694), [#699](https://github.com/texane/stlink/pull/699) +* Added creation of icons for .desktop file ([#708](https://github.com/texane/stlink/pull/708)) +* Added memory map for STM32F411RE target ([#709](https://github.com/texane/stlink/pull/709)) +* Added reset through AIRCR ([#540](https://github.com/texane/stlink/pull/540), [#712](https://github.com/texane/stlink/pull/712) +* Implemented intel hex support for GTK GUI ([#718](https://github.com/texane/stlink/pull/718)) Fixes: -* FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION -* Proper flash page size calculation for F412 target -* Fixed flash memory map for F72xxx target -* Return correct value on EOF for Semihosting SYS_READ - -For a complete list of changes see [the milestone](https://github.com/texane/stlink/milestone/6?closed=1) +* Fixed missing flash_loader for L011 ([#675](https://github.com/texane/stlink/pull/675)) +* Fixed serial number size mismatch with stlink_open_usb() ([#680](https://github.com/texane/stlink/pull/680)) +* Debian packaging, CMake and README.md fixes ([#683](https://github.com/texane/stlink/pull/683)) +* Fix for stlink library calls exit() or _exit() ([#634](https://github.com/texane/stlink/pull/634), [#696](https://github.com/texane/stlink/pull/696) +* Fix for libusb deprecation ([#703](https://github.com/texane/stlink/pull/703), [#704](https://github.com/texane/stlink/pull/704) +* Renamed STLINK_CHIPID_STM32_L4R9 to STLINK_CHIPID_STM32_L4RX ([#706](https://github.com/texane/stlink/pull/706)) +* Fixed flash memory map for F72XXX target ([#711](https://github.com/texane/stlink/pull/711)) +* Proper flash page size calculation for F412 target ([#721](https://github.com/texane/stlink/pull/721)) +* Return correct value on EOF for Semihosting SYS_READ ([#725](https://github.com/texane/stlink/pull/725), [#726](https://github.com/texane/stlink/pull/726, [#729](https://github.com/texane/stlink/pull/729, [#731](https://github.com/texane/stlink/pull/731) +* Fix for mem_write() ([#730](https://github.com/texane/stlink/pull/730)) +* FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION ([#733](https://github.com/texane/stlink/pull/733)) v1.5.0 ====== From e06daedccfdf043191821d9fbf8d1664542912de Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 21 Feb 2020 22:51:29 +0100 Subject: [PATCH 0705/1435] Minor corrections in CHANGELOG.md --- CHANGELOG.md | 6 +++--- src/flash_loader.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 20d242a1a..213d26358 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -10,9 +10,9 @@ Major changes and added features: * Added O_BINARY option to open file ([#753](https://github.com/texane/stlink/pull/753)) * Added preliminary support for some STM32G0 chips ([#759](https://github.com/texane/stlink/pull/759)) ([#760](https://github.com/texane/stlink/pull/760)) -* Added support for mass erasing second bank on STM32F10x_XL ([#767](https://github.com/texane/stlink/pull/767)) +* Added support for mass erasing second bank on STM32F10x_XL ([#767](https://github.com/texane/stlink/pull/767), [#768](https://github.com/texane/stlink/pull/768)) * Added call to clear PG bit after writing to flash ([#773](https://github.com/texane/stlink/pull/773)) -* Added howto for sending NRST signal through GDB ([#776](https://github.com/texane/stlink/pull/776)) +* Added howto for sending NRST signal through GDB ([#774](https://github.com/texane/stlink/pull/774), [#776](https://github.com/texane/stlink/pull/776)) * Added support to write option bytes for the STM32G0 ([#778](https://github.com/texane/stlink/pull/778)) * Added simple read/write support for STM32WB55 chips ([#786](https://github.com/texane/stlink/pull/786)) * Added STLink V3SET VID:PIDs to the udev rules ([#789](https://github.com/texane/stlink/pull/789)) @@ -35,7 +35,7 @@ Updates and fixes: * Fixed versioning when compiling from the checked out git-repo ([#762](https://github.com/texane/stlink/pull/762)) * Fixed "unkown chip id", piped output and st-util -v ([#763](https://github.com/texane/stlink/pull/763)) * win32: move usleep definition to unistd.h ([#765](https://github.com/texane/stlink/pull/765)) -* Fixed relative path to the UI files needed by stlink-gui-local (GUI) ([#771](https://github.com/texane/stlink/pull/771)) +* Fixed relative path to the UI files needed by stlink-gui-local (GUI) ([#770](https://github.com/texane/stlink/pull/770), [#771](https://github.com/texane/stlink/pull/771)) * Fixed package name "devscripts" in doc/compiling.md ([#775](https://github.com/texane/stlink/pull/775)) * Fixed apparent STM32G0 flashing issue ([#797](https://github.com/texane/stlink/pull/797)) * Fixed few potential memory/resource leaks ([#803](https://github.com/texane/stlink/pull/803)) diff --git a/src/flash_loader.c b/src/flash_loader.c index 1e125e926..9f6e3a79d 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -317,11 +317,11 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L41X) || - (sl->chip_id == STLINK_CHIPID_STM32_L43X) || - (sl->chip_id == STLINK_CHIPID_STM32_L46X) || - (sl->chip_id == STLINK_CHIPID_STM32_L4RX) || - (sl->chip_id == STLINK_CHIPID_STM32_L496X)) + (sl->chip_id == STLINK_CHIPID_STM32_L41X) || + (sl->chip_id == STLINK_CHIPID_STM32_L43X) || + (sl->chip_id == STLINK_CHIPID_STM32_L46X) || + (sl->chip_id == STLINK_CHIPID_STM32_L4RX) || + (sl->chip_id == STLINK_CHIPID_STM32_L496X)) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); From ee20ab091e9c4b81b6b0ef74d5c6bbf88fe7353d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 22 Feb 2020 01:24:49 +0100 Subject: [PATCH 0706/1435] Updated README.md --- README.md | 203 ++++++++++++++++++++++++++++-------------------------- 1 file changed, 104 insertions(+), 99 deletions(-) diff --git a/README.md b/README.md index 5d98f0e7e..594e0fae9 100644 --- a/README.md +++ b/README.md @@ -1,18 +1,21 @@ Open source version of the STMicroelectronics Stlink Tools ========================================================== -[![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/texane/stlink/releases/latest) [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) +[![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/texane/stlink/releases/latest) [![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/v1.6.0.svg)](https://github.com/texane/stlink/releases/master) [![Downloads](https://img.shields.io/github/downloads/texane/stlink/total.svg)](https://github.com/texane/stlink/releases) - [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) [![macOS Status](https://img.shields.io/travis/texane/stlink/master.svg?label=osx)](https://travis-ci.org/texane/stlink) +Recent new features and bugfixes can be found in the [Changelog](CHANGELOG.md) of this software project. + + +## Introduction -## HOWTO +This stlink toolset supports several so called stlink programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG. -This stlink toolset supports several so called stlink programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG. These programmer boards are available in four versions: +These programmer boards are available in four versions: * **STLINKv1:** - transport layer: SCSI passthru commands over USB @@ -24,39 +27,122 @@ This stlink toolset supports several so called stlink programmer boards (and clo * transport layer: raw USB commands * present on some STM32 nucleo boards * **STLINKv3:** - * _currently not supported by this toolset_ + * _not yet supported by this toolset (but planned)_ + + +## Supported hardware combinations + +Currently known working combinations of programmers and targets are listed in [doc/tested-boards.md](doc/tested-boards.md). ## Installation -Windows users can [download v1.3.0](https://github.com/texane/stlink/releases/tag/1.3.0) from the releases page. +**Windows**: download [v1.6.0](https://github.com/texane/stlink/releases/tag/v1.6.0) from the releases page. + +**macOS**: install [from homebrew](http://brewformulas.org/Stlink) or download [v1.6.0](https://github.com/texane/stlink/releases/tag/v1.6.0) from the releases page. -Mac OS X users can install from [homebrew](http://brewformulas.org/Stlink) or [download v1.3.0](https://github.com/texane/stlink/releases/tag/1.3.0) from the releases page. +**Linux**: -Debian Linux users can install it via the ```stlink-tools``` package [repository](https://packages.debian.org/buster/stlink-tools) +We recommend to install `stlink-tools` from the package repository of the used distribution: -Ubuntu Linux users can install it via the ```stlink-tools``` package [repository](https://packages.ubuntu.com/stlink-tools) +* Debian Linux: [(Link)](https://packages.debian.org/buster/stlink-tools) +* Ubuntu Linux: [(Link)](https://packages.ubuntu.com/stlink-tools) +* Arch Linux: [(Link)](https://www.archlinux.org/packages/community/x86_64/stlink) +* Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) +* Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) +* Gentoo Linux: [(Link)](https://packages.gentoo.org/packages/dev-embedded/stlink) -Arch Linux users can install from the [repository](https://www.archlinux.org/packages/community/x86_64/stlink) +**Other Operating Systems**: -Alpine Linux users can install from the [repository](https://pkgs.alpinelinux.org/packages?name=stlink) +* RedHat/CentOS 7: Users can install [from EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel7) +* FreeBSD: Users can install [from freshports](https://www.freshports.org/devel/stlink) +* OpenBSD: Users need to install [from source](doc/compiling.md). -Fedora users can install from [repository](https://src.fedoraproject.org/rpms/stlink) -RedHat/CentOS 7 users can install from EPEL [repository](https://src.fedoraproject.org/rpms/stlink/branch/epel7) +## Installation from source (advanced users) -Gentoo Linux users can install from the official portage [repository](https://packages.gentoo.org/packages/dev-embedded/stlink) +When there is no executable available for your platform or you need the latest (possible unstable) version you need to compile the toolset yourself. This procedure is explained in the [compiling manual](doc/compiling.md). -FreeBSD users can install from [freshports](https://www.freshports.org/devel/stlink) -OpenBSD users need to install [from source](doc/compiling.md). +## Contributing and versioning +* The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) +* Before creating a pull request, please _ALWAYS_ open a new issue for the discussion of the intended new features. Bugfixes don't require a discussion via a ticket-issue. However they should always be described in a few words as soon as they appear to help others as well. +* Contributors and/or maintainers may submit comments or request changes to patch-proposals and/or pull-requests. -## Installation from source (advanced users) -When there is no executable available for your platform or you need the latest (possible unstable) version you need to compile yourself. This is explained in the [compiling manual](doc/compiling.md). +## License + +The stlink library and tools are licensed under the [BSD license](LICENSE.md). + +The flashloaders/stm32l0x.s and flashloaders/stm32lx.s source files are licensed under the GPLv2+. +# Current state of the project + +## Known missing features + +Some features are currently missing from the `texane/stlink` toolset. +Here we would appreciate any help and would love to welcome new contributors who want to get involved: + +* Instrumentation Trace Macro (ITM) Cell ([#136](https://github.com/texane/stlink/issues/136)) +* OTP area programming ([#202](https://github.com/texane/stlink/issues/202)) +* EEPROM area programming ([#318](https://github.com/texane/stlink/issues/218)) +* Protection bits area reading ([#346](https://github.com/texane/stlink/issues/346)) +* Writing external memory connected to an STM32 controller (e.g Quad SPI NOR flash) ([#412](https://github.com/texane/stlink/issues/412)) +* MCU hotplug ([#449](https://github.com/texane/stlink/issues/449)) +* Writing options bytes (region) ([#458](https://github.com/texane/stlink/issues/458)) +* Control programming speed ([#462](https://github.com/texane/stlink/issues/462)) +* Support for STLINKv3 programmer ([#820](https://github.com/texane/stlink/issues/820)) + + +## Known bugs +### Sometimes flashing only works after a mass erase + +There is seen a problem sometimes where a flash loader run error occurs and is resolved after mass-erase of the flash: + +``` +2015-12-09T22:01:57 INFO src/stlink-common.c: Successfully loaded flash loader in sram +2015-12-09T22:02:18 ERROR src/stlink-common.c: flash loader run error +2015-12-09T22:02:18 ERROR src/stlink-common.c: run_flash_loader(0x8000000) failed! == -1 +``` + +Issue related to this bug: [#356](https://github.com/texane/stlink/issues/356) + + +### Flash size is detected as zero bytes size + +It is possible that the STM32 flash is write protected, the st-flash tool will show something like this: + +``` +st-flash write prog.bin 0x8000000 +2017-01-24T18:44:14 INFO src/stlink-common.c: Loading device parameters.... +2017-01-24T18:44:14 INFO src/stlink-common.c: Device connected is: F1 High-density device, id 0x10036414 +2017-01-24T18:44:14 INFO src/stlink-common.c: SRAM size: 0x10000 bytes (64 KiB), Flash: 0 bytes (0 KiB) in pages of 2048 bytes +``` + +As you can see, it gives out something unexpected like +``` +Flash: 0 bytes (0 KiB) in pages of 2048 bytes +``` + +``` +st-info --probe +Found 1 stlink programmers + serial: 303030303030303030303031 +openocd: "\x30\x30\x30\x30\x30\x30\x30\x30\x30\x30\x30\x31" + flash: 0 (pagesize: 2048) + sram: 65536 + chipid: 0x0414 + descr: F1 High-density device +``` + +Try to remove the write protection (probably only possible with ST Link Utility from ST itself). + +Issue related to this bug: [#545](https://github.com/texane/stlink/issues/545) + + +# HOWTO ## Using the gdb server To run the gdb server: @@ -177,84 +263,3 @@ A: Sometimes when you will try to use GDB `next` command to skip a loop, it will Q: Load command does not work in GDB. A: Some people report XML/EXPAT is not enabled by default when compiling GDB. Memory map parsing thus fail. Use --enable-expat. - - -## Currently known working combinations of programmer and target - -See [doc/tested-boards.md](doc/tested-boards.md) - -## Changelog - -The [Changelog](CHANGELOG.md) for the StLink Tools. - - -## Known missing features - -Some features are missing from the `texane/stlink` project and we would like you to help us out if you want to get involved: - -* Control programming speed (See [#462](https://github.com/texane/stlink/issues/462)) -* OTP area programming (See [#202](https://github.com/texane/stlink/issues/202)) -* EEPROM area programming (See [#318](https://github.com/texane/stlink/issues/218)) -* Protection bits area reading (See [#346](https://github.com/texane/stlink/issues/346)) -* MCU hotplug (See [#449](https://github.com/texane/stlink/issues/449)) -* Writing options bytes (region) (See [#458](https://github.com/texane/stlink/issues/458)) -* Instrumentation Trace Macro (ITM) Cell (See [#136](https://github.com/texane/stlink/issues/136)) -* Writing external memory connected to an STM32 controller (e.g Quad SPI NOR flash) (See [#412](https://github.com/texane/stlink/issues/412)) - - -## Known bugs -### Sometimes flashing only works after a mass erase - -There is seen a problem sometimes where a flash loader run error occurs and is resolved after mass-erase of the flash: - -``` -2015-12-09T22:01:57 INFO src/stlink-common.c: Successfully loaded flash loader in sram -2015-12-09T22:02:18 ERROR src/stlink-common.c: flash loader run error -2015-12-09T22:02:18 ERROR src/stlink-common.c: run_flash_loader(0x8000000) failed! == -1 -``` - -Issue related to this bug: [#356](https://github.com/texane/stlink/issues/356) - - -### Flash size is detected as zero bytes size - -It is possible that the STM32 flash is write protected, the st-flash tool will show something like this: - -``` -st-flash write prog.bin 0x8000000 -2017-01-24T18:44:14 INFO src/stlink-common.c: Loading device parameters.... -2017-01-24T18:44:14 INFO src/stlink-common.c: Device connected is: F1 High-density device, id 0x10036414 -2017-01-24T18:44:14 INFO src/stlink-common.c: SRAM size: 0x10000 bytes (64 KiB), Flash: 0 bytes (0 KiB) in pages of 2048 bytes -``` - -As you can see, it gives out something unexpected like -``` -Flash: 0 bytes (0 KiB) in pages of 2048 bytes -``` - -``` -st-info --probe -Found 1 stlink programmers - serial: 303030303030303030303031 -openocd: "\x30\x30\x30\x30\x30\x30\x30\x30\x30\x30\x30\x31" - flash: 0 (pagesize: 2048) - sram: 65536 - chipid: 0x0414 - descr: F1 High-density device -``` - -Try to remove the write protection (probably only possible with ST Link Utility from ST itself). - -Issue related to this bug: [#545](https://github.com/texane/stlink/issues/545) - - -## Contributing and versioning - -* The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) -* When creating a pull request, please open first a issue for discussion of new features. Bugfixes don't need a discussion. - -## License - -The stlink library and tools are licensed under the [BSD license](LICENSE.md). - -The flashloaders/stm32l0x.s and flashloaders/stm32lx.s source files are licensed under the GPLv2+. From afaded2782ca193841198a5451b2bec89998a7e3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 22 Feb 2020 17:50:31 +0100 Subject: [PATCH 0707/1435] General Project Update - Formatting fixes in CHANGELOG.md - Added comment in .travis.sh - Update for .travis.yml: gcc/g++ v5->v6 --- .travis.sh | 2 +- .travis.yml | 13 ++++++++----- CHANGELOG.md | 14 +++++++------- 3 files changed, 16 insertions(+), 13 deletions(-) diff --git a/.travis.sh b/.travis.sh index 06e95ef80..05568d37d 100755 --- a/.travis.sh +++ b/.travis.sh @@ -8,7 +8,7 @@ echo "----" if [ "$TRAVIS_OS_NAME" == "linux" ]; then sudo apt-get update -qq || true sudo apt-get install -qq -y --no-install-recommends libgtk-3-dev -else +else #("$TRAVIS_OS_NAME" == "osx") brew install libusb fi diff --git a/.travis.yml b/.travis.yml index c878be799..b0f985012 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,21 +1,24 @@ -language: c + compiler: - gcc - clang + +language: c + os: - linux - osx + addons: apt: sources: -# - llvm-toolchain-precise-3.8 - sourceline: 'ppa:ubuntu-toolchain-r/test' packages: - clang -# - clang-3.8 - - g++-5 - - gcc-5 + - g++-6 + - gcc-6 - libusb-1.0.0-dev + script: - git fetch --tags - printenv diff --git a/CHANGELOG.md b/CHANGELOG.md index f122e77ec..25abd0a54 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -9,7 +9,7 @@ Release date: 2020-02-20 Major changes and added features: * Added O_BINARY option to open file ([#753](https://github.com/texane/stlink/pull/753)) -* Added preliminary support for some STM32G0 chips ([#759](https://github.com/texane/stlink/pull/759)) ([#760](https://github.com/texane/stlink/pull/760)) +* Added preliminary support for some STM32G0 chips ([#759](https://github.com/texane/stlink/pull/759), [#760](https://github.com/texane/stlink/pull/760)) * Added support for mass erasing second bank on STM32F10x_XL ([#767](https://github.com/texane/stlink/pull/767)) * Added call to clear PG bit after writing to flash ([#773](https://github.com/texane/stlink/pull/773)) * Added howto for sending NRST signal through GDB ([#776](https://github.com/texane/stlink/pull/776)) @@ -39,7 +39,7 @@ Updates and fixes: * Fixed package name "devscripts" in doc/compiling.md ([#775](https://github.com/texane/stlink/pull/775)) * Fixed apparent STM32G0 flashing issue ([#797](https://github.com/texane/stlink/pull/797)) * Fixed few potential memory/resource leaks ([#803](https://github.com/texane/stlink/pull/803)) -* Fixed flash verification error on STM32WB55RG ([#810](https://github.com/texane/stlink/pull/810)) ([#816](https://github.com/texane/stlink/pull/816)) +* Fixed flash verification error on STM32WB55RG ([#810](https://github.com/texane/stlink/pull/810), [#816](https://github.com/texane/stlink/pull/816)) * Do not issue JTAG reset on stlink-v1 (Gwenhael Goavec-Merou) * Fixed flash size of STM32 Discovery vl (Gwenhael Goavec-Merou) * Added support for writing option bytes on STM32L0 (Adrian Imboden) @@ -63,10 +63,10 @@ Major changes and added features: * Updated libusb to 1.0.22 ([#695](https://github.com/texane/stlink/pull/695)) * Added desktop file for linux ([#688](https://github.com/texane/stlink/pull/688)) * Added icons for stlink GUI ([#697](https://github.com/texane/stlink/pull/697)) -* Added support for STM32L4R9 target ([#694](https://github.com/texane/stlink/pull/694), [#699](https://github.com/texane/stlink/pull/699) +* Added support for STM32L4R9 target ([#694](https://github.com/texane/stlink/pull/694), [#699](https://github.com/texane/stlink/pull/699)) * Added creation of icons for .desktop file ([#708](https://github.com/texane/stlink/pull/708)) * Added memory map for STM32F411RE target ([#709](https://github.com/texane/stlink/pull/709)) -* Added reset through AIRCR ([#540](https://github.com/texane/stlink/pull/540), [#712](https://github.com/texane/stlink/pull/712) +* Added reset through AIRCR ([#540](https://github.com/texane/stlink/pull/540), [#712](https://github.com/texane/stlink/pull/712)) * Implemented intel hex support for GTK GUI ([#718](https://github.com/texane/stlink/pull/718)) Fixes: @@ -74,12 +74,12 @@ Fixes: * Fixed missing flash_loader for L011 ([#675](https://github.com/texane/stlink/pull/675)) * Fixed serial number size mismatch with stlink_open_usb() ([#680](https://github.com/texane/stlink/pull/680)) * Debian packaging, CMake and README.md fixes ([#683](https://github.com/texane/stlink/pull/683)) -* Fix for stlink library calls exit() or _exit() ([#634](https://github.com/texane/stlink/pull/634), [#696](https://github.com/texane/stlink/pull/696) -* Fix for libusb deprecation ([#703](https://github.com/texane/stlink/pull/703), [#704](https://github.com/texane/stlink/pull/704) +* Fix for stlink library calls exit() or _exit() ([#634](https://github.com/texane/stlink/pull/634), [#696](https://github.com/texane/stlink/pull/696)) +* Fix for libusb deprecation ([#703](https://github.com/texane/stlink/pull/703), [#704](https://github.com/texane/stlink/pull/704)) * Renamed STLINK_CHIPID_STM32_L4R9 to STLINK_CHIPID_STM32_L4RX ([#706](https://github.com/texane/stlink/pull/706)) * Fixed flash memory map for F72XXX target ([#711](https://github.com/texane/stlink/pull/711)) * Proper flash page size calculation for F412 target ([#721](https://github.com/texane/stlink/pull/721)) -* Return correct value on EOF for Semihosting SYS_READ ([#725](https://github.com/texane/stlink/pull/725), [#726](https://github.com/texane/stlink/pull/726, [#729](https://github.com/texane/stlink/pull/729, [#731](https://github.com/texane/stlink/pull/731) +* Return correct value on EOF for Semihosting SYS_READ ([#725](https://github.com/texane/stlink/pull/725), [#726](https://github.com/texane/stlink/pull/726), [#729](https://github.com/texane/stlink/pull/729), [#731](https://github.com/texane/stlink/pull/731)) * Fix for mem_write() ([#730](https://github.com/texane/stlink/pull/730)) * FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION ([#733](https://github.com/texane/stlink/pull/733)) From 3af8048356f3b4663750aa35dda53829846b6df3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 23 Feb 2020 03:08:08 +0100 Subject: [PATCH 0708/1435] General Project Update - Corrected CHANGELOG.md - Added comment in .travis.sh - Update for .travis.yml: gcc/g++ v5->v6 --- .travis.sh | 2 +- .travis.yml | 13 ++++++++----- CHANGELOG.md | 14 +++++++------- stlinkv1_macosx_driver/README.md | 18 ++++++------------ 4 files changed, 22 insertions(+), 25 deletions(-) diff --git a/.travis.sh b/.travis.sh index 06e95ef80..05568d37d 100755 --- a/.travis.sh +++ b/.travis.sh @@ -8,7 +8,7 @@ echo "----" if [ "$TRAVIS_OS_NAME" == "linux" ]; then sudo apt-get update -qq || true sudo apt-get install -qq -y --no-install-recommends libgtk-3-dev -else +else #("$TRAVIS_OS_NAME" == "osx") brew install libusb fi diff --git a/.travis.yml b/.travis.yml index c878be799..b0f985012 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,21 +1,24 @@ -language: c + compiler: - gcc - clang + +language: c + os: - linux - osx + addons: apt: sources: -# - llvm-toolchain-precise-3.8 - sourceline: 'ppa:ubuntu-toolchain-r/test' packages: - clang -# - clang-3.8 - - g++-5 - - gcc-5 + - g++-6 + - gcc-6 - libusb-1.0.0-dev + script: - git fetch --tags - printenv diff --git a/CHANGELOG.md b/CHANGELOG.md index f122e77ec..ba4c46d08 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -9,7 +9,7 @@ Release date: 2020-02-20 Major changes and added features: * Added O_BINARY option to open file ([#753](https://github.com/texane/stlink/pull/753)) -* Added preliminary support for some STM32G0 chips ([#759](https://github.com/texane/stlink/pull/759)) ([#760](https://github.com/texane/stlink/pull/760)) +* Added preliminary support for some STM32G0 chips ([#759](https://github.com/texane/stlink/pull/759), [#760](https://github.com/texane/stlink/pull/760)) * Added support for mass erasing second bank on STM32F10x_XL ([#767](https://github.com/texane/stlink/pull/767)) * Added call to clear PG bit after writing to flash ([#773](https://github.com/texane/stlink/pull/773)) * Added howto for sending NRST signal through GDB ([#776](https://github.com/texane/stlink/pull/776)) @@ -39,7 +39,7 @@ Updates and fixes: * Fixed package name "devscripts" in doc/compiling.md ([#775](https://github.com/texane/stlink/pull/775)) * Fixed apparent STM32G0 flashing issue ([#797](https://github.com/texane/stlink/pull/797)) * Fixed few potential memory/resource leaks ([#803](https://github.com/texane/stlink/pull/803)) -* Fixed flash verification error on STM32WB55RG ([#810](https://github.com/texane/stlink/pull/810)) ([#816](https://github.com/texane/stlink/pull/816)) +* Fixed flash verification error on STM32WB55RG ([#810](https://github.com/texane/stlink/pull/810), [#816](https://github.com/texane/stlink/pull/816)) * Do not issue JTAG reset on stlink-v1 (Gwenhael Goavec-Merou) * Fixed flash size of STM32 Discovery vl (Gwenhael Goavec-Merou) * Added support for writing option bytes on STM32L0 (Adrian Imboden) @@ -63,10 +63,10 @@ Major changes and added features: * Updated libusb to 1.0.22 ([#695](https://github.com/texane/stlink/pull/695)) * Added desktop file for linux ([#688](https://github.com/texane/stlink/pull/688)) * Added icons for stlink GUI ([#697](https://github.com/texane/stlink/pull/697)) -* Added support for STM32L4R9 target ([#694](https://github.com/texane/stlink/pull/694), [#699](https://github.com/texane/stlink/pull/699) +* Added support for STM32L4R9 target ([#694](https://github.com/texane/stlink/pull/694), [#699](https://github.com/texane/stlink/pull/699)) * Added creation of icons for .desktop file ([#708](https://github.com/texane/stlink/pull/708)) * Added memory map for STM32F411RE target ([#709](https://github.com/texane/stlink/pull/709)) -* Added reset through AIRCR ([#540](https://github.com/texane/stlink/pull/540), [#712](https://github.com/texane/stlink/pull/712) +* Added reset through AIRCR ([#540](https://github.com/texane/stlink/pull/540), [#712](https://github.com/texane/stlink/pull/712)) * Implemented intel hex support for GTK GUI ([#718](https://github.com/texane/stlink/pull/718)) Fixes: @@ -74,12 +74,12 @@ Fixes: * Fixed missing flash_loader for L011 ([#675](https://github.com/texane/stlink/pull/675)) * Fixed serial number size mismatch with stlink_open_usb() ([#680](https://github.com/texane/stlink/pull/680)) * Debian packaging, CMake and README.md fixes ([#683](https://github.com/texane/stlink/pull/683)) -* Fix for stlink library calls exit() or _exit() ([#634](https://github.com/texane/stlink/pull/634), [#696](https://github.com/texane/stlink/pull/696) -* Fix for libusb deprecation ([#703](https://github.com/texane/stlink/pull/703), [#704](https://github.com/texane/stlink/pull/704) +* Fix for stlink library calls exit() or _exit() ([#634](https://github.com/texane/stlink/pull/634), [#696](https://github.com/texane/stlink/pull/696)) +* Fix for libusb deprecation ([#703](https://github.com/texane/stlink/pull/703), [#704](https://github.com/texane/stlink/pull/704)) * Renamed STLINK_CHIPID_STM32_L4R9 to STLINK_CHIPID_STM32_L4RX ([#706](https://github.com/texane/stlink/pull/706)) * Fixed flash memory map for F72XXX target ([#711](https://github.com/texane/stlink/pull/711)) * Proper flash page size calculation for F412 target ([#721](https://github.com/texane/stlink/pull/721)) -* Return correct value on EOF for Semihosting SYS_READ ([#725](https://github.com/texane/stlink/pull/725), [#726](https://github.com/texane/stlink/pull/726, [#729](https://github.com/texane/stlink/pull/729, [#731](https://github.com/texane/stlink/pull/731) +* Return correct value on EOF for Semihosting SYS_READ ([#726](https://github.com/texane/stlink/pull/726), [#729](https://github.com/texane/stlink/pull/729), [#731](https://github.com/texane/stlink/pull/731)) * Fix for mem_write() ([#730](https://github.com/texane/stlink/pull/730)) * FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION ([#733](https://github.com/texane/stlink/pull/733)) diff --git a/stlinkv1_macosx_driver/README.md b/stlinkv1_macosx_driver/README.md index 4e6b8c6a0..b2a68442c 100644 --- a/stlinkv1_macosx_driver/README.md +++ b/stlinkv1_macosx_driver/README.md @@ -4,18 +4,14 @@ to: texane@gmail.com Hi, -i managed to get the stlink v1 working under os x and i would like to share the solution so maybe you can -add it in your package. +i managed to get the stlink v1 working under os x and i would like to share the solution so maybe you can add it in your package. The problem is that os x claims the device as scsi and libusb won't be able to connect to it. -I've created what is called a codeless driver which claims the device and has a higher priority then the -default apple mass storage driver, so the device can be accessed through libusb. +I've created what is called a codeless driver which claims the device and has a higher priority then the default apple mass storage driver, so the device can be accessed through libusb. -I tested this codeless driver under OS X 10.6.8 and 10.7.2. I assume it works with any 10.6.x and 10.7.x -version as well. +I tested this codeless driver under OS X 10.6.8 and 10.7.2. +I assume it works with any 10.6.x and 10.7.x version as well. -Attached to this mail you'll find the osx folder with the source code of the driver, both drivers (for -10.6.x and 10.7.x), an install.sh script and the modified Makefile, i only added a line at the end which -invoke the `install.sh`. +Attached to this mail you'll find the osx folder with the source code of the driver, both drivers (for 10.6.x and 10.7.x), an install.sh script and the modified Makefile, i only added a line at the end which invoke the `install.sh`. First, unpack the `osx.tar.gz` contents: ```bash @@ -41,13 +37,11 @@ P.S. If error `OS X version not supported` occurs. For the latest versions of Ma For OS X 10.10 Yosemite you must force the system to load unsigned kernelextensions ```bash -sudo nvram boot-args="kext-dev-mode=1“ +sudo nvram boot-args="kext-dev-mode=1" ``` reboot the system! ### OS X 10.11 El Capitan -(Update from another user) - For OS X 10.11 El Capitan: the Yosemite kext seems to work (tested on 10.11.04). From a69634c1128dcd08ab9fbb931dfb687ab5d90765 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 24 Feb 2020 22:55:29 +0100 Subject: [PATCH 0709/1435] Updated README.md --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index 594e0fae9..7a95a0bde 100644 --- a/README.md +++ b/README.md @@ -69,6 +69,7 @@ When there is no executable available for your platform or you need the latest ( * The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) * Before creating a pull request, please _ALWAYS_ open a new issue for the discussion of the intended new features. Bugfixes don't require a discussion via a ticket-issue. However they should always be described in a few words as soon as they appear to help others as well. * Contributors and/or maintainers may submit comments or request changes to patch-proposals and/or pull-requests. +* **ATTENTION: _NEVER EVER_ use the '#' character to count-up single points within a listing as '#' is _exclusively_ reserved for referencing github issues and pull-requests. Otherwise you accidentally introduce false cross references within the project.** ## License From 5020ba7f921d456ec821e35d0797e5bb88d1bfcc Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 24 Feb 2020 23:11:51 +0100 Subject: [PATCH 0710/1435] Resolved conflicts with develop branch. --- .travis.sh | 2 +- .travis.yml | 13 +- CHANGELOG.md | 36 ++++-- README.md | 205 ++++++++++++++++--------------- include/stlink.h | 8 ++ include/stlink/commands.h | 1 + include/stlink/usb.h | 16 +-- src/common.c | 43 ++++--- src/tools/flash.c | 10 +- src/usb.c | 199 +++++++++++++++++++++++++----- stlinkv1_macosx_driver/README.md | 18 +-- 11 files changed, 360 insertions(+), 191 deletions(-) diff --git a/.travis.sh b/.travis.sh index 06e95ef80..05568d37d 100755 --- a/.travis.sh +++ b/.travis.sh @@ -8,7 +8,7 @@ echo "----" if [ "$TRAVIS_OS_NAME" == "linux" ]; then sudo apt-get update -qq || true sudo apt-get install -qq -y --no-install-recommends libgtk-3-dev -else +else #("$TRAVIS_OS_NAME" == "osx") brew install libusb fi diff --git a/.travis.yml b/.travis.yml index c878be799..b0f985012 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,21 +1,24 @@ -language: c + compiler: - gcc - clang + +language: c + os: - linux - osx + addons: apt: sources: -# - llvm-toolchain-precise-3.8 - sourceline: 'ppa:ubuntu-toolchain-r/test' packages: - clang -# - clang-3.8 - - g++-5 - - gcc-5 + - g++-6 + - gcc-6 - libusb-1.0.0-dev + script: - git fetch --tags - printenv diff --git a/CHANGELOG.md b/CHANGELOG.md index 213d26358..10f12f81b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -9,7 +9,7 @@ Release date: 2020-02-20 Major changes and added features: * Added O_BINARY option to open file ([#753](https://github.com/texane/stlink/pull/753)) -* Added preliminary support for some STM32G0 chips ([#759](https://github.com/texane/stlink/pull/759)) ([#760](https://github.com/texane/stlink/pull/760)) +* Added preliminary support for some STM32G0 chips ([#759](https://github.com/texane/stlink/pull/759), [#760](https://github.com/texane/stlink/pull/760)) * Added support for mass erasing second bank on STM32F10x_XL ([#767](https://github.com/texane/stlink/pull/767), [#768](https://github.com/texane/stlink/pull/768)) * Added call to clear PG bit after writing to flash ([#773](https://github.com/texane/stlink/pull/773)) * Added howto for sending NRST signal through GDB ([#774](https://github.com/texane/stlink/pull/774), [#776](https://github.com/texane/stlink/pull/776)) @@ -26,7 +26,7 @@ Major changes and added features: Updates and fixes: -* Make udev rules and modprobe conf installation optional ([#741](https://github.com/texane/stlink/pull/741)) +* Made udev rules and modprobe conf installation optional ([#741](https://github.com/texane/stlink/pull/741)) * Fixed case when __FILE__ don't contain "/" nor "\\". ([#745](https://github.com/texane/stlink/pull/745)) * Fixed double dash issue in doc/man ([#746](https://github.com/texane/stlink/pull/746)) * Fixed Debug error on line 123 in CMakeLists.txt (@xor-gate) @@ -39,7 +39,7 @@ Updates and fixes: * Fixed package name "devscripts" in doc/compiling.md ([#775](https://github.com/texane/stlink/pull/775)) * Fixed apparent STM32G0 flashing issue ([#797](https://github.com/texane/stlink/pull/797)) * Fixed few potential memory/resource leaks ([#803](https://github.com/texane/stlink/pull/803)) -* Fixed flash verification error on STM32WB55RG ([#810](https://github.com/texane/stlink/pull/810)) ([#816](https://github.com/texane/stlink/pull/816)) +* Fixed flash verification error on STM32WB55RG ([#810](https://github.com/texane/stlink/pull/810), [#816](https://github.com/texane/stlink/pull/816)) * Do not issue JTAG reset on stlink-v1 (Gwenhael Goavec-Merou) * Fixed flash size of STM32 Discovery vl (Gwenhael Goavec-Merou) * Added support for writing option bytes on STM32L0 (Adrian Imboden) @@ -59,19 +59,29 @@ Release date: 2018-09-13 Major changes and added features: -* Implemented intel hex support for GTK GUI -* Updated libusb to 1.0.22 -* Added memory map for STM32F411RE target -* Add support for STM32L4R9 target +* Added button to export stm32 flash memory to a file ([#691](https://github.com/texane/stlink/pull/691)) +* Updated libusb to 1.0.22 ([#695](https://github.com/texane/stlink/pull/695)) +* Added desktop file for linux ([#688](https://github.com/texane/stlink/pull/688)) +* Added icons for stlink GUI ([#697](https://github.com/texane/stlink/pull/697)) +* Added support for STM32L4R9 target ([#694](https://github.com/texane/stlink/pull/694), [#699](https://github.com/texane/stlink/pull/699)) +* Added creation of icons for .desktop file ([#708](https://github.com/texane/stlink/pull/708)) +* Added memory map for STM32F411RE target ([#709](https://github.com/texane/stlink/pull/709)) +* Added reset through AIRCR ([#540](https://github.com/texane/stlink/pull/540), [#712](https://github.com/texane/stlink/pull/712)) +* Implemented intel hex support for GTK GUI ([#718](https://github.com/texane/stlink/pull/718)) Fixes: -* FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION -* Proper flash page size calculation for F412 target -* Fixed flash memory map for F72xxx target -* Return correct value on EOF for Semihosting SYS_READ - -For a complete list of changes see [the milestone](https://github.com/texane/stlink/milestone/6?closed=1) +* Fixed missing flash_loader for L011 ([#675](https://github.com/texane/stlink/pull/675)) +* Fixed serial number size mismatch with stlink_open_usb() ([#680](https://github.com/texane/stlink/pull/680)) +* Debian packaging, CMake and README.md fixes ([#683](https://github.com/texane/stlink/pull/683)) +* Fix for stlink library calls exit() or _exit() ([#634](https://github.com/texane/stlink/pull/634), [#696](https://github.com/texane/stlink/pull/696)) +* Fix for libusb deprecation ([#703](https://github.com/texane/stlink/pull/703), [#704](https://github.com/texane/stlink/pull/704)) +* Renamed STLINK_CHIPID_STM32_L4R9 to STLINK_CHIPID_STM32_L4RX ([#706](https://github.com/texane/stlink/pull/706)) +* Fixed flash memory map for F72XXX target ([#711](https://github.com/texane/stlink/pull/711)) +* Proper flash page size calculation for F412 target ([#721](https://github.com/texane/stlink/pull/721)) +* Return correct value on EOF for Semihosting SYS_READ ([#726](https://github.com/texane/stlink/pull/726), [#729](https://github.com/texane/stlink/pull/729), [#731](https://github.com/texane/stlink/pull/731)) +* Fix for mem_write() ([#730](https://github.com/texane/stlink/pull/730)) +* FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION ([#733](https://github.com/texane/stlink/pull/733)) v1.5.0 ====== diff --git a/README.md b/README.md index c8955a521..594e0fae9 100644 --- a/README.md +++ b/README.md @@ -1,18 +1,21 @@ Open source version of the STMicroelectronics Stlink Tools ========================================================== -[![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/texane/stlink/releases/latest) [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) -[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/v1.6.0.svg)](https://github.com/texane/stlink/releases/develop) +[![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/texane/stlink/releases/latest) +[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/v1.6.0.svg)](https://github.com/texane/stlink/releases/master) [![Downloads](https://img.shields.io/github/downloads/texane/stlink/total.svg)](https://github.com/texane/stlink/releases) - [![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) [![macOS Status](https://img.shields.io/travis/texane/stlink/master.svg?label=osx)](https://travis-ci.org/texane/stlink) +Recent new features and bugfixes can be found in the [Changelog](CHANGELOG.md) of this software project. + + +## Introduction -## HOWTO +This stlink toolset supports several so called stlink programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG. -This stlink toolset supports several so called stlink programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG. These programmer boards are available in four versions: +These programmer boards are available in four versions: * **STLINKv1:** - transport layer: SCSI passthru commands over USB @@ -24,39 +27,122 @@ This stlink toolset supports several so called stlink programmer boards (and clo * transport layer: raw USB commands * present on some STM32 nucleo boards * **STLINKv3:** - * _currently not supported by this toolset_ + * _not yet supported by this toolset (but planned)_ + + +## Supported hardware combinations + +Currently known working combinations of programmers and targets are listed in [doc/tested-boards.md](doc/tested-boards.md). ## Installation -Windows users can [download v1.3.0](https://github.com/texane/stlink/releases/tag/1.3.0) from the releases page. +**Windows**: download [v1.6.0](https://github.com/texane/stlink/releases/tag/v1.6.0) from the releases page. + +**macOS**: install [from homebrew](http://brewformulas.org/Stlink) or download [v1.6.0](https://github.com/texane/stlink/releases/tag/v1.6.0) from the releases page. -Mac OS X users can install from [homebrew](http://brewformulas.org/Stlink) or [download v1.3.0](https://github.com/texane/stlink/releases/tag/1.3.0) from the releases page. +**Linux**: -Debian Linux users can install it via the ```stlink-tools``` package [repository](https://packages.debian.org/buster/stlink-tools) +We recommend to install `stlink-tools` from the package repository of the used distribution: -Ubuntu Linux users can install it via the ```stlink-tools``` package [repository](https://packages.ubuntu.com/stlink-tools) +* Debian Linux: [(Link)](https://packages.debian.org/buster/stlink-tools) +* Ubuntu Linux: [(Link)](https://packages.ubuntu.com/stlink-tools) +* Arch Linux: [(Link)](https://www.archlinux.org/packages/community/x86_64/stlink) +* Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) +* Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) +* Gentoo Linux: [(Link)](https://packages.gentoo.org/packages/dev-embedded/stlink) -Arch Linux users can install from the [repository](https://www.archlinux.org/packages/community/x86_64/stlink) +**Other Operating Systems**: -Alpine Linux users can install from the [repository](https://pkgs.alpinelinux.org/packages?name=stlink) +* RedHat/CentOS 7: Users can install [from EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel7) +* FreeBSD: Users can install [from freshports](https://www.freshports.org/devel/stlink) +* OpenBSD: Users need to install [from source](doc/compiling.md). -Fedora users can install from [repository](https://src.fedoraproject.org/rpms/stlink) -RedHat/CentOS 7 users can install from EPEL [repository](https://src.fedoraproject.org/rpms/stlink/branch/epel7) +## Installation from source (advanced users) -Gentoo Linux users can install from the official portage [repository](https://packages.gentoo.org/packages/dev-embedded/stlink) +When there is no executable available for your platform or you need the latest (possible unstable) version you need to compile the toolset yourself. This procedure is explained in the [compiling manual](doc/compiling.md). -FreeBSD users can install from [freshports](https://www.freshports.org/devel/stlink) -OpenBSD users need to install [from source](doc/compiling.md). +## Contributing and versioning +* The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) +* Before creating a pull request, please _ALWAYS_ open a new issue for the discussion of the intended new features. Bugfixes don't require a discussion via a ticket-issue. However they should always be described in a few words as soon as they appear to help others as well. +* Contributors and/or maintainers may submit comments or request changes to patch-proposals and/or pull-requests. -## Installation from source (advanced users) -When there is no executable available for your platform or you need the latest (possible unstable) version you need to compile yourself. This is explained in the [compiling manual](doc/compiling.md). +## License + +The stlink library and tools are licensed under the [BSD license](LICENSE.md). + +The flashloaders/stm32l0x.s and flashloaders/stm32lx.s source files are licensed under the GPLv2+. +# Current state of the project + +## Known missing features + +Some features are currently missing from the `texane/stlink` toolset. +Here we would appreciate any help and would love to welcome new contributors who want to get involved: + +* Instrumentation Trace Macro (ITM) Cell ([#136](https://github.com/texane/stlink/issues/136)) +* OTP area programming ([#202](https://github.com/texane/stlink/issues/202)) +* EEPROM area programming ([#318](https://github.com/texane/stlink/issues/218)) +* Protection bits area reading ([#346](https://github.com/texane/stlink/issues/346)) +* Writing external memory connected to an STM32 controller (e.g Quad SPI NOR flash) ([#412](https://github.com/texane/stlink/issues/412)) +* MCU hotplug ([#449](https://github.com/texane/stlink/issues/449)) +* Writing options bytes (region) ([#458](https://github.com/texane/stlink/issues/458)) +* Control programming speed ([#462](https://github.com/texane/stlink/issues/462)) +* Support for STLINKv3 programmer ([#820](https://github.com/texane/stlink/issues/820)) + + +## Known bugs +### Sometimes flashing only works after a mass erase + +There is seen a problem sometimes where a flash loader run error occurs and is resolved after mass-erase of the flash: + +``` +2015-12-09T22:01:57 INFO src/stlink-common.c: Successfully loaded flash loader in sram +2015-12-09T22:02:18 ERROR src/stlink-common.c: flash loader run error +2015-12-09T22:02:18 ERROR src/stlink-common.c: run_flash_loader(0x8000000) failed! == -1 +``` + +Issue related to this bug: [#356](https://github.com/texane/stlink/issues/356) + + +### Flash size is detected as zero bytes size + +It is possible that the STM32 flash is write protected, the st-flash tool will show something like this: + +``` +st-flash write prog.bin 0x8000000 +2017-01-24T18:44:14 INFO src/stlink-common.c: Loading device parameters.... +2017-01-24T18:44:14 INFO src/stlink-common.c: Device connected is: F1 High-density device, id 0x10036414 +2017-01-24T18:44:14 INFO src/stlink-common.c: SRAM size: 0x10000 bytes (64 KiB), Flash: 0 bytes (0 KiB) in pages of 2048 bytes +``` + +As you can see, it gives out something unexpected like +``` +Flash: 0 bytes (0 KiB) in pages of 2048 bytes +``` + +``` +st-info --probe +Found 1 stlink programmers + serial: 303030303030303030303031 +openocd: "\x30\x30\x30\x30\x30\x30\x30\x30\x30\x30\x30\x31" + flash: 0 (pagesize: 2048) + sram: 65536 + chipid: 0x0414 + descr: F1 High-density device +``` + +Try to remove the write protection (probably only possible with ST Link Utility from ST itself). + +Issue related to this bug: [#545](https://github.com/texane/stlink/issues/545) + + +# HOWTO ## Using the gdb server To run the gdb server: @@ -177,84 +263,3 @@ A: Sometimes when you will try to use GDB `next` command to skip a loop, it will Q: Load command does not work in GDB. A: Some people report XML/EXPAT is not enabled by default when compiling GDB. Memory map parsing thus fail. Use --enable-expat. - - -## Currently known working combinations of programmer and target - -See [doc/tested-boards.md](doc/tested-boards.md) - -## Changelog - -The [Changelog](CHANGELOG.md) for the StLink Tools. - - -## Known missing features - -Some features are missing from the `texane/stlink` project and we would like you to help us out if you want to get involved: - -* Control programming speed (See [#462](https://github.com/texane/stlink/issues/462)) -* OTP area programming (See [#202](https://github.com/texane/stlink/issues/202)) -* EEPROM area programming (See [#318](https://github.com/texane/stlink/issues/218)) -* Protection bits area reading (See [#346](https://github.com/texane/stlink/issues/346)) -* MCU hotplug (See [#449](https://github.com/texane/stlink/issues/449)) -* Writing options bytes (region) (See [#458](https://github.com/texane/stlink/issues/458)) -* Instrumentation Trace Macro (ITM) Cell (See [#136](https://github.com/texane/stlink/issues/136)) -* Writing external memory connected to an STM32 controller (e.g Quad SPI NOR flash) (See [#412](https://github.com/texane/stlink/issues/412)) - - -## Known bugs -### Sometimes flashing only works after a mass erase - -There is seen a problem sometimes where a flash loader run error occurs and is resolved after mass-erase of the flash: - -``` -2015-12-09T22:01:57 INFO src/stlink-common.c: Successfully loaded flash loader in sram -2015-12-09T22:02:18 ERROR src/stlink-common.c: flash loader run error -2015-12-09T22:02:18 ERROR src/stlink-common.c: run_flash_loader(0x8000000) failed! == -1 -``` - -Issue related to this bug: [#356](https://github.com/texane/stlink/issues/356) - - -### Flash size is detected as zero bytes size - -It is possible that the STM32 flash is write protected, the st-flash tool will show something like this: - -``` -st-flash write prog.bin 0x8000000 -2017-01-24T18:44:14 INFO src/stlink-common.c: Loading device parameters.... -2017-01-24T18:44:14 INFO src/stlink-common.c: Device connected is: F1 High-density device, id 0x10036414 -2017-01-24T18:44:14 INFO src/stlink-common.c: SRAM size: 0x10000 bytes (64 KiB), Flash: 0 bytes (0 KiB) in pages of 2048 bytes -``` - -As you can see, it gives out something unexpected like -``` -Flash: 0 bytes (0 KiB) in pages of 2048 bytes -``` - -``` -st-info --probe -Found 1 stlink programmers - serial: 303030303030303030303031 -openocd: "\x30\x30\x30\x30\x30\x30\x30\x30\x30\x30\x30\x31" - flash: 0 (pagesize: 2048) - sram: 65536 - chipid: 0x0414 - descr: F1 High-density device -``` - -Try to remove the write protection (probably only possible with ST Link Utility from ST itself). - -Issue related to this bug: [#545](https://github.com/texane/stlink/issues/545) - - -## Contributing and versioning - -* The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) -* When creating a pull request, please open first a issue for discussion of new features. Bugfixes don't need a discussion. - -## License - -The stlink library and tools are licensed under the [BSD license](LICENSE.md). - -The flashloaders/stm32l0x.s and flashloaders/stm32lx.s source files are licensed under the GPLv2+. diff --git a/include/stlink.h b/include/stlink.h index 69b6ae31c..a69e357b5 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -52,6 +52,11 @@ extern "C" { #define STLINK_DEBUG_APIV2_SWD_SET_FREQ 0x43 +#define STLINK_APIV3_SET_COM_FREQ 0x61 +#define STLINK_APIV3_GET_COM_FREQ 0x62 + +#define STLINK_APIV3_GET_VERSION_EX 0xFB + // Baud rate divisors for SWDCLK #define STLINK_SWDCLK_4MHZ_DIVISOR 0 #define STLINK_SWDCLK_1P8MHZ_DIVISOR 1 @@ -68,6 +73,9 @@ extern "C" { #define STLINK_SERIAL_MAX_SIZE 64 +#define STLINK_V3_MAX_FREQ_NB 10 + + /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 diff --git a/include/stlink/commands.h b/include/stlink/commands.h index 9ff5a8fb9..acf664cb1 100644 --- a/include/stlink/commands.h +++ b/include/stlink/commands.h @@ -20,6 +20,7 @@ enum stlink_debug_commands { STLINK_DEBUG_ENTER = 0x20, STLINK_DEBUG_EXIT = 0x21, STLINK_DEBUG_READCOREID = 0x22, + STLINK_DEBUG_APIV2_ENTER = 0x30, STLINK_DEBUG_ENTER_SWD = 0xa3 }; diff --git a/include/stlink/usb.h b/include/stlink/usb.h index fd32a0731..4bf28c355 100644 --- a/include/stlink/usb.h +++ b/include/stlink/usb.h @@ -18,12 +18,15 @@ extern "C" { #endif -#define STLINK_USB_VID_ST 0x0483 -#define STLINK_USB_PID_STLINK 0x3744 -#define STLINK_USB_PID_STLINK_32L 0x3748 -#define STLINK_USB_PID_STLINK_32L_AUDIO 0x374a -#define STLINK_USB_PID_STLINK_NUCLEO 0x374b -#define STLINK_USB_PID_STLINK_NO_UMS 0x3752 +#define STLINK_USB_VID_ST 0x0483 +#define STLINK_USB_PID_STLINK 0x3744 +#define STLINK_USB_PID_STLINK_32L 0x3748 +#define STLINK_USB_PID_STLINK_32L_AUDIO 0x374a +#define STLINK_USB_PID_STLINK_NUCLEO 0x374b +#define STLINK_USB_PID_STLINK_V3_USBLOADER 0x374d +#define STLINK_USB_PID_STLINK_V3E_PID 0x374e +#define STLINK_USB_PID_STLINK_V3S_PID 0x374f +#define STLINK_USB_PID_STLINK_V3_2VCP_PID 0x3753 #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 @@ -55,4 +58,3 @@ extern "C" { #endif #endif /* STLINK_USB_H */ - diff --git a/src/common.c b/src/common.c index 018e01c4c..6226c893b 100644 --- a/src/common.c +++ b/src/common.c @@ -938,22 +938,33 @@ int stlink_status(stlink_t *sl) { * @param slv output parsed version object */ void _parse_version(stlink_t *sl, stlink_version_t *slv) { - uint32_t b0 = sl->q_buf[0]; //lsb - uint32_t b1 = sl->q_buf[1]; - uint32_t b2 = sl->q_buf[2]; - uint32_t b3 = sl->q_buf[3]; - uint32_t b4 = sl->q_buf[4]; - uint32_t b5 = sl->q_buf[5]; //msb - - // b0 b1 || b2 b3 | b4 b5 - // 4b | 6b | 6b || 2B | 2B - // stlink_v | jtag_v | swim_v || st_vid | stlink_pid - - slv->stlink_v = (b0 & 0xf0) >> 4; - slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); - slv->swim_v = b1 & 0x3f; - slv->st_vid = (b3 << 8) | b2; - slv->stlink_pid = (b5 << 8) | b4; + if (sl->version.stlink_v < 3) { + uint32_t b0 = sl->q_buf[0]; //lsb + uint32_t b1 = sl->q_buf[1]; + uint32_t b2 = sl->q_buf[2]; + uint32_t b3 = sl->q_buf[3]; + uint32_t b4 = sl->q_buf[4]; + uint32_t b5 = sl->q_buf[5]; //msb + + // b0 b1 || b2 b3 | b4 b5 + // 4b | 6b | 6b || 2B | 2B + // stlink_v | jtag_v | swim_v || st_vid | stlink_pid + + slv->stlink_v = (b0 & 0xf0) >> 4; + slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); + slv->swim_v = b1 & 0x3f; + slv->st_vid = (b3 << 8) | b2; + slv->stlink_pid = (b5 << 8) | b4; + } else { + // V3 uses different version format, for reference see OpenOCD source + // (that was written from docs available from ST under NDA): + // https://github.com/ntfreak/openocd/blob/a6dacdff58ef36fcdac00c53ec27f19de1fbce0d/src/jtag/drivers/stlink_usb.c#L965 + slv->stlink_v = sl->q_buf[0]; + slv->swim_v = sl->q_buf[1]; + slv->jtag_v = sl->q_buf[2]; + slv->st_vid = (uint32_t)((sl->q_buf[9] << 8) | sl->q_buf[8]); + slv->stlink_pid = (uint32_t)((sl->q_buf[11] << 8) | sl->q_buf[10]); + } return; } diff --git a/src/tools/flash.c b/src/tools/flash.c index 1b63b1696..f87b65940 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -29,11 +29,11 @@ static void cleanup(int signum) { static void usage(void) { - puts("stlinkv1 command line: ./st-flash [--debug] [--reset] [--format ] [--flash=] {read|write} /dev/sgX "); - puts("stlinkv1 command line: ./st-flash [--debug] /dev/sgX erase"); - puts("stlinkv2 command line: ./st-flash [--debug] [--reset] [--serial ] [--format ] [--flash=] {read|write} "); - puts("stlinkv2 command line: ./st-flash [--debug] [--serial ] erase"); - puts("stlinkv2 command line: ./st-flash [--debug] [--serial ] reset"); + puts("stlinkv1 command line: ./st-flash [--debug] [--reset] [--format ] [--flash=] {read|write} /dev/sgX "); + puts("stlinkv1 command line: ./st-flash [--debug] /dev/sgX erase"); + puts("stlinkv2/3 command line: ./st-flash [--debug] [--reset] [--serial ] [--format ] [--flash=] {read|write} "); + puts("stlinkv2/3 command line: ./st-flash [--debug] [--serial ] erase"); + puts("stlinkv2/3 command line: ./st-flash [--debug] [--serial ] reset"); puts(" Use hex format for addr, and ."); puts(" fsize: Use decimal, octal or hex by prefix 0xXXX for hex, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); puts(" Format may be 'binary' (default) or 'ihex', although must be specified for binary format only."); diff --git a/src/usb.c b/src/usb.c index d3a541774..9df9d7296 100644 --- a/src/usb.c +++ b/src/usb.c @@ -22,6 +22,53 @@ enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; +static inline uint32_t le_to_h_u32(const uint8_t* buf) +{ + return (uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24); +} + +static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, uint32_t khz) +{ + unsigned int i; + int speed_index = -1; + int speed_diff = INT_MAX; + int last_valid_speed = -1; + bool match = true; + + for (i = 0; i < map_size; i++) { + if (!map[i]) + continue; + last_valid_speed = i; + if (khz == map[i]) { + speed_index = i; + break; + } else { + int current_diff = khz - map[i]; + /* get abs value for comparison */ + current_diff = (current_diff > 0) ? current_diff : -current_diff; + if ((current_diff < speed_diff) && khz >= map[i]) { + speed_diff = current_diff; + speed_index = i; + } + } + } + + if (speed_index == -1) { + /* this will only be here if we cannot match the slow speed. + * use the slowest speed we support.*/ + speed_index = last_valid_speed; + match = false; + } else if (i == map_size) + match = false; + + if (!match) { + ILOG("Unable to match requested speed %d kHz, using %d kHz\n", \ + khz, map[speed_index]); + } + + return speed_index; +} + void _stlink_usb_close(stlink_t* sl) { if (!sl) return; @@ -135,6 +182,19 @@ int _stlink_usb_version(stlink_t *sl) { return (int) size; } + /* STLINK-V3 requires a specific command */ + if (sl->version.stlink_v == 3) { + rep_len = 12; + i = fill_command(sl, SG_DXFER_FROM_DEV, 16); + cmd[i++] = STLINK_APIV3_GET_VERSION_EX; + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size != rep_len) { + printf("[!] send_recv STLINK_APIV3_GET_VERSION_EX\n"); + return (int) size; + } + } + return 0; } @@ -334,17 +394,23 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; ssize_t size; - const int rep_len = 0; + unsigned char* const data = sl->q_buf; + const uint32_t rep_len = sl->version.stlink_v > 1 ? 2 : 0; int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_ENTER; + cmd[i++] = sl->version.stlink_v > 1? STLINK_DEBUG_APIV2_ENTER : STLINK_DEBUG_ENTER; cmd[i++] = STLINK_DEBUG_ENTER_SWD; - size = send_only(slu, 1, cmd, slu->cmd_len); + + if (rep_len == 0) { + size = send_only(slu, 1, cmd, slu->cmd_len); + } else { + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + } if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_ENTER\n"); - return (int) size; + printf("[!] send_recv STLINK_DEBUG_ENTER\n"); + return (int) size; } return 0; @@ -466,9 +532,8 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { ssize_t size; int rep_len = 2; int i; - // clock speed only supported by stlink/v2 and for firmware >= 22 - if (sl->version.stlink_v >= 2 && sl->version.jtag_v >= 22) { + if (sl->version.stlink_v == 2 && sl->version.jtag_v >= 22) { i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -483,9 +548,55 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { } return 0; - } else { - return -1; + } else if (sl->version.stlink_v == 3) { + int speed_index; + uint32_t map[STLINK_V3_MAX_FREQ_NB]; + i = fill_command(sl, SG_DXFER_FROM_DEV, 16); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_APIV3_GET_COM_FREQ; + cmd[i++] = 0; // SWD mode + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52); + if (size == -1) { + printf("[!] send_recv STLINK_APIV3_GET_COM_FREQ\n"); + return (int) size; + } + + int speeds_size = data[8]; + + if (speeds_size > STLINK_V3_MAX_FREQ_NB) + speeds_size = STLINK_V3_MAX_FREQ_NB; + + for (i = 0; i < speeds_size; i++) + map[i] = le_to_h_u32(&data[12 + 4 * i]); + + /* set to zero all the next entries */ + for (i = speeds_size; i < STLINK_V3_MAX_FREQ_NB; i++) + map[i] = 0; + + speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), 1800); + + i = fill_command(sl, SG_DXFER_FROM_DEV, 16); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_APIV3_SET_COM_FREQ; + cmd[i++] = 0; // SWD mode + cmd[i++] = 0; + cmd[i++] = (uint8_t)((map[speed_index] >> 0) & 0xFF); + cmd[i++] = (uint8_t)((map[speed_index] >> 8) & 0xFF); + cmd[i++] = (uint8_t)((map[speed_index] >> 16) & 0xFF); + cmd[i++] = (uint8_t)((map[speed_index] >> 24) & 0xFF); + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8); + if (size == -1) { + printf("[!] send_recv STLINK_APIV3_SET_COM_FREQ\n"); + return (int) size; + } + + return 0; } + return -1; } int _stlink_usb_exit_debug_mode(stlink_t *sl) { @@ -827,34 +938,49 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST } } - if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) || - (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO) || - (desc.idProduct == STLINK_USB_PID_STLINK_NO_UMS) || - (desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO)) { + if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) || + (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO) || + (desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO) || + (desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER) || + (desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID) || + (desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID) || + (desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID)) { struct libusb_device_handle *handle; ret = libusb_open(list[cnt], &handle); if (ret) - continue; + continue; sl->serial_size = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)sl->serial, sizeof(sl->serial)); libusb_close(handle); + if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) + || (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO) + || (desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO)) { + sl->version.stlink_v = 2; + } else if ((desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER) + || (desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID) + || (desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID) + || (desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID)) { + sl->version.stlink_v = 3; + } + if ((serial == NULL) || (*serial == 0)) - break; + break; if (sl->serial_size < 0) - continue; + continue; if (memcmp(serial, &sl->serial, sl->serial_size) == 0) - break; + break; continue; } if (desc.idProduct == STLINK_USB_PID_STLINK) { slu->protocoll = 1; + sl->version.stlink_v = 1; break; } } @@ -904,7 +1030,12 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST // TODO - could use the scanning techniq from stm8 code here... slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; - if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO || desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO || desc.idProduct == STLINK_USB_PID_STLINK_NO_UMS) { + if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO || + desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO || + desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER || + desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID || + desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID || + desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID) { slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; } else { slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; @@ -914,21 +1045,23 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST // TODO - never used at the moment, always CMD_SIZE slu->cmd_len = (slu->protocoll == 1)? STLINK_SG_SIZE: STLINK_CMD_SIZE; + // Initialize stlink version (sl->version) + stlink_version(sl); + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { ILOG("-- exit_dfu_mode\n"); stlink_exit_dfu_mode(sl); } + // set the speed before entering the mode + // as the chip discovery phase should be done at this speed too + // Set the stlink clock speed (default is 1800kHz) + stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { - stlink_enter_swd_mode(sl); + stlink_enter_swd_mode(sl); } - - // Initialize stlink version (sl->version) - stlink_version(sl); - // Set the stlink clock speed (default is 1800kHz) - stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); - if (reset) { if( sl->version.stlink_v > 1 ) stlink_jtag_reset(sl, 2); stlink_reset(sl); @@ -976,9 +1109,12 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { } if (desc.idProduct != STLINK_USB_PID_STLINK_32L && - desc.idProduct != STLINK_USB_PID_STLINK_32L_AUDIO && - desc.idProduct != STLINK_USB_PID_STLINK_NO_UMS && - desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO) + desc.idProduct != STLINK_USB_PID_STLINK_32L_AUDIO && + desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO && + desc.idProduct != STLINK_USB_PID_STLINK_V3_USBLOADER && + desc.idProduct != STLINK_USB_PID_STLINK_V3E_PID && + desc.idProduct != STLINK_USB_PID_STLINK_V3S_PID && + desc.idProduct != STLINK_USB_PID_STLINK_V3_2VCP_PID) continue; slcnt++; @@ -1001,9 +1137,8 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { break; } - if (desc.idProduct != STLINK_USB_PID_STLINK_32L && - desc.idProduct != STLINK_USB_PID_STLINK_32L_AUDIO && - desc.idProduct != STLINK_USB_PID_STLINK_NO_UMS && + if (desc.idProduct != STLINK_USB_PID_STLINK_32L && + desc.idProduct != STLINK_USB_PID_STLINK_32L_AUDIO && desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO) continue; @@ -1024,7 +1159,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { libusb_close(handle); stlink_t *sl = NULL; - sl = stlink_open_usb(0, 1, serial); + sl = stlink_open_usb(0, 1, serial); if (!sl) continue; diff --git a/stlinkv1_macosx_driver/README.md b/stlinkv1_macosx_driver/README.md index 4e6b8c6a0..b2a68442c 100644 --- a/stlinkv1_macosx_driver/README.md +++ b/stlinkv1_macosx_driver/README.md @@ -4,18 +4,14 @@ to: texane@gmail.com Hi, -i managed to get the stlink v1 working under os x and i would like to share the solution so maybe you can -add it in your package. +i managed to get the stlink v1 working under os x and i would like to share the solution so maybe you can add it in your package. The problem is that os x claims the device as scsi and libusb won't be able to connect to it. -I've created what is called a codeless driver which claims the device and has a higher priority then the -default apple mass storage driver, so the device can be accessed through libusb. +I've created what is called a codeless driver which claims the device and has a higher priority then the default apple mass storage driver, so the device can be accessed through libusb. -I tested this codeless driver under OS X 10.6.8 and 10.7.2. I assume it works with any 10.6.x and 10.7.x -version as well. +I tested this codeless driver under OS X 10.6.8 and 10.7.2. +I assume it works with any 10.6.x and 10.7.x version as well. -Attached to this mail you'll find the osx folder with the source code of the driver, both drivers (for -10.6.x and 10.7.x), an install.sh script and the modified Makefile, i only added a line at the end which -invoke the `install.sh`. +Attached to this mail you'll find the osx folder with the source code of the driver, both drivers (for 10.6.x and 10.7.x), an install.sh script and the modified Makefile, i only added a line at the end which invoke the `install.sh`. First, unpack the `osx.tar.gz` contents: ```bash @@ -41,13 +37,11 @@ P.S. If error `OS X version not supported` occurs. For the latest versions of Ma For OS X 10.10 Yosemite you must force the system to load unsigned kernelextensions ```bash -sudo nvram boot-args="kext-dev-mode=1“ +sudo nvram boot-args="kext-dev-mode=1" ``` reboot the system! ### OS X 10.11 El Capitan -(Update from another user) - For OS X 10.11 El Capitan: the Yosemite kext seems to work (tested on 10.11.04). From 14c2cbe0c6e15429fb8f02919c94ed976fbf371e Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Tue, 25 Feb 2020 22:08:24 +0000 Subject: [PATCH 0711/1435] Bump Standards-Version to 4.5.0, no changes. --- debian/control | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian/control b/debian/control index c541d5bef..4382cdcd5 100644 --- a/debian/control +++ b/debian/control @@ -2,7 +2,7 @@ Source: stlink Priority: optional Maintainer: Luca Boccassi Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev -Standards-Version: 4.4.0 +Standards-Version: 4.5.0 Rules-Requires-Root: no Section: electronics Homepage: https://github.com/texane/stlink From d3021e569f2a151ba415d75a8984db17307b1170 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Tue, 25 Feb 2020 22:10:41 +0000 Subject: [PATCH 0712/1435] Add d/s/options to ignore repacked files Gbp-Dch: ignore --- debian/source/options | 1 + 1 file changed, 1 insertion(+) create mode 100644 debian/source/options diff --git a/debian/source/options b/debian/source/options new file mode 100644 index 000000000..7022977a9 --- /dev/null +++ b/debian/source/options @@ -0,0 +1 @@ +extend-diff-ignore=stlinkv1_macosx_driver From 00441133fa59e09ac8da87d25ee2bdabb2c6e720 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Tue, 25 Feb 2020 22:13:51 +0000 Subject: [PATCH 0713/1435] Update libstlink1 symbols file for 1.6.0. --- debian/libstlink1.symbols | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/debian/libstlink1.symbols b/debian/libstlink1.symbols index 51fa9bdb1..4518989a1 100644 --- a/debian/libstlink1.symbols +++ b/debian/libstlink1.symbols @@ -78,6 +78,8 @@ libstlink.so.1 libstlink1 #MINVER# stlink_force_debug@Base 1.5.0 stlink_fread@Base 1.5.0 stlink_fwrite_flash@Base 1.5.0 + stlink_fwrite_option_bytes@Base 1.6.0 + stlink_fwrite_option_bytes_32bit@Base 1.6.0 stlink_fwrite_sram@Base 1.5.0 stlink_get_erased_pattern@Base 1.5.0 stlink_is_core_halted@Base 1.5.0 @@ -95,6 +97,8 @@ libstlink.so.1 libstlink1 #MINVER# stlink_read_all_unsupported_regs@Base 1.5.0 stlink_read_debug32@Base 1.5.0 stlink_read_mem32@Base 1.5.0 + stlink_read_option_bytes_f2@Base 1.6.0 + stlink_read_option_bytes_f4@Base 1.6.0 stlink_read_reg@Base 1.5.0 stlink_read_unsupported_reg@Base 1.5.0 stlink_reset@Base 1.5.0 @@ -115,6 +119,7 @@ libstlink.so.1 libstlink1 #MINVER# stlink_write_flash@Base 1.5.0 stlink_write_mem32@Base 1.5.0 stlink_write_mem8@Base 1.5.0 + stlink_write_option_bytes@Base 1.6.0 stlink_write_reg@Base 1.5.0 stlink_write_unsupported_reg@Base 1.5.0 stm32l1_write_half_pages@Base 1.5.0 From f92878df5e2761cf38fc4719b18e288a0a1fa61e Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Tue, 25 Feb 2020 22:08:48 +0000 Subject: [PATCH 0714/1435] Update changelog for 1.6.0+ds-1 release --- debian/changelog | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/debian/changelog b/debian/changelog index 5d132ca55..0ad68fed3 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,11 @@ +stlink (1.6.0+ds-1) unstable; urgency=medium + + * Merge tag 'v1.6.0' into debian + * Bump Standards-Version to 4.5.0, no changes. + * Update libstlink1 symbols file for 1.6.0. + + -- Luca Boccassi Tue, 25 Feb 2020 22:08:33 +0000 + stlink (1.5.1+ds-2) unstable; urgency=medium * Mark library packages as Multi-Arch: same. From 2f9748e52f4739354668bc77bd208ca471cc528b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 26 Feb 2020 20:32:55 +0100 Subject: [PATCH 0715/1435] General Project Update - Fixes in CHANGELOG.md - Added note in README.md - Updated package requirements. --- CHANGELOG.md | 12 +++++++----- README.md | 2 +- doc/compiling.md | 15 ++++++++------- 3 files changed, 16 insertions(+), 13 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 10f12f81b..2832464a2 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -26,6 +26,7 @@ Major changes and added features: Updates and fixes: +* Build failure when platform is 32 bit, but stuct stat.st_size is 64 bit. ([#629](https://github.com/texane/stlink/pull/629)) * Made udev rules and modprobe conf installation optional ([#741](https://github.com/texane/stlink/pull/741)) * Fixed case when __FILE__ don't contain "/" nor "\\". ([#745](https://github.com/texane/stlink/pull/745)) * Fixed double dash issue in doc/man ([#746](https://github.com/texane/stlink/pull/746)) @@ -33,7 +34,7 @@ Updates and fixes: * Only do bank calculation on STM32L4 devices with dual banked flash ([#751](https://github.com/texane/stlink/pull/751)) * Updated STM32F3xx chip ID that covers a few different devices ([#758](https://github.com/texane/stlink/pull/758)) * Fixed versioning when compiling from the checked out git-repo ([#762](https://github.com/texane/stlink/pull/762)) -* Fixed "unkown chip id", piped output and st-util -v ([#763](https://github.com/texane/stlink/pull/763)) +* Fixed "unkown chip id", piped output and st-util -v ([#107](https://github.com/texane/stlink/pull/107), [#763](https://github.com/texane/stlink/pull/763)) * win32: move usleep definition to unistd.h ([#765](https://github.com/texane/stlink/pull/765)) * Fixed relative path to the UI files needed by stlink-gui-local (GUI) ([#770](https://github.com/texane/stlink/pull/770), [#771](https://github.com/texane/stlink/pull/771)) * Fixed package name "devscripts" in doc/compiling.md ([#775](https://github.com/texane/stlink/pull/775)) @@ -149,10 +150,10 @@ Release date: 2017-01-28 Major changes and added features: -* Deprecation of autotools (autoconf, automake) (@xor-gate) +* Deprecation of autotools (autoconf, automake) ([#83](https://github.com/texane/stlink/pull/83), [#431](https://github.com/texane/stlink/pull/431), [#434](https://github.com/texane/stlink/pull/434)) * Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#3fd0f09](https://github.com/texane/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) * Added support for native debian packaging ([#444](https://github.com/texane/stlink/pull/444), [#485](https://github.com/texane/stlink/pull/485)) -* Added intel hex file reading for `st-flash` ([#459](https://github.com/texane/stlink/pull/541)) +* Added intel hex file reading for `st-flash` ([#110](https://github.com/texane/stlink/pull/110), [#157](https://github.com/texane/stlink/pull/157), [#200](https://github.com/texane/stlink/pull/200), [#239](https://github.com/texane/stlink/pull/239), [#457](https://github.com/texane/stlink/pull/547), [#459](https://github.com/texane/stlink/pull/549)) * Added `--reset` command to `st-flash` ([#505](https://github.com/texane/stlink/pull/505)) * Support serial numbers argument for `st-util` and `st-flash` for multi-programmer setups ([#541](https://github.com/texane/stlink/pull/541)) * Added kill ('k') command to gdb-server for `st-util` ([#9804416](https://github.com/texane/stlink/commit/98044163ab34bf5159f121d1c49ffb3550321ca0)) @@ -171,14 +172,15 @@ Chip support added for: Updates and fixes: +* Set SWDCLK and fixed jtag_reset bug ([#254](https://github.com/texane/stlink/pull/254), [#291](https://github.com/texane/stlink/pull/291), [#475](https://github.com/texane/stlink/pull/475), [#533](https://github.com/texane/stlink/pull/533), [#534](https://github.com/texane/stlink/pull/534)) * Fixed STM32F030 erase error ([#442](https://github.com/texane/stlink/pull/442)) * Fixed Cygwin build ([#68b0f3b](https://github.com/texane/stlink/commit/68b0f3bddc3c4aaffe34caa6a3201029edd8ad56)) * Reset flash mass erase (MER) bit after mass erase for safety ([#489](https://github.com/texane/stlink/pull/489)) * Fixed memory map for STM32F4 (@zulusw) -* Fixed STM32L-problem with flash loader (issue #390) (Tom de Boer) +* Fixed STM32L-problem with flash loader ([#390](https://github.com/texane/stlink/pull/390)) * `st-util` don't read target voltage on startup as it crashes STM32F100 (probably stlink/v1) (Greg Alexander) * Do a JTAG reset prior to reading CPU information when processor is in deep sleep (@andyg24) -* Redesign of `st-flash` commandline options parsing (pull-request #459) (@dev26th) +* Redesign of `st-flash` commandline options parsing ([#459](https://github.com/texane/stlink/pull/459)) v1.2.0 ====== diff --git a/README.md b/README.md index 594e0fae9..df7fbfc05 100644 --- a/README.md +++ b/README.md @@ -69,7 +69,7 @@ When there is no executable available for your platform or you need the latest ( * The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) * Before creating a pull request, please _ALWAYS_ open a new issue for the discussion of the intended new features. Bugfixes don't require a discussion via a ticket-issue. However they should always be described in a few words as soon as they appear to help others as well. * Contributors and/or maintainers may submit comments or request changes to patch-proposals and/or pull-requests. - +* Please start new forks from the develop branch if possible as pull requests will go into this branch as well. ## License diff --git a/doc/compiling.md b/doc/compiling.md index 555dce487..61bb12e6e 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -1,10 +1,11 @@ -# Compiling +# Compiling from sources -## Build from sources +## Package requirements -* CMake (minimal v2.8.7) -* C compiler (gcc, clang, mingw) -* Libusb 1.0 (minimal v1.0.9) +* CMake (v2.8.7 or later) +* C compiler (gcc, clang or mingw) +* libusb 1.0 (v1.0.13 or later) +* libusb-dev 1.0 (v1.0.13 or later) * (optional) pandoc for generating manpages from markdown Run from the root of the source directory: @@ -127,7 +128,7 @@ you can use the following cmake option: $ cmake -DLIB_INSTALL_DIR:PATH="/usr/lib64" .. ``` -## Windows (MinGW64) +## Windows (MinGW64) ### Prequistes @@ -149,7 +150,7 @@ Check and execute (in the script folder) `\scripts\mingw64-build.bat NOTE: when installing different toolchains make sure you edit the path in the `mingw64-build.bat` the build script uses currently `C:\Program Files\mingw-w64\x86_64-5.3.0-win32-sjlj-rt_v4-rev0\mingw64\bin` -## Windows (Visual Studio) +## Windows (Visual Studio) ### Prerequisites From f5d0454ab0a18f209ad5b7d0d51f3945b27dd892 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 27 Feb 2020 01:56:59 +0100 Subject: [PATCH 0716/1435] Hotfix: Reverts commit 6692fdc. CKS32-Clone-Patch broke flashing on STM32 F3xx, F4xx and L1xx. (#761) --- include/stm32.h | 1 - src/flash_loader.c | 1 - 2 files changed, 2 deletions(-) diff --git a/include/stm32.h b/include/stm32.h index 858d2b22a..9a01baaf4 100644 --- a/include/stm32.h +++ b/include/stm32.h @@ -9,7 +9,6 @@ // cortex core ids #define STM32VL_CORE_ID 0x1ba01477 -#define CS32VL_CORE_ID 0x2ba01477 #define STM32F7_CORE_ID 0x5ba02477 // Constant STM32 memory map figures diff --git a/src/flash_loader.c b/src/flash_loader.c index 9f6e3a79d..f88a42eca 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -267,7 +267,6 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || - sl->core_id == CS32VL_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_F3 || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL || From 83a31a09b358021a3b6b65962f7ea4c6550f0289 Mon Sep 17 00:00:00 2001 From: Slyshyk Oleksiy Date: Sat, 29 Feb 2020 16:23:22 +0200 Subject: [PATCH 0717/1435] Add win32 travis build (#2) * add mingw64 build to travis CI * Make .travis-lin-mingw.sh executable * .travis-lin-mingw.sh: make build dir * show $PWD in travis-lin-mingw * update .travis-lin-mingw.sh * --- * update .travis-lin-mingw.sh * update p7zip cmd * fix sign/unsign comparioson in usb.c * revert call .travis.sh * clean up .travis-lin-mingw.sh --- .travis-lin-mingw.sh | 14 ++++++++++++++ .travis.yml | 3 +++ cmake/modules/FindLibUSB.cmake | 3 ++- src/usb.c | 2 +- 4 files changed, 20 insertions(+), 2 deletions(-) create mode 100755 .travis-lin-mingw.sh diff --git a/.travis-lin-mingw.sh b/.travis-lin-mingw.sh new file mode 100755 index 000000000..0422a06f6 --- /dev/null +++ b/.travis-lin-mingw.sh @@ -0,0 +1,14 @@ +#!/bin/bash + +DIR=$PWD + +if [ "$TRAVIS_OS_NAME" == "linux" ]; then + echo "WORK DIR:$DIR" + mkdir -p $DIR/build/linux-mingw32-release + cd $DIR/build/linux-mingw32-release + echo "cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR" + cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR + echo "make" + make +fi + diff --git a/.travis.yml b/.travis.yml index b0f985012..b1832d57f 100644 --- a/.travis.yml +++ b/.travis.yml @@ -18,9 +18,12 @@ addons: - g++-6 - gcc-6 - libusb-1.0.0-dev + - p7zip + - mingw-w64 script: - git fetch --tags - printenv - cmake --version - ./.travis.sh + - ./.travis-lin-mingw.sh diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index 5233e489d..2ad35b3d8 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -84,7 +84,8 @@ if(NOT LIBUSB_FOUND) file(MAKE_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) if(${ZIP_EXECUTABLE} MATCHES "p7zip") - execute_process(COMMAND ${ZIP_EXECUTABLE} -d --keep -f ${LIBUSB_WIN_ARCHIVE_PATH} WORKING_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) + #execute_process(COMMAND ${ZIP_EXECUTABLE} -d --keep -f ${LIBUSB_WIN_ARCHIVE_PATH} WORKING_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) + execute_process(COMMAND ${ZIP_EXECUTABLE} -d ${LIBUSB_WIN_ARCHIVE_PATH} WORKING_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) else() execute_process(COMMAND ${ZIP_EXECUTABLE} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o${LIBUSB_WIN_OUTPUT_FOLDER}) endif() diff --git a/src/usb.c b/src/usb.c index 9df9d7296..81bd7ae2c 100644 --- a/src/usb.c +++ b/src/usb.c @@ -189,7 +189,7 @@ int _stlink_usb_version(stlink_t *sl) { cmd[i++] = STLINK_APIV3_GET_VERSION_EX; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); - if (size != rep_len) { + if (size != (ssize_t)rep_len) { printf("[!] send_recv STLINK_APIV3_GET_VERSION_EX\n"); return (int) size; } From 4d55b6b3bf2bfecab3251fbe966c86eaad4e027a Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sun, 1 Mar 2020 18:47:59 +0200 Subject: [PATCH 0718/1435] make Version.cmake more error-resistant. fix #772 --- cmake/Version.cmake | 103 +++++++++++++++++++++++++++++--------------- 1 file changed, 69 insertions(+), 34 deletions(-) diff --git a/cmake/Version.cmake b/cmake/Version.cmake index e74d775d6..e5ce9f4c6 100644 --- a/cmake/Version.cmake +++ b/cmake/Version.cmake @@ -1,7 +1,11 @@ # Determine project version # * Using Git # * Local .version file -find_package (Git QUIET) + +set(__detect_version 0) + +find_package (Git) + if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") # Working off a git repo, using git versioning # Check if HEAD is pointing to a tag @@ -9,43 +13,74 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") COMMAND "${GIT_EXECUTABLE}" describe --always --tag WORKING_DIRECTORY "${PROJECT_SOURCE_DIR}" OUTPUT_VARIABLE PROJECT_VERSION + RESULT_VARIABLE GIT_DESCRIBE_RESULT + ERROR_VARIABLE GIT_DESCRIBE_ERROR OUTPUT_STRIP_TRAILING_WHITESPACE) - # If the sources have been changed locally, add -dirty to the version. - execute_process ( - COMMAND "${GIT_EXECUTABLE}" diff --quiet - WORKING_DIRECTORY "${PROJECT_SOURCE_DIR}" - RESULT_VARIABLE res) - - if (res EQUAL 1) - set (PROJECT_VERSION "${PROJECT_VERSION}-dirty") - endif() - - # strip a leading v off of the version as proceeding code expectes just the version numbering. - string(REGEX REPLACE "^v" "" PROJECT_VERSION ${PROJECT_VERSION}) - - string(REGEX REPLACE "^(0|[1-9][0-9]*)[.](0|[1-9][0-9]*)[.](0|[1-9][0-9]*)(-[.0-9A-Za-z-]+)?([+][.0-9A-Za-z-]+)?$" - "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) - list(LENGTH PROJECT_VERSION_LIST len) - if(len EQUAL 3) - list(GET PROJECT_VERSION_LIST 0 PROJECT_VERSION_MAJOR) - list(GET PROJECT_VERSION_LIST 1 PROJECT_VERSION_MINOR) - list(GET PROJECT_VERSION_LIST 2 PROJECT_VERSION_PATCH) - endif() -elseif(EXISTS ${PROJECT_SOURCE_DIR}/.version) - # If git is not available (e.g. when building from source package) - # we can extract the package version from .version file. - file (STRINGS .version PROJECT_VERSION) - - # TODO create function to extract semver from file or string and check if it is correct instead of copy-pasting - string(REGEX REPLACE "^(0|[1-9][0-9]*)[.](0|[1-9][0-9]*)[.](0|[1-9][0-9]*)(-[.0-9A-Za-z-]+)?([+][.0-9A-Za-z-]+)?$" - "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) - list(GET PROJECT_VERSION_LIST 0 PROJECT_VERSION_MAJOR) - list(GET PROJECT_VERSION_LIST 1 PROJECT_VERSION_MINOR) - list(GET PROJECT_VERSION_LIST 2 PROJECT_VERSION_PATCH) + if(GIT_DESCRIBE_RESULT EQUAL 0) + # If the sources have been changed locally, add -dirty to the version. + execute_process ( + COMMAND "${GIT_EXECUTABLE}" diff --quiet + WORKING_DIRECTORY "${PROJECT_SOURCE_DIR}" + RESULT_VARIABLE res) + + if (res EQUAL 1) + set (PROJECT_VERSION "${PROJECT_VERSION}-dirty") + endif() + + # strip a leading v off of the version as proceeding code expectes just the version numbering. + string(REGEX REPLACE "^v" "" PROJECT_VERSION ${PROJECT_VERSION}) + + string(REGEX REPLACE "^(0|[1-9][0-9]*)[.](0|[1-9][0-9]*)[.](0|[1-9][0-9]*)(-[.0-9A-Za-z-]+)?([+][.0-9A-Za-z-]+)?$" + "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) + list(LENGTH PROJECT_VERSION_LIST len) + if(len EQUAL 3) + list(GET PROJECT_VERSION_LIST 0 PROJECT_VERSION_MAJOR) + list(GET PROJECT_VERSION_LIST 1 PROJECT_VERSION_MINOR) + list(GET PROJECT_VERSION_LIST 2 PROJECT_VERSION_PATCH) + set(__detect_version 1) + else() + message(STATUS "Fail to extract version's parts from \"${PROJECT_VERSION}\"") + endif() + + else(GIT_DESCRIBE_RESULT EQUAL 0) + message(WARNING "git describe failed.") + message(WARNING "${GIT_DESCRIBE_ERROR}") + endif(GIT_DESCRIBE_RESULT EQUAL 0) else() - message(FATAL_ERROR "Unable to determine project version") + message(STATUS "Git or repo not found.") endif() + + +if(NOT __detect_version) + message(STATUS "Try to detect version from \"${PROJECT_SOURCE_DIR}/.version\" file.") + if(EXISTS ${PROJECT_SOURCE_DIR}/.version) + # If git is not available (e.g. when building from source package) + # we can extract the package version from .version file. + file (STRINGS .version PROJECT_VERSION) + + # TODO create function to extract semver from file or string and check if it is correct instead of copy-pasting + string(REGEX REPLACE "^(0|[1-9][0-9]*)[.](0|[1-9][0-9]*)[.](0|[1-9][0-9]*)(-[.0-9A-Za-z-]+)?([+][.0-9A-Za-z-]+)?$" + "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) + list(LENGTH PROJECT_VERSION_LIST len) + if(len EQUAL 3) + list(GET PROJECT_VERSION_LIST 0 PROJECT_VERSION_MAJOR) + list(GET PROJECT_VERSION_LIST 1 PROJECT_VERSION_MINOR) + list(GET PROJECT_VERSION_LIST 2 PROJECT_VERSION_PATCH) + set(__detect_version 1) + else() + message(STATUS "Fail to extract version's parts from \"${PROJECT_VERSION}\"") + endif() + else() + message(STATUS "File \"${PROJECT_SOURCE_DIR}/.version\" did not exists.") + endif() +endif() + +if(NOT __detect_version) + message(FATAL_ERROR "Unable to determine project version") +endif() + + message(STATUS "stlink version: ${PROJECT_VERSION}") message(STATUS " Major ${PROJECT_VERSION_MAJOR} Minor ${PROJECT_VERSION_MINOR} Patch ${PROJECT_VERSION_PATCH}") From ecf86c735bdcdb82b098de52b5656c0d8ca94302 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sun, 1 Mar 2020 22:39:43 +0200 Subject: [PATCH 0719/1435] compare git version with .version --- .version | 2 +- cmake/Version.cmake | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/.version b/.version index dc1e644a1..ce6a70b9d 100644 --- a/.version +++ b/.version @@ -1 +1 @@ -1.6.0 +1.6.0 \ No newline at end of file diff --git a/cmake/Version.cmake b/cmake/Version.cmake index e5ce9f4c6..2ca1c0ff8 100644 --- a/cmake/Version.cmake +++ b/cmake/Version.cmake @@ -39,6 +39,15 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") list(GET PROJECT_VERSION_LIST 1 PROJECT_VERSION_MINOR) list(GET PROJECT_VERSION_LIST 2 PROJECT_VERSION_PATCH) set(__detect_version 1) + set(__version_str "${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}") + if(EXISTS "${PROJECT_SOURCE_DIR}/.version") + file(READ "${PROJECT_SOURCE_DIR}/.version" __version_file) + if(NOT __version_str STREQUAL __version_file) + message(STATUS "Rewrite ${PROJECT_SOURCE_DIR}/.version with ${__version_str}") + endif() + else() + file(WRITE "${PROJECT_SOURCE_DIR}/.version" ${__version_str}) + endif() else() message(STATUS "Fail to extract version's parts from \"${PROJECT_VERSION}\"") endif() From 268313bcabec25086eb7be51abd0012722bd0d48 Mon Sep 17 00:00:00 2001 From: Lutz Freitag Date: Sun, 15 Mar 2020 11:19:03 +0100 Subject: [PATCH 0720/1435] clear the PG bit before setting the PER bit after the flash loader ran the PG bit is still set in the CR register. in order to program the next page that page needs to be erased first and to get that working the PG bit has to be cleared so the flash controller knows what to do. this fixes #579 --- src/common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/common.c b/src/common.c index 6226c893b..95e504f9e 100644 --- a/src/common.c +++ b/src/common.c @@ -1893,6 +1893,9 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) /* unlock if locked */ unlock_flash_if(sl); + /* clear the pg bit */ + clear_flash_cr_pg(sl); + /* set the page erase bit */ set_flash_cr_per(sl); From b40c2436b68a35544a1eae10f4b6a3de7648a566 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 27 Feb 2020 01:56:59 +0100 Subject: [PATCH 0721/1435] Hotfix: Reverts commit 6692fdc. CKS32-Clone-Patch broke flashing on STM32 F3xx, F4xx and L1xx. (#761) --- include/stm32.h | 1 - src/flash_loader.c | 1 - 2 files changed, 2 deletions(-) diff --git a/include/stm32.h b/include/stm32.h index 858d2b22a..9a01baaf4 100644 --- a/include/stm32.h +++ b/include/stm32.h @@ -9,7 +9,6 @@ // cortex core ids #define STM32VL_CORE_ID 0x1ba01477 -#define CS32VL_CORE_ID 0x2ba01477 #define STM32F7_CORE_ID 0x5ba02477 // Constant STM32 memory map figures diff --git a/src/flash_loader.c b/src/flash_loader.c index 9f6e3a79d..f88a42eca 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -267,7 +267,6 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || - sl->core_id == CS32VL_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_F3 || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL || From 01ab4a979102d4812d11d037ec0041cdcce981b1 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 16 Mar 2020 12:15:23 +0100 Subject: [PATCH 0722/1435] Merged PR #825 Added support for G031/G041 chips. Closes #825. --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 6226c893b..0b80035f4 100644 --- a/src/common.c +++ b/src/common.c @@ -2637,7 +2637,7 @@ static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t l /* Check if chip is supported and for correct address */ if(sl->chip_id != STLINK_CHIPID_STM32_G0_CAT1 && - sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2) { + sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2) { ELOG("Option bytes writing is currently only supported for the STM32G0\n"); return -1; } From 5e70eb3dae66046d5e7b8a7e433480ed5e06c46f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 16 Mar 2020 12:57:38 +0100 Subject: [PATCH 0723/1435] Removed duplicated chip IDs. --- include/stlink/chipid.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index c0b0f3e13..368e157a7 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -75,8 +75,6 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_G4_CAT2 = 0x468, // See: RM 0440 s46.6.1 "MCU device ID code". STLINK_CHIPID_STM32_G4_CAT3 = 0x469, STLINK_CHIPID_STM32_L4RX = 0x470, // taken from the STM32L4R9I-DISCO board - STLINK_CHIPID_STM32_G0_CAT1 = 0x466, // G031/041 - STLINK_CHIPID_STM32_G0_CAT2 = 0x460, // G071/081 STLINK_CHIPID_STM32_WB55 = 0x495 }; From 1873ec70ffeb997ad355561070c87b270d31e674 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 16 Mar 2020 13:34:17 +0100 Subject: [PATCH 0724/1435] Removed duplicated chip IDs. --- include/stlink/chipid.h | 6 ++---- src/chipid.c | 13 +------------ 2 files changed, 3 insertions(+), 16 deletions(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index be5836990..f179db779 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -69,14 +69,12 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F72XXX = 0x452, /* This ID is found on the NucleoF722ZE board */ STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, - STLINK_CHIPID_STM32_G0_CAT2 = 0x460, // G071/081 + STLINK_CHIPID_STM32_G0_CAT2 = 0x460, // G070/G071/081 STLINK_CHIPID_STM32_F413 = 0x463, - STLINK_CHIPID_STM32_G0_CAT1 = 0x466, // G031/041 + STLINK_CHIPID_STM32_G0_CAT1 = 0x466, // G030/G031/041 STLINK_CHIPID_STM32_G4_CAT2 = 0x468, // See: RM 0440 s46.6.1 "MCU device ID code". STLINK_CHIPID_STM32_G4_CAT3 = 0x469, STLINK_CHIPID_STM32_L4RX = 0x470, // taken from the STM32L4R9I-DISCO board - STLINK_CHIPID_STM32_G07X = 0x460, // Actually, 'G070 and 'G071/081 - STLINK_CHIPID_STM32_G03X = 0x466, // Actually, 'G030 and 'G031/041 STLINK_CHIPID_STM32_WB55 = 0x495 }; diff --git a/src/chipid.c b/src/chipid.c index f595a7bf3..a978d91ef 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -522,7 +522,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x2000 }, { - // STM32GG030/031/041 (from RM0444) + // STM32G030/031/041 (from RM0454 & RM0444) .chip_id = STLINK_CHIPID_STM32_G0_CAT1, .description = "G030/G031/G041 device", .flash_type = STLINK_FLASH_TYPE_G0, @@ -554,17 +554,6 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7000 // 28K (table 2) }, - { - // STM32G031/041 (from RM0454 & RM0444) - .chip_id = STLINK_CHIPID_STM32_G03X, - .description = "G030/G031/G041 device", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2K (sec 3.2) - .sram_size = 0x2000, // 8K (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000 // 8k (table 2) - }, { // STM32WB55 (from RM0434) .chip_id = STLINK_CHIPID_STM32_WB55, From 44e2c375766f71f9a051ffaa5f2ba5b68af2ad86 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 16 Mar 2020 19:01:19 +0100 Subject: [PATCH 0725/1435] Whitespace cleanup. --- src/sg.c | 36 ++++-------------------------------- 1 file changed, 4 insertions(+), 32 deletions(-) diff --git a/src/sg.c b/src/sg.c index e7ff5d14e..8fa351cf6 100644 --- a/src/sg.c +++ b/src/sg.c @@ -109,8 +109,7 @@ void _stlink_sg_close(stlink_t *sl) { } } -static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, uint32_t *tag) -{ +static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, uint32_t *tag) { unsigned char csw[13]; memset(csw, 0, sizeof(csw)); int transferred; @@ -229,9 +228,7 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint * @param endpoint_in * @param endpoint_out */ - static void -get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_out) -{ +static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_out) { DLOG("Fetching sense...\n"); uint8_t cdb[16]; memset(cdb, 0, sizeof(cdb)); @@ -324,7 +321,6 @@ int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, return real_transferred; } - int stlink_q(stlink_t *sl) { struct stlink_libsg* sg = sl->backend_data; //uint8_t cdb_len = 6; // FIXME varies!!! @@ -385,7 +381,6 @@ int stlink_q(stlink_t *sl) { } // TODO thinking, cleanup - void stlink_stat(stlink_t *stl, char *txt) { if (stl->q_len <= 0) return; @@ -404,7 +399,6 @@ void stlink_stat(stlink_t *stl, char *txt) { } } - int _stlink_sg_version(stlink_t *stl) { struct stlink_libsg *sl = stl->backend_data; clear_cdb(sl); @@ -417,7 +411,6 @@ int _stlink_sg_version(stlink_t *stl) { // Get stlink mode: // STLINK_DEV_DFU_MODE || STLINK_DEV_MASS_MODE || STLINK_DEV_DEBUG_MODE // usb dfu || usb mass || jtag or swd - int _stlink_sg_current_mode(stlink_t *stl) { struct stlink_libsg *sl = stl->backend_data; clear_cdb(sl); @@ -431,7 +424,6 @@ int _stlink_sg_current_mode(stlink_t *stl) { } // Exit the mass mode and enter the swd debug mode. - int _stlink_sg_enter_swd_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -443,7 +435,6 @@ int _stlink_sg_enter_swd_mode(stlink_t *sl) { // Exit the mass mode and enter the jtag debug mode. // (jtag is disabled in the discovery's stlink firmware) - int _stlink_sg_enter_jtag_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_enter_jtag_mode ***\n"); @@ -525,7 +516,6 @@ int _stlink_sg_core_id(stlink_t *sl) { } // Arm-core reset -> halted state. - int _stlink_sg_reset(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -545,7 +535,6 @@ int _stlink_sg_reset(stlink_t *sl) { } // Arm-core reset -> halted state. - int _stlink_sg_jtag_reset(stlink_t *sl, int value) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -562,7 +551,6 @@ int _stlink_sg_jtag_reset(stlink_t *sl, int value) { } // Arm-core status: halted or running. - int _stlink_sg_status(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -573,7 +561,6 @@ int _stlink_sg_status(stlink_t *sl) { } // Force the core into the debug mode -> halted state. - int _stlink_sg_force_debug(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -588,7 +575,6 @@ int _stlink_sg_force_debug(stlink_t *sl) { } // Read all arm-core registers. - int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { struct stlink_libsg *sg = sl->backend_data; @@ -696,7 +682,6 @@ int _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int idx) { // Write a register of the debug module of the core. // XXX ?(atomic writes) // TODO test - void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_write_dreg ***\n"); @@ -713,7 +698,6 @@ void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { } // Force the core exit the debug mode. - int _stlink_sg_run(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -729,7 +713,6 @@ int _stlink_sg_run(stlink_t *sl) { } // Step the arm-core. - int _stlink_sg_step(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -764,7 +747,6 @@ void stlink_set_hw_bp(stlink_t *sl, int fp_nr, uint32_t addr, int fp) { } // TODO test - // TODO make delegate! void stlink_clr_hw_bp(stlink_t *sl, int fp_nr) { struct stlink_libsg *sg = sl->backend_data; @@ -779,7 +761,6 @@ void stlink_clr_hw_bp(stlink_t *sl, int fp_nr) { } // Read a "len" bytes to the sl->q_buf from the memory, max 6kB (6144 bytes) - int _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -804,7 +785,6 @@ int _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { } // Write a "len" bytes from the sl->q_buf to the memory, max 64 Bytes. - int _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; int ret; @@ -833,7 +813,6 @@ int _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { } // Write a "len" bytes from the sl->q_buf to the memory, max Q_BUF_LEN bytes. - int _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; int ret; @@ -862,7 +841,6 @@ int _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { } // Write one DWORD data to memory - int _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -875,7 +853,6 @@ int _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { } // Read one DWORD data from memory - int _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -891,9 +868,7 @@ int _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { } // Exit the jtag or swd mode and enter the mass mode. - -int _stlink_sg_exit_debug_mode(stlink_t *stl) -{ +int _stlink_sg_exit_debug_mode(stlink_t *stl) { if (stl) { struct stlink_libsg* sl = stl->backend_data; clear_cdb(sl); @@ -905,7 +880,6 @@ int _stlink_sg_exit_debug_mode(stlink_t *stl) return 0; } - // 1) open a sg device, switch the stlink from dfu to mass mode // 2) wait 5s until the kernel driver stops reseting the broken device // 3) reopen the device @@ -943,7 +917,6 @@ static stlink_backend_t _stlink_sg_backend = { }; static stlink_t* stlink_open(const int verbose) { - stlink_t *sl = malloc(sizeof (stlink_t)); struct stlink_libsg *slsg = malloc(sizeof (struct stlink_libsg)); if (sl == NULL || slsg == NULL) { @@ -965,7 +938,7 @@ static stlink_t* stlink_open(const int verbose) { #if defined (__FreeBSD__) #define LIBUSBX_API_VERSION LIBUSB_API_VERSION -#endif +#endif #if LIBUSBX_API_VERSION < 0x01000106 libusb_set_debug(slsg->libusb_ctx, 3); #else @@ -984,7 +957,6 @@ static stlink_t* stlink_open(const int verbose) { // TODO // Could read the interface config descriptor, and assert lots of the assumptions - // assumption: numInterfaces is always 1... if (libusb_kernel_driver_active(slsg->usb_handle, 0) == 1) { int r = libusb_detach_kernel_driver(slsg->usb_handle, 0); From 946f8638c1e5cf0e0f487c04ab3d1d2e69a70322 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 17 Mar 2020 20:48:45 +0100 Subject: [PATCH 0726/1435] Updated CHANGELOG.md for Release v1.3.0 --- CHANGELOG.md | 57 ++++++++++++++++++++++++++++++---------------------- 1 file changed, 33 insertions(+), 24 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 2832464a2..022701580 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -117,13 +117,13 @@ Major changes and added features: Updates and fixes: +* Fixed gdb-server: L0xx has no FP_CTRL register for breakpoints ([#273](https://github.com/texane/stlink/pull/273)) * Fixed compilation with GCC 7 ([#590](https://github.com/texane/stlink/pull/590)) * Skipped GTK detection if we're cross-compiling ([#588](https://github.com/texane/stlink/pull/588)) * Fixed possible memory leak ([#570](https://github.com/texane/stlink/pull/570)) * Fixed building with mingw64 ([#569](https://github.com/texane/stlink/pull/569), [#610](https://github.com/texane/stlink/pull/610)) * Updated libusb to 1.0.21 for Windows ([#562](https://github.com/texane/stlink/pull/562)) * Fixed low-voltage flashing on STM32F7 parts. ([#567](https://github.com/texane/stlink/pull/567)) -* Updated libusb to 1.0.21 for Windows ([#562](https://github.com/texane/stlink/pull/562)) v1.3.1 ====== @@ -151,36 +151,48 @@ Release date: 2017-01-28 Major changes and added features: * Deprecation of autotools (autoconf, automake) ([#83](https://github.com/texane/stlink/pull/83), [#431](https://github.com/texane/stlink/pull/431), [#434](https://github.com/texane/stlink/pull/434)) -* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#3fd0f09](https://github.com/texane/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) -* Added support for native debian packaging ([#444](https://github.com/texane/stlink/pull/444), [#485](https://github.com/texane/stlink/pull/485)) * Added intel hex file reading for `st-flash` ([#110](https://github.com/texane/stlink/pull/110), [#157](https://github.com/texane/stlink/pull/157), [#200](https://github.com/texane/stlink/pull/200), [#239](https://github.com/texane/stlink/pull/239), [#457](https://github.com/texane/stlink/pull/547), [#459](https://github.com/texane/stlink/pull/549)) -* Added `--reset` command to `st-flash` ([#505](https://github.com/texane/stlink/pull/505)) -* Support serial numbers argument for `st-util` and `st-flash` for multi-programmer setups ([#541](https://github.com/texane/stlink/pull/541)) -* Added kill ('k') command to gdb-server for `st-util` ([#9804416](https://github.com/texane/stlink/commit/98044163ab34bf5159f121d1c49ffb3550321ca0)) -* Added manpages (generated with pandoc from Markdown) ([#464](https://github.com/texane/stlink/pull/464)) -* Rewritten commandline parsing for `st-flash` ([#459](https://github.com/texane/stlink/pull/459)) +* Added manpages (generated with pandoc from Markdown) ([#208](https://github.com/texane/stlink/pull/208), [#464](https://github.com/texane/stlink/pull/464), [#466](https://github.com/texane/stlink/pull/466), [#467](https://github.com/texane/stlink/pull/467)) +* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/texane/stlink/pull/228), ([#507](https://github.com/texane/stlink/pull/507), commit [#2c0ab7f](https://github.com/texane/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) +* Support serial numbers argument for `st-util` and `st-flash` to probe and control multiple connected programmers ([#318](https://github.com/texane/stlink/pull/318), [#398](https://github.com/texane/stlink/pull/398), [#541](https://github.com/texane/stlink/pull/541)) +* Merge st-probe tool into st-info ([#398](https://github.com/texane/stlink/pull/398)) +* Added support for native debian packaging ([#444](https://github.com/texane/stlink/pull/444), [#472](https://github.com/texane/stlink/pull/472), [#473](https://github.com/texane/stlink/pull/473), [#482](https://github.com/texane/stlink/pull/482), [#483](https://github.com/texane/stlink/pull/483), [#484](https://github.com/texane/stlink/pull/484), [#485](https://github.com/texane/stlink/pull/485)) * Added support for ARM semihosting to `st-util` ([#454](https://github.com/texane/stlink/pull/454), [#455](https://github.com/texane/stlink/pull/455)) +* Rewritten commandline parsing for `st-flash` ([#459](https://github.com/texane/stlink/pull/459)) +* Added `--reset` command to `st-flash` ([#505](https://github.com/texane/stlink/pull/505)) +* st-util should detect when USB commands fail ([#525](https://github.com/texane/stlink/pull/525), ([#527](https://github.com/texane/stlink/pull/527), ([#528](https://github.com/texane/stlink/pull/528)) + Chip support added for: -* STM32L432 ([#501](https://github.com/texane/stlink/pull/501)) -* STM32F412 ([#538](https://github.com/texane/stlink/pull/538)) -* STM32F410 ([#9c635e4](https://github.com/texane/stlink/commit/9c635e419deca697ff823000aad2e39d47ec8d6c)) -* Added memory map for STM32F401XE ([#460](https://github.com/texane/stlink/pull/460)) -* L0x Category 5 devices ([#406](https://github.com/texane/stlink/pull/406)) -* Added L0 Category 2 device (chip id: 0x425) ([#72b8e5e](https://github.com/texane/stlink/commit/72b8e5ec87e4fa386a8e94fe68df29467d4354ce)) +* STM32F401XE: Added memory map for device ([#460](https://github.com/texane/stlink/pull/460)) +* STM32F410RBTx ([#418](https://github.com/texane/stlink/pull/418)) +* STM32F412 ([#537](https://github.com/texane/stlink/pull/537), [#538](https://github.com/texane/stlink/pull/538)) +* STM32F7xx ([#324](https://github.com/texane/stlink/pull/324), [#326](https://github.com/texane/stlink/pull/326), [#327](https://github.com/texane/stlink/pull/327), [#337](https://github.com/texane/stlink/pull/337)) +* STM32F767ZI ([#509](https://github.com/texane/stlink/pull/509)) +* STM32L0xx Cat2 devices (chip id: 0x425) ([#414](https://github.com/texane/stlink/pull/414)) +* STM32L0xx Cat5 devices (chip id: 0x447) ([#406](https://github.com/texane/stlink/pull/406)) +* STM32L4xx ([#321](https://github.com/texane/stlink/pull/321)) +* STM32L432 ([#500](https://github.com/texane/stlink/pull/500), [#501](https://github.com/texane/stlink/pull/501)) + Updates and fixes: * Set SWDCLK and fixed jtag_reset bug ([#254](https://github.com/texane/stlink/pull/254), [#291](https://github.com/texane/stlink/pull/291), [#475](https://github.com/texane/stlink/pull/475), [#533](https://github.com/texane/stlink/pull/533), [#534](https://github.com/texane/stlink/pull/534)) -* Fixed STM32F030 erase error ([#442](https://github.com/texane/stlink/pull/442)) -* Fixed Cygwin build ([#68b0f3b](https://github.com/texane/stlink/commit/68b0f3bddc3c4aaffe34caa6a3201029edd8ad56)) -* Reset flash mass erase (MER) bit after mass erase for safety ([#489](https://github.com/texane/stlink/pull/489)) -* Fixed memory map for STM32F4 (@zulusw) +* Fixed "unaligned addr or size" when trying to write a program in RAM ([#323](https://github.com/texane/stlink/pull/323)) +* Fixed flashing on STM32_F3_SMALL ([#325](https://github.com/texane/stlink/pull/325)) * Fixed STM32L-problem with flash loader ([#390](https://github.com/texane/stlink/pull/390)) -* `st-util` don't read target voltage on startup as it crashes STM32F100 (probably stlink/v1) (Greg Alexander) -* Do a JTAG reset prior to reading CPU information when processor is in deep sleep (@andyg24) +* Don't read the target voltage on startup, because it crashes STM32F100 ([#423](https://github.com/texane/stlink/pull/423), [#424](https://github.com/texane/stlink/pull/424)) +* Added a useful error message instead of "[!] send_recv" ([#425](https://github.com/texane/stlink/pull/425), [#426](https://github.com/texane/stlink/pull/426)) +* Do a JTAG reset prior to reading CPU information when processor is in deep sleep ([#428](https://github.com/texane/stlink/pull/428), [#430](https://github.com/texane/stlink/pull/430), [#451](https://github.com/texane/stlink/pull/451)) +* Fixed STM32F030 erase error ([#442](https://github.com/texane/stlink/pull/442)) +* Fixed memory map for STM32F7xx ([#453](https://github.com/texane/stlink/pull/453), [#456](https://github.com/texane/stlink/pull/456)) * Redesign of `st-flash` commandline options parsing ([#459](https://github.com/texane/stlink/pull/459)) +* Fixed Release target to generate the man-pages with pandoc ([#479](https://github.com/texane/stlink/pull/479)) +* Fixed Cygwin build ([#487](https://github.com/texane/stlink/pull/487), ([#506](https://github.com/texane/stlink/pull/506)) +* Reset flash mass erase (MER) bit after mass erase for safety ([#489](https://github.com/texane/stlink/pull/489)) +* Wrong extract command in FindLibUSB.cmake ([#510](https://github.com/texane/stlink/pull/510), [#511](https://github.com/texane/stlink/pull/511)) + v1.2.0 ====== @@ -193,12 +205,9 @@ Features added: * Added stlink usb probe API functions (Jerry Jacobs) * Added parameter to specify one stlink v2 of many (Georg von Zengen) -Changes: - -* Refactoring/fixes of flash loader (Maxime Coquelin) - Updates and fixes: +* Refactoring/fixes of flash loader (Maxime Coquelin) * Synchronized cache for stm32f7 (Tristan Gingold) * Allow flashing of STM32L4 down to 1.71 V (Greg Meiste) * Fix on stm32l4 to clear flash mass erase flags on CR (Bruno Dal Bo) From 35fff921f572d520359c89966dbc0212218b9666 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 18 Mar 2020 00:27:40 +0100 Subject: [PATCH 0727/1435] Updated CHANGELOG.md for Release v1.3.1 --- CHANGELOG.md | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 022701580..3d453a2d6 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -132,15 +132,17 @@ Release date: 2017-02-25 Major changes and added features: -* Added preliminary support for STM32L011 to see it after probe (chipid `0x457`) (@xor-gate) -* Stripped full paths to source files in log (commit [#2c0ab7f](https://github.com/texane/stlink/commit/2c0ab7f0eb6cfda5cfbdc08bb9f6760d27c2b667)) -* Added support for STM32F413 target ([#549](https://github.com/texane/stlink/pull/549)) * Added support for Semihosting `SYS_READC` ([#546](https://github.com/texane/stlink/pull/546)) +* Added support for STM32F413 ([#549](https://github.com/texane/stlink/pull/549), [#550](https://github.com/texane/stlink/pull/550)) +* Added preliminary support for STM32L011 to see it after probe (chipid `0x457`) ([#558](https://github.com/texane/stlink/pull/558)) Updates and fixes: -* Updated documentation markdown files -* Compilation fixes ([#552](https://github.com/texane/stlink/pull/552)) +* cmake/CPackConfig.cmake: Fixup OSX zip filename +* Updated source repositories in README.md: Windows, macOS, Alpine Linux +* Stripped full paths to source files in log ([#548](https://github.com/texane/stlink/pull/548)) +* Compilation fixes ([#551](https://github.com/texane/stlink/pull/551), [#552](https://github.com/texane/stlink/pull/552)) +* Fixed incorrect release folder name in docs ([#560](https://github.com/texane/stlink/pull/560)) * Fixed compilation when path includes spaces ([#561](https://github.com/texane/stlink/pull/561)) v1.3.0 @@ -162,7 +164,6 @@ Major changes and added features: * Added `--reset` command to `st-flash` ([#505](https://github.com/texane/stlink/pull/505)) * st-util should detect when USB commands fail ([#525](https://github.com/texane/stlink/pull/525), ([#527](https://github.com/texane/stlink/pull/527), ([#528](https://github.com/texane/stlink/pull/528)) - Chip support added for: * STM32F401XE: Added memory map for device ([#460](https://github.com/texane/stlink/pull/460)) @@ -175,7 +176,6 @@ Chip support added for: * STM32L4xx ([#321](https://github.com/texane/stlink/pull/321)) * STM32L432 ([#500](https://github.com/texane/stlink/pull/500), [#501](https://github.com/texane/stlink/pull/501)) - Updates and fixes: * Set SWDCLK and fixed jtag_reset bug ([#254](https://github.com/texane/stlink/pull/254), [#291](https://github.com/texane/stlink/pull/291), [#475](https://github.com/texane/stlink/pull/475), [#533](https://github.com/texane/stlink/pull/533), [#534](https://github.com/texane/stlink/pull/534)) From ff8334f0ee34243834327da08e0432890b0a8920 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 18 Mar 2020 11:46:37 +0100 Subject: [PATCH 0728/1435] Updated CHANGELOG.md for Release v1.4.0 --- CHANGELOG.md | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 3d453a2d6..f1d45ce2c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -53,6 +53,7 @@ General project updates: * Fixed travis build config file (Nightwalker-87) * Archived page from github project wiki to doc/wiki_old.md (Nightwalker-87) + v1.5.1 ====== @@ -84,6 +85,7 @@ Fixes: * Fix for mem_write() ([#730](https://github.com/texane/stlink/pull/730)) * FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION ([#733](https://github.com/texane/stlink/pull/733)) + v1.5.0 ====== @@ -102,6 +104,7 @@ Fixes: * Fixed verification of flash error for STM32L496x device ([#618](https://github.com/texane/stlink/pull/618)) * Fixed build on Fedora with GCC 8 ([#666](https://github.com/texane/stlink/pull/668)) + v1.4.0 ====== @@ -109,21 +112,28 @@ Release date: 2017-07-01 Major changes and added features: -* Added support for STM32L452 target ([#608](https://github.com/texane/stlink/pull/608)) -* Initial support to compile with Microsoft Visual Studio 2017 ([#602](https://github.com/texane/stlink/pull/602)) +* Allow building of debian package with CPack ([#554](https://github.com/texane/stlink/pull/554), commit [#2c0ab7f](https://github.com/texane/stlink/commit/5b69f25198a1a8f34e2ee48d1ad20f79447e3d55)) +* Added support for STM32L011 target ([#564](https://github.com/texane/stlink/pull/564), [#565](https://github.com/texane/stlink/pull/565), [#572](https://github.com/texane/stlink/pull/572)) * Added support for flashing second bank on STM32F10x_XL ([#592](https://github.com/texane/stlink/pull/592)) -* Added support for STM32L011 target ([#572](https://github.com/texane/stlink/pull/572)) -* Allow building of debian package with CPack (@xor-gate) +* Initial support to compile with Microsoft Visual Studio 2017 ([#602](https://github.com/texane/stlink/pull/602)) +* Added support for STM32L452 target ([#603](https://github.com/texane/stlink/pull/603), [#608](https://github.com/texane/stlink/pull/608)) Updates and fixes: * Fixed gdb-server: L0xx has no FP_CTRL register for breakpoints ([#273](https://github.com/texane/stlink/pull/273)) -* Fixed compilation with GCC 7 ([#590](https://github.com/texane/stlink/pull/590)) -* Skipped GTK detection if we're cross-compiling ([#588](https://github.com/texane/stlink/pull/588)) -* Fixed possible memory leak ([#570](https://github.com/texane/stlink/pull/570)) -* Fixed building with mingw64 ([#569](https://github.com/texane/stlink/pull/569), [#610](https://github.com/texane/stlink/pull/610)) * Updated libusb to 1.0.21 for Windows ([#562](https://github.com/texane/stlink/pull/562)) -* Fixed low-voltage flashing on STM32F7 parts. ([#567](https://github.com/texane/stlink/pull/567)) +* Fixed low-voltage flashing on STM32F7 devices ([#566](https://github.com/texane/stlink/pull/566), [#567](https://github.com/texane/stlink/pull/567)) +* Fixed building with mingw64 ([#569](https://github.com/texane/stlink/pull/569), [#573](https://github.com/texane/stlink/pull/573), [#578](https://github.com/texane/stlink/pull/578), [#584](https://github.com/texane/stlink/pull/584), [#610](https://github.com/texane/stlink/pull/610)) +* Fixed possible memory leak ([#570](https://github.com/texane/stlink/pull/570), [#571](https://github.com/texane/stlink/pull/571)) +* Added --flash=n[k][m] command line option to override device model ([#576](https://github.com/texane/stlink/pull/576)) +* Fixed installation path for shared objects ([#581](https://github.com/texane/stlink/pull/581)) +* Fixed a few -Wformat warnings ([#582](https://github.com/texane/stlink/pull/582)) +* Removed unused defines in mimgw.h ([#583](https://github.com/texane/stlink/pull/583)) +* Skip GTK detection when cross-compiling ([#588](https://github.com/texane/stlink/pull/588)) +* Fixed compilation with GCC 7 ([#590](https://github.com/texane/stlink/pull/590), [#591](https://github.com/texane/stlink/pull/591)) +* Fixed flashing to 'f0 device' targets ([#594](https://github.com/texane/stlink/pull/594), [#595](https://github.com/texane/stlink/pull/595)) +* Fix wrong counting when flashing ([#605](https://github.com/texane/stlink/pull/605)) + v1.3.1 ====== @@ -134,17 +144,18 @@ Major changes and added features: * Added support for Semihosting `SYS_READC` ([#546](https://github.com/texane/stlink/pull/546)) * Added support for STM32F413 ([#549](https://github.com/texane/stlink/pull/549), [#550](https://github.com/texane/stlink/pull/550)) -* Added preliminary support for STM32L011 to see it after probe (chipid `0x457`) ([#558](https://github.com/texane/stlink/pull/558)) +* Added preliminary support for STM32L011 to see it after probe (chipid `0x457`) ([#558](https://github.com/texane/stlink/pull/558), [#598](https://github.com/texane/stlink/pull/598)) Updates and fixes: * cmake/CPackConfig.cmake: Fixup OSX zip filename * Updated source repositories in README.md: Windows, macOS, Alpine Linux +* Compilation fixes ([#547](https://github.com/texane/stlink/pull/547), [#551](https://github.com/texane/stlink/pull/551), [#552](https://github.com/texane/stlink/pull/552)) * Stripped full paths to source files in log ([#548](https://github.com/texane/stlink/pull/548)) -* Compilation fixes ([#551](https://github.com/texane/stlink/pull/551), [#552](https://github.com/texane/stlink/pull/552)) * Fixed incorrect release folder name in docs ([#560](https://github.com/texane/stlink/pull/560)) * Fixed compilation when path includes spaces ([#561](https://github.com/texane/stlink/pull/561)) + v1.3.0 ====== From b1f143ad30547e694010aa52bd34e0aeff2dbe26 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 18 Mar 2020 14:19:41 +0100 Subject: [PATCH 0729/1435] Updated CHANGELOG.md for Release v1.5.0 --- CHANGELOG.md | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index f1d45ce2c..7079f8b15 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -93,17 +93,21 @@ Release date: 2018-02-16 Major changes and added features: -* STM32F72xx73xx support ([#1969148](https://github.com/texane/stlink/commit/19691485359afef1a256964afcbb8dcf4b733209)) * Added support of STM32L496xx/4A6xx devices ([#615](https://github.com/texane/stlink/pull/615)) +* Added unknown chip dummy to obtain the serial of the ST-link by a call to st-info --probe ([#641](https://github.com/texane/stlink/pull/641)) +* Added support for STM32F72xx (chip id: 0x452) devices (commit [#1969148](https://github.com/texane/stlink/commit/19691485359afef1a256964afcbb8dcf4b733209)) -Fixes: +Updates and fixes: -* Fixed memory map for stm32l496xx boards ([#639](https://github.com/texane/stlink/pull/639)) +* Fixed verification of flash error for STM32L496x device ([#617](https://github.com/texane/stlink/pull/617), [#618](https://github.com/texane/stlink/pull/618)) +* Updated Linux source repositories in README.md: Gentoo, Fedora and RedHat/CentOS ([#622](https://github.com/texane/stlink/pull/622), [#635](https://github.com/texane/stlink/pull/635)) +* Updated changelog in debian package ([#630](https://github.com/texane/stlink/pull/630)) +* Added LIB_INSTALL_DIR to correct libs install on 64-bit systems ([#633](https://github.com/texane/stlink/pull/633), [#636](https://github.com/texane/stlink/pull/636)) * Fixed write for microcontroller with RAM size less or equal to 32K ([#637](https://github.com/texane/stlink/pull/637)) -* Added LIB_INSTALL_DIR to correct libs install on 64-bit systems ([#636](https://github.com/texane/stlink/pull/636)) -* Fixed verification of flash error for STM32L496x device ([#618](https://github.com/texane/stlink/pull/618)) -* Fixed build on Fedora with GCC 8 ([#666](https://github.com/texane/stlink/pull/668)) - +* Fixed memory map for stm32l496xx boards ([#639](https://github.com/texane/stlink/pull/639)) +* Fixed __FILE__ base name extraction ([#624](https://github.com/texane/stlink/pull/624), [#628](https://github.com/texane/stlink/pull/628), [#648](https://github.com/texane/stlink/pull/648)) +* Added debian/triggers to run ldconfig ([#664](https://github.com/texane/stlink/pull/664)) +* Fixed build on Fedora with GCC 8 ([#666](https://github.com/texane/stlink/pull/666), [#667](https://github.com/texane/stlink/pull/667), [#668](https://github.com/texane/stlink/pull/668)) v1.4.0 ====== From 975fcb06728927ae9428f5babe727724f09c8c69 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 18 Mar 2020 19:27:04 +0100 Subject: [PATCH 0730/1435] Updated CHANGELOG.md for Release v1.5.1 --- CHANGELOG.md | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 7079f8b15..f19a443b6 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -61,28 +61,31 @@ Release date: 2018-09-13 Major changes and added features: +* Added reset through AIRCR ([#540](https://github.com/texane/stlink/pull/540), [#712](https://github.com/texane/stlink/pull/712)) +* Added creation of icons for .desktop file ([#684](https://github.com/texane/stlink/pull/684), [#708](https://github.com/texane/stlink/pull/708)) +* Added desktop file for linux ([#688](https://github.com/texane/stlink/pull/688)) * Added button to export stm32 flash memory to a file ([#691](https://github.com/texane/stlink/pull/691)) * Updated libusb to 1.0.22 ([#695](https://github.com/texane/stlink/pull/695)) -* Added desktop file for linux ([#688](https://github.com/texane/stlink/pull/688)) * Added icons for stlink GUI ([#697](https://github.com/texane/stlink/pull/697)) * Added support for STM32L4R9 target ([#694](https://github.com/texane/stlink/pull/694), [#699](https://github.com/texane/stlink/pull/699)) -* Added creation of icons for .desktop file ([#708](https://github.com/texane/stlink/pull/708)) * Added memory map for STM32F411RE target ([#709](https://github.com/texane/stlink/pull/709)) -* Added reset through AIRCR ([#540](https://github.com/texane/stlink/pull/540), [#712](https://github.com/texane/stlink/pull/712)) -* Implemented intel hex support for GTK GUI ([#718](https://github.com/texane/stlink/pull/718)) +* Implemented intel hex support for GTK GUI ([#713](https://github.com/texane/stlink/pull/713), [#718](https://github.com/texane/stlink/pull/718)) -Fixes: +Updates and fixes: -* Fixed missing flash_loader for L011 ([#675](https://github.com/texane/stlink/pull/675)) -* Fixed serial number size mismatch with stlink_open_usb() ([#680](https://github.com/texane/stlink/pull/680)) -* Debian packaging, CMake and README.md fixes ([#683](https://github.com/texane/stlink/pull/683)) +* Fixed missing flash_loader for L011 ([#356](https://github.com/texane/stlink/pull/356), [#654](https://github.com/texane/stlink/pull/654), [#675](https://github.com/texane/stlink/pull/675)) * Fix for stlink library calls exit() or _exit() ([#634](https://github.com/texane/stlink/pull/634), [#696](https://github.com/texane/stlink/pull/696)) +* Added semihosting parameter documentation in doc/man ([#674](https://github.com/texane/stlink/pull/674)) +* Fixed reference to non-exisiting st-term tool in doc/man ([#676](https://github.com/texane/stlink/pull/676)) +* Fixed serial number size mismatch with stlink_open_usb() ([#680](https://github.com/texane/stlink/pull/680)) +* Debian packaging, CMake and README.md fixes ([#682](https://github.com/texane/stlink/pull/682), [#683](https://github.com/texane/stlink/pull/683)) +* Disabled static library installation by default ([#702](https://github.com/texane/stlink/pull/702)) * Fix for libusb deprecation ([#703](https://github.com/texane/stlink/pull/703), [#704](https://github.com/texane/stlink/pull/704)) * Renamed STLINK_CHIPID_STM32_L4R9 to STLINK_CHIPID_STM32_L4RX ([#706](https://github.com/texane/stlink/pull/706)) -* Fixed flash memory map for F72XXX target ([#711](https://github.com/texane/stlink/pull/711)) -* Proper flash page size calculation for F412 target ([#721](https://github.com/texane/stlink/pull/721)) -* Return correct value on EOF for Semihosting SYS_READ ([#726](https://github.com/texane/stlink/pull/726), [#729](https://github.com/texane/stlink/pull/729), [#731](https://github.com/texane/stlink/pull/731)) -* Fix for mem_write() ([#730](https://github.com/texane/stlink/pull/730)) +* Regression: stlink installation under Linux (Debian 9) is broken since #695 ([#700](https://github.com/texane/stlink/pull/700), [#701](https://github.com/texane/stlink/pull/701), [#707](https://github.com/texane/stlink/pull/707)) +* Fixed flash memory map for F72xxx target ([#711](https://github.com/texane/stlink/pull/711)) +* Proper flash page size calculation for F412xx target ([#721](https://github.com/texane/stlink/pull/721)) +* Return correct value on EOF for Semihosting SYS_READ ([#726](https://github.com/texane/stlink/pull/726), [#727](https://github.com/texane/stlink/pull/727), [#729](https://github.com/texane/stlink/pull/729), [#730](https://github.com/texane/stlink/pull/730), [#731](https://github.com/texane/stlink/pull/731)) * FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION ([#733](https://github.com/texane/stlink/pull/733)) @@ -109,6 +112,7 @@ Updates and fixes: * Added debian/triggers to run ldconfig ([#664](https://github.com/texane/stlink/pull/664)) * Fixed build on Fedora with GCC 8 ([#666](https://github.com/texane/stlink/pull/666), [#667](https://github.com/texane/stlink/pull/667), [#668](https://github.com/texane/stlink/pull/668)) + v1.4.0 ====== From bc423e2e26a6b9de843a2170bfd78fd70464fec4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 18 Mar 2020 23:00:51 +0100 Subject: [PATCH 0731/1435] Added missing tickets to CHANGELOG.md --- CHANGELOG.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index f19a443b6..30cd219f5 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -85,7 +85,7 @@ Updates and fixes: * Regression: stlink installation under Linux (Debian 9) is broken since #695 ([#700](https://github.com/texane/stlink/pull/700), [#701](https://github.com/texane/stlink/pull/701), [#707](https://github.com/texane/stlink/pull/707)) * Fixed flash memory map for F72xxx target ([#711](https://github.com/texane/stlink/pull/711)) * Proper flash page size calculation for F412xx target ([#721](https://github.com/texane/stlink/pull/721)) -* Return correct value on EOF for Semihosting SYS_READ ([#726](https://github.com/texane/stlink/pull/726), [#727](https://github.com/texane/stlink/pull/727), [#729](https://github.com/texane/stlink/pull/729), [#730](https://github.com/texane/stlink/pull/730), [#731](https://github.com/texane/stlink/pull/731)) +* Return correct value on EOF for Semihosting SYS_READ ([#726](https://github.com/texane/stlink/pull/726), [#727](https://github.com/texane/stlink/pull/727), [#728](https://github.com/texane/stlink/pull/728), [#729](https://github.com/texane/stlink/pull/729), [#730](https://github.com/texane/stlink/pull/730), [#731](https://github.com/texane/stlink/pull/731), [#732](https://github.com/texane/stlink/pull/732)) * FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION ([#733](https://github.com/texane/stlink/pull/733)) @@ -211,6 +211,7 @@ Updates and fixes: * Fixed Cygwin build ([#487](https://github.com/texane/stlink/pull/487), ([#506](https://github.com/texane/stlink/pull/506)) * Reset flash mass erase (MER) bit after mass erase for safety ([#489](https://github.com/texane/stlink/pull/489)) * Wrong extract command in FindLibUSB.cmake ([#510](https://github.com/texane/stlink/pull/510), [#511](https://github.com/texane/stlink/pull/511)) +* Fixed compilation error on Ubuntu 16.10 ([#514](https://github.com/texane/stlink/pull/514), [#525](https://github.com/texane/stlink/pull/525)) v1.2.0 From 116f4e58f62c15e24fd7c48613873c483ec9b968 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 18 Mar 2020 23:11:46 +0100 Subject: [PATCH 0732/1435] Removed CKS32F103 in tested-boards.md --- doc/tested-boards.md | 1 - 1 file changed, 1 deletion(-) diff --git a/doc/tested-boards.md b/doc/tested-boards.md index b28163a30..ebc47c2ac 100644 --- a/doc/tested-boards.md +++ b/doc/tested-boards.md @@ -7,7 +7,6 @@ Known working targets: * STM32F100xx (Medium Density VL) * STM32F103 (according to jpa- on ##stm32) -* CKS32F103 (chinese STM32F103-Clone) No information: From 13c62114393f12a9b4d3cfc574cfabedfed50d5c Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Thu, 19 Mar 2020 15:21:27 +0100 Subject: [PATCH 0733/1435] changed text for F72/F73 --- src/chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/chipid.c b/src/chipid.c index df07d524f..f04c3eaa6 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -27,7 +27,7 @@ static const struct stlink_chipid_params devices[] = { { //RM0431 and DS document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F72XXX, - .description = "F72 device", + .description = "F72/F73 device", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1ff07a22, // section 35.2 .flash_pagesize = 0x800, // No flash pages From b8813fab9734521a1857189aab5dbf2a30d37ea4 Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Thu, 19 Mar 2020 17:47:34 +0100 Subject: [PATCH 0734/1435] Fixed long wait when the loader refuses to run. Fixes #290 --- src/flash_loader.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/flash_loader.c b/src/flash_loader.c index f88a42eca..9c24ff9e8 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -384,10 +384,20 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe /* run loader */ stlink_run(sl); -#define WAIT_ROUNDS 10000 +// This piece of code used to try to spin for .1 second by waiting +// doing 10000 rounds of 10 microseconds. But because this usually runs +// on Unix-like OSes, the 10 microseconds get rounded up to the "tick" +// (actually almost two ticks) of the system. 1 milisecond. Thus, the +// ten thousand attempts, when "something goes wrong" that requires +// the error message "flash loader run error" would wait for something +// like 20 seconds before coming up with the error. +// by increasing the sleep-per-round to the same order-of-magnitude as +// the tick-rounding that the OS uses, the wait until the error message is +// reduced to the same order of magnitude as what was intended. -- REW. +#define WAIT_ROUNDS 100 /* wait until done (reaches breakpoint) */ for (i = 0; i < WAIT_ROUNDS; i++) { - usleep(10); + usleep(1000); if (stlink_is_core_halted(sl)) break; } From 60db4e56dcded849b453c74e9d00aa8dd070bce6 Mon Sep 17 00:00:00 2001 From: petertorelli Date: Fri, 20 Mar 2020 08:43:58 -0700 Subject: [PATCH 0735/1435] Added more error info to WLOGs during probe. --- src/usb.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/usb.c b/src/usb.c index 9df9d7296..ad062735d 100644 --- a/src/usb.c +++ b/src/usb.c @@ -1102,9 +1102,9 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { /* Count stlink */ while ((dev = devs[i++]) != NULL) { struct libusb_device_descriptor desc; - int r = libusb_get_device_descriptor(dev, &desc); - if (r < 0) { - WLOG("failed to get libusb device descriptor\n"); + ret = libusb_get_device_descriptor(dev, &desc); + if (ret < 0) { + WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); break; } @@ -1133,7 +1133,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { struct libusb_device_descriptor desc; ret = libusb_get_device_descriptor(dev, &desc); if (ret < 0) { - WLOG("failed to get libusb device descriptor\n"); + WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); break; } @@ -1148,7 +1148,11 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { ret = libusb_open(dev, &handle); if (ret < 0) { - WLOG("failed to get libusb device descriptor\n"); + if (ret == LIBUSB_ERROR_ACCESS) { + WLOG("failed to open USB device (LIBUSB_ERROR_ACCESS), try running as root?\n"); + } else { + WLOG("failed to open USB device (libusb error: %d)\n", ret); + } break; } @@ -1159,7 +1163,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { libusb_close(handle); stlink_t *sl = NULL; - sl = stlink_open_usb(0, 1, serial); + sl = stlink_open_usb(0, 1, serial); if (!sl) continue; From c9efcba111171c8e03beeec81e93f55075204722 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 21 Mar 2020 00:26:59 +0100 Subject: [PATCH 0736/1435] Updated CHANGELOG.md for Release v1.6.0 --- CHANGELOG.md | 46 ++++++++++++++++++++++------------------------ 1 file changed, 22 insertions(+), 24 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 30cd219f5..3e3824a01 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -8,49 +8,47 @@ Release date: 2020-02-20 Major changes and added features: -* Added O_BINARY option to open file ([#753](https://github.com/texane/stlink/pull/753)) -* Added preliminary support for some STM32G0 chips ([#759](https://github.com/texane/stlink/pull/759), [#760](https://github.com/texane/stlink/pull/760)) +* Initial support for STM32L41X ([#754](https://github.com/texane/stlink/pull/754), [#799](https://github.com/texane/stlink/pull/799)) +* Added preliminary support for some STM32G0 chips ([#759](https://github.com/texane/stlink/pull/759), [#760](https://github.com/texane/stlink/pull/760), [#797](https://github.com/texane/stlink/pull/797)) * Added support for mass erasing second bank on STM32F10x_XL ([#767](https://github.com/texane/stlink/pull/767), [#768](https://github.com/texane/stlink/pull/768)) * Added call to clear PG bit after writing to flash ([#773](https://github.com/texane/stlink/pull/773)) -* Added howto for sending NRST signal through GDB ([#774](https://github.com/texane/stlink/pull/774), [#776](https://github.com/texane/stlink/pull/776)) * Added support to write option bytes for the STM32G0 ([#778](https://github.com/texane/stlink/pull/778)) -* Added simple read/write support for STM32WB55 chips ([#786](https://github.com/texane/stlink/pull/786)) +* Added support for STM32WB55 chips ([#786](https://github.com/texane/stlink/pull/786), [#810](https://github.com/texane/stlink/pull/810), [#816](https://github.com/texane/stlink/pull/816)) * Added STLink V3SET VID:PIDs to the udev rules ([#789](https://github.com/texane/stlink/pull/789)) * Support for "STM32+Audio" v2-1 firmware ([#790](https://github.com/texane/stlink/pull/790)) -* Initial support for STM32L41X ([#799](https://github.com/texane/stlink/pull/799)) * Build for Windows under Debian/Ubuntu ([#802](https://github.com/texane/stlink/pull/802)) * Allow for 64 bytes serials ([#809](https://github.com/texane/stlink/pull/809)) -* Added support to read and write option bytes for STM32F2 series (Orie22) -* Added full support for STLINK CHIP ID L4RX (Brad Natelborg) -* Added support to write option bytes to STM32F4 devices (Davey Struijk) +* Added full support for STLINK CHIP ID L4RX ([#814](https://github.com/texane/stlink/pull/814), [#839](https://github.com/texane/stlink/pull/839)) +* Added support for writing option bytes on STM32L0 ([#830](https://github.com/texane/stlink/pull/830)) +* Added support to read and write option bytes for STM32F2 series ([#836](https://github.com/texane/stlink/pull/836), [#837](https://github.com/texane/stlink/pull/837)) +* Added support to read and write option bytes for STM32F446 ([#843](https://github.com/texane/stlink/pull/843)) Updates and fixes: -* Build failure when platform is 32 bit, but stuct stat.st_size is 64 bit. ([#629](https://github.com/texane/stlink/pull/629)) +* Updated STM32F3xx chip ID that covers a few different devices ([#685](https://github.com/texane/stlink/pull/685), [#758](https://github.com/texane/stlink/pull/758)) * Made udev rules and modprobe conf installation optional ([#741](https://github.com/texane/stlink/pull/741)) -* Fixed case when __FILE__ don't contain "/" nor "\\". ([#745](https://github.com/texane/stlink/pull/745)) -* Fixed double dash issue in doc/man ([#746](https://github.com/texane/stlink/pull/746)) -* Fixed Debug error on line 123 in CMakeLists.txt (@xor-gate) -* Only do bank calculation on STM32L4 devices with dual banked flash ([#751](https://github.com/texane/stlink/pull/751)) -* Updated STM32F3xx chip ID that covers a few different devices ([#758](https://github.com/texane/stlink/pull/758)) +* Fixed case when __FILE__ don't contain "/" nor "\\" ([#745](https://github.com/texane/stlink/pull/745)) +* Fixed double dash issue in doc/man ([#746](https://github.com/texane/stlink/pull/746), [#747](https://github.com/texane/stlink/pull/747)) +* Compiling documentation: package is called libusb-1.0-0-dev on Debian ([#748](https://github.com/texane/stlink/pull/748)) +* Only do bank calculation on STM32L4 devices with dual banked flash / Added chip ID 0x464 for STM32L41xxx/L42xxx devices ([#751](https://github.com/texane/stlink/pull/751)) +* Added O_BINARY option to open file ([#753](https://github.com/texane/stlink/pull/753)) * Fixed versioning when compiling from the checked out git-repo ([#762](https://github.com/texane/stlink/pull/762)) -* Fixed "unkown chip id", piped output and st-util -v ([#107](https://github.com/texane/stlink/pull/107), [#763](https://github.com/texane/stlink/pull/763)) +* Fixed "unkown chip id", piped output and st-util -v ([#107](https://github.com/texane/stlink/pull/107), [#665](https://github.com/texane/stlink/pull/665), [#763](https://github.com/texane/stlink/pull/763)) * win32: move usleep definition to unistd.h ([#765](https://github.com/texane/stlink/pull/765)) * Fixed relative path to the UI files needed by stlink-gui-local (GUI) ([#770](https://github.com/texane/stlink/pull/770), [#771](https://github.com/texane/stlink/pull/771)) +* Added howto for sending NRST signal through GDB ([#774](https://github.com/texane/stlink/pull/774), [#776](https://github.com/texane/stlink/pull/776), [#779](https://github.com/texane/stlink/pull/779)) * Fixed package name "devscripts" in doc/compiling.md ([#775](https://github.com/texane/stlink/pull/775)) -* Fixed apparent STM32G0 flashing issue ([#797](https://github.com/texane/stlink/pull/797)) * Fixed few potential memory/resource leaks ([#803](https://github.com/texane/stlink/pull/803)) -* Fixed flash verification error on STM32WB55RG ([#810](https://github.com/texane/stlink/pull/810), [#816](https://github.com/texane/stlink/pull/816)) -* Do not issue JTAG reset on stlink-v1 (Gwenhael Goavec-Merou) -* Fixed flash size of STM32 Discovery vl (Gwenhael Goavec-Merou) -* Added support for writing option bytes on STM32L0 (Adrian Imboden) +* Do not issue JTAG reset on stlink-v1 ([#828](https://github.com/texane/stlink/pull/828)) +* Fixed flash size of STM32 Discovery vl ([#829](https://github.com/texane/stlink/pull/829)) +* Updated Linux source repositories in README.md: Debian and Ubuntu ([#821](https://github.com/texane/stlink/pull/821), [#835](https://github.com/texane/stlink/pull/835), [#859](https://github.com/texane/stlink/pull/859)) * Updated documentation on software structure ([#851](https://github.com/texane/stlink/pull/851)) General project updates: -* Updated issue templates, README.md and CHANGELOG.md (Nightwalker-87) -* Added CODE_OF_CONDUCT (Nightwalker-87) +* Updated README.md, CHANGELOG.md and issue templates (Nightwalker-87) * Fixed travis build config file (Nightwalker-87) +* Added CODE_OF_CONDUCT (Nightwalker-87) * Archived page from github project wiki to doc/wiki_old.md (Nightwalker-87) @@ -140,7 +138,7 @@ Updates and fixes: * Skip GTK detection when cross-compiling ([#588](https://github.com/texane/stlink/pull/588)) * Fixed compilation with GCC 7 ([#590](https://github.com/texane/stlink/pull/590), [#591](https://github.com/texane/stlink/pull/591)) * Fixed flashing to 'f0 device' targets ([#594](https://github.com/texane/stlink/pull/594), [#595](https://github.com/texane/stlink/pull/595)) -* Fix wrong counting when flashing ([#605](https://github.com/texane/stlink/pull/605)) +* Fixed wrong counting when flashing ([#605](https://github.com/texane/stlink/pull/605)) v1.3.1 @@ -171,7 +169,7 @@ Release date: 2017-01-28 Major changes and added features: -* Deprecation of autotools (autoconf, automake) ([#83](https://github.com/texane/stlink/pull/83), [#431](https://github.com/texane/stlink/pull/431), [#434](https://github.com/texane/stlink/pull/434)) +* Deprecation of autotools (autoconf, automake) and fixed build with MinGW ([#83](https://github.com/texane/stlink/pull/83), [#431](https://github.com/texane/stlink/pull/431), [#434](https://github.com/texane/stlink/pull/434), [#465](https://github.com/texane/stlink/pull/465)) * Added intel hex file reading for `st-flash` ([#110](https://github.com/texane/stlink/pull/110), [#157](https://github.com/texane/stlink/pull/157), [#200](https://github.com/texane/stlink/pull/200), [#239](https://github.com/texane/stlink/pull/239), [#457](https://github.com/texane/stlink/pull/547), [#459](https://github.com/texane/stlink/pull/549)) * Added manpages (generated with pandoc from Markdown) ([#208](https://github.com/texane/stlink/pull/208), [#464](https://github.com/texane/stlink/pull/464), [#466](https://github.com/texane/stlink/pull/466), [#467](https://github.com/texane/stlink/pull/467)) * Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/texane/stlink/pull/228), ([#507](https://github.com/texane/stlink/pull/507), commit [#2c0ab7f](https://github.com/texane/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) From c8a2f133f0703a434da05e89148526806225e364 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 21 Mar 2020 01:59:05 +0100 Subject: [PATCH 0737/1435] General Project Update - Minor documentation fixes - HOWTO and FAQ --> tutorial.md --- CHANGELOG.md | 2 +- README.md | 123 ------------------------------------------ doc/release.md | 2 +- doc/tutorial.md | 138 +++++++++++++++++++++++++++++++++++++++++++++--- 4 files changed, 134 insertions(+), 131 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 3e3824a01..e6356caf3 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -39,9 +39,9 @@ Updates and fixes: * Added howto for sending NRST signal through GDB ([#774](https://github.com/texane/stlink/pull/774), [#776](https://github.com/texane/stlink/pull/776), [#779](https://github.com/texane/stlink/pull/779)) * Fixed package name "devscripts" in doc/compiling.md ([#775](https://github.com/texane/stlink/pull/775)) * Fixed few potential memory/resource leaks ([#803](https://github.com/texane/stlink/pull/803)) +* Updated Linux source repositories in README.md: Debian and Ubuntu ([#821](https://github.com/texane/stlink/pull/821), [#835](https://github.com/texane/stlink/pull/835), [#859](https://github.com/texane/stlink/pull/859)) * Do not issue JTAG reset on stlink-v1 ([#828](https://github.com/texane/stlink/pull/828)) * Fixed flash size of STM32 Discovery vl ([#829](https://github.com/texane/stlink/pull/829)) -* Updated Linux source repositories in README.md: Debian and Ubuntu ([#821](https://github.com/texane/stlink/pull/821), [#835](https://github.com/texane/stlink/pull/835), [#859](https://github.com/texane/stlink/pull/859)) * Updated documentation on software structure ([#851](https://github.com/texane/stlink/pull/851)) General project updates: diff --git a/README.md b/README.md index 3bc6c2c80..6a6fd4ae3 100644 --- a/README.md +++ b/README.md @@ -142,126 +142,3 @@ openocd: "\x30\x30\x30\x30\x30\x30\x30\x30\x30\x30\x30\x31" Try to remove the write protection (probably only possible with ST Link Utility from ST itself). Issue related to this bug: [#545](https://github.com/texane/stlink/issues/545) - - -# HOWTO -## Using the gdb server - -To run the gdb server: - -``` -$ make && [sudo] ./st-util - -There are a few options: - -./st-util - usage: - - -h, --help Print this help - -vXX, --verbose=XX Specify a specific verbosity level (0..99) - -v, --verbose Specify generally verbose logging - -s X, --stlink_version=X - Choose what version of stlink to use, (defaults to 2) - -1, --stlinkv1 Force stlink version 1 - -p 4242, --listen_port=1234 - Set the gdb server listen port. (default port: 4242) - -m, --multi - Set gdb server to extended mode. - st-util will continue listening for connections after disconnect. - -n, --no-reset - Do not reset board on connection. -``` - -The STLINKv2 device to use can be specified in the environment -variable `STLINK_DEVICE` in the format `:`. - -Then, in your project directory, someting like this... -(remember, you need to run an _ARM_ gdb, not an x86 gdb) - -``` -$ arm-none-eabi-gdb fancyblink.elf -... -(gdb) tar extended-remote :4242 -... -(gdb) load -Loading section .text, size 0x458 lma 0x8000000 -Loading section .data, size 0x8 lma 0x8000458 -Start address 0x80001c1, load size 1120 -Transfer rate: 1 KB/sec, 560 bytes/write. -(gdb) -... -(gdb) continue -``` - - -## Resetting the chip from GDB - -You may reset the chip using GDB if you want. You'll need to use `target -extended-remote' command like in this session: - -``` -(gdb) target extended-remote localhost:4242 -Remote debugging using localhost:4242 -0x080007a8 in _startup () -(gdb) kill -Kill the program being debugged? (y or n) y -(gdb) run -Starting program: /home/whitequark/ST/apps/bally/firmware.elf -``` - -Remember that you can shorten the commands. `tar ext :4242` is good enough -for GDB. - -If you need to send a hard reset signal through `NRST` pin, you can use the following command: - -``` -(gdb) monitor jtag_reset -``` - - -## Running programs from SRAM - -You can run your firmware directly from SRAM if you want to. Just link -it at 0x20000000 and do - -``` -(gdb) load firmware.elf -``` - -It will be loaded, and pc will be adjusted to point to start of the -code, if it is linked correctly (i.e. ELF has correct entry point). - - -## Writing to flash - -The GDB stub ships with a correct memory map, including the flash area. -If you would link your executable to `0x08000000` and then do - -``` -(gdb) load firmware.elf -``` - -then it would be written to the memory. - - -## Writing Option Bytes - -Example to read and write option bytes (currently writing only supported for STM32G0 and STM32L0) -``` -./st-flash --debug --reset --format binary --flash=128k read option_bytes_dump.bin 0x1FFF7800 4 -./st-flash --debug --reset --format binary --flash=128k write option_bytes_dump.bin 0x1FFF7800 -``` - - -## FAQ - -Q: My breakpoints do not work at all or only work once. - -A: Optimizations can cause severe instruction reordering. For example, if you are doing something like `REG = 0x100;' in a loop, the code may be split into two parts: loading 0x100 into some intermediate register and moving that value to REG. When you set up a breakpoint, GDB will hook to the first instruction, which may be called only once if there are enough unused registers. In my experience, -O3 causes that frequently. - -Q: At some point I use GDB command `next', and it hangs. - -A: Sometimes when you will try to use GDB `next` command to skip a loop, it will use a rather inefficient single-stepping way of doing that. Set up a breakpoint manually in that case and do `continue`. - -Q: Load command does not work in GDB. - -A: Some people report XML/EXPAT is not enabled by default when compiling GDB. Memory map parsing thus fail. Use --enable-expat. diff --git a/doc/release.md b/doc/release.md index c2dca87b2..ae8b864ee 100644 --- a/doc/release.md +++ b/doc/release.md @@ -1,7 +1,7 @@ Release ======= -This document describes the steps takes for developers to create a release +This document describes the steps it takes for developers to create a release 1. Update `.version` with semantic version: `x.x.x` 2. Update `README.md` with semantic version `x.x.x` in commits badge diff --git a/doc/tutorial.md b/doc/tutorial.md index 35c607ac0..af4bae849 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -37,7 +37,7 @@ Before continuing, the following dependencies must be met: Also make sure `gtk+` version 3.0 is installed. (`sudo apt-get install gtk+-3.0` or similiar) -STLINK should run on any system meeting the above constraints. +STLINK should run on any system meeting the above constraints. The STLINK software source code is retrieved using: @@ -62,7 +62,6 @@ It includes: Using the GDB server ==================== - This assumes you have got the libopencm3 project downloaded in `ocm3`. The libopencm3 project has some good, reliable examples for each of the @@ -85,11 +84,11 @@ the discovery kit you are using, you must run one of the 2 commands: $> ./st-util --stlinkv1 # STM32L or STM32F4 discovery kit (onboard ST-link/V2) -$> ./st-util +$> ./st-util # Full help for other options (listen port, version) $> ./st-util --help -``` +``` Then, GDB can be used to interact with the kit: @@ -113,7 +112,7 @@ command line, now we can simply “load” the target: ``` (gdb) load -``` +``` st-util will load all sections into their appropriate addresses, and “correctly” set the PC register. So, to run your freshly loaded program, @@ -127,6 +126,7 @@ Your program should now be running, and, if you used one of the blinking examples from libopencm3, the LEDs on the board should be blinking for you. + Building and flashing a program =============================== @@ -154,7 +154,7 @@ It is also possible to write a hexfile which is more convinient: $> ./st-flash --format ihex write myapp.hex ``` -#### +#### Of course, you can use this instead of the gdb server, if you prefer. Just remember to use the “.bin” image, rather than the .elf file. @@ -167,6 +167,132 @@ $> [sudo] ./st-flash write fancy_blink.bin 0x08000000 Upon reset, the board LEDs should be blinking. + +HOWTO +===== +## Using the gdb server + +To run the gdb server: + +``` +$ make && [sudo] ./st-util + +There are a few options: + +./st-util - usage: + + -h, --help Print this help + -vXX, --verbose=XX Specify a specific verbosity level (0..99) + -v, --verbose Specify generally verbose logging + -s X, --stlink_version=X + Choose what version of stlink to use, (defaults to 2) + -1, --stlinkv1 Force stlink version 1 + -p 4242, --listen_port=1234 + Set the gdb server listen port. (default port: 4242) + -m, --multi + Set gdb server to extended mode. + st-util will continue listening for connections after disconnect. + -n, --no-reset + Do not reset board on connection. +``` + +The STLINKv2 device to use can be specified in the environment +variable `STLINK_DEVICE` in the format `:`. + +Then, in your project directory, someting like this... +(remember, you need to run an _ARM_ gdb, not an x86 gdb) + +``` +$ arm-none-eabi-gdb fancyblink.elf +... +(gdb) tar extended-remote :4242 +... +(gdb) load +Loading section .text, size 0x458 lma 0x8000000 +Loading section .data, size 0x8 lma 0x8000458 +Start address 0x80001c1, load size 1120 +Transfer rate: 1 KB/sec, 560 bytes/write. +(gdb) +... +(gdb) continue +``` + + +## Resetting the chip from GDB + +You may reset the chip using GDB if you want. You'll need to use `target +extended-remote' command like in this session: + +``` +(gdb) target extended-remote localhost:4242 +Remote debugging using localhost:4242 +0x080007a8 in _startup () +(gdb) kill +Kill the program being debugged? (y or n) y +(gdb) run +Starting program: /home/whitequark/ST/apps/bally/firmware.elf +``` + +Remember that you can shorten the commands. `tar ext :4242` is good enough +for GDB. + +If you need to send a hard reset signal through `NRST` pin, you can use the following command: + +``` +(gdb) monitor jtag_reset +``` + + +## Running programs from SRAM + +You can run your firmware directly from SRAM if you want to. Just link +it at 0x20000000 and do + +``` +(gdb) load firmware.elf +``` + +It will be loaded, and pc will be adjusted to point to start of the +code, if it is linked correctly (i.e. ELF has correct entry point). + + +## Writing to flash + +The GDB stub ships with a correct memory map, including the flash area. +If you would link your executable to `0x08000000` and then do + +``` +(gdb) load firmware.elf +``` + +then it would be written to the memory. + + +## Writing Option Bytes + +Example to read and write option bytes (currently writing only supported for STM32G0 and STM32L0) +``` +./st-flash --debug --reset --format binary --flash=128k read option_bytes_dump.bin 0x1FFF7800 4 +./st-flash --debug --reset --format binary --flash=128k write option_bytes_dump.bin 0x1FFF7800 +``` + + +FAQ +=== + +Q: My breakpoints do not work at all or only work once. + +A: Optimizations can cause severe instruction reordering. For example, if you are doing something like `REG = 0x100;' in a loop, the code may be split into two parts: loading 0x100 into some intermediate register and moving that value to REG. When you set up a breakpoint, GDB will hook to the first instruction, which may be called only once if there are enough unused registers. In my experience, -O3 causes that frequently. + +Q: At some point I use GDB command `next', and it hangs. + +A: Sometimes when you will try to use GDB `next` command to skip a loop, it will use a rather inefficient single-stepping way of doing that. Set up a breakpoint manually in that case and do `continue`. + +Q: Load command does not work in GDB. + +A: Some people report XML/EXPAT is not enabled by default when compiling GDB. Memory map parsing thus fail. Use --enable-expat. + + Notes ===== From 784fdde0ae238bcb385be4d13850c3b78bbe602f Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 21 Mar 2020 14:48:40 +0200 Subject: [PATCH 0738/1435] check if app's need for libssp. --- CMakeLists.txt | 29 +++++++++++++++++++---------- src/gdbserver/CMakeLists.txt | 4 ++-- src/tools/gui/CMakeLists.txt | 4 ++-- tests/CMakeLists.txt | 4 ++-- 4 files changed, 25 insertions(+), 16 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 90378f9ed..d9e2bf6bd 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -57,6 +57,15 @@ if (STLINK_HAVE_UNISTD_H) add_definitions(-DSTLINK_HAVE_UNISTD_H) endif() +include(CheckLibraryExists) +CHECK_LIBRARY_EXISTS(ssp __stack_chk_fail "" _stack_chk_fail_exists) + +if(_stack_chk_fail_exists) + set(SSP_LIB ssp) +else() + set(SSP_LIB "") +endif() + if (CMAKE_BUILD_TYPE STREQUAL "") set(CMAKE_BUILD_TYPE "Debug") endif() @@ -135,13 +144,13 @@ if (APPLE) find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) find_library(IOKit IOKit) - target_link_libraries(${STLINK_LIB_SHARED} ${CoreFoundation} ${IOKit} ${ObjC}) + target_link_libraries(${STLINK_LIB_SHARED} ${CoreFoundation} ${IOKit} ${ObjC} ${SSP_LIB}) endif() if (WIN32 OR MSYS OR MINGW) - target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} wsock32 ws2_32) + target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} wsock32 ws2_32 ${SSP_LIB}) else() - target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY}) + target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB}) endif() @@ -164,13 +173,13 @@ if (APPLE) find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) find_library(IOKit IOKit) - target_link_libraries(${STLINK_LIB_STATIC} ${CoreFoundation} ${IOKit} ${ObjC}) + target_link_libraries(${STLINK_LIB_STATIC} ${CoreFoundation} ${IOKit} ${ObjC} ${SSP_LIB}) endif() if (WIN32 OR MSYS OR MINGW) - target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} wsock32 ws2_32) + target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} wsock32 ws2_32 ${SSP_LIB}) else() - target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY}) + target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB}) endif() set_target_properties(${STLINK_LIB_STATIC} PROPERTIES OUTPUT_NAME ${PROJECT_NAME}) @@ -186,16 +195,16 @@ endif() ### add_executable(st-flash src/tools/flash.c src/tools/flash_opts.c) if (WIN32 OR APPLE) - target_link_libraries(st-flash ${STLINK_LIB_STATIC}) + target_link_libraries(st-flash ${STLINK_LIB_STATIC} ${SSP_LIB}) else() - target_link_libraries(st-flash ${STLINK_LIB_SHARED}) + target_link_libraries(st-flash ${STLINK_LIB_SHARED} ${SSP_LIB}) endif() add_executable(st-info src/tools/info.c) if (WIN32 OR APPLE) - target_link_libraries(st-info ${STLINK_LIB_STATIC}) + target_link_libraries(st-info ${STLINK_LIB_STATIC} ${SSP_LIB}) else() - target_link_libraries(st-info ${STLINK_LIB_SHARED}) + target_link_libraries(st-info ${STLINK_LIB_SHARED} ${SSP_LIB}) endif() install(TARGETS st-flash st-info diff --git a/src/gdbserver/CMakeLists.txt b/src/gdbserver/CMakeLists.txt index 2393690ce..b4674ebbb 100644 --- a/src/gdbserver/CMakeLists.txt +++ b/src/gdbserver/CMakeLists.txt @@ -14,9 +14,9 @@ endif() add_executable(st-util ${STUTIL_SOURCE}) if (WIN32 OR APPLE) - target_link_libraries(st-util ${STLINK_LIB_STATIC}) + target_link_libraries(st-util ${STLINK_LIB_STATIC} ${SSP_LIB}) else() - target_link_libraries(st-util ${STLINK_LIB_SHARED}) + target_link_libraries(st-util ${STLINK_LIB_SHARED} ${SSP_LIB}) endif() install(TARGETS st-util diff --git a/src/tools/gui/CMakeLists.txt b/src/tools/gui/CMakeLists.txt index c619a0547..91aabc53b 100644 --- a/src/tools/gui/CMakeLists.txt +++ b/src/tools/gui/CMakeLists.txt @@ -10,13 +10,13 @@ include_directories(SYSTEM ${gtk_INCLUDE_DIRS}) add_executable(stlink-gui-local ${GUI_SOURCES}) set_target_properties(stlink-gui-local PROPERTIES COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_CURRENT_SOURCE_DIR}") -target_link_libraries(stlink-gui-local ${STLINK_LIB_STATIC} ${gtk_LDFLAGS}) +target_link_libraries(stlink-gui-local ${STLINK_LIB_STATIC} ${gtk_LDFLAGS} ${SSP_LIB}) add_executable(stlink-gui ${GUI_SOURCES}) set_target_properties(stlink-gui PROPERTIES COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/${INSTALLED_UI_DIR}") -target_link_libraries(stlink-gui ${STLINK_LIB_STATIC} ${gtk_LDFLAGS}) +target_link_libraries(stlink-gui ${STLINK_LIB_STATIC} ${gtk_LDFLAGS} ${SSP_LIB}) install(TARGETS stlink-gui RUNTIME DESTINATION bin) diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 8df28ce7e..9d0bdffaf 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -6,10 +6,10 @@ set(TESTS foreach(test ${TESTS}) add_executable(${test} ${test}.c) add_dependencies(${test} ${STLINK_LIB_STATIC}) - target_link_libraries(${test} ${STLINK_LIB_STATIC}) + target_link_libraries(${test} ${STLINK_LIB_STATIC} ${SSP_LIB}) add_test(${test} ${CMAKE_CURRENT_BINARY_DIR}/${test}) endforeach() add_executable(flash flash.c "${CMAKE_SOURCE_DIR}/src/tools/flash_opts.c") -target_link_libraries(flash ${STLINK_LIB_STATIC}) +target_link_libraries(flash ${STLINK_LIB_STATIC} ${SSP_LIB}) add_test(flash ${CMAKE_CURRENT_BINARY_DIR}/flash) From e75a5d22ef50c2cd6bd49e77b83c4ebd5b0b81ac Mon Sep 17 00:00:00 2001 From: Rogier Wolff Date: Sat, 21 Mar 2020 16:08:09 +0100 Subject: [PATCH 0739/1435] reduce clutter in output messages --- src/chipid.c | 96 +++++++++++++++++++------------------- src/common.c | 12 ++++- src/gdbserver/gdb-server.c | 5 +- src/usb.c | 4 +- 4 files changed, 65 insertions(+), 52 deletions(-) diff --git a/src/chipid.c b/src/chipid.c index f04c3eaa6..f296f2509 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -5,7 +5,7 @@ static const struct stlink_chipid_params devices[] = { { //RM0410 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F7XXXX, - .description = "F76xxx device", + .description = "F76xxx", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1ff0f442, // section 45.2 .flash_pagesize = 0x800, // No flash pages @@ -16,7 +16,7 @@ static const struct stlink_chipid_params devices[] = { { //RM0385 and DS10916 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F7, - .description = "F7 device", + .description = "F7xx", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1ff0f442, // section 41.2 .flash_pagesize = 0x800, // No flash pages @@ -27,7 +27,7 @@ static const struct stlink_chipid_params devices[] = { { //RM0431 and DS document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F72XXX, - .description = "F72/F73 device", + .description = "F72x/F73x", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1ff07a22, // section 35.2 .flash_pagesize = 0x800, // No flash pages @@ -37,7 +37,7 @@ static const struct stlink_chipid_params devices[] = { }, { // table 2, PM0063 .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, - .description = "F1 Medium-density device", + .description = "F1xx Medium-density", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, @@ -47,7 +47,7 @@ static const struct stlink_chipid_params devices[] = { }, { // table 1, PM0059 .chip_id = STLINK_CHIPID_STM32_F2, - .description = "F2 device", + .description = "F2xx", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/ .flash_pagesize = 0x20000, @@ -67,7 +67,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_F4, - .description = "F4 device", + .description = "F4xx", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, @@ -77,7 +77,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_F4_DSI, - .description = "F46x and F47x device", + .description = "F46x/F47x", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, @@ -87,7 +87,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_F4_HD, - .description = "F42x and F43x device", + .description = "F42x/F43x", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ .flash_pagesize = 0x4000, @@ -97,7 +97,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_F4_LP, - .description = "F4 device (low power)", + .description = "F4xx (low power)", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, @@ -107,7 +107,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_F411RE, - .description = "F4 device (low power) - stm32f411re", + .description = "stm32f411re", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, @@ -117,7 +117,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_F4_DE, - .description = "F4 device (Dynamic Efficency)", + .description = "F4xx (Dynamic Efficency)", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, @@ -127,7 +127,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_F1_HIGH, - .description = "F1 High-density device", + .description = "F1xx High-density", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -139,7 +139,7 @@ static const struct stlink_chipid_params devices[] = { // This ignores the EEPROM! (and uses the page erase size, // not the sector write protection...) .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM, - .description = "L1 Med-density device", + .description = "L1xx Medium-density", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, .flash_pagesize = 0x100, @@ -149,7 +149,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_L1_CAT2, - .description = "L1 Cat.2 device", + .description = "L1xx Cat.2", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, .flash_pagesize = 0x100, @@ -159,7 +159,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, - .description = "L1 Medium-Plus-density device", + .description = "L1xx Medium-Plus-density", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, @@ -169,7 +169,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_L1_HIGH, - .description = "L1 High-density device", + .description = "L1xx High-density", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, @@ -189,7 +189,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_F1_CONN, - .description = "F1 Connectivity line device", + .description = "F1 Connectivity line", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -199,7 +199,7 @@ static const struct stlink_chipid_params devices[] = { }, {//Low and Medium density VL have same chipid. RM0041 25.6.1 .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, - .description = "F1 Medium/Low-density Value Line device", + .description = "F1xx Value Line", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, @@ -210,7 +210,7 @@ static const struct stlink_chipid_params devices[] = { { // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. .chip_id = STLINK_CHIPID_STM32_F446, - .description = "F446 device", + .description = "F446", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1fff7a22, .flash_pagesize = 0x20000, @@ -221,7 +221,7 @@ static const struct stlink_chipid_params devices[] = { { // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. .chip_id = STLINK_CHIPID_STM32_F410, - .description = "F410 device", + .description = "F410", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1fff7a22, .flash_pagesize = 0x4000, @@ -233,7 +233,7 @@ static const struct stlink_chipid_params devices[] = { // This is STK32F303VCT6 device from STM32 F3 Discovery board. // Support based on DM00043574.pdf (RM0316) document. .chip_id = STLINK_CHIPID_STM32_F3, - .description = "F3 device", + .description = "F3xx", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, @@ -245,7 +245,7 @@ static const struct stlink_chipid_params devices[] = { // This is STK32F373VCT6 device from STM32 F373 eval board // Support based on 303 above (37x and 30x have same memory map) .chip_id = STLINK_CHIPID_STM32_F37x, - .description = "F3 device", + .description = "F3xx", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, @@ -255,7 +255,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, - .description = "F1 High-density value line device", + .description = "F1xx High-density value line", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -265,7 +265,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_F1_XL, - .description = "F1 XL-density device", + .description = "F1xx XL-density", .flash_type = STLINK_FLASH_TYPE_F1_XL, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -277,7 +277,7 @@ static const struct stlink_chipid_params devices[] = { //Use this as an example for mapping future chips: //RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F0_CAN, - .description = "F07x device", + .description = "F07x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 @@ -289,7 +289,7 @@ static const struct stlink_chipid_params devices[] = { //Use this as an example for mapping future chips: //RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F0, - .description = "F0 device", + .description = "F0xx", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 @@ -301,7 +301,7 @@ static const struct stlink_chipid_params devices[] = { // RM0402 document was used to find these parameters // Table 4. .chip_id = STLINK_CHIPID_STM32_F412, - .description = "F4 device", + .description = "F412", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) .flash_pagesize = 0x4000, // Table 5. Flash module organization ? @@ -313,7 +313,7 @@ static const struct stlink_chipid_params devices[] = { // RM0430 DocID029473 Rev 2 document was used to find these parameters // Figure 2, Table 4, Table 5, Section 35.2 .chip_id = STLINK_CHIPID_STM32_F413, - .description = "F4 device", + .description = "F413", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector sizes, but 0x4000 is smallest) @@ -323,7 +323,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_F09X, - .description = "F09X device", + .description = "F09X", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) @@ -335,7 +335,7 @@ static const struct stlink_chipid_params devices[] = { //Use this as an example for mapping future chips: //RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F04, - .description = "F04x device", + .description = "F04x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 @@ -347,7 +347,7 @@ static const struct stlink_chipid_params devices[] = { //Use this as an example for mapping future chips: //RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F0_SMALL, - .description = "F0 small device", + .description = "F0xx small", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 @@ -358,7 +358,7 @@ static const struct stlink_chipid_params devices[] = { { // STM32F30x .chip_id = STLINK_CHIPID_STM32_F3_SMALL, - .description = "F3 small device", + .description = "F3xx small", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, @@ -370,7 +370,7 @@ static const struct stlink_chipid_params devices[] = { // STM32L0x // RM0367,RM0377 documents was used to find these parameters .chip_id = STLINK_CHIPID_STM32_L0, - .description = "L0x3 device", + .description = "L0x3", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, @@ -382,7 +382,7 @@ static const struct stlink_chipid_params devices[] = { // STM32L0x Category 5 // RM0367,RM0377 documents was used to find these parameters .chip_id = STLINK_CHIPID_STM32_L0_CAT5, - .description = "L0x Category 5 device", + .description = "L0xx Category 5", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, @@ -394,7 +394,7 @@ static const struct stlink_chipid_params devices[] = { // STM32L0x Category 2 // RM0367,RM0377 documents was used to find these parameters .chip_id = STLINK_CHIPID_STM32_L0_CAT2, - .description = "L0x Category 2 device", + .description = "L0xx Category 2", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, @@ -406,7 +406,7 @@ static const struct stlink_chipid_params devices[] = { // STM32F334, STM32F303x6/8, and STM32F328 // From RM0364 and RM0316 .chip_id = STLINK_CHIPID_STM32_F334, - .description = "F3xx medium density device", // (RM0316 sec 33.6.1) + .description = "F334 medium density", // (RM0316 sec 33.6.1) .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, @@ -418,7 +418,7 @@ static const struct stlink_chipid_params devices[] = { // This is STK32F303RET6 device from STM32 F3 Nucelo board. // Support based on DM00043574.pdf (RM0316) document rev 5. .chip_id = STLINK_CHIPID_STM32_F303_HIGH, - .description = "F303 high density device", + .description = "F303 high density", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register .flash_pagesize = 0x800, // 4.2.1 Flash memory organization @@ -430,7 +430,7 @@ static const struct stlink_chipid_params devices[] = { // STM32L4x6 // From RM0351. .chip_id = STLINK_CHIPID_STM32_L4, - .description = "L4 device", + .description = "L4xx", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81) @@ -445,7 +445,7 @@ static const struct stlink_chipid_params devices[] = { // STM32L4RX // From DM00310109.pdf .chip_id = STLINK_CHIPID_STM32_L4RX, - .description = "L4Rx device", + .description = "L4Rx", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049) .flash_pagesize = 0x1000, // 4k, section 3.3, pg 97 @@ -457,7 +457,7 @@ static const struct stlink_chipid_params devices[] = { // STLINK_CHIPID_STM32_L41X // From RM0394 Rev 4 and DS12469 Rev 5 .chip_id = STLINK_CHIPID_STM32_L41X, - .description = "L41x device", + .description = "L41x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, sec 47.2, page 1586) .flash_pagesize = 0x800, // 2K (DS12469, sec 3.4, page 17) @@ -471,7 +471,7 @@ static const struct stlink_chipid_params devices[] = { // STLINK_CHIPID_STM32_L43X // From RM0392. .chip_id = STLINK_CHIPID_STM32_L43X, - .description = "L43x/L44x device", + .description = "L43x/L44x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) .flash_pagesize = 0x800, // 2K (sec 3.2, page 74; also appears in sec 3.3.1 and tables 7-8 on pages 75-76) @@ -486,7 +486,7 @@ static const struct stlink_chipid_params devices[] = { // STLINK_CHIPID_STM32_L496X // Support based on en.DM00083560.pdf (RM0351) document rev 5. .chip_id = STLINK_CHIPID_STM32_L496X, - .description = "L496x/L4A6x device", + .description = "L496x/L4A6x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) @@ -500,7 +500,7 @@ static const struct stlink_chipid_params devices[] = { // STLINK_CHIPID_STM32_L46X // From RM0394 (updated version of RM0392?). .chip_id = STLINK_CHIPID_STM32_L46X, - .description = "L45x/46x device", + .description = "L45x/46x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) .flash_pagesize = 0x800, // 2K (sec 3.2, page 73; also appears in sec 3.3.1 and tables 7 on pages 73-74) @@ -513,7 +513,7 @@ static const struct stlink_chipid_params devices[] = { { // STM32L011 .chip_id = STLINK_CHIPID_STM32_L011, - .description = "L011 device", + .description = "L011", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, @@ -524,7 +524,7 @@ static const struct stlink_chipid_params devices[] = { { // STM32GG030/031/041 (from RM0444) .chip_id = STLINK_CHIPID_STM32_G0_CAT1, - .description = "G030/G031/G041 device", + .description = "G030/G031/G041", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2K (sec 3.2) @@ -535,7 +535,7 @@ static const struct stlink_chipid_params devices[] = { { // STM32G071/081 (from RM0444) .chip_id = STLINK_CHIPID_STM32_G0_CAT2, - .description = "G070/G071/G081 device", + .description = "G070/G071/G081", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2K (sec 3.2) @@ -546,7 +546,7 @@ static const struct stlink_chipid_params devices[] = { { // STM32G431/441 (from RM0440) .chip_id = STLINK_CHIPID_STM32_G4_CAT2, - .description = "G4 Category-2 device", + .description = "G4 Category-2", .flash_type = STLINK_FLASH_TYPE_G4, .flash_size_reg = 0x1FFF75E0, // Section 47.2 .flash_pagesize = 0x800, // 2K (sec 3.3.1) @@ -557,7 +557,7 @@ static const struct stlink_chipid_params devices[] = { { // STM32WB55 (from RM0434) .chip_id = STLINK_CHIPID_STM32_WB55, - .description = "WB55 device", + .description = "WB55", .flash_type = STLINK_FLASH_TYPE_WB, .flash_size_reg = 0x1FFF75E0, .flash_pagesize = 0x1000, // 4K diff --git a/src/common.c b/src/common.c index 6226c893b..a6d60c552 100644 --- a/src/common.c +++ b/src/common.c @@ -830,7 +830,9 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { * @return 0 for success, or -1 for unsupported core type. */ int stlink_load_device_params(stlink_t *sl) { - ILOG("Loading device parameters....\n"); + // This seems to normally work so is unnecessary info for a normal + // user. Demoted to debug. -- REW + DLOG("Loading device parameters....\n"); const struct stlink_chipid_params *params = NULL; stlink_core_id(sl); uint32_t chip_id; @@ -894,11 +896,19 @@ int stlink_load_device_params(stlink_t *sl) { sl->sram_size = 0x1000; } +#if 0 + // Old code -- REW ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); // TODO make note of variable page size here..... ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %u bytes\n", sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, (unsigned int)sl->flash_pgsz); +#else + ILOG("%s: %d KiB SRAM, %d KiB flash in %d %s pages.\n", + params->description, sl->sram_size / 1024, sl->flash_size / 1024, + (sl->flash_pgsz < 1024)? sl->flash_pgsz : sl->flash_pgsz/1024, + (sl->flash_pgsz < 1024)? "byte" : "KiB"); +#endif return 0; } diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index a874a81da..72f676bb2 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -246,8 +246,9 @@ int main(int argc, char** argv) { } - - ILOG("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); + // This is low-level information for debugging, not useful for normal use. + // So: Demoted to a debug meesage. -- REW + DLOG("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); sl->verbose=0; current_memory_map = make_memory_map(sl); diff --git a/src/usb.c b/src/usb.c index 9df9d7296..85f5727a4 100644 --- a/src/usb.c +++ b/src/usb.c @@ -1049,7 +1049,9 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST stlink_version(sl); if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { - ILOG("-- exit_dfu_mode\n"); + // This seems to work, and is unnecessary information for the user. + // Demoted to debug -- REW + DLOG("-- exit_dfu_mode\n"); stlink_exit_dfu_mode(sl); } From d439956cb2ce5222fa8cfaa7992a90f4cef98eae Mon Sep 17 00:00:00 2001 From: Rogier Wolff Date: Sat, 21 Mar 2020 17:34:54 +0100 Subject: [PATCH 0740/1435] now return error in probe when things go bad. --- src/usb.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/usb.c b/src/usb.c index 9df9d7296..8c932e71e 100644 --- a/src/usb.c +++ b/src/usb.c @@ -1069,15 +1069,17 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST } ret = stlink_load_device_params(sl); - -on_libusb_error: if (ret == -1) { - stlink_close(sl); - return NULL; + // This one didn't have any message. + goto on_libusb_error; } - return sl; +on_libusb_error: + stlink_close(sl); + return NULL; + + on_error: if (slu->libusb_ctx) libusb_exit(slu->libusb_ctx); From e49ad2770ede3377cd4865210c6f88a42ce48378 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 21 Mar 2020 21:31:12 +0200 Subject: [PATCH 0741/1435] fix intendation in Version.cmake --- cmake/Version.cmake | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/cmake/Version.cmake b/cmake/Version.cmake index 2ca1c0ff8..71859015c 100644 --- a/cmake/Version.cmake +++ b/cmake/Version.cmake @@ -7,15 +7,15 @@ set(__detect_version 0) find_package (Git) if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") - # Working off a git repo, using git versioning - # Check if HEAD is pointing to a tag - execute_process ( - COMMAND "${GIT_EXECUTABLE}" describe --always --tag - WORKING_DIRECTORY "${PROJECT_SOURCE_DIR}" - OUTPUT_VARIABLE PROJECT_VERSION + # Working off a git repo, using git versioning + # Check if HEAD is pointing to a tag + execute_process ( + COMMAND "${GIT_EXECUTABLE}" describe --always --tag + WORKING_DIRECTORY "${PROJECT_SOURCE_DIR}" + OUTPUT_VARIABLE PROJECT_VERSION RESULT_VARIABLE GIT_DESCRIBE_RESULT ERROR_VARIABLE GIT_DESCRIBE_ERROR - OUTPUT_STRIP_TRAILING_WHITESPACE) + OUTPUT_STRIP_TRAILING_WHITESPACE) if(GIT_DESCRIBE_RESULT EQUAL 0) # If the sources have been changed locally, add -dirty to the version. From 4df1caf4f4f463b69276136b648c693586896ba1 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 22 Mar 2020 00:47:39 +0100 Subject: [PATCH 0742/1435] Minor fixes in CHANGELOG.md --- CHANGELOG.md | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index e6356caf3..586e44206 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -19,7 +19,7 @@ Major changes and added features: * Build for Windows under Debian/Ubuntu ([#802](https://github.com/texane/stlink/pull/802)) * Allow for 64 bytes serials ([#809](https://github.com/texane/stlink/pull/809)) * Added full support for STLINK CHIP ID L4RX ([#814](https://github.com/texane/stlink/pull/814), [#839](https://github.com/texane/stlink/pull/839)) -* Added support for writing option bytes on STM32L0 ([#830](https://github.com/texane/stlink/pull/830)) +* Added support for writing option bytes on STM32L0xx ([#830](https://github.com/texane/stlink/pull/830)) * Added support to read and write option bytes for STM32F2 series ([#836](https://github.com/texane/stlink/pull/836), [#837](https://github.com/texane/stlink/pull/837)) * Added support to read and write option bytes for STM32F446 ([#843](https://github.com/texane/stlink/pull/843)) @@ -62,16 +62,16 @@ Major changes and added features: * Added reset through AIRCR ([#540](https://github.com/texane/stlink/pull/540), [#712](https://github.com/texane/stlink/pull/712)) * Added creation of icons for .desktop file ([#684](https://github.com/texane/stlink/pull/684), [#708](https://github.com/texane/stlink/pull/708)) * Added desktop file for linux ([#688](https://github.com/texane/stlink/pull/688)) -* Added button to export stm32 flash memory to a file ([#691](https://github.com/texane/stlink/pull/691)) +* Added button to export STM32 flash memory to a file ([#691](https://github.com/texane/stlink/pull/691)) * Updated libusb to 1.0.22 ([#695](https://github.com/texane/stlink/pull/695)) -* Added icons for stlink GUI ([#697](https://github.com/texane/stlink/pull/697)) +* Added icons for STLink GUI ([#697](https://github.com/texane/stlink/pull/697)) * Added support for STM32L4R9 target ([#694](https://github.com/texane/stlink/pull/694), [#699](https://github.com/texane/stlink/pull/699)) * Added memory map for STM32F411RE target ([#709](https://github.com/texane/stlink/pull/709)) * Implemented intel hex support for GTK GUI ([#713](https://github.com/texane/stlink/pull/713), [#718](https://github.com/texane/stlink/pull/718)) Updates and fixes: -* Fixed missing flash_loader for L011 ([#356](https://github.com/texane/stlink/pull/356), [#654](https://github.com/texane/stlink/pull/654), [#675](https://github.com/texane/stlink/pull/675)) +* Fixed missing flash_loader for STM32L011 ([#356](https://github.com/texane/stlink/pull/356), [#654](https://github.com/texane/stlink/pull/654), [#675](https://github.com/texane/stlink/pull/675)) * Fix for stlink library calls exit() or _exit() ([#634](https://github.com/texane/stlink/pull/634), [#696](https://github.com/texane/stlink/pull/696)) * Added semihosting parameter documentation in doc/man ([#674](https://github.com/texane/stlink/pull/674)) * Fixed reference to non-exisiting st-term tool in doc/man ([#676](https://github.com/texane/stlink/pull/676)) @@ -81,8 +81,8 @@ Updates and fixes: * Fix for libusb deprecation ([#703](https://github.com/texane/stlink/pull/703), [#704](https://github.com/texane/stlink/pull/704)) * Renamed STLINK_CHIPID_STM32_L4R9 to STLINK_CHIPID_STM32_L4RX ([#706](https://github.com/texane/stlink/pull/706)) * Regression: stlink installation under Linux (Debian 9) is broken since #695 ([#700](https://github.com/texane/stlink/pull/700), [#701](https://github.com/texane/stlink/pull/701), [#707](https://github.com/texane/stlink/pull/707)) -* Fixed flash memory map for F72xxx target ([#711](https://github.com/texane/stlink/pull/711)) -* Proper flash page size calculation for F412xx target ([#721](https://github.com/texane/stlink/pull/721)) +* Fixed flash memory map for STM32F72xxx target ([#711](https://github.com/texane/stlink/pull/711)) +* Proper flash page size calculation for STM32F412xx target ([#721](https://github.com/texane/stlink/pull/721)) * Return correct value on EOF for Semihosting SYS_READ ([#726](https://github.com/texane/stlink/pull/726), [#727](https://github.com/texane/stlink/pull/727), [#728](https://github.com/texane/stlink/pull/728), [#729](https://github.com/texane/stlink/pull/729), [#730](https://github.com/texane/stlink/pull/730), [#731](https://github.com/texane/stlink/pull/731), [#732](https://github.com/texane/stlink/pull/732)) * FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION ([#733](https://github.com/texane/stlink/pull/733)) @@ -105,7 +105,7 @@ Updates and fixes: * Updated changelog in debian package ([#630](https://github.com/texane/stlink/pull/630)) * Added LIB_INSTALL_DIR to correct libs install on 64-bit systems ([#633](https://github.com/texane/stlink/pull/633), [#636](https://github.com/texane/stlink/pull/636)) * Fixed write for microcontroller with RAM size less or equal to 32K ([#637](https://github.com/texane/stlink/pull/637)) -* Fixed memory map for stm32l496xx boards ([#639](https://github.com/texane/stlink/pull/639)) +* Fixed memory map for STM32L496xx boards ([#639](https://github.com/texane/stlink/pull/639)) * Fixed __FILE__ base name extraction ([#624](https://github.com/texane/stlink/pull/624), [#628](https://github.com/texane/stlink/pull/628), [#648](https://github.com/texane/stlink/pull/648)) * Added debian/triggers to run ldconfig ([#664](https://github.com/texane/stlink/pull/664)) * Fixed build on Fedora with GCC 8 ([#666](https://github.com/texane/stlink/pull/666), [#667](https://github.com/texane/stlink/pull/667), [#668](https://github.com/texane/stlink/pull/668)) @@ -126,7 +126,7 @@ Major changes and added features: Updates and fixes: -* Fixed gdb-server: L0xx has no FP_CTRL register for breakpoints ([#273](https://github.com/texane/stlink/pull/273)) +* Fixed gdb-server: STM32L0xx has no FP_CTRL register for breakpoints ([#273](https://github.com/texane/stlink/pull/273)) * Updated libusb to 1.0.21 for Windows ([#562](https://github.com/texane/stlink/pull/562)) * Fixed low-voltage flashing on STM32F7 devices ([#566](https://github.com/texane/stlink/pull/566), [#567](https://github.com/texane/stlink/pull/567)) * Fixed building with mingw64 ([#569](https://github.com/texane/stlink/pull/569), [#573](https://github.com/texane/stlink/pull/573), [#578](https://github.com/texane/stlink/pull/578), [#584](https://github.com/texane/stlink/pull/584), [#610](https://github.com/texane/stlink/pull/610)) @@ -226,9 +226,9 @@ Features added: Updates and fixes: * Refactoring/fixes of flash loader (Maxime Coquelin) -* Synchronized cache for stm32f7 (Tristan Gingold) +* Synchronized cache for STM32F7 (Tristan Gingold) * Allow flashing of STM32L4 down to 1.71 V (Greg Meiste) -* Fix on stm32l4 to clear flash mass erase flags on CR (Bruno Dal Bo) +* Fix on STM32L4 to clear flash mass erase flags on CR (Bruno Dal Bo) * Proper writing of page 0 of second bank for stm32l476xe (Tobias Badertscher) * Trace the read data in stlink_read_debug32 and not the address of the variable (Tobias Badertscher) * Mac OS X El Capitan platform support confirmation (Nikolay) @@ -238,8 +238,8 @@ Updates and fixes: * Make sure MCU is halted before running RAM based flashloaders (mlundinse) * Could not flash STM32_F3_SMALL (Max Chen) * STM32F4 8-bit support for 1.8v operation (Andy Isaacson) -* Fixed F2 memory map (Nicolas Schodet) -* Memory map for stm32f42xxx and stm32f43xxx devices (Craig Lilley) +* Fixed STM32F2xx memory map (Nicolas Schodet) +* Memory map for STM32F42xxx and STM32F43xxx devices (Craig Lilley) * Stm32l0x flash loader (Robin Kreis) Chip support added for: @@ -247,7 +247,7 @@ Chip support added for: * STM32L053R8 (Jean-Luc Béchennec) * STM32F7 Support (mlundinse) * Added STM32L4 to CHIPID #defines and devices[], flash driver and loader (Dave Vandervies) -* Basic support for F446 (Pavel Kirienko) +* Basic support for STM32F446 (Pavel Kirienko) * STM32F303 High Density * STM32L1xx Cat.2 devices (Nicolas Schodet) From 10ae5294cd03aacfc07312010f026d3cb12ea56c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 23 Mar 2020 19:11:18 +0100 Subject: [PATCH 0743/1435] Updated /doc/compiling.md (Closes #113) - Added note on correct libusb version. - Formatting improvements - Corrections to grammar and wording --- doc/compiling.md | 151 +++++++++++++++++++++++++++-------------------- 1 file changed, 86 insertions(+), 65 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index 61bb12e6e..2728c153b 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -1,12 +1,11 @@ # Compiling from sources +## General package requirements -## Package requirements - -* CMake (v2.8.7 or later) +* cmake (v2.8.7 or later) * C compiler (gcc, clang or mingw) -* libusb 1.0 (v1.0.13 or later) -* libusb-dev 1.0 (v1.0.13 or later) -* (optional) pandoc for generating manpages from markdown +* libusb-1.0 (v1.0.13 or later) +* libusb-dev-1.0 (v1.0.13 or later) +* pandoc _(optional; for generating manpages from markdown)_ Run from the root of the source directory: @@ -15,8 +14,7 @@ $ make release $ make debug ``` -The debug target should only be necessary for people who want - to modify the sources and run under a debugger. +The debug target should only be necessary for people who want to modify the sources and run under a debugger. The top level Makefile is just a handy wrapper for: ``` @@ -25,83 +23,100 @@ $ cmake -DCMAKE_BUILD_TYPE=Debug .. $ make ``` -You could install to a user folder e.g `$HOME`: +You may install to a user folder e.g `$HOME`: ``` $ cd build/Release; make install DESTDIR=$HOME ``` -Or system wide: +Or system-wide: ``` $ cd build/Release; sudo make install ``` -## Linux +## Linux / Unix ## Common requirements -* Debian based distros (debian, ubuntu) - * `build-essential` +* `build-essential` * `cmake` -* `libusb-1.0` (plus development headers for building, on debian based distros `libusb-1.0-0-dev` package) -* (optional) for `stlink-gui` we need libgtk-3-dev +* `libusb-1.0` +* `libusb-1.0-0-dev` (development headers for building, _only on debian based distros_) +* `libgtk-3-dev` _(optional; required for `stlink-gui`)_ + +As of today several distributions namely: + +- CentOS 6, 7, 8 +- Debian 8, 9, 10, sid +- Fedora 30, 31, Rawhide +- NetBSD 7.2, 8.1, 9.0 +- openSUSE Leap 15.1, Leap 15.2 +- Ubuntu 14.04 LTS, 16.04 LTS, 18.04 LTS, 19.10 + +provide packages for libusb 0.1 and libusb 1.0. + +**Please ensure that the correct version 1.0 is installed.** +Other relevant distributions appear to have packages named _libusb-compat-0.1_ or alike to distinguish from libusb packages based on version 1.0.x. + ### Fixing cannot open shared object file When installing system-wide (`sudo make install`) the dynamic library cache needs to be updated with the command `ldconfig`. + ## Permissions with udev -Make sure you install udev files which are necessary to run the tools without root - permissions. By default most distributions don't allow access to USB devices. The - udev rules create devices nodes and set the group of this to `stlink. +Make sure you install udev files which are necessary to run the tools without root permissions. +By default most distributions don't allow access to USB devices. +The udev rules create devices nodes and set the group of this to `stlink`. -The rules are located in the `etc/udev/rules.d` directory. You will need to copy it -to /etc/udev/rules.d, and then either execute as root (or reboot your machine): +The rules are located in the `etc/udev/rules.d` directory. +You will need to copy it to /etc/udev/rules.d, and then either execute as root (or reboot your machine): ``` $ udevadm control --reload-rules $ udevadm trigger ``` -Udev will now create device node files `/dev/stlinkv2_XX`, `/dev/stlinkv1_XX`. You must - make sure the `stlink` group exists and the user who is trying to access is added - to this group. +Udev will now create device node files `/dev/stlinkv2_XX`, `/dev/stlinkv1_XX`. +**You need to make sure the `stlink` group exists and the user, who is trying to access, is added to this group.** + ### Note for STLINKv1 usage -The STLINKv1's SCSI emulation is very broken, so the best thing to do -is tell your operating system to completely ignore it. +The STLINKv1's SCSI emulation is corrupted, so the best thing to do is tell your operating system to completely ignore it. Options (do one of these before you plug it in) -* `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` -* or 1. `echo "options usb-storage quirks=483:3744:i" >> /etc/modprobe.conf` -* 2. `modprobe -r usb-storage && modprobe usb-storage` -* or 1. `cp stlink_v1.modprobe.conf /etc/modprobe.d` -* 2. `modprobe -r usb-storage && modprobe usb-storage` +* `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` or + 1. `echo "options usb-storage quirks=483:3744:i" >> /etc/modprobe.conf` + 2. `modprobe -r usb-storage && modprobe usb-storage` +* or + 1. `cp stlink_v1.modprobe.conf /etc/modprobe.d` + 2. `modprobe -r usb-storage && modprobe usb-storage` + ### Build Debian Package -To build the debian package you need the following extra packages: `devscripts debhelper`. +To build the debian package you need the additional packages `devscripts` and `debhelper`. ``` $ git archive --prefix=$(git describe)/ HEAD | bzip2 --stdout > ../libstlink_$(sed -En -e "s/.*\((.*)\).*/\1/" -e "1,1 p" debian/changelog).orig.tar.bz2 $ debuild -uc -us ``` -## Mac OS X + +## macOS +### Prerequisites When compiling on a mac you need the following: * A compiler toolchain (XCode) -* CMake -* Libusb 1.0 +* cmake +* **libusb 1.0** -The best way is to install [homebrew](http://brew.sh) which is a package manager - for opensource software which is missing from the Apple App Store. Then install - the dependencies: +The best way is to install [homebrew](http://brew.sh) which is a package manager for opensource software which is missing from the Apple App Store. Then install the dependencies: ``` brew install libusb cmake @@ -109,92 +124,98 @@ brew install libusb cmake Compile as described in the first section of this document. + ## Build using different directories for udev and modprobe -To put the udev or the modprobe configuration files into a different directory -during installation you can use the following cmake options: +To put the udev or the modprobe configuration files into a different directory during installation use the following cmake options: ``` $ cmake -DSTLINK_UDEV_RULES_DIR="/usr/lib/udev/rules.d" \ -DSTLINK_MODPROBED_DIR="/usr/lib/modprobe.d" .. ``` + ## Build using different directory for shared libs -To put the compiled shared libs into a different directory during installation -you can use the following cmake option: +To put the compiled shared libs into a different directory during installation you can use the following cmake option: ``` -$ cmake -DLIB_INSTALL_DIR:PATH="/usr/lib64" .. +$ cmake -DLIB_INSTALL_DIR:PATH="/usr/lib64" .. ``` -## Windows (MinGW64) -### Prequistes +## Windows (MinGW64) +### Prerequisites -* 7Zip -* CMake 2.8 or higher +* 7zip +* cmake 2.8 or higher * MinGW64 GCC toolchain (5.3.0) + ### Installation -1. Install 7Zip from +1. Install 7zip from 2. Install CMake from 3. Install MinGW64 from (mingw-w64-install.exe) 4. Git clone or download stlink sourcefiles zip + ### Building Check and execute (in the script folder) `\scripts\mingw64-build.bat` -NOTE: when installing different toolchains make sure you edit the path in the `mingw64-build.bat` - the build script uses currently `C:\Program Files\mingw-w64\x86_64-5.3.0-win32-sjlj-rt_v4-rev0\mingw64\bin` +**NOTE:** when installing different toolchains make sure you edit the path in the `mingw64-build.bat`. +The build script currently uses `C:\Program Files\mingw-w64\x86_64-5.3.0-win32-sjlj-rt_v4-rev0\mingw64\bin` -## Windows (Visual Studio) +## Windows (Visual Studio) ### Prerequisites -* 7Zip -* CMake (tested with version 3.9.0-rc2) -* Visual Studio 2017 Community (other versions will likely work but are untested; the Community edition is free for open source +* 7zip +* cmake (tested with version 3.9.0-rc2) +* Visual Studio 2017 Community Edition (other versions will likely work but are untested; the Community Edition is free for open source development) + ### Installation -1. Install 7Zip from +1. Install 7zip from 2. Install CMake from 3. Git clone or download stlink sourcefiles zip + ### Building -These instructions are for a 32bit version. +These instructions are for a 32-bit version. In a command prompt, change directory to the folder where the stlink files were cloned (or unzipped). Make sure the build folder exists (`mkdir build` if not). From the build folder, run cmake (`cd build; cmake ..`). -This will create a solution (stlink.sln) in the build folder. Open it in Visual Studio, select the Solution Configuration (Debug or -Release) and build the solution normally (F7). +This will create a solution (stlink.sln) in the build folder. +Open it in Visual Studio, select the Solution Configuration (_Debug_ or _Release_) and build the solution normally (F7). -NOTES: This solution will link to the dll version of libusb-1.0. To debug or run the executable, the dll version of libusb-1.0 must -be either on the path, or in the same folder as the executable. It can be copied from here: -`build\3thparty\libusb-1.0.21\MS32\dll\libusb-1.0.dll`. +NOTES: This solution will link to the dll version of libusb-1.0. +To debug or run the executable, the dll version of libusb-1.0 must be either on the path, or in the same folder as the executable. +It can be copied from here: `build\3thparty\libusb-1.0.21\MS32\dll\libusb-1.0.dll`. -## Linux (MinGW64) -### Prequistes +## Linux (MinGW64) +### Prerequisites -* 7Zip -* CMake 2.8 or higher +* 7zip +* cmake 2.8 or higher * MinGW64 GCC toolchain (5.3.0) + ### Installation (Debian / Ubuntu) sudo apt install p7zip mingw-w64 + ### Building -These instructions are for a 32bit version. +These instructions are for a 32-bit version. ```sh cd From e3c76aa67315db32bd303303023d6c74c51e900b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 24 Mar 2020 02:21:03 +0100 Subject: [PATCH 0744/1435] Removed deprecated LIBUSBX_API Closes #211 #782. See also #733. --- src/sg.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/src/sg.c b/src/sg.c index 8fa351cf6..8633b1d4d 100644 --- a/src/sg.c +++ b/src/sg.c @@ -936,15 +936,6 @@ static stlink_t* stlink_open(const int verbose) { return NULL; } -#if defined (__FreeBSD__) - #define LIBUSBX_API_VERSION LIBUSB_API_VERSION -#endif -#if LIBUSBX_API_VERSION < 0x01000106 - libusb_set_debug(slsg->libusb_ctx, 3); -#else - libusb_set_option(slsg->libusb_ctx, LIBUSB_OPTION_LOG_LEVEL, 3); -#endif - slsg->usb_handle = libusb_open_device_with_vid_pid(slsg->libusb_ctx, STLINK_USB_VID_ST, STLINK_USB_PID_STLINK); if (slsg->usb_handle == NULL) { WLOG("Failed to find an stlink v1 by VID:PID\n"); From c3f2b6b9714493b7d1d7a078b180b90db586c7a9 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 24 Mar 2020 13:33:32 +0100 Subject: [PATCH 0745/1435] Update for README.md - Updated "known missing features" - Removed section "known bugs" Note: Users should use the github ticket system to submit failures instead, otherwise they may not be fixed. --- README.md | 50 +------------------------------------------------- 1 file changed, 1 insertion(+), 49 deletions(-) diff --git a/README.md b/README.md index 6a6fd4ae3..0219d0d7f 100644 --- a/README.md +++ b/README.md @@ -88,57 +88,9 @@ Some features are currently missing from the `texane/stlink` toolset. Here we would appreciate any help and would love to welcome new contributors who want to get involved: * Instrumentation Trace Macro (ITM) Cell ([#136](https://github.com/texane/stlink/issues/136)) -* OTP area programming ([#202](https://github.com/texane/stlink/issues/202)) -* EEPROM area programming ([#318](https://github.com/texane/stlink/issues/218)) +* OTP & EEPROM area programming ([#202](https://github.com/texane/stlink/issues/202), [#333](https://github.com/texane/stlink/issues/333), [#686](https://github.com/texane/stlink/issues/686)) * Protection bits area reading ([#346](https://github.com/texane/stlink/issues/346)) * Writing external memory connected to an STM32 controller (e.g Quad SPI NOR flash) ([#412](https://github.com/texane/stlink/issues/412)) * MCU hotplug ([#449](https://github.com/texane/stlink/issues/449)) * Writing options bytes (region) ([#458](https://github.com/texane/stlink/issues/458)) -* Control programming speed ([#462](https://github.com/texane/stlink/issues/462)) * Support for STLINKv3 programmer ([#820](https://github.com/texane/stlink/issues/820)) - - -## Known bugs -### Sometimes flashing only works after a mass erase - -There is seen a problem sometimes where a flash loader run error occurs and is resolved after mass-erase of the flash: - -``` -2015-12-09T22:01:57 INFO src/stlink-common.c: Successfully loaded flash loader in sram -2015-12-09T22:02:18 ERROR src/stlink-common.c: flash loader run error -2015-12-09T22:02:18 ERROR src/stlink-common.c: run_flash_loader(0x8000000) failed! == -1 -``` - -Issue related to this bug: [#356](https://github.com/texane/stlink/issues/356) - - -### Flash size is detected as zero bytes size - -It is possible that the STM32 flash is write protected, the st-flash tool will show something like this: - -``` -st-flash write prog.bin 0x8000000 -2017-01-24T18:44:14 INFO src/stlink-common.c: Loading device parameters.... -2017-01-24T18:44:14 INFO src/stlink-common.c: Device connected is: F1 High-density device, id 0x10036414 -2017-01-24T18:44:14 INFO src/stlink-common.c: SRAM size: 0x10000 bytes (64 KiB), Flash: 0 bytes (0 KiB) in pages of 2048 bytes -``` - -As you can see, it gives out something unexpected like -``` -Flash: 0 bytes (0 KiB) in pages of 2048 bytes -``` - -``` -st-info --probe -Found 1 stlink programmers - serial: 303030303030303030303031 -openocd: "\x30\x30\x30\x30\x30\x30\x30\x30\x30\x30\x30\x31" - flash: 0 (pagesize: 2048) - sram: 65536 - chipid: 0x0414 - descr: F1 High-density device -``` - -Try to remove the write protection (probably only possible with ST Link Utility from ST itself). - -Issue related to this bug: [#545](https://github.com/texane/stlink/issues/545) From c783d0e777ccc83a7a8be26a4f4d3414e0478560 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 24 Mar 2020 17:09:14 +0100 Subject: [PATCH 0746/1435] Refactoring for tool "st-info" - Resorted cmds to the order they appear. --- doc/man/st-info.md | 30 +++++++++++++++--------------- src/tools/info.c | 38 +++++++++++++++++++------------------- 2 files changed, 34 insertions(+), 34 deletions(-) diff --git a/doc/man/st-info.md b/doc/man/st-info.md index 67d9373d7..ca2579785 100644 --- a/doc/man/st-info.md +++ b/doc/man/st-info.md @@ -12,7 +12,7 @@ st-info - Provides information about connected STLink and STM32 devices # DESCRIPTION Provides information about connected STLink programmers and STM32 devices: -Serial code, openocd, flash, sram, page size, chipid, description. +Serial code, OpenOCD hla-serial, flash, page size, sram, chipid, description. # OPTIONS @@ -20,29 +20,29 @@ Serial code, openocd, flash, sram, page size, chipid, description. \--version : Print version information -\--flash -: Display amount of flash memory available in the device +\--probe +: Display the summarized information of the connected programmers and devices -\--sram -: Display amount of sram memory available in device +\--serial +: Display the serial code of the device -\--descr -: Display textual description of the device +\--hla-serial +: Display the hex escaped serial code of the device + +\--flash +: Display amount of flash memory available in the device \--pagesize : Display the page size of the device +\--sram +: Display amount of sram memory available in device + \--chipid : Display the chip ID of the device -\--serial -: Display the serial code of the device - -\--hla-serial -: Display the hex escaped serial code of the device - -\--probe -: Display the summarized information of the connected programmers and devices +\--descr +: Display textual description of the device # EXAMPLES diff --git a/src/tools/info.c b/src/tools/info.c index 2ad8f2c09..3ebbba8de 100644 --- a/src/tools/info.c +++ b/src/tools/info.c @@ -8,14 +8,14 @@ static void usage(void) { puts("st-info --version"); + puts("st-info --probe"); + puts("st-info --serial"); + puts("st-info --hla-serial"); puts("st-info --flash"); - puts("st-info --sram"); - puts("st-info --descr"); puts("st-info --pagesize"); + puts("st-info --sram"); puts("st-info --chipid"); - puts("st-info --serial"); - puts("st-info --hla-serial"); - puts("st-info --probe"); + puts("st-info --descr"); } /* Print normal or OpenOCD hla_serial with newline */ @@ -45,20 +45,20 @@ static void stlink_print_info(stlink_t *sl) if (!sl) return; - printf(" serial: "); + printf(" serial: "); stlink_print_serial(sl, false); - printf("openocd: "); + printf(" hla-serial: "); stlink_print_serial(sl, true); - printf(" flash: %u (pagesize: %u)\n", - (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); + printf(" flash: %u (pagesize: %u)\n", + (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); - printf(" sram: %u\n", (unsigned int)sl->sram_size); - printf(" chipid: 0x%.4x\n", sl->chip_id); + printf(" sram: %u\n", (unsigned int)sl->sram_size); + printf(" chipid: 0x%.4x\n", sl->chip_id); params = stlink_chipid_get_params(sl->chip_id); if (params) - printf(" descr: %s\n", params->description); + printf(" descr: %s\n", params->description); } static void stlink_probe(void) @@ -113,18 +113,18 @@ static int print_data(char **av) if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); - if (strcmp(av[1], "--flash") == 0) + if (strcmp(av[1], "--serial") == 0) + stlink_print_serial(sl, false); + else if (strcmp(av[1], "--hla-serial") == 0) + stlink_print_serial(sl, true); + else if (strcmp(av[1], "--flash") == 0) printf("0x%x\n", (unsigned int)sl->flash_size); - else if (strcmp(av[1], "--sram") == 0) - printf("0x%x\n", (unsigned int)sl->sram_size); else if (strcmp(av[1], "--pagesize") == 0) printf("0x%x\n", (unsigned int)sl->flash_pgsz); + else if (strcmp(av[1], "--sram") == 0) + printf("0x%x\n", (unsigned int)sl->sram_size); else if (strcmp(av[1], "--chipid") == 0) printf("0x%.4x\n", sl->chip_id); - else if (strcmp(av[1], "--serial") == 0) - stlink_print_serial(sl, false); - else if (strcmp(av[1], "--hla-serial") == 0) - stlink_print_serial(sl, true); else if (strcmp(av[1], "--descr") == 0) { const struct stlink_chipid_params *params = stlink_chipid_get_params(sl->chip_id); if (params == NULL) From 562cd2496e696dbd22950925866aac662d81ee5f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 24 Mar 2020 19:00:49 +0100 Subject: [PATCH 0747/1435] Refactoring for tool "st-flash" - Fixed formatting for options display. --- src/tools/flash.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/tools/flash.c b/src/tools/flash.c index f87b65940..82b5c349e 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -29,17 +29,17 @@ static void cleanup(int signum) { static void usage(void) { - puts("stlinkv1 command line: ./st-flash [--debug] [--reset] [--format ] [--flash=] {read|write} /dev/sgX "); - puts("stlinkv1 command line: ./st-flash [--debug] /dev/sgX erase"); - puts("stlinkv2/3 command line: ./st-flash [--debug] [--reset] [--serial ] [--format ] [--flash=] {read|write} "); - puts("stlinkv2/3 command line: ./st-flash [--debug] [--serial ] erase"); - puts("stlinkv2/3 command line: ./st-flash [--debug] [--serial ] reset"); - puts(" Use hex format for addr, and ."); - puts(" fsize: Use decimal, octal or hex by prefix 0xXXX for hex, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); - puts(" Format may be 'binary' (default) or 'ihex', although must be specified for binary format only."); - puts(" ./st-flash [--version]"); + puts("stlinkv1 command line: ./st-flash [--debug] [--reset] [--format ] [--flash=] {read|write} /dev/sgX "); + puts("stlinkv1 command line: ./st-flash [--debug] /dev/sgX erase"); + puts("stlinkv2/3 command line: ./st-flash [--debug] [--reset] [--serial ] [--format ] [--flash=] {read|write} "); + puts("stlinkv2/3 command line: ./st-flash [--debug] [--serial ] erase"); + puts("stlinkv2/3 command line: ./st-flash [--debug] [--serial ] reset"); + puts(" , and : Use hex format."); + puts(" : Use decimal, octal or hex (prefix 0xXXX) format, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); + puts(" : Can be 'binary' (default) or 'ihex', although must be specified for binary format only."); + puts("print tool version info: ./st-flash [--version]"); puts("example write option byte: ./st-flash --debug --reset --area=option write 0xXXXXXXXX"); - puts("example read option byte: ./st-flash --debug --reset --area=option read > option_byte"); + puts("example read option byte: ./st-flash --debug --reset --area=option read > option_byte"); } int main(int ac, char** av) From a09ef54cf53f0e8c194ef33c49dfe96622e5c127 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 24 Mar 2020 21:11:38 +0100 Subject: [PATCH 0748/1435] General Project Update - Whitespace cleanup - Recycled content of old wiki page. --- README.md | 1 + doc/tutorial.md | 98 +++++++++++++++++++++++++++++++ doc/wiki_old.md | 108 ----------------------------------- include/stlink/tools/flash.h | 1 - src/common.c | 10 ++-- src/tools/flash.c | 6 +- src/tools/flash_opts.c | 22 +------ 7 files changed, 111 insertions(+), 135 deletions(-) delete mode 100644 doc/wiki_old.md diff --git a/README.md b/README.md index 0219d0d7f..b26a147e9 100644 --- a/README.md +++ b/README.md @@ -39,6 +39,7 @@ Currently known working combinations of programmers and targets are listed in [d **Windows**: download [v1.6.0](https://github.com/texane/stlink/releases/tag/v1.6.0) from the releases page. +Windows pre-compiled binaries are available at http://www.emb4fun.de/archive/stlink/index.html (outdated, not recommended for use) **macOS**: install [from homebrew](http://brewformulas.org/Stlink) or download [v1.6.0](https://github.com/texane/stlink/releases/tag/v1.6.0) from the releases page. diff --git a/doc/tutorial.md b/doc/tutorial.md index af4bae849..100d9a641 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -276,6 +276,42 @@ Example to read and write option bytes (currently writing only supported for STM ./st-flash --debug --reset --format binary --flash=128k write option_bytes_dump.bin 0x1FFF7800 ``` +## Installation of openOCD on Mac OS X with STlink-v2: + +`sudo port install openocd +jlink +stlink +ft2232` + +`/opt/local/bin/openocd --version` + +> Open On-Chip Debugger 0.7.0 (2014-08-11-22:12) + +`openocd -f /opt/local/share/openocd/scripts/interface/stlink-v2.cfg -f /opt/local/share/openocd/scripts/target/stm32f1x_stlink.cfg ` + +> Open On-Chip Debugger 0.8.0 (2014-08-11-15:36) +> +> Licensed under GNU GPL v2 +> +> For bug reports, read http://openocd.sourceforge.net/doc/doxygen/bugs.html +> +> Info : This adapter doesn't support configurable speed +> +> Info : STLINK v2 JTAG v21 API v2 SWIM v4 VID 0x0483 PID 0x3748 +> +> Info : using stlink api v2 +> +> Info : Target voltage: 3.244269 +> +> Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints + +and connecting to the server through telnet yields a successful installation + +`telnet localhost 4444` + +> Connected to localhost. +> +> Escape character is '^]'. +> +> Open On-Chip Debugger + FAQ === @@ -292,6 +328,68 @@ Q: Load command does not work in GDB. A: Some people report XML/EXPAT is not enabled by default when compiling GDB. Memory map parsing thus fail. Use --enable-expat. +Q: How can I install stlink and flash binaries on Mac OS X ? + +A: Installed on Mac OS X 10.9.4 with ports method, + however STlink v2 does not seem to work with libusb if you upgrade to the newest firmware !! + Only older firmware on STlink v2 works. + +[https://coderwall.com/p/oznj_q](https://coderwall.com/p/oznj_q) + +`sudo port install libusb automake autoconf pkgconfig` + +`aclocal --force -I /opt/local/share/aclocal` + +`git clone https://github.com/texane/stlink.git stlink-utility` + +`cd stlink-utility` + +`./autogen.sh` + +`./configure` + +`make` + +Then trying to flash the image with STLINK v2 : + +`./st-flash write ~/Downloads/irq.bin 0x8000000` + +> libusb_handle_events() timeout +> +> [!] send_recv + +ST-Link/V2 debugger with downgraded V2.14.3 firmware: + +https://drive.google.com/folderview?id=0Bzv7UpKpOQhnbXJVVEg4VUo2M1k + +After downgrading the firmware, flashing works as described here: + +http://community.spark.io/t/how-to-flash-a-brand-new-freshly-soldered-stm32f103-chip/3906 + +`./st-flash write ~/Downloads/irq.bin 0x8000000` + +> 2014-08-11T23:14:52 INFO src/stlink-common.c: Loading device parameters.... +> +> 2014-08-11T23:14:52 INFO src/stlink-common.c: Device connected is: F1 Medium-density device, id 0x20036410 +> +> 2014-08-11T23:14:52 INFO src/stlink-common.c: SRAM size: 0x5000 bytes (20 KiB), Flash: 0x20000 bytes (128 KiB) in +> pages of 1024 bytes +> +> 2014-08-11T23:14:52 INFO src/stlink-common.c: Attempting to write 24904 (0x6148) bytes to stm32 address: 134217728 +> (0x8000000) +> +> Flash page at addr: 0x08006000 erased +> +> 2014-08-11T23:14:53 INFO src/stlink-common.c: Finished erasing 25 pages of 1024 (0x400) bytes +> +> 2014-08-11T23:14:53 INFO src/stlink-common.c: Starting Flash write for VL/F0 core id +> +> 2014-08-11T23:14:53 INFO src/stlink-common.c: Successfully loaded flash loader in sram 24/24 pages written +> +> 2014-08-11T23:14:54 INFO src/stlink-common.c: Starting verification of write complete +> +> 2014-08-11T23:14:54 INFO src/stlink-common.c: Flash written and verified! jolly good! + Notes ===== diff --git a/doc/wiki_old.md b/doc/wiki_old.md deleted file mode 100644 index 81e70a277..000000000 --- a/doc/wiki_old.md +++ /dev/null @@ -1,108 +0,0 @@ -Welcome to the stlink wiki! (Archived: 2014-08-11) - -Misc: -Windows pre-compiled binaries are available at http://www.emb4fun.de/archive/stlink/index.html - -FAQ: -Q: Where can I get help? Is there a forum or maybe a mailing list? - -A: todo - -Q: How can I install stlink and flash binaries on Mac OS X ? - -A: **20140811: ** installed on Mac OS X 10.9.4 with ports method, however STlink v2 does not seem to work with libusb if you upgrade to the newest firmware !! Only older firmware on STlink v2 works. - -[https://coderwall.com/p/oznj_q](https://coderwall.com/p/oznj_q) - -`sudo port install libusb automake autoconf pkgconfig` - -`aclocal --force -I /opt/local/share/aclocal` - -`git clone https://github.com/texane/stlink.git stlink-utility` - -`cd stlink-utility` - -`./autogen.sh` - -`./configure` - -`make` - - -Then trying to flash the image with STLINK v2 : - -`./st-flash write ~/Downloads/irq.bin 0x8000000` - -> libusb_handle_events() timeout -> -> [!] send_recv - -After downgrading the firmware, flashing works -ST-Link/V2 debugger with downgraded V2.14.3 firmware: - -https://drive.google.com/folderview?id=0Bzv7UpKpOQhnbXJVVEg4VUo2M1k - -as described here: - -http://community.spark.io/t/how-to-flash-a-brand-new-freshly-soldered-stm32f103-chip/3906 - -`./st-flash write ~/Downloads/irq.bin 0x8000000` - -> 2014-08-11T23:14:52 INFO src/stlink-common.c: Loading device parameters.... -> -> 2014-08-11T23:14:52 INFO src/stlink-common.c: Device connected is: F1 Medium-density device, id 0x20036410 -> -> 2014-08-11T23:14:52 INFO src/stlink-common.c: SRAM size: 0x5000 bytes (20 KiB), Flash: 0x20000 bytes (128 KiB) in -> pages of 1024 bytes -> -> 2014-08-11T23:14:52 INFO src/stlink-common.c: Attempting to write 24904 (0x6148) bytes to stm32 address: 134217728 -> (0x8000000) -> -> Flash page at addr: 0x08006000 erased -> -> 2014-08-11T23:14:53 INFO src/stlink-common.c: Finished erasing 25 pages of 1024 (0x400) bytes -> -> 2014-08-11T23:14:53 INFO src/stlink-common.c: Starting Flash write for VL/F0 core id -> -> 2014-08-11T23:14:53 INFO src/stlink-common.c: Successfully loaded flash loader in sram 24/24 pages written -> -> 2014-08-11T23:14:54 INFO src/stlink-common.c: Starting verification of write complete -> -> 2014-08-11T23:14:54 INFO src/stlink-common.c: Flash written and verified! jolly good! - - -Installation of openOCD on Mac OS X with STlink-v2 has been successful: - -`sudo port install openocd +jlink +stlink +ft2232` - -`/opt/local/bin/openocd --version` - -> Open On-Chip Debugger 0.7.0 (2014-08-11-22:12) - -`openocd -f /opt/local/share/openocd/scripts/interface/stlink-v2.cfg -f /opt/local/share/openocd/scripts/target/stm32f1x_stlink.cfg ` - -> Open On-Chip Debugger 0.8.0 (2014-08-11-15:36) -> -> Licensed under GNU GPL v2 -> -> For bug reports, read http://openocd.sourceforge.net/doc/doxygen/bugs.html -> -> Info : This adapter doesn't support configurable speed -> -> Info : STLINK v2 JTAG v21 API v2 SWIM v4 VID 0x0483 PID 0x3748 -> -> Info : using stlink api v2 -> -> Info : Target voltage: 3.244269 -> -> Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints - -and connecting to the server through telnet yields a successful installation - -`telnet localhost 4444` - -> Connected to localhost. -> -> Escape character is '^]'. -> -> Open On-Chip Debugger diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index 8ca1eddf9..a73d7aee4 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -31,4 +31,3 @@ struct flash_opts int flash_get_opts(struct flash_opts* o, int ac, char** av); #endif // STLINK_FLASH_H_ - diff --git a/src/common.c b/src/common.c index 134921341..913d70e35 100644 --- a/src/common.c +++ b/src/common.c @@ -904,9 +904,9 @@ int stlink_load_device_params(stlink_t *sl) { sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, (unsigned int)sl->flash_pgsz); #else - ILOG("%s: %d KiB SRAM, %d KiB flash in %d %s pages.\n", - params->description, sl->sram_size / 1024, sl->flash_size / 1024, - (sl->flash_pgsz < 1024)? sl->flash_pgsz : sl->flash_pgsz/1024, + ILOG("%s: %d KiB SRAM, %d KiB flash in %d %s pages.\n", + params->description, sl->sram_size / 1024, sl->flash_size / 1024, + (sl->flash_pgsz < 1024)? sl->flash_pgsz : sl->flash_pgsz/1024, (sl->flash_pgsz < 1024)? "byte" : "KiB"); #endif return 0; @@ -1905,7 +1905,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) /* clear the pg bit */ clear_flash_cr_pg(sl); - + /* set the page erase bit */ set_flash_cr_per(sl); @@ -2855,7 +2855,7 @@ static int stlink_write_option_bytes_l1(stlink_t *sl, uint8_t* base, stm32_addr_ stlink_read_debug32(sl, addr+4, &val); WLOG("2nd option bytes is 0x%08x\n",val); } - } + } /* Reload options */ stlink_read_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); diff --git a/src/tools/flash.c b/src/tools/flash.c index 82b5c349e..e1e9f41f6 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -164,7 +164,9 @@ int main(int ac, char** av) goto on_error; } } - else if (o.addr == STM32_G0_OPTION_BYTES_BASE || o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE || o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE + 4){ + else if (o.addr == STM32_G0_OPTION_BYTES_BASE || + o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE || + o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE + 4){ err = stlink_fwrite_option_bytes(sl, o.filename, o.addr); if (err == -1) { @@ -219,7 +221,7 @@ int main(int ac, char** av) err = stlink_read_option_bytes_f4(sl,&option_byte); printf("%x\n",option_byte); }else{ - printf("This format is available for STM32F2 and STM32F4 Only\n"); + printf("This format is available for STM32F2 and STM32F4 only\n"); } }else{ if ((o.addr >= sl->flash_base) && (o.size == 0) && diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index 3f74ac057..ef41601a5 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -6,22 +6,19 @@ static bool starts_with(const char * str, const char * prefix) { size_t n = strlen(prefix); - if(strlen(str) < n) return false; + if (strlen(str) < n) return false; return (0 == strncmp(str, prefix, n)); } -int flash_get_opts(struct flash_opts* o, int ac, char** av) -{ +int flash_get_opts(struct flash_opts* o, int ac, char** av) { bool serial_specified = false; // defaults - memset(o, 0, sizeof(*o)); o->log_level = STND_LOG_LEVEL; // options - while(ac >= 1) { if (strcmp(av[0], "--version") == 0) { printf("v%s\n", STLINK_VERSION); @@ -44,18 +41,15 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) else { serial = av[0] + strlen("--serial="); } - /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ int j = (int)strlen(serial); - int length = j / 2; //the length of the destination-array + int length = j / 2; // the length of the destination-array if(j % 2 != 0) return -1; - for(size_t k = 0; j >= 0 && k < sizeof(o->serial); ++k, j -= 2) { char buffer[3] = {0}; memcpy(buffer, serial + j, 2); o->serial[length - k] = (uint8_t)strtol(buffer, NULL, 16); } - serial_specified = true; } else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { @@ -92,7 +86,6 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) else { format = av[0] + strlen("--format="); } - if (strcmp(format, "binary") == 0) o->format = FLASH_FORMAT_BINARY; else if (strcmp(format, "ihex") == 0) @@ -132,7 +125,6 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) } // command and (optional) device name - while(ac >= 1) { // looks like for stlinkv1 the device name and command may be swaped - check both positions in all cases if (strcmp(av[0], "erase") == 0) { if (o->cmd != FLASH_CMD_NONE) return -1; @@ -174,32 +166,26 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) case FLASH_CMD_READ: // expect filename, addr and size if((o->area == FLASH_OPTION_BYTES) &&(ac == 0)) break; if (ac != 3) return -1; - o->filename = av[0]; o->addr = (uint32_t) strtoul(av[1], &tail, 16); if(tail[0] != '\0') return -1; - o->size = strtoul(av[2], &tail, 16); if(tail[0] != '\0') return -1; - break; case FLASH_CMD_WRITE: if(o->area == FLASH_OPTION_BYTES){ if(ac != 1) return -1; - o->val = (uint32_t)strtoul(av[0], &tail, 16); } else if(o->format == FLASH_FORMAT_BINARY) { // expect filename and addr if (ac != 2) return -1; - o->filename = av[0]; o->addr = (uint32_t) strtoul(av[1], &tail, 16); if(tail[0] != '\0') return -1; } else if(o->format == FLASH_FORMAT_IHEX) { // expect filename if (ac != 1) return -1; - o->filename = av[0]; } else { @@ -211,9 +197,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) } // some constistence checks - if(serial_specified && o->devname != NULL) return -1; // serial not supported for v1 return 0; } - From 49f887d5247fdd28f163b6317790c4f087e652cc Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Wed, 25 Mar 2020 11:55:44 +0200 Subject: [PATCH 0749/1435] setting up a libusb log level accordingly to verbosity. --- include/stlink.h | 5 +++-- include/stlink/logging.h | 1 + src/logging.c | 21 +++++++++++++++++++++ src/sg.c | 6 ++++++ src/usb.c | 6 ++++++ 5 files changed, 37 insertions(+), 2 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index a69e357b5..f7eb9c69a 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -168,8 +168,8 @@ typedef struct flash_loader { size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() // bootloader - // sys_base and sys_size are not used by the tools, but are only there to - // download the bootloader code (see tests/sg.c) + // sys_base and sys_size are not used by the tools, but are only there to + // download the bootloader code (see tests/sg.c) stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() @@ -243,6 +243,7 @@ typedef struct flash_loader { #include "stlink/chipid.h" #include "stlink/flash_loader.h" #include "stlink/version.h" +#include "stlink/logging.h" #ifdef __cplusplus } diff --git a/include/stlink/logging.h b/include/stlink/logging.h index da5f7d19d..1083b2c55 100644 --- a/include/stlink/logging.h +++ b/include/stlink/logging.h @@ -18,6 +18,7 @@ enum ugly_loglevel { int ugly_init(int maximum_threshold); int ugly_log(int level, const char *tag, const char *format, ...); +int ugly_libusb_log_level(enum ugly_loglevel v); #define UGLY_LOG_FILE (strstr(__FILE__, "/") != NULL ? \ strrchr(__FILE__, '/') + 1 : strstr(__FILE__, "\\") != NULL ? \ diff --git a/src/logging.c b/src/logging.c index d4fb96b2e..59c2ea298 100644 --- a/src/logging.c +++ b/src/logging.c @@ -54,3 +54,24 @@ int ugly_log(int level, const char *tag, const char *format, ...) { va_end(args); return 1; } + + +/* + * Log message levels. + * - LIBUSB_LOG_LEVEL_NONE (0) : no messages ever printed by the library (default) + * - LIBUSB_LOG_LEVEL_ERROR (1) : error messages are printed to stderr + * - LIBUSB_LOG_LEVEL_WARNING (2) : warning and error messages are printed to stderr + * - LIBUSB_LOG_LEVEL_INFO (3) : informational messages are printed to stderr + * - LIBUSB_LOG_LEVEL_DEBUG (4) : debug and informational messages are printed to stderr +*/ +int ugly_libusb_log_level(enum ugly_loglevel v) +{ + switch (v) { + case UDEBUG: return 4; + case UINFO: return 3; + case UWARN: return 2; + case UERROR: return 1; + }; + + return 2; +} diff --git a/src/sg.c b/src/sg.c index 8633b1d4d..d1ee5aea1 100644 --- a/src/sg.c +++ b/src/sg.c @@ -936,6 +936,12 @@ static stlink_t* stlink_open(const int verbose) { return NULL; } +#if LIBUSB_API_VERSION < 0x01000106 + libusb_set_debug(slsg->libusb_ctx, ugly_libusb_log_level(verbose)); +#else + libusb_set_option(slsg->libusb_ctx, LIBUSB_OPTION_LOG_LEVEL, ugly_libusb_log_level(verbose)); +#endif + slsg->usb_handle = libusb_open_device_with_vid_pid(slsg->libusb_ctx, STLINK_USB_VID_ST, STLINK_USB_PID_STLINK); if (slsg->usb_handle == NULL) { WLOG("Failed to find an stlink v1 by VID:PID\n"); diff --git a/src/usb.c b/src/usb.c index 7832612cf..b99e04b27 100644 --- a/src/usb.c +++ b/src/usb.c @@ -902,6 +902,12 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST goto on_error; } +#if LIBUSB_API_VERSION < 0x01000106 + libusb_set_debug(slu->libusb_ctx, ugly_libusb_log_level(verbose)); +#else + libusb_set_option(slu->libusb_ctx, LIBUSB_OPTION_LOG_LEVEL, ugly_libusb_log_level(verbose)); +#endif + libusb_device **list; /** @todo We should use ssize_t and use it as a counter if > 0. As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) */ int cnt = (int) libusb_get_device_list(slu->libusb_ctx, &list); From c27b8f4616c335ed32ff58a2749c0f167a9ce657 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Wed, 25 Mar 2020 12:16:52 +0200 Subject: [PATCH 0750/1435] update libusb to 1.0.23 --- cmake/modules/FindLibUSB.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index 2ad35b3d8..fb122db3e 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -67,7 +67,7 @@ if(NOT LIBUSB_FOUND) if(WIN32 OR MSVC OR MINGW OR MSYS) find_package(7Zip REQUIRED) - set(LIBUSB_WIN_VERSION 1.0.22) + set(LIBUSB_WIN_VERSION 1.0.23) set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/3thparty/libusb-${LIBUSB_WIN_VERSION}) From eb4175e4fb43870c1553cb6a4bc6b53c166e049f Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 28 Mar 2020 20:41:41 +0200 Subject: [PATCH 0751/1435] include for INT_MAX --- src/usb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/usb.c b/src/usb.c index 7832612cf..d373f1997 100644 --- a/src/usb.c +++ b/src/usb.c @@ -2,6 +2,7 @@ #include #include #include +#include #if !defined(_MSC_VER) #include #endif From 18735deb1b96c37ce73a89b625e6020726dd45bb Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 28 Mar 2020 21:00:30 +0200 Subject: [PATCH 0752/1435] check LIBUSB_API_VERSION --- CMakeLists.txt | 1 + include/stlink/sg.h | 48 ++++++++++++++++---------------------- include/stlink/stlinkusb.h | 38 ++++++++++++++++++++++++++++++ include/stlink/usb.h | 2 +- src/usb.c | 8 ------- 5 files changed, 60 insertions(+), 37 deletions(-) create mode 100644 include/stlink/stlinkusb.h diff --git a/CMakeLists.txt b/CMakeLists.txt index d9e2bf6bd..c319bda4d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -82,6 +82,7 @@ set(STLINK_HEADERS include/stlink/mmap.h include/stlink/chipid.h include/stlink/flash_loader.h + include/stlink/stlinkusb.h ) set(STLINK_SOURCE diff --git a/include/stlink/sg.h b/include/stlink/sg.h index e521ba217..98efd4e58 100644 --- a/include/stlink/sg.h +++ b/include/stlink/sg.h @@ -6,20 +6,12 @@ */ #ifndef STLINK_SG_H -#define STLINK_SG_H - -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable: 4200 4255 4668 4820) -#include -#pragma warning(pop) -#else -#include -#endif +#define STLINK_SG_H +#include "stlinkusb.h" #include "stlink.h" -#ifdef __cplusplus +#ifdef __cplusplus extern "C" { #endif @@ -49,29 +41,29 @@ extern "C" { - struct stlink_libsg { - libusb_context* libusb_ctx; - libusb_device_handle *usb_handle; - unsigned ep_rep; - unsigned ep_req; +struct stlink_libsg { + libusb_context* libusb_ctx; + libusb_device_handle *usb_handle; + unsigned ep_rep; + unsigned ep_req; - int sg_fd; - int do_scsi_pt_err; + int sg_fd; + int do_scsi_pt_err; - unsigned char cdb_cmd_blk[CDB_SL]; + unsigned char cdb_cmd_blk[CDB_SL]; - int q_data_dir; // Q_DATA_IN, Q_DATA_OUT - // the start of the query data in the device memory space - uint32_t q_addr; + int q_data_dir; // Q_DATA_IN, Q_DATA_OUT + // the start of the query data in the device memory space + uint32_t q_addr; - // Sense (error information) data - // obsolete, this was fed to the scsi tools - unsigned char sense_buf[SENSE_BUF_LEN]; + // Sense (error information) data + // obsolete, this was fed to the scsi tools + unsigned char sense_buf[SENSE_BUF_LEN]; - struct stlink_reg reg; - }; + struct stlink_reg reg; +}; - stlink_t* stlink_v1_open(const int verbose, int reset); +stlink_t* stlink_v1_open(const int verbose, int reset); #ifdef __cplusplus } diff --git a/include/stlink/stlinkusb.h b/include/stlink/stlinkusb.h new file mode 100644 index 000000000..a5d664472 --- /dev/null +++ b/include/stlink/stlinkusb.h @@ -0,0 +1,38 @@ +#ifndef STLINKUSB_H +#define STLINKUSB_H + +#include + +/* + + libusb ver | LIBUSB_API_VERSION +-------------+-------------------- + v1.0.13 | 0x01000100 + v1.0.14 | 0x010000FF + v1.0.15 | 0x01000101 + v1.0.16 | 0x01000102 < MINIMAL_API_VERSION + v1.0.17 | 0x01000102 + v1.0.18 | 0x01000102 + v1.0.19 | 0x01000103 + v1.0.20 | 0x01000104 + v1.0.21 | 0x01000105 + v1.0.22 | 0x01000106 + v1.0.23 | 0x01000107 + +*/ + +#if !defined ( LIBUSBX_API_VERSION ) +#if defined (__FreeBSD__) +#define LIBUSBX_API_VVERSION LIBUSB_API_VERSION +#elif !defined (LIBUSB_API_VERSION) +#error unsupported libusb version +#endif +#endif + +#define MINIMAL_API_VERSION 0x01000102 + +#if ( LIBUSB_API_VERSION < MINIMAL_API_VERSION ) +#error unsupported libusb version +#endif + +#endif // STLINKUSB_H diff --git a/include/stlink/usb.h b/include/stlink/usb.h index 4bf28c355..2d5ff731c 100644 --- a/include/stlink/usb.h +++ b/include/stlink/usb.h @@ -9,9 +9,9 @@ #define STLINK_USB_H #include -#include #include "stlink.h" +#include "stlinkusb.h" #include "stlink/logging.h" #ifdef __cplusplus diff --git a/src/usb.c b/src/usb.c index d373f1997..bfa5fd2f4 100644 --- a/src/usb.c +++ b/src/usb.c @@ -8,14 +8,6 @@ #endif #include #include -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable: 4200 4255 4668 4820) -#include -#pragma warning(pop) -#else -#include -#endif #include #include From cefcb7316c8987f705c6b08d1ac4f5b1c2cb468f Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 28 Mar 2020 21:16:32 +0200 Subject: [PATCH 0753/1435] check MD5 while download libusb --- cmake/modules/FindLibUSB.cmake | 1 + 1 file changed, 1 insertion(+) diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index fb122db3e..9569fe133 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -79,6 +79,7 @@ if(NOT LIBUSB_FOUND) file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download ${LIBUSB_WIN_ARCHIVE_PATH} + EXPECTED_MD5 750e64b45aca94fafbdff07171004d03 ) endif() file(MAKE_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) From 04630e4302d7447aa6e981f7fe1a38d0f21e3017 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 28 Mar 2020 21:31:44 +0200 Subject: [PATCH 0754/1435] fix intendation --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index c319bda4d..306d3d6ff 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -82,7 +82,7 @@ set(STLINK_HEADERS include/stlink/mmap.h include/stlink/chipid.h include/stlink/flash_loader.h - include/stlink/stlinkusb.h + include/stlink/stlinkusb.h ) set(STLINK_SOURCE From f36d45ab922c0ccf80472205fd6f17dd478fd833 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 28 Mar 2020 21:57:08 +0200 Subject: [PATCH 0755/1435] specify correct MD5 for libusb-1.0.23.7z --- cmake/modules/FindLibUSB.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index 9569fe133..f88556205 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -79,7 +79,7 @@ if(NOT LIBUSB_FOUND) file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download ${LIBUSB_WIN_ARCHIVE_PATH} - EXPECTED_MD5 750e64b45aca94fafbdff07171004d03 + EXPECTED_MD5 cf3d38d2ff053ef343d10c0b8b0950c2 ) endif() file(MAKE_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) From 085ccae6a3e75368b75a14cd3553efcd70f27d70 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sun, 29 Mar 2020 08:28:38 +0300 Subject: [PATCH 0756/1435] fix typo --- include/stlink/stlinkusb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/stlink/stlinkusb.h b/include/stlink/stlinkusb.h index a5d664472..5e1220c34 100644 --- a/include/stlink/stlinkusb.h +++ b/include/stlink/stlinkusb.h @@ -23,7 +23,7 @@ #if !defined ( LIBUSBX_API_VERSION ) #if defined (__FreeBSD__) -#define LIBUSBX_API_VVERSION LIBUSB_API_VERSION +#define LIBUSBX_API_VERSION LIBUSB_API_VERSION #elif !defined (LIBUSB_API_VERSION) #error unsupported libusb version #endif From 61de93ff76aa32b300c8d0f0d2506b8872b950a4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 30 Mar 2020 02:11:38 +0200 Subject: [PATCH 0757/1435] Update for CHANGELOG.md & minor fixes --- CHANGELOG.md | 29 +++++++----- doc/tested-boards.md | 2 +- doc/wiki_old.md | 108 ------------------------------------------- 3 files changed, 18 insertions(+), 121 deletions(-) delete mode 100644 doc/wiki_old.md diff --git a/CHANGELOG.md b/CHANGELOG.md index 586e44206..d88d83098 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -9,6 +9,7 @@ Release date: 2020-02-20 Major changes and added features: * Initial support for STM32L41X ([#754](https://github.com/texane/stlink/pull/754), [#799](https://github.com/texane/stlink/pull/799)) +* Working support for CKS32F103C8T6 and related CKS devices with Core-ID 0x2ba01477 ([#756](https://github.com/texane/stlink/pull/756), [#757](https://github.com/texane/stlink/pull/757), [#805](https://github.com/texane/stlink/pull/805), [#834](https://github.com/texane/stlink/pull/834), Regression-Fixes: [#761](https://github.com/texane/stlink/pull/761), [#766](https://github.com/texane/stlink/pull/766)) * Added preliminary support for some STM32G0 chips ([#759](https://github.com/texane/stlink/pull/759), [#760](https://github.com/texane/stlink/pull/760), [#797](https://github.com/texane/stlink/pull/797)) * Added support for mass erasing second bank on STM32F10x_XL ([#767](https://github.com/texane/stlink/pull/767), [#768](https://github.com/texane/stlink/pull/768)) * Added call to clear PG bit after writing to flash ([#773](https://github.com/texane/stlink/pull/773)) @@ -30,9 +31,9 @@ Updates and fixes: * Fixed case when __FILE__ don't contain "/" nor "\\" ([#745](https://github.com/texane/stlink/pull/745)) * Fixed double dash issue in doc/man ([#746](https://github.com/texane/stlink/pull/746), [#747](https://github.com/texane/stlink/pull/747)) * Compiling documentation: package is called libusb-1.0-0-dev on Debian ([#748](https://github.com/texane/stlink/pull/748)) -* Only do bank calculation on STM32L4 devices with dual banked flash / Added chip ID 0x464 for STM32L41xxx/L42xxx devices ([#751](https://github.com/texane/stlink/pull/751)) +* Only do bank calculation on STM32L4 devices with dual banked flash / Added chip-ID 0x464 for STM32L41xxx/L42xxx devices ([#751](https://github.com/texane/stlink/pull/751)) * Added O_BINARY option to open file ([#753](https://github.com/texane/stlink/pull/753)) -* Fixed versioning when compiling from the checked out git-repo ([#762](https://github.com/texane/stlink/pull/762)) +* Fixed versioning when compiling from the checked out git-repo ([#762](https://github.com/texane/stlink/pull/762), [#772](https://github.com/texane/stlink/pull/772)) * Fixed "unkown chip id", piped output and st-util -v ([#107](https://github.com/texane/stlink/pull/107), [#665](https://github.com/texane/stlink/pull/665), [#763](https://github.com/texane/stlink/pull/763)) * win32: move usleep definition to unistd.h ([#765](https://github.com/texane/stlink/pull/765)) * Fixed relative path to the UI files needed by stlink-gui-local (GUI) ([#770](https://github.com/texane/stlink/pull/770), [#771](https://github.com/texane/stlink/pull/771)) @@ -71,7 +72,7 @@ Major changes and added features: Updates and fixes: -* Fixed missing flash_loader for STM32L011 ([#356](https://github.com/texane/stlink/pull/356), [#654](https://github.com/texane/stlink/pull/654), [#675](https://github.com/texane/stlink/pull/675)) +* Fixed missing flash_loader for STM32L011 ([#654](https://github.com/texane/stlink/pull/654), [#675](https://github.com/texane/stlink/pull/675)) * Fix for stlink library calls exit() or _exit() ([#634](https://github.com/texane/stlink/pull/634), [#696](https://github.com/texane/stlink/pull/696)) * Added semihosting parameter documentation in doc/man ([#674](https://github.com/texane/stlink/pull/674)) * Fixed reference to non-exisiting st-term tool in doc/man ([#676](https://github.com/texane/stlink/pull/676)) @@ -94,9 +95,9 @@ Release date: 2018-02-16 Major changes and added features: -* Added support of STM32L496xx/4A6xx devices ([#615](https://github.com/texane/stlink/pull/615)) +* Added support of STM32L496xx/4A6xx devices ([#615](https://github.com/texane/stlink/pull/615), [#657](https://github.com/texane/stlink/pull/657)) * Added unknown chip dummy to obtain the serial of the ST-link by a call to st-info --probe ([#641](https://github.com/texane/stlink/pull/641)) -* Added support for STM32F72xx (chip id: 0x452) devices (commit [#1969148](https://github.com/texane/stlink/commit/19691485359afef1a256964afcbb8dcf4b733209)) +* Added support for STM32F72xx (chip-ID: 0x452) devices (commit [#1969148](https://github.com/texane/stlink/commit/19691485359afef1a256964afcbb8dcf4b733209)) Updates and fixes: @@ -118,7 +119,7 @@ Release date: 2017-07-01 Major changes and added features: -* Allow building of debian package with CPack ([#554](https://github.com/texane/stlink/pull/554), commit [#2c0ab7f](https://github.com/texane/stlink/commit/5b69f25198a1a8f34e2ee48d1ad20f79447e3d55)) +* Allow building of debian package with CPack ([#554](https://github.com/texane/stlink/pull/554), commit [#5b69f25](https://github.com/texane/stlink/commit/5b69f25198a1a8f34e2ee48d1ad20f79447e3d55)) * Added support for STM32L011 target ([#564](https://github.com/texane/stlink/pull/564), [#565](https://github.com/texane/stlink/pull/565), [#572](https://github.com/texane/stlink/pull/572)) * Added support for flashing second bank on STM32F10x_XL ([#592](https://github.com/texane/stlink/pull/592)) * Initial support to compile with Microsoft Visual Studio 2017 ([#602](https://github.com/texane/stlink/pull/602)) @@ -150,7 +151,7 @@ Major changes and added features: * Added support for Semihosting `SYS_READC` ([#546](https://github.com/texane/stlink/pull/546)) * Added support for STM32F413 ([#549](https://github.com/texane/stlink/pull/549), [#550](https://github.com/texane/stlink/pull/550)) -* Added preliminary support for STM32L011 to see it after probe (chipid `0x457`) ([#558](https://github.com/texane/stlink/pull/558), [#598](https://github.com/texane/stlink/pull/598)) +* Added preliminary support for STM32L011 to see it after probe (chip-ID 0x457) ([#558](https://github.com/texane/stlink/pull/558), [#598](https://github.com/texane/stlink/pull/598)) Updates and fixes: @@ -171,12 +172,12 @@ Major changes and added features: * Deprecation of autotools (autoconf, automake) and fixed build with MinGW ([#83](https://github.com/texane/stlink/pull/83), [#431](https://github.com/texane/stlink/pull/431), [#434](https://github.com/texane/stlink/pull/434), [#465](https://github.com/texane/stlink/pull/465)) * Added intel hex file reading for `st-flash` ([#110](https://github.com/texane/stlink/pull/110), [#157](https://github.com/texane/stlink/pull/157), [#200](https://github.com/texane/stlink/pull/200), [#239](https://github.com/texane/stlink/pull/239), [#457](https://github.com/texane/stlink/pull/547), [#459](https://github.com/texane/stlink/pull/549)) +* Added support for ARM semihosting to `st-util` ([#147](https://github.com/texane/stlink/pull/147), [#227](https://github.com/texane/stlink/pull/227), [#454](https://github.com/texane/stlink/pull/454), [#455](https://github.com/texane/stlink/pull/455)) * Added manpages (generated with pandoc from Markdown) ([#208](https://github.com/texane/stlink/pull/208), [#464](https://github.com/texane/stlink/pull/464), [#466](https://github.com/texane/stlink/pull/466), [#467](https://github.com/texane/stlink/pull/467)) -* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/texane/stlink/pull/228), ([#507](https://github.com/texane/stlink/pull/507), commit [#2c0ab7f](https://github.com/texane/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) +* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/texane/stlink/pull/228), ([#507](https://github.com/texane/stlink/pull/507), commit [#3fd0f09](https://github.com/texane/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) * Support serial numbers argument for `st-util` and `st-flash` to probe and control multiple connected programmers ([#318](https://github.com/texane/stlink/pull/318), [#398](https://github.com/texane/stlink/pull/398), [#541](https://github.com/texane/stlink/pull/541)) * Merge st-probe tool into st-info ([#398](https://github.com/texane/stlink/pull/398)) * Added support for native debian packaging ([#444](https://github.com/texane/stlink/pull/444), [#472](https://github.com/texane/stlink/pull/472), [#473](https://github.com/texane/stlink/pull/473), [#482](https://github.com/texane/stlink/pull/482), [#483](https://github.com/texane/stlink/pull/483), [#484](https://github.com/texane/stlink/pull/484), [#485](https://github.com/texane/stlink/pull/485)) -* Added support for ARM semihosting to `st-util` ([#454](https://github.com/texane/stlink/pull/454), [#455](https://github.com/texane/stlink/pull/455)) * Rewritten commandline parsing for `st-flash` ([#459](https://github.com/texane/stlink/pull/459)) * Added `--reset` command to `st-flash` ([#505](https://github.com/texane/stlink/pull/505)) * st-util should detect when USB commands fail ([#525](https://github.com/texane/stlink/pull/525), ([#527](https://github.com/texane/stlink/pull/527), ([#528](https://github.com/texane/stlink/pull/528)) @@ -188,14 +189,13 @@ Chip support added for: * STM32F412 ([#537](https://github.com/texane/stlink/pull/537), [#538](https://github.com/texane/stlink/pull/538)) * STM32F7xx ([#324](https://github.com/texane/stlink/pull/324), [#326](https://github.com/texane/stlink/pull/326), [#327](https://github.com/texane/stlink/pull/327), [#337](https://github.com/texane/stlink/pull/337)) * STM32F767ZI ([#509](https://github.com/texane/stlink/pull/509)) -* STM32L0xx Cat2 devices (chip id: 0x425) ([#414](https://github.com/texane/stlink/pull/414)) -* STM32L0xx Cat5 devices (chip id: 0x447) ([#406](https://github.com/texane/stlink/pull/406)) +* STM32L0xx Cat2 devices (chip-ID: 0x425) ([#414](https://github.com/texane/stlink/pull/414)) +* STM32L0xx Cat5 devices (chip-ID: 0x447) ([#406](https://github.com/texane/stlink/pull/406)) * STM32L4xx ([#321](https://github.com/texane/stlink/pull/321)) * STM32L432 ([#500](https://github.com/texane/stlink/pull/500), [#501](https://github.com/texane/stlink/pull/501)) Updates and fixes: -* Set SWDCLK and fixed jtag_reset bug ([#254](https://github.com/texane/stlink/pull/254), [#291](https://github.com/texane/stlink/pull/291), [#475](https://github.com/texane/stlink/pull/475), [#533](https://github.com/texane/stlink/pull/533), [#534](https://github.com/texane/stlink/pull/534)) * Fixed "unaligned addr or size" when trying to write a program in RAM ([#323](https://github.com/texane/stlink/pull/323)) * Fixed flashing on STM32_F3_SMALL ([#325](https://github.com/texane/stlink/pull/325)) * Fixed STM32L-problem with flash loader ([#390](https://github.com/texane/stlink/pull/390)) @@ -205,6 +205,8 @@ Updates and fixes: * Fixed STM32F030 erase error ([#442](https://github.com/texane/stlink/pull/442)) * Fixed memory map for STM32F7xx ([#453](https://github.com/texane/stlink/pull/453), [#456](https://github.com/texane/stlink/pull/456)) * Redesign of `st-flash` commandline options parsing ([#459](https://github.com/texane/stlink/pull/459)) +* Set SWDCLK and fixed jtag_reset bug ([#475](https://github.com/texane/stlink/pull/475), [#534](https://github.com/texane/stlink/pull/534)) +* doc/compiling.md: Add note about installation and ldconfig ([#478](https://github.com/texane/stlink/pull/478), commit [#be66bbf](https://github.com/texane/stlink/commit/be66bbf200c718904514b044ba84d64a36456218)) * Fixed Release target to generate the man-pages with pandoc ([#479](https://github.com/texane/stlink/pull/479)) * Fixed Cygwin build ([#487](https://github.com/texane/stlink/pull/487), ([#506](https://github.com/texane/stlink/pull/506)) * Reset flash mass erase (MER) bit after mass erase for safety ([#489](https://github.com/texane/stlink/pull/489)) @@ -241,6 +243,8 @@ Updates and fixes: * Fixed STM32F2xx memory map (Nicolas Schodet) * Memory map for STM32F42xxx and STM32F43xxx devices (Craig Lilley) * Stm32l0x flash loader (Robin Kreis) +* Send F4 memory-map and features for STM32F429 ([#188](https://github.com/texane/stlink/pull/188), [#196](https://github.com/texane/stlink/pull/196), [#250](https://github.com/texane/stlink/pull/250), [#251](https://github.com/texane/stlink/pull/251)) (Release v1.1.0) +* Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/texane/stlink/pull/218), [#288](https://github.com/texane/stlink/pull/288)) (Release v1.1.0) Chip support added for: @@ -250,6 +254,7 @@ Chip support added for: * Basic support for STM32F446 (Pavel Kirienko) * STM32F303 High Density * STM32L1xx Cat.2 devices (Nicolas Schodet) +* STM32L1xx (chip-ID 0x427) ([#152](https://github.com/texane/stlink/pull/152), [#163](https://github.com/texane/stlink/pull/163), [#165](https://github.com/texane/stlink/pull/165)) (Release v1.0.0) Board support added for: diff --git a/doc/tested-boards.md b/doc/tested-boards.md index ebc47c2ac..a9fa2f1c6 100644 --- a/doc/tested-boards.md +++ b/doc/tested-boards.md @@ -18,7 +18,7 @@ STLink v2 (as found on the 32L and F4 Discovery boards), known working targets: * STM32F030F4P6 (custom board) * STM32F051R8T6 (STM320518-EVAL board) * STM32F100xx (Medium Density VL, as on the 32VL Discovery board) -* STM32F103VET6 (HY-STM32 board) +* STM32F103VET6 (HY-STM32 board) ([#149](https://github.com/texane/stlink/pull/149)) * STM32F105RCT6 (DecaWave EVB1000 board) * STM32F303xx (STM32F3 Discovery board) * STM32F407xx (STM32F4 Discovery board) diff --git a/doc/wiki_old.md b/doc/wiki_old.md deleted file mode 100644 index 81e70a277..000000000 --- a/doc/wiki_old.md +++ /dev/null @@ -1,108 +0,0 @@ -Welcome to the stlink wiki! (Archived: 2014-08-11) - -Misc: -Windows pre-compiled binaries are available at http://www.emb4fun.de/archive/stlink/index.html - -FAQ: -Q: Where can I get help? Is there a forum or maybe a mailing list? - -A: todo - -Q: How can I install stlink and flash binaries on Mac OS X ? - -A: **20140811: ** installed on Mac OS X 10.9.4 with ports method, however STlink v2 does not seem to work with libusb if you upgrade to the newest firmware !! Only older firmware on STlink v2 works. - -[https://coderwall.com/p/oznj_q](https://coderwall.com/p/oznj_q) - -`sudo port install libusb automake autoconf pkgconfig` - -`aclocal --force -I /opt/local/share/aclocal` - -`git clone https://github.com/texane/stlink.git stlink-utility` - -`cd stlink-utility` - -`./autogen.sh` - -`./configure` - -`make` - - -Then trying to flash the image with STLINK v2 : - -`./st-flash write ~/Downloads/irq.bin 0x8000000` - -> libusb_handle_events() timeout -> -> [!] send_recv - -After downgrading the firmware, flashing works -ST-Link/V2 debugger with downgraded V2.14.3 firmware: - -https://drive.google.com/folderview?id=0Bzv7UpKpOQhnbXJVVEg4VUo2M1k - -as described here: - -http://community.spark.io/t/how-to-flash-a-brand-new-freshly-soldered-stm32f103-chip/3906 - -`./st-flash write ~/Downloads/irq.bin 0x8000000` - -> 2014-08-11T23:14:52 INFO src/stlink-common.c: Loading device parameters.... -> -> 2014-08-11T23:14:52 INFO src/stlink-common.c: Device connected is: F1 Medium-density device, id 0x20036410 -> -> 2014-08-11T23:14:52 INFO src/stlink-common.c: SRAM size: 0x5000 bytes (20 KiB), Flash: 0x20000 bytes (128 KiB) in -> pages of 1024 bytes -> -> 2014-08-11T23:14:52 INFO src/stlink-common.c: Attempting to write 24904 (0x6148) bytes to stm32 address: 134217728 -> (0x8000000) -> -> Flash page at addr: 0x08006000 erased -> -> 2014-08-11T23:14:53 INFO src/stlink-common.c: Finished erasing 25 pages of 1024 (0x400) bytes -> -> 2014-08-11T23:14:53 INFO src/stlink-common.c: Starting Flash write for VL/F0 core id -> -> 2014-08-11T23:14:53 INFO src/stlink-common.c: Successfully loaded flash loader in sram 24/24 pages written -> -> 2014-08-11T23:14:54 INFO src/stlink-common.c: Starting verification of write complete -> -> 2014-08-11T23:14:54 INFO src/stlink-common.c: Flash written and verified! jolly good! - - -Installation of openOCD on Mac OS X with STlink-v2 has been successful: - -`sudo port install openocd +jlink +stlink +ft2232` - -`/opt/local/bin/openocd --version` - -> Open On-Chip Debugger 0.7.0 (2014-08-11-22:12) - -`openocd -f /opt/local/share/openocd/scripts/interface/stlink-v2.cfg -f /opt/local/share/openocd/scripts/target/stm32f1x_stlink.cfg ` - -> Open On-Chip Debugger 0.8.0 (2014-08-11-15:36) -> -> Licensed under GNU GPL v2 -> -> For bug reports, read http://openocd.sourceforge.net/doc/doxygen/bugs.html -> -> Info : This adapter doesn't support configurable speed -> -> Info : STLINK v2 JTAG v21 API v2 SWIM v4 VID 0x0483 PID 0x3748 -> -> Info : using stlink api v2 -> -> Info : Target voltage: 3.244269 -> -> Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints - -and connecting to the server through telnet yields a successful installation - -`telnet localhost 4444` - -> Connected to localhost. -> -> Escape character is '^]'. -> -> Open On-Chip Debugger From f57954ab87d27a96183782b9e72633943e6fc597 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 31 Mar 2020 14:52:45 +0200 Subject: [PATCH 0758/1435] add usb pid for st-link v2.1, found on nucleo l432kc and nucleo l552ze. --- include/stlink/usb.h | 1 + src/usb.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/include/stlink/usb.h b/include/stlink/usb.h index 4bf28c355..239c5b4ef 100644 --- a/include/stlink/usb.h +++ b/include/stlink/usb.h @@ -23,6 +23,7 @@ extern "C" { #define STLINK_USB_PID_STLINK_32L 0x3748 #define STLINK_USB_PID_STLINK_32L_AUDIO 0x374a #define STLINK_USB_PID_STLINK_NUCLEO 0x374b +#define STLINK_USB_PID_STLINK_V2_1 0x3752 #define STLINK_USB_PID_STLINK_V3_USBLOADER 0x374d #define STLINK_USB_PID_STLINK_V3E_PID 0x374e #define STLINK_USB_PID_STLINK_V3S_PID 0x374f diff --git a/src/usb.c b/src/usb.c index 7832612cf..c5a314d45 100644 --- a/src/usb.c +++ b/src/usb.c @@ -941,6 +941,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) || (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO) || (desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO) || + (desc.idProduct == STLINK_USB_PID_STLINK_V2_1) || (desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER) || (desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID) || (desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID) || @@ -957,7 +958,8 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) || (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO) - || (desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO)) { + || (desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO) + || (desc.idProduct == STLINK_USB_PID_STLINK_V2_1)) { sl->version.stlink_v = 2; } else if ((desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER) || (desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID) @@ -1032,6 +1034,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO || desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO || + desc.idProduct == STLINK_USB_PID_STLINK_V2_1 || desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER || desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID || desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID || @@ -1115,6 +1118,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { if (desc.idProduct != STLINK_USB_PID_STLINK_32L && desc.idProduct != STLINK_USB_PID_STLINK_32L_AUDIO && desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO && + desc.idProduct != STLINK_USB_PID_STLINK_V2_1 && desc.idProduct != STLINK_USB_PID_STLINK_V3_USBLOADER && desc.idProduct != STLINK_USB_PID_STLINK_V3E_PID && desc.idProduct != STLINK_USB_PID_STLINK_V3S_PID && From 140a03e7fd230798806328fe05bea5cda614a047 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 31 Mar 2020 15:26:27 +0200 Subject: [PATCH 0759/1435] update udev rules for stlinkv2-1 --- etc/udev/rules.d/49-stlinkv2-1.rules | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/etc/udev/rules.d/49-stlinkv2-1.rules b/etc/udev/rules.d/49-stlinkv2-1.rules index 15a797a05..b89b84012 100644 --- a/etc/udev/rules.d/49-stlinkv2-1.rules +++ b/etc/udev/rules.d/49-stlinkv2-1.rules @@ -10,6 +10,10 @@ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ MODE:="0666", \ SYMLINK+="stlinkv2-1_%n" +SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3752", \ + MODE:="0666", \ + SYMLINK+="stlinkv2-1_%n" + # If you share your linux system with other users, or just don't like the # idea of write permission for everybody, you can replace MODE:="0666" with # OWNER:="yourusername" to create the device owned by you, or with From ac4775623df9ef74b3bd86c2939482c99cf01f80 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 31 Mar 2020 09:43:50 +0200 Subject: [PATCH 0760/1435] add stm32g4 cat3 (dual flash bank) devices. --- src/chipid.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/chipid.c b/src/chipid.c index 75448e01b..4659a55c9 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -554,6 +554,20 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7000 // 28K (table 2) }, + { + // STM32G471/473/474/483/484 (from RM0440) + .chip_id = STLINK_CHIPID_STM32_G4_CAT3, + .description = "G4 Category-3", + .flash_type = STLINK_FLASH_TYPE_G4, + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = 0x800, // 2K (sec 3.3.1) + // SRAM1 is 80k at 0x20000000 + // SRAM2 is 16k at 0x20014000 + // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x18000, // 128K (sec 2.4) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000 // 28K (table 2) + }, { // STM32WB55 (from RM0434) .chip_id = STLINK_CHIPID_STM32_WB55, From 0cd94a9adcce03406db887842badd6ac82c71e1b Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 31 Mar 2020 09:43:03 +0200 Subject: [PATCH 0761/1435] stm32g0431/441: update doc --- src/chipid.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/chipid.c b/src/chipid.c index 4659a55c9..426780cf7 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -550,6 +550,9 @@ static const struct stlink_chipid_params devices[] = { .flash_type = STLINK_FLASH_TYPE_G4, .flash_size_reg = 0x1FFF75E0, // Section 47.2 .flash_pagesize = 0x800, // 2K (sec 3.3.1) + // SRAM1 is 16k at 0x20000000 + // SRAM2 is 6k at 0x20014000 + // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 .sram_size = 0x8000, // 32K (sec 2.4) .bootrom_base = 0x1fff0000, .bootrom_size = 0x7000 // 28K (table 2) From db6e93e52aa86add8ff0453ca2d26ca13310fa8e Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Wed, 1 Apr 2020 20:40:34 +0300 Subject: [PATCH 0762/1435] set minimal LIBUSBX_API_VERSION to depend on OS --- include/stlink/stlinkusb.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/include/stlink/stlinkusb.h b/include/stlink/stlinkusb.h index 5e1220c34..4d904b0c5 100644 --- a/include/stlink/stlinkusb.h +++ b/include/stlink/stlinkusb.h @@ -10,7 +10,7 @@ v1.0.13 | 0x01000100 v1.0.14 | 0x010000FF v1.0.15 | 0x01000101 - v1.0.16 | 0x01000102 < MINIMAL_API_VERSION + v1.0.16 | 0x01000102 v1.0.17 | 0x01000102 v1.0.18 | 0x01000102 v1.0.19 | 0x01000103 @@ -21,15 +21,23 @@ */ -#if !defined ( LIBUSBX_API_VERSION ) #if defined (__FreeBSD__) +#if !defined ( LIBUSBX_API_VERSION ) #define LIBUSBX_API_VERSION LIBUSB_API_VERSION #elif !defined (LIBUSB_API_VERSION) #error unsupported libusb version #endif #endif +#if defined (__FreeBSD__) #define MINIMAL_API_VERSION 0x01000102 +#elif defined (__linux__) +#define MINIMAL_API_VERSION 0x01000104 +#elif defined (__APPLE__) +#define MINIMAL_API_VERSION 0x01000104 +#elif defined (_WIN32) +#define MINIMAL_API_VERSION 0x01000106 +#endif #if ( LIBUSB_API_VERSION < MINIMAL_API_VERSION ) #error unsupported libusb version From a76f468587713ee7bc1cf959d50c55446918a878 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 2 Apr 2020 02:18:49 +0200 Subject: [PATCH 0763/1435] [doc] Updated list of supported devices --- README.md | 2 +- doc/devices_boards.md | 258 ++++++++++++++++++++++++++++++++++++++++ doc/tested-boards.md | 57 --------- include/stlink/chipid.h | 32 ++--- 4 files changed, 269 insertions(+), 80 deletions(-) create mode 100644 doc/devices_boards.md delete mode 100644 doc/tested-boards.md diff --git a/README.md b/README.md index b26a147e9..5c601f36c 100644 --- a/README.md +++ b/README.md @@ -32,7 +32,7 @@ These programmer boards are available in four versions: ## Supported hardware combinations -Currently known working combinations of programmers and targets are listed in [doc/tested-boards.md](doc/tested-boards.md). +Currently known working combinations of programmers and targets are listed in [doc/devices_boards.md](doc/tested-boards.md). ## Installation diff --git a/doc/devices_boards.md b/doc/devices_boards.md new file mode 100644 index 000000000..d9e106503 --- /dev/null +++ b/doc/devices_boards.md @@ -0,0 +1,258 @@ +Boards supported by the STlink toolset +====================================== + +The following devices are supported by the STlink tools. + +All Boards are expected to work with ST-Link-v2 programmers. + + +**STM32F0 / ARM Cortex M0 / Core-ID: 0x0bb11477 (STM32F0_CORE_ID)** + +| Chip-ID | Product-Code | +| --- | --- | +| 0x440 | STM32F0**30**x**8** | +| 0x442 | STM32F0**30**x**C** | +| 0x444 | STM32F0**3**xx**4** | +| 0x444 | STM32F0**3**xx**6** | +| 0x445 | STM32F0**4**xxx | +| 0x440 | STM32F0**5**xxx | +| 0x445 | STM32F0**70**x**6** | +| 0x448 | STM32F0**70**x**B** | +| 0x448 | STM32F0**71**xx | +| 0x448 | STM32F0**72**xx | +| 0x442 | STM32F0**9**xxx | + +Tested boards [incl. STLink programmers]: +* Nucleo-F030R8 [v2-1] +* Nucleo-32 [v2-1] +* STM32F0-Discovery [v2] +* STM320518-EVAL +* Nucleo-F072RB [v2-1] +* Nucleo-F091RC [v2-1] + + +**STM32F1 / ARM Cortex M3 / Core-ID: 0x1ba01477 (STM32F1_CORE_ID)** + +| Product-Code | Product Line | +| --- | --- | +| STM32F10**0**yyxx | Value line (V) | +| STM32F10**1**yyxx | Access line (A) | +| STM32F10**2**yyxx | USB Access line (USB-A) | +| STM32F10**3**yyxx | Performance line (P) | +| STM32F10**5**yyxx | Connectivity line (C) | +| STM32F10**7**yyxx | Connectivity line (C) | + +| Chip-ID | Product Line | Code (yy) | V | A | USB-A | P | C | +| --- | --- | --- | --- | --- | --- | --- | --- | +| 0x412 | Low-Density | x4 x6 | F100 | F101 | F102 | F103 | | +| 0x410 | Medium Density | x8 xB | | F101 | F102 | F103 | | +| 0x414 | High density | xC xD xE | | F101 | F103 | | | +| 0x418 | STM32F105xx/107xx | x8 xB xC | | | | | F105
    F107 | +| 0x420 | Medium density value | x8 xB | F100 | | | | | +| 0x428 | High density Value | xC xD xE | F100 | | | | | +| 0x430 | XL-Density | xF XG | | F101 | | F103 | | + +Tested boards [incl. STLink programmers]: +* 32VL-Discovery (STM32F100RBT6) with STLink-v1 [v1, v2] +* STM32F103-Bluepill: C8Tx & R8xx [v2] +* Nucleo-F103RB [v2-1] +* HY-STM32 (STM32F103VETx) [v1, v2] +* DecaWave EVB1000 (STM32F105RCTx) [v1, v2] + + +**STM32F2 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F2_CORE_ID)** + +| Chip-ID | Product-Code | Product Line | +| --- | --- | --- | +| 0x411 | STM32F2yyxx | (all devices) | + + +**STM32F1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM3F1c_CORE_ID)** + +| Product-Code | Chip-ID | STLink
    Programmer | Boards | +| --- | --- | --- | --- | +| CKS32F103C8Tx | 0x410 | v2 | "STM32"-Bluepill ( _**Fake-Marking !**_ )
    STM32F103C8T6 clone from China Key Systems (CKS) | +| CKS32F103C8Tx | 0x410 | v2 | CKS32-Bluepill (Clone)
    STM32F103C8T6 clone from China Key Systems (CKS) | + + +**STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3_CORE_ID)** + +| Product-Code | Product Line | +| --- | --- | +| STM32F3**01**yyxx | Access line (A) | +| STM32F3**02**yyxx | USB & CAN line (USB/CAN) | +| STM32F3**03**yyxx | Performance line (P) | +| STM32F3**34**yy | Digital Power line (DP) | +| STM32F3**73**yy | Precision Measurement line (PM) 64k/16k / 128k/24k / 265k/32k | +| STM32F3**18**yy | General Purpose line (GP) 64k/16k | +| STM32F3**28**yy | General Purpose line (GP) 64k/16k | +| STM32F3**58**yy | General Purpose line (GP) 265k/48k | +| STM32F3**78**yy | Precision Measurement line (PM) 265k/32k | +| STM32F3**98**yy | General Purpose line (GP) 512k/80k | + +| Chip-ID | Product Line | Code (yy) | A | USB/CAN | P | others | +| --- | --- | --- | --- | --- | --- | --- | +| 0x422 | _N/A_ | xB xC | | F302 | F303 | | +| 0x422 | _N/A_ | - | | | | F358 | +| 0x432 | _N/A_ | - | | | | F373
    F378 | +| 0x438 | _N/A_ | x4 x6 x8 | | | F303 | | +| 0x438 | _N/A_ | - | | | | F334
    F328 | +| 0x439 | _N/A_ | x4 x6 x8 | F301 | F302 | | | +| 0x439 | _N/A_ | - | | | | F318 | +| 0x446 | _N/A_ | xD xE | | F302 | F303 | | +| 0x446 | _N/A_ | - | | | | F398 | + +Tested boards [incl. STLink programmers]: +* Nucleo-F302K8 [v2-1] +* Nucleo-F303K8 [v2-1] +* STM32F3348-Discovery [v2-1] +* Nucleo-F334R8 [v2-1] +* STM32F303-Discovery [v2] +* Nucleo-F303RE [v2-1] + + +**STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3c_CORE_ID)** + +| Product-Code | Chip-ID | STLink
    Programmer | Boards | +| --- | --- | --- | --- | +| GD32F303VGT6 | 0x430 | _N/A_ | STM32F303 clone from GigaDevice GD)
    _unsupported_ | + + +**STM32F4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F4_CORE_ID)** + +| Chip-ID | Product-Code | +| --- | --- | +| 0x413 | STM32F4**0**xxx | +| 0x413 | STM32F4**1**xxx | +| 0x419 | STM32F4**2**xxx | +| 0x419 | STM32F4**3**xxx | +| 0x423 | STM32F4**01**x**B** | +| 0x423 | STM32F4**01**x**C** | +| 0x433 | STM32F4**01**x**D** | +| 0x433 | STM32F4**01**x**E** | +| 0x458 | STM32F4**10**xx | +| 0x431 | STM32F4**11**xx | +| 0x441 | STM32F4**12**xx | +| 0x421 | STM32F4**46**xx | +| 0x434 | STM32F4**69**xx | +| 0x434 | STM32F4**79**xx | +| 0x463 | STM32F4**13**xx | +| 0x463 | STM32F4**23**xx | + +Tested boards [incl. STLink programmers]: +* STM32F407-Discovery [v2] +* 32F411E-Discovery with gyro, audio [v2] +* 32F429I-Discovery with LCD [v2] +* 32F439VIT6-Discovery [v2] (reseated MCU) +* Nucleo-F401RE [v2-1] +* Nucleo-F411RE [v2-1] +* 32F413H-Discovery [v2-1] + + +**STM32F7 / ARM Cortex M7F / Core-ID: 0x5ba02477 (STM32F7_CORE_ID)** + +| Chip-ID | Product-Code | +| --- | --- | +| 0x452 | STM32F7**2**xxx | +| 0x452 | STM32F7**3**xxx | +| 0x449 | STM32F7**4**xxx | +| 0x449 | STM32F7**5**xxx | +| 0x451 | STM32F7**6**xxx | +| 0x451 | STM32F7**7**xxx | + +Tested boards [incl. STLink programmers]: +* STM32F756NGHx evaluation board [v2-1] +* 32F769I-Discovery [v2-1] +* Nucleo-F722ZE [v2-1] +* Nucleo-F746ZG [v2-1] + + +**STM32G0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32G0_CORE_ID)** + +| Chip-ID | Product-Code | +| --- | --- | +| 0x466 | STM32G0**3**xxx | +| 0x466 | STM32G0**4**xxx | +| 0x460 | STM32G0**7**xxx | +| 0x460 | STM32G0**8**xxx | + + +**STM32G4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32G4_CORE_ID)** + +| Chip-ID | Product-Code | +| --- | --- | +| 0x468 | STM32G4**31**xx | +| 0x468 | STM32G4**41**xx | +| 0x469 | STM32G4**7**xxx | +| 0x469 | STM32G4**8**xxx | + + +**STM32L0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32L0_CORE_ID)** + +| Chip-ID | Product-Code | +| --- | --- | +| 0x457 | STM32L0**1**xxx | +| 0x457 | STM32L0**2**xxx | +| 0x425 | STM32L0**31**xx | +| 0x425 | STM32L0**41**xx | +| 0x417 | STM32L0**5**xxx | +| 0x417 | STM32L0**6**xxx | +| 0x447 | STM32L0**7**xxx | +| 0x447 | STM32L0**8**xxx | + +Tested boards [incl. STLink programmers]: +* Nucleo-L053R8 [v2-1] + + +**STM32L1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32L1_CORE_ID)** + +| Chip-ID | Product-Code | +| --- | --- | +| 0x416 | STM32L1xxx**6** | +| 0x416 | STM32L1xxx**8** | +| 0x416 | STM32L1xxx**B** | +| 0x429 | STM32L1xxx**6A** | +| 0x429 | STM32L1xxx**8A** | +| 0x429 | STM32L1xxx**BA** | +| 0x427 | STM32L1xxx**C** | +| 0x436 | STM32L1xxx**D** | +| 0x437 | STM32L1xxx**E** | + +Tested boards [incl. STLink programmers]: +* Nucleo-L152RE [v2-1] +* 32L152C-Discovery [v2] + + +**STM32L4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32L4_CORE_ID)** + +| Chip-ID | Product-Code | +| --- | --- | +| 0x464 | STM32L4**12**xx | +| 0x464 | STM32L4**22**xx | +| 0x435 | STM32L4**3**xxx | +| 0x435 | STM32L4**4**xxx | +| 0x462 | STM32L4**5**xxx | +| 0x462 | STM32L4**6**xxx | +| 0x415 | STM32L4**7**xxx | +| 0x415 | STM32L4**8**xxx | +| 0x461 | STM32L4**96**xx | +| 0x461 | STM32L4**A6**xx | +| 0x470 | STM32L4**R**xx | +| 0x470 | STM32L4**S**xx | +| 0x471 | STM32L4**P5**xx | +| 0x471 | STM32L4**Q5**xx | + +Tested boards [incl. STLink programmers]: +* Nucleo-L452RE [v2-1] +* Nucleo-L476RG [v2-1] +* Nucleo-L496ZG [v2-1] +* 32L4R9I-Discovery [v2-1] + + +**STM32W / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32W_CORE_ID)** + +| Chip-ID | Product-Code | +| --- | --- | +| 0x495 | STM32WB**50**xx | +| 0x495 | STM32WB**55**xx | +| 0x497 | STM32WLE**5**xx | diff --git a/doc/tested-boards.md b/doc/tested-boards.md deleted file mode 100644 index ebc47c2ac..000000000 --- a/doc/tested-boards.md +++ /dev/null @@ -1,57 +0,0 @@ -Stlink tested and compatible boards -=================================== - -STLink v1 (as found on the 32VL Discovery board) - -Known working targets: - -* STM32F100xx (Medium Density VL) -* STM32F103 (according to jpa- on ##stm32) - -No information: - -* everything else! - -STLink v2 (as found on the 32L and F4 Discovery boards), known working targets: - -* STM32F0 (STM32F0 Discovery board) -* STM32F030F4P6 (custom board) -* STM32F051R8T6 (STM320518-EVAL board) -* STM32F100xx (Medium Density VL, as on the 32VL Discovery board) -* STM32F103VET6 (HY-STM32 board) -* STM32F105RCT6 (DecaWave EVB1000 board) -* STM32F303xx (STM32F3 Discovery board) -* STM32F407xx (STM32F4 Discovery board) -* STM32F411E-DISCO (STM32F4 Discovery board with gyro, audio) -* STM32F429I-DISCO (STM32F4 Discovery board with LCD) -* STM32F439VIT6 (Discovery board reseated CPU) -* STM32L052K8T6 (custom board) -* STM32L1xx (STM32L Discovery board) -* STM32L151CB (custom board) -* STM32L152RB (STM32L-Discovery board, custom board) -* STM32L496ZG (STM32-Nucleo-L496ZG board) - - -* STM32F103VC, STM32F107RC, STM32L151RB, STM32F205RE and STM32F405RE on custom boards - from [UweBonnes/wiki_fuer_alex](https://github.com/UweBonnes/wiki_fuer_alex/tree/master/layout) - - -STLink v2-1 (as found on the Nucleo boards), known working targets: - -* STM32F030R8T6 (STM32 Nucleo-F030R8 board) -* STM32F042K6 (STM32 Nucleo-32 Board) -* STM32F072RBT6 (STM32 Nucleo-F072RB board) -* STM32F103RB (STM32 Nucleo-F103RB board) -* STM32F303RET6 (STM32 Nucleo-F303RE board) -* STM32F334R8 (STM32 Nucleo-F334R8 board) -* STM32F401xx (STM32 Nucleo-F401RE board) -* STM32F411RET6 (STM32 Nucleo-F411RE board) -* STM32F756NGHx (STM32F7 evaluation board) -* STM32F769NI (STM32F7 discovery board) -* STM32L053R8 (STM32 Nucleo-L053R8 board) -* STM32L152RE (STM32-Nucleo-L152RE board -* STM32L452RET6 (STM32 Nucleo-L452RE board) -* STM32L476RG (STM32 Nucleo-L476RG board) - - -Please report any and all known working combinations so I can update this! diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index f179db779..8895cd4f8 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -28,7 +28,7 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F3 = 0x422, STLINK_CHIPID_STM32_F4_LP = 0x423, STLINK_CHIPID_STM32_L0_CAT2 = 0x425, - STLINK_CHIPID_STM32_L1_MEDIUM_PLUS = 0x427, + STLINK_CHIPID_STM32_L1_MEDIUM_PLUS = 0x427, /* assigned to some L1 "Medium-plus" chips */ STLINK_CHIPID_STM32_F1_VL_HIGH = 0x428, STLINK_CHIPID_STM32_L1_CAT2 = 0x429, STLINK_CHIPID_STM32_F1_XL = 0x430, @@ -36,23 +36,11 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F37x = 0x432, STLINK_CHIPID_STM32_F4_DE = 0x433, STLINK_CHIPID_STM32_F4_DSI = 0x434, - /* - * 0x435 covers STM32L43xxx and STM32L44xxx devices - * 0x461 covers STM32L496xx and STM32L4A6xx devices - * 0x462 covers STM32L45xxx and STM32L46xxx devices - * 0x464 covers STM32L41xxx and STM32L42xxx devices - */ - STLINK_CHIPID_STM32_L43X = 0x435, - STLINK_CHIPID_STM32_L496X = 0x461, - STLINK_CHIPID_STM32_L46X = 0x462, - STLINK_CHIPID_STM32_L41X = 0x464, - /* - * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus" - * and some that are called "High". 0x427 is assigned to the other "Medium- - * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and - * 0x436 HIGH. - */ - STLINK_CHIPID_STM32_L1_HIGH = 0x436, + STLINK_CHIPID_STM32_L43X = 0x435, /* covers STM32L43xxx and STM32L44xxx devices */ + STLINK_CHIPID_STM32_L496X = 0x461, /* covers STM32L496xx and STM32L4A6xx devices */ + STLINK_CHIPID_STM32_L46X = 0x462, /* covers STM32L45xxx and STM32L46xxx devices */ + STLINK_CHIPID_STM32_L41X = 0x464, /* covers STM32L41xxx and STM32L42xxx devices */ + STLINK_CHIPID_STM32_L1_HIGH = 0x436, /* assigned to some L1 chips called "Medium-Plus" and to some called "High" */ STLINK_CHIPID_STM32_L152_RE = 0x437, STLINK_CHIPID_STM32_F334 = 0x438, STLINK_CHIPID_STM32_F3_SMALL = 0x439, @@ -69,12 +57,12 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F72XXX = 0x452, /* This ID is found on the NucleoF722ZE board */ STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, - STLINK_CHIPID_STM32_G0_CAT2 = 0x460, // G070/G071/081 + STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ STLINK_CHIPID_STM32_F413 = 0x463, - STLINK_CHIPID_STM32_G0_CAT1 = 0x466, // G030/G031/041 - STLINK_CHIPID_STM32_G4_CAT2 = 0x468, // See: RM 0440 s46.6.1 "MCU device ID code". + STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ + STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ STLINK_CHIPID_STM32_G4_CAT3 = 0x469, - STLINK_CHIPID_STM32_L4RX = 0x470, // taken from the STM32L4R9I-DISCO board + STLINK_CHIPID_STM32_L4RX = 0x470, /* taken from the STM32L4R9I-DISCO board */ STLINK_CHIPID_STM32_WB55 = 0x495 }; From cda2215327987c67e44ffbcaf04a8bc82b86bf24 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 2 Apr 2020 15:53:21 +0200 Subject: [PATCH 0764/1435] Update issue templates --- .github/ISSUE_TEMPLATE/bug-report.md | 38 ++++++++++++++++++++++ .github/ISSUE_TEMPLATE/feature-request.md | 39 +++++++++++++++++++++++ 2 files changed, 77 insertions(+) create mode 100644 .github/ISSUE_TEMPLATE/bug-report.md create mode 100644 .github/ISSUE_TEMPLATE/feature-request.md diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md new file mode 100644 index 000000000..2d565a3f7 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -0,0 +1,38 @@ +--- +name: Bug Report +about: Create a report to help us improve +title: "[Your device name]: [Title]" +labels: bug/needs-investigation +assignees: '' + +--- + +Thank you for giving feedback to the stlink project. + +In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out each of the following items appropriate to your specific problem: + +- Programmer/board type: [enter here] (e.g Stlink /v1, /v2, /v2-clone, /v2-1) +- Programmer firmware version: [enter here] (e.g STSW-LINK007 2.27.15) +- Operating system and version: [enter here] (e.g Linux, Mac OS X, Windows) +- **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.1.0/git-c722056) +- Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) +- Target chip (and board if applicable): [enter here] (e.g STM32F402VG) + +Futher we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: + +Commandline-Output: + +``` +OUTPUT/ERROR of the commandline tool(s) +``` + +Expected/description: + +`short description of the expected value` + + +**NOTICE: This bug report may be closed without further notice, if not enough information is provided!** + +Thank you for your support. + +The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/feature-request.md b/.github/ISSUE_TEMPLATE/feature-request.md new file mode 100644 index 000000000..2aa7a5c7f --- /dev/null +++ b/.github/ISSUE_TEMPLATE/feature-request.md @@ -0,0 +1,39 @@ +--- +name: Feature Request +about: Suggest an idea for this project +title: "[feature] " +labels: code/feature-request +assignees: '' + +--- + +Thank you for giving feedback to the stlink project. + +In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out the check boxes below by setting a 'x' into the checkboxes ( [x] ) and edit each item appropriate to your specific problem. + +- [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard +- [ ] Programmer firmware version: e.g STSW-LINK007 2.27.15 +- [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) +- [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 +- [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` +- [ ] Target chip (and optional board): e.g STM32F402VG (STM32Fxxx Discovery) + +Futher we kindly ask you to describe the detected problem as detailled as possible and to add debug output if available, by using the following template: + +Commandline-Output: + +``` +OUTPUT/ERROR of the commandline tool(s) +``` + +Expected/description: + +`short description of the expected value` + + +**NOTICE: This feature request may be closed without notice when not enough information is provided!** + + +Thank you for your support. + +The stlink project maintainers From d3c11fbef6d8205742152f646b223323dc4c0913 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 2 Apr 2020 20:55:27 +0200 Subject: [PATCH 0765/1435] General Project Update - [doc] Updated list of supported devices - [doc] verify udev-rules (Closes #764) - Removed old issue-templates. - Updated BSD-3 license file. --- .github/ISSUE_TEMPLATE/bug_report.md | 32 -------------- .github/ISSUE_TEMPLATE/feature_request.md | 32 -------------- .github/ISSUE_TEMPLATE/support_question.md | 32 -------------- LICENSE.md | 48 ++++++++++----------- doc/devices_boards.md | 1 + doc/tutorial.md | 49 ++++++++++++++++++++++ 6 files changed, 74 insertions(+), 120 deletions(-) delete mode 100644 .github/ISSUE_TEMPLATE/bug_report.md delete mode 100644 .github/ISSUE_TEMPLATE/feature_request.md delete mode 100644 .github/ISSUE_TEMPLATE/support_question.md diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md deleted file mode 100644 index 821b406bc..000000000 --- a/.github/ISSUE_TEMPLATE/bug_report.md +++ /dev/null @@ -1,32 +0,0 @@ -# Bug Report - -Thank you for giving feedback to the stlink project. - -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out the check boxes below by setting a 'x' into the checkboxes ( [x] ) and edit each item appropriate to your specific problem. - -- [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard -- [ ] Programmer firmware version: e.g STSW-LINK007 2.27.15 -- [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) -- [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 -- [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` -- [ ] Target chip (and optional board): e.g STM32F402VG (STM32Fxxx Discovery) - -Futher we kindly ask you to describe the detected problem as detailled as possible and to add debug output if available, by using the following template: - -Commandline-Output: - -``` -OUTPUT/ERROR of the commandline tool(s) -``` - -Expected/description: - -`short description of the expected value` - - -**NOTICE: The bug report may be closed without notice when not enough information is provided!** - - -Thank you for your support. - -The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/feature_request.md b/.github/ISSUE_TEMPLATE/feature_request.md deleted file mode 100644 index bf626eb97..000000000 --- a/.github/ISSUE_TEMPLATE/feature_request.md +++ /dev/null @@ -1,32 +0,0 @@ -# Feature Request - -Thank you for giving feedback to the stlink project. - -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out the check boxes below by setting a 'x' into the checkboxes ( [x] ) and edit each item appropriate to your specific problem. - -- [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard -- [ ] Programmer firmware version: e.g STSW-LINK007 2.27.15 -- [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) -- [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 -- [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` -- [ ] Target chip (and optional board): e.g STM32F402VG (STM32Fxxx Discovery) - -Futher we kindly ask you to describe the detected problem as detailled as possible and to add debug output if available, by using the following template: - -Commandline-Output: - -``` -OUTPUT/ERROR of the commandline tool(s) -``` - -Expected/description: - -`short description of the expected value` - - -**NOTICE: This feature request may be closed without notice when not enough information is provided!** - - -Thank you for your support. - -The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/support_question.md b/.github/ISSUE_TEMPLATE/support_question.md deleted file mode 100644 index 795c13a6e..000000000 --- a/.github/ISSUE_TEMPLATE/support_question.md +++ /dev/null @@ -1,32 +0,0 @@ -# Support question - -Thank you for giving feedback to the stlink project. - -In order to allow developers and other contributors to help you with your question, please take some time to fill out the check boxes below by setting a 'x' into the checkboxes ( [x] ) and edit each item appropriate to your specific problem. - -- [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard -- [ ] Programmer firmware version: e.g STSW-LINK007 2.27.15 -- [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) -- [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 -- [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` -- [ ] Target chip (and optional board): e.g STM32F402VG (STM32Fxxx Discovery) - -Futher we kindly ask you to describe the detected problem as detailled as possible and to add debug output if available, by using the following template: - -Commandline-Output: - -``` -OUTPUT/ERROR of the commandline tool(s) -``` - -Expected/description: - -`short description of the expected value` - - -**NOTICE: This support question may be closed without notice when not enough information is provided!** - - -Thank you for your support. - -The stlink project maintainers diff --git a/LICENSE.md b/LICENSE.md index 3d464ca1e..0a3ddd1f7 100644 --- a/LICENSE.md +++ b/LICENSE.md @@ -1,29 +1,29 @@ -Copyright (c) 2011 The stlink project (github.com/texane/stlink) contributors. - All rights reserved. -Copyright (c) 2011 The "Capt'ns Missing Link" Authors. All rights reserved. +BSD 3-Clause License + +Copyright (c) 2020, The stlink project (github.com/texane/stlink) & "Capt'ns Missing Link" authors. +All rights reserved. Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are -met: +modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above - copyright notice, this list of conditions and the following - disclaimer in the documentation and/or other materials provided - with the distribution. - * Neither the name of Martin Capitanio nor the names of its - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. +3. Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/doc/devices_boards.md b/doc/devices_boards.md index d9e106503..00acdd2cf 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -243,6 +243,7 @@ Tested boards [incl. STLink programmers]: | 0x471 | STM32L4**Q5**xx | Tested boards [incl. STLink programmers]: +* Nucleo-L432KC [v2-1] * Nucleo-L452RE [v2-1] * Nucleo-L476RG [v2-1] * Nucleo-L496ZG [v2-1] diff --git a/doc/tutorial.md b/doc/tutorial.md index 100d9a641..4d870d11b 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -170,6 +170,55 @@ Upon reset, the board LEDs should be blinking. HOWTO ===== + +## Verify if udev rules are set correctly (by Dave Hylands) + +To investigate, start by plugging your STLINK device into the usb port. Then run lsusb. You should see an entry something like the following: + +``` +Bus 005 Device 017: ID 0483:374b STMicroelectronics ST-LINK/V2.1 (Nucleo-F103RB) +``` + +Note the bus number (005) and the Device (017). You should then do: +`ls -l /dev/bus/usb/005/017` (replacing 005 and 017 appropriately). + +On my system I see the following: + +``` +crw-rw-rw- 1 root root 189, 528 Jan 24 17:52 /dev/bus/usb/005/017 +``` + +which is world writable (this is from the MODE:="0666" below). I have several files in my `/etc/udev/rules.d` directory. In this particular case, the `49-stlinkv2-1.rules` file contains the following: + +``` +# stm32 nucleo boards, with onboard st/linkv2-1 +# ie, STM32F0, STM32F4. +# STM32VL has st/linkv1, which is quite different + +SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ + MODE:="0666", \ + SYMLINK+="stlinkv2-1_%n" + +# If you share your linux system with other users, or just don't like the +# idea of write permission for everybody, you can replace MODE:="0666" with +# OWNER:="yourusername" to create the device owned by you, or with +# GROUP:="somegroupname" and mange access using standard unix groups. +``` + +and the idVendor of 0483 and idProduct of 374b matches the vendor id from the lsusb output. + +Make sure that you have all 3 files from here: https://github.com/texane/stlink/tree/master/etc/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing excisting files in `/etc/udev/ruled.d` you should run the following: + +``` +sudo udevadm control --reload-rules +sudo udevadm trigger +``` + +to ensure that the rules actually take effect. Using the trigger command means that you shouldn't need to unplug and replug the device, but you might want to try that for good measure as well. + +If the VID:PID of your device doesn't match those in any of the 3 files, then you may need to create a custom rule file to match your VID:PID. + + ## Using the gdb server To run the gdb server: From 7d4822d03ba758bc4013cf74e91ba44070b6b81c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 2 Apr 2020 21:29:02 +0200 Subject: [PATCH 0766/1435] [doc] Added st-flash --flash CL option (Closes #902) --- doc/tutorial.md | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/doc/tutorial.md b/doc/tutorial.md index 4d870d11b..1d48eaa38 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -1,3 +1,20 @@ +stlink Tools Tutorial +===================== + +## Useful tool options +### st-flash + +#### --flash=n[k][m] + +(since v1.4.0) + +You can specify `--flash=128k` for example, to override the STM32F103C8T6 to assume 128k of flash instead of the default of 64k. +This option accepts decimal (128k), octal 0200k, or hex 0x80k. +Obviously leaving the multiplier out is equally valid, for example: `--flash=0x20000`. +The size may be followed by an optional "k" or "m" to multiply the given value by 1k (1024) or 1M respectively. + +------ + Using STM32 discovery kits with open source tools ======== From 3bc5e6f69944cef9f44e3c56b31beb2609f67722 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 3 Apr 2020 11:49:31 +0200 Subject: [PATCH 0767/1435] [doc] Added reference to tutorial --- README.md | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 5c601f36c..1f9771982 100644 --- a/README.md +++ b/README.md @@ -32,7 +32,12 @@ These programmer boards are available in four versions: ## Supported hardware combinations -Currently known working combinations of programmers and targets are listed in [doc/devices_boards.md](doc/tested-boards.md). +Currently known working combinations of programmers and targets are listed in [devices_boards.md](doc/devices_boards.md). + + +## Tutorial & HOWTO + +Our [tutorial.md](doc/tutorial.md may help you along with some advanced tasks and additional info. ## Installation @@ -77,7 +82,7 @@ When there is no executable available for your platform or you need the latest ( ## License -The stlink library and tools are licensed under the [BSD license](LICENSE.md). +The stlink library and tools are licensed under the [BSD-3 license](LICENSE.md). The flashloaders/stm32l0x.s and flashloaders/stm32lx.s source files are licensed under the GPLv2+. From 27aa88821197d3ffe82baff4e971c3488ec39899 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 4 Apr 2020 13:03:22 +0200 Subject: [PATCH 0768/1435] Updated compiling doc & version support - Added info on version support - Updated compiling instructions - Updated minGW-w64 gcc-TC to v8.1.0 - Minor formatting fixes (Closes #896, #897, #899) --- cmake/modules/FindLibUSB.cmake | 8 +- doc/compiling.md | 284 +++++++++++++++------------------ doc/version_support.md | 82 ++++++++++ include/stlink/stlinkusb.h | 20 +-- scripts/mingw64-build.bat | 2 +- 5 files changed, 230 insertions(+), 166 deletions(-) create mode 100644 doc/version_support.md diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index f88556205..c8f467902 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -6,13 +6,13 @@ # LIBUSB_LIBRARY - The libraries needed to use libusb # LIBUSB_DEFINITIONS - Compiler switches required for using libusb -# FreeBSD -if (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") + +if (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr/include ) -else () +else () # other OS FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr @@ -22,6 +22,8 @@ else () ) endif() + +# macOS if (APPLE) set(LIBUSB_NAME libusb-1.0.a) elseif(MSYS OR MINGW) diff --git a/doc/compiling.md b/doc/compiling.md index 2728c153b..0133981b1 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -1,224 +1,204 @@ # Compiling from sources -## General package requirements -* cmake (v2.8.7 or later) -* C compiler (gcc, clang or mingw) -* libusb-1.0 (v1.0.13 or later) -* libusb-dev-1.0 (v1.0.13 or later) -* pandoc _(optional; for generating manpages from markdown)_ +## Microsoft Windows (10, 8.1) +### Common Requirements -Run from the root of the source directory: +On Windows users should ensure that the following software is installed: -``` -$ make release -$ make debug -``` - -The debug target should only be necessary for people who want to modify the sources and run under a debugger. -The top level Makefile is just a handy wrapper for: +* `7zip` +* `git` +* `cmake` (3.17.0 or later) +* `MinGW-w64` (7.0.0 or later) with GCC toolchain 8.1.0 -``` -$ mkdir build && cd build -$ cmake -DCMAKE_BUILD_TYPE=Debug .. -$ make -``` -You may install to a user folder e.g `$HOME`: +### Installation -``` -$ cd build/Release; make install DESTDIR=$HOME -``` +1. Install `7zip` from +2. Install `git` from +3. Install `cmake` from +4. Install + - _EITHER_: **MinGW-w64** from (mingw-w64-install.exe)
    + Ensure that you add MinGW to the $PATH system variable when following the instructions by the setup assistant.
    + - _OR_: **Visual Studio 2017 CE** (other versions will likely work as well, but are untested; the Community edition is free for open source + development) +5. Create a new destination folder at a place of your choice +6. Open the command-line (cmd.exe) and execute `cd C:\$Path-to-your-destination-folder$\` +7. Fetch the project sourcefiles by running `git clone https://github.com/texane/stlink.git`from the command-line (cmd.exe)
    + or download the stlink zip-sourcefolder from the Release page on GitHub -Or system-wide: -``` -$ cd build/Release; sudo make install -``` +### Building +#### MinGW64 +1. Use the command-line to move to the `scripts` directory within the source-folder: `cd stlink\scripts\` +2. Execute `./mingw64-build.bat` -## Linux / Unix -## Common requirements +NOTE:
    +Per default the build script (currently) uses `C:\Program Files\mingw-w64\x86_64-8.1.0-release-win32-sjlj-rt_v6-rev0\mingw64\bin`.
    +When installing different toolchains make sure to update the path in the `mingw64-build.bat`.
    +This can be achieved by opening the .bat file with a common text editor. -* `build-essential` -* `cmake` -* `libusb-1.0` -* `libusb-1.0-0-dev` (development headers for building, _only on debian based distros_) -* `libgtk-3-dev` _(optional; required for `stlink-gui`)_ -As of today several distributions namely: +#### Visual Studio (32 bit) -- CentOS 6, 7, 8 -- Debian 8, 9, 10, sid -- Fedora 30, 31, Rawhide -- NetBSD 7.2, 8.1, 9.0 -- openSUSE Leap 15.1, Leap 15.2 -- Ubuntu 14.04 LTS, 16.04 LTS, 18.04 LTS, 19.10 +1. In a command prompt, change the directory to the folder where the stlink files were cloned (or unzipped) to. +2. Make sure the build folder exists (`mkdir build` if not). +3. From the build folder, run cmake (`cd build; cmake ..`). -provide packages for libusb 0.1 and libusb 1.0. +This will create a solution (stlink.sln) in the build folder. Open it in Visual Studio, select the Solution Configuration (Debug or +Release) and build the solution normally (F7). -**Please ensure that the correct version 1.0 is installed.** -Other relevant distributions appear to have packages named _libusb-compat-0.1_ or alike to distinguish from libusb packages based on version 1.0.x. +NOTE:
    +This solution will link to the dll version of libusb-1.0.y
    +To debug or run the executable, the dll version of libusb-1.0 must be either on the path, or in the same folder as the executable.
    +It can be copied from here: `build\3thparty\libusb-1.0.21\MS32\dll\libusb-1.0.dll`. +## Linux +### Common requirements -### Fixing cannot open shared object file +Install the following packages from your package repository: -When installing system-wide (`sudo make install`) the dynamic library cache needs to be updated with the command `ldconfig`. +* `gcc` or `clang` or `mingw32-gcc` or `mingw64-gcc` (C-compiler; very likely gcc is already present) +* `build-essential` (on Debian based distros (debian, ubuntu)) +* `cmake` (3.4.2 or later, use the latest version available from the repository) +* `libusb-1.0` +* `libusb-1.0-0-dev` (development headers for building) +* `libgtk-3-dev` (_optional_, needed for `stlink-gui`) +* `pandoc` (_optional_, needed for generating manpages from markdown) +or execute (Debian-based systems only): `apt-get install gcc build-essential cmake libusb-1.0 libusb-1.0-0-dev libgtk-3-dev pandoc` -## Permissions with udev +(Replace gcc with the intended C-compiler if necessary or leave out any optional package not needed.) -Make sure you install udev files which are necessary to run the tools without root permissions. -By default most distributions don't allow access to USB devices. -The udev rules create devices nodes and set the group of this to `stlink`. -The rules are located in the `etc/udev/rules.d` directory. -You will need to copy it to /etc/udev/rules.d, and then either execute as root (or reboot your machine): - -``` -$ udevadm control --reload-rules -$ udevadm trigger -``` - -Udev will now create device node files `/dev/stlinkv2_XX`, `/dev/stlinkv1_XX`. -**You need to make sure the `stlink` group exists and the user, who is trying to access, is added to this group.** - - -### Note for STLINKv1 usage +### Installation -The STLINKv1's SCSI emulation is corrupted, so the best thing to do is tell your operating system to completely ignore it. +1. Open a new terminal console +2. Create a new destination folder at a place of your choice e.g. at `~/git`: `mkdir $HOME/git` +3. Change to this directory: `cd ~/git` +4. Fetch the project sourcefiles by running `git clone https://github.com/texane/stlink.git` -Options (do one of these before you plug it in) -* `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` or - 1. `echo "options usb-storage quirks=483:3744:i" >> /etc/modprobe.conf` - 2. `modprobe -r usb-storage && modprobe usb-storage` -* or - 1. `cp stlink_v1.modprobe.conf /etc/modprobe.d` - 2. `modprobe -r usb-storage && modprobe usb-storage` +### Building +1. Change into the project source directory: `cd stlink` +2. Run `make release` to create the _Release_ target +3. Run `make debug` to create the _Debug_ target (_optional_)
    + The debug target is only necessary in order to modify the sources and to run under a debugger. -### Build Debian Package +The top level Makefile is just a handy wrapper for: -To build the debian package you need the additional packages `devscripts` and `debhelper`. +##### MinGW64: +```sh +$ mkdir build && cd build +$ cmake -DCMAKE_BUILD_TYPE=release -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw64.cmake -S .. +$ make ``` -$ git archive --prefix=$(git describe)/ HEAD | bzip2 --stdout > ../libstlink_$(sed -En -e "s/.*\((.*)\).*/\1/" -e "1,1 p" debian/changelog).orig.tar.bz2 -$ debuild -uc -us -``` - -## macOS -### Prerequisites +##### MinGW32: -When compiling on a mac you need the following: - -* A compiler toolchain (XCode) -* cmake -* **libusb 1.0** - -The best way is to install [homebrew](http://brew.sh) which is a package manager for opensource software which is missing from the Apple App Store. Then install the dependencies: - -``` -brew install libusb cmake +```sh +$ mkdir build && cd build +$ cmake -DCMAKE_BUILD_TYPE=release -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake -S .. +$ make ``` -Compile as described in the first section of this document. - - -## Build using different directories for udev and modprobe +As an alternative you may also install +- to a user folder e.g `$HOME` with `cd build/Release && make install DESTDIR=$HOME` +- or system wide with `cd build/Release && sudo make install`. -To put the udev or the modprobe configuration files into a different directory during installation use the following cmake options: - -``` -$ cmake -DSTLINK_UDEV_RULES_DIR="/usr/lib/udev/rules.d" \ - -DSTLINK_MODPROBED_DIR="/usr/lib/modprobe.d" .. -``` +When installing system-wide, the dynamic library cache needs to be updated with the command `ldconfig`. -## Build using different directory for shared libs +### Build a Debian Package -To put the compiled shared libs into a different directory during installation you can use the following cmake option: +To build the debian package you need the following extra packages: `devscripts debhelper`. +```sh +$ git archive --prefix=$(git describe)/ HEAD | bzip2 --stdout > ../libstlink_$(sed -En -e "s/.*\((.*)\).*/\1/" -e "1,1 p" debian/changelog).orig.tar.bz2 +$ debuild -uc -us ``` -$ cmake -DLIB_INSTALL_DIR:PATH="/usr/lib64" .. -``` - -## Windows (MinGW64) -### Prerequisites -* 7zip -* cmake 2.8 or higher -* MinGW64 GCC toolchain (5.3.0) +### Set permissions with udev +By default most distributions don't allow access to USB devices. +Therefore make sure you install udev files which are necessary to run the tools without root permissions. +udev rules create devices nodes and set the group of these to `stlink`. -### Installation - -1. Install 7zip from -2. Install CMake from -3. Install MinGW64 from (mingw-w64-install.exe) -4. Git clone or download stlink sourcefiles zip +The rules are located in the subdirectory `etc/udev/rules.d` within the sourcefolder. +Copy them to the directory path `/etc/udev/rules.d` and subsequently reload the udev rules: +```sh +$ cp etc/udev/rules.d /etc/udev/rules.d +$ udevadm control --reload-rules +$ udevadm trigger +``` -### Building +Udev will now create device node files `/dev/stlinkv2_XX`, `/dev/stlinkv1_XX`. +You need to ensure that the group `stlink` exists and the user who is trying to access these devices is a member of this group. -Check and execute (in the script folder) `\scripts\mingw64-build.bat` -**NOTE:** when installing different toolchains make sure you edit the path in the `mingw64-build.bat`. -The build script currently uses `C:\Program Files\mingw-w64\x86_64-5.3.0-win32-sjlj-rt_v4-rev0\mingw64\bin` +### Note on the use of STLink-v1 programmers: +At the time of writing the STLink-v1 has mostly been replaced with the newer generation STLink-v2 programmers and thus is only rarely used. +As there are some caveats as well, we recommend to use the STLink-v2 programmers if possible. -## Windows (Visual Studio) -### Prerequisites +To be more precise, the STLINKv1's SCSI emulation is somehow broken, so the best advice possibly is to tell your operating system to completely ignore it. -* 7zip -* cmake (tested with version 3.9.0-rc2) -* Visual Studio 2017 Community Edition (other versions will likely work but are untested; the Community Edition is free for open source -development) +Choose on of the following options _before_ connecting the device to your computer: +* `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` +* _OR_ + 1. `echo "options usb-storage quirks=483:3744:i" >> /etc/modprobe.conf` + 2. `modprobe -r usb-storage && modprobe usb-storage` +* _OR_ + 1. `cp stlink_v1.modprobe.conf /etc/modprobe.d` + 2. `modprobe -r usb-storage && modprobe usb-storage` -### Installation -1. Install 7zip from -2. Install CMake from -3. Git clone or download stlink sourcefiles zip +Author: nightwalker-87 +----- -### Building +---- **The following content is outdated and unrevised!** ---- -These instructions are for a 32-bit version. +## Mac OS X -In a command prompt, change directory to the folder where the stlink files were cloned (or unzipped). -Make sure the build folder exists (`mkdir build` if not). -From the build folder, run cmake (`cd build; cmake ..`). +When compiling on a mac you need the following: -This will create a solution (stlink.sln) in the build folder. -Open it in Visual Studio, select the Solution Configuration (_Debug_ or _Release_) and build the solution normally (F7). +* A compiler toolchain (XCode) +* CMake +* Libusb 1.0 -NOTES: This solution will link to the dll version of libusb-1.0. -To debug or run the executable, the dll version of libusb-1.0 must be either on the path, or in the same folder as the executable. -It can be copied from here: `build\3thparty\libusb-1.0.21\MS32\dll\libusb-1.0.dll`. +The best way is to install [homebrew](http://brew.sh) which is a package manager + for opensource software which is missing from the Apple App Store. Then install + the dependencies: +``` +brew install libusb cmake +``` -## Linux (MinGW64) -### Prerequisites +Compile as described in the first section of this document. -* 7zip -* cmake 2.8 or higher -* MinGW64 GCC toolchain (5.3.0) +## Build using different directories for udev and modprobe -### Installation (Debian / Ubuntu) +To put the udev or the modprobe configuration files into a different directory +during installation you can use the following cmake options: -sudo apt install p7zip mingw-w64 +``` +$ cmake -DSTLINK_UDEV_RULES_DIR="/usr/lib/udev/rules.d" \ + -DSTLINK_MODPROBED_DIR="/usr/lib/modprobe.d" .. +``` -### Building +## Build using different directory for shared libs -These instructions are for a 32-bit version. +To put the compiled shared libs into a different directory during installation +you can use the following cmake option: -```sh -cd -cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake -S . -B ./build/linux-mingw32 -cmake --build ./build/linux-mingw32 --target all +``` +$ cmake -DLIB_INSTALL_DIR:PATH="/usr/lib64" .. ``` diff --git a/doc/version_support.md b/doc/version_support.md new file mode 100644 index 000000000..963ca2988 --- /dev/null +++ b/doc/version_support.md @@ -0,0 +1,82 @@ + +Sources: [pkgs.org - libusb](https://pkgs.org/search/?q=libusb) & [pkgs.org - cmake](https://pkgs.org/search/?q=cmake) (as of Mar 2020): + + +## Supported Operating Systems + +### Microsoft Windows + +On Windows users should ensure that cmake 3.17.0 is installed.
    +Up on compiling c-make will check **automatically**, whether `libusb` 1.0.20 or later is present.
    +If this is not the case, the installation routine will download the latest version (1.0.23 at the time of writing).
    +Thus no user interaction regarding libusb is necessary. + +* Windows 10 +* Windows 8.1 + +### Apple macOS + +On macOS users should ensure that cmake 3.17.0 is installed. + +--> libusb Installation routine: (TBD) Work in progress... + +* macOS 10.15 Catalina +* macOS 10.14 Mojave +* macOS 10.13 High Sierra + +### Linux-/Unix-based: + +| Operating System | libusb
    version | cmake
    version | Notes | +| --- | --- | --- | --- | +| Alpine Edge | 1.0.23 | 3.17.0 | | +| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | | +| Arch Linux | 1.0.23 | 3.17.0 | | +| Fedora Rawhide | 1.0.23 | 3.17.0 | named `libusbx`, but `libusb`-codebase is used | +| KaOS | 1.0.23 | 3.17.0 | | +| OpenMandriva Cooker | 1.0.23 | 3.17.0 | | +| PCLinuxOS | 1.0.23 | 3.17.0 | named `lib64usb1.0_0-1.0.23-1pclos2019.x86_64` | +| Slackware Current | 1.0.23 | 3.17.0 | | +| Solus | 1.0.23 | 3.16.5 | | +| Debian Sid | 1.0.23 | 3.16.3 | | +| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | | +| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | | +| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | | +| Alpine 3.11 | 1.0.23 | 3.15.5 | | +| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | | +| Mageia Cauldron | 1.0.22 | 3.17.0 | | +| NetBSD 9.0 | 1.0.22 | 3.16.1 | | +| NetBSD 8.1 | 1.0.22 | 3.16.1 | | +| NetBSD 7.2 | 1.0.22 | 3.16.1 | | +| Alpine 3.10 | 1.0.22 | 3.14.5 | | +| Fedora 31 | 1.0.22 | 3.14.5 | named `libusbx`, but `libusb`-codebase is used | +| Mageia 7.1 | 1.0.22 | 3.14.3 | | +| Fedora 30 | 1.0.22 | 3.14.2 | named `libusbx`, but `libusb`-codebase is used | +| Debian 10 (Buster) | 1.0.22 | 3.13.4 | | +| Alpine 3.9 | 1.0.22 | 3.13.0 | | +| CentOS 8 | 1.0.22 | 3.11.4 | named `libusbx`, but `libusb`-codebase is used | +| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | | +| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | | +| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | | +| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | | +| Slackware 14.2 | **1.0.20** | 3.5.2 | | +| Ubuntu 16.04 LTS (Xenial Xerus) | **1.0.20** | 3.5.1 | | +| OpenMandriva Lx 3.0 | **1.0.20** | **3.4.2** | | +| FreeBSD 13 | **1.0.16** - 1.0.18 | 3.15.5 | linux_libusb-13.0r358841 (integrated) | +| FreeBSD 12 | **1.0.16** - 1.0.18 | 3.15.5 | linux_libusb-11.0r261448_4 (integrated) | +| FreeBSD 11 | **1.0.16** - 1.0.18 | 3.15.5 | linux_libusb-11.0r261448_4 (integrated) | + + +## Unsupported Operating Systems as of Release 1.6.1 (2020) + +| Operating System | libusb
    version | cmake
    version | End of OS-Support | Notes | +| --- | --- | --- | --- | --- | +| CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but `libusb`-codebase is used | +| Debian 8 (Jessie) | 1.0.**19** | 3.0.2 | Jun 2020 | +| Ubuntu 14.04 LTS (Trusty Tahr) | 1.0.**17** | **2.8.12.2** | Apr 2019 | +| CentOS 6 | 1.0.**9** | **2.8.12.2** | Dec 2020 | named `libusbx`, but `libusb`-codebase is used | +| Slackware 14.1 | 1.0.**9** | **2.8.12** | | +| Slackware 14.0 | 1.0.**9** | **2.8.8** | | + +_All other operating systems which are not listed are unsupported._ + +Author: nightwalker-87 diff --git a/include/stlink/stlinkusb.h b/include/stlink/stlinkusb.h index 4d904b0c5..633d82bd0 100644 --- a/include/stlink/stlinkusb.h +++ b/include/stlink/stlinkusb.h @@ -22,25 +22,25 @@ */ #if defined (__FreeBSD__) -#if !defined ( LIBUSBX_API_VERSION ) -#define LIBUSBX_API_VERSION LIBUSB_API_VERSION -#elif !defined (LIBUSB_API_VERSION) -#error unsupported libusb version -#endif + #if !defined ( LIBUSBX_API_VERSION ) + #define LIBUSBX_API_VERSION LIBUSB_API_VERSION + #elif !defined (LIBUSB_API_VERSION) + #error unsupported libusb version + #endif #endif #if defined (__FreeBSD__) -#define MINIMAL_API_VERSION 0x01000102 + #define MINIMAL_API_VERSION 0x01000102 // v1.0.16 #elif defined (__linux__) -#define MINIMAL_API_VERSION 0x01000104 + #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 #elif defined (__APPLE__) -#define MINIMAL_API_VERSION 0x01000104 + #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 #elif defined (_WIN32) -#define MINIMAL_API_VERSION 0x01000106 + #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 #endif #if ( LIBUSB_API_VERSION < MINIMAL_API_VERSION ) -#error unsupported libusb version + #error unsupported libusb version #endif #endif // STLINKUSB_H diff --git a/scripts/mingw64-build.bat b/scripts/mingw64-build.bat index 3f92ae8e0..773195410 100644 --- a/scripts/mingw64-build.bat +++ b/scripts/mingw64-build.bat @@ -1,5 +1,5 @@ @echo off -set PATH=C:\Program Files (x86)\CMake\bin;C:\Program Files\CMake\bin;C:\Program Files\mingw-w64\x86_64-5.3.0-win32-sjlj-rt_v4-rev0\mingw64\bin;%PATH% +set PATH=C:\Program Files (x86)\CMake\bin;C:\Program Files\CMake\bin;C:\Program Files\mingw-w64\x86_64-8.1.0-release-win32-sjlj-rt_v6-rev0\mingw64\bin;%PATH% cmake -G "MinGW Makefiles" .. mingw32-make mingw32-make install DESTDIR=_install From 587fb48ce4db923cf683b7e9d58471d8166457d3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 5 Apr 2020 14:25:45 +0200 Subject: [PATCH 0769/1435] Updated cmake configuration - Alligned formatting - Updated version requirement - Updated pkg-maintainer - [doc] Added note in compiling manual - Fixed install paths in build script - Updated C-flag -std=gnu99 to gnu11 --- .gitignore | 1 + CMakeLists.txt | 173 ++++++++++++------------- cmake/CPackConfig.cmake | 27 ---- cmake/c_flag_overrides.cmake | 2 +- cmake/{CFlags.cmake => c_flags.cmake} | 12 +- cmake/cpack_config.cmake | 28 ++++ cmake/linux-mingw32.cmake | 6 +- cmake/linux-mingw64.cmake | 6 +- cmake/modules/Find7Zip.cmake | 7 +- cmake/modules/FindLibUSB.cmake | 88 +++++++------ cmake/modules/pandocology.cmake | 2 +- cmake/{Version.cmake => version.cmake} | 7 +- doc/app-example/CMakeLists.txt | 22 ++-- doc/compiling.md | 6 +- doc/man/CMakeLists.txt | 50 +++---- include/CMakeLists.txt | 23 +--- scripts/mingw64-build.bat | 5 +- src/gdbserver/CMakeLists.txt | 7 +- src/tools/gui/CMakeLists.txt | 29 +++-- tests/CMakeLists.txt | 12 +- usr/lib/pkgconfig/CMakeLists.txt | 13 +- 21 files changed, 259 insertions(+), 267 deletions(-) delete mode 100644 cmake/CPackConfig.cmake rename cmake/{CFlags.cmake => c_flags.cmake} (86%) create mode 100644 cmake/cpack_config.cmake rename cmake/{Version.cmake => version.cmake} (94%) diff --git a/.gitignore b/.gitignore index 3a3a5f38a..23e7ddc07 100644 --- a/.gitignore +++ b/.gitignore @@ -1,3 +1,4 @@ build +build-mingw obj-* *.user* diff --git a/CMakeLists.txt b/CMakeLists.txt index 306d3d6ff..4c53f05ea 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,78 +1,81 @@ -cmake_minimum_required(VERSION 2.8.7) +cmake_minimum_required(VERSION 3.4.2) set(CMAKE_USER_MAKE_RULES_OVERRIDE cmake/c_flag_overrides.cmake) + project(stlink C) -set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics Stlink Tools") +set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics ST-LINK Tools") set(STLINK_UDEV_RULES_DIR "/etc/udev/rules.d" CACHE PATH "Udev rules directory") set(STLINK_MODPROBED_DIR "/etc/modprobe.d" CACHE PATH "modprobe.d directory") set(STLINK_STATIC_LIB ON CACHE BOOL "Install static lib") -if( IS_DIRECTORY ${LIB_INSTALL_DIR}) +set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) +set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) +set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) + +if (IS_DIRECTORY ${LIB_INSTALL_DIR}) set(LIB_INSTALL_DIR ${LIB_INSTALL_DIR} CACHE PATH "Main library directory") set(STLINK_LIBRARY_PATH "${LIB_INSTALL_DIR}") -else() +else () set(LIB_INSTALL_DIR "lib" CACHE PATH "Main library directory") set(STLINK_LIBRARY_PATH "${CMAKE_INSTALL_PREFIX}/${LIB_INSTALL_DIR}" ) -endif() +endif () -if( IS_DIRECTORY ${INCLUDE_INSTALL_DIR}) +if (IS_DIRECTORY ${INCLUDE_INSTALL_DIR}) set(INCLUDE_INSTALL_DIR ${INCLUDE_INSTALL_DIR} CACHE PATH "Main include directory") set(STLINK_INCLUDE_PATH "${INCLUDE_INSTALL_DIR}" ) -else() +else () set(INCLUDE_INSTALL_DIR "include" CACHE PATH "Main include directory") set(STLINK_INCLUDE_PATH "${CMAKE_INSTALL_PREFIX}/${INCLUDE_INSTALL_DIR}") -endif() +endif () option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) option(STLINK_INSTALL_UDEV_RULES "Install udev rules files" ON) option(STLINK_INSTALL_MODPROBE_CONF "Install modprobe conf files" ON) -if (POLICY CMP0042) - # Newer cmake on MacOS should use @rpath - cmake_policy (SET CMP0042 NEW) -endif () +# cmake (3.0+) on MacOS should use @rpath +cmake_policy(SET CMP0042 NEW) set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") -include(cmake/Version.cmake) -if(NOT MSVC) - include(cmake/CFlags.cmake) -endif() +include(cmake/version.cmake) +if (NOT MSVC) + include(cmake/c_flags.cmake) +endif () ### # Dependencies ### find_package(LibUSB REQUIRED) if (NOT APPLE AND NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) - find_package(PkgConfig) - pkg_check_modules(gtk gtk+-3.0) + find_package(PkgConfig) + pkg_check_modules(gtk gtk+-3.0) endif () include(CheckIncludeFile) CHECK_INCLUDE_FILE(sys/mman.h STLINK_HAVE_SYS_MMAN_H) if (STLINK_HAVE_SYS_MMAN_H) - add_definitions(-DSTLINK_HAVE_SYS_MMAN_H) -endif() + add_definitions(-DSTLINK_HAVE_SYS_MMAN_H) +endif () CHECK_INCLUDE_FILE(unistd.h STLINK_HAVE_UNISTD_H) if (STLINK_HAVE_UNISTD_H) - add_definitions(-DSTLINK_HAVE_UNISTD_H) -endif() + add_definitions(-DSTLINK_HAVE_UNISTD_H) +endif () include(CheckLibraryExists) CHECK_LIBRARY_EXISTS(ssp __stack_chk_fail "" _stack_chk_fail_exists) -if(_stack_chk_fail_exists) +if (_stack_chk_fail_exists) set(SSP_LIB ssp) -else() +else () set(SSP_LIB "") -endif() +endif () if (CMAKE_BUILD_TYPE STREQUAL "") - set(CMAKE_BUILD_TYPE "Debug") -endif() + set(CMAKE_BUILD_TYPE "Debug") +endif () if (${CMAKE_BUILD_TYPE} MATCHES "Debug") - include(CTest) -endif() + include(CTest) +endif () set(STLINK_HEADERS include/stlink.h @@ -82,7 +85,6 @@ set(STLINK_HEADERS include/stlink/mmap.h include/stlink/chipid.h include/stlink/flash_loader.h - include/stlink/stlinkusb.h ) set(STLINK_SOURCE @@ -95,8 +97,8 @@ set(STLINK_SOURCE ) if (WIN32 OR MSYS OR MINGW) - set (STLINK_SOURCE "${STLINK_SOURCE};src/mmap.c;src/mingw/mingw.c") - set (STLINK_HEADERS "${STLINK_HEADERS};src/mingw/mingw.h") + set (STLINK_SOURCE "${STLINK_SOURCE};src/mmap.c;src/mingw/mingw.c") + set (STLINK_HEADERS "${STLINK_HEADERS};src/mingw/mingw.h") endif () include_directories(${LIBUSB_INCLUDE_DIR}) @@ -104,55 +106,56 @@ include_directories(include) include_directories(${PROJECT_BINARY_DIR}/include) include_directories(src/mingw) if (MSVC) - include_directories(src/win32) - include_directories(src/getopt) - # Use string.h rather than strings.h and disable annoying warnings - add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) + include_directories(src/win32) + include_directories(src/getopt) + # Use string.h rather than strings.h and disable annoying warnings + add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) endif () ### # Shared library ### if (NOT WIN32) -set(STLINK_LIB_SHARED ${PROJECT_NAME}) + set(STLINK_LIB_SHARED ${PROJECT_NAME}) else () -set(STLINK_LIB_SHARED ${PROJECT_NAME}-shared) -endif() + set(STLINK_LIB_SHARED ${PROJECT_NAME}-shared) +endif () -add_library(${STLINK_LIB_SHARED} SHARED - ${STLINK_HEADERS} # header files for ide projects generated by cmake - ${STLINK_SOURCE} -) -target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY}) +add_library( + ${STLINK_LIB_SHARED} SHARED + ${STLINK_HEADERS} # header files for ide projects generated by cmake + ${STLINK_SOURCE} + ) +target_link_libraries( + ${STLINK_LIB_SHARED} + ${LIBUSB_LIBRARY} + ) + +set(STLINK_SHARED_VERSION ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}) -if (WIN32 OR MSYS OR MINGW) - set(STLINK_SHARED_VERSION ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}) -else() - set(STLINK_SHARED_VERSION ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}) -endif() message(STATUS "STLINK_LIB_SHARED: ${STLINK_LIB_SHARED}") message(STATUS "PROJECT_VERSION_MAJOR: ${PROJECT_VERSION_MAJOR}") message(STATUS "VERSION: ${STLINK_SHARED_VERSION}") set_target_properties(${STLINK_LIB_SHARED} - PROPERTIES SOVERSION ${PROJECT_VERSION_MAJOR} - VERSION ${STLINK_SHARED_VERSION} -) + PROPERTIES SOVERSION ${PROJECT_VERSION_MAJOR} + VERSION ${STLINK_SHARED_VERSION} + ) # Link shared library with apple OS libraries if (APPLE) - find_library(ObjC objc) - find_library(CoreFoundation CoreFoundation) - find_library(IOKit IOKit) + find_library(ObjC objc) + find_library(CoreFoundation CoreFoundation) + find_library(IOKit IOKit) target_link_libraries(${STLINK_LIB_SHARED} ${CoreFoundation} ${IOKit} ${ObjC} ${SSP_LIB}) -endif() +endif () if (WIN32 OR MSYS OR MINGW) target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} wsock32 ws2_32 ${SSP_LIB}) -else() +else () target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB}) -endif() +endif () install(TARGETS ${STLINK_LIB_SHARED} @@ -165,31 +168,29 @@ install(TARGETS ${STLINK_LIB_SHARED} set(STLINK_LIB_STATIC ${PROJECT_NAME}-static) add_library(${STLINK_LIB_STATIC} STATIC - ${STLINK_HEADERS} # header files for ide projects generated by cmake - ${STLINK_SOURCE} -) + ${STLINK_HEADERS} # header files for ide projects generated by cmake + ${STLINK_SOURCE} + ) # Link shared library with apple OS libraries if (APPLE) - find_library(ObjC objc) - find_library(CoreFoundation CoreFoundation) - find_library(IOKit IOKit) + find_library(ObjC objc) + find_library(CoreFoundation CoreFoundation) + find_library(IOKit IOKit) target_link_libraries(${STLINK_LIB_STATIC} ${CoreFoundation} ${IOKit} ${ObjC} ${SSP_LIB}) endif() if (WIN32 OR MSYS OR MINGW) target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} wsock32 ws2_32 ${SSP_LIB}) -else() +else () target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB}) -endif() +endif () set_target_properties(${STLINK_LIB_STATIC} PROPERTIES OUTPUT_NAME ${PROJECT_NAME}) if (STLINK_STATIC_LIB) - install(TARGETS ${STLINK_LIB_STATIC} - ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH} - ) -endif() + install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH}) +endif () ### # Tools @@ -197,32 +198,28 @@ endif() add_executable(st-flash src/tools/flash.c src/tools/flash_opts.c) if (WIN32 OR APPLE) target_link_libraries(st-flash ${STLINK_LIB_STATIC} ${SSP_LIB}) -else() +else () target_link_libraries(st-flash ${STLINK_LIB_SHARED} ${SSP_LIB}) -endif() +endif () add_executable(st-info src/tools/info.c) if (WIN32 OR APPLE) target_link_libraries(st-info ${STLINK_LIB_STATIC} ${SSP_LIB}) -else() +else () target_link_libraries(st-info ${STLINK_LIB_SHARED} ${SSP_LIB}) -endif() +endif () -install(TARGETS st-flash st-info - RUNTIME DESTINATION bin -) +install(TARGETS st-flash st-info RUNTIME DESTINATION bin) if (CMAKE_SYSTEM_NAME STREQUAL "Linux") - if (STLINK_INSTALL_MODPROBE_CONF) - install(FILES etc/modprobe.d/stlink_v1.conf - DESTINATION ${STLINK_MODPROBED_DIR}/) - endif() - if (STLINK_INSTALL_UDEV_RULES) - file(GLOB RULES_FILES etc/udev/rules.d/*.rules) - install(FILES ${RULES_FILES} - DESTINATION ${STLINK_UDEV_RULES_DIR}/) - endif() -endif() + if (STLINK_INSTALL_MODPROBE_CONF) + install(FILES etc/modprobe.d/stlink_v1.conf DESTINATION ${STLINK_MODPROBED_DIR}/) + endif () + if (STLINK_INSTALL_UDEV_RULES) + file(GLOB RULES_FILES etc/udev/rules.d/*.rules) + install(FILES ${RULES_FILES} DESTINATION ${STLINK_UDEV_RULES_DIR}/) + endif () +endif () add_subdirectory(src/gdbserver) add_subdirectory(src/tools/gui) @@ -235,5 +232,5 @@ add_subdirectory(include) add_subdirectory(doc/man) add_subdirectory(tests) -include(cmake/CPackConfig.cmake) +include(cmake/cpack_config.cmake) include(CPack) diff --git a/cmake/CPackConfig.cmake b/cmake/CPackConfig.cmake deleted file mode 100644 index 20768453b..000000000 --- a/cmake/CPackConfig.cmake +++ /dev/null @@ -1,27 +0,0 @@ -set (CPACK_PACKAGE_NAME ${PROJECT_NAME}) -set (CPACK_PACKAGE_VERSION ${PROJECT_VERSION}) -set (CPACK_SET_DESTDIR "ON") -if (APPLE) - set(CPACK_GENERATOR "ZIP") - set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-macosx-amd64") - file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/osx") - set (CPACK_INSTALL_PREFIX "") - set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/osx") -elseif (WIN32) - set(CPACK_GENERATOR "ZIP") - file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/windows") - set (CPACK_INSTALL_PREFIX "") - set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/windows") -elseif(${CMAKE_SYSTEM_NAME} STREQUAL "Linux" AND EXISTS "/etc/debian_version") - message(STATUS "Debian-based Linux OS detected") - set(CPACK_GENERATOR "DEB") - - if ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "x86_64") - set(CPACK_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${PROJECT_VERSION}-amd64" ) - endif() - - set(CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/texane/stlink") - set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Jerry Jacobs") - set(CPACK_PACKAGE_CONTACT "jerry.jacobs@xor-gate.org") - set(CPACK_DEBIAN_PACKAGE_DESCRIPTION "STM32 stlink programmer tools") -endif() diff --git a/cmake/c_flag_overrides.cmake b/cmake/c_flag_overrides.cmake index 663e08175..c15815e17 100644 --- a/cmake/c_flag_overrides.cmake +++ b/cmake/c_flag_overrides.cmake @@ -1,6 +1,6 @@ if(MSVC) message(STATUS "MSVC C Flags override to /MT") - set(CMAKE_C_FLAGS_DEBUG_INIT "/D_DEBUG /MTd /Zi /Ob0 /Od /RTC1") + set(CMAKE_C_FLAGS_DEBUG_INIT "/D_DEBUG /MTd /Zi /Ob0 /Od /RTC1") set(CMAKE_C_FLAGS_MINSIZEREL_INIT "/MT /O1 /Ob1 /D NDEBUG") set(CMAKE_C_FLAGS_RELEASE_INIT "/MT /O2 /Ob2 /D NDEBUG") set(CMAKE_C_FLAGS_RELWITHDEBINFO_INIT "/MT /Zi /O2 /Ob1 /D NDEBUG") diff --git a/cmake/CFlags.cmake b/cmake/c_flags.cmake similarity index 86% rename from cmake/CFlags.cmake rename to cmake/c_flags.cmake index b76856d24..fbadd6d9e 100644 --- a/cmake/CFlags.cmake +++ b/cmake/c_flags.cmake @@ -14,7 +14,7 @@ function(add_cflag_if_supported flag) endif() endfunction() -add_cflag_if_supported("-std=gnu99") +add_cflag_if_supported("-std=gnu11") add_cflag_if_supported("-Wall") add_cflag_if_supported("-Wextra") add_cflag_if_supported("-Wshadow") @@ -34,17 +34,17 @@ add_cflag_if_supported("-Wimplicit-function-declaration") # /usr/include/sys/types.h:218: warning: previous declaration of 'truncate' was here ## if (NOT CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") - add_cflag_if_supported("-Wredundant-decls") + add_cflag_if_supported("-Wredundant-decls") endif () if (NOT WIN32) - add_cflag_if_supported("-fPIC") + add_cflag_if_supported("-fPIC") endif () if(${CMAKE_BUILD_TYPE} MATCHES "Debug") - add_cflag_if_supported("-ggdb") - add_cflag_if_supported("-O0") + add_cflag_if_supported("-ggdb") + add_cflag_if_supported("-O0") else() - add_cflag_if_supported("-O2") + add_cflag_if_supported("-O2") add_cflag_if_supported("-Werror") endif() diff --git a/cmake/cpack_config.cmake b/cmake/cpack_config.cmake new file mode 100644 index 000000000..72a98a821 --- /dev/null +++ b/cmake/cpack_config.cmake @@ -0,0 +1,28 @@ +set (CPACK_PACKAGE_NAME ${PROJECT_NAME}) +set (CPACK_PACKAGE_VERSION ${PROJECT_VERSION}) +set (CPACK_SET_DESTDIR "ON") + +if (APPLE) + set(CPACK_GENERATOR "ZIP") + set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-macosx-amd64") + file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/osx") + set (CPACK_INSTALL_PREFIX "") + set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/osx") +elseif (WIN32) + set(CPACK_GENERATOR "ZIP") + file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/windows") + set (CPACK_INSTALL_PREFIX "") + set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/windows") +elseif (${CMAKE_SYSTEM_NAME} STREQUAL "Linux" AND EXISTS "/etc/debian_version") + message(STATUS "Debian-based Linux OS detected") + set(CPACK_GENERATOR "DEB") + + if ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "x86_64") + set(CPACK_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${PROJECT_VERSION}-amd64" ) + endif() + + set(CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/texane/stlink") + set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Luca Boccassi") + set(CPACK_PACKAGE_CONTACT "bluca@debian.org") + set(CPACK_DEBIAN_PACKAGE_DESCRIPTION "STM32 STlink programmer tools") +endif() diff --git a/cmake/linux-mingw32.cmake b/cmake/linux-mingw32.cmake index 2044a7e22..2b4799037 100644 --- a/cmake/linux-mingw32.cmake +++ b/cmake/linux-mingw32.cmake @@ -1,4 +1,4 @@ -# Sample toolchain file for building for Windows from an Debian/Ubuntu Linux system. +# Sample toolchain file for building for Windows from a Debian/Ubuntu Linux system. # # Typical usage: # *) install cross compiler: `sudo apt-get install mingw-w64` @@ -14,7 +14,7 @@ set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}-g++) set(CMAKE_RC_COMPILER ${TOOLCHAIN_PREFIX}-windres) # target environment on the build host system -# set 1st to dir with the cross compiler's C/C++ headers/libs +# set 1st to dir with the cross compiler's C/C++ headers/libs set(CMAKE_FIND_ROOT_PATH /usr/${TOOLCHAIN_PREFIX}) # modify default behavior of FIND_XXX() commands to @@ -22,4 +22,4 @@ set(CMAKE_FIND_ROOT_PATH /usr/${TOOLCHAIN_PREFIX}) # search for programs in the build host environment set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) \ No newline at end of file +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) diff --git a/cmake/linux-mingw64.cmake b/cmake/linux-mingw64.cmake index db4bd70d0..f8b523965 100644 --- a/cmake/linux-mingw64.cmake +++ b/cmake/linux-mingw64.cmake @@ -1,4 +1,4 @@ -# Sample toolchain file for building for Windows from an Ubuntu Linux system. +# Sample toolchain file for building for Windows from a Debian/Ubuntu Linux system. # # Typical usage: # *) install cross compiler: `sudo apt-get install mingw-w64` @@ -14,7 +14,7 @@ set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}-g++) set(CMAKE_RC_COMPILER ${TOOLCHAIN_PREFIX}-windres) # target environment on the build host system -# set 1st to dir with the cross compiler's C/C++ headers/libs +# set 1st to dir with the cross compiler's C/C++ headers/libs set(CMAKE_FIND_ROOT_PATH /usr/${TOOLCHAIN_PREFIX}) # modify default behavior of FIND_XXX() commands to @@ -22,4 +22,4 @@ set(CMAKE_FIND_ROOT_PATH /usr/${TOOLCHAIN_PREFIX}) # search for programs in the build host environment set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) \ No newline at end of file +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) diff --git a/cmake/modules/Find7Zip.cmake b/cmake/modules/Find7Zip.cmake index e4d33dfce..c462f73de 100644 --- a/cmake/modules/Find7Zip.cmake +++ b/cmake/modules/Find7Zip.cmake @@ -1,5 +1,4 @@ -find_program(ZIP_EXECUTABLE NAMES 7z.exe p7zip - HINTS - "C:\\Program Files\\7-Zip\\" - "C:\\Program Files (x86)\\7-Zip\\" +find_program( + ZIP_EXECUTABLE NAMES 7z.exe p7zip + HINTS "C:\\Program Files\\7-Zip\\" "C:\\Program Files (x86)\\7-Zip\\" ) diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index c8f467902..a8b65cba3 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -8,56 +8,60 @@ if (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD - FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h - HINTS - /usr/include - ) + FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h + HINTS + /usr/include + ) else () # other OS - FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h - HINTS - /usr - /usr/local - /opt - PATH_SUFFIXES libusb-1.0 - ) + FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h + HINTS + /usr + /usr/local + /opt + PATH_SUFFIXES libusb-1.0 + ) endif() # macOS if (APPLE) - set(LIBUSB_NAME libusb-1.0.a) + set(LIBUSB_NAME libusb-1.0.a) elseif(MSYS OR MINGW) - set(LIBUSB_NAME usb-1.0) + set(LIBUSB_NAME usb-1.0) elseif(MSVC) - set(LIBUSB_NAME libusb-1.0.lib) + set(LIBUSB_NAME libusb-1.0.lib) elseif(CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") - set(LIBUSB_NAME usb) + set(LIBUSB_NAME usb) else() - set(LIBUSB_NAME usb-1.0) + set(LIBUSB_NAME usb-1.0) endif() if (MSYS OR MINGW) - if (CMAKE_SIZEOF_VOID_P EQUAL 8) - find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/static) - else () - find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW32/static) - endif () -elseif(MSVC) - if (CMAKE_SIZEOF_VOID_P EQUAL 8) - find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + if (CMAKE_SIZEOF_VOID_P EQUAL 8) + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/static) + else () + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW32/static) + endif () +elseif (MSVC) + if (CMAKE_SIZEOF_VOID_P EQUAL 8) + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS64/dll) - else () - find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS32/dll) - endif () + else () + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS32/dll) + endif () else() - find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS - /usr - /usr/local - /opt) + find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS + /usr + /usr/local + /opt) endif () include(FindPackageHandleStandardArgs) @@ -72,7 +76,7 @@ if(NOT LIBUSB_FOUND) set(LIBUSB_WIN_VERSION 1.0.23) set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) - set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/3thparty/libusb-${LIBUSB_WIN_VERSION}) + set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/3rdparty/libusb-${LIBUSB_WIN_VERSION}) if(EXISTS ${LIBUSB_WIN_ARCHIVE_PATH}) message(STATUS "libusb archive already in build folder") @@ -102,13 +106,15 @@ if(NOT LIBUSB_FOUND) if (MSYS OR MINGW) if (CMAKE_SIZEOF_VOID_P EQUAL 8) - find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/static NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH ) else () - find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW32/static NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH @@ -116,13 +122,15 @@ if(NOT LIBUSB_FOUND) endif () elseif(MSVC) if (CMAKE_SIZEOF_VOID_P EQUAL 8) - find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS64/dll NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH ) else () - find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS32/dll NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH diff --git a/cmake/modules/pandocology.cmake b/cmake/modules/pandocology.cmake index f39f8d952..763eae558 100644 --- a/cmake/modules/pandocology.cmake +++ b/cmake/modules/pandocology.cmake @@ -93,6 +93,7 @@ function(pandocology_get_file_extension varname filename) STRING(REGEX MATCH "\\.[^.]*\$" result "${name}") SET(${varname} "${result}" PARENT_SCOPE) endfunction() + ############################################################################### function(pandocology_add_input_dir source_dir dest_parent_dir dir_dest_filelist_var) @@ -370,4 +371,3 @@ endfunction() function(add_pandoc_document) add_document(${ARGV}) endfunction() - diff --git a/cmake/Version.cmake b/cmake/version.cmake similarity index 94% rename from cmake/Version.cmake rename to cmake/version.cmake index 71859015c..bdfe95ace 100644 --- a/cmake/Version.cmake +++ b/cmake/version.cmake @@ -60,8 +60,6 @@ else() message(STATUS "Git or repo not found.") endif() - - if(NOT __detect_version) message(STATUS "Try to detect version from \"${PROJECT_SOURCE_DIR}/.version\" file.") if(EXISTS ${PROJECT_SOURCE_DIR}/.version) @@ -71,7 +69,7 @@ if(NOT __detect_version) # TODO create function to extract semver from file or string and check if it is correct instead of copy-pasting string(REGEX REPLACE "^(0|[1-9][0-9]*)[.](0|[1-9][0-9]*)[.](0|[1-9][0-9]*)(-[.0-9A-Za-z-]+)?([+][.0-9A-Za-z-]+)?$" - "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) + "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) list(LENGTH PROJECT_VERSION_LIST len) if(len EQUAL 3) list(GET PROJECT_VERSION_LIST 0 PROJECT_VERSION_MAJOR) @@ -90,6 +88,5 @@ if(NOT __detect_version) message(FATAL_ERROR "Unable to determine project version") endif() - message(STATUS "stlink version: ${PROJECT_VERSION}") -message(STATUS " Major ${PROJECT_VERSION_MAJOR} Minor ${PROJECT_VERSION_MINOR} Patch ${PROJECT_VERSION_PATCH}") +message(STATUS "Major ${PROJECT_VERSION_MAJOR} Minor ${PROJECT_VERSION_MINOR} Patch ${PROJECT_VERSION_PATCH}") diff --git a/doc/app-example/CMakeLists.txt b/doc/app-example/CMakeLists.txt index 0e91bed6f..a7697720c 100644 --- a/doc/app-example/CMakeLists.txt +++ b/doc/app-example/CMakeLists.txt @@ -1,12 +1,11 @@ -# Warning: This example assumes that you are building on a host -# with pkg-config available (e.g. linux). The logic required to -# build under windows/mingw and/or mac was intentionally omitted -# to keep this CMakeLists as small as possible +# Warning: This example assumes that you are building on a host with pkg-config available (e.g. linux). +# The logic required to build under windows/mingw and/or mac was intentionally omitted to keep this +# CMakeLists as small as possible. -cmake_minimum_required(VERSION 2.8) +cmake_minimum_required(VERSION 3.4.2) project(st-hello) -set(PROJECT_VERSION 0.1) +set(PROJECT_VERSION 0.1) set(SRCS main.c) find_package(PkgConfig) @@ -14,15 +13,10 @@ pkg_check_modules(STLINK REQUIRED stlink) set(CMAKE_C_FLAGS " ${STLINK_CFLAGS_OTHER} -Wall -Werror") -include_directories( - ${STLINK_INCLUDE_DIRS} -) +include_directories(${STLINK_INCLUDE_DIRS}) add_executable(${PROJECT_NAME} ${SRCS}) -target_link_libraries(${PROJECT_NAME} - ${STLINK_LIBRARIES} -) +target_link_libraries(${PROJECT_NAME} ${STLINK_LIBRARIES}) -install(TARGETS ${PROJECT_NAME} - DESTINATION bin) +install(TARGETS ${PROJECT_NAME} DESTINATION bin) diff --git a/doc/compiling.md b/doc/compiling.md index 0133981b1..bcaf7d567 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -15,10 +15,10 @@ On Windows users should ensure that the following software is installed: 1. Install `7zip` from 2. Install `git` from -3. Install `cmake` from +3. Install `cmake` from
    + Ensure that you add cmake to the $PATH system variable when following the instructions by the setup assistant. 4. Install - _EITHER_: **MinGW-w64** from (mingw-w64-install.exe)
    - Ensure that you add MinGW to the $PATH system variable when following the instructions by the setup assistant.
    - _OR_: **Visual Studio 2017 CE** (other versions will likely work as well, but are untested; the Community edition is free for open source development) 5. Create a new destination folder at a place of your choice @@ -51,7 +51,7 @@ Release) and build the solution normally (F7). NOTE:
    This solution will link to the dll version of libusb-1.0.y
    To debug or run the executable, the dll version of libusb-1.0 must be either on the path, or in the same folder as the executable.
    -It can be copied from here: `build\3thparty\libusb-1.0.21\MS32\dll\libusb-1.0.dll`. +It can be copied from here: `build\3rdparty\libusb-1.0.21\MS32\dll\libusb-1.0.dll`. ## Linux ### Common requirements diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 949cd2fcf..dce8fbfa6 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -1,37 +1,37 @@ set(MANPAGES - st-util - st-flash - st-info -) + st-util + st-flash + st-info + ) # Only generate manpages with pandoc in Debug builds if(${STLINK_GENERATE_MANPAGES}) - include(pandocology) + include(pandocology) - foreach(manpage ${MANPAGES}) - add_document( - ${manpage}.1 - SOURCES ${manpage}.md - PANDOC_DIRECTIVES -s -t man - PRODUCT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - ) - endforeach() + foreach(manpage ${MANPAGES}) + add_document( + ${manpage}.1 + SOURCES ${manpage}.md + PANDOC_DIRECTIVES -s -t man + PRODUCT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + ) + endforeach() else() - message(STATUS "Manpage generation disabled") + message(STATUS "Manpage generation disabled") endif() # Install from output folder or this folder foreach(manpage ${MANPAGES}) - if(EXISTS ${CMAKE_CURRENT_BINARY_DIR}/${manpage}.1) - set(f "${CMAKE_CURRENT_BINARY_DIR}/${manpage}.1") - elseif(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${manpage}.1") - set(f "${CMAKE_CURRENT_SOURCE_DIR}/${manpage}.1") - else() - message(AUTHOR_WARNING "Manpage ${manpage} not generated") - endif() + if(EXISTS ${CMAKE_CURRENT_BINARY_DIR}/${manpage}.1) + set(f "${CMAKE_CURRENT_BINARY_DIR}/${manpage}.1") + elseif(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${manpage}.1") + set(f "${CMAKE_CURRENT_SOURCE_DIR}/${manpage}.1") + else() + message(AUTHOR_WARNING "Manpage ${manpage} not generated") + endif() - if (f AND NOT WIN32) - install(FILES ${f} DESTINATION ${CMAKE_INSTALL_PREFIX}/share/man/man1) - unset(f) - endif() + if (f AND NOT WIN32) + install(FILES ${f} DESTINATION ${CMAKE_INSTALL_PREFIX}/share/man/man1) + unset(f) + endif() endforeach() diff --git a/include/CMakeLists.txt b/include/CMakeLists.txt index a5121aee5..94df89958 100644 --- a/include/CMakeLists.txt +++ b/include/CMakeLists.txt @@ -1,17 +1,8 @@ configure_file( - "${PROJECT_SOURCE_DIR}/include/stlink/version.h.in" - "${CMAKE_BINARY_DIR}/include/stlink/version.h" -) -file(GLOB STLINK_HEADERS - "stlink/*.h" - "${CMAKE_BINARY_DIR}/include/stlink/*.h" -) -install(FILES ${CMAKE_SOURCE_DIR}/include/stlink.h - DESTINATION ${STLINK_INCLUDE_PATH} -) -install(FILES ${CMAKE_SOURCE_DIR}/include/stm32.h - DESTINATION ${STLINK_INCLUDE_PATH} -) -install(FILES ${STLINK_HEADERS} - DESTINATION ${STLINK_INCLUDE_PATH}/stlink -) + "${PROJECT_SOURCE_DIR}/include/stlink/version.h.in" + "${CMAKE_BINARY_DIR}/include/stlink/version.h" + ) +file(GLOB STLINK_HEADERS "stlink/*.h" "${CMAKE_BINARY_DIR}/include/stlink/*.h") +install(FILES ${CMAKE_SOURCE_DIR}/include/stlink.h DESTINATION ${STLINK_INCLUDE_PATH}) +install(FILES ${CMAKE_SOURCE_DIR}/include/stm32.h DESTINATION ${STLINK_INCLUDE_PATH}) +install(FILES ${STLINK_HEADERS} DESTINATION ${STLINK_INCLUDE_PATH}/stlink) diff --git a/scripts/mingw64-build.bat b/scripts/mingw64-build.bat index 773195410..15ec21cd0 100644 --- a/scripts/mingw64-build.bat +++ b/scripts/mingw64-build.bat @@ -1,5 +1,8 @@ @echo off -set PATH=C:\Program Files (x86)\CMake\bin;C:\Program Files\CMake\bin;C:\Program Files\mingw-w64\x86_64-8.1.0-release-win32-sjlj-rt_v6-rev0\mingw64\bin;%PATH% +cd .. +mkdir build-mingw +cd build-mingw +set PATH=C:\Program Files (x86)\CMake\bin;C:\Program Files\CMake\bin;C:\Program Files\mingw-w64\x86_64-8.1.0-win32-sjlj-rt_v6-rev0\mingw64\bin;%PATH% cmake -G "MinGW Makefiles" .. mingw32-make mingw32-make install DESTDIR=_install diff --git a/src/gdbserver/CMakeLists.txt b/src/gdbserver/CMakeLists.txt index b4674ebbb..5fb0c1ab8 100644 --- a/src/gdbserver/CMakeLists.txt +++ b/src/gdbserver/CMakeLists.txt @@ -4,7 +4,8 @@ set(STUTIL_SOURCE gdb-server.c gdb-server.h semihosting.c - semihosting.h) + semihosting.h + ) if (MSVC) # We need a getopt from somewhere... @@ -19,6 +20,4 @@ else() target_link_libraries(st-util ${STLINK_LIB_SHARED} ${SSP_LIB}) endif() -install(TARGETS st-util - RUNTIME DESTINATION bin -) +install(TARGETS st-util RUNTIME DESTINATION bin) diff --git a/src/tools/gui/CMakeLists.txt b/src/tools/gui/CMakeLists.txt index 91aabc53b..850f483a9 100644 --- a/src/tools/gui/CMakeLists.txt +++ b/src/tools/gui/CMakeLists.txt @@ -1,5 +1,6 @@ if (NOT gtk_FOUND) - return() + message(STATUS "gtk not found!") + return() endif() set(GUI_SOURCES stlink-gui.c stlink-gui.h) @@ -8,26 +9,26 @@ set(INSTALLED_UI_DIR share/stlink) include_directories(SYSTEM ${gtk_INCLUDE_DIRS}) add_executable(stlink-gui-local ${GUI_SOURCES}) -set_target_properties(stlink-gui-local PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_CURRENT_SOURCE_DIR}") +set_target_properties( + stlink-gui-local PROPERTIES + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_CURRENT_SOURCE_DIR}" + ) target_link_libraries(stlink-gui-local ${STLINK_LIB_STATIC} ${gtk_LDFLAGS} ${SSP_LIB}) add_executable(stlink-gui ${GUI_SOURCES}) -set_target_properties(stlink-gui PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/${INSTALLED_UI_DIR}") +set_target_properties( + stlink-gui PROPERTIES + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/${INSTALLED_UI_DIR}" + ) target_link_libraries(stlink-gui ${STLINK_LIB_STATIC} ${gtk_LDFLAGS} ${SSP_LIB}) -install(TARGETS stlink-gui - RUNTIME DESTINATION bin) -install(FILES stlink-gui.ui - DESTINATION ${INSTALLED_UI_DIR}) +install(TARGETS stlink-gui RUNTIME DESTINATION bin) +install(FILES stlink-gui.ui DESTINATION ${INSTALLED_UI_DIR}) + if (${CMAKE_SYSTEM_NAME} MATCHES "Linux") # Install desktop entry - install(FILES stlink-gui.desktop - DESTINATION share/applications) + install(FILES stlink-gui.desktop DESTINATION share/applications) # Install icon - install(FILES art/stlink-gui.svg - DESTINATION share/icons/hicolor/scalable/apps) + install(FILES art/stlink-gui.svg DESTINATION share/icons/hicolor/scalable/apps) endif (${CMAKE_SYSTEM_NAME} MATCHES "Linux") - diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 9d0bdffaf..e8ec5fec0 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -1,13 +1,13 @@ set(TESTS - usb - sg -) + usb + sg + ) foreach(test ${TESTS}) - add_executable(${test} ${test}.c) - add_dependencies(${test} ${STLINK_LIB_STATIC}) + add_executable(${test} ${test}.c) + add_dependencies(${test} ${STLINK_LIB_STATIC}) target_link_libraries(${test} ${STLINK_LIB_STATIC} ${SSP_LIB}) - add_test(${test} ${CMAKE_CURRENT_BINARY_DIR}/${test}) + add_test(${test} ${CMAKE_CURRENT_BINARY_DIR}/${test}) endforeach() add_executable(flash flash.c "${CMAKE_SOURCE_DIR}/src/tools/flash_opts.c") diff --git a/usr/lib/pkgconfig/CMakeLists.txt b/usr/lib/pkgconfig/CMakeLists.txt index a656ff623..5a8227125 100644 --- a/usr/lib/pkgconfig/CMakeLists.txt +++ b/usr/lib/pkgconfig/CMakeLists.txt @@ -5,10 +5,11 @@ set(PKG_CONFIG_CFLAGS "-I\${includedir}") set(PKG_CONFIG_REQUIRES "libusb-1.0") configure_file( - "${CMAKE_CURRENT_SOURCE_DIR}/pkg-config.pc.cmake" - "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" -) + "${CMAKE_CURRENT_SOURCE_DIR}/pkg-config.pc.cmake" + "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" + ) -install(FILES "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" - DESTINATION ${STLINK_LIBRARY_PATH}/pkgconfig/ -) +install( + FILES "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" + DESTINATION ${STLINK_LIBRARY_PATH}/pkgconfig/ + ) From 1818d9375d324cb4c02809e9204abe419805be30 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 5 Apr 2020 14:57:59 +0200 Subject: [PATCH 0770/1435] Fixed indentation & whitespace. --- CMakeLists.txt | 103 +++++++++++++++++-------------- doc/man/CMakeLists.txt | 59 ++++++++---------- include/CMakeLists.txt | 4 +- src/gdbserver/CMakeLists.txt | 6 +- src/tools/gui/CMakeLists.txt | 10 +-- tests/CMakeLists.txt | 15 ++--- usr/lib/pkgconfig/CMakeLists.txt | 6 +- 7 files changed, 103 insertions(+), 100 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 4c53f05ea..5d5dab72e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -40,9 +40,11 @@ if (NOT MSVC) include(cmake/c_flags.cmake) endif () + ### # Dependencies ### + find_package(LibUSB REQUIRED) if (NOT APPLE AND NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) find_package(PkgConfig) @@ -78,27 +80,27 @@ if (${CMAKE_BUILD_TYPE} MATCHES "Debug") endif () set(STLINK_HEADERS - include/stlink.h - include/stlink/usb.h - include/stlink/sg.h - include/stlink/logging.h - include/stlink/mmap.h - include/stlink/chipid.h - include/stlink/flash_loader.h -) + include/stlink.h + include/stlink/usb.h + include/stlink/sg.h + include/stlink/logging.h + include/stlink/mmap.h + include/stlink/chipid.h + include/stlink/flash_loader.h + ) set(STLINK_SOURCE - src/chipid.c - src/common.c - src/usb.c - src/sg.c - src/logging.c - src/flash_loader.c -) + src/chipid.c + src/common.c + src/usb.c + src/sg.c + src/logging.c + src/flash_loader.c + ) if (WIN32 OR MSYS OR MINGW) set (STLINK_SOURCE "${STLINK_SOURCE};src/mmap.c;src/mingw/mingw.c") - set (STLINK_HEADERS "${STLINK_HEADERS};src/mingw/mingw.h") + set (STLINK_HEADERS "${STLINK_HEADERS};src/mingw/mingw.h") endif () include_directories(${LIBUSB_INCLUDE_DIR}) @@ -106,15 +108,17 @@ include_directories(include) include_directories(${PROJECT_BINARY_DIR}/include) include_directories(src/mingw) if (MSVC) - include_directories(src/win32) - include_directories(src/getopt) - # Use string.h rather than strings.h and disable annoying warnings - add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) + include_directories(src/win32) + include_directories(src/getopt) + # Use string.h rather than strings.h and disable annoying warnings + add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) endif () + ### # Shared library ### + if (NOT WIN32) set(STLINK_LIB_SHARED ${PROJECT_NAME}) else () @@ -123,8 +127,8 @@ endif () add_library( ${STLINK_LIB_SHARED} SHARED - ${STLINK_HEADERS} # header files for ide projects generated by cmake - ${STLINK_SOURCE} + ${STLINK_HEADERS} # header files for ide projects generated by cmake + ${STLINK_SOURCE} ) target_link_libraries( ${STLINK_LIB_SHARED} @@ -133,21 +137,21 @@ target_link_libraries( set(STLINK_SHARED_VERSION ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}) - message(STATUS "STLINK_LIB_SHARED: ${STLINK_LIB_SHARED}") message(STATUS "PROJECT_VERSION_MAJOR: ${PROJECT_VERSION_MAJOR}") message(STATUS "VERSION: ${STLINK_SHARED_VERSION}") -set_target_properties(${STLINK_LIB_SHARED} +set_target_properties( + ${STLINK_LIB_SHARED} PROPERTIES SOVERSION ${PROJECT_VERSION_MAJOR} - VERSION ${STLINK_SHARED_VERSION} + VERSION ${STLINK_SHARED_VERSION} ) # Link shared library with apple OS libraries if (APPLE) - find_library(ObjC objc) - find_library(CoreFoundation CoreFoundation) - find_library(IOKit IOKit) + find_library(ObjC objc) + find_library(CoreFoundation CoreFoundation) + find_library(IOKit IOKit) target_link_libraries(${STLINK_LIB_SHARED} ${CoreFoundation} ${IOKit} ${ObjC} ${SSP_LIB}) endif () @@ -157,28 +161,31 @@ else () target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB}) endif () +install( + TARGETS ${STLINK_LIB_SHARED} + DESTINATION ${STLINK_LIBRARY_PATH} + ) -install(TARGETS ${STLINK_LIB_SHARED} - DESTINATION ${STLINK_LIBRARY_PATH} -) ### # Static library ### + set(STLINK_LIB_STATIC ${PROJECT_NAME}-static) -add_library(${STLINK_LIB_STATIC} STATIC - ${STLINK_HEADERS} # header files for ide projects generated by cmake - ${STLINK_SOURCE} - ) +add_library( + ${STLINK_LIB_STATIC} STATIC + ${STLINK_HEADERS} # header files for ide projects generated by cmake + ${STLINK_SOURCE} +) # Link shared library with apple OS libraries if (APPLE) - find_library(ObjC objc) - find_library(CoreFoundation CoreFoundation) - find_library(IOKit IOKit) + find_library(ObjC objc) + find_library(CoreFoundation CoreFoundation) + find_library(IOKit IOKit) target_link_libraries(${STLINK_LIB_STATIC} ${CoreFoundation} ${IOKit} ${ObjC} ${SSP_LIB}) -endif() +endif () if (WIN32 OR MSYS OR MINGW) target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} wsock32 ws2_32 ${SSP_LIB}) @@ -192,9 +199,11 @@ if (STLINK_STATIC_LIB) install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH}) endif () + ### # Tools ### + add_executable(st-flash src/tools/flash.c src/tools/flash_opts.c) if (WIN32 OR APPLE) target_link_libraries(st-flash ${STLINK_LIB_STATIC} ${SSP_LIB}) @@ -212,21 +221,23 @@ endif () install(TARGETS st-flash st-info RUNTIME DESTINATION bin) if (CMAKE_SYSTEM_NAME STREQUAL "Linux") - if (STLINK_INSTALL_MODPROBE_CONF) - install(FILES etc/modprobe.d/stlink_v1.conf DESTINATION ${STLINK_MODPROBED_DIR}/) - endif () - if (STLINK_INSTALL_UDEV_RULES) - file(GLOB RULES_FILES etc/udev/rules.d/*.rules) - install(FILES ${RULES_FILES} DESTINATION ${STLINK_UDEV_RULES_DIR}/) - endif () + if (STLINK_INSTALL_MODPROBE_CONF) + install(FILES etc/modprobe.d/stlink_v1.conf DESTINATION ${STLINK_MODPROBED_DIR}/) + endif () + if (STLINK_INSTALL_UDEV_RULES) + file(GLOB RULES_FILES etc/udev/rules.d/*.rules) + install(FILES ${RULES_FILES} DESTINATION ${STLINK_UDEV_RULES_DIR}/) + endif () endif () add_subdirectory(src/gdbserver) add_subdirectory(src/tools/gui) + ### # Others ### + add_subdirectory(usr/lib/pkgconfig) add_subdirectory(include) add_subdirectory(doc/man) diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index dce8fbfa6..5b435c022 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -1,37 +1,32 @@ -set(MANPAGES - st-util - st-flash - st-info - ) +set(MANPAGES st-util st-flash st-info) # Only generate manpages with pandoc in Debug builds -if(${STLINK_GENERATE_MANPAGES}) - include(pandocology) - - foreach(manpage ${MANPAGES}) - add_document( - ${manpage}.1 - SOURCES ${manpage}.md - PANDOC_DIRECTIVES -s -t man - PRODUCT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - ) - endforeach() -else() - message(STATUS "Manpage generation disabled") -endif() +if (${STLINK_GENERATE_MANPAGES}) + include(pandocology) + foreach (manpage ${MANPAGES}) + add_document( + ${manpage}.1 + SOURCES ${manpage}.md + PANDOC_DIRECTIVES -s -t man + PRODUCT_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} + ) + endforeach () +else () + message(STATUS "Manpage generation disabled") +endif () # Install from output folder or this folder -foreach(manpage ${MANPAGES}) - if(EXISTS ${CMAKE_CURRENT_BINARY_DIR}/${manpage}.1) - set(f "${CMAKE_CURRENT_BINARY_DIR}/${manpage}.1") - elseif(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${manpage}.1") - set(f "${CMAKE_CURRENT_SOURCE_DIR}/${manpage}.1") - else() - message(AUTHOR_WARNING "Manpage ${manpage} not generated") - endif() +foreach (manpage ${MANPAGES}) + if (EXISTS ${CMAKE_CURRENT_BINARY_DIR}/${manpage}.1) + set(f "${CMAKE_CURRENT_BINARY_DIR}/${manpage}.1") + elseif (EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${manpage}.1") + set(f "${CMAKE_CURRENT_SOURCE_DIR}/${manpage}.1") + else() + message(AUTHOR_WARNING "Manpage ${manpage} not generated") + endif() - if (f AND NOT WIN32) - install(FILES ${f} DESTINATION ${CMAKE_INSTALL_PREFIX}/share/man/man1) - unset(f) - endif() -endforeach() + if (f AND NOT WIN32) + install(FILES ${f} DESTINATION ${CMAKE_INSTALL_PREFIX}/share/man/man1) + unset(f) + endif () +endforeach () diff --git a/include/CMakeLists.txt b/include/CMakeLists.txt index 94df89958..6e5e3c279 100644 --- a/include/CMakeLists.txt +++ b/include/CMakeLists.txt @@ -1,6 +1,6 @@ configure_file( - "${PROJECT_SOURCE_DIR}/include/stlink/version.h.in" - "${CMAKE_BINARY_DIR}/include/stlink/version.h" + "${PROJECT_SOURCE_DIR}/include/stlink/version.h.in" + "${CMAKE_BINARY_DIR}/include/stlink/version.h" ) file(GLOB STLINK_HEADERS "stlink/*.h" "${CMAKE_BINARY_DIR}/include/stlink/*.h") install(FILES ${CMAKE_SOURCE_DIR}/include/stlink.h DESTINATION ${STLINK_INCLUDE_PATH}) diff --git a/src/gdbserver/CMakeLists.txt b/src/gdbserver/CMakeLists.txt index 5fb0c1ab8..ff9bde165 100644 --- a/src/gdbserver/CMakeLists.txt +++ b/src/gdbserver/CMakeLists.txt @@ -10,14 +10,14 @@ set(STUTIL_SOURCE if (MSVC) # We need a getopt from somewhere... set(STUTIL_SOURCE "${STUTIL_SOURCE};../getopt/getopt.c") -endif() +endif () add_executable(st-util ${STUTIL_SOURCE}) if (WIN32 OR APPLE) target_link_libraries(st-util ${STLINK_LIB_STATIC} ${SSP_LIB}) -else() +else () target_link_libraries(st-util ${STLINK_LIB_SHARED} ${SSP_LIB}) -endif() +endif () install(TARGETS st-util RUNTIME DESTINATION bin) diff --git a/src/tools/gui/CMakeLists.txt b/src/tools/gui/CMakeLists.txt index 850f483a9..d7add834b 100644 --- a/src/tools/gui/CMakeLists.txt +++ b/src/tools/gui/CMakeLists.txt @@ -1,7 +1,7 @@ if (NOT gtk_FOUND) message(STATUS "gtk not found!") - return() -endif() + return() +endif () set(GUI_SOURCES stlink-gui.c stlink-gui.h) set(INSTALLED_UI_DIR share/stlink) @@ -12,7 +12,7 @@ add_executable(stlink-gui-local ${GUI_SOURCES}) set_target_properties( stlink-gui-local PROPERTIES COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_CURRENT_SOURCE_DIR}" - ) + ) target_link_libraries(stlink-gui-local ${STLINK_LIB_STATIC} ${gtk_LDFLAGS} ${SSP_LIB}) @@ -20,7 +20,7 @@ add_executable(stlink-gui ${GUI_SOURCES}) set_target_properties( stlink-gui PROPERTIES COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/${INSTALLED_UI_DIR}" - ) + ) target_link_libraries(stlink-gui ${STLINK_LIB_STATIC} ${gtk_LDFLAGS} ${SSP_LIB}) install(TARGETS stlink-gui RUNTIME DESTINATION bin) @@ -31,4 +31,4 @@ if (${CMAKE_SYSTEM_NAME} MATCHES "Linux") install(FILES stlink-gui.desktop DESTINATION share/applications) # Install icon install(FILES art/stlink-gui.svg DESTINATION share/icons/hicolor/scalable/apps) -endif (${CMAKE_SYSTEM_NAME} MATCHES "Linux") +endif () diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index e8ec5fec0..c6b04ddb3 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -1,14 +1,11 @@ -set(TESTS - usb - sg - ) +set(TESTS usb sg) -foreach(test ${TESTS}) - add_executable(${test} ${test}.c) - add_dependencies(${test} ${STLINK_LIB_STATIC}) +foreach (test ${TESTS}) + add_executable(${test} ${test}.c) + add_dependencies(${test} ${STLINK_LIB_STATIC}) target_link_libraries(${test} ${STLINK_LIB_STATIC} ${SSP_LIB}) - add_test(${test} ${CMAKE_CURRENT_BINARY_DIR}/${test}) -endforeach() + add_test(${test} ${CMAKE_CURRENT_BINARY_DIR}/${test}) +endforeach () add_executable(flash flash.c "${CMAKE_SOURCE_DIR}/src/tools/flash_opts.c") target_link_libraries(flash ${STLINK_LIB_STATIC} ${SSP_LIB}) diff --git a/usr/lib/pkgconfig/CMakeLists.txt b/usr/lib/pkgconfig/CMakeLists.txt index 5a8227125..02e80cb72 100644 --- a/usr/lib/pkgconfig/CMakeLists.txt +++ b/usr/lib/pkgconfig/CMakeLists.txt @@ -5,11 +5,11 @@ set(PKG_CONFIG_CFLAGS "-I\${includedir}") set(PKG_CONFIG_REQUIRES "libusb-1.0") configure_file( - "${CMAKE_CURRENT_SOURCE_DIR}/pkg-config.pc.cmake" - "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" + "${CMAKE_CURRENT_SOURCE_DIR}/pkg-config.pc.cmake" + "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" ) install( FILES "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" - DESTINATION ${STLINK_LIBRARY_PATH}/pkgconfig/ + DESTINATION ${STLINK_LIBRARY_PATH}/pkgconfig/ ) From e7ed76bd12ab6cb022b4c011fa706eae69ad77f8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 5 Apr 2020 18:01:49 +0200 Subject: [PATCH 0771/1435] Added cmake uninstall target (Fixes #619) --- CMakeLists.txt | 15 +++++++++++++++ cmake_uninstall.cmake.in | 21 +++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 cmake_uninstall.cmake.in diff --git a/CMakeLists.txt b/CMakeLists.txt index 5d5dab72e..df5033f7e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -245,3 +245,18 @@ add_subdirectory(tests) include(cmake/cpack_config.cmake) include(CPack) + + +### +# Uninstall target +### + +if (NOT TARGET uninstall) + configure_file( + "${CMAKE_CURRENT_SOURCE_DIR}/cmake_uninstall.cmake.in" + "${CMAKE_CURRENT_BINARY_DIR}/cmake_uninstall.cmake" + IMMEDIATE @ONLY + ) + add_custom_target(uninstall + COMMAND ${CMAKE_COMMAND} -P ${CMAKE_CURRENT_BINARY_DIR}/cmake_uninstall.cmake) +endif () diff --git a/cmake_uninstall.cmake.in b/cmake_uninstall.cmake.in new file mode 100644 index 000000000..ed17c45cd --- /dev/null +++ b/cmake_uninstall.cmake.in @@ -0,0 +1,21 @@ +if(NOT EXISTS "@CMAKE_BINARY_DIR@/install_manifest.txt") + message(FATAL_ERROR "Cannot find install manifest: @CMAKE_BINARY_DIR@/install_manifest.txt") +endif() + +file(READ "@CMAKE_BINARY_DIR@/install_manifest.txt" files) +string(REGEX REPLACE "\n" ";" files "${files}") +foreach (file ${files}) + message(STATUS "Uninstalling $ENV{DESTDIR}${file}") + if (IS_SYMLINK "$ENV{DESTDIR}${file}" OR EXISTS "$ENV{DESTDIR}${file}") + exec_program("@CMAKE_COMMAND@" + ARGS "-E remove \"$ENV{DESTDIR}${file}\"" + OUTPUT_VARIABLE rm_out + RETURN_VALUE rm_retval + ) + if (NOT "${rm_retval}" STREQUAL 0) + message(FATAL_ERROR "Problem when removing $ENV{DESTDIR}${file}") + endif () + else (IS_SYMLINK "$ENV{DESTDIR}${file}" OR EXISTS "$ENV{DESTDIR}${file}") + message(STATUS "File $ENV{DESTDIR}${file} does not exist.") + endif () +endforeach () From 41f8417eaa196a7f8247b52f604bf8eb946e5f30 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 5 Apr 2020 18:12:39 +0200 Subject: [PATCH 0772/1435] Integrated module GNUInstallDirs.cmake (Fixes #557) --- CMakeLists.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index df5033f7e..f46a5f591 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -3,8 +3,9 @@ set(CMAKE_USER_MAKE_RULES_OVERRIDE cmake/c_flag_overrides.cmake) project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics ST-LINK Tools") -set(STLINK_UDEV_RULES_DIR "/etc/udev/rules.d" CACHE PATH "Udev rules directory") -set(STLINK_MODPROBED_DIR "/etc/modprobe.d" CACHE PATH "modprobe.d directory") +include(GNUInstallDirs) +set(STLINK_UDEV_RULES_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/udev/rules.d" CACHE PATH "Udev rules directory") +set(STLINK_MODPROBED_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/modprobe.d" CACHE PATH "modprobe.d directory") set(STLINK_STATIC_LIB ON CACHE BOOL "Install static lib") set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) From 7158df1de436ba7bec96181bc853e685ca27062a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 5 Apr 2020 22:02:47 +0200 Subject: [PATCH 0773/1435] Update for CHANGELOG.md & minor fixes --- CHANGELOG.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index d88d83098..c33bcbb47 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -72,7 +72,7 @@ Major changes and added features: Updates and fixes: -* Fixed missing flash_loader for STM32L011 ([#654](https://github.com/texane/stlink/pull/654), [#675](https://github.com/texane/stlink/pull/675)) +* Fixed missing flash_loader for STM32L0x ([#269](https://github.com/texane/stlink/pull/269), [#274](https://github.com/texane/stlink/pull/274), [#654](https://github.com/texane/stlink/pull/654), [#675](https://github.com/texane/stlink/pull/675)) * Fix for stlink library calls exit() or _exit() ([#634](https://github.com/texane/stlink/pull/634), [#696](https://github.com/texane/stlink/pull/696)) * Added semihosting parameter documentation in doc/man ([#674](https://github.com/texane/stlink/pull/674)) * Fixed reference to non-exisiting st-term tool in doc/man ([#676](https://github.com/texane/stlink/pull/676)) @@ -128,11 +128,11 @@ Major changes and added features: Updates and fixes: * Fixed gdb-server: STM32L0xx has no FP_CTRL register for breakpoints ([#273](https://github.com/texane/stlink/pull/273)) +* Added --flash=n[k][m] command line option to override device model ([#305](https://github.com/texane/stlink/pull/305), [#516](https://github.com/texane/stlink/pull/516), [#576](https://github.com/texane/stlink/pull/576)) * Updated libusb to 1.0.21 for Windows ([#562](https://github.com/texane/stlink/pull/562)) * Fixed low-voltage flashing on STM32F7 devices ([#566](https://github.com/texane/stlink/pull/566), [#567](https://github.com/texane/stlink/pull/567)) * Fixed building with mingw64 ([#569](https://github.com/texane/stlink/pull/569), [#573](https://github.com/texane/stlink/pull/573), [#578](https://github.com/texane/stlink/pull/578), [#584](https://github.com/texane/stlink/pull/584), [#610](https://github.com/texane/stlink/pull/610)) * Fixed possible memory leak ([#570](https://github.com/texane/stlink/pull/570), [#571](https://github.com/texane/stlink/pull/571)) -* Added --flash=n[k][m] command line option to override device model ([#576](https://github.com/texane/stlink/pull/576)) * Fixed installation path for shared objects ([#581](https://github.com/texane/stlink/pull/581)) * Fixed a few -Wformat warnings ([#582](https://github.com/texane/stlink/pull/582)) * Removed unused defines in mimgw.h ([#583](https://github.com/texane/stlink/pull/583)) @@ -150,7 +150,7 @@ Release date: 2017-02-25 Major changes and added features: * Added support for Semihosting `SYS_READC` ([#546](https://github.com/texane/stlink/pull/546)) -* Added support for STM32F413 ([#549](https://github.com/texane/stlink/pull/549), [#550](https://github.com/texane/stlink/pull/550)) +* Added support for STM32F413 ([#549](https://github.com/texane/stlink/pull/549), [#550](https://github.com/texane/stlink/pull/550), [#758](https://github.com/texane/stlink/pull/758)) * Added preliminary support for STM32L011 to see it after probe (chip-ID 0x457) ([#558](https://github.com/texane/stlink/pull/558), [#598](https://github.com/texane/stlink/pull/598)) Updates and fixes: From e9c8135675d701198f2df22e50bc3062242fcb09 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Mon, 6 Apr 2020 19:20:04 +0800 Subject: [PATCH 0774/1435] Fix int length issues --- src/common.c | 11 +++++++++-- src/usb.c | 2 +- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/common.c b/src/common.c index 6226c893b..ffc6057bb 100644 --- a/src/common.c +++ b/src/common.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include @@ -1257,8 +1258,14 @@ static int map_file(mapped_file_t* mf, const char* path) { fprintf(stderr, "fstat() == -1\n"); goto on_error; } - - mf->base = (uint8_t*) mmap(NULL, st.st_size, PROT_READ, MAP_SHARED, fd, 0); + if (sizeof(st.st_size) != sizeof(size_t)) { + /* On 32 bit systems, check if there is an overflow */ + if (st.st_size > (off_t)UINT32_MAX) { + fprintf(stderr, "mmap() size_t overflow\n"); + goto on_error; + } + } + mf->base = (uint8_t*) mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); if (mf->base == MAP_FAILED) { fprintf(stderr, "mmap() == MAP_FAILED\n"); goto on_error; diff --git a/src/usb.c b/src/usb.c index 9df9d7296..81bd7ae2c 100644 --- a/src/usb.c +++ b/src/usb.c @@ -189,7 +189,7 @@ int _stlink_usb_version(stlink_t *sl) { cmd[i++] = STLINK_APIV3_GET_VERSION_EX; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); - if (size != rep_len) { + if (size != (ssize_t)rep_len) { printf("[!] send_recv STLINK_APIV3_GET_VERSION_EX\n"); return (int) size; } From 46bf0abf77cca47133d3839460cc7679e0f78714 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 3 Apr 2020 16:13:35 +0200 Subject: [PATCH 0775/1435] add dual bank flash configuration info to chipid database. add a 'has_dual_bank' info to flash param, helping handling a couple of cases - selecting over dual bank specific code path without handling multiple chip id all over the code. - handling dual bank mode dynamic configuration --- include/stlink.h | 2 ++ include/stlink/chipid.h | 1 + src/common.c | 2 ++ 3 files changed, 5 insertions(+) diff --git a/include/stlink.h b/include/stlink.h index a69e357b5..ba7ef6196 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -159,6 +159,8 @@ typedef struct flash_loader { int serial_size; enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx + bool has_dual_bank; + stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() size_t flash_size; // calculated by stlink_load_device_params() size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 8895cd4f8..d23596c0d 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -73,6 +73,7 @@ struct stlink_chipid_params { uint32_t chip_id; char *description; enum stlink_flash_type flash_type; + bool has_dual_bank; uint32_t flash_size_reg; uint32_t flash_pagesize; uint32_t sram_size; diff --git a/src/common.c b/src/common.c index b6496c00c..5ccfcf0bb 100644 --- a/src/common.c +++ b/src/common.c @@ -885,7 +885,9 @@ int stlink_load_device_params(stlink_t *sl) { } else { sl->flash_size = flash_size * 1024; } + sl->flash_type = params->flash_type; + sl->has_dual_bank = params->has_dual_bank; sl->flash_pgsz = params->flash_pagesize; sl->sram_size = params->sram_size; sl->sys_base = params->bootrom_base; From 804c38ead8aef3e4a1640a82a9b9c01f4f60eed1 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 6 Apr 2020 11:18:09 +0200 Subject: [PATCH 0776/1435] stm32g4: read flash optr to get flash bank mode on cat3 devices. g4 cat3 devices can be configured in two mode via option bytes: - dual bank, 2x256kib, 2KiB pages. - single bank, 1x512KiB, 4KiB pages. in anycase, these have two banks, and need to be handled with more care. -> read optr after loading flash params to patch page size. -> in single bank mode, mass erase _must_ be triggered by applying MER1 and MER2 bits. erasing half of the flash will lead to a pgserr. --- src/chipid.c | 1 + src/common.c | 12 ++++++++++++ 2 files changed, 13 insertions(+) diff --git a/src/chipid.c b/src/chipid.c index 426780cf7..b9d3933f0 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -562,6 +562,7 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_G4_CAT3, .description = "G4 Category-3", .flash_type = STLINK_FLASH_TYPE_G4, + .has_dual_bank = true, .flash_size_reg = 0x1FFF75E0, // Section 47.2 .flash_pagesize = 0x800, // 2K (sec 3.3.1) // SRAM1 is 80k at 0x20000000 diff --git a/src/common.c b/src/common.c index 5ccfcf0bb..8cfbece35 100644 --- a/src/common.c +++ b/src/common.c @@ -128,9 +128,13 @@ #define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ #define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ #define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ + // G0/G4 FLASH status register #define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ +// G4 FLASH option register +#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ + // WB (RM0434) #define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) #define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) @@ -899,6 +903,14 @@ int stlink_load_device_params(stlink_t *sl) { sl->sram_size = 0x1000; } + if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { + uint32_t flash_optr; + stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); + if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { + sl->flash_pgsz <<= 1; + } + } + #if 0 // Old code -- REW ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); From 55ca316cd61a959746d809e1d9b20fa485ec39d8 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 6 Apr 2020 11:09:26 +0200 Subject: [PATCH 0777/1435] stm32g4: handle mass erase. toggle proper MER bits, taking in account dual bank mode enabled or not. --- src/common.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 8cfbece35..b1461c419 100644 --- a/src/common.c +++ b/src/common.c @@ -120,6 +120,7 @@ #define STM32Gx_FLASH_CR_PNB (3) /* Page number */ #define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ #define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ #define STM32Gx_FLASH_CR_STRT (16) /* Start */ #define STM32Gx_FLASH_CR_OPTSTRT (17) /* Start of modification of option bytes */ #define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ @@ -519,7 +520,10 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - cr_mer = (1 << FLASH_CR_MER); + cr_mer = (1 << STM32Gx_FLASH_CR_MER1); + if (sl->has_dual_bank) { + cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); + } cr_pg = (1 << FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; From 6a2bf1cbe21cf3409926c24f360210ba14d469ff Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 3 Apr 2020 14:50:55 +0200 Subject: [PATCH 0778/1435] stm32g4: allow mass erase. --- src/common.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/common.c b/src/common.c index b1461c419..601660360 100644 --- a/src/common.c +++ b/src/common.c @@ -1980,7 +1980,6 @@ int stlink_erase_flash_mass(stlink_t *sl) { /* TODO: User MER bit to mass-erase G0, G4, WB series. */ if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4 || sl->flash_type == STLINK_FLASH_TYPE_WB) { /* erase each page */ int i = 0, num_pages = (int) sl->flash_size/sl->flash_pgsz; From 98cd484854b8842452759f8752dea5ca2e98c6ea Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 6 Apr 2020 14:00:54 +0200 Subject: [PATCH 0779/1435] common: add flash error check. use it for mass erase. only implement it for g0/g4 for now, but this is most probably a must for all chips. --- src/common.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/common.c b/src/common.c index 601660360..fd73c1614 100644 --- a/src/common.c +++ b/src/common.c @@ -131,7 +131,9 @@ #define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ // G0/G4 FLASH status register +#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) #define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ +#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ // G4 FLASH option register #define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ @@ -688,6 +690,22 @@ static void wait_flash_busy_progress(stlink_t *sl) { fprintf(stdout, "\n"); } +static int check_flash_error(stlink_t *sl) +{ + uint32_t res = 0; + if ((sl->flash_type == STLINK_FLASH_TYPE_G0) || + (sl->flash_type == STLINK_FLASH_TYPE_G4)) { + res = read_flash_sr(sl) & STM32Gx_FLASH_SR_ERROR_MASK; + } + + if (res) { + ELOG("Flash programming error : %#010x\n", res); + return -1; + } + + return 0; +} + static inline unsigned int is_flash_eop(stlink_t *sl) { return read_flash_sr(sl) & (1 << FLASH_SR_EOP); } @@ -2018,6 +2036,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { /* wait for completion */ wait_flash_busy_progress(sl); + check_flash_error(sl); + /* relock the flash */ lock_flash(sl); From 4437314d3383798d4518fe169c7de9db9ac39dc5 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 6 Apr 2020 16:45:26 +0200 Subject: [PATCH 0780/1435] enable mass erase for g0, worksforme --- src/common.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/common.c b/src/common.c index fd73c1614..26202fcef 100644 --- a/src/common.c +++ b/src/common.c @@ -1997,7 +1997,6 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) int stlink_erase_flash_mass(stlink_t *sl) { /* TODO: User MER bit to mass-erase G0, G4, WB series. */ if (sl->flash_type == STLINK_FLASH_TYPE_L0 || - sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_WB) { /* erase each page */ int i = 0, num_pages = (int) sl->flash_size/sl->flash_pgsz; From be6aafddd1dc6eab29038b0010a582de060cfedd Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 7 Apr 2020 12:12:34 +0200 Subject: [PATCH 0781/1435] Minor fixes - Updated CentOS repo in README.md - Whitespace fixes --- Makefile | 47 +++++++++++++++++++++--------------------- README.md | 2 +- doc/version_support.md | 3 ++- 3 files changed, 26 insertions(+), 26 deletions(-) diff --git a/Makefile b/Makefile index 7f81488bb..a94ec598b 100644 --- a/Makefile +++ b/Makefile @@ -1,49 +1,48 @@ ## -# This Makefile is used to drive building of Debug and Release -# targets of CMake +# This Makefile is used to drive building of Debug and Release targets of CMake ## MAKEFLAGS += -s all: release -ci: debug release test +ci: debug release test help: - @echo " release: Run a release build" - @echo " debug: Run a debug build" - @echo " lint: Lint check all source-code" - @echo " test: Build and run tests" - @echo " clean: Clean all build output" - @echo "rebuild_cache: Rebuild all CMake caches" + @echo " release: Run a release build" + @echo " debug: Run a debug build" + @echo " lint: Lint check all source-code" + @echo " test: Build and run tests" + @echo " clean: Clean all build output" + @echo "rebuild_cache: Rebuild all CMake caches" rebuild_cache: build/Debug build/Release - @$(MAKE) -C build/Debug rebuild_cache - @$(MAKE) -C build/Release rebuild_cache + @$(MAKE) -C build/Debug rebuild_cache + @$(MAKE) -C build/Release rebuild_cache debug: build/Debug - @echo "[DEBUG]" - @$(MAKE) -C build/Debug + @echo "[DEBUG]" + @$(MAKE) -C build/Debug release: build/Release - @echo "[RELEASE]" - @$(MAKE) -C build/Release + @echo "[RELEASE]" + @$(MAKE) -C build/Release package: build/Release - @echo "[PACKAGE] Release" - @$(MAKE) -C build/Release package + @echo "[PACKAGE] Release" + @$(MAKE) -C build/Release package test: debug - @$(MAKE) -C build/Debug test + @$(MAKE) -C build/Debug test build/Debug: - @mkdir -p $@ - @cd $@ && cmake -DCMAKE_BUILD_TYPE=Debug $(CMAKEFLAGS) ../../ + @mkdir -p $@ + @cd $@ && cmake -DCMAKE_BUILD_TYPE=Debug $(CMAKEFLAGS) ../../ build/Release: - @mkdir -p $@ - @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Release $(CMAKEFLAGS) ../../ + @mkdir -p $@ + @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Release $(CMAKEFLAGS) ../../ clean: - @echo "[CLEAN]" - @rm -Rf build + @echo "[CLEAN]" + @rm -Rf build .PHONY: clean diff --git a/README.md b/README.md index b26a147e9..807449594 100644 --- a/README.md +++ b/README.md @@ -56,7 +56,7 @@ We recommend to install `stlink-tools` from the package repository of the used d **Other Operating Systems**: -* RedHat/CentOS 7: Users can install [from EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel7) +* RedHat/CentOS 8: Users can install [from EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel8) * FreeBSD: Users can install [from freshports](https://www.freshports.org/devel/stlink) * OpenBSD: Users need to install [from source](doc/compiling.md). diff --git a/doc/version_support.md b/doc/version_support.md index 963ca2988..5c8f65841 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -3,7 +3,6 @@ Sources: [pkgs.org - libusb](https://pkgs.org/search/?q=libusb) & [pkgs.org - cm ## Supported Operating Systems - ### Microsoft Windows On Windows users should ensure that cmake 3.17.0 is installed.
    @@ -14,6 +13,7 @@ Thus no user interaction regarding libusb is necessary. * Windows 10 * Windows 8.1 + ### Apple macOS On macOS users should ensure that cmake 3.17.0 is installed. @@ -24,6 +24,7 @@ On macOS users should ensure that cmake 3.17.0 is installed. * macOS 10.14 Mojave * macOS 10.13 High Sierra + ### Linux-/Unix-based: | Operating System | libusb
    version | cmake
    version | Notes | From a8c1f41f1b1c9dd1314f99a1d42de1008f5a4f74 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 7 Apr 2020 16:10:55 +0200 Subject: [PATCH 0782/1435] Refactoring for libusb detection --- cmake/modules/FindLibUSB.cmake | 219 ++++++++++++++++----------------- 1 file changed, 106 insertions(+), 113 deletions(-) diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index a8b65cba3..dc90bcc32 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -6,139 +6,132 @@ # LIBUSB_LIBRARY - The libraries needed to use libusb # LIBUSB_DEFINITIONS - Compiler switches required for using libusb +if (NOT (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD")) # all OS apart from FreeBSD + FIND_PATH( + LIBUSB_INCLUDE_DIR NAMES libusb.h + HINTS /usr /usr/local /opt + PATH_SUFFIXES libusb-1.0 + ) +endif () -if (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD - FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h - HINTS - /usr/include - ) -else () # other OS - FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h - HINTS - /usr - /usr/local - /opt - PATH_SUFFIXES libusb-1.0 - ) -endif() +if (APPLE) # macOS + set(LIBUSB_NAME libusb-1.0.a) + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS /usr /usr/local /opt + ) +elseif (MINGW OR MSYS) # Windows with MinGW or MSYS + set(LIBUSB_NAME usb-1.0) -# macOS -if (APPLE) - set(LIBUSB_NAME libusb-1.0.a) -elseif(MSYS OR MINGW) - set(LIBUSB_NAME usb-1.0) -elseif(MSVC) - set(LIBUSB_NAME libusb-1.0.lib) -elseif(CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") - set(LIBUSB_NAME usb) -else() - set(LIBUSB_NAME usb-1.0) -endif() + if (CMAKE_SIZEOF_VOID_P EQUAL 8) # 64-bit + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/static + NO_DEFAULT_PATH + NO_CMAKE_FIND_ROOT_PATH + ) + else () # 32-bit + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW32/static + NO_DEFAULT_PATH + NO_CMAKE_FIND_ROOT_PATH + ) + endif () -if (MSYS OR MINGW) - if (CMAKE_SIZEOF_VOID_P EQUAL 8) - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/static) - else () - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW32/static) - endif () -elseif (MSVC) - if (CMAKE_SIZEOF_VOID_P EQUAL 8) - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS64/dll) - else () - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS32/dll) - endif () -else() - find_library(LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS - /usr - /usr/local - /opt) -endif () +elseif (MSVC) # Windows with MSVC + set(LIBUSB_NAME libusb-1.0.lib) + if (CMAKE_SIZEOF_VOID_P EQUAL 8) # 64-bit + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS64/dll + NO_DEFAULT_PATH + NO_CMAKE_FIND_ROOT_PATH + ) + else () # 32-bit + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS32/dll + NO_DEFAULT_PATH + NO_CMAKE_FIND_ROOT_PATH + ) + endif () + +elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD + # libusb is integrated into FreeBSD + FIND_PATH( + LIBUSB_INCLUDE_DIR NAMES libusb.h + HINTS /usr/include + ) + + set(LIBUSB_NAME usb) + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS /usr /usr/local /opt + ) + +else () # all other OS + set(LIBUSB_NAME usb-1.0) + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS /usr /usr/local /opt + ) +endif() include(FindPackageHandleStandardArgs) FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) - mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) -if(NOT LIBUSB_FOUND) - if(WIN32 OR MSVC OR MINGW OR MSYS) - find_package(7Zip REQUIRED) +if (NOT LIBUSB_FOUND) + if (WIN32 OR MINGW OR MSYS OR MSVC) # Windows - set(LIBUSB_WIN_VERSION 1.0.23) + # Preparations for installing libusb library + find_package(7Zip REQUIRED) + set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version to 1.0.23 (latest as of Apr 2020) set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/3rdparty/libusb-${LIBUSB_WIN_VERSION}) - if(EXISTS ${LIBUSB_WIN_ARCHIVE_PATH}) + # Get libusb package + if (EXISTS ${LIBUSB_WIN_ARCHIVE_PATH}) # ... should the package be already there (for whatever reason) message(STATUS "libusb archive already in build folder") - else() + else () # ... download the package (1.0.23 as of Apr 2020) message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download - ${LIBUSB_WIN_ARCHIVE_PATH} - EXPECTED_MD5 cf3d38d2ff053ef343d10c0b8b0950c2 - ) - endif() + ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 cf3d38d2ff053ef343d10c0b8b0950c2 + ) + endif () + file(MAKE_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) - if(${ZIP_EXECUTABLE} MATCHES "p7zip") - #execute_process(COMMAND ${ZIP_EXECUTABLE} -d --keep -f ${LIBUSB_WIN_ARCHIVE_PATH} WORKING_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) - execute_process(COMMAND ${ZIP_EXECUTABLE} -d ${LIBUSB_WIN_ARCHIVE_PATH} WORKING_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) - else() - execute_process(COMMAND ${ZIP_EXECUTABLE} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o${LIBUSB_WIN_OUTPUT_FOLDER}) - endif() + # Extract libusb package + if (${ZIP_EXECUTABLE} MATCHES "p7zip") + execute_process( + COMMAND ${ZIP_EXECUTABLE} -d ${LIBUSB_WIN_ARCHIVE_PATH} + WORKING_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER} + ) + else () + execute_process( + COMMAND ${ZIP_EXECUTABLE} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o ${LIBUSB_WIN_OUTPUT_FOLDER} + ) + endif () - FIND_PATH(LIBUSB_INCLUDE_DIR NAMES libusb.h - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/include - PATH_SUFFIXES libusb-1.0 - NO_DEFAULT_PATH - NO_CMAKE_FIND_ROOT_PATH - ) + # Find path to libusb library + FIND_PATH( + LIBUSB_INCLUDE_DIR NAMES libusb.h + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/include + PATH_SUFFIXES libusb-1.0 + NO_DEFAULT_PATH + NO_CMAKE_FIND_ROOT_PATH + ) - if (MSYS OR MINGW) - if (CMAKE_SIZEOF_VOID_P EQUAL 8) - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/static - NO_DEFAULT_PATH - NO_CMAKE_FIND_ROOT_PATH - ) - else () - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW32/static - NO_DEFAULT_PATH - NO_CMAKE_FIND_ROOT_PATH - ) - endif () - elseif(MSVC) - if (CMAKE_SIZEOF_VOID_P EQUAL 8) - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS64/dll - NO_DEFAULT_PATH - NO_CMAKE_FIND_ROOT_PATH - ) - else () - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS32/dll - NO_DEFAULT_PATH - NO_CMAKE_FIND_ROOT_PATH - ) - endif () - endif () FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) - endif() -else() - message(STATUS "found USB") -endif() + message(STATUS "installed libusb library") + else () # all other OS + message(FATAL_ERROR "libusb library not found on your system! Compilation terminated.") + endif () +else (NOT LIBUSB_FOUND) + message(STATUS "found libusb library") +endif () From 23c071edea45f6e8852fef52d884a680973d6d8f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 7 Apr 2020 17:01:26 +0200 Subject: [PATCH 0783/1435] Updated documentation - Compiling manual - Updated version support for macOS --- README.md | 21 +++++++++++----- doc/compiling.md | 57 +++++++++++++++++++++--------------------- doc/version_support.md | 11 +++----- 3 files changed, 47 insertions(+), 42 deletions(-) diff --git a/README.md b/README.md index 807449594..343dbd39c 100644 --- a/README.md +++ b/README.md @@ -37,11 +37,20 @@ Currently known working combinations of programmers and targets are listed in [d ## Installation -**Windows**: download [v1.6.0](https://github.com/texane/stlink/releases/tag/v1.6.0) from the releases page. +**Windows**: -Windows pre-compiled binaries are available at http://www.emb4fun.de/archive/stlink/index.html (outdated, not recommended for use) +Please compile and install from source as described in our [compiling manual](doc/compiling.md#Windows). -**macOS**: install [from homebrew](http://brewformulas.org/Stlink) or download [v1.6.0](https://github.com/texane/stlink/releases/tag/v1.6.0) from the releases page. +Long awaited binaries will be available soon... + +**macOS**: + +We recommend to install from: + +* [homebrew](https://formulae.brew.sh/formula/stlink) or +* [MacPorts](https://ports.macports.org/port/stlink) + +Alternatively one can compile and install from source as described in our [compiling manual](doc/compiling.md#macOS). **Linux**: @@ -56,9 +65,9 @@ We recommend to install `stlink-tools` from the package repository of the used d **Other Operating Systems**: -* RedHat/CentOS 8: Users can install [from EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel8) -* FreeBSD: Users can install [from freshports](https://www.freshports.org/devel/stlink) -* OpenBSD: Users need to install [from source](doc/compiling.md). +* RedHat/CentOS 8: Users can install from [EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel8) +* FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) +* OpenBSD: Users need to compile and install from source as described in our [compiling manual](doc/compiling.md). ## Installation from source (advanced users) diff --git a/doc/compiling.md b/doc/compiling.md index bcaf7d567..64f4de466 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -28,7 +28,7 @@ On Windows users should ensure that the following software is installed: ### Building -#### MinGW64 +#### MinGW-w64 1. Use the command-line to move to the `scripts` directory within the source-folder: `cd stlink\scripts\` 2. Execute `./mingw64-build.bat` @@ -158,47 +158,46 @@ Choose on of the following options _before_ connecting the device to your comput 2. `modprobe -r usb-storage && modprobe usb-storage` -Author: nightwalker-87 +## macOS +### Common requirements ------ +The best way is to install a package manager for open source software, +either [homebrew](https://brew.sh) or [MacPorts](https://www.macports.org/). ----- **The following content is outdated and unrevised!** ---- +Then install the following dependencies from the package repository: -## Mac OS X +* `git` +* `cmake` +* `libusb` -When compiling on a mac you need the following: +To do this with only one simple command, type: -* A compiler toolchain (XCode) -* CMake -* Libusb 1.0 +* for homebrew: `sudo brew install git cmake libusb` or +* for MacPorts:`sudo port install git cmake libusb` -The best way is to install [homebrew](http://brew.sh) which is a package manager - for opensource software which is missing from the Apple App Store. Then install - the dependencies: +Additionally we recommend to install Xcode which delivers the necessary C-compiler toolchain Clang (LLVM). -``` -brew install libusb cmake -``` -Compile as described in the first section of this document. +### Installation + +1. Open a new terminal window +2. Create a new destination folder at a place of your choice e.g. at `~/git`: `mkdir $HOME/git` +3. Change to this directory: `cd ~/git` +4. Fetch the project sourcefiles by running `git clone https://github.com/texane/stlink.git` -## Build using different directories for udev and modprobe +### Building -To put the udev or the modprobe configuration files into a different directory -during installation you can use the following cmake options: +1. Change into the project source directory: `cd stlink` +2. Run `make release` to create the _Release_ target +3. Run `make debug` to create the _Debug_ target (_optional_)
    + The debug target is only necessary in order to modify the sources and to run under a debugger. -``` -$ cmake -DSTLINK_UDEV_RULES_DIR="/usr/lib/udev/rules.d" \ - -DSTLINK_MODPROBED_DIR="/usr/lib/modprobe.d" .. -``` +## Build using a different directory for shared libs -## Build using different directory for shared libs +To put the compiled shared libs into a different directory during installation, +you can use the cmake option `cmake -DLIB_INSTALL_DIR:PATH="/usr/lib64" ..`. -To put the compiled shared libs into a different directory during installation -you can use the following cmake option: -``` -$ cmake -DLIB_INSTALL_DIR:PATH="/usr/lib64" .. -``` +Author: nightwalker-87 diff --git a/doc/version_support.md b/doc/version_support.md index 5c8f65841..8b1a9b92d 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -16,13 +16,10 @@ Thus no user interaction regarding libusb is necessary. ### Apple macOS -On macOS users should ensure that cmake 3.17.0 is installed. - ---> libusb Installation routine: (TBD) Work in progress... - -* macOS 10.15 Catalina -* macOS 10.14 Mojave -* macOS 10.13 High Sierra +| Package Repository | libusb
    version | cmake
    version | Supported macOS versions | +| --- | --- | --- | --- | +| homebrew | 1.0.23 | 3.17.0 | 10.12 (Sierra)- 10.15 (Catalina) | +| MacPorts | 1.0.23 | 3.17.0 | 10.6 (Snow Leopard) - 10.15 (Catalina) | ### Linux-/Unix-based: From af1570ffe971752e25dbe0d6bfcb59ff1bc46391 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 7 Apr 2020 17:11:45 +0200 Subject: [PATCH 0784/1435] Minor formatting fixes --- CMakeLists.txt | 2 +- cmake/version.cmake | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index f46a5f591..1f0b46449 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,7 +4,7 @@ set(CMAKE_USER_MAKE_RULES_OVERRIDE cmake/c_flag_overrides.cmake) project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics ST-LINK Tools") include(GNUInstallDirs) -set(STLINK_UDEV_RULES_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/udev/rules.d" CACHE PATH "Udev rules directory") +set(STLINK_UDEV_RULES_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/udev/rules.d" CACHE PATH "udev rules directory") set(STLINK_MODPROBED_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/modprobe.d" CACHE PATH "modprobe.d directory") set(STLINK_STATIC_LIB ON CACHE BOOL "Install static lib") diff --git a/cmake/version.cmake b/cmake/version.cmake index bdfe95ace..e9e2f7a05 100644 --- a/cmake/version.cmake +++ b/cmake/version.cmake @@ -4,7 +4,7 @@ set(__detect_version 0) -find_package (Git) +find_package(Git) if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") # Working off a git repo, using git versioning From 59c5cfd7ec5c7f2a035944ecc5ca01d3d7b31170 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 7 Apr 2020 18:30:26 +0200 Subject: [PATCH 0785/1435] [doc] macOS ST-Link-v1 detection Added documentation on how to solve a failed detection of the ST-Link-v1 programmer in macOS v10.11 and later. (Closes #574, #587) --- doc/tutorial.md | 64 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/doc/tutorial.md b/doc/tutorial.md index 1d48eaa38..9c1f7f26d 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -13,6 +13,70 @@ This option accepts decimal (128k), octal 0200k, or hex 0x80k. Obviously leaving the multiplier out is equally valid, for example: `--flash=0x20000`. The size may be followed by an optional "k" or "m" to multiply the given value by 1k (1024) or 1M respectively. + +## Solution to common problems +### ST-Link-v1 driver: Issue with Kernel Extension (kext) (macOS 10.11 and later only) +#### Problem: + +st-util fails to detect a ST-Link-v1 device: + +``` +st-util -1 +st-util $VERSION-STRING$ +WARN src/sg.c: Failed to find an stlink v1 by VID:PID +ERROR src/sg.c: Could not open stlink device +``` + +#### Solution (clean setup): + +1) Configure System Integrity Protection (SIP) + +The root of this problem is a system security setting introduced by Apple with OS X El Capitan (10.11) in 2015. +The so called System Integrity Protection (SIP) is active per default +and prevents the operating system amongst other things to load unsigned Kernel Extension Modules (kext). +Thus the ST-Link-v1 driver supplied with the tools, which installs as a kext, remains not functional, +while SIP is fully activated (as is per default). + +Action needs to be taken here by booting into the recovery mode where a terminal console window needs to be opened. + +Here it is **NOT RECOMMEND to disable SIP completely as with the command** `csrutil disable`, +**because this leaves the system more vulnerable to common threats. +Instead there is a more adequate and reasonable option implemented by Apple. +Running** `csrutil enable --without kext`, **allows to load unsigned kernel extensions +while leaving SIP active with all other security features.** +So who ever intends to run the ST-Link-v1 programmer on macOS please take this into account. + +Further details can be found here: https://forums.developer.apple.com/thread/17452 + +2) Install the ST-Link-v1 driver from the subdirectory `/stlinkv1_macosx_driver` + by referring to the instructions in the README file available there. + +3) Move the $OS_VERSION$.kext file to `/System/Library/Extensions`. + +4) Load the Kernel Extension (kext): `$ sudo kextload -v /System/Library/Extensions/stlink_shield10_x.kext` + +``` +Requesting load of /System/Library/Extensions/stlink_shield10_x.kext. +/System/Library/Extensions/stlink_shield10_x.kext loaded successfully (or already loaded). +``` + +5) Enter the command `$ sudo touch /System/Library/Extensions` + + +7) Verify correct detection of the ST-Link-v1 device with the following input: `st-util -1` + +You should then see a similar output like in this example: + +``` +INFO common.c: Loading device parameters.... +INFO common.c: Device connected is: F1 High-density device, id 0x10036414 +INFO common.c: SRAM size: 0x10000 bytes (64 KiB), Flash: 0x80000 bytes (512 KiB) in pages of 2048 bytes +INFO sg.c: Successfully opened a stlink v1 debugger +INFO gdb-server.c: Chip ID is 00000414, Core ID is 1ba01477. +INFO gdb-server.c: Listening at *:4242... +``` + + ------ Using STM32 discovery kits with open source tools From 97484422008df0f75c978627054776f35842a075 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 8 Apr 2020 00:12:36 +0200 Subject: [PATCH 0786/1435] Deprecated old appveyor-mingw script --- scripts/appveyor-mingw.sh | 21 --------------------- 1 file changed, 21 deletions(-) delete mode 100644 scripts/appveyor-mingw.sh diff --git a/scripts/appveyor-mingw.sh b/scripts/appveyor-mingw.sh deleted file mode 100644 index 4842410ba..000000000 --- a/scripts/appveyor-mingw.sh +++ /dev/null @@ -1,21 +0,0 @@ -#!/bin/sh -set -e -cd `dirname "$0"`/.. -if [ "$ARCH" = "i686" ]; then - f=i686-4.9.2-release-win32-sjlj-rt_v3-rev1.7z - if ! [ -e $f ]; then - curl -LsSO http://sourceforge.net/projects/mingw-w64/files/Toolchains%20targetting%20Win32/Personal%20Builds/mingw-builds/4.9.2/threads-win32/sjlj/$f - fi - 7z x $f > /dev/null - mv mingw32 /MinGW -else - f=x86_64-4.9.2-release-win32-seh-rt_v3-rev1.7z - if ! [ -e $f ]; then - curl -LsSO http://sourceforge.net/projects/mingw-w64/files/Toolchains%20targetting%20Win64/Personal%20Builds/mingw-builds/4.9.2/threads-win32/seh/$f - fi - 7z x $f > /dev/null - mv mingw64 /MinGW -fi -cd build -cmake .. -G"$GENERATOR" -cmake --build . --config RelWithDebInfo From 17511a6fed8f012e86acebb925ea1977c4798381 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 8 Apr 2020 01:58:59 +0200 Subject: [PATCH 0787/1435] Update for CHANGELOG.md --- CHANGELOG.md | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index c33bcbb47..1401843a9 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -26,6 +26,8 @@ Major changes and added features: Updates and fixes: +* Fixed "unkown chip id", piped output and st-util -v ([#107](https://github.com/texane/stlink/pull/107), [#665](https://github.com/texane/stlink/pull/665), [#763](https://github.com/texane/stlink/pull/763)) +* Fixed an issue with versioning stuck at 1.4.0 for versions cloned with git ([#563](https://github.com/texane/stlink/pull/563), [#762](https://github.com/texane/stlink/pull/762), [#772](https://github.com/texane/stlink/pull/772)) * Updated STM32F3xx chip ID that covers a few different devices ([#685](https://github.com/texane/stlink/pull/685), [#758](https://github.com/texane/stlink/pull/758)) * Made udev rules and modprobe conf installation optional ([#741](https://github.com/texane/stlink/pull/741)) * Fixed case when __FILE__ don't contain "/" nor "\\" ([#745](https://github.com/texane/stlink/pull/745)) @@ -34,7 +36,6 @@ Updates and fixes: * Only do bank calculation on STM32L4 devices with dual banked flash / Added chip-ID 0x464 for STM32L41xxx/L42xxx devices ([#751](https://github.com/texane/stlink/pull/751)) * Added O_BINARY option to open file ([#753](https://github.com/texane/stlink/pull/753)) * Fixed versioning when compiling from the checked out git-repo ([#762](https://github.com/texane/stlink/pull/762), [#772](https://github.com/texane/stlink/pull/772)) -* Fixed "unkown chip id", piped output and st-util -v ([#107](https://github.com/texane/stlink/pull/107), [#665](https://github.com/texane/stlink/pull/665), [#763](https://github.com/texane/stlink/pull/763)) * win32: move usleep definition to unistd.h ([#765](https://github.com/texane/stlink/pull/765)) * Fixed relative path to the UI files needed by stlink-gui-local (GUI) ([#770](https://github.com/texane/stlink/pull/770), [#771](https://github.com/texane/stlink/pull/771)) * Added howto for sending NRST signal through GDB ([#774](https://github.com/texane/stlink/pull/774), [#776](https://github.com/texane/stlink/pull/776), [#779](https://github.com/texane/stlink/pull/779)) @@ -190,7 +191,7 @@ Chip support added for: * STM32F7xx ([#324](https://github.com/texane/stlink/pull/324), [#326](https://github.com/texane/stlink/pull/326), [#327](https://github.com/texane/stlink/pull/327), [#337](https://github.com/texane/stlink/pull/337)) * STM32F767ZI ([#509](https://github.com/texane/stlink/pull/509)) * STM32L0xx Cat2 devices (chip-ID: 0x425) ([#414](https://github.com/texane/stlink/pull/414)) -* STM32L0xx Cat5 devices (chip-ID: 0x447) ([#406](https://github.com/texane/stlink/pull/406)) +* STM32L0xx Cat5 devices (chip-ID: 0x447) ([#387](https://github.com/texane/stlink/pull/387), [#406](https://github.com/texane/stlink/pull/406)) * STM32L4xx ([#321](https://github.com/texane/stlink/pull/321)) * STM32L432 ([#500](https://github.com/texane/stlink/pull/500), [#501](https://github.com/texane/stlink/pull/501)) @@ -198,7 +199,7 @@ Updates and fixes: * Fixed "unaligned addr or size" when trying to write a program in RAM ([#323](https://github.com/texane/stlink/pull/323)) * Fixed flashing on STM32_F3_SMALL ([#325](https://github.com/texane/stlink/pull/325)) -* Fixed STM32L-problem with flash loader ([#390](https://github.com/texane/stlink/pull/390)) +* Fixed STM32L-problem with flash loader ([#390](https://github.com/texane/stlink/pull/390), [#407](https://github.com/texane/stlink/pull/407),[#408](https://github.com/texane/stlink/pull/408)) * Don't read the target voltage on startup, because it crashes STM32F100 ([#423](https://github.com/texane/stlink/pull/423), [#424](https://github.com/texane/stlink/pull/424)) * Added a useful error message instead of "[!] send_recv" ([#425](https://github.com/texane/stlink/pull/425), [#426](https://github.com/texane/stlink/pull/426)) * Do a JTAG reset prior to reading CPU information when processor is in deep sleep ([#428](https://github.com/texane/stlink/pull/428), [#430](https://github.com/texane/stlink/pull/430), [#451](https://github.com/texane/stlink/pull/451)) @@ -253,6 +254,7 @@ Chip support added for: * Added STM32L4 to CHIPID #defines and devices[], flash driver and loader (Dave Vandervies) * Basic support for STM32F446 (Pavel Kirienko) * STM32F303 High Density +* STM32F469/STM32F479 ([#345](https://github.com/texane/stlink/pull/345), [#555](https://github.com/texane/stlink/pull/555)) (Release v1.2.0) * STM32L1xx Cat.2 devices (Nicolas Schodet) * STM32L1xx (chip-ID 0x427) ([#152](https://github.com/texane/stlink/pull/152), [#163](https://github.com/texane/stlink/pull/163), [#165](https://github.com/texane/stlink/pull/165)) (Release v1.0.0) From 9f2cad2c978a55a4125e6b8c4c656a59e7f9448c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 8 Apr 2020 12:45:10 +0200 Subject: [PATCH 0788/1435] Avoid re-define of O_BINARY on Windows (Fixes #788) --- src/common.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/common.c b/src/common.c index 26202fcef..4e04a33a5 100644 --- a/src/common.c +++ b/src/common.c @@ -16,9 +16,12 @@ #include "stlink/mmap.h" #include "stlink/logging.h" -#ifndef _WIN32 -#define O_BINARY 0 //! @todo get rid of this OH MY (@xor-gate) +#ifdef _WIN32 +#ifndef O_BINARY +#define O_BINARY 0 #endif +#endif + #ifdef _MSC_VER #define __attribute__(x) #endif From ad06dace83d2f6deefcef10b504c250a4a918e89 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 8 Apr 2020 14:10:01 +0200 Subject: [PATCH 0789/1435] Removed old tested-boards list. --- doc/tested-boards.md | 57 -------------------------------------------- 1 file changed, 57 deletions(-) delete mode 100644 doc/tested-boards.md diff --git a/doc/tested-boards.md b/doc/tested-boards.md deleted file mode 100644 index a9fa2f1c6..000000000 --- a/doc/tested-boards.md +++ /dev/null @@ -1,57 +0,0 @@ -Stlink tested and compatible boards -=================================== - -STLink v1 (as found on the 32VL Discovery board) - -Known working targets: - -* STM32F100xx (Medium Density VL) -* STM32F103 (according to jpa- on ##stm32) - -No information: - -* everything else! - -STLink v2 (as found on the 32L and F4 Discovery boards), known working targets: - -* STM32F0 (STM32F0 Discovery board) -* STM32F030F4P6 (custom board) -* STM32F051R8T6 (STM320518-EVAL board) -* STM32F100xx (Medium Density VL, as on the 32VL Discovery board) -* STM32F103VET6 (HY-STM32 board) ([#149](https://github.com/texane/stlink/pull/149)) -* STM32F105RCT6 (DecaWave EVB1000 board) -* STM32F303xx (STM32F3 Discovery board) -* STM32F407xx (STM32F4 Discovery board) -* STM32F411E-DISCO (STM32F4 Discovery board with gyro, audio) -* STM32F429I-DISCO (STM32F4 Discovery board with LCD) -* STM32F439VIT6 (Discovery board reseated CPU) -* STM32L052K8T6 (custom board) -* STM32L1xx (STM32L Discovery board) -* STM32L151CB (custom board) -* STM32L152RB (STM32L-Discovery board, custom board) -* STM32L496ZG (STM32-Nucleo-L496ZG board) - - -* STM32F103VC, STM32F107RC, STM32L151RB, STM32F205RE and STM32F405RE on custom boards - from [UweBonnes/wiki_fuer_alex](https://github.com/UweBonnes/wiki_fuer_alex/tree/master/layout) - - -STLink v2-1 (as found on the Nucleo boards), known working targets: - -* STM32F030R8T6 (STM32 Nucleo-F030R8 board) -* STM32F042K6 (STM32 Nucleo-32 Board) -* STM32F072RBT6 (STM32 Nucleo-F072RB board) -* STM32F103RB (STM32 Nucleo-F103RB board) -* STM32F303RET6 (STM32 Nucleo-F303RE board) -* STM32F334R8 (STM32 Nucleo-F334R8 board) -* STM32F401xx (STM32 Nucleo-F401RE board) -* STM32F411RET6 (STM32 Nucleo-F411RE board) -* STM32F756NGHx (STM32F7 evaluation board) -* STM32F769NI (STM32F7 discovery board) -* STM32L053R8 (STM32 Nucleo-L053R8 board) -* STM32L152RE (STM32-Nucleo-L152RE board -* STM32L452RET6 (STM32 Nucleo-L452RE board) -* STM32L476RG (STM32 Nucleo-L476RG board) - - -Please report any and all known working combinations so I can update this! From 34c0a31204d33fd15a1186709e3f60d186bcda3e Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Wed, 8 Apr 2020 20:33:23 +0800 Subject: [PATCH 0790/1435] Fix dead loop after an unexpected unplug * Fix by adding error handler in gdb-server * Enhance logs for functions with return values --- src/gdbserver/gdb-server.c | 222 ++++++++++++++++++++++++++++--------- 1 file changed, 167 insertions(+), 55 deletions(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 72f676bb2..3aa769e02 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -1115,8 +1115,13 @@ int serve(stlink_t *sl, st_state_t *st) { * emulate attaching and detaching to target. */ unsigned int attached = 1; - + /* + * If a critical error is detected, break from the loop + */ + int critical_error = 0; + int ret; while(1) { + ret = 0; char* packet; int status = gdb_recv_packet(client, &packet); @@ -1226,32 +1231,75 @@ int serve(stlink_t *sl, st_state_t *st) { if (!strncmp(cmd, "resume", 6)) {// resume DLOG("Rcmd: resume\n"); cache_sync(sl); - stlink_run(sl); + ret = stlink_run(sl); + if (ret) { + DLOG("Rcmd: resume failed\n"); + reply = strdup("E00"); + + } else { + reply = strdup("OK"); + } - reply = strdup("OK"); } else if (!strncmp(cmd, "halt", 4)) { //halt - reply = strdup("OK"); + ret = stlink_force_debug(sl); + if (ret) { + DLOG("Rcmd: halt failed\n"); + reply = strdup("E00"); - stlink_force_debug(sl); + } else { + reply = strdup("OK"); + DLOG("Rcmd: halt\n"); + } - DLOG("Rcmd: halt\n"); } else if (!strncmp(cmd, "jtag_reset", 10)) { //jtag_reset reply = strdup("OK"); - stlink_jtag_reset(sl, 0); - stlink_jtag_reset(sl, 1); - stlink_force_debug(sl); + ret = stlink_jtag_reset(sl, 0); + if (ret) { + DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); + reply = strdup("E00"); + + } + + ret = stlink_jtag_reset(sl, 1); + if (ret) { + DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); + reply = strdup("E00"); + + } - DLOG("Rcmd: jtag_reset\n"); + ret = stlink_force_debug(sl); + if (ret) { + DLOG("Rcmd: jtag_reset failed with force_debug\n"); + reply = strdup("E00"); + + } + if (strcmp(reply, "E00")) { + // no errors have been found + DLOG("Rcmd: jtag_reset\n"); + } } else if (!strncmp(cmd, "reset", 5)) { //reset - reply = strdup("OK"); - stlink_force_debug(sl); - stlink_reset(sl); + ret = stlink_force_debug(sl); + if (ret) { + DLOG("Rcmd: reset failed with force_debug\n"); + reply = strdup("E00"); + } + + ret = stlink_reset(sl); + if (ret) { + DLOG("Rcmd: reset failed with reset\n"); + reply = strdup("E00"); + } + init_code_breakpoints(sl); init_data_watchpoints(sl); - DLOG("Rcmd: reset\n"); + if (reply == NULL) { + reply = strdup("OK"); + DLOG("Rcmd: reset\n"); + } + } else if (!strncmp(cmd, "semihosting ", 12)) { DLOG("Rcmd: got semihosting cmd '%s'", cmd); char *arg = cmd + 12; @@ -1369,7 +1417,10 @@ int serve(stlink_t *sl, st_state_t *st) { case 'c': cache_sync(sl); - stlink_run(sl); + ret = stlink_run(sl); + if (ret) { + DLOG("Semihost: run failed\n"); + } while(1) { status = gdb_check_for_interrupt(client); @@ -1384,10 +1435,12 @@ int serve(stlink_t *sl, st_state_t *st) { break; } - stlink_status(sl); + ret = stlink_status(sl); + if (ret) { + DLOG("Semihost: status failed\n"); + } if(sl->core_stat == STLINK_CORE_HALTED) { struct stlink_reg reg; - int ret; stm32_addr_t pc; stm32_addr_t addr; int offset = 0; @@ -1397,7 +1450,10 @@ int serve(stlink_t *sl, st_state_t *st) { break; } - stlink_read_all_regs (sl, ®); + ret = stlink_read_all_regs (sl, ®); + if (ret) { + DLOG("Semihost: read_all_regs failed\n"); + } /* Read PC */ pc = reg.r[15]; @@ -1421,17 +1477,29 @@ int serve(stlink_t *sl, st_state_t *st) { if (insn == 0xBEAB && !has_breakpoint(addr)) { - do_semihosting (sl, reg.r[0], reg.r[1], ®.r[0]); + ret = do_semihosting (sl, reg.r[0], reg.r[1], ®.r[0]); + if (ret) { + DLOG("Semihost: do_semihosting failed\n"); + } /* Write return value */ - stlink_write_reg(sl, reg.r[0], 0); + ret = stlink_write_reg(sl, reg.r[0], 0); + if (ret) { + DLOG("Semihost: write_reg failed for return value\n"); + } /* Jump over the break instruction */ - stlink_write_reg(sl, reg.r[15] + 2, 15); + ret = stlink_write_reg(sl, reg.r[15] + 2, 15); + if (ret) { + DLOG("Semihost: write_reg failed for jumping over break\n"); + } /* continue execution */ cache_sync(sl); - stlink_run(sl); + ret = stlink_run(sl); + if (ret) { + DLOG("Semihost: continue execution failed with stlink_run\n"); + } } else { break; } @@ -1444,10 +1512,17 @@ int serve(stlink_t *sl, st_state_t *st) { break; case 's': - cache_sync(sl); - stlink_step(sl); + cache_sync(sl); + ret = stlink_step(sl); + if (ret) { + // have problem sending step packet + ELOG("Step: cannot send step request\n"); + reply = strdup("E00"); + critical_error = 1; // absolutely critical + } else { + reply = strdup("S05"); // TRAP + } - reply = strdup("S05"); // TRAP break; case '?': @@ -1460,7 +1535,10 @@ int serve(stlink_t *sl, st_state_t *st) { break; case 'g': - stlink_read_all_regs(sl, ®p); + ret = stlink_read_all_regs(sl, ®p); + if (ret) { + DLOG("g packet: read_all_regs failed\n"); + } reply = calloc(8 * 16 + 1, 1); for(int i = 0; i < 16; i++) @@ -1473,41 +1551,48 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned myreg = 0xDEADDEAD; if(id < 16) { - stlink_read_reg(sl, id, ®p); + ret = stlink_read_reg(sl, id, ®p); myreg = htonl(regp.r[id]); } else if(id == 0x19) { - stlink_read_reg(sl, 16, ®p); + ret = stlink_read_reg(sl, 16, ®p); myreg = htonl(regp.xpsr); } else if(id == 0x1A) { - stlink_read_reg(sl, 17, ®p); + ret = stlink_read_reg(sl, 17, ®p); myreg = htonl(regp.main_sp); } else if(id == 0x1B) { - stlink_read_reg(sl, 18, ®p); + ret = stlink_read_reg(sl, 18, ®p); myreg = htonl(regp.process_sp); } else if(id == 0x1C) { - stlink_read_unsupported_reg(sl, id, ®p); + ret = stlink_read_unsupported_reg(sl, id, ®p); myreg = htonl(regp.control); } else if(id == 0x1D) { - stlink_read_unsupported_reg(sl, id, ®p); + ret = stlink_read_unsupported_reg(sl, id, ®p); myreg = htonl(regp.faultmask); } else if(id == 0x1E) { - stlink_read_unsupported_reg(sl, id, ®p); + ret = stlink_read_unsupported_reg(sl, id, ®p); myreg = htonl(regp.basepri); } else if(id == 0x1F) { - stlink_read_unsupported_reg(sl, id, ®p); + ret = stlink_read_unsupported_reg(sl, id, ®p); myreg = htonl(regp.primask); } else if(id >= 0x20 && id < 0x40) { - stlink_read_unsupported_reg(sl, id, ®p); + ret = stlink_read_unsupported_reg(sl, id, ®p); myreg = htonl(regp.s[id-0x20]); } else if(id == 0x40) { - stlink_read_unsupported_reg(sl, id, ®p); + ret = stlink_read_unsupported_reg(sl, id, ®p); myreg = htonl(regp.fpscr); } else { + ret = 1; reply = strdup("E00"); } + if (ret) { + DLOG("p packet: stlink_read_unsupported_reg failed with id %u\n", id); + } - reply = calloc(8 + 1, 1); - sprintf(reply, "%08x", myreg); + if (reply == NULL) { + // if reply is set to "E00", skip + reply = calloc(8 + 1, 1); + sprintf(reply, "%08x", myreg); + } break; } @@ -1519,31 +1604,36 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned reg = (unsigned int) strtoul(s_reg, NULL, 16); unsigned value = (unsigned int) strtoul(s_value, NULL, 16); + if(reg < 16) { - stlink_write_reg(sl, ntohl(value), reg); + ret = stlink_write_reg(sl, ntohl(value), reg); } else if(reg == 0x19) { - stlink_write_reg(sl, ntohl(value), 16); + ret = stlink_write_reg(sl, ntohl(value), 16); } else if(reg == 0x1A) { - stlink_write_reg(sl, ntohl(value), 17); + ret = stlink_write_reg(sl, ntohl(value), 17); } else if(reg == 0x1B) { - stlink_write_reg(sl, ntohl(value), 18); + ret = stlink_write_reg(sl, ntohl(value), 18); } else if(reg == 0x1C) { - stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); } else if(reg == 0x1D) { - stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); } else if(reg == 0x1E) { - stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); } else if(reg == 0x1F) { - stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); } else if(reg >= 0x20 && reg < 0x40) { - stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); } else if(reg == 0x40) { - stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); } else { + ret = 1; reply = strdup("E00"); } - - if(!reply) { + if (ret) { + DLOG("P packet: stlink_write_unsupported_reg failed with reg %u\n", reg); + } + if(reply == NULL) { + // note that NULL may not be zero reply = strdup("OK"); } @@ -1555,7 +1645,10 @@ int serve(stlink_t *sl, st_state_t *st) { char str[9] = {0}; strncpy(str, &packet[1 + i * 8], 8); uint32_t reg = (uint32_t) strtoul(str, NULL, 16); - stlink_write_reg(sl, ntohl(reg), i); + ret = stlink_write_reg(sl, ntohl(reg), i); + if (ret) { + DLOG("G packet: stlink_write_reg failed"); + } } reply = strdup("OK"); @@ -1729,9 +1822,13 @@ int serve(stlink_t *sl, st_state_t *st) { } case 'R': { + /* Reset the core. */ - stlink_reset(sl); + ret = stlink_reset(sl); + if (ret) { + DLOG("R packet : stlink_reset failed\n"); + } init_code_breakpoints(sl); init_data_watchpoints(sl); @@ -1743,8 +1840,15 @@ int serve(stlink_t *sl, st_state_t *st) { } case 'k': /* Kill request - reset the connection itself */ - stlink_run(sl); - stlink_exit_debug_mode(sl); + ret = stlink_run(sl); + if (ret) { + DLOG("Kill: stlink_run failed\n"); + } + + ret = stlink_exit_debug_mode(sl); + if (ret) { + DLOG("Kill: stlink_exit_debug_mode failed\n"); + } stlink_close(sl); sl = do_connect(st); @@ -1754,7 +1858,10 @@ int serve(stlink_t *sl, st_state_t *st) { if (st->reset) { stlink_reset(sl); } - stlink_force_debug(sl); + ret = stlink_force_debug(sl); + if (ret) { + DLOG("Kill: stlink_force_debug failed\n"); + } init_cache(sl); init_code_breakpoints(sl); init_data_watchpoints(sl); @@ -1782,6 +1889,11 @@ int serve(stlink_t *sl, st_state_t *st) { free(reply); } + if (critical_error) { + close_socket(client); + return 1; + } + free(packet); } From c6753e3bdbcc23b2665373af389abe04cdbd150a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 8 Apr 2020 15:29:01 +0200 Subject: [PATCH 0791/1435] Fixed compilation errors (Regression) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit -> error: ‘O_BINARY’ undeclared -> tabspaces in Makefile --- Makefile | 44 ++++++++++++++++++++++---------------------- src/common.c | 5 +++-- 2 files changed, 25 insertions(+), 24 deletions(-) diff --git a/Makefile b/Makefile index a94ec598b..df9099a9e 100644 --- a/Makefile +++ b/Makefile @@ -4,45 +4,45 @@ MAKEFLAGS += -s all: release -ci: debug release test +ci: debug release test help: - @echo " release: Run a release build" - @echo " debug: Run a debug build" - @echo " lint: Lint check all source-code" - @echo " test: Build and run tests" - @echo " clean: Clean all build output" - @echo "rebuild_cache: Rebuild all CMake caches" + @echo " release: Run a release build" + @echo " debug: Run a debug build" + @echo " lint: Lint check all source-code" + @echo " test: Build and run tests" + @echo " clean: Clean all build output" + @echo "rebuild_cache: Rebuild all CMake caches" rebuild_cache: build/Debug build/Release - @$(MAKE) -C build/Debug rebuild_cache - @$(MAKE) -C build/Release rebuild_cache + @$(MAKE) -C build/Debug rebuild_cache + @$(MAKE) -C build/Release rebuild_cache debug: build/Debug - @echo "[DEBUG]" - @$(MAKE) -C build/Debug + @echo "[DEBUG]" + @$(MAKE) -C build/Debug release: build/Release - @echo "[RELEASE]" - @$(MAKE) -C build/Release + @echo "[RELEASE]" + @$(MAKE) -C build/Release package: build/Release - @echo "[PACKAGE] Release" - @$(MAKE) -C build/Release package + @echo "[PACKAGE] Release" + @$(MAKE) -C build/Release package test: debug - @$(MAKE) -C build/Debug test + @$(MAKE) -C build/Debug test build/Debug: - @mkdir -p $@ - @cd $@ && cmake -DCMAKE_BUILD_TYPE=Debug $(CMAKEFLAGS) ../../ + @mkdir -p $@ + @cd $@ && cmake -DCMAKE_BUILD_TYPE=Debug $(CMAKEFLAGS) ../../ build/Release: - @mkdir -p $@ - @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Release $(CMAKEFLAGS) ../../ + @mkdir -p $@ + @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Release $(CMAKEFLAGS) ../../ clean: - @echo "[CLEAN]" - @rm -Rf build + @echo "[CLEAN]" + @rm -Rf build .PHONY: clean diff --git a/src/common.c b/src/common.c index 913d70e35..27db09fa2 100644 --- a/src/common.c +++ b/src/common.c @@ -15,9 +15,10 @@ #include "stlink/mmap.h" #include "stlink/logging.h" -#ifndef _WIN32 -#define O_BINARY 0 //! @todo get rid of this OH MY (@xor-gate) +#ifndef O_BINARY +#define O_BINARY 0 #endif + #ifdef _MSC_VER #define __attribute__(x) #endif From 6f941b22eb00844eca7d17ebe3168d34276ef6b3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 8 Apr 2020 15:34:10 +0200 Subject: [PATCH 0792/1435] Fixed compilation errors (Regression) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit -> error: ‘O_BINARY’ undeclared -> tabspaces in Makefile --- Makefile | 45 ++++++++++++++++++++++----------------------- src/common.c | 2 -- 2 files changed, 22 insertions(+), 25 deletions(-) diff --git a/Makefile b/Makefile index 7f81488bb..0636eb9bd 100644 --- a/Makefile +++ b/Makefile @@ -1,6 +1,5 @@ ## -# This Makefile is used to drive building of Debug and Release -# targets of CMake +# This Makefile is used to drive building of Debug and Release targets of CMake ## MAKEFLAGS += -s @@ -8,42 +7,42 @@ all: release ci: debug release test help: - @echo " release: Run a release build" - @echo " debug: Run a debug build" - @echo " lint: Lint check all source-code" - @echo " test: Build and run tests" - @echo " clean: Clean all build output" - @echo "rebuild_cache: Rebuild all CMake caches" + @echo " release: Run a release build" + @echo " debug: Run a debug build" + @echo " lint: Lint check all source-code" + @echo " test: Build and run tests" + @echo " clean: Clean all build output" + @echo "rebuild_cache: Rebuild all CMake caches" rebuild_cache: build/Debug build/Release - @$(MAKE) -C build/Debug rebuild_cache - @$(MAKE) -C build/Release rebuild_cache + @$(MAKE) -C build/Debug rebuild_cache + @$(MAKE) -C build/Release rebuild_cache debug: build/Debug - @echo "[DEBUG]" - @$(MAKE) -C build/Debug + @echo "[DEBUG]" + @$(MAKE) -C build/Debug release: build/Release - @echo "[RELEASE]" - @$(MAKE) -C build/Release + @echo "[RELEASE]" + @$(MAKE) -C build/Release package: build/Release - @echo "[PACKAGE] Release" - @$(MAKE) -C build/Release package + @echo "[PACKAGE] Release" + @$(MAKE) -C build/Release package test: debug - @$(MAKE) -C build/Debug test + @$(MAKE) -C build/Debug test build/Debug: - @mkdir -p $@ - @cd $@ && cmake -DCMAKE_BUILD_TYPE=Debug $(CMAKEFLAGS) ../../ + @mkdir -p $@ + @cd $@ && cmake -DCMAKE_BUILD_TYPE=Debug $(CMAKEFLAGS) ../../ build/Release: - @mkdir -p $@ - @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Release $(CMAKEFLAGS) ../../ + @mkdir -p $@ + @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Release $(CMAKEFLAGS) ../../ clean: - @echo "[CLEAN]" - @rm -Rf build + @echo "[CLEAN]" + @rm -Rf build .PHONY: clean diff --git a/src/common.c b/src/common.c index 4e04a33a5..f432cf5a1 100644 --- a/src/common.c +++ b/src/common.c @@ -16,11 +16,9 @@ #include "stlink/mmap.h" #include "stlink/logging.h" -#ifdef _WIN32 #ifndef O_BINARY #define O_BINARY 0 #endif -#endif #ifdef _MSC_VER #define __attribute__(x) From 38c8b8b499f1d9e87db214e9fb2c144e593c8a08 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 8 Apr 2020 23:44:51 +0200 Subject: [PATCH 0793/1435] Cleanup - Whitespace fixes - Removed old appveyor-mingw script - travis-lin-mingw.sh -> .gitignore --- .appveyor.yml | 21 ---------------- .gitignore | 2 ++ cmake/version.cmake | 61 ++++++++++++++++++++++----------------------- src/win32/unistd.h | 31 ++++++++++++----------- 4 files changed, 48 insertions(+), 67 deletions(-) delete mode 100644 .appveyor.yml diff --git a/.appveyor.yml b/.appveyor.yml deleted file mode 100644 index 10c0e935a..000000000 --- a/.appveyor.yml +++ /dev/null @@ -1,21 +0,0 @@ -version: '{build}' -environment: - matrix: - - GENERATOR: "MSYS Makefiles" - ARCH: i686 # this is for 32-bit MinGW-w64 - - GENERATOR: "MSYS Makefiles" - ARCH: 64 -cache: - - i686-4.9.2-release-win32-sjlj-rt_v3-rev1.7z - - x86_64-4.9.2-release-win32-seh-rt_v3-rev1.7z - - libusb-1.0.20.7z -build_script: -- ps: | - mkdir build - cd build - if ($env:GENERATOR -ne "MSYS Makefiles") { - cmake .. -G"$env:GENERATOR" - cmake --build . --config Debug - } -- cmd: | - if "%GENERATOR%"=="MSYS Makefiles" (C:\MinGW\msys\1.0\bin\sh --login /c/projects/stlink/scripts/appveyor-mingw.sh) diff --git a/.gitignore b/.gitignore index 23e7ddc07..d2dde3a25 100644 --- a/.gitignore +++ b/.gitignore @@ -2,3 +2,5 @@ build build-mingw obj-* *.user* + +.travis-lin-mingw.sh diff --git a/cmake/version.cmake b/cmake/version.cmake index e9e2f7a05..fe778c419 100644 --- a/cmake/version.cmake +++ b/cmake/version.cmake @@ -15,78 +15,77 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") OUTPUT_VARIABLE PROJECT_VERSION RESULT_VARIABLE GIT_DESCRIBE_RESULT ERROR_VARIABLE GIT_DESCRIBE_ERROR - OUTPUT_STRIP_TRAILING_WHITESPACE) + OUTPUT_STRIP_TRAILING_WHITESPACE + ) - if(GIT_DESCRIBE_RESULT EQUAL 0) + if (GIT_DESCRIBE_RESULT EQUAL 0) # If the sources have been changed locally, add -dirty to the version. execute_process ( - COMMAND "${GIT_EXECUTABLE}" diff --quiet - WORKING_DIRECTORY "${PROJECT_SOURCE_DIR}" - RESULT_VARIABLE res) + COMMAND "${GIT_EXECUTABLE}" diff --quiet + WORKING_DIRECTORY "${PROJECT_SOURCE_DIR}" + RESULT_VARIABLE res + ) if (res EQUAL 1) set (PROJECT_VERSION "${PROJECT_VERSION}-dirty") - endif() + endif () # strip a leading v off of the version as proceeding code expectes just the version numbering. string(REGEX REPLACE "^v" "" PROJECT_VERSION ${PROJECT_VERSION}) string(REGEX REPLACE "^(0|[1-9][0-9]*)[.](0|[1-9][0-9]*)[.](0|[1-9][0-9]*)(-[.0-9A-Za-z-]+)?([+][.0-9A-Za-z-]+)?$" - "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) + "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) list(LENGTH PROJECT_VERSION_LIST len) - if(len EQUAL 3) + if (len EQUAL 3) list(GET PROJECT_VERSION_LIST 0 PROJECT_VERSION_MAJOR) list(GET PROJECT_VERSION_LIST 1 PROJECT_VERSION_MINOR) list(GET PROJECT_VERSION_LIST 2 PROJECT_VERSION_PATCH) set(__detect_version 1) set(__version_str "${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}") - if(EXISTS "${PROJECT_SOURCE_DIR}/.version") + if (EXISTS "${PROJECT_SOURCE_DIR}/.version") file(READ "${PROJECT_SOURCE_DIR}/.version" __version_file) - if(NOT __version_str STREQUAL __version_file) + if (NOT __version_str STREQUAL __version_file) message(STATUS "Rewrite ${PROJECT_SOURCE_DIR}/.version with ${__version_str}") - endif() - else() + endif () + else () file(WRITE "${PROJECT_SOURCE_DIR}/.version" ${__version_str}) - endif() - else() - message(STATUS "Fail to extract version's parts from \"${PROJECT_VERSION}\"") - endif() + endif () + else () + message(STATUS "Fail to extract version parts from \"${PROJECT_VERSION}\"") + endif () else(GIT_DESCRIBE_RESULT EQUAL 0) message(WARNING "git describe failed.") message(WARNING "${GIT_DESCRIBE_ERROR}") endif(GIT_DESCRIBE_RESULT EQUAL 0) -else() +else () message(STATUS "Git or repo not found.") -endif() +endif () -if(NOT __detect_version) +if (NOT __detect_version) message(STATUS "Try to detect version from \"${PROJECT_SOURCE_DIR}/.version\" file.") - if(EXISTS ${PROJECT_SOURCE_DIR}/.version) + if (EXISTS ${PROJECT_SOURCE_DIR}/.version) # If git is not available (e.g. when building from source package) # we can extract the package version from .version file. - file (STRINGS .version PROJECT_VERSION) + file(STRINGS .version PROJECT_VERSION) # TODO create function to extract semver from file or string and check if it is correct instead of copy-pasting string(REGEX REPLACE "^(0|[1-9][0-9]*)[.](0|[1-9][0-9]*)[.](0|[1-9][0-9]*)(-[.0-9A-Za-z-]+)?([+][.0-9A-Za-z-]+)?$" "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) list(LENGTH PROJECT_VERSION_LIST len) - if(len EQUAL 3) + if (len EQUAL 3) list(GET PROJECT_VERSION_LIST 0 PROJECT_VERSION_MAJOR) list(GET PROJECT_VERSION_LIST 1 PROJECT_VERSION_MINOR) list(GET PROJECT_VERSION_LIST 2 PROJECT_VERSION_PATCH) set(__detect_version 1) - else() - message(STATUS "Fail to extract version's parts from \"${PROJECT_VERSION}\"") - endif() - else() + else () + message(STATUS "Fail to extract version parts from \"${PROJECT_VERSION}\"") + endif () + else () message(STATUS "File \"${PROJECT_SOURCE_DIR}/.version\" did not exists.") - endif() -endif() - -if(NOT __detect_version) + endif () message(FATAL_ERROR "Unable to determine project version") -endif() +endif () message(STATUS "stlink version: ${PROJECT_VERSION}") message(STATUS "Major ${PROJECT_VERSION_MAJOR} Minor ${PROJECT_VERSION_MINOR} Patch ${PROJECT_VERSION_PATCH}") diff --git a/src/win32/unistd.h b/src/win32/unistd.h index 4c94aed34..5b2798b41 100644 --- a/src/win32/unistd.h +++ b/src/win32/unistd.h @@ -1,9 +1,9 @@ #ifndef _UNISTD_H #define _UNISTD_H 1 -/* This file intended to serve as a drop-in replacement for - * unistd.h on Windows - * Please add functionality as neeeded +/* + * This file intended to serve as a drop-in replacement for unistd.h on Windows + * Please add functionality as neeeded. */ #include @@ -16,19 +16,18 @@ #if defined(_MSC_VER) #pragma warning(pop) #endif -#include /* getopt at: https://gist.github.com/ashelly/7776712 */ -#include /* for getpid() and the exec..() family */ -#include /* for _getcwd() and _chdir() */ +#include // getopt at: https://gist.github.com/ashelly/7776712 +#include // for getpid() and the exec..() family +#include // for _getcwd() and _chdir() #define srandom srand #define random rand -/* Values for the second argument to access. - These may be OR'd together. */ -#define R_OK 4 /* Test for read permission. */ -#define W_OK 2 /* Test for write permission. */ -//#define X_OK 1 /* execute permission - unsupported in windows*/ -#define F_OK 0 /* Test for existence. */ +/* Values for the second argument to access. These may be OR'd together. */ +#define R_OK 4 // Test for read permission +#define W_OK 2 // Test for write permission +// #define X_OK 1 // execute permission - unsupported in windows +#define F_OK 0 // Test for existence #define access _access #define dup2 _dup2 @@ -40,7 +39,9 @@ #define chdir _chdir #define isatty _isatty #define lseek _lseek -/* read, write, and close are NOT being #defined here, because while there are file handle specific versions for Windows, they probably don't work for sockets. You need to look at your app and consider whether to call e.g. closesocket(). */ +/* read, write, and close are NOT being defined here, + * because while there are file handle specific versions for Windows, they probably don't work for sockets. + * You need to look at your app and consider whether to call e.g. closesocket(). */ #define ssize_t int @@ -49,7 +50,7 @@ #define STDERR_FILENO 2 /* should be in some equivalent to */ typedef __int8 int8_t; -typedef __int16 int16_t; +typedef __int16 int16_t; typedef __int32 int32_t; typedef __int64 int64_t; typedef unsigned __int8 uint8_t; @@ -61,4 +62,4 @@ typedef unsigned __int64 uint64_t; int usleep(unsigned int waitTime); #endif -#endif /* unistd.h */ +#endif /* unistd.h */ From 12faa5332ccc02f47c18d2c4ec2c0c0489f7e741 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Fri, 10 Apr 2020 22:07:52 +0800 Subject: [PATCH 0794/1435] Fix memory overlap --- tests/flash.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/flash.c b/tests/flash.c index 6c8b8ed9b..b17aa99ae 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -30,9 +30,9 @@ static bool execute_test(const struct Test * test) { // parse (tokenize) the test command line #if defined(_MSC_VER) - char *cmd_line = alloca(strlen(test->cmd_line)); + char *cmd_line = alloca(strlen(test->cmd_line) + 1); #else - char cmd_line[strlen(test->cmd_line)]; + char cmd_line[strlen(test->cmd_line) + 1]; #endif strcpy(cmd_line, test->cmd_line); From 90081dd1f3b31574e76bd068e0814e7015420089 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 10 Apr 2020 14:34:51 +0200 Subject: [PATCH 0795/1435] usb.h: define some stlink usb pid macros, stop copypasting. ease v1/v2/v2.1/v3 identification and supported devices filtering --- include/stlink/usb.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/stlink/usb.h b/include/stlink/usb.h index 9357c248e..1448481be 100644 --- a/include/stlink/usb.h +++ b/include/stlink/usb.h @@ -29,6 +29,24 @@ extern "C" { #define STLINK_USB_PID_STLINK_V3S_PID 0x374f #define STLINK_USB_PID_STLINK_V3_2VCP_PID 0x3753 +#define STLINK_V1_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK ) + +#define STLINK_V2_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK_32L || \ + (pid) == STLINK_USB_PID_STLINK_32L_AUDIO || \ + (pid) == STLINK_USB_PID_STLINK_NUCLEO) + +#define STLINK_V2_1_USB_PID(pid) ( (pid) == STLINK_USB_PID_STLINK_V2_1 ) + +#define STLINK_V3_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK_V3_USBLOADER || \ + (pid) == STLINK_USB_PID_STLINK_V3E_PID || \ + (pid) == STLINK_USB_PID_STLINK_V3S_PID || \ + (pid) == STLINK_USB_PID_STLINK_V3_2VCP_PID ) + +#define STLINK_SUPPORTED_USB_PID(pid) ( STLINK_V1_USB_PID(pid) || \ + STLINK_V2_USB_PID(pid) || \ + STLINK_V2_1_USB_PID(pid) || \ + STLINK_V3_USB_PID(pid)) + #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 From 8fba7ab9fe9647957763be5f00443cb2192f8a28 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 10 Apr 2020 11:51:27 +0200 Subject: [PATCH 0796/1435] usb.c: align probe code. actually open all counted devices - the two vid check need to be aligned. also now display if some st device has been skipped. --- src/usb.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/src/usb.c b/src/usb.c index f9d141745..7ebd58b1a 100644 --- a/src/usb.c +++ b/src/usb.c @@ -1114,15 +1114,13 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { break; } - if (desc.idProduct != STLINK_USB_PID_STLINK_32L && - desc.idProduct != STLINK_USB_PID_STLINK_32L_AUDIO && - desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO && - desc.idProduct != STLINK_USB_PID_STLINK_V2_1 && - desc.idProduct != STLINK_USB_PID_STLINK_V3_USBLOADER && - desc.idProduct != STLINK_USB_PID_STLINK_V3E_PID && - desc.idProduct != STLINK_USB_PID_STLINK_V3S_PID && - desc.idProduct != STLINK_USB_PID_STLINK_V3_2VCP_PID) - continue; + if (desc.idVendor != STLINK_USB_VID_ST) + continue; + + if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { + WLOG("skipping ST device : %#04x:%#04x)\n", desc.idVendor, desc.idProduct); + continue; + } slcnt++; } @@ -1144,10 +1142,9 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { break; } - if (desc.idProduct != STLINK_USB_PID_STLINK_32L && - desc.idProduct != STLINK_USB_PID_STLINK_32L_AUDIO && - desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO) + if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { continue; + } struct libusb_device_handle* handle; char serial[STLINK_SERIAL_MAX_SIZE]; From 6b03c7f9ed4c65139aa05900e288bd5228d62024 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 10 Apr 2020 11:55:03 +0200 Subject: [PATCH 0797/1435] usb.c: rework probe loop to _not_ free all stuff without closing if _one_ probe failed. we return count and list of successfully probed devices, no need to free everything if some libusb call of the last probe attempt failed. --- src/usb.c | 45 ++++++++++++++++++--------------------------- 1 file changed, 18 insertions(+), 27 deletions(-) diff --git a/src/usb.c b/src/usb.c index 7ebd58b1a..e3b2a453c 100644 --- a/src/usb.c +++ b/src/usb.c @@ -1101,14 +1101,13 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { stlink_t **_sldevs; libusb_device *dev; int i = 0; - int ret = 0; size_t slcnt = 0; size_t slcur = 0; /* Count stlink */ while ((dev = devs[i++]) != NULL) { struct libusb_device_descriptor desc; - ret = libusb_get_device_descriptor(dev, &desc); + int ret = libusb_get_device_descriptor(dev, &desc); if (ret < 0) { WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); break; @@ -1136,7 +1135,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { i = 0; while ((dev = devs[i++]) != NULL) { struct libusb_device_descriptor desc; - ret = libusb_get_device_descriptor(dev, &desc); + int ret = libusb_get_device_descriptor(dev, &desc); if (ret < 0) { WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); break; @@ -1146,40 +1145,32 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { continue; } - struct libusb_device_handle* handle; - char serial[STLINK_SERIAL_MAX_SIZE]; - memset(serial, 0, sizeof(serial)); + struct libusb_device_handle* handle; + char serial[STLINK_SERIAL_MAX_SIZE] = {0,}; - ret = libusb_open(dev, &handle); - if (ret < 0) { - if (ret == LIBUSB_ERROR_ACCESS) { + ret = libusb_open(dev, &handle); + if (ret < 0) { + if (ret == LIBUSB_ERROR_ACCESS) { WLOG("failed to open USB device (LIBUSB_ERROR_ACCESS), try running as root?\n"); } else { WLOG("failed to open USB device (libusb error: %d)\n", ret); - } - break; - } + } + break; + } + + ret = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)&serial, sizeof(serial)); - ret = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)&serial, sizeof(serial)); - if (ret < 0) - *serial = 0; + libusb_close(handle); - libusb_close(handle); + if (ret < 0) { + continue; + } - stlink_t *sl = NULL; - sl = stlink_open_usb(0, 1, serial); + stlink_t *sl = stlink_open_usb(0, 1, serial); if (!sl) continue; - _sldevs[slcur] = sl; - slcur++; - } - - /* Something went wrong */ - if (ret < 0) { - free(_sldevs); - *sldevs = NULL; - return 0; + _sldevs[slcur++] = sl; } *sldevs = _sldevs; From aff1df29adfb945983e8938807fd58aa2222b5bf Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 10 Apr 2020 11:58:28 +0200 Subject: [PATCH 0798/1435] stlink_probe_usb_devs: return number of successfully opened devices, not number of probed devices. --- src/usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/usb.c b/src/usb.c index e3b2a453c..6000e1b4b 100644 --- a/src/usb.c +++ b/src/usb.c @@ -1174,7 +1174,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { } *sldevs = _sldevs; - return slcnt; + return slcur; } size_t stlink_probe_usb(stlink_t **stdevs[]) { From 512999da56107e783e1982a459d3197b4959bb9d Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 10 Apr 2020 15:04:51 +0200 Subject: [PATCH 0799/1435] stlink_open_usb: use macros for stlink pid filtering --- src/usb.c | 25 +++++-------------------- 1 file changed, 5 insertions(+), 20 deletions(-) diff --git a/src/usb.c b/src/usb.c index 6000e1b4b..d1c7e6484 100644 --- a/src/usb.c +++ b/src/usb.c @@ -937,14 +937,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST } } - if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) || - (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO) || - (desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO) || - (desc.idProduct == STLINK_USB_PID_STLINK_V2_1) || - (desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER) || - (desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID) || - (desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID) || - (desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID)) { + if (STLINK_V2_USB_PID(desc.idProduct) || STLINK_V2_1_USB_PID(desc.idProduct) || STLINK_V3_USB_PID(desc.idProduct)) { struct libusb_device_handle *handle; ret = libusb_open(list[cnt], &handle); @@ -955,15 +948,9 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST (unsigned char *)sl->serial, sizeof(sl->serial)); libusb_close(handle); - if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) - || (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO) - || (desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO) - || (desc.idProduct == STLINK_USB_PID_STLINK_V2_1)) { - sl->version.stlink_v = 2; - } else if ((desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER) - || (desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID) - || (desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID) - || (desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID)) { + if (STLINK_V2_USB_PID(desc.idProduct) || STLINK_V2_1_USB_PID(desc.idProduct)) { + sl->version.stlink_v = 2; + } else if (STLINK_V3_USB_PID(desc.idProduct)) { sl->version.stlink_v = 3; } @@ -977,9 +964,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST break; continue; - } - - if (desc.idProduct == STLINK_USB_PID_STLINK) { + } else if (STLINK_V1_USB_PID(desc.idProduct)) { slu->protocoll = 1; sl->version.stlink_v = 1; break; From 395eee53dfa65302466cd46296b3f2681f3a3f0a Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 10 Apr 2020 17:25:20 +0200 Subject: [PATCH 0800/1435] stlink_open_usb: fix serial lookup mecanism when a v1 device is connected. serial match was not done for v1 device, resulting in attempting to open it systematically, leading to some libusb device claim call failure. Lookup device serial for all chips, compare it if needed, and continue. --- src/usb.c | 56 +++++++++++++++++++++++++++---------------------------- 1 file changed, 27 insertions(+), 29 deletions(-) diff --git a/src/usb.c b/src/usb.c index d1c7e6484..850ae18a1 100644 --- a/src/usb.c +++ b/src/usb.c @@ -926,6 +926,8 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST } while (cnt--) { + struct libusb_device_handle *handle; + libusb_get_device_descriptor( list[cnt], &desc ); if (desc.idVendor != STLINK_USB_VID_ST) continue; @@ -937,48 +939,44 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST } } - if (STLINK_V2_USB_PID(desc.idProduct) || STLINK_V2_1_USB_PID(desc.idProduct) || STLINK_V3_USB_PID(desc.idProduct)) { - struct libusb_device_handle *handle; - - ret = libusb_open(list[cnt], &handle); - if (ret) - continue; + ret = libusb_open(list[cnt], &handle); - sl->serial_size = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, - (unsigned char *)sl->serial, sizeof(sl->serial)); - libusb_close(handle); + /* could not open device, continue */ + if (ret) + continue; - if (STLINK_V2_USB_PID(desc.idProduct) || STLINK_V2_1_USB_PID(desc.idProduct)) { - sl->version.stlink_v = 2; - } else if (STLINK_V3_USB_PID(desc.idProduct)) { - sl->version.stlink_v = 3; - } + sl->serial_size = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, + (unsigned char *)sl->serial, sizeof(sl->serial)); - if ((serial == NULL) || (*serial == 0)) - break; + libusb_close(handle); - if (sl->serial_size < 0) - continue; + /* could not read serial, continue */ + if (sl->serial_size < 0) + continue; - if (memcmp(serial, &sl->serial, sl->serial_size) == 0) - break; + /* if no serial provided, or if serial match device, fixup version and protocol */ + if (((serial == NULL) || (*serial == 0)) || (memcmp(serial, &sl->serial, sl->serial_size) == 0)) { + if (STLINK_V1_USB_PID(desc.idProduct)) { + slu->protocoll = 1; + sl->version.stlink_v = 1; + } else if (STLINK_V2_USB_PID(desc.idProduct) || STLINK_V2_1_USB_PID(desc.idProduct)) { + sl->version.stlink_v = 2; + } else if (STLINK_V3_USB_PID(desc.idProduct)) { + sl->version.stlink_v = 3; + } - continue; - } else if (STLINK_V1_USB_PID(desc.idProduct)) { - slu->protocoll = 1; - sl->version.stlink_v = 1; - break; - } + break; + } } if (cnt < 0) { - WLOG ("Couldn't find %s ST-Link/V2 devices\n",(devBus && devAddr)?"matched":"any"); + WLOG ("Couldn't find %s ST-Link devices\n", (devBus && devAddr) ? "matched":"any"); goto on_error; } else { ret = libusb_open(list[cnt], &slu->usb_handle); if (ret != 0) { - WLOG("Error %d (%s) opening ST-Link/V2 device %03d:%03d\n", - ret, strerror (errno), libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); + WLOG("Error %d (%s) opening ST-Link v%d device %03d:%03d\n", + ret, strerror (errno), sl->version.stlink_v, libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); libusb_free_device_list(list, 1); goto on_error; } From cec61aaea33fbe7a07887867dda9149ea74c16a0 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 10 Apr 2020 17:26:15 +0200 Subject: [PATCH 0801/1435] stlink_open_usb: remove wrong comment, we do handle protocoll (?) v1 for stlinkv1 --- src/usb.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/usb.c b/src/usb.c index 850ae18a1..970d3ee81 100644 --- a/src/usb.c +++ b/src/usb.c @@ -1027,8 +1027,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST } slu->sg_transfer_idx = 0; - // TODO - never used at the moment, always CMD_SIZE - slu->cmd_len = (slu->protocoll == 1)? STLINK_SG_SIZE: STLINK_CMD_SIZE; + slu->cmd_len = (slu->protocoll == 1) ? STLINK_SG_SIZE: STLINK_CMD_SIZE; // Initialize stlink version (sl->version) stlink_version(sl); From 99a8aaab253a1cda634291b6a975d1560bb89c0a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 10 Apr 2020 23:38:17 +0200 Subject: [PATCH 0802/1435] General Project Update - Updated CHANGELOG.md - README.md: Edited note on licensing. - Formatting in tutorial.md Temporarily removed travis-lin-mingw script for clean travis builds. --- .gitignore | 2 - .travis-lin-mingw.sh | 14 ------ CHANGELOG.md | 6 ++- README.md | 16 +++--- doc/tutorial.md | 115 ++++++++++++++++++++++--------------------- 5 files changed, 71 insertions(+), 82 deletions(-) delete mode 100755 .travis-lin-mingw.sh diff --git a/.gitignore b/.gitignore index d2dde3a25..23e7ddc07 100644 --- a/.gitignore +++ b/.gitignore @@ -2,5 +2,3 @@ build build-mingw obj-* *.user* - -.travis-lin-mingw.sh diff --git a/.travis-lin-mingw.sh b/.travis-lin-mingw.sh deleted file mode 100755 index 0422a06f6..000000000 --- a/.travis-lin-mingw.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash - -DIR=$PWD - -if [ "$TRAVIS_OS_NAME" == "linux" ]; then - echo "WORK DIR:$DIR" - mkdir -p $DIR/build/linux-mingw32-release - cd $DIR/build/linux-mingw32-release - echo "cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR" - cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR - echo "make" - make -fi - diff --git a/CHANGELOG.md b/CHANGELOG.md index 1401843a9..9e31aaf47 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -20,6 +20,7 @@ Major changes and added features: * Build for Windows under Debian/Ubuntu ([#802](https://github.com/texane/stlink/pull/802)) * Allow for 64 bytes serials ([#809](https://github.com/texane/stlink/pull/809)) * Added full support for STLINK CHIP ID L4RX ([#814](https://github.com/texane/stlink/pull/814), [#839](https://github.com/texane/stlink/pull/839)) +* Added support for the STLink-v2.1 when flashed with no mass storage (PID 0x3752) ([#819](https://github.com/texane/stlink/pull/819), [#861](https://github.com/texane/stlink/pull/861)) * Added support for writing option bytes on STM32L0xx ([#830](https://github.com/texane/stlink/pull/830)) * Added support to read and write option bytes for STM32F2 series ([#836](https://github.com/texane/stlink/pull/836), [#837](https://github.com/texane/stlink/pull/837)) * Added support to read and write option bytes for STM32F446 ([#843](https://github.com/texane/stlink/pull/843)) @@ -65,7 +66,7 @@ Major changes and added features: * Added creation of icons for .desktop file ([#684](https://github.com/texane/stlink/pull/684), [#708](https://github.com/texane/stlink/pull/708)) * Added desktop file for linux ([#688](https://github.com/texane/stlink/pull/688)) * Added button to export STM32 flash memory to a file ([#691](https://github.com/texane/stlink/pull/691)) -* Updated libusb to 1.0.22 ([#695](https://github.com/texane/stlink/pull/695)) +* Updated libusb to 1.0.22 ([#695](https://github.com/texane/stlink/pull/695)) - (related Bugs: [#438](https://github.com/texane/stlink/pull/438), [#632](https://github.com/texane/stlink/pull/632)) * Added icons for STLink GUI ([#697](https://github.com/texane/stlink/pull/697)) * Added support for STM32L4R9 target ([#694](https://github.com/texane/stlink/pull/694), [#699](https://github.com/texane/stlink/pull/699)) * Added memory map for STM32F411RE target ([#709](https://github.com/texane/stlink/pull/709)) @@ -132,7 +133,7 @@ Updates and fixes: * Added --flash=n[k][m] command line option to override device model ([#305](https://github.com/texane/stlink/pull/305), [#516](https://github.com/texane/stlink/pull/516), [#576](https://github.com/texane/stlink/pull/576)) * Updated libusb to 1.0.21 for Windows ([#562](https://github.com/texane/stlink/pull/562)) * Fixed low-voltage flashing on STM32F7 devices ([#566](https://github.com/texane/stlink/pull/566), [#567](https://github.com/texane/stlink/pull/567)) -* Fixed building with mingw64 ([#569](https://github.com/texane/stlink/pull/569), [#573](https://github.com/texane/stlink/pull/573), [#578](https://github.com/texane/stlink/pull/578), [#584](https://github.com/texane/stlink/pull/584), [#610](https://github.com/texane/stlink/pull/610)) +* Fixed building with mingw64 ([#569](https://github.com/texane/stlink/pull/569), [#573](https://github.com/texane/stlink/pull/573), [#578](https://github.com/texane/stlink/pull/578), [#582](https://github.com/texane/stlink/pull/582), [#584](https://github.com/texane/stlink/pull/584), [#610](https://github.com/texane/stlink/pull/610), [#846](https://github.com/texane/stlink/pull/846)) * Fixed possible memory leak ([#570](https://github.com/texane/stlink/pull/570), [#571](https://github.com/texane/stlink/pull/571)) * Fixed installation path for shared objects ([#581](https://github.com/texane/stlink/pull/581)) * Fixed a few -Wformat warnings ([#582](https://github.com/texane/stlink/pull/582)) @@ -246,6 +247,7 @@ Updates and fixes: * Stm32l0x flash loader (Robin Kreis) * Send F4 memory-map and features for STM32F429 ([#188](https://github.com/texane/stlink/pull/188), [#196](https://github.com/texane/stlink/pull/196), [#250](https://github.com/texane/stlink/pull/250), [#251](https://github.com/texane/stlink/pull/251)) (Release v1.1.0) * Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/texane/stlink/pull/218), [#288](https://github.com/texane/stlink/pull/288)) (Release v1.1.0) +* Corrected flash size register address for STM32F2 devices ([#278](https://github.com/texane/stlink/pull/278)) (Release v1.0.0) Chip support added for: diff --git a/README.md b/README.md index 4b1195166..e6de34dab 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -Open source version of the STMicroelectronics Stlink Tools +Open source version of the STMicroelectronics STlink Tools ========================================================== [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) @@ -11,6 +11,13 @@ Open source version of the STMicroelectronics Stlink Tools Recent new features and bugfixes can be found in the [Changelog](CHANGELOG.md) of this software project. +#### License + +The stlink library and tools are licensed under the **[BSD-3 License](LICENSE.md)**.
    +The source files **stm32l0x.s** and **stm32lx.s** found in the subdirectory `/flashloaders/` +are licensed under the **General Public License (GPL v2+)**. + + ## Introduction This stlink toolset supports several so called stlink programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG. @@ -89,13 +96,6 @@ When there is no executable available for your platform or you need the latest ( * Please start new forks from the develop branch if possible as pull requests will go into this branch as well. -## License - -The stlink library and tools are licensed under the [BSD-3 license](LICENSE.md). - -The flashloaders/stm32l0x.s and flashloaders/stm32lx.s source files are licensed under the GPLv2+. - - # Current state of the project ## Known missing features diff --git a/doc/tutorial.md b/doc/tutorial.md index 9c1f7f26d..66bed0382 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -2,6 +2,7 @@ stlink Tools Tutorial ===================== ## Useful tool options + ### st-flash #### --flash=n[k][m] @@ -14,8 +15,8 @@ Obviously leaving the multiplier out is equally valid, for example: `--flash=0x2 The size may be followed by an optional "k" or "m" to multiply the given value by 1k (1024) or 1M respectively. -## Solution to common problems -### ST-Link-v1 driver: Issue with Kernel Extension (kext) (macOS 10.11 and later only) +## Solutions to common problems +### a) ST-Link-v1 driver: Issue with Kernel Extension (kext) (macOS 10.11 and later only) #### Problem: st-util fails to detect a ST-Link-v1 device: @@ -39,11 +40,13 @@ while SIP is fully activated (as is per default). Action needs to be taken here by booting into the recovery mode where a terminal console window needs to be opened. -Here it is **NOT RECOMMEND to disable SIP completely as with the command** `csrutil disable`, -**because this leaves the system more vulnerable to common threats. +For macOS 10.11 - 10.13 it is not recommended to disable SIP completely as with the command `csrutil disable`, +because this leaves the system more vulnerable to common threats. Instead there is a more adequate and reasonable option implemented by Apple. -Running** `csrutil enable --without kext`, **allows to load unsigned kernel extensions -while leaving SIP active with all other security features.** +Running `csrutil enable --without kext`, allows to load unsigned kernel extensions +while leaving SIP active with all other security features. +Unfortunately this option has been removed in macOS 10.14, which leaves the only option to disable SIP completely. + So who ever intends to run the ST-Link-v1 programmer on macOS please take this into account. Further details can be found here: https://forums.developer.apple.com/thread/17452 @@ -76,8 +79,56 @@ INFO gdb-server.c: Chip ID is 00000414, Core ID is 1ba01477. INFO gdb-server.c: Listening at *:4242... ``` +### b) Verify if udev rules are set correctly (by Dave Hylands) + +To investigate, start by plugging your STLINK device into the usb port. Then run lsusb. You should see an entry something like the following: + +``` +Bus 005 Device 017: ID 0483:374b STMicroelectronics ST-LINK/V2.1 (Nucleo-F103RB) +``` + +Note the bus number (005) and the Device (017). You should then do: +`ls -l /dev/bus/usb/005/017` (replacing 005 and 017 appropriately). + +On my system I see the following: + +``` +crw-rw-rw- 1 root root 189, 528 Jan 24 17:52 /dev/bus/usb/005/017 +``` + +which is world writable (this is from the MODE:="0666" below). I have several files in my `/etc/udev/rules.d` directory. In this particular case, the `49-stlinkv2-1.rules` file contains the following: + +``` +# stm32 nucleo boards, with onboard st/linkv2-1 +# ie, STM32F0, STM32F4. +# STM32VL has st/linkv1, which is quite different + +SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ + MODE:="0666", \ + SYMLINK+="stlinkv2-1_%n" + +# If you share your linux system with other users, or just don't like the +# idea of write permission for everybody, you can replace MODE:="0666" with +# OWNER:="yourusername" to create the device owned by you, or with +# GROUP:="somegroupname" and mange access using standard unix groups. +``` + +and the idVendor of 0483 and idProduct of 374b matches the vendor id from the lsusb output. + +Make sure that you have all 3 files from here: https://github.com/texane/stlink/tree/master/etc/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing excisting files in `/etc/udev/ruled.d` you should run the following: + +``` +sudo udevadm control --reload-rules +sudo udevadm trigger +``` + +to ensure that the rules actually take effect. Using the trigger command means that you shouldn't need to unplug and replug the device, but you might want to try that for good measure as well. + +If the VID:PID of your device doesn't match those in any of the 3 files, then you may need to create a custom rule file to match your VID:PID. + ------ +( Content below is currently unrevised and may be outdated as of Apr 2020. ) Using STM32 discovery kits with open source tools ======== @@ -249,56 +300,8 @@ $> [sudo] ./st-flash write fancy_blink.bin 0x08000000 Upon reset, the board LEDs should be blinking. -HOWTO -===== - -## Verify if udev rules are set correctly (by Dave Hylands) - -To investigate, start by plugging your STLINK device into the usb port. Then run lsusb. You should see an entry something like the following: - -``` -Bus 005 Device 017: ID 0483:374b STMicroelectronics ST-LINK/V2.1 (Nucleo-F103RB) -``` - -Note the bus number (005) and the Device (017). You should then do: -`ls -l /dev/bus/usb/005/017` (replacing 005 and 017 appropriately). - -On my system I see the following: - -``` -crw-rw-rw- 1 root root 189, 528 Jan 24 17:52 /dev/bus/usb/005/017 -``` - -which is world writable (this is from the MODE:="0666" below). I have several files in my `/etc/udev/rules.d` directory. In this particular case, the `49-stlinkv2-1.rules` file contains the following: - -``` -# stm32 nucleo boards, with onboard st/linkv2-1 -# ie, STM32F0, STM32F4. -# STM32VL has st/linkv1, which is quite different - -SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ - MODE:="0666", \ - SYMLINK+="stlinkv2-1_%n" - -# If you share your linux system with other users, or just don't like the -# idea of write permission for everybody, you can replace MODE:="0666" with -# OWNER:="yourusername" to create the device owned by you, or with -# GROUP:="somegroupname" and mange access using standard unix groups. -``` - -and the idVendor of 0483 and idProduct of 374b matches the vendor id from the lsusb output. - -Make sure that you have all 3 files from here: https://github.com/texane/stlink/tree/master/etc/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing excisting files in `/etc/udev/ruled.d` you should run the following: - -``` -sudo udevadm control --reload-rules -sudo udevadm trigger -``` - -to ensure that the rules actually take effect. Using the trigger command means that you shouldn't need to unplug and replug the device, but you might want to try that for good measure as well. - -If the VID:PID of your device doesn't match those in any of the 3 files, then you may need to create a custom rule file to match your VID:PID. - +HOWTO (old) +=========== ## Using the gdb server From 7e4540aa7ddf478fca44aad140c3af04bfbaee5a Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Sat, 11 Apr 2020 12:11:08 +0800 Subject: [PATCH 0803/1435] Fix code style alignment --- src/tools/flash_opts.c | 48 +++++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index ef41601a5..a6633d973 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -93,30 +93,30 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { else return -1; } - else if ( starts_with(av[0], "--flash=") ) { - const char *arg = av[0] + strlen("--flash="); - char *ep = 0; - - o->flash_size = (uint32_t)strtoul(arg,&ep,0); - while ( *ep ) { - switch ( *ep++ ) { - case 0: - break; - case 'k': - case 'K': - o->flash_size *= 1024u; - break; - case 'm': - case 'M': - o->flash_size *= 1024u * 1024u; - break; - default: - fprintf(stderr,"Invalid --flash=%s\n",arg); - return -1; - } - } - } - else { + else if ( starts_with(av[0], "--flash=") ) { + const char *arg = av[0] + strlen("--flash="); + char *ep = 0; + + o->flash_size = (uint32_t)strtoul(arg,&ep,0); + while ( *ep ) { + switch ( *ep++ ) { + case 0: + break; + case 'k': + case 'K': + o->flash_size *= 1024u; + break; + case 'm': + case 'M': + o->flash_size *= 1024u * 1024u; + break; + default: + fprintf(stderr,"Invalid --flash=%s\n",arg); + return -1; + } + } + } + else { break; // non-option found } From cc27e61e9d5bd45e3d9d78f972649bec01f26707 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Sat, 11 Apr 2020 13:46:59 +0800 Subject: [PATCH 0804/1435] Fix 0xFF optimization bug --- include/stlink.h | 1 + include/stlink/tools/flash.h | 4 ++- src/common.c | 56 ++++++++++++++++++++++++------------ src/tools/flash.c | 5 ++-- src/tools/flash_opts.c | 3 ++ 5 files changed, 47 insertions(+), 22 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index 94e980435..508b50f7d 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -151,6 +151,7 @@ typedef struct flash_loader { // transport layer verboseness: 0 for no debug info, 10 for lots int verbose; + int opt; uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram int core_stat; // set by stlink_status(), values STLINK_CORE_xxxxx diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index a73d7aee4..659c17f28 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -6,6 +6,7 @@ #define DEBUG_LOG_LEVEL 100 #define STND_LOG_LEVEL 50 +#define ENABLE_OPT 1 enum flash_cmd {FLASH_CMD_NONE = 0, FLASH_CMD_WRITE = 1, FLASH_CMD_READ = 2, FLASH_CMD_ERASE = 3, CMD_RESET = 4}; enum flash_format {FLASH_FORMAT_BINARY = 0, FLASH_FORMAT_IHEX = 1}; @@ -24,9 +25,10 @@ struct flash_opts enum flash_area area; uint32_t val; size_t flash_size; /* --flash=n[k][m] */ + int opt; }; -#define FLASH_OPTS_INITIALIZER {0, NULL, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0 } +#define FLASH_OPTS_INITIALIZER {0, NULL, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0} int flash_get_opts(struct flash_opts* o, int ac, char** av); diff --git a/src/common.c b/src/common.c index f432cf5a1..c5506c061 100644 --- a/src/common.c +++ b/src/common.c @@ -2621,17 +2621,30 @@ int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr unsigned int num_empty, idx; uint8_t erased_pattern = stlink_get_erased_pattern(sl); - idx = (unsigned int)length; - for(num_empty = 0; num_empty != length; ++num_empty) { - if (data[--idx] != erased_pattern) { - break; + /* + * This optimization may cause unexpected garbage data remaining + * Turned off by default + */ + if (sl->opt) { + idx = (unsigned int)length; + for(num_empty = 0; num_empty != length; ++num_empty) { + if (data[--idx] != erased_pattern) { + break; + } } + /* Round down to words */ + num_empty -= (num_empty & 3); + if(num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); + } + } else { + num_empty = 0; } - /* Round down to words */ - num_empty -= (num_empty & 3); - if(num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); - } + /* + * a kind of weird behaviour here: + * if the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed + */ err = stlink_write_flash(sl, addr, data, (num_empty == length) ? (uint32_t) length : (uint32_t) length - num_empty, num_empty == length); stlink_fwrite_finalize(sl, addr); return err; @@ -2655,18 +2668,23 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { ELOG("map_file() == -1\n"); return -1; } - - idx = (unsigned int) mf.len; - for(num_empty = 0; num_empty != mf.len; ++num_empty) { - if (mf.base[--idx] != erased_pattern) { - break; + + if (sl->opt) { + idx = (unsigned int) mf.len; + for(num_empty = 0; num_empty != mf.len; ++num_empty) { + if (mf.base[--idx] != erased_pattern) { + break; + } } + /* Round down to words */ + num_empty -= (num_empty & 3); + if(num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); + } + } else { + num_empty = 0; } - /* Round down to words */ - num_empty -= (num_empty & 3); - if(num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); - } + err = stlink_write_flash(sl, addr, mf.base, (num_empty == mf.len) ? (uint32_t) mf.len : (uint32_t) mf.len - num_empty, num_empty == mf.len); stlink_fwrite_finalize(sl, addr); unmap_file(&mf); diff --git a/src/tools/flash.c b/src/tools/flash.c index e1e9f41f6..67e03c62b 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -29,9 +29,9 @@ static void cleanup(int signum) { static void usage(void) { - puts("stlinkv1 command line: ./st-flash [--debug] [--reset] [--format ] [--flash=] {read|write} /dev/sgX "); + puts("stlinkv1 command line: ./st-flash [--debug] [--reset] [--opt] [--format ] [--flash=] {read|write} /dev/sgX "); puts("stlinkv1 command line: ./st-flash [--debug] /dev/sgX erase"); - puts("stlinkv2/3 command line: ./st-flash [--debug] [--reset] [--serial ] [--format ] [--flash=] {read|write} "); + puts("stlinkv2/3 command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] {read|write} "); puts("stlinkv2/3 command line: ./st-flash [--debug] [--serial ] erase"); puts("stlinkv2/3 command line: ./st-flash [--debug] [--serial ] reset"); puts(" , and : Use hex format."); @@ -73,6 +73,7 @@ int main(int ac, char** av) } sl->verbose = o.log_level; + sl->opt = o.opt; connected_stlink = sl; signal(SIGINT, &cleanup); diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index a6633d973..d409603f9 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -27,6 +27,9 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { else if (strcmp(av[0], "--debug") == 0) { o->log_level = DEBUG_LOG_LEVEL; } + else if (strcmp(av[0], "--opt") == 0) { + o->opt = ENABLE_OPT; + } else if (strcmp(av[0], "--reset") == 0) { o->reset = 1; } From e97eaa329a43dde694851cf27b55aa3891f9e85e Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Sat, 11 Apr 2020 14:06:38 +0800 Subject: [PATCH 0805/1435] Add man documentation about --opt --- doc/man/st-flash.1 | 39 +++++++++++++++++++++------------------ doc/man/st-flash.md | 3 +++ 2 files changed, 24 insertions(+), 18 deletions(-) diff --git a/doc/man/st-flash.1 b/doc/man/st-flash.1 index 36df7daa8..c2654f280 100644 --- a/doc/man/st-flash.1 +++ b/doc/man/st-flash.1 @@ -1,52 +1,55 @@ -.\" Automatically generated by Pandoc 2.4 +.\" Automatically generated by Pandoc 2.9 .\" -.TH "st\-flash" "1" "Feb 2018" "Open Source STMicroelectronics Stlink Tools" "stlink" +.TH "st-flash" "1" "Feb 2018" "Open Source STMicroelectronics Stlink Tools" "stlink" .hy .SH NAME .PP -st\-flash \- Flash binary files to STM32 device +st-flash - Flash binary files to STM32 device .SH SYNOPSIS .PP -\f[I]st\-flash\f[R] [\f[I]OPTIONS\f[R]] {read|write|erase} +\f[I]st-flash\f[R] [\f[I]OPTIONS\f[R]] {read|write|erase} [\f[I]FILE\f[R]] .SH DESCRIPTION .PP Flash binary files to arbitrary sections of memory, or read arbitrary addresses of memory out to a binary file. .PP -You can use this instead of st\-util(1) if you prefer, but remember to +You can use this instead of st-util(1) if you prefer, but remember to use the \f[B].bin\f[R] image, rather than the \f[B].elf\f[R] file. .PP Use hexadecimal format for the \f[I]ADDR\f[R] and \f[I]SIZE\f[R]. .SH COMMANDS .TP -.B write \f[I]FILE\f[R] \f[I]ADDR\f[R] +write \f[I]FILE\f[R] \f[I]ADDR\f[R] Write firmware \f[I]FILE\f[R] to device starting from \f[I]ADDR\f[R] .TP -.B read \f[I]FILE\f[R] \f[I]ADDR\f[R] \f[I]SIZE\f[R] +read \f[I]FILE\f[R] \f[I]ADDR\f[R] \f[I]SIZE\f[R] Read firmware from device starting from \f[I]ADDR\f[R] up to \f[I]SIZE\f[R] bytes to \f[I]FILE\f[R] .TP -.B erase +erase Perform a mass erasing of the device firmware .TP -.B reset +reset Reset the target .SH OPTIONS .TP -.B \-\-version +--version Print version information .TP -.B \-\-debug +--debug TODO .TP -.B \-\-reset +--reset TODO .TP -.B \-\-serial \f[I]iSerial\f[R] +--opt +Enable ignore ending empty bytes optimization +.TP +--serial \f[I]iSerial\f[R] TODO .TP -.B \-\-flash=fsize +--flash=fsize Where fsize is the size in decimal, octal, or hex followed by an optional multiplier `k' for KB, or `m' for MB. Use a leading \[lq]0x\[rq] to specify hexadecimal, or a leading zero for @@ -57,7 +60,7 @@ Flash \f[C]firmware.bin\f[R] to device .IP .nf \f[C] -$ st\-flash write firmware.bin 0x8000000 +$ st-flash write firmware.bin 0x8000000 \f[R] .fi .PP @@ -65,7 +68,7 @@ Read firmware from device (4096 bytes) .IP .nf \f[C] -$ st\-flash read firmware.bin 0x8000000 0x1000 +$ st-flash read firmware.bin 0x8000000 0x1000 \f[R] .fi .PP @@ -73,12 +76,12 @@ Erase firmware from device .IP .nf \f[C] -$ st\-flash erase +$ st-flash erase \f[R] .fi .SH SEE ALSO .PP -st\-util(1), st\-info(1) +st-util(1), st-info(1) .SH COPYRIGHT .PP This work is copyrighted. diff --git a/doc/man/st-flash.md b/doc/man/st-flash.md index 1860a8c72..b787e8dd7 100644 --- a/doc/man/st-flash.md +++ b/doc/man/st-flash.md @@ -45,6 +45,9 @@ reset \--reset : TODO +\--opt +: Enable ignore ending empty bytes optimization + \--serial *iSerial* : TODO From 12637a47f52a6595417b672963bf47cbe026b272 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Sat, 11 Apr 2020 16:44:25 +0800 Subject: [PATCH 0806/1435] Indent with four spaces --- .travis-lin-mingw.sh | 14 ------------ src/tools/flash_opts.c | 48 +++++++++++++++++++++--------------------- 2 files changed, 24 insertions(+), 38 deletions(-) delete mode 100755 .travis-lin-mingw.sh diff --git a/.travis-lin-mingw.sh b/.travis-lin-mingw.sh deleted file mode 100755 index 0422a06f6..000000000 --- a/.travis-lin-mingw.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash - -DIR=$PWD - -if [ "$TRAVIS_OS_NAME" == "linux" ]; then - echo "WORK DIR:$DIR" - mkdir -p $DIR/build/linux-mingw32-release - cd $DIR/build/linux-mingw32-release - echo "cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR" - cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR - echo "make" - make -fi - diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index d409603f9..a24bde1be 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -96,30 +96,30 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { else return -1; } - else if ( starts_with(av[0], "--flash=") ) { - const char *arg = av[0] + strlen("--flash="); - char *ep = 0; - - o->flash_size = (uint32_t)strtoul(arg,&ep,0); - while ( *ep ) { - switch ( *ep++ ) { - case 0: - break; - case 'k': - case 'K': - o->flash_size *= 1024u; - break; - case 'm': - case 'M': - o->flash_size *= 1024u * 1024u; - break; - default: - fprintf(stderr,"Invalid --flash=%s\n",arg); - return -1; - } - } - } - else { + else if ( starts_with(av[0], "--flash=") ) { + const char *arg = av[0] + strlen("--flash="); + char *ep = 0; + + o->flash_size = (uint32_t)strtoul(arg,&ep,0); + while ( *ep ) { + switch ( *ep++ ) { + case 0: + break; + case 'k': + case 'K': + o->flash_size *= 1024u; + break; + case 'm': + case 'M': + o->flash_size *= 1024u * 1024u; + break; + default: + fprintf(stderr,"Invalid --flash=%s\n",arg); + return -1; + } + } + } + else { break; // non-option found } From 11156bc66b7b3473654def392cccca9f0c3222d7 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Sat, 11 Apr 2020 20:02:03 +0800 Subject: [PATCH 0807/1435] Add TODO tag in source code --- src/common.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index c5506c061..af9a87a8a 100644 --- a/src/common.c +++ b/src/common.c @@ -2641,6 +2641,7 @@ int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr num_empty = 0; } /* + * TODO: investigate: * a kind of weird behaviour here: * if the file is identified to be all-empty and four-bytes aligned, * still flash the whole file even if ignoring message is printed @@ -2684,7 +2685,12 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { } else { num_empty = 0; } - + /* + * TODO: investigate: + * a kind of weird behaviour here: + * if the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed + */ err = stlink_write_flash(sl, addr, mf.base, (num_empty == mf.len) ? (uint32_t) mf.len : (uint32_t) mf.len - num_empty, num_empty == mf.len); stlink_fwrite_finalize(sl, addr); unmap_file(&mf); From 734bfdaa4754d6a6dd9ac974670ec7c0b9096347 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Sat, 11 Apr 2020 20:24:08 +0800 Subject: [PATCH 0808/1435] Remove .travis-lin-mingw.sh in travis.yml --- .travis.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/.travis.yml b/.travis.yml index b1832d57f..d88bf1036 100644 --- a/.travis.yml +++ b/.travis.yml @@ -26,4 +26,3 @@ script: - printenv - cmake --version - ./.travis.sh - - ./.travis-lin-mingw.sh From 2979df40480be52678f41e20c3ed1893888ea0dc Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Sat, 11 Apr 2020 22:24:33 +0800 Subject: [PATCH 0809/1435] Fix 32 bit build on develop branch --- src/common.c | 22 +++++++++++----------- src/gdbserver/gdb-server.c | 2 +- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/common.c b/src/common.c index af9a87a8a..b44c1e692 100644 --- a/src/common.c +++ b/src/common.c @@ -190,10 +190,10 @@ #define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ // Bits requesting flash operations (useful when we want to clear them) #define STM32L4_FLASH_CR_OPBITS \ - ((1lu<chip_id == STLINK_CHIPID_STM32_L496X || sl->chip_id == STLINK_CHIPID_STM32_L4RX) { // This chip use dual banked flash - if (flashopt & (1lu << STM32L4_FLASH_OPTR_DUALBANK)) { + if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { uint32_t banksize = (uint32_t) sl->flash_size / 2; if (flashaddr >= banksize) { flashaddr -= banksize; @@ -1731,7 +1731,7 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { // For 1MB chips without the dual-bank option set, the page address will // overflow into the BKER bit, which gives us the correct bank:page value. - return bker | flashaddr/sl->flash_pgsz; + return bker | flashaddr/(uint32_t)sl->flash_pgsz; } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ @@ -1907,7 +1907,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) // Set the page to erase. if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); // sec 3.10.5 - PNB[7:0] is offset by 3. @@ -1916,14 +1916,14 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_write_debug32(sl, STM32WB_FLASH_CR, val); } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { - uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. val &= ~(0x3F << 3); val |= ((flash_page & 0x3F) << 3) | ( 1 << FLASH_CR_PER ); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { - uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. val &= ~(0x7F << 3); @@ -2000,7 +2000,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_WB) { /* erase each page */ - int i = 0, num_pages = (int) sl->flash_size/sl->flash_pgsz; + int i = 0, num_pages = (int)(sl->flash_size/sl->flash_pgsz); for (i = 0; i < num_pages; i++) { /* addr must be an addr inside the page */ stm32_addr_t addr = (stm32_addr_t) sl->flash_base + i * (stm32_addr_t) sl->flash_pgsz; diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 3aa769e02..9cff5f917 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -862,7 +862,7 @@ static int flash_go(stlink_t *sl) { for(struct flash_block* fb = flash_root; fb; fb = fb->next) { DLOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length); - for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += FLASH_PAGE) { + for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += (uint32_t)FLASH_PAGE) { unsigned length = fb->length - (page - fb->addr); //Update FLASH_PAGE From 067639ff8cb6fb23a00c9122822e542560f9a4ee Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Sun, 12 Apr 2020 21:02:42 +0800 Subject: [PATCH 0810/1435] Enhance error log with file path for map_file() --- src/common.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/common.c b/src/common.c index b44c1e692..813151f67 100644 --- a/src/common.c +++ b/src/common.c @@ -1302,19 +1302,19 @@ static int map_file(mapped_file_t* mf, const char* path) { } if (fstat(fd, &st) == -1) { - fprintf(stderr, "fstat() == -1\n"); + fprintf(stderr, "fstat(%s) == -1\n", path); goto on_error; } if (sizeof(st.st_size) != sizeof(size_t)) { /* On 32 bit systems, check if there is an overflow */ if (st.st_size > (off_t)UINT32_MAX) { - fprintf(stderr, "mmap() size_t overflow\n"); + fprintf(stderr, "mmap() size_t overflow for file %s\n", path); goto on_error; } } mf->base = (uint8_t*) mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); if (mf->base == MAP_FAILED) { - fprintf(stderr, "mmap() == MAP_FAILED\n"); + fprintf(stderr, "mmap() == MAP_FAILED for file %s\n", path); goto on_error; } From cadfa941621cef85205622d6af0f87648d2a31c7 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 12 Apr 2020 18:26:46 +0200 Subject: [PATCH 0811/1435] General Project Update - Updated travis CI build configuration - Updated project references - Minor formatting fixes --- .travis.yml | 109 ++++++++++++++++++++++++++++++++------- CMakeLists.txt | 18 ++++--- README.md | 10 ++-- cmake/cpack_config.cmake | 3 +- 4 files changed, 106 insertions(+), 34 deletions(-) diff --git a/.travis.yml b/.travis.yml index d88bf1036..079888765 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,25 +1,96 @@ - -compiler: - - gcc - - clang - language: c -os: - - linux - - osx +matrix: + include: + ### 64-bit builds ### + - os: linux + arch: x64 + compiler: gcc-5 + addons: + apt: + sources: ['ubuntu-toolchain-r-test'] + packages: ['gcc-5', 'libusb-1.0.0-dev'] + - os: linux + arch: x64 + compiler: gcc-7 + addons: + apt: + sources: ['ubuntu-toolchain-r-test'] + packages: ['gcc-7', 'libusb-1.0.0-dev'] + - os: linux + arch: x64 + compiler: gcc-9 + addons: + apt: + sources: ['ubuntu-toolchain-r-test'] + packages: ['gcc-9', 'libusb-1.0.0-dev'] + - os: linux + arch: x64 + compiler: clang-3.7 + addons: + apt: + sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-xenial-3.7'] + packages: ['clang-3.7', 'libusb-1.0.0-dev'] + - os: linux + arch: x64 + compiler: clang-6.0 + addons: + apt: + sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] + packages: ['clang-6.0', 'libusb-1.0.0-dev'] + + ### 32-bit builds ### + - os: linux + arch: x86 + compiler: gcc-5 + addons: + apt: + sources: ['ubuntu-toolchain-r-test'] + packages: ['gcc-5', 'libusb-1.0.0-dev'] + - os: linux + arch: x86 + compiler: gcc-6 + addons: + apt: + sources: ['ubuntu-toolchain-r-test'] + packages: ['gcc-6', 'libusb-1.0.0-dev'] + - os: linux + arch: x86 + compiler: gcc-7 + addons: + apt: + sources: ['ubuntu-toolchain-r-test'] + packages: ['gcc-7', 'libusb-1.0.0-dev'] + - os: linux + arch: x86 + compiler: clang-3.7 + addons: + apt: + sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-xenial-3.7'] + packages: ['clang-3.7', 'libusb-1.0.0-dev'] + - os: linux + arch: x86 + compiler: clang-6.0 + addons: + apt: + sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] + packages: ['clang-6.0', 'libusb-1.0.0-dev'] -addons: - apt: - sources: - - sourceline: 'ppa:ubuntu-toolchain-r/test' - packages: - - clang - - g++-6 - - gcc-6 - - libusb-1.0.0-dev - - p7zip - - mingw-w64 + ### macOS ### + - os: osx + compiler: gcc + addons: + homebrew: + packages: + - libusb + - gcc + - os: osx + compiler: clang + addons: + homebrew: + packages: + - libusb + - clang script: - git fetch --tags diff --git a/CMakeLists.txt b/CMakeLists.txt index 1f0b46449..8a282f550 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -17,12 +17,12 @@ if (IS_DIRECTORY ${LIB_INSTALL_DIR}) set(STLINK_LIBRARY_PATH "${LIB_INSTALL_DIR}") else () set(LIB_INSTALL_DIR "lib" CACHE PATH "Main library directory") - set(STLINK_LIBRARY_PATH "${CMAKE_INSTALL_PREFIX}/${LIB_INSTALL_DIR}" ) + set(STLINK_LIBRARY_PATH "${CMAKE_INSTALL_PREFIX}/${LIB_INSTALL_DIR}") endif () if (IS_DIRECTORY ${INCLUDE_INSTALL_DIR}) set(INCLUDE_INSTALL_DIR ${INCLUDE_INSTALL_DIR} CACHE PATH "Main include directory") - set(STLINK_INCLUDE_PATH "${INCLUDE_INSTALL_DIR}" ) + set(STLINK_INCLUDE_PATH "${INCLUDE_INSTALL_DIR}") else () set(INCLUDE_INSTALL_DIR "include" CACHE PATH "Main include directory") set(STLINK_INCLUDE_PATH "${CMAKE_INSTALL_PREFIX}/${INCLUDE_INSTALL_DIR}") @@ -148,7 +148,7 @@ set_target_properties( VERSION ${STLINK_SHARED_VERSION} ) -# Link shared library with apple OS libraries +# Link shared library with Apple macOS libraries if (APPLE) find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) @@ -178,9 +178,9 @@ add_library( ${STLINK_LIB_STATIC} STATIC ${STLINK_HEADERS} # header files for ide projects generated by cmake ${STLINK_SOURCE} -) + ) -# Link shared library with apple OS libraries +# Link shared library with Apple macOS libraries if (APPLE) find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) @@ -257,7 +257,9 @@ if (NOT TARGET uninstall) "${CMAKE_CURRENT_SOURCE_DIR}/cmake_uninstall.cmake.in" "${CMAKE_CURRENT_BINARY_DIR}/cmake_uninstall.cmake" IMMEDIATE @ONLY - ) - add_custom_target(uninstall - COMMAND ${CMAKE_COMMAND} -P ${CMAKE_CURRENT_BINARY_DIR}/cmake_uninstall.cmake) + ) + add_custom_target( + uninstall COMMAND ${CMAKE_COMMAND} + -P ${CMAKE_CURRENT_BINARY_DIR}/cmake_uninstall.cmake + ) endif () diff --git a/README.md b/README.md index e6de34dab..29d1ef766 100644 --- a/README.md +++ b/README.md @@ -2,11 +2,11 @@ Open source version of the STMicroelectronics STlink Tools ========================================================== [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) -[![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/texane/stlink/releases/latest) -[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/v1.6.0.svg)](https://github.com/texane/stlink/releases/master) -[![Downloads](https://img.shields.io/github/downloads/texane/stlink/total.svg)](https://github.com/texane/stlink/releases) -[![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/texane/stlink) -[![macOS Status](https://img.shields.io/travis/texane/stlink/master.svg?label=osx)](https://travis-ci.org/texane/stlink) +[![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/stlink-org/stlink/releases/latest) +[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/v1.6.0.svg)](https://github.com/stlink-org/stlink/releases/master) +[![Downloads](https://img.shields.io/github/downloads/texane/stlink/total.svg)](https://github.com/stlink-org/stlink/releases) +[![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/stlink-org/stlink) +[![macOS Status](https://img.shields.io/travis/texane/stlink/master.svg?label=osx)](https://travis-ci.org/stlink-org/stlink) Recent new features and bugfixes can be found in the [Changelog](CHANGELOG.md) of this software project. diff --git a/cmake/cpack_config.cmake b/cmake/cpack_config.cmake index 72a98a821..b8d4be186 100644 --- a/cmake/cpack_config.cmake +++ b/cmake/cpack_config.cmake @@ -16,12 +16,11 @@ elseif (WIN32) elseif (${CMAKE_SYSTEM_NAME} STREQUAL "Linux" AND EXISTS "/etc/debian_version") message(STATUS "Debian-based Linux OS detected") set(CPACK_GENERATOR "DEB") - if ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "x86_64") set(CPACK_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${PROJECT_VERSION}-amd64" ) endif() - set(CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/texane/stlink") + set(CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/stlink-org/stlink") set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Luca Boccassi") set(CPACK_PACKAGE_CONTACT "bluca@debian.org") set(CPACK_DEBIAN_PACKAGE_DESCRIPTION "STM32 STlink programmer tools") From 79676cdf793eedcfa210147098e621926d1cb222 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Mon, 13 Apr 2020 17:12:58 +0800 Subject: [PATCH 0812/1435] Add md5 checksum for binary file --- CMakeLists.txt | 1 + src/common.c | 23 +++- src/md5.c | 339 +++++++++++++++++++++++++++++++++++++++++++++++++ src/md5.h | 100 +++++++++++++++ 4 files changed, 462 insertions(+), 1 deletion(-) create mode 100755 src/md5.c create mode 100755 src/md5.h diff --git a/CMakeLists.txt b/CMakeLists.txt index 1f0b46449..7dd8c4d0c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -97,6 +97,7 @@ set(STLINK_SOURCE src/sg.c src/logging.c src/flash_loader.c + src/md5.c ) if (WIN32 OR MSYS OR MINGW) diff --git a/src/common.c b/src/common.c index 813151f67..43cec756d 100644 --- a/src/common.c +++ b/src/common.c @@ -15,6 +15,7 @@ #include "stlink.h" #include "stlink/mmap.h" #include "stlink/logging.h" +#include "md5.h" #ifndef O_BINARY #define O_BINARY 0 @@ -1365,6 +1366,20 @@ static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) { return 0; } +static void md5_calculate(mapped_file_t *mf, const char *path) { + /* calculate md5 checksum of given binary file */ + Md5Context md5Context; + MD5_HASH md5Hash; + Md5Initialise(&md5Context); + Md5Update(&md5Context, mf->base, (uint32_t)mf->len); + Md5Finalise(&md5Context, &md5Hash); + printf("file %s md5 checksum: ",path); + for(int i = 0; i < (int) sizeof(md5Hash); i++) { + printf("%x", md5Hash.bytes[i]); + } + printf("\n"); +} + static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { unsigned int val; /* set stack*/ @@ -1446,6 +1461,8 @@ int stlink_fwrite_sram(stlink_t * sl, const char* path, stm32_addr_t addr) { return -1; } + md5_calculate(&mf, path); + /* check addr range is inside the sram */ if (addr < sl->sram_base) { fprintf(stderr, "addr too low\n"); @@ -2669,7 +2686,9 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { ELOG("map_file() == -1\n"); return -1; } - + + md5_calculate(&mf, path); + if (sl->opt) { idx = (unsigned int) mf.len; for(num_empty = 0; num_empty != mf.len; ++num_empty) { @@ -3234,6 +3253,8 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr return -1; } + md5_calculate(&mf, path); + err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t) mf.len); stlink_fwrite_finalize(sl, addr); unmap_file(&mf); diff --git a/src/md5.c b/src/md5.c new file mode 100755 index 000000000..ff7d2d76e --- /dev/null +++ b/src/md5.c @@ -0,0 +1,339 @@ +/* + * Retrieved from https://github.com/WaterJuice/WjCryptLib + */ + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// WjCryptLib_Md5 +// +// Implementation of MD5 hash function. Originally written by Alexander Peslyak. Modified by WaterJuice retaining +// Public Domain license. +// +// This is free and unencumbered software released into the public domain - June 2013 waterjuice.org +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// IMPORTS +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#include "md5.h" +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// INTERNAL FUNCTIONS +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// F, G, H, I +// +// The basic MD5 functions. F and G are optimised compared to their RFC 1321 definitions for architectures that lack +// an AND-NOT instruction, just like in Colin Plumb's implementation. +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define F( x, y, z ) ( (z) ^ ((x) & ((y) ^ (z))) ) +#define G( x, y, z ) ( (y) ^ ((z) & ((x) ^ (y))) ) +#define H( x, y, z ) ( (x) ^ (y) ^ (z) ) +#define I( x, y, z ) ( (y) ^ ((x) | ~(z)) ) + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// STEP +// +// The MD5 transformation for all four rounds. +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#define STEP( f, a, b, c, d, x, t, s ) \ + (a) += f((b), (c), (d)) + (x) + (t); \ + (a) = (((a) << (s)) | (((a) & 0xffffffff) >> (32 - (s)))); \ + (a) += (b); + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// TransformFunction +// +// This processes one or more 64-byte data blocks, but does NOT update the bit counters. There are no alignment +// requirements. +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static +void* + TransformFunction + ( + Md5Context* ctx, + void const* data, + uintmax_t size + ) +{ + uint8_t* ptr; + uint32_t a; + uint32_t b; + uint32_t c; + uint32_t d; + uint32_t saved_a; + uint32_t saved_b; + uint32_t saved_c; + uint32_t saved_d; + + #define GET(n) (ctx->block[(n)]) + #define SET(n) (ctx->block[(n)] = \ + ((uint32_t)ptr[(n)*4 + 0] << 0 ) \ + | ((uint32_t)ptr[(n)*4 + 1] << 8 ) \ + | ((uint32_t)ptr[(n)*4 + 2] << 16) \ + | ((uint32_t)ptr[(n)*4 + 3] << 24) ) + + ptr = (uint8_t*)data; + + a = ctx->a; + b = ctx->b; + c = ctx->c; + d = ctx->d; + + do + { + saved_a = a; + saved_b = b; + saved_c = c; + saved_d = d; + + // Round 1 + STEP( F, a, b, c, d, SET(0), 0xd76aa478, 7 ) + STEP( F, d, a, b, c, SET(1), 0xe8c7b756, 12 ) + STEP( F, c, d, a, b, SET(2), 0x242070db, 17 ) + STEP( F, b, c, d, a, SET(3), 0xc1bdceee, 22 ) + STEP( F, a, b, c, d, SET(4), 0xf57c0faf, 7 ) + STEP( F, d, a, b, c, SET(5), 0x4787c62a, 12 ) + STEP( F, c, d, a, b, SET(6), 0xa8304613, 17 ) + STEP( F, b, c, d, a, SET(7), 0xfd469501, 22 ) + STEP( F, a, b, c, d, SET(8 ), 0x698098d8, 7 ) + STEP( F, d, a, b, c, SET(9 ), 0x8b44f7af, 12 ) + STEP( F, c, d, a, b, SET(10 ), 0xffff5bb1, 17 ) + STEP( F, b, c, d, a, SET(11 ), 0x895cd7be, 22 ) + STEP( F, a, b, c, d, SET(12 ), 0x6b901122, 7 ) + STEP( F, d, a, b, c, SET(13 ), 0xfd987193, 12 ) + STEP( F, c, d, a, b, SET(14 ), 0xa679438e, 17 ) + STEP( F, b, c, d, a, SET(15 ), 0x49b40821, 22 ) + + // Round 2 + STEP( G, a, b, c, d, GET(1), 0xf61e2562, 5 ) + STEP( G, d, a, b, c, GET(6), 0xc040b340, 9 ) + STEP( G, c, d, a, b, GET(11), 0x265e5a51, 14 ) + STEP( G, b, c, d, a, GET(0), 0xe9b6c7aa, 20 ) + STEP( G, a, b, c, d, GET(5), 0xd62f105d, 5 ) + STEP( G, d, a, b, c, GET(10), 0x02441453, 9 ) + STEP( G, c, d, a, b, GET(15), 0xd8a1e681, 14 ) + STEP( G, b, c, d, a, GET(4), 0xe7d3fbc8, 20 ) + STEP( G, a, b, c, d, GET(9), 0x21e1cde6, 5 ) + STEP( G, d, a, b, c, GET(14), 0xc33707d6, 9 ) + STEP( G, c, d, a, b, GET(3), 0xf4d50d87, 14 ) + STEP( G, b, c, d, a, GET(8), 0x455a14ed, 20 ) + STEP( G, a, b, c, d, GET(13), 0xa9e3e905, 5 ) + STEP( G, d, a, b, c, GET(2), 0xfcefa3f8, 9 ) + STEP( G, c, d, a, b, GET(7), 0x676f02d9, 14 ) + STEP( G, b, c, d, a, GET(12), 0x8d2a4c8a, 20 ) + + // Round 3 + STEP( H, a, b, c, d, GET(5), 0xfffa3942, 4 ) + STEP( H, d, a, b, c, GET(8), 0x8771f681, 11 ) + STEP( H, c, d, a, b, GET(11), 0x6d9d6122, 16 ) + STEP( H, b, c, d, a, GET(14), 0xfde5380c, 23 ) + STEP( H, a, b, c, d, GET(1), 0xa4beea44, 4 ) + STEP( H, d, a, b, c, GET(4), 0x4bdecfa9, 11 ) + STEP( H, c, d, a, b, GET(7), 0xf6bb4b60, 16 ) + STEP( H, b, c, d, a, GET(10), 0xbebfbc70, 23 ) + STEP( H, a, b, c, d, GET(13), 0x289b7ec6, 4 ) + STEP( H, d, a, b, c, GET(0), 0xeaa127fa, 11 ) + STEP( H, c, d, a, b, GET(3), 0xd4ef3085, 16 ) + STEP( H, b, c, d, a, GET(6), 0x04881d05, 23 ) + STEP( H, a, b, c, d, GET(9), 0xd9d4d039, 4 ) + STEP( H, d, a, b, c, GET(12), 0xe6db99e5, 11 ) + STEP( H, c, d, a, b, GET(15), 0x1fa27cf8, 16 ) + STEP( H, b, c, d, a, GET(2), 0xc4ac5665, 23 ) + + // Round 4 + STEP( I, a, b, c, d, GET(0), 0xf4292244, 6 ) + STEP( I, d, a, b, c, GET(7), 0x432aff97, 10 ) + STEP( I, c, d, a, b, GET(14), 0xab9423a7, 15 ) + STEP( I, b, c, d, a, GET(5), 0xfc93a039, 21 ) + STEP( I, a, b, c, d, GET(12), 0x655b59c3, 6 ) + STEP( I, d, a, b, c, GET(3), 0x8f0ccc92, 10 ) + STEP( I, c, d, a, b, GET(10), 0xffeff47d, 15 ) + STEP( I, b, c, d, a, GET(1), 0x85845dd1, 21 ) + STEP( I, a, b, c, d, GET(8), 0x6fa87e4f, 6 ) + STEP( I, d, a, b, c, GET(15), 0xfe2ce6e0, 10 ) + STEP( I, c, d, a, b, GET(6), 0xa3014314, 15 ) + STEP( I, b, c, d, a, GET(13), 0x4e0811a1, 21 ) + STEP( I, a, b, c, d, GET(4), 0xf7537e82, 6 ) + STEP( I, d, a, b, c, GET(11), 0xbd3af235, 10 ) + STEP( I, c, d, a, b, GET(2), 0x2ad7d2bb, 15 ) + STEP( I, b, c, d, a, GET(9), 0xeb86d391, 21 ) + + a += saved_a; + b += saved_b; + c += saved_c; + d += saved_d; + + ptr += 64; + } while( size -= 64 ); + + ctx->a = a; + ctx->b = b; + ctx->c = c; + ctx->d = d; + + #undef GET + #undef SET + + return ptr; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// EXPORTED FUNCTIONS +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Md5Initialise +// +// Initialises an MD5 Context. Use this to initialise/reset a context. +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +void + Md5Initialise + ( + Md5Context* Context // [out] + ) +{ + Context->a = 0x67452301; + Context->b = 0xefcdab89; + Context->c = 0x98badcfe; + Context->d = 0x10325476; + + Context->lo = 0; + Context->hi = 0; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Md5Update +// +// Adds data to the MD5 context. This will process the data and update the internal state of the context. Keep on +// calling this function until all the data has been added. Then call Md5Finalise to calculate the hash. +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +void + Md5Update + ( + Md5Context* Context, // [in out] + void const* Buffer, // [in] + uint32_t BufferSize // [in] + ) +{ + uint32_t saved_lo; + uint32_t used; + uint32_t free; + + saved_lo = Context->lo; + if( (Context->lo = (saved_lo + BufferSize) & 0x1fffffff) < saved_lo ) + { + Context->hi++; + } + Context->hi += (uint32_t)( BufferSize >> 29 ); + + used = saved_lo & 0x3f; + + if( used ) + { + free = 64 - used; + + if( BufferSize < free ) + { + memcpy( &Context->buffer[used], Buffer, BufferSize ); + return; + } + + memcpy( &Context->buffer[used], Buffer, free ); + Buffer = (uint8_t*)Buffer + free; + BufferSize -= free; + TransformFunction(Context, Context->buffer, 64); + } + + if( BufferSize >= 64 ) + { + Buffer = TransformFunction( Context, Buffer, BufferSize & ~(unsigned long)0x3f ); + BufferSize &= 0x3f; + } + + memcpy( Context->buffer, Buffer, BufferSize ); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Md5Finalise +// +// Performs the final calculation of the hash and returns the digest (16 byte buffer containing 128bit hash). After +// calling this, Md5Initialised must be used to reuse the context. +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +void + Md5Finalise + ( + Md5Context* Context, // [in out] + MD5_HASH* Digest // [in] + ) +{ + uint32_t used; + uint32_t free; + + used = Context->lo & 0x3f; + + Context->buffer[used++] = 0x80; + + free = 64 - used; + + if(free < 8) + { + memset( &Context->buffer[used], 0, free ); + TransformFunction( Context, Context->buffer, 64 ); + used = 0; + free = 64; + } + + memset( &Context->buffer[used], 0, free - 8 ); + + Context->lo <<= 3; + Context->buffer[56] = (uint8_t)( Context->lo ); + Context->buffer[57] = (uint8_t)( Context->lo >> 8 ); + Context->buffer[58] = (uint8_t)( Context->lo >> 16 ); + Context->buffer[59] = (uint8_t)( Context->lo >> 24 ); + Context->buffer[60] = (uint8_t)( Context->hi ); + Context->buffer[61] = (uint8_t)( Context->hi >> 8 ); + Context->buffer[62] = (uint8_t)( Context->hi >> 16 ); + Context->buffer[63] = (uint8_t)( Context->hi >> 24 ); + + TransformFunction( Context, Context->buffer, 64 ); + + Digest->bytes[0] = (uint8_t)( Context->a ); + Digest->bytes[1] = (uint8_t)( Context->a >> 8 ); + Digest->bytes[2] = (uint8_t)( Context->a >> 16 ); + Digest->bytes[3] = (uint8_t)( Context->a >> 24 ); + Digest->bytes[4] = (uint8_t)( Context->b ); + Digest->bytes[5] = (uint8_t)( Context->b >> 8 ); + Digest->bytes[6] = (uint8_t)( Context->b >> 16 ); + Digest->bytes[7] = (uint8_t)( Context->b >> 24 ); + Digest->bytes[8] = (uint8_t)( Context->c ); + Digest->bytes[9] = (uint8_t)( Context->c >> 8 ); + Digest->bytes[10] = (uint8_t)( Context->c >> 16 ); + Digest->bytes[11] = (uint8_t)( Context->c >> 24 ); + Digest->bytes[12] = (uint8_t)( Context->d ); + Digest->bytes[13] = (uint8_t)( Context->d >> 8 ); + Digest->bytes[14] = (uint8_t)( Context->d >> 16 ); + Digest->bytes[15] = (uint8_t)( Context->d >> 24 ); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Md5Calculate +// +// Combines Md5Initialise, Md5Update, and Md5Finalise into one function. Calculates the MD5 hash of the buffer. +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +void + Md5Calculate + ( + void const* Buffer, // [in] + uint32_t BufferSize, // [in] + MD5_HASH* Digest // [in] + ) +{ + Md5Context context; + + Md5Initialise( &context ); + Md5Update( &context, Buffer, BufferSize ); + Md5Finalise( &context, Digest ); +} diff --git a/src/md5.h b/src/md5.h new file mode 100755 index 000000000..5ef252221 --- /dev/null +++ b/src/md5.h @@ -0,0 +1,100 @@ +/* + * Retrieved from https://github.com/WaterJuice/WjCryptLib + */ + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// WjCryptLib_Md5 +// +// Implementation of MD5 hash function. Originally written by Alexander Peslyak. Modified by WaterJuice retaining +// Public Domain license. +// +// This is free and unencumbered software released into the public domain - June 2013 waterjuice.org +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#pragma once + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// IMPORTS +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#include +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// TYPES +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +// Md5Context - This must be initialised using Md5Initialised. Do not modify the contents of this structure directly. +typedef struct +{ + uint32_t lo; + uint32_t hi; + uint32_t a; + uint32_t b; + uint32_t c; + uint32_t d; + uint8_t buffer[64]; + uint32_t block[16]; +} Md5Context; + +#define MD5_HASH_SIZE ( 128 / 8 ) + +typedef struct +{ + uint8_t bytes [MD5_HASH_SIZE]; +} MD5_HASH; + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// PUBLIC FUNCTIONS +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Md5Initialise +// +// Initialises an MD5 Context. Use this to initialise/reset a context. +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +void + Md5Initialise + ( + Md5Context* Context // [out] + ); + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Md5Update +// +// Adds data to the MD5 context. This will process the data and update the internal state of the context. Keep on +// calling this function until all the data has been added. Then call Md5Finalise to calculate the hash. +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +void + Md5Update + ( + Md5Context* Context, // [in out] + void const* Buffer, // [in] + uint32_t BufferSize // [in] + ); + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Md5Finalise +// +// Performs the final calculation of the hash and returns the digest (16 byte buffer containing 128bit hash). After +// calling this, Md5Initialised must be used to reuse the context. +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +void + Md5Finalise + ( + Md5Context* Context, // [in out] + MD5_HASH* Digest // [in] + ); + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// Md5Calculate +// +// Combines Md5Initialise, Md5Update, and Md5Finalise into one function. Calculates the MD5 hash of the buffer. +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +void + Md5Calculate + ( + void const* Buffer, // [in] + uint32_t BufferSize, // [in] + MD5_HASH* Digest // [in] + ); From 42c5fd7e69ae7205befb37fac8868b1fd5965ad7 Mon Sep 17 00:00:00 2001 From: Simon Derr Date: Mon, 13 Apr 2020 10:46:56 +0200 Subject: [PATCH 0813/1435] st-flash: minor usage fix, and make cmdline parsing more user friendly Somewhat fix the help message that showed some parameters as mandatory, when in reality they depend on the operation type and file format. Try to show explicit error messages for the most common mistakes. --- src/tools/flash.c | 2 +- src/tools/flash_opts.c | 27 ++++++++++++++++++++------- 2 files changed, 21 insertions(+), 8 deletions(-) diff --git a/src/tools/flash.c b/src/tools/flash.c index 67e03c62b..b9cc86d45 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -31,7 +31,7 @@ static void usage(void) { puts("stlinkv1 command line: ./st-flash [--debug] [--reset] [--opt] [--format ] [--flash=] {read|write} /dev/sgX "); puts("stlinkv1 command line: ./st-flash [--debug] /dev/sgX erase"); - puts("stlinkv2/3 command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] {read|write} "); + puts("stlinkv2/3 command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] {read|write} [addr] [size]"); puts("stlinkv2/3 command line: ./st-flash [--debug] [--serial ] erase"); puts("stlinkv2/3 command line: ./st-flash [--debug] [--serial ] reset"); puts(" , and : Use hex format."); diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index a24bde1be..261d8b524 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -11,6 +11,18 @@ static bool starts_with(const char * str, const char * prefix) { return (0 == strncmp(str, prefix, n)); } +static int invalid_args(const char *expected) +{ + fprintf(stderr, "*** Error: Expected args for this command: %s\n", expected); + return -1; +} + +static int bad_arg(const char *arg) +{ + fprintf(stderr, "*** Error: Invalid value for %s\n", arg); + return -1; +} + int flash_get_opts(struct flash_opts* o, int ac, char** av) { bool serial_specified = false; @@ -94,7 +106,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { else if (strcmp(format, "ihex") == 0) o->format = FLASH_FORMAT_IHEX; else - return -1; + return bad_arg("format"); } else if ( starts_with(av[0], "--flash=") ) { const char *arg = av[0] + strlen("--flash="); @@ -168,12 +180,13 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { case FLASH_CMD_READ: // expect filename, addr and size if((o->area == FLASH_OPTION_BYTES) &&(ac == 0)) break; + if (ac != 3) return invalid_args("read "); if (ac != 3) return -1; o->filename = av[0]; o->addr = (uint32_t) strtoul(av[1], &tail, 16); - if(tail[0] != '\0') return -1; + if(tail[0] != '\0') return bad_arg("addr"); o->size = strtoul(av[2], &tail, 16); - if(tail[0] != '\0') return -1; + if(tail[0] != '\0') return bad_arg("size"); break; case FLASH_CMD_WRITE: @@ -182,17 +195,17 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { o->val = (uint32_t)strtoul(av[0], &tail, 16); } else if(o->format == FLASH_FORMAT_BINARY) { // expect filename and addr - if (ac != 2) return -1; + if (ac != 2) return invalid_args("write "); o->filename = av[0]; o->addr = (uint32_t) strtoul(av[1], &tail, 16); - if(tail[0] != '\0') return -1; + if(tail[0] != '\0') return bad_arg("addr"); } else if(o->format == FLASH_FORMAT_IHEX) { // expect filename - if (ac != 1) return -1; + if (ac != 1) return invalid_args("write "); o->filename = av[0]; } else { - return -1; + return -1; // should have been caught during format parsing } break; From eb243044338b9a1f312a92b7dbc5c2b61fc0360a Mon Sep 17 00:00:00 2001 From: Simon Derr Date: Mon, 13 Apr 2020 11:55:39 +0200 Subject: [PATCH 0814/1435] src/tools/flash_opts.c: fix style issues --- src/tools/flash_opts.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index 261d8b524..5f6417bac 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -11,16 +11,14 @@ static bool starts_with(const char * str, const char * prefix) { return (0 == strncmp(str, prefix, n)); } -static int invalid_args(const char *expected) -{ - fprintf(stderr, "*** Error: Expected args for this command: %s\n", expected); - return -1; +static int invalid_args(const char *expected) { + fprintf(stderr, "*** Error: Expected args for this command: %s\n", expected); + return -1; } -static int bad_arg(const char *arg) -{ - fprintf(stderr, "*** Error: Invalid value for %s\n", arg); - return -1; +static int bad_arg(const char *arg) { + fprintf(stderr, "*** Error: Invalid value for %s\n", arg); + return -1; } int flash_get_opts(struct flash_opts* o, int ac, char** av) { From 35cbe57f4f6c2e2052b32c4c2431a578c6344a10 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Mon, 13 Apr 2020 18:30:44 +0800 Subject: [PATCH 0815/1435] Add st official checksum for binary file --- src/common.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/common.c b/src/common.c index 43cec756d..d3944eec5 100644 --- a/src/common.c +++ b/src/common.c @@ -1380,6 +1380,16 @@ static void md5_calculate(mapped_file_t *mf, const char *path) { printf("\n"); } +static void stlink_checksum(mapped_file_t *mp, const char* path) { + /* checksum that backward compatible with official ST tools */ + uint32_t sum = 0; + uint8_t *mp_byte = (uint8_t *)mp->base; + for (size_t i = 0; i < mp->len; ++i) { + sum += mp_byte[i]; + } + printf("file %s stlink checksum: 0x%08x\n", path, sum); +} + static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { unsigned int val; /* set stack*/ @@ -1462,6 +1472,7 @@ int stlink_fwrite_sram(stlink_t * sl, const char* path, stm32_addr_t addr) { } md5_calculate(&mf, path); + stlink_checksum(&mf, path); /* check addr range is inside the sram */ if (addr < sl->sram_base) { @@ -2688,6 +2699,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { } md5_calculate(&mf, path); + stlink_checksum(&mf, path); if (sl->opt) { idx = (unsigned int) mf.len; @@ -3254,6 +3266,7 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr } md5_calculate(&mf, path); + stlink_checksum(&mf, path); err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t) mf.len); stlink_fwrite_finalize(sl, addr); From 6eb9103a235dcf24c86e39553f807a987b533aa0 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 13 Apr 2020 15:02:43 +0200 Subject: [PATCH 0816/1435] Updated build-settings - Added new build configs for Travis - Refactoring for cmake modules - Updated Travis build script - Makefile: binary build for Windows --- .travis.sh | 38 ++++++-- .travis.yml | 8 ++ Makefile | 14 ++- cmake/modules/FindLibUSB.cmake | 155 ++++++++++++++++++--------------- cmake/version.cmake | 61 +++++++------ 5 files changed, 176 insertions(+), 100 deletions(-) diff --git a/.travis.sh b/.travis.sh index 05568d37d..3d6da055f 100755 --- a/.travis.sh +++ b/.travis.sh @@ -5,15 +5,43 @@ ls -1 /usr/bin/clang* ls -1 /usr/bin/scan-build* echo "----" +echo "WORK DIR:$DIR" +DIR=$PWD + if [ "$TRAVIS_OS_NAME" == "linux" ]; then sudo apt-get update -qq || true sudo apt-get install -qq -y --no-install-recommends libgtk-3-dev + + echo "--> Building Debug..." + mkdir -p build/Debug && cd build/Debug + echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install" + cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ + make && make package && cd - + + echo "--> Building Release..." + mkdir -p build/Release && cd build/Release + echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install" + cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ + make && make package && cd - + + echo "--> Building Binary..." + mkdir -p build/Binary && cd build/Binary + cho "-DCMAKE_BUILD_TYPE=Binary -DCMAKE_INSTALL_PREFIX=$PWD/_install" + cmake -DCMAKE_BUILD_TYPE=Binary -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ + make && make package && cd - + else #("$TRAVIS_OS_NAME" == "osx") brew install libusb -fi -echo "=== Building Debug" -mkdir -p build/Debug && cd build/Debug && cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ && make && make package && cd - + echo "--> Building Debug..." + mkdir -p build/Debug && cd build/Debug + echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install" + cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ + make && make package && cd - -echo "=== Building Release" -mkdir -p build/Release && cd build/Release && cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ && make && make package && cd - + echo "--> Building Release..." + mkdir -p build/Release && cd build/Release + echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install" + cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ + make && make package && cd - +fi diff --git a/.travis.yml b/.travis.yml index 079888765..221e8ece7 100644 --- a/.travis.yml +++ b/.travis.yml @@ -38,6 +38,14 @@ matrix: apt: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] packages: ['clang-6.0', 'libusb-1.0.0-dev'] + - os: linux + arch: x64 + compiler: clang-6.0 + addons: + apt: + sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] + packages: ['clang-6.0', 'libusb-1.0.0-dev'] + env: CFLAGS=-m32 LDFLAGS=-m32 ### 32-bit builds ### - os: linux diff --git a/Makefile b/Makefile index 0636eb9bd..6b44bd70c 100644 --- a/Makefile +++ b/Makefile @@ -4,11 +4,12 @@ MAKEFLAGS += -s all: release -ci: debug release test +ci: debug release binary test help: - @echo " release: Run a release build" @echo " debug: Run a debug build" + @echo " release: Run a release build" + @echo " binary: Build Windows-Binary" @echo " lint: Lint check all source-code" @echo " test: Build and run tests" @echo " clean: Clean all build output" @@ -17,6 +18,7 @@ help: rebuild_cache: build/Debug build/Release @$(MAKE) -C build/Debug rebuild_cache @$(MAKE) -C build/Release rebuild_cache + @$(MAKE) -C build/Binary rebuild_cache debug: build/Debug @echo "[DEBUG]" @@ -26,6 +28,10 @@ release: build/Release @echo "[RELEASE]" @$(MAKE) -C build/Release +binary: build/Binary + @echo "[BINARY]" + @$(MAKE) -C build/Binary + package: build/Release @echo "[PACKAGE] Release" @$(MAKE) -C build/Release package @@ -41,6 +47,10 @@ build/Release: @mkdir -p $@ @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Release $(CMAKEFLAGS) ../../ +build/Binary: + @mkdir -p $@ + @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Binary $(CMAKEFLAGS) ../../ + clean: @echo "[CLEAN]" @rm -Rf build diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index dc90bcc32..b583b8491 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -1,102 +1,90 @@ # FindLibUSB.cmake # Once done this will define # -# LIBUSB_FOUND - System has libusb -# LIBUSB_INCLUDE_DIR - The libusb include directory -# LIBUSB_LIBRARY - The libraries needed to use libusb -# LIBUSB_DEFINITIONS - Compiler switches required for using libusb +# LIBUSB_FOUND libusb present on system +# LIBUSB_INCLUDE_DIR the libusb include directory +# LIBUSB_LIBRARY the libraries needed to use libusb +# LIBUSB_DEFINITIONS compiler switches required for using libusb -if (NOT (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD")) # all OS apart from FreeBSD +include(FindPackageHandleStandardArgs) + +if (APPLE) # macOS FIND_PATH( LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr /usr/local /opt PATH_SUFFIXES libusb-1.0 ) -endif () - -if (APPLE) # macOS set(LIBUSB_NAME libusb-1.0.a) find_library( LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS /usr /usr/local /opt ) - -elseif (MINGW OR MSYS) # Windows with MinGW or MSYS - set(LIBUSB_NAME usb-1.0) - - if (CMAKE_SIZEOF_VOID_P EQUAL 8) # 64-bit - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/static - NO_DEFAULT_PATH - NO_CMAKE_FIND_ROOT_PATH - ) - else () # 32-bit - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW32/static - NO_DEFAULT_PATH - NO_CMAKE_FIND_ROOT_PATH - ) + FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) + if (NOT LIBUSB_FOUND) + message(FATAL_ERROR "No libusb library found on your system! Install libusb-1.0 from Homebrew or MacPorts") endif () -elseif (MSVC) # Windows with MSVC - set(LIBUSB_NAME libusb-1.0.lib) - if (CMAKE_SIZEOF_VOID_P EQUAL 8) # 64-bit - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS64/dll - NO_DEFAULT_PATH - NO_CMAKE_FIND_ROOT_PATH - ) - else () # 32-bit - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS32/dll - NO_DEFAULT_PATH - NO_CMAKE_FIND_ROOT_PATH - ) - endif () - -elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD - # libusb is integrated into FreeBSD +elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated into the system FIND_PATH( LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr/include ) - set(LIBUSB_NAME usb) find_library( LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS /usr /usr/local /opt ) + FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) + if (NOT LIBUSB_FOUND) + message(FATAL_ERROR "Expected libusb library not found on your system! Verify your system integrity.") + endif () -else () # all other OS - set(LIBUSB_NAME usb-1.0) - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS /usr /usr/local /opt - ) -endif() +elseif (WIN32 OR (EXISTS "/etc/debian_version" AND ${CMAKE_BUILD_TYPE} MATCHES "Binary")) + # Windows & Windows-Binary-Build on Debian/Ubuntu -include(FindPackageHandleStandardArgs) -FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) -mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) + # for MinGW/MSYS/MSVC: 64-bit or 32-bit? + if (CMAKE_SIZEOF_VOID_P EQUAL 8) + set(ARCH 64) + else () + set(ARCH 32) + endif () -if (NOT LIBUSB_FOUND) - if (WIN32 OR MINGW OR MSYS OR MSVC) # Windows + if (NOT EXISTS "/etc/debian_version") + FIND_PATH( + LIBUSB_INCLUDE_DIR NAMES libusb.h + HINTS /usr /usr/local /opt + PATH_SUFFIXES libusb-1.0 + ) + if (MINGW OR MSYS) + set(LIBUSB_NAME usb-1.0) + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW${ARCH}/static + ) + else (MSVC) + set(LIBUSB_NAME libusb-1.0.lib) + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS${ARCH}/dll + ) + endif () + endif () + + if (NOT LIBUSB_FOUND OR EXISTS "/etc/debian_version") # Preparations for installing libusb library find_package(7Zip REQUIRED) - set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version to 1.0.23 (latest as of Apr 2020) + set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/3rdparty/libusb-${LIBUSB_WIN_VERSION}) # Get libusb package - if (EXISTS ${LIBUSB_WIN_ARCHIVE_PATH}) # ... should the package be already there (for whatever reason) + if (EXISTS ${LIBUSB_WIN_ARCHIVE_PATH}) # ... should the package be already there (for whatever reason) message(STATUS "libusb archive already in build folder") - else () # ... download the package (1.0.23 as of Apr 2020) + else () # ... download the package message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download @@ -127,11 +115,42 @@ if (NOT LIBUSB_FOUND) NO_CMAKE_FIND_ROOT_PATH ) - FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) - message(STATUS "installed libusb library") - else () # all other OS - message(FATAL_ERROR "libusb library not found on your system! Compilation terminated.") + if (MINGW OR MSYS) + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW${ARCH}/static + NO_DEFAULT_PATH + NO_CMAKE_FIND_ROOT_PATH + ) + + else (MSVC) + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS${ARCH}/dll + NO_DEFAULT_PATH + NO_CMAKE_FIND_ROOT_PATH + ) + endif () + message(STATUS "Missing libusb library has been installed") + endif () + FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) + +else () # all other OS (unix-based) + FIND_PATH( + LIBUSB_INCLUDE_DIR NAMES libusb.h + HINTS /usr /usr/local /opt + PATH_SUFFIXES libusb-1.0 + ) + set(LIBUSB_NAME usb-1.0) + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS /usr /usr/local /opt + ) + FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) + + if (NOT LIBUSB_FOUND) + message(FATAL_ERROR "libusb library not found on your system! Install libusb 1.0.x from your package repository.") endif () -else (NOT LIBUSB_FOUND) - message(STATUS "found libusb library") endif () diff --git a/cmake/version.cmake b/cmake/version.cmake index fe778c419..38254409f 100644 --- a/cmake/version.cmake +++ b/cmake/version.cmake @@ -5,9 +5,11 @@ set(__detect_version 0) find_package(Git) +set(ERROR_FLAG "0") if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") # Working off a git repo, using git versioning + # Check if HEAD is pointing to a tag execute_process ( COMMAND "${GIT_EXECUTABLE}" describe --always --tag @@ -17,22 +19,22 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") ERROR_VARIABLE GIT_DESCRIBE_ERROR OUTPUT_STRIP_TRAILING_WHITESPACE ) - if (GIT_DESCRIBE_RESULT EQUAL 0) + # If the sources have been changed locally, add -dirty to the version. execute_process ( COMMAND "${GIT_EXECUTABLE}" diff --quiet WORKING_DIRECTORY "${PROJECT_SOURCE_DIR}" RESULT_VARIABLE res ) - if (res EQUAL 1) - set (PROJECT_VERSION "${PROJECT_VERSION}-dirty") + set(PROJECT_VERSION "${PROJECT_VERSION}-dirty") endif () - # strip a leading v off of the version as proceeding code expectes just the version numbering. + # Strip a leading v off of the version as proceeding code expects just the version numbering. string(REGEX REPLACE "^v" "" PROJECT_VERSION ${PROJECT_VERSION}) + # Read version string string(REGEX REPLACE "^(0|[1-9][0-9]*)[.](0|[1-9][0-9]*)[.](0|[1-9][0-9]*)(-[.0-9A-Za-z-]+)?([+][.0-9A-Za-z-]+)?$" "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) list(LENGTH PROJECT_VERSION_LIST len) @@ -42,34 +44,46 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") list(GET PROJECT_VERSION_LIST 2 PROJECT_VERSION_PATCH) set(__detect_version 1) set(__version_str "${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}") + + # Compare git-Version with version read from .version file in source folder if (EXISTS "${PROJECT_SOURCE_DIR}/.version") + + # Local .version file found, read version string... file(READ "${PROJECT_SOURCE_DIR}/.version" __version_file) + + # ...the version does not match with git-version string if (NOT __version_str STREQUAL __version_file) - message(STATUS "Rewrite ${PROJECT_SOURCE_DIR}/.version with ${__version_str}") + message(STATUS "Rewrite ${PROJECT_SOURCE_DIR}/.version with ${__version_str}.") endif () - else () + + else (EXISTS "${PROJECT_SOURCE_DIR}/.version") + + # No local .version file found: Create a new one... file(WRITE "${PROJECT_SOURCE_DIR}/.version" ${__version_str}) + endif () - else () - message(STATUS "Fail to extract version parts from \"${PROJECT_VERSION}\"") - endif () - else(GIT_DESCRIBE_RESULT EQUAL 0) - message(WARNING "git describe failed.") - message(WARNING "${GIT_DESCRIBE_ERROR}") + message(STATUS "stlink version: ${PROJECT_VERSION}") + message(STATUS "Major ${PROJECT_VERSION_MAJOR} Minor ${PROJECT_VERSION_MINOR} Patch ${PROJECT_VERSION_PATCH}") + + else (len EQUAL 3) + message(STATUS "Failed to extract version parts from \"${PROJECT_VERSION}\"") + set(ERROR_FLAG "1") + endif (len EQUAL 3) + + else (GIT_DESCRIBE_RESULT EQUAL 0) + message(WARNING "git describe failed: ${GIT_DESCRIBE_ERROR}") + set(ERROR_FLAG "1") endif(GIT_DESCRIBE_RESULT EQUAL 0) -else () - message(STATUS "Git or repo not found.") endif () -if (NOT __detect_version) - message(STATUS "Try to detect version from \"${PROJECT_SOURCE_DIR}/.version\" file.") +if (ERROR_FLAG EQUAL 1) + message(STATUS "Git and/or repository not found.") # e.g. when building from source package + message(STATUS "Try to detect version from \"${PROJECT_SOURCE_DIR}/.version\" file instead...") if (EXISTS ${PROJECT_SOURCE_DIR}/.version) - # If git is not available (e.g. when building from source package) - # we can extract the package version from .version file. file(STRINGS .version PROJECT_VERSION) - # TODO create function to extract semver from file or string and check if it is correct instead of copy-pasting + # Read version string string(REGEX REPLACE "^(0|[1-9][0-9]*)[.](0|[1-9][0-9]*)[.](0|[1-9][0-9]*)(-[.0-9A-Za-z-]+)?([+][.0-9A-Za-z-]+)?$" "\\1;\\2;\\3" PROJECT_VERSION_LIST ${PROJECT_VERSION}) list(LENGTH PROJECT_VERSION_LIST len) @@ -81,11 +95,8 @@ if (NOT __detect_version) else () message(STATUS "Fail to extract version parts from \"${PROJECT_VERSION}\"") endif () - else () - message(STATUS "File \"${PROJECT_SOURCE_DIR}/.version\" did not exists.") + else (EXISTS ${PROJECT_SOURCE_DIR}/.version) + message(STATUS "File \"${PROJECT_SOURCE_DIR}/.version\" does not exist.") + message(FATAL_ERROR "Unable to determine project version") endif () - message(FATAL_ERROR "Unable to determine project version") endif () - -message(STATUS "stlink version: ${PROJECT_VERSION}") -message(STATUS "Major ${PROJECT_VERSION_MAJOR} Minor ${PROJECT_VERSION_MINOR} Patch ${PROJECT_VERSION_PATCH}") From 6515e57b9ea4db69de3f66ba8db709163ab22456 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Mon, 13 Apr 2020 21:20:20 +0800 Subject: [PATCH 0817/1435] Adjust output format for better formating --- src/common.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/common.c b/src/common.c index d3944eec5..e719c6031 100644 --- a/src/common.c +++ b/src/common.c @@ -1373,11 +1373,11 @@ static void md5_calculate(mapped_file_t *mf, const char *path) { Md5Initialise(&md5Context); Md5Update(&md5Context, mf->base, (uint32_t)mf->len); Md5Finalise(&md5Context, &md5Hash); - printf("file %s md5 checksum: ",path); + printf("md5 checksum: "); for(int i = 0; i < (int) sizeof(md5Hash); i++) { printf("%x", md5Hash.bytes[i]); } - printf("\n"); + printf(", "); } static void stlink_checksum(mapped_file_t *mp, const char* path) { @@ -1387,7 +1387,7 @@ static void stlink_checksum(mapped_file_t *mp, const char* path) { for (size_t i = 0; i < mp->len; ++i) { sum += mp_byte[i]; } - printf("file %s stlink checksum: 0x%08x\n", path, sum); + printf("stlink checksum: 0x%08x\n", sum); } static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { @@ -1470,7 +1470,7 @@ int stlink_fwrite_sram(stlink_t * sl, const char* path, stm32_addr_t addr) { fprintf(stderr, "map_file() == -1\n"); return -1; } - + printf("file %s "); md5_calculate(&mf, path); stlink_checksum(&mf, path); @@ -2698,6 +2698,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { return -1; } + printf("file %s "); md5_calculate(&mf, path); stlink_checksum(&mf, path); @@ -3265,6 +3266,7 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr return -1; } + printf("file %s "); md5_calculate(&mf, path); stlink_checksum(&mf, path); From 1047fdd44063d26e25974704ef23ef9ee8595e3e Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Mon, 13 Apr 2020 21:26:16 +0800 Subject: [PATCH 0818/1435] Add documentation about the checksum --- doc/tutorial.md | 5 +++++ src/common.c | 22 +++++++++++----------- 2 files changed, 16 insertions(+), 11 deletions(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index 66bed0382..f19a6ecd9 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -539,6 +539,11 @@ want to disassemble the code at 0x20000000, use:\ (gdb) disassemble 0x20000001 ``` +Checksum of binary file +----------------------- + +When flashing a file, the checksum of which is calculated, both in md5 and the sum algorithm used by ST's official tool. The detail of sum algorithm can be found in [https://www.st.com/resource/en/user_manual/cd00262073-stm32-stlink-utility-software-description-stmicroelectronics.pdf](https://www.st.com/resource/en/user_manual/cd00262073-stm32-stlink-utility-software-description-stmicroelectronics.pdf). + References ========== diff --git a/src/common.c b/src/common.c index e719c6031..d04644071 100644 --- a/src/common.c +++ b/src/common.c @@ -1366,7 +1366,7 @@ static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) { return 0; } -static void md5_calculate(mapped_file_t *mf, const char *path) { +static void md5_calculate(mapped_file_t *mf) { /* calculate md5 checksum of given binary file */ Md5Context md5Context; MD5_HASH md5Hash; @@ -1380,7 +1380,7 @@ static void md5_calculate(mapped_file_t *mf, const char *path) { printf(", "); } -static void stlink_checksum(mapped_file_t *mp, const char* path) { +static void stlink_checksum(mapped_file_t *mp) { /* checksum that backward compatible with official ST tools */ uint32_t sum = 0; uint8_t *mp_byte = (uint8_t *)mp->base; @@ -1470,9 +1470,9 @@ int stlink_fwrite_sram(stlink_t * sl, const char* path, stm32_addr_t addr) { fprintf(stderr, "map_file() == -1\n"); return -1; } - printf("file %s "); - md5_calculate(&mf, path); - stlink_checksum(&mf, path); + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); /* check addr range is inside the sram */ if (addr < sl->sram_base) { @@ -2698,9 +2698,9 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { return -1; } - printf("file %s "); - md5_calculate(&mf, path); - stlink_checksum(&mf, path); + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); if (sl->opt) { idx = (unsigned int) mf.len; @@ -3266,9 +3266,9 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr return -1; } - printf("file %s "); - md5_calculate(&mf, path); - stlink_checksum(&mf, path); + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t) mf.len); stlink_fwrite_finalize(sl, addr); From fc507fd4842cd9b4719378d0ee79a6a123eecae3 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Sun, 12 Apr 2020 15:58:17 +0200 Subject: [PATCH 0819/1435] flash.c: stlink_open_usb is actually able to open v1 and v2 (and v3 ..) devices. no need to check that _not used_ o.devname .. no need to specify devname in commandline get rid of the devname cmdline stuff, and update comments --- src/tools/flash.c | 13 ++++--------- src/tools/flash_opts.c | 11 +---------- 2 files changed, 5 insertions(+), 19 deletions(-) diff --git a/src/tools/flash.c b/src/tools/flash.c index b9cc86d45..f703bc813 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -29,11 +29,9 @@ static void cleanup(int signum) { static void usage(void) { - puts("stlinkv1 command line: ./st-flash [--debug] [--reset] [--opt] [--format ] [--flash=] {read|write} /dev/sgX "); - puts("stlinkv1 command line: ./st-flash [--debug] /dev/sgX erase"); - puts("stlinkv2/3 command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] {read|write} [addr] [size]"); - puts("stlinkv2/3 command line: ./st-flash [--debug] [--serial ] erase"); - puts("stlinkv2/3 command line: ./st-flash [--debug] [--serial ] reset"); + puts("command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] {read|write} [addr] [size]"); + puts("command line: ./st-flash [--debug] [--serial ] erase"); + puts("command line: ./st-flash [--debug] [--serial ] reset"); puts(" , and : Use hex format."); puts(" : Use decimal, octal or hex (prefix 0xXXX) format, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); puts(" : Can be 'binary' (default) or 'ihex', although must be specified for binary format only."); @@ -59,10 +57,7 @@ int main(int ac, char** av) printf("st-flash %s\n", STLINK_VERSION); - if (o.devname != NULL) /* stlinkv1 */ - sl = stlink_v1_open(o.log_level, 1); - else /* stlinkv2 */ - sl = stlink_open_usb(o.log_level, 1, (char *)o.serial); + sl = stlink_open_usb(o.log_level, 1, (char *)o.serial); if (sl == NULL) return -1; diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index 5f6417bac..c139977ce 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -22,7 +22,6 @@ static int bad_arg(const char *arg) { } int flash_get_opts(struct flash_opts* o, int ac, char** av) { - bool serial_specified = false; // defaults memset(o, 0, sizeof(*o)); @@ -63,7 +62,6 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { memcpy(buffer, serial + j, 2); o->serial[length - k] = (uint8_t)strtol(buffer, NULL, 16); } - serial_specified = true; } else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { const char * area; @@ -138,7 +136,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } // command and (optional) device name - while(ac >= 1) { // looks like for stlinkv1 the device name and command may be swaped - check both positions in all cases + while(ac >= 1) { if (strcmp(av[0], "erase") == 0) { if (o->cmd != FLASH_CMD_NONE) return -1; o->cmd = FLASH_CMD_ERASE; @@ -155,10 +153,6 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { if (o->cmd != FLASH_CMD_NONE) return -1; o->cmd = CMD_RESET; } - else if(starts_with(av[0], "/dev/")) { - if (o->devname) return -1; - o->devname = av[0]; - } else { break; } @@ -210,8 +204,5 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { default: break ; } - // some constistence checks - if(serial_specified && o->devname != NULL) return -1; // serial not supported for v1 - return 0; } From 308fccb04875c51dcfcf0730872ca0de37929bc8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 14 Apr 2020 21:01:52 +0200 Subject: [PATCH 0820/1435] General Project Update - Updated CHANGELOG.md - Updated links to project repository - Improved project description - Minor revision for tutorial.md - Formatting fixes --- CHANGELOG.md | 6 +-- README.md | 37 ++++++++----- doc/compiling.md | 6 +-- doc/tutorial.md | 133 +++++++++++++---------------------------------- 4 files changed, 67 insertions(+), 115 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 9e31aaf47..99d307f9a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -173,7 +173,7 @@ Release date: 2017-01-28 Major changes and added features: * Deprecation of autotools (autoconf, automake) and fixed build with MinGW ([#83](https://github.com/texane/stlink/pull/83), [#431](https://github.com/texane/stlink/pull/431), [#434](https://github.com/texane/stlink/pull/434), [#465](https://github.com/texane/stlink/pull/465)) -* Added intel hex file reading for `st-flash` ([#110](https://github.com/texane/stlink/pull/110), [#157](https://github.com/texane/stlink/pull/157), [#200](https://github.com/texane/stlink/pull/200), [#239](https://github.com/texane/stlink/pull/239), [#457](https://github.com/texane/stlink/pull/547), [#459](https://github.com/texane/stlink/pull/549)) +* Added intel hex file reading for `st-flash` ([#110](https://github.com/texane/stlink/pull/110), [#157](https://github.com/texane/stlink/pull/157), [#457](https://github.com/texane/stlink/pull/547), [#459](https://github.com/texane/stlink/pull/549)) * Added support for ARM semihosting to `st-util` ([#147](https://github.com/texane/stlink/pull/147), [#227](https://github.com/texane/stlink/pull/227), [#454](https://github.com/texane/stlink/pull/454), [#455](https://github.com/texane/stlink/pull/455)) * Added manpages (generated with pandoc from Markdown) ([#208](https://github.com/texane/stlink/pull/208), [#464](https://github.com/texane/stlink/pull/464), [#466](https://github.com/texane/stlink/pull/466), [#467](https://github.com/texane/stlink/pull/467)) * Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/texane/stlink/pull/228), ([#507](https://github.com/texane/stlink/pull/507), commit [#3fd0f09](https://github.com/texane/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) @@ -190,7 +190,7 @@ Chip support added for: * STM32F410RBTx ([#418](https://github.com/texane/stlink/pull/418)) * STM32F412 ([#537](https://github.com/texane/stlink/pull/537), [#538](https://github.com/texane/stlink/pull/538)) * STM32F7xx ([#324](https://github.com/texane/stlink/pull/324), [#326](https://github.com/texane/stlink/pull/326), [#327](https://github.com/texane/stlink/pull/327), [#337](https://github.com/texane/stlink/pull/337)) -* STM32F767ZI ([#509](https://github.com/texane/stlink/pull/509)) +* STM32F7x7x ([#433](https://github.com/texane/stlink/pull/433), [#435](https://github.com/texane/stlink/pull/435), [#436](https://github.com/texane/stlink/pull/436), [#509](https://github.com/texane/stlink/pull/509)) * STM32L0xx Cat2 devices (chip-ID: 0x425) ([#414](https://github.com/texane/stlink/pull/414)) * STM32L0xx Cat5 devices (chip-ID: 0x447) ([#387](https://github.com/texane/stlink/pull/387), [#406](https://github.com/texane/stlink/pull/406)) * STM32L4xx ([#321](https://github.com/texane/stlink/pull/321)) @@ -207,7 +207,7 @@ Updates and fixes: * Fixed STM32F030 erase error ([#442](https://github.com/texane/stlink/pull/442)) * Fixed memory map for STM32F7xx ([#453](https://github.com/texane/stlink/pull/453), [#456](https://github.com/texane/stlink/pull/456)) * Redesign of `st-flash` commandline options parsing ([#459](https://github.com/texane/stlink/pull/459)) -* Set SWDCLK and fixed jtag_reset bug ([#475](https://github.com/texane/stlink/pull/475), [#534](https://github.com/texane/stlink/pull/534)) +* Set SWDCLK and fixed jtag_reset bug ([#462](https://github.com/texane/stlink/pull/462), [#475](https://github.com/texane/stlink/pull/475), [#534](https://github.com/texane/stlink/pull/534)) * doc/compiling.md: Add note about installation and ldconfig ([#478](https://github.com/texane/stlink/pull/478), commit [#be66bbf](https://github.com/texane/stlink/commit/be66bbf200c718904514b044ba84d64a36456218)) * Fixed Release target to generate the man-pages with pandoc ([#479](https://github.com/texane/stlink/pull/479)) * Fixed Cygwin build ([#487](https://github.com/texane/stlink/pull/487), ([#506](https://github.com/texane/stlink/pull/506)) diff --git a/README.md b/README.md index 29d1ef766..b2ff03d54 100644 --- a/README.md +++ b/README.md @@ -20,21 +20,32 @@ are licensed under the **General Public License (GPL v2+)**. ## Introduction -This stlink toolset supports several so called stlink programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG. +STLink is an open source toolset to program and debug STM32 devices and boards manufactured by STMicroelectronics. +It supports several so called STLINK programmer boards (and clones thereof) which use a microcontroller chip +to translate commands from USB to JTAG/SWD. There are four generations available on the market: -These programmer boards are available in four versions: - -* **STLINKv1:** +* **STLINK/v1** _(obsolete as of 21-11-2019)_ - transport layer: SCSI passthru commands over USB - - present on STM32VL discovery kits -* **STLINKv2:** - * transport layer: raw USB commands - * present on STM32L discovery and nucleo and later kits -* **STLINKv2-1:** - * transport layer: raw USB commands - * present on some STM32 nucleo boards -* **STLINKv3:** - * _not yet supported by this toolset (but planned)_ + - stand-alone programmer and present on STM32VL Discovery boards +* **STLINK/v2** + - transport layer: raw USB commands + - stand-alone programmer and present on STM32L Discovery and Nucleo boards +* **STLINK/v2-1** + - transport layer: raw USB commands + - present on some STM32 Nucleo boards +* **STLINK/v3** + - transport layer: raw USB commands + - stand-alone programmer + +On the user level there is no difference in handling or operation between these different revisions. + +The STlink toolset includes: + +* a communication library (libstlink.a), +* a programmer and chip information tool (st-info), +* a flash manipulation tool (st-flash), +* a GDB server (st-util) and +* a GUI-Interface (stlink-gui) _[optional]_ ## Supported hardware combinations diff --git a/doc/compiling.md b/doc/compiling.md index 64f4de466..59685ef17 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -23,7 +23,7 @@ On Windows users should ensure that the following software is installed: development) 5. Create a new destination folder at a place of your choice 6. Open the command-line (cmd.exe) and execute `cd C:\$Path-to-your-destination-folder$\` -7. Fetch the project sourcefiles by running `git clone https://github.com/texane/stlink.git`from the command-line (cmd.exe)
    +7. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git`from the command-line (cmd.exe)
    or download the stlink zip-sourcefolder from the Release page on GitHub @@ -76,7 +76,7 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma 1. Open a new terminal console 2. Create a new destination folder at a place of your choice e.g. at `~/git`: `mkdir $HOME/git` 3. Change to this directory: `cd ~/git` -4. Fetch the project sourcefiles by running `git clone https://github.com/texane/stlink.git` +4. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git` ### Building @@ -183,7 +183,7 @@ Additionally we recommend to install Xcode which delivers the necessary C-compil 1. Open a new terminal window 2. Create a new destination folder at a place of your choice e.g. at `~/git`: `mkdir $HOME/git` 3. Change to this directory: `cd ~/git` -4. Fetch the project sourcefiles by running `git clone https://github.com/texane/stlink.git` +4. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git` ### Building diff --git a/doc/tutorial.md b/doc/tutorial.md index f19a6ecd9..75e03f1bc 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -14,12 +14,17 @@ This option accepts decimal (128k), octal 0200k, or hex 0x80k. Obviously leaving the multiplier out is equally valid, for example: `--flash=0x20000`. The size may be followed by an optional "k" or "m" to multiply the given value by 1k (1024) or 1M respectively. +#### Checksum for binary files + +When flashing a file, a checksum is calculated for the binary file, both in md5 and the sum algorithm. +The latter is also used by the official ST-Link utility tool from STMicroelectronics as described in the document: [`UM0892 - User manual - STM32 ST-LINK utility software description`](https://www.st.com/resource/en/user_manual/cd00262073-stm32-stlink-utility-software-description-stmicroelectronics.pdf). + ## Solutions to common problems -### a) ST-Link-v1 driver: Issue with Kernel Extension (kext) (macOS 10.11 and later only) +### a) STLINK/v1 driver: Issue with Kernel Extension (kext) (macOS 10.11 and later only) #### Problem: -st-util fails to detect a ST-Link-v1 device: +st-util fails to detect a STLINK/v1 device: ``` st-util -1 @@ -35,7 +40,7 @@ ERROR src/sg.c: Could not open stlink device The root of this problem is a system security setting introduced by Apple with OS X El Capitan (10.11) in 2015. The so called System Integrity Protection (SIP) is active per default and prevents the operating system amongst other things to load unsigned Kernel Extension Modules (kext). -Thus the ST-Link-v1 driver supplied with the tools, which installs as a kext, remains not functional, +Thus the STLINK/v1 driver supplied with the tools, which installs as a kext, remains not functional, while SIP is fully activated (as is per default). Action needs to be taken here by booting into the recovery mode where a terminal console window needs to be opened. @@ -47,7 +52,7 @@ Running `csrutil enable --without kext`, allows to load unsigned kernel extensio while leaving SIP active with all other security features. Unfortunately this option has been removed in macOS 10.14, which leaves the only option to disable SIP completely. -So who ever intends to run the ST-Link-v1 programmer on macOS please take this into account. +So who ever intends to run the STLINK/v1 programmer on macOS please take this into account. Further details can be found here: https://forums.developer.apple.com/thread/17452 @@ -66,7 +71,7 @@ Requesting load of /System/Library/Extensions/stlink_shield10_x.kext. 5) Enter the command `$ sudo touch /System/Library/Extensions` -7) Verify correct detection of the ST-Link-v1 device with the following input: `st-util -1` +7) Verify correct detection of the STLINK/v1 device with the following input: `st-util -1` You should then see a similar output like in this example: @@ -81,7 +86,7 @@ INFO gdb-server.c: Listening at *:4242... ### b) Verify if udev rules are set correctly (by Dave Hylands) -To investigate, start by plugging your STLINK device into the usb port. Then run lsusb. You should see an entry something like the following: +To investigate, start by plugging your STLINK device into the usb port. Then run `lsusb`. You should see an entry something like the following: ``` Bus 005 Device 017: ID 0483:374b STMicroelectronics ST-LINK/V2.1 (Nucleo-F103RB) @@ -96,7 +101,7 @@ On my system I see the following: crw-rw-rw- 1 root root 189, 528 Jan 24 17:52 /dev/bus/usb/005/017 ``` -which is world writable (this is from the MODE:="0666" below). I have several files in my `/etc/udev/rules.d` directory. In this particular case, the `49-stlinkv2-1.rules` file contains the following: +which is world writable (this is from the `MODE:="0666"` below). I have several files in my `/etc/udev/rules.d` directory. In this particular case, the `49-stlinkv2-1.rules` file contains the following: ``` # stm32 nucleo boards, with onboard st/linkv2-1 @@ -113,9 +118,9 @@ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ # GROUP:="somegroupname" and mange access using standard unix groups. ``` -and the idVendor of 0483 and idProduct of 374b matches the vendor id from the lsusb output. +and the `idVendor` of `0483` and `idProduct` of `374b` matches the vendor id from the `lsusb` output. -Make sure that you have all 3 files from here: https://github.com/texane/stlink/tree/master/etc/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing excisting files in `/etc/udev/ruled.d` you should run the following: +Make sure that you have all 3 files from here: https://github.com/stlink-org/stlink/tree/master/etc/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing excisting files in `/etc/udev/ruled.d` you should run the following: ``` sudo udevadm control --reload-rules @@ -135,8 +140,7 @@ Using STM32 discovery kits with open source tools This guide details the use of STMicroelectronics STM32 discovery kits in an open source environment. -Installing a GNU toolchain -========================== +## Installing a GNU toolchain Any toolchain supporting the cortex m3 should do. You can find the necessary to install such a toolchain here: @@ -149,51 +153,7 @@ Details for the installation are provided in the topmost `README` file. This documentation assumes the toolchains is installed in a `$TOOLCHAIN_PATH`. -Installing STLINK -================= - -STLINK is open source software to program and debug ST’s STM32 Discovery -kits. Those kits have an onboard chip that translates USB commands sent -by the host PC into JTAG/SWD commands. This chip is called STLINK, (yes, -isn’t that confusing? suggest a better name!) and comes in 2 versions -(STLINK v1 and v2). From a software point of view, those versions differ -only in the transport layer used to communicate (v1 uses SCSI passthru -commands, while v2 uses raw USB). From a user point of view, they are -identical. - - -Before continuing, the following dependencies must be met: - -- libusb-1.0 -- cmake - -Also make sure `gtk+` version 3.0 is installed. (`sudo apt-get install gtk+-3.0` or similiar) - -STLINK should run on any system meeting the above constraints. - -The STLINK software source code is retrieved using: - -``` -$> git clone https://github.com/texane/stlink.git -``` - -Everything can be built from the top directory: - -``` -$> cd stlink -$> make -$> cd build/Release && make install DESTDIR=_install -``` - -It includes: - -- a communication library (libstlink.a), -- a GDB server (st-util), -- a flash manipulation tool (st-flash). -- a programmer and chip information tool (st-info) - -Using the GDB server -==================== +## Using the GDB server This assumes you have got the libopencm3 project downloaded in `ocm3`. The libopencm3 project has some good, reliable examples for each of the @@ -259,8 +219,7 @@ examples from libopencm3, the LEDs on the board should be blinking for you. -Building and flashing a program -=============================== +## Building and flashing a program If you want to simply flash binary files to arbitrary sections of memory, or read arbitary addresses of memory out to a binary file, use @@ -300,9 +259,6 @@ $> [sudo] ./st-flash write fancy_blink.bin 0x08000000 Upon reset, the board LEDs should be blinking. -HOWTO (old) -=========== - ## Using the gdb server To run the gdb server: @@ -376,6 +332,16 @@ If you need to send a hard reset signal through `NRST` pin, you can use the foll ``` +## Disassembling THUMB code in GDB + +By default, the disassemble command in GDB operates in ARM mode. The programs running on CORTEX-M3 are compiled in THUMB mode. +To correctly disassemble them under GDB, uses an odd address. For instance, if you want to disassemble the code at 0x20000000, use: + +``` +(gdb) disassemble 0x20000001 +``` + + ## Running programs from SRAM You can run your firmware directly from SRAM if you want to. Just link @@ -469,19 +435,15 @@ A: Installed on Mac OS X 10.9.4 with ports method, [https://coderwall.com/p/oznj_q](https://coderwall.com/p/oznj_q) -`sudo port install libusb automake autoconf pkgconfig` - -`aclocal --force -I /opt/local/share/aclocal` - -`git clone https://github.com/texane/stlink.git stlink-utility` - -`cd stlink-utility` - -`./autogen.sh` - -`./configure` - -`make` +``` +sudo port install libusb automake autoconf pkgconfig +aclocal --force -I /opt/local/share/aclocal +git clone https://github.com/stlink-org/stlink.git stlink-utility +cd stlink-utility +./autogen.sh +./configure +make +``` Then trying to flash the image with STLINK v2 : @@ -524,26 +486,6 @@ http://community.spark.io/t/how-to-flash-a-brand-new-freshly-soldered-stm32f103- > 2014-08-11T23:14:54 INFO src/stlink-common.c: Flash written and verified! jolly good! -Notes -===== - -Disassembling THUMB code in GDB -------------------------------- - -By default, the disassemble command in GDB operates in ARM mode. The -programs running on CORTEX-M3 are compiled in THUMB mode. To correctly -disassemble them under GDB, uses an odd address. For instance, if you -want to disassemble the code at 0x20000000, use:\ - -``` -(gdb) disassemble 0x20000001 -``` - -Checksum of binary file ------------------------ - -When flashing a file, the checksum of which is calculated, both in md5 and the sum algorithm used by ST's official tool. The detail of sum algorithm can be found in [https://www.st.com/resource/en/user_manual/cd00262073-stm32-stlink-utility-software-description-stmicroelectronics.pdf](https://www.st.com/resource/en/user_manual/cd00262073-stm32-stlink-utility-software-description-stmicroelectronics.pdf). - References ========== @@ -554,5 +496,4 @@ References documentation related to the STM32L discovery kit - - libopencm3, a project providing a firmware library, with solid - examples for Cortex M3, M4 and M0 processors from any vendor. + libopencm3, a project providing a firmware library, with solid examples for Cortex M3, M4 and M0 processors from any vendor. From 6f934a396ef320ee5ade3de95135818e1683aefd Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 15 Apr 2020 16:20:17 +0200 Subject: [PATCH 0821/1435] Whitespace cleanup --- CMakeLists.txt | 4 +- cmake/c_flag_overrides.cmake | 4 +- cmake/c_flags.cmake | 6 +- cmake/cpack_config.cmake | 14 +- cmake/modules/FindLibUSB.cmake | 2 +- cmake/modules/pandocology.cmake | 40 +++--- cmake/version.cmake | 4 +- cmake_uninstall.cmake.in | 4 +- doc/man/CMakeLists.txt | 2 +- src/common.c | 166 +++++++++++----------- src/flash_loader.c | 2 +- src/gdbserver/gdb-remote.c | 36 ++--- src/gdbserver/gdb-server.c | 234 ++++++++++++++++---------------- src/gdbserver/semihosting.c | 22 +-- src/md5.c | 14 +- src/mingw/mingw.c | 30 ++-- src/sg.c | 4 +- src/tools/flash.c | 16 +-- src/tools/flash_opts.c | 32 ++--- src/tools/gui/stlink-gui.c | 14 +- src/usb.c | 6 +- tests/flash.c | 14 +- 22 files changed, 335 insertions(+), 335 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 45e332b10..3572c2a15 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -101,8 +101,8 @@ set(STLINK_SOURCE ) if (WIN32 OR MSYS OR MINGW) - set (STLINK_SOURCE "${STLINK_SOURCE};src/mmap.c;src/mingw/mingw.c") - set (STLINK_HEADERS "${STLINK_HEADERS};src/mingw/mingw.h") + set(STLINK_SOURCE "${STLINK_SOURCE};src/mmap.c;src/mingw/mingw.c") + set(STLINK_HEADERS "${STLINK_HEADERS};src/mingw/mingw.h") endif () include_directories(${LIBUSB_INCLUDE_DIR}) diff --git a/cmake/c_flag_overrides.cmake b/cmake/c_flag_overrides.cmake index c15815e17..1a1d163fb 100644 --- a/cmake/c_flag_overrides.cmake +++ b/cmake/c_flag_overrides.cmake @@ -1,7 +1,7 @@ -if(MSVC) +if (MSVC) message(STATUS "MSVC C Flags override to /MT") set(CMAKE_C_FLAGS_DEBUG_INIT "/D_DEBUG /MTd /Zi /Ob0 /Od /RTC1") set(CMAKE_C_FLAGS_MINSIZEREL_INIT "/MT /O1 /Ob1 /D NDEBUG") set(CMAKE_C_FLAGS_RELEASE_INIT "/MT /O2 /Ob2 /D NDEBUG") set(CMAKE_C_FLAGS_RELWITHDEBINFO_INIT "/MT /Zi /O2 /Ob1 /D NDEBUG") -endif() +endif () diff --git a/cmake/c_flags.cmake b/cmake/c_flags.cmake index fbadd6d9e..c7954bf54 100644 --- a/cmake/c_flags.cmake +++ b/cmake/c_flags.cmake @@ -11,7 +11,7 @@ function(add_cflag_if_supported flag) if (C_SUPPORTS${flagclean}) set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${flag}" PARENT_SCOPE) - endif() + endif () endfunction() add_cflag_if_supported("-std=gnu11") @@ -41,10 +41,10 @@ if (NOT WIN32) add_cflag_if_supported("-fPIC") endif () -if(${CMAKE_BUILD_TYPE} MATCHES "Debug") +if (${CMAKE_BUILD_TYPE} MATCHES "Debug") add_cflag_if_supported("-ggdb") add_cflag_if_supported("-O0") else() add_cflag_if_supported("-O2") add_cflag_if_supported("-Werror") -endif() +endif () diff --git a/cmake/cpack_config.cmake b/cmake/cpack_config.cmake index b8d4be186..c70cf3a63 100644 --- a/cmake/cpack_config.cmake +++ b/cmake/cpack_config.cmake @@ -1,27 +1,27 @@ -set (CPACK_PACKAGE_NAME ${PROJECT_NAME}) -set (CPACK_PACKAGE_VERSION ${PROJECT_VERSION}) -set (CPACK_SET_DESTDIR "ON") +set(CPACK_PACKAGE_NAME ${PROJECT_NAME}) +set(CPACK_PACKAGE_VERSION ${PROJECT_VERSION}) +set(CPACK_SET_DESTDIR "ON") if (APPLE) set(CPACK_GENERATOR "ZIP") set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-macosx-amd64") file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/osx") - set (CPACK_INSTALL_PREFIX "") + set(CPACK_INSTALL_PREFIX "") set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/osx") elseif (WIN32) set(CPACK_GENERATOR "ZIP") file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/windows") - set (CPACK_INSTALL_PREFIX "") + set(CPACK_INSTALL_PREFIX "") set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/windows") elseif (${CMAKE_SYSTEM_NAME} STREQUAL "Linux" AND EXISTS "/etc/debian_version") message(STATUS "Debian-based Linux OS detected") set(CPACK_GENERATOR "DEB") if ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "x86_64") set(CPACK_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${PROJECT_VERSION}-amd64" ) - endif() + endif () set(CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/stlink-org/stlink") set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Luca Boccassi") set(CPACK_PACKAGE_CONTACT "bluca@debian.org") set(CPACK_DEBIAN_PACKAGE_DESCRIPTION "STM32 STlink programmer tools") -endif() +endif () diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/FindLibUSB.cmake index dc90bcc32..1fd465e4b 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/FindLibUSB.cmake @@ -77,7 +77,7 @@ else () # all other OS LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS /usr /usr/local /opt ) -endif() +endif () include(FindPackageHandleStandardArgs) FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) diff --git a/cmake/modules/pandocology.cmake b/cmake/modules/pandocology.cmake index 763eae558..ff9053197 100644 --- a/cmake/modules/pandocology.cmake +++ b/cmake/modules/pandocology.cmake @@ -42,10 +42,10 @@ include(CMakeParseArguments) -if(NOT EXISTS ${PANDOC_EXECUTABLE}) +if (NOT EXISTS ${PANDOC_EXECUTABLE}) find_program(PANDOC_EXECUTABLE pandoc) mark_as_advanced(PANDOC_EXECUTABLE) -endif() +endif () ############################################################################### # Based on code from UseLATEX @@ -133,7 +133,7 @@ This process created the file `CMakeCache.txt' and the directory `CMakeFiles'. Please delete them: $ rm -r CMakeFiles/ CmakeCache.txt ") - ENDIF() + ENDif () endfunction() # This builds a document @@ -171,7 +171,7 @@ function(add_document target_name) if (NOT PANDOC_EXECUTABLE) message(WARNING "Pandoc not found. Install Pandoc (http://johnmacfarlane.net/pandoc/) or set cache variable PANDOC_EXECUTABLE.") return() - endif() + endif () set(options EXPORT_ARCHIVE NO_EXPORT_PRODUCT EXPORT_PDF DIRECT_TEX_TO_PDF VERBOSE) set(oneValueArgs PRODUCT_DIRECTORY) @@ -188,29 +188,29 @@ function(add_document target_name) if (NOT "${target_extension}" STREQUAL ".tex" AND NOT "${target_extension}" STREQUAL ".latex") # if (NOT "${target_extension}" STREQUAL ".tex") MESSAGE(FATAL_ERROR "Target '${target_name}': Cannot use 'EXPORT_PDF' for target of type '${target_extension}': target type must be '.tex' or '.latex'") - endif() - endif() + endif () + endif () if (${ADD_DOCUMENT_DIRECT_TEX_TO_PDF}) list(LENGTH ${ADD_DOCUMENT_SOURCES} SOURCE_LEN) if (SOURCE_LEN GREATER 1) MESSAGE(FATAL_ERROR "Target '${target_name}': Only one source can be specified when using the 'DIRECT_TEX_TO_PDF' option") - endif() + endif () # set(ADD_DOCUMENT_SOURCES, list(GET ${ADD_DOCUMENT_SOURCES} 1)) pandocology_get_file_stemname(source_stemname ${ADD_DOCUMENT_SOURCES}) pandocology_get_file_extension(source_extension ${ADD_DOCUMENT_SOURCES}) if (NOT "${source_extension}" STREQUAL ".tex" AND NOT "${source_extension}" STREQUAL ".latex") MESSAGE(FATAL_ERROR "Target '${target_name}': Cannot use 'DIRECT_TEX_TO_PDF' for source of type '${source_extension}': source type must be '.tex' or '.latex'") - endif() + endif () SET(check_target ${source_stemname}.pdf) IF (NOT ${check_target} STREQUAL ${target_name}) MESSAGE(FATAL_ERROR "Target '${target_name}': Must use target name of '${check_target}' if using 'DIRECT_TEX_TO_PDF'") - endif() - endif() + endif () + endif () ## set up output directory if ("${ADD_DOCUMENT_PRODUCT_DIRECTORY}" STREQUAL "") set(ADD_DOCUMENT_PRODUCT_DIRECTORY "product") - endif() + endif () get_filename_component(product_directory ${CMAKE_BINARY_DIR}/${ADD_DOCUMENT_PRODUCT_DIRECTORY} ABSOLUTE) # get_filename_component(absolute_product_path ${product_directory}/${target_name} ABSOLUTE) @@ -232,7 +232,7 @@ function(add_document target_name) pandocology_add_input_dir(${CMAKE_CURRENT_SOURCE_DIR}/${resource_dir} ${CMAKE_CURRENT_BINARY_DIR} build_resources) if (${ADD_DOCUMENT_EXPORT_ARCHIVE}) pandocology_add_input_dir(${CMAKE_CURRENT_SOURCE_DIR}/${resource_dir} ${product_directory} exported_resources) - endif() + endif () endforeach() ## primary command @@ -255,7 +255,7 @@ function(add_document target_name) # we produce the target in the source directory, in case other build targets require it as a source COMMAND latexmk -gg -halt-on-error -interaction=nonstopmode -file-line-error -pdf ${build_sources} 2>/dev/null >/dev/null || (grep --no-messages -A8 ".*:[0-9]*:.*" ${target_stemname}.log && false) ) - endif() + endif () add_to_make_clean(${CMAKE_CURRENT_BINARY_DIR}/${target_name}) else() add_custom_command( @@ -267,7 +267,7 @@ function(add_document target_name) COMMAND ${PANDOC_EXECUTABLE} ${build_sources} ${ADD_DOCUMENT_PANDOC_DIRECTIVES} -o ${target_name} ) add_to_make_clean(${CMAKE_CURRENT_BINARY_DIR}/${target_name}) - endif() + endif () ## figure out what all is going to be produced by this build set, and set ## those as dependencies of the primary target @@ -275,14 +275,14 @@ function(add_document target_name) set(primary_target_dependencies ${primary_target_dependencies} ${CMAKE_CURRENT_BINARY_DIR}/${target_name}) if (NOT ${ADD_DOCUMENT_NO_EXPORT_PRODUCT}) set(primary_target_dependencies ${primary_target_dependencies} ${product_directory}/${target_name}) - endif() + endif () if (${ADD_DOCUMENT_EXPORT_PDF}) set(primary_target_dependencies ${primary_target_dependencies} ${CMAKE_CURRENT_BINARY_DIR}/${target_stemname}.pdf) set(primary_target_dependencies ${primary_target_dependencies} ${product_directory}/${target_stemname}.pdf) - endif() + endif () if (${ADD_DOCUMENT_EXPORT_ARCHIVE}) set(primary_target_dependencies ${primary_target_dependencies} ${product_directory}/${target_stemname}.tbz) - endif() + endif () ## primary target # # target cannot have same (absolute name) as dependencies: @@ -326,7 +326,7 @@ function(add_document target_name) ) add_to_make_clean(${CMAKE_CURRENT_BINARY_DIR}/${target_stemname}.pdf) add_to_make_clean(${product_directory}/${target_stemname}.pdf) - endif() + endif () ## copy products if (NOT ${ADD_DOCUMENT_NO_EXPORT_PRODUCT}) @@ -336,7 +336,7 @@ function(add_document target_name) COMMAND ${CMAKE_COMMAND} -E copy ${target_name} ${product_directory} ) add_to_make_clean(${product_directory}/${target_name}) - endif() + endif () ## copy resources if (${ADD_DOCUMENT_EXPORT_ARCHIVE}) @@ -359,7 +359,7 @@ function(add_document target_name) # ALL # DEPENDS ${product_directory}/${target_stemname}.tbz # ) - endif() + endif () endfunction(add_document) diff --git a/cmake/version.cmake b/cmake/version.cmake index fe778c419..d27b43515 100644 --- a/cmake/version.cmake +++ b/cmake/version.cmake @@ -27,7 +27,7 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") ) if (res EQUAL 1) - set (PROJECT_VERSION "${PROJECT_VERSION}-dirty") + set(PROJECT_VERSION "${PROJECT_VERSION}-dirty") endif () # strip a leading v off of the version as proceeding code expectes just the version numbering. @@ -57,7 +57,7 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") else(GIT_DESCRIBE_RESULT EQUAL 0) message(WARNING "git describe failed.") message(WARNING "${GIT_DESCRIBE_ERROR}") - endif(GIT_DESCRIBE_RESULT EQUAL 0) + endif (GIT_DESCRIBE_RESULT EQUAL 0) else () message(STATUS "Git or repo not found.") endif () diff --git a/cmake_uninstall.cmake.in b/cmake_uninstall.cmake.in index ed17c45cd..0c9f6a437 100644 --- a/cmake_uninstall.cmake.in +++ b/cmake_uninstall.cmake.in @@ -1,6 +1,6 @@ -if(NOT EXISTS "@CMAKE_BINARY_DIR@/install_manifest.txt") +if (NOT EXISTS "@CMAKE_BINARY_DIR@/install_manifest.txt") message(FATAL_ERROR "Cannot find install manifest: @CMAKE_BINARY_DIR@/install_manifest.txt") -endif() +endif () file(READ "@CMAKE_BINARY_DIR@/install_manifest.txt" files) string(REGEX REPLACE "\n" ";" files "${files}") diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 5b435c022..090a2237e 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -23,7 +23,7 @@ foreach (manpage ${MANPAGES}) set(f "${CMAKE_CURRENT_SOURCE_DIR}/${manpage}.1") else() message(AUTHOR_WARNING "Manpage ${manpage} not generated") - endif() + endif () if (f AND NOT WIN32) install(FILES ${f} DESTINATION ${CMAKE_INSTALL_PREFIX}/share/man/man1) diff --git a/src/common.c b/src/common.c index d04644071..e94240351 100644 --- a/src/common.c +++ b/src/common.c @@ -546,7 +546,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { stlink_write_debug32(sl, cr_reg, val); } - if(v) + if (v) val |= cr_mer; else val &= ~cr_mer; @@ -905,7 +905,7 @@ int stlink_load_device_params(stlink_t *sl) { sl->flash_size = (flash_size & 0xff) * 1024; } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_HIGH) { // 0 is 384k and 1 is 256k - if ( flash_size == 0 ) { + if ( flash_size == 0){ sl->flash_size = 384 * 1024; } else { sl->flash_size = 256 * 1024; @@ -923,7 +923,7 @@ int stlink_load_device_params(stlink_t *sl) { //medium and low devices have the same chipid. ram size depends on flash size. //STM32F100xx datasheet Doc ID 16455 Table 2 - if(sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){ + if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){ sl->sram_size = 0x1000; } @@ -1091,7 +1091,7 @@ int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem8 ***\n"); - if (len > 0x40 ) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour + if (len > 0x40){ // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour fprintf(stderr, "Error: Data length > 64: +%d byte.\n", len); abort(); @@ -1374,7 +1374,7 @@ static void md5_calculate(mapped_file_t *mf) { Md5Update(&md5Context, mf->base, (uint32_t)mf->len); Md5Finalise(&md5Context, &md5Hash); printf("md5 checksum: "); - for(int i = 0; i < (int) sizeof(md5Hash); i++) { + for (int i = 0; i < (int) sizeof(md5Hash); i++) { printf("%x", md5Hash.bytes[i]); } printf(", "); @@ -1426,7 +1426,7 @@ int stlink_mwrite_sram(stlink_t * sl, uint8_t* data, uint32_t length, stm32_addr len = length; - if(len & 3) { + if (len & 3) { len -= len & 3; } @@ -1445,7 +1445,7 @@ int stlink_mwrite_sram(stlink_t * sl, uint8_t* data, uint32_t length, stm32_addr stlink_write_mem32(sl, addr + (uint32_t) off, size); } - if(length > len) { + if (length > len) { memcpy(sl->q_buf, data + len, length - len); stlink_write_mem8(sl, addr + (uint32_t) len, length - len); } @@ -1492,7 +1492,7 @@ int stlink_fwrite_sram(stlink_t * sl, const char* path, stm32_addr_t addr) { len = mf.len; - if(len & 3) { + if (len & 3) { len -= len & 3; } @@ -1511,7 +1511,7 @@ int stlink_fwrite_sram(stlink_t * sl, const char* path, stm32_addr_t addr) { stlink_write_mem32(sl, addr + (uint32_t) off, size); } - if(mf.len > len) { + if (mf.len > len) { memcpy(sl->q_buf, mf.base + len, mf.len - len); stlink_write_mem8(sl, addr + (uint32_t) len, mf.len - len); } @@ -1595,7 +1595,7 @@ struct stlink_fread_ihex_worker_arg { static bool stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg* the_arg) { uint32_t addr = the_arg->addr; uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + (uint8_t)((addr & 0x00FF0000) >> 16); - if(17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", (addr & 0xFFFF0000) >> 16, (uint8_t)(0x100 - sum))) + if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", (addr & 0xFFFF0000) >> 16, (uint8_t)(0x100 - sum))) return false; the_arg->lba = (addr & 0xFFFF0000); @@ -1605,26 +1605,26 @@ static bool stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg* th static bool stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg* the_arg) { uint8_t count = the_arg->buf_pos; - if(count == 0) return true; + if (count == 0) return true; uint32_t addr = the_arg->addr; - if(the_arg->lba != (addr & 0xFFFF0000)) { // segment changed - if(!stlink_fread_ihex_newsegment(the_arg)) return false; + if (the_arg->lba != (addr & 0xFFFF0000)) { // segment changed + if (!stlink_fread_ihex_newsegment(the_arg)) return false; } uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + (uint8_t)(addr & 0x000000FF); - if(9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) + if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) return false; - for(uint8_t i = 0; i < count; ++i) { + for (uint8_t i = 0; i < count; ++i) { uint8_t b = the_arg->buf[i]; sum += b; - if(2 != fprintf(the_arg->file, "%02X", b)) + if (2 != fprintf(the_arg->file, "%02X", b)) return false; } - if(4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) + if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) return false; the_arg->addr += count; @@ -1645,9 +1645,9 @@ static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg* the_arg, static bool stlink_fread_ihex_worker(void* arg, uint8_t* block, ssize_t len) { struct stlink_fread_ihex_worker_arg* the_arg = (struct stlink_fread_ihex_worker_arg*)arg; - for(ssize_t i = 0; i < len; ++i) { - if(the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full - if(!stlink_fread_ihex_writeline(the_arg)) return false; + for (ssize_t i = 0; i < len; ++i) { + if (the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full + if (!stlink_fread_ihex_writeline(the_arg)) return false; } the_arg->buf[the_arg->buf_pos++] = block[i]; @@ -1657,11 +1657,11 @@ static bool stlink_fread_ihex_worker(void* arg, uint8_t* block, ssize_t len) { } static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg* the_arg) { - if(!stlink_fread_ihex_writeline(the_arg)) return false; + if (!stlink_fread_ihex_writeline(the_arg)) return false; // FIXME do we need the Start Linear Address? - if(13 != fprintf(the_arg->file, ":00000001FF\r\n")) // EoF + if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) // EoF return false; return (0 == fclose(the_arg->file)); @@ -1678,11 +1678,11 @@ int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr return -1; } - if(is_ihex) { + if (is_ihex) { struct stlink_fread_ihex_worker_arg arg; - if(stlink_fread_ihex_init(&arg, fd, addr)) { + if (stlink_fread_ihex_init(&arg, fd, addr)) { error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); - if(!stlink_fread_ihex_finalize(&arg)) + if (!stlink_fread_ihex_finalize(&arg)) error = -1; } else { @@ -1722,18 +1722,18 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ flashaddr -= 0x100000; } if (flashaddr<0x4000) return (offset + 0); - else if(flashaddr<0x8000) return(offset + 1); - else if(flashaddr<0xc000) return(offset + 2); - else if(flashaddr<0x10000) return(offset + 3); - else if(flashaddr<0x20000) return(offset + 4); + else if (flashaddr<0x8000) return(offset + 1); + else if (flashaddr<0xc000) return(offset + 2); + else if (flashaddr<0x10000) return(offset + 3); + else if (flashaddr<0x20000) return(offset + 4); else return offset + (flashaddr/0x20000) +4; } uint32_t calculate_F7_sectornum(uint32_t flashaddr){ flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address - if(flashaddr<0x20000) return(flashaddr/0x8000); - else if(flashaddr<0x40000) return(4); + if (flashaddr<0x20000) return(flashaddr/0x8000); + else if (flashaddr<0x40000) return(4); else return(flashaddr/0x40000) +4; } @@ -1778,14 +1778,14 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ sector -= 12; } if (sector<4) sl->flash_pgsz=0x4000; - else if(sector<5) sl->flash_pgsz=0x10000; + else if (sector<5) sl->flash_pgsz=0x10000; else sl->flash_pgsz=0x20000; } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { uint32_t sector=calculate_F7_sectornum(flashaddr); if (sector<4) sl->flash_pgsz=0x8000; - else if(sector<5) sl->flash_pgsz=0x20000; + else if (sector<5) sl->flash_pgsz=0x20000; else sl->flash_pgsz=0x40000; } return (uint32_t) sl->flash_pgsz; @@ -1866,7 +1866,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) /* check if the locks are set */ stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if((val & (1<<0))||(val & (1<<1))) { + if ((val & (1<<0))||(val & (1<<1))) { /* disable pecr protection */ stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef); stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405); @@ -1903,7 +1903,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) */ do { stlink_read_debug32(sl, STM32L_FLASH_SR, &val) - } while((val & (1 << 0)) != 0); + } while ((val & (1 << 0)) != 0); #endif /* fix_to_be_confirmed */ @@ -2265,7 +2265,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t (sl->chip_id != STLINK_CHIPID_STM32_L496X) && (sl->chip_id != STLINK_CHIPID_STM32_L4RX)) { - if( sl->version.stlink_v == 1 ) { + if ( sl->version.stlink_v == 1){ printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes on F4 devices\n"); write_flash_cr_psiz(sl, 2); } @@ -2299,7 +2299,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t set_flash_cr_pg(sl); size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; - for(off = 0; off < len;) { + for (off = 0; off < len;) { size_t size = len - off > buf_size ? buf_size : len - off; printf("size: %u\n", (unsigned int)size); @@ -2483,11 +2483,11 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t // note: length not checked static uint8_t stlink_parse_hex(const char* hex) { uint8_t d[2]; - for(int i = 0; i < 2; ++i) { + for (int i = 0; i < 2; ++i) { char c = *(hex + i); - if(c >= '0' && c <= '9') d[i] = c - '0'; - else if(c >= 'A' && c <= 'F') d[i] = c - 'A' + 10; - else if(c >= 'a' && c <= 'f') d[i] = c - 'a' + 10; + if (c >= '0' && c <= '9') d[i] = c - '0'; + else if (c >= 'A' && c <= 'F') d[i] = c - 'A' + 10; + else if (c >= 'a' && c <= 'f') d[i] = c - 'a' + 10; else return 0; // error } return (d[0] << 4) | (d[1]); @@ -2500,15 +2500,15 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, uint32_t end = 0; bool eof_found = false; - for(int scan = 0; (res == 0) && (scan < 2); ++scan) { // parse file two times - first to find memory range, second - to fill it - if(scan == 1) { - if(!eof_found) { + for (int scan = 0; (res == 0) && (scan < 2); ++scan) { // parse file two times - first to find memory range, second - to fill it + if (scan == 1) { + if (!eof_found) { ELOG("No EoF recond\n"); res = -1; break; } - if(*begin >= end) { + if (*begin >= end) { ELOG("No data found in file\n"); res = -1; break; @@ -2516,7 +2516,7 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, *size = (end - *begin) + 1; data = calloc(*size, 1); // use calloc to get NULL if out of memory - if(!data) { + if (!data) { ELOG("Cannot allocate %d bytes\n", *size); res = -1; break; @@ -2526,7 +2526,7 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, } FILE* file = fopen(path, "r"); - if(!file) { + if (!file) { ELOG("Cannot open file\n"); res = -1; break; @@ -2535,17 +2535,17 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, uint32_t lba = 0; char line[1 + 5*2 + 255*2 + 2]; - while(fgets(line, sizeof(line), file)) { - if(line[0] == '\n' || line[0] == '\r') continue; // skip empty lines - if(line[0] != ':') { // no marker - wrong file format + while (fgets(line, sizeof(line), file)) { + if (line[0] == '\n' || line[0] == '\r') continue; // skip empty lines + if (line[0] != ':') { // no marker - wrong file format ELOG("Wrong file format - no marker\n"); res = -1; break; } size_t l = strlen(line); - while(l > 0 && (line[l-1] == '\n' || line[l-1] == '\r')) --l; // trim EoL - if((l < 11) || (l == (sizeof(line)-1))) { // line too short or long - wrong file format + while (l > 0 && (line[l-1] == '\n' || line[l-1] == '\r')) --l; // trim EoL + if ((l < 11) || (l == (sizeof(line)-1))) { // line too short or long - wrong file format ELOG("Wrong file format - wrong line length\n"); res = -1; break; @@ -2553,17 +2553,17 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, // check sum uint8_t chksum = 0; - for(size_t i = 1; i < l; i += 2) { + for (size_t i = 1; i < l; i += 2) { chksum += stlink_parse_hex(line + i); } - if(chksum != 0) { + if (chksum != 0) { ELOG("Wrong file format - checksum mismatch\n"); res = -1; break; } uint8_t reclen = stlink_parse_hex(line + 1); - if(((uint32_t)reclen + 5)*2 + 1 != l) { + if (((uint32_t)reclen + 5)*2 + 1 != l) { ELOG("Wrong file format - record length mismatch\n"); res = -1; break; @@ -2574,17 +2574,17 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, switch(rectype) { case 0: // data - if(scan == 0) { + if (scan == 0) { uint32_t b = lba + offset; uint32_t e = b + reclen - 1; - if(b < *begin) *begin = b; - if(e > end) end = e; + if (b < *begin) *begin = b; + if (e > end) end = e; } else { - for(uint8_t i = 0; i < reclen; ++i) { + for (uint8_t i = 0; i < reclen; ++i) { uint8_t b = stlink_parse_hex(line + 9 + i*2); uint32_t addr = lba + offset + i; - if(addr >= *begin && addr <= end) { + if (addr >= *begin && addr <= end) { data[addr - *begin] = b; } } @@ -2604,7 +2604,7 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, break; case 4: // Extended Linear Address - if(reclen == 2) { + if (reclen == 2) { lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | ((uint32_t)stlink_parse_hex(line + 11) << 16); } else { @@ -2620,13 +2620,13 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, ELOG("Wrong file format - unexpected record type %d\n", rectype); res = -1; } - if(res != 0) break; + if (res != 0) break; } fclose(file); } - if(res == 0) { + if (res == 0) { *mem = data; } else { @@ -2655,14 +2655,14 @@ int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr */ if (sl->opt) { idx = (unsigned int)length; - for(num_empty = 0; num_empty != length; ++num_empty) { + for (num_empty = 0; num_empty != length; ++num_empty) { if (data[--idx] != erased_pattern) { break; } } /* Round down to words */ num_empty -= (num_empty & 3); - if(num_empty != 0) { + if (num_empty != 0) { ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); } } else { @@ -2704,14 +2704,14 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { if (sl->opt) { idx = (unsigned int) mf.len; - for(num_empty = 0; num_empty != mf.len; ++num_empty) { + for (num_empty = 0; num_empty != mf.len; ++num_empty) { if (mf.base[--idx] != erased_pattern) { break; } } /* Round down to words */ num_empty -= (num_empty & 3); - if(num_empty != 0) { + if (num_empty != 0) { ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); } } else { @@ -2740,7 +2740,7 @@ static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t l uint32_t val; - if(len != 4) { + if (len != 4) { ELOG("Wrong length for writing option bytes, must be 4 is %d\n", len); return -1; } @@ -2749,7 +2749,7 @@ static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t l stlink_core_id(sl); /* Check if chip is supported and for correct address */ - if(sl->chip_id != STLINK_CHIPID_STM32_G0_CAT1 && + if (sl->chip_id != STLINK_CHIPID_STM32_G0_CAT1 && sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2) { ELOG("Option bytes writing is currently only supported for the STM32G0\n"); return -1; @@ -2833,7 +2833,7 @@ static int stlink_write_option_bytes_l0_cat2(stlink_t *sl, uint8_t* base, uint32 uint32_t val; - if(len != 4) { + if (len != 4) { ELOG("Wrong length for writting option bytes, must be 4 is %d\n", len); return -1; } @@ -2891,7 +2891,7 @@ static int stlink_write_option_bytes_l1(stlink_t *sl, uint8_t* base, stm32_addr_ uint32_t val; uint32_t data; - if(len != 4 && len != 8) { + if (len != 4 && len != 8) { ELOG("Wrong length for writting option bytes, must be 4 or 8 is %d\n", len); return -1; } @@ -2932,7 +2932,7 @@ static int stlink_write_option_bytes_l1(stlink_t *sl, uint8_t* base, stm32_addr_ /* Write options bytes */ write_uint32((unsigned char*) &data, *(uint32_t*) (base)); - if( data != val ) { + if ( data != val ) { WLOG("Writing option bytes 0x%04x\n", data); stlink_write_debug32(sl, addr, data); stlink_read_debug32(sl, addr, &val); @@ -2940,7 +2940,7 @@ static int stlink_write_option_bytes_l1(stlink_t *sl, uint8_t* base, stm32_addr_ } - if(len==8) { + if (len==8) { /* Clear errors */ stlink_write_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_SR_OFF, 0x00003F00); @@ -2949,7 +2949,7 @@ static int stlink_write_option_bytes_l1(stlink_t *sl, uint8_t* base, stm32_addr_ /* Write options bytes */ write_uint32((unsigned char*) &data, *(uint32_t*) (base+4)); - if( data != val ) { + if ( data != val ) { WLOG("Writing 2nd option bytes 0x%04x\n", data); stlink_write_debug32(sl, addr+4, data); stlink_read_debug32(sl, addr+4, &val); @@ -2976,7 +2976,7 @@ static int stlink_write_option_bytes_l496x(stlink_t *sl, uint8_t* base, uint32_t uint32_t val; - if(len != 4) { + if (len != 4) { ELOG("Wrong length for writting option bytes, must be 4 is %d\n", len); return -1; } @@ -3082,7 +3082,7 @@ static int stlink_write_option_bytes_f2(stlink_t *sl, uint32_t option_byte) { stlink_read_debug32(sl, FLASH_F2_SR, &val); WLOG("wait BSY flag to be 0\n"); - while(val & 0x00010000){ + while (val & 0x00010000){ stlink_read_debug32(sl, FLASH_F2_SR, &val); } WLOG("BSY flag is 0\n"); @@ -3132,7 +3132,7 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint32_t option_byte) { stlink_read_debug32(sl, FLASH_F4_SR, &val); WLOG("wait BSY flag to be 0\n"); - while(val & 0x00010000){ + while (val & 0x00010000){ stlink_read_debug32(sl, FLASH_F4_SR, &val); } WLOG("BSY flag is 0\n"); @@ -3228,17 +3228,17 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui WLOG("Option bytes write chip_id 0x%08x addr 0x%08x\n",sl->chip_id,addr); /* Check if chip is supported and for correct address */ - if(((sl->chip_id == STLINK_CHIPID_STM32_G0_CAT1) || + if (((sl->chip_id == STLINK_CHIPID_STM32_G0_CAT1) || (sl->chip_id == STLINK_CHIPID_STM32_G0_CAT2)) && (addr == STM32_G0_OPTION_BYTES_BASE)) { return stlink_write_option_bytes_g0x(sl, base, len); } - else if((sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) && (addr == STM32_L0_CAT2_OPTION_BYTES_BASE)) { + else if ((sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) && (addr == STM32_L0_CAT2_OPTION_BYTES_BASE)) { return stlink_write_option_bytes_l0_cat2(sl, base, len); } - else if((sl->chip_id == STLINK_CHIPID_STM32_L496X) && (addr == STM32_L496X_OPTION_BYTES_BASE)) { + else if ((sl->chip_id == STLINK_CHIPID_STM32_L496X) && (addr == STM32_L496X_OPTION_BYTES_BASE)) { return stlink_write_option_bytes_l496x(sl, base, len); } - else if(((sl->chip_id == STLINK_CHIPID_STM32_L152_RE) || (sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH) ) && + else if (((sl->chip_id == STLINK_CHIPID_STM32_L152_RE) || (sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH) ) && ((addr == STM32_L1_OPTION_BYTES_BASE) || (addr == STM32_L1_OPTION_BYTES_BASE+4))) { return stlink_write_option_bytes_l1(sl, base, addr, len); } @@ -3284,9 +3284,9 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr */ int stlink_fwrite_option_bytes_32bit(stlink_t *sl, uint32_t val) { - if(sl->chip_id == STLINK_CHIPID_STM32_F2){ + if (sl->chip_id == STLINK_CHIPID_STM32_F2){ return stlink_write_option_bytes_f2(sl, val); - }else if(sl->chip_id == STLINK_CHIPID_STM32_F446){ + } else if (sl->chip_id == STLINK_CHIPID_STM32_F446){ return stlink_write_option_bytes_f4(sl, val); } else diff --git a/src/flash_loader.c b/src/flash_loader.c index 9c24ff9e8..a1c9c3757 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -226,7 +226,7 @@ static int loader_v_dependent_assignment(stlink_t *sl, { int retval = 0; - if( sl->version.stlink_v == 1 ) { + if ( sl->version.stlink_v == 1){ printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes\n"); *loader_code = high_v_loader; *loader_size = high_v_loader_size; diff --git a/src/gdbserver/gdb-remote.c b/src/gdbserver/gdb-remote.c index e4aad312d..3b1794f3e 100644 --- a/src/gdbserver/gdb-remote.c +++ b/src/gdbserver/gdb-remote.c @@ -27,7 +27,7 @@ int gdb_send_packet(int fd, char* data) { packet[0] = '$'; uint8_t cksum = 0; - for(unsigned int i = 0; i < data_length; i++) { + for (unsigned int i = 0; i < data_length; i++) { packet[i + 1] = data[i]; cksum += data[i]; } @@ -36,19 +36,19 @@ int gdb_send_packet(int fd, char* data) { packet[length - 2] = hex[cksum >> 4]; packet[length - 1] = hex[cksum & 0xf]; - while(1) { - if(write(fd, packet, length) != length) { + while (1) { + if (write(fd, packet, length) != length) { free(packet); return -2; } char ack; - if(read(fd, &ack, 1) != 1) { + if (read(fd, &ack, 1) != 1) { free(packet); return -2; } - if(ack == '+') { + if (ack == '+') { free(packet); return 0; } @@ -64,7 +64,7 @@ int gdb_recv_packet(int fd, char** buffer) { char* packet_buffer = malloc(packet_size); unsigned state; - if(packet_buffer == NULL) + if (packet_buffer == NULL) return -2; start: @@ -79,15 +79,15 @@ int gdb_recv_packet(int fd, char** buffer) { */ char c; - while(state != 4) { - if(read(fd, &c, 1) != 1) { + while (state != 4) { + if (read(fd, &c, 1) != 1) { free(packet_buffer); return -2; } switch(state) { case 0: - if(c != '$') { + if (c != '$') { // ignore } else { state = 1; @@ -95,16 +95,16 @@ int gdb_recv_packet(int fd, char** buffer) { break; case 1: - if(c == '#') { + if (c == '#') { state = 2; } else { packet_buffer[packet_idx++] = c; cksum += c; - if(packet_idx == packet_size) { + if (packet_idx == packet_size) { packet_size += ALLOC_STEP; void* p = realloc(packet_buffer, packet_size); - if(p != NULL) + if (p != NULL) packet_buffer = p; else { free(packet_buffer); @@ -127,9 +127,9 @@ int gdb_recv_packet(int fd, char** buffer) { } uint8_t recv_cksum_int = strtoul(recv_cksum, NULL, 16); - if(recv_cksum_int != cksum) { + if (recv_cksum_int != cksum) { char nack = '-'; - if(write(fd, &nack, 1) != 1) { + if (write(fd, &nack, 1) != 1) { free(packet_buffer); return -2; } @@ -137,7 +137,7 @@ int gdb_recv_packet(int fd, char** buffer) { goto start; } else { char ack = '+'; - if(write(fd, &ack, 1) != 1) { + if (write(fd, &ack, 1) != 1) { free(packet_buffer); return -2; } @@ -157,13 +157,13 @@ int gdb_check_for_interrupt(int fd) { pfd.fd = fd; pfd.events = POLLIN; - if(poll(&pfd, 1, 0) != 0) { + if (poll(&pfd, 1, 0) != 0) { char c; - if(read(fd, &c, 1) != 1) + if (read(fd, &c, 1) != 1) return -2; - if(c == '\x03') // ^C + if (c == '\x03') // ^C return 1; } diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 9cff5f917..1c45c2538 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -89,10 +89,10 @@ static stlink_t* do_connect(st_state_t *st) { stlink_t *ret = NULL; switch (st->stlink_version) { case 2: - if(serial_specified){ + if (serial_specified){ ret = stlink_open_usb(st->logging_level, st->reset, serialnumber); } - else{ + else { ret = stlink_open_usb(st->logging_level, st->reset, NULL); } break; @@ -199,8 +199,8 @@ int parse_options(int argc, char** argv, st_state_t *st) { /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ int j = (int)strlen(optarg); int length = j / 2; //the length of the destination-array - if(j % 2 != 0) return -1; - for(size_t k = 0; j >= 0 && k < sizeof(serialnumber); ++k, j -= 2) { + if (j % 2 != 0) return -1; + for (size_t k = 0; j >= 0 && k < sizeof(serialnumber); ++k, j -= 2) { char buffer[3] = {0}; memcpy(buffer, optarg + j, 2); serialnumber[length - k] = (uint8_t)strtol(buffer, NULL, 16); @@ -234,7 +234,7 @@ int main(int argc, char** argv) { printf("st-util %s\n", STLINK_VERSION); sl = do_connect(&state); - if(sl == NULL) return 1; + if (sl == NULL) return 1; connected_stlink = sl; signal(SIGINT, &cleanup); @@ -255,7 +255,7 @@ int main(int argc, char** argv) { #if defined(__MINGW32__) || defined(_MSC_VER) WSADATA wsadata; - if (WSAStartup(MAKEWORD(2,2),&wsadata) !=0 ) { + if (WSAStartup(MAKEWORD(2,2),&wsadata) !=0){ goto winsock_error; } #endif @@ -532,27 +532,27 @@ char* make_memory_map(stlink_t *sl) { char* map = malloc(sz); map[0] = '\0'; - if(sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F446 || sl->chip_id==STLINK_CHIPID_STM32_F411RE) { + if (sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F446 || sl->chip_id==STLINK_CHIPID_STM32_F411RE) { strcpy(map, memory_map_template_F4); - } else if(sl->chip_id==STLINK_CHIPID_STM32_F4_DE) { + } else if (sl->chip_id==STLINK_CHIPID_STM32_F4_DE) { strcpy(map, memory_map_template_F4_DE); - } else if(sl->core_id==STM32F7_CORE_ID) { + } else if (sl->core_id==STM32F7_CORE_ID) { snprintf(map, sz, memory_map_template_F7, (unsigned int)sl->sram_size); - } else if(sl->chip_id==STLINK_CHIPID_STM32_F4_HD) { + } else if (sl->chip_id==STLINK_CHIPID_STM32_F4_HD) { strcpy(map, memory_map_template_F4_HD); - } else if(sl->chip_id==STLINK_CHIPID_STM32_F2) { + } else if (sl->chip_id==STLINK_CHIPID_STM32_F2) { snprintf(map, sz, memory_map_template_F2, (unsigned int)sl->flash_size, (unsigned int)sl->sram_size, (unsigned int)sl->flash_size - 0x20000, (unsigned int)sl->sys_base, (unsigned int)sl->sys_size); - } else if((sl->chip_id==STLINK_CHIPID_STM32_L4) || + } else if ((sl->chip_id==STLINK_CHIPID_STM32_L4) || (sl->chip_id==STLINK_CHIPID_STM32_L43X) || (sl->chip_id==STLINK_CHIPID_STM32_L46X)) { snprintf(map, sz, memory_map_template_L4, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if(sl->chip_id==STLINK_CHIPID_STM32_L496X) { + } else if (sl->chip_id==STLINK_CHIPID_STM32_L496X) { snprintf(map, sz, memory_map_template_L496, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); } else { @@ -603,7 +603,7 @@ static void init_data_watchpoints(stlink_t *sl) { stlink_write_debug32(sl, 0xE000EDFC, data); // make sure all watchpoints are cleared - for(int i = 0; i < DATA_WATCH_NUM; i++) { + for (int i = 0; i < DATA_WATCH_NUM; i++) { data_watches[i].fun = WATCHDISABLED; stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); } @@ -620,15 +620,15 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, mask = -1; i = len; - while(i) { + while (i) { i >>= 1; mask++; } - if((mask != (uint32_t)-1) && (mask < 16)) { - for(i = 0; i < DATA_WATCH_NUM; i++) { + if ((mask != (uint32_t)-1) && (mask < 16)) { + for (i = 0; i < DATA_WATCH_NUM; i++) { // is this an empty slot ? - if(data_watches[i].fun == WATCHDISABLED) { + if (data_watches[i].fun == WATCHDISABLED) { DLOG("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len); data_watches[i].fun = wf; @@ -659,8 +659,8 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { int i; - for(i = 0 ; i < DATA_WATCH_NUM; i++) { - if((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) { + for (i = 0 ; i < DATA_WATCH_NUM; i++) { + if ((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) { DLOG("delete watchpoint %d addr %x\n", i, addr); data_watches[i].fun = WATCHDISABLED; @@ -698,7 +698,7 @@ static void init_code_breakpoints(stlink_t *sl) { ILOG("Found %i hw breakpoint registers\n", code_break_num); - for(int i = 0; i < code_break_num; i++) { + for (int i = 0; i < code_break_num; i++) { code_breaks[i].type = 0; stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMP0 + i * 4, 0); } @@ -706,7 +706,7 @@ static void init_code_breakpoints(stlink_t *sl) { static int has_breakpoint(stm32_addr_t addr) { - for(int i = 0; i < code_break_num; i++) { + for (int i = 0; i < code_break_num; i++) { if (code_breaks[i].addr == addr) { return 1; } @@ -719,7 +719,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { uint32_t mask; int type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW; - if(addr & 1) { + if (addr & 1) { ELOG("update_code_breakpoint: unaligned address %08x\n", addr); return -1; } @@ -731,16 +731,16 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { } int id = -1; - for(int i = 0; i < code_break_num; i++) { - if(fpb_addr == code_breaks[i].addr || + for (int i = 0; i < code_break_num; i++) { + if (fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { id = i; break; } } - if(id == -1) { - if(set) return -1; // Free slot not found + if (id == -1) { + if (set) return -1; // Free slot not found else return 0; // Breakpoint is already removed } @@ -749,18 +749,18 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { bp->addr = fpb_addr; if (sl->core_id==STM32F7_CORE_ID) { - if(set) bp->type = type; + if (set) bp->type = type; else bp->type = 0; mask = (bp->addr) | 1; } else { - if(set) bp->type |= type; + if (set) bp->type |= type; else bp->type &= ~type; mask = (bp->addr) | 1 | (bp->type << 30); } - if(bp->type == 0) { + if (bp->type == 0) { DLOG("clearing hw break %d\n", id); stlink_write_debug32(sl, 0xe0002008 + id * 4, 0); @@ -789,13 +789,13 @@ static struct flash_block* flash_root; static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { - if(addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) { + if (addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) { ELOG("flash_add_block: incorrect bounds\n"); return -1; } stlink_calculate_pagesize(sl, addr); - if(addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) { + if (addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) { ELOG("flash_add_block: unaligned block\n"); return -1; } @@ -815,7 +815,7 @@ static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { unsigned int fit_blocks = 0, fit_length = 0; - for(struct flash_block* fb = flash_root; fb; fb = fb->next) { + for (struct flash_block* fb = flash_root; fb; fb = fb->next) { /* Block: ------X------Y-------- * Data: a-----b * a--b @@ -826,7 +826,7 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { unsigned X = fb->addr, Y = fb->addr + fb->length; unsigned a = addr, b = addr + length; - if(a < Y && b > X) { + if (a < Y && b > X) { // from start of the block unsigned start = (a > X ? a : X) - X; unsigned end = (b > Y ? Y : b) - X; @@ -838,12 +838,12 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { } } - if(fit_blocks == 0) { + if (fit_blocks == 0) { ELOG("Unfit data block %08x -> %04x\n", addr, length); return -1; } - if(fit_length != length) { + if (fit_length != length) { WLOG("data block %08x -> %04x truncated to %04x\n", addr, length, fit_length); WLOG("(this is not an error, just a GDB glitch)\n"); @@ -859,10 +859,10 @@ static int flash_go(stlink_t *sl) { stlink_reset(sl); stlink_force_debug(sl); - for(struct flash_block* fb = flash_root; fb; fb = fb->next) { + for (struct flash_block* fb = flash_root; fb; fb = fb->next) { DLOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length); - for(stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += (uint32_t)FLASH_PAGE) { + for (stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += (uint32_t)FLASH_PAGE) { unsigned length = fb->length - (page - fb->addr); //Update FLASH_PAGE @@ -881,7 +881,7 @@ static int flash_go(stlink_t *sl) { error = 0; error: - for(struct flash_block* fb = flash_root, *next; fb; fb = next) { + for (struct flash_block* fb = flash_root, *next; fb; fb = next) { next = fb->next; free(fb->data); free(fb); @@ -956,7 +956,7 @@ static void init_cache (stlink_t *sl) { int i; /* Assume only F7 has a cache. */ - if(sl->core_id!=STM32F7_CORE_ID) + if (sl->core_id!=STM32F7_CORE_ID) return; stlink_read_debug32(sl, CLIDR, &clidr); @@ -972,14 +972,14 @@ static void init_cache (stlink_t *sl) { (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7); ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr, cache_desc.dminline, cache_desc.iminline); - for(i = 0; i < 7; i++) + for (i = 0; i < 7; i++) { unsigned int ct = (clidr >> (3 * i)) & 0x07; cache_desc.dcache[i].width = 0; cache_desc.icache[i].width = 0; - if(ct == 2 || ct == 3 || ct == 4) + if (ct == 2 || ct == 3 || ct == 4) { /* Data. */ stlink_write_debug32(sl, CSSELR, i << 1); @@ -987,7 +987,7 @@ static void init_cache (stlink_t *sl) { read_cache_level_desc(sl, &cache_desc.dcache[i]); } - if(ct == 1 || ct == 3) + if (ct == 1 || ct == 3) { /* Instruction. */ stlink_write_debug32(sl, CSSELR, (i << 1) | 1); @@ -1035,7 +1035,7 @@ static void cache_sync(stlink_t *sl) { unsigned ccr; - if(sl->core_id!=STM32F7_CORE_ID) + if (sl->core_id!=STM32F7_CORE_ID) return; if (!cache_modified) return; @@ -1063,7 +1063,7 @@ static size_t unhexify(const char *in, char *out, size_t out_count) int serve(stlink_t *sl, st_state_t *st) { SOCKET sock = socket(AF_INET, SOCK_STREAM, 0); - if(!IS_SOCK_VALID(sock)) { + if (!IS_SOCK_VALID(sock)) { perror("socket"); return 1; } @@ -1077,13 +1077,13 @@ int serve(stlink_t *sl, st_state_t *st) { serv_addr.sin_addr.s_addr = INADDR_ANY; serv_addr.sin_port = htons(st->listen_port); - if(bind(sock, (struct sockaddr *) &serv_addr, sizeof(serv_addr)) < 0) { + if (bind(sock, (struct sockaddr *) &serv_addr, sizeof(serv_addr)) < 0) { perror("bind"); close_socket(sock); return 1; } - if(listen(sock, 5) < 0) { + if (listen(sock, 5) < 0) { perror("listen"); close_socket(sock); return 1; @@ -1093,7 +1093,7 @@ int serve(stlink_t *sl, st_state_t *st) { SOCKET client = accept(sock, NULL, NULL); //signal (SIGINT, SIG_DFL); - if(!IS_SOCK_VALID(client)) { + if (!IS_SOCK_VALID(client)) { perror("accept"); close_socket(sock); return 1; @@ -1120,12 +1120,12 @@ int serve(stlink_t *sl, st_state_t *st) { */ int critical_error = 0; int ret; - while(1) { + while (1) { ret = 0; char* packet; int status = gdb_recv_packet(client, &packet); - if(status < 0) { + if (status < 0) { ELOG("cannot recv: %d\n", status); close_socket(client); return 1; @@ -1138,13 +1138,13 @@ int serve(stlink_t *sl, st_state_t *st) { switch(packet[0]) { case 'q': { - if(packet[1] == 'P' || packet[1] == 'C' || packet[1] == 'L') { + if (packet[1] == 'P' || packet[1] == 'C' || packet[1] == 'L') { reply = strdup(""); break; } char *separator = strstr(packet, ":"), *params = ""; - if(separator == NULL) { + if (separator == NULL) { separator = packet + strlen(packet); } else { params = separator + 1; @@ -1156,8 +1156,8 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("query: %s;%s\n", queryName, params); - if(!strcmp(queryName, "Supported")) { - if(sl->chip_id==STLINK_CHIPID_STM32_F4 + if (!strcmp(queryName, "Supported")) { + if (sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F4_HD || sl->core_id==STM32F7_CORE_ID) { reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); @@ -1165,7 +1165,7 @@ int serve(stlink_t *sl, st_state_t *st) { else { reply = strdup("PacketSize=3fff;qXfer:memory-map:read+"); } - } else if(!strcmp(queryName, "Xfer")) { + } else if (!strcmp(queryName, "Xfer")) { char *type, *op, *__s_addr, *s_length; char *tok = params; char *annex __attribute__((unused)); @@ -1184,18 +1184,18 @@ int serve(stlink_t *sl, st_state_t *st) { const char* data = NULL; - if(!strcmp(type, "memory-map") && !strcmp(op, "read")) + if (!strcmp(type, "memory-map") && !strcmp(op, "read")) data = current_memory_map; - if(!strcmp(type, "features") && !strcmp(op, "read")) + if (!strcmp(type, "features") && !strcmp(op, "read")) data = target_description_F4; - if(data) { + if (data) { unsigned data_length = (unsigned int) strlen(data); - if(addr + length > data_length) + if (addr + length > data_length) length = data_length - addr; - if(length == 0) { + if (length == 0) { reply = strdup("l"); } else { reply = calloc(length + 2, 1); @@ -1203,11 +1203,11 @@ int serve(stlink_t *sl, st_state_t *st) { strncpy(&reply[1], data, length); } } - } else if(!strncmp(queryName, "Rcmd,",4)) { + } else if (!strncmp(queryName, "Rcmd,",4)) { // Rcmd uses the wrong separator separator = strstr(packet, ","); params = ""; - if(separator == NULL) { + if (separator == NULL) { separator = packet + strlen(packet); } else { params = separator + 1; @@ -1328,7 +1328,7 @@ int serve(stlink_t *sl, st_state_t *st) { free(cmd); } - if(reply == NULL) + if (reply == NULL) reply = strdup(""); free(queryName); @@ -1342,7 +1342,7 @@ int serve(stlink_t *sl, st_state_t *st) { cmdName++; // vCommand -> Command - if(!strcmp(cmdName, "FlashErase")) { + if (!strcmp(cmdName, "FlashErase")) { char *__s_addr, *s_length; char *tok = params; @@ -1355,12 +1355,12 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("FlashErase: addr:%08x,len:%04x\n", addr, length); - if(flash_add_block(addr, length, sl) < 0) { + if (flash_add_block(addr, length, sl) < 0) { reply = strdup("E00"); } else { reply = strdup("OK"); } - } else if(!strcmp(cmdName, "FlashWrite")) { + } else if (!strcmp(cmdName, "FlashWrite")) { char *__s_addr, *data; char *tok = params; @@ -1375,8 +1375,8 @@ int serve(stlink_t *sl, st_state_t *st) { // Additional byte is reserved for alignment fix. uint8_t *decoded = calloc(data_length + 1, 1); unsigned dec_index = 0; - for(unsigned int i = 0; i < data_length; i++) { - if(data[i] == 0x7d) { + for (unsigned int i = 0; i < data_length; i++) { + if (data[i] == 0x7d) { i++; decoded[dec_index++] = data[i] ^ 0x20; } else { @@ -1385,31 +1385,31 @@ int serve(stlink_t *sl, st_state_t *st) { } // Fix alignment - if(dec_index % 2 != 0) + if (dec_index % 2 != 0) dec_index++; DLOG("binary packet %d -> %d\n", data_length, dec_index); - if(flash_populate(addr, decoded, dec_index) < 0) { + if (flash_populate(addr, decoded, dec_index) < 0) { reply = strdup("E00"); } else { reply = strdup("OK"); } free(decoded); - } else if(!strcmp(cmdName, "FlashDone")) { - if(flash_go(sl) < 0) { + } else if (!strcmp(cmdName, "FlashDone")) { + if (flash_go(sl) < 0) { reply = strdup("E00"); } else { reply = strdup("OK"); } - } else if(!strcmp(cmdName, "Kill")) { + } else if (!strcmp(cmdName, "Kill")) { attached = 0; reply = strdup("OK"); } - if(reply == NULL) + if (reply == NULL) reply = strdup(""); break; @@ -1422,15 +1422,15 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("Semihost: run failed\n"); } - while(1) { + while (1) { status = gdb_check_for_interrupt(client); - if(status < 0) { + if (status < 0) { ELOG("cannot check for int: %d\n", status); close_socket(client); return 1; } - if(status == 1) { + if (status == 1) { stlink_force_debug(sl); break; } @@ -1439,7 +1439,7 @@ int serve(stlink_t *sl, st_state_t *st) { if (ret) { DLOG("Semihost: status failed\n"); } - if(sl->core_stat == STLINK_CORE_HALTED) { + if (sl->core_stat == STLINK_CORE_HALTED) { struct stlink_reg reg; stm32_addr_t pc; stm32_addr_t addr; @@ -1526,7 +1526,7 @@ int serve(stlink_t *sl, st_state_t *st) { break; case '?': - if(attached) { + if (attached) { reply = strdup("S05"); // TRAP } else { /* Stub shall reply OK if not attached. */ @@ -1541,7 +1541,7 @@ int serve(stlink_t *sl, st_state_t *st) { } reply = calloc(8 * 16 + 1, 1); - for(int i = 0; i < 16; i++) + for (int i = 0; i < 16; i++) sprintf(&reply[i * 8], "%08x", (uint32_t)htonl(regp.r[i])); break; @@ -1550,34 +1550,34 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned id = (unsigned int) strtoul(&packet[1], NULL, 16); unsigned myreg = 0xDEADDEAD; - if(id < 16) { + if (id < 16) { ret = stlink_read_reg(sl, id, ®p); myreg = htonl(regp.r[id]); - } else if(id == 0x19) { + } else if (id == 0x19) { ret = stlink_read_reg(sl, 16, ®p); myreg = htonl(regp.xpsr); - } else if(id == 0x1A) { + } else if (id == 0x1A) { ret = stlink_read_reg(sl, 17, ®p); myreg = htonl(regp.main_sp); - } else if(id == 0x1B) { + } else if (id == 0x1B) { ret = stlink_read_reg(sl, 18, ®p); myreg = htonl(regp.process_sp); - } else if(id == 0x1C) { + } else if (id == 0x1C) { ret = stlink_read_unsupported_reg(sl, id, ®p); myreg = htonl(regp.control); - } else if(id == 0x1D) { + } else if (id == 0x1D) { ret = stlink_read_unsupported_reg(sl, id, ®p); myreg = htonl(regp.faultmask); - } else if(id == 0x1E) { + } else if (id == 0x1E) { ret = stlink_read_unsupported_reg(sl, id, ®p); myreg = htonl(regp.basepri); - } else if(id == 0x1F) { + } else if (id == 0x1F) { ret = stlink_read_unsupported_reg(sl, id, ®p); myreg = htonl(regp.primask); - } else if(id >= 0x20 && id < 0x40) { + } else if (id >= 0x20 && id < 0x40) { ret = stlink_read_unsupported_reg(sl, id, ®p); myreg = htonl(regp.s[id-0x20]); - } else if(id == 0x40) { + } else if (id == 0x40) { ret = stlink_read_unsupported_reg(sl, id, ®p); myreg = htonl(regp.fpscr); } else { @@ -1605,25 +1605,25 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned value = (unsigned int) strtoul(s_value, NULL, 16); - if(reg < 16) { + if (reg < 16) { ret = stlink_write_reg(sl, ntohl(value), reg); - } else if(reg == 0x19) { + } else if (reg == 0x19) { ret = stlink_write_reg(sl, ntohl(value), 16); - } else if(reg == 0x1A) { + } else if (reg == 0x1A) { ret = stlink_write_reg(sl, ntohl(value), 17); - } else if(reg == 0x1B) { + } else if (reg == 0x1B) { ret = stlink_write_reg(sl, ntohl(value), 18); - } else if(reg == 0x1C) { + } else if (reg == 0x1C) { ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if(reg == 0x1D) { + } else if (reg == 0x1D) { ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if(reg == 0x1E) { + } else if (reg == 0x1E) { ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if(reg == 0x1F) { + } else if (reg == 0x1F) { ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if(reg >= 0x20 && reg < 0x40) { + } else if (reg >= 0x20 && reg < 0x40) { ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if(reg == 0x40) { + } else if (reg == 0x40) { ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); } else { ret = 1; @@ -1632,7 +1632,7 @@ int serve(stlink_t *sl, st_state_t *st) { if (ret) { DLOG("P packet: stlink_write_unsupported_reg failed with reg %u\n", reg); } - if(reply == NULL) { + if (reply == NULL) { // note that NULL may not be zero reply = strdup("OK"); } @@ -1641,7 +1641,7 @@ int serve(stlink_t *sl, st_state_t *st) { } case 'G': - for(int i = 0; i < 16; i++) { + for (int i = 0; i < 16; i++) { char str[9] = {0}; strncpy(str, &packet[1 + i * 8], 8); uint32_t reg = (uint32_t) strtoul(str, NULL, 16); @@ -1676,7 +1676,7 @@ int serve(stlink_t *sl, st_state_t *st) { } reply = calloc(count * 2 + 1, 1); - for(unsigned int i = 0; i < count; i++) { + for (unsigned int i = 0; i < count; i++) { reply[i * 2 + 0] = hex[sl->q_buf[i + adj_start] >> 4]; reply[i * 2 + 1] = hex[sl->q_buf[i + adj_start] & 0xf]; } @@ -1693,10 +1693,10 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned count = (unsigned int) strtoul(s_count, NULL, 16); int err = 0; - if(start % 4) { + if (start % 4) { unsigned align_count = 4 - start % 4; if (align_count > count) align_count = count; - for(unsigned int i = 0; i < align_count; i ++) { + for (unsigned int i = 0; i < align_count; i ++) { char hextmp[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; uint8_t byte = strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; @@ -1708,10 +1708,10 @@ int serve(stlink_t *sl, st_state_t *st) { hexdata += 2*align_count; } - if(count - count % 4) { + if (count - count % 4) { unsigned aligned_count = count - count % 4; - for(unsigned int i = 0; i < aligned_count; i ++) { + for (unsigned int i = 0; i < aligned_count; i ++) { char hextmp[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; uint8_t byte = strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; @@ -1723,8 +1723,8 @@ int serve(stlink_t *sl, st_state_t *st) { hexdata += 2*aligned_count; } - if(count) { - for(unsigned int i = 0; i < count; i ++) { + if (count) { + for (unsigned int i = 0; i < count; i ++) { char hextmp[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; uint8_t byte = strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; @@ -1743,7 +1743,7 @@ int serve(stlink_t *sl, st_state_t *st) { switch (packet[1]) { case '1': - if(update_code_breakpoint(sl, addr, 1) < 0) { + if (update_code_breakpoint(sl, addr, 1) < 0) { reply = strdup("E00"); } else { reply = strdup("OK"); @@ -1754,15 +1754,15 @@ int serve(stlink_t *sl, st_state_t *st) { case '3': // insert read watchpoint case '4': { // insert access watchpoint enum watchfun wf; - if(packet[1] == '2') { + if (packet[1] == '2') { wf = WATCHWRITE; - } else if(packet[1] == '3') { + } else if (packet[1] == '3') { wf = WATCHREAD; } else { wf = WATCHACCESS; } - if(add_data_watchpoint(sl, wf, addr, len) < 0) { + if (add_data_watchpoint(sl, wf, addr, len) < 0) { reply = strdup("E00"); } else { reply = strdup("OK"); @@ -1790,7 +1790,7 @@ int serve(stlink_t *sl, st_state_t *st) { case '2' : // remove write watchpoint case '3' : // remove read watchpoint case '4' : // remove access watchpoint - if(delete_data_watchpoint(sl, addr) < 0) { + if (delete_data_watchpoint(sl, addr) < 0) { reply = strdup("E00"); break; } else { @@ -1852,7 +1852,7 @@ int serve(stlink_t *sl, st_state_t *st) { stlink_close(sl); sl = do_connect(st); - if(sl == NULL) cleanup(0); + if (sl == NULL) cleanup(0); connected_stlink = sl; if (st->reset) { @@ -1874,11 +1874,11 @@ int serve(stlink_t *sl, st_state_t *st) { reply = strdup(""); } - if(reply) { + if (reply) { DLOG("send: %s\n", reply); int result = gdb_send_packet(client, reply); - if(result != 0) { + if (result != 0) { ELOG("cannot send: %d\n", result); free(reply); free(packet); diff --git a/src/gdbserver/semihosting.c b/src/gdbserver/semihosting.c index 9e92cf3bd..40758b61d 100644 --- a/src/gdbserver/semihosting.c +++ b/src/gdbserver/semihosting.c @@ -178,7 +178,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { uint32_t name_len; char *name; - if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { + if (mem_read(sl, r1, args, sizeof (args)) != 0){ DLOG("Semihosting SYS_OPEN error: " "cannot read args from target memory\n"); *ret = -1; @@ -215,7 +215,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return -1; } - if (mem_read(sl, name_address, name, name_len) != 0 ) { + if (mem_read(sl, name_address, name, name_len) != 0){ free(name); *ret = -1; DLOG("Semihosting SYS_OPEN error: " @@ -238,7 +238,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { uint32_t args[1]; int fd; - if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { + if (mem_read(sl, r1, args, sizeof (args)) != 0){ DLOG("Semihosting SYS_CLOSE error: " "cannot read args from target memory\n"); *ret = -1; @@ -263,7 +263,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { uint32_t buffer_len; void *buffer; - if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { + if (mem_read(sl, r1, args, sizeof (args)) != 0){ DLOG("Semihosting SYS_WRITE error: " "cannot read args from target memory\n"); *ret = -1; @@ -289,7 +289,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return -1; } - if (mem_read(sl, buffer_address, buffer, buffer_len) != 0 ) { + if (mem_read(sl, buffer_address, buffer, buffer_len) != 0){ DLOG("Semihosting SYS_WRITE error: " "cannot read buffer from target memory\n"); free(buffer); @@ -322,7 +322,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { void *buffer; ssize_t read_result; - if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { + if (mem_read(sl, r1, args, sizeof (args)) != 0){ DLOG("Semihosting SYS_READ error: " "cannot read args from target memory\n"); *ret = -1; @@ -357,7 +357,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (read_result == -1) { *ret = buffer_len; } else { - if (mem_write(sl, buffer_address, buffer, read_result) != 0 ) { + if (mem_write(sl, buffer_address, buffer, read_result) != 0){ DLOG("Semihosting SYS_READ error: " "cannot write buffer to target memory\n"); free(buffer); @@ -385,7 +385,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { uint32_t name_len; char *name; - if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { + if (mem_read(sl, r1, args, sizeof (args)) != 0){ DLOG("Semihosting SYS_REMOVE error: " "cannot read args from target memory\n"); *ret = -1; @@ -414,7 +414,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return -1; } - if (mem_read(sl, name_address, name, name_len) != 0 ) { + if (mem_read(sl, name_address, name, name_len) != 0){ free(name); *ret = -1; DLOG("Semihosting SYS_REMOVE error: " @@ -438,7 +438,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { int fd; off_t offset; - if (mem_read(sl, r1, args, sizeof (args)) != 0 ) { + if (mem_read(sl, r1, args, sizeof (args)) != 0){ DLOG("Semihosting SYS_SEEK error: " "cannot read args from target memory\n"); *ret = -1; @@ -482,7 +482,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { uint8_t buf[WRITE0_BUFFER_SIZE]; while (true) { - if (mem_read(sl, r1, buf, WRITE0_BUFFER_SIZE) != 0 ) { + if (mem_read(sl, r1, buf, WRITE0_BUFFER_SIZE) != 0){ DLOG("Semihosting WRITE0: " "cannot read target memory at 0x%08x\n", r1); return -1; diff --git a/src/md5.c b/src/md5.c index ff7d2d76e..e2b526c7d 100755 --- a/src/md5.c +++ b/src/md5.c @@ -70,7 +70,7 @@ void* #define GET(n) (ctx->block[(n)]) #define SET(n) (ctx->block[(n)] = \ - ((uint32_t)ptr[(n)*4 + 0] << 0 ) \ + ((uint32_t)ptr[(n)*4 + 0] << 0) \ | ((uint32_t)ptr[(n)*4 + 1] << 8 ) \ | ((uint32_t)ptr[(n)*4 + 2] << 16) \ | ((uint32_t)ptr[(n)*4 + 3] << 24) ) @@ -167,7 +167,7 @@ void* d += saved_d; ptr += 64; - } while( size -= 64 ); + } while ( size -= 64 ); ctx->a = a; ctx->b = b; @@ -223,7 +223,7 @@ void uint32_t free; saved_lo = Context->lo; - if( (Context->lo = (saved_lo + BufferSize) & 0x1fffffff) < saved_lo ) + if ( (Context->lo = (saved_lo + BufferSize) & 0x1fffffff) < saved_lo ) { Context->hi++; } @@ -231,11 +231,11 @@ void used = saved_lo & 0x3f; - if( used ) + if ( used ) { free = 64 - used; - if( BufferSize < free ) + if ( BufferSize < free ) { memcpy( &Context->buffer[used], Buffer, BufferSize ); return; @@ -247,7 +247,7 @@ void TransformFunction(Context, Context->buffer, 64); } - if( BufferSize >= 64 ) + if ( BufferSize >= 64 ) { Buffer = TransformFunction( Context, Buffer, BufferSize & ~(unsigned long)0x3f ); BufferSize &= 0x3f; @@ -278,7 +278,7 @@ void free = 64 - used; - if(free < 8) + if (free < 8) { memset( &Context->buffer[used], 0, free ); TransformFunction( Context, Context->buffer, 64 ); diff --git a/src/mingw/mingw.c b/src/mingw/mingw.c index 4cb917ac4..646fca238 100644 --- a/src/mingw/mingw.c +++ b/src/mingw/mingw.c @@ -27,11 +27,11 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) FD_ZERO(&efds); for (i = 0, op = ip = 0; i < nfds; ++i) { fds[i].revents = 0; - if(fds[i].events & (POLLIN|POLLPRI)) { + if (fds[i].events & (POLLIN|POLLPRI)) { ip = &ifds; FD_SET(fds[i].fd, ip); } - if(fds[i].events & POLLOUT) { + if (fds[i].events & POLLOUT) { op = &ofds; FD_SET(fds[i].fd, op); } @@ -42,7 +42,7 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) #endif /* Set up the timeval structure for the timeout parameter */ - if(timo < 0) { + if (timo < 0) { toptr = 0; } else { toptr = &timeout; @@ -59,17 +59,17 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) printf("Exiting select rc=%d\n", rc); #endif - if(rc <= 0) + if (rc <= 0) return rc; - if(rc > 0) { + if (rc > 0) { for ( i = 0; i < nfds; ++i) { int fd = fds[i].fd; - if(fds[i].events & (POLLIN|POLLPRI) && FD_ISSET(fd, &ifds)) + if (fds[i].events & (POLLIN|POLLPRI) && FD_ISSET(fd, &ifds)) fds[i].revents |= POLLIN; - if(fds[i].events & POLLOUT && FD_ISSET(fd, &ofds)) + if (fds[i].events & POLLOUT && FD_ISSET(fd, &ofds)) fds[i].revents |= POLLOUT; - if(FD_ISSET(fd, &efds)) + if (FD_ISSET(fd, &efds)) /* Some error was detected ... should be some way to know. */ fds[i].revents |= POLLHUP; #ifdef DEBUG_POLL @@ -118,7 +118,7 @@ SOCKET win32_socket(int domain, int type, int protocol) { SOCKET fd = socket(domain, type, protocol); - if(fd == INVALID_SOCKET) { + if (fd == INVALID_SOCKET) { set_socket_errno(WSAGetLastError()); } return fd; @@ -133,7 +133,7 @@ win32_connect(SOCKET fd, struct sockaddr *addr, socklen_t addr_len) { int rc = connect(fd, addr, addr_len); assert(rc == 0 || rc == SOCKET_ERROR); - if(rc == SOCKET_ERROR) { + if (rc == SOCKET_ERROR) { set_connect_errno(WSAGetLastError()); } return rc; @@ -148,7 +148,7 @@ SOCKET win32_accept(SOCKET fd, struct sockaddr *addr, socklen_t *addr_len) { SOCKET newfd = accept(fd, addr, addr_len); - if(newfd == INVALID_SOCKET) { + if (newfd == INVALID_SOCKET) { set_socket_errno(WSAGetLastError()); newfd = (SOCKET)-1; } @@ -165,7 +165,7 @@ win32_shutdown(SOCKET fd, int mode) { int rc = shutdown(fd, mode); assert(rc == 0 || rc == SOCKET_ERROR); - if(rc == SOCKET_ERROR) { + if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } return rc; @@ -174,7 +174,7 @@ win32_shutdown(SOCKET fd, int mode) int win32_close_socket(SOCKET fd) { int rc = closesocket(fd); - if(rc == SOCKET_ERROR) { + if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } return rc; @@ -183,7 +183,7 @@ int win32_close_socket(SOCKET fd) ssize_t win32_write_socket(SOCKET fd, void *buf, int n) { int rc = send(fd, buf, n, 0); - if(rc == SOCKET_ERROR) { + if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } return rc; @@ -192,7 +192,7 @@ ssize_t win32_write_socket(SOCKET fd, void *buf, int n) ssize_t win32_read_socket(SOCKET fd, void *buf, int n) { int rc = recv(fd, buf, n, 0); - if(rc == SOCKET_ERROR) { + if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } return rc; diff --git a/src/sg.c b/src/sg.c index d1ee5aea1..031cc64e5 100644 --- a/src/sg.c +++ b/src/sg.c @@ -921,9 +921,9 @@ static stlink_t* stlink_open(const int verbose) { struct stlink_libsg *slsg = malloc(sizeof (struct stlink_libsg)); if (sl == NULL || slsg == NULL) { WLOG("Couldn't malloc stlink and stlink_sg structures out of memory!\n"); - if(sl != NULL) + if (sl != NULL) free(sl); - if(slsg != NULL) + if (slsg != NULL) free(slsg); return NULL; } diff --git a/src/tools/flash.c b/src/tools/flash.c index f703bc813..f39b6c6e4 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -129,7 +129,7 @@ int main(int ac, char** av) if (o.cmd == FLASH_CMD_WRITE) /* write */ { size_t size = 0; - if(o.format == FLASH_FORMAT_IHEX) { + if (o.format == FLASH_FORMAT_IHEX) { err = stlink_parse_ihex(o.filename, stlink_get_erased_pattern(sl), &mem, &size, &o.addr); if (err == -1) { printf("Cannot parse %s as Intel-HEX file\n", o.filename); @@ -138,7 +138,7 @@ int main(int ac, char** av) } if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { - if(o.format == FLASH_FORMAT_IHEX) + if (o.format == FLASH_FORMAT_IHEX) err = stlink_mwrite_flash(sl, mem, (uint32_t)size, o.addr); else err = stlink_fwrite_flash(sl, o.filename, o.addr); @@ -150,7 +150,7 @@ int main(int ac, char** av) } else if ((o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { - if(o.format == FLASH_FORMAT_IHEX) + if (o.format == FLASH_FORMAT_IHEX) err = stlink_mwrite_sram(sl, mem, (uint32_t)size, o.addr); else err = stlink_fwrite_sram(sl, o.filename, o.addr); @@ -207,19 +207,19 @@ int main(int ac, char** av) } else /* read */ { - if(o.area == FLASH_OPTION_BYTES){ - if(sl->chip_id == STLINK_CHIPID_STM32_F2){ + if (o.area == FLASH_OPTION_BYTES){ + if (sl->chip_id == STLINK_CHIPID_STM32_F2){ uint32_t option_byte = 0; err = stlink_read_option_bytes_f2(sl,&option_byte); printf("%x\n",option_byte); - }else if(sl->chip_id == STLINK_CHIPID_STM32_F446){ + } else if (sl->chip_id == STLINK_CHIPID_STM32_F446){ uint32_t option_byte = 0; err = stlink_read_option_bytes_f4(sl,&option_byte); printf("%x\n",option_byte); - }else{ + } else { printf("This format is available for STM32F2 and STM32F4 only\n"); } - }else{ + } else { if ((o.addr >= sl->flash_base) && (o.size == 0) && (o.addr < sl->flash_base + sl->flash_size)){ o.size = sl->flash_size; diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index c139977ce..085d278db 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -28,7 +28,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { o->log_level = STND_LOG_LEVEL; // options - while(ac >= 1) { + while (ac >= 1) { if (strcmp(av[0], "--version") == 0) { printf("v%s\n", STLINK_VERSION); exit(EXIT_SUCCESS); @@ -44,7 +44,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } else if (strcmp(av[0], "--serial") == 0 || starts_with(av[0], "--serial=")) { const char * serial; - if(strcmp(av[0], "--serial") == 0) { + if (strcmp(av[0], "--serial") == 0) { ac--; av++; if (ac < 1) return -1; @@ -56,8 +56,8 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ int j = (int)strlen(serial); int length = j / 2; // the length of the destination-array - if(j % 2 != 0) return -1; - for(size_t k = 0; j >= 0 && k < sizeof(o->serial); ++k, j -= 2) { + if (j % 2 != 0) return -1; + for (size_t k = 0; j >= 0 && k < sizeof(o->serial); ++k, j -= 2) { char buffer[3] = {0}; memcpy(buffer, serial + j, 2); o->serial[length - k] = (uint8_t)strtol(buffer, NULL, 16); @@ -65,7 +65,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { const char * area; - if(strcmp(av[0], "--area") == 0) { + if (strcmp(av[0], "--area") == 0) { ac--; av++; if (ac < 1) return -1; @@ -88,7 +88,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { const char * format; - if(strcmp(av[0], "--format") == 0) { + if (strcmp(av[0], "--format") == 0) { ac--; av++; if (ac < 1) return -1; @@ -136,7 +136,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } // command and (optional) device name - while(ac >= 1) { + while (ac >= 1) { if (strcmp(av[0], "erase") == 0) { if (o->cmd != FLASH_CMD_NONE) return -1; o->cmd = FLASH_CMD_ERASE; @@ -167,32 +167,32 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { return -1; case FLASH_CMD_ERASE: // no more arguments expected - if(ac != 0) return -1; + if (ac != 0) return -1; break; case FLASH_CMD_READ: // expect filename, addr and size - if((o->area == FLASH_OPTION_BYTES) &&(ac == 0)) break; + if ((o->area == FLASH_OPTION_BYTES) &&(ac == 0)) break; if (ac != 3) return invalid_args("read "); if (ac != 3) return -1; o->filename = av[0]; o->addr = (uint32_t) strtoul(av[1], &tail, 16); - if(tail[0] != '\0') return bad_arg("addr"); + if (tail[0] != '\0') return bad_arg("addr"); o->size = strtoul(av[2], &tail, 16); - if(tail[0] != '\0') return bad_arg("size"); + if (tail[0] != '\0') return bad_arg("size"); break; case FLASH_CMD_WRITE: - if(o->area == FLASH_OPTION_BYTES){ - if(ac != 1) return -1; + if (o->area == FLASH_OPTION_BYTES){ + if (ac != 1) return -1; o->val = (uint32_t)strtoul(av[0], &tail, 16); } - else if(o->format == FLASH_FORMAT_BINARY) { // expect filename and addr + else if (o->format == FLASH_FORMAT_BINARY) { // expect filename and addr if (ac != 2) return invalid_args("write "); o->filename = av[0]; o->addr = (uint32_t) strtoul(av[1], &tail, 16); - if(tail[0] != '\0') return bad_arg("addr"); + if (tail[0] != '\0') return bad_arg("addr"); } - else if(o->format == FLASH_FORMAT_IHEX) { // expect filename + else if (o->format == FLASH_FORMAT_IHEX) { // expect filename if (ac != 1) return invalid_args("write "); o->filename = av[0]; } diff --git a/src/tools/gui/stlink-gui.c b/src/tools/gui/stlink-gui.c index c1cf26b76..0dc8bd723 100644 --- a/src/tools/gui/stlink-gui.c +++ b/src/tools/gui/stlink-gui.c @@ -142,7 +142,7 @@ mem_view_add_as_hex (GtkListStore *store, gchar *hex_str; hex_str = g_strdup_printf ("0x%08X", value); - gtk_list_store_set (store, iter, column, hex_str, -1); + gtk_list_store_set(store, iter, column, hex_str, -1); g_free (hex_str); } @@ -439,7 +439,7 @@ static void mem_jmp (GtkTreeView *view, } } } - g_value_unset (&value); + g_value_unset(&value); } while (gtk_tree_model_iter_next (model, &iter)); } } @@ -751,10 +751,10 @@ int export_to_file(const char*filename, const struct mem_t flash_mem) { printf("%s\n", filename); FILE * f=fopen(filename, "w"); - if(f==NULL) + if (f==NULL) return -1; - for(gsize i=0;iflash_mem)!=0) + if (export_to_file (filename, gui->flash_mem)!=0) stlink_gui_set_info_error_message(gui, "Failed to export flash"); else stlink_gui_set_info_error_message(gui, "Export successful"); @@ -886,7 +886,7 @@ stlink_gui_init_dnd (STlinkGUI *gui) { "text/uri-list", 0, TARGET_FILENAME }, }; - gtk_drag_dest_set (GTK_WIDGET (gui->window), + gtk_drag_dest_set(GTK_WIDGET (gui->window), GTK_DEST_DEFAULT_ALL, target_list, G_N_ELEMENTS (target_list), diff --git a/src/usb.c b/src/usb.c index 970d3ee81..206600f14 100644 --- a/src/usb.c +++ b/src/usb.c @@ -144,7 +144,7 @@ static int fill_command unsigned char* const cmd = sl->c_buf; int i = 0; memset(cmd, 0, sizeof (sl->c_buf)); - if(slu->protocoll == 1) { + if (slu->protocoll == 1) { cmd[i++] = 'U'; cmd[i++] = 'S'; cmd[i++] = 'B'; @@ -651,7 +651,7 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { } sl->q_len = (int) size; stlink_print_data(sl); - for(i=0; i<16; i++) + for (i=0; i<16; i++) regp->r[i]= read_uint32(sl->q_buf, i*4); regp->xpsr = read_uint32(sl->q_buf, 64); regp->main_sp = read_uint32(sl->q_buf, 68); @@ -1049,7 +1049,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST } if (reset) { - if( sl->version.stlink_v > 1 ) stlink_jtag_reset(sl, 2); + if ( sl->version.stlink_v > 1)stlink_jtag_reset(sl, 2); stlink_reset(sl); usleep(10000); } diff --git a/tests/flash.c b/tests/flash.c index b17aa99ae..d193666ff 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -15,12 +15,12 @@ struct Test { }; static bool cmp_strings(const char * s1, const char * s2) { - if(s1 == NULL || s2 == NULL) return (s1 == s2); + if (s1 == NULL || s2 == NULL) return (s1 == s2); else return (0 == strcmp(s1, s2)); } static bool cmp_mem(const uint8_t * s1, const uint8_t * s2, size_t size) { - if(s1 == NULL || s2 == NULL) return (s1 == s2); + if (s1 == NULL || s2 == NULL) return (s1 == s2); else return (0 == memcmp(s1, s2, size)); } @@ -36,8 +36,8 @@ static bool execute_test(const struct Test * test) { #endif strcpy(cmd_line, test->cmd_line); - for(char * tok = strtok(cmd_line, " "); tok; tok = strtok(NULL, " ")) { - if((size_t)ac >= sizeof(av)/sizeof(av[0])) return false; + for (char * tok = strtok(cmd_line, " "); tok; tok = strtok(NULL, " ")) { + if ((size_t)ac >= sizeof(av)/sizeof(av[0])) return false; av[ac] = tok; ++ac; @@ -50,7 +50,7 @@ static bool execute_test(const struct Test * test) { // compare results bool ret = (res == test->res); - if(ret && (res == 0)) { + if (ret && (res == 0)) { ret &= (opts.cmd == test->opts.cmd); ret &= cmp_strings(opts.devname, test->opts.devname); ret &= cmp_mem(opts.serial, test->opts.serial, sizeof(opts.serial)); @@ -104,8 +104,8 @@ static struct Test tests[] = { int main() { bool allOk = true; - for(size_t i = 0; i < sizeof(tests)/sizeof(tests[0]); ++i) { - if(!execute_test(&tests[i])) allOk = false; + for (size_t i = 0; i < sizeof(tests)/sizeof(tests[0]); ++i) { + if (!execute_test(&tests[i])) allOk = false; } return (allOk ? 0 : 1); From ee4a52288a68126f3c74fee7d3413fa5ee9900bd Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 6 Apr 2020 14:32:34 +0200 Subject: [PATCH 0822/1435] st-flash: print proper error in case of option byte read error. User could get a wrong "stlink_fread()" error in case of bad stlink_read_option_foo.. --- src/tools/flash.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/tools/flash.c b/src/tools/flash.c index f39b6c6e4..6e7b37103 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -218,6 +218,10 @@ int main(int ac, char** av) printf("%x\n",option_byte); } else { printf("This format is available for STM32F2 and STM32F4 only\n"); + if (err == -1) + { + printf("could not read option bytes\n"); + goto on_error; } } else { if ((o.addr >= sl->flash_base) && (o.size == 0) && @@ -229,11 +233,12 @@ int main(int ac, char** av) o.size = sl->sram_size; } err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); - } - if (err == -1) - { - printf("stlink_fread() == -1\n"); - goto on_error; + + if (err == -1) + { + printf("stlink_fread() == -1\n"); + goto on_error; + } } } From 8430a6e6fa7d507fa5a19ef2552f3ae5422aa24e Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 6 Apr 2020 14:01:35 +0200 Subject: [PATCH 0823/1435] add read, write option byte for g4 and g0 use g0 code, same logic with different base address. also cleanup some duplicate lock/unlock code. --- include/stlink.h | 1 + include/stm32.h | 1 + src/common.c | 57 +++++++++++++++++++++++++++-------------------- src/tools/flash.c | 9 +++++--- 4 files changed, 41 insertions(+), 27 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index 508b50f7d..a21874454 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -236,6 +236,7 @@ typedef struct flash_loader { int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); int stlink_load_device_params(stlink_t *sl); + int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte); int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte); int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte); diff --git a/include/stm32.h b/include/stm32.h index 9a01baaf4..890d11254 100644 --- a/include/stm32.h +++ b/include/stm32.h @@ -15,6 +15,7 @@ #define STM32_FLASH_BASE ((uint32_t)0x08000000) #define STM32_SRAM_BASE ((uint32_t)0x20000000) #define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) +#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) #define STM32_L0_CAT2_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) #define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) #define STM32_L496X_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) diff --git a/src/common.c b/src/common.c index e94240351..332b9125d 100644 --- a/src/common.c +++ b/src/common.c @@ -2736,7 +2736,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t len) { +static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, uint32_t len) { uint32_t val; @@ -2750,25 +2750,16 @@ static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t l /* Check if chip is supported and for correct address */ if (sl->chip_id != STLINK_CHIPID_STM32_G0_CAT1 && - sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2) { - ELOG("Option bytes writing is currently only supported for the STM32G0\n"); + sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2 && + sl->chip_id != STLINK_CHIPID_STM32_G4_CAT2 && + sl->chip_id != STLINK_CHIPID_STM32_G4_CAT3) { + ELOG("Option bytes writing is currently only supported for the STM32G0/G4\n"); return -1; } - /* Unlock flash if necessary (ref manuel page 52) */ - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - if ((val & (1u << STM32Gx_FLASH_CR_LOCK))) { - - /* disable flash write protection. */ - stlink_write_debug32(sl, STM32Gx_FLASH_KEYR, 0x45670123); - stlink_write_debug32(sl, STM32Gx_FLASH_KEYR, 0xCDEF89AB); - - // check that the lock is no longer set. - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - if ((val & (1u << STM32Gx_FLASH_CR_LOCK))) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; } /* Unlock option bytes if necessary (ref manuel page 61) */ @@ -2802,7 +2793,9 @@ static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t l /* Wait for 'busy' bit in FLASH_SR to clear. */ do { stlink_read_debug32(sl, STM32Gx_FLASH_SR, &val); - } while ((val & (1 << 16)) != 0); + } while ((val & (1 << STM32Gx_FLASH_SR_BSY)) != 0); + + check_flash_error(sl); /* apply options bytes immediate */ stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -2813,10 +2806,9 @@ static int stlink_write_option_bytes_g0x(stlink_t *sl, uint8_t* base, uint32_t l stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); val |= (1u << STM32Gx_FLASH_CR_OPTLOCK); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + /* Re-lock flash. */ - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1u << STM32Gx_FLASH_CR_LOCK); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + lock_flash(sl); return 0; } @@ -3147,6 +3139,19 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint32_t option_byte) { return 0; } +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) +{ + uint32_t ret = stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); + WLOG("option bytes CR = %#010x\n", *option_byte); + return ret; +} + /** * Read option bytes * @param sl @@ -3183,7 +3188,7 @@ int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { /** * Read option bytes * @param sl - * @param option_byte value to write + * @param option_byte value to read * @return 0 on success, -ve on failure. */ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { @@ -3230,9 +3235,13 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui /* Check if chip is supported and for correct address */ if (((sl->chip_id == STLINK_CHIPID_STM32_G0_CAT1) || (sl->chip_id == STLINK_CHIPID_STM32_G0_CAT2)) && (addr == STM32_G0_OPTION_BYTES_BASE)) { - return stlink_write_option_bytes_g0x(sl, base, len); + return stlink_write_option_bytes_gx(sl, base, len); + } + else if (((sl->chip_id == STLINK_CHIPID_STM32_G4_CAT2) || + (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3)) && (addr == STM32_G4_OPTION_BYTES_BASE)) { + return stlink_write_option_bytes_gx(sl, base, len); } - else if ((sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) && (addr == STM32_L0_CAT2_OPTION_BYTES_BASE)) { + else if((sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) && (addr == STM32_L0_CAT2_OPTION_BYTES_BASE)) { return stlink_write_option_bytes_l0_cat2(sl, base, len); } else if ((sl->chip_id == STLINK_CHIPID_STM32_L496X) && (addr == STM32_L496X_OPTION_BYTES_BASE)) { diff --git a/src/tools/flash.c b/src/tools/flash.c index 6e7b37103..e211a2e81 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -208,16 +208,19 @@ int main(int ac, char** av) else /* read */ { if (o.area == FLASH_OPTION_BYTES){ + uint32_t option_byte = 0; if (sl->chip_id == STLINK_CHIPID_STM32_F2){ - uint32_t option_byte = 0; err = stlink_read_option_bytes_f2(sl,&option_byte); printf("%x\n",option_byte); } else if (sl->chip_id == STLINK_CHIPID_STM32_F446){ - uint32_t option_byte = 0; err = stlink_read_option_bytes_f4(sl,&option_byte); printf("%x\n",option_byte); + }else if(sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { + err = stlink_read_option_bytes_Gx(sl,&option_byte); + printf("%x\n",option_byte); } else { - printf("This format is available for STM32F2 and STM32F4 only\n"); + printf("This format is only available for STM32F2, STM32F4, STM32G0 and STM32G4\n"); + } if (err == -1) { printf("could not read option bytes\n"); From 1801fb1f005a93756ea566cb0cdb658611982f99 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 14 Apr 2020 15:03:19 +0200 Subject: [PATCH 0824/1435] flash.c: move device specific read option stuff to common.c --- include/stlink.h | 9 ++++----- src/common.c | 20 ++++++++++++++++++++ src/tools/flash.c | 26 ++++++++------------------ 3 files changed, 32 insertions(+), 23 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index a21874454..078251cf8 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -213,8 +213,6 @@ typedef struct flash_loader { uint8_t stlink_get_erased_pattern(stlink_t *sl); int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_fwrite_option_bytes_32bit(stlink_t *sl,uint32_t val); int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); @@ -236,9 +234,10 @@ typedef struct flash_loader { int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); int stlink_load_device_params(stlink_t *sl); - int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte); - int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte); - int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte); + + int stlink_read_option_bytes(stlink_t *sl, uint32_t* option_byte); + int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); + int stlink_fwrite_option_bytes_32bit(stlink_t *sl,uint32_t val); #include "stlink/sg.h" #include "stlink/usb.h" diff --git a/src/common.c b/src/common.c index 332b9125d..00d982593 100644 --- a/src/common.c +++ b/src/common.c @@ -3218,6 +3218,26 @@ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { return 0; } +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes(stlink_t *sl, uint32_t* option_byte) { + int err = -1; + if (sl->chip_id == STLINK_CHIPID_STM32_F2){ + err = stlink_read_option_bytes_f2(sl, option_byte); + }else if(sl->chip_id == STLINK_CHIPID_STM32_F446){ + err = stlink_read_option_bytes_f4(sl, option_byte); + }else if(sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { + err = stlink_read_option_bytes_Gx(sl, option_byte); + }else{ + ELOG("This format is only available for STM32F2, STM32F4, STM32G0 and STM32G4\n"); + } + return err; +} + /** * Write option bytes * @param sl diff --git a/src/tools/flash.c b/src/tools/flash.c index e211a2e81..06256823c 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -207,26 +207,16 @@ int main(int ac, char** av) } else /* read */ { - if (o.area == FLASH_OPTION_BYTES){ - uint32_t option_byte = 0; - if (sl->chip_id == STLINK_CHIPID_STM32_F2){ - err = stlink_read_option_bytes_f2(sl,&option_byte); + if(o.area == FLASH_OPTION_BYTES){ + uint32_t option_byte; + err = stlink_read_option_bytes(sl, &option_byte); + if (err == -1) { + printf("could not read option bytes (%d)\n", err); + goto on_error; + } else { printf("%x\n",option_byte); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F446){ - err = stlink_read_option_bytes_f4(sl,&option_byte); - printf("%x\n",option_byte); - }else if(sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { - err = stlink_read_option_bytes_Gx(sl,&option_byte); - printf("%x\n",option_byte); - } else { - printf("This format is only available for STM32F2, STM32F4, STM32G0 and STM32G4\n"); - } - if (err == -1) - { - printf("could not read option bytes\n"); - goto on_error; } - } else { + }else{ if ((o.addr >= sl->flash_base) && (o.size == 0) && (o.addr < sl->flash_base + sl->flash_size)){ o.size = sl->flash_size; From 2aeae8d85f74b00aeb64cfcf5c4d644f8fbecf08 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 14 Apr 2020 16:30:58 +0200 Subject: [PATCH 0825/1435] chipid: add option bytes info to chip db --- include/stlink.h | 4 ++++ include/stlink/chipid.h | 2 ++ src/common.c | 2 ++ 3 files changed, 8 insertions(+) diff --git a/include/stlink.h b/include/stlink.h index 078251cf8..f22abbb42 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -170,6 +170,10 @@ typedef struct flash_loader { stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() + /* option settings */ + stm32_addr_t option_base; + size_t option_size; + // bootloader // sys_base and sys_size are not used by the tools, but are only there to // download the bootloader code (see tests/sg.c) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index d23596c0d..64227962b 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -79,6 +79,8 @@ struct stlink_chipid_params { uint32_t sram_size; uint32_t bootrom_base; uint32_t bootrom_size; + uint32_t option_base; + uint32_t option_size; }; const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); diff --git a/src/common.c b/src/common.c index 00d982593..4525d0222 100644 --- a/src/common.c +++ b/src/common.c @@ -920,6 +920,8 @@ int stlink_load_device_params(stlink_t *sl) { sl->sram_size = params->sram_size; sl->sys_base = params->bootrom_base; sl->sys_size = params->bootrom_size; + sl->option_base = params->option_base; + sl->option_size = params->option_size; //medium and low devices have the same chipid. ram size depends on flash size. //STM32F100xx datasheet Doc ID 16455 Table 2 From 92ceb7f35a667637b574924be9d43f70e6073eb3 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 14 Apr 2020 16:33:15 +0200 Subject: [PATCH 0826/1435] chipid: insert data for supported chips, from common.c --- src/chipid.c | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/src/chipid.c b/src/chipid.c index b9d3933f0..5d43c3ab0 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -175,7 +175,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x100, .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/ .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 + .bootrom_size = 0x1000, + .option_base = STM32_L1_OPTION_BYTES_BASE, + .option_size = 8, }, { .chip_id = STLINK_CHIPID_STM32_L152_RE, @@ -400,7 +402,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x80, .sram_size = 0x2000, .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000 + .bootrom_size = 0x1000, + .option_base = STM32_L0_CAT2_OPTION_BYTES_BASE, + .option_size = 4, }, { // STM32F334, STM32F303x6/8, and STM32F328 @@ -494,7 +498,9 @@ static const struct stlink_chipid_params devices[] = { // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000 // 28k (per bank), same source as base + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L496X_OPTION_BYTES_BASE, + .option_size = 4, }, { // STLINK_CHIPID_STM32_L46X @@ -530,7 +536,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // 2K (sec 3.2) .sram_size = 0x2000, // 8K (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000 // 8K (sec 2.2.2 table 3) + .bootrom_size = 0x2000, // 8K (sec 2.2.2 table 3) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4, }, { // STM32G071/081 (from RM0444) @@ -541,7 +549,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // 2K (sec 3.2) .sram_size = 0x9000, // 36K (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000 // 28K (sec 2.2.2 table 2) + .bootrom_size = 0x7000, // 28K (sec 2.2.2 table 2) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, }, { // STM32G431/441 (from RM0440) @@ -555,7 +565,10 @@ static const struct stlink_chipid_params devices[] = { // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 .sram_size = 0x8000, // 32K (sec 2.4) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000 // 28K (table 2) + .bootrom_size = 0x7000, // 28K (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4*4, + }, { // STM32G471/473/474/483/484 (from RM0440) @@ -570,7 +583,9 @@ static const struct stlink_chipid_params devices[] = { // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 .sram_size = 0x18000, // 128K (sec 2.4) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000 // 28K (table 2) + .bootrom_size = 0x7000, // 28K (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4*4, }, { // STM32WB55 (from RM0434) From 6f0795d931500d556420e27e2d62683a336c1fd2 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 14 Apr 2020 17:35:15 +0200 Subject: [PATCH 0827/1435] chipid: add some l0 and l4 option info to allow option byte read --- include/stlink/chipid.h | 2 +- include/stm32.h | 4 ++-- src/chipid.c | 26 +++++++++++++++++--------- src/common.c | 2 +- 4 files changed, 21 insertions(+), 13 deletions(-) diff --git a/include/stlink/chipid.h b/include/stlink/chipid.h index 64227962b..98164a8fc 100644 --- a/include/stlink/chipid.h +++ b/include/stlink/chipid.h @@ -57,7 +57,7 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F72XXX = 0x452, /* This ID is found on the NucleoF722ZE board */ STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, - STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ + STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ STLINK_CHIPID_STM32_F413 = 0x463, STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ diff --git a/include/stm32.h b/include/stm32.h index 890d11254..c71718653 100644 --- a/include/stm32.h +++ b/include/stm32.h @@ -16,9 +16,9 @@ #define STM32_SRAM_BASE ((uint32_t)0x20000000) #define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) -#define STM32_L0_CAT2_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_L0_CATx_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) #define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) -#define STM32_L496X_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) +#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) #endif /* STM32_H */ diff --git a/src/chipid.c b/src/chipid.c index 5d43c3ab0..bc3d37567 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -378,7 +378,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x80, .sram_size = 0x2000, .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000 + .bootrom_size = 0x1000, + .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_size = 4, }, { // STM32L0x Category 5 @@ -390,7 +392,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x80, .sram_size = 0x5000, .bootrom_base = 0x1ff0000, - .bootrom_size = 0x2000 + .bootrom_size = 0x2000, + .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_size = 4, }, { // STM32L0x Category 2 @@ -403,7 +407,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2000, .bootrom_base = 0x1ff0000, .bootrom_size = 0x1000, - .option_base = STM32_L0_CAT2_OPTION_BYTES_BASE, + .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, .option_size = 4, }, { @@ -443,7 +447,9 @@ static const struct stlink_chipid_params devices[] = { // sizes; table 2, page 74 for SRAM2 location) .sram_size = 0x18000, .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000 // 28k (per bank), same source as base + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, }, { // STM32L4RX @@ -484,7 +490,9 @@ static const struct stlink_chipid_params devices[] = { // sizes; table 2, page 74 for SRAM2 location) .sram_size = 0xc000, .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000 // 28k (per bank), same source as base + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, }, { // STLINK_CHIPID_STM32_L496X @@ -499,7 +507,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L496X_OPTION_BYTES_BASE, + .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, }, { @@ -537,8 +545,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2000, // 8K (sec 2.3) .bootrom_base = 0x1fff0000, .bootrom_size = 0x2000, // 8K (sec 2.2.2 table 3) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 8*4, }, { // STM32G071/081 (from RM0444) @@ -551,7 +559,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7000, // 28K (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, + .option_size = 8*4, }, { // STM32G431/441 (from RM0440) diff --git a/src/common.c b/src/common.c index 4525d0222..351c74497 100644 --- a/src/common.c +++ b/src/common.c @@ -2863,7 +2863,7 @@ static int stlink_write_option_bytes_l0_cat2(stlink_t *sl, uint8_t* base, uint32 uint32_t data; write_uint32((unsigned char*) &data, *(uint32_t*) (base)); WLOG("Writing option bytes 0x%04x\n", data); - stlink_write_debug32(sl, STM32_L0_CAT2_OPTION_BYTES_BASE, data); + stlink_write_debug32(sl, STM32_L0_CATx_OPTION_BYTES_BASE, data); /* Reload options */ stlink_read_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); From 72cfd5ee20658cbd9a4cefd01e0099b461018822 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 14 Apr 2020 15:32:47 +0200 Subject: [PATCH 0828/1435] option: refactor option flash code. unify option bytes read/write, interface, use chipid db to store size and base to provide some write sanity check and generic option read code. --- include/stlink.h | 6 +- src/chipid.c | 8 +- src/common.c | 195 +++++++++++++++++++++++++--------------------- src/tools/flash.c | 12 +-- 4 files changed, 119 insertions(+), 102 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index f22abbb42..db737acb0 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -239,9 +239,11 @@ typedef struct flash_loader { int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); int stlink_load_device_params(stlink_t *sl); - int stlink_read_option_bytes(stlink_t *sl, uint32_t* option_byte); + int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); + int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); + + int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_fwrite_option_bytes_32bit(stlink_t *sl,uint32_t val); #include "stlink/sg.h" #include "stlink/usb.h" diff --git a/src/chipid.c b/src/chipid.c index bc3d37567..60d0787e9 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -546,7 +546,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x2000, // 8K (sec 2.2.2 table 3) .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 8*4, + .option_size = 4, }, { // STM32G071/081 (from RM0444) @@ -559,7 +559,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7000, // 28K (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 8*4, + .option_size = 4, }, { // STM32G431/441 (from RM0440) @@ -575,7 +575,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7000, // 28K (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4*4, + .option_size = 4, }, { @@ -593,7 +593,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, .bootrom_size = 0x7000, // 28K (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4*4, + .option_size = 4, }, { // STM32WB55 (from RM0434) diff --git a/src/common.c b/src/common.c index 351c74497..66d21b2b4 100644 --- a/src/common.c +++ b/src/common.c @@ -2738,26 +2738,12 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, uint32_t len) { +static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t val; - if (len != 4) { - ELOG("Wrong length for writing option bytes, must be 4 is %d\n", len); - return -1; - } - - // Make sure we've loaded the context with the chip details - stlink_core_id(sl); - - /* Check if chip is supported and for correct address */ - if (sl->chip_id != STLINK_CHIPID_STM32_G0_CAT1 && - sl->chip_id != STLINK_CHIPID_STM32_G0_CAT2 && - sl->chip_id != STLINK_CHIPID_STM32_G4_CAT2 && - sl->chip_id != STLINK_CHIPID_STM32_G4_CAT3) { - ELOG("Option bytes writing is currently only supported for the STM32G0/G4\n"); - return -1; - } + (void) addr; + (void) len; if (unlock_flash_if(sl)) { ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); @@ -2783,7 +2769,7 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, uint32_t le /* Write options bytes */ uint32_t data; write_uint32((unsigned char*) &data, *(uint32_t*) (base)); - WLOG("Writing option bytes 0x%04x\n", data); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); //stlink_write_debug32(sl, addr, data); stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); @@ -2823,14 +2809,12 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, uint32_t le * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l0_cat2(stlink_t *sl, uint8_t* base, uint32_t len) { +static int stlink_write_option_bytes_l0_cat2(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t val; + (void) addr; + (void) len; - if (len != 4) { - ELOG("Wrong length for writting option bytes, must be 4 is %d\n", len); - return -1; - } stlink_read_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); if (val & STM32L0_FLASH_PELOCK_BIT) { WLOG("Unlocking flash\n"); @@ -2885,10 +2869,6 @@ static int stlink_write_option_bytes_l1(stlink_t *sl, uint8_t* base, stm32_addr_ uint32_t val; uint32_t data; - if (len != 4 && len != 8) { - ELOG("Wrong length for writting option bytes, must be 4 or 8 is %d\n", len); - return -1; - } stlink_read_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); if (val & STM32L1_FLASH_PELOCK_BIT) { WLOG("Unlocking flash\n"); @@ -2966,14 +2946,12 @@ static int stlink_write_option_bytes_l1(stlink_t *sl, uint8_t* base, stm32_addr_ * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l496x(stlink_t *sl, uint8_t* base, uint32_t len) { +static int stlink_write_option_bytes_l496x(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t val; - if (len != 4) { - ELOG("Wrong length for writting option bytes, must be 4 is %d\n", len); - return -1; - } + (void) addr; + (void) len; /* Unlock flash if necessary */ stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); @@ -3047,8 +3025,18 @@ static int stlink_write_option_bytes_l496x(stlink_t *sl, uint8_t* base, uint32_t * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f2(stlink_t *sl, uint32_t option_byte) { +static int stlink_write_option_bytes_f2(stlink_t *sl, uint8_t *base, stm32_addr_t addr, size_t len) { uint32_t val; + uint32_t option_byte; + + (void) addr; /* todo: add sanitary check */ + + if(len != 4) { + ELOG("Wrong length for writting option bytes, must be 4 is %d\n", len); + return -1; + } + + option_byte = *(uint32_t*) (base); stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); if (val & FLASH_F2_OPT_LOCK_BIT) { @@ -3097,8 +3085,18 @@ static int stlink_write_option_bytes_f2(stlink_t *sl, uint32_t option_byte) { * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f4(stlink_t *sl, uint32_t option_byte) { +static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t val; + uint32_t option_byte; + + (void) addr; /* todo: add sanitary check */ + + if(len != 4) { + ELOG("Wrong length for writing option bytes, must be 4 is %d\n", len); + return -1; + } + + option_byte = *(uint32_t*) (base); stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); if (val & FLASH_F4_OPT_LOCK_BIT) { @@ -3219,25 +3217,54 @@ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { return 0; } +/** +* Read first option bytes +* @param sl +* @param option_byte option value +* @return 0 on success, -ve on failure. +*/ +int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) +{ + return stlink_read_debug32(sl, sl->option_base, option_byte); +} /** * Read option bytes * @param sl - * @param option_byte value to read + * @param option_byte option value * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes(stlink_t *sl, uint32_t* option_byte) { - int err = -1; - if (sl->chip_id == STLINK_CHIPID_STM32_F2){ - err = stlink_read_option_bytes_f2(sl, option_byte); - }else if(sl->chip_id == STLINK_CHIPID_STM32_F446){ - err = stlink_read_option_bytes_f4(sl, option_byte); - }else if(sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { - err = stlink_read_option_bytes_Gx(sl, option_byte); - }else{ - ELOG("This format is only available for STM32F2, STM32F4, STM32G0 and STM32G4\n"); +int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) +{ + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F2: + return stlink_read_option_bytes_f2(sl, option_byte); + case STLINK_CHIPID_STM32_F446: + return stlink_read_option_bytes_f4(sl, option_byte); + case STLINK_CHIPID_STM32_G0_CAT1: + case STLINK_CHIPID_STM32_G0_CAT2: + case STLINK_CHIPID_STM32_G4_CAT2: + case STLINK_CHIPID_STM32_G4_CAT3: + return stlink_read_option_bytes_Gx(sl, option_byte); + default: + return stlink_read_option_bytes_generic(sl, option_byte); } - return err; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) +{ + WLOG("About to write option byte %#10x to target.\n", option_byte); + return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *) &option_byte, 4); } /** @@ -3247,34 +3274,42 @@ int stlink_read_option_bytes(stlink_t *sl, uint32_t* option_byte) { * @param base option bytes to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) +{ + if (sl->option_base == 0) { + ELOG("Option bytes writing is currently not supported for connected chip\n"); + return -1; + } - // Make sure we've loaded the context with the chip details - stlink_core_id(sl); + if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { + ELOG("Option bytes start address out of Option bytes range\n"); + return -1; + } - WLOG("Option bytes write chip_id 0x%08x addr 0x%08x\n",sl->chip_id,addr); + if (addr + len > sl->option_base + sl->option_size) { + ELOG("Option bytes data too long\n"); + return -1; + } - /* Check if chip is supported and for correct address */ - if (((sl->chip_id == STLINK_CHIPID_STM32_G0_CAT1) || - (sl->chip_id == STLINK_CHIPID_STM32_G0_CAT2)) && (addr == STM32_G0_OPTION_BYTES_BASE)) { - return stlink_write_option_bytes_gx(sl, base, len); - } - else if (((sl->chip_id == STLINK_CHIPID_STM32_G4_CAT2) || - (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3)) && (addr == STM32_G4_OPTION_BYTES_BASE)) { - return stlink_write_option_bytes_gx(sl, base, len); - } - else if((sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) && (addr == STM32_L0_CAT2_OPTION_BYTES_BASE)) { - return stlink_write_option_bytes_l0_cat2(sl, base, len); - } - else if ((sl->chip_id == STLINK_CHIPID_STM32_L496X) && (addr == STM32_L496X_OPTION_BYTES_BASE)) { - return stlink_write_option_bytes_l496x(sl, base, len); - } - else if (((sl->chip_id == STLINK_CHIPID_STM32_L152_RE) || (sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH) ) && - ((addr == STM32_L1_OPTION_BYTES_BASE) || (addr == STM32_L1_OPTION_BYTES_BASE+4))) { + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F2: + return stlink_write_option_bytes_f2(sl, base, addr, len); + case STLINK_CHIPID_STM32_F446: + return stlink_write_option_bytes_f4(sl, base, addr, len); + case STLINK_CHIPID_STM32_L0_CAT2: + return stlink_write_option_bytes_l0_cat2(sl, base, addr, len); + case STLINK_CHIPID_STM32_L496X: + return stlink_write_option_bytes_l496x(sl, base, addr, len); + case STLINK_CHIPID_STM32_L152_RE: + case STLINK_CHIPID_STM32_L1_HIGH: return stlink_write_option_bytes_l1(sl, base, addr, len); - } - else { - ELOG("Option bytes writing is currently only supported for the STM32F2, STM32G0, STM32L496x/L4A6x, STM32L1 and STM32L0\n"); + case STLINK_CHIPID_STM32_G0_CAT1: + case STLINK_CHIPID_STM32_G0_CAT2: + case STLINK_CHIPID_STM32_G4_CAT2: + case STLINK_CHIPID_STM32_G4_CAT3: + return stlink_write_option_bytes_gx(sl, base, addr, len); + default: + ELOG("Option bytes writing is currently not implemented for connected chip\n"); return -1; } @@ -3306,23 +3341,3 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr unmap_file(&mf); return err; } - -/** - * Write the given 32-bit value with option byte - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_fwrite_option_bytes_32bit(stlink_t *sl, uint32_t val) { - - if (sl->chip_id == STLINK_CHIPID_STM32_F2){ - return stlink_write_option_bytes_f2(sl, val); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F446){ - return stlink_write_option_bytes_f4(sl, val); - } - else - { - ELOG("Option bytes writing is currently only supported for the STM32F2, STM32F4, STM32G0 and STM32L0\n"); - return -1; - } -} diff --git a/src/tools/flash.c b/src/tools/flash.c index 06256823c..20fbacd9a 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -160,9 +160,8 @@ int main(int ac, char** av) goto on_error; } } - else if (o.addr == STM32_G0_OPTION_BYTES_BASE || - o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE || - o.addr == STM32_L0_CAT2_OPTION_BYTES_BASE + 4){ + else if ((o.addr >= sl->option_base) && + (o.addr < sl->option_base + sl->option_size)) { err = stlink_fwrite_option_bytes(sl, o.filename, o.addr); if (err == -1) { @@ -171,10 +170,11 @@ int main(int ac, char** av) } } else if (o.area == FLASH_OPTION_BYTES){ - err = stlink_fwrite_option_bytes_32bit(sl, o.val); + // XXX some sanity check should be done here to check o.val parsing. + err = stlink_write_option_bytes32(sl, o.val); if (err == -1) { - printf("stlink_fwrite_option_bytes() == -1\n"); + printf("stlink_write_option_bytes32() == -1\n"); goto on_error; } } @@ -209,7 +209,7 @@ int main(int ac, char** av) { if(o.area == FLASH_OPTION_BYTES){ uint32_t option_byte; - err = stlink_read_option_bytes(sl, &option_byte); + err = stlink_read_option_bytes32(sl, &option_byte); if (err == -1) { printf("could not read option bytes (%d)\n", err); goto on_error; From e146a28a67cdfea1d4e9b5bf76471e05fe692494 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 14 Apr 2020 19:01:05 +0200 Subject: [PATCH 0829/1435] st-flash: add sanity check to option flash. current opt parse code can make bad cmdline parameter attempt to flash bad flash option. ie: calling st-flash write --area=option a_file.bin will make parser attempt to translate "a_file.bon" to an uint32 and will return 0.., --- src/tools/flash.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/tools/flash.c b/src/tools/flash.c index 20fbacd9a..e91001659 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -170,7 +170,11 @@ int main(int ac, char** av) } } else if (o.area == FLASH_OPTION_BYTES){ - // XXX some sanity check should be done here to check o.val parsing. + if (o.val == 0) { + printf("attempting to set option byte to 0, abort.\n"); + goto on_error; + } + err = stlink_write_option_bytes32(sl, o.val); if (err == -1) { From 3aaec273da217faf54601c02480ce990baa09894 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Thu, 16 Apr 2020 15:12:40 +0200 Subject: [PATCH 0830/1435] common.c: fix define - use Gx Base for Gx defines avoid some potential issues later. --- src/common.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/common.c b/src/common.c index 66d21b2b4..0ccdeccdb 100644 --- a/src/common.c +++ b/src/common.c @@ -79,13 +79,13 @@ // Flash registers common to STM32G0 and STM32G4 series. #define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32Gx_FLASH_ACR (STM32G0_FLASH_REGS_ADDR + 0x00) -#define STM32Gx_FLASH_KEYR (STM32G0_FLASH_REGS_ADDR + 0x08) -#define STM32Gx_FLASH_OPTKEYR (STM32G0_FLASH_REGS_ADDR + 0x0c) -#define STM32Gx_FLASH_SR (STM32G0_FLASH_REGS_ADDR + 0x10) -#define STM32Gx_FLASH_CR (STM32G0_FLASH_REGS_ADDR + 0x14) -#define STM32Gx_FLASH_ECCR (STM32G0_FLASH_REGS_ADDR + 0x18) -#define STM32Gx_FLASH_OPTR (STM32G0_FLASH_REGS_ADDR + 0x20) +#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) +#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) +#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) +#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) +#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) +#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) +#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) // G0 (RM0444 Table 1, sec 3.7) // Mostly the same as G4 chips, but the notation From 977576215e64b9b138fff890f8fbf52d17572e4d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 16 Apr 2020 21:00:30 +0200 Subject: [PATCH 0831/1435] Partial project restructuring - Updated travis CI build config - Refactoring of cmake build config - Alligned coding style for GUI - Whitespace cleanup for GUI - Moved source code for GUI --- .travis.sh | 13 +- .travis.yml | 24 +- CMakeLists.txt | 48 +- cmake/c_flag_overrides.cmake | 7 - {usr/lib => debian}/pkgconfig/CMakeLists.txt | 0 .../pkgconfig/pkg-config.pc.cmake | 0 src/{tools/gui => stlink-gui}/CMakeLists.txt | 21 +- .../gui/stlink-gui.c => stlink-gui/gui.c} | 625 +++++++----------- .../gui/stlink-gui.h => stlink-gui/gui.h} | 6 +- .../gui/stlink-gui.ui => stlink-gui/gui.ui} | 0 src/stlink-gui/icons/export-icons.sh | 40 ++ .../hicolor/128x128/apps/stlink-gui.png | Bin .../icons}/hicolor/16x16/apps/stlink-gui.png | Bin .../icons}/hicolor/22x22/apps/stlink-gui.png | Bin .../icons}/hicolor/24x24/apps/stlink-gui.png | Bin .../hicolor/256x256/apps/stlink-gui.png | Bin .../icons}/hicolor/32x32/apps/stlink-gui.png | Bin .../icons}/hicolor/48x48/apps/stlink-gui.png | Bin .../icons}/hicolor/64x64/apps/stlink-gui.png | Bin .../art => stlink-gui/icons}/stlink-gui.png | Bin .../art => stlink-gui/icons}/stlink-gui.svg | 0 .../art => stlink-gui/icons}/stlink-gui.xpm | 0 .../icons}/stlink-gui_48.png | Bin .../gui => stlink-gui}/stlink-gui.desktop | 0 src/tools/gui/art/export-icons.sh | 38 -- 25 files changed, 324 insertions(+), 498 deletions(-) delete mode 100644 cmake/c_flag_overrides.cmake rename {usr/lib => debian}/pkgconfig/CMakeLists.txt (100%) rename {usr/lib => debian}/pkgconfig/pkg-config.pc.cmake (100%) rename src/{tools/gui => stlink-gui}/CMakeLists.txt (55%) rename src/{tools/gui/stlink-gui.c => stlink-gui/gui.c} (62%) rename src/{tools/gui/stlink-gui.h => stlink-gui/gui.h} (98%) rename src/{tools/gui/stlink-gui.ui => stlink-gui/gui.ui} (100%) create mode 100644 src/stlink-gui/icons/export-icons.sh rename src/{tools/gui/art => stlink-gui/icons}/hicolor/128x128/apps/stlink-gui.png (100%) rename src/{tools/gui/art => stlink-gui/icons}/hicolor/16x16/apps/stlink-gui.png (100%) rename src/{tools/gui/art => stlink-gui/icons}/hicolor/22x22/apps/stlink-gui.png (100%) rename src/{tools/gui/art => stlink-gui/icons}/hicolor/24x24/apps/stlink-gui.png (100%) rename src/{tools/gui/art => stlink-gui/icons}/hicolor/256x256/apps/stlink-gui.png (100%) rename src/{tools/gui/art => stlink-gui/icons}/hicolor/32x32/apps/stlink-gui.png (100%) rename src/{tools/gui/art => stlink-gui/icons}/hicolor/48x48/apps/stlink-gui.png (100%) rename src/{tools/gui/art => stlink-gui/icons}/hicolor/64x64/apps/stlink-gui.png (100%) rename src/{tools/gui/art => stlink-gui/icons}/stlink-gui.png (100%) rename src/{tools/gui/art => stlink-gui/icons}/stlink-gui.svg (100%) rename src/{tools/gui/art => stlink-gui/icons}/stlink-gui.xpm (100%) rename src/{tools/gui/art => stlink-gui/icons}/stlink-gui_48.png (100%) rename src/{tools/gui => stlink-gui}/stlink-gui.desktop (100%) delete mode 100755 src/tools/gui/art/export-icons.sh diff --git a/.travis.sh b/.travis.sh index 3d6da055f..5291ec95b 100755 --- a/.travis.sh +++ b/.travis.sh @@ -24,13 +24,12 @@ if [ "$TRAVIS_OS_NAME" == "linux" ]; then cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ make && make package && cd - - echo "--> Building Binary..." - mkdir -p build/Binary && cd build/Binary - cho "-DCMAKE_BUILD_TYPE=Binary -DCMAKE_INSTALL_PREFIX=$PWD/_install" - cmake -DCMAKE_BUILD_TYPE=Binary -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ - make && make package && cd - - -else #("$TRAVIS_OS_NAME" == "osx") +# echo "--> Building Binary..." +# mkdir -p build/Binary && cd build/Binary +# cho "-DCMAKE_BUILD_TYPE=Binary -DCMAKE_INSTALL_PREFIX=$PWD/_install" +# cmake -DCMAKE_BUILD_TYPE=Binary -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ +# make && make package && cd - +else [ "$TRAVIS_OS_NAME" == "osx" ]; brew install libusb echo "--> Building Debug..." diff --git a/.travis.yml b/.travis.yml index 221e8ece7..542a25d98 100644 --- a/.travis.yml +++ b/.travis.yml @@ -38,14 +38,14 @@ matrix: apt: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] packages: ['clang-6.0', 'libusb-1.0.0-dev'] - - os: linux - arch: x64 - compiler: clang-6.0 - addons: - apt: - sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] - packages: ['clang-6.0', 'libusb-1.0.0-dev'] - env: CFLAGS=-m32 LDFLAGS=-m32 +# - os: linux +# arch: x64 +# compiler: clang-6.0 +# addons: +# apt: +# sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] +# packages: ['clang-6.0', 'libusb-1.0.0-dev'] +# env: CFLAGS=-m32 LDFLAGS=-m32 ### 32-bit builds ### - os: linux @@ -57,18 +57,18 @@ matrix: packages: ['gcc-5', 'libusb-1.0.0-dev'] - os: linux arch: x86 - compiler: gcc-6 + compiler: gcc-7 addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-6', 'libusb-1.0.0-dev'] + packages: ['gcc-7', 'libusb-1.0.0-dev'] - os: linux arch: x86 - compiler: gcc-7 + compiler: gcc-9 addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-7', 'libusb-1.0.0-dev'] + packages: ['gcc-9', 'libusb-1.0.0-dev'] - os: linux arch: x86 compiler: clang-3.7 diff --git a/CMakeLists.txt b/CMakeLists.txt index 3572c2a15..87bd47aac 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,16 +1,24 @@ cmake_minimum_required(VERSION 3.4.2) -set(CMAKE_USER_MAKE_RULES_OVERRIDE cmake/c_flag_overrides.cmake) +cmake_policy(SET CMP0042 NEW) +set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") +include(GNUInstallDirs) project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics ST-LINK Tools") -include(GNUInstallDirs) + set(STLINK_UDEV_RULES_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/udev/rules.d" CACHE PATH "udev rules directory") set(STLINK_MODPROBED_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/modprobe.d" CACHE PATH "modprobe.d directory") set(STLINK_STATIC_LIB ON CACHE BOOL "Install static lib") -set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) -set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) -set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) +option(STLINK_INSTALL_UDEV_RULES "Install udev rules files" ON) +option(STLINK_INSTALL_MODPROBE_CONF "Install modprobe conf files" ON) +option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) + +# ==== + +#set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) +#set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) +#set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) if (IS_DIRECTORY ${LIB_INSTALL_DIR}) set(LIB_INSTALL_DIR ${LIB_INSTALL_DIR} CACHE PATH "Main library directory") @@ -28,17 +36,16 @@ else () set(STLINK_INCLUDE_PATH "${CMAKE_INSTALL_PREFIX}/${INCLUDE_INSTALL_DIR}") endif () -option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) -option(STLINK_INSTALL_UDEV_RULES "Install udev rules files" ON) -option(STLINK_INSTALL_MODPROBE_CONF "Install modprobe conf files" ON) - -# cmake (3.0+) on MacOS should use @rpath -cmake_policy(SET CMP0042 NEW) - -set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") include(cmake/version.cmake) + if (NOT MSVC) include(cmake/c_flags.cmake) +else () + message(STATUS "MSVC C Flags override to /MT") + set(CMAKE_C_FLAGS_DEBUG_INIT "/D_DEBUG /MTd /Zi /Ob0 /Od /RTC1") + set(CMAKE_C_FLAGS_MINSIZEREL_INIT "/MT /O1 /Ob1 /D NDEBUG") + set(CMAKE_C_FLAGS_RELEASE_INIT "/MT /O2 /Ob2 /D NDEBUG") + set(CMAKE_C_FLAGS_RELWITHDEBINFO_INIT "/MT /Zi /O2 /Ob1 /D NDEBUG") endif () @@ -207,16 +214,13 @@ endif () ### add_executable(st-flash src/tools/flash.c src/tools/flash_opts.c) -if (WIN32 OR APPLE) - target_link_libraries(st-flash ${STLINK_LIB_STATIC} ${SSP_LIB}) -else () - target_link_libraries(st-flash ${STLINK_LIB_SHARED} ${SSP_LIB}) -endif () - add_executable(st-info src/tools/info.c) + if (WIN32 OR APPLE) + target_link_libraries(st-flash ${STLINK_LIB_STATIC} ${SSP_LIB}) target_link_libraries(st-info ${STLINK_LIB_STATIC} ${SSP_LIB}) else () + target_link_libraries(st-flash ${STLINK_LIB_SHARED} ${SSP_LIB}) target_link_libraries(st-info ${STLINK_LIB_SHARED} ${SSP_LIB}) endif () @@ -233,14 +237,14 @@ if (CMAKE_SYSTEM_NAME STREQUAL "Linux") endif () add_subdirectory(src/gdbserver) -add_subdirectory(src/tools/gui) +add_subdirectory(src/stlink-gui) ### # Others ### -add_subdirectory(usr/lib/pkgconfig) +add_subdirectory(debian/pkgconfig) add_subdirectory(include) add_subdirectory(doc/man) add_subdirectory(tests) @@ -248,6 +252,8 @@ add_subdirectory(tests) include(cmake/cpack_config.cmake) include(CPack) +# ==== + ### # Uninstall target diff --git a/cmake/c_flag_overrides.cmake b/cmake/c_flag_overrides.cmake deleted file mode 100644 index 1a1d163fb..000000000 --- a/cmake/c_flag_overrides.cmake +++ /dev/null @@ -1,7 +0,0 @@ -if (MSVC) - message(STATUS "MSVC C Flags override to /MT") - set(CMAKE_C_FLAGS_DEBUG_INIT "/D_DEBUG /MTd /Zi /Ob0 /Od /RTC1") - set(CMAKE_C_FLAGS_MINSIZEREL_INIT "/MT /O1 /Ob1 /D NDEBUG") - set(CMAKE_C_FLAGS_RELEASE_INIT "/MT /O2 /Ob2 /D NDEBUG") - set(CMAKE_C_FLAGS_RELWITHDEBINFO_INIT "/MT /Zi /O2 /Ob1 /D NDEBUG") -endif () diff --git a/usr/lib/pkgconfig/CMakeLists.txt b/debian/pkgconfig/CMakeLists.txt similarity index 100% rename from usr/lib/pkgconfig/CMakeLists.txt rename to debian/pkgconfig/CMakeLists.txt diff --git a/usr/lib/pkgconfig/pkg-config.pc.cmake b/debian/pkgconfig/pkg-config.pc.cmake similarity index 100% rename from usr/lib/pkgconfig/pkg-config.pc.cmake rename to debian/pkgconfig/pkg-config.pc.cmake diff --git a/src/tools/gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt similarity index 55% rename from src/tools/gui/CMakeLists.txt rename to src/stlink-gui/CMakeLists.txt index d7add834b..bb6465481 100644 --- a/src/tools/gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -3,32 +3,31 @@ if (NOT gtk_FOUND) return() endif () -set(GUI_SOURCES stlink-gui.c stlink-gui.h) -set(INSTALLED_UI_DIR share/stlink) +set(GUI_SOURCES gui.c gui.h) +set(INSTALLED_UI_DIR share/stlink) ### TODO: Check Path include_directories(SYSTEM ${gtk_INCLUDE_DIRS}) +# stlink-gui-local add_executable(stlink-gui-local ${GUI_SOURCES}) set_target_properties( stlink-gui-local PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_CURRENT_SOURCE_DIR}" + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_CURRENT_SOURCE_DIR}" ### TODO: Check Path ) target_link_libraries(stlink-gui-local ${STLINK_LIB_STATIC} ${gtk_LDFLAGS} ${SSP_LIB}) - +# stlink-gui add_executable(stlink-gui ${GUI_SOURCES}) set_target_properties( stlink-gui PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/${INSTALLED_UI_DIR}" + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/${INSTALLED_UI_DIR}" ### TODO: Check Path ) target_link_libraries(stlink-gui ${STLINK_LIB_STATIC} ${gtk_LDFLAGS} ${SSP_LIB}) -install(TARGETS stlink-gui RUNTIME DESTINATION bin) -install(FILES stlink-gui.ui DESTINATION ${INSTALLED_UI_DIR}) +install(TARGETS stlink-gui RUNTIME DESTINATION bin) ### TODO: Check Path +install(FILES gui.ui DESTINATION ${INSTALLED_UI_DIR}) ### TODO: Check Path if (${CMAKE_SYSTEM_NAME} MATCHES "Linux") - # Install desktop entry - install(FILES stlink-gui.desktop DESTINATION share/applications) - # Install icon - install(FILES art/stlink-gui.svg DESTINATION share/icons/hicolor/scalable/apps) + install(FILES stlink-gui.desktop DESTINATION share/applications) # Install desktop entry + install(FILES icons/stlink-gui.svg DESTINATION share/icons/hicolor/scalable/apps) # Install icon endif () diff --git a/src/tools/gui/stlink-gui.c b/src/stlink-gui/gui.c similarity index 62% rename from src/tools/gui/stlink-gui.c rename to src/stlink-gui/gui.c index 0dc8bd723..f90196c06 100644 --- a/src/tools/gui/stlink-gui.c +++ b/src/stlink-gui/gui.c @@ -1,11 +1,11 @@ -#include -#include #include +#include +#include #include #include #include -#include "stlink-gui.h" +#include "gui.h" #define MEM_READ_SIZE 1024 @@ -15,30 +15,21 @@ G_DEFINE_TYPE (STlinkGUI, stlink_gui, G_TYPE_OBJECT); -static void -stlink_gui_dispose (GObject *gobject) -{ +static void stlink_gui_dispose (GObject *gobject) { G_OBJECT_CLASS (stlink_gui_parent_class)->dispose (gobject); } -static void -stlink_gui_finalize (GObject *gobject) -{ +static void stlink_gui_finalize (GObject *gobject) { G_OBJECT_CLASS (stlink_gui_parent_class)->finalize (gobject); } -static void -stlink_gui_class_init (STlinkGUIClass *klass) -{ +static void stlink_gui_class_init (STlinkGUIClass *klass) { GObjectClass *gobject_class = G_OBJECT_CLASS (klass); - gobject_class->dispose = stlink_gui_dispose; gobject_class->finalize = stlink_gui_finalize; } -static void -stlink_gui_init (STlinkGUI *self) -{ +static void stlink_gui_init (STlinkGUI *self) { self->sl = NULL; self->filename = NULL; @@ -54,9 +45,7 @@ stlink_gui_init (STlinkGUI *self) self->file_mem.base = 0; } -static gboolean -set_info_error_message_idle (STlinkGUI *gui) -{ +static gboolean set_info_error_message_idle (STlinkGUI *gui) { if (gui->error_message != NULL) { gchar *markup; @@ -72,40 +61,31 @@ set_info_error_message_idle (STlinkGUI *gui) return FALSE; } -static void -stlink_gui_set_info_error_message (STlinkGUI *gui, const gchar *message) -{ +static void stlink_gui_set_info_error_message (STlinkGUI *gui, const gchar *message) { gui->error_message = g_strdup (message); g_idle_add ((GSourceFunc) set_info_error_message_idle, gui); } -static void -stlink_gui_set_sensitivity (STlinkGUI *gui, gboolean sensitivity) -{ +static void stlink_gui_set_sensitivity (STlinkGUI *gui, gboolean sensitivity) { gtk_widget_set_sensitive (GTK_WIDGET (gui->open_button), sensitivity); - if (sensitivity && gui->sl) gtk_widget_set_sensitive (GTK_WIDGET (gui->disconnect_button), sensitivity); - if (sensitivity && !gui->sl) gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), sensitivity); - if (sensitivity && gui->sl && gui->filename) gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), sensitivity); - gtk_widget_set_sensitive (GTK_WIDGET (gui->export_button), sensitivity && (gui->sl != NULL)); } -static void -mem_view_init_headers (GtkTreeView *view) -{ +static void mem_view_init_headers (GtkTreeView *view) { GtkCellRenderer *renderer; gint i; g_return_if_fail (view != NULL); renderer = gtk_cell_renderer_text_new (); - gtk_tree_view_insert_column_with_attributes (view, + gtk_tree_view_insert_column_with_attributes ( + view, -1, "Address", renderer, @@ -133,12 +113,11 @@ mem_view_init_headers (GtkTreeView *view) } } -static void -mem_view_add_as_hex (GtkListStore *store, - GtkTreeIter *iter, - gint column, - guint32 value) -{ +static void mem_view_add_as_hex ( + GtkListStore *store, + GtkTreeIter *iter, + gint column, + guint32 value) { gchar *hex_str; hex_str = g_strdup_printf ("0x%08X", value); @@ -146,13 +125,12 @@ mem_view_add_as_hex (GtkListStore *store, g_free (hex_str); } -static void -mem_view_add_buffer (GtkListStore *store, - GtkTreeIter *iter, - guint32 address, - guchar *buffer, - gint len) -{ +static void mem_view_add_buffer ( + GtkListStore *store, + GtkTreeIter *iter, + guint32 address, + guchar *buffer, + gint len) { guint32 *word; gint i, step; gint column = 0; @@ -174,61 +152,41 @@ mem_view_add_buffer (GtkListStore *store, } } -static guint32 -hexstr_to_guint32 (const gchar *str, GError **err) -{ +static guint32 hexstr_to_guint32 (const gchar *str, GError **err) { guint32 val; gchar *end_ptr; val = (guint32) strtoul (str, &end_ptr, 16); if ((errno == ERANGE && val == UINT_MAX) || (errno != 0 && val == 0)) { - g_set_error (err, - g_quark_from_string ("hextou32"), - 1, - "Invalid hexstring"); + g_set_error (err, g_quark_from_string ("hextou32"), 1, "Invalid hexstring"); return UINT32_MAX; } if (end_ptr == str) { - g_set_error (err, - g_quark_from_string ("hextou32"), - 2, - "Invalid hexstring"); + g_set_error (err, g_quark_from_string ("hextou32"), 2, "Invalid hexstring"); return UINT32_MAX; } return val; } - -static void -stlink_gui_update_mem_view (STlinkGUI *gui, struct mem_t *mem, GtkTreeView *view) { +static void stlink_gui_update_mem_view (STlinkGUI *gui, struct mem_t *mem, GtkTreeView *view) { GtkListStore *store; GtkTreeIter iter; store = GTK_LIST_STORE (gtk_tree_view_get_model (view)); - mem_view_add_buffer (store, - &iter, - mem->base, - mem->memory, - (gint) mem->size); + mem_view_add_buffer (store, &iter, mem->base, mem->memory, (gint) mem->size); gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); gtk_progress_bar_set_fraction (gui->progress.bar, 0); stlink_gui_set_sensitivity (gui, TRUE); } -static gboolean -stlink_gui_update_devmem_view (STlinkGUI *gui) -{ +static gboolean stlink_gui_update_devmem_view (STlinkGUI *gui) { stlink_gui_update_mem_view (gui, &gui->flash_mem, gui->devmem_treeview); return FALSE; } - - -static gpointer -stlink_gui_populate_devmem_view (gpointer data) -{ +static gpointer stlink_gui_populate_devmem_view (gpointer data) { guint off; stm32_addr_t addr; @@ -240,23 +198,21 @@ stlink_gui_populate_devmem_view (gpointer data) addr = gui->sl->flash_base; - if (gui->flash_mem.memory) { + if (gui->flash_mem.memory) g_free (gui->flash_mem.memory); - } gui->flash_mem.memory = g_malloc (gui->sl->flash_size); gui->flash_mem.size = gui->sl->flash_size; gui->flash_mem.base = gui->sl->flash_base; for (off = 0; off < gui->sl->flash_size; off += MEM_READ_SIZE) { - guint n_read = MEM_READ_SIZE; + guint n_read = MEM_READ_SIZE; if (off + MEM_READ_SIZE > gui->sl->flash_size) { n_read = (guint) gui->sl->flash_size - off; /* align if needed */ - if (n_read & 3) { + if (n_read & 3) n_read = (n_read + 4) & ~(3); - } } /* reads to sl->q_buf */ stlink_read_mem32(gui->sl, addr + off, n_read); @@ -270,29 +226,22 @@ stlink_gui_populate_devmem_view (gpointer data) gui->progress.fraction = (gdouble) (off + n_read) / gui->sl->flash_size; } g_idle_add ((GSourceFunc) stlink_gui_update_devmem_view, gui); - return NULL; } -static gboolean -stlink_gui_update_filemem_view (STlinkGUI *gui) -{ +static gboolean stlink_gui_update_filemem_view (STlinkGUI *gui) { gchar *basename; basename = g_path_get_basename (gui->filename); gtk_notebook_set_tab_label_text (gui->notebook, - GTK_WIDGET (gtk_notebook_get_nth_page (gui->notebook, 1)), - basename); + GTK_WIDGET (gtk_notebook_get_nth_page (gui->notebook, 1)), basename); g_free (basename); stlink_gui_update_mem_view (gui, &gui->file_mem, gui->filemem_treeview); - return FALSE; } -static gpointer -stlink_gui_populate_filemem_view (gpointer data) -{ +static gpointer stlink_gui_populate_filemem_view (gpointer data) { guchar buffer[MEM_READ_SIZE]; GFile *file; GFileInfo *file_info; @@ -306,81 +255,73 @@ stlink_gui_populate_filemem_view (gpointer data) g_return_val_if_fail (gui != NULL, NULL); g_return_val_if_fail (gui->filename != NULL, NULL); - if (g_str_has_suffix (gui->filename, ".hex")) { - // If the file has prefix .hex - try to interpret it as Intel-HEX. - // It's difficult to merge the world of standard functions and GLib, - // so do it simple - load whole file into buffer and copy the data - // to the destination afterwards. - // We loose meanwhile the displaying of the progress and need - // double memory. - - uint8_t* mem = NULL; - size_t size = 0; - uint32_t begin = 0; - int res = stlink_parse_ihex (gui->filename, 0, &mem, &size, &begin); - - if (res == 0) { - if (gui->file_mem.memory) { - g_free (gui->file_mem.memory); - } - gui->file_mem.size = size; - gui->file_mem.memory = g_malloc (size); - gui->file_mem.base = begin; - - memcpy (gui->file_mem.memory, mem, size); - } - else { - stlink_gui_set_info_error_message (gui, "Cannot interpret the file as Intel-HEX"); - } - - free(mem); - } - else { - file = g_file_new_for_path (gui->filename); - input_stream = G_INPUT_STREAM (g_file_read (file, NULL, &err)); - if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); - goto out; - } - - file_info = g_file_input_stream_query_info (G_FILE_INPUT_STREAM (input_stream), - G_FILE_ATTRIBUTE_STANDARD_SIZE, NULL, &err); - if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); - goto out_input; - } - if (gui->file_mem.memory) { - g_free (gui->file_mem.memory); - } - gui->file_mem.size = g_file_info_get_size (file_info); - gui->file_mem.memory = g_malloc (gui->file_mem.size); - - for (off = 0; off < (gint) gui->file_mem.size; off += MEM_READ_SIZE) { - guint n_read = MEM_READ_SIZE; - - if (off + MEM_READ_SIZE > (gint) gui->file_mem.size) { - n_read = (guint) gui->file_mem.size - off; - } - - if (g_input_stream_read (G_INPUT_STREAM (input_stream), - &buffer, n_read, NULL, &err) == -1) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); - goto out_input; - } - memcpy (gui->file_mem.memory + off, buffer, n_read); - gui->progress.fraction = (gdouble) (off + n_read) / gui->file_mem.size; - } - -out_input: - g_object_unref (input_stream); -out: - g_object_unref (file); - } - - g_idle_add ((GSourceFunc) stlink_gui_update_filemem_view, gui); + if (g_str_has_suffix (gui->filename, ".hex")) { + // If the file has prefix .hex - try to interpret it as Intel-HEX. + // It's difficult to merge the world of standard functions and GLib, + // so do it simple - load whole file into buffer and copy the data to the + // destination afterwards. + // We loose meanwhile the displaying of the progress and need double memory. + + uint8_t* mem = NULL; + size_t size = 0; + uint32_t begin = 0; + int res = stlink_parse_ihex (gui->filename, 0, &mem, &size, &begin); + + if (res == 0) { + if (gui->file_mem.memory) + g_free (gui->file_mem.memory); + gui->file_mem.size = size; + gui->file_mem.memory = g_malloc (size); + gui->file_mem.base = begin; + + memcpy (gui->file_mem.memory, mem, size); + } else { + stlink_gui_set_info_error_message (gui, "Cannot interpret the file as Intel-HEX"); + } + + free(mem); + } else { + file = g_file_new_for_path (gui->filename); + input_stream = G_INPUT_STREAM (g_file_read (file, NULL, &err)); + if (err) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + goto out; + } + + file_info = g_file_input_stream_query_info (G_FILE_INPUT_STREAM (input_stream), + G_FILE_ATTRIBUTE_STANDARD_SIZE, NULL, &err); + if (err) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + goto out_input; + } + if (gui->file_mem.memory) + g_free (gui->file_mem.memory); + gui->file_mem.size = g_file_info_get_size (file_info); + gui->file_mem.memory = g_malloc (gui->file_mem.size); + + for (off = 0; off < (gint) gui->file_mem.size; off += MEM_READ_SIZE) { + guint n_read = MEM_READ_SIZE; + + if (off + MEM_READ_SIZE > (gint) gui->file_mem.size) + n_read = (guint) gui->file_mem.size - off; + + if (g_input_stream_read (G_INPUT_STREAM (input_stream), + &buffer, n_read, NULL, &err) == -1) { + stlink_gui_set_info_error_message (gui, err->message); + g_error_free (err); + goto out_input; + } + memcpy (gui->file_mem.memory + off, buffer, n_read); + gui->progress.fraction = (gdouble) (off + n_read) / gui->file_mem.size; + } + + out_input: g_object_unref (input_stream); + out: g_object_unref (file); + } + + g_idle_add ((GSourceFunc) stlink_gui_update_filemem_view, gui); return NULL; } @@ -388,29 +329,23 @@ static void mem_jmp (GtkTreeView *view, GtkEntry *entry, guint32 base_addr, gsize size, - GError **err) -{ + GError **err) { GtkTreeModel *model; guint32 jmp_addr; GtkTreeIter iter; jmp_addr = hexstr_to_guint32 (gtk_entry_get_text (entry), err); - if (err && *err) { + if (err && *err) return; - } if (jmp_addr < base_addr || jmp_addr > base_addr + size) { - g_set_error (err, - g_quark_from_string ("mem_jmp"), - 1, - "Invalid address"); + g_set_error (err, g_quark_from_string ("mem_jmp"), 1, "Invalid address"); return; } model = gtk_tree_view_get_model (view); - if (!model) { + if (!model) return; - } if (gtk_tree_model_get_iter_first (model, &iter)) { do { @@ -429,12 +364,7 @@ static void mem_jmp (GtkTreeView *view, path = gtk_tree_model_get_path (model, &iter); gtk_tree_selection_select_iter (selection, &iter); - gtk_tree_view_scroll_to_cell (view, - path, - NULL, - TRUE, - 0.0, - 0.0); + gtk_tree_view_scroll_to_cell (view, path, NULL, TRUE, 0.0, 0.0); gtk_tree_path_free (path); } } @@ -444,9 +374,7 @@ static void mem_jmp (GtkTreeView *view, } } -static void -devmem_jmp_cb (GtkWidget *widget, gpointer data) -{ +static void devmem_jmp_cb (GtkWidget *widget, gpointer data) { STlinkGUI *gui; GError *err = NULL; (void) widget; @@ -465,9 +393,7 @@ devmem_jmp_cb (GtkWidget *widget, gpointer data) } } -static void -filemem_jmp_cb (GtkWidget *widget, gpointer data) -{ +static void filemem_jmp_cb (GtkWidget *widget, gpointer data) { STlinkGUI *gui; GError *err = NULL; (void) widget; @@ -488,9 +414,7 @@ filemem_jmp_cb (GtkWidget *widget, gpointer data) } } -static gchar * -dev_format_chip_id (guint32 chip_id) -{ +static gchar *dev_format_chip_id (guint32 chip_id) { const struct stlink_chipid_params *params; params = stlink_chipid_get_params(chip_id); @@ -500,31 +424,25 @@ dev_format_chip_id (guint32 chip_id) return g_strdup (params->description); } -static gchar * -dev_format_mem_size (gsize flash_size) -{ +static gchar *dev_format_mem_size (gsize flash_size) { return g_strdup_printf ("%u kB", (unsigned int)(flash_size / 1024)); } -static void -stlink_gui_set_connected (STlinkGUI *gui) -{ +static void stlink_gui_set_connected (STlinkGUI *gui) { gchar *tmp_str; GtkListStore *store; GtkTreeIter iter; gtk_statusbar_push (gui->statusbar, - gtk_statusbar_get_context_id (gui->statusbar, "conn"), - "Connected"); + gtk_statusbar_get_context_id (gui->statusbar, "conn"), "Connected"); gtk_widget_set_sensitive (GTK_WIDGET (gui->device_frame), TRUE); gtk_widget_set_sensitive (GTK_WIDGET (gui->devmem_box), TRUE); gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), FALSE); - if (gui->filename) { + if (gui->filename) gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), TRUE); - } tmp_str = dev_format_chip_id (gui->sl->chip_id); gtk_label_set_text (gui->chip_id_label, tmp_str); @@ -548,9 +466,8 @@ stlink_gui_set_connected (STlinkGUI *gui) g_free (tmp_str); store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->devmem_treeview)); - if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) { + if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) gtk_list_store_clear (store); - } stlink_gui_set_sensitivity (gui, FALSE); gtk_notebook_set_current_page (gui->notebook, PAGE_DEVMEM); @@ -560,9 +477,7 @@ stlink_gui_set_connected (STlinkGUI *gui) g_thread_new ("devmem", (GThreadFunc) stlink_gui_populate_devmem_view, gui); } -static void -connect_button_cb (GtkWidget *widget, gpointer data) -{ +static void connect_button_cb (GtkWidget *widget, gpointer data) { STlinkGUI *gui; gint i; (void) widget; @@ -574,11 +489,11 @@ connect_button_cb (GtkWidget *widget, gpointer data) /* try version 1 then version 2 */ gui->sl = stlink_v1_open(0, 1); + if (gui->sl == NULL) + gui->sl = stlink_open_usb(0, 1, NULL); if (gui->sl == NULL) { - gui->sl = stlink_open_usb(0, 1, NULL); - } - if (gui->sl == NULL) { - stlink_gui_set_info_error_message (gui, "Failed to connect to STLink."); return; + stlink_gui_set_info_error_message (gui, "Failed to connect to STLink."); + return; } /* code below taken from flash/main.c, refactoring might be in order */ @@ -601,8 +516,7 @@ connect_button_cb (GtkWidget *widget, gpointer data) stlink_gui_set_connected (gui); } -static void stlink_gui_set_disconnected (STlinkGUI *gui) -{ +static void stlink_gui_set_disconnected (STlinkGUI *gui) { gtk_statusbar_push (gui->statusbar, gtk_statusbar_get_context_id (gui->statusbar, "conn"), "Disconnected"); @@ -614,9 +528,7 @@ static void stlink_gui_set_disconnected (STlinkGUI *gui) gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), TRUE); } -static void -disconnect_button_cb (GtkWidget *widget, gpointer data) -{ +static void disconnect_button_cb (GtkWidget *widget, gpointer data) { STlinkGUI *gui; (void) widget; @@ -631,9 +543,7 @@ disconnect_button_cb (GtkWidget *widget, gpointer data) } -static void -stlink_gui_open_file (STlinkGUI *gui) -{ +static void stlink_gui_open_file (STlinkGUI *gui) { GtkWidget *dialog; GtkListStore *store; GtkTreeIter iter; @@ -646,13 +556,11 @@ stlink_gui_open_file (STlinkGUI *gui) NULL); if (gtk_dialog_run (GTK_DIALOG (dialog)) == GTK_RESPONSE_ACCEPT) { - gui->filename = - gtk_file_chooser_get_filename (GTK_FILE_CHOOSER (dialog)); + gui->filename = gtk_file_chooser_get_filename (GTK_FILE_CHOOSER (dialog)); store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->filemem_treeview)); - if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) { + if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) gtk_list_store_clear (store); - } stlink_gui_set_sensitivity (gui, FALSE); gtk_notebook_set_current_page (gui->notebook, PAGE_FILEMEM); @@ -663,37 +571,30 @@ stlink_gui_open_file (STlinkGUI *gui) gtk_widget_destroy (dialog); } -static void -open_button_cb (GtkWidget *widget, gpointer data) -{ +static void open_button_cb (GtkWidget *widget, gpointer data) { STlinkGUI *gui; (void) widget; gui = STLINK_GUI (data); - stlink_gui_open_file (gui); } -static gboolean -stlink_gui_write_flash_update (STlinkGUI *gui) -{ +static gboolean stlink_gui_write_flash_update (STlinkGUI *gui) { stlink_gui_set_sensitivity (gui, TRUE); gui->progress.activity_mode = FALSE; gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); - return FALSE; } -static gpointer -stlink_gui_write_flash (gpointer data) -{ +static gpointer stlink_gui_write_flash (gpointer data) { g_return_val_if_fail (STLINK_IS_GUI (data), NULL); STlinkGUI *gui = (STlinkGUI *)data; g_return_val_if_fail ((gui->sl != NULL), NULL); g_return_val_if_fail ((gui->filename != NULL), NULL); - if (stlink_mwrite_flash(gui->sl, gui->file_mem.memory, (uint32_t)gui->file_mem.size, gui->sl->flash_base) < 0) { + if (stlink_mwrite_flash(gui->sl, gui->file_mem.memory, + (uint32_t)gui->file_mem.size, gui->sl->flash_base) < 0) { stlink_gui_set_info_error_message (gui, "Failed to write to flash"); } @@ -701,9 +602,7 @@ stlink_gui_write_flash (gpointer data) return NULL; } -static void -flash_button_cb (GtkWidget *widget, gpointer data) -{ +static void flash_button_cb (GtkWidget *widget, gpointer data) { STlinkGUI *gui; gchar *tmp_str; guint32 address; @@ -722,47 +621,38 @@ flash_button_cb (GtkWidget *widget, gpointer data) result = gtk_dialog_run (gui->flash_dialog); if (result == GTK_RESPONSE_OK) { - address = hexstr_to_guint32 (gtk_entry_get_text (gui->flash_dialog_entry), - &err); + address = hexstr_to_guint32 (gtk_entry_get_text (gui->flash_dialog_entry), &err); if (err) { stlink_gui_set_info_error_message (gui, err->message); } else { - if (address > gui->sl->flash_base + gui->sl->flash_size || - address < gui->sl->flash_base) { + if (address > gui->sl->flash_base + gui->sl->flash_size || address < gui->sl->flash_base) { stlink_gui_set_info_error_message (gui, "Invalid address"); - } - else if (address + gui->file_mem.size > - gui->sl->flash_base + gui->sl->flash_size) { + } else if (address + gui->file_mem.size > gui->sl->flash_base + gui->sl->flash_size) { stlink_gui_set_info_error_message (gui, "Binary overwrites flash"); } else { stlink_gui_set_sensitivity (gui, FALSE); - gtk_progress_bar_set_text (gui->progress.bar, - "Writing to flash"); + gtk_progress_bar_set_text (gui->progress.bar, "Writing to flash"); gui->progress.activity_mode = TRUE; gtk_widget_show (GTK_WIDGET (gui->progress.bar)); - g_thread_new ("flash", - (GThreadFunc) stlink_gui_write_flash, gui); + g_thread_new ("flash", (GThreadFunc) stlink_gui_write_flash, gui); } } } } -int export_to_file(const char*filename, const struct mem_t flash_mem) -{ +int export_to_file(const char*filename, const struct mem_t flash_mem) { printf("%s\n", filename); FILE * f=fopen(filename, "w"); - if (f==NULL) + if (f == NULL) return -1; for (gsize i=0;iflash_mem)!=0) + if (export_to_file (filename, gui->flash_mem) != 0) { stlink_gui_set_info_error_message(gui, "Failed to export flash"); - else + } else { stlink_gui_set_info_error_message(gui, "Export successful"); + } g_free (filename); } gtk_widget_destroy (dialog); } -static gboolean -progress_pulse_timeout (STlinkGUI *gui) { +static gboolean progress_pulse_timeout (STlinkGUI *gui) { if (gui->progress.activity_mode) { gtk_progress_bar_pulse (gui->progress.bar); } else { @@ -802,12 +691,11 @@ progress_pulse_timeout (STlinkGUI *gui) { return TRUE; } -static void -notebook_switch_page_cb (GtkNotebook *notebook, - GtkWidget *widget, - guint page_num, - gpointer data) -{ +static void notebook_switch_page_cb ( + GtkNotebook *notebook, + GtkWidget *widget, + guint page_num, + gpointer data) { STlinkGUI *gui; (void) notebook; (void) widget; @@ -815,22 +703,20 @@ notebook_switch_page_cb (GtkNotebook *notebook, gui = STLINK_GUI (data); if (page_num == 1) { - if (gui->filename == NULL) { + if (gui->filename == NULL) stlink_gui_open_file (gui); - } } } -static void -dnd_received_cb (GtkWidget *widget, - GdkDragContext *context, - gint x, - gint y, - GtkSelectionData *selection_data, - guint target_type, - guint timestamp, - gpointer data) -{ +static void dnd_received_cb ( + GtkWidget *widget, + GdkDragContext *context, + gint x, + gint y, + GtkSelectionData *selection_data, + guint target_type, + guint timestamp, + gpointer data) { GFile *file_uri; gchar **file_list; const guchar *file_data; @@ -841,14 +727,12 @@ dnd_received_cb (GtkWidget *widget, (void) x; (void) y; - if (selection_data != NULL && - gtk_selection_data_get_length (selection_data) > 0) { + if (selection_data != NULL && gtk_selection_data_get_length (selection_data) > 0) { switch (target_type) { case TARGET_FILENAME: - if (gui->filename) { + if (gui->filename) g_free (gui->filename); - } file_data = gtk_selection_data_get_data (selection_data); file_list = g_strsplit ((gchar *)file_data, "\r\n", 0); @@ -859,11 +743,9 @@ dnd_received_cb (GtkWidget *widget, g_strfreev (file_list); g_object_unref (file_uri); - store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->devmem_treeview)); - if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) { + if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) gtk_list_store_clear (store); - } stlink_gui_set_sensitivity (gui, FALSE); gtk_notebook_set_current_page (gui->notebook, PAGE_FILEMEM); @@ -873,39 +755,34 @@ dnd_received_cb (GtkWidget *widget, break; } } - gtk_drag_finish (context, - TRUE, - gdk_drag_context_get_suggested_action (context) == GDK_ACTION_MOVE, - timestamp); + gtk_drag_finish ( + context, + TRUE, + gdk_drag_context_get_suggested_action (context) == GDK_ACTION_MOVE, + timestamp); } -void -stlink_gui_init_dnd (STlinkGUI *gui) -{ - GtkTargetEntry target_list[] = { - { "text/uri-list", 0, TARGET_FILENAME }, - }; - - gtk_drag_dest_set(GTK_WIDGET (gui->window), - GTK_DEST_DEFAULT_ALL, - target_list, - G_N_ELEMENTS (target_list), - GDK_ACTION_COPY); - - g_signal_connect (gui->window, "drag-data-received", - G_CALLBACK (dnd_received_cb), gui); +void stlink_gui_init_dnd (STlinkGUI *gui) { + GtkTargetEntry target_list[] = { { "text/uri-list", 0, TARGET_FILENAME }, }; + + gtk_drag_dest_set( + GTK_WIDGET (gui->window), + GTK_DEST_DEFAULT_ALL, + target_list, + G_N_ELEMENTS (target_list), + GDK_ACTION_COPY); + + g_signal_connect (gui->window, "drag-data-received", G_CALLBACK (dnd_received_cb), gui); } -static void -stlink_gui_build_ui (STlinkGUI *gui) { +static void stlink_gui_build_ui (STlinkGUI *gui) { GtkBuilder *builder; GtkListStore *devmem_store; GtkListStore *filemem_store; - gchar *ui_file = STLINK_UI_DIR "/stlink-gui.ui"; + gchar *ui_file = STLINK_UI_DIR "/gui.ui"; - if (!g_file_test (ui_file, G_FILE_TEST_EXISTS)) { - ui_file = "stlink-gui.ui"; - } + if (!g_file_test (ui_file, G_FILE_TEST_EXISTS)) + ui_file = "gui.ui"; builder = gtk_builder_new (); if (!gtk_builder_add_from_file (builder, ui_file, NULL)) { g_printerr ("Failed to load UI file: %s\n", ui_file); @@ -913,37 +790,25 @@ stlink_gui_build_ui (STlinkGUI *gui) { } gui->window = GTK_WINDOW (gtk_builder_get_object (builder, "window")); - g_signal_connect (G_OBJECT (gui->window), "destroy", - G_CALLBACK (gtk_main_quit), NULL); + g_signal_connect (G_OBJECT (gui->window), "destroy", G_CALLBACK (gtk_main_quit), NULL); /* set up toolutton clicked callbacks */ - gui->open_button = - GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "open_button")); - g_signal_connect (G_OBJECT (gui->open_button), "clicked", - G_CALLBACK (open_button_cb), gui); - - gui->connect_button = - GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "connect_button")); - g_signal_connect (G_OBJECT (gui->connect_button), "clicked", - G_CALLBACK (connect_button_cb), gui); - - gui->disconnect_button = - GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "disconnect_button")); - g_signal_connect (G_OBJECT (gui->disconnect_button), "clicked", - G_CALLBACK (disconnect_button_cb), gui); - - gui->flash_button = - GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "flash_button")); - g_signal_connect (G_OBJECT (gui->flash_button), "clicked", - G_CALLBACK (flash_button_cb), gui); - - gui->export_button = - GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "export_button")); - g_signal_connect (G_OBJECT (gui->export_button), "clicked", - G_CALLBACK (export_button_cb), gui); - - gui->devmem_treeview = - GTK_TREE_VIEW (gtk_builder_get_object (builder, "devmem_treeview")); + gui->open_button = GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "open_button")); + g_signal_connect (G_OBJECT (gui->open_button), "clicked", G_CALLBACK (open_button_cb), gui); + + gui->connect_button = GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "connect_button")); + g_signal_connect (G_OBJECT (gui->connect_button), "clicked", G_CALLBACK (connect_button_cb), gui); + + gui->disconnect_button = GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "disconnect_button")); + g_signal_connect (G_OBJECT (gui->disconnect_button), "clicked", G_CALLBACK (disconnect_button_cb), gui); + + gui->flash_button = GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "flash_button")); + g_signal_connect (G_OBJECT (gui->flash_button), "clicked", G_CALLBACK (flash_button_cb), gui); + + gui->export_button = GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "export_button")); + g_signal_connect (G_OBJECT (gui->export_button), "clicked", G_CALLBACK (export_button_cb), gui); + + gui->devmem_treeview = GTK_TREE_VIEW (gtk_builder_get_object (builder, "devmem_treeview")); mem_view_init_headers (gui->devmem_treeview); devmem_store = gtk_list_store_new (5, G_TYPE_STRING, @@ -954,8 +819,7 @@ stlink_gui_build_ui (STlinkGUI *gui) { gtk_tree_view_set_model (gui->devmem_treeview, GTK_TREE_MODEL (devmem_store)); g_object_unref (devmem_store); - gui->filemem_treeview = - GTK_TREE_VIEW (gtk_builder_get_object (builder, "filemem_treeview")); + gui->filemem_treeview = GTK_TREE_VIEW (gtk_builder_get_object (builder, "filemem_treeview")); mem_view_init_headers (gui->filemem_treeview); filemem_store = gtk_list_store_new (5, G_TYPE_STRING, @@ -966,75 +830,43 @@ stlink_gui_build_ui (STlinkGUI *gui) { gtk_tree_view_set_model (gui->filemem_treeview, GTK_TREE_MODEL (filemem_store)); g_object_unref (filemem_store); - gui->core_id_label = - GTK_LABEL (gtk_builder_get_object (builder, "core_id_value")); - - gui->chip_id_label = - GTK_LABEL (gtk_builder_get_object (builder, "chip_id_value")); + gui->core_id_label = GTK_LABEL (gtk_builder_get_object (builder, "core_id_value")); + gui->chip_id_label = GTK_LABEL (gtk_builder_get_object (builder, "chip_id_value")); + gui->flash_size_label = GTK_LABEL (gtk_builder_get_object (builder, "flash_size_value")); + gui->ram_size_label = GTK_LABEL (gtk_builder_get_object (builder, "ram_size_value")); + gui->device_frame = GTK_FRAME (gtk_builder_get_object (builder, "device_frame")); - gui->flash_size_label = - GTK_LABEL (gtk_builder_get_object (builder, "flash_size_value")); + gui->notebook = GTK_NOTEBOOK (gtk_builder_get_object (builder, "mem_notebook")); + g_signal_connect (gui->notebook, "switch-page", G_CALLBACK (notebook_switch_page_cb), gui); - gui->ram_size_label = - GTK_LABEL (gtk_builder_get_object (builder, "ram_size_value")); + gui->devmem_box = GTK_BOX (gtk_builder_get_object (builder, "devmem_box")); + gui->filemem_box = GTK_BOX (gtk_builder_get_object (builder, "filemem_box")); - gui->device_frame = - GTK_FRAME (gtk_builder_get_object (builder, "device_frame")); + gui->devmem_jmp_entry = GTK_ENTRY (gtk_builder_get_object (builder, "devmem_jmp_entry")); + g_signal_connect (gui->devmem_jmp_entry, "activate", G_CALLBACK (devmem_jmp_cb), gui); - gui->notebook = - GTK_NOTEBOOK (gtk_builder_get_object (builder, "mem_notebook")); - g_signal_connect (gui->notebook, "switch-page", - G_CALLBACK (notebook_switch_page_cb), gui); - - gui->devmem_box = - GTK_BOX (gtk_builder_get_object (builder, "devmem_box")); - - gui->filemem_box = - GTK_BOX (gtk_builder_get_object (builder, "filemem_box")); - - gui->devmem_jmp_entry = - GTK_ENTRY (gtk_builder_get_object (builder, "devmem_jmp_entry")); - g_signal_connect (gui->devmem_jmp_entry, "activate", - G_CALLBACK (devmem_jmp_cb), gui); - - gui->filemem_jmp_entry = - GTK_ENTRY (gtk_builder_get_object (builder, "filemem_jmp_entry")); - g_signal_connect (gui->filemem_jmp_entry, "activate", - G_CALLBACK (filemem_jmp_cb), gui); + gui->filemem_jmp_entry = GTK_ENTRY (gtk_builder_get_object (builder, "filemem_jmp_entry")); + g_signal_connect (gui->filemem_jmp_entry, "activate", G_CALLBACK (filemem_jmp_cb), gui); gtk_editable_set_editable (GTK_EDITABLE (gui->filemem_jmp_entry), TRUE); - gui->progress.bar = - GTK_PROGRESS_BAR (gtk_builder_get_object (builder, "progressbar")); + gui->progress.bar = GTK_PROGRESS_BAR (gtk_builder_get_object (builder, "progressbar")); gtk_progress_bar_set_show_text (gui->progress.bar, TRUE); - gui->progress.timer = g_timeout_add (100, - (GSourceFunc) progress_pulse_timeout, - gui); + gui->progress.timer = g_timeout_add (100, (GSourceFunc) progress_pulse_timeout, gui); - gui->statusbar = - GTK_STATUSBAR (gtk_builder_get_object (builder, "statusbar")); + gui->statusbar = GTK_STATUSBAR (gtk_builder_get_object (builder, "statusbar")); - gui->infobar = - GTK_INFO_BAR (gtk_builder_get_object (builder, "infobar")); + gui->infobar = GTK_INFO_BAR (gtk_builder_get_object (builder, "infobar")); gtk_info_bar_add_button (gui->infobar, "_OK", GTK_RESPONSE_OK); gui->infolabel = GTK_LABEL (gtk_label_new ("")); - gtk_container_add (GTK_CONTAINER (gtk_info_bar_get_content_area (gui->infobar)), - GTK_WIDGET (gui->infolabel)); + gtk_container_add (GTK_CONTAINER (gtk_info_bar_get_content_area (gui->infobar)), GTK_WIDGET (gui->infolabel)); g_signal_connect (gui->infobar, "response", G_CALLBACK (gtk_widget_hide), NULL); /* flash dialog */ - gui->flash_dialog = - GTK_DIALOG (gtk_builder_get_object (builder, "flash_dialog")); - g_signal_connect_swapped (gui->flash_dialog, "response", - G_CALLBACK (gtk_widget_hide), gui->flash_dialog); - - gui->flash_dialog_ok = - GTK_BUTTON (gtk_builder_get_object (builder, "flash_dialog_ok_button")); - - gui->flash_dialog_cancel = - GTK_BUTTON (gtk_builder_get_object (builder, "flash_dialog_cancel_button")); - - gui->flash_dialog_entry = - GTK_ENTRY (gtk_builder_get_object (builder, "flash_dialog_entry")); + gui->flash_dialog = GTK_DIALOG (gtk_builder_get_object (builder, "flash_dialog")); + g_signal_connect_swapped (gui->flash_dialog, "response", G_CALLBACK (gtk_widget_hide), gui->flash_dialog); + gui->flash_dialog_ok = GTK_BUTTON (gtk_builder_get_object (builder, "flash_dialog_ok_button")); + gui->flash_dialog_cancel = GTK_BUTTON (gtk_builder_get_object (builder, "flash_dialog_cancel_button")); + gui->flash_dialog_entry = GTK_ENTRY (gtk_builder_get_object (builder, "flash_dialog_entry")); /* make it so */ gtk_widget_show_all (GTK_WIDGET (gui->window)); @@ -1044,9 +876,7 @@ stlink_gui_build_ui (STlinkGUI *gui) { stlink_gui_set_disconnected (gui); } -int -main (int argc, char **argv) -{ +int main (int argc, char **argv) { STlinkGUI *gui; gtk_init (&argc, &argv); @@ -1056,6 +886,5 @@ main (int argc, char **argv) stlink_gui_init_dnd (gui); gtk_main (); - return 0; } diff --git a/src/tools/gui/stlink-gui.h b/src/stlink-gui/gui.h similarity index 98% rename from src/tools/gui/stlink-gui.h rename to src/stlink-gui/gui.h index 30c503fd3..c83e638f6 100644 --- a/src/tools/gui/stlink-gui.h +++ b/src/stlink-gui/gui.h @@ -39,8 +39,7 @@ struct mem_t { guint32 base; }; -struct _STlinkGUI -{ +struct _STlinkGUI { GObject parent_instance; /*< private >*/ @@ -82,8 +81,7 @@ struct _STlinkGUI stlink_t *sl; }; -struct _STlinkGUIClass -{ +struct _STlinkGUIClass { GObjectClass parent_class; /* class members */ diff --git a/src/tools/gui/stlink-gui.ui b/src/stlink-gui/gui.ui similarity index 100% rename from src/tools/gui/stlink-gui.ui rename to src/stlink-gui/gui.ui diff --git a/src/stlink-gui/icons/export-icons.sh b/src/stlink-gui/icons/export-icons.sh new file mode 100644 index 000000000..f36cb5598 --- /dev/null +++ b/src/stlink-gui/icons/export-icons.sh @@ -0,0 +1,40 @@ +#!/bin/sh +# +# create the XPM icon and all resolutions below hicolor as PNG + +APPNAME="stlink-gui" +ORIGIN="stlink-gui_icon.svg" +OUTDIR="hicolor" + +# possible size options are --export-dpi / --export-width / --export-height +OPTS="-z --export-id-only" +ID="scalable-icon" +RESOLUTIONS="16 22 24 32 48 64 128 256" + +if ! [ -d $OUTDIR ]; then + echo "output directory missing. Create it..." + mkdir $OUTDIR + for RES in $RESOLUTIONS; do + mkdir -p $OUTDIR/${RES}x${RES}/apps + done +fi + +# create single app icon +inkscape $OPTS --export-width=32 --export-id=$ID --export-png=$APPNAME.png $ORIGIN +if [ $? != 0 ]; then + exit 1; +fi +convert $APPNAME.png $APPNAME.xpm + +# create all the resolutions +ALL="" +for RES in $RESOLUTIONS; do + inkscape $OPTS --export-width=$RES --export-id=$ID --export-png=$OUTDIR/${RES}x${RES}/apps/$APPNAME.png $ORIGIN + ALL="$ALL $OUTDIR/${RES}x${RES}/apps/$APPNAME.png" +done + +# this is for windows... +#echo "build Windows icon from $ALL" +#convert $ALL $APPNAME.ico + +exit 0 diff --git a/src/tools/gui/art/hicolor/128x128/apps/stlink-gui.png b/src/stlink-gui/icons/hicolor/128x128/apps/stlink-gui.png similarity index 100% rename from src/tools/gui/art/hicolor/128x128/apps/stlink-gui.png rename to src/stlink-gui/icons/hicolor/128x128/apps/stlink-gui.png diff --git a/src/tools/gui/art/hicolor/16x16/apps/stlink-gui.png b/src/stlink-gui/icons/hicolor/16x16/apps/stlink-gui.png similarity index 100% rename from src/tools/gui/art/hicolor/16x16/apps/stlink-gui.png rename to src/stlink-gui/icons/hicolor/16x16/apps/stlink-gui.png diff --git a/src/tools/gui/art/hicolor/22x22/apps/stlink-gui.png b/src/stlink-gui/icons/hicolor/22x22/apps/stlink-gui.png similarity index 100% rename from src/tools/gui/art/hicolor/22x22/apps/stlink-gui.png rename to src/stlink-gui/icons/hicolor/22x22/apps/stlink-gui.png diff --git a/src/tools/gui/art/hicolor/24x24/apps/stlink-gui.png b/src/stlink-gui/icons/hicolor/24x24/apps/stlink-gui.png similarity index 100% rename from src/tools/gui/art/hicolor/24x24/apps/stlink-gui.png rename to src/stlink-gui/icons/hicolor/24x24/apps/stlink-gui.png diff --git a/src/tools/gui/art/hicolor/256x256/apps/stlink-gui.png b/src/stlink-gui/icons/hicolor/256x256/apps/stlink-gui.png similarity index 100% rename from src/tools/gui/art/hicolor/256x256/apps/stlink-gui.png rename to src/stlink-gui/icons/hicolor/256x256/apps/stlink-gui.png diff --git a/src/tools/gui/art/hicolor/32x32/apps/stlink-gui.png b/src/stlink-gui/icons/hicolor/32x32/apps/stlink-gui.png similarity index 100% rename from src/tools/gui/art/hicolor/32x32/apps/stlink-gui.png rename to src/stlink-gui/icons/hicolor/32x32/apps/stlink-gui.png diff --git a/src/tools/gui/art/hicolor/48x48/apps/stlink-gui.png b/src/stlink-gui/icons/hicolor/48x48/apps/stlink-gui.png similarity index 100% rename from src/tools/gui/art/hicolor/48x48/apps/stlink-gui.png rename to src/stlink-gui/icons/hicolor/48x48/apps/stlink-gui.png diff --git a/src/tools/gui/art/hicolor/64x64/apps/stlink-gui.png b/src/stlink-gui/icons/hicolor/64x64/apps/stlink-gui.png similarity index 100% rename from src/tools/gui/art/hicolor/64x64/apps/stlink-gui.png rename to src/stlink-gui/icons/hicolor/64x64/apps/stlink-gui.png diff --git a/src/tools/gui/art/stlink-gui.png b/src/stlink-gui/icons/stlink-gui.png similarity index 100% rename from src/tools/gui/art/stlink-gui.png rename to src/stlink-gui/icons/stlink-gui.png diff --git a/src/tools/gui/art/stlink-gui.svg b/src/stlink-gui/icons/stlink-gui.svg similarity index 100% rename from src/tools/gui/art/stlink-gui.svg rename to src/stlink-gui/icons/stlink-gui.svg diff --git a/src/tools/gui/art/stlink-gui.xpm b/src/stlink-gui/icons/stlink-gui.xpm similarity index 100% rename from src/tools/gui/art/stlink-gui.xpm rename to src/stlink-gui/icons/stlink-gui.xpm diff --git a/src/tools/gui/art/stlink-gui_48.png b/src/stlink-gui/icons/stlink-gui_48.png similarity index 100% rename from src/tools/gui/art/stlink-gui_48.png rename to src/stlink-gui/icons/stlink-gui_48.png diff --git a/src/tools/gui/stlink-gui.desktop b/src/stlink-gui/stlink-gui.desktop similarity index 100% rename from src/tools/gui/stlink-gui.desktop rename to src/stlink-gui/stlink-gui.desktop diff --git a/src/tools/gui/art/export-icons.sh b/src/tools/gui/art/export-icons.sh deleted file mode 100755 index 9d61719b9..000000000 --- a/src/tools/gui/art/export-icons.sh +++ /dev/null @@ -1,38 +0,0 @@ -#!/bin/sh -# -# create the XPM icon and all resolutions below hicolor as PNG - -APPNAME="stlink-gui" -ORIGIN="stlink-gui_icon.svg" -OUTDIR="hicolor" - -## possible size options are --export-dpi / --export-width / --export-height -OPTS="-z --export-id-only" -ID="scalable-icon" -RESOLUTIONS="16 22 24 32 48 64 128 256" - - if ! [ -d $OUTDIR ]; then - echo "output directory missing. Create it..." - mkdir $OUTDIR - for RES in $RESOLUTIONS; do - mkdir -p $OUTDIR/${RES}x${RES}/apps - done - fi - - # create single app icon - inkscape $OPTS --export-width=32 --export-id=$ID --export-png=$APPNAME.png $ORIGIN - if [ $? != 0 ]; then exit 1; fi - convert $APPNAME.png $APPNAME.xpm - - # create all the resolutions - ALL="" - for RES in $RESOLUTIONS; do - inkscape $OPTS --export-width=$RES --export-id=$ID --export-png=$OUTDIR/${RES}x${RES}/apps/$APPNAME.png $ORIGIN - ALL="$ALL $OUTDIR/${RES}x${RES}/apps/$APPNAME.png" - done - - # this is for windows... - #echo "build Windows icon from $ALL" - #convert $ALL $APPNAME.ico - -exit 0 From c2c480846a493ae5493a5aecda41ad53f0b83bb2 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 17 Apr 2020 00:37:03 +0200 Subject: [PATCH 0832/1435] Project cleanup - Updated old project references - Alligned code style in /tests - Added note on OS support to README.md --- CHANGELOG.md | 272 +++++++++++++++++++++++------------------------ LICENSE.md | 2 +- README.md | 30 +++--- debian/control | 8 +- debian/copyright | 4 +- debian/watch | 2 +- tests/flash.c | 154 ++++++++++++++++++++------- tests/sg.c | 67 ++++++------ tests/usb.c | 19 ++-- 9 files changed, 319 insertions(+), 239 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 99d307f9a..8cf102910 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -8,44 +8,44 @@ Release date: 2020-02-20 Major changes and added features: -* Initial support for STM32L41X ([#754](https://github.com/texane/stlink/pull/754), [#799](https://github.com/texane/stlink/pull/799)) -* Working support for CKS32F103C8T6 and related CKS devices with Core-ID 0x2ba01477 ([#756](https://github.com/texane/stlink/pull/756), [#757](https://github.com/texane/stlink/pull/757), [#805](https://github.com/texane/stlink/pull/805), [#834](https://github.com/texane/stlink/pull/834), Regression-Fixes: [#761](https://github.com/texane/stlink/pull/761), [#766](https://github.com/texane/stlink/pull/766)) -* Added preliminary support for some STM32G0 chips ([#759](https://github.com/texane/stlink/pull/759), [#760](https://github.com/texane/stlink/pull/760), [#797](https://github.com/texane/stlink/pull/797)) -* Added support for mass erasing second bank on STM32F10x_XL ([#767](https://github.com/texane/stlink/pull/767), [#768](https://github.com/texane/stlink/pull/768)) -* Added call to clear PG bit after writing to flash ([#773](https://github.com/texane/stlink/pull/773)) -* Added support to write option bytes for the STM32G0 ([#778](https://github.com/texane/stlink/pull/778)) -* Added support for STM32WB55 chips ([#786](https://github.com/texane/stlink/pull/786), [#810](https://github.com/texane/stlink/pull/810), [#816](https://github.com/texane/stlink/pull/816)) -* Added STLink V3SET VID:PIDs to the udev rules ([#789](https://github.com/texane/stlink/pull/789)) -* Support for "STM32+Audio" v2-1 firmware ([#790](https://github.com/texane/stlink/pull/790)) -* Build for Windows under Debian/Ubuntu ([#802](https://github.com/texane/stlink/pull/802)) -* Allow for 64 bytes serials ([#809](https://github.com/texane/stlink/pull/809)) -* Added full support for STLINK CHIP ID L4RX ([#814](https://github.com/texane/stlink/pull/814), [#839](https://github.com/texane/stlink/pull/839)) -* Added support for the STLink-v2.1 when flashed with no mass storage (PID 0x3752) ([#819](https://github.com/texane/stlink/pull/819), [#861](https://github.com/texane/stlink/pull/861)) -* Added support for writing option bytes on STM32L0xx ([#830](https://github.com/texane/stlink/pull/830)) -* Added support to read and write option bytes for STM32F2 series ([#836](https://github.com/texane/stlink/pull/836), [#837](https://github.com/texane/stlink/pull/837)) -* Added support to read and write option bytes for STM32F446 ([#843](https://github.com/texane/stlink/pull/843)) +* Initial support for STM32L41X ([#754](https://github.com/stlink-org/stlink/pull/754), [#799](https://github.com/stlink-org/stlink/pull/799)) +* Working support for CKS32F103C8T6 and related CKS devices with Core-ID 0x2ba01477 ([#756](https://github.com/stlink-org/stlink/pull/756), [#757](https://github.com/stlink-org/stlink/pull/757), [#805](https://github.com/stlink-org/stlink/pull/805), [#834](https://github.com/stlink-org/stlink/pull/834), Regression-Fixes: [#761](https://github.com/stlink-org/stlink/pull/761), [#766](https://github.com/stlink-org/stlink/pull/766)) +* Added preliminary support for some STM32G0 chips ([#759](https://github.com/stlink-org/stlink/pull/759), [#760](https://github.com/stlink-org/stlink/pull/760), [#797](https://github.com/stlink-org/stlink/pull/797)) +* Added support for mass erasing second bank on STM32F10x_XL ([#767](https://github.com/stlink-org/stlink/pull/767), [#768](https://github.com/stlink-org/stlink/pull/768)) +* Added call to clear PG bit after writing to flash ([#773](https://github.com/stlink-org/stlink/pull/773)) +* Added support to write option bytes for the STM32G0 ([#778](https://github.com/stlink-org/stlink/pull/778)) +* Added support for STM32WB55 chips ([#786](https://github.com/stlink-org/stlink/pull/786), [#810](https://github.com/stlink-org/stlink/pull/810), [#816](https://github.com/stlink-org/stlink/pull/816)) +* Added STLink V3SET VID:PIDs to the udev rules ([#789](https://github.com/stlink-org/stlink/pull/789)) +* Support for "STM32+Audio" v2-1 firmware ([#790](https://github.com/stlink-org/stlink/pull/790)) +* Build for Windows under Debian/Ubuntu ([#802](https://github.com/stlink-org/stlink/pull/802)) +* Allow for 64 bytes serials ([#809](https://github.com/stlink-org/stlink/pull/809)) +* Added full support for STLINK CHIP ID L4RX ([#814](https://github.com/stlink-org/stlink/pull/814), [#839](https://github.com/stlink-org/stlink/pull/839)) +* Added support for the STLink-v2.1 when flashed with no mass storage (PID 0x3752) ([#819](https://github.com/stlink-org/stlink/pull/819), [#861](https://github.com/stlink-org/stlink/pull/861)) +* Added support for writing option bytes on STM32L0xx ([#830](https://github.com/stlink-org/stlink/pull/830)) +* Added support to read and write option bytes for STM32F2 series ([#836](https://github.com/stlink-org/stlink/pull/836), [#837](https://github.com/stlink-org/stlink/pull/837)) +* Added support to read and write option bytes for STM32F446 ([#843](https://github.com/stlink-org/stlink/pull/843)) Updates and fixes: -* Fixed "unkown chip id", piped output and st-util -v ([#107](https://github.com/texane/stlink/pull/107), [#665](https://github.com/texane/stlink/pull/665), [#763](https://github.com/texane/stlink/pull/763)) -* Fixed an issue with versioning stuck at 1.4.0 for versions cloned with git ([#563](https://github.com/texane/stlink/pull/563), [#762](https://github.com/texane/stlink/pull/762), [#772](https://github.com/texane/stlink/pull/772)) -* Updated STM32F3xx chip ID that covers a few different devices ([#685](https://github.com/texane/stlink/pull/685), [#758](https://github.com/texane/stlink/pull/758)) -* Made udev rules and modprobe conf installation optional ([#741](https://github.com/texane/stlink/pull/741)) -* Fixed case when __FILE__ don't contain "/" nor "\\" ([#745](https://github.com/texane/stlink/pull/745)) -* Fixed double dash issue in doc/man ([#746](https://github.com/texane/stlink/pull/746), [#747](https://github.com/texane/stlink/pull/747)) -* Compiling documentation: package is called libusb-1.0-0-dev on Debian ([#748](https://github.com/texane/stlink/pull/748)) -* Only do bank calculation on STM32L4 devices with dual banked flash / Added chip-ID 0x464 for STM32L41xxx/L42xxx devices ([#751](https://github.com/texane/stlink/pull/751)) -* Added O_BINARY option to open file ([#753](https://github.com/texane/stlink/pull/753)) -* Fixed versioning when compiling from the checked out git-repo ([#762](https://github.com/texane/stlink/pull/762), [#772](https://github.com/texane/stlink/pull/772)) -* win32: move usleep definition to unistd.h ([#765](https://github.com/texane/stlink/pull/765)) -* Fixed relative path to the UI files needed by stlink-gui-local (GUI) ([#770](https://github.com/texane/stlink/pull/770), [#771](https://github.com/texane/stlink/pull/771)) -* Added howto for sending NRST signal through GDB ([#774](https://github.com/texane/stlink/pull/774), [#776](https://github.com/texane/stlink/pull/776), [#779](https://github.com/texane/stlink/pull/779)) -* Fixed package name "devscripts" in doc/compiling.md ([#775](https://github.com/texane/stlink/pull/775)) -* Fixed few potential memory/resource leaks ([#803](https://github.com/texane/stlink/pull/803)) -* Updated Linux source repositories in README.md: Debian and Ubuntu ([#821](https://github.com/texane/stlink/pull/821), [#835](https://github.com/texane/stlink/pull/835), [#859](https://github.com/texane/stlink/pull/859)) -* Do not issue JTAG reset on stlink-v1 ([#828](https://github.com/texane/stlink/pull/828)) -* Fixed flash size of STM32 Discovery vl ([#829](https://github.com/texane/stlink/pull/829)) -* Updated documentation on software structure ([#851](https://github.com/texane/stlink/pull/851)) +* Fixed "unkown chip id", piped output and st-util -v ([#107](https://github.com/stlink-org/stlink/pull/107), [#665](https://github.com/stlink-org/stlink/pull/665), [#763](https://github.com/stlink-org/stlink/pull/763)) +* Fixed an issue with versioning stuck at 1.4.0 for versions cloned with git ([#563](https://github.com/stlink-org/stlink/pull/563), [#762](https://github.com/stlink-org/stlink/pull/762), [#772](https://github.com/stlink-org/stlink/pull/772)) +* Updated STM32F3xx chip ID that covers a few different devices ([#685](https://github.com/stlink-org/stlink/pull/685), [#758](https://github.com/stlink-org/stlink/pull/758)) +* Made udev rules and modprobe conf installation optional ([#741](https://github.com/stlink-org/stlink/pull/741)) +* Fixed case when __FILE__ don't contain "/" nor "\\" ([#745](https://github.com/stlink-org/stlink/pull/745)) +* Fixed double dash issue in doc/man ([#746](https://github.com/stlink-org/stlink/pull/746), [#747](https://github.com/stlink-org/stlink/pull/747)) +* Compiling documentation: package is called libusb-1.0-0-dev on Debian ([#748](https://github.com/stlink-org/stlink/pull/748)) +* Only do bank calculation on STM32L4 devices with dual banked flash / Added chip-ID 0x464 for STM32L41xxx/L42xxx devices ([#751](https://github.com/stlink-org/stlink/pull/751)) +* Added O_BINARY option to open file ([#753](https://github.com/stlink-org/stlink/pull/753)) +* Fixed versioning when compiling from the checked out git-repo ([#762](https://github.com/stlink-org/stlink/pull/762), [#772](https://github.com/stlink-org/stlink/pull/772)) +* win32: move usleep definition to unistd.h ([#765](https://github.com/stlink-org/stlink/pull/765)) +* Fixed relative path to the UI files needed by stlink-gui-local (GUI) ([#770](https://github.com/stlink-org/stlink/pull/770), [#771](https://github.com/stlink-org/stlink/pull/771)) +* Added howto for sending NRST signal through GDB ([#774](https://github.com/stlink-org/stlink/pull/774), [#776](https://github.com/stlink-org/stlink/pull/776), [#779](https://github.com/stlink-org/stlink/pull/779)) +* Fixed package name "devscripts" in doc/compiling.md ([#775](https://github.com/stlink-org/stlink/pull/775)) +* Fixed few potential memory/resource leaks ([#803](https://github.com/stlink-org/stlink/pull/803)) +* Updated Linux source repositories in README.md: Debian and Ubuntu ([#821](https://github.com/stlink-org/stlink/pull/821), [#835](https://github.com/stlink-org/stlink/pull/835), [#859](https://github.com/stlink-org/stlink/pull/859)) +* Do not issue JTAG reset on stlink-v1 ([#828](https://github.com/stlink-org/stlink/pull/828)) +* Fixed flash size of STM32 Discovery vl ([#829](https://github.com/stlink-org/stlink/pull/829)) +* Updated documentation on software structure ([#851](https://github.com/stlink-org/stlink/pull/851)) General project updates: @@ -62,32 +62,32 @@ Release date: 2018-09-13 Major changes and added features: -* Added reset through AIRCR ([#540](https://github.com/texane/stlink/pull/540), [#712](https://github.com/texane/stlink/pull/712)) -* Added creation of icons for .desktop file ([#684](https://github.com/texane/stlink/pull/684), [#708](https://github.com/texane/stlink/pull/708)) -* Added desktop file for linux ([#688](https://github.com/texane/stlink/pull/688)) -* Added button to export STM32 flash memory to a file ([#691](https://github.com/texane/stlink/pull/691)) -* Updated libusb to 1.0.22 ([#695](https://github.com/texane/stlink/pull/695)) - (related Bugs: [#438](https://github.com/texane/stlink/pull/438), [#632](https://github.com/texane/stlink/pull/632)) -* Added icons for STLink GUI ([#697](https://github.com/texane/stlink/pull/697)) -* Added support for STM32L4R9 target ([#694](https://github.com/texane/stlink/pull/694), [#699](https://github.com/texane/stlink/pull/699)) -* Added memory map for STM32F411RE target ([#709](https://github.com/texane/stlink/pull/709)) -* Implemented intel hex support for GTK GUI ([#713](https://github.com/texane/stlink/pull/713), [#718](https://github.com/texane/stlink/pull/718)) +* Added reset through AIRCR ([#540](https://github.com/stlink-org/stlink/pull/540), [#712](https://github.com/stlink-org/stlink/pull/712)) +* Added creation of icons for .desktop file ([#684](https://github.com/stlink-org/stlink/pull/684), [#708](https://github.com/stlink-org/stlink/pull/708)) +* Added desktop file for linux ([#688](https://github.com/stlink-org/stlink/pull/688)) +* Added button to export STM32 flash memory to a file ([#691](https://github.com/stlink-org/stlink/pull/691)) +* Updated libusb to 1.0.22 ([#695](https://github.com/stlink-org/stlink/pull/695)) - (related Bugs: [#438](https://github.com/stlink-org/stlink/pull/438), [#632](https://github.com/stlink-org/stlink/pull/632)) +* Added icons for STLink GUI ([#697](https://github.com/stlink-org/stlink/pull/697)) +* Added support for STM32L4R9 target ([#694](https://github.com/stlink-org/stlink/pull/694), [#699](https://github.com/stlink-org/stlink/pull/699)) +* Added memory map for STM32F411RE target ([#709](https://github.com/stlink-org/stlink/pull/709)) +* Implemented intel hex support for GTK GUI ([#713](https://github.com/stlink-org/stlink/pull/713), [#718](https://github.com/stlink-org/stlink/pull/718)) Updates and fixes: -* Fixed missing flash_loader for STM32L0x ([#269](https://github.com/texane/stlink/pull/269), [#274](https://github.com/texane/stlink/pull/274), [#654](https://github.com/texane/stlink/pull/654), [#675](https://github.com/texane/stlink/pull/675)) -* Fix for stlink library calls exit() or _exit() ([#634](https://github.com/texane/stlink/pull/634), [#696](https://github.com/texane/stlink/pull/696)) -* Added semihosting parameter documentation in doc/man ([#674](https://github.com/texane/stlink/pull/674)) -* Fixed reference to non-exisiting st-term tool in doc/man ([#676](https://github.com/texane/stlink/pull/676)) -* Fixed serial number size mismatch with stlink_open_usb() ([#680](https://github.com/texane/stlink/pull/680)) -* Debian packaging, CMake and README.md fixes ([#682](https://github.com/texane/stlink/pull/682), [#683](https://github.com/texane/stlink/pull/683)) -* Disabled static library installation by default ([#702](https://github.com/texane/stlink/pull/702)) -* Fix for libusb deprecation ([#703](https://github.com/texane/stlink/pull/703), [#704](https://github.com/texane/stlink/pull/704)) -* Renamed STLINK_CHIPID_STM32_L4R9 to STLINK_CHIPID_STM32_L4RX ([#706](https://github.com/texane/stlink/pull/706)) -* Regression: stlink installation under Linux (Debian 9) is broken since #695 ([#700](https://github.com/texane/stlink/pull/700), [#701](https://github.com/texane/stlink/pull/701), [#707](https://github.com/texane/stlink/pull/707)) -* Fixed flash memory map for STM32F72xxx target ([#711](https://github.com/texane/stlink/pull/711)) -* Proper flash page size calculation for STM32F412xx target ([#721](https://github.com/texane/stlink/pull/721)) -* Return correct value on EOF for Semihosting SYS_READ ([#726](https://github.com/texane/stlink/pull/726), [#727](https://github.com/texane/stlink/pull/727), [#728](https://github.com/texane/stlink/pull/728), [#729](https://github.com/texane/stlink/pull/729), [#730](https://github.com/texane/stlink/pull/730), [#731](https://github.com/texane/stlink/pull/731), [#732](https://github.com/texane/stlink/pull/732)) -* FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION ([#733](https://github.com/texane/stlink/pull/733)) +* Fixed missing flash_loader for STM32L0x ([#269](https://github.com/stlink-org/stlink/pull/269), [#274](https://github.com/stlink-org/stlink/pull/274), [#654](https://github.com/stlink-org/stlink/pull/654), [#675](https://github.com/stlink-org/stlink/pull/675)) +* Fix for stlink library calls exit() or _exit() ([#634](https://github.com/stlink-org/stlink/pull/634), [#696](https://github.com/stlink-org/stlink/pull/696)) +* Added semihosting parameter documentation in doc/man ([#674](https://github.com/stlink-org/stlink/pull/674)) +* Fixed reference to non-exisiting st-term tool in doc/man ([#676](https://github.com/stlink-org/stlink/pull/676)) +* Fixed serial number size mismatch with stlink_open_usb() ([#680](https://github.com/stlink-org/stlink/pull/680)) +* Debian packaging, CMake and README.md fixes ([#682](https://github.com/stlink-org/stlink/pull/682), [#683](https://github.com/stlink-org/stlink/pull/683)) +* Disabled static library installation by default ([#702](https://github.com/stlink-org/stlink/pull/702)) +* Fix for libusb deprecation ([#703](https://github.com/stlink-org/stlink/pull/703), [#704](https://github.com/stlink-org/stlink/pull/704)) +* Renamed STLINK_CHIPID_STM32_L4R9 to STLINK_CHIPID_STM32_L4RX ([#706](https://github.com/stlink-org/stlink/pull/706)) +* Regression: stlink installation under Linux (Debian 9) is broken since #695 ([#700](https://github.com/stlink-org/stlink/pull/700), [#701](https://github.com/stlink-org/stlink/pull/701), [#707](https://github.com/stlink-org/stlink/pull/707)) +* Fixed flash memory map for STM32F72xxx target ([#711](https://github.com/stlink-org/stlink/pull/711)) +* Proper flash page size calculation for STM32F412xx target ([#721](https://github.com/stlink-org/stlink/pull/721)) +* Return correct value on EOF for Semihosting SYS_READ ([#726](https://github.com/stlink-org/stlink/pull/726), [#727](https://github.com/stlink-org/stlink/pull/727), [#728](https://github.com/stlink-org/stlink/pull/728), [#729](https://github.com/stlink-org/stlink/pull/729), [#730](https://github.com/stlink-org/stlink/pull/730), [#731](https://github.com/stlink-org/stlink/pull/731), [#732](https://github.com/stlink-org/stlink/pull/732)) +* FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION ([#733](https://github.com/stlink-org/stlink/pull/733)) v1.5.0 @@ -97,21 +97,21 @@ Release date: 2018-02-16 Major changes and added features: -* Added support of STM32L496xx/4A6xx devices ([#615](https://github.com/texane/stlink/pull/615), [#657](https://github.com/texane/stlink/pull/657)) -* Added unknown chip dummy to obtain the serial of the ST-link by a call to st-info --probe ([#641](https://github.com/texane/stlink/pull/641)) -* Added support for STM32F72xx (chip-ID: 0x452) devices (commit [#1969148](https://github.com/texane/stlink/commit/19691485359afef1a256964afcbb8dcf4b733209)) +* Added support of STM32L496xx/4A6xx devices ([#615](https://github.com/stlink-org/stlink/pull/615), [#657](https://github.com/stlink-org/stlink/pull/657)) +* Added unknown chip dummy to obtain the serial of the ST-link by a call to st-info --probe ([#641](https://github.com/stlink-org/stlink/pull/641)) +* Added support for STM32F72xx (chip-ID: 0x452) devices (commit [#1969148](https://github.com/stlink-org/stlink/commit/19691485359afef1a256964afcbb8dcf4b733209)) Updates and fixes: -* Fixed verification of flash error for STM32L496x device ([#617](https://github.com/texane/stlink/pull/617), [#618](https://github.com/texane/stlink/pull/618)) -* Updated Linux source repositories in README.md: Gentoo, Fedora and RedHat/CentOS ([#622](https://github.com/texane/stlink/pull/622), [#635](https://github.com/texane/stlink/pull/635)) -* Updated changelog in debian package ([#630](https://github.com/texane/stlink/pull/630)) -* Added LIB_INSTALL_DIR to correct libs install on 64-bit systems ([#633](https://github.com/texane/stlink/pull/633), [#636](https://github.com/texane/stlink/pull/636)) -* Fixed write for microcontroller with RAM size less or equal to 32K ([#637](https://github.com/texane/stlink/pull/637)) -* Fixed memory map for STM32L496xx boards ([#639](https://github.com/texane/stlink/pull/639)) -* Fixed __FILE__ base name extraction ([#624](https://github.com/texane/stlink/pull/624), [#628](https://github.com/texane/stlink/pull/628), [#648](https://github.com/texane/stlink/pull/648)) -* Added debian/triggers to run ldconfig ([#664](https://github.com/texane/stlink/pull/664)) -* Fixed build on Fedora with GCC 8 ([#666](https://github.com/texane/stlink/pull/666), [#667](https://github.com/texane/stlink/pull/667), [#668](https://github.com/texane/stlink/pull/668)) +* Fixed verification of flash error for STM32L496x device ([#617](https://github.com/stlink-org/stlink/pull/617), [#618](https://github.com/stlink-org/stlink/pull/618)) +* Updated Linux source repositories in README.md: Gentoo, Fedora and RedHat/CentOS ([#622](https://github.com/stlink-org/stlink/pull/622), [#635](https://github.com/stlink-org/stlink/pull/635)) +* Updated changelog in debian package ([#630](https://github.com/stlink-org/stlink/pull/630)) +* Added LIB_INSTALL_DIR to correct libs install on 64-bit systems ([#633](https://github.com/stlink-org/stlink/pull/633), [#636](https://github.com/stlink-org/stlink/pull/636)) +* Fixed write for microcontroller with RAM size less or equal to 32K ([#637](https://github.com/stlink-org/stlink/pull/637)) +* Fixed memory map for STM32L496xx boards ([#639](https://github.com/stlink-org/stlink/pull/639)) +* Fixed __FILE__ base name extraction ([#624](https://github.com/stlink-org/stlink/pull/624), [#628](https://github.com/stlink-org/stlink/pull/628), [#648](https://github.com/stlink-org/stlink/pull/648)) +* Added debian/triggers to run ldconfig ([#664](https://github.com/stlink-org/stlink/pull/664)) +* Fixed build on Fedora with GCC 8 ([#666](https://github.com/stlink-org/stlink/pull/666), [#667](https://github.com/stlink-org/stlink/pull/667), [#668](https://github.com/stlink-org/stlink/pull/668)) v1.4.0 @@ -121,27 +121,27 @@ Release date: 2017-07-01 Major changes and added features: -* Allow building of debian package with CPack ([#554](https://github.com/texane/stlink/pull/554), commit [#5b69f25](https://github.com/texane/stlink/commit/5b69f25198a1a8f34e2ee48d1ad20f79447e3d55)) -* Added support for STM32L011 target ([#564](https://github.com/texane/stlink/pull/564), [#565](https://github.com/texane/stlink/pull/565), [#572](https://github.com/texane/stlink/pull/572)) -* Added support for flashing second bank on STM32F10x_XL ([#592](https://github.com/texane/stlink/pull/592)) -* Initial support to compile with Microsoft Visual Studio 2017 ([#602](https://github.com/texane/stlink/pull/602)) -* Added support for STM32L452 target ([#603](https://github.com/texane/stlink/pull/603), [#608](https://github.com/texane/stlink/pull/608)) +* Allow building of debian package with CPack ([#554](https://github.com/stlink-org/stlink/pull/554), commit [#5b69f25](https://github.com/stlink-org/stlink/commit/5b69f25198a1a8f34e2ee48d1ad20f79447e3d55)) +* Added support for STM32L011 target ([#564](https://github.com/stlink-org/stlink/pull/564), [#565](https://github.com/stlink-org/stlink/pull/565), [#572](https://github.com/stlink-org/stlink/pull/572)) +* Added support for flashing second bank on STM32F10x_XL ([#592](https://github.com/stlink-org/stlink/pull/592)) +* Initial support to compile with Microsoft Visual Studio 2017 ([#602](https://github.com/stlink-org/stlink/pull/602)) +* Added support for STM32L452 target ([#603](https://github.com/stlink-org/stlink/pull/603), [#608](https://github.com/stlink-org/stlink/pull/608)) Updates and fixes: -* Fixed gdb-server: STM32L0xx has no FP_CTRL register for breakpoints ([#273](https://github.com/texane/stlink/pull/273)) -* Added --flash=n[k][m] command line option to override device model ([#305](https://github.com/texane/stlink/pull/305), [#516](https://github.com/texane/stlink/pull/516), [#576](https://github.com/texane/stlink/pull/576)) -* Updated libusb to 1.0.21 for Windows ([#562](https://github.com/texane/stlink/pull/562)) -* Fixed low-voltage flashing on STM32F7 devices ([#566](https://github.com/texane/stlink/pull/566), [#567](https://github.com/texane/stlink/pull/567)) -* Fixed building with mingw64 ([#569](https://github.com/texane/stlink/pull/569), [#573](https://github.com/texane/stlink/pull/573), [#578](https://github.com/texane/stlink/pull/578), [#582](https://github.com/texane/stlink/pull/582), [#584](https://github.com/texane/stlink/pull/584), [#610](https://github.com/texane/stlink/pull/610), [#846](https://github.com/texane/stlink/pull/846)) -* Fixed possible memory leak ([#570](https://github.com/texane/stlink/pull/570), [#571](https://github.com/texane/stlink/pull/571)) -* Fixed installation path for shared objects ([#581](https://github.com/texane/stlink/pull/581)) -* Fixed a few -Wformat warnings ([#582](https://github.com/texane/stlink/pull/582)) -* Removed unused defines in mimgw.h ([#583](https://github.com/texane/stlink/pull/583)) -* Skip GTK detection when cross-compiling ([#588](https://github.com/texane/stlink/pull/588)) -* Fixed compilation with GCC 7 ([#590](https://github.com/texane/stlink/pull/590), [#591](https://github.com/texane/stlink/pull/591)) -* Fixed flashing to 'f0 device' targets ([#594](https://github.com/texane/stlink/pull/594), [#595](https://github.com/texane/stlink/pull/595)) -* Fixed wrong counting when flashing ([#605](https://github.com/texane/stlink/pull/605)) +* Fixed gdb-server: STM32L0xx has no FP_CTRL register for breakpoints ([#273](https://github.com/stlink-org/stlink/pull/273)) +* Added --flash=n[k][m] command line option to override device model ([#305](https://github.com/stlink-org/stlink/pull/305), [#516](https://github.com/stlink-org/stlink/pull/516), [#576](https://github.com/stlink-org/stlink/pull/576)) +* Updated libusb to 1.0.21 for Windows ([#562](https://github.com/stlink-org/stlink/pull/562)) +* Fixed low-voltage flashing on STM32F7 devices ([#566](https://github.com/stlink-org/stlink/pull/566), [#567](https://github.com/stlink-org/stlink/pull/567)) +* Fixed building with mingw64 ([#569](https://github.com/stlink-org/stlink/pull/569), [#573](https://github.com/stlink-org/stlink/pull/573), [#578](https://github.com/stlink-org/stlink/pull/578), [#582](https://github.com/stlink-org/stlink/pull/582), [#584](https://github.com/stlink-org/stlink/pull/584), [#610](https://github.com/stlink-org/stlink/pull/610), [#846](https://github.com/stlink-org/stlink/pull/846)) +* Fixed possible memory leak ([#570](https://github.com/stlink-org/stlink/pull/570), [#571](https://github.com/stlink-org/stlink/pull/571)) +* Fixed installation path for shared objects ([#581](https://github.com/stlink-org/stlink/pull/581)) +* Fixed a few -Wformat warnings ([#582](https://github.com/stlink-org/stlink/pull/582)) +* Removed unused defines in mimgw.h ([#583](https://github.com/stlink-org/stlink/pull/583)) +* Skip GTK detection when cross-compiling ([#588](https://github.com/stlink-org/stlink/pull/588)) +* Fixed compilation with GCC 7 ([#590](https://github.com/stlink-org/stlink/pull/590), [#591](https://github.com/stlink-org/stlink/pull/591)) +* Fixed flashing to 'f0 device' targets ([#594](https://github.com/stlink-org/stlink/pull/594), [#595](https://github.com/stlink-org/stlink/pull/595)) +* Fixed wrong counting when flashing ([#605](https://github.com/stlink-org/stlink/pull/605)) v1.3.1 @@ -151,18 +151,18 @@ Release date: 2017-02-25 Major changes and added features: -* Added support for Semihosting `SYS_READC` ([#546](https://github.com/texane/stlink/pull/546)) -* Added support for STM32F413 ([#549](https://github.com/texane/stlink/pull/549), [#550](https://github.com/texane/stlink/pull/550), [#758](https://github.com/texane/stlink/pull/758)) -* Added preliminary support for STM32L011 to see it after probe (chip-ID 0x457) ([#558](https://github.com/texane/stlink/pull/558), [#598](https://github.com/texane/stlink/pull/598)) +* Added support for Semihosting `SYS_READC` ([#546](https://github.com/stlink-org/stlink/pull/546)) +* Added support for STM32F413 ([#549](https://github.com/stlink-org/stlink/pull/549), [#550](https://github.com/stlink-org/stlink/pull/550), [#758](https://github.com/stlink-org/stlink/pull/758)) +* Added preliminary support for STM32L011 to see it after probe (chip-ID 0x457) ([#558](https://github.com/stlink-org/stlink/pull/558), [#598](https://github.com/stlink-org/stlink/pull/598)) Updates and fixes: * cmake/CPackConfig.cmake: Fixup OSX zip filename * Updated source repositories in README.md: Windows, macOS, Alpine Linux -* Compilation fixes ([#547](https://github.com/texane/stlink/pull/547), [#551](https://github.com/texane/stlink/pull/551), [#552](https://github.com/texane/stlink/pull/552)) -* Stripped full paths to source files in log ([#548](https://github.com/texane/stlink/pull/548)) -* Fixed incorrect release folder name in docs ([#560](https://github.com/texane/stlink/pull/560)) -* Fixed compilation when path includes spaces ([#561](https://github.com/texane/stlink/pull/561)) +* Compilation fixes ([#547](https://github.com/stlink-org/stlink/pull/547), [#551](https://github.com/stlink-org/stlink/pull/551), [#552](https://github.com/stlink-org/stlink/pull/552)) +* Stripped full paths to source files in log ([#548](https://github.com/stlink-org/stlink/pull/548)) +* Fixed incorrect release folder name in docs ([#560](https://github.com/stlink-org/stlink/pull/560)) +* Fixed compilation when path includes spaces ([#561](https://github.com/stlink-org/stlink/pull/561)) v1.3.0 @@ -172,48 +172,48 @@ Release date: 2017-01-28 Major changes and added features: -* Deprecation of autotools (autoconf, automake) and fixed build with MinGW ([#83](https://github.com/texane/stlink/pull/83), [#431](https://github.com/texane/stlink/pull/431), [#434](https://github.com/texane/stlink/pull/434), [#465](https://github.com/texane/stlink/pull/465)) -* Added intel hex file reading for `st-flash` ([#110](https://github.com/texane/stlink/pull/110), [#157](https://github.com/texane/stlink/pull/157), [#457](https://github.com/texane/stlink/pull/547), [#459](https://github.com/texane/stlink/pull/549)) -* Added support for ARM semihosting to `st-util` ([#147](https://github.com/texane/stlink/pull/147), [#227](https://github.com/texane/stlink/pull/227), [#454](https://github.com/texane/stlink/pull/454), [#455](https://github.com/texane/stlink/pull/455)) -* Added manpages (generated with pandoc from Markdown) ([#208](https://github.com/texane/stlink/pull/208), [#464](https://github.com/texane/stlink/pull/464), [#466](https://github.com/texane/stlink/pull/466), [#467](https://github.com/texane/stlink/pull/467)) -* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/texane/stlink/pull/228), ([#507](https://github.com/texane/stlink/pull/507), commit [#3fd0f09](https://github.com/texane/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) -* Support serial numbers argument for `st-util` and `st-flash` to probe and control multiple connected programmers ([#318](https://github.com/texane/stlink/pull/318), [#398](https://github.com/texane/stlink/pull/398), [#541](https://github.com/texane/stlink/pull/541)) -* Merge st-probe tool into st-info ([#398](https://github.com/texane/stlink/pull/398)) -* Added support for native debian packaging ([#444](https://github.com/texane/stlink/pull/444), [#472](https://github.com/texane/stlink/pull/472), [#473](https://github.com/texane/stlink/pull/473), [#482](https://github.com/texane/stlink/pull/482), [#483](https://github.com/texane/stlink/pull/483), [#484](https://github.com/texane/stlink/pull/484), [#485](https://github.com/texane/stlink/pull/485)) -* Rewritten commandline parsing for `st-flash` ([#459](https://github.com/texane/stlink/pull/459)) -* Added `--reset` command to `st-flash` ([#505](https://github.com/texane/stlink/pull/505)) -* st-util should detect when USB commands fail ([#525](https://github.com/texane/stlink/pull/525), ([#527](https://github.com/texane/stlink/pull/527), ([#528](https://github.com/texane/stlink/pull/528)) +* Deprecation of autotools (autoconf, automake) and fixed build with MinGW ([#83](https://github.com/stlink-org/stlink/pull/83), [#431](https://github.com/stlink-org/stlink/pull/431), [#434](https://github.com/stlink-org/stlink/pull/434), [#465](https://github.com/stlink-org/stlink/pull/465)) +* Added intel hex file reading for `st-flash` ([#110](https://github.com/stlink-org/stlink/pull/110), [#157](https://github.com/stlink-org/stlink/pull/157), [#457](https://github.com/stlink-org/stlink/pull/547), [#459](https://github.com/stlink-org/stlink/pull/549)) +* Added support for ARM semihosting to `st-util` ([#147](https://github.com/stlink-org/stlink/pull/147), [#227](https://github.com/stlink-org/stlink/pull/227), [#454](https://github.com/stlink-org/stlink/pull/454), [#455](https://github.com/stlink-org/stlink/pull/455)) +* Added manpages (generated with pandoc from Markdown) ([#208](https://github.com/stlink-org/stlink/pull/208), [#464](https://github.com/stlink-org/stlink/pull/464), [#466](https://github.com/stlink-org/stlink/pull/466), [#467](https://github.com/stlink-org/stlink/pull/467)) +* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/stlink-org/stlink/pull/228), ([#507](https://github.com/stlink-org/stlink/pull/507), commit [#3fd0f09](https://github.com/stlink-org/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) +* Support serial numbers argument for `st-util` and `st-flash` to probe and control multiple connected programmers ([#318](https://github.com/stlink-org/stlink/pull/318), [#398](https://github.com/stlink-org/stlink/pull/398), [#541](https://github.com/stlink-org/stlink/pull/541)) +* Merge st-probe tool into st-info ([#398](https://github.com/stlink-org/stlink/pull/398)) +* Added support for native debian packaging ([#444](https://github.com/stlink-org/stlink/pull/444), [#472](https://github.com/stlink-org/stlink/pull/472), [#473](https://github.com/stlink-org/stlink/pull/473), [#482](https://github.com/stlink-org/stlink/pull/482), [#483](https://github.com/stlink-org/stlink/pull/483), [#484](https://github.com/stlink-org/stlink/pull/484), [#485](https://github.com/stlink-org/stlink/pull/485)) +* Rewritten commandline parsing for `st-flash` ([#459](https://github.com/stlink-org/stlink/pull/459)) +* Added `--reset` command to `st-flash` ([#505](https://github.com/stlink-org/stlink/pull/505)) +* st-util should detect when USB commands fail ([#525](https://github.com/stlink-org/stlink/pull/525), ([#527](https://github.com/stlink-org/stlink/pull/527), ([#528](https://github.com/stlink-org/stlink/pull/528)) Chip support added for: -* STM32F401XE: Added memory map for device ([#460](https://github.com/texane/stlink/pull/460)) -* STM32F410RBTx ([#418](https://github.com/texane/stlink/pull/418)) -* STM32F412 ([#537](https://github.com/texane/stlink/pull/537), [#538](https://github.com/texane/stlink/pull/538)) -* STM32F7xx ([#324](https://github.com/texane/stlink/pull/324), [#326](https://github.com/texane/stlink/pull/326), [#327](https://github.com/texane/stlink/pull/327), [#337](https://github.com/texane/stlink/pull/337)) -* STM32F7x7x ([#433](https://github.com/texane/stlink/pull/433), [#435](https://github.com/texane/stlink/pull/435), [#436](https://github.com/texane/stlink/pull/436), [#509](https://github.com/texane/stlink/pull/509)) -* STM32L0xx Cat2 devices (chip-ID: 0x425) ([#414](https://github.com/texane/stlink/pull/414)) -* STM32L0xx Cat5 devices (chip-ID: 0x447) ([#387](https://github.com/texane/stlink/pull/387), [#406](https://github.com/texane/stlink/pull/406)) -* STM32L4xx ([#321](https://github.com/texane/stlink/pull/321)) -* STM32L432 ([#500](https://github.com/texane/stlink/pull/500), [#501](https://github.com/texane/stlink/pull/501)) +* STM32F401XE: Added memory map for device ([#460](https://github.com/stlink-org/stlink/pull/460)) +* STM32F410RBTx ([#418](https://github.com/stlink-org/stlink/pull/418)) +* STM32F412 ([#537](https://github.com/stlink-org/stlink/pull/537), [#538](https://github.com/stlink-org/stlink/pull/538)) +* STM32F7xx ([#324](https://github.com/stlink-org/stlink/pull/324), [#326](https://github.com/stlink-org/stlink/pull/326), [#327](https://github.com/stlink-org/stlink/pull/327), [#337](https://github.com/stlink-org/stlink/pull/337)) +* STM32F7x7x ([#433](https://github.com/stlink-org/stlink/pull/433), [#435](https://github.com/stlink-org/stlink/pull/435), [#436](https://github.com/stlink-org/stlink/pull/436), [#509](https://github.com/stlink-org/stlink/pull/509)) +* STM32L0xx Cat2 devices (chip-ID: 0x425) ([#414](https://github.com/stlink-org/stlink/pull/414)) +* STM32L0xx Cat5 devices (chip-ID: 0x447) ([#387](https://github.com/stlink-org/stlink/pull/387), [#406](https://github.com/stlink-org/stlink/pull/406)) +* STM32L4xx ([#321](https://github.com/stlink-org/stlink/pull/321)) +* STM32L432 ([#500](https://github.com/stlink-org/stlink/pull/500), [#501](https://github.com/stlink-org/stlink/pull/501)) Updates and fixes: -* Fixed "unaligned addr or size" when trying to write a program in RAM ([#323](https://github.com/texane/stlink/pull/323)) -* Fixed flashing on STM32_F3_SMALL ([#325](https://github.com/texane/stlink/pull/325)) -* Fixed STM32L-problem with flash loader ([#390](https://github.com/texane/stlink/pull/390), [#407](https://github.com/texane/stlink/pull/407),[#408](https://github.com/texane/stlink/pull/408)) -* Don't read the target voltage on startup, because it crashes STM32F100 ([#423](https://github.com/texane/stlink/pull/423), [#424](https://github.com/texane/stlink/pull/424)) -* Added a useful error message instead of "[!] send_recv" ([#425](https://github.com/texane/stlink/pull/425), [#426](https://github.com/texane/stlink/pull/426)) -* Do a JTAG reset prior to reading CPU information when processor is in deep sleep ([#428](https://github.com/texane/stlink/pull/428), [#430](https://github.com/texane/stlink/pull/430), [#451](https://github.com/texane/stlink/pull/451)) -* Fixed STM32F030 erase error ([#442](https://github.com/texane/stlink/pull/442)) -* Fixed memory map for STM32F7xx ([#453](https://github.com/texane/stlink/pull/453), [#456](https://github.com/texane/stlink/pull/456)) -* Redesign of `st-flash` commandline options parsing ([#459](https://github.com/texane/stlink/pull/459)) -* Set SWDCLK and fixed jtag_reset bug ([#462](https://github.com/texane/stlink/pull/462), [#475](https://github.com/texane/stlink/pull/475), [#534](https://github.com/texane/stlink/pull/534)) -* doc/compiling.md: Add note about installation and ldconfig ([#478](https://github.com/texane/stlink/pull/478), commit [#be66bbf](https://github.com/texane/stlink/commit/be66bbf200c718904514b044ba84d64a36456218)) -* Fixed Release target to generate the man-pages with pandoc ([#479](https://github.com/texane/stlink/pull/479)) -* Fixed Cygwin build ([#487](https://github.com/texane/stlink/pull/487), ([#506](https://github.com/texane/stlink/pull/506)) -* Reset flash mass erase (MER) bit after mass erase for safety ([#489](https://github.com/texane/stlink/pull/489)) -* Wrong extract command in FindLibUSB.cmake ([#510](https://github.com/texane/stlink/pull/510), [#511](https://github.com/texane/stlink/pull/511)) -* Fixed compilation error on Ubuntu 16.10 ([#514](https://github.com/texane/stlink/pull/514), [#525](https://github.com/texane/stlink/pull/525)) +* Fixed "unaligned addr or size" when trying to write a program in RAM ([#323](https://github.com/stlink-org/stlink/pull/323)) +* Fixed flashing on STM32_F3_SMALL ([#325](https://github.com/stlink-org/stlink/pull/325)) +* Fixed STM32L-problem with flash loader ([#390](https://github.com/stlink-org/stlink/pull/390), [#407](https://github.com/stlink-org/stlink/pull/407),[#408](https://github.com/stlink-org/stlink/pull/408)) +* Don't read the target voltage on startup, because it crashes STM32F100 ([#423](https://github.com/stlink-org/stlink/pull/423), [#424](https://github.com/stlink-org/stlink/pull/424)) +* Added a useful error message instead of "[!] send_recv" ([#425](https://github.com/stlink-org/stlink/pull/425), [#426](https://github.com/stlink-org/stlink/pull/426)) +* Do a JTAG reset prior to reading CPU information when processor is in deep sleep ([#428](https://github.com/stlink-org/stlink/pull/428), [#430](https://github.com/stlink-org/stlink/pull/430), [#451](https://github.com/stlink-org/stlink/pull/451)) +* Fixed STM32F030 erase error ([#442](https://github.com/stlink-org/stlink/pull/442)) +* Fixed memory map for STM32F7xx ([#453](https://github.com/stlink-org/stlink/pull/453), [#456](https://github.com/stlink-org/stlink/pull/456)) +* Redesign of `st-flash` commandline options parsing ([#459](https://github.com/stlink-org/stlink/pull/459)) +* Set SWDCLK and fixed jtag_reset bug ([#462](https://github.com/stlink-org/stlink/pull/462), [#475](https://github.com/stlink-org/stlink/pull/475), [#534](https://github.com/stlink-org/stlink/pull/534)) +* doc/compiling.md: Add note about installation and ldconfig ([#478](https://github.com/stlink-org/stlink/pull/478), commit [#be66bbf](https://github.com/stlink-org/stlink/commit/be66bbf200c718904514b044ba84d64a36456218)) +* Fixed Release target to generate the man-pages with pandoc ([#479](https://github.com/stlink-org/stlink/pull/479)) +* Fixed Cygwin build ([#487](https://github.com/stlink-org/stlink/pull/487), ([#506](https://github.com/stlink-org/stlink/pull/506)) +* Reset flash mass erase (MER) bit after mass erase for safety ([#489](https://github.com/stlink-org/stlink/pull/489)) +* Wrong extract command in FindLibUSB.cmake ([#510](https://github.com/stlink-org/stlink/pull/510), [#511](https://github.com/stlink-org/stlink/pull/511)) +* Fixed compilation error on Ubuntu 16.10 ([#514](https://github.com/stlink-org/stlink/pull/514), [#525](https://github.com/stlink-org/stlink/pull/525)) v1.2.0 @@ -245,9 +245,9 @@ Updates and fixes: * Fixed STM32F2xx memory map (Nicolas Schodet) * Memory map for STM32F42xxx and STM32F43xxx devices (Craig Lilley) * Stm32l0x flash loader (Robin Kreis) -* Send F4 memory-map and features for STM32F429 ([#188](https://github.com/texane/stlink/pull/188), [#196](https://github.com/texane/stlink/pull/196), [#250](https://github.com/texane/stlink/pull/250), [#251](https://github.com/texane/stlink/pull/251)) (Release v1.1.0) -* Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/texane/stlink/pull/218), [#288](https://github.com/texane/stlink/pull/288)) (Release v1.1.0) -* Corrected flash size register address for STM32F2 devices ([#278](https://github.com/texane/stlink/pull/278)) (Release v1.0.0) +* Send F4 memory-map and features for STM32F429 ([#188](https://github.com/stlink-org/stlink/pull/188), [#196](https://github.com/stlink-org/stlink/pull/196), [#250](https://github.com/stlink-org/stlink/pull/250), [#251](https://github.com/stlink-org/stlink/pull/251)) (Release v1.1.0) +* Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/stlink-org/stlink/pull/218), [#288](https://github.com/stlink-org/stlink/pull/288)) (Release v1.1.0) +* Corrected flash size register address for STM32F2 devices ([#278](https://github.com/stlink-org/stlink/pull/278)) (Release v1.0.0) Chip support added for: @@ -256,9 +256,9 @@ Chip support added for: * Added STM32L4 to CHIPID #defines and devices[], flash driver and loader (Dave Vandervies) * Basic support for STM32F446 (Pavel Kirienko) * STM32F303 High Density -* STM32F469/STM32F479 ([#345](https://github.com/texane/stlink/pull/345), [#555](https://github.com/texane/stlink/pull/555)) (Release v1.2.0) +* STM32F469/STM32F479 ([#345](https://github.com/stlink-org/stlink/pull/345), [#555](https://github.com/stlink-org/stlink/pull/555)) (Release v1.2.0) * STM32L1xx Cat.2 devices (Nicolas Schodet) -* STM32L1xx (chip-ID 0x427) ([#152](https://github.com/texane/stlink/pull/152), [#163](https://github.com/texane/stlink/pull/163), [#165](https://github.com/texane/stlink/pull/165)) (Release v1.0.0) +* STM32L1xx (chip-ID 0x427) ([#152](https://github.com/stlink-org/stlink/pull/152), [#163](https://github.com/stlink-org/stlink/pull/163), [#165](https://github.com/stlink-org/stlink/pull/165)) (Release v1.0.0) Board support added for: diff --git a/LICENSE.md b/LICENSE.md index 0a3ddd1f7..9c3b59f0f 100644 --- a/LICENSE.md +++ b/LICENSE.md @@ -1,6 +1,6 @@ BSD 3-Clause License -Copyright (c) 2020, The stlink project (github.com/texane/stlink) & "Capt'ns Missing Link" authors. +Copyright (c) 2020, The stlink project (github.com/stlink-org/stlink) & "Capt'ns Missing Link" authors. All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/README.md b/README.md index b2ff03d54..86be05c8f 100644 --- a/README.md +++ b/README.md @@ -2,11 +2,11 @@ Open source version of the STMicroelectronics STlink Tools ========================================================== [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) -[![GitHub release](https://img.shields.io/github/release/texane/stlink.svg)](https://github.com/stlink-org/stlink/releases/latest) -[![GitHub commits](https://img.shields.io/github/commits-since/texane/stlink/v1.6.0.svg)](https://github.com/stlink-org/stlink/releases/master) -[![Downloads](https://img.shields.io/github/downloads/texane/stlink/total.svg)](https://github.com/stlink-org/stlink/releases) -[![Linux Status](https://img.shields.io/travis/texane/stlink/master.svg?label=linux)](https://travis-ci.org/stlink-org/stlink) -[![macOS Status](https://img.shields.io/travis/texane/stlink/master.svg?label=osx)](https://travis-ci.org/stlink-org/stlink) +[![GitHub release](https://img.shields.io/github/release/stlink-org/stlink.svg)](https://github.com/stlink-org/stlink/releases/latest) +[![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.6.0.svg)](https://github.com/stlink-org/stlink/releases/master) +[![Downloads](https://img.shields.io/github/downloads/stlink-org/stlink/total.svg)](https://github.com/stlink-org/stlink/releases) +[![Linux Status](https://img.shields.io/travis/stlink-org/stlink/master.svg?label=linux)](https://travis-ci.org/stlink-org/stlink) +[![macOS Status](https://img.shields.io/travis/stlink-org/stlink/master.svg?label=osx)](https://travis-ci.org/stlink-org/stlink) Recent new features and bugfixes can be found in the [Changelog](CHANGELOG.md) of this software project. @@ -48,10 +48,12 @@ The STlink toolset includes: * a GUI-Interface (stlink-gui) _[optional]_ -## Supported hardware combinations +## Supported operating systems and hardware combinations Currently known working combinations of programmers and targets are listed in [devices_boards.md](doc/devices_boards.md). +Supported operating systems are listed in [version_support.md](doc/version_support.md). + ## Tutorial & HOWTO @@ -110,13 +112,13 @@ When there is no executable available for your platform or you need the latest ( # Current state of the project ## Known missing features -Some features are currently missing from the `texane/stlink` toolset. +Some features are currently missing from the `stlink-org/stlink` toolset. Here we would appreciate any help and would love to welcome new contributors who want to get involved: -* Instrumentation Trace Macro (ITM) Cell ([#136](https://github.com/texane/stlink/issues/136)) -* OTP & EEPROM area programming ([#202](https://github.com/texane/stlink/issues/202), [#333](https://github.com/texane/stlink/issues/333), [#686](https://github.com/texane/stlink/issues/686)) -* Protection bits area reading ([#346](https://github.com/texane/stlink/issues/346)) -* Writing external memory connected to an STM32 controller (e.g Quad SPI NOR flash) ([#412](https://github.com/texane/stlink/issues/412)) -* MCU hotplug ([#449](https://github.com/texane/stlink/issues/449)) -* Writing options bytes (region) ([#458](https://github.com/texane/stlink/issues/458)) -* Support for STLINKv3 programmer ([#820](https://github.com/texane/stlink/issues/820)) +* Instrumentation Trace Macro (ITM) Cell ([#136](https://github.com/stlink-org/stlink/issues/136)) +* OTP & EEPROM area programming ([#202](https://github.com/stlink-org/stlink/issues/202), [#333](https://github.com/stlink-org/stlink/issues/333), [#686](https://github.com/stlink-org/stlink/issues/686)) +* Protection bits area reading ([#346](https://github.com/stlink-org/stlink/issues/346)) +* Writing external memory connected to an STM32 controller (e.g Quad SPI NOR flash) ([#412](https://github.com/stlink-org/stlink/issues/412)) +* MCU hotplug ([#449](https://github.com/stlink-org/stlink/issues/449)) +* Writing options bytes (region) ([#458](https://github.com/stlink-org/stlink/issues/458)) +* Support for STLINKv3 programmer ([#820](https://github.com/stlink-org/stlink/issues/820)) diff --git a/debian/control b/debian/control index e33fc757c..3c1e9700f 100644 --- a/debian/control +++ b/debian/control @@ -1,12 +1,12 @@ Source: stlink Priority: optional -Maintainer: Andrew 'Necromant' Andrianov +Maintainer: Luca Bocassi Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.1.3 Section: electronics -Homepage: https://github.com/texane/stlink -Vcs-Git: https://github.com/texane/stlink.git -Vcs-Browser: https://github.com/texane/stlink +Homepage: https://github.com/stlink-org/stlink +Vcs-Git: https://github.com/stlink-org/stlink.git +Vcs-Browser: https://github.com/stlink-org/stlink Package: libstlink-dev Section: libdevel diff --git a/debian/copyright b/debian/copyright index 941a4a011..7a6d585c5 100644 --- a/debian/copyright +++ b/debian/copyright @@ -1,7 +1,7 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink -Upstream-Contact: Andrew 'Necromant' Andrianov -Source: https://github.com/texane/stlink +Upstream-Contact: Luca Bocassi +Source: https://github.com/stlink-org/stlink Files: * Copyright: 2011-2018 agpanarin diff --git a/debian/watch b/debian/watch index cc653ca9f..20ad1260e 100644 --- a/debian/watch +++ b/debian/watch @@ -1,3 +1,3 @@ version=3 opts=filenamemangle=s/.+\/v?(\d\S+)\.tar\.gz/-$1\.tar\.gz/ \ - https://github.com/texane/stlink/tags .*/v?(\d\S+)\.tar\.gz + https://github.com/stlink-org/stlink/tags .*/v?(\d\S+)\.tar\.gz diff --git a/tests/flash.c b/tests/flash.c index d193666ff..27391b244 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -4,8 +4,9 @@ #include #include + #if defined(_MSC_VER) -#include + #include #endif struct Test { @@ -15,39 +16,46 @@ struct Test { }; static bool cmp_strings(const char * s1, const char * s2) { - if (s1 == NULL || s2 == NULL) return (s1 == s2); - else return (0 == strcmp(s1, s2)); + if (s1 == NULL || s2 == NULL) { + return (s1 == s2); + } else { + return (0 == strcmp(s1, s2)); + } } static bool cmp_mem(const uint8_t * s1, const uint8_t * s2, size_t size) { - if (s1 == NULL || s2 == NULL) return (s1 == s2); - else return (0 == memcmp(s1, s2, size)); + if (s1 == NULL || s2 == NULL) { + return (s1 == s2); + } else { + return (0 == memcmp(s1, s2, size)); + } } static bool execute_test(const struct Test * test) { int ac = 0; char* av[32]; - // parse (tokenize) the test command line -#if defined(_MSC_VER) - char *cmd_line = alloca(strlen(test->cmd_line) + 1); -#else - char cmd_line[strlen(test->cmd_line) + 1]; -#endif + /* parse (tokenize) the test command line */ + #if defined(_MSC_VER) + char *cmd_line = alloca(strlen(test->cmd_line) + 1); + #else + char cmd_line[strlen(test->cmd_line) + 1]; + #endif + strcpy(cmd_line, test->cmd_line); for (char * tok = strtok(cmd_line, " "); tok; tok = strtok(NULL, " ")) { - if ((size_t)ac >= sizeof(av)/sizeof(av[0])) return false; - + if ((size_t)ac >= sizeof(av)/sizeof(av[0])) + return false; av[ac] = tok; ++ac; } - // call + /* call */ struct flash_opts opts; int res = flash_get_opts(&opts, ac, av); - // compare results + /* compare results */ bool ret = (res == test->res); if (ret && (res == 0)) { @@ -69,45 +77,115 @@ static bool execute_test(const struct Test * test) { static struct Test tests[] = { { "", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset read /dev/sg0 test.bin 0x80000000 0x1000", 0, - { .cmd = FLASH_CMD_READ, .devname = "/dev/sg0", .serial = { 0 }, .filename = "test.bin", - .addr = 0x80000000, .size = 0x1000, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { .cmd = FLASH_CMD_READ, + .devname = "/dev/sg0", + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0x1000, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .format = FLASH_FORMAT_BINARY } + }, { "--debug --reset write /dev/sg0 test.bin 0x80000000", 0, - { .cmd = FLASH_CMD_WRITE, .devname = "/dev/sg0", .serial = { 0 }, .filename = "test.bin", - .addr = 0x80000000, .size = 0, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { .cmd = FLASH_CMD_WRITE, + .devname = "/dev/sg0", + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .format = FLASH_FORMAT_BINARY } + }, { "--serial A1020304 /dev/sg0 erase", -1, FLASH_OPTS_INITIALIZER }, { "/dev/sg0 erase", 0, - { .cmd = FLASH_CMD_ERASE, .devname = "/dev/sg0", .serial = { 0 }, .filename = NULL, - .addr = 0, .size = 0, .reset = 0, .log_level = STND_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { .cmd = FLASH_CMD_ERASE, + .devname = "/dev/sg0", + .serial = { 0 }, + .filename = NULL, + .addr = 0, + .size = 0, + .reset = 0, + .log_level = STND_LOG_LEVEL, + .format = FLASH_FORMAT_BINARY } + }, { "--debug --reset read test.bin 0x80000000 0x1000", 0, - { .cmd = FLASH_CMD_READ, .devname = NULL, .serial = { 0 }, .filename = "test.bin", - .addr = 0x80000000, .size = 0x1000, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { .cmd = FLASH_CMD_READ, + .devname = NULL, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0x1000, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .format = FLASH_FORMAT_BINARY } + }, { "--debug --reset write test.bin 0x80000000", 0, - { .cmd = FLASH_CMD_WRITE, .devname = NULL, .serial = { 0 }, .filename = "test.bin", - .addr = 0x80000000, .size = 0, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { .cmd = FLASH_CMD_WRITE, + .devname = NULL, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .format = FLASH_FORMAT_BINARY } + }, { "erase", 0, - { .cmd = FLASH_CMD_ERASE, .devname = NULL, .serial = { 0 }, .filename = NULL, - .addr = 0, .size = 0, .reset = 0, .log_level = STND_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { .cmd = FLASH_CMD_ERASE, + .devname = NULL, + .serial = { 0 }, + .filename = NULL, + .addr = 0, + .size = 0, + .reset = 0, + .log_level = STND_LOG_LEVEL, + .format = FLASH_FORMAT_BINARY } + }, { "--debug --reset --format=ihex write test.hex", 0, - { .cmd = FLASH_CMD_WRITE, .devname = NULL, .serial = { 0 }, .filename = "test.hex", - .addr = 0, .size = 0, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_IHEX } }, + { .cmd = FLASH_CMD_WRITE, + .devname = NULL, + .serial = { 0 }, + .filename = "test.hex", + .addr = 0, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .format = FLASH_FORMAT_IHEX } + }, { "--debug --reset --format=binary write test.hex", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset --format=ihex write test.hex 0x80000000", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset write test.hex sometext", -1, FLASH_OPTS_INITIALIZER }, { "--serial A1020304 erase", 0, - { .cmd = FLASH_CMD_ERASE, .devname = NULL, .serial = "\0\0\0\0\0\0\0\0\xA1\x02\x03\x04", .filename = NULL, - .addr = 0, .size = 0, .reset = 0, .log_level = STND_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { .cmd = FLASH_CMD_ERASE, + .devname = NULL, + .serial = "\0\0\0\0\0\0\0\0\xA1\x02\x03\x04", + .filename = NULL, + .addr = 0, + .size = 0, + .reset = 0, + .log_level = STND_LOG_LEVEL, + .format = FLASH_FORMAT_BINARY } + }, { "--serial=A1020304 erase", 0, - { .cmd = FLASH_CMD_ERASE, .devname = NULL, .serial = "\0\0\0\0\0\0\0\0\xA1\x02\x03\x04", .filename = NULL, - .addr = 0, .size = 0, .reset = 0, .log_level = STND_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { .cmd = FLASH_CMD_ERASE, + .devname = NULL, + .serial = "\0\0\0\0\0\0\0\0\xA1\x02\x03\x04", + .filename = NULL, + .addr = 0, + .size = 0, + .reset = 0, + .log_level = STND_LOG_LEVEL, + .format = FLASH_FORMAT_BINARY } + }, }; -int main() -{ +int main() { bool allOk = true; for (size_t i = 0; i < sizeof(tests)/sizeof(tests[0]); ++i) { - if (!execute_test(&tests[i])) allOk = false; + if (!execute_test(&tests[i])) + allOk = false; } - return (allOk ? 0 : 1); } - diff --git a/tests/sg.c b/tests/sg.c index a014717d7..32ef55b69 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -1,6 +1,6 @@ -/* +/* * File: test_main.c - * + * * main() ripped out of old stlink-hw.c */ @@ -10,7 +10,7 @@ #include #if defined(_MSC_VER) -#define __attribute__(x) + #define __attribute__(x) #endif static void __attribute__((unused)) mark_buf(stlink_t *sl) { @@ -24,24 +24,22 @@ static void __attribute__((unused)) mark_buf(stlink_t *sl) { sl->q_buf[16] = 0x33; sl->q_buf[63] = 0x44; sl->q_buf[64] = 0x69; - sl->q_buf[1024 * 6 - 1] = 0x42; //6kB - sl->q_buf[1024 * 8 - 1] = 0x42; //8kB + sl->q_buf[1024 * 6 - 1] = 0x42; // 6kB + sl->q_buf[1024 * 8 - 1] = 0x42; // 8kB } -int main(void) -{ +int main(void) { /* Avoid unused parameter warning */ // set scpi lib debug level: 0 for no debug info, 10 for lots - - fputs( - "\nUsage: stlink-access-test [anything at all] ...\n" - "\n*** Notice: The stlink firmware violates the USB standard.\n" - "*** Because we just use libusb, we can just tell the kernel's\n" - "*** driver to simply ignore the device...\n" - "*** Unplug the stlink and execute once as root:\n" - "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n", - stderr); + fputs( + "\nUsage: stlink-access-test [anything at all] ...\n" + "\n*** Notice: The stlink firmware violates the USB standard.\n" + "*** Because we just use libusb, we can just tell the kernel's\n" + "*** driver to simply ignore the device...\n" + "*** Unplug the stlink and execute once as root:\n" + "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n", + stderr); stlink_t *sl = stlink_v1_open(99, 1); if (sl == NULL) @@ -51,8 +49,6 @@ int main(void) stlink_enter_swd_mode(sl); stlink_current_mode(sl); stlink_core_id(sl); - //---------------------------------------------------------------------- - stlink_status(sl); //stlink_force_debug(sl); stlink_reset(sl); @@ -67,19 +63,19 @@ int main(void) #if 0 stlink_read_mem32(sl, 0xe000edf0, 4); DD(sl, "DHCSR = 0x%08x", read_uint32(sl->q_buf, 0)); - stlink_read_mem32(sl, 0x4001100c, 4); DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); #endif + #if 0 - // happy new year 2011: let blink all the leds + // let blink all the leds // see "RM0041 Reference manual - STM32F100xx advanced ARM-based 32-bit MCUs" -#define GPIOC 0x40011000 // port C -#define GPIOC_CRH (GPIOC + 0x04) // port configuration register high -#define GPIOC_ODR (GPIOC + 0x0c) // port output data register -#define LED_BLUE (1<<8) // pin 8 -#define LED_GREEN (1<<9) // pin 9 + #define GPIOC 0x40011000 // port C + #define GPIOC_CRH (GPIOC + 0x04) // port configuration register high + #define GPIOC_ODR (GPIOC + 0x0c) // port output data register + #define LED_BLUE (1<<8) // pin 8 + #define LED_GREEN (1<<9) // pin 9 stlink_read_mem32(sl, GPIOC_CRH, 4); uint32_t io_conf = read_uint32(sl->q_buf, 0); DLOG("GPIOC_CRH = 0x%08x\n", io_conf); @@ -92,8 +88,8 @@ int main(void) for (int i = 0; i < 100; i++) { write_uint32(sl->q_buf, LED_BLUE | LED_GREEN); stlink_write_mem32(sl, GPIOC_ODR, 4); - /* stlink_read_mem32(sl, 0x4001100c, 4); */ - /* DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); */ + //stlink_read_mem32(sl, 0x4001100c, 4); + //DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); usleep(100 * 1000); memset(sl->q_buf, 0, sizeof(sl->q_buf)); @@ -101,8 +97,8 @@ int main(void) usleep(100 * 1000); } write_uint32(sl->q_buf, io_conf); // set old state - #endif + #if 0 // TODO rtfm: stlink doesn't have flash write routines // writing to the flash area confuses the fw for the next read access @@ -119,18 +115,19 @@ int main(void) stlink_read_mem32(sl, 0x08000c00, 256); stlink_read_mem32(sl, 0x08000c00, 256); #endif + #if 0 // sram 0x20000000 8kB fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); memset(sl->q_buf, 0, sizeof(sl->q_buf)); mark_buf(sl); //stlink_write_mem8(sl, 0x20000000, 16); - //stlink_write_mem8(sl, 0x20000000, 1); //stlink_write_mem8(sl, 0x20000001, 1); stlink_write_mem8(sl, 0x2000000b, 3); stlink_read_mem32(sl, 0x20000000, 16); #endif + #if 0 // a not aligned mem32 access doesn't work indeed fputs("\n++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); @@ -149,6 +146,7 @@ int main(void) stlink_write_mem32(sl, 0x20000000, 17); stlink_read_mem32(sl, 0x20000000, 32); #endif + #if 0 // sram 0x20000000 8kB fputs("++++++++++ read/write 32bit, sram at 0x2000 0000 ++++++++++++\n", stderr); @@ -162,26 +160,30 @@ int main(void) stlink_read_mem32(sl, 0x20000000, 1024 * 6); stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2); #endif + #if 0 stlink_run(sl); stlink_status(sl); - stlink_force_debug(sl); stlink_status(sl); #endif + #if 0 /* read the system bootloader */ fputs("\n++++++++++ reading bootloader ++++++++++++++++\n\n", stderr); stlink_fread(sl, "/tmp/barfoo", sl->sys_base, sl->sys_size); #endif + #if 0 /* read the flash memory */ fputs("\n+++++++ read flash memory\n\n", stderr); /* mark_buf(sl); */ stlink_read_mem32(sl, 0x08000000, 4); #endif + #if 0 /* flash programming */ fputs("\n+++++++ program flash memory\n\n", stderr); stlink_fwrite_flash(sl, "/tmp/foobar", 0x08000000); #endif + #if 0 /* check file contents */ fputs("\n+++++++ check flash memory\n\n", stderr); { @@ -189,6 +191,7 @@ int main(void) printf("_____ stlink_fcheck_flash() == %d\n", res); } #endif + #if 0 fputs("\n+++++++ sram write and execute\n\n", stderr); stlink_fwrite_sram(sl, "/tmp/foobar", sl->sram_base); @@ -198,13 +201,13 @@ int main(void) #if 0 stlink_run(sl); stlink_status(sl); - //---------------------------------------------------------------------- // back to mass mode, just in case ... stlink_exit_debug_mode(sl); stlink_current_mode(sl); stlink_close(sl); #endif - //fflush(stderr); fflush(stdout); + //fflush(stderr); + //fflush(stdout); return EXIT_SUCCESS; } diff --git a/tests/usb.c b/tests/usb.c index 06fd73429..082c8583b 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -1,10 +1,9 @@ #include #include -int main(int ac, char** av) -{ - (void)ac; - (void)av; +int main(int ac, char** av) { + (void)ac; + (void)av; stlink_t* sl; struct stlink_reg regs; @@ -43,12 +42,12 @@ int main(int ac, char** av) printf("FP_CTRL\n"); stlink_read_mem32(sl, STLINK_REG_CM3_FP_CTRL, 4); - // no idea what reg this is.. */ - // stlink_read_mem32(sl, 0xe000ed90, 4); + // no idea what reg this is... + //stlink_read_mem32(sl, 0xe000ed90, 4); // no idea what register this is... - // stlink_read_mem32(sl, 0xe000edf0, 4); + //stlink_read_mem32(sl, 0xe000edf0, 4); // offset 0xC into TIM11 register? TIMx_DIER? - // stlink_read_mem32(sl, 0x4001100c, 4); */ + //stlink_read_mem32(sl, 0x4001100c, 4); /* Test 32 bit Write */ write_uint32(sl->q_buf,0x01234567); @@ -72,14 +71,13 @@ int main(int ac, char** av) printf("-- reset\n"); stlink_reset(sl); stlink_force_debug(sl); - /* Test reg write*/ + /* Test reg write */ stlink_write_reg(sl, 0x01234567, 3); stlink_write_reg(sl, 0x89abcdef, 4); stlink_write_reg(sl, 0x12345678, 15); for (off = 0; off < 21; off += 1) stlink_read_reg(sl, off, ®s); - stlink_read_all_regs(sl, ®s); printf("-- status\n"); @@ -96,6 +94,5 @@ int main(int ac, char** av) stlink_close(sl); } - return 0; } From aa38587e3c357b6c09934409baa9d685994a09f9 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 17 Apr 2020 12:54:43 +0200 Subject: [PATCH 0833/1435] Restored functionality of make test builds (Fixes #926) --- include/stlink/tools/flash.h | 3 +-- tests/flash.c | 30 +++++------------------------- 2 files changed, 6 insertions(+), 27 deletions(-) diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index 659c17f28..15e020b35 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -14,7 +14,6 @@ enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1,FLASH_OTP = 2, F struct flash_opts { enum flash_cmd cmd; - const char* devname; uint8_t serial[STLINK_SERIAL_MAX_SIZE]; const char* filename; stm32_addr_t addr; @@ -28,7 +27,7 @@ struct flash_opts int opt; }; -#define FLASH_OPTS_INITIALIZER {0, NULL, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0} +#define FLASH_OPTS_INITIALIZER {0, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0} int flash_get_opts(struct flash_opts* o, int ac, char** av); diff --git a/tests/flash.c b/tests/flash.c index 27391b244..53032474a 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -60,7 +60,6 @@ static bool execute_test(const struct Test * test) { if (ret && (res == 0)) { ret &= (opts.cmd == test->opts.cmd); - ret &= cmp_strings(opts.devname, test->opts.devname); ret &= cmp_mem(opts.serial, test->opts.serial, sizeof(opts.serial)); ret &= cmp_strings(opts.filename, test->opts.filename); ret &= (opts.addr == test->opts.addr); @@ -76,9 +75,8 @@ static bool execute_test(const struct Test * test) { static struct Test tests[] = { { "", -1, FLASH_OPTS_INITIALIZER }, - { "--debug --reset read /dev/sg0 test.bin 0x80000000 0x1000", 0, + { "--debug --reset read test.bin 0x80000000 0x1000", 0, { .cmd = FLASH_CMD_READ, - .devname = "/dev/sg0", .serial = { 0 }, .filename = "test.bin", .addr = 0x80000000, @@ -87,9 +85,8 @@ static struct Test tests[] = { .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, - { "--debug --reset write /dev/sg0 test.bin 0x80000000", 0, + { "--debug --reset write test.bin 0x80000000", 0, { .cmd = FLASH_CMD_WRITE, - .devname = "/dev/sg0", .serial = { 0 }, .filename = "test.bin", .addr = 0x80000000, @@ -98,21 +95,8 @@ static struct Test tests[] = { .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, - { "--serial A1020304 /dev/sg0 erase", -1, FLASH_OPTS_INITIALIZER }, - { "/dev/sg0 erase", 0, - { .cmd = FLASH_CMD_ERASE, - .devname = "/dev/sg0", - .serial = { 0 }, - .filename = NULL, - .addr = 0, - .size = 0, - .reset = 0, - .log_level = STND_LOG_LEVEL, - .format = FLASH_FORMAT_BINARY } - }, { "--debug --reset read test.bin 0x80000000 0x1000", 0, { .cmd = FLASH_CMD_READ, - .devname = NULL, .serial = { 0 }, .filename = "test.bin", .addr = 0x80000000, @@ -123,7 +107,6 @@ static struct Test tests[] = { }, { "--debug --reset write test.bin 0x80000000", 0, { .cmd = FLASH_CMD_WRITE, - .devname = NULL, .serial = { 0 }, .filename = "test.bin", .addr = 0x80000000, @@ -134,7 +117,6 @@ static struct Test tests[] = { }, { "erase", 0, { .cmd = FLASH_CMD_ERASE, - .devname = NULL, .serial = { 0 }, .filename = NULL, .addr = 0, @@ -145,7 +127,6 @@ static struct Test tests[] = { }, { "--debug --reset --format=ihex write test.hex", 0, { .cmd = FLASH_CMD_WRITE, - .devname = NULL, .serial = { 0 }, .filename = "test.hex", .addr = 0, @@ -157,10 +138,10 @@ static struct Test tests[] = { { "--debug --reset --format=binary write test.hex", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset --format=ihex write test.hex 0x80000000", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset write test.hex sometext", -1, FLASH_OPTS_INITIALIZER }, + { "--serial A1020304 erase sometext", -1, FLASH_OPTS_INITIALIZER }, { "--serial A1020304 erase", 0, { .cmd = FLASH_CMD_ERASE, - .devname = NULL, - .serial = "\0\0\0\0\0\0\0\0\xA1\x02\x03\x04", + .serial = "\xA1\x02\x03\x04", .filename = NULL, .addr = 0, .size = 0, @@ -170,8 +151,7 @@ static struct Test tests[] = { }, { "--serial=A1020304 erase", 0, { .cmd = FLASH_CMD_ERASE, - .devname = NULL, - .serial = "\0\0\0\0\0\0\0\0\xA1\x02\x03\x04", + .serial = "\xA1\x02\x03\x04", .filename = NULL, .addr = 0, .size = 0, From 07c5e324a805a21763416e1a419764dd5185effa Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 17 Apr 2020 13:21:07 +0200 Subject: [PATCH 0834/1435] Updated CHANGELOG for upcoming release --- CHANGELOG.md | 61 ++++++++++++++++++++++++++++++++++- CMakeLists.txt | 22 ++++++------- src/stlink-gui/CMakeLists.txt | 2 +- 3 files changed, 71 insertions(+), 14 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 8cf102910..ce2a9e595 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,65 @@ -Stlink ChangeLog +stlink ChangeLog ================ +v1.6.1 +====== + +Release date: (TBD) + +This release drops support for some older operating systems. Check project README for details. + +Features: + +- Support for STM32L1, SM32L4 option bytes write (#596, #844, #847) +- CMake now creates an uninstall target (#619, #907) +- Support for STM32G4 (#822) +- Add aliased SRAM2 region in the L496 memory map (#824) +- Improved support for STM32G0 (#825, #850, #856, #857) +- Added usb PID and udev rules for STlink v2.1 found on Nucleo-L432KC and Nucleo-L552ze boards (#900) +- STM32G0/G4 improvements (#910) + - Enable mass erase with a flash programming check + - Handle G4 Cat3 devices with configurable dual bank flash by using a helper +- Calculate checksums for flash operations (#862, #924) + +Updates & changes: + +- Improved argument parsing for CLI tools (#378, #922) +- [doc] Updated tutorial: macOS ST-Link-v1 detection (#574, #587) +- Define libusb version compatibility for supported operating systems via LIBUSB_API_VERSION (#211, #782, #895) +- [doc] Verify correct udev configuration for device access (#764) +- Added more error info to WLOGs during probe (#883) +- Added travis build for win32 (#870) +- Added check for libssp during compilation (#885) +- Silence unnecessary messages (#886) +- Set up a libusb log level accordingly to verbosity (commit 49f887d5247fdd28f163b6317790c4f087e652cc) +- [doc] Define libusb & cmake version compatibility (#896, #897, #899, commit 27aa88821197d3ffe82baff4e971c3488ec39899) +- Update for STM32G471/473/474/483/484 devices (#901) +- [doc] st-flash --flash=n[k][m] command line option to override device model (#902) +- [doc] Update compiling instructions (#113, commit 10ae5294cd03aacfc07312010f026d3cb12ea56c) +- [doc] Defined version compatibility and installation instructions for macOS (commit 23c071edea45f6e8852fef52d884a680973d6d8f) +- Deprecated old appveyor-mingw script (commit 97484422008df0f75c978627054776f35842a075) +- Enhanced error log with file path for map_file() (#650, #879, #921) + +Fixes: + +- Fixed wait-loop for flash_loader_run() (#290) +- Clear the PG bit before setting the PER bit (#579, #876) +- Fixed compilation issues with int length on 32-bit platforms (#629, #908) +- Fixed st-info --probe mechanism (#679, #918) +- Fixed sign-compare (size != rep_len) in usb.c (Regression) (#772, #869, #872, #891) +- Avoid re-define of O_BINARY on Windows (#788) +- Fixed st-flash manpage read example (#858) +- Fixed stlink support with no mass storage (#861) +- Make Version.cmake more error-resistant (#872) +- Error return in failed probe (#887, #890) +- Fixed formatting for options display in st-flash & st-info (commits c783d0e777ccc83a7a8be26a4f4d3414e0478560 and 562cd2496e696dbd22950925866aac662d81ee5f) +- Fixed dead loop after an unexpected unplug (#780, #812, #913) +- Fixed broken build on 32-bit systems (#919, #920) +- st-flash: minor usage fix and make cmdline parsing more user friendly (#925) +- Better argument parsing for CLI tools: stlink_open_usb can address v1, v2, v3 (#378, #922) +- Restored functionality of make test builds (Regression) (#926) + + v1.6.0 ====== diff --git a/CMakeLists.txt b/CMakeLists.txt index 87bd47aac..421ec7c6f 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -107,7 +107,7 @@ set(STLINK_SOURCE src/md5.c ) -if (WIN32 OR MSYS OR MINGW) +if (WIN32 OR MINGW OR MSYS) set(STLINK_SOURCE "${STLINK_SOURCE};src/mmap.c;src/mingw/mingw.c") set(STLINK_HEADERS "${STLINK_HEADERS};src/mingw/mingw.h") endif () @@ -116,6 +116,7 @@ include_directories(${LIBUSB_INCLUDE_DIR}) include_directories(include) include_directories(${PROJECT_BINARY_DIR}/include) include_directories(src/mingw) + if (MSVC) include_directories(src/win32) include_directories(src/getopt) @@ -130,7 +131,7 @@ endif () if (NOT WIN32) set(STLINK_LIB_SHARED ${PROJECT_NAME}) -else () +else (WIN32) set(STLINK_LIB_SHARED ${PROJECT_NAME}-shared) endif () @@ -164,16 +165,13 @@ if (APPLE) target_link_libraries(${STLINK_LIB_SHARED} ${CoreFoundation} ${IOKit} ${ObjC} ${SSP_LIB}) endif () -if (WIN32 OR MSYS OR MINGW) +if (WIN32 OR MINGW OR MSYS) target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} wsock32 ws2_32 ${SSP_LIB}) else () target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB}) endif () -install( - TARGETS ${STLINK_LIB_SHARED} - DESTINATION ${STLINK_LIBRARY_PATH} - ) +install(TARGETS ${STLINK_LIB_SHARED} DESTINATION ${STLINK_LIBRARY_PATH}) ### TODO: Check path ### @@ -188,7 +186,7 @@ add_library( ${STLINK_SOURCE} ) -# Link shared library with Apple macOS libraries +# Link static library with Apple macOS libraries if (APPLE) find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) @@ -196,7 +194,7 @@ if (APPLE) target_link_libraries(${STLINK_LIB_STATIC} ${CoreFoundation} ${IOKit} ${ObjC} ${SSP_LIB}) endif () -if (WIN32 OR MSYS OR MINGW) +if (WIN32 OR MINGW OR MSYS) ### TODO: MinGW OR MSYS on Linux target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} wsock32 ws2_32 ${SSP_LIB}) else () target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB}) @@ -205,7 +203,7 @@ endif () set_target_properties(${STLINK_LIB_STATIC} PROPERTIES OUTPUT_NAME ${PROJECT_NAME}) if (STLINK_STATIC_LIB) - install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH}) + install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH}) ### TODO: Check path endif () @@ -224,7 +222,7 @@ else () target_link_libraries(st-info ${STLINK_LIB_SHARED} ${SSP_LIB}) endif () -install(TARGETS st-flash st-info RUNTIME DESTINATION bin) +install(TARGETS st-flash st-info RUNTIME DESTINATION bin) ### TODO: Check path if (CMAKE_SYSTEM_NAME STREQUAL "Linux") if (STLINK_INSTALL_MODPROBE_CONF) @@ -245,7 +243,7 @@ add_subdirectory(src/stlink-gui) ### add_subdirectory(debian/pkgconfig) -add_subdirectory(include) +add_subdirectory(include) ### TODO: Check path add_subdirectory(doc/man) add_subdirectory(tests) diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index bb6465481..64aba11a5 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -28,6 +28,6 @@ install(TARGETS stlink-gui RUNTIME DESTINATION bin) install(FILES gui.ui DESTINATION ${INSTALLED_UI_DIR}) ### TODO: Check Path if (${CMAKE_SYSTEM_NAME} MATCHES "Linux") - install(FILES stlink-gui.desktop DESTINATION share/applications) # Install desktop entry + install(FILES stlink-gui.desktop DESTINATION share/applications) # Install desktop entry install(FILES icons/stlink-gui.svg DESTINATION share/icons/hicolor/scalable/apps) # Install icon endif () From 264417e4b3159cc7664768c26015a9246c828c8c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 17 Apr 2020 14:41:48 +0200 Subject: [PATCH 0835/1435] Fix for version string read without git --- CMakeLists.txt | 13 +++++++------ cmake/version.cmake | 9 ++++++++- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 421ec7c6f..5ea53e114 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -54,12 +54,14 @@ endif () ### find_package(LibUSB REQUIRED) + if (NOT APPLE AND NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) find_package(PkgConfig) pkg_check_modules(gtk gtk+-3.0) endif () include(CheckIncludeFile) + CHECK_INCLUDE_FILE(sys/mman.h STLINK_HAVE_SYS_MMAN_H) if (STLINK_HAVE_SYS_MMAN_H) add_definitions(-DSTLINK_HAVE_SYS_MMAN_H) @@ -71,8 +73,8 @@ if (STLINK_HAVE_UNISTD_H) endif () include(CheckLibraryExists) -CHECK_LIBRARY_EXISTS(ssp __stack_chk_fail "" _stack_chk_fail_exists) +CHECK_LIBRARY_EXISTS(ssp __stack_chk_fail "" _stack_chk_fail_exists) if (_stack_chk_fail_exists) set(SSP_LIB ssp) else () @@ -151,11 +153,10 @@ message(STATUS "STLINK_LIB_SHARED: ${STLINK_LIB_SHARED}") message(STATUS "PROJECT_VERSION_MAJOR: ${PROJECT_VERSION_MAJOR}") message(STATUS "VERSION: ${STLINK_SHARED_VERSION}") -set_target_properties( - ${STLINK_LIB_SHARED} - PROPERTIES SOVERSION ${PROJECT_VERSION_MAJOR} - VERSION ${STLINK_SHARED_VERSION} - ) +set_target_properties(${STLINK_LIB_SHARED} PROPERTIES + SOVERSION ${PROJECT_VERSION_MAJOR} + VERSION ${STLINK_SHARED_VERSION} + ) # Link shared library with Apple macOS libraries if (APPLE) diff --git a/cmake/version.cmake b/cmake/version.cmake index 38254409f..da9d76eba 100644 --- a/cmake/version.cmake +++ b/cmake/version.cmake @@ -77,7 +77,14 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") endif(GIT_DESCRIBE_RESULT EQUAL 0) endif () -if (ERROR_FLAG EQUAL 1) +# Failure to read version via git +# Possible cases: +# -> git is not found or +# -> /.git does not exist or +# -> GIT_DESCRIBE failed or +# -> version string is of invalid format + +if (NOT GIT_FOUND OR NOT EXISTS "${PROJECT_SOURCE_DIR}/.git" OR ERROR_FLAG EQUAL 1) message(STATUS "Git and/or repository not found.") # e.g. when building from source package message(STATUS "Try to detect version from \"${PROJECT_SOURCE_DIR}/.version\" file instead...") if (EXISTS ${PROJECT_SOURCE_DIR}/.version) From 155439230a042e24812b505ab5d1f6c7e5a49c3a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 17 Apr 2020 15:43:35 +0200 Subject: [PATCH 0836/1435] Unified naming for cmake modules & paths --- CMakeLists.txt | 4 ++-- cmake/modules/{Find7Zip.cmake => Find7zip.cmake} | 4 ++++ cmake/modules/{FindLibUSB.cmake => Findlibusb.cmake} | 4 ++-- debian/libstlink-dev.install | 3 +-- debian/{pkgconfig => pkg-config}/CMakeLists.txt | 2 +- debian/{pkgconfig => pkg-config}/pkg-config.pc.cmake | 1 - src/stlink-gui/CMakeLists.txt | 2 +- 7 files changed, 11 insertions(+), 9 deletions(-) rename cmake/modules/{Find7Zip.cmake => Find7zip.cmake} (57%) rename cmake/modules/{FindLibUSB.cmake => Findlibusb.cmake} (99%) rename debian/{pkgconfig => pkg-config}/CMakeLists.txt (91%) rename debian/{pkgconfig => pkg-config}/pkg-config.pc.cmake (99%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 5ea53e114..a8daa6e62 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -53,7 +53,7 @@ endif () # Dependencies ### -find_package(LibUSB REQUIRED) +find_package(libusb REQUIRED) if (NOT APPLE AND NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) find_package(PkgConfig) @@ -243,7 +243,7 @@ add_subdirectory(src/stlink-gui) # Others ### -add_subdirectory(debian/pkgconfig) +add_subdirectory(debian/pkg-config) add_subdirectory(include) ### TODO: Check path add_subdirectory(doc/man) add_subdirectory(tests) diff --git a/cmake/modules/Find7Zip.cmake b/cmake/modules/Find7zip.cmake similarity index 57% rename from cmake/modules/Find7Zip.cmake rename to cmake/modules/Find7zip.cmake index c462f73de..0ccd23a50 100644 --- a/cmake/modules/Find7Zip.cmake +++ b/cmake/modules/Find7zip.cmake @@ -1,3 +1,7 @@ +# Find7zip.cmake +# Detect 7zip file archiver on Windows systems to extract (zip-)archives + + find_program( ZIP_EXECUTABLE NAMES 7z.exe p7zip HINTS "C:\\Program Files\\7-Zip\\" "C:\\Program Files (x86)\\7-Zip\\" diff --git a/cmake/modules/FindLibUSB.cmake b/cmake/modules/Findlibusb.cmake similarity index 99% rename from cmake/modules/FindLibUSB.cmake rename to cmake/modules/Findlibusb.cmake index b583b8491..5b3e80fe6 100644 --- a/cmake/modules/FindLibUSB.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -1,4 +1,4 @@ -# FindLibUSB.cmake +# Findlibusb.cmake # Once done this will define # # LIBUSB_FOUND libusb present on system @@ -75,7 +75,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND ${CMAKE_BUILD_TYPE} MATCHES " if (NOT LIBUSB_FOUND OR EXISTS "/etc/debian_version") # Preparations for installing libusb library - find_package(7Zip REQUIRED) + find_package(7zip REQUIRED) set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) diff --git a/debian/libstlink-dev.install b/debian/libstlink-dev.install index 0c3543cd9..18fd98b03 100644 --- a/debian/libstlink-dev.install +++ b/debian/libstlink-dev.install @@ -1,5 +1,4 @@ usr/include/* usr/lib/*/lib*.a -usr/lib/*/pkgconfig/* +usr/lib/*/pkg-config/* usr/lib/*/lib*.so - diff --git a/debian/pkgconfig/CMakeLists.txt b/debian/pkg-config/CMakeLists.txt similarity index 91% rename from debian/pkgconfig/CMakeLists.txt rename to debian/pkg-config/CMakeLists.txt index 02e80cb72..a31e27e50 100644 --- a/debian/pkgconfig/CMakeLists.txt +++ b/debian/pkg-config/CMakeLists.txt @@ -11,5 +11,5 @@ configure_file( install( FILES "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" - DESTINATION ${STLINK_LIBRARY_PATH}/pkgconfig/ + DESTINATION ${STLINK_LIBRARY_PATH}/pkg-config/ ) diff --git a/debian/pkgconfig/pkg-config.pc.cmake b/debian/pkg-config/pkg-config.pc.cmake similarity index 99% rename from debian/pkgconfig/pkg-config.pc.cmake rename to debian/pkg-config/pkg-config.pc.cmake index 4170bf84b..c00eb070e 100644 --- a/debian/pkgconfig/pkg-config.pc.cmake +++ b/debian/pkg-config/pkg-config.pc.cmake @@ -8,4 +8,3 @@ includedir=${PKG_CONFIG_INCLUDEDIR} libdir=${PKG_CONFIG_LIBDIR} Libs: ${PKG_CONFIG_LIBS} Cflags: ${PKG_CONFIG_CFLAGS} - diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 64aba11a5..c51cf56af 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -1,6 +1,6 @@ if (NOT gtk_FOUND) message(STATUS "gtk not found!") - return() + return() # no GTK present => no GUI build endif () set(GUI_SOURCES gui.c gui.h) From ccd167379059b9db53d4e788fdca866b409669a1 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 17 Apr 2020 17:01:36 +0200 Subject: [PATCH 0837/1435] Enable pkg_check for gtk on macOS --- CMakeLists.txt | 2 +- doc/compiling.md | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index a8daa6e62..ee74227fa 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -55,7 +55,7 @@ endif () find_package(libusb REQUIRED) -if (NOT APPLE AND NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) +if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) find_package(PkgConfig) pkg_check_modules(gtk gtk+-3.0) endif () diff --git a/doc/compiling.md b/doc/compiling.md index 59685ef17..a228817a8 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -61,6 +61,7 @@ Install the following packages from your package repository: * `gcc` or `clang` or `mingw32-gcc` or `mingw64-gcc` (C-compiler; very likely gcc is already present) * `build-essential` (on Debian based distros (debian, ubuntu)) * `cmake` (3.4.2 or later, use the latest version available from the repository) +* `pkg-config` * `libusb-1.0` * `libusb-1.0-0-dev` (development headers for building) * `libgtk-3-dev` (_optional_, needed for `stlink-gui`) @@ -168,6 +169,7 @@ Then install the following dependencies from the package repository: * `git` * `cmake` +* `pkg-config` * `libusb` To do this with only one simple command, type: From 9fd9045fdb6c1776ebbeaf634c57739f3e53c826 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 17 Apr 2020 18:13:23 +0200 Subject: [PATCH 0838/1435] General Project Update - Added gtk-package to travis build config - Added gtk to version_support.md (GUI) - Minor correction for CHANGELOG.md - README: Removed reference to OpenBSD --- .travis.yml | 28 ++++++++++++++------------- CHANGELOG.md | 1 - README.md | 1 - doc/version_support.md | 44 +++++++++++++++++++++--------------------- 4 files changed, 37 insertions(+), 37 deletions(-) diff --git a/.travis.yml b/.travis.yml index 542a25d98..b7ff93ff9 100644 --- a/.travis.yml +++ b/.travis.yml @@ -9,42 +9,42 @@ matrix: addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-5', 'libusb-1.0.0-dev'] + packages: ['gcc-5', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux arch: x64 compiler: gcc-7 addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-7', 'libusb-1.0.0-dev'] + packages: ['gcc-7', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux arch: x64 compiler: gcc-9 addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-9', 'libusb-1.0.0-dev'] + packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux arch: x64 compiler: clang-3.7 addons: apt: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-xenial-3.7'] - packages: ['clang-3.7', 'libusb-1.0.0-dev'] + packages: ['clang-3.7', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux arch: x64 compiler: clang-6.0 addons: apt: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] - packages: ['clang-6.0', 'libusb-1.0.0-dev'] + packages: ['clang-6.0', 'libusb-1.0.0-dev', 'libgtk-3-dev'] # - os: linux # arch: x64 # compiler: clang-6.0 # addons: # apt: # sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] -# packages: ['clang-6.0', 'libusb-1.0.0-dev'] +# packages: ['clang-6.0', 'libusb-1.0.0-dev', 'libgtk-3-dev'] # env: CFLAGS=-m32 LDFLAGS=-m32 ### 32-bit builds ### @@ -54,35 +54,35 @@ matrix: addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-5', 'libusb-1.0.0-dev'] + packages: ['gcc-5', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux arch: x86 compiler: gcc-7 addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-7', 'libusb-1.0.0-dev'] + packages: ['gcc-7', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux arch: x86 compiler: gcc-9 addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-9', 'libusb-1.0.0-dev'] + packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux arch: x86 compiler: clang-3.7 addons: apt: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-xenial-3.7'] - packages: ['clang-3.7', 'libusb-1.0.0-dev'] + packages: ['clang-3.7', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux arch: x86 compiler: clang-6.0 addons: apt: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] - packages: ['clang-6.0', 'libusb-1.0.0-dev'] + packages: ['clang-6.0', 'libusb-1.0.0-dev', 'libgtk-3-dev'] ### macOS ### - os: osx @@ -90,15 +90,17 @@ matrix: addons: homebrew: packages: - - libusb - gcc + - libusb + - gtk+3 - os: osx compiler: clang addons: homebrew: packages: - - libusb - clang + - libusb + - gtk+3 script: - git fetch --tags diff --git a/CHANGELOG.md b/CHANGELOG.md index ce2a9e595..9c6060434 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -28,7 +28,6 @@ Updates & changes: - Define libusb version compatibility for supported operating systems via LIBUSB_API_VERSION (#211, #782, #895) - [doc] Verify correct udev configuration for device access (#764) - Added more error info to WLOGs during probe (#883) -- Added travis build for win32 (#870) - Added check for libssp during compilation (#885) - Silence unnecessary messages (#886) - Set up a libusb log level accordingly to verbosity (commit 49f887d5247fdd28f163b6317790c4f087e652cc) diff --git a/README.md b/README.md index 86be05c8f..a0147ed14 100644 --- a/README.md +++ b/README.md @@ -92,7 +92,6 @@ We recommend to install `stlink-tools` from the package repository of the used d * RedHat/CentOS 8: Users can install from [EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel8) * FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) -* OpenBSD: Users need to compile and install from source as described in our [compiling manual](doc/compiling.md). ## Installation from source (advanced users) diff --git a/doc/version_support.md b/doc/version_support.md index 8b1a9b92d..81d1cc98c 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -16,52 +16,52 @@ Thus no user interaction regarding libusb is necessary. ### Apple macOS -| Package Repository | libusb
    version | cmake
    version | Supported macOS versions | -| --- | --- | --- | --- | -| homebrew | 1.0.23 | 3.17.0 | 10.12 (Sierra)- 10.15 (Catalina) | -| MacPorts | 1.0.23 | 3.17.0 | 10.6 (Snow Leopard) - 10.15 (Catalina) | +| Package Repository | libusb
    version | cmake
    version | gtk
    version | Supported macOS versions | +| --- | --- | --- | --- | --- | +| homebrew | 1.0.23 | 3.17.0 | 3.24.18
    gtk+3 | 10.12 (Sierra)- 10.15 (Catalina) | +| MacPorts | 1.0.23 | 3.17.0 | _N/A_ | 10.6 (Snow Leopard) - 10.15 (Catalina) | ### Linux-/Unix-based: -| Operating System | libusb
    version | cmake
    version | Notes | -| --- | --- | --- | --- | +| Operating System | libusb
    version | cmake
    version | gtk
    version | Notes | +| --- | --- | --- | --- | --- | | Alpine Edge | 1.0.23 | 3.17.0 | | | ALT Linux Sisyphus | 1.0.23 | 3.17.0 | | | Arch Linux | 1.0.23 | 3.17.0 | | -| Fedora Rawhide | 1.0.23 | 3.17.0 | named `libusbx`, but `libusb`-codebase is used | +| Fedora Rawhide | 1.0.23 | 3.17.0 | | named `libusbx`, but `libusb`-codebase is used | | KaOS | 1.0.23 | 3.17.0 | | | OpenMandriva Cooker | 1.0.23 | 3.17.0 | | -| PCLinuxOS | 1.0.23 | 3.17.0 | named `lib64usb1.0_0-1.0.23-1pclos2019.x86_64` | +| PCLinuxOS | 1.0.23 | 3.17.0 | | named `lib64usb1.0_0-1.0.23-1pclos2019.x86_64` | | Slackware Current | 1.0.23 | 3.17.0 | | | Solus | 1.0.23 | 3.16.5 | | -| Debian Sid | 1.0.23 | 3.16.3 | | +| Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
    libgtk-3-dev | | | OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | | -| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | | +| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
    libgtk-3-dev | | | openSUSE Tumbleweed | 1.0.23 | 3.16.2 | | | Alpine 3.11 | 1.0.23 | 3.15.5 | | -| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | | +| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
    libgtk-3-dev | | | Mageia Cauldron | 1.0.22 | 3.17.0 | | | NetBSD 9.0 | 1.0.22 | 3.16.1 | | | NetBSD 8.1 | 1.0.22 | 3.16.1 | | | NetBSD 7.2 | 1.0.22 | 3.16.1 | | | Alpine 3.10 | 1.0.22 | 3.14.5 | | -| Fedora 31 | 1.0.22 | 3.14.5 | named `libusbx`, but `libusb`-codebase is used | +| Fedora 31 | 1.0.22 | 3.14.5 | | named `libusbx`, but `libusb`-codebase is used | | Mageia 7.1 | 1.0.22 | 3.14.3 | | -| Fedora 30 | 1.0.22 | 3.14.2 | named `libusbx`, but `libusb`-codebase is used | -| Debian 10 (Buster) | 1.0.22 | 3.13.4 | | +| Fedora 30 | 1.0.22 | 3.14.2 | | named `libusbx`, but `libusb`-codebase is used | +| Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
    libgtk-3-dev | | | Alpine 3.9 | 1.0.22 | 3.13.0 | | -| CentOS 8 | 1.0.22 | 3.11.4 | named `libusbx`, but `libusb`-codebase is used | +| CentOS 8 | 1.0.22 | 3.11.4 | | named `libusbx`, but `libusb`-codebase is used | | openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | | | openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | | -| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | | -| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | | +| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
    libgtk-3-dev | | +| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
    libgtk-3-dev | | | Slackware 14.2 | **1.0.20** | 3.5.2 | | -| Ubuntu 16.04 LTS (Xenial Xerus) | **1.0.20** | 3.5.1 | | +| Ubuntu 16.04 LTS (Xenial Xerus) | **1.0.20** | 3.5.1 | 3.18.9
    libgtk-3-dev | | | OpenMandriva Lx 3.0 | **1.0.20** | **3.4.2** | | -| FreeBSD 13 | **1.0.16** - 1.0.18 | 3.15.5 | linux_libusb-13.0r358841 (integrated) | -| FreeBSD 12 | **1.0.16** - 1.0.18 | 3.15.5 | linux_libusb-11.0r261448_4 (integrated) | -| FreeBSD 11 | **1.0.16** - 1.0.18 | 3.15.5 | linux_libusb-11.0r261448_4 (integrated) | +| FreeBSD 13 | **1.0.16** - 1.0.18 | 3.15.5 | | linux_libusb-13.0r358841 (integrated) | +| FreeBSD 12 | **1.0.16** - 1.0.18 | 3.15.5 | | linux_libusb-11.0r261448_4 (integrated) | +| FreeBSD 11 | **1.0.16** - 1.0.18 | 3.15.5 | | linux_libusb-11.0r261448_4 (integrated) | ## Unsupported Operating Systems as of Release 1.6.1 (2020) @@ -69,7 +69,7 @@ Thus no user interaction regarding libusb is necessary. | Operating System | libusb
    version | cmake
    version | End of OS-Support | Notes | | --- | --- | --- | --- | --- | | CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but `libusb`-codebase is used | -| Debian 8 (Jessie) | 1.0.**19** | 3.0.2 | Jun 2020 | +| Debian 8 (Jessie) | 1.0.**19** | 3.**0.2** | Jun 2020 | | Ubuntu 14.04 LTS (Trusty Tahr) | 1.0.**17** | **2.8.12.2** | Apr 2019 | | CentOS 6 | 1.0.**9** | **2.8.12.2** | Dec 2020 | named `libusbx`, but `libusb`-codebase is used | | Slackware 14.1 | 1.0.**9** | **2.8.12** | | From e98c7d4926ec129e272209552d802a839c743230 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 17 Apr 2020 20:45:33 +0200 Subject: [PATCH 0839/1435] Updated cmake settings from GTK to GTK3 --- CMakeLists.txt | 2 +- src/stlink-gui/CMakeLists.txt | 14 ++++++++------ 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index ee74227fa..e8da6c45c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -57,7 +57,7 @@ find_package(libusb REQUIRED) if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) find_package(PkgConfig) - pkg_check_modules(gtk gtk+-3.0) + pkg_check_modules(GTK3 gtk+-3.0) endif () include(CheckIncludeFile) diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index c51cf56af..dee6cc258 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -1,12 +1,14 @@ -if (NOT gtk_FOUND) - message(STATUS "gtk not found!") - return() # no GTK present => no GUI build +if (NOT GTK3_FOUND) + message(STATUS "GTK3 not found!") + return() # no GTK3 present => no GUI build +else (GTK3_FOUND) + message(STATUS "Found GTK3: -I${GTK3_INCLUDE_DIRS}, ${GTK3_LIBRARIES}") endif () set(GUI_SOURCES gui.c gui.h) set(INSTALLED_UI_DIR share/stlink) ### TODO: Check Path -include_directories(SYSTEM ${gtk_INCLUDE_DIRS}) +include_directories(SYSTEM ${GTK3_INCLUDE_DIRS}) # stlink-gui-local add_executable(stlink-gui-local ${GUI_SOURCES}) @@ -14,7 +16,7 @@ set_target_properties( stlink-gui-local PROPERTIES COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_CURRENT_SOURCE_DIR}" ### TODO: Check Path ) -target_link_libraries(stlink-gui-local ${STLINK_LIB_STATIC} ${gtk_LDFLAGS} ${SSP_LIB}) +target_link_libraries(stlink-gui-local ${STLINK_LIB_STATIC} ${GTK3_LDFLAGS} ${SSP_LIB}) # stlink-gui add_executable(stlink-gui ${GUI_SOURCES}) @@ -22,7 +24,7 @@ set_target_properties( stlink-gui PROPERTIES COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/${INSTALLED_UI_DIR}" ### TODO: Check Path ) -target_link_libraries(stlink-gui ${STLINK_LIB_STATIC} ${gtk_LDFLAGS} ${SSP_LIB}) +target_link_libraries(stlink-gui ${STLINK_LIB_STATIC} ${GTK3_LDFLAGS} ${SSP_LIB}) install(TARGETS stlink-gui RUNTIME DESTINATION bin) ### TODO: Check Path install(FILES gui.ui DESTINATION ${INSTALLED_UI_DIR}) ### TODO: Check Path From f48914512ceb75790abf40fb8df9ed592ab901e1 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 17 Apr 2020 21:09:05 +0200 Subject: [PATCH 0840/1435] [doc] Updated package requirements - Added info on GTK3 libs & versioning - Updated compiling instructions for macOS --- doc/compiling.md | 15 ++++++---- doc/version_support.md | 68 +++++++++++++++++++++--------------------- 2 files changed, 44 insertions(+), 39 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index a228817a8..15d8b4fc2 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -58,6 +58,7 @@ It can be copied from here: `build\3rdparty\libusb-1.0.21\MS32\dll\libusb-1.0.dl Install the following packages from your package repository: +* `git` * `gcc` or `clang` or `mingw32-gcc` or `mingw64-gcc` (C-compiler; very likely gcc is already present) * `build-essential` (on Debian based distros (debian, ubuntu)) * `cmake` (3.4.2 or later, use the latest version available from the repository) @@ -162,22 +163,26 @@ Choose on of the following options _before_ connecting the device to your comput ## macOS ### Common requirements -The best way is to install a package manager for open source software, +The best and recommended way is to install a package manager for open source software, either [homebrew](https://brew.sh) or [MacPorts](https://www.macports.org/). Then install the following dependencies from the package repository: * `git` +* `gcc` or `llvm` (for clang) (C-compiler) * `cmake` * `pkg-config` * `libusb` +* `gtk+3` or `gtk3` (_optional_, needed for `stlink-gui`) To do this with only one simple command, type: -* for homebrew: `sudo brew install git cmake libusb` or -* for MacPorts:`sudo port install git cmake libusb` - -Additionally we recommend to install Xcode which delivers the necessary C-compiler toolchain Clang (LLVM). +* for homebrew: + - with gcc: `sudo brew install git gcc cmake libusb gtk+3` or + - with clang: `sudo brew install git llvm cmake libusb gtk+3` or +* for MacPorts: + - with gcc: `sudo port install git llvm-9.0 cmake libusb gtk3` or + - with clang: `sudo port install git gcc9 cmake libusb gtk3` ### Installation diff --git a/doc/version_support.md b/doc/version_support.md index 81d1cc98c..75def2e66 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,5 +1,5 @@ -Sources: [pkgs.org - libusb](https://pkgs.org/search/?q=libusb) & [pkgs.org - cmake](https://pkgs.org/search/?q=cmake) (as of Mar 2020): +_Source:_ pkgs.org - [libusb](https://pkgs.org/search/?q=libusb); [cmake](https://pkgs.org/search/?q=cmake); [gtk](https://pkgs.org/search/?q=gtk) (as of Apr 2020) ## Supported Operating Systems @@ -16,55 +16,55 @@ Thus no user interaction regarding libusb is necessary. ### Apple macOS -| Package Repository | libusb
    version | cmake
    version | gtk
    version | Supported macOS versions | +| Package Repository | libusb
    version | cmake
    version | gtk-3
    version | Supported macOS versions | | --- | --- | --- | --- | --- | | homebrew | 1.0.23 | 3.17.0 | 3.24.18
    gtk+3 | 10.12 (Sierra)- 10.15 (Catalina) | -| MacPorts | 1.0.23 | 3.17.0 | _N/A_ | 10.6 (Snow Leopard) - 10.15 (Catalina) | +| MacPorts | 1.0.23 | 3.17.0 | 3.24.18
    gtk3 | 10.6 (Snow Leopard) - 10.15 (Catalina) | ### Linux-/Unix-based: -| Operating System | libusb
    version | cmake
    version | gtk
    version | Notes | +| Operating System | libusb
    version | cmake
    version | gtk-3
    version | Notes | | --- | --- | --- | --- | --- | -| Alpine Edge | 1.0.23 | 3.17.0 | | -| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | | -| Arch Linux | 1.0.23 | 3.17.0 | | -| Fedora Rawhide | 1.0.23 | 3.17.0 | | named `libusbx`, but `libusb`-codebase is used | -| KaOS | 1.0.23 | 3.17.0 | | -| OpenMandriva Cooker | 1.0.23 | 3.17.0 | | -| PCLinuxOS | 1.0.23 | 3.17.0 | | named `lib64usb1.0_0-1.0.23-1pclos2019.x86_64` | -| Slackware Current | 1.0.23 | 3.17.0 | | -| Solus | 1.0.23 | 3.16.5 | | +| Alpine Edge | 1.0.23 | 3.17.0 | 3.24.18
    gtk+3.0-dev | | +| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | 3.24.18
    libgtk+3-devel | | +| Arch Linux | 1.0.23 | 3.17.0 | 3.24.18
    gtk3 | | +| Fedora Rawhide | 1.0.23 | 3.17.0 | 3.24.18
    gtk3-devel | | named `libusbx`, but
    `libusb`-codebase is used | +| KaOS | 1.0.23 | 3.17.0 | 3.24.18
    gtk3 | | +| OpenMandriva Cooker | 1.0.23 | 3.17.0 | 3.24.18
    libgtk+3.0-devel
    lib64gtk+3.0-devel | | +| PCLinuxOS | 1.0.23
    lib64usb1.0 | 3.17.0 | 3.24.18
    lib64gtk+3.0-devel | | +| Slackware Current | 1.0.23 | 3.17.0 | 3.24.18
    gtk+3 | | +| Solus | 1.0.23 | 3.16.5 | 3.24.16
    libgtk-3-devel | | | Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
    libgtk-3-dev | | -| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | | +| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | 3.24.13
    libgtk+3.0-devel
    lib64gtk+3.0-devel | | | Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
    libgtk-3-dev | | -| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | | -| Alpine 3.11 | 1.0.23 | 3.15.5 | | +| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | 3.24.16
    gtk3-devel | | +| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.13
    gtk+3.0-dev | | | Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
    libgtk-3-dev | | -| Mageia Cauldron | 1.0.22 | 3.17.0 | | -| NetBSD 9.0 | 1.0.22 | 3.16.1 | | -| NetBSD 8.1 | 1.0.22 | 3.16.1 | | -| NetBSD 7.2 | 1.0.22 | 3.16.1 | | -| Alpine 3.10 | 1.0.22 | 3.14.5 | | -| Fedora 31 | 1.0.22 | 3.14.5 | | named `libusbx`, but `libusb`-codebase is used | -| Mageia 7.1 | 1.0.22 | 3.14.3 | | -| Fedora 30 | 1.0.22 | 3.14.2 | | named `libusbx`, but `libusb`-codebase is used | +| Mageia Cauldron | 1.0.22 | 3.17.0 | 3.24.18
    libgtk+3.0-devel
    lib64gtk+3.0-devel | | +| NetBSD 9.0 | 1.0.22 | 3.16.1 | 3.24.12
    gtk+3 | | +| NetBSD 8.1 | 1.0.22 | 3.16.1 | 3.24.12
    gtk+3 | | +| NetBSD 7.2 | 1.0.22 | 3.16.1 | _N/A_ | | +| Alpine 3.10 | 1.0.22 | 3.14.5 | 3.24.8
    gtk+3.0-dev | | +| Fedora 31 | 1.0.22 | 3.14.5 | 3.24.12
    gtk3-devel | named `libusbx`, but
    `libusb`-codebase is used | +| Mageia 7.1 | 1.0.22 | 3.14.3 | 3.24.8
    libgtk+3.0-devel
    lib64gtk+3.0-devel | | +| Fedora 30 | 1.0.22 | 3.14.2 | 3.24.8
    gtk3-devel | named `libusbx`, but
    `libusb`-codebase is used | | Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
    libgtk-3-dev | | -| Alpine 3.9 | 1.0.22 | 3.13.0 | | -| CentOS 8 | 1.0.22 | 3.11.4 | | named `libusbx`, but `libusb`-codebase is used | -| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | | -| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | | +| Alpine 3.9 | 1.0.22 | 3.13.0 | 3.24.1
    gtk+3.0-dev | | +| CentOS 8 | 1.0.22 | 3.11.4 | 3.22.30
    gtk3-devel | named `libusbx`, but
    `libusb`-codebase is used | +| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | 3.24.14
    gtk3-devel | | +| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | 3.22.30
    gtk3-devel | | | Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
    libgtk-3-dev | | | Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
    libgtk-3-dev | | -| Slackware 14.2 | **1.0.20** | 3.5.2 | | +| Slackware 14.2 | **1.0.20** | 3.5.2 | 3.18.9
    gtk+3 | | | Ubuntu 16.04 LTS (Xenial Xerus) | **1.0.20** | 3.5.1 | 3.18.9
    libgtk-3-dev | | -| OpenMandriva Lx 3.0 | **1.0.20** | **3.4.2** | | -| FreeBSD 13 | **1.0.16** - 1.0.18 | 3.15.5 | | linux_libusb-13.0r358841 (integrated) | -| FreeBSD 12 | **1.0.16** - 1.0.18 | 3.15.5 | | linux_libusb-11.0r261448_4 (integrated) | -| FreeBSD 11 | **1.0.16** - 1.0.18 | 3.15.5 | | linux_libusb-11.0r261448_4 (integrated) | +| OpenMandriva Lx 3.0 | **1.0.20** | **3.4.2** | 3.18.9
    libgtk+3.0-devel
    lib64gtk+3.0-devel | | +| FreeBSD 13 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
    gtk3 | linux_libusb-13.0r358841
    (integrated) | +| FreeBSD 12 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
    gtk3 | linux_libusb-11.0r261448_4
    (integrated) | +| FreeBSD 11 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
    gtk3 | linux_libusb-11.0r261448_4
    (integrated) | -## Unsupported Operating Systems as of Release 1.6.1 (2020) +## Unsupported Operating Systems (as of Release v1.6.1) | Operating System | libusb
    version | cmake
    version | End of OS-Support | Notes | | --- | --- | --- | --- | --- | From 68fdd3927d9e2ae9fce662458d2be530832c946f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 18 Apr 2020 16:45:05 +0200 Subject: [PATCH 0841/1435] Reconfigured cmake packaging - Refactoring for package config & build - deb-pkg: postinst script with depmod -a (Fixes #845) --- CHANGELOG.md | 2 +- CMakeLists.txt | 60 +++-- Makefile | 11 +- cmake/cpack_config.cmake | 27 --- cmake/linux-mingw32.cmake | 25 -- cmake/linux-mingw64.cmake | 25 -- .../{Find7zip.cmake => Find_7zip.cmake} | 3 +- .../{Findlibusb.cmake => Find_libusb.cmake} | 6 +- cmake/{ => modules}/c_flags.cmake | 12 +- .../get_version.cmake} | 0 cmake/packaging/CMakeLists.txt | 4 + cmake/packaging/cpack_config.cmake | 85 +++++++ cmake/packaging/debian/CMakeLists.txt | 0 cmake/packaging/debian/changelog | 226 ++++++++++++++++++ {debian => cmake/packaging/debian}/copyright | 0 cmake/packaging/debian/postinst | 4 + cmake/packaging/fedora/CMakeLists.txt | 0 cmake/packaging/opensuse/CMakeLists.txt | 0 cmake/packaging/windows/CMakeLists.txt | 0 debian/changelog | 129 ---------- debian/pkg-config/CMakeLists.txt | 26 +- src/stlink-gui/CMakeLists.txt | 2 +- 22 files changed, 385 insertions(+), 262 deletions(-) delete mode 100644 cmake/cpack_config.cmake delete mode 100644 cmake/linux-mingw32.cmake delete mode 100644 cmake/linux-mingw64.cmake rename cmake/modules/{Find7zip.cmake => Find_7zip.cmake} (91%) rename cmake/modules/{Findlibusb.cmake => Find_libusb.cmake} (99%) rename cmake/{ => modules}/c_flags.cmake (88%) rename cmake/{version.cmake => modules/get_version.cmake} (100%) create mode 100644 cmake/packaging/CMakeLists.txt create mode 100644 cmake/packaging/cpack_config.cmake create mode 100644 cmake/packaging/debian/CMakeLists.txt create mode 100644 cmake/packaging/debian/changelog rename {debian => cmake/packaging/debian}/copyright (100%) create mode 100644 cmake/packaging/debian/postinst create mode 100644 cmake/packaging/fedora/CMakeLists.txt create mode 100644 cmake/packaging/opensuse/CMakeLists.txt create mode 100644 cmake/packaging/windows/CMakeLists.txt delete mode 100644 debian/changelog diff --git a/CHANGELOG.md b/CHANGELOG.md index 9c6060434..d0b920f71 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -258,7 +258,7 @@ Updates and fixes: * Fixed "unaligned addr or size" when trying to write a program in RAM ([#323](https://github.com/stlink-org/stlink/pull/323)) * Fixed flashing on STM32_F3_SMALL ([#325](https://github.com/stlink-org/stlink/pull/325)) -* Fixed STM32L-problem with flash loader ([#390](https://github.com/stlink-org/stlink/pull/390), [#407](https://github.com/stlink-org/stlink/pull/407),[#408](https://github.com/stlink-org/stlink/pull/408)) +* Fixed STM32L-problem with flash loader ([#390](https://github.com/stlink-org/stlink/pull/390), [#407](https://github.com/stlink-org/stlink/pull/407), [#408](https://github.com/stlink-org/stlink/pull/408)) * Don't read the target voltage on startup, because it crashes STM32F100 ([#423](https://github.com/stlink-org/stlink/pull/423), [#424](https://github.com/stlink-org/stlink/pull/424)) * Added a useful error message instead of "[!] send_recv" ([#425](https://github.com/stlink-org/stlink/pull/425), [#426](https://github.com/stlink-org/stlink/pull/426)) * Do a JTAG reset prior to reading CPU information when processor is in deep sleep ([#428](https://github.com/stlink-org/stlink/pull/428), [#430](https://github.com/stlink-org/stlink/pull/430), [#451](https://github.com/stlink-org/stlink/pull/451)) diff --git a/CMakeLists.txt b/CMakeLists.txt index e8da6c45c..ccb5fefa9 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,8 +1,21 @@ +### +# General cmake settings +### + cmake_minimum_required(VERSION 3.4.2) cmake_policy(SET CMP0042 NEW) set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") +set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) +set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) + +# Define GNU standard installation directories include(GNUInstallDirs) + +### +# General project settings +### + project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics ST-LINK Tools") @@ -14,10 +27,23 @@ option(STLINK_INSTALL_UDEV_RULES "Install udev rules files" ON) option(STLINK_INSTALL_MODPROBE_CONF "Install modprobe conf files" ON) option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) +# Determine project version +include(${CMAKE_MODULE_PATH}/get_version.cmake) + +# Set C build flags +if (NOT MSVC) + include(${CMAKE_MODULE_PATH}/c_flags.cmake) +else () + message(STATUS "MSVC C Flags override to /MT") + set(CMAKE_C_FLAGS_DEBUG_INIT "/D_DEBUG /MTd /Zi /Ob0 /Od /RTC1") + set(CMAKE_C_FLAGS_MINSIZEREL_INIT "/MT /O1 /Ob1 /D NDEBUG") + set(CMAKE_C_FLAGS_RELEASE_INIT "/MT /O2 /Ob2 /D NDEBUG") + set(CMAKE_C_FLAGS_RELWITHDEBINFO_INIT "/MT /Zi /O2 /Ob1 /D NDEBUG") +endif () + + # ==== -#set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) -#set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) #set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) if (IS_DIRECTORY ${LIB_INSTALL_DIR}) @@ -36,24 +62,12 @@ else () set(STLINK_INCLUDE_PATH "${CMAKE_INSTALL_PREFIX}/${INCLUDE_INSTALL_DIR}") endif () -include(cmake/version.cmake) - -if (NOT MSVC) - include(cmake/c_flags.cmake) -else () - message(STATUS "MSVC C Flags override to /MT") - set(CMAKE_C_FLAGS_DEBUG_INIT "/D_DEBUG /MTd /Zi /Ob0 /Od /RTC1") - set(CMAKE_C_FLAGS_MINSIZEREL_INIT "/MT /O1 /Ob1 /D NDEBUG") - set(CMAKE_C_FLAGS_RELEASE_INIT "/MT /O2 /Ob2 /D NDEBUG") - set(CMAKE_C_FLAGS_RELWITHDEBINFO_INIT "/MT /Zi /O2 /Ob1 /D NDEBUG") -endif () - ### # Dependencies ### -find_package(libusb REQUIRED) +find_package(_libusb REQUIRED) if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) find_package(PkgConfig) @@ -243,17 +257,21 @@ add_subdirectory(src/stlink-gui) # Others ### -add_subdirectory(debian/pkg-config) add_subdirectory(include) ### TODO: Check path add_subdirectory(doc/man) add_subdirectory(tests) -include(cmake/cpack_config.cmake) -include(CPack) - # ==== +### +# Package build +### + +add_subdirectory(cmake/packaging) +include(cmake/packaging/cpack_config.cmake) + + ### # Uninstall target ### @@ -261,11 +279,11 @@ include(CPack) if (NOT TARGET uninstall) configure_file( "${CMAKE_CURRENT_SOURCE_DIR}/cmake_uninstall.cmake.in" - "${CMAKE_CURRENT_BINARY_DIR}/cmake_uninstall.cmake" + "${CMAKE_CURRENT_BINARY_DIR}/cmake/cmake_uninstall.cmake" IMMEDIATE @ONLY ) add_custom_target( uninstall COMMAND ${CMAKE_COMMAND} - -P ${CMAKE_CURRENT_BINARY_DIR}/cmake_uninstall.cmake + -P ${CMAKE_CURRENT_BINARY_DIR}/cmake/cmake_uninstall.cmake ) endif () diff --git a/Makefile b/Makefile index 6b44bd70c..c3bd59c52 100644 --- a/Makefile +++ b/Makefile @@ -18,7 +18,6 @@ help: rebuild_cache: build/Debug build/Release @$(MAKE) -C build/Debug rebuild_cache @$(MAKE) -C build/Release rebuild_cache - @$(MAKE) -C build/Binary rebuild_cache debug: build/Debug @echo "[DEBUG]" @@ -28,10 +27,6 @@ release: build/Release @echo "[RELEASE]" @$(MAKE) -C build/Release -binary: build/Binary - @echo "[BINARY]" - @$(MAKE) -C build/Binary - package: build/Release @echo "[PACKAGE] Release" @$(MAKE) -C build/Release package @@ -45,11 +40,7 @@ build/Debug: build/Release: @mkdir -p $@ - @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Release $(CMAKEFLAGS) ../../ - -build/Binary: - @mkdir -p $@ - @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Binary $(CMAKEFLAGS) ../../ + @cd $@ && cmake -DCMAKE_BUILD_TYPE=Release $(CMAKEFLAGS) -Wno-dev ../../ clean: @echo "[CLEAN]" diff --git a/cmake/cpack_config.cmake b/cmake/cpack_config.cmake deleted file mode 100644 index c70cf3a63..000000000 --- a/cmake/cpack_config.cmake +++ /dev/null @@ -1,27 +0,0 @@ -set(CPACK_PACKAGE_NAME ${PROJECT_NAME}) -set(CPACK_PACKAGE_VERSION ${PROJECT_VERSION}) -set(CPACK_SET_DESTDIR "ON") - -if (APPLE) - set(CPACK_GENERATOR "ZIP") - set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-macosx-amd64") - file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/osx") - set(CPACK_INSTALL_PREFIX "") - set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/osx") -elseif (WIN32) - set(CPACK_GENERATOR "ZIP") - file(MAKE_DIRECTORY "${CMAKE_BINARY_DIR}/dist/windows") - set(CPACK_INSTALL_PREFIX "") - set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist/windows") -elseif (${CMAKE_SYSTEM_NAME} STREQUAL "Linux" AND EXISTS "/etc/debian_version") - message(STATUS "Debian-based Linux OS detected") - set(CPACK_GENERATOR "DEB") - if ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "x86_64") - set(CPACK_PACKAGE_FILE_NAME "${CPACK_PACKAGE_NAME}-${PROJECT_VERSION}-amd64" ) - endif () - - set(CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/stlink-org/stlink") - set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Luca Boccassi") - set(CPACK_PACKAGE_CONTACT "bluca@debian.org") - set(CPACK_DEBIAN_PACKAGE_DESCRIPTION "STM32 STlink programmer tools") -endif () diff --git a/cmake/linux-mingw32.cmake b/cmake/linux-mingw32.cmake deleted file mode 100644 index 2b4799037..000000000 --- a/cmake/linux-mingw32.cmake +++ /dev/null @@ -1,25 +0,0 @@ -# Sample toolchain file for building for Windows from a Debian/Ubuntu Linux system. -# -# Typical usage: -# *) install cross compiler: `sudo apt-get install mingw-w64` -# *) cd build -# *) cmake -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake .. - -set(CMAKE_SYSTEM_NAME Windows) -set(TOOLCHAIN_PREFIX i686-w64-mingw32) - -# cross compilers to use for C and C++ -set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}-gcc) -set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}-g++) -set(CMAKE_RC_COMPILER ${TOOLCHAIN_PREFIX}-windres) - -# target environment on the build host system -# set 1st to dir with the cross compiler's C/C++ headers/libs -set(CMAKE_FIND_ROOT_PATH /usr/${TOOLCHAIN_PREFIX}) - -# modify default behavior of FIND_XXX() commands to -# search for headers/libs in the target environment and -# search for programs in the build host environment -set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) -set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) diff --git a/cmake/linux-mingw64.cmake b/cmake/linux-mingw64.cmake deleted file mode 100644 index f8b523965..000000000 --- a/cmake/linux-mingw64.cmake +++ /dev/null @@ -1,25 +0,0 @@ -# Sample toolchain file for building for Windows from a Debian/Ubuntu Linux system. -# -# Typical usage: -# *) install cross compiler: `sudo apt-get install mingw-w64` -# *) cd build -# *) cmake -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw64.cmake .. - -set(CMAKE_SYSTEM_NAME Windows) -set(TOOLCHAIN_PREFIX x86_64-w64-mingw32) - -# cross compilers to use for C and C++ -set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}-gcc) -set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}-g++) -set(CMAKE_RC_COMPILER ${TOOLCHAIN_PREFIX}-windres) - -# target environment on the build host system -# set 1st to dir with the cross compiler's C/C++ headers/libs -set(CMAKE_FIND_ROOT_PATH /usr/${TOOLCHAIN_PREFIX}) - -# modify default behavior of FIND_XXX() commands to -# search for headers/libs in the target environment and -# search for programs in the build host environment -set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) -set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) -set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) diff --git a/cmake/modules/Find7zip.cmake b/cmake/modules/Find_7zip.cmake similarity index 91% rename from cmake/modules/Find7zip.cmake rename to cmake/modules/Find_7zip.cmake index 0ccd23a50..c75cf1150 100644 --- a/cmake/modules/Find7zip.cmake +++ b/cmake/modules/Find_7zip.cmake @@ -1,7 +1,6 @@ -# Find7zip.cmake +# Find_7zip.cmake # Detect 7zip file archiver on Windows systems to extract (zip-)archives - find_program( ZIP_EXECUTABLE NAMES 7z.exe p7zip HINTS "C:\\Program Files\\7-Zip\\" "C:\\Program Files (x86)\\7-Zip\\" diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Find_libusb.cmake similarity index 99% rename from cmake/modules/Findlibusb.cmake rename to cmake/modules/Find_libusb.cmake index 5b3e80fe6..e46c6d46e 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Find_libusb.cmake @@ -1,4 +1,4 @@ -# Findlibusb.cmake +# Find_libusb.cmake # Once done this will define # # LIBUSB_FOUND libusb present on system @@ -75,7 +75,9 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND ${CMAKE_BUILD_TYPE} MATCHES " if (NOT LIBUSB_FOUND OR EXISTS "/etc/debian_version") # Preparations for installing libusb library - find_package(7zip REQUIRED) + + find_package(_7zip REQUIRED) + set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) diff --git a/cmake/c_flags.cmake b/cmake/modules/c_flags.cmake similarity index 88% rename from cmake/c_flags.cmake rename to cmake/modules/c_flags.cmake index c7954bf54..d6b12403b 100644 --- a/cmake/c_flags.cmake +++ b/cmake/modules/c_flags.cmake @@ -34,17 +34,17 @@ add_cflag_if_supported("-Wimplicit-function-declaration") # /usr/include/sys/types.h:218: warning: previous declaration of 'truncate' was here ## if (NOT CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") - add_cflag_if_supported("-Wredundant-decls") + add_cflag_if_supported("-Wredundant-decls") endif () if (NOT WIN32) - add_cflag_if_supported("-fPIC") + add_cflag_if_supported("-fPIC") endif () if (${CMAKE_BUILD_TYPE} MATCHES "Debug") - add_cflag_if_supported("-ggdb") - add_cflag_if_supported("-O0") -else() - add_cflag_if_supported("-O2") + add_cflag_if_supported("-ggdb") + add_cflag_if_supported("-O0") +else () + add_cflag_if_supported("-O2") add_cflag_if_supported("-Werror") endif () diff --git a/cmake/version.cmake b/cmake/modules/get_version.cmake similarity index 100% rename from cmake/version.cmake rename to cmake/modules/get_version.cmake diff --git a/cmake/packaging/CMakeLists.txt b/cmake/packaging/CMakeLists.txt new file mode 100644 index 000000000..e831f611f --- /dev/null +++ b/cmake/packaging/CMakeLists.txt @@ -0,0 +1,4 @@ +add_subdirectory(debian) +add_subdirectory(fedora) +add_subdirectory(opensuse) +add_subdirectory(windows) diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake new file mode 100644 index 000000000..522fb7f11 --- /dev/null +++ b/cmake/packaging/cpack_config.cmake @@ -0,0 +1,85 @@ +### +# Configure package +### + +set(CPACK_PACKAGE_NAME ${PROJECT_NAME}) +set(CPACK_PACKAGE_VERSION ${PROJECT_VERSION}) +set(CPACK_SET_DESTDIR "ON") +set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist") + +if (APPLE) + set(CPACK_GENERATOR "ZIP") + set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-macosx-amd64") + set(CPACK_INSTALL_PREFIX "") +elseif (WIN32) ### TODO: Binary build config for windows... + set(CPACK_GENERATOR "ZIP") + set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-win32") + set(CPACK_INSTALL_PREFIX "") + + # Sample toolchain file for building for Windows from a Debian/Ubuntu Linux system. + # Typical usage: + # *) install cross compiler: `sudo apt-get install mingw-w64` + # *) cd build + # *) cmake -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw64.cmake .. + # *) cmake -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake .. + + #set(CMAKE_SYSTEM_NAME Windows) + #set(TOOLCHAIN_PREFIX x86_64-w64-mingw32) + #set(TOOLCHAIN_PREFIX i686-w64-mingw32) + + # cross compilers to use for C and C++ + #set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}-gcc) + #set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}-g++) + #set(CMAKE_RC_COMPILER ${TOOLCHAIN_PREFIX}-windres) + + # target environment on the build host system + # set 1st to dir with the cross compiler's C/C++ headers/libs + #set(CMAKE_FIND_ROOT_PATH /usr/${TOOLCHAIN_PREFIX}) + + # modify default behavior of FIND_XXX() commands to + # search for headers/libs in the target environment and + # search for programs in the build host environment + #set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) + #set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) + #set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + +elseif (${CMAKE_SYSTEM_NAME} STREQUAL "Linux" AND EXISTS "/etc/debian_version") + message(STATUS "Debian-based Linux OS detected") + + ### Debian-specific + set(CPACK_GENERATOR "DEB") + set(CPACK_DEBIAN_PACKAGE_DESCRIPTION "Open source STM32 MCU programming toolset") + set(CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/stlink-org/stlink") + set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Luca Boccassi") + set(CPACK_PACKAGE_CONTACT "bluca@debian.org") + + ## Set debian_revision number + # Convention: Restart the debian_revision at 1 each time the upstream_version is increased. + set(CPACK_DEBIAN_PACKAGE_RELEASE "0") + + ## Debian package name + # CPack DEB generator generates package file name in deb format: + # _-_.deb + set(CPACK_DEBIAN_FILE_NAME DEB-DEFAULT) + + ## Add CHANGELOG in Debian-specific format + ### TODO + + ## Add license file + ### TODO + + # Include a postinst-script + set(CPACK_DEBIAN_PACKAGE_CONTROL_EXTRA "${CMAKE_SOURCE_DIR}/cmake/packaging/debian/postinst") + + ### rpm-specific ### TODO: Package config for opensuse should go here... + +else () + ### TODO: Package config for fedora should go here... +endif () + + +### +# Build package +### + +include(CPack) diff --git a/cmake/packaging/debian/CMakeLists.txt b/cmake/packaging/debian/CMakeLists.txt new file mode 100644 index 000000000..e69de29bb diff --git a/cmake/packaging/debian/changelog b/cmake/packaging/debian/changelog new file mode 100644 index 000000000..b4e942d7c --- /dev/null +++ b/cmake/packaging/debian/changelog @@ -0,0 +1,226 @@ +stlink (1.6.0) unstable; urgency=medium + +Release date: 2020-02-20 + +Major changes and added features: + +* Initial support for STM32L41X +* Working support for CKS32F103C8T6 and related CKS devices with Core-ID 0x2ba01477 +* Added preliminary support for some STM32G0 chips +* Added support for mass erasing second bank on STM32F10x_XL +* Added call to clear PG bit after writing to flash +* Added support to write option bytes for the STM32G0 +* Added support for STM32WB55 chips +* Added STLink V3SET VID:PIDs to the udev rules +* Support for "STM32+Audio" v2-1 firmware +* Build for Windows under Debian/Ubuntu +* Allow for 64 bytes serials +* Added full support for STLINK CHIP ID L4RX +* Added support for the STLink-v2.1 when flashed with no mass storage (PID 0x3752) +* Added support for writing option bytes on STM32L0xx +* Added support to read and write option bytes for STM32F2 series +* Added support to read and write option bytes for STM32F446 + +Updates and fixes: + +* Fixed "unkown chip id", piped output and st-util -v +* Fixed an issue with versioning stuck at 1.4.0 for versions cloned with git +* Updated STM32F3xx chip ID that covers a few different devices +* Made udev rules and modprobe conf installation optional +* Fixed case when __FILE__ don't contain "/" nor "\\" +* Fixed double dash issue in doc/man +* Compiling documentation: package is called libusb-1.0-0-dev on Debian +* Only do bank calculation on STM32L4 devices with dual banked flash / Added chip-ID 0x464 for STM32L41xxx/L42xxx devices +* Added O_BINARY option to open file +* Fixed versioning when compiling from the checked out git-repo +* win32: move usleep definition to unistd.h +* Fixed relative path to the UI files needed by stlink-gui-local (GUI) +* Added howto for sending NRST signal through GDB +* Fixed package name "devscripts" in doc/compiling.md +* Fixed few potential memory/resource leaks +* Updated Linux source repositories in README.md: Debian and Ubuntu +* Do not issue JTAG reset on stlink-v1 +* Fixed flash size of STM32 Discovery vl +* Updated documentation on software structure + +General project updates: + +* Updated README.md, CHANGELOG.md and issue templates +* Fixed travis build config file +* Added CODE_OF_CONDUCT +* Archived page from github project wiki to doc/wiki_old.md + +-- Luca Boccassi Tue, 25 Feb 2020 22:08:33 +0000 + + +stlink (1.5.1) unstable; urgency=medium + +Release date: 2018-09-13 + +Major changes and added features: + +* Added reset through AIRCR +* Added creation of icons for .desktop file +* Added desktop file for linux +* Added button to export STM32 flash memory to a file +* Updated libusb to 1.0.22 +* Added icons for STLink GUI +* Added support for STM32L4R9 target +* Added memory map for STM32F411RE target +* Implemented intel hex support for GTK GUI + +Updates and fixes: + +* Fixed missing flash_loader for STM32L0x +* Fix for stlink library calls exit() or _exit() +* Added semihosting parameter documentation in doc/man +* Fixed reference to non-exisiting st-term tool in doc/man +* Fixed serial number size mismatch with stlink_open_usb() +* Debian packaging, CMake and README.md fixes +* Disabled static library installation by default +* Fix for libusb deprecation +* Renamed STLINK_CHIPID_STM32_L4R9 to STLINK_CHIPID_STM32_L4RX +* Regression: stlink installation under Linux (Debian 9) is broken since #695 +* Fixed flash memory map for STM32F72xxx target +* Proper flash page size calculation for STM32F412xx target +* Return correct value on EOF for Semihosting SYS_READ +* FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION + +-- Luca Boccassi Fri, 28 Sep 2018 10:26:39 +0100 + + +stlink (1.5.0) unstable; urgency=medium + +Release date: 2018-02-16 + +Major changes and added features: + +* Added support of STM32L496xx/4A6xx devices +* Added unknown chip dummy to obtain the serial of the ST-link by a call to st-info --probe +* Added support for STM32F72xx (chip-ID: 0x452) devices + +Updates and fixes: + +* Fixed verification of flash error for STM32L496x device +* Updated Linux source repositories in README.md: Gentoo, Fedora and RedHat/CentOS +* Updated changelog in debian package +* Added LIB_INSTALL_DIR to correct libs install on 64-bit systems +* Fixed write for microcontroller with RAM size less or equal to 32K +* Fixed memory map for STM32L496xx boards +* Fixed __FILE__ base name extraction +* Added debian/triggers to run ldconfig +* Fixed build on Fedora with GCC 8 + +-- Luca Boccassi Fri, 16 Mar 2018 16:56:17 +0000 + + +stlink (1.4.0) unstable; urgency=low + +Release date: 2017-07-01 + +Major changes and added features: + +* Allow building of debian package with CPack +* Added support for STM32L011 target +* Added support for flashing second bank on STM32F10x_XL +* Initial support to compile with Microsoft Visual Studio 2017 +* Added support for STM32L452 target + +Updates and fixes: + +* Fixed gdb-server: STM32L0xx has no FP_CTRL register for breakpoints +* Added --flash=n[k][m] command line option to override device model +* Updated libusb to 1.0.21 for Windows +* Fixed low-voltage flashing on STM32F7 devices +* Fixed building with mingw64 +* Fixed possible memory leak +* Fixed installation path for shared objects +* Fixed a few -Wformat warnings +* Removed unused defines in mimgw.h +* Skip GTK detection when cross-compiling +* Fixed compilation with GCC 7 +* Fixed flashing to 'f0 device' targets +* Fixed wrong counting when flashing + +-- Andrew 'Necromant' Andrianov Sat, 01 Jul 2017 00:00:00 +0000 + + +stlink (1.3.1) unstable; urgency=low + +Release date: 2017-02-25 + +Major changes and added features: + +* Added support for Semihosting `SYS_READC` +* Added support for STM32F413 +* Added preliminary support for STM32L011 to see it after probe (chip-ID 0x457) + +Updates and fixes: + +* cmake/CPackConfig.cmake: Fixup OSX zip filename +* Updated source repositories in README.md: Windows, macOS, Alpine Linux +* Compilation fixes +* Stripped full paths to source files in log +* Fixed incorrect release folder name in docs +* Fixed compilation when path includes spaces + +-- Andrew 'Necromant' Andrianov Sat, 25 Feb 2017 00:00:00 +0000 + + +stlink (1.3.0) unstable; urgency=low + +Release date: 2017-01-28 + +Major changes and added features: + +* Deprecation of autotools (autoconf, automake) and fixed build with MinGW +* Added intel hex file reading for `st-flash` +* Added support for ARM semihosting to `st-util` +* Added manpages (generated with pandoc from Markdown) +* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature +* Support serial numbers argument for `st-util` and `st-flash` to probe and control multiple connected programmers +* Merge st-probe tool into st-info +* Added support for native debian packaging +* Rewritten commandline parsing for `st-flash` +* Added `--reset` command to `st-flash` +* st-util should detect when USB commands fail + +Chip support added for: + +* STM32F401XE: Added memory map for device +* STM32F410RBTx +* STM32F412 +* STM32F7xx +* STM32F7x7x +* STM32L0xx Cat2 devices (chip-ID: 0x425) +* STM32L0xx Cat5 devices (chip-ID: 0x447) +* STM32L4xx +* STM32L432 + +Updates and fixes: + +* Fixed "unaligned addr or size" when trying to write a program in RAM +* Fixed flashing on STM32_F3_SMALL +* Fixed STM32L-problem with flash loader +* Don't read the target voltage on startup, because it crashes STM32F100 +* Added a useful error message instead of "[!] send_recv" +* Do a JTAG reset prior to reading CPU information when processor is in deep sleep +* Fixed STM32F030 erase error +* Fixed memory map for STM32F7xx +* Redesign of `st-flash` commandline options parsing +* Set SWDCLK and fixed jtag_reset bug +* doc/compiling.md: Add note about installation and ldconfig +* Fixed Release target to generate the man-pages with pandoc +* Fixed Cygwin build +* Reset flash mass erase (MER) bit after mass erase for safety +* Wrong extract command in FindLibUSB.cmake +* Fixed compilation error on Ubuntu 16.10 + +-- Andrew 'Necromant' Andrianov Sat, 28 Jan 2017 00:00:00 +0000 + + +libstlink (1.2.1) unstable; urgency=low + +* Initial Debian-packaged release. + +-- Andrew 'Necromant' Andrianov Sat, 09 Jul 2016 23:16:07 +0300 diff --git a/debian/copyright b/cmake/packaging/debian/copyright similarity index 100% rename from debian/copyright rename to cmake/packaging/debian/copyright diff --git a/cmake/packaging/debian/postinst b/cmake/packaging/debian/postinst new file mode 100644 index 000000000..bc74428ae --- /dev/null +++ b/cmake/packaging/debian/postinst @@ -0,0 +1,4 @@ +#!/bin/bash +# This `DEBIAN/postinst` script is run post-installation + +depmod -a diff --git a/cmake/packaging/fedora/CMakeLists.txt b/cmake/packaging/fedora/CMakeLists.txt new file mode 100644 index 000000000..e69de29bb diff --git a/cmake/packaging/opensuse/CMakeLists.txt b/cmake/packaging/opensuse/CMakeLists.txt new file mode 100644 index 000000000..e69de29bb diff --git a/cmake/packaging/windows/CMakeLists.txt b/cmake/packaging/windows/CMakeLists.txt new file mode 100644 index 000000000..e69de29bb diff --git a/debian/changelog b/debian/changelog deleted file mode 100644 index ac18fd872..000000000 --- a/debian/changelog +++ /dev/null @@ -1,129 +0,0 @@ -stlink (1.5.0) unstable; urgency=medium - - [ Jerry Jacobs ] - * README.md: Update version badge to v1.4.0 - - [ Viallard Anthony ] - * Add support of STM32L496xx/4A6xx devices (#615) - - [ rdlim ] - * Fix verification of flash error for STM32L496x device (#617) (#618) - - [ dflogeras ] - * Add note about availability in Gentoo package manager (#622) - - [ yaofei zheng ] - * update debian package version (#630) - - [ Lyle Cheatham ] - * Minor formatting fix in FAQ section of README.md (#631) - - [ Vasiliy Glazov ] - * README.md: Added information about Fedora and RedHat/CentOS packages. - (#635) - * Added LIB_INSTALL_DIR to correct libs install on 64-bit systems (#636) - - [ Gwenhael Goavec-Merou ] - * fix write for microcontroler with RAM size less or equal to 32K (#637) - - [ Mateusz Krawiec ] - * Fix memory map for stm32l496xx boards. (#639) - - [ Rüdiger Fortanier ] - * Add unknown chip output (#641) - - [ Slyshyk Oleksiy ] - * fix __FILE__ base name extraction, #628 (#648) - - [ texane ] - * STM32F72xx73xx support, from bob.feretich@rafresearch.com - - [ Kirill Kolyshkin ] - * debian/triggers: add (to run ldconfig) (#664) - - [ Slyshyk Oleksiy ] - * Try to fix #666 issue (#667) - * Try to fix 666 issue (#668) - - [ Jerry Jacobs ] - * Update ChangeLog.md - * Update README.md - - [ texane ] - * STM32F042K6 Nucleo-32 Board reported to work, by frank@bauernoeppel.de - - [ Anatol Pomozov ] - * Update .version file to match release number (#670) - - -- Anatol Pomozov Mon, 19 Feb 2018 11:00:29 -0800 - -libstlink (1.4.0) unstable; urgency=low - - * Major changes and added features - - Add support for STM32L452 target (#608) - - Initial support to compile with Microsoft Visual Studio 2017 (#602) - - Added support for flashing second bank on STM32F10x_XL (#592) - - Add support for STM32L011 target (#572) - - Allow building of debian package with CPack (@xor-gate) - * Updates and fixes - - Fix compilation with GCC 7 (#590) - - Skip GTK detection if we're cross-compiling (#588) - - Fix possible memory leak (#570) - - Fix building with mingw64 (#569, #610) - - Update libusb to 1.0.21 for Windows (#562) - - Fixing low-voltage flashing on STM32F7 parts. (#567) - - Update libusb to 1.0.21 for Windows (#562) - - -- Andrew 'Necromant' Andrianov Sat, 01 Jul 2017 00:00:00 +0000 - -libstlink (1.3.1) unstable; urgency=low - - * Major changes and added features: - - Add preliminary support for STM32L011 to see it after probe (chipid 0x457) (@xor-gate) - - Strip full paths to source files in log (commit #2c0ab7f) - - Add support for STM32F413 target (#549) - - Add support for Semihosting SYS_READC (#546) - * Updates and fixes: - - Update documentation markdown files - - Compilation fixes (#552) - - Fix compilation when path includes spaces (#561) - - -- Andrew 'Necromant' Andrianov Sat, 25 Feb 2017 00:00:00 +0000 - -libstlink (1.3.0) unstable; urgency=low - - * Major changes and added features: - - Deprecation of autotools (autoconf, automake) (@xor-gate) - - Removal of undocumented st-term utility, which is now replaced by st-util ARM semihosting feature (#3fd0f09) - - Add support for native debian packaging (#444, #485) - - Add intel hex file reading for st-flash (#459) - - Add --reset command to st-flash (#505) - - Support serial numbers argument for st-util and st-flash for multi-programmer setups (#541) - - Add kill ('k') command to gdb-server for st-util (#9804416) - - Add manpages (generated with pandoc from Markdown) (#464) - - Rewrite commandline parsing for st-flash (#459) - - Add support for ARM semihosting to st-util (#454, #455) - * Chip support added for: - - STM32L432 (#501) - - STM32F412 (#538) - - STM32F410 (#9c635e4) - - Add memory map for STM32F401XE (#460) - - L0x Category 5 devices (#406) - - Add L0 Category 2 device (chip id: 0x425) (#72b8e5e) - * Updates and fixes: - - Fixed STM32F030 erase error (#442) - - Fixed Cygwin build (#68b0f3b) - - Reset flash mass erase (MER) bit after mass erase for safety (#489) - - Fix memory map for STM32F4 (@zulusw) - - Fix STM32L-problem with flash loader (issue #390) (Tom de Boer) - - st-util don't read target voltage on startup as it crashes STM32F100 (probably stlink/v1) (Greg Alexander) - - Do a JTAG reset prior to reading CPU information when processor is in deep sleep (@andyg24) - - Redesign of st-flash commandline options parsing (pull-request #459) (@dev26th) - - -- Andrew 'Necromant' Andrianov Sat, 28 Jan 2017 00:00:00 +0000 - -libstlink (1.2.1) unstable; urgency=low - - * Initial Debian-Packaged Release. - - -- Andrew 'Necromant' Andrianov Sat, 09 Jul 2016 23:16:07 +0300 diff --git a/debian/pkg-config/CMakeLists.txt b/debian/pkg-config/CMakeLists.txt index a31e27e50..fa3a326a8 100644 --- a/debian/pkg-config/CMakeLists.txt +++ b/debian/pkg-config/CMakeLists.txt @@ -1,15 +1,15 @@ -set(PKG_CONFIG_LIBDIR "\${prefix}/lib/\${deb_host_multiarch}") -set(PKG_CONFIG_INCLUDEDIR "\${prefix}/include/\${deb_host_multiarch}/${PROJECT_NAME}") -set(PKG_CONFIG_LIBS "-L\${libdir} -l:libstlink.so.${PROJECT_VERSION_MAJOR}") -set(PKG_CONFIG_CFLAGS "-I\${includedir}") -set(PKG_CONFIG_REQUIRES "libusb-1.0") +#set(PKG_CONFIG_LIBDIR "\${prefix}/lib/\${deb_host_multiarch}") +#set(PKG_CONFIG_INCLUDEDIR "\${prefix}/include/\${deb_host_multiarch}/${PROJECT_NAME}") +#set(PKG_CONFIG_LIBS "-L\${libdir} -l:libstlink.so.${PROJECT_VERSION_MAJOR}") +#set(PKG_CONFIG_CFLAGS "-I\${includedir}") +#set(PKG_CONFIG_REQUIRES "libusb-1.0") -configure_file( - "${CMAKE_CURRENT_SOURCE_DIR}/pkg-config.pc.cmake" - "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" - ) +#configure_file( +# "${CMAKE_CURRENT_SOURCE_DIR}/pkg-config.pc.cmake" +# "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" +# ) -install( - FILES "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" - DESTINATION ${STLINK_LIBRARY_PATH}/pkg-config/ - ) +#install( +# FILES "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" +# DESTINATION ${STLINK_LIBRARY_PATH}/debian/ +# ) diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index dee6cc258..74b71cecd 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -1,6 +1,6 @@ if (NOT GTK3_FOUND) message(STATUS "GTK3 not found!") - return() # no GTK3 present => no GUI build + return() # no GTK3 present => no GUI build else (GTK3_FOUND) message(STATUS "Found GTK3: -I${GTK3_INCLUDE_DIRS}, ${GTK3_LIBRARIES}") endif () From 1986173163cdff574abc3cadd30f59744731b6e3 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Sun, 12 Apr 2020 14:45:41 +0200 Subject: [PATCH 0842/1435] stlink_open_usb: load device param returning -1 is not an usb issue. do not abort in case of load device param "error" : this is supposed to return -1 if device is "unknown" or not detected, which is not reaaally an error. we want probe to tell us what is the connected device even if we can not operate it we want probe to tell us that it can not operate it, not to hide the connected stlink --- src/usb.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/usb.c b/src/usb.c index 206600f14..68c484ddd 100644 --- a/src/usb.c +++ b/src/usb.c @@ -1054,11 +1054,8 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST usleep(10000); } - ret = stlink_load_device_params(sl); - if (ret == -1) { - // This one didn't have any message. - goto on_libusb_error; - } + stlink_load_device_params(sl); + return sl; on_libusb_error: From 784ea36bdc3f0a71d67590a64424f2249e8e14cc Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Sun, 12 Apr 2020 16:06:15 +0200 Subject: [PATCH 0843/1435] usb.c: indent, make error use ELOG, and add trace --- src/usb.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/usb.c b/src/usb.c index 68c484ddd..c9ea7039a 100644 --- a/src/usb.c +++ b/src/usb.c @@ -1045,7 +1045,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { - stlink_enter_swd_mode(sl); + stlink_enter_swd_mode(sl); } if (reset) { @@ -1130,9 +1130,9 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { ret = libusb_open(dev, &handle); if (ret < 0) { if (ret == LIBUSB_ERROR_ACCESS) { - WLOG("failed to open USB device (LIBUSB_ERROR_ACCESS), try running as root?\n"); - } else { - WLOG("failed to open USB device (libusb error: %d)\n", ret); + ELOG("Could not open USB device %#06x:%#06x, access error.\n", desc.idVendor, desc.idProduct, ret); + } else { + ELOG("Failed to open USB device %#06x:%#06x, libusb error: %d)\n", desc.idVendor, desc.idProduct, ret); } break; } @@ -1146,8 +1146,10 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { } stlink_t *sl = stlink_open_usb(0, 1, serial); - if (!sl) + if (!sl) { + ELOG("Failed to open USB device %#06x:%#06x\n", desc.idVendor, desc.idProduct); continue; + } _sldevs[slcur++] = sl; } From 5aa001cfab6eb70e697691915c8754553bc83b92 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Sun, 12 Apr 2020 16:31:49 +0200 Subject: [PATCH 0844/1435] flash.c: stlink_open_usb can now return a sl with no, or unknown target. check flash type before attempting to continue flash operations --- src/tools/flash.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/tools/flash.c b/src/tools/flash.c index f39b6c6e4..a08581094 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -59,8 +59,14 @@ int main(int ac, char** av) sl = stlink_open_usb(o.log_level, 1, (char *)o.serial); - if (sl == NULL) + if (sl == NULL) { return -1; + } + + if (sl->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { + printf("Failed to connect to target\n"); + return -1; + } if ( o.flash_size != 0u && o.flash_size != sl->flash_size ) { sl->flash_size = o.flash_size; From 8f778b2e4c33d8e5916ea3f19bf4b06f50566537 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Thu, 16 Apr 2020 16:46:27 +0200 Subject: [PATCH 0845/1435] st-util: open usb can return sl pointer with no target connected. Check if connected target chip id is known. Some more info regarding connected chip should be set in chipid to know if debugging / attach is possible, but not yet. some more checks should be done to generate flash map / handle flashing if flash type is not supported.. --- src/gdbserver/gdb-server.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 1c45c2538..2b5b1d3cb 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -234,7 +234,14 @@ int main(int argc, char** argv) { printf("st-util %s\n", STLINK_VERSION); sl = do_connect(&state); - if (sl == NULL) return 1; + if (sl == NULL) { + return 1; + } + + if (sl->chip_id == STLINK_CHIPID_UNKNOWN) { + ELOG("Unsupported Target (Chip ID is %#010x, Core ID is %#010x).\n", sl->chip_id, sl->core_id); + return 1; + } connected_stlink = sl; signal(SIGINT, &cleanup); @@ -245,10 +252,7 @@ int main(int argc, char** argv) { stlink_reset(sl); } - - // This is low-level information for debugging, not useful for normal use. - // So: Demoted to a debug meesage. -- REW - DLOG("Chip ID is %08x, Core ID is %08x.\n", sl->chip_id, sl->core_id); + DLOG("Chip ID is %#010x, Core ID is %#08x.\n", sl->chip_id, sl->core_id); sl->verbose=0; current_memory_map = make_memory_map(sl); @@ -1852,7 +1856,8 @@ int serve(stlink_t *sl, st_state_t *st) { stlink_close(sl); sl = do_connect(st); - if (sl == NULL) cleanup(0); + if (sl == NULL || sl->chip_id == STLINK_CHIPID_UNKNOWN) + cleanup(0); connected_stlink = sl; if (st->reset) { From 15f1c81b08a8109f314157c79416b9f3037220ac Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Thu, 16 Apr 2020 16:37:19 +0200 Subject: [PATCH 0846/1435] st-util: remove v1/v2 stlink version stuff, useless --- src/gdbserver/gdb-server.c | 42 ++++++++------------------------------ 1 file changed, 9 insertions(+), 33 deletions(-) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 1c45c2538..fdea6246c 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -59,7 +59,6 @@ static const char* current_memory_map = NULL; typedef struct _st_state_t { // things from command line, bleh - int stlink_version; int logging_level; int listen_port; int persistent; @@ -86,21 +85,13 @@ static void cleanup(int signum) { static stlink_t* do_connect(st_state_t *st) { - stlink_t *ret = NULL; - switch (st->stlink_version) { - case 2: - if (serial_specified){ - ret = stlink_open_usb(st->logging_level, st->reset, serialnumber); - } - else { - ret = stlink_open_usb(st->logging_level, st->reset, NULL); - } - break; - case 1: - ret = stlink_v1_open(st->logging_level, st->reset); - break; + stlink_t *sl = NULL; + if (serial_specified) { + sl = stlink_open_usb(st->logging_level, st->reset, serialnumber); + } else { + sl = stlink_open_usb(st->logging_level, st->reset, NULL); } - return ret; + return sl; } @@ -108,8 +99,6 @@ int parse_options(int argc, char** argv, st_state_t *st) { static struct option long_options[] = { {"help", no_argument, NULL, 'h'}, {"verbose", optional_argument, NULL, 'v'}, - {"stlink_version", required_argument, NULL, 's'}, - {"stlinkv1", no_argument, NULL, '1'}, {"listen_port", required_argument, NULL, 'p'}, {"multi", optional_argument, NULL, 'm'}, {"no-reset", optional_argument, NULL, 'n'}, @@ -123,7 +112,6 @@ int parse_options(int argc, char** argv, st_state_t *st) { " -V, --version\t\tPrint the version\n" " -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n" " -v, --verbose\t\tSpecify generally verbose logging\n" - " -s X, --stlink_version=X\n" "\t\t\tChoose what version of stlink to use, (defaults to 2)\n" " -1, --stlinkv1\tForce stlink version 1\n" " -p 4242, --listen_port=1234\n" @@ -139,7 +127,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { " --serial \n" "\t\t\tUse a specific serial number.\n" "\n" - "The STLINKv2 device to use can be specified in the environment\n" + "The STLINK device to use can be specified in the environment\n" "variable STLINK_DEVICE on the format :.\n" "\n" ; @@ -148,7 +136,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { int option_index = 0; int c; int q; - while ((c = getopt_long(argc, argv, "hv::s:1p:mn", long_options, &option_index)) != -1) { + while ((c = getopt_long(argc, argv, "hv::p:mn", long_options, &option_index)) != -1) { switch (c) { case 0: break; @@ -163,17 +151,6 @@ int parse_options(int argc, char** argv, st_state_t *st) { st->logging_level = DEBUG_LOGGING_LEVEL; } break; - case '1': - st->stlink_version = 1; - break; - case 's': - sscanf(optarg, "%i", &q); - if (q < 0 || q > 2) { - fprintf(stderr, "stlink version %d unknown!\n", q); - exit(EXIT_FAILURE); - } - st->stlink_version = q; - break; case 'p': sscanf(optarg, "%i", &q); if (q < 0) { @@ -225,13 +202,12 @@ int main(int argc, char** argv) { memset(&state, 0, sizeof(state)); // set defaults... - state.stlink_version = 2; state.logging_level = DEFAULT_LOGGING_LEVEL; state.listen_port = DEFAULT_GDB_LISTEN_PORT; state.reset = 1; /* By default, reset board */ parse_options(argc, argv, &state); - printf("st-util %s\n", STLINK_VERSION); + printf("st-util\n"); sl = do_connect(&state); if (sl == NULL) return 1; From 19facc978911790e4f363e4466e7a9d22e7c519a Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 17 Apr 2020 11:41:37 +0200 Subject: [PATCH 0847/1435] indent --- src/common.c | 132 +++++++++++++++++++++++++-------------------------- 1 file changed, 65 insertions(+), 67 deletions(-) diff --git a/src/common.c b/src/common.c index 0ccdeccdb..9694a8b8e 100644 --- a/src/common.c +++ b/src/common.c @@ -696,7 +696,7 @@ static int check_flash_error(stlink_t *sl) { uint32_t res = 0; if ((sl->flash_type == STLINK_FLASH_TYPE_G0) || - (sl->flash_type == STLINK_FLASH_TYPE_G4)) { + (sl->flash_type == STLINK_FLASH_TYPE_G4)) { res = read_flash_sr(sl) & STM32Gx_FLASH_SR_ERROR_MASK; } @@ -1172,13 +1172,13 @@ int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct s bool stlink_is_core_halted(stlink_t *sl) { - bool ret = false; + bool ret = false; - stlink_status(sl); - if (sl->q_buf[0] == STLINK_CORE_HALTED) - ret = true; + stlink_status(sl); + if (sl->q_buf[0] == STLINK_CORE_HALTED) + ret = true; - return ret; + return ret; } int stlink_step(stlink_t *sl) { @@ -1204,8 +1204,6 @@ int stlink_current_mode(stlink_t *sl) { } - - // End of delegates.... Common code below here... // Endianness @@ -2915,19 +2913,20 @@ static int stlink_write_option_bytes_l1(stlink_t *sl, uint8_t* base, stm32_addr_ if (len==8) { - /* Clear errors */ - stlink_write_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_SR_OFF, 0x00003F00); + /* Clear errors */ + stlink_write_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_SR_OFF, 0x00003F00); stlink_read_debug32(sl, addr+4, &val); WLOG("2nd option bytes 0x%08x is 0x%08x\n",addr,val); /* Write options bytes */ - write_uint32((unsigned char*) &data, *(uint32_t*) (base+4)); - if ( data != val ) { - WLOG("Writing 2nd option bytes 0x%04x\n", data); - stlink_write_debug32(sl, addr+4, data); - stlink_read_debug32(sl, addr+4, &val); - WLOG("2nd option bytes is 0x%08x\n",val); + write_uint32((unsigned char*) &data, *(uint32_t*) (base+4)); + + if ( data != val ) { + WLOG("Writing 2nd option bytes 0x%04x\n", data); + stlink_write_debug32(sl, addr+4, data); + stlink_read_debug32(sl, addr+4, &val); + WLOG("2nd option bytes is 0x%08x\n",val); } } @@ -3120,7 +3119,6 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_ stlink_write_debug32(sl, FLASH_F4_OPT_CR, (option_byte & 0x0FFFFFFC)|0x00000002); - stlink_read_debug32(sl, FLASH_F4_SR, &val); WLOG("wait BSY flag to be 0\n"); @@ -3210,7 +3208,7 @@ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { } stlink_read_debug32(sl, FLASH_F4_OPT_CR, option_byte); - WLOG("option bytes CR = %x\n",option_byte); + WLOG("option bytes CR = %x\n", option_byte); WLOG("Option flash re-lock\n"); stlink_write_debug32(sl, FLASH_F4_OPT_CR, val | 0x00000001); @@ -3236,23 +3234,23 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) */ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; - } - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: - return stlink_read_option_bytes_f2(sl, option_byte); - case STLINK_CHIPID_STM32_F446: - return stlink_read_option_bytes_f4(sl, option_byte); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: - return stlink_read_option_bytes_Gx(sl, option_byte); - default: - return stlink_read_option_bytes_generic(sl, option_byte); - } + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F2: + return stlink_read_option_bytes_f2(sl, option_byte); + case STLINK_CHIPID_STM32_F446: + return stlink_read_option_bytes_f4(sl, option_byte); + case STLINK_CHIPID_STM32_G0_CAT1: + case STLINK_CHIPID_STM32_G0_CAT2: + case STLINK_CHIPID_STM32_G4_CAT2: + case STLINK_CHIPID_STM32_G4_CAT3: + return stlink_read_option_bytes_Gx(sl, option_byte); + default: + return stlink_read_option_bytes_generic(sl, option_byte); + } } /** @@ -3276,43 +3274,43 @@ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) */ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { - if (sl->option_base == 0) { - ELOG("Option bytes writing is currently not supported for connected chip\n"); - return -1; - } - - if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { - ELOG("Option bytes start address out of Option bytes range\n"); - return -1; - } + if (sl->option_base == 0) { + ELOG("Option bytes writing is currently not supported for connected chip\n"); + return -1; + } - if (addr + len > sl->option_base + sl->option_size) { - ELOG("Option bytes data too long\n"); - return -1; - } + if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { + ELOG("Option bytes start address out of Option bytes range\n"); + return -1; + } - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: - return stlink_write_option_bytes_f2(sl, base, addr, len); - case STLINK_CHIPID_STM32_F446: - return stlink_write_option_bytes_f4(sl, base, addr, len); - case STLINK_CHIPID_STM32_L0_CAT2: - return stlink_write_option_bytes_l0_cat2(sl, base, addr, len); - case STLINK_CHIPID_STM32_L496X: - return stlink_write_option_bytes_l496x(sl, base, addr, len); - case STLINK_CHIPID_STM32_L152_RE: - case STLINK_CHIPID_STM32_L1_HIGH: - return stlink_write_option_bytes_l1(sl, base, addr, len); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: - return stlink_write_option_bytes_gx(sl, base, addr, len); - default: - ELOG("Option bytes writing is currently not implemented for connected chip\n"); + if (addr + len > sl->option_base + sl->option_size) { + ELOG("Option bytes data too long\n"); return -1; } + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F2: + return stlink_write_option_bytes_f2(sl, base, addr, len); + case STLINK_CHIPID_STM32_F446: + return stlink_write_option_bytes_f4(sl, base, addr, len); + case STLINK_CHIPID_STM32_L0_CAT2: + return stlink_write_option_bytes_l0_cat2(sl, base, addr, len); + case STLINK_CHIPID_STM32_L496X: + return stlink_write_option_bytes_l496x(sl, base, addr, len); + case STLINK_CHIPID_STM32_L152_RE: + case STLINK_CHIPID_STM32_L1_HIGH: + return stlink_write_option_bytes_l1(sl, base, addr, len); + case STLINK_CHIPID_STM32_G0_CAT1: + case STLINK_CHIPID_STM32_G0_CAT2: + case STLINK_CHIPID_STM32_G4_CAT2: + case STLINK_CHIPID_STM32_G4_CAT3: + return stlink_write_option_bytes_gx(sl, base, addr, len); + default: + ELOG("Option bytes writing is currently not implemented for connected chip\n"); + return -1; + } + } /** From 2cccbd91beda0145fe89ba70af8d675029191d4d Mon Sep 17 00:00:00 2001 From: Jochen Wilhelmy Date: Sun, 19 Apr 2020 14:18:32 +0200 Subject: [PATCH 0848/1435] Add CMAKEFLAGS and install target --- Makefile | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 6b44bd70c..9bdea88a9 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,9 @@ ## # This Makefile is used to drive building of Debug and Release targets of CMake ## -MAKEFLAGS += -s + +# additional flags for cmake, e.g. install path -DCMAKE_INSTALL_PREFIX=$(HOME)/.local +CMAKEFLAGS += all: release ci: debug release binary test @@ -10,6 +12,8 @@ help: @echo " debug: Run a debug build" @echo " release: Run a release build" @echo " binary: Build Windows-Binary" + @echo " install: Install release build" + @echo " package: Package release build" @echo " lint: Lint check all source-code" @echo " test: Build and run tests" @echo " clean: Clean all build output" @@ -32,6 +36,10 @@ binary: build/Binary @echo "[BINARY]" @$(MAKE) -C build/Binary +install: build/Release + @echo "[INSTALL] Release" + @$(MAKE) -C build/Release install + package: build/Release @echo "[PACKAGE] Release" @$(MAKE) -C build/Release package From e93c51691e4541ea3fa62b2c1022280f54e3231c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 19 Apr 2020 21:19:06 +0200 Subject: [PATCH 0849/1435] Removed unused build target --- Makefile | 10 ---------- cmake/modules/Findlibusb.cmake | 4 +--- 2 files changed, 1 insertion(+), 13 deletions(-) diff --git a/Makefile b/Makefile index 9bdea88a9..a35400617 100644 --- a/Makefile +++ b/Makefile @@ -11,7 +11,6 @@ ci: debug release binary test help: @echo " debug: Run a debug build" @echo " release: Run a release build" - @echo " binary: Build Windows-Binary" @echo " install: Install release build" @echo " package: Package release build" @echo " lint: Lint check all source-code" @@ -22,7 +21,6 @@ help: rebuild_cache: build/Debug build/Release @$(MAKE) -C build/Debug rebuild_cache @$(MAKE) -C build/Release rebuild_cache - @$(MAKE) -C build/Binary rebuild_cache debug: build/Debug @echo "[DEBUG]" @@ -32,10 +30,6 @@ release: build/Release @echo "[RELEASE]" @$(MAKE) -C build/Release -binary: build/Binary - @echo "[BINARY]" - @$(MAKE) -C build/Binary - install: build/Release @echo "[INSTALL] Release" @$(MAKE) -C build/Release install @@ -55,10 +49,6 @@ build/Release: @mkdir -p $@ @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Release $(CMAKEFLAGS) ../../ -build/Binary: - @mkdir -p $@ - @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Binary $(CMAKEFLAGS) ../../ - clean: @echo "[CLEAN]" @rm -Rf build diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index 5b3e80fe6..c5366377e 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -41,9 +41,7 @@ elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated message(FATAL_ERROR "Expected libusb library not found on your system! Verify your system integrity.") endif () -elseif (WIN32 OR (EXISTS "/etc/debian_version" AND ${CMAKE_BUILD_TYPE} MATCHES "Binary")) - # Windows & Windows-Binary-Build on Debian/Ubuntu - +elseif (WIN32) # Windows # for MinGW/MSYS/MSVC: 64-bit or 32-bit? if (CMAKE_SIZEOF_VOID_P EQUAL 8) set(ARCH 64) From 145ca6d64a44ed867a59229db403ec121086d511 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 19 Apr 2020 23:39:40 +0200 Subject: [PATCH 0850/1435] General Project Update - Updated github branch template - Updated project CHANGELOG.md --- CHANGELOG.md | 8 ++++++-- README.md | 2 +- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index d0b920f71..a5cf843c9 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -12,14 +12,16 @@ Features: - Support for STM32L1, SM32L4 option bytes write (#596, #844, #847) - CMake now creates an uninstall target (#619, #907) +- Added CMAKEFLAGS and install target (#804, #935) - Support for STM32G4 (#822) - Add aliased SRAM2 region in the L496 memory map (#824) - Improved support for STM32G0 (#825, #850, #856, #857) +- Added postinst script with 'depmod -a' for 'make package' (#845, #931) +- Calculate checksums for flash operations (#862, #924) - Added usb PID and udev rules for STlink v2.1 found on Nucleo-L432KC and Nucleo-L552ze boards (#900) - STM32G0/G4 improvements (#910) - Enable mass erase with a flash programming check - Handle G4 Cat3 devices with configurable dual bank flash by using a helper -- Calculate checksums for flash operations (#862, #924) Updates & changes: @@ -38,6 +40,8 @@ Updates & changes: - [doc] Defined version compatibility and installation instructions for macOS (commit 23c071edea45f6e8852fef52d884a680973d6d8f) - Deprecated old appveyor-mingw script (commit 97484422008df0f75c978627054776f35842a075) - Enhanced error log with file path for map_file() (#650, #879, #921) +- Refactoring: Overall option code rework (#927) +- Refactoring: Build settings / GUI-Build on UNIX-based systems if GTK3 is detected (#929) Fixes: @@ -56,7 +60,7 @@ Fixes: - Fixed broken build on 32-bit systems (#919, #920) - st-flash: minor usage fix and make cmdline parsing more user friendly (#925) - Better argument parsing for CLI tools: stlink_open_usb can address v1, v2, v3 (#378, #922) -- Restored functionality of make test builds (Regression) (#926) +- Restored functionality of make test builds (Regression) (#926, #929) v1.6.0 diff --git a/README.md b/README.md index a0147ed14..735712329 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ Open source version of the STMicroelectronics STlink Tools [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) [![GitHub release](https://img.shields.io/github/release/stlink-org/stlink.svg)](https://github.com/stlink-org/stlink/releases/latest) -[![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.6.0.svg)](https://github.com/stlink-org/stlink/releases/master) +[![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.6.0.svg)](https://github.com/stlink-org/stlink/releases/develop) [![Downloads](https://img.shields.io/github/downloads/stlink-org/stlink/total.svg)](https://github.com/stlink-org/stlink/releases) [![Linux Status](https://img.shields.io/travis/stlink-org/stlink/master.svg?label=linux)](https://travis-ci.org/stlink-org/stlink) [![macOS Status](https://img.shields.io/travis/stlink-org/stlink/master.svg?label=osx)](https://travis-ci.org/stlink-org/stlink) From c7874f805c63c60285f2b190f6589da8ae5e47fa Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 20 Apr 2020 01:28:29 +0200 Subject: [PATCH 0851/1435] Fixes to prevent merge conflict --- CMakeLists.txt | 2 +- Makefile | 3 ++- cmake/modules/{Find7zip.cmake => Find_7zip.cmake} | 3 +-- cmake/modules/{Findlibusb.cmake => Find_libusb.cmake} | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) rename cmake/modules/{Find7zip.cmake => Find_7zip.cmake} (91%) rename cmake/modules/{Findlibusb.cmake => Find_libusb.cmake} (99%) diff --git a/CMakeLists.txt b/CMakeLists.txt index e8da6c45c..19a3e24c4 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -53,7 +53,7 @@ endif () # Dependencies ### -find_package(libusb REQUIRED) +find_package(_libusb REQUIRED) if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) find_package(PkgConfig) diff --git a/Makefile b/Makefile index a35400617..5272c74d2 100644 --- a/Makefile +++ b/Makefile @@ -1,6 +1,7 @@ ## # This Makefile is used to drive building of Debug and Release targets of CMake ## +MAKEFLAGS += -s # additional flags for cmake, e.g. install path -DCMAKE_INSTALL_PREFIX=$(HOME)/.local CMAKEFLAGS += @@ -47,7 +48,7 @@ build/Debug: build/Release: @mkdir -p $@ - @cd $@ && cmake -Wno-dev -DCMAKE_BUILD_TYPE=Release $(CMAKEFLAGS) ../../ + @cd $@ && cmake -DCMAKE_BUILD_TYPE=Release $(CMAKEFLAGS) -Wno-dev ../../ clean: @echo "[CLEAN]" diff --git a/cmake/modules/Find7zip.cmake b/cmake/modules/Find_7zip.cmake similarity index 91% rename from cmake/modules/Find7zip.cmake rename to cmake/modules/Find_7zip.cmake index 0ccd23a50..c75cf1150 100644 --- a/cmake/modules/Find7zip.cmake +++ b/cmake/modules/Find_7zip.cmake @@ -1,7 +1,6 @@ -# Find7zip.cmake +# Find_7zip.cmake # Detect 7zip file archiver on Windows systems to extract (zip-)archives - find_program( ZIP_EXECUTABLE NAMES 7z.exe p7zip HINTS "C:\\Program Files\\7-Zip\\" "C:\\Program Files (x86)\\7-Zip\\" diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Find_libusb.cmake similarity index 99% rename from cmake/modules/Findlibusb.cmake rename to cmake/modules/Find_libusb.cmake index c5366377e..d9dd706c8 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Find_libusb.cmake @@ -1,4 +1,4 @@ -# Findlibusb.cmake +# Find_libusb.cmake # Once done this will define # # LIBUSB_FOUND libusb present on system @@ -73,7 +73,7 @@ elseif (WIN32) # Windows if (NOT LIBUSB_FOUND OR EXISTS "/etc/debian_version") # Preparations for installing libusb library - find_package(7zip REQUIRED) + find_package(_7zip REQUIRED) set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) From 48a9db00be3fe6fa3682fbb538d2db03fb78a899 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 20 Apr 2020 01:45:19 +0200 Subject: [PATCH 0852/1435] Removed remnants of unused build target --- Makefile | 1 - cmake/modules/Find_libusb.cmake | 6 +----- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/Makefile b/Makefile index c3bd59c52..354f114fc 100644 --- a/Makefile +++ b/Makefile @@ -9,7 +9,6 @@ ci: debug release binary test help: @echo " debug: Run a debug build" @echo " release: Run a release build" - @echo " binary: Build Windows-Binary" @echo " lint: Lint check all source-code" @echo " test: Build and run tests" @echo " clean: Clean all build output" diff --git a/cmake/modules/Find_libusb.cmake b/cmake/modules/Find_libusb.cmake index e46c6d46e..d9dd706c8 100644 --- a/cmake/modules/Find_libusb.cmake +++ b/cmake/modules/Find_libusb.cmake @@ -41,9 +41,7 @@ elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated message(FATAL_ERROR "Expected libusb library not found on your system! Verify your system integrity.") endif () -elseif (WIN32 OR (EXISTS "/etc/debian_version" AND ${CMAKE_BUILD_TYPE} MATCHES "Binary")) - # Windows & Windows-Binary-Build on Debian/Ubuntu - +elseif (WIN32) # Windows # for MinGW/MSYS/MSVC: 64-bit or 32-bit? if (CMAKE_SIZEOF_VOID_P EQUAL 8) set(ARCH 64) @@ -75,9 +73,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND ${CMAKE_BUILD_TYPE} MATCHES " if (NOT LIBUSB_FOUND OR EXISTS "/etc/debian_version") # Preparations for installing libusb library - find_package(_7zip REQUIRED) - set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) From bc869d75e56d3878e2db3e5941b971c548f0ae22 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 20 Apr 2020 01:46:26 +0200 Subject: [PATCH 0853/1435] Fixes to prevent merge conflict --- Makefile | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Makefile b/Makefile index 354f114fc..b6d2a2a31 100644 --- a/Makefile +++ b/Makefile @@ -9,6 +9,8 @@ ci: debug release binary test help: @echo " debug: Run a debug build" @echo " release: Run a release build" + @echo " install: Install release build" + @echo " package: Package release build" @echo " lint: Lint check all source-code" @echo " test: Build and run tests" @echo " clean: Clean all build output" @@ -26,6 +28,10 @@ release: build/Release @echo "[RELEASE]" @$(MAKE) -C build/Release +install: build/Release + @echo "[INSTALL] Release" + @$(MAKE) -C build/Release install + package: build/Release @echo "[PACKAGE] Release" @$(MAKE) -C build/Release package From 5f983a60958c8476b40260c851eb50bd95b86c83 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Mon, 20 Apr 2020 14:39:00 +0800 Subject: [PATCH 0854/1435] Fix uninitialized cpuid --- src/common.c | 8 ++++++-- tests/usb.c | 10 +++++++--- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/src/common.c b/src/common.c index 6226c893b..0bd914828 100644 --- a/src/common.c +++ b/src/common.c @@ -814,9 +814,13 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { uint32_t raw; - if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) + if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { + cpuid->implementer_id = 0; + cpuid->variant = 0; + cpuid->part = 0; + cpuid->revision = 0; return -1; - + } cpuid->implementer_id = (raw >> 24) & 0x7f; cpuid->variant = (raw >> 20) & 0xf; cpuid->part = (raw >> 4) & 0xfff; diff --git a/tests/usb.c b/tests/usb.c index 06fd73429..4558c8d69 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -30,9 +30,13 @@ int main(int ac, char** av) printf("-- core_id: %#x\n", sl->core_id); cortex_m3_cpuid_t cpuid; - stlink_cpu_id(sl, &cpuid); - printf("cpuid:impl_id = %0#x, variant = %#x\n", cpuid.implementer_id, cpuid.variant); - printf("cpuid:part = %#x, rev = %#x\n", cpuid.part, cpuid.revision); + if (stlink_cpu_id(sl, &cpuid)) { + printf("Failed reading stlink_cpu_id\n"); + } else { + printf("cpuid:impl_id = %0#x, variant = %#x\n", cpuid.implementer_id, cpuid.variant); + printf("cpuid:part = %#x, rev = %#x\n", cpuid.part, cpuid.revision); + } + printf("-- read_sram\n"); static const uint32_t sram_base = STM32_SRAM_BASE; From 629314c44f801f82d478fe49e7b409cdb7364077 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 20 Apr 2020 14:46:36 +0200 Subject: [PATCH 0855/1435] Corrections in cmake build - Name pattern for libusb detection - Include of GNUInstallDirs module - Removed old ci-leftover in Makefile (Fixes #936) --- CMakeLists.txt | 4 +--- Makefile | 2 +- cmake/modules/Find_libusb.cmake | 8 ++++---- 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index ccb5fefa9..2a923be5b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -8,9 +8,6 @@ set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) -# Define GNU standard installation directories -include(GNUInstallDirs) - ### # General project settings @@ -18,6 +15,7 @@ include(GNUInstallDirs) project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics ST-LINK Tools") +include(GNUInstallDirs) # Define GNU standard installation directories set(STLINK_UDEV_RULES_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/udev/rules.d" CACHE PATH "udev rules directory") set(STLINK_MODPROBED_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/modprobe.d" CACHE PATH "modprobe.d directory") diff --git a/Makefile b/Makefile index 5272c74d2..444f1920b 100644 --- a/Makefile +++ b/Makefile @@ -7,7 +7,7 @@ MAKEFLAGS += -s CMAKEFLAGS += all: release -ci: debug release binary test +ci: debug release test help: @echo " debug: Run a debug build" diff --git a/cmake/modules/Find_libusb.cmake b/cmake/modules/Find_libusb.cmake index d9dd706c8..a44e02236 100644 --- a/cmake/modules/Find_libusb.cmake +++ b/cmake/modules/Find_libusb.cmake @@ -19,7 +19,7 @@ if (APPLE) # macOS LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS /usr /usr/local /opt ) - FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + FIND_PACKAGE_HANDLE_STANDARD_ARGS(_libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) if (NOT LIBUSB_FOUND) message(FATAL_ERROR "No libusb library found on your system! Install libusb-1.0 from Homebrew or MacPorts") @@ -35,7 +35,7 @@ elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS /usr /usr/local /opt ) - FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + FIND_PACKAGE_HANDLE_STANDARD_ARGS(_libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) if (NOT LIBUSB_FOUND) message(FATAL_ERROR "Expected libusb library not found on your system! Verify your system integrity.") @@ -131,7 +131,7 @@ elseif (WIN32) # Windows endif () message(STATUS "Missing libusb library has been installed") endif () - FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + FIND_PACKAGE_HANDLE_STANDARD_ARGS(_libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) else () # all other OS (unix-based) @@ -145,7 +145,7 @@ else () # all other OS (unix-based) LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS /usr /usr/local /opt ) - FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + FIND_PACKAGE_HANDLE_STANDARD_ARGS(_libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) if (NOT LIBUSB_FOUND) From e8503fb9b0a54483ab7d5dfc9f4989973711f1ef Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 17 Apr 2020 15:36:47 +0200 Subject: [PATCH 0856/1435] stlink.h: document a bit flash types. f1 xl should probably merged back into f0, with dual bank bit set. --- include/stlink.h | 10 +++++----- src/common.c | 2 ++ 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index db737acb0..87d708ef3 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -81,11 +81,11 @@ extern "C" { enum stlink_flash_type { STLINK_FLASH_TYPE_UNKNOWN = 0, - STLINK_FLASH_TYPE_F0, - STLINK_FLASH_TYPE_L0, - STLINK_FLASH_TYPE_F4, - STLINK_FLASH_TYPE_L4, - STLINK_FLASH_TYPE_F1_XL, + STLINK_FLASH_TYPE_F0, /* used by f0, f1 (except f1xl),f3. */ + STLINK_FLASH_TYPE_F1_XL, /* f0 flash with dual bank, apparently */ + STLINK_FLASH_TYPE_F4, /* used by f2, f4, f7 */ + STLINK_FLASH_TYPE_L0, /* l0, l1 */ + STLINK_FLASH_TYPE_L4, /* l4, l4+ */ STLINK_FLASH_TYPE_G0, STLINK_FLASH_TYPE_G4, STLINK_FLASH_TYPE_WB diff --git a/src/common.c b/src/common.c index 9694a8b8e..7ca017eb4 100644 --- a/src/common.c +++ b/src/common.c @@ -3238,6 +3238,7 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) ELOG("Option bytes read is currently not supported for connected chip\n"); return -1; } + switch (sl->chip_id) { case STLINK_CHIPID_STM32_F2: return stlink_read_option_bytes_f2(sl, option_byte); @@ -3289,6 +3290,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui return -1; } + /* filter out on chip_id, until complete flash family are handled */ switch (sl->chip_id) { case STLINK_CHIPID_STM32_F2: return stlink_write_option_bytes_f2(sl, base, addr, len); From 498de0cc8cb44c30ca401afdf7d36f9cbda5c5e8 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 17 Apr 2020 11:38:54 +0200 Subject: [PATCH 0857/1435] option write : remove size check, this has already been done earlier --- src/common.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/src/common.c b/src/common.c index 7ca017eb4..9fda97cdf 100644 --- a/src/common.c +++ b/src/common.c @@ -3028,12 +3028,8 @@ static int stlink_write_option_bytes_f2(stlink_t *sl, uint8_t *base, stm32_addr_ uint32_t val; uint32_t option_byte; - (void) addr; /* todo: add sanitary check */ - - if(len != 4) { - ELOG("Wrong length for writting option bytes, must be 4 is %d\n", len); - return -1; - } + (void) addr; + (void) len; option_byte = *(uint32_t*) (base); @@ -3088,12 +3084,8 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_ uint32_t val; uint32_t option_byte; - (void) addr; /* todo: add sanitary check */ - - if(len != 4) { - ELOG("Wrong length for writing option bytes, must be 4 is %d\n", len); - return -1; - } + (void) addr; + (void) len; option_byte = *(uint32_t*) (base); From 598af1c1aff066a61494b611d41ad62b35f0be92 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 17 Apr 2020 11:41:10 +0200 Subject: [PATCH 0858/1435] use constant for optkey --- src/common.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/src/common.c b/src/common.c index 9fda97cdf..afeb6106a 100644 --- a/src/common.c +++ b/src/common.c @@ -53,6 +53,9 @@ #define FLASH_KEY1 0x45670123 #define FLASH_KEY2 0xcdef89ab +#define FLASH_OPTKEY1 0x08192A3B +#define FLASH_OPTKEY2 0x4C5D6E7F + #define FLASH_SR_BSY 0 #define FLASH_SR_EOP 5 @@ -2753,8 +2756,8 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_ if ((val & (1 << STM32Gx_FLASH_CR_OPTLOCK))) { /* disable option byte write protection. */ - stlink_write_debug32(sl, STM32Gx_FLASH_OPTKEYR, 0x08192A3B); - stlink_write_debug32(sl, STM32Gx_FLASH_OPTKEYR, 0x4C5D6E7F); + stlink_write_debug32(sl, STM32Gx_FLASH_OPTKEYR, FLASH_OPTKEY1); + stlink_write_debug32(sl, STM32Gx_FLASH_OPTKEYR, FLASH_OPTKEY2); /* check that the lock is no longer set. */ stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -2973,8 +2976,8 @@ static int stlink_write_option_bytes_l496x(stlink_t *sl, uint8_t* base, stm32_ad if ((val & (1 << STM32L4_FLASH_CR_OPTLOCK))) { /* disable option byte write protection. */ - stlink_write_debug32(sl, STM32L4_FLASH_OPTKEYR, 0x08192A3B); - stlink_write_debug32(sl, STM32L4_FLASH_OPTKEYR, 0x4C5D6E7F); + stlink_write_debug32(sl, STM32L4_FLASH_OPTKEYR, FLASH_OPTKEY1); + stlink_write_debug32(sl, STM32L4_FLASH_OPTKEYR, FLASH_OPTKEY2); /* check that the lock is no longer set. */ stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); @@ -3038,8 +3041,8 @@ static int stlink_write_option_bytes_f2(stlink_t *sl, uint8_t *base, stm32_addr_ WLOG("Unlocking option flash\n"); //Unlock the FLASH_OPT_CR register (FLASH Programming manual page 15) //https://www.st.com/resource/en/programming_manual/cd00233952.pdf - stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, 0x08192A3B); - stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, 0x4C5D6E7F); + stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, FLASH_OPTKEY1); + stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, FLASH_OPTKEY2); stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); if (val & FLASH_F2_OPT_LOCK_BIT) { @@ -3094,8 +3097,8 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_ WLOG("Unlocking option flash\n"); //Unlock the FLASH_OPT_CR register (FLASH Programming manual page 15) //https://www.st.com/resource/en/programming_manual/cd00233952.pdf - stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, 0x08192A3B); - stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, 0x4C5D6E7F); + stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, FLASH_OPTKEY1); + stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, FLASH_OPTKEY2); stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); if (val & FLASH_F4_OPT_LOCK_BIT) { @@ -3156,8 +3159,8 @@ int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { WLOG("Unlocking option flash\n"); //Unlock the FLASH_OPT_CR register (FLASH Programming manual page 15) //https://www.st.com/resource/en/programming_manual/cd00233952.pdf - stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, 0x08192A3B); - stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, 0x4C5D6E7F); + stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, FLASH_OPTKEY1); + stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, FLASH_OPTKEY2); stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); if (val & FLASH_F2_OPT_LOCK_BIT) { @@ -3189,8 +3192,8 @@ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { WLOG("Unlocking option flash\n"); //Unlock the FLASH_OPT_CR register (FLASH Programming manual page 15) //https://www.st.com/resource/en/programming_manual/cd00233952.pdf - stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, 0x08192A3B); - stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, 0x4C5D6E7F); + stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, FLASH_OPTKEY1); + stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, FLASH_OPTKEY2); stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); if (val & FLASH_F4_OPT_LOCK_BIT) { From 7640daae4c0ade48a4179b3a7750272471b8c8e5 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 20 Apr 2020 18:34:12 +0200 Subject: [PATCH 0859/1435] Fixed compilation error on windows Extraction of downloaded libusb archive failed due to wrong command option formatting since commit a8c1f41f1b1c9dd1314f99a1d42de1008f5a4f74. --- cmake/modules/Find_libusb.cmake | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cmake/modules/Find_libusb.cmake b/cmake/modules/Find_libusb.cmake index a44e02236..8da0090d8 100644 --- a/cmake/modules/Find_libusb.cmake +++ b/cmake/modules/Find_libusb.cmake @@ -73,7 +73,7 @@ elseif (WIN32) # Windows if (NOT LIBUSB_FOUND OR EXISTS "/etc/debian_version") # Preparations for installing libusb library - find_package(_7zip REQUIRED) + find_package(7zip REQUIRED) set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) @@ -100,8 +100,8 @@ elseif (WIN32) # Windows ) else () execute_process( - COMMAND ${ZIP_EXECUTABLE} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o ${LIBUSB_WIN_OUTPUT_FOLDER} - ) + COMMAND ${ZIP_EXECUTABLE} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o${LIBUSB_WIN_OUTPUT_FOLDER} + ) # <-- Note the absence of a space character following the -o option! endif () # Find path to libusb library From a7568d3cf93c00705b1809186e069fc52210445f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 20 Apr 2020 20:00:12 +0200 Subject: [PATCH 0860/1435] Fixed package name in Find_libusb module Regression from previous commit 7640daae4c0ade48a4179b3a7750272471b8c8e5. --- cmake/modules/Find_libusb.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake/modules/Find_libusb.cmake b/cmake/modules/Find_libusb.cmake index 8da0090d8..57e0fa8cf 100644 --- a/cmake/modules/Find_libusb.cmake +++ b/cmake/modules/Find_libusb.cmake @@ -73,7 +73,7 @@ elseif (WIN32) # Windows if (NOT LIBUSB_FOUND OR EXISTS "/etc/debian_version") # Preparations for installing libusb library - find_package(7zip REQUIRED) + find_package(_7zip REQUIRED) set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) From d7e1e6a11e439256abe36a02663d065320cbc4df Mon Sep 17 00:00:00 2001 From: Glaeqen Date: Tue, 21 Apr 2020 00:13:49 +0200 Subject: [PATCH 0861/1435] Added compilation guideline for MSVC toolchain --- doc/compiling.md | 45 ++++++++++++++++++++++++++++++++++++--------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index 15d8b4fc2..7296af650 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -19,13 +19,27 @@ On Windows users should ensure that the following software is installed: Ensure that you add cmake to the $PATH system variable when following the instructions by the setup assistant. 4. Install - _EITHER_: **MinGW-w64** from (mingw-w64-install.exe)
    - - _OR_: **Visual Studio 2017 CE** (other versions will likely work as well, but are untested; the Community edition is free for open source - development) + - _OR_: **MSVC toolchain** from Visual Studio Build Tools 2019 5. Create a new destination folder at a place of your choice 6. Open the command-line (cmd.exe) and execute `cd C:\$Path-to-your-destination-folder$\` 7. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git`from the command-line (cmd.exe)
    or download the stlink zip-sourcefolder from the Release page on GitHub +#### MSVC toolchain - minimal installation + +Visual Studio IDE is not necessary, only Windows SDK & build tools are required (~3,3GB). + +1. Open +2. Navigate through menus as follows (might change overtime) + + `All downloads > Tools for Visual Studio 2019 > Build Tools for Visual Studio 2019 > Download` +3. Start downloaded executable. After Visual Studio Installer bootstraps and main window pops up, open `Individual Components` tab, and pick + - latest build tools (eg. `MSVC v142 - VS 2019 C++ x64/x86 build tools (v14.25)`) + - latest Windows SDK (eg. `Windows 10 SDK (10.0.18362.0)`) +4. After installation finishes, you can press `Launch` button in Visual Studio Installer's main menu. + - Thus you can open `Developer Command Prompt for VS 2019`. It is `cmd.exe` instance with adjusted PATHs including eg. `msbuild`. + - Alternatively, you can use `Developer Powershell for VS 2019` which is the same thing for `powershell.exe`. Both are available from Start menu. + - Another option is to add `msbuild` to PATH manually. Its location should be `C:\Program Files (x86)\Microsoft Visual Studio\2019\BuildTools\MSBuild\Current\Bin`. Then, it should be available from any `powershell.exe` or `cmd.exe` session. ### Building #### MinGW-w64 @@ -39,19 +53,32 @@ When installing different toolchains make sure to update the path in the `mingw6 This can be achieved by opening the .bat file with a common text editor. -#### Visual Studio (32 bit) +#### MSVC toolchain 1. In a command prompt, change the directory to the folder where the stlink files were cloned (or unzipped) to. 2. Make sure the build folder exists (`mkdir build` if not). 3. From the build folder, run cmake (`cd build; cmake ..`). -This will create a solution (stlink.sln) in the build folder. Open it in Visual Studio, select the Solution Configuration (Debug or -Release) and build the solution normally (F7). +This will create a solution file `stlink.sln` in the build folder. +Now, you can build whole `stlink` suite using following command: +``` +msbuild /m /p:Configuration=Release stlink.sln +``` +Options: +- `/m` - compilation runs in parallel utilizing multiple cores +- `/p:Configuration=Release` - generates *Release*, optimized build. + +Directory `\build\Release` contains final executables. +(`st-util.exe` is located in `\build\src\gdbserver\Release`). -NOTE:
    -This solution will link to the dll version of libusb-1.0.y
    -To debug or run the executable, the dll version of libusb-1.0 must be either on the path, or in the same folder as the executable.
    -It can be copied from here: `build\3rdparty\libusb-1.0.21\MS32\dll\libusb-1.0.dll`. +**NOTE 1:** + +Executables link against libusb.dll library. It has to be placed in the same directory as binaries or in PATH. +It can be copied from: `\build\3rdparty\libusb-{version}\MS{arch}\dll\libusb-1.0.dll`. + +**NOTE 2:** + +[ST-LINK drivers](https://www.st.com/en/development-tools/stsw-link009.html) are required for `stlink` to work. ## Linux ### Common requirements From abaa8f5782df7b8cfe4e3171b168d373bd680fa8 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Tue, 21 Apr 2020 09:50:50 +0800 Subject: [PATCH 0862/1435] Add cleanroom document --rebased --- flashloaders/cleanroom.md | 232 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 232 insertions(+) create mode 100644 flashloaders/cleanroom.md diff --git a/flashloaders/cleanroom.md b/flashloaders/cleanroom.md new file mode 100644 index 000000000..594e7191a --- /dev/null +++ b/flashloaders/cleanroom.md @@ -0,0 +1,232 @@ +English version can be found below. + +# 净室工程文档 + +代码位于的section：`.text` +编译制导添加`.syntax unified` + +传入参数约定： + +参数全部通过寄存器传递 + +`r0`: 拷贝源点起始地址 +`r1`: 拷贝终点起始地址 +`r2`: 拷贝word（4字节）数(存在例外) + +程序功能：将数据从源点拷贝到终点，在拷贝完毕后触发断点以结束执行，结束时`r2`值需清零表明传输完毕。 + +限制：不可使用栈，可自由使用的临时寄存器为`R3`到`R12`。`R13`为`sp`（stack pointer），`R14`为lr（一般用于储存跳转地址），`R15`为`pc`（program counter）。 + +要求：每完成一次拷贝，需等待flash完成写入，单次拷贝宽度、检查写入完成的方式见每个文件的具体要求。 + +特殊地址`flash_base`存放地址需2字节对齐。 + +## stm32f0.s + +例外：`r2`:拷贝half word（2字节）数 + +特殊地址定义：`flash_base`:定义为0x40022000 + +`FLASH_CR`: 相对`flash_base`的offset为16 + +`FLASH_SR`: 相对`flash_base`的offset为12 + +参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f0.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f0.h) +[https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) + +特殊要求： +每次拷贝开始前需要读出FLASH_CR处的4字节内容，将其最低bit设置为1，写回FLASH_CR。 + +每次写入数据宽度为2字节（半字）。 + +每完成一次写入，需等待flash完成写入，检查方式为读取FLASH_SR处4字节内容，若取值为1，则说明写入尚未完成，需继续轮询等待；否则需要检查FLASH_SR处值是否为4，若是4，则应直接准备退出。 + +退出：全部拷贝执行完毕后触发断点前，将FLASH_CR处4字节内容最低bit清为0，写回FLASH_CR。 + + + +## stm32f4.s + +特殊地址定义： `flash_base`：定义为0x40023c00 + +`FLASH_SR`:相对flash_base的offset为0xe（14） + +参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h) +[https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf](https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf) + +特殊要求： + +每次写入的数据宽度为4字节（字）。 + +每完成一次写入，需等待flash完成写入，检查方式为读取FLASH_SR处2字节内容，若取值为1，则说明写入尚未完成，需继续轮询等待。 + +## stm32f4lv.s + +特殊地址定义：`flash_base`：定义为0x40023c00 + +`FLASH_SR`:相对`flash_base`的offset为0xe (14) + +参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h) +[https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf](https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf) + +特殊要求： + +每次写入的数据宽度为1字节（1/4字）。 + +每完成一次写入，需等待flash完成写入，检查方式为读取FLASH_SR处2字节内容，若取值为1，则说明写入尚未完成，需继续轮询等待。 + +## stm32f7.s + +参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h) +[https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) + +要求同stm32f4.s，额外要求在每次拷贝执行完毕、flash写入成功检测前，执行`dsb sy`指令以建立内存屏障。 + + +## stm32f7lv.s + +参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h) +[https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) +要求基本同stm32f7.s，差异要求为每次写入的数据宽度为1字节（1/4字）。 + +## stm32l0x.s + +特殊要求： + +每次写入的数据宽度为4字节（字） + +无需实现检查flash写入完成功能 + +## stm32l4.s + +例外：`r2`： 拷贝双字（8字节）数 + +特殊地址定义：`flash_base`: 0x40022000 + +`FLASH_BSY`：相对flash_base的offset为0x12 + +参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32l4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32l4.h) +[https://www.st.com/resource/en/reference_manual/dm00310109-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00310109-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) + +拷贝方式：一次性拷贝连续的8个字节（使用两个连续寄存器作中转）并写入 + +每完成一次写入，需等待flash完成写入，检查方式为读取FLASH_BSY处半字（2字节），若其最低位非1，可继续拷贝。 + +## stm32lx.s + +要求与stm32l0x.s相同 + +# Clean Room Documentation English Version + +Code is situated in section `.text` + +Shall add a compile directive at the head: `.syntax unified` + +**Calling convention**: + +All parameters would be passed over registers + +`r0`: the base address of the copy source +`r1`: the base address of the copy destination +`r2`: the total word (4 bytes) count to be copied (with expeptions) + +**What the program is expected to do**: + +Copy data from source to destination, after which trigger a breakpint to exit. Before exit, `r2` must be cleared to zero to indicate that the copy is done. + +**Limitation**: No stack operations are permitted. Registers ranging from `r3` to `r12` are free to use. Note that `r13` is `sp`(stack pointer), `r14` is `lr`(commonly used to store jump address), `r15` is `pc`(program counter). + +**Requirement**: After every single copy, wait until the flash finishes. The detailed single copy length and the way to check can be found below. Address of `flash_base` shall be two-bytes aligned. + +## stm32f0.s + +**Exception**: `r2` stores the total half word (2 bytes) count to be copied + +`flash_base`: 0x40022000 + +`FLASH_CR`: offset from `flash_base` is 16 + +`FLASH_SR`: offset from `flash_base` is 12 + +**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f0.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f0.h) +[https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) + +**Special requirements**: + +Before every copy, read a word from FLASH_CR, set the lowest bit to 1 and write back. Copy one half word each time. + +How to wait for the write process: read a word from FLASH_SR, loop until the content is not 1. After that, check FLASH_SR, proceed if the content is not 4, otherwise exit. + +Exit: after the copying process and before triggering the breakpoint, clear the lowest bit in FLASH_CR. + +## stm32f4.s + +`flash_base`: 0x40023c00 + +`FLASH_SR`: offset from `flash_base` is 0xe (14) + +**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h) +[https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf](https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf) + + +**Special requirements**: + +Copy one word each time. +How to wait for the write process: read a half word from FLASH_SR, loop until the content is not 1. + +## stm32f4lv.s + +`flash_base`: 0x40023c00 + +`FLASH_SR`: offset from `flash_base` is 0xe (14) + +**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h) +[https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf](https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf) + +**Special Requirements**: + +Copy one byte each time. + +How to wait from the write process: read a half word from FLASH_SR, loop until the content is not 1. + +## stm32f7.s + +**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h) +[https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) + +Mostly same with `stm32f4.s`. Require establishing a memory barrier after every copy and before checking for finished writing by `dsb sy` + +## stm32f7lv.s + +**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h) +[https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) + +**Special Requirements**: + +Mostly same with `stm32f7.s`. Copy one byte each time. + +## stm32l0x.s + +**Special Requirements**: + +Copy one word each time. No wait for write. + +## stm32l4.s + +**Exception**: r2 stores the double word count to be copied. + +`flash_base`: 0x40022000 +`FLASH_BSY`: offset from `flash_base` is 0x12 + +**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32l4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32l4.h) +[https://www.st.com/resource/en/reference_manual/dm00310109-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00310109-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) + +**Special Requirements**: + +Copy one double word each time (More than one registers are allowed). + +How to wait for the write process: read a half word from `FLASH_BSY`, loop until the lowest bit turns non-1. + +## stm32lx.s + +Same with stm32l0x.s. \ No newline at end of file From 9b19f9225460472af9d98959b7217d0a840ee972 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 21 Apr 2020 14:49:25 +0200 Subject: [PATCH 0863/1435] Fixed compilation errors - Moved include of GNUInstallDirs module in cmake-routine - Removed old ci-leftover in Makefile - cmake: Fixed name pattern for libusb module (Fixes #940) - Wrong command option formatting for 7zip (Fixes #936) Extraction of downloaded libusb archive on Windows failed since commit a8c1f41f1b1c9dd1314f99a1d42de1008f5a4f74. --- CMakeLists.txt | 6 ++---- Makefile | 2 +- .../modules/{Find_7zip.cmake => Find7zip.cmake} | 2 +- .../{Find_libusb.cmake => Findlibusb.cmake} | 16 ++++++++-------- 4 files changed, 12 insertions(+), 14 deletions(-) rename cmake/modules/{Find_7zip.cmake => Find7zip.cmake} (91%) rename cmake/modules/{Find_libusb.cmake => Findlibusb.cmake} (92%) diff --git a/CMakeLists.txt b/CMakeLists.txt index ccb5fefa9..fd79ac10e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -8,9 +8,6 @@ set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) -# Define GNU standard installation directories -include(GNUInstallDirs) - ### # General project settings @@ -18,6 +15,7 @@ include(GNUInstallDirs) project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics ST-LINK Tools") +include(GNUInstallDirs) # Define GNU standard installation directories set(STLINK_UDEV_RULES_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/udev/rules.d" CACHE PATH "udev rules directory") set(STLINK_MODPROBED_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/modprobe.d" CACHE PATH "modprobe.d directory") @@ -67,7 +65,7 @@ endif () # Dependencies ### -find_package(_libusb REQUIRED) +find_package(libusb REQUIRED) if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) find_package(PkgConfig) diff --git a/Makefile b/Makefile index 5272c74d2..444f1920b 100644 --- a/Makefile +++ b/Makefile @@ -7,7 +7,7 @@ MAKEFLAGS += -s CMAKEFLAGS += all: release -ci: debug release binary test +ci: debug release test help: @echo " debug: Run a debug build" diff --git a/cmake/modules/Find_7zip.cmake b/cmake/modules/Find7zip.cmake similarity index 91% rename from cmake/modules/Find_7zip.cmake rename to cmake/modules/Find7zip.cmake index c75cf1150..83eb912d4 100644 --- a/cmake/modules/Find_7zip.cmake +++ b/cmake/modules/Find7zip.cmake @@ -1,4 +1,4 @@ -# Find_7zip.cmake +# Find7zip.cmake # Detect 7zip file archiver on Windows systems to extract (zip-)archives find_program( diff --git a/cmake/modules/Find_libusb.cmake b/cmake/modules/Findlibusb.cmake similarity index 92% rename from cmake/modules/Find_libusb.cmake rename to cmake/modules/Findlibusb.cmake index d9dd706c8..13f70d7b7 100644 --- a/cmake/modules/Find_libusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -1,4 +1,4 @@ -# Find_libusb.cmake +# Findlibusb.cmake # Once done this will define # # LIBUSB_FOUND libusb present on system @@ -19,7 +19,7 @@ if (APPLE) # macOS LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS /usr /usr/local /opt ) - FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + FIND_PACKAGE_HANDLE_STANDARD_ARGS(libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) if (NOT LIBUSB_FOUND) message(FATAL_ERROR "No libusb library found on your system! Install libusb-1.0 from Homebrew or MacPorts") @@ -35,7 +35,7 @@ elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS /usr /usr/local /opt ) - FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + FIND_PACKAGE_HANDLE_STANDARD_ARGS(libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) if (NOT LIBUSB_FOUND) message(FATAL_ERROR "Expected libusb library not found on your system! Verify your system integrity.") @@ -73,7 +73,7 @@ elseif (WIN32) # Windows if (NOT LIBUSB_FOUND OR EXISTS "/etc/debian_version") # Preparations for installing libusb library - find_package(_7zip REQUIRED) + find_package(7zip REQUIRED) set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) @@ -100,8 +100,8 @@ elseif (WIN32) # Windows ) else () execute_process( - COMMAND ${ZIP_EXECUTABLE} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o ${LIBUSB_WIN_OUTPUT_FOLDER} - ) + COMMAND ${ZIP_EXECUTABLE} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o${LIBUSB_WIN_OUTPUT_FOLDER} + ) # <-- Note the absence of a space character following the -o option! endif () # Find path to libusb library @@ -131,7 +131,7 @@ elseif (WIN32) # Windows endif () message(STATUS "Missing libusb library has been installed") endif () - FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + FIND_PACKAGE_HANDLE_STANDARD_ARGS(libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) else () # all other OS (unix-based) @@ -145,7 +145,7 @@ else () # all other OS (unix-based) LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS /usr /usr/local /opt ) - FIND_PACKAGE_HANDLE_STANDARD_ARGS(Libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + FIND_PACKAGE_HANDLE_STANDARD_ARGS(libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) if (NOT LIBUSB_FOUND) From 9373f133935e967182518bbdfa9501d7ebbcc2d8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 21 Apr 2020 15:47:56 +0200 Subject: [PATCH 0864/1435] Updated CHANGELOG.md --- CHANGELOG.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index a5cf843c9..9ad6b6497 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -22,6 +22,7 @@ Features: - STM32G0/G4 improvements (#910) - Enable mass erase with a flash programming check - Handle G4 Cat3 devices with configurable dual bank flash by using a helper +- Display programmer serial when no target is connected (#432, #933, #943) Updates & changes: @@ -42,6 +43,7 @@ Updates & changes: - Enhanced error log with file path for map_file() (#650, #879, #921) - Refactoring: Overall option code rework (#927) - Refactoring: Build settings / GUI-Build on UNIX-based systems if GTK3 is detected (#929) +- Reconfiguration of package build process (#931, #936, #940, commit 9b19f9225460472af9d98959b7217d0a840ee972) Fixes: @@ -61,6 +63,7 @@ Fixes: - st-flash: minor usage fix and make cmdline parsing more user friendly (#925) - Better argument parsing for CLI tools: stlink_open_usb can address v1, v2, v3 (#378, #922) - Restored functionality of make test builds (Regression) (#926, #929) +- Fixed compilation error due to uninitialized cpuid (#937, #938) v1.6.0 From 09ea99aea51f741ce9c8c0e2ad755d40b3d86021 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mikl=C3=B3s=20M=C3=A1rton?= Date: Mon, 24 Feb 2020 21:34:36 +0100 Subject: [PATCH 0865/1435] Add support for STLink V3 Flash programming is broken --- include/stlink.h | 68 ++++++- include/stlink/commands.h | 48 +++-- include/stlink/tools/flash.h | 2 +- include/stlink/usb.h | 14 +- src/common.c | 100 ++++++---- src/flash_loader.c | 4 +- src/gdbserver/gdb-server.c | 2 +- src/logging.c | 2 +- src/sg.c | 20 +- src/tools/flash.c | 10 +- src/usb.c | 368 ++++++++++++++++++++++++++++------- 11 files changed, 479 insertions(+), 159 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index d4170c7a7..f9de94fd4 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -24,10 +24,17 @@ extern "C" { //#define Q_BUF_LEN 96 #define Q_BUF_LEN (1024 * 100) - // STLINK_DEBUG_RESETSYS, etc: +// STLINK_DEBUG_RESETSYS, etc: +enum target_state { + TARGET_UNKNOWN = 0, + TARGET_RUNNING = 1, + TARGET_HALTED = 2, + TARGET_RESET = 3, + TARGET_DEBUG_RUNNING = 4, +}; + #define STLINK_CORE_RUNNING 0x80 #define STLINK_CORE_HALTED 0x81 -#define STLINK_CORE_STAT_UNKNOWN -1 #define STLINK_GET_VERSION 0xf1 #define STLINK_GET_CURRENT_MODE 0xf5 @@ -52,6 +59,11 @@ extern "C" { #define STLINK_DEBUG_APIV2_SWD_SET_FREQ 0x43 +#define STLINK_APIV3_SET_COM_FREQ 0x61 +#define STLINK_APIV3_GET_COM_FREQ 0x62 + +#define STLINK_APIV3_GET_VERSION_EX 0xFB + // Baud rate divisors for SWDCLK #define STLINK_SWDCLK_4MHZ_DIVISOR 0 #define STLINK_SWDCLK_1P8MHZ_DIVISOR 1 @@ -68,7 +80,45 @@ extern "C" { #define STLINK_SERIAL_MAX_SIZE 64 - /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ +#define STLINK_V3_MAX_FREQ_NB 10 + +/* Cortex Debug Control Block */ +#define DCB_DHCSR 0xE000EDF0 +#define DCB_DCRSR 0xE000EDF4 +#define DCB_DCRDR 0xE000EDF8 +#define DCB_DEMCR 0xE000EDFC + +/* DCB_DHCSR bit and field definitions */ +#define DBGKEY (0xA05F << 16) +#define C_DEBUGEN (1 << 0) +#define C_HALT (1 << 1) +#define C_STEP (1 << 2) +#define C_MASKINTS (1 << 3) +#define S_REGRDY (1 << 16) +#define S_HALT (1 << 17) +#define S_SLEEP (1 << 18) +#define S_LOCKUP (1 << 19) +#define S_RETIRE_ST (1 << 24) +#define S_RESET_ST (1 << 25) + + +/* + * Map the relevant features, quirks and workaround for specific firmware + * version of stlink + */ +#define STLINK_F_HAS_TRACE (1<<0) +#define STLINK_F_HAS_SWD_SET_FREQ (1<<1) +#define STLINK_F_HAS_JTAG_SET_FREQ (1<<2) +#define STLINK_F_HAS_MEM_16BIT (1<<3) +#define STLINK_F_HAS_GETLASTRWSTATUS2 (1<<4) +#define STLINK_F_HAS_DAP_REG (1<<5) +#define STLINK_F_QUIRK_JTAG_DP_READ (1<<6) +#define STLINK_F_HAS_AP_INIT (1<<7) +#define STLINK_F_HAS_DPBANKSEL (1<<8) +#define STLINK_F_HAS_RW8_512BYTES (1<<9) + + +/* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 enum stlink_flash_type { @@ -111,12 +161,22 @@ typedef struct flash_loader { uint8_t revision; } cortex_m3_cpuid_t; + enum stlink_jtag_api_version { + STLINK_JTAG_API_V1 = 1, + STLINK_JTAG_API_V2, + STLINK_JTAG_API_V3, + }; + typedef struct stlink_version_ { uint32_t stlink_v; uint32_t jtag_v; uint32_t swim_v; uint32_t st_vid; uint32_t stlink_pid; + /** jtag api version supported */ + enum stlink_jtag_api_version jtag_api; + /** one bit for each feature supported. See macros STLINK_F_* */ + uint32_t flags; } stlink_version_t; enum transport_type { @@ -144,7 +204,7 @@ typedef struct flash_loader { int verbose; uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram - int core_stat; // set by stlink_status(), values STLINK_CORE_xxxxx + enum target_state core_stat; // set by stlink_status() char serial[STLINK_SERIAL_MAX_SIZE]; int serial_size; diff --git a/include/stlink/commands.h b/include/stlink/commands.h index 9ff5a8fb9..a6830ff26 100644 --- a/include/stlink/commands.h +++ b/include/stlink/commands.h @@ -2,25 +2,35 @@ #define STLINK_COMMANDS_H_ enum stlink_debug_commands { - STLINK_DEBUG_ENTER_JTAG = 0x00, - STLINK_DEBUG_GETSTATUS = 0x01, - STLINK_DEBUG_FORCEDEBUG = 0x02, - STLINK_DEBUG_RESETSYS = 0x03, - STLINK_DEBUG_READALLREGS = 0x04, - STLINK_DEBUG_READREG = 0x05, - STLINK_DEBUG_WRITEREG = 0x06, - STLINK_DEBUG_READMEM_32BIT = 0x07, - STLINK_DEBUG_WRITEMEM_32BIT = 0x08, - STLINK_DEBUG_RUNCORE = 0x09, - STLINK_DEBUG_STEPCORE = 0x0a, - STLINK_DEBUG_SETFP = 0x0b, - STLINK_DEBUG_WRITEMEM_8BIT = 0x0d, - STLINK_DEBUG_CLEARFP = 0x0e, - STLINK_DEBUG_WRITEDEBUGREG = 0x0f, - STLINK_DEBUG_ENTER = 0x20, - STLINK_DEBUG_EXIT = 0x21, - STLINK_DEBUG_READCOREID = 0x22, - STLINK_DEBUG_ENTER_SWD = 0xa3 + STLINK_DEBUG_ENTER_JTAG = 0x00, + STLINK_DEBUG_GETSTATUS = 0x01, + STLINK_DEBUG_FORCEDEBUG = 0x02, + STLINK_DEBUG_APIV1_RESETSYS = 0x03, + STLINK_DEBUG_APIV1_READALLREGS = 0x04, + STLINK_DEBUG_APIV1_READREG = 0x05, + STLINK_DEBUG_APIV1_WRITEREG = 0x06, + STLINK_DEBUG_READMEM_32BIT = 0x07, + STLINK_DEBUG_WRITEMEM_32BIT = 0x08, + STLINK_DEBUG_RUNCORE = 0x09, + STLINK_DEBUG_STEPCORE = 0x0a, + STLINK_DEBUG_APIV1_SETFP = 0x0b, + STLINK_DEBUG_WRITEMEM_8BIT = 0x0d, + STLINK_DEBUG_APIV1_CLEARFP = 0x0e, + STLINK_DEBUG_APIV1_WRITEDEBUGREG = 0x0f, + STLINK_DEBUG_APIV1_ENTER = 0x20, + STLINK_DEBUG_EXIT = 0x21, + STLINK_DEBUG_READCOREID = 0x22, + STLINK_DEBUG_APIV2_ENTER = 0x30, + STLINK_DEBUG_APIV2_READ_IDCODES = 0x31, + STLINK_DEBUG_APIV2_RESETSYS = 0x32, + STLINK_DEBUG_APIV2_READREG = 0x33, + STLINK_DEBUG_APIV2_WRITEREG = 0x34, + STLINK_DEBUG_APIV2_WRITEDEBUGREG = 0x35, + STLINK_DEBUG_APIV2_READDEBUGREG = 0x36, + STLINK_DEBUG_APIV2_READALLREGS = 0x3A, + STLINK_DEBUG_APIV2_GETLASTRWSTATUS = 0x3B, + STLINK_DEBUG_APIV2_GETLASTRWSTATUS2 = 0x3E, + STLINK_DEBUG_ENTER_SWD = 0xa3 }; #endif /* STLINK_COMMANDS_H_ */ diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index 8ca1eddf9..6851ede8b 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -5,7 +5,7 @@ #include #define DEBUG_LOG_LEVEL 100 -#define STND_LOG_LEVEL 50 +#define STND_LOG_LEVEL 100 enum flash_cmd {FLASH_CMD_NONE = 0, FLASH_CMD_WRITE = 1, FLASH_CMD_READ = 2, FLASH_CMD_ERASE = 3, CMD_RESET = 4}; enum flash_format {FLASH_FORMAT_BINARY = 0, FLASH_FORMAT_IHEX = 1}; diff --git a/include/stlink/usb.h b/include/stlink/usb.h index 621695ea4..a69101c1f 100644 --- a/include/stlink/usb.h +++ b/include/stlink/usb.h @@ -18,11 +18,15 @@ extern "C" { #endif -#define STLINK_USB_VID_ST 0x0483 -#define STLINK_USB_PID_STLINK 0x3744 -#define STLINK_USB_PID_STLINK_32L 0x3748 -#define STLINK_USB_PID_STLINK_32L_AUDIO 0x374a -#define STLINK_USB_PID_STLINK_NUCLEO 0x374b +#define STLINK_USB_VID_ST 0x0483 +#define STLINK_USB_PID_STLINK 0x3744 +#define STLINK_USB_PID_STLINK_32L 0x3748 +#define STLINK_USB_PID_STLINK_32L_AUDIO 0x374a +#define STLINK_USB_PID_STLINK_NUCLEO 0x374b +#define STLINK_USB_PID_STLINK_V3_USBLOADER 0x374d +#define STLINK_USB_PID_STLINK_V3E_PID 0x374e +#define STLINK_USB_PID_STLINK_V3S_PID 0x374f +#define STLINK_USB_PID_STLINK_V3_2VCP_PID 0x3753 #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 diff --git a/src/common.c b/src/common.c index 9a3098114..db0ab445e 100644 --- a/src/common.c +++ b/src/common.c @@ -892,23 +892,48 @@ int stlink_status(stlink_t *sl) { * @param sl stlink context, assumed to contain valid data in the buffer * @param slv output parsed version object */ -void _parse_version(stlink_t *sl, stlink_version_t *slv) { - uint32_t b0 = sl->q_buf[0]; //lsb - uint32_t b1 = sl->q_buf[1]; - uint32_t b2 = sl->q_buf[2]; - uint32_t b3 = sl->q_buf[3]; - uint32_t b4 = sl->q_buf[4]; - uint32_t b5 = sl->q_buf[5]; //msb - - // b0 b1 || b2 b3 | b4 b5 - // 4b | 6b | 6b || 2B | 2B - // stlink_v | jtag_v | swim_v || st_vid | stlink_pid - - slv->stlink_v = (b0 & 0xf0) >> 4; - slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); - slv->swim_v = b1 & 0x3f; - slv->st_vid = (b3 << 8) | b2; - slv->stlink_pid = (b5 << 8) | b4; +void _parse_version(stlink_t *sl, stlink_version_t *slv) +{ + sl->version.flags = 0; + if (sl->version.stlink_v < 3) { + uint32_t b0 = sl->q_buf[0]; //lsb + uint32_t b1 = sl->q_buf[1]; + uint32_t b2 = sl->q_buf[2]; + uint32_t b3 = sl->q_buf[3]; + uint32_t b4 = sl->q_buf[4]; + uint32_t b5 = sl->q_buf[5]; //msb + + // b0 b1 || b2 b3 | b4 b5 + // 4b | 6b | 6b || 2B | 2B + // stlink_v | jtag_v | swim_v || st_vid | stlink_pid + + slv->stlink_v = (b0 & 0xf0) >> 4; + slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); + slv->swim_v = b1 & 0x3f; + slv->st_vid = (b3 << 8) | b2; + slv->stlink_pid = (b5 << 8) | b4; + /* ST-LINK/V1 from J11 switch to api-v2 (and support SWD) */ + if (slv->stlink_v == 1) + slv->jtag_api = slv->jtag_v > 11? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; + else { + slv->jtag_api = STLINK_JTAG_API_V2; + /* preferred API to get last R/W status from J15 */ + if (sl->version.jtag_v >= 15) + sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + } + } else { + // V3 uses different version format, for reference see OpenOCD source + // (that was written from docs available from ST under NDA): + // https://github.com/ntfreak/openocd/blob/a6dacdff58ef36fcdac00c53ec27f19de1fbce0d/src/jtag/drivers/stlink_usb.c#L965 + slv->stlink_v = sl->q_buf[0]; + slv->swim_v = sl->q_buf[1]; + slv->jtag_v = sl->q_buf[2]; + slv->st_vid = (uint32_t)((sl->q_buf[9] << 8) | sl->q_buf[8]); + slv->stlink_pid = (uint32_t)((sl->q_buf[11] << 8) | sl->q_buf[10]); + slv->jtag_api = STLINK_JTAG_API_V3; + /* preferred API to get last R/W status */ + sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + } return; } @@ -1065,13 +1090,8 @@ int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct s bool stlink_is_core_halted(stlink_t *sl) { - bool ret = false; - - stlink_status(sl); - if (sl->q_buf[0] == STLINK_CORE_HALTED) - ret = true; - - return ret; + stlink_status(sl); + return sl->core_stat == TARGET_HALTED; } int stlink_step(stlink_t *sl) { @@ -1140,21 +1160,21 @@ void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { // this function is called by stlink_status() // do not call stlink_core_stat() directly, always use stlink_status() void stlink_core_stat(stlink_t *sl) { - if (sl->q_len <= 0) - return; - - switch (sl->q_buf[0]) { - case STLINK_CORE_RUNNING: - sl->core_stat = STLINK_CORE_RUNNING; + switch (sl->core_stat ) { + case TARGET_RUNNING: DLOG(" core status: running\n"); return; - case STLINK_CORE_HALTED: - sl->core_stat = STLINK_CORE_HALTED; + case TARGET_HALTED: DLOG(" core status: halted\n"); return; + case TARGET_RESET: + DLOG(" core status: reset\n"); + return; + case TARGET_DEBUG_RUNNING: + DLOG(" core status: debug running\n"); + return; default: - sl->core_stat = STLINK_CORE_STAT_UNKNOWN; - fprintf(stderr, " core status: unknown\n"); + DLOG(" core status: unknown\n"); } } @@ -1162,7 +1182,7 @@ void stlink_print_data(stlink_t * sl) { if (sl->q_len <= 0 || sl->verbose < UDEBUG) return; if (sl->verbose > 2) - fprintf(stdout, "data_len = %d 0x%x\n", sl->q_len, sl->q_len); + DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); for (int i = 0; i < sl->q_len; i++) { if (i % 16 == 0) { @@ -1173,9 +1193,9 @@ void stlink_print_data(stlink_t * sl) { fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); */ } - fprintf(stdout, " %02x", (unsigned int) sl->q_buf[i]); + DLOG(" %02x", (unsigned int) sl->q_buf[i]); } - fputs("\n\n", stdout); + DLOG("\n\n"); } /* memory mapped file */ @@ -2059,17 +2079,15 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t /* erase each page */ int page_count = 0; for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + (uint32_t) off)) { - /* addr must be an addr inside the page */ + // addr must be an addr inside the page if (stlink_erase_flash_page(sl, addr + (uint32_t) off) == -1) { ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); return -1; } - fprintf(stdout,"\rFlash page at addr: 0x%08lx erased", + ILOG("Flash page at addr: 0x%08lx erased\n", (unsigned long)(addr + off)); - fflush(stdout); page_count++; } - fprintf(stdout,"\n"); ILOG("Finished erasing %d pages of %d (%#x) bytes\n", page_count, sl->flash_pgsz, sl->flash_pgsz); diff --git a/src/flash_loader.c b/src/flash_loader.c index 73db427a7..eaf81019e 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -321,7 +321,9 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* } memcpy(sl->q_buf, loader_code, loader_size); - stlink_write_mem32(sl, sl->sram_base, loader_size); + int ret = stlink_write_mem32(sl, sl->sram_base, loader_size); + if (ret) + return ret; *addr = sl->sram_base; *size = loader_size; diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index bdfeb703d..2dfbc7454 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -1384,7 +1384,7 @@ int serve(stlink_t *sl, st_state_t *st) { } stlink_status(sl); - if(sl->core_stat == STLINK_CORE_HALTED) { + if(sl->core_stat == TARGET_HALTED) { struct stlink_reg reg; int ret; stm32_addr_t pc; diff --git a/src/logging.c b/src/logging.c index d4fb96b2e..d2ca11f2a 100644 --- a/src/logging.c +++ b/src/logging.c @@ -11,7 +11,7 @@ #include "stlink/logging.h" -static int max_level = UINFO; +static int max_level = UDEBUG; int ugly_init(int maximum_threshold) { max_level = maximum_threshold; diff --git a/src/sg.c b/src/sg.c index e7ff5d14e..4e8349bc2 100644 --- a/src/sg.c +++ b/src/sg.c @@ -435,7 +435,7 @@ int _stlink_sg_current_mode(stlink_t *stl) { int _stlink_sg_enter_swd_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); - sg->cdb_cmd_blk[1] = STLINK_DEBUG_ENTER; + sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_ENTER; sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_SWD; sl->q_len = 0; // >0 -> aboard return stlink_q(sl); @@ -448,7 +448,7 @@ int _stlink_sg_enter_jtag_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_enter_jtag_mode ***\n"); clear_cdb(sg); - sg->cdb_cmd_blk[1] = STLINK_DEBUG_ENTER; + sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_ENTER; sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_JTAG; sl->q_len = 0; return stlink_q(sl); @@ -529,7 +529,7 @@ int _stlink_sg_core_id(stlink_t *sl) { int _stlink_sg_reset(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); - sg->cdb_cmd_blk[1] = STLINK_DEBUG_RESETSYS; + sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_RESETSYS; sl->q_len = 2; sg->q_addr = 0; if (stlink_q(sl)) @@ -593,7 +593,7 @@ int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); - sg->cdb_cmd_blk[1] = STLINK_DEBUG_READALLREGS; + sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_READALLREGS; sl->q_len = 84; sg->q_addr = 0; if (stlink_q(sl)) @@ -634,7 +634,7 @@ int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { int _stlink_sg_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); - sg->cdb_cmd_blk[1] = STLINK_DEBUG_READREG; + sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_READREG; sg->cdb_cmd_blk[2] = r_idx; sl->q_len = 4; sg->q_addr = 0; @@ -679,7 +679,7 @@ int _stlink_sg_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { int _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int idx) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); - sg->cdb_cmd_blk[1] = STLINK_DEBUG_WRITEREG; + sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_WRITEREG; // 2: reg index // 3-6: reg content sg->cdb_cmd_blk[2] = idx; @@ -701,7 +701,7 @@ void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_write_dreg ***\n"); clear_cdb(sg); - sg->cdb_cmd_blk[1] = STLINK_DEBUG_WRITEDEBUGREG; + sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_WRITEDEBUGREG; // 2-5: address of reg of the debug module // 6-9: reg content write_uint32(sg->cdb_cmd_blk + 2, addr); @@ -750,7 +750,7 @@ void stlink_set_hw_bp(stlink_t *sl, int fp_nr, uint32_t addr, int fp) { DLOG("\n*** stlink_set_hw_bp ***\n"); struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); - sg->cdb_cmd_blk[1] = STLINK_DEBUG_SETFP; + sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_SETFP; // 2:The number of the flash patch used to set the breakpoint // 3-6: Address of the breakpoint (LSB) // 7: FP_ALL (0x02) / FP_UPPER (0x01) / FP_LOWER (0x00) @@ -770,7 +770,7 @@ void stlink_clr_hw_bp(stlink_t *sl, int fp_nr) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_clr_hw_bp ***\n"); clear_cdb(sg); - sg->cdb_cmd_blk[1] = STLINK_DEBUG_CLEARFP; + sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_CLEARFP; sg->cdb_cmd_blk[2] = fp_nr; sl->q_len = 2; @@ -1045,7 +1045,7 @@ static stlink_t* stlink_open(const int verbose) { sl->backend_data = slsg; sl->backend = &_stlink_sg_backend; - sl->core_stat = STLINK_CORE_STAT_UNKNOWN; + sl->core_stat = TARGET_UNKNOWN; slsg->q_addr = 0; return sl; diff --git a/src/tools/flash.c b/src/tools/flash.c index f5fd1a386..a8d937930 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -29,11 +29,11 @@ static void cleanup(int signum) { static void usage(void) { - puts("stlinkv1 command line: ./st-flash [--debug] [--reset] [--format ] [--flash=] {read|write} /dev/sgX "); - puts("stlinkv1 command line: ./st-flash [--debug] /dev/sgX erase"); - puts("stlinkv2 command line: ./st-flash [--debug] [--reset] [--serial ] [--format ] [--flash=] {read|write} "); - puts("stlinkv2 command line: ./st-flash [--debug] [--serial ] erase"); - puts("stlinkv2 command line: ./st-flash [--debug] [--serial ] reset"); + puts("stlinkv1 command line: ./st-flash [--debug] [--reset] [--format ] [--flash=] {read|write} /dev/sgX "); + puts("stlinkv1 command line: ./st-flash [--debug] /dev/sgX erase"); + puts("stlinkv2/3 command line: ./st-flash [--debug] [--reset] [--serial ] [--format ] [--flash=] {read|write} "); + puts("stlinkv2/3 command line: ./st-flash [--debug] [--serial ] erase"); + puts("stlinkv2/3 command line: ./st-flash [--debug] [--serial ] reset"); puts(" Use hex format for addr, and ."); puts(" fsize: Use decimal, octal or hex by prefix 0xXXX for hex, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); puts(" Format may be 'binary' (default) or 'ihex', although must be specified for binary format only."); diff --git a/src/usb.c b/src/usb.c index 7f5c21283..12945d6d2 100644 --- a/src/usb.c +++ b/src/usb.c @@ -22,6 +22,53 @@ enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; +static inline uint32_t le_to_h_u32(const uint8_t* buf) +{ + return (uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24); +} + +static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, uint32_t khz) +{ + unsigned int i; + int speed_index = -1; + int speed_diff = INT_MAX; + int last_valid_speed = -1; + bool match = true; + + for (i = 0; i < map_size; i++) { + if (!map[i]) + continue; + last_valid_speed = i; + if (khz == map[i]) { + speed_index = i; + break; + } else { + int current_diff = khz - map[i]; + /* get abs value for comparison */ + current_diff = (current_diff > 0) ? current_diff : -current_diff; + if ((current_diff < speed_diff) && khz >= map[i]) { + speed_diff = current_diff; + speed_index = i; + } + } + } + + if (speed_index == -1) { + /* this will only be here if we cannot match the slow speed. + * use the slowest speed we support.*/ + speed_index = last_valid_speed; + match = false; + } else if (i == map_size) + match = false; + + if (!match) { + ILOG("Unable to match requested speed %d kHz, using %d kHz\n", \ + khz, map[speed_index]); + } + + return speed_index; +} + void _stlink_usb_close(stlink_t* sl) { if (!sl) return; @@ -39,34 +86,34 @@ void _stlink_usb_close(stlink_t* sl) { } ssize_t send_recv(struct stlink_libusb* handle, int terminate, - unsigned char* txbuf, size_t txsize, - unsigned char* rxbuf, size_t rxsize) { + unsigned char* txbuf, size_t txsize, + unsigned char* rxbuf, size_t rxsize) { /* note: txbuf and rxbuf can point to the same area */ int res = 0; int t; t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, - txbuf, - (int) txsize, - &res, - 3000); + txbuf, + (int) txsize, + &res, + 3000); if (t) { printf("[!] send_recv send request failed: %s\n", libusb_error_name(t)); return -1; } else if ((size_t)res != txsize) { printf("[!] send_recv send request wrote %u bytes (instead of %u).\n", - (unsigned int)res, (unsigned int)txsize); + (unsigned int)res, (unsigned int)txsize); } if (rxsize != 0) { t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, - rxbuf, - (int) rxsize, - &res, - 3000); + rxbuf, + (int) rxsize, + &res, + 3000); if (t) { printf("[!] send_recv read reply failed: %s\n", - libusb_error_name(t)); + libusb_error_name(t)); return -1; } } @@ -75,13 +122,13 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, /* Read the SG reply */ unsigned char sg_buf[13]; t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, - sg_buf, - 13, - &res, - 3000); + sg_buf, + 13, + &res, + 3000); if (t) { printf("[!] send_recv read storage failed: %s\n", - libusb_error_name(t)); + libusb_error_name(t)); return -1; } /* The STLink doesn't seem to evaluate the sequence number */ @@ -135,6 +182,19 @@ int _stlink_usb_version(stlink_t *sl) { return (int) size; } + /* STLINK-V3 requires a specific command */ + if (sl->version.stlink_v == 3) { + rep_len = 12; + i = fill_command(sl, SG_DXFER_FROM_DEV, 16); + cmd[i++] = STLINK_APIV3_GET_VERSION_EX; + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size != rep_len) { + printf("[!] send_recv STLINK_APIV3_GET_VERSION_EX\n"); + return (int) size; + } + } + return 0; } @@ -207,6 +267,30 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { return 0; } +int _stlink_usb_get_rw_status(stlink_t *sl) +{ + if (sl->version.jtag_api == STLINK_JTAG_API_V1) + return -1; + + unsigned char* const rdata = sl->q_buf; + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + int i, ret = 0; + + i = fill_command(sl, SG_DXFER_FROM_DEV, 12); + cmd[i++] = STLINK_DEBUG_COMMAND; + if (sl->version.flags & STLINK_F_HAS_GETLASTRWSTATUS2) { + cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS2; + ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 12); + } else { + cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS; + ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2); + } + if (ret < 0) + return -1; + return 0; +} + int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; @@ -221,12 +305,11 @@ int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { ret = send_only(slu, 0, cmd, slu->cmd_len); if (ret == -1) return ret; - - ret = send_only(slu, 1, data, len); + ret = send_only(slu, 0, data, len); if (ret == -1) return ret; - return 0; + return _stlink_usb_get_rw_status(sl); } int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -274,11 +357,14 @@ int _stlink_usb_core_id(stlink_t * sl) { unsigned char* const cmd = sl->c_buf; unsigned char* const data = sl->q_buf; ssize_t size; - int rep_len = 4; + int rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 12; int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_READCOREID; + if (sl->version.jtag_api == STLINK_JTAG_API_V1) + cmd[i++] = STLINK_DEBUG_READCOREID; + else + cmd[i++] = STLINK_DEBUG_APIV2_READ_IDCODES; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { @@ -286,11 +372,39 @@ int _stlink_usb_core_id(stlink_t * sl) { return -1; } - sl->core_id = read_uint32(data, 0); + if (sl->version.jtag_api == STLINK_JTAG_API_V1) + sl->core_id = read_uint32(data, 0); + else + sl->core_id = read_uint32(data, 4); return 0; } +int _stlink_usb_status_v2(stlink_t *sl) +{ + int result; + uint32_t status; + + result = _stlink_usb_read_debug32(sl, DCB_DHCSR, &status); + DLOG("core status: %08X\n", status); + if (result != 0) { + sl->core_stat = TARGET_UNKNOWN; + } else { + if (status & S_HALT) { + sl->core_stat = TARGET_HALTED; + } else if (status & S_RESET_ST) { + sl->core_stat = TARGET_RESET; + } else { + sl->core_stat = TARGET_RUNNING; + } + } + + return result; +} int _stlink_usb_status(stlink_t * sl) { + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { + return _stlink_usb_status_v2(sl); + } + struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -307,6 +421,14 @@ int _stlink_usb_status(stlink_t * sl) { return (int) size; } sl->q_len = (int) size; + if (sl->q_len > 1) { + if (sl->q_buf[0] == STLINK_CORE_RUNNING) + sl->core_stat = TARGET_RUNNING; + else if (sl->q_buf[0] == STLINK_CORE_HALTED) + sl->core_stat = TARGET_HALTED; + else + sl->core_stat = TARGET_UNKNOWN; + } return 0; } @@ -334,14 +456,19 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; ssize_t size; - const int rep_len = 0; + unsigned char* const data = sl->q_buf; + const uint32_t rep_len = sl->version.stlink_v > 1 ? 2 : 0; int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_ENTER; + cmd[i++] = sl->version.jtag_api == STLINK_JTAG_API_V1 ? STLINK_DEBUG_APIV1_ENTER : STLINK_DEBUG_APIV2_ENTER; cmd[i++] = STLINK_DEBUG_ENTER_SWD; - size = send_only(slu, 1, cmd, slu->cmd_len); + if (rep_len == 0) { + size = send_only(slu, 1, cmd, slu->cmd_len); + } else { + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + } if (size == -1) { printf("[!] send_recv STLINK_DEBUG_ENTER\n"); return (int) size; @@ -378,7 +505,10 @@ int _stlink_usb_reset(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_RESETSYS; + if (sl->version.jtag_api == STLINK_JTAG_API_V1) + cmd[i++] = STLINK_DEBUG_APIV1_RESETSYS; + else + cmd[i++] = STLINK_DEBUG_APIV2_RESETSYS; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { @@ -388,7 +518,7 @@ int _stlink_usb_reset(stlink_t * sl) { // Reset through AIRCR so NRST does not need to be connected return stlink_write_debug32(sl, STLINK_REG_AIRCR, - STLINK_REG_AIRCR_VECTKEY | STLINK_REG_AIRCR_SYSRESETREQ); + STLINK_REG_AIRCR_VECTKEY | STLINK_REG_AIRCR_SYSRESETREQ); } @@ -440,6 +570,14 @@ int _stlink_usb_step(stlink_t* sl) { */ int _stlink_usb_run(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; + + int res; + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { + res = _stlink_usb_write_debug32(sl, DCB_DHCSR, DBGKEY|C_DEBUGEN); + return res; + } + + unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; @@ -466,9 +604,8 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { ssize_t size; int rep_len = 2; int i; - // clock speed only supported by stlink/v2 and for firmware >= 22 - if (sl->version.stlink_v >= 2 && sl->version.jtag_v >= 22) { + if (sl->version.stlink_v == 2 && sl->version.jtag_v >= 22) { i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -483,9 +620,55 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { } return 0; - } else { - return -1; + } else if (sl->version.stlink_v == 3) { + int speed_index; + uint32_t map[STLINK_V3_MAX_FREQ_NB]; + i = fill_command(sl, SG_DXFER_FROM_DEV, 16); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_APIV3_GET_COM_FREQ; + cmd[i++] = 0; // SWD mode + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52); + if (size == -1) { + printf("[!] send_recv STLINK_APIV3_GET_COM_FREQ\n"); + return (int) size; + } + + int speeds_size = data[8]; + + if (speeds_size > STLINK_V3_MAX_FREQ_NB) + speeds_size = STLINK_V3_MAX_FREQ_NB; + + for (i = 0; i < speeds_size; i++) + map[i] = le_to_h_u32(&data[12 + 4 * i]); + + /* set to zero all the next entries */ + for (i = speeds_size; i < STLINK_V3_MAX_FREQ_NB; i++) + map[i] = 0; + + speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), 1800); + + i = fill_command(sl, SG_DXFER_FROM_DEV, 16); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_APIV3_SET_COM_FREQ; + cmd[i++] = 0; // SWD mode + cmd[i++] = 0; + cmd[i++] = (uint8_t)((map[speed_index] >> 0) & 0xFF); + cmd[i++] = (uint8_t)((map[speed_index] >> 8) & 0xFF); + cmd[i++] = (uint8_t)((map[speed_index] >> 16) & 0xFF); + cmd[i++] = (uint8_t)((map[speed_index] >> 24) & 0xFF); + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8); + if (size == -1) { + printf("[!] send_recv STLINK_APIV3_SET_COM_FREQ\n"); + return (int) size; + } + + return 0; } + return -1; } int _stlink_usb_exit_debug_mode(stlink_t *sl) { @@ -535,33 +718,40 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { unsigned char* const cmd = sl->c_buf; unsigned char* const data = sl->q_buf; ssize_t size; - uint32_t rep_len = 84; + uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 84 : 88; int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_READALLREGS; + if (sl->version.jtag_api == STLINK_JTAG_API_V1) + cmd[i++] = STLINK_DEBUG_APIV1_READALLREGS; + else + cmd[i++] = STLINK_DEBUG_APIV2_READALLREGS; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv STLINK_DEBUG_READALLREGS\n"); return (int) size; } + + /* V1: regs data from offset 0 */ + /* V2: status at offset 0, regs data from offset 4 */ + int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; sl->q_len = (int) size; stlink_print_data(sl); - for(i=0; i<16; i++) + for(i=reg_offset; i<16; i++) regp->r[i]= read_uint32(sl->q_buf, i*4); - regp->xpsr = read_uint32(sl->q_buf, 64); - regp->main_sp = read_uint32(sl->q_buf, 68); - regp->process_sp = read_uint32(sl->q_buf, 72); - regp->rw = read_uint32(sl->q_buf, 76); - regp->rw2 = read_uint32(sl->q_buf, 80); + regp->xpsr = read_uint32(sl->q_buf, reg_offset + 64); + regp->main_sp = read_uint32(sl->q_buf, reg_offset + 68); + regp->process_sp = read_uint32(sl->q_buf, reg_offset + 72); + regp->rw = read_uint32(sl->q_buf, reg_offset + 76); + regp->rw2 = read_uint32(sl->q_buf, reg_offset + 80); if (sl->verbose < 2) return 0; - DLOG("xpsr = 0x%08x\n", read_uint32(sl->q_buf, 64)); - DLOG("main_sp = 0x%08x\n", read_uint32(sl->q_buf, 68)); - DLOG("process_sp = 0x%08x\n", read_uint32(sl->q_buf, 72)); - DLOG("rw = 0x%08x\n", read_uint32(sl->q_buf, 76)); - DLOG("rw2 = 0x%08x\n", read_uint32(sl->q_buf, 80)); + DLOG("xpsr = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 64)); + DLOG("main_sp = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 68)); + DLOG("process_sp = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 72)); + DLOG("rw = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 76)); + DLOG("rw2 = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 80)); return 0; } @@ -572,11 +762,15 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t r; - uint32_t rep_len = 4; + uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 8; + int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_READREG; + if (sl->version.jtag_api == STLINK_JTAG_API_V1) + cmd[i++] = STLINK_DEBUG_APIV1_READREG; + else + cmd[i++] = STLINK_DEBUG_APIV2_READREG; cmd[i++] = (uint8_t) r_idx; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { @@ -585,7 +779,7 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { } sl->q_len = (int) size; stlink_print_data(sl); - r = read_uint32(sl->q_buf, 0); + r = read_uint32(sl->q_buf, reg_offset); DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); switch (r_idx) { @@ -723,7 +917,10 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_WRITEREG; + if (sl->version.jtag_api == STLINK_JTAG_API_V1) + cmd[i++] = STLINK_DEBUG_APIV1_WRITEREG; + else + cmd[i++] = STLINK_DEBUG_APIV2_WRITEREG; cmd[i++] = idx; write_uint32(&cmd[i], reg); size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); @@ -731,7 +928,7 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { printf("[!] send_recv STLINK_DEBUG_WRITEREG\n"); return (int) size; } -sl->q_len = (int) size; + sl->q_len = (int) size; stlink_print_data(sl); return 0; @@ -785,7 +982,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST sl->backend = &_stlink_usb_backend; sl->backend_data = slu; - sl->core_stat = STLINK_CORE_STAT_UNKNOWN; + sl->core_stat = TARGET_UNKNOWN; if (libusb_init(&(slu->libusb_ctx))) { WLOG("failed to init libusb context, wrong version of libraries?\n"); goto on_error; @@ -822,36 +1019,54 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST if (devBus && devAddr) { if ((libusb_get_bus_number(list[cnt]) != devBus) - || (libusb_get_device_address(list[cnt]) != devAddr)) { + || (libusb_get_device_address(list[cnt]) != devAddr)) { continue; } } - if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) || (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO) || (desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO)) { + if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) + || (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO) + || (desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO) + || (desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER) + || (desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID) + || (desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID) + || (desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID)) { struct libusb_device_handle *handle; ret = libusb_open(list[cnt], &handle); if (ret) - continue; + continue; sl->serial_size = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)sl->serial, sizeof(sl->serial)); libusb_close(handle); + if ((desc.idProduct == STLINK_USB_PID_STLINK_32L) + || (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO) + || (desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO)) { + sl->version.stlink_v = 2; + } else if ((desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER) + || (desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID) + || (desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID) + || (desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID)) { + sl->version.stlink_v = 3; + } + if ((serial == NULL) || (*serial == 0)) - break; + break; if (sl->serial_size < 0) - continue; + continue; if (memcmp(serial, &sl->serial, sl->serial_size) == 0) - break; + break; continue; } if (desc.idProduct == STLINK_USB_PID_STLINK) { slu->protocoll = 1; + sl->version.stlink_v = 1; break; } } @@ -901,7 +1116,12 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST // TODO - could use the scanning techniq from stm8 code here... slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; - if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO || desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO) { + if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO + || desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO + || desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER + || desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID + || desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID + || desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID) { slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; } else { slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; @@ -911,21 +1131,23 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST // TODO - never used at the moment, always CMD_SIZE slu->cmd_len = (slu->protocoll == 1)? STLINK_SG_SIZE: STLINK_CMD_SIZE; + // Initialize stlink version (sl->version) + stlink_version(sl); + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { ILOG("-- exit_dfu_mode\n"); stlink_exit_dfu_mode(sl); } + // set the speed before entering the mode + // as the chip discovery phase should be done at this speed too + // Set the stlink clock speed (default is 1800kHz) + stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } - - // Initialize stlink version (sl->version) - stlink_version(sl); - // Set the stlink clock speed (default is 1800kHz) - stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); - if (reset) { if( sl->version.stlink_v > 1 ) stlink_jtag_reset(sl, 2); stlink_reset(sl); @@ -972,9 +1194,13 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { break; } - if (desc.idProduct != STLINK_USB_PID_STLINK_32L && - desc.idProduct != STLINK_USB_PID_STLINK_32L_AUDIO && - desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO) + if (desc.idProduct != STLINK_USB_PID_STLINK_32L + && desc.idProduct != STLINK_USB_PID_STLINK_32L_AUDIO + && desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO + && desc.idProduct != STLINK_USB_PID_STLINK_V3_USBLOADER + && desc.idProduct != STLINK_USB_PID_STLINK_V3E_PID + && desc.idProduct != STLINK_USB_PID_STLINK_V3S_PID + && desc.idProduct != STLINK_USB_PID_STLINK_V3_2VCP_PID) continue; slcnt++; @@ -997,9 +1223,9 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { break; } - if (desc.idProduct != STLINK_USB_PID_STLINK_32L && - desc.idProduct != STLINK_USB_PID_STLINK_32L_AUDIO && - desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO) + if (desc.idProduct != STLINK_USB_PID_STLINK_32L && + desc.idProduct != STLINK_USB_PID_STLINK_32L_AUDIO && + desc.idProduct != STLINK_USB_PID_STLINK_NUCLEO) continue; struct libusb_device_handle* handle; @@ -1014,7 +1240,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { ret = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)&serial, sizeof(serial)); if (ret < 0) - *serial = 0; + *serial = 0; libusb_close(handle); From 1752c123b4633521e0c04baa4c60ea59c61228a5 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Wed, 22 Apr 2020 14:54:42 +0800 Subject: [PATCH 0866/1435] Fix issue 663 with enhanced error output --- src/common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/common.c b/src/common.c index 0dc6bc967..50f87f42c 100644 --- a/src/common.c +++ b/src/common.c @@ -949,7 +949,7 @@ int stlink_load_device_params(stlink_t *sl) { sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, (unsigned int)sl->flash_pgsz); #else - ILOG("%s: %d KiB SRAM, %d KiB flash in %d %s pages.\n", + ILOG("%s: %zd KiB SRAM, %zd KiB flash in at least %zd %s pages.\n", params->description, sl->sram_size / 1024, sl->flash_size / 1024, (sl->flash_pgsz < 1024)? sl->flash_pgsz : sl->flash_pgsz/1024, (sl->flash_pgsz < 1024)? "byte" : "KiB"); @@ -2223,7 +2223,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t WLOG("unaligned len 0x%x -- padding with zero\n", len); len += 1; } else if (addr & (sl->flash_pgsz - 1)) { - ELOG("addr not a multiple of pagesize, not supported\n"); + ELOG("addr not a multiple of current pagesize (%zd bytes), not supported\n", sl->flash_pgsz); return -1; } From 4a2881413af584bc53a19789c4e317d0ec2be9a2 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 17 Apr 2020 11:20:29 +0200 Subject: [PATCH 0867/1435] common: add some flash option lock/unlock helpers --- src/common.c | 180 +++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 174 insertions(+), 6 deletions(-) diff --git a/src/common.c b/src/common.c index afeb6106a..2f226f016 100644 --- a/src/common.c +++ b/src/common.c @@ -1,5 +1,4 @@ #define DEBUG_FLASH 0 - #include #include #include @@ -35,6 +34,7 @@ #define FLASH_ACR (FLASH_REGS_ADDR + 0x00) #define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) +#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) #define FLASH_SR (FLASH_REGS_ADDR + 0x0c) #define FLASH_CR (FLASH_REGS_ADDR + 0x10) #define FLASH_AR (FLASH_REGS_ADDR + 0x14) @@ -56,6 +56,12 @@ #define FLASH_OPTKEY1 0x08192A3B #define FLASH_OPTKEY2 0x4C5D6E7F +#define FLASH_F0_OPTKEY1 0x45670123 +#define FLASH_F0_OPTKEY2 0xCDEF89AB + +#define FLASH_L0_OPTKEY1 0xFBEAD9C8 +#define FLASH_L0_OPTKEY2 0x24252627 + #define FLASH_SR_BSY 0 #define FLASH_SR_EOP 5 @@ -64,6 +70,7 @@ #define FLASH_CR_MER 2 #define FLASH_CR_STRT 6 #define FLASH_CR_LOCK 7 +#define FLASH_CR_OPTWRE 9 //32L = 32F1 same CoreID as 32F4! @@ -167,6 +174,7 @@ // WB Flash control register. #define STM32WB_FLASH_CR_STRT (16) /* FLASH_CR Start */ +#define STM32WB_FLASH_CR_OPTLOCK (30) /* FLASH_CR Option Lock */ #define STM32WB_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ // WB Flash status register. #define STM32WB_FLASH_SR_BSY (16) /* FLASH_SR Busy */ @@ -230,8 +238,9 @@ #define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) #define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) #define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) -#define FLASH_F4_OPT_CR (FLASH_F4_REGS_ADDR + 0x14) -#define FLASH_F4_OPT_LOCK_BIT (1u << 0) +#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) +#define FLASH_F4_OPTCR_LOCK 0 +#define FLASH_F4_OPTCR_START 1 #define FLASH_F4_CR_STRT 16 #define FLASH_F4_CR_LOCK 31 #define FLASH_F4_CR_SER 1 @@ -301,6 +310,19 @@ uint32_t read_uint32(const unsigned char *c, const int pt) { return ui; } +static uint32_t get_stm32l0_flash_base(stlink_t *sl) +{ + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_L1_CAT2: + case STLINK_CHIPID_STM32_L1_MEDIUM: + case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS: + case STLINK_CHIPID_STM32_L1_HIGH: + return STM32L1_FLASH_REGS_ADDR; + default: + return STM32L0_FLASH_REGS_ADDR; + } +} + static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { uint32_t rdp; stlink_read_debug32(sl, FLASH_WRPR, &rdp); @@ -386,9 +408,8 @@ static void unlock_flash(stlink_t *sl) { } } +/* unlock flash if already locked */ static int unlock_flash_if(stlink_t *sl) { - /* unlock flash if already locked */ - if (is_flash_locked(sl)) { unlock_flash(sl); if (is_flash_locked(sl)) { @@ -430,6 +451,154 @@ static void lock_flash(stlink_t *sl) { } } +static bool is_flash_option_locked(stlink_t *sl) { + uint32_t optlock_shift, optcr_reg; + int active_bit_level = 1; + uint32_t n; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; /* bit is "option write enable", not lock */ + break; + case STLINK_FLASH_TYPE_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_L0: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STLINK_FLASH_TYPE_L4: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_WB: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + default: + return -1; + } + + stlink_read_debug32(sl, optcr_reg, &n); + + if (active_bit_level == 0) + return !(n & (1u << optlock_shift)); + return n & (1u << optlock_shift); + +} + +static int lock_flash_option(stlink_t *sl) { + uint32_t optlock_shift, optcr_reg, n; + int active_bit_level = 1; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; + break; + case STLINK_FLASH_TYPE_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_L0: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STLINK_FLASH_TYPE_L4: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_WB: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + + default: + return -1; + } + + stlink_read_debug32(sl, optcr_reg, &n); + if (active_bit_level == 0) + n &= ~(1u << optlock_shift); + else + n |= (1u << optlock_shift); + stlink_write_debug32(sl, optcr_reg, n); + + return 0; +} + +static int unlock_flash_option(stlink_t *sl) +{ + uint32_t optkey_reg; + uint32_t optkey1 = FLASH_OPTKEY1; + uint32_t optkey2 = FLASH_OPTKEY2; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optkey_reg = FLASH_OPTKEYR; + optkey1 = FLASH_F0_OPTKEY1; + optkey2 = FLASH_F0_OPTKEY2; + break; + case STLINK_FLASH_TYPE_F4: + optkey_reg = FLASH_F4_OPT_KEYR; + break; + case STLINK_FLASH_TYPE_L0: + optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; + optkey1 = FLASH_L0_OPTKEY1; + optkey2 = FLASH_L0_OPTKEY2; + break; + case STLINK_FLASH_TYPE_L4: + optkey_reg = STM32L4_FLASH_OPTKEYR; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optkey_reg = STM32Gx_FLASH_OPTKEYR; + break; + case STLINK_FLASH_TYPE_WB: + optkey_reg = STM32WB_FLASH_OPT_KEYR; + break; + + default: + return -1; + } + + stlink_write_debug32(sl, optkey_reg, optkey1); + stlink_write_debug32(sl, optkey_reg, optkey2); + + return 0; +} + +static int unlock_flash_option_if(stlink_t *sl) { + if (is_flash_option_locked(sl)) { + if (unlock_flash_option(sl)) { + ELOG("Could not unlock flash option!\n"); + return -1; + } + if (is_flash_option_locked(sl)) { + ELOG("Failed to unlock flash option!\n"); + return -1; + } + } + DLOG("Successfully unlocked flash option\n"); + return 0; +} static void set_flash_cr_pg(stlink_t *sl) { uint32_t cr_reg, x; @@ -3307,7 +3476,6 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui ELOG("Option bytes writing is currently not implemented for connected chip\n"); return -1; } - } /** From 29cfb7deb6d5c253f93c10c27965aa3bd1aa3912 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 20 Apr 2020 17:40:30 +0200 Subject: [PATCH 0868/1435] common: add some l0/l1 support in helpers give l0/l1 some love - l0/l1 are a bit specific regarding keys, bits, and lock registers. Also make handling of f0/f1 explicit: ultimate goal is to have some sanity check and clear codepath in that code in case some new target is added - and that the whole code uses these helpers. some work should be done to refactor a bit the flash register mapping based on family, but not yet. lo lock --- src/common.c | 101 +++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 73 insertions(+), 28 deletions(-) diff --git a/src/common.c b/src/common.c index 2f226f016..6281d5332 100644 --- a/src/common.c +++ b/src/common.c @@ -53,6 +53,12 @@ #define FLASH_KEY1 0x45670123 #define FLASH_KEY2 0xcdef89ab +#define FLASH_L0_PRGKEY1 0x8c9daebf +#define FLASH_L0_PRGKEY2 0x13141516 + +#define FLASH_L0_PEKEY1 0x89abcdef +#define FLASH_L0_PEKEY2 0x02030405 + #define FLASH_OPTKEY1 0x08192A3B #define FLASH_OPTKEY2 0x4C5D6E7F @@ -363,48 +369,74 @@ static inline uint32_t read_flash_cr2(stlink_t *sl) { static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ - uint32_t cr_lock_shift, cr = read_flash_cr(sl); + uint32_t cr_lock_shift; + uint32_t cr_reg; + uint32_t n; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; - else if (sl->flash_type == STLINK_FLASH_TYPE_L4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + cr_lock_shift = STM32L0_FLASH_PELOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - else - cr_lock_shift = FLASH_CR_LOCK; + } else { + return -1; + } - return cr & (1u << cr_lock_shift); + stlink_read_debug32(sl, cr_reg, &n); + return n & (1u << cr_lock_shift); } static void unlock_flash(stlink_t *sl) { uint32_t key_reg; + uint32_t flash_key1 = FLASH_KEY1; + uint32_t flash_key2 = FLASH_KEY2; /* the unlock sequence consists of 2 write cycles where 2 key values are written to the FLASH_KEYR register. an invalid sequence results in a definitive lock of the FPEC block until next reset. */ - if (sl->flash_type == STLINK_FLASH_TYPE_F4) + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + key_reg = FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { key_reg = FLASH_F4_KEYR; - else if (sl->flash_type == STLINK_FLASH_TYPE_L4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; + flash_key1 = FLASH_L0_PEKEY1; + flash_key2 = FLASH_L0_PEKEY2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { key_reg = STM32L4_FLASH_KEYR; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { key_reg = STM32Gx_FLASH_KEYR; - else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { key_reg = STM32WB_FLASH_KEYR; - else - key_reg = FLASH_KEYR; + } else { + return; + } - stlink_write_debug32(sl, key_reg, FLASH_KEY1); - stlink_write_debug32(sl, key_reg, FLASH_KEY2); + stlink_write_debug32(sl, key_reg, flash_key1); + stlink_write_debug32(sl, key_reg, flash_key2); if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - stlink_write_debug32(sl, FLASH_KEYR2, FLASH_KEY1); - stlink_write_debug32(sl, FLASH_KEYR2, FLASH_KEY2); + stlink_write_debug32(sl, FLASH_KEYR2, flash_key1); + stlink_write_debug32(sl, FLASH_KEYR2, flash_key2); } } @@ -424,9 +456,16 @@ static int unlock_flash_if(stlink_t *sl) { static void lock_flash(stlink_t *sl) { uint32_t cr_lock_shift, cr_reg, n; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STLINK_FLASH_TYPE_F0 || + sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + cr_lock_shift = STM32L0_FLASH_PELOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; @@ -438,11 +477,11 @@ static void lock_flash(stlink_t *sl) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; } else { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; + return; } - n = read_flash_cr(sl) | (1u << cr_lock_shift); + stlink_read_debug32(sl, cr_reg, &n); + n |= (1u << cr_lock_shift); stlink_write_debug32(sl, cr_reg, n); if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { @@ -795,7 +834,11 @@ static void set_flash_cr2_strt(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res, sr_reg; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) + sr_reg = FLASH_SR; + else if (sl->flash_type == STLINK_FLASH_TYPE_L0) + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + else if (sl->flash_type == STLINK_FLASH_TYPE_F4) sr_reg = FLASH_F4_SR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) sr_reg = STM32L4_FLASH_SR; @@ -805,7 +848,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { else if (sl->flash_type == STLINK_FLASH_TYPE_WB) sr_reg = STM32WB_FLASH_SR; else - sr_reg = FLASH_SR; + return -1; stlink_read_debug32(sl, sr_reg, &res); @@ -822,7 +865,9 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; unsigned int res; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_L0)) + sr_busy_shift = FLASH_SR_BSY; + else if (sl->flash_type == STLINK_FLASH_TYPE_F4) sr_busy_shift = FLASH_F4_SR_BSY; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) sr_busy_shift = STM32L4_FLASH_SR_BSY; @@ -832,7 +877,7 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { else if (sl->flash_type == STLINK_FLASH_TYPE_WB) sr_busy_shift = STM32WB_FLASH_SR_BSY; else - sr_busy_shift = FLASH_SR_BSY; + return -1; res = read_flash_sr(sl) & (1 << sr_busy_shift); From 2cff67a59bf959a4c1dea9863b47401748ec0e5e Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 20 Apr 2020 15:57:48 +0200 Subject: [PATCH 0869/1435] update f2 and f4 option read/write code routines 1) no need to unlock option flash to read it. "The option byte are always read-accessible and write-protected by default." current device specific option read code now only differs from generic read code by reading option bytes in the flash option byte register instead of option base. 2) f4 and f2 have similar registers : use the same write code, with flash/option lock helpers. add flash busy wait and relock at end of access. 3) add f446 option info to chip id --- src/chipid.c | 4 +- src/common.c | 168 +++++++-------------------------------------------- 2 files changed, 26 insertions(+), 146 deletions(-) diff --git a/src/chipid.c b/src/chipid.c index 60d0787e9..ee85aaf65 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -218,7 +218,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x20000, .sram_size = 0x20000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, + .option_size = 4, }, { // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. diff --git a/src/common.c b/src/common.c index 6281d5332..6770aca3f 100644 --- a/src/common.c +++ b/src/common.c @@ -3235,62 +3235,6 @@ static int stlink_write_option_bytes_l496x(stlink_t *sl, uint8_t* base, stm32_ad } -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_f2(stlink_t *sl, uint8_t *base, stm32_addr_t addr, size_t len) { - uint32_t val; - uint32_t option_byte; - - (void) addr; - (void) len; - - option_byte = *(uint32_t*) (base); - - stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); - if (val & FLASH_F2_OPT_LOCK_BIT) { - WLOG("Unlocking option flash\n"); - //Unlock the FLASH_OPT_CR register (FLASH Programming manual page 15) - //https://www.st.com/resource/en/programming_manual/cd00233952.pdf - stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, FLASH_OPTKEY1); - stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, FLASH_OPTKEY2); - - stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); - if (val & FLASH_F2_OPT_LOCK_BIT) { - ELOG("Option flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } - } - - stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); - WLOG("option bytes CR = %x\n",val); - - stlink_write_debug32(sl, FLASH_F2_OPT_CR, option_byte & 0x0FFFFFFC); - - stlink_write_debug32(sl, FLASH_F2_OPT_CR, (option_byte & 0x0FFFFFFC)|0x00000002); - - - stlink_read_debug32(sl, FLASH_F2_SR, &val); - WLOG("wait BSY flag to be 0\n"); - - while (val & 0x00010000){ - stlink_read_debug32(sl, FLASH_F2_SR, &val); - } - WLOG("BSY flag is 0\n"); - - stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); - WLOG("option bytes CR = %x\n",val); - WLOG("Option flash re-lock\n"); - stlink_write_debug32(sl, FLASH_F2_OPT_CR, val | 0x00000001); - - DLOG("STM32 F2 option bytes are written\n"); - - return 0; -} - /** * Write option bytes * @param sl @@ -3298,52 +3242,37 @@ static int stlink_write_option_bytes_f2(stlink_t *sl, uint8_t *base, stm32_addr_ * @return 0 on success, -ve on failure. */ static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - uint32_t val; uint32_t option_byte; (void) addr; (void) len; - option_byte = *(uint32_t*) (base); - - stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); - if (val & FLASH_F4_OPT_LOCK_BIT) { - WLOG("Unlocking option flash\n"); - //Unlock the FLASH_OPT_CR register (FLASH Programming manual page 15) - //https://www.st.com/resource/en/programming_manual/cd00233952.pdf - stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, FLASH_OPTKEY1); - stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, FLASH_OPTKEY2); + wait_flash_busy(sl); - stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); - if (val & FLASH_F4_OPT_LOCK_BIT) { - ELOG("Option flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; } - stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); - WLOG("option bytes CR = %x\n",val); - - stlink_write_debug32(sl, FLASH_F4_OPT_CR, option_byte & 0x0FFFFFFC); + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); - stlink_write_debug32(sl, FLASH_F4_OPT_CR, (option_byte & 0x0FFFFFFC)|0x00000002); + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F4_OPTCR, (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | (1 << FLASH_F4_OPTCR_START)); - stlink_read_debug32(sl, FLASH_F4_SR, &val); - WLOG("wait BSY flag to be 0\n"); + wait_flash_busy(sl); - while (val & 0x00010000){ - stlink_read_debug32(sl, FLASH_F4_SR, &val); - } - WLOG("BSY flag is 0\n"); + check_flash_error(sl); - stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); - WLOG("option bytes CR = %x\n",val); - WLOG("Option flash re-lock\n"); - stlink_write_debug32(sl, FLASH_F4_OPT_CR, val | 0x00000001); + /* option bytes are reloaded at reset only, no obl. */ - DLOG("STM32 F4 option bytes are written\n"); + lock_flash_option(sl); + lock_flash(sl); - return 0; + return 0; } /** @@ -3352,11 +3281,8 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_ * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) -{ - uint32_t ret = stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); - WLOG("option bytes CR = %#010x\n", *option_byte); - return ret; +int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) { + return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); } /** @@ -3366,30 +3292,7 @@ int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) * @return 0 on success, -ve on failure. */ int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { - uint32_t val; - - stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); - if (val & FLASH_F2_OPT_LOCK_BIT) { - WLOG("Unlocking option flash\n"); - //Unlock the FLASH_OPT_CR register (FLASH Programming manual page 15) - //https://www.st.com/resource/en/programming_manual/cd00233952.pdf - stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, FLASH_OPTKEY1); - stlink_write_debug32(sl, FLASH_F2_OPT_KEYR, FLASH_OPTKEY2); - - stlink_read_debug32(sl, FLASH_F2_OPT_CR, &val); - if (val & FLASH_F2_OPT_LOCK_BIT) { - ELOG("Option flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } - } - - stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); - WLOG("option bytes CR = %x\n",option_byte); - - WLOG("Option flash re-lock\n"); - stlink_write_debug32(sl, FLASH_F2_OPT_CR, val | 0x00000001); - - return 0; + return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); } /** @@ -3399,39 +3302,15 @@ int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { * @return 0 on success, -ve on failure. */ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { - uint32_t val; - - stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); - if (val & FLASH_F4_OPT_LOCK_BIT) { - WLOG("Unlocking option flash\n"); - //Unlock the FLASH_OPT_CR register (FLASH Programming manual page 15) - //https://www.st.com/resource/en/programming_manual/cd00233952.pdf - stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, FLASH_OPTKEY1); - stlink_write_debug32(sl, FLASH_F4_OPT_KEYR, FLASH_OPTKEY2); - - stlink_read_debug32(sl, FLASH_F4_OPT_CR, &val); - if (val & FLASH_F4_OPT_LOCK_BIT) { - ELOG("Option flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } - } - - stlink_read_debug32(sl, FLASH_F4_OPT_CR, option_byte); - WLOG("option bytes CR = %x\n", option_byte); - - WLOG("Option flash re-lock\n"); - stlink_write_debug32(sl, FLASH_F4_OPT_CR, val | 0x00000001); - - return 0; + return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); } /** -* Read first option bytes + * Read first option bytes * @param sl * @param option_byte option value * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) -{ +int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { return stlink_read_debug32(sl, sl->option_base, option_byte); } @@ -3502,7 +3381,6 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui /* filter out on chip_id, until complete flash family are handled */ switch (sl->chip_id) { case STLINK_CHIPID_STM32_F2: - return stlink_write_option_bytes_f2(sl, base, addr, len); case STLINK_CHIPID_STM32_F446: return stlink_write_option_bytes_f4(sl, base, addr, len); case STLINK_CHIPID_STM32_L0_CAT2: From 9e53550d24a9434c4c01754cb5fd69f1f3fc705d Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 20 Apr 2020 15:57:40 +0200 Subject: [PATCH 0870/1435] update l4 option code to use helpers, based on l496. use generic unlock for l4, rename l496 to l4x, add wait flash busy, complete chip id for l476 (and other) --- src/chipid.c | 4 +++- src/common.c | 56 ++++++++++++++-------------------------------------- 2 files changed, 18 insertions(+), 42 deletions(-) diff --git a/src/chipid.c b/src/chipid.c index ee85aaf65..17cb4d546 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -53,7 +53,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x20000, .sram_size = 0x20000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, + .option_size = 4, }, { // PM0063 .chip_id = STLINK_CHIPID_STM32_F1_LOW, diff --git a/src/common.c b/src/common.c index 6770aca3f..79d346e46 100644 --- a/src/common.c +++ b/src/common.c @@ -78,8 +78,6 @@ #define FLASH_CR_LOCK 7 #define FLASH_CR_OPTWRE 9 - -//32L = 32F1 same CoreID as 32F4! #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) #define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) #define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) @@ -3162,43 +3160,23 @@ static int stlink_write_option_bytes_l1(stlink_t *sl, uint8_t* base, stm32_addr_ * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l496x(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t val; (void) addr; (void) len; - /* Unlock flash if necessary */ - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - if ((val & (1u << STM32L4_FLASH_CR_LOCK))) { - - /* disable flash write protection. */ - stlink_write_debug32(sl, STM32L4_FLASH_KEYR, 0x45670123); - stlink_write_debug32(sl, STM32L4_FLASH_KEYR, 0xCDEF89AB); + wait_flash_busy(sl); - // check that the lock is no longer set. - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - if ((val & (1u << STM32L4_FLASH_CR_LOCK))) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; } - /* Unlock option bytes if necessary (ref manuel page 61) */ - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - if ((val & (1 << STM32L4_FLASH_CR_OPTLOCK))) { - - /* disable option byte write protection. */ - stlink_write_debug32(sl, STM32L4_FLASH_OPTKEYR, FLASH_OPTKEY1); - stlink_write_debug32(sl, STM32L4_FLASH_OPTKEYR, FLASH_OPTKEY2); - - /* check that the lock is no longer set. */ - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - if ((val & (1 << STM32L4_FLASH_CR_OPTLOCK))) { - ELOG("Options bytes unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; } /* Write options bytes */ @@ -3213,23 +3191,18 @@ static int stlink_write_option_bytes_l496x(stlink_t *sl, uint8_t* base, stm32_ad stlink_write_debug32(sl, STM32L4_FLASH_CR, val); /* Wait for 'busy' bit in FLASH_SR to clear. */ - do { - stlink_read_debug32(sl, STM32L4_FLASH_SR, &val); - } while ((val & (1 << 16)) != 0); + wait_flash_busy(sl); + + check_flash_error(sl); /* apply options bytes immediate */ stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - /* Re-lock option bytes */ - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1u << STM32L4_FLASH_CR_OPTLOCK); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); /* Re-lock flash. */ - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1u << STM32L4_FLASH_CR_LOCK); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + lock_flash_option(sl); + lock_flash(sl); return 0; } @@ -3386,7 +3359,8 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui case STLINK_CHIPID_STM32_L0_CAT2: return stlink_write_option_bytes_l0_cat2(sl, base, addr, len); case STLINK_CHIPID_STM32_L496X: - return stlink_write_option_bytes_l496x(sl, base, addr, len); + case STLINK_CHIPID_STM32_L4: + return stlink_write_option_bytes_l4(sl, base, addr, len); case STLINK_CHIPID_STM32_L152_RE: case STLINK_CHIPID_STM32_L1_HIGH: return stlink_write_option_bytes_l1(sl, base, addr, len); From 70043c426cc8f590ace5b4997759721161bfa88c Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 20 Apr 2020 15:31:37 +0200 Subject: [PATCH 0871/1435] update gx option code: use helpers. --- src/common.c | 25 ++++++------------------- 1 file changed, 6 insertions(+), 19 deletions(-) diff --git a/src/common.c b/src/common.c index 79d346e46..0a29a5716 100644 --- a/src/common.c +++ b/src/common.c @@ -2958,25 +2958,16 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_ (void) addr; (void) len; + wait_flash_busy(sl); + if (unlock_flash_if(sl)) { ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); return -1; } - /* Unlock option bytes if necessary (ref manuel page 61) */ - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - if ((val & (1 << STM32Gx_FLASH_CR_OPTLOCK))) { - - /* disable option byte write protection. */ - stlink_write_debug32(sl, STM32Gx_FLASH_OPTKEYR, FLASH_OPTKEY1); - stlink_write_debug32(sl, STM32Gx_FLASH_OPTKEYR, FLASH_OPTKEY2); - - /* check that the lock is no longer set. */ - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - if ((val & (1 << STM32Gx_FLASH_CR_OPTLOCK))) { - ELOG("Options bytes unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; } /* Write options bytes */ @@ -3003,12 +2994,8 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_ val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - /* Re-lock option bytes */ - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1u << STM32Gx_FLASH_CR_OPTLOCK); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - /* Re-lock flash. */ + lock_flash_option(sl); lock_flash(sl); return 0; From f23de8741a27ed46ccff4b9fa7806fc278b5961e Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 20 Apr 2020 16:06:54 +0200 Subject: [PATCH 0872/1435] update l0/l1 option code: merge l0/l1, code is the same except flash base, add wait states and relock --- src/common.c | 168 ++++++++++++--------------------------------------- 1 file changed, 39 insertions(+), 129 deletions(-) diff --git a/src/common.c b/src/common.c index 0a29a5716..147fee1ea 100644 --- a/src/common.c +++ b/src/common.c @@ -24,8 +24,6 @@ #define __attribute__(x) #endif -/* todo: stm32l15xxx flash memory, pm0062 manual */ - /* stm32f FPEC flash controller interface, pm0063 manual */ // TODO - all of this needs to be abstracted out.... // STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) @@ -213,13 +211,14 @@ #define STM32L4_FLASH_OPTR_DUALBANK 21 -//STM32L0x flash register base and offsets -//same as 32L1 above -// RM0090 - DM00031020.pdf +//STM32L0x flash register base and offsets RM0090 - DM00031020.pdf #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32L0_FLASH_PELOCK_BIT (1u << 0) -#define STM32L0_FLASH_OPTLOCK_BIT (1u << 2) -#define STM32L0_FLASH_OBL_LAUNCH_BIT (1u << 18) +#define STM32L1_FLASH_REGS_ADDR ((uint32_t)0x40023c00) + +#define STM32L0_FLASH_PELOCK (0) +#define STM32L0_FLASH_OPTLOCK (2) +#define STM32L0_FLASH_OBL_LAUNCH (18) + #define FLASH_ACR_OFF ((uint32_t) 0x00) #define FLASH_PECR_OFF ((uint32_t) 0x04) #define FLASH_PDKEYR_OFF ((uint32_t) 0x08) @@ -230,12 +229,6 @@ #define FLASH_OBR_OFF ((uint32_t) 0x1c) #define FLASH_WRPR_OFF ((uint32_t) 0x20) -//STM32L1 -#define STM32L1_FLASH_REGS_ADDR ((uint32_t)0x40023c00) -#define STM32L1_FLASH_PELOCK_BIT (1u << 0) -#define STM32L1_FLASH_OPTLOCK_BIT (1u << 2) -#define STM32L1_FLASH_OBL_LAUNCH_BIT (1u << 18) - //STM32F4 #define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) #define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) @@ -268,7 +261,6 @@ #define FLASH_F2_CR_SNB_MASK 0x78 #define FLASH_F2_SR_BSY 16 - #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 @@ -3001,62 +2993,6 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_ return 0; } - -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_l0_cat2(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - - uint32_t val; - (void) addr; - (void) len; - - stlink_read_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); - if (val & STM32L0_FLASH_PELOCK_BIT) { - WLOG("Unlocking flash\n"); - //Unlock data EEPROM and the FLASH_PECR register (reference page 74) - stlink_write_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PEKEYR_OFF, 0x89ABCDEF); - stlink_write_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PEKEYR_OFF, 0x02030405); - - stlink_read_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); - if (val & STM32L0_FLASH_PELOCK_BIT) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } - } - - stlink_read_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); - if ((val & (STM32L0_FLASH_OPTLOCK_BIT))) { - WLOG("Unlocking options\n"); - //Unlock the Option bytes area (reference page 76) - stlink_write_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_OPTKEYR_OFF, 0xFBEAD9C8); - stlink_write_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_OPTKEYR_OFF, 0x24252627); - - stlink_read_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); - if (val & STM32L0_FLASH_OPTLOCK_BIT) { - ELOG("Options unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } - } - - /* Write options bytes */ - uint32_t data; - write_uint32((unsigned char*) &data, *(uint32_t*) (base)); - WLOG("Writing option bytes 0x%04x\n", data); - stlink_write_debug32(sl, STM32_L0_CATx_OPTION_BYTES_BASE, data); - - /* Reload options */ - stlink_read_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); - val |= (STM32L0_FLASH_OBL_LAUNCH_BIT); - stlink_write_debug32(sl, STM32L0_FLASH_REGS_ADDR + FLASH_PECR_OFF, val); - - return 0; -} - /** * Write option bytes * @param sl @@ -3064,78 +3000,51 @@ static int stlink_write_option_bytes_l0_cat2(stlink_t *sl, uint8_t* base, stm32_ * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l1(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - +static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) +{ + uint32_t flash_base = get_stm32l0_flash_base(sl); uint32_t val; uint32_t data; - stlink_read_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); - if (val & STM32L1_FLASH_PELOCK_BIT) { - WLOG("Unlocking flash\n"); - //Unlock data EEPROM and the FLASH_PECR register (reference page 74) - stlink_write_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_PEKEYR_OFF, 0x89ABCDEF); - stlink_write_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_PEKEYR_OFF, 0x02030405); + wait_flash_busy(sl); - stlink_read_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); - if (val & STM32L1_FLASH_PELOCK_BIT) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; } - stlink_read_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); - if ((val & (STM32L1_FLASH_OPTLOCK_BIT))) { - WLOG("Unlocking options\n"); - //Unlock the Option bytes area (reference page 76) - stlink_write_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_OPTKEYR_OFF, 0xFBEAD9C8); - stlink_write_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_OPTKEYR_OFF, 0x24252627); - - stlink_read_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); - if (val & STM32L1_FLASH_OPTLOCK_BIT) { - ELOG("Options unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; } - /* Clear errors */ - stlink_write_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_SR_OFF, 0x00003F00); + stlink_write_debug32(sl, flash_base + FLASH_SR_OFF, STM32L0_FLASH_REGS_ADDR); - stlink_read_debug32(sl, addr, &val); - WLOG("Option bytes 0x%08x is 0x%08x\n",addr,val); + while (len != 0) { + /* Write options bytes */ + write_uint32((unsigned char*) &data, *(uint32_t*) (base)); - /* Write options bytes */ - write_uint32((unsigned char*) &data, *(uint32_t*) (base)); - if ( data != val ) { - WLOG("Writing option bytes 0x%04x\n", data); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); stlink_write_debug32(sl, addr, data); - stlink_read_debug32(sl, addr, &val); - WLOG("Option bytes is 0x%08x\n",val); - } - - if (len==8) { - /* Clear errors */ - stlink_write_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_SR_OFF, 0x00003F00); - - stlink_read_debug32(sl, addr+4, &val); - WLOG("2nd option bytes 0x%08x is 0x%08x\n",addr,val); + wait_flash_busy(sl); - /* Write options bytes */ - write_uint32((unsigned char*) &data, *(uint32_t*) (base+4)); + if (check_flash_error(sl)) + break; - if ( data != val ) { - WLOG("Writing 2nd option bytes 0x%04x\n", data); - stlink_write_debug32(sl, addr+4, data); - stlink_read_debug32(sl, addr+4, &val); - WLOG("2nd option bytes is 0x%08x\n",val); - } + len-=4; + addr+=4; + base+=4; } /* Reload options */ - stlink_read_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_PECR_OFF, &val); - val |= (STM32L1_FLASH_OBL_LAUNCH_BIT); - stlink_write_debug32(sl, STM32L1_FLASH_REGS_ADDR + FLASH_PECR_OFF, val); + stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); + val |= (1 << STM32L0_FLASH_OBL_LAUNCH); + stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); + + lock_flash_option(sl); + lock_flash(sl); return 0; } @@ -3218,6 +3127,7 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_ ELOG("Flash option unlock failed!\n"); return -1; } + write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); /* write option byte, ensuring we dont lock opt, and set strt bit */ @@ -3344,13 +3254,13 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui case STLINK_CHIPID_STM32_F446: return stlink_write_option_bytes_f4(sl, base, addr, len); case STLINK_CHIPID_STM32_L0_CAT2: - return stlink_write_option_bytes_l0_cat2(sl, base, addr, len); + case STLINK_CHIPID_STM32_L0_CAT5: + case STLINK_CHIPID_STM32_L152_RE: + case STLINK_CHIPID_STM32_L1_HIGH: + return stlink_write_option_bytes_l0(sl, base, addr, len); case STLINK_CHIPID_STM32_L496X: case STLINK_CHIPID_STM32_L4: return stlink_write_option_bytes_l4(sl, base, addr, len); - case STLINK_CHIPID_STM32_L152_RE: - case STLINK_CHIPID_STM32_L1_HIGH: - return stlink_write_option_bytes_l1(sl, base, addr, len); case STLINK_CHIPID_STM32_G0_CAT1: case STLINK_CHIPID_STM32_G0_CAT2: case STLINK_CHIPID_STM32_G4_CAT2: From c4d9936976032cd863b7bce23ef2f25813ab2370 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Fri, 17 Apr 2020 16:23:47 +0200 Subject: [PATCH 0873/1435] common: implement flash check error for l0 and f0 --- src/common.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/src/common.c b/src/common.c index 147fee1ea..461e74a75 100644 --- a/src/common.c +++ b/src/common.c @@ -67,11 +67,16 @@ #define FLASH_L0_OPTKEY2 0x24252627 #define FLASH_SR_BSY 0 +#define FLASH_SR_PG_ERR 2 +#define FLASH_SR_WRPRT_ERR 4 #define FLASH_SR_EOP 5 +#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) + #define FLASH_CR_PG 0 #define FLASH_CR_PER 1 #define FLASH_CR_MER 2 +#define FLASH_CR_OPTPG 4 #define FLASH_CR_STRT 6 #define FLASH_CR_LOCK 7 #define FLASH_CR_OPTWRE 9 @@ -219,6 +224,8 @@ #define STM32L0_FLASH_OPTLOCK (2) #define STM32L0_FLASH_OBL_LAUNCH (18) +#define STM32L0_FLASH_SR_ERROR_MASK 0x00003F00 + #define FLASH_ACR_OFF ((uint32_t) 0x00) #define FLASH_PECR_OFF ((uint32_t) 0x04) #define FLASH_PDKEYR_OFF ((uint32_t) 0x08) @@ -902,10 +909,19 @@ static void wait_flash_busy_progress(stlink_t *sl) { static int check_flash_error(stlink_t *sl) { uint32_t res = 0; - if ((sl->flash_type == STLINK_FLASH_TYPE_G0) || - (sl->flash_type == STLINK_FLASH_TYPE_G4)) { - res = read_flash_sr(sl) & STM32Gx_FLASH_SR_ERROR_MASK; - } + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + res = read_flash_sr(sl) & FLASH_SR_ERROR_MASK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + res = read_flash_sr(sl) & STM32Gx_FLASH_SR_ERROR_MASK; + break; + case STLINK_FLASH_TYPE_L0: + res = read_flash_sr(sl) & STM32L0_FLASH_SR_ERROR_MASK; + default: + break; + } if (res) { ELOG("Flash programming error : %#010x\n", res); From a69a6fb68153e74bc93b397137be018c8dd0bb02 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Mon, 20 Apr 2020 18:35:45 +0200 Subject: [PATCH 0874/1435] use defines --- src/common.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/common.c b/src/common.c index 461e74a75..019e21756 100644 --- a/src/common.c +++ b/src/common.c @@ -2091,8 +2091,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); if ((val & (1<<0))||(val & (1<<1))) { /* disable pecr protection */ - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); /* check pecr.pelock is cleared */ stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -2102,8 +2102,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) } /* unlock program memory */ - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); /* check pecr.prglock is cleared */ stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -2603,8 +2603,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t /* todo: check write operation */ /* disable pecr protection */ - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x89abcdef); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, 0x02030405); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); /* check pecr.pelock is cleared */ stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -2614,8 +2614,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t } /* unlock program memory */ - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x8c9daebf); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, 0x13141516); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); /* check pecr.prglock is cleared */ stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); From 853468d1744d0c116bffa017e01f6d29ae735fdf Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 21 Apr 2020 10:27:40 +0200 Subject: [PATCH 0875/1435] common: whitespace fixes --- src/common.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/src/common.c b/src/common.c index 019e21756..e0c5fde2a 100644 --- a/src/common.c +++ b/src/common.c @@ -734,8 +734,8 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); if (sl->has_dual_bank) { - cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); - } + cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); + } cr_pg = (1 << FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; @@ -1100,7 +1100,7 @@ int stlink_load_device_params(stlink_t *sl) { sl->chip_id = 0x413; } - params = stlink_chipid_get_params(sl->chip_id); // chipid.c + params = stlink_chipid_get_params(sl->chip_id); if (params == NULL) { WLOG("unknown chip id! %#x\n", chip_id); return -1; @@ -1166,12 +1166,12 @@ int stlink_load_device_params(stlink_t *sl) { // TODO make note of variable page size here..... ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %u bytes\n", sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, - (unsigned int)sl->flash_pgsz); + (unsigned int)sl->flash_pgsz); #else ILOG("%s: %d KiB SRAM, %d KiB flash in %d %s pages.\n", - params->description, sl->sram_size / 1024, sl->flash_size / 1024, - (sl->flash_pgsz < 1024)? sl->flash_pgsz : sl->flash_pgsz/1024, - (sl->flash_pgsz < 1024)? "byte" : "KiB"); + params->description, sl->sram_size / 1024, sl->flash_size / 1024, + (sl->flash_pgsz < 1024)? sl->flash_pgsz : sl->flash_pgsz/1024, + (sl->flash_pgsz < 1024)? "byte" : "KiB"); #endif return 0; } @@ -1285,9 +1285,9 @@ int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { ret = sl->backend->read_debug32(sl, addr, data); if (!ret) - DLOG("*** stlink_read_debug32 %x is %#x\n", *data, addr); + DLOG("*** stlink_read_debug32 %x is %#x\n", *data, addr); - return ret; + return ret; } int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { @@ -1955,7 +1955,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr){ uint32_t calculate_F7_sectornum(uint32_t flashaddr){ flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address - if (flashaddr<0x20000) return(flashaddr/0x8000); + if (flashaddr<0x20000) return(flashaddr/0x8000); else if (flashaddr<0x40000) return(4); else return(flashaddr/0x40000) +4; @@ -2347,7 +2347,7 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, stlink_read_mem32(sl, address + (uint32_t) off, aligned_size); if (memcmp(sl->q_buf, data + off, cmp_size)) { - ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); + ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); return -1; } } @@ -2521,7 +2521,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t /* set programming mode */ set_flash_cr_pg(sl); - size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; + size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; for (off = 0; off < len;) { size_t size = len - off > buf_size ? buf_size : len - off; @@ -2642,7 +2642,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { fprintf(stdout, "\r%3u/%3u pages written", (unsigned int)(off/sl->flash_pgsz), - (unsigned int)(len/sl->flash_pgsz)); + (unsigned int)(len/sl->flash_pgsz)); fflush(stdout); } @@ -3236,8 +3236,8 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) */ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { - WLOG("About to write option byte %#10x to target.\n", option_byte); - return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *) &option_byte, 4); + WLOG("About to write option byte %#10x to target.\n", option_byte); + return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *) &option_byte, 4); } /** From f29e1a6a03733cc8839f297d264a5168bd4e0361 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 21 Apr 2020 10:49:00 +0200 Subject: [PATCH 0876/1435] common: warn on unsupported access. should only happen currently after adding a new flash family. --- src/common.c | 41 +++++++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/src/common.c b/src/common.c index e0c5fde2a..c124e6091 100644 --- a/src/common.c +++ b/src/common.c @@ -391,6 +391,7 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; } else { + ELOG("unsupported flash method, abort\n"); return -1; } @@ -425,6 +426,7 @@ static void unlock_flash(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { key_reg = STM32WB_FLASH_KEYR; } else { + ELOG("unsupported flash method, abort\n"); return; } @@ -474,6 +476,7 @@ static void lock_flash(stlink_t *sl) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; } else { + ELOG("unsupported flash method, abort\n"); return; } @@ -521,6 +524,7 @@ static bool is_flash_option_locked(stlink_t *sl) { optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; default: + ELOG("unsupported flash method, abort\n"); return -1; } @@ -564,8 +568,8 @@ static int lock_flash_option(stlink_t *sl) { optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - default: + ELOG("unsupported flash method, abort\n"); return -1; } @@ -612,6 +616,7 @@ static int unlock_flash_option(stlink_t *sl) break; default: + ELOG("unsupported flash method, abort\n"); return -1; } @@ -831,21 +836,23 @@ static void set_flash_cr2_strt(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res, sr_reg; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { sr_reg = FLASH_SR; - else if (sl->flash_type == STLINK_FLASH_TYPE_L0) + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - else if (sl->flash_type == STLINK_FLASH_TYPE_F4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { sr_reg = FLASH_F4_SR; - else if (sl->flash_type == STLINK_FLASH_TYPE_L4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { sr_reg = STM32L4_FLASH_SR; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { sr_reg = STM32WB_FLASH_SR; - else + } else { + ELOG("unsupported flash method, abort"); return -1; + } stlink_read_debug32(sl, sr_reg, &res); @@ -862,19 +869,21 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; unsigned int res; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_L0)) + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_L0)) { sr_busy_shift = FLASH_SR_BSY; - else if (sl->flash_type == STLINK_FLASH_TYPE_F4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { sr_busy_shift = FLASH_F4_SR_BSY; - else if (sl->flash_type == STLINK_FLASH_TYPE_L4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { sr_busy_shift = STM32L4_FLASH_SR_BSY; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { sr_busy_shift = STM32Gx_FLASH_SR_BSY; - else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { sr_busy_shift = STM32WB_FLASH_SR_BSY; - else + } else { + ELOG("unsupported flash method, abort"); return -1; + } res = read_flash_sr(sl) & (1 << sr_busy_shift); From 8e69625531ec8f6def7a50a60a21f2aeffcd272a Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Tue, 21 Apr 2020 10:52:52 +0200 Subject: [PATCH 0877/1435] write option byte: final refactor now that all flash family methods are aligned, refactor main method to avoid duplicated lock/unlock, add info traces, and map methods based on familly instead of a small subset of selected devices. nb1: f0/f1 support is still missing nb2: option read/write is still conditioned by presence of option_base and option_size in chipid.c, but adding more chips should only be a matter of adding these two informations. --- src/common.c | 152 +++++++++++++++++++-------------------------------- 1 file changed, 55 insertions(+), 97 deletions(-) diff --git a/src/common.c b/src/common.c index c124e6091..f6cf08e2f 100644 --- a/src/common.c +++ b/src/common.c @@ -2971,27 +2971,14 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t val; - - (void) addr; + int ret = 0; (void) len; - wait_flash_busy(sl); - - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } - - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; - } - /* Write options bytes */ uint32_t data; write_uint32((unsigned char*) &data, *(uint32_t*) (base)); WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - //stlink_write_debug32(sl, addr, data); + stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); /* Set Options Start bit */ @@ -2999,23 +2986,16 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_ val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - /* Wait for 'busy' bit in FLASH_SR to clear. */ - do { - stlink_read_debug32(sl, STM32Gx_FLASH_SR, &val); - } while ((val & (1 << STM32Gx_FLASH_SR_BSY)) != 0); + wait_flash_busy(sl); - check_flash_error(sl); + ret = check_flash_error(sl); - /* apply options bytes immediate */ + /* Reload options */ stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); - - return 0; + return ret; } /** @@ -3030,18 +3010,7 @@ static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t* base, stm32_addr_ uint32_t flash_base = get_stm32l0_flash_base(sl); uint32_t val; uint32_t data; - - wait_flash_busy(sl); - - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } - - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; - } + int ret = 0; /* Clear errors */ stlink_write_debug32(sl, flash_base + FLASH_SR_OFF, STM32L0_FLASH_REGS_ADDR); @@ -3055,7 +3024,7 @@ static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t* base, stm32_addr_ wait_flash_busy(sl); - if (check_flash_error(sl)) + if ((ret = check_flash_error(sl))) break; len-=4; @@ -3068,10 +3037,7 @@ static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t* base, stm32_addr_ val |= (1 << STM32L0_FLASH_OBL_LAUNCH); stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); - lock_flash_option(sl); - lock_flash(sl); - - return 0; + return ret; } /** @@ -3084,22 +3050,11 @@ static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t* base, stm32_addr_ static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t val; + int ret = 0; (void) addr; (void) len; - wait_flash_busy(sl); - - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } - - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; - } - /* Write options bytes */ uint32_t data; write_uint32((unsigned char*) &data, *(uint32_t*) (base)); @@ -3114,18 +3069,14 @@ static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t* base, stm32_addr_ /* Wait for 'busy' bit in FLASH_SR to clear. */ wait_flash_busy(sl); - check_flash_error(sl); + ret = check_flash_error(sl); /* apply options bytes immediate */ stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); - - return 0; + return ret; } @@ -3137,22 +3088,11 @@ static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t* base, stm32_addr_ */ static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t option_byte; + int ret = 0; (void) addr; (void) len; - wait_flash_busy(sl); - - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } - - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; - } - write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); /* write option byte, ensuring we dont lock opt, and set strt bit */ @@ -3160,14 +3100,11 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_ wait_flash_busy(sl); - check_flash_error(sl); + ret = check_flash_error(sl); /* option bytes are reloaded at reset only, no obl. */ - lock_flash_option(sl); - lock_flash(sl); - - return 0; + return ret; } /** @@ -3258,6 +3195,8 @@ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) */ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { + int ret = -1; + if (sl->option_base == 0) { ELOG("Option bytes writing is currently not supported for connected chip\n"); return -1; @@ -3273,28 +3212,47 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui return -1; } - /* filter out on chip_id, until complete flash family are handled */ - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: - case STLINK_CHIPID_STM32_F446: - return stlink_write_option_bytes_f4(sl, base, addr, len); - case STLINK_CHIPID_STM32_L0_CAT2: - case STLINK_CHIPID_STM32_L0_CAT5: - case STLINK_CHIPID_STM32_L152_RE: - case STLINK_CHIPID_STM32_L1_HIGH: - return stlink_write_option_bytes_l0(sl, base, addr, len); - case STLINK_CHIPID_STM32_L496X: - case STLINK_CHIPID_STM32_L4: - return stlink_write_option_bytes_l4(sl, base, addr, len); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: - return stlink_write_option_bytes_gx(sl, base, addr, len); + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F4: + ret = stlink_write_option_bytes_f4(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_L0: + ret = stlink_write_option_bytes_l0(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_L4: + ret = stlink_write_option_bytes_l4(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + ret = stlink_write_option_bytes_gx(sl, base, addr, len); + break; default: ELOG("Option bytes writing is currently not implemented for connected chip\n"); - return -1; + break; } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; } /** From e9facddc3cd2243f663a69d429432a1695ab1051 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Wed, 22 Apr 2020 14:54:42 +0800 Subject: [PATCH 0878/1435] Add more note about flash page size --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 50f87f42c..a833ab0ea 100644 --- a/src/common.c +++ b/src/common.c @@ -2223,7 +2223,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t WLOG("unaligned len 0x%x -- padding with zero\n", len); len += 1; } else if (addr & (sl->flash_pgsz - 1)) { - ELOG("addr not a multiple of current pagesize (%zd bytes), not supported\n", sl->flash_pgsz); + ELOG("addr not a multiple of current pagesize (%zd bytes), not supported, check page start address and compare with flash module organisation in related ST reference manual of your device.\n", sl->flash_pgsz); return -1; } From ad0e52540e4003f05b7f6fa488e91c1d52c78df2 Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Wed, 22 Apr 2020 10:57:45 +0200 Subject: [PATCH 0879/1435] doc: update doc to mention STLINK_DEVICE and --probe parameters if applicable in all man files --- doc/man/st-flash.md | 3 +++ doc/man/st-info.md | 3 +++ doc/man/st-util.md | 5 ++--- doc/tutorial.md | 4 ++-- 4 files changed, 10 insertions(+), 5 deletions(-) diff --git a/doc/man/st-flash.md b/doc/man/st-flash.md index b787e8dd7..d5565e923 100644 --- a/doc/man/st-flash.md +++ b/doc/man/st-flash.md @@ -20,6 +20,9 @@ You can use this instead of st-util(1) if you prefer, but remember to use the Use hexadecimal format for the *ADDR* and *SIZE*. +The STLink device to use can be specified using the --serial parameter, or via +the environment variable STLINK_DEVICE on the format :. + # COMMANDS write *FILE* *ADDR* diff --git a/doc/man/st-info.md b/doc/man/st-info.md index ca2579785..94a430000 100644 --- a/doc/man/st-info.md +++ b/doc/man/st-info.md @@ -11,9 +11,12 @@ st-info - Provides information about connected STLink and STM32 devices # DESCRIPTION + Provides information about connected STLink programmers and STM32 devices: Serial code, OpenOCD hla-serial, flash, page size, sram, chipid, description. +The STLink device to probe can be specified via the environment variable +STLINK_DEVICE on the format :. # OPTIONS diff --git a/doc/man/st-util.md b/doc/man/st-util.md index e62261213..3582bc06d 100644 --- a/doc/man/st-util.md +++ b/doc/man/st-util.md @@ -18,9 +18,8 @@ If a port number is not specified using the **--listen_port** option, the default **4242** port will be used. Stlink version 2 is used by default unless the option **--stlinkv1** is given. - -The STLinkV2 device to use can be specified in the environment -variable STLINK_DEVICE on the format :. +The STLink device to use can be specified using the --serial parameter, or via +the environment variable STLINK_DEVICE on the format :. # OPTIONS diff --git a/doc/tutorial.md b/doc/tutorial.md index 75e03f1bc..2ff0188ce 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -285,8 +285,8 @@ There are a few options: Do not reset board on connection. ``` -The STLINKv2 device to use can be specified in the environment -variable `STLINK_DEVICE` in the format `:`. +The STLink device to use can be specified using the --serial parameter, or via +the environment variable STLINK_DEVICE on the format :. Then, in your project directory, someting like this... (remember, you need to run an _ARM_ gdb, not an x86 gdb) From 5e0fd8b61c81f47f40592f9844b0f4507069137d Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Wed, 22 Apr 2020 11:00:27 +0200 Subject: [PATCH 0880/1435] doc: remove stlink version parameter selectors doc and examples --- doc/man/st-util.md | 7 ------- doc/tutorial.md | 25 ++++++------------------- 2 files changed, 6 insertions(+), 26 deletions(-) diff --git a/doc/man/st-util.md b/doc/man/st-util.md index 3582bc06d..9a54fb309 100644 --- a/doc/man/st-util.md +++ b/doc/man/st-util.md @@ -17,7 +17,6 @@ Run the main binary of the local package (src/main.rs). If a port number is not specified using the **--listen_port** option, the default **4242** port will be used. -Stlink version 2 is used by default unless the option **--stlinkv1** is given. The STLink device to use can be specified using the --serial parameter, or via the environment variable STLINK_DEVICE on the format :. @@ -35,12 +34,6 @@ the environment variable STLINK_DEVICE on the format :. -v, \--verbose : Specify generally verbose logging --s *X*, \--stlink_version=*X* -: Choose what version of stlink to use, (defaults to 2) - --1, \--stlinkv1 -: Force stlink version 1 - -p *4242*, \--listen_port=1234 : Set the gdb server listen port. (default port: 4242) diff --git a/doc/tutorial.md b/doc/tutorial.md index 2ff0188ce..929aa3250 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -168,18 +168,14 @@ will help you verify that: - Your arm-none-eabi-gdb is functional - Your board is functional -A GDB server must be started to interact with the STM32. Depending on -the discovery kit you are using, you must run one of the 2 commands: +A GDB server must be started to interact with the STM32 by running +st-util tool : ``` -# STM32VL discovery kit (onboard ST-link) -$> ./st-util --stlinkv1 - -# STM32L or STM32F4 discovery kit (onboard ST-link/V2) -$> ./st-util +$> st-util # Full help for other options (listen port, version) -$> ./st-util --help +$> st-util --help ``` Then, GDB can be used to interact with the kit: @@ -226,16 +222,10 @@ memory, or read arbitary addresses of memory out to a binary file, use the st-flash tool, as shown below: ``` -# stlinkv1 command to read 4096 from flash into out.bin -$> ./st-flash read out.bin 0x8000000 4096 - -# stlinkv2 command +# stlink command to read 4096 from flash into out.bin $> ./st-flash read out.bin 0x8000000 4096 -# stlinkv1 command to write the file in.bin into flash -$> ./st-flash write in.bin 0x8000000 - -# stlinkv2 command +# stlinkv command to write the file in.bin into flash $> ./st-flash write in.bin 0x8000000 ``` @@ -273,9 +263,6 @@ There are a few options: -h, --help Print this help -vXX, --verbose=XX Specify a specific verbosity level (0..99) -v, --verbose Specify generally verbose logging - -s X, --stlink_version=X - Choose what version of stlink to use, (defaults to 2) - -1, --stlinkv1 Force stlink version 1 -p 4242, --listen_port=1234 Set the gdb server listen port. (default port: 4242) -m, --multi From 5db2dc4c0410ace65308cddcc03d1c0cfa4855cf Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 23 Apr 2020 11:03:15 +0200 Subject: [PATCH 0881/1435] cmake replaces 7zip for package extraction The exctraction of the libusb library archive on windows no longer requires an external unarchiver. --- cmake/modules/Find7zip.cmake | 7 ------- cmake/modules/Findlibusb.cmake | 17 +++++------------ 2 files changed, 5 insertions(+), 19 deletions(-) delete mode 100644 cmake/modules/Find7zip.cmake diff --git a/cmake/modules/Find7zip.cmake b/cmake/modules/Find7zip.cmake deleted file mode 100644 index 83eb912d4..000000000 --- a/cmake/modules/Find7zip.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# Find7zip.cmake -# Detect 7zip file archiver on Windows systems to extract (zip-)archives - -find_program( - ZIP_EXECUTABLE NAMES 7z.exe p7zip - HINTS "C:\\Program Files\\7-Zip\\" "C:\\Program Files (x86)\\7-Zip\\" -) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index 13f70d7b7..898820033 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -73,7 +73,6 @@ elseif (WIN32) # Windows if (NOT LIBUSB_FOUND OR EXISTS "/etc/debian_version") # Preparations for installing libusb library - find_package(7zip REQUIRED) set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) @@ -92,17 +91,11 @@ elseif (WIN32) # Windows file(MAKE_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) - # Extract libusb package - if (${ZIP_EXECUTABLE} MATCHES "p7zip") - execute_process( - COMMAND ${ZIP_EXECUTABLE} -d ${LIBUSB_WIN_ARCHIVE_PATH} - WORKING_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER} - ) - else () - execute_process( - COMMAND ${ZIP_EXECUTABLE} x -y ${LIBUSB_WIN_ARCHIVE_PATH} -o${LIBUSB_WIN_OUTPUT_FOLDER} - ) # <-- Note the absence of a space character following the -o option! - endif () + # Extract libusb package with cmake + execute_process( + COMMAND ${CMAKE_COMMAND} -E tar xv ${LIBUSB_WIN_ARCHIVE_PATH} + WORKING_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER} + ) # Find path to libusb library FIND_PATH( From 39f22639ef461d5cd082e07df67d16de3082d9e3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 23 Apr 2020 11:04:38 +0200 Subject: [PATCH 0882/1435] Updated license file for deb package --- LICENSE.md | 2 +- cmake/packaging/debian/copyright | 321 +++++++++++++++---------------- 2 files changed, 153 insertions(+), 170 deletions(-) diff --git a/LICENSE.md b/LICENSE.md index 9c3b59f0f..4cb795b18 100644 --- a/LICENSE.md +++ b/LICENSE.md @@ -1,6 +1,6 @@ BSD 3-Clause License -Copyright (c) 2020, The stlink project (github.com/stlink-org/stlink) & "Capt'ns Missing Link" authors. +Copyright (c) 2020, stlink-org All rights reserved. Redistribution and use in source and binary forms, with or without diff --git a/cmake/packaging/debian/copyright b/cmake/packaging/debian/copyright index 7a6d585c5..4a7b110ae 100644 --- a/cmake/packaging/debian/copyright +++ b/cmake/packaging/debian/copyright @@ -2,173 +2,156 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink Upstream-Contact: Luca Bocassi Source: https://github.com/stlink-org/stlink - -Files: * -Copyright: 2011-2018 agpanarin - 2011-2018 Alexey Cherevatenko - 2011-2018 Anatoli - 2011-2018 Andrea Mucignat - 2011-2018 Andrew 'Necromant' Andrianov - 2011-2018 Andrey Yurovsky - 2011-2018 Andy Isaacson - 2011-2018 Áron RADICS - 2011-2018 A Sheaff - 2011-2018 Björn Hauffe - 2011-2018 bob - 2011-2018 Breton M. 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Koszek - 2011-2018 Woodrow Douglass - 2011-2018 The "Capt'ns Missing Link" Authors. +Disclaimer: +Comment: License: BSD-3-clause - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions - are met: - . - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - * Neither the name of Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - . - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. 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Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + . + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +Files: * +Copyright: 2011-2020 stlink-org + Martin Capitanio [capnm] + Fabien Le Mentec [texane] + Jerry Jacobs [xor-gate] + [Nightwalker-87] + . + Alexey Cherevatenko + Alexey Panarin + Anatoli Klassen [dev26th] + Andrea Mucignat + Andrew Andrianov [necromant] + Andrey Yurovsky + Andy Isaacson + Áron Radics + A. Sheaff + Björn Hauffe + Ihor Bobalo + Breton M. Saunders + Bruno Dal Bo + Burns Fisher + Chris Dew + Chris Hiszpanski + Chris Li + Chris Samuelson + Christian Deussen [nullsub] + Christophe Levantis + Craig Lilley + Dan Dev + Dan Hepler + Daniel Campoverde [alx741] + Daniel O'Connor + Dave Flogeras + Dave Murphy [WinterMute] + Dave Vandervies [dj3vande] + Denis Fokin + Denis Osterland + Dmitry Bravikov [bravikov] + Efe Can İçöz + Ethan Zonca + Fabien Chouteau + Florian Hars + Friedrich Beckmann + Geoffrey Brown + George Talusan [gtalusan] + Georg von Zengen + Giuseppe Barba + Greg Alexander [galexander1] + Greg Meiste [meisteg] + Guillaume Revaillot [grevaillot] + Hakkavélin + Halt Hammerzeit + htk + Ian Griffiths + Jack Peel + Jakub Tyszkowski + Jan Sarenik + Jean-Luc Béchennec + Jean-Marie Lemetayer + Jeff Kent + Jeffrey Nelson + Jens Hoffmann + Jerome Lambourg + Jim Paris + Jiří Netolický + Jerry Nosky [jnosky] + Johannes Taelman + Jonas Danielsson + Jonas Norling + Josh Bialkowski + Karl Palsson [karlp] + Kevlar Harness + Kyle Manna + Lari Lehtomäki + Martin Nowak + Matteo Collina + Max Chen + Maxime Coquelin [mcoquelin-stm32] + Maxime Vincent + Michael Pratt [prattmic] + Michael Sparmann + Mike Szczys + Magnus Lundin [mlu] + mux + Ned Konz + Nic McDonald + Nicolas Schodet + Oleksiy Slyshyk [slyshykO] + Olivier Croquette + Olivier Gay + Onno Kortmann + orangeudav + Pavel Kirienko + Pekka Nikander + Pete Nelson + Peter Zotov + Petteri Aimonen + Piotr Haber + Rene Hopf [rene-dev] + Robin Kreis + Roger Wolff [rewolff] + Rob Spanton + Rytis Karpuska + Sean Simmons + Sergey Alirzaev + Simon Wright + Stany Marcel + Stefan Misik + Sven Wegener + Joel Bodenmann [Tectu] + Tuomo Kaikkonen + Theodore A. Roth + Thomas Gärtner + Tobias Badertscher + Tom de Boer + Tristan Gingold + Uli Köhler + Uwe Bonnes [UweBonnes] + Vadim Kaushan + Vasiliy Glazov [Vascom] + Vegard Storheil Eriksen + Viacheslav Dobromyslov + Victor Mayoral Vilches + William Ransohoff [WRansohoff] + Wojciech A. Koszek + Woodrow Douglass + Xim [chenguokai] + ... and others From 3e3f782e5e4e98570c41e9f139e8d07c743e311a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 23 Apr 2020 22:52:00 +0200 Subject: [PATCH 0883/1435] Updated pkgconfig (Closes #944) --- CMakeLists.txt | 2 +- cmake/pkgconfig/CMakeLists.txt | 15 +++++++++++++++ .../pkgconfig/pkgconfig.pc.cmake | 9 +++++---- debian/pkg-config/CMakeLists.txt | 15 --------------- 4 files changed, 21 insertions(+), 20 deletions(-) create mode 100644 cmake/pkgconfig/CMakeLists.txt rename debian/pkg-config/pkg-config.pc.cmake => cmake/pkgconfig/pkgconfig.pc.cmake (99%) delete mode 100644 debian/pkg-config/CMakeLists.txt diff --git a/CMakeLists.txt b/CMakeLists.txt index fd79ac10e..3ec381239 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -68,6 +68,7 @@ endif () find_package(libusb REQUIRED) if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) + add_subdirectory(cmake/pkgconfig) find_package(PkgConfig) pkg_check_modules(GTK3 gtk+-3.0) endif () @@ -269,7 +270,6 @@ add_subdirectory(tests) add_subdirectory(cmake/packaging) include(cmake/packaging/cpack_config.cmake) - ### # Uninstall target ### diff --git a/cmake/pkgconfig/CMakeLists.txt b/cmake/pkgconfig/CMakeLists.txt new file mode 100644 index 000000000..53870fee4 --- /dev/null +++ b/cmake/pkgconfig/CMakeLists.txt @@ -0,0 +1,15 @@ +set(PKG_CONFIG_LIBDIR "\${prefix}/lib/\${deb_host_multiarch}") +set(PKG_CONFIG_INCLUDEDIR "\${prefix}/include/\${deb_host_multiarch}/${PROJECT_NAME}") +set(PKG_CONFIG_LIBS "-L\${libdir} -l:libstlink.so.${PROJECT_VERSION_MAJOR}") +set(PKG_CONFIG_CFLAGS "-I\${includedir}") +set(PKG_CONFIG_REQUIRES "libusb-1.0") + +configure_file( + "${CMAKE_CURRENT_SOURCE_DIR}/pkgconfig.pc.cmake" + "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" + ) + +install( + FILES "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" + DESTINATION ${STLINK_LIBRARY_PATH}/pkgconfig + ) diff --git a/debian/pkg-config/pkg-config.pc.cmake b/cmake/pkgconfig/pkgconfig.pc.cmake similarity index 99% rename from debian/pkg-config/pkg-config.pc.cmake rename to cmake/pkgconfig/pkgconfig.pc.cmake index c00eb070e..4f881daec 100644 --- a/debian/pkg-config/pkg-config.pc.cmake +++ b/cmake/pkgconfig/pkgconfig.pc.cmake @@ -1,10 +1,11 @@ +prefix=${CMAKE_INSTALL_PREFIX} deb_host_multiarch=${CMAKE_LIBRARY_PATH} +libdir=${PKG_CONFIG_LIBDIR} +includedir=${PKG_CONFIG_INCLUDEDIR} + Name: ${PROJECT_NAME} Description: ${PROJECT_DESCRIPTION} Version: ${PROJECT_VERSION} -Requires: ${PKG_CONFIG_REQUIRES} -prefix=${CMAKE_INSTALL_PREFIX} -includedir=${PKG_CONFIG_INCLUDEDIR} -libdir=${PKG_CONFIG_LIBDIR} Libs: ${PKG_CONFIG_LIBS} Cflags: ${PKG_CONFIG_CFLAGS} +Requires: ${PKG_CONFIG_REQUIRES} diff --git a/debian/pkg-config/CMakeLists.txt b/debian/pkg-config/CMakeLists.txt deleted file mode 100644 index fa3a326a8..000000000 --- a/debian/pkg-config/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -#set(PKG_CONFIG_LIBDIR "\${prefix}/lib/\${deb_host_multiarch}") -#set(PKG_CONFIG_INCLUDEDIR "\${prefix}/include/\${deb_host_multiarch}/${PROJECT_NAME}") -#set(PKG_CONFIG_LIBS "-L\${libdir} -l:libstlink.so.${PROJECT_VERSION_MAJOR}") -#set(PKG_CONFIG_CFLAGS "-I\${includedir}") -#set(PKG_CONFIG_REQUIRES "libusb-1.0") - -#configure_file( -# "${CMAKE_CURRENT_SOURCE_DIR}/pkg-config.pc.cmake" -# "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" -# ) - -#install( -# FILES "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" -# DESTINATION ${STLINK_LIBRARY_PATH}/debian/ -# ) From 22f44856abe4f272f33c48a31c7167e3b45dd0ab Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 24 Apr 2020 01:08:02 +0200 Subject: [PATCH 0884/1435] Updated compiling manual - Removed requirement for 7zip on Windows - Added note on GNUInstallDir presets (#557) --- doc/compiling.md | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index 15d8b4fc2..38e680f03 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -5,25 +5,23 @@ On Windows users should ensure that the following software is installed: -* `7zip` -* `git` +* `git` (_optional, but recommended_) * `cmake` (3.17.0 or later) * `MinGW-w64` (7.0.0 or later) with GCC toolchain 8.1.0 ### Installation -1. Install `7zip` from -2. Install `git` from -3. Install `cmake` from
    +1. Install `git` from +2. Install `cmake` from
    Ensure that you add cmake to the $PATH system variable when following the instructions by the setup assistant. -4. Install +3. Install - _EITHER_: **MinGW-w64** from (mingw-w64-install.exe)
    - _OR_: **Visual Studio 2017 CE** (other versions will likely work as well, but are untested; the Community edition is free for open source development) -5. Create a new destination folder at a place of your choice -6. Open the command-line (cmd.exe) and execute `cd C:\$Path-to-your-destination-folder$\` -7. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git`from the command-line (cmd.exe)
    +4. Create a new destination folder at a place of your choice +5. Open the command-line (cmd.exe) and execute `cd C:\$Path-to-your-destination-folder$\` +6. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git`from the command-line (cmd.exe)
    or download the stlink zip-sourcefolder from the Release page on GitHub @@ -201,10 +199,22 @@ To do this with only one simple command, type: The debug target is only necessary in order to modify the sources and to run under a debugger. -## Build using a different directory for shared libs +## Build options +### Build using a different directory for shared libs To put the compiled shared libs into a different directory during installation, you can use the cmake option `cmake -DLIB_INSTALL_DIR:PATH="/usr/lib64" ..`. +### Standard installation directories + +The cmake build system of this toolset includes `GNUInstallDirs` to define GNU standard installation directories. +This module provides install directory variables as defined by the GNU Coding Standards. + +Below are the preset default cmake options, which apply if none of these options are redefined: + +* `-DCMAKE_INSTALL_SYSCONFDIR=/etc` +* `-DCMAKE_INSTALL_PREFIX=/usr/local` + + Author: nightwalker-87 From 44e2a4fdbd3ad4398ab483c27275ea86540c31b6 Mon Sep 17 00:00:00 2001 From: xp Date: Fri, 24 Apr 2020 13:45:00 +0800 Subject: [PATCH 0885/1435] rewrite as clean room doc --- flashloaders/stm32f0.s | 85 +++++++++++++++++++++++++--------------- flashloaders/stm32f4.s | 53 +++++++++++++------------ flashloaders/stm32f4lv.s | 54 +++++++++++++------------ flashloaders/stm32f7.s | 65 ++++++++++++++++-------------- flashloaders/stm32f7lv.s | 66 ++++++++++++++++--------------- flashloaders/stm32l0x.s | 74 +++++++--------------------------- flashloaders/stm32l4.s | 60 ++++++++++++++-------------- flashloaders/stm32lx.s | 70 +++++++-------------------------- 8 files changed, 238 insertions(+), 289 deletions(-) diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s index fe12f90f3..885353912 100644 --- a/flashloaders/stm32f0.s +++ b/flashloaders/stm32f0.s @@ -1,32 +1,53 @@ -/* Adopted from STM AN4065 stm32f0xx_flash.c:FLASH_ProgramWord */ - -write: - ldr r4, STM32_FLASH_BASE - mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */ - mov r6, #4 /* PGERR */ -write_half_word: - ldr r3, [r4, #16] /* FLASH->CR */ - orr r3, r5 - str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */ - ldrh r3, [r0] /* r3 = *sram */ - strh r3, [r1] /* *flash = r3 */ -busy: - ldr r3, [r4, #12] /* FLASH->SR */ - tst r3, r5 /* FLASH_SR_BUSY */ - beq busy - - tst r3, r6 /* PGERR */ - bne exit - - add r0, r0, #2 /* sram += 2 */ - add r1, r1, #2 /* flash += 2 */ - sub r2, r2, #0x01 /* count-- */ - cmp r2, #0 - bne write_half_word -exit: - ldr r3, [r4, #16] /* FLASH->CR */ - bic r3, r5 - str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */ - bkpt #0x00 - -STM32_FLASH_BASE: .word 0x40022000 + .syntax unified + .text + + .global mycopy +mycopy: + ldr r12, flash_base + ldr r11, flash_off_cr + add r11, r11, r12 + ldr r10, flash_off_sr + add r10, r10, r12 + +myloop: + # FLASH_CR ^= 1 + ldr r3, [r11] + orr r3, r3, #0x1 + str r3, [r11] + + # copy 2 bytes + ldrh r3, [r0] + strh r3, [r1] + + add r0, r0, #2 + add r1, r1, #2 + + # wait if FLASH_SR == 1 +mywait: + ldr r3, [r10] + tst r3, #0x1 + beq mywait + + # exit if FLASH_SR == 4 + tst r3, #0x4 + beq myexit + + # loop if r2 != 0 + sub r2, r2, #1 + cmp r2, #0 + bne myloop + +myexit: + # FLASH_CR &= ~1 + ldr r3, [r11] + bic r3, r3, #0x1 + str r3, [r11] + + bkpt + +flash_base: + .word 0x40022000 +flash_off_cr: + .word 0x10 +flash_off_sr: + .word 0x0c diff --git a/flashloaders/stm32f4.s b/flashloaders/stm32f4.s index 21f5a8f7f..a47054dae 100644 --- a/flashloaders/stm32f4.s +++ b/flashloaders/stm32f4.s @@ -1,32 +1,35 @@ -.global start -.syntax unified + .syntax unified + .text -@ r0 = source -@ r1 = target -@ r2 = wordcount -@ r3 = flash_base -@ r4 = temp + .global mycopy +mycopy: + ldr r12, flash_base + ldr r10, flash_off_sr + add r10, r10, r12 -start: - ldr r3, flash_base -next: - cbz r2, done - ldr r4, [r0] - str r4, [r1] +myloop: + # copy 4 bytes + ldr r3, [r0] + str r3, [r1] -wait: - ldrh r4, [r3, #0x0e] - tst.w r4, #1 - bne wait + add r0, r0, #4 + add r1, r1, #4 - add r0, #4 - add r1, #4 - sub r2, #1 - b next -done: - bkpt + # wait if FLASH_SR == 1 +mywait: + ldrh r3, [r10] + tst r3, #0x1 + beq mywait + + # loop if r2 != 0 + sub r2, r2, #1 + cmp r2, #0 + bne myloop -.align 2 +myexit: + bkpt flash_base: - .word 0x40023c00 + .word 0x40023c00 +flash_off_sr: + .word 0x0e diff --git a/flashloaders/stm32f4lv.s b/flashloaders/stm32f4lv.s index f60ee8797..cfbbe8520 100644 --- a/flashloaders/stm32f4lv.s +++ b/flashloaders/stm32f4lv.s @@ -1,33 +1,35 @@ -.global start -.syntax unified + .syntax unified + .text -@ r0 = source -@ r1 = target -@ r2 = wordcount -@ r3 = flash_base -@ r4 = temp + .global mycopy +mycopy: + ldr r12, flash_base + ldr r10, flash_off_sr + add r10, r10, r12 -start: - lsls r2, r2, #2 - ldr r3, flash_base -next: - cbz r2, done - ldrb r4, [r0] - strb r4, [r1] +myloop: + # copy 1 bytes + ldrb r3, [r0] + strb r3, [r1] -wait: - ldrh r4, [r3, #0x0e] - tst.w r4, #1 - bne wait + add r0, r0, #1 + add r1, r1, #1 - add r0, #1 - add r1, #1 - sub r2, #1 - b next -done: - bkpt + # wait if FLASH_SR == 1 +mywait: + ldrh r3, [r10] + tst r3, #0x1 + beq mywait + + # loop if r2 != 0 + sub r2, r2, #1 + cmp r2, #0 + bne myloop -.align 2 +myexit: + bkpt flash_base: - .word 0x40023c00 + .word 0x40023c00 +flash_off_sr: + .word 0x0e diff --git a/flashloaders/stm32f7.s b/flashloaders/stm32f7.s index 0334c80a0..f873f0ebd 100644 --- a/flashloaders/stm32f7.s +++ b/flashloaders/stm32f7.s @@ -1,33 +1,38 @@ -.global start -.syntax unified - -@ r0 = source -@ r1 = target -@ r2 = wordcount -@ r3 = flash_base -@ r4 = temp - -start: - ldr r3, flash_base -next: - cbz r2, done - ldr r4, [r0] - str r4, [r1] - dsb sy - -wait: - ldrh r4, [r3, #0x0e] - tst.w r4, #1 - bne wait - - add r0, #4 - add r1, #4 - sub r2, #1 - b next -done: - bkpt + .syntax unified + .text + + .global mycopy +mycopy: + ldr r12, flash_base + ldr r10, flash_off_sr + add r10, r10, r12 + +myloop: + # copy 4 bytes + ldr r3, [r0] + str r3, [r1] + + add r0, r0, #4 + add r1, r1, #4 -.align 2 + # memory barrier + dsb sy + + # wait if FLASH_SR == 1 +mywait: + ldrh r3, [r10] + tst r3, #0x1 + beq mywait + + # loop if r2 != 0 + sub r2, r2, #1 + cmp r2, #0 + bne myloop + +myexit: + bkpt flash_base: - .word 0x40023c00 + .word 0x40023c00 +flash_off_sr: + .word 0x0e diff --git a/flashloaders/stm32f7lv.s b/flashloaders/stm32f7lv.s index 650922719..fe5be0529 100644 --- a/flashloaders/stm32f7lv.s +++ b/flashloaders/stm32f7lv.s @@ -1,34 +1,38 @@ -.global start -.syntax unified - -@ r0 = source -@ r1 = target -@ r2 = wordcount -@ r3 = flash_base -@ r4 = temp - -start: - lsls r2, r2, #2 - ldr r3, flash_base -next: - cbz r2, done - ldrb r4, [r0] - strb r4, [r1] - dsb sy - -wait: - ldrh r4, [r3, #0x0e] - tst.w r4, #1 - bne wait - - add r0, #1 - add r1, #1 - sub r2, #1 - b next -done: - bkpt + .syntax unified + .text + + .global mycopy +mycopy: + ldr r12, flash_base + ldr r10, flash_off_sr + add r10, r10, r12 + +myloop: + # copy 1 byte + ldrb r3, [r0] + strb r3, [r1] + + add r0, r0, #1 + add r1, r1, #1 -.align 2 + # memory barrier + dsb sy + + # wait if FLASH_SR == 1 +mywait: + ldrh r3, [r10] + tst r3, #0x1 + beq mywait + + # loop if r2 != 0 + sub r2, r2, #1 + cmp r2, #0 + bne myloop + +myexit: + bkpt flash_base: - .word 0x40023c00 + .word 0x40023c00 +flash_off_sr: + .word 0x0e diff --git a/flashloaders/stm32l0x.s b/flashloaders/stm32l0x.s index fcbd06e39..1ce7dd144 100644 --- a/flashloaders/stm32l0x.s +++ b/flashloaders/stm32l0x.s @@ -1,64 +1,20 @@ -/*************************************************************************** - * Copyright (C) 2010 by Spencer Oliver * - * spen@spen-soft.co.uk * - * * - * Copyright (C) 2011 Øyvind Harboe * - * oyvind.harboe@zylin.com * - * * - * Copyright (C) 2011 Clement Burin des Roziers * - * clement.burin-des-roziers@hikob.com * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ - - -// Build : arm-eabi-gcc -c stm32lx.S - .text .syntax unified - .cpu cortex-m0plus - .thumb - .thumb_func - .global write - -/* - r0 - source address - r1 - destination address - r2 - count -*/ + .text - // Go to compare - b test_done + .global mycopy +mycopy: +myloop: + # copy 4 bytes + ldr r3, [r0] + str r3, [r1] -write_word: - // Load one word from address in r0, increment by 4 - ldr r4, [r0] - // Store the word to address in r1, increment by 4 - str r4, [r1] - // Decrement r2 - subs r2, #1 - adds r1, #4 - // does not matter, only first addr is important - // next 15 bytes are in sequnce RM0367 page 66 - adds r0, #4 + add r0, r0, #4 + add r1, r1, #4 -test_done: - // Test r2 - cmp r2, #0 - // Loop if not zero - bcc.n write_word + # loop if r2 != 0 + sub r2, r2, #1 + cmp r2, #0 + bne myloop - // Set breakpoint to exit - bkpt #0x00 +myexit: + bkpt diff --git a/flashloaders/stm32l4.s b/flashloaders/stm32l4.s index 6aa2be050..0a68b687a 100644 --- a/flashloaders/stm32l4.s +++ b/flashloaders/stm32l4.s @@ -1,39 +1,37 @@ -.global start -.syntax unified + .syntax unified + .text -@ Adapted from stm32f4.s -@ STM32L4's flash controller expects double-word writes, has the flash -@ controller mapped in a different location with the registers we care about -@ moved down from the base address, and has BSY moved to bit 16 of SR. -@ r0 = source -@ r1 = target -@ r2 = wordcount -@ r3 = flash_base -@ r4 = temp -@ r5 = temp + .global mycopy +mycopy: + ldr r12, flash_base + ldr r10, flash_off_bsy + add r10, r10, r12 -start: - ldr r3, flash_base -next: - cbz r2, done - ldr r4, [r0] /* copy doubleword from source to target */ - ldr r5, [r0, #4] - str r4, [r1] - str r5, [r1, #4] +myloop: + # copy 8 bytes + ldr r3, [r0] + ldr r3, [r0， #4] + str r3, [r1] + str r3, [r1， #4] -wait: - ldrh r4, [r3, #0x12] /* high half of status register */ - tst r4, #1 /* BSY = bit 16 */ - bne wait + add r0, r0, #8 + add r1, r1, #8 - add r0, #8 - add r1, #8 - sub r2, #1 - b next -done: - bkpt + # wait if FLASH_BSY[0b] == 1 +mywait: + ldrh r3, [r10] + tst r3, #0x1 + beq mywait + + # loop if r2 != 0 + sub r2, r2, #1 + cmp r2, #0 + bne myloop -.align 2 +myexit: + bkpt flash_base: .word 0x40022000 +flash_off_bsy: + .word 0x12 diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s index 10e5644bf..1ce7dd144 100644 --- a/flashloaders/stm32lx.s +++ b/flashloaders/stm32lx.s @@ -1,60 +1,20 @@ -/*************************************************************************** - * Copyright (C) 2010 by Spencer Oliver * - * spen@spen-soft.co.uk * - * * - * Copyright (C) 2011 Øyvind Harboe * - * oyvind.harboe@zylin.com * - * * - * Copyright (C) 2011 Clement Burin des Roziers * - * clement.burin-des-roziers@hikob.com * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ - - -// Build : arm-eabi-gcc -c stm32lx.s - .text .syntax unified - .cpu cortex-m3 - .thumb - .thumb_func - .global write - -/* - r0 - source address - r1 - destination address - r2 - output, remaining word count -*/ + .text - // Go to compare - b test_done + .global mycopy +mycopy: +myloop: + # copy 4 bytes + ldr r3, [r0] + str r3, [r1] -write_word: - // Load one word from address in r0, increment by 4 - ldr.w ip, [r0], #4 - // Store the word to address in r1, increment by 4 - str.w ip, [r1], #4 - // Decrement r2 - subs r2, #1 + add r0, r0, #4 + add r1, r1, #4 -test_done: - // Test r2 - cmp r2, #0 - // Loop if not zero - bhi write_word + # loop if r2 != 0 + sub r2, r2, #1 + cmp r2, #0 + bne myloop - // Set breakpoint to exit - bkpt #0x00 +myexit: + bkpt From 14518803dd2dbdaf15a1cd3e9216b6f0a919aeeb Mon Sep 17 00:00:00 2001 From: xp Date: Fri, 24 Apr 2020 14:31:52 +0800 Subject: [PATCH 0886/1435] bugfix --- flashloaders/stm32l4.s | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/flashloaders/stm32l4.s b/flashloaders/stm32l4.s index 0a68b687a..79abac0d4 100644 --- a/flashloaders/stm32l4.s +++ b/flashloaders/stm32l4.s @@ -10,9 +10,9 @@ mycopy: myloop: # copy 8 bytes ldr r3, [r0] - ldr r3, [r0， #4] + ldr r4, [r0, #4] str r3, [r1] - str r3, [r1， #4] + str r4, [r1, #4] add r0, r0, #8 add r1, r1, #8 From 43085438f2c674d2fa3506dcb698930b87b71432 Mon Sep 17 00:00:00 2001 From: xp Date: Fri, 24 Apr 2020 16:39:56 +0800 Subject: [PATCH 0887/1435] update --- flashloaders/stm32f0.s | 58 +++++++++++++++++++++++----------------- flashloaders/stm32f4.s | 11 ++++---- flashloaders/stm32f4lv.s | 11 ++++---- flashloaders/stm32f7.s | 11 ++++---- flashloaders/stm32f7lv.s | 11 ++++---- flashloaders/stm32l0x.s | 8 +++--- flashloaders/stm32l4.s | 15 ++++++----- flashloaders/stm32lx.s | 8 +++--- 8 files changed, 76 insertions(+), 57 deletions(-) diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s index 885353912..1adeada05 100644 --- a/flashloaders/stm32f0.s +++ b/flashloaders/stm32f0.s @@ -1,53 +1,63 @@ .syntax unified .text +flash_base: + .align 2 + .word 0x40022000 +flash_off_cr: + .word 0x10 +flash_off_sr: + .word 0x0c + .global mycopy mycopy: - ldr r12, flash_base - ldr r11, flash_off_cr - add r11, r11, r12 - ldr r10, flash_off_sr - add r10, r10, r12 + ldr r7, =flash_base + ldr r4, [r7] + ldr r7, =flash_off_cr + ldr r6, [r7] + adds r6, r6, r4 + ldr r7, =flash_off_sr + ldr r5, [r7] + adds r5, r5, r4 myloop: # FLASH_CR ^= 1 - ldr r3, [r11] - orr r3, r3, #0x1 - str r3, [r11] + ldr r7, =0x1 + ldr r3, [r6] + orrs r3, r3, r7 + str r3, [r6] # copy 2 bytes ldrh r3, [r0] strh r3, [r1] - add r0, r0, #2 - add r1, r1, #2 + ldr r7, =2 + adds r0, r0, r7 + adds r1, r1, r7 # wait if FLASH_SR == 1 mywait: - ldr r3, [r10] - tst r3, #0x1 + ldr r7, =0x1 + ldr r3, [r5] + tst r3, r7 beq mywait # exit if FLASH_SR == 4 - tst r3, #0x4 + ldr r7, =0x4 + tst r3, r7 beq myexit # loop if r2 != 0 - sub r2, r2, #1 + ldr r7, =0x1 + subs r2, r2, r7 cmp r2, #0 bne myloop myexit: # FLASH_CR &= ~1 - ldr r3, [r11] - bic r3, r3, #0x1 - str r3, [r11] + ldr r7, =0x1 + ldr r3, [r6] + bics r3, r3, r7 + str r3, [r6] bkpt - -flash_base: - .word 0x40022000 -flash_off_cr: - .word 0x10 -flash_off_sr: - .word 0x0c diff --git a/flashloaders/stm32f4.s b/flashloaders/stm32f4.s index a47054dae..938ca8401 100644 --- a/flashloaders/stm32f4.s +++ b/flashloaders/stm32f4.s @@ -1,6 +1,12 @@ .syntax unified .text +flash_base: + .align 2 + .word 0x40023c00 +flash_off_sr: + .word 0x0e + .global mycopy mycopy: ldr r12, flash_base @@ -28,8 +34,3 @@ mywait: myexit: bkpt - -flash_base: - .word 0x40023c00 -flash_off_sr: - .word 0x0e diff --git a/flashloaders/stm32f4lv.s b/flashloaders/stm32f4lv.s index cfbbe8520..fa8bedbaa 100644 --- a/flashloaders/stm32f4lv.s +++ b/flashloaders/stm32f4lv.s @@ -1,6 +1,12 @@ .syntax unified .text +flash_base: + .align 2 + .word 0x40023c00 +flash_off_sr: + .word 0x0e + .global mycopy mycopy: ldr r12, flash_base @@ -28,8 +34,3 @@ mywait: myexit: bkpt - -flash_base: - .word 0x40023c00 -flash_off_sr: - .word 0x0e diff --git a/flashloaders/stm32f7.s b/flashloaders/stm32f7.s index f873f0ebd..604ab0465 100644 --- a/flashloaders/stm32f7.s +++ b/flashloaders/stm32f7.s @@ -1,6 +1,12 @@ .syntax unified .text +flash_base: + .align 2 + .word 0x40023c00 +flash_off_sr: + .word 0x0e + .global mycopy mycopy: ldr r12, flash_base @@ -31,8 +37,3 @@ mywait: myexit: bkpt - -flash_base: - .word 0x40023c00 -flash_off_sr: - .word 0x0e diff --git a/flashloaders/stm32f7lv.s b/flashloaders/stm32f7lv.s index fe5be0529..157347542 100644 --- a/flashloaders/stm32f7lv.s +++ b/flashloaders/stm32f7lv.s @@ -1,6 +1,12 @@ .syntax unified .text +flash_base: + .algin 2 + .word 0x40023c00 +flash_off_sr: + .word 0x0e + .global mycopy mycopy: ldr r12, flash_base @@ -31,8 +37,3 @@ mywait: myexit: bkpt - -flash_base: - .word 0x40023c00 -flash_off_sr: - .word 0x0e diff --git a/flashloaders/stm32l0x.s b/flashloaders/stm32l0x.s index 1ce7dd144..893aa6f9b 100644 --- a/flashloaders/stm32l0x.s +++ b/flashloaders/stm32l0x.s @@ -8,11 +8,13 @@ myloop: ldr r3, [r0] str r3, [r1] - add r0, r0, #4 - add r1, r1, #4 + ldr r7, =4 + add r0, r0, r7 + add r1, r1, r7 # loop if r2 != 0 - sub r2, r2, #1 + ldr r7, =1 + subs r2, r2, r7 cmp r2, #0 bne myloop diff --git a/flashloaders/stm32l4.s b/flashloaders/stm32l4.s index 0a68b687a..b136e59e7 100644 --- a/flashloaders/stm32l4.s +++ b/flashloaders/stm32l4.s @@ -1,6 +1,12 @@ .syntax unified .text +flash_base: + .align 2 + .word 0x40022000 +flash_off_bsy: + .word 0x12 + .global mycopy mycopy: ldr r12, flash_base @@ -10,9 +16,9 @@ mycopy: myloop: # copy 8 bytes ldr r3, [r0] - ldr r3, [r0， #4] + ldr r4, [r0, #4] str r3, [r1] - str r3, [r1， #4] + str r4, [r1, #4] add r0, r0, #8 add r1, r1, #8 @@ -30,8 +36,3 @@ mywait: myexit: bkpt - -flash_base: - .word 0x40022000 -flash_off_bsy: - .word 0x12 diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s index 1ce7dd144..893aa6f9b 100644 --- a/flashloaders/stm32lx.s +++ b/flashloaders/stm32lx.s @@ -8,11 +8,13 @@ myloop: ldr r3, [r0] str r3, [r1] - add r0, r0, #4 - add r1, r1, #4 + ldr r7, =4 + add r0, r0, r7 + add r1, r1, r7 # loop if r2 != 0 - sub r2, r2, #1 + ldr r7, =1 + subs r2, r2, r7 cmp r2, #0 bne myloop From 8aaf95abf6dedef3f5de1f6659aecfb0e7eb60eb Mon Sep 17 00:00:00 2001 From: xp Date: Fri, 24 Apr 2020 16:59:47 +0800 Subject: [PATCH 0888/1435] rewrite flashloaders as clean room doc --- flashloaders/stm32f0.s | 95 ++++++++++++++++++++++++++-------------- flashloaders/stm32f4.s | 54 ++++++++++++----------- flashloaders/stm32f4lv.s | 55 ++++++++++++----------- flashloaders/stm32f7.s | 66 +++++++++++++++------------- flashloaders/stm32f7lv.s | 67 +++++++++++++++------------- flashloaders/stm32l0x.s | 76 +++++++------------------------- flashloaders/stm32l4.s | 61 +++++++++++++------------- flashloaders/stm32lx.s | 72 +++++++----------------------- 8 files changed, 257 insertions(+), 289 deletions(-) diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s index fe12f90f3..8eaf81905 100644 --- a/flashloaders/stm32f0.s +++ b/flashloaders/stm32f0.s @@ -1,32 +1,63 @@ -/* Adopted from STM AN4065 stm32f0xx_flash.c:FLASH_ProgramWord */ - -write: - ldr r4, STM32_FLASH_BASE - mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */ - mov r6, #4 /* PGERR */ -write_half_word: - ldr r3, [r4, #16] /* FLASH->CR */ - orr r3, r5 - str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */ - ldrh r3, [r0] /* r3 = *sram */ - strh r3, [r1] /* *flash = r3 */ -busy: - ldr r3, [r4, #12] /* FLASH->SR */ - tst r3, r5 /* FLASH_SR_BUSY */ - beq busy - - tst r3, r6 /* PGERR */ - bne exit - - add r0, r0, #2 /* sram += 2 */ - add r1, r1, #2 /* flash += 2 */ - sub r2, r2, #0x01 /* count-- */ - cmp r2, #0 - bne write_half_word -exit: - ldr r3, [r4, #16] /* FLASH->CR */ - bic r3, r5 - str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */ - bkpt #0x00 - -STM32_FLASH_BASE: .word 0x40022000 + .syntax unified + .text + + .global mycopy +mycopy: + ldr r7, =flash_base + ldr r4, [r7] + ldr r7, =flash_off_cr + ldr r6, [r7] + adds r6, r6, r4 + ldr r7, =flash_off_sr + ldr r5, [r7] + adds r5, r5, r4 + +myloop: + # FLASH_CR ^= 1 + ldr r7, =0x1 + ldr r3, [r6] + orrs r3, r3, r7 + str r3, [r6] + + # copy 2 bytes + ldrh r3, [r0] + strh r3, [r1] + + ldr r7, =2 + adds r0, r0, r7 + adds r1, r1, r7 + + # wait if FLASH_SR == 1 +mywait: + ldr r7, =0x1 + ldr r3, [r5] + tst r3, r7 + beq mywait + + # exit if FLASH_SR == 4 + ldr r7, =0x4 + tst r3, r7 + beq myexit + + # loop if r2 != 0 + ldr r7, =0x1 + subs r2, r2, r7 + cmp r2, #0 + bne myloop + +myexit: + # FLASH_CR &= ~1 + ldr r7, =0x1 + ldr r3, [r6] + bics r3, r3, r7 + str r3, [r6] + + bkpt + +flash_base: + .align 2 + .word 0x40022000 +flash_off_cr: + .word 0x10 +flash_off_sr: + .word 0x0c diff --git a/flashloaders/stm32f4.s b/flashloaders/stm32f4.s index 21f5a8f7f..085e6870c 100644 --- a/flashloaders/stm32f4.s +++ b/flashloaders/stm32f4.s @@ -1,32 +1,36 @@ -.global start -.syntax unified + .syntax unified + .text -@ r0 = source -@ r1 = target -@ r2 = wordcount -@ r3 = flash_base -@ r4 = temp + .global mycopy +mycopy: + ldr r12, flash_base + ldr r10, flash_off_sr + add r10, r10, r12 -start: - ldr r3, flash_base -next: - cbz r2, done - ldr r4, [r0] - str r4, [r1] +myloop: + # copy 4 bytes + ldr r3, [r0] + str r3, [r1] -wait: - ldrh r4, [r3, #0x0e] - tst.w r4, #1 - bne wait + add r0, r0, #4 + add r1, r1, #4 - add r0, #4 - add r1, #4 - sub r2, #1 - b next -done: - bkpt + # wait if FLASH_SR == 1 +mywait: + ldrh r3, [r10] + tst r3, #0x1 + beq mywait + + # loop if r2 != 0 + sub r2, r2, #1 + cmp r2, #0 + bne myloop -.align 2 +myexit: + bkpt flash_base: - .word 0x40023c00 + .align 2 + .word 0x40023c00 +flash_off_sr: + .word 0x0e diff --git a/flashloaders/stm32f4lv.s b/flashloaders/stm32f4lv.s index f60ee8797..f0adfd208 100644 --- a/flashloaders/stm32f4lv.s +++ b/flashloaders/stm32f4lv.s @@ -1,33 +1,36 @@ -.global start -.syntax unified + .syntax unified + .text -@ r0 = source -@ r1 = target -@ r2 = wordcount -@ r3 = flash_base -@ r4 = temp + .global mycopy +mycopy: + ldr r12, flash_base + ldr r10, flash_off_sr + add r10, r10, r12 -start: - lsls r2, r2, #2 - ldr r3, flash_base -next: - cbz r2, done - ldrb r4, [r0] - strb r4, [r1] +myloop: + # copy 1 bytes + ldrb r3, [r0] + strb r3, [r1] -wait: - ldrh r4, [r3, #0x0e] - tst.w r4, #1 - bne wait + add r0, r0, #1 + add r1, r1, #1 - add r0, #1 - add r1, #1 - sub r2, #1 - b next -done: - bkpt + # wait if FLASH_SR == 1 +mywait: + ldrh r3, [r10] + tst r3, #0x1 + beq mywait + + # loop if r2 != 0 + sub r2, r2, #1 + cmp r2, #0 + bne myloop -.align 2 +myexit: + bkpt flash_base: - .word 0x40023c00 + .align 2 + .word 0x40023c00 +flash_off_sr: + .word 0x0e diff --git a/flashloaders/stm32f7.s b/flashloaders/stm32f7.s index 0334c80a0..5d87515be 100644 --- a/flashloaders/stm32f7.s +++ b/flashloaders/stm32f7.s @@ -1,33 +1,39 @@ -.global start -.syntax unified - -@ r0 = source -@ r1 = target -@ r2 = wordcount -@ r3 = flash_base -@ r4 = temp - -start: - ldr r3, flash_base -next: - cbz r2, done - ldr r4, [r0] - str r4, [r1] - dsb sy - -wait: - ldrh r4, [r3, #0x0e] - tst.w r4, #1 - bne wait - - add r0, #4 - add r1, #4 - sub r2, #1 - b next -done: - bkpt + .syntax unified + .text + + .global mycopy +mycopy: + ldr r12, flash_base + ldr r10, flash_off_sr + add r10, r10, r12 + +myloop: + # copy 4 bytes + ldr r3, [r0] + str r3, [r1] + + add r0, r0, #4 + add r1, r1, #4 -.align 2 + # memory barrier + dsb sy + + # wait if FLASH_SR == 1 +mywait: + ldrh r3, [r10] + tst r3, #0x1 + beq mywait + + # loop if r2 != 0 + sub r2, r2, #1 + cmp r2, #0 + bne myloop + +myexit: + bkpt flash_base: - .word 0x40023c00 + .align 2 + .word 0x40023c00 +flash_off_sr: + .word 0x0e diff --git a/flashloaders/stm32f7lv.s b/flashloaders/stm32f7lv.s index 650922719..70cd948bd 100644 --- a/flashloaders/stm32f7lv.s +++ b/flashloaders/stm32f7lv.s @@ -1,34 +1,39 @@ -.global start -.syntax unified - -@ r0 = source -@ r1 = target -@ r2 = wordcount -@ r3 = flash_base -@ r4 = temp - -start: - lsls r2, r2, #2 - ldr r3, flash_base -next: - cbz r2, done - ldrb r4, [r0] - strb r4, [r1] - dsb sy - -wait: - ldrh r4, [r3, #0x0e] - tst.w r4, #1 - bne wait - - add r0, #1 - add r1, #1 - sub r2, #1 - b next -done: - bkpt + .syntax unified + .text + + .global mycopy +mycopy: + ldr r12, flash_base + ldr r10, flash_off_sr + add r10, r10, r12 + +myloop: + # copy 1 byte + ldrb r3, [r0] + strb r3, [r1] + + add r0, r0, #1 + add r1, r1, #1 -.align 2 + # memory barrier + dsb sy + + # wait if FLASH_SR == 1 +mywait: + ldrh r3, [r10] + tst r3, #0x1 + beq mywait + + # loop if r2 != 0 + sub r2, r2, #1 + cmp r2, #0 + bne myloop + +myexit: + bkpt flash_base: - .word 0x40023c00 + .algin 2 + .word 0x40023c00 +flash_off_sr: + .word 0x0e diff --git a/flashloaders/stm32l0x.s b/flashloaders/stm32l0x.s index fcbd06e39..893aa6f9b 100644 --- a/flashloaders/stm32l0x.s +++ b/flashloaders/stm32l0x.s @@ -1,64 +1,22 @@ -/*************************************************************************** - * Copyright (C) 2010 by Spencer Oliver * - * spen@spen-soft.co.uk * - * * - * Copyright (C) 2011 Øyvind Harboe * - * oyvind.harboe@zylin.com * - * * - * Copyright (C) 2011 Clement Burin des Roziers * - * clement.burin-des-roziers@hikob.com * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ - - -// Build : arm-eabi-gcc -c stm32lx.S - .text .syntax unified - .cpu cortex-m0plus - .thumb - .thumb_func - .global write - -/* - r0 - source address - r1 - destination address - r2 - count -*/ + .text - // Go to compare - b test_done + .global mycopy +mycopy: +myloop: + # copy 4 bytes + ldr r3, [r0] + str r3, [r1] -write_word: - // Load one word from address in r0, increment by 4 - ldr r4, [r0] - // Store the word to address in r1, increment by 4 - str r4, [r1] - // Decrement r2 - subs r2, #1 - adds r1, #4 - // does not matter, only first addr is important - // next 15 bytes are in sequnce RM0367 page 66 - adds r0, #4 + ldr r7, =4 + add r0, r0, r7 + add r1, r1, r7 -test_done: - // Test r2 - cmp r2, #0 - // Loop if not zero - bcc.n write_word + # loop if r2 != 0 + ldr r7, =1 + subs r2, r2, r7 + cmp r2, #0 + bne myloop - // Set breakpoint to exit - bkpt #0x00 +myexit: + bkpt diff --git a/flashloaders/stm32l4.s b/flashloaders/stm32l4.s index 6aa2be050..5b5252a54 100644 --- a/flashloaders/stm32l4.s +++ b/flashloaders/stm32l4.s @@ -1,39 +1,38 @@ -.global start -.syntax unified + .syntax unified + .text -@ Adapted from stm32f4.s -@ STM32L4's flash controller expects double-word writes, has the flash -@ controller mapped in a different location with the registers we care about -@ moved down from the base address, and has BSY moved to bit 16 of SR. -@ r0 = source -@ r1 = target -@ r2 = wordcount -@ r3 = flash_base -@ r4 = temp -@ r5 = temp + .global mycopy +mycopy: + ldr r12, flash_base + ldr r10, flash_off_bsy + add r10, r10, r12 -start: - ldr r3, flash_base -next: - cbz r2, done - ldr r4, [r0] /* copy doubleword from source to target */ - ldr r5, [r0, #4] - str r4, [r1] - str r5, [r1, #4] +myloop: + # copy 8 bytes + ldr r3, [r0] + ldr r4, [r0, #4] + str r3, [r1] + str r4, [r1, #4] -wait: - ldrh r4, [r3, #0x12] /* high half of status register */ - tst r4, #1 /* BSY = bit 16 */ - bne wait + add r0, r0, #8 + add r1, r1, #8 - add r0, #8 - add r1, #8 - sub r2, #1 - b next -done: - bkpt + # wait if FLASH_BSY[0b] == 1 +mywait: + ldrh r3, [r10] + tst r3, #0x1 + beq mywait + + # loop if r2 != 0 + sub r2, r2, #1 + cmp r2, #0 + bne myloop -.align 2 +myexit: + bkpt flash_base: + .align 2 .word 0x40022000 +flash_off_bsy: + .word 0x12 diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s index 10e5644bf..893aa6f9b 100644 --- a/flashloaders/stm32lx.s +++ b/flashloaders/stm32lx.s @@ -1,60 +1,22 @@ -/*************************************************************************** - * Copyright (C) 2010 by Spencer Oliver * - * spen@spen-soft.co.uk * - * * - * Copyright (C) 2011 Øyvind Harboe * - * oyvind.harboe@zylin.com * - * * - * Copyright (C) 2011 Clement Burin des Roziers * - * clement.burin-des-roziers@hikob.com * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, write to the * - * Free Software Foundation, Inc., * - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * - ***************************************************************************/ - - -// Build : arm-eabi-gcc -c stm32lx.s - .text .syntax unified - .cpu cortex-m3 - .thumb - .thumb_func - .global write - -/* - r0 - source address - r1 - destination address - r2 - output, remaining word count -*/ + .text - // Go to compare - b test_done + .global mycopy +mycopy: +myloop: + # copy 4 bytes + ldr r3, [r0] + str r3, [r1] -write_word: - // Load one word from address in r0, increment by 4 - ldr.w ip, [r0], #4 - // Store the word to address in r1, increment by 4 - str.w ip, [r1], #4 - // Decrement r2 - subs r2, #1 + ldr r7, =4 + add r0, r0, r7 + add r1, r1, r7 -test_done: - // Test r2 - cmp r2, #0 - // Loop if not zero - bhi write_word + # loop if r2 != 0 + ldr r7, =1 + subs r2, r2, r7 + cmp r2, #0 + bne myloop - // Set breakpoint to exit - bkpt #0x00 +myexit: + bkpt From 8bbedab02055519312445b9d95bff1b52becc172 Mon Sep 17 00:00:00 2001 From: xp Date: Fri, 24 Apr 2020 17:21:32 +0800 Subject: [PATCH 0889/1435] fix typo --- flashloaders/stm32f7lv.s | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/flashloaders/stm32f7lv.s b/flashloaders/stm32f7lv.s index 70cd948bd..c144205f2 100644 --- a/flashloaders/stm32f7lv.s +++ b/flashloaders/stm32f7lv.s @@ -33,7 +33,7 @@ myexit: bkpt flash_base: - .algin 2 + .align 2 .word 0x40023c00 flash_off_sr: .word 0x0e From 5a1efc01f705e60bbec4a328b169e528106bb8f7 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 24 Apr 2020 15:01:28 +0200 Subject: [PATCH 0890/1435] Updated cmake settings - Distinguish test binaries from binaries - Build all binaries to /bin subfolder - Added comments to explain settings - Moved header files for logging and mmap --- CMakeLists.txt | 35 +++++++++++++------------------ Makefile | 1 + include/stlink.h | 2 +- include/stlink/usb.h | 2 +- src/common.c | 24 ++++++++++----------- src/gdbserver/gdb-server.c | 2 +- src/gdbserver/semihosting.c | 4 ++-- src/logging.c | 2 +- {include/stlink => src}/logging.h | 0 src/mmap.c | 2 +- {include/stlink => src}/mmap.h | 0 src/sg.c | 2 +- tests/CMakeLists.txt | 18 ++++++++-------- 13 files changed, 45 insertions(+), 49 deletions(-) rename {include/stlink => src}/logging.h (100%) rename {include/stlink => src}/mmap.h (100%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 3ec381239..8e6501dc9 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -7,6 +7,7 @@ cmake_policy(SET CMP0042 NEW) set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) +set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) ### @@ -25,10 +26,10 @@ option(STLINK_INSTALL_UDEV_RULES "Install udev rules files" ON) option(STLINK_INSTALL_MODPROBE_CONF "Install modprobe conf files" ON) option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) -# Determine project version +## Determine project version include(${CMAKE_MODULE_PATH}/get_version.cmake) -# Set C build flags +## Set C build flags if (NOT MSVC) include(${CMAKE_MODULE_PATH}/c_flags.cmake) else () @@ -39,11 +40,7 @@ else () set(CMAKE_C_FLAGS_RELWITHDEBINFO_INIT "/MT /Zi /O2 /Ob1 /D NDEBUG") endif () - -# ==== - -#set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) - +## Set installation directories for libraries if (IS_DIRECTORY ${LIB_INSTALL_DIR}) set(LIB_INSTALL_DIR ${LIB_INSTALL_DIR} CACHE PATH "Main library directory") set(STLINK_LIBRARY_PATH "${LIB_INSTALL_DIR}") @@ -52,6 +49,7 @@ else () set(STLINK_LIBRARY_PATH "${CMAKE_INSTALL_PREFIX}/${LIB_INSTALL_DIR}") endif () +## Set installation directories for header files if (IS_DIRECTORY ${INCLUDE_INSTALL_DIR}) set(INCLUDE_INSTALL_DIR ${INCLUDE_INSTALL_DIR} CACHE PATH "Main include directory") set(STLINK_INCLUDE_PATH "${INCLUDE_INSTALL_DIR}") @@ -67,12 +65,14 @@ endif () find_package(libusb REQUIRED) +## Package configuration (pkg-config) on unix-based systems if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) add_subdirectory(cmake/pkgconfig) find_package(PkgConfig) pkg_check_modules(GTK3 gtk+-3.0) endif () +## Check for system-specific additional header files and libraries include(CheckIncludeFile) CHECK_INCLUDE_FILE(sys/mman.h STLINK_HAVE_SYS_MMAN_H) @@ -94,20 +94,13 @@ else () set(SSP_LIB "") endif () -if (CMAKE_BUILD_TYPE STREQUAL "") - set(CMAKE_BUILD_TYPE "Debug") -endif () -if (${CMAKE_BUILD_TYPE} MATCHES "Debug") - include(CTest) -endif () +# ==== set(STLINK_HEADERS include/stlink.h include/stlink/usb.h include/stlink/sg.h - include/stlink/logging.h - include/stlink/mmap.h include/stlink/chipid.h include/stlink/flash_loader.h ) @@ -115,11 +108,11 @@ set(STLINK_HEADERS set(STLINK_SOURCE src/chipid.c src/common.c - src/usb.c - src/sg.c - src/logging.c src/flash_loader.c + src/logging.c src/md5.c + src/sg.c + src/usb.c ) if (WIN32 OR MINGW OR MSYS) @@ -139,6 +132,10 @@ if (MSVC) add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) endif () +# Include test execution for test-targets for target Debug +if (${CMAKE_BUILD_TYPE} MATCHES "Debug") + include(CTest) +endif () ### # Shared library @@ -236,8 +233,6 @@ else () target_link_libraries(st-info ${STLINK_LIB_SHARED} ${SSP_LIB}) endif () -install(TARGETS st-flash st-info RUNTIME DESTINATION bin) ### TODO: Check path - if (CMAKE_SYSTEM_NAME STREQUAL "Linux") if (STLINK_INSTALL_MODPROBE_CONF) install(FILES etc/modprobe.d/stlink_v1.conf DESTINATION ${STLINK_MODPROBED_DIR}/) diff --git a/Makefile b/Makefile index 444f1920b..57043ac97 100644 --- a/Makefile +++ b/Makefile @@ -40,6 +40,7 @@ package: build/Release @$(MAKE) -C build/Release package test: debug + @echo "[TEST]" @$(MAKE) -C build/Debug test build/Debug: diff --git a/include/stlink.h b/include/stlink.h index db737acb0..c311a527b 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -252,7 +252,7 @@ typedef struct flash_loader { #include "stlink/chipid.h" #include "stlink/flash_loader.h" #include "stlink/version.h" -#include "stlink/logging.h" +#include "../src/logging.h" #ifdef __cplusplus } diff --git a/include/stlink/usb.h b/include/stlink/usb.h index 1448481be..88a9a981a 100644 --- a/include/stlink/usb.h +++ b/include/stlink/usb.h @@ -12,7 +12,7 @@ #include "stlink.h" #include "stlinkusb.h" -#include "stlink/logging.h" +#include "../src/logging.h" #ifdef __cplusplus extern "C" { diff --git a/src/common.c b/src/common.c index 0dc6bc967..9dff4e768 100644 --- a/src/common.c +++ b/src/common.c @@ -13,8 +13,8 @@ #include #include "stlink.h" -#include "stlink/mmap.h" -#include "stlink/logging.h" +#include "mmap.h" +#include "logging.h" #include "md5.h" #ifndef O_BINARY @@ -2672,12 +2672,12 @@ int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr } else { num_empty = 0; } - /* + /* * TODO: investigate: - * a kind of weird behaviour here: + * a kind of weird behaviour here: * if the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed - */ + * still flash the whole file even if ignoring message is printed + */ err = stlink_write_flash(sl, addr, data, (num_empty == length) ? (uint32_t) length : (uint32_t) length - num_empty, num_empty == length); stlink_fwrite_finalize(sl, addr); return err; @@ -2721,12 +2721,12 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { } else { num_empty = 0; } - /* + /* * TODO: investigate: - * a kind of weird behaviour here: + * a kind of weird behaviour here: * if the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed - */ + * still flash the whole file even if ignoring message is printed + */ err = stlink_write_flash(sl, addr, mf.base, (num_empty == mf.len) ? (uint32_t) mf.len : (uint32_t) mf.len - num_empty, num_empty == mf.len); stlink_fwrite_finalize(sl, addr); unmap_file(&mf); @@ -3258,9 +3258,9 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) } /** - * Write option bytes + * Write option bytes * @param sl - * @param option_byte value to write + * @param option_byte value to write * @return 0 on success, -ve on failure. */ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) diff --git a/src/gdbserver/gdb-server.c b/src/gdbserver/gdb-server.c index 2b5b1d3cb..219c3424b 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/gdbserver/gdb-server.c @@ -24,7 +24,7 @@ #endif #include -#include +#include "../logging.h" #include "gdb-remote.h" #include "gdb-server.h" diff --git a/src/gdbserver/semihosting.c b/src/gdbserver/semihosting.c index 40758b61d..d41a83246 100644 --- a/src/gdbserver/semihosting.c +++ b/src/gdbserver/semihosting.c @@ -8,7 +8,7 @@ #include "semihosting.h" #include -#include +#include "../logging.h" static int mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { @@ -100,7 +100,7 @@ static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) // the requested bytes. (perhaps reading the whole area is faster??). // // If 16 and 8 bit writes are available, then they could be used instead. - + // Just return when the length is zero avoiding unneeded work. if (len == 0) return 0; diff --git a/src/logging.c b/src/logging.c index 59c2ea298..4ad89a5ed 100644 --- a/src/logging.c +++ b/src/logging.c @@ -9,7 +9,7 @@ #include #include -#include "stlink/logging.h" +#include "logging.h" static int max_level = UINFO; diff --git a/include/stlink/logging.h b/src/logging.h similarity index 100% rename from include/stlink/logging.h rename to src/logging.h diff --git a/src/mmap.c b/src/mmap.c index 90ae5fc17..b76e4ad64 100644 --- a/src/mmap.c +++ b/src/mmap.c @@ -3,7 +3,7 @@ #include #include -#include "stlink/mmap.h" +#include "mmap.h" void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offset) { diff --git a/include/stlink/mmap.h b/src/mmap.h similarity index 100% rename from include/stlink/mmap.h rename to src/mmap.h diff --git a/src/sg.c b/src/sg.c index 031cc64e5..eee6be498 100644 --- a/src/sg.c +++ b/src/sg.c @@ -83,7 +83,7 @@ #include #include "stlink.h" -#include "stlink/logging.h" +#include "logging.h" #define STLINK_OK 0x80 #define STLINK_FALSE 0x81 diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index c6b04ddb3..d6fe9fdd5 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -1,12 +1,12 @@ -set(TESTS usb sg) +set(TESTEXEC usb sg) -foreach (test ${TESTS}) - add_executable(${test} ${test}.c) - add_dependencies(${test} ${STLINK_LIB_STATIC}) - target_link_libraries(${test} ${STLINK_LIB_STATIC} ${SSP_LIB}) - add_test(${test} ${CMAKE_CURRENT_BINARY_DIR}/${test}) +foreach (test ${TESTEXEC}) + add_executable(test-${test} ${test}.c) + add_dependencies(test-${test} ${STLINK_LIB_STATIC}) + target_link_libraries(test-${test} ${STLINK_LIB_STATIC} ${SSP_LIB}) + add_test(test-${test} ${CMAKE_BINARY_DIR}/bin/test-${test}) endforeach () -add_executable(flash flash.c "${CMAKE_SOURCE_DIR}/src/tools/flash_opts.c") -target_link_libraries(flash ${STLINK_LIB_STATIC} ${SSP_LIB}) -add_test(flash ${CMAKE_CURRENT_BINARY_DIR}/flash) +add_executable(test-flash flash.c "${CMAKE_SOURCE_DIR}/src/tools/flash_opts.c") +target_link_libraries(test-flash ${STLINK_LIB_STATIC} ${SSP_LIB}) +add_test(test-flash ${CMAKE_BINARY_DIR}/bin/test-flash) From 15e2e1d811a384421aa78bcf5f9a28e91214a770 Mon Sep 17 00:00:00 2001 From: xp Date: Sat, 25 Apr 2020 14:08:58 +0800 Subject: [PATCH 0891/1435] fix align --- flashloaders/stm32f0.s | 2 +- flashloaders/stm32f4.s | 2 +- flashloaders/stm32f4lv.s | 2 +- flashloaders/stm32f7.s | 2 +- flashloaders/stm32f7lv.s | 2 +- flashloaders/stm32l4.s | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s index 8eaf81905..489e30672 100644 --- a/flashloaders/stm32f0.s +++ b/flashloaders/stm32f0.s @@ -54,8 +54,8 @@ myexit: bkpt -flash_base: .align 2 +flash_base: .word 0x40022000 flash_off_cr: .word 0x10 diff --git a/flashloaders/stm32f4.s b/flashloaders/stm32f4.s index 085e6870c..836f6e1f2 100644 --- a/flashloaders/stm32f4.s +++ b/flashloaders/stm32f4.s @@ -29,8 +29,8 @@ mywait: myexit: bkpt -flash_base: .align 2 +flash_base: .word 0x40023c00 flash_off_sr: .word 0x0e diff --git a/flashloaders/stm32f4lv.s b/flashloaders/stm32f4lv.s index f0adfd208..ef9f3a0bb 100644 --- a/flashloaders/stm32f4lv.s +++ b/flashloaders/stm32f4lv.s @@ -29,8 +29,8 @@ mywait: myexit: bkpt -flash_base: .align 2 +flash_base: .word 0x40023c00 flash_off_sr: .word 0x0e diff --git a/flashloaders/stm32f7.s b/flashloaders/stm32f7.s index 5d87515be..3f02e75f8 100644 --- a/flashloaders/stm32f7.s +++ b/flashloaders/stm32f7.s @@ -32,8 +32,8 @@ mywait: myexit: bkpt -flash_base: .align 2 +flash_base: .word 0x40023c00 flash_off_sr: .word 0x0e diff --git a/flashloaders/stm32f7lv.s b/flashloaders/stm32f7lv.s index c144205f2..99eb37d88 100644 --- a/flashloaders/stm32f7lv.s +++ b/flashloaders/stm32f7lv.s @@ -32,8 +32,8 @@ mywait: myexit: bkpt -flash_base: .align 2 +flash_base: .word 0x40023c00 flash_off_sr: .word 0x0e diff --git a/flashloaders/stm32l4.s b/flashloaders/stm32l4.s index 5b5252a54..16c6d1063 100644 --- a/flashloaders/stm32l4.s +++ b/flashloaders/stm32l4.s @@ -31,8 +31,8 @@ mywait: myexit: bkpt -flash_base: .align 2 +flash_base: .word 0x40022000 flash_off_bsy: .word 0x12 From 36bb77dd6f9aa3f4c2cb99845c827c75810047c6 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Sat, 25 Apr 2020 15:25:27 +0800 Subject: [PATCH 0892/1435] Cleanroom for flashloaders done --- flashloaders/Makefile | 38 ++++++ flashloaders/linker.ld | 9 ++ src/flash_loader.c | 273 +++++++++++++++++++---------------------- 3 files changed, 175 insertions(+), 145 deletions(-) create mode 100644 flashloaders/Makefile create mode 100644 flashloaders/linker.ld diff --git a/flashloaders/Makefile b/flashloaders/Makefile new file mode 100644 index 000000000..7b17cb2a0 --- /dev/null +++ b/flashloaders/Makefile @@ -0,0 +1,38 @@ +# Note that according to the original GPLed code, compiling is noted to be +# as simple as gcc -c, this fails with my tests where this will lead to a wrong +# address read by the program. +# This makefile will save your time from dealing with compile errors +# Adjust CC if needed + +CC = /opt/local/gcc-arm-none-eabi-8-2018-q4-major/bin/arm-none-eabi-gcc + +CFLAGS_thumb1 = -mcpu=Cortex-M0 -Tlinker.ld -ffreestanding -nostdlib +CFLAGS_thumb2 = -mcpu=Cortex-M3 -Tlinker.ld -ffreestanding -nostdlib + +all: stm32vl.o stm32f0.o stm32l.o stm32f4.o stm32f4_lv.o stm32l4.o stm32f7.o stm32f7_lv.o + +stm32vl.o: stm32f0.s + $(CC) stm32f0.s $(CFLAGS_thumb2) -o stm32vl.o +stm32f0.o: stm32f0.s + $(CC) stm32f0.s $(CFLAGS_thumb1) -o stm32f0.o +stm32l.o: stm32lx.s + $(CC) stm32lx.s $(CFLAGS_thumb2) -o stm32l.o +stm32f4.o: stm32f4.s + $(CC) stm32f4.s $(CFLAGS_thumb2) -o stm32f4.o +stm32f4_lv.o: stm32f4lv.s + $(CC) stm32f4lv.s $(CFLAGS_thumb2) -o stm32f4_lv.o +stm32l4.o: stm32l4.s + $(CC) stm32l4.s $(CFLAGS_thumb2) -o stm32l4.o +stm32f7.o: stm32f7.s + $(CC) stm32f7.s $(CFLAGS_thumb2) -o stm32f7.o +stm32f7_lv.o: stm32f7lv.s + $(CC) stm32f7lv.s $(CFLAGS_thumb2) -o stm32f7_lv.o + +clean: + rm *.o + + + + + + diff --git a/flashloaders/linker.ld b/flashloaders/linker.ld new file mode 100644 index 000000000..5bc738966 --- /dev/null +++ b/flashloaders/linker.ld @@ -0,0 +1,9 @@ +/*. Entry Point *./ +ENTRY( mycopy ) + + +/*. Specify the memory areas .*/ +MEMORY +{ + RAM ( xrw) : ORIGIN = 0x20000000 , LENGTH = 64K +} \ No newline at end of file diff --git a/src/flash_loader.c b/src/flash_loader.c index a1c9c3757..cee2aaba1 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -7,26 +7,34 @@ #define FLASH_REGS_BANK2_OFS 0x40 #define FLASH_BANK2_START_ADDR 0x08080000 -/* from openocd, contrib/loaders/flash/stm32.s */ -static const uint8_t loader_code_stm32vl[] = { - 0x08, 0x4c, /* ldr r4, STM32_FLASH_BASE */ - 0x1c, 0x44, /* add r4, r3 */ - /* write_half_word: */ - 0x01, 0x23, /* movs r3, #0x01 */ - 0x23, 0x61, /* str r3, [r4, #STM32_FLASH_CR_OFFSET] */ - 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */ - 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */ - /* busy: */ - 0xe3, 0x68, /* ldr r3, [r4, #STM32_FLASH_SR_OFFSET] */ - 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */ - 0xfb, 0xd0, /* beq busy */ - 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */ - 0x01, 0xd1, /* bne exit */ - 0x01, 0x3a, /* subs r2, r2, #0x01 */ - 0xf0, 0xd1, /* bne write_half_word */ - /* exit: */ - 0x00, 0xbe, /* bkpt #0x00 */ - 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */ + /* flashloaders/stm32f0.s -- compiled with thumb2 */ + static const uint8_t loader_code_stm32vl[] = { + 0x16, 0x4f, 0x3c, 0x68, + 0x16, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x16, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x4f, 0xf0, 0x01, 0x07, + 0x33, 0x68, 0x3b, 0x43, + 0x33, 0x60, 0x03, 0x88, + 0x0b, 0x80, 0x4f, 0xf0, + 0x02, 0x07, 0xc0, 0x19, + 0xc9, 0x19, 0x4f, 0xf0, + 0x01, 0x07, 0x2b, 0x68, + 0x3b, 0x42, 0xfa, 0xd0, + 0x4f, 0xf0, 0x04, 0x07, + 0x3b, 0x42, 0x04, 0xd0, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xe6, 0xd1, 0x4f, 0xf0, + 0x01, 0x07, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x20, + 0x54, 0x00, 0x00, 0x20, + 0x58, 0x00, 0x00, 0x20 }; /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ @@ -47,157 +55,132 @@ static const uint8_t loader_code_stm32vl[] = { 0x00, 0x30, // nop /* add r0,#0 */ 0x00, 0x30, // nop /* add r0,#0 */ #endif - 0x0A, 0x4C, // ldr r4, STM32_FLASH_BASE - 0x01, 0x25, // mov r5, #1 /* FLASH_CR_PG, FLASH_SR_BUSY */ - 0x04, 0x26, // mov r6, #4 /* PGERR */ - // write_half_word: - 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */ - 0x2B, 0x43, // orr r3, r5 - 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR |= FLASH_CR_PG */ - 0x03, 0x88, // ldrh r3, [r0] /* r3 = *sram */ - 0x0B, 0x80, // strh r3, [r1] /* *flash = r3 */ - // busy: - 0xE3, 0x68, // ldr r3, [r4, #12] /* FLASH->SR */ - 0x2B, 0x42, // tst r3, r5 /* FLASH_SR_BUSY */ - 0xFC, 0xD0, // beq busy - - 0x33, 0x42, // tst r3, r6 /* PGERR */ - 0x04, 0xD1, // bne exit - - 0x02, 0x30, // add r0, r0, #2 /* sram += 2 */ - 0x02, 0x31, // add r1, r1, #2 /* flash += 2 */ - 0x01, 0x3A, // sub r2, r2, #0x01 /* count-- */ - 0x00, 0x2A, // cmp r2, #0 - 0xF0, 0xD1, // bne write_half_word - // exit: - 0x23, 0x69, // ldr r3, [r4, #16] /* FLASH->CR */ - 0xAB, 0x43, // bic r3, r5 - 0x23, 0x61, // str r3, [r4, #16] /* FLASH->CR &= ~FLASH_CR_PG */ - 0x00, 0xBE, // bkpt #0x00 - 0x00, 0x20, 0x02, 0x40, /* STM32_FLASH_BASE: .word 0x40022000 */ + 0x13, 0x4f, 0x3c, 0x68, + 0x13, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x13, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x12, 0x4f, 0x33, 0x68, + 0x3b, 0x43, 0x33, 0x60, + 0x03, 0x88, 0x0b, 0x80, + 0x10, 0x4f, 0xc0, 0x19, + 0xc9, 0x19, 0x0e, 0x4f, + 0x2b, 0x68, 0x3b, 0x42, + 0xfb, 0xd0, 0x0e, 0x4f, + 0x3b, 0x42, 0x03, 0xd0, + 0x0a, 0x4f, 0xd2, 0x1b, + 0x00, 0x2a, 0xeb, 0xd1, + 0x08, 0x4f, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0xc0, 0x46, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x44, 0x00, 0x00, 0x20, + 0x48, 0x00, 0x00, 0x20, + 0x4c, 0x00, 0x00, 0x20, + 0x01, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32l[] = { // flashloaders/stm32lx.s - 0x04, 0xe0, // b test_done ; Go to compare - // write_word: - 0x04, 0x68, // ldr r4, [r0] ; Load one word from address in r0 - 0x0c, 0x60, // str r4, [r1] ; Store the word to address in r1 - 0x04, 0x30, // adds r0, #4 ; Increment r0 - 0x04, 0x31, // adds r1, #4 ; Increment r1 - 0x01, 0x3a, // subs r2, #1 ; Decrement r2 - // test_done: - 0x00, 0x2a, // cmp r2, #0 ; Compare r2 to 0 - 0xf8, 0xd8, // bhi write_word ; Loop if above 0 - 0x00, 0xbe, // bkpt #0x00 ; Set breakpoint to exit - 0x00, 0x00 + 0x03, 0x68, 0x0b, 0x60, + 0x4f, 0xf0, 0x04, 0x07, + 0x38, 0x44, 0x39, 0x44, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xf4, 0xd1, 0x00, 0xbe, }; static const uint8_t loader_code_stm32f4[] = { // flashloaders/stm32f4.s - 0x07, 0x4b, - - 0x62, 0xb1, - 0x04, 0x68, - 0x0c, 0x60, - - 0xdc, 0x89, - 0x14, 0xf0, 0x01, 0x0f, - 0xfb, 0xd1, - 0x00, 0xf1, 0x04, 0x00, - 0x01, 0xf1, 0x04, 0x01, - 0xa2, 0xf1, 0x01, 0x02, - 0xf1, 0xe7, - - 0x00, 0xbe, - - 0x00, 0x3c, 0x02, 0x40, + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32f4_lv[] = { // flashloaders/stm32f4lv.s - 0x92, 0x00, - - 0x08, 0x4b, - 0x62, 0xb1, - 0x04, 0x78, - 0x0c, 0x70, - - 0xdc, 0x89, - 0x14, 0xf0, 0x01, 0x0f, - 0xfb, 0xd1, - 0x00, 0xf1, 0x01, 0x00, - 0x01, 0xf1, 0x01, 0x01, - 0xa2, 0xf1, 0x01, 0x02, - 0xf1, 0xe7, - - 0x00, 0xbe, - 0x00, 0xbf, - - 0x00, 0x3c, 0x02, 0x40, + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32l4[] = { // flashloaders/stm32l4.s - 0x08, 0x4b, // start: ldr r3, [pc, #32] ; - 0x72, 0xb1, // next: cbz r2, - 0x04, 0x68, // ldr r4, [r0, #0] - 0x45, 0x68, // ldr r5, [r0, #4] - 0x0c, 0x60, // str r4, [r1, #0] - 0x4d, 0x60, // str r5, [r1, #4] - 0x5c, 0x8a, // wait: ldrh r4, [r3, #18] - 0x14, 0xf0, 0x01, 0x0f, // tst.w r4, #1 - 0xfb, 0xd1, // bne.n - 0x00, 0xf1, 0x08, 0x00, // add.w r0, r0, #8 - 0x01, 0xf1, 0x08, 0x01, // add.w r1, r1, #8 - 0xa2, 0xf1, 0x01, 0x02, // sub.w r2, r2, #1 - 0xef, 0xe7, // b.n - 0x00, 0xbe, // done: bkpt 0x0000 - 0x00, 0x20, 0x02, 0x40 // flash_base: .word 0x40022000 + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x44, 0x68, 0x0b, 0x60, + 0x4c, 0x60, 0x00, 0xf1, + 0x08, 0x00, 0x01, 0xf1, + 0x08, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x12, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32f7[] = { // flashloaders/stm32f7.s - 0x08, 0x4b, - 0x72, 0xb1, - 0x04, 0x68, - 0x0c, 0x60, - 0xbf, 0xf3, 0x4f, 0x8f, // DSB Memory barrier for in order flash write - 0xdc, 0x89, - 0x14, 0xf0, 0x01, 0x0f, - 0xfb, 0xd1, - 0x00, 0xf1, 0x04, 0x00, - 0x01, 0xf1, 0x04, 0x01, - 0xa2, 0xf1, 0x01, 0x02, - 0xef, 0xe7, - 0x00, 0xbe, // bkpt #0x00 - 0x00, 0x3c, 0x02, 0x40, + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32f7_lv[] = { // flashloaders/stm32f7lv.s - 0x92, 0x00, // lsls r2, r2, #2 - 0x09, 0x4b, // ldr r3, [pc, #36] ; (0x20000028 ) - // next: - 0x72, 0xb1, // cbz r2, 24 - 0x04, 0x78, // ldrb r4, [r0, #0] - 0x0c, 0x70, // strb r4, [r1, #0] - 0xbf, 0xf3, 0x4f, 0x8f, // dsb sy - // wait: - 0xdc, 0x89, // ldrh r4, [r3, #14] - 0x14, 0xf0, 0x01, 0x0f, // tst.w r4, #1 - 0xfb, 0xd1, // bne.n e - 0x00, 0xf1, 0x01, 0x00, // add r0, r0, #1 - 0x01, 0xf1, 0x01, 0x01, // add r1, r1, #1 - 0xa2, 0xf1, 0x01, 0x02, // sub r2, r2, #1 - 0xef, 0xe7, // b next - // done: - 0x00, 0xbe, // bkpt - 0x00, 0xbf, // nop - // flash_base: - 0x00, 0x3c, 0x02, 0x40 // .word 0x40023c00 + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 }; From 489a37e3c72858ca5fdcdcfb3af09decc397cbb6 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Sat, 25 Apr 2020 18:13:08 +0800 Subject: [PATCH 0893/1435] Document error fix --- flashloaders/cleanroom.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/flashloaders/cleanroom.md b/flashloaders/cleanroom.md index 594e7191a..1bae4535d 100644 --- a/flashloaders/cleanroom.md +++ b/flashloaders/cleanroom.md @@ -39,7 +39,7 @@ English version can be found below. 每次写入数据宽度为2字节（半字）。 -每完成一次写入，需等待flash完成写入，检查方式为读取FLASH_SR处4字节内容，若取值为1，则说明写入尚未完成，需继续轮询等待；否则需要检查FLASH_SR处值是否为4，若是4，则应直接准备退出。 +每完成一次写入，需等待flash完成写入，检查方式为读取FLASH_SR处4字节内容，若取值为1，则说明写入尚未完成，需继续轮询等待；否则需要检查FLASH_SR处值是否为4，若非4，则应直接准备退出。 退出：全部拷贝执行完毕后触发断点前，将FLASH_CR处4字节内容最低bit清为0，写回FLASH_CR。 @@ -155,7 +155,7 @@ Copy data from source to destination, after which trigger a breakpint to exit. B Before every copy, read a word from FLASH_CR, set the lowest bit to 1 and write back. Copy one half word each time. -How to wait for the write process: read a word from FLASH_SR, loop until the content is not 1. After that, check FLASH_SR, proceed if the content is not 4, otherwise exit. +How to wait for the write process: read a word from FLASH_SR, loop until the content is not 1. After that, check FLASH_SR, proceed if the content is 4, otherwise exit. Exit: after the copying process and before triggering the breakpoint, clear the lowest bit in FLASH_CR. From 9096984a8361c05b0d7b6205e212651c616f65cb Mon Sep 17 00:00:00 2001 From: xp Date: Sat, 25 Apr 2020 19:52:51 +0800 Subject: [PATCH 0894/1435] fix stm32f0 loop condition --- flashloaders/stm32f0.s | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s index 489e30672..3dd0ae6e8 100644 --- a/flashloaders/stm32f0.s +++ b/flashloaders/stm32f0.s @@ -34,10 +34,10 @@ mywait: tst r3, r7 beq mywait - # exit if FLASH_SR == 4 + # exit if FLASH_SR != 4 ldr r7, =0x4 tst r3, r7 - beq myexit + bne myexit # loop if r2 != 0 ldr r7, =0x1 From b0971737c89e872bce134fb1c38cdf819fb963de Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Sat, 25 Apr 2020 19:55:35 +0800 Subject: [PATCH 0895/1435] Sync flashloader.c with stm32f0.s --- src/flash_loader.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/flash_loader.c b/src/flash_loader.c index cee2aaba1..ba12b0b64 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -22,7 +22,7 @@ 0x01, 0x07, 0x2b, 0x68, 0x3b, 0x42, 0xfa, 0xd0, 0x4f, 0xf0, 0x04, 0x07, - 0x3b, 0x42, 0x04, 0xd0, + 0x3b, 0x42, 0x04, 0xd1, 0x4f, 0xf0, 0x01, 0x07, 0xd2, 0x1b, 0x00, 0x2a, 0xe6, 0xd1, 0x4f, 0xf0, @@ -66,7 +66,7 @@ 0xc9, 0x19, 0x0e, 0x4f, 0x2b, 0x68, 0x3b, 0x42, 0xfb, 0xd0, 0x0e, 0x4f, - 0x3b, 0x42, 0x03, 0xd0, + 0x3b, 0x42, 0x03, 0xd1, 0x0a, 0x4f, 0xd2, 0x1b, 0x00, 0x2a, 0xeb, 0xd1, 0x08, 0x4f, 0x33, 0x68, From 8b77d027d37fe21ea3fce1db6d63ae3042eb9a35 Mon Sep 17 00:00:00 2001 From: xp Date: Sat, 25 Apr 2020 20:21:13 +0800 Subject: [PATCH 0896/1435] fix: stm32-lv r2(4) and copy(1) has different data unit size --- flashloaders/stm32f4lv.s | 12 +++++++++--- flashloaders/stm32f7lv.s | 12 +++++++++--- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/flashloaders/stm32f4lv.s b/flashloaders/stm32f4lv.s index ef9f3a0bb..92f70facc 100644 --- a/flashloaders/stm32f4lv.s +++ b/flashloaders/stm32f4lv.s @@ -8,12 +8,18 @@ mycopy: add r10, r10, r12 myloop: - # copy 1 bytes + # copy 1 byte each time and 4 times as one group ldrb r3, [r0] + ldrb r4, [r0, #1] + ldrb r5, [r0, #2] + ldrb r6, [r0, #3] strb r3, [r1] + strb r4, [r1, #1] + strb r5, [r1, #2] + strb r6, [r1, #3] - add r0, r0, #1 - add r1, r1, #1 + add r0, r0, #4 + add r1, r1, #4 # wait if FLASH_SR == 1 mywait: diff --git a/flashloaders/stm32f7lv.s b/flashloaders/stm32f7lv.s index 99eb37d88..013b56f87 100644 --- a/flashloaders/stm32f7lv.s +++ b/flashloaders/stm32f7lv.s @@ -8,12 +8,18 @@ mycopy: add r10, r10, r12 myloop: - # copy 1 byte + # copy 1 byte each time and 4 times as one group ldrb r3, [r0] + ldrb r4, [r0, #1] + ldrb r5, [r0, #2] + ldrb r6, [r0, #3] strb r3, [r1] + strb r4, [r1, #1] + strb r5, [r1, #2] + strb r6, [r1, #3] - add r0, r0, #1 - add r1, r1, #1 + add r0, r0, #4 + add r1, r1, #4 # memory barrier dsb sy From 09b40ca7bcb8e30df0cf374946327f858771f456 Mon Sep 17 00:00:00 2001 From: xp Date: Sat, 25 Apr 2020 20:37:26 +0800 Subject: [PATCH 0897/1435] update --- flashloaders/stm32f4lv.s | 18 +++++++++--------- flashloaders/stm32f7lv.o | Bin 0 -> 792 bytes flashloaders/stm32f7lv.s | 18 +++++++++--------- 3 files changed, 18 insertions(+), 18 deletions(-) create mode 100644 flashloaders/stm32f7lv.o diff --git a/flashloaders/stm32f4lv.s b/flashloaders/stm32f4lv.s index 92f70facc..c338b984a 100644 --- a/flashloaders/stm32f4lv.s +++ b/flashloaders/stm32f4lv.s @@ -7,19 +7,19 @@ mycopy: ldr r10, flash_off_sr add r10, r10, r12 + # original r2 indicates the count of 4 bytes need to copy, + # but we can only copy one byte each time. + # as we have no flash larger than 1GB, we do a little trick here. + ldr r3, =4 + mul r2, r2, r3 + myloop: - # copy 1 byte each time and 4 times as one group + # copy 1 byte ldrb r3, [r0] - ldrb r4, [r0, #1] - ldrb r5, [r0, #2] - ldrb r6, [r0, #3] strb r3, [r1] - strb r4, [r1, #1] - strb r5, [r1, #2] - strb r6, [r1, #3] - add r0, r0, #4 - add r1, r1, #4 + add r0, r0, #1 + add r1, r1, #1 # wait if FLASH_SR == 1 mywait: diff --git a/flashloaders/stm32f7lv.o b/flashloaders/stm32f7lv.o new file mode 100644 index 0000000000000000000000000000000000000000..f71d5e6366b415ff04a5340db3c4e011bef88b53 GIT binary patch literal 792 zcmah{y-EW?5dQWqQG-8;T56*P3_%ZtfPyI^sFfk$3&cHhA%TQDaw{g4kD$Gc_!t)I zBgD>5@BzeV6SQ$Acbi-aabV{AX7}5<*_*vQJU$XaK$}1YqYQWnl6Y<)$Y2VScJ542RLe&berkQfu3RXob3Cs3+vm#hbw~drkAnZ%L@4FE z7DCPt3;7Bm>&!4$A!^_~wsrC;^8a)jfyN^k7}w)jXw&r=qf@@7yi3mg@@%=k6nTPN cf0HOq>EIrd&~!b1Z&BS1ZH(SSa7RA!3p%Ax&;S4c literal 0 HcmV?d00001 diff --git a/flashloaders/stm32f7lv.s b/flashloaders/stm32f7lv.s index 013b56f87..55c9add1a 100644 --- a/flashloaders/stm32f7lv.s +++ b/flashloaders/stm32f7lv.s @@ -7,19 +7,19 @@ mycopy: ldr r10, flash_off_sr add r10, r10, r12 + # original r2 indicates the count of 4 bytes need to copy, + # but we can only copy one byte each time. + # as we have no flash larger than 1GB, we do a little trick here. + ldr r3, =4 + mul r2, r2, r3 + myloop: - # copy 1 byte each time and 4 times as one group + # copy 1 byte ldrb r3, [r0] - ldrb r4, [r0, #1] - ldrb r5, [r0, #2] - ldrb r6, [r0, #3] strb r3, [r1] - strb r4, [r1, #1] - strb r5, [r1, #2] - strb r6, [r1, #3] - add r0, r0, #4 - add r1, r1, #4 + add r0, r0, #1 + add r1, r1, #1 # memory barrier dsb sy From a4fec73a27516f787fa0853b1fab9ecaa7225f61 Mon Sep 17 00:00:00 2001 From: xp Date: Sat, 25 Apr 2020 20:53:05 +0800 Subject: [PATCH 0898/1435] update --- flashloaders/stm32f4lv.s | 10 +++++----- flashloaders/stm32f7lv.o | Bin 792 -> 0 bytes flashloaders/stm32f7lv.s | 10 +++++----- 3 files changed, 10 insertions(+), 10 deletions(-) delete mode 100644 flashloaders/stm32f7lv.o diff --git a/flashloaders/stm32f4lv.s b/flashloaders/stm32f4lv.s index c338b984a..4ba351faa 100644 --- a/flashloaders/stm32f4lv.s +++ b/flashloaders/stm32f4lv.s @@ -7,11 +7,11 @@ mycopy: ldr r10, flash_off_sr add r10, r10, r12 - # original r2 indicates the count of 4 bytes need to copy, - # but we can only copy one byte each time. - # as we have no flash larger than 1GB, we do a little trick here. - ldr r3, =4 - mul r2, r2, r3 + # tip 1: original r2 indicates the count of 4 bytes need to copy, + # but we can only copy one byte each time. + # as we have no flash larger than 1GB, we do a little trick here. + # tip 2: r2 is always a power of 2 + mov r2, r2, lsl#2 myloop: # copy 1 byte diff --git a/flashloaders/stm32f7lv.o b/flashloaders/stm32f7lv.o deleted file mode 100644 index f71d5e6366b415ff04a5340db3c4e011bef88b53..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 792 zcmah{y-EW?5dQWqQG-8;T56*P3_%ZtfPyI^sFfk$3&cHhA%TQDaw{g4kD$Gc_!t)I zBgD>5@BzeV6SQ$Acbi-aabV{AX7}5<*_*vQJU$XaK$}1YqYQWnl6Y<)$Y2VScJ542RLe&berkQfu3RXob3Cs3+vm#hbw~drkAnZ%L@4FE z7DCPt3;7Bm>&!4$A!^_~wsrC;^8a)jfyN^k7}w)jXw&r=qf@@7yi3mg@@%=k6nTPN cf0HOq>EIrd&~!b1Z&BS1ZH(SSa7RA!3p%Ax&;S4c diff --git a/flashloaders/stm32f7lv.s b/flashloaders/stm32f7lv.s index 55c9add1a..d82726eeb 100644 --- a/flashloaders/stm32f7lv.s +++ b/flashloaders/stm32f7lv.s @@ -7,11 +7,11 @@ mycopy: ldr r10, flash_off_sr add r10, r10, r12 - # original r2 indicates the count of 4 bytes need to copy, - # but we can only copy one byte each time. - # as we have no flash larger than 1GB, we do a little trick here. - ldr r3, =4 - mul r2, r2, r3 + # tip 1: original r2 indicates the count in 4 bytes need to copy, + # but we can only copy one byte each time. + # as we have no flash larger than 1GB, we do a little trick here. + # tip 2: r2 is always a power of 2 + mov r2, r2, lsl#2 myloop: # copy 1 byte From 65ca384008ed8516d3f582b22ef7cd4a39c8ed6a Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Sat, 25 Apr 2020 21:01:21 +0800 Subject: [PATCH 0899/1435] Sync flashloader.c with commit a4fec73a27516f787fa0853b1fab9ecaa7225f61 --- src/flash_loader.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/flash_loader.c b/src/flash_loader.c index ba12b0b64..a3fd2cefd 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -114,9 +114,10 @@ static const uint8_t loader_code_stm32f4_lv[] = { // flashloaders/stm32f4lv.s - 0xdf, 0xf8, 0x28, 0xc0, - 0xdf, 0xf8, 0x28, 0xa0, - 0xe2, 0x44, 0x03, 0x78, + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, 0x0b, 0x70, 0x00, 0xf1, 0x01, 0x00, 0x01, 0xf1, 0x01, 0x01, 0xba, 0xf8, @@ -167,9 +168,10 @@ static const uint8_t loader_code_stm32f7_lv[] = { // flashloaders/stm32f7lv.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x78, + 0xdf, 0xf8, 0x30, 0xc0, + 0xdf, 0xf8, 0x30, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, 0x0b, 0x70, 0x00, 0xf1, 0x01, 0x00, 0x01, 0xf1, 0x01, 0x01, 0xbf, 0xf3, From f82700623127538c8cf5cddbbeba6afc12d3adbf Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 25 Apr 2020 22:34:18 +0200 Subject: [PATCH 0900/1435] Refactoring for cmake build settings - Moved additional header files to /src - Simplified header-paths - Added missing license title for getopt - Added comments and sections to CMakeLists - Improved file structure (partially) - Co-build st-util with st-info & st-flash - GUI: Renamed .ui file to match executable - Added install targets for executables - Added missing "uninstall" cmd to Makefile --- CMakeLists.txt | 126 +++++++++++------- Makefile | 5 + cmake/packaging/CMakeLists.txt | 2 + doc/man/CMakeLists.txt | 4 + include/CMakeLists.txt | 1 + include/stlink.h | 18 +-- include/stlink/flash_loader.h | 2 +- include/stlink/tools/flash.h | 1 + src/chipid.c | 7 +- src/common.c | 2 +- src/flash_loader.c | 18 +-- src/gdbserver/CMakeLists.txt | 23 ---- src/getopt/LICENSE.txt | 2 + src/getopt/getopt.c | 38 +++--- .../stlinkusb.h => src/libusb_settings.h | 4 +- src/md5.c | 3 +- src/sg.c | 2 +- {include/stlink => src}/sg.h | 7 +- src/{gdbserver => st-util}/gdb-remote.c | 4 +- src/{gdbserver => st-util}/gdb-remote.h | 0 src/{gdbserver => st-util}/gdb-server.c | 4 +- src/{gdbserver => st-util}/gdb-server.h | 0 src/{gdbserver => st-util}/semihosting.c | 5 +- src/{gdbserver => st-util}/semihosting.h | 0 src/stlink-gui/CMakeLists.txt | 28 ++-- src/stlink-gui/gui.c | 4 +- src/stlink-gui/{gui.ui => stlink-gui.ui} | 0 src/tools/flash.c | 3 +- src/tools/flash_opts.c | 4 +- src/usb.c | 6 +- {include/stlink => src}/usb.h | 8 +- tests/CMakeLists.txt | 4 + tests/flash.c | 2 +- tests/sg.c | 1 + tests/usb.c | 2 +- 35 files changed, 185 insertions(+), 155 deletions(-) delete mode 100644 src/gdbserver/CMakeLists.txt rename include/stlink/stlinkusb.h => src/libusb_settings.h (91%) rename {include/stlink => src}/sg.h (95%) rename src/{gdbserver => st-util}/gdb-remote.c (99%) rename src/{gdbserver => st-util}/gdb-remote.h (100%) rename src/{gdbserver => st-util}/gdb-server.c (99%) rename src/{gdbserver => st-util}/gdb-server.h (100%) rename src/{gdbserver => st-util}/semihosting.c (99%) rename src/{gdbserver => st-util}/semihosting.h (100%) rename src/stlink-gui/{gui.ui => stlink-gui.ui} (100%) rename {include/stlink => src}/usb.h (96%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 8e6501dc9..95e27d215 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -95,36 +95,51 @@ else () endif () +### +# Main build process +### + +## Define include directories to avoid absolute paths for header defines +include_directories(${LIBUSB_INCLUDE_DIR}) + # ==== +include_directories(include) ### TODO: Clean this up... +include_directories(${PROJECT_BINARY_DIR}/include/stlink) +include_directories(include/stlink) +include_directories(include/stlink/tools) +# ==== + +include_directories(src) set(STLINK_HEADERS - include/stlink.h - include/stlink/usb.h - include/stlink/sg.h - include/stlink/chipid.h - include/stlink/flash_loader.h - ) + include/stlink.h + include/stlink/backend.h + include/stlink/chipid.h + include/stlink/commands.h + include/stlink/flash_loader.h + include/stlink/reg.h + src/logging.h + src/md5.h + src/sg.h + src/usb.h + ) set(STLINK_SOURCE - src/chipid.c - src/common.c - src/flash_loader.c - src/logging.c - src/md5.c - src/sg.c - src/usb.c - ) + src/common.c + src/chipid.c + src/flash_loader.c + src/logging.c + src/md5.c + src/sg.c + src/usb.c + ) if (WIN32 OR MINGW OR MSYS) + include_directories(src/mingw) set(STLINK_SOURCE "${STLINK_SOURCE};src/mmap.c;src/mingw/mingw.c") - set(STLINK_HEADERS "${STLINK_HEADERS};src/mingw/mingw.h") + set(STLINK_HEADERS "${STLINK_HEADERS};src/mmap.h;src/mingw/mingw.h") endif () -include_directories(${LIBUSB_INCLUDE_DIR}) -include_directories(include) -include_directories(${PROJECT_BINARY_DIR}/include) -include_directories(src/mingw) - if (MSVC) include_directories(src/win32) include_directories(src/getopt) @@ -132,11 +147,12 @@ if (MSVC) add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) endif () -# Include test execution for test-targets for target Debug +## Include test execution for test-targets for target Debug if (${CMAKE_BUILD_TYPE} MATCHES "Debug") include(CTest) endif () + ### # Shared library ### @@ -148,14 +164,15 @@ else (WIN32) endif () add_library( - ${STLINK_LIB_SHARED} SHARED - ${STLINK_HEADERS} # header files for ide projects generated by cmake - ${STLINK_SOURCE} - ) + ${STLINK_LIB_SHARED} SHARED + ${STLINK_HEADERS} # header files for ide projects generated by cmake + ${STLINK_SOURCE} + ) + target_link_libraries( - ${STLINK_LIB_SHARED} - ${LIBUSB_LIBRARY} - ) + ${STLINK_LIB_SHARED} + ${LIBUSB_LIBRARY} + ) set(STLINK_SHARED_VERSION ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}) @@ -163,7 +180,8 @@ message(STATUS "STLINK_LIB_SHARED: ${STLINK_LIB_SHARED}") message(STATUS "PROJECT_VERSION_MAJOR: ${PROJECT_VERSION_MAJOR}") message(STATUS "VERSION: ${STLINK_SHARED_VERSION}") -set_target_properties(${STLINK_LIB_SHARED} PROPERTIES +set_target_properties( + ${STLINK_LIB_SHARED} PROPERTIES SOVERSION ${PROJECT_VERSION_MAJOR} VERSION ${STLINK_SHARED_VERSION} ) @@ -182,7 +200,7 @@ else () target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB}) endif () -install(TARGETS ${STLINK_LIB_SHARED} DESTINATION ${STLINK_LIBRARY_PATH}) ### TODO: Check path +install(TARGETS ${STLINK_LIB_SHARED} DESTINATION ${STLINK_LIBRARY_PATH}) ### @@ -197,6 +215,11 @@ add_library( ${STLINK_SOURCE} ) +set_target_properties( + ${STLINK_LIB_STATIC} PROPERTIES + OUTPUT_NAME ${PROJECT_NAME} + ) + # Link static library with Apple macOS libraries if (APPLE) find_library(ObjC objc) @@ -205,32 +228,40 @@ if (APPLE) target_link_libraries(${STLINK_LIB_STATIC} ${CoreFoundation} ${IOKit} ${ObjC} ${SSP_LIB}) endif () -if (WIN32 OR MINGW OR MSYS) ### TODO: MinGW OR MSYS on Linux +if (WIN32 OR MINGW OR MSYS) target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} wsock32 ws2_32 ${SSP_LIB}) else () target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB}) endif () -set_target_properties(${STLINK_LIB_STATIC} PROPERTIES OUTPUT_NAME ${PROJECT_NAME}) - if (STLINK_STATIC_LIB) - install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH}) ### TODO: Check path + install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH}) endif () ### -# Tools +# Build toolset executables ### +set(ST-UTIL_SOURCES src/st-util/gdb-remote.c src/st-util/gdb-server.c src/st-util/semihosting.c) + +if (MSVC) + # Add getopt to sources + set(ST-UTIL_SOURCES "${ST-UTIL_SOURCES};src/getopt/getopt.c") +endif () + add_executable(st-flash src/tools/flash.c src/tools/flash_opts.c) add_executable(st-info src/tools/info.c) +add_executable(st-util ${ST-UTIL_SOURCES}) if (WIN32 OR APPLE) target_link_libraries(st-flash ${STLINK_LIB_STATIC} ${SSP_LIB}) target_link_libraries(st-info ${STLINK_LIB_STATIC} ${SSP_LIB}) + target_link_libraries(st-util ${STLINK_LIB_STATIC} ${SSP_LIB}) else () target_link_libraries(st-flash ${STLINK_LIB_SHARED} ${SSP_LIB}) target_link_libraries(st-info ${STLINK_LIB_SHARED} ${SSP_LIB}) + target_link_libraries(st-util ${STLINK_LIB_SHARED} ${SSP_LIB}) endif () if (CMAKE_SYSTEM_NAME STREQUAL "Linux") @@ -243,27 +274,24 @@ if (CMAKE_SYSTEM_NAME STREQUAL "Linux") endif () endif () -add_subdirectory(src/gdbserver) -add_subdirectory(src/stlink-gui) - +install(TARGETS st-flash DESTINATION bin) +install(TARGETS st-info DESTINATION bin) +install(TARGETS st-util DESTINATION bin) ### -# Others +# Additional build tasks ### -add_subdirectory(include) ### TODO: Check path -add_subdirectory(doc/man) -add_subdirectory(tests) - +# ==== +add_subdirectory(include) # contains subordinate CMakeLists for version config and old header includes + ### TODO: Clean this up ... # ==== +add_subdirectory(src/stlink-gui) # contains subordinate CMakeLists to build GUI +add_subdirectory(tests) # contains subordinate CMakeLists to build test executables +add_subdirectory(doc/man) # contains subordinate CMakeLists to generate manpages +add_subdirectory(cmake/packaging) # contains subordinate CMakeLists to build packages -### -# Package build -### - -add_subdirectory(cmake/packaging) -include(cmake/packaging/cpack_config.cmake) ### # Uninstall target diff --git a/Makefile b/Makefile index 57043ac97..74a4fece5 100644 --- a/Makefile +++ b/Makefile @@ -13,6 +13,7 @@ help: @echo " debug: Run a debug build" @echo " release: Run a release build" @echo " install: Install release build" + @echo " uninstall: Uninstall release build" @echo " package: Package release build" @echo " lint: Lint check all source-code" @echo " test: Build and run tests" @@ -35,6 +36,10 @@ install: build/Release @echo "[INSTALL] Release" @$(MAKE) -C build/Release install +uninstall: build/Release + @echo "[UNINSTALL] Release" + @$(MAKE) -C build/Release uninstall + package: build/Release @echo "[PACKAGE] Release" @$(MAKE) -C build/Release package diff --git a/cmake/packaging/CMakeLists.txt b/cmake/packaging/CMakeLists.txt index e831f611f..431c85d2d 100644 --- a/cmake/packaging/CMakeLists.txt +++ b/cmake/packaging/CMakeLists.txt @@ -2,3 +2,5 @@ add_subdirectory(debian) add_subdirectory(fedora) add_subdirectory(opensuse) add_subdirectory(windows) + +include(cpack_config.cmake) diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 090a2237e..221c84d7b 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -1,3 +1,7 @@ +### +# Generate manpages +### + set(MANPAGES st-util st-flash st-info) # Only generate manpages with pandoc in Debug builds diff --git a/include/CMakeLists.txt b/include/CMakeLists.txt index 6e5e3c279..6cf397659 100644 --- a/include/CMakeLists.txt +++ b/include/CMakeLists.txt @@ -2,6 +2,7 @@ configure_file( "${PROJECT_SOURCE_DIR}/include/stlink/version.h.in" "${CMAKE_BINARY_DIR}/include/stlink/version.h" ) + file(GLOB STLINK_HEADERS "stlink/*.h" "${CMAKE_BINARY_DIR}/include/stlink/*.h") install(FILES ${CMAKE_SOURCE_DIR}/include/stlink.h DESTINATION ${STLINK_INCLUDE_PATH}) install(FILES ${CMAKE_SOURCE_DIR}/include/stm32.h DESTINATION ${STLINK_INCLUDE_PATH}) diff --git a/include/stlink.h b/include/stlink.h index a28b60116..74c366d1c 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -137,7 +137,7 @@ typedef struct flash_loader { typedef struct _stlink stlink_t; -#include "stlink/backend.h" +#include struct _stlink { struct _stlink_backend *backend; @@ -245,14 +245,14 @@ typedef struct flash_loader { int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); -#include "stlink/sg.h" -#include "stlink/usb.h" -#include "stlink/reg.h" -#include "stlink/commands.h" -#include "stlink/chipid.h" -#include "stlink/flash_loader.h" -#include "stlink/version.h" -#include "../src/logging.h" +#include +#include +#include +#include +#include +#include +#include +#include #ifdef __cplusplus } diff --git a/include/stlink/flash_loader.h b/include/stlink/flash_loader.h index 95042f7b6..5f4526114 100644 --- a/include/stlink/flash_loader.h +++ b/include/stlink/flash_loader.h @@ -10,7 +10,7 @@ #include #include -#include "stlink.h" +#include #ifdef __cplusplus extern "C" { diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index 15e020b35..8c3f7d766 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -2,6 +2,7 @@ #define STLINK_TOOLS_FLASH_H_ #include + #include #define DEBUG_LOG_LEVEL 100 diff --git a/src/chipid.c b/src/chipid.c index 17cb4d546..fcc1c55eb 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -1,5 +1,5 @@ -#include "stlink.h" -#include "stlink/chipid.h" +#include +#include static const struct stlink_chipid_params devices[] = { { @@ -580,7 +580,6 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28K (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, - }, { // STM32G471/473/474/483/484 (from RM0440) @@ -621,8 +620,6 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x0, .bootrom_size = 0x0 }, - - }; const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) diff --git a/src/common.c b/src/common.c index 99cc0b513..9d21624f8 100644 --- a/src/common.c +++ b/src/common.c @@ -11,7 +11,7 @@ #include #include -#include "stlink.h" +#include #include "mmap.h" #include "logging.h" #include "md5.h" diff --git a/src/flash_loader.c b/src/flash_loader.c index a1c9c3757..ed253f92b 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -1,9 +1,9 @@ -#include "stlink.h" - #include #include #include +#include + #define FLASH_REGS_BANK2_OFS 0x40 #define FLASH_BANK2_START_ADDR 0x08080000 @@ -384,16 +384,16 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe /* run loader */ stlink_run(sl); -// This piece of code used to try to spin for .1 second by waiting +// This piece of code used to try to spin for .1 second by waiting // doing 10000 rounds of 10 microseconds. But because this usually runs -// on Unix-like OSes, the 10 microseconds get rounded up to the "tick" +// on Unix-like OSes, the 10 microseconds get rounded up to the "tick" // (actually almost two ticks) of the system. 1 milisecond. Thus, the -// ten thousand attempts, when "something goes wrong" that requires -// the error message "flash loader run error" would wait for something -// like 20 seconds before coming up with the error. -// by increasing the sleep-per-round to the same order-of-magnitude as +// ten thousand attempts, when "something goes wrong" that requires +// the error message "flash loader run error" would wait for something +// like 20 seconds before coming up with the error. +// by increasing the sleep-per-round to the same order-of-magnitude as // the tick-rounding that the OS uses, the wait until the error message is -// reduced to the same order of magnitude as what was intended. -- REW. +// reduced to the same order of magnitude as what was intended. -- REW. #define WAIT_ROUNDS 100 /* wait until done (reaches breakpoint) */ for (i = 0; i < WAIT_ROUNDS; i++) { diff --git a/src/gdbserver/CMakeLists.txt b/src/gdbserver/CMakeLists.txt deleted file mode 100644 index ff9bde165..000000000 --- a/src/gdbserver/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -set(STUTIL_SOURCE - gdb-remote.c - gdb-remote.h - gdb-server.c - gdb-server.h - semihosting.c - semihosting.h - ) - -if (MSVC) - # We need a getopt from somewhere... - set(STUTIL_SOURCE "${STUTIL_SOURCE};../getopt/getopt.c") -endif () - -add_executable(st-util ${STUTIL_SOURCE}) - -if (WIN32 OR APPLE) - target_link_libraries(st-util ${STLINK_LIB_STATIC} ${SSP_LIB}) -else () - target_link_libraries(st-util ${STLINK_LIB_SHARED} ${SSP_LIB}) -endif () - -install(TARGETS st-util RUNTIME DESTINATION bin) diff --git a/src/getopt/LICENSE.txt b/src/getopt/LICENSE.txt index 340303a96..4e4ed8bd5 100644 --- a/src/getopt/LICENSE.txt +++ b/src/getopt/LICENSE.txt @@ -1,3 +1,5 @@ +BSD 3-Clause License + Copyright (c) 2012, Kim Gräsman All rights reserved. diff --git a/src/getopt/getopt.c b/src/getopt/getopt.c index 72dce14d6..5dd45bff7 100644 --- a/src/getopt/getopt.c +++ b/src/getopt/getopt.c @@ -1,8 +1,8 @@ -#include "getopt.h" - #include #include +#include "getopt.h" + #if !defined(_MSC_VER) const int no_argument = 0; const int required_argument = 1; @@ -19,8 +19,8 @@ static char* optcursor = NULL; /* Implemented based on [1] and [2] for optional arguments. optopt is handled FreeBSD-style, per [3]. - Other GNU and FreeBSD extensions are purely accidental. - + Other GNU and FreeBSD extensions are purely accidental. + [1] http://pubs.opengroup.org/onlinepubs/000095399/functions/getopt.html [2] http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html [3] http://www.freebsd.org/cgi/man.cgi?query=getopt&sektion=3&manpath=FreeBSD+9.0-RELEASE @@ -37,22 +37,22 @@ int getopt(int argc, char* const argv[], const char* optstring) { if (optind >= argc) goto no_more_optchars; - /* If, when getopt() is called argv[optind] is a null pointer, getopt() + /* If, when getopt() is called argv[optind] is a null pointer, getopt() shall return -1 without changing optind. */ if (argv[optind] == NULL) goto no_more_optchars; - /* If, when getopt() is called *argv[optind] is not the character '-', + /* If, when getopt() is called *argv[optind] is not the character '-', getopt() shall return -1 without changing optind. */ if (*argv[optind] != '-') goto no_more_optchars; - /* If, when getopt() is called argv[optind] points to the string "-", + /* If, when getopt() is called argv[optind] points to the string "-", getopt() shall return -1 without changing optind. */ if (strcmp(argv[optind], "-") == 0) goto no_more_optchars; - /* If, when getopt() is called argv[optind] points to the string "--", + /* If, when getopt() is called argv[optind] points to the string "--", getopt() shall return -1 after incrementing optind. */ if (strcmp(argv[optind], "--") == 0) { ++optind; @@ -64,12 +64,12 @@ int getopt(int argc, char* const argv[], const char* optstring) { optchar = *optcursor; - /* FreeBSD: The variable optopt saves the last known option character + /* FreeBSD: The variable optopt saves the last known option character returned by getopt(). */ optopt = optchar; - /* The getopt() function shall return the next option character (if one is - found) from argv that matches a character in optstring, if there is + /* The getopt() function shall return the next option character (if one is + found) from argv that matches a character in optstring, if there is one that matches. */ optdecl = strchr(optstring, optchar); if (optdecl) { @@ -79,15 +79,15 @@ int getopt(int argc, char* const argv[], const char* optstring) { optarg = ++optcursor; if (*optarg == '\0') { /* GNU extension: Two colons mean an option takes an - optional arg; if there is text in the current argv-element - (i.e., in the same word as the option name itself, for example, + optional arg; if there is text in the current argv-element + (i.e., in the same word as the option name itself, for example, "-oarg"), then it is returned in optarg, otherwise optarg is set to zero. */ if (optdecl[2] != ':') { /* If the option was the last character in the string pointed to by an element of argv, then optarg shall contain the next element of argv, and optind shall be incremented by 2. If the resulting - value of optind is greater than argc, this indicates a missing + value of optind is greater than argc, this indicates a missing option-argument, and getopt() shall return an error indication. Otherwise, optarg shall point to the string following the @@ -97,7 +97,7 @@ int getopt(int argc, char* const argv[], const char* optstring) { if (++optind < argc) { optarg = argv[optind]; } else { - /* If it detects a missing option-argument, it shall return the + /* If it detects a missing option-argument, it shall return the colon character ( ':' ) if the first character of optstring was a colon, or a question-mark character ( '?' ) otherwise. */ @@ -112,7 +112,7 @@ int getopt(int argc, char* const argv[], const char* optstring) { optcursor = NULL; } } else { - /* If getopt() encounters an option character that is not contained in + /* If getopt() encounters an option character that is not contained in optstring, it shall return the question-mark ( '?' ) character. */ optchar = '?'; } @@ -131,7 +131,7 @@ int getopt(int argc, char* const argv[], const char* optstring) { [1] http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html */ -int getopt_long(int argc, char* const argv[], const char* optstring, +int getopt_long(int argc, char* const argv[], const char* optstring, const struct option* longopts, int* longindex) { const struct option* o = longopts; const struct option* match = NULL; @@ -165,7 +165,7 @@ int getopt_long(int argc, char* const argv[], const char* optstring, if (longindex) *longindex = (match - longopts); - /* If flag is NULL, then getopt_long() shall return val. + /* If flag is NULL, then getopt_long() shall return val. Otherwise, getopt_long() returns 0, and flag shall point to a variable which shall be set to val if the option is found, but left unchanged if the option is not found. */ @@ -190,7 +190,7 @@ int getopt_long(int argc, char* const argv[], const char* optstring, retval = ':'; } } else if (strchr(argv[optind], '=')) { - /* An argument was provided to a non-argument option. + /* An argument was provided to a non-argument option. I haven't seen this specified explicitly, but both GNU and BSD-based implementations show this behavior. */ diff --git a/include/stlink/stlinkusb.h b/src/libusb_settings.h similarity index 91% rename from include/stlink/stlinkusb.h rename to src/libusb_settings.h index 633d82bd0..c2e2df923 100644 --- a/include/stlink/stlinkusb.h +++ b/src/libusb_settings.h @@ -1,5 +1,5 @@ -#ifndef STLINKUSB_H -#define STLINKUSB_H +#ifndef LIBUSB_SETTINGS_H +#define LIBUSB_SETTINGS_H #include diff --git a/src/md5.c b/src/md5.c index e2b526c7d..521c52969 100755 --- a/src/md5.c +++ b/src/md5.c @@ -15,9 +15,10 @@ // IMPORTS //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -#include "md5.h" #include +#include "md5.h" + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // INTERNAL FUNCTIONS //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/src/sg.c b/src/sg.c index eee6be498..a0790f3c7 100644 --- a/src/sg.c +++ b/src/sg.c @@ -82,7 +82,7 @@ #include #include -#include "stlink.h" +#include #include "logging.h" #define STLINK_OK 0x80 diff --git a/include/stlink/sg.h b/src/sg.h similarity index 95% rename from include/stlink/sg.h rename to src/sg.h index 98efd4e58..3a8a7a239 100644 --- a/include/stlink/sg.h +++ b/src/sg.h @@ -1,5 +1,5 @@ /* - * File: stlink/sg.h + * File: sg.h * Author: karl * * Created on October 1, 2011, 11:29 PM @@ -8,8 +8,8 @@ #ifndef STLINK_SG_H #define STLINK_SG_H -#include "stlinkusb.h" -#include "stlink.h" +#include "libusb_settings.h" +#include #ifdef __cplusplus extern "C" { @@ -70,4 +70,3 @@ stlink_t* stlink_v1_open(const int verbose, int reset); #endif #endif /* STLINK_SG_H */ - diff --git a/src/gdbserver/gdb-remote.c b/src/st-util/gdb-remote.c similarity index 99% rename from src/gdbserver/gdb-remote.c rename to src/st-util/gdb-remote.c index 3b1794f3e..24636e8c9 100644 --- a/src/gdbserver/gdb-remote.c +++ b/src/st-util/gdb-remote.c @@ -8,6 +8,7 @@ #include #include #include + #if defined(__MINGW32__) || defined(_MSC_VER) #include #else @@ -15,6 +16,8 @@ #include #endif +#include "gdb-remote.h" + static const char hex[] = "0123456789abcdef"; int gdb_send_packet(int fd, char* data) { @@ -169,4 +172,3 @@ int gdb_check_for_interrupt(int fd) { return 0; } - diff --git a/src/gdbserver/gdb-remote.h b/src/st-util/gdb-remote.h similarity index 100% rename from src/gdbserver/gdb-remote.h rename to src/st-util/gdb-remote.h diff --git a/src/gdbserver/gdb-server.c b/src/st-util/gdb-server.c similarity index 99% rename from src/gdbserver/gdb-server.c rename to src/st-util/gdb-server.c index ce9f6eef7..a3839cfc8 100644 --- a/src/gdbserver/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -14,6 +14,7 @@ #include #define __attribute__(x) #endif + #if defined(_WIN32) #include #else @@ -24,8 +25,7 @@ #endif #include -#include "../logging.h" - +#include #include "gdb-remote.h" #include "gdb-server.h" #include "semihosting.h" diff --git a/src/gdbserver/gdb-server.h b/src/st-util/gdb-server.h similarity index 100% rename from src/gdbserver/gdb-server.h rename to src/st-util/gdb-server.h diff --git a/src/gdbserver/semihosting.c b/src/st-util/semihosting.c similarity index 99% rename from src/gdbserver/semihosting.c rename to src/st-util/semihosting.c index d41a83246..fed66ab60 100644 --- a/src/gdbserver/semihosting.c +++ b/src/st-util/semihosting.c @@ -5,10 +5,9 @@ #include #include -#include "semihosting.h" - #include -#include "../logging.h" +#include +#include "semihosting.h" static int mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { diff --git a/src/gdbserver/semihosting.h b/src/st-util/semihosting.h similarity index 100% rename from src/gdbserver/semihosting.h rename to src/st-util/semihosting.h diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 74b71cecd..b5ef99df9 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -1,35 +1,41 @@ +### +# Build GUI +### + +## GUI-Building requires the presence of a GTK3 toolset if (NOT GTK3_FOUND) message(STATUS "GTK3 not found!") - return() # no GTK3 present => no GUI build + return() # no GTK3 present => no GUI build else (GTK3_FOUND) message(STATUS "Found GTK3: -I${GTK3_INCLUDE_DIRS}, ${GTK3_LIBRARIES}") endif () -set(GUI_SOURCES gui.c gui.h) -set(INSTALLED_UI_DIR share/stlink) ### TODO: Check Path - include_directories(SYSTEM ${GTK3_INCLUDE_DIRS}) -# stlink-gui-local +set(GUI_SOURCES gui.c gui.h) + +## stlink-gui-local add_executable(stlink-gui-local ${GUI_SOURCES}) set_target_properties( stlink-gui-local PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_CURRENT_SOURCE_DIR}" ### TODO: Check Path + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_CURRENT_SOURCE_DIR}" + # Note: ${CMAKE_CURRENT_SOURCE_DIR} is src/stlink-gui ) target_link_libraries(stlink-gui-local ${STLINK_LIB_STATIC} ${GTK3_LDFLAGS} ${SSP_LIB}) -# stlink-gui +## stlink-gui add_executable(stlink-gui ${GUI_SOURCES}) set_target_properties( stlink-gui PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/${INSTALLED_UI_DIR}" ### TODO: Check Path + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin" + # Note: ${CMAKE_INSTALL_PREFIX} defaults to /usr/local ) target_link_libraries(stlink-gui ${STLINK_LIB_STATIC} ${GTK3_LDFLAGS} ${SSP_LIB}) -install(TARGETS stlink-gui RUNTIME DESTINATION bin) ### TODO: Check Path -install(FILES gui.ui DESTINATION ${INSTALLED_UI_DIR}) ### TODO: Check Path +install(TARGETS stlink-gui DESTINATION bin) +install(FILES stlink-gui.ui DESTINATION bin) if (${CMAKE_SYSTEM_NAME} MATCHES "Linux") - install(FILES stlink-gui.desktop DESTINATION share/applications) # Install desktop entry + install(FILES stlink-gui.desktop DESTINATION share/applications) # Install desktop application entry install(FILES icons/stlink-gui.svg DESTINATION share/icons/hicolor/scalable/apps) # Install icon endif () diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index f90196c06..5d5a422d5 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -779,10 +779,10 @@ static void stlink_gui_build_ui (STlinkGUI *gui) { GtkBuilder *builder; GtkListStore *devmem_store; GtkListStore *filemem_store; - gchar *ui_file = STLINK_UI_DIR "/gui.ui"; + gchar *ui_file = STLINK_UI_DIR "/stlink-gui.ui"; if (!g_file_test (ui_file, G_FILE_TEST_EXISTS)) - ui_file = "gui.ui"; + ui_file = "stlink-gui.ui"; builder = gtk_builder_new (); if (!gtk_builder_add_from_file (builder, ui_file, NULL)) { g_printerr ("Failed to load UI file: %s\n", ui_file); diff --git a/src/stlink-gui/gui.ui b/src/stlink-gui/stlink-gui.ui similarity index 100% rename from src/stlink-gui/gui.ui rename to src/stlink-gui/stlink-gui.ui diff --git a/src/tools/flash.c b/src/tools/flash.c index 3a9cc3674..841b93c3c 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -2,7 +2,6 @@ // TODO - this should be done as just a simple flag to the st-util command line... - #include #include #include @@ -10,7 +9,7 @@ #include #include -#include +#include static stlink_t *connected_stlink = NULL; diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index 085d278db..544d4ad90 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -1,9 +1,9 @@ -#include - #include #include #include +#include + static bool starts_with(const char * str, const char * prefix) { size_t n = strlen(prefix); if (strlen(str) < n) return false; diff --git a/src/usb.c b/src/usb.c index c9ea7039a..4e7a2983f 100644 --- a/src/usb.c +++ b/src/usb.c @@ -7,11 +7,13 @@ #include #endif #include -#include #include #include -#include "stlink.h" +#if defined(__MINGW32__) || defined(_MSC_VER) +#include +#endif +#include enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; diff --git a/include/stlink/usb.h b/src/usb.h similarity index 96% rename from include/stlink/usb.h rename to src/usb.h index 88a9a981a..968f38ba4 100644 --- a/include/stlink/usb.h +++ b/src/usb.h @@ -1,5 +1,5 @@ /* - * File: stlink/usb.h + * File: usb.h * Author: karl * * Created on October 1, 2011, 11:29 PM @@ -10,9 +10,9 @@ #include -#include "stlink.h" -#include "stlinkusb.h" -#include "../src/logging.h" +#include +#include "libusb_settings.h" +#include "logging.h" #ifdef __cplusplus extern "C" { diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index d6fe9fdd5..40d2203db 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -1,3 +1,7 @@ +### +# Build test executables +### + set(TESTEXEC usb sg) foreach (test ${TESTEXEC}) diff --git a/tests/flash.c b/tests/flash.c index 53032474a..903370cc3 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -3,7 +3,7 @@ #include #include -#include +#include #if defined(_MSC_VER) #include diff --git a/tests/sg.c b/tests/sg.c index 32ef55b69..1af177174 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -7,6 +7,7 @@ #include #include #include + #include #if defined(_MSC_VER) diff --git a/tests/usb.c b/tests/usb.c index a2c3ef8cd..d4098834d 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -1,4 +1,5 @@ #include + #include int main(int ac, char** av) { @@ -35,7 +36,6 @@ int main(int ac, char** av) { printf("cpuid:impl_id = %0#x, variant = %#x\n", cpuid.implementer_id, cpuid.variant); printf("cpuid:part = %#x, rev = %#x\n", cpuid.part, cpuid.revision); } - printf("-- read_sram\n"); static const uint32_t sram_base = STM32_SRAM_BASE; From 6a768d36f5c95ded5fb5ebc203d0ef2fa4a28802 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Mon, 27 Apr 2020 14:41:01 +0800 Subject: [PATCH 0901/1435] Add a documentation about flashloaders and adjust clean room document version order --- doc/flashloaders.md | 54 ++++++++++ flashloaders/cleanroom.md | 211 +++++++++++++++++++------------------- 2 files changed, 160 insertions(+), 105 deletions(-) create mode 100644 doc/flashloaders.md diff --git a/doc/flashloaders.md b/doc/flashloaders.md new file mode 100644 index 000000000..6a7cb3504 --- /dev/null +++ b/doc/flashloaders.md @@ -0,0 +1,54 @@ +# Flashloaders + +## What do flashloaders do + +The on-chip FLASH of STM32 needs to be written once a byte/half word/word/double word, which would lead to a unbearably long flashing time if the process is solely done by `stlink` from the host side. Flashloaders are introduced to cooperate with `stlink` so that the flashing process is divided into two stages. In the first stage, `stlink` loads flashloaders and flash data to SRAM where busy check is not applied. In the second stage, flashloaders are kick-started, writing data from SRAM to FLASH, where a busy check is applied. Thus the write-check\_if\_busy cycle of flashing is done solely by STM32 chip, which saves considerable time in communications between `stlink` and STM32. + +As SRAM is usually less in size than FLASH, `stlink` only flashes one page (may be less if SRAM is insufficient) at a time. The whole flashing process may consist of server launches of flashloaders. + +## The flahsing process + +1. `st-flash` loads compiled binary of corresponding flashloader to SRAM by calling `stlink_flash_loader_init` in `src/flash_loader.c` +2. `st-flash` erases corresponding flash page by calling `stlink_erase_flash_page` in `common.c`. +3. `st-flash` calls `stlink_flash_loader_run` in `flash_loader.c`. In this function + + buffer of one flash page is written to SRAM following the flashloader + + the buffer start address (in SRAM) is written to register `r0` + + the target start address (in FLASH, page aligned) is written to register `r1` + + the buffer size is written to register `r2` + + the start address (for now 0x20000000) of flash loader is written to `r15` (`pc`) + + After that, launching the flashloader and waiting for a halted core (triggered by our flashloader) and confirming that flashing is completed with a zeroed `r2` +4. flashloader part: much like a `memcpy` with busy check + + copy a single unit of data from SRAM to FLASH + + (for most devices) wait until flash is not busy + + trigger a breakpoint which halts the core when finished + +## Constraints + +Thus for developers who want to modify flashloaders, the following constraints should be satisfied. + +* only thumb-1 (for stm32f0 etc) or (thumb-1 and thumb-2) (for stm32f1 etc) instructions can be used, no ARM instructions. +* no stack, since it may overwrite buffer data. +* for most devices, after writing a single unit data, wait until FLASH is not busy. +* for some devices, check if there are any errors during flashing process. +* respect unit size of a single copy. +* after flashing, trigger a breakpint to halt the core. +* a sucessful run ends with `r2` set to zero when halted. +* be sure that flashloaders are at least be capable of running at 0x20000000 (the base address of SRAM) + + +For devices that need to wait until the flash is not busy, check FLASH_SR_BUSY bit. For devices that need to check if there is any errors during flash, check FLASH\_SR\_(X)ERR where `X` can be any error state + +FLASH_SR related offset and copy unit size may be found in ST official reference manuals and/or some header files in other open source projects. Clean room document provides some of them. + + +## Debug tricks + +If you find some flashloaders to be broken or you need to write a new flashloader for new devices, the following tricks may help. + +1. Modify `WAIT_ROUNDS` marco to a bigger value so that you will have time to kill st-flash when it is waiting for a halted core. +2. run `st-flash` and kill it after the flashloader is loaded to SRAM +3. launch `st-util` and `gdb`/`lldb` +4. set a breakpoint at the base address of SRAM +5. jump to the base address and start your debug + +The tricks work because by this means, most work (flash unlock, flash erase, load flashloader to SRAM) would have been done automatically, saving time to construct a debug environment. \ No newline at end of file diff --git a/flashloaders/cleanroom.md b/flashloaders/cleanroom.md index 1bae4535d..a468efe49 100644 --- a/flashloaders/cleanroom.md +++ b/flashloaders/cleanroom.md @@ -1,232 +1,233 @@ -English version can be found below. +Original Chinese version can be found below. -# 净室工程文档 +# Clean Room Documentation English Version -代码位于的section：`.text` -编译制导添加`.syntax unified` +Code is situated in section `.text` -传入参数约定： +Shall add a compile directive at the head: `.syntax unified` -参数全部通过寄存器传递 +**Calling convention**: -`r0`: 拷贝源点起始地址 -`r1`: 拷贝终点起始地址 -`r2`: 拷贝word（4字节）数(存在例外) +All parameters would be passed over registers -程序功能：将数据从源点拷贝到终点，在拷贝完毕后触发断点以结束执行，结束时`r2`值需清零表明传输完毕。 +`r0`: the base address of the copy source +`r1`: the base address of the copy destination +`r2`: the total word (4 bytes) count to be copied (with expeptions) -限制：不可使用栈，可自由使用的临时寄存器为`R3`到`R12`。`R13`为`sp`（stack pointer），`R14`为lr（一般用于储存跳转地址），`R15`为`pc`（program counter）。 +**What the program is expected to do**: -要求：每完成一次拷贝，需等待flash完成写入，单次拷贝宽度、检查写入完成的方式见每个文件的具体要求。 +Copy data from source to destination, after which trigger a breakpint to exit. Before exit, `r2` must be cleared to zero to indicate that the copy is done. -特殊地址`flash_base`存放地址需2字节对齐。 +**Limitation**: No stack operations are permitted. Registers ranging from `r3` to `r12` are free to use. Note that `r13` is `sp`(stack pointer), `r14` is `lr`(commonly used to store jump address), `r15` is `pc`(program counter). + +**Requirement**: After every single copy, wait until the flash finishes. The detailed single copy length and the way to check can be found below. Address of `flash_base` shall be two-bytes aligned. ## stm32f0.s -例外：`r2`:拷贝half word（2字节）数 +**Exception**: `r2` stores the total half word (2 bytes) count to be copied -特殊地址定义：`flash_base`:定义为0x40022000 +`flash_base`: 0x40022000 -`FLASH_CR`: 相对`flash_base`的offset为16 +`FLASH_CR`: offset from `flash_base` is 16 -`FLASH_SR`: 相对`flash_base`的offset为12 +`FLASH_SR`: offset from `flash_base` is 12 -参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f0.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f0.h) +**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f0.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f0.h) [https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) -特殊要求： -每次拷贝开始前需要读出FLASH_CR处的4字节内容，将其最低bit设置为1，写回FLASH_CR。 - -每次写入数据宽度为2字节（半字）。 - -每完成一次写入，需等待flash完成写入，检查方式为读取FLASH_SR处4字节内容，若取值为1，则说明写入尚未完成，需继续轮询等待；否则需要检查FLASH_SR处值是否为4，若非4，则应直接准备退出。 +**Special requirements**: -退出：全部拷贝执行完毕后触发断点前，将FLASH_CR处4字节内容最低bit清为0，写回FLASH_CR。 +Before every copy, read a word from FLASH_CR, set the lowest bit to 1 and write back. Copy one half word each time. +How to wait for the write process: read a word from FLASH_SR, loop until the content is not 1. After that, check FLASH_SR, proceed if the content is 4, otherwise exit. +Exit: after the copying process and before triggering the breakpoint, clear the lowest bit in FLASH_CR. ## stm32f4.s -特殊地址定义： `flash_base`：定义为0x40023c00 +`flash_base`: 0x40023c00 -`FLASH_SR`:相对flash_base的offset为0xe（14） +`FLASH_SR`: offset from `flash_base` is 0xe (14) -参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h) +**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h) [https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf](https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf) -特殊要求： -每次写入的数据宽度为4字节（字）。 +**Special requirements**: -每完成一次写入，需等待flash完成写入，检查方式为读取FLASH_SR处2字节内容，若取值为1，则说明写入尚未完成，需继续轮询等待。 +Copy one word each time. +How to wait for the write process: read a half word from FLASH_SR, loop until the content is not 1. ## stm32f4lv.s -特殊地址定义：`flash_base`：定义为0x40023c00 +`flash_base`: 0x40023c00 -`FLASH_SR`:相对`flash_base`的offset为0xe (14) +`FLASH_SR`: offset from `flash_base` is 0xe (14) -参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h) +**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h) [https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf](https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf) -特殊要求： +**Special Requirements**: -每次写入的数据宽度为1字节（1/4字）。 +Copy one byte each time. -每完成一次写入，需等待flash完成写入，检查方式为读取FLASH_SR处2字节内容，若取值为1，则说明写入尚未完成，需继续轮询等待。 +How to wait from the write process: read a half word from FLASH_SR, loop until the content is not 1. ## stm32f7.s -参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h) +**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h) [https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) -要求同stm32f4.s，额外要求在每次拷贝执行完毕、flash写入成功检测前，执行`dsb sy`指令以建立内存屏障。 - +Mostly same with `stm32f4.s`. Require establishing a memory barrier after every copy and before checking for finished writing by `dsb sy` ## stm32f7lv.s -参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h) +**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h) [https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) -要求基本同stm32f7.s，差异要求为每次写入的数据宽度为1字节（1/4字）。 -## stm32l0x.s +**Special Requirements**: -特殊要求： +Mostly same with `stm32f7.s`. Copy one byte each time. -每次写入的数据宽度为4字节（字） +## stm32l0x.s -无需实现检查flash写入完成功能 +**Special Requirements**: -## stm32l4.s +Copy one word each time. No wait for write. -例外：`r2`： 拷贝双字（8字节）数 +## stm32l4.s -特殊地址定义：`flash_base`: 0x40022000 +**Exception**: r2 stores the double word count to be copied. -`FLASH_BSY`：相对flash_base的offset为0x12 +`flash_base`: 0x40022000 +`FLASH_BSY`: offset from `flash_base` is 0x12 -参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32l4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32l4.h) +**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32l4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32l4.h) [https://www.st.com/resource/en/reference_manual/dm00310109-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00310109-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) -拷贝方式：一次性拷贝连续的8个字节（使用两个连续寄存器作中转）并写入 +**Special Requirements**: -每完成一次写入，需等待flash完成写入，检查方式为读取FLASH_BSY处半字（2字节），若其最低位非1，可继续拷贝。 +Copy one double word each time (More than one registers are allowed). + +How to wait for the write process: read a half word from `FLASH_BSY`, loop until the lowest bit turns non-1. ## stm32lx.s -要求与stm32l0x.s相同 +Same with stm32l0x.s. -# Clean Room Documentation English Version -Code is situated in section `.text` +# 净室工程文档-原始中文版 -Shall add a compile directive at the head: `.syntax unified` +代码位于的section：`.text` +编译制导添加`.syntax unified` -**Calling convention**: +传入参数约定： -All parameters would be passed over registers +参数全部通过寄存器传递 -`r0`: the base address of the copy source -`r1`: the base address of the copy destination -`r2`: the total word (4 bytes) count to be copied (with expeptions) +`r0`: 拷贝源点起始地址 +`r1`: 拷贝终点起始地址 +`r2`: 拷贝word（4字节）数(存在例外) -**What the program is expected to do**: +程序功能：将数据从源点拷贝到终点，在拷贝完毕后触发断点以结束执行，结束时`r2`值需清零表明传输完毕。 -Copy data from source to destination, after which trigger a breakpint to exit. Before exit, `r2` must be cleared to zero to indicate that the copy is done. +限制：不可使用栈，可自由使用的临时寄存器为`R3`到`R12`。`R13`为`sp`（stack pointer），`R14`为lr（一般用于储存跳转地址），`R15`为`pc`（program counter）。 -**Limitation**: No stack operations are permitted. Registers ranging from `r3` to `r12` are free to use. Note that `r13` is `sp`(stack pointer), `r14` is `lr`(commonly used to store jump address), `r15` is `pc`(program counter). +要求：每完成一次拷贝，需等待flash完成写入，单次拷贝宽度、检查写入完成的方式见每个文件的具体要求。 -**Requirement**: After every single copy, wait until the flash finishes. The detailed single copy length and the way to check can be found below. Address of `flash_base` shall be two-bytes aligned. +特殊地址`flash_base`存放地址需2字节对齐。 ## stm32f0.s -**Exception**: `r2` stores the total half word (2 bytes) count to be copied +例外：`r2`:拷贝half word（2字节）数 -`flash_base`: 0x40022000 +特殊地址定义：`flash_base`:定义为0x40022000 -`FLASH_CR`: offset from `flash_base` is 16 +`FLASH_CR`: 相对`flash_base`的offset为16 -`FLASH_SR`: offset from `flash_base` is 12 +`FLASH_SR`: 相对`flash_base`的offset为12 -**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f0.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f0.h) +参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f0.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f0.h) [https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) -**Special requirements**: +特殊要求： +每次拷贝开始前需要读出FLASH_CR处的4字节内容，将其最低bit设置为1，写回FLASH_CR。 -Before every copy, read a word from FLASH_CR, set the lowest bit to 1 and write back. Copy one half word each time. +每次写入数据宽度为2字节（半字）。 + +每完成一次写入，需等待flash完成写入，检查方式为读取FLASH_SR处4字节内容，若取值为1，则说明写入尚未完成，需继续轮询等待；否则需要检查FLASH_SR处值是否为4，若非4，则应直接准备退出。 + +退出：全部拷贝执行完毕后触发断点前，将FLASH_CR处4字节内容最低bit清为0，写回FLASH_CR。 -How to wait for the write process: read a word from FLASH_SR, loop until the content is not 1. After that, check FLASH_SR, proceed if the content is 4, otherwise exit. -Exit: after the copying process and before triggering the breakpoint, clear the lowest bit in FLASH_CR. ## stm32f4.s -`flash_base`: 0x40023c00 +特殊地址定义： `flash_base`：定义为0x40023c00 -`FLASH_SR`: offset from `flash_base` is 0xe (14) +`FLASH_SR`:相对flash_base的offset为0xe（14） -**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h) +参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h) [https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf](https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf) +特殊要求： -**Special requirements**: +每次写入的数据宽度为4字节（字）。 -Copy one word each time. -How to wait for the write process: read a half word from FLASH_SR, loop until the content is not 1. +每完成一次写入，需等待flash完成写入，检查方式为读取FLASH_SR处2字节内容，若取值为1，则说明写入尚未完成，需继续轮询等待。 ## stm32f4lv.s -`flash_base`: 0x40023c00 +特殊地址定义：`flash_base`：定义为0x40023c00 -`FLASH_SR`: offset from `flash_base` is 0xe (14) +`FLASH_SR`:相对`flash_base`的offset为0xe (14) -**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h) +参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f4.h) [https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf](https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf) -**Special Requirements**: +特殊要求： -Copy one byte each time. +每次写入的数据宽度为1字节（1/4字）。 -How to wait from the write process: read a half word from FLASH_SR, loop until the content is not 1. +每完成一次写入，需等待flash完成写入，检查方式为读取FLASH_SR处2字节内容，若取值为1，则说明写入尚未完成，需继续轮询等待。 ## stm32f7.s -**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h) +参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h) [https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) -Mostly same with `stm32f4.s`. Require establishing a memory barrier after every copy and before checking for finished writing by `dsb sy` +要求同stm32f4.s，额外要求在每次拷贝执行完毕、flash写入成功检测前，执行`dsb sy`指令以建立内存屏障。 + ## stm32f7lv.s -**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h) +参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32f7.h) [https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00124865-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) - -**Special Requirements**: - -Mostly same with `stm32f7.s`. Copy one byte each time. +要求基本同stm32f7.s，差异要求为每次写入的数据宽度为1字节（1/4字）。 ## stm32l0x.s -**Special Requirements**: +特殊要求： -Copy one word each time. No wait for write. +每次写入的数据宽度为4字节（字） + +无需实现检查flash写入完成功能 ## stm32l4.s -**Exception**: r2 stores the double word count to be copied. +例外：`r2`： 拷贝双字（8字节）数 -`flash_base`: 0x40022000 -`FLASH_BSY`: offset from `flash_base` is 0x12 +特殊地址定义：`flash_base`: 0x40022000 -**Reference**: [https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32l4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32l4.h) -[https://www.st.com/resource/en/reference_manual/dm00310109-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00310109-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) +`FLASH_BSY`：相对flash_base的offset为0x12 -**Special Requirements**: +参考：[https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32l4.h](https://chromium.googlesource.com/chromiumos/platform/ec/+/master/chip/stm32/registers-stm32l4.h) +[https://www.st.com/resource/en/reference_manual/dm00310109-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf](https://www.st.com/resource/en/reference_manual/dm00310109-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf) -Copy one double word each time (More than one registers are allowed). +拷贝方式：一次性拷贝连续的8个字节（使用两个连续寄存器作中转）并写入 -How to wait for the write process: read a half word from `FLASH_BSY`, loop until the lowest bit turns non-1. +每完成一次写入，需等待flash完成写入，检查方式为读取FLASH_BSY处半字（2字节），若其最低位非1，可继续拷贝。 ## stm32lx.s -Same with stm32l0x.s. \ No newline at end of file +要求与stm32l0x.s相同 \ No newline at end of file From e87bdff95b946ebfbfed7d5157d6e3bcd32e6f67 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 27 Apr 2020 20:20:50 +0200 Subject: [PATCH 0902/1435] General Project Update - Updated project README - Updated .gitignore - Updated project contributors - Added contribution guidelines --- .gitignore | 1 + .travis.yml | 12 ++++++++ CMakeLists.txt | 1 + CONTRIBUTING.md | 49 ++++++++++++++++++++++++++++++++ README.md | 16 +++++++---- cmake/packaging/debian/copyright | 2 +- 6 files changed, 74 insertions(+), 7 deletions(-) create mode 100644 CONTRIBUTING.md diff --git a/.gitignore b/.gitignore index 23e7ddc07..09b9b33de 100644 --- a/.gitignore +++ b/.gitignore @@ -2,3 +2,4 @@ build build-mingw obj-* *.user* +.project diff --git a/.travis.yml b/.travis.yml index b7ff93ff9..3e015dd07 100644 --- a/.travis.yml +++ b/.travis.yml @@ -4,6 +4,7 @@ matrix: include: ### 64-bit builds ### - os: linux + env: BADGE=linux arch: x64 compiler: gcc-5 addons: @@ -11,6 +12,7 @@ matrix: sources: ['ubuntu-toolchain-r-test'] packages: ['gcc-5', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux + env: BADGE=linux arch: x64 compiler: gcc-7 addons: @@ -18,6 +20,7 @@ matrix: sources: ['ubuntu-toolchain-r-test'] packages: ['gcc-7', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux + env: BADGE=linux arch: x64 compiler: gcc-9 addons: @@ -25,6 +28,7 @@ matrix: sources: ['ubuntu-toolchain-r-test'] packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux + env: BADGE=linux arch: x64 compiler: clang-3.7 addons: @@ -32,6 +36,7 @@ matrix: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-xenial-3.7'] packages: ['clang-3.7', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux + env: BADGE=linux arch: x64 compiler: clang-6.0 addons: @@ -49,6 +54,7 @@ matrix: ### 32-bit builds ### - os: linux + env: BADGE=linux arch: x86 compiler: gcc-5 addons: @@ -56,6 +62,7 @@ matrix: sources: ['ubuntu-toolchain-r-test'] packages: ['gcc-5', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux + env: BADGE=linux arch: x86 compiler: gcc-7 addons: @@ -63,6 +70,7 @@ matrix: sources: ['ubuntu-toolchain-r-test'] packages: ['gcc-7', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux + env: BADGE=linux arch: x86 compiler: gcc-9 addons: @@ -70,6 +78,7 @@ matrix: sources: ['ubuntu-toolchain-r-test'] packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux + env: BADGE=linux arch: x86 compiler: clang-3.7 addons: @@ -77,6 +86,7 @@ matrix: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-xenial-3.7'] packages: ['clang-3.7', 'libusb-1.0.0-dev', 'libgtk-3-dev'] - os: linux + env: BADGE=linux arch: x86 compiler: clang-6.0 addons: @@ -86,6 +96,7 @@ matrix: ### macOS ### - os: osx + env: BADGE=osx compiler: gcc addons: homebrew: @@ -94,6 +105,7 @@ matrix: - libusb - gtk+3 - os: osx + env: BADGE=osx compiler: clang addons: homebrew: diff --git a/CMakeLists.txt b/CMakeLists.txt index 95e27d215..b5301fb0a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -278,6 +278,7 @@ install(TARGETS st-flash DESTINATION bin) install(TARGETS st-info DESTINATION bin) install(TARGETS st-util DESTINATION bin) + ### # Additional build tasks ### diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md new file mode 100644 index 000000000..a9bb02661 --- /dev/null +++ b/CONTRIBUTING.md @@ -0,0 +1,49 @@ +# Contribution guidelines + +## Contributing to the stlink project +We love your input! We want to make contributing to this project as easy and transparent as possible, whether it's: + +- Reporting a bug +- Discussing the current state of the code +- Submitting a fix +- Proposing new features +- Assistance with maintaining + +We use GitHub to host code, to track issues and feature requests, as well as accept pull requests. +Report a bug by [opening a new issue]() with one of the available templates. It's that easy! + + +## Coding conventions +To read code written by other contributors can turn out to be quite demanding - a variable which seems to self-explaining, may appear cryptic to other readers. If you plan to contribute, please take this into account and feel encouraged to help others understand your code. In order to help you along, we have composed some contribution guidelines for this project. As this project already has a history you may find parts in the codebase that do not seem to comply with these guidelines, but we are trying to improve continuosly. However we can do even better, if every contributor considers the following points: + +* Naming of all source code elements as well as comments should exclusively be written in English. +* All functions and global variables should be fully explained. This includes a short description on _what_ the respective function does (but not necessarily _how_ this is achieved), an explantion of transfer parameters and/or return values (if applicable). +* Use [fixed width integer types](http://en.cppreference.com/w/c/types/integer) wherever possible and size-appropiate datatypes. +* Only make use of the datatype `char` for specific characters, otherwise use `int8_t` or `uint8_t` respectively. + + +### Coding Style +* Use 4 spaces for indentation rather than tabs (the latter results in inconsistent appearance on different platforms) +* Use `/* your comment */` formatting for multi-line comments or section titles and `// your comment` for inline comments. +* Please try to avoid special characters where possible, as they are interpreted differently on particular platforms and systems. Otherwise these may result in mojibake within the sourcecode or cause translation errors when compiling. +* Use state-of-the-art UTF-8 encoding whereever possible. + + +## Github Flow +We Use [Github Flow](https://guides.github.com/introduction/flow/index.html) which implies that all code changes happen through Pull Requests (PRs). +They are the best way to propose changes to the codebase and we actively welcome your own ones: + +1. PRs should focus on _one_ single topic. +2. Fork the repo and create your branch from `develop`. +3. Begin to implement your changes on a local or personal branch. +4. Take a look at existing PR and check if these target the same part of the codebase. + Should this be the case, you are encouraged to get in touch with the respective author and discuss on how to proceed. +5. Keep your personal feature-branch up to date with the current development branch, by merging in recent changes regularly. +6. Don't open a PR unless your contribution has evolved to a somehow completed set of changes. +7. If you've changed major features, update the documentation. +8. Ensure your PR passes our travis CI tests. +9. Issue that pull request! + + +## License +When you submit code changes, your submissions are understood to be under the same [BSD-3 License](LICENSE.md) that covers this project.
    Feel free to contact the project maintainers should there be any related questions. diff --git a/README.md b/README.md index 735712329..4bf663e34 100644 --- a/README.md +++ b/README.md @@ -3,10 +3,12 @@ Open source version of the STMicroelectronics STlink Tools [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) [![GitHub release](https://img.shields.io/github/release/stlink-org/stlink.svg)](https://github.com/stlink-org/stlink/releases/latest) -[![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.6.0.svg)](https://github.com/stlink-org/stlink/releases/develop) -[![Downloads](https://img.shields.io/github/downloads/stlink-org/stlink/total.svg)](https://github.com/stlink-org/stlink/releases) -[![Linux Status](https://img.shields.io/travis/stlink-org/stlink/master.svg?label=linux)](https://travis-ci.org/stlink-org/stlink) -[![macOS Status](https://img.shields.io/travis/stlink-org/stlink/master.svg?label=osx)](https://travis-ci.org/stlink-org/stlink) +[![Downloads](https://img.shields.io/github/downloads/stlink-org/stlink/total)](https://github.com/stlink-org/stlink/releases/latest) +![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.6.0/develop) +![GitHub activity](https://img.shields.io/github/commit-activity/m/stlink-org/stlink) +![GitHub contributors](https://img.shields.io/github/contributors/stlink-org/stlink) +[![Linux Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=linux&label=linux)](https://travis-ci.org/stlink-org/stlink) +[![macOS Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=osx&label=osx)](https://travis-ci.org/stlink-org/stlink) Recent new features and bugfixes can be found in the [Changelog](CHANGELOG.md) of this software project. @@ -104,8 +106,10 @@ When there is no executable available for your platform or you need the latest ( * The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) * Before creating a pull request, please _ALWAYS_ open a new issue for the discussion of the intended new features. Bugfixes don't require a discussion via a ticket-issue. However they should always be described in a few words as soon as they appear to help others as well. * Contributors and/or maintainers may submit comments or request changes to patch-proposals and/or pull-requests. -* **ATTENTION: _NEVER EVER_ use the '#' character to count-up single points within a listing as '#' is _exclusively_ reserved for referencing github issues and pull-requests. Otherwise you accidentally introduce false cross references within the project.** -* Please start new forks from the develop branch if possible as pull requests will go into this branch as well. +* **ATTENTION: _NEVER EVER_ use the '#' character to count-up single points within a listing as '#' is _exclusively_ reserved for referencing GitHub issues and pull-requests. Otherwise you accidentally introduce false cross references within the project.** +* Please start new forks from the develop branch, as pull requests will go into this branch as well. + +Please also refer to our [Contribution Guidelines](CONTRIBUTING.md). # Current state of the project diff --git a/cmake/packaging/debian/copyright b/cmake/packaging/debian/copyright index 4a7b110ae..4e58490f6 100644 --- a/cmake/packaging/debian/copyright +++ b/cmake/packaging/debian/copyright @@ -48,6 +48,7 @@ Copyright: 2011-2020 stlink-org Breton M. Saunders Bruno Dal Bo Burns Fisher + Cheng Guokai (Xim) [chenguokai] Chris Dew Chris Hiszpanski Chris Li @@ -153,5 +154,4 @@ Copyright: 2011-2020 stlink-org William Ransohoff [WRansohoff] Wojciech A. Koszek Woodrow Douglass - Xim [chenguokai] ... and others From 38a5c14877964e7ea272565b372576d61710790f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 27 Apr 2020 23:29:01 +0200 Subject: [PATCH 0903/1435] Updated CHANGELOG.md --- CHANGELOG.md | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 9ad6b6497..f79cd846c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -26,9 +26,10 @@ Features: Updates & changes: +- Define libusb version compatibility for supported operating systems via LIBUSB_API_VERSION (#211, #782, #895) - Improved argument parsing for CLI tools (#378, #922) - [doc] Updated tutorial: macOS ST-Link-v1 detection (#574, #587) -- Define libusb version compatibility for supported operating systems via LIBUSB_API_VERSION (#211, #782, #895) +- Enhanced output for error msg "addr not a multiple of pagesize, not supported" (#663, #945) - [doc] Verify correct udev configuration for device access (#764) - Added more error info to WLOGs during probe (#883) - Added check for libssp during compilation (#885) @@ -41,9 +42,15 @@ Updates & changes: - [doc] Defined version compatibility and installation instructions for macOS (commit 23c071edea45f6e8852fef52d884a680973d6d8f) - Deprecated old appveyor-mingw script (commit 97484422008df0f75c978627054776f35842a075) - Enhanced error log with file path for map_file() (#650, #879, #921) -- Refactoring: Overall option code rework (#927) -- Refactoring: Build settings / GUI-Build on UNIX-based systems if GTK3 is detected (#929) -- Reconfiguration of package build process (#931, #936, #940, commit 9b19f9225460472af9d98959b7217d0a840ee972) +- [refactoring] Overall option code rework (#927) +- [refactoring] Build settings / GUI-Build on UNIX-based systems if GTK3 is detected (#929) +- [refactoring] Reconfiguration of package build process (#931, #936, #940, commit 9b19f9225460472af9d98959b7217d0a840ee972) +- [refactoring] st-util: Removed now useless v1/v2 STLink version stuff (#934) +- [refactoring] Cleanup for option bytes and flash settings (#941) +- Added compilation guideline for MSVC toolchain (#942) +- st-util: Removal of useless v1/v2 stlink version stuff (#934) +- libusb package extraction no longer requires 7zip as an external unarchiver (commit 5db2dc4c0410ace65308cddcc03d1c0cfa4855cf) +- [refactoring] Cleanup of cmake build process (#944, #946, #947) Fixes: @@ -60,7 +67,7 @@ Fixes: - Fixed formatting for options display in st-flash & st-info (commits c783d0e777ccc83a7a8be26a4f4d3414e0478560 and 562cd2496e696dbd22950925866aac662d81ee5f) - Fixed dead loop after an unexpected unplug (#780, #812, #913) - Fixed broken build on 32-bit systems (#919, #920) -- st-flash: minor usage fix and make cmdline parsing more user friendly (#925) +- st-flash: Minor usage fix and make cmdline parsing more user friendly (#925) - Better argument parsing for CLI tools: stlink_open_usb can address v1, v2, v3 (#378, #922) - Restored functionality of make test builds (Regression) (#926, #929) - Fixed compilation error due to uninitialized cpuid (#937, #938) From ce6ffe70303cc75b663b91b0f2905821f3235a17 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 29 Apr 2020 16:24:14 +0200 Subject: [PATCH 0904/1435] Refactoring for package distribution - New cpack package-config for DEB and RPM - Toolchain file for cross-building - Script to automate MinGW cross-building - Added file headers for .cmake files - Added dpkg and rpm to required pkgs --- .travis.yml | 20 ++-- Makefile | 2 +- cmake/modules/Findlibusb.cmake | 25 +++-- cmake/modules/c_flags.cmake | 3 + cmake/modules/get_version.cmake | 8 +- cmake/modules/set_toolchain.cmake | 20 ++++ cmake/packaging/cpack_config.cmake | 108 +++++++++++-------- cmake/packaging/windows/generate_binaries.sh | 26 +++++ debian/.gitignore | 10 -- doc/compiling.md | 2 + 10 files changed, 148 insertions(+), 76 deletions(-) create mode 100644 cmake/modules/set_toolchain.cmake create mode 100644 cmake/packaging/windows/generate_binaries.sh delete mode 100644 debian/.gitignore diff --git a/.travis.yml b/.travis.yml index 3e015dd07..a66777f5f 100644 --- a/.travis.yml +++ b/.travis.yml @@ -10,7 +10,7 @@ matrix: addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-5', 'libusb-1.0.0-dev', 'libgtk-3-dev'] + packages: ['gcc-5', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - os: linux env: BADGE=linux arch: x64 @@ -18,7 +18,7 @@ matrix: addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-7', 'libusb-1.0.0-dev', 'libgtk-3-dev'] + packages: ['gcc-7', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - os: linux env: BADGE=linux arch: x64 @@ -26,7 +26,7 @@ matrix: addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev'] + packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - os: linux env: BADGE=linux arch: x64 @@ -34,7 +34,7 @@ matrix: addons: apt: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-xenial-3.7'] - packages: ['clang-3.7', 'libusb-1.0.0-dev', 'libgtk-3-dev'] + packages: ['clang-3.7', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - os: linux env: BADGE=linux arch: x64 @@ -42,7 +42,7 @@ matrix: addons: apt: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] - packages: ['clang-6.0', 'libusb-1.0.0-dev', 'libgtk-3-dev'] + packages: ['clang-6.0', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] # - os: linux # arch: x64 # compiler: clang-6.0 @@ -60,7 +60,7 @@ matrix: addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-5', 'libusb-1.0.0-dev', 'libgtk-3-dev'] + packages: ['gcc-5', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - os: linux env: BADGE=linux arch: x86 @@ -68,7 +68,7 @@ matrix: addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-7', 'libusb-1.0.0-dev', 'libgtk-3-dev'] + packages: ['gcc-7', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - os: linux env: BADGE=linux arch: x86 @@ -76,7 +76,7 @@ matrix: addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev'] + packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - os: linux env: BADGE=linux arch: x86 @@ -84,7 +84,7 @@ matrix: addons: apt: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-xenial-3.7'] - packages: ['clang-3.7', 'libusb-1.0.0-dev', 'libgtk-3-dev'] + packages: ['clang-3.7', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - os: linux env: BADGE=linux arch: x86 @@ -92,7 +92,7 @@ matrix: addons: apt: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] - packages: ['clang-6.0', 'libusb-1.0.0-dev', 'libgtk-3-dev'] + packages: ['clang-6.0', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] ### macOS ### - os: osx diff --git a/Makefile b/Makefile index 74a4fece5..7f373ebcd 100644 --- a/Makefile +++ b/Makefile @@ -45,7 +45,7 @@ package: build/Release @$(MAKE) -C build/Release package test: debug - @echo "[TEST]" + @echo "[TEST] Debug" @$(MAKE) -C build/Debug test build/Debug: diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index 898820033..bc613779d 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -1,4 +1,6 @@ # Findlibusb.cmake +# Find and install external libusb library + # Once done this will define # # LIBUSB_FOUND libusb present on system @@ -8,7 +10,7 @@ include(FindPackageHandleStandardArgs) -if (APPLE) # macOS +if (APPLE) # macOS FIND_PATH( LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr /usr/local /opt @@ -25,7 +27,7 @@ if (APPLE) # macOS message(FATAL_ERROR "No libusb library found on your system! Install libusb-1.0 from Homebrew or MacPorts") endif () -elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated into the system +elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated into the system FIND_PATH( LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr/include @@ -41,7 +43,7 @@ elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated message(FATAL_ERROR "Expected libusb library not found on your system! Verify your system integrity.") endif () -elseif (WIN32) # Windows +elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-toolchain on Debian # for MinGW/MSYS/MSVC: 64-bit or 32-bit? if (CMAKE_SIZEOF_VOID_P EQUAL 8) set(ARCH 64) @@ -49,7 +51,7 @@ elseif (WIN32) # Windows set(ARCH 32) endif () - if (NOT EXISTS "/etc/debian_version") + if (WIN32 AND NOT EXISTS "/etc/debian_version") # Skip this for Debian... FIND_PATH( LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr /usr/local /opt @@ -71,12 +73,17 @@ elseif (WIN32) # Windows endif () endif () - if (NOT LIBUSB_FOUND OR EXISTS "/etc/debian_version") + if (NOT LIBUSB_FOUND) # Preparations for installing libusb library set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) - set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) - set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/3rdparty/libusb-${LIBUSB_WIN_VERSION}) + if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems + set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) + set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/3rdparty/libusb-${LIBUSB_WIN_VERSION}) + else (EXISTS "/etc/debian_version" AND MINGW) # ... only for cross-building on Debian + set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_SOURCE_DIR}/build-mingw/${LIBUSB_WIN_ARCHIVE}) + set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_SOURCE_DIR}/build-mingw/3rdparty/libusb-${LIBUSB_WIN_VERSION}) + endif () # Get libusb package if (EXISTS ${LIBUSB_WIN_ARCHIVE_PATH}) # ... should the package be already there (for whatever reason) @@ -107,6 +114,7 @@ elseif (WIN32) # Windows ) if (MINGW OR MSYS) + set(LIBUSB_NAME usb-1.0) find_library( LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW${ARCH}/static @@ -115,6 +123,7 @@ elseif (WIN32) # Windows ) else (MSVC) + set(LIBUSB_NAME libusb-1.0.lib) find_library( LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS${ARCH}/dll @@ -127,7 +136,7 @@ elseif (WIN32) # Windows FIND_PACKAGE_HANDLE_STANDARD_ARGS(libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) -else () # all other OS (unix-based) +else () # all other OS (unix-based) FIND_PATH( LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr /usr/local /opt diff --git a/cmake/modules/c_flags.cmake b/cmake/modules/c_flags.cmake index d6b12403b..520182e37 100644 --- a/cmake/modules/c_flags.cmake +++ b/cmake/modules/c_flags.cmake @@ -1,3 +1,6 @@ +# c_flags.cmake +# Configure C compiler flags + include(CheckCCompilerFlag) function(add_cflag_if_supported flag) diff --git a/cmake/modules/get_version.cmake b/cmake/modules/get_version.cmake index da9d76eba..b80f0c9db 100644 --- a/cmake/modules/get_version.cmake +++ b/cmake/modules/get_version.cmake @@ -1,6 +1,5 @@ -# Determine project version -# * Using Git -# * Local .version file +# get_version.cmake +# Determine project version by using Git or a local .version file set(__detect_version 0) @@ -77,13 +76,14 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") endif(GIT_DESCRIBE_RESULT EQUAL 0) endif () +## # Failure to read version via git # Possible cases: # -> git is not found or # -> /.git does not exist or # -> GIT_DESCRIBE failed or # -> version string is of invalid format - +## if (NOT GIT_FOUND OR NOT EXISTS "${PROJECT_SOURCE_DIR}/.git" OR ERROR_FLAG EQUAL 1) message(STATUS "Git and/or repository not found.") # e.g. when building from source package message(STATUS "Try to detect version from \"${PROJECT_SOURCE_DIR}/.version\" file instead...") diff --git a/cmake/modules/set_toolchain.cmake b/cmake/modules/set_toolchain.cmake new file mode 100644 index 000000000..3c40e917e --- /dev/null +++ b/cmake/modules/set_toolchain.cmake @@ -0,0 +1,20 @@ +# set_toolchain.cmake +# Toolchain file for cross-building on a Debian/Ubuntu Linux system + +### +# Set toolchain and configure target environment on the build host system +### + +# Set cross compilers to use for C and C++ +set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}-gcc) +set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}-g++) +set(CMAKE_RC_COMPILER ${TOOLCHAIN_PREFIX}-windres) + +# Set path to directory with headers and libraries of the cross compiler +set(CMAKE_FIND_ROOT_PATH /usr/${TOOLCHAIN_PREFIX}) + +# Modify default behavior of FIND_XXX() commands to search for headers and libraries +# in the target environment and search for programs in the build host environment +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index 522fb7f11..c81362896 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -1,67 +1,68 @@ +# cpack_config.cmake +# Configure and generate packages for distribution + ### # Configure package ### set(CPACK_PACKAGE_NAME ${PROJECT_NAME}) set(CPACK_PACKAGE_VERSION ${PROJECT_VERSION}) +set(CPACK_PACKAGE_DESCRIPTION "Open source STM32 MCU programming toolset") +set(CPACK_PACKAGE_VENDOR "stlink-org") +set(CMAKE_PROJECT_HOMEPAGE_URL "https://github.com/stlink-org/stlink") + set(CPACK_SET_DESTDIR "ON") set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist") -if (APPLE) +if (APPLE) # macOS set(CPACK_GENERATOR "ZIP") set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-macosx-amd64") set(CPACK_INSTALL_PREFIX "") -elseif (WIN32) ### TODO: Binary build config for windows... + +elseif (WIN32 AND NOT EXISTS "/etc/debian_version") # Windows set(CPACK_GENERATOR "ZIP") set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-win32") set(CPACK_INSTALL_PREFIX "") - # Sample toolchain file for building for Windows from a Debian/Ubuntu Linux system. - # Typical usage: - # *) install cross compiler: `sudo apt-get install mingw-w64` - # *) cd build - # *) cmake -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw64.cmake .. - # *) cmake -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake .. - - #set(CMAKE_SYSTEM_NAME Windows) - #set(TOOLCHAIN_PREFIX x86_64-w64-mingw32) - #set(TOOLCHAIN_PREFIX i686-w64-mingw32) - - # cross compilers to use for C and C++ - #set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}-gcc) - #set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}-g++) - #set(CMAKE_RC_COMPILER ${TOOLCHAIN_PREFIX}-windres) - - # target environment on the build host system - # set 1st to dir with the cross compiler's C/C++ headers/libs - #set(CMAKE_FIND_ROOT_PATH /usr/${TOOLCHAIN_PREFIX}) - - # modify default behavior of FIND_XXX() commands to - # search for headers/libs in the target environment and - # search for programs in the build host environment - #set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) - #set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) - #set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) - -elseif (${CMAKE_SYSTEM_NAME} STREQUAL "Linux" AND EXISTS "/etc/debian_version") +elseif (WIN32) # Windows cross-build on Debian/Ubuntu + set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_SOURCE_DIR}/build/Release/dist") + set(CPACK_GENERATOR "ZIP") + set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-${TOOLCHAIN_PREFIX}") + set(CPACK_INSTALL_PREFIX "") + +elseif (EXISTS "/etc/debian_version") # Package-build is available on Debian/Ubuntu only message(STATUS "Debian-based Linux OS detected") - ### Debian-specific - set(CPACK_GENERATOR "DEB") - set(CPACK_DEBIAN_PACKAGE_DESCRIPTION "Open source STM32 MCU programming toolset") - set(CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/stlink-org/stlink") - set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Luca Boccassi") - set(CPACK_PACKAGE_CONTACT "bluca@debian.org") + set(CPACK_GENERATOR "DEB;RPM") # RPM requires package `rpm` - ## Set debian_revision number - # Convention: Restart the debian_revision at 1 each time the upstream_version is increased. - set(CPACK_DEBIAN_PACKAGE_RELEASE "0") + ### + # Debian (DEB) + ### + + # CPACK_DEB_PACKAGE_NAME --> Default: CPACK_PACKAGE_NAME - ## Debian package name + ## DEB package file name # CPack DEB generator generates package file name in deb format: # _-_.deb set(CPACK_DEBIAN_FILE_NAME DEB-DEFAULT) + # CPACK_DEBIAN_PACKAGE_VERSION --> Default: CPACK_PACKAGE_VERSION + + ## Set debian_revision number + # Convention: Restart the debian_revision at 1 each time the upstream_version is increased. + set(CPACK_DEBIAN_PACKAGE_RELEASE "1") + + # CPACK_DEBIAN_PACKAGE_ARCHITECTURE --> Default: Output of dpkg --print-architecture + set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.4.2), libusb-1.0-0-dev (>= 1.0.20)") + set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Luca Boccassi ") + # CPACK_DEBIAN_PACKAGE_DESCRIPTION --> Default: CPACK_DEBIAN_PACKAGE_DESCRIPTION (as it is set) + # CPACK_DEBIAN_PACKAGE_SECTION --> Default: “devel” + # CPACK_DEBIAN_ARCHIVE_TYPE --> Default: “gnutar” + # CPACK_DEBIAN_COMPRESSION_TYPE --> Default: “gzip” + # CPACK_DEBIAN_PACKAGE_PRIORITY --> Default: “optional” + # CPACK_DEBIAN_PACKAGE_HOMEPAGE --> Default: CMAKE_PROJECT_HOMEPAGE_URL + set(CPACK_DEBIAN_PACKAGE_SUGGESTS "libgtk-3-dev, pandoc") + ## Add CHANGELOG in Debian-specific format ### TODO @@ -71,15 +72,36 @@ elseif (${CMAKE_SYSTEM_NAME} STREQUAL "Linux" AND EXISTS "/etc/debian_version") # Include a postinst-script set(CPACK_DEBIAN_PACKAGE_CONTROL_EXTRA "${CMAKE_SOURCE_DIR}/cmake/packaging/debian/postinst") - ### rpm-specific ### TODO: Package config for opensuse should go here... + ### + # Slackware & Redhat (RPM) + ### + + # CPACK_RPM_PACKAGE_SUMMARY --> Default: CPACK_PACKAGE_DESCRIPTION_SUMMARY + # CPACK_RPM_PACKAGE_NAME --> Default: CPACK_PACKAGE_NAME + + ## RPM package file name + # Allow rpmbuild to generate package file name + set(CPACK_RPM_FILE_NAME RPM-DEFAULT) + + # CPACK_RPM_PACKAGE_VERSION --> Default: CPACK_PACKAGE_VERSION + # CPACK_RPM_PACKAGE_ARCHITECTURE --> Default: Native architecture output by uname -m + + ## Set rpm revision number + # Convention: Restart the debian_revision at 1 each time the upstream_version is increased. + set(CPACK_RPM_PACKAGE_RELEASE "1") + set(CPACK_RPM_PACKAGE_LICENSE "BSD-3") + # CPACK_RPM_PACKAGE_GROUP --> Default: “unknown” (RPM Groups are deprecated on Fedora) + # CPACK_RPM_PACKAGE_VENDOR --> Default: CPACK_PACKAGE_VENDOR (as it is set) + # CPACK_RPM_PACKAGE_URL --> Default: CMAKE_PROJECT_HOMEPAGE_URL + set(CPACK_RPM_PACKAGE_DESCRIPTION CPACK_DEBIAN_PACKAGE_DESCRIPTION) else () - ### TODO: Package config for fedora should go here... + # No package configuration on other platforms ... endif () ### -# Build package +# Build packages ### include(CPack) diff --git a/cmake/packaging/windows/generate_binaries.sh b/cmake/packaging/windows/generate_binaries.sh new file mode 100644 index 000000000..ba5b965f5 --- /dev/null +++ b/cmake/packaging/windows/generate_binaries.sh @@ -0,0 +1,26 @@ +### +# Build package with binaries for Windows +### + +# Install this cross-compiler toolchain: +#sudo apt-get install mingw-w64 + +# x86_64 +mkdir build-mingw +cd build-mingw +cmake -DCMAKE_SYSTEM_NAME=Windows \ + -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ + -DCMAKE_TOOLCHAIN_FILE=./cmake/modules/set_toolchain.cmake .. +make package +cd .. +rm -rf build-mingw + +# i686 +mkdir build-mingw +cd build-mingw +cmake -DCMAKE_SYSTEM_NAME=Windows \ + -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ + -DCMAKE_TOOLCHAIN_FILE=./cmake/modules/set_toolchain.cmake .. +make package +cd .. +rm -rf build-mingw diff --git a/debian/.gitignore b/debian/.gitignore deleted file mode 100644 index 7624d1c9b..000000000 --- a/debian/.gitignore +++ /dev/null @@ -1,10 +0,0 @@ -.debhelper -files -debhelper-build-stamp -*.log -*.substvars -libstlink-dev -libstlink -stlink-gui -stlink-tools -tmp diff --git a/doc/compiling.md b/doc/compiling.md index 65d2510d0..3c8b78d73 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -87,6 +87,8 @@ Install the following packages from your package repository: * `gcc` or `clang` or `mingw32-gcc` or `mingw64-gcc` (C-compiler; very likely gcc is already present) * `build-essential` (on Debian based distros (debian, ubuntu)) * `cmake` (3.4.2 or later, use the latest version available from the repository) +* `dpkg` +* `rpm` * `pkg-config` * `libusb-1.0` * `libusb-1.0-0-dev` (development headers for building) From 06a5d716b82b2e897c1c54682866c1dbef55e848 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Wed, 29 Apr 2020 22:40:06 +0800 Subject: [PATCH 0905/1435] Remove all 'my' in tag name --- flashloaders/linker.ld | 2 +- flashloaders/stm32f0.s | 12 ++++++------ flashloaders/stm32f4.s | 10 +++++----- flashloaders/stm32f4lv.s | 10 +++++----- flashloaders/stm32f7.s | 10 +++++----- flashloaders/stm32f7lv.s | 10 +++++----- flashloaders/stm32l0x.s | 10 +++++----- flashloaders/stm32l4.s | 10 +++++----- flashloaders/stm32lx.s | 10 +++++----- src/flash_loader.c | 2 ++ 10 files changed, 44 insertions(+), 42 deletions(-) diff --git a/flashloaders/linker.ld b/flashloaders/linker.ld index 5bc738966..4d06433ea 100644 --- a/flashloaders/linker.ld +++ b/flashloaders/linker.ld @@ -1,5 +1,5 @@ /*. Entry Point *./ -ENTRY( mycopy ) +ENTRY( copy ) /*. Specify the memory areas .*/ diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s index 3dd0ae6e8..6c4b8588f 100644 --- a/flashloaders/stm32f0.s +++ b/flashloaders/stm32f0.s @@ -1,8 +1,8 @@ .syntax unified .text - .global mycopy -mycopy: + .global copy +copy: ldr r7, =flash_base ldr r4, [r7] ldr r7, =flash_off_cr @@ -12,7 +12,7 @@ mycopy: ldr r5, [r7] adds r5, r5, r4 -myloop: +loop: # FLASH_CR ^= 1 ldr r7, =0x1 ldr r3, [r6] @@ -37,15 +37,15 @@ mywait: # exit if FLASH_SR != 4 ldr r7, =0x4 tst r3, r7 - bne myexit + bne exit # loop if r2 != 0 ldr r7, =0x1 subs r2, r2, r7 cmp r2, #0 - bne myloop + bne loop -myexit: +exit: # FLASH_CR &= ~1 ldr r7, =0x1 ldr r3, [r6] diff --git a/flashloaders/stm32f4.s b/flashloaders/stm32f4.s index 836f6e1f2..b4e0f4913 100644 --- a/flashloaders/stm32f4.s +++ b/flashloaders/stm32f4.s @@ -1,13 +1,13 @@ .syntax unified .text - .global mycopy -mycopy: + .global copy +copy: ldr r12, flash_base ldr r10, flash_off_sr add r10, r10, r12 -myloop: +loop: # copy 4 bytes ldr r3, [r0] str r3, [r1] @@ -24,9 +24,9 @@ mywait: # loop if r2 != 0 sub r2, r2, #1 cmp r2, #0 - bne myloop + bne loop -myexit: +exit: bkpt .align 2 diff --git a/flashloaders/stm32f4lv.s b/flashloaders/stm32f4lv.s index 4ba351faa..f5cc29841 100644 --- a/flashloaders/stm32f4lv.s +++ b/flashloaders/stm32f4lv.s @@ -1,8 +1,8 @@ .syntax unified .text - .global mycopy -mycopy: + .global copy +copy: ldr r12, flash_base ldr r10, flash_off_sr add r10, r10, r12 @@ -13,7 +13,7 @@ mycopy: # tip 2: r2 is always a power of 2 mov r2, r2, lsl#2 -myloop: +loop: # copy 1 byte ldrb r3, [r0] strb r3, [r1] @@ -30,9 +30,9 @@ mywait: # loop if r2 != 0 sub r2, r2, #1 cmp r2, #0 - bne myloop + bne loop -myexit: +exit: bkpt .align 2 diff --git a/flashloaders/stm32f7.s b/flashloaders/stm32f7.s index 3f02e75f8..8694d864e 100644 --- a/flashloaders/stm32f7.s +++ b/flashloaders/stm32f7.s @@ -1,13 +1,13 @@ .syntax unified .text - .global mycopy -mycopy: + .global copy +copy: ldr r12, flash_base ldr r10, flash_off_sr add r10, r10, r12 -myloop: +loop: # copy 4 bytes ldr r3, [r0] str r3, [r1] @@ -27,9 +27,9 @@ mywait: # loop if r2 != 0 sub r2, r2, #1 cmp r2, #0 - bne myloop + bne loop -myexit: +exit: bkpt .align 2 diff --git a/flashloaders/stm32f7lv.s b/flashloaders/stm32f7lv.s index d82726eeb..b48e40f0d 100644 --- a/flashloaders/stm32f7lv.s +++ b/flashloaders/stm32f7lv.s @@ -1,8 +1,8 @@ .syntax unified .text - .global mycopy -mycopy: + .global copy +copy: ldr r12, flash_base ldr r10, flash_off_sr add r10, r10, r12 @@ -13,7 +13,7 @@ mycopy: # tip 2: r2 is always a power of 2 mov r2, r2, lsl#2 -myloop: +loop: # copy 1 byte ldrb r3, [r0] strb r3, [r1] @@ -33,9 +33,9 @@ mywait: # loop if r2 != 0 sub r2, r2, #1 cmp r2, #0 - bne myloop + bne loop -myexit: +exit: bkpt .align 2 diff --git a/flashloaders/stm32l0x.s b/flashloaders/stm32l0x.s index 893aa6f9b..f9c257e2e 100644 --- a/flashloaders/stm32l0x.s +++ b/flashloaders/stm32l0x.s @@ -1,9 +1,9 @@ .syntax unified .text - .global mycopy -mycopy: -myloop: + .global copy +copy: +loop: # copy 4 bytes ldr r3, [r0] str r3, [r1] @@ -16,7 +16,7 @@ myloop: ldr r7, =1 subs r2, r2, r7 cmp r2, #0 - bne myloop + bne loop -myexit: +exit: bkpt diff --git a/flashloaders/stm32l4.s b/flashloaders/stm32l4.s index 16c6d1063..c68198bfa 100644 --- a/flashloaders/stm32l4.s +++ b/flashloaders/stm32l4.s @@ -1,13 +1,13 @@ .syntax unified .text - .global mycopy -mycopy: + .global copy +copy: ldr r12, flash_base ldr r10, flash_off_bsy add r10, r10, r12 -myloop: +loop: # copy 8 bytes ldr r3, [r0] ldr r4, [r0, #4] @@ -26,9 +26,9 @@ mywait: # loop if r2 != 0 sub r2, r2, #1 cmp r2, #0 - bne myloop + bne loop -myexit: +exit: bkpt .align 2 diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s index 893aa6f9b..f9c257e2e 100644 --- a/flashloaders/stm32lx.s +++ b/flashloaders/stm32lx.s @@ -1,9 +1,9 @@ .syntax unified .text - .global mycopy -mycopy: -myloop: + .global copy +copy: +loop: # copy 4 bytes ldr r3, [r0] str r3, [r1] @@ -16,7 +16,7 @@ myloop: ldr r7, =1 subs r2, r2, r7 cmp r2, #0 - bne myloop + bne loop -myexit: +exit: bkpt diff --git a/src/flash_loader.c b/src/flash_loader.c index a3fd2cefd..80f5c262c 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -7,6 +7,8 @@ #define FLASH_REGS_BANK2_OFS 0x40 #define FLASH_BANK2_START_ADDR 0x08080000 +/* DO NOT MODIFY SOURCECODE DIRECTLY, EDIT ASSEMBLY FILES INSTEAD */ + /* flashloaders/stm32f0.s -- compiled with thumb2 */ static const uint8_t loader_code_stm32vl[] = { 0x16, 0x4f, 0x3c, 0x68, From 1f9724e8216ecc8205dffde900767f39659ce0db Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 29 Apr 2020 17:08:41 +0200 Subject: [PATCH 0906/1435] Removed deprecated debian pkg config settings --- {debian => cmake/packaging/debian}/rules | 0 debian/compat | 1 - debian/control | 53 ---------- debian/gbp.conf | 7 -- debian/libstlink-dev.install | 4 - debian/libstlink1.install | 1 - debian/libstlink1.symbols | 125 ----------------------- debian/source/format | 1 - debian/stlink-gui.install | 4 - debian/stlink-tools.install | 3 - debian/stlink-tools.manpages | 1 - debian/watch | 3 - 12 files changed, 203 deletions(-) rename {debian => cmake/packaging/debian}/rules (100%) delete mode 100644 debian/compat delete mode 100644 debian/control delete mode 100644 debian/gbp.conf delete mode 100644 debian/libstlink-dev.install delete mode 100644 debian/libstlink1.install delete mode 100644 debian/libstlink1.symbols delete mode 100644 debian/source/format delete mode 100644 debian/stlink-gui.install delete mode 100644 debian/stlink-tools.install delete mode 100644 debian/stlink-tools.manpages delete mode 100644 debian/watch diff --git a/debian/rules b/cmake/packaging/debian/rules similarity index 100% rename from debian/rules rename to cmake/packaging/debian/rules diff --git a/debian/compat b/debian/compat deleted file mode 100644 index ec635144f..000000000 --- a/debian/compat +++ /dev/null @@ -1 +0,0 @@ -9 diff --git a/debian/control b/debian/control deleted file mode 100644 index 3c1e9700f..000000000 --- a/debian/control +++ /dev/null @@ -1,53 +0,0 @@ -Source: stlink -Priority: optional -Maintainer: Luca Bocassi -Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev -Standards-Version: 4.1.3 -Section: electronics -Homepage: https://github.com/stlink-org/stlink -Vcs-Git: https://github.com/stlink-org/stlink.git -Vcs-Browser: https://github.com/stlink-org/stlink - -Package: libstlink-dev -Section: libdevel -Architecture: any -Depends: libstlink1 (= ${binary:Version}), ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. - . - This package contains the development files for stlink. - -Package: libstlink1 -Section: libs -Architecture: any -Depends: ${shlibs:Depends}, ${misc:Depends} -Breaks: libstlink -Replaces: libstlink -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. - . - This package contains the shared library for stlink. - -Package: stlink-tools -Architecture: any -Depends: libstlink1 (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} -Breaks: libstlink -Replaces: libstlink -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. - . - This package contains commandline utilities for stlink, and modprobe and - udev rules. - -Package: stlink-gui -Architecture: any -Depends: libstlink1 (= ${binary:Version}), stlink-tools (= ${binary:Version}), - ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. - . - This package contains a GUI tool for stlink. diff --git a/debian/gbp.conf b/debian/gbp.conf deleted file mode 100644 index 418e536e9..000000000 --- a/debian/gbp.conf +++ /dev/null @@ -1,7 +0,0 @@ -[buildpackage] -upstream-tag = %(version)s -debian-branch = debian - -[dch] -git-log = --first-parent -customizations = /usr/share/doc/git-buildpackage/examples/wrap_cl.py diff --git a/debian/libstlink-dev.install b/debian/libstlink-dev.install deleted file mode 100644 index 18fd98b03..000000000 --- a/debian/libstlink-dev.install +++ /dev/null @@ -1,4 +0,0 @@ -usr/include/* -usr/lib/*/lib*.a -usr/lib/*/pkg-config/* -usr/lib/*/lib*.so diff --git a/debian/libstlink1.install b/debian/libstlink1.install deleted file mode 100644 index 3ddde5841..000000000 --- a/debian/libstlink1.install +++ /dev/null @@ -1 +0,0 @@ -usr/lib/*/lib*.so.* diff --git a/debian/libstlink1.symbols b/debian/libstlink1.symbols deleted file mode 100644 index 51fa9bdb1..000000000 --- a/debian/libstlink1.symbols +++ /dev/null @@ -1,125 +0,0 @@ -libstlink.so.1 libstlink1 #MINVER# - _parse_version@Base 1.5.0 - _stlink_sg_close@Base 1.5.0 - _stlink_sg_core_id@Base 1.5.0 - _stlink_sg_current_mode@Base 1.5.0 - _stlink_sg_enter_jtag_mode@Base 1.5.0 - _stlink_sg_enter_swd_mode@Base 1.5.0 - _stlink_sg_exit_debug_mode@Base 1.5.0 - _stlink_sg_exit_dfu_mode@Base 1.5.0 - _stlink_sg_force_debug@Base 1.5.0 - _stlink_sg_jtag_reset@Base 1.5.0 - _stlink_sg_read_all_regs@Base 1.5.0 - _stlink_sg_read_debug32@Base 1.5.0 - _stlink_sg_read_mem32@Base 1.5.0 - _stlink_sg_read_reg@Base 1.5.0 - _stlink_sg_reset@Base 1.5.0 - _stlink_sg_run@Base 1.5.0 - _stlink_sg_status@Base 1.5.0 - _stlink_sg_step@Base 1.5.0 - _stlink_sg_version@Base 1.5.0 - _stlink_sg_write_debug32@Base 1.5.0 - _stlink_sg_write_mem32@Base 1.5.0 - _stlink_sg_write_mem8@Base 1.5.0 - _stlink_sg_write_reg@Base 1.5.0 - _stlink_usb_close@Base 1.5.0 - _stlink_usb_core_id@Base 1.5.0 - _stlink_usb_current_mode@Base 1.5.0 - _stlink_usb_enter_swd_mode@Base 1.5.0 - _stlink_usb_exit_debug_mode@Base 1.5.0 - _stlink_usb_exit_dfu_mode@Base 1.5.0 - _stlink_usb_force_debug@Base 1.5.0 - _stlink_usb_jtag_reset@Base 1.5.0 - _stlink_usb_read_all_regs@Base 1.5.0 - _stlink_usb_read_all_unsupported_regs@Base 1.5.0 - _stlink_usb_read_debug32@Base 1.5.0 - _stlink_usb_read_mem32@Base 1.5.0 - _stlink_usb_read_reg@Base 1.5.0 - _stlink_usb_read_unsupported_reg@Base 1.5.0 - _stlink_usb_reset@Base 1.5.0 - _stlink_usb_run@Base 1.5.0 - _stlink_usb_set_swdclk@Base 1.5.0 - _stlink_usb_status@Base 1.5.0 - _stlink_usb_step@Base 1.5.0 - _stlink_usb_target_voltage@Base 1.5.0 - _stlink_usb_version@Base 1.5.0 - _stlink_usb_write_debug32@Base 1.5.0 - _stlink_usb_write_mem32@Base 1.5.0 - _stlink_usb_write_mem8@Base 1.5.0 - _stlink_usb_write_reg@Base 1.5.0 - _stlink_usb_write_unsupported_reg@Base 1.5.0 - calculate_F4_sectornum@Base 1.5.0 - calculate_F7_sectornum@Base 1.5.0 - calculate_L4_page@Base 1.5.0 - is_bigendian@Base 1.5.0 - read_uint16@Base 1.5.0 - read_uint32@Base 1.5.0 - send_recv@Base 1.5.0 - send_usb_data_only@Base 1.5.0 - send_usb_mass_storage_command@Base 1.5.0 - stlink_calculate_pagesize@Base 1.5.0 - stlink_chip_id@Base 1.5.0 - stlink_chipid_get_params@Base 1.5.0 - stlink_close@Base 1.5.0 - stlink_clr_hw_bp@Base 1.5.0 - stlink_core_id@Base 1.5.0 - stlink_core_stat@Base 1.5.0 - stlink_cpu_id@Base 1.5.0 - stlink_current_mode@Base 1.5.0 - stlink_enter_swd_mode@Base 1.5.0 - stlink_erase_flash_mass@Base 1.5.0 - stlink_erase_flash_page@Base 1.5.0 - stlink_exit_debug_mode@Base 1.5.0 - stlink_exit_dfu_mode@Base 1.5.0 - stlink_fcheck_flash@Base 1.5.0 - stlink_flash_loader_init@Base 1.5.0 - stlink_flash_loader_run@Base 1.5.0 - stlink_flash_loader_write_to_sram@Base 1.5.0 - stlink_force_debug@Base 1.5.0 - stlink_fread@Base 1.5.0 - stlink_fwrite_flash@Base 1.5.0 - stlink_fwrite_sram@Base 1.5.0 - stlink_get_erased_pattern@Base 1.5.0 - stlink_is_core_halted@Base 1.5.0 - stlink_jtag_reset@Base 1.5.0 - stlink_load_device_params@Base 1.5.0 - stlink_mwrite_flash@Base 1.5.0 - stlink_mwrite_sram@Base 1.5.0 - stlink_open_usb@Base 1.5.0 - stlink_parse_ihex@Base 1.5.0 - stlink_print_data@Base 1.5.0 - stlink_probe_usb@Base 1.5.0 - stlink_probe_usb_free@Base 1.5.0 - stlink_q@Base 1.5.0 - stlink_read_all_regs@Base 1.5.0 - stlink_read_all_unsupported_regs@Base 1.5.0 - stlink_read_debug32@Base 1.5.0 - stlink_read_mem32@Base 1.5.0 - stlink_read_reg@Base 1.5.0 - stlink_read_unsupported_reg@Base 1.5.0 - stlink_reset@Base 1.5.0 - stlink_run@Base 1.5.0 - stlink_run_at@Base 1.5.0 - stlink_set_hw_bp@Base 1.5.0 - stlink_set_swdclk@Base 1.5.0 - stlink_stat@Base 1.5.0 - stlink_status@Base 1.5.0 - stlink_step@Base 1.5.0 - stlink_target_voltage@Base 1.5.0 - stlink_v1_open@Base 1.5.0 - stlink_v1_open_inner@Base 1.5.0 - stlink_verify_write_flash@Base 1.5.0 - stlink_version@Base 1.5.0 - stlink_write_debug32@Base 1.5.0 - stlink_write_dreg@Base 1.5.0 - stlink_write_flash@Base 1.5.0 - stlink_write_mem32@Base 1.5.0 - stlink_write_mem8@Base 1.5.0 - stlink_write_reg@Base 1.5.0 - stlink_write_unsupported_reg@Base 1.5.0 - stm32l1_write_half_pages@Base 1.5.0 - ugly_init@Base 1.5.0 - ugly_log@Base 1.5.0 - write_buffer_to_sram@Base 1.5.0 - write_uint16@Base 1.5.0 - write_uint32@Base 1.5.0 diff --git a/debian/source/format b/debian/source/format deleted file mode 100644 index 89ae9db8f..000000000 --- a/debian/source/format +++ /dev/null @@ -1 +0,0 @@ -3.0 (native) diff --git a/debian/stlink-gui.install b/debian/stlink-gui.install deleted file mode 100644 index b419ac054..000000000 --- a/debian/stlink-gui.install +++ /dev/null @@ -1,4 +0,0 @@ -/usr/bin/stlink-gui* -/usr/share/stlink/stlink-gui.ui -/usr/share/applications/stlink-gui.desktop -/usr/share/icons/hicolor/scalable/apps/stlink-gui.svg diff --git a/debian/stlink-tools.install b/debian/stlink-tools.install deleted file mode 100644 index ca875a0e6..000000000 --- a/debian/stlink-tools.install +++ /dev/null @@ -1,3 +0,0 @@ -/usr/bin/st-* -lib/udev/rules.d/*.rules -etc/modprobe.d/*.conf diff --git a/debian/stlink-tools.manpages b/debian/stlink-tools.manpages deleted file mode 100644 index 6a461c09e..000000000 --- a/debian/stlink-tools.manpages +++ /dev/null @@ -1 +0,0 @@ -doc/man/st-*.1 diff --git a/debian/watch b/debian/watch deleted file mode 100644 index 20ad1260e..000000000 --- a/debian/watch +++ /dev/null @@ -1,3 +0,0 @@ -version=3 -opts=filenamemangle=s/.+\/v?(\d\S+)\.tar\.gz/-$1\.tar\.gz/ \ - https://github.com/stlink-org/stlink/tags .*/v?(\d\S+)\.tar\.gz From 9b478a04e0d105f037cda2c29617409dc1f55a36 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 29 Apr 2020 19:20:47 +0200 Subject: [PATCH 0907/1435] Simplified subdir structure for packaging --- cmake/packaging/CMakeLists.txt | 5 ++--- cmake/packaging/{debian => deb}/CMakeLists.txt | 0 cmake/packaging/{debian => deb}/changelog | 0 cmake/packaging/{debian => deb}/copyright | 0 cmake/packaging/{debian => deb}/postinst | 0 cmake/packaging/{debian => deb}/rules | 0 cmake/packaging/opensuse/CMakeLists.txt | 0 cmake/packaging/{fedora => rpm}/CMakeLists.txt | 0 doc/compiling.md | 5 ++--- 9 files changed, 4 insertions(+), 6 deletions(-) rename cmake/packaging/{debian => deb}/CMakeLists.txt (100%) rename cmake/packaging/{debian => deb}/changelog (100%) rename cmake/packaging/{debian => deb}/copyright (100%) rename cmake/packaging/{debian => deb}/postinst (100%) rename cmake/packaging/{debian => deb}/rules (100%) delete mode 100644 cmake/packaging/opensuse/CMakeLists.txt rename cmake/packaging/{fedora => rpm}/CMakeLists.txt (100%) diff --git a/cmake/packaging/CMakeLists.txt b/cmake/packaging/CMakeLists.txt index 431c85d2d..1cf640552 100644 --- a/cmake/packaging/CMakeLists.txt +++ b/cmake/packaging/CMakeLists.txt @@ -1,6 +1,5 @@ -add_subdirectory(debian) -add_subdirectory(fedora) -add_subdirectory(opensuse) +add_subdirectory(deb) +add_subdirectory(rpm) add_subdirectory(windows) include(cpack_config.cmake) diff --git a/cmake/packaging/debian/CMakeLists.txt b/cmake/packaging/deb/CMakeLists.txt similarity index 100% rename from cmake/packaging/debian/CMakeLists.txt rename to cmake/packaging/deb/CMakeLists.txt diff --git a/cmake/packaging/debian/changelog b/cmake/packaging/deb/changelog similarity index 100% rename from cmake/packaging/debian/changelog rename to cmake/packaging/deb/changelog diff --git a/cmake/packaging/debian/copyright b/cmake/packaging/deb/copyright similarity index 100% rename from cmake/packaging/debian/copyright rename to cmake/packaging/deb/copyright diff --git a/cmake/packaging/debian/postinst b/cmake/packaging/deb/postinst similarity index 100% rename from cmake/packaging/debian/postinst rename to cmake/packaging/deb/postinst diff --git a/cmake/packaging/debian/rules b/cmake/packaging/deb/rules similarity index 100% rename from cmake/packaging/debian/rules rename to cmake/packaging/deb/rules diff --git a/cmake/packaging/opensuse/CMakeLists.txt b/cmake/packaging/opensuse/CMakeLists.txt deleted file mode 100644 index e69de29bb..000000000 diff --git a/cmake/packaging/fedora/CMakeLists.txt b/cmake/packaging/rpm/CMakeLists.txt similarity index 100% rename from cmake/packaging/fedora/CMakeLists.txt rename to cmake/packaging/rpm/CMakeLists.txt diff --git a/doc/compiling.md b/doc/compiling.md index 3c8b78d73..e20cbca83 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -85,10 +85,9 @@ Install the following packages from your package repository: * `git` * `gcc` or `clang` or `mingw32-gcc` or `mingw64-gcc` (C-compiler; very likely gcc is already present) -* `build-essential` (on Debian based distros (debian, ubuntu)) +* `build-essential` (on Debian based distros (Debian, Ubuntu)) * `cmake` (3.4.2 or later, use the latest version available from the repository) -* `dpkg` -* `rpm` +* `rpm` (on Debian based distros (Debian, Ubuntu), needed for package build with `make package`) * `pkg-config` * `libusb-1.0` * `libusb-1.0-0-dev` (development headers for building) From e952bcdb339cb0e65dc3af65d559a1a304152dab Mon Sep 17 00:00:00 2001 From: Rafael Lee Date: Wed, 29 Apr 2020 01:16:06 +0800 Subject: [PATCH 0908/1435] Add function to get number from char* like 0xff, 12, 1k, 1M, 0b1001 --- src/tools/flash_opts.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index 544d4ad90..f635fa04c 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -11,6 +11,45 @@ static bool starts_with(const char * str, const char * prefix) { return (0 == strncmp(str, prefix, n)); } +// support positive integer from 0 to 0x7fffffff +// support decimal, hexadecimal, octal, binary format like 0xff 12 1k 1M, 0b1001 +// negative numbers are not supported +static int32_t get_integer_from_char_array (const char * const str) { + int32_t value; + char *tail; + + // hexadecimal + if ((strncmp ("0x", str, 2) == 0) || (strncmp ("0X", str, 2) == 0)) { + value = strtoul (str + 2, &tail, 16); + } + // binary + else if ((strncmp ("0b", str, 2) == 0) || (strncmp ("0B", str, 2) == 0)) { + value = strtoul (str + 2, &tail, 2); + } + // octal + else if ((strncmp ("0", str, 1) == 0) || (strncmp ("0", str, 1) == 0)) { + value = strtoul (str + 1, &tail, 8); + } + // decimal + else { + value = strtoul (str, &tail, 10); + } + + if (((tail[0] == 'k') || (tail[0] == 'K')) && (tail[1] == '\0')) { + return value * 1024; + } + else if (((tail[0] == 'm') || (tail[0] == 'M')) && (tail[1] == '\0')) { + return value * 1024 * 1024; + } + else if (tail[0] == '\0') { + return value; + } + else { + return -1; + } + return value; +} + static int invalid_args(const char *expected) { fprintf(stderr, "*** Error: Expected args for this command: %s\n", expected); return -1; @@ -22,6 +61,7 @@ static int bad_arg(const char *arg) { } int flash_get_opts(struct flash_opts* o, int ac, char** av) { + bool serial_specified = false; // defaults memset(o, 0, sizeof(*o)); From 9fdcc0cc3d1bc47734f28082496e1123409411d7 Mon Sep 17 00:00:00 2001 From: Rafael Lee Date: Wed, 29 Apr 2020 02:11:24 +0800 Subject: [PATCH 0909/1435] Modify strtoul with only one encoding to more user friendly interface --- src/tools/flash_opts.c | 49 +++++++++++++++++------------------------- 1 file changed, 20 insertions(+), 29 deletions(-) diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index f635fa04c..781188905 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -61,7 +61,6 @@ static int bad_arg(const char *arg) { } int flash_get_opts(struct flash_opts* o, int ac, char** av) { - bool serial_specified = false; // defaults memset(o, 0, sizeof(*o)); @@ -146,26 +145,10 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } else if ( starts_with(av[0], "--flash=") ) { const char *arg = av[0] + strlen("--flash="); - char *ep = 0; - - o->flash_size = (uint32_t)strtoul(arg,&ep,0); - while ( *ep ) { - switch ( *ep++ ) { - case 0: - break; - case 'k': - case 'K': - o->flash_size *= 1024u; - break; - case 'm': - case 'M': - o->flash_size *= 1024u * 1024u; - break; - default: - fprintf(stderr,"Invalid --flash=%s\n",arg); - return -1; - } - } + + int32_t flash_size = get_integer_from_char_array(arg); + if (flash_size < 0) return bad_arg("--flash"); + else o->flash_size = (size_t) flash_size; } else { break; // non-option found @@ -201,7 +184,6 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { av++; } - char * tail; switch(o->cmd) { case FLASH_CMD_NONE: // no command found return -1; @@ -215,22 +197,31 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { if (ac != 3) return invalid_args("read "); if (ac != 3) return -1; o->filename = av[0]; - o->addr = (uint32_t) strtoul(av[1], &tail, 16); - if (tail[0] != '\0') return bad_arg("addr"); - o->size = strtoul(av[2], &tail, 16); - if (tail[0] != '\0') return bad_arg("size"); + int32_t address = get_integer_from_char_array(av[1]); + if(address < 0) return bad_arg("addr"); + else o->addr = (stm32_addr_t) address; + + int32_t size = get_integer_from_char_array(av[2]); + if(size < 0) return bad_arg("size"); + else o->size = (size_t) size; + break; case FLASH_CMD_WRITE: if (o->area == FLASH_OPTION_BYTES){ if (ac != 1) return -1; - o->val = (uint32_t)strtoul(av[0], &tail, 16); + + int32_t val = get_integer_from_char_array(av[0]); + if(val < 0) return bad_arg("val"); + else o->val = (uint32_t) val; + } else if (o->format == FLASH_FORMAT_BINARY) { // expect filename and addr if (ac != 2) return invalid_args("write "); o->filename = av[0]; - o->addr = (uint32_t) strtoul(av[1], &tail, 16); - if (tail[0] != '\0') return bad_arg("addr"); + int32_t addr = get_integer_from_char_array(av[1]); + if(addr < 0) return bad_arg("addr"); + else o->addr = (stm32_addr_t) addr; } else if (o->format == FLASH_FORMAT_IHEX) { // expect filename if (ac != 1) return invalid_args("write "); From af8807bc3dffb6e4f536fe942d33e65dddf2a55f Mon Sep 17 00:00:00 2001 From: Rafael Lee Date: Thu, 30 Apr 2020 01:37:12 +0800 Subject: [PATCH 0910/1435] Add range checking in converting string to integer --- src/tools/flash_opts.c | 40 +++++++++++++++++++++++++++++++++------- 1 file changed, 33 insertions(+), 7 deletions(-) diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index 781188905..5baea2a9d 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -11,11 +11,12 @@ static bool starts_with(const char * str, const char * prefix) { return (0 == strncmp(str, prefix, n)); } -// support positive integer from 0 to 0x7fffffff +// support positive integer from 0 to INT64_MAX +// INT64_MAX+1 to UINT64_MAX are not supported // support decimal, hexadecimal, octal, binary format like 0xff 12 1k 1M, 0b1001 // negative numbers are not supported -static int32_t get_integer_from_char_array (const char * const str) { - int32_t value; +static int64_t get_long_integer_from_char_array (const char * const str) { + uint64_t value; char *tail; // hexadecimal @@ -36,18 +37,43 @@ static int32_t get_integer_from_char_array (const char * const str) { } if (((tail[0] == 'k') || (tail[0] == 'K')) && (tail[1] == '\0')) { - return value * 1024; + value = value * 1024; } else if (((tail[0] == 'm') || (tail[0] == 'M')) && (tail[1] == '\0')) { - return value * 1024 * 1024; + value = value * 1024 * 1024; } else if (tail[0] == '\0') { - return value; + // value not change } else { return -1; } - return value; + if (value >= INT64_MAX) { + fprintf (stderr, "*** Error: Integer greater than INT64_MAX\n"); + return -1l; + } + else { + return (int64_t)value; + } +} + +// support positive integer from 0 to INT32_MAX +// INT32_MAX+1 to UINT32_MAX are not supported +// support decimal, hexadecimal, octal, binary format like 0xff 12 1k 1M, 0b1001 +// negative numbers are not supported +static int32_t get_integer_from_char_array (const char * const str) { + int64_t v = get_long_integer_from_char_array (str); + if (v < 0) { + return (int32_t)v; + } + else if (v >= INT32_MAX) { + fprintf(stderr, "*** Error: Integer greater than INT32_MAX, \ +cannot convert to int32_t\n"); + return -1; + } + else { + return (int32_t)v; + } } static int invalid_args(const char *expected) { From 2f50899fb8bd03dece4b66382d46e84da613d6cc Mon Sep 17 00:00:00 2001 From: Rafael Lee Date: Fri, 1 May 2020 02:09:12 +0800 Subject: [PATCH 0911/1435] Modify get_integer_from_char_array to support unsigned integer --- src/tools/flash_opts.c | 35 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index 5baea2a9d..d3a39299b 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -11,11 +11,11 @@ static bool starts_with(const char * str, const char * prefix) { return (0 == strncmp(str, prefix, n)); } -// support positive integer from 0 to INT64_MAX -// INT64_MAX+1 to UINT64_MAX are not supported +// support positive integer from 0 to UINT64_MAX // support decimal, hexadecimal, octal, binary format like 0xff 12 1k 1M, 0b1001 // negative numbers are not supported -static int64_t get_long_integer_from_char_array (const char * const str) { +// return 0 if success else return -1 +static int get_long_integer_from_char_array (const char *const str, uint64_t *read_value) { uint64_t value; char *tail; @@ -48,31 +48,28 @@ static int64_t get_long_integer_from_char_array (const char * const str) { else { return -1; } - if (value >= INT64_MAX) { - fprintf (stderr, "*** Error: Integer greater than INT64_MAX\n"); - return -1l; - } - else { - return (int64_t)value; - } + *read_value = value; + return 0; } -// support positive integer from 0 to INT32_MAX -// INT32_MAX+1 to UINT32_MAX are not supported +// support positive integer from 0 to UINT32_MAX // support decimal, hexadecimal, octal, binary format like 0xff 12 1k 1M, 0b1001 // negative numbers are not supported -static int32_t get_integer_from_char_array (const char * const str) { - int64_t v = get_long_integer_from_char_array (str); - if (v < 0) { - return (int32_t)v; +// return 0 if success else return -1 +static int get_integer_from_char_array (const char *const str, uint32_t *read_value) { + uint64_t value; + int result = get_long_integer_from_char_array (str, &value); + if (result != 0) { + return result; } - else if (v >= INT32_MAX) { - fprintf(stderr, "*** Error: Integer greater than INT32_MAX, \ + else if (value > UINT32_MAX) { + fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, \ cannot convert to int32_t\n"); return -1; } else { - return (int32_t)v; + *read_value = value; + return 0; } } From fc964c81d0b34a6cbc391251397162f0f43c6772 Mon Sep 17 00:00:00 2001 From: Rafael Lee Date: Fri, 1 May 2020 02:10:44 +0800 Subject: [PATCH 0912/1435] Modify function calls --- src/tools/flash_opts.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index d3a39299b..f83956e45 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -90,6 +90,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { o->log_level = STND_LOG_LEVEL; // options + int result; while (ac >= 1) { if (strcmp(av[0], "--version") == 0) { printf("v%s\n", STLINK_VERSION); @@ -169,8 +170,9 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { else if ( starts_with(av[0], "--flash=") ) { const char *arg = av[0] + strlen("--flash="); - int32_t flash_size = get_integer_from_char_array(arg); - if (flash_size < 0) return bad_arg("--flash"); + uint32_t flash_size; + result = get_integer_from_char_array(arg, &flash_size); + if (result != 0) return bad_arg ("--flash"); else o->flash_size = (size_t) flash_size; } else { @@ -220,12 +222,14 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { if (ac != 3) return invalid_args("read "); if (ac != 3) return -1; o->filename = av[0]; - int32_t address = get_integer_from_char_array(av[1]); - if(address < 0) return bad_arg("addr"); + uint32_t address; + result = get_integer_from_char_array(av[1], &address); + if (result != 0) return bad_arg ("addr"); else o->addr = (stm32_addr_t) address; - int32_t size = get_integer_from_char_array(av[2]); - if(size < 0) return bad_arg("size"); + uint32_t size; + result = get_integer_from_char_array(av[2], &size); + if (result != 0) return bad_arg ("size"); else o->size = (size_t) size; break; @@ -234,16 +238,18 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { if (o->area == FLASH_OPTION_BYTES){ if (ac != 1) return -1; - int32_t val = get_integer_from_char_array(av[0]); - if(val < 0) return bad_arg("val"); + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) return bad_arg ("val"); else o->val = (uint32_t) val; } else if (o->format == FLASH_FORMAT_BINARY) { // expect filename and addr if (ac != 2) return invalid_args("write "); o->filename = av[0]; - int32_t addr = get_integer_from_char_array(av[1]); - if(addr < 0) return bad_arg("addr"); + uint32_t addr; + result = get_integer_from_char_array(av[1], &addr); + if (result != 0) return bad_arg ("addr"); else o->addr = (stm32_addr_t) addr; } else if (o->format == FLASH_FORMAT_IHEX) { // expect filename From 0f1bf6e3410200a351aa5d9b000cbf7354b2ddd9 Mon Sep 17 00:00:00 2001 From: Rafael Lee Date: Fri, 1 May 2020 02:24:52 +0800 Subject: [PATCH 0913/1435] Add test cases for new syntax --- tests/flash.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/tests/flash.c b/tests/flash.c index 903370cc3..96a43a2c3 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -95,16 +95,36 @@ static struct Test tests[] = { .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, - { "--debug --reset read test.bin 0x80000000 0x1000", 0, + { "--debug --reset read test.bin 0x80000000 1000", 0, { .cmd = FLASH_CMD_READ, .serial = { 0 }, .filename = "test.bin", .addr = 0x80000000, - .size = 0x1000, + .size = 1000, .reset = 1, .log_level = DEBUG_LOG_LEVEL, .format = FLASH_FORMAT_BINARY } }, + { "--debug --reset read test.bin 0x80000000 1k", 0, + { .cmd = FLASH_CMD_READ, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 1024, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .format = FLASH_FORMAT_BINARY } + }, + { "--debug --reset read test.bin 0x80000000 1M", 0, + { .cmd = FLASH_CMD_READ, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 1048576, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .format = FLASH_FORMAT_BINARY } + }, { "--debug --reset write test.bin 0x80000000", 0, { .cmd = FLASH_CMD_WRITE, .serial = { 0 }, From f160c5ef3b74bdf5f6ad1a751dffaa68daad414a Mon Sep 17 00:00:00 2001 From: Rafael Lee Date: Fri, 1 May 2020 02:34:42 +0800 Subject: [PATCH 0914/1435] Modify strncmp to starts_with --- src/tools/flash_opts.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index f83956e45..147f56366 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -20,15 +20,15 @@ static int get_long_integer_from_char_array (const char *const str, uint64_t *re char *tail; // hexadecimal - if ((strncmp ("0x", str, 2) == 0) || (strncmp ("0X", str, 2) == 0)) { + if (starts_with (str, "0x") || starts_with (str, "0X")) { value = strtoul (str + 2, &tail, 16); } // binary - else if ((strncmp ("0b", str, 2) == 0) || (strncmp ("0B", str, 2) == 0)) { + else if (starts_with (str, "0b") || starts_with (str, "0B")) { value = strtoul (str + 2, &tail, 2); } // octal - else if ((strncmp ("0", str, 1) == 0) || (strncmp ("0", str, 1) == 0)) { + else if (starts_with (str, "0")) { value = strtoul (str + 1, &tail, 8); } // decimal From cb777ce57654f187f235c70a95d347d6c8b9c3b8 Mon Sep 17 00:00:00 2001 From: Rafael Lee Date: Fri, 1 May 2020 09:49:55 +0800 Subject: [PATCH 0915/1435] Fix CI, cast variable explicitly --- src/tools/flash_opts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index 147f56366..044527a8b 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -68,7 +68,7 @@ cannot convert to int32_t\n"); return -1; } else { - *read_value = value; + *read_value = (uint32_t)value; return 0; } } From 2ad60ff0718b6886f4a2b59452ca5d7a84f2bbd5 Mon Sep 17 00:00:00 2001 From: Paul Gallagher Date: Sat, 2 May 2020 15:41:27 +0800 Subject: [PATCH 0916/1435] Fix: tutorial.md should be correctly linked from readme --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 4bf663e34..12052a7a8 100644 --- a/README.md +++ b/README.md @@ -59,7 +59,7 @@ Supported operating systems are listed in [version_support.md](doc/version_suppo ## Tutorial & HOWTO -Our [tutorial.md](doc/tutorial.md may help you along with some advanced tasks and additional info. +Our [tutorial.md](doc/tutorial.md) may help you along with some advanced tasks and additional info. ## Installation From 5e0e29984c562bf42f1c7edb04bb0e4d1030950a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 6 May 2020 19:48:21 +0200 Subject: [PATCH 0917/1435] Updated travis CI test-builds - Added builds for clang -m32 on arch: AMD64 - Corrected invalid config settings - Added clang-9 builds for linux - Moved scripts to root directory - Added MinGW cross-test-build for linux --- .travis.sh | 95 ++++++++++++------- .travis.yml | 87 ++++++++++------- doc/version_support.md | 4 +- .../mingw64-build.bat => mingw64-build.bat | 4 +- ...n_clang_analyze.sh => run_clang_analyze.sh | 0 5 files changed, 117 insertions(+), 73 deletions(-) rename scripts/mingw64-build.bat => mingw64-build.bat (91%) rename scripts/run_clang_analyze.sh => run_clang_analyze.sh (100%) diff --git a/.travis.sh b/.travis.sh index 5291ec95b..e61098f89 100755 --- a/.travis.sh +++ b/.travis.sh @@ -8,39 +8,64 @@ echo "----" echo "WORK DIR:$DIR" DIR=$PWD -if [ "$TRAVIS_OS_NAME" == "linux" ]; then - sudo apt-get update -qq || true - sudo apt-get install -qq -y --no-install-recommends libgtk-3-dev - - echo "--> Building Debug..." - mkdir -p build/Debug && cd build/Debug - echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install" - cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ - make && make package && cd - - - echo "--> Building Release..." - mkdir -p build/Release && cd build/Release - echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install" - cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ - make && make package && cd - - -# echo "--> Building Binary..." -# mkdir -p build/Binary && cd build/Binary -# cho "-DCMAKE_BUILD_TYPE=Binary -DCMAKE_INSTALL_PREFIX=$PWD/_install" -# cmake -DCMAKE_BUILD_TYPE=Binary -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ -# make && make package && cd - -else [ "$TRAVIS_OS_NAME" == "osx" ]; - brew install libusb - - echo "--> Building Debug..." - mkdir -p build/Debug && cd build/Debug - echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install" - cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ - make && make package && cd - - - echo "--> Building Release..." - mkdir -p build/Release && cd build/Release - echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install" - cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ - make && make package && cd - +if [ "$TRAVIS_JOB_NAME" == "linux-mingw" ]; then + echo "--> Building Release for Windows (x86-64) ..." + mkdir -p build-mingw && cd build-mingw + echo "-DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ + -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR" + cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ + -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR + make && rm -rf build-mingw && cd - + + echo "--> Building Release for Windows (i686) ..." + mkdir -p build-mingw && cd build-mingw + echo "-DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ + -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR" + cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ + -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR + make && rm -rf build-mingw && cd - + +elif [ "$TRAVIS_OS_NAME" == "linux" ]; then + sudo apt-get update -qq || true + sudo apt-get install -qq -y --no-install-recommends libgtk-3-dev + + echo "--> Building Debug..." + mkdir -p build/Debug && cd build/Debug + echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install" + cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR + make && make package && cd - + + echo "--> Building Release..." + mkdir -p build/Release && cd build/Release + echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install" + cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR + make && make package && cd - + +elif [ "$TRAVIS_OS_NAME" == "osx" ]; then + brew install libusb + + echo "--> Building Debug..." + mkdir -p build/Debug && cd build/Debug + echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install" + cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR + make && make package && cd - + + echo "--> Building Release..." + mkdir -p build/Release && cd build/Release + echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install" + cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR + make && make package && cd - + +else # local test-build + echo "--> Building Debug..." + mkdir -p build/Debug && cd build/Debug + echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install" + cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ + make && make package && cd - + + echo "--> Building Release..." + mkdir -p build/Release && cd build/Release + echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install" + cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ + make && make package && cd - fi diff --git a/.travis.yml b/.travis.yml index a66777f5f..17db35765 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,98 +1,111 @@ language: c -matrix: +jobs: include: - ### 64-bit builds ### + ### 64-bit builds on AMD64 ### - os: linux + dist: bionic env: BADGE=linux - arch: x64 compiler: gcc-5 addons: apt: sources: ['ubuntu-toolchain-r-test'] packages: ['gcc-5', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - os: linux + dist: bionic env: BADGE=linux - arch: x64 - compiler: gcc-7 - addons: - apt: - sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-7', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - - os: linux - env: BADGE=linux - arch: x64 compiler: gcc-9 addons: apt: sources: ['ubuntu-toolchain-r-test'] packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - os: linux + dist: xenial env: BADGE=linux - arch: x64 compiler: clang-3.7 addons: apt: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-xenial-3.7'] packages: ['clang-3.7', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - os: linux + dist: bionic env: BADGE=linux - arch: x64 compiler: clang-6.0 addons: apt: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] packages: ['clang-6.0', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] -# - os: linux -# arch: x64 -# compiler: clang-6.0 -# addons: -# apt: -# sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] -# packages: ['clang-6.0', 'libusb-1.0.0-dev', 'libgtk-3-dev'] -# env: CFLAGS=-m32 LDFLAGS=-m32 - - ### 32-bit builds ### - os: linux + dist: bionic env: BADGE=linux - arch: x86 - compiler: gcc-5 + compiler: clang-9 addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-5', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] + packages: ['clang-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] + + - os: linux + dist: bionic + env: BADGE=linux-mingw + name: linux-mingw + compiler: gcc-9 + addons: + apt: + sources: ['ubuntu-toolchain-r-test'] + packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm', 'mingw-w64'] + + ### 32-bit builds on AMD64 ### - os: linux + dist: bionic env: BADGE=linux - arch: x86 - compiler: gcc-7 + compiler: gcc-5 addons: apt: sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-7', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] + packages: ['gcc-5', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - os: linux + dist: bionic env: BADGE=linux - arch: x86 compiler: gcc-9 addons: apt: sources: ['ubuntu-toolchain-r-test'] packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - os: linux + dist: xenial env: BADGE=linux - arch: x86 compiler: clang-3.7 addons: apt: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-xenial-3.7'] packages: ['clang-3.7', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - os: linux + dist: bionic env: BADGE=linux - arch: x86 compiler: clang-6.0 addons: apt: sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] packages: ['clang-6.0', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + - os: linux + dist: bionic + env: BADGE=linux + compiler: clang-9 + addons: + apt: + sources: ['ubuntu-toolchain-r-test'] + packages: ['clang-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + ### macOS ### - os: osx @@ -114,8 +127,14 @@ matrix: - libusb - gtk+3 + ### Windows ### +# - os: windows +# env: BADGE=windows +# compiler: gcc + script: - git fetch --tags - printenv - cmake --version - - ./.travis.sh + - if [[ "$TRAVIS_OS_NAME" == "linux" ]] || [[ "$TRAVIS_OS_NAME" == "osx" ]]; then ./.travis.sh; fi +# - if [[ "$TRAVIS_OS_NAME" == "windows" ]]; then cmd.exe /C 'mingw64-build.bat'; fi diff --git a/doc/version_support.md b/doc/version_support.md index 75def2e66..f889fbc32 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -68,10 +68,10 @@ Thus no user interaction regarding libusb is necessary. | Operating System | libusb
    version | cmake
    version | End of OS-Support | Notes | | --- | --- | --- | --- | --- | -| CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but `libusb`-codebase is used | +| CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but
    `libusb`-codebase is used | | Debian 8 (Jessie) | 1.0.**19** | 3.**0.2** | Jun 2020 | | Ubuntu 14.04 LTS (Trusty Tahr) | 1.0.**17** | **2.8.12.2** | Apr 2019 | -| CentOS 6 | 1.0.**9** | **2.8.12.2** | Dec 2020 | named `libusbx`, but `libusb`-codebase is used | +| CentOS 6 | 1.0.**9** | **2.8.12.2** | Dec 2020 | named `libusbx`, but
    `libusb`-codebase is used | | Slackware 14.1 | 1.0.**9** | **2.8.12** | | | Slackware 14.0 | 1.0.**9** | **2.8.8** | | diff --git a/scripts/mingw64-build.bat b/mingw64-build.bat similarity index 91% rename from scripts/mingw64-build.bat rename to mingw64-build.bat index 15ec21cd0..9d5cf4d06 100644 --- a/scripts/mingw64-build.bat +++ b/mingw64-build.bat @@ -1,5 +1,5 @@ -@echo off -cd .. +@echo on + mkdir build-mingw cd build-mingw set PATH=C:\Program Files (x86)\CMake\bin;C:\Program Files\CMake\bin;C:\Program Files\mingw-w64\x86_64-8.1.0-win32-sjlj-rt_v6-rev0\mingw64\bin;%PATH% diff --git a/scripts/run_clang_analyze.sh b/run_clang_analyze.sh similarity index 100% rename from scripts/run_clang_analyze.sh rename to run_clang_analyze.sh From e11b077da3aba4470f0a66815d262100e2ff630c Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Thu, 7 May 2020 18:16:07 +0800 Subject: [PATCH 0918/1435] Fix https://github.com/stlink-org/stlink/issues/893 * Add --freq argument for st-flash --- include/stlink.h | 2 ++ include/stlink/tools/flash.h | 3 +- src/st-util/gdb-server.c | 4 +-- src/stlink-gui/gui.c | 2 +- src/tools/flash.c | 8 +++--- src/tools/flash_opts.c | 50 +++++++++++++++++++++++++++++++++ src/tools/info.c | 2 +- src/usb.c | 47 +++++++++++++++++++++++++++++-- src/usb.h | 2 +- tests/flash.c | 54 ++++++++++++++++++++++++++++++++++++ tests/usb.c | 2 +- 11 files changed, 162 insertions(+), 14 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index 74c366d1c..ffa65b332 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -159,6 +159,8 @@ typedef struct flash_loader { char serial[STLINK_SERIAL_MAX_SIZE]; int serial_size; + int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR + enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx bool has_dual_bank; diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index 8c3f7d766..b8954af65 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -26,9 +26,10 @@ struct flash_opts uint32_t val; size_t flash_size; /* --flash=n[k][m] */ int opt; + int freq; }; -#define FLASH_OPTS_INITIALIZER {0, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0} +#define FLASH_OPTS_INITIALIZER {0, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} int flash_get_opts(struct flash_opts* o, int ac, char** av); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index a3839cfc8..20954821b 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -87,9 +87,9 @@ static void cleanup(int signum) { static stlink_t* do_connect(st_state_t *st) { stlink_t *sl = NULL; if (serial_specified) { - sl = stlink_open_usb(st->logging_level, st->reset, serialnumber); + sl = stlink_open_usb(st->logging_level, st->reset, serialnumber, 0); } else { - sl = stlink_open_usb(st->logging_level, st->reset, NULL); + sl = stlink_open_usb(st->logging_level, st->reset, NULL, 0); } return sl; } diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index 5d5a422d5..6e9d59b1e 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -490,7 +490,7 @@ static void connect_button_cb (GtkWidget *widget, gpointer data) { /* try version 1 then version 2 */ gui->sl = stlink_v1_open(0, 1); if (gui->sl == NULL) - gui->sl = stlink_open_usb(0, 1, NULL); + gui->sl = stlink_open_usb(0, 1, NULL, 0); if (gui->sl == NULL) { stlink_gui_set_info_error_message (gui, "Failed to connect to STLink."); return; diff --git a/src/tools/flash.c b/src/tools/flash.c index 841b93c3c..3a83daf8a 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -28,9 +28,9 @@ static void cleanup(int signum) { static void usage(void) { - puts("command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] {read|write} [addr] [size]"); - puts("command line: ./st-flash [--debug] [--serial ] erase"); - puts("command line: ./st-flash [--debug] [--serial ] reset"); + puts("command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] {read|write} [addr] [size]"); + puts("command line: ./st-flash [--debug] [--freq=] [--serial ] erase"); + puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); puts(" , and : Use hex format."); puts(" : Use decimal, octal or hex (prefix 0xXXX) format, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); puts(" : Can be 'binary' (default) or 'ihex', although must be specified for binary format only."); @@ -56,7 +56,7 @@ int main(int ac, char** av) printf("st-flash %s\n", STLINK_VERSION); - sl = stlink_open_usb(o.log_level, 1, (char *)o.serial); + sl = stlink_open_usb(o.log_level, 1, (char *)o.serial, o.freq); if (sl == NULL) { return -1; diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index 044527a8b..a5c9d287f 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -149,6 +149,56 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { return -1; } + else if (strcmp(av[0], "--freq") == 0 || starts_with(av[0], "--freq=")) { + const char* freq; + if (strcmp(av[0], "--freq") == 0) { + ac--; + av++; + if (ac < 1) return -1; + freq = av[0]; + } + else { + freq = av[0] + strlen("--freq="); + } + if (strcmp(freq, "5K") == 0 || strcmp(freq, "5k") == 0) { + o->freq = 5; + } + else if (strcmp(freq, "15K") == 0 || strcmp(freq, "15k") == 0) { + o->freq = 15; + } + else if (strcmp(freq, "25K") == 0 || strcmp(freq, "25k") == 0) { + o->freq = 25; + } + else if (strcmp(freq, "50K") == 0 || strcmp(freq, "50k") == 0) { + o->freq = 50; + } + else if (strcmp(freq, "100K") == 0 || strcmp(freq, "100k") == 0) { + o->freq = 100; + } + else if (strcmp(freq, "125K") == 0 || strcmp(freq, "125k") == 0) { + o->freq = 125; + } + else if (strcmp(freq, "240K") == 0 || strcmp(freq, "240k") == 0) { + o->freq = 240; + } + else if (strcmp(freq, "480K") == 0 || strcmp(freq, "480k") == 0) { + o->freq = 480; + } + else if (strcmp(freq, "950K") == 0 || strcmp(freq, "950k") == 0) { + o->freq = 950; + } + else if (strcmp(freq, "1200K") == 0 || strcmp(freq, "1200k") == 0 || strcmp(freq, "1.2M") == 0 || strcmp(freq, "1.2m") == 0) { + o->freq = 1200; + } + else if (strcmp(freq, "1800K") == 0 || strcmp(freq, "1800k") == 0 || strcmp(freq, "1.8M") == 0 || strcmp(freq, "1.8m") == 0) { + o->freq = 1800; + } + else if (strcmp(freq, "4000K") == 0 || strcmp(freq, "4000k") == 0 || strcmp(freq, "4M") == 0 || strcmp(freq, "4m") == 0) { + o->freq = 4000; + } + else + return -1; + } else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { const char * format; if (strcmp(av[0], "--format") == 0) { diff --git a/src/tools/info.c b/src/tools/info.c index 3ebbba8de..45d484270 100644 --- a/src/tools/info.c +++ b/src/tools/info.c @@ -81,7 +81,7 @@ static stlink_t *stlink_open_first(void) stlink_t* sl = NULL; sl = stlink_v1_open(0, 1); if (sl == NULL) - sl = stlink_open_usb(0, 1, NULL); + sl = stlink_open_usb(0, 1, NULL, 0); return sl; } diff --git a/src/usb.c b/src/usb.c index 4e7a2983f..ef3743c78 100644 --- a/src/usb.c +++ b/src/usb.c @@ -873,7 +873,7 @@ static stlink_backend_t _stlink_usb_backend = { _stlink_usb_set_swdclk }; -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[STLINK_SERIAL_MAX_SIZE]) +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; @@ -1041,10 +1041,51 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST stlink_exit_dfu_mode(sl); } + + sl->opt = freq; // set the speed before entering the mode // as the chip discovery phase should be done at this speed too // Set the stlink clock speed (default is 1800kHz) - stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); + DLOG("JTAG/SWD freq set to %d\n", freq); + switch (freq) { + case 5: + stlink_set_swdclk(sl, STLINK_SWDCLK_5KHZ_DIVISOR); + break; + case 15: + stlink_set_swdclk(sl, STLINK_SWDCLK_15KHZ_DIVISOR); + break; + case 25: + stlink_set_swdclk(sl, STLINK_SWDCLK_25KHZ_DIVISOR); + break; + case 50: + stlink_set_swdclk(sl, STLINK_SWDCLK_50KHZ_DIVISOR); + break; + case 100: + stlink_set_swdclk(sl, STLINK_SWDCLK_100KHZ_DIVISOR); + break; + case 125: + stlink_set_swdclk(sl, STLINK_SWDCLK_125KHZ_DIVISOR); + break; + case 240: + stlink_set_swdclk(sl, STLINK_SWDCLK_240KHZ_DIVISOR); + break; + case 480: + stlink_set_swdclk(sl, STLINK_SWDCLK_480KHZ_DIVISOR); + break; + case 950: + stlink_set_swdclk(sl, STLINK_SWDCLK_950KHZ_DIVISOR); + break; + case 1200: + stlink_set_swdclk(sl, STLINK_SWDCLK_1P2MHZ_DIVISOR); + break; + case 0: case 1800: + stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); + break; + case 4000: + stlink_set_swdclk(sl, STLINK_SWDCLK_4MHZ_DIVISOR); + break; + } + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); @@ -1147,7 +1188,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { continue; } - stlink_t *sl = stlink_open_usb(0, 1, serial); + stlink_t *sl = stlink_open_usb(0, 1, serial, 0); if (!sl) { ELOG("Failed to open USB device %#06x:%#06x\n", desc.idVendor, desc.idProduct); continue; diff --git a/src/usb.h b/src/usb.h index 968f38ba4..061042e8d 100644 --- a/src/usb.h +++ b/src/usb.h @@ -68,7 +68,7 @@ extern "C" { * @retval NULL Error while opening the stlink * @retval !NULL Stlink found and ready to use */ - stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[STLINK_SERIAL_MAX_SIZE]); + stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq); size_t stlink_probe_usb(stlink_t **stdevs[]); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); diff --git a/tests/flash.c b/tests/flash.c index 96a43a2c3..3166e72b5 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -83,6 +83,7 @@ static struct Test tests[] = { .size = 0x1000, .reset = 1, .log_level = DEBUG_LOG_LEVEL, + .freq = 0, .format = FLASH_FORMAT_BINARY } }, { "--debug --reset write test.bin 0x80000000", 0, @@ -93,6 +94,51 @@ static struct Test tests[] = { .size = 0, .reset = 1, .log_level = DEBUG_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } + }, + { "--debug --freq 5k --reset write test.bin 0x80000000", 0, + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 5, + .format = FLASH_FORMAT_BINARY } + }, + { "--debug --freq 15K --reset write test.bin 0x80000000", 0, + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 15, + .format = FLASH_FORMAT_BINARY } + }, + { "--debug --freq=5k --reset write test.bin 0x80000000", 0, + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } + }, + { "--debug --freq=6k --reset write test.bin 0x80000000", -1, + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 6, .format = FLASH_FORMAT_BINARY } }, { "--debug --reset read test.bin 0x80000000 1000", 0, @@ -103,6 +149,7 @@ static struct Test tests[] = { .size = 1000, .reset = 1, .log_level = DEBUG_LOG_LEVEL, + .freq = 0, .format = FLASH_FORMAT_BINARY } }, { "--debug --reset read test.bin 0x80000000 1k", 0, @@ -113,6 +160,7 @@ static struct Test tests[] = { .size = 1024, .reset = 1, .log_level = DEBUG_LOG_LEVEL, + .freq = 0, .format = FLASH_FORMAT_BINARY } }, { "--debug --reset read test.bin 0x80000000 1M", 0, @@ -123,6 +171,7 @@ static struct Test tests[] = { .size = 1048576, .reset = 1, .log_level = DEBUG_LOG_LEVEL, + .freq = 0, .format = FLASH_FORMAT_BINARY } }, { "--debug --reset write test.bin 0x80000000", 0, @@ -133,6 +182,7 @@ static struct Test tests[] = { .size = 0, .reset = 1, .log_level = DEBUG_LOG_LEVEL, + .freq = 0, .format = FLASH_FORMAT_BINARY } }, { "erase", 0, @@ -143,6 +193,7 @@ static struct Test tests[] = { .size = 0, .reset = 0, .log_level = STND_LOG_LEVEL, + .freq = 0, .format = FLASH_FORMAT_BINARY } }, { "--debug --reset --format=ihex write test.hex", 0, @@ -153,6 +204,7 @@ static struct Test tests[] = { .size = 0, .reset = 1, .log_level = DEBUG_LOG_LEVEL, + .freq = 0, .format = FLASH_FORMAT_IHEX } }, { "--debug --reset --format=binary write test.hex", -1, FLASH_OPTS_INITIALIZER }, @@ -167,6 +219,7 @@ static struct Test tests[] = { .size = 0, .reset = 0, .log_level = STND_LOG_LEVEL, + .freq = 0, .format = FLASH_FORMAT_BINARY } }, { "--serial=A1020304 erase", 0, @@ -177,6 +230,7 @@ static struct Test tests[] = { .size = 0, .reset = 0, .log_level = STND_LOG_LEVEL, + .freq = 0, .format = FLASH_FORMAT_BINARY } }, }; diff --git a/tests/usb.c b/tests/usb.c index d4098834d..5165ea563 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -9,7 +9,7 @@ int main(int ac, char** av) { stlink_t* sl; struct stlink_reg regs; - sl = stlink_open_usb(10, 1, NULL); + sl = stlink_open_usb(10, 1, NULL, 0); if (sl != NULL) { printf("-- version\n"); stlink_version(sl); From 931141869e17f72a01dc14ebd27cca8f86348c32 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Thu, 7 May 2020 18:52:34 +0800 Subject: [PATCH 0919/1435] Fix missing cmp and wrong expected value for freq --- tests/flash.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/flash.c b/tests/flash.c index 3166e72b5..d47b3564d 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -66,6 +66,7 @@ static bool execute_test(const struct Test * test) { ret &= (opts.size == test->opts.size); ret &= (opts.reset == test->opts.reset); ret &= (opts.log_level == test->opts.log_level); + ret &= (opts.freq == test->opts.freq); ret &= (opts.format == test->opts.format); } @@ -127,7 +128,7 @@ static struct Test tests[] = { .size = 0, .reset = 1, .log_level = DEBUG_LOG_LEVEL, - .freq = 0, + .freq = 5, .format = FLASH_FORMAT_BINARY } }, { "--debug --freq=6k --reset write test.bin 0x80000000", -1, From 6c6f27b0f55fdd482ece7d223293ddc3e9a7a90b Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Fri, 8 May 2020 15:40:29 +0800 Subject: [PATCH 0920/1435] Add documentation of --freq and --opt --- doc/tutorial.md | 11 +++++++++++ include/stlink.h | 2 +- include/stlink/tools/flash.h | 4 ++-- src/usb.c | 2 +- 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index 929aa3250..ad64a8db8 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -19,6 +19,17 @@ The size may be followed by an optional "k" or "m" to multiply the given value b When flashing a file, a checksum is calculated for the binary file, both in md5 and the sum algorithm. The latter is also used by the official ST-Link utility tool from STMicroelectronics as described in the document: [`UM0892 - User manual - STM32 ST-LINK utility software description`](https://www.st.com/resource/en/user_manual/cd00262073-stm32-stlink-utility-software-description-stmicroelectronics.pdf). +#### --freq=n[k][m] + +(since v1.6.1) + +You can specify the frequency of SWD/JTAG interface, to override the default 1800KHz configuration. This option accpets decimal only (5K or 1.8M). `Hz` is left out in this option. Valid frequencies are `5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)` + +#### --opt + +(since v1.6.1, optional; enabled by default from v1.0.0 to v1.6.0) + +You can enable the optimization to skip flashing empty (0x00 or 0xff) bytes at the end of binary file. May cause some garbage data left after a flash. ## Solutions to common problems ### a) STLINK/v1 driver: Issue with Kernel Extension (kext) (macOS 10.11 and later only) diff --git a/include/stlink.h b/include/stlink.h index ffa65b332..b8080fd5e 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -151,7 +151,7 @@ typedef struct flash_loader { // transport layer verboseness: 0 for no debug info, 10 for lots int verbose; - int opt; + int opt; // set by main() in tools/flash.c, empty tail bytes drop optimization uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram int core_stat; // set by stlink_status(), values STLINK_CORE_xxxxx diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index b8954af65..a912a14aa 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -25,8 +25,8 @@ struct flash_opts enum flash_area area; uint32_t val; size_t flash_size; /* --flash=n[k][m] */ - int opt; - int freq; + int opt; /* enable empty tail data drop optimization */ + int freq; /* --freq=n[k][m] frequency of JTAG/SWD */ }; #define FLASH_OPTS_INITIALIZER {0, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} diff --git a/src/usb.c b/src/usb.c index ef3743c78..148ad7652 100644 --- a/src/usb.c +++ b/src/usb.c @@ -1042,7 +1042,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST } - sl->opt = freq; + sl->freq = freq; // set the speed before entering the mode // as the chip discovery phase should be done at this speed too // Set the stlink clock speed (default is 1800kHz) From f6e9cb1be385494a4dda45f03f58d7109ae971ea Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 9 May 2020 21:28:59 +0200 Subject: [PATCH 0921/1435] Additional fixes for #863 - Comment for selection of API-Version (#271) - Whitespace cleanup - Fixed casting (-Wshorten-64-to-32) --- include/stlink.h | 466 +++++++++++++++++++++++------------------------ src/usb.c | 22 +-- 2 files changed, 238 insertions(+), 250 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index 4e7fedc66..3aca9d8ee 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -1,9 +1,10 @@ /* - * File: stlink.h + * File: stlink.h * - * This should contain all the common top level stlink interfaces, regardless - * of how the backend does the work.... + * This should contain all the common top level stlink interfaces, + * regardless of how the backend does the work.... */ + #ifndef STLINK_H #define STLINK_H @@ -19,10 +20,10 @@ extern "C" { #define STLINK_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) - // Max data transfer size. - // 6kB = max mem32_read block, 8kB sram - //#define Q_BUF_LEN 96 -#define Q_BUF_LEN (1024 * 100) +/* Max data transfer size */ +// 6kB = max mem32_read block, 8kB sram +//#define Q_BUF_LEN 96 +#define Q_BUF_LEN (1024 * 100) // STLINK_DEBUG_RESETSYS, etc: enum target_state { @@ -33,79 +34,76 @@ enum target_state { TARGET_DEBUG_RUNNING = 4, }; -#define STLINK_CORE_RUNNING 0x80 -#define STLINK_CORE_HALTED 0x81 +#define STLINK_CORE_RUNNING 0x80 +#define STLINK_CORE_HALTED 0x81 -#define STLINK_GET_VERSION 0xf1 -#define STLINK_GET_CURRENT_MODE 0xf5 -#define STLINK_GET_TARGET_VOLTAGE 0xF7 +#define STLINK_GET_VERSION 0xF1 +#define STLINK_GET_CURRENT_MODE 0xF5 +#define STLINK_GET_TARGET_VOLTAGE 0xF7 -#define STLINK_DEBUG_COMMAND 0xF2 -#define STLINK_DFU_COMMAND 0xF3 -#define STLINK_DFU_EXIT 0x07 +#define STLINK_DEBUG_COMMAND 0xF2 +#define STLINK_DFU_COMMAND 0xF3 +#define STLINK_DFU_EXIT 0x07 - // STLINK_GET_CURRENT_MODE -#define STLINK_DEV_DFU_MODE 0x00 -#define STLINK_DEV_MASS_MODE 0x01 -#define STLINK_DEV_DEBUG_MODE 0x02 -#define STLINK_DEV_UNKNOWN_MODE -1 +// STLINK_GET_CURRENT_MODE +#define STLINK_DEV_DFU_MODE 0x00 +#define STLINK_DEV_MASS_MODE 0x01 +#define STLINK_DEV_DEBUG_MODE 0x02 +#define STLINK_DEV_UNKNOWN_MODE -1 - // TODO - possible poor names... -#define STLINK_SWD_ENTER 0x30 -#define STLINK_SWD_READCOREID 0x32 // TBD -#define STLINK_JTAG_WRITEDEBUG_32BIT 0x35 -#define STLINK_JTAG_READDEBUG_32BIT 0x36 -#define STLINK_JTAG_DRIVE_NRST 0x3c +// TODO - possible poor names... +#define STLINK_SWD_ENTER 0x30 +#define STLINK_SWD_READCOREID 0x32 // TBD +#define STLINK_JTAG_WRITEDEBUG_32BIT 0x35 +#define STLINK_JTAG_READDEBUG_32BIT 0x36 +#define STLINK_JTAG_DRIVE_NRST 0x3C -#define STLINK_DEBUG_APIV2_SWD_SET_FREQ 0x43 +#define STLINK_DEBUG_APIV2_SWD_SET_FREQ 0x43 -#define STLINK_APIV3_SET_COM_FREQ 0x61 -#define STLINK_APIV3_GET_COM_FREQ 0x62 +#define STLINK_APIV3_SET_COM_FREQ 0x61 +#define STLINK_APIV3_GET_COM_FREQ 0x62 -#define STLINK_APIV3_GET_VERSION_EX 0xFB +#define STLINK_APIV3_GET_VERSION_EX 0xFB -// Baud rate divisors for SWDCLK -#define STLINK_SWDCLK_4MHZ_DIVISOR 0 -#define STLINK_SWDCLK_1P8MHZ_DIVISOR 1 -#define STLINK_SWDCLK_1P2MHZ_DIVISOR 2 -#define STLINK_SWDCLK_950KHZ_DIVISOR 3 -#define STLINK_SWDCLK_480KHZ_DIVISOR 7 -#define STLINK_SWDCLK_240KHZ_DIVISOR 15 -#define STLINK_SWDCLK_125KHZ_DIVISOR 31 -#define STLINK_SWDCLK_100KHZ_DIVISOR 40 -#define STLINK_SWDCLK_50KHZ_DIVISOR 79 -#define STLINK_SWDCLK_25KHZ_DIVISOR 158 -#define STLINK_SWDCLK_15KHZ_DIVISOR 265 -#define STLINK_SWDCLK_5KHZ_DIVISOR 798 +/* Baud rate divisors for SWDCLK */ +#define STLINK_SWDCLK_4MHZ_DIVISOR 0 +#define STLINK_SWDCLK_1P8MHZ_DIVISOR 1 +#define STLINK_SWDCLK_1P2MHZ_DIVISOR 2 +#define STLINK_SWDCLK_950KHZ_DIVISOR 3 +#define STLINK_SWDCLK_480KHZ_DIVISOR 7 +#define STLINK_SWDCLK_240KHZ_DIVISOR 15 +#define STLINK_SWDCLK_125KHZ_DIVISOR 31 +#define STLINK_SWDCLK_100KHZ_DIVISOR 40 +#define STLINK_SWDCLK_50KHZ_DIVISOR 79 +#define STLINK_SWDCLK_25KHZ_DIVISOR 158 +#define STLINK_SWDCLK_15KHZ_DIVISOR 265 +#define STLINK_SWDCLK_5KHZ_DIVISOR 798 -#define STLINK_SERIAL_MAX_SIZE 64 +#define STLINK_SERIAL_MAX_SIZE 64 -#define STLINK_V3_MAX_FREQ_NB 10 +#define STLINK_V3_MAX_FREQ_NB 10 /* Cortex Debug Control Block */ -#define DCB_DHCSR 0xE000EDF0 -#define DCB_DCRSR 0xE000EDF4 -#define DCB_DCRDR 0xE000EDF8 -#define DCB_DEMCR 0xE000EDFC +#define DCB_DHCSR 0xE000EDF0 +#define DCB_DCRSR 0xE000EDF4 +#define DCB_DCRDR 0xE000EDF8 +#define DCB_DEMCR 0xE000EDFC /* DCB_DHCSR bit and field definitions */ -#define DBGKEY (0xA05F << 16) -#define C_DEBUGEN (1 << 0) -#define C_HALT (1 << 1) -#define C_STEP (1 << 2) -#define C_MASKINTS (1 << 3) -#define S_REGRDY (1 << 16) -#define S_HALT (1 << 17) -#define S_SLEEP (1 << 18) -#define S_LOCKUP (1 << 19) -#define S_RETIRE_ST (1 << 24) -#define S_RESET_ST (1 << 25) - - -/* - * Map the relevant features, quirks and workaround for specific firmware - * version of stlink - */ +#define DBGKEY (0xA05F << 16) +#define C_DEBUGEN (1 << 0) +#define C_HALT (1 << 1) +#define C_STEP (1 << 2) +#define C_MASKINTS (1 << 3) +#define S_REGRDY (1 << 16) +#define S_HALT (1 << 17) +#define S_SLEEP (1 << 18) +#define S_LOCKUP (1 << 19) +#define S_RETIRE_ST (1 << 24) +#define S_RESET_ST (1 << 25) + + +/* Map the relevant features, quirks and workaround for specific firmware version of stlink */ #define STLINK_F_HAS_TRACE (1<<0) #define STLINK_F_HAS_SWD_SET_FREQ (1<<1) #define STLINK_F_HAS_JTAG_SET_FREQ (1<<2) @@ -120,181 +118,181 @@ enum target_state { #define C_BUF_LEN 32 - enum stlink_flash_type { - STLINK_FLASH_TYPE_UNKNOWN = 0, - STLINK_FLASH_TYPE_F0, /* used by f0, f1 (except f1xl),f3. */ - STLINK_FLASH_TYPE_F1_XL, /* f0 flash with dual bank, apparently */ - STLINK_FLASH_TYPE_F4, /* used by f2, f4, f7 */ - STLINK_FLASH_TYPE_L0, /* l0, l1 */ - STLINK_FLASH_TYPE_L4, /* l4, l4+ */ - STLINK_FLASH_TYPE_G0, - STLINK_FLASH_TYPE_G4, - STLINK_FLASH_TYPE_WB - }; - - struct stlink_reg { - uint32_t r[16]; - uint32_t s[32]; - uint32_t xpsr; - uint32_t main_sp; - uint32_t process_sp; - uint32_t rw; - uint32_t rw2; - uint8_t control; - uint8_t faultmask; - uint8_t basepri; - uint8_t primask; - uint32_t fpscr; - }; - - typedef uint32_t stm32_addr_t; +enum stlink_flash_type { + STLINK_FLASH_TYPE_UNKNOWN = 0, + STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */ + STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank, apparently */ + STLINK_FLASH_TYPE_F4, // used by f2, f4, f7 */ + STLINK_FLASH_TYPE_L0, // l0, l1 */ + STLINK_FLASH_TYPE_L4, // l4, l4+ */ + STLINK_FLASH_TYPE_G0, + STLINK_FLASH_TYPE_G4, + STLINK_FLASH_TYPE_WB +}; + +struct stlink_reg { + uint32_t r[16]; + uint32_t s[32]; + uint32_t xpsr; + uint32_t main_sp; + uint32_t process_sp; + uint32_t rw; + uint32_t rw2; + uint8_t control; + uint8_t faultmask; + uint8_t basepri; + uint8_t primask; + uint32_t fpscr; +}; + +typedef uint32_t stm32_addr_t; typedef struct flash_loader { - stm32_addr_t loader_addr; /* loader sram adddr */ - stm32_addr_t buf_addr; /* buffer sram address */ +stm32_addr_t loader_addr; // loader sram addr +stm32_addr_t buf_addr; // buffer sram address } flash_loader_t; - typedef struct _cortex_m3_cpuid_ { - uint16_t implementer_id; - uint16_t variant; - uint16_t part; - uint8_t revision; - } cortex_m3_cpuid_t; - - enum stlink_jtag_api_version { - STLINK_JTAG_API_V1 = 1, - STLINK_JTAG_API_V2, - STLINK_JTAG_API_V3, - }; - - typedef struct stlink_version_ { - uint32_t stlink_v; - uint32_t jtag_v; - uint32_t swim_v; - uint32_t st_vid; - uint32_t stlink_pid; - /** jtag api version supported */ - enum stlink_jtag_api_version jtag_api; - /** one bit for each feature supported. See macros STLINK_F_* */ - uint32_t flags; - } stlink_version_t; - - enum transport_type { - TRANSPORT_TYPE_ZERO = 0, - TRANSPORT_TYPE_LIBSG, - TRANSPORT_TYPE_LIBUSB, - TRANSPORT_TYPE_INVALID - }; - - typedef struct _stlink stlink_t; +typedef struct _cortex_m3_cpuid_ { + uint16_t implementer_id; + uint16_t variant; + uint16_t part; + uint8_t revision; +} cortex_m3_cpuid_t; + +enum stlink_jtag_api_version { + STLINK_JTAG_API_V1 = 1, + STLINK_JTAG_API_V2, + STLINK_JTAG_API_V3, +}; + +typedef struct stlink_version_ { + uint32_t stlink_v; + uint32_t jtag_v; + uint32_t swim_v; + uint32_t st_vid; + uint32_t stlink_pid; + // jtag api version supported + enum stlink_jtag_api_version jtag_api; + // one bit for each feature supported. See macros STLINK_F_* + uint32_t flags; +} stlink_version_t; + +enum transport_type { + TRANSPORT_TYPE_ZERO = 0, + TRANSPORT_TYPE_LIBSG, + TRANSPORT_TYPE_LIBUSB, + TRANSPORT_TYPE_INVALID +}; + +typedef struct _stlink stlink_t; #include - struct _stlink { - struct _stlink_backend *backend; - void *backend_data; - - // Room for the command header - unsigned char c_buf[C_BUF_LEN]; - // Data transferred from or to device - unsigned char q_buf[Q_BUF_LEN]; - int q_len; - - // transport layer verboseness: 0 for no debug info, 10 for lots - int verbose; - int opt; - uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID - uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram - enum target_state core_stat; // set by stlink_status() - - char serial[STLINK_SERIAL_MAX_SIZE]; - int serial_size; - - enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx - bool has_dual_bank; - - stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() - size_t flash_size; // calculated by stlink_load_device_params() - size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() - - /* sram settings */ - stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() - size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() - - /* option settings */ - stm32_addr_t option_base; - size_t option_size; - - // bootloader - // sys_base and sys_size are not used by the tools, but are only there to - // download the bootloader code (see tests/sg.c) - stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() - size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() - - struct stlink_version_ version; - }; - - int stlink_enter_swd_mode(stlink_t *sl); - int stlink_enter_jtag_mode(stlink_t *sl); - int stlink_exit_debug_mode(stlink_t *sl); - int stlink_exit_dfu_mode(stlink_t *sl); - void stlink_close(stlink_t *sl); - int stlink_core_id(stlink_t *sl); - int stlink_reset(stlink_t *sl); - int stlink_jtag_reset(stlink_t *sl, int value); - int stlink_run(stlink_t *sl); - int stlink_status(stlink_t *sl); - int stlink_version(stlink_t *sl); - int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); - int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); - int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); - int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); - int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); - int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); - int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); - int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); - int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); - int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, struct stlink_reg *regp); - int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); - int stlink_step(stlink_t *sl); - int stlink_current_mode(stlink_t *sl); - int stlink_force_debug(stlink_t *sl); - int stlink_target_voltage(stlink_t *sl); - int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); - - int stlink_erase_flash_mass(stlink_t* sl); - int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); - int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); - uint8_t stlink_get_erased_pattern(stlink_t *sl); - int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); - int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); - int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); - - int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); - int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); - - int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); - uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); - uint16_t read_uint16(const unsigned char *c, const int pt); - void stlink_core_stat(stlink_t *sl); - void stlink_print_data(stlink_t *sl); - unsigned int is_bigendian(void); - uint32_t read_uint32(const unsigned char *c, const int pt); - void write_uint32(unsigned char* buf, uint32_t ui); - void write_uint16(unsigned char* buf, uint16_t ui); - bool stlink_is_core_halted(stlink_t *sl); - int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); - int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); - int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); - int stlink_load_device_params(stlink_t *sl); - - int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); - int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); - - int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); - int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); +struct _stlink { + struct _stlink_backend *backend; + void *backend_data; + + // Room for the command header + unsigned char c_buf[C_BUF_LEN]; + // Data transferred from or to device + unsigned char q_buf[Q_BUF_LEN]; + int q_len; + + // transport layer verboseness: 0 for no debug info, 10 for lots + int verbose; + int opt; + uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID + uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram + enum target_state core_stat; // set by stlink_status() + + char serial[STLINK_SERIAL_MAX_SIZE]; + int serial_size; + + enum stlink_flash_type flash_type; + // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx + bool has_dual_bank; + + stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() + size_t flash_size; // calculated by stlink_load_device_params() + size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() + + /* sram settings */ + stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() + size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() + + /* option settings */ + stm32_addr_t option_base; + size_t option_size; + + // bootloader + // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code (see tests/sg.c) + stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() + size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() + + struct stlink_version_ version; +}; + +int stlink_enter_swd_mode(stlink_t *sl); +int stlink_enter_jtag_mode(stlink_t *sl); +int stlink_exit_debug_mode(stlink_t *sl); +int stlink_exit_dfu_mode(stlink_t *sl); +void stlink_close(stlink_t *sl); +int stlink_core_id(stlink_t *sl); +int stlink_reset(stlink_t *sl); +int stlink_jtag_reset(stlink_t *sl, int value); +int stlink_run(stlink_t *sl); +int stlink_status(stlink_t *sl); +int stlink_version(stlink_t *sl); +int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); +int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); +int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); +int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); +int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); +int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); +int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); +int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, struct stlink_reg *regp); +int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); +int stlink_step(stlink_t *sl); +int stlink_current_mode(stlink_t *sl); +int stlink_force_debug(stlink_t *sl); +int stlink_target_voltage(stlink_t *sl); +int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); + +int stlink_erase_flash_mass(stlink_t* sl); +int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); +int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); +uint8_t stlink_get_erased_pattern(stlink_t *sl); +int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); +int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); +int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); +int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); +int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); + +int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); +int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); + +int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); +uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); +uint16_t read_uint16(const unsigned char *c, const int pt); +void stlink_core_stat(stlink_t *sl); +void stlink_print_data(stlink_t *sl); +unsigned int is_bigendian(void); +uint32_t read_uint32(const unsigned char *c, const int pt); +void write_uint32(unsigned char* buf, uint32_t ui); +void write_uint16(unsigned char* buf, uint16_t ui); +bool stlink_is_core_halted(stlink_t *sl); +int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); +int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); +int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); +int stlink_load_device_params(stlink_t *sl); + +int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); + +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); #include #include diff --git a/src/usb.c b/src/usb.c index 8db78016d..bd9f8e51e 100644 --- a/src/usb.c +++ b/src/usb.c @@ -87,11 +87,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, int res = 0; int t; - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, - txbuf, - (int) txsize, - &res, - 3000); + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int) txsize, &res, 3000); if (t) { printf("[!] send_recv send request failed: %s\n", libusb_error_name(t)); return -1; @@ -101,11 +97,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, } if (rxsize != 0) { - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, - rxbuf, - (int) rxsize, - &res, - 3000); + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int) rxsize, &res, 3000); if (t) { printf("[!] send_recv read reply failed: %s\n", libusb_error_name(t)); @@ -116,11 +108,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, if ((handle->protocoll == 1) && terminate) { /* Read the SG reply */ unsigned char sg_buf[13]; - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, - sg_buf, - 13, - &res, - 3000); + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); if (t) { printf("[!] send_recv read storage failed: %s\n", libusb_error_name(t)); @@ -270,7 +258,8 @@ int _stlink_usb_get_rw_status(stlink_t *sl) unsigned char* const rdata = sl->q_buf; struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; - int i, ret = 0; + int i; + int16_t ret = 0; i = fill_command(sl, SG_DXFER_FROM_DEV, 12); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -456,6 +445,7 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; + // Select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30) cmd[i++] = sl->version.jtag_api == STLINK_JTAG_API_V1 ? STLINK_DEBUG_APIV1_ENTER : STLINK_DEBUG_APIV2_ENTER; cmd[i++] = STLINK_DEBUG_ENTER_SWD; From 7a5b6ef2f707660e79d2ff7fde4aa84390da19be Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 9 May 2020 22:20:17 +0200 Subject: [PATCH 0922/1435] Whitespace cleanup --- include/stlink.h | 331 ++++++++++++++++++++++++----------------------- 1 file changed, 166 insertions(+), 165 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index b8080fd5e..68ca0ab39 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -1,9 +1,10 @@ /* * File: stlink.h * - * This should contain all the common top level stlink interfaces, regardless - * of how the backend does the work.... + * This should contain all the common top level stlink interfaces, + * regardless of how the backend does the work.... */ + #ifndef STLINK_H #define STLINK_H @@ -19,12 +20,12 @@ extern "C" { #define STLINK_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) - // Max data transfer size. - // 6kB = max mem32_read block, 8kB sram - //#define Q_BUF_LEN 96 +// Max data transfer size. +// 6kB = max mem32_read block, 8kB sram +//#define Q_BUF_LEN 96 #define Q_BUF_LEN (1024 * 100) - // STLINK_DEBUG_RESETSYS, etc: +// STLINK_DEBUG_RESETSYS, etc: #define STLINK_CORE_RUNNING 0x80 #define STLINK_CORE_HALTED 0x81 #define STLINK_CORE_STAT_UNKNOWN -1 @@ -37,13 +38,13 @@ extern "C" { #define STLINK_DFU_COMMAND 0xF3 #define STLINK_DFU_EXIT 0x07 - // STLINK_GET_CURRENT_MODE +// STLINK_GET_CURRENT_MODE #define STLINK_DEV_DFU_MODE 0x00 #define STLINK_DEV_MASS_MODE 0x01 #define STLINK_DEV_DEBUG_MODE 0x02 #define STLINK_DEV_UNKNOWN_MODE -1 - // TODO - possible poor names... +// TODO - possible poor names... #define STLINK_SWD_ENTER 0x30 #define STLINK_SWD_READCOREID 0x32 // TBD #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35 @@ -76,176 +77,176 @@ extern "C" { #define STLINK_V3_MAX_FREQ_NB 10 - /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ +/* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 - enum stlink_flash_type { - STLINK_FLASH_TYPE_UNKNOWN = 0, - STLINK_FLASH_TYPE_F0, /* used by f0, f1 (except f1xl),f3. */ - STLINK_FLASH_TYPE_F1_XL, /* f0 flash with dual bank, apparently */ - STLINK_FLASH_TYPE_F4, /* used by f2, f4, f7 */ - STLINK_FLASH_TYPE_L0, /* l0, l1 */ - STLINK_FLASH_TYPE_L4, /* l4, l4+ */ - STLINK_FLASH_TYPE_G0, - STLINK_FLASH_TYPE_G4, - STLINK_FLASH_TYPE_WB - }; - - struct stlink_reg { - uint32_t r[16]; - uint32_t s[32]; - uint32_t xpsr; - uint32_t main_sp; - uint32_t process_sp; - uint32_t rw; - uint32_t rw2; - uint8_t control; - uint8_t faultmask; - uint8_t basepri; - uint8_t primask; - uint32_t fpscr; - }; - - typedef uint32_t stm32_addr_t; +enum stlink_flash_type { + STLINK_FLASH_TYPE_UNKNOWN = 0, + STLINK_FLASH_TYPE_F0, /* used by f0, f1 (except f1xl),f3. */ + STLINK_FLASH_TYPE_F1_XL, /* f0 flash with dual bank, apparently */ + STLINK_FLASH_TYPE_F4, /* used by f2, f4, f7 */ + STLINK_FLASH_TYPE_L0, /* l0, l1 */ + STLINK_FLASH_TYPE_L4, /* l4, l4+ */ + STLINK_FLASH_TYPE_G0, + STLINK_FLASH_TYPE_G4, + STLINK_FLASH_TYPE_WB +}; + +struct stlink_reg { + uint32_t r[16]; + uint32_t s[32]; + uint32_t xpsr; + uint32_t main_sp; + uint32_t process_sp; + uint32_t rw; + uint32_t rw2; + uint8_t control; + uint8_t faultmask; + uint8_t basepri; + uint8_t primask; + uint32_t fpscr; +}; + +typedef uint32_t stm32_addr_t; typedef struct flash_loader { stm32_addr_t loader_addr; /* loader sram adddr */ stm32_addr_t buf_addr; /* buffer sram address */ } flash_loader_t; - typedef struct _cortex_m3_cpuid_ { - uint16_t implementer_id; - uint16_t variant; - uint16_t part; - uint8_t revision; - } cortex_m3_cpuid_t; - - typedef struct stlink_version_ { - uint32_t stlink_v; - uint32_t jtag_v; - uint32_t swim_v; - uint32_t st_vid; - uint32_t stlink_pid; - } stlink_version_t; - - enum transport_type { - TRANSPORT_TYPE_ZERO = 0, - TRANSPORT_TYPE_LIBSG, - TRANSPORT_TYPE_LIBUSB, - TRANSPORT_TYPE_INVALID - }; +typedef struct _cortex_m3_cpuid_ { + uint16_t implementer_id; + uint16_t variant; + uint16_t part; + uint8_t revision; +} cortex_m3_cpuid_t; + +typedef struct stlink_version_ { + uint32_t stlink_v; + uint32_t jtag_v; + uint32_t swim_v; + uint32_t st_vid; + uint32_t stlink_pid; +} stlink_version_t; + +enum transport_type { + TRANSPORT_TYPE_ZERO = 0, + TRANSPORT_TYPE_LIBSG, + TRANSPORT_TYPE_LIBUSB, + TRANSPORT_TYPE_INVALID +}; typedef struct _stlink stlink_t; #include - struct _stlink { - struct _stlink_backend *backend; - void *backend_data; - - // Room for the command header - unsigned char c_buf[C_BUF_LEN]; - // Data transferred from or to device - unsigned char q_buf[Q_BUF_LEN]; - int q_len; - - // transport layer verboseness: 0 for no debug info, 10 for lots - int verbose; - int opt; // set by main() in tools/flash.c, empty tail bytes drop optimization - uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID - uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram - int core_stat; // set by stlink_status(), values STLINK_CORE_xxxxx - - char serial[STLINK_SERIAL_MAX_SIZE]; - int serial_size; - - int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR - - enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx - bool has_dual_bank; - - stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() - size_t flash_size; // calculated by stlink_load_device_params() - size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() - - /* sram settings */ - stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() - size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() - - /* option settings */ - stm32_addr_t option_base; - size_t option_size; - - // bootloader - // sys_base and sys_size are not used by the tools, but are only there to - // download the bootloader code (see tests/sg.c) - stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() - size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() - - struct stlink_version_ version; - }; - - int stlink_enter_swd_mode(stlink_t *sl); - int stlink_enter_jtag_mode(stlink_t *sl); - int stlink_exit_debug_mode(stlink_t *sl); - int stlink_exit_dfu_mode(stlink_t *sl); - void stlink_close(stlink_t *sl); - int stlink_core_id(stlink_t *sl); - int stlink_reset(stlink_t *sl); - int stlink_jtag_reset(stlink_t *sl, int value); - int stlink_run(stlink_t *sl); - int stlink_status(stlink_t *sl); - int stlink_version(stlink_t *sl); - int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); - int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); - int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); - int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); - int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); - int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); - int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); - int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); - int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); - int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, struct stlink_reg *regp); - int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); - int stlink_step(stlink_t *sl); - int stlink_current_mode(stlink_t *sl); - int stlink_force_debug(stlink_t *sl); - int stlink_target_voltage(stlink_t *sl); - int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); - - int stlink_erase_flash_mass(stlink_t* sl); - int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); - int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); - uint8_t stlink_get_erased_pattern(stlink_t *sl); - int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); - int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); - int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); - - int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); - int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); - - int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); - uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); - uint16_t read_uint16(const unsigned char *c, const int pt); - void stlink_core_stat(stlink_t *sl); - void stlink_print_data(stlink_t *sl); - unsigned int is_bigendian(void); - uint32_t read_uint32(const unsigned char *c, const int pt); - void write_uint32(unsigned char* buf, uint32_t ui); - void write_uint16(unsigned char* buf, uint16_t ui); - bool stlink_is_core_halted(stlink_t *sl); - int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); - int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); - int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); - int stlink_load_device_params(stlink_t *sl); - - int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); - int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); - - int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); - int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); +struct _stlink { + struct _stlink_backend *backend; + void *backend_data; + + // Room for the command header + unsigned char c_buf[C_BUF_LEN]; + // Data transferred from or to device + unsigned char q_buf[Q_BUF_LEN]; + int q_len; + + // transport layer verboseness: 0 for no debug info, 10 for lots + int verbose; + int opt; // set by main() in tools/flash.c, empty tail bytes drop optimization + uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID + uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram + int core_stat; // set by stlink_status(), values STLINK_CORE_xxxxx + + char serial[STLINK_SERIAL_MAX_SIZE]; + int serial_size; + + int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR + + enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx + bool has_dual_bank; + + stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() + size_t flash_size; // calculated by stlink_load_device_params() + size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() + + /* sram settings */ + stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() + size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() + + /* option settings */ + stm32_addr_t option_base; + size_t option_size; + + // bootloader + // sys_base and sys_size are not used by the tools, but are only there to + // download the bootloader code (see tests/sg.c) + stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() + size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() + + struct stlink_version_ version; +}; + +int stlink_enter_swd_mode(stlink_t *sl); +int stlink_enter_jtag_mode(stlink_t *sl); +int stlink_exit_debug_mode(stlink_t *sl); +int stlink_exit_dfu_mode(stlink_t *sl); +void stlink_close(stlink_t *sl); +int stlink_core_id(stlink_t *sl); +int stlink_reset(stlink_t *sl); +int stlink_jtag_reset(stlink_t *sl, int value); +int stlink_run(stlink_t *sl); +int stlink_status(stlink_t *sl); +int stlink_version(stlink_t *sl); +int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); +int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); +int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); +int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); +int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); +int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); +int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); +int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, struct stlink_reg *regp); +int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); +int stlink_step(stlink_t *sl); +int stlink_current_mode(stlink_t *sl); +int stlink_force_debug(stlink_t *sl); +int stlink_target_voltage(stlink_t *sl); +int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); + +int stlink_erase_flash_mass(stlink_t* sl); +int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); +int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); +uint8_t stlink_get_erased_pattern(stlink_t *sl); +int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); +int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); +int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); +int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); +int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); + +int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); +int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); + +int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); +uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); +uint16_t read_uint16(const unsigned char *c, const int pt); +void stlink_core_stat(stlink_t *sl); +void stlink_print_data(stlink_t *sl); +unsigned int is_bigendian(void); +uint32_t read_uint32(const unsigned char *c, const int pt); +void write_uint32(unsigned char* buf, uint32_t ui); +void write_uint16(unsigned char* buf, uint16_t ui); +bool stlink_is_core_halted(stlink_t *sl); +int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); +int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); +int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); +int stlink_load_device_params(stlink_t *sl); + +int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); + +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); #include #include From 7bb34fcfb2a19c03c7daa2986aad4515f699f24b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 10 May 2020 00:47:37 +0200 Subject: [PATCH 0923/1435] Update for windows binary packaging - Updated steps for release preparation - Changed destination for binary archives (Closes #798) --- cmake/packaging/cpack_config.cmake | 3 +-- cmake/packaging/windows/generate_binaries.sh | 2 ++ doc/release.md | 13 +++++++------ 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index c81362896..a0fddd71c 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -25,12 +25,11 @@ elseif (WIN32 AND NOT EXISTS "/etc/debian_version") set(CPACK_INSTALL_PREFIX "") elseif (WIN32) # Windows cross-build on Debian/Ubuntu - set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_SOURCE_DIR}/build/Release/dist") set(CPACK_GENERATOR "ZIP") set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-${TOOLCHAIN_PREFIX}") set(CPACK_INSTALL_PREFIX "") -elseif (EXISTS "/etc/debian_version") # Package-build is available on Debian/Ubuntu only +elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is available on Debian/Ubuntu only message(STATUS "Debian-based Linux OS detected") set(CPACK_GENERATOR "DEB;RPM") # RPM requires package `rpm` diff --git a/cmake/packaging/windows/generate_binaries.sh b/cmake/packaging/windows/generate_binaries.sh index ba5b965f5..d38f8d62f 100644 --- a/cmake/packaging/windows/generate_binaries.sh +++ b/cmake/packaging/windows/generate_binaries.sh @@ -12,6 +12,7 @@ cmake -DCMAKE_SYSTEM_NAME=Windows \ -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=./cmake/modules/set_toolchain.cmake .. make package +cp dist/*.zip ../build/Release/dist cd .. rm -rf build-mingw @@ -22,5 +23,6 @@ cmake -DCMAKE_SYSTEM_NAME=Windows \ -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=./cmake/modules/set_toolchain.cmake .. make package +cp dist/*.zip ../build/Release/dist cd .. rm -rf build-mingw diff --git a/doc/release.md b/doc/release.md index ae8b864ee..4b536d95a 100644 --- a/doc/release.md +++ b/doc/release.md @@ -1,10 +1,11 @@ Release ======= -This document describes the steps it takes for developers to create a release +This document describes the necessary steps for developers to create a release: -1. Update `.version` with semantic version: `x.x.x` -2. Update `README.md` with semantic version `x.x.x` in commits badge -2. Create and push git tag and commits `git tag x.x.x` -3. Create source tarball/zipfile with `make dist` -4. Create binary package with `make package` +1. Update `CHANGELOG.md` and `cmake/packaging/deb/changelog` +2. Update `.version` with semantic version: `x.x.x` +3. Update `README.md` with semantic version `x.x.x` in commits badge +4. Create and push git tag and commits `git tag x.x.x` +5. Create binary packages (.rpm / .deb / .zip) with `make package && sh ./cmake/packaging/windows/generate_binaries.sh` +6. Upload packages to the [release page](https://github.com/stlink-org/stlink/releases) of this project From d11e6f4c8affac671e42ed55d88d6b911418a215 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 10 May 2020 02:11:08 +0200 Subject: [PATCH 0924/1435] Updated tutorial - Added table for available tool options - Removed install instructions for OpenOCD - Removed outdated content - Fixed toolset description in desktop-file - Added documentation for the stlink-gui (Closes #884) --- doc/tutorial.md | 167 +++++------------------------- src/stlink-gui/stlink-gui.desktop | 2 +- 2 files changed, 25 insertions(+), 144 deletions(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index ad64a8db8..694142184 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -1,35 +1,32 @@ stlink Tools Tutorial ===================== -## Useful tool options +## Available tools and options -### st-flash - -#### --flash=n[k][m] - -(since v1.4.0) - -You can specify `--flash=128k` for example, to override the STM32F103C8T6 to assume 128k of flash instead of the default of 64k. -This option accepts decimal (128k), octal 0200k, or hex 0x80k. -Obviously leaving the multiplier out is equally valid, for example: `--flash=0x20000`. -The size may be followed by an optional "k" or "m" to multiply the given value by 1k (1024) or 1M respectively. - -#### Checksum for binary files +| Option | Tool | Description | Available
    since | +| --- | --- | --- | --- | +| --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k
    for the STM32F103C8T6 to assume 128k of flash being present. This option accepts
    decimal (128k), octal 0200k, or hex 0x80k values. Leaving the multiplier out is
    equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k"
    or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | +| --freq=n[k][m] | st-flash,
    st-util | The frequency of the SWD/JTAG interface can be specified, to override the default
    1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
    the unit `Hz` being left out. Valid frequencies are `5K, 15K, 25K, 50K, 100K,`
    `125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | +| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at
    the end of binary file. This may cause some garbage data left after a flash operation.
    This option was enabled by default in earlier releases. | v1.6.1 | +| --version | st-info,
    st-flash,
    st-util | Print version information. | | +| --help | st-flash,
    st-util | Print list of available commands. _(To be added to this table.)_ | | +### st-flash: Checksum for binary files When flashing a file, a checksum is calculated for the binary file, both in md5 and the sum algorithm. The latter is also used by the official ST-Link utility tool from STMicroelectronics as described in the document: [`UM0892 - User manual - STM32 ST-LINK utility software description`](https://www.st.com/resource/en/user_manual/cd00262073-stm32-stlink-utility-software-description-stmicroelectronics.pdf). -#### --freq=n[k][m] - -(since v1.6.1) +### stlink-gui +The `stlink` toolset also provides a GUI which is an optional feature. It is only installed if a gtk3 toolset has been detected during package installation or compilation from source. It is not available for Windows. If you prefer to have an user interface on the latter system, please use the official `ST-LINK Utility` instead. -You can specify the frequency of SWD/JTAG interface, to override the default 1800KHz configuration. This option accpets decimal only (5K or 1.8M). `Hz` is left out in this option. Valid frequencies are `5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)` +The stlink-gui offers the following features: +* Connect/disconnect to a present STlink programmer +* Display basic device information +* Select a binary file from the local filesystem to flash it to the detected device connected to the programmer +* Export the memory of the connected chip to a file which can be saved to the local filesystem +* Display of the memory address map in the main window for each, the device memory and a loaded binary file -#### --opt +Within the GUI main window tooltips explain the available user elements. -(since v1.6.1, optional; enabled by default from v1.0.0 to v1.6.0) - -You can enable the optimization to skip flashing empty (0x00 or 0xff) bytes at the end of binary file. May cause some garbage data left after a flash. ## Solutions to common problems ### a) STLINK/v1 driver: Issue with Kernel Extension (kext) (macOS 10.11 and later only) @@ -153,22 +150,13 @@ This guide details the use of STMicroelectronics STM32 discovery kits in an open ## Installing a GNU toolchain -Any toolchain supporting the cortex m3 should do. You can find the -necessary to install such a toolchain here: - -``` -https://github.com/esden/summon-arm-toolchain -``` - -Details for the installation are provided in the topmost `README` file. -This documentation assumes the toolchains is installed in a -`$TOOLCHAIN_PATH`. +Any toolchain supporting the cortex m3 should do. ## Using the GDB server -This assumes you have got the libopencm3 project downloaded in `ocm3`. -The libopencm3 project has some good, reliable examples for each of the -Discovery boards. +This assumes you have got the [libopencm3](http://www.libopencm3.org) project downloaded in `ocm3`. +The libopencm3 project provides a firmware library, with solid examples for Cortex M3, M4 and M0 processors +from any vendor. It has some good, reliable examples for each of the Discovery boards. Even if you don’t plan on using libopencm3, the examples they provide will help you verify that: @@ -179,7 +167,7 @@ will help you verify that: - Your arm-none-eabi-gdb is functional - Your board is functional -A GDB server must be started to interact with the STM32 by running +A GDB server must be started to interact with the STM32 by running st-util tool : ``` @@ -283,7 +271,7 @@ There are a few options: Do not reset board on connection. ``` -The STLink device to use can be specified using the --serial parameter, or via +The STLink device to use can be specified using the --serial parameter, or via the environment variable STLINK_DEVICE on the format :. Then, in your project directory, someting like this... @@ -373,42 +361,6 @@ Example to read and write option bytes (currently writing only supported for STM ./st-flash --debug --reset --format binary --flash=128k write option_bytes_dump.bin 0x1FFF7800 ``` -## Installation of openOCD on Mac OS X with STlink-v2: - -`sudo port install openocd +jlink +stlink +ft2232` - -`/opt/local/bin/openocd --version` - -> Open On-Chip Debugger 0.7.0 (2014-08-11-22:12) - -`openocd -f /opt/local/share/openocd/scripts/interface/stlink-v2.cfg -f /opt/local/share/openocd/scripts/target/stm32f1x_stlink.cfg ` - -> Open On-Chip Debugger 0.8.0 (2014-08-11-15:36) -> -> Licensed under GNU GPL v2 -> -> For bug reports, read http://openocd.sourceforge.net/doc/doxygen/bugs.html -> -> Info : This adapter doesn't support configurable speed -> -> Info : STLINK v2 JTAG v21 API v2 SWIM v4 VID 0x0483 PID 0x3748 -> -> Info : using stlink api v2 -> -> Info : Target voltage: 3.244269 -> -> Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints - -and connecting to the server through telnet yields a successful installation - -`telnet localhost 4444` - -> Connected to localhost. -> -> Escape character is '^]'. -> -> Open On-Chip Debugger - FAQ === @@ -424,74 +376,3 @@ A: Sometimes when you will try to use GDB `next` command to skip a loop, it will Q: Load command does not work in GDB. A: Some people report XML/EXPAT is not enabled by default when compiling GDB. Memory map parsing thus fail. Use --enable-expat. - -Q: How can I install stlink and flash binaries on Mac OS X ? - -A: Installed on Mac OS X 10.9.4 with ports method, - however STlink v2 does not seem to work with libusb if you upgrade to the newest firmware !! - Only older firmware on STlink v2 works. - -[https://coderwall.com/p/oznj_q](https://coderwall.com/p/oznj_q) - -``` -sudo port install libusb automake autoconf pkgconfig -aclocal --force -I /opt/local/share/aclocal -git clone https://github.com/stlink-org/stlink.git stlink-utility -cd stlink-utility -./autogen.sh -./configure -make -``` - -Then trying to flash the image with STLINK v2 : - -`./st-flash write ~/Downloads/irq.bin 0x8000000` - -> libusb_handle_events() timeout -> -> [!] send_recv - -ST-Link/V2 debugger with downgraded V2.14.3 firmware: - -https://drive.google.com/folderview?id=0Bzv7UpKpOQhnbXJVVEg4VUo2M1k - -After downgrading the firmware, flashing works as described here: - -http://community.spark.io/t/how-to-flash-a-brand-new-freshly-soldered-stm32f103-chip/3906 - -`./st-flash write ~/Downloads/irq.bin 0x8000000` - -> 2014-08-11T23:14:52 INFO src/stlink-common.c: Loading device parameters.... -> -> 2014-08-11T23:14:52 INFO src/stlink-common.c: Device connected is: F1 Medium-density device, id 0x20036410 -> -> 2014-08-11T23:14:52 INFO src/stlink-common.c: SRAM size: 0x5000 bytes (20 KiB), Flash: 0x20000 bytes (128 KiB) in -> pages of 1024 bytes -> -> 2014-08-11T23:14:52 INFO src/stlink-common.c: Attempting to write 24904 (0x6148) bytes to stm32 address: 134217728 -> (0x8000000) -> -> Flash page at addr: 0x08006000 erased -> -> 2014-08-11T23:14:53 INFO src/stlink-common.c: Finished erasing 25 pages of 1024 (0x400) bytes -> -> 2014-08-11T23:14:53 INFO src/stlink-common.c: Starting Flash write for VL/F0 core id -> -> 2014-08-11T23:14:53 INFO src/stlink-common.c: Successfully loaded flash loader in sram 24/24 pages written -> -> 2014-08-11T23:14:54 INFO src/stlink-common.c: Starting verification of write complete -> -> 2014-08-11T23:14:54 INFO src/stlink-common.c: Flash written and verified! jolly good! - - -References -========== - -- - documentation related to the STM32L mcu - -- - documentation related to the STM32L discovery kit - -- - libopencm3, a project providing a firmware library, with solid examples for Cortex M3, M4 and M0 processors from any vendor. diff --git a/src/stlink-gui/stlink-gui.desktop b/src/stlink-gui/stlink-gui.desktop index 54cb40349..72bc26ac6 100644 --- a/src/stlink-gui/stlink-gui.desktop +++ b/src/stlink-gui/stlink-gui.desktop @@ -1,7 +1,7 @@ [Desktop Entry] Name=stlink GenericName=Stlink Tools -Comment=STM32 discovery line Linux programmer +Comment=Open source STM32 MCU programming toolset Exec=stlink-gui Icon=stlink-gui Terminal=false From 06c66ed308d6e65ad70757c7177444257cb2ea1a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 10 May 2020 16:45:13 +0200 Subject: [PATCH 0925/1435] Updated documentation - Added note on windows binary installation - Contributors now listed in separate file (Closes #738) (Closes #795) --- README.md | 5 +- cmake/packaging/cpack_config.cmake | 7 +- cmake/packaging/deb/copyright | 122 +--------------------------- contributors.txt | 124 +++++++++++++++++++++++++++++ 4 files changed, 134 insertions(+), 124 deletions(-) create mode 100644 contributors.txt diff --git a/README.md b/README.md index 4bf663e34..842284ff7 100644 --- a/README.md +++ b/README.md @@ -66,9 +66,10 @@ Our [tutorial.md](doc/tutorial.md may help you along with some advanced tasks an **Windows**: -Please compile and install from source as described in our [compiling manual](doc/compiling.md#Windows). +As of Release v1.6.1 stand-alone Windows binaries are made available (again) on the release page of the project. +Please ensure to select the correct version for your system (i686 or x86_64). The archive file can be unzipped to any desired location as it does not contain any hardcoded paths. However we suggest to move the unzipped application folder to `C:\Program Files\` on 32-bit systems and to `C:\Program Files (x86)\` on 64-bit systems (the toolset is a 32-bit). -Long awaited binaries will be available soon... +Alternatively one may compile and install from source as described in our [compiling manual](doc/compiling.md#Windows). **macOS**: diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index a0fddd71c..da03bb596 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -19,7 +19,7 @@ if (APPLE) set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-macosx-amd64") set(CPACK_INSTALL_PREFIX "") -elseif (WIN32 AND NOT EXISTS "/etc/debian_version") # Windows +elseif (WIN32 AND (NOT EXISTS "/etc/debian_version")) # Windows set(CPACK_GENERATOR "ZIP") set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-win32") set(CPACK_INSTALL_PREFIX "") @@ -75,6 +75,8 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av # Slackware & Redhat (RPM) ### + set(CPACK_SET_DESTDIR "OFF") + # CPACK_RPM_PACKAGE_SUMMARY --> Default: CPACK_PACKAGE_DESCRIPTION_SUMMARY # CPACK_RPM_PACKAGE_NAME --> Default: CPACK_PACKAGE_NAME @@ -94,6 +96,9 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av # CPACK_RPM_PACKAGE_VENDOR --> Default: CPACK_PACKAGE_VENDOR (as it is set) # CPACK_RPM_PACKAGE_URL --> Default: CMAKE_PROJECT_HOMEPAGE_URL set(CPACK_RPM_PACKAGE_DESCRIPTION CPACK_DEBIAN_PACKAGE_DESCRIPTION) + + ## Add CHANGELOG in rpm-specific format + ### TODO else () # No package configuration on other platforms ... endif () diff --git a/cmake/packaging/deb/copyright b/cmake/packaging/deb/copyright index 4e58490f6..37a101b98 100644 --- a/cmake/packaging/deb/copyright +++ b/cmake/packaging/deb/copyright @@ -34,124 +34,4 @@ Copyright: 2011-2020 stlink-org Jerry Jacobs [xor-gate] [Nightwalker-87] . - Alexey Cherevatenko - Alexey Panarin - Anatoli Klassen [dev26th] - Andrea Mucignat - Andrew Andrianov [necromant] - Andrey Yurovsky - Andy Isaacson - Áron Radics - A. Sheaff - Björn Hauffe - Ihor Bobalo - Breton M. Saunders - Bruno Dal Bo - Burns Fisher - Cheng Guokai (Xim) [chenguokai] - Chris Dew - Chris Hiszpanski - Chris Li - Chris Samuelson - Christian Deussen [nullsub] - Christophe Levantis - Craig Lilley - Dan Dev - Dan Hepler - Daniel Campoverde [alx741] - Daniel O'Connor - Dave Flogeras - Dave Murphy [WinterMute] - Dave Vandervies [dj3vande] - Denis Fokin - Denis Osterland - Dmitry Bravikov [bravikov] - Efe Can İçöz - Ethan Zonca - Fabien Chouteau - Florian Hars - Friedrich Beckmann - Geoffrey Brown - George Talusan [gtalusan] - Georg von Zengen - Giuseppe Barba - Greg Alexander [galexander1] - Greg Meiste [meisteg] - Guillaume Revaillot [grevaillot] - Hakkavélin - Halt Hammerzeit - htk - Ian Griffiths - Jack Peel - Jakub Tyszkowski - Jan Sarenik - Jean-Luc Béchennec - Jean-Marie Lemetayer - Jeff Kent - Jeffrey Nelson - Jens Hoffmann - Jerome Lambourg - Jim Paris - Jiří Netolický - Jerry Nosky [jnosky] - Johannes Taelman - Jonas Danielsson - Jonas Norling - Josh Bialkowski - Karl Palsson [karlp] - Kevlar Harness - Kyle Manna - Lari Lehtomäki - Martin Nowak - Matteo Collina - Max Chen - Maxime Coquelin [mcoquelin-stm32] - Maxime Vincent - Michael Pratt [prattmic] - Michael Sparmann - Mike Szczys - Magnus Lundin [mlu] - mux - Ned Konz - Nic McDonald - Nicolas Schodet - Oleksiy Slyshyk [slyshykO] - Olivier Croquette - Olivier Gay - Onno Kortmann - orangeudav - Pavel Kirienko - Pekka Nikander - Pete Nelson - Peter Zotov - Petteri Aimonen - Piotr Haber - Rene Hopf [rene-dev] - Robin Kreis - Roger Wolff [rewolff] - Rob Spanton - Rytis Karpuska - Sean Simmons - Sergey Alirzaev - Simon Wright - Stany Marcel - Stefan Misik - Sven Wegener - Joel Bodenmann [Tectu] - Tuomo Kaikkonen - Theodore A. Roth - Thomas Gärtner - Tobias Badertscher - Tom de Boer - Tristan Gingold - Uli Köhler - Uwe Bonnes [UweBonnes] - Vadim Kaushan - Vasiliy Glazov [Vascom] - Vegard Storheil Eriksen - Viacheslav Dobromyslov - Victor Mayoral Vilches - William Ransohoff [WRansohoff] - Wojciech A. Koszek - Woodrow Douglass - ... and others + and many others... A list of contributors can be found in "contributors.txt". diff --git a/contributors.txt b/contributors.txt new file mode 100644 index 000000000..32c8e58e3 --- /dev/null +++ b/contributors.txt @@ -0,0 +1,124 @@ +List of contributors to the stlink project: + +Alexey Cherevatenko +Alexey Panarin +Anatoli Klassen [dev26th] +Andrea Mucignat +Andrew Andrianov [necromant] +Andrey Yurovsky +Andy Isaacson +Áron Radics +A. Sheaff +Björn Hauffe +Ihor Bobalo +Breton M. Saunders +Bruno Dal Bo +Burns Fisher +Cheng Guokai (Xim) [chenguokai] +Chris Dew +Chris Hiszpanski +Chris Li +Chris Samuelson +Christian Deussen [nullsub] +Christophe Levantis +Craig Lilley +Dan Dev +Dan Hepler +Daniel Campoverde [alx741] +Daniel O'Connor +Dave Flogeras +Dave Murphy [WinterMute] +Dave Vandervies [dj3vande] +Denis Fokin +Denis Osterland +Dmitry Bravikov [bravikov] +Efe Can İçöz +Ethan Zonca +Fabien Chouteau +Florian Hars +Friedrich Beckmann +Geoffrey Brown +George Talusan [gtalusan] +Georg von Zengen +Giuseppe Barba +Greg Alexander [galexander1] +Greg Meiste [meisteg] +Guillaume Revaillot [grevaillot] +Hakkavélin +Halt Hammerzeit +htk +Ian Griffiths +Jack Peel +Jakub Tyszkowski +Jan Sarenik +Jean-Luc Béchennec +Jean-Marie Lemetayer +Jeff Kent +Jeffrey Nelson +Jens Hoffmann +Jerome Lambourg +Jim Paris +Jiří Netolický +Jerry Nosky [jnosky] +Johannes Taelman +Jonas Danielsson +Jonas Norling +Josh Bialkowski +Karl Palsson [karlp] +Kevlar Harness +Kyle Manna +Lari Lehtomäki +Martin Nowak +Matteo Collina +Max Chen +Maxime Coquelin [mcoquelin-stm32] +Maxime Vincent +Michael Pratt [prattmic] +Michael Sparmann +Mike Szczys +Magnus Lundin [mlu] +mux +Ned Konz +Nic McDonald +Nicolas Schodet +Oleksiy Slyshyk [slyshykO] +Olivier Croquette +Olivier Gay +Onno Kortmann +orangeudav +Pavel Kirienko +Pekka Nikander +Pete Nelson +Peter Zotov +Petteri Aimonen +Piotr Haber +Rene Hopf [rene-dev] +Robin Kreis +Roger Wolff [rewolff] +Rob Spanton +Rytis Karpuska +Sean Simmons +Sergey Alirzaev +Simon Wright +Stany Marcel +Stefan Misik +Sven Wegener +Joel Bodenmann [Tectu] +Tuomo Kaikkonen +Theodore A. Roth +Thomas Gärtner +Tobias Badertscher +Tom de Boer +Tristan Gingold +Uli Köhler +Uwe Bonnes [UweBonnes] +Vadim Kaushan +Vasiliy Glazov [Vascom] +Vegard Storheil Eriksen +Viacheslav Dobromyslov +Victor Mayoral Vilches +William Ransohoff [WRansohoff] +Wojciech A. Koszek +Woodrow Douglass + +... and others From 4c1f5b9575a90178a9f8fd29b64ccbbb00953ec9 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 13 May 2020 12:38:43 +0200 Subject: [PATCH 0926/1435] Update issue templates Added reference to #906 in bug report template --- ...ort--only-valid-if-template-is-reused--.md | 38 +++++++++++++++++++ .github/ISSUE_TEMPLATE/bug-report.md | 6 +-- 2 files changed, 41 insertions(+), 3 deletions(-) create mode 100644 .github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md diff --git a/.github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md b/.github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md new file mode 100644 index 000000000..255596955 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md @@ -0,0 +1,38 @@ +--- +name: Bug Report (only valid if template is reused!) +about: 'Please read #906 before submitting a ticket.' +title: "[STM32 device name]: [Title]" +labels: '' +assignees: '' + +--- + +Thank you for giving feedback to the stlink project. + +In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out each of the following items appropriate to your specific problem: + +- Programmer/board type: [enter here] (e.g Stlink /v1, /v2, /v2-clone, /v2-1) +- Programmer firmware version: [enter here] (e.g STSW-LINK007 2.27.15) +- Operating system and version: [enter here] (e.g Linux, Mac OS X, Windows) +- **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.1.0/git-c722056) +- Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) +- Target chip (and board if applicable): [enter here] (e.g STM32F402VG) + +Futher we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: + +Commandline-Output: + +``` +OUTPUT/ERROR of the commandline tool(s) +``` + +Expected/description: + +`short description of the expected value` + + +**NOTICE: This bug report may be closed without further notice, if not enough information is provided!** + +Thank you for your support. + +The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index 2d565a3f7..344a53ea6 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -1,8 +1,8 @@ --- name: Bug Report -about: Create a report to help us improve -title: "[Your device name]: [Title]" -labels: bug/needs-investigation +about: 'Please read #906 before submitting a ticket.' +title: "[STM32 device name]: [Title]" +labels: '' assignees: '' --- From def770b0c5ea841a69e7828a11baa4c306d2ce6a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 17 May 2020 12:40:45 +0200 Subject: [PATCH 0927/1435] Bugfix & cleanup - Fixed problem "libusb: warning [libusb_exit] application left some devices open" resulting from deprecated commands reintroduced in merge commit 0a91936b263f3fd09a42fb1ec32a72a06d9a39d6. - Whitespace cleanup --- src/mingw/mingw.h | 14 +- src/usb.c | 497 +++++++++++++++++++++------------------------- 2 files changed, 234 insertions(+), 277 deletions(-) diff --git a/src/mingw/mingw.h b/src/mingw/mingw.h index e3a7267a9..8f5b992fe 100644 --- a/src/mingw/mingw.h +++ b/src/mingw/mingw.h @@ -37,7 +37,7 @@ struct pollfd { short revents; /* returned events */ }; #endif -#define poll(x, y, z) win32_poll(x, y, z) +#define poll(x, y, z) win32_poll(x, y, z) /* These wrappers do nothing special except set the global errno variable if * an error occurs (winsock doesn't do this by default). They set errno @@ -45,12 +45,12 @@ struct pollfd { * outside of this file "shouldn't" have to worry about winsock specific error * handling. */ -#define socket(x, y, z) win32_socket(x, y, z) -#define connect(x, y, z) win32_connect(x, y, z) -#define accept(x, y, z) win32_accept(x, y, z) -#define shutdown(x, y) win32_shutdown(x, y) -#define read(x, y, z) win32_read_socket(x, y, z) -#define write(x, y, z) win32_write_socket(x, y, z) +#define socket(x, y, z) win32_socket(x, y, z) +#define connect(x, y, z) win32_connect(x, y, z) +#define accept(x, y, z) win32_accept(x, y, z) +#define shutdown(x, y) win32_shutdown(x, y) +#define read(x, y, z) win32_read_socket(x, y, z) +#define write(x, y, z) win32_write_socket(x, y, z) /* Winsock uses int instead of the usual socklen_t */ typedef int socklen_t; diff --git a/src/usb.c b/src/usb.c index 3445a7464..fcb2e1b30 100644 --- a/src/usb.c +++ b/src/usb.c @@ -17,13 +17,11 @@ enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; -static inline uint32_t le_to_h_u32(const uint8_t* buf) -{ +static inline uint32_t le_to_h_u32(const uint8_t* buf) { return (uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24); } -static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, uint32_t khz) -{ +static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, uint32_t khz) { unsigned int i; int speed_index = -1; int speed_diff = INT_MAX; @@ -31,59 +29,51 @@ static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, u bool match = true; for (i = 0; i < map_size; i++) { - if (!map[i]) - continue; - last_valid_speed = i; - if (khz == map[i]) { - speed_index = i; - break; - } else { - int current_diff = khz - map[i]; - /* get abs value for comparison */ - current_diff = (current_diff > 0) ? current_diff : -current_diff; - if ((current_diff < speed_diff) && khz >= map[i]) { - speed_diff = current_diff; - speed_index = i; - } - } + if (!map[i]) continue; + last_valid_speed = i; + if (khz == map[i]) { + speed_index = i; + break; + } else { + int current_diff = khz - map[i]; + // Get abs value for comparison + current_diff = (current_diff > 0) ? current_diff : -current_diff; + if ((current_diff < speed_diff) && khz >= map[i]) { + speed_diff = current_diff; + speed_index = i; + } + } } if (speed_index == -1) { - /* this will only be here if we cannot match the slow speed. - * use the slowest speed we support.*/ - speed_index = last_valid_speed; - match = false; - } else if (i == map_size) - match = false; - + // This will only be here if we cannot match the slow speed. Use the slowest speed we support. + speed_index = last_valid_speed; + match = false; + } else if (i == map_size) { + match = false; + } if (!match) { - ILOG("Unable to match requested speed %d kHz, using %d kHz\n", \ - khz, map[speed_index]); + ILOG("Unable to match requested speed %d kHz, using %d kHz\n", khz, map[speed_index]); } return speed_index; } void _stlink_usb_close(stlink_t* sl) { - if (!sl) - return; + if (!sl) return; struct stlink_libusb * const handle = sl->backend_data; - // maybe we couldn't even get the usb device? + // Maybe we couldn't even get the usb device? if (handle != NULL) { - if (handle->usb_handle != NULL) { - libusb_close(handle->usb_handle); - } - + if (handle->usb_handle != NULL) libusb_close(handle->usb_handle); libusb_exit(handle->libusb_ctx); free(handle); } } ssize_t send_recv(struct stlink_libusb* handle, int terminate, - unsigned char* txbuf, size_t txsize, - unsigned char* rxbuf, size_t rxsize) { - /* note: txbuf and rxbuf can point to the same area */ + unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, size_t rxsize) { + /* Note: txbuf and rxbuf can point to the same area */ int res = 0; int t; @@ -93,43 +83,39 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, return -1; } else if ((size_t)res != txsize) { printf("[!] send_recv send request wrote %u bytes (instead of %u).\n", - (unsigned int)res, (unsigned int)txsize); + (unsigned int)res, (unsigned int)txsize); } if (rxsize != 0) { t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int) rxsize, &res, 3000); if (t) { - printf("[!] send_recv read reply failed: %s\n", - libusb_error_name(t)); + printf("[!] send_recv read reply failed: %s\n", libusb_error_name(t)); return -1; } } if ((handle->protocoll == 1) && terminate) { - /* Read the SG reply */ + // Read the SG reply unsigned char sg_buf[13]; t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); if (t) { - printf("[!] send_recv read storage failed: %s\n", - libusb_error_name(t)); + printf("[!] send_recv read storage failed: %s\n", libusb_error_name(t)); return -1; } - /* The STLink doesn't seem to evaluate the sequence number */ + // The STLink doesn't seem to evaluate the sequence number. handle->sg_transfer_idx++; } return res; } -static inline int send_only -(struct stlink_libusb* handle, int terminate, - unsigned char* txbuf, size_t txsize) { +static inline int send_only(struct stlink_libusb* handle, int terminate, + unsigned char* txbuf, size_t txsize) { return (int) send_recv(handle, terminate, txbuf, txsize, NULL, 0); } -static int fill_command -(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t len) { +static int fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t len) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; int i = 0; @@ -142,9 +128,9 @@ static int fill_command write_uint32(&cmd[i], slu->sg_transfer_idx); write_uint32(&cmd[i + 4], len); i += 8; - cmd[i++] = (dir == SG_DXFER_FROM_DEV)?0x80:0; - cmd[i++] = 0; /* Logical unit */ - cmd[i++] = 0xa; /* Command length */ + cmd[i++] = (dir == SG_DXFER_FROM_DEV) ? 0x80 : 0; + cmd[i++] = 0; // Logical unit + cmd[i++] = 0xa; // Command length } return i; } @@ -226,6 +212,7 @@ int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { return (int) size; } *data = read_uint32(rdata, 4); + return 0; } @@ -250,10 +237,8 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { return 0; } -int _stlink_usb_get_rw_status(stlink_t *sl) -{ - if (sl->version.jtag_api == STLINK_JTAG_API_V1) - return -1; +int _stlink_usb_get_rw_status(stlink_t *sl) { + if (sl->version.jtag_api == STLINK_JTAG_API_V1) return -1; unsigned char* const rdata = sl->q_buf; struct stlink_libusb * const slu = sl->backend_data; @@ -270,8 +255,8 @@ int _stlink_usb_get_rw_status(stlink_t *sl) cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS; ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2); } - if (ret < 0) - return -1; + if (ret < 0) return -1; + return 0; } @@ -287,11 +272,9 @@ int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); ret = send_only(slu, 0, cmd, slu->cmd_len); - if (ret == -1) - return ret; + if (ret == -1) return ret; ret = send_only(slu, 0, data, len); - if (ret == -1) - return ret; + if (ret == -1) return ret; return _stlink_usb_get_rw_status(sl); } @@ -308,12 +291,9 @@ int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); ret = send_only(slu, 0, cmd, slu->cmd_len); - if (ret == -1) - return ret; - + if (ret == -1) return ret; ret = send_only(slu, 1, data, len); - if (ret == -1) - return ret; + if (ret == -1) return ret; return 0; } @@ -333,6 +313,7 @@ int _stlink_usb_current_mode(stlink_t * sl) { printf("[!] send_recv STLINK_GET_CURRENT_MODE\n"); return -1; } + return sl->q_buf[0]; } @@ -345,21 +326,22 @@ int _stlink_usb_core_id(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - if (sl->version.jtag_api == STLINK_JTAG_API_V1) + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { cmd[i++] = STLINK_DEBUG_READCOREID; - else + } else { cmd[i++] = STLINK_DEBUG_APIV2_READ_IDCODES; - + } size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv STLINK_DEBUG_READCOREID\n"); return -1; } - if (sl->version.jtag_api == STLINK_JTAG_API_V1) + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { sl->core_id = read_uint32(data, 0); - else + } else { sl->core_id = read_uint32(data, 4); + } return 0; } int _stlink_usb_status_v2(stlink_t *sl) @@ -385,9 +367,7 @@ int _stlink_usb_status_v2(stlink_t *sl) } int _stlink_usb_status(stlink_t * sl) { - if (sl->version.jtag_api != STLINK_JTAG_API_V1) { - return _stlink_usb_status_v2(sl); - } + if (sl->version.jtag_api != STLINK_JTAG_API_V1) return _stlink_usb_status_v2(sl); struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; @@ -398,7 +378,6 @@ int _stlink_usb_status(stlink_t * sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_GETSTATUS; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv STLINK_DEBUG_GETSTATUS\n"); @@ -445,7 +424,7 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - // Select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30) + // Select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). cmd[i++] = sl->version.jtag_api == STLINK_JTAG_API_V1 ? STLINK_DEBUG_APIV1_ENTER : STLINK_DEBUG_APIV2_ENTER; cmd[i++] = STLINK_DEBUG_ENTER_SWD; @@ -455,8 +434,8 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); } if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_ENTER\n"); - return (int) size; + printf("[!] send_recv STLINK_DEBUG_ENTER\n"); + return (int) size; } return 0; @@ -470,7 +449,6 @@ int _stlink_usb_exit_dfu_mode(stlink_t* sl) { cmd[i++] = STLINK_DFU_COMMAND; cmd[i++] = STLINK_DFU_EXIT; - size = send_only(slu, 1, cmd, slu->cmd_len); if (size == -1) { printf("[!] send_recv STLINK_DFU_EXIT\n"); @@ -490,10 +468,11 @@ int _stlink_usb_reset(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - if (sl->version.jtag_api == STLINK_JTAG_API_V1) + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { cmd[i++] = STLINK_DEBUG_APIV1_RESETSYS; - else + } else { cmd[i++] = STLINK_DEBUG_APIV2_RESETSYS; + } size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { @@ -501,12 +480,11 @@ int _stlink_usb_reset(stlink_t * sl) { return (int) size; } - // Reset through AIRCR so NRST does not need to be connected - return stlink_write_debug32(sl, STLINK_REG_AIRCR, - STLINK_REG_AIRCR_VECTKEY | STLINK_REG_AIRCR_SYSRESETREQ); + // Reset through AIRCR so that NRST does not need to be connected. + return stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ); } - int _stlink_usb_jtag_reset(stlink_t * sl, int value) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; @@ -518,7 +496,6 @@ int _stlink_usb_jtag_reset(stlink_t * sl, int value) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_JTAG_DRIVE_NRST; cmd[i++] = value; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv STLINK_JTAG_DRIVE_NRST\n"); @@ -539,7 +516,6 @@ int _stlink_usb_step(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_STEPCORE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv STLINK_DEBUG_STEPCORE\n"); @@ -557,6 +533,7 @@ int _stlink_usb_run(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; int res; + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { res = _stlink_usb_write_debug32(sl, DCB_DHCSR, DBGKEY|C_DEBUGEN); return res; @@ -571,7 +548,6 @@ int _stlink_usb_run(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_RUNCORE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv STLINK_DEBUG_RUNCORE\n"); @@ -589,6 +565,7 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { ssize_t size; int rep_len = 2; int i; + // clock speed only supported by stlink/v2 and for firmware >= 22 if (sl->version.stlink_v == 2 && sl->version.jtag_v >= 22) { i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); @@ -597,7 +574,6 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { cmd[i++] = STLINK_DEBUG_APIV2_SWD_SET_FREQ; cmd[i++] = clk_divisor & 0xFF; cmd[i++] = (clk_divisor >> 8) & 0xFF; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv STLINK_DEBUG_APIV2_SWD_SET_FREQ\n"); @@ -613,7 +589,6 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_APIV3_GET_COM_FREQ; cmd[i++] = 0; // SWD mode - size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52); if (size == -1) { printf("[!] send_recv STLINK_APIV3_GET_COM_FREQ\n"); @@ -622,15 +597,12 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { int speeds_size = data[8]; - if (speeds_size > STLINK_V3_MAX_FREQ_NB) - speeds_size = STLINK_V3_MAX_FREQ_NB; + if (speeds_size > STLINK_V3_MAX_FREQ_NB) speeds_size = STLINK_V3_MAX_FREQ_NB; - for (i = 0; i < speeds_size; i++) - map[i] = le_to_h_u32(&data[12 + 4 * i]); + for (i = 0; i < speeds_size; i++) map[i] = le_to_h_u32(&data[12 + 4 * i]); - /* set to zero all the next entries */ - for (i = speeds_size; i < STLINK_V3_MAX_FREQ_NB; i++) - map[i] = 0; + // Set to zero all the next entries + for (i = speeds_size; i < STLINK_V3_MAX_FREQ_NB; i++) map[i] = 0; speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), 1800); @@ -685,16 +657,16 @@ int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { cmd[i++] = STLINK_DEBUG_READMEM_32BIT; write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_READMEM_32BIT\n"); return (int) size; } sl->q_len = (int) size; - stlink_print_data(sl); + return 0; } @@ -707,11 +679,15 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - if (sl->version.jtag_api == STLINK_JTAG_API_V1) + + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { cmd[i++] = STLINK_DEBUG_APIV1_READALLREGS; - else + } else { cmd[i++] = STLINK_DEBUG_APIV2_READALLREGS; + } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_READALLREGS\n"); return (int) size; @@ -722,15 +698,15 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; sl->q_len = (int) size; stlink_print_data(sl); - for(i=reg_offset; i<16; i++) - regp->r[i]= read_uint32(sl->q_buf, i*4); + + for(i=reg_offset; i<16; i++) regp->r[i]= read_uint32(sl->q_buf, i*4); regp->xpsr = read_uint32(sl->q_buf, reg_offset + 64); regp->main_sp = read_uint32(sl->q_buf, reg_offset + 68); regp->process_sp = read_uint32(sl->q_buf, reg_offset + 72); regp->rw = read_uint32(sl->q_buf, reg_offset + 76); regp->rw2 = read_uint32(sl->q_buf, reg_offset + 80); - if (sl->verbose < 2) - return 0; + + if (sl->verbose < 2) return 0; DLOG("xpsr = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 64)); DLOG("main_sp = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 68)); @@ -752,16 +728,21 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - if (sl->version.jtag_api == STLINK_JTAG_API_V1) + + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { cmd[i++] = STLINK_DEBUG_APIV1_READREG; - else + } else { cmd[i++] = STLINK_DEBUG_APIV2_READREG; + } + cmd[i++] = (uint8_t) r_idx; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_READREG\n"); return (int) size; } + sl->q_len = (int) size; stlink_print_data(sl); r = read_uint32(sl->q_buf, reg_offset); @@ -778,10 +759,10 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { regp->process_sp = r; break; case 19: - regp->rw = r; /* XXX ?(primask, basemask etc.) */ + regp->rw = r; // XXX ?(primask, basemask etc.) break; case 20: - regp->rw2 = r; /* XXX ?(primask, basemask etc.) */ + regp->rw2 = r; // XXX ?(primask, basemask etc.) break; default: regp->r[r_idx] = r; @@ -796,34 +777,30 @@ int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg int ret; sl->q_buf[0] = (unsigned char) r_idx; - for (int i = 1; i < 4; i++) { - sl->q_buf[i] = 0; - } + for (int i = 1; i < 4; i++) sl->q_buf[i] = 0; ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); - if (ret == -1) - return ret; + if (ret == -1) return ret; ret = _stlink_usb_read_mem32(sl, STLINK_REG_DCRDR, 4); - if (ret == -1) - return ret; + if (ret == -1) return ret; r = read_uint32(sl->q_buf, 0); DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); switch (r_idx) { - case 0x14: - regp->primask = (uint8_t) (r & 0xFF); - regp->basepri = (uint8_t) ((r>>8) & 0xFF); - regp->faultmask = (uint8_t) ((r>>16) & 0xFF); - regp->control = (uint8_t) ((r>>24) & 0xFF); - break; - case 0x21: - regp->fpscr = r; - break; - default: - regp->s[r_idx - 0x40] = r; - break; + case 0x14: + regp->primask = (uint8_t) (r & 0xFF); + regp->basepri = (uint8_t) ((r>>8) & 0xFF); + regp->faultmask = (uint8_t) ((r>>16) & 0xFF); + regp->control = (uint8_t) ((r>>24) & 0xFF); + break; + case 0x21: + regp->fpscr = r; + break; + default: + regp->s[r_idx - 0x40] = r; + break; } return 0; @@ -833,17 +810,14 @@ int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) int ret; ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); - if (ret == -1) - return ret; + if (ret == -1) return ret; ret = _stlink_usb_read_unsupported_reg(sl, 0x21, regp); - if (ret == -1) - return ret; + if (ret == -1) return ret; for (int i = 0; i < 32; i++) { ret = _stlink_usb_read_unsupported_reg(sl, 0x40+i, regp); - if (ret == -1) - return ret; + if (ret == -1) return ret; } return 0; @@ -856,24 +830,35 @@ int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, str if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ /* These are held in the same register */ ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); - if (ret == -1) - return ret; + if (ret == -1) return ret; val = (uint8_t) (val>>24); switch (r_idx) { - case 0x1C: /* control */ - val = (((uint32_t) val) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) regp->primask); - break; - case 0x1D: /* faultmask */ - val = (((uint32_t) regp->control) << 24) | (((uint32_t) val) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) regp->primask); - break; - case 0x1E: /* basepri */ - val = (((uint32_t) regp->control) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) val) << 8) | ((uint32_t) regp->primask); - break; - case 0x1F: /* primask */ - val = (((uint32_t) regp->control) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) val); - break; + case 0x1C: /* control */ + val = (((uint32_t) val) << 24) | + (((uint32_t) regp->faultmask) << 16) | + (((uint32_t) regp->basepri) << 8) | + ((uint32_t) regp->primask); + break; + case 0x1D: /* faultmask */ + val = (((uint32_t) regp->control) << 24) | + (((uint32_t) val) << 16) | + (((uint32_t) regp->basepri) << 8) | + ((uint32_t) regp->primask); + break; + case 0x1E: /* basepri */ + val = (((uint32_t) regp->control) << 24) | + (((uint32_t) regp->faultmask) << 16) | + (((uint32_t) val) << 8) | + ((uint32_t) regp->primask); + break; + case 0x1F: /* primask */ + val = (((uint32_t) regp->control) << 24) | + (((uint32_t) regp->faultmask) << 16) | + (((uint32_t) regp->basepri) << 8) | + ((uint32_t) val); + break; } r_idx = 0x14; @@ -882,8 +867,7 @@ int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, str write_uint32(sl->q_buf, val); ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRDR, 4); - if (ret == -1) - return ret; + if (ret == -1) return ret; sl->q_buf[0] = (unsigned char) r_idx; sl->q_buf[1] = 0; @@ -902,13 +886,17 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - if (sl->version.jtag_api == STLINK_JTAG_API_V1) + + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { cmd[i++] = STLINK_DEBUG_APIV1_WRITEREG; - else + } else { cmd[i++] = STLINK_DEBUG_APIV2_WRITEREG; + } + cmd[i++] = idx; write_uint32(&cmd[i], reg); size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_WRITEREG\n"); return (int) size; @@ -949,8 +937,7 @@ static stlink_backend_t _stlink_usb_backend = { _stlink_usb_set_swdclk }; -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq) -{ +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; int ret = -1; @@ -958,10 +945,9 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST sl = calloc(1, sizeof (stlink_t)); slu = calloc(1, sizeof (struct stlink_libusb)); - if (sl == NULL) - goto on_malloc_error; - if (slu == NULL) - goto on_malloc_error; + + if (sl == NULL) goto on_malloc_error; + if (slu == NULL) goto on_malloc_error; ugly_init(verbose); sl->backend = &_stlink_usb_backend; @@ -980,81 +966,66 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST #endif libusb_device **list; - /** @todo We should use ssize_t and use it as a counter if > 0. As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) */ + /* @TODO: We should use ssize_t and use it as a counter if > 0. + * As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) + */ int cnt = (int) libusb_get_device_list(slu->libusb_ctx, &list); struct libusb_device_descriptor desc; - int devBus =0; - int devAddr=0; - - /* @TODO: Reading a environment variable in a usb open function is not very nice, this - should be refactored and moved into the CLI tools, and instead of giving USB_BUS:USB_ADDR a real stlink - serial string should be passed to this function. Probably people are using this but this is very odd because - as programmer can change to multiple busses and it is better to detect them based on serial. */ + int devBus = 0; + int devAddr = 0; + + /* @TODO: Reading a environment variable in a usb open function is not very nice, this should be refactored + * and moved into the CLI tools, and instead of giving USB_BUS:USB_ADDR a real stlink serial string should + * be passed to this function. Probably people are using this but this is very odd because as programmer + * can change to multiple busses and it is better to detect them based on serial. + */ char *device = getenv("STLINK_DEVICE"); if (device) { char *c = strchr(device,':'); - if (c==NULL) { + if (c == NULL) { WLOG("STLINK_DEVICE must be : format\n"); goto on_error; } - devBus=atoi(device); - *c++=0; - devAddr=atoi(c); + devBus = atoi(device); + *c++ = 0; + devAddr = atoi(c); ILOG("bus %03d dev %03d\n",devBus, devAddr); } while (cnt--) { - struct libusb_device_handle *handle; + struct libusb_device_handle *handle; - libusb_get_device_descriptor( list[cnt], &desc ); - if (desc.idVendor != STLINK_USB_VID_ST) - continue; + libusb_get_device_descriptor(list[cnt], &desc); + if (desc.idVendor != STLINK_USB_VID_ST) continue; if (devBus && devAddr) { - if ((libusb_get_bus_number(list[cnt]) != devBus) - || (libusb_get_device_address(list[cnt]) != devAddr)) { + if ((libusb_get_bus_number(list[cnt]) != devBus) || (libusb_get_device_address(list[cnt]) != devAddr)) { continue; } } - ret = libusb_open(list[cnt], &handle); + ret = libusb_open(list[cnt], &handle); + if (ret) continue; // could not open device - /* could not open device, continue */ - if (ret) - continue; + sl->serial_size = libusb_get_string_descriptor_ascii( + handle, desc.iSerialNumber, (unsigned char *)sl->serial, sizeof(sl->serial)); + libusb_close(handle); - sl->serial_size = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, - (unsigned char *)sl->serial, sizeof(sl->serial)); - - if ((serial == NULL) || (*serial == 0)) - break; - - if (sl->serial_size < 0) - continue; + if (sl->serial_size < 0) continue; // could not read serial - if (memcmp(serial, &sl->serial, sl->serial_size) == 0) + // if no serial provided, or if serial match device, fixup version and protocol + if (((serial == NULL) || (*serial == 0)) || (memcmp(serial, &sl->serial, sl->serial_size) == 0)) { + if (STLINK_V1_USB_PID(desc.idProduct)) { + slu->protocoll = 1; + sl->version.stlink_v = 1; + } else if (STLINK_V2_USB_PID(desc.idProduct) || STLINK_V2_1_USB_PID(desc.idProduct)) { + sl->version.stlink_v = 2; + } else if (STLINK_V3_USB_PID(desc.idProduct)) { + sl->version.stlink_v = 3; + } break; - - libusb_close(handle); - - /* could not read serial, continue */ - if (sl->serial_size < 0) - continue; - - /* if no serial provided, or if serial match device, fixup version and protocol */ - if (((serial == NULL) || (*serial == 0)) || (memcmp(serial, &sl->serial, sl->serial_size) == 0)) { - if (STLINK_V1_USB_PID(desc.idProduct)) { - slu->protocoll = 1; - sl->version.stlink_v = 1; - } else if (STLINK_V2_USB_PID(desc.idProduct) || STLINK_V2_1_USB_PID(desc.idProduct)) { - sl->version.stlink_v = 2; - } else if (STLINK_V3_USB_PID(desc.idProduct)) { - sl->version.stlink_v = 3; - } - - break; - } + } } if (cnt < 0) { @@ -1063,8 +1034,8 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST } else { ret = libusb_open(list[cnt], &slu->usb_handle); if (ret != 0) { - WLOG("Error %d (%s) opening ST-Link v%d device %03d:%03d\n", - ret, strerror (errno), sl->version.stlink_v, libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); + WLOG("Error %d (%s) opening ST-Link v%d device %03d:%03d\n", ret, strerror (errno), + sl->version.stlink_v, libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); libusb_free_device_list(list, 1); goto on_error; } @@ -1130,10 +1101,9 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST stlink_exit_dfu_mode(sl); } - sl->freq = freq; - // set the speed before entering the mode - // as the chip discovery phase should be done at this speed too + // set the speed before entering the mode as the chip discovery phase + // should be done at this speed too // Set the stlink clock speed (default is 1800kHz) DLOG("JTAG/SWD freq set to %d\n", freq); switch (freq) { @@ -1174,38 +1144,29 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST stlink_set_swdclk(sl, STLINK_SWDCLK_4MHZ_DIVISOR); break; } - - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { - stlink_enter_swd_mode(sl); - } + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); if (reset) { - if ( sl->version.stlink_v > 1)stlink_jtag_reset(sl, 2); + if ( sl->version.stlink_v > 1) stlink_jtag_reset(sl, 2); stlink_reset(sl); usleep(10000); } stlink_load_device_params(sl); - return sl; -on_libusb_error: - stlink_close(sl); - return NULL; + on_libusb_error: + stlink_close(sl); + return NULL; + on_error: + if (slu->libusb_ctx) libusb_exit(slu->libusb_ctx); -on_error: - if (slu->libusb_ctx) - libusb_exit(slu->libusb_ctx); - -on_malloc_error: - if (sl != NULL) - free(sl); - if (slu != NULL) - free(slu); - - return NULL; + on_malloc_error: + if (sl != NULL) free(sl); + if (slu != NULL) free(slu); + return NULL; } static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { @@ -1219,18 +1180,19 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { while ((dev = devs[i++]) != NULL) { struct libusb_device_descriptor desc; int ret = libusb_get_device_descriptor(dev, &desc); + if (ret < 0) { WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); break; } - if (desc.idVendor != STLINK_USB_VID_ST) - continue; + if (desc.idVendor != STLINK_USB_VID_ST) continue; + + if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { + WLOG("skipping ST device : %#04x:%#04x)\n", desc.idVendor, desc.idProduct); + continue; + } - if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { - WLOG("skipping ST device : %#04x:%#04x)\n", desc.idVendor, desc.idProduct); - continue; - } slcnt++; } @@ -1246,45 +1208,44 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { while ((dev = devs[i++]) != NULL) { struct libusb_device_descriptor desc; int ret = libusb_get_device_descriptor(dev, &desc); + if (ret < 0) { WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); break; } - if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { - continue; - } + if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) continue; - struct libusb_device_handle* handle; + struct libusb_device_handle* handle; char serial[STLINK_SERIAL_MAX_SIZE] = {0,}; - ret = libusb_open(dev, &handle); - if (ret < 0) { - if (ret == LIBUSB_ERROR_ACCESS) { - ELOG("Could not open USB device %#06x:%#06x, access error.\n", desc.idVendor, desc.idProduct, ret); - } else { - ELOG("Failed to open USB device %#06x:%#06x, libusb error: %d)\n", desc.idVendor, desc.idProduct, ret); - } - break; - } - ret = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)&serial, sizeof(serial)); + ret = libusb_open(dev, &handle); + + if (ret < 0) { + if (ret == LIBUSB_ERROR_ACCESS) { + ELOG("Could not open USB device %#06x:%#06x, access error.\n", desc.idVendor, desc.idProduct, ret); + } else { + ELOG("Failed to open USB device %#06x:%#06x, libusb error: %d)\n", desc.idVendor, desc.idProduct, ret); + } + break; + } + ret = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)&serial, sizeof(serial)); - libusb_close(handle); + libusb_close(handle); - if (ret < 0) { - continue; - } + if (ret < 0) continue; stlink_t *sl = stlink_open_usb(0, 1, serial, 0); if (!sl) { ELOG("Failed to open USB device %#06x:%#06x\n", desc.idVendor, desc.idProduct); continue; - } + } _sldevs[slcur++] = sl; } *sldevs = _sldevs; + return slcur; } @@ -1297,12 +1258,10 @@ size_t stlink_probe_usb(stlink_t **stdevs[]) { ssize_t cnt; r = libusb_init(NULL); - if (r < 0) - return 0; + if (r < 0) return 0; cnt = libusb_get_device_list(NULL, &devs); - if (cnt < 0) - return 0; + if (cnt < 0) return 0; slcnt = stlink_probe_usb_devs(devs, &sldevs); libusb_free_device_list(devs, 1); @@ -1310,15 +1269,13 @@ size_t stlink_probe_usb(stlink_t **stdevs[]) { libusb_exit(NULL); *stdevs = sldevs; + return slcnt; } void stlink_probe_usb_free(stlink_t ***stdevs, size_t size) { - if (stdevs == NULL || *stdevs == NULL || size == 0) - return; - - for (size_t n = 0; n < size; n++) - stlink_close((*stdevs)[n]); + if (stdevs == NULL || *stdevs == NULL || size == 0) return; + for (size_t n = 0; n < size; n++) stlink_close((*stdevs)[n]); free(*stdevs); *stdevs = NULL; } From e3aa887f7ffdfcfb3a0529ee3b94a7d3fe39b5d8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 18 May 2020 00:49:08 +0200 Subject: [PATCH 0928/1435] Update for library linking - Simplified code - Added version info for static library --- CMakeLists.txt | 41 ++++++++++++++++++++++++----------------- Makefile | 3 ++- 2 files changed, 26 insertions(+), 18 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index b5301fb0a..57a9161e7 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -19,11 +19,11 @@ set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics ST-LINK T include(GNUInstallDirs) # Define GNU standard installation directories set(STLINK_UDEV_RULES_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/udev/rules.d" CACHE PATH "udev rules directory") -set(STLINK_MODPROBED_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/modprobe.d" CACHE PATH "modprobe.d directory") -set(STLINK_STATIC_LIB ON CACHE BOOL "Install static lib") - option(STLINK_INSTALL_UDEV_RULES "Install udev rules files" ON) + +set(STLINK_MODPROBED_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/modprobe.d" CACHE PATH "modprobe.d directory") option(STLINK_INSTALL_MODPROBE_CONF "Install modprobe conf files" ON) + option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) ## Determine project version @@ -186,16 +186,14 @@ set_target_properties( VERSION ${STLINK_SHARED_VERSION} ) -# Link shared library with Apple macOS libraries -if (APPLE) +# Link shared library +if (APPLE) # ... with Apple macOS libraries find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) find_library(IOKit IOKit) - target_link_libraries(${STLINK_LIB_SHARED} ${CoreFoundation} ${IOKit} ${ObjC} ${SSP_LIB}) -endif () - -if (WIN32 OR MINGW OR MSYS) - target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} wsock32 ws2_32 ${SSP_LIB}) + target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB} ${ObjC} ${CoreFoundation} ${IOKit}) +elseif (WIN32) # ... with Windows libraries + target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB} wsock32 ws2_32) else () target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB}) endif () @@ -207,6 +205,9 @@ install(TARGETS ${STLINK_LIB_SHARED} DESTINATION ${STLINK_LIBRARY_PATH}) # Static library ### +# Install static library per default +set(STLINK_STATIC_LIB ON CACHE BOOL "Install static lib") + set(STLINK_LIB_STATIC ${PROJECT_NAME}-static) add_library( @@ -215,21 +216,27 @@ add_library( ${STLINK_SOURCE} ) +set(STLINK_STATIC_VERSION ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}) + +message(STATUS "STLINK_LIB_STATIC: ${STLINK_LIB_STATIC}") +message(STATUS "PROJECT_VERSION_MAJOR: ${PROJECT_VERSION_MAJOR}") +message(STATUS "VERSION: ${STLINK_STATIC_VERSION}") + set_target_properties( ${STLINK_LIB_STATIC} PROPERTIES + SOVERSION ${PROJECT_VERSION_MAJOR} + VERSION ${STLINK_STATIC_VERSION} OUTPUT_NAME ${PROJECT_NAME} ) -# Link static library with Apple macOS libraries -if (APPLE) +# Link static library +if (APPLE) # ... with Apple macOS libraries find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) find_library(IOKit IOKit) - target_link_libraries(${STLINK_LIB_STATIC} ${CoreFoundation} ${IOKit} ${ObjC} ${SSP_LIB}) -endif () - -if (WIN32 OR MINGW OR MSYS) - target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} wsock32 ws2_32 ${SSP_LIB}) + target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB} ${ObjC} ${CoreFoundation} ${IOKit}) +elseif (WIN32) # ... with Windows libraries + target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB} wsock32 ws2_32) else () target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB}) endif () diff --git a/Makefile b/Makefile index 7f373ebcd..3f46d2943 100644 --- a/Makefile +++ b/Makefile @@ -1,6 +1,7 @@ ## -# This Makefile is used to drive building of Debug and Release targets of CMake +# This Makefile is used to drive building of CMake build targets ## + MAKEFLAGS += -s # additional flags for cmake, e.g. install path -DCMAKE_INSTALL_PREFIX=$(HOME)/.local From d73f864a375287ed93efaedd87a106a378c91d12 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Mon, 18 May 2020 11:53:58 +0800 Subject: [PATCH 0929/1435] Fix some uninitialized variables --- src/flash_loader.c | 2 +- src/usb.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/flash_loader.c b/src/flash_loader.c index 6862d493c..20a2bdc73 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -191,7 +191,7 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { - size_t size; + size_t size = 0; /* allocate the loader in sram */ if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { diff --git a/src/usb.c b/src/usb.c index fcb2e1b30..b986aed57 100644 --- a/src/usb.c +++ b/src/usb.c @@ -347,7 +347,7 @@ int _stlink_usb_core_id(stlink_t * sl) { int _stlink_usb_status_v2(stlink_t *sl) { int result; - uint32_t status; + uint32_t status = 0; result = _stlink_usb_read_debug32(sl, DCB_DHCSR, &status); DLOG("core status: %08X\n", status); From f8ef21cd130c2ad6460c375747be5987112c4703 Mon Sep 17 00:00:00 2001 From: Chen Guokai Date: Mon, 18 May 2020 11:58:31 +0800 Subject: [PATCH 0930/1435] Fix issue 958, move F0 flashloader nops to assembly --- flashloaders/stm32f0.s | 14 ++++++++++++++ src/flash_loader.c | 19 ++----------------- 2 files changed, 16 insertions(+), 17 deletions(-) diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s index 6c4b8588f..cbb932b49 100644 --- a/flashloaders/stm32f0.s +++ b/flashloaders/stm32f0.s @@ -3,6 +3,20 @@ .global copy copy: + /* + * These two NOPs here are a safety precaution, added by Pekka Nikander + * while debugging the STM32F05x support. They may not be needed, but + * there were strange problems with simpler programs, like a program + * that had just a breakpoint or a program that first moved zero to register r2 + * and then had a breakpoint. So, it appears safest to have these two nops. + * + * Feel free to remove them, if you dare, but then please do test the result + * rigorously. Also, if you remove these, it may be a good idea first to + * #if 0 them out, with a comment when these were taken out, and to remove + * these only a few months later... But YMMV. + */ + nop + nop ldr r7, =flash_base ldr r4, [r7] ldr r7, =flash_off_cr diff --git a/src/flash_loader.c b/src/flash_loader.c index 20a2bdc73..a2c5879ce 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -41,22 +41,7 @@ /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ static const uint8_t loader_code_stm32f0[] = { -#if 1 - /* - * These two NOPs here are a safety precaution, added by Pekka Nikander - * while debugging the STM32F05x support. They may not be needed, but - * there were strange problems with simpler programs, like a program - * that had just a breakpoint or a program that first moved zero to register r2 - * and then had a breakpoint. So, it appears safest to have these two nops. - * - * Feel free to remove them, if you dare, but then please do test the result - * rigorously. Also, if you remove these, it may be a good idea first to - * #if 0 them out, with a comment when these were taken out, and to remove - * these only a few months later... But YMMV. - */ - 0x00, 0x30, // nop /* add r0,#0 */ - 0x00, 0x30, // nop /* add r0,#0 */ -#endif + 0xc0, 0x46, 0xc0, 0x46, 0x13, 0x4f, 0x3c, 0x68, 0x13, 0x4f, 0x3e, 0x68, 0x36, 0x19, 0x13, 0x4f, @@ -77,9 +62,9 @@ 0x00, 0x20, 0x02, 0x40, 0x10, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, - 0x44, 0x00, 0x00, 0x20, 0x48, 0x00, 0x00, 0x20, 0x4c, 0x00, 0x00, 0x20, + 0x50, 0x00, 0x00, 0x20, 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00 From 97d3173f480db33c770ef2c66a002d708b139fa0 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 18 May 2020 15:13:36 +0200 Subject: [PATCH 0931/1435] Updated package & install configuration - Added package changelog files for deb & rpm - Added license file for deb pkg - Added rules file for deb pkg - Changed install subdirectory --- .travis.sh | 32 ++-- CMakeLists.txt | 6 +- cmake/packaging/cpack_config.cmake | 26 ++-- cmake/packaging/deb/changelog | 237 ++++------------------------- cmake/packaging/deb/control | 9 ++ cmake/packaging/deb/copyright | 16 +- cmake/packaging/deb/rules | 2 +- cmake/packaging/rpm/changelog | 2 + mingw64-build.bat | 2 +- 9 files changed, 85 insertions(+), 247 deletions(-) create mode 100644 cmake/packaging/deb/control create mode 100644 cmake/packaging/rpm/changelog diff --git a/.travis.sh b/.travis.sh index e61098f89..3bab4c5d0 100755 --- a/.travis.sh +++ b/.travis.sh @@ -12,17 +12,17 @@ if [ "$TRAVIS_JOB_NAME" == "linux-mingw" ]; then echo "--> Building Release for Windows (x86-64) ..." mkdir -p build-mingw && cd build-mingw echo "-DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR" + -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR" cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR + -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && rm -rf build-mingw && cd - echo "--> Building Release for Windows (i686) ..." mkdir -p build-mingw && cd build-mingw echo "-DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR" + -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR" cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR + -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && rm -rf build-mingw && cd - elif [ "$TRAVIS_OS_NAME" == "linux" ]; then @@ -31,14 +31,14 @@ elif [ "$TRAVIS_OS_NAME" == "linux" ]; then echo "--> Building Debug..." mkdir -p build/Debug && cd build/Debug - echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install" - cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR + echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install" + cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && make package && cd - echo "--> Building Release..." mkdir -p build/Release && cd build/Release - echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install" - cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR + echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install" + cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && make package && cd - elif [ "$TRAVIS_OS_NAME" == "osx" ]; then @@ -46,26 +46,26 @@ elif [ "$TRAVIS_OS_NAME" == "osx" ]; then echo "--> Building Debug..." mkdir -p build/Debug && cd build/Debug - echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install" - cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR + echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install" + cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && make package && cd - echo "--> Building Release..." mkdir -p build/Release && cd build/Release - echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install" - cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install $DIR + echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install" + cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && make package && cd - else # local test-build echo "--> Building Debug..." mkdir -p build/Debug && cd build/Debug - echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install" - cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ + echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install" + cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install ../../ make && make package && cd - echo "--> Building Release..." mkdir -p build/Release && cd build/Release - echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install" - cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/_install ../../ + echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install" + cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install ../../ make && make package && cd - fi diff --git a/CMakeLists.txt b/CMakeLists.txt index 57a9161e7..1526f3122 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -67,7 +67,7 @@ find_package(libusb REQUIRED) ## Package configuration (pkg-config) on unix-based systems if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) - add_subdirectory(cmake/pkgconfig) + #add_subdirectory(cmake/pkgconfig) find_package(PkgConfig) pkg_check_modules(GTK3 gtk+-3.0) endif () @@ -187,7 +187,7 @@ set_target_properties( ) # Link shared library -if (APPLE) # ... with Apple macOS libraries +if (APPLE) # ... with Apple macOS libraries find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) find_library(IOKit IOKit) @@ -230,7 +230,7 @@ set_target_properties( ) # Link static library -if (APPLE) # ... with Apple macOS libraries +if (APPLE) # ... with Apple macOS libraries find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) find_library(IOKit IOKit) diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index da03bb596..f36a50b40 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -62,20 +62,23 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av # CPACK_DEBIAN_PACKAGE_HOMEPAGE --> Default: CMAKE_PROJECT_HOMEPAGE_URL set(CPACK_DEBIAN_PACKAGE_SUGGESTS "libgtk-3-dev, pandoc") - ## Add CHANGELOG in Debian-specific format - ### TODO - - ## Add license file - ### TODO - - # Include a postinst-script - set(CPACK_DEBIAN_PACKAGE_CONTROL_EXTRA "${CMAKE_SOURCE_DIR}/cmake/packaging/debian/postinst") + ## Additional package files in Debian-specific format: + # * changelog (package changelog) + # * copyright (license file) + # * rules + # * postinst-script + set(CPACK_DEBIAN_PACKAGE_CONTROL_EXTRA + "${CMAKE_SOURCE_DIR}/cmake/packaging/deb/changelog" + "${CMAKE_SOURCE_DIR}/cmake/packaging/deb/copyright" + "${CMAKE_SOURCE_DIR}/cmake/packaging/deb/rules" + "${CMAKE_SOURCE_DIR}/cmake/packaging/deb/postinst" + ) ### # Slackware & Redhat (RPM) ### - set(CPACK_SET_DESTDIR "OFF") + set(CPACK_SET_DESTDIR "OFF") # Required for relocatable package # CPACK_RPM_PACKAGE_SUMMARY --> Default: CPACK_PACKAGE_DESCRIPTION_SUMMARY # CPACK_RPM_PACKAGE_NAME --> Default: CPACK_PACKAGE_NAME @@ -97,8 +100,9 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av # CPACK_RPM_PACKAGE_URL --> Default: CMAKE_PROJECT_HOMEPAGE_URL set(CPACK_RPM_PACKAGE_DESCRIPTION CPACK_DEBIAN_PACKAGE_DESCRIPTION) - ## Add CHANGELOG in rpm-specific format - ### TODO + ## Add package changelog in rpm-specific format + set(CPACK_RPM_CHANGELOG_FILE "${CMAKE_SOURCE_DIR}/cmake/packaging/rpm/changelog") + else () # No package configuration on other platforms ... endif () diff --git a/cmake/packaging/deb/changelog b/cmake/packaging/deb/changelog index b4e942d7c..f4b644176 100644 --- a/cmake/packaging/deb/changelog +++ b/cmake/packaging/deb/changelog @@ -1,226 +1,49 @@ -stlink (1.6.0) unstable; urgency=medium - -Release date: 2020-02-20 - -Major changes and added features: - -* Initial support for STM32L41X -* Working support for CKS32F103C8T6 and related CKS devices with Core-ID 0x2ba01477 -* Added preliminary support for some STM32G0 chips -* Added support for mass erasing second bank on STM32F10x_XL -* Added call to clear PG bit after writing to flash -* Added support to write option bytes for the STM32G0 -* Added support for STM32WB55 chips -* Added STLink V3SET VID:PIDs to the udev rules -* Support for "STM32+Audio" v2-1 firmware -* Build for Windows under Debian/Ubuntu -* Allow for 64 bytes serials -* Added full support for STLINK CHIP ID L4RX -* Added support for the STLink-v2.1 when flashed with no mass storage (PID 0x3752) -* Added support for writing option bytes on STM32L0xx -* Added support to read and write option bytes for STM32F2 series -* Added support to read and write option bytes for STM32F446 - -Updates and fixes: - -* Fixed "unkown chip id", piped output and st-util -v -* Fixed an issue with versioning stuck at 1.4.0 for versions cloned with git -* Updated STM32F3xx chip ID that covers a few different devices -* Made udev rules and modprobe conf installation optional -* Fixed case when __FILE__ don't contain "/" nor "\\" -* Fixed double dash issue in doc/man -* Compiling documentation: package is called libusb-1.0-0-dev on Debian -* Only do bank calculation on STM32L4 devices with dual banked flash / Added chip-ID 0x464 for STM32L41xxx/L42xxx devices -* Added O_BINARY option to open file -* Fixed versioning when compiling from the checked out git-repo -* win32: move usleep definition to unistd.h -* Fixed relative path to the UI files needed by stlink-gui-local (GUI) -* Added howto for sending NRST signal through GDB -* Fixed package name "devscripts" in doc/compiling.md -* Fixed few potential memory/resource leaks -* Updated Linux source repositories in README.md: Debian and Ubuntu -* Do not issue JTAG reset on stlink-v1 -* Fixed flash size of STM32 Discovery vl -* Updated documentation on software structure - -General project updates: - -* Updated README.md, CHANGELOG.md and issue templates -* Fixed travis build config file -* Added CODE_OF_CONDUCT -* Archived page from github project wiki to doc/wiki_old.md - --- Luca Boccassi Tue, 25 Feb 2020 22:08:33 +0000 - - -stlink (1.5.1) unstable; urgency=medium - -Release date: 2018-09-13 - -Major changes and added features: - -* Added reset through AIRCR -* Added creation of icons for .desktop file -* Added desktop file for linux -* Added button to export STM32 flash memory to a file -* Updated libusb to 1.0.22 -* Added icons for STLink GUI -* Added support for STM32L4R9 target -* Added memory map for STM32F411RE target -* Implemented intel hex support for GTK GUI - -Updates and fixes: - -* Fixed missing flash_loader for STM32L0x -* Fix for stlink library calls exit() or _exit() -* Added semihosting parameter documentation in doc/man -* Fixed reference to non-exisiting st-term tool in doc/man -* Fixed serial number size mismatch with stlink_open_usb() -* Debian packaging, CMake and README.md fixes -* Disabled static library installation by default -* Fix for libusb deprecation -* Renamed STLINK_CHIPID_STM32_L4R9 to STLINK_CHIPID_STM32_L4RX -* Regression: stlink installation under Linux (Debian 9) is broken since #695 -* Fixed flash memory map for STM32F72xxx target -* Proper flash page size calculation for STM32F412xx target -* Return correct value on EOF for Semihosting SYS_READ -* FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION - --- Luca Boccassi Fri, 28 Sep 2018 10:26:39 +0100 - - -stlink (1.5.0) unstable; urgency=medium - -Release date: 2018-02-16 - -Major changes and added features: - -* Added support of STM32L496xx/4A6xx devices -* Added unknown chip dummy to obtain the serial of the ST-link by a call to st-info --probe -* Added support for STM32F72xx (chip-ID: 0x452) devices - -Updates and fixes: - -* Fixed verification of flash error for STM32L496x device -* Updated Linux source repositories in README.md: Gentoo, Fedora and RedHat/CentOS -* Updated changelog in debian package -* Added LIB_INSTALL_DIR to correct libs install on 64-bit systems -* Fixed write for microcontroller with RAM size less or equal to 32K -* Fixed memory map for STM32L496xx boards -* Fixed __FILE__ base name extraction -* Added debian/triggers to run ldconfig -* Fixed build on Fedora with GCC 8 - --- Luca Boccassi Fri, 16 Mar 2018 16:56:17 +0000 +stlink (1.6.0+ds-1) unstable; urgency=medium + * Merge tag 'v1.6.0' into debian + * Bump Standards-Version to 4.5.0, no changes. + * Update libstlink1 symbols file for 1.6.0. -stlink (1.4.0) unstable; urgency=low + -- Luca Boccassi Tue, 25 Feb 2020 22:08:33 +0000 -Release date: 2017-07-01 +stlink (1.5.1+ds-2) unstable; urgency=medium -Major changes and added features: + * Mark library packages as Multi-Arch: same. + * Apply cross.patch to fix cross-compiling the GUI. Thanks Helmut for the patch! (Closes: #941320) + * Vcs-Git: add -b debian + * Set Rules-Requires-Root: no + * Bump Standards-Version to 4.4.0 -* Allow building of debian package with CPack -* Added support for STM32L011 target -* Added support for flashing second bank on STM32F10x_XL -* Initial support to compile with Microsoft Visual Studio 2017 -* Added support for STM32L452 target + -- Luca Boccassi Sun, 29 Sep 2019 12:50:58 +0100 -Updates and fixes: +stlink (1.5.1+ds-1) unstable; urgency=medium -* Fixed gdb-server: STM32L0xx has no FP_CTRL register for breakpoints -* Added --flash=n[k][m] command line option to override device model -* Updated libusb to 1.0.21 for Windows -* Fixed low-voltage flashing on STM32F7 devices -* Fixed building with mingw64 -* Fixed possible memory leak -* Fixed installation path for shared objects -* Fixed a few -Wformat warnings -* Removed unused defines in mimgw.h -* Skip GTK detection when cross-compiling -* Fixed compilation with GCC 7 -* Fixed flashing to 'f0 device' targets -* Fixed wrong counting when flashing + * Merge tag 'v1.5.1' into debian. See upstream changelog for info: + https://github.com/stlink-org/stlink/releases/tag/v1.5.1 + * Mark packages as linux-any, other systems not supported. --- Andrew 'Necromant' Andrianov Sat, 01 Jul 2017 00:00:00 +0000 + -- Luca Boccassi Fri, 28 Sep 2018 10:26:39 +0100 +stlink (1.5.0+ds-1) unstable; urgency=medium -stlink (1.3.1) unstable; urgency=low + * Upload to unstable. (Closes: #869421) -Release date: 2017-02-25 + -- Luca Boccassi Fri, 16 Mar 2018 16:56:17 +0000 -Major changes and added features: +stlink (1.4.0) unstable; urgency=low -* Added support for Semihosting `SYS_READC` -* Added support for STM32F413 -* Added preliminary support for STM32L011 to see it after probe (chip-ID 0x457) + -- Andrew 'Necromant' Andrianov Sat, 01 Jul 2017 00:00:00 +0000 -Updates and fixes: +stlink (1.3.1) unstable; urgency=low -* cmake/CPackConfig.cmake: Fixup OSX zip filename -* Updated source repositories in README.md: Windows, macOS, Alpine Linux -* Compilation fixes -* Stripped full paths to source files in log -* Fixed incorrect release folder name in docs -* Fixed compilation when path includes spaces + -- Andrew 'Necromant' Andrianov Sat, 25 Feb 2017 00:00:00 +0000 --- Andrew 'Necromant' Andrianov Sat, 25 Feb 2017 00:00:00 +0000 +stlink (1.3.0) unstable; urgency=low + -- Andrew 'Necromant' Andrianov Sat, 28 Jan 2017 00:00:00 +0000 -stlink (1.3.0) unstable; urgency=low +stlink (1.2.1) unstable; urgency=low + + * Initial Debian-Packaged Release. -Release date: 2017-01-28 - -Major changes and added features: - -* Deprecation of autotools (autoconf, automake) and fixed build with MinGW -* Added intel hex file reading for `st-flash` -* Added support for ARM semihosting to `st-util` -* Added manpages (generated with pandoc from Markdown) -* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature -* Support serial numbers argument for `st-util` and `st-flash` to probe and control multiple connected programmers -* Merge st-probe tool into st-info -* Added support for native debian packaging -* Rewritten commandline parsing for `st-flash` -* Added `--reset` command to `st-flash` -* st-util should detect when USB commands fail - -Chip support added for: - -* STM32F401XE: Added memory map for device -* STM32F410RBTx -* STM32F412 -* STM32F7xx -* STM32F7x7x -* STM32L0xx Cat2 devices (chip-ID: 0x425) -* STM32L0xx Cat5 devices (chip-ID: 0x447) -* STM32L4xx -* STM32L432 - -Updates and fixes: - -* Fixed "unaligned addr or size" when trying to write a program in RAM -* Fixed flashing on STM32_F3_SMALL -* Fixed STM32L-problem with flash loader -* Don't read the target voltage on startup, because it crashes STM32F100 -* Added a useful error message instead of "[!] send_recv" -* Do a JTAG reset prior to reading CPU information when processor is in deep sleep -* Fixed STM32F030 erase error -* Fixed memory map for STM32F7xx -* Redesign of `st-flash` commandline options parsing -* Set SWDCLK and fixed jtag_reset bug -* doc/compiling.md: Add note about installation and ldconfig -* Fixed Release target to generate the man-pages with pandoc -* Fixed Cygwin build -* Reset flash mass erase (MER) bit after mass erase for safety -* Wrong extract command in FindLibUSB.cmake -* Fixed compilation error on Ubuntu 16.10 - --- Andrew 'Necromant' Andrianov Sat, 28 Jan 2017 00:00:00 +0000 - - -libstlink (1.2.1) unstable; urgency=low - -* Initial Debian-packaged release. - --- Andrew 'Necromant' Andrianov Sat, 09 Jul 2016 23:16:07 +0300 + -- Andrew 'Necromant' Andrianov Sat, 09 Jul 2016 23:16:07 +0300 diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control new file mode 100644 index 000000000..d96746e65 --- /dev/null +++ b/cmake/packaging/deb/control @@ -0,0 +1,9 @@ +Source: stlink +Maintainer: Luca Bocassi +Build-Depends: cmake, dh-cmake, debhelper (>= 9), libusb-1.0-0-dev, libgtk-3-dev +Standards-Version: 4.1.3 +Section: electronics +Priority: optional +Homepage: https://github.com/stlink-org/stlink +Vcs-Git: https://github.com/stlink-org/stlink.git +Vcs-Browser: https://github.com/stlink-org/stlink diff --git a/cmake/packaging/deb/copyright b/cmake/packaging/deb/copyright index 37a101b98..a14d4eb6e 100644 --- a/cmake/packaging/deb/copyright +++ b/cmake/packaging/deb/copyright @@ -4,6 +4,14 @@ Upstream-Contact: Luca Bocassi Source: https://github.com/stlink-org/stlink Disclaimer: Comment: +Files: * +Copyright: 2011-2020 stlink-org + Martin Capitanio [capnm] + Fabien Le Mentec [texane] + Jerry Jacobs [xor-gate] + [Nightwalker-87] + and many others... + A list of contributors can be found in "contributors.txt". License: BSD-3-clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -27,11 +35,3 @@ License: BSD-3-clause CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -Files: * -Copyright: 2011-2020 stlink-org - Martin Capitanio [capnm] - Fabien Le Mentec [texane] - Jerry Jacobs [xor-gate] - [Nightwalker-87] - . - and many others... A list of contributors can be found in "contributors.txt". diff --git a/cmake/packaging/deb/rules b/cmake/packaging/deb/rules index e183fffb7..2f80faeac 100755 --- a/cmake/packaging/deb/rules +++ b/cmake/packaging/deb/rules @@ -11,7 +11,7 @@ include /usr/share/dpkg/default.mk export DEB_BUILD_MAINT_OPTIONS = hardening=+all %: - dh $@ --buildsystem cmake + dh $@ --buildsystem cmake --with cpack override_dh_auto_configure: dh_auto_configure -- \ diff --git a/cmake/packaging/rpm/changelog b/cmake/packaging/rpm/changelog new file mode 100644 index 000000000..de2400d65 --- /dev/null +++ b/cmake/packaging/rpm/changelog @@ -0,0 +1,2 @@ +* Mon Jun 01 2020 Vasiliy Glazov - 1.6.1 +- Initial RPM-packaged release diff --git a/mingw64-build.bat b/mingw64-build.bat index 9d5cf4d06..eeaacddab 100644 --- a/mingw64-build.bat +++ b/mingw64-build.bat @@ -5,5 +5,5 @@ cd build-mingw set PATH=C:\Program Files (x86)\CMake\bin;C:\Program Files\CMake\bin;C:\Program Files\mingw-w64\x86_64-8.1.0-win32-sjlj-rt_v6-rev0\mingw64\bin;%PATH% cmake -G "MinGW Makefiles" .. mingw32-make -mingw32-make install DESTDIR=_install +mingw32-make install DESTDIR=install mingw32-make package From 1b3200d5bc1d6c5b90a54f4c92aa8fbe3f8bb660 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 18 May 2020 18:34:16 +0200 Subject: [PATCH 0932/1435] Updated build settings - Removed unneeded commands in travis.sh - Removed -Wno-dev flag in Release target - cmake: Grouped udev and modprobe.d config - rpm package now relocatable (CPackRPM) --- .travis.sh | 6 +++--- CMakeLists.txt | 36 +++++++++++++++++++++--------------- Makefile | 2 +- doc/man/CMakeLists.txt | 2 +- 4 files changed, 26 insertions(+), 20 deletions(-) diff --git a/.travis.sh b/.travis.sh index 3bab4c5d0..2c98a6ef6 100755 --- a/.travis.sh +++ b/.travis.sh @@ -33,7 +33,7 @@ elif [ "$TRAVIS_OS_NAME" == "linux" ]; then mkdir -p build/Debug && cd build/Debug echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && make package && cd - + make && cd - echo "--> Building Release..." mkdir -p build/Release && cd build/Release @@ -48,7 +48,7 @@ elif [ "$TRAVIS_OS_NAME" == "osx" ]; then mkdir -p build/Debug && cd build/Debug echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && make package && cd - + make && cd - echo "--> Building Release..." mkdir -p build/Release && cd build/Release @@ -61,7 +61,7 @@ else # local test-build mkdir -p build/Debug && cd build/Debug echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install ../../ - make && make package && cd - + make && cd - echo "--> Building Release..." mkdir -p build/Release && cd build/Release diff --git a/CMakeLists.txt b/CMakeLists.txt index 1526f3122..8b3210dbf 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -18,14 +18,6 @@ project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics ST-LINK Tools") include(GNUInstallDirs) # Define GNU standard installation directories -set(STLINK_UDEV_RULES_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/udev/rules.d" CACHE PATH "udev rules directory") -option(STLINK_INSTALL_UDEV_RULES "Install udev rules files" ON) - -set(STLINK_MODPROBED_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/modprobe.d" CACHE PATH "modprobe.d directory") -option(STLINK_INSTALL_MODPROBE_CONF "Install modprobe conf files" ON) - -option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) - ## Determine project version include(${CMAKE_MODULE_PATH}/get_version.cmake) @@ -271,20 +263,32 @@ else () target_link_libraries(st-util ${STLINK_LIB_SHARED} ${SSP_LIB}) endif () +install(TARGETS st-flash DESTINATION bin) +install(TARGETS st-info DESTINATION bin) +install(TARGETS st-util DESTINATION bin) + + +### +# udev and modprobe.d configuration +### + if (CMAKE_SYSTEM_NAME STREQUAL "Linux") + ## modprobe.d rules + set(STLINK_MODPROBED_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/modprobe.d" CACHE PATH "modprobe.d directory") + option(STLINK_INSTALL_MODPROBE_CONF "Install modprobe conf files" ON) if (STLINK_INSTALL_MODPROBE_CONF) - install(FILES etc/modprobe.d/stlink_v1.conf DESTINATION ${STLINK_MODPROBED_DIR}/) + install(FILES ${CMAKE_SOURCE_DIR}/etc/modprobe.d/stlink_v1.conf DESTINATION ${STLINK_MODPROBED_DIR}/) endif () + + ## udev rules + set(STLINK_UDEV_RULES_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/udev/rules.d" CACHE PATH "udev rules directory") + option(STLINK_INSTALL_UDEV_RULES "Install udev rules files" ON) if (STLINK_INSTALL_UDEV_RULES) - file(GLOB RULES_FILES etc/udev/rules.d/*.rules) + file(GLOB RULES_FILES ${CMAKE_SOURCE_DIR}/etc/udev/rules.d/*.rules) install(FILES ${RULES_FILES} DESTINATION ${STLINK_UDEV_RULES_DIR}/) endif () endif () -install(TARGETS st-flash DESTINATION bin) -install(TARGETS st-info DESTINATION bin) -install(TARGETS st-util DESTINATION bin) - ### # Additional build tasks @@ -297,9 +301,11 @@ add_subdirectory(include) # contains subordinate CMakeLists for version config a add_subdirectory(src/stlink-gui) # contains subordinate CMakeLists to build GUI add_subdirectory(tests) # contains subordinate CMakeLists to build test executables -add_subdirectory(doc/man) # contains subordinate CMakeLists to generate manpages add_subdirectory(cmake/packaging) # contains subordinate CMakeLists to build packages +option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) +add_subdirectory(doc/man) # contains subordinate CMakeLists to generate manpages + ### # Uninstall target diff --git a/Makefile b/Makefile index 3f46d2943..53b0ddcde 100644 --- a/Makefile +++ b/Makefile @@ -55,7 +55,7 @@ build/Debug: build/Release: @mkdir -p $@ - @cd $@ && cmake -DCMAKE_BUILD_TYPE=Release $(CMAKEFLAGS) -Wno-dev ../../ + @cd $@ && cmake -DCMAKE_BUILD_TYPE=Release $(CMAKEFLAGS) ../../ clean: @echo "[CLEAN]" diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 221c84d7b..3646654f4 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -30,7 +30,7 @@ foreach (manpage ${MANPAGES}) endif () if (f AND NOT WIN32) - install(FILES ${f} DESTINATION ${CMAKE_INSTALL_PREFIX}/share/man/man1) + install(FILES ${f} DESTINATION ${CMAKE_INSTALL_MANDIR}/man1) unset(f) endif () endforeach () From 7ef06378aa16e210dc480ef5ae2bc12973becc0c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 19 May 2020 11:28:35 +0200 Subject: [PATCH 0933/1435] Refactoring for build settings Tidy up install paths & directories: -> modprobe.d & udev rules (both are now ON per default on Linux) -> stlink-gui supplements -> man pages - Fixed paths according to GNUInstallDirs - cmake: Restructured library config - Test files & gui now use shared library --- .travis.sh | 12 +-- CMakeLists.txt | 88 +++++++------------ {etc => config}/modprobe.d/stlink_v1.conf | 0 .../udev/rules.d/49-stlinkv1.rules | 0 .../udev/rules.d/49-stlinkv2-1.rules | 0 .../udev/rules.d/49-stlinkv2.rules | 0 .../udev/rules.d/49-stlinkv3.rules | 0 doc/man/CMakeLists.txt | 2 +- src/stlink-gui/CMakeLists.txt | 29 +++--- tests/CMakeLists.txt | 6 +- 10 files changed, 56 insertions(+), 81 deletions(-) rename {etc => config}/modprobe.d/stlink_v1.conf (100%) rename {etc => config}/udev/rules.d/49-stlinkv1.rules (100%) rename {etc => config}/udev/rules.d/49-stlinkv2-1.rules (100%) rename {etc => config}/udev/rules.d/49-stlinkv2.rules (100%) rename {etc => config}/udev/rules.d/49-stlinkv3.rules (100%) diff --git a/.travis.sh b/.travis.sh index 2c98a6ef6..cc0958bf5 100755 --- a/.travis.sh +++ b/.travis.sh @@ -35,11 +35,11 @@ elif [ "$TRAVIS_OS_NAME" == "linux" ]; then cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && cd - - echo "--> Building Release..." + echo "--> Building Release with package..." mkdir -p build/Release && cd build/Release echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && make package && cd - + make package && cd - elif [ "$TRAVIS_OS_NAME" == "osx" ]; then brew install libusb @@ -50,11 +50,11 @@ elif [ "$TRAVIS_OS_NAME" == "osx" ]; then cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && cd - - echo "--> Building Release..." + echo "--> Building Release with package..." mkdir -p build/Release && cd build/Release echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && make package && cd - + make package && cd - else # local test-build echo "--> Building Debug..." @@ -63,9 +63,9 @@ else # local test-build cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install ../../ make && cd - - echo "--> Building Release..." + echo "--> Building Release with package..." mkdir -p build/Release && cd build/Release echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install ../../ - make && make package && cd - + make package && cd - fi diff --git a/CMakeLists.txt b/CMakeLists.txt index 8b3210dbf..dcdaf2ad4 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -9,7 +9,6 @@ set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) - ### # General project settings ### @@ -32,16 +31,7 @@ else () set(CMAKE_C_FLAGS_RELWITHDEBINFO_INIT "/MT /Zi /O2 /Ob1 /D NDEBUG") endif () -## Set installation directories for libraries -if (IS_DIRECTORY ${LIB_INSTALL_DIR}) - set(LIB_INSTALL_DIR ${LIB_INSTALL_DIR} CACHE PATH "Main library directory") - set(STLINK_LIBRARY_PATH "${LIB_INSTALL_DIR}") -else () - set(LIB_INSTALL_DIR "lib" CACHE PATH "Main library directory") - set(STLINK_LIBRARY_PATH "${CMAKE_INSTALL_PREFIX}/${LIB_INSTALL_DIR}") -endif () - -## Set installation directories for header files +## Set installation directories for header files ### TODO: Clean this up... if (IS_DIRECTORY ${INCLUDE_INSTALL_DIR}) set(INCLUDE_INSTALL_DIR ${INCLUDE_INSTALL_DIR} CACHE PATH "Main include directory") set(STLINK_INCLUDE_PATH "${INCLUDE_INSTALL_DIR}") @@ -95,13 +85,14 @@ endif () include_directories(${LIBUSB_INCLUDE_DIR}) # ==== -include_directories(include) ### TODO: Clean this up... +include_directories(${PROJECT_SOURCE_DIR}/include) ### TODO: Clean this up... include_directories(${PROJECT_BINARY_DIR}/include/stlink) -include_directories(include/stlink) -include_directories(include/stlink/tools) +include_directories(${PROJECT_SOURCE_DIR}/include/stlink) +include_directories(${PROJECT_SOURCE_DIR}/include/stlink/tools) # ==== include_directories(src) +include_directories(src/tools) ### TODO: Clean this up... set(STLINK_HEADERS include/stlink.h @@ -145,29 +136,30 @@ if (${CMAKE_BUILD_TYPE} MATCHES "Debug") endif () +### +# Libraries +### + +set(STLINK_LIBRARY_PATH ${CMAKE_INSTALL_LIBDIR} CACHE PATH "Main library install directory") + +# Set the environment variable LD_LIBRARY_PATH to point to /usr/local/lib (per default). +execute_process (COMMAND bash -c "export LD_LIBRARY_PATH="${CMAKE_INSTALL_LIBDIR}"") + + ### # Shared library ### +# Set library name if (NOT WIN32) set(STLINK_LIB_SHARED ${PROJECT_NAME}) else (WIN32) set(STLINK_LIB_SHARED ${PROJECT_NAME}-shared) endif () -add_library( - ${STLINK_LIB_SHARED} SHARED - ${STLINK_HEADERS} # header files for ide projects generated by cmake - ${STLINK_SOURCE} - ) - -target_link_libraries( - ${STLINK_LIB_SHARED} - ${LIBUSB_LIBRARY} - ) +add_library(${STLINK_LIB_SHARED} SHARED ${STLINK_HEADERS} ${STLINK_SOURCE}) set(STLINK_SHARED_VERSION ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}) - message(STATUS "STLINK_LIB_SHARED: ${STLINK_LIB_SHARED}") message(STATUS "PROJECT_VERSION_MAJOR: ${PROJECT_VERSION_MAJOR}") message(STATUS "VERSION: ${STLINK_SHARED_VERSION}") @@ -176,6 +168,7 @@ set_target_properties( ${STLINK_LIB_SHARED} PROPERTIES SOVERSION ${PROJECT_VERSION_MAJOR} VERSION ${STLINK_SHARED_VERSION} + OUTPUT_NAME ${PROJECT_NAME} ) # Link shared library @@ -197,19 +190,12 @@ install(TARGETS ${STLINK_LIB_SHARED} DESTINATION ${STLINK_LIBRARY_PATH}) # Static library ### -# Install static library per default -set(STLINK_STATIC_LIB ON CACHE BOOL "Install static lib") - +# Set library name set(STLINK_LIB_STATIC ${PROJECT_NAME}-static) -add_library( - ${STLINK_LIB_STATIC} STATIC - ${STLINK_HEADERS} # header files for ide projects generated by cmake - ${STLINK_SOURCE} - ) +add_library(${STLINK_LIB_STATIC} STATIC ${STLINK_HEADERS} ${STLINK_SOURCE}) set(STLINK_STATIC_VERSION ${PROJECT_VERSION_MAJOR}.${PROJECT_VERSION_MINOR}.${PROJECT_VERSION_PATCH}) - message(STATUS "STLINK_LIB_STATIC: ${STLINK_LIB_STATIC}") message(STATUS "PROJECT_VERSION_MAJOR: ${PROJECT_VERSION_MAJOR}") message(STATUS "VERSION: ${STLINK_STATIC_VERSION}") @@ -233,9 +219,7 @@ else () target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB}) endif () -if (STLINK_STATIC_LIB) - install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH}) -endif () +install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH}) ### @@ -263,30 +247,24 @@ else () target_link_libraries(st-util ${STLINK_LIB_SHARED} ${SSP_LIB}) endif () -install(TARGETS st-flash DESTINATION bin) -install(TARGETS st-info DESTINATION bin) -install(TARGETS st-util DESTINATION bin) +install(TARGETS st-flash DESTINATION ${CMAKE_INSTALL_BINDIR}) +install(TARGETS st-info DESTINATION ${CMAKE_INSTALL_BINDIR}) +install(TARGETS st-util DESTINATION ${CMAKE_INSTALL_BINDIR}) ### -# udev and modprobe.d configuration +# Device configuration (Linux only) ### if (CMAKE_SYSTEM_NAME STREQUAL "Linux") - ## modprobe.d rules - set(STLINK_MODPROBED_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/modprobe.d" CACHE PATH "modprobe.d directory") - option(STLINK_INSTALL_MODPROBE_CONF "Install modprobe conf files" ON) - if (STLINK_INSTALL_MODPROBE_CONF) - install(FILES ${CMAKE_SOURCE_DIR}/etc/modprobe.d/stlink_v1.conf DESTINATION ${STLINK_MODPROBED_DIR}/) - endif () - - ## udev rules - set(STLINK_UDEV_RULES_DIR "${CMAKE_INSTALL_FULL_SYSCONFDIR}/udev/rules.d" CACHE PATH "udev rules directory") - option(STLINK_INSTALL_UDEV_RULES "Install udev rules files" ON) - if (STLINK_INSTALL_UDEV_RULES) - file(GLOB RULES_FILES ${CMAKE_SOURCE_DIR}/etc/udev/rules.d/*.rules) - install(FILES ${RULES_FILES} DESTINATION ${STLINK_UDEV_RULES_DIR}/) - endif () + ## Install modprobe.d conf files / rules to /usr/local/etc/stlink (default) + set(STLINK_MODPROBED_DIR "${CMAKE_INSTALL_SYSCONFDIR}/${PROJECT_NAME}/modprobe.d" CACHE PATH "modprobe.d directory") + install(FILES ${CMAKE_SOURCE_DIR}/config/modprobe.d/stlink_v1.conf DESTINATION ${STLINK_MODPROBED_DIR}) + + ## Install udev rules files / rules to /usr/local/etc/stlink (default) + set(STLINK_UDEV_RULES_DIR "${CMAKE_INSTALL_SYSCONFDIR}/${PROJECT_NAME}/udev/rules.d" CACHE PATH "udev rules directory") + file(GLOB RULES_FILES ${CMAKE_SOURCE_DIR}/config/udev/rules.d/*.rules) + install(FILES ${RULES_FILES} DESTINATION ${STLINK_UDEV_RULES_DIR}) endif () diff --git a/etc/modprobe.d/stlink_v1.conf b/config/modprobe.d/stlink_v1.conf similarity index 100% rename from etc/modprobe.d/stlink_v1.conf rename to config/modprobe.d/stlink_v1.conf diff --git a/etc/udev/rules.d/49-stlinkv1.rules b/config/udev/rules.d/49-stlinkv1.rules similarity index 100% rename from etc/udev/rules.d/49-stlinkv1.rules rename to config/udev/rules.d/49-stlinkv1.rules diff --git a/etc/udev/rules.d/49-stlinkv2-1.rules b/config/udev/rules.d/49-stlinkv2-1.rules similarity index 100% rename from etc/udev/rules.d/49-stlinkv2-1.rules rename to config/udev/rules.d/49-stlinkv2-1.rules diff --git a/etc/udev/rules.d/49-stlinkv2.rules b/config/udev/rules.d/49-stlinkv2.rules similarity index 100% rename from etc/udev/rules.d/49-stlinkv2.rules rename to config/udev/rules.d/49-stlinkv2.rules diff --git a/etc/udev/rules.d/49-stlinkv3.rules b/config/udev/rules.d/49-stlinkv3.rules similarity index 100% rename from etc/udev/rules.d/49-stlinkv3.rules rename to config/udev/rules.d/49-stlinkv3.rules diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 3646654f4..23da9e150 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -30,7 +30,7 @@ foreach (manpage ${MANPAGES}) endif () if (f AND NOT WIN32) - install(FILES ${f} DESTINATION ${CMAKE_INSTALL_MANDIR}/man1) + install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/man/man1) unset(f) endif () endforeach () diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index b5ef99df9..c38fdadaa 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -16,26 +16,23 @@ set(GUI_SOURCES gui.c gui.h) ## stlink-gui-local add_executable(stlink-gui-local ${GUI_SOURCES}) -set_target_properties( - stlink-gui-local PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_CURRENT_SOURCE_DIR}" - # Note: ${CMAKE_CURRENT_SOURCE_DIR} is src/stlink-gui - ) -target_link_libraries(stlink-gui-local ${STLINK_LIB_STATIC} ${GTK3_LDFLAGS} ${SSP_LIB}) +set_target_properties(stlink-gui-local PROPERTIES + # Note: ${CMAKE_CURRENT_SOURCE_DIR} is src/stlink-gui + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_CURRENT_SOURCE_DIR}") +target_link_libraries(stlink-gui-local ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) ## stlink-gui add_executable(stlink-gui ${GUI_SOURCES}) -set_target_properties( - stlink-gui PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin" - # Note: ${CMAKE_INSTALL_PREFIX} defaults to /usr/local - ) -target_link_libraries(stlink-gui ${STLINK_LIB_STATIC} ${GTK3_LDFLAGS} ${SSP_LIB}) +set_target_properties(stlink-gui PROPERTIES + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_BINDIR}") +target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) -install(TARGETS stlink-gui DESTINATION bin) -install(FILES stlink-gui.ui DESTINATION bin) +install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) +install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_BINDIR}) if (${CMAKE_SYSTEM_NAME} MATCHES "Linux") - install(FILES stlink-gui.desktop DESTINATION share/applications) # Install desktop application entry - install(FILES icons/stlink-gui.svg DESTINATION share/icons/hicolor/scalable/apps) # Install icon + # Install desktop application entry + install(FILES stlink-gui.desktop DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/applications) + # Install icons + install(FILES icons/stlink-gui.svg DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/icons/hicolor/scalable/apps) endif () diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 40d2203db..6e60fdd5a 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -6,11 +6,11 @@ set(TESTEXEC usb sg) foreach (test ${TESTEXEC}) add_executable(test-${test} ${test}.c) - add_dependencies(test-${test} ${STLINK_LIB_STATIC}) - target_link_libraries(test-${test} ${STLINK_LIB_STATIC} ${SSP_LIB}) + add_dependencies(test-${test} ${STLINK_LIB_SHARED}) + target_link_libraries(test-${test} ${STLINK_LIB_SHARED} ${SSP_LIB}) add_test(test-${test} ${CMAKE_BINARY_DIR}/bin/test-${test}) endforeach () add_executable(test-flash flash.c "${CMAKE_SOURCE_DIR}/src/tools/flash_opts.c") -target_link_libraries(test-flash ${STLINK_LIB_STATIC} ${SSP_LIB}) +target_link_libraries(test-flash ${STLINK_LIB_SHARED} ${SSP_LIB}) add_test(test-flash ${CMAKE_BINARY_DIR}/bin/test-flash) From 5fc02abf33722fbf27996e955b2cc3017368e45a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 19 May 2020 14:08:07 +0200 Subject: [PATCH 0934/1435] Improved cmake-config for GUI build --- src/stlink-gui/CMakeLists.txt | 57 ++++++++++++++++++----------------- src/stlink-gui/gui.c | 3 +- 2 files changed, 31 insertions(+), 29 deletions(-) diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index c38fdadaa..8c36e5a1f 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -2,37 +2,40 @@ # Build GUI ### -## GUI-Building requires the presence of a GTK3 toolset -if (NOT GTK3_FOUND) - message(STATUS "GTK3 not found!") - return() # no GTK3 present => no GUI build -else (GTK3_FOUND) - message(STATUS "Found GTK3: -I${GTK3_INCLUDE_DIRS}, ${GTK3_LIBRARIES}") -endif () +if (NOT WIN32) + ## GUI-Building requires the presence of a GTK3 toolset + if (NOT GTK3_FOUND) + message(STATUS "GTK3 not found!") + return() # no GTK3 present => no GUI build + else (GTK3_FOUND) + message(STATUS "Found GTK3: -I${GTK3_INCLUDE_DIRS}, ${GTK3_LIBRARIES}") + include_directories(SYSTEM ${GTK3_INCLUDE_DIRS}) + + # Install desktop application entry + install(FILES stlink-gui.desktop + DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/applications) -include_directories(SYSTEM ${GTK3_INCLUDE_DIRS}) + # Install icons + install(FILES icons/stlink-gui.svg + DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/icons/hicolor/scalable/apps) -set(GUI_SOURCES gui.c gui.h) + set(GUI_SOURCES gui.c gui.h) -## stlink-gui-local -add_executable(stlink-gui-local ${GUI_SOURCES}) -set_target_properties(stlink-gui-local PROPERTIES - # Note: ${CMAKE_CURRENT_SOURCE_DIR} is src/stlink-gui - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_CURRENT_SOURCE_DIR}") -target_link_libraries(stlink-gui-local ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) + ## stlink-gui-local + add_executable(stlink-gui-local ${GUI_SOURCES}) + file(COPY stlink-gui.ui DESTINATION ${CMAKE_BINARY_DIR}/bin) + set_target_properties(stlink-gui-local PROPERTIES + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_BINARY_DIR}/bin") + target_link_libraries(stlink-gui-local ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) -## stlink-gui -add_executable(stlink-gui ${GUI_SOURCES}) -set_target_properties(stlink-gui PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_BINDIR}") -target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) + ## stlink-gui + add_executable(stlink-gui ${GUI_SOURCES}) + install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_BINDIR}) + set_target_properties(stlink-gui PROPERTIES + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin") + target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) + install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) -install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) -install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_BINDIR}) -if (${CMAKE_SYSTEM_NAME} MATCHES "Linux") - # Install desktop application entry - install(FILES stlink-gui.desktop DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/applications) - # Install icons - install(FILES icons/stlink-gui.svg DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/icons/hicolor/scalable/apps) + endif () endif () diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index 5d5a422d5..0a95aee76 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -781,8 +781,7 @@ static void stlink_gui_build_ui (STlinkGUI *gui) { GtkListStore *filemem_store; gchar *ui_file = STLINK_UI_DIR "/stlink-gui.ui"; - if (!g_file_test (ui_file, G_FILE_TEST_EXISTS)) - ui_file = "stlink-gui.ui"; + if (!g_file_test (ui_file, G_FILE_TEST_EXISTS)) ui_file = "stlink-gui.ui"; builder = gtk_builder_new (); if (!gtk_builder_add_from_file (builder, ui_file, NULL)) { g_printerr ("Failed to load UI file: %s\n", ui_file); From 73dc5fed246317711f0ece4252064dbf3b63534b Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Tue, 19 May 2020 17:50:10 +0300 Subject: [PATCH 0935/1435] link libssp statically --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index dcdaf2ad4..c61b9b6bf 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -71,7 +71,7 @@ include(CheckLibraryExists) CHECK_LIBRARY_EXISTS(ssp __stack_chk_fail "" _stack_chk_fail_exists) if (_stack_chk_fail_exists) - set(SSP_LIB ssp) + set(SSP_LIB -static ssp) else () set(SSP_LIB "") endif () From af765a20228dd973d9933ed49228049bc121fcce Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 22 May 2020 15:11:43 +0200 Subject: [PATCH 0936/1435] Minor fixes for flashloader files --- flashloaders/stm32f0.s | 4 ++-- flashloaders/stm32f4.s | 4 ++-- flashloaders/stm32f4lv.s | 4 ++-- flashloaders/stm32f7.s | 4 ++-- flashloaders/stm32f7lv.s | 4 ++-- flashloaders/stm32l4.s | 4 ++-- 6 files changed, 12 insertions(+), 12 deletions(-) diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s index cbb932b49..f30e4bfc6 100644 --- a/flashloaders/stm32f0.s +++ b/flashloaders/stm32f0.s @@ -42,11 +42,11 @@ loop: adds r1, r1, r7 # wait if FLASH_SR == 1 -mywait: +wait: ldr r7, =0x1 ldr r3, [r5] tst r3, r7 - beq mywait + beq wait # exit if FLASH_SR != 4 ldr r7, =0x4 diff --git a/flashloaders/stm32f4.s b/flashloaders/stm32f4.s index b4e0f4913..a88ad9e02 100644 --- a/flashloaders/stm32f4.s +++ b/flashloaders/stm32f4.s @@ -16,10 +16,10 @@ loop: add r1, r1, #4 # wait if FLASH_SR == 1 -mywait: +wait: ldrh r3, [r10] tst r3, #0x1 - beq mywait + beq wait # loop if r2 != 0 sub r2, r2, #1 diff --git a/flashloaders/stm32f4lv.s b/flashloaders/stm32f4lv.s index f5cc29841..41467a9ef 100644 --- a/flashloaders/stm32f4lv.s +++ b/flashloaders/stm32f4lv.s @@ -22,10 +22,10 @@ loop: add r1, r1, #1 # wait if FLASH_SR == 1 -mywait: +wait: ldrh r3, [r10] tst r3, #0x1 - beq mywait + beq wait # loop if r2 != 0 sub r2, r2, #1 diff --git a/flashloaders/stm32f7.s b/flashloaders/stm32f7.s index 8694d864e..3779a5ea6 100644 --- a/flashloaders/stm32f7.s +++ b/flashloaders/stm32f7.s @@ -19,10 +19,10 @@ loop: dsb sy # wait if FLASH_SR == 1 -mywait: +wait: ldrh r3, [r10] tst r3, #0x1 - beq mywait + beq wait # loop if r2 != 0 sub r2, r2, #1 diff --git a/flashloaders/stm32f7lv.s b/flashloaders/stm32f7lv.s index b48e40f0d..e7b66cc2c 100644 --- a/flashloaders/stm32f7lv.s +++ b/flashloaders/stm32f7lv.s @@ -25,10 +25,10 @@ loop: dsb sy # wait if FLASH_SR == 1 -mywait: +wait: ldrh r3, [r10] tst r3, #0x1 - beq mywait + beq wait # loop if r2 != 0 sub r2, r2, #1 diff --git a/flashloaders/stm32l4.s b/flashloaders/stm32l4.s index c68198bfa..32c27a057 100644 --- a/flashloaders/stm32l4.s +++ b/flashloaders/stm32l4.s @@ -18,10 +18,10 @@ loop: add r1, r1, #8 # wait if FLASH_BSY[0b] == 1 -mywait: +wait: ldrh r3, [r10] tst r3, #0x1 - beq mywait + beq wait # loop if r2 != 0 sub r2, r2, #1 From 937f4d6aeaf7ddc50bc181a1448a40fc9389e8c2 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 22 May 2020 19:42:16 +0200 Subject: [PATCH 0937/1435] General Project Update - Updated CHANGELOG - Minor fixes --- CHANGELOG.md | 126 ++++++++++++++++++++++++++++--------------------- CMakeLists.txt | 6 +-- README.md | 2 +- 3 files changed, 74 insertions(+), 60 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index f79cd846c..b6b63e156 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -10,67 +10,83 @@ This release drops support for some older operating systems. Check project READM Features: -- Support for STM32L1, SM32L4 option bytes write (#596, #844, #847) -- CMake now creates an uninstall target (#619, #907) -- Added CMAKEFLAGS and install target (#804, #935) -- Support for STM32G4 (#822) -- Add aliased SRAM2 region in the L496 memory map (#824) -- Improved support for STM32G0 (#825, #850, #856, #857) -- Added postinst script with 'depmod -a' for 'make package' (#845, #931) -- Calculate checksums for flash operations (#862, #924) -- Added usb PID and udev rules for STlink v2.1 found on Nucleo-L432KC and Nucleo-L552ze boards (#900) -- STM32G0/G4 improvements (#910) +- Basic compatibility for STLink-v3 programmer ([#271](https://github.com/stlink-org/stlink/pull/271), [#863](https://github.com/stlink-org/stlink/pull/863), [#954](https://github.com/stlink-org/stlink/pull/954)) + - Added support for JTAG command API v2 & distinguish protocol versions v1 and v2 + - Compatibility with the STLink-v3 firmware which dropped support for the previous API v1 + - As of firmware version J11 the ST-LINK-V1 programmer supports API v2 commands as well +- Display programmer serial when no target is connected ([#432](https://github.com/stlink-org/stlink/pull/432), [#933](https://github.com/stlink-org/stlink/pull/933), [#943](https://github.com/stlink-org/stlink/pull/943)) +- Support for STM32L1, SM32L4 option bytes write ([#596](https://github.com/stlink-org/stlink/pull/596), [#844](https://github.com/stlink-org/stlink/pull/844), [#847](https://github.com/stlink-org/stlink/pull/847)) +- CMake now creates an uninstall target ([#619](https://github.com/stlink-org/stlink/pull/619), [#907](https://github.com/stlink-org/stlink/pull/907)) +- Added CMAKEFLAGS and install target ([#804](https://github.com/stlink-org/stlink/pull/804), [#935](https://github.com/stlink-org/stlink/pull/935)) +- Support for STM32G4 ([#822](https://github.com/stlink-org/stlink/pull/822)) +- Add aliased SRAM2 region in the L496 memory map ([#824](https://github.com/stlink-org/stlink/pull/824)) +- Improved support for STM32G0 ([#825](https://github.com/stlink-org/stlink/pull/825), [#850](https://github.com/stlink-org/stlink/pull/850), [#856](https://github.com/stlink-org/stlink/pull/856), [#857](https://github.com/stlink-org/stlink/pull/857)) +- Added postinst script with 'depmod -a' for 'make package' ([#845](https://github.com/stlink-org/stlink/pull/845), [#931](https://github.com/stlink-org/stlink/pull/931)) +- Calculate checksums for flash operations ([#862](https://github.com/stlink-org/stlink/pull/862), [#924](https://github.com/stlink-org/stlink/pull/924)) +- Adjust the JTAG/SWD frequency via cmdline option ([#893](https://github.com/stlink-org/stlink/pull/893), [#953](https://github.com/stlink-org/stlink/pull/953)) +- Added usb PID and udev rules for STlink v2.1 found on Nucleo-L432KC and Nucleo-L552ze boards ([#900](https://github.com/stlink-org/stlink/pull/900)) +- STM32G0/G4 improvements ([#910](https://github.com/stlink-org/stlink/pull/910)) - Enable mass erase with a flash programming check - Handle G4 Cat3 devices with configurable dual bank flash by using a helper -- Display programmer serial when no target is connected (#432, #933, #943) Updates & changes: -- Define libusb version compatibility for supported operating systems via LIBUSB_API_VERSION (#211, #782, #895) -- Improved argument parsing for CLI tools (#378, #922) -- [doc] Updated tutorial: macOS ST-Link-v1 detection (#574, #587) -- Enhanced output for error msg "addr not a multiple of pagesize, not supported" (#663, #945) -- [doc] Verify correct udev configuration for device access (#764) -- Added more error info to WLOGs during probe (#883) -- Added check for libssp during compilation (#885) -- Silence unnecessary messages (#886) -- Set up a libusb log level accordingly to verbosity (commit 49f887d5247fdd28f163b6317790c4f087e652cc) -- [doc] Define libusb & cmake version compatibility (#896, #897, #899, commit 27aa88821197d3ffe82baff4e971c3488ec39899) -- Update for STM32G471/473/474/483/484 devices (#901) -- [doc] st-flash --flash=n[k][m] command line option to override device model (#902) -- [doc] Update compiling instructions (#113, commit 10ae5294cd03aacfc07312010f026d3cb12ea56c) -- [doc] Defined version compatibility and installation instructions for macOS (commit 23c071edea45f6e8852fef52d884a680973d6d8f) -- Deprecated old appveyor-mingw script (commit 97484422008df0f75c978627054776f35842a075) -- Enhanced error log with file path for map_file() (#650, #879, #921) -- [refactoring] Overall option code rework (#927) -- [refactoring] Build settings / GUI-Build on UNIX-based systems if GTK3 is detected (#929) -- [refactoring] Reconfiguration of package build process (#931, #936, #940, commit 9b19f9225460472af9d98959b7217d0a840ee972) -- [refactoring] st-util: Removed now useless v1/v2 STLink version stuff (#934) -- [refactoring] Cleanup for option bytes and flash settings (#941) -- Added compilation guideline for MSVC toolchain (#942) -- st-util: Removal of useless v1/v2 stlink version stuff (#934) -- libusb package extraction no longer requires 7zip as an external unarchiver (commit 5db2dc4c0410ace65308cddcc03d1c0cfa4855cf) -- [refactoring] Cleanup of cmake build process (#944, #946, #947) +- [doc] Update compiling instructions ([#113](https://github.com/stlink-org/stlink/pull/113), commit [#10ae529](https://github.com/stlink-org/stlink/commit/10ae5294cd03aacfc07312010f026d3cb12ea56c)) +- Define libusb version compatibility for supported operating systems via LIBUSB_API_VERSION ([#211](https://github.com/stlink-org/stlink/pull/211), [#782](https://github.com/stlink-org/stlink/pull/782), [#895](https://github.com/stlink-org/stlink/pull/895)) +- Improved argument parsing for CLI tools ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) +- [doc] Updated tutorial: macOS ST-Link-v1 detection ([#574](https://github.com/stlink-org/stlink/pull/574), [#587](https://github.com/stlink-org/stlink/pull/587)) +- Enhanced error log with file path for map_file() ([#650](https://github.com/stlink-org/stlink/pull/650), [#879](https://github.com/stlink-org/stlink/pull/879), [#921](https://github.com/stlink-org/stlink/pull/921)) +- Enhanced output for error msg "addr not a multiple of pagesize, not supported" ([#663](https://github.com/stlink-org/stlink/pull/663), [#945](https://github.com/stlink-org/stlink/pull/945)) +- [refactoring] Package distribution: Provide Windows binaries via Debian-based cross-build ([#738](https://github.com/stlink-org/stlink/pull/738), [#795](https://github.com/stlink-org/stlink/pull/795), [#798](https://github.com/stlink-org/stlink/pull/798), [#955](https://github.com/stlink-org/stlink/pull/955)) + - Update, corrections & cleanup for build settings (see #955 for details) + - New cpack package-config for DEB and RPM build + - Update for travis build configuration: builds for clang -m32, clang-9, MinGW-cross on linux + - Updated steps for release preparation + - Project contributors now listed in separate file + - Test files & gui now use shared stlink-library +- [doc] Verify correct udev configuration for device access ([#764](https://github.com/stlink-org/stlink/pull/764)) +- Added more error info to WLOGs during probe ([#883](https://github.com/stlink-org/stlink/pull/883)) +- [doc] Add missing documentation for stlink-gui ([#884](https://github.com/stlink-org/stlink/pull/884)) +- Added check for libssp during compilation ([#885](https://github.com/stlink-org/stlink/pull/885)) +- Silence unnecessary messages ([#886](https://github.com/stlink-org/stlink/pull/886)) +- [doc] Define libusb & cmake version compatibility ([#896](https://github.com/stlink-org/stlink/pull/896), [#897](https://github.com/stlink-org/stlink/pull/897), [#899](https://github.com/stlink-org/stlink/pull/899), commit [#27aa888](https://github.com/stlink-org/stlink/commit/27aa88821197d3ffe82baff4e971c3488ec39899)) +- Update for STM32G471/473/474/483/484 devices ([#901](https://github.com/stlink-org/stlink/pull/901)) +- [doc] st-flash --flash=n[k][m] command line option to override device model ([#902](https://github.com/stlink-org/stlink/pull/902)) +- [refactoring] BSD-License-compliant rewrite of flashloader source files ([#915](https://github.com/stlink-org/stlink/pull/915), [#932](https://github.com/stlink-org/stlink/pull/932)) +- [refactoring] Overall option code rework ([#927](https://github.com/stlink-org/stlink/pull/927)) +- [refactoring] Build settings / GUI-Build on UNIX-based systems if GTK3 is detected ([#929](https://github.com/stlink-org/stlink/pull/929)) +- [refactoring] Reconfiguration of package build process ([#931](https://github.com/stlink-org/stlink/pull/931), [#936](https://github.com/stlink-org/stlink/pull/936), [#940](https://github.com/stlink-org/stlink/pull/940), commit [#9b19f92](https://github.com/stlink-org/stlink/commit/9b19f9225460472af9d98959b7217d0a840ee972)) +- [refactoring] st-util: Removed now useless v1/v2 STLink version stuff ([#934](https://github.com/stlink-org/stlink/pull/934)) +- [refactoring] Cleanup for option bytes and flash settings ([#941](https://github.com/stlink-org/stlink/pull/941)) +- Added compilation guideline for MSVC toolchain ([#942](https://github.com/stlink-org/stlink/pull/942)) +- [refactoring] Cleanup of cmake build process ([#944](https://github.com/stlink-org/stlink/pull/944), [#946](https://github.com/stlink-org/stlink/pull/946), [#947](https://github.com/stlink-org/stlink/pull/947)) +- Set up a libusb log level accordingly to verbosity (commit [#49f887d](https://github.com/stlink-org/stlink/commit/49f887d5247fdd28f163b6317790c4f087e652cc)) +- [doc] Defined version compatibility and installation instructions for macOS (commit [#23c071e](https://github.com/stlink-org/stlink/commit/23c071edea45f6e8852fef52d884a680973d6d8f)) +- Deprecated old appveyor-mingw script (commit [#9748442](https://github.com/stlink-org/stlink/commit/97484422008df0f75c978627054776f35842a075)) +- libusb package extraction no longer requires 7zip as an external unarchiver (commit [#5db2dc4](https://github.com/stlink-org/stlink/commit/5db2dc4c0410ace65308cddcc03d1c0cfa4855cf)) + Fixes: -- Fixed wait-loop for flash_loader_run() (#290) -- Clear the PG bit before setting the PER bit (#579, #876) -- Fixed compilation issues with int length on 32-bit platforms (#629, #908) -- Fixed st-info --probe mechanism (#679, #918) -- Fixed sign-compare (size != rep_len) in usb.c (Regression) (#772, #869, #872, #891) -- Avoid re-define of O_BINARY on Windows (#788) -- Fixed st-flash manpage read example (#858) -- Fixed stlink support with no mass storage (#861) -- Make Version.cmake more error-resistant (#872) -- Error return in failed probe (#887, #890) -- Fixed formatting for options display in st-flash & st-info (commits c783d0e777ccc83a7a8be26a4f4d3414e0478560 and 562cd2496e696dbd22950925866aac662d81ee5f) -- Fixed dead loop after an unexpected unplug (#780, #812, #913) -- Fixed broken build on 32-bit systems (#919, #920) -- st-flash: Minor usage fix and make cmdline parsing more user friendly (#925) -- Better argument parsing for CLI tools: stlink_open_usb can address v1, v2, v3 (#378, #922) -- Restored functionality of make test builds (Regression) (#926, #929) -- Fixed compilation error due to uninitialized cpuid (#937, #938) +- Fixed wait-loop for flash_loader_run() ([#290](https://github.com/stlink-org/stlink/pull/290)) +- Better argument parsing for CLI tools: stlink_open_usb can address v1, v2, v3 ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) +- Clear the PG bit before setting the PER bit ([#579](https://github.com/stlink-org/stlink/pull/579), [#876](https://github.com/stlink-org/stlink/pull/876)) +- Fixed compilation issues with int length on 32-bit platforms ([#629](https://github.com/stlink-org/stlink/pull/629), [#908](https://github.com/stlink-org/stlink/pull/908)) +- Fixed st-info --probe mechanism ([#679](https://github.com/stlink-org/stlink/pull/679), [#918](https://github.com/stlink-org/stlink/pull/918)) +- [regression] Fixed sign-compare (size != rep_len) in usb.c ([#772](https://github.com/stlink-org/stlink/pull/772), [#869](https://github.com/stlink-org/stlink/pull/869), [#872](https://github.com/stlink-org/stlink/pull/872), [#891](https://github.com/stlink-org/stlink/pull/891)) +- Fixed dead loop after an unexpected unplug ([#780](https://github.com/stlink-org/stlink/pull/780), [#812](https://github.com/stlink-org/stlink/pull/812), [#913](https://github.com/stlink-org/stlink/pull/913)) +- Avoid re-define of O_BINARY on Windows ([#788](https://github.com/stlink-org/stlink/pull/788)) +- Fixed st-flash manpage read example ([#858](https://github.com/stlink-org/stlink/pull/858)) +- Fixed stlink support with no mass storage ([#861](https://github.com/stlink-org/stlink/pull/861)) +- Make Version.cmake more error-resistant ([#872](https://github.com/stlink-org/stlink/pull/872)) +- Error return in failed probe ([#887](https://github.com/stlink-org/stlink/pull/887), [#890](https://github.com/stlink-org/stlink/pull/890)) +- Fixed broken build on 32-bit systems ([#919](https://github.com/stlink-org/stlink/pull/919), [#920](https://github.com/stlink-org/stlink/pull/920)) +- st-flash: Minor usage fix and make cmdline parsing more user friendly ([#925](https://github.com/stlink-org/stlink/pull/925)) +- [regression] Restored functionality of make test builds ([#926](https://github.com/stlink-org/stlink/pull/926), [#929](https://github.com/stlink-org/stlink/pull/929)) +- Fixed compilation error due to uninitialized cpuid ([#937](https://github.com/stlink-org/stlink/pull/937), [#938](https://github.com/stlink-org/stlink/pull/938)) +- Fixes for STM32F0 flashloader ([#958](https://github.com/stlink-org/stlink/pull/958), [#959](https://github.com/stlink-org/stlink/pull/959) +- Set static link for libssp (stack-smashing protection) ([#960](https://github.com/stlink-org/stlink/pull/960), [#961](https://github.com/stlink-org/stlink/pull/961)) +- Fixed formatting for options display in st-flash & st-info (commits [#c783d0e](https://github.com/stlink-org/stlink/commit/c783d0e777ccc83a7a8be26a4f4d3414e0478560) and [#562cd24](https://github.com/stlink-org/stlink/commit/562cd2496e696dbd22950925866aac662d81ee5f)) v1.6.0 @@ -81,7 +97,7 @@ Release date: 2020-02-20 Major changes and added features: * Initial support for STM32L41X ([#754](https://github.com/stlink-org/stlink/pull/754), [#799](https://github.com/stlink-org/stlink/pull/799)) -* Working support for CKS32F103C8T6 and related CKS devices with Core-ID 0x2ba01477 ([#756](https://github.com/stlink-org/stlink/pull/756), [#757](https://github.com/stlink-org/stlink/pull/757), [#805](https://github.com/stlink-org/stlink/pull/805), [#834](https://github.com/stlink-org/stlink/pull/834), Regression-Fixes: [#761](https://github.com/stlink-org/stlink/pull/761), [#766](https://github.com/stlink-org/stlink/pull/766)) +* Verified support for CKS32F103C8T6 and related CKS devices with Core-ID 0x2ba01477 ([#756](https://github.com/stlink-org/stlink/pull/756), [#757](https://github.com/stlink-org/stlink/pull/757), [#805](https://github.com/stlink-org/stlink/pull/805), [#834](https://github.com/stlink-org/stlink/pull/834), Regression-Fixes: [#761](https://github.com/stlink-org/stlink/pull/761), [#766](https://github.com/stlink-org/stlink/pull/766)) * Added preliminary support for some STM32G0 chips ([#759](https://github.com/stlink-org/stlink/pull/759), [#760](https://github.com/stlink-org/stlink/pull/760), [#797](https://github.com/stlink-org/stlink/pull/797)) * Added support for mass erasing second bank on STM32F10x_XL ([#767](https://github.com/stlink-org/stlink/pull/767), [#768](https://github.com/stlink-org/stlink/pull/768)) * Added call to clear PG bit after writing to flash ([#773](https://github.com/stlink-org/stlink/pull/773)) @@ -155,7 +171,7 @@ Updates and fixes: * Disabled static library installation by default ([#702](https://github.com/stlink-org/stlink/pull/702)) * Fix for libusb deprecation ([#703](https://github.com/stlink-org/stlink/pull/703), [#704](https://github.com/stlink-org/stlink/pull/704)) * Renamed STLINK_CHIPID_STM32_L4R9 to STLINK_CHIPID_STM32_L4RX ([#706](https://github.com/stlink-org/stlink/pull/706)) -* Regression: stlink installation under Linux (Debian 9) is broken since #695 ([#700](https://github.com/stlink-org/stlink/pull/700), [#701](https://github.com/stlink-org/stlink/pull/701), [#707](https://github.com/stlink-org/stlink/pull/707)) +* [regression] stlink installation under Linux (Debian 9) is broken since #695 ([#700](https://github.com/stlink-org/stlink/pull/700), [#701](https://github.com/stlink-org/stlink/pull/701), [#707](https://github.com/stlink-org/stlink/pull/707)) * Fixed flash memory map for STM32F72xxx target ([#711](https://github.com/stlink-org/stlink/pull/711)) * Proper flash page size calculation for STM32F412xx target ([#721](https://github.com/stlink-org/stlink/pull/721)) * Return correct value on EOF for Semihosting SYS_READ ([#726](https://github.com/stlink-org/stlink/pull/726), [#727](https://github.com/stlink-org/stlink/pull/727), [#728](https://github.com/stlink-org/stlink/pull/728), [#729](https://github.com/stlink-org/stlink/pull/729), [#730](https://github.com/stlink-org/stlink/pull/730), [#731](https://github.com/stlink-org/stlink/pull/731), [#732](https://github.com/stlink-org/stlink/pull/732)) diff --git a/CMakeLists.txt b/CMakeLists.txt index c61b9b6bf..6b17fdc57 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -164,8 +164,7 @@ message(STATUS "STLINK_LIB_SHARED: ${STLINK_LIB_SHARED}") message(STATUS "PROJECT_VERSION_MAJOR: ${PROJECT_VERSION_MAJOR}") message(STATUS "VERSION: ${STLINK_SHARED_VERSION}") -set_target_properties( - ${STLINK_LIB_SHARED} PROPERTIES +set_target_properties(${STLINK_LIB_SHARED} PROPERTIES SOVERSION ${PROJECT_VERSION_MAJOR} VERSION ${STLINK_SHARED_VERSION} OUTPUT_NAME ${PROJECT_NAME} @@ -200,8 +199,7 @@ message(STATUS "STLINK_LIB_STATIC: ${STLINK_LIB_STATIC}") message(STATUS "PROJECT_VERSION_MAJOR: ${PROJECT_VERSION_MAJOR}") message(STATUS "VERSION: ${STLINK_STATIC_VERSION}") -set_target_properties( - ${STLINK_LIB_STATIC} PROPERTIES +set_target_properties(${STLINK_LIB_STATIC} PROPERTIES SOVERSION ${PROJECT_VERSION_MAJOR} VERSION ${STLINK_STATIC_VERSION} OUTPUT_NAME ${PROJECT_NAME} diff --git a/README.md b/README.md index 42ee63aa2..b2495840d 100644 --- a/README.md +++ b/README.md @@ -125,4 +125,4 @@ Here we would appreciate any help and would love to welcome new contributors who * Writing external memory connected to an STM32 controller (e.g Quad SPI NOR flash) ([#412](https://github.com/stlink-org/stlink/issues/412)) * MCU hotplug ([#449](https://github.com/stlink-org/stlink/issues/449)) * Writing options bytes (region) ([#458](https://github.com/stlink-org/stlink/issues/458)) -* Support for STLINKv3 programmer ([#820](https://github.com/stlink-org/stlink/issues/820)) +* Enhanced support for STLINKv3 programmer ([#820](https://github.com/stlink-org/stlink/issues/820)) From ea17f9ac77064e3c47b58fd014834f06bd763724 Mon Sep 17 00:00:00 2001 From: Geoffrey Brown Date: Fri, 22 May 2020 14:40:26 -0400 Subject: [PATCH 0938/1435] added connect under reset code --- .vscode/settings.json | 3 +++ src/usb.c | 5 +++-- src/usb.h | 2 +- tests/usb.c | 23 ++++++++++++++++++++--- 4 files changed, 27 insertions(+), 6 deletions(-) create mode 100644 .vscode/settings.json diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 000000000..cad7657df --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,3 @@ +{ + "cmake.configureOnOpen": false +} \ No newline at end of file diff --git a/src/usb.c b/src/usb.c index b986aed57..26243daa3 100644 --- a/src/usb.c +++ b/src/usb.c @@ -937,7 +937,7 @@ static stlink_backend_t _stlink_usb_backend = { _stlink_usb_set_swdclk }; -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq) { +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; int ret = -1; @@ -1145,9 +1145,10 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[ST break; } + if (reset == 2) stlink_jtag_reset(sl,0); if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); - if (reset) { + if (reset == 1) { if ( sl->version.stlink_v > 1) stlink_jtag_reset(sl, 2); stlink_reset(sl); usleep(10000); diff --git a/src/usb.h b/src/usb.h index 061042e8d..5c1f5b7ca 100644 --- a/src/usb.h +++ b/src/usb.h @@ -68,7 +68,7 @@ extern "C" { * @retval NULL Error while opening the stlink * @retval !NULL Stlink found and ready to use */ - stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq); + stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq); size_t stlink_probe_usb(stlink_t **stdevs[]); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); diff --git a/tests/usb.c b/tests/usb.c index 5165ea563..ce72e24a5 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -1,15 +1,32 @@ #include #include +#include + +static void usage(void) +{ + puts("test-usb --reset"); + puts("test-usb --no-reset"); +} int main(int ac, char** av) { - (void)ac; - (void)av; stlink_t* sl; struct stlink_reg regs; + int reset = 0; + + if (ac == 2) { + if (strcmp(av[1], "--reset") == 0) + reset = 2; + if (strcmp(av[1], "--no-reset") == 0) + reset = 1; + } + if (reset == 0) { + usage(); + return 0; + } - sl = stlink_open_usb(10, 1, NULL, 0); + sl = stlink_open_usb(10, reset, NULL, 0); if (sl != NULL) { printf("-- version\n"); stlink_version(sl); From ce0df3ba3c3ea211f343b1b83800d7a8161792e4 Mon Sep 17 00:00:00 2001 From: Geoffrey Brown Date: Fri, 22 May 2020 17:51:17 -0400 Subject: [PATCH 0939/1435] removed .vscode --- .vscode/settings.json | 3 --- 1 file changed, 3 deletions(-) delete mode 100644 .vscode/settings.json diff --git a/.vscode/settings.json b/.vscode/settings.json deleted file mode 100644 index cad7657df..000000000 --- a/.vscode/settings.json +++ /dev/null @@ -1,3 +0,0 @@ -{ - "cmake.configureOnOpen": false -} \ No newline at end of file From 25d0e56161d02014f77b9efd1a3fc66ef30f27b5 Mon Sep 17 00:00:00 2001 From: Geoffrey Brown Date: Sat, 23 May 2020 16:01:12 -0400 Subject: [PATCH 0940/1435] Added --connect-under-reset to st-flash and st-info --- include/stlink/tools/flash.h | 3 ++- src/tools/flash_opts.c | 3 +++ src/tools/info.c | 39 +++++++++++++++++++++++++----------- src/usb.c | 10 ++++++++- 4 files changed, 41 insertions(+), 14 deletions(-) diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index a912a14aa..3a4dc3ec4 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -27,9 +27,10 @@ struct flash_opts size_t flash_size; /* --flash=n[k][m] */ int opt; /* enable empty tail data drop optimization */ int freq; /* --freq=n[k][m] frequency of JTAG/SWD */ + bool connect_under_reset; }; -#define FLASH_OPTS_INITIALIZER {0, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +#define FLASH_OPTS_INITIALIZER {0, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} int flash_get_opts(struct flash_opts* o, int ac, char** av); diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index a5c9d287f..c8d7841de 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -225,6 +225,9 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { if (result != 0) return bad_arg ("--flash"); else o->flash_size = (size_t) flash_size; } + else if (strcmp(av[0],"--connect-under-reset")== 0){ + o->connect_under_reset = true; + } else { break; // non-option found } diff --git a/src/tools/info.c b/src/tools/info.c index 45d484270..8464d8632 100644 --- a/src/tools/info.c +++ b/src/tools/info.c @@ -11,11 +11,11 @@ static void usage(void) puts("st-info --probe"); puts("st-info --serial"); puts("st-info --hla-serial"); - puts("st-info --flash"); - puts("st-info --pagesize"); - puts("st-info --sram"); - puts("st-info --chipid"); - puts("st-info --descr"); + puts("st-info --flash [--connect-under-reset]"); + puts("st-info --pagesize [--connect-under-reset]"); + puts("st-info --sram [--connect-under-reset]"); + puts("st-info --chipid [--connect-under-reset]"); + puts("st-info --descr [--connect-under-reset]"); } /* Print normal or OpenOCD hla_serial with newline */ @@ -76,19 +76,25 @@ static void stlink_probe(void) stlink_probe_usb_free(&stdevs, size); } -static stlink_t *stlink_open_first(void) +static stlink_t *stlink_open_first(bool under_reset) { stlink_t* sl = NULL; sl = stlink_v1_open(0, 1); - if (sl == NULL) - sl = stlink_open_usb(0, 1, NULL, 0); - + if (sl == NULL) { + if (under_reset) { + sl = stlink_open_usb(0, 2, NULL, 0); + } else { + sl = stlink_open_usb(0, 1, NULL, 0); + } + } + return sl; } -static int print_data(char **av) +static int print_data(int ac, char **av) { stlink_t* sl = NULL; + bool under_reset = false; // Probe needs all devices unclaimed if (strcmp(av[1], "--probe") == 0) { @@ -99,7 +105,16 @@ static int print_data(char **av) return 0; } - sl = stlink_open_first(); + if (ac == 3) { + if (strcmp(av[2],"--connect-under-reset") == 0) { + under_reset = true; + } else { + usage(); + return -1; + } + } + + sl = stlink_open_first(under_reset); if (sl == NULL) { return -1; @@ -149,7 +164,7 @@ int main(int ac, char** av) return -1; } - err = print_data(av); + err = print_data(ac,av); return err; } diff --git a/src/usb.c b/src/usb.c index 26243daa3..a711749da 100644 --- a/src/usb.c +++ b/src/usb.c @@ -1145,7 +1145,15 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL break; } - if (reset == 2) stlink_jtag_reset(sl,0); + if (reset == 2) { + stlink_jtag_reset(sl,0); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); + stlink_force_debug(sl); + stlink_jtag_reset(sl,1); + usleep(10000); + } + + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); if (reset == 1) { From fd2a5c37d4e5b7886bef1157717ea64a611b7b5a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 25 May 2020 00:40:56 +0200 Subject: [PATCH 0941/1435] Minor formatting fixes & corrections --- README.md | 9 +++------ contributors.txt | 6 ++++++ doc/app-example/CMakeLists.txt | 7 ++++--- doc/app-example/README.md | 2 +- doc/app-example/main.c | 7 +++---- doc/devices_boards.md | 2 +- doc/release.md | 2 +- doc/version_support.md | 2 ++ run_clang_analyze.sh | 5 +++-- 9 files changed, 24 insertions(+), 18 deletions(-) diff --git a/README.md b/README.md index b2495840d..7dc634c9c 100644 --- a/README.md +++ b/README.md @@ -15,16 +15,13 @@ Recent new features and bugfixes can be found in the [Changelog](CHANGELOG.md) o #### License -The stlink library and tools are licensed under the **[BSD-3 License](LICENSE.md)**.
    -The source files **stm32l0x.s** and **stm32lx.s** found in the subdirectory `/flashloaders/` -are licensed under the **General Public License (GPL v2+)**. +The stlink library and tools are licensed under the **[BSD-3 License](LICENSE.md)**. ## Introduction STLink is an open source toolset to program and debug STM32 devices and boards manufactured by STMicroelectronics. -It supports several so called STLINK programmer boards (and clones thereof) which use a microcontroller chip -to translate commands from USB to JTAG/SWD. There are four generations available on the market: +It supports several so called STLINK programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG/SWD. There are four generations available on the market which are _all_ supported by this toolset: * **STLINK/v1** _(obsolete as of 21-11-2019)_ - transport layer: SCSI passthru commands over USB @@ -59,7 +56,7 @@ Supported operating systems are listed in [version_support.md](doc/version_suppo ## Tutorial & HOWTO -Our [tutorial.md](doc/tutorial.md) may help you along with some advanced tasks and additional info. +Our [tutorial](doc/tutorial.md) may help you along with some advanced tasks and additional info. ## Installation diff --git a/contributors.txt b/contributors.txt index 32c8e58e3..8811da855 100644 --- a/contributors.txt +++ b/contributors.txt @@ -37,6 +37,7 @@ Ethan Zonca Fabien Chouteau Florian Hars Friedrich Beckmann +Gabriel Górski [Glaeqen] Geoffrey Brown George Talusan [gtalusan] Georg von Zengen @@ -60,6 +61,7 @@ Jerome Lambourg Jim Paris Jiří Netolický Jerry Nosky [jnosky] +Jochen Wilhelmy [Jochen0x90h] Johannes Taelman Jonas Danielsson Jonas Norling @@ -68,6 +70,7 @@ Karl Palsson [karlp] Kevlar Harness Kyle Manna Lari Lehtomäki +Lutz Freitag [nerdmaennchen] Martin Nowak Matteo Collina Max Chen @@ -76,6 +79,7 @@ Maxime Vincent Michael Pratt [prattmic] Michael Sparmann Mike Szczys +Miklós Márton [martonmiklos] Magnus Lundin [mlu] mux Ned Konz @@ -89,6 +93,7 @@ orangeudav Pavel Kirienko Pekka Nikander Pete Nelson +Peter Torelli [petertorelli] Peter Zotov Petteri Aimonen Piotr Haber @@ -99,6 +104,7 @@ Rob Spanton Rytis Karpuska Sean Simmons Sergey Alirzaev +Simon Derr [sderr] Simon Wright Stany Marcel Stefan Misik diff --git a/doc/app-example/CMakeLists.txt b/doc/app-example/CMakeLists.txt index a7697720c..5f71a5d4f 100644 --- a/doc/app-example/CMakeLists.txt +++ b/doc/app-example/CMakeLists.txt @@ -6,17 +6,18 @@ cmake_minimum_required(VERSION 3.4.2) project(st-hello) set(PROJECT_VERSION 0.1) + set(SRCS main.c) +include_directories(${STLINK_INCLUDE_DIRS}) + find_package(PkgConfig) pkg_check_modules(STLINK REQUIRED stlink) set(CMAKE_C_FLAGS " ${STLINK_CFLAGS_OTHER} -Wall -Werror") -include_directories(${STLINK_INCLUDE_DIRS}) - add_executable(${PROJECT_NAME} ${SRCS}) target_link_libraries(${PROJECT_NAME} ${STLINK_LIBRARIES}) -install(TARGETS ${PROJECT_NAME} DESTINATION bin) +install(TARGETS ${PROJECT_NAME} DESTINATION ${CMAKE_INSTALL_BINDIR}) diff --git a/doc/app-example/README.md b/doc/app-example/README.md index 683056171..f3a0bf9bb 100644 --- a/doc/app-example/README.md +++ b/doc/app-example/README.md @@ -1,2 +1,2 @@ This is a simple standalone application example that uses libstlink. -You can use this as a boilerplate for your own app development +It can be used as a boilerplate for app development. diff --git a/doc/app-example/main.c b/doc/app-example/main.c index 12621434a..b8e64b259 100644 --- a/doc/app-example/main.c +++ b/doc/app-example/main.c @@ -2,8 +2,7 @@ #include #include -static stlink_t *stlink_open_first(void) -{ +static stlink_t *stlink_open_first(void) { stlink_t* sl = NULL; sl = stlink_v1_open(0, 1); if (sl == NULL) @@ -13,8 +12,7 @@ static stlink_t *stlink_open_first(void) } -int main() -{ +int main() { stlink_t* sl = NULL; sl = stlink_open_first(); @@ -25,5 +23,6 @@ int main() fprintf(stderr, "STlink device opened, that's cool!\n"); stlink_close(sl); + return 0; } diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 00acdd2cf..8291f7532 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -53,7 +53,7 @@ Tested boards [incl. STLink programmers]: | 0x430 | XL-Density | xF XG | | F101 | | F103 | | Tested boards [incl. STLink programmers]: -* 32VL-Discovery (STM32F100RBT6) with STLink-v1 [v1, v2] +* STM32VL-Discovery (STM32F100RBT6) with STLink-v1 [v1, v2] * STM32F103-Bluepill: C8Tx & R8xx [v2] * Nucleo-F103RB [v2-1] * HY-STM32 (STM32F103VETx) [v1, v2] diff --git a/doc/release.md b/doc/release.md index 4b536d95a..b44183b80 100644 --- a/doc/release.md +++ b/doc/release.md @@ -3,7 +3,7 @@ Release This document describes the necessary steps for developers to create a release: -1. Update `CHANGELOG.md` and `cmake/packaging/deb/changelog` +1. Update `CHANGELOG.md` 2. Update `.version` with semantic version: `x.x.x` 3. Update `README.md` with semantic version `x.x.x` in commits badge 4. Create and push git tag and commits `git tag x.x.x` diff --git a/doc/version_support.md b/doc/version_support.md index f889fbc32..4d1f724f7 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -21,6 +21,8 @@ Thus no user interaction regarding libusb is necessary. | homebrew | 1.0.23 | 3.17.0 | 3.24.18
    gtk+3 | 10.12 (Sierra)- 10.15 (Catalina) | | MacPorts | 1.0.23 | 3.17.0 | 3.24.18
    gtk3 | 10.6 (Snow Leopard) - 10.15 (Catalina) | +NOTE: In order to use a STLINK/v1 programmer on macOS, versions 10.13, 10.14 or 10.15 are required. + ### Linux-/Unix-based: diff --git a/run_clang_analyze.sh b/run_clang_analyze.sh index 8d5c5a988..fd1b78b55 100755 --- a/run_clang_analyze.sh +++ b/run_clang_analyze.sh @@ -1,6 +1,7 @@ #!/bin/bash -# Run this hacky script in project root directory to start -# clang static analysis. Adjust ccc-analyzer path if nesesary +# Run this hacky script in project root directory to start clang static analysis. +# Adjust ccc-analyzer path if necessary + CCC_ANALYZER=/usr/share/clang/scan-build-3.5/ccc-analyzer mkdir -p build-clang-analyze/reports cd build-clang-analyze From 252ac0b3cc0690d8d2e26c117ca178f481e9fdb2 Mon Sep 17 00:00:00 2001 From: matthew sherwood Date: Mon, 25 May 2020 15:33:44 -0400 Subject: [PATCH 0942/1435] Update compiling.md neither `make release` nor `make debug` would execute properly on a fresh clone of the directory until i ran `make clean`. system is linux mint - 5.3.0-53-generic #47~18.04.1-Ubuntu SMP Thu May 7 13:10:50 UTC 2020 x86_64 x86_64 x86_64 GNU/Linux --- doc/compiling.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index e20cbca83..2da79f071 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -110,8 +110,9 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma ### Building 1. Change into the project source directory: `cd stlink` -2. Run `make release` to create the _Release_ target -3. Run `make debug` to create the _Debug_ target (_optional_)
    +2. Run `make clean` -- required by some linux variants. +3. Run `make release` to create the _Release_ target +4. Run `make debug` to create the _Debug_ target (_optional_)
    The debug target is only necessary in order to modify the sources and to run under a debugger. The top level Makefile is just a handy wrapper for: From 230497c1a457673be20b18e6e3453a4104075133 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 26 May 2020 13:58:56 +0200 Subject: [PATCH 0943/1435] Updated stlink-v1 driver for macOS - Updated xcode project settings v11.3.1 - Removed support for 10.6-10.12 - Compiled new kexts for macOS 10.13-10.15 - Moved instructions to separate README - Updated installation instructions --- doc/tutorial.md | 65 +- .../Makefile | 25 +- stlinkv1_macos_driver/README.md | 50 ++ stlinkv1_macos_driver/install.sh | 22 + .../Contents/Info.plist | 82 +++ .../Contents/MacOS/stlink_shield_10_13 | Bin 0 -> 33840 bytes .../stlink_shield_10_13.kext/Contents/PkgInfo | 1 + .../Contents/_CodeSignature/CodeResources | 115 ++++ .../Contents/Info.plist | 82 +++ .../Contents/MacOS/stlink_shield_10_14 | Bin 0 -> 33840 bytes .../stlink_shield_10_14.kext/Contents/PkgInfo | 1 + .../Contents/_CodeSignature/CodeResources | 115 ++++ .../Contents/Info.plist | 82 +++ .../Contents/MacOS/stlink_shield_10_15 | Bin 0 -> 33840 bytes .../stlink_shield_10_15.kext/Contents/PkgInfo | 1 + .../Contents/_CodeSignature/CodeResources | 115 ++++ .../stlink_shield_xcode/Info.plist | 60 ++ .../stlink_shield.xcodeproj/project.pbxproj | 613 ++++++++++++++++++ .../contents.xcworkspacedata | 7 + .../xcshareddata/IDEWorkspaceChecks.plist | 8 + .../xcshareddata/WorkspaceSettings.xcsettings | 8 + .../UserInterfaceState.xcuserstate | Bin 0 -> 185319 bytes .../WorkspaceSettings.xcsettings | 22 + .../xcschemes/stlink_shield_10.13.xcscheme | 67 ++ .../xcschemes/stlink_shield_10.14.xcscheme | 67 ++ .../xcschemes/stlink_shield_10.15.xcscheme | 67 ++ .../xcschemes/xcschememanagement.plist | 67 ++ stlinkv1_macosx_driver/README.md | 47 -- stlinkv1_macosx_driver/osx.tar.gz | Bin 23580 -> 0 bytes 29 files changed, 1666 insertions(+), 123 deletions(-) rename {stlinkv1_macosx_driver => stlinkv1_macos_driver}/Makefile (74%) create mode 100644 stlinkv1_macos_driver/README.md create mode 100644 stlinkv1_macos_driver/install.sh create mode 100644 stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/Info.plist create mode 100644 stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/MacOS/stlink_shield_10_13 create mode 100644 stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/PkgInfo create mode 100644 stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/_CodeSignature/CodeResources create mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist create mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/MacOS/stlink_shield_10_14 create mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/PkgInfo create mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/_CodeSignature/CodeResources create mode 100644 stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/Info.plist create mode 100644 stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/MacOS/stlink_shield_10_15 create mode 100644 stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/PkgInfo create mode 100644 stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/_CodeSignature/CodeResources create mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/Info.plist create mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj create mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/contents.xcworkspacedata create mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/xcshareddata/IDEWorkspaceChecks.plist create mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/xcshareddata/WorkspaceSettings.xcsettings create mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/xcuserdata/vm-user.xcuserdatad/UserInterfaceState.xcuserstate create mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/xcuserdata/vm-user.xcuserdatad/WorkspaceSettings.xcsettings create mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.13.xcscheme create mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.14.xcscheme create mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.15.xcscheme create mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist delete mode 100644 stlinkv1_macosx_driver/README.md delete mode 100644 stlinkv1_macosx_driver/osx.tar.gz diff --git a/doc/tutorial.md b/doc/tutorial.md index 694142184..81315dbef 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -29,70 +29,7 @@ Within the GUI main window tooltips explain the available user elements. ## Solutions to common problems -### a) STLINK/v1 driver: Issue with Kernel Extension (kext) (macOS 10.11 and later only) -#### Problem: - -st-util fails to detect a STLINK/v1 device: - -``` -st-util -1 -st-util $VERSION-STRING$ -WARN src/sg.c: Failed to find an stlink v1 by VID:PID -ERROR src/sg.c: Could not open stlink device -``` - -#### Solution (clean setup): - -1) Configure System Integrity Protection (SIP) - -The root of this problem is a system security setting introduced by Apple with OS X El Capitan (10.11) in 2015. -The so called System Integrity Protection (SIP) is active per default -and prevents the operating system amongst other things to load unsigned Kernel Extension Modules (kext). -Thus the STLINK/v1 driver supplied with the tools, which installs as a kext, remains not functional, -while SIP is fully activated (as is per default). - -Action needs to be taken here by booting into the recovery mode where a terminal console window needs to be opened. - -For macOS 10.11 - 10.13 it is not recommended to disable SIP completely as with the command `csrutil disable`, -because this leaves the system more vulnerable to common threats. -Instead there is a more adequate and reasonable option implemented by Apple. -Running `csrutil enable --without kext`, allows to load unsigned kernel extensions -while leaving SIP active with all other security features. -Unfortunately this option has been removed in macOS 10.14, which leaves the only option to disable SIP completely. - -So who ever intends to run the STLINK/v1 programmer on macOS please take this into account. - -Further details can be found here: https://forums.developer.apple.com/thread/17452 - -2) Install the ST-Link-v1 driver from the subdirectory `/stlinkv1_macosx_driver` - by referring to the instructions in the README file available there. - -3) Move the $OS_VERSION$.kext file to `/System/Library/Extensions`. - -4) Load the Kernel Extension (kext): `$ sudo kextload -v /System/Library/Extensions/stlink_shield10_x.kext` - -``` -Requesting load of /System/Library/Extensions/stlink_shield10_x.kext. -/System/Library/Extensions/stlink_shield10_x.kext loaded successfully (or already loaded). -``` - -5) Enter the command `$ sudo touch /System/Library/Extensions` - - -7) Verify correct detection of the STLINK/v1 device with the following input: `st-util -1` - -You should then see a similar output like in this example: - -``` -INFO common.c: Loading device parameters.... -INFO common.c: Device connected is: F1 High-density device, id 0x10036414 -INFO common.c: SRAM size: 0x10000 bytes (64 KiB), Flash: 0x80000 bytes (512 KiB) in pages of 2048 bytes -INFO sg.c: Successfully opened a stlink v1 debugger -INFO gdb-server.c: Chip ID is 00000414, Core ID is 1ba01477. -INFO gdb-server.c: Listening at *:4242... -``` - -### b) Verify if udev rules are set correctly (by Dave Hylands) +### a) Verify if udev rules are set correctly (by Dave Hylands) To investigate, start by plugging your STLINK device into the usb port. Then run `lsusb`. You should see an entry something like the following: diff --git a/stlinkv1_macosx_driver/Makefile b/stlinkv1_macos_driver/Makefile similarity index 74% rename from stlinkv1_macosx_driver/Makefile rename to stlinkv1_macos_driver/Makefile index 9947ff672..e6ba6309b 100644 --- a/stlinkv1_macosx_driver/Makefile +++ b/stlinkv1_macos_driver/Makefile @@ -1,15 +1,17 @@ -# make ... for both stlink v1 and stlink v2 support -## +### +# Makefile for STlink-v1 support +### + VPATH=src -SOURCES_LIB=stlink-common.c stlink-usb.c stlink-sg.c uglylogging.c +SOURCES_LIB=common.c usb.c sg.c logging.c OBJS_LIB=$(SOURCES_LIB:.c=.o) -TEST_PROGRAMS=test_usb test_sg +TEST_PROGRAMS=test-flash test-sg test-usb LDFLAGS=-L. -lstlink -lusb-1.0 CFLAGS+=-g CFLAGS+=-DDEBUG=1 -CFLAGS+=-std=gnu99 +CFLAGS+=-std=gnu11 CFLAGS+=-Wall -Wextra @@ -20,8 +22,8 @@ all: $(LIBRARY) flash gdbserver $(TEST_PROGRAMS) $(LIBRARY): $(OBJS_LIB) @echo "objs are $(OBJS_LIB)" $(AR) -cr $@ $^ - @echo "done making library" - + @echo "Compilation of library completed." + test_sg: test_sg.o $(LIBRARY) @echo "building test_sg" @@ -40,18 +42,17 @@ test_usb: test_usb.o $(LIBRARY) clean: rm -rf $(OBJS_LIB) rm -rf $(LIBRARY) - rm -rf test_usb* - rm -rf test_sg* + rm -rf test-flash* test-sg* test-usb* $(MAKE) -C flash clean $(MAKE) -C gdbserver clean - + flash: $(MAKE) -C flash gdbserver: $(MAKE) -C gdbserver CONFIG_USE_LIBSG="$(CONFIG_USE_LIBSG)" -osx_stlink_shield: - ./osx/install.sh +macos_stlink_shield: + ./install.sh .PHONY: clean all flash gdbserver diff --git a/stlinkv1_macos_driver/README.md b/stlinkv1_macos_driver/README.md new file mode 100644 index 000000000..ca4a3da30 --- /dev/null +++ b/stlinkv1_macos_driver/README.md @@ -0,0 +1,50 @@ +### +# Installation instructions for STLINK/v1 driver +### + +When connecting to the STLINK/v1 on macOS via USB, the system claims the programmer as a SCSI device. Thus libusb is not able to initialise and establish a connection to it. To solve this issue Marco Cassinerio (marco.cassinerio@gmail.com) has created a so called "codeless driver" which claims the device. It is of higher priority then the default apple mass storage driver, what allows the device to be accessed through libusb. + +To make use of this alternative approach one needs to go through the following steps: + +1) Install the macOS Kernel Extension (kext): + - Open a terminal console and navigate to this subdirectory `/stlinkv1_macos_driver` + - Use the command ```sudo sh ./install.sh``` to install the appropiate kext for your system version. + +2) Install the ST-Link-v1 driver from this subdirectory `/stlinkv1_macos_driver` by executing: ```sudo make osx_stlink_shield```. This should result in the following output: + +``` +Requesting load of /System/Library/Extensions/stlink_shield.kext. +/System/Library/Extensions/stlink_shield.kext loaded successfully (or already loaded). +``` + +3) Configure System Integrity Protection (SIP) + +The above system security setting introduced by Apple with OS X El Capitan (10.11) in 2015 is active per default +and prevents the operating system amongst other things to load unsigned Kernel Extension Modules (kext). +Thus the STLINK/v1 driver supplied with the tools, which installs as a kext, remains not functional, +until SIP is fully deactivated. + +Without SIP-deactivation, st-util fails to detect a STLINK/v1 device: + +``` +st-util -1 +st-util $VERSION-STRING$ +WARN src/sg.c: Failed to find an stlink v1 by VID:PID +ERROR src/sg.c: Could not open stlink device +``` + +In order to deactivate SIP, boot into the recovery mode and run ```csrutil disable``` in a terminal console window. + +4) Reboot the system. + +5) Verify correct detection of the STLINK/v1 device with the following input: `st-util -1` +You should then see a similar output like in this example: + +``` +INFO common.c: Loading device parameters.... +INFO common.c: Device connected is: F1 High-density device, id 0x10036414 +INFO common.c: SRAM size: 0x10000 bytes (64 KiB), Flash: 0x80000 bytes (512 KiB) in pages of 2048 bytes +INFO sg.c: Successfully opened a stlink v1 debugger +INFO gdb-server.c: Chip ID is 00000414, Core ID is 1ba01477. +INFO gdb-server.c: Listening at *:4242... +``` diff --git a/stlinkv1_macos_driver/install.sh b/stlinkv1_macos_driver/install.sh new file mode 100644 index 000000000..9e5f8d813 --- /dev/null +++ b/stlinkv1_macos_driver/install.sh @@ -0,0 +1,22 @@ +#!/bin/bash + +ISMACOS=$(sw_vers -productVersion) +case $ISMACOS in +10.13*) + KEXT="stlink_shield_10_13.kext" + ;; +10.14*) + KEXT="stlink_shield_10_14.kext" + ;; +10.15*) + KEXT="stlink_shield_10_15.kext" + ;; +*) + echo "OS X version not supported." + exit 1 + ;; +esac +chown -R root:wheel $KEXT/ +cp -R $KEXT /System/Library/Extensions/stlink_shield.kext +kextload -v /System/Library/Extensions/stlink_shield.kext +touch /System/Library/Extensions diff --git a/stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/Info.plist b/stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/Info.plist new file mode 100644 index 000000000..fc759b362 --- /dev/null +++ b/stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/Info.plist @@ -0,0 +1,82 @@ + + + + + BuildMachineOSBuild + 18G4032 + CFBundleDevelopmentRegion + English + CFBundleIdentifier + com.libusb.stlink-shield + CFBundleInfoDictionaryVersion + 6.0 + CFBundlePackageType + KEXT + CFBundleSignature + ???? + CFBundleSupportedPlatforms + + MacOSX + + CFBundleVersion + 1.0.0 + DTCompiler + com.apple.compilers.llvm.clang.1_0 + DTPlatformBuild + 11C504 + DTPlatformVersion + GM + DTSDKBuild + 19B90 + DTSDKName + macosx10.15 + DTXcode + 1130 + DTXcodeBuild + 11C504 + IOKitPersonalities + + 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diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/xcuserdata/vm-user.xcuserdatad/WorkspaceSettings.xcsettings b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/xcuserdata/vm-user.xcuserdatad/WorkspaceSettings.xcsettings new file mode 100644 index 000000000..e097e4fe6 --- /dev/null +++ b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/xcuserdata/vm-user.xcuserdatad/WorkspaceSettings.xcsettings @@ -0,0 +1,22 @@ + + + + + BuildLocationStyle + UseAppPreferences + CustomBuildIntermediatesPath + Build/Intermediates.noindex + CustomBuildLocationType + RelativeToDerivedData + CustomBuildProductsPath + Build/Products + DerivedDataLocationStyle + Default + IssueFilterStyle + ShowActiveSchemeOnly + LiveSourceIssuesEnabled + + SharedBuildFolderName + Build + + diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.13.xcscheme b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.13.xcscheme new file mode 100644 index 000000000..d98dd9b97 --- /dev/null +++ b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.13.xcscheme @@ -0,0 +1,67 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.14.xcscheme b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.14.xcscheme new file mode 100644 index 000000000..79299d7a5 --- /dev/null +++ b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.14.xcscheme @@ -0,0 +1,67 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.15.xcscheme b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.15.xcscheme new file mode 100644 index 000000000..e72a90366 --- /dev/null +++ b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.15.xcscheme @@ -0,0 +1,67 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist new file mode 100644 index 000000000..d23112ec9 --- /dev/null +++ b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist @@ -0,0 +1,67 @@ + + + + + SchemeUserState + + stlink_shield 10.7.xcscheme_^#shared#^_ + + orderHint + 2 + + stlink_shield copy copy.xcscheme_^#shared#^_ + + orderHint + 3 + + stlink_shield copy.xcscheme_^#shared#^_ + + orderHint + 2 + + stlink_shield.xcscheme_^#shared#^_ + + orderHint + 1 + + stlink_shield_10.13.xcscheme_^#shared#^_ + + orderHint + 0 + + stlink_shield_10.14 copy.xcscheme_^#shared#^_ + + orderHint + 4 + + stlink_shield_10.14.xcscheme_^#shared#^_ + + orderHint + 1 + + stlink_shield_10.15.xcscheme_^#shared#^_ + + orderHint + 2 + + + SuppressBuildableAutocreation + + 8F9084E724786F0B009109AD + + primary + + + 8F9084F324786F0F009109AD + + primary + + + 8F9084FF24786F39009109AD + + primary + + + + + diff --git a/stlinkv1_macosx_driver/README.md b/stlinkv1_macosx_driver/README.md deleted file mode 100644 index b2a68442c..000000000 --- a/stlinkv1_macosx_driver/README.md +++ /dev/null @@ -1,47 +0,0 @@ -from: marco.cassinerio@gmail.com - -to: texane@gmail.com - -Hi, - -i managed to get the stlink v1 working under os x and i would like to share the solution so maybe you can add it in your package. -The problem is that os x claims the device as scsi and libusb won't be able to connect to it. -I've created what is called a codeless driver which claims the device and has a higher priority then the default apple mass storage driver, so the device can be accessed through libusb. - -I tested this codeless driver under OS X 10.6.8 and 10.7.2. -I assume it works with any 10.6.x and 10.7.x version as well. - -Attached to this mail you'll find the osx folder with the source code of the driver, both drivers (for 10.6.x and 10.7.x), an install.sh script and the modified Makefile, i only added a line at the end which invoke the `install.sh`. - -First, unpack the `osx.tar.gz` contents: -```bash -tar xzvf osx.tar.gz -``` - -Then, install the driver using: -```bash -sudo make osx_stlink_shield -``` - -no reboot required. - -P.S. If error `OS X version not supported` occurs. For the latest versions of Mac OS X you may need to change the `osx/install.sh` as follows: -```bash -< ISOSXLION=$(sw_vers -productVersion) ---- -> ISOSXLION=$(sw_vers -productVersion | sed -e 's:.[[:digit:]]*$::') -``` - -### OS X 10.10 Yosemite - -For OS X 10.10 Yosemite you must force the system to load unsigned kernelextensions - -```bash -sudo nvram boot-args="kext-dev-mode=1" -``` - -reboot the system! - -### OS X 10.11 El Capitan - -For OS X 10.11 El Capitan: the Yosemite kext seems to work (tested on 10.11.04). diff --git a/stlinkv1_macosx_driver/osx.tar.gz b/stlinkv1_macosx_driver/osx.tar.gz deleted file mode 100644 index 57bc314668c66f849b8fdcd50a5e38a430cac624..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 23580 zcmZ^~V|1o5`z>DEwx-6^wr$&(+HRk^Q`@%fsohR(d#b7J=Q;Df=l93?aK2p0o$QsJ zmE2itCu?7%F>qjVE`l0hkXOB1$rQ5bWHQUkk6N!XQ>#Cx6*{J;bkKR#({N$C2{kON zsBjiN@W5@{0Dwt<6aJ5F9AjSFQ)jOH{o6Zjr-{7(jCu_VQppgxx;)l)U^OJx%+G}$b~H7vx@ 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z^b$4}E|{bOvR+l7Mt?tPE68rEI6VU~2H4}g?9Ho!Dey64_NhWK7&XEuWT-iQT?mwb z{z>Lk^nx71hT^tmVv3dKMK%UY>hznc{swaj8(Q(Jf4#D40ZL;5$zJB~TIHe3teGsF&|mIBQ{|BlgSBpFFszXV-_zP`F{gBZ;X+FoX?8eMnHgD zstvOkjA8TtCy?`)V2okkiU-4Ag**?1*owc+sOfTP#n!gkA~piLGv5|pSJiU3SWZKF zdu zVK3wmv%L$s zi&*kYIG(M2)sEOtI6&O~4CvqF16YKrif>q8J!R+X|G@Vj>6>7kv`4pZLmU|{GY5xw zZpCT>0jua|oZ;7KPT3s+pN0$yGY!zrh}I5N(cyruH+{b70S1|bTVG^WXndQ4M+I+r zLp?|Nj7o%MnnDl(?5niOi|~LSh*=Ar^;-lvGG$VI<3`px51~Fmzv0-2%-*C%W^&U0 zLWqkYXrsOj8wdW{M{6n4Tr=qa!O;?{Ub|rIE#Y7CsWtBeSo;RB+E*Y#?t6a)P%*)* zZj=0w55(`IEs$TfsItgqRQiy|y(I5_x&<(P=^nikdC`IJ<99^--@of${_fpLMTBGy M^A0x(5eCYC0W6&Nj{pDw From 3e49becc2f20f2b62cff266f12f4f99d6101446f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 27 May 2020 12:35:05 +0200 Subject: [PATCH 0944/1435] Corrected udev & modprobe install directories (Fixes #966) --- CMakeLists.txt | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 6b17fdc57..b660e0f23 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -255,12 +255,12 @@ install(TARGETS st-util DESTINATION ${CMAKE_INSTALL_BINDIR}) ### if (CMAKE_SYSTEM_NAME STREQUAL "Linux") - ## Install modprobe.d conf files / rules to /usr/local/etc/stlink (default) - set(STLINK_MODPROBED_DIR "${CMAKE_INSTALL_SYSCONFDIR}/${PROJECT_NAME}/modprobe.d" CACHE PATH "modprobe.d directory") + ## Install modprobe.d conf files to /etc/modprobe.d/ (explicitly hardcoded) + set(STLINK_MODPROBED_DIR "/etc/modprobe.d" CACHE PATH "modprobe.d directory") install(FILES ${CMAKE_SOURCE_DIR}/config/modprobe.d/stlink_v1.conf DESTINATION ${STLINK_MODPROBED_DIR}) - ## Install udev rules files / rules to /usr/local/etc/stlink (default) - set(STLINK_UDEV_RULES_DIR "${CMAKE_INSTALL_SYSCONFDIR}/${PROJECT_NAME}/udev/rules.d" CACHE PATH "udev rules directory") + ## Install udev rules files to /etc/udev/rules.d/ (explicitly hardcoded) + set(STLINK_UDEV_RULES_DIR "/etc/udev/rules.d" CACHE PATH "udev rules directory") file(GLOB RULES_FILES ${CMAKE_SOURCE_DIR}/config/udev/rules.d/*.rules) install(FILES ${RULES_FILES} DESTINATION ${STLINK_UDEV_RULES_DIR}) endif () From 4337408e0413e61b74be90fe46f9b0336acc7215 Mon Sep 17 00:00:00 2001 From: rutgerhendriks <3134550+rutgerhendriks@users.noreply.github.com> Date: Wed, 27 May 2020 15:59:44 +0200 Subject: [PATCH 0945/1435] Create ccpp.yml --- .github/workflows/ccpp.yml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 .github/workflows/ccpp.yml diff --git a/.github/workflows/ccpp.yml b/.github/workflows/ccpp.yml new file mode 100644 index 000000000..23aa0bfc5 --- /dev/null +++ b/.github/workflows/ccpp.yml @@ -0,0 +1,17 @@ +name: C/C++ CI + +on: + push: + branches: [ master ] + pull_request: + branches: [ master ] + +jobs: + build: + + runs-on: ubuntu-latest + + steps: + - uses: actions/checkout@v2 + - name: make + run: make From 71011a3e7dec751f193556881507eb213f1da6b2 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 27 May 2020 21:50:45 +0200 Subject: [PATCH 0946/1435] Updated README for STLink-v1 setup on macOS --- stlinkv1_macos_driver/README.md | 38 +++++++++++---------------------- 1 file changed, 13 insertions(+), 25 deletions(-) diff --git a/stlinkv1_macos_driver/README.md b/stlinkv1_macos_driver/README.md index ca4a3da30..7221732c0 100644 --- a/stlinkv1_macos_driver/README.md +++ b/stlinkv1_macos_driver/README.md @@ -1,43 +1,31 @@ -### # Installation instructions for STLINK/v1 driver -### When connecting to the STLINK/v1 on macOS via USB, the system claims the programmer as a SCSI device. Thus libusb is not able to initialise and establish a connection to it. To solve this issue Marco Cassinerio (marco.cassinerio@gmail.com) has created a so called "codeless driver" which claims the device. It is of higher priority then the default apple mass storage driver, what allows the device to be accessed through libusb. To make use of this alternative approach one needs to go through the following steps: -1) Install the macOS Kernel Extension (kext): - - Open a terminal console and navigate to this subdirectory `/stlinkv1_macos_driver` - - Use the command ```sudo sh ./install.sh``` to install the appropiate kext for your system version. - -2) Install the ST-Link-v1 driver from this subdirectory `/stlinkv1_macos_driver` by executing: ```sudo make osx_stlink_shield```. This should result in the following output: - -``` -Requesting load of /System/Library/Extensions/stlink_shield.kext. -/System/Library/Extensions/stlink_shield.kext loaded successfully (or already loaded). -``` - -3) Configure System Integrity Protection (SIP) +1) Configure System Integrity Protection (SIP) The above system security setting introduced by Apple with OS X El Capitan (10.11) in 2015 is active per default and prevents the operating system amongst other things to load unsigned Kernel Extension Modules (kext). Thus the STLINK/v1 driver supplied with the tools, which installs as a kext, remains not functional, -until SIP is fully deactivated. +until SIP is fully deactivated. Without SIP-deactivation, st-util would fail to detect a STLINK/v1 device later on. -Without SIP-deactivation, st-util fails to detect a STLINK/v1 device: +In order to deactivate SIP, boot into the recovery mode and run ```csrutil disable``` in a terminal console window. -``` -st-util -1 -st-util $VERSION-STRING$ -WARN src/sg.c: Failed to find an stlink v1 by VID:PID -ERROR src/sg.c: Could not open stlink device -``` +2) Reboot the system. -In order to deactivate SIP, boot into the recovery mode and run ```csrutil disable``` in a terminal console window. +3) Install the macOS Kernel Extension (kext) (ST-Link-v1 driver): + - Open a terminal console and navigate to this subdirectory `/stlinkv1_macos_driver` + - Use the command ```sudo sh ./install.sh``` to install the appropiate kext for your system version. + This should result in the following output: -4) Reboot the system. +``` +Requesting load of /System/Library/Extensions/stlink_shield.kext. +/System/Library/Extensions/stlink_shield.kext loaded successfully (or already loaded). +``` -5) Verify correct detection of the STLINK/v1 device with the following input: `st-util -1` +4) Verify correct detection of the STLINK/v1 device with the following input: `st-util -1` You should then see a similar output like in this example: ``` From 9b6cd7f99ba33fe7f783cbdc49bddafeee017ca8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 28 May 2020 11:09:32 +0200 Subject: [PATCH 0947/1435] General Project Update - Updated CHANGELOG - Corrected instructions for udev & STLink-v1 --- CHANGELOG.md | 134 +++++++++++++++++++++++++---------------------- doc/compiling.md | 22 ++++---- 2 files changed, 81 insertions(+), 75 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index b6b63e156..94c47e8fb 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -4,89 +4,98 @@ stlink ChangeLog v1.6.1 ====== -Release date: (TBD) +Release date: 2020-06-xx This release drops support for some older operating systems. Check project README for details. Features: -- Basic compatibility for STLink-v3 programmer ([#271](https://github.com/stlink-org/stlink/pull/271), [#863](https://github.com/stlink-org/stlink/pull/863), [#954](https://github.com/stlink-org/stlink/pull/954)) +* Basic compatibility for STLink-v3 programmer ([#271](https://github.com/stlink-org/stlink/pull/271), [#863](https://github.com/stlink-org/stlink/pull/863), [#954](https://github.com/stlink-org/stlink/pull/954)) - Added support for JTAG command API v2 & distinguish protocol versions v1 and v2 - Compatibility with the STLink-v3 firmware which dropped support for the previous API v1 - As of firmware version J11 the ST-LINK-V1 programmer supports API v2 commands as well -- Display programmer serial when no target is connected ([#432](https://github.com/stlink-org/stlink/pull/432), [#933](https://github.com/stlink-org/stlink/pull/933), [#943](https://github.com/stlink-org/stlink/pull/943)) -- Support for STM32L1, SM32L4 option bytes write ([#596](https://github.com/stlink-org/stlink/pull/596), [#844](https://github.com/stlink-org/stlink/pull/844), [#847](https://github.com/stlink-org/stlink/pull/847)) -- CMake now creates an uninstall target ([#619](https://github.com/stlink-org/stlink/pull/619), [#907](https://github.com/stlink-org/stlink/pull/907)) -- Added CMAKEFLAGS and install target ([#804](https://github.com/stlink-org/stlink/pull/804), [#935](https://github.com/stlink-org/stlink/pull/935)) -- Support for STM32G4 ([#822](https://github.com/stlink-org/stlink/pull/822)) -- Add aliased SRAM2 region in the L496 memory map ([#824](https://github.com/stlink-org/stlink/pull/824)) -- Improved support for STM32G0 ([#825](https://github.com/stlink-org/stlink/pull/825), [#850](https://github.com/stlink-org/stlink/pull/850), [#856](https://github.com/stlink-org/stlink/pull/856), [#857](https://github.com/stlink-org/stlink/pull/857)) -- Added postinst script with 'depmod -a' for 'make package' ([#845](https://github.com/stlink-org/stlink/pull/845), [#931](https://github.com/stlink-org/stlink/pull/931)) -- Calculate checksums for flash operations ([#862](https://github.com/stlink-org/stlink/pull/862), [#924](https://github.com/stlink-org/stlink/pull/924)) -- Adjust the JTAG/SWD frequency via cmdline option ([#893](https://github.com/stlink-org/stlink/pull/893), [#953](https://github.com/stlink-org/stlink/pull/953)) -- Added usb PID and udev rules for STlink v2.1 found on Nucleo-L432KC and Nucleo-L552ze boards ([#900](https://github.com/stlink-org/stlink/pull/900)) -- STM32G0/G4 improvements ([#910](https://github.com/stlink-org/stlink/pull/910)) +* Display programmer serial when no target is connected ([#432](https://github.com/stlink-org/stlink/pull/432), [#933](https://github.com/stlink-org/stlink/pull/933), [#943](https://github.com/stlink-org/stlink/pull/943)) +* Added connect under reset to stlink_open_usb( ) ([#577](https://github.com/stlink-org/stlink/pull/577), [#963](https://github.com/stlink-org/stlink/pull/963)) +* Support for STM32L1, SM32L4 option bytes write ([#596](https://github.com/stlink-org/stlink/pull/596), [#844](https://github.com/stlink-org/stlink/pull/844), [#847](https://github.com/stlink-org/stlink/pull/847)) +* Added CMAKEFLAGS and install target ([#804](https://github.com/stlink-org/stlink/pull/804), [#935](https://github.com/stlink-org/stlink/pull/935)) +* Support for STM32G4 ([#822](https://github.com/stlink-org/stlink/pull/822)) +* Add aliased SRAM2 region in the L496 memory map ([#824](https://github.com/stlink-org/stlink/pull/824)) +* Improved support for STM32G0 ([#825](https://github.com/stlink-org/stlink/pull/825), [#850](https://github.com/stlink-org/stlink/pull/850), [#856](https://github.com/stlink-org/stlink/pull/856), [#857](https://github.com/stlink-org/stlink/pull/857)) +* Added postinst script with 'depmod -a' for 'make package' ([#845](https://github.com/stlink-org/stlink/pull/845), [#931](https://github.com/stlink-org/stlink/pull/931)) +* Calculate checksums for flash operations ([#862](https://github.com/stlink-org/stlink/pull/862), [#924](https://github.com/stlink-org/stlink/pull/924)) +* Adjust the JTAG/SWD frequency via cmdline option ([#893](https://github.com/stlink-org/stlink/pull/893), [#953](https://github.com/stlink-org/stlink/pull/953)) +* Added usb PID and udev rules for STlink v2.1 found on Nucleo-L432KC and Nucleo-L552ze boards ([#900](https://github.com/stlink-org/stlink/pull/900)) +* STM32G0/G4 improvements ([#910](https://github.com/stlink-org/stlink/pull/910)) - Enable mass erase with a flash programming check - Handle G4 Cat3 devices with configurable dual bank flash by using a helper Updates & changes: -- [doc] Update compiling instructions ([#113](https://github.com/stlink-org/stlink/pull/113), commit [#10ae529](https://github.com/stlink-org/stlink/commit/10ae5294cd03aacfc07312010f026d3cb12ea56c)) -- Define libusb version compatibility for supported operating systems via LIBUSB_API_VERSION ([#211](https://github.com/stlink-org/stlink/pull/211), [#782](https://github.com/stlink-org/stlink/pull/782), [#895](https://github.com/stlink-org/stlink/pull/895)) -- Improved argument parsing for CLI tools ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) -- [doc] Updated tutorial: macOS ST-Link-v1 detection ([#574](https://github.com/stlink-org/stlink/pull/574), [#587](https://github.com/stlink-org/stlink/pull/587)) -- Enhanced error log with file path for map_file() ([#650](https://github.com/stlink-org/stlink/pull/650), [#879](https://github.com/stlink-org/stlink/pull/879), [#921](https://github.com/stlink-org/stlink/pull/921)) -- Enhanced output for error msg "addr not a multiple of pagesize, not supported" ([#663](https://github.com/stlink-org/stlink/pull/663), [#945](https://github.com/stlink-org/stlink/pull/945)) -- [refactoring] Package distribution: Provide Windows binaries via Debian-based cross-build ([#738](https://github.com/stlink-org/stlink/pull/738), [#795](https://github.com/stlink-org/stlink/pull/795), [#798](https://github.com/stlink-org/stlink/pull/798), [#955](https://github.com/stlink-org/stlink/pull/955)) - - Update, corrections & cleanup for build settings (see #955 for details) +* [doc] Updated compiling instructions ([#113](https://github.com/stlink-org/stlink/pull/113), commit [#10ae529](https://github.com/stlink-org/stlink/commit/10ae5294cd03aacfc07312010f026d3cb12ea56c)) +* Defined libusb version compatibility for supported systems via LIBUSB_API_VERSION ([#211](https://github.com/stlink-org/stlink/pull/211), [#782](https://github.com/stlink-org/stlink/pull/782), [#895](https://github.com/stlink-org/stlink/pull/895)) +* Improved argument parsing for CLI tools ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) +* [doc] Updated tutorial: macOS ST-Link-v1 detection ([#574](https://github.com/stlink-org/stlink/pull/574), [#587](https://github.com/stlink-org/stlink/pull/587)) +* Enhanced error log with file path for map_file() ([#650](https://github.com/stlink-org/stlink/pull/650), [#879](https://github.com/stlink-org/stlink/pull/879), [#921](https://github.com/stlink-org/stlink/pull/921)) +* Enhanced output for error msg "addr not a multiple of pagesize, not supported" ([#663](https://github.com/stlink-org/stlink/pull/663), [#945](https://github.com/stlink-org/stlink/pull/945)) +* Package distribution: Provide Windows binaries via Debian-based cross-build ([#738](https://github.com/stlink-org/stlink/pull/738), [#795](https://github.com/stlink-org/stlink/pull/795), [#798](https://github.com/stlink-org/stlink/pull/798), [#870](https://github.com/stlink-org/stlink/pull/870), [#955](https://github.com/stlink-org/stlink/pull/955)) + - [refactoring] Update, corrections & cleanup for build settings (see #955 for details) - New cpack package-config for DEB and RPM build - Update for travis build configuration: builds for clang -m32, clang-9, MinGW-cross on linux - Updated steps for release preparation - Project contributors now listed in separate file - Test files & gui now use shared stlink-library -- [doc] Verify correct udev configuration for device access ([#764](https://github.com/stlink-org/stlink/pull/764)) -- Added more error info to WLOGs during probe ([#883](https://github.com/stlink-org/stlink/pull/883)) -- [doc] Add missing documentation for stlink-gui ([#884](https://github.com/stlink-org/stlink/pull/884)) -- Added check for libssp during compilation ([#885](https://github.com/stlink-org/stlink/pull/885)) -- Silence unnecessary messages ([#886](https://github.com/stlink-org/stlink/pull/886)) -- [doc] Define libusb & cmake version compatibility ([#896](https://github.com/stlink-org/stlink/pull/896), [#897](https://github.com/stlink-org/stlink/pull/897), [#899](https://github.com/stlink-org/stlink/pull/899), commit [#27aa888](https://github.com/stlink-org/stlink/commit/27aa88821197d3ffe82baff4e971c3488ec39899)) -- Update for STM32G471/473/474/483/484 devices ([#901](https://github.com/stlink-org/stlink/pull/901)) -- [doc] st-flash --flash=n[k][m] command line option to override device model ([#902](https://github.com/stlink-org/stlink/pull/902)) -- [refactoring] BSD-License-compliant rewrite of flashloader source files ([#915](https://github.com/stlink-org/stlink/pull/915), [#932](https://github.com/stlink-org/stlink/pull/932)) -- [refactoring] Overall option code rework ([#927](https://github.com/stlink-org/stlink/pull/927)) -- [refactoring] Build settings / GUI-Build on UNIX-based systems if GTK3 is detected ([#929](https://github.com/stlink-org/stlink/pull/929)) -- [refactoring] Reconfiguration of package build process ([#931](https://github.com/stlink-org/stlink/pull/931), [#936](https://github.com/stlink-org/stlink/pull/936), [#940](https://github.com/stlink-org/stlink/pull/940), commit [#9b19f92](https://github.com/stlink-org/stlink/commit/9b19f9225460472af9d98959b7217d0a840ee972)) -- [refactoring] st-util: Removed now useless v1/v2 STLink version stuff ([#934](https://github.com/stlink-org/stlink/pull/934)) -- [refactoring] Cleanup for option bytes and flash settings ([#941](https://github.com/stlink-org/stlink/pull/941)) -- Added compilation guideline for MSVC toolchain ([#942](https://github.com/stlink-org/stlink/pull/942)) -- [refactoring] Cleanup of cmake build process ([#944](https://github.com/stlink-org/stlink/pull/944), [#946](https://github.com/stlink-org/stlink/pull/946), [#947](https://github.com/stlink-org/stlink/pull/947)) -- Set up a libusb log level accordingly to verbosity (commit [#49f887d](https://github.com/stlink-org/stlink/commit/49f887d5247fdd28f163b6317790c4f087e652cc)) -- [doc] Defined version compatibility and installation instructions for macOS (commit [#23c071e](https://github.com/stlink-org/stlink/commit/23c071edea45f6e8852fef52d884a680973d6d8f)) -- Deprecated old appveyor-mingw script (commit [#9748442](https://github.com/stlink-org/stlink/commit/97484422008df0f75c978627054776f35842a075)) -- libusb package extraction no longer requires 7zip as an external unarchiver (commit [#5db2dc4](https://github.com/stlink-org/stlink/commit/5db2dc4c0410ace65308cddcc03d1c0cfa4855cf)) - +* [doc] Verify correct udev configuration for device access ([#764](https://github.com/stlink-org/stlink/pull/764)) +* Added more error info to WLOGs during probe ([#883](https://github.com/stlink-org/stlink/pull/883)) +* [doc] Added missing documentation for stlink-gui ([#884](https://github.com/stlink-org/stlink/pull/884)) +* Added check for libssp during compilation ([#885](https://github.com/stlink-org/stlink/pull/885)) +* Silenced unnecessary messages ([#886](https://github.com/stlink-org/stlink/pull/886)) +* [doc] Defined libusb & cmake version compatibility ([#896](https://github.com/stlink-org/stlink/pull/896), [#897](https://github.com/stlink-org/stlink/pull/897), [#899](https://github.com/stlink-org/stlink/pull/899), commit [#27aa888](https://github.com/stlink-org/stlink/commit/27aa88821197d3ffe82baff4e971c3488ec39899)) +* Update for STM32G471/473/474/483/484 devices ([#901](https://github.com/stlink-org/stlink/pull/901)) +* [doc] st-flash --flash=n[k][m] command line option to override device model ([#902](https://github.com/stlink-org/stlink/pull/902)) +* [refactoring] Improved cmake build process ([#912](https://github.com/stlink-org/stlink/pull/912)) + - Set up a libusb log level accordingly to verbosity ([#894](https://github.com/stlink-org/stlink/pull/894) + - [compatibility] Updated libusb to v1.0.23 ([#895](https://github.com/stlink-org/stlink/pull/895) + - Updated compiling doc & version support ([#896](https://github.com/stlink-org/stlink/pull/896), [#897](https://github.com/stlink-org/stlink/pull/897), [#899](https://github.com/stlink-org/stlink/pull/899)) + - Version requirements & pkg-maintainer + - Fixed install paths in build script + - Updated C-flag -std=gnu99 to gnu11) + - Added cmake uninstall target ([#619](https://github.com/stlink-org/stlink/pull/619), [#907](https://github.com/stlink-org/stlink/pull/907)) + - Integrated module GNUInstallDirs.cmake ([#557](https://github.com/stlink-org/stlink/pull/557)) + - [doc] Defined version compatibility and installation instructions for macOS + - [refactoring] libusb detection + - Deprecated old appveyor-mingw script +* [refactoring] BSD-License-compliant rewrite of flashloader source files ([#915](https://github.com/stlink-org/stlink/pull/915), [#932](https://github.com/stlink-org/stlink/pull/932)) +* [refactoring] Overall option code rework ([#927](https://github.com/stlink-org/stlink/pull/927)) +* [refactoring] Build settings / GUI-Build on UNIX-based systems if GTK3 is detected ([#929](https://github.com/stlink-org/stlink/pull/929)) +* [refactoring] Reconfiguration of package build process ([#931](https://github.com/stlink-org/stlink/pull/931), [#936](https://github.com/stlink-org/stlink/pull/936), [#940](https://github.com/stlink-org/stlink/pull/940), commit [#9b19f92](https://github.com/stlink-org/stlink/commit/9b19f9225460472af9d98959b7217d0a840ee972)) +* [refactoring] st-util: Removed now useless v1/v2 STLink version stuff ([#934](https://github.com/stlink-org/stlink/pull/934)) +* [refactoring] Cleanup for option bytes and flash settings ([#941](https://github.com/stlink-org/stlink/pull/941)) +* Added compilation guideline for MSVC toolchain ([#942](https://github.com/stlink-org/stlink/pull/942)) +* [refactoring] Cleanup of cmake build process ([#944](https://github.com/stlink-org/stlink/pull/944), [#946](https://github.com/stlink-org/stlink/pull/946), [#947](https://github.com/stlink-org/stlink/pull/947)) + - libusb package extraction no longer requires 7zip as an external unarchiver Fixes: -- Fixed wait-loop for flash_loader_run() ([#290](https://github.com/stlink-org/stlink/pull/290)) -- Better argument parsing for CLI tools: stlink_open_usb can address v1, v2, v3 ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) -- Clear the PG bit before setting the PER bit ([#579](https://github.com/stlink-org/stlink/pull/579), [#876](https://github.com/stlink-org/stlink/pull/876)) -- Fixed compilation issues with int length on 32-bit platforms ([#629](https://github.com/stlink-org/stlink/pull/629), [#908](https://github.com/stlink-org/stlink/pull/908)) -- Fixed st-info --probe mechanism ([#679](https://github.com/stlink-org/stlink/pull/679), [#918](https://github.com/stlink-org/stlink/pull/918)) -- [regression] Fixed sign-compare (size != rep_len) in usb.c ([#772](https://github.com/stlink-org/stlink/pull/772), [#869](https://github.com/stlink-org/stlink/pull/869), [#872](https://github.com/stlink-org/stlink/pull/872), [#891](https://github.com/stlink-org/stlink/pull/891)) -- Fixed dead loop after an unexpected unplug ([#780](https://github.com/stlink-org/stlink/pull/780), [#812](https://github.com/stlink-org/stlink/pull/812), [#913](https://github.com/stlink-org/stlink/pull/913)) -- Avoid re-define of O_BINARY on Windows ([#788](https://github.com/stlink-org/stlink/pull/788)) -- Fixed st-flash manpage read example ([#858](https://github.com/stlink-org/stlink/pull/858)) -- Fixed stlink support with no mass storage ([#861](https://github.com/stlink-org/stlink/pull/861)) -- Make Version.cmake more error-resistant ([#872](https://github.com/stlink-org/stlink/pull/872)) -- Error return in failed probe ([#887](https://github.com/stlink-org/stlink/pull/887), [#890](https://github.com/stlink-org/stlink/pull/890)) -- Fixed broken build on 32-bit systems ([#919](https://github.com/stlink-org/stlink/pull/919), [#920](https://github.com/stlink-org/stlink/pull/920)) -- st-flash: Minor usage fix and make cmdline parsing more user friendly ([#925](https://github.com/stlink-org/stlink/pull/925)) -- [regression] Restored functionality of make test builds ([#926](https://github.com/stlink-org/stlink/pull/926), [#929](https://github.com/stlink-org/stlink/pull/929)) -- Fixed compilation error due to uninitialized cpuid ([#937](https://github.com/stlink-org/stlink/pull/937), [#938](https://github.com/stlink-org/stlink/pull/938)) -- Fixes for STM32F0 flashloader ([#958](https://github.com/stlink-org/stlink/pull/958), [#959](https://github.com/stlink-org/stlink/pull/959) -- Set static link for libssp (stack-smashing protection) ([#960](https://github.com/stlink-org/stlink/pull/960), [#961](https://github.com/stlink-org/stlink/pull/961)) -- Fixed formatting for options display in st-flash & st-info (commits [#c783d0e](https://github.com/stlink-org/stlink/commit/c783d0e777ccc83a7a8be26a4f4d3414e0478560) and [#562cd24](https://github.com/stlink-org/stlink/commit/562cd2496e696dbd22950925866aac662d81ee5f)) +* Fixed wait-loop for flash_loader_run() ([#290](https://github.com/stlink-org/stlink/pull/290)) +* Better argument parsing for CLI tools: stlink_open_usb can address v1, v2, v3 ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) +* Clear the PG bit before setting the PER bit ([#579](https://github.com/stlink-org/stlink/pull/579), [#876](https://github.com/stlink-org/stlink/pull/876)) +* Fixed compilation issues with int length on 32-bit platforms ([#629](https://github.com/stlink-org/stlink/pull/629), [#908](https://github.com/stlink-org/stlink/pull/908)) +* Fixed st-info --probe mechanism ([#679](https://github.com/stlink-org/stlink/pull/679), [#918](https://github.com/stlink-org/stlink/pull/918)) +* [regression] Fixed sign-compare (size != rep_len) in usb.c ([#772](https://github.com/stlink-org/stlink/pull/772), [#869](https://github.com/stlink-org/stlink/pull/869), [#872](https://github.com/stlink-org/stlink/pull/872), [#891](https://github.com/stlink-org/stlink/pull/891)) +* Fixed dead loop after an unexpected unplug ([#780](https://github.com/stlink-org/stlink/pull/780), [#812](https://github.com/stlink-org/stlink/pull/812), [#913](https://github.com/stlink-org/stlink/pull/913)) +* Avoid re-define of O_BINARY on Windows ([#788](https://github.com/stlink-org/stlink/pull/788)) +* Fixed st-flash manpage read example ([#858](https://github.com/stlink-org/stlink/pull/858)) +* Fixed stlink support with no mass storage ([#861](https://github.com/stlink-org/stlink/pull/861)) +* Make Version.cmake more error-resistant ([#872](https://github.com/stlink-org/stlink/pull/872)) +* Error return in failed probe ([#887](https://github.com/stlink-org/stlink/pull/887), [#890](https://github.com/stlink-org/stlink/pull/890)) +* Fixed broken build on 32-bit systems ([#919](https://github.com/stlink-org/stlink/pull/919), [#920](https://github.com/stlink-org/stlink/pull/920)) +* st-flash: Minor usage fix and make cmdline parsing more user friendly ([#925](https://github.com/stlink-org/stlink/pull/925)) +* [regression] Restored functionality of make test builds ([#926](https://github.com/stlink-org/stlink/pull/926), [#929](https://github.com/stlink-org/stlink/pull/929)) +* Fixed compilation error due to uninitialized cpuid ([#937](https://github.com/stlink-org/stlink/pull/937), [#938](https://github.com/stlink-org/stlink/pull/938)) +* Fixes for STM32F0 flashloader ([#958](https://github.com/stlink-org/stlink/pull/958), [#959](https://github.com/stlink-org/stlink/pull/959)) +* Set static link for libssp (stack-smashing protection) ([#960](https://github.com/stlink-org/stlink/pull/960), [#961](https://github.com/stlink-org/stlink/pull/961)) +* Fixed udev rules installing to wrong directory ([#966](https://github.com/stlink-org/stlink/pull/966)) +* Fixed formatting for options display in st-flash & st-info (commits [#c783d0e](https://github.com/stlink-org/stlink/commit/c783d0e777ccc83a7a8be26a4f4d3414e0478560) and [#562cd24](https://github.com/stlink-org/stlink/commit/562cd2496e696dbd22950925866aac662d81ee5f)) v1.6.0 @@ -333,6 +342,7 @@ Updates and fixes: * Fixed STM32F2xx memory map (Nicolas Schodet) * Memory map for STM32F42xxx and STM32F43xxx devices (Craig Lilley) * Stm32l0x flash loader (Robin Kreis) +* Fixed segfault when programmer is already busy and NULL pointers are in the list ([#256](https://github.com/stlink-org/stlink/pull/256), [#394](https://github.com/stlink-org/stlink/pull/394)) * Send F4 memory-map and features for STM32F429 ([#188](https://github.com/stlink-org/stlink/pull/188), [#196](https://github.com/stlink-org/stlink/pull/196), [#250](https://github.com/stlink-org/stlink/pull/250), [#251](https://github.com/stlink-org/stlink/pull/251)) (Release v1.1.0) * Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/stlink-org/stlink/pull/218), [#288](https://github.com/stlink-org/stlink/pull/288)) (Release v1.1.0) * Corrected flash size register address for STM32F2 devices ([#278](https://github.com/stlink-org/stlink/pull/278)) (Release v1.0.0) diff --git a/doc/compiling.md b/doc/compiling.md index 2da79f071..428d9cc3c 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -153,11 +153,11 @@ $ debuild -uc -us ### Set permissions with udev By default most distributions don't allow access to USB devices. -Therefore make sure you install udev files which are necessary to run the tools without root permissions. +Therefore make sure you install udev files which are necessary to run the tools without root permissions.
      udev rules create devices nodes and set the group of these to `stlink`. -The rules are located in the subdirectory `etc/udev/rules.d` within the sourcefolder. -Copy them to the directory path `/etc/udev/rules.d` and subsequently reload the udev rules: +The rules are located in the subdirectory `config/udev/rules.d` within the sourcefolder and are automatically installed along with `sudo make install` on linux. +Afterwards it may be necessary to reload the udev rules: ```sh $ cp etc/udev/rules.d /etc/udev/rules.d @@ -165,18 +165,14 @@ $ udevadm control --reload-rules $ udevadm trigger ``` -Udev will now create device node files `/dev/stlinkv2_XX`, `/dev/stlinkv1_XX`. +Udev will now create device node files `/dev/stlinkv2_XX`, `/dev/stlinkv1_XX`.
      You need to ensure that the group `stlink` exists and the user who is trying to access these devices is a member of this group. -### Note on the use of STLink-v1 programmers: +### Note on the use of STLink-v1 programmers (legacy): -At the time of writing the STLink-v1 has mostly been replaced with the newer generation STLink-v2 programmers and thus is only rarely used. -As there are some caveats as well, we recommend to use the STLink-v2 programmers if possible. - -To be more precise, the STLINKv1's SCSI emulation is somehow broken, so the best advice possibly is to tell your operating system to completely ignore it. - -Choose on of the following options _before_ connecting the device to your computer: +As the STLINKv1's SCSI emulation is somehow broken, the best advice possibly is to tell your operating system to completely ignore it.
      +Choose one of the following options _before_ connecting the device to your computer: * `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` * _OR_ @@ -208,8 +204,8 @@ To do this with only one simple command, type: - with gcc: `sudo brew install git gcc cmake libusb gtk+3` or - with clang: `sudo brew install git llvm cmake libusb gtk+3` or * for MacPorts: - - with gcc: `sudo port install git llvm-9.0 cmake libusb gtk3` or - - with clang: `sudo port install git gcc9 cmake libusb gtk3` + - with gcc: `sudo port install git gcc10 cmake libusb gtk3` or + - with clang: `sudo port install git llvm-10 cmake libusb gtk3` ### Installation From a5dc016b42ab1faf872c8fce49521f1bacf28256 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 28 May 2020 11:42:26 +0200 Subject: [PATCH 0948/1435] Changed kext-path to /Library/Extensions --- CMakeLists.txt | 2 +- stlinkv1_macos_driver/README.md | 7 ++++--- stlinkv1_macos_driver/install.sh | 8 ++++---- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 6b17fdc57..7e54b3fa2 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -143,7 +143,7 @@ endif () set(STLINK_LIBRARY_PATH ${CMAKE_INSTALL_LIBDIR} CACHE PATH "Main library install directory") # Set the environment variable LD_LIBRARY_PATH to point to /usr/local/lib (per default). -execute_process (COMMAND bash -c "export LD_LIBRARY_PATH="${CMAKE_INSTALL_LIBDIR}"") +execute_process (COMMAND bash -c "export LD_LIBRARY_PATH="${CMAKE_INSTALL_LIBDIR}" ") ### diff --git a/stlinkv1_macos_driver/README.md b/stlinkv1_macos_driver/README.md index 7221732c0..e0f9256e8 100644 --- a/stlinkv1_macos_driver/README.md +++ b/stlinkv1_macos_driver/README.md @@ -21,11 +21,12 @@ In order to deactivate SIP, boot into the recovery mode and run ```csrutil disab This should result in the following output: ``` -Requesting load of /System/Library/Extensions/stlink_shield.kext. -/System/Library/Extensions/stlink_shield.kext loaded successfully (or already loaded). +Requesting load of /Library/Extensions/stlink_shield.kext. +/Library/Extensions/stlink_shield.kext loaded successfully (or already loaded). ``` +4) Reboot the system. -4) Verify correct detection of the STLINK/v1 device with the following input: `st-util -1` +5) Verify correct detection of the STLINK/v1 device with the following input: `st-util -1` You should then see a similar output like in this example: ``` diff --git a/stlinkv1_macos_driver/install.sh b/stlinkv1_macos_driver/install.sh index 9e5f8d813..19e9f141d 100644 --- a/stlinkv1_macos_driver/install.sh +++ b/stlinkv1_macos_driver/install.sh @@ -10,13 +10,13 @@ case $ISMACOS in ;; 10.15*) KEXT="stlink_shield_10_15.kext" - ;; + ;; *) echo "OS X version not supported." exit 1 ;; esac chown -R root:wheel $KEXT/ -cp -R $KEXT /System/Library/Extensions/stlink_shield.kext -kextload -v /System/Library/Extensions/stlink_shield.kext -touch /System/Library/Extensions +cp -R $KEXT /Library/Extensions/stlink_shield.kext +kextload -v /Library/Extensions/stlink_shield.kext +touch /Library/Extensions From 7829600c9af2cd354f61fc9ed2165b58733d54de Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 28 May 2020 21:57:56 +0200 Subject: [PATCH 0949/1435] Preparation for Release v1.6.1 --- .version | 2 +- CHANGELOG.md | 3 ++- README.md | 4 +++- contributors.txt | 1 + 4 files changed, 7 insertions(+), 3 deletions(-) diff --git a/.version b/.version index ce6a70b9d..9c6d6293b 100644 --- a/.version +++ b/.version @@ -1 +1 @@ -1.6.0 \ No newline at end of file +1.6.1 diff --git a/CHANGELOG.md b/CHANGELOG.md index 94c47e8fb..3195bae3c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -4,7 +4,7 @@ stlink ChangeLog v1.6.1 ====== -Release date: 2020-06-xx +Release date: 2020-06-01 This release drops support for some older operating systems. Check project README for details. @@ -37,6 +37,7 @@ Updates & changes: * [doc] Updated tutorial: macOS ST-Link-v1 detection ([#574](https://github.com/stlink-org/stlink/pull/574), [#587](https://github.com/stlink-org/stlink/pull/587)) * Enhanced error log with file path for map_file() ([#650](https://github.com/stlink-org/stlink/pull/650), [#879](https://github.com/stlink-org/stlink/pull/879), [#921](https://github.com/stlink-org/stlink/pull/921)) * Enhanced output for error msg "addr not a multiple of pagesize, not supported" ([#663](https://github.com/stlink-org/stlink/pull/663), [#945](https://github.com/stlink-org/stlink/pull/945)) +* Updated STLink-v1 driver for macOS ([#735](https://github.com/stlink-org/stlink/pull/735), [#964](https://github.com/stlink-org/stlink/pull/964)) * Package distribution: Provide Windows binaries via Debian-based cross-build ([#738](https://github.com/stlink-org/stlink/pull/738), [#795](https://github.com/stlink-org/stlink/pull/795), [#798](https://github.com/stlink-org/stlink/pull/798), [#870](https://github.com/stlink-org/stlink/pull/870), [#955](https://github.com/stlink-org/stlink/pull/955)) - [refactoring] Update, corrections & cleanup for build settings (see #955 for details) - New cpack package-config for DEB and RPM build diff --git a/README.md b/README.md index 7dc634c9c..21ab9f48b 100644 --- a/README.md +++ b/README.md @@ -4,7 +4,7 @@ Open source version of the STMicroelectronics STlink Tools [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) [![GitHub release](https://img.shields.io/github/release/stlink-org/stlink.svg)](https://github.com/stlink-org/stlink/releases/latest) [![Downloads](https://img.shields.io/github/downloads/stlink-org/stlink/total)](https://github.com/stlink-org/stlink/releases/latest) -![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.6.0/develop) +![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.6.1/develop) ![GitHub activity](https://img.shields.io/github/commit-activity/m/stlink-org/stlink) ![GitHub contributors](https://img.shields.io/github/contributors/stlink-org/stlink) [![Linux Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=linux&label=linux)](https://travis-ci.org/stlink-org/stlink) @@ -53,6 +53,8 @@ Currently known working combinations of programmers and targets are listed in [d Supported operating systems are listed in [version_support.md](doc/version_support.md). +The `stlink` toolset continues to maintain backwards compatibility with the **STLINK/v1** programmer.
      +Please note that on macOS this support is limited to versions 10.13 - 10.15. ## Tutorial & HOWTO diff --git a/contributors.txt b/contributors.txt index 8811da855..fec7510c3 100644 --- a/contributors.txt +++ b/contributors.txt @@ -13,6 +13,7 @@ Björn Hauffe Ihor Bobalo Breton M. Saunders Bruno Dal Bo +Brian Team [dot4qu] Burns Fisher Cheng Guokai (Xim) [chenguokai] Chris Dew From 2016590502558caa98c21abad2ce83c5f4804a98 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?S=C3=B6ren=20Tempel?= Date: Mon, 1 Jun 2020 00:20:26 +0200 Subject: [PATCH 0950/1435] doc/man: Fix installation directory On Unix-like operating systems man pages are commonly installed to `/usr/share/man` not `/usr/share/stlink/man`. --- doc/man/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 23da9e150..9b3c50764 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -30,7 +30,7 @@ foreach (manpage ${MANPAGES}) endif () if (f AND NOT WIN32) - install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/man/man1) + install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/man/man1) unset(f) endif () endforeach () From e95b5ffcfe38c917a1f421c2257e58a3d9b2e8cc Mon Sep 17 00:00:00 2001 From: Vasiliy Glazov Date: Mon, 1 Jun 2020 08:44:11 +0300 Subject: [PATCH 0951/1435] Fix installation path for desktop-file and icons. This change fixes installation path for desktop-file and icons. They should be installed directly to ``` /usr/share/applications/ /usr/share/icons/hicolor/scalable/apps/ ``` --- src/stlink-gui/CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 8c36e5a1f..cc68509fe 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -13,11 +13,11 @@ if (NOT WIN32) # Install desktop application entry install(FILES stlink-gui.desktop - DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/applications) + DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/applications) # Install icons install(FILES icons/stlink-gui.svg - DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/icons/hicolor/scalable/apps) + DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/icons/hicolor/scalable/apps) set(GUI_SOURCES gui.c gui.h) From c774dca67676dbf06784ca088a6ff369ef4fe9ce Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Tue, 2 Jun 2020 17:46:05 +0300 Subject: [PATCH 0952/1435] link ssp as static only for WIN32 --- CMakeLists.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 86282775e..ae7ddf971 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -71,7 +71,11 @@ include(CheckLibraryExists) CHECK_LIBRARY_EXISTS(ssp __stack_chk_fail "" _stack_chk_fail_exists) if (_stack_chk_fail_exists) - set(SSP_LIB -static ssp) + if(WIN32) + set(SSP_LIB -static ssp) + else() + set(SSP_LIB -static ssp) + endif() else () set(SSP_LIB "") endif () From b1af21d396e5888a4df802d9364f172cd9260846 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Tue, 2 Jun 2020 17:55:34 +0300 Subject: [PATCH 0953/1435] link ssp as static only for WIN32 --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index ae7ddf971..51d09412d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -74,7 +74,7 @@ if (_stack_chk_fail_exists) if(WIN32) set(SSP_LIB -static ssp) else() - set(SSP_LIB -static ssp) + set(SSP_LIB ssp) endif() else () set(SSP_LIB "") From ade735dd671ea30ebbef36aaa17b51c6294425cf Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 3 Jun 2020 20:02:09 +0200 Subject: [PATCH 0954/1435] Moved unused pkg-config settings to /doc/dev (Closes #971) --- .gitignore | 2 +- CMakeLists.txt | 7 -- doc/compiling.md | 2 - doc/{ => dev}/app-example/CMakeLists.txt | 0 doc/{ => dev}/app-example/README.md | 0 doc/{ => dev}/app-example/main.c | 0 doc/{ => dev}/developer.txt | 115 ++++++++++-------- .../dev/pkg-config}/CMakeLists.txt | 0 .../dev/pkg-config}/pkgconfig.pc.cmake | 0 9 files changed, 67 insertions(+), 59 deletions(-) rename doc/{ => dev}/app-example/CMakeLists.txt (100%) rename doc/{ => dev}/app-example/README.md (100%) rename doc/{ => dev}/app-example/main.c (100%) rename doc/{ => dev}/developer.txt (93%) rename {cmake/pkgconfig => doc/dev/pkg-config}/CMakeLists.txt (100%) rename {cmake/pkgconfig => doc/dev/pkg-config}/pkgconfig.pc.cmake (100%) diff --git a/.gitignore b/.gitignore index 09b9b33de..229242a53 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,5 @@ build build-mingw +.project obj-* *.user* -.project diff --git a/CMakeLists.txt b/CMakeLists.txt index 51d09412d..0538f3b14 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -47,13 +47,6 @@ endif () find_package(libusb REQUIRED) -## Package configuration (pkg-config) on unix-based systems -if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) - #add_subdirectory(cmake/pkgconfig) - find_package(PkgConfig) - pkg_check_modules(GTK3 gtk+-3.0) -endif () - ## Check for system-specific additional header files and libraries include(CheckIncludeFile) diff --git a/doc/compiling.md b/doc/compiling.md index 428d9cc3c..c278c9ca8 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -88,7 +88,6 @@ Install the following packages from your package repository: * `build-essential` (on Debian based distros (Debian, Ubuntu)) * `cmake` (3.4.2 or later, use the latest version available from the repository) * `rpm` (on Debian based distros (Debian, Ubuntu), needed for package build with `make package`) -* `pkg-config` * `libusb-1.0` * `libusb-1.0-0-dev` (development headers for building) * `libgtk-3-dev` (_optional_, needed for `stlink-gui`) @@ -194,7 +193,6 @@ Then install the following dependencies from the package repository: * `git` * `gcc` or `llvm` (for clang) (C-compiler) * `cmake` -* `pkg-config` * `libusb` * `gtk+3` or `gtk3` (_optional_, needed for `stlink-gui`) diff --git a/doc/app-example/CMakeLists.txt b/doc/dev/app-example/CMakeLists.txt similarity index 100% rename from doc/app-example/CMakeLists.txt rename to doc/dev/app-example/CMakeLists.txt diff --git a/doc/app-example/README.md b/doc/dev/app-example/README.md similarity index 100% rename from doc/app-example/README.md rename to doc/dev/app-example/README.md diff --git a/doc/app-example/main.c b/doc/dev/app-example/main.c similarity index 100% rename from doc/app-example/main.c rename to doc/dev/app-example/main.c diff --git a/doc/developer.txt b/doc/dev/developer.txt similarity index 93% rename from doc/developer.txt rename to doc/dev/developer.txt index 2d05b9312..4032eca3e 100644 --- a/doc/developer.txt +++ b/doc/dev/developer.txt @@ -1,4 +1,21 @@ - +=== Compilation with pkg-config === + +In order to use pkg-config for development purposes, add the following lines to the toplevel CMakeLists.txt file: + +### +# Additional build tasks +### + +## Package configuration (pkg-config) on unix-based systems +if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) + add_subdirectory(doc/dev/pkg-config) # Option A: external tool pkg-config + find_package(PkgConfig) # Option B: internal cmake module for pkg-config integration + pkg_check_modules(GTK3 gtk+-3.0) +endif () + +ToDo: Check for compatibility issues between options A and B. + + === Target Identification === The following information is available about the target: @@ -42,7 +59,7 @@ Include stlink/backend.h int (*current_mode) (stlink_t * stl); int (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); - int (*set_swdclk) (stlink_t * stl, uint16_t divisor); + int (*set_swdclk) (stlink_t * stl, uint16_t divisor); } stlink_backend_t; Descriptions below describe the actions of the usb.h backend: @@ -55,7 +72,7 @@ int (*exit_debug_mode) (stlink_t * sl); int (*enter_swd_mode) (stlink_t * sl); _stlink_usb_enter_swd_mode: Send STLINK_DEBUG_ENTER+STLINK_DEBUG_ENTER_SWD returns -1 or 0 - + int (*enter_jtag_mode) (stlink_t * stl); int (*exit_dfu_mode) (stlink_t * stl); @@ -65,19 +82,19 @@ int (*exit_dfu_mode) (stlink_t * stl); int (*core_id) (stlink_t * stl); _stlink_usb_core_id: Assign the result from STLINK_DEBUG_READCOREID to stl->core_id returns -1 or 0 - + int (*reset) (stlink_t * stl); _stlink_usb_reset: Send STLINK_DEBUG_RESETSYS and reset via AIRCR - AIRCR is part of the CMSIS System Control Block (SCB), which is located in + AIRCR is part of the CMSIS System Control Block (SCB), which is located in the System Control Space at 0xE000ED0C returns -1 or 0 ? - + int (*jtag_reset) (stlink_t * stl, int value); _stlink_usb_jtag_reset: Send STLINK_JTAG_DRIVE_NRST. "value" is sent as argument for STLINK_JTAG_DRIVE_NRST and probably contains the status of the NRST line (0: low, 1: high). Also the value 2 is used in the software. returns -1 or 0 - + int (*run) (stlink_t * stl); _stlink_usb_run: Send STLINK_DEBUG_RUNCORE returns -1 or 0 @@ -85,12 +102,12 @@ int (*run) (stlink_t * stl); int (*status) (stlink_t * stl); _stlink_usb_status: Assign the result from STLINK_DEBUG_GETSTATUS to stl->q_len returns -1 or 0 - + int (*version) (stlink_t *sl); _stlink_usb_version: Read version with STLINK_GET_VERSION. Result is stored in sl->q_buf (6 bytes????) returns -1 or 0 - + int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); _stlink_usb_read_debug32: Send STLINK_JTAG_READDEBUG_32BIT to read 32 bits from "addr". The result data is stored at "*data". @@ -99,10 +116,10 @@ int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); _stlink_usb_read_mem32: Use STLINK_DEBUG_READMEM_32BIT to read "len" bytes from "addr" - Result is returned in sl->q_buf, sl->q_len returns the size of the data (should be + Result is returned in sl->q_buf, sl->q_len returns the size of the data (should be equal to "len"???). returns -1 or 0 - + int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); _stlink_usb_write_debug32: Use STLINK_JTAG_WRITEDEBUG_32BIT to store "data" at "addr" @@ -124,13 +141,13 @@ int (*read_all_regs) (stlink_t *sl, struct stlink_reg * regp); _stlink_usb_read_all_regs: Send STLINK_DEBUG_READALLREGS to read all register values and store them into *regp; returns -1 or 0 - + int (*read_reg) (stlink_t *sl, int r_idx, struct stlink_reg * regp); _stlink_usb_read_reg: Send STLINK_DEBUG_READREG to read specific register "r_idx". - The result is then stored in *regp in the correct register. + The result is then stored in *regp in the correct register. Example if "r_idx" is 18, then the result is stored in regp->process_sp returns -1 or 0 - + int (*read_all_unsupported_regs) (stlink_t *sl, struct stlink_reg *regp); _stlink_usb_read_all_unsupported_regs: Calls "_stlink_usb_read_unsupported_reg" (see below) to read all registers. @@ -142,7 +159,7 @@ int (*read_unsupported_reg) (stlink_t *sl, int r_idx, struct stlink_reg *regp); Also will fill regp->s (???) for some specific "r_idx" values. WARNING: Some r_idx values may lead to a out of array bound problem in C. returns -1 or 0 - + int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, struct stlink_reg *regp); _stlink_usb_write_unsupported_reg: Updates one of the following registers: @@ -154,14 +171,14 @@ int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, struct stli returns -1 or 0 int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); - _stlink_usb_write_reg: Use STLINK_DEBUG_WRITEREG to update register "idx" + _stlink_usb_write_reg: Use STLINK_DEBUG_WRITEREG to update register "idx" with value "reg". returns -1 or 0 - + int (*step) (stlink_t * stl); _stlink_usb_step: Send STLINK_DEBUG_STEPCORE returns -1 or 0 - + int (*current_mode) (stlink_t * stl); _stlink_usb_current_mode: Send STLINK_GET_CURRENT_MODE and return the current mode. @@ -174,15 +191,15 @@ int (*current_mode) (stlink_t * stl); int (*force_debug) (stlink_t *sl); _stlink_usb_force_debug: Sends STLINK_DEBUG_FORCEDEBUG. No other side effects returns -1 or 0 - + int32_t (*target_voltage) (stlink_t *sl); _stlink_usb_target_voltage: Send STLINK_GET_TARGET_VOLTAGE returns -1 or the target voltage. (??? dimension is not clear...) -int (*set_swdclk) (stlink_t * stl, uint16_t divisor); +int (*set_swdclk) (stlink_t * stl, uint16_t divisor); _stlink_usb_set_swdclk: Send STLINK_DEBUG_APIV2_SWD_SET_FREQ and "divisor" value returns -1 or 0 - + === Other Functions === @@ -193,17 +210,17 @@ Include: stlink.h Prototype: void stlink_close(stlink_t *sl); Include: inc/stlink.h Definition: src/common.c -Description: +Description: Calls the backend "close" procedure and frees 'sl' Backend: "close" Arguments: sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() Return: - - + Include: inc/stlink.h Prototype: int stlink_core_id(stlink_t *sl); Definition: src/common.c -Description: +Description: Calls the backend "core_id", calls stlink_print_data() on higher verbose levels. Assigns the core id returned by STLINK_DEBUGREADCOREID to sl->core_id Only some specific core ids are used: See include/stm32.h @@ -216,8 +233,8 @@ Return: -1 for error. 0 for success. Include: inc/stlink.h Prototype: int stlink_reset(stlink_t *sl); Definition: src/common.c -Description: - Just calls the backend "reset" procedure (reset via STLINK_DEBUG_RESETSYS +Description: + Just calls the backend "reset" procedure (reset via STLINK_DEBUG_RESETSYS and reset via AIRCR register at 0xE000ED0C) Backend: "reset" Arguments: @@ -227,29 +244,29 @@ Return: -1 for error. 0 for success. Include: inc/stlink.h Prototype: int stlink_jtag_reset(stlink_t *sl, int value); Definition: src/common.c -Description: - Just calls the backend "jtag_reset" procedure +Description: + Just calls the backend "jtag_reset" procedure Backend: "jtag_reset" Arguments: sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() value: 0: drive low, 1: drive high, 2: ???? Return: -1 for error. 0 for success. - - + + Include: inc/stlink.h Prototype: int stlink_run(stlink_t *sl); Definition: src/common.c -Description: +Description: Just calls the backend "run" procedure. Backend: "run" Arguments: sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() Return: -1 for error. 0 for success. - + Include: inc/stlink.h Prototype: int stlink_status(stlink_t *sl); Definition: src/common.c -Description: +Description: Calls the backend "status" procedure and the procedure "stlink_core_stat()" to store the status in "sl->core_stat". Possible value for "sl->core_stat" are: STLINK_CORE_RUNNING @@ -259,12 +276,12 @@ Backend: "status" Arguments: sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() Return: -1 for error. 0 for success. - + Include: inc/stlink.h Prototype: int stlink_version(stlink_t *sl); Definition: src/common.c -Description: +Description: Calls the backend "version" procedure, parses the result and puts the result into sl->version This version probably refers to the version of the adapter. Backend: "version" @@ -272,9 +289,9 @@ Arguments: sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() Return: -1 for error. 0 for success. - + int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); - int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); + int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); @@ -305,9 +322,9 @@ Return: -1 for error. 0 for success. Include: inc/stlink.h Prototype: int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); Definition: src/common.c -Description: +Description: Tries to read out the chip id via memory read from the device. - Note: sl->chip_id is NOT updated by this procedure. Instead this happens in stlink_load_device_params(): + Note: sl->chip_id is NOT updated by this procedure. Instead this happens in stlink_load_device_params(): Do not call this function, but instead call stlink_load_device_params() Backend: - Arguments: @@ -319,7 +336,7 @@ Return: -1 for error. 0 for success. Include: inc/stlink.h Prototype: int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); Definition: src/common.c -Description: +Description: Reads the CPU id from STLINK_REG_CM3_CPUID (0xE000ED00, first value of the SCB, system control block) and splits this into cpuid->implementer_id @@ -333,19 +350,19 @@ Arguments: cpuid: Pointer. Result is stored via this pointer. Return: -1 for error. 0 for success. - - + + int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); uint16_t read_uint16(const unsigned char *c, const int pt); void stlink_core_stat(stlink_t *sl); - + Include: inc/stlink.h Prototype: void stlink_print_data(stlink_t *sl); Definition: src/common.c -Description: +Description: If debug logging is enabled: Print the HEX content of the q_buf array. q_buf will contain the result of the last "backend" command. Backend: - @@ -362,21 +379,21 @@ Return: - int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); - - + + Include: inc/stlink.h Prototype: int stlink_load_device_params(stlink_t *sl); Definition: src/common.c -Description: +Description: This is one of the most important procedures. It will get all the device info and store the results in the "sl" structure. Many other procedures will depend on this information. - The identification is based on the stlink_chip_id() result and the flash_size register value + The identification is based on the stlink_chip_id() result and the flash_size register value Backend: - Arguments: sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() Return: -1 for error. 0 for success. - + int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte); int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte); diff --git a/cmake/pkgconfig/CMakeLists.txt b/doc/dev/pkg-config/CMakeLists.txt similarity index 100% rename from cmake/pkgconfig/CMakeLists.txt rename to doc/dev/pkg-config/CMakeLists.txt diff --git a/cmake/pkgconfig/pkgconfig.pc.cmake b/doc/dev/pkg-config/pkgconfig.pc.cmake similarity index 100% rename from cmake/pkgconfig/pkgconfig.pc.cmake rename to doc/dev/pkg-config/pkgconfig.pc.cmake From 8f42f5443852bfb062fdb858a157d88a800470a9 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 4 Jun 2020 12:50:02 +0200 Subject: [PATCH 0955/1435] Deleted duplicated issue template --- ...ort--only-valid-if-template-is-reused--.md | 38 ------------------- 1 file changed, 38 deletions(-) delete mode 100644 .github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md diff --git a/.github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md b/.github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md deleted file mode 100644 index 255596955..000000000 --- a/.github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md +++ /dev/null @@ -1,38 +0,0 @@ ---- -name: Bug Report (only valid if template is reused!) -about: 'Please read #906 before submitting a ticket.' -title: "[STM32 device name]: [Title]" -labels: '' -assignees: '' - ---- - -Thank you for giving feedback to the stlink project. - -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out each of the following items appropriate to your specific problem: - -- Programmer/board type: [enter here] (e.g Stlink /v1, /v2, /v2-clone, /v2-1) -- Programmer firmware version: [enter here] (e.g STSW-LINK007 2.27.15) -- Operating system and version: [enter here] (e.g Linux, Mac OS X, Windows) -- **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.1.0/git-c722056) -- Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) -- Target chip (and board if applicable): [enter here] (e.g STM32F402VG) - -Futher we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: - -Commandline-Output: - -``` -OUTPUT/ERROR of the commandline tool(s) -``` - -Expected/description: - -`short description of the expected value` - - -**NOTICE: This bug report may be closed without further notice, if not enough information is provided!** - -Thank you for your support. - -The stlink project maintainers From 05f79e1cdf72a3a6ebdeac229842e39577e6700b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 4 Jun 2020 21:33:34 +0200 Subject: [PATCH 0956/1435] [regression] Fixed GTK3 detection --- CMakeLists.txt | 2 +- doc/dev/developer.txt | 7 +------ src/stlink-gui/CMakeLists.txt | 7 ++++--- 3 files changed, 6 insertions(+), 10 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 0538f3b14..4055110ad 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -140,7 +140,7 @@ endif () set(STLINK_LIBRARY_PATH ${CMAKE_INSTALL_LIBDIR} CACHE PATH "Main library install directory") # Set the environment variable LD_LIBRARY_PATH to point to /usr/local/lib (per default). -execute_process (COMMAND bash -c "export LD_LIBRARY_PATH="${CMAKE_INSTALL_LIBDIR}" ") +execute_process (COMMAND bash -c "export LD_LIBRARY_PATH=${CMAKE_INSTALL_LIBDIR}") ### diff --git a/doc/dev/developer.txt b/doc/dev/developer.txt index 4032eca3e..32afd4352 100644 --- a/doc/dev/developer.txt +++ b/doc/dev/developer.txt @@ -8,14 +8,9 @@ In order to use pkg-config for development purposes, add the following lines to ## Package configuration (pkg-config) on unix-based systems if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) - add_subdirectory(doc/dev/pkg-config) # Option A: external tool pkg-config - find_package(PkgConfig) # Option B: internal cmake module for pkg-config integration - pkg_check_modules(GTK3 gtk+-3.0) + add_subdirectory(doc/dev/pkg-config) # external tool pkg-config endif () -ToDo: Check for compatibility issues between options A and B. - - === Target Identification === The following information is available about the target: diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index cc68509fe..89e5403d8 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -2,7 +2,10 @@ # Build GUI ### -if (NOT WIN32) +if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) + find_package(PkgConfig) + pkg_check_modules(GTK3 gtk+-3.0) + ## GUI-Building requires the presence of a GTK3 toolset if (NOT GTK3_FOUND) message(STATUS "GTK3 not found!") @@ -35,7 +38,5 @@ if (NOT WIN32) COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) - - endif () endif () From c7041cc2be2582caca522c18babeb40aadcc246f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 4 Jun 2020 21:53:17 +0200 Subject: [PATCH 0957/1435] Reorganised project source directories (Closes #976) --- CMakeLists.txt | 62 +++-- doc/dev/developer.txt | 4 +- inc/CMakeLists.txt | 9 + {include => inc}/stlink.h | 0 {include => inc}/stm32.h | 0 {include/stlink => inc}/version.h.in | 0 include/CMakeLists.txt | 9 - {include/stlink => src}/backend.h | 0 {include/stlink => src}/commands.h | 0 src/common.c | 6 +- src/{ => mmap}/mmap.c | 0 src/{ => mmap}/mmap.h | 0 {include/stlink => src}/reg.h | 0 src/{tools => st-flash}/flash.c | 2 +- .../stlink/tools => src/st-flash}/flash.h | 0 src/{tools => st-flash}/flash_opts.c | 2 +- src/{tools => st-info}/info.c | 0 src/st-util/semihosting.c | 59 ++--- src/stlink-gui/CMakeLists.txt | 7 +- src/{ => stlink-lib}/chipid.c | 2 +- {include/stlink => src/stlink-lib}/chipid.h | 0 src/{ => stlink-lib}/flash_loader.c | 243 +++++++++--------- .../stlink => src/stlink-lib}/flash_loader.h | 0 src/{ => stlink-lib}/logging.c | 0 src/{ => stlink-lib}/logging.h | 0 src/{ => stlink-lib}/md5.c | 0 src/{ => stlink-lib}/md5.h | 0 src/{ => stlink-lib}/sg.c | 1 + src/{ => stlink-lib}/sg.h | 2 +- src/{ => stlink-lib}/usb.c | 3 +- src/{ => stlink-lib}/usb.h | 2 +- tests/CMakeLists.txt | 2 +- 32 files changed, 193 insertions(+), 222 deletions(-) create mode 100644 inc/CMakeLists.txt rename {include => inc}/stlink.h (100%) rename {include => inc}/stm32.h (100%) rename {include/stlink => inc}/version.h.in (100%) delete mode 100644 include/CMakeLists.txt rename {include/stlink => src}/backend.h (100%) rename {include/stlink => src}/commands.h (100%) rename src/{ => mmap}/mmap.c (100%) rename src/{ => mmap}/mmap.h (100%) rename {include/stlink => src}/reg.h (100%) rename src/{tools => st-flash}/flash.c (99%) rename {include/stlink/tools => src/st-flash}/flash.h (100%) rename src/{tools => st-flash}/flash_opts.c (99%) rename src/{tools => st-info}/info.c (100%) rename src/{ => stlink-lib}/chipid.c (99%) rename {include/stlink => src/stlink-lib}/chipid.h (100%) rename src/{ => stlink-lib}/flash_loader.c (71%) rename {include/stlink => src/stlink-lib}/flash_loader.h (100%) rename src/{ => stlink-lib}/logging.c (100%) rename src/{ => stlink-lib}/logging.h (100%) rename src/{ => stlink-lib}/md5.c (100%) rename src/{ => stlink-lib}/md5.h (100%) rename src/{ => stlink-lib}/sg.c (99%) rename src/{ => stlink-lib}/sg.h (98%) rename src/{ => stlink-lib}/usb.c (99%) rename src/{ => stlink-lib}/usb.h (98%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 0538f3b14..854ce9ed5 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -81,43 +81,41 @@ endif () ## Define include directories to avoid absolute paths for header defines include_directories(${LIBUSB_INCLUDE_DIR}) -# ==== -include_directories(${PROJECT_SOURCE_DIR}/include) ### TODO: Clean this up... -include_directories(${PROJECT_BINARY_DIR}/include/stlink) -include_directories(${PROJECT_SOURCE_DIR}/include/stlink) -include_directories(${PROJECT_SOURCE_DIR}/include/stlink/tools) -# ==== +include_directories(${PROJECT_SOURCE_DIR}/inc) # contains top-level header files +include_directories(${PROJECT_BINARY_DIR}/inc) # contains version.h include_directories(src) -include_directories(src/tools) ### TODO: Clean this up... +include_directories(src/mmap) +include_directories(src/st-flash) +include_directories(src/stlink-lib) set(STLINK_HEADERS - include/stlink.h - include/stlink/backend.h - include/stlink/chipid.h - include/stlink/commands.h - include/stlink/flash_loader.h - include/stlink/reg.h - src/logging.h - src/md5.h - src/sg.h - src/usb.h + inc/stlink.h + src/backend.h + src/commands.h + src/reg.h + src/stlink-lib/chipid.h + src/stlink-lib/flash_loader.h + src/stlink-lib/logging.h + src/stlink-lib/md5.h + src/stlink-lib/sg.h + src/stlink-lib/usb.h ) set(STLINK_SOURCE src/common.c - src/chipid.c - src/flash_loader.c - src/logging.c - src/md5.c - src/sg.c - src/usb.c + src/stlink-lib/chipid.c + src/stlink-lib/flash_loader.c + src/stlink-lib/logging.c + src/stlink-lib/md5.c + src/stlink-lib/sg.c + src/stlink-lib/usb.c ) if (WIN32 OR MINGW OR MSYS) include_directories(src/mingw) - set(STLINK_SOURCE "${STLINK_SOURCE};src/mmap.c;src/mingw/mingw.c") - set(STLINK_HEADERS "${STLINK_HEADERS};src/mmap.h;src/mingw/mingw.h") + set(STLINK_SOURCE "${STLINK_SOURCE};src/mmap/mmap.c;src/mingw/mingw.c") + set(STLINK_HEADERS "${STLINK_HEADERS};src/mmap/mmap.h;src/mingw/mingw.h") endif () if (MSVC) @@ -140,7 +138,7 @@ endif () set(STLINK_LIBRARY_PATH ${CMAKE_INSTALL_LIBDIR} CACHE PATH "Main library install directory") # Set the environment variable LD_LIBRARY_PATH to point to /usr/local/lib (per default). -execute_process (COMMAND bash -c "export LD_LIBRARY_PATH="${CMAKE_INSTALL_LIBDIR}" ") +execute_process (COMMAND bash -c "export LD_LIBRARY_PATH=${CMAKE_INSTALL_LIBDIR}") ### @@ -221,6 +219,8 @@ install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH}) # Build toolset executables ### +set(ST-FLASH_SOURCES src/st-flash/flash.c src/st-flash/flash_opts.c) +set(ST-INFO_SOURCES src/st-info/info.c) set(ST-UTIL_SOURCES src/st-util/gdb-remote.c src/st-util/gdb-server.c src/st-util/semihosting.c) if (MSVC) @@ -228,8 +228,8 @@ if (MSVC) set(ST-UTIL_SOURCES "${ST-UTIL_SOURCES};src/getopt/getopt.c") endif () -add_executable(st-flash src/tools/flash.c src/tools/flash_opts.c) -add_executable(st-info src/tools/info.c) +add_executable(st-flash ${ST-FLASH_SOURCES}) +add_executable(st-info ${ST-INFO_SOURCES}) add_executable(st-util ${ST-UTIL_SOURCES}) if (WIN32 OR APPLE) @@ -267,11 +267,7 @@ endif () # Additional build tasks ### -# ==== -add_subdirectory(include) # contains subordinate CMakeLists for version config and old header includes - ### TODO: Clean this up ... -# ==== - +add_subdirectory(inc) # contains subordinate CMakeLists for version config add_subdirectory(src/stlink-gui) # contains subordinate CMakeLists to build GUI add_subdirectory(tests) # contains subordinate CMakeLists to build test executables add_subdirectory(cmake/packaging) # contains subordinate CMakeLists to build packages diff --git a/doc/dev/developer.txt b/doc/dev/developer.txt index 4032eca3e..077234e54 100644 --- a/doc/dev/developer.txt +++ b/doc/dev/developer.txt @@ -8,9 +8,7 @@ In order to use pkg-config for development purposes, add the following lines to ## Package configuration (pkg-config) on unix-based systems if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) - add_subdirectory(doc/dev/pkg-config) # Option A: external tool pkg-config - find_package(PkgConfig) # Option B: internal cmake module for pkg-config integration - pkg_check_modules(GTK3 gtk+-3.0) + add_subdirectory(doc/dev/pkg-config) # external tool pkg-config endif () ToDo: Check for compatibility issues between options A and B. diff --git a/inc/CMakeLists.txt b/inc/CMakeLists.txt new file mode 100644 index 000000000..66af7e33f --- /dev/null +++ b/inc/CMakeLists.txt @@ -0,0 +1,9 @@ +configure_file( + "${PROJECT_SOURCE_DIR}/inc/version.h.in" + "${CMAKE_BINARY_DIR}/inc/version.h" + ) + +file(GLOB STLINK_HEADERS "src/st-link-lib/*.h" "${CMAKE_BINARY_DIR}/inc/version.h") +install(FILES ${STLINK_HEADERS} DESTINATION ${STLINK_INCLUDE_PATH}) +install(FILES ${CMAKE_SOURCE_DIR}/inc/stlink.h DESTINATION ${STLINK_INCLUDE_PATH}) +install(FILES ${CMAKE_SOURCE_DIR}/inc/stm32.h DESTINATION ${STLINK_INCLUDE_PATH}) diff --git a/include/stlink.h b/inc/stlink.h similarity index 100% rename from include/stlink.h rename to inc/stlink.h diff --git a/include/stm32.h b/inc/stm32.h similarity index 100% rename from include/stm32.h rename to inc/stm32.h diff --git a/include/stlink/version.h.in b/inc/version.h.in similarity index 100% rename from include/stlink/version.h.in rename to inc/version.h.in diff --git a/include/CMakeLists.txt b/include/CMakeLists.txt deleted file mode 100644 index 6cf397659..000000000 --- a/include/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -configure_file( - "${PROJECT_SOURCE_DIR}/include/stlink/version.h.in" - "${CMAKE_BINARY_DIR}/include/stlink/version.h" - ) - -file(GLOB STLINK_HEADERS "stlink/*.h" "${CMAKE_BINARY_DIR}/include/stlink/*.h") -install(FILES ${CMAKE_SOURCE_DIR}/include/stlink.h DESTINATION ${STLINK_INCLUDE_PATH}) -install(FILES ${CMAKE_SOURCE_DIR}/include/stm32.h DESTINATION ${STLINK_INCLUDE_PATH}) -install(FILES ${STLINK_HEADERS} DESTINATION ${STLINK_INCLUDE_PATH}/stlink) diff --git a/include/stlink/backend.h b/src/backend.h similarity index 100% rename from include/stlink/backend.h rename to src/backend.h diff --git a/include/stlink/commands.h b/src/commands.h similarity index 100% rename from include/stlink/commands.h rename to src/commands.h diff --git a/src/common.c b/src/common.c index e8f7cebc6..fb669e255 100644 --- a/src/common.c +++ b/src/common.c @@ -12,9 +12,9 @@ #include #include -#include "mmap.h" -#include "logging.h" -#include "md5.h" +#include +#include +#include #ifndef O_BINARY #define O_BINARY 0 diff --git a/src/mmap.c b/src/mmap/mmap.c similarity index 100% rename from src/mmap.c rename to src/mmap/mmap.c diff --git a/src/mmap.h b/src/mmap/mmap.h similarity index 100% rename from src/mmap.h rename to src/mmap/mmap.h diff --git a/include/stlink/reg.h b/src/reg.h similarity index 100% rename from include/stlink/reg.h rename to src/reg.h diff --git a/src/tools/flash.c b/src/st-flash/flash.c similarity index 99% rename from src/tools/flash.c rename to src/st-flash/flash.c index 3a83daf8a..fc62bcf15 100644 --- a/src/tools/flash.c +++ b/src/st-flash/flash.c @@ -9,7 +9,7 @@ #include #include -#include +#include "flash.h" static stlink_t *connected_stlink = NULL; diff --git a/include/stlink/tools/flash.h b/src/st-flash/flash.h similarity index 100% rename from include/stlink/tools/flash.h rename to src/st-flash/flash.h diff --git a/src/tools/flash_opts.c b/src/st-flash/flash_opts.c similarity index 99% rename from src/tools/flash_opts.c rename to src/st-flash/flash_opts.c index c8d7841de..9d8d3225b 100644 --- a/src/tools/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -2,7 +2,7 @@ #include #include -#include +#include "flash.h" static bool starts_with(const char * str, const char * prefix) { size_t n = strlen(prefix); diff --git a/src/tools/info.c b/src/st-info/info.c similarity index 100% rename from src/tools/info.c rename to src/st-info/info.c diff --git a/src/st-util/semihosting.c b/src/st-util/semihosting.c index fed66ab60..cb03868cd 100644 --- a/src/st-util/semihosting.c +++ b/src/st-util/semihosting.c @@ -9,70 +9,52 @@ #include #include "semihosting.h" -static int mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) -{ +static int mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { int offset = addr % 4; int len = 4; - if (sl == NULL || data == NULL) { - return -1; - } + if (sl == NULL || data == NULL) return -1; /* Read address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, len) != 0) { - return -1; - } + if (stlink_read_mem32(sl, addr - offset, len) != 0) return -1; *data = sl->q_buf[offset]; return 0; } #ifdef UNUSED -static int mem_read_u16(stlink_t *sl, uint32_t addr, uint16_t *data) -{ +static int mem_read_u16(stlink_t *sl, uint32_t addr, uint16_t *data) { int offset = addr % 4; int len = (offset > 2 ? 8 : 4); - if (sl == NULL || data == NULL) { - return -1; - } + if (sl == NULL || data == NULL) return -1; /* Read address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, len) != 0) { - return -1; - } + if (stlink_read_mem32(sl, addr - offset, len) != 0) return -1; memcpy(data, &sl->q_buf[offset], sizeof(*data)); return 0; } -static int mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) -{ +static int mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) { int offset = addr % 4; int len = (offset > 0 ? 8 : 4); - if (sl == NULL || data == NULL) { - return -1; - } + if (sl == NULL || data == NULL) return -1; /* Read address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, len) != 0) { - return -1; - } + if (stlink_read_mem32(sl, addr - offset, len) != 0) return -1; memcpy(data, &sl->q_buf[offset], sizeof(*data)); return 0; } #endif -static int mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) -{ +static int mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { int offset = addr % 4; int read_len = len + offset; - if (sl == NULL || data == NULL) { - return -1; - } + if (sl == NULL || data == NULL) return -1; /* Align read size */ if ((read_len % 4) != 0) { @@ -80,16 +62,13 @@ static int mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) } /* Address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, read_len) != 0) { - return -1; - } + if (stlink_read_mem32(sl, addr - offset, read_len) != 0) return -1; memcpy(data, &sl->q_buf[offset], len); return 0; } -static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) -{ +static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { // Note: this function can write more than it is asked to! // If addr is not an even 32 bit boundary, or len is not a multiple of 4. // @@ -106,9 +85,7 @@ static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) int offset = addr % 4; int write_len = len + offset; - if (sl == NULL || data == NULL) { - return -1; - } + if (sl == NULL || data == NULL) return -1; /* Align read size */ if ((write_len % 4) != 0) { @@ -118,9 +95,7 @@ static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) memcpy(&sl->q_buf[offset], data, len); /* Address and length must be aligned */ - if (stlink_write_mem32(sl, addr - offset, write_len) != 0) { - return -1; - } + if (stlink_write_mem32(sl, addr - offset, write_len) != 0) return -1; return 0; } @@ -162,9 +137,7 @@ static int saved_errno = 0; int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { - if (sl == NULL || ret == NULL) { - return -1; - } + if (sl == NULL || ret == NULL) return -1; DLOG("Do semihosting R0=0x%08x R1=0x%08x\n", r0, r1); diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index cc68509fe..89e5403d8 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -2,7 +2,10 @@ # Build GUI ### -if (NOT WIN32) +if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) + find_package(PkgConfig) + pkg_check_modules(GTK3 gtk+-3.0) + ## GUI-Building requires the presence of a GTK3 toolset if (NOT GTK3_FOUND) message(STATUS "GTK3 not found!") @@ -35,7 +38,5 @@ if (NOT WIN32) COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) - - endif () endif () diff --git a/src/chipid.c b/src/stlink-lib/chipid.c similarity index 99% rename from src/chipid.c rename to src/stlink-lib/chipid.c index fcc1c55eb..e6a82a2a9 100644 --- a/src/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,5 +1,5 @@ #include -#include +#include "chipid.h" static const struct stlink_chipid_params devices[] = { { diff --git a/include/stlink/chipid.h b/src/stlink-lib/chipid.h similarity index 100% rename from include/stlink/chipid.h rename to src/stlink-lib/chipid.h diff --git a/src/flash_loader.c b/src/stlink-lib/flash_loader.c similarity index 71% rename from src/flash_loader.c rename to src/stlink-lib/flash_loader.c index a2c5879ce..b97a6edaa 100644 --- a/src/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -3,6 +3,7 @@ #include #include +#include "flash_loader.h" #define FLASH_REGS_BANK2_OFS 0x40 #define FLASH_BANK2_START_ADDR 0x08080000 @@ -11,164 +12,164 @@ /* flashloaders/stm32f0.s -- compiled with thumb2 */ static const uint8_t loader_code_stm32vl[] = { - 0x16, 0x4f, 0x3c, 0x68, - 0x16, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x16, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x4f, 0xf0, 0x01, 0x07, - 0x33, 0x68, 0x3b, 0x43, - 0x33, 0x60, 0x03, 0x88, - 0x0b, 0x80, 0x4f, 0xf0, - 0x02, 0x07, 0xc0, 0x19, - 0xc9, 0x19, 0x4f, 0xf0, - 0x01, 0x07, 0x2b, 0x68, - 0x3b, 0x42, 0xfa, 0xd0, - 0x4f, 0xf0, 0x04, 0x07, - 0x3b, 0x42, 0x04, 0xd1, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xe6, 0xd1, 0x4f, 0xf0, - 0x01, 0x07, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x50, 0x00, 0x00, 0x20, - 0x54, 0x00, 0x00, 0x20, + 0x16, 0x4f, 0x3c, 0x68, + 0x16, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x16, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x4f, 0xf0, 0x01, 0x07, + 0x33, 0x68, 0x3b, 0x43, + 0x33, 0x60, 0x03, 0x88, + 0x0b, 0x80, 0x4f, 0xf0, + 0x02, 0x07, 0xc0, 0x19, + 0xc9, 0x19, 0x4f, 0xf0, + 0x01, 0x07, 0x2b, 0x68, + 0x3b, 0x42, 0xfa, 0xd0, + 0x4f, 0xf0, 0x04, 0x07, + 0x3b, 0x42, 0x04, 0xd1, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xe6, 0xd1, 0x4f, 0xf0, + 0x01, 0x07, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x20, + 0x54, 0x00, 0x00, 0x20, 0x58, 0x00, 0x00, 0x20 }; /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ static const uint8_t loader_code_stm32f0[] = { - 0xc0, 0x46, 0xc0, 0x46, - 0x13, 0x4f, 0x3c, 0x68, - 0x13, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x13, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x12, 0x4f, 0x33, 0x68, - 0x3b, 0x43, 0x33, 0x60, - 0x03, 0x88, 0x0b, 0x80, - 0x10, 0x4f, 0xc0, 0x19, - 0xc9, 0x19, 0x0e, 0x4f, - 0x2b, 0x68, 0x3b, 0x42, - 0xfb, 0xd0, 0x0e, 0x4f, - 0x3b, 0x42, 0x03, 0xd1, - 0x0a, 0x4f, 0xd2, 0x1b, - 0x00, 0x2a, 0xeb, 0xd1, - 0x08, 0x4f, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0xc0, 0x46, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x48, 0x00, 0x00, 0x20, - 0x4c, 0x00, 0x00, 0x20, - 0x50, 0x00, 0x00, 0x20, - 0x01, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, + 0xc0, 0x46, 0xc0, 0x46, + 0x13, 0x4f, 0x3c, 0x68, + 0x13, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x13, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x12, 0x4f, 0x33, 0x68, + 0x3b, 0x43, 0x33, 0x60, + 0x03, 0x88, 0x0b, 0x80, + 0x10, 0x4f, 0xc0, 0x19, + 0xc9, 0x19, 0x0e, 0x4f, + 0x2b, 0x68, 0x3b, 0x42, + 0xfb, 0xd0, 0x0e, 0x4f, + 0x3b, 0x42, 0x03, 0xd1, + 0x0a, 0x4f, 0xd2, 0x1b, + 0x00, 0x2a, 0xeb, 0xd1, + 0x08, 0x4f, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0xc0, 0x46, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x48, 0x00, 0x00, 0x20, + 0x4c, 0x00, 0x00, 0x20, + 0x50, 0x00, 0x00, 0x20, + 0x01, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32l[] = { // flashloaders/stm32lx.s - 0x03, 0x68, 0x0b, 0x60, - 0x4f, 0xf0, 0x04, 0x07, - 0x38, 0x44, 0x39, 0x44, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, + 0x03, 0x68, 0x0b, 0x60, + 0x4f, 0xf0, 0x04, 0x07, + 0x38, 0x44, 0x39, 0x44, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, 0xf4, 0xd1, 0x00, 0xbe, }; static const uint8_t loader_code_stm32f4[] = { // flashloaders/stm32f4.s - 0xdf, 0xf8, 0x28, 0xc0, - 0xdf, 0xf8, 0x28, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32f4_lv[] = { // flashloaders/stm32f4lv.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32l4[] = { // flashloaders/stm32l4.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x44, 0x68, 0x0b, 0x60, - 0x4c, 0x60, 0x00, 0xf1, - 0x08, 0x00, 0x01, 0xf1, - 0x08, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x44, 0x68, 0x0b, 0x60, + 0x4c, 0x60, 0x00, 0xf1, + 0x08, 0x00, 0x01, 0xf1, + 0x08, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, 0x12, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32f7[] = { // flashloaders/stm32f7.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32f7_lv[] = { // flashloaders/stm32f7lv.s - 0xdf, 0xf8, 0x30, 0xc0, - 0xdf, 0xf8, 0x30, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, + 0xdf, 0xf8, 0x30, 0xc0, + 0xdf, 0xf8, 0x30, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 }; diff --git a/include/stlink/flash_loader.h b/src/stlink-lib/flash_loader.h similarity index 100% rename from include/stlink/flash_loader.h rename to src/stlink-lib/flash_loader.h diff --git a/src/logging.c b/src/stlink-lib/logging.c similarity index 100% rename from src/logging.c rename to src/stlink-lib/logging.c diff --git a/src/logging.h b/src/stlink-lib/logging.h similarity index 100% rename from src/logging.h rename to src/stlink-lib/logging.h diff --git a/src/md5.c b/src/stlink-lib/md5.c similarity index 100% rename from src/md5.c rename to src/stlink-lib/md5.c diff --git a/src/md5.h b/src/stlink-lib/md5.h similarity index 100% rename from src/md5.h rename to src/stlink-lib/md5.h diff --git a/src/sg.c b/src/stlink-lib/sg.c similarity index 99% rename from src/sg.c rename to src/stlink-lib/sg.c index 798cda9ab..7fae19976 100644 --- a/src/sg.c +++ b/src/stlink-lib/sg.c @@ -84,6 +84,7 @@ #include #include "logging.h" +#include "sg.h" #define STLINK_OK 0x80 #define STLINK_FALSE 0x81 diff --git a/src/sg.h b/src/stlink-lib/sg.h similarity index 98% rename from src/sg.h rename to src/stlink-lib/sg.h index 3a8a7a239..811b339c7 100644 --- a/src/sg.h +++ b/src/stlink-lib/sg.h @@ -8,8 +8,8 @@ #ifndef STLINK_SG_H #define STLINK_SG_H -#include "libusb_settings.h" #include +#include #ifdef __cplusplus extern "C" { diff --git a/src/usb.c b/src/stlink-lib/usb.c similarity index 99% rename from src/usb.c rename to src/stlink-lib/usb.c index a711749da..b76639731 100644 --- a/src/usb.c +++ b/src/stlink-lib/usb.c @@ -14,6 +14,7 @@ #include #endif #include +#include "usb.h" enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; @@ -1147,7 +1148,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL if (reset == 2) { stlink_jtag_reset(sl,0); - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); stlink_force_debug(sl); stlink_jtag_reset(sl,1); usleep(10000); diff --git a/src/usb.h b/src/stlink-lib/usb.h similarity index 98% rename from src/usb.h rename to src/stlink-lib/usb.h index 5c1f5b7ca..3581eabf1 100644 --- a/src/usb.h +++ b/src/stlink-lib/usb.h @@ -11,7 +11,7 @@ #include #include -#include "libusb_settings.h" +#include #include "logging.h" #ifdef __cplusplus diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index 6e60fdd5a..a3011fc7e 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -11,6 +11,6 @@ foreach (test ${TESTEXEC}) add_test(test-${test} ${CMAKE_BINARY_DIR}/bin/test-${test}) endforeach () -add_executable(test-flash flash.c "${CMAKE_SOURCE_DIR}/src/tools/flash_opts.c") +add_executable(test-flash flash.c "${CMAKE_SOURCE_DIR}/src/st-flash/flash_opts.c") target_link_libraries(test-flash ${STLINK_LIB_SHARED} ${SSP_LIB}) add_test(test-flash ${CMAKE_BINARY_DIR}/bin/test-flash) From e895a7c85e8150bf6874f7831d3bee247418091b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 5 Jun 2020 16:41:47 +0200 Subject: [PATCH 0958/1435] [refactoring] Build settings for win32 - Grouped source files for win32 - Whitespace & code style cleanup --- CMakeLists.txt | 62 ++++--- src/common.c | 100 ++++++------ src/mmap/mmap.h | 31 ---- src/st-util/gdb-remote.c | 4 +- src/st-util/gdb-server.c | 2 +- src/stlink-lib/usb.c | 5 +- src/{ => win32}/getopt/LICENSE.txt | 0 src/{ => win32}/getopt/README.md | 0 src/{ => win32}/getopt/getopt.c | 0 src/{ => win32}/getopt/getopt.h | 0 src/{mmap => win32}/mmap.c | 1 - src/win32/mmap.h | 29 ++++ src/win32/{ => unistd}/unistd.h | 0 src/{mingw/mingw.c => win32/win32_socket.c} | 171 +++++++++----------- src/{mingw/mingw.h => win32/win32_socket.h} | 20 +-- 15 files changed, 206 insertions(+), 219 deletions(-) delete mode 100644 src/mmap/mmap.h rename src/{ => win32}/getopt/LICENSE.txt (100%) rename src/{ => win32}/getopt/README.md (100%) rename src/{ => win32}/getopt/getopt.c (100%) rename src/{ => win32}/getopt/getopt.h (100%) rename src/{mmap => win32}/mmap.c (99%) create mode 100644 src/win32/mmap.h rename src/win32/{ => unistd}/unistd.h (100%) rename src/{mingw/mingw.c => win32/win32_socket.c} (59%) rename src/{mingw/mingw.h => win32/win32_socket.h} (81%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 854ce9ed5..c1ced137d 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -48,29 +48,34 @@ endif () find_package(libusb REQUIRED) ## Check for system-specific additional header files and libraries + include(CheckIncludeFile) +include(CheckLibraryExists) + +CHECK_LIBRARY_EXISTS(ssp __stack_chk_fail "" _stack_chk_fail_exists) +if (_stack_chk_fail_exists) + if (WIN32) + set(SSP_LIB -static ssp) + else () + set(SSP_LIB ssp) + endif () +else () + set(SSP_LIB "") +endif () CHECK_INCLUDE_FILE(sys/mman.h STLINK_HAVE_SYS_MMAN_H) if (STLINK_HAVE_SYS_MMAN_H) add_definitions(-DSTLINK_HAVE_SYS_MMAN_H) -endif () +endif() CHECK_INCLUDE_FILE(unistd.h STLINK_HAVE_UNISTD_H) if (STLINK_HAVE_UNISTD_H) add_definitions(-DSTLINK_HAVE_UNISTD_H) endif () -include(CheckLibraryExists) - -CHECK_LIBRARY_EXISTS(ssp __stack_chk_fail "" _stack_chk_fail_exists) -if (_stack_chk_fail_exists) - if(WIN32) - set(SSP_LIB -static ssp) - else() - set(SSP_LIB ssp) - endif() -else () - set(SSP_LIB "") +if (MSVC) + # Use string.h rather than strings.h and disable annoying warnings + add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) endif () @@ -85,10 +90,14 @@ include_directories(${PROJECT_SOURCE_DIR}/inc) # contains top-level header files include_directories(${PROJECT_BINARY_DIR}/inc) # contains version.h include_directories(src) -include_directories(src/mmap) include_directories(src/st-flash) include_directories(src/stlink-lib) +if (MSVC) + include_directories(src/win32) + include_directories(src/win32/unistd) +endif () + set(STLINK_HEADERS inc/stlink.h src/backend.h @@ -112,17 +121,21 @@ set(STLINK_SOURCE src/stlink-lib/usb.c ) -if (WIN32 OR MINGW OR MSYS) - include_directories(src/mingw) - set(STLINK_SOURCE "${STLINK_SOURCE};src/mmap/mmap.c;src/mingw/mingw.c") - set(STLINK_HEADERS "${STLINK_HEADERS};src/mmap/mmap.h;src/mingw/mingw.h") -endif () - -if (MSVC) +if (WIN32) include_directories(src/win32) - include_directories(src/getopt) - # Use string.h rather than strings.h and disable annoying warnings - add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) + set(STLINK_SOURCE "${STLINK_SOURCE};src/win32/win32_socket.c") + set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/win32_socket.h") + + if (MSVC) + include_directories(src/win32/unistd) + set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/unistd/unistd.h") + endif () + + if (NOT STLINK_HAVE_SYS_MMAN_H) + include_directories(src/win32/mmap) + set(STLINK_SOURCE "${STLINK_SOURCE};src/win32/mmap.c") + set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/mmap.h") + endif() endif () ## Include test execution for test-targets for target Debug @@ -225,7 +238,8 @@ set(ST-UTIL_SOURCES src/st-util/gdb-remote.c src/st-util/gdb-server.c src/st-uti if (MSVC) # Add getopt to sources - set(ST-UTIL_SOURCES "${ST-UTIL_SOURCES};src/getopt/getopt.c") + include_directories(src/win32/getopt) + set(ST-UTIL_SOURCES "${ST-UTIL_SOURCES};src/win32/getopt/getopt.c") endif () add_executable(st-flash ${ST-FLASH_SOURCES}) diff --git a/src/common.c b/src/common.c index fb669e255..c9a54cf9f 100644 --- a/src/common.c +++ b/src/common.c @@ -12,10 +12,15 @@ #include #include -#include #include #include +#ifdef STLINK_HAVE_SYS_MMAN_H +#include +#else +#include +#endif + #ifndef O_BINARY #define O_BINARY 0 #endif @@ -193,24 +198,26 @@ #define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) #define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) -#define STM32L4_FLASH_SR_BSY 16 -#define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */ - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ -#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ +#define STM32L4_FLASH_SR_BSY 16 +#define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */ + +#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ +#define STM32L4_FLASH_CR_PG 0 /* Program */ +#define STM32L4_FLASH_CR_PER 1 /* Page erase */ +#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ +#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ +#define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ +#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ +#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ // Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu<flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; - x |= 1 << FLASH_CR_PG; + x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; - x |= 1 << STM32L4_FLASH_CR_PG; + x |= (1 << STM32L4_FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; @@ -662,7 +668,7 @@ static void set_flash_cr_pg(stlink_t *sl) { x |= (1 << FLASH_CR_PG); } else { cr_reg = FLASH_CR; - x = 1 << FLASH_CR_PG; + x = (1 << FLASH_CR_PG); } stlink_write_debug32(sl, cr_reg, x); @@ -704,7 +710,7 @@ static void set_flash_cr_per(stlink_t *sl) { } static void set_flash_cr2_per(stlink_t *sl) { - const uint32_t n = 1 << FLASH_CR_PER; + const uint32_t n = (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_CR2, n); } @@ -728,12 +734,12 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); - cr_pg = 1 << STM32L4_FLASH_CR_PG; + cr_pg = (1 << STM32L4_FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; @@ -748,8 +754,8 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { cr_pg = (1 << FLASH_CR_PG); } else { cr_reg = FLASH_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); } stlink_read_debug32(sl, cr_reg, &val); @@ -767,8 +773,8 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { } static void set_flash_cr2_mer(stlink_t *sl, bool v) { - const uint32_t cr_pg = 1 << FLASH_CR_PER; - const uint32_t cr_mer = 1 << FLASH_CR_MER; + const uint32_t cr_pg = (1 << FLASH_CR_PER); + const uint32_t cr_mer = (1 << FLASH_CR_MER); uint32_t val; stlink_read_debug32(sl, FLASH_CR2, &val); @@ -785,13 +791,13 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; - cr_mer = 1 << FLASH_CR_MER; + cr_mer = (1 << FLASH_CR_MER); } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); } else { cr_reg = FLASH_CR; - cr_mer = 1 << FLASH_CR_MER; + cr_mer = (1 << FLASH_CR_MER); } stlink_read_debug32(sl, cr_reg, &val); @@ -804,20 +810,20 @@ static void set_flash_cr_strt(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; - cr_strt = 1 << FLASH_F4_CR_STRT; + cr_strt = (1 << FLASH_F4_CR_STRT); } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; - cr_strt = 1 << STM32L4_FLASH_CR_STRT; + cr_strt = (1 << STM32L4_FLASH_CR_STRT); } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - cr_strt = 1 << STM32Gx_FLASH_CR_STRT; + cr_strt = (1 << STM32Gx_FLASH_CR_STRT); } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; - cr_strt = 1 << STM32WB_FLASH_CR_STRT; + cr_strt = (1 << STM32WB_FLASH_CR_STRT); } else { cr_reg = FLASH_CR; - cr_strt = 1 << FLASH_CR_STRT; + cr_strt = (1 << FLASH_CR_STRT); } stlink_read_debug32(sl, cr_reg, &val); @@ -2377,8 +2383,7 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, } -int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize) -{ +int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize) { unsigned int count; unsigned int num_half_pages = len / pagesize; uint32_t val; @@ -2742,7 +2747,8 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, uint32_t end = 0; bool eof_found = false; - for (int scan = 0; (res == 0) && (scan < 2); ++scan) { // parse file two times - first to find memory range, second - to fill it + for (int scan = 0; (res == 0) && (scan < 2); ++scan) { + // parse file two times - first to find memory range, second - to fill it if (scan == 1) { if (!eof_found) { ELOG("No EoF recond\n"); @@ -3015,8 +3021,7 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_ * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) -{ +static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t flash_base = get_stm32l0_flash_base(sl); uint32_t val; uint32_t data; @@ -3162,8 +3167,7 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { * @param option_byte option value * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) -{ +int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) { if (sl->option_base == 0) { ELOG("Option bytes read is currently not supported for connected chip\n"); return -1; @@ -3190,8 +3194,7 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) -{ +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { WLOG("About to write option byte %#10x to target.\n", option_byte); return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *) &option_byte, 4); } @@ -3203,8 +3206,7 @@ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) * @param base option bytes to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) -{ +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { int ret = -1; if (sl->option_base == 0) { diff --git a/src/mmap/mmap.h b/src/mmap/mmap.h deleted file mode 100644 index ab94fb7d4..000000000 --- a/src/mmap/mmap.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef STLINK_MMAP_H -#define STLINK_MMAP_H - -#ifdef STLINK_HAVE_SYS_MMAN_H -#include -#else - -#define PROT_READ (1<<0) -#define PROT_WRITE (1<<1) - -#define MAP_SHARED (1<<0) -#define MAP_PRIVATE (1<<1) - -#define MAP_ANONYMOUS (1<<5) - -#define MAP_FAILED ((void *)-1) - -#ifdef __cplusplus -extern "C" { -#endif - - void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); - int munmap(void *addr, size_t len); - -#ifdef __cplusplus -} -#endif - -#endif /* HAVE_SYS_MMAN_H */ - -#endif /* STLINK_MMAP_H */ diff --git a/src/st-util/gdb-remote.c b/src/st-util/gdb-remote.c index 24636e8c9..d5ea0b1c6 100644 --- a/src/st-util/gdb-remote.c +++ b/src/st-util/gdb-remote.c @@ -9,8 +9,8 @@ #include #include -#if defined(__MINGW32__) || defined(_MSC_VER) -#include +#if defined(_WIN32) +#include #else #include #include diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index a7107ff88..b851409e0 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -16,7 +16,7 @@ #endif #if defined(_WIN32) -#include +#include #else #include #include diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index b76639731..ec126cc7e 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -10,9 +10,10 @@ #include #include -#if defined(__MINGW32__) || defined(_MSC_VER) -#include +#if defined(_WIN32) +#include #endif + #include #include "usb.h" diff --git a/src/getopt/LICENSE.txt b/src/win32/getopt/LICENSE.txt similarity index 100% rename from src/getopt/LICENSE.txt rename to src/win32/getopt/LICENSE.txt diff --git a/src/getopt/README.md b/src/win32/getopt/README.md similarity index 100% rename from src/getopt/README.md rename to src/win32/getopt/README.md diff --git a/src/getopt/getopt.c b/src/win32/getopt/getopt.c similarity index 100% rename from src/getopt/getopt.c rename to src/win32/getopt/getopt.c diff --git a/src/getopt/getopt.h b/src/win32/getopt/getopt.h similarity index 100% rename from src/getopt/getopt.h rename to src/win32/getopt/getopt.h diff --git a/src/mmap/mmap.c b/src/win32/mmap.c similarity index 99% rename from src/mmap/mmap.c rename to src/win32/mmap.c index b76e4ad64..60bb440e9 100644 --- a/src/mmap/mmap.c +++ b/src/win32/mmap.c @@ -20,7 +20,6 @@ void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offs return MAP_FAILED; } - count = read(fd, buf, len); if (count != (ssize_t)len) { diff --git a/src/win32/mmap.h b/src/win32/mmap.h new file mode 100644 index 000000000..1f2e756cb --- /dev/null +++ b/src/win32/mmap.h @@ -0,0 +1,29 @@ +#ifndef STLINK_MMAP_H +#define STLINK_MMAP_H + +#ifdef STLINK_HAVE_SYS_MMAN_H +#include +#else + +#define PROT_READ (1 << 0) +#define PROT_WRITE (1 << 1) + +#define MAP_SHARED (1 << 0) +#define MAP_PRIVATE (1 << 1) +#define MAP_ANONYMOUS (1 << 5) +#define MAP_FAILED ((void *)-1) + +#ifdef __cplusplus +extern "C" { +#endif + +void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); +int munmap(void *addr, size_t len); + +#ifdef __cplusplus +} +#endif + +#endif /* HAVE_SYS_MMAN_H */ + +#endif /* STLINK_MMAP_H */ diff --git a/src/win32/unistd.h b/src/win32/unistd/unistd.h similarity index 100% rename from src/win32/unistd.h rename to src/win32/unistd/unistd.h diff --git a/src/mingw/mingw.c b/src/win32/win32_socket.c similarity index 59% rename from src/mingw/mingw.c rename to src/win32/win32_socket.c index 646fca238..3a3abae16 100644 --- a/src/mingw/mingw.c +++ b/src/win32/win32_socket.c @@ -1,6 +1,6 @@ -#if defined(__MINGW32__) || defined(_MSC_VER) +#if defined(_WIN32) -#include "mingw.h" +#include "win32_socket.h" #undef socket #undef connect @@ -11,23 +11,23 @@ #include #include -int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) -{ +int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { struct timeval timeout, *toptr; fd_set ifds, ofds, efds, *ip, *op; unsigned int i; int rc; - /* Set up the file-descriptor sets in ifds, ofds and efds. */ #ifdef _MSC_VER #pragma warning(disable: 4548) #endif + + /* Set up the file-descriptor sets in ifds, ofds and efds. */ FD_ZERO(&ifds); FD_ZERO(&ofds); FD_ZERO(&efds); for (i = 0, op = ip = 0; i < nfds; ++i) { fds[i].revents = 0; - if (fds[i].events & (POLLIN|POLLPRI)) { + if (fds[i].events & (POLLIN | POLLPRI)) { ip = &ifds; FD_SET(fds[i].fd, ip); } @@ -36,7 +36,8 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) FD_SET(fds[i].fd, op); } FD_SET(fds[i].fd, &efds); - } + } + #ifdef _MSC_VER #pragma warning(default: 4548) #endif @@ -54,13 +55,14 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) printf("Entering select() sec=%ld usec=%ld ip=%lx op=%lx\n", (long)timeout.tv_sec, (long)timeout.tv_usec, (long)ip, (long)op); #endif + rc = select(0, ip, op, &efds, toptr); + #ifdef DEBUG_POLL printf("Exiting select rc=%d\n", rc); #endif - if (rc <= 0) - return rc; + if (rc <= 0) return rc; if (rc > 0) { for ( i = 0; i < nfds; ++i) { @@ -72,19 +74,20 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) if (FD_ISSET(fd, &efds)) /* Some error was detected ... should be some way to know. */ fds[i].revents |= POLLHUP; + #ifdef DEBUG_POLL - printf("%d %d %d revent = %x\n", - FD_ISSET(fd, &ifds), FD_ISSET(fd, &ofds), FD_ISSET(fd, &efds), - fds[i].revents - ); + printf("%d %d %d revent = %x\n", + FD_ISSET(fd, &ifds), FD_ISSET(fd, &ofds), FD_ISSET(fd, &efds), + fds[i].revents + ); #endif + } } return rc; } -static void -set_connect_errno(int winsock_err) -{ + +static void set_connect_errno(int winsock_err) { switch(winsock_err) { case WSAEINVAL: case WSAEALREADY: @@ -97,9 +100,7 @@ set_connect_errno(int winsock_err) } } -static void -set_socket_errno(int winsock_err) -{ +static void set_socket_errno(int winsock_err) { switch(winsock_err) { case WSAEWOULDBLOCK: errno = EAGAIN; @@ -109,44 +110,36 @@ set_socket_errno(int winsock_err) break; } } + /* - * A wrapper around the socket() function. The purpose of this wrapper - * is to ensure that the global errno symbol is set if an error occurs, + * A wrapper around the socket() function. + * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ -SOCKET -win32_socket(int domain, int type, int protocol) -{ +SOCKET win32_socket(int domain, int type, int protocol) { SOCKET fd = socket(domain, type, protocol); - if (fd == INVALID_SOCKET) { - set_socket_errno(WSAGetLastError()); - } + if (fd == INVALID_SOCKET) set_socket_errno(WSAGetLastError()); return fd; } + /* - * A wrapper around the connect() function. The purpose of this wrapper - * is to ensure that the global errno symbol is set if an error occurs, + * A wrapper around the connect() function. + * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ -int -win32_connect(SOCKET fd, struct sockaddr *addr, socklen_t addr_len) -{ +int win32_connect(SOCKET fd, struct sockaddr *addr, socklen_t addr_len) { int rc = connect(fd, addr, addr_len); assert(rc == 0 || rc == SOCKET_ERROR); - if (rc == SOCKET_ERROR) { - set_connect_errno(WSAGetLastError()); - } + if (rc == SOCKET_ERROR) set_connect_errno(WSAGetLastError()); return rc; } /* - * A wrapper around the accept() function. The purpose of this wrapper - * is to ensure that the global errno symbol is set if an error occurs, + * A wrapper around the accept() function. + * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ -SOCKET -win32_accept(SOCKET fd, struct sockaddr *addr, socklen_t *addr_len) -{ +SOCKET win32_accept(SOCKET fd, struct sockaddr *addr, socklen_t *addr_len) { SOCKET newfd = accept(fd, addr, addr_len); if (newfd == INVALID_SOCKET) { set_socket_errno(WSAGetLastError()); @@ -156,62 +149,45 @@ win32_accept(SOCKET fd, struct sockaddr *addr, socklen_t *addr_len) } /* - * A wrapper around the shutdown() function. The purpose of this wrapper - * is to ensure that the global errno symbol is set if an error occurs, + * A wrapper around the shutdown() function. + * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ -int -win32_shutdown(SOCKET fd, int mode) -{ +int win32_shutdown(SOCKET fd, int mode) { int rc = shutdown(fd, mode); assert(rc == 0 || rc == SOCKET_ERROR); - if (rc == SOCKET_ERROR) { - set_socket_errno(WSAGetLastError()); - } + if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); return rc; } -int win32_close_socket(SOCKET fd) -{ +int win32_close_socket(SOCKET fd) { int rc = closesocket(fd); - if (rc == SOCKET_ERROR) { - set_socket_errno(WSAGetLastError()); - } + if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); return rc; } -ssize_t win32_write_socket(SOCKET fd, void *buf, int n) -{ +ssize_t win32_write_socket(SOCKET fd, void *buf, int n) { int rc = send(fd, buf, n, 0); - if (rc == SOCKET_ERROR) { - set_socket_errno(WSAGetLastError()); - } + if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); return rc; } -ssize_t win32_read_socket(SOCKET fd, void *buf, int n) -{ +ssize_t win32_read_socket(SOCKET fd, void *buf, int n) { int rc = recv(fd, buf, n, 0); - if (rc == SOCKET_ERROR) { - set_socket_errno(WSAGetLastError()); - } + if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); return rc; } -char * win32_strtok_r(char *s, const char *delim, char **lasts) -{ +char * win32_strtok_r(char *s, const char *delim, char **lasts) { register char *spanp; register int c, sc; char *tok; - if (s == NULL && (s = *lasts) == NULL) - return (NULL); + if (s == NULL && (s = *lasts) == NULL) return (NULL); - /* - * Skip (span) leading delimiters (s += strspn(s, delim), sort of). - */ + // Skip (span) leading delimiters (s += strspn(s, delim), sort of). cont: c = *s++; for (spanp = (char *)delim; (sc = *spanp++) != 0;) { @@ -219,7 +195,7 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) goto cont; } - if (c == 0) { /* no non-delimiter characters */ + if (c == 0) { // no non-delimiter characters *lasts = NULL; return (NULL); } @@ -234,10 +210,11 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) spanp = (char *)delim; do { if ((sc = *spanp++) == c) { - if (c == 0) + if (c == 0) { s = NULL; - else + } else { s[-1] = 0; + } *lasts = s; return (tok); } @@ -246,24 +223,23 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) /* NOTREACHED */ } -char *win32_strsep (char **stringp, const char *delim) -{ +char *win32_strsep (char **stringp, const char *delim) { register char *s; register const char *spanp; register int c, sc; char *tok; - if ((s = *stringp) == NULL) - return (NULL); + if ((s = *stringp) == NULL) return (NULL); for (tok = s;;) { c = *s++; spanp = delim; do { if ((sc = *spanp++) == c) { - if (c == 0) + if (c == 0) { s = NULL; - else + } else { s[-1] = 0; + } *stringp = s; return (tok); } @@ -273,24 +249,23 @@ char *win32_strsep (char **stringp, const char *delim) } #ifndef STLINK_HAVE_UNISTD_H -int usleep(unsigned int waitTime) -{ - if (waitTime >= 1000) - { - // Don't do long busy-waits. - // However much it seems like the QPC code would be more accurate, - // you can and probably will lose your time slice at any point during the wait, - // so we might as well voluntarily give up the CPU with a WaitForSingleObject. - HANDLE timer; - LARGE_INTEGER dueTime; - dueTime.QuadPart = -10 * (LONGLONG)waitTime; - - timer = CreateWaitableTimer(NULL, TRUE, NULL); - SetWaitableTimer(timer, &dueTime, 0, NULL, NULL, 0); - WaitForSingleObject(timer, INFINITE); - CloseHandle(timer); +int usleep(unsigned int waitTime) { + if (waitTime >= 1000) { + /* Don't do long busy-waits. + * However much it seems like the QPC code would be more accurate, + * you can and probably will lose your time slice at any point during the wait, + * so we might as well voluntarily give up the CPU with a WaitForSingleObject. + */ + HANDLE timer; + LARGE_INTEGER dueTime; + dueTime.QuadPart = -10 * (LONGLONG)waitTime; + timer = CreateWaitableTimer(NULL, TRUE, NULL); + SetWaitableTimer(timer, &dueTime, 0, NULL, NULL, 0); + WaitForSingleObject(timer, INFINITE); + CloseHandle(timer); + return 0; - } + } LARGE_INTEGER perf_cnt, start, now; QueryPerformanceFrequency(&perf_cnt); @@ -304,6 +279,4 @@ int usleep(unsigned int waitTime) } #endif -#endif - - +#endif // defined(_WIN32) diff --git a/src/mingw/mingw.h b/src/win32/win32_socket.h similarity index 81% rename from src/mingw/mingw.h rename to src/win32/win32_socket.h index 8f5b992fe..0d26a80e3 100644 --- a/src/mingw/mingw.h +++ b/src/win32/win32_socket.h @@ -9,19 +9,20 @@ #include #include + #if defined(_MSC_VER) #pragma comment(lib, "ws2_32.lib") #endif + #include #if defined(_MSC_VER) #pragma warning(pop) #endif -/* winsock doesn't feature poll(), so there is a version implemented - * in terms of select() in mingw.c. The following definitions - * are copied from linux man pages. A poll() macro is defined to - * call the version in mingw.c. +/* winsock doesn't feature poll(), so there is a version implemented in terms of select() in mingw.c. + * The following definitions are copied from linux man pages. + * A poll() macro is defined to call the version in mingw.c. */ #if !defined(_WIN32_WINNT) || (_WIN32_WINNT < 0x0600) @@ -39,11 +40,10 @@ struct pollfd { #endif #define poll(x, y, z) win32_poll(x, y, z) -/* These wrappers do nothing special except set the global errno variable if - * an error occurs (winsock doesn't do this by default). They set errno - * to unix-like values (i.e. WSAEWOULDBLOCK is mapped to EAGAIN), so code - * outside of this file "shouldn't" have to worry about winsock specific error - * handling. +/* These wrappers do nothing special except set the global errno variable if an error occurs + * (winsock doesn't do this by default). + * They set errno to unix-like values (i.e. WSAEWOULDBLOCK is mapped to EAGAIN), + * so code outside of this file "shouldn't" have to worry about winsock specific error handling. */ #define socket(x, y, z) win32_socket(x, y, z) #define connect(x, y, z) win32_connect(x, y, z) @@ -71,4 +71,4 @@ char *win32_strsep(char **stringp, const char *delim); ssize_t win32_read_socket(SOCKET fd, void *buf, int n); ssize_t win32_write_socket(SOCKET fd, void *buf, int n); -#endif //defined(__MINGW32__) || defined(_MSC_VER) +#endif // defined(__MINGW32__) || defined(_MSC_VER) From 97974649c38533a2a7a2e72bb356fe20e8b232ce Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 6 Jun 2020 00:13:15 +0200 Subject: [PATCH 0959/1435] Whitespace & code style cleanup --- CMakeLists.txt | 7 +- src/st-util/gdb-remote.c | 35 +-- src/st-util/gdb-server.c | 518 +++++++++++++++----------------------- src/stlink-lib/usb.c | 2 + src/win32/unistd/unistd.h | 12 +- src/win32/win32_socket.c | 4 +- src/win32/win32_socket.h | 4 +- 7 files changed, 227 insertions(+), 355 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index c1ced137d..8428e7565 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -9,6 +9,7 @@ set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) + ### # General project settings ### @@ -93,11 +94,6 @@ include_directories(src) include_directories(src/st-flash) include_directories(src/stlink-lib) -if (MSVC) - include_directories(src/win32) - include_directories(src/win32/unistd) -endif () - set(STLINK_HEADERS inc/stlink.h src/backend.h @@ -127,6 +123,7 @@ if (WIN32) set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/win32_socket.h") if (MSVC) + # Add drop-in replacement for unistd.h to sources include_directories(src/win32/unistd) set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/unistd/unistd.h") endif () diff --git a/src/st-util/gdb-remote.c b/src/st-util/gdb-remote.c index d5ea0b1c6..04729cc75 100644 --- a/src/st-util/gdb-remote.c +++ b/src/st-util/gdb-remote.c @@ -1,7 +1,6 @@ /* * Copyright (C) 2011 Peter Zotov - * Use of this source code is governed by a BSD-style - * license that can be found in the LICENSE file. + * Use of this source code is governed by a BSD-style license that can be found in the LICENSE file. */ #include @@ -23,7 +22,7 @@ static const char hex[] = "0123456789abcdef"; int gdb_send_packet(int fd, char* data) { unsigned int data_length = (unsigned int) strlen(data); int length = data_length + 4; - char* packet = malloc(length); /* '$' data (hex) '#' cksum (hex) */ + char* packet = malloc(length); // '$' data (hex) '#' cksum (hex) memset(packet, 0, length); @@ -67,8 +66,7 @@ int gdb_recv_packet(int fd, char** buffer) { char* packet_buffer = malloc(packet_size); unsigned state; - if (packet_buffer == NULL) - return -2; + if (packet_buffer == NULL) return -2; start: state = 0; @@ -90,11 +88,7 @@ int gdb_recv_packet(int fd, char** buffer) { switch(state) { case 0: - if (c != '$') { - // ignore - } else { - state = 1; - } + if (c != '$') { /* ignore */ } else { state = 1; } break; case 1: @@ -107,9 +101,9 @@ int gdb_recv_packet(int fd, char** buffer) { if (packet_idx == packet_size) { packet_size += ALLOC_STEP; void* p = realloc(packet_buffer, packet_size); - if (p != NULL) + if (p != NULL) { packet_buffer = p; - else { + } else { free(packet_buffer); return -2; } @@ -136,7 +130,6 @@ int gdb_recv_packet(int fd, char** buffer) { free(packet_buffer); return -2; } - goto start; } else { char ack = '+'; @@ -152,9 +145,11 @@ int gdb_recv_packet(int fd, char** buffer) { return packet_idx; } -// Here we skip any characters which are not \x03, GDB interrupt. -// As we use the mode with ACK, in a (very unlikely) situation of a packet -// lost because of this skipping, it will be resent anyway. +/* + * Here we skip any characters which are not \x03, GDB interrupt. + * As we use the mode with ACK, in a (very unlikely) situation of a packet lost + * because of this skipping, it will be resent anyway. + */ int gdb_check_for_interrupt(int fd) { struct pollfd pfd; pfd.fd = fd; @@ -162,12 +157,8 @@ int gdb_check_for_interrupt(int fd) { if (poll(&pfd, 1, 0) != 0) { char c; - - if (read(fd, &c, 1) != 1) - return -2; - - if (c == '\x03') // ^C - return 1; + if (read(fd, &c, 1) != 1) return -2; + if (c == '\x03') return 1; // ^C } return 0; diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index b851409e0..119d0ff9a 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -1,8 +1,8 @@ /* * Copyright (C) 2011 Peter Zotov - * Use of this source code is governed by a BSD-style - * license that can be found in the LICENSE file. + * Use of this source code is governed by a BSD-style license that can be found in the LICENSE file. */ + #include #include #include @@ -10,6 +10,7 @@ #include #include #include + #if defined(_MSC_VER) #include #define __attribute__(x) @@ -32,11 +33,11 @@ #define FLASH_BASE 0x08000000 -/* Semihosting doesn't have a short option, we define a value to identify it */ +// Semihosting doesn't have a short option, we define a value to identify it #define SEMIHOSTING_OPTION 128 #define SERIAL_OPTION 127 -//Allways update the FLASH_PAGE before each use, by calling stlink_calculate_pagesize +// always update the FLASH_PAGE before each use, by calling stlink_calculate_pagesize #define FLASH_PAGE (sl->flash_pgsz) static stlink_t *connected_stlink = NULL; @@ -71,7 +72,7 @@ char* make_memory_map(stlink_t *sl); static void init_cache (stlink_t *sl); static void cleanup(int signum) { - (void)signum; + (void)signum; if (connected_stlink) { /* Switch back to mass storage mode before closing. */ @@ -86,10 +87,10 @@ static void cleanup(int signum) { static stlink_t* do_connect(st_state_t *st) { stlink_t *sl = NULL; - if (serial_specified) { - sl = stlink_open_usb(st->logging_level, st->reset, serialnumber, 0); - } else { - sl = stlink_open_usb(st->logging_level, st->reset, NULL, 0); + if (serial_specified) { + sl = stlink_open_usb(st->logging_level, st->reset, serialnumber, 0); + } else { + sl = stlink_open_usb(st->logging_level, st->reset, NULL, 0); } return sl; } @@ -201,18 +202,16 @@ int main(int argc, char** argv) { st_state_t state; memset(&state, 0, sizeof(state)); - // set defaults... + // set defaults ... state.logging_level = DEFAULT_LOGGING_LEVEL; state.listen_port = DEFAULT_GDB_LISTEN_PORT; - state.reset = 1; /* By default, reset board */ + state.reset = 1; // by default, reset board parse_options(argc, argv, &state); printf("st-util\n"); sl = do_connect(&state); - if (sl == NULL) { - return 1; - } + if (sl == NULL) return 1; if (sl->chip_id == STLINK_CHIPID_UNKNOWN) { ELOG("Unsupported Target (Chip ID is %#010x, Core ID is %#010x).\n", sl->chip_id, sl->core_id); @@ -224,42 +223,32 @@ int main(int argc, char** argv) { signal(SIGTERM, &cleanup); signal(SIGSEGV, &cleanup); - if (state.reset) { - stlink_reset(sl); - } + if (state.reset) stlink_reset(sl); DLOG("Chip ID is %#010x, Core ID is %#08x.\n", sl->chip_id, sl->core_id); sl->verbose=0; current_memory_map = make_memory_map(sl); -#if defined(__MINGW32__) || defined(_MSC_VER) - WSADATA wsadata; - if (WSAStartup(MAKEWORD(2,2),&wsadata) !=0){ - goto winsock_error; - } +#if defined(_WIN32) + WSADATA wsadata; + if (WSAStartup(MAKEWORD(2,2),&wsadata) !=0) goto winsock_error; #endif init_cache(sl); do { - if (serve(sl, &state)) { - usleep (1 * 1000); // don't go bezurk if serve returns with error - } - - /* in case serve() changed the connection */ - sl = connected_stlink; - - /* Continue */ - stlink_run(sl); + if (serve(sl, &state)) { usleep (1 * 1000); } // don't go beserk if serve returns with error + sl = connected_stlink; // in case serve() changed the connection + stlink_run(sl); // continue } while (state.persistent); -#if defined(__MINGW32__) || defined(_MSC_VER) +#if defined(_WIN32) winsock_error: WSACleanup(); #endif - /* Switch back to mass storage mode before closing. */ + // switch back to mass storage mode before closing stlink_exit_debug_mode(sl); stlink_close(sl); @@ -507,7 +496,7 @@ static const char* const memory_map_template_F4_DE = ""; char* make_memory_map(stlink_t *sl) { - /* This will be freed in serve() */ + // this will be freed in serve() const size_t sz = 4096; char* map = malloc(sz); map[0] = '\0'; @@ -545,7 +534,6 @@ char* make_memory_map(stlink_t *sl) { return map; } - /* * DWT_COMP0 0xE0001020 * DWT_MASK0 0xE0001024 @@ -589,8 +577,8 @@ static void init_data_watchpoints(stlink_t *sl) { } } -static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, - stm32_addr_t addr, unsigned int len) { +static int add_data_watchpoint( + stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len) { int i = 0; uint32_t mask, dummy; @@ -635,8 +623,7 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, return -1; } -static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) -{ +static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { int i; for (i = 0 ; i < DATA_WATCH_NUM; i++) { @@ -657,9 +644,9 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) static int code_break_num; static int code_lit_num; -#define CODE_BREAK_NUM_MAX 15 -#define CODE_BREAK_LOW 0x01 -#define CODE_BREAK_HIGH 0x02 +#define CODE_BREAK_NUM_MAX 15 +#define CODE_BREAK_LOW 0x01 +#define CODE_BREAK_HIGH 0x02 struct code_hw_breakpoint { stm32_addr_t addr; @@ -687,9 +674,7 @@ static void init_code_breakpoints(stlink_t *sl) { static int has_breakpoint(stm32_addr_t addr) { for (int i = 0; i < code_break_num; i++) { - if (code_breaks[i].addr == addr) { - return 1; - } + if (code_breaks[i].addr == addr) return 1; } return 0; } @@ -704,52 +689,43 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { return -1; } - if (sl->core_id==STM32F7_CORE_ID) { - fpb_addr = addr; - } else { - fpb_addr = addr & ~0x3; - } + if (sl->core_id==STM32F7_CORE_ID) { + fpb_addr = addr; + } else { + fpb_addr = addr & ~0x3; + } int id = -1; for (int i = 0; i < code_break_num; i++) { - if (fpb_addr == code_breaks[i].addr || - (set && code_breaks[i].type == 0)) { + if (fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { id = i; break; } } if (id == -1) { - if (set) return -1; // Free slot not found - else return 0; // Breakpoint is already removed + if (set) { return -1; } // free slot not found + else { return 0; } // breakpoint is already removed } struct code_hw_breakpoint* bp = &code_breaks[id]; bp->addr = fpb_addr; - if (sl->core_id==STM32F7_CORE_ID) { - if (set) bp->type = type; - else bp->type = 0; - - mask = (bp->addr) | 1; - } else { - if (set) bp->type |= type; - else bp->type &= ~type; - - mask = (bp->addr) | 1 | (bp->type << 30); - } + if (sl->core_id==STM32F7_CORE_ID) { + if (set) { bp->type = type; } else { bp->type = 0; } + mask = (bp->addr) | 1; + } else { + if (set) { bp->type |= type; } else { bp->type &= ~type; } + mask = (bp->addr) | 1 | (bp->type << 30); + } if (bp->type == 0) { DLOG("clearing hw break %d\n", id); - stlink_write_debug32(sl, 0xe0002008 + id * 4, 0); } else { - DLOG("setting hw break %d at %08x (%d)\n", - id, bp->addr, bp->type); - DLOG("reg %08x \n", - mask); - + DLOG("setting hw break %d at %08x (%d)\n", id, bp->addr, bp->type); + DLOG("reg %08x \n", mask); stlink_write_debug32(sl, 0xe0002008 + id * 4, mask); } @@ -782,7 +758,6 @@ static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { struct flash_block* new = malloc(sizeof(struct flash_block)); new->next = flash_root; - new->addr = addr; new->length = length; new->data = calloc(length, 1); @@ -824,8 +799,7 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { } if (fit_length != length) { - WLOG("data block %08x -> %04x truncated to %04x\n", - addr, length, fit_length); + WLOG("data block %08x -> %04x truncated to %04x\n", addr, length, fit_length); WLOG("(this is not an error, just a GDB glitch)\n"); } @@ -835,7 +809,7 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { static int flash_go(stlink_t *sl) { int error = -1; - // Some kinds of clock settings do not allow writing to flash. + // some kinds of clock settings do not allow writing to flash. stlink_reset(sl); stlink_force_debug(sl); @@ -845,14 +819,13 @@ static int flash_go(stlink_t *sl) { for (stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += (uint32_t)FLASH_PAGE) { unsigned length = fb->length - (page - fb->addr); - //Update FLASH_PAGE + // update FLASH_PAGE stlink_calculate_pagesize(sl, page); DLOG("flash_do: page %08x\n", page); unsigned len = (length > FLASH_PAGE) ? (unsigned int) FLASH_PAGE : length; int ret = stlink_write_flash(sl, page, fb->data + (page - fb->addr), len, 0); - if (ret < 0) - goto error; + if (ret < 0) goto error; } } @@ -882,98 +855,86 @@ static int flash_go(stlink_t *sl) { #define DCCSW 0xE000EF6C #define ICIALLU 0xE000EF50 -struct cache_level_desc -{ - unsigned int nsets; - unsigned int nways; - unsigned int log2_nways; - unsigned int width; +struct cache_level_desc { + unsigned int nsets; + unsigned int nways; + unsigned int log2_nways; + unsigned int width; }; -struct cache_desc_t -{ - /* Minimal line size in bytes. */ - unsigned int dminline; - unsigned int iminline; +struct cache_desc_t { + // Minimal line size in bytes + unsigned int dminline; + unsigned int iminline; - /* Last level of unification (uniprocessor). */ - unsigned int louu; + // Last level of unification (uniprocessor) + unsigned int louu; - struct cache_level_desc icache[7]; - struct cache_level_desc dcache[7]; + struct cache_level_desc icache[7]; + struct cache_level_desc dcache[7]; }; static struct cache_desc_t cache_desc; -/* Return the smallest R so that V <= (1 << R). Not performance critical. */ -static unsigned ceil_log2(unsigned v) -{ - unsigned res; - for (res = 0; (1U << res) < v; res++) - ; - return res; +// return the smallest R so that V <= (1 << R); not performance critical +static unsigned ceil_log2(unsigned v) { + unsigned res; + for (res = 0; (1U << res) < v; res++) ; + return res; } -static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) -{ - unsigned int ccsidr; - unsigned int log2_nsets; - - stlink_read_debug32(sl, CCSIDR, &ccsidr); - desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1; - desc->nways = ((ccsidr >> 3) & 0x1ff) + 1; - desc->log2_nways = ceil_log2 (desc->nways); - log2_nsets = ceil_log2 (desc->nsets); - desc->width = 4 + (ccsidr & 7) + log2_nsets; - ILOG("%08x LineSize: %u, ways: %u, sets: %u (width: %u)\n", - ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width); +static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) { + unsigned int ccsidr; + unsigned int log2_nsets; + + stlink_read_debug32(sl, CCSIDR, &ccsidr); + desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1; + desc->nways = ((ccsidr >> 3) & 0x1ff) + 1; + desc->log2_nways = ceil_log2 (desc->nways); + log2_nsets = ceil_log2 (desc->nsets); + desc->width = 4 + (ccsidr & 7) + log2_nsets; + ILOG("%08x LineSize: %u, ways: %u, sets: %u (width: %u)\n", + ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width); } static void init_cache (stlink_t *sl) { - unsigned int clidr; - unsigned int ccr; - unsigned int ctr; - int i; - - /* Assume only F7 has a cache. */ - if (sl->core_id!=STM32F7_CORE_ID) - return; - - stlink_read_debug32(sl, CLIDR, &clidr); - stlink_read_debug32(sl, CCR, &ccr); - stlink_read_debug32(sl, CTR, &ctr); - cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f); - cache_desc.iminline = 4 << (ctr & 0x0f); - cache_desc.louu = (clidr >> 27) & 7; - - ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n", - clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off"); - ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n", - (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7); - ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr, - cache_desc.dminline, cache_desc.iminline); - for (i = 0; i < 7; i++) - { - unsigned int ct = (clidr >> (3 * i)) & 0x07; - - cache_desc.dcache[i].width = 0; - cache_desc.icache[i].width = 0; - - if (ct == 2 || ct == 3 || ct == 4) - { - /* Data. */ - stlink_write_debug32(sl, CSSELR, i << 1); - ILOG("D-Cache L%d: ", i); - read_cache_level_desc(sl, &cache_desc.dcache[i]); - } - - if (ct == 1 || ct == 3) - { - /* Instruction. */ - stlink_write_debug32(sl, CSSELR, (i << 1) | 1); - ILOG("I-Cache L%d: ", i); - read_cache_level_desc(sl, &cache_desc.icache[i]); - } + unsigned int clidr; + unsigned int ccr; + unsigned int ctr; + int i; + + // Assume only F7 has a cache + if (sl->core_id!=STM32F7_CORE_ID) return; + + stlink_read_debug32(sl, CLIDR, &clidr); + stlink_read_debug32(sl, CCR, &ccr); + stlink_read_debug32(sl, CTR, &ctr); + cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f); + cache_desc.iminline = 4 << (ctr & 0x0f); + cache_desc.louu = (clidr >> 27) & 7; + + ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n", + clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off"); + ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n", + (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7); + ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr, + cache_desc.dminline, cache_desc.iminline); + for (i = 0; i < 7; i++) { + unsigned int ct = (clidr >> (3 * i)) & 0x07; + cache_desc.dcache[i].width = 0; + cache_desc.icache[i].width = 0; + + if (ct == 2 || ct == 3 || ct == 4) { // Data + stlink_write_debug32(sl, CSSELR, i << 1); + ILOG("D-Cache L%d: ", i); + read_cache_level_desc(sl, &cache_desc.dcache[i]); + } + + if (ct == 1 || ct == 3) { // Instruction + stlink_write_debug32(sl, CSSELR, (i << 1) | 1); + ILOG("I-Cache L%d: ", i); + read_cache_level_desc(sl, &cache_desc.icache[i]); + } } } @@ -987,54 +948,43 @@ static void cache_flush(stlink_t *sl, unsigned ccr) { unsigned max_addr = 1 << desc->width; unsigned way_sh = 32 - desc->log2_nways; - /* D-cache clean by set-ways. */ + // D-cache clean by set-ways. for (addr = (level << 1); addr < max_addr; addr += cache_desc.dminline) { unsigned int way; - for (way = 0; way < desc->nways; way++) - stlink_write_debug32(sl, DCCSW, addr | (way << way_sh)); - } + stlink_write_debug32(sl, DCCSW, addr | (way << way_sh)); + } } - /* Invalidate all I-cache to oPU. */ - if (ccr & CCR_IC) - stlink_write_debug32(sl, ICIALLU, 0); + // invalidate all I-cache to oPU + if (ccr & CCR_IC) stlink_write_debug32(sl, ICIALLU, 0); } static int cache_modified; -static void cache_change(stm32_addr_t start, unsigned count) -{ - if (count == 0) - return; - (void)start; - cache_modified = 1; +static void cache_change(stm32_addr_t start, unsigned count) { + if (count == 0) return; + (void)start; + cache_modified = 1; } -static void cache_sync(stlink_t *sl) -{ - unsigned ccr; +static void cache_sync(stlink_t *sl) { + unsigned ccr; - if (sl->core_id!=STM32F7_CORE_ID) - return; - if (!cache_modified) - return; - cache_modified = 0; + if (sl->core_id!=STM32F7_CORE_ID) return; + if (!cache_modified) return; + cache_modified = 0; - stlink_read_debug32(sl, CCR, &ccr); - if (ccr & (CCR_IC | CCR_DC)) - cache_flush(sl, ccr); + stlink_read_debug32(sl, CCR, &ccr); + if (ccr & (CCR_IC | CCR_DC)) cache_flush(sl, ccr); } -static size_t unhexify(const char *in, char *out, size_t out_count) -{ +static size_t unhexify(const char *in, char *out, size_t out_count) { size_t i; unsigned int c; for (i = 0; i < out_count; i++) { - if (sscanf(in + (2 * i), "%02x", &c) != 1) { - return i; - } + if (sscanf(in + (2 * i), "%02x", &c) != 1) return i; out[i] = (char)c; } @@ -1082,24 +1032,21 @@ int serve(stlink_t *sl, st_state_t *st) { close_socket(sock); stlink_force_debug(sl); - if (st->reset) { - stlink_reset(sl); - } + if (st->reset) stlink_reset(sl); init_code_breakpoints(sl); init_data_watchpoints(sl); ILOG("GDB connected.\n"); /* - * To allow resetting the chip from GDB it is required to - * emulate attaching and detaching to target. + * To allow resetting the chip from GDB it is required to emulate attaching + * and detaching to target. */ unsigned int attached = 1; - /* - * If a critical error is detected, break from the loop - */ + // if a critical error is detected, break from the loop int critical_error = 0; int ret; + while (1) { ret = 0; char* packet; @@ -1137,12 +1084,11 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("query: %s;%s\n", queryName, params); if (!strcmp(queryName, "Supported")) { - if (sl->chip_id==STLINK_CHIPID_STM32_F4 - || sl->chip_id==STLINK_CHIPID_STM32_F4_HD - || sl->core_id==STM32F7_CORE_ID) { - reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); - } - else { + if (sl->chip_id==STLINK_CHIPID_STM32_F4 || + sl->chip_id==STLINK_CHIPID_STM32_F4_HD || + sl->core_id==STM32F7_CORE_ID) { + reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); + } else { reply = strdup("PacketSize=3fff;qXfer:memory-map:read+"); } } else if (!strcmp(queryName, "Xfer")) { @@ -1174,7 +1120,6 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned data_length = (unsigned int) strlen(data); if (addr + length > data_length) length = data_length - addr; - if (length == 0) { reply = strdup("l"); } else { @@ -1208,52 +1153,48 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("unhexified Rcmd: '%s'\n", cmd); - if (!strncmp(cmd, "resume", 6)) {// resume + if (!strncmp(cmd, "resume", 6)) { // resume DLOG("Rcmd: resume\n"); cache_sync(sl); ret = stlink_run(sl); if (ret) { DLOG("Rcmd: resume failed\n"); reply = strdup("E00"); - } else { reply = strdup("OK"); } - } else if (!strncmp(cmd, "halt", 4)) { //halt + } else if (!strncmp(cmd, "halt", 4)) { // halt ret = stlink_force_debug(sl); if (ret) { DLOG("Rcmd: halt failed\n"); reply = strdup("E00"); - } else { reply = strdup("OK"); DLOG("Rcmd: halt\n"); } - } else if (!strncmp(cmd, "jtag_reset", 10)) { //jtag_reset + } else if (!strncmp(cmd, "jtag_reset", 10)) { // jtag_reset reply = strdup("OK"); ret = stlink_jtag_reset(sl, 0); if (ret) { DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); reply = strdup("E00"); - } ret = stlink_jtag_reset(sl, 1); if (ret) { DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); reply = strdup("E00"); - } ret = stlink_force_debug(sl); if (ret) { DLOG("Rcmd: jtag_reset failed with force_debug\n"); reply = strdup("E00"); - } + if (strcmp(reply, "E00")) { // no errors have been found DLOG("Rcmd: jtag_reset\n"); @@ -1284,19 +1225,13 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("Rcmd: got semihosting cmd '%s'", cmd); char *arg = cmd + 12; - /* Skip whitespaces */ - while (isspace(*arg)) { - arg++; - } + // Skip whitespaces + while (isspace(*arg)) { arg++; } - if (!strncmp(arg, "enable", 6) - || !strncmp(arg, "1", 1)) - { + if (!strncmp(arg, "enable", 6) || !strncmp(arg, "1", 1)) { semihosting = true; reply = strdup("OK"); - } else if (!strncmp(arg, "disable", 7) - || !strncmp(arg, "0", 1)) - { + } else if (!strncmp(arg, "disable", 7) || !strncmp(arg, "0", 1)) { semihosting = false; reply = strdup("OK"); } else { @@ -1350,8 +1285,7 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned addr = (unsigned int) strtoul(__s_addr, NULL, 16); unsigned data_length = status - (unsigned int) (data - packet); - // Length of decoded data cannot be more than - // encoded, as escapes are removed. + // Length of decoded data cannot be more than encoded, as escapes are removed. // Additional byte is reserved for alignment fix. uint8_t *decoded = calloc(data_length + 1, 1); unsigned dec_index = 0; @@ -1364,9 +1298,8 @@ int serve(stlink_t *sl, st_state_t *st) { } } - // Fix alignment - if (dec_index % 2 != 0) - dec_index++; + // fix alignment + if (dec_index % 2 != 0) dec_index++; DLOG("binary packet %d -> %d\n", data_length, dec_index); @@ -1385,7 +1318,6 @@ int serve(stlink_t *sl, st_state_t *st) { } } else if (!strcmp(cmdName, "Kill")) { attached = 0; - reply = strdup("OK"); } @@ -1398,9 +1330,7 @@ int serve(stlink_t *sl, st_state_t *st) { case 'c': cache_sync(sl); ret = stlink_run(sl); - if (ret) { - DLOG("Semihost: run failed\n"); - } + if (ret) DLOG("Semihost: run failed\n"); while (1) { status = gdb_check_for_interrupt(client); @@ -1416,9 +1346,7 @@ int serve(stlink_t *sl, st_state_t *st) { } ret = stlink_status(sl); - if (ret) { - DLOG("Semihost: status failed\n"); - } + if (ret) DLOG("Semihost: status failed\n"); if(sl->core_stat == TARGET_HALTED) { struct stlink_reg reg; stm32_addr_t pc; @@ -1426,30 +1354,23 @@ int serve(stlink_t *sl, st_state_t *st) { int offset = 0; uint16_t insn; - if (!semihosting) { - break; - } + if (!semihosting) break; ret = stlink_read_all_regs (sl, ®); - if (ret) { - DLOG("Semihost: read_all_regs failed\n"); - } + if (ret) DLOG("Semihost: read_all_regs failed\n"); - /* Read PC */ + // Read PC pc = reg.r[15]; - /* Compute aligned value */ + // Compute aligned value offset = pc % 4; addr = pc - offset; - /* Read instructions (address and length must be - * aligned). - */ + // Read instructions (address and length must be aligned). ret = stlink_read_mem32(sl, addr, (offset > 2 ? 8 : 4)); if (ret != 0) { - DLOG("Semihost: cannot read instructions at: " - "0x%08x\n", addr); + DLOG("Semihost: cannot read instructions at: 0x%08x\n", addr); break; } @@ -1458,28 +1379,20 @@ int serve(stlink_t *sl, st_state_t *st) { if (insn == 0xBEAB && !has_breakpoint(addr)) { ret = do_semihosting (sl, reg.r[0], reg.r[1], ®.r[0]); - if (ret) { - DLOG("Semihost: do_semihosting failed\n"); - } + if (ret) DLOG("Semihost: do_semihosting failed\n"); - /* Write return value */ + // Write return value ret = stlink_write_reg(sl, reg.r[0], 0); - if (ret) { - DLOG("Semihost: write_reg failed for return value\n"); - } + if (ret) DLOG("Semihost: write_reg failed for return value\n"); - /* Jump over the break instruction */ + // Jump over the break instruction ret = stlink_write_reg(sl, reg.r[15] + 2, 15); - if (ret) { - DLOG("Semihost: write_reg failed for jumping over break\n"); - } + if (ret) DLOG("Semihost: write_reg failed for jumping over break\n"); - /* continue execution */ + // Continue execution cache_sync(sl); ret = stlink_run(sl); - if (ret) { - DLOG("Semihost: continue execution failed with stlink_run\n"); - } + if (ret) DLOG("Semihost: continue execution failed with stlink_run\n"); } else { break; } @@ -1492,10 +1405,10 @@ int serve(stlink_t *sl, st_state_t *st) { break; case 's': - cache_sync(sl); + cache_sync(sl); ret = stlink_step(sl); if (ret) { - // have problem sending step packet + // ... having a problem sending step packet ELOG("Step: cannot send step request\n"); reply = strdup("E00"); critical_error = 1; // absolutely critical @@ -1509,21 +1422,18 @@ int serve(stlink_t *sl, st_state_t *st) { if (attached) { reply = strdup("S05"); // TRAP } else { - /* Stub shall reply OK if not attached. */ + // Stub shall reply OK if not attached. reply = strdup("OK"); } break; case 'g': ret = stlink_read_all_regs(sl, ®p); - if (ret) { - DLOG("g packet: read_all_regs failed\n"); - } + if (ret) DLOG("g packet: read_all_regs failed\n"); reply = calloc(8 * 16 + 1, 1); for (int i = 0; i < 16; i++) sprintf(&reply[i * 8], "%08x", (uint32_t)htonl(regp.r[i])); - break; case 'p': { @@ -1564,12 +1474,10 @@ int serve(stlink_t *sl, st_state_t *st) { ret = 1; reply = strdup("E00"); } - if (ret) { - DLOG("p packet: stlink_read_unsupported_reg failed with id %u\n", id); - } + if (ret) DLOG("p packet: stlink_read_unsupported_reg failed with id %u\n", id); if (reply == NULL) { - // if reply is set to "E00", skip + // If reply is set to "E00", skip reply = calloc(8 + 1, 1); sprintf(reply, "%08x", myreg); } @@ -1609,13 +1517,8 @@ int serve(stlink_t *sl, st_state_t *st) { ret = 1; reply = strdup("E00"); } - if (ret) { - DLOG("P packet: stlink_write_unsupported_reg failed with reg %u\n", reg); - } - if (reply == NULL) { - // note that NULL may not be zero - reply = strdup("OK"); - } + if (ret) DLOG("P packet: stlink_write_unsupported_reg failed with reg %u\n", reg); + if (reply == NULL) reply = strdup("OK"); // note that NULL may not be zero break; } @@ -1626,9 +1529,7 @@ int serve(stlink_t *sl, st_state_t *st) { strncpy(str, &packet[1 + i * 8], 8); uint32_t reg = (uint32_t) strtoul(str, NULL, 16); ret = stlink_write_reg(sl, ntohl(reg), i); - if (ret) { - DLOG("G packet: stlink_write_reg failed"); - } + if (ret) DLOG("G packet: stlink_write_reg failed"); } reply = strdup("OK"); @@ -1643,17 +1544,12 @@ int serve(stlink_t *sl, st_state_t *st) { unsigned adj_start = start % 4; unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; - if (count_rnd > sl->flash_pgsz) - count_rnd = (unsigned int) sl->flash_pgsz; - if (count_rnd > 0x1800) - count_rnd = 0x1800; - if (count_rnd < count) - count = count_rnd; - - if (stlink_read_mem32(sl, start - adj_start, count_rnd) != 0) { - /* read failed somehow, don't return stale buffer */ - count = 0; - } + if (count_rnd > sl->flash_pgsz) count_rnd = (unsigned int) sl->flash_pgsz; + if (count_rnd > 0x1800) count_rnd = 0x1800; + if (count_rnd < count) count = count_rnd; + + if (stlink_read_mem32(sl, start - adj_start, count_rnd) != 0) count = 0; + // read failed somehow, don't return stale buffer reply = calloc(count * 2 + 1, 1); for (unsigned int i = 0; i < count; i++) { @@ -1785,15 +1681,9 @@ int serve(stlink_t *sl, st_state_t *st) { } case '!': { - /* - * Enter extended mode which allows restarting. - * We do support that always. - */ - - /* - * Also, set to persistent mode - * to allow GDB disconnect. - */ + // Enter extended mode which allows restarting. We do support that always. + + // Also, set to persistent mode to allow GDB disconnect. st->persistent = 1; reply = strdup("OK"); @@ -1802,9 +1692,7 @@ int serve(stlink_t *sl, st_state_t *st) { } case 'R': { - - /* Reset the core. */ - + // Reset the core. ret = stlink_reset(sl); if (ret) { DLOG("R packet : stlink_reset failed\n"); @@ -1819,35 +1707,25 @@ int serve(stlink_t *sl, st_state_t *st) { break; } case 'k': - /* Kill request - reset the connection itself */ + // Kill request - reset the connection itself ret = stlink_run(sl); - if (ret) { - DLOG("Kill: stlink_run failed\n"); - } - + if (ret) DLOG("Kill: stlink_run failed\n"); ret = stlink_exit_debug_mode(sl); - if (ret) { - DLOG("Kill: stlink_exit_debug_mode failed\n"); - } + if (ret) DLOG("Kill: stlink_exit_debug_mode failed\n"); stlink_close(sl); sl = do_connect(st); - if (sl == NULL || sl->chip_id == STLINK_CHIPID_UNKNOWN) - cleanup(0); + if (sl == NULL || sl->chip_id == STLINK_CHIPID_UNKNOWN) cleanup(0); connected_stlink = sl; - if (st->reset) { - stlink_reset(sl); - } + if (st->reset) stlink_reset(sl); ret = stlink_force_debug(sl); - if (ret) { - DLOG("Kill: stlink_force_debug failed\n"); - } + if (ret) DLOG("Kill: stlink_force_debug failed\n"); init_cache(sl); init_code_breakpoints(sl); init_data_watchpoints(sl); - reply = NULL; /* no response */ + reply = NULL; // no response break; diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index ec126cc7e..c22f2fe5e 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -3,9 +3,11 @@ #include #include #include + #if !defined(_MSC_VER) #include #endif + #include #include #include diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index 5b2798b41..0cdb9af7b 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -3,19 +3,23 @@ /* * This file intended to serve as a drop-in replacement for unistd.h on Windows - * Please add functionality as neeeded. + * Please add functionality as needed. */ #include #include + #if defined(_MSC_VER) #pragma warning(push) #pragma warning(disable: 4820) #endif + #include + #if defined(_MSC_VER) #pragma warning(pop) #endif + #include // getopt at: https://gist.github.com/ashelly/7776712 #include // for getpid() and the exec..() family #include // for _getcwd() and _chdir() @@ -23,7 +27,7 @@ #define srandom srand #define random rand -/* Values for the second argument to access. These may be OR'd together. */ +/* values for the second argument to access. These may be OR'd together. */ #define R_OK 4 // Test for read permission #define W_OK 2 // Test for write permission // #define X_OK 1 // execute permission - unsupported in windows @@ -48,7 +52,7 @@ #define STDIN_FILENO 0 #define STDOUT_FILENO 1 #define STDERR_FILENO 2 -/* should be in some equivalent to */ +// should be in some equivalent to typedef __int8 int8_t; typedef __int16 int16_t; typedef __int32 int32_t; @@ -62,4 +66,4 @@ typedef unsigned __int64 uint64_t; int usleep(unsigned int waitTime); #endif -#endif /* unistd.h */ +#endif // _UNISTD_H diff --git a/src/win32/win32_socket.c b/src/win32/win32_socket.c index 3a3abae16..18f2351f8 100644 --- a/src/win32/win32_socket.c +++ b/src/win32/win32_socket.c @@ -220,7 +220,7 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) { } } while (sc != 0); } - /* NOTREACHED */ + // NOT REACHED } char *win32_strsep (char **stringp, const char *delim) { @@ -245,7 +245,7 @@ char *win32_strsep (char **stringp, const char *delim) { } } while (sc != 0); } - /* NOTREACHED */ + // NOT REACHED } #ifndef STLINK_HAVE_UNISTD_H diff --git a/src/win32/win32_socket.h b/src/win32/win32_socket.h index 0d26a80e3..d2a3ac38c 100644 --- a/src/win32/win32_socket.h +++ b/src/win32/win32_socket.h @@ -1,4 +1,4 @@ -#if defined(__MINGW32__) || defined(_MSC_VER) +#if defined(_WIN32) #define _USE_W32_SOCKETS 1 @@ -71,4 +71,4 @@ char *win32_strsep(char **stringp, const char *delim); ssize_t win32_read_socket(SOCKET fd, void *buf, int n); ssize_t win32_write_socket(SOCKET fd, void *buf, int n); -#endif // defined(__MINGW32__) || defined(_MSC_VER) +#endif // defined(_WIN32) From 03a358bd078f8d0c965b26ba2ae3098894a2179a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 6 Jun 2020 01:00:17 +0200 Subject: [PATCH 0960/1435] Added check for cflag -std=gnu18 --- cmake/modules/c_flags.cmake | 1 + 1 file changed, 1 insertion(+) diff --git a/cmake/modules/c_flags.cmake b/cmake/modules/c_flags.cmake index 520182e37..8291ea0ee 100644 --- a/cmake/modules/c_flags.cmake +++ b/cmake/modules/c_flags.cmake @@ -18,6 +18,7 @@ function(add_cflag_if_supported flag) endfunction() add_cflag_if_supported("-std=gnu11") +add_cflag_if_supported("-std=gnu18") add_cflag_if_supported("-Wall") add_cflag_if_supported("-Wextra") add_cflag_if_supported("-Wshadow") From 77df52ff61fdfe2c8675b504e523535bf972da61 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 12:34:32 +0100 Subject: [PATCH 0961/1435] Update Files-Excluded in d/copyright for new layout --- debian/copyright | 4 +--- debian/source/options | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/debian/copyright b/debian/copyright index d56807ca5..cf13a5b4f 100644 --- a/debian/copyright +++ b/debian/copyright @@ -4,9 +4,7 @@ Upstream-Contact: Andrew 'Necromant' Andrianov Source: https://github.com/texane/stlink Comment: Upstream tarball has been repackaged to remove binary OSX kernel drivers that are of unknown license and of no use to Debian. - Upstream's debian directory is also removed. -Files-Excluded: stlinkv1_macosx_driver - debian +Files-Excluded: stlinkv1_macos_driver Files: * Copyright: 2011-2018 agpanarin diff --git a/debian/source/options b/debian/source/options index 7022977a9..506210d2c 100644 --- a/debian/source/options +++ b/debian/source/options @@ -1 +1 @@ -extend-diff-ignore=stlinkv1_macosx_driver +extend-diff-ignore=stlinkv1_macos_driver From 3775e7504eeecbae40813993dc181ae1605a5235 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 12:36:32 +0100 Subject: [PATCH 0962/1435] Fix d/watch intermediary file name --- debian/watch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian/watch b/debian/watch index 921dc8f0d..45fece19b 100644 --- a/debian/watch +++ b/debian/watch @@ -1,3 +1,3 @@ version=3 -opts=dversionmangle=s/\+ds$//,repacksuffix=+ds,filenamemangle=s/.+\/v?(\d\S+)\.tar\.gz/-$1\.tar\.gz/ \ +opts=dversionmangle=s/\+ds$//,repacksuffix=+ds,filenamemangle=s/.+\/v?(\d\S+)\.tar\.gz/stlink-$1\.tar\.gz/ \ https://github.com/texane/stlink/tags .*/v?(\d\S+)\.tar\.gz From b4ddd0d38dfabb88298179fcaf6f5fefa274e35d Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 12:44:55 +0100 Subject: [PATCH 0963/1435] Drop cross.patch, merged upstream in v1.6.1 --- debian/patches/cross.patch | 15 --------------- debian/patches/series | 1 - 2 files changed, 16 deletions(-) delete mode 100644 debian/patches/cross.patch delete mode 100644 debian/patches/series diff --git a/debian/patches/cross.patch b/debian/patches/cross.patch deleted file mode 100644 index 92084238b..000000000 --- a/debian/patches/cross.patch +++ /dev/null @@ -1,15 +0,0 @@ -Author: Helmut Grohne -Description: do not stop the GUI from being cross-compiled -Bug-Debian: 941320 -Forwarded: yes ---- a/CMakeLists.txt -+++ b/CMakeLists.txt -@@ -39,7 +39,7 @@ - # Dependencies - ### - find_package(LibUSB REQUIRED) --if (NOT APPLE AND NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) -+if (NOT APPLE AND NOT WIN32) - find_package(PkgConfig) - pkg_check_modules(gtk gtk+-3.0) - endif () diff --git a/debian/patches/series b/debian/patches/series deleted file mode 100644 index def274a02..000000000 --- a/debian/patches/series +++ /dev/null @@ -1 +0,0 @@ -cross.patch From fbaf536f940a5f93debc72ba69429dae4bba9252 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 14:30:41 +0100 Subject: [PATCH 0964/1435] Bump Build-Depends to cmake >= 3.4.2 --- debian/control | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian/control b/debian/control index 4382cdcd5..0e81de671 100644 --- a/debian/control +++ b/debian/control @@ -1,7 +1,7 @@ Source: stlink Priority: optional Maintainer: Luca Boccassi -Build-Depends: debhelper (>= 9), cmake, libusb-1.0-0-dev, libgtk-3-dev +Build-Depends: debhelper (>= 9), cmake (>= 3.4.2), libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.5.0 Rules-Requires-Root: no Section: electronics From 1ea5b4d8ff9bae9fc4d921563f800129e66ae164 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 14:30:56 +0100 Subject: [PATCH 0965/1435] Add new symbols from upstream version 1.6.1 --- debian/libstlink1.symbols | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/debian/libstlink1.symbols b/debian/libstlink1.symbols index 4518989a1..159f27d0f 100644 --- a/debian/libstlink1.symbols +++ b/debian/libstlink1.symbols @@ -1,4 +1,8 @@ libstlink.so.1 libstlink1 #MINVER# + Md5Calculate@Base 1.6.1 + Md5Finalise@Base 1.6.1 + Md5Initialise@Base 1.6.1 + Md5Update@Base 1.6.1 _parse_version@Base 1.5.0 _stlink_sg_close@Base 1.5.0 _stlink_sg_core_id@Base 1.5.0 @@ -29,6 +33,7 @@ libstlink.so.1 libstlink1 #MINVER# _stlink_usb_exit_debug_mode@Base 1.5.0 _stlink_usb_exit_dfu_mode@Base 1.5.0 _stlink_usb_force_debug@Base 1.5.0 + _stlink_usb_get_rw_status@Base 1.6.1 _stlink_usb_jtag_reset@Base 1.5.0 _stlink_usb_read_all_regs@Base 1.5.0 _stlink_usb_read_all_unsupported_regs@Base 1.5.0 @@ -40,6 +45,7 @@ libstlink.so.1 libstlink1 #MINVER# _stlink_usb_run@Base 1.5.0 _stlink_usb_set_swdclk@Base 1.5.0 _stlink_usb_status@Base 1.5.0 + _stlink_usb_status_v2@Base 1.6.1 _stlink_usb_step@Base 1.5.0 _stlink_usb_target_voltage@Base 1.5.0 _stlink_usb_version@Base 1.5.0 @@ -79,7 +85,7 @@ libstlink.so.1 libstlink1 #MINVER# stlink_fread@Base 1.5.0 stlink_fwrite_flash@Base 1.5.0 stlink_fwrite_option_bytes@Base 1.6.0 - stlink_fwrite_option_bytes_32bit@Base 1.6.0 +#MISSING: 1.6.1# stlink_fwrite_option_bytes_32bit@Base 1.6.0 stlink_fwrite_sram@Base 1.5.0 stlink_get_erased_pattern@Base 1.5.0 stlink_is_core_halted@Base 1.5.0 @@ -97,8 +103,11 @@ libstlink.so.1 libstlink1 #MINVER# stlink_read_all_unsupported_regs@Base 1.5.0 stlink_read_debug32@Base 1.5.0 stlink_read_mem32@Base 1.5.0 + stlink_read_option_bytes32@Base 1.6.1 + stlink_read_option_bytes_Gx@Base 1.6.1 stlink_read_option_bytes_f2@Base 1.6.0 stlink_read_option_bytes_f4@Base 1.6.0 + stlink_read_option_bytes_generic@Base 1.6.1 stlink_read_reg@Base 1.5.0 stlink_read_unsupported_reg@Base 1.5.0 stlink_reset@Base 1.5.0 @@ -119,11 +128,13 @@ libstlink.so.1 libstlink1 #MINVER# stlink_write_flash@Base 1.5.0 stlink_write_mem32@Base 1.5.0 stlink_write_mem8@Base 1.5.0 + stlink_write_option_bytes32@Base 1.6.1 stlink_write_option_bytes@Base 1.6.0 stlink_write_reg@Base 1.5.0 stlink_write_unsupported_reg@Base 1.5.0 stm32l1_write_half_pages@Base 1.5.0 ugly_init@Base 1.5.0 + ugly_libusb_log_level@Base 1.6.1 ugly_log@Base 1.5.0 write_buffer_to_sram@Base 1.5.0 write_uint16@Base 1.5.0 From c74c942a37913f70fa96a3e10dc6527b026c8fe7 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 14:31:24 +0100 Subject: [PATCH 0966/1435] Adjust install files, some files moved --- debian/stlink-gui.install | 8 ++++---- debian/stlink-tools.manpages | 4 +++- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/debian/stlink-gui.install b/debian/stlink-gui.install index b419ac054..5620a25e5 100644 --- a/debian/stlink-gui.install +++ b/debian/stlink-gui.install @@ -1,4 +1,4 @@ -/usr/bin/stlink-gui* -/usr/share/stlink/stlink-gui.ui -/usr/share/applications/stlink-gui.desktop -/usr/share/icons/hicolor/scalable/apps/stlink-gui.svg +/usr/bin/stlink-gui +/usr/bin/stlink-gui.ui /usr/share/stlink/ +/usr/share/stlink/applications/stlink-gui.desktop /usr/share/applications/ +/usr/share/stlink/icons/hicolor/scalable/apps/stlink-gui.svg /usr/share/icons/hicolor/scalable/apps/stlink-gui.svg diff --git a/debian/stlink-tools.manpages b/debian/stlink-tools.manpages index 6a461c09e..049509abe 100644 --- a/debian/stlink-tools.manpages +++ b/debian/stlink-tools.manpages @@ -1 +1,3 @@ -doc/man/st-*.1 +usr/share/stlink/man/man1/st-flash.1 +usr/share/stlink/man/man1/st-info.1 +usr/share/stlink/man/man1/st-util.1 From f5095079717ebe4168ac26ea0b4a65c0b1f4ec1f Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 14:31:41 +0100 Subject: [PATCH 0967/1435] Remove unused variable from d/rules --- debian/rules | 1 - 1 file changed, 1 deletion(-) diff --git a/debian/rules b/debian/rules index e228a7087..99ee08aa7 100755 --- a/debian/rules +++ b/debian/rules @@ -15,5 +15,4 @@ export DEB_BUILD_MAINT_OPTIONS = hardening=+all override_dh_auto_configure: dh_auto_configure -- \ - -DLIB_INSTALL_DIR=/usr/lib/$(DEB_HOST_MULTIARCH) \ -DSTLINK_UDEV_RULES_DIR='/lib/udev/rules.d' From 0052b907a9c216b816c79abc33b8ffb8fd29ec4f Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 14:32:03 +0100 Subject: [PATCH 0968/1435] Generate pkgconfig file from d/rules, upstream doesn't do it --- debian/rules | 5 +++++ debian/stlink.pc.in | 10 ++++++++++ 2 files changed, 15 insertions(+) create mode 100644 debian/stlink.pc.in diff --git a/debian/rules b/debian/rules index 99ee08aa7..512bd533f 100755 --- a/debian/rules +++ b/debian/rules @@ -16,3 +16,8 @@ export DEB_BUILD_MAINT_OPTIONS = hardening=+all override_dh_auto_configure: dh_auto_configure -- \ -DSTLINK_UDEV_RULES_DIR='/lib/udev/rules.d' + +override_dh_auto_install: + dh_auto_install + mkdir -p $(CURDIR)/debian/tmp/usr/lib/$(DEB_HOST_MULTIARCH)/pkgconfig + sed -e "s/@VERSION@/$(DEB_VERSION_UPSTREAM)/" -e "s/@DEB_HOST_MULTIARCH@/$(DEB_HOST_MULTIARCH)/" $(CURDIR)/debian/stlink.pc.in > $(CURDIR)/debian/tmp/usr/lib/$(DEB_HOST_MULTIARCH)/pkgconfig/stlink.pc diff --git a/debian/stlink.pc.in b/debian/stlink.pc.in new file mode 100644 index 000000000..7fde2d968 --- /dev/null +++ b/debian/stlink.pc.in @@ -0,0 +1,10 @@ +prefix=/usr +includedir=${prefix}/include/stlink +libdir=${prefix}/lib/@DEB_HOST_MULTIARCH@ + +Name: stlink +Description: Open source version of the STMicroelectronics Stlink Tools +Version: @VERSION@ +Requires: libusb-1.0 +Libs: -L${libdir} -lstlink +Cflags: -I${includedir} From b85c7fb41e9b5a8c5dcde7f6f241d101537e161f Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 14:33:19 +0100 Subject: [PATCH 0969/1435] Switch to debhelper-compat 12 --- debian/compat | 1 - debian/control | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) delete mode 100644 debian/compat diff --git a/debian/compat b/debian/compat deleted file mode 100644 index ec635144f..000000000 --- a/debian/compat +++ /dev/null @@ -1 +0,0 @@ -9 diff --git a/debian/control b/debian/control index 0e81de671..7172583e9 100644 --- a/debian/control +++ b/debian/control @@ -1,7 +1,7 @@ Source: stlink Priority: optional Maintainer: Luca Boccassi -Build-Depends: debhelper (>= 9), cmake (>= 3.4.2), libusb-1.0-0-dev, libgtk-3-dev +Build-Depends: debhelper-compat (= 12), cmake (>= 3.4.2), libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.5.0 Rules-Requires-Root: no Section: electronics From 7056afe415028d6786075d12325e3b835e5d0f02 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sat, 6 Jun 2020 14:45:15 +0100 Subject: [PATCH 0970/1435] Update changelog for 1.6.1+ds-1 release --- debian/changelog | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/debian/changelog b/debian/changelog index 0ad68fed3..26f17b1fb 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,18 @@ +stlink (1.6.1+ds-1) unstable; urgency=medium + + * Merge tag 'v1.6.1' into debian + * Update Files-Excluded in d/copyright for new layout + * Fix d/watch intermediary file name + * Drop cross.patch, merged upstream in v1.6.1 + * Bump Build-Depends to cmake >= 3.4.2 + * Add new symbols from upstream version 1.6.1 + * Adjust install files, some files moved + * Remove unused variable from d/rules + * Generate pkgconfig file from d/rules, upstream doesn't do it + * Switch to debhelper-compat 12 + + -- Luca Boccassi Sat, 06 Jun 2020 14:44:54 +0100 + stlink (1.6.0+ds-1) unstable; urgency=medium * Merge tag 'v1.6.0' into debian From c1918c0ff636494546bddbc5cc3793fc287c6594 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 12 Jun 2020 22:28:16 +0200 Subject: [PATCH 0971/1435] Aligned coding style - Added config for uncrustify style settings - Applied changes to source files - Moved some header files --- CMakeLists.txt | 7 +- config/code_style.cfg | 3090 ++++++++++++++++++++++++ flashloaders/linker.ld | 6 +- {src => inc}/backend.h | 4 +- inc/stlink.h | 57 +- inc/stm32.h | 10 +- inc/version.h.in | 2 +- src/common.c | 1970 +++++++-------- src/reg.h | 20 - src/st-flash/flash.c | 153 +- src/st-flash/flash.h | 11 +- src/st-flash/flash_opts.c | 342 +-- src/st-info/info.c | 103 +- src/st-util/gdb-remote.c | 55 +- src/st-util/gdb-remote.h | 2 +- src/st-util/gdb-server.c | 1664 +++++++------ src/st-util/gdb-server.h | 2 +- src/st-util/semihosting.c | 230 +- src/st-util/semihosting.h | 4 +- src/stlink-gui/gui.c | 1089 +++++---- src/stlink-gui/gui.h | 39 +- src/stlink-lib/chipid.c | 1259 +++++----- src/stlink-lib/chipid.h | 134 +- src/{ => stlink-lib}/commands.h | 2 +- src/stlink-lib/flash_loader.c | 497 ++-- src/stlink-lib/flash_loader.h | 8 +- src/{ => stlink-lib}/libusb_settings.h | 36 +- src/stlink-lib/logging.c | 36 +- src/stlink-lib/logging.h | 17 +- src/stlink-lib/md5.c | 259 +- src/stlink-lib/md5.h | 127 +- src/stlink-lib/reg.h | 20 + src/stlink-lib/sg.c | 401 +-- src/stlink-lib/sg.h | 45 +- src/stlink-lib/usb.c | 603 +++-- src/stlink-lib/usb.h | 66 +- src/win32/getopt/README.md | 7 +- src/win32/getopt/getopt.c | 341 ++- src/win32/getopt/getopt.h | 15 +- src/win32/mmap.c | 18 +- src/win32/unistd/unistd.h | 27 +- src/win32/win32_socket.c | 144 +- src/win32/win32_socket.h | 4 +- tests/flash.c | 237 +- tests/sg.c | 58 +- tests/usb.c | 42 +- 46 files changed, 8306 insertions(+), 4957 deletions(-) create mode 100644 config/code_style.cfg rename {src => inc}/backend.h (94%) delete mode 100644 src/reg.h rename src/{ => stlink-lib}/commands.h (97%) rename src/{ => stlink-lib}/libusb_settings.h (53%) create mode 100644 src/stlink-lib/reg.h diff --git a/CMakeLists.txt b/CMakeLists.txt index 8428e7565..52f6867f4 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -95,10 +95,11 @@ include_directories(src/st-flash) include_directories(src/stlink-lib) set(STLINK_HEADERS + inc/backend.h + src/stlink-lib/commands.h + src/stlink-lib/libusb_settings.h + src/stlink-lib/reg.h inc/stlink.h - src/backend.h - src/commands.h - src/reg.h src/stlink-lib/chipid.h src/stlink-lib/flash_loader.h src/stlink-lib/logging.h diff --git a/config/code_style.cfg b/config/code_style.cfg new file mode 100644 index 000000000..c6ced268c --- /dev/null +++ b/config/code_style.cfg @@ -0,0 +1,3090 @@ +# Uncrustify-0.71.0 + +# +# General options +# + +# The type of line endings. +# +# Default: auto +newlines = auto # lf/crlf/cr/auto + +# The original size of tabs in the input. +# +# Default: 8 +input_tab_size = 4 # unsigned number + +# The size of tabs in the output (only used if align_with_tabs=true). +# +# Default: 8 +output_tab_size = 4 # unsigned number + +# The ASCII value of the string escape char, usually 92 (\) or (Pawn) 94 (^). +# +# Default: 92 +string_escape_char = 92 # unsigned number + +# Alternate string escape char (usually only used for Pawn). +# Only works right before the quote char. +string_escape_char2 = 0 # unsigned number + +# Replace tab characters found in string literals with the escape sequence \t +# instead. +string_replace_tab_chars = false # true/false + +# Allow interpreting '>=' and '>>=' as part of a template in code like +# 'void f(list>=val);'. If true, 'assert(x<0 && y>=3)' will be broken. +# Improvements to template detection may make this option obsolete. +tok_split_gte = false # true/false + +# Disable formatting of NL_CONT ('\\n') ended lines (e.g. multiline macros) +#disable_processing_nl_cont = false # true/false ### not 0.69 + +# Specify the marker used in comments to disable processing of part of the +# file. +# The comment should be used alone in one line. +# +# Default: *INDENT-OFF* +disable_processing_cmt = " *INDENT-OFF*" # string + +# Specify the marker used in comments to (re)enable processing in a file. +# The comment should be used alone in one line. +# +# Default: *INDENT-ON* +enable_processing_cmt = " *INDENT-ON*" # string + +# Enable parsing of digraphs. +enable_digraphs = false # true/false + +# Add or remove the UTF-8 BOM (recommend 'remove'). +utf8_bom = ignore # ignore/add/remove/force + +# If the file contains bytes with values between 128 and 255, but is not +# UTF-8, then output as UTF-8. +utf8_byte = false # true/false + +# Force the output encoding to UTF-8. +utf8_force = true # true/false + +# Add or remove space between 'do' and '{'. +#sp_do_brace_open = add # ignore/add/remove/force ### not 0.69 + +# Add or remove space between '}' and 'while'. +#sp_brace_close_while = add # ignore/add/remove/force ### not 0.69 + +# Add or remove space between 'while' and '('. +#sp_while_paren_open = add # ignore/add/remove/force ### not 0.69 + +# +# Spacing options +# + +# Add or remove space around non-assignment symbolic operators ('+', '/', '%', +# '<<', and so forth). +sp_arith = add # ignore/add/remove/force + +# Add or remove space around arithmetic operators '+' and '-'. +# +# Overrides sp_arith. +sp_arith_additive = add # ignore/add/remove/force + +# Add or remove space around assignment operator '=', '+=', etc. +sp_assign = add # ignore/add/remove/force + +# Add or remove space around '=' in C++11 lambda capture specifications. +# +# Overrides sp_assign. +sp_cpp_lambda_assign = add # ignore/add/remove/force + +# Add or remove space after the capture specification of a C++11 lambda when +# an argument list is present, as in '[] (int x){ ... }'. +#sp_cpp_lambda_square_paren = add # ignore/add/remove/force ### not 0.69 + +# Add or remove space after the capture specification of a C++11 lambda with +# no argument list is present, as in '[] { ... }'. +#sp_cpp_lambda_square_brace = add # ignore/add/remove/force ### not 0.69 + +# Add or remove space after the argument list of a C++11 lambda, as in +# '[](int x) { ... }'. +#sp_cpp_lambda_paren_brace = add # ignore/add/remove/force ### not 0.69 + +# Add or remove space between a lambda body and its call operator of an +# immediately invoked lambda, as in '[]( ... ){ ... } ( ... )'. +#sp_cpp_lambda_fparen = add # ignore/add/remove/force ### not 0.69 + +# Add or remove space around assignment operator '=' in a prototype. +# +# If set to ignore, use sp_assign. +sp_assign_default = add # ignore/add/remove/force + +# Add or remove space before assignment operator '=', '+=', etc. +# +# Overrides sp_assign. +sp_before_assign = add # ignore/add/remove/force + +# Add or remove space after assignment operator '=', '+=', etc. +# +# Overrides sp_assign. +sp_after_assign = add # ignore/add/remove/force + +# Add or remove space in 'NS_ENUM ('. +sp_enum_paren = add # ignore/add/remove/force + +# Add or remove space around assignment '=' in enum. +sp_enum_assign = add # ignore/add/remove/force + +# Add or remove space before assignment '=' in enum. +# +# Overrides sp_enum_assign. +sp_enum_before_assign = add # ignore/add/remove/force + +# Add or remove space after assignment '=' in enum. +# +# Overrides sp_enum_assign. +sp_enum_after_assign = add # ignore/add/remove/force + +# Add or remove space around assignment ':' in enum. +sp_enum_colon = add # ignore/add/remove/force + +# Add or remove space around preprocessor '##' concatenation operator. +# +# Default: add +sp_pp_concat = add # ignore/add/remove/force + +# Add or remove space after preprocessor '#' stringify operator. +# Also affects the '#@' charizing operator. +sp_pp_stringify = ignore # ignore/add/remove/force + +# Add or remove space before preprocessor '#' stringify operator +# as in '#define x(y) L#y'. +sp_before_pp_stringify = ignore # ignore/add/remove/force + +# Add or remove space around boolean operators '&&' and '||'. +sp_bool = add # ignore/add/remove/force + +# Add or remove space around compare operator '<', '>', '==', etc. +sp_compare = add # ignore/add/remove/force + +# Add or remove space inside '(' and ')'. +sp_inside_paren = remove # ignore/add/remove/force + +# Add or remove space between nested parentheses, i.e. '((' vs. ') )'. +sp_paren_paren = remove # ignore/add/remove/force + +# Add or remove space between back-to-back parentheses, i.e. ')(' vs. ') ('. +sp_cparen_oparen = add # ignore/add/remove/force + +# Whether to balance spaces inside nested parentheses. +sp_balance_nested_parens = false # true/false + +# Add or remove space between ')' and '{'. +sp_paren_brace = add # ignore/add/remove/force + +# Add or remove space between nested braces, i.e. '{{' vs '{ {'. +sp_brace_brace = remove # ignore/add/remove/force + +# Add or remove space before pointer star '*'. +sp_before_ptr_star = ignore # ignore/add/remove/force + +# Add or remove space before pointer star '*' that isn't followed by a +# variable name. If set to ignore, sp_before_ptr_star is used instead. +sp_before_unnamed_ptr_star = ignore # ignore/add/remove/force + +# Add or remove space between pointer stars '*'. +sp_between_ptr_star = ignore # ignore/add/remove/force + +# Add or remove space after pointer star '*', if followed by a word. +# +# Overrides sp_type_func. +sp_after_ptr_star = ignore # ignore/add/remove/force + +# Add or remove space after pointer caret '^', if followed by a word. +sp_after_ptr_block_caret = ignore # ignore/add/remove/force + +# Add or remove space after pointer star '*', if followed by a qualifier. +sp_after_ptr_star_qualifier = ignore # ignore/add/remove/force + +# Add or remove space after a pointer star '*', if followed by a function +# prototype or function definition. +# +# Overrides sp_after_ptr_star and sp_type_func. +sp_after_ptr_star_func = ignore # ignore/add/remove/force + +# Add or remove space after a pointer star '*', if followed by an open +# parenthesis, as in 'void* (*)(). +sp_ptr_star_paren = ignore # ignore/add/remove/force + +# Add or remove space before a pointer star '*', if followed by a function +# prototype or function definition. +sp_before_ptr_star_func = ignore # ignore/add/remove/force + +# Add or remove space before a reference sign '&'. +sp_before_byref = ignore # ignore/add/remove/force + +# Add or remove space before a reference sign '&' that isn't followed by a +# variable name. If set to ignore, sp_before_byref is used instead. +sp_before_unnamed_byref = ignore # ignore/add/remove/force + +# Add or remove space after reference sign '&', if followed by a word. +# +# Overrides sp_type_func. +sp_after_byref = ignore # ignore/add/remove/force + +# Add or remove space after a reference sign '&', if followed by a function +# prototype or function definition. +# +# Overrides sp_after_byref and sp_type_func. +sp_after_byref_func = ignore # ignore/add/remove/force + +# Add or remove space before a reference sign '&', if followed by a function +# prototype or function definition. +sp_before_byref_func = ignore # ignore/add/remove/force + +# Add or remove space between type and word. +# +# Default: force +sp_after_type = force # ignore/add/remove/force + +# Add or remove space between 'decltype(...)' and word. +sp_after_decltype = ignore # ignore/add/remove/force + +# (D) Add or remove space before the parenthesis in the D constructs +# 'template Foo(' and 'class Foo('. +sp_before_template_paren = ignore # ignore/add/remove/force + +# Add or remove space between 'template' and '<'. +# If set to ignore, sp_before_angle is used. +sp_template_angle = ignore # ignore/add/remove/force + +# Add or remove space before '<'. +sp_before_angle = ignore # ignore/add/remove/force + +# Add or remove space inside '<' and '>'. +sp_inside_angle = ignore # ignore/add/remove/force + +# Add or remove space inside '<>'. +sp_inside_angle_empty = add # ignore/add/remove/force + +# Add or remove space between '>' and ':'. +sp_angle_colon = ignore # ignore/add/remove/force + +# Add or remove space after '>'. +sp_after_angle = ignore # ignore/add/remove/force + +# Add or remove space between '>' and '(' as found in 'new List(foo);'. +sp_angle_paren = remove # ignore/add/remove/force + +# Add or remove space between '>' and '()' as found in 'new List();'. +sp_angle_paren_empty = remove # ignore/add/remove/force + +# Add or remove space between '>' and a word as in 'List m;' or +# 'template static ...'. +sp_angle_word = add # ignore/add/remove/force + +# Add or remove space between '>' and '>' in '>>' (template stuff). +# +# Default: add +sp_angle_shift = add # ignore/add/remove/force + +# (C++11) Permit removal of the space between '>>' in 'foo >'. Note +# that sp_angle_shift cannot remove the space without this option. +sp_permit_cpp11_shift = false # true/false + +# Add or remove space before '(' of control statements ('if', 'for', 'switch', +# 'while', etc.). +sp_before_sparen = add # ignore/add/remove/force + +# Add or remove space inside '(' and ')' of control statements. +sp_inside_sparen = ignore # ignore/add/remove/force + +# Add or remove space after '(' of control statements. +# +# Overrides sp_inside_sparen. +sp_inside_sparen_open = ignore # ignore/add/remove/force + +# Add or remove space before ')' of control statements. +# +# Overrides sp_inside_sparen. +sp_inside_sparen_close = ignore # ignore/add/remove/force + +# Add or remove space after ')' of control statements. +sp_after_sparen = ignore # ignore/add/remove/force + +# Add or remove space between ')' and '{' of of control statements. +sp_sparen_brace = add # ignore/add/remove/force + +# (D) Add or remove space between 'invariant' and '('. +sp_invariant_paren = ignore # ignore/add/remove/force + +# (D) Add or remove space after the ')' in 'invariant (C) c'. +sp_after_invariant_paren = ignore # ignore/add/remove/force + +# Add or remove space before empty statement ';' on 'if', 'for' and 'while'. +sp_special_semi = add # ignore/add/remove/force + +# Add or remove space before ';'. +# +# Default: remove +sp_before_semi = remove # ignore/add/remove/force + +# Add or remove space before ';' in non-empty 'for' statements. +sp_before_semi_for = remove # ignore/add/remove/force + +# Add or remove space before a semicolon of an empty part of a for statement. +sp_before_semi_for_empty = add # ignore/add/remove/force + +# Add or remove space after ';', except when followed by a comment. +# +# Default: add +sp_after_semi = add # ignore/add/remove/force + +# Add or remove space after ';' in non-empty 'for' statements. +# +# Default: force +sp_after_semi_for = force # ignore/add/remove/force + +# Add or remove space after the final semicolon of an empty part of a for +# statement, as in 'for ( ; ; )'. +sp_after_semi_for_empty = ignore # ignore/add/remove/force + +# Add or remove space before '[' (except '[]'). +sp_before_square = ignore # ignore/add/remove/force + +# Add or remove space before '[' for a variable definition. +# +# Default: remove +#sp_before_vardef_square = remove # ignore/add/remove/force ### not 0.69 + +# Add or remove space before '[' for asm block. +#sp_before_square_asm_block = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove space before '[]'. +sp_before_squares = ignore # ignore/add/remove/force + +# Add or remove space before C++17 structured bindings. +sp_cpp_before_struct_binding = ignore # ignore/add/remove/force + +# Add or remove space inside a non-empty '[' and ']'. +sp_inside_square = ignore # ignore/add/remove/force + +# (OC) Add or remove space inside a non-empty Objective-C boxed array '@[' and +# ']'. If set to ignore, sp_inside_square is used. +sp_inside_square_oc_array = ignore # ignore/add/remove/force + +# Add or remove space after ',', i.e. 'a,b' vs. 'a, b'. +sp_after_comma = add # ignore/add/remove/force + +# Add or remove space before ','. +# +# Default: remove +sp_before_comma = remove # ignore/add/remove/force + +# (C#) Add or remove space between ',' and ']' in multidimensional array type +# like 'int[,,]'. +sp_after_mdatype_commas = ignore # ignore/add/remove/force + +# (C#) Add or remove space between '[' and ',' in multidimensional array type +# like 'int[,,]'. +sp_before_mdatype_commas = ignore # ignore/add/remove/force + +# (C#) Add or remove space between ',' in multidimensional array type +# like 'int[,,]'. +sp_between_mdatype_commas = ignore # ignore/add/remove/force + +# Add or remove space between an open parenthesis and comma, +# i.e. '(,' vs. '( ,'. +# +# Default: force +sp_paren_comma = force # ignore/add/remove/force + +# Add or remove space before the variadic '...' when preceded by a +# non-punctuator. +sp_before_ellipsis = ignore # ignore/add/remove/force + +# Add or remove space between a type and '...'. +sp_type_ellipsis = ignore # ignore/add/remove/force + +# (D) Add or remove space between a type and '?'. +sp_type_question = ignore # ignore/add/remove/force + +# Add or remove space between ')' and '...'. +sp_paren_ellipsis = ignore # ignore/add/remove/force + +# Add or remove space between ')' and a qualifier such as 'const'. +sp_paren_qualifier = ignore # ignore/add/remove/force + +# Add or remove space between ')' and 'noexcept'. +sp_paren_noexcept = ignore # ignore/add/remove/force + +# Add or remove space after class ':'. +sp_after_class_colon = ignore # ignore/add/remove/force + +# Add or remove space before class ':'. +sp_before_class_colon = ignore # ignore/add/remove/force + +# Add or remove space after class constructor ':'. +sp_after_constr_colon = ignore # ignore/add/remove/force + +# Add or remove space before class constructor ':'. +sp_before_constr_colon = ignore # ignore/add/remove/force + +# Add or remove space before case ':'. +# +# Default: remove +sp_before_case_colon = remove # ignore/add/remove/force + +# Add or remove space between 'operator' and operator sign. +sp_after_operator = ignore # ignore/add/remove/force + +# Add or remove space between the operator symbol and the open parenthesis, as +# in 'operator ++('. +sp_after_operator_sym = ignore # ignore/add/remove/force + +# Overrides sp_after_operator_sym when the operator has no arguments, as in +# 'operator *()'. +sp_after_operator_sym_empty = ignore # ignore/add/remove/force + +# Add or remove space after C/D cast, i.e. 'cast(int)a' vs. 'cast(int) a' or +# '(int)a' vs. '(int) a'. +sp_after_cast = remove # ignore/add/remove/force + +# Add or remove spaces inside cast parentheses. +sp_inside_paren_cast = ignore # ignore/add/remove/force + +# Add or remove space between the type and open parenthesis in a C++ cast, +# i.e. 'int(exp)' vs. 'int (exp)'. +sp_cpp_cast_paren = remove # ignore/add/remove/force + +# Add or remove space between 'sizeof' and '('. +sp_sizeof_paren = remove # ignore/add/remove/force + +# Add or remove space between 'sizeof' and '...'. +sp_sizeof_ellipsis = add # ignore/add/remove/force + +# Add or remove space between 'sizeof...' and '('. +sp_sizeof_ellipsis_paren = add # ignore/add/remove/force + +# Add or remove space between 'decltype' and '('. +sp_decltype_paren = ignore # ignore/add/remove/force + +# (Pawn) Add or remove space after the tag keyword. +sp_after_tag = ignore # ignore/add/remove/force + +# Add or remove space inside enum '{' and '}'. +sp_inside_braces_enum = ignore # ignore/add/remove/force + +# Add or remove space inside struct/union '{' and '}'. +sp_inside_braces_struct = ignore # ignore/add/remove/force + +# (OC) Add or remove space inside Objective-C boxed dictionary '{' and '}' +sp_inside_braces_oc_dict = ignore # ignore/add/remove/force + +# Add or remove space after open brace in an unnamed temporary +# direct-list-initialization. +sp_after_type_brace_init_lst_open = ignore # ignore/add/remove/force + +# Add or remove space before close brace in an unnamed temporary +# direct-list-initialization. +sp_before_type_brace_init_lst_close = ignore # ignore/add/remove/force + +# Add or remove space inside an unnamed temporary direct-list-initialization. +sp_inside_type_brace_init_lst = ignore # ignore/add/remove/force + +# Add or remove space inside '{' and '}'. +sp_inside_braces = ignore # ignore/add/remove/force + +# Add or remove space inside '{}'. +sp_inside_braces_empty = ignore # ignore/add/remove/force + +# Add or remove space around trailing return operator '->'. +#sp_trailing_return = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove space between return type and function name. A minimum of 1 +# is forced except for pointer return types. +sp_type_func = ignore # ignore/add/remove/force + +# Add or remove space between type and open brace of an unnamed temporary +# direct-list-initialization. +sp_type_brace_init_lst = ignore # ignore/add/remove/force + +# Add or remove space between function name and '(' on function declaration. +sp_func_proto_paren = remove # ignore/add/remove/force + +# Add or remove space between function name and '()' on function declaration +# without parameters. +sp_func_proto_paren_empty = remove # ignore/add/remove/force + +# Add or remove space between function name and '(' with a typedef specifier. +#sp_func_type_paren = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove space between alias name and '(' of a non-pointer function type typedef. +sp_func_def_paren = ignore # ignore/add/remove/force + +# Add or remove space between function name and '()' on function definition +# without parameters. +sp_func_def_paren_empty = remove # ignore/add/remove/force + +# Add or remove space inside empty function '()'. +# Overrides sp_after_angle unless use_sp_after_angle_always is set to true. +sp_inside_fparens = ignore # ignore/add/remove/force + +# Add or remove space inside function '(' and ')'. +sp_inside_fparen = ignore # ignore/add/remove/force + +# Add or remove space inside the first parentheses in a function type, as in +# 'void (*x)(...)'. +sp_inside_tparen = ignore # ignore/add/remove/force + +# Add or remove space between the ')' and '(' in a function type, as in +# 'void (*x)(...)'. +sp_after_tparen_close = ignore # ignore/add/remove/force + +# Add or remove space between ']' and '(' when part of a function call. +sp_square_fparen = add # ignore/add/remove/force + +# Add or remove space between ')' and '{' of function. +sp_fparen_brace = add # ignore/add/remove/force + +# Add or remove space between ')' and '{' of s function call in object +# initialization. +# +# Overrides sp_fparen_brace. +sp_fparen_brace_initializer = ignore # ignore/add/remove/force + +# (Java) Add or remove space between ')' and '{{' of double brace initializer. +sp_fparen_dbrace = ignore # ignore/add/remove/force + +# Add or remove space between function name and '(' on function calls. +sp_func_call_paren = ignore # ignore/add/remove/force + +# Add or remove space between function name and '()' on function calls without +# parameters. If set to ignore (the default), sp_func_call_paren is used. +sp_func_call_paren_empty = ignore # ignore/add/remove/force + +# Add or remove space between the user function name and '(' on function +# calls. You need to set a keyword to be a user function in the config file, +# like: +# set func_call_user tr _ i18n +sp_func_call_user_paren = ignore # ignore/add/remove/force + +# Add or remove space inside user function '(' and ')'. +sp_func_call_user_inside_fparen = ignore # ignore/add/remove/force + +# Add or remove space between nested parentheses with user functions, +# i.e. '((' vs. '( ('. +sp_func_call_user_paren_paren = ignore # ignore/add/remove/force + +# Add or remove space between a constructor/destructor and the open +# parenthesis. +sp_func_class_paren = ignore # ignore/add/remove/force + +# Add or remove space between a constructor without parameters or destructor +# and '()'. +sp_func_class_paren_empty = ignore # ignore/add/remove/force + +# Add or remove space between 'return' and '('. +sp_return_paren = ignore # ignore/add/remove/force + +# Add or remove space between 'return' and '{'. +sp_return_brace = ignore # ignore/add/remove/force + +# Add or remove space between '__attribute__' and '('. +sp_attribute_paren = ignore # ignore/add/remove/force + +# Add or remove space between 'defined' and '(' in '#if defined (FOO)'. +sp_defined_paren = ignore # ignore/add/remove/force + +# Add or remove space between 'throw' and '(' in 'throw (something)'. +sp_throw_paren = ignore # ignore/add/remove/force + +# Add or remove space between 'throw' and anything other than '(' as in +# '@throw [...];'. +sp_after_throw = ignore # ignore/add/remove/force + +# Add or remove space between 'catch' and '(' in 'catch (something) { }'. +# If set to ignore, sp_before_sparen is used. +sp_catch_paren = ignore # ignore/add/remove/force + +# (OC) Add or remove space between '@catch' and '(' +# in '@catch (something) { }'. If set to ignore, sp_catch_paren is used. +sp_oc_catch_paren = ignore # ignore/add/remove/force + +# (OC) Add or remove space before Objective-C protocol list +# as in '@protocol Protocol' or '@interface MyClass : NSObject'. +#sp_before_oc_proto_list = ignore # ignore/add/remove/force ### not 0.69 + +# (OC) Add or remove space between class name and '(' +# in '@interface className(categoryName):BaseClass' +sp_oc_classname_paren = ignore # ignore/add/remove/force + +# (D) Add or remove space between 'version' and '(' +# in 'version (something) { }'. If set to ignore, sp_before_sparen is used. +sp_version_paren = ignore # ignore/add/remove/force + +# (D) Add or remove space between 'scope' and '(' +# in 'scope (something) { }'. If set to ignore, sp_before_sparen is used. +sp_scope_paren = ignore # ignore/add/remove/force + +# Add or remove space between 'super' and '(' in 'super (something)'. +# +# Default: remove +sp_super_paren = remove # ignore/add/remove/force + +# Add or remove space between 'this' and '(' in 'this (something)'. +# +# Default: remove +sp_this_paren = remove # ignore/add/remove/force + +# Add or remove space between a macro name and its definition. +sp_macro = ignore # ignore/add/remove/force + +# Add or remove space between a macro function ')' and its definition. +sp_macro_func = ignore # ignore/add/remove/force + +# Add or remove space between 'else' and '{' if on the same line. +sp_else_brace = add # ignore/add/remove/force + +# Add or remove space between '}' and 'else' if on the same line. +sp_brace_else = add # ignore/add/remove/force + +# Add or remove space between '}' and the name of a typedef on the same line. +sp_brace_typedef = add # ignore/add/remove/force + +# Add or remove space before the '{' of a 'catch' statement, if the '{' and +# 'catch' are on the same line, as in 'catch (decl) {'. +sp_catch_brace = add # ignore/add/remove/force + +# (OC) Add or remove space before the '{' of a '@catch' statement, if the '{' +# and '@catch' are on the same line, as in '@catch (decl) {'. +# If set to ignore, sp_catch_brace is used. +sp_oc_catch_brace = ignore # ignore/add/remove/force + +# Add or remove space between '}' and 'catch' if on the same line. +sp_brace_catch = add # ignore/add/remove/force + +# (OC) Add or remove space between '}' and '@catch' if on the same line. +# If set to ignore, sp_brace_catch is used. +sp_oc_brace_catch = ignore # ignore/add/remove/force + +# Add or remove space between 'finally' and '{' if on the same line. +sp_finally_brace = add # ignore/add/remove/force + +# Add or remove space between '}' and 'finally' if on the same line. +sp_brace_finally = add # ignore/add/remove/force + +# Add or remove space between 'try' and '{' if on the same line. +sp_try_brace = add # ignore/add/remove/force + +# Add or remove space between get/set and '{' if on the same line. +sp_getset_brace = add # ignore/add/remove/force + +# Add or remove space between a variable and '{' for C++ uniform +# initialization. +#sp_word_brace_init_lst = add # ignore/add/remove/force ### not 0.69 + +# Add or remove space between a variable and '{' for a namespace. +# +# Default: add +sp_word_brace_ns = add # ignore/add/remove/force + +# Add or remove space before the '::' operator. +sp_before_dc = ignore # ignore/add/remove/force + +# Add or remove space after the '::' operator. +sp_after_dc = ignore # ignore/add/remove/force + +# (D) Add or remove around the D named array initializer ':' operator. +sp_d_array_colon = ignore # ignore/add/remove/force + +# Add or remove space after the '!' (not) unary operator. +# +# Default: remove +sp_not = remove # ignore/add/remove/force + +# Add or remove space after the '~' (invert) unary operator. +# +# Default: remove +sp_inv = remove # ignore/add/remove/force + +# Add or remove space after the '&' (address-of) unary operator. This does not +# affect the spacing after a '&' that is part of a type. +# +# Default: remove +sp_addr = remove # ignore/add/remove/force + +# Add or remove space around the '.' or '->' operators. +# +# Default: remove +sp_member = remove # ignore/add/remove/force + +# Add or remove space after the '*' (dereference) unary operator. This does +# not affect the spacing after a '*' that is part of a type. +# +# Default: remove +sp_deref = remove # ignore/add/remove/force + +# Add or remove space after '+' or '-', as in 'x = -5' or 'y = +7'. +# +# Default: remove +sp_sign = remove # ignore/add/remove/force + +# Add or remove space between '++' and '--' the word to which it is being +# applied, as in '(--x)' or 'y++;'. +# +# Default: remove +sp_incdec = remove # ignore/add/remove/force + +# Add or remove space before a backslash-newline at the end of a line. +# +# Default: add +sp_before_nl_cont = add # ignore/add/remove/force + +# (OC) Add or remove space after the scope '+' or '-', as in '-(void) foo;' +# or '+(int) bar;'. +sp_after_oc_scope = ignore # ignore/add/remove/force + +# (OC) Add or remove space after the colon in message specs, +# i.e. '-(int) f:(int) x;' vs. '-(int) f: (int) x;'. +sp_after_oc_colon = ignore # ignore/add/remove/force + +# (OC) Add or remove space before the colon in message specs, +# i.e. '-(int) f: (int) x;' vs. '-(int) f : (int) x;'. +sp_before_oc_colon = ignore # ignore/add/remove/force + +# (OC) Add or remove space after the colon in immutable dictionary expression +# 'NSDictionary *test = @{@"foo" :@"bar"};'. +sp_after_oc_dict_colon = ignore # ignore/add/remove/force + +# (OC) Add or remove space before the colon in immutable dictionary expression +# 'NSDictionary *test = @{@"foo" :@"bar"};'. +sp_before_oc_dict_colon = ignore # ignore/add/remove/force + +# (OC) Add or remove space after the colon in message specs, +# i.e. '[object setValue:1];' vs. '[object setValue: 1];'. +sp_after_send_oc_colon = ignore # ignore/add/remove/force + +# (OC) Add or remove space before the colon in message specs, +# i.e. '[object setValue:1];' vs. '[object setValue :1];'. +sp_before_send_oc_colon = ignore # ignore/add/remove/force + +# (OC) Add or remove space after the (type) in message specs, +# i.e. '-(int)f: (int) x;' vs. '-(int)f: (int)x;'. +sp_after_oc_type = ignore # ignore/add/remove/force + +# (OC) Add or remove space after the first (type) in message specs, +# i.e. '-(int) f:(int)x;' vs. '-(int)f:(int)x;'. +sp_after_oc_return_type = ignore # ignore/add/remove/force + +# (OC) Add or remove space between '@selector' and '(', +# i.e. '@selector(msgName)' vs. '@selector (msgName)'. +# Also applies to '@protocol()' constructs. +sp_after_oc_at_sel = ignore # ignore/add/remove/force + +# (OC) Add or remove space between '@selector(x)' and the following word, +# i.e. '@selector(foo) a:' vs. '@selector(foo)a:'. +sp_after_oc_at_sel_parens = ignore # ignore/add/remove/force + +# (OC) Add or remove space inside '@selector' parentheses, +# i.e. '@selector(foo)' vs. '@selector( foo )'. +# Also applies to '@protocol()' constructs. +sp_inside_oc_at_sel_parens = ignore # ignore/add/remove/force + +# (OC) Add or remove space before a block pointer caret, +# i.e. '^int (int arg){...}' vs. ' ^int (int arg){...}'. +sp_before_oc_block_caret = ignore # ignore/add/remove/force + +# (OC) Add or remove space after a block pointer caret, +# i.e. '^int (int arg){...}' vs. '^ int (int arg){...}'. +sp_after_oc_block_caret = ignore # ignore/add/remove/force + +# (OC) Add or remove space between the receiver and selector in a message, +# as in '[receiver selector ...]'. +sp_after_oc_msg_receiver = ignore # ignore/add/remove/force + +# (OC) Add or remove space after '@property'. +sp_after_oc_property = ignore # ignore/add/remove/force + +# (OC) Add or remove space between '@synchronized' and the open parenthesis, +# i.e. '@synchronized(foo)' vs. '@synchronized (foo)'. +sp_after_oc_synchronized = ignore # ignore/add/remove/force + +# Add or remove space around the ':' in 'b ? t : f'. +sp_cond_colon = add # ignore/add/remove/force + +# Add or remove space before the ':' in 'b ? t : f'. +# +# Overrides sp_cond_colon. +sp_cond_colon_before = ignore # ignore/add/remove/force + +# Add or remove space after the ':' in 'b ? t : f'. +# +# Overrides sp_cond_colon. +sp_cond_colon_after = ignore # ignore/add/remove/force + +# Add or remove space around the '?' in 'b ? t : f'. +sp_cond_question = add # ignore/add/remove/force + +# Add or remove space before the '?' in 'b ? t : f'. +# +# Overrides sp_cond_question. +sp_cond_question_before = ignore # ignore/add/remove/force + +# Add or remove space after the '?' in 'b ? t : f'. +# +# Overrides sp_cond_question. +sp_cond_question_after = ignore # ignore/add/remove/force + +# In the abbreviated ternary form '(a ?: b)', add or remove space between '?' +# and ':'. +# +# Overrides all other sp_cond_* options. +sp_cond_ternary_short = ignore # ignore/add/remove/force + +# Fix the spacing between 'case' and the label. Only 'ignore' and 'force' make +# sense here. +sp_case_label = ignore # ignore/add/remove/force + +# (D) Add or remove space around the D '..' operator. +sp_range = ignore # ignore/add/remove/force + +# Add or remove space after ':' in a Java/C++11 range-based 'for', +# as in 'for (Type var : expr)'. +sp_after_for_colon = ignore # ignore/add/remove/force + +# Add or remove space before ':' in a Java/C++11 range-based 'for', +# as in 'for (Type var : expr)'. +sp_before_for_colon = ignore # ignore/add/remove/force + +# (D) Add or remove space between 'extern' and '(' as in 'extern (C)'. +sp_extern_paren = ignore # ignore/add/remove/force + +# Add or remove space after the opening of a C++ comment, +# i.e. '// A' vs. '//A'. +sp_cmt_cpp_start = add # ignore/add/remove/force + +# If true, space is added with sp_cmt_cpp_start will be added after doxygen +# sequences like '///', '///<', '//!' and '//!<'. +sp_cmt_cpp_doxygen = false # true/false + +# If true, space is added with sp_cmt_cpp_start will be added after Qt +# translator or meta-data comments like '//:', '//=', and '//~'. +sp_cmt_cpp_qttr = false # true/false + +# Add or remove space between #else or #endif and a trailing comment. +sp_endif_cmt = add # ignore/add/remove/force + +# Add or remove space after 'new', 'delete' and 'delete[]'. +sp_after_new = ignore # ignore/add/remove/force + +# Add or remove space between 'new' and '(' in 'new()'. +sp_between_new_paren = ignore # ignore/add/remove/force + +# Add or remove space between ')' and type in 'new(foo) BAR'. +sp_after_newop_paren = ignore # ignore/add/remove/force + +# Add or remove space inside parenthesis of the new operator +# as in 'new(foo) BAR'. +sp_inside_newop_paren = ignore # ignore/add/remove/force + +# Add or remove space after the open parenthesis of the new operator, +# as in 'new(foo) BAR'. +# +# Overrides sp_inside_newop_paren. +sp_inside_newop_paren_open = ignore # ignore/add/remove/force + +# Add or remove space before the close parenthesis of the new operator, +# as in 'new(foo) BAR'. +# +# Overrides sp_inside_newop_paren. +sp_inside_newop_paren_close = ignore # ignore/add/remove/force + +# Add or remove space before a trailing or embedded comment. +sp_before_tr_emb_cmt = ignore # ignore/add/remove/force + +# Number of spaces before a trailing or embedded comment. +sp_num_before_tr_emb_cmt = 0 # unsigned number + +# (Java) Add or remove space between an annotation and the open parenthesis. +sp_annotation_paren = ignore # ignore/add/remove/force + +# If true, vbrace tokens are dropped to the previous token and skipped. +sp_skip_vbrace_tokens = false # true/false + +# Add or remove space after 'noexcept'. +sp_after_noexcept = ignore # ignore/add/remove/force + +# Add or remove space after '_'. +sp_vala_after_translation = ignore # ignore/add/remove/force + +# If true, a is inserted after #define. +force_tab_after_define = false # true/false + +# +# Indenting options +# + +# The number of columns to indent per level. Usually 2, 3, 4, or 8. +# +# Default: 8 +indent_columns = 4 # unsigned number + +# The continuation indent. If non-zero, this overrides the indent of '(', '[' +# and '=' continuation indents. Negative values are OK; negative value is +# absolute and not increased for each '(' or '[' level. +# +# For FreeBSD, this is set to 4. +indent_continue = 0 # number + +# The continuation indent, only for class header line(s). If non-zero, this +# overrides the indent of 'class' continuation indents. +indent_continue_class_head = 0 # unsigned number + +# Whether to indent empty lines (i.e. lines which contain only spaces before +# the newline character). +indent_single_newlines = false # true/false + +# The continuation indent for func_*_param if they are true. If non-zero, this +# overrides the indent. +indent_param = 0 # unsigned number + +# How to use tabs when indenting code. +# +# 0: Spaces only +# 1: Indent with tabs to brace level, align with spaces (default) +# 2: Indent and align with tabs, using spaces when not on a tabstop +# +# Default: 1 +indent_with_tabs = 0 # unsigned number + +# Whether to indent comments that are not at a brace level with tabs on a +# tabstop. Requires indent_with_tabs=2. If false, will use spaces. +indent_cmt_with_tabs = false # true/false + +# Whether to indent strings broken by '\' so that they line up. +indent_align_string = false # true/false + +# The number of spaces to indent multi-line XML strings. +# Requires indent_align_string=true. +indent_xml_string = 0 # unsigned number + +# Spaces to indent '{' from level. +indent_brace = 0 # unsigned number + +# Whether braces are indented to the body level. +indent_braces = false # true/false + +# Whether to disable indenting function braces if indent_braces=true. +indent_braces_no_func = false # true/false + +# Whether to disable indenting class braces if indent_braces=true. +indent_braces_no_class = false # true/false + +# Whether to disable indenting struct braces if indent_braces=true. +indent_braces_no_struct = false # true/false + +# Whether to indent based on the size of the brace parent, +# i.e. 'if' => 3 spaces, 'for' => 4 spaces, etc. +indent_brace_parent = false # true/false + +# Whether to indent based on the open parenthesis instead of the open brace +# in '({\n'. +indent_paren_open_brace = false # true/false + +# (C#) Whether to indent the brace of a C# delegate by another level. +indent_cs_delegate_brace = false # true/false + +# (C#) Whether to indent a C# delegate (to handle delegates with no brace) by +# another level. +indent_cs_delegate_body = false # true/false + +# Whether to indent the body of a 'namespace'. +indent_namespace = false # true/false + +# Whether to indent only the first namespace, and not any nested namespaces. +# Requires indent_namespace=true. +indent_namespace_single_indent = false # true/false + +# The number of spaces to indent a namespace block. +# If set to zero, use the value indent_columns +indent_namespace_level = 0 # unsigned number + +# If the body of the namespace is longer than this number, it won't be +# indented. Requires indent_namespace=true. 0 means no limit. +indent_namespace_limit = 0 # unsigned number + +# Whether the 'extern "C"' body is indented. +indent_extern = false # true/false + +# Whether the 'class' body is indented. +indent_class = false # true/false + +# Whether to indent the stuff after a leading base class colon. +indent_class_colon = false # true/false + +# Whether to indent based on a class colon instead of the stuff after the +# colon. Requires indent_class_colon=true. +indent_class_on_colon = false # true/false + +# Whether to indent the stuff after a leading class initializer colon. +indent_constr_colon = false # true/false + +# Virtual indent from the ':' for member initializers. +# +# Default: 2 +indent_ctor_init_leading = 2 # unsigned number + +# Additional indent for constructor initializer list. +# Negative values decrease indent down to the first column. +indent_ctor_init = 0 # number + +# Whether to indent 'if' following 'else' as a new block under the 'else'. +# If false, 'else\nif' is treated as 'else if' for indenting purposes. +indent_else_if = false # true/false + +# Amount to indent variable declarations after a open brace. +# +# <0: Relative +# >=0: Absolute +indent_var_def_blk = 0 # number + +# Whether to indent continued variable declarations instead of aligning. +indent_var_def_cont = false # true/false + +# Whether to indent continued shift expressions ('<<' and '>>') instead of +# aligning. Set align_left_shift=false when enabling this. +indent_shift = false # true/false + +# Whether to force indentation of function definitions to start in column 1. +indent_func_def_force_col1 = false # true/false + +# Whether to indent continued function call parameters one indent level, +# rather than aligning parameters under the open parenthesis. +indent_func_call_param = false # true/false + +# Whether to indent continued function definition parameters one indent level, +# rather than aligning parameters under the open parenthesis. +indent_func_def_param = false # true/false + +# for function definitions, only if indent_func_def_param is false +# Allows to align params when appropriate and indent them when not +# behave as if it was true if paren position is more than this value +# if paren position is more than the option value +#indent_func_def_param_paren_pos_threshold = 0 # unsigned number ### not 0.69 + +# Whether to indent continued function call prototype one indent level, +# rather than aligning parameters under the open parenthesis. +indent_func_proto_param = false # true/false + +# Whether to indent continued function call declaration one indent level, +# rather than aligning parameters under the open parenthesis. +indent_func_class_param = false # true/false + +# Whether to indent continued class variable constructors one indent level, +# rather than aligning parameters under the open parenthesis. +indent_func_ctor_var_param = false # true/false + +# Whether to indent continued template parameter list one indent level, +# rather than aligning parameters under the open parenthesis. +indent_template_param = false # true/false + +# Double the indent for indent_func_xxx_param options. +# Use both values of the options indent_columns and indent_param. +indent_func_param_double = false # true/false + +# Indentation column for standalone 'const' qualifier on a function +# prototype. +indent_func_const = 0 # unsigned number + +# Indentation column for standalone 'throw' qualifier on a function +# prototype. +indent_func_throw = 0 # unsigned number + +# How to indent within a macro followed by a brace on the same line +# This allows reducing the indent in macros that have (for example) +# `do { ... } while (0)` blocks bracketing them. +# +# true: add an indent for the brace on the same line as the macro +# false: do not add an indent for the brace on the same line as the macro +# +# Default: true +#indent_macro_brace = true # true/false ### not 0.69 + +# The number of spaces to indent a continued '->' or '.'. +# Usually set to 0, 1, or indent_columns. +indent_member = 0 # unsigned number + +# Whether lines broken at '.' or '->' should be indented by a single indent. +# The indent_member option will not be effective if this is set to true. +indent_member_single = false # true/false + +# Spaces to indent single line ('//') comments on lines before code. +indent_sing_line_comments = 0 # unsigned number + +# When opening a paren for a control statement (if, for, while, etc), increase +# the indent level by this value. Negative values decrease the indent level. +#indent_sparen_extra = 0 # number ### not 0.69 + +# Whether to indent trailing single line ('//') comments relative to the code +# instead of trying to keep the same absolute column. +indent_relative_single_line_comments = false # true/false + +# Spaces to indent 'case' from 'switch'. Usually 0 or indent_columns. +indent_switch_case = 0 # unsigned number + +# indent 'break' with 'case' from 'switch'. +#indent_switch_break_with_case = false # true/false ### not 0.69 + +# Whether to indent preprocessor statements inside of switch statements. +# +# Default: true +indent_switch_pp = true # true/false + +# Spaces to shift the 'case' line, without affecting any other lines. +# Usually 0. +indent_case_shift = 0 # unsigned number + +# Spaces to indent '{' from 'case'. By default, the brace will appear under +# the 'c' in case. Usually set to 0 or indent_columns. Negative values are OK. +indent_case_brace = 0 # number + +# Whether to indent comments found in first column. +indent_col1_comment = false # true/false + +# Whether to indent multi string literal in first column. +indent_col1_multi_string_literal = false # true/false + +# How to indent goto labels. +# +# >0: Absolute column where 1 is the leftmost column +# <=0: Subtract from brace indent +# +# Default: 1 +indent_label = 1 # number + +# How to indent access specifiers that are followed by a +# colon. +# +# >0: Absolute column where 1 is the leftmost column +# <=0: Subtract from brace indent +# +# Default: 1 +indent_access_spec = 1 # number + +# Whether to indent the code after an access specifier by one level. +# If true, this option forces 'indent_access_spec=0'. +indent_access_spec_body = false # true/false + +# If an open parenthesis is followed by a newline, whether to indent the next +# line so that it lines up after the open parenthesis (not recommended). +indent_paren_nl = false # true/false + +# How to indent a close parenthesis after a newline. +# +# 0: Indent to body level (default) +# 1: Align under the open parenthesis +# 2: Indent to the brace level +indent_paren_close = 0 # unsigned number + +# Whether to indent the open parenthesis of a function definition, +# if the parenthesis is on its own line. +indent_paren_after_func_def = false # true/false + +# Whether to indent the open parenthesis of a function declaration, +# if the parenthesis is on its own line. +indent_paren_after_func_decl = false # true/false + +# Whether to indent the open parenthesis of a function call, +# if the parenthesis is on its own line. +indent_paren_after_func_call = false # true/false + +# Whether to indent a comma when inside a parenthesis. +# If true, aligns under the open parenthesis. +indent_comma_paren = false # true/false + +# Whether to indent a Boolean operator when inside a parenthesis. +# If true, aligns under the open parenthesis. +indent_bool_paren = false # true/false + +# Whether to indent a semicolon when inside a for parenthesis. +# If true, aligns under the open for parenthesis. +indent_semicolon_for_paren = false # true/false + +# Whether to align the first expression to following ones +# if indent_bool_paren=true. +indent_first_bool_expr = false # true/false + +# Whether to align the first expression to following ones +# if indent_semicolon_for_paren=true. +indent_first_for_expr = false # true/false + +# If an open square is followed by a newline, whether to indent the next line +# so that it lines up after the open square (not recommended). +indent_square_nl = false # true/false + +# (ESQL/C) Whether to preserve the relative indent of 'EXEC SQL' bodies. +indent_preserve_sql = false # true/false + +# Whether to align continued statements at the '='. If false or if the '=' is +# followed by a newline, the next line is indent one tab. +# +# Default: true +indent_align_assign = true # true/false + +# If true, the indentation of the chunks after a '=' sequence will be set at +# LHS token indentation column before '='. +#indent_off_after_assign = false # true/false ### not 0.69 + +# Whether to align continued statements at the '('. If false or the '(' is +# followed by a newline, the next line indent is one tab. +# +# Default: true +indent_align_paren = true # true/false + +# (OC) Whether to indent Objective-C code inside message selectors. +#indent_oc_inside_msg_sel = false # true/false ### not 0.69 + +# (OC) Whether to indent Objective-C blocks at brace level instead of usual +# rules. +indent_oc_block = false # true/false + +# (OC) Indent for Objective-C blocks in a message relative to the parameter +# name. +# +# =0: Use indent_oc_block rules +# >0: Use specified number of spaces to indent +indent_oc_block_msg = 0 # unsigned number + +# (OC) Minimum indent for subsequent parameters +indent_oc_msg_colon = 0 # unsigned number + +# (OC) Whether to prioritize aligning with initial colon (and stripping spaces +# from lines, if necessary). +# +# Default: true +indent_oc_msg_prioritize_first_colon = true # true/false + +# (OC) Whether to indent blocks the way that Xcode does by default +# (from the keyword if the parameter is on its own line; otherwise, from the +# previous indentation level). Requires indent_oc_block_msg=true. +indent_oc_block_msg_xcode_style = false # true/false + +# (OC) Whether to indent blocks from where the brace is, relative to a +# message keyword. Requires indent_oc_block_msg=true. +indent_oc_block_msg_from_keyword = false # true/false + +# (OC) Whether to indent blocks from where the brace is, relative to a message +# colon. Requires indent_oc_block_msg=true. +indent_oc_block_msg_from_colon = false # true/false + +# (OC) Whether to indent blocks from where the block caret is. +# Requires indent_oc_block_msg=true. +indent_oc_block_msg_from_caret = false # true/false + +# (OC) Whether to indent blocks from where the brace caret is. +# Requires indent_oc_block_msg=true. +indent_oc_block_msg_from_brace = false # true/false + +# When indenting after virtual brace open and newline add further spaces to +# reach this minimum indent. +indent_min_vbrace_open = 0 # unsigned number + +# Whether to add further spaces after regular indent to reach next tabstop +# when identing after virtual brace open and newline. +indent_vbrace_open_on_tabstop = false # true/false + +# How to indent after a brace followed by another token (not a newline). +# true: indent all contained lines to match the token +# false: indent all contained lines to match the brace +# +# Default: true +indent_token_after_brace = true # true/false + +# Whether to indent the body of a C++11 lambda. +indent_cpp_lambda_body = false # true/false + +# How to indent compound literals that are being returned. +# true: add both the indent from return & the compound literal open brace (ie: +# 2 indent levels) +# false: only indent 1 level, don't add the indent for the open brace, only add +# the indent for the return. +# +# Default: true +#indent_compound_literal_return = true # true/false ### not 0.69 + +# (C#) Whether to indent a 'using' block if no braces are used. +# +# Default: true +indent_using_block = true # true/false + +# How to indent the continuation of ternary operator. +# +# 0: Off (default) +# 1: When the `if_false` is a continuation, indent it under `if_false` +# 2: When the `:` is a continuation, indent it under `?` +indent_ternary_operator = 0 # unsigned number + +# Whether to indent the statments inside ternary operator. +#indent_inside_ternary_operator = false # true/false ### not 0.69 + +# If true, the indentation of the chunks after a `return` sequence will be set at return indentation column. +#indent_off_after_return = false # true/false ### not 0.69 + +# If true, the indentation of the chunks after a `return new` sequence will be set at return indentation column. +indent_off_after_return_new = false # true/false + +# If true, the tokens after return are indented with regular single indentation. By default (false) the indentation is after the return token. +indent_single_after_return = false # true/false + +# Whether to ignore indent and alignment for 'asm' blocks (i.e. assume they +# have their own indentation). +indent_ignore_asm_block = false # true/false + +# +# Newline adding and removing options +# + +# Whether to collapse empty blocks between '{' and '}'. +nl_collapse_empty_body = false # true/false + +# Don't split one-line braced assignments, as in 'foo_t f = { 1, 2 };'. +nl_assign_leave_one_liners = false # true/false + +# Don't split one-line braced statements inside a 'class xx { }' body. +nl_class_leave_one_liners = false # true/false + +# Don't split one-line enums, as in 'enum foo { BAR = 15 };' +nl_enum_leave_one_liners = false # true/false + +# Don't split one-line get or set functions. +nl_getset_leave_one_liners = false # true/false + +# (C#) Don't split one-line property get or set functions. +nl_cs_property_leave_one_liners = false # true/false + +# Don't split one-line function definitions, as in 'int foo() { return 0; }'. +# might modify nl_func_type_name +nl_func_leave_one_liners = false # true/false + +# Don't split one-line C++11 lambdas, as in '[]() { return 0; }'. +nl_cpp_lambda_leave_one_liners = false # true/false + +# Don't split one-line if/else statements, as in 'if(...) b++;'. +nl_if_leave_one_liners = false # true/false + +# Don't split one-line while statements, as in 'while(...) b++;'. +nl_while_leave_one_liners = false # true/false + +# Don't split one-line for statements, as in 'for(...) b++;'. +nl_for_leave_one_liners = false # true/false + +# (OC) Don't split one-line Objective-C messages. +nl_oc_msg_leave_one_liner = false # true/false + +# (OC) Add or remove newline between method declaration and '{'. +nl_oc_mdef_brace = ignore # ignore/add/remove/force + +# (OC) Add or remove newline between Objective-C block signature and '{'. +nl_oc_block_brace = ignore # ignore/add/remove/force + +# (OC) Add or remove blank line before '@interface' statement. +#nl_oc_before_interface = ignore # ignore/add/remove/force ### not 0.69 + +# (OC) Add or remove blank line before '@implementation' statement. +#nl_oc_before_implementation = ignore # ignore/add/remove/force ### not 0.69 + +# (OC) Add or remove blank line before '@end' statement. +#nl_oc_before_end = ignore # ignore/add/remove/force ### not 0.69 + +# (OC) Add or remove newline between '@interface' and '{'. +nl_oc_interface_brace = ignore # ignore/add/remove/force + +# (OC) Add or remove newline between '@implementation' and '{'. +nl_oc_implementation_brace = ignore # ignore/add/remove/force + +# Add or remove newlines at the start of the file. +nl_start_of_file = remove # ignore/add/remove/force + +# The minimum number of newlines at the start of the file (only used if +# nl_start_of_file is 'add' or 'force'). +nl_start_of_file_min = 0 # unsigned number + +# Add or remove newline at the end of the file. +nl_end_of_file = ignore # ignore/add/remove/force + +# The minimum number of newlines at the end of the file (only used if +# nl_end_of_file is 'add' or 'force'). +nl_end_of_file_min = 0 # unsigned number + +# Add or remove newline between '=' and '{'. +nl_assign_brace = ignore # ignore/add/remove/force + +# (D) Add or remove newline between '=' and '['. +nl_assign_square = ignore # ignore/add/remove/force + +# Add or remove newline between '[]' and '{'. +nl_tsquare_brace = ignore # ignore/add/remove/force + +# (D) Add or remove newline after '= ['. Will also affect the newline before +# the ']'. +nl_after_square_assign = ignore # ignore/add/remove/force + +# Add or remove newline between a function call's ')' and '{', as in +# 'list_for_each(item, &list) { }'. +nl_fcall_brace = ignore # ignore/add/remove/force + +# Add or remove newline between 'enum' and '{'. +nl_enum_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'enum' and 'class'. +nl_enum_class = ignore # ignore/add/remove/force + +# Add or remove newline between 'enum class' and the identifier. +nl_enum_class_identifier = ignore # ignore/add/remove/force + +# Add or remove newline between 'enum class' type and ':'. +nl_enum_identifier_colon = ignore # ignore/add/remove/force + +# Add or remove newline between 'enum class identifier :' and type. +nl_enum_colon_type = ignore # ignore/add/remove/force + +# Add or remove newline between 'struct and '{'. +nl_struct_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'union' and '{'. +nl_union_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'if' and '{'. +nl_if_brace = remove # ignore/add/remove/force + +# Add or remove newline between '}' and 'else'. +nl_brace_else = remove # ignore/add/remove/force + +# Add or remove newline between 'else if' and '{'. If set to ignore, +# nl_if_brace is used instead. +nl_elseif_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'else' and '{'. +nl_else_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'else' and 'if'. +nl_else_if = remove # ignore/add/remove/force + +# Add or remove newline before '{' opening brace +#nl_before_opening_brace_func_class_def = remove # ignore/add/remove/force ### not 0.69 + +# Add or remove newline before 'if'/'else if' closing parenthesis. +nl_before_if_closing_paren = remove # ignore/add/remove/force + +# Add or remove newline between '}' and 'finally'. +nl_brace_finally = remove # ignore/add/remove/force + +# Add or remove newline between 'finally' and '{'. +nl_finally_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'try' and '{'. +nl_try_brace = remove # ignore/add/remove/force + +# Add or remove newline between get/set and '{'. +nl_getset_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'for' and '{'. +nl_for_brace = remove # ignore/add/remove/force + +# Add or remove newline before the '{' of a 'catch' statement, as in +# 'catch (decl) {'. +nl_catch_brace = remove # ignore/add/remove/force + +# (OC) Add or remove newline before the '{' of a '@catch' statement, as in +# '@catch (decl) {'. If set to ignore, nl_catch_brace is used. +nl_oc_catch_brace = ignore # ignore/add/remove/force + +# Add or remove newline between '}' and 'catch'. +nl_brace_catch = remove # ignore/add/remove/force + +# (OC) Add or remove newline between '}' and '@catch'. If set to ignore, +# nl_brace_catch is used. +nl_oc_brace_catch = ignore # ignore/add/remove/force + +# Add or remove newline between '}' and ']'. +nl_brace_square = ignore # ignore/add/remove/force + +# Add or remove newline between '}' and ')' in a function invocation. +nl_brace_fparen = ignore # ignore/add/remove/force + +# Add or remove newline between 'while' and '{'. +nl_while_brace = remove # ignore/add/remove/force + +# (D) Add or remove newline between 'scope (x)' and '{'. +nl_scope_brace = ignore # ignore/add/remove/force + +# (D) Add or remove newline between 'unittest' and '{'. +nl_unittest_brace = ignore # ignore/add/remove/force + +# (D) Add or remove newline between 'version (x)' and '{'. +nl_version_brace = ignore # ignore/add/remove/force + +# (C#) Add or remove newline between 'using' and '{'. +nl_using_brace = ignore # ignore/add/remove/force + +# Add or remove newline between two open or close braces. Due to general +# newline/brace handling, REMOVE may not work. +nl_brace_brace = add # ignore/add/remove/force + +# Add or remove newline between 'do' and '{'. +nl_do_brace = remove # ignore/add/remove/force + +# Add or remove newline between '}' and 'while' of 'do' statement. +nl_brace_while = remove # ignore/add/remove/force + +# Add or remove newline between 'switch' and '{'. +nl_switch_brace = remove # ignore/add/remove/force + +# Add or remove newline between 'synchronized' and '{'. +nl_synchronized_brace = remove # ignore/add/remove/force + +# Add a newline between ')' and '{' if the ')' is on a different line than the +# if/for/etc. +# +# Overrides nl_for_brace, nl_if_brace, nl_switch_brace, nl_while_switch and +# nl_catch_brace. +nl_multi_line_cond = false # true/false + +# Add a newline after '(' if an if/for/while/switch condition spans multiple +# lines +#nl_multi_line_sparen_open = ignore # ignore/add/remove/force ### not 0.69 + +# Add a newline before ')' if an if/for/while/switch condition spans multiple +# lines. Overrides nl_before_if_closing_paren if both are specified. +#nl_multi_line_sparen_close = ignore # ignore/add/remove/force ### not 0.69 + +# Force a newline in a define after the macro name for multi-line defines. +nl_multi_line_define = false # true/false + +# Whether to add a newline before 'case', and a blank line before a 'case' +# statement that follows a ';' or '}'. +nl_before_case = false # true/false + +# Whether to add a newline after a 'case' statement. +nl_after_case = false # true/false + +# Add or remove newline between a case ':' and '{'. +# +# Overrides nl_after_case. +nl_case_colon_brace = ignore # ignore/add/remove/force + +# Add or remove newline between ')' and 'throw'. +nl_before_throw = ignore # ignore/add/remove/force + +# Add or remove newline between 'namespace' and '{'. +nl_namespace_brace = ignore # ignore/add/remove/force + +# Add or remove newline after 'template<...>' of a template class. +nl_template_class = ignore # ignore/add/remove/force + +# Add or remove newline after 'template<...>' of a template class declaration. +# +# Overrides nl_template_class. +#nl_template_class_decl = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<>' of a specialized class declaration. +# +# Overrides nl_template_class_decl. +#nl_template_class_decl_special = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<...>' of a template class definition. +# +# Overrides nl_template_class. +#nl_template_class_def = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<>' of a specialized class definition. +# +# Overrides nl_template_class_def. +#nl_template_class_def_special = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<...>' of a template function. +#nl_template_func = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<...>' of a template function +# declaration. +# +# Overrides nl_template_func. +#nl_template_func_decl = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<>' of a specialized function +# declaration. +# +# Overrides nl_template_func_decl. +#nl_template_func_decl_special = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<...>' of a template function +# definition. +# +# Overrides nl_template_func. +#nl_template_func_def = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<>' of a specialized function +# definition. +# +# Overrides nl_template_func_def. +#nl_template_func_def_special = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline after 'template<...>' of a template variable. +#nl_template_var = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline between 'template<...>' and 'using' of a templated +# type alias. +#nl_template_using = ignore # ignore/add/remove/force ### not 0.69 + +# Add or remove newline between 'class' and '{'. +nl_class_brace = ignore # ignore/add/remove/force + +# Add or remove newline before or after (depending on pos_class_comma, +# may not be IGNORE) each',' in the base class list. +nl_class_init_args = ignore # ignore/add/remove/force + +# Add or remove newline after each ',' in the constructor member +# initialization. Related to nl_constr_colon, pos_constr_colon and +# pos_constr_comma. +nl_constr_init_args = ignore # ignore/add/remove/force + +# Add or remove newline before first element, after comma, and after last +# element, in 'enum'. +nl_enum_own_lines = ignore # ignore/add/remove/force + +# Add or remove newline between return type and function name in a function +# definition. +# might be modified by nl_func_leave_one_liners +nl_func_type_name = ignore # ignore/add/remove/force + +# Add or remove newline between return type and function name inside a class +# definition. If set to ignore, nl_func_type_name or nl_func_proto_type_name +# is used instead. +nl_func_type_name_class = ignore # ignore/add/remove/force + +# Add or remove newline between class specification and '::' +# in 'void A::f() { }'. Only appears in separate member implementation (does +# not appear with in-line implementation). +nl_func_class_scope = ignore # ignore/add/remove/force + +# Add or remove newline between function scope and name, as in +# 'void A :: f() { }'. +nl_func_scope_name = ignore # ignore/add/remove/force + +# Add or remove newline between return type and function name in a prototype. +nl_func_proto_type_name = ignore # ignore/add/remove/force + +# Add or remove newline between a function name and the opening '(' in the +# declaration. +nl_func_paren = remove # ignore/add/remove/force + +# Overrides nl_func_paren for functions with no parameters. +nl_func_paren_empty = ignore # ignore/add/remove/force + +# Add or remove newline between a function name and the opening '(' in the +# definition. +nl_func_def_paren = remove # ignore/add/remove/force + +# Overrides nl_func_def_paren for functions with no parameters. +nl_func_def_paren_empty = ignore # ignore/add/remove/force + +# Add or remove newline between a function name and the opening '(' in the +# call. +nl_func_call_paren = ignore # ignore/add/remove/force + +# Overrides nl_func_call_paren for functions with no parameters. +nl_func_call_paren_empty = ignore # ignore/add/remove/force + +# Add or remove newline after '(' in a function declaration. +nl_func_decl_start = remove # ignore/add/remove/force + +# Add or remove newline after '(' in a function definition. +nl_func_def_start = remove # ignore/add/remove/force + +# Overrides nl_func_decl_start when there is only one parameter. +nl_func_decl_start_single = ignore # ignore/add/remove/force + +# Overrides nl_func_def_start when there is only one parameter. +nl_func_def_start_single = ignore # ignore/add/remove/force + +# Whether to add a newline after '(' in a function declaration if '(' and ')' +# are in different lines. If false, nl_func_decl_start is used instead. +nl_func_decl_start_multi_line = false # true/false + +# Whether to add a newline after '(' in a function definition if '(' and ')' +# are in different lines. If false, nl_func_def_start is used instead. +nl_func_def_start_multi_line = false # true/false + +# Add or remove newline after each ',' in a function declaration. +nl_func_decl_args = ignore # ignore/add/remove/force + +# Add or remove newline after each ',' in a function definition. +nl_func_def_args = ignore # ignore/add/remove/force + +# Add or remove newline after each ',' in a function call. +#nl_func_call_args = ignore # ignore/add/remove/force ### not 0.69 + +# Whether to add a newline after each ',' in a function declaration if '(' +# and ')' are in different lines. If false, nl_func_decl_args is used instead. +nl_func_decl_args_multi_line = false # true/false + +# Whether to add a newline after each ',' in a function definition if '(' +# and ')' are in different lines. If false, nl_func_def_args is used instead. +nl_func_def_args_multi_line = false # true/false + +# Add or remove newline before the ')' in a function declaration. +nl_func_decl_end = remove # ignore/add/remove/force + +# Add or remove newline before the ')' in a function definition. +nl_func_def_end = remove # ignore/add/remove/force + +# Overrides nl_func_decl_end when there is only one parameter. +nl_func_decl_end_single = ignore # ignore/add/remove/force + +# Overrides nl_func_def_end when there is only one parameter. +nl_func_def_end_single = ignore # ignore/add/remove/force + +# Whether to add a newline before ')' in a function declaration if '(' and ')' +# are in different lines. If false, nl_func_decl_end is used instead. +nl_func_decl_end_multi_line = false # true/false + +# Whether to add a newline before ')' in a function definition if '(' and ')' +# are in different lines. If false, nl_func_def_end is used instead. +nl_func_def_end_multi_line = false # true/false + +# Add or remove newline between '()' in a function declaration. +nl_func_decl_empty = remove # ignore/add/remove/force + +# Add or remove newline between '()' in a function definition. +nl_func_def_empty = remove # ignore/add/remove/force + +# Add or remove newline between '()' in a function call. +nl_func_call_empty = remove # ignore/add/remove/force + +# Whether to add a newline after '(' in a function call, +# has preference over nl_func_call_start_multi_line. +nl_func_call_start = ignore # ignore/add/remove/force + +# Whether to add a newline before ')' in a function call. +#nl_func_call_end = ignore # ignore/add/remove/force ### not 0.69 + +# Whether to add a newline after '(' in a function call if '(' and ')' are in +# different lines. +nl_func_call_start_multi_line = false # true/false + +# Whether to add a newline after each ',' in a function call if '(' and ')' +# are in different lines. +nl_func_call_args_multi_line = false # true/false + +# Whether to add a newline before ')' in a function call if '(' and ')' are in +# different lines. +nl_func_call_end_multi_line = false # true/false + +# Whether to respect nl_func_call_XXX option incase of closure args. +#nl_func_call_args_multi_line_ignore_closures = false # true/false ### not 0.69 + +# Whether to add a newline after '<' of a template parameter list. +#nl_template_start = false # true/false ### not 0.69 + +# Whether to add a newline after each ',' in a template parameter list. +#nl_template_args = false # true/false ### not 0.69 + +# Whether to add a newline before '>' of a template parameter list. +#nl_template_end = false # true/false ### not 0.69 + +# (OC) Whether to put each Objective-C message parameter on a separate line. +# See nl_oc_msg_leave_one_liner. +nl_oc_msg_args = false # true/false + +# Add or remove newline between function signature and '{'. +nl_fdef_brace = ignore # ignore/add/remove/force + +# Add or remove newline between function signature and '{', +# if signature ends with ')'. Overrides nl_fdef_brace. +nl_fdef_brace_cond = ignore # ignore/add/remove/force + +# Add or remove newline between C++11 lambda signature and '{'. +nl_cpp_ldef_brace = ignore # ignore/add/remove/force + +# Add or remove newline between 'return' and the return expression. +nl_return_expr = ignore # ignore/add/remove/force + +# Whether to add a newline after semicolons, except in 'for' statements. +nl_after_semicolon = false # true/false + +# (Java) Add or remove newline between the ')' and '{{' of the double brace +# initializer. +nl_paren_dbrace_open = ignore # ignore/add/remove/force + +# Whether to add a newline after the type in an unnamed temporary +# direct-list-initialization. +nl_type_brace_init_lst = ignore # ignore/add/remove/force + +# Whether to add a newline after the open brace in an unnamed temporary +# direct-list-initialization. +nl_type_brace_init_lst_open = ignore # ignore/add/remove/force + +# Whether to add a newline before the close brace in an unnamed temporary +# direct-list-initialization. +nl_type_brace_init_lst_close = ignore # ignore/add/remove/force + +# Whether to add a newline after '{'. This also adds a newline before the +# matching '}'. +nl_after_brace_open = false # true/false + +# Whether to add a newline between the open brace and a trailing single-line +# comment. Requires nl_after_brace_open=true. +nl_after_brace_open_cmt = false # true/false + +# Whether to add a newline after a virtual brace open with a non-empty body. +# These occur in un-braced if/while/do/for statement bodies. +nl_after_vbrace_open = false # true/false + +# Whether to add a newline after a virtual brace open with an empty body. +# These occur in un-braced if/while/do/for statement bodies. +nl_after_vbrace_open_empty = false # true/false + +# Whether to add a newline after '}'. Does not apply if followed by a +# necessary ';'. +nl_after_brace_close = false # true/false + +# Whether to add a newline after a virtual brace close, +# as in 'if (foo) a++; return;'. +nl_after_vbrace_close = false # true/false + +# Add or remove newline between the close brace and identifier, +# as in 'struct { int a; } b;'. Affects enumerations, unions and +# structures. If set to ignore, uses nl_after_brace_close. +nl_brace_struct_var = ignore # ignore/add/remove/force + +# Whether to alter newlines in '#define' macros. +nl_define_macro = false # true/false + +# Whether to alter newlines between consecutive parenthesis closes. The number +# of closing parentheses in a line will depend on respective open parenthesis +# lines. +nl_squeeze_paren_close = false # true/false + +# Whether to remove blanks after '#ifxx' and '#elxx', or before '#elxx' and +# '#endif'. Does not affect top-level #ifdefs. +nl_squeeze_ifdef = false # true/false + +# Makes the nl_squeeze_ifdef option affect the top-level #ifdefs as well. +nl_squeeze_ifdef_top_level = false # true/false + +# Add or remove blank line before 'if'. +nl_before_if = add # ignore/add/remove/force + +# Add or remove blank line after 'if' statement. Add/Force work only if the +# next token is not a closing brace. +nl_after_if = add # ignore/add/remove/force + +# Add or remove blank line before 'for'. +nl_before_for = add # ignore/add/remove/force + +# Add or remove blank line after 'for' statement. +nl_after_for = add # ignore/add/remove/force + +# Add or remove blank line before 'while'. +nl_before_while = add # ignore/add/remove/force + +# Add or remove blank line after 'while' statement. +nl_after_while = add # ignore/add/remove/force + +# Add or remove blank line before 'switch'. +nl_before_switch = add # ignore/add/remove/force + +# Add or remove blank line after 'switch' statement. +nl_after_switch = add # ignore/add/remove/force + +# Add or remove blank line before 'synchronized'. +nl_before_synchronized = add # ignore/add/remove/force + +# Add or remove blank line after 'synchronized' statement. +nl_after_synchronized = add # ignore/add/remove/force + +# Add or remove blank line before 'do'. +nl_before_do = add # ignore/add/remove/force + +# Add or remove blank line after 'do/while' statement. +nl_after_do = add # ignore/add/remove/force + +# Whether to put a blank line before 'return' statements, unless after an open +# brace. +nl_before_return = false # true/false + +# Whether to put a blank line after 'return' statements, unless followed by a +# close brace. +nl_after_return = false # true/false + +# Whether to put a blank line before a member '.' or '->' operators. +#nl_before_member = ignore # ignore/add/remove/force ### not 0.69 + +# (Java) Whether to put a blank line after a member '.' or '->' operators. +#nl_after_member = ignore # ignore/add/remove/force ### not 0.69 + +# Whether to double-space commented-entries in 'struct'/'union'/'enum'. +nl_ds_struct_enum_cmt = false # true/false + +# Whether to force a newline before '}' of a 'struct'/'union'/'enum'. +# (Lower priority than eat_blanks_before_close_brace.) +nl_ds_struct_enum_close_brace = false # true/false + +# Add or remove newline before or after (depending on pos_class_colon) a class +# colon, as in 'class Foo : public Bar'. +nl_class_colon = ignore # ignore/add/remove/force + +# Add or remove newline around a class constructor colon. The exact position +# depends on nl_constr_init_args, pos_constr_colon and pos_constr_comma. +nl_constr_colon = ignore # ignore/add/remove/force + +# Whether to collapse a two-line namespace, like 'namespace foo\n{ decl; }' +# into a single line. If true, prevents other brace newline rules from turning +# such code into four lines. +nl_namespace_two_to_one_liner = false # true/false + +# Whether to remove a newline in simple unbraced if statements, turning them +# into one-liners, as in 'if(b)\n i++;' => 'if(b) i++;'. +nl_create_if_one_liner = false # true/false + +# Whether to remove a newline in simple unbraced for statements, turning them +# into one-liners, as in 'for (...)\n stmt;' => 'for (...) stmt;'. +nl_create_for_one_liner = false # true/false + +# Whether to remove a newline in simple unbraced while statements, turning +# them into one-liners, as in 'while (expr)\n stmt;' => 'while (expr) stmt;'. +nl_create_while_one_liner = false # true/false + +# Whether to collapse a function definition whose body (not counting braces) +# is only one line so that the entire definition (prototype, braces, body) is +# a single line. +nl_create_func_def_one_liner = false # true/false + +# Whether to collapse a function definition whose body (not counting braces) +# is only one line so that the entire definition (prototype, braces, body) is +# a single line. +#nl_create_list_one_liner = false # true/false ### not 0.69 + +# Whether to split one-line simple unbraced if statements into two lines by +# adding a newline, as in 'if(b) i++;'. +nl_split_if_one_liner = false # true/false + +# Whether to split one-line simple unbraced for statements into two lines by +# adding a newline, as in 'for (...) stmt;'. +nl_split_for_one_liner = false # true/false + +# Whether to split one-line simple unbraced while statements into two lines by +# adding a newline, as in 'while (expr) stmt;'. +nl_split_while_one_liner = false # true/false + +# +# Blank line options +# + +# The maximum number of consecutive newlines (3 = 2 blank lines). +nl_max = 0 # unsigned number + +# The maximum number of consecutive newlines in a function. +nl_max_blank_in_func = 0 # unsigned number + +# The number of newlines before a function prototype. +nl_before_func_body_proto = 0 # unsigned number + +# The number of newlines before a multi-line function definition. +nl_before_func_body_def = 0 # unsigned number + +# The number of newlines before a class constructor/destructor prototype. +nl_before_func_class_proto = 0 # unsigned number + +# The number of newlines before a class constructor/destructor definition. +nl_before_func_class_def = 0 # unsigned number + +# The number of newlines after a function prototype. +nl_after_func_proto = 0 # unsigned number + +# The number of newlines after a function prototype, if not followed by +# another function prototype. +nl_after_func_proto_group = 0 # unsigned number + +# The number of newlines after a class constructor/destructor prototype. +nl_after_func_class_proto = 0 # unsigned number + +# The number of newlines after a class constructor/destructor prototype, +# if not followed by another constructor/destructor prototype. +nl_after_func_class_proto_group = 0 # unsigned number + +# Whether one-line method definitions inside a class body should be treated +# as if they were prototypes for the purposes of adding newlines. +# +# Requires nl_class_leave_one_liners=true. Overrides nl_before_func_body_def +# and nl_before_func_class_def for one-liners. +nl_class_leave_one_liner_groups = false # true/false + +# The number of newlines after '}' of a multi-line function body. +nl_after_func_body = 0 # unsigned number + +# The number of newlines after '}' of a multi-line function body in a class +# declaration. Also affects class constructors/destructors. +# +# Overrides nl_after_func_body. +nl_after_func_body_class = 0 # unsigned number + +# The number of newlines after '}' of a single line function body. Also +# affects class constructors/destructors. +# +# Overrides nl_after_func_body and nl_after_func_body_class. +nl_after_func_body_one_liner = 0 # unsigned number + +# The number of blank lines after a block of variable definitions at the top +# of a function body. +# +# 0: No change (default). +nl_func_var_def_blk = 0 # unsigned number + +# The number of newlines before a block of typedefs. If nl_after_access_spec +# is non-zero, that option takes precedence. +# +# 0: No change (default). +nl_typedef_blk_start = 0 # unsigned number + +# The number of newlines after a block of typedefs. +# +# 0: No change (default). +nl_typedef_blk_end = 0 # unsigned number + +# The maximum number of consecutive newlines within a block of typedefs. +# +# 0: No change (default). +nl_typedef_blk_in = 0 # unsigned number + +# The number of newlines before a block of variable definitions not at the top +# of a function body. If nl_after_access_spec is non-zero, that option takes +# precedence. +# +# 0: No change (default). +nl_var_def_blk_start = 0 # unsigned number + +# The number of newlines after a block of variable definitions not at the top +# of a function body. +# +# 0: No change (default). +nl_var_def_blk_end = 0 # unsigned number + +# The maximum number of consecutive newlines within a block of variable +# definitions. +# +# 0: No change (default). +nl_var_def_blk_in = 0 # unsigned number + +# The minimum number of newlines before a multi-line comment. +# Doesn't apply if after a brace open or another multi-line comment. +nl_before_block_comment = 0 # unsigned number + +# The minimum number of newlines before a single-line C comment. +# Doesn't apply if after a brace open or other single-line C comments. +nl_before_c_comment = 0 # unsigned number + +# The minimum number of newlines before a CPP comment. +# Doesn't apply if after a brace open or other CPP comments. +nl_before_cpp_comment = 0 # unsigned number + +# Whether to force a newline after a multi-line comment. +nl_after_multiline_comment = false # true/false + +# Whether to force a newline after a label's colon. +nl_after_label_colon = false # true/false + +# The number of newlines after '}' or ';' of a struct/enum/union definition. +nl_after_struct = 0 # unsigned number + +# The number of newlines before a class definition. +nl_before_class = 0 # unsigned number + +# The number of newlines after '}' or ';' of a class definition. +nl_after_class = 0 # unsigned number + +# The number of newlines before a namespace. +#nl_before_namespace = 0 # unsigned number ### not 0.69 + +# The number of newlines after '{' of a namespace. This also adds newlines +# before the matching '}'. +# +# 0: Apply eat_blanks_after_open_brace or eat_blanks_before_close_brace if +# applicable, otherwise no change. +# +# Overrides eat_blanks_after_open_brace and eat_blanks_before_close_brace. +nl_inside_namespace = 0 # unsigned number + +# The number of newlines after '}' of a namespace. +#nl_after_namespace = 0 # unsigned number ### not 0.69 + +# The number of newlines before an access specifier label. This also includes +# the Qt-specific 'signals:' and 'slots:'. Will not change the newline count +# if after a brace open. +# +# 0: No change (default). +nl_before_access_spec = 0 # unsigned number + +# The number of newlines after an access specifier label. This also includes +# the Qt-specific 'signals:' and 'slots:'. Will not change the newline count +# if after a brace open. +# +# 0: No change (default). +# +# Overrides nl_typedef_blk_start and nl_var_def_blk_start. +nl_after_access_spec = 0 # unsigned number + +# The number of newlines between a function definition and the function +# comment, as in '// comment\n void foo() {...}'. +# +# 0: No change (default). +nl_comment_func_def = 0 # unsigned number + +# The number of newlines after a try-catch-finally block that isn't followed +# by a brace close. +# +# 0: No change (default). +nl_after_try_catch_finally = 0 # unsigned number + +# (C#) The number of newlines before and after a property, indexer or event +# declaration. +# +# 0: No change (default). +nl_around_cs_property = 0 # unsigned number + +# (C#) The number of newlines between the get/set/add/remove handlers. +# +# 0: No change (default). +nl_between_get_set = 0 # unsigned number + +# (C#) Add or remove newline between property and the '{'. +nl_property_brace = ignore # ignore/add/remove/force + +# Whether to remove blank lines after '{'. +eat_blanks_after_open_brace = false # true/false + +# Whether to remove blank lines before '}'. +eat_blanks_before_close_brace = false # true/false + +# How aggressively to remove extra newlines not in preprocessor. +# +# 0: No change (default) +# 1: Remove most newlines not handled by other config +# 2: Remove all newlines and reformat completely by config +nl_remove_extra_newlines = 0 # unsigned number + +# (Java) Add or remove newline after an annotation statement. Only affects +# annotations that are after a newline. +nl_after_annotation = ignore # ignore/add/remove/force + +# (Java) Add or remove newline between two annotations. +nl_between_annotation = ignore # ignore/add/remove/force + +# The number of newlines before a whole-file #ifdef. +# +# 0: No change (default). +#nl_before_whole_file_ifdef = 0 # unsigned number ### not 0.69 + +# The number of newlines after a whole-file #ifdef. +# +# 0: No change (default). +#nl_after_whole_file_ifdef = 0 # unsigned number ### not 0.69 + +# The number of newlines before a whole-file #endif. +# +# 0: No change (default). +#nl_before_whole_file_endif = 0 # unsigned number ### not 0.69 + +# The number of newlines after a whole-file #endif. +# +# 0: No change (default). +#nl_after_whole_file_endif = 0 # unsigned number ### not 0.69 + +# +# Positioning options +# + +# The position of arithmetic operators in wrapped expressions. +pos_arith = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of assignment in wrapped expressions. Do not affect '=' +# followed by '{'. +pos_assign = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of Boolean operators in wrapped expressions. +pos_bool = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of comparison operators in wrapped expressions. +pos_compare = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of conditional operators, as in the '?' and ':' of +# 'expr ? stmt : stmt', in wrapped expressions. +pos_conditional = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of the comma in wrapped expressions. +pos_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of the comma in enum entries. +pos_enum_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of the comma in the base class list if there is more than one +# line. Affects nl_class_init_args. +pos_class_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of the comma in the constructor initialization list. +# Related to nl_constr_colon, nl_constr_init_args and pos_constr_colon. +pos_constr_comma = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of trailing/leading class colon, between class and base class +# list. Affects nl_class_colon. +pos_class_colon = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# The position of colons between constructor and member initialization. +# Related to nl_constr_colon, nl_constr_init_args and pos_constr_comma. +pos_constr_colon = ignore # ignore/break/force/lead/trail/join/lead_break/lead_force/trail_break/trail_force + +# +# Line splitting options +# + +# Try to limit code width to N columns. +code_width = 0 # unsigned number + +# Whether to fully split long 'for' statements at semi-colons. +ls_for_split_full = false # true/false + +# Whether to fully split long function prototypes/calls at commas. +# The option ls_code_width has priority over the option ls_func_split_full. +ls_func_split_full = false # true/false + +# Whether to split lines as close to code_width as possible and ignore some +# groupings. +# The option ls_code_width has priority over the option ls_func_split_full. +ls_code_width = false # true/false + +# +# Code alignment options (not left column spaces/tabs) +# + +# Whether to keep non-indenting tabs. +align_keep_tabs = false # true/false + +# Whether to use tabs for aligning. +align_with_tabs = false # true/false + +# Whether to bump out to the next tab when aligning. +align_on_tabstop = false # true/false + +# Whether to right-align numbers. +align_number_right = false # true/false + +# Whether to keep whitespace not required for alignment. +align_keep_extra_space = false # true/false + +# Whether to align variable definitions in prototypes and functions. +align_func_params = false # true/false + +# The span for aligning parameter definitions in function on parameter name. +# +# 0: Don't align (default). +align_func_params_span = 0 # unsigned number + +# The threshold for aligning function parameter definitions. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_func_params_thresh = 0 # number + +# The gap for aligning function parameter definitions. +align_func_params_gap = 0 # unsigned number + +# The span for aligning constructor value. +# +# 0: Don't align (default). +align_constr_value_span = 0 # unsigned number + +# The threshold for aligning constructor value. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_constr_value_thresh = 0 # number + +# The gap for aligning constructor value. +align_constr_value_gap = 0 # unsigned number + +# Whether to align parameters in single-line functions that have the same +# name. The function names must already be aligned with each other. +align_same_func_call_params = false # true/false + +# The span for aligning function-call parameters for single line functions. +# +# 0: Don't align (default). +align_same_func_call_params_span = 0 # unsigned number + +# The threshold for aligning function-call parameters for single line +# functions. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_same_func_call_params_thresh = 0 # number + +# The span for aligning variable definitions. +# +# 0: Don't align (default). +align_var_def_span = 0 # unsigned number + +# How to consider (or treat) the '*' in the alignment of variable definitions. +# +# 0: Part of the type 'void * foo;' (default) +# 1: Part of the variable 'void *foo;' +# 2: Dangling 'void *foo;' +# Dangling: the '*' will not be taken into account when aligning. +align_var_def_star_style = 0 # unsigned number + +# How to consider (or treat) the '&' in the alignment of variable definitions. +# +# 0: Part of the type 'long & foo;' (default) +# 1: Part of the variable 'long &foo;' +# 2: Dangling 'long &foo;' +# Dangling: the '&' will not be taken into account when aligning. +align_var_def_amp_style = 0 # unsigned number + +# The threshold for aligning variable definitions. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_var_def_thresh = 0 # number + +# The gap for aligning variable definitions. +align_var_def_gap = 0 # unsigned number + +# Whether to align the colon in struct bit fields. +align_var_def_colon = false # true/false + +# The gap for aligning the colon in struct bit fields. +align_var_def_colon_gap = 0 # unsigned number + +# Whether to align any attribute after the variable name. +align_var_def_attribute = false # true/false + +# Whether to align inline struct/enum/union variable definitions. +align_var_def_inline = false # true/false + +# The span for aligning on '=' in assignments. +# +# 0: Don't align (default). +align_assign_span = 0 # unsigned number + +# The span for aligning on '=' in function prototype modifier. +# +# 0: Don't align (default). +align_assign_func_proto_span = 0 # unsigned number + +# The threshold for aligning on '=' in assignments. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_assign_thresh = 0 # number + +# How to apply align_assign_span to function declaration "assignments", i.e. +# 'virtual void foo() = 0' or '~foo() = {default|delete}'. +# +# 0: Align with other assignments (default) +# 1: Align with each other, ignoring regular assignments +# 2: Don't align +align_assign_decl_func = 0 # unsigned number + +# The span for aligning on '=' in enums. +# +# 0: Don't align (default). +align_enum_equ_span = 0 # unsigned number + +# The threshold for aligning on '=' in enums. +# Use a negative number for absolute thresholds. +# +# 0: no limit (default). +align_enum_equ_thresh = 0 # number + +# The span for aligning class member definitions. +# +# 0: Don't align (default). +align_var_class_span = 0 # unsigned number + +# The threshold for aligning class member definitions. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_var_class_thresh = 0 # number + +# The gap for aligning class member definitions. +align_var_class_gap = 0 # unsigned number + +# The span for aligning struct/union member definitions. +# +# 0: Don't align (default). +align_var_struct_span = 0 # unsigned number + +# The threshold for aligning struct/union member definitions. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_var_struct_thresh = 0 # number + +# The gap for aligning struct/union member definitions. +align_var_struct_gap = 0 # unsigned number + +# The span for aligning struct initializer values. +# +# 0: Don't align (default). +align_struct_init_span = 0 # unsigned number + +# The span for aligning single-line typedefs. +# +# 0: Don't align (default). +align_typedef_span = 0 # unsigned number + +# The minimum space between the type and the synonym of a typedef. +align_typedef_gap = 0 # unsigned number + +# How to align typedef'd functions with other typedefs. +# +# 0: Don't mix them at all (default) +# 1: Align the open parenthesis with the types +# 2: Align the function type name with the other type names +align_typedef_func = 0 # unsigned number + +# How to consider (or treat) the '*' in the alignment of typedefs. +# +# 0: Part of the typedef type, 'typedef int * pint;' (default) +# 1: Part of type name: 'typedef int *pint;' +# 2: Dangling: 'typedef int *pint;' +# Dangling: the '*' will not be taken into account when aligning. +align_typedef_star_style = 0 # unsigned number + +# How to consider (or treat) the '&' in the alignment of typedefs. +# +# 0: Part of the typedef type, 'typedef int & intref;' (default) +# 1: Part of type name: 'typedef int &intref;' +# 2: Dangling: 'typedef int &intref;' +# Dangling: the '&' will not be taken into account when aligning. +align_typedef_amp_style = 0 # unsigned number + +# The span for aligning comments that end lines. +# +# 0: Don't align (default). +align_right_cmt_span = 0 # unsigned number + +# Minimum number of columns between preceding text and a trailing comment in +# order for the comment to qualify for being aligned. Must be non-zero to have +# an effect. +align_right_cmt_gap = 0 # unsigned number + +# If aligning comments, whether to mix with comments after '}' and #endif with +# less than three spaces before the comment. +align_right_cmt_mix = false # true/false + +# Whether to only align trailing comments that are at the same brace level. +align_right_cmt_same_level = false # true/false + +# Minimum column at which to align trailing comments. Comments which are +# aligned beyond this column, but which can be aligned in a lesser column, +# may be "pulled in". +# +# 0: Ignore (default). +align_right_cmt_at_col = 0 # unsigned number + +# The span for aligning function prototypes. +# +# 0: Don't align (default). +align_func_proto_span = 0 # unsigned number + +# The threshold for aligning function prototypes. +# Use a negative number for absolute thresholds. +# +# 0: No limit (default). +align_func_proto_thresh = 0 # number + +# Minimum gap between the return type and the function name. +align_func_proto_gap = 0 # unsigned number + +# Whether to align function prototypes on the 'operator' keyword instead of +# what follows. +align_on_operator = false # true/false + +# Whether to mix aligning prototype and variable declarations. If true, +# align_var_def_XXX options are used instead of align_func_proto_XXX options. +align_mix_var_proto = false # true/false + +# Whether to align single-line functions with function prototypes. +# Uses align_func_proto_span. +align_single_line_func = false # true/false + +# Whether to align the open brace of single-line functions. +# Requires align_single_line_func=true. Uses align_func_proto_span. +align_single_line_brace = false # true/false + +# Gap for align_single_line_brace. +align_single_line_brace_gap = 0 # unsigned number + +# (OC) The span for aligning Objective-C message specifications. +# +# 0: Don't align (default). +align_oc_msg_spec_span = 0 # unsigned number + +# Whether to align macros wrapped with a backslash and a newline. This will +# not work right if the macro contains a multi-line comment. +align_nl_cont = false # true/false + +# Whether to align macro functions and variables together. +align_pp_define_together = false # true/false + +# The span for aligning on '#define' bodies. +# +# =0: Don't align (default) +# >0: Number of lines (including comments) between blocks +align_pp_define_span = 0 # unsigned number + +# The minimum space between label and value of a preprocessor define. +align_pp_define_gap = 0 # unsigned number + +# Whether to align lines that start with '<<' with previous '<<'. +# +# Default: true +align_left_shift = true # true/false + +# Whether to align text after 'asm volatile ()' colons. +align_asm_colon = false # true/false + +# (OC) Span for aligning parameters in an Objective-C message call +# on the ':'. +# +# 0: Don't align. +align_oc_msg_colon_span = 0 # unsigned number + +# (OC) Whether to always align with the first parameter, even if it is too +# short. +align_oc_msg_colon_first = false # true/false + +# (OC) Whether to align parameters in an Objective-C '+' or '-' declaration +# on the ':'. +align_oc_decl_colon = false # true/false + +# (OC) Whether to not align parameters in an Objectve-C message call if first +# colon is not on next line of the message call (the same way Xcode does +# aligment) +#align_oc_msg_colon_xcode_like = false # true/false ### not 0.69 + +# +# Comment modification options +# + +# Try to wrap comments at N columns. +cmt_width = 0 # unsigned number + +# How to reflow comments. +# +# 0: No reflowing (apart from the line wrapping due to cmt_width) (default) +# 1: No touching at all +# 2: Full reflow +cmt_reflow_mode = 0 # unsigned number + +# Whether to convert all tabs to spaces in comments. If false, tabs in +# comments are left alone, unless used for indenting. +cmt_convert_tab_to_spaces = false # true/false + +# Whether to apply changes to multi-line comments, including cmt_width, +# keyword substitution and leading chars. +# +# Default: true +cmt_indent_multi = true # true/false + +# Whether to group c-comments that look like they are in a block. +cmt_c_group = false # true/false + +# Whether to put an empty '/*' on the first line of the combined c-comment. +cmt_c_nl_start = false # true/false + +# Whether to add a newline before the closing '*/' of the combined c-comment. +cmt_c_nl_end = false # true/false + +# Whether to change cpp-comments into c-comments. +cmt_cpp_to_c = false # true/false + +# Whether to group cpp-comments that look like they are in a block. Only +# meaningful if cmt_cpp_to_c=true. +cmt_cpp_group = false # true/false + +# Whether to put an empty '/*' on the first line of the combined cpp-comment +# when converting to a c-comment. +# +# Requires cmt_cpp_to_c=true and cmt_cpp_group=true. +cmt_cpp_nl_start = false # true/false + +# Whether to add a newline before the closing '*/' of the combined cpp-comment +# when converting to a c-comment. +# +# Requires cmt_cpp_to_c=true and cmt_cpp_group=true. +cmt_cpp_nl_end = false # true/false + +# Whether to put a star on subsequent comment lines. +cmt_star_cont = false # true/false + +# The number of spaces to insert at the start of subsequent comment lines. +cmt_sp_before_star_cont = 0 # unsigned number + +# The number of spaces to insert after the star on subsequent comment lines. +cmt_sp_after_star_cont = 0 # unsigned number + +# For multi-line comments with a '*' lead, remove leading spaces if the first +# and last lines of the comment are the same length. +# +# Default: true +cmt_multi_check_last = true # true/false + +# For multi-line comments with a '*' lead, remove leading spaces if the first +# and last lines of the comment are the same length AND if the length is +# bigger as the first_len minimum. +# +# Default: 4 +cmt_multi_first_len_minimum = 4 # unsigned number + +# Path to a file that contains text to insert at the beginning of a file if +# the file doesn't start with a C/C++ comment. If the inserted text contains +# '$(filename)', that will be replaced with the current file's name. +cmt_insert_file_header = "" # string + +# Path to a file that contains text to insert at the end of a file if the +# file doesn't end with a C/C++ comment. If the inserted text contains +# '$(filename)', that will be replaced with the current file's name. +cmt_insert_file_footer = "" # string + +# Path to a file that contains text to insert before a function definition if +# the function isn't preceded by a C/C++ comment. If the inserted text +# contains '$(function)', '$(javaparam)' or '$(fclass)', these will be +# replaced with, respectively, the name of the function, the javadoc '@param' +# and '@return' stuff, or the name of the class to which the member function +# belongs. +cmt_insert_func_header = "" # string + +# Path to a file that contains text to insert before a class if the class +# isn't preceded by a C/C++ comment. If the inserted text contains '$(class)', +# that will be replaced with the class name. +cmt_insert_class_header = "" # string + +# Path to a file that contains text to insert before an Objective-C message +# specification, if the method isn't preceded by a C/C++ comment. If the +# inserted text contains '$(message)' or '$(javaparam)', these will be +# replaced with, respectively, the name of the function, or the javadoc +# '@param' and '@return' stuff. +cmt_insert_oc_msg_header = "" # string + +# Whether a comment should be inserted if a preprocessor is encountered when +# stepping backwards from a function name. +# +# Applies to cmt_insert_oc_msg_header, cmt_insert_func_header and +# cmt_insert_class_header. +cmt_insert_before_preproc = false # true/false + +# Whether a comment should be inserted if a function is declared inline to a +# class definition. +# +# Applies to cmt_insert_func_header. +# +# Default: true +cmt_insert_before_inlines = true # true/false + +# Whether a comment should be inserted if the function is a class constructor +# or destructor. +# +# Applies to cmt_insert_func_header. +cmt_insert_before_ctor_dtor = false # true/false + +# +# Code modifying options (non-whitespace) +# + +# Add or remove braces on a single-line 'do' statement. +mod_full_brace_do = remove # ignore/add/remove/force + +# Add or remove braces on a single-line 'for' statement. +mod_full_brace_for = remove # ignore/add/remove/force + +# (Pawn) Add or remove braces on a single-line function definition. +mod_full_brace_function = ignore # ignore/add/remove/force + +# Add or remove braces on a single-line 'if' statement. Braces will not be +# removed if the braced statement contains an 'else'. +mod_full_brace_if = add # ignore/add/remove/force + +# Whether to enforce that all blocks of an 'if'/'else if'/'else' chain either +# have, or do not have, braces. If true, braces will be added if any block +# needs braces, and will only be removed if they can be removed from all +# blocks. +# +# Overrides mod_full_brace_if. +mod_full_brace_if_chain = false # true/false + +# Whether to add braces to all blocks of an 'if'/'else if'/'else' chain. +# If true, mod_full_brace_if_chain will only remove braces from an 'if' that +# does not have an 'else if' or 'else'. +mod_full_brace_if_chain_only = true # true/false + +# Add or remove braces on single-line 'while' statement. +mod_full_brace_while = remove # ignore/add/remove/force + +# Add or remove braces on single-line 'using ()' statement. +mod_full_brace_using = remove # ignore/add/remove/force + +# Don't remove braces around statements that span N newlines +mod_full_brace_nl = 0 # unsigned number + +# Whether to prevent removal of braces from 'if'/'for'/'while'/etc. blocks +# which span multiple lines. +# +# Affects: +# mod_full_brace_for +# mod_full_brace_if +# mod_full_brace_if_chain +# mod_full_brace_if_chain_only +# mod_full_brace_while +# mod_full_brace_using +# +# Does not affect: +# mod_full_brace_do +# mod_full_brace_function +mod_full_brace_nl_block_rem_mlcond = false # true/false + +# Add or remove unnecessary parenthesis on 'return' statement. +mod_paren_on_return = add # ignore/add/remove/force + +# (Pawn) Whether to change optional semicolons to real semicolons. +mod_pawn_semicolon = false # true/false + +# Whether to fully parenthesize Boolean expressions in 'while' and 'if' +# statement, as in 'if (a && b > c)' => 'if (a && (b > c))'. +mod_full_paren_if_bool = false # true/false + +# Whether to remove superfluous semicolons. +mod_remove_extra_semicolon = false # true/false + +# If a function body exceeds the specified number of newlines and doesn't have +# a comment after the close brace, a comment will be added. +mod_add_long_function_closebrace_comment = 0 # unsigned number + +# If a namespace body exceeds the specified number of newlines and doesn't +# have a comment after the close brace, a comment will be added. +mod_add_long_namespace_closebrace_comment = 0 # unsigned number + +# If a class body exceeds the specified number of newlines and doesn't have a +# comment after the close brace, a comment will be added. +mod_add_long_class_closebrace_comment = 0 # unsigned number + +# If a switch body exceeds the specified number of newlines and doesn't have a +# comment after the close brace, a comment will be added. +mod_add_long_switch_closebrace_comment = 0 # unsigned number + +# If an #ifdef body exceeds the specified number of newlines and doesn't have +# a comment after the #endif, a comment will be added. +mod_add_long_ifdef_endif_comment = 0 # unsigned number + +# If an #ifdef or #else body exceeds the specified number of newlines and +# doesn't have a comment after the #else, a comment will be added. +mod_add_long_ifdef_else_comment = 0 # unsigned number + +# Whether to take care of the case by the mod_sort_xx options. +#mod_sort_case_sensitive = false # true/false ### not 0.69 + +# Whether to sort consecutive single-line 'import' statements. +mod_sort_import = false # true/false + +# (C#) Whether to sort consecutive single-line 'using' statements. +mod_sort_using = false # true/false + +# Whether to sort consecutive single-line '#include' statements (C/C++) and +# '#import' statements (Objective-C). Be aware that this has the potential to +# break your code if your includes/imports have ordering dependencies. +mod_sort_include = false # true/false + +# Whether to prioritize '#include' and '#import' statements that contain +# filename without extension when sorting is enabled. +#mod_sort_incl_import_prioritize_filename = false # true/false ### not 0.69 + +# Whether to prioritize '#include' and '#import' statements that does not +# contain extensions when sorting is enabled. +#mod_sort_incl_import_prioritize_extensionless = false # true/false ### not 0.69 + +# Whether to prioritize '#include' and '#import' statements that contain +# angle over quotes when sorting is enabled. +#mod_sort_incl_import_prioritize_angle_over_quotes = false # true/false ### not 0.69 + +# Whether to ignore file extension in '#include' and '#import' statements +# for sorting comparison. +#mod_sort_incl_import_ignore_extension = false # true/false ### not 0.69 + +# Whether to group '#include' and '#import' statements when sorting is enabled. +#mod_sort_incl_import_grouping_enabled = false # true/false ### not 0.69 + +# Whether to move a 'break' that appears after a fully braced 'case' before +# the close brace, as in 'case X: { ... } break;' => 'case X: { ... break; }'. +mod_move_case_break = false # true/false + +# Add or remove braces around a fully braced case statement. Will only remove +# braces if there are no variable declarations in the block. +mod_case_brace = ignore # ignore/add/remove/force + +# Whether to remove a void 'return;' that appears as the last statement in a +# function. +mod_remove_empty_return = false # true/false + +# Add or remove the comma after the last value of an enumeration. +mod_enum_last_comma = ignore # ignore/add/remove/force + +# (OC) Whether to organize the properties. If true, properties will be +# rearranged according to the mod_sort_oc_property_*_weight factors. +mod_sort_oc_properties = false # true/false + +# (OC) Weight of a class property modifier. +mod_sort_oc_property_class_weight = 0 # number + +# (OC) Weight of 'atomic' and 'nonatomic'. +mod_sort_oc_property_thread_safe_weight = 0 # number + +# (OC) Weight of 'readwrite' when organizing properties. +mod_sort_oc_property_readwrite_weight = 0 # number + +# (OC) Weight of a reference type specifier ('retain', 'copy', 'assign', +# 'weak', 'strong') when organizing properties. +mod_sort_oc_property_reference_weight = 0 # number + +# (OC) Weight of getter type ('getter=') when organizing properties. +mod_sort_oc_property_getter_weight = 0 # number + +# (OC) Weight of setter type ('setter=') when organizing properties. +mod_sort_oc_property_setter_weight = 0 # number + +# (OC) Weight of nullability type ('nullable', 'nonnull', 'null_unspecified', +# 'null_resettable') when organizing properties. +mod_sort_oc_property_nullability_weight = 0 # number + +# +# Preprocessor options +# + +# Add or remove indentation of preprocessor directives inside #if blocks +# at brace level 0 (file-level). +pp_indent = ignore # ignore/add/remove/force + +# Whether to indent #if/#else/#endif at the brace level. If false, these are +# indented from column 1. +pp_indent_at_level = false # true/false + +# Specifies the number of columns to indent preprocessors per level +# at brace level 0 (file-level). If pp_indent_at_level=false, also specifies +# the number of columns to indent preprocessors per level +# at brace level > 0 (function-level). +# +# Default: 1 +pp_indent_count = 1 # unsigned number + +# Add or remove space after # based on pp_level of #if blocks. +pp_space = ignore # ignore/add/remove/force + +# Sets the number of spaces per level added with pp_space. +pp_space_count = 0 # unsigned number + +# The indent for '#region' and '#endregion' in C# and '#pragma region' in +# C/C++. Negative values decrease indent down to the first column. +pp_indent_region = 0 # number + +# Whether to indent the code between #region and #endregion. +pp_region_indent_code = false # true/false + +# If pp_indent_at_level=true, sets the indent for #if, #else and #endif when +# not at file-level. Negative values decrease indent down to the first column. +# +# =0: Indent preprocessors using output_tab_size +# >0: Column at which all preprocessors will be indented +pp_indent_if = 0 # number + +# Whether to indent the code between #if, #else and #endif. +pp_if_indent_code = false # true/false + +# Whether to indent '#define' at the brace level. If false, these are +# indented from column 1. +pp_define_at_level = false # true/false + +# Whether to ignore the '#define' body while formatting. +pp_ignore_define_body = false # true/false + +# Whether to indent case statements between #if, #else, and #endif. +# Only applies to the indent of the preprocesser that the case statements +# directly inside of. +# +# Default: true +pp_indent_case = true # true/false + +# Whether to indent whole function definitions between #if, #else, and #endif. +# Only applies to the indent of the preprocesser that the function definition +# is directly inside of. +# +# Default: true +pp_indent_func_def = true # true/false + +# Whether to indent extern C blocks between #if, #else, and #endif. +# Only applies to the indent of the preprocesser that the extern block is +# directly inside of. +# +# Default: true +pp_indent_extern = true # true/false + +# Whether to indent braces directly inside #if, #else, and #endif. +# Only applies to the indent of the preprocesser that the braces are directly +# inside of. +# +# Default: true +pp_indent_brace = true # true/false + +# +# Sort includes options +# + +# The regex for include category with priority 0. +include_category_0 = "" # string + +# The regex for include category with priority 1. +include_category_1 = "" # string + +# The regex for include category with priority 2. +include_category_2 = "" # string + +# +# Use or Do not Use options +# + +# true: indent_func_call_param will be used (default) +# false: indent_func_call_param will NOT be used +# +# Default: true +use_indent_func_call_param = true # true/false + +# The value of the indentation for a continuation line is calculated +# differently if the statement is: +# - a declaration: your case with QString fileName ... +# - an assignment: your case with pSettings = new QSettings( ... +# +# At the second case the indentation value might be used twice: +# - at the assignment +# - at the function call (if present) +# +# To prevent the double use of the indentation value, use this option with the +# value 'true'. +# +# true: indent_continue will be used only once +# false: indent_continue will be used every time (default) +use_indent_continue_only_once = false # true/false + +# The value might be used twice: +# - at the assignment +# - at the opening brace +# +# To prevent the double use of the indentation value, use this option with the +# value 'true'. +# +# true: indentation will be used only once +# false: indentation will be used every time (default) +indent_cpp_lambda_only_once = false # true/false + +# Whether sp_after_angle takes precedence over sp_inside_fparen. This was the +# historic behavior, but is probably not the desired behavior, so this is off +# by default. +#use_sp_after_angle_always = false # true/false ### not 0.69 + +# Whether to apply special formatting for Qt SIGNAL/SLOT macros. Essentially, +# this tries to format these so that they match Qt's normalized form (i.e. the +# result of QMetaObject::normalizedSignature), which can slightly improve the +# performance of the QObject::connect call, rather than how they would +# otherwise be formatted. +# +# See options_for_QT.cpp for details. +# +# Default: true +use_options_overriding_for_qt_macros = true # true/false + +# If true: the form feed character is removed from the list +# of whitespace characters. +# See https://en.cppreference.com/w/cpp/string/byte/isspace +#use_form_feed_no_more_as_whitespace_character = false # true/false ### not 0.69 + +# +# Warn levels - 1: error, 2: warning (default), 3: note +# + +# (C#) Warning is given if doing tab-to-\t replacement and we have found one +# in a C# verbatim string literal. +# +# Default: 2 +warn_level_tabs_found_in_verbatim_string_literals = 2 # unsigned number + +# Limit the number of loops. +# Used by uncrustify.cpp to exit from infinite loop. +# 0: no limit. +#debug_max_number_of_loops = 0 # number ### not 0.69 + +# Set the number of the line to protocol; +# Used in the function prot_the_line if the 2. parameter is zero. +# 0: nothing protocol. +#debug_line_number_to_protocol = 0 # number ### not 0.69 + +# Meaning of the settings: +# Ignore - do not do any changes +# Add - makes sure there is 1 or more space/brace/newline/etc +# Force - makes sure there is exactly 1 space/brace/newline/etc, +# behaves like Add in some contexts +# Remove - removes space/brace/newline/etc +# +# +# - Token(s) can be treated as specific type(s) with the 'set' option: +# `set tokenType tokenString [tokenString...]` +# +# Example: +# `set BOOL __AND__ __OR__` +# +# tokenTypes are defined in src/token_enum.h, use them without the +# 'CT_' prefix: 'CT_BOOL' => 'BOOL' +# +# +# - Token(s) can be treated as type(s) with the 'type' option. +# `type tokenString [tokenString...]` +# +# Example: +# `type int c_uint_8 Rectangle` +# +# This can also be achieved with `set TYPE int c_uint_8 Rectangle` +# +# +# To embed whitespace in tokenStrings use the '\' escape character, or quote +# the tokenStrings. These quotes are supported: "'` +# +# +# - Support for the auto detection of languages through the file ending can be +# added using the 'file_ext' command. +# `file_ext langType langString [langString..]` +# +# Example: +# `file_ext CPP .ch .cxx .cpp.in` +# +# langTypes are defined in uncrusify_types.h in the lang_flag_e enum, use +# them without the 'LANG_' prefix: 'LANG_CPP' => 'CPP' +# +# +# - Custom macro-based indentation can be set up using 'macro-open', +# 'macro-else' and 'macro-close'. +# `(macro-open | macro-else | macro-close) tokenString` +# +# Example: +# `macro-open BEGIN_TEMPLATE_MESSAGE_MAP` +# `macro-open BEGIN_MESSAGE_MAP` +# `macro-close END_MESSAGE_MAP` +# +# +# option(s) with 'not default' value: 0 +# diff --git a/flashloaders/linker.ld b/flashloaders/linker.ld index 4d06433ea..7267fe10f 100644 --- a/flashloaders/linker.ld +++ b/flashloaders/linker.ld @@ -1,9 +1,9 @@ -/*. Entry Point *./ +/* Entry Point */ ENTRY( copy ) -/*. Specify the memory areas .*/ +/* Specify the memory areas */ MEMORY { RAM ( xrw) : ORIGIN = 0x20000000 , LENGTH = 64K -} \ No newline at end of file +} diff --git a/src/backend.h b/inc/backend.h similarity index 94% rename from src/backend.h rename to inc/backend.h index 42d12d4ac..f852da05d 100644 --- a/src/backend.h +++ b/inc/backend.h @@ -28,7 +28,7 @@ int (*current_mode) (stlink_t * stl); int (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); - int (*set_swdclk) (stlink_t * stl, uint16_t divisor); + int (*set_swdclk) (stlink_t * stl, uint16_t divisor); } stlink_backend_t; -#endif /* STLINK_BACKEND_H_ */ +#endif // STLINK_BACKEND_H_ diff --git a/inc/stlink.h b/inc/stlink.h index c87c6b173..140d68866 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -18,11 +18,11 @@ extern "C" { #endif -#define STLINK_ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0])) +#define STLINK_ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0])) /* Max data transfer size */ // 6kB = max mem32_read block, 8kB sram -//#define Q_BUF_LEN 96 +// #define Q_BUF_LEN 96 #define Q_BUF_LEN (1024 * 100) // STLINK_DEBUG_RESETSYS, etc: @@ -103,16 +103,16 @@ enum target_state { #define S_RESET_ST (1 << 25) /* Map the relevant features, quirks and workaround for specific firmware version of stlink */ -#define STLINK_F_HAS_TRACE (1<<0) -#define STLINK_F_HAS_SWD_SET_FREQ (1<<1) -#define STLINK_F_HAS_JTAG_SET_FREQ (1<<2) -#define STLINK_F_HAS_MEM_16BIT (1<<3) -#define STLINK_F_HAS_GETLASTRWSTATUS2 (1<<4) -#define STLINK_F_HAS_DAP_REG (1<<5) -#define STLINK_F_QUIRK_JTAG_DP_READ (1<<6) -#define STLINK_F_HAS_AP_INIT (1<<7) -#define STLINK_F_HAS_DPBANKSEL (1<<8) -#define STLINK_F_HAS_RW8_512BYTES (1<<9) +#define STLINK_F_HAS_TRACE (1 << 0) +#define STLINK_F_HAS_SWD_SET_FREQ (1 << 1) +#define STLINK_F_HAS_JTAG_SET_FREQ (1 << 2) +#define STLINK_F_HAS_MEM_16BIT (1 << 3) +#define STLINK_F_HAS_GETLASTRWSTATUS2 (1 << 4) +#define STLINK_F_HAS_DAP_REG (1 << 5) +#define STLINK_F_QUIRK_JTAG_DP_READ (1 << 6) +#define STLINK_F_HAS_AP_INIT (1 << 7) +#define STLINK_F_HAS_DPBANKSEL (1 << 8) +#define STLINK_F_HAS_RW8_512BYTES (1 << 9) #define C_BUF_LEN 32 @@ -146,8 +146,8 @@ struct stlink_reg { typedef uint32_t stm32_addr_t; typedef struct flash_loader { -stm32_addr_t loader_addr; // loader sram addr -stm32_addr_t buf_addr; // buffer sram address + stm32_addr_t loader_addr; // loader sram addr + stm32_addr_t buf_addr; // buffer sram address } flash_loader_t; typedef struct _cortex_m3_cpuid_ { @@ -183,16 +183,16 @@ enum transport_type { }; typedef struct _stlink stlink_t; - + #include struct _stlink { struct _stlink_backend *backend; void *backend_data; - // Room for the command header + // room for the command header unsigned char c_buf[C_BUF_LEN]; - // Data transferred from or to device + // data transferred from or to device unsigned char q_buf[Q_BUF_LEN]; int q_len; @@ -205,28 +205,29 @@ struct _stlink { char serial[STLINK_SERIAL_MAX_SIZE]; int serial_size; - int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR + int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx bool has_dual_bank; - stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() - size_t flash_size; // calculated by stlink_load_device_params() - size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() + stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() + size_t flash_size; // calculated by stlink_load_device_params() + size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() /* sram settings */ - stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() - size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() + stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() + size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() - /* option settings */ + /* option settings */ stm32_addr_t option_base; size_t option_size; // bootloader - // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code (see tests/sg.c) - stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() - size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() + // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code + // (see tests/sg.c) + stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() + size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() struct stlink_version_ version; }; @@ -306,4 +307,4 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr } #endif -#endif /* STLINK_H */ +#endif // STLINK_H diff --git a/inc/stm32.h b/inc/stm32.h index c71718653..36c14ee23 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -1,17 +1,17 @@ /* - * File: stm32.h + * File: stm32.h * - * STM32 specific defines + * STM32-specific defines */ #ifndef STM32_H #define STM32_H -// cortex core ids +/* Cortex core ids */ #define STM32VL_CORE_ID 0x1ba01477 #define STM32F7_CORE_ID 0x5ba02477 -// Constant STM32 memory map figures +/* Constant STM32 memory map figures */ #define STM32_FLASH_BASE ((uint32_t)0x08000000) #define STM32_SRAM_BASE ((uint32_t)0x20000000) #define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) @@ -21,4 +21,4 @@ #define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) -#endif /* STM32_H */ +#endif // STM32_H diff --git a/inc/version.h.in b/inc/version.h.in index 4ce2a5cac..66159e0e5 100644 --- a/inc/version.h.in +++ b/inc/version.h.in @@ -6,4 +6,4 @@ #define STLINK_VERSION_MINOR @PROJECT_VERSION_MINOR@ #define STLINK_VERSION_PATCH @PROJECT_VERSION_PATCH@ -#endif /* STLINK_VERSION_ */ +#endif // STLINK_VERSION_H_ diff --git a/src/common.c b/src/common.c index c9a54cf9f..361a24dbf 100644 --- a/src/common.c +++ b/src/common.c @@ -191,7 +191,7 @@ // WB Flash status register. #define STM32WB_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -//32L4 register base is at FLASH_REGS_ADDR (0x40022000) +// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) #define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) #define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) #define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) @@ -214,16 +214,16 @@ #define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ // Bits requesting flash operations (useful when we want to clear them) #define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu< le (don't swap) - buf[0] = ((unsigned char*) &ui)[0]; - buf[1] = ((unsigned char*) &ui)[1]; - buf[2] = ((unsigned char*) &ui)[2]; - buf[3] = ((unsigned char*) &ui)[3]; + buf[0] = ((unsigned char*)&ui)[0]; + buf[1] = ((unsigned char*)&ui)[1]; + buf[2] = ((unsigned char*)&ui)[2]; + buf[3] = ((unsigned char*)&ui)[3]; } else { - buf[0] = ((unsigned char*) &ui)[3]; - buf[1] = ((unsigned char*) &ui)[2]; - buf[2] = ((unsigned char*) &ui)[1]; - buf[3] = ((unsigned char*) &ui)[0]; + buf[0] = ((unsigned char*)&ui)[3]; + buf[1] = ((unsigned char*)&ui)[2]; + buf[2] = ((unsigned char*)&ui)[1]; + buf[3] = ((unsigned char*)&ui)[0]; } } void write_uint16(unsigned char* buf, uint16_t ui) { if (!is_bigendian()) { // le -> le (don't swap) - buf[0] = ((unsigned char*) &ui)[0]; - buf[1] = ((unsigned char*) &ui)[1]; + buf[0] = ((unsigned char*)&ui)[0]; + buf[1] = ((unsigned char*)&ui)[1]; } else { - buf[0] = ((unsigned char*) &ui)[1]; - buf[1] = ((unsigned char*) &ui)[0]; + buf[0] = ((unsigned char*)&ui)[1]; + buf[1] = ((unsigned char*)&ui)[0]; } } uint32_t read_uint32(const unsigned char *c, const int pt) { uint32_t ui; - char *p = (char *) &ui; + char *p = (char *)&ui; if (!is_bigendian()) { // le -> le (don't swap) p[0] = c[pt + 0]; @@ -317,49 +317,51 @@ uint32_t read_uint32(const unsigned char *c, const int pt) { p[2] = c[pt + 1]; p[3] = c[pt + 0]; } - return ui; + + return(ui); } static uint32_t get_stm32l0_flash_base(stlink_t *sl) { switch (sl->chip_id) { - case STLINK_CHIPID_STM32_L1_CAT2: - case STLINK_CHIPID_STM32_L1_MEDIUM: - case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS: - case STLINK_CHIPID_STM32_L1_HIGH: - return STM32L1_FLASH_REGS_ADDR; - default: - return STM32L0_FLASH_REGS_ADDR; + case STLINK_CHIPID_STM32_L1_CAT2: + case STLINK_CHIPID_STM32_L1_MEDIUM: + case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS: + case STLINK_CHIPID_STM32_L1_HIGH: + return(STM32L1_FLASH_REGS_ADDR); + default: + return(STM32L0_FLASH_REGS_ADDR); } } static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { uint32_t rdp; stlink_read_debug32(sl, FLASH_WRPR, &rdp); - return rdp & 0xff; + return(rdp & 0xff); } static inline uint32_t read_flash_cr(stlink_t *sl) { uint32_t reg, res; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { reg = FLASH_F4_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_L4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { reg = STM32L4_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { reg = STM32Gx_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { reg = STM32WB_FLASH_CR; - else + } else { reg = FLASH_CR; + } stlink_read_debug32(sl, reg, &res); #if DEBUG_FLASH fprintf(stdout, "CR:0x%x\n", res); #endif - return res; + return(res); } static inline uint32_t read_flash_cr2(stlink_t *sl) { @@ -368,7 +370,7 @@ static inline uint32_t read_flash_cr2(stlink_t *sl) { #if DEBUG_FLASH fprintf(stdout, "CR2:0x%x\n", res); #endif - return res; + return(res); } static inline unsigned int is_flash_locked(stlink_t *sl) { @@ -378,7 +380,7 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { uint32_t n; if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { @@ -399,25 +401,24 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { cr_lock_shift = STM32WB_FLASH_CR_LOCK; } else { ELOG("unsupported flash method, abort\n"); - return -1; + return(-1); } stlink_read_debug32(sl, cr_reg, &n); - return n & (1u << cr_lock_shift); + return(n & (1u << cr_lock_shift)); } static void unlock_flash(stlink_t *sl) { uint32_t key_reg; uint32_t flash_key1 = FLASH_KEY1; uint32_t flash_key2 = FLASH_KEY2; - /* the unlock sequence consists of 2 write cycles where - 2 key values are written to the FLASH_KEYR register. - an invalid sequence results in a definitive lock of - the FPEC block until next reset. - */ + /* The unlock sequence consists of 2 write cycles where 2 key values are written + * to the FLASH_KEYR register. + * An invalid sequence results in a definitive lock of the FPEC block until next reset. + */ if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { key_reg = FLASH_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { key_reg = FLASH_F4_KEYR; @@ -428,7 +429,7 @@ static void unlock_flash(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { key_reg = STM32L4_FLASH_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + sl->flash_type == STLINK_FLASH_TYPE_G4) { key_reg = STM32Gx_FLASH_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { key_reg = STM32WB_FLASH_KEYR; @@ -450,20 +451,22 @@ static void unlock_flash(stlink_t *sl) { static int unlock_flash_if(stlink_t *sl) { if (is_flash_locked(sl)) { unlock_flash(sl); + if (is_flash_locked(sl)) { WLOG("Failed to unlock flash!\n"); - return -1; + return(-1); } } + DLOG("Successfully unlocked flash\n"); - return 0; + return(0); } static void lock_flash(stlink_t *sl) { uint32_t cr_lock_shift, cr_reg, n; if (sl->flash_type == STLINK_FLASH_TYPE_F0 || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { @@ -503,43 +506,45 @@ static bool is_flash_option_locked(stlink_t *sl) { uint32_t n; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; /* bit is "option write enable", not lock */ - break; - case STLINK_FLASH_TYPE_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_L0: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STLINK_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_WB: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; // bit is "option write enable", not lock + break; + case STLINK_FLASH_TYPE_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_L0: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STLINK_FLASH_TYPE_L4: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_WB: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + default: + ELOG("unsupported flash method, abort\n"); + return(-1); } stlink_read_debug32(sl, optcr_reg, &n); - if (active_bit_level == 0) - return !(n & (1u << optlock_shift)); - return n & (1u << optlock_shift); + if (active_bit_level == 0) { + return(!(n & (1u << optlock_shift))); + } + + return(n & (1u << optlock_shift)); } @@ -548,46 +553,48 @@ static int lock_flash_option(stlink_t *sl) { int active_bit_level = 1; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; - break; - case STLINK_FLASH_TYPE_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_L0: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STLINK_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_WB: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; + break; + case STLINK_FLASH_TYPE_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_L0: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STLINK_FLASH_TYPE_L4: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_WB: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + default: + ELOG("unsupported flash method, abort\n"); + return(-1); } stlink_read_debug32(sl, optcr_reg, &n); - if (active_bit_level == 0) + + if (active_bit_level == 0) { n &= ~(1u << optlock_shift); - else + } else { n |= (1u << optlock_shift); - stlink_write_debug32(sl, optcr_reg, n); + } - return 0; + stlink_write_debug32(sl, optcr_reg, n); + return(0); } static int unlock_flash_option(stlink_t *sl) { @@ -596,55 +603,56 @@ static int unlock_flash_option(stlink_t *sl) { uint32_t optkey2 = FLASH_OPTKEY2; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optkey_reg = FLASH_OPTKEYR; - optkey1 = FLASH_F0_OPTKEY1; - optkey2 = FLASH_F0_OPTKEY2; - break; - case STLINK_FLASH_TYPE_F4: - optkey_reg = FLASH_F4_OPT_KEYR; - break; - case STLINK_FLASH_TYPE_L0: - optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; - optkey1 = FLASH_L0_OPTKEY1; - optkey2 = FLASH_L0_OPTKEY2; - break; - case STLINK_FLASH_TYPE_L4: - optkey_reg = STM32L4_FLASH_OPTKEYR; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optkey_reg = STM32Gx_FLASH_OPTKEYR; - break; - case STLINK_FLASH_TYPE_WB: - optkey_reg = STM32WB_FLASH_OPT_KEYR; - break; + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optkey_reg = FLASH_OPTKEYR; + optkey1 = FLASH_F0_OPTKEY1; + optkey2 = FLASH_F0_OPTKEY2; + break; + case STLINK_FLASH_TYPE_F4: + optkey_reg = FLASH_F4_OPT_KEYR; + break; + case STLINK_FLASH_TYPE_L0: + optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; + optkey1 = FLASH_L0_OPTKEY1; + optkey2 = FLASH_L0_OPTKEY2; + break; + case STLINK_FLASH_TYPE_L4: + optkey_reg = STM32L4_FLASH_OPTKEYR; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optkey_reg = STM32Gx_FLASH_OPTKEYR; + break; + case STLINK_FLASH_TYPE_WB: + optkey_reg = STM32WB_FLASH_OPT_KEYR; + break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; + default: + ELOG("unsupported flash method, abort\n"); + return(-1); } stlink_write_debug32(sl, optkey_reg, optkey1); stlink_write_debug32(sl, optkey_reg, optkey2); - - return 0; + return(0); } static int unlock_flash_option_if(stlink_t *sl) { if (is_flash_option_locked(sl)) { if (unlock_flash_option(sl)) { ELOG("Could not unlock flash option!\n"); - return -1; + return(-1); } + if (is_flash_option_locked(sl)) { ELOG("Failed to unlock flash option!\n"); - return -1; + return(-1); } } + DLOG("Successfully unlocked flash option\n"); - return 0; + return(0); } static void set_flash_cr_pg(stlink_t *sl) { @@ -677,17 +685,18 @@ static void set_flash_cr_pg(stlink_t *sl) { static void clear_flash_cr_pg(stlink_t *sl) { uint32_t cr_reg, n; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_L4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; - else + } else { cr_reg = FLASH_CR; + } n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); stlink_write_debug32(sl, cr_reg, n); @@ -697,12 +706,13 @@ static void set_flash_cr_per(stlink_t *sl) { uint32_t cr_reg, val; if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) + sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; - else + } else { cr_reg = FLASH_CR; + } stlink_read_debug32(sl, cr_reg, &val); val |= (1 << FLASH_CR_PER); @@ -718,12 +728,13 @@ static void clear_flash_cr_per(stlink_t *sl) { uint32_t cr_reg; if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) + sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - else if (sl->flash_type == STLINK_FLASH_TYPE_WB) + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; - else + } else { cr_reg = FLASH_CR; + } const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER); stlink_write_debug32(sl, cr_reg, n); @@ -744,9 +755,11 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { sl->flash_type == STLINK_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); + if (sl->has_dual_bank) { cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); } + cr_pg = (1 << FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; @@ -759,16 +772,19 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { } stlink_read_debug32(sl, cr_reg, &val); + if (val & cr_pg) { - /* STM32F030 will drop MER bit if PG was set */ + // STM32F030 will drop MER bit if PG was set val &= ~cr_pg; stlink_write_debug32(sl, cr_reg, val); } - if (v) + if (v) { val |= cr_mer; - else + } else { val &= ~cr_mer; + } + stlink_write_debug32(sl, cr_reg, val); } @@ -779,10 +795,13 @@ static void set_flash_cr2_mer(stlink_t *sl, bool v) { stlink_read_debug32(sl, FLASH_CR2, &val); val &= ~cr_pg; - if (v) + + if (v) { val |= cr_mer; - else + } else { val &= ~cr_mer; + } + stlink_write_debug32(sl, FLASH_CR2, val); } @@ -842,7 +861,8 @@ static void set_flash_cr2_strt(stlink_t *sl) { static inline uint32_t read_flash_sr(stlink_t *sl) { uint32_t res, sr_reg; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { sr_reg = FLASH_SR; } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; @@ -851,44 +871,45 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { sr_reg = STM32L4_FLASH_SR; } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + sl->flash_type == STLINK_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { sr_reg = STM32WB_FLASH_SR; } else { ELOG("unsupported flash method, abort"); - return -1; + return(-1); } stlink_read_debug32(sl, sr_reg, &res); - - return res; + return(res); } static inline uint32_t read_flash_sr2(stlink_t *sl) { uint32_t res; stlink_read_debug32(sl, FLASH_SR2, &res); - return res; + return(res); } static inline unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; unsigned int res; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_L0)) { + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_L0)) { sr_busy_shift = FLASH_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { sr_busy_shift = FLASH_F4_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { sr_busy_shift = STM32L4_FLASH_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + sl->flash_type == STLINK_FLASH_TYPE_G4) { sr_busy_shift = STM32Gx_FLASH_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { sr_busy_shift = STM32WB_FLASH_SR_BSY; } else { ELOG("unsupported flash method, abort"); - return -1; + return(-1); } res = read_flash_sr(sl) & (1 << sr_busy_shift); @@ -897,11 +918,11 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { res |= read_flash_sr2(sl) & (1 << sr_busy_shift); } - return res; + return(res); } static void wait_flash_busy(stlink_t *sl) { - /* todo: add some delays here */ + // TODO: add some delays here while (is_flash_busy(sl)) ; } @@ -910,44 +931,48 @@ static void wait_flash_busy_progress(stlink_t *sl) { int i = 0; fprintf(stdout, "Mass erasing"); fflush(stdout); + while (is_flash_busy(sl)) { usleep(10000); i++; + if (i % 100 == 0) { fprintf(stdout, "."); fflush(stdout); } } + fprintf(stdout, "\n"); } static int check_flash_error(stlink_t *sl) { uint32_t res = 0; + switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - res = read_flash_sr(sl) & FLASH_SR_ERROR_MASK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - res = read_flash_sr(sl) & STM32Gx_FLASH_SR_ERROR_MASK; - break; - case STLINK_FLASH_TYPE_L0: - res = read_flash_sr(sl) & STM32L0_FLASH_SR_ERROR_MASK; - default: - break; + case STLINK_FLASH_TYPE_F0: + res = read_flash_sr(sl) & FLASH_SR_ERROR_MASK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + res = read_flash_sr(sl) & STM32Gx_FLASH_SR_ERROR_MASK; + break; + case STLINK_FLASH_TYPE_L0: + res = read_flash_sr(sl) & STM32L0_FLASH_SR_ERROR_MASK; + default: + break; } if (res) { ELOG("Flash programming error : %#010x\n", res); - return -1; + return(-1); } - return 0; + return(0); } static inline unsigned int is_flash_eop(stlink_t *sl) { - return read_flash_sr(sl) & (1 << FLASH_SR_EOP); + return(read_flash_sr(sl) & (1 << FLASH_SR_EOP)); } static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) { @@ -956,7 +981,7 @@ static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) { } static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) { - /* todo: add some delays here */ + // TODO: add some delays here while (is_flash_eop(sl) == 0) ; } @@ -992,12 +1017,12 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { } static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { - stlink_write_debug32(sl, STM32L4_FLASH_SR, 0xFFFFFFFF & ~(1<backend->close(sl); free(sl); } @@ -1021,26 +1049,28 @@ int stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); - if (ret == -1) - return ret; - return sl->backend->exit_debug_mode(sl); + if (ret == -1) { + return(ret); + } + + return(sl->backend->exit_debug_mode(sl)); } int stlink_enter_swd_mode(stlink_t *sl) { DLOG("*** stlink_enter_swd_mode ***\n"); - return sl->backend->enter_swd_mode(sl); + return(sl->backend->enter_swd_mode(sl)); } // Force the core into the debug mode -> halted state. int stlink_force_debug(stlink_t *sl) { DLOG("*** stlink_force_debug_mode ***\n"); - return sl->backend->force_debug(sl); + return(sl->backend->force_debug(sl)); } int stlink_exit_dfu_mode(stlink_t *sl) { DLOG("*** stlink_exit_dfu_mode ***\n"); - return sl->backend->exit_dfu_mode(sl); + return(sl->backend->exit_dfu_mode(sl)); } int stlink_core_id(stlink_t *sl) { @@ -1048,14 +1078,18 @@ int stlink_core_id(stlink_t *sl) { DLOG("*** stlink_core_id ***\n"); ret = sl->backend->core_id(sl); + if (ret == -1) { ELOG("Failed to read core_id\n"); - return ret; + return(ret); } - if (sl->verbose > 2) + + if (sl->verbose > 2) { stlink_print_data(sl); + } + DLOG("core_id = 0x%08x\n", sl->core_id); - return ret; + return(ret); } // stlink_chip_id() is called by stlink_load_device_params() @@ -1064,13 +1098,17 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { int ret; ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - if (ret == -1) - return ret; - if (*chip_id == 0) - ret = stlink_read_debug32(sl, 0x40015800, chip_id); //Try Corex M0 DBGMCU_IDCODE register address + if (ret == -1) { + return(ret); + } + + if (*chip_id == 0) { + // Try Corex M0 DBGMCU_IDCODE register address + ret = stlink_read_debug32(sl, 0x40015800, chip_id); + } - return ret; + return(ret); } /** @@ -1086,23 +1124,24 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { cpuid->variant = 0; cpuid->part = 0; cpuid->revision = 0; - return -1; + return(-1); } + cpuid->implementer_id = (raw >> 24) & 0x7f; cpuid->variant = (raw >> 20) & 0xf; cpuid->part = (raw >> 4) & 0xfff; cpuid->revision = raw & 0xf; - return 0; + return(0); } /** - * reads and decodes the flash parameters, as dynamically as possible + * Reads and decodes the flash parameters, as dynamically as possible * @param sl * @return 0 for success, or -1 for unsupported core type. */ int stlink_load_device_params(stlink_t *sl) { - // This seems to normally work so is unnecessary info for a normal - // user. Demoted to debug. -- REW + // This seems to normally work so is unnecessary info for a normal user. + // Demoted to debug. -- REW DLOG("Loading device parameters....\n"); const struct stlink_chipid_params *params = NULL; stlink_core_id(sl); @@ -1111,43 +1150,50 @@ int stlink_load_device_params(stlink_t *sl) { stlink_chip_id(sl, &chip_id); sl->chip_id = chip_id & 0xfff; - /* Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4*/ + + // Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4 if (sl->chip_id == 0x411) { uint32_t cpuid; stlink_read_debug32(sl, 0xE000ED00, &cpuid); - if ((cpuid & 0xfff0) == 0xc240) + + if ((cpuid & 0xfff0) == 0xc240) { sl->chip_id = 0x413; + } } params = stlink_chipid_get_params(sl->chip_id); + if (params == NULL) { WLOG("unknown chip id! %#x\n", chip_id); - return -1; + return(-1); } if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { WLOG("Invalid flash type, please check device declaration\n"); sl->flash_size = 0; - return 0; + return(0); } // These are fixed... sl->flash_base = STM32_FLASH_BASE; sl->sram_base = STM32_SRAM_BASE; - stlink_read_debug32(sl,(params->flash_size_reg) & ~3, &flash_size); - if (params->flash_size_reg & 2) - flash_size = flash_size >>16; + stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size); + + if (params->flash_size_reg & 2) { + flash_size = flash_size >> 16; + } + flash_size = flash_size & 0xffff; if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || - sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && ( flash_size == 0 )) { - sl->flash_size = 128 * 1024; + sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && (flash_size == 0)) { + sl->flash_size = 128 * 1024; } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { sl->flash_size = (flash_size & 0xff) * 1024; } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_HIGH) { // 0 is 384k and 1 is 256k - if ( flash_size == 0){ + if (flash_size == 0) { sl->flash_size = 384 * 1024; } else { sl->flash_size = 256 * 1024; @@ -1165,54 +1211,53 @@ int stlink_load_device_params(stlink_t *sl) { sl->option_base = params->option_base; sl->option_size = params->option_size; - //medium and low devices have the same chipid. ram size depends on flash size. - //STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024){ + // medium and low devices have the same chipid. ram size depends on flash size. + // STM32F100xx datasheet Doc ID 16455 Table 2 + if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024) { sl->sram_size = 0x1000; } if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { uint32_t flash_optr; stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); - if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { - sl->flash_pgsz <<= 1; - } + + if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { sl->flash_pgsz <<= 1; } } #if 0 // Old code -- REW ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); - // TODO make note of variable page size here..... + // TODO: make note of variable page size here..... ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %u bytes\n", - sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, - (unsigned int)sl->flash_pgsz); + sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, + (unsigned int)sl->flash_pgsz); #else ILOG("%s: %zd KiB SRAM, %zd KiB flash in at least %zd %s pages.\n", - params->description, sl->sram_size / 1024, sl->flash_size / 1024, - (sl->flash_pgsz < 1024)? sl->flash_pgsz : sl->flash_pgsz/1024, - (sl->flash_pgsz < 1024)? "byte" : "KiB"); + params->description, sl->sram_size / 1024, sl->flash_size / 1024, + (sl->flash_pgsz < 1024) ? sl->flash_pgsz : sl->flash_pgsz / 1024, + (sl->flash_pgsz < 1024) ? "byte" : "KiB"); #endif - return 0; + return(0); } int stlink_reset(stlink_t *sl) { DLOG("*** stlink_reset ***\n"); - return sl->backend->reset(sl); + return(sl->backend->reset(sl)); } int stlink_jtag_reset(stlink_t *sl, int value) { DLOG("*** stlink_jtag_reset ***\n"); - return sl->backend->jtag_reset(sl, value); + return(sl->backend->jtag_reset(sl, value)); } int stlink_run(stlink_t *sl) { DLOG("*** stlink_run ***\n"); - return sl->backend->run(sl); + return(sl->backend->run(sl)); } int stlink_set_swdclk(stlink_t *sl, uint16_t divisor) { DLOG("*** set_swdclk ***\n"); - return sl->backend->set_swdclk(sl, divisor); + return(sl->backend->set_swdclk(sl, divisor)); } int stlink_status(stlink_t *sl) { @@ -1221,8 +1266,7 @@ int stlink_status(stlink_t *sl) { DLOG("*** stlink_status ***\n"); ret = sl->backend->status(sl); stlink_core_stat(sl); - - return ret; + return(ret); } /** @@ -1232,13 +1276,14 @@ int stlink_status(stlink_t *sl) { */ void _parse_version(stlink_t *sl, stlink_version_t *slv) { sl->version.flags = 0; + if (sl->version.stlink_v < 3) { - uint32_t b0 = sl->q_buf[0]; //lsb + uint32_t b0 = sl->q_buf[0]; // lsb uint32_t b1 = sl->q_buf[1]; uint32_t b2 = sl->q_buf[2]; uint32_t b3 = sl->q_buf[3]; uint32_t b4 = sl->q_buf[4]; - uint32_t b5 = sl->q_buf[5]; //msb + uint32_t b5 = sl->q_buf[5]; // msb // b0 b1 || b2 b3 | b4 b5 // 4b | 6b | 6b || 2B | 2B @@ -1249,14 +1294,17 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { slv->swim_v = b1 & 0x3f; slv->st_vid = (b3 << 8) | b2; slv->stlink_pid = (b5 << 8) | b4; - /* ST-LINK/V1 from J11 switch to api-v2 (and support SWD) */ - if (slv->stlink_v == 1) - slv->jtag_api = slv->jtag_v > 11? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; - else { + + // ST-LINK/V1 from J11 switch to api-v2 (and support SWD) + if (slv->stlink_v == 1) { + slv->jtag_api = slv->jtag_v > 11 ? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; + } else { slv->jtag_api = STLINK_JTAG_API_V2; - /* preferred API to get last R/W status from J15 */ - if (sl->version.jtag_v >= 15) + + // preferred API to get last R/W status from J15 + if (sl->version.jtag_v >= 15) { sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + } } } else { // V3 uses different version format, for reference see OpenOCD source @@ -1271,13 +1319,16 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { /* preferred API to get last R/W status */ sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; } + return; } int stlink_version(stlink_t *sl) { DLOG("*** looking up stlink version\n"); - if (sl->backend->version(sl)) - return -1; + + if (sl->backend->version(sl)) { + return(-1); + } _parse_version(sl, &sl->version); @@ -1286,21 +1337,25 @@ int stlink_version(stlink_t *sl) { DLOG("stlink version = 0x%x\n", sl->version.stlink_v); DLOG("jtag version = 0x%x\n", sl->version.jtag_v); DLOG("swim version = 0x%x\n", sl->version.swim_v); + if (sl->version.jtag_v == 0) { DLOG(" notice: the firmware doesn't support a jtag/swd interface\n"); } + if (sl->version.swim_v == 0) { DLOG(" notice: the firmware doesn't support a swim interface\n"); } - return 0; + return(0); } int stlink_target_voltage(stlink_t *sl) { int voltage = -1; DLOG("*** reading target voltage\n"); + if (sl->backend->target_voltage != NULL) { voltage = sl->backend->target_voltage(sl); + if (voltage != -1) { DLOG("target voltage = %ldmV\n", voltage); } else { @@ -1309,66 +1364,76 @@ int stlink_target_voltage(stlink_t *sl) { } else { DLOG("reading voltage not supported by backend\n"); } - return voltage; + + return(voltage); } int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { int ret; ret = sl->backend->read_debug32(sl, addr, data); - if (!ret) + + if (!ret) { DLOG("*** stlink_read_debug32 %x is %#x\n", *data, addr); + } - return ret; + return(ret); } int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr); - return sl->backend->write_debug32(sl, addr, data); + return(sl->backend->write_debug32(sl, addr, data)); } int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); + if (len % 4 != 0) { - fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", + len % 4); abort(); } - return sl->backend->write_mem32(sl, addr, len); + + return(sl->backend->write_mem32(sl, addr, len)); } int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_read_mem32 ***\n"); + if (len % 4 != 0) { // !!! never ever: fw gives just wrong values fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); abort(); } - return sl->backend->read_mem32(sl, addr, len); + + return(sl->backend->read_mem32(sl, addr, len)); } int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem8 ***\n"); - if (len > 0x40){ // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour + + if (len > 0x40) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour fprintf(stderr, "Error: Data length > 64: +%d byte.\n", len); abort(); } - return sl->backend->write_mem8(sl, addr, len); + + return(sl->backend->write_mem8(sl, addr, len)); } int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("*** stlink_read_all_regs ***\n"); - return sl->backend->read_all_regs(sl, regp); + return(sl->backend->read_all_regs(sl, regp)); } int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("*** stlink_read_all_unsupported_regs ***\n"); - return sl->backend->read_all_unsupported_regs(sl, regp); + return(sl->backend->read_all_unsupported_regs(sl, regp)); } int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { DLOG("*** stlink_write_reg\n"); - return sl->backend->write_reg(sl, reg, idx); + return(sl->backend->write_reg(sl, reg, idx)); } int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { @@ -1377,10 +1442,10 @@ int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { if (r_idx > 20 || r_idx < 0) { fprintf(stderr, "Error: register index must be in [0..20]\n"); - return -1; + return(-1); } - return sl->backend->read_reg(sl, r_idx, regp); + return(sl->backend->read_reg(sl, r_idx, regp)); } int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { @@ -1390,18 +1455,18 @@ int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp DLOG(" (%d) ***\n", r_idx); /* Convert to values used by STLINK_REG_DCRSR */ - if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ + if (r_idx >= 0x1C && r_idx <= 0x1F) { // primask, basepri, faultmask, or control r_convert = 0x14; - } else if (r_idx == 0x40) { /* FPSCR */ + } else if (r_idx == 0x40) { // FPSCR r_convert = 0x21; } else if (r_idx >= 0x20 && r_idx < 0x40) { r_convert = 0x40 + (r_idx - 0x20); } else { fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return -1; + return(-1); } - return sl->backend->read_unsupported_reg(sl, r_convert, regp); + return(sl->backend->read_unsupported_reg(sl, r_convert, regp)); } int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct stlink_reg *regp) { @@ -1412,45 +1477,46 @@ int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct s /* Convert to values used by STLINK_REG_DCRSR */ if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ - r_convert = r_idx; /* The backend function handles this */ - } else if (r_idx == 0x40) { /* FPSCR */ + r_convert = r_idx; // the backend function handles this + } else if (r_idx == 0x40) { // FPSCR r_convert = 0x21; } else if (r_idx >= 0x20 && r_idx < 0x40) { r_convert = 0x40 + (r_idx - 0x20); } else { fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return -1; + return(-1); } - return sl->backend->write_unsupported_reg(sl, val, r_convert, regp); + return(sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); } -bool stlink_is_core_halted(stlink_t *sl) -{ +bool stlink_is_core_halted(stlink_t *sl) { stlink_status(sl); - return sl->core_stat == TARGET_HALTED; + return(sl->core_stat == TARGET_HALTED); } int stlink_step(stlink_t *sl) { DLOG("*** stlink_step ***\n"); - return sl->backend->step(sl); + return(sl->backend->step(sl)); } int stlink_current_mode(stlink_t *sl) { int mode = sl->backend->current_mode(sl); + switch (mode) { case STLINK_DEV_DFU_MODE: DLOG("stlink current mode: dfu\n"); - return mode; + return(mode); case STLINK_DEV_DEBUG_MODE: DLOG("stlink current mode: debug (jtag or swd)\n"); - return mode; + return(mode); case STLINK_DEV_MASS_MODE: DLOG("stlink current mode: mass\n"); - return mode; + return(mode); } + DLOG("stlink mode: unknown!\n"); - return STLINK_DEV_UNKNOWN_MODE; + return(STLINK_DEV_UNKNOWN_MODE); } @@ -1463,12 +1529,12 @@ int stlink_current_mode(stlink_t *sl) { unsigned int is_bigendian(void) { static volatile const unsigned int i = 1; - return *(volatile const char*) &i == 0; + return(*(volatile const char*)&i == 0); } uint16_t read_uint16(const unsigned char *c, const int pt) { uint32_t ui; - char *p = (char *) &ui; + char *p = (char *)&ui; if (!is_bigendian()) { // le -> le (don't swap) p[0] = c[pt + 0]; @@ -1477,18 +1543,17 @@ uint16_t read_uint16(const unsigned char *c, const int pt) { p[0] = c[pt + 1]; p[1] = c[pt + 0]; } - return ui; + + return(ui); } // same as above with entrypoint. void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { stlink_write_reg(sl, addr, 15); /* pc register */ - stlink_run(sl); - while (stlink_is_core_halted(sl)) - usleep(3000000); + while (stlink_is_core_halted(sl)) { usleep(3000000); } } @@ -1514,27 +1579,26 @@ void stlink_core_stat(stlink_t *sl) { } void stlink_print_data(stlink_t * sl) { - if (sl->q_len <= 0 || sl->verbose < UDEBUG) - return; - if (sl->verbose > 2) - DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); + if (sl->q_len <= 0 || sl->verbose < UDEBUG) { return; } + + if (sl->verbose > 2) { DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); } for (int i = 0; i < sl->q_len; i++) { if (i % 16 == 0) { - /* - if (sl->q_data_dir == Q_DATA_OUT) - fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); - else - fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); - */ + // if (sl->q_data_dir == Q_DATA_OUT) { + // fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); + // } else { + // fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); + // } } - DLOG(" %02x", (unsigned int) sl->q_buf[i]); + + DLOG(" %02x", (unsigned int)sl->q_buf[i]); } + DLOG("\n\n"); } -/* memory mapped file */ - +/* Memory mapped file */ typedef struct mapped_file { uint8_t* base; size_t len; @@ -1547,86 +1611,85 @@ static int map_file(mapped_file_t* mf, const char* path) { struct stat st; const int fd = open(path, O_RDONLY | O_BINARY); + if (fd == -1) { fprintf(stderr, "open(%s) == -1\n", path); - return -1; + return(-1); } if (fstat(fd, &st) == -1) { fprintf(stderr, "fstat(%s) == -1\n", path); goto on_error; } + if (sizeof(st.st_size) != sizeof(size_t)) { - /* On 32 bit systems, check if there is an overflow */ + // on 32 bit systems, check if there is an overflow if (st.st_size > (off_t)UINT32_MAX) { fprintf(stderr, "mmap() size_t overflow for file %s\n", path); goto on_error; } } - mf->base = (uint8_t*) mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); + + mf->base = (uint8_t*)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); + if (mf->base == MAP_FAILED) { fprintf(stderr, "mmap() == MAP_FAILED for file %s\n", path); goto on_error; } mf->len = st.st_size; - - /* success */ - error = 0; + error = 0; // success on_error: close(fd); - - return error; + return(error); } static void unmap_file(mapped_file_t * mf) { - munmap((void*) mf->base, mf->len); - mf->base = (unsigned char*) MAP_FAILED; + munmap((void*)mf->base, mf->len); + mf->base = (unsigned char*)MAP_FAILED; mf->len = 0; } -/* Limit the block size to compare to 0x1800 - Anything larger will stall the STLINK2 - Maybe STLINK V1 needs smaller value!*/ +/* Limit the block size to compare to 0x1800 as anything larger will stall the STLINK2 + * Maybe STLINK V1 needs smaller value! + */ static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) { size_t off; size_t n_cmp = sl->flash_pgsz; - if ( n_cmp > 0x1800) - n_cmp = 0x1800; + + if ( n_cmp > 0x1800) { n_cmp = 0x1800; } for (off = 0; off < mf->len; off += n_cmp) { size_t aligned_size; - /* adjust last page size */ - size_t cmp_size = n_cmp; - if ((off + n_cmp) > mf->len) - cmp_size = mf->len - off; + size_t cmp_size = n_cmp; // adjust last page size + + if ((off + n_cmp) > mf->len) { cmp_size = mf->len - off; } aligned_size = cmp_size; - if (aligned_size & (4 - 1)) - aligned_size = (cmp_size + 4) & ~(4 - 1); - stlink_read_mem32(sl, addr + (uint32_t) off, aligned_size); + if (aligned_size & (4 - 1)) { aligned_size = (cmp_size + 4) & ~(4 - 1); } + + stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); - if (memcmp(sl->q_buf, mf->base + off, cmp_size)) - return -1; + if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { return(-1); } } - return 0; + return(0); } static void md5_calculate(mapped_file_t *mf) { - /* calculate md5 checksum of given binary file */ - Md5Context md5Context; - MD5_HASH md5Hash; + // calculate md5 checksum of given binary file + Md5Context md5Context; + MD5_HASH md5Hash; Md5Initialise(&md5Context); Md5Update(&md5Context, mf->base, (uint32_t)mf->len); Md5Finalise(&md5Context, &md5Hash); printf("md5 checksum: "); - for (int i = 0; i < (int) sizeof(md5Hash); i++) { - printf("%x", md5Hash.bytes[i]); - } + + for (int i = 0; i < (int)sizeof(md5Hash); i++) { printf("%x", md5Hash.bytes[i]); } + printf(", "); } @@ -1634,31 +1697,31 @@ static void stlink_checksum(mapped_file_t *mp) { /* checksum that backward compatible with official ST tools */ uint32_t sum = 0; uint8_t *mp_byte = (uint8_t *)mp->base; - for (size_t i = 0; i < mp->len; ++i) { - sum += mp_byte[i]; - } + + for (size_t i = 0; i < mp->len; ++i) { sum += mp_byte[i]; } + printf("stlink checksum: 0x%08x\n", sum); } static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { unsigned int val; - /* set stack*/ + // set stack stlink_read_debug32(sl, addr, &val); stlink_write_reg(sl, val, 13); - /* Set PC to the reset routine*/ + // set PC to the reset routine stlink_read_debug32(sl, addr + 4, &val); stlink_write_reg(sl, val, 15); stlink_run(sl); } int stlink_mwrite_sram(stlink_t * sl, uint8_t* data, uint32_t length, stm32_addr_t addr) { - /* write the file in sram at addr */ + // write the file in sram at addr int error = -1; size_t off; size_t len; - /* check addr range is inside the sram */ + // check addr range is inside the sram if (addr < sl->sram_base) { fprintf(stderr, "addr too low\n"); goto on_error; @@ -1669,47 +1732,42 @@ int stlink_mwrite_sram(stlink_t * sl, uint8_t* data, uint32_t length, stm32_addr fprintf(stderr, "addr too high\n"); goto on_error; } else if (addr & 3) { - /* todo */ fprintf(stderr, "unaligned addr\n"); goto on_error; } len = length; - if (len & 3) { - len -= len & 3; - } + if (len & 3) { len -= len & 3; } - /* do the copy by 1k blocks */ + // do the copy by 1kB blocks for (off = 0; off < len; off += 1024) { size_t size = 1024; - if ((off + size) > len) - size = len - off; + + if ((off + size) > len) { size = len - off; } memcpy(sl->q_buf, data + off, size); - /* round size if needed */ - if (size & 3) - size += 2; + if (size & 3) { size += 2; } // round size if needed - stlink_write_mem32(sl, addr + (uint32_t) off, size); + stlink_write_mem32(sl, addr + (uint32_t)off, size); } if (length > len) { memcpy(sl->q_buf, data + len, length - len); - stlink_write_mem8(sl, addr + (uint32_t) len, length - len); + stlink_write_mem8(sl, addr + (uint32_t)len, length - len); } - /* success */ - error = 0; + + error = 0; // success stlink_fwrite_finalize(sl, addr); on_error: - return error; + return(error); } int stlink_fwrite_sram(stlink_t * sl, const char* path, stm32_addr_t addr) { - /* write the file in sram at addr */ + // write the file in sram at addr int error = -1; size_t off; @@ -1718,13 +1776,14 @@ int stlink_fwrite_sram(stlink_t * sl, const char* path, stm32_addr_t addr) { if (map_file(&mf, path) == -1) { fprintf(stderr, "map_file() == -1\n"); - return -1; + return(-1); } + printf("file %s ", path); md5_calculate(&mf); stlink_checksum(&mf); - /* check addr range is inside the sram */ + // check if addr range is inside the SRAM if (addr < sl->sram_base) { fprintf(stderr, "addr too low\n"); goto on_error; @@ -1735,88 +1794,80 @@ int stlink_fwrite_sram(stlink_t * sl, const char* path, stm32_addr_t addr) { fprintf(stderr, "addr too high\n"); goto on_error; } else if (addr & 3) { - /* todo */ fprintf(stderr, "unaligned addr\n"); goto on_error; } len = mf.len; - if (len & 3) { - len -= len & 3; - } + if (len & 3) { len -= len & 3; } - /* do the copy by 1k blocks */ + // do the copy by 1kB blocks for (off = 0; off < len; off += 1024) { size_t size = 1024; - if ((off + size) > len) - size = len - off; + + if ((off + size) > len) { size = len - off; } memcpy(sl->q_buf, mf.base + off, size); - /* round size if needed */ - if (size & 3) - size += 2; + if (size & 3) { size += 2; } // round size if needed - stlink_write_mem32(sl, addr + (uint32_t) off, size); + stlink_write_mem32(sl, addr + (uint32_t)off, size); } if (mf.len > len) { memcpy(sl->q_buf, mf.base + len, mf.len - len); - stlink_write_mem8(sl, addr + (uint32_t) len, mf.len - len); + stlink_write_mem8(sl, addr + (uint32_t)len, mf.len - len); } - /* check the file ha been written */ + // check the file has been written if (check_file(sl, &mf, addr) == -1) { fprintf(stderr, "check_file() == -1\n"); goto on_error; } - /* success */ - error = 0; + error = 0; // success stlink_fwrite_finalize(sl, addr); on_error: unmap_file(&mf); - return error; + return(error); } typedef bool (*save_block_fn)(void* arg, uint8_t* block, ssize_t len); -static int stlink_read(stlink_t* sl, stm32_addr_t addr, size_t size, save_block_fn fn, void* fn_arg) { +static int stlink_read( + stlink_t* sl, stm32_addr_t addr, size_t size, save_block_fn fn, void* fn_arg) { int error = -1; - if (size <1) - size = sl->flash_size; + if (size < 1) { size = sl->flash_size; } - if (size > sl->flash_size) + if (size > sl->flash_size) { size = sl->flash_size; + } + + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz; for (size_t off = 0; off < size; off += cmp_size) { size_t aligned_size; - /* adjust last page size */ - if ((off + cmp_size) > size) - cmp_size = size - off; + // adjust last page size + if ((off + cmp_size) > size) { cmp_size = size - off; } aligned_size = cmp_size; - if (aligned_size & (4 - 1)) - aligned_size = (cmp_size + 4) & ~(4 - 1); - stlink_read_mem32(sl, addr + (uint32_t) off, aligned_size); + if (aligned_size & (4 - 1)) { aligned_size = (cmp_size + 4) & ~(4 - 1); } - if (!fn(fn_arg, sl->q_buf, aligned_size)) { - goto on_error; - } + stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); + + if (!fn(fn_arg, sl->q_buf, aligned_size)) { goto on_error; } } - /* success */ - error = 0; + error = 0; // success on_error: - return error; + return(error); } struct stlink_fread_worker_arg { @@ -1825,12 +1876,12 @@ struct stlink_fread_worker_arg { static bool stlink_fread_worker(void* arg, uint8_t* block, ssize_t len) { struct stlink_fread_worker_arg* the_arg = (struct stlink_fread_worker_arg*)arg; + if (write(the_arg->fd, block, len) != len) { fprintf(stderr, "write() != aligned_size\n"); - return false; - } - else { - return true; + return(false); + } else { + return(true); } } @@ -1845,45 +1896,56 @@ struct stlink_fread_ihex_worker_arg { static bool stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg* the_arg) { uint32_t addr = the_arg->addr; uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + (uint8_t)((addr & 0x00FF0000) >> 16); - if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", (addr & 0xFFFF0000) >> 16, (uint8_t)(0x100 - sum))) - return false; - the_arg->lba = (addr & 0xFFFF0000); + if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", (addr & 0xFFFF0000) >> 16, + (uint8_t)(0x100 - sum))) { + return(false); + } - return true; + the_arg->lba = (addr & 0xFFFF0000); + return(true); } static bool stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg* the_arg) { uint8_t count = the_arg->buf_pos; - if (count == 0) return true; + + if (count == 0) { return(true); } uint32_t addr = the_arg->addr; if (the_arg->lba != (addr & 0xFFFF0000)) { // segment changed - if (!stlink_fread_ihex_newsegment(the_arg)) return false; + if (!stlink_fread_ihex_newsegment(the_arg)) { + return(false); + } } uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + (uint8_t)(addr & 0x000000FF); - if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) - return false; + + if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) { + return(false); + } for (uint8_t i = 0; i < count; ++i) { uint8_t b = the_arg->buf[i]; sum += b; - if (2 != fprintf(the_arg->file, "%02X", b)) - return false; + + if (2 != fprintf(the_arg->file, "%02X", b)) { + return(false); + } } - if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) - return false; + if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) { + return(false); + } the_arg->addr += count; the_arg->buf_pos = 0; - return true; + return(true); } -static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg* the_arg, int fd, stm32_addr_t addr) { +static bool stlink_fread_ihex_init( + struct stlink_fread_ihex_worker_arg* the_arg, int fd, stm32_addr_t addr) { the_arg->file = fdopen(fd, "w"); the_arg->addr = addr; the_arg->lba = 0; @@ -1897,109 +1959,127 @@ static bool stlink_fread_ihex_worker(void* arg, uint8_t* block, ssize_t len) { for (ssize_t i = 0; i < len; ++i) { if (the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full - if (!stlink_fread_ihex_writeline(the_arg)) return false; + if (!stlink_fread_ihex_writeline(the_arg)) { return(false); } } the_arg->buf[the_arg->buf_pos++] = block[i]; } - return true; + return(true); } static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg* the_arg) { - if (!stlink_fread_ihex_writeline(the_arg)) return false; + if (!stlink_fread_ihex_writeline(the_arg)) { return(false); } - // FIXME do we need the Start Linear Address? + // FIXME: do we need the Start Linear Address? - if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) // EoF - return false; + if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) { // EoF + return(false); + } return (0 == fclose(the_arg->file)); } int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size) { - /* read size bytes from addr to file */ + // read size bytes from addr to file int error; - int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); + if (fd == -1) { fprintf(stderr, "open(%s) == -1\n", path); - return -1; + return(-1); } if (is_ihex) { struct stlink_fread_ihex_worker_arg arg; + if (stlink_fread_ihex_init(&arg, fd, addr)) { error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); - if (!stlink_fread_ihex_finalize(&arg)) - error = -1; - } - else { + + if (!stlink_fread_ihex_finalize(&arg)) { error = -1; } + } else { error = -1; } - } - else { + } else { struct stlink_fread_worker_arg arg = { fd }; error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); } close(fd); - - return error; + return(error); } int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) { - /* write the buffer right after the loader */ + // write the buffer right after the loader size_t chunk = size & ~0x3; size_t rem = size & 0x3; + if (chunk) { memcpy(sl->q_buf, buf, chunk); stlink_write_mem32(sl, fl->buf_addr, chunk); } + if (rem) { - memcpy(sl->q_buf, buf+chunk, rem); - stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t) chunk, rem); + memcpy(sl->q_buf, buf + chunk, rem); + stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, rem); } - return 0; + + return(0); } -uint32_t calculate_F4_sectornum(uint32_t flashaddr){ +uint32_t calculate_F4_sectornum(uint32_t flashaddr) { uint32_t offset = 0; - flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address + flashaddr &= ~STM32_FLASH_BASE; // page now holding the actual flash address + if (flashaddr >= 0x100000) { offset = 12; flashaddr -= 0x100000; } - if (flashaddr<0x4000) return (offset + 0); - else if (flashaddr<0x8000) return(offset + 1); - else if (flashaddr<0xc000) return(offset + 2); - else if (flashaddr<0x10000) return(offset + 3); - else if (flashaddr<0x20000) return(offset + 4); - else return offset + (flashaddr/0x20000) +4; + + if (flashaddr < 0x4000) { + return (offset + 0); + } else if (flashaddr < 0x8000) { + return(offset + 1); + } else if (flashaddr < 0xc000) { + return(offset + 2); + } else if (flashaddr < 0x10000) { + return(offset + 3); + } else if (flashaddr < 0x20000) { + return(offset + 4); + } else { + return(offset + (flashaddr / 0x20000) + 4); + } } -uint32_t calculate_F7_sectornum(uint32_t flashaddr){ - flashaddr &= ~STM32_FLASH_BASE; //Page now holding the actual flash address - if (flashaddr<0x20000) return(flashaddr/0x8000); - else if (flashaddr<0x40000) return(4); - else return(flashaddr/0x40000) +4; +uint32_t calculate_F7_sectornum(uint32_t flashaddr) { + flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address + + if (flashaddr < 0x20000) { + return(flashaddr / 0x8000); + } else if (flashaddr < 0x40000) { + return(4); + } else { + return((flashaddr / 0x40000) + 4); + } } -// Returns BKER:PNB for the given page address +// returns BKER:PNB for the given page address uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { uint32_t bker = 0; uint32_t flashopt; stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); flashaddr -= STM32_FLASH_BASE; + if (sl->chip_id == STLINK_CHIPID_STM32_L4 || sl->chip_id == STLINK_CHIPID_STM32_L496X || sl->chip_id == STLINK_CHIPID_STM32_L4RX) { - // This chip use dual banked flash + // this chip use dual banked flash if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { - uint32_t banksize = (uint32_t) sl->flash_size / 2; + uint32_t banksize = (uint32_t)sl->flash_size / 2; + if (flashaddr >= banksize) { flashaddr -= banksize; bker = 0x100; @@ -2007,38 +2087,47 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { } } - // For 1MB chips without the dual-bank option set, the page address will - // overflow into the BKER bit, which gives us the correct bank:page value. - return bker | flashaddr/(uint32_t)sl->flash_pgsz; + // For 1MB chips without the dual-bank option set, the page address will overflow + // into the BKER bit, which gives us the correct bank:page value. + return(bker | flashaddr / (uint32_t)sl->flash_pgsz); } -uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ +uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || (sl->chip_id == STLINK_CHIPID_STM32_F4) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || - (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || - (sl->chip_id == STLINK_CHIPID_STM32_F446) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || - (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || - (sl->chip_id == STLINK_CHIPID_STM32_F412)) { - uint32_t sector=calculate_F4_sectornum(flashaddr); - if (sector>= 12) { - sector -= 12; + (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || + (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || + (sl->chip_id == STLINK_CHIPID_STM32_F446) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || + (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || + (sl->chip_id == STLINK_CHIPID_STM32_F412)) { + uint32_t sector = calculate_F4_sectornum(flashaddr); + + if (sector >= 12) { sector -= 12; } + + if (sector < 4) { + sl->flash_pgsz = 0x4000; + } else if (sector < 5) { + sl->flash_pgsz = 0x10000; + } else { + sl->flash_pgsz = 0x20000; + } + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || + sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { + uint32_t sector = calculate_F7_sectornum(flashaddr); + + if (sector < 4) { + sl->flash_pgsz = 0x8000; + } else if (sector < 5) { + sl->flash_pgsz = 0x20000; + } else { + sl->flash_pgsz = 0x40000; } - if (sector<4) sl->flash_pgsz=0x4000; - else if (sector<5) sl->flash_pgsz=0x10000; - else sl->flash_pgsz=0x20000; - } - else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { - uint32_t sector=calculate_F7_sectornum(flashaddr); - if (sector<4) sl->flash_pgsz=0x8000; - else if (sector<5) sl->flash_pgsz=0x20000; - else sl->flash_pgsz=0x40000; } - return (uint32_t) sl->flash_pgsz; + + return((uint32_t)sl->flash_pgsz); } /** @@ -2047,17 +2136,16 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ * @param flashaddr an address in the flash page to erase * @return 0 on success -ve on failure */ -int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) -{ +int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_L4) { - /* wait for ongoing op to finish */ + // wait for ongoing op to finish wait_flash_busy(sl); - /* unlock if locked */ + // unlock if locked unlock_flash_if(sl); - /* select the page to erase */ + // select the page to erase if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || (sl->chip_id == STLINK_CHIPID_STM32_L43X) || (sl->chip_id == STLINK_CHIPID_STM32_L46X) || @@ -2066,38 +2154,35 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); - fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, stlink_calculate_pagesize(sl, flashaddr)); + fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", + page, stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_bker_pnb(sl, page); } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { // calculate the actual page from the address - uint32_t sector=calculate_F7_sectornum(flashaddr); - - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); + uint32_t sector = calculate_F7_sectornum(flashaddr); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", + sector, stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_snb(sl, sector); } else { // calculate the actual page from the address - uint32_t sector=calculate_F4_sectornum(flashaddr); + uint32_t sector = calculate_F4_sectornum(flashaddr); - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", + sector, stlink_calculate_pagesize(sl, flashaddr)); - //the SNB values for flash sectors in the second bank do not directly follow the values for the first bank on 2mb devices... - if (sector >= 12) sector += 4; + // the SNB values for flash sectors in the second bank do not directly + // follow the values for the first bank on 2mb devices... + if (sector >= 12) { sector += 4; } write_flash_cr_snb(sl, sector); } - /* start erase operation */ - set_flash_cr_strt(sl); - - /* wait for completion */ - wait_flash_busy(sl); - - /* relock the flash */ - //todo: fails to program if this is in - lock_flash(sl); + set_flash_cr_strt(sl); // start erase operation + wait_flash_busy(sl); // wait for completion + lock_flash(sl); // TODO: fails to program if this is in #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); #endif @@ -2105,6 +2190,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) uint32_t val; uint32_t flash_regs_base; + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || @@ -2114,61 +2200,61 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) flash_regs_base = STM32L_FLASH_REGS_ADDR; } - /* check if the locks are set */ + // check if the locks are set stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if ((val & (1<<0))||(val & (1<<1))) { - /* disable pecr protection */ + + if ((val & (1 << 0)) || (val & (1 << 1))) { + // disable pecr protection stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); - /* check pecr.pelock is cleared */ + // check pecr.pelock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { WLOG("pecr.pelock not clear (%#x)\n", val); - return -1; + return(-1); } - /* unlock program memory */ + // unlock program memory stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); - /* check pecr.prglock is cleared */ + // check pecr.prglock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { WLOG("pecr.prglock not clear (%#x)\n", val); - return -1; + return(-1); } } - /* set pecr.{erase,prog} */ + // set pecr.{erase,prog} val |= (1 << 9) | (1 << 3); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); -#if 0 /* fix_to_be_confirmed */ - - /* wait for sr.busy to be cleared - * MP: Test shows that busy bit is not set here. Perhaps, PM0062 is - * wrong and we do not need to wait here for clearing the busy bit. - * TEXANE: ok, if experience says so and it works for you, we comment - * it. If someone has a problem, please drop an email. +#if 0 + /* Wait for sr.busy to be cleared + * MP: Test shows that busy bit is not set here. Perhaps, PM0062 is wrong + * and we do not need to wait here for clearing the busy bit. */ do { stlink_read_debug32(sl, STM32L_FLASH_SR, &val) } while ((val & (1 << 0)) != 0); +#endif -#endif /* fix_to_be_confirmed */ - - /* write 0 to the first word of the page to be erased */ + // write 0 to the first word of the page to be erased stlink_write_debug32(sl, flashaddr, 0); - /* MP: It is better to wait for clearing the busy bit after issuing - page erase command, even though PM0062 recommends to wait before it. - Test shows that a few iterations is performed in the following loop - before busy bit is cleared.*/ - do { + /* MP: It is better to wait for clearing the busy bit after issuing page + * erase command, even though PM0062 recommends to wait before it. + * Test shows that a few iterations is performed in the following loop + * before busy bit is cleared. + */ + do stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - } while ((val & (1 << 0)) != 0); + while ((val & (1 << 0)) != 0); - /* reset lock bits */ + // reset lock bits stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); @@ -2176,14 +2262,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { uint32_t val; - // Wait for any ongoing Flash operation to finish. - wait_flash_busy(sl); - // Unlock Flash if necessary. + wait_flash_busy(sl); // wait for any ongoing Flash operation to finish unlock_flash_if(sl); - // Set the 'enable Flash erase' bit. - set_flash_cr_per(sl); + set_flash_cr_per(sl); // set the 'enable Flash erase' bit - // Set the page to erase. + // set the page to erase if (sl->flash_type == STLINK_FLASH_TYPE_WB) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); @@ -2198,154 +2281,107 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. val &= ~(0x3F << 3); - val |= ((flash_page & 0x3F) << 3) | ( 1 << FLASH_CR_PER ); + val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. val &= ~(0x7F << 3); - val |= ((flash_page & 0x7F) << 3) | ( 1 << FLASH_CR_PER ); + val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); } - // Set the 'start operation' bit. - set_flash_cr_strt(sl); - // Wait for the 'busy' bit to clear. - wait_flash_busy(sl); - // Clear the 'enable page erase' bit. - clear_flash_cr_per(sl); - // Re-lock the flash. + set_flash_cr_strt(sl); // set the 'start operation' bit + wait_flash_busy(sl); // wait for the 'busy' bit to clear + clear_flash_cr_per(sl); // clear the 'enable page erase' bit lock_flash(sl); } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr < FLASH_BANK2_START_ADDR))) { - /* wait for ongoing op to finish */ + ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr < FLASH_BANK2_START_ADDR))) { wait_flash_busy(sl); - - /* unlock if locked */ unlock_flash_if(sl); - - /* clear the pg bit */ - clear_flash_cr_pg(sl); - - /* set the page erase bit */ - set_flash_cr_per(sl); - - /* select the page to erase */ - write_flash_ar(sl, flashaddr); - - /* start erase operation, reset by hw with bsy bit */ - set_flash_cr_strt(sl); - - /* wait for completion */ + clear_flash_cr_pg(sl); // clear the pg bit + set_flash_cr_per(sl); // set the page erase bit + write_flash_ar(sl, flashaddr); // select the page to erase + set_flash_cr_strt(sl); // start erase operation, reset by hw with busy bit wait_flash_busy(sl); - - /* relock the flash */ lock_flash(sl); } else if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr >= FLASH_BANK2_START_ADDR)) { - /* wait for ongoing op to finish */ wait_flash_busy(sl); - - /* unlock if locked */ unlock_flash_if(sl); - - /* set the page erase bit */ - set_flash_cr2_per(sl); - - /* select the page to erase */ - write_flash_ar2(sl, flashaddr); - - /* start erase operation, reset by hw with bsy bit */ - set_flash_cr2_strt(sl); - - /* wait for completion */ + set_flash_cr2_per(sl); // set the page erase bit + write_flash_ar2(sl, flashaddr); // select the page to erase + set_flash_cr2_strt(sl); // start erase operation, reset by hw with busy bit wait_flash_busy(sl); - - /* relock the flash */ lock_flash(sl); } else { WLOG("unknown coreid %x, page erase failed\n", sl->core_id); - return -1; + return(-1); } - /* todo: verify the erased page */ - - return 0; + // TODO: verify the erased page + return(0); } int stlink_erase_flash_mass(stlink_t *sl) { - /* TODO: User MER bit to mass-erase G0, G4, WB series. */ + // TODO: User MER bit to mass-erase G0, G4, WB series. if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_WB) { - /* erase each page */ - int i = 0, num_pages = (int)(sl->flash_size/sl->flash_pgsz); + // erase each page + int i = 0, num_pages = (int)(sl->flash_size / sl->flash_pgsz); + for (i = 0; i < num_pages; i++) { - /* addr must be an addr inside the page */ - stm32_addr_t addr = (stm32_addr_t) sl->flash_base + i * (stm32_addr_t) sl->flash_pgsz; + // addr must be an addr inside the page + stm32_addr_t addr = (stm32_addr_t)sl->flash_base + i * (stm32_addr_t)sl->flash_pgsz; + if (stlink_erase_flash_page(sl, addr) == -1) { WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr); - return -1; + return(-1); } - fprintf(stdout,"-> Flash page at %5d/%5d erased\n", i, num_pages); + + fprintf(stdout, "-> Flash page at %5d/%5d erased\n", i, num_pages); fflush(stdout); } + fprintf(stdout, "\n"); } else { - /* wait for ongoing op to finish */ wait_flash_busy(sl); - - /* unlock if locked */ unlock_flash_if(sl); - - /* set the mass erase bit */ - set_flash_cr_mer(sl,1); - - /* start erase operation, reset by hw with bsy bit */ - set_flash_cr_strt(sl); + set_flash_cr_mer(sl, 1); // set the mass erase bit + set_flash_cr_strt(sl); // start erase operation, reset by hw with busy bit if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - /* set the mass erase bit in bank 2 */ - set_flash_cr2_mer(sl,1); - - /* start erase operation in bank 2 */ - set_flash_cr2_strt(sl); + set_flash_cr2_mer(sl, 1); // set the mass erase bit in bank 2 + set_flash_cr2_strt(sl); // start erase operation in bank 2 } - /* wait for completion */ wait_flash_busy_progress(sl); - check_flash_error(sl); - - /* relock the flash */ lock_flash(sl); - /* reset the mass erase bit */ - set_flash_cr_mer(sl,0); + set_flash_cr_mer(sl, 0); // reset the mass erase bit if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - /* reset the mass erase bit in bank 2 */ - set_flash_cr2_mer(sl,0); + set_flash_cr2_mer(sl, 0); // reset the mass erase bit in bank 2 } - /* todo: verify the erased memory */ + // TODO: verify the erased memory } - return 0; + + return(0); } int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { - /* check the contents of path are at addr */ + // check the contents of path are at addr int res; mapped_file_t mf = MAPPED_FILE_INITIALIZER; - if (map_file(&mf, path) == -1) - return -1; + if (map_file(&mf, path) == -1) { return(-1); } res = check_file(sl, &mf, addr); - unmap_file(&mf); - - return res; + return(res); } /** @@ -2358,32 +2394,34 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { */ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) { size_t off; - size_t cmp_size = (sl->flash_pgsz > 0x1800)? 0x1800:sl->flash_pgsz; + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; ILOG("Starting verification of write complete\n"); + for (off = 0; off < length; off += cmp_size) { size_t aligned_size; - /* adjust last page size */ - if ((off + cmp_size) > length) - cmp_size = length - off; + // adjust last page size + if ((off + cmp_size) > length) { cmp_size = length - off; } aligned_size = cmp_size; - if (aligned_size & (4 - 1)) - aligned_size = (cmp_size + 4) & ~(4 - 1); - stlink_read_mem32(sl, address + (uint32_t) off, aligned_size); + if (aligned_size & (4 - 1)) { aligned_size = (cmp_size + 4) & ~(4 - 1); } + + stlink_read_mem32(sl, address + (uint32_t)off, aligned_size); if (memcmp(sl->q_buf, data + off, cmp_size)) { ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); - return -1; + return(-1); } } + ILOG("Flash written and verified! jolly good!\n"); - return 0; + return(0); } -int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize) { +int stm32l1_write_half_pages( + stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize) { unsigned int count; unsigned int num_half_pages = len / pagesize; uint32_t val; @@ -2400,215 +2438,223 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uin } ILOG("Starting Half page flash write for STM32L core id\n"); - /* flash loader initialization */ + + /* Flash loader initialisation */ if (stlink_flash_loader_init(sl, &fl) == -1) { WLOG("stlink_flash_loader_init() == -1\n"); - return -1; + return(-1); } - /* Unlock already done */ + + // unlock already done stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << FLASH_L1_FPRG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); val |= (1 << FLASH_L1_PROG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + do { stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); } while ((val & (1 << 0)) != 0); - for (count = 0; count < num_half_pages; count ++) { - if (stlink_flash_loader_run(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) { + for (count = 0; count < num_half_pages; count++) { + if (stlink_flash_loader_run( + sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) { WLOG("l1_stlink_flash_loader_run(%#zx) failed! == -1\n", addr + count * pagesize); stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~((1 << FLASH_L1_FPRG) |(1 << FLASH_L1_PROG)); + val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return -1; + return(-1); } - /* wait for sr.busy to be cleared */ + + // wait for sr.busy to be cleared if (sl->verbose >= 1) { - /* show progress. writing procedure is slow - and previous errors are misleading */ + // show progress; writing procedure is slow and previous errors are misleading fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); fflush(stdout); } + do { stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); } while ((val & (1 << 0)) != 0); } + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~(1 << FLASH_L1_PROG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~(1 << FLASH_L1_FPRG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - return 0; + return(0); } -int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint8_t eraseonly) { +int stlink_write_flash( + stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint8_t eraseonly) { size_t off; flash_loader_t fl; - ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", - len, len, addr, addr); - /* check addr range is inside the flash */ + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); + // check addr range is inside the flash stlink_calculate_pagesize(sl, addr); + if (addr < sl->flash_base) { ELOG("addr too low %#x < %#x\n", addr, sl->flash_base); - return -1; + return(-1); } else if ((addr + len) < addr) { ELOG("addr overruns\n"); - return -1; + return(-1); } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { ELOG("addr too high\n"); - return -1; + return(-1); } else if (addr & 1) { ELOG("unaligned addr 0x%x\n", addr); - return -1; + return(-1); } else if (len & 1) { WLOG("unaligned len 0x%x -- padding with zero\n", len); len += 1; } else if (addr & (sl->flash_pgsz - 1)) { - ELOG("addr not a multiple of current pagesize (%zd bytes), not supported, check page start address and compare with flash module organisation in related ST reference manual of your device.\n", sl->flash_pgsz); - return -1; + ELOG("addr not a multiple of current pagesize (%zd bytes), not supported, " + "check page start address and compare with flash module organisation " + "in related ST reference manual of your device.\n", sl->flash_pgsz); + return(-1); } - // Make sure we've loaded the context with the chip details + // make sure we've loaded the context with the chip details stlink_core_id(sl); - /* erase each page */ + + // Erase each page int page_count = 0; - for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + (uint32_t) off)) { + + for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + (uint32_t)off)) { // addr must be an addr inside the page - if (stlink_erase_flash_page(sl, addr + (uint32_t) off) == -1) { + if (stlink_erase_flash_page(sl, addr + (uint32_t)off) == -1) { ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); - return -1; + return(-1); } - ILOG("Flash page at addr: 0x%08lx erased\n", - (unsigned long)(addr + off)); + + ILOG("Flash page at addr: 0x%08lx erased\n", (unsigned long)(addr + off)); page_count++; } + ILOG("Finished erasing %d pages of %d (%#x) bytes\n", - page_count, sl->flash_pgsz, sl->flash_pgsz); + page_count, sl->flash_pgsz, sl->flash_pgsz); - if (eraseonly) - return 0; + if (eraseonly) { return(0); } if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_L4)) { - /* todo: check write operation */ + // TODO: check write operation ILOG("Starting Flash write for F2/F4/L4\n"); - /* flash loader initialization */ + + // Flash loader initialisation if (stlink_flash_loader_init(sl, &fl) == -1) { ELOG("stlink_flash_loader_init() == -1\n"); - return -1; + return(-1); } - /* First unlock the cr */ - unlock_flash_if(sl); + unlock_flash_if(sl); // first unlock the cr - /* TODO: Check that Voltage range is 2.7 - 3.6 V */ + // TODO: Check that Voltage range is 2.7 - 3.6 V if ((sl->chip_id != STLINK_CHIPID_STM32_L4) && (sl->chip_id != STLINK_CHIPID_STM32_L43X) && (sl->chip_id != STLINK_CHIPID_STM32_L46X) && (sl->chip_id != STLINK_CHIPID_STM32_L496X) && (sl->chip_id != STLINK_CHIPID_STM32_L4RX)) { - if ( sl->version.stlink_v == 1){ - printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes on F4 devices\n"); + if ( sl->version.stlink_v == 1) { + printf("STLINK V1 cannot read voltage, defaulting to 32-bit " + "writes on F4 devices\n"); write_flash_cr_psiz(sl, 2); - } - else { - /* set parallelisim to 32 bit*/ + } else { + // set parallelism to 32 bit int voltage = stlink_target_voltage(sl); + if (voltage == -1) { printf("Failed to read Target voltage\n"); - return voltage; + return(voltage); } else if (voltage > 2700) { printf("enabling 32-bit flash writes\n"); write_flash_cr_psiz(sl, 2); } else { - printf("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage); + printf("Target voltage (%d mV) too low for 32-bit flash, " + "using 8-bit flash writes\n", voltage); write_flash_cr_psiz(sl, 0); } } } else { - /* L4 does not have a byte-write mode */ + // L4 does not have a byte-write mode int voltage = stlink_target_voltage(sl); + if (voltage == -1) { printf("Failed to read Target voltage\n"); - return voltage; + return(voltage); } else if (voltage < 1710) { printf("Target voltage (%d mV) too low for flash writes!\n", voltage); - return -1; + return(-1); } } - /* set programming mode */ + // set programming mode set_flash_cr_pg(sl); size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; + for (off = 0; off < len;) { size_t size = len - off > buf_size ? buf_size : len - off; - printf("size: %u\n", (unsigned int)size); - if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t) off, base + off, size) == -1) { + if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); - return -1; + return(-1); } off += size; } - /* Relock flash */ clear_flash_cr_pg(sl); lock_flash(sl); - } //STM32F4END - else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + // STM32F4END + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { fprintf(stdout, "Writing\r\n"); fflush(stdout); - // Wait for any ongoing operations to finish. wait_flash_busy(sl); - // Unlock flash if necessary. - unlock_flash_if(sl); - // Set PG 'allow programming' bit. - set_flash_cr_pg(sl); - // Write all words. + unlock_flash_if(sl); // unlock flash if necessary + set_flash_cr_pg(sl); // set PG 'allow programming' bit + // write all words. off = 0; - fprintf(stdout, "Starting %3u page write\r\n", (unsigned int)(len/sl->flash_pgsz)); + fprintf(stdout, "Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); fflush(stdout); + for ( ; off < len; off += sizeof(uint32_t)) { uint32_t data; - if (off > 254) - fprintf(stdout, "\r"); - if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { + if (off > 254) { fprintf(stdout, "\r"); } + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off/sl->flash_pgsz), - (unsigned int)(len/sl->flash_pgsz)); + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); fflush(stdout); } - write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); - stlink_write_debug32(sl, addr + (uint32_t) off, data); - // Wait for 'busy' bit in FLASH_SR to clear. - wait_flash_busy(sl); + + write_uint32((unsigned char*)&data, *(uint32_t*)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } - // (Flash writes happen 2 words at a time.) + + // flash writes happen as 2 words at a time if ((off / sizeof(uint32_t)) % 2 != 0) { - // Write a single word of zeros. - stlink_write_debug32(sl, addr + (uint32_t) off, 0); - // Wait for 'busy' bit in FLASH_SR to clear. - wait_flash_busy(sl); + stlink_write_debug32(sl, addr + (uint32_t)off, 0); // write a single word of zeros + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } - // Reset PG bit. - clear_flash_cr_pg(sl); - // Re-lock flash. + + clear_flash_cr_pg(sl); // reset PG bit. lock_flash(sl); - } - else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - /* use fast word write. todo: half page. */ + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + // use fast word write + // TODO: half page uint32_t val; uint32_t flash_regs_base; uint32_t pagesize; @@ -2624,123 +2670,144 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t pagesize = L1_WRITE_BLOCK_SIZE; } - /* todo: check write operation */ + // TODO: check write operation - /* disable pecr protection */ + // disable pecr protection stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); - /* check pecr.pelock is cleared */ + // check pecr.pelock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { fprintf(stderr, "pecr.pelock not clear\n"); - return -1; + return(-1); } - /* unlock program memory */ + // unlock program memory stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); - /* check pecr.prglock is cleared */ + // check pecr.prglock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { fprintf(stderr, "pecr.prglock not clear\n"); - return -1; + return(-1); } + off = 0; + if (len > pagesize) { if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) { - /* This may happen on a blank device! */ + // this may happen on a blank device! WLOG("\nwrite_half_pages failed == -1\n"); } else { - off = (len / pagesize)*pagesize; + off = (len / pagesize) * pagesize; } } - /* write remainingword in program memory */ + // write remaining word in program memory for ( ; off < len; off += sizeof(uint32_t)) { uint32_t data; - if (off > 254) - fprintf(stdout, "\r"); - if ((off % sl->flash_pgsz) > (sl->flash_pgsz -5)) { + if (off > 254) { fprintf(stdout, "\r"); } + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off/sl->flash_pgsz), - (unsigned int)(len/sl->flash_pgsz)); + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); fflush(stdout); } - write_uint32((unsigned char*) &data, *(uint32_t*) (base + off)); - stlink_write_debug32(sl, addr + (uint32_t) off, data); + write_uint32((unsigned char*)&data, *(uint32_t*)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); - /* wait for sr.busy to be cleared */ + // wait for sr.busy to be cleared do { stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); } while ((val & (1 << 0)) != 0); - /* todo: check redo write operation */ - + // TODO: check redo write operation } + fprintf(stdout, "\n"); - /* reset lock bits */ + // reset lock bits stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { ILOG("Starting Flash write for VL/F0/F3/F1_XL core id\n"); - /* flash loader initialization */ + + // flash loader initialisation if (stlink_flash_loader_init(sl, &fl) == -1) { ELOG("stlink_flash_loader_init() == -1\n"); - return -1; + return(-1); } int write_block_count = 0; + for (off = 0; off < len; off += sl->flash_pgsz) { - /* adjust last write size */ + // adjust last write size size_t size = sl->flash_pgsz; - if ((off + sl->flash_pgsz) > len) size = len - off; - /* unlock and set programming mode */ + if ((off + sl->flash_pgsz) > len) { size = len - off; } + + // unlock and set programming mode unlock_flash_if(sl); - if (sl->flash_type != STLINK_FLASH_TYPE_F1_XL) { - set_flash_cr_pg(sl); - } + + if (sl->flash_type != STLINK_FLASH_TYPE_F1_XL) { set_flash_cr_pg(sl); } + DLOG("Finished unlocking flash, running loader!\n"); - if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t) off, base + off, size) == -1) { + + if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); - return -1; + return(-1); } + lock_flash(sl); + if (sl->verbose >= 1) { - /* show progress. writing procedure is slow - and previous errors are misleading */ - fprintf(stdout, "\r%3u/%lu pages written", ++write_block_count, (unsigned long)((len+sl->flash_pgsz-1)/sl->flash_pgsz)); + // show progress; writing procedure is slow and previous errors are misleading + fprintf(stdout, "\r%3u/%lu pages written", ++write_block_count, + (unsigned long)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); fflush(stdout); } } + fprintf(stdout, "\n"); } else { ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); - return -1; + return(-1); } - return stlink_verify_write_flash(sl, addr, base, len); + return(stlink_verify_write_flash(sl, addr, base, len)); } -// note: length not checked +// TODO: length not checked static uint8_t stlink_parse_hex(const char* hex) { uint8_t d[2]; + for (int i = 0; i < 2; ++i) { char c = *(hex + i); - if (c >= '0' && c <= '9') d[i] = c - '0'; - else if (c >= 'A' && c <= 'F') d[i] = c - 'A' + 10; - else if (c >= 'a' && c <= 'f') d[i] = c - 'a' + 10; - else return 0; // error + + if (c >= '0' && c <= '9') { + d[i] = c - '0'; + } else if (c >= 'A' && c <= 'F') { + d[i] = c - 'A' + 10; + } else if (c >= 'a' && c <= 'f') { + d[i] = c - 'a' + 10; + } else { + return(0); // error + } } - return (d[0] << 4) | (d[1]); + + return((d[0] << 4) | (d[1])); } -int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin) { +int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, + uint32_t * begin) { int res = 0; *begin = UINT32_MAX; uint8_t* data = NULL; @@ -2764,6 +2831,7 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, *size = (end - *begin) + 1; data = calloc(*size, 1); // use calloc to get NULL if out of memory + if (!data) { ELOG("Cannot allocate %d bytes\n", *size); res = -1; @@ -2774,6 +2842,7 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, } FILE* file = fopen(path, "r"); + if (!file) { ELOG("Cannot open file\n"); res = -1; @@ -2781,10 +2850,11 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, } uint32_t lba = 0; + char line[1 + 5 * 2 + 255 * 2 + 2]; - char line[1 + 5*2 + 255*2 + 2]; while (fgets(line, sizeof(line), file)) { - if (line[0] == '\n' || line[0] == '\r') continue; // skip empty lines + if (line[0] == '\n' || line[0] == '\r') { continue; } // skip empty lines + if (line[0] != ':') { // no marker - wrong file format ELOG("Wrong file format - no marker\n"); res = -1; @@ -2792,18 +2862,19 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, } size_t l = strlen(line); - while (l > 0 && (line[l-1] == '\n' || line[l-1] == '\r')) --l; // trim EoL - if ((l < 11) || (l == (sizeof(line)-1))) { // line too short or long - wrong file format + + while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { --l; } // trim EoL + + if ((l < 11) || (l == (sizeof(line) - 1))) { // line too short or long - wrong file format ELOG("Wrong file format - wrong line length\n"); res = -1; break; } - // check sum - uint8_t chksum = 0; - for (size_t i = 1; i < l; i += 2) { - chksum += stlink_parse_hex(line + i); - } + uint8_t chksum = 0; // check sum + + for (size_t i = 1; i < l; i += 2) { chksum += stlink_parse_hex(line + i); } + if (chksum != 0) { ELOG("Wrong file format - checksum mismatch\n"); res = -1; @@ -2811,64 +2882,61 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, } uint8_t reclen = stlink_parse_hex(line + 1); - if (((uint32_t)reclen + 5)*2 + 1 != l) { + + if (((uint32_t)reclen + 5) * 2 + 1 != l) { ELOG("Wrong file format - record length mismatch\n"); res = -1; break; } - uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | ((uint16_t)stlink_parse_hex(line + 5)); - uint8_t rectype = stlink_parse_hex(line + 7); - - switch(rectype) { - case 0: // data - if (scan == 0) { - uint32_t b = lba + offset; - uint32_t e = b + reclen - 1; - if (b < *begin) *begin = b; - if (e > end) end = e; - } - else { - for (uint8_t i = 0; i < reclen; ++i) { - uint8_t b = stlink_parse_hex(line + 9 + i*2); - uint32_t addr = lba + offset + i; - if (addr >= *begin && addr <= end) { - data[addr - *begin] = b; - } - } - } - break; + uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | + ((uint16_t)stlink_parse_hex(line + 5)); + uint8_t rectype = stlink_parse_hex(line + 7); - case 1: // EoF - eof_found = true; - break; + switch (rectype) { + case 0: /* Data */ + if (scan == 0) { + uint32_t b = lba + offset; + uint32_t e = b + reclen - 1; - case 2: // Extended Segment Address, unexpected - res = -1; - break; + if (b < *begin) { *begin = b; } - case 3: // Start Segment Address, unexpected - res = -1; - break; + if (e > end) { end = e; } + } else { + for (uint8_t i = 0; i < reclen; ++i) { + uint8_t b = stlink_parse_hex(line + 9 + i * 2); + uint32_t addr = lba + offset + i; - case 4: // Extended Linear Address - if (reclen == 2) { - lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | ((uint32_t)stlink_parse_hex(line + 11) << 16); - } - else { - ELOG("Wrong file format - wrong LBA length\n"); - res = -1; + if (addr >= *begin && addr <= end) { data[addr - *begin] = b; } } - break; - - case 5: // Start Linear Address - expected, but ignore - break; - - default: - ELOG("Wrong file format - unexpected record type %d\n", rectype); + } + break; + case 1: /* EoF */ + eof_found = true; + break; + case 2: /* Extended Segment Address, unexpected */ + res = -1; + break; + case 3: /* Start Segment Address, unexpected */ + res = -1; + break; + case 4: /* Extended Linear Address */ + if (reclen == 2) { + lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | + ((uint32_t)stlink_parse_hex(line + 11) << 16); + } else { + ELOG("Wrong file format - wrong LBA length\n"); res = -1; + } + break; + case 5: /* Start Linear Address - expected, but ignore */ + break; + default: + ELOG("Wrong file format - unexpected record type %d\n", rectype); + res = -1; } - if (res != 0) break; + + if (res != 0) { break; } } fclose(file); @@ -2876,55 +2944,56 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, if (res == 0) { *mem = data; - } - else { + } else { free(data); } - return res; + return(res); } uint8_t stlink_get_erased_pattern(stlink_t *sl) { - if (sl->flash_type == STLINK_FLASH_TYPE_L0) - return 0x00; - else - return 0xff; + if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + return(0x00); + } else { + return(0xff); + } } int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr) { - /* write the block in flash at addr */ + /* Write the block in flash at addr */ int err; unsigned int num_empty, idx; uint8_t erased_pattern = stlink_get_erased_pattern(sl); /* - * This optimization may cause unexpected garbage data remaining - * Turned off by default + * This optimisation may cause unexpected garbage data remaining. + * Therfore it is turned off by default. */ if (sl->opt) { idx = (unsigned int)length; - for (num_empty = 0; num_empty != length; ++num_empty) { - if (data[--idx] != erased_pattern) { - break; - } - } - /* Round down to words */ - num_empty -= (num_empty & 3); + + for (num_empty = 0; num_empty != length; ++num_empty) + if (data[--idx] != erased_pattern) { break; } + + num_empty -= (num_empty & 3); // Round down to words + if (num_empty != 0) { ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); } } else { num_empty = 0; } + /* - * TODO: investigate: - * a kind of weird behaviour here: - * if the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. */ - err = stlink_write_flash(sl, addr, data, (num_empty == length) ? (uint32_t) length : (uint32_t) length - num_empty, num_empty == length); + err = stlink_write_flash(sl, addr, data, + (num_empty == length) ? (uint32_t)length : (uint32_t)length - num_empty, + num_empty == length); stlink_fwrite_finalize(sl, addr); - return err; + return(err); } /** @@ -2935,7 +3004,7 @@ int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr * @return 0 on success, -ve on failure. */ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { - /* write the file in flash at addr */ + /* Write the file in flash at addr */ int err; unsigned int num_empty, idx; uint8_t erased_pattern = stlink_get_erased_pattern(sl); @@ -2943,7 +3012,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { if (map_file(&mf, path) == -1) { ELOG("map_file() == -1\n"); - return -1; + return(-1); } printf("file %s ", path); @@ -2951,30 +3020,32 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { stlink_checksum(&mf); if (sl->opt) { - idx = (unsigned int) mf.len; + idx = (unsigned int)mf.len; + for (num_empty = 0; num_empty != mf.len; ++num_empty) { - if (mf.base[--idx] != erased_pattern) { - break; - } + if (mf.base[--idx] != erased_pattern) { break; } } - /* Round down to words */ - num_empty -= (num_empty & 3); + + num_empty -= (num_empty & 3); // round down to words + if (num_empty != 0) { ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); } } else { num_empty = 0; } + /* - * TODO: investigate: - * a kind of weird behaviour here: - * if the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. */ - err = stlink_write_flash(sl, addr, mf.base, (num_empty == mf.len) ? (uint32_t) mf.len : (uint32_t) mf.len - num_empty, num_empty == mf.len); + err = stlink_write_flash(sl, addr, mf.base, + (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty, + num_empty == mf.len); stlink_fwrite_finalize(sl, addr); unmap_file(&mf); - return err; + return(err); } /** @@ -2984,20 +3055,19 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - +static int stlink_write_option_bytes_gx( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { + /* Write options bytes */ uint32_t val; int ret = 0; - (void) len; - - /* Write options bytes */ + (void)len; uint32_t data; - write_uint32((unsigned char*) &data, *(uint32_t*) (base)); - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + write_uint32((unsigned char*)&data, *(uint32_t*)(base)); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); - /* Set Options Start bit */ + // Set Options Start bit stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); @@ -3006,12 +3076,12 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_ ret = check_flash_error(sl); - /* Reload options */ + // Reload options stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - return ret; + return(ret); } /** @@ -3021,38 +3091,36 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t* base, stm32_addr_ * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_l0( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t flash_base = get_stm32l0_flash_base(sl); uint32_t val; uint32_t data; int ret = 0; - /* Clear errors */ + // Clear errors stlink_write_debug32(sl, flash_base + FLASH_SR_OFF, STM32L0_FLASH_REGS_ADDR); while (len != 0) { - /* Write options bytes */ - write_uint32((unsigned char*) &data, *(uint32_t*) (base)); + write_uint32((unsigned char*)&data, *(uint32_t*)(base)); // write options bytes WLOG("Writing option bytes %#10x to %#10x\n", data, addr); stlink_write_debug32(sl, addr, data); - wait_flash_busy(sl); - if ((ret = check_flash_error(sl))) - break; + if ((ret = check_flash_error(sl))) { break; } - len-=4; - addr+=4; - base+=4; + len -= 4; + addr += 4; + base += 4; } - /* Reload options */ + // Reload options stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); val |= (1 << STM32L0_FLASH_OBL_LAUNCH); stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); - return ret; + return(ret); } /** @@ -3062,36 +3130,34 @@ static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t* base, stm32_addr_ * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_l4( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t val; int ret = 0; + (void)addr; + (void)len; - (void) addr; - (void) len; - - /* Write options bytes */ + // write options bytes uint32_t data; - write_uint32((unsigned char*) &data, *(uint32_t*) (base)); + write_uint32((unsigned char*)&data, *(uint32_t*)(base)); WLOG("Writing option bytes 0x%04x\n", data); stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); - /* Set Options Start bit */ + // set options start bit stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); val |= (1 << STM32L4_FLASH_CR_OPTSTRT); stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - /* Wait for 'busy' bit in FLASH_SR to clear. */ wait_flash_busy(sl); - ret = check_flash_error(sl); - /* apply options bytes immediate */ + // apply options bytes immediate stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - return ret; + return(ret); } @@ -3101,25 +3167,24 @@ static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t* base, stm32_addr_ * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_f4( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { uint32_t option_byte; int ret = 0; + (void)addr; + (void)len; - (void) addr; - (void) len; - - write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); + write_uint32((unsigned char*)&option_byte, *(uint32_t*)(base)); - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F4_OPTCR, (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | (1 << FLASH_F4_OPTCR_START)); + // write option byte, ensuring we dont lock opt, and set strt bit + stlink_write_debug32(sl, FLASH_F4_OPTCR, + (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | (1 << FLASH_F4_OPTCR_START)); wait_flash_busy(sl); - ret = check_flash_error(sl); - /* option bytes are reloaded at reset only, no obl. */ - - return ret; + // option bytes are reloaded at reset only, no obl. */ + return(ret); } /** @@ -3129,7 +3194,7 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_ * @return 0 on success, -ve on failure. */ int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); + return(stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte)); } /** @@ -3139,7 +3204,7 @@ int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) { * @return 0 on success, -ve on failure. */ int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); + return(stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte)); } /** @@ -3149,16 +3214,16 @@ int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { * @return 0 on success, -ve on failure. */ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); + return(stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte)); } /** * Read first option bytes -* @param sl -* @param option_byte option value -* @return 0 on success, -ve on failure. -*/ + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_debug32(sl, sl->option_base, option_byte); + return(stlink_read_debug32(sl, sl->option_base, option_byte)); } /** @@ -3170,21 +3235,21 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) { if (sl->option_base == 0) { ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; + return(-1); } switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: - return stlink_read_option_bytes_f2(sl, option_byte); - case STLINK_CHIPID_STM32_F446: - return stlink_read_option_bytes_f4(sl, option_byte); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: - return stlink_read_option_bytes_Gx(sl, option_byte); - default: - return stlink_read_option_bytes_generic(sl, option_byte); + case STLINK_CHIPID_STM32_F2: + return(stlink_read_option_bytes_f2(sl, option_byte)); + case STLINK_CHIPID_STM32_F446: + return(stlink_read_option_bytes_f4(sl, option_byte)); + case STLINK_CHIPID_STM32_G0_CAT1: + case STLINK_CHIPID_STM32_G0_CAT2: + case STLINK_CHIPID_STM32_G4_CAT2: + case STLINK_CHIPID_STM32_G4_CAT3: + return(stlink_read_option_bytes_Gx(sl, option_byte)); + default: + return(stlink_read_option_bytes_generic(sl, option_byte)); } } @@ -3196,7 +3261,7 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) { */ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { WLOG("About to write option byte %#10x to target.\n", option_byte); - return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *) &option_byte, 4); + return(stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, 4)); } /** @@ -3211,60 +3276,60 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui if (sl->option_base == 0) { ELOG("Option bytes writing is currently not supported for connected chip\n"); - return -1; + return(-1); } if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { ELOG("Option bytes start address out of Option bytes range\n"); - return -1; + return(-1); } if (addr + len > sl->option_base + sl->option_size) { ELOG("Option bytes data too long\n"); - return -1; + return(-1); } wait_flash_busy(sl); if (unlock_flash_if(sl)) { ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; + return(-1); } if (unlock_flash_option_if(sl)) { ELOG("Flash option unlock failed!\n"); - return -1; + return(-1); } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F4: - ret = stlink_write_option_bytes_f4(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_L0: - ret = stlink_write_option_bytes_l0(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_L4: - ret = stlink_write_option_bytes_l4(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - ret = stlink_write_option_bytes_gx(sl, base, addr, len); - break; - default: - ELOG("Option bytes writing is currently not implemented for connected chip\n"); - break; + case STLINK_FLASH_TYPE_F4: + ret = stlink_write_option_bytes_f4(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_L0: + ret = stlink_write_option_bytes_l0(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_L4: + ret = stlink_write_option_bytes_l4(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + ret = stlink_write_option_bytes_gx(sl, base, addr, len); + break; + default: + ELOG("Option bytes writing is currently not implemented for connected chip\n"); + break; } - if (ret) + if (ret) { ELOG("Flash option write failed!\n"); - else - ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + } else { + ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + } - /* Re-lock flash. */ lock_flash_option(sl); lock_flash(sl); - return ret; + return(ret); } /** @@ -3275,21 +3340,22 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui * @return 0 on success, -ve on failure. */ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr) { - /* write the file in flash at addr */ + /* Write the file in flash at addr */ int err; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { ELOG("map_file() == -1\n"); - return -1; + return(-1); } printf("file %s ", path); md5_calculate(&mf); stlink_checksum(&mf); - err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t) mf.len); + err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); stlink_fwrite_finalize(sl, addr); unmap_file(&mf); - return err; + + return(err); } diff --git a/src/reg.h b/src/reg.h deleted file mode 100644 index 765ac9525..000000000 --- a/src/reg.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef STLINK_REG_H_ -#define STLINK_REG_H_ - -#define STLINK_REG_CM3_CPUID 0xE000ED00 -#define STLINK_REG_CM3_FP_CTRL 0xE0002000 -#define STLINK_REG_CM3_FP_COMP0 0xE0002008 - -/* Cortex™-M3 Technical Reference Manual */ -/* Debug Halting Control and Status Register */ -#define STLINK_REG_DHCSR 0xe000edf0 -#define STLINK_REG_DHCSR_DBGKEY 0xa05f0000 -#define STLINK_REG_DCRSR 0xe000edf4 -#define STLINK_REG_DCRDR 0xe000edf8 - -/* Application Interrupt and Reset Control Register */ -#define STLINK_REG_AIRCR 0xe000ed0c -#define STLINK_REG_AIRCR_VECTKEY 0x05fa0000 -#define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004 - -#endif /* STLINK_REG_H_ */ diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index fc62bcf15..43378965c 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -1,4 +1,4 @@ -/* simple wrapper around the stlink_flash_write function */ +/* Simple wrapper around the stlink_flash_write function */ // TODO - this should be done as just a simple flag to the st-util command line... @@ -16,8 +16,7 @@ static stlink_t *connected_stlink = NULL; static void cleanup(int signum) { (void)signum; - if (connected_stlink) { - /* Switch back to mass storage mode before closing. */ + if (connected_stlink) { // switch back to mass storage mode before closing stlink_run(connected_stlink); stlink_exit_debug_mode(connected_stlink); stlink_close(connected_stlink); @@ -26,8 +25,7 @@ static void cleanup(int signum) { exit(1); } -static void usage(void) -{ +static void usage(void) { puts("command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] {read|write} [addr] [size]"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] erase"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); @@ -39,37 +37,34 @@ static void usage(void) puts("example read option byte: ./st-flash --debug --reset --area=option read > option_byte"); } -int main(int ac, char** av) -{ +int main(int ac, char** av) { stlink_t* sl = NULL; struct flash_opts o; int err = -1; uint8_t * mem = NULL; o.size = 0; - if (flash_get_opts(&o, ac - 1, av + 1) == -1) - { + + if (flash_get_opts(&o, ac - 1, av + 1) == -1) { printf("invalid command line\n"); usage(); - return -1; + return(-1); } printf("st-flash %s\n", STLINK_VERSION); sl = stlink_open_usb(o.log_level, 1, (char *)o.serial, o.freq); - if (sl == NULL) { - return -1; - } + if (sl == NULL) { return(-1); } if (sl->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { printf("Failed to connect to target\n"); - return -1; + return(-1); } if ( o.flash_size != 0u && o.flash_size != sl->flash_size ) { sl->flash_size = o.flash_size; - printf("Forcing flash size: --flash=0x%08X\n",(unsigned int)sl->flash_size); + printf("Forcing flash size: --flash=0x%08X\n", (unsigned int)sl->flash_size); } sl->verbose = o.log_level; @@ -94,7 +89,7 @@ int main(int ac, char** av) } } - if (o.reset){ + if (o.reset) { if (sl->version.stlink_v > 1) { if (stlink_jtag_reset(sl, 2)) { printf("Failed to reset JTAG\n"); @@ -108,19 +103,19 @@ int main(int ac, char** av) } } - // Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 - if (sl->chip_id == STLINK_CHIPID_STM32_F4) - { - memset(sl->q_buf,0,4); - for (int i=0;i<8;i++) { - stlink_write_mem32(sl,0x40026000+0x10+0x18*i,4); - stlink_write_mem32(sl,0x40026400+0x10+0x18*i,4); - stlink_write_mem32(sl,0x40026000+0x24+0x18*i,4); - stlink_write_mem32(sl,0x40026400+0x24+0x18*i,4); + // disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 + if (sl->chip_id == STLINK_CHIPID_STM32_F4) { + memset(sl->q_buf, 0, 4); + + for (int i = 0; i < 8; i++) { + stlink_write_mem32(sl, 0x40026000 + 0x10 + 0x18 * i, 4); + stlink_write_mem32(sl, 0x40026400 + 0x10 + 0x18 * i, 4); + stlink_write_mem32(sl, 0x40026000 + 0x24 + 0x18 * i, 4); + stlink_write_mem32(sl, 0x40026400 + 0x24 + 0x18 * i, 4); } } - // Core must be halted to use RAM based flashloaders + // core must be halted to use RAM based flashloaders if (stlink_force_debug(sl)) { printf("Failed to halt the core\n"); goto on_error; @@ -131,77 +126,75 @@ int main(int ac, char** av) goto on_error; } - if (o.cmd == FLASH_CMD_WRITE) /* write */ - { + if (o.cmd == FLASH_CMD_WRITE) { // write size_t size = 0; + if (o.format == FLASH_FORMAT_IHEX) { err = stlink_parse_ihex(o.filename, stlink_get_erased_pattern(sl), &mem, &size, &o.addr); + if (err == -1) { printf("Cannot parse %s as Intel-HEX file\n", o.filename); goto on_error; } } + if ((o.addr >= sl->flash_base) && - (o.addr < sl->flash_base + sl->flash_size)) { - if (o.format == FLASH_FORMAT_IHEX) + (o.addr < sl->flash_base + sl->flash_size)) { + if (o.format == FLASH_FORMAT_IHEX) { err = stlink_mwrite_flash(sl, mem, (uint32_t)size, o.addr); - else + } else { err = stlink_fwrite_flash(sl, o.filename, o.addr); - if (err == -1) - { + } + + if (err == -1) { printf("stlink_fwrite_flash() == -1\n"); goto on_error; } - } - else if ((o.addr >= sl->sram_base) && - (o.addr < sl->sram_base + sl->sram_size)) { - if (o.format == FLASH_FORMAT_IHEX) + } else if ((o.addr >= sl->sram_base) && + (o.addr < sl->sram_base + sl->sram_size)) { + if (o.format == FLASH_FORMAT_IHEX) { err = stlink_mwrite_sram(sl, mem, (uint32_t)size, o.addr); - else + } else { err = stlink_fwrite_sram(sl, o.filename, o.addr); - if (err == -1) - { + } + + if (err == -1) { printf("stlink_fwrite_sram() == -1\n"); goto on_error; } - } - else if ((o.addr >= sl->option_base) && - (o.addr < sl->option_base + sl->option_size)) { + } else if ((o.addr >= sl->option_base) && + (o.addr < sl->option_base + sl->option_size)) { err = stlink_fwrite_option_bytes(sl, o.filename, o.addr); - if (err == -1) - { + + if (err == -1) { printf("stlink_fwrite_option_bytes() == -1\n"); goto on_error; } - } - else if (o.area == FLASH_OPTION_BYTES){ + } else if (o.area == FLASH_OPTION_BYTES) { if (o.val == 0) { printf("attempting to set option byte to 0, abort.\n"); goto on_error; - } + } err = stlink_write_option_bytes32(sl, o.val); - if (err == -1) - { + + if (err == -1) { printf("stlink_write_option_bytes32() == -1\n"); goto on_error; } - } - else { + } else { err = -1; printf("Unknown memory region\n"); goto on_error; } - } else if (o.cmd == FLASH_CMD_ERASE) - { + } else if (o.cmd == FLASH_CMD_ERASE) { err = stlink_erase_flash_mass(sl); - if (err == -1) - { + + if (err == -1) { printf("stlink_erase_flash_mass() == -1\n"); goto on_error; } - } else if (o.cmd == CMD_RESET) - { + } else if (o.cmd == CMD_RESET) { if (sl->version.stlink_v > 1) { if (stlink_jtag_reset(sl, 2)) { printf("Failed to reset JTAG\n"); @@ -213,49 +206,47 @@ int main(int ac, char** av) printf("Failed to reset device\n"); goto on_error; } - } - else /* read */ - { - if(o.area == FLASH_OPTION_BYTES){ - uint32_t option_byte; - err = stlink_read_option_bytes32(sl, &option_byte); - if (err == -1) { - printf("could not read option bytes (%d)\n", err); - goto on_error; - } else { - printf("%x\n",option_byte); + } else { // read + if (o.area == FLASH_OPTION_BYTES) { + uint32_t option_byte; + err = stlink_read_option_bytes32(sl, &option_byte); + + if (err == -1) { + printf("could not read option bytes (%d)\n", err); + goto on_error; + } else { + printf("%x\n", option_byte); } - }else{ + } else { if ((o.addr >= sl->flash_base) && (o.size == 0) && - (o.addr < sl->flash_base + sl->flash_size)){ + (o.addr < sl->flash_base + sl->flash_size)) { o.size = sl->flash_size; - } - else if ((o.addr >= sl->sram_base) && (o.size == 0) && - (o.addr < sl->sram_base + sl->sram_size)){ + } else if ((o.addr >= sl->sram_base) && (o.size == 0) && + (o.addr < sl->sram_base + sl->sram_size)) { o.size = sl->sram_size; } + err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); - if (err == -1) - { + if (err == -1) { printf("stlink_fread() == -1\n"); goto on_error; } } } - if (o.reset){ - if (sl->version.stlink_v > 1) stlink_jtag_reset(sl, 2); + if (o.reset) { + if (sl->version.stlink_v > 1) { stlink_jtag_reset(sl, 2); } + stlink_reset(sl); } - /* success */ - err = 0; + err = 0; // success on_error: stlink_exit_debug_mode(sl); stlink_close(sl); free(mem); - return err; + return(err); } diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index 3a4dc3ec4..0b7555188 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -11,9 +11,8 @@ enum flash_cmd {FLASH_CMD_NONE = 0, FLASH_CMD_WRITE = 1, FLASH_CMD_READ = 2, FLASH_CMD_ERASE = 3, CMD_RESET = 4}; enum flash_format {FLASH_FORMAT_BINARY = 0, FLASH_FORMAT_IHEX = 1}; -enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1,FLASH_OTP = 2, FLASH_OPTION_BYTES = 3}; -struct flash_opts -{ +enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1, FLASH_OTP = 2, FLASH_OPTION_BYTES = 3}; +struct flash_opts { enum flash_cmd cmd; uint8_t serial[STLINK_SERIAL_MAX_SIZE]; const char* filename; @@ -24,9 +23,9 @@ struct flash_opts enum flash_format format; enum flash_area area; uint32_t val; - size_t flash_size; /* --flash=n[k][m] */ - int opt; /* enable empty tail data drop optimization */ - int freq; /* --freq=n[k][m] frequency of JTAG/SWD */ + size_t flash_size; // --flash=n[k][m] + int opt; // enable empty tail data drop optimization + int freq; // --freq=n[k][m] frequency of JTAG/SWD bool connect_under_reset; }; diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 9d8d3225b..6d1940675 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -6,7 +6,8 @@ static bool starts_with(const char * str, const char * prefix) { size_t n = strlen(prefix); - if (strlen(str) < n) return false; + + if (strlen(str) < n) { return(false); } return (0 == strncmp(str, prefix, n)); } @@ -19,37 +20,28 @@ static int get_long_integer_from_char_array (const char *const str, uint64_t *re uint64_t value; char *tail; - // hexadecimal - if (starts_with (str, "0x") || starts_with (str, "0X")) { + if (starts_with (str, "0x") || starts_with (str, "0X")) { // hexadecimal value = strtoul (str + 2, &tail, 16); - } - // binary - else if (starts_with (str, "0b") || starts_with (str, "0B")) { + } else if (starts_with (str, "0b") || starts_with (str, "0B")) { // binary value = strtoul (str + 2, &tail, 2); - } - // octal - else if (starts_with (str, "0")) { + } else if (starts_with (str, "0")) { // octal value = strtoul (str + 1, &tail, 8); - } - // decimal - else { + } else { // decimal value = strtoul (str, &tail, 10); } if (((tail[0] == 'k') || (tail[0] == 'K')) && (tail[1] == '\0')) { value = value * 1024; - } - else if (((tail[0] == 'm') || (tail[0] == 'M')) && (tail[1] == '\0')) { + } else if (((tail[0] == 'm') || (tail[0] == 'M')) && (tail[1] == '\0')) { value = value * 1024 * 1024; + } else if (tail[0] == '\0') { + /* value not changed */ + } else { + return(-1); } - else if (tail[0] == '\0') { - // value not change - } - else { - return -1; - } + *read_value = value; - return 0; + return(0); } // support positive integer from 0 to UINT32_MAX @@ -59,28 +51,26 @@ static int get_long_integer_from_char_array (const char *const str, uint64_t *re static int get_integer_from_char_array (const char *const str, uint32_t *read_value) { uint64_t value; int result = get_long_integer_from_char_array (str, &value); + if (result != 0) { - return result; - } - else if (value > UINT32_MAX) { - fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, \ -cannot convert to int32_t\n"); - return -1; - } - else { + return(result); + } else if (value > UINT32_MAX) { + fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, cannot convert to int32_t\n"); + return(-1); + } else { *read_value = (uint32_t)value; - return 0; + return(0); } } static int invalid_args(const char *expected) { fprintf(stderr, "*** Error: Expected args for this command: %s\n", expected); - return -1; + return(-1); } static int bad_arg(const char *arg) { fprintf(stderr, "*** Error: Invalid value for %s\n", arg); - return -1; + return(-1); } int flash_get_opts(struct flash_opts* o, int ac, char** av) { @@ -91,170 +81,177 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { // options int result; + while (ac >= 1) { if (strcmp(av[0], "--version") == 0) { printf("v%s\n", STLINK_VERSION); exit(EXIT_SUCCESS); - } - else if (strcmp(av[0], "--debug") == 0) { + } else if (strcmp(av[0], "--debug") == 0) { o->log_level = DEBUG_LOG_LEVEL; - } - else if (strcmp(av[0], "--opt") == 0) { + } else if (strcmp(av[0], "--opt") == 0) { o->opt = ENABLE_OPT; - } - else if (strcmp(av[0], "--reset") == 0) { + } else if (strcmp(av[0], "--reset") == 0) { o->reset = 1; - } - else if (strcmp(av[0], "--serial") == 0 || starts_with(av[0], "--serial=")) { + } else if (strcmp(av[0], "--serial") == 0 || starts_with(av[0], "--serial=")) { const char * serial; + if (strcmp(av[0], "--serial") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { return(-1); } + serial = av[0]; - } - else { + } else { serial = av[0] + strlen("--serial="); } - /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ + + /** @todo This is not really portable, as strlen really returns size_t we need to obey + and not cast it to a signed type. */ int j = (int)strlen(serial); - int length = j / 2; // the length of the destination-array - if (j % 2 != 0) return -1; + int length = j / 2; // the length of the destination-array + + if (j % 2 != 0) { return(-1); } + for (size_t k = 0; j >= 0 && k < sizeof(o->serial); ++k, j -= 2) { char buffer[3] = {0}; memcpy(buffer, serial + j, 2); o->serial[length - k] = (uint8_t)strtol(buffer, NULL, 16); } - } - else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { + } else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { const char * area; + if (strcmp(av[0], "--area") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { return(-1); } + area = av[0]; - } - else { + } else { area = av[0] + strlen("--area="); } - if (strcmp(area, "main") == 0) + + if (strcmp(area, "main") == 0) { o->area = FLASH_MAIN_MEMORY; - else if (strcmp(area, "system") == 0) + } else if (strcmp(area, "system") == 0) { o->area = FLASH_SYSTEM_MEMORY; - else if (strcmp(area, "otp") == 0) + } else if (strcmp(area, "otp") == 0) { o->area = FLASH_OTP; - else if (strcmp(area, "option") == 0) + } else if (strcmp(area, "option") == 0) { o->area = FLASH_OPTION_BYTES; - else - return -1; + } else { + return(-1); + } - } - else if (strcmp(av[0], "--freq") == 0 || starts_with(av[0], "--freq=")) { + } else if (strcmp(av[0], "--freq") == 0 || starts_with(av[0], "--freq=")) { const char* freq; + if (strcmp(av[0], "--freq") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { + return(-1); + } + freq = av[0]; - } - else { + } else { freq = av[0] + strlen("--freq="); } + if (strcmp(freq, "5K") == 0 || strcmp(freq, "5k") == 0) { o->freq = 5; - } - else if (strcmp(freq, "15K") == 0 || strcmp(freq, "15k") == 0) { + } else if (strcmp(freq, "15K") == 0 || strcmp(freq, "15k") == 0) { o->freq = 15; - } - else if (strcmp(freq, "25K") == 0 || strcmp(freq, "25k") == 0) { + } else if (strcmp(freq, "25K") == 0 || strcmp(freq, "25k") == 0) { o->freq = 25; - } - else if (strcmp(freq, "50K") == 0 || strcmp(freq, "50k") == 0) { + } else if (strcmp(freq, "50K") == 0 || strcmp(freq, "50k") == 0) { o->freq = 50; - } - else if (strcmp(freq, "100K") == 0 || strcmp(freq, "100k") == 0) { + } else if (strcmp(freq, "100K") == 0 || strcmp(freq, "100k") == 0) { o->freq = 100; - } - else if (strcmp(freq, "125K") == 0 || strcmp(freq, "125k") == 0) { + } else if (strcmp(freq, "125K") == 0 || strcmp(freq, "125k") == 0) { o->freq = 125; - } - else if (strcmp(freq, "240K") == 0 || strcmp(freq, "240k") == 0) { + } else if (strcmp(freq, "240K") == 0 || strcmp(freq, "240k") == 0) { o->freq = 240; - } - else if (strcmp(freq, "480K") == 0 || strcmp(freq, "480k") == 0) { + } else if (strcmp(freq, "480K") == 0 || strcmp(freq, "480k") == 0) { o->freq = 480; - } - else if (strcmp(freq, "950K") == 0 || strcmp(freq, "950k") == 0) { + } else if (strcmp(freq, "950K") == 0 || strcmp(freq, "950k") == 0) { o->freq = 950; - } - else if (strcmp(freq, "1200K") == 0 || strcmp(freq, "1200k") == 0 || strcmp(freq, "1.2M") == 0 || strcmp(freq, "1.2m") == 0) { + } else if (strcmp(freq, "1200K") == 0 || strcmp(freq, "1200k") == 0 || + strcmp(freq, "1.2M") == 0 || strcmp(freq, "1.2m") == 0) { o->freq = 1200; - } - else if (strcmp(freq, "1800K") == 0 || strcmp(freq, "1800k") == 0 || strcmp(freq, "1.8M") == 0 || strcmp(freq, "1.8m") == 0) { + } else if (strcmp(freq, "1800K") == 0 || strcmp(freq, "1800k") == 0 || + strcmp(freq, "1.8M") == 0 || strcmp(freq, "1.8m") == 0) { o->freq = 1800; - } - else if (strcmp(freq, "4000K") == 0 || strcmp(freq, "4000k") == 0 || strcmp(freq, "4M") == 0 || strcmp(freq, "4m") == 0) { + } else if (strcmp(freq, "4000K") == 0 || strcmp(freq, "4000k") == 0 || + strcmp(freq, "4M") == 0 || strcmp(freq, "4m") == 0) { o->freq = 4000; + } else { + return(-1); } - else - return -1; - } - else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { + } else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { const char * format; + if (strcmp(av[0], "--format") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { return(-1); } + format = av[0]; - } - else { + } else { format = av[0] + strlen("--format="); } - if (strcmp(format, "binary") == 0) + + if (strcmp(format, "binary") == 0) { o->format = FLASH_FORMAT_BINARY; - else if (strcmp(format, "ihex") == 0) + } else if (strcmp(format, "ihex") == 0) { o->format = FLASH_FORMAT_IHEX; - else - return bad_arg("format"); - } - else if ( starts_with(av[0], "--flash=") ) { + } else { + return(bad_arg("format")); + } + } else if ( starts_with(av[0], "--flash=")) { const char *arg = av[0] + strlen("--flash="); uint32_t flash_size; result = get_integer_from_char_array(arg, &flash_size); - if (result != 0) return bad_arg ("--flash"); - else o->flash_size = (size_t) flash_size; - } - else if (strcmp(av[0],"--connect-under-reset")== 0){ + + if (result != 0) { + return(bad_arg ("--flash")); + } else { + o->flash_size = (size_t)flash_size; + } + } else if (strcmp(av[0], "--connect-under-reset") == 0) { o->connect_under_reset = true; - } - else { - break; // non-option found + } else { + break; // non-option found + } ac--; av++; } - // command and (optional) device name + /* command and (optional) device name */ while (ac >= 1) { if (strcmp(av[0], "erase") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + if (o->cmd != FLASH_CMD_NONE) { return(-1); } + o->cmd = FLASH_CMD_ERASE; - } - else if (strcmp(av[0], "read") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + } else if (strcmp(av[0], "read") == 0) { + if (o->cmd != FLASH_CMD_NONE) { return(-1); } + o->cmd = FLASH_CMD_READ; - } - else if (strcmp(av[0], "write") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + } else if (strcmp(av[0], "write") == 0) { + if (o->cmd != FLASH_CMD_NONE) { return(-1); } + o->cmd = FLASH_CMD_WRITE; - } - else if (strcmp(av[0], "reset") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + } else if (strcmp(av[0], "reset") == 0) { + if (o->cmd != FLASH_CMD_NONE) { return(-1); } + o->cmd = CMD_RESET; - } - else { + } else { break; } @@ -262,60 +259,83 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { av++; } - switch(o->cmd) { - case FLASH_CMD_NONE: // no command found - return -1; + switch (o->cmd) { + case FLASH_CMD_NONE: // no command found + return(-1); - case FLASH_CMD_ERASE: // no more arguments expected - if (ac != 0) return -1; - break; + case FLASH_CMD_ERASE: // no more arguments expected - case FLASH_CMD_READ: // expect filename, addr and size - if ((o->area == FLASH_OPTION_BYTES) &&(ac == 0)) break; - if (ac != 3) return invalid_args("read "); - if (ac != 3) return -1; - o->filename = av[0]; - uint32_t address; - result = get_integer_from_char_array(av[1], &address); - if (result != 0) return bad_arg ("addr"); - else o->addr = (stm32_addr_t) address; + if (ac != 0) { return(-1); } - uint32_t size; - result = get_integer_from_char_array(av[2], &size); - if (result != 0) return bad_arg ("size"); - else o->size = (size_t) size; + break; - break; + case FLASH_CMD_READ: // expect filename, addr and size - case FLASH_CMD_WRITE: - if (o->area == FLASH_OPTION_BYTES){ - if (ac != 1) return -1; + if ((o->area == FLASH_OPTION_BYTES) && (ac == 0)) { break; } - uint32_t val; - result = get_integer_from_char_array(av[0], &val); - if (result != 0) return bad_arg ("val"); - else o->val = (uint32_t) val; + if (ac != 3) { return(invalid_args("read ")); } + if (ac != 3) { return(-1); } + + o->filename = av[0]; + uint32_t address; + result = get_integer_from_char_array(av[1], &address); + + if (result != 0) { + return(bad_arg ("addr")); + } else { + o->addr = (stm32_addr_t)address; + } + + uint32_t size; + result = get_integer_from_char_array(av[2], &size); + + if (result != 0) { + return(bad_arg ("size")); + } else { + o->size = (size_t)size; + } + + break; + + case FLASH_CMD_WRITE: + + if (o->area == FLASH_OPTION_BYTES) { + if (ac != 1) { return(-1); } + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + + if (result != 0) { + return(bad_arg ("val")); + } else { + o->val = (uint32_t)val; } - else if (o->format == FLASH_FORMAT_BINARY) { // expect filename and addr - if (ac != 2) return invalid_args("write "); - o->filename = av[0]; - uint32_t addr; - result = get_integer_from_char_array(av[1], &addr); - if (result != 0) return bad_arg ("addr"); - else o->addr = (stm32_addr_t) addr; - } - else if (o->format == FLASH_FORMAT_IHEX) { // expect filename - if (ac != 1) return invalid_args("write "); - o->filename = av[0]; - } - else { - return -1; // should have been caught during format parsing + + } else if (o->format == FLASH_FORMAT_BINARY) { // expect filename and addr + if (ac != 2) { return(invalid_args("write ")); } + + o->filename = av[0]; + uint32_t addr; + result = get_integer_from_char_array(av[1], &addr); + + if (result != 0) { + return(bad_arg ("addr")); + } else { + o->addr = (stm32_addr_t)addr; } - break; + } else if (o->format == FLASH_FORMAT_IHEX) { // expect filename + if (ac != 1) { return(invalid_args("write ")); } + + o->filename = av[0]; + } else { + return(-1); // should have been caught during format parsing + } + + break; - default: break ; + default: break; } - return 0; + return(0); } diff --git a/src/st-info/info.c b/src/st-info/info.c index 8464d8632..1bc48a05e 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -5,8 +5,7 @@ #include -static void usage(void) -{ +static void usage(void) { puts("st-info --version"); puts("st-info --probe"); puts("st-info --serial"); @@ -19,31 +18,32 @@ static void usage(void) } /* Print normal or OpenOCD hla_serial with newline */ -static void stlink_print_serial(stlink_t *sl, bool openocd) -{ +static void stlink_print_serial(stlink_t *sl, bool openocd) { const char *fmt; if (openocd) { - printf("\""); - fmt = "\\x%02x"; + printf("\""); + fmt = "\\x%02x"; } else { - fmt = "%02x"; + fmt = "%02x"; } for (int n = 0; n < sl->serial_size; n++) printf(fmt, sl->serial[n]); - if (openocd) - printf("\""); + if (openocd) { + printf("\""); + } + printf("\n"); } -static void stlink_print_info(stlink_t *sl) -{ +static void stlink_print_info(stlink_t *sl) { const struct stlink_chipid_params *params = NULL; - if (!sl) + if (!sl) { return; + } printf(" serial: "); stlink_print_serial(sl, false); @@ -51,18 +51,17 @@ static void stlink_print_info(stlink_t *sl) stlink_print_serial(sl, true); printf(" flash: %u (pagesize: %u)\n", - (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); + (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); printf(" sram: %u\n", (unsigned int)sl->sram_size); printf(" chipid: 0x%.4x\n", sl->chip_id); - params = stlink_chipid_get_params(sl->chip_id); - if (params) - printf(" descr: %s\n", params->description); + params = stlink_chipid_get_params(sl->chip_id); + + if (params) { printf(" descr: %s\n", params->description); } } -static void stlink_probe(void) -{ +static void stlink_probe(void) { stlink_t **stdevs; size_t size; @@ -70,16 +69,15 @@ static void stlink_probe(void) printf("Found %u stlink programmers\n", (unsigned int)size); - for (size_t n = 0; n < size; n++) - stlink_print_info(stdevs[n]); + for (size_t n = 0; n < size; n++) stlink_print_info(stdevs[n]); stlink_probe_usb_free(&stdevs, size); } -static stlink_t *stlink_open_first(bool under_reset) -{ +static stlink_t *stlink_open_first(bool under_reset) { stlink_t* sl = NULL; sl = stlink_v1_open(0, 1); + if (sl == NULL) { if (under_reset) { sl = stlink_open_usb(0, 2, NULL, 0); @@ -87,84 +85,79 @@ static stlink_t *stlink_open_first(bool under_reset) sl = stlink_open_usb(0, 1, NULL, 0); } } - - return sl; + + return(sl); } -static int print_data(int ac, char **av) -{ +static int print_data(int ac, char **av) { stlink_t* sl = NULL; bool under_reset = false; - // Probe needs all devices unclaimed + // probe needs all devices unclaimed if (strcmp(av[1], "--probe") == 0) { stlink_probe(); - return 0; + return(0); } else if (strcmp(av[1], "--version") == 0) { printf("v%s\n", STLINK_VERSION); - return 0; + return(0); } if (ac == 3) { - if (strcmp(av[2],"--connect-under-reset") == 0) { + if (strcmp(av[2], "--connect-under-reset") == 0) { under_reset = true; } else { usage(); - return -1; + return(-1); } } sl = stlink_open_first(under_reset); - if (sl == NULL) { - return -1; - } + if (sl == NULL) { return(-1); } sl->verbose = 0; - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) - stlink_exit_dfu_mode(sl); + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { stlink_exit_dfu_mode(sl); } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) - stlink_enter_swd_mode(sl); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } - if (strcmp(av[1], "--serial") == 0) + if (strcmp(av[1], "--serial") == 0) { stlink_print_serial(sl, false); - else if (strcmp(av[1], "--hla-serial") == 0) + } else if (strcmp(av[1], "--hla-serial") == 0) { stlink_print_serial(sl, true); - else if (strcmp(av[1], "--flash") == 0) + } else if (strcmp(av[1], "--flash") == 0) { printf("0x%x\n", (unsigned int)sl->flash_size); - else if (strcmp(av[1], "--pagesize") == 0) + } else if (strcmp(av[1], "--pagesize") == 0) { printf("0x%x\n", (unsigned int)sl->flash_pgsz); - else if (strcmp(av[1], "--sram") == 0) + } else if (strcmp(av[1], "--sram") == 0) { printf("0x%x\n", (unsigned int)sl->sram_size); - else if (strcmp(av[1], "--chipid") == 0) + } else if (strcmp(av[1], "--chipid") == 0) { printf("0x%.4x\n", sl->chip_id); - else if (strcmp(av[1], "--descr") == 0) { + } else if (strcmp(av[1], "--descr") == 0) { const struct stlink_chipid_params *params = stlink_chipid_get_params(sl->chip_id); - if (params == NULL) - return -1; + + if (params == NULL) { return(-1); } + printf("%s\n", params->description); } - if (sl) - { + if (sl) { stlink_exit_debug_mode(sl); stlink_close(sl); } - return 0; + return(0); } -int main(int ac, char** av) -{ +int main(int ac, char** av) { int err = -1; + if (ac < 2) { usage(); - return -1; + return(-1); } - err = print_data(ac,av); + err = print_data(ac, av); - return err; + return(err); } diff --git a/src/st-util/gdb-remote.c b/src/st-util/gdb-remote.c index 04729cc75..bdf8afd24 100644 --- a/src/st-util/gdb-remote.c +++ b/src/st-util/gdb-remote.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Peter Zotov + * Copyright (c) 2011 Peter Zotov * Use of this source code is governed by a BSD-style license that can be found in the LICENSE file. */ @@ -20,7 +20,7 @@ static const char hex[] = "0123456789abcdef"; int gdb_send_packet(int fd, char* data) { - unsigned int data_length = (unsigned int) strlen(data); + unsigned int data_length = (unsigned int)strlen(data); int length = data_length + 4; char* packet = malloc(length); // '$' data (hex) '#' cksum (hex) @@ -29,6 +29,7 @@ int gdb_send_packet(int fd, char* data) { packet[0] = '$'; uint8_t cksum = 0; + for (unsigned int i = 0; i < data_length; i++) { packet[i + 1] = data[i]; cksum += data[i]; @@ -41,18 +42,19 @@ int gdb_send_packet(int fd, char* data) { while (1) { if (write(fd, packet, length) != length) { free(packet); - return -2; + return(-2); } char ack; + if (read(fd, &ack, 1) != 1) { free(packet); - return -2; + return(-2); } if (ack == '+') { free(packet); - return 0; + return(0); } } } @@ -66,7 +68,9 @@ int gdb_recv_packet(int fd, char** buffer) { char* packet_buffer = malloc(packet_size); unsigned state; - if (packet_buffer == NULL) return -2; + if (packet_buffer == NULL) { + return(-2); + } start: state = 0; @@ -80,18 +84,25 @@ int gdb_recv_packet(int fd, char** buffer) { */ char c; + while (state != 4) { if (read(fd, &c, 1) != 1) { free(packet_buffer); - return -2; + return(-2); } - switch(state) { + switch (state) { case 0: - if (c != '$') { /* ignore */ } else { state = 1; } + + if (c != '$') { /* ignore */ + } else { + state = 1; + } + break; case 1: + if (c == '#') { state = 2; } else { @@ -101,14 +112,16 @@ int gdb_recv_packet(int fd, char** buffer) { if (packet_idx == packet_size) { packet_size += ALLOC_STEP; void* p = realloc(packet_buffer, packet_size); + if (p != NULL) { packet_buffer = p; } else { free(packet_buffer); - return -2; + return(-2); } } } + break; case 2: @@ -124,25 +137,29 @@ int gdb_recv_packet(int fd, char** buffer) { } uint8_t recv_cksum_int = strtoul(recv_cksum, NULL, 16); + if (recv_cksum_int != cksum) { char nack = '-'; + if (write(fd, &nack, 1) != 1) { free(packet_buffer); - return -2; + return(-2); } + goto start; } else { char ack = '+'; + if (write(fd, &ack, 1) != 1) { free(packet_buffer); - return -2; + return(-2); } } packet_buffer[packet_idx] = 0; *buffer = packet_buffer; - return packet_idx; + return(packet_idx); } /* @@ -157,9 +174,15 @@ int gdb_check_for_interrupt(int fd) { if (poll(&pfd, 1, 0) != 0) { char c; - if (read(fd, &c, 1) != 1) return -2; - if (c == '\x03') return 1; // ^C + + if (read(fd, &c, 1) != 1) { + return(-2); + } + + if (c == '\x03') { + return(1); // ^C + } } - return 0; + return(0); } diff --git a/src/st-util/gdb-remote.h b/src/st-util/gdb-remote.h index bfa01046c..6e76746b7 100644 --- a/src/st-util/gdb-remote.h +++ b/src/st-util/gdb-remote.h @@ -5,4 +5,4 @@ int gdb_send_packet(int fd, char* data); int gdb_recv_packet(int fd, char** buffer); int gdb_check_for_interrupt(int fd); -#endif +#endif // _GDB_REMOTE_H_ diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 119d0ff9a..94cd6fda7 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Peter Zotov + * Copyright (c) 2011 Peter Zotov * Use of this source code is governed by a BSD-style license that can be found in the LICENSE file. */ @@ -69,13 +69,13 @@ typedef struct _st_state_t { int serve(stlink_t *sl, st_state_t *st); char* make_memory_map(stlink_t *sl); -static void init_cache (stlink_t *sl); +static void init_cache(stlink_t *sl); static void cleanup(int signum) { (void)signum; if (connected_stlink) { - /* Switch back to mass storage mode before closing. */ + // Switch back to mass storage mode before closing stlink_run(connected_stlink); stlink_exit_debug_mode(connected_stlink); stlink_close(connected_stlink); @@ -87,12 +87,14 @@ static void cleanup(int signum) { static stlink_t* do_connect(st_state_t *st) { stlink_t *sl = NULL; + if (serial_specified) { sl = stlink_open_usb(st->logging_level, st->reset, serialnumber, 0); } else { sl = stlink_open_usb(st->logging_level, st->reset, NULL, 0); } - return sl; + + return(sl); } @@ -109,92 +111,104 @@ int parse_options(int argc, char** argv, st_state_t *st) { {0, 0, 0, 0}, }; const char * help_str = "%s - usage:\n\n" - " -h, --help\t\tPrint this help\n" - " -V, --version\t\tPrint the version\n" - " -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n" - " -v, --verbose\t\tSpecify generally verbose logging\n" - "\t\t\tChoose what version of stlink to use, (defaults to 2)\n" - " -1, --stlinkv1\tForce stlink version 1\n" - " -p 4242, --listen_port=1234\n" - "\t\t\tSet the gdb server listen port. " - "(default port: " STRINGIFY(DEFAULT_GDB_LISTEN_PORT) ")\n" - " -m, --multi\n" - "\t\t\tSet gdb server to extended mode.\n" - "\t\t\tst-util will continue listening for connections after disconnect.\n" - " -n, --no-reset\n" - "\t\t\tDo not reset board on connection.\n" - " --semihosting\n" - "\t\t\tEnable semihosting support.\n" - " --serial \n" - "\t\t\tUse a specific serial number.\n" - "\n" - "The STLINK device to use can be specified in the environment\n" - "variable STLINK_DEVICE on the format :.\n" - "\n" - ; + " -h, --help\t\tPrint this help\n" + " -V, --version\t\tPrint the version\n" + " -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n" + " -v, --verbose\t\tSpecify generally verbose logging\n" + "\t\t\tChoose what version of stlink to use, (defaults to 2)\n" + " -1, --stlinkv1\tForce stlink version 1\n" + " -p 4242, --listen_port=1234\n" + "\t\t\tSet the gdb server listen port. " + "(default port: " STRINGIFY(DEFAULT_GDB_LISTEN_PORT) ")\n" + " -m, --multi\n" + "\t\t\tSet gdb server to extended mode.\n" + "\t\t\tst-util will continue listening for connections after disconnect.\n" + " -n, --no-reset\n" + "\t\t\tDo not reset board on connection.\n" + " --semihosting\n" + "\t\t\tEnable semihosting support.\n" + " --serial \n" + "\t\t\tUse a specific serial number.\n" + "\n" + "The STLINK device to use can be specified in the environment\n" + "variable STLINK_DEVICE on the format :.\n" + "\n" + ; int option_index = 0; int c; int q; - while ((c = getopt_long(argc, argv, "hv::p:mn", long_options, &option_index)) != -1) { + + while ((c = getopt_long(argc, argv, "hv::p:mn", long_options, &option_index)) != -1) switch (c) { - case 0: - break; - case 'h': - printf(help_str, argv[0]); - exit(EXIT_SUCCESS); - break; - case 'v': - if (optarg) { - st->logging_level = atoi(optarg); - } else { - st->logging_level = DEBUG_LOGGING_LEVEL; - } - break; - case 'p': - sscanf(optarg, "%i", &q); - if (q < 0) { - fprintf(stderr, "Can't use a negative port to listen on: %d\n", q); - exit(EXIT_FAILURE); - } - st->listen_port = q; - break; - case 'm': - st->persistent = 1; - break; - case 'n': - st->reset = 0; - break; - case 'V': - printf("v%s\n", STLINK_VERSION); - exit(EXIT_SUCCESS); - case SEMIHOSTING_OPTION: - semihosting = true; - break; - case SERIAL_OPTION: - printf("use serial %s\n",optarg); - /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ - int j = (int)strlen(optarg); - int length = j / 2; //the length of the destination-array - if (j % 2 != 0) return -1; - for (size_t k = 0; j >= 0 && k < sizeof(serialnumber); ++k, j -= 2) { - char buffer[3] = {0}; - memcpy(buffer, optarg + j, 2); - serialnumber[length - k] = (uint8_t)strtol(buffer, NULL, 16); - } - serial_specified = true; - break; + case 0: + break; + case 'h': + printf(help_str, argv[0]); + exit(EXIT_SUCCESS); + break; + case 'v': + + if (optarg) { + st->logging_level = atoi(optarg); + } else { + st->logging_level = DEBUG_LOGGING_LEVEL; + } + + break; + case 'p': + sscanf(optarg, "%i", &q); + + if (q < 0) { + fprintf(stderr, "Can't use a negative port to listen on: %d\n", q); + exit(EXIT_FAILURE); + } + + st->listen_port = q; + break; + case 'm': + st->persistent = 1; + break; + case 'n': + st->reset = 0; + break; + case 'V': + printf("v%s\n", STLINK_VERSION); + exit(EXIT_SUCCESS); + case SEMIHOSTING_OPTION: + semihosting = true; + break; + case SERIAL_OPTION: + printf("use serial %s\n", optarg); + /* TODO: This is not really portable, as strlen really returns size_t, + * we need to obey and not cast it to a signed type. + */ + int j = (int)strlen(optarg); + int length = j / 2; // the length of the destination-array + + if (j % 2 != 0) { return(-1); } + + for (size_t k = 0; j >= 0 && k < sizeof(serialnumber); ++k, j -= 2) { + char buffer[3] = {0}; + memcpy(buffer, optarg + j, 2); + serialnumber[length - k] = (uint8_t)strtol(buffer, NULL, 16); + } + + serial_specified = true; + break; } - } + if (optind < argc) { printf("non-option ARGV-elements: "); - while (optind < argc) - printf("%s ", argv[optind++]); + + while (optind < argc) { printf("%s ", argv[optind++]); } + printf("\n"); } - return 0; + + return(0); } int main(int argc, char** argv) { @@ -211,11 +225,12 @@ int main(int argc, char** argv) { printf("st-util\n"); sl = do_connect(&state); - if (sl == NULL) return 1; - if (sl->chip_id == STLINK_CHIPID_UNKNOWN) { + if (sl == NULL) { return(1); } + + if (sl->chip_id == STLINK_CHIPID_UNKNOWN) { ELOG("Unsupported Target (Chip ID is %#010x, Core ID is %#010x).\n", sl->chip_id, sl->core_id); - return 1; + return(1); } connected_stlink = sl; @@ -223,22 +238,25 @@ int main(int argc, char** argv) { signal(SIGTERM, &cleanup); signal(SIGSEGV, &cleanup); - if (state.reset) stlink_reset(sl); + if (state.reset) { stlink_reset(sl); } DLOG("Chip ID is %#010x, Core ID is %#08x.\n", sl->chip_id, sl->core_id); - sl->verbose=0; + sl->verbose = 0; current_memory_map = make_memory_map(sl); #if defined(_WIN32) - WSADATA wsadata; - if (WSAStartup(MAKEWORD(2,2),&wsadata) !=0) goto winsock_error; + WSADATA wsadata; + + if (WSAStartup(MAKEWORD(2, 2), &wsadata) != 0) { goto winsock_error; } + #endif init_cache(sl); - do { - if (serve(sl, &state)) { usleep (1 * 1000); } // don't go beserk if serve returns with error + do { // don't go beserk if serve() returns with error + if (serve(sl, &state)) { usleep (1 * 1000); } + sl = connected_stlink; // in case serve() changed the connection stlink_run(sl); // continue } while (state.persistent); @@ -252,7 +270,7 @@ int main(int argc, char** argv) { stlink_exit_debug_mode(sl); stlink_close(sl); - return 0; + return(0); } static const char* const target_description_F4 = @@ -328,14 +346,14 @@ static const char* const memory_map_template_F4 = " " // code = sram, bootrom or flash; flash is bigger " " // ccm ram " " // sram - " " //Sectors 0..3 - " 0x4000" //16kB + " " // Sectors 0..3 + " 0x4000" // 16kB " " - " " //Sector 4 - " 0x10000" //64kB + " " // Sector 4 + " 0x10000" // 64kB " " - " " //Sectors 5..11 - " 0x20000" //128kB + " " // Sectors 5..11 + " 0x20000" // 128kB " " " " // peripheral regs " " // AHB3 Peripherals @@ -356,14 +374,14 @@ static const char* const memory_map_template_F4_HD = " " // fmc bank 2 & 3 (nand flash) " " // fmc bank 4 (pc card) " " // fmc sdram bank 1 & 2 - " " //Sectors 0..3 - " 0x4000" //16kB + " " // Sectors 0..3 + " 0x4000" // 16kB " " - " " //Sector 4 - " 0x10000" //64kB + " " // Sector 4 + " 0x10000" // 64kB " " - " " //Sectors 5..11 - " 0x20000" //128kB + " " // Sectors 5..11 + " 0x20000" // 128kB " " " " // peripheral regs " " // cortex regs @@ -376,20 +394,20 @@ static const char* const memory_map_template_F2 = "" "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram - " " //Sectors 0..3 - " 0x4000" //16kB + " " // code = sram, bootrom or flash; flash is bigger + " " // sram + " " // Sectors 0..3 + " 0x4000" // 16kB " " - " " //Sector 4 - " 0x10000" //64kB + " " // Sector 4 + " 0x10000" // 64kB " " - " " //Sectors 5.. - " 0x20000" //128kB + " " // Sectors 5.. + " 0x20000" // 128kB " " " " // peripheral regs " " // cortex regs - " " // bootrom + " " // bootrom " " // option byte area ""; @@ -398,9 +416,9 @@ static const char* const memory_map_template_L4 = "" "" - " " // code = sram, bootrom or flash; flash is bigger - " " // SRAM2 (32 KB) - " " // SRAM1 (96 KB) + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM2 (32kB) + " " // SRAM1 (96kB) " " " 0x800" " " @@ -417,9 +435,9 @@ static const char* const memory_map_template_L496 = "" "" - " " // code = sram, bootrom or flash; flash is bigger - " " // SRAM2 (64 KB) - " " // SRAM1 + aliased SRAM2 (256+64=320 KB) + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM2 (64kB) + " " // SRAM1 + aliased SRAM2 (256 + 64 = 320kB) " " " 0x800" " " @@ -436,14 +454,14 @@ static const char* const memory_map_template = "" "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram 8k + " " // code = sram, bootrom or flash; flash is bigger + " " // sram 8kB " " " 0x%x" " " " " // peripheral regs " " // cortex regs - " " // bootrom + " " // bootrom " " // option byte area ""; @@ -454,7 +472,7 @@ static const char* const memory_map_template_F7 = "" " " // ITCM ram 16kB " " // ITCM flash - " " // sram + " " // sram " " // Sectors 0..3 " 0x8000" // 32kB " " @@ -479,14 +497,14 @@ static const char* const memory_map_template_F4_DE = "" " " // code = sram, bootrom or flash; flash is bigger " " // sram - " " //Sectors 0..3 - " 0x4000" //16kB + " " // Sectors 0..3 + " 0x4000" // 16kB " " - " " //Sector 4 - " 0x10000" //64kB + " " // Sector 4 + " 0x10000" // 64kB " " - " " //Sectors 5..7 - " 0x20000" //128kB + " " // Sectors 5..7 + " 0x20000" // 128kB " " " " // peripheral regs " " // cortex regs @@ -501,37 +519,45 @@ char* make_memory_map(stlink_t *sl) { char* map = malloc(sz); map[0] = '\0'; - if (sl->chip_id==STLINK_CHIPID_STM32_F4 || sl->chip_id==STLINK_CHIPID_STM32_F446 || sl->chip_id==STLINK_CHIPID_STM32_F411RE) { - strcpy(map, memory_map_template_F4); - } else if (sl->chip_id==STLINK_CHIPID_STM32_F4_DE) { + if (sl->chip_id == STLINK_CHIPID_STM32_F4 || + sl->chip_id == STLINK_CHIPID_STM32_F446 || + sl->chip_id == STLINK_CHIPID_STM32_F411RE) { + strcpy(map, memory_map_template_F4); + } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) { strcpy(map, memory_map_template_F4_DE); - } else if (sl->core_id==STM32F7_CORE_ID) { + } else if (sl->core_id == STM32F7_CORE_ID) { snprintf(map, sz, memory_map_template_F7, - (unsigned int)sl->sram_size); - } else if (sl->chip_id==STLINK_CHIPID_STM32_F4_HD) { + (unsigned int)sl->sram_size); + } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) { strcpy(map, memory_map_template_F4_HD); - } else if (sl->chip_id==STLINK_CHIPID_STM32_F2) { + } else if (sl->chip_id == STLINK_CHIPID_STM32_F2) { snprintf(map, sz, memory_map_template_F2, - (unsigned int)sl->flash_size, - (unsigned int)sl->sram_size, - (unsigned int)sl->flash_size - 0x20000, - (unsigned int)sl->sys_base, (unsigned int)sl->sys_size); - } else if ((sl->chip_id==STLINK_CHIPID_STM32_L4) || - (sl->chip_id==STLINK_CHIPID_STM32_L43X) || - (sl->chip_id==STLINK_CHIPID_STM32_L46X)) { + (unsigned int)sl->flash_size, + (unsigned int)sl->sram_size, + (unsigned int)sl->flash_size - 0x20000, + (unsigned int)sl->sys_base, + (unsigned int)sl->sys_size); + } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || + (sl->chip_id == STLINK_CHIPID_STM32_L43X) || + (sl->chip_id == STLINK_CHIPID_STM32_L46X)) { snprintf(map, sz, memory_map_template_L4, - (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id==STLINK_CHIPID_STM32_L496X) { + (unsigned int)sl->flash_size, + (unsigned int)sl->flash_size); + } else if (sl->chip_id == STLINK_CHIPID_STM32_L496X) { snprintf(map, sz, memory_map_template_L496, - (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); + (unsigned int)sl->flash_size, + (unsigned int)sl->flash_size); } else { snprintf(map, sz, memory_map_template, - (unsigned int)sl->flash_size, - (unsigned int)sl->sram_size, - (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz, - (unsigned int)sl->sys_base, (unsigned int)sl->sys_size); + (unsigned int)sl->flash_size, + (unsigned int)sl->sram_size, + (unsigned int)sl->flash_size, + (unsigned int)sl->flash_pgsz, + (unsigned int)sl->sys_base, + (unsigned int)sl->sys_size); } - return map; + + return(map); } /* @@ -566,7 +592,7 @@ static void init_data_watchpoints(stlink_t *sl) { DLOG("init watchpoints\n"); stlink_read_debug32(sl, 0xE000EDFC, &data); - data |= 1<<24; + data |= 1 << 24; // set trcena in debug command to turn on dwt unit stlink_write_debug32(sl, 0xE000EDFC, data); @@ -577,8 +603,7 @@ static void init_data_watchpoints(stlink_t *sl) { } } -static int add_data_watchpoint( - stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len) { +static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len) { int i = 0; uint32_t mask, dummy; @@ -588,13 +613,14 @@ static int add_data_watchpoint( mask = -1; i = len; + while (i) { i >>= 1; mask++; } if ((mask != (uint32_t)-1) && (mask < 16)) { - for (i = 0; i < DATA_WATCH_NUM; i++) { + for (i = 0; i < DATA_WATCH_NUM; i++) // is this an empty slot ? if (data_watches[i].fun == WATCHDISABLED) { DLOG("insert watchpoint %d addr %x wf %u mask %u len %d\n", i, addr, wf, mask, len); @@ -614,43 +640,42 @@ static int add_data_watchpoint( // just to make sure the matched bit is clear ! stlink_read_debug32(sl, 0xE0001028 + i * 16, &dummy); - return 0; + return(0); } - } } DLOG("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len); - return -1; + return(-1); } static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { int i; - for (i = 0 ; i < DATA_WATCH_NUM; i++) { + for (i = 0; i < DATA_WATCH_NUM; i++) { if ((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) { DLOG("delete watchpoint %d addr %x\n", i, addr); data_watches[i].fun = WATCHDISABLED; stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); - return 0; + return(0); } } DLOG("failure: delete watchpoint addr %x\n", addr); - return -1; + return(-1); } static int code_break_num; static int code_lit_num; -#define CODE_BREAK_NUM_MAX 15 -#define CODE_BREAK_LOW 0x01 +#define CODE_BREAK_NUM_MAX 15 +#define CODE_BREAK_LOW 0x01 #define CODE_BREAK_HIGH 0x02 struct code_hw_breakpoint { stm32_addr_t addr; - int type; + int type; }; static struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; @@ -658,7 +683,7 @@ static struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; static void init_code_breakpoints(stlink_t *sl) { unsigned int val; memset(sl->q_buf, 0, 4); - stlink_write_debug32(sl, STLINK_REG_CM3_FP_CTRL, 0x03 /*KEY | ENABLE4*/); + stlink_write_debug32(sl, STLINK_REG_CM3_FP_CTRL, 0x03 /* KEY | ENABLE4 */); stlink_read_debug32(sl, STLINK_REG_CM3_FP_CTRL, &val); code_break_num = ((val >> 4) & 0xf); code_lit_num = ((val >> 8) & 0xf); @@ -671,12 +696,11 @@ static void init_code_breakpoints(stlink_t *sl) { } } -static int has_breakpoint(stm32_addr_t addr) -{ - for (int i = 0; i < code_break_num; i++) { - if (code_breaks[i].addr == addr) return 1; - } - return 0; +static int has_breakpoint(stm32_addr_t addr) { + for (int i = 0; i < code_break_num; i++) + if (code_breaks[i].addr == addr) { return(1); } + + return(0); } static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { @@ -686,37 +710,53 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { if (addr & 1) { ELOG("update_code_breakpoint: unaligned address %08x\n", addr); - return -1; + return(-1); } - if (sl->core_id==STM32F7_CORE_ID) { + if (sl->core_id == STM32F7_CORE_ID) { fpb_addr = addr; } else { fpb_addr = addr & ~0x3; } int id = -1; - for (int i = 0; i < code_break_num; i++) { + + for (int i = 0; i < code_break_num; i++) if (fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { id = i; break; } - } + if (id == -1) { - if (set) { return -1; } // free slot not found - else { return 0; } // breakpoint is already removed + if (set) { + return(-1); + } // free slot not found + else { + return(0); + } // breakpoint is already removed + } struct code_hw_breakpoint* bp = &code_breaks[id]; bp->addr = fpb_addr; - if (sl->core_id==STM32F7_CORE_ID) { - if (set) { bp->type = type; } else { bp->type = 0; } + if (sl->core_id == STM32F7_CORE_ID) { + if (set) { + bp->type = type; + } else { + bp->type = 0; + } + mask = (bp->addr) | 1; } else { - if (set) { bp->type |= type; } else { bp->type &= ~type; } + if (set) { + bp->type |= type; + } else { + bp->type &= ~type; + } + mask = (bp->addr) | 1 | (bp->type << 30); } @@ -729,13 +769,13 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { stlink_write_debug32(sl, 0xe0002008 + id * 4, mask); } - return 0; + return(0); } struct flash_block { stm32_addr_t addr; - unsigned length; + unsigned length; uint8_t* data; struct flash_block* next; @@ -747,13 +787,14 @@ static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { if (addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) { ELOG("flash_add_block: incorrect bounds\n"); - return -1; + return(-1); } stlink_calculate_pagesize(sl, addr); + if (addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) { ELOG("flash_add_block: unaligned block\n"); - return -1; + return(-1); } struct flash_block* new = malloc(sizeof(struct flash_block)); @@ -763,15 +804,15 @@ static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { new->data = calloc(length, 1); flash_root = new; - - return 0; + return(0); } static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { unsigned int fit_blocks = 0, fit_length = 0; for (struct flash_block* fb = flash_root; fb; fb = fb->next) { - /* Block: ------X------Y-------- + /* + * Block: ------X------Y-------- * Data: a-----b * a--b * a-----------b @@ -781,6 +822,7 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { unsigned X = fb->addr, Y = fb->addr + fb->length; unsigned a = addr, b = addr + length; + if (a < Y && b > X) { // from start of the block unsigned start = (a > X ? a : X) - X; @@ -795,7 +837,7 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { if (fit_blocks == 0) { ELOG("Unfit data block %08x -> %04x\n", addr, length); - return -1; + return(-1); } if (fit_length != length) { @@ -803,7 +845,7 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { WLOG("(this is not an error, just a GDB glitch)\n"); } - return 0; + return(0); } static int flash_go(stlink_t *sl) { @@ -823,17 +865,18 @@ static int flash_go(stlink_t *sl) { stlink_calculate_pagesize(sl, page); DLOG("flash_do: page %08x\n", page); - unsigned len = (length > FLASH_PAGE) ? (unsigned int) FLASH_PAGE : length; + unsigned len = (length > FLASH_PAGE) ? (unsigned int)FLASH_PAGE : length; int ret = stlink_write_flash(sl, page, fb->data + (page - fb->addr), len, 0); - if (ret < 0) goto error; + + if (ret < 0) { goto error; } } } stlink_reset(sl); - error = 0; error: + for (struct flash_block* fb = flash_root, *next; fb; fb = next) { next = fb->next; free(fb->data); @@ -841,8 +884,7 @@ static int flash_go(stlink_t *sl) { } flash_root = NULL; - - return error; + return(error); } #define CLIDR 0xE000ED78 @@ -863,11 +905,11 @@ struct cache_level_desc { }; struct cache_desc_t { - // Minimal line size in bytes + // minimal line size in bytes unsigned int dminline; unsigned int iminline; - // Last level of unification (uniprocessor) + // last level of unification (uniprocessor) unsigned int louu; struct cache_level_desc icache[7]; @@ -879,8 +921,10 @@ static struct cache_desc_t cache_desc; // return the smallest R so that V <= (1 << R); not performance critical static unsigned ceil_log2(unsigned v) { unsigned res; - for (res = 0; (1U << res) < v; res++) ; - return res; + + for (res = 0; (1U << res) < v; res++); + + return(res); } static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) { @@ -894,7 +938,7 @@ static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) { log2_nsets = ceil_log2 (desc->nsets); desc->width = 4 + (ccsidr & 7) + log2_nsets; ILOG("%08x LineSize: %u, ways: %u, sets: %u (width: %u)\n", - ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width); + ccsidr, 4 << (ccsidr & 7), desc->nways, desc->nsets, desc->width); } static void init_cache (stlink_t *sl) { @@ -903,8 +947,8 @@ static void init_cache (stlink_t *sl) { unsigned int ctr; int i; - // Assume only F7 has a cache - if (sl->core_id!=STM32F7_CORE_ID) return; + // assume only F7 has a cache + if (sl->core_id != STM32F7_CORE_ID) { return; } stlink_read_debug32(sl, CLIDR, &clidr); stlink_read_debug32(sl, CCR, &ccr); @@ -914,23 +958,24 @@ static void init_cache (stlink_t *sl) { cache_desc.louu = (clidr >> 27) & 7; ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n", - clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off"); + clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off"); ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n", - (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7); + (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7); ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr, - cache_desc.dminline, cache_desc.iminline); + cache_desc.dminline, cache_desc.iminline); + for (i = 0; i < 7; i++) { unsigned int ct = (clidr >> (3 * i)) & 0x07; cache_desc.dcache[i].width = 0; cache_desc.icache[i].width = 0; - if (ct == 2 || ct == 3 || ct == 4) { // Data + if (ct == 2 || ct == 3 || ct == 4) { // data stlink_write_debug32(sl, CSSELR, i << 1); ILOG("D-Cache L%d: ", i); read_cache_level_desc(sl, &cache_desc.dcache[i]); } - if (ct == 1 || ct == 3) { // Instruction + if (ct == 1 || ct == 3) { // instruction stlink_write_debug32(sl, CSSELR, (i << 1) | 1); ILOG("I-Cache L%d: ", i); read_cache_level_desc(sl, &cache_desc.icache[i]); @@ -941,7 +986,7 @@ static void init_cache (stlink_t *sl) { static void cache_flush(stlink_t *sl, unsigned ccr) { int level; - if (ccr & CCR_DC) + if (ccr & CCR_DC) { for (level = cache_desc.louu - 1; level >= 0; level--) { struct cache_level_desc *desc = &cache_desc.dcache[level]; unsigned addr; @@ -951,19 +996,25 @@ static void cache_flush(stlink_t *sl, unsigned ccr) { // D-cache clean by set-ways. for (addr = (level << 1); addr < max_addr; addr += cache_desc.dminline) { unsigned int way; - for (way = 0; way < desc->nways; way++) + + for (way = 0; way < desc->nways; way++) { stlink_write_debug32(sl, DCCSW, addr | (way << way_sh)); + } } } + } // invalidate all I-cache to oPU - if (ccr & CCR_IC) stlink_write_debug32(sl, ICIALLU, 0); + if (ccr & CCR_IC) { + stlink_write_debug32(sl, ICIALLU, 0); + } } static int cache_modified; static void cache_change(stm32_addr_t start, unsigned count) { - if (count == 0) return; + if (count == 0) { return; } + (void)start; cache_modified = 1; } @@ -971,12 +1022,14 @@ static void cache_change(stm32_addr_t start, unsigned count) { static void cache_sync(stlink_t *sl) { unsigned ccr; - if (sl->core_id!=STM32F7_CORE_ID) return; - if (!cache_modified) return; - cache_modified = 0; + if (sl->core_id != STM32F7_CORE_ID) { return; } + if (!cache_modified) { return; } + + cache_modified = 0; stlink_read_debug32(sl, CCR, &ccr); - if (ccr & (CCR_IC | CCR_DC)) cache_flush(sl, ccr); + + if (ccr & (CCR_IC | CCR_DC)) { cache_flush(sl, ccr); } } static size_t unhexify(const char *in, char *out, size_t out_count) { @@ -984,55 +1037,60 @@ static size_t unhexify(const char *in, char *out, size_t out_count) { unsigned int c; for (i = 0; i < out_count; i++) { - if (sscanf(in + (2 * i), "%02x", &c) != 1) return i; + if (sscanf(in + (2 * i), "%02x", &c) != 1) { return(i); } + out[i] = (char)c; } - return i; + return(i); } int serve(stlink_t *sl, st_state_t *st) { SOCKET sock = socket(AF_INET, SOCK_STREAM, 0); + if (!IS_SOCK_VALID(sock)) { perror("socket"); - return 1; + return(1); } unsigned int val = 1; setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val)); struct sockaddr_in serv_addr; - memset(&serv_addr,0,sizeof(struct sockaddr_in)); + memset(&serv_addr, 0, sizeof(struct sockaddr_in)); serv_addr.sin_family = AF_INET; serv_addr.sin_addr.s_addr = INADDR_ANY; serv_addr.sin_port = htons(st->listen_port); - if (bind(sock, (struct sockaddr *) &serv_addr, sizeof(serv_addr)) < 0) { + if (bind(sock, (struct sockaddr *)&serv_addr, sizeof(serv_addr)) < 0) { perror("bind"); close_socket(sock); - return 1; + return(1); } if (listen(sock, 5) < 0) { perror("listen"); close_socket(sock); - return 1; + return(1); } ILOG("Listening at *:%d...\n", st->listen_port); SOCKET client = accept(sock, NULL, NULL); - //signal (SIGINT, SIG_DFL); + + // signal (SIGINT, SIG_DFL); if (!IS_SOCK_VALID(client)) { perror("accept"); close_socket(sock); - return 1; + return(1); } close_socket(sock); stlink_force_debug(sl); - if (st->reset) stlink_reset(sl); + + if (st->reset) { stlink_reset(sl); } + init_code_breakpoints(sl); init_data_watchpoints(sl); @@ -1052,10 +1110,11 @@ int serve(stlink_t *sl, st_state_t *st) { char* packet; int status = gdb_recv_packet(client, &packet); + if (status < 0) { ELOG("cannot recv: %d\n", status); close_socket(client); - return 1; + return(1); } DLOG("recv: %s\n", packet); @@ -1063,686 +1122,736 @@ int serve(stlink_t *sl, st_state_t *st) { char* reply = NULL; struct stlink_reg regp; - switch(packet[0]) { - case 'q': { - if (packet[1] == 'P' || packet[1] == 'C' || packet[1] == 'L') { - reply = strdup(""); - break; - } + switch (packet[0]) { + case 'q': { + if (packet[1] == 'P' || packet[1] == 'C' || packet[1] == 'L') { + reply = strdup(""); + break; + } - char *separator = strstr(packet, ":"), *params = ""; - if (separator == NULL) { - separator = packet + strlen(packet); + char *separator = strstr(packet, ":"), *params = ""; + + if (separator == NULL) { + separator = packet + strlen(packet); + } else { + params = separator + 1; + } + + unsigned queryNameLength = (unsigned int)(separator - &packet[1]); + char* queryName = calloc(queryNameLength + 1, 1); + strncpy(queryName, &packet[1], queryNameLength); + + DLOG("query: %s;%s\n", queryName, params); + + if (!strcmp(queryName, "Supported")) { + if (sl->chip_id == STLINK_CHIPID_STM32_F4 || + sl->chip_id == STLINK_CHIPID_STM32_F4_HD || + sl->core_id == STM32F7_CORE_ID) { + reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); } else { - params = separator + 1; + reply = strdup("PacketSize=3fff;qXfer:memory-map:read+"); } + } else if (!strcmp(queryName, "Xfer")) { + char *type, *op, *__s_addr, *s_length; + char *tok = params; + char *annex __attribute__((unused)); - unsigned queryNameLength = (unsigned int) (separator - &packet[1]); - char* queryName = calloc(queryNameLength + 1, 1); - strncpy(queryName, &packet[1], queryNameLength); + type = strsep(&tok, ":"); + op = strsep(&tok, ":"); + annex = strsep(&tok, ":"); + __s_addr = strsep(&tok, ","); + s_length = tok; - DLOG("query: %s;%s\n", queryName, params); + unsigned addr = (unsigned int)strtoul(__s_addr, NULL, 16), + length = (unsigned int)strtoul(s_length, NULL, 16); - if (!strcmp(queryName, "Supported")) { - if (sl->chip_id==STLINK_CHIPID_STM32_F4 || - sl->chip_id==STLINK_CHIPID_STM32_F4_HD || - sl->core_id==STM32F7_CORE_ID) { - reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); - } else { - reply = strdup("PacketSize=3fff;qXfer:memory-map:read+"); - } - } else if (!strcmp(queryName, "Xfer")) { - char *type, *op, *__s_addr, *s_length; - char *tok = params; - char *annex __attribute__((unused)); - - type = strsep(&tok, ":"); - op = strsep(&tok, ":"); - annex = strsep(&tok, ":"); - __s_addr = strsep(&tok, ","); - s_length = tok; - - unsigned addr = (unsigned int) strtoul(__s_addr, NULL, 16), - length = (unsigned int) strtoul(s_length, NULL, 16); - - DLOG("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", - type, op, annex, addr, length); - - const char* data = NULL; - - if (!strcmp(type, "memory-map") && !strcmp(op, "read")) - data = current_memory_map; - - if (!strcmp(type, "features") && !strcmp(op, "read")) - data = target_description_F4; - - if (data) { - unsigned data_length = (unsigned int) strlen(data); - if (addr + length > data_length) - length = data_length - addr; - if (length == 0) { - reply = strdup("l"); - } else { - reply = calloc(length + 2, 1); - reply[0] = 'm'; - strncpy(&reply[1], data, length); - } - } - } else if (!strncmp(queryName, "Rcmd,",4)) { - // Rcmd uses the wrong separator - separator = strstr(packet, ","); - params = ""; - if (separator == NULL) { - separator = packet + strlen(packet); - } else { - params = separator + 1; - } + DLOG("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", + type, op, annex, addr, length); - size_t hex_len = strlen(params); - size_t alloc_size = (hex_len / 2) + 1; - size_t cmd_len; - char *cmd = malloc(alloc_size); + const char* data = NULL; - if (cmd == NULL) { - DLOG("Rcmd unhexify allocation error\n"); - break; - } + if (!strcmp(type, "memory-map") && !strcmp(op, "read")) { + data = current_memory_map; + } - cmd_len = unhexify(params, cmd, alloc_size - 1); - cmd[cmd_len] = 0; + if (!strcmp(type, "features") && !strcmp(op, "read")) { + data = target_description_F4; + } - DLOG("unhexified Rcmd: '%s'\n", cmd); + if (data) { + unsigned data_length = (unsigned int)strlen(data); - if (!strncmp(cmd, "resume", 6)) { // resume - DLOG("Rcmd: resume\n"); - cache_sync(sl); - ret = stlink_run(sl); - if (ret) { - DLOG("Rcmd: resume failed\n"); - reply = strdup("E00"); - } else { - reply = strdup("OK"); - } - - } else if (!strncmp(cmd, "halt", 4)) { // halt - ret = stlink_force_debug(sl); - if (ret) { - DLOG("Rcmd: halt failed\n"); - reply = strdup("E00"); - } else { - reply = strdup("OK"); - DLOG("Rcmd: halt\n"); - } - - } else if (!strncmp(cmd, "jtag_reset", 10)) { // jtag_reset - reply = strdup("OK"); + if (addr + length > data_length) { length = data_length - addr; } - ret = stlink_jtag_reset(sl, 0); - if (ret) { - DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); - reply = strdup("E00"); - } - - ret = stlink_jtag_reset(sl, 1); - if (ret) { - DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); - reply = strdup("E00"); - } - - ret = stlink_force_debug(sl); - if (ret) { - DLOG("Rcmd: jtag_reset failed with force_debug\n"); - reply = strdup("E00"); - } - - if (strcmp(reply, "E00")) { - // no errors have been found - DLOG("Rcmd: jtag_reset\n"); - } - } else if (!strncmp(cmd, "reset", 5)) { //reset - - ret = stlink_force_debug(sl); - if (ret) { - DLOG("Rcmd: reset failed with force_debug\n"); - reply = strdup("E00"); - } - - ret = stlink_reset(sl); - if (ret) { - DLOG("Rcmd: reset failed with reset\n"); - reply = strdup("E00"); - } - - init_code_breakpoints(sl); - init_data_watchpoints(sl); - - if (reply == NULL) { - reply = strdup("OK"); - DLOG("Rcmd: reset\n"); - } - - } else if (!strncmp(cmd, "semihosting ", 12)) { - DLOG("Rcmd: got semihosting cmd '%s'", cmd); - char *arg = cmd + 12; - - // Skip whitespaces - while (isspace(*arg)) { arg++; } - - if (!strncmp(arg, "enable", 6) || !strncmp(arg, "1", 1)) { - semihosting = true; - reply = strdup("OK"); - } else if (!strncmp(arg, "disable", 7) || !strncmp(arg, "0", 1)) { - semihosting = false; - reply = strdup("OK"); - } else { - DLOG("Rcmd: unknown semihosting arg: '%s'\n", arg); - } + if (length == 0) { + reply = strdup("l"); } else { - DLOG("Rcmd: %s\n", cmd); + reply = calloc(length + 2, 1); + reply[0] = 'm'; + strncpy(&reply[1], data, length); } - free(cmd); } + } else if (!strncmp(queryName, "Rcmd,", 4)) { + // Rcmd uses the wrong separator + separator = strstr(packet, ","); + params = ""; - if (reply == NULL) - reply = strdup(""); + if (separator == NULL) { + separator = packet + strlen(packet); + } else { + params = separator + 1; + } - free(queryName); + size_t hex_len = strlen(params); + size_t alloc_size = (hex_len / 2) + 1; + size_t cmd_len; + char *cmd = malloc(alloc_size); - break; - } - - case 'v': { - char *params = NULL; - char *cmdName = strtok_r(packet, ":;", ¶ms); + if (cmd == NULL) { + DLOG("Rcmd unhexify allocation error\n"); + break; + } - cmdName++; // vCommand -> Command + cmd_len = unhexify(params, cmd, alloc_size - 1); + cmd[cmd_len] = 0; - if (!strcmp(cmdName, "FlashErase")) { - char *__s_addr, *s_length; - char *tok = params; + DLOG("unhexified Rcmd: '%s'\n", cmd); - __s_addr = strsep(&tok, ","); - s_length = tok; + if (!strncmp(cmd, "resume", 6)) { // resume + DLOG("Rcmd: resume\n"); + cache_sync(sl); + ret = stlink_run(sl); - unsigned addr = (unsigned int) strtoul(__s_addr, NULL, 16), - length = (unsigned int) strtoul(s_length, NULL, 16); + if (ret) { + DLOG("Rcmd: resume failed\n"); + reply = strdup("E00"); + } else { + reply = strdup("OK"); + } - DLOG("FlashErase: addr:%08x,len:%04x\n", - addr, length); + } else if (!strncmp(cmd, "halt", 4)) { // halt + ret = stlink_force_debug(sl); - if (flash_add_block(addr, length, sl) < 0) { + if (ret) { + DLOG("Rcmd: halt failed\n"); reply = strdup("E00"); } else { reply = strdup("OK"); + DLOG("Rcmd: halt\n"); } - } else if (!strcmp(cmdName, "FlashWrite")) { - char *__s_addr, *data; - char *tok = params; - - __s_addr = strsep(&tok, ":"); - data = tok; - - unsigned addr = (unsigned int) strtoul(__s_addr, NULL, 16); - unsigned data_length = status - (unsigned int) (data - packet); - - // Length of decoded data cannot be more than encoded, as escapes are removed. - // Additional byte is reserved for alignment fix. - uint8_t *decoded = calloc(data_length + 1, 1); - unsigned dec_index = 0; - for (unsigned int i = 0; i < data_length; i++) { - if (data[i] == 0x7d) { - i++; - decoded[dec_index++] = data[i] ^ 0x20; - } else { - decoded[dec_index++] = data[i]; - } + + } else if (!strncmp(cmd, "jtag_reset", 10)) { // jtag_reset + reply = strdup("OK"); + ret = stlink_jtag_reset(sl, 0); + + if (ret) { + DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); + reply = strdup("E00"); } - // fix alignment - if (dec_index % 2 != 0) dec_index++; + ret = stlink_jtag_reset(sl, 1); - DLOG("binary packet %d -> %d\n", data_length, dec_index); + if (ret) { + DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); + reply = strdup("E00"); + } - if (flash_populate(addr, decoded, dec_index) < 0) { + ret = stlink_force_debug(sl); + + if (ret) { + DLOG("Rcmd: jtag_reset failed with force_debug\n"); reply = strdup("E00"); - } else { - reply = strdup("OK"); } - free(decoded); - } else if (!strcmp(cmdName, "FlashDone")) { - if (flash_go(sl) < 0) { + if (strcmp(reply, "E00")) { + // no errors have been found + DLOG("Rcmd: jtag_reset\n"); + } + } else if (!strncmp(cmd, "reset", 5)) { // reset + + ret = stlink_force_debug(sl); + + if (ret) { + DLOG("Rcmd: reset failed with force_debug\n"); reply = strdup("E00"); - } else { - reply = strdup("OK"); } - } else if (!strcmp(cmdName, "Kill")) { - attached = 0; - reply = strdup("OK"); - } - if (reply == NULL) - reply = strdup(""); + ret = stlink_reset(sl); - break; - } + if (ret) { + DLOG("Rcmd: reset failed with reset\n"); + reply = strdup("E00"); + } + + init_code_breakpoints(sl); + init_data_watchpoints(sl); - case 'c': - cache_sync(sl); - ret = stlink_run(sl); - if (ret) DLOG("Semihost: run failed\n"); - - while (1) { - status = gdb_check_for_interrupt(client); - if (status < 0) { - ELOG("cannot check for int: %d\n", status); - close_socket(client); - return 1; + if (reply == NULL) { + reply = strdup("OK"); + DLOG("Rcmd: reset\n"); } - if (status == 1) { - stlink_force_debug(sl); - break; + } else if (!strncmp(cmd, "semihosting ", 12)) { + DLOG("Rcmd: got semihosting cmd '%s'", cmd); + char *arg = cmd + 12; + + while (isspace(*arg)) { arg++; } // skip whitespaces + + if (!strncmp(arg, "enable", 6) || !strncmp(arg, "1", 1)) { + semihosting = true; + reply = strdup("OK"); + } else if (!strncmp(arg, "disable", 7) || !strncmp(arg, "0", 1)) { + semihosting = false; + reply = strdup("OK"); + } else { + DLOG("Rcmd: unknown semihosting arg: '%s'\n", arg); } + } else { + DLOG("Rcmd: %s\n", cmd); + } - ret = stlink_status(sl); - if (ret) DLOG("Semihost: status failed\n"); - if(sl->core_stat == TARGET_HALTED) { - struct stlink_reg reg; - stm32_addr_t pc; - stm32_addr_t addr; - int offset = 0; - uint16_t insn; + free(cmd); + } - if (!semihosting) break; + if (reply == NULL) { reply = strdup(""); } - ret = stlink_read_all_regs (sl, ®); - if (ret) DLOG("Semihost: read_all_regs failed\n"); + free(queryName); + break; + } - // Read PC - pc = reg.r[15]; + case 'v': { + char *params = NULL; + char *cmdName = strtok_r(packet, ":;", ¶ms); - // Compute aligned value - offset = pc % 4; - addr = pc - offset; + cmdName++; // vCommand -> Command - // Read instructions (address and length must be aligned). - ret = stlink_read_mem32(sl, addr, (offset > 2 ? 8 : 4)); + if (!strcmp(cmdName, "FlashErase")) { + char *__s_addr, *s_length; + char *tok = params; - if (ret != 0) { - DLOG("Semihost: cannot read instructions at: 0x%08x\n", addr); - break; - } + __s_addr = strsep(&tok, ","); + s_length = tok; - memcpy(&insn, &sl->q_buf[offset], sizeof(insn)); + unsigned addr = (unsigned int)strtoul(__s_addr, NULL, 16), + length = (unsigned int)strtoul(s_length, NULL, 16); - if (insn == 0xBEAB && !has_breakpoint(addr)) { + DLOG("FlashErase: addr:%08x,len:%04x\n", + addr, length); - ret = do_semihosting (sl, reg.r[0], reg.r[1], ®.r[0]); - if (ret) DLOG("Semihost: do_semihosting failed\n"); + if (flash_add_block(addr, length, sl) < 0) { + reply = strdup("E00"); + } else { + reply = strdup("OK"); + } + } else if (!strcmp(cmdName, "FlashWrite")) { + char *__s_addr, *data; + char *tok = params; - // Write return value - ret = stlink_write_reg(sl, reg.r[0], 0); - if (ret) DLOG("Semihost: write_reg failed for return value\n"); + __s_addr = strsep(&tok, ":"); + data = tok; - // Jump over the break instruction - ret = stlink_write_reg(sl, reg.r[15] + 2, 15); - if (ret) DLOG("Semihost: write_reg failed for jumping over break\n"); + unsigned addr = (unsigned int)strtoul(__s_addr, NULL, 16); + unsigned data_length = status - (unsigned int)(data - packet); - // Continue execution - cache_sync(sl); - ret = stlink_run(sl); - if (ret) DLOG("Semihost: continue execution failed with stlink_run\n"); - } else { - break; - } - } + // Length of decoded data cannot be more than encoded, as escapes are removed. + // Additional byte is reserved for alignment fix. + uint8_t *decoded = calloc(data_length + 1, 1); + unsigned dec_index = 0; - usleep(100000); + for (unsigned int i = 0; i < data_length; i++) { + if (data[i] == 0x7d) { + i++; + decoded[dec_index++] = data[i] ^ 0x20; + } else { + decoded[dec_index++] = data[i]; + } } - reply = strdup("S05"); // TRAP - break; + // fix alignment + if (dec_index % 2 != 0) { dec_index++; } + + DLOG("binary packet %d -> %d\n", data_length, dec_index); - case 's': - cache_sync(sl); - ret = stlink_step(sl); - if (ret) { - // ... having a problem sending step packet - ELOG("Step: cannot send step request\n"); + if (flash_populate(addr, decoded, dec_index) < 0) { reply = strdup("E00"); - critical_error = 1; // absolutely critical } else { - reply = strdup("S05"); // TRAP + reply = strdup("OK"); } - break; - - case '?': - if (attached) { - reply = strdup("S05"); // TRAP + free(decoded); + } else if (!strcmp(cmdName, "FlashDone")) { + if (flash_go(sl) < 0) { + reply = strdup("E00"); } else { - // Stub shall reply OK if not attached. reply = strdup("OK"); } - break; + } else if (!strcmp(cmdName, "Kill")) { + attached = 0; + reply = strdup("OK"); + } - case 'g': - ret = stlink_read_all_regs(sl, ®p); - if (ret) DLOG("g packet: read_all_regs failed\n"); + if (reply == NULL) { reply = strdup(""); } - reply = calloc(8 * 16 + 1, 1); - for (int i = 0; i < 16; i++) - sprintf(&reply[i * 8], "%08x", (uint32_t)htonl(regp.r[i])); - break; + break; + } - case 'p': { - unsigned id = (unsigned int) strtoul(&packet[1], NULL, 16); - unsigned myreg = 0xDEADDEAD; - - if (id < 16) { - ret = stlink_read_reg(sl, id, ®p); - myreg = htonl(regp.r[id]); - } else if (id == 0x19) { - ret = stlink_read_reg(sl, 16, ®p); - myreg = htonl(regp.xpsr); - } else if (id == 0x1A) { - ret = stlink_read_reg(sl, 17, ®p); - myreg = htonl(regp.main_sp); - } else if (id == 0x1B) { - ret = stlink_read_reg(sl, 18, ®p); - myreg = htonl(regp.process_sp); - } else if (id == 0x1C) { - ret = stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.control); - } else if (id == 0x1D) { - ret = stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.faultmask); - } else if (id == 0x1E) { - ret = stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.basepri); - } else if (id == 0x1F) { - ret = stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.primask); - } else if (id >= 0x20 && id < 0x40) { - ret = stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.s[id-0x20]); - } else if (id == 0x40) { - ret = stlink_read_unsupported_reg(sl, id, ®p); - myreg = htonl(regp.fpscr); - } else { - ret = 1; - reply = strdup("E00"); + case 'c': + cache_sync(sl); + ret = stlink_run(sl); + + if (ret) { DLOG("Semihost: run failed\n"); } + + while (1) { + status = gdb_check_for_interrupt(client); + + if (status < 0) { + ELOG("cannot check for int: %d\n", status); + close_socket(client); + return(1); } - if (ret) DLOG("p packet: stlink_read_unsupported_reg failed with id %u\n", id); - if (reply == NULL) { - // If reply is set to "E00", skip - reply = calloc(8 + 1, 1); - sprintf(reply, "%08x", myreg); + if (status == 1) { + stlink_force_debug(sl); + break; } - break; - } + ret = stlink_status(sl); - case 'P': { - char* s_reg = &packet[1]; - char* s_value = strstr(&packet[1], "=") + 1; - - unsigned reg = (unsigned int) strtoul(s_reg, NULL, 16); - unsigned value = (unsigned int) strtoul(s_value, NULL, 16); - - - if (reg < 16) { - ret = stlink_write_reg(sl, ntohl(value), reg); - } else if (reg == 0x19) { - ret = stlink_write_reg(sl, ntohl(value), 16); - } else if (reg == 0x1A) { - ret = stlink_write_reg(sl, ntohl(value), 17); - } else if (reg == 0x1B) { - ret = stlink_write_reg(sl, ntohl(value), 18); - } else if (reg == 0x1C) { - ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if (reg == 0x1D) { - ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if (reg == 0x1E) { - ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if (reg == 0x1F) { - ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if (reg >= 0x20 && reg < 0x40) { - ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else if (reg == 0x40) { - ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); - } else { - ret = 1; - reply = strdup("E00"); + if (ret) { DLOG("Semihost: status failed\n"); } + + if (sl->core_stat == TARGET_HALTED) { + struct stlink_reg reg; + stm32_addr_t pc; + stm32_addr_t addr; + int offset = 0; + uint16_t insn; + + if (!semihosting) { break; } + + ret = stlink_read_all_regs (sl, ®); + + if (ret) { DLOG("Semihost: read_all_regs failed\n"); } + + // read PC + pc = reg.r[15]; + + // compute aligned value + offset = pc % 4; + addr = pc - offset; + + // read instructions (address and length must be aligned). + ret = stlink_read_mem32(sl, addr, (offset > 2 ? 8 : 4)); + + if (ret != 0) { + DLOG("Semihost: cannot read instructions at: 0x%08x\n", addr); + break; + } + + memcpy(&insn, &sl->q_buf[offset], sizeof(insn)); + + if (insn == 0xBEAB && !has_breakpoint(addr)) { + + ret = do_semihosting (sl, reg.r[0], reg.r[1], ®.r[0]); + + if (ret) { DLOG("Semihost: do_semihosting failed\n"); } + + // write return value + ret = stlink_write_reg(sl, reg.r[0], 0); + + if (ret) { DLOG("Semihost: write_reg failed for return value\n"); } + + // jump over the break instruction + ret = stlink_write_reg(sl, reg.r[15] + 2, 15); + + if (ret) { DLOG("Semihost: write_reg failed for jumping over break\n"); } + + // continue execution + cache_sync(sl); + ret = stlink_run(sl); + + if (ret) { DLOG("Semihost: continue execution failed with stlink_run\n"); } + } else { + break; + } } - if (ret) DLOG("P packet: stlink_write_unsupported_reg failed with reg %u\n", reg); - if (reply == NULL) reply = strdup("OK"); // note that NULL may not be zero - break; + usleep(100000); } - case 'G': - for (int i = 0; i < 16; i++) { - char str[9] = {0}; - strncpy(str, &packet[1 + i * 8], 8); - uint32_t reg = (uint32_t) strtoul(str, NULL, 16); - ret = stlink_write_reg(sl, ntohl(reg), i); - if (ret) DLOG("G packet: stlink_write_reg failed"); - } + reply = strdup("S05"); // TRAP + break; - reply = strdup("OK"); - break; + case 's': + cache_sync(sl); + ret = stlink_step(sl); - case 'm': { - char* s_start = &packet[1]; - char* s_count = strstr(&packet[1], ",") + 1; + if (ret) { + // ... having a problem sending step packet + ELOG("Step: cannot send step request\n"); + reply = strdup("E00"); + critical_error = 1; // absolutely critical + } else { + reply = strdup("S05"); // TRAP + } - stm32_addr_t start = (stm32_addr_t) strtoul(s_start, NULL, 16); - unsigned count = (unsigned int) strtoul(s_count, NULL, 16); + break; - unsigned adj_start = start % 4; - unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; - if (count_rnd > sl->flash_pgsz) count_rnd = (unsigned int) sl->flash_pgsz; - if (count_rnd > 0x1800) count_rnd = 0x1800; - if (count_rnd < count) count = count_rnd; + case '?': - if (stlink_read_mem32(sl, start - adj_start, count_rnd) != 0) count = 0; - // read failed somehow, don't return stale buffer + if (attached) { + reply = strdup("S05"); // TRAP + } else { + reply = strdup("OK"); // stub shall reply OK if not attached + } - reply = calloc(count * 2 + 1, 1); - for (unsigned int i = 0; i < count; i++) { - reply[i * 2 + 0] = hex[sl->q_buf[i + adj_start] >> 4]; - reply[i * 2 + 1] = hex[sl->q_buf[i + adj_start] & 0xf]; - } + break; - break; + case 'g': + ret = stlink_read_all_regs(sl, ®p); + + if (ret) { DLOG("g packet: read_all_regs failed\n"); } + + reply = calloc(8 * 16 + 1, 1); + + for (int i = 0; i < 16; i++) { + sprintf(&reply[i * 8], "%08x", (uint32_t)htonl(regp.r[i])); } - case 'M': { - char* s_start = &packet[1]; - char* s_count = strstr(&packet[1], ",") + 1; - char* hexdata = strstr(packet, ":") + 1; - - stm32_addr_t start = (stm32_addr_t) strtoul(s_start, NULL, 16); - unsigned count = (unsigned int) strtoul(s_count, NULL, 16); - int err = 0; - - if (start % 4) { - unsigned align_count = 4 - start % 4; - if (align_count > count) align_count = count; - for (unsigned int i = 0; i < align_count; i ++) { - char hextmp[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; - uint8_t byte = strtoul(hextmp, NULL, 16); - sl->q_buf[i] = byte; - } - err |= stlink_write_mem8(sl, start, align_count); - cache_change(start, align_count); - start += align_count; - count -= align_count; - hexdata += 2*align_count; - } + break; - if (count - count % 4) { - unsigned aligned_count = count - count % 4; + case 'p': { + unsigned id = (unsigned int)strtoul(&packet[1], NULL, 16); + unsigned myreg = 0xDEADDEAD; + + if (id < 16) { + ret = stlink_read_reg(sl, id, ®p); + myreg = htonl(regp.r[id]); + } else if (id == 0x19) { + ret = stlink_read_reg(sl, 16, ®p); + myreg = htonl(regp.xpsr); + } else if (id == 0x1A) { + ret = stlink_read_reg(sl, 17, ®p); + myreg = htonl(regp.main_sp); + } else if (id == 0x1B) { + ret = stlink_read_reg(sl, 18, ®p); + myreg = htonl(regp.process_sp); + } else if (id == 0x1C) { + ret = stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.control); + } else if (id == 0x1D) { + ret = stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.faultmask); + } else if (id == 0x1E) { + ret = stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.basepri); + } else if (id == 0x1F) { + ret = stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.primask); + } else if (id >= 0x20 && id < 0x40) { + ret = stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.s[id - 0x20]); + } else if (id == 0x40) { + ret = stlink_read_unsupported_reg(sl, id, ®p); + myreg = htonl(regp.fpscr); + } else { + ret = 1; + reply = strdup("E00"); + } - for (unsigned int i = 0; i < aligned_count; i ++) { - char hextmp[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; - uint8_t byte = strtoul(hextmp, NULL, 16); - sl->q_buf[i] = byte; - } - err |= stlink_write_mem32(sl, start, aligned_count); - cache_change(start, aligned_count); - count -= aligned_count; - start += aligned_count; - hexdata += 2*aligned_count; - } + if (ret) { DLOG("p packet: stlink_read_unsupported_reg failed with id %u\n", id); } - if (count) { - for (unsigned int i = 0; i < count; i ++) { - char hextmp[3] = { hexdata[i*2], hexdata[i*2+1], 0 }; - uint8_t byte = strtoul(hextmp, NULL, 16); - sl->q_buf[i] = byte; - } - err |= stlink_write_mem8(sl, start, count); - cache_change(start, count); - } - reply = strdup(err ? "E00" : "OK"); - break; + if (reply == NULL) { + // if reply is set to "E00", skip + reply = calloc(8 + 1, 1); + sprintf(reply, "%08x", myreg); } - case 'Z': { - char *endptr; - stm32_addr_t addr = (stm32_addr_t) strtoul(&packet[3], &endptr, 16); - stm32_addr_t len = (stm32_addr_t) strtoul(&endptr[1], NULL, 16); - - switch (packet[1]) { - case '1': - if (update_code_breakpoint(sl, addr, 1) < 0) { - reply = strdup("E00"); - } else { - reply = strdup("OK"); - } - break; + break; + } - case '2': // insert write watchpoint - case '3': // insert read watchpoint - case '4': { // insert access watchpoint - enum watchfun wf; - if (packet[1] == '2') { - wf = WATCHWRITE; - } else if (packet[1] == '3') { - wf = WATCHREAD; - } else { - wf = WATCHACCESS; - } - - if (add_data_watchpoint(sl, wf, addr, len) < 0) { - reply = strdup("E00"); - } else { - reply = strdup("OK"); - break; - } - } - break; + case 'P': { + char* s_reg = &packet[1]; + char* s_value = strstr(&packet[1], "=") + 1; + + unsigned reg = (unsigned int)strtoul(s_reg, NULL, 16); + unsigned value = (unsigned int)strtoul(s_value, NULL, 16); + + + if (reg < 16) { + ret = stlink_write_reg(sl, ntohl(value), reg); + } else if (reg == 0x19) { + ret = stlink_write_reg(sl, ntohl(value), 16); + } else if (reg == 0x1A) { + ret = stlink_write_reg(sl, ntohl(value), 17); + } else if (reg == 0x1B) { + ret = stlink_write_reg(sl, ntohl(value), 18); + } else if (reg == 0x1C) { + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if (reg == 0x1D) { + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if (reg == 0x1E) { + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if (reg == 0x1F) { + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if (reg >= 0x20 && reg < 0x40) { + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else if (reg == 0x40) { + ret = stlink_write_unsupported_reg(sl, ntohl(value), reg, ®p); + } else { + ret = 1; + reply = strdup("E00"); + } - default: - reply = strdup(""); - } - break; + if (ret) { DLOG("P packet: stlink_write_unsupported_reg failed with reg %u\n", reg); } + + if (reply == NULL) { reply = strdup("OK"); /* Note: NULL may not be zero */ } + + break; + } + + case 'G': + + for (int i = 0; i < 16; i++) { + char str[9] = {0}; + strncpy(str, &packet[1 + i * 8], 8); + uint32_t reg = (uint32_t)strtoul(str, NULL, 16); + ret = stlink_write_reg(sl, ntohl(reg), i); + + if (ret) { DLOG("G packet: stlink_write_reg failed"); } } - case 'z': { - char *endptr; - stm32_addr_t addr = (stm32_addr_t) strtoul(&packet[3], &endptr, 16); - //stm32_addr_t len = strtoul(&endptr[1], NULL, 16); - - switch (packet[1]) { - case '1': // remove breakpoint - update_code_breakpoint(sl, addr, 0); - reply = strdup("OK"); - break; - case '2' : // remove write watchpoint - case '3' : // remove read watchpoint - case '4' : // remove access watchpoint - if (delete_data_watchpoint(sl, addr) < 0) { - reply = strdup("E00"); - break; - } else { - reply = strdup("OK"); - break; - } - - default: - reply = strdup(""); - } - break; + reply = strdup("OK"); + break; + + case 'm': { + char* s_start = &packet[1]; + char* s_count = strstr(&packet[1], ",") + 1; + + stm32_addr_t start = (stm32_addr_t)strtoul(s_start, NULL, 16); + unsigned count = (unsigned int)strtoul(s_count, NULL, 16); + + unsigned adj_start = start % 4; + unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; + + if (count_rnd > sl->flash_pgsz) { count_rnd = (unsigned int)sl->flash_pgsz; } + + if (count_rnd > 0x1800) { count_rnd = 0x1800; } + + if (count_rnd < count) { count = count_rnd; } + + if (stlink_read_mem32(sl, start - adj_start, count_rnd) != 0) { count = 0; } + + // read failed somehow, don't return stale buffer + + reply = calloc(count * 2 + 1, 1); + + for (unsigned int i = 0; i < count; i++) { + reply[i * 2 + 0] = hex[sl->q_buf[i + adj_start] >> 4]; + reply[i * 2 + 1] = hex[sl->q_buf[i + adj_start] & 0xf]; } - case '!': { - // Enter extended mode which allows restarting. We do support that always. + break; + } - // Also, set to persistent mode to allow GDB disconnect. - st->persistent = 1; + case 'M': { + char* s_start = &packet[1]; + char* s_count = strstr(&packet[1], ",") + 1; + char* hexdata = strstr(packet, ":") + 1; - reply = strdup("OK"); + stm32_addr_t start = (stm32_addr_t)strtoul(s_start, NULL, 16); + unsigned count = (unsigned int)strtoul(s_count, NULL, 16); + int err = 0; - break; + if (start % 4) { + unsigned align_count = 4 - start % 4; + + if (align_count > count) { align_count = count; } + + for (unsigned int i = 0; i < align_count; i++) { + char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; + uint8_t byte = strtoul(hextmp, NULL, 16); + sl->q_buf[i] = byte; + } + + err |= stlink_write_mem8(sl, start, align_count); + cache_change(start, align_count); + start += align_count; + count -= align_count; + hexdata += 2 * align_count; } - case 'R': { - // Reset the core. - ret = stlink_reset(sl); - if (ret) { - DLOG("R packet : stlink_reset failed\n"); + if (count - count % 4) { + unsigned aligned_count = count - count % 4; + + for (unsigned int i = 0; i < aligned_count; i++) { + char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; + uint8_t byte = strtoul(hextmp, NULL, 16); + sl->q_buf[i] = byte; } - init_code_breakpoints(sl); - init_data_watchpoints(sl); - attached = 1; + err |= stlink_write_mem32(sl, start, aligned_count); + cache_change(start, aligned_count); + count -= aligned_count; + start += aligned_count; + hexdata += 2 * aligned_count; + } - reply = strdup("OK"); + if (count) { + for (unsigned int i = 0; i < count; i++) { + char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; + uint8_t byte = strtoul(hextmp, NULL, 16); + sl->q_buf[i] = byte; + } + + err |= stlink_write_mem8(sl, start, count); + cache_change(start, count); + } + + reply = strdup(err ? "E00" : "OK"); + break; + } + + case 'Z': { + char *endptr; + stm32_addr_t addr = (stm32_addr_t)strtoul(&packet[3], &endptr, 16); + stm32_addr_t len = (stm32_addr_t)strtoul(&endptr[1], NULL, 16); + + switch (packet[1]) { + case '1': + + if (update_code_breakpoint(sl, addr, 1) < 0) { + reply = strdup("E00"); + } else { + reply = strdup("OK"); + } break; + + case '2': // insert write watchpoint + case '3': // insert read watchpoint + case '4': { // insert access watchpoint + enum watchfun wf; + + if (packet[1] == '2') { + wf = WATCHWRITE; + } else if (packet[1] == '3') { + wf = WATCHREAD; + } else { + wf = WATCHACCESS; + } + + if (add_data_watchpoint(sl, wf, addr, len) < 0) { + reply = strdup("E00"); + } else { + reply = strdup("OK"); + break; + } } - case 'k': - // Kill request - reset the connection itself - ret = stlink_run(sl); - if (ret) DLOG("Kill: stlink_run failed\n"); - ret = stlink_exit_debug_mode(sl); - if (ret) DLOG("Kill: stlink_exit_debug_mode failed\n"); - stlink_close(sl); - - sl = do_connect(st); - if (sl == NULL || sl->chip_id == STLINK_CHIPID_UNKNOWN) cleanup(0); - connected_stlink = sl; - - if (st->reset) stlink_reset(sl); - ret = stlink_force_debug(sl); - if (ret) DLOG("Kill: stlink_force_debug failed\n"); - init_cache(sl); - init_code_breakpoints(sl); - init_data_watchpoints(sl); - - reply = NULL; // no response + break; + default: + reply = strdup(""); + } + break; + } + case 'z': { + char *endptr; + stm32_addr_t addr = (stm32_addr_t)strtoul(&packet[3], &endptr, 16); + // stm32_addr_t len = strtoul(&endptr[1], NULL, 16); + + switch (packet[1]) { + case '1': // remove breakpoint + update_code_breakpoint(sl, addr, 0); + reply = strdup("OK"); break; + case '2': // remove write watchpoint + case '3': // remove read watchpoint + case '4': // remove access watchpoint + + if (delete_data_watchpoint(sl, addr) < 0) { + reply = strdup("E00"); + break; + } else { + reply = strdup("OK"); + break; + } + default: reply = strdup(""); + } + break; + } + + case '!': { + // enter extended mode which allows restarting. We do support that always. + // also, set to persistent mode to allow GDB disconnect. + st->persistent = 1; + + reply = strdup("OK"); + break; + } + + case 'R': { + // reset the core. + ret = stlink_reset(sl); + + if (ret) { DLOG("R packet : stlink_reset failed\n"); } + + init_code_breakpoints(sl); + init_data_watchpoints(sl); + + attached = 1; + + reply = strdup("OK"); + break; + } + case 'k': + // kill request - reset the connection itself + ret = stlink_run(sl); + + if (ret) { DLOG("Kill: stlink_run failed\n"); } + + ret = stlink_exit_debug_mode(sl); + + if (ret) { DLOG("Kill: stlink_exit_debug_mode failed\n"); } + + stlink_close(sl); + + sl = do_connect(st); + + if (sl == NULL || sl->chip_id == STLINK_CHIPID_UNKNOWN) { cleanup(0); } + + connected_stlink = sl; + + if (st->reset) { stlink_reset(sl); } + + ret = stlink_force_debug(sl); + + if (ret) { DLOG("Kill: stlink_force_debug failed\n"); } + + init_cache(sl); + init_code_breakpoints(sl); + init_data_watchpoints(sl); + + reply = NULL; // no response + break; + + default: + reply = strdup(""); } if (reply) { DLOG("send: %s\n", reply); int result = gdb_send_packet(client, reply); + if (result != 0) { ELOG("cannot send: %d\n", result); free(reply); free(packet); close_socket(client); - return 1; + return(1); } free(reply); @@ -1750,13 +1859,12 @@ int serve(stlink_t *sl, st_state_t *st) { if (critical_error) { close_socket(client); - return 1; + return(1); } free(packet); } close_socket(client); - - return 0; + return(0); } diff --git a/src/st-util/gdb-server.h b/src/st-util/gdb-server.h index 8c8d47114..b50a7941d 100644 --- a/src/st-util/gdb-server.h +++ b/src/st-util/gdb-server.h @@ -8,4 +8,4 @@ #define DEBUG_LOGGING_LEVEL 100 #define DEFAULT_GDB_LISTEN_PORT 4242 -#endif +#endif // _GDB_SERVER_H diff --git a/src/st-util/semihosting.c b/src/st-util/semihosting.c index cb03868cd..821dcdbbb 100644 --- a/src/st-util/semihosting.c +++ b/src/st-util/semihosting.c @@ -13,13 +13,13 @@ static int mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { int offset = addr % 4; int len = 4; - if (sl == NULL || data == NULL) return -1; + if (sl == NULL || data == NULL) { return(-1); } - /* Read address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, len) != 0) return -1; + // read address and length must be aligned + if (stlink_read_mem32(sl, addr - offset, len) != 0) { return(-1); } *data = sl->q_buf[offset]; - return 0; + return(0); } #ifdef UNUSED @@ -27,26 +27,26 @@ static int mem_read_u16(stlink_t *sl, uint32_t addr, uint16_t *data) { int offset = addr % 4; int len = (offset > 2 ? 8 : 4); - if (sl == NULL || data == NULL) return -1; + if (sl == NULL || data == NULL) { return(-1); } - /* Read address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, len) != 0) return -1; + // read address and length must be aligned + if (stlink_read_mem32(sl, addr - offset, len) != 0) { return(-1); } memcpy(data, &sl->q_buf[offset], sizeof(*data)); - return 0; + return(0); } static int mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) { int offset = addr % 4; int len = (offset > 0 ? 8 : 4); - if (sl == NULL || data == NULL) return -1; + if (sl == NULL || data == NULL) { return(-1); } - /* Read address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, len) != 0) return -1; + // read address and length must be aligned + if (stlink_read_mem32(sl, addr - offset, len) != 0) { return(-1); } memcpy(data, &sl->q_buf[offset], sizeof(*data)); - return 0; + return(0); } #endif @@ -54,50 +54,42 @@ static int mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { int offset = addr % 4; int read_len = len + offset; - if (sl == NULL || data == NULL) return -1; + if (sl == NULL || data == NULL) { return(-1); } - /* Align read size */ - if ((read_len % 4) != 0) { - read_len += 4 - (read_len % 4); - } + // align read size + if ((read_len % 4) != 0) { read_len += 4 - (read_len % 4); } - /* Address and length must be aligned */ - if (stlink_read_mem32(sl, addr - offset, read_len) != 0) return -1; + // address and length must be aligned + if (stlink_read_mem32(sl, addr - offset, read_len) != 0) { return(-1); } memcpy(data, &sl->q_buf[offset], len); - return 0; + return(0); } static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { - // Note: this function can write more than it is asked to! - // If addr is not an even 32 bit boundary, or len is not a multiple of 4. - // - // If only 32 bit values can be written to the target, - // then this function should read the target memory at the - // start and end of the buffer where it will write more that - // the requested bytes. (perhaps reading the whole area is faster??). - // - // If 16 and 8 bit writes are available, then they could be used instead. - - // Just return when the length is zero avoiding unneeded work. - if (len == 0) return 0; + /* Note: this function can write more than it is asked to! + * If addr is not an even 32 bit boundary, or len is not a multiple of 4. + * If only 32 bit values can be written to the target, then this function should read + * the target memory at the start and end of the buffer where it will write more that + * the requested bytes. (perhaps reading the whole area is faster??). + * If 16 and 8 bit writes are available, then they could be used instead. + * Just return when the length is zero avoiding unneeded work. */ + if (len == 0) { return(0); } int offset = addr % 4; int write_len = len + offset; - if (sl == NULL || data == NULL) return -1; + if (sl == NULL || data == NULL) { return(-1); } - /* Align read size */ - if ((write_len % 4) != 0) { - write_len += 4 - (write_len % 4); - } + // align read size + if ((write_len % 4) != 0) { write_len += 4 - (write_len % 4); } memcpy(&sl->q_buf[offset], data, len); - /* Address and length must be aligned */ - if (stlink_write_mem32(sl, addr - offset, write_len) != 0) return -1; + // address and length must be aligned + if (stlink_write_mem32(sl, addr - offset, write_len) != 0) { return(-1); } - return 0; + return(0); } /* For the SYS_WRITE0 call, we don't know the size of the null-terminated buffer @@ -137,7 +129,7 @@ static int saved_errno = 0; int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { - if (sl == NULL || ret == NULL) return -1; + if (sl == NULL || ret == NULL) { return(-1); } DLOG("Do semihosting R0=0x%08x R1=0x%08x\n", r0, r1); @@ -150,11 +142,10 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { uint32_t name_len; char *name; - if (mem_read(sl, r1, args, sizeof (args)) != 0){ - DLOG("Semihosting SYS_OPEN error: " - "cannot read args from target memory\n"); + if (mem_read(sl, r1, args, sizeof(args)) != 0) { + DLOG("Semihosting SYS_OPEN error: cannot read args from target memory\n"); *ret = -1; - return -1; + return(-1); } name_address = args[0]; @@ -165,7 +156,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { /* Invalid mode */ DLOG("Semihosting SYS_OPEN error: invalid mode %d\n", mode); *ret = -1; - return -1; + return(-1); } /* Add the trailing zero that is not counted in the length argument (see @@ -174,25 +165,24 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { name_len += 1; if (name_len > MAX_BUFFER_SIZE) { - DLOG("Semihosting SYS_OPEN error: name buffer size is too big %d\n", - name_len); + DLOG("Semihosting SYS_OPEN error: name buffer size is too big %d\n", name_len); *ret = -1; - return -1; + return(-1); } + name = malloc(name_len); if (name == NULL) { DLOG("Semihosting SYS_OPEN error: cannot allocate name buffer\n"); *ret = -1; - return -1; + return(-1); } - if (mem_read(sl, name_address, name, name_len) != 0){ + if (mem_read(sl, name_address, name, name_len) != 0) { free(name); *ret = -1; - DLOG("Semihosting SYS_OPEN error: " - "cannot read name from target memory\n"); - return -1; + DLOG("Semihosting SYS_OPEN error: cannot read name from target memory\n"); + return(-1); } DLOG("Semihosting: open('%s', (SH open mode)%d, 0644)\n", name, mode); @@ -208,13 +198,12 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { case SEMIHOST_SYS_CLOSE: { uint32_t args[1]; - int fd; + int fd; - if (mem_read(sl, r1, args, sizeof (args)) != 0){ - DLOG("Semihosting SYS_CLOSE error: " - "cannot read args from target memory\n"); + if (mem_read(sl, r1, args, sizeof(args)) != 0) { + DLOG("Semihosting SYS_CLOSE error: cannot read args from target memory\n"); *ret = -1; - return -1; + return(-1); } fd = (int)args[0]; @@ -231,15 +220,14 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { { uint32_t args[3]; uint32_t buffer_address; - int fd; + int fd; uint32_t buffer_len; void *buffer; - if (mem_read(sl, r1, args, sizeof (args)) != 0){ - DLOG("Semihosting SYS_WRITE error: " - "cannot read args from target memory\n"); + if (mem_read(sl, r1, args, sizeof(args)) != 0) { + DLOG("Semihosting SYS_WRITE error: cannot read args from target memory\n"); *ret = -1; - return -1; + return(-1); } fd = (int)args[0]; @@ -248,9 +236,9 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (buffer_len > MAX_BUFFER_SIZE) { DLOG("Semihosting SYS_WRITE error: buffer size is too big %d\n", - buffer_len); + buffer_len); *ret = buffer_len; - return -1; + return(-1); } buffer = malloc(buffer_len); @@ -258,19 +246,18 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (buffer == NULL) { DLOG("Semihosting SYS_WRITE error: cannot allocate buffer\n"); *ret = buffer_len; - return -1; + return(-1); } - if (mem_read(sl, buffer_address, buffer, buffer_len) != 0){ - DLOG("Semihosting SYS_WRITE error: " - "cannot read buffer from target memory\n"); + if (mem_read(sl, buffer_address, buffer, buffer_len) != 0) { + DLOG("Semihosting SYS_WRITE error: cannot read buffer from target memory\n"); free(buffer); *ret = buffer_len; - return -1; + return(-1); } - DLOG("Semihosting: write(%d, target_addr:0x%08x, %zu)\n", fd, - buffer_address, buffer_len); + DLOG("Semihosting: write(%d, target_addr:0x%08x, %zu)\n", fd, buffer_address, + buffer_len); *ret = (uint32_t)write(fd, buffer, buffer_len); saved_errno = errno; @@ -289,16 +276,15 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { { uint32_t args[3]; uint32_t buffer_address; - int fd; + int fd; uint32_t buffer_len; void *buffer; - ssize_t read_result; + ssize_t read_result; - if (mem_read(sl, r1, args, sizeof (args)) != 0){ - DLOG("Semihosting SYS_READ error: " - "cannot read args from target memory\n"); + if (mem_read(sl, r1, args, sizeof(args)) != 0) { + DLOG("Semihosting SYS_READ error: cannot read args from target memory\n"); *ret = -1; - return -1; + return(-1); } fd = (int)args[0]; @@ -306,10 +292,9 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { buffer_len = args[2]; if (buffer_len > MAX_BUFFER_SIZE) { - DLOG("Semihosting SYS_READ error: buffer size is too big %d\n", - buffer_len); + DLOG("Semihosting SYS_READ error: buffer size is too big %d\n", buffer_len); *ret = buffer_len; - return -1; + return(-1); } buffer = malloc(buffer_len); @@ -317,11 +302,11 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (buffer == NULL) { DLOG("Semihosting SYS_READ error: cannot allocatebuffer\n"); *ret = buffer_len; - return -1; + return(-1); } - DLOG("Semihosting: read(%d, target_addr:0x%08x, %zu)\n", fd, - buffer_address, buffer_len); + DLOG("Semihosting: read(%d, target_addr:0x%08x, %zu)\n", fd, buffer_address, + buffer_len); read_result = read(fd, buffer, buffer_len); saved_errno = errno; @@ -329,12 +314,11 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (read_result == -1) { *ret = buffer_len; } else { - if (mem_write(sl, buffer_address, buffer, read_result) != 0){ - DLOG("Semihosting SYS_READ error: " - "cannot write buffer to target memory\n"); + if (mem_write(sl, buffer_address, buffer, read_result) != 0) { + DLOG("Semihosting SYS_READ error: cannot write buffer to target memory\n"); free(buffer); *ret = buffer_len; - return -1; + return(-1); } else { *ret = buffer_len - (uint32_t)read_result; } @@ -357,11 +341,10 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { uint32_t name_len; char *name; - if (mem_read(sl, r1, args, sizeof (args)) != 0){ - DLOG("Semihosting SYS_REMOVE error: " - "cannot read args from target memory\n"); + if (mem_read(sl, r1, args, sizeof(args)) != 0) { + DLOG("Semihosting SYS_REMOVE error: cannot read args from target memory\n"); *ret = -1; - return -1; + return(-1); } name_address = args[0]; @@ -373,74 +356,68 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { name_len += 1; if (name_len > MAX_BUFFER_SIZE) { - DLOG("Semihosting SYS_REMOVE error: " - "name buffer size is too big %d\n", name_len); + DLOG("Semihosting SYS_REMOVE error: name buffer size is too big %d\n", + name_len); *ret = -1; - return -1; + return(-1); } + name = malloc(name_len); if (name == NULL) { DLOG("Semihosting SYS_REMOVE error: cannot allocate name buffer\n"); *ret = -1; - return -1; + return(-1); } - if (mem_read(sl, name_address, name, name_len) != 0){ + if (mem_read(sl, name_address, name, name_len) != 0) { free(name); *ret = -1; - DLOG("Semihosting SYS_REMOVE error: " - "cannot read name from target memory\n"); - return -1; + DLOG("Semihosting SYS_REMOVE error: cannot read name from target memory\n"); + return(-1); } DLOG("Semihosting: unlink('%s')\n", name); - *ret = (uint32_t)unlink(name); saved_errno = errno; - DLOG("Semihosting: return %d\n", *ret); - free(name); break; } case SEMIHOST_SYS_SEEK: { uint32_t args[2]; - int fd; - off_t offset; + int fd; + off_t offset; - if (mem_read(sl, r1, args, sizeof (args)) != 0){ - DLOG("Semihosting SYS_SEEK error: " - "cannot read args from target memory\n"); + if (mem_read(sl, r1, args, sizeof(args)) != 0) { + DLOG("Semihosting SYS_SEEK error: cannot read args from target memory\n"); *ret = -1; - return -1; + return(-1); } fd = (int)args[0]; offset = (off_t)args[1]; DLOG("Semihosting: lseek(%d, %d, SEEK_SET)\n", fd, offset); - *ret = (uint32_t)lseek(fd, offset, SEEK_SET); saved_errno = errno; - if (*ret != (uint32_t)-1) { - /* Success */ - *ret = 0; - } + if (*ret != (uint32_t)-1) { *ret = 0; /* Success */ } + DLOG("Semihosting: return %d\n", *ret); break; } case SEMIHOST_SYS_WRITEC: { uint8_t c; + if (mem_read_u8(sl, r1, &c) == 0) { fprintf(stderr, "%c", c); } else { - DLOG("Semihosting WRITEC: " - "cannot read target memory at 0x%08x\n", r1); + DLOG("Semihosting WRITEC: cannot read target memory at 0x%08x\n", r1); } + break; } case SEMIHOST_SYS_READC: @@ -454,24 +431,25 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { uint8_t buf[WRITE0_BUFFER_SIZE]; while (true) { - if (mem_read(sl, r1, buf, WRITE0_BUFFER_SIZE) != 0){ - DLOG("Semihosting WRITE0: " - "cannot read target memory at 0x%08x\n", r1); - return -1; + if (mem_read(sl, r1, buf, WRITE0_BUFFER_SIZE) != 0) { + DLOG("Semihosting WRITE0: cannot read target memory at 0x%08x\n", r1); + return(-1); } + for (int i = 0; i < WRITE0_BUFFER_SIZE; i++) { - if (buf[i] == 0) { - return 0; - } + if (buf[i] == 0) { return(0); } + fprintf(stderr, "%c", buf[i]); } + r1 += WRITE0_BUFFER_SIZE; } + break; } default: fprintf(stderr, "semihosting: unsupported call %#x\n", r0); - return -1; + return(-1); } - return 0; + return(0); } diff --git a/src/st-util/semihosting.h b/src/st-util/semihosting.h index 8157df9df..8c1ac15f0 100644 --- a/src/st-util/semihosting.h +++ b/src/st-util/semihosting.h @@ -29,6 +29,6 @@ #define SEMIHOST_SYS_ELAPSED 0x30 #define SEMIHOST_SYS_TICKFREQ 0x31 -int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret); +int do_semihosting(stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret); -#endif /* ! _SEMIHOSTING_H_ */ +#endif // _SEMIHOSTING_H_ diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index 7ae591f2d..ed38fcc7c 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -13,23 +13,23 @@ #define G_VALUE_INIT {0, {{0}}} #endif -G_DEFINE_TYPE (STlinkGUI, stlink_gui, G_TYPE_OBJECT); +G_DEFINE_TYPE(STlinkGUI, stlink_gui, G_TYPE_OBJECT); -static void stlink_gui_dispose (GObject *gobject) { - G_OBJECT_CLASS (stlink_gui_parent_class)->dispose (gobject); +static void stlink_gui_dispose(GObject *gobject) { + G_OBJECT_CLASS(stlink_gui_parent_class)->dispose(gobject); } -static void stlink_gui_finalize (GObject *gobject) { - G_OBJECT_CLASS (stlink_gui_parent_class)->finalize (gobject); +static void stlink_gui_finalize(GObject *gobject) { + G_OBJECT_CLASS(stlink_gui_parent_class)->finalize(gobject); } -static void stlink_gui_class_init (STlinkGUIClass *klass) { - GObjectClass *gobject_class = G_OBJECT_CLASS (klass); +static void stlink_gui_class_init(STlinkGUIClass *klass) { + GObjectClass *gobject_class = G_OBJECT_CLASS(klass); gobject_class->dispose = stlink_gui_dispose; gobject_class->finalize = stlink_gui_finalize; } -static void stlink_gui_init (STlinkGUI *self) { +static void stlink_gui_init(STlinkGUI *self) { self->sl = NULL; self->filename = NULL; @@ -45,162 +45,159 @@ static void stlink_gui_init (STlinkGUI *self) { self->file_mem.base = 0; } -static gboolean set_info_error_message_idle (STlinkGUI *gui) { +static gboolean set_info_error_message_idle(STlinkGUI *gui) { if (gui->error_message != NULL) { gchar *markup; - markup = g_markup_printf_escaped ("%s", gui->error_message); - gtk_label_set_markup (gui->infolabel, markup); - gtk_info_bar_set_message_type (gui->infobar, GTK_MESSAGE_ERROR); - gtk_widget_show (GTK_WIDGET (gui->infobar)); + markup = g_markup_printf_escaped("%s", gui->error_message); + gtk_label_set_markup(gui->infolabel, markup); + gtk_info_bar_set_message_type(gui->infobar, GTK_MESSAGE_ERROR); + gtk_widget_show(GTK_WIDGET(gui->infobar)); - g_free (markup); - g_free (gui->error_message); + g_free(markup); + g_free(gui->error_message); gui->error_message = NULL; } - return FALSE; + + return(FALSE); } -static void stlink_gui_set_info_error_message (STlinkGUI *gui, const gchar *message) { - gui->error_message = g_strdup (message); - g_idle_add ((GSourceFunc) set_info_error_message_idle, gui); +static void stlink_gui_set_info_error_message(STlinkGUI *gui, const gchar *message) { + gui->error_message = g_strdup(message); + g_idle_add((GSourceFunc)set_info_error_message_idle, gui); } -static void stlink_gui_set_sensitivity (STlinkGUI *gui, gboolean sensitivity) { - gtk_widget_set_sensitive (GTK_WIDGET (gui->open_button), sensitivity); - if (sensitivity && gui->sl) - gtk_widget_set_sensitive (GTK_WIDGET (gui->disconnect_button), sensitivity); - if (sensitivity && !gui->sl) - gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), sensitivity); - if (sensitivity && gui->sl && gui->filename) - gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), sensitivity); - gtk_widget_set_sensitive (GTK_WIDGET (gui->export_button), sensitivity && (gui->sl != NULL)); +static void stlink_gui_set_sensitivity(STlinkGUI *gui, gboolean sensitivity) { + gtk_widget_set_sensitive(GTK_WIDGET(gui->open_button), sensitivity); + + if (sensitivity && gui->sl) { + gtk_widget_set_sensitive(GTK_WIDGET(gui->disconnect_button), sensitivity); + } + + if (sensitivity && !gui->sl) { + gtk_widget_set_sensitive(GTK_WIDGET(gui->connect_button), sensitivity); + } + + if (sensitivity && gui->sl && gui->filename) { + gtk_widget_set_sensitive(GTK_WIDGET(gui->flash_button), sensitivity); + } + + gtk_widget_set_sensitive(GTK_WIDGET(gui->export_button), sensitivity && (gui->sl != NULL)); } -static void mem_view_init_headers (GtkTreeView *view) { +static void mem_view_init_headers(GtkTreeView *view) { GtkCellRenderer *renderer; - gint i; - - g_return_if_fail (view != NULL); - - renderer = gtk_cell_renderer_text_new (); - gtk_tree_view_insert_column_with_attributes ( - view, - -1, - "Address", - renderer, - "text", - 0, /* column */ - NULL); + gint i; + + g_return_if_fail(view != NULL); + + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_insert_column_with_attributes(view, -1, "Address", renderer, "text", 0, /* column */ NULL); + for (i = 0; i < 4; i++) { gchar *label; - label = g_strdup_printf ("%X", i * 4); - renderer = gtk_cell_renderer_text_new (); - gtk_tree_view_insert_column_with_attributes (view, - -1, - label, - renderer, - "text", - (i + 1), /* column */ - NULL); - g_free (label); + label = g_strdup_printf("%X", i * 4); + renderer = gtk_cell_renderer_text_new(); + gtk_tree_view_insert_column_with_attributes(view, -1, label, renderer, "text", (i + 1), /* column */ NULL); + g_free(label); } for (i = 0; i < 5; i++) { - GtkTreeViewColumn *column = gtk_tree_view_get_column (view, i); - gtk_tree_view_column_set_expand (column, TRUE); + GtkTreeViewColumn *column = gtk_tree_view_get_column(view, i); + gtk_tree_view_column_set_expand(column, TRUE); } } -static void mem_view_add_as_hex ( - GtkListStore *store, - GtkTreeIter *iter, - gint column, - guint32 value) { +static void mem_view_add_as_hex(GtkListStore *store, + GtkTreeIter *iter, + gint column, + guint32 value) { gchar *hex_str; - hex_str = g_strdup_printf ("0x%08X", value); + hex_str = g_strdup_printf("0x%08X", value); gtk_list_store_set(store, iter, column, hex_str, -1); - g_free (hex_str); + g_free(hex_str); } -static void mem_view_add_buffer ( - GtkListStore *store, - GtkTreeIter *iter, - guint32 address, - guchar *buffer, - gint len) { +static void mem_view_add_buffer(GtkListStore *store, + GtkTreeIter *iter, + guint32 address, + guchar *buffer, + gint len) { guint32 *word; - gint i, step; - gint column = 0; + gint i, step; + gint column = 0; - step = sizeof (*word); + step = sizeof(*word); for (i = 0; i < len; i += step) { - word = (guint *) &buffer[i]; + word = (guint *)&buffer[i]; if (column == 0) { - /* new row */ - gtk_list_store_append (store, iter); - - /* add address */ - mem_view_add_as_hex (store, iter, column, (address + i)); + gtk_list_store_append(store, iter); // new row + mem_view_add_as_hex(store, iter, column, (address + i)); // add address } - mem_view_add_as_hex (store, iter, (column + 1), *word); + + mem_view_add_as_hex(store, iter, (column + 1), *word); column = (column + 1) % step; } } -static guint32 hexstr_to_guint32 (const gchar *str, GError **err) { - guint32 val; - gchar *end_ptr; +static guint32 hexstr_to_guint32(const gchar *str, GError **err) { + guint32 val; + gchar *end_ptr; + + val = (guint32)strtoul(str, &end_ptr, 16); - val = (guint32) strtoul (str, &end_ptr, 16); if ((errno == ERANGE && val == UINT_MAX) || (errno != 0 && val == 0)) { - g_set_error (err, g_quark_from_string ("hextou32"), 1, "Invalid hexstring"); - return UINT32_MAX; + g_set_error(err, g_quark_from_string("hextou32"), 1, "Invalid hexstring"); + return(UINT32_MAX); } + if (end_ptr == str) { - g_set_error (err, g_quark_from_string ("hextou32"), 2, "Invalid hexstring"); - return UINT32_MAX; + g_set_error(err, g_quark_from_string("hextou32"), 2, "Invalid hexstring"); + return(UINT32_MAX); } - return val; + + return(val); } -static void stlink_gui_update_mem_view (STlinkGUI *gui, struct mem_t *mem, GtkTreeView *view) { +static void stlink_gui_update_mem_view(STlinkGUI *gui, struct mem_t *mem, GtkTreeView *view) { GtkListStore *store; - GtkTreeIter iter; + GtkTreeIter iter; - store = GTK_LIST_STORE (gtk_tree_view_get_model (view)); + store = GTK_LIST_STORE(gtk_tree_view_get_model(view)); - mem_view_add_buffer (store, &iter, mem->base, mem->memory, (gint) mem->size); + mem_view_add_buffer(store, &iter, mem->base, mem->memory, (gint)mem->size); - gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); - gtk_progress_bar_set_fraction (gui->progress.bar, 0); - stlink_gui_set_sensitivity (gui, TRUE); + gtk_widget_hide(GTK_WIDGET(gui->progress.bar)); + gtk_progress_bar_set_fraction(gui->progress.bar, 0); + stlink_gui_set_sensitivity(gui, TRUE); } -static gboolean stlink_gui_update_devmem_view (STlinkGUI *gui) { - stlink_gui_update_mem_view (gui, &gui->flash_mem, gui->devmem_treeview); - return FALSE; +static gboolean stlink_gui_update_devmem_view(STlinkGUI *gui) { + stlink_gui_update_mem_view(gui, &gui->flash_mem, gui->devmem_treeview); + return(FALSE); } -static gpointer stlink_gui_populate_devmem_view (gpointer data) { - guint off; - stm32_addr_t addr; +static gpointer stlink_gui_populate_devmem_view(gpointer data) { + guint off; + stm32_addr_t addr; - g_return_val_if_fail (STLINK_IS_GUI (data), NULL); + g_return_val_if_fail(STLINK_IS_GUI(data), NULL); STlinkGUI *gui = (STlinkGUI *)data; - g_return_val_if_fail ((gui != NULL), NULL); - g_return_val_if_fail ((gui->sl != NULL), NULL); + g_return_val_if_fail((gui != NULL), NULL); + g_return_val_if_fail((gui->sl != NULL), NULL); addr = gui->sl->flash_base; - if (gui->flash_mem.memory) - g_free (gui->flash_mem.memory); - gui->flash_mem.memory = g_malloc (gui->sl->flash_size); + if (gui->flash_mem.memory) { + g_free(gui->flash_mem.memory); + } + + gui->flash_mem.memory = g_malloc(gui->sl->flash_size); gui->flash_mem.size = gui->sl->flash_size; gui->flash_mem.base = gui->sl->flash_base; @@ -208,304 +205,319 @@ static gpointer stlink_gui_populate_devmem_view (gpointer data) { guint n_read = MEM_READ_SIZE; if (off + MEM_READ_SIZE > gui->sl->flash_size) { - n_read = (guint) gui->sl->flash_size - off; + n_read = (guint)gui->sl->flash_size - off; - /* align if needed */ - if (n_read & 3) - n_read = (n_read + 4) & ~(3); + if (n_read & 3) { n_read = (n_read + 4) & ~(3); } // align if needed } - /* reads to sl->q_buf */ - stlink_read_mem32(gui->sl, addr + off, n_read); + + stlink_read_mem32(gui->sl, addr + off, n_read); // reads to sl->q_buf + if (gui->sl->q_len < 0) { - stlink_gui_set_info_error_message (gui, "Failed to read memory"); - g_free (gui->flash_mem.memory); + stlink_gui_set_info_error_message(gui, "Failed to read memory"); + g_free(gui->flash_mem.memory); gui->flash_mem.memory = NULL; - return NULL; + return(NULL); } - memcpy (gui->flash_mem.memory + off, gui->sl->q_buf, n_read); - gui->progress.fraction = (gdouble) (off + n_read) / gui->sl->flash_size; + + memcpy(gui->flash_mem.memory + off, gui->sl->q_buf, n_read); + gui->progress.fraction = (gdouble)(off + n_read) / gui->sl->flash_size; } - g_idle_add ((GSourceFunc) stlink_gui_update_devmem_view, gui); - return NULL; + + g_idle_add((GSourceFunc)stlink_gui_update_devmem_view, gui); + return(NULL); } -static gboolean stlink_gui_update_filemem_view (STlinkGUI *gui) { +static gboolean stlink_gui_update_filemem_view(STlinkGUI *gui) { gchar *basename; - basename = g_path_get_basename (gui->filename); - gtk_notebook_set_tab_label_text (gui->notebook, - GTK_WIDGET (gtk_notebook_get_nth_page (gui->notebook, 1)), basename); - g_free (basename); + basename = g_path_get_basename(gui->filename); + gtk_notebook_set_tab_label_text( + gui->notebook, GTK_WIDGET(gtk_notebook_get_nth_page(gui->notebook, 1)), basename); + g_free(basename); - stlink_gui_update_mem_view (gui, &gui->file_mem, gui->filemem_treeview); - return FALSE; + stlink_gui_update_mem_view(gui, &gui->file_mem, gui->filemem_treeview); + return(FALSE); } -static gpointer stlink_gui_populate_filemem_view (gpointer data) { - guchar buffer[MEM_READ_SIZE]; - GFile *file; - GFileInfo *file_info; +static gpointer stlink_gui_populate_filemem_view(gpointer data) { + guchar buffer[MEM_READ_SIZE]; + GFile *file; + GFileInfo *file_info; GInputStream *input_stream; - gint off; - GError *err = NULL; + gint off; + GError *err = NULL; - g_return_val_if_fail (STLINK_IS_GUI (data), NULL); + g_return_val_if_fail(STLINK_IS_GUI(data), NULL); STlinkGUI *gui = (STlinkGUI *)data; - g_return_val_if_fail (gui != NULL, NULL); - g_return_val_if_fail (gui->filename != NULL, NULL); + g_return_val_if_fail(gui != NULL, NULL); + g_return_val_if_fail(gui->filename != NULL, NULL); - if (g_str_has_suffix (gui->filename, ".hex")) { - // If the file has prefix .hex - try to interpret it as Intel-HEX. - // It's difficult to merge the world of standard functions and GLib, - // so do it simple - load whole file into buffer and copy the data to the - // destination afterwards. - // We loose meanwhile the displaying of the progress and need double memory. + if (g_str_has_suffix(gui->filename, ".hex")) { + /* If the file has prefix .hex - try to interpret it as Intel-HEX. + * It's difficult to merge the world of standard functions and GLib, so do it simple: + * Load whole file into buffer and copy the data to the destination afterwards. + * In the meanwhile we loose the displaying of the progress and need double memory. + */ uint8_t* mem = NULL; - size_t size = 0; + size_t size = 0; uint32_t begin = 0; - int res = stlink_parse_ihex (gui->filename, 0, &mem, &size, &begin); + int res = stlink_parse_ihex(gui->filename, 0, &mem, &size, &begin); if (res == 0) { - if (gui->file_mem.memory) - g_free (gui->file_mem.memory); + if (gui->file_mem.memory) { + g_free(gui->file_mem.memory); + } + gui->file_mem.size = size; - gui->file_mem.memory = g_malloc (size); + gui->file_mem.memory = g_malloc(size); gui->file_mem.base = begin; - memcpy (gui->file_mem.memory, mem, size); + memcpy(gui->file_mem.memory, mem, size); } else { - stlink_gui_set_info_error_message (gui, "Cannot interpret the file as Intel-HEX"); + stlink_gui_set_info_error_message(gui, "Cannot interpret the file as Intel-HEX"); } free(mem); } else { - file = g_file_new_for_path (gui->filename); - input_stream = G_INPUT_STREAM (g_file_read (file, NULL, &err)); + file = g_file_new_for_path(gui->filename); + input_stream = G_INPUT_STREAM(g_file_read(file, NULL, &err)); + if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); + stlink_gui_set_info_error_message(gui, err->message); + g_error_free(err); goto out; } - file_info = g_file_input_stream_query_info (G_FILE_INPUT_STREAM (input_stream), - G_FILE_ATTRIBUTE_STANDARD_SIZE, NULL, &err); + file_info = g_file_input_stream_query_info( + G_FILE_INPUT_STREAM(input_stream), G_FILE_ATTRIBUTE_STANDARD_SIZE, NULL, &err); + if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); + stlink_gui_set_info_error_message(gui, err->message); + g_error_free(err); goto out_input; } - if (gui->file_mem.memory) - g_free (gui->file_mem.memory); - gui->file_mem.size = g_file_info_get_size (file_info); - gui->file_mem.memory = g_malloc (gui->file_mem.size); - for (off = 0; off < (gint) gui->file_mem.size; off += MEM_READ_SIZE) { + if (gui->file_mem.memory) { g_free(gui->file_mem.memory); } + + gui->file_mem.size = g_file_info_get_size(file_info); + gui->file_mem.memory = g_malloc(gui->file_mem.size); + + for (off = 0; off < (gint)gui->file_mem.size; off += MEM_READ_SIZE) { guint n_read = MEM_READ_SIZE; - if (off + MEM_READ_SIZE > (gint) gui->file_mem.size) - n_read = (guint) gui->file_mem.size - off; + if (off + MEM_READ_SIZE > (gint)gui->file_mem.size) { + n_read = (guint)gui->file_mem.size - off; + } - if (g_input_stream_read (G_INPUT_STREAM (input_stream), - &buffer, n_read, NULL, &err) == -1) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); + if (g_input_stream_read( + G_INPUT_STREAM(input_stream), &buffer, n_read, NULL, &err) == -1) { + stlink_gui_set_info_error_message(gui, err->message); + g_error_free(err); goto out_input; } - memcpy (gui->file_mem.memory + off, buffer, n_read); - gui->progress.fraction = (gdouble) (off + n_read) / gui->file_mem.size; + + memcpy(gui->file_mem.memory + off, buffer, n_read); + gui->progress.fraction = (gdouble)(off + n_read) / gui->file_mem.size; } - out_input: g_object_unref (input_stream); - out: g_object_unref (file); +out_input: g_object_unref(input_stream); +out: g_object_unref(file); } - g_idle_add ((GSourceFunc) stlink_gui_update_filemem_view, gui); - return NULL; + g_idle_add((GSourceFunc)stlink_gui_update_filemem_view, gui); + return(NULL); } -static void mem_jmp (GtkTreeView *view, - GtkEntry *entry, - guint32 base_addr, - gsize size, - GError **err) { +static void mem_jmp(GtkTreeView *view, + GtkEntry *entry, + guint32 base_addr, + gsize size, + GError **err) { GtkTreeModel *model; - guint32 jmp_addr; - GtkTreeIter iter; + guint32 jmp_addr; + GtkTreeIter iter; - jmp_addr = hexstr_to_guint32 (gtk_entry_get_text (entry), err); - if (err && *err) - return; + jmp_addr = hexstr_to_guint32(gtk_entry_get_text(entry), err); + + if (err && *err) { return; } if (jmp_addr < base_addr || jmp_addr > base_addr + size) { - g_set_error (err, g_quark_from_string ("mem_jmp"), 1, "Invalid address"); + g_set_error(err, g_quark_from_string("mem_jmp"), 1, "Invalid address"); return; } - model = gtk_tree_view_get_model (view); - if (!model) - return; + model = gtk_tree_view_get_model(view); + + if (!model) { return; } - if (gtk_tree_model_get_iter_first (model, &iter)) { + if (gtk_tree_model_get_iter_first(model, &iter)) { do { guint32 addr; - GValue value = G_VALUE_INIT; + GValue value = G_VALUE_INIT; + + gtk_tree_model_get_value(model, &iter, 0, &value); + + if (G_VALUE_HOLDS_STRING(&value)) { + addr = hexstr_to_guint32(g_value_get_string(&value), err); - gtk_tree_model_get_value (model, &iter, 0, &value); - if (G_VALUE_HOLDS_STRING (&value)) { - addr = hexstr_to_guint32 (g_value_get_string (&value), err); if (!*err) { if (addr == (jmp_addr & 0xFFFFFFF0)) { GtkTreeSelection *selection; - GtkTreePath *path; + GtkTreePath *path; - selection = gtk_tree_view_get_selection (view); - path = gtk_tree_model_get_path (model, &iter); + selection = gtk_tree_view_get_selection(view); + path = gtk_tree_model_get_path(model, &iter); - gtk_tree_selection_select_iter (selection, &iter); - gtk_tree_view_scroll_to_cell (view, path, NULL, TRUE, 0.0, 0.0); - gtk_tree_path_free (path); + gtk_tree_selection_select_iter(selection, &iter); + gtk_tree_view_scroll_to_cell(view, path, NULL, TRUE, 0.0, 0.0); + gtk_tree_path_free(path); } } } + g_value_unset(&value); - } while (gtk_tree_model_iter_next (model, &iter)); + } while (gtk_tree_model_iter_next(model, &iter)); } } -static void devmem_jmp_cb (GtkWidget *widget, gpointer data) { +static void devmem_jmp_cb(GtkWidget *widget, gpointer data) { STlinkGUI *gui; - GError *err = NULL; - (void) widget; + GError *err = NULL; + (void)widget; - gui = STLINK_GUI (data); + gui = STLINK_GUI(data); - mem_jmp (gui->devmem_treeview, + mem_jmp(gui->devmem_treeview, gui->devmem_jmp_entry, gui->sl->flash_base, gui->sl->flash_size, &err); if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); + stlink_gui_set_info_error_message(gui, err->message); + g_error_free(err); } } -static void filemem_jmp_cb (GtkWidget *widget, gpointer data) { +static void filemem_jmp_cb(GtkWidget *widget, gpointer data) { STlinkGUI *gui; - GError *err = NULL; - (void) widget; + GError *err = NULL; + (void)widget; - gui = STLINK_GUI (data); + gui = STLINK_GUI(data); - g_return_if_fail (gui->filename != NULL); + g_return_if_fail(gui->filename != NULL); - mem_jmp (gui->filemem_treeview, + mem_jmp(gui->filemem_treeview, gui->filemem_jmp_entry, 0, gui->file_mem.size, &err); if (err) { - stlink_gui_set_info_error_message (gui, err->message); - g_error_free (err); + stlink_gui_set_info_error_message(gui, err->message); + g_error_free(err); } } -static gchar *dev_format_chip_id (guint32 chip_id) { +static gchar *dev_format_chip_id(guint32 chip_id) { const struct stlink_chipid_params *params; params = stlink_chipid_get_params(chip_id); - if (!params) - return g_strdup_printf ("0x%x", chip_id); - return g_strdup (params->description); + if (!params) { return(g_strdup_printf("0x%x", chip_id)); } + + return(g_strdup(params->description)); } -static gchar *dev_format_mem_size (gsize flash_size) { - return g_strdup_printf ("%u kB", (unsigned int)(flash_size / 1024)); +static gchar *dev_format_mem_size(gsize flash_size) { + return(g_strdup_printf("%u kB", (unsigned int)(flash_size / 1024))); } -static void stlink_gui_set_connected (STlinkGUI *gui) { - gchar *tmp_str; +static void stlink_gui_set_connected(STlinkGUI *gui) { + gchar *tmp_str; GtkListStore *store; - GtkTreeIter iter; + GtkTreeIter iter; + + gtk_statusbar_push(gui->statusbar, gtk_statusbar_get_context_id(gui->statusbar, "conn"), "Connected"); - gtk_statusbar_push (gui->statusbar, - gtk_statusbar_get_context_id (gui->statusbar, "conn"), "Connected"); + gtk_widget_set_sensitive(GTK_WIDGET(gui->device_frame), TRUE); + gtk_widget_set_sensitive(GTK_WIDGET(gui->devmem_box), TRUE); + gtk_widget_set_sensitive(GTK_WIDGET(gui->connect_button), FALSE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->device_frame), TRUE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->devmem_box), TRUE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), FALSE); + if (gui->filename) { + gtk_widget_set_sensitive(GTK_WIDGET(gui->flash_button), TRUE); + } - if (gui->filename) - gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), TRUE); + tmp_str = dev_format_chip_id(gui->sl->chip_id); + gtk_label_set_text(gui->chip_id_label, tmp_str); + g_free(tmp_str); - tmp_str = dev_format_chip_id (gui->sl->chip_id); - gtk_label_set_text (gui->chip_id_label, tmp_str); - g_free (tmp_str); + tmp_str = g_strdup_printf("0x%x", gui->sl->core_id); + gtk_label_set_text(gui->core_id_label, tmp_str); + g_free(tmp_str); - tmp_str = g_strdup_printf ("0x%x", gui->sl->core_id); - gtk_label_set_text (gui->core_id_label, tmp_str); - g_free (tmp_str); + tmp_str = dev_format_mem_size(gui->sl->flash_size); + gtk_label_set_text(gui->flash_size_label, tmp_str); + g_free(tmp_str); - tmp_str = dev_format_mem_size (gui->sl->flash_size); - gtk_label_set_text (gui->flash_size_label, tmp_str); - g_free (tmp_str); + tmp_str = dev_format_mem_size(gui->sl->sram_size); + gtk_label_set_text(gui->ram_size_label, tmp_str); + g_free(tmp_str); - tmp_str = dev_format_mem_size (gui->sl->sram_size); - gtk_label_set_text (gui->ram_size_label, tmp_str); - g_free (tmp_str); + tmp_str = g_strdup_printf("0x%08X", gui->sl->flash_base); + gtk_entry_set_text(gui->devmem_jmp_entry, tmp_str); + gtk_editable_set_editable(GTK_EDITABLE(gui->devmem_jmp_entry), TRUE); + g_free(tmp_str); - tmp_str = g_strdup_printf ("0x%08X", gui->sl->flash_base); - gtk_entry_set_text (gui->devmem_jmp_entry, tmp_str); - gtk_editable_set_editable (GTK_EDITABLE (gui->devmem_jmp_entry), TRUE); - g_free (tmp_str); + store = GTK_LIST_STORE(gtk_tree_view_get_model(gui->devmem_treeview)); - store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->devmem_treeview)); - if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) - gtk_list_store_clear (store); + if (gtk_tree_model_get_iter_first(GTK_TREE_MODEL(store), &iter)) { + gtk_list_store_clear(store); + } - stlink_gui_set_sensitivity (gui, FALSE); - gtk_notebook_set_current_page (gui->notebook, PAGE_DEVMEM); - gtk_widget_show (GTK_WIDGET (gui->progress.bar)); - gtk_progress_bar_set_text (gui->progress.bar, "Reading memory"); + stlink_gui_set_sensitivity(gui, FALSE); + gtk_notebook_set_current_page(gui->notebook, PAGE_DEVMEM); + gtk_widget_show(GTK_WIDGET(gui->progress.bar)); + gtk_progress_bar_set_text(gui->progress.bar, "Reading memory"); - g_thread_new ("devmem", (GThreadFunc) stlink_gui_populate_devmem_view, gui); + g_thread_new("devmem", (GThreadFunc)stlink_gui_populate_devmem_view, gui); } -static void connect_button_cb (GtkWidget *widget, gpointer data) { +static void connect_button_cb(GtkWidget *widget, gpointer data) { STlinkGUI *gui; - gint i; - (void) widget; + gint i; + (void)widget; - gui = STLINK_GUI (data); + gui = STLINK_GUI(data); - if (gui->sl != NULL) - return; + if (gui->sl != NULL) { return; } + + gui->sl = stlink_v1_open(0, 1); // try version 1 then version 2 + + if (gui->sl == NULL) { gui->sl = stlink_open_usb(0, 1, NULL, 0); } - /* try version 1 then version 2 */ - gui->sl = stlink_v1_open(0, 1); - if (gui->sl == NULL) - gui->sl = stlink_open_usb(0, 1, NULL, 0); if (gui->sl == NULL) { - stlink_gui_set_info_error_message (gui, "Failed to connect to STLink."); + stlink_gui_set_info_error_message(gui, "Failed to connect to STLink."); return; } - /* code below taken from flash/main.c, refactoring might be in order */ - if (stlink_current_mode(gui->sl) == STLINK_DEV_DFU_MODE) + // code below taken from flash/main.c, refactoring might be in order + if (stlink_current_mode(gui->sl) == STLINK_DEV_DFU_MODE) { stlink_exit_dfu_mode(gui->sl); + } - if (stlink_current_mode(gui->sl) != STLINK_DEV_DEBUG_MODE) + if (stlink_current_mode(gui->sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(gui->sl); + } - /* Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 */ + // disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 if (gui->sl->chip_id == STLINK_CHIPID_STM32_F4) { memset(gui->sl->q_buf, 0, 4); + for (i = 0; i < 8; i++) { stlink_write_mem32(gui->sl, 0x40026000 + 0x10 + 0x18 * i, 4); stlink_write_mem32(gui->sl, 0x40026400 + 0x10 + 0x18 * i, 4); @@ -513,128 +525,133 @@ static void connect_button_cb (GtkWidget *widget, gpointer data) { stlink_write_mem32(gui->sl, 0x40026400 + 0x24 + 0x18 * i, 4); } } - stlink_gui_set_connected (gui); + + stlink_gui_set_connected(gui); } -static void stlink_gui_set_disconnected (STlinkGUI *gui) { - gtk_statusbar_push (gui->statusbar, - gtk_statusbar_get_context_id (gui->statusbar, "conn"), - "Disconnected"); +static void stlink_gui_set_disconnected(STlinkGUI *gui) { + gtk_statusbar_push(gui->statusbar, gtk_statusbar_get_context_id(gui->statusbar, "conn"), "Disconnected"); - gtk_widget_set_sensitive (GTK_WIDGET (gui->device_frame), FALSE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->flash_button), FALSE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->export_button), FALSE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->disconnect_button), FALSE); - gtk_widget_set_sensitive (GTK_WIDGET (gui->connect_button), TRUE); + gtk_widget_set_sensitive(GTK_WIDGET(gui->device_frame), FALSE); + gtk_widget_set_sensitive(GTK_WIDGET(gui->flash_button), FALSE); + gtk_widget_set_sensitive(GTK_WIDGET(gui->export_button), FALSE); + gtk_widget_set_sensitive(GTK_WIDGET(gui->disconnect_button), FALSE); + gtk_widget_set_sensitive(GTK_WIDGET(gui->connect_button), TRUE); } -static void disconnect_button_cb (GtkWidget *widget, gpointer data) { +static void disconnect_button_cb(GtkWidget *widget, gpointer data) { STlinkGUI *gui; - (void) widget; + (void)widget; - gui = STLINK_GUI (data); + gui = STLINK_GUI(data); if (gui->sl != NULL) { stlink_exit_debug_mode(gui->sl); stlink_close(gui->sl); gui->sl = NULL; } - stlink_gui_set_disconnected (gui); + + stlink_gui_set_disconnected(gui); } -static void stlink_gui_open_file (STlinkGUI *gui) { - GtkWidget *dialog; +static void stlink_gui_open_file(STlinkGUI *gui) { + GtkWidget *dialog; GtkListStore *store; - GtkTreeIter iter; + GtkTreeIter iter; - dialog = gtk_file_chooser_dialog_new ("Open file", - gui->window, - GTK_FILE_CHOOSER_ACTION_OPEN, - "_Cancel", GTK_RESPONSE_CANCEL, - "_Open", GTK_RESPONSE_ACCEPT, - NULL); + dialog = gtk_file_chooser_dialog_new("Open file", + gui->window, + GTK_FILE_CHOOSER_ACTION_OPEN, + "_Cancel", GTK_RESPONSE_CANCEL, + "_Open", GTK_RESPONSE_ACCEPT, + NULL); - if (gtk_dialog_run (GTK_DIALOG (dialog)) == GTK_RESPONSE_ACCEPT) { - gui->filename = gtk_file_chooser_get_filename (GTK_FILE_CHOOSER (dialog)); + if (gtk_dialog_run(GTK_DIALOG(dialog)) == GTK_RESPONSE_ACCEPT) { + gui->filename = gtk_file_chooser_get_filename(GTK_FILE_CHOOSER(dialog)); - store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->filemem_treeview)); - if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) - gtk_list_store_clear (store); + store = GTK_LIST_STORE(gtk_tree_view_get_model(gui->filemem_treeview)); - stlink_gui_set_sensitivity (gui, FALSE); - gtk_notebook_set_current_page (gui->notebook, PAGE_FILEMEM); - gtk_widget_show (GTK_WIDGET (gui->progress.bar)); - gtk_progress_bar_set_text (gui->progress.bar, "Reading file"); - g_thread_new ("file", (GThreadFunc) stlink_gui_populate_filemem_view, gui); + if (gtk_tree_model_get_iter_first(GTK_TREE_MODEL(store), &iter)) { + gtk_list_store_clear(store); + } + + stlink_gui_set_sensitivity(gui, FALSE); + gtk_notebook_set_current_page(gui->notebook, PAGE_FILEMEM); + gtk_widget_show(GTK_WIDGET(gui->progress.bar)); + gtk_progress_bar_set_text(gui->progress.bar, "Reading file"); + g_thread_new("file", (GThreadFunc)stlink_gui_populate_filemem_view, gui); } - gtk_widget_destroy (dialog); + + gtk_widget_destroy(dialog); } -static void open_button_cb (GtkWidget *widget, gpointer data) { - STlinkGUI *gui; - (void) widget; +static void open_button_cb(GtkWidget *widget, gpointer data) { + STlinkGUI *gui; + (void)widget; - gui = STLINK_GUI (data); - stlink_gui_open_file (gui); + gui = STLINK_GUI(data); + stlink_gui_open_file(gui); } -static gboolean stlink_gui_write_flash_update (STlinkGUI *gui) { - stlink_gui_set_sensitivity (gui, TRUE); +static gboolean stlink_gui_write_flash_update(STlinkGUI *gui) { + stlink_gui_set_sensitivity(gui, TRUE); gui->progress.activity_mode = FALSE; - gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); - return FALSE; + gtk_widget_hide(GTK_WIDGET(gui->progress.bar)); + return(FALSE); } -static gpointer stlink_gui_write_flash (gpointer data) { - g_return_val_if_fail (STLINK_IS_GUI (data), NULL); +static gpointer stlink_gui_write_flash(gpointer data) { + g_return_val_if_fail(STLINK_IS_GUI(data), NULL); STlinkGUI *gui = (STlinkGUI *)data; - g_return_val_if_fail ((gui->sl != NULL), NULL); - g_return_val_if_fail ((gui->filename != NULL), NULL); + g_return_val_if_fail((gui->sl != NULL), NULL); + g_return_val_if_fail((gui->filename != NULL), NULL); - if (stlink_mwrite_flash(gui->sl, gui->file_mem.memory, - (uint32_t)gui->file_mem.size, gui->sl->flash_base) < 0) { - stlink_gui_set_info_error_message (gui, "Failed to write to flash"); + if (stlink_mwrite_flash( + gui->sl, gui->file_mem.memory, (uint32_t)gui->file_mem.size, gui->sl->flash_base) < 0) { + stlink_gui_set_info_error_message(gui, "Failed to write to flash"); } - g_idle_add ((GSourceFunc) stlink_gui_write_flash_update, gui); - return NULL; + g_idle_add((GSourceFunc)stlink_gui_write_flash_update, gui); + return(NULL); } -static void flash_button_cb (GtkWidget *widget, gpointer data) { +static void flash_button_cb(GtkWidget *widget, gpointer data) { STlinkGUI *gui; - gchar *tmp_str; - guint32 address; - gint result; - GError *err = NULL; - (void) widget; + gchar *tmp_str; + guint32 address; + gint result; + GError *err = NULL; + (void)widget; - gui = STLINK_GUI (data); - g_return_if_fail (gui->sl != NULL); + gui = STLINK_GUI(data); + g_return_if_fail(gui->sl != NULL); - if (!g_strcmp0 (gtk_entry_get_text (gui->flash_dialog_entry), "")) { - tmp_str = g_strdup_printf ("0x%08X", gui->sl->flash_base); - gtk_entry_set_text (gui->flash_dialog_entry, tmp_str); - g_free (tmp_str); + if (!g_strcmp0(gtk_entry_get_text(gui->flash_dialog_entry), "")) { + tmp_str = g_strdup_printf("0x%08X", gui->sl->flash_base); + gtk_entry_set_text(gui->flash_dialog_entry, tmp_str); + g_free(tmp_str); } - result = gtk_dialog_run (gui->flash_dialog); + result = gtk_dialog_run(gui->flash_dialog); + if (result == GTK_RESPONSE_OK) { - address = hexstr_to_guint32 (gtk_entry_get_text (gui->flash_dialog_entry), &err); + address = hexstr_to_guint32(gtk_entry_get_text(gui->flash_dialog_entry), &err); + if (err) { - stlink_gui_set_info_error_message (gui, err->message); + stlink_gui_set_info_error_message(gui, err->message); } else { if (address > gui->sl->flash_base + gui->sl->flash_size || address < gui->sl->flash_base) { - stlink_gui_set_info_error_message (gui, "Invalid address"); + stlink_gui_set_info_error_message(gui, "Invalid address"); } else if (address + gui->file_mem.size > gui->sl->flash_base + gui->sl->flash_size) { - stlink_gui_set_info_error_message (gui, "Binary overwrites flash"); + stlink_gui_set_info_error_message(gui, "Binary overwrites flash"); } else { - stlink_gui_set_sensitivity (gui, FALSE); - gtk_progress_bar_set_text (gui->progress.bar, "Writing to flash"); + stlink_gui_set_sensitivity(gui, FALSE); + gtk_progress_bar_set_text(gui->progress.bar, "Writing to flash"); gui->progress.activity_mode = TRUE; - gtk_widget_show (GTK_WIDGET (gui->progress.bar)); - g_thread_new ("flash", (GThreadFunc) stlink_gui_write_flash, gui); + gtk_widget_show(GTK_WIDGET(gui->progress.bar)); + g_thread_new("flash", (GThreadFunc)stlink_gui_write_flash, gui); } } } @@ -642,248 +659,258 @@ static void flash_button_cb (GtkWidget *widget, gpointer data) { int export_to_file(const char*filename, const struct mem_t flash_mem) { printf("%s\n", filename); - FILE * f=fopen(filename, "w"); - if (f == NULL) - return -1; - for (gsize i=0;iwindow, - GTK_FILE_CHOOSER_ACTION_SAVE, - "_Cancel", - GTK_RESPONSE_CANCEL, - "_Open", - GTK_RESPONSE_ACCEPT, - NULL); - GtkFileChooser *chooser = GTK_FILE_CHOOSER (dialog); - gtk_file_chooser_set_do_overwrite_confirmation (chooser, TRUE); - gint res = gtk_dialog_run (GTK_DIALOG (dialog)); + dialog = gtk_file_chooser_dialog_new("Save as", + gui->window, + GTK_FILE_CHOOSER_ACTION_SAVE, + "_Cancel", + GTK_RESPONSE_CANCEL, + "_Open", + GTK_RESPONSE_ACCEPT, + NULL); + GtkFileChooser *chooser = GTK_FILE_CHOOSER(dialog); + gtk_file_chooser_set_do_overwrite_confirmation(chooser, TRUE); + gint res = gtk_dialog_run(GTK_DIALOG(dialog)); + if (res == GTK_RESPONSE_ACCEPT) { char *filename; - filename = gtk_file_chooser_get_filename (chooser); - if (export_to_file (filename, gui->flash_mem) != 0) { + filename = gtk_file_chooser_get_filename(chooser); + + if (export_to_file(filename, gui->flash_mem) != 0) { stlink_gui_set_info_error_message(gui, "Failed to export flash"); } else { stlink_gui_set_info_error_message(gui, "Export successful"); } - g_free (filename); + + g_free(filename); } - gtk_widget_destroy (dialog); + gtk_widget_destroy(dialog); } -static gboolean progress_pulse_timeout (STlinkGUI *gui) { +static gboolean progress_pulse_timeout(STlinkGUI *gui) { if (gui->progress.activity_mode) { - gtk_progress_bar_pulse (gui->progress.bar); + gtk_progress_bar_pulse(gui->progress.bar); } else { - gtk_progress_bar_set_fraction (gui->progress.bar, gui->progress.fraction); + gtk_progress_bar_set_fraction(gui->progress.bar, gui->progress.fraction); } - return TRUE; + + return(TRUE); } -static void notebook_switch_page_cb ( - GtkNotebook *notebook, - GtkWidget *widget, - guint page_num, - gpointer data) { +static void notebook_switch_page_cb(GtkNotebook *notebook, + GtkWidget *widget, + guint page_num, + gpointer data) { STlinkGUI *gui; - (void) notebook; - (void) widget; + (void)notebook; + (void)widget; - gui = STLINK_GUI (data); + gui = STLINK_GUI(data); if (page_num == 1) { - if (gui->filename == NULL) - stlink_gui_open_file (gui); - } -} - -static void dnd_received_cb ( - GtkWidget *widget, - GdkDragContext *context, - gint x, - gint y, - GtkSelectionData *selection_data, - guint target_type, - guint timestamp, - gpointer data) { - GFile *file_uri; - gchar **file_list; + if (gui->filename == NULL) { stlink_gui_open_file(gui); } + } +} + +static void dnd_received_cb(GtkWidget *widget, + GdkDragContext *context, + gint x, + gint y, + GtkSelectionData *selection_data, + guint target_type, + guint timestamp, + gpointer data) { + GFile *file_uri; + gchar **file_list; const guchar *file_data; - STlinkGUI *gui = STLINK_GUI (data); + STlinkGUI *gui = STLINK_GUI(data); GtkListStore *store; - GtkTreeIter iter; - (void) widget; - (void) x; - (void) y; + GtkTreeIter iter; + (void)widget; + (void)x; + (void)y; - if (selection_data != NULL && gtk_selection_data_get_length (selection_data) > 0) { + if (selection_data != NULL && gtk_selection_data_get_length(selection_data) > 0) { switch (target_type) { case TARGET_FILENAME: - if (gui->filename) - g_free (gui->filename); + if (gui->filename) { + g_free(gui->filename); + } - file_data = gtk_selection_data_get_data (selection_data); - file_list = g_strsplit ((gchar *)file_data, "\r\n", 0); + file_data = gtk_selection_data_get_data(selection_data); + file_list = g_strsplit((gchar *)file_data, "\r\n", 0); - file_uri = g_file_new_for_uri (file_list[0]); - gui->filename = g_file_get_path (file_uri); + file_uri = g_file_new_for_uri(file_list[0]); + gui->filename = g_file_get_path(file_uri); - g_strfreev (file_list); - g_object_unref (file_uri); + g_strfreev(file_list); + g_object_unref(file_uri); - store = GTK_LIST_STORE (gtk_tree_view_get_model (gui->devmem_treeview)); - if (gtk_tree_model_get_iter_first (GTK_TREE_MODEL (store), &iter)) - gtk_list_store_clear (store); + store = GTK_LIST_STORE(gtk_tree_view_get_model(gui->devmem_treeview)); + + if (gtk_tree_model_get_iter_first(GTK_TREE_MODEL(store), &iter)) { + gtk_list_store_clear(store); + } - stlink_gui_set_sensitivity (gui, FALSE); - gtk_notebook_set_current_page (gui->notebook, PAGE_FILEMEM); - gtk_widget_show (GTK_WIDGET (gui->progress.bar)); - gtk_progress_bar_set_text (gui->progress.bar, "Reading file"); - g_thread_new ("file", (GThreadFunc) stlink_gui_populate_filemem_view, gui); + stlink_gui_set_sensitivity(gui, FALSE); + gtk_notebook_set_current_page(gui->notebook, PAGE_FILEMEM); + gtk_widget_show(GTK_WIDGET(gui->progress.bar)); + gtk_progress_bar_set_text(gui->progress.bar, "Reading file"); + g_thread_new("file", (GThreadFunc)stlink_gui_populate_filemem_view, gui); break; } } - gtk_drag_finish ( - context, - TRUE, - gdk_drag_context_get_suggested_action (context) == GDK_ACTION_MOVE, - timestamp); + + gtk_drag_finish( + context, + TRUE, + gdk_drag_context_get_suggested_action(context) == GDK_ACTION_MOVE, + timestamp); } -void stlink_gui_init_dnd (STlinkGUI *gui) { - GtkTargetEntry target_list[] = { { "text/uri-list", 0, TARGET_FILENAME }, }; +void stlink_gui_init_dnd(STlinkGUI *gui) { + GtkTargetEntry target_list[] = { + { "text/uri-list", 0, TARGET_FILENAME }, + }; gtk_drag_dest_set( - GTK_WIDGET (gui->window), - GTK_DEST_DEFAULT_ALL, - target_list, - G_N_ELEMENTS (target_list), - GDK_ACTION_COPY); + GTK_WIDGET(gui->window), + GTK_DEST_DEFAULT_ALL, + target_list, + G_N_ELEMENTS(target_list), + GDK_ACTION_COPY); - g_signal_connect (gui->window, "drag-data-received", G_CALLBACK (dnd_received_cb), gui); + g_signal_connect(gui->window, "drag-data-received", G_CALLBACK(dnd_received_cb), gui); } -static void stlink_gui_build_ui (STlinkGUI *gui) { - GtkBuilder *builder; +static void stlink_gui_build_ui(STlinkGUI *gui) { + GtkBuilder *builder; GtkListStore *devmem_store; GtkListStore *filemem_store; gchar *ui_file = STLINK_UI_DIR "/stlink-gui.ui"; - if (!g_file_test (ui_file, G_FILE_TEST_EXISTS)) ui_file = "stlink-gui.ui"; - builder = gtk_builder_new (); - if (!gtk_builder_add_from_file (builder, ui_file, NULL)) { - g_printerr ("Failed to load UI file: %s\n", ui_file); - exit (1); - } - - gui->window = GTK_WINDOW (gtk_builder_get_object (builder, "window")); - g_signal_connect (G_OBJECT (gui->window), "destroy", G_CALLBACK (gtk_main_quit), NULL); - - /* set up toolutton clicked callbacks */ - gui->open_button = GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "open_button")); - g_signal_connect (G_OBJECT (gui->open_button), "clicked", G_CALLBACK (open_button_cb), gui); - - gui->connect_button = GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "connect_button")); - g_signal_connect (G_OBJECT (gui->connect_button), "clicked", G_CALLBACK (connect_button_cb), gui); - - gui->disconnect_button = GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "disconnect_button")); - g_signal_connect (G_OBJECT (gui->disconnect_button), "clicked", G_CALLBACK (disconnect_button_cb), gui); - - gui->flash_button = GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "flash_button")); - g_signal_connect (G_OBJECT (gui->flash_button), "clicked", G_CALLBACK (flash_button_cb), gui); - - gui->export_button = GTK_TOOL_BUTTON (gtk_builder_get_object (builder, "export_button")); - g_signal_connect (G_OBJECT (gui->export_button), "clicked", G_CALLBACK (export_button_cb), gui); - - gui->devmem_treeview = GTK_TREE_VIEW (gtk_builder_get_object (builder, "devmem_treeview")); - mem_view_init_headers (gui->devmem_treeview); - devmem_store = gtk_list_store_new (5, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING); - gtk_tree_view_set_model (gui->devmem_treeview, GTK_TREE_MODEL (devmem_store)); - g_object_unref (devmem_store); - - gui->filemem_treeview = GTK_TREE_VIEW (gtk_builder_get_object (builder, "filemem_treeview")); - mem_view_init_headers (gui->filemem_treeview); - filemem_store = gtk_list_store_new (5, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING, - G_TYPE_STRING); - gtk_tree_view_set_model (gui->filemem_treeview, GTK_TREE_MODEL (filemem_store)); - g_object_unref (filemem_store); - - gui->core_id_label = GTK_LABEL (gtk_builder_get_object (builder, "core_id_value")); - gui->chip_id_label = GTK_LABEL (gtk_builder_get_object (builder, "chip_id_value")); - gui->flash_size_label = GTK_LABEL (gtk_builder_get_object (builder, "flash_size_value")); - gui->ram_size_label = GTK_LABEL (gtk_builder_get_object (builder, "ram_size_value")); - gui->device_frame = GTK_FRAME (gtk_builder_get_object (builder, "device_frame")); - - gui->notebook = GTK_NOTEBOOK (gtk_builder_get_object (builder, "mem_notebook")); - g_signal_connect (gui->notebook, "switch-page", G_CALLBACK (notebook_switch_page_cb), gui); - - gui->devmem_box = GTK_BOX (gtk_builder_get_object (builder, "devmem_box")); - gui->filemem_box = GTK_BOX (gtk_builder_get_object (builder, "filemem_box")); - - gui->devmem_jmp_entry = GTK_ENTRY (gtk_builder_get_object (builder, "devmem_jmp_entry")); - g_signal_connect (gui->devmem_jmp_entry, "activate", G_CALLBACK (devmem_jmp_cb), gui); - - gui->filemem_jmp_entry = GTK_ENTRY (gtk_builder_get_object (builder, "filemem_jmp_entry")); - g_signal_connect (gui->filemem_jmp_entry, "activate", G_CALLBACK (filemem_jmp_cb), gui); - gtk_editable_set_editable (GTK_EDITABLE (gui->filemem_jmp_entry), TRUE); - - gui->progress.bar = GTK_PROGRESS_BAR (gtk_builder_get_object (builder, "progressbar")); - gtk_progress_bar_set_show_text (gui->progress.bar, TRUE); - gui->progress.timer = g_timeout_add (100, (GSourceFunc) progress_pulse_timeout, gui); - - gui->statusbar = GTK_STATUSBAR (gtk_builder_get_object (builder, "statusbar")); - - gui->infobar = GTK_INFO_BAR (gtk_builder_get_object (builder, "infobar")); - gtk_info_bar_add_button (gui->infobar, "_OK", GTK_RESPONSE_OK); - gui->infolabel = GTK_LABEL (gtk_label_new ("")); - gtk_container_add (GTK_CONTAINER (gtk_info_bar_get_content_area (gui->infobar)), GTK_WIDGET (gui->infolabel)); - g_signal_connect (gui->infobar, "response", G_CALLBACK (gtk_widget_hide), NULL); - - /* flash dialog */ - gui->flash_dialog = GTK_DIALOG (gtk_builder_get_object (builder, "flash_dialog")); - g_signal_connect_swapped (gui->flash_dialog, "response", G_CALLBACK (gtk_widget_hide), gui->flash_dialog); - gui->flash_dialog_ok = GTK_BUTTON (gtk_builder_get_object (builder, "flash_dialog_ok_button")); - gui->flash_dialog_cancel = GTK_BUTTON (gtk_builder_get_object (builder, "flash_dialog_cancel_button")); - gui->flash_dialog_entry = GTK_ENTRY (gtk_builder_get_object (builder, "flash_dialog_entry")); - - /* make it so */ - gtk_widget_show_all (GTK_WIDGET (gui->window)); - gtk_widget_hide (GTK_WIDGET (gui->infobar)); - gtk_widget_hide (GTK_WIDGET (gui->progress.bar)); - - stlink_gui_set_disconnected (gui); -} - -int main (int argc, char **argv) { + if (!g_file_test(ui_file, G_FILE_TEST_EXISTS)) { ui_file = "stlink-gui.ui"; } + + builder = gtk_builder_new(); + + if (!gtk_builder_add_from_file(builder, ui_file, NULL)) { + g_printerr("Failed to load UI file: %s\n", ui_file); + exit(1); + } + + gui->window = GTK_WINDOW(gtk_builder_get_object(builder, "window")); + g_signal_connect(G_OBJECT(gui->window), "destroy", G_CALLBACK(gtk_main_quit), NULL); + + /* Setup for toolbutton clicked callbacks */ + gui->open_button = GTK_TOOL_BUTTON(gtk_builder_get_object(builder, "open_button")); + g_signal_connect(G_OBJECT(gui->open_button), "clicked", G_CALLBACK(open_button_cb), gui); + + gui->connect_button = GTK_TOOL_BUTTON(gtk_builder_get_object(builder, "connect_button")); + g_signal_connect(G_OBJECT(gui->connect_button), "clicked", G_CALLBACK(connect_button_cb), gui); + + gui->disconnect_button = GTK_TOOL_BUTTON(gtk_builder_get_object(builder, "disconnect_button")); + g_signal_connect(G_OBJECT(gui->disconnect_button), "clicked", G_CALLBACK(disconnect_button_cb), gui); + + gui->flash_button = GTK_TOOL_BUTTON(gtk_builder_get_object(builder, "flash_button")); + g_signal_connect(G_OBJECT(gui->flash_button), "clicked", G_CALLBACK(flash_button_cb), gui); + + gui->export_button = GTK_TOOL_BUTTON(gtk_builder_get_object(builder, "export_button")); + g_signal_connect(G_OBJECT(gui->export_button), "clicked", G_CALLBACK(export_button_cb), gui); + + gui->devmem_treeview = GTK_TREE_VIEW(gtk_builder_get_object(builder, "devmem_treeview")); + mem_view_init_headers(gui->devmem_treeview); + devmem_store = gtk_list_store_new(5, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING); + gtk_tree_view_set_model(gui->devmem_treeview, GTK_TREE_MODEL(devmem_store)); + g_object_unref(devmem_store); + + gui->filemem_treeview = GTK_TREE_VIEW(gtk_builder_get_object(builder, "filemem_treeview")); + mem_view_init_headers(gui->filemem_treeview); + filemem_store = gtk_list_store_new(5, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING, + G_TYPE_STRING); + gtk_tree_view_set_model(gui->filemem_treeview, GTK_TREE_MODEL(filemem_store)); + g_object_unref(filemem_store); + + gui->core_id_label = GTK_LABEL(gtk_builder_get_object(builder, "core_id_value")); + gui->chip_id_label = GTK_LABEL(gtk_builder_get_object(builder, "chip_id_value")); + gui->flash_size_label = GTK_LABEL(gtk_builder_get_object(builder, "flash_size_value")); + gui->ram_size_label = GTK_LABEL(gtk_builder_get_object(builder, "ram_size_value")); + gui->device_frame = GTK_FRAME(gtk_builder_get_object(builder, "device_frame")); + + gui->notebook = GTK_NOTEBOOK(gtk_builder_get_object(builder, "mem_notebook")); + g_signal_connect(gui->notebook, "switch-page", G_CALLBACK(notebook_switch_page_cb), gui); + + gui->devmem_box = GTK_BOX(gtk_builder_get_object(builder, "devmem_box")); + gui->filemem_box = GTK_BOX(gtk_builder_get_object(builder, "filemem_box")); + + gui->devmem_jmp_entry = GTK_ENTRY(gtk_builder_get_object(builder, "devmem_jmp_entry")); + g_signal_connect(gui->devmem_jmp_entry, "activate", G_CALLBACK(devmem_jmp_cb), gui); + + gui->filemem_jmp_entry = GTK_ENTRY(gtk_builder_get_object(builder, "filemem_jmp_entry")); + g_signal_connect(gui->filemem_jmp_entry, "activate", G_CALLBACK(filemem_jmp_cb), gui); + gtk_editable_set_editable(GTK_EDITABLE(gui->filemem_jmp_entry), TRUE); + + gui->progress.bar = GTK_PROGRESS_BAR(gtk_builder_get_object(builder, "progressbar")); + gtk_progress_bar_set_show_text(gui->progress.bar, TRUE); + gui->progress.timer = g_timeout_add(100, (GSourceFunc)progress_pulse_timeout, gui); + + gui->statusbar = GTK_STATUSBAR(gtk_builder_get_object(builder, "statusbar")); + + gui->infobar = GTK_INFO_BAR(gtk_builder_get_object(builder, "infobar")); + gtk_info_bar_add_button(gui->infobar, "_OK", GTK_RESPONSE_OK); + gui->infolabel = GTK_LABEL(gtk_label_new("")); + gtk_container_add(GTK_CONTAINER(gtk_info_bar_get_content_area(gui->infobar)), GTK_WIDGET(gui->infolabel)); + g_signal_connect(gui->infobar, "response", G_CALLBACK(gtk_widget_hide), NULL); + + /* Flash dialog */ + gui->flash_dialog = GTK_DIALOG(gtk_builder_get_object(builder, "flash_dialog")); + g_signal_connect_swapped(gui->flash_dialog, "response", G_CALLBACK(gtk_widget_hide), gui->flash_dialog); + gui->flash_dialog_ok = GTK_BUTTON(gtk_builder_get_object(builder, "flash_dialog_ok_button")); + gui->flash_dialog_cancel = GTK_BUTTON(gtk_builder_get_object(builder, "flash_dialog_cancel_button")); + gui->flash_dialog_entry = GTK_ENTRY(gtk_builder_get_object(builder, "flash_dialog_entry")); + + // make it so + gtk_widget_show_all(GTK_WIDGET(gui->window)); + gtk_widget_hide(GTK_WIDGET(gui->infobar)); + gtk_widget_hide(GTK_WIDGET(gui->progress.bar)); + + stlink_gui_set_disconnected(gui); +} + +int main(int argc, char **argv) { STlinkGUI *gui; - gtk_init (&argc, &argv); + gtk_init(&argc, &argv); - gui = g_object_new (STLINK_TYPE_GUI, NULL); - stlink_gui_build_ui (gui); - stlink_gui_init_dnd (gui); + gui = g_object_new(STLINK_TYPE_GUI, NULL); + stlink_gui_build_ui(gui); + stlink_gui_init_dnd(gui); - gtk_main (); - return 0; + gtk_main(); + return(0); } diff --git a/src/stlink-gui/gui.h b/src/stlink-gui/gui.h index c83e638f6..b3d5dfff8 100644 --- a/src/stlink-gui/gui.h +++ b/src/stlink-gui/gui.h @@ -1,19 +1,18 @@ - #ifndef __STLINK_GUI_H__ #define __STLINK_GUI_H__ #include -#define STLINK_TYPE_GUI (stlink_gui_get_type ()) -#define STLINK_GUI(obj) (G_TYPE_CHECK_INSTANCE_CAST ((obj), STLINK_TYPE_GUI, STlinkGUI)) -#define STLINK_IS_GUI(obj) (G_TYPE_CHECK_INSTANCE_TYPE ((obj), STLINK_TYPE_GUI)) -#define STLINK_GUI_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST ((klass), STLINK_TYPE_GUI, STlinkGUIClass)) -#define STLINK_IS_GUI_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE ((klass), STLINK_TYPE_GUI)) -#define STLINK_GUI_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS ((obj), STLINK_TYPE_GUI, STlinkGUIlass)) -#define STLINK_GUI_GET_PRIVATE(obj) (G_TYPE_INSTANCE_GET_PRIVATE ((obj), STLINK_TYPE_GUI, STlinkGUIPrivate)) +#define STLINK_TYPE_GUI (stlink_gui_get_type()) +#define STLINK_GUI(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), STLINK_TYPE_GUI, STlinkGUI)) +#define STLINK_IS_GUI(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), STLINK_TYPE_GUI)) +#define STLINK_GUI_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), STLINK_TYPE_GUI, STlinkGUIClass)) +#define STLINK_IS_GUI_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), STLINK_TYPE_GUI)) +#define STLINK_GUI_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), STLINK_TYPE_GUI, STlinkGUIlass)) +#define STLINK_GUI_GET_PRIVATE(obj) (G_TYPE_INSTANCE_GET_PRIVATE((obj), STLINK_TYPE_GUI, STlinkGUIPrivate)) -typedef struct _STlinkGUI STlinkGUI; -typedef struct _STlinkGUIClass STlinkGUIClass; +typedef struct _STlinkGUI STlinkGUI; +typedef struct _STlinkGUIClass STlinkGUIClass; typedef struct _STlinkGUIPrivate STlinkGUIPrivate; enum stlink_gui_pages_t { @@ -28,21 +27,21 @@ enum stlink_gui_dnd_targets_t { struct progress_t { GtkProgressBar *bar; - guint timer; - gboolean activity_mode; - gdouble fraction; + guint timer; + gboolean activity_mode; + gdouble fraction; }; struct mem_t { guchar *memory; - gsize size; + gsize size; guint32 base; }; struct _STlinkGUI { GObject parent_instance; - /*< private >*/ + /* < private > */ GtkWindow *window; GtkTreeView *devmem_treeview; GtkTreeView *filemem_treeview; @@ -72,9 +71,9 @@ struct _STlinkGUI { GtkButton *flash_dialog_cancel; GtkEntry *flash_dialog_entry; - struct progress_t progress; - struct mem_t flash_mem; - struct mem_t file_mem; + struct progress_t progress; + struct mem_t flash_mem; + struct mem_t file_mem; gchar *error_message; gchar *filename; @@ -87,7 +86,7 @@ struct _STlinkGUIClass { /* class members */ }; -GType stlink_gui_get_type (void); +GType stlink_gui_get_type(void); int export_to_file(const char*filename, const struct mem_t flash_mem); -#endif +#endif // __STLINK_GUI_H__ diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index e6a82a2a9..bf0a56c96 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -2,636 +2,637 @@ #include "chipid.h" static const struct stlink_chipid_params devices[] = { - { - //RM0410 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F7XXXX, - .description = "F76xxx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 45.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, //! "System memory" starting address from - .bootrom_size = 0xEDC0 //! @todo "System memory" byte size in hex from - }, - { - //RM0385 and DS10916 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F7, - .description = "F7xx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 41.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18 - }, - { - //RM0431 and DS document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F72XXX, - .description = "F72x/F73x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff07a22, // section 35.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 24 - }, - { // table 2, PM0063 - .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, - .description = "F1xx Medium-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x5000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { // table 1, PM0059 - .chip_id = STLINK_CHIPID_STM32_F2, - .description = "F2xx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/ - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - }, - { // PM0063 - .chip_id = STLINK_CHIPID_STM32_F1_LOW, - .description = "F1 Low-density device", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2800, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F4, - .description = "F4xx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ - .flash_pagesize = 0x4000, - .sram_size = 0x30000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_DSI, - .description = "F46x/F47x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_HD, - .description = "F42x/F43x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/ - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_LP, - .description = "F4xx (low power)", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F411RE, - .description = "stm32f411re", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_DE, - .description = "F4xx (Dynamic Efficency)", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F1_HIGH, - .description = "F1xx High-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - // This ignores the EEPROM! (and uses the page erase size, - // not the sector write protection...) - .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM, - .description = "L1xx Medium-density", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x4000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 - }, - { - .chip_id = STLINK_CHIPID_STM32_L1_CAT2, - .description = "L1xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x8000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 - }, - { - .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, - .description = "L1xx Medium-Plus-density", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/ - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 - }, - { - .chip_id = STLINK_CHIPID_STM32_L1_HIGH, - .description = "L1xx High-density", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/ - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .option_base = STM32_L1_OPTION_BYTES_BASE, - .option_size = 8, - }, - { - .chip_id = STLINK_CHIPID_STM32_L152_RE, - .description = "L152RE", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x14000, /*Not completely clear if there are some with 32K*/ - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 - }, - { - .chip_id = STLINK_CHIPID_STM32_F1_CONN, - .description = "F1 Connectivity line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1fffb000, - .bootrom_size = 0x4800 - }, - {//Low and Medium density VL have same chipid. RM0041 25.6.1 - .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, - .description = "F1xx Value Line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2000,//0x1000 for low density devices - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. - .chip_id = STLINK_CHIPID_STM32_F446, - .description = "F446", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - }, - { - // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. - .chip_id = STLINK_CHIPID_STM32_F410, - .description = "F410", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x4000, - .sram_size = 0x8000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 - }, - { - // This is STK32F303VCT6 device from STM32 F3 Discovery board. - // Support based on DM00043574.pdf (RM0316) document. - .chip_id = STLINK_CHIPID_STM32_F3, - .description = "F3xx", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - // This is STK32F373VCT6 device from STM32 F373 eval board - // Support based on 303 above (37x and 30x have same memory map) - .chip_id = STLINK_CHIPID_STM32_F37x, - .description = "F3xx", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, - .description = "F1xx High-density value line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x8000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 - }, - { - .chip_id = STLINK_CHIPID_STM32_F1_XL, - .description = "F1xx XL-density", - .flash_type = STLINK_FLASH_TYPE_F1_XL, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x18000, - .bootrom_base = 0x1fffe000, - .bootrom_size = 0x1800 - }, - { - //Use this as an example for mapping future chips: - //RM0091 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F0_CAN, - .description = "F07x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 - .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2 - }, - { - //Use this as an example for mapping future chips: - //RM0091 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F0, - .description = "F0xx", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 - }, - { - // RM0402 document was used to find these parameters - // Table 4. - .chip_id = STLINK_CHIPID_STM32_F412, - .description = "F412", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) - .flash_pagesize = 0x4000, // Table 5. Flash module organization ? - .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4 - }, - { - // RM0430 DocID029473 Rev 2 document was used to find these parameters - // Figure 2, Table 4, Table 5, Section 35.2 - .chip_id = STLINK_CHIPID_STM32_F413, - .description = "F413", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 - .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector sizes, but 0x4000 is smallest) - .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 only says 0x40000) - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4 - }, - { - .chip_id = STLINK_CHIPID_STM32_F09X, - .description = "F09X", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) - .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) - .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 - .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2 - }, - { - //Use this as an example for mapping future chips: - //RM0091 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F04, - .description = "F04x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 - }, - { - //Use this as an example for mapping future chips: - //RM0091 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F0_SMALL, - .description = "F0xx small", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 - }, - { - // STM32F30x - .chip_id = STLINK_CHIPID_STM32_F3_SMALL, - .description = "F3xx small", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000 - }, - { - // STM32L0x - // RM0367,RM0377 documents was used to find these parameters - .chip_id = STLINK_CHIPID_STM32_L0, - .description = "L0x3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32L0x Category 5 - // RM0367,RM0377 documents was used to find these parameters - .chip_id = STLINK_CHIPID_STM32_L0_CAT5, - .description = "L0xx Category 5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x5000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x2000, - .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32L0x Category 2 - // RM0367,RM0377 documents was used to find these parameters - .chip_id = STLINK_CHIPID_STM32_L0_CAT2, - .description = "L0xx Category 2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32F334, STM32F303x6/8, and STM32F328 - // From RM0364 and RM0316 - .chip_id = STLINK_CHIPID_STM32_F334, - .description = "F334 medium density", // (RM0316 sec 33.6.1) - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0x3000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000 - }, - { - // This is STK32F303RET6 device from STM32 F3 Nucelo board. - // Support based on DM00043574.pdf (RM0316) document rev 5. - .chip_id = STLINK_CHIPID_STM32_F303_HIGH, - .description = "F303 high density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register - .flash_pagesize = 0x800, // 4.2.1 Flash memory organization - .sram_size = 0x10000, // 3.3 Embedded SRAM - .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory - .bootrom_size = 0x2000 - }, - { - // STM32L4x6 - // From RM0351. - .chip_id = STLINK_CHIPID_STM32_L4, - .description = "L4xx", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = 0x800, // 2K (sec 3.2, page 78; also appears in sec 3.3.1 and tables 4-6 on pages 79-81) - // SRAM1 is "up to" 96k in the standard Cortex-M memory map; - // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32L4RX - // From DM00310109.pdf - .chip_id = STLINK_CHIPID_STM32_L4RX, - .description = "L4Rx", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 97 - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 - .bootrom_size = 0x7000 // 28k (per bank), same source as base (pg 99) - }, - { - // STLINK_CHIPID_STM32_L41X - // From RM0394 Rev 4 and DS12469 Rev 5 - .chip_id = STLINK_CHIPID_STM32_L41X, - .description = "L41x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, sec 47.2, page 1586) - .flash_pagesize = 0x800, // 2K (DS12469, sec 3.4, page 17) - // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 (DS12469, sec 3.5, page 18) - .sram_size = 0xa000, // 40K (DS12469, sec 3.5, page 18) - .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000 // 28k, same source as base - }, - { - // STLINK_CHIPID_STM32_L43X - // From RM0392. - .chip_id = STLINK_CHIPID_STM32_L43X, - .description = "L43x/L44x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = 0x800, // 2K (sec 3.2, page 74; also appears in sec 3.3.1 and tables 7-8 on pages 75-76) - // SRAM1 is "up to" 64k in the standard Cortex-M memory map; - // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0xc000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STLINK_CHIPID_STM32_L496X - // Support based on en.DM00083560.pdf (RM0351) document rev 5. - .chip_id = STLINK_CHIPID_STM32_L496X, - .description = "L496x/L4A6x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) - // SRAM1 is 256k at 0x20000000 - // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) - .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) - .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STLINK_CHIPID_STM32_L46X - // From RM0394 (updated version of RM0392?). - .chip_id = STLINK_CHIPID_STM32_L46X, - .description = "L45x/46x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = 0x800, // 2K (sec 3.2, page 73; also appears in sec 3.3.1 and tables 7 on pages 73-74) - // SRAM1 is 128k at 0x20000000; - // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, page 68, also fig 2 on page 63) - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system memory, also fig 2 on page 63) - .bootrom_size = 0x7000 // 28k (per bank), same source as base - }, - { - // STM32L011 - .chip_id = STLINK_CHIPID_STM32_L011, - .description = "L011", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x2000 - }, - { - // STM32G030/031/041 (from RM0454 & RM0444) - .chip_id = STLINK_CHIPID_STM32_G0_CAT1, - .description = "G030/G031/G041", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2K (sec 3.2) - .sram_size = 0x2000, // 8K (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000, // 8K (sec 2.2.2 table 3) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G071/081 (from RM0444) - .chip_id = STLINK_CHIPID_STM32_G0_CAT2, - .description = "G070/G071/G081", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2K (sec 3.2) - .sram_size = 0x9000, // 36K (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28K (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G431/441 (from RM0440) - .chip_id = STLINK_CHIPID_STM32_G4_CAT2, - .description = "G4 Category-2", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2K (sec 3.3.1) - // SRAM1 is 16k at 0x20000000 - // SRAM2 is 6k at 0x20014000 - // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x8000, // 32K (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28K (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G471/473/474/483/484 (from RM0440) - .chip_id = STLINK_CHIPID_STM32_G4_CAT3, - .description = "G4 Category-3", - .flash_type = STLINK_FLASH_TYPE_G4, - .has_dual_bank = true, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2K (sec 3.3.1) - // SRAM1 is 80k at 0x20000000 - // SRAM2 is 16k at 0x20014000 - // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x18000, // 128K (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28K (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32WB55 (from RM0434) - .chip_id = STLINK_CHIPID_STM32_WB55, - .description = "WB55", - .flash_type = STLINK_FLASH_TYPE_WB, - .flash_size_reg = 0x1FFF75E0, - .flash_pagesize = 0x1000, // 4K - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, // See the memory map - .bootrom_size = 0x7000 - }, - { - // unknown - .chip_id = STLINK_CHIPID_UNKNOWN, - .description = "unknown device", - .flash_type = STLINK_FLASH_TYPE_UNKNOWN, - .flash_size_reg = 0x0, - .flash_pagesize = 0x0, - .sram_size = 0x0, - .bootrom_base = 0x0, - .bootrom_size = 0x0 - }, - }; + { + // RM0410 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F7XXXX, + .description = "F76xxx", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff0f442, // section 45.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x80000, // "SRAM" byte size in hex from + .bootrom_base = 0x00200000, // ! "System memory" starting address from + .bootrom_size = 0xEDC0 // ! @todo "System memory" byte size in hex from + }, + { + // RM0385 and DS10916 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F7, + .description = "F7xx", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff0f442, // section 41.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 + .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18 + }, + { + // RM0431 and DS document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F72XXX, + .description = "F72x/F73x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff07a22, // section 35.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 + .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 24 + }, + { // table 2, PM0063 + .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, + .description = "F1xx Medium-density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x5000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { // table 1, PM0059 + .chip_id = STLINK_CHIPID_STM32_F2, + .description = "F2xx", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, // as in RM0033 Rev 5 + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, + .option_size = 4, + }, + { // PM0063 + .chip_id = STLINK_CHIPID_STM32_F1_LOW, + .description = "F1 Low-density device", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2800, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F4, + .description = "F4xx", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_pagesize = 0x4000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_DSI, + .description = "F46x/F47x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_HD, + .description = "F42x/F43x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_LP, + .description = "F4xx (low power)", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x10000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F411RE, + .description = "stm32f411re", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_DE, + .description = "F4xx (Dynamic Efficency)", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F1_HIGH, + .description = "F1xx High-density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + // This ignores the EEPROM! (and uses the page erase size, + // not the sector write protection...) + .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM, + .description = "L1xx Medium-density", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x4000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = STLINK_CHIPID_STM32_L1_CAT2, + .description = "L1xx Cat.2", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x8000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, + .description = "L1xx Medium-Plus-density", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x8000, // not completely clear if there are some with 48k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = STLINK_CHIPID_STM32_L1_HIGH, + .description = "L1xx High-density", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0xC000, // not completely clear if there are some with 32k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .option_base = STM32_L1_OPTION_BYTES_BASE, + .option_size = 8, + }, + { + .chip_id = STLINK_CHIPID_STM32_L152_RE, + .description = "L152RE", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x14000, // not completely clear if there are some with 32k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = STLINK_CHIPID_STM32_F1_CONN, + .description = "F1 Connectivity line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1fffb000, + .bootrom_size = 0x4800 + }, + { // Low and Medium density VL have same chipid. RM0041 25.6.1 + .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, + .description = "F1xx Value Line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2000, // 0x1000 for low density devices + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. + .chip_id = STLINK_CHIPID_STM32_F446, + .description = "F446", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, + .option_size = 4, + }, + { + // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. + .chip_id = STLINK_CHIPID_STM32_F410, + .description = "F410", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x4000, + .sram_size = 0x8000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + // This is STK32F303VCT6 device from STM32 F3 Discovery board. + // Support based on DM00043574.pdf (RM0316) document. + .chip_id = STLINK_CHIPID_STM32_F3, + .description = "F3xx", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + // This is STK32F373VCT6 device from STM32 F373 eval board + // Support based on 303 above (37x and 30x have same memory map) + .chip_id = STLINK_CHIPID_STM32_F37x, + .description = "F3xx", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, + .description = "F1xx High-density value line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x8000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = STLINK_CHIPID_STM32_F1_XL, + .description = "F1xx XL-density", + .flash_type = STLINK_FLASH_TYPE_F1_XL, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x18000, + .bootrom_base = 0x1fffe000, + .bootrom_size = 0x1800 + }, + { + // Use this as an example for mapping future chips: + // RM0091 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F0_CAN, + .description = "F07x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 + .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 + .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2 + }, + { + // Use this as an example for mapping future chips: + // RM0091 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F0, + .description = "F0xx", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + }, + { + // RM0402 document was used to find these parameters + // Table 4. + .chip_id = STLINK_CHIPID_STM32_F412, + .description = "F412", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) + .flash_pagesize = 0x4000, // Table 5. Flash module organization ? + .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4 + }, + { + // RM0430 DocID029473 Rev 2 document was used to find these parameters + // Figure 2, Table 4, Table 5, Section 35.2 + .chip_id = STLINK_CHIPID_STM32_F413, + .description = "F413", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 + .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector sizes, but 0x4000 is smallest) + .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 only says 0x40000) + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4 + }, + { + .chip_id = STLINK_CHIPID_STM32_F09X, + .description = "F09X", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) + .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) + .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 + .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2 + }, + { + // Use this as an example for mapping future chips: + // RM0091 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F04, + .description = "F04x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + }, + { + // Use this as an example for mapping future chips: + // RM0091 document was used to find these paramaters + .chip_id = STLINK_CHIPID_STM32_F0_SMALL, + .description = "F0xx small", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + }, + { + // STM32F30x + .chip_id = STLINK_CHIPID_STM32_F3_SMALL, + .description = "F3xx small", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1fffd800, + .bootrom_size = 0x2000 + }, + { + // STM32L0x + // RM0367,RM0377 documents was used to find these parameters + .chip_id = STLINK_CHIPID_STM32_L0, + .description = "L0x3", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000, + .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32L0x Category 5 + // RM0367,RM0377 documents was used to find these parameters + .chip_id = STLINK_CHIPID_STM32_L0_CAT5, + .description = "L0xx Category 5", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x5000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x2000, + .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32L0x Category 2 + // RM0367,RM0377 documents was used to find these parameters + .chip_id = STLINK_CHIPID_STM32_L0_CAT2, + .description = "L0xx Category 2", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000, + .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32F334, STM32F303x6/8, and STM32F328 + // From RM0364 and RM0316 + .chip_id = STLINK_CHIPID_STM32_F334, + .description = "F334 medium density", // (RM0316 sec 33.6.1) + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0x3000, + .bootrom_base = 0x1fffd800, + .bootrom_size = 0x2000 + }, + { + // This is STK32F303RET6 device from STM32 F3 Nucelo board. + // Support based on DM00043574.pdf (RM0316) document rev 5. + .chip_id = STLINK_CHIPID_STM32_F303_HIGH, + .description = "F303 high density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register + .flash_pagesize = 0x800, // 4.2.1 Flash memory organization + .sram_size = 0x10000, // 3.3 Embedded SRAM + .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory + .bootrom_size = 0x2000 + }, + { + // STM32L4x6 + // From RM0351. + .chip_id = STLINK_CHIPID_STM32_L4, + .description = "L4xx", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 + // and tables 4-6 on pages 79-81) + // SRAM1 is "up to" 96k in the standard Cortex-M memory map; + // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32L4RX + // From DM00310109.pdf + .chip_id = STLINK_CHIPID_STM32_L4RX, + .description = "L4Rx", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 97 + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 + .bootrom_size = 0x7000 // 28k (per bank), same source as base (pg 99) + }, + { + // STLINK_CHIPID_STM32_L41X + // From RM0394 Rev 4 and DS12469 Rev 5 + .chip_id = STLINK_CHIPID_STM32_L41X, + .description = "L41x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, sec 47.2, page 1586) + .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) + // SRAM1 is 32k at 0x20000000 + // SRAM2 is 8k at 0x10000000 and 0x20008000 (DS12469, sec 3.5, page 18) + .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) + .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) + .bootrom_size = 0x7000 // 28k, same source as base + }, + { + // STLINK_CHIPID_STM32_L43X + // From RM0392. + .chip_id = STLINK_CHIPID_STM32_L43X, + .description = "L43x/L44x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 + // and tables 7-8 on pages 75-76) + // SRAM1 is "up to" 64k in the standard Cortex-M memory map; + // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0xc000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STLINK_CHIPID_STM32_L496X + // Support based on en.DM00083560.pdf (RM0351) document rev 5. + .chip_id = STLINK_CHIPID_STM32_L496X, + .description = "L496x/L4A6x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) + .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) + // SRAM1 is 256k at 0x20000000 + // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) + .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) + .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STLINK_CHIPID_STM32_L46X + // From RM0394 (updated version of RM0392?). + .chip_id = STLINK_CHIPID_STM32_L46X, + .description = "L45x/46x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 + // and tables 7 on pages 73-74) + // SRAM1 is 128k at 0x20000000; + // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, page 68, also fig 2 on page 63) + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system memory, also fig 2 on page 63) + .bootrom_size = 0x7000 // 28k (per bank), same source as base + }, + { + // STM32L011 + .chip_id = STLINK_CHIPID_STM32_L011, + .description = "L011", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x2000 + }, + { + // STM32G030/031/041 (from RM0454 & RM0444) + .chip_id = STLINK_CHIPID_STM32_G0_CAT1, + .description = "G030/G031/G041", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x2000, // 8k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G071/081 (from RM0444) + .chip_id = STLINK_CHIPID_STM32_G0_CAT2, + .description = "G070/G071/G081", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x9000, // 36k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G431/441 (from RM0440) + .chip_id = STLINK_CHIPID_STM32_G4_CAT2, + .description = "G4 Category-2", + .flash_type = STLINK_FLASH_TYPE_G4, + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = 0x800, // 2k (sec 3.3.1) + // SRAM1 is 16k at 0x20000000 + // SRAM2 is 6k at 0x20014000 + // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x8000, // 32k (sec 2.4) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G471/473/474/483/484 (from RM0440) + .chip_id = STLINK_CHIPID_STM32_G4_CAT3, + .description = "G4 Category-3", + .flash_type = STLINK_FLASH_TYPE_G4, + .has_dual_bank = true, + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = 0x800, // 2k (sec 3.3.1) + // SRAM1 is 80k at 0x20000000 + // SRAM2 is 16k at 0x20014000 + // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x18000, // 128k (sec 2.4) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32WB55 (from RM0434) + .chip_id = STLINK_CHIPID_STM32_WB55, + .description = "WB55", + .flash_type = STLINK_FLASH_TYPE_WB, + .flash_size_reg = 0x1FFF75E0, + .flash_pagesize = 0x1000, // 4k + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, // see the memory map + .bootrom_size = 0x7000 + }, + { + // unknown + .chip_id = STLINK_CHIPID_UNKNOWN, + .description = "unknown device", + .flash_type = STLINK_FLASH_TYPE_UNKNOWN, + .flash_size_reg = 0x0, + .flash_pagesize = 0x0, + .sram_size = 0x0, + .bootrom_base = 0x0, + .bootrom_size = 0x0 + }, +}; -const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) -{ - const struct stlink_chipid_params *params = NULL; +const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { + const struct stlink_chipid_params *params = NULL; - for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { - if (devices[n].chip_id == chipid) { - params = &devices[n]; - break; - } - } + for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) + if (devices[n].chip_id == chipid) { + params = &devices[n]; + break; + } - return params; + return(params); } diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 98164a8fc..b591f0012 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -8,79 +8,77 @@ extern "C" { /** * Chip IDs are explained in the appropriate programming manual for the * DBGMCU_IDCODE register (0xE0042000) - * stm32 chipids, only lower 12 bits.. + * stm32 chipids, only lower 12 bits... */ enum stlink_stm32_chipids { - STLINK_CHIPID_UNKNOWN = 0x000, + STLINK_CHIPID_UNKNOWN = 0x000, - STLINK_CHIPID_STM32_F1_MEDIUM = 0x410, - STLINK_CHIPID_STM32_F2 = 0x411, - STLINK_CHIPID_STM32_F1_LOW = 0x412, - STLINK_CHIPID_STM32_F4 = 0x413, - STLINK_CHIPID_STM32_F1_HIGH = 0x414, - STLINK_CHIPID_STM32_L4 = 0x415, - STLINK_CHIPID_STM32_L1_MEDIUM = 0x416, - STLINK_CHIPID_STM32_L0 = 0x417, - STLINK_CHIPID_STM32_F1_CONN = 0x418, - STLINK_CHIPID_STM32_F4_HD = 0x419, - STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW = 0x420, - STLINK_CHIPID_STM32_F446 = 0x421, - STLINK_CHIPID_STM32_F3 = 0x422, - STLINK_CHIPID_STM32_F4_LP = 0x423, - STLINK_CHIPID_STM32_L0_CAT2 = 0x425, - STLINK_CHIPID_STM32_L1_MEDIUM_PLUS = 0x427, /* assigned to some L1 "Medium-plus" chips */ - STLINK_CHIPID_STM32_F1_VL_HIGH = 0x428, - STLINK_CHIPID_STM32_L1_CAT2 = 0x429, - STLINK_CHIPID_STM32_F1_XL = 0x430, - STLINK_CHIPID_STM32_F411RE = 0x431, - STLINK_CHIPID_STM32_F37x = 0x432, - STLINK_CHIPID_STM32_F4_DE = 0x433, - STLINK_CHIPID_STM32_F4_DSI = 0x434, - STLINK_CHIPID_STM32_L43X = 0x435, /* covers STM32L43xxx and STM32L44xxx devices */ - STLINK_CHIPID_STM32_L496X = 0x461, /* covers STM32L496xx and STM32L4A6xx devices */ - STLINK_CHIPID_STM32_L46X = 0x462, /* covers STM32L45xxx and STM32L46xxx devices */ - STLINK_CHIPID_STM32_L41X = 0x464, /* covers STM32L41xxx and STM32L42xxx devices */ - STLINK_CHIPID_STM32_L1_HIGH = 0x436, /* assigned to some L1 chips called "Medium-Plus" and to some called "High" */ - STLINK_CHIPID_STM32_L152_RE = 0x437, - STLINK_CHIPID_STM32_F334 = 0x438, - STLINK_CHIPID_STM32_F3_SMALL = 0x439, - STLINK_CHIPID_STM32_F0 = 0x440, - STLINK_CHIPID_STM32_F412 = 0x441, - STLINK_CHIPID_STM32_F09X = 0x442, - STLINK_CHIPID_STM32_F0_SMALL = 0x444, - STLINK_CHIPID_STM32_F04 = 0x445, - STLINK_CHIPID_STM32_F303_HIGH = 0x446, - STLINK_CHIPID_STM32_L0_CAT5 = 0x447, - STLINK_CHIPID_STM32_F0_CAN = 0x448, - STLINK_CHIPID_STM32_F7 = 0x449, /* This ID is found on the NucleoF746ZG board */ - STLINK_CHIPID_STM32_F7XXXX = 0x451, - STLINK_CHIPID_STM32_F72XXX = 0x452, /* This ID is found on the NucleoF722ZE board */ - STLINK_CHIPID_STM32_L011 = 0x457, - STLINK_CHIPID_STM32_F410 = 0x458, - STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ - STLINK_CHIPID_STM32_F413 = 0x463, - STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ - STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ - STLINK_CHIPID_STM32_G4_CAT3 = 0x469, - STLINK_CHIPID_STM32_L4RX = 0x470, /* taken from the STM32L4R9I-DISCO board */ - STLINK_CHIPID_STM32_WB55 = 0x495 + STLINK_CHIPID_STM32_F1_MEDIUM = 0x410, + STLINK_CHIPID_STM32_F2 = 0x411, + STLINK_CHIPID_STM32_F1_LOW = 0x412, + STLINK_CHIPID_STM32_F4 = 0x413, + STLINK_CHIPID_STM32_F1_HIGH = 0x414, + STLINK_CHIPID_STM32_L4 = 0x415, + STLINK_CHIPID_STM32_L1_MEDIUM = 0x416, + STLINK_CHIPID_STM32_L0 = 0x417, + STLINK_CHIPID_STM32_F1_CONN = 0x418, + STLINK_CHIPID_STM32_F4_HD = 0x419, + STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW = 0x420, + STLINK_CHIPID_STM32_F446 = 0x421, + STLINK_CHIPID_STM32_F3 = 0x422, + STLINK_CHIPID_STM32_F4_LP = 0x423, + STLINK_CHIPID_STM32_L0_CAT2 = 0x425, + STLINK_CHIPID_STM32_L1_MEDIUM_PLUS = 0x427, /* assigned to some L1 "Medium-plus" chips */ + STLINK_CHIPID_STM32_F1_VL_HIGH = 0x428, + STLINK_CHIPID_STM32_L1_CAT2 = 0x429, + STLINK_CHIPID_STM32_F1_XL = 0x430, + STLINK_CHIPID_STM32_F411RE = 0x431, + STLINK_CHIPID_STM32_F37x = 0x432, + STLINK_CHIPID_STM32_F4_DE = 0x433, + STLINK_CHIPID_STM32_F4_DSI = 0x434, + STLINK_CHIPID_STM32_L43X = 0x435, /* covers STM32L43xxx and STM32L44xxx devices */ + STLINK_CHIPID_STM32_L496X = 0x461, /* covers STM32L496xx and STM32L4A6xx devices */ + STLINK_CHIPID_STM32_L46X = 0x462, /* covers STM32L45xxx and STM32L46xxx devices */ + STLINK_CHIPID_STM32_L41X = 0x464, /* covers STM32L41xxx and STM32L42xxx devices */ + STLINK_CHIPID_STM32_L1_HIGH = 0x436, /* assigned to some L1 "Medium-Plus" and "High" chips */ + STLINK_CHIPID_STM32_L152_RE = 0x437, + STLINK_CHIPID_STM32_F334 = 0x438, + STLINK_CHIPID_STM32_F3_SMALL = 0x439, + STLINK_CHIPID_STM32_F0 = 0x440, + STLINK_CHIPID_STM32_F412 = 0x441, + STLINK_CHIPID_STM32_F09X = 0x442, + STLINK_CHIPID_STM32_F0_SMALL = 0x444, + STLINK_CHIPID_STM32_F04 = 0x445, + STLINK_CHIPID_STM32_F303_HIGH = 0x446, + STLINK_CHIPID_STM32_L0_CAT5 = 0x447, + STLINK_CHIPID_STM32_F0_CAN = 0x448, + STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the NucleoF746ZG board */ + STLINK_CHIPID_STM32_F7XXXX = 0x451, + STLINK_CHIPID_STM32_F72XXX = 0x452, /* ID found on the NucleoF722ZE board */ + STLINK_CHIPID_STM32_L011 = 0x457, + STLINK_CHIPID_STM32_F410 = 0x458, + STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ + STLINK_CHIPID_STM32_F413 = 0x463, + STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ + STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ + STLINK_CHIPID_STM32_G4_CAT3 = 0x469, + STLINK_CHIPID_STM32_L4RX = 0x470, /* ID found on the STM32L4R9I-DISCO board */ + STLINK_CHIPID_STM32_WB55 = 0x495 }; -/** - * Chipid parameters - */ +/** Chipid parameters */ struct stlink_chipid_params { - uint32_t chip_id; - char *description; - enum stlink_flash_type flash_type; - bool has_dual_bank; - uint32_t flash_size_reg; - uint32_t flash_pagesize; - uint32_t sram_size; - uint32_t bootrom_base; - uint32_t bootrom_size; - uint32_t option_base; - uint32_t option_size; + uint32_t chip_id; + char *description; + enum stlink_flash_type flash_type; + bool has_dual_bank; + uint32_t flash_size_reg; + uint32_t flash_pagesize; + uint32_t sram_size; + uint32_t bootrom_base; + uint32_t bootrom_size; + uint32_t option_base; + uint32_t option_size; }; const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); @@ -89,4 +87,4 @@ const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); } #endif -#endif /* STLINK_CHIPID_H_ */ +#endif // STLINK_CHIPID_H_ diff --git a/src/commands.h b/src/stlink-lib/commands.h similarity index 97% rename from src/commands.h rename to src/stlink-lib/commands.h index a6830ff26..0925e8e67 100644 --- a/src/commands.h +++ b/src/stlink-lib/commands.h @@ -33,4 +33,4 @@ enum stlink_debug_commands { STLINK_DEBUG_ENTER_SWD = 0xa3 }; -#endif /* STLINK_COMMANDS_H_ */ +#endif // STLINK_COMMANDS_H_ diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index b97a6edaa..71601e3da 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -10,207 +10,203 @@ /* DO NOT MODIFY SOURCECODE DIRECTLY, EDIT ASSEMBLY FILES INSTEAD */ - /* flashloaders/stm32f0.s -- compiled with thumb2 */ - static const uint8_t loader_code_stm32vl[] = { - 0x16, 0x4f, 0x3c, 0x68, - 0x16, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x16, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x4f, 0xf0, 0x01, 0x07, - 0x33, 0x68, 0x3b, 0x43, - 0x33, 0x60, 0x03, 0x88, - 0x0b, 0x80, 0x4f, 0xf0, - 0x02, 0x07, 0xc0, 0x19, - 0xc9, 0x19, 0x4f, 0xf0, - 0x01, 0x07, 0x2b, 0x68, - 0x3b, 0x42, 0xfa, 0xd0, - 0x4f, 0xf0, 0x04, 0x07, - 0x3b, 0x42, 0x04, 0xd1, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xe6, 0xd1, 0x4f, 0xf0, - 0x01, 0x07, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x50, 0x00, 0x00, 0x20, - 0x54, 0x00, 0x00, 0x20, - 0x58, 0x00, 0x00, 0x20 - }; - - /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ - static const uint8_t loader_code_stm32f0[] = { - 0xc0, 0x46, 0xc0, 0x46, - 0x13, 0x4f, 0x3c, 0x68, - 0x13, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x13, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x12, 0x4f, 0x33, 0x68, - 0x3b, 0x43, 0x33, 0x60, - 0x03, 0x88, 0x0b, 0x80, - 0x10, 0x4f, 0xc0, 0x19, - 0xc9, 0x19, 0x0e, 0x4f, - 0x2b, 0x68, 0x3b, 0x42, - 0xfb, 0xd0, 0x0e, 0x4f, - 0x3b, 0x42, 0x03, 0xd1, - 0x0a, 0x4f, 0xd2, 0x1b, - 0x00, 0x2a, 0xeb, 0xd1, - 0x08, 0x4f, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0xc0, 0x46, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x48, 0x00, 0x00, 0x20, - 0x4c, 0x00, 0x00, 0x20, - 0x50, 0x00, 0x00, 0x20, - 0x01, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32l[] = { - // flashloaders/stm32lx.s - - 0x03, 0x68, 0x0b, 0x60, - 0x4f, 0xf0, 0x04, 0x07, - 0x38, 0x44, 0x39, 0x44, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xf4, 0xd1, 0x00, 0xbe, - }; - - static const uint8_t loader_code_stm32f4[] = { - // flashloaders/stm32f4.s - - 0xdf, 0xf8, 0x28, 0xc0, - 0xdf, 0xf8, 0x28, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32f4_lv[] = { - // flashloaders/stm32f4lv.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32l4[] = { - // flashloaders/stm32l4.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x44, 0x68, 0x0b, 0x60, - 0x4c, 0x60, 0x00, 0xf1, - 0x08, 0x00, 0x01, 0xf1, - 0x08, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, - 0x12, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32f7[] = { - // flashloaders/stm32f7.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32f7_lv[] = { - // flashloaders/stm32f7lv.s - 0xdf, 0xf8, 0x30, 0xc0, - 0xdf, 0xf8, 0x30, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - - -int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) -{ - size_t size = 0; - - /* allocate the loader in sram */ - if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { - WLOG("Failed to write flash loader to sram!\n"); - return -1; - } - - /* allocate a one page buffer in sram right after loader */ - fl->buf_addr = fl->loader_addr + (uint32_t) size; - ILOG("Successfully loaded flash loader in sram\n"); - - return 0; +/* flashloaders/stm32f0.s -- compiled with thumb2 */ +static const uint8_t loader_code_stm32vl[] = { + 0x16, 0x4f, 0x3c, 0x68, + 0x16, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x16, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x4f, 0xf0, 0x01, 0x07, + 0x33, 0x68, 0x3b, 0x43, + 0x33, 0x60, 0x03, 0x88, + 0x0b, 0x80, 0x4f, 0xf0, + 0x02, 0x07, 0xc0, 0x19, + 0xc9, 0x19, 0x4f, 0xf0, + 0x01, 0x07, 0x2b, 0x68, + 0x3b, 0x42, 0xfa, 0xd0, + 0x4f, 0xf0, 0x04, 0x07, + 0x3b, 0x42, 0x04, 0xd1, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xe6, 0xd1, 0x4f, 0xf0, + 0x01, 0x07, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x20, + 0x54, 0x00, 0x00, 0x20, + 0x58, 0x00, 0x00, 0x20 +}; + +/* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ +static const uint8_t loader_code_stm32f0[] = { + 0xc0, 0x46, 0xc0, 0x46, + 0x13, 0x4f, 0x3c, 0x68, + 0x13, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x13, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x12, 0x4f, 0x33, 0x68, + 0x3b, 0x43, 0x33, 0x60, + 0x03, 0x88, 0x0b, 0x80, + 0x10, 0x4f, 0xc0, 0x19, + 0xc9, 0x19, 0x0e, 0x4f, + 0x2b, 0x68, 0x3b, 0x42, + 0xfb, 0xd0, 0x0e, 0x4f, + 0x3b, 0x42, 0x03, 0xd1, + 0x0a, 0x4f, 0xd2, 0x1b, + 0x00, 0x2a, 0xeb, 0xd1, + 0x08, 0x4f, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0xc0, 0x46, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x48, 0x00, 0x00, 0x20, + 0x4c, 0x00, 0x00, 0x20, + 0x50, 0x00, 0x00, 0x20, + 0x01, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32l[] = { + // flashloaders/stm32lx.s + + 0x03, 0x68, 0x0b, 0x60, + 0x4f, 0xf0, 0x04, 0x07, + 0x38, 0x44, 0x39, 0x44, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xf4, 0xd1, 0x00, 0xbe, +}; + +static const uint8_t loader_code_stm32f4[] = { + // flashloaders/stm32f4.s + + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32f4_lv[] = { + // flashloaders/stm32f4lv.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32l4[] = { + // flashloaders/stm32l4.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x44, 0x68, 0x0b, 0x60, + 0x4c, 0x60, 0x00, 0xf1, + 0x08, 0x00, 0x01, 0xf1, + 0x08, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x12, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32f7[] = { + // flashloaders/stm32f7.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32f7_lv[] = { + // flashloaders/stm32f7lv.s + 0xdf, 0xf8, 0x30, 0xc0, + 0xdf, 0xf8, 0x30, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + + +int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { + size_t size = 0; + + // allocate the loader in SRAM + if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { + WLOG("Failed to write flash loader to sram!\n"); + return(-1); + } + + // allocate a one page buffer in SRAM right after loader + fl->buf_addr = fl->loader_addr + (uint32_t)size; + ILOG("Successfully loaded flash loader in sram\n"); + + return(0); } static int loader_v_dependent_assignment(stlink_t *sl, const uint8_t **loader_code, size_t *loader_size, const uint8_t *high_v_loader, size_t high_v_loader_size, - const uint8_t *low_v_loader, size_t low_v_loader_size) -{ + const uint8_t *low_v_loader, size_t low_v_loader_size) { int retval = 0; - if ( sl->version.stlink_v == 1){ + if ( sl->version.stlink_v == 1) { printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes\n"); *loader_code = high_v_loader; *loader_size = high_v_loader_size; - } - else { + } else { int voltage = stlink_target_voltage(sl); + if (voltage == -1) { retval = -1; printf("Failed to read Target voltage\n"); - } - else { + } else { if (voltage > 2700) { *loader_code = high_v_loader; *loader_size = high_v_loader_size; @@ -220,11 +216,11 @@ static int loader_v_dependent_assignment(stlink_t *sl, } } } - return retval; + + return(retval); } -int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) -{ +int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { const uint8_t* loader_code; size_t loader_size; @@ -236,7 +232,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_L011 || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */ + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { // STM32l loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || @@ -249,38 +245,34 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || - sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F4_DE || - sl->chip_id == STLINK_CHIPID_STM32_F4_LP || - sl->chip_id == STLINK_CHIPID_STM32_F4_HD || - sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || - sl->chip_id == STLINK_CHIPID_STM32_F410 || - sl->chip_id == STLINK_CHIPID_STM32_F411RE || - sl->chip_id == STLINK_CHIPID_STM32_F412 || - sl->chip_id == STLINK_CHIPID_STM32_F413 || - sl->chip_id == STLINK_CHIPID_STM32_F446 - ) { + sl->chip_id == STLINK_CHIPID_STM32_F4 || + sl->chip_id == STLINK_CHIPID_STM32_F4_DE || + sl->chip_id == STLINK_CHIPID_STM32_F4_LP || + sl->chip_id == STLINK_CHIPID_STM32_F4_HD || + sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || + sl->chip_id == STLINK_CHIPID_STM32_F410 || + sl->chip_id == STLINK_CHIPID_STM32_F411RE || + sl->chip_id == STLINK_CHIPID_STM32_F412 || + sl->chip_id == STLINK_CHIPID_STM32_F413 || + sl->chip_id == STLINK_CHIPID_STM32_F446) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f4, sizeof(loader_code_stm32f4), loader_code_stm32f4_lv, sizeof(loader_code_stm32f4_lv)); - if (retval == -1) { - return retval; - } + + if (retval == -1) { return(retval); } } else if (sl->core_id == STM32F7_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX || - sl->chip_id == STLINK_CHIPID_STM32_F72XXX - ) { + sl->chip_id == STLINK_CHIPID_STM32_F72XXX) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f7, sizeof(loader_code_stm32f7), loader_code_stm32f7_lv, sizeof(loader_code_stm32f7_lv)); - if (retval == -1) { - return retval; - } + + if (retval == -1) { return(retval); } } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || @@ -293,101 +285,102 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* (sl->chip_id == STLINK_CHIPID_STM32_L43X) || (sl->chip_id == STLINK_CHIPID_STM32_L46X) || (sl->chip_id == STLINK_CHIPID_STM32_L4RX) || - (sl->chip_id == STLINK_CHIPID_STM32_L496X)) - { + (sl->chip_id == STLINK_CHIPID_STM32_L496X)) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { - ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", sl->core_id, sl->chip_id); - return -1; + ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", + sl->core_id, sl->chip_id); + return(-1); } memcpy(sl->q_buf, loader_code, loader_size); int ret = stlink_write_mem32(sl, sl->sram_base, loader_size); - if (ret) - return ret; + + if (ret) { return(ret); } *addr = sl->sram_base; *size = loader_size; - /* success */ - return 0; + return(0); // success } -int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) -{ +int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { struct stlink_reg rr; int i = 0; size_t count = 0; uint32_t flash_base = 0; DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); - // FIXME This can never return -1 + + // TODO: This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { // IMPOSSIBLE! ELOG("write_buffer_to_sram() == -1\n"); - return -1; + return(-1); } if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { count = size / sizeof(uint16_t); - if (size % sizeof(uint16_t)) - ++count; + + if (size % sizeof(uint16_t)) { ++count; } } else if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_L0) { count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) - ++count; + + if (size % sizeof(uint32_t)) { ++count; } } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { count = size / sizeof(uint64_t); - if (size % sizeof(uint64_t)) - ++count; + + if (size % sizeof(uint64_t)) { ++count; } } if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { flash_base = FLASH_REGS_BANK2_OFS; } - /* setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); /* source */ - stlink_write_reg(sl, target, 1); /* target */ - stlink_write_reg(sl, (uint32_t) count, 2); /* count */ - stlink_write_reg(sl, flash_base, 3); /* flash register base, only used on VL/F1_XL, but harmless for others */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ + /* Setup core */ + stlink_write_reg(sl, fl->buf_addr, 0); // source + stlink_write_reg(sl, target, 1); // target + stlink_write_reg(sl, (uint32_t)count, 2); // count + stlink_write_reg(sl, flash_base, 3); // flash register base + // only used on VL/F1_XL, but harmless for others + stlink_write_reg(sl, fl->loader_addr, 15); // pc register - /* run loader */ + /* Run loader */ stlink_run(sl); -// This piece of code used to try to spin for .1 second by waiting -// doing 10000 rounds of 10 microseconds. But because this usually runs -// on Unix-like OSes, the 10 microseconds get rounded up to the "tick" -// (actually almost two ticks) of the system. 1 milisecond. Thus, the -// ten thousand attempts, when "something goes wrong" that requires -// the error message "flash loader run error" would wait for something -// like 20 seconds before coming up with the error. -// by increasing the sleep-per-round to the same order-of-magnitude as -// the tick-rounding that the OS uses, the wait until the error message is -// reduced to the same order of magnitude as what was intended. -- REW. +/* This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. + * But because this usually runs on Unix-like OSes, the 10 µs get rounded up to the "tick" + * (actually almost two ticks) of the system. 1 ms. Thus, the ten thousand attempts, when + * "something goes wrong" that requires the error message "flash loader run error" would wait + * for something like 20 seconds before coming up with the error. + * By increasing the sleep-per-round to the same order-of-magnitude as the tick-rounding that + * the OS uses, the wait until the error message is reduced to the same order of magnitude + * as what was intended. -- REW. + */ #define WAIT_ROUNDS 100 - /* wait until done (reaches breakpoint) */ + + // wait until done (reaches breakpoint) for (i = 0; i < WAIT_ROUNDS; i++) { usleep(1000); - if (stlink_is_core_halted(sl)) - break; + + if (stlink_is_core_halted(sl)) { break; } } if (i >= WAIT_ROUNDS) { ELOG("flash loader run error\n"); - return -1; + return(-1); } - /* check written byte count */ + // check written byte count stlink_read_reg(sl, 2, &rr); + if (rr.r[2] != 0) { ELOG("write error, count == %u\n", rr.r[2]); - return -1; + return(-1); } - return 0; + return(0); } diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 5f4526114..29fd5b068 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -1,8 +1,8 @@ /* - * File: stlink.h + * File: stlink.h * - * This should contain all the common top level stlink interfaces, regardless - * of how the backend does the work.... + * This should contain all the common top level stlink interfaces, + * regardless of how the backend does the work.... */ #ifndef STLINK_FLASH_LOADER_H_ #define STLINK_FLASH_LOADER_H_ @@ -24,4 +24,4 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe } #endif -#endif /* STLINK_FLASH_LOADER_H_ */ +#endif // STLINK_FLASH_LOADER_H_ diff --git a/src/libusb_settings.h b/src/stlink-lib/libusb_settings.h similarity index 53% rename from src/libusb_settings.h rename to src/stlink-lib/libusb_settings.h index c2e2df923..046c0b33d 100644 --- a/src/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -5,24 +5,24 @@ /* - libusb ver | LIBUSB_API_VERSION --------------+-------------------- - v1.0.13 | 0x01000100 - v1.0.14 | 0x010000FF - v1.0.15 | 0x01000101 - v1.0.16 | 0x01000102 - v1.0.17 | 0x01000102 - v1.0.18 | 0x01000102 - v1.0.19 | 0x01000103 - v1.0.20 | 0x01000104 - v1.0.21 | 0x01000105 - v1.0.22 | 0x01000106 - v1.0.23 | 0x01000107 - -*/ + libusb ver | LIBUSB_API_VERSION + -----------+-------------------- + v1.0.13 | 0x01000100 + v1.0.14 | 0x010000FF + v1.0.15 | 0x01000101 + v1.0.16 | 0x01000102 + v1.0.17 | 0x01000102 + v1.0.18 | 0x01000102 + v1.0.19 | 0x01000103 + v1.0.20 | 0x01000104 + v1.0.21 | 0x01000105 + v1.0.22 | 0x01000106 + v1.0.23 | 0x01000107 + + */ #if defined (__FreeBSD__) - #if !defined ( LIBUSBX_API_VERSION ) + #if !defined (LIBUSBX_API_VERSION) #define LIBUSBX_API_VERSION LIBUSB_API_VERSION #elif !defined (LIBUSB_API_VERSION) #error unsupported libusb version @@ -39,8 +39,8 @@ #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 #endif -#if ( LIBUSB_API_VERSION < MINIMAL_API_VERSION ) +#if (LIBUSB_API_VERSION < MINIMAL_API_VERSION) #error unsupported libusb version #endif -#endif // STLINKUSB_H +#endif // LIBUSB_SETTINGS_H diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index ad144f6a4..a5eef9e17 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -1,7 +1,7 @@ /* - * UglyLogging. Slow, yet another wheel reinvented, but enough to make the - * rest of our code pretty enough. + * UglyLogging * + * Slow, yet another wheel reinvented, but enough to make the rest of our code pretty enough. */ #include #include @@ -15,23 +15,24 @@ static int max_level = UDEBUG; int ugly_init(int maximum_threshold) { max_level = maximum_threshold; - return 0; + return(0); } int ugly_log(int level, const char *tag, const char *format, ...) { if (level > max_level) { - return 0; + return(0); } - // Flush to maintain order of streams - fflush(stdout); + fflush(stdout); // flush to maintain order of streams va_list args; va_start(args, format); time_t mytt = time(NULL); struct tm *tt; tt = localtime(&mytt); - fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt->tm_year + 1900, tt->tm_mon + 1, tt->tm_mday, tt->tm_hour, tt->tm_min, tt->tm_sec); + fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt->tm_year + 1900, tt->tm_mon + 1, + tt->tm_mday, tt->tm_hour, tt->tm_min, tt->tm_sec); + switch (level) { case UDEBUG: fprintf(stderr, "DEBUG %s: ", tag); @@ -49,13 +50,13 @@ int ugly_log(int level, const char *tag, const char *format, ...) { fprintf(stderr, "%d %s: ", level, tag); break; } + vfprintf(stderr, format, args); fflush(stderr); va_end(args); - return 1; + return(1); } - /* * Log message levels. * - LIBUSB_LOG_LEVEL_NONE (0) : no messages ever printed by the library (default) @@ -63,15 +64,14 @@ int ugly_log(int level, const char *tag, const char *format, ...) { * - LIBUSB_LOG_LEVEL_WARNING (2) : warning and error messages are printed to stderr * - LIBUSB_LOG_LEVEL_INFO (3) : informational messages are printed to stderr * - LIBUSB_LOG_LEVEL_DEBUG (4) : debug and informational messages are printed to stderr -*/ -int ugly_libusb_log_level(enum ugly_loglevel v) -{ + */ +int ugly_libusb_log_level(enum ugly_loglevel v) { switch (v) { - case UDEBUG: return 4; - case UINFO: return 3; - case UWARN: return 2; - case UERROR: return 1; - }; + case UDEBUG: return(4); + case UINFO: return(3); + case UWARN: return(2); + case UERROR: return(1); + } - return 2; + return(2); } diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index 1083b2c55..78562b0d9 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -3,9 +3,9 @@ */ #ifndef UGLYLOGGING_H -#define UGLYLOGGING_H +#define UGLYLOGGING_H -#ifdef __cplusplus +#ifdef __cplusplus extern "C" { #endif @@ -21,11 +21,11 @@ int ugly_log(int level, const char *tag, const char *format, ...); int ugly_libusb_log_level(enum ugly_loglevel v); #define UGLY_LOG_FILE (strstr(__FILE__, "/") != NULL ? \ - strrchr(__FILE__, '/') + 1 : strstr(__FILE__, "\\") != NULL ? \ - strrchr(__FILE__, '\\') + 1 : __FILE__) + strrchr(__FILE__, '/') + 1 : strstr(__FILE__, "\\") != NULL ? \ + strrchr(__FILE__, '\\') + 1 : __FILE__) -/** @todo we need to write this in a more generic way, for now this should compile - on visual studio (See http://stackoverflow.com/a/8673872/1836746) */ +// TODO: we need to write this in a more generic way, for now this should compile +// on visual studio (See http://stackoverflow.com/a/8673872/1836746) #define DLOG_HELPER(format, ...) ugly_log(UDEBUG, UGLY_LOG_FILE, format, __VA_ARGS__) #define DLOG(...) DLOG_HELPER(__VA_ARGS__, "") #define ILOG_HELPER(format, ...) ugly_log(UINFO, UGLY_LOG_FILE, format, __VA_ARGS__) @@ -35,9 +35,8 @@ int ugly_libusb_log_level(enum ugly_loglevel v); #define ELOG_HELPER(format, ...) ugly_log(UERROR, UGLY_LOG_FILE, format, __VA_ARGS__) #define ELOG(...) ELOG_HELPER(__VA_ARGS__, "") -#ifdef __cplusplus +#ifdef __cplusplus } #endif -#endif /* UGLYLOGGING_H */ - +#endif // UGLYLOGGING_H diff --git a/src/stlink-lib/md5.c b/src/stlink-lib/md5.c index 521c52969..4c353bfd6 100755 --- a/src/stlink-lib/md5.c +++ b/src/stlink-lib/md5.c @@ -1,80 +1,53 @@ /* - * Retrieved from https://github.com/WaterJuice/WjCryptLib + * WjCryptLib_Md5 (https://github.com/WaterJuice/WjCryptLib) + * Implementation of MD5 hash function. Originally written by Alexander Peslyak. + * Modified by WaterJuice retaining Public Domain license. + * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org */ -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// WjCryptLib_Md5 -// -// Implementation of MD5 hash function. Originally written by Alexander Peslyak. Modified by WaterJuice retaining -// Public Domain license. -// -// This is free and unencumbered software released into the public domain - June 2013 waterjuice.org -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// IMPORTS -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - #include #include "md5.h" -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// INTERNAL FUNCTIONS -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// F, G, H, I -// -// The basic MD5 functions. F and G are optimised compared to their RFC 1321 definitions for architectures that lack -// an AND-NOT instruction, just like in Colin Plumb's implementation. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -#define F( x, y, z ) ( (z) ^ ((x) & ((y) ^ (z))) ) -#define G( x, y, z ) ( (y) ^ ((z) & ((x) ^ (y))) ) -#define H( x, y, z ) ( (x) ^ (y) ^ (z) ) -#define I( x, y, z ) ( (y) ^ ((x) | ~(z)) ) - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// STEP -// -// The MD5 transformation for all four rounds. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/* INTERNAL FUNCTIONS */ + +/* F, G, H, I + * + * The basic MD5 functions. + * F and G are optimised compared to their RFC 1321 definitions for architectures + * that lack an AND-NOT instruction, just like in Colin Plumb's implementation. + */ +#define F( x, y, z ) ((z) ^ ((x) & ((y) ^ (z)))) +#define G( x, y, z ) ((y) ^ ((z) & ((x) ^ (y)))) +#define H( x, y, z ) ((x) ^ (y) ^ (z)) +#define I( x, y, z ) ((y) ^ ((x) | ~(z))) + +/* STEP: The MD5 transformation for all four rounds. */ #define STEP( f, a, b, c, d, x, t, s ) \ (a) += f((b), (c), (d)) + (x) + (t); \ (a) = (((a) << (s)) | (((a) & 0xffffffff) >> (32 - (s)))); \ (a) += (b); -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// TransformFunction -// -// This processes one or more 64-byte data blocks, but does NOT update the bit counters. There are no alignment -// requirements. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -static -void* - TransformFunction - ( - Md5Context* ctx, - void const* data, - uintmax_t size - ) -{ +/* TransformFunction + * This processes one or more 64-byte data blocks, but does NOT update the bit counters. + * There are no alignment requirements. + */ +static void* TransformFunction(Md5Context* ctx, void const* data, uintmax_t size) { uint8_t* ptr; - uint32_t a; - uint32_t b; - uint32_t c; - uint32_t d; - uint32_t saved_a; - uint32_t saved_b; - uint32_t saved_c; - uint32_t saved_d; + uint32_t a; + uint32_t b; + uint32_t c; + uint32_t d; + uint32_t saved_a; + uint32_t saved_b; + uint32_t saved_c; + uint32_t saved_d; #define GET(n) (ctx->block[(n)]) - #define SET(n) (ctx->block[(n)] = \ - ((uint32_t)ptr[(n)*4 + 0] << 0) \ - | ((uint32_t)ptr[(n)*4 + 1] << 8 ) \ - | ((uint32_t)ptr[(n)*4 + 2] << 16) \ - | ((uint32_t)ptr[(n)*4 + 3] << 24) ) + #define SET(n) (ctx->block[(n)] = ((uint32_t)ptr[(n) * 4 + 0] << 0) | \ + ((uint32_t)ptr[(n) * 4 + 1] << 8) | \ + ((uint32_t)ptr[(n) * 4 + 2] << 16) | \ + ((uint32_t)ptr[(n) * 4 + 3] << 24)) ptr = (uint8_t*)data; @@ -83,8 +56,7 @@ void* c = ctx->c; d = ctx->d; - do - { + do { saved_a = a; saved_b = b; saved_c = c; @@ -178,24 +150,16 @@ void* #undef GET #undef SET - return ptr; + return(ptr); } -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// EXPORTED FUNCTIONS -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Initialise -// -// Initialises an MD5 Context. Use this to initialise/reset a context. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Initialise - ( - Md5Context* Context // [out] - ) -{ +/* EXPORTED FUNCTIONS */ + +/* Md5Initialise + * Initialises an MD5 Context. + * Use this to initialise/reset a context. + */ +void Md5Initialise(Md5Context* Context /* [out] */) { Context->a = 0x67452301; Context->b = 0xefcdab89; Context->c = 0x98badcfe; @@ -205,39 +169,31 @@ void Context->hi = 0; } -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Update -// -// Adds data to the MD5 context. This will process the data and update the internal state of the context. Keep on -// calling this function until all the data has been added. Then call Md5Finalise to calculate the hash. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Update - ( - Md5Context* Context, // [in out] - void const* Buffer, // [in] - uint32_t BufferSize // [in] - ) -{ - uint32_t saved_lo; - uint32_t used; - uint32_t free; +/* Md5Update + * Adds data to the MD5 context. + * This will process the data and update the internal state of the context. + * Keep on calling this function until all the data has been added. + * Then call Md5Finalise to calculate the hash. + */ +void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */) { + uint32_t saved_lo; + uint32_t used; + uint32_t free; saved_lo = Context->lo; - if ( (Context->lo = (saved_lo + BufferSize) & 0x1fffffff) < saved_lo ) - { + + if ((Context->lo = (saved_lo + BufferSize) & 0x1fffffff) < saved_lo) { Context->hi++; } - Context->hi += (uint32_t)( BufferSize >> 29 ); + + Context->hi += (uint32_t)(BufferSize >> 29); used = saved_lo & 0x3f; - if ( used ) - { + if ( used ) { free = 64 - used; - if ( BufferSize < free ) - { + if ( BufferSize < free ) { memcpy( &Context->buffer[used], Buffer, BufferSize ); return; } @@ -248,8 +204,7 @@ void TransformFunction(Context, Context->buffer, 64); } - if ( BufferSize >= 64 ) - { + if ( BufferSize >= 64 ) { Buffer = TransformFunction( Context, Buffer, BufferSize & ~(unsigned long)0x3f ); BufferSize &= 0x3f; } @@ -257,21 +212,14 @@ void memcpy( Context->buffer, Buffer, BufferSize ); } -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Finalise -// -// Performs the final calculation of the hash and returns the digest (16 byte buffer containing 128bit hash). After -// calling this, Md5Initialised must be used to reuse the context. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Finalise - ( - Md5Context* Context, // [in out] - MD5_HASH* Digest // [in] - ) -{ - uint32_t used; - uint32_t free; +/* Md5Finalise + * Performs the final calculation of the hash and returns the digest + * (16 byte buffer containing 128bit hash). + * After calling this, Md5Initialised must be used to reuse the context. + */ +void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */) { + uint32_t used; + uint32_t free; used = Context->lo & 0x3f; @@ -279,8 +227,7 @@ void free = 64 - used; - if (free < 8) - { + if (free < 8) { memset( &Context->buffer[used], 0, free ); TransformFunction( Context, Context->buffer, 64 ); used = 0; @@ -290,48 +237,40 @@ void memset( &Context->buffer[used], 0, free - 8 ); Context->lo <<= 3; - Context->buffer[56] = (uint8_t)( Context->lo ); - Context->buffer[57] = (uint8_t)( Context->lo >> 8 ); - Context->buffer[58] = (uint8_t)( Context->lo >> 16 ); - Context->buffer[59] = (uint8_t)( Context->lo >> 24 ); - Context->buffer[60] = (uint8_t)( Context->hi ); - Context->buffer[61] = (uint8_t)( Context->hi >> 8 ); - Context->buffer[62] = (uint8_t)( Context->hi >> 16 ); - Context->buffer[63] = (uint8_t)( Context->hi >> 24 ); + Context->buffer[56] = (uint8_t)(Context->lo); + Context->buffer[57] = (uint8_t)(Context->lo >> 8); + Context->buffer[58] = (uint8_t)(Context->lo >> 16); + Context->buffer[59] = (uint8_t)(Context->lo >> 24); + Context->buffer[60] = (uint8_t)(Context->hi); + Context->buffer[61] = (uint8_t)(Context->hi >> 8); + Context->buffer[62] = (uint8_t)(Context->hi >> 16); + Context->buffer[63] = (uint8_t)(Context->hi >> 24); TransformFunction( Context, Context->buffer, 64 ); - Digest->bytes[0] = (uint8_t)( Context->a ); - Digest->bytes[1] = (uint8_t)( Context->a >> 8 ); - Digest->bytes[2] = (uint8_t)( Context->a >> 16 ); - Digest->bytes[3] = (uint8_t)( Context->a >> 24 ); - Digest->bytes[4] = (uint8_t)( Context->b ); - Digest->bytes[5] = (uint8_t)( Context->b >> 8 ); - Digest->bytes[6] = (uint8_t)( Context->b >> 16 ); - Digest->bytes[7] = (uint8_t)( Context->b >> 24 ); - Digest->bytes[8] = (uint8_t)( Context->c ); - Digest->bytes[9] = (uint8_t)( Context->c >> 8 ); - Digest->bytes[10] = (uint8_t)( Context->c >> 16 ); - Digest->bytes[11] = (uint8_t)( Context->c >> 24 ); - Digest->bytes[12] = (uint8_t)( Context->d ); - Digest->bytes[13] = (uint8_t)( Context->d >> 8 ); - Digest->bytes[14] = (uint8_t)( Context->d >> 16 ); - Digest->bytes[15] = (uint8_t)( Context->d >> 24 ); + Digest->bytes[0] = (uint8_t)(Context->a); + Digest->bytes[1] = (uint8_t)(Context->a >> 8); + Digest->bytes[2] = (uint8_t)(Context->a >> 16); + Digest->bytes[3] = (uint8_t)(Context->a >> 24); + Digest->bytes[4] = (uint8_t)(Context->b); + Digest->bytes[5] = (uint8_t)(Context->b >> 8); + Digest->bytes[6] = (uint8_t)(Context->b >> 16); + Digest->bytes[7] = (uint8_t)(Context->b >> 24); + Digest->bytes[8] = (uint8_t)(Context->c); + Digest->bytes[9] = (uint8_t)(Context->c >> 8); + Digest->bytes[10] = (uint8_t)(Context->c >> 16); + Digest->bytes[11] = (uint8_t)(Context->c >> 24); + Digest->bytes[12] = (uint8_t)(Context->d); + Digest->bytes[13] = (uint8_t)(Context->d >> 8); + Digest->bytes[14] = (uint8_t)(Context->d >> 16); + Digest->bytes[15] = (uint8_t)(Context->d >> 24); } -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Calculate -// -// Combines Md5Initialise, Md5Update, and Md5Finalise into one function. Calculates the MD5 hash of the buffer. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Calculate - ( - void const* Buffer, // [in] - uint32_t BufferSize, // [in] - MD5_HASH* Digest // [in] - ) -{ +/* Md5Calculate + * Combines Md5Initialise, Md5Update, and Md5Finalise into one function. + * Calculates the MD5 hash of the buffer. + */ +void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */) { Md5Context context; Md5Initialise( &context ); diff --git a/src/stlink-lib/md5.h b/src/stlink-lib/md5.h index 5ef252221..a69d7fc6b 100755 --- a/src/stlink-lib/md5.h +++ b/src/stlink-lib/md5.h @@ -1,100 +1,63 @@ /* - * Retrieved from https://github.com/WaterJuice/WjCryptLib + * WjCryptLib_Md5 (https://github.com/WaterJuice/WjCryptLib) + * Implementation of MD5 hash function. Originally written by Alexander Peslyak. + * Modified by WaterJuice retaining Public Domain license. + * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org */ -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// WjCryptLib_Md5 -// -// Implementation of MD5 hash function. Originally written by Alexander Peslyak. Modified by WaterJuice retaining -// Public Domain license. -// -// This is free and unencumbered software released into the public domain - June 2013 waterjuice.org -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - #pragma once -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// IMPORTS -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// - #include #include -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// TYPES -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/* TYPES */ -// Md5Context - This must be initialised using Md5Initialised. Do not modify the contents of this structure directly. -typedef struct -{ - uint32_t lo; - uint32_t hi; - uint32_t a; - uint32_t b; - uint32_t c; - uint32_t d; - uint8_t buffer[64]; - uint32_t block[16]; +/* Md5Context + * This must be initialised using Md5Initialised. + * Do not modify the contents of this structure directly. + */ +typedef struct { + uint32_t lo; + uint32_t hi; + uint32_t a; + uint32_t b; + uint32_t c; + uint32_t d; + uint8_t buffer[64]; + uint32_t block[16]; } Md5Context; -#define MD5_HASH_SIZE ( 128 / 8 ) +#define MD5_HASH_SIZE (128 / 8) -typedef struct -{ - uint8_t bytes [MD5_HASH_SIZE]; +typedef struct { + uint8_t bytes [MD5_HASH_SIZE]; } MD5_HASH; -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// PUBLIC FUNCTIONS -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/* PUBLIC FUNCTIONS */ -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Initialise -// -// Initialises an MD5 Context. Use this to initialise/reset a context. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Initialise - ( - Md5Context* Context // [out] - ); +/* Md5Initialise + * Initialises an MD5 Context. + * Use this to initialise/reset a context. + */ +void Md5Initialise(Md5Context* Context /* [out] */); -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Update -// -// Adds data to the MD5 context. This will process the data and update the internal state of the context. Keep on -// calling this function until all the data has been added. Then call Md5Finalise to calculate the hash. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Update - ( - Md5Context* Context, // [in out] - void const* Buffer, // [in] - uint32_t BufferSize // [in] - ); +/* Md5Update + * Adds data to the MD5 context. + * This will process the data and update the internal state of the context. + * Keep on calling this function until all the data has been added. + * Then call Md5Finalise to calculate the hash. + */ +void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */); -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Finalise -// -// Performs the final calculation of the hash and returns the digest (16 byte buffer containing 128bit hash). After -// calling this, Md5Initialised must be used to reuse the context. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Finalise - ( - Md5Context* Context, // [in out] - MD5_HASH* Digest // [in] - ); +/* Md5Finalise + * Performs the final calculation of the hash and returns the digest + * (16 byte buffer containing 128bit hash). + * After calling this, Md5Initialised must be used to reuse the context. + */ +void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */); -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -// Md5Calculate -// -// Combines Md5Initialise, Md5Update, and Md5Finalise into one function. Calculates the MD5 hash of the buffer. -//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -void - Md5Calculate - ( - void const* Buffer, // [in] - uint32_t BufferSize, // [in] - MD5_HASH* Digest // [in] - ); +/* Md5Calculate + * Combines Md5Initialise, Md5Update, and Md5Finalise into one function. + * Calculates the MD5 hash of the buffer. + */ +void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */); diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h new file mode 100644 index 000000000..dde77ef50 --- /dev/null +++ b/src/stlink-lib/reg.h @@ -0,0 +1,20 @@ +#ifndef STLINK_REG_H_ +#define STLINK_REG_H_ + +#define STLINK_REG_CM3_CPUID 0xE000ED00 +#define STLINK_REG_CM3_FP_CTRL 0xE0002000 +#define STLINK_REG_CM3_FP_COMP0 0xE0002008 + +/* Cortex™-M3 Technical Reference Manual */ +/* Debug Halting Control and Status Register */ +#define STLINK_REG_DHCSR 0xe000edf0 +#define STLINK_REG_DHCSR_DBGKEY 0xa05f0000 +#define STLINK_REG_DCRSR 0xe000edf4 +#define STLINK_REG_DCRDR 0xe000edf8 + +/* Application Interrupt and Reset Control Register */ +#define STLINK_REG_AIRCR 0xe000ed0c +#define STLINK_REG_AIRCR_VECTKEY 0x05fa0000 +#define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004 + +#endif // STLINK_REG_H_ diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 7fae19976..5cc27b1fe 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -27,7 +27,7 @@ * www.usb.org/developers/devclass_docs/usbmassbulk_10.pdf * * dt - Data Transfer (IN/OUT) - * CBW - Command Block Wrapper + * CBW - Command Block Wrapper * CSW - Command Status Wrapper * RFU - Reserved for Future Use * @@ -90,8 +90,8 @@ #define STLINK_FALSE 0x81 static void clear_cdb(struct stlink_libsg *sl) { - for (size_t i = 0; i < sizeof (sl->cdb_cmd_blk); i++) - sl->cdb_cmd_blk[i] = 0; + for (size_t i = 0; i < sizeof(sl->cdb_cmd_blk); i++) { sl->cdb_cmd_blk[i] = 0; } + // set default sl->cdb_cmd_blk[0] = STLINK_DEBUG_COMMAND; sl->q_data_dir = Q_DATA_IN; @@ -116,46 +116,53 @@ static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t end int transferred; int ret; int try = 0; + do { ret = libusb_bulk_transfer(handle, endpoint, (unsigned char *)&csw, sizeof(csw), - &transferred, SG_TIMEOUT_MSEC); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(handle, endpoint); - } + &transferred, SG_TIMEOUT_MSEC); + + if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(handle, endpoint); } + try++; } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { WLOG("%s: receiving failed: %d\n", __func__, ret); - return -1; + return(-1); } + if (transferred != sizeof(csw)) { WLOG("%s: received unexpected amount: %d\n", __func__, transferred); - return -1; + return(-1); } uint32_t rsig = read_uint32(csw, 0); uint32_t rtag = read_uint32(csw, 4); /* uint32_t residue = read_uint32(csw, 8); */ #define USB_CSW_SIGNATURE 0x53425355 // 'U' 'S' 'B' 'S' (reversed) + if (rsig != USB_CSW_SIGNATURE) { WLOG("status signature was invalid: %#x\n", rsig); - return -1; + return(-1); } + *tag = rtag; uint8_t rstatus = csw[12]; - return rstatus; + return(rstatus); } static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { char dbugblah[100]; char *dbugp = dbugblah; dbugp += sprintf(dbugp, "Sending CDB ["); + for (uint8_t i = 0; i < cdb_len; i++) { - dbugp += sprintf(dbugp, " %#02x", (unsigned int) cdb[i]); + dbugp += sprintf(dbugp, " %#02x", (unsigned int)cdb[i]); } + sprintf(dbugp, "]\n"); DLOG(dbugblah); - return 0; + return(0); } /** @@ -170,15 +177,14 @@ static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { * @return */ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, - uint8_t *cdb, uint8_t cdb_length, - uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { + uint8_t *cdb, uint8_t cdb_length, + uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { DLOG("Sending usb m-s cmd: cdblen:%d, rxsize=%d\n", cdb_length, expected_rx_size); dump_CDB_command(cdb, cdb_length); static uint32_t tag; - if (tag == 0) { - tag = 1; - } + + if (tag == 0) { tag = 1; } int try = 0; int ret = 0; @@ -193,14 +199,14 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint c_buf[i++] = 'C'; write_uint32(&c_buf[i], tag); uint32_t this_tag = tag++; - write_uint32(&c_buf[i+4], expected_rx_size); - i+= 8; + write_uint32(&c_buf[i + 4], expected_rx_size); + i += 8; c_buf[i++] = flags; c_buf[i++] = lun; c_buf[i++] = cdb_length; - // Now the actual CDB request + // now the actual CDB request assert(cdb_length <= CDB_SL); memcpy(&(c_buf[i]), cdb, cdb_length); @@ -209,19 +215,22 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint // send.... do { ret = libusb_bulk_transfer(handle, endpoint_out, c_buf, sending_length, - &real_transferred, SG_TIMEOUT_MSEC); + &real_transferred, SG_TIMEOUT_MSEC); + if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(handle, endpoint_out); } + try++; } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { WLOG("sending failed: %d\n", ret); - return -1; + return(-1); } - return this_tag; -} + return(this_tag); +} /** * Straight from stm8 stlink code... @@ -238,36 +247,44 @@ static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t cdb[0] = REQUEST_SENSE; cdb[4] = REQUEST_SENSE_LENGTH; uint32_t tag = send_usb_mass_storage_command(handle, endpoint_out, cdb, sizeof(cdb), 0, - LIBUSB_ENDPOINT_IN, REQUEST_SENSE_LENGTH); + LIBUSB_ENDPOINT_IN, REQUEST_SENSE_LENGTH); + if (tag == 0) { WLOG("refusing to send request sense with tag 0\n"); return; } + unsigned char sense[REQUEST_SENSE_LENGTH]; int transferred; int ret; int try = 0; + do { ret = libusb_bulk_transfer(handle, endpoint_in, sense, sizeof(sense), - &transferred, SG_TIMEOUT_MSEC); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(handle, endpoint_in); - } + &transferred, SG_TIMEOUT_MSEC); + + if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(handle, endpoint_in); } + try++; } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { WLOG("receiving sense failed: %d\n", ret); return; } + if (transferred != sizeof(sense)) { WLOG("received unexpected amount of sense: %d != %d\n", transferred, sizeof(sense)); } + uint32_t received_tag; int status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); + if (status != 0) { WLOG("receiving sense failed with status: %02x\n", status); return; } + if (sense[0] != 0x70 && sense[0] != 0x71) { WLOG("No sense data\n"); } else { @@ -286,49 +303,55 @@ static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t * @return number of bytes actually sent, or -1 for failures. */ int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, - unsigned char endpoint_in, unsigned char *cbuf, unsigned int length) { + unsigned char endpoint_in, unsigned char *cbuf, unsigned int length) { int ret; int real_transferred; int try = 0; + do { ret = libusb_bulk_transfer(handle, endpoint_out, cbuf, length, - &real_transferred, SG_TIMEOUT_MSEC); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(handle, endpoint_out); - } + &real_transferred, SG_TIMEOUT_MSEC); + + if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(handle, endpoint_out); } + try++; } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); + if (ret != LIBUSB_SUCCESS) { WLOG("sending failed: %d\n", ret); - return -1; + return(-1); } // now, swallow up the status, so that things behave nicely... uint32_t received_tag; // -ve is for my errors, 0 is good, +ve is libusb sense status bytes int status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); + if (status < 0) { WLOG("receiving status failed: %d\n", status); - return -1; + return(-1); } + if (status != 0) { WLOG("receiving status not passed :(: %02x\n", status); } + if (status == 1) { get_sense(handle, endpoint_in, endpoint_out); - return -1; + return(-1); } - return real_transferred; + return(real_transferred); } int stlink_q(stlink_t *sl) { struct stlink_libsg* sg = sl->backend_data; - //uint8_t cdb_len = 6; // FIXME varies!!! + // uint8_t cdb_len = 6; // FIXME varies!!! uint8_t cdb_len = 10; // FIXME varies!!! uint8_t lun = 0; // always zero... uint32_t tag = send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, - sg->cdb_cmd_blk, cdb_len, lun, LIBUSB_ENDPOINT_IN, sl->q_len); + sg->cdb_cmd_blk, cdb_len, lun, + LIBUSB_ENDPOINT_IN, sl->q_len); // now wait for our response... @@ -337,19 +360,20 @@ int stlink_q(stlink_t *sl) { int try = 0; int real_transferred; int ret; + if (rx_length > 0) { do { ret = libusb_bulk_transfer(sg->usb_handle, sg->ep_rep, sl->q_buf, rx_length, - &real_transferred, SG_TIMEOUT_MSEC); - if (ret == LIBUSB_ERROR_PIPE) { - libusb_clear_halt(sg->usb_handle, sg->ep_req); - } + &real_transferred, SG_TIMEOUT_MSEC); + + if (ret == LIBUSB_ERROR_PIPE) { libusb_clear_halt(sg->usb_handle, sg->ep_req); } + try++; } while ((ret == LIBUSB_ERROR_PIPE) && (try < 3)); if (ret != LIBUSB_SUCCESS) { WLOG("Receiving failed: %d\n", ret); - return -1; + return(-1); } if (real_transferred != rx_length) { @@ -360,31 +384,36 @@ int stlink_q(stlink_t *sl) { uint32_t received_tag; // -ve is for my errors, 0 is good, +ve is libusb sense status bytes int status = get_usb_mass_storage_status(sg->usb_handle, sg->ep_rep, &received_tag); + if (status < 0) { WLOG("receiving status failed: %d\n", status); - return -1; + return(-1); } + if (status != 0) { WLOG("receiving status not passed :(: %02x\n", status); } + if (status == 1) { get_sense(sg->usb_handle, sg->ep_rep, sg->ep_req); - return -1; + return(-1); } + if (received_tag != tag) { WLOG("received tag %d but expected %d\n", received_tag, tag); - //return -1; + // return -1; } + if (rx_length > 0 && real_transferred != rx_length) { - return -1; + return(-1); } - return 0; + + return(0); } -// TODO thinking, cleanup +// TODO: thinking, cleanup void stlink_stat(stlink_t *stl, char *txt) { - if (stl->q_len <= 0) - return; + if (stl->q_len <= 0) { return; } stlink_print_data(stl); @@ -406,7 +435,7 @@ int _stlink_sg_version(stlink_t *stl) { sl->cdb_cmd_blk[0] = STLINK_GET_VERSION; stl->q_len = 6; sl->q_addr = 0; - return stlink_q(stl); + return(stlink_q(stl)); } // Get stlink mode: @@ -418,23 +447,23 @@ int _stlink_sg_current_mode(stlink_t *stl) { sl->cdb_cmd_blk[0] = STLINK_GET_CURRENT_MODE; stl->q_len = 2; sl->q_addr = 0; - if (stlink_q(stl)) - return -1; - return stl->q_buf[0]; + if (stlink_q(stl)) { return(-1); } + + return(stl->q_buf[0]); } -// Exit the mass mode and enter the swd debug mode. +// exit the mass mode and enter the swd debug mode. int _stlink_sg_enter_swd_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_ENTER; sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_SWD; sl->q_len = 0; // >0 -> aboard - return stlink_q(sl); + return(stlink_q(sl)); } -// Exit the mass mode and enter the jtag debug mode. +// exit the mass mode and enter the jtag debug mode. // (jtag is disabled in the discovery's stlink firmware) int _stlink_sg_enter_jtag_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; @@ -443,7 +472,7 @@ int _stlink_sg_enter_jtag_mode(stlink_t *sl) { sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_ENTER; sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_JTAG; sl->q_len = 0; - return stlink_q(sl); + return(stlink_q(sl)); } // XXX kernel driver performs reset, the device temporally disappears @@ -455,7 +484,7 @@ int _stlink_sg_exit_dfu_mode(stlink_t *sl) { sg->cdb_cmd_blk[0] = STLINK_DFU_COMMAND; sg->cdb_cmd_blk[1] = STLINK_DFU_EXIT; sl->q_len = 0; // ?? - return stlink_q(sl); + return(stlink_q(sl)); /* [135121.844564] sd 19:0:0:0: [sdb] Unhandled error code [135121.844569] sd 19:0:0:0: [sdb] Result: hostbyte=DID_ERROR driverbyte=DRIVER_OK @@ -498,7 +527,7 @@ int _stlink_sg_exit_dfu_mode(stlink_t *sl) { [135131.678551] end_request: I/O error, dev sdb, sector 63872 ... [135131.853565] end_request: I/O error, dev sdb, sector 4096 - */ + */ } int _stlink_sg_core_id(stlink_t *sl) { @@ -509,73 +538,75 @@ int _stlink_sg_core_id(stlink_t *sl) { sl->q_len = 4; sg->q_addr = 0; ret = stlink_q(sl); - if (ret) - return ret; + + if (ret) { return(ret); } sl->core_id = read_uint32(sl->q_buf, 0); - return 0; + return(0); } -// Arm-core reset -> halted state. +// arm-core reset -> halted state. int _stlink_sg_reset(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_RESETSYS; sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } // Reset through AIRCR so NRST does not need to be connected if (stlink_write_debug32(sl, STLINK_REG_AIRCR, - STLINK_REG_AIRCR_VECTKEY | STLINK_REG_AIRCR_SYSRESETREQ)) - return -1; + STLINK_REG_AIRCR_VECTKEY | \ + STLINK_REG_AIRCR_SYSRESETREQ)) { + return(-1); + } stlink_stat(sl, "core reset"); - return 0; + return(0); } -// Arm-core reset -> halted state. +// arm-core reset -> halted state. int _stlink_sg_jtag_reset(stlink_t *sl, int value) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_JTAG_DRIVE_NRST; - sg->cdb_cmd_blk[2] = (value)?0:1; + sg->cdb_cmd_blk[2] = (value) ? 0 : 1; sl->q_len = 3; sg->q_addr = 2; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } stlink_stat(sl, "core reset"); - return 0; + return(0); } -// Arm-core status: halted or running. +// arm-core status: halted or running. int _stlink_sg_status(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_GETSTATUS; sl->q_len = 2; sg->q_addr = 0; - return stlink_q(sl); + return(stlink_q(sl)); } -// Force the core into the debug mode -> halted state. +// force the core into the debug mode -> halted state. int _stlink_sg_force_debug(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_FORCEDEBUG; sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } stlink_stat(sl, "force debug"); - return 0; + return(0); } -// Read all arm-core registers. +// read all arm-core registers. int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { struct stlink_libsg *sg = sl->backend_data; @@ -583,27 +614,28 @@ int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_READALLREGS; sl->q_len = 84; sg->q_addr = 0; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } stlink_print_data(sl); - // TODO - most of this should be re-extracted up.... + // TODO: most of this should be re-extracted up.... // 0-3 | 4-7 | ... | 60-63 | 64-67 | 68-71 | 72-75 | 76-79 | 80-83 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 for (int i = 0; i < 16; i++) { regp->r[i] = read_uint32(sl->q_buf, 4 * i); - if (sl->verbose > 1) - DLOG("r%2d = 0x%08x\n", i, regp->r[i]); + + if (sl->verbose > 1) { DLOG("r%2d = 0x%08x\n", i, regp->r[i]); } } + regp->xpsr = read_uint32(sl->q_buf, 64); regp->main_sp = read_uint32(sl->q_buf, 68); regp->process_sp = read_uint32(sl->q_buf, 72); regp->rw = read_uint32(sl->q_buf, 76); regp->rw2 = read_uint32(sl->q_buf, 80); - if (sl->verbose < 2) - return 0; + + if (sl->verbose < 2) { return(0); } DLOG("xpsr = 0x%08x\n", regp->xpsr); DLOG("main_sp = 0x%08x\n", regp->main_sp); @@ -611,10 +643,10 @@ int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("rw = 0x%08x\n", regp->rw); DLOG("rw2 = 0x%08x\n", regp->rw2); - return 0; + return(0); } -// Read an arm-core register, the index must be in the range 0..20. +// read an arm-core register, the index must be in the range 0..20. // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 @@ -625,8 +657,8 @@ int _stlink_sg_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { sg->cdb_cmd_blk[2] = r_idx; sl->q_len = 4; sg->q_addr = 0; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // 0-3 | 4-7 | ... | 60-63 | 64-67 | 68-71 | 72-75 | 76-79 | 80-83 @@ -647,19 +679,19 @@ int _stlink_sg_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { regp->process_sp = r; break; case 19: - regp->rw = r; //XXX ?(primask, basemask etc.) + regp->rw = r; // XXX ?(primask, basemask etc.) break; case 20: - regp->rw2 = r; //XXX ?(primask, basemask etc.) + regp->rw2 = r; // XXX ?(primask, basemask etc.) break; default: regp->r[r_idx] = r; } - return 0; + return(0); } -// Write an arm-core register. Index: +// write an arm-core register. Index: // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 @@ -673,16 +705,16 @@ int _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int idx) { write_uint32(sg->cdb_cmd_blk + 3, reg); sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } stlink_stat(sl, "write reg"); - return 0; + return(0); } -// Write a register of the debug module of the core. +// write a register of the debug module of the core. // XXX ?(atomic writes) -// TODO test +// TODO: test void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_write_dreg ***\n"); @@ -698,38 +730,37 @@ void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { stlink_stat(sl, "write debug reg"); } -// Force the core exit the debug mode. +// force the core exit the debug mode. int _stlink_sg_run(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_RUNCORE; sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } stlink_stat(sl, "run core"); - return 0; + return(0); } -// Step the arm-core. +// step the arm-core. int _stlink_sg_step(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_STEPCORE; sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } stlink_stat(sl, "step core"); - return 0; + return(0); } -// TODO test +// TODO: test and make delegate! // see Cortex-M3 Technical Reference Manual -// TODO make delegate! void stlink_set_hw_bp(stlink_t *sl, int fp_nr, uint32_t addr, int fp) { DLOG("\n*** stlink_set_hw_bp ***\n"); struct stlink_libsg *sg = sl->backend_data; @@ -747,8 +778,7 @@ void stlink_set_hw_bp(stlink_t *sl, int fp_nr, uint32_t addr, int fp) { stlink_stat(sl, "set flash breakpoint"); } -// TODO test -// TODO make delegate! +// TODO: test and make delegate! void stlink_clr_hw_bp(stlink_t *sl, int fp_nr) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_clr_hw_bp ***\n"); @@ -761,7 +791,7 @@ void stlink_clr_hw_bp(stlink_t *sl, int fp_nr) { stlink_stat(sl, "clear flash breakpoint"); } -// Read a "len" bytes to the sl->q_buf from the memory, max 6kB (6144 bytes) +// read a "len" bytes to the sl->q_buf from the memory, max 6kB (6144 bytes) int _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -778,14 +808,14 @@ int _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { // (broken residue issue) sl->q_len = len; sg->q_addr = addr; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } stlink_print_data(sl); - return 0; + return(0); } -// Write a "len" bytes from the sl->q_buf to the memory, max 64 Bytes. +// write a "len" bytes from the sl->q_buf to the memory, max 64 Bytes. int _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; int ret; @@ -799,21 +829,21 @@ int _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { // this sends the command... ret = send_usb_mass_storage_command(sg->usb_handle, - sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); - if (ret == -1) - return ret; + sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); + + if (ret == -1) { return(ret); } // This sends the data... ret = send_usb_data_only(sg->usb_handle, - sg->ep_req, sg->ep_rep, sl->q_buf, len); - if (ret == -1) - return ret; + sg->ep_req, sg->ep_rep, sl->q_buf, len); + + if (ret == -1) { return(ret); } stlink_print_data(sl); - return 0; + return(0); } -// Write a "len" bytes from the sl->q_buf to the memory, max Q_BUF_LEN bytes. +// write a "len" bytes from the sl->q_buf to the memory, max Q_BUF_LEN bytes. int _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; int ret; @@ -827,21 +857,21 @@ int _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { // this sends the command... ret = send_usb_mass_storage_command(sg->usb_handle, - sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); - if (ret == -1) - return ret; + sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); + + if (ret == -1) { return(ret); } // This sends the data... ret = send_usb_data_only(sg->usb_handle, - sg->ep_req, sg->ep_rep, sl->q_buf, len); - if (ret == -1) - return ret; + sg->ep_req, sg->ep_rep, sl->q_buf, len); + + if (ret == -1) { return(ret); } stlink_print_data(sl); - return 0; + return(0); } -// Write one DWORD data to memory +// write one DWORD data to memory int _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -850,10 +880,10 @@ int _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { write_uint32(sg->cdb_cmd_blk + 2, addr); write_uint32(sg->cdb_cmd_blk + 6, data); sl->q_len = 2; - return stlink_q(sl); + return(stlink_q(sl)); } -// Read one DWORD data from memory +// read one DWORD data from memory int _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -861,24 +891,24 @@ int _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { // 2-5: addr write_uint32(sg->cdb_cmd_blk + 2, addr); sl->q_len = 8; - if (stlink_q(sl)) - return -1; + + if (stlink_q(sl)) { return(-1); } *data = read_uint32(sl->q_buf, 4); - return 0; + return(0); } -// Exit the jtag or swd mode and enter the mass mode. +// exit the jtag or swd mode and enter the mass mode. int _stlink_sg_exit_debug_mode(stlink_t *stl) { if (stl) { struct stlink_libsg* sl = stl->backend_data; clear_cdb(sl); sl->cdb_cmd_blk[1] = STLINK_DEBUG_EXIT; stl->q_len = 0; // >0 -> aboard - return stlink_q(stl); + return(stlink_q(stl)); } - return 0; + return(0); } // 1) open a sg device, switch the stlink from dfu to mass mode @@ -906,35 +936,38 @@ static stlink_backend_t _stlink_sg_backend = { _stlink_sg_write_mem8, _stlink_sg_read_all_regs, _stlink_sg_read_reg, - NULL, /* read_all_unsupported_regs */ - NULL, /* read_unsupported_regs */ - NULL, /* write_unsupported_regs */ + NULL, // read_all_unsupported_regs + NULL, // read_unsupported_regs + NULL, // write_unsupported_regs _stlink_sg_write_reg, _stlink_sg_step, _stlink_sg_current_mode, _stlink_sg_force_debug, - NULL, /* target_voltage */ - NULL /* set_swdclk */ + NULL, // target_voltage + NULL // set_swdclk }; static stlink_t* stlink_open(const int verbose) { - stlink_t *sl = malloc(sizeof (stlink_t)); - struct stlink_libsg *slsg = malloc(sizeof (struct stlink_libsg)); + stlink_t *sl = malloc(sizeof(stlink_t)); + struct stlink_libsg *slsg = malloc(sizeof(struct stlink_libsg)); + if (sl == NULL || slsg == NULL) { WLOG("Couldn't malloc stlink and stlink_sg structures out of memory!\n"); - if (sl != NULL) - free(sl); - if (slsg != NULL) - free(slsg); - return NULL; + + if (sl != NULL) { free(sl); } + + if (slsg != NULL) { free(slsg); } + + return(NULL); } + memset(sl, 0, sizeof(stlink_t)); if (libusb_init(&(slsg->libusb_ctx))) { WLOG("failed to init libusb context, wrong version of libraries?\n"); free(sl); free(slsg); - return NULL; + return(NULL); } #if LIBUSB_API_VERSION < 0x01000106 @@ -944,32 +977,35 @@ static stlink_t* stlink_open(const int verbose) { #endif slsg->usb_handle = libusb_open_device_with_vid_pid(slsg->libusb_ctx, STLINK_USB_VID_ST, STLINK_USB_PID_STLINK); + if (slsg->usb_handle == NULL) { WLOG("Failed to find an stlink v1 by VID:PID\n"); libusb_close(slsg->usb_handle); libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return NULL; + return(NULL); } - // TODO - // Could read the interface config descriptor, and assert lots of the assumptions + // TODO: Could read the interface config descriptor, and assert lots of the assumptions // assumption: numInterfaces is always 1... if (libusb_kernel_driver_active(slsg->usb_handle, 0) == 1) { int r = libusb_detach_kernel_driver(slsg->usb_handle, 0); + if (r < 0) { WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); libusb_close(slsg->usb_handle); libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return NULL; + return(NULL); } + DLOG("Kernel driver was successfully detached\n"); } int config; + if (libusb_get_configuration(slsg->usb_handle, &config)) { /* this may fail for a previous configured device */ WLOG("libusb_get_configuration()\n"); @@ -977,7 +1013,7 @@ static stlink_t* stlink_open(const int verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return NULL; + return(NULL); } @@ -985,6 +1021,7 @@ static stlink_t* stlink_open(const int verbose) { if (config != 1) { WLOG("Your stlink got into a real weird configuration, trying to fix it!\n"); DLOG("setting new configuration (%d -> 1)\n", config); + if (libusb_set_configuration(slsg->usb_handle, 1)) { /* this may fail for a previous configured device */ WLOG("libusb_set_configuration() failed\n"); @@ -992,7 +1029,7 @@ static stlink_t* stlink_open(const int verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return NULL; + return(NULL); } } @@ -1002,7 +1039,7 @@ static stlink_t* stlink_open(const int verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return NULL; + return(NULL); } // assumption: endpoint config is fixed mang. really. @@ -1018,31 +1055,34 @@ static stlink_t* stlink_open(const int verbose) { sl->core_stat = TARGET_UNKNOWN; slsg->q_addr = 0; - return sl; + return(sl); } stlink_t* stlink_v1_open_inner(const int verbose) { ugly_init(verbose); stlink_t *sl = stlink_open(verbose); + if (sl == NULL) { ELOG("Could not open stlink device\n"); - return NULL; + return(NULL); } stlink_version(sl); + if ((sl->version.st_vid != STLINK_USB_VID_ST) || (sl->version.stlink_pid != STLINK_USB_PID_STLINK)) { ELOG("WTF? successfully opened, but unable to read version details. BROKEN!\n"); - return NULL; + return(NULL); } DLOG("Reading current mode...\n"); + switch (stlink_current_mode(sl)) { case STLINK_DEV_MASS_MODE: - return sl; + return(sl); case STLINK_DEV_DEBUG_MODE: // TODO go to mass? - return sl; + return(sl); default: ILOG("Current mode unusable, trying to get back to a useful state...\n"); break; @@ -1053,26 +1093,27 @@ stlink_t* stlink_v1_open_inner(const int verbose) { // re-query device info (and retest) stlink_version(sl); + if ((sl->version.st_vid != STLINK_USB_VID_ST) || (sl->version.stlink_pid != STLINK_USB_PID_STLINK)) { ELOG("WTF? successfully opened, but unable to read version details. BROKEN!\n"); - return NULL; + return(NULL); } - return sl; + return(sl); } stlink_t* stlink_v1_open(const int verbose, int reset) { stlink_t *sl = stlink_v1_open_inner(verbose); - if (sl == NULL) - return NULL; + + if (sl == NULL) { return(NULL); } // by now, it _must_ be fully open and in a useful mode.... stlink_enter_swd_mode(sl); - /* Now we are ready to read the parameters */ - if (reset) { - stlink_reset(sl); - } + + // now we are ready to read the parameters + if (reset) { stlink_reset(sl); } + stlink_load_device_params(sl); ILOG("Successfully opened a stlink v1 debugger\n"); - return sl; + return(sl); } diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index 811b339c7..f34b2e122 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -1,8 +1,6 @@ /* * File: sg.h * Author: karl - * - * Created on October 1, 2011, 11:29 PM */ #ifndef STLINK_SG_H @@ -15,31 +13,28 @@ extern "C" { #endif - // device access -#define RDWR 0 -#define RO 1 -#define SG_TIMEOUT_SEC 1 // actually 1 is about 2 sec -#define SG_TIMEOUT_MSEC 3 * 1000 - // Each CDB can be a total of 6, 10, 12, or 16 bytes, later version - // of the SCSI standard also allow for variable-length CDBs (min. CDB is 6). - // the stlink needs max. 10 bytes. -#define CDB_6 6 -#define CDB_10 10 -#define CDB_12 12 -#define CDB_16 16 +/* Device access */ +#define RDWR 0 +#define RO 1 +#define SG_TIMEOUT_SEC 1 // actually 1 is about 2 sec +#define SG_TIMEOUT_MSEC 3 * 1000 -#define CDB_SL 10 +// Each CDB can be a total of 6, 10, 12, or 16 bytes, later version of the SCSI standard +// also allow for variable-length CDBs (min. CDB is 6). The stlink needs max. 10 bytes. +#define CDB_6 6 +#define CDB_10 10 +#define CDB_12 12 +#define CDB_16 16 - // Query data flow direction. -#define Q_DATA_OUT 0 -#define Q_DATA_IN 1 - - // The SCSI Request Sense command is used to obtain sense data - // (error information) from a target device. - // http://en.wikipedia.org/wiki/SCSI_Request_Sense_Command -#define SENSE_BUF_LEN 32 +#define CDB_SL 10 +/* Query data flow direction */ +#define Q_DATA_OUT 0 +#define Q_DATA_IN 1 +// The SCSI Request Sense command is used to obtain sense data (error information) from +// a target device. (http://en.wikipedia.org/wiki/SCSI_Request_Sense_Command) +#define SENSE_BUF_LEN 32 struct stlink_libsg { libusb_context* libusb_ctx; @@ -65,8 +60,8 @@ struct stlink_libsg { stlink_t* stlink_v1_open(const int verbose, int reset); -#ifdef __cplusplus +#ifdef __cplusplus } #endif -#endif /* STLINK_SG_H */ +#endif // STLINK_SG_H diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index c22f2fe5e..f9b4775f3 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -19,10 +19,10 @@ #include #include "usb.h" -enum SCSI_Generic_Direction {SG_DXFER_TO_DEV=0, SG_DXFER_FROM_DEV=0x80}; +enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; static inline uint32_t le_to_h_u32(const uint8_t* buf) { - return (uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24); + return((uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24)); } static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, uint32_t khz) { @@ -33,15 +33,18 @@ static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, u bool match = true; for (i = 0; i < map_size; i++) { - if (!map[i]) continue; + if (!map[i]) { continue; } + last_valid_speed = i; + if (khz == map[i]) { speed_index = i; break; } else { int current_diff = khz - map[i]; - // Get abs value for comparison + // get abs value for comparison current_diff = (current_diff > 0) ? current_diff : -current_diff; + if ((current_diff < speed_diff) && khz >= map[i]) { speed_diff = current_diff; speed_index = i; @@ -50,72 +53,80 @@ static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, u } if (speed_index == -1) { - // This will only be here if we cannot match the slow speed. Use the slowest speed we support. + // This will only be here if we cannot match the slow speed. + // Use the slowest speed we support. speed_index = last_valid_speed; match = false; } else if (i == map_size) { match = false; } + if (!match) { ILOG("Unable to match requested speed %d kHz, using %d kHz\n", khz, map[speed_index]); } - return speed_index; + return(speed_index); } void _stlink_usb_close(stlink_t* sl) { - if (!sl) return; + if (!sl) { return; } struct stlink_libusb * const handle = sl->backend_data; - // Maybe we couldn't even get the usb device? + + // maybe we couldn't even get the usb device? if (handle != NULL) { - if (handle->usb_handle != NULL) libusb_close(handle->usb_handle); + if (handle->usb_handle != NULL) { libusb_close(handle->usb_handle); } + libusb_exit(handle->libusb_ctx); free(handle); } } ssize_t send_recv(struct stlink_libusb* handle, int terminate, - unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, size_t rxsize) { - /* Note: txbuf and rxbuf can point to the same area */ + unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, size_t rxsize) { + // Note: txbuf and rxbuf can point to the same area int res = 0; int t; - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int) txsize, &res, 3000); + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int)txsize, &res, 3000); + if (t) { printf("[!] send_recv send request failed: %s\n", libusb_error_name(t)); - return -1; + return(-1); } else if ((size_t)res != txsize) { printf("[!] send_recv send request wrote %u bytes (instead of %u).\n", - (unsigned int)res, (unsigned int)txsize); + (unsigned int)res, (unsigned int)txsize); } if (rxsize != 0) { - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int) rxsize, &res, 3000); + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int)rxsize, &res, 3000); + if (t) { printf("[!] send_recv read reply failed: %s\n", libusb_error_name(t)); - return -1; + return(-1); } } if ((handle->protocoll == 1) && terminate) { - // Read the SG reply + // read the SG reply unsigned char sg_buf[13]; t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); + if (t) { printf("[!] send_recv read storage failed: %s\n", libusb_error_name(t)); - return -1; + return(-1); } + // The STLink doesn't seem to evaluate the sequence number. handle->sg_transfer_idx++; } - return res; + return(res); } static inline int send_only(struct stlink_libusb* handle, int terminate, - unsigned char* txbuf, size_t txsize) { - return (int) send_recv(handle, terminate, txbuf, txsize, NULL, 0); + unsigned char* txbuf, size_t txsize) { + return((int)send_recv(handle, terminate, txbuf, txsize, NULL, 0)); } @@ -123,7 +134,8 @@ static int fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; int i = 0; - memset(cmd, 0, sizeof (sl->c_buf)); + memset(cmd, 0, sizeof(sl->c_buf)); + if (slu->protocoll == 1) { cmd[i++] = 'U'; cmd[i++] = 'S'; @@ -133,10 +145,11 @@ static int fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t write_uint32(&cmd[i + 4], len); i += 8; cmd[i++] = (dir == SG_DXFER_FROM_DEV) ? 0x80 : 0; - cmd[i++] = 0; // Logical unit - cmd[i++] = 0xa; // Command length + cmd[i++] = 0; // logical unit + cmd[i++] = 0xa; // command length } - return i; + + return(i); } int _stlink_usb_version(stlink_t *sl) { @@ -150,9 +163,10 @@ int _stlink_usb_version(stlink_t *sl) { cmd[i++] = STLINK_GET_VERSION; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_GET_VERSION\n"); - return (int) size; + return((int)size); } /* STLINK-V3 requires a specific command */ @@ -162,13 +176,14 @@ int _stlink_usb_version(stlink_t *sl) { cmd[i++] = STLINK_APIV3_GET_VERSION_EX; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size != (ssize_t)rep_len) { printf("[!] send_recv STLINK_APIV3_GET_VERSION_EX\n"); - return (int) size; + return((int)size); } } - return 0; + return(0); } int32_t _stlink_usb_target_voltage(stlink_t *sl) { @@ -184,19 +199,20 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { cmd[i++] = STLINK_GET_TARGET_VOLTAGE; size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_GET_TARGET_VOLTAGE\n"); - return -1; + return(-1); } else if (size != 8) { printf("[!] wrong length STLINK_GET_TARGET_VOLTAGE\n"); - return -1; + return(-1); } factor = (rdata[3] << 24) | (rdata[2] << 16) | (rdata[1] << 8) | (rdata[0] << 0); reading = (rdata[7] << 24) | (rdata[6] << 16) | (rdata[5] << 8) | (rdata[4] << 0); voltage = 2400 * reading / factor; - return voltage; + return(voltage); } int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { @@ -211,13 +227,15 @@ int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { cmd[i++] = STLINK_JTAG_READDEBUG_32BIT; write_uint32(&cmd[i], addr); size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_JTAG_READDEBUG_32BIT\n"); - return (int) size; + return((int)size); } + *data = read_uint32(rdata, 4); - return 0; + return(0); } int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { @@ -233,16 +251,17 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { write_uint32(&cmd[i], addr); write_uint32(&cmd[i + 4], data); size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_JTAG_WRITEDEBUG_32BIT\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } int _stlink_usb_get_rw_status(stlink_t *sl) { - if (sl->version.jtag_api == STLINK_JTAG_API_V1) return -1; + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return(-1); } unsigned char* const rdata = sl->q_buf; struct stlink_libusb * const slu = sl->backend_data; @@ -252,6 +271,7 @@ int _stlink_usb_get_rw_status(stlink_t *sl) { i = fill_command(sl, SG_DXFER_FROM_DEV, 12); cmd[i++] = STLINK_DEBUG_COMMAND; + if (sl->version.flags & STLINK_F_HAS_GETLASTRWSTATUS2) { cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS2; ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 12); @@ -259,9 +279,10 @@ int _stlink_usb_get_rw_status(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS; ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2); } - if (ret < 0) return -1; - return 0; + if (ret < 0) { return(-1); } + + return(0); } int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -276,11 +297,14 @@ int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); ret = send_only(slu, 0, cmd, slu->cmd_len); - if (ret == -1) return ret; + + if (ret == -1) { return(ret); } + ret = send_only(slu, 0, data, len); - if (ret == -1) return ret; - return _stlink_usb_get_rw_status(sl); + if (ret == -1) { return(ret); } + + return(_stlink_usb_get_rw_status(sl)); } int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -295,11 +319,14 @@ int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); ret = send_only(slu, 0, cmd, slu->cmd_len); - if (ret == -1) return ret; + + if (ret == -1) { return(ret); } + ret = send_only(slu, 1, data, len); - if (ret == -1) return ret; - return 0; + if (ret == -1) { return(ret); } + + return(0); } @@ -313,12 +340,13 @@ int _stlink_usb_current_mode(stlink_t * sl) { cmd[i++] = STLINK_GET_CURRENT_MODE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_GET_CURRENT_MODE\n"); - return -1; + return(-1); } - return sl->q_buf[0]; + return(sl->q_buf[0]); } int _stlink_usb_core_id(stlink_t * sl) { @@ -330,15 +358,18 @@ int _stlink_usb_core_id(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { cmd[i++] = STLINK_DEBUG_READCOREID; } else { cmd[i++] = STLINK_DEBUG_APIV2_READ_IDCODES; } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_READCOREID\n"); - return -1; + return(-1); } if (sl->version.jtag_api == STLINK_JTAG_API_V1) { @@ -346,16 +377,18 @@ int _stlink_usb_core_id(stlink_t * sl) { } else { sl->core_id = read_uint32(data, 4); } - return 0; + + return(0); } -int _stlink_usb_status_v2(stlink_t *sl) -{ + +int _stlink_usb_status_v2(stlink_t *sl) { int result; uint32_t status = 0; result = _stlink_usb_read_debug32(sl, DCB_DHCSR, &status); DLOG("core status: %08X\n", status); - if (result != 0) { + + if (result != 0) { sl->core_stat = TARGET_UNKNOWN; } else { if (status & S_HALT) { @@ -367,11 +400,11 @@ int _stlink_usb_status_v2(stlink_t *sl) } } - return result; + return(result); } int _stlink_usb_status(stlink_t * sl) { - if (sl->version.jtag_api != STLINK_JTAG_API_V1) return _stlink_usb_status_v2(sl); + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { return(_stlink_usb_status_v2(sl)); } struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; @@ -383,21 +416,25 @@ int _stlink_usb_status(stlink_t * sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_GETSTATUS; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_GETSTATUS\n"); - return (int) size; + return((int)size); } - sl->q_len = (int) size; + + sl->q_len = (int)size; + if (sl->q_len > 1) { - if (sl->q_buf[0] == STLINK_CORE_RUNNING) + if (sl->q_buf[0] == STLINK_CORE_RUNNING) { sl->core_stat = TARGET_RUNNING; - else if (sl->q_buf[0] == STLINK_CORE_HALTED) + } else if (sl->q_buf[0] == STLINK_CORE_HALTED) { sl->core_stat = TARGET_HALTED; - else + } else { sl->core_stat = TARGET_UNKNOWN; + } } - return 0; + return(0); } int _stlink_usb_force_debug(stlink_t *sl) { @@ -411,12 +448,13 @@ int _stlink_usb_force_debug(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_FORCEDEBUG; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_FORCEDEBUG\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } int _stlink_usb_enter_swd_mode(stlink_t * sl) { @@ -428,7 +466,7 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - // Select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). + // select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). cmd[i++] = sl->version.jtag_api == STLINK_JTAG_API_V1 ? STLINK_DEBUG_APIV1_ENTER : STLINK_DEBUG_APIV2_ENTER; cmd[i++] = STLINK_DEBUG_ENTER_SWD; @@ -437,12 +475,13 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { } else { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); } + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_ENTER\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } int _stlink_usb_exit_dfu_mode(stlink_t* sl) { @@ -454,12 +493,13 @@ int _stlink_usb_exit_dfu_mode(stlink_t* sl) { cmd[i++] = STLINK_DFU_COMMAND; cmd[i++] = STLINK_DFU_EXIT; size = send_only(slu, 1, cmd, slu->cmd_len); + if (size == -1) { printf("[!] send_recv STLINK_DFU_EXIT\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } @@ -472,6 +512,7 @@ int _stlink_usb_reset(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { cmd[i++] = STLINK_DEBUG_APIV1_RESETSYS; } else { @@ -479,14 +520,15 @@ int _stlink_usb_reset(stlink_t * sl) { } size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_RESETSYS\n"); - return (int) size; + return((int)size); } - // Reset through AIRCR so that NRST does not need to be connected. - return stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | - STLINK_REG_AIRCR_SYSRESETREQ); + // reset through AIRCR so that NRST does not need to be connected + return(stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ)); } int _stlink_usb_jtag_reset(stlink_t * sl, int value) { @@ -501,12 +543,13 @@ int _stlink_usb_jtag_reset(stlink_t * sl, int value) { cmd[i++] = STLINK_JTAG_DRIVE_NRST; cmd[i++] = value; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_JTAG_DRIVE_NRST\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } @@ -521,12 +564,13 @@ int _stlink_usb_step(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_STEPCORE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_STEPCORE\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } /** @@ -539,8 +583,8 @@ int _stlink_usb_run(stlink_t* sl) { int res; if (sl->version.jtag_api != STLINK_JTAG_API_V1) { - res = _stlink_usb_write_debug32(sl, DCB_DHCSR, DBGKEY|C_DEBUGEN); - return res; + res = _stlink_usb_write_debug32(sl, DCB_DHCSR, DBGKEY | C_DEBUGEN); + return(res); } @@ -553,15 +597,15 @@ int _stlink_usb_run(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_RUNCORE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_RUNCORE\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } - int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; @@ -579,12 +623,13 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { cmd[i++] = clk_divisor & 0xFF; cmd[i++] = (clk_divisor >> 8) & 0xFF; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size == -1) { printf("[!] send_recv STLINK_DEBUG_APIV2_SWD_SET_FREQ\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } else if (sl->version.stlink_v == 3) { int speed_index; uint32_t map[STLINK_V3_MAX_FREQ_NB]; @@ -594,14 +639,17 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { cmd[i++] = STLINK_APIV3_GET_COM_FREQ; cmd[i++] = 0; // SWD mode size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52); + if (size == -1) { printf("[!] send_recv STLINK_APIV3_GET_COM_FREQ\n"); - return (int) size; + return((int)size); } int speeds_size = data[8]; - if (speeds_size > STLINK_V3_MAX_FREQ_NB) speeds_size = STLINK_V3_MAX_FREQ_NB; + if (speeds_size > STLINK_V3_MAX_FREQ_NB) { + speeds_size = STLINK_V3_MAX_FREQ_NB; + } for (i = 0; i < speeds_size; i++) map[i] = le_to_h_u32(&data[12 + 4 * i]); @@ -622,14 +670,16 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { cmd[i++] = (uint8_t)((map[speed_index] >> 24) & 0xFF); size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8); + if (size == -1) { printf("[!] send_recv STLINK_APIV3_SET_COM_FREQ\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } - return -1; + + return(-1); } int _stlink_usb_exit_debug_mode(stlink_t *sl) { @@ -642,12 +692,13 @@ int _stlink_usb_exit_debug_mode(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_EXIT; size = send_only(slu, 1, cmd, slu->cmd_len); + if (size == -1) { printf("[!] send_only STLINK_DEBUG_EXIT\n"); - return (int) size; + return((int)size); } - return 0; + return(0); } int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -665,13 +716,13 @@ int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { if (size == -1) { printf("[!] send_recv STLINK_DEBUG_READMEM_32BIT\n"); - return (int) size; + return((int)size); } - sl->q_len = (int) size; + sl->q_len = (int)size; stlink_print_data(sl); - return 0; + return(0); } int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { @@ -694,23 +745,24 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { if (size == -1) { printf("[!] send_recv STLINK_DEBUG_READALLREGS\n"); - return (int) size; + return((int)size); } /* V1: regs data from offset 0 */ /* V2: status at offset 0, regs data from offset 4 */ int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; - sl->q_len = (int) size; + sl->q_len = (int)size; stlink_print_data(sl); - for(i=reg_offset; i<16; i++) regp->r[i]= read_uint32(sl->q_buf, i*4); + for (i = reg_offset; i < 16; i++) regp->r[i] = read_uint32(sl->q_buf, i * 4); + regp->xpsr = read_uint32(sl->q_buf, reg_offset + 64); regp->main_sp = read_uint32(sl->q_buf, reg_offset + 68); regp->process_sp = read_uint32(sl->q_buf, reg_offset + 72); regp->rw = read_uint32(sl->q_buf, reg_offset + 76); regp->rw2 = read_uint32(sl->q_buf, reg_offset + 80); - if (sl->verbose < 2) return 0; + if (sl->verbose < 2) { return(0); } DLOG("xpsr = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 64)); DLOG("main_sp = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 68)); @@ -718,7 +770,7 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("rw = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 76)); DLOG("rw2 = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 80)); - return 0; + return(0); } int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { @@ -739,15 +791,15 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { cmd[i++] = STLINK_DEBUG_APIV2_READREG; } - cmd[i++] = (uint8_t) r_idx; + cmd[i++] = (uint8_t)r_idx; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv STLINK_DEBUG_READREG\n"); - return (int) size; + return((int)size); } - sl->q_len = (int) size; + sl->q_len = (int)size; stlink_print_data(sl); r = read_uint32(sl->q_buf, reg_offset); DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); @@ -772,7 +824,7 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { regp->r[r_idx] = r; } - return 0; + return(0); } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ @@ -780,89 +832,96 @@ int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg uint32_t r; int ret; - sl->q_buf[0] = (unsigned char) r_idx; + sl->q_buf[0] = (unsigned char)r_idx; + for (int i = 1; i < 4; i++) sl->q_buf[i] = 0; ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); - if (ret == -1) return ret; + + if (ret == -1) { return(ret); } ret = _stlink_usb_read_mem32(sl, STLINK_REG_DCRDR, 4); - if (ret == -1) return ret; + + if (ret == -1) { return(ret); } r = read_uint32(sl->q_buf, 0); DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); switch (r_idx) { - case 0x14: - regp->primask = (uint8_t) (r & 0xFF); - regp->basepri = (uint8_t) ((r>>8) & 0xFF); - regp->faultmask = (uint8_t) ((r>>16) & 0xFF); - regp->control = (uint8_t) ((r>>24) & 0xFF); - break; - case 0x21: - regp->fpscr = r; - break; - default: - regp->s[r_idx - 0x40] = r; - break; + case 0x14: + regp->primask = (uint8_t)(r & 0xFF); + regp->basepri = (uint8_t)((r >> 8) & 0xFF); + regp->faultmask = (uint8_t)((r >> 16) & 0xFF); + regp->control = (uint8_t)((r >> 24) & 0xFF); + break; + case 0x21: + regp->fpscr = r; + break; + default: + regp->s[r_idx - 0x40] = r; + break; } - return 0; + return(0); } int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { int ret; ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); - if (ret == -1) return ret; + + if (ret == -1) { return(ret); } ret = _stlink_usb_read_unsupported_reg(sl, 0x21, regp); - if (ret == -1) return ret; + + if (ret == -1) { return(ret); } for (int i = 0; i < 32; i++) { - ret = _stlink_usb_read_unsupported_reg(sl, 0x40+i, regp); - if (ret == -1) return ret; + ret = _stlink_usb_read_unsupported_reg(sl, 0x40 + i, regp); + + if (ret == -1) { return(ret); } } - return 0; + return(0); } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct stlink_reg *regp) { int ret; - if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ + if (r_idx >= 0x1C && r_idx <= 0x1F) { // primask, basepri, faultmask, or control /* These are held in the same register */ ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); - if (ret == -1) return ret; - val = (uint8_t) (val>>24); + if (ret == -1) { return(ret); } + + val = (uint8_t)(val >> 24); switch (r_idx) { - case 0x1C: /* control */ - val = (((uint32_t) val) << 24) | - (((uint32_t) regp->faultmask) << 16) | - (((uint32_t) regp->basepri) << 8) | - ((uint32_t) regp->primask); - break; - case 0x1D: /* faultmask */ - val = (((uint32_t) regp->control) << 24) | - (((uint32_t) val) << 16) | - (((uint32_t) regp->basepri) << 8) | - ((uint32_t) regp->primask); - break; - case 0x1E: /* basepri */ - val = (((uint32_t) regp->control) << 24) | - (((uint32_t) regp->faultmask) << 16) | - (((uint32_t) val) << 8) | - ((uint32_t) regp->primask); - break; - case 0x1F: /* primask */ - val = (((uint32_t) regp->control) << 24) | - (((uint32_t) regp->faultmask) << 16) | - (((uint32_t) regp->basepri) << 8) | - ((uint32_t) val); - break; + case 0x1C: /* control */ + val = (((uint32_t)val) << 24) | + (((uint32_t)regp->faultmask) << 16) | + (((uint32_t)regp->basepri) << 8) | + ((uint32_t)regp->primask); + break; + case 0x1D: /* faultmask */ + val = (((uint32_t)regp->control) << 24) | + (((uint32_t)val) << 16) | + (((uint32_t)regp->basepri) << 8) | + ((uint32_t)regp->primask); + break; + case 0x1E: /* basepri */ + val = (((uint32_t)regp->control) << 24) | + (((uint32_t)regp->faultmask) << 16) | + (((uint32_t)val) << 8) | + ((uint32_t)regp->primask); + break; + case 0x1F: /* primask */ + val = (((uint32_t)regp->control) << 24) | + (((uint32_t)regp->faultmask) << 16) | + (((uint32_t)regp->basepri) << 8) | + ((uint32_t)val); + break; } r_idx = 0x14; @@ -871,14 +930,15 @@ int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, str write_uint32(sl->q_buf, val); ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRDR, 4); - if (ret == -1) return ret; - sl->q_buf[0] = (unsigned char) r_idx; + if (ret == -1) { return(ret); } + + sl->q_buf[0] = (unsigned char)r_idx; sl->q_buf[1] = 0; sl->q_buf[2] = 0x01; sl->q_buf[3] = 0; - return _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); + return(_stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4)); } int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { @@ -903,19 +963,20 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { if (size == -1) { printf("[!] send_recv STLINK_DEBUG_WRITEREG\n"); - return (int) size; + return((int)size); } - sl->q_len = (int) size; + + sl->q_len = (int)size; stlink_print_data(sl); - return 0; + return(0); } static stlink_backend_t _stlink_usb_backend = { _stlink_usb_close, _stlink_usb_exit_debug_mode, _stlink_usb_enter_swd_mode, - NULL, // no enter_jtag_mode here... + NULL, // don't enter_jtag_mode here... _stlink_usb_exit_dfu_mode, _stlink_usb_core_id, _stlink_usb_reset, @@ -947,17 +1008,19 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL int ret = -1; int config; - sl = calloc(1, sizeof (stlink_t)); - slu = calloc(1, sizeof (struct stlink_libusb)); + sl = calloc(1, sizeof(stlink_t)); + slu = calloc(1, sizeof(struct stlink_libusb)); - if (sl == NULL) goto on_malloc_error; - if (slu == NULL) goto on_malloc_error; + if (sl == NULL) { goto on_malloc_error; } + + if (slu == NULL) { goto on_malloc_error; } ugly_init(verbose); sl->backend = &_stlink_usb_backend; sl->backend_data = slu; sl->core_stat = TARGET_UNKNOWN; + if (libusb_init(&(slu->libusb_ctx))) { WLOG("failed to init libusb context, wrong version of libraries?\n"); goto on_error; @@ -970,53 +1033,58 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL #endif libusb_device **list; - /* @TODO: We should use ssize_t and use it as a counter if > 0. - * As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) - */ - int cnt = (int) libusb_get_device_list(slu->libusb_ctx, &list); + // TODO: We should use ssize_t and use it as a counter if > 0. + // As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) + int cnt = (int)libusb_get_device_list(slu->libusb_ctx, &list); struct libusb_device_descriptor desc; int devBus = 0; int devAddr = 0; - /* @TODO: Reading a environment variable in a usb open function is not very nice, this should be refactored - * and moved into the CLI tools, and instead of giving USB_BUS:USB_ADDR a real stlink serial string should - * be passed to this function. Probably people are using this but this is very odd because as programmer - * can change to multiple busses and it is better to detect them based on serial. - */ + // TODO: Reading a environment variable in a usb open function is not very nice, this should + // be refactored and moved into the CLI tools, and instead of giving USB_BUS:USB_ADDR a real + // stlink serial string should be passed to this function. Probably people are using this + // but this is very odd because as programmer can change to multiple busses and it is better + // to detect them based on serial. char *device = getenv("STLINK_DEVICE"); + if (device) { - char *c = strchr(device,':'); + char *c = strchr(device, ':'); + if (c == NULL) { WLOG("STLINK_DEVICE must be : format\n"); goto on_error; } + devBus = atoi(device); *c++ = 0; devAddr = atoi(c); - ILOG("bus %03d dev %03d\n",devBus, devAddr); + ILOG("bus %03d dev %03d\n", devBus, devAddr); } while (cnt--) { struct libusb_device_handle *handle; libusb_get_device_descriptor(list[cnt], &desc); - if (desc.idVendor != STLINK_USB_VID_ST) continue; + + if (desc.idVendor != STLINK_USB_VID_ST) { continue; } if (devBus && devAddr) { - if ((libusb_get_bus_number(list[cnt]) != devBus) || (libusb_get_device_address(list[cnt]) != devAddr)) { + if ((libusb_get_bus_number(list[cnt]) != devBus) || + (libusb_get_device_address(list[cnt]) != devAddr)) { continue; } } ret = libusb_open(list[cnt], &handle); - if (ret) continue; // could not open device + + if (ret) { continue; } // could not open device sl->serial_size = libusb_get_string_descriptor_ascii( - handle, desc.iSerialNumber, (unsigned char *)sl->serial, sizeof(sl->serial)); + handle, desc.iSerialNumber, (unsigned char *)sl->serial, sizeof(sl->serial)); libusb_close(handle); - if (sl->serial_size < 0) continue; // could not read serial + if (sl->serial_size < 0) { continue; } // could not read serial // if no serial provided, or if serial match device, fixup version and protocol if (((serial == NULL) || (*serial == 0)) || (memcmp(serial, &sl->serial, sl->serial_size) == 0)) { @@ -1028,18 +1096,23 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL } else if (STLINK_V3_USB_PID(desc.idProduct)) { sl->version.stlink_v = 3; } + break; } } if (cnt < 0) { - WLOG ("Couldn't find %s ST-Link devices\n", (devBus && devAddr) ? "matched":"any"); + WLOG ("Couldn't find %s ST-Link devices\n", (devBus && devAddr) ? "matched" : "any"); goto on_error; } else { ret = libusb_open(list[cnt], &slu->usb_handle); + if (ret != 0) { - WLOG("Error %d (%s) opening ST-Link v%d device %03d:%03d\n", ret, strerror (errno), - sl->version.stlink_v, libusb_get_bus_number(list[cnt]), libusb_get_device_address(list[cnt])); + WLOG("Error %d (%s) opening ST-Link v%d device %03d:%03d\n", ret, + strerror(errno), + sl->version.stlink_v, + libusb_get_bus_number(list[cnt]), + libusb_get_device_address(list[cnt])); libusb_free_device_list(list, 1); goto on_error; } @@ -1049,6 +1122,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { ret = libusb_detach_kernel_driver(slu->usb_handle, 0); + if (ret < 0) { WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-ret)); goto on_libusb_error; @@ -1056,15 +1130,16 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL } if (libusb_get_configuration(slu->usb_handle, &config)) { - /* this may fail for a previous configured device */ + // this may fail for a previous configured device WLOG("libusb_get_configuration()\n"); goto on_libusb_error; } if (config != 1) { printf("setting new configuration (%d -> 1)\n", config); + if (libusb_set_configuration(slu->usb_handle, 1)) { - /* this may fail for a previous configured device */ + // this may fail for a previous configured device WLOG("libusb_set_configuration() failed\n"); goto on_libusb_error; } @@ -1075,8 +1150,9 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL goto on_libusb_error; } - // TODO - could use the scanning techniq from stm8 code here... + // TODO: Could use the scanning technique from STM8 code here... slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; + if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO || desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO || desc.idProduct == STLINK_USB_PID_STLINK_V2_1 || @@ -1090,17 +1166,14 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL } slu->sg_transfer_idx = 0; - slu->cmd_len = (slu->protocoll == 1) ? STLINK_SG_SIZE: STLINK_CMD_SIZE; + slu->cmd_len = (slu->protocoll == 1) ? STLINK_SG_SIZE : STLINK_CMD_SIZE; - // Initialize stlink version (sl->version) - stlink_version(sl); - - // Initialize stlink version (sl->version) + // initialize stlink version (sl->version) stlink_version(sl); if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { - // This seems to work, and is unnecessary information for the user. - // Demoted to debug -- REW + // this seems to work, and is unnecessary information for the user. + // demoted to debug -- REW DLOG("-- exit_dfu_mode\n"); stlink_exit_dfu_mode(sl); } @@ -1108,78 +1181,86 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL sl->freq = freq; // set the speed before entering the mode as the chip discovery phase // should be done at this speed too - // Set the stlink clock speed (default is 1800kHz) + // set the stlink clock speed (default is 1800kHz) DLOG("JTAG/SWD freq set to %d\n", freq); + switch (freq) { - case 5: - stlink_set_swdclk(sl, STLINK_SWDCLK_5KHZ_DIVISOR); - break; - case 15: - stlink_set_swdclk(sl, STLINK_SWDCLK_15KHZ_DIVISOR); - break; - case 25: - stlink_set_swdclk(sl, STLINK_SWDCLK_25KHZ_DIVISOR); - break; - case 50: - stlink_set_swdclk(sl, STLINK_SWDCLK_50KHZ_DIVISOR); - break; - case 100: - stlink_set_swdclk(sl, STLINK_SWDCLK_100KHZ_DIVISOR); - break; - case 125: - stlink_set_swdclk(sl, STLINK_SWDCLK_125KHZ_DIVISOR); - break; - case 240: - stlink_set_swdclk(sl, STLINK_SWDCLK_240KHZ_DIVISOR); - break; - case 480: - stlink_set_swdclk(sl, STLINK_SWDCLK_480KHZ_DIVISOR); - break; - case 950: - stlink_set_swdclk(sl, STLINK_SWDCLK_950KHZ_DIVISOR); - break; - case 1200: - stlink_set_swdclk(sl, STLINK_SWDCLK_1P2MHZ_DIVISOR); - break; - case 0: case 1800: - stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); - break; - case 4000: - stlink_set_swdclk(sl, STLINK_SWDCLK_4MHZ_DIVISOR); - break; + case 5: + stlink_set_swdclk(sl, STLINK_SWDCLK_5KHZ_DIVISOR); + break; + case 15: + stlink_set_swdclk(sl, STLINK_SWDCLK_15KHZ_DIVISOR); + break; + case 25: + stlink_set_swdclk(sl, STLINK_SWDCLK_25KHZ_DIVISOR); + break; + case 50: + stlink_set_swdclk(sl, STLINK_SWDCLK_50KHZ_DIVISOR); + break; + case 100: + stlink_set_swdclk(sl, STLINK_SWDCLK_100KHZ_DIVISOR); + break; + case 125: + stlink_set_swdclk(sl, STLINK_SWDCLK_125KHZ_DIVISOR); + break; + case 240: + stlink_set_swdclk(sl, STLINK_SWDCLK_240KHZ_DIVISOR); + break; + case 480: + stlink_set_swdclk(sl, STLINK_SWDCLK_480KHZ_DIVISOR); + break; + case 950: + stlink_set_swdclk(sl, STLINK_SWDCLK_950KHZ_DIVISOR); + break; + case 1200: + stlink_set_swdclk(sl, STLINK_SWDCLK_1P2MHZ_DIVISOR); + break; + case 0: case 1800: + stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); + break; + case 4000: + stlink_set_swdclk(sl, STLINK_SWDCLK_4MHZ_DIVISOR); + break; } if (reset == 2) { - stlink_jtag_reset(sl,0); - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); - stlink_force_debug(sl); - stlink_jtag_reset(sl,1); - usleep(10000); + stlink_jtag_reset(sl, 0); + + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } + + stlink_force_debug(sl); + stlink_jtag_reset(sl, 1); + usleep(10000); } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) stlink_enter_swd_mode(sl); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } if (reset == 1) { - if ( sl->version.stlink_v > 1) stlink_jtag_reset(sl, 2); + if ( sl->version.stlink_v > 1) { stlink_jtag_reset(sl, 2); } + stlink_reset(sl); usleep(10000); } stlink_load_device_params(sl); - return sl; + return(sl); + +on_libusb_error: + stlink_close(sl); + return(NULL); - on_libusb_error: - stlink_close(sl); - return NULL; +on_error: - on_error: - if (slu->libusb_ctx) libusb_exit(slu->libusb_ctx); + if (slu->libusb_ctx) { libusb_exit(slu->libusb_ctx); } - on_malloc_error: - if (sl != NULL) free(sl); - if (slu != NULL) free(slu); - return NULL; +on_malloc_error: + + if (sl != NULL) { free(sl); } + + if (slu != NULL) { free(slu); } + + return(NULL); } static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { @@ -1189,7 +1270,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { size_t slcnt = 0; size_t slcur = 0; - /* Count stlink */ + /* Count STLINKs */ while ((dev = devs[i++]) != NULL) { struct libusb_device_descriptor desc; int ret = libusb_get_device_descriptor(dev, &desc); @@ -1199,7 +1280,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { break; } - if (desc.idVendor != STLINK_USB_VID_ST) continue; + if (desc.idVendor != STLINK_USB_VID_ST) { continue; } if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { WLOG("skipping ST device : %#04x:%#04x)\n", desc.idVendor, desc.idProduct); @@ -1209,15 +1290,16 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { slcnt++; } - /* Allocate list of pointers */ - _sldevs = calloc(slcnt, sizeof(stlink_t *)); + _sldevs = calloc(slcnt, sizeof(stlink_t *)); // allocate list of pointers + if (!_sldevs) { *sldevs = NULL; - return 0; + return(0); } - /* Open stlinks and attach to list */ + /* Open STLINKS and attach them to list */ i = 0; + while ((dev = devs[i++]) != NULL) { struct libusb_device_descriptor desc; int ret = libusb_get_device_descriptor(dev, &desc); @@ -1227,10 +1309,10 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { break; } - if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) continue; + if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { continue; } struct libusb_device_handle* handle; - char serial[STLINK_SERIAL_MAX_SIZE] = {0,}; + char serial[STLINK_SERIAL_MAX_SIZE] = {0, }; ret = libusb_open(dev, &handle); @@ -1240,15 +1322,18 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { } else { ELOG("Failed to open USB device %#06x:%#06x, libusb error: %d)\n", desc.idVendor, desc.idProduct, ret); } + break; } + ret = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)&serial, sizeof(serial)); libusb_close(handle); - if (ret < 0) continue; + if (ret < 0) { continue; } stlink_t *sl = stlink_open_usb(0, 1, serial, 0); + if (!sl) { ELOG("Failed to open USB device %#06x:%#06x\n", desc.idVendor, desc.idProduct); continue; @@ -1259,7 +1344,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { *sldevs = _sldevs; - return slcur; + return(slcur); } size_t stlink_probe_usb(stlink_t **stdevs[]) { @@ -1271,10 +1356,12 @@ size_t stlink_probe_usb(stlink_t **stdevs[]) { ssize_t cnt; r = libusb_init(NULL); - if (r < 0) return 0; + + if (r < 0) { return(0); } cnt = libusb_get_device_list(NULL, &devs); - if (cnt < 0) return 0; + + if (cnt < 0) { return(0); } slcnt = stlink_probe_usb_devs(devs, &sldevs); libusb_free_device_list(devs, 1); @@ -1283,12 +1370,14 @@ size_t stlink_probe_usb(stlink_t **stdevs[]) { *stdevs = sldevs; - return slcnt; + return(slcnt); } void stlink_probe_usb_free(stlink_t ***stdevs, size_t size) { - if (stdevs == NULL || *stdevs == NULL || size == 0) return; - for (size_t n = 0; n < size; n++) stlink_close((*stdevs)[n]); + if (stdevs == NULL || *stdevs == NULL || size == 0) { return; } + + for (size_t n = 0; n < size; n++) { stlink_close((*stdevs)[n]); } + free(*stdevs); *stdevs = NULL; } diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 3581eabf1..d11f17381 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -1,8 +1,6 @@ /* * File: usb.h * Author: karl - * - * Created on October 1, 2011, 11:29 PM */ #ifndef STLINK_USB_H @@ -29,51 +27,51 @@ extern "C" { #define STLINK_USB_PID_STLINK_V3S_PID 0x374f #define STLINK_USB_PID_STLINK_V3_2VCP_PID 0x3753 -#define STLINK_V1_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK ) +#define STLINK_V1_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK) #define STLINK_V2_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK_32L || \ - (pid) == STLINK_USB_PID_STLINK_32L_AUDIO || \ - (pid) == STLINK_USB_PID_STLINK_NUCLEO) + (pid) == STLINK_USB_PID_STLINK_32L_AUDIO || \ + (pid) == STLINK_USB_PID_STLINK_NUCLEO) -#define STLINK_V2_1_USB_PID(pid) ( (pid) == STLINK_USB_PID_STLINK_V2_1 ) +#define STLINK_V2_1_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK_V2_1) #define STLINK_V3_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK_V3_USBLOADER || \ - (pid) == STLINK_USB_PID_STLINK_V3E_PID || \ - (pid) == STLINK_USB_PID_STLINK_V3S_PID || \ - (pid) == STLINK_USB_PID_STLINK_V3_2VCP_PID ) + (pid) == STLINK_USB_PID_STLINK_V3E_PID || \ + (pid) == STLINK_USB_PID_STLINK_V3S_PID || \ + (pid) == STLINK_USB_PID_STLINK_V3_2VCP_PID) -#define STLINK_SUPPORTED_USB_PID(pid) ( STLINK_V1_USB_PID(pid) || \ - STLINK_V2_USB_PID(pid) || \ - STLINK_V2_1_USB_PID(pid) || \ - STLINK_V3_USB_PID(pid)) +#define STLINK_SUPPORTED_USB_PID(pid) (STLINK_V1_USB_PID(pid) || \ + STLINK_V2_USB_PID(pid) || \ + STLINK_V2_1_USB_PID(pid) || \ + STLINK_V3_USB_PID(pid)) #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 - struct stlink_libusb { - libusb_context* libusb_ctx; - libusb_device_handle* usb_handle; - unsigned int ep_req; - unsigned int ep_rep; - int protocoll; - unsigned int sg_transfer_idx; - unsigned int cmd_len; - }; +struct stlink_libusb { + libusb_context* libusb_ctx; + libusb_device_handle* usb_handle; + unsigned int ep_req; + unsigned int ep_rep; + int protocoll; + unsigned int sg_transfer_idx; + unsigned int cmd_len; +}; - /** - * Open a stlink - * @param verbose Verbosity loglevel - * @param reset Reset stlink programmer - * @param serial Serial number to search for, when NULL the first stlink found is opened (binary format) - * @retval NULL Error while opening the stlink - * @retval !NULL Stlink found and ready to use - */ - stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq); - size_t stlink_probe_usb(stlink_t **stdevs[]); - void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); +/** + * Open a stlink + * @param verbose Verbosity loglevel + * @param reset Reset stlink programmer + * @param serial Serial number to search for, when NULL the first stlink found is opened (binary format) + * @retval NULL Error while opening the stlink + * @retval !NULL Stlink found and ready to use + */ +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq); +size_t stlink_probe_usb(stlink_t **stdevs[]); +void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); #ifdef __cplusplus } #endif -#endif /* STLINK_USB_H */ +#endif // STLINK_USB_H diff --git a/src/win32/getopt/README.md b/src/win32/getopt/README.md index 9bf81fa73..2ec27c2d5 100644 --- a/src/win32/getopt/README.md +++ b/src/win32/getopt/README.md @@ -1,10 +1,11 @@ getopt_port =========== -[Kim Gräsman](http://grundlig.wordpress.com) +[Kim Gräsman](http://grundlig.wordpress.com) [@kimgr](http://twitter.com/kimgr) -An original implementation of `getopt` and `getopt_long` with limited GNU extensions. Provided under the BSD license, to allow non-GPL projects to use `getopt`-style command-line parsing. +An original implementation of `getopt` and `getopt_long` with limited GNU extensions. +Provided under the BSD license, to allow non-GPL projects to use `getopt`-style command-line parsing. So far only built with Visual C++, but has no inherently non-portable constructs. @@ -18,4 +19,4 @@ See also: * [XGetOpt](http://www.codeproject.com/Articles/1940/XGetopt-A-Unix-compatible-getopt-for-MFC-and-Win32) -- No `getopt_long` support. * [Free Getopt](https://sourceforge.net/projects/freegetopt/) -- No `getopt_long` support. -For license terms, see LICENSE.txt. \ No newline at end of file +For license terms, see LICENSE.txt. diff --git a/src/win32/getopt/getopt.c b/src/win32/getopt/getopt.c index 5dd45bff7..85e8804d8 100644 --- a/src/win32/getopt/getopt.c +++ b/src/win32/getopt/getopt.c @@ -11,196 +11,191 @@ const int optional_argument = 2; char* optarg; int optopt; -/* The variable optind [...] shall be initialized to 1 by the system. */ -int optind = 1; +int optind = 1; // The variable optind [...] shall be initialized to 1 by the system int opterr; static char* optcursor = NULL; /* Implemented based on [1] and [2] for optional arguments. - optopt is handled FreeBSD-style, per [3]. - Other GNU and FreeBSD extensions are purely accidental. - -[1] http://pubs.opengroup.org/onlinepubs/000095399/functions/getopt.html -[2] http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html -[3] http://www.freebsd.org/cgi/man.cgi?query=getopt&sektion=3&manpath=FreeBSD+9.0-RELEASE -*/ + * optopt is handled FreeBSD-style, per [3]. + * Other GNU and FreeBSD extensions are purely accidental. + * + * [1] http://pubs.opengroup.org/onlinepubs/000095399/functions/getopt.html + * [2] http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html + * [3] http://www.freebsd.org/cgi/man.cgi?query=getopt&sektion=3&manpath=FreeBSD+9.0-RELEASE + */ int getopt(int argc, char* const argv[], const char* optstring) { - int optchar = -1; - const char* optdecl = NULL; - - optarg = NULL; - opterr = 0; - optopt = 0; - - /* Unspecified, but we need it to avoid overrunning the argv bounds. */ - if (optind >= argc) - goto no_more_optchars; - - /* If, when getopt() is called argv[optind] is a null pointer, getopt() - shall return -1 without changing optind. */ - if (argv[optind] == NULL) - goto no_more_optchars; - - /* If, when getopt() is called *argv[optind] is not the character '-', - getopt() shall return -1 without changing optind. */ - if (*argv[optind] != '-') - goto no_more_optchars; - - /* If, when getopt() is called argv[optind] points to the string "-", - getopt() shall return -1 without changing optind. */ - if (strcmp(argv[optind], "-") == 0) - goto no_more_optchars; - - /* If, when getopt() is called argv[optind] points to the string "--", - getopt() shall return -1 after incrementing optind. */ - if (strcmp(argv[optind], "--") == 0) { - ++optind; - goto no_more_optchars; - } - - if (optcursor == NULL || *optcursor == '\0') - optcursor = argv[optind] + 1; - - optchar = *optcursor; - - /* FreeBSD: The variable optopt saves the last known option character - returned by getopt(). */ - optopt = optchar; - - /* The getopt() function shall return the next option character (if one is - found) from argv that matches a character in optstring, if there is - one that matches. */ - optdecl = strchr(optstring, optchar); - if (optdecl) { - /* [I]f a character is followed by a colon, the option takes an - argument. */ - if (optdecl[1] == ':') { - optarg = ++optcursor; - if (*optarg == '\0') { - /* GNU extension: Two colons mean an option takes an - optional arg; if there is text in the current argv-element - (i.e., in the same word as the option name itself, for example, - "-oarg"), then it is returned in optarg, otherwise optarg is set - to zero. */ - if (optdecl[2] != ':') { - /* If the option was the last character in the string pointed to by - an element of argv, then optarg shall contain the next element - of argv, and optind shall be incremented by 2. If the resulting - value of optind is greater than argc, this indicates a missing - option-argument, and getopt() shall return an error indication. - - Otherwise, optarg shall point to the string following the - option character in that element of argv, and optind shall be - incremented by 1. - */ - if (++optind < argc) { - optarg = argv[optind]; - } else { - /* If it detects a missing option-argument, it shall return the - colon character ( ':' ) if the first character of optstring - was a colon, or a question-mark character ( '?' ) otherwise. - */ - optarg = NULL; - optchar = (optstring[0] == ':') ? ':' : '?'; - } - } else { - optarg = NULL; - } - } + int optchar = -1; + const char* optdecl = NULL; + + optarg = NULL; + opterr = 0; + optopt = 0; + + /* Unspecified, but we need it to avoid overrunning the argv bounds. */ + if (optind >= argc) { goto no_more_optchars; } + + /* If, when getopt() is called argv[optind] is a null pointer, + * getopt() shall return -1 without changing optind. + */ + if (argv[optind] == NULL) { goto no_more_optchars; } + + /* If, when getopt() is called *argv[optind] is not the character '-', + * getopt() shall return -1 without changing optind. + */ + if (*argv[optind] != '-') { goto no_more_optchars; } + + /* If, when getopt() is called argv[optind] points to the string "-", + * getopt() shall return -1 without changing optind. + */ + if (strcmp(argv[optind], "-") == 0) { goto no_more_optchars; } + + /* If, when getopt() is called argv[optind] points to the string "--", + * getopt() shall return -1 after incrementing optind. + */ + if (strcmp(argv[optind], "--") == 0) { + ++optind; + goto no_more_optchars; + } - optcursor = NULL; + if (optcursor == NULL || *optcursor == '\0') { optcursor = argv[optind] + 1; } + + optchar = *optcursor; + + /* FreeBSD: The variable optopt saves the last known option character returned by getopt(). */ + optopt = optchar; + + /* The getopt() function shall return the next option character (if one is found) + * from argv that matches a character in optstring, if there is one that matches. + */ + optdecl = strchr(optstring, optchar); + + if (optdecl) { + /* [I]f a character is followed by a colon, the option takes an argument. */ + if (optdecl[1] == ':') { + optarg = ++optcursor; + + if (*optarg == '\0') { + /* GNU extension: Two colons mean an option takes an optional arg; + * if there is text in the current argv-element (i.e., in the same word + * as the option name itself, for example, "-oarg"), then it is returned + * in optarg, otherwise optarg is set to zero. + */ + if (optdecl[2] != ':') { + /* If the option was the last character in the string pointed to by + * an element of argv, then optarg shall contain the next element + * of argv, and optind shall be incremented by 2. If the resulting + * value of optind is greater than argc, this indicates a missing + * option-argument, and getopt() shall return an error indication. + * Otherwise, optarg shall point to the string following the + * option character in that element of argv, and optind shall be + * incremented by 1. + */ + if (++optind < argc) { + optarg = argv[optind]; + } else { + /* If it detects a missing option-argument, it shall return the + * colon character ( ':' ) if the first character of optstring + * was a colon, or a question-mark character ( '?' ) otherwise. + */ + optarg = NULL; + optchar = (optstring[0] == ':') ? ':' : '?'; + } + } else { + optarg = NULL; + } + } + + optcursor = NULL; + } + } else { + /* If getopt() encounters an option character that is not contained in + * optstring, it shall return the question-mark ( '?' ) character. + */ + optchar = '?'; } - } else { - /* If getopt() encounters an option character that is not contained in - optstring, it shall return the question-mark ( '?' ) character. */ - optchar = '?'; - } - if (optcursor == NULL || *++optcursor == '\0') - ++optind; + if (optcursor == NULL || *++optcursor == '\0') { ++optind; } - return optchar; + return(optchar); no_more_optchars: - optcursor = NULL; - return -1; + optcursor = NULL; + return(-1); } -/* Implementation based on [1]. - -[1] http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html -*/ -int getopt_long(int argc, char* const argv[], const char* optstring, - const struct option* longopts, int* longindex) { - const struct option* o = longopts; - const struct option* match = NULL; - int num_matches = 0; - size_t argument_name_length = 0; - const char* current_argument = NULL; - int retval = -1; - - optarg = NULL; - optopt = 0; - - if (optind >= argc) - return -1; - - if (strlen(argv[optind]) < 3 || strncmp(argv[optind], "--", 2) != 0) - return getopt(argc, argv, optstring); - - /* It's an option; starts with -- and is longer than two chars. */ - current_argument = argv[optind] + 2; - argument_name_length = strcspn(current_argument, "="); - for (; o->name; ++o) { - if (strncmp(o->name, current_argument, argument_name_length) == 0) { - match = o; - ++num_matches; +/* Implementation based on http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html */ +int getopt_long(int argc, + char* const argv[], + const char* optstring, + const struct option* longopts, + int* longindex) { + const struct option* o = longopts; + const struct option* match = NULL; + int num_matches = 0; + size_t argument_name_length = 0; + const char* current_argument = NULL; + int retval = -1; + + optarg = NULL; + optopt = 0; + + if (optind >= argc) { return(-1); } + + if (strlen(argv[optind]) < 3 || strncmp(argv[optind], "--", 2) != 0) { + return(getopt(argc, argv, optstring)); } - } - - if (num_matches == 1) { - /* If longindex is not NULL, it points to a variable which is set to the - index of the long option relative to longopts. */ - if (longindex) - *longindex = (match - longopts); - - /* If flag is NULL, then getopt_long() shall return val. - Otherwise, getopt_long() returns 0, and flag shall point to a variable - which shall be set to val if the option is found, but left unchanged if - the option is not found. */ - if (match->flag) - *(match->flag) = match->val; - - retval = match->flag ? 0 : match->val; - - if (match->has_arg != no_argument) { - optarg = strchr(argv[optind], '='); - if (optarg != NULL) - ++optarg; - - if (match->has_arg == required_argument) { - /* Only scan the next argv for required arguments. Behavior is not - specified, but has been observed with Ubuntu and Mac OSX. */ - if (optarg == NULL && ++optind < argc) { - optarg = argv[optind]; + + // it's an option; starts with -- and is longer than two chars + current_argument = argv[optind] + 2; + argument_name_length = strcspn(current_argument, "="); + + for ( ; o->name; ++o) + if (strncmp(o->name, current_argument, argument_name_length) == 0) { + match = o; + ++num_matches; } - if (optarg == NULL) - retval = ':'; - } - } else if (strchr(argv[optind], '=')) { - /* An argument was provided to a non-argument option. - I haven't seen this specified explicitly, but both GNU and BSD-based - implementations show this behavior. - */ - retval = '?'; + + if (num_matches == 1) { + /* If longindex is not NULL, it points to a variable which is set to the + * index of the long option relative to longopts. + */ + if (longindex) { *longindex = (match - longopts); } + + /* If flag is NULL, then getopt_long() shall return val. + * Otherwise, getopt_long() returns 0, and flag shall point to a variable + * which shall be set to val if the option is found, but left unchanged if + * the option is not found. + */ + if (match->flag) { *(match->flag) = match->val; } + + retval = match->flag ? 0 : match->val; + + if (match->has_arg != no_argument) { + optarg = strchr(argv[optind], '='); + + if (optarg != NULL) { ++optarg; } + + if (match->has_arg == required_argument) { + /* Only scan the next argv for required arguments. Behavior is not + specified, but has been observed with Ubuntu and macOS. */ + if (optarg == NULL && ++optind < argc) { optarg = argv[optind]; } + + if (optarg == NULL) { retval = ':'; } + } + } else if (strchr(argv[optind], '=')) { + /* An argument was provided to a non-argument option. + * I haven't seen this specified explicitly, but both GNU and BSD-based + * implementations show this behavior. + */ + retval = '?'; + } + } else { + // unknown option or ambiguous match + retval = '?'; } - } else { - /* Unknown option or ambiguous match. */ - retval = '?'; - } - ++optind; - return retval; + ++optind; + return(retval); } diff --git a/src/win32/getopt/getopt.h b/src/win32/getopt/getopt.h index bc189b9d4..3aaf73bed 100644 --- a/src/win32/getopt/getopt.h +++ b/src/win32/getopt/getopt.h @@ -20,16 +20,19 @@ extern char* optarg; extern int optind, opterr, optopt; struct option { - const char* name; - int has_arg; - int* flag; - int val; + const char* name; + int has_arg; + int* flag; + int val; }; int getopt(int argc, char* const argv[], const char* optstring); -int getopt_long(int argc, char* const argv[], - const char* optstring, const struct option* longopts, int* longindex); +int getopt_long(int argc, + char* const argv[], + const char* optstring, + const struct option* longopts, + int* longindex); #if defined(__cplusplus) } diff --git a/src/win32/mmap.c b/src/win32/mmap.c index 60bb440e9..d702a78f6 100644 --- a/src/win32/mmap.c +++ b/src/win32/mmap.c @@ -5,34 +5,34 @@ #include "mmap.h" -void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offset) { - +void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offset) { void *buf; ssize_t count; - if ( addr || fd == -1 || (prot & PROT_WRITE)) return MAP_FAILED; + if ( addr || fd == -1 || (prot & PROT_WRITE)) { return(MAP_FAILED); } buf = malloc(len); - if ( NULL == buf ) return MAP_FAILED; - if (lseek(fd,offset,SEEK_SET) != offset) { + if ( NULL == buf ) { return(MAP_FAILED); } + + if (lseek(fd, offset, SEEK_SET) != offset) { free(buf); - return MAP_FAILED; + return(MAP_FAILED); } count = read(fd, buf, len); if (count != (ssize_t)len) { free (buf); - return MAP_FAILED; + return(MAP_FAILED); } - return buf; + return(buf); (void)flags; } int munmap (void *addr, size_t len) { free (addr); - return 0; + return(0); (void)len; } diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index 0cdb9af7b..ac9d0add3 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -27,7 +27,7 @@ #define srandom srand #define random rand -/* values for the second argument to access. These may be OR'd together. */ +/* Values for the second argument to access. These may be OR'd together. */ #define R_OK 4 // Test for read permission #define W_OK 2 // Test for write permission // #define X_OK 1 // execute permission - unsupported in windows @@ -43,24 +43,27 @@ #define chdir _chdir #define isatty _isatty #define lseek _lseek -/* read, write, and close are NOT being defined here, + +/* + * Read, write, and close are NOT being defined here, * because while there are file handle specific versions for Windows, they probably don't work for sockets. - * You need to look at your app and consider whether to call e.g. closesocket(). */ + * You need to look at your app and consider whether to call e.g. closesocket(). + */ #define ssize_t int -#define STDIN_FILENO 0 +#define STDIN_FILENO 0 #define STDOUT_FILENO 1 #define STDERR_FILENO 2 // should be in some equivalent to -typedef __int8 int8_t; -typedef __int16 int16_t; -typedef __int32 int32_t; -typedef __int64 int64_t; -typedef unsigned __int8 uint8_t; -typedef unsigned __int16 uint16_t; -typedef unsigned __int32 uint32_t; -typedef unsigned __int64 uint64_t; +typedef __int8 int8_t; +typedef __int16 int16_t; +typedef __int32 int32_t; +typedef __int64 int64_t; +typedef unsigned __int8 uint8_t; +typedef unsigned __int16 uint16_t; +typedef unsigned __int32 uint32_t; +typedef unsigned __int64 uint64_t; #ifndef STLINK_HAVE_UNISTD_H int usleep(unsigned int waitTime); diff --git a/src/win32/win32_socket.c b/src/win32/win32_socket.c index 18f2351f8..de1c7e112 100644 --- a/src/win32/win32_socket.c +++ b/src/win32/win32_socket.c @@ -25,16 +25,20 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { FD_ZERO(&ifds); FD_ZERO(&ofds); FD_ZERO(&efds); + for (i = 0, op = ip = 0; i < nfds; ++i) { fds[i].revents = 0; + if (fds[i].events & (POLLIN | POLLPRI)) { ip = &ifds; FD_SET(fds[i].fd, ip); } + if (fds[i].events & POLLOUT) { op = &ofds; FD_SET(fds[i].fd, op); } + FD_SET(fds[i].fd, &efds); } @@ -53,7 +57,7 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { #ifdef DEBUG_POLL printf("Entering select() sec=%ld usec=%ld ip=%lx op=%lx\n", - (long)timeout.tv_sec, (long)timeout.tv_usec, (long)ip, (long)op); + (long)timeout.tv_sec, (long)timeout.tv_usec, (long)ip, (long)op); #endif rc = select(0, ip, op, &efds, toptr); @@ -62,33 +66,41 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { printf("Exiting select rc=%d\n", rc); #endif - if (rc <= 0) return rc; + if (rc <= 0) { return(rc); } if (rc > 0) { for ( i = 0; i < nfds; ++i) { int fd = fds[i].fd; - if (fds[i].events & (POLLIN|POLLPRI) && FD_ISSET(fd, &ifds)) + + if (fds[i].events & (POLLIN | POLLPRI) && FD_ISSET(fd, &ifds)) { fds[i].revents |= POLLIN; - if (fds[i].events & POLLOUT && FD_ISSET(fd, &ofds)) + } + + if (fds[i].events & POLLOUT && FD_ISSET(fd, &ofds)) { fds[i].revents |= POLLOUT; - if (FD_ISSET(fd, &efds)) - /* Some error was detected ... should be some way to know. */ + } + + if (FD_ISSET(fd, &efds)) { + // Some error was detected ... should be some way to know fds[i].revents |= POLLHUP; + } #ifdef DEBUG_POLL printf("%d %d %d revent = %x\n", - FD_ISSET(fd, &ifds), FD_ISSET(fd, &ofds), FD_ISSET(fd, &efds), - fds[i].revents - ); + FD_ISSET(fd, &ifds), + FD_ISSET(fd, &ofds), + FD_ISSET(fd, &efds), + fds[i].revents); #endif } } - return rc; + + return(rc); } static void set_connect_errno(int winsock_err) { - switch(winsock_err) { + switch (winsock_err) { case WSAEINVAL: case WSAEALREADY: case WSAEWOULDBLOCK: @@ -101,7 +113,7 @@ static void set_connect_errno(int winsock_err) { } static void set_socket_errno(int winsock_err) { - switch(winsock_err) { + switch (winsock_err) { case WSAEWOULDBLOCK: errno = EAGAIN; break; @@ -111,71 +123,81 @@ static void set_socket_errno(int winsock_err) { } } -/* - * A wrapper around the socket() function. +/* A wrapper around the socket() function. * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ SOCKET win32_socket(int domain, int type, int protocol) { SOCKET fd = socket(domain, type, protocol); - if (fd == INVALID_SOCKET) set_socket_errno(WSAGetLastError()); - return fd; + + if (fd == INVALID_SOCKET) { set_socket_errno(WSAGetLastError()); } + + return(fd); } -/* - * A wrapper around the connect() function. +/* A wrapper around the connect() function. * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ int win32_connect(SOCKET fd, struct sockaddr *addr, socklen_t addr_len) { int rc = connect(fd, addr, addr_len); assert(rc == 0 || rc == SOCKET_ERROR); - if (rc == SOCKET_ERROR) set_connect_errno(WSAGetLastError()); - return rc; + + if (rc == SOCKET_ERROR) { set_connect_errno(WSAGetLastError()); } + + return(rc); } -/* - * A wrapper around the accept() function. +/* A wrapper around the accept() function. * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ SOCKET win32_accept(SOCKET fd, struct sockaddr *addr, socklen_t *addr_len) { SOCKET newfd = accept(fd, addr, addr_len); + if (newfd == INVALID_SOCKET) { set_socket_errno(WSAGetLastError()); newfd = (SOCKET)-1; } - return newfd; + + return(newfd); } -/* - * A wrapper around the shutdown() function. +/* A wrapper around the shutdown() function. * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ int win32_shutdown(SOCKET fd, int mode) { int rc = shutdown(fd, mode); assert(rc == 0 || rc == SOCKET_ERROR); - if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); - return rc; + + if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } + + return(rc); } int win32_close_socket(SOCKET fd) { int rc = closesocket(fd); - if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); - return rc; + + if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } + + return(rc); } ssize_t win32_write_socket(SOCKET fd, void *buf, int n) { int rc = send(fd, buf, n, 0); - if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); - return rc; + + if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } + + return(rc); } ssize_t win32_read_socket(SOCKET fd, void *buf, int n) { int rc = recv(fd, buf, n, 0); - if (rc == SOCKET_ERROR) set_socket_errno(WSAGetLastError()); - return rc; + + if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } + + return(rc); } @@ -185,41 +207,45 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) { char *tok; - if (s == NULL && (s = *lasts) == NULL) return (NULL); + if (s == NULL && (s = *lasts) == NULL) { return (NULL); } - // Skip (span) leading delimiters (s += strspn(s, delim), sort of). + // skip (span) leading delimiters (s += strspn(s, delim), sort of). cont: c = *s++; - for (spanp = (char *)delim; (sc = *spanp++) != 0;) { - if (c == sc) - goto cont; - } + + for (spanp = (char *)delim; (sc = *spanp++) != 0;) + if (c == sc) { goto cont; } + if (c == 0) { // no non-delimiter characters *lasts = NULL; return (NULL); } + tok = s - 1; - /* - * Scan token (scan for delimiters: s += strcspn(s, delim), sort of). + /* Scan token (scan for delimiters: s += strcspn(s, delim), sort of). * Note that delim must have one NUL; we stop if we see that, too. */ - for (;;) { + for ( ; ;) { c = *s++; spanp = (char *)delim; - do { + + do if ((sc = *spanp++) == c) { if (c == 0) { s = NULL; } else { s[-1] = 0; } + *lasts = s; - return (tok); + return(tok); } - } while (sc != 0); + + while (sc != 0); } + // NOT REACHED } @@ -229,22 +255,29 @@ char *win32_strsep (char **stringp, const char *delim) { register int c, sc; char *tok; - if ((s = *stringp) == NULL) return (NULL); - for (tok = s;;) { + if ((s = *stringp) == NULL) { + return(NULL); + } + + for (tok = s; ;) { c = *s++; spanp = delim; - do { + + do if ((sc = *spanp++) == c) { if (c == 0) { s = NULL; } else { s[-1] = 0; } + *stringp = s; - return (tok); + return(tok); } - } while (sc != 0); + + while (sc != 0); } + // NOT REACHED } @@ -264,18 +297,19 @@ int usleep(unsigned int waitTime) { WaitForSingleObject(timer, INFINITE); CloseHandle(timer); - return 0; + return(0); } + LARGE_INTEGER perf_cnt, start, now; QueryPerformanceFrequency(&perf_cnt); QueryPerformanceCounter(&start); - do { - QueryPerformanceCounter((LARGE_INTEGER*) &now); - } while ((now.QuadPart - start.QuadPart) / (float)perf_cnt.QuadPart * 1000 * 1000 < waitTime); + do + QueryPerformanceCounter((LARGE_INTEGER*)&now); + while ((now.QuadPart - start.QuadPart) / (float)perf_cnt.QuadPart * 1000 * 1000 < waitTime); - return 0; + return(0); } #endif diff --git a/src/win32/win32_socket.h b/src/win32/win32_socket.h index d2a3ac38c..ea1a39c93 100644 --- a/src/win32/win32_socket.h +++ b/src/win32/win32_socket.h @@ -62,8 +62,8 @@ SOCKET win32_accept(SOCKET, struct sockaddr*, socklen_t *); int win32_shutdown(SOCKET, int); int win32_close_socket(SOCKET fd); -#define strtok_r(x, y, z) win32_strtok_r(x, y, z) -#define strsep(x,y) win32_strsep(x,y) +#define strtok_r(x, y, z) win32_strtok_r(x, y, z) +#define strsep(x,y) win32_strsep(x,y) char *win32_strtok_r(char *s, const char *delim, char **lasts); char *win32_strsep(char **stringp, const char *delim); diff --git a/tests/flash.c b/tests/flash.c index d47b3564d..a8d479b2d 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -6,7 +6,7 @@ #include #if defined(_MSC_VER) - #include +#include #endif struct Test { @@ -37,25 +37,25 @@ static bool execute_test(const struct Test * test) { /* parse (tokenize) the test command line */ #if defined(_MSC_VER) - char *cmd_line = alloca(strlen(test->cmd_line) + 1); + char *cmd_line = alloca(strlen(test->cmd_line) + 1); #else - char cmd_line[strlen(test->cmd_line) + 1]; + char cmd_line[strlen(test->cmd_line) + 1]; #endif strcpy(cmd_line, test->cmd_line); for (char * tok = strtok(cmd_line, " "); tok; tok = strtok(NULL, " ")) { - if ((size_t)ac >= sizeof(av)/sizeof(av[0])) - return false; + if ((size_t)ac >= sizeof(av) / sizeof(av[0])) return(false); + av[ac] = tok; ++ac; } - /* call */ + /* Call */ struct flash_opts opts; int res = flash_get_opts(&opts, ac, av); - /* compare results */ + /* Compare results */ bool ret = (res == test->res); if (ret && (res == 0)) { @@ -71,87 +71,87 @@ static bool execute_test(const struct Test * test) { } printf("[%s] (%d) %s\n", ret ? "OK" : "ERROR", res, test->cmd_line); - return ret; + return(ret); } static struct Test tests[] = { { "", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset read test.bin 0x80000000 0x1000", 0, - { .cmd = FLASH_CMD_READ, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0x1000, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_READ, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0x1000, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } }, { "--debug --reset write test.bin 0x80000000", 0, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } }, { "--debug --freq 5k --reset write test.bin 0x80000000", 0, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 5, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 5, + .format = FLASH_FORMAT_BINARY } }, { "--debug --freq 15K --reset write test.bin 0x80000000", 0, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 15, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 15, + .format = FLASH_FORMAT_BINARY } }, { "--debug --freq=5k --reset write test.bin 0x80000000", 0, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 5, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 5, + .format = FLASH_FORMAT_BINARY } }, { "--debug --freq=6k --reset write test.bin 0x80000000", -1, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 6, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 6, + .format = FLASH_FORMAT_BINARY } }, { "--debug --reset read test.bin 0x80000000 1000", 0, - { .cmd = FLASH_CMD_READ, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 1000, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_READ, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 1000, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } }, { "--debug --reset read test.bin 0x80000000 1k", 0, { .cmd = FLASH_CMD_READ, @@ -176,71 +176,72 @@ static struct Test tests[] = { .format = FLASH_FORMAT_BINARY } }, { "--debug --reset write test.bin 0x80000000", 0, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.bin", + .addr = 0x80000000, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } }, { "erase", 0, - { .cmd = FLASH_CMD_ERASE, - .serial = { 0 }, - .filename = NULL, - .addr = 0, - .size = 0, - .reset = 0, - .log_level = STND_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_ERASE, + .serial = { 0 }, + .filename = NULL, + .addr = 0, + .size = 0, + .reset = 0, + .log_level = STND_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } }, { "--debug --reset --format=ihex write test.hex", 0, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.hex", - .addr = 0, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_IHEX } + { .cmd = FLASH_CMD_WRITE, + .serial = { 0 }, + .filename = "test.hex", + .addr = 0, + .size = 0, + .reset = 1, + .log_level = DEBUG_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_IHEX } }, { "--debug --reset --format=binary write test.hex", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset --format=ihex write test.hex 0x80000000", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset write test.hex sometext", -1, FLASH_OPTS_INITIALIZER }, { "--serial A1020304 erase sometext", -1, FLASH_OPTS_INITIALIZER }, { "--serial A1020304 erase", 0, - { .cmd = FLASH_CMD_ERASE, - .serial = "\xA1\x02\x03\x04", - .filename = NULL, - .addr = 0, - .size = 0, - .reset = 0, - .log_level = STND_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_ERASE, + .serial = "\xA1\x02\x03\x04", + .filename = NULL, + .addr = 0, + .size = 0, + .reset = 0, + .log_level = STND_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } }, { "--serial=A1020304 erase", 0, - { .cmd = FLASH_CMD_ERASE, - .serial = "\xA1\x02\x03\x04", - .filename = NULL, - .addr = 0, - .size = 0, - .reset = 0, - .log_level = STND_LOG_LEVEL, - .freq = 0, - .format = FLASH_FORMAT_BINARY } + { .cmd = FLASH_CMD_ERASE, + .serial = "\xA1\x02\x03\x04", + .filename = NULL, + .addr = 0, + .size = 0, + .reset = 0, + .log_level = STND_LOG_LEVEL, + .freq = 0, + .format = FLASH_FORMAT_BINARY } }, }; int main() { bool allOk = true; - for (size_t i = 0; i < sizeof(tests)/sizeof(tests[0]); ++i) { + + for (size_t i = 0; i < sizeof(tests) / sizeof(tests[0]); ++i) if (!execute_test(&tests[i])) allOk = false; - } + return (allOk ? 0 : 1); } diff --git a/tests/sg.c b/tests/sg.c index 1af177174..745df845f 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -1,9 +1,3 @@ -/* - * File: test_main.c - * - * main() ripped out of old stlink-hw.c - */ - #include #include #include @@ -11,7 +5,7 @@ #include #if defined(_MSC_VER) - #define __attribute__(x) +#define __attribute__(x) #endif static void __attribute__((unused)) mark_buf(stlink_t *sl) { @@ -30,28 +24,28 @@ static void __attribute__((unused)) mark_buf(stlink_t *sl) { } -int main(void) { +int main(void) { // main() ripped out of old stlink-hw.c /* Avoid unused parameter warning */ // set scpi lib debug level: 0 for no debug info, 10 for lots fputs( - "\nUsage: stlink-access-test [anything at all] ...\n" - "\n*** Notice: The stlink firmware violates the USB standard.\n" - "*** Because we just use libusb, we can just tell the kernel's\n" - "*** driver to simply ignore the device...\n" - "*** Unplug the stlink and execute once as root:\n" - "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n", - stderr); + "\nUsage: stlink-access-test [anything at all] ...\n" + "\n*** Notice: The stlink firmware violates the USB standard.\n" + "*** Because we just use libusb, we can just tell the kernel's\n" + "*** driver to simply ignore the device...\n" + "*** Unplug the stlink and execute once as root:\n" + "modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i\n\n", + stderr); stlink_t *sl = stlink_v1_open(99, 1); - if (sl == NULL) - return 0; + + if (sl == NULL) return(0); // we are in mass mode, go to swd stlink_enter_swd_mode(sl); stlink_current_mode(sl); stlink_core_id(sl); stlink_status(sl); - //stlink_force_debug(sl); + // stlink_force_debug(sl); stlink_reset(sl); stlink_status(sl); // core system control block @@ -75,8 +69,8 @@ int main(void) { #define GPIOC 0x40011000 // port C #define GPIOC_CRH (GPIOC + 0x04) // port configuration register high #define GPIOC_ODR (GPIOC + 0x0c) // port output data register - #define LED_BLUE (1<<8) // pin 8 - #define LED_GREEN (1<<9) // pin 9 + #define LED_BLUE (1 << 8) // pin 8 + #define LED_GREEN (1 << 9) // pin 9 stlink_read_mem32(sl, GPIOC_CRH, 4); uint32_t io_conf = read_uint32(sl->q_buf, 0); DLOG("GPIOC_CRH = 0x%08x\n", io_conf); @@ -86,17 +80,19 @@ int main(void) { stlink_write_mem32(sl, GPIOC_CRH, 4); memset(sl->q_buf, 0, sizeof(sl->q_buf)); + for (int i = 0; i < 100; i++) { write_uint32(sl->q_buf, LED_BLUE | LED_GREEN); stlink_write_mem32(sl, GPIOC_ODR, 4); - //stlink_read_mem32(sl, 0x4001100c, 4); - //DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); + // stlink_read_mem32(sl, 0x4001100c, 4); + // DD(sl, "GPIOC_ODR = 0x%08x", read_uint32(sl->q_buf, 0)); usleep(100 * 1000); memset(sl->q_buf, 0, sizeof(sl->q_buf)); stlink_write_mem32(sl, GPIOC_ODR, 4); // PC lo usleep(100 * 1000); } + write_uint32(sl->q_buf, io_conf); // set old state #endif @@ -104,10 +100,10 @@ int main(void) { // TODO rtfm: stlink doesn't have flash write routines // writing to the flash area confuses the fw for the next read access - //stlink_read_mem32(sl, 0, 1024*6); + // stlink_read_mem32(sl, 0, 1024*6); // flash 0x08000000 128kB fputs("++++++++++ read a flash at 0x0800 0000\n", stderr); - stlink_read_mem32(sl, 0x08000000, 1024 * 6); //max 6kB + stlink_read_mem32(sl, 0x08000000, 1024 * 6); // max 6kB clear_buf(sl); stlink_read_mem32(sl, 0x08000c00, 5); stlink_read_mem32(sl, 0x08000c00, 4); @@ -122,9 +118,9 @@ int main(void) { fputs("\n++++++++++ read/write 8bit, sram at 0x2000 0000 ++++++++++++++++\n\n", stderr); memset(sl->q_buf, 0, sizeof(sl->q_buf)); mark_buf(sl); - //stlink_write_mem8(sl, 0x20000000, 16); - //stlink_write_mem8(sl, 0x20000000, 1); - //stlink_write_mem8(sl, 0x20000001, 1); + // stlink_write_mem8(sl, 0x20000000, 16); + // stlink_write_mem8(sl, 0x20000000, 1); + // stlink_write_mem8(sl, 0x20000001, 1); stlink_write_mem8(sl, 0x2000000b, 3); stlink_read_mem32(sl, 0x20000000, 16); #endif @@ -157,7 +153,7 @@ int main(void) { stlink_read_mem32(sl, 0x20000000, 64); mark_buf(sl); - stlink_write_mem32(sl, 0x20000000, 1024 * 8); //8kB + stlink_write_mem32(sl, 0x20000000, 1024 * 8); // 8kB stlink_read_mem32(sl, 0x20000000, 1024 * 6); stlink_read_mem32(sl, 0x20000000 + 1024 * 6, 1024 * 2); #endif @@ -208,7 +204,7 @@ int main(void) { stlink_close(sl); #endif - //fflush(stderr); - //fflush(stdout); - return EXIT_SUCCESS; + // fflush(stderr); + // fflush(stdout); + return(EXIT_SUCCESS); } diff --git a/tests/usb.c b/tests/usb.c index ce72e24a5..03c135f00 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -3,14 +3,12 @@ #include #include -static void usage(void) -{ +static void usage(void) { puts("test-usb --reset"); puts("test-usb --no-reset"); } int main(int ac, char** av) { - stlink_t* sl; struct stlink_reg regs; int reset = 0; @@ -18,15 +16,18 @@ int main(int ac, char** av) { if (ac == 2) { if (strcmp(av[1], "--reset") == 0) reset = 2; - if (strcmp(av[1], "--no-reset") == 0) + + if (strcmp(av[1], "--no-reset") == 0) reset = 1; } + if (reset == 0) { usage(); - return 0; + return(0); } sl = stlink_open_usb(10, reset, NULL, 0); + if (sl != NULL) { printf("-- version\n"); stlink_version(sl); @@ -47,6 +48,7 @@ int main(int ac, char** av) { printf("-- core_id: %#x\n", sl->core_id); cortex_m3_cpuid_t cpuid; + if (stlink_cpu_id(sl, &cpuid)) { printf("Failed reading stlink_cpu_id\n"); } else { @@ -57,6 +59,7 @@ int main(int ac, char** av) { printf("-- read_sram\n"); static const uint32_t sram_base = STM32_SRAM_BASE; uint32_t off; + for (off = 0; off < 16; off += 4) stlink_read_mem32(sl, sram_base + off, 4); @@ -64,24 +67,24 @@ int main(int ac, char** av) { stlink_read_mem32(sl, STLINK_REG_CM3_FP_CTRL, 4); // no idea what reg this is... - //stlink_read_mem32(sl, 0xe000ed90, 4); + // stlink_read_mem32(sl, 0xe000ed90, 4); // no idea what register this is... - //stlink_read_mem32(sl, 0xe000edf0, 4); + // stlink_read_mem32(sl, 0xe000edf0, 4); // offset 0xC into TIM11 register? TIMx_DIER? - //stlink_read_mem32(sl, 0x4001100c, 4); + // stlink_read_mem32(sl, 0x4001100c, 4); - /* Test 32 bit Write */ - write_uint32(sl->q_buf,0x01234567); - stlink_write_mem32(sl,0x200000a8,4); - write_uint32(sl->q_buf,0x89abcdef); - stlink_write_mem32(sl,0x200000ac, 4); + /* Test 32 bit write */ + write_uint32(sl->q_buf, 0x01234567); + stlink_write_mem32(sl, 0x200000a8, 4); + write_uint32(sl->q_buf, 0x89abcdef); + stlink_write_mem32(sl, 0x200000ac, 4); stlink_read_mem32(sl, 0x200000a8, 4); stlink_read_mem32(sl, 0x200000ac, 4); /* Test 8 bit write */ - write_uint32(sl->q_buf,0x01234567); - stlink_write_mem8(sl,0x200001a8,3); - write_uint32(sl->q_buf,0x89abcdef); + write_uint32(sl->q_buf, 0x01234567); + stlink_write_mem8(sl, 0x200001a8, 3); + write_uint32(sl->q_buf, 0x89abcdef); stlink_write_mem8(sl, 0x200001ac, 3); stlink_read_mem32(sl, 0x200001a8, 4); stlink_read_mem32(sl, 0x200001ac, 4); @@ -96,8 +99,8 @@ int main(int ac, char** av) { stlink_write_reg(sl, 0x01234567, 3); stlink_write_reg(sl, 0x89abcdef, 4); stlink_write_reg(sl, 0x12345678, 15); - for (off = 0; off < 21; off += 1) - stlink_read_reg(sl, off, ®s); + + for (off = 0; off < 21; off += 1) stlink_read_reg(sl, off, ®s); stlink_read_all_regs(sl, ®s); @@ -115,5 +118,6 @@ int main(int ac, char** av) { stlink_close(sl); } - return 0; + + return(0); } From 06aec5b541ac0e97125dad5e14ce0f8e72e5e6c4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 13 Jun 2020 21:45:05 +0200 Subject: [PATCH 0972/1435] Code style fixes for win32_socket. --- src/win32/win32_socket.c | 12 ++++++------ src/win32/win32_socket.h | 4 ++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/win32/win32_socket.c b/src/win32/win32_socket.c index de1c7e112..9138a7679 100644 --- a/src/win32/win32_socket.c +++ b/src/win32/win32_socket.c @@ -231,7 +231,7 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) { c = *s++; spanp = (char *)delim; - do + do { if ((sc = *spanp++) == c) { if (c == 0) { s = NULL; @@ -243,7 +243,7 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) { return(tok); } - while (sc != 0); + } while (sc != 0); } // NOT REACHED @@ -263,7 +263,7 @@ char *win32_strsep (char **stringp, const char *delim) { c = *s++; spanp = delim; - do + do { if ((sc = *spanp++) == c) { if (c == 0) { s = NULL; @@ -275,7 +275,7 @@ char *win32_strsep (char **stringp, const char *delim) { return(tok); } - while (sc != 0); + } while (sc != 0); } // NOT REACHED @@ -305,9 +305,9 @@ int usleep(unsigned int waitTime) { QueryPerformanceFrequency(&perf_cnt); QueryPerformanceCounter(&start); - do + do { QueryPerformanceCounter((LARGE_INTEGER*)&now); - while ((now.QuadPart - start.QuadPart) / (float)perf_cnt.QuadPart * 1000 * 1000 < waitTime); + } while ((now.QuadPart - start.QuadPart) / (float)perf_cnt.QuadPart * 1000 * 1000 < waitTime); return(0); } diff --git a/src/win32/win32_socket.h b/src/win32/win32_socket.h index ea1a39c93..5f8f09589 100644 --- a/src/win32/win32_socket.h +++ b/src/win32/win32_socket.h @@ -20,9 +20,9 @@ #pragma warning(pop) #endif -/* winsock doesn't feature poll(), so there is a version implemented in terms of select() in mingw.c. +/* winsock doesn't feature poll(), so there is a version implemented in terms of select() in win32_socket.c. * The following definitions are copied from linux man pages. - * A poll() macro is defined to call the version in mingw.c. + * A poll() macro is defined to call the version in win32_socket.c. */ #if !defined(_WIN32_WINNT) || (_WIN32_WINNT < 0x0600) From d473c99f10ec10ca525c9cbe9b0e3d3c36bf5af7 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 14 Jun 2020 17:20:49 +0200 Subject: [PATCH 0973/1435] Fix for external CMAKE_MODULE_PATH (Closes #962) --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 52f6867f4..59b9d963c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,7 +4,7 @@ cmake_minimum_required(VERSION 3.4.2) cmake_policy(SET CMP0042 NEW) -set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") +set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) From ffe6240012d7cb83749bf00baf0e300cf7cab2ea Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 15 Jun 2020 10:46:09 +0200 Subject: [PATCH 0974/1435] Minor whitespace and code style fix --- cmake/modules/get_version.cmake | 2 +- src/stlink-lib/libusb_settings.h | 26 +++++++++++++------------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/cmake/modules/get_version.cmake b/cmake/modules/get_version.cmake index b80f0c9db..dddb35549 100644 --- a/cmake/modules/get_version.cmake +++ b/cmake/modules/get_version.cmake @@ -55,7 +55,7 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") message(STATUS "Rewrite ${PROJECT_SOURCE_DIR}/.version with ${__version_str}.") endif () - else (EXISTS "${PROJECT_SOURCE_DIR}/.version") + else (NOT EXISTS "${PROJECT_SOURCE_DIR}/.version") # No local .version file found: Create a new one... file(WRITE "${PROJECT_SOURCE_DIR}/.version" ${__version_str}) diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index 046c0b33d..fea28237b 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -5,19 +5,19 @@ /* - libusb ver | LIBUSB_API_VERSION - -----------+-------------------- - v1.0.13 | 0x01000100 - v1.0.14 | 0x010000FF - v1.0.15 | 0x01000101 - v1.0.16 | 0x01000102 - v1.0.17 | 0x01000102 - v1.0.18 | 0x01000102 - v1.0.19 | 0x01000103 - v1.0.20 | 0x01000104 - v1.0.21 | 0x01000105 - v1.0.22 | 0x01000106 - v1.0.23 | 0x01000107 + libusb ver | LIBUSB_API_VERSION + -----------+-------------------- + v1.0.13 | 0x01000100 + v1.0.14 | 0x010000FF + v1.0.15 | 0x01000101 + v1.0.16 | 0x01000102 + v1.0.17 | 0x01000102 + v1.0.18 | 0x01000102 + v1.0.19 | 0x01000103 + v1.0.20 | 0x01000104 + v1.0.21 | 0x01000105 + v1.0.22 | 0x01000106 + v1.0.23 | 0x01000107 */ From 15bdf0a4f0c29c14e81974d322bcf31ee5338de8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 16 Jun 2020 16:54:46 +0200 Subject: [PATCH 0975/1435] Changed path for udev rules to default /etc/udev/rules.d/ -> /lib/udev/rules.d/ --- CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 59b9d963c..82e5bf769 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -268,8 +268,8 @@ if (CMAKE_SYSTEM_NAME STREQUAL "Linux") set(STLINK_MODPROBED_DIR "/etc/modprobe.d" CACHE PATH "modprobe.d directory") install(FILES ${CMAKE_SOURCE_DIR}/config/modprobe.d/stlink_v1.conf DESTINATION ${STLINK_MODPROBED_DIR}) - ## Install udev rules files to /etc/udev/rules.d/ (explicitly hardcoded) - set(STLINK_UDEV_RULES_DIR "/etc/udev/rules.d" CACHE PATH "udev rules directory") + ## Install udev rules files to /lib/udev/rules.d/ (explicitly hardcoded) + set(STLINK_UDEV_RULES_DIR "/lib/udev/rules.d" CACHE PATH "udev rules directory") file(GLOB RULES_FILES ${CMAKE_SOURCE_DIR}/config/udev/rules.d/*.rules) install(FILES ${RULES_FILES} DESTINATION ${STLINK_UDEV_RULES_DIR}) endif () From e250773b88c915a9726a9eae112262fb74dcd193 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 17 Jun 2020 11:32:41 +0200 Subject: [PATCH 0976/1435] [doc] Added --reset option for st-flash (Closes #642) --- doc/tutorial.md | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/tutorial.md b/doc/tutorial.md index 81315dbef..7b8b1d461 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -8,6 +8,7 @@ stlink Tools Tutorial | --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k
      for the STM32F103C8T6 to assume 128k of flash being present. This option accepts
      decimal (128k), octal 0200k, or hex 0x80k values. Leaving the multiplier out is
      equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k"
      or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | | --freq=n[k][m] | st-flash,
      st-util | The frequency of the SWD/JTAG interface can be specified, to override the default
      1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
      the unit `Hz` being left out. Valid frequencies are `5K, 15K, 25K, 50K, 100K,`
      `125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at
      the end of binary file. This may cause some garbage data left after a flash operation.
      This option was enabled by default in earlier releases. | v1.6.1 | +| --reset | st-flash | Trigger a reset both before and after flashing. | v1.0.0 | | --version | st-info,
      st-flash,
      st-util | Print version information. | | | --help | st-flash,
      st-util | Print list of available commands. _(To be added to this table.)_ | | From 3f20a25cc0330b3a3e8093a93bba99d91227bbed Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 17 Jun 2020 15:15:33 +0200 Subject: [PATCH 0977/1435] Updated cmake-settings - Changed header installation path - Fix for cpack output directory --- CMakeLists.txt | 19 ++++++++----------- cmake/modules/get_version.cmake | 2 +- cmake/packaging/cpack_config.cmake | 1 + inc/CMakeLists.txt | 7 ++++--- 4 files changed, 14 insertions(+), 15 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 82e5bf769..5171628ad 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -32,15 +32,6 @@ else () set(CMAKE_C_FLAGS_RELWITHDEBINFO_INIT "/MT /Zi /O2 /Ob1 /D NDEBUG") endif () -## Set installation directories for header files ### TODO: Clean this up... -if (IS_DIRECTORY ${INCLUDE_INSTALL_DIR}) - set(INCLUDE_INSTALL_DIR ${INCLUDE_INSTALL_DIR} CACHE PATH "Main include directory") - set(STLINK_INCLUDE_PATH "${INCLUDE_INSTALL_DIR}") -else () - set(INCLUDE_INSTALL_DIR "include" CACHE PATH "Main include directory") - set(STLINK_INCLUDE_PATH "${CMAKE_INSTALL_PREFIX}/${INCLUDE_INSTALL_DIR}") -endif () - ### # Dependencies @@ -94,12 +85,19 @@ include_directories(src) include_directories(src/st-flash) include_directories(src/stlink-lib) +## Set installation directory for header files +set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR} CACHE PATH "Main include install directory") + +## Subordinate CMakeLists for version config & header installation +add_subdirectory(inc) + +## Define source- and headerfiles for stlink library set(STLINK_HEADERS inc/backend.h + inc/stlink.h src/stlink-lib/commands.h src/stlink-lib/libusb_settings.h src/stlink-lib/reg.h - inc/stlink.h src/stlink-lib/chipid.h src/stlink-lib/flash_loader.h src/stlink-lib/logging.h @@ -279,7 +277,6 @@ endif () # Additional build tasks ### -add_subdirectory(inc) # contains subordinate CMakeLists for version config add_subdirectory(src/stlink-gui) # contains subordinate CMakeLists to build GUI add_subdirectory(tests) # contains subordinate CMakeLists to build test executables add_subdirectory(cmake/packaging) # contains subordinate CMakeLists to build packages diff --git a/cmake/modules/get_version.cmake b/cmake/modules/get_version.cmake index dddb35549..70fbde816 100644 --- a/cmake/modules/get_version.cmake +++ b/cmake/modules/get_version.cmake @@ -52,7 +52,7 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") # ...the version does not match with git-version string if (NOT __version_str STREQUAL __version_file) - message(STATUS "Rewrite ${PROJECT_SOURCE_DIR}/.version with ${__version_str}.") + message(STATUS "Rewrite ${PROJECT_SOURCE_DIR}/.version with ${__version_str}!") endif () else (NOT EXISTS "${PROJECT_SOURCE_DIR}/.version") diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index f36a50b40..469e743ca 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -12,6 +12,7 @@ set(CPACK_PACKAGE_VENDOR "stlink-org") set(CMAKE_PROJECT_HOMEPAGE_URL "https://github.com/stlink-org/stlink") set(CPACK_SET_DESTDIR "ON") +file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/dist) set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist") if (APPLE) # macOS diff --git a/inc/CMakeLists.txt b/inc/CMakeLists.txt index 66af7e33f..c816c7044 100644 --- a/inc/CMakeLists.txt +++ b/inc/CMakeLists.txt @@ -3,7 +3,8 @@ configure_file( "${CMAKE_BINARY_DIR}/inc/version.h" ) -file(GLOB STLINK_HEADERS "src/st-link-lib/*.h" "${CMAKE_BINARY_DIR}/inc/version.h") +file(GLOB STLINK_HEADERS + "${CMAKE_SOURCE_DIR}/inc/*.h" + "${CMAKE_SOURCE_DIR}/src/stlink-lib/*.h" + "${CMAKE_BINARY_DIR}/inc/version.h") install(FILES ${STLINK_HEADERS} DESTINATION ${STLINK_INCLUDE_PATH}) -install(FILES ${CMAKE_SOURCE_DIR}/inc/stlink.h DESTINATION ${STLINK_INCLUDE_PATH}) -install(FILES ${CMAKE_SOURCE_DIR}/inc/stm32.h DESTINATION ${STLINK_INCLUDE_PATH}) From ae0db2da1517ba0fc6273d8bb4b04a076e971cba Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 17 Jun 2020 17:19:58 +0200 Subject: [PATCH 0978/1435] st-info: Fixed width int sizes for casting --- src/st-info/info.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/src/st-info/info.c b/src/st-info/info.c index 1bc48a05e..2343140de 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -28,12 +28,9 @@ static void stlink_print_serial(stlink_t *sl, bool openocd) { fmt = "%02x"; } - for (int n = 0; n < sl->serial_size; n++) - printf(fmt, sl->serial[n]); + for (int n = 0; n < sl->serial_size; n++) { printf(fmt, sl->serial[n]); } - if (openocd) { - printf("\""); - } + if (openocd) { printf("\""); } printf("\n"); } @@ -41,19 +38,15 @@ static void stlink_print_serial(stlink_t *sl, bool openocd) { static void stlink_print_info(stlink_t *sl) { const struct stlink_chipid_params *params = NULL; - if (!sl) { - return; - } + if (!sl) { return; } printf(" serial: "); stlink_print_serial(sl, false); printf(" hla-serial: "); stlink_print_serial(sl, true); - printf(" flash: %u (pagesize: %u)\n", - (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); - - printf(" sram: %u\n", (unsigned int)sl->sram_size); + (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); + printf(" sram: %u\n", (uint32_t)sl->sram_size); printf(" chipid: 0x%.4x\n", sl->chip_id); params = stlink_chipid_get_params(sl->chip_id); @@ -69,7 +62,7 @@ static void stlink_probe(void) { printf("Found %u stlink programmers\n", (unsigned int)size); - for (size_t n = 0; n < size; n++) stlink_print_info(stdevs[n]); + for (size_t n = 0; n < size; n++) { stlink_print_info(stdevs[n]); } stlink_probe_usb_free(&stdevs, size); } @@ -126,11 +119,11 @@ static int print_data(int ac, char **av) { } else if (strcmp(av[1], "--hla-serial") == 0) { stlink_print_serial(sl, true); } else if (strcmp(av[1], "--flash") == 0) { - printf("0x%x\n", (unsigned int)sl->flash_size); + printf("0x%x\n", (uint32_t)sl->flash_size); } else if (strcmp(av[1], "--pagesize") == 0) { - printf("0x%x\n", (unsigned int)sl->flash_pgsz); + printf("0x%x\n", (uint32_t)sl->flash_pgsz); } else if (strcmp(av[1], "--sram") == 0) { - printf("0x%x\n", (unsigned int)sl->sram_size); + printf("0x%x\n", (uint32_t)sl->sram_size); } else if (strcmp(av[1], "--chipid") == 0) { printf("0x%.4x\n", sl->chip_id); } else if (strcmp(av[1], "--descr") == 0) { From 2952859d61903f99555a7736e60b3237fbe0132a Mon Sep 17 00:00:00 2001 From: Geoffrey Brown Date: Wed, 17 Jun 2020 17:16:58 -0400 Subject: [PATCH 0979/1435] change timeout on flash write --- src/stlink-lib/flash_loader.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 71601e3da..0e79c3c0a 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -360,11 +360,11 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe * the OS uses, the wait until the error message is reduced to the same order of magnitude * as what was intended. -- REW. */ -#define WAIT_ROUNDS 100 +#define WAIT_ROUNDS 30 // wait until done (reaches breakpoint) for (i = 0; i < WAIT_ROUNDS; i++) { - usleep(1000); + usleep(10000); if (stlink_is_core_halted(sl)) { break; } } From 1541dfcb0bfa3984e54b599d6b7d13c3f26c65d7 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Thu, 18 Jun 2020 17:17:51 +0300 Subject: [PATCH 0980/1435] fix #988 --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 361a24dbf..3459a53a0 100644 --- a/src/common.c +++ b/src/common.c @@ -1624,7 +1624,7 @@ static int map_file(mapped_file_t* mf, const char* path) { if (sizeof(st.st_size) != sizeof(size_t)) { // on 32 bit systems, check if there is an overflow - if (st.st_size > (off_t)UINT32_MAX) { + if (st.st_size > (off_t)INT32_MAX) { fprintf(stderr, "mmap() size_t overflow for file %s\n", path); goto on_error; } From 54e5627a269dddcd00fd1476f7dee62c5b207a52 Mon Sep 17 00:00:00 2001 From: Jan Bramkamp Date: Sat, 20 Jun 2020 01:44:25 +0200 Subject: [PATCH 0981/1435] Add support for FreeBSD's libusb reimplementation FreeBSD reimplemented the libusb API, but their implementation of libusb_set_debug() expects an enum libusb_debug_level instead of an enum libusb_log_level. This causes excessive logging on FreeBSD drowning out all expected output. To keep the changes to other platforms minimal the FreeBSD specific code is kept inside an ifdef block and the enum values are recreated as magic numbers just like the log levels for other platforms. --- src/stlink-lib/logging.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index a5eef9e17..744f1759d 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -66,12 +66,25 @@ int ugly_log(int level, const char *tag, const char *format, ...) { * - LIBUSB_LOG_LEVEL_DEBUG (4) : debug and informational messages are printed to stderr */ int ugly_libusb_log_level(enum ugly_loglevel v) { +#if __FreeBSD__ + // FreeBSD includes its own reimplementation of libusb. + // Its libusb_set_debug() function expects a lib_debug_level + // instead of a lib_log_level and is verbose enough to drown out + // all other output. switch (v) { - case UDEBUG: return(4); - case UINFO: return(3); - case UWARN: return(2); - case UERROR: return(1); + case UDEBUG: return (3); // LIBUSB_DEBUG_FUNCTION + LIBUSB_DEBUG_TRANSFER + case UINFO: return (1); // LIBUSB_DEBUG_FUNCTION only + case UWARN: return (0); // LIBUSB_DEBUG_NO + case UERROR: return (0); // LIBUSB_DEBUG_NO } - - return(2); + return (0); +#else + switch (v) { + case UDEBUG: return (4); + case UINFO: return (3); + case UWARN: return (2); + case UERROR: return (1); + } + return (2); +#endif } From 44c7de765fdae723c5e3fda1268f5df5f4587b7b Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 21 Jun 2020 13:23:44 +0100 Subject: [PATCH 0982/1435] Update d/copyright to remove GPL-2+ stanza about flashloaders The 2 loaders were rewritten from scratch --- debian/copyright | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/debian/copyright b/debian/copyright index cf13a5b4f..98af5a9d0 100644 --- a/debian/copyright +++ b/debian/copyright @@ -153,25 +153,3 @@ License: BSD-3-clause THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -Files: flashloaders/stm32l0x.s - flashloaders/stm32lx.s -Copyright: 2010 Spencer Oliver - 2011 Øyvind Harboe - 2011 Clement Burin des Roziers -License: GPL-2+ - This package is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - . - This package is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - . - You should have received a copy of the GNU General Public License - along with this program. If not, see - . - On Debian systems, the complete text of the GNU General - Public License version 2 can be found in "/usr/share/common-licenses/GPL-2". From 1195dae9e549fe0b474fe11a2b58bfcb2a31dab5 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 21 Jun 2020 13:24:37 +0100 Subject: [PATCH 0983/1435] Update upstream URLs for new Github org --- debian/control | 2 +- debian/copyright | 2 +- debian/watch | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/debian/control b/debian/control index 7172583e9..3ac6af91f 100644 --- a/debian/control +++ b/debian/control @@ -5,7 +5,7 @@ Build-Depends: debhelper-compat (= 12), cmake (>= 3.4.2), libusb-1.0-0-dev, libg Standards-Version: 4.5.0 Rules-Requires-Root: no Section: electronics -Homepage: https://github.com/texane/stlink +Homepage: https://github.com/stlink-org/stlink Vcs-Git: https://github.com/bluca/stlink.git -b debian Vcs-Browser: https://github.com/bluca/stlink diff --git a/debian/copyright b/debian/copyright index 98af5a9d0..1a0febd9c 100644 --- a/debian/copyright +++ b/debian/copyright @@ -1,7 +1,7 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink Upstream-Contact: Andrew 'Necromant' Andrianov -Source: https://github.com/texane/stlink +Source: https://github.com/stlink-org/stlink Comment: Upstream tarball has been repackaged to remove binary OSX kernel drivers that are of unknown license and of no use to Debian. Files-Excluded: stlinkv1_macos_driver diff --git a/debian/watch b/debian/watch index 45fece19b..6eb6b78d6 100644 --- a/debian/watch +++ b/debian/watch @@ -1,3 +1,3 @@ version=3 opts=dversionmangle=s/\+ds$//,repacksuffix=+ds,filenamemangle=s/.+\/v?(\d\S+)\.tar\.gz/stlink-$1\.tar\.gz/ \ - https://github.com/texane/stlink/tags .*/v?(\d\S+)\.tar\.gz + https://github.com/stlink-org/stlink/tags .*/v?(\d\S+)\.tar\.gz From 9fd796c0ffebe746b4383382161ee946c49889e6 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 21 Jun 2020 13:32:09 +0100 Subject: [PATCH 0984/1435] Patch CMake's hard-coded define of XML gui file location Closes: #963219 --- debian/patches/guipath.patch | 11 +++++++++++ debian/patches/series | 1 + 2 files changed, 12 insertions(+) create mode 100644 debian/patches/guipath.patch create mode 100644 debian/patches/series diff --git a/debian/patches/guipath.patch b/debian/patches/guipath.patch new file mode 100644 index 000000000..d3effc92b --- /dev/null +++ b/debian/patches/guipath.patch @@ -0,0 +1,11 @@ +--- a/src/stlink-gui/CMakeLists.txt ++++ b/src/stlink-gui/CMakeLists.txt +@@ -32,7 +32,7 @@ + add_executable(stlink-gui ${GUI_SOURCES}) + install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_BINDIR}) + set_target_properties(stlink-gui PROPERTIES +- COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin") ++ COMPILE_DEFINITIONS STLINK_UI_DIR="/usr/share/stlink") + target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) + install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) + diff --git a/debian/patches/series b/debian/patches/series new file mode 100644 index 000000000..1fdcf9977 --- /dev/null +++ b/debian/patches/series @@ -0,0 +1 @@ +guipath.patch From a741f41552927bae5580c06ae63dfe674765a5a6 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 21 Jun 2020 13:41:52 +0100 Subject: [PATCH 0985/1435] Update changelog for 1.6.1+ds-2 release --- debian/changelog | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/debian/changelog b/debian/changelog index 26f17b1fb..f1265ee32 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,12 @@ +stlink (1.6.1+ds-2) unstable; urgency=medium + + * Update d/copyright to remove GPL-2+ stanza about flashloaders + * Update upstream URLs for new Github org + * Patch CMake's hard-coded define of XML gui file location (Closes: + #963219) + + -- Luca Boccassi Sun, 21 Jun 2020 13:41:37 +0100 + stlink (1.6.1+ds-1) unstable; urgency=medium * Merge tag 'v1.6.1' into debian From ff263131cf0d00657c308402762cdd591d313d5e Mon Sep 17 00:00:00 2001 From: Jan Bramkamp Date: Sun, 21 Jun 2020 16:40:51 +0200 Subject: [PATCH 0986/1435] Use #ifdef instead of #if --- src/stlink-lib/logging.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index 744f1759d..ce0a2baab 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -66,7 +66,7 @@ int ugly_log(int level, const char *tag, const char *format, ...) { * - LIBUSB_LOG_LEVEL_DEBUG (4) : debug and informational messages are printed to stderr */ int ugly_libusb_log_level(enum ugly_loglevel v) { -#if __FreeBSD__ +#ifdef __FreeBSD__ // FreeBSD includes its own reimplementation of libusb. // Its libusb_set_debug() function expects a lib_debug_level // instead of a lib_log_level and is verbose enough to drown out From c1ea72d842702160173504f4e5869b55b8e986d7 Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Thu, 25 Jun 2020 10:48:51 +0200 Subject: [PATCH 0987/1435] Add support for writing option bytes to the Nucleo 144 STM32F767ZI. This adds --area=option_boot_add, --area=optcr and --area=optcr1 --- include/stlink.h | 14 +- include/stlink/tools/flash.h | 2 +- include/stm32.h | 1 + src/chipid.c | 14 +- src/common.c | 560 +++++++++++++++++++++++++++++++++-- src/flash_loader.c | 20 +- src/tools/flash.c | 131 +++++--- src/tools/flash_opts.c | 110 +++++-- src/usb.c | 1 + 9 files changed, 750 insertions(+), 103 deletions(-) diff --git a/include/stlink.h b/include/stlink.h index c87c6b173..c96cf2ef9 100644 --- a/include/stlink.h +++ b/include/stlink.h @@ -120,7 +120,8 @@ enum stlink_flash_type { STLINK_FLASH_TYPE_UNKNOWN = 0, STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */ STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank, apparently */ - STLINK_FLASH_TYPE_F4, // used by f2, f4, f7 */ + STLINK_FLASH_TYPE_F4, // used by f2, f4 */ + STLINK_FLASH_TYPE_F7, STLINK_FLASH_TYPE_L0, // l0, l1 */ STLINK_FLASH_TYPE_L4, // l4, l4+ */ STLINK_FLASH_TYPE_G0, @@ -146,8 +147,8 @@ struct stlink_reg { typedef uint32_t stm32_addr_t; typedef struct flash_loader { -stm32_addr_t loader_addr; // loader sram addr -stm32_addr_t buf_addr; // buffer sram address + stm32_addr_t loader_addr; // loader sram addr + stm32_addr_t buf_addr; // buffer sram address } flash_loader_t; typedef struct _cortex_m3_cpuid_ { @@ -288,7 +289,14 @@ int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr int stlink_load_device_params(stlink_t *sl); int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); +int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); +int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte); +int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte); + int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); +int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); +int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_control_register); +int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_control_register1); int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); diff --git a/include/stlink/tools/flash.h b/include/stlink/tools/flash.h index a912a14aa..e5b4d2572 100644 --- a/include/stlink/tools/flash.h +++ b/include/stlink/tools/flash.h @@ -11,7 +11,7 @@ enum flash_cmd {FLASH_CMD_NONE = 0, FLASH_CMD_WRITE = 1, FLASH_CMD_READ = 2, FLASH_CMD_ERASE = 3, CMD_RESET = 4}; enum flash_format {FLASH_FORMAT_BINARY = 0, FLASH_FORMAT_IHEX = 1}; -enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1,FLASH_OTP = 2, FLASH_OPTION_BYTES = 3}; +enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1, FLASH_OTP = 2, FLASH_OPTION_BYTES = 3, FLASH_OPTION_BYTES_BOOT_ADD = 4, FLASH_OPTCR = 5, FLASH_OPTCR1 = 6}; struct flash_opts { enum flash_cmd cmd; diff --git a/include/stm32.h b/include/stm32.h index c71718653..be5bb5bc7 100644 --- a/include/stm32.h +++ b/include/stm32.h @@ -20,5 +20,6 @@ #define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) #define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) #endif /* STM32_H */ diff --git a/src/chipid.c b/src/chipid.c index fcc1c55eb..abddb7dc5 100644 --- a/src/chipid.c +++ b/src/chipid.c @@ -6,12 +6,14 @@ static const struct stlink_chipid_params devices[] = { //RM0410 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F7XXXX, .description = "F76xxx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 45.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, //! "System memory" starting address from - .bootrom_size = 0xEDC0 //! @todo "System memory" byte size in hex from + .flash_type = STLINK_FLASH_TYPE_F7, + .flash_size_reg = 0x1ff0f442, // section 45.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x80000, // "SRAM" byte size in hex from + .bootrom_base = 0x00200000, //! "System memory" starting address from + .bootrom_size = 0xEDC0, //! @todo "System memory" byte size in hex from + .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 + .option_size = 0x20 }, { //RM0385 and DS10916 document was used to find these paramaters diff --git a/src/common.c b/src/common.c index e8f7cebc6..0c3b0fe69 100644 --- a/src/common.c +++ b/src/common.c @@ -236,6 +236,33 @@ #define FLASH_OBR_OFF ((uint32_t) 0x1c) #define FLASH_WRPR_OFF ((uint32_t) 0x20) +//STM32F7 +#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) +#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) +#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) +#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) +#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) +#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) +#define FLASH_F7_OPTCR_LOCK 0 +#define FLASH_F7_OPTCR_START 1 +#define FLASH_F7_CR_STRT 16 +#define FLASH_F7_CR_LOCK 31 +#define FLASH_F7_CR_SER 1 +#define FLASH_F7_CR_SNB 3 +#define FLASH_F7_CR_SNB_MASK 0xf8 +#define FLASH_F7_SR_BSY 16 +#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ +#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ +#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ +#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ +#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ +#define FLASH_F7_SR_EOP 0 /* End of operation */ +#define FLASH_F7_OPTCR1_BOOT_ADD0 0 +#define FLASH_F7_OPTCR1_BOOT_ADD1 16 + +#define FLASH_F7_SR_ERROR_MASK ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | (1 << FLASH_F7_SR_OP_ERR)) + //STM32F4 #define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) #define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) @@ -337,6 +364,8 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) reg = FLASH_F4_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_F7) + reg = FLASH_F7_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) reg = STM32L4_FLASH_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || @@ -377,6 +406,9 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; @@ -414,6 +446,8 @@ static void unlock_flash(stlink_t *sl) { key_reg = FLASH_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { key_reg = FLASH_F4_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + key_reg = FLASH_F7_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; flash_key1 = FLASH_L0_PEKEY1; @@ -462,6 +496,9 @@ static void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; @@ -506,6 +543,10 @@ static bool is_flash_option_locked(stlink_t *sl) { optcr_reg = FLASH_F4_OPTCR; optlock_shift = FLASH_F4_OPTCR_LOCK; break; + case STLINK_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; case STLINK_FLASH_TYPE_L0: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; @@ -551,6 +592,10 @@ static int lock_flash_option(stlink_t *sl) { optcr_reg = FLASH_F4_OPTCR; optlock_shift = FLASH_F4_OPTCR_LOCK; break; + case STLINK_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; case STLINK_FLASH_TYPE_L0: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; @@ -599,6 +644,9 @@ static int unlock_flash_option(stlink_t *sl) case STLINK_FLASH_TYPE_F4: optkey_reg = FLASH_F4_OPT_KEYR; break; + case STLINK_FLASH_TYPE_F7: + optkey_reg = FLASH_F7_OPT_KEYR; + break; case STLINK_FLASH_TYPE_L0: optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; optkey1 = FLASH_L0_OPTKEY1; @@ -649,6 +697,9 @@ static void set_flash_cr_pg(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + x |= 1 << FLASH_CR_PG; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; @@ -673,6 +724,8 @@ static void clear_flash_cr_pg(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) cr_reg = FLASH_F4_CR; + else if (sl->flash_type == STLINK_FLASH_TYPE_F7) + cr_reg = FLASH_F7_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_L4) cr_reg = STM32L4_FLASH_CR; else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || @@ -730,6 +783,10 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); @@ -786,6 +843,9 @@ static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_mer = 1 << FLASH_CR_MER; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); @@ -805,6 +865,9 @@ static void set_flash_cr_strt(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_strt = 1 << FLASH_F4_CR_STRT; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_strt = 1 << FLASH_F7_CR_STRT; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_strt = 1 << STM32L4_FLASH_CR_STRT; @@ -842,6 +905,8 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { sr_reg = STM32L4_FLASH_SR; } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || @@ -873,6 +938,8 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { sr_busy_shift = FLASH_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { sr_busy_shift = FLASH_F4_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_busy_shift = FLASH_F7_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { sr_busy_shift = STM32L4_FLASH_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || @@ -919,17 +986,20 @@ static int check_flash_error(stlink_t *sl) { uint32_t res = 0; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - res = read_flash_sr(sl) & FLASH_SR_ERROR_MASK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - res = read_flash_sr(sl) & STM32Gx_FLASH_SR_ERROR_MASK; - break; - case STLINK_FLASH_TYPE_L0: - res = read_flash_sr(sl) & STM32L0_FLASH_SR_ERROR_MASK; - default: - break; + case STLINK_FLASH_TYPE_F0: + res = read_flash_sr(sl) & FLASH_SR_ERROR_MASK; + break; + case STLINK_FLASH_TYPE_F7: + res = read_flash_sr(sl) & FLASH_F7_SR_ERROR_MASK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + res = read_flash_sr(sl) & STM32Gx_FLASH_SR_ERROR_MASK; + break; + case STLINK_FLASH_TYPE_L0: + res = read_flash_sr(sl) & STM32L0_FLASH_SR_ERROR_MASK; + default: + break; } if (res) { @@ -1311,13 +1381,13 @@ int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { ret = sl->backend->read_debug32(sl, addr, data); if (!ret) - DLOG("*** stlink_read_debug32 %x is %#x\n", *data, addr); + DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); return ret; } int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { - DLOG("*** stlink_write_debug32 %x to %#x\n", data, addr); + DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); return sl->backend->write_debug32(sl, addr, data); } @@ -1522,9 +1592,11 @@ void stlink_print_data(stlink_t * sl) { fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); */ } - DLOG(" %02x", (unsigned int) sl->q_buf[i]); + //DLOG(" %02x", (unsigned int) sl->q_buf[i]); + fprintf(stderr, " %02x", (unsigned int) sl->q_buf[i]); } - DLOG("\n\n"); + //DLOG("\n\n"); + fprintf(stderr, "\n"); } /* memory mapped file */ @@ -1913,7 +1985,7 @@ static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg* the_ int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size) { /* read size bytes from addr to file */ - + ILOG("read from address %#010x size %d\n", addr, size); int error; int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); @@ -2044,6 +2116,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr){ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if (sl->flash_type == STLINK_FLASH_TYPE_F4 || + sl->flash_type == STLINK_FLASH_TYPE_F7 || sl->flash_type == STLINK_FLASH_TYPE_L4) { /* wait for ongoing op to finish */ wait_flash_busy(sl); @@ -2487,10 +2560,12 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t if (eraseonly) return 0; - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4)) { /* todo: check write operation */ - ILOG("Starting Flash write for F2/F4/L4\n"); + ILOG("Starting Flash write for F2/F4/F7/L4\n"); /* flash loader initialization */ if (stlink_flash_loader_init(sl, &fl) == -1) { ELOG("stlink_flash_loader_init() == -1\n"); @@ -3117,13 +3192,62 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t* base, stm32_addr_ return ret; } +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { + uint32_t option_byte; + int ret = 0; + + //(void) addr; + //(void) len; + + ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t*) (base), addr); + write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); + ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); + + if ( addr == 0 ) { + addr = FLASH_F7_OPTCR; + ILOG("No address provided, using %#10x\n", addr); + } + + if ( addr == FLASH_F7_OPTCR ) { + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); + } else if ( addr == FLASH_F7_OPTCR1 ) { + // Read FLASH_F7_OPTCR + uint32_t oldvalue; + stlink_read_debug32(sl, FLASH_F7_OPTCR, &oldvalue); + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_byte); + // Write FLASH_F7_OPTCR lock and start address + stlink_write_debug32(sl, FLASH_F7_OPTCR, (oldvalue & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); + } else { + WLOG("WIP: write %#010x to address %#010x\n", option_byte, addr); + stlink_write_debug32(sl, addr, option_byte); + } + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t*) base, addr); + + /* option bytes are reloaded at reset only, no obl. */ + + return ret; +} + /** * Read option bytes * @param sl * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) { +int stlink_read_option_control_register_Gx(stlink_t *sl, uint32_t* option_byte) { return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); } @@ -3133,19 +3257,106 @@ int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) { * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { +int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) { + return stlink_read_option_control_register_Gx(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f2(stlink_t *sl, uint32_t* option_byte) { return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); } +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { + return stlink_read_option_control_register_f2(sl, option_byte); +} + /** * Read option bytes * @param sl * @param option_byte value to read * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { +int stlink_read_option_control_register_f4(stlink_t *sl, uint32_t* option_byte) { return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); } + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { + return stlink_read_option_control_register_f4(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f7(stlink_t *sl, uint32_t* option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); + return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t* option_byte) { + DLOG("@@@@ Read option control register 1 byte from %#10x\n", FLASH_F7_OPTCR1); + return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t* option_byte) { + DLOG("@@@@ Read option byte boot address\n"); + return stlink_read_option_control_register1_f7(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + * + * Since multiple bytes can be read, we read and print all but one here + * and then return the last one just like other devices + */ +int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t* option_byte) { + int err = -1; + for (uint8_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { + err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), option_byte); + if (err == -1) { + return err; + } else { + printf("%08x\n", *option_byte); + } + } + + return stlink_read_debug32(sl, sl->option_base + (sl->option_size / 4 - 1) * sizeof(uint32_t), option_byte); +} + /** * Read first option bytes * @param sl @@ -3153,9 +3364,43 @@ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { * @return 0 on success, -ve on failure. */ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { + DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); return stlink_read_debug32(sl, sl->option_base, option_byte); } +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +//int stlink_read_option_bytes_boot_add_generic(stlink_t *sl, uint32_t* option_byte) { +// DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); +// return stlink_read_debug32(sl, sl->option_base, option_byte); +//} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +//int stlink_read_option_control_register_generic(stlink_t *sl, uint32_t* option_byte) { +// DLOG("@@@@ Read option control register byte from %#10x\n", sl->option_base); +// return stlink_read_debug32(sl, sl->option_base, option_byte); +//} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +//int stlink_read_option_control_register1_generic(stlink_t *sl, uint32_t* option_byte) { +// DLOG("@@@@ Read option control register 1 byte from %#10x\n", sl->option_base); +// return stlink_read_debug32(sl, sl->option_base, option_byte); +//} + /** * Read option bytes * @param sl @@ -3174,6 +3419,8 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) return stlink_read_option_bytes_f2(sl, option_byte); case STLINK_CHIPID_STM32_F446: return stlink_read_option_bytes_f4(sl, option_byte); + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_bytes_f7(sl, option_byte); case STLINK_CHIPID_STM32_G0_CAT1: case STLINK_CHIPID_STM32_G0_CAT2: case STLINK_CHIPID_STM32_G4_CAT2: @@ -3184,6 +3431,72 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) } } +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte) +{ + if (sl->option_base == 0) { + ELOG("Option bytes boot address read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_bytes_boot_add_f7(sl, option_byte); + default: + return -1; + //return stlink_read_option_bytes_boot_add_generic(sl, option_byte); + } +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte) +{ + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_control_register_f7(sl, option_byte); + default: + return -1; + //return stlink_read_option_control_register_generic(sl, option_byte); + } +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte) +{ + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_control_register1_f7(sl, option_byte); + default: + return -1; + //return stlink_read_option_control_register1_generic(sl, option_byte); + } +} + /** * Write option bytes * @param sl @@ -3192,7 +3505,7 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) */ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { - WLOG("About to write option byte %#10x to target.\n", option_byte); + WLOG("About to write option byte %#10x to %#10x.\n", option_byte, sl->option_base); return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *) &option_byte, 4); } @@ -3212,6 +3525,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui return -1; } + if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { ELOG("Option bytes start address out of Option bytes range\n"); return -1; @@ -3238,6 +3552,9 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui case STLINK_FLASH_TYPE_F4: ret = stlink_write_option_bytes_f4(sl, base, addr, len); break; + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_f7(sl, base, addr, len); + break; case STLINK_FLASH_TYPE_L0: ret = stlink_write_option_bytes_l0(sl, base, addr, len); break; @@ -3255,8 +3572,203 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui if (ret) ELOG("Flash option write failed!\n"); - else - ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + else + ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option_control_register) { + int ret = 0; + + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", option_control_register, FLASH_F7_OPTCR); + //write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); + //ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, FLASH_F7_OPTCR1); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t option_control_register1) { + int ret = 0; + + ILOG("Asked to write option control register 1 %#010x to %#010x.\n", option_control_register1, FLASH_F7_OPTCR1); + //write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); + //ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + uint32_t current_control_register_value; + stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); + + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); + stlink_write_debug32(sl, FLASH_F7_OPTCR, (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, FLASH_F7_OPTCR1); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_add) { + ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); + return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add) +{ + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); + break; + default: + ELOG("Option bytes boot address writing is currently not implemented for connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_control_register) +{ + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_control_register_f7(sl, option_control_register); + break; + default: + ELOG("Option control register writing is currently not implemented for connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register %#010x!\n", option_control_register); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_control_register1) +{ + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_control_register1_f7(sl, option_control_register1); + break; + default: + ELOG("Option control register 1 writing is currently not implemented for connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); /* Re-lock flash. */ lock_flash_option(sl); diff --git a/src/flash_loader.c b/src/flash_loader.c index a2c5879ce..b6058cd0e 100644 --- a/src/flash_loader.c +++ b/src/flash_loader.c @@ -176,19 +176,19 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { - size_t size = 0; + size_t size = 0; - /* allocate the loader in sram */ - if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { - WLOG("Failed to write flash loader to sram!\n"); - return -1; - } + /* allocate the loader in sram */ + if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { + WLOG("Failed to write flash loader to sram!\n"); + return -1; + } - /* allocate a one page buffer in sram right after loader */ - fl->buf_addr = fl->loader_addr + (uint32_t) size; - ILOG("Successfully loaded flash loader in sram\n"); + /* allocate a one page buffer in sram right after loader */ + fl->buf_addr = fl->loader_addr + (uint32_t) size; + ILOG("Successfully loaded flash loader in sram\n"); - return 0; + return 0; } static int loader_v_dependent_assignment(stlink_t *sl, diff --git a/src/tools/flash.c b/src/tools/flash.c index 3a83daf8a..9c4e20dff 100644 --- a/src/tools/flash.c +++ b/src/tools/flash.c @@ -28,15 +28,23 @@ static void cleanup(int signum) { static void usage(void) { - puts("command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] {read|write} [addr] [size]"); + puts("command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] erase"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); puts(" , and : Use hex format."); puts(" : Use decimal, octal or hex (prefix 0xXXX) format, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); puts(" : Can be 'binary' (default) or 'ihex', although must be specified for binary format only."); + puts(" : Can be 'main' (default), 'system', 'otp', 'optcr', 'optcr1', 'option' or 'option_boot_add'"); puts("print tool version info: ./st-flash [--version]"); - puts("example write option byte: ./st-flash --debug --reset --area=option write 0xXXXXXXXX"); - puts("example read option byte: ./st-flash --debug --reset --area=option read > option_byte"); + puts("example read option byte: ./st-flash --area=option read [path] [size]"); + puts("example write option byte: ./st-flash --area=option write 0xXXXXXXXX"); + puts("On selected targets:"); + puts("example read boot_add option byte: ./st-flash --area=option_boot_add read"); + puts("example write boot_add option byte: ./st-flash --area=option_boot_add write 0xXXXXXXXX"); + puts("example read option control register byte: ./st-flash --area=optcr read"); + puts("example write option control register1 byte: ./st-flash --area=optcr write 0xXXXXXXXX"); + puts("example read option control register1 byte: ./st-flash --area=optcr1 read"); + puts("example write option control register1 byte: ./st-flash --area=optcr1 write 0xXXXXXXXX"); } int main(int ac, char** av) @@ -54,7 +62,7 @@ int main(int ac, char** av) return -1; } - printf("st-flash %s\n", STLINK_VERSION); + ILOG("st-flash %s\n", STLINK_VERSION); sl = stlink_open_usb(o.log_level, 1, (char *)o.serial, o.freq); @@ -62,7 +70,7 @@ int main(int ac, char** av) return -1; } - if (sl->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { + if (STLINK_FLASH_TYPE_UNKNOWN == sl->flash_type) { printf("Failed to connect to target\n"); return -1; } @@ -80,14 +88,14 @@ int main(int ac, char** av) signal(SIGTERM, &cleanup); signal(SIGSEGV, &cleanup); - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { + if (STLINK_DEV_DFU_MODE == stlink_current_mode(sl)) { if (stlink_exit_dfu_mode(sl)) { printf("Failed to exit DFU mode\n"); goto on_error; } } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { + if (STLINK_DEV_DEBUG_MODE != stlink_current_mode(sl)) { if (stlink_enter_swd_mode(sl)) { printf("Failed to enter SWD mode\n"); goto on_error; @@ -109,7 +117,7 @@ int main(int ac, char** av) } // Disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 - if (sl->chip_id == STLINK_CHIPID_STM32_F4) + if (STLINK_CHIPID_STM32_F4 == sl->chip_id) { memset(sl->q_buf,0,4); for (int i=0;i<8;i++) { @@ -131,19 +139,20 @@ int main(int ac, char** av) goto on_error; } - if (o.cmd == FLASH_CMD_WRITE) /* write */ + if (FLASH_CMD_WRITE == o.cmd) // write { size_t size = 0; - if (o.format == FLASH_FORMAT_IHEX) { + if (FLASH_FORMAT_IHEX == o.format) { err = stlink_parse_ihex(o.filename, stlink_get_erased_pattern(sl), &mem, &size, &o.addr); if (err == -1) { printf("Cannot parse %s as Intel-HEX file\n", o.filename); goto on_error; } } + if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { - if (o.format == FLASH_FORMAT_IHEX) + if (FLASH_FORMAT_IHEX == o.format) err = stlink_mwrite_flash(sl, mem, (uint32_t)size, o.addr); else err = stlink_fwrite_flash(sl, o.filename, o.addr); @@ -155,7 +164,7 @@ int main(int ac, char** av) } else if ((o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { - if (o.format == FLASH_FORMAT_IHEX) + if (FLASH_FORMAT_IHEX == o.format) err = stlink_mwrite_sram(sl, mem, (uint32_t)size, o.addr); else err = stlink_fwrite_sram(sl, o.filename, o.addr); @@ -174,25 +183,39 @@ int main(int ac, char** av) goto on_error; } } - else if (o.area == FLASH_OPTION_BYTES){ + else if (FLASH_OPTION_BYTES == o.area) { if (o.val == 0) { printf("attempting to set option byte to 0, abort.\n"); goto on_error; - } + } err = stlink_write_option_bytes32(sl, o.val); - if (err == -1) - { + if (err == -1) { printf("stlink_write_option_bytes32() == -1\n"); goto on_error; } } - else { + else if (FLASH_OPTCR == o.area) { + DLOG("@@@@ Write %d (%0#10x) to option control register\n", o.val, o.val); + + err = stlink_write_option_control_register32(sl, o.val); + } + else if (FLASH_OPTCR1 == o.area) { + DLOG("@@@@ Write %d (%0#10x) to option control register 1\n", o.val, o.val); + + err = stlink_write_option_control_register1_32(sl, o.val); + } + else if (FLASH_OPTION_BYTES_BOOT_ADD == o.area) { + DLOG("@@@@ Write %d (%0#10x) to option bytes boot address\n", o.val, o.val); + + err = stlink_write_option_bytes_boot_add32(sl, o.val); + } + else { err = -1; printf("Unknown memory region\n"); goto on_error; } - } else if (o.cmd == FLASH_CMD_ERASE) + } else if (FLASH_CMD_ERASE == o.cmd) { err = stlink_erase_flash_mass(sl); if (err == -1) @@ -200,7 +223,7 @@ int main(int ac, char** av) printf("stlink_erase_flash_mass() == -1\n"); goto on_error; } - } else if (o.cmd == CMD_RESET) + } else if (CMD_RESET == o.cmd) { if (sl->version.stlink_v > 1) { if (stlink_jtag_reset(sl, 2)) { @@ -216,35 +239,69 @@ int main(int ac, char** av) } else /* read */ { - if(o.area == FLASH_OPTION_BYTES){ - uint32_t option_byte; - err = stlink_read_option_bytes32(sl, &option_byte); - if (err == -1) { - printf("could not read option bytes (%d)\n", err); - goto on_error; - } else { - printf("%x\n",option_byte); - } - }else{ - if ((o.addr >= sl->flash_base) && (o.size == 0) && - (o.addr < sl->flash_base + sl->flash_size)){ + if ((FLASH_MAIN_MEMORY == o.area) || (FLASH_SYSTEM_MEMORY == o.area)) { + if ((o.size == 0) && (o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { o.size = sl->flash_size; } - else if ((o.addr >= sl->sram_base) && (o.size == 0) && - (o.addr < sl->sram_base + sl->sram_size)){ + else if ((o.size == 0) && (o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { o.size = sl->sram_size; } - err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); + err = stlink_fread(sl, o.filename, FLASH_FORMAT_IHEX == o.format, o.addr, o.size); - if (err == -1) - { + if (err == -1) { printf("stlink_fread() == -1\n"); goto on_error; } + } else if (FLASH_OPTION_BYTES == o.area) { + uint8_t remaining_option_length = sl->option_size / 4; + DLOG("@@@@ Read %d (%#x) option bytes from %#10x\n", remaining_option_length, remaining_option_length, sl->option_base); + + if (NULL != o.filename) { + if (0 == o.size) { + o.size = sl->option_size; + } + err = stlink_fread(sl, o.filename, FLASH_FORMAT_IHEX == o.format, sl->option_base, o.size); + } else { + uint32_t option_byte = 0; + err = stlink_read_option_bytes32(sl, &option_byte); + if (err == -1) { + printf("could not read option bytes (%d)\n", err); + goto on_error; + } else { + printf("%08x\n", option_byte); + } + } + } else if (FLASH_OPTION_BYTES_BOOT_ADD == o.area) { + uint32_t option_byte = 0; + err = stlink_read_option_bytes_boot_add32(sl, &option_byte); + if (err == -1) { + printf("could not read option bytes boot address (%d)\n", err); + goto on_error; + } else { + printf("%08x\n",option_byte); + } + } else if (FLASH_OPTCR == o.area) { + uint32_t option_byte = 0; + err = stlink_read_option_control_register32(sl, &option_byte); + if (err == -1) { + printf("could not read option control register (%d)\n", err); + goto on_error; + } else { + printf("%08x\n",option_byte); + } + } else if (FLASH_OPTCR1 == o.area) { + uint32_t option_byte = 0; + err = stlink_read_option_control_register1_32(sl, &option_byte); + if (err == -1) { + printf("could not read option control register (%d)\n", err); + goto on_error; + } else { + printf("%08x\n",option_byte); + } } } - if (o.reset){ + if (o.reset) { if (sl->version.stlink_v > 1) stlink_jtag_reset(sl, 2); stlink_reset(sl); } diff --git a/src/tools/flash_opts.c b/src/tools/flash_opts.c index a5c9d287f..8557445e0 100644 --- a/src/tools/flash_opts.c +++ b/src/tools/flash_opts.c @@ -145,6 +145,12 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { o->area = FLASH_OTP; else if (strcmp(area, "option") == 0) o->area = FLASH_OPTION_BYTES; + else if (strcmp(area, "option_boot_add") == 0) + o->area = FLASH_OPTION_BYTES_BOOT_ADD; + else if (strcmp(area, "optcr") == 0) + o->area = FLASH_OPTCR; + else if (strcmp(area, "optcr1") == 0) + o->area = FLASH_OPTCR1; else return -1; @@ -236,19 +242,19 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { // command and (optional) device name while (ac >= 1) { if (strcmp(av[0], "erase") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = FLASH_CMD_ERASE; } else if (strcmp(av[0], "read") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = FLASH_CMD_READ; } else if (strcmp(av[0], "write") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = FLASH_CMD_WRITE; } else if (strcmp(av[0], "reset") == 0) { - if (o->cmd != FLASH_CMD_NONE) return -1; + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = CMD_RESET; } else { @@ -268,33 +274,93 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { break; case FLASH_CMD_READ: // expect filename, addr and size - if ((o->area == FLASH_OPTION_BYTES) &&(ac == 0)) break; - if (ac != 3) return invalid_args("read "); - if (ac != 3) return -1; - o->filename = av[0]; - uint32_t address; - result = get_integer_from_char_array(av[1], &address); - if (result != 0) return bad_arg ("addr"); - else o->addr = (stm32_addr_t) address; + if ((FLASH_MAIN_MEMORY == o->area) || (FLASH_SYSTEM_MEMORY == o->area)) { + if (ac != 3) return invalid_args("read "); + o->filename = av[0]; + uint32_t address; + result = get_integer_from_char_array(av[1], &address); + if (result != 0) return bad_arg ("addr"); + else o->addr = (stm32_addr_t) address; - uint32_t size; - result = get_integer_from_char_array(av[2], &size); - if (result != 0) return bad_arg ("size"); - else o->size = (size_t) size; + uint32_t size; + result = get_integer_from_char_array(av[2], &size); + if (result != 0) return bad_arg ("size"); + else o->size = (size_t) size; + break; + } + else if ((FLASH_OTP == o->area)) { + return bad_arg("TODO: otp not implemented yet"); + if (ac > 1) return invalid_args("otp read: [path]"); + if (ac > 0) o->filename = av[0]; + break; + } + else if ((FLASH_OPTION_BYTES == o->area)) { + if (ac > 2) return invalid_args("option bytes read: [path] [size]"); + if (ac > 0) o->filename = av[0]; + if (ac > 1) { + uint32_t size; + result = get_integer_from_char_array(av[1], &size); + if (result != 0) return bad_arg("option bytes read: invalid size"); + else o->size = (size_t) size; + } + break; + } + else if ((FLASH_OPTION_BYTES_BOOT_ADD == o->area)) { + if (ac > 0) return invalid_args("option bytes boot_add read"); + break; + } + else if ((FLASH_OPTCR == o->area)) { + if (ac > 0) return invalid_args("option control register read"); + break; + } + else if ((FLASH_OPTCR1 == o->area)) { + if (ac > 0) return invalid_args("option control register 1 read"); + break; + } break; case FLASH_CMD_WRITE: - if (o->area == FLASH_OPTION_BYTES){ - if (ac != 1) return -1; - + // TODO: should be boot add 0 and boot add 1 uint32 + if (FLASH_OPTION_BYTES == o->area) { // expect filename and optional address + if (ac >=1 && ac <= 2) { + o->filename = av[0]; + } + else + return invalid_args("write [addr]"); + + if (ac == 2) { + uint32_t addr; + result = get_integer_from_char_array(av[1], &addr); + if (result != 0) return bad_arg ("addr"); + else o->addr = (stm32_addr_t) addr; + } + } + else if (FLASH_OPTION_BYTES_BOOT_ADD == o->area) { // expect option bytes boot address + if (ac != 1) return invalid_args("option bytes boot_add write "); + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) return bad_arg ("val"); + else o->val = (uint32_t) val; + } + else if (FLASH_OPTCR == o->area) { // expect option control register value + if (ac != 1) return invalid_args("option control register write "); + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) return bad_arg ("val"); + else o->val = (uint32_t) val; + } + else if (FLASH_OPTCR1 == o->area) { // expect option control register 1 value + if (ac != 1) return invalid_args("option control register 1 write "); + uint32_t val; result = get_integer_from_char_array(av[0], &val); if (result != 0) return bad_arg ("val"); else o->val = (uint32_t) val; - } - else if (o->format == FLASH_FORMAT_BINARY) { // expect filename and addr + else if (FLASH_FORMAT_BINARY == o->format) { // expect filename and addr if (ac != 2) return invalid_args("write "); o->filename = av[0]; uint32_t addr; @@ -302,7 +368,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { if (result != 0) return bad_arg ("addr"); else o->addr = (stm32_addr_t) addr; } - else if (o->format == FLASH_FORMAT_IHEX) { // expect filename + else if (FLASH_FORMAT_IHEX == o->format) { // expect filename if (ac != 1) return invalid_args("write "); o->filename = av[0]; } diff --git a/src/usb.c b/src/usb.c index b986aed57..b492afed7 100644 --- a/src/usb.c +++ b/src/usb.c @@ -655,6 +655,7 @@ int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_READMEM_32BIT; + DLOG("using address %#010x\n", addr); write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); size = send_recv(slu, 1, cmd, slu->cmd_len, data, len); From 972ecf8d960919d0c9433c73b809ddcc701f847b Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Thu, 25 Jun 2020 12:40:15 +0200 Subject: [PATCH 0988/1435] Continue merging upstream --- src/common.c | 3 +- src/st-flash/flash.c | 5 +- src/st-flash/flash_opts.c | 417 ++++++++++++++++------------- src/stlink-lib/chipid.c | 2 +- src/stlink-lib/flash_loader.c | 486 +++++++++++++++++----------------- 5 files changed, 481 insertions(+), 432 deletions(-) diff --git a/src/common.c b/src/common.c index 1703dee76..58e67d447 100644 --- a/src/common.c +++ b/src/common.c @@ -3637,8 +3637,9 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui if (ret) { ELOG("Flash option write failed!\n"); - else + } else { ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + } /* Re-lock flash. */ lock_flash_option(sl); diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 6d70fc5e6..128b8acc0 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -140,7 +140,6 @@ int main(int ac, char** av) { { size_t size = 0; if (FLASH_FORMAT_IHEX == o.format) { - if (o.format == FLASH_FORMAT_IHEX) { err = stlink_parse_ihex(o.filename, stlink_get_erased_pattern(sl), &mem, &size, &o.addr); if (err == -1) { @@ -150,7 +149,7 @@ int main(int ac, char** av) { } if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { - if (FLASH_FORMAT_IHEX == o.format) + if (FLASH_FORMAT_IHEX == o.format) { err = stlink_mwrite_flash(sl, mem, (uint32_t)size, o.addr); } else { err = stlink_fwrite_flash(sl, o.filename, o.addr); @@ -162,7 +161,7 @@ int main(int ac, char** av) { } } else if ((o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { - if (FLASH_FORMAT_IHEX == o.format) + if (FLASH_FORMAT_IHEX == o.format) { err = stlink_mwrite_sram(sl, mem, (uint32_t)size, o.addr); } else { err = stlink_fwrite_sram(sl, o.filename, o.addr); diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 6d1940675..8557445e0 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -2,12 +2,11 @@ #include #include -#include "flash.h" +#include static bool starts_with(const char * str, const char * prefix) { size_t n = strlen(prefix); - - if (strlen(str) < n) { return(false); } + if (strlen(str) < n) return false; return (0 == strncmp(str, prefix, n)); } @@ -20,28 +19,37 @@ static int get_long_integer_from_char_array (const char *const str, uint64_t *re uint64_t value; char *tail; - if (starts_with (str, "0x") || starts_with (str, "0X")) { // hexadecimal + // hexadecimal + if (starts_with (str, "0x") || starts_with (str, "0X")) { value = strtoul (str + 2, &tail, 16); - } else if (starts_with (str, "0b") || starts_with (str, "0B")) { // binary + } + // binary + else if (starts_with (str, "0b") || starts_with (str, "0B")) { value = strtoul (str + 2, &tail, 2); - } else if (starts_with (str, "0")) { // octal + } + // octal + else if (starts_with (str, "0")) { value = strtoul (str + 1, &tail, 8); - } else { // decimal + } + // decimal + else { value = strtoul (str, &tail, 10); } if (((tail[0] == 'k') || (tail[0] == 'K')) && (tail[1] == '\0')) { value = value * 1024; - } else if (((tail[0] == 'm') || (tail[0] == 'M')) && (tail[1] == '\0')) { + } + else if (((tail[0] == 'm') || (tail[0] == 'M')) && (tail[1] == '\0')) { value = value * 1024 * 1024; - } else if (tail[0] == '\0') { - /* value not changed */ - } else { - return(-1); } - + else if (tail[0] == '\0') { + // value not change + } + else { + return -1; + } *read_value = value; - return(0); + return 0; } // support positive integer from 0 to UINT32_MAX @@ -51,26 +59,28 @@ static int get_long_integer_from_char_array (const char *const str, uint64_t *re static int get_integer_from_char_array (const char *const str, uint32_t *read_value) { uint64_t value; int result = get_long_integer_from_char_array (str, &value); - if (result != 0) { - return(result); - } else if (value > UINT32_MAX) { - fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, cannot convert to int32_t\n"); - return(-1); - } else { + return result; + } + else if (value > UINT32_MAX) { + fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, \ +cannot convert to int32_t\n"); + return -1; + } + else { *read_value = (uint32_t)value; - return(0); + return 0; } } static int invalid_args(const char *expected) { fprintf(stderr, "*** Error: Expected args for this command: %s\n", expected); - return(-1); + return -1; } static int bad_arg(const char *arg) { fprintf(stderr, "*** Error: Invalid value for %s\n", arg); - return(-1); + return -1; } int flash_get_opts(struct flash_opts* o, int ac, char** av) { @@ -81,177 +91,173 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { // options int result; - while (ac >= 1) { if (strcmp(av[0], "--version") == 0) { printf("v%s\n", STLINK_VERSION); exit(EXIT_SUCCESS); - } else if (strcmp(av[0], "--debug") == 0) { + } + else if (strcmp(av[0], "--debug") == 0) { o->log_level = DEBUG_LOG_LEVEL; - } else if (strcmp(av[0], "--opt") == 0) { + } + else if (strcmp(av[0], "--opt") == 0) { o->opt = ENABLE_OPT; - } else if (strcmp(av[0], "--reset") == 0) { + } + else if (strcmp(av[0], "--reset") == 0) { o->reset = 1; - } else if (strcmp(av[0], "--serial") == 0 || starts_with(av[0], "--serial=")) { + } + else if (strcmp(av[0], "--serial") == 0 || starts_with(av[0], "--serial=")) { const char * serial; - if (strcmp(av[0], "--serial") == 0) { ac--; av++; - - if (ac < 1) { return(-1); } - + if (ac < 1) return -1; serial = av[0]; - } else { + } + else { serial = av[0] + strlen("--serial="); } - - /** @todo This is not really portable, as strlen really returns size_t we need to obey - and not cast it to a signed type. */ + /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ int j = (int)strlen(serial); - int length = j / 2; // the length of the destination-array - - if (j % 2 != 0) { return(-1); } - + int length = j / 2; // the length of the destination-array + if (j % 2 != 0) return -1; for (size_t k = 0; j >= 0 && k < sizeof(o->serial); ++k, j -= 2) { char buffer[3] = {0}; memcpy(buffer, serial + j, 2); o->serial[length - k] = (uint8_t)strtol(buffer, NULL, 16); } - } else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { + } + else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { const char * area; - if (strcmp(av[0], "--area") == 0) { ac--; av++; - - if (ac < 1) { return(-1); } - + if (ac < 1) return -1; area = av[0]; - } else { + } + else { area = av[0] + strlen("--area="); } - - if (strcmp(area, "main") == 0) { + if (strcmp(area, "main") == 0) o->area = FLASH_MAIN_MEMORY; - } else if (strcmp(area, "system") == 0) { + else if (strcmp(area, "system") == 0) o->area = FLASH_SYSTEM_MEMORY; - } else if (strcmp(area, "otp") == 0) { + else if (strcmp(area, "otp") == 0) o->area = FLASH_OTP; - } else if (strcmp(area, "option") == 0) { + else if (strcmp(area, "option") == 0) o->area = FLASH_OPTION_BYTES; - } else { - return(-1); - } + else if (strcmp(area, "option_boot_add") == 0) + o->area = FLASH_OPTION_BYTES_BOOT_ADD; + else if (strcmp(area, "optcr") == 0) + o->area = FLASH_OPTCR; + else if (strcmp(area, "optcr1") == 0) + o->area = FLASH_OPTCR1; + else + return -1; - } else if (strcmp(av[0], "--freq") == 0 || starts_with(av[0], "--freq=")) { + } + else if (strcmp(av[0], "--freq") == 0 || starts_with(av[0], "--freq=")) { const char* freq; - if (strcmp(av[0], "--freq") == 0) { ac--; av++; - - if (ac < 1) { - return(-1); - } - + if (ac < 1) return -1; freq = av[0]; - } else { + } + else { freq = av[0] + strlen("--freq="); } - if (strcmp(freq, "5K") == 0 || strcmp(freq, "5k") == 0) { o->freq = 5; - } else if (strcmp(freq, "15K") == 0 || strcmp(freq, "15k") == 0) { + } + else if (strcmp(freq, "15K") == 0 || strcmp(freq, "15k") == 0) { o->freq = 15; - } else if (strcmp(freq, "25K") == 0 || strcmp(freq, "25k") == 0) { + } + else if (strcmp(freq, "25K") == 0 || strcmp(freq, "25k") == 0) { o->freq = 25; - } else if (strcmp(freq, "50K") == 0 || strcmp(freq, "50k") == 0) { + } + else if (strcmp(freq, "50K") == 0 || strcmp(freq, "50k") == 0) { o->freq = 50; - } else if (strcmp(freq, "100K") == 0 || strcmp(freq, "100k") == 0) { + } + else if (strcmp(freq, "100K") == 0 || strcmp(freq, "100k") == 0) { o->freq = 100; - } else if (strcmp(freq, "125K") == 0 || strcmp(freq, "125k") == 0) { + } + else if (strcmp(freq, "125K") == 0 || strcmp(freq, "125k") == 0) { o->freq = 125; - } else if (strcmp(freq, "240K") == 0 || strcmp(freq, "240k") == 0) { + } + else if (strcmp(freq, "240K") == 0 || strcmp(freq, "240k") == 0) { o->freq = 240; - } else if (strcmp(freq, "480K") == 0 || strcmp(freq, "480k") == 0) { + } + else if (strcmp(freq, "480K") == 0 || strcmp(freq, "480k") == 0) { o->freq = 480; - } else if (strcmp(freq, "950K") == 0 || strcmp(freq, "950k") == 0) { + } + else if (strcmp(freq, "950K") == 0 || strcmp(freq, "950k") == 0) { o->freq = 950; - } else if (strcmp(freq, "1200K") == 0 || strcmp(freq, "1200k") == 0 || - strcmp(freq, "1.2M") == 0 || strcmp(freq, "1.2m") == 0) { + } + else if (strcmp(freq, "1200K") == 0 || strcmp(freq, "1200k") == 0 || strcmp(freq, "1.2M") == 0 || strcmp(freq, "1.2m") == 0) { o->freq = 1200; - } else if (strcmp(freq, "1800K") == 0 || strcmp(freq, "1800k") == 0 || - strcmp(freq, "1.8M") == 0 || strcmp(freq, "1.8m") == 0) { + } + else if (strcmp(freq, "1800K") == 0 || strcmp(freq, "1800k") == 0 || strcmp(freq, "1.8M") == 0 || strcmp(freq, "1.8m") == 0) { o->freq = 1800; - } else if (strcmp(freq, "4000K") == 0 || strcmp(freq, "4000k") == 0 || - strcmp(freq, "4M") == 0 || strcmp(freq, "4m") == 0) { + } + else if (strcmp(freq, "4000K") == 0 || strcmp(freq, "4000k") == 0 || strcmp(freq, "4M") == 0 || strcmp(freq, "4m") == 0) { o->freq = 4000; - } else { - return(-1); } - } else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { + else + return -1; + } + else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { const char * format; - if (strcmp(av[0], "--format") == 0) { ac--; av++; - - if (ac < 1) { return(-1); } - + if (ac < 1) return -1; format = av[0]; - } else { + } + else { format = av[0] + strlen("--format="); } - - if (strcmp(format, "binary") == 0) { + if (strcmp(format, "binary") == 0) o->format = FLASH_FORMAT_BINARY; - } else if (strcmp(format, "ihex") == 0) { + else if (strcmp(format, "ihex") == 0) o->format = FLASH_FORMAT_IHEX; - } else { - return(bad_arg("format")); - } - } else if ( starts_with(av[0], "--flash=")) { + else + return bad_arg("format"); + } + else if ( starts_with(av[0], "--flash=") ) { const char *arg = av[0] + strlen("--flash="); uint32_t flash_size; result = get_integer_from_char_array(arg, &flash_size); - - if (result != 0) { - return(bad_arg ("--flash")); - } else { - o->flash_size = (size_t)flash_size; - } - } else if (strcmp(av[0], "--connect-under-reset") == 0) { - o->connect_under_reset = true; - } else { - break; // non-option found - + if (result != 0) return bad_arg ("--flash"); + else o->flash_size = (size_t) flash_size; + } + else { + break; // non-option found } ac--; av++; } - /* command and (optional) device name */ + // command and (optional) device name while (ac >= 1) { if (strcmp(av[0], "erase") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } - + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = FLASH_CMD_ERASE; - } else if (strcmp(av[0], "read") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } - + } + else if (strcmp(av[0], "read") == 0) { + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = FLASH_CMD_READ; - } else if (strcmp(av[0], "write") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } - + } + else if (strcmp(av[0], "write") == 0) { + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = FLASH_CMD_WRITE; - } else if (strcmp(av[0], "reset") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } - + } + else if (strcmp(av[0], "reset") == 0) { + if (FLASH_CMD_NONE != o->cmd) return -1; o->cmd = CMD_RESET; - } else { + } + else { break; } @@ -259,83 +265,120 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { av++; } - switch (o->cmd) { - case FLASH_CMD_NONE: // no command found - return(-1); - - case FLASH_CMD_ERASE: // no more arguments expected - - if (ac != 0) { return(-1); } - - break; - - case FLASH_CMD_READ: // expect filename, addr and size - - if ((o->area == FLASH_OPTION_BYTES) && (ac == 0)) { break; } - - if (ac != 3) { return(invalid_args("read ")); } - - if (ac != 3) { return(-1); } - - o->filename = av[0]; - uint32_t address; - result = get_integer_from_char_array(av[1], &address); - - if (result != 0) { - return(bad_arg ("addr")); - } else { - o->addr = (stm32_addr_t)address; - } - - uint32_t size; - result = get_integer_from_char_array(av[2], &size); - - if (result != 0) { - return(bad_arg ("size")); - } else { - o->size = (size_t)size; - } - - break; - - case FLASH_CMD_WRITE: - - if (o->area == FLASH_OPTION_BYTES) { - if (ac != 1) { return(-1); } + switch(o->cmd) { + case FLASH_CMD_NONE: // no command found + return -1; - uint32_t val; - result = get_integer_from_char_array(av[0], &val); + case FLASH_CMD_ERASE: // no more arguments expected + if (ac != 0) return -1; + break; - if (result != 0) { - return(bad_arg ("val")); - } else { - o->val = (uint32_t)val; + case FLASH_CMD_READ: // expect filename, addr and size + if ((FLASH_MAIN_MEMORY == o->area) || (FLASH_SYSTEM_MEMORY == o->area)) { + if (ac != 3) return invalid_args("read "); + o->filename = av[0]; + uint32_t address; + result = get_integer_from_char_array(av[1], &address); + if (result != 0) return bad_arg ("addr"); + else o->addr = (stm32_addr_t) address; + + uint32_t size; + result = get_integer_from_char_array(av[2], &size); + if (result != 0) return bad_arg ("size"); + else o->size = (size_t) size; + + break; } - - } else if (o->format == FLASH_FORMAT_BINARY) { // expect filename and addr - if (ac != 2) { return(invalid_args("write ")); } - - o->filename = av[0]; - uint32_t addr; - result = get_integer_from_char_array(av[1], &addr); - - if (result != 0) { - return(bad_arg ("addr")); - } else { - o->addr = (stm32_addr_t)addr; + else if ((FLASH_OTP == o->area)) { + return bad_arg("TODO: otp not implemented yet"); + if (ac > 1) return invalid_args("otp read: [path]"); + if (ac > 0) o->filename = av[0]; + break; } - } else if (o->format == FLASH_FORMAT_IHEX) { // expect filename - if (ac != 1) { return(invalid_args("write ")); } - - o->filename = av[0]; - } else { - return(-1); // should have been caught during format parsing - } + else if ((FLASH_OPTION_BYTES == o->area)) { + if (ac > 2) return invalid_args("option bytes read: [path] [size]"); + if (ac > 0) o->filename = av[0]; + if (ac > 1) { + uint32_t size; + result = get_integer_from_char_array(av[1], &size); + if (result != 0) return bad_arg("option bytes read: invalid size"); + else o->size = (size_t) size; + } + break; + } + else if ((FLASH_OPTION_BYTES_BOOT_ADD == o->area)) { + if (ac > 0) return invalid_args("option bytes boot_add read"); + break; + } + else if ((FLASH_OPTCR == o->area)) { + if (ac > 0) return invalid_args("option control register read"); + break; + } + else if ((FLASH_OPTCR1 == o->area)) { + if (ac > 0) return invalid_args("option control register 1 read"); + break; + } + break; - break; + case FLASH_CMD_WRITE: + // TODO: should be boot add 0 and boot add 1 uint32 + if (FLASH_OPTION_BYTES == o->area) { // expect filename and optional address + if (ac >=1 && ac <= 2) { + o->filename = av[0]; + } + else + return invalid_args("write [addr]"); + + if (ac == 2) { + uint32_t addr; + result = get_integer_from_char_array(av[1], &addr); + if (result != 0) return bad_arg ("addr"); + else o->addr = (stm32_addr_t) addr; + } + } + else if (FLASH_OPTION_BYTES_BOOT_ADD == o->area) { // expect option bytes boot address + if (ac != 1) return invalid_args("option bytes boot_add write "); + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) return bad_arg ("val"); + else o->val = (uint32_t) val; + } + else if (FLASH_OPTCR == o->area) { // expect option control register value + if (ac != 1) return invalid_args("option control register write "); + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) return bad_arg ("val"); + else o->val = (uint32_t) val; + } + else if (FLASH_OPTCR1 == o->area) { // expect option control register 1 value + if (ac != 1) return invalid_args("option control register 1 write "); + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) return bad_arg ("val"); + else o->val = (uint32_t) val; + } + else if (FLASH_FORMAT_BINARY == o->format) { // expect filename and addr + if (ac != 2) return invalid_args("write "); + o->filename = av[0]; + uint32_t addr; + result = get_integer_from_char_array(av[1], &addr); + if (result != 0) return bad_arg ("addr"); + else o->addr = (stm32_addr_t) addr; + } + else if (FLASH_FORMAT_IHEX == o->format) { // expect filename + if (ac != 1) return invalid_args("write "); + o->filename = av[0]; + } + else { + return -1; // should have been caught during format parsing + } + break; - default: break; + default: break ; } - return(0); + return 0; } diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 147b0e74e..3763587e1 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -11,7 +11,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // No flash pages .sram_size = 0x80000, // "SRAM" byte size in hex from .bootrom_base = 0x00200000, // ! "System memory" starting address from - .bootrom_size = 0xEDC0 // ! @todo "System memory" byte size in hex from + .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 .option_size = 0x20 }, diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 0e79c3c0a..b6058cd0e 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -3,210 +3,213 @@ #include #include -#include "flash_loader.h" #define FLASH_REGS_BANK2_OFS 0x40 #define FLASH_BANK2_START_ADDR 0x08080000 /* DO NOT MODIFY SOURCECODE DIRECTLY, EDIT ASSEMBLY FILES INSTEAD */ -/* flashloaders/stm32f0.s -- compiled with thumb2 */ -static const uint8_t loader_code_stm32vl[] = { - 0x16, 0x4f, 0x3c, 0x68, - 0x16, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x16, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x4f, 0xf0, 0x01, 0x07, - 0x33, 0x68, 0x3b, 0x43, - 0x33, 0x60, 0x03, 0x88, - 0x0b, 0x80, 0x4f, 0xf0, - 0x02, 0x07, 0xc0, 0x19, - 0xc9, 0x19, 0x4f, 0xf0, - 0x01, 0x07, 0x2b, 0x68, - 0x3b, 0x42, 0xfa, 0xd0, - 0x4f, 0xf0, 0x04, 0x07, - 0x3b, 0x42, 0x04, 0xd1, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xe6, 0xd1, 0x4f, 0xf0, - 0x01, 0x07, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x50, 0x00, 0x00, 0x20, - 0x54, 0x00, 0x00, 0x20, - 0x58, 0x00, 0x00, 0x20 -}; - -/* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ -static const uint8_t loader_code_stm32f0[] = { - 0xc0, 0x46, 0xc0, 0x46, - 0x13, 0x4f, 0x3c, 0x68, - 0x13, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x13, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x12, 0x4f, 0x33, 0x68, - 0x3b, 0x43, 0x33, 0x60, - 0x03, 0x88, 0x0b, 0x80, - 0x10, 0x4f, 0xc0, 0x19, - 0xc9, 0x19, 0x0e, 0x4f, - 0x2b, 0x68, 0x3b, 0x42, - 0xfb, 0xd0, 0x0e, 0x4f, - 0x3b, 0x42, 0x03, 0xd1, - 0x0a, 0x4f, 0xd2, 0x1b, - 0x00, 0x2a, 0xeb, 0xd1, - 0x08, 0x4f, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0xc0, 0x46, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x48, 0x00, 0x00, 0x20, - 0x4c, 0x00, 0x00, 0x20, - 0x50, 0x00, 0x00, 0x20, - 0x01, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00 -}; - -static const uint8_t loader_code_stm32l[] = { - // flashloaders/stm32lx.s - - 0x03, 0x68, 0x0b, 0x60, - 0x4f, 0xf0, 0x04, 0x07, - 0x38, 0x44, 0x39, 0x44, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xf4, 0xd1, 0x00, 0xbe, -}; - -static const uint8_t loader_code_stm32f4[] = { - // flashloaders/stm32f4.s - - 0xdf, 0xf8, 0x28, 0xc0, - 0xdf, 0xf8, 0x28, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 -}; - -static const uint8_t loader_code_stm32f4_lv[] = { - // flashloaders/stm32f4lv.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 -}; - -static const uint8_t loader_code_stm32l4[] = { - // flashloaders/stm32l4.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x44, 0x68, 0x0b, 0x60, - 0x4c, 0x60, 0x00, 0xf1, - 0x08, 0x00, 0x01, 0xf1, - 0x08, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, - 0x12, 0x00, 0x00, 0x00 -}; - -static const uint8_t loader_code_stm32f7[] = { - // flashloaders/stm32f7.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 -}; - -static const uint8_t loader_code_stm32f7_lv[] = { - // flashloaders/stm32f7lv.s - 0xdf, 0xf8, 0x30, 0xc0, - 0xdf, 0xf8, 0x30, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 -}; - - -int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { + /* flashloaders/stm32f0.s -- compiled with thumb2 */ + static const uint8_t loader_code_stm32vl[] = { + 0x16, 0x4f, 0x3c, 0x68, + 0x16, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x16, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x4f, 0xf0, 0x01, 0x07, + 0x33, 0x68, 0x3b, 0x43, + 0x33, 0x60, 0x03, 0x88, + 0x0b, 0x80, 0x4f, 0xf0, + 0x02, 0x07, 0xc0, 0x19, + 0xc9, 0x19, 0x4f, 0xf0, + 0x01, 0x07, 0x2b, 0x68, + 0x3b, 0x42, 0xfa, 0xd0, + 0x4f, 0xf0, 0x04, 0x07, + 0x3b, 0x42, 0x04, 0xd1, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xe6, 0xd1, 0x4f, 0xf0, + 0x01, 0x07, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x20, + 0x54, 0x00, 0x00, 0x20, + 0x58, 0x00, 0x00, 0x20 + }; + + /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ + static const uint8_t loader_code_stm32f0[] = { + 0xc0, 0x46, 0xc0, 0x46, + 0x13, 0x4f, 0x3c, 0x68, + 0x13, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x13, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x12, 0x4f, 0x33, 0x68, + 0x3b, 0x43, 0x33, 0x60, + 0x03, 0x88, 0x0b, 0x80, + 0x10, 0x4f, 0xc0, 0x19, + 0xc9, 0x19, 0x0e, 0x4f, + 0x2b, 0x68, 0x3b, 0x42, + 0xfb, 0xd0, 0x0e, 0x4f, + 0x3b, 0x42, 0x03, 0xd1, + 0x0a, 0x4f, 0xd2, 0x1b, + 0x00, 0x2a, 0xeb, 0xd1, + 0x08, 0x4f, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0xc0, 0x46, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x48, 0x00, 0x00, 0x20, + 0x4c, 0x00, 0x00, 0x20, + 0x50, 0x00, 0x00, 0x20, + 0x01, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00 + }; + + static const uint8_t loader_code_stm32l[] = { + // flashloaders/stm32lx.s + + 0x03, 0x68, 0x0b, 0x60, + 0x4f, 0xf0, 0x04, 0x07, + 0x38, 0x44, 0x39, 0x44, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xf4, 0xd1, 0x00, 0xbe, + }; + + static const uint8_t loader_code_stm32f4[] = { + // flashloaders/stm32f4.s + + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 + }; + + static const uint8_t loader_code_stm32f4_lv[] = { + // flashloaders/stm32f4lv.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 + }; + + static const uint8_t loader_code_stm32l4[] = { + // flashloaders/stm32l4.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x44, 0x68, 0x0b, 0x60, + 0x4c, 0x60, 0x00, 0xf1, + 0x08, 0x00, 0x01, 0xf1, + 0x08, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x12, 0x00, 0x00, 0x00 + }; + + static const uint8_t loader_code_stm32f7[] = { + // flashloaders/stm32f7.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 + }; + + static const uint8_t loader_code_stm32f7_lv[] = { + // flashloaders/stm32f7lv.s + 0xdf, 0xf8, 0x30, 0xc0, + 0xdf, 0xf8, 0x30, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 + }; + + + +int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) +{ size_t size = 0; - // allocate the loader in SRAM + /* allocate the loader in sram */ if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { WLOG("Failed to write flash loader to sram!\n"); - return(-1); + return -1; } - // allocate a one page buffer in SRAM right after loader - fl->buf_addr = fl->loader_addr + (uint32_t)size; + /* allocate a one page buffer in sram right after loader */ + fl->buf_addr = fl->loader_addr + (uint32_t) size; ILOG("Successfully loaded flash loader in sram\n"); - return(0); + return 0; } static int loader_v_dependent_assignment(stlink_t *sl, const uint8_t **loader_code, size_t *loader_size, const uint8_t *high_v_loader, size_t high_v_loader_size, - const uint8_t *low_v_loader, size_t low_v_loader_size) { + const uint8_t *low_v_loader, size_t low_v_loader_size) +{ int retval = 0; - if ( sl->version.stlink_v == 1) { + if ( sl->version.stlink_v == 1){ printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes\n"); *loader_code = high_v_loader; *loader_size = high_v_loader_size; - } else { + } + else { int voltage = stlink_target_voltage(sl); - if (voltage == -1) { retval = -1; printf("Failed to read Target voltage\n"); - } else { + } + else { if (voltage > 2700) { *loader_code = high_v_loader; *loader_size = high_v_loader_size; @@ -216,11 +219,11 @@ static int loader_v_dependent_assignment(stlink_t *sl, } } } - - return(retval); + return retval; } -int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { +int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) +{ const uint8_t* loader_code; size_t loader_size; @@ -232,7 +235,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_L011 || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { // STM32l + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */ loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || @@ -245,34 +248,38 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || - sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F4_DE || - sl->chip_id == STLINK_CHIPID_STM32_F4_LP || - sl->chip_id == STLINK_CHIPID_STM32_F4_HD || - sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || - sl->chip_id == STLINK_CHIPID_STM32_F410 || - sl->chip_id == STLINK_CHIPID_STM32_F411RE || - sl->chip_id == STLINK_CHIPID_STM32_F412 || - sl->chip_id == STLINK_CHIPID_STM32_F413 || - sl->chip_id == STLINK_CHIPID_STM32_F446) { + sl->chip_id == STLINK_CHIPID_STM32_F4 || + sl->chip_id == STLINK_CHIPID_STM32_F4_DE || + sl->chip_id == STLINK_CHIPID_STM32_F4_LP || + sl->chip_id == STLINK_CHIPID_STM32_F4_HD || + sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || + sl->chip_id == STLINK_CHIPID_STM32_F410 || + sl->chip_id == STLINK_CHIPID_STM32_F411RE || + sl->chip_id == STLINK_CHIPID_STM32_F412 || + sl->chip_id == STLINK_CHIPID_STM32_F413 || + sl->chip_id == STLINK_CHIPID_STM32_F446 + ) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f4, sizeof(loader_code_stm32f4), loader_code_stm32f4_lv, sizeof(loader_code_stm32f4_lv)); - - if (retval == -1) { return(retval); } + if (retval == -1) { + return retval; + } } else if (sl->core_id == STM32F7_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX || - sl->chip_id == STLINK_CHIPID_STM32_F72XXX) { + sl->chip_id == STLINK_CHIPID_STM32_F72XXX + ) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f7, sizeof(loader_code_stm32f7), loader_code_stm32f7_lv, sizeof(loader_code_stm32f7_lv)); - - if (retval == -1) { return(retval); } + if (retval == -1) { + return retval; + } } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || @@ -285,102 +292,101 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* (sl->chip_id == STLINK_CHIPID_STM32_L43X) || (sl->chip_id == STLINK_CHIPID_STM32_L46X) || (sl->chip_id == STLINK_CHIPID_STM32_L4RX) || - (sl->chip_id == STLINK_CHIPID_STM32_L496X)) { + (sl->chip_id == STLINK_CHIPID_STM32_L496X)) + { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { - ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", - sl->core_id, sl->chip_id); - return(-1); + ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", sl->core_id, sl->chip_id); + return -1; } memcpy(sl->q_buf, loader_code, loader_size); int ret = stlink_write_mem32(sl, sl->sram_base, loader_size); - - if (ret) { return(ret); } + if (ret) + return ret; *addr = sl->sram_base; *size = loader_size; - return(0); // success + /* success */ + return 0; } -int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { +int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) +{ struct stlink_reg rr; int i = 0; size_t count = 0; uint32_t flash_base = 0; DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); - - // TODO: This can never return -1 + // FIXME This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { // IMPOSSIBLE! ELOG("write_buffer_to_sram() == -1\n"); - return(-1); + return -1; } if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { count = size / sizeof(uint16_t); - - if (size % sizeof(uint16_t)) { ++count; } + if (size % sizeof(uint16_t)) + ++count; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_L0) { count = size / sizeof(uint32_t); - - if (size % sizeof(uint32_t)) { ++count; } + if (size % sizeof(uint32_t)) + ++count; } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { count = size / sizeof(uint64_t); - - if (size % sizeof(uint64_t)) { ++count; } + if (size % sizeof(uint64_t)) + ++count; } if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { flash_base = FLASH_REGS_BANK2_OFS; } - /* Setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); // source - stlink_write_reg(sl, target, 1); // target - stlink_write_reg(sl, (uint32_t)count, 2); // count - stlink_write_reg(sl, flash_base, 3); // flash register base - // only used on VL/F1_XL, but harmless for others - stlink_write_reg(sl, fl->loader_addr, 15); // pc register + /* setup core */ + stlink_write_reg(sl, fl->buf_addr, 0); /* source */ + stlink_write_reg(sl, target, 1); /* target */ + stlink_write_reg(sl, (uint32_t) count, 2); /* count */ + stlink_write_reg(sl, flash_base, 3); /* flash register base, only used on VL/F1_XL, but harmless for others */ + stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ - /* Run loader */ + /* run loader */ stlink_run(sl); -/* This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. - * But because this usually runs on Unix-like OSes, the 10 µs get rounded up to the "tick" - * (actually almost two ticks) of the system. 1 ms. Thus, the ten thousand attempts, when - * "something goes wrong" that requires the error message "flash loader run error" would wait - * for something like 20 seconds before coming up with the error. - * By increasing the sleep-per-round to the same order-of-magnitude as the tick-rounding that - * the OS uses, the wait until the error message is reduced to the same order of magnitude - * as what was intended. -- REW. - */ -#define WAIT_ROUNDS 30 - - // wait until done (reaches breakpoint) +// This piece of code used to try to spin for .1 second by waiting +// doing 10000 rounds of 10 microseconds. But because this usually runs +// on Unix-like OSes, the 10 microseconds get rounded up to the "tick" +// (actually almost two ticks) of the system. 1 milisecond. Thus, the +// ten thousand attempts, when "something goes wrong" that requires +// the error message "flash loader run error" would wait for something +// like 20 seconds before coming up with the error. +// by increasing the sleep-per-round to the same order-of-magnitude as +// the tick-rounding that the OS uses, the wait until the error message is +// reduced to the same order of magnitude as what was intended. -- REW. +#define WAIT_ROUNDS 100 + /* wait until done (reaches breakpoint) */ for (i = 0; i < WAIT_ROUNDS; i++) { - usleep(10000); - - if (stlink_is_core_halted(sl)) { break; } + usleep(1000); + if (stlink_is_core_halted(sl)) + break; } if (i >= WAIT_ROUNDS) { ELOG("flash loader run error\n"); - return(-1); + return -1; } - // check written byte count + /* check written byte count */ stlink_read_reg(sl, 2, &rr); - if (rr.r[2] != 0) { ELOG("write error, count == %u\n", rr.r[2]); - return(-1); + return -1; } - return(0); + return 0; } From 77c58f054e091f9c2c4c2db7cdb44e242901b24b Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Thu, 25 Jun 2020 14:55:34 +0200 Subject: [PATCH 0989/1435] re-applied the changes to the original files --- src/st-flash/flash_opts.c | 455 ++++++++++++++++--------------- src/stlink-lib/flash_loader.c | 486 +++++++++++++++++----------------- 2 files changed, 478 insertions(+), 463 deletions(-) diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 8557445e0..6653c6e62 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -2,11 +2,12 @@ #include #include -#include +#include "flash.h" static bool starts_with(const char * str, const char * prefix) { size_t n = strlen(prefix); - if (strlen(str) < n) return false; + + if (strlen(str) < n) { return(false); } return (0 == strncmp(str, prefix, n)); } @@ -19,37 +20,28 @@ static int get_long_integer_from_char_array (const char *const str, uint64_t *re uint64_t value; char *tail; - // hexadecimal - if (starts_with (str, "0x") || starts_with (str, "0X")) { + if (starts_with (str, "0x") || starts_with (str, "0X")) { // hexadecimal value = strtoul (str + 2, &tail, 16); - } - // binary - else if (starts_with (str, "0b") || starts_with (str, "0B")) { + } else if (starts_with (str, "0b") || starts_with (str, "0B")) { // binary value = strtoul (str + 2, &tail, 2); - } - // octal - else if (starts_with (str, "0")) { + } else if (starts_with (str, "0")) { // octal value = strtoul (str + 1, &tail, 8); - } - // decimal - else { + } else { // decimal value = strtoul (str, &tail, 10); } if (((tail[0] == 'k') || (tail[0] == 'K')) && (tail[1] == '\0')) { value = value * 1024; - } - else if (((tail[0] == 'm') || (tail[0] == 'M')) && (tail[1] == '\0')) { + } else if (((tail[0] == 'm') || (tail[0] == 'M')) && (tail[1] == '\0')) { value = value * 1024 * 1024; + } else if (tail[0] == '\0') { + /* value not changed */ + } else { + return(-1); } - else if (tail[0] == '\0') { - // value not change - } - else { - return -1; - } + *read_value = value; - return 0; + return(0); } // support positive integer from 0 to UINT32_MAX @@ -59,28 +51,26 @@ static int get_long_integer_from_char_array (const char *const str, uint64_t *re static int get_integer_from_char_array (const char *const str, uint32_t *read_value) { uint64_t value; int result = get_long_integer_from_char_array (str, &value); + if (result != 0) { - return result; - } - else if (value > UINT32_MAX) { - fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, \ -cannot convert to int32_t\n"); - return -1; - } - else { + return(result); + } else if (value > UINT32_MAX) { + fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, cannot convert to int32_t\n"); + return(-1); + } else { *read_value = (uint32_t)value; - return 0; + return(0); } } static int invalid_args(const char *expected) { fprintf(stderr, "*** Error: Expected args for this command: %s\n", expected); - return -1; + return(-1); } static int bad_arg(const char *arg) { fprintf(stderr, "*** Error: Invalid value for %s\n", arg); - return -1; + return(-1); } int flash_get_opts(struct flash_opts* o, int ac, char** av) { @@ -91,148 +81,158 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { // options int result; + while (ac >= 1) { if (strcmp(av[0], "--version") == 0) { printf("v%s\n", STLINK_VERSION); exit(EXIT_SUCCESS); - } - else if (strcmp(av[0], "--debug") == 0) { + } else if (strcmp(av[0], "--debug") == 0) { o->log_level = DEBUG_LOG_LEVEL; - } - else if (strcmp(av[0], "--opt") == 0) { + } else if (strcmp(av[0], "--opt") == 0) { o->opt = ENABLE_OPT; - } - else if (strcmp(av[0], "--reset") == 0) { + } else if (strcmp(av[0], "--reset") == 0) { o->reset = 1; - } - else if (strcmp(av[0], "--serial") == 0 || starts_with(av[0], "--serial=")) { + } else if (strcmp(av[0], "--serial") == 0 || starts_with(av[0], "--serial=")) { const char * serial; + if (strcmp(av[0], "--serial") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { return(-1); } + serial = av[0]; - } - else { + } else { serial = av[0] + strlen("--serial="); } - /** @todo This is not really portable, as strlen really returns size_t we need to obey and not cast it to a signed type. */ + + /** @todo This is not really portable, as strlen really returns size_t we need to obey + and not cast it to a signed type. */ int j = (int)strlen(serial); - int length = j / 2; // the length of the destination-array - if (j % 2 != 0) return -1; + int length = j / 2; // the length of the destination-array + + if (j % 2 != 0) { return(-1); } + for (size_t k = 0; j >= 0 && k < sizeof(o->serial); ++k, j -= 2) { char buffer[3] = {0}; memcpy(buffer, serial + j, 2); o->serial[length - k] = (uint8_t)strtol(buffer, NULL, 16); } - } - else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { + } else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { const char * area; + if (strcmp(av[0], "--area") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { return(-1); } + area = av[0]; - } - else { + } else { area = av[0] + strlen("--area="); } - if (strcmp(area, "main") == 0) + + if (strcmp(area, "main") == 0) { o->area = FLASH_MAIN_MEMORY; - else if (strcmp(area, "system") == 0) + } else if (strcmp(area, "system") == 0) { o->area = FLASH_SYSTEM_MEMORY; - else if (strcmp(area, "otp") == 0) + } else if (strcmp(area, "otp") == 0) { o->area = FLASH_OTP; - else if (strcmp(area, "option") == 0) + } else if (strcmp(area, "option") == 0) { o->area = FLASH_OPTION_BYTES; - else if (strcmp(area, "option_boot_add") == 0) + } else if (strcmp(area, "option_boot_add") == 0) { o->area = FLASH_OPTION_BYTES_BOOT_ADD; - else if (strcmp(area, "optcr") == 0) + } else if (strcmp(area, "optcr") == 0) { o->area = FLASH_OPTCR; - else if (strcmp(area, "optcr1") == 0) + } else if (strcmp(area, "optcr1") == 0) { o->area = FLASH_OPTCR1; - else - return -1; + } else { + return(-1); + } - } - else if (strcmp(av[0], "--freq") == 0 || starts_with(av[0], "--freq=")) { + } else if (strcmp(av[0], "--freq") == 0 || starts_with(av[0], "--freq=")) { const char* freq; + if (strcmp(av[0], "--freq") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { + return(-1); + } + freq = av[0]; - } - else { + } else { freq = av[0] + strlen("--freq="); } + if (strcmp(freq, "5K") == 0 || strcmp(freq, "5k") == 0) { o->freq = 5; - } - else if (strcmp(freq, "15K") == 0 || strcmp(freq, "15k") == 0) { + } else if (strcmp(freq, "15K") == 0 || strcmp(freq, "15k") == 0) { o->freq = 15; - } - else if (strcmp(freq, "25K") == 0 || strcmp(freq, "25k") == 0) { + } else if (strcmp(freq, "25K") == 0 || strcmp(freq, "25k") == 0) { o->freq = 25; - } - else if (strcmp(freq, "50K") == 0 || strcmp(freq, "50k") == 0) { + } else if (strcmp(freq, "50K") == 0 || strcmp(freq, "50k") == 0) { o->freq = 50; - } - else if (strcmp(freq, "100K") == 0 || strcmp(freq, "100k") == 0) { + } else if (strcmp(freq, "100K") == 0 || strcmp(freq, "100k") == 0) { o->freq = 100; - } - else if (strcmp(freq, "125K") == 0 || strcmp(freq, "125k") == 0) { + } else if (strcmp(freq, "125K") == 0 || strcmp(freq, "125k") == 0) { o->freq = 125; - } - else if (strcmp(freq, "240K") == 0 || strcmp(freq, "240k") == 0) { + } else if (strcmp(freq, "240K") == 0 || strcmp(freq, "240k") == 0) { o->freq = 240; - } - else if (strcmp(freq, "480K") == 0 || strcmp(freq, "480k") == 0) { + } else if (strcmp(freq, "480K") == 0 || strcmp(freq, "480k") == 0) { o->freq = 480; - } - else if (strcmp(freq, "950K") == 0 || strcmp(freq, "950k") == 0) { + } else if (strcmp(freq, "950K") == 0 || strcmp(freq, "950k") == 0) { o->freq = 950; - } - else if (strcmp(freq, "1200K") == 0 || strcmp(freq, "1200k") == 0 || strcmp(freq, "1.2M") == 0 || strcmp(freq, "1.2m") == 0) { + } else if (strcmp(freq, "1200K") == 0 || strcmp(freq, "1200k") == 0 || + strcmp(freq, "1.2M") == 0 || strcmp(freq, "1.2m") == 0) { o->freq = 1200; - } - else if (strcmp(freq, "1800K") == 0 || strcmp(freq, "1800k") == 0 || strcmp(freq, "1.8M") == 0 || strcmp(freq, "1.8m") == 0) { + } else if (strcmp(freq, "1800K") == 0 || strcmp(freq, "1800k") == 0 || + strcmp(freq, "1.8M") == 0 || strcmp(freq, "1.8m") == 0) { o->freq = 1800; - } - else if (strcmp(freq, "4000K") == 0 || strcmp(freq, "4000k") == 0 || strcmp(freq, "4M") == 0 || strcmp(freq, "4m") == 0) { + } else if (strcmp(freq, "4000K") == 0 || strcmp(freq, "4000k") == 0 || + strcmp(freq, "4M") == 0 || strcmp(freq, "4m") == 0) { o->freq = 4000; + } else { + return(-1); } - else - return -1; - } - else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { + } else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { const char * format; + if (strcmp(av[0], "--format") == 0) { ac--; av++; - if (ac < 1) return -1; + + if (ac < 1) { return(-1); } + format = av[0]; - } - else { + } else { format = av[0] + strlen("--format="); } - if (strcmp(format, "binary") == 0) + + if (strcmp(format, "binary") == 0) { o->format = FLASH_FORMAT_BINARY; - else if (strcmp(format, "ihex") == 0) + } else if (strcmp(format, "ihex") == 0) { o->format = FLASH_FORMAT_IHEX; - else - return bad_arg("format"); - } - else if ( starts_with(av[0], "--flash=") ) { + } else { + return(bad_arg("format")); + } + } else if ( starts_with(av[0], "--flash=")) { const char *arg = av[0] + strlen("--flash="); uint32_t flash_size; result = get_integer_from_char_array(arg, &flash_size); - if (result != 0) return bad_arg ("--flash"); - else o->flash_size = (size_t) flash_size; - } - else { - break; // non-option found + + if (result != 0) { + return(bad_arg ("--flash")); + } else { + o->flash_size = (size_t)flash_size; + } + } else if (strcmp(av[0], "--connect-under-reset") == 0) { + o->connect_under_reset = true; + } else { + break; // non-option found + } ac--; @@ -242,22 +242,21 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { // command and (optional) device name while (ac >= 1) { if (strcmp(av[0], "erase") == 0) { - if (FLASH_CMD_NONE != o->cmd) return -1; + if (FLASH_CMD_NONE != o->cmd) { return(-1); } o->cmd = FLASH_CMD_ERASE; - } - else if (strcmp(av[0], "read") == 0) { - if (FLASH_CMD_NONE != o->cmd) return -1; + } else if (strcmp(av[0], "read") == 0) { + if (FLASH_CMD_NONE != o->cmd) { return(-1); } + o->cmd = FLASH_CMD_READ; - } - else if (strcmp(av[0], "write") == 0) { - if (FLASH_CMD_NONE != o->cmd) return -1; + } else if (strcmp(av[0], "write") == 0) { + if (FLASH_CMD_NONE != o->cmd) { return(-1); } + o->cmd = FLASH_CMD_WRITE; - } - else if (strcmp(av[0], "reset") == 0) { - if (FLASH_CMD_NONE != o->cmd) return -1; + } else if (strcmp(av[0], "reset") == 0) { + if (FLASH_CMD_NONE != o->cmd) { return(-1); } + o->cmd = CMD_RESET; - } - else { + } else { break; } @@ -265,120 +264,142 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { av++; } - switch(o->cmd) { - case FLASH_CMD_NONE: // no command found - return -1; - - case FLASH_CMD_ERASE: // no more arguments expected - if (ac != 0) return -1; - break; + switch (o->cmd) { + case FLASH_CMD_NONE: // no command found + return(-1); - case FLASH_CMD_READ: // expect filename, addr and size - if ((FLASH_MAIN_MEMORY == o->area) || (FLASH_SYSTEM_MEMORY == o->area)) { - if (ac != 3) return invalid_args("read "); - o->filename = av[0]; - uint32_t address; - result = get_integer_from_char_array(av[1], &address); - if (result != 0) return bad_arg ("addr"); - else o->addr = (stm32_addr_t) address; + case FLASH_CMD_ERASE: // no more arguments expected + if (ac != 0) { return(-1); } - uint32_t size; - result = get_integer_from_char_array(av[2], &size); - if (result != 0) return bad_arg ("size"); - else o->size = (size_t) size; + break; - break; + case FLASH_CMD_READ: // expect filename, addr and size + if ((FLASH_MAIN_MEMORY == o->area) || (FLASH_SYSTEM_MEMORY == o->area)) { + if (ac != 3) { return invalid_args("read "); } + + o->filename = av[0]; + uint32_t address; + result = get_integer_from_char_array(av[1], &address); + if (result != 0) { + return bad_arg ("addr"); + } else { + o->addr = (stm32_addr_t) address; } - else if ((FLASH_OTP == o->area)) { - return bad_arg("TODO: otp not implemented yet"); - if (ac > 1) return invalid_args("otp read: [path]"); - if (ac > 0) o->filename = av[0]; - break; + + uint32_t size; + result = get_integer_from_char_array(av[2], &size); + if (result != 0) { + return bad_arg ("size"); + } else { + o->size = (size_t) size; } - else if ((FLASH_OPTION_BYTES == o->area)) { - if (ac > 2) return invalid_args("option bytes read: [path] [size]"); - if (ac > 0) o->filename = av[0]; - if (ac > 1) { - uint32_t size; - result = get_integer_from_char_array(av[1], &size); - if (result != 0) return bad_arg("option bytes read: invalid size"); - else o->size = (size_t) size; + + break; + } else if ((FLASH_OTP == o->area)) { + return bad_arg("TODO: otp not implemented yet"); + if (ac > 1) { return invalid_args("otp read: [path]"); } + if (ac > 0) { o->filename = av[0]; } + break; + } else if ((FLASH_OPTION_BYTES == o->area)) { + if (ac > 2) { return invalid_args("option bytes read: [path] [size]"); } + if (ac > 0) { o->filename = av[0]; } + if (ac > 1) { + uint32_t size; + result = get_integer_from_char_array(av[1], &size); + if (result != 0) { + return bad_arg("option bytes read: invalid size"); + } else { + o->size = (size_t) size; } - break; - } - else if ((FLASH_OPTION_BYTES_BOOT_ADD == o->area)) { - if (ac > 0) return invalid_args("option bytes boot_add read"); - break; - } - else if ((FLASH_OPTCR == o->area)) { - if (ac > 0) return invalid_args("option control register read"); - break; - } - else if ((FLASH_OPTCR1 == o->area)) { - if (ac > 0) return invalid_args("option control register 1 read"); - break; } break; + } else if ((FLASH_OPTION_BYTES_BOOT_ADD == o->area)) { + if (ac > 0) { return invalid_args("option bytes boot_add read"); } + break; + } else if ((FLASH_OPTCR == o->area)) { + if (ac > 0) { return invalid_args("option control register read"); } + break; + } else if ((FLASH_OPTCR1 == o->area)) { + if (ac > 0) { return invalid_args("option control register 1 read"); } + break; + } - case FLASH_CMD_WRITE: - // TODO: should be boot add 0 and boot add 1 uint32 - if (FLASH_OPTION_BYTES == o->area) { // expect filename and optional address - if (ac >=1 && ac <= 2) { - o->filename = av[0]; - } - else - return invalid_args("write [addr]"); - - if (ac == 2) { - uint32_t addr; - result = get_integer_from_char_array(av[1], &addr); - if (result != 0) return bad_arg ("addr"); - else o->addr = (stm32_addr_t) addr; - } - } - else if (FLASH_OPTION_BYTES_BOOT_ADD == o->area) { // expect option bytes boot address - if (ac != 1) return invalid_args("option bytes boot_add write "); - - uint32_t val; - result = get_integer_from_char_array(av[0], &val); - if (result != 0) return bad_arg ("val"); - else o->val = (uint32_t) val; - } - else if (FLASH_OPTCR == o->area) { // expect option control register value - if (ac != 1) return invalid_args("option control register write "); - - uint32_t val; - result = get_integer_from_char_array(av[0], &val); - if (result != 0) return bad_arg ("val"); - else o->val = (uint32_t) val; - } - else if (FLASH_OPTCR1 == o->area) { // expect option control register 1 value - if (ac != 1) return invalid_args("option control register 1 write "); - - uint32_t val; - result = get_integer_from_char_array(av[0], &val); - if (result != 0) return bad_arg ("val"); - else o->val = (uint32_t) val; - } - else if (FLASH_FORMAT_BINARY == o->format) { // expect filename and addr - if (ac != 2) return invalid_args("write "); + break; + + case FLASH_CMD_WRITE: + // TODO: should be boot add 0 and boot add 1 uint32 + if (FLASH_OPTION_BYTES == o->area) { // expect filename and optional address + if (ac >=1 && ac <= 2) { o->filename = av[0]; + } else { + return invalid_args("write [addr]"); + } + + if (ac == 2) { uint32_t addr; result = get_integer_from_char_array(av[1], &addr); - if (result != 0) return bad_arg ("addr"); - else o->addr = (stm32_addr_t) addr; - } - else if (FLASH_FORMAT_IHEX == o->format) { // expect filename - if (ac != 1) return invalid_args("write "); - o->filename = av[0]; + if (result != 0) { + return bad_arg ("addr"); + } else { + o->addr = (stm32_addr_t) addr; + } } - else { - return -1; // should have been caught during format parsing + } else if (FLASH_OPTION_BYTES_BOOT_ADD == o->area) { // expect option bytes boot address + if (ac != 1) { return invalid_args("option bytes boot_add write "); } + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + + if (result != 0) { + return(bad_arg ("val")); + } else { + o->val = (uint32_t)val; + } + } else if (FLASH_OPTCR == o->area) { // expect option control register value + if (ac != 1) { return invalid_args("option control register write "); } + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + + if (result != 0) { + return bad_arg ("val"); + } else { + o->val = (uint32_t) val; + } + } else if (FLASH_OPTCR1 == o->area) { // expect option control register 1 value + if (ac != 1) { return invalid_args("option control register 1 write "); } + + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) { + return bad_arg ("val"); + } else { + o->val = (uint32_t) val; + } + } else if (FLASH_FORMAT_BINARY == o->format) { // expect filename and addr + if (ac != 2) { return invalid_args("write "); } + + o->filename = av[0]; + uint32_t addr; + result = get_integer_from_char_array(av[1], &addr); + + if (result != 0) { + return(bad_arg ("addr")); + } else { + o->addr = (stm32_addr_t)addr; } - break; + } else if (o->format == FLASH_FORMAT_IHEX) { // expect filename + if (ac != 1) { return(invalid_args("write ")); } + + o->filename = av[0]; + } else { + return(-1); // should have been caught during format parsing + } + + break; - default: break ; + default: break; } - return 0; + return(0); } diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index b6058cd0e..0e79c3c0a 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -3,213 +3,210 @@ #include #include +#include "flash_loader.h" #define FLASH_REGS_BANK2_OFS 0x40 #define FLASH_BANK2_START_ADDR 0x08080000 /* DO NOT MODIFY SOURCECODE DIRECTLY, EDIT ASSEMBLY FILES INSTEAD */ - /* flashloaders/stm32f0.s -- compiled with thumb2 */ - static const uint8_t loader_code_stm32vl[] = { - 0x16, 0x4f, 0x3c, 0x68, - 0x16, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x16, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x4f, 0xf0, 0x01, 0x07, - 0x33, 0x68, 0x3b, 0x43, - 0x33, 0x60, 0x03, 0x88, - 0x0b, 0x80, 0x4f, 0xf0, - 0x02, 0x07, 0xc0, 0x19, - 0xc9, 0x19, 0x4f, 0xf0, - 0x01, 0x07, 0x2b, 0x68, - 0x3b, 0x42, 0xfa, 0xd0, - 0x4f, 0xf0, 0x04, 0x07, - 0x3b, 0x42, 0x04, 0xd1, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xe6, 0xd1, 0x4f, 0xf0, - 0x01, 0x07, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x50, 0x00, 0x00, 0x20, - 0x54, 0x00, 0x00, 0x20, - 0x58, 0x00, 0x00, 0x20 - }; - - /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ - static const uint8_t loader_code_stm32f0[] = { - 0xc0, 0x46, 0xc0, 0x46, - 0x13, 0x4f, 0x3c, 0x68, - 0x13, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x13, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x12, 0x4f, 0x33, 0x68, - 0x3b, 0x43, 0x33, 0x60, - 0x03, 0x88, 0x0b, 0x80, - 0x10, 0x4f, 0xc0, 0x19, - 0xc9, 0x19, 0x0e, 0x4f, - 0x2b, 0x68, 0x3b, 0x42, - 0xfb, 0xd0, 0x0e, 0x4f, - 0x3b, 0x42, 0x03, 0xd1, - 0x0a, 0x4f, 0xd2, 0x1b, - 0x00, 0x2a, 0xeb, 0xd1, - 0x08, 0x4f, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0xc0, 0x46, - 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x48, 0x00, 0x00, 0x20, - 0x4c, 0x00, 0x00, 0x20, - 0x50, 0x00, 0x00, 0x20, - 0x01, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32l[] = { - // flashloaders/stm32lx.s - - 0x03, 0x68, 0x0b, 0x60, - 0x4f, 0xf0, 0x04, 0x07, - 0x38, 0x44, 0x39, 0x44, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xf4, 0xd1, 0x00, 0xbe, - }; - - static const uint8_t loader_code_stm32f4[] = { - // flashloaders/stm32f4.s - - 0xdf, 0xf8, 0x28, 0xc0, - 0xdf, 0xf8, 0x28, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32f4_lv[] = { - // flashloaders/stm32f4lv.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32l4[] = { - // flashloaders/stm32l4.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x44, 0x68, 0x0b, 0x60, - 0x4c, 0x60, 0x00, 0xf1, - 0x08, 0x00, 0x01, 0xf1, - 0x08, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x20, 0x02, 0x40, - 0x12, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32f7[] = { - // flashloaders/stm32f7.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, - 0x04, 0x00, 0x01, 0xf1, - 0x04, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - static const uint8_t loader_code_stm32f7_lv[] = { - // flashloaders/stm32f7lv.s - 0xdf, 0xf8, 0x30, 0xc0, - 0xdf, 0xf8, 0x30, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, - 0x01, 0x00, 0x01, 0xf1, - 0x01, 0x01, 0xbf, 0xf3, - 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, - 0x00, 0xbe, 0x00, 0xbf, - 0x00, 0x3c, 0x02, 0x40, - 0x0e, 0x00, 0x00, 0x00 - }; - - - -int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) -{ +/* flashloaders/stm32f0.s -- compiled with thumb2 */ +static const uint8_t loader_code_stm32vl[] = { + 0x16, 0x4f, 0x3c, 0x68, + 0x16, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x16, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x4f, 0xf0, 0x01, 0x07, + 0x33, 0x68, 0x3b, 0x43, + 0x33, 0x60, 0x03, 0x88, + 0x0b, 0x80, 0x4f, 0xf0, + 0x02, 0x07, 0xc0, 0x19, + 0xc9, 0x19, 0x4f, 0xf0, + 0x01, 0x07, 0x2b, 0x68, + 0x3b, 0x42, 0xfa, 0xd0, + 0x4f, 0xf0, 0x04, 0x07, + 0x3b, 0x42, 0x04, 0xd1, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xe6, 0xd1, 0x4f, 0xf0, + 0x01, 0x07, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x50, 0x00, 0x00, 0x20, + 0x54, 0x00, 0x00, 0x20, + 0x58, 0x00, 0x00, 0x20 +}; + +/* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ +static const uint8_t loader_code_stm32f0[] = { + 0xc0, 0x46, 0xc0, 0x46, + 0x13, 0x4f, 0x3c, 0x68, + 0x13, 0x4f, 0x3e, 0x68, + 0x36, 0x19, 0x13, 0x4f, + 0x3d, 0x68, 0x2d, 0x19, + 0x12, 0x4f, 0x33, 0x68, + 0x3b, 0x43, 0x33, 0x60, + 0x03, 0x88, 0x0b, 0x80, + 0x10, 0x4f, 0xc0, 0x19, + 0xc9, 0x19, 0x0e, 0x4f, + 0x2b, 0x68, 0x3b, 0x42, + 0xfb, 0xd0, 0x0e, 0x4f, + 0x3b, 0x42, 0x03, 0xd1, + 0x0a, 0x4f, 0xd2, 0x1b, + 0x00, 0x2a, 0xeb, 0xd1, + 0x08, 0x4f, 0x33, 0x68, + 0xbb, 0x43, 0x33, 0x60, + 0x00, 0xbe, 0xc0, 0x46, + 0x00, 0x20, 0x02, 0x40, + 0x10, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x00, 0x00, + 0x48, 0x00, 0x00, 0x20, + 0x4c, 0x00, 0x00, 0x20, + 0x50, 0x00, 0x00, 0x20, + 0x01, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, + 0x04, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32l[] = { + // flashloaders/stm32lx.s + + 0x03, 0x68, 0x0b, 0x60, + 0x4f, 0xf0, 0x04, 0x07, + 0x38, 0x44, 0x39, 0x44, + 0x4f, 0xf0, 0x01, 0x07, + 0xd2, 0x1b, 0x00, 0x2a, + 0xf4, 0xd1, 0x00, 0xbe, +}; + +static const uint8_t loader_code_stm32f4[] = { + // flashloaders/stm32f4.s + + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32f4_lv[] = { + // flashloaders/stm32f4lv.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32l4[] = { + // flashloaders/stm32l4.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x44, 0x68, 0x0b, 0x60, + 0x4c, 0x60, 0x00, 0xf1, + 0x08, 0x00, 0x01, 0xf1, + 0x08, 0x01, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x20, 0x02, 0x40, + 0x12, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32f7[] = { + // flashloaders/stm32f7.s + 0xdf, 0xf8, 0x2c, 0xc0, + 0xdf, 0xf8, 0x2c, 0xa0, + 0xe2, 0x44, 0x03, 0x68, + 0x0b, 0x60, 0x00, 0xf1, + 0x04, 0x00, 0x01, 0xf1, + 0x04, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + +static const uint8_t loader_code_stm32f7_lv[] = { + // flashloaders/stm32f7lv.s + 0xdf, 0xf8, 0x30, 0xc0, + 0xdf, 0xf8, 0x30, 0xa0, + 0xe2, 0x44, 0x4f, 0xea, + 0x82, 0x02, 0x03, 0x78, + 0x0b, 0x70, 0x00, 0xf1, + 0x01, 0x00, 0x01, 0xf1, + 0x01, 0x01, 0xbf, 0xf3, + 0x4f, 0x8f, 0xba, 0xf8, + 0x00, 0x30, 0x13, 0xf0, + 0x01, 0x0f, 0xfa, 0xd0, + 0xa2, 0xf1, 0x01, 0x02, + 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0xbe, 0x00, 0xbf, + 0x00, 0x3c, 0x02, 0x40, + 0x0e, 0x00, 0x00, 0x00 +}; + + +int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { size_t size = 0; - /* allocate the loader in sram */ + // allocate the loader in SRAM if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { WLOG("Failed to write flash loader to sram!\n"); - return -1; + return(-1); } - /* allocate a one page buffer in sram right after loader */ - fl->buf_addr = fl->loader_addr + (uint32_t) size; + // allocate a one page buffer in SRAM right after loader + fl->buf_addr = fl->loader_addr + (uint32_t)size; ILOG("Successfully loaded flash loader in sram\n"); - return 0; + return(0); } static int loader_v_dependent_assignment(stlink_t *sl, const uint8_t **loader_code, size_t *loader_size, const uint8_t *high_v_loader, size_t high_v_loader_size, - const uint8_t *low_v_loader, size_t low_v_loader_size) -{ + const uint8_t *low_v_loader, size_t low_v_loader_size) { int retval = 0; - if ( sl->version.stlink_v == 1){ + if ( sl->version.stlink_v == 1) { printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes\n"); *loader_code = high_v_loader; *loader_size = high_v_loader_size; - } - else { + } else { int voltage = stlink_target_voltage(sl); + if (voltage == -1) { retval = -1; printf("Failed to read Target voltage\n"); - } - else { + } else { if (voltage > 2700) { *loader_code = high_v_loader; *loader_size = high_v_loader_size; @@ -219,11 +216,11 @@ static int loader_v_dependent_assignment(stlink_t *sl, } } } - return retval; + + return(retval); } -int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) -{ +int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { const uint8_t* loader_code; size_t loader_size; @@ -235,7 +232,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_L011 || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { /* stm32l */ + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { // STM32l loader_code = loader_code_stm32l; loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || @@ -248,38 +245,34 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || - sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F4_DE || - sl->chip_id == STLINK_CHIPID_STM32_F4_LP || - sl->chip_id == STLINK_CHIPID_STM32_F4_HD || - sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || - sl->chip_id == STLINK_CHIPID_STM32_F410 || - sl->chip_id == STLINK_CHIPID_STM32_F411RE || - sl->chip_id == STLINK_CHIPID_STM32_F412 || - sl->chip_id == STLINK_CHIPID_STM32_F413 || - sl->chip_id == STLINK_CHIPID_STM32_F446 - ) { + sl->chip_id == STLINK_CHIPID_STM32_F4 || + sl->chip_id == STLINK_CHIPID_STM32_F4_DE || + sl->chip_id == STLINK_CHIPID_STM32_F4_LP || + sl->chip_id == STLINK_CHIPID_STM32_F4_HD || + sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || + sl->chip_id == STLINK_CHIPID_STM32_F410 || + sl->chip_id == STLINK_CHIPID_STM32_F411RE || + sl->chip_id == STLINK_CHIPID_STM32_F412 || + sl->chip_id == STLINK_CHIPID_STM32_F413 || + sl->chip_id == STLINK_CHIPID_STM32_F446) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f4, sizeof(loader_code_stm32f4), loader_code_stm32f4_lv, sizeof(loader_code_stm32f4_lv)); - if (retval == -1) { - return retval; - } + + if (retval == -1) { return(retval); } } else if (sl->core_id == STM32F7_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F7XXXX || - sl->chip_id == STLINK_CHIPID_STM32_F72XXX - ) { + sl->chip_id == STLINK_CHIPID_STM32_F72XXX) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f7, sizeof(loader_code_stm32f7), loader_code_stm32f7_lv, sizeof(loader_code_stm32f7_lv)); - if (retval == -1) { - return retval; - } + + if (retval == -1) { return(retval); } } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || @@ -292,101 +285,102 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* (sl->chip_id == STLINK_CHIPID_STM32_L43X) || (sl->chip_id == STLINK_CHIPID_STM32_L46X) || (sl->chip_id == STLINK_CHIPID_STM32_L4RX) || - (sl->chip_id == STLINK_CHIPID_STM32_L496X)) - { + (sl->chip_id == STLINK_CHIPID_STM32_L496X)) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { - ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", sl->core_id, sl->chip_id); - return -1; + ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", + sl->core_id, sl->chip_id); + return(-1); } memcpy(sl->q_buf, loader_code, loader_size); int ret = stlink_write_mem32(sl, sl->sram_base, loader_size); - if (ret) - return ret; + + if (ret) { return(ret); } *addr = sl->sram_base; *size = loader_size; - /* success */ - return 0; + return(0); // success } -int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) -{ +int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { struct stlink_reg rr; int i = 0; size_t count = 0; uint32_t flash_base = 0; DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); - // FIXME This can never return -1 + + // TODO: This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { // IMPOSSIBLE! ELOG("write_buffer_to_sram() == -1\n"); - return -1; + return(-1); } if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { count = size / sizeof(uint16_t); - if (size % sizeof(uint16_t)) - ++count; + + if (size % sizeof(uint16_t)) { ++count; } } else if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_L0) { count = size / sizeof(uint32_t); - if (size % sizeof(uint32_t)) - ++count; + + if (size % sizeof(uint32_t)) { ++count; } } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { count = size / sizeof(uint64_t); - if (size % sizeof(uint64_t)) - ++count; + + if (size % sizeof(uint64_t)) { ++count; } } if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { flash_base = FLASH_REGS_BANK2_OFS; } - /* setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); /* source */ - stlink_write_reg(sl, target, 1); /* target */ - stlink_write_reg(sl, (uint32_t) count, 2); /* count */ - stlink_write_reg(sl, flash_base, 3); /* flash register base, only used on VL/F1_XL, but harmless for others */ - stlink_write_reg(sl, fl->loader_addr, 15); /* pc register */ + /* Setup core */ + stlink_write_reg(sl, fl->buf_addr, 0); // source + stlink_write_reg(sl, target, 1); // target + stlink_write_reg(sl, (uint32_t)count, 2); // count + stlink_write_reg(sl, flash_base, 3); // flash register base + // only used on VL/F1_XL, but harmless for others + stlink_write_reg(sl, fl->loader_addr, 15); // pc register - /* run loader */ + /* Run loader */ stlink_run(sl); -// This piece of code used to try to spin for .1 second by waiting -// doing 10000 rounds of 10 microseconds. But because this usually runs -// on Unix-like OSes, the 10 microseconds get rounded up to the "tick" -// (actually almost two ticks) of the system. 1 milisecond. Thus, the -// ten thousand attempts, when "something goes wrong" that requires -// the error message "flash loader run error" would wait for something -// like 20 seconds before coming up with the error. -// by increasing the sleep-per-round to the same order-of-magnitude as -// the tick-rounding that the OS uses, the wait until the error message is -// reduced to the same order of magnitude as what was intended. -- REW. -#define WAIT_ROUNDS 100 - /* wait until done (reaches breakpoint) */ +/* This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. + * But because this usually runs on Unix-like OSes, the 10 µs get rounded up to the "tick" + * (actually almost two ticks) of the system. 1 ms. Thus, the ten thousand attempts, when + * "something goes wrong" that requires the error message "flash loader run error" would wait + * for something like 20 seconds before coming up with the error. + * By increasing the sleep-per-round to the same order-of-magnitude as the tick-rounding that + * the OS uses, the wait until the error message is reduced to the same order of magnitude + * as what was intended. -- REW. + */ +#define WAIT_ROUNDS 30 + + // wait until done (reaches breakpoint) for (i = 0; i < WAIT_ROUNDS; i++) { - usleep(1000); - if (stlink_is_core_halted(sl)) - break; + usleep(10000); + + if (stlink_is_core_halted(sl)) { break; } } if (i >= WAIT_ROUNDS) { ELOG("flash loader run error\n"); - return -1; + return(-1); } - /* check written byte count */ + // check written byte count stlink_read_reg(sl, 2, &rr); + if (rr.r[2] != 0) { ELOG("write error, count == %u\n", rr.r[2]); - return -1; + return(-1); } - return 0; + return(0); } From a5b98f58756b6a1414ca8175c578e07998a59061 Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Thu, 25 Jun 2020 15:00:53 +0200 Subject: [PATCH 0990/1435] Fix compiler warning implicit cast --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 58e67d447..86d2ca8ea 100644 --- a/src/common.c +++ b/src/common.c @@ -3421,7 +3421,7 @@ int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t* option_byte) { } } - return stlink_read_debug32(sl, sl->option_base + (sl->option_size / 4 - 1) * sizeof(uint32_t), option_byte); + return stlink_read_debug32(sl, sl->option_base + (uint32_t) (sl->option_size / 4 - 1) * sizeof(uint32_t), option_byte); } /** From fc56f2412d80f09843b8f37a670ffc516640faaa Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 27 Jun 2020 02:28:00 +0200 Subject: [PATCH 0991/1435] General Project Update - Updated CHANGELOG.md - cpack: corrections for pkg config --- CHANGELOG.md | 3 ++- cmake/packaging/deb/changelog | 50 +++-------------------------------- cmake/packaging/deb/control | 4 +-- cmake/packaging/deb/copyright | 5 ++-- cmake/packaging/deb/rules | 3 +-- cmake/packaging/rpm/changelog | 4 +-- doc/version_support.md | 2 +- 7 files changed, 13 insertions(+), 58 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 3195bae3c..7717ca6f4 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -19,7 +19,7 @@ Features: * Support for STM32L1, SM32L4 option bytes write ([#596](https://github.com/stlink-org/stlink/pull/596), [#844](https://github.com/stlink-org/stlink/pull/844), [#847](https://github.com/stlink-org/stlink/pull/847)) * Added CMAKEFLAGS and install target ([#804](https://github.com/stlink-org/stlink/pull/804), [#935](https://github.com/stlink-org/stlink/pull/935)) * Support for STM32G4 ([#822](https://github.com/stlink-org/stlink/pull/822)) -* Add aliased SRAM2 region in the L496 memory map ([#824](https://github.com/stlink-org/stlink/pull/824)) +* Added aliased SRAM2 region in the L496 memory map ([#824](https://github.com/stlink-org/stlink/pull/824)) * Improved support for STM32G0 ([#825](https://github.com/stlink-org/stlink/pull/825), [#850](https://github.com/stlink-org/stlink/pull/850), [#856](https://github.com/stlink-org/stlink/pull/856), [#857](https://github.com/stlink-org/stlink/pull/857)) * Added postinst script with 'depmod -a' for 'make package' ([#845](https://github.com/stlink-org/stlink/pull/845), [#931](https://github.com/stlink-org/stlink/pull/931)) * Calculate checksums for flash operations ([#862](https://github.com/stlink-org/stlink/pull/862), [#924](https://github.com/stlink-org/stlink/pull/924)) @@ -358,6 +358,7 @@ Chip support added for: * STM32F469/STM32F479 ([#345](https://github.com/stlink-org/stlink/pull/345), [#555](https://github.com/stlink-org/stlink/pull/555)) (Release v1.2.0) * STM32L1xx Cat.2 devices (Nicolas Schodet) * STM32L1xx (chip-ID 0x427) ([#152](https://github.com/stlink-org/stlink/pull/152), [#163](https://github.com/stlink-org/stlink/pull/163), [#165](https://github.com/stlink-org/stlink/pull/165)) (Release v1.0.0) +* Added SIGINT handler for stlink cleanup ([#31](https://github.com/stlink-org/stlink/pull/31), [#135](https://github.com/stlink-org/stlink/pull/135)) (Release v1.0.0) Board support added for: diff --git a/cmake/packaging/deb/changelog b/cmake/packaging/deb/changelog index f4b644176..ec65e6744 100644 --- a/cmake/packaging/deb/changelog +++ b/cmake/packaging/deb/changelog @@ -1,49 +1,5 @@ -stlink (1.6.0+ds-1) unstable; urgency=medium +stlink (1.6.1+ds-1) unstable; urgency=medium - * Merge tag 'v1.6.0' into debian - * Bump Standards-Version to 4.5.0, no changes. - * Update libstlink1 symbols file for 1.6.0. + * Initial cpack-based package release for Debian/Ubuntu - -- Luca Boccassi Tue, 25 Feb 2020 22:08:33 +0000 - -stlink (1.5.1+ds-2) unstable; urgency=medium - - * Mark library packages as Multi-Arch: same. - * Apply cross.patch to fix cross-compiling the GUI. Thanks Helmut for the patch! (Closes: #941320) - * Vcs-Git: add -b debian - * Set Rules-Requires-Root: no - * Bump Standards-Version to 4.4.0 - - -- Luca Boccassi Sun, 29 Sep 2019 12:50:58 +0100 - -stlink (1.5.1+ds-1) unstable; urgency=medium - - * Merge tag 'v1.5.1' into debian. See upstream changelog for info: - https://github.com/stlink-org/stlink/releases/tag/v1.5.1 - * Mark packages as linux-any, other systems not supported. - - -- Luca Boccassi Fri, 28 Sep 2018 10:26:39 +0100 - -stlink (1.5.0+ds-1) unstable; urgency=medium - - * Upload to unstable. (Closes: #869421) - - -- Luca Boccassi Fri, 16 Mar 2018 16:56:17 +0000 - -stlink (1.4.0) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 01 Jul 2017 00:00:00 +0000 - -stlink (1.3.1) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 25 Feb 2017 00:00:00 +0000 - -stlink (1.3.0) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 28 Jan 2017 00:00:00 +0000 - -stlink (1.2.1) unstable; urgency=low - - * Initial Debian-Packaged Release. - - -- Andrew 'Necromant' Andrianov Sat, 09 Jul 2016 23:16:07 +0300 + -- Nightwalker-87 Sat, 06 Jun 2020 00:00:00 +0100 diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index d96746e65..9f17b0042 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -1,7 +1,7 @@ Source: stlink -Maintainer: Luca Bocassi +Maintainer: stlink-org Build-Depends: cmake, dh-cmake, debhelper (>= 9), libusb-1.0-0-dev, libgtk-3-dev -Standards-Version: 4.1.3 +Standards-Version: 4.5.0 Section: electronics Priority: optional Homepage: https://github.com/stlink-org/stlink diff --git a/cmake/packaging/deb/copyright b/cmake/packaging/deb/copyright index a14d4eb6e..fb1c49d74 100644 --- a/cmake/packaging/deb/copyright +++ b/cmake/packaging/deb/copyright @@ -1,9 +1,8 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink -Upstream-Contact: Luca Bocassi +Upstream-Contact: stlink-org Source: https://github.com/stlink-org/stlink -Disclaimer: -Comment: + Files: * Copyright: 2011-2020 stlink-org Martin Capitanio [capnm] diff --git a/cmake/packaging/deb/rules b/cmake/packaging/deb/rules index 2f80faeac..ae3abcabe 100755 --- a/cmake/packaging/deb/rules +++ b/cmake/packaging/deb/rules @@ -1,7 +1,7 @@ #!/usr/bin/make -f # See debhelper(7) (uncomment to enable) # output every command that modifies files on the build system. -DH_VERBOSE = 1 +#DH_VERBOSE = 1 # see EXAMPLES in dpkg-buildflags(1) and read /usr/share/dpkg/* DPKG_EXPORT_BUILDFLAGS = 1 @@ -15,5 +15,4 @@ export DEB_BUILD_MAINT_OPTIONS = hardening=+all override_dh_auto_configure: dh_auto_configure -- \ - -DLIB_INSTALL_DIR=/usr/lib/$(DEB_HOST_MULTIARCH) \ -DSTLINK_UDEV_RULES_DIR='/lib/udev/rules.d' diff --git a/cmake/packaging/rpm/changelog b/cmake/packaging/rpm/changelog index de2400d65..564bd95ae 100644 --- a/cmake/packaging/rpm/changelog +++ b/cmake/packaging/rpm/changelog @@ -1,2 +1,2 @@ -* Mon Jun 01 2020 Vasiliy Glazov - 1.6.1 -- Initial RPM-packaged release +* Mon Jun 01 2020 Nightwalker-87 - 1.6.1 +- Initial cpack-based RPM package release diff --git a/doc/version_support.md b/doc/version_support.md index 4d1f724f7..4076fb422 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -68,7 +68,7 @@ NOTE: In order to use a STLINK/v1 programmer on macOS, versions 10.13, 10.14 or ## Unsupported Operating Systems (as of Release v1.6.1) -| Operating System | libusb
      version | cmake
      version | End of OS-Support | Notes | +| Operating System | libusb
      version | cmake
      version | End of
      OS-Support | Notes | | --- | --- | --- | --- | --- | | CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but
      `libusb`-codebase is used | | Debian 8 (Jessie) | 1.0.**19** | 3.**0.2** | Jun 2020 | From 31b1fa16201521e2aaf464576f2f169981abede0 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 28 Jun 2020 21:01:59 +0200 Subject: [PATCH 0992/1435] Fixed install paths (headers & stlink-gui.ui) --- CMakeLists.txt | 4 ++-- src/stlink-gui/CMakeLists.txt | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 5171628ad..fae458dd7 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -86,7 +86,7 @@ include_directories(src/st-flash) include_directories(src/stlink-lib) ## Set installation directory for header files -set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR} CACHE PATH "Main include install directory") +set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} CACHE PATH "Main include install directory") ## Subordinate CMakeLists for version config & header installation add_subdirectory(inc) @@ -147,7 +147,7 @@ endif () set(STLINK_LIBRARY_PATH ${CMAKE_INSTALL_LIBDIR} CACHE PATH "Main library install directory") # Set the environment variable LD_LIBRARY_PATH to point to /usr/local/lib (per default). -execute_process (COMMAND bash -c "export LD_LIBRARY_PATH=${CMAKE_INSTALL_LIBDIR}") +execute_process(COMMAND bash -c "export LD_LIBRARY_PATH=${CMAKE_INSTALL_LIBDIR}") ### diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 89e5403d8..258f83cc1 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -33,9 +33,9 @@ if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) ## stlink-gui add_executable(stlink-gui ${GUI_SOURCES}) - install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_BINDIR}) + install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}) set_target_properties(stlink-gui PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin") + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) endif () From 66c6696337c2e6e3db5036422e0cd10726b428ab Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 28 Jun 2020 22:48:30 +0200 Subject: [PATCH 0993/1435] Corrected settings for deb pkg distribution --- cmake/packaging/deb/changelog | 50 +--------- cmake/packaging/deb/control | 7 +- cmake/packaging/deb/copyright | 8 +- cmake/packaging/deb/rules | 3 +- debian/changelog | 122 +---------------------- debian/control | 22 ++--- debian/copyright | 178 ++++++---------------------------- debian/libstlink-dev.install | 1 - debian/stlink-gui.install | 6 +- debian/stlink.pc.in | 2 +- 10 files changed, 58 insertions(+), 341 deletions(-) diff --git a/cmake/packaging/deb/changelog b/cmake/packaging/deb/changelog index f4b644176..196da940e 100644 --- a/cmake/packaging/deb/changelog +++ b/cmake/packaging/deb/changelog @@ -1,49 +1,5 @@ -stlink (1.6.0+ds-1) unstable; urgency=medium +stlink (1.6.1) unstable; urgency=medium - * Merge tag 'v1.6.0' into debian - * Bump Standards-Version to 4.5.0, no changes. - * Update libstlink1 symbols file for 1.6.0. + * Initial Debian-packaged Release. - -- Luca Boccassi Tue, 25 Feb 2020 22:08:33 +0000 - -stlink (1.5.1+ds-2) unstable; urgency=medium - - * Mark library packages as Multi-Arch: same. - * Apply cross.patch to fix cross-compiling the GUI. Thanks Helmut for the patch! (Closes: #941320) - * Vcs-Git: add -b debian - * Set Rules-Requires-Root: no - * Bump Standards-Version to 4.4.0 - - -- Luca Boccassi Sun, 29 Sep 2019 12:50:58 +0100 - -stlink (1.5.1+ds-1) unstable; urgency=medium - - * Merge tag 'v1.5.1' into debian. See upstream changelog for info: - https://github.com/stlink-org/stlink/releases/tag/v1.5.1 - * Mark packages as linux-any, other systems not supported. - - -- Luca Boccassi Fri, 28 Sep 2018 10:26:39 +0100 - -stlink (1.5.0+ds-1) unstable; urgency=medium - - * Upload to unstable. (Closes: #869421) - - -- Luca Boccassi Fri, 16 Mar 2018 16:56:17 +0000 - -stlink (1.4.0) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 01 Jul 2017 00:00:00 +0000 - -stlink (1.3.1) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 25 Feb 2017 00:00:00 +0000 - -stlink (1.3.0) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 28 Jan 2017 00:00:00 +0000 - -stlink (1.2.1) unstable; urgency=low - - * Initial Debian-Packaged Release. - - -- Andrew 'Necromant' Andrianov Sat, 09 Jul 2016 23:16:07 +0300 + -- Nightwalker-87 Mon, 01 Jun 2020 00:00:00 +0100 diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index d96746e65..759668ba6 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -1,9 +1,10 @@ Source: stlink -Maintainer: Luca Bocassi +Priority: optional +Maintainer: stlink-org Build-Depends: cmake, dh-cmake, debhelper (>= 9), libusb-1.0-0-dev, libgtk-3-dev -Standards-Version: 4.1.3 +Standards-Version: 4.5.0 +Rules-Requires-Root: no Section: electronics -Priority: optional Homepage: https://github.com/stlink-org/stlink Vcs-Git: https://github.com/stlink-org/stlink.git Vcs-Browser: https://github.com/stlink-org/stlink diff --git a/cmake/packaging/deb/copyright b/cmake/packaging/deb/copyright index a14d4eb6e..f5dfdc51b 100644 --- a/cmake/packaging/deb/copyright +++ b/cmake/packaging/deb/copyright @@ -1,9 +1,9 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink -Upstream-Contact: Luca Bocassi +Upstream-Contact: Nightwalker-87 Source: https://github.com/stlink-org/stlink -Disclaimer: -Comment: +Files-Excluded: stlinkv1_macos_driver + Files: * Copyright: 2011-2020 stlink-org Martin Capitanio [capnm] @@ -11,7 +11,7 @@ Copyright: 2011-2020 stlink-org Jerry Jacobs [xor-gate] [Nightwalker-87] and many others... - A list of contributors can be found in "contributors.txt". + An extended list of contributors can be found in "contributors.txt". License: BSD-3-clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: diff --git a/cmake/packaging/deb/rules b/cmake/packaging/deb/rules index 2f80faeac..ae3abcabe 100755 --- a/cmake/packaging/deb/rules +++ b/cmake/packaging/deb/rules @@ -1,7 +1,7 @@ #!/usr/bin/make -f # See debhelper(7) (uncomment to enable) # output every command that modifies files on the build system. -DH_VERBOSE = 1 +#DH_VERBOSE = 1 # see EXAMPLES in dpkg-buildflags(1) and read /usr/share/dpkg/* DPKG_EXPORT_BUILDFLAGS = 1 @@ -15,5 +15,4 @@ export DEB_BUILD_MAINT_OPTIONS = hardening=+all override_dh_auto_configure: dh_auto_configure -- \ - -DLIB_INSTALL_DIR=/usr/lib/$(DEB_HOST_MULTIARCH) \ -DSTLINK_UDEV_RULES_DIR='/lib/udev/rules.d' diff --git a/debian/changelog b/debian/changelog index f1265ee32..c54850340 100644 --- a/debian/changelog +++ b/debian/changelog @@ -44,7 +44,7 @@ stlink (1.5.1+ds-2) unstable; urgency=medium stlink (1.5.1+ds-1) unstable; urgency=medium * Merge tag 'v1.5.1' into debian. See upstream changelog for info: - https://github.com/texane/stlink/releases/tag/v1.5.1 + https://github.com/stlink-org/stlink/releases/tag/v1.5.1 * Mark packages as linux-any, other systems not supported. -- Luca Boccassi Fri, 28 Sep 2018 10:26:39 +0100 @@ -55,131 +55,19 @@ stlink (1.5.0+ds-1) unstable; urgency=medium -- Luca Boccassi Fri, 16 Mar 2018 16:56:17 +0000 -stlink (1.5.0) unstable; urgency=medium - - [ Jerry Jacobs ] - * README.md: Update version badge to v1.4.0 - - [ Viallard Anthony ] - * Add support of STM32L496xx/4A6xx devices (#615) - - [ rdlim ] - * Fix verification of flash error for STM32L496x device (#617) (#618) - - [ dflogeras ] - * Add note about availability in Gentoo package manager (#622) - - [ yaofei zheng ] - * update debian package version (#630) - - [ Lyle Cheatham ] - * Minor formatting fix in FAQ section of README.md (#631) - - [ Vasiliy Glazov ] - * README.md: Added information about Fedora and RedHat/CentOS packages. - (#635) - * Added LIB_INSTALL_DIR to correct libs install on 64-bit systems (#636) - - [ Gwenhael Goavec-Merou ] - * fix write for microcontroler with RAM size less or equal to 32K (#637) - - [ Mateusz Krawiec ] - * Fix memory map for stm32l496xx boards. (#639) - - [ Rüdiger Fortanier ] - * Add unknown chip output (#641) - - [ Slyshyk Oleksiy ] - * fix __FILE__ base name extraction, #628 (#648) - - [ texane ] - * STM32F72xx73xx support, from bob.feretich@rafresearch.com - - [ Kirill Kolyshkin ] - * debian/triggers: add (to run ldconfig) (#664) - - [ Slyshyk Oleksiy ] - * Try to fix #666 issue (#667) - * Try to fix 666 issue (#668) - - [ Jerry Jacobs ] - * Update ChangeLog.md - * Update README.md - - [ texane ] - * STM32F042K6 Nucleo-32 Board reported to work, by frank@bauernoeppel.de - - [ Anatol Pomozov ] - * Update .version file to match release number (#670) - - -- Anatol Pomozov Mon, 19 Feb 2018 11:00:29 -0800 - -libstlink (1.4.0) unstable; urgency=low - - * Major changes and added features - - Add support for STM32L452 target (#608) - - Initial support to compile with Microsoft Visual Studio 2017 (#602) - - Added support for flashing second bank on STM32F10x_XL (#592) - - Add support for STM32L011 target (#572) - - Allow building of debian package with CPack (@xor-gate) - * Updates and fixes - - Fix compilation with GCC 7 (#590) - - Skip GTK detection if we're cross-compiling (#588) - - Fix possible memory leak (#570) - - Fix building with mingw64 (#569, #610) - - Update libusb to 1.0.21 for Windows (#562) - - Fixing low-voltage flashing on STM32F7 parts. (#567) - - Update libusb to 1.0.21 for Windows (#562) +stlink (1.4.0) unstable; urgency=low -- Andrew 'Necromant' Andrianov Sat, 01 Jul 2017 00:00:00 +0000 -libstlink (1.3.1) unstable; urgency=low - - * Major changes and added features: - - Add preliminary support for STM32L011 to see it after probe (chipid 0x457) (@xor-gate) - - Strip full paths to source files in log (commit #2c0ab7f) - - Add support for STM32F413 target (#549) - - Add support for Semihosting SYS_READC (#546) - * Updates and fixes: - - Update documentation markdown files - - Compilation fixes (#552) - - Fix compilation when path includes spaces (#561) +stlink (1.3.1) unstable; urgency=low -- Andrew 'Necromant' Andrianov Sat, 25 Feb 2017 00:00:00 +0000 -libstlink (1.3.0) unstable; urgency=low - - * Major changes and added features: - - Deprecation of autotools (autoconf, automake) (@xor-gate) - - Removal of undocumented st-term utility, which is now replaced by st-util ARM semihosting feature (#3fd0f09) - - Add support for native debian packaging (#444, #485) - - Add intel hex file reading for st-flash (#459) - - Add --reset command to st-flash (#505) - - Support serial numbers argument for st-util and st-flash for multi-programmer setups (#541) - - Add kill ('k') command to gdb-server for st-util (#9804416) - - Add manpages (generated with pandoc from Markdown) (#464) - - Rewrite commandline parsing for st-flash (#459) - - Add support for ARM semihosting to st-util (#454, #455) - * Chip support added for: - - STM32L432 (#501) - - STM32F412 (#538) - - STM32F410 (#9c635e4) - - Add memory map for STM32F401XE (#460) - - L0x Category 5 devices (#406) - - Add L0 Category 2 device (chip id: 0x425) (#72b8e5e) - * Updates and fixes: - - Fixed STM32F030 erase error (#442) - - Fixed Cygwin build (#68b0f3b) - - Reset flash mass erase (MER) bit after mass erase for safety (#489) - - Fix memory map for STM32F4 (@zulusw) - - Fix STM32L-problem with flash loader (issue #390) (Tom de Boer) - - st-util don't read target voltage on startup as it crashes STM32F100 (probably stlink/v1) (Greg Alexander) - - Do a JTAG reset prior to reading CPU information when processor is in deep sleep (@andyg24) - - Redesign of st-flash commandline options parsing (pull-request #459) (@dev26th) +stlink (1.3.0) unstable; urgency=low -- Andrew 'Necromant' Andrianov Sat, 28 Jan 2017 00:00:00 +0000 -libstlink (1.2.1) unstable; urgency=low +stlink (1.2.1) unstable; urgency=low * Initial Debian-Packaged Release. diff --git a/debian/control b/debian/control index 3ac6af91f..598e0e89f 100644 --- a/debian/control +++ b/debian/control @@ -14,9 +14,7 @@ Section: libdevel Architecture: linux-any Multi-Arch: same Depends: libstlink1 (= ${binary:Version}), ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Description: Open source STM32 MCU programming toolset. . This package contains the development files for stlink. @@ -25,28 +23,22 @@ Section: libs Architecture: linux-any Multi-Arch: same Depends: ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Description: Open source STM32 MCU programming toolset. . This package contains the shared library for stlink. Package: stlink-tools Architecture: linux-any Depends: libstlink1 (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Description: Open source STM32 MCU programming toolset. . - This package contains commandline utilities for stlink, and modprobe and - udev rules. + This package contains commandline utilities for stlink, modprobe- and + udev-rules. Package: stlink-gui Architecture: linux-any Depends: libstlink1 (= ${binary:Version}), stlink-tools (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Description: Open source STM32 MCU programming toolset. . - This package contains a GUI tool for stlink. + This package contains a GUI for stlink. diff --git a/debian/copyright b/debian/copyright index 1a0febd9c..8329cc250 100644 --- a/debian/copyright +++ b/debian/copyright @@ -1,155 +1,37 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink -Upstream-Contact: Andrew 'Necromant' Andrianov +Upstream-Contact: Luca Boccassi Source: https://github.com/stlink-org/stlink -Comment: Upstream tarball has been repackaged to remove binary OSX kernel - drivers that are of unknown license and of no use to Debian. Files-Excluded: stlinkv1_macos_driver Files: * -Copyright: 2011-2018 agpanarin - 2011-2018 Alexey Cherevatenko - 2011-2018 Anatoli - 2011-2018 Andrea Mucignat - 2011-2018 Andrew 'Necromant' Andrianov - 2011-2018 Andrey Yurovsky - 2011-2018 Andy Isaacson - 2011-2018 Áron RADICS - 2011-2018 A Sheaff - 2011-2018 Björn Hauffe - 2011-2018 bob - 2011-2018 Breton M. Saunders - 2011-2018 Bruno Dal Bo - 2011-2018 Burns - 2011-2018 Chris Dew - 2011-2018 Chris Hiszpanski - 2011-2018 Chris Li - 2011-2018 Chris Samuelson - 2011-2018 Christophe Levantis - 2011-2018 Craig Lilley - 2011-2018 dandev37 - 2011-2018 Dan Hepler - 2011-2018 Daniel Campoverde [alx741] - 2011-2018 Daniel O'Connor - 2011-2018 Dave Flogeras - 2011-2018 Dave Murphy - 2011-2018 Dave Vandervies - 2011-2018 Denis Fokin - 2011-2018 Denis Osterland - 2011-2018 Dmitry Bravikov - 2011-2018 Efe Can İçöz - 2011-2018 Ethan Zonca - 2011-2018 Fabien Chouteau - 2011-2018 Fabien Le Mentec - 2011-2018 fhars - 2011-2018 Friedrich Beckmann - 2011-2018 Geoffrey Brown - 2011-2018 George Talusan - 2011-2018 Georg von Zengen - 2011-2018 giuseppe barba - 2011-2018 Greg Alexander - 2011-2018 Greg Meiste - 2011-2018 Hakkavélin - 2011-2018 htk - 2011-2018 Ian Griffiths <6thimage@gmail.com> - 2011-2018 Jack Peel - 2011-2018 Jakub Tyszkowski - 2011-2018 Jan Sarenik - 2011-2018 Jean-Luc Béchennec - 2011-2018 Jean-Marie Lemetayer - 2011-2018 Jeff Kent - 2011-2018 Jeffrey Nelson - 2011-2018 Jens Hoffmann - 2011-2018 Jerome Lambourg - 2011-2018 Jerry Jacobs - 2011-2018 Jim Paris - 2011-2018 Jiří Netolický - 2011-2018 jnosky - 2011-2018 jnosky - 2011-2018 JohannesTaelman - 2011-2018 Jonas Danielsson - 2011-2018 Jonas Norling - 2011-2018 Josh Bialkowski - 2011-2018 Karl Palsson - 2011-2018 kevin - 2011-2018 Kyle Manna - 2011-2018 Lari Lehtomäki - 2011-2018 le mentec fabien - 2011-2018 Martin Nowak - 2011-2018 Matteo Collina - 2011-2018 Max Chen - 2011-2018 Maxime Coquelin - 2011-2018 Maxime Vincent - 2011-2018 Michael Pratt - 2011-2018 Michael Sparmann - 2011-2018 Mike Szczys - 2011-2018 mlundinse - 2011-2018 mux - 2011-2018 Ned Konz - 2011-2018 Nic McDonald - 2011-2018 Nicolas Schodet - 2011-2018 Nikolay - 2011-2018 nullsub - 2011-2018 Olivier Croquette - 2011-2018 Olivier Gay - 2011-2018 Onno Kortmann - 2011-2018 orangeudav - 2011-2018 Pavel Kirienko - 2011-2018 Pekka Nikander - 2011-2018 Pete - 2011-2018 Peter Zotov - 2011-2018 Petteri Aimonen - 2011-2018 Piotr Haber - 2011-2018 Rene Hopf - 2011-2018 Robin Kreis - 2011-2018 Rob Spanton - 2011-2018 Rytis Karpuska - 2011-2018 Sean Simmons - 2011-2018 Sergey Alirzaev - 2011-2018 Simon Wright - 2011-2018 Stany MARCEL - 2011-2018 Stefan Misik - 2011-2018 Sven Wegener - 2011-2018 Tectu - 2011-2018 tekaikko - 2011-2018 texane - 2011-2018 Theodore A. Roth - 2011-2018 Thomas Gärtner - 2011-2018 Tobias Badertscher - 2011-2018 Tom de Boer - 2011-2018 Tristan Gingold - 2011-2018 Uli Köhler - 2011-2018 Uwe Bonnes - 2011-2018 Vadim Kaushan - 2011-2018 Vegard Storheil Eriksen - 2011-2018 Viacheslav Dobromyslov - 2011-2018 Victor Mayoral Vilches - 2011-2018 Wojciech A. Koszek - 2011-2018 Woodrow Douglass - 2011-2018 The "Capt'ns Missing Link" Authors. +Copyright: 2011-2020 stlink-org + Martin Capitanio [capnm] + Fabien Le Mentec [texane] + Jerry Jacobs [xor-gate] + [Nightwalker-87] + and many others... + An extended list of contributors can be found in "contributors.txt". License: BSD-3-clause - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions - are met: - . - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in - the documentation and/or other materials provided with the - distribution. - * Neither the name of Intel Corporation nor the names of its - contributors may be used to endorse or promote products derived - from this software without specific prior written permission. - . - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + . + 1. Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + 3. Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + . + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/debian/libstlink-dev.install b/debian/libstlink-dev.install index 0c3543cd9..4e0e0d184 100644 --- a/debian/libstlink-dev.install +++ b/debian/libstlink-dev.install @@ -2,4 +2,3 @@ usr/include/* usr/lib/*/lib*.a usr/lib/*/pkgconfig/* usr/lib/*/lib*.so - diff --git a/debian/stlink-gui.install b/debian/stlink-gui.install index 5620a25e5..96c55213f 100644 --- a/debian/stlink-gui.install +++ b/debian/stlink-gui.install @@ -1,4 +1,4 @@ /usr/bin/stlink-gui -/usr/bin/stlink-gui.ui /usr/share/stlink/ -/usr/share/stlink/applications/stlink-gui.desktop /usr/share/applications/ -/usr/share/stlink/icons/hicolor/scalable/apps/stlink-gui.svg /usr/share/icons/hicolor/scalable/apps/stlink-gui.svg +/usr/share/stlink/stlink-gui.ui +/usr/share/applications/stlink-gui.desktop +/usr/share/icons/hicolor/scalable/apps/stlink-gui.svg diff --git a/debian/stlink.pc.in b/debian/stlink.pc.in index 7fde2d968..9f740ba09 100644 --- a/debian/stlink.pc.in +++ b/debian/stlink.pc.in @@ -3,7 +3,7 @@ includedir=${prefix}/include/stlink libdir=${prefix}/lib/@DEB_HOST_MULTIARCH@ Name: stlink -Description: Open source version of the STMicroelectronics Stlink Tools +Description: Open source STM32 MCU programming toolset Version: @VERSION@ Requires: libusb-1.0 Libs: -L${libdir} -lstlink From 2694214df73557ef30ed234845a0d0f4de9df56b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 29 Jun 2020 08:48:43 +0200 Subject: [PATCH 0994/1435] Corrected install paths & changelog files - man-pages - desktop-file and icons - Fix for external CMAKE_MODULE_PATH - udev-rules - headers & stlink-gui.ui --- CHANGELOG.md | 3 ++- CMakeLists.txt | 15 +++++++++++---- cmake/packaging/deb/changelog | 4 ++-- cmake/packaging/rpm/changelog | 4 ++-- doc/man/CMakeLists.txt | 2 +- doc/version_support.md | 2 +- src/stlink-gui/CMakeLists.txt | 8 ++++---- 7 files changed, 23 insertions(+), 15 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 3195bae3c..7717ca6f4 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -19,7 +19,7 @@ Features: * Support for STM32L1, SM32L4 option bytes write ([#596](https://github.com/stlink-org/stlink/pull/596), [#844](https://github.com/stlink-org/stlink/pull/844), [#847](https://github.com/stlink-org/stlink/pull/847)) * Added CMAKEFLAGS and install target ([#804](https://github.com/stlink-org/stlink/pull/804), [#935](https://github.com/stlink-org/stlink/pull/935)) * Support for STM32G4 ([#822](https://github.com/stlink-org/stlink/pull/822)) -* Add aliased SRAM2 region in the L496 memory map ([#824](https://github.com/stlink-org/stlink/pull/824)) +* Added aliased SRAM2 region in the L496 memory map ([#824](https://github.com/stlink-org/stlink/pull/824)) * Improved support for STM32G0 ([#825](https://github.com/stlink-org/stlink/pull/825), [#850](https://github.com/stlink-org/stlink/pull/850), [#856](https://github.com/stlink-org/stlink/pull/856), [#857](https://github.com/stlink-org/stlink/pull/857)) * Added postinst script with 'depmod -a' for 'make package' ([#845](https://github.com/stlink-org/stlink/pull/845), [#931](https://github.com/stlink-org/stlink/pull/931)) * Calculate checksums for flash operations ([#862](https://github.com/stlink-org/stlink/pull/862), [#924](https://github.com/stlink-org/stlink/pull/924)) @@ -358,6 +358,7 @@ Chip support added for: * STM32F469/STM32F479 ([#345](https://github.com/stlink-org/stlink/pull/345), [#555](https://github.com/stlink-org/stlink/pull/555)) (Release v1.2.0) * STM32L1xx Cat.2 devices (Nicolas Schodet) * STM32L1xx (chip-ID 0x427) ([#152](https://github.com/stlink-org/stlink/pull/152), [#163](https://github.com/stlink-org/stlink/pull/163), [#165](https://github.com/stlink-org/stlink/pull/165)) (Release v1.0.0) +* Added SIGINT handler for stlink cleanup ([#31](https://github.com/stlink-org/stlink/pull/31), [#135](https://github.com/stlink-org/stlink/pull/135)) (Release v1.0.0) Board support added for: diff --git a/CMakeLists.txt b/CMakeLists.txt index 86282775e..096291b88 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,7 +4,7 @@ cmake_minimum_required(VERSION 3.4.2) cmake_policy(SET CMP0042 NEW) -set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_SOURCE_DIR}/cmake/modules") +set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) @@ -94,6 +94,13 @@ include_directories(${PROJECT_SOURCE_DIR}/include/stlink/tools) include_directories(src) include_directories(src/tools) ### TODO: Clean this up... +## Set installation directory for header files +set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} CACHE PATH "Main include install directory") + +## Subordinate CMakeLists for version config & header installation +#add_subdirectory(inc) + +## Define source- and headerfiles for stlink library set(STLINK_HEADERS include/stlink.h include/stlink/backend.h @@ -143,7 +150,7 @@ endif () set(STLINK_LIBRARY_PATH ${CMAKE_INSTALL_LIBDIR} CACHE PATH "Main library install directory") # Set the environment variable LD_LIBRARY_PATH to point to /usr/local/lib (per default). -execute_process (COMMAND bash -c "export LD_LIBRARY_PATH="${CMAKE_INSTALL_LIBDIR}" ") +execute_process(COMMAND bash -c "export LD_LIBRARY_PATH=${CMAKE_INSTALL_LIBDIR}") ### @@ -259,8 +266,8 @@ if (CMAKE_SYSTEM_NAME STREQUAL "Linux") set(STLINK_MODPROBED_DIR "/etc/modprobe.d" CACHE PATH "modprobe.d directory") install(FILES ${CMAKE_SOURCE_DIR}/config/modprobe.d/stlink_v1.conf DESTINATION ${STLINK_MODPROBED_DIR}) - ## Install udev rules files to /etc/udev/rules.d/ (explicitly hardcoded) - set(STLINK_UDEV_RULES_DIR "/etc/udev/rules.d" CACHE PATH "udev rules directory") + ## Install udev rules files to /lib/udev/rules.d/ (explicitly hardcoded) + set(STLINK_UDEV_RULES_DIR "/lib/udev/rules.d" CACHE PATH "udev rules directory") file(GLOB RULES_FILES ${CMAKE_SOURCE_DIR}/config/udev/rules.d/*.rules) install(FILES ${RULES_FILES} DESTINATION ${STLINK_UDEV_RULES_DIR}) endif () diff --git a/cmake/packaging/deb/changelog b/cmake/packaging/deb/changelog index 196da940e..997ed4056 100644 --- a/cmake/packaging/deb/changelog +++ b/cmake/packaging/deb/changelog @@ -1,5 +1,5 @@ -stlink (1.6.1) unstable; urgency=medium +stlink (1.6.1+ds-1) unstable; urgency=medium - * Initial Debian-packaged Release. + * Initial cpack-based package release for Debian/Ubuntu -- Nightwalker-87 Mon, 01 Jun 2020 00:00:00 +0100 diff --git a/cmake/packaging/rpm/changelog b/cmake/packaging/rpm/changelog index de2400d65..564bd95ae 100644 --- a/cmake/packaging/rpm/changelog +++ b/cmake/packaging/rpm/changelog @@ -1,2 +1,2 @@ -* Mon Jun 01 2020 Vasiliy Glazov - 1.6.1 -- Initial RPM-packaged release +* Mon Jun 01 2020 Nightwalker-87 - 1.6.1 +- Initial cpack-based RPM package release diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 23da9e150..9b3c50764 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -30,7 +30,7 @@ foreach (manpage ${MANPAGES}) endif () if (f AND NOT WIN32) - install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/man/man1) + install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/man/man1) unset(f) endif () endforeach () diff --git a/doc/version_support.md b/doc/version_support.md index 4d1f724f7..4076fb422 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -68,7 +68,7 @@ NOTE: In order to use a STLINK/v1 programmer on macOS, versions 10.13, 10.14 or ## Unsupported Operating Systems (as of Release v1.6.1) -| Operating System | libusb
      version | cmake
      version | End of OS-Support | Notes | +| Operating System | libusb
      version | cmake
      version | End of
      OS-Support | Notes | | --- | --- | --- | --- | --- | | CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but
      `libusb`-codebase is used | | Debian 8 (Jessie) | 1.0.**19** | 3.**0.2** | Jun 2020 | diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 8c36e5a1f..db29a72dd 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -13,11 +13,11 @@ if (NOT WIN32) # Install desktop application entry install(FILES stlink-gui.desktop - DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/applications) + DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/applications) # Install icons install(FILES icons/stlink-gui.svg - DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}/icons/hicolor/scalable/apps) + DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/icons/hicolor/scalable/apps) set(GUI_SOURCES gui.c gui.h) @@ -30,9 +30,9 @@ if (NOT WIN32) ## stlink-gui add_executable(stlink-gui ${GUI_SOURCES}) - install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_BINDIR}) + install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}) set_target_properties(stlink-gui PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin") + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) From 77652688f21253f94e23a7d1c02d5a5bf0008295 Mon Sep 17 00:00:00 2001 From: rutgerhendriks <3134550+rutgerhendriks@users.noreply.github.com> Date: Mon, 6 Jul 2020 09:37:32 +0200 Subject: [PATCH 0995/1435] Delete ccpp.yml Remove ccpp.yml from workflows --- .github/workflows/ccpp.yml | 17 ----------------- 1 file changed, 17 deletions(-) delete mode 100644 .github/workflows/ccpp.yml diff --git a/.github/workflows/ccpp.yml b/.github/workflows/ccpp.yml deleted file mode 100644 index 23aa0bfc5..000000000 --- a/.github/workflows/ccpp.yml +++ /dev/null @@ -1,17 +0,0 @@ -name: C/C++ CI - -on: - push: - branches: [ master ] - pull_request: - branches: [ master ] - -jobs: - build: - - runs-on: ubuntu-latest - - steps: - - uses: actions/checkout@v2 - - name: make - run: make From e273ec53e8cf2d3df68ada1095f39232f3d7b14f Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Mon, 6 Jul 2020 09:55:19 +0200 Subject: [PATCH 0996/1435] Revert changing all compiler warning preventions --- src/st-flash/flash.c | 48 +++++++++++++++++++-------------------- src/st-flash/flash_opts.c | 22 +++++++++--------- src/stlink-lib/usb.c | 1 - 3 files changed, 34 insertions(+), 37 deletions(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 128b8acc0..4bdc20a16 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -25,8 +25,7 @@ static void cleanup(int signum) { exit(1); } -static void usage(void) -{ +static void usage(void) { puts("command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] erase"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); @@ -60,13 +59,13 @@ int main(int ac, char** av) { return(-1); } - ILOG("st-flash %s\n", STLINK_VERSION); + printf("st-flash %s\n", STLINK_VERSION); sl = stlink_open_usb(o.log_level, 1, (char *)o.serial, o.freq); if (sl == NULL) { return(-1); } - if (STLINK_FLASH_TYPE_UNKNOWN == sl->flash_type) { + if (sl->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { printf("Failed to connect to target\n"); return(-1); } @@ -84,14 +83,14 @@ int main(int ac, char** av) { signal(SIGTERM, &cleanup); signal(SIGSEGV, &cleanup); - if (STLINK_DEV_DFU_MODE == stlink_current_mode(sl)) { + if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { if (stlink_exit_dfu_mode(sl)) { printf("Failed to exit DFU mode\n"); goto on_error; } } - if (STLINK_DEV_DEBUG_MODE != stlink_current_mode(sl)) { + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { if (stlink_enter_swd_mode(sl)) { printf("Failed to enter SWD mode\n"); goto on_error; @@ -113,7 +112,7 @@ int main(int ac, char** av) { } // disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 - if (STLINK_CHIPID_STM32_F4 == sl->chip_id) { + if (sl->chip_id == STLINK_CHIPID_STM32_F4) { memset(sl->q_buf, 0, 4); for (int i = 0; i < 8; i++) { @@ -136,10 +135,9 @@ int main(int ac, char** av) { goto on_error; } - if (FLASH_CMD_WRITE == o.cmd) // write - { + if (o.cmd == FLASH_CMD_WRITE) { // write size_t size = 0; - if (FLASH_FORMAT_IHEX == o.format) { + if (o.format == FLASH_FORMAT_IHEX) { err = stlink_parse_ihex(o.filename, stlink_get_erased_pattern(sl), &mem, &size, &o.addr); if (err == -1) { @@ -149,7 +147,7 @@ int main(int ac, char** av) { } if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { - if (FLASH_FORMAT_IHEX == o.format) { + if (o.format == FLASH_FORMAT_IHEX) { err = stlink_mwrite_flash(sl, mem, (uint32_t)size, o.addr); } else { err = stlink_fwrite_flash(sl, o.filename, o.addr); @@ -161,7 +159,7 @@ int main(int ac, char** av) { } } else if ((o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { - if (FLASH_FORMAT_IHEX == o.format) { + if (o.format == FLASH_FORMAT_IHEX) { err = stlink_mwrite_sram(sl, mem, (uint32_t)size, o.addr); } else { err = stlink_fwrite_sram(sl, o.filename, o.addr); @@ -179,7 +177,7 @@ int main(int ac, char** av) { printf("stlink_fwrite_option_bytes() == -1\n"); goto on_error; } - } else if (FLASH_OPTION_BYTES == o.area) { + } else if (o.area == FLASH_OPTION_BYTES) { if (o.val == 0) { printf("attempting to set option byte to 0, abort.\n"); goto on_error; @@ -191,15 +189,15 @@ int main(int ac, char** av) { printf("stlink_write_option_bytes32() == -1\n"); goto on_error; } - } else if (FLASH_OPTCR == o.area) { + } else if (o.area == FLASH_OPTCR) { DLOG("@@@@ Write %d (%0#10x) to option control register\n", o.val, o.val); err = stlink_write_option_control_register32(sl, o.val); - } else if (FLASH_OPTCR1 == o.area) { + } else if (o.area == FLASH_OPTCR1) { DLOG("@@@@ Write %d (%0#10x) to option control register 1\n", o.val, o.val); err = stlink_write_option_control_register1_32(sl, o.val); - } else if (FLASH_OPTION_BYTES_BOOT_ADD == o.area) { + } else if (o.area == FLASH_OPTION_BYTES_BOOT_ADD) { DLOG("@@@@ Write %d (%0#10x) to option bytes boot address\n", o.val, o.val); err = stlink_write_option_bytes_boot_add32(sl, o.val); @@ -208,14 +206,14 @@ int main(int ac, char** av) { printf("Unknown memory region\n"); goto on_error; } - } else if (FLASH_CMD_ERASE == o.cmd) { + } else if (o.cmd == FLASH_CMD_ERASE) { err = stlink_erase_flash_mass(sl); if (err == -1) { printf("stlink_erase_flash_mass() == -1\n"); goto on_error; } - } else if (CMD_RESET == o.cmd) { + } else if (o.cmd == CMD_RESET) { if (sl->version.stlink_v > 1) { if (stlink_jtag_reset(sl, 2)) { printf("Failed to reset JTAG\n"); @@ -228,20 +226,20 @@ int main(int ac, char** av) { goto on_error; } } else { // read - if ((FLASH_MAIN_MEMORY == o.area) || (FLASH_SYSTEM_MEMORY == o.area)) { + if ((o.area == FLASH_MAIN_MEMORY) || (o.area == FLASH_SYSTEM_MEMORY)) { if ((o.size == 0) && (o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { o.size = sl->flash_size; } else if ((o.size == 0) && (o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { o.size = sl->sram_size; } - err = stlink_fread(sl, o.filename, FLASH_FORMAT_IHEX == o.format, o.addr, o.size); + err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); if (err == -1) { printf("stlink_fread() == -1\n"); goto on_error; } - } else if (FLASH_OPTION_BYTES == o.area) { + } else if (o.area == FLASH_OPTION_BYTES) { uint8_t remaining_option_length = sl->option_size / 4; DLOG("@@@@ Read %d (%#x) option bytes from %#10x\n", remaining_option_length, remaining_option_length, sl->option_base); @@ -249,7 +247,7 @@ int main(int ac, char** av) { if (0 == o.size) { o.size = sl->option_size; } - err = stlink_fread(sl, o.filename, FLASH_FORMAT_IHEX == o.format, sl->option_base, o.size); + err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, sl->option_base, o.size); } else { uint32_t option_byte = 0; err = stlink_read_option_bytes32(sl, &option_byte); @@ -260,7 +258,7 @@ int main(int ac, char** av) { printf("%08x\n", option_byte); } } - } else if (FLASH_OPTION_BYTES_BOOT_ADD == o.area) { + } else if (o.area == FLASH_OPTION_BYTES_BOOT_ADD) { uint32_t option_byte = 0; err = stlink_read_option_bytes_boot_add32(sl, &option_byte); if (err == -1) { @@ -269,7 +267,7 @@ int main(int ac, char** av) { } else { printf("%08x\n",option_byte); } - } else if (FLASH_OPTCR == o.area) { + } else if (o.area == FLASH_OPTCR) { uint32_t option_byte = 0; err = stlink_read_option_control_register32(sl, &option_byte); if (err == -1) { @@ -278,7 +276,7 @@ int main(int ac, char** av) { } else { printf("%08x\n",option_byte); } - } else if (FLASH_OPTCR1 == o.area) { + } else if (o.area == FLASH_OPTCR1) { uint32_t option_byte = 0; err = stlink_read_option_control_register1_32(sl, &option_byte); if (err == -1) { diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 6653c6e62..1cfd6fe89 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -274,7 +274,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { break; case FLASH_CMD_READ: // expect filename, addr and size - if ((FLASH_MAIN_MEMORY == o->area) || (FLASH_SYSTEM_MEMORY == o->area)) { + if ((o->area == FLASH_MAIN_MEMORY) || (o->area == FLASH_SYSTEM_MEMORY)) { if (ac != 3) { return invalid_args("read "); } o->filename = av[0]; @@ -295,12 +295,12 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } break; - } else if ((FLASH_OTP == o->area)) { + } else if ((o->area == FLASH_OTP)) { return bad_arg("TODO: otp not implemented yet"); if (ac > 1) { return invalid_args("otp read: [path]"); } if (ac > 0) { o->filename = av[0]; } break; - } else if ((FLASH_OPTION_BYTES == o->area)) { + } else if ((o->area == FLASH_OPTION_BYTES)) { if (ac > 2) { return invalid_args("option bytes read: [path] [size]"); } if (ac > 0) { o->filename = av[0]; } if (ac > 1) { @@ -313,13 +313,13 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } } break; - } else if ((FLASH_OPTION_BYTES_BOOT_ADD == o->area)) { + } else if ((o->area == FLASH_OPTION_BYTES_BOOT_ADD)) { if (ac > 0) { return invalid_args("option bytes boot_add read"); } break; - } else if ((FLASH_OPTCR == o->area)) { + } else if ((o->area == FLASH_OPTCR)) { if (ac > 0) { return invalid_args("option control register read"); } break; - } else if ((FLASH_OPTCR1 == o->area)) { + } else if ((o->area == FLASH_OPTCR1)) { if (ac > 0) { return invalid_args("option control register 1 read"); } break; } @@ -328,7 +328,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { case FLASH_CMD_WRITE: // TODO: should be boot add 0 and boot add 1 uint32 - if (FLASH_OPTION_BYTES == o->area) { // expect filename and optional address + if (o->area == FLASH_OPTION_BYTES) { // expect filename and optional address if (ac >=1 && ac <= 2) { o->filename = av[0]; } else { @@ -344,7 +344,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { o->addr = (stm32_addr_t) addr; } } - } else if (FLASH_OPTION_BYTES_BOOT_ADD == o->area) { // expect option bytes boot address + } else if (o->area == FLASH_OPTION_BYTES_BOOT_ADD) { // expect option bytes boot address if (ac != 1) { return invalid_args("option bytes boot_add write "); } uint32_t val; @@ -355,7 +355,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } else { o->val = (uint32_t)val; } - } else if (FLASH_OPTCR == o->area) { // expect option control register value + } else if (o->area == FLASH_OPTCR) { // expect option control register value if (ac != 1) { return invalid_args("option control register write "); } uint32_t val; @@ -366,7 +366,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } else { o->val = (uint32_t) val; } - } else if (FLASH_OPTCR1 == o->area) { // expect option control register 1 value + } else if (o->area == FLASH_OPTCR1) { // expect option control register 1 value if (ac != 1) { return invalid_args("option control register 1 write "); } uint32_t val; @@ -376,7 +376,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } else { o->val = (uint32_t) val; } - } else if (FLASH_FORMAT_BINARY == o->format) { // expect filename and addr + } else if (o->format == FLASH_FORMAT_BINARY) { // expect filename and addr if (ac != 2) { return invalid_args("write "); } o->filename = av[0]; diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index a7875eb57..f9b4775f3 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -710,7 +710,6 @@ int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_READMEM_32BIT; - DLOG("using address %#010x\n", addr); write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); size = send_recv(slu, 1, cmd, slu->cmd_len, data, len); From ca02a8d507430e2a45e5c6fa9b019ab042c91770 Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Mon, 6 Jul 2020 10:07:26 +0200 Subject: [PATCH 0997/1435] src/st-flash/flash.c: improved error message --- src/st-flash/flash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 4bdc20a16..9116f9c80 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -236,7 +236,7 @@ int main(int ac, char** av) { err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, o.addr, o.size); if (err == -1) { - printf("stlink_fread() == -1\n"); + printf("could not read main memory (%d)\n", err); goto on_error; } } else if (o.area == FLASH_OPTION_BYTES) { From ebb3164d903f9780beaf6d5f7c95b27f2b64ddc1 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 18 Jul 2020 00:46:26 +0200 Subject: [PATCH 0998/1435] Updated CHANGELOG & README --- CHANGELOG.md | 27 ++++++++++++++++++++++++++- README.md | 8 +++++--- 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 7717ca6f4..5ad1ec2d4 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,31 @@ stlink ChangeLog ================ +v1.6.2 +====== + +Release date: (TBD) + +Features: + +Updates & changes: + +* [doc] st-flash --reset parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) +* [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) +* Imported debian pkg-settings ([#986](https://github.com/stlink-org/stlink/pull/986)) +* Add support for FreeBSD's libusb reimplementation ([#992](https://github.com/stlink-org/stlink/pull/992), [#993](https://github.com/stlink-org/stlink/pull/993)) + +Fixes: + +* [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) +* cmake compile failure with external CMAKE_MODULE_PATH set ([#962](https://github.com/stlink-org/stlink/pull/962)) +* doc/man: Fixed installation directory ([#970](https://github.com/stlink-org/stlink/pull/970)) +* Fixed installation path for desktop-file and icons ([#972](https://github.com/stlink-org/stlink/pull/972)) +* Fix for static linking of libssp ([#973](https://github.com/stlink-org/stlink/pull/973), [#974](https://github.com/stlink-org/stlink/pull/974)) +* Fixed connect under reset for st-flash and st-util ([#983](https://github.com/stlink-org/stlink/pull/983)) +* Fix for mmap() size_t overflow in st-flash ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) + + v1.6.1 ====== @@ -139,7 +164,7 @@ Updates and fixes: * Fixed relative path to the UI files needed by stlink-gui-local (GUI) ([#770](https://github.com/stlink-org/stlink/pull/770), [#771](https://github.com/stlink-org/stlink/pull/771)) * Added howto for sending NRST signal through GDB ([#774](https://github.com/stlink-org/stlink/pull/774), [#776](https://github.com/stlink-org/stlink/pull/776), [#779](https://github.com/stlink-org/stlink/pull/779)) * Fixed package name "devscripts" in doc/compiling.md ([#775](https://github.com/stlink-org/stlink/pull/775)) -* Fixed few potential memory/resource leaks ([#803](https://github.com/stlink-org/stlink/pull/803)) +* Fixed few potential memory/resource leaks ([#803](https://github.com/stlink-org/stlink/pull/803), [#831](https://github.com/stlink-org/stlink/pull/831)) * Updated Linux source repositories in README.md: Debian and Ubuntu ([#821](https://github.com/stlink-org/stlink/pull/821), [#835](https://github.com/stlink-org/stlink/pull/835), [#859](https://github.com/stlink-org/stlink/pull/859)) * Do not issue JTAG reset on stlink-v1 ([#828](https://github.com/stlink-org/stlink/pull/828)) * Fixed flash size of STM32 Discovery vl ([#829](https://github.com/stlink-org/stlink/pull/829)) diff --git a/README.md b/README.md index 21ab9f48b..5be842156 100644 --- a/README.md +++ b/README.md @@ -23,7 +23,7 @@ The stlink library and tools are licensed under the **[BSD-3 License](LICENSE.md STLink is an open source toolset to program and debug STM32 devices and boards manufactured by STMicroelectronics. It supports several so called STLINK programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG/SWD. There are four generations available on the market which are _all_ supported by this toolset: -* **STLINK/v1** _(obsolete as of 21-11-2019)_ +* **STLINK/v1** _(obsolete as of 21-11-2019, continued support by this toolset)_ - transport layer: SCSI passthru commands over USB - stand-alone programmer and present on STM32VL Discovery boards * **STLINK/v2** @@ -83,8 +83,10 @@ Alternatively one can compile and install from source as described in our [compi We recommend to install `stlink-tools` from the package repository of the used distribution: -* Debian Linux: [(Link)](https://packages.debian.org/buster/stlink-tools) -* Ubuntu Linux: [(Link)](https://packages.ubuntu.com/stlink-tools) +**Note:** As packages distributed via the [Debian](https://packages.debian.org/buster/stlink-tools) and [Ubuntu](https://packages.ubuntu.com/stlink-tools) repositories differ from our self-maintained deb-package, we recommend to use the latter instead (see link below). It provides the opportunity to handle and fix user-reported package issues directly within the project and is not redundant to any limitations deriving from external maintenance guidelines. + +* Debian Linux: [(Link)](https://github.com/stlink-org/stlink/releases) +* Ubuntu Linux: [(Link)](https://github.com/stlink-org/stlink/releases) * Arch Linux: [(Link)](https://www.archlinux.org/packages/community/x86_64/stlink) * Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) * Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) From 56a699d37569caf591497427d42b5ad466c7a480 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 18 Jul 2020 00:56:49 +0200 Subject: [PATCH 0999/1435] Added missing cmake install prefix (Closes #1006) --- src/stlink-gui/CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 258f83cc1..46224dddb 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -35,7 +35,7 @@ if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) add_executable(stlink-gui ${GUI_SOURCES}) install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}) set_target_properties(stlink-gui PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}") + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) endif () From f57ae0c7142dd86b2dd5b0c298f7105ab65d574e Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Sun, 19 Jul 2020 16:55:02 +0200 Subject: [PATCH 1000/1435] Remove double parantheses --- src/st-flash/flash_opts.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 1cfd6fe89..ab716bb31 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -295,12 +295,12 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } break; - } else if ((o->area == FLASH_OTP)) { + } else if (o->area == FLASH_OTP) { return bad_arg("TODO: otp not implemented yet"); if (ac > 1) { return invalid_args("otp read: [path]"); } if (ac > 0) { o->filename = av[0]; } break; - } else if ((o->area == FLASH_OPTION_BYTES)) { + } else if (o->area == FLASH_OPTION_BYTES) { if (ac > 2) { return invalid_args("option bytes read: [path] [size]"); } if (ac > 0) { o->filename = av[0]; } if (ac > 1) { @@ -313,13 +313,13 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } } break; - } else if ((o->area == FLASH_OPTION_BYTES_BOOT_ADD)) { + } else if (o->area == FLASH_OPTION_BYTES_BOOT_ADD) { if (ac > 0) { return invalid_args("option bytes boot_add read"); } break; - } else if ((o->area == FLASH_OPTCR)) { + } else if (o->area == FLASH_OPTCR) { if (ac > 0) { return invalid_args("option control register read"); } break; - } else if ((o->area == FLASH_OPTCR1)) { + } else if (o->area == FLASH_OPTCR1) { if (ac > 0) { return invalid_args("option control register 1 read"); } break; } From 2dd47a432710c77f9dfd9a661212643a9667361f Mon Sep 17 00:00:00 2001 From: Rutger Hendriks Date: Sun, 19 Jul 2020 17:35:38 +0200 Subject: [PATCH 1001/1435] Reverted the last comparison changes --- src/st-flash/flash_opts.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index ab716bb31..e74ecc1ce 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -242,18 +242,18 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { // command and (optional) device name while (ac >= 1) { if (strcmp(av[0], "erase") == 0) { - if (FLASH_CMD_NONE != o->cmd) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return(-1); } o->cmd = FLASH_CMD_ERASE; } else if (strcmp(av[0], "read") == 0) { - if (FLASH_CMD_NONE != o->cmd) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return(-1); } o->cmd = FLASH_CMD_READ; } else if (strcmp(av[0], "write") == 0) { - if (FLASH_CMD_NONE != o->cmd) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return(-1); } o->cmd = FLASH_CMD_WRITE; } else if (strcmp(av[0], "reset") == 0) { - if (FLASH_CMD_NONE != o->cmd) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return(-1); } o->cmd = CMD_RESET; } else { From 1bcfdf5d42a29dedb44821ce30bbe6b915ebbb9a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 8 Aug 2020 13:22:56 +0200 Subject: [PATCH 1002/1435] Updated CHANGELOG.md & contributors.txt --- CHANGELOG.md | 2 ++ cmake/packaging/deb/control | 2 +- contributors.txt | 1 + 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 5ad1ec2d4..01e679b3c 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -8,6 +8,8 @@ Release date: (TBD) Features: +* Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) + Updates & changes: * [doc] st-flash --reset parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index 759668ba6..ef51a6cea 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -1,6 +1,6 @@ Source: stlink Priority: optional -Maintainer: stlink-org +Maintainer: Nightwalker-87 Build-Depends: cmake, dh-cmake, debhelper (>= 9), libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.5.0 Rules-Requires-Root: no diff --git a/contributors.txt b/contributors.txt index fec7510c3..cc9403456 100644 --- a/contributors.txt +++ b/contributors.txt @@ -103,6 +103,7 @@ Robin Kreis Roger Wolff [rewolff] Rob Spanton Rytis Karpuska +Rutger Hendriks [rutgerhendriks] Sean Simmons Sergey Alirzaev Simon Derr [sderr] From baab8ca2f9f7b5fcfd9a15c0bc61069a846e1f4f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 15 Aug 2020 21:31:52 +0200 Subject: [PATCH 1003/1435] Updated ISSUE_TEMPLATES (Closes #1014) --- ...ort--only-valid-if-template-is-reused--.md | 38 ------------------- .github/ISSUE_TEMPLATE/bug-report.md | 15 ++++---- .github/ISSUE_TEMPLATE/feature-request.md | 16 ++++---- 3 files changed, 14 insertions(+), 55 deletions(-) delete mode 100644 .github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md diff --git a/.github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md b/.github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md deleted file mode 100644 index 255596955..000000000 --- a/.github/ISSUE_TEMPLATE/bug-report--only-valid-if-template-is-reused--.md +++ /dev/null @@ -1,38 +0,0 @@ ---- -name: Bug Report (only valid if template is reused!) -about: 'Please read #906 before submitting a ticket.' -title: "[STM32 device name]: [Title]" -labels: '' -assignees: '' - ---- - -Thank you for giving feedback to the stlink project. - -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out each of the following items appropriate to your specific problem: - -- Programmer/board type: [enter here] (e.g Stlink /v1, /v2, /v2-clone, /v2-1) -- Programmer firmware version: [enter here] (e.g STSW-LINK007 2.27.15) -- Operating system and version: [enter here] (e.g Linux, Mac OS X, Windows) -- **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.1.0/git-c722056) -- Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) -- Target chip (and board if applicable): [enter here] (e.g STM32F402VG) - -Futher we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: - -Commandline-Output: - -``` -OUTPUT/ERROR of the commandline tool(s) -``` - -Expected/description: - -`short description of the expected value` - - -**NOTICE: This bug report may be closed without further notice, if not enough information is provided!** - -Thank you for your support. - -The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index 344a53ea6..fc30f3993 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -1,18 +1,19 @@ --- -name: Bug Report -about: 'Please read #906 before submitting a ticket.' -title: "[STM32 device name]: [Title]" +name: "Bug Report" +about: "Report a bug" +title: "[STM32 device name]: [_$YourTitle_]" labels: '' -assignees: '' - --- Thank you for giving feedback to the stlink project. +**NOTICE: Please read and follow instructions in #906 before submitting a ticket. This feature request will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** + +- [ ] I made serious effort to avoid creating duplicate or nearly similar issue + In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out each of the following items appropriate to your specific problem: - Programmer/board type: [enter here] (e.g Stlink /v1, /v2, /v2-clone, /v2-1) -- Programmer firmware version: [enter here] (e.g STSW-LINK007 2.27.15) - Operating system and version: [enter here] (e.g Linux, Mac OS X, Windows) - **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.1.0/git-c722056) - Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) @@ -31,8 +32,6 @@ Expected/description: `short description of the expected value` -**NOTICE: This bug report may be closed without further notice, if not enough information is provided!** - Thank you for your support. The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/feature-request.md b/.github/ISSUE_TEMPLATE/feature-request.md index 2aa7a5c7f..133b895b2 100644 --- a/.github/ISSUE_TEMPLATE/feature-request.md +++ b/.github/ISSUE_TEMPLATE/feature-request.md @@ -1,18 +1,19 @@ --- -name: Feature Request -about: Suggest an idea for this project -title: "[feature] " +name: "Feature Request" +about: "Suggest an idea for this project" +title: "[feature] [_$YourTitle_]" labels: code/feature-request -assignees: '' - --- Thank you for giving feedback to the stlink project. +**NOTICE: Please read and follow instructions in #906 before submitting a ticket. This feature request will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** + +- [ ] I made serious effort to avoid creating duplicate or nearly similar issue + In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out the check boxes below by setting a 'x' into the checkboxes ( [x] ) and edit each item appropriate to your specific problem. - [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard -- [ ] Programmer firmware version: e.g STSW-LINK007 2.27.15 - [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) - [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 - [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` @@ -31,9 +32,6 @@ Expected/description: `short description of the expected value` -**NOTICE: This feature request may be closed without notice when not enough information is provided!** - - Thank you for your support. The stlink project maintainers From 6f3657477739582a437693797136267c45009415 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 15 Aug 2020 21:38:36 +0200 Subject: [PATCH 1004/1435] Updated ISSUE_TEMPLATES (Closes #1014) --- .github/ISSUE_TEMPLATE/bug-report.md | 15 +++++++-------- .github/ISSUE_TEMPLATE/feature-request.md | 16 +++++++--------- 2 files changed, 14 insertions(+), 17 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index 344a53ea6..fc30f3993 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -1,18 +1,19 @@ --- -name: Bug Report -about: 'Please read #906 before submitting a ticket.' -title: "[STM32 device name]: [Title]" +name: "Bug Report" +about: "Report a bug" +title: "[STM32 device name]: [_$YourTitle_]" labels: '' -assignees: '' - --- Thank you for giving feedback to the stlink project. +**NOTICE: Please read and follow instructions in #906 before submitting a ticket. This feature request will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** + +- [ ] I made serious effort to avoid creating duplicate or nearly similar issue + In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out each of the following items appropriate to your specific problem: - Programmer/board type: [enter here] (e.g Stlink /v1, /v2, /v2-clone, /v2-1) -- Programmer firmware version: [enter here] (e.g STSW-LINK007 2.27.15) - Operating system and version: [enter here] (e.g Linux, Mac OS X, Windows) - **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.1.0/git-c722056) - Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) @@ -31,8 +32,6 @@ Expected/description: `short description of the expected value` -**NOTICE: This bug report may be closed without further notice, if not enough information is provided!** - Thank you for your support. The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/feature-request.md b/.github/ISSUE_TEMPLATE/feature-request.md index 2aa7a5c7f..133b895b2 100644 --- a/.github/ISSUE_TEMPLATE/feature-request.md +++ b/.github/ISSUE_TEMPLATE/feature-request.md @@ -1,18 +1,19 @@ --- -name: Feature Request -about: Suggest an idea for this project -title: "[feature] " +name: "Feature Request" +about: "Suggest an idea for this project" +title: "[feature] [_$YourTitle_]" labels: code/feature-request -assignees: '' - --- Thank you for giving feedback to the stlink project. +**NOTICE: Please read and follow instructions in #906 before submitting a ticket. This feature request will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** + +- [ ] I made serious effort to avoid creating duplicate or nearly similar issue + In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out the check boxes below by setting a 'x' into the checkboxes ( [x] ) and edit each item appropriate to your specific problem. - [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard -- [ ] Programmer firmware version: e.g STSW-LINK007 2.27.15 - [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) - [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 - [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` @@ -31,9 +32,6 @@ Expected/description: `short description of the expected value` -**NOTICE: This feature request may be closed without notice when not enough information is provided!** - - Thank you for your support. The stlink project maintainers From 61c5e395e2a850c0bc593d086d858091939ce238 Mon Sep 17 00:00:00 2001 From: Hassan DRAGA <61518789+dragahassan@users.noreply.github.com> Date: Fri, 28 Aug 2020 10:35:16 -0300 Subject: [PATCH 1005/1435] Fixing wrong path It's seem etc folder no longer exist, now it's on "stlink/config/udev/rules.d" instead of "stlink/etc/udev/rules.d". --- doc/compiling.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/compiling.md b/doc/compiling.md index c278c9ca8..48a429774 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -159,7 +159,7 @@ The rules are located in the subdirectory `config/udev/rules.d` within the sourc Afterwards it may be necessary to reload the udev rules: ```sh -$ cp etc/udev/rules.d /etc/udev/rules.d +$ cp config/udev/rules.d /etc/udev/rules.d $ udevadm control --reload-rules $ udevadm trigger ``` From 00a6ae027725e9850da5f550e193fa3dc7297eb5 Mon Sep 17 00:00:00 2001 From: Hassan DRAGA <61518789+dragahassan@users.noreply.github.com> Date: Fri, 28 Aug 2020 10:43:06 -0300 Subject: [PATCH 1006/1435] Updating commands Updating commands for "rules.d" --- doc/compiling.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index 48a429774..7f2ba698e 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -159,9 +159,9 @@ The rules are located in the subdirectory `config/udev/rules.d` within the sourc Afterwards it may be necessary to reload the udev rules: ```sh -$ cp config/udev/rules.d /etc/udev/rules.d -$ udevadm control --reload-rules -$ udevadm trigger +$ sudo cp -a config/udev/rules.d/. /etc/udev/rules.d +$ sudo udevadm control --reload-rules +$ sudo udevadm trigger ``` Udev will now create device node files `/dev/stlinkv2_XX`, `/dev/stlinkv1_XX`.
      From 5ea485de396ce004604a0adc4bf1278c6a3a845f Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Fri, 28 Aug 2020 23:35:45 +0300 Subject: [PATCH 1007/1435] use SetConsoleCtrlHandler for windows --- .gitignore | 1 + src/st-util/gdb-server.c | 21 ++++++++++++++++++--- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/.gitignore b/.gitignore index 229242a53..9fbe0139c 100644 --- a/.gitignore +++ b/.gitignore @@ -3,3 +3,4 @@ build-mingw .project obj-* *.user* +.cmake/ diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 94cd6fda7..60c9c16d3 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -71,19 +71,30 @@ int serve(stlink_t *sl, st_state_t *st); char* make_memory_map(stlink_t *sl); static void init_cache(stlink_t *sl); -static void cleanup(int signum) { - (void)signum; - +static void _cleanup() { if (connected_stlink) { // Switch back to mass storage mode before closing stlink_run(connected_stlink); stlink_exit_debug_mode(connected_stlink); stlink_close(connected_stlink); } +} +static void cleanup(int signum) { + printf("Receive signal %i. Exiting...\n", signum); + _cleanup(); exit(1); + (void)signum; } +#if defined(_WIN32) +BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { + printf("Receive signal %i. Exiting...\r\n", (int)fdwCtrlType); + _cleanup(); + return FALSE; +} +#endif + static stlink_t* do_connect(st_state_t *st) { stlink_t *sl = NULL; @@ -234,9 +245,13 @@ int main(int argc, char** argv) { } connected_stlink = sl; +#if defined(_WIN32) + SetConsoleCtrlHandler((PHANDLER_ROUTINE) CtrlHandler, TRUE); +#else signal(SIGINT, &cleanup); signal(SIGTERM, &cleanup); signal(SIGSEGV, &cleanup); +#endif if (state.reset) { stlink_reset(sl); } From 203d68544b5fe4858854c06df66e1142d12b27bd Mon Sep 17 00:00:00 2001 From: Alex Suykov Date: Wed, 9 Sep 2020 23:47:58 +0300 Subject: [PATCH 1008/1435] Fix reg_offset handling in stlink_usb_read_all_regs --- src/stlink-lib/usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index f9b4775f3..9726ddc4a 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -754,7 +754,7 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { sl->q_len = (int)size; stlink_print_data(sl); - for (i = reg_offset; i < 16; i++) regp->r[i] = read_uint32(sl->q_buf, i * 4); + for (i = 0; i < 16; i++) regp->r[i] = read_uint32(sl->q_buf, reg_offset + i * 4); regp->xpsr = read_uint32(sl->q_buf, reg_offset + 64); regp->main_sp = read_uint32(sl->q_buf, reg_offset + 68); From bf41f1404562ac5b632edd31bc4ba9afcf2f33d8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 20 Sep 2020 14:26:26 +0200 Subject: [PATCH 1009/1435] General Project Update - Updated list of required packages - Fixed install path of stlink-gui.ui file - Minor fixes in compiling.md - Updated CHANGELOG.md --- CHANGELOG.md | 2 ++ doc/compiling.md | 7 +++-- doc/version_support.md | 52 +++++++++++++++++------------------ src/stlink-gui/CMakeLists.txt | 2 +- 4 files changed, 33 insertions(+), 30 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 01e679b3c..d9dc64a11 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -26,6 +26,8 @@ Fixes: * Fix for static linking of libssp ([#973](https://github.com/stlink-org/stlink/pull/973), [#974](https://github.com/stlink-org/stlink/pull/974)) * Fixed connect under reset for st-flash and st-util ([#983](https://github.com/stlink-org/stlink/pull/983)) * Fix for mmap() size_t overflow in st-flash ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) +* [regression] stlink-gui installation issue on Ubuntu-18.04 ([#1006](https://github.com/stlink-org/stlink/pull/1006)) +* st-util: wrong register values passed to gdb (st-link v2) ([#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027)) v1.6.1 diff --git a/doc/compiling.md b/doc/compiling.md index 7f2ba698e..d8cb62ebb 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -159,7 +159,7 @@ The rules are located in the subdirectory `config/udev/rules.d` within the sourc Afterwards it may be necessary to reload the udev rules: ```sh -$ sudo cp -a config/udev/rules.d/. /etc/udev/rules.d +$ sudo cp -a config/udev/rules.d/* /etc/udev/rules.d/ $ sudo udevadm control --reload-rules $ sudo udevadm trigger ``` @@ -217,8 +217,9 @@ To do this with only one simple command, type: ### Building 1. Change into the project source directory: `cd stlink` -2. Run `make release` to create the _Release_ target -3. Run `make debug` to create the _Debug_ target (_optional_)
      +2. Run `make clean` to clean remnants of any previous builds. +3. Run `make release` to create the _Release_ target +4. Run `make debug` to create the _Debug_ target (_optional_)
      The debug target is only necessary in order to modify the sources and to run under a debugger. diff --git a/doc/version_support.md b/doc/version_support.md index 4076fb422..43c201101 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -28,39 +28,39 @@ NOTE: In order to use a STLINK/v1 programmer on macOS, versions 10.13, 10.14 or | Operating System | libusb
      version | cmake
      version | gtk-3
      version | Notes | | --- | --- | --- | --- | --- | -| Alpine Edge | 1.0.23 | 3.17.0 | 3.24.18
      gtk+3.0-dev | | -| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | 3.24.18
      libgtk+3-devel | | +| Alpine Edge | 1.0.23 | 3.17.0 | 3.99.0
      gtk+3.0 | | +| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | 3.24.18
      libgtk+3 | | | Arch Linux | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | -| Fedora Rawhide | 1.0.23 | 3.17.0 | 3.24.18
      gtk3-devel | | named `libusbx`, but
      `libusb`-codebase is used | +| Fedora Rawhide | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | named `libusbx`, but
      `libusb`-codebase is used | | KaOS | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | -| OpenMandriva Cooker | 1.0.23 | 3.17.0 | 3.24.18
      libgtk+3.0-devel
      lib64gtk+3.0-devel | | -| PCLinuxOS | 1.0.23
      lib64usb1.0 | 3.17.0 | 3.24.18
      lib64gtk+3.0-devel | | +| OpenMandriva Cooker | 1.0.23 | 3.17.0 | 3.24.18
      libgtk+3.0
      lib64gtk+3.0 | | +| PCLinuxOS | 1.0.23
      lib64usb1.0 | 3.17.0 | 3.24.18
      lib64gtk+3.0 | | | Slackware Current | 1.0.23 | 3.17.0 | 3.24.18
      gtk+3 | | -| Solus | 1.0.23 | 3.16.5 | 3.24.16
      libgtk-3-devel | | -| Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
      libgtk-3-dev | | -| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | 3.24.13
      libgtk+3.0-devel
      lib64gtk+3.0-devel | | -| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
      libgtk-3-dev | | -| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | 3.24.16
      gtk3-devel | | -| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.13
      gtk+3.0-dev | | -| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
      libgtk-3-dev | | -| Mageia Cauldron | 1.0.22 | 3.17.0 | 3.24.18
      libgtk+3.0-devel
      lib64gtk+3.0-devel | | +| Solus | 1.0.23 | 3.16.5 | 3.24.16
      libgtk-3 | | +| Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
      libgtk-3 | | +| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | 3.24.13
      libgtk+3.0
      lib64gtk+3.0 | | +| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
      libgtk-3 | | +| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | 3.24.16
      gtk3 | | +| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.13
      gtk+3.0 | | +| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
      libgtk-3 | | +| Mageia Cauldron | 1.0.22 | 3.17.0 | 3.24.18
      libgtk+3.0
      lib64gtk+3.0 | | | NetBSD 9.0 | 1.0.22 | 3.16.1 | 3.24.12
      gtk+3 | | | NetBSD 8.1 | 1.0.22 | 3.16.1 | 3.24.12
      gtk+3 | | | NetBSD 7.2 | 1.0.22 | 3.16.1 | _N/A_ | | -| Alpine 3.10 | 1.0.22 | 3.14.5 | 3.24.8
      gtk+3.0-dev | | -| Fedora 31 | 1.0.22 | 3.14.5 | 3.24.12
      gtk3-devel | named `libusbx`, but
      `libusb`-codebase is used | -| Mageia 7.1 | 1.0.22 | 3.14.3 | 3.24.8
      libgtk+3.0-devel
      lib64gtk+3.0-devel | | -| Fedora 30 | 1.0.22 | 3.14.2 | 3.24.8
      gtk3-devel | named `libusbx`, but
      `libusb`-codebase is used | -| Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
      libgtk-3-dev | | -| Alpine 3.9 | 1.0.22 | 3.13.0 | 3.24.1
      gtk+3.0-dev | | -| CentOS 8 | 1.0.22 | 3.11.4 | 3.22.30
      gtk3-devel | named `libusbx`, but
      `libusb`-codebase is used | -| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | 3.24.14
      gtk3-devel | | -| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | 3.22.30
      gtk3-devel | | -| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
      libgtk-3-dev | | -| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
      libgtk-3-dev | | +| Alpine 3.10 | 1.0.22 | 3.14.5 | 3.24.8
      gtk+3.0 | | +| Fedora 31 | 1.0.22 | 3.14.5 | 3.24.12
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | +| Mageia 7.1 | 1.0.22 | 3.14.3 | 3.24.8
      libgtk+3.0
      lib64gtk+3.0 | | +| Fedora 30 | 1.0.22 | 3.14.2 | 3.24.8
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | +| Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
      libgtk-3 | | +| Alpine 3.9 | 1.0.22 | 3.13.0 | 3.24.1
      gtk+3.0 | | +| CentOS 8 | 1.0.22 | 3.11.4 | 3.22.30
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | +| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | 3.24.14
      gtk3 | | +| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | 3.22.30
      gtk3 | | +| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
      libgtk-3 | | +| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
      libgtk-3 | | | Slackware 14.2 | **1.0.20** | 3.5.2 | 3.18.9
      gtk+3 | | -| Ubuntu 16.04 LTS (Xenial Xerus) | **1.0.20** | 3.5.1 | 3.18.9
      libgtk-3-dev | | -| OpenMandriva Lx 3.0 | **1.0.20** | **3.4.2** | 3.18.9
      libgtk+3.0-devel
      lib64gtk+3.0-devel | | +| Ubuntu 16.04 LTS (Xenial Xerus) | **1.0.20** | 3.5.1 | 3.18.9
      libgtk-3 | | +| OpenMandriva Lx 3.0 | **1.0.20** | **3.4.2** | 3.18.9
      libgtk+3.0
      lib64gtk+3.0 | | | FreeBSD 13 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-13.0r358841
      (integrated) | | FreeBSD 12 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-11.0r261448_4
      (integrated) | | FreeBSD 11 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-11.0r261448_4
      (integrated) | diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 46224dddb..22a22f59d 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -35,7 +35,7 @@ if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) add_executable(stlink-gui ${GUI_SOURCES}) install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}) set_target_properties(stlink-gui PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/${CMAKE_INSTALL_DATAROOTDIR}/${PROJECT_NAME}") + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_FULL_DATAROOTDIR}/${PROJECT_NAME}") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) endif () From 304635af647843eed06b16c3cc5806d23cd4c2d0 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Sat, 26 Sep 2020 17:27:00 +0500 Subject: [PATCH 1010/1435] Using vl flashoader with all F1 series --- src/stlink-lib/flash_loader.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 0e79c3c0a..7de485ca3 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -237,6 +237,12 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_size = sizeof(loader_code_stm32l); } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F1_MEDIUM || + sl->chip_id == STLINK_CHIPID_STM32_F1_HIGH || + sl->chip_id == STLINK_CHIPID_STM32_F1_LOW || + sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || + sl->chip_id == STLINK_CHIPID_STM32_F1_VL_HIGH || + sl->chip_id == STLINK_CHIPID_STM32_F1_XL || + sl->chip_id == STLINK_CHIPID_STM32_F1_CONN || sl->chip_id == STLINK_CHIPID_STM32_F3 || sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL || sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH || From 2a746afa8ba27d8ebf5d4d5b833aba5cc0641312 Mon Sep 17 00:00:00 2001 From: Timothy Lee Date: Thu, 8 Oct 2020 20:42:09 +1100 Subject: [PATCH 1011/1435] Increase STM32L0 option_size to 20 The FLASH_OPTR, FLASH_WRPROT1 and FLASH_WRPROT2 registers are spread across 20 option bytes. With the original option_size of 4, only the lower 16 bits of FLASH_OPTR could be modified. --- src/stlink-lib/chipid.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 3763587e1..dc9f31e44 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -386,7 +386,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1ff0000, .bootrom_size = 0x1000, .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, - .option_size = 4, + .option_size = 20, }, { // STM32L0x Category 5 @@ -400,7 +400,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1ff0000, .bootrom_size = 0x2000, .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, - .option_size = 4, + .option_size = 20, }, { // STM32L0x Category 2 @@ -414,7 +414,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1ff0000, .bootrom_size = 0x1000, .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, - .option_size = 4, + .option_size = 20, }, { // STM32F334, STM32F303x6/8, and STM32F328 From cdac31075590578ff67bbfd4221ab892d50fab42 Mon Sep 17 00:00:00 2001 From: Geert Stappers Date: Sat, 10 Oct 2020 22:10:42 +0200 Subject: [PATCH 1012/1435] [manual] Added st-info --probe example output To show what to expect: information about the ST-link and the target. Bumped date to this month and removed a trailing space. Modified: doc/man/st-info.md --- doc/man/st-info.md | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/doc/man/st-info.md b/doc/man/st-info.md index 94a430000..9164642f2 100644 --- a/doc/man/st-info.md +++ b/doc/man/st-info.md @@ -1,6 +1,6 @@ % st-flash(1) Open Source STMicroelectronics Stlink Tools | stlink % -% Feb 2018 +% Oct 2020 # NAME st-info - Provides information about connected STLink and STM32 devices @@ -15,7 +15,7 @@ st-info - Provides information about connected STLink and STM32 devices Provides information about connected STLink programmers and STM32 devices: Serial code, OpenOCD hla-serial, flash, page size, sram, chipid, description. -The STLink device to probe can be specified via the environment variable +The STLink device to probe can be specified via the environment variable STLINK_DEVICE on the format :. # OPTIONS @@ -52,6 +52,13 @@ STLINK_DEVICE on the format :. Display information about connected programmers and devices $ st-info --probe + Found 1 stlink programmers + serial: 303033413030323233343338353130323334333133393339 + hla-serial: "\x30\x30\x33\x41\x30\x30\x32\x32\x33\x34\x33\x38\x35\x31\x30\x32\x33\x34\x33\x31\x33\x39\x33\x39" + flash: 131072 (pagesize: 128) + sram: 20480 + chipid: 0x0447 + descr: L0xx Category 5 # SEE ALSO From 1c137bf07fb0e4e17acf73bb0229979971af7389 Mon Sep 17 00:00:00 2001 From: Timothy Lee Date: Wed, 14 Oct 2020 15:28:22 +1100 Subject: [PATCH 1013/1435] st-flash: respect --connect-under-reset option when opening USB connection --- src/st-flash/flash.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 9116f9c80..d8bd8772c 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -61,7 +61,9 @@ int main(int ac, char** av) { printf("st-flash %s\n", STLINK_VERSION); - sl = stlink_open_usb(o.log_level, 1, (char *)o.serial, o.freq); + sl = stlink_open_usb(o.log_level, + o.connect_under_reset ? 2 : 1, + (char *)o.serial, o.freq); if (sl == NULL) { return(-1); } From e8254501a1ce4832c3df9511180ffd6860446353 Mon Sep 17 00:00:00 2001 From: Timothy Lee Date: Sun, 18 Oct 2020 22:33:57 +1100 Subject: [PATCH 1014/1435] Add ability to identify STM32H742/743/753 --- inc/stlink.h | 3 ++- src/common.c | 5 +++++ src/stlink-lib/chipid.c | 11 +++++++++++ src/stlink-lib/chipid.h | 1 + 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/inc/stlink.h b/inc/stlink.h index 1566a0bd6..39f5f283c 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -126,7 +126,8 @@ enum stlink_flash_type { STLINK_FLASH_TYPE_L4, // l4, l4+ */ STLINK_FLASH_TYPE_G0, STLINK_FLASH_TYPE_G4, - STLINK_FLASH_TYPE_WB + STLINK_FLASH_TYPE_WB, + STLINK_FLASH_TYPE_H7, }; struct stlink_reg { diff --git a/src/common.c b/src/common.c index 86d2ca8ea..9aaae9073 100644 --- a/src/common.c +++ b/src/common.c @@ -1172,6 +1172,11 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { return(ret); } + if (*chip_id == 0) { + // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + ret = stlink_read_debug32(sl, 0x5c001000, chip_id); + } + if (*chip_id == 0) { // Try Corex M0 DBGMCU_IDCODE register address ret = stlink_read_debug32(sl, 0x40015800, chip_id); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index dc9f31e44..a9fb5af9d 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -614,6 +614,17 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fff0000, // see the memory map .bootrom_size = 0x7000 }, + { + // STM32H742/743/753 (from RM0433) + .chip_id = STLINK_CHIPID_STM32_H74XXX, + .description = "H742/743/753", + .flash_type = STLINK_FLASH_TYPE_H7, + .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) + .flash_pagesize = 0x20000, // 128k sector (pg147) + .sram_size = 0x20000, // 128k "DTCM" from Table 7 + .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 + .bootrom_size = 0x20000 // "System memory" byte size in hex from Table 7 + }, { // unknown .chip_id = STLINK_CHIPID_UNKNOWN, diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index b591f0012..f717022ca 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -53,6 +53,7 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_L0_CAT5 = 0x447, STLINK_CHIPID_STM32_F0_CAN = 0x448, STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the NucleoF746ZG board */ + STLINK_CHIPID_STM32_H74XXX = 0x450, /* Found on page 3189 in the RM0433*/ STLINK_CHIPID_STM32_F7XXXX = 0x451, STLINK_CHIPID_STM32_F72XXX = 0x452, /* ID found on the NucleoF722ZE board */ STLINK_CHIPID_STM32_L011 = 0x457, From aada8fc2ddb56debe5900d4affd63e6fb352dc67 Mon Sep 17 00:00:00 2001 From: Timothy Lee Date: Sun, 18 Oct 2020 23:32:06 +1100 Subject: [PATCH 1015/1435] Support flashing of STM32H7xx --- src/common.c | 118 +++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 109 insertions(+), 9 deletions(-) diff --git a/src/common.c b/src/common.c index 9aaae9073..26275c175 100644 --- a/src/common.c +++ b/src/common.c @@ -302,6 +302,22 @@ #define FLASH_F2_CR_SNB_MASK 0x78 #define FLASH_F2_SR_BSY 16 +// STM32H7xx +#define FLASH_H7_CR_LOCK 0 +#define FLASH_H7_CR_PG 1 +#define FLASH_H7_CR_SER 2 +#define FLASH_H7_CR_PSIZE 4 +#define FLASH_H7_CR_START 7 +#define FLASH_H7_CR_SNB 8 +#define FLASH_H7_CR_SNB_MASK 0x700 + +#define FLASH_H7_SR_QW 2 + +#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) +#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) +#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) + #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 @@ -381,6 +397,8 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { reg = STM32Gx_FLASH_CR; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + reg = FLASH_H7_CR1; } else { reg = FLASH_CR; } @@ -431,6 +449,9 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + cr_lock_shift = FLASH_H7_CR_LOCK; } else { ELOG("unsupported flash method, abort\n"); return(-1); @@ -467,6 +488,8 @@ static void unlock_flash(stlink_t *sl) { key_reg = STM32Gx_FLASH_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { key_reg = STM32WB_FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + key_reg = FLASH_H7_KEYR1; } else { ELOG("unsupported flash method, abort\n"); return; @@ -498,6 +521,7 @@ static int unlock_flash_if(stlink_t *sl) { static void lock_flash(stlink_t *sl) { uint32_t cr_lock_shift, cr_reg, n; + uint32_t cr_mask = 0xffffffffu; if (sl->flash_type == STLINK_FLASH_TYPE_F0 || sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { @@ -522,12 +546,17 @@ static void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + cr_lock_shift = FLASH_H7_CR_LOCK; + cr_mask = ~(1u << FLASH_H7_CR_SER); } else { ELOG("unsupported flash method, abort\n"); return; } stlink_read_debug32(sl, cr_reg, &n); + n &= cr_mask; n |= (1u << cr_lock_shift); stlink_write_debug32(sl, cr_reg, n); @@ -724,6 +753,9 @@ static void set_flash_cr_pg(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + x |= (1 << FLASH_H7_CR_PG); } else { cr_reg = FLASH_CR; x = (1 << FLASH_CR_PG); @@ -902,6 +934,9 @@ static void set_flash_cr_strt(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; cr_strt = (1 << STM32WB_FLASH_CR_STRT); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + cr_strt = 1 << FLASH_H7_CR_START; } else { cr_reg = FLASH_CR; cr_strt = (1 << FLASH_CR_STRT); @@ -939,6 +974,8 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { sr_reg = STM32Gx_FLASH_SR; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_reg = FLASH_H7_SR1; } else { ELOG("unsupported flash method, abort"); return(-1); @@ -973,6 +1010,8 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { sr_busy_shift = STM32Gx_FLASH_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { sr_busy_shift = STM32WB_FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_busy_shift = FLASH_H7_SR_QW; } else { ELOG("unsupported flash method, abort"); return(-1); @@ -1064,25 +1103,48 @@ static inline void write_flash_ar2(stlink_t *sl, uint32_t n) { } static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) { + uint32_t cr_reg, psize_shift; uint32_t x = read_flash_cr(sl); - x &= ~(0x03 << 8); - x |= (n << 8); + + if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + psize_shift = FLASH_H7_CR_PSIZE; + } else { + cr_reg = FLASH_F4_CR; + psize_shift = 8; + } + + x &= ~(0x03 << psize_shift); + x |= (n << psize_shift); #if DEBUG_FLASH fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); #endif - stlink_write_debug32(sl, FLASH_F4_CR, x); + stlink_write_debug32(sl, cr_reg, x); } - static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { + uint32_t cr_reg, snb_mask, snb_shift, ser_shift; uint32_t x = read_flash_cr(sl); - x &= ~FLASH_F4_CR_SNB_MASK; - x |= (n << FLASH_F4_CR_SNB); - x |= (1 << FLASH_F4_CR_SER); + + if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + snb_mask = FLASH_H7_CR_SNB_MASK; + snb_shift = FLASH_H7_CR_SNB; + ser_shift = FLASH_H7_CR_SER; + } else { + cr_reg = FLASH_F4_CR; + snb_mask = FLASH_F4_CR_SNB_MASK; + snb_shift = FLASH_F4_CR_SNB; + ser_shift = FLASH_F4_CR_SER; + } + + x &= ~snb_mask; + x |= (n << snb_shift); + x |= (1 << ser_shift); #if DEBUG_FLASH fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); #endif - stlink_write_debug32(sl, FLASH_F4_CR, x); + stlink_write_debug32(sl, cr_reg, x); } static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { @@ -2141,6 +2203,11 @@ uint32_t calculate_F7_sectornum(uint32_t flashaddr) { } +uint32_t calculate_H7_sectornum(uint32_t flashaddr) { + flashaddr &= ~STM32_FLASH_BASE; // sector holding the flash address + return(flashaddr / 0x20000); +} + // returns BKER:PNB for the given page address uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { uint32_t bker = 0; @@ -2214,7 +2281,8 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_F7 || - sl->flash_type == STLINK_FLASH_TYPE_L4) { + sl->flash_type == STLINK_FLASH_TYPE_L4 || + sl->flash_type == STLINK_FLASH_TYPE_H7) { // wait for ongoing op to finish wait_flash_busy(sl); @@ -2239,6 +2307,13 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // calculate the actual page from the address uint32_t sector = calculate_F7_sectornum(flashaddr); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", + sector, stlink_calculate_pagesize(sl, flashaddr)); + write_flash_cr_snb(sl, sector); + } else if (sl->chip_id == STLINK_CHIPID_STM32_H74XXX) { + // calculate the actual page from the address + uint32_t sector = calculate_H7_sectornum(flashaddr); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_snb(sl, sector); @@ -2854,6 +2929,31 @@ int stlink_write_flash( } fprintf(stdout, "\n"); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + ILOG("Starting Flash write for H7 core id\n"); + + unlock_flash_if(sl); // unlock the cr + set_flash_cr_pg(sl); // set programming mode + + for (off = 0; off < len;) { + // Program STM32H7x with 32-byte Flash words + size_t chunk = (len - off > 32) ? 32 : len - off; + memcpy(sl->q_buf, base + off, chunk); + stlink_write_mem32(sl, addr + (uint32_t)off, 32); + wait_flash_busy(sl); + + off += chunk; + + if (sl->verbose >= 1) { + // show progress + fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, (unsigned int)len); + fflush(stdout); + } + } + fprintf(stdout, "\n"); + + clear_flash_cr_pg(sl); + lock_flash(sl); } else { ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); return(-1); From bbc2b5417174418c597abc75755b12c11aee8f9a Mon Sep 17 00:00:00 2001 From: Timothy Lee Date: Mon, 19 Oct 2020 23:29:54 +1100 Subject: [PATCH 1016/1435] [feature] support STM32H7 option bytes --- inc/stm32.h | 1 + src/common.c | 95 +++++++++++++++++++++++++++++++++++++++++ src/stlink-lib/chipid.c | 4 +- 3 files changed, 99 insertions(+), 1 deletion(-) diff --git a/inc/stm32.h b/inc/stm32.h index 96836c9b7..1773e703b 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -21,5 +21,6 @@ #define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) #define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) +#define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C) #endif // STM32_H diff --git a/src/common.c b/src/common.c index 26275c175..a08db2733 100644 --- a/src/common.c +++ b/src/common.c @@ -313,10 +313,23 @@ #define FLASH_H7_SR_QW 2 +#define FLASH_H7_OPTCR_OPTLOCK 0 +#define FLASH_H7_OPTCR_OPTSTART 1 +#define FLASH_H7_OPTCR_MER 4 + +#define FLASH_H7_OPTSR_OPT_BUSY 0 +#define FLASH_H7_OPTSR_OPTCHANGEERR 30 + +#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 + #define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) #define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) #define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) #define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) +#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) +#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) +#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 @@ -603,6 +616,10 @@ static bool is_flash_option_locked(stlink_t *sl) { optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; + case STLINK_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + break; default: ELOG("unsupported flash method, abort\n"); return -1; @@ -654,6 +671,10 @@ static int lock_flash_option(stlink_t *sl) { optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; + case STLINK_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + break; default: ELOG("unsupported flash method, abort\n"); return -1; @@ -704,6 +725,9 @@ static int unlock_flash_option(stlink_t *sl) { case STLINK_FLASH_TYPE_WB: optkey_reg = STM32WB_FLASH_OPT_KEYR; break; + case STLINK_FLASH_TYPE_H7: + optkey_reg = FLASH_H7_OPT_KEYR; + break; default: ELOG("unsupported flash method, abort\n"); return(-1); @@ -3413,6 +3437,74 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t* base, stm32_addr_ return ret; } +/** + * Write STM32H7xx option bytes + * @param sl + * @param base option bytes to write + * @param addr of the memory mapped option bytes + * @param len number of bytes to write (must be multiple of 4) + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_h7( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { + uint32_t val; + uint32_t data; + + // Wait until previous flash option has completed + wait_flash_busy(sl); + + // Clear previous error + stlink_write_debug32(sl, FLASH_H7_OPTCCR, 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + + while (len != 0) { + switch (addr) { + case FLASH_H7_REGS_ADDR + 0x20: // FLASH_OPTSR_PRG + case FLASH_H7_REGS_ADDR + 0x2c: // FLASH_PRAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x34: // FLASH_SCAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 + case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG + /* Write to FLASH_xxx_PRG registers */ + write_uint32((unsigned char*)&data, *(uint32_t*)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + + /* Skip if the value in the CUR register is identical */ + stlink_read_debug32(sl, addr - 4, &val); + if (val == data) { + break; + } + + /* Write new option byte values and start modification */ + stlink_write_debug32(sl, addr, data); + stlink_read_debug32(sl, FLASH_H7_OPTCR, &val); + val |= (1 << FLASH_H7_OPTCR_OPTSTART); + stlink_write_debug32(sl, FLASH_H7_OPTCR, val); + + /* Wait for the option bytes modification to complete */ + do { + stlink_read_debug32(sl, FLASH_H7_OPTSR_CUR, &val); + } while ((val & (1 << FLASH_H7_OPTSR_OPT_BUSY)) != 0); + + /* Check for errors */ + if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { + stlink_write_debug32(sl, FLASH_H7_OPTCCR, 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + return -1; + } + break; + + default: + /* Skip non-programmable registers */ + break; + } + + len -= 4; + addr += 4; + base += 4; + } + + return 0; +} + /** * Read option bytes * @param sl @@ -3735,6 +3827,9 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui case STLINK_FLASH_TYPE_G4: ret = stlink_write_option_bytes_gx(sl, base, addr, len); break; + case STLINK_FLASH_TYPE_H7: + ret = stlink_write_option_bytes_h7(sl, base, addr, len); + break; default: ELOG("Option bytes writing is currently not implemented for connected chip\n"); break; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index a9fb5af9d..c191fa919 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -623,7 +623,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x20000, // 128k sector (pg147) .sram_size = 0x20000, // 128k "DTCM" from Table 7 .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 - .bootrom_size = 0x20000 // "System memory" byte size in hex from Table 7 + .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 + .option_base = STM32_H7_OPTION_BYTES_BASE, + .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 }, { // unknown From 781557dfba15d6539ccf85e2a385e4004af875a8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 24 Oct 2020 18:06:56 +0200 Subject: [PATCH 1017/1435] Removed outdated debian configuration Debian package build uses cmake environment. --- cmake/packaging/cpack_config.cmake | 2 +- debian/.gitignore | 10 -- debian/changelog | 74 --------------- debian/control | 44 --------- debian/copyright | 37 -------- debian/gbp.conf | 7 -- debian/libstlink-dev.install | 4 - debian/libstlink1.install | 1 - debian/libstlink1.symbols | 141 ----------------------------- debian/patches/guipath.patch | 11 --- debian/patches/series | 1 - debian/rules | 23 ----- debian/source/format | 1 - debian/source/options | 1 - debian/stlink-gui.install | 4 - debian/stlink-tools.install | 3 - debian/stlink-tools.manpages | 3 - debian/stlink.pc.in | 10 -- debian/watch | 3 - 19 files changed, 1 insertion(+), 379 deletions(-) delete mode 100644 debian/.gitignore delete mode 100644 debian/changelog delete mode 100644 debian/control delete mode 100644 debian/copyright delete mode 100644 debian/gbp.conf delete mode 100644 debian/libstlink-dev.install delete mode 100644 debian/libstlink1.install delete mode 100644 debian/libstlink1.symbols delete mode 100644 debian/patches/guipath.patch delete mode 100644 debian/patches/series delete mode 100755 debian/rules delete mode 100644 debian/source/format delete mode 100644 debian/source/options delete mode 100644 debian/stlink-gui.install delete mode 100644 debian/stlink-tools.install delete mode 100644 debian/stlink-tools.manpages delete mode 100644 debian/stlink.pc.in delete mode 100644 debian/watch diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index 469e743ca..acd5630fa 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -54,7 +54,7 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av # CPACK_DEBIAN_PACKAGE_ARCHITECTURE --> Default: Output of dpkg --print-architecture set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.4.2), libusb-1.0-0-dev (>= 1.0.20)") - set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Luca Boccassi ") + set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Nightwalker-87 ") # CPACK_DEBIAN_PACKAGE_DESCRIPTION --> Default: CPACK_DEBIAN_PACKAGE_DESCRIPTION (as it is set) # CPACK_DEBIAN_PACKAGE_SECTION --> Default: “devel” # CPACK_DEBIAN_ARCHIVE_TYPE --> Default: “gnutar” diff --git a/debian/.gitignore b/debian/.gitignore deleted file mode 100644 index 7624d1c9b..000000000 --- a/debian/.gitignore +++ /dev/null @@ -1,10 +0,0 @@ -.debhelper -files -debhelper-build-stamp -*.log -*.substvars -libstlink-dev -libstlink -stlink-gui -stlink-tools -tmp diff --git a/debian/changelog b/debian/changelog deleted file mode 100644 index c54850340..000000000 --- a/debian/changelog +++ /dev/null @@ -1,74 +0,0 @@ -stlink (1.6.1+ds-2) unstable; urgency=medium - - * Update d/copyright to remove GPL-2+ stanza about flashloaders - * Update upstream URLs for new Github org - * Patch CMake's hard-coded define of XML gui file location (Closes: - #963219) - - -- Luca Boccassi Sun, 21 Jun 2020 13:41:37 +0100 - -stlink (1.6.1+ds-1) unstable; urgency=medium - - * Merge tag 'v1.6.1' into debian - * Update Files-Excluded in d/copyright for new layout - * Fix d/watch intermediary file name - * Drop cross.patch, merged upstream in v1.6.1 - * Bump Build-Depends to cmake >= 3.4.2 - * Add new symbols from upstream version 1.6.1 - * Adjust install files, some files moved - * Remove unused variable from d/rules - * Generate pkgconfig file from d/rules, upstream doesn't do it - * Switch to debhelper-compat 12 - - -- Luca Boccassi Sat, 06 Jun 2020 14:44:54 +0100 - -stlink (1.6.0+ds-1) unstable; urgency=medium - - * Merge tag 'v1.6.0' into debian - * Bump Standards-Version to 4.5.0, no changes. - * Update libstlink1 symbols file for 1.6.0. - - -- Luca Boccassi Tue, 25 Feb 2020 22:08:33 +0000 - -stlink (1.5.1+ds-2) unstable; urgency=medium - - * Mark library packages as Multi-Arch: same. - * Apply cross.patch to fix cross-compiling the GUI. Thanks Helmut for - the patch! (Closes: #941320) - * Vcs-Git: add -b debian - * Set Rules-Requires-Root: no - * Bump Standards-Version to 4.4.0 - - -- Luca Boccassi Sun, 29 Sep 2019 12:50:58 +0100 - -stlink (1.5.1+ds-1) unstable; urgency=medium - - * Merge tag 'v1.5.1' into debian. See upstream changelog for info: - https://github.com/stlink-org/stlink/releases/tag/v1.5.1 - * Mark packages as linux-any, other systems not supported. - - -- Luca Boccassi Fri, 28 Sep 2018 10:26:39 +0100 - -stlink (1.5.0+ds-1) unstable; urgency=medium - - * Upload to unstable. (Closes: #869421) - - -- Luca Boccassi Fri, 16 Mar 2018 16:56:17 +0000 - -stlink (1.4.0) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 01 Jul 2017 00:00:00 +0000 - -stlink (1.3.1) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 25 Feb 2017 00:00:00 +0000 - -stlink (1.3.0) unstable; urgency=low - - -- Andrew 'Necromant' Andrianov Sat, 28 Jan 2017 00:00:00 +0000 - -stlink (1.2.1) unstable; urgency=low - - * Initial Debian-Packaged Release. - - -- Andrew 'Necromant' Andrianov Sat, 09 Jul 2016 23:16:07 +0300 diff --git a/debian/control b/debian/control deleted file mode 100644 index 598e0e89f..000000000 --- a/debian/control +++ /dev/null @@ -1,44 +0,0 @@ -Source: stlink -Priority: optional -Maintainer: Luca Boccassi -Build-Depends: debhelper-compat (= 12), cmake (>= 3.4.2), libusb-1.0-0-dev, libgtk-3-dev -Standards-Version: 4.5.0 -Rules-Requires-Root: no -Section: electronics -Homepage: https://github.com/stlink-org/stlink -Vcs-Git: https://github.com/bluca/stlink.git -b debian -Vcs-Browser: https://github.com/bluca/stlink - -Package: libstlink-dev -Section: libdevel -Architecture: linux-any -Multi-Arch: same -Depends: libstlink1 (= ${binary:Version}), ${misc:Depends} -Description: Open source STM32 MCU programming toolset. - . - This package contains the development files for stlink. - -Package: libstlink1 -Section: libs -Architecture: linux-any -Multi-Arch: same -Depends: ${shlibs:Depends}, ${misc:Depends} -Description: Open source STM32 MCU programming toolset. - . - This package contains the shared library for stlink. - -Package: stlink-tools -Architecture: linux-any -Depends: libstlink1 (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: Open source STM32 MCU programming toolset. - . - This package contains commandline utilities for stlink, modprobe- and - udev-rules. - -Package: stlink-gui -Architecture: linux-any -Depends: libstlink1 (= ${binary:Version}), stlink-tools (= ${binary:Version}), - ${shlibs:Depends}, ${misc:Depends} -Description: Open source STM32 MCU programming toolset. - . - This package contains a GUI for stlink. diff --git a/debian/copyright b/debian/copyright deleted file mode 100644 index 8329cc250..000000000 --- a/debian/copyright +++ /dev/null @@ -1,37 +0,0 @@ -Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ -Upstream-Name: stlink -Upstream-Contact: Luca Boccassi -Source: https://github.com/stlink-org/stlink -Files-Excluded: stlinkv1_macos_driver - -Files: * -Copyright: 2011-2020 stlink-org - Martin Capitanio [capnm] - Fabien Le Mentec [texane] - Jerry Jacobs [xor-gate] - [Nightwalker-87] - and many others... - An extended list of contributors can be found in "contributors.txt". -License: BSD-3-clause - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - . - 1. Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - 2. Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - 3. Neither the name of the copyright holder nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - . - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/debian/gbp.conf b/debian/gbp.conf deleted file mode 100644 index 418e536e9..000000000 --- a/debian/gbp.conf +++ /dev/null @@ -1,7 +0,0 @@ -[buildpackage] -upstream-tag = %(version)s -debian-branch = debian - -[dch] -git-log = --first-parent -customizations = /usr/share/doc/git-buildpackage/examples/wrap_cl.py diff --git a/debian/libstlink-dev.install b/debian/libstlink-dev.install deleted file mode 100644 index 4e0e0d184..000000000 --- a/debian/libstlink-dev.install +++ /dev/null @@ -1,4 +0,0 @@ -usr/include/* -usr/lib/*/lib*.a -usr/lib/*/pkgconfig/* -usr/lib/*/lib*.so diff --git a/debian/libstlink1.install b/debian/libstlink1.install deleted file mode 100644 index 3ddde5841..000000000 --- a/debian/libstlink1.install +++ /dev/null @@ -1 +0,0 @@ -usr/lib/*/lib*.so.* diff --git a/debian/libstlink1.symbols b/debian/libstlink1.symbols deleted file mode 100644 index 159f27d0f..000000000 --- a/debian/libstlink1.symbols +++ /dev/null @@ -1,141 +0,0 @@ -libstlink.so.1 libstlink1 #MINVER# - Md5Calculate@Base 1.6.1 - Md5Finalise@Base 1.6.1 - Md5Initialise@Base 1.6.1 - Md5Update@Base 1.6.1 - _parse_version@Base 1.5.0 - _stlink_sg_close@Base 1.5.0 - _stlink_sg_core_id@Base 1.5.0 - _stlink_sg_current_mode@Base 1.5.0 - _stlink_sg_enter_jtag_mode@Base 1.5.0 - _stlink_sg_enter_swd_mode@Base 1.5.0 - _stlink_sg_exit_debug_mode@Base 1.5.0 - _stlink_sg_exit_dfu_mode@Base 1.5.0 - _stlink_sg_force_debug@Base 1.5.0 - _stlink_sg_jtag_reset@Base 1.5.0 - _stlink_sg_read_all_regs@Base 1.5.0 - _stlink_sg_read_debug32@Base 1.5.0 - _stlink_sg_read_mem32@Base 1.5.0 - _stlink_sg_read_reg@Base 1.5.0 - _stlink_sg_reset@Base 1.5.0 - _stlink_sg_run@Base 1.5.0 - _stlink_sg_status@Base 1.5.0 - _stlink_sg_step@Base 1.5.0 - _stlink_sg_version@Base 1.5.0 - _stlink_sg_write_debug32@Base 1.5.0 - _stlink_sg_write_mem32@Base 1.5.0 - _stlink_sg_write_mem8@Base 1.5.0 - _stlink_sg_write_reg@Base 1.5.0 - _stlink_usb_close@Base 1.5.0 - _stlink_usb_core_id@Base 1.5.0 - _stlink_usb_current_mode@Base 1.5.0 - _stlink_usb_enter_swd_mode@Base 1.5.0 - _stlink_usb_exit_debug_mode@Base 1.5.0 - _stlink_usb_exit_dfu_mode@Base 1.5.0 - _stlink_usb_force_debug@Base 1.5.0 - _stlink_usb_get_rw_status@Base 1.6.1 - _stlink_usb_jtag_reset@Base 1.5.0 - _stlink_usb_read_all_regs@Base 1.5.0 - _stlink_usb_read_all_unsupported_regs@Base 1.5.0 - _stlink_usb_read_debug32@Base 1.5.0 - _stlink_usb_read_mem32@Base 1.5.0 - _stlink_usb_read_reg@Base 1.5.0 - _stlink_usb_read_unsupported_reg@Base 1.5.0 - _stlink_usb_reset@Base 1.5.0 - _stlink_usb_run@Base 1.5.0 - _stlink_usb_set_swdclk@Base 1.5.0 - _stlink_usb_status@Base 1.5.0 - _stlink_usb_status_v2@Base 1.6.1 - _stlink_usb_step@Base 1.5.0 - _stlink_usb_target_voltage@Base 1.5.0 - _stlink_usb_version@Base 1.5.0 - _stlink_usb_write_debug32@Base 1.5.0 - _stlink_usb_write_mem32@Base 1.5.0 - _stlink_usb_write_mem8@Base 1.5.0 - _stlink_usb_write_reg@Base 1.5.0 - _stlink_usb_write_unsupported_reg@Base 1.5.0 - calculate_F4_sectornum@Base 1.5.0 - calculate_F7_sectornum@Base 1.5.0 - calculate_L4_page@Base 1.5.0 - is_bigendian@Base 1.5.0 - read_uint16@Base 1.5.0 - read_uint32@Base 1.5.0 - send_recv@Base 1.5.0 - send_usb_data_only@Base 1.5.0 - send_usb_mass_storage_command@Base 1.5.0 - stlink_calculate_pagesize@Base 1.5.0 - stlink_chip_id@Base 1.5.0 - stlink_chipid_get_params@Base 1.5.0 - stlink_close@Base 1.5.0 - stlink_clr_hw_bp@Base 1.5.0 - stlink_core_id@Base 1.5.0 - stlink_core_stat@Base 1.5.0 - stlink_cpu_id@Base 1.5.0 - stlink_current_mode@Base 1.5.0 - stlink_enter_swd_mode@Base 1.5.0 - stlink_erase_flash_mass@Base 1.5.0 - stlink_erase_flash_page@Base 1.5.0 - stlink_exit_debug_mode@Base 1.5.0 - stlink_exit_dfu_mode@Base 1.5.0 - stlink_fcheck_flash@Base 1.5.0 - stlink_flash_loader_init@Base 1.5.0 - stlink_flash_loader_run@Base 1.5.0 - stlink_flash_loader_write_to_sram@Base 1.5.0 - stlink_force_debug@Base 1.5.0 - stlink_fread@Base 1.5.0 - stlink_fwrite_flash@Base 1.5.0 - stlink_fwrite_option_bytes@Base 1.6.0 -#MISSING: 1.6.1# stlink_fwrite_option_bytes_32bit@Base 1.6.0 - stlink_fwrite_sram@Base 1.5.0 - stlink_get_erased_pattern@Base 1.5.0 - stlink_is_core_halted@Base 1.5.0 - stlink_jtag_reset@Base 1.5.0 - stlink_load_device_params@Base 1.5.0 - stlink_mwrite_flash@Base 1.5.0 - stlink_mwrite_sram@Base 1.5.0 - stlink_open_usb@Base 1.5.0 - stlink_parse_ihex@Base 1.5.0 - stlink_print_data@Base 1.5.0 - stlink_probe_usb@Base 1.5.0 - stlink_probe_usb_free@Base 1.5.0 - stlink_q@Base 1.5.0 - stlink_read_all_regs@Base 1.5.0 - stlink_read_all_unsupported_regs@Base 1.5.0 - stlink_read_debug32@Base 1.5.0 - stlink_read_mem32@Base 1.5.0 - stlink_read_option_bytes32@Base 1.6.1 - stlink_read_option_bytes_Gx@Base 1.6.1 - stlink_read_option_bytes_f2@Base 1.6.0 - stlink_read_option_bytes_f4@Base 1.6.0 - stlink_read_option_bytes_generic@Base 1.6.1 - stlink_read_reg@Base 1.5.0 - stlink_read_unsupported_reg@Base 1.5.0 - stlink_reset@Base 1.5.0 - stlink_run@Base 1.5.0 - stlink_run_at@Base 1.5.0 - stlink_set_hw_bp@Base 1.5.0 - stlink_set_swdclk@Base 1.5.0 - stlink_stat@Base 1.5.0 - stlink_status@Base 1.5.0 - stlink_step@Base 1.5.0 - stlink_target_voltage@Base 1.5.0 - stlink_v1_open@Base 1.5.0 - stlink_v1_open_inner@Base 1.5.0 - stlink_verify_write_flash@Base 1.5.0 - stlink_version@Base 1.5.0 - stlink_write_debug32@Base 1.5.0 - stlink_write_dreg@Base 1.5.0 - stlink_write_flash@Base 1.5.0 - stlink_write_mem32@Base 1.5.0 - stlink_write_mem8@Base 1.5.0 - stlink_write_option_bytes32@Base 1.6.1 - stlink_write_option_bytes@Base 1.6.0 - stlink_write_reg@Base 1.5.0 - stlink_write_unsupported_reg@Base 1.5.0 - stm32l1_write_half_pages@Base 1.5.0 - ugly_init@Base 1.5.0 - ugly_libusb_log_level@Base 1.6.1 - ugly_log@Base 1.5.0 - write_buffer_to_sram@Base 1.5.0 - write_uint16@Base 1.5.0 - write_uint32@Base 1.5.0 diff --git a/debian/patches/guipath.patch b/debian/patches/guipath.patch deleted file mode 100644 index d3effc92b..000000000 --- a/debian/patches/guipath.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/src/stlink-gui/CMakeLists.txt -+++ b/src/stlink-gui/CMakeLists.txt -@@ -32,7 +32,7 @@ - add_executable(stlink-gui ${GUI_SOURCES}) - install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_BINDIR}) - set_target_properties(stlink-gui PROPERTIES -- COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin") -+ COMPILE_DEFINITIONS STLINK_UI_DIR="/usr/share/stlink") - target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) - install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) - diff --git a/debian/patches/series b/debian/patches/series deleted file mode 100644 index 1fdcf9977..000000000 --- a/debian/patches/series +++ /dev/null @@ -1 +0,0 @@ -guipath.patch diff --git a/debian/rules b/debian/rules deleted file mode 100755 index 512bd533f..000000000 --- a/debian/rules +++ /dev/null @@ -1,23 +0,0 @@ -#!/usr/bin/make -f -# See debhelper(7) (uncomment to enable) -# output every command that modifies files on the build system. -#DH_VERBOSE = 1 - -# see EXAMPLES in dpkg-buildflags(1) and read /usr/share/dpkg/* -DPKG_EXPORT_BUILDFLAGS = 1 -include /usr/share/dpkg/default.mk - -# see FEATURE AREAS in dpkg-buildflags(1) -export DEB_BUILD_MAINT_OPTIONS = hardening=+all - -%: - dh $@ --buildsystem cmake - -override_dh_auto_configure: - dh_auto_configure -- \ - -DSTLINK_UDEV_RULES_DIR='/lib/udev/rules.d' - -override_dh_auto_install: - dh_auto_install - mkdir -p $(CURDIR)/debian/tmp/usr/lib/$(DEB_HOST_MULTIARCH)/pkgconfig - sed -e "s/@VERSION@/$(DEB_VERSION_UPSTREAM)/" -e "s/@DEB_HOST_MULTIARCH@/$(DEB_HOST_MULTIARCH)/" $(CURDIR)/debian/stlink.pc.in > $(CURDIR)/debian/tmp/usr/lib/$(DEB_HOST_MULTIARCH)/pkgconfig/stlink.pc diff --git a/debian/source/format b/debian/source/format deleted file mode 100644 index 163aaf8d8..000000000 --- a/debian/source/format +++ /dev/null @@ -1 +0,0 @@ -3.0 (quilt) diff --git a/debian/source/options b/debian/source/options deleted file mode 100644 index 506210d2c..000000000 --- a/debian/source/options +++ /dev/null @@ -1 +0,0 @@ -extend-diff-ignore=stlinkv1_macos_driver diff --git a/debian/stlink-gui.install b/debian/stlink-gui.install deleted file mode 100644 index 96c55213f..000000000 --- a/debian/stlink-gui.install +++ /dev/null @@ -1,4 +0,0 @@ -/usr/bin/stlink-gui -/usr/share/stlink/stlink-gui.ui -/usr/share/applications/stlink-gui.desktop -/usr/share/icons/hicolor/scalable/apps/stlink-gui.svg diff --git a/debian/stlink-tools.install b/debian/stlink-tools.install deleted file mode 100644 index ca875a0e6..000000000 --- a/debian/stlink-tools.install +++ /dev/null @@ -1,3 +0,0 @@ -/usr/bin/st-* -lib/udev/rules.d/*.rules -etc/modprobe.d/*.conf diff --git a/debian/stlink-tools.manpages b/debian/stlink-tools.manpages deleted file mode 100644 index 049509abe..000000000 --- a/debian/stlink-tools.manpages +++ /dev/null @@ -1,3 +0,0 @@ -usr/share/stlink/man/man1/st-flash.1 -usr/share/stlink/man/man1/st-info.1 -usr/share/stlink/man/man1/st-util.1 diff --git a/debian/stlink.pc.in b/debian/stlink.pc.in deleted file mode 100644 index 9f740ba09..000000000 --- a/debian/stlink.pc.in +++ /dev/null @@ -1,10 +0,0 @@ -prefix=/usr -includedir=${prefix}/include/stlink -libdir=${prefix}/lib/@DEB_HOST_MULTIARCH@ - -Name: stlink -Description: Open source STM32 MCU programming toolset -Version: @VERSION@ -Requires: libusb-1.0 -Libs: -L${libdir} -lstlink -Cflags: -I${includedir} diff --git a/debian/watch b/debian/watch deleted file mode 100644 index 6eb6b78d6..000000000 --- a/debian/watch +++ /dev/null @@ -1,3 +0,0 @@ -version=3 -opts=dversionmangle=s/\+ds$//,repacksuffix=+ds,filenamemangle=s/.+\/v?(\d\S+)\.tar\.gz/stlink-$1\.tar\.gz/ \ - https://github.com/stlink-org/stlink/tags .*/v?(\d\S+)\.tar\.gz From e43b434c8ac59885710cb4b2b05fb49d7c023ad4 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Tue, 27 Oct 2020 11:41:39 +0500 Subject: [PATCH 1018/1435] Small rewrote setting breakpoints in gdb-server for Cortex-M7 --- inc/stm32.h | 1 + src/common.c | 8 +++- src/st-util/gdb-server.c | 92 +++++++++++++--------------------------- src/stlink-lib/reg.h | 10 ++++- 4 files changed, 47 insertions(+), 64 deletions(-) diff --git a/inc/stm32.h b/inc/stm32.h index 1773e703b..768fabb87 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -10,6 +10,7 @@ /* Cortex core ids */ #define STM32VL_CORE_ID 0x1ba01477 #define STM32F7_CORE_ID 0x5ba02477 +#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 JTAG ID Code (RM0433 pg3065) /* Constant STM32 memory map figures */ #define STM32_FLASH_BASE ((uint32_t)0x08000000) diff --git a/src/common.c b/src/common.c index a08db2733..c7f2883db 100644 --- a/src/common.c +++ b/src/common.c @@ -1252,7 +1252,13 @@ int stlink_core_id(stlink_t *sl) { int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { int ret; - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); + if (sl->core_id == STM32H7_CORE_ID) { + // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + ret = stlink_read_debug32(sl, 0x5c001000, chip_id); + } else { + // default chipid address + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); + } if (ret == -1) { return(ret); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 60c9c16d3..d2685cef6 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -575,21 +575,6 @@ char* make_memory_map(stlink_t *sl) { return(map); } -/* - * DWT_COMP0 0xE0001020 - * DWT_MASK0 0xE0001024 - * DWT_FUNCTION0 0xE0001028 - * DWT_COMP1 0xE0001030 - * DWT_MASK1 0xE0001034 - * DWT_FUNCTION1 0xE0001038 - * DWT_COMP2 0xE0001040 - * DWT_MASK2 0xE0001044 - * DWT_FUNCTION2 0xE0001048 - * DWT_COMP3 0xE0001050 - * DWT_MASK3 0xE0001054 - * DWT_FUNCTION3 0xE0001058 - */ - #define DATA_WATCH_NUM 4 enum watchfun { WATCHDISABLED = 0, WATCHREAD = 5, WATCHWRITE = 6, WATCHACCESS = 7 }; @@ -606,15 +591,15 @@ static void init_data_watchpoints(stlink_t *sl) { uint32_t data; DLOG("init watchpoints\n"); - stlink_read_debug32(sl, 0xE000EDFC, &data); + stlink_read_debug32(sl, STLINK_REG_CM3_DEMCR, &data); data |= 1 << 24; - // set trcena in debug command to turn on dwt unit - stlink_write_debug32(sl, 0xE000EDFC, data); + // set TRCENA in debug command to turn on DWT unit + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, data); // make sure all watchpoints are cleared for (int i = 0; i < DATA_WATCH_NUM; i++) { data_watches[i].fun = WATCHDISABLED; - stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); + stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), 0); } } @@ -645,16 +630,16 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr data_watches[i].mask = mask; // insert comparator address - stlink_write_debug32(sl, 0xE0001020 + i * 16, addr); + stlink_write_debug32(sl, STLINK_REG_CM3_DWT_COMPn(i), addr); // insert mask - stlink_write_debug32(sl, 0xE0001024 + i * 16, mask); + stlink_write_debug32(sl, STLINK_REG_CM3_DWT_MASKn(i), mask); // insert function - stlink_write_debug32(sl, 0xE0001028 + i * 16, wf); + stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), wf); // just to make sure the matched bit is clear ! - stlink_read_debug32(sl, 0xE0001028 + i * 16, &dummy); + stlink_read_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), &dummy); return(0); } } @@ -671,7 +656,7 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { DLOG("delete watchpoint %d addr %x\n", i, addr); data_watches[i].fun = WATCHDISABLED; - stlink_write_debug32(sl, 0xe0001028 + i * 16, 0); + stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), 0); return(0); } @@ -705,9 +690,15 @@ static void init_code_breakpoints(stlink_t *sl) { ILOG("Found %i hw breakpoint registers\n", code_break_num); + if (sl->core_id == STM32F7_CORE_ID || sl->core_id == STM32H7_CORE_ID) { + // Cortex-M7 can have locked to write FP_* registers + // IHI0029D, p. 48, Lock Access Register + stlink_write_debug32(sl, STLINK_REG_CM7_FP_LAR, STLINK_REG_CM7_FP_LAR_KEY); + } + for (int i = 0; i < code_break_num; i++) { code_breaks[i].type = 0; - stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMP0 + i * 4, 0); + stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(i), 0); } } @@ -719,69 +710,46 @@ static int has_breakpoint(stm32_addr_t addr) { } static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { - stm32_addr_t fpb_addr; uint32_t mask; int type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW; + stm32_addr_t fpb_addr = addr & 0x1FFFFFFC; if (addr & 1) { ELOG("update_code_breakpoint: unaligned address %08x\n", addr); return(-1); } - if (sl->core_id == STM32F7_CORE_ID) { - fpb_addr = addr; - } else { - fpb_addr = addr & ~0x3; - } - int id = -1; - for (int i = 0; i < code_break_num; i++) if (fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { id = i; break; } - if (id == -1) { - if (set) { - return(-1); - } // free slot not found - else { - return(0); - } // breakpoint is already removed - + if (set) + return(-1); // free slot not found + else + return(0); // breakpoint is already removed } struct code_hw_breakpoint* bp = &code_breaks[id]; - bp->addr = fpb_addr; - - if (sl->core_id == STM32F7_CORE_ID) { - if (set) { - bp->type = type; - } else { - bp->type = 0; - } - - mask = (bp->addr) | 1; - } else { - if (set) { - bp->type |= type; - } else { - bp->type &= ~type; - } - - mask = (bp->addr) | 1 | (bp->type << 30); - } + if (set) + bp->type |= type; + else + bp->type &= ~type; + + // DDI0403E, p. 759, FP_COMPn register description + mask = (bp->type << 30) | (bp->addr) | 1; if (bp->type == 0) { DLOG("clearing hw break %d\n", id); - stlink_write_debug32(sl, 0xe0002008 + id * 4, 0); + stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(id), 0); } else { DLOG("setting hw break %d at %08x (%d)\n", id, bp->addr, bp->type); DLOG("reg %08x \n", mask); - stlink_write_debug32(sl, 0xe0002008 + id * 4, mask); + stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(id), mask); } return(0); diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index dde77ef50..3a3682140 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -2,8 +2,16 @@ #define STLINK_REG_H_ #define STLINK_REG_CM3_CPUID 0xE000ED00 + #define STLINK_REG_CM3_FP_CTRL 0xE0002000 -#define STLINK_REG_CM3_FP_COMP0 0xE0002008 +#define STLINK_REG_CM3_FP_COMPn(n) (0xE0002008 + n*4) +#define STLINK_REG_CM7_FP_LAR 0xE0000FB0 +#define STLINK_REG_CM7_FP_LAR_KEY 0xC5ACCE55 + +#define STLINK_REG_CM3_DEMCR 0xE000EDFC +#define STLINK_REG_CM3_DWT_COMPn(n) (0xE0001020 + n*16) +#define STLINK_REG_CM3_DWT_MASKn(n) (0xE0001024 + n*16) +#define STLINK_REG_CM3_DWT_FUNn(n) (0xE0001028 + n*16) /* Cortex™-M3 Technical Reference Manual */ /* Debug Halting Control and Status Register */ From e5dcb5048c58bcbb95fee79e4775b7b447a5fc4f Mon Sep 17 00:00:00 2001 From: Timothy Lee Date: Tue, 27 Oct 2020 20:28:48 +1100 Subject: [PATCH 1019/1435] [feature] support STM32F4 option bytes --- inc/stm32.h | 1 + src/common.c | 1 + src/stlink-lib/chipid.c | 4 +++- 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/inc/stm32.h b/inc/stm32.h index 1773e703b..b81d3149d 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -20,6 +20,7 @@ #define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) #define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023C14) #define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C) diff --git a/src/common.c b/src/common.c index a08db2733..32c00ad3b 100644 --- a/src/common.c +++ b/src/common.c @@ -3680,6 +3680,7 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) { switch (sl->chip_id) { case STLINK_CHIPID_STM32_F2: return stlink_read_option_bytes_f2(sl, option_byte); + case STLINK_CHIPID_STM32_F4: case STLINK_CHIPID_STM32_F446: return stlink_read_option_bytes_f4(sl, option_byte); case STLINK_CHIPID_STM32_F7XXXX: diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index c191fa919..a8d160445 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -77,7 +77,9 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, .sram_size = 0x30000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .option_base = STM32_F4_OPTION_BYTES_BASE, + .option_size = 4, }, { .chip_id = STLINK_CHIPID_STM32_F4_DSI, From 59f8b479f6e87181b4d3430ff5a57ce08f820291 Mon Sep 17 00:00:00 2001 From: Fabian Herb Date: Mon, 26 Oct 2020 16:11:49 +0000 Subject: [PATCH 1020/1435] st-util: Add specialized memory map for STM32H7 devices --- src/st-util/gdb-server.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 60c9c16d3..2e936a5de 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -504,6 +504,24 @@ static const char* const memory_map_template_F7 = " " // option byte area "      "; +static const char* const memory_map_template_H7 = + "" + "" + "" + " " // ITCMRAM 64kB + " " // DTCMRAM 128kB + " " // RAM D1 512kB + " " // RAM D2 288kB + " " // RAM D3 64kB + " " + " 0x%x" + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + ""; + static const char* const memory_map_template_F4_DE = "" @@ -543,6 +561,10 @@ char* make_memory_map(stlink_t *sl) { } else if (sl->core_id == STM32F7_CORE_ID) { snprintf(map, sz, memory_map_template_F7, (unsigned int)sl->sram_size); + } else if (sl->chip_id == STLINK_CHIPID_STM32_H74XXX) { + snprintf(map, sz, memory_map_template_H7, + (unsigned int)sl->flash_size, + (unsigned int)sl->flash_pgsz); } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) { strcpy(map, memory_map_template_F4_HD); } else if (sl->chip_id == STLINK_CHIPID_STM32_F2) { From 31bea45e32d843b5b2d5bb2ea3bba3dbec73ac1b Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Thu, 29 Oct 2020 13:30:16 +0500 Subject: [PATCH 1021/1435] Autodetect breakpoint style and cache support --- src/st-util/gdb-server.c | 75 ++++++++++++++++++++++------------------ src/stlink-lib/reg.h | 14 +++++++- 2 files changed, 55 insertions(+), 34 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index d2685cef6..c832098f1 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -669,9 +669,13 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { static int code_break_num; static int code_lit_num; +static int code_break_rev; #define CODE_BREAK_NUM_MAX 15 #define CODE_BREAK_LOW 0x01 #define CODE_BREAK_HIGH 0x02 +#define CODE_BREAK_REMAP 0x04 +#define CODE_BREAK_REV_V1 0x00 +#define CODE_BREAK_REV_V2 0x01 struct code_hw_breakpoint { stm32_addr_t addr; @@ -683,14 +687,16 @@ static struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; static void init_code_breakpoints(stlink_t *sl) { unsigned int val; memset(sl->q_buf, 0, 4); - stlink_write_debug32(sl, STLINK_REG_CM3_FP_CTRL, 0x03 /* KEY | ENABLE4 */); + stlink_write_debug32(sl, STLINK_REG_CM3_FP_CTRL, 0x03 /* KEY | ENABLE */); stlink_read_debug32(sl, STLINK_REG_CM3_FP_CTRL, &val); code_break_num = ((val >> 4) & 0xf); code_lit_num = ((val >> 8) & 0xf); + code_break_rev = ((val >> 28) & 0xf); ILOG("Found %i hw breakpoint registers\n", code_break_num); - if (sl->core_id == STM32F7_CORE_ID || sl->core_id == STM32H7_CORE_ID) { + stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &val); + if (((val>>4) & 0xFFF) == 0xC27) { // Cortex-M7 can have locked to write FP_* registers // IHI0029D, p. 48, Lock Access Register stlink_write_debug32(sl, STLINK_REG_CM7_FP_LAR, STLINK_REG_CM7_FP_LAR_KEY); @@ -711,14 +717,22 @@ static int has_breakpoint(stm32_addr_t addr) { static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { uint32_t mask; - int type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW; - stm32_addr_t fpb_addr = addr & 0x1FFFFFFC; + int type; + stm32_addr_t fpb_addr; if (addr & 1) { ELOG("update_code_breakpoint: unaligned address %08x\n", addr); return(-1); } + if (code_break_rev == CODE_BREAK_REV_V1) { + type = (addr & 0x2) ? CODE_BREAK_HIGH : CODE_BREAK_LOW; + fpb_addr = addr & 0x1FFFFFFC; + } else { + type = CODE_BREAK_REMAP; + fpb_addr = addr; + } + int id = -1; for (int i = 0; i < code_break_num; i++) if (fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { @@ -741,7 +755,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { bp->type &= ~type; // DDI0403E, p. 759, FP_COMPn register description - mask = (bp->type << 30) | (bp->addr) | 1; + mask = ((bp->type&0x03) << 30) | bp->addr | 1; if (bp->type == 0) { DLOG("clearing hw break %d\n", id); @@ -870,16 +884,6 @@ static int flash_go(stlink_t *sl) { return(error); } -#define CLIDR 0xE000ED78 -#define CTR 0xE000ED7C -#define CCSIDR 0xE000ED80 -#define CSSELR 0xE000ED84 -#define CCR 0xE000ED14 -#define CCR_DC (1 << 16) -#define CCR_IC (1 << 17) -#define DCCSW 0xE000EF6C -#define ICIALLU 0xE000EF50 - struct cache_level_desc { unsigned int nsets; unsigned int nways; @@ -888,6 +892,8 @@ struct cache_level_desc { }; struct cache_desc_t { + unsigned used; + // minimal line size in bytes unsigned int dminline; unsigned int iminline; @@ -914,7 +920,7 @@ static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) { unsigned int ccsidr; unsigned int log2_nsets; - stlink_read_debug32(sl, CCSIDR, &ccsidr); + stlink_read_debug32(sl, STLINK_REG_CM7_CCSIDR, &ccsidr); desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1; desc->nways = ((ccsidr >> 3) & 0x1ff) + 1; desc->log2_nways = ceil_log2 (desc->nways); @@ -930,18 +936,22 @@ static void init_cache (stlink_t *sl) { unsigned int ctr; int i; - // assume only F7 has a cache - if (sl->core_id != STM32F7_CORE_ID) { return; } - - stlink_read_debug32(sl, CLIDR, &clidr); - stlink_read_debug32(sl, CCR, &ccr); - stlink_read_debug32(sl, CTR, &ctr); + // Check have cache + stlink_read_debug32(sl, STLINK_REG_CM7_CTR, &ctr); + if ((ctr >> 29) != 0x04) { + cache_desc.used = 0; + return; + } else + cache_desc.used = 1; cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f); cache_desc.iminline = 4 << (ctr & 0x0f); + + stlink_read_debug32(sl, STLINK_REG_CM7_CLIDR, &clidr); cache_desc.louu = (clidr >> 27) & 7; + stlink_read_debug32(sl, STLINK_REG_CM7_CCR, &ccr); ILOG("Chip clidr: %08x, I-Cache: %s, D-Cache: %s\n", - clidr, ccr & CCR_IC ? "on" : "off", ccr & CCR_DC ? "on" : "off"); + clidr, ccr & STLINK_REG_CM7_CCR_IC ? "on" : "off", ccr & STLINK_REG_CM7_CCR_DC ? "on" : "off"); ILOG(" cache: LoUU: %u, LoC: %u, LoUIS: %u\n", (clidr >> 27) & 7, (clidr >> 24) & 7, (clidr >> 21) & 7); ILOG(" cache: ctr: %08x, DminLine: %u bytes, IminLine: %u bytes\n", ctr, @@ -953,13 +963,13 @@ static void init_cache (stlink_t *sl) { cache_desc.icache[i].width = 0; if (ct == 2 || ct == 3 || ct == 4) { // data - stlink_write_debug32(sl, CSSELR, i << 1); + stlink_write_debug32(sl, STLINK_REG_CM7_CSSELR, i << 1); ILOG("D-Cache L%d: ", i); read_cache_level_desc(sl, &cache_desc.dcache[i]); } if (ct == 1 || ct == 3) { // instruction - stlink_write_debug32(sl, CSSELR, (i << 1) | 1); + stlink_write_debug32(sl, STLINK_REG_CM7_CSSELR, (i << 1) | 1); ILOG("I-Cache L%d: ", i); read_cache_level_desc(sl, &cache_desc.icache[i]); } @@ -969,7 +979,7 @@ static void init_cache (stlink_t *sl) { static void cache_flush(stlink_t *sl, unsigned ccr) { int level; - if (ccr & CCR_DC) { + if (ccr & STLINK_REG_CM7_CCR_DC) { for (level = cache_desc.louu - 1; level >= 0; level--) { struct cache_level_desc *desc = &cache_desc.dcache[level]; unsigned addr; @@ -981,15 +991,15 @@ static void cache_flush(stlink_t *sl, unsigned ccr) { unsigned int way; for (way = 0; way < desc->nways; way++) { - stlink_write_debug32(sl, DCCSW, addr | (way << way_sh)); + stlink_write_debug32(sl, STLINK_REG_CM7_DCCSW, addr | (way << way_sh)); } } } } // invalidate all I-cache to oPU - if (ccr & CCR_IC) { - stlink_write_debug32(sl, ICIALLU, 0); + if (ccr & STLINK_REG_CM7_CCR_IC) { + stlink_write_debug32(sl, STLINK_REG_CM7_ICIALLU, 0); } } @@ -1005,14 +1015,13 @@ static void cache_change(stm32_addr_t start, unsigned count) { static void cache_sync(stlink_t *sl) { unsigned ccr; - if (sl->core_id != STM32F7_CORE_ID) { return; } + if (!cache_desc.used) { return; } if (!cache_modified) { return; } cache_modified = 0; - stlink_read_debug32(sl, CCR, &ccr); - - if (ccr & (CCR_IC | CCR_DC)) { cache_flush(sl, ccr); } + stlink_read_debug32(sl, STLINK_REG_CM7_CCR, &ccr); + if (ccr & (STLINK_REG_CM7_CCR_IC | STLINK_REG_CM7_CCR_DC)) { cache_flush(sl, ccr); } } static size_t unhexify(const char *in, char *out, size_t out_count) { diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 3a3682140..734107d6a 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -6,7 +6,7 @@ #define STLINK_REG_CM3_FP_CTRL 0xE0002000 #define STLINK_REG_CM3_FP_COMPn(n) (0xE0002008 + n*4) #define STLINK_REG_CM7_FP_LAR 0xE0000FB0 -#define STLINK_REG_CM7_FP_LAR_KEY 0xC5ACCE55 +#define STLINK_REG_CM7_FP_LAR_KEY 0xC5ACCE55 #define STLINK_REG_CM3_DEMCR 0xE000EDFC #define STLINK_REG_CM3_DWT_COMPn(n) (0xE0001020 + n*16) @@ -25,4 +25,16 @@ #define STLINK_REG_AIRCR_VECTKEY 0x05fa0000 #define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004 +/* ARM Cortex-M7 Processor Technical Reference Manual */ +/* Cache Control and Status Register */ +#define STLINK_REG_CM7_CTR 0xE000ED7C +#define STLINK_REG_CM7_CLIDR 0xE000ED78 +#define STLINK_REG_CM7_CCR 0xE000ED14 +#define STLINK_REG_CM7_CCR_DC (1 << 16) +#define STLINK_REG_CM7_CCR_IC (1 << 17) +#define STLINK_REG_CM7_CSSELR 0xE000ED84 +#define STLINK_REG_CM7_DCCSW 0xE000EF6C +#define STLINK_REG_CM7_ICIALLU 0xE000EF50 +#define STLINK_REG_CM7_CCSIDR 0xE000ED80 + #endif // STLINK_REG_H_ From f503de605561a71bd4dafca59826d7847604ccd3 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Thu, 29 Oct 2020 18:06:33 +0000 Subject: [PATCH 1022/1435] Add cross.patch to fix cross-compilation. Thanks Helmut! Closes: #973339 --- debian/patches/cross.patch | 11 +++++++++++ debian/patches/series | 1 + 2 files changed, 12 insertions(+) create mode 100644 debian/patches/cross.patch diff --git a/debian/patches/cross.patch b/debian/patches/cross.patch new file mode 100644 index 000000000..8d927ba4b --- /dev/null +++ b/debian/patches/cross.patch @@ -0,0 +1,11 @@ +--- stlink-1.6.1+ds.orig/CMakeLists.txt ++++ stlink-1.6.1+ds/CMakeLists.txt +@@ -48,7 +48,7 @@ + find_package(libusb REQUIRED) + + ## Package configuration (pkg-config) on unix-based systems +-if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) ++if (NOT WIN32) + #add_subdirectory(cmake/pkgconfig) + find_package(PkgConfig) + pkg_check_modules(GTK3 gtk+-3.0) diff --git a/debian/patches/series b/debian/patches/series index 1fdcf9977..b3c28e7e1 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -1 +1,2 @@ guipath.patch +cross.patch From a952c950a62038b231a8e303c03d1c34b0e13bcd Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Thu, 29 Oct 2020 18:06:53 +0000 Subject: [PATCH 1023/1435] Update changelog for 1.6.1+ds-3 release --- debian/changelog | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/debian/changelog b/debian/changelog index f1265ee32..ac046a5f4 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,10 @@ +stlink (1.6.1+ds-3) unstable; urgency=medium + + * Add cross.patch to fix cross-compilation. Thanks Helmut! (Closes: + #973339) + + -- Luca Boccassi Thu, 29 Oct 2020 18:06:39 +0000 + stlink (1.6.1+ds-2) unstable; urgency=medium * Update d/copyright to remove GPL-2+ stanza about flashloaders From 504858566be82af996566795c41684b701b52ce1 Mon Sep 17 00:00:00 2001 From: anton Date: Sun, 1 Nov 2020 20:42:21 +0500 Subject: [PATCH 1024/1435] Improv MCU reseting --- src/stlink-lib/reg.h | 1 + src/stlink-lib/usb.c | 43 ++++++++++++++++++++++++++++++++++++++----- 2 files changed, 39 insertions(+), 5 deletions(-) diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 734107d6a..653852440 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -17,6 +17,7 @@ /* Debug Halting Control and Status Register */ #define STLINK_REG_DHCSR 0xe000edf0 #define STLINK_REG_DHCSR_DBGKEY 0xa05f0000 +#define STLINK_REG_DHCSR_S_RESET_ST 0x02000000 #define STLINK_REG_DCRSR 0xe000edf4 #define STLINK_REG_DCRDR 0xe000edf8 diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 9726ddc4a..6b914d805 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -508,9 +508,14 @@ int _stlink_usb_reset(stlink_t * sl) { unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + uint32_t dhcsr; + int ret, i, rep_len = 2; + // clear S_RESET_ST in DHCSR registr + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + + // send reset command + i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; if (sl->version.jtag_api == STLINK_JTAG_API_V1) { @@ -526,9 +531,37 @@ int _stlink_usb_reset(stlink_t * sl) { return((int)size); } - // reset through AIRCR so that NRST does not need to be connected - return(stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | - STLINK_REG_AIRCR_SYSRESETREQ)); + usleep(10000); + + dhcsr = 0; + ret = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + // reset not done yet + // try reset through AIRCR so that NRST does not need to be connected + + WLOG("NRST is not connected\n"); + DLOG("Using reset through SYSRESETREQ\n"); + ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ); + if (ret) + return(ret); + + usleep(10000); + } + + // waiting for a reset within 500ms + for (i=0; i<50; i++) { + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) + break; + usleep(10000); + } + + if (i >= 50) + return(-1); + return(0); } int _stlink_usb_jtag_reset(stlink_t * sl, int value) { From 4d07eb363dc9ca68936fd828d62340d8a9b558e3 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Mon, 2 Nov 2020 21:52:13 +0500 Subject: [PATCH 1025/1435] Split flash write function to optimize gdb flash loading --- inc/stlink.h | 4 + src/common.c | 382 +++++++++++++++++++++------------------ src/st-util/gdb-server.c | 28 ++- 3 files changed, 234 insertions(+), 180 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 39f5f283c..e78b9569f 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -303,6 +303,10 @@ int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_contr int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int stlink_flashloader_stop(stlink_t *sl); + #include #include #include diff --git a/src/common.c b/src/common.c index c7f2883db..71caeeaa8 100644 --- a/src/common.c +++ b/src/common.c @@ -2669,151 +2669,140 @@ int stm32l1_write_half_pages( return(0); } -int stlink_write_flash( - stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint8_t eraseonly) { - size_t off; - flash_loader_t fl; - ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); - // check addr range is inside the flash - stlink_calculate_pagesize(sl, addr); - - if (addr < sl->flash_base) { - ELOG("addr too low %#x < %#x\n", addr, sl->flash_base); - return(-1); - } else if ((addr + len) < addr) { - ELOG("addr overruns\n"); - return(-1); - } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { - ELOG("addr too high\n"); - return(-1); - } else if (addr & 1) { - ELOG("unaligned addr 0x%x\n", addr); - return(-1); - } else if (len & 1) { - WLOG("unaligned len 0x%x -- padding with zero\n", len); - len += 1; - } else if (addr & (sl->flash_pgsz - 1)) { - ELOG("addr not a multiple of current pagesize (%zd bytes), not supported, " - "check page start address and compare with flash module organisation " - "in related ST reference manual of your device.\n", sl->flash_pgsz); - return(-1); - } - - // make sure we've loaded the context with the chip details - stlink_core_id(sl); - - // Erase each page - int page_count = 0; - - for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + (uint32_t)off)) { - // addr must be an addr inside the page - if (stlink_erase_flash_page(sl, addr + (uint32_t)off) == -1) { - ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); - return(-1); - } - - ILOG("Flash page at addr: 0x%08lx erased\n", (unsigned long)(addr + off)); - page_count++; - } - - ILOG("Finished erasing %d pages of %d (%#x) bytes\n", - page_count, sl->flash_pgsz, sl->flash_pgsz); - - if (eraseonly) { return(0); } - +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_F7) || (sl->flash_type == STLINK_FLASH_TYPE_L4)) { - // TODO: check write operation - ILOG("Starting Flash write for F2/F4/F7/L4\n"); + // Flash loader initialisation - if (stlink_flash_loader_init(sl, &fl) == -1) { + if (stlink_flash_loader_init(sl, fl) == -1) { ELOG("stlink_flash_loader_init() == -1\n"); return(-1); } unlock_flash_if(sl); // first unlock the cr - // TODO: Check that Voltage range is 2.7 - 3.6 V - if ((sl->chip_id != STLINK_CHIPID_STM32_L4) && - (sl->chip_id != STLINK_CHIPID_STM32_L43X) && - (sl->chip_id != STLINK_CHIPID_STM32_L46X) && - (sl->chip_id != STLINK_CHIPID_STM32_L496X) && - (sl->chip_id != STLINK_CHIPID_STM32_L4RX)) { + int voltage; + if (sl->version.stlink_v == 1) { + WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); + voltage = 3200; + } else { + voltage = stlink_target_voltage(sl); + } + + if (voltage == -1) { + ELOG("Failed to read Target voltage\n"); + return(voltage); + } - if ( sl->version.stlink_v == 1) { - printf("STLINK V1 cannot read voltage, defaulting to 32-bit " - "writes on F4 devices\n"); + if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + // L4 does not have a byte-write mode + if (voltage < 1710) { + ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); + return(-1); + } + } else { + if (voltage > 2700) { + ILOG("enabling 32-bit flash writes\n"); write_flash_cr_psiz(sl, 2); } else { - // set parallelism to 32 bit - int voltage = stlink_target_voltage(sl); - - if (voltage == -1) { - printf("Failed to read Target voltage\n"); - return(voltage); - } else if (voltage > 2700) { - printf("enabling 32-bit flash writes\n"); - write_flash_cr_psiz(sl, 2); - } else { - printf("Target voltage (%d mV) too low for 32-bit flash, " - "using 8-bit flash writes\n", voltage); - write_flash_cr_psiz(sl, 0); - } + ILOG("Target voltage (%d mV) too low for 32-bit flash, " + "using 8-bit flash writes\n", voltage); + write_flash_cr_psiz(sl, 0); } + } + + // set programming mode + set_flash_cr_pg(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + ILOG("Starting Flash write for WB/G0/G4\n"); + + wait_flash_busy(sl); + unlock_flash_if(sl); // unlock flash if necessary + set_flash_cr_pg(sl); // set PG 'allow programming' bit + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + ILOG("Starting Flash write for L0\n"); + + uint32_t val; + uint32_t flash_regs_base; + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || + sl->chip_id == STLINK_CHIPID_STM32_L011) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; } else { - // L4 does not have a byte-write mode - int voltage = stlink_target_voltage(sl); + flash_regs_base = STM32L_FLASH_REGS_ADDR; + } - if (voltage == -1) { - printf("Failed to read Target voltage\n"); - return(voltage); - } else if (voltage < 1710) { - printf("Target voltage (%d mV) too low for flash writes!\n", voltage); - return(-1); - } + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); + + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { + ELOG("pecr.pelock not clear\n"); + return(-1); } - // set programming mode - set_flash_cr_pg(sl); + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); - size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { + ELOG("pecr.prglock not clear\n"); + return(-1); + } + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); + + // flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return(-1); + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + ILOG("Starting Flash write for H7\n"); + + unlock_flash_if(sl); // unlock the cr + set_flash_cr_pg(sl); // set programming mode + } else { + ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + return(-1); + } + return(0); +} + +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, + uint8_t* base, uint32_t len) { + size_t off; + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; for (off = 0; off < len;) { size_t size = len - off > buf_size ? buf_size : len - off; - printf("size: %u\n", (unsigned int)size); - - if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t)off, base + off, size) == -1) { + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); return(-1); } off += size; } - - clear_flash_cr_pg(sl); - lock_flash(sl); - - // STM32F4END } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { - fprintf(stdout, "Writing\r\n"); - fflush(stdout); - wait_flash_busy(sl); - unlock_flash_if(sl); // unlock flash if necessary - set_flash_cr_pg(sl); // set PG 'allow programming' bit - // write all words. - off = 0; - fprintf(stdout, "Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - - for ( ; off < len; off += sizeof(uint32_t)) { + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; - if (off > 254) { fprintf(stdout, "\r"); } - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", (unsigned int)(off / sl->flash_pgsz), @@ -2825,18 +2814,14 @@ int stlink_write_flash( stlink_write_debug32(sl, addr + (uint32_t)off, data); wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } + fprintf(stdout, "\n"); // flash writes happen as 2 words at a time if ((off / sizeof(uint32_t)) % 2 != 0) { stlink_write_debug32(sl, addr + (uint32_t)off, 0); // write a single word of zeros wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } - - clear_flash_cr_pg(sl); // reset PG bit. - lock_flash(sl); } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - // use fast word write - // TODO: half page uint32_t val; uint32_t flash_regs_base; uint32_t pagesize; @@ -2852,32 +2837,6 @@ int stlink_write_flash( pagesize = L1_WRITE_BLOCK_SIZE; } - // TODO: check write operation - - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); - - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if (val & (1 << 0)) { - fprintf(stderr, "pecr.pelock not clear\n"); - return(-1); - } - - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); - - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if (val & (1 << 1)) { - fprintf(stderr, "pecr.prglock not clear\n"); - return(-1); - } - off = 0; if (len > pagesize) { @@ -2892,9 +2851,7 @@ int stlink_write_flash( // write remaining word in program memory for ( ; off < len; off += sizeof(uint32_t)) { uint32_t data; - - if (off > 254) { fprintf(stdout, "\r"); } - + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", (unsigned int)(off / sl->flash_pgsz), @@ -2912,29 +2869,13 @@ int stlink_write_flash( // TODO: check redo write operation } - fprintf(stdout, "\n"); - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - ILOG("Starting Flash write for VL/F0/F3/F1_XL core id\n"); - - // flash loader initialisation - if (stlink_flash_loader_init(sl, &fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return(-1); - } - int write_block_count = 0; - for (off = 0; off < len; off += sl->flash_pgsz) { // adjust last write size - size_t size = sl->flash_pgsz; - - if ((off + sl->flash_pgsz) > len) { size = len - off; } + size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; // unlock and set programming mode unlock_flash_if(sl); @@ -2943,7 +2884,7 @@ int stlink_write_flash( DLOG("Finished unlocking flash, running loader!\n"); - if (stlink_flash_loader_run(sl, &fl, addr + (uint32_t)off, base + off, size) == -1) { + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); return(-1); } @@ -2952,19 +2893,15 @@ int stlink_write_flash( if (sl->verbose >= 1) { // show progress; writing procedure is slow and previous errors are misleading - fprintf(stdout, "\r%3u/%lu pages written", ++write_block_count, - (unsigned long)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); + fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, + (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); fflush(stdout); } } - - fprintf(stdout, "\n"); + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - ILOG("Starting Flash write for H7 core id\n"); - - unlock_flash_if(sl); // unlock the cr - set_flash_cr_pg(sl); // set programming mode - for (off = 0; off < len;) { // Program STM32H7x with 32-byte Flash words size_t chunk = (len - off > 32) ? 32 : len - off; @@ -2980,15 +2917,110 @@ int stlink_write_flash( fflush(stdout); } } - fprintf(stdout, "\n"); + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else { + return(-1); + } + + return(0); +} + +int stlink_flashloader_stop(stlink_t *sl) { + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4) || + (sl->flash_type == STLINK_FLASH_TYPE_WB) || + (sl->flash_type == STLINK_FLASH_TYPE_G0) || + (sl->flash_type == STLINK_FLASH_TYPE_G4) || + (sl->flash_type == STLINK_FLASH_TYPE_H7)) { clear_flash_cr_pg(sl); lock_flash(sl); - } else { - ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + uint32_t val; + uint32_t flash_regs_base; + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || + sl->chip_id == STLINK_CHIPID_STM32_L011) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; + } else { + flash_regs_base = STM32L_FLASH_REGS_ADDR; + } + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } + + return(0); +} + +int stlink_write_flash( + stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint8_t eraseonly) { + size_t off; + int ret; + flash_loader_t fl; + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); + // check addr range is inside the flash + stlink_calculate_pagesize(sl, addr); + + if (addr < sl->flash_base) { + ELOG("addr too low %#x < %#x\n", addr, sl->flash_base); + return(-1); + } else if ((addr + len) < addr) { + ELOG("addr overruns\n"); + return(-1); + } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { + ELOG("addr too high\n"); + return(-1); + } else if (addr & 1) { + ELOG("unaligned addr 0x%x\n", addr); return(-1); + } else if (len & 1) { + WLOG("unaligned len 0x%x -- padding with zero\n", len); + len += 1; + } else if (addr & (sl->flash_pgsz - 1)) { + ELOG("addr not a multiple of current pagesize (%zd bytes), not supported, " + "check page start address and compare with flash module organisation " + "in related ST reference manual of your device.\n", sl->flash_pgsz); + return(-1); + } + + // make sure we've loaded the context with the chip details + stlink_core_id(sl); + + // Erase each page + int page_count = 0; + + for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + (uint32_t)off)) { + // addr must be an addr inside the page + if (stlink_erase_flash_page(sl, addr + (uint32_t)off) == -1) { + ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); + return(-1); + } + + ILOG("Flash page at addr: 0x%08lx erased\n", (unsigned long)(addr + off)); + page_count++; } + ILOG("Finished erasing %d pages of %d (%#x) bytes\n", + page_count, sl->flash_pgsz, sl->flash_pgsz); + + if (eraseonly) { return(0); } + + ret = stlink_flashloader_start(sl, &fl); + if (ret) + return ret; + ret = stlink_flashloader_write(sl, &fl, addr, base, len); + if (ret) + return ret; + ret = stlink_flashloader_stop(sl); + if (ret) + return ret; + return(stlink_verify_write_flash(sl, addr, base, len)); } diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index c832098f1..5e8a2549e 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -847,13 +847,31 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { static int flash_go(stlink_t *sl) { int error = -1; - + int ret; + flash_loader_t fl; + // some kinds of clock settings do not allow writing to flash. stlink_reset(sl); stlink_force_debug(sl); for (struct flash_block* fb = flash_root; fb; fb = fb->next) { - DLOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length); + ILOG("flash_erase: block %08x -> %04x\n", fb->addr, fb->length); + + for (stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += (uint32_t)FLASH_PAGE) { + // update FLASH_PAGE + stlink_calculate_pagesize(sl, page); + + ILOG("flash_erase: page %08x\n", page); + ret = stlink_erase_flash_page(sl, page); + if (ret < 0) { goto error; } + } + } + + ret = stlink_flashloader_start(sl, &fl); + if (ret < 0) { goto error; } + + for (struct flash_block* fb = flash_root; fb; fb = fb->next) { + ILOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length); for (stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += (uint32_t)FLASH_PAGE) { unsigned length = fb->length - (page - fb->addr); @@ -861,14 +879,14 @@ static int flash_go(stlink_t *sl) { // update FLASH_PAGE stlink_calculate_pagesize(sl, page); - DLOG("flash_do: page %08x\n", page); + ILOG("flash_do: page %08x\n", page); unsigned len = (length > FLASH_PAGE) ? (unsigned int)FLASH_PAGE : length; - int ret = stlink_write_flash(sl, page, fb->data + (page - fb->addr), len, 0); - + ret = stlink_flashloader_write(sl, &fl, page, fb->data + (page - fb->addr), len); if (ret < 0) { goto error; } } } + stlink_flashloader_stop(sl); stlink_reset(sl); error = 0; From a7ea06d7d9b44e9033de68980b4ae2816b13a435 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Tue, 3 Nov 2020 10:23:07 +0500 Subject: [PATCH 1026/1435] Remove duplicate register definitions --- inc/stlink.h | 19 ------------------- src/stlink-lib/reg.h | 13 +++++++++++-- src/stlink-lib/usb.c | 8 ++++---- 3 files changed, 15 insertions(+), 25 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index e78b9569f..c4466b10b 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -83,25 +83,6 @@ enum target_state { #define STLINK_V3_MAX_FREQ_NB 10 -/* Cortex Debug Control Block */ -#define DCB_DHCSR 0xE000EDF0 -#define DCB_DCRSR 0xE000EDF4 -#define DCB_DCRDR 0xE000EDF8 -#define DCB_DEMCR 0xE000EDFC - -/* DCB_DHCSR bit and field definitions */ -#define DBGKEY (0xA05F << 16) -#define C_DEBUGEN (1 << 0) -#define C_HALT (1 << 1) -#define C_STEP (1 << 2) -#define C_MASKINTS (1 << 3) -#define S_REGRDY (1 << 16) -#define S_HALT (1 << 17) -#define S_SLEEP (1 << 18) -#define S_LOCKUP (1 << 19) -#define S_RETIRE_ST (1 << 24) -#define S_RESET_ST (1 << 25) - /* Map the relevant features, quirks and workaround for specific firmware version of stlink */ #define STLINK_F_HAS_TRACE (1 << 0) #define STLINK_F_HAS_SWD_SET_FREQ (1 << 1) diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 653852440..926480648 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -16,8 +16,17 @@ /* Cortex™-M3 Technical Reference Manual */ /* Debug Halting Control and Status Register */ #define STLINK_REG_DHCSR 0xe000edf0 -#define STLINK_REG_DHCSR_DBGKEY 0xa05f0000 -#define STLINK_REG_DHCSR_S_RESET_ST 0x02000000 +#define STLINK_REG_DHCSR_DBGKEY (0xA05F << 16) +#define STLINK_REG_DHCSR_C_DEBUGEN (1 << 0) +#define STLINK_REG_DHCSR_C_HALT (1 << 1) +#define STLINK_REG_DHCSR_C_STEP (1 << 2) +#define STLINK_REG_DHCSR_C_MASKINTS (1 << 3) +#define STLINK_REG_DHCSR_S_REGRDY (1 << 16) +#define STLINK_REG_DHCSR_S_HALT (1 << 17) +#define STLINK_REG_DHCSR_S_SLEEP (1 << 18) +#define STLINK_REG_DHCSR_S_LOCKUP (1 << 19) +#define STLINK_REG_DHCSR_S_RETIRE_ST (1 << 24) +#define STLINK_REG_DHCSR_S_RESET_ST (1 << 25) #define STLINK_REG_DCRSR 0xe000edf4 #define STLINK_REG_DCRDR 0xe000edf8 diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 6b914d805..4e805a709 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -385,15 +385,15 @@ int _stlink_usb_status_v2(stlink_t *sl) { int result; uint32_t status = 0; - result = _stlink_usb_read_debug32(sl, DCB_DHCSR, &status); + result = _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &status); DLOG("core status: %08X\n", status); if (result != 0) { sl->core_stat = TARGET_UNKNOWN; } else { - if (status & S_HALT) { + if (status & STLINK_REG_DHCSR_C_HALT) { sl->core_stat = TARGET_HALTED; - } else if (status & S_RESET_ST) { + } else if (status & STLINK_REG_DHCSR_S_RESET_ST) { sl->core_stat = TARGET_RESET; } else { sl->core_stat = TARGET_RUNNING; @@ -616,7 +616,7 @@ int _stlink_usb_run(stlink_t* sl) { int res; if (sl->version.jtag_api != STLINK_JTAG_API_V1) { - res = _stlink_usb_write_debug32(sl, DCB_DHCSR, DBGKEY | C_DEBUGEN); + res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN); return(res); } From 922eba585b47d7ce5814a83fd96409c98acd9e6b Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Tue, 3 Nov 2020 12:19:47 +0500 Subject: [PATCH 1027/1435] Optimized timeout of the chip reset function --- CMakeLists.txt | 12 ++++++++++++ src/stlink-lib/helper.c | 13 +++++++++++++ src/stlink-lib/helper.h | 6 ++++++ src/stlink-lib/usb.c | 21 ++++++++++----------- src/win32/sys_time.c | 20 ++++++++++++++++++++ src/win32/sys_time.h | 30 ++++++++++++++++++++++++++++++ 6 files changed, 91 insertions(+), 11 deletions(-) create mode 100644 src/stlink-lib/helper.c create mode 100644 src/stlink-lib/helper.h create mode 100644 src/win32/sys_time.c create mode 100644 src/win32/sys_time.h diff --git a/CMakeLists.txt b/CMakeLists.txt index fae458dd7..4ab43271e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -60,6 +60,11 @@ if (STLINK_HAVE_SYS_MMAN_H) add_definitions(-DSTLINK_HAVE_SYS_MMAN_H) endif() +CHECK_INCLUDE_FILE(sys/time.h STLINK_HAVE_SYS_TIME_H) +if (STLINK_HAVE_SYS_TIME_H) + add_definitions(-DSTLINK_HAVE_SYS_TIME_H) +endif() + CHECK_INCLUDE_FILE(unistd.h STLINK_HAVE_UNISTD_H) if (STLINK_HAVE_UNISTD_H) add_definitions(-DSTLINK_HAVE_UNISTD_H) @@ -104,6 +109,7 @@ set(STLINK_HEADERS src/stlink-lib/md5.h src/stlink-lib/sg.h src/stlink-lib/usb.h + src/stlink-lib/helper.h ) set(STLINK_SOURCE @@ -114,6 +120,7 @@ set(STLINK_SOURCE src/stlink-lib/md5.c src/stlink-lib/sg.c src/stlink-lib/usb.c + src/stlink-lib/helper.c ) if (WIN32) @@ -132,6 +139,11 @@ if (WIN32) set(STLINK_SOURCE "${STLINK_SOURCE};src/win32/mmap.c") set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/mmap.h") endif() + + if (NOT STLINK_HAVE_SYS_TIME_H) + set(STLINK_SOURCE "${STLINK_SOURCE};src/win32/sys_time.c") + set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/sys_time.h") + endif() endif () ## Include test execution for test-targets for target Debug diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c new file mode 100644 index 000000000..50c55230b --- /dev/null +++ b/src/stlink-lib/helper.c @@ -0,0 +1,13 @@ +#include + +#ifdef STLINK_HAVE_SYS_TIME_H +#include +#else +#include +#endif + +unsigned time_ms() { + struct timeval tv; + gettimeofday(&tv, NULL); + return (unsigned)tv.tv_sec * 1000 + tv.tv_usec / 1000; +} diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h new file mode 100644 index 000000000..defd0504b --- /dev/null +++ b/src/stlink-lib/helper.h @@ -0,0 +1,6 @@ +#ifndef SYS_HELPER_H +#define SYS_HELPER_H + +unsigned time_ms(); + +#endif SYS_HELPER_H diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 4e805a709..b502ca2a6 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -17,6 +17,7 @@ #endif #include +#include #include "usb.h" enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; @@ -509,10 +510,10 @@ int _stlink_usb_reset(stlink_t * sl) { unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t dhcsr; - int ret, i, rep_len = 2; + int ret, timeout, i, rep_len = 2; // clear S_RESET_ST in DHCSR registr - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); // send reset command i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); @@ -534,14 +535,14 @@ int _stlink_usb_reset(stlink_t * sl) { usleep(10000); dhcsr = 0; - ret = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + ret = _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { // reset not done yet // try reset through AIRCR so that NRST does not need to be connected WLOG("NRST is not connected\n"); DLOG("Using reset through SYSRESETREQ\n"); - ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | + ret = _stlink_usb_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | STLINK_REG_AIRCR_SYSRESETREQ); if (ret) return(ret); @@ -550,18 +551,16 @@ int _stlink_usb_reset(stlink_t * sl) { } // waiting for a reset within 500ms - for (i=0; i<50; i++) { + timeout = time_ms() + 500; + while (time_ms() < timeout) { // DDI0337E, p. 10-4, Debug Halting Control and Status Register dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) - break; - usleep(10000); + return(0); } - if (i >= 50) - return(-1); - return(0); + return(-1); } int _stlink_usb_jtag_reset(stlink_t * sl, int value) { diff --git a/src/win32/sys_time.c b/src/win32/sys_time.c new file mode 100644 index 000000000..ea7c25dda --- /dev/null +++ b/src/win32/sys_time.c @@ -0,0 +1,20 @@ +#include +#include + +#include "sys_time.h" + +/* Simple gettimeofday implementation without converting Windows time to Linux time */ +int gettimeofday(struct timeval *tv, struct timezone *tz) { + FILETIME ftime; + ULARGE_INTEGER ulint; + + GetSystemTimeAsFileTime(&ftime); + ulint.LowPart = ftime.dwLowDateTime; + ulint.HighPart = ftime.dwHighDateTime; + + tv->tv_sec = (long)(ulint.QuadPart / 10000000L); + tv->tv_usec = (long)(ulint.QuadPart % 10000000L); + + return 0; + (void)tz; +} diff --git a/src/win32/sys_time.h b/src/win32/sys_time.h new file mode 100644 index 000000000..87c3a42fd --- /dev/null +++ b/src/win32/sys_time.h @@ -0,0 +1,30 @@ +#ifndef STLINK_TIME_H +#define STLINK_TIME_H + +#ifdef STLINK_HAVE_SYS_TIME_H +#include +#else + +struct timeval { + long tv_sec; + long tv_usec; +}; + +struct timezone { + int tz_minuteswest; + int tz_dsttime; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int gettimeofday(struct timeval *tv, struct timezone *tz); + +#ifdef __cplusplus +} +#endif + +#endif /* STLINK_HAVE_SYS_TIME_H */ + +#endif /* STLINK_TIME_H */ From ddd39354b545f6176345cce8f2d520bd109dcbe7 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Tue, 3 Nov 2020 14:49:19 +0500 Subject: [PATCH 1028/1435] Trying to use a soft reset before starting debugging --- inc/stlink.h | 1 + src/common.c | 50 ++++++++++++++++++++++++++++++++++++---- src/st-util/gdb-server.c | 13 +++++++---- src/stlink-lib/reg.h | 2 ++ 4 files changed, 57 insertions(+), 9 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index c4466b10b..2ec2db367 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -223,6 +223,7 @@ void stlink_close(stlink_t *sl); int stlink_core_id(stlink_t *sl); int stlink_reset(stlink_t *sl); int stlink_jtag_reset(stlink_t *sl, int value); +int stlink_soft_reset(stlink_t *sl, int halt_on_reset); int stlink_run(stlink_t *sl); int stlink_status(stlink_t *sl); int stlink_version(stlink_t *sl); diff --git a/src/common.c b/src/common.c index 71caeeaa8..ed3f7b222 100644 --- a/src/common.c +++ b/src/common.c @@ -1416,6 +1416,48 @@ int stlink_jtag_reset(stlink_t *sl, int value) { return(sl->backend->jtag_reset(sl, value)); } +int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { + int ret; + uint32_t dhcsr, demcr; + + DLOG("*** stlink_soft_reset ***\n"); + + // halt core and enable debugging (if not already done) + // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) + _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | + STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); + + // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) + stlink_read_debug32(sl, STLINK_REG_CM3_DEMCR, &demcr); + if (halt_on_reset) { + demcr |= STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_CORERESET; + } else { + demcr &= ~STLINK_REG_CM3_DEMCR_VC_CORERESET; + } + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, demcr); + + // clear S_RESET_ST in DHCSR register + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + + // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) + ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ); + if (ret) + return(ret); + + // waiting for a reset within 500ms + timeout = time_ms() + 500; + while (time_ms() < timeout) { + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) + return(0); + } + + return(-1); +} + int stlink_run(stlink_t *sl) { DLOG("*** stlink_run ***\n"); return(sl->backend->run(sl)); @@ -2899,8 +2941,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr } } if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } + fprintf(stdout, "\n"); + } } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { for (off = 0; off < len;) { // Program STM32H7x with 32-byte Flash words @@ -2918,8 +2960,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr } } if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } + fprintf(stdout, "\n"); + } } else { return(-1); } diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 5e8a2549e..4eca5819e 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -591,9 +591,9 @@ static void init_data_watchpoints(stlink_t *sl) { uint32_t data; DLOG("init watchpoints\n"); + // set TRCENA in debug command to turn on DWT unit stlink_read_debug32(sl, STLINK_REG_CM3_DEMCR, &data); - data |= 1 << 24; - // set TRCENA in debug command to turn on DWT unit + data |= STLINK_REG_CM3_DEMCR_TRCENA; stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, data); // make sure all watchpoints are cleared @@ -887,7 +887,7 @@ static int flash_go(stlink_t *sl) { } stlink_flashloader_stop(sl); - stlink_reset(sl); + //stlink_reset(sl); error = 0; error: @@ -1804,13 +1804,16 @@ int serve(stlink_t *sl, st_state_t *st) { case 'R': { // reset the core. - ret = stlink_reset(sl); - + ret = stlink_soft_reset(sl, 1 /* halt on reset */); if (ret) { DLOG("R packet : stlink_reset failed\n"); } init_code_breakpoints(sl); init_data_watchpoints(sl); + if (stlink_status(sl) == TARGET_HALTED) { + stlink_run(sl); + } + attached = 1; reply = strdup("OK"); diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 926480648..d9323a042 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -9,6 +9,8 @@ #define STLINK_REG_CM7_FP_LAR_KEY 0xC5ACCE55 #define STLINK_REG_CM3_DEMCR 0xE000EDFC +#define STLINK_REG_CM3_DEMCR_TRCENA (1 << 24) +#define STLINK_REG_CM3_DEMCR_VC_CORERESET (1 << 0) #define STLINK_REG_CM3_DWT_COMPn(n) (0xE0001020 + n*16) #define STLINK_REG_CM3_DWT_MASKn(n) (0xE0001024 + n*16) #define STLINK_REG_CM3_DWT_FUNn(n) (0xE0001028 + n*16) From b401eaff9a144f973f44f5914a70fc82da36d39f Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Thu, 5 Nov 2020 16:57:30 +0500 Subject: [PATCH 1029/1435] Improve soft reset with core halt --- src/common.c | 58 +++++++++++++++++++++++++++++----------- src/st-util/gdb-server.c | 22 +++++++-------- src/stlink-lib/helper.c | 2 ++ src/stlink-lib/helper.h | 2 +- src/stlink-lib/reg.h | 13 +++++++-- src/stlink-lib/usb.c | 14 ++++------ 6 files changed, 71 insertions(+), 40 deletions(-) diff --git a/src/common.c b/src/common.c index ed3f7b222..cdf0fa497 100644 --- a/src/common.c +++ b/src/common.c @@ -14,6 +14,7 @@ #include #include #include +#include #ifdef STLINK_HAVE_SYS_MMAN_H #include @@ -1418,44 +1419,71 @@ int stlink_jtag_reset(stlink_t *sl, int value) { int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { int ret; - uint32_t dhcsr, demcr; + unsigned timeout; + uint32_t dhcsr, dfsr; - DLOG("*** stlink_soft_reset ***\n"); + ELOG("*** stlink_soft_reset %s***\n", halt_on_reset?"(halt) ":""); // halt core and enable debugging (if not already done) // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) - _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); - + // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) - stlink_read_debug32(sl, STLINK_REG_CM3_DEMCR, &demcr); if (halt_on_reset) { - demcr |= STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_CORERESET; + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, STLINK_REG_CM3_DEMCR_TRCENA | + STLINK_REG_CM3_DEMCR_VC_HARDERR | STLINK_REG_CM3_DEMCR_VC_BUSERR | + STLINK_REG_CM3_DEMCR_VC_CORERESET); + + // clear VCATCH in the DFSR register + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); } else { - demcr &= ~STLINK_REG_CM3_DEMCR_VC_CORERESET; + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, STLINK_REG_CM3_DEMCR_TRCENA | + STLINK_REG_CM3_DEMCR_VC_HARDERR | STLINK_REG_CM3_DEMCR_VC_BUSERR); } - stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, demcr); - // clear S_RESET_ST in DHCSR register + // clear S_RESET_ST in the DHCSR register stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - + // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | STLINK_REG_AIRCR_SYSRESETREQ); - if (ret) + if (ret) { + ELOG("Soft reset failed: error write to AIRCR\n"); return(ret); + } // waiting for a reset within 500ms + // DDI0337E, p. 10-4, Debug Halting Control and Status Register timeout = time_ms() + 500; while (time_ms() < timeout) { // DDI0337E, p. 10-4, Debug Halting Control and Status Register dhcsr = STLINK_REG_DHCSR_S_RESET_ST; stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) - return(0); + if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) { + if (halt_on_reset) { + // waiting halt by the SYSRESETREQ exception + // DDI0403E, p. C1-699, Debug Fault Status Register + dfsr = 0; + stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + if ((dfsr&STLINK_REG_DFSR_VCATCH) == 0) { + continue; + } + } + timeout = 0; + break; + } } - return(-1); + // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); + + if (timeout) { + ELOG("Soft reset failed: timeout\n"); + return(-1); + } + + return(0); } int stlink_run(stlink_t *sl) { @@ -2735,7 +2763,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { if (voltage == -1) { ELOG("Failed to read Target voltage\n"); - return(voltage); + return(-1); } if (sl->flash_type == STLINK_FLASH_TYPE_L4) { diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 4eca5819e..d69ac0626 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -591,7 +591,7 @@ static void init_data_watchpoints(stlink_t *sl) { uint32_t data; DLOG("init watchpoints\n"); - // set TRCENA in debug command to turn on DWT unit + // set TRCENA in debug command to turn on DWT unit stlink_read_debug32(sl, STLINK_REG_CM3_DEMCR, &data); data |= STLINK_REG_CM3_DEMCR_TRCENA; stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, data); @@ -849,7 +849,7 @@ static int flash_go(stlink_t *sl) { int error = -1; int ret; flash_loader_t fl; - + // some kinds of clock settings do not allow writing to flash. stlink_reset(sl); stlink_force_debug(sl); @@ -863,12 +863,12 @@ static int flash_go(stlink_t *sl) { ILOG("flash_erase: page %08x\n", page); ret = stlink_erase_flash_page(sl, page); - if (ret < 0) { goto error; } + if (ret) { goto error; } } } ret = stlink_flashloader_start(sl, &fl); - if (ret < 0) { goto error; } + if (ret) { goto error; } for (struct flash_block* fb = flash_root; fb; fb = fb->next) { ILOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length); @@ -882,12 +882,12 @@ static int flash_go(stlink_t *sl) { ILOG("flash_do: page %08x\n", page); unsigned len = (length > FLASH_PAGE) ? (unsigned int)FLASH_PAGE : length; ret = stlink_flashloader_write(sl, &fl, page, fb->data + (page - fb->addr), len); - if (ret < 0) { goto error; } + if (ret) { goto error; } } } stlink_flashloader_stop(sl); - //stlink_reset(sl); + stlink_soft_reset(sl, 1 /* halt on reset */); error = 0; error: @@ -1390,8 +1390,8 @@ int serve(stlink_t *sl, st_state_t *st) { free(decoded); } else if (!strcmp(cmdName, "FlashDone")) { - if (flash_go(sl) < 0) { - reply = strdup("E00"); + if (flash_go(sl)) { + reply = strdup("E08"); } else { reply = strdup("OK"); } @@ -1804,16 +1804,12 @@ int serve(stlink_t *sl, st_state_t *st) { case 'R': { // reset the core. - ret = stlink_soft_reset(sl, 1 /* halt on reset */); + ret = stlink_reset(sl); if (ret) { DLOG("R packet : stlink_reset failed\n"); } init_code_breakpoints(sl); init_data_watchpoints(sl); - if (stlink_status(sl) == TARGET_HALTED) { - stlink_run(sl); - } - attached = 1; reply = strdup("OK"); diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index 50c55230b..8b2c8e8f7 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -1,5 +1,7 @@ #include +#include + #ifdef STLINK_HAVE_SYS_TIME_H #include #else diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index defd0504b..12c2ea2a7 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -3,4 +3,4 @@ unsigned time_ms(); -#endif SYS_HELPER_H +#endif /* SYS_HELPER_H */ diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index d9323a042..2e93dc5b1 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -10,6 +10,8 @@ #define STLINK_REG_CM3_DEMCR 0xE000EDFC #define STLINK_REG_CM3_DEMCR_TRCENA (1 << 24) +#define STLINK_REG_CM3_DEMCR_VC_HARDERR (1 << 10) +#define STLINK_REG_CM3_DEMCR_VC_BUSERR (1 << 8) #define STLINK_REG_CM3_DEMCR_VC_CORERESET (1 << 0) #define STLINK_REG_CM3_DWT_COMPn(n) (0xE0001020 + n*16) #define STLINK_REG_CM3_DWT_MASKn(n) (0xE0001024 + n*16) @@ -17,6 +19,12 @@ /* Cortex™-M3 Technical Reference Manual */ /* Debug Halting Control and Status Register */ +#define STLINK_REG_DFSR 0xE000ED30 +#define STLINK_REG_DFSR_HALT (1 << 0) +#define STLINK_REG_DFSR_BKPT (1 << 1) +#define STLINK_REG_DFSR_VCATCH (1 << 3) +#define STLINK_REG_DFSR_EXTERNAL (1 << 4) +#define STLINK_REG_DFSR_CLEAR 0x0000001F #define STLINK_REG_DHCSR 0xe000edf0 #define STLINK_REG_DHCSR_DBGKEY (0xA05F << 16) #define STLINK_REG_DHCSR_C_DEBUGEN (1 << 0) @@ -34,8 +42,9 @@ /* Application Interrupt and Reset Control Register */ #define STLINK_REG_AIRCR 0xe000ed0c -#define STLINK_REG_AIRCR_VECTKEY 0x05fa0000 -#define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004 +#define STLINK_REG_AIRCR_VECTKEY 0x05fa0000 +#define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004 +#define STLINK_REG_AIRCR_VECTRESET 0x00000001 /* ARM Cortex-M7 Processor Technical Reference Manual */ /* Cache Control and Status Register */ diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index b502ca2a6..7909a4e69 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -510,7 +510,8 @@ int _stlink_usb_reset(stlink_t * sl) { unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t dhcsr; - int ret, timeout, i, rep_len = 2; + unsigned timeout; + int i, rep_len = 2; // clear S_RESET_ST in DHCSR registr _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); @@ -535,19 +536,14 @@ int _stlink_usb_reset(stlink_t * sl) { usleep(10000); dhcsr = 0; - ret = _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { // reset not done yet // try reset through AIRCR so that NRST does not need to be connected - + WLOG("NRST is not connected\n"); DLOG("Using reset through SYSRESETREQ\n"); - ret = _stlink_usb_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | - STLINK_REG_AIRCR_SYSRESETREQ); - if (ret) - return(ret); - - usleep(10000); + return stlink_soft_reset(sl, 0); } // waiting for a reset within 500ms From 85f0e939111d7350bdd40746161da7ef656d5151 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Thu, 5 Nov 2020 17:00:48 +0500 Subject: [PATCH 1030/1435] Add switch to Thumb mode before starting flash loader --- src/stlink-lib/flash_loader.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 7de485ca3..c86aefbf7 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -316,6 +316,8 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe int i = 0; size_t count = 0; uint32_t flash_base = 0; + const char *error = NULL; + uint32_t dhcsr, dfsr; DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); @@ -354,6 +356,13 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe // only used on VL/F1_XL, but harmless for others stlink_write_reg(sl, fl->loader_addr, 15); // pc register + /* Make sure we are in Thumb mode */ + stlink_read_reg(sl, 16, &rr); + if ((rr.xpsr & (1 << 24)) == 0) { + ILOG("Go to Thumb mode\n"); + stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); + } + /* Run loader */ stlink_run(sl); @@ -376,17 +385,26 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe } if (i >= WAIT_ROUNDS) { - ELOG("flash loader run error\n"); - return(-1); + error = "Flash loader run error"; + goto error; } // check written byte count stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { - ELOG("write error, count == %u\n", rr.r[2]); - return(-1); + error = "Write error"; + goto error; } return(0); + +error: + dhcsr = dfsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + stlink_read_all_regs(sl, &rr); + ELOG("%s (R2 0x%08X R15 0x%08X DHCSR 0x%08X DFSR 0x%08X)\n", error, rr.r[2], rr.r[15], dhcsr, dfsr); + + return(-1); } From 0135a0ea162e72a6d15de768140522078bb6bf81 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Thu, 5 Nov 2020 18:50:10 +0500 Subject: [PATCH 1031/1435] Expand and simplify stlink V2 + support --- src/stlink-lib/usb.c | 41 +++++++++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 7909a4e69..92ad4cbc5 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -262,7 +262,7 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { } int _stlink_usb_get_rw_status(stlink_t *sl) { - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return(-1); } + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return(0); } unsigned char* const rdata = sl->q_buf; struct stlink_libusb * const slu = sl->backend_data; @@ -355,15 +355,17 @@ int _stlink_usb_core_id(stlink_t * sl) { unsigned char* const cmd = sl->c_buf; unsigned char* const data = sl->q_buf; ssize_t size; - int rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 12; + int offset, rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 12; int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; if (sl->version.jtag_api == STLINK_JTAG_API_V1) { cmd[i++] = STLINK_DEBUG_READCOREID; + offset = 0; } else { cmd[i++] = STLINK_DEBUG_APIV2_READ_IDCODES; + offset = 4; } size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); @@ -373,11 +375,7 @@ int _stlink_usb_core_id(stlink_t * sl) { return(-1); } - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { - sl->core_id = read_uint32(data, 0); - } else { - sl->core_id = read_uint32(data, 4); - } + sl->core_id = read_uint32(data, offset); return(0); } @@ -440,6 +438,14 @@ int _stlink_usb_status(stlink_t * sl) { int _stlink_usb_force_debug(stlink_t *sl) { struct stlink_libusb *slu = sl->backend_data; + + int res; + + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { + res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); + return(res); + } + unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; @@ -583,6 +589,17 @@ int _stlink_usb_jtag_reset(stlink_t * sl, int value) { int _stlink_usb_step(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; + + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { + // emulates the JTAG v1 API by using DHCSR + _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN); + _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_STEP | + STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN); + return _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_DEBUGEN); + } + unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; @@ -792,11 +809,11 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { if (sl->verbose < 2) { return(0); } - DLOG("xpsr = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 64)); - DLOG("main_sp = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 68)); - DLOG("process_sp = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 72)); - DLOG("rw = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 76)); - DLOG("rw2 = 0x%08x\n", read_uint32(sl->q_buf, reg_offset + 80)); + DLOG("xpsr = 0x%08x\n", regp->xpsr); + DLOG("main_sp = 0x%08x\n", regp->main_sp); + DLOG("process_sp = 0x%08x\n", regp->process_sp); + DLOG("rw = 0x%08x\n", regp->rw); + DLOG("rw2 = 0x%08x\n", regp->rw2); return(0); } From f3c824c83e10548b89513b12f55f113452259a97 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Thu, 5 Nov 2020 18:54:03 +0500 Subject: [PATCH 1032/1435] More robust fw flash by gdb --- src/common.c | 2 +- src/st-util/gdb-server.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index cdf0fa497..89f27aa66 100644 --- a/src/common.c +++ b/src/common.c @@ -1422,7 +1422,7 @@ int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { unsigned timeout; uint32_t dhcsr, dfsr; - ELOG("*** stlink_soft_reset %s***\n", halt_on_reset?"(halt) ":""); + DLOG("*** stlink_soft_reset %s***\n", halt_on_reset?"(halt) ":""); // halt core and enable debugging (if not already done) // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index d69ac0626..63ba68fcf 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -853,6 +853,8 @@ static int flash_go(stlink_t *sl) { // some kinds of clock settings do not allow writing to flash. stlink_reset(sl); stlink_force_debug(sl); + // delay to ensure that STM32 HSI clock and others have started up fully + usleep(10000); for (struct flash_block* fb = flash_root; fb; fb = fb->next) { ILOG("flash_erase: block %08x -> %04x\n", fb->addr, fb->length); From 43019fcde99b8e745a767b8e2c307d5868c09878 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Thu, 5 Nov 2020 19:34:22 +0500 Subject: [PATCH 1033/1435] Fix change SWD frequency of stlink v3 --- doc/dev/developer.txt | 2 +- inc/backend.h | 2 +- inc/stlink.h | 2 +- src/common.c | 4 +-- src/stlink-lib/usb.c | 68 +++++++++++++++++-------------------------- 5 files changed, 31 insertions(+), 47 deletions(-) diff --git a/doc/dev/developer.txt b/doc/dev/developer.txt index 32afd4352..9c4da22f7 100644 --- a/doc/dev/developer.txt +++ b/doc/dev/developer.txt @@ -300,7 +300,7 @@ Return: -1 for error. 0 for success. int stlink_current_mode(stlink_t *sl); int stlink_force_debug(stlink_t *sl); int stlink_target_voltage(stlink_t *sl); - int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); + int stlink_set_swdclk(stlink_t *sl, int freq_khz); int stlink_erase_flash_mass(stlink_t* sl); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); diff --git a/inc/backend.h b/inc/backend.h index f852da05d..d60708031 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -28,7 +28,7 @@ int (*current_mode) (stlink_t * stl); int (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); - int (*set_swdclk) (stlink_t * stl, uint16_t divisor); + int (*set_swdclk) (stlink_t * stl, int freq_khz); } stlink_backend_t; #endif // STLINK_BACKEND_H_ diff --git a/inc/stlink.h b/inc/stlink.h index 2ec2db367..7fce9d3dc 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -242,7 +242,7 @@ int stlink_step(stlink_t *sl); int stlink_current_mode(stlink_t *sl); int stlink_force_debug(stlink_t *sl); int stlink_target_voltage(stlink_t *sl); -int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); +int stlink_set_swdclk(stlink_t *sl, int freq_khz); int stlink_erase_flash_mass(stlink_t* sl); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); diff --git a/src/common.c b/src/common.c index 89f27aa66..7321b39a4 100644 --- a/src/common.c +++ b/src/common.c @@ -1491,9 +1491,9 @@ int stlink_run(stlink_t *sl) { return(sl->backend->run(sl)); } -int stlink_set_swdclk(stlink_t *sl, uint16_t divisor) { +int stlink_set_swdclk(stlink_t *sl, int freq_khz) { DLOG("*** set_swdclk ***\n"); - return(sl->backend->set_swdclk(sl, divisor)); + return(sl->backend->set_swdclk(sl, freq_khz)); } int stlink_status(stlink_t *sl) { diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 92ad4cbc5..f5a91abf4 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -651,7 +651,7 @@ int _stlink_usb_run(stlink_t* sl) { return(0); } -int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { +int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -661,6 +661,28 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { // clock speed only supported by stlink/v2 and for firmware >= 22 if (sl->version.stlink_v == 2 && sl->version.jtag_v >= 22) { + uint16_t clk_divisor; + if (clk_freq) { + const uint32_t map[] = {5, 15, 25, 50, 100, 125, 240, 480, 950, 1200, 1800, 4000}; + int speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); + switch (map[speed_index]) { + case 5: clk_divisor = STLINK_SWDCLK_5KHZ_DIVISOR; break; + case 15: clk_divisor = STLINK_SWDCLK_15KHZ_DIVISOR; break; + case 25: clk_divisor = STLINK_SWDCLK_25KHZ_DIVISOR; break; + case 50: clk_divisor = STLINK_SWDCLK_50KHZ_DIVISOR; break; + case 100: clk_divisor = STLINK_SWDCLK_100KHZ_DIVISOR; break; + case 125: clk_divisor = STLINK_SWDCLK_125KHZ_DIVISOR; break; + case 240: clk_divisor = STLINK_SWDCLK_240KHZ_DIVISOR; break; + case 480: clk_divisor = STLINK_SWDCLK_480KHZ_DIVISOR; break; + case 950: clk_divisor = STLINK_SWDCLK_950KHZ_DIVISOR; break; + case 1200: clk_divisor = STLINK_SWDCLK_1P2MHZ_DIVISOR; break; + default: + case 1800: clk_divisor = STLINK_SWDCLK_1P8MHZ_DIVISOR; break; + case 4000: clk_divisor = STLINK_SWDCLK_4MHZ_DIVISOR; break; + } + } else + clk_divisor = STLINK_SWDCLK_1P8MHZ_DIVISOR; + i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -691,7 +713,6 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { } int speeds_size = data[8]; - if (speeds_size > STLINK_V3_MAX_FREQ_NB) { speeds_size = STLINK_V3_MAX_FREQ_NB; } @@ -701,7 +722,8 @@ int _stlink_usb_set_swdclk(stlink_t* sl, uint16_t clk_divisor) { // Set to zero all the next entries for (i = speeds_size; i < STLINK_V3_MAX_FREQ_NB; i++) map[i] = 0; - speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), 1800); + if (!clk_freq) clk_freq = 1800; // set default frequency + speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); i = fill_command(sl, SG_DXFER_FROM_DEV, 16); @@ -1228,45 +1250,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL // should be done at this speed too // set the stlink clock speed (default is 1800kHz) DLOG("JTAG/SWD freq set to %d\n", freq); - - switch (freq) { - case 5: - stlink_set_swdclk(sl, STLINK_SWDCLK_5KHZ_DIVISOR); - break; - case 15: - stlink_set_swdclk(sl, STLINK_SWDCLK_15KHZ_DIVISOR); - break; - case 25: - stlink_set_swdclk(sl, STLINK_SWDCLK_25KHZ_DIVISOR); - break; - case 50: - stlink_set_swdclk(sl, STLINK_SWDCLK_50KHZ_DIVISOR); - break; - case 100: - stlink_set_swdclk(sl, STLINK_SWDCLK_100KHZ_DIVISOR); - break; - case 125: - stlink_set_swdclk(sl, STLINK_SWDCLK_125KHZ_DIVISOR); - break; - case 240: - stlink_set_swdclk(sl, STLINK_SWDCLK_240KHZ_DIVISOR); - break; - case 480: - stlink_set_swdclk(sl, STLINK_SWDCLK_480KHZ_DIVISOR); - break; - case 950: - stlink_set_swdclk(sl, STLINK_SWDCLK_950KHZ_DIVISOR); - break; - case 1200: - stlink_set_swdclk(sl, STLINK_SWDCLK_1P2MHZ_DIVISOR); - break; - case 0: case 1800: - stlink_set_swdclk(sl, STLINK_SWDCLK_1P8MHZ_DIVISOR); - break; - case 4000: - stlink_set_swdclk(sl, STLINK_SWDCLK_4MHZ_DIVISOR); - break; - } + stlink_set_swdclk(sl, freq); if (reset == 2) { stlink_jtag_reset(sl, 0); From 2acfa8b8f2211d5d53e3e39fa79c90c56dd54409 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Thu, 5 Nov 2020 20:42:32 +0500 Subject: [PATCH 1034/1435] Add debug message of current CPU mode --- src/common.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/common.c b/src/common.c index 7321b39a4..8eb3370ef 100644 --- a/src/common.c +++ b/src/common.c @@ -1487,7 +1487,12 @@ int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { } int stlink_run(stlink_t *sl) { + struct stlink_reg rr; DLOG("*** stlink_run ***\n"); + + stlink_read_reg(sl, 16, &rr); + DLOG("Run in %s mode\n", (rr.xpsr & (1 << 24))?"ARM":"THUMB"); + return(sl->backend->run(sl)); } From 4e58872913acd4bcbef5ac9b63514cb04bba4727 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Fri, 6 Nov 2020 16:17:54 +0500 Subject: [PATCH 1035/1435] Add printing st-link version to st-info --- src/common.c | 2 +- src/st-info/info.c | 30 +++++++++++++++++++++++------- 2 files changed, 24 insertions(+), 8 deletions(-) diff --git a/src/common.c b/src/common.c index 8eb3370ef..d04d10049 100644 --- a/src/common.c +++ b/src/common.c @@ -1487,7 +1487,7 @@ int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { } int stlink_run(stlink_t *sl) { - struct stlink_reg rr; + struct stlink_reg rr; DLOG("*** stlink_run ***\n"); stlink_read_reg(sl, 16, &rr); diff --git a/src/st-info/info.c b/src/st-info/info.c index 2343140de..4f2fae1eb 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -35,23 +35,36 @@ static void stlink_print_serial(stlink_t *sl, bool openocd) { printf("\n"); } +static void stlink_print_version(stlink_t *sl) { + // Implementation of version printing is minimalistic + // but contains all available information from sl->version + printf("V%d", sl->version.stlink_v); + if (sl->version.jtag_v > 0) + printf("J%d", sl->version.jtag_v); + if (sl->version.swim_v > 0) + printf("S%d", sl->version.swim_v); + printf("\n"); +} + static void stlink_print_info(stlink_t *sl) { const struct stlink_chipid_params *params = NULL; if (!sl) { return; } - printf(" serial: "); + printf(" version: "); + stlink_print_version(sl); + printf(" serial: "); stlink_print_serial(sl, false); - printf(" hla-serial: "); + printf(" hla-serial: "); stlink_print_serial(sl, true); - printf(" flash: %u (pagesize: %u)\n", + printf(" flash: %u (pagesize: %u)\n", (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); - printf(" sram: %u\n", (uint32_t)sl->sram_size); - printf(" chipid: 0x%.4x\n", sl->chip_id); + printf(" sram: %u\n", (uint32_t)sl->sram_size); + printf(" chipid: 0x%.4x\n", sl->chip_id); params = stlink_chipid_get_params(sl->chip_id); - if (params) { printf(" descr: %s\n", params->description); } + if (params) { printf(" descr: %s\n", params->description); } } static void stlink_probe(void) { @@ -62,7 +75,10 @@ static void stlink_probe(void) { printf("Found %u stlink programmers\n", (unsigned int)size); - for (size_t n = 0; n < size; n++) { stlink_print_info(stdevs[n]); } + for (size_t n = 0; n < size; n++) { + if (size>1) printf("%lu.\n", n+1); + stlink_print_info(stdevs[n]); + } stlink_probe_usb_free(&stdevs, size); } From 277eee7aec00493151d940a12d697651e8977d66 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Sat, 7 Nov 2020 13:50:14 +0500 Subject: [PATCH 1036/1435] Move check of current instruction mode to stlink_run --- src/common.c | 8 +++++++- src/stlink-lib/flash_loader.c | 7 ------- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/src/common.c b/src/common.c index d04d10049..e3c4fdd2e 100644 --- a/src/common.c +++ b/src/common.c @@ -1490,8 +1490,14 @@ int stlink_run(stlink_t *sl) { struct stlink_reg rr; DLOG("*** stlink_run ***\n"); + /* Make sure we are in Thumb mode + * Cortex-M chips don't support ARM mode instructions + * xPSR may be incorrect if the vector table has invalid data */ stlink_read_reg(sl, 16, &rr); - DLOG("Run in %s mode\n", (rr.xpsr & (1 << 24))?"ARM":"THUMB"); + if ((rr.xpsr & (1 << 24)) == 0) { + ILOG("Go to Thumb mode\n"); + stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); + } return(sl->backend->run(sl)); } diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index c86aefbf7..b7726e875 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -356,13 +356,6 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe // only used on VL/F1_XL, but harmless for others stlink_write_reg(sl, fl->loader_addr, 15); // pc register - /* Make sure we are in Thumb mode */ - stlink_read_reg(sl, 16, &rr); - if ((rr.xpsr & (1 << 24)) == 0) { - ILOG("Go to Thumb mode\n"); - stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); - } - /* Run loader */ stlink_run(sl); From 54000d67acefd86df4bdb0594dee940dd04763fa Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Mon, 9 Nov 2020 13:41:51 +0500 Subject: [PATCH 1037/1435] H7 add support dual bank, mass erase and new chips --- inc/stm32.h | 2 + src/common.c | 400 ++++++++++++++++++++-------------------- src/stlink-lib/chipid.c | 31 +++- src/stlink-lib/chipid.h | 2 + 4 files changed, 239 insertions(+), 196 deletions(-) diff --git a/inc/stm32.h b/inc/stm32.h index 768fabb87..1ea0d1f04 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -14,6 +14,8 @@ /* Constant STM32 memory map figures */ #define STM32_FLASH_BASE ((uint32_t)0x08000000) +#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) +#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) #define STM32_SRAM_BASE ((uint32_t)0x20000000) #define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) diff --git a/src/common.c b/src/common.c index e3c4fdd2e..0ac2d1153 100644 --- a/src/common.c +++ b/src/common.c @@ -30,6 +30,9 @@ #define __attribute__(x) #endif +#define BANK_1 0 +#define BANK_2 1 + /* stm32f FPEC flash controller interface, pm0063 manual */ // TODO - all of this needs to be abstracted out.... // STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) @@ -50,7 +53,6 @@ #define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) #define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) #define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) -#define FLASH_BANK2_START_ADDR 0x08080000 // For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... #define FLASH_RDPTR_KEY 0x00a5 @@ -307,12 +309,17 @@ #define FLASH_H7_CR_LOCK 0 #define FLASH_H7_CR_PG 1 #define FLASH_H7_CR_SER 2 +#define FLASH_H7_CR_BER 3 #define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START 7 +#define FLASH_H7_CR_START(chipid) (chipid==STLINK_CHIPID_STM32_H7AX?5:7) #define FLASH_H7_CR_SNB 8 #define FLASH_H7_CR_SNB_MASK 0x700 #define FLASH_H7_SR_QW 2 +#define FLASH_H7_SR_WRPERR 17 +#define FLASH_H7_SR_PGSERR 18 +#define FLASH_H7_SR_STRBERR 19 +#define FLASH_H7_SR_ERROR_MASK ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | (1 << FLASH_H7_SR_WRPERR)) #define FLASH_H7_OPTCR_OPTLOCK 0 #define FLASH_H7_OPTCR_OPTSTART 1 @@ -325,10 +332,17 @@ #define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) #define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) #define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) +#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) #define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) +#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) #define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) +#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) +#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) +#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) #define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) +#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) #define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) #define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) @@ -397,7 +411,7 @@ static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { return(rdp & 0xff); } -static inline uint32_t read_flash_cr(stlink_t *sl) { +static inline uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { uint32_t reg, res; if (sl->flash_type == STLINK_FLASH_TYPE_F4) { @@ -412,9 +426,9 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { reg = STM32WB_FLASH_CR; } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - reg = FLASH_H7_CR1; + reg = (bank == BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; } else { - reg = FLASH_CR; + reg = (bank == BANK_1)?FLASH_CR:FLASH_CR2; } stlink_read_debug32(sl, reg, &res); @@ -425,15 +439,6 @@ static inline uint32_t read_flash_cr(stlink_t *sl) { return(res); } -static inline uint32_t read_flash_cr2(stlink_t *sl) { - uint32_t res; - stlink_read_debug32(sl, FLASH_CR2, &res); -#if DEBUG_FLASH - fprintf(stdout, "CR2:0x%x\n", res); -#endif - return(res); -} - static inline unsigned int is_flash_locked(stlink_t *sl) { /* return non zero for true */ uint32_t cr_lock_shift; @@ -476,7 +481,7 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { } static void unlock_flash(stlink_t *sl) { - uint32_t key_reg; + uint32_t key_reg, key2_reg = 0; uint32_t flash_key1 = FLASH_KEY1; uint32_t flash_key2 = FLASH_KEY2; /* The unlock sequence consists of 2 write cycles where 2 key values are written @@ -484,9 +489,11 @@ static void unlock_flash(stlink_t *sl) { * An invalid sequence results in a definitive lock of the FPEC block until next reset. */ - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if (sl->flash_type == STLINK_FLASH_TYPE_F0) { key_reg = FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + key_reg = FLASH_KEYR; + key2_reg = FLASH_KEYR2; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { key_reg = FLASH_F4_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { @@ -504,6 +511,9 @@ static void unlock_flash(stlink_t *sl) { key_reg = STM32WB_FLASH_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { key_reg = FLASH_H7_KEYR1; + if (sl->has_dual_bank) { + key2_reg = FLASH_H7_KEYR2; + } } else { ELOG("unsupported flash method, abort\n"); return; @@ -512,9 +522,9 @@ static void unlock_flash(stlink_t *sl) { stlink_write_debug32(sl, key_reg, flash_key1); stlink_write_debug32(sl, key_reg, flash_key2); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - stlink_write_debug32(sl, FLASH_KEYR2, flash_key1); - stlink_write_debug32(sl, FLASH_KEYR2, flash_key2); + if (key2_reg) { + stlink_write_debug32(sl, key2_reg, flash_key1); + stlink_write_debug32(sl, key2_reg, flash_key2); } } @@ -534,13 +544,16 @@ static int unlock_flash_if(stlink_t *sl) { } static void lock_flash(stlink_t *sl) { - uint32_t cr_lock_shift, cr_reg, n; + uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; uint32_t cr_mask = 0xffffffffu; - if (sl->flash_type == STLINK_FLASH_TYPE_F0 || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + if (sl->flash_type == STLINK_FLASH_TYPE_F0) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + cr_reg = FLASH_CR; + cr2_reg = FLASH_CR2; + cr_lock_shift = FLASH_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; @@ -562,6 +575,9 @@ static void lock_flash(stlink_t *sl) { cr_lock_shift = STM32WB_FLASH_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; + if (sl->has_dual_bank) { + cr2_reg = FLASH_H7_CR2; + } cr_lock_shift = FLASH_H7_CR_LOCK; cr_mask = ~(1u << FLASH_H7_CR_SER); } else { @@ -574,9 +590,9 @@ static void lock_flash(stlink_t *sl) { n |= (1u << cr_lock_shift); stlink_write_debug32(sl, cr_reg, n); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - n = read_flash_cr2(sl) | (1u << cr_lock_shift); - stlink_write_debug32(sl, FLASH_CR2, n); + if (cr2_reg) { + n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift); + stlink_write_debug32(sl, cr2_reg, n); } } @@ -637,7 +653,7 @@ static bool is_flash_option_locked(stlink_t *sl) { } static int lock_flash_option(stlink_t *sl) { - uint32_t optlock_shift, optcr_reg, n; + uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; int active_bit_level = 1; switch (sl->flash_type) { @@ -675,6 +691,8 @@ static int lock_flash_option(stlink_t *sl) { case STLINK_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + if (sl->has_dual_bank) + optcr2_reg = FLASH_H7_OPTCR2; break; default: ELOG("unsupported flash method, abort\n"); @@ -690,11 +708,24 @@ static int lock_flash_option(stlink_t *sl) { } stlink_write_debug32(sl, optcr_reg, n); + + if (optcr2_reg) { + stlink_read_debug32(sl, optcr2_reg, &n); + + if (active_bit_level == 0) { + n &= ~(1u << optlock_shift); + } else { + n |= (1u << optlock_shift); + } + + stlink_write_debug32(sl, optcr2_reg, n); + } + return(0); } static int unlock_flash_option(stlink_t *sl) { - uint32_t optkey_reg; + uint32_t optkey_reg, optkey2_reg = 0; uint32_t optkey1 = FLASH_OPTKEY1; uint32_t optkey2 = FLASH_OPTKEY2; @@ -728,6 +759,8 @@ static int unlock_flash_option(stlink_t *sl) { break; case STLINK_FLASH_TYPE_H7: optkey_reg = FLASH_H7_OPT_KEYR; + if (sl->has_dual_bank) + optkey2_reg = FLASH_H7_OPT_KEYR2; break; default: ELOG("unsupported flash method, abort\n"); @@ -736,6 +769,12 @@ static int unlock_flash_option(stlink_t *sl) { stlink_write_debug32(sl, optkey_reg, optkey1); stlink_write_debug32(sl, optkey_reg, optkey2); + + if (optkey2_reg) { + stlink_write_debug32(sl, optkey2_reg, optkey1); + stlink_write_debug32(sl, optkey2_reg, optkey2); + } + return(0); } @@ -756,10 +795,10 @@ static int unlock_flash_option_if(stlink_t *sl) { return(0); } -static void set_flash_cr_pg(stlink_t *sl) { +static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { uint32_t cr_reg, x; - x = read_flash_cr(sl); + x = read_flash_cr(sl, bank); if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; @@ -779,7 +818,7 @@ static void set_flash_cr_pg(stlink_t *sl) { cr_reg = STM32WB_FLASH_CR; x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; + cr_reg = (bank == BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; x |= (1 << FLASH_H7_CR_PG); } else { cr_reg = FLASH_CR; @@ -789,8 +828,9 @@ static void set_flash_cr_pg(stlink_t *sl) { stlink_write_debug32(sl, cr_reg, x); } -static void clear_flash_cr_pg(stlink_t *sl) { +static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { uint32_t cr_reg, n; + uint32_t bit = FLASH_CR_PG; if (sl->flash_type == STLINK_FLASH_TYPE_F4) { cr_reg = FLASH_F4_CR; @@ -803,15 +843,18 @@ static void clear_flash_cr_pg(stlink_t *sl) { cr_reg = STM32Gx_FLASH_CR; } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; + bit = FLASH_H7_CR_PG; } else { cr_reg = FLASH_CR; } - n = read_flash_cr(sl) & ~(1 << FLASH_CR_PG); + n = read_flash_cr(sl, bank) & ~(1 << bit); stlink_write_debug32(sl, cr_reg, n); } -static void set_flash_cr_per(stlink_t *sl) { +static void set_flash_cr_per(stlink_t *sl, unsigned bank) { uint32_t cr_reg, val; if (sl->flash_type == STLINK_FLASH_TYPE_G0 || @@ -820,7 +863,7 @@ static void set_flash_cr_per(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; } else { - cr_reg = FLASH_CR; + cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; } stlink_read_debug32(sl, cr_reg, &val); @@ -828,12 +871,7 @@ static void set_flash_cr_per(stlink_t *sl) { stlink_write_debug32(sl, cr_reg, val); } -static void set_flash_cr2_per(stlink_t *sl) { - const uint32_t n = (1 << FLASH_CR_PER); - stlink_write_debug32(sl, FLASH_CR2, n); -} - -static void clear_flash_cr_per(stlink_t *sl) { +static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { uint32_t cr_reg; if (sl->flash_type == STLINK_FLASH_TYPE_G0 || @@ -842,14 +880,14 @@ static void clear_flash_cr_per(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { cr_reg = STM32WB_FLASH_CR; } else { - cr_reg = FLASH_CR; + cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; } - const uint32_t n = read_flash_cr(sl) & ~(1 << FLASH_CR_PER); + const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER); stlink_write_debug32(sl, cr_reg, n); } -static void set_flash_cr_mer(stlink_t *sl, bool v) { +static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { uint32_t val, cr_reg, cr_mer, cr_pg; if (sl->flash_type == STLINK_FLASH_TYPE_F4) { @@ -878,8 +916,12 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { cr_reg = STM32WB_FLASH_CR; cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; + cr_mer = (1 << FLASH_H7_CR_BER); + cr_pg = (1 << FLASH_H7_CR_PG); } else { - cr_reg = FLASH_CR; + cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); } @@ -901,46 +943,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { stlink_write_debug32(sl, cr_reg, val); } -static void set_flash_cr2_mer(stlink_t *sl, bool v) { - const uint32_t cr_pg = (1 << FLASH_CR_PER); - const uint32_t cr_mer = (1 << FLASH_CR_MER); - uint32_t val; - - stlink_read_debug32(sl, FLASH_CR2, &val); - val &= ~cr_pg; - - if (v) { - val |= cr_mer; - } else { - val &= ~cr_mer; - } - - stlink_write_debug32(sl, FLASH_CR2, val); -} - -static void __attribute__((unused)) clear_flash_cr_mer(stlink_t *sl) { - uint32_t val, cr_reg, cr_mer; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_mer = 1 << FLASH_CR_MER; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_mer = 1 << FLASH_CR_MER; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); - } else { - cr_reg = FLASH_CR; - cr_mer = (1 << FLASH_CR_MER); - } - - stlink_read_debug32(sl, cr_reg, &val); - val &= ~cr_mer; - stlink_write_debug32(sl, cr_reg, val); -} - -static void set_flash_cr_strt(stlink_t *sl) { +static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { uint32_t val, cr_reg, cr_strt; if (sl->flash_type == STLINK_FLASH_TYPE_F4) { @@ -960,10 +963,10 @@ static void set_flash_cr_strt(stlink_t *sl) { cr_reg = STM32WB_FLASH_CR; cr_strt = (1 << STM32WB_FLASH_CR_STRT); } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - cr_strt = 1 << FLASH_H7_CR_START; + cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; + cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); } else { - cr_reg = FLASH_CR; + cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; cr_strt = (1 << FLASH_CR_STRT); } @@ -972,20 +975,12 @@ static void set_flash_cr_strt(stlink_t *sl) { stlink_write_debug32(sl, cr_reg, val); } -static void set_flash_cr2_strt(stlink_t *sl) { - uint32_t val; - - stlink_read_debug32(sl, FLASH_CR2, &val); - val |= 1 << FLASH_CR_STRT; - stlink_write_debug32(sl, FLASH_CR2, val); -} - -static inline uint32_t read_flash_sr(stlink_t *sl) { +static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { uint32_t res, sr_reg; if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - sr_reg = FLASH_SR; + sr_reg = (bank==BANK_1)?FLASH_SR:FLASH_SR2; } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { @@ -1000,7 +995,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { sr_reg = STM32WB_FLASH_SR; } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - sr_reg = FLASH_H7_SR1; + sr_reg = (bank==BANK_1)?FLASH_H7_SR1:FLASH_H7_SR2; } else { ELOG("unsupported flash method, abort"); return(-1); @@ -1010,12 +1005,6 @@ static inline uint32_t read_flash_sr(stlink_t *sl) { return(res); } -static inline uint32_t read_flash_sr2(stlink_t *sl) { - uint32_t res; - stlink_read_debug32(sl, FLASH_SR2, &res); - return(res); -} - static inline unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; unsigned int res; @@ -1042,10 +1031,11 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { return(-1); } - res = read_flash_sr(sl) & (1 << sr_busy_shift); + res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - res |= read_flash_sr2(sl) & (1 << sr_busy_shift); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank)) { + res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); } return(res); @@ -1081,17 +1071,31 @@ static int check_flash_error(stlink_t *sl) switch (sl->flash_type) { case STLINK_FLASH_TYPE_F0: - res = read_flash_sr(sl) & FLASH_SR_ERROR_MASK; + res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; break; case STLINK_FLASH_TYPE_F7: - res = read_flash_sr(sl) & FLASH_F7_SR_ERROR_MASK; + res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; break; case STLINK_FLASH_TYPE_G0: case STLINK_FLASH_TYPE_G4: - res = read_flash_sr(sl) & STM32Gx_FLASH_SR_ERROR_MASK; + res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; break; case STLINK_FLASH_TYPE_L0: - res = read_flash_sr(sl) & STM32L0_FLASH_SR_ERROR_MASK; + res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; + break; + case STLINK_FLASH_TYPE_H7: + res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; + if (sl->has_dual_bank) { + res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; + } + if (res) { + // Clear errors + stlink_write_debug32(sl, FLASH_H7_CCR1, res); + if (sl->has_dual_bank) { + stlink_write_debug32(sl, FLASH_H7_CCR2, res); + } + } + break; default: break; } @@ -1104,35 +1108,16 @@ static int check_flash_error(stlink_t *sl) return(0); } -static inline unsigned int is_flash_eop(stlink_t *sl) { - return(read_flash_sr(sl) & (1 << FLASH_SR_EOP)); -} - -static void __attribute__((unused)) clear_flash_sr_eop(stlink_t *sl) { - const uint32_t n = read_flash_sr(sl) & ~(1 << FLASH_SR_EOP); - stlink_write_debug32(sl, FLASH_SR, n); -} - -static void __attribute__((unused)) wait_flash_eop(stlink_t *sl) { - // TODO: add some delays here - while (is_flash_eop(sl) == 0) - ; -} - -static inline void write_flash_ar(stlink_t *sl, uint32_t n) { - stlink_write_debug32(sl, FLASH_AR, n); -} - -static inline void write_flash_ar2(stlink_t *sl, uint32_t n) { - stlink_write_debug32(sl, FLASH_AR2, n); +static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { + stlink_write_debug32(sl, (bank==BANK_1)?FLASH_AR:FLASH_AR2, n); } -static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) { +static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n, unsigned bank) { uint32_t cr_reg, psize_shift; - uint32_t x = read_flash_cr(sl); + uint32_t x = read_flash_cr(sl, bank); if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; + cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; psize_shift = FLASH_H7_CR_PSIZE; } else { cr_reg = FLASH_F4_CR; @@ -1147,12 +1132,12 @@ static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n) { stlink_write_debug32(sl, cr_reg, x); } -static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { +static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { uint32_t cr_reg, snb_mask, snb_shift, ser_shift; - uint32_t x = read_flash_cr(sl); + uint32_t x = read_flash_cr(sl, bank); if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; + cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; snb_mask = FLASH_H7_CR_SNB_MASK; snb_shift = FLASH_H7_CR_SNB; ser_shift = FLASH_H7_CR_SER; @@ -1174,7 +1159,7 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n) { static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { stlink_write_debug32(sl, STM32L4_FLASH_SR, 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); - uint32_t x = read_flash_cr(sl); + uint32_t x = read_flash_cr(sl, BANK_1); x &= ~STM32L4_FLASH_CR_OPBITS; x &= ~STM32L4_FLASH_CR_PAGEMASK; x &= ~(1 << STM32L4_FLASH_CR_MER1); @@ -1391,6 +1376,11 @@ int stlink_load_device_params(stlink_t *sl) { if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { sl->flash_pgsz <<= 1; } } + // H7 devices with small flash has one bank + if (sl->has_dual_bank && sl->flash_type == STLINK_FLASH_TYPE_H7) { + sl->has_dual_bank = (flash_size/sl->flash_pgsz) > 1; + } + #if 0 // Old code -- REW ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); @@ -2314,9 +2304,9 @@ uint32_t calculate_F7_sectornum(uint32_t flashaddr) { } -uint32_t calculate_H7_sectornum(uint32_t flashaddr) { - flashaddr &= ~STM32_FLASH_BASE; // sector holding the flash address - return(flashaddr / 0x20000); +uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, unsigned bank) { + flashaddr &= ~((bank==BANK_1)?STM32_FLASH_BASE:STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address + return(flashaddr / sl->flash_pgsz); } // returns BKER:PNB for the given page address @@ -2392,8 +2382,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_F7 || - sl->flash_type == STLINK_FLASH_TYPE_L4 || - sl->flash_type == STLINK_FLASH_TYPE_H7) { + sl->flash_type == STLINK_FLASH_TYPE_L4) { // wait for ongoing op to finish wait_flash_busy(sl); @@ -2420,14 +2409,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); - write_flash_cr_snb(sl, sector); - } else if (sl->chip_id == STLINK_CHIPID_STM32_H74XXX) { - // calculate the actual page from the address - uint32_t sector = calculate_H7_sectornum(flashaddr); - - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", - sector, stlink_calculate_pagesize(sl, flashaddr)); - write_flash_cr_snb(sl, sector); + write_flash_cr_snb(sl, sector, BANK_1); } else { // calculate the actual page from the address uint32_t sector = calculate_F4_sectornum(flashaddr); @@ -2439,14 +2421,14 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // follow the values for the first bank on 2mb devices... if (sector >= 12) { sector += 4; } - write_flash_cr_snb(sl, sector); + write_flash_cr_snb(sl, sector, BANK_1); } - set_flash_cr_strt(sl); // start erase operation + set_flash_cr_strt(sl, BANK_1); // start erase operation wait_flash_busy(sl); // wait for completion lock_flash(sl); // TODO: fails to program if this is in #if DEBUG_FLASH - fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl)); + fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); #endif } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { @@ -2526,7 +2508,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { uint32_t val; wait_flash_busy(sl); // wait for any ongoing Flash operation to finish unlock_flash_if(sl); - set_flash_cr_per(sl); // set the 'enable Flash erase' bit + set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit // set the page to erase if (sl->flash_type == STLINK_FLASH_TYPE_WB) { @@ -2554,27 +2536,29 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); } - set_flash_cr_strt(sl); // set the 'start operation' bit + set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit wait_flash_busy(sl); // wait for the 'busy' bit to clear - clear_flash_cr_per(sl); // clear the 'enable page erase' bit + clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit lock_flash(sl); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr < FLASH_BANK2_START_ADDR))) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || + sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE)?BANK_1:BANK_2; wait_flash_busy(sl); unlock_flash_if(sl); - clear_flash_cr_pg(sl); // clear the pg bit - set_flash_cr_per(sl); // set the page erase bit - write_flash_ar(sl, flashaddr); // select the page to erase - set_flash_cr_strt(sl); // start erase operation, reset by hw with busy bit + clear_flash_cr_pg(sl, bank); // clear the pg bit + set_flash_cr_per(sl, bank); // set the page erase bit + write_flash_ar(sl, flashaddr, bank); // select the page to erase + set_flash_cr_strt(sl, bank); // start erase operation, reset by hw with busy bit wait_flash_busy(sl); lock_flash(sl); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (flashaddr >= FLASH_BANK2_START_ADDR)) { - wait_flash_busy(sl); - unlock_flash_if(sl); - set_flash_cr2_per(sl); // set the page erase bit - write_flash_ar2(sl, flashaddr); // select the page to erase - set_flash_cr2_strt(sl); // start erase operation, reset by hw with busy bit - wait_flash_busy(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE)?BANK_1:BANK_2; + wait_flash_busy(sl); // wait for ongoing op to finish + unlock_flash_if(sl); // unlock if locked + uint32_t sector = calculate_H7_sectornum(sl, flashaddr, bank);// calculate the actual page from the address + write_flash_cr_snb(sl, sector, bank); // select the page to erase + set_flash_cr_strt(sl, bank); // start erase operation + wait_flash_busy(sl); // wait for completion lock_flash(sl); } else { WLOG("unknown coreid %x, page erase failed\n", sl->core_id); @@ -2586,7 +2570,9 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } int stlink_erase_flash_mass(stlink_t *sl) { - // TODO: User MER bit to mass-erase G0, G4, WB series. + int err = 0; + + // TODO: User MER bit to mass-erase WB series. if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_WB) { // erase each page @@ -2609,28 +2595,39 @@ int stlink_erase_flash_mass(stlink_t *sl) { } else { wait_flash_busy(sl); unlock_flash_if(sl); - set_flash_cr_mer(sl, 1); // set the mass erase bit - set_flash_cr_strt(sl); // start erase operation, reset by hw with busy bit - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - set_flash_cr2_mer(sl, 1); // set the mass erase bit in bank 2 - set_flash_cr2_strt(sl); // start erase operation in bank 2 + if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_id != STLINK_CHIPID_STM32_H7AX) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->has_dual_bank) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } + + set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit + set_flash_cr_strt(sl, BANK_1); // start erase operation, reset by hw with busy bit + + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank)) { + set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 + set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 } wait_flash_busy_progress(sl); - check_flash_error(sl); + err = check_flash_error(sl); lock_flash(sl); - set_flash_cr_mer(sl, 0); // reset the mass erase bit - - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - set_flash_cr2_mer(sl, 0); // reset the mass erase bit in bank 2 + // reset the mass erase bit + set_flash_cr_mer(sl, 0, BANK_1); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank)) { + set_flash_cr_mer(sl, 0, BANK_2); } // TODO: verify the erased memory } - return(0); + return(err); } int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { @@ -2786,16 +2783,16 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { } else { if (voltage > 2700) { ILOG("enabling 32-bit flash writes\n"); - write_flash_cr_psiz(sl, 2); + write_flash_cr_psiz(sl, 2, BANK_1); } else { ILOG("Target voltage (%d mV) too low for 32-bit flash, " "using 8-bit flash writes\n", voltage); - write_flash_cr_psiz(sl, 0); + write_flash_cr_psiz(sl, 0, BANK_1); } } // set programming mode - set_flash_cr_pg(sl); + set_flash_cr_pg(sl, BANK_1); } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { @@ -2803,7 +2800,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { wait_flash_busy(sl); unlock_flash_if(sl); // unlock flash if necessary - set_flash_cr_pg(sl); // set PG 'allow programming' bit + set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { ILOG("Starting Flash write for L0\n"); @@ -2852,7 +2849,17 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { ILOG("Starting Flash write for H7\n"); unlock_flash_if(sl); // unlock the cr - set_flash_cr_pg(sl); // set programming mode + set_flash_cr_pg(sl, BANK_1); // set programming mode + if (sl->has_dual_bank) { + set_flash_cr_pg(sl, BANK_2); + } + if (sl->chip_id != STLINK_CHIPID_STM32_H7AX) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->has_dual_bank) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } } else { ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); return(-1); @@ -2961,7 +2968,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr // unlock and set programming mode unlock_flash_if(sl); - if (sl->flash_type != STLINK_FLASH_TYPE_F1_XL) { set_flash_cr_pg(sl); } + if (sl->flash_type != STLINK_FLASH_TYPE_F1_XL) { set_flash_cr_pg(sl, BANK_1); } DLOG("Finished unlocking flash, running loader!\n"); @@ -2984,10 +2991,10 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr } } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { for (off = 0; off < len;) { - // Program STM32H7x with 32-byte Flash words - size_t chunk = (len - off > 32) ? 32 : len - off; + // Program STM32H7x with 64-byte Flash words + size_t chunk = (len - off > 64) ? 64 : len - off; memcpy(sl->q_buf, base + off, chunk); - stlink_write_mem32(sl, addr + (uint32_t)off, 32); + stlink_write_mem32(sl, addr + (uint32_t)off, 64); wait_flash_busy(sl); off += chunk; @@ -3009,7 +3016,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr } int stlink_flashloader_stop(stlink_t *sl) { - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_F7) || (sl->flash_type == STLINK_FLASH_TYPE_L4) || (sl->flash_type == STLINK_FLASH_TYPE_WB) || @@ -3017,7 +3024,10 @@ int stlink_flashloader_stop(stlink_t *sl) { (sl->flash_type == STLINK_FLASH_TYPE_G4) || (sl->flash_type == STLINK_FLASH_TYPE_H7)) { - clear_flash_cr_pg(sl); + clear_flash_cr_pg(sl, BANK_1); + if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank) { + clear_flash_cr_pg(sl, BANK_2); + } lock_flash(sl); } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { uint32_t val; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index c191fa919..5cf2ddd1c 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -617,8 +617,9 @@ static const struct stlink_chipid_params devices[] = { { // STM32H742/743/753 (from RM0433) .chip_id = STLINK_CHIPID_STM32_H74XXX, - .description = "H742/743/753", + .description = "H74x/H75x", .flash_type = STLINK_FLASH_TYPE_H7, + .has_dual_bank = true, .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) .flash_pagesize = 0x20000, // 128k sector (pg147) .sram_size = 0x20000, // 128k "DTCM" from Table 7 @@ -627,6 +628,34 @@ static const struct stlink_chipid_params devices[] = { .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 }, + { + // STM32H7A3/7B3 (from RM0455) + .chip_id = STLINK_CHIPID_STM32_H7AX, + .description = "H7Ax/H7Bx", + .flash_type = STLINK_FLASH_TYPE_H7, + .has_dual_bank = true, + .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) + .flash_pagesize = 0x2000, // 8k sector (p.146) + .sram_size = 0x20000, // 128k "DTCM" (Figure 1) + .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 12-14) + .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to two banks (Table 12-14) + .option_base = STM32_H7_OPTION_BYTES_BASE, + .option_size = 44, + }, + { + // STM32H72x/H73x (from RM0468) + .chip_id = STLINK_CHIPID_STM32_H72X, + .description = "H72x/H73x", + .flash_type = STLINK_FLASH_TYPE_H7, + .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) + .flash_pagesize = 0x20000, // 128k sector (p.152) + .sram_size = 0x20000, // 128k "DTCM" (Figure 1) + .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 6) + .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) + .option_base = STM32_H7_OPTION_BYTES_BASE, + .option_size = 44, + }, + { // unknown .chip_id = STLINK_CHIPID_UNKNOWN, diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f717022ca..a342df2dc 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -64,6 +64,8 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ STLINK_CHIPID_STM32_G4_CAT3 = 0x469, STLINK_CHIPID_STM32_L4RX = 0x470, /* ID found on the STM32L4R9I-DISCO board */ + STLINK_CHIPID_STM32_H7AX = 0x480, /* RM0455, p. 2863 */ + STLINK_CHIPID_STM32_H72X = 0x483, /* RM0468, p. 3199 */ STLINK_CHIPID_STM32_WB55 = 0x495 }; From d902fba40aa3db82c4b144849a5ea427492cb06e Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Wed, 11 Nov 2020 19:57:57 +0500 Subject: [PATCH 1038/1435] Fix printf format --- src/st-info/info.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/st-info/info.c b/src/st-info/info.c index 4f2fae1eb..2e1ce0e96 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -38,11 +38,11 @@ static void stlink_print_serial(stlink_t *sl, bool openocd) { static void stlink_print_version(stlink_t *sl) { // Implementation of version printing is minimalistic // but contains all available information from sl->version - printf("V%d", sl->version.stlink_v); + printf("V%u", sl->version.stlink_v); if (sl->version.jtag_v > 0) - printf("J%d", sl->version.jtag_v); + printf("J%u", sl->version.jtag_v); if (sl->version.swim_v > 0) - printf("S%d", sl->version.swim_v); + printf("S%u", sl->version.swim_v); printf("\n"); } From 79b225945b93a6306f374eb9438d78136d3fea8f Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Thu, 12 Nov 2020 22:39:49 +0200 Subject: [PATCH 1039/1435] link for WIN32 & APPLE with stlink-static --- CMakeLists.txt | 12 ++++++------ tests/CMakeLists.txt | 12 +++++++++--- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index fae458dd7..824c3671e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -155,11 +155,7 @@ execute_process(COMMAND bash -c "export LD_LIBRARY_PATH=${CMAKE_INSTALL_LIBDIR}" ### # Set library name -if (NOT WIN32) - set(STLINK_LIB_SHARED ${PROJECT_NAME}) -else (WIN32) - set(STLINK_LIB_SHARED ${PROJECT_NAME}-shared) -endif () +set(STLINK_LIB_SHARED ${PROJECT_NAME}-shared) add_library(${STLINK_LIB_SHARED} SHARED ${STLINK_HEADERS} ${STLINK_SOURCE}) @@ -195,6 +191,10 @@ install(TARGETS ${STLINK_LIB_SHARED} DESTINATION ${STLINK_LIBRARY_PATH}) # Set library name set(STLINK_LIB_STATIC ${PROJECT_NAME}-static) +set(STLINK_LIB_STATIC_OUTPUT_NAME ${PROJECT_NAME}) +if (MSVC) + set(STLINK_LIB_STATIC_OUTPUT_NAME ${PROJECT_NAME}-static) +endif() add_library(${STLINK_LIB_STATIC} STATIC ${STLINK_HEADERS} ${STLINK_SOURCE}) @@ -206,7 +206,7 @@ message(STATUS "VERSION: ${STLINK_STATIC_VERSION}") set_target_properties(${STLINK_LIB_STATIC} PROPERTIES SOVERSION ${PROJECT_VERSION_MAJOR} VERSION ${STLINK_STATIC_VERSION} - OUTPUT_NAME ${PROJECT_NAME} + OUTPUT_NAME ${STLINK_LIB_STATIC_OUTPUT_NAME} ) # Link static library diff --git a/tests/CMakeLists.txt b/tests/CMakeLists.txt index a3011fc7e..0f23214d6 100644 --- a/tests/CMakeLists.txt +++ b/tests/CMakeLists.txt @@ -4,13 +4,19 @@ set(TESTEXEC usb sg) +set(TEST_DEPENDENCY ${STLINK_LIB_SHARED}) +if (WIN32 OR APPLE) + set(TEST_DEPENDENCY ${STLINK_LIB_STATIC}) +endif() + foreach (test ${TESTEXEC}) add_executable(test-${test} ${test}.c) - add_dependencies(test-${test} ${STLINK_LIB_SHARED}) - target_link_libraries(test-${test} ${STLINK_LIB_SHARED} ${SSP_LIB}) + add_dependencies(test-${test} ${TEST_DEPENDENCY}) + target_link_libraries(test-${test} ${TEST_DEPENDENCY} ${SSP_LIB}) add_test(test-${test} ${CMAKE_BINARY_DIR}/bin/test-${test}) endforeach () add_executable(test-flash flash.c "${CMAKE_SOURCE_DIR}/src/st-flash/flash_opts.c") -target_link_libraries(test-flash ${STLINK_LIB_SHARED} ${SSP_LIB}) +add_dependencies(test-flash ${TEST_DEPENDENCY}) +target_link_libraries(test-flash ${TEST_DEPENDENCY} ${SSP_LIB}) add_test(test-flash ${CMAKE_BINARY_DIR}/bin/test-flash) From 27d3144fce97ecf8ece522b96ad5c60eb8dc446d Mon Sep 17 00:00:00 2001 From: John Hall Date: Wed, 25 Nov 2020 10:51:20 -0800 Subject: [PATCH 1040/1435] Adding framework for st-trace. --- .gitignore | 1 + CMakeLists.txt | 5 ++ src/st-trace/trace.c | 143 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 149 insertions(+) create mode 100644 src/st-trace/trace.c diff --git a/.gitignore b/.gitignore index 9fbe0139c..8b1dc465d 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,4 @@ build-mingw obj-* *.user* .cmake/ +*.swp diff --git a/CMakeLists.txt b/CMakeLists.txt index 824c3671e..08a889660 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -231,6 +231,7 @@ install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH}) set(ST-FLASH_SOURCES src/st-flash/flash.c src/st-flash/flash_opts.c) set(ST-INFO_SOURCES src/st-info/info.c) set(ST-UTIL_SOURCES src/st-util/gdb-remote.c src/st-util/gdb-server.c src/st-util/semihosting.c) +set(ST-TRACE_SOURCES src/st-trace/trace.c) if (MSVC) # Add getopt to sources @@ -241,20 +242,24 @@ endif () add_executable(st-flash ${ST-FLASH_SOURCES}) add_executable(st-info ${ST-INFO_SOURCES}) add_executable(st-util ${ST-UTIL_SOURCES}) +add_executable(st-trace ${ST-TRACE_SOURCES}) if (WIN32 OR APPLE) target_link_libraries(st-flash ${STLINK_LIB_STATIC} ${SSP_LIB}) target_link_libraries(st-info ${STLINK_LIB_STATIC} ${SSP_LIB}) target_link_libraries(st-util ${STLINK_LIB_STATIC} ${SSP_LIB}) + target_link_libraries(st-trace ${STLINK_LIB_STATIC} ${SSP_LIB}) else () target_link_libraries(st-flash ${STLINK_LIB_SHARED} ${SSP_LIB}) target_link_libraries(st-info ${STLINK_LIB_SHARED} ${SSP_LIB}) target_link_libraries(st-util ${STLINK_LIB_SHARED} ${SSP_LIB}) + target_link_libraries(st-trace ${STLINK_LIB_SHARED} ${SSP_LIB}) endif () install(TARGETS st-flash DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-info DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-util DESTINATION ${CMAKE_INSTALL_BINDIR}) +install(TARGETS st-trace DESTINATION ${CMAKE_INSTALL_BINDIR}) ### diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c new file mode 100644 index 000000000..d7ece29d4 --- /dev/null +++ b/src/st-trace/trace.c @@ -0,0 +1,143 @@ +#include +#include +#include +#include +#include +#include + +#include +#include + + +#define DEFAULT_LOGGING_LEVEL 50 +#define DEBUG_LOGGING_LEVEL 100 + +#define APP_RESULT_SUCCESS 0 +#define APP_RESULT_INVALID_PARAMS 1 + + +struct _st_settings_t +{ + bool show_help; + bool show_version; + int logging_level; + int core_frequency_mhz; + bool reset_board; + char* serial_number; + bool wait_sync; +}; +typedef struct _st_settings_t st_settings_t; + + +static void usage(void) { + puts("st-trace - usage:"); + puts(" -h, --help Print this help"); + puts(" -V, --version Print this version"); + puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); + puts(" -v, --verbose Specify a generally verbose logging"); + puts(" -cXX, --clock=XX Specify the core frequency in MHz"); + puts(" -n, --no-reset Do not reset board on connection"); + puts(" -sXX, --serial=XX Use a specific serial number"); + puts(" -a, --no-sync Do not wait for a sync packet"); +} + +bool parse_options(int argc, char** argv, st_settings_t *settings) { + + static struct option long_options[] = { + {"help", no_argument, NULL, 'h'}, + {"version", no_argument, NULL, 'V'}, + {"verbose", optional_argument, NULL, 'v'}, + {"clock", required_argument, NULL, 'c'}, + {"no-reset", no_argument, NULL, 'n'}, + {"serial", required_argument, NULL, 's'}, + {"no-sync", no_argument, NULL, 'a'}, + {0, 0, 0, 0}, + }; + int option_index = 0; + int c; + + settings->show_help = false; + settings->show_version = false; + settings->logging_level = DEFAULT_LOGGING_LEVEL; + settings->core_frequency_mhz = 0; + settings->reset_board = true; + settings->serial_number = NULL; + settings->wait_sync = true; + + while ((c = getopt_long(argc, argv, "hVv::c:ns:a", long_options, &option_index)) != -1) { + switch (c) { + case 'h': + settings->show_help = true; + break; + case 'V': + settings->show_version = true; + break; + case 'v': + if (optarg) { + settings->logging_level = atoi(optarg); + } else { + settings->logging_level = DEBUG_LOGGING_LEVEL; + } + break; + case 'c': + settings->core_frequency_mhz = atoi(optarg); + break; + case 'n': + settings->reset_board = false; + break; + case 's': + settings->serial_number = optarg; + break; + case 'a': + settings->wait_sync = false; + break; + case '?': + return false; + break; + default: + printf("ERROR: Unknown command line option: '%c' (0x%02x)\n", c, c); + return false; + } + } + + if (optind < argc) { + while (optind < argc) { + printf("ERROR: Unknown command line argument: '%s'\n", argv[optind++]); + } + return false; + } + + return true; +} + +int main(int argc, char** argv) +{ + st_settings_t settings; + + if (!parse_options(argc, argv, &settings)) { + usage(); + return APP_RESULT_INVALID_PARAMS; + } + + /* if (settings.logging_level >= UDEBUG) */ + printf("show_help = %s\n", settings.show_help ? "true" : "false"); + printf("show_version = %s\n", settings.show_version ? "true" : "false"); + printf("logging_level = %d\n", settings.logging_level); + printf("core_frequency = %d MHz\n", settings.core_frequency_mhz); + printf("reset_board = %s\n", settings.reset_board ? "true" : "false"); + printf("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); + printf("wait_sync = %s\n", settings.wait_sync ? "true" : "false"); + + if (settings.show_help) { + usage(); + return APP_RESULT_SUCCESS; + } + + if (settings.show_version) { + printf("v%s\n", STLINK_VERSION); + return APP_RESULT_SUCCESS; + } + + return APP_RESULT_SUCCESS; +} + From 0f411da1d75620e5b005643afaf7110cf25b2d70 Mon Sep 17 00:00:00 2001 From: John Hall Date: Wed, 25 Nov 2020 23:49:42 +0000 Subject: [PATCH 1041/1435] Getting to build on raspberry pi. Adding calls to identify st-links. --- raspberrypi-build.sh | 20 +++++++++++ src/st-trace/trace.c | 80 +++++++++++++++++++++++++++++++++----------- 2 files changed, 81 insertions(+), 19 deletions(-) create mode 100755 raspberrypi-build.sh diff --git a/raspberrypi-build.sh b/raspberrypi-build.sh new file mode 100755 index 000000000..7f77dab45 --- /dev/null +++ b/raspberrypi-build.sh @@ -0,0 +1,20 @@ +#!/bin/bash + +mkdir -p build/raspberry +mkdir -p build/raspberry/inc +mkdir -p build/raspberry/bin + +cat << EOF > build/raspberry/inc/version.h +#ifndef STLINK_VERSION_H_ +#define STLINK_VERSION_H_ + +#define STLINK_VERSION "1.6.1-116-g27d3-pi-dirty" +#define STLINK_VERSION_MAJOR 1 +#define STLINK_VERSION_MINOR 6 +#define STLINK_VERSION_PATCH 1 + +#endif // STLINK_VERSION_H_ +EOF + +gcc -std=gnu99 -Iinc -Isrc/stlink-lib/ -I/usr/include/libusb-1.0/ -Ibuild/raspberry/inc -DLIBUSB_API_VERSION=MINIMAL_API_VERSION -DSTLINK_HAVE_SYS_MMAN_H src/*.c src/stlink-lib/*.c src/st-trace/*.c -lusb-1.0 -o build/raspberry/bin/st-trace + diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index d7ece29d4..03f1ac43d 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -12,8 +12,9 @@ #define DEFAULT_LOGGING_LEVEL 50 #define DEBUG_LOGGING_LEVEL 100 -#define APP_RESULT_SUCCESS 0 -#define APP_RESULT_INVALID_PARAMS 1 +#define APP_RESULT_SUCCESS 0 +#define APP_RESULT_INVALID_PARAMS 1 +#define APP_RESULT_STLINK_NOT_FOUND 2 struct _st_settings_t @@ -30,15 +31,15 @@ typedef struct _st_settings_t st_settings_t; static void usage(void) { - puts("st-trace - usage:"); - puts(" -h, --help Print this help"); - puts(" -V, --version Print this version"); - puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); - puts(" -v, --verbose Specify a generally verbose logging"); - puts(" -cXX, --clock=XX Specify the core frequency in MHz"); - puts(" -n, --no-reset Do not reset board on connection"); - puts(" -sXX, --serial=XX Use a specific serial number"); - puts(" -a, --no-sync Do not wait for a sync packet"); + puts("st-trace - usage:"); + puts(" -h, --help Print this help"); + puts(" -V, --version Print this version"); + puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); + puts(" -v, --verbose Specify a generally verbose logging"); + puts(" -cXX, --clock=XX Specify the core frequency in MHz"); + puts(" -n, --no-reset Do not reset board on connection"); + puts(" -sXX, --serial=XX Use a specific serial number"); + puts(" -a, --no-sync Do not wait for a sync packet"); } bool parse_options(int argc, char** argv, st_settings_t *settings) { @@ -110,6 +111,33 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return true; } +static bool FindStLink(const st_settings_t* settings, stlink_t* link) { + stlink_t **stdevs; + size_t size; + bool result = false; + + size = stlink_probe_usb(&stdevs); + if (settings->logging_level >= UDEBUG) { + printf("Found %u stlink programmers\n", (unsigned int)size); + } + + if (!settings->serial_number && size > 0) { + *link = *stdevs[0]; + result = true; + } else { + for (size_t n = 0; n < size; n++) { + if (strncmp(stdevs[n]->serial, settings->serial_number, stdevs[n]->serial_size) == 0) { + *link = *stdevs[n]; + result = true; + } + } + } + + stlink_probe_usb_free(&stdevs, size); + + return result; +} + int main(int argc, char** argv) { st_settings_t settings; @@ -119,14 +147,15 @@ int main(int argc, char** argv) return APP_RESULT_INVALID_PARAMS; } - /* if (settings.logging_level >= UDEBUG) */ - printf("show_help = %s\n", settings.show_help ? "true" : "false"); - printf("show_version = %s\n", settings.show_version ? "true" : "false"); - printf("logging_level = %d\n", settings.logging_level); - printf("core_frequency = %d MHz\n", settings.core_frequency_mhz); - printf("reset_board = %s\n", settings.reset_board ? "true" : "false"); - printf("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); - printf("wait_sync = %s\n", settings.wait_sync ? "true" : "false"); + if (settings.logging_level >= UDEBUG) { + printf("show_help = %s\n", settings.show_help ? "true" : "false"); + printf("show_version = %s\n", settings.show_version ? "true" : "false"); + printf("logging_level = %d\n", settings.logging_level); + printf("core_frequency = %d MHz\n", settings.core_frequency_mhz); + printf("reset_board = %s\n", settings.reset_board ? "true" : "false"); + printf("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); + printf("wait_sync = %s\n", settings.wait_sync ? "true" : "false"); + } if (settings.show_help) { usage(); @@ -137,6 +166,19 @@ int main(int argc, char** argv) printf("v%s\n", STLINK_VERSION); return APP_RESULT_SUCCESS; } + + stlink_t link; + if (!FindStLink(&settings, &link)) { + if (settings.serial_number) { + printf("ERROR: Unable to locate st-link '%s'\n", settings.serial_number); + } else { + printf("ERROR: Unable to locate st-link\n"); + } + return APP_RESULT_STLINK_NOT_FOUND; + } + + + return APP_RESULT_SUCCESS; } From 5ad3bb9846c58086c9758aa5e1816b551473c422 Mon Sep 17 00:00:00 2001 From: John Hall Date: Wed, 25 Nov 2020 16:15:51 -0800 Subject: [PATCH 1042/1435] Separating out method to check if stlink is usable. Adding a log macro. Adding logs with stlink list. --- src/st-trace/trace.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 03f1ac43d..2fec00c8d 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -16,6 +16,8 @@ #define APP_RESULT_INVALID_PARAMS 1 #define APP_RESULT_STLINK_NOT_FOUND 2 +#define LOG(SETTINGS, LEVEL, ARGS...) if (settings->logging_level >= LEVEL) printf(ARGS) + struct _st_settings_t { @@ -111,25 +113,34 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return true; } +static bool CompareStlink(const st_settings_t* settings, const stlink_t* link) { + if (!settings->serial_number) { + return true; + } + + if (strncmp(link->serial, settings->serial_number, link->serial_size) == 0) { + return true; + } + + return false; +} + static bool FindStLink(const st_settings_t* settings, stlink_t* link) { stlink_t **stdevs; size_t size; bool result = false; size = stlink_probe_usb(&stdevs); - if (settings->logging_level >= UDEBUG) { - printf("Found %u stlink programmers\n", (unsigned int)size); - } + LOG(settings, UDEBUG, "Found %u stlink programmers\n", (unsigned int)size); - if (!settings->serial_number && size > 0) { - *link = *stdevs[0]; - result = true; - } else { - for (size_t n = 0; n < size; n++) { - if (strncmp(stdevs[n]->serial, settings->serial_number, stdevs[n]->serial_size) == 0) { - *link = *stdevs[n]; - result = true; + for (size_t n = 0; n < size; n++) { + if (CompareStlink(settings, stdevs[n])) { + LOG(settings, UDEBUG, "Matching stlink '%*s'\n", stdevs[n]->serial_size, stdevs[n]->serial); + if (result) { + LOG(settings, UWARN, "WARNING: Multiple matching stlinks\n"); } + *link = *stdevs[n]; + result = true; } } From 4aed3205a8d014091662925329dcd4b46db0be6d Mon Sep 17 00:00:00 2001 From: John Hall Date: Thu, 26 Nov 2020 05:52:37 +0000 Subject: [PATCH 1043/1435] Fixed that serial numbers are stored as binary values. --- src/st-trace/trace.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 2fec00c8d..19ea1def2 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -113,12 +113,26 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return true; } +static const char* GetSerialString(const stlink_t* link) { + const char kHexChars[16] = "0123456789abcdef"; + static char serial[2 * sizeof(link->serial) + 1]; + + size_t cursor = 0; + for (size_t n = 0; n < link->serial_size; n++) { + serial[cursor++] = kHexChars[(link->serial[n] >> 4) & 0x0f]; + serial[cursor++] = kHexChars[(link->serial[n] >> 0) & 0x0f]; + } + serial[cursor++] = 0; + + return serial; +} + static bool CompareStlink(const st_settings_t* settings, const stlink_t* link) { if (!settings->serial_number) { return true; } - if (strncmp(link->serial, settings->serial_number, link->serial_size) == 0) { + if (strncmp(GetSerialString(link), settings->serial_number, strlen(settings->serial_number)) == 0) { return true; } @@ -131,16 +145,17 @@ static bool FindStLink(const st_settings_t* settings, stlink_t* link) { bool result = false; size = stlink_probe_usb(&stdevs); - LOG(settings, UDEBUG, "Found %u stlink programmers\n", (unsigned int)size); + LOG(settings, UDEBUG, "Found %u stlink programmer(s)\n", (unsigned int)size); for (size_t n = 0; n < size; n++) { if (CompareStlink(settings, stdevs[n])) { - LOG(settings, UDEBUG, "Matching stlink '%*s'\n", stdevs[n]->serial_size, stdevs[n]->serial); + LOG(settings, UDEBUG, "Matching stlink '%s'\n", GetSerialString(stdevs[n])); if (result) { - LOG(settings, UWARN, "WARNING: Multiple matching stlinks\n"); + LOG(settings, UWARN, "WARNING: Multiple matching stlink programmers. Using '%s'\n", GetSerialString(link)); + } else { + *link = *stdevs[n]; + result = true; } - *link = *stdevs[n]; - result = true; } } From f5cc12ce331ec2ecd41b8838f279332bf1ebcc96 Mon Sep 17 00:00:00 2001 From: John Hall Date: Thu, 26 Nov 2020 05:59:27 +0000 Subject: [PATCH 1044/1435] Cleaning up logging a bit. --- src/st-trace/trace.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 19ea1def2..8f02a06f1 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -16,7 +16,7 @@ #define APP_RESULT_INVALID_PARAMS 1 #define APP_RESULT_STLINK_NOT_FOUND 2 -#define LOG(SETTINGS, LEVEL, ARGS...) if (settings->logging_level >= LEVEL) printf(ARGS) +#define LOG(SETTINGS, LEVEL, ARGS...) if ((SETTINGS)->logging_level >= (LEVEL)) printf(ARGS) struct _st_settings_t @@ -98,14 +98,14 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return false; break; default: - printf("ERROR: Unknown command line option: '%c' (0x%02x)\n", c, c); + LOG(settings, UERROR, "ERROR: Unknown command line option: '%c' (0x%02x)\n", c, c); return false; } } if (optind < argc) { while (optind < argc) { - printf("ERROR: Unknown command line argument: '%s'\n", argv[optind++]); + LOG(settings, UERROR, "ERROR: Unknown command line argument: '%s'\n", argv[optind++]); } return false; } @@ -173,15 +173,13 @@ int main(int argc, char** argv) return APP_RESULT_INVALID_PARAMS; } - if (settings.logging_level >= UDEBUG) { - printf("show_help = %s\n", settings.show_help ? "true" : "false"); - printf("show_version = %s\n", settings.show_version ? "true" : "false"); - printf("logging_level = %d\n", settings.logging_level); - printf("core_frequency = %d MHz\n", settings.core_frequency_mhz); - printf("reset_board = %s\n", settings.reset_board ? "true" : "false"); - printf("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); - printf("wait_sync = %s\n", settings.wait_sync ? "true" : "false"); - } + LOG(&settings, UDEBUG, "show_help = %s\n", settings.show_help ? "true" : "false"); + LOG(&settings, UDEBUG, "show_version = %s\n", settings.show_version ? "true" : "false"); + LOG(&settings, UDEBUG, "logging_level = %d\n", settings.logging_level); + LOG(&settings, UDEBUG, "core_frequency = %d MHz\n", settings.core_frequency_mhz); + LOG(&settings, UDEBUG, "reset_board = %s\n", settings.reset_board ? "true" : "false"); + LOG(&settings, UDEBUG, "serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); + LOG(&settings, UDEBUG, "wait_sync = %s\n", settings.wait_sync ? "true" : "false"); if (settings.show_help) { usage(); @@ -195,11 +193,7 @@ int main(int argc, char** argv) stlink_t link; if (!FindStLink(&settings, &link)) { - if (settings.serial_number) { - printf("ERROR: Unable to locate st-link '%s'\n", settings.serial_number); - } else { - printf("ERROR: Unable to locate st-link\n"); - } + LOG(&settings, UERROR, "ERROR: Unable to locate st-link\n"); return APP_RESULT_STLINK_NOT_FOUND; } From be8d86f6333da1dba6b94e2f22bc9788965177de Mon Sep 17 00:00:00 2001 From: John Hall Date: Thu, 26 Nov 2020 06:46:42 +0000 Subject: [PATCH 1045/1435] Fixing to use built in logging. --- src/st-trace/trace.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 8f02a06f1..0f651b0d8 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -16,8 +16,6 @@ #define APP_RESULT_INVALID_PARAMS 1 #define APP_RESULT_STLINK_NOT_FOUND 2 -#define LOG(SETTINGS, LEVEL, ARGS...) if ((SETTINGS)->logging_level >= (LEVEL)) printf(ARGS) - struct _st_settings_t { @@ -66,6 +64,7 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { settings->reset_board = true; settings->serial_number = NULL; settings->wait_sync = true; + ugly_init(settings->logging_level); while ((c = getopt_long(argc, argv, "hVv::c:ns:a", long_options, &option_index)) != -1) { switch (c) { @@ -81,6 +80,7 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { } else { settings->logging_level = DEBUG_LOGGING_LEVEL; } + ugly_init(settings->logging_level); break; case 'c': settings->core_frequency_mhz = atoi(optarg); @@ -98,14 +98,14 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return false; break; default: - LOG(settings, UERROR, "ERROR: Unknown command line option: '%c' (0x%02x)\n", c, c); + ELOG("Unknown command line option: '%c' (0x%02x)\n", c, c); return false; } } if (optind < argc) { while (optind < argc) { - LOG(settings, UERROR, "ERROR: Unknown command line argument: '%s'\n", argv[optind++]); + ELOG("Unknown command line argument: '%s'\n", argv[optind++]); } return false; } @@ -145,13 +145,13 @@ static bool FindStLink(const st_settings_t* settings, stlink_t* link) { bool result = false; size = stlink_probe_usb(&stdevs); - LOG(settings, UDEBUG, "Found %u stlink programmer(s)\n", (unsigned int)size); + DLOG("Found %u stlink programmer(s)\n", (unsigned int)size); for (size_t n = 0; n < size; n++) { if (CompareStlink(settings, stdevs[n])) { - LOG(settings, UDEBUG, "Matching stlink '%s'\n", GetSerialString(stdevs[n])); + DLOG("Matching stlink '%s'\n", GetSerialString(stdevs[n])); if (result) { - LOG(settings, UWARN, "WARNING: Multiple matching stlink programmers. Using '%s'\n", GetSerialString(link)); + WLOG("Multiple matching stlink programmers. Using '%s'\n", GetSerialString(link)); } else { *link = *stdevs[n]; result = true; @@ -173,13 +173,13 @@ int main(int argc, char** argv) return APP_RESULT_INVALID_PARAMS; } - LOG(&settings, UDEBUG, "show_help = %s\n", settings.show_help ? "true" : "false"); - LOG(&settings, UDEBUG, "show_version = %s\n", settings.show_version ? "true" : "false"); - LOG(&settings, UDEBUG, "logging_level = %d\n", settings.logging_level); - LOG(&settings, UDEBUG, "core_frequency = %d MHz\n", settings.core_frequency_mhz); - LOG(&settings, UDEBUG, "reset_board = %s\n", settings.reset_board ? "true" : "false"); - LOG(&settings, UDEBUG, "serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); - LOG(&settings, UDEBUG, "wait_sync = %s\n", settings.wait_sync ? "true" : "false"); + DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); + DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); + DLOG("logging_level = %d\n", settings.logging_level); + DLOG("core_frequency = %d MHz\n", settings.core_frequency_mhz); + DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); + DLOG("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); + DLOG("wait_sync = %s\n", settings.wait_sync ? "true" : "false"); if (settings.show_help) { usage(); @@ -193,7 +193,7 @@ int main(int argc, char** argv) stlink_t link; if (!FindStLink(&settings, &link)) { - LOG(&settings, UERROR, "ERROR: Unable to locate st-link\n"); + ELOG("Unable to locate st-link\n"); return APP_RESULT_STLINK_NOT_FOUND; } From 2fd0ab86144c894979fd3271f898902696fd80e4 Mon Sep 17 00:00:00 2001 From: John Hall Date: Thu, 26 Nov 2020 16:28:43 +0000 Subject: [PATCH 1046/1435] Library already supported specifying which stlink to use. --- src/st-trace/trace.c | 68 ++++++++++---------------------------------- 1 file changed, 15 insertions(+), 53 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 0f651b0d8..0427d5760 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -113,60 +113,25 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return true; } -static const char* GetSerialString(const stlink_t* link) { - const char kHexChars[16] = "0123456789abcdef"; - static char serial[2 * sizeof(link->serial) + 1]; - - size_t cursor = 0; - for (size_t n = 0; n < link->serial_size; n++) { - serial[cursor++] = kHexChars[(link->serial[n] >> 4) & 0x0f]; - serial[cursor++] = kHexChars[(link->serial[n] >> 0) & 0x0f]; - } - serial[cursor++] = 0; - - return serial; -} - -static bool CompareStlink(const st_settings_t* settings, const stlink_t* link) { - if (!settings->serial_number) { - return true; - } - - if (strncmp(GetSerialString(link), settings->serial_number, strlen(settings->serial_number)) == 0) { - return true; - } - - return false; -} - -static bool FindStLink(const st_settings_t* settings, stlink_t* link) { - stlink_t **stdevs; - size_t size; - bool result = false; - - size = stlink_probe_usb(&stdevs); - DLOG("Found %u stlink programmer(s)\n", (unsigned int)size); - - for (size_t n = 0; n < size; n++) { - if (CompareStlink(settings, stdevs[n])) { - DLOG("Matching stlink '%s'\n", GetSerialString(stdevs[n])); - if (result) { - WLOG("Multiple matching stlink programmers. Using '%s'\n", GetSerialString(link)); - } else { - *link = *stdevs[n]; - result = true; - } +static stlink_t* StLinkConnect(const st_settings_t* settings) { + if (settings->serial_number) { + char serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; + size_t length = 0; + for (uint32_t n = 0; n < strlen(settings->serial_number) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { + char buffer[3] = { 0 }; + memcpy(buffer, settings->serial_number + n, 2); + serial_number[length++] = (uint8_t)strtol(buffer, NULL, 16); } + return stlink_open_usb(settings->logging_level, false, serial_number, 0); + } else { + return stlink_open_usb(settings->logging_level, false, NULL, 0); } - - stlink_probe_usb_free(&stdevs, size); - - return result; } int main(int argc, char** argv) { st_settings_t settings; + stlink_t* link = NULL; if (!parse_options(argc, argv, &settings)) { usage(); @@ -191,15 +156,12 @@ int main(int argc, char** argv) return APP_RESULT_SUCCESS; } - stlink_t link; - if (!FindStLink(&settings, &link)) { + link = StLinkConnect(&settings); + if (!link) { ELOG("Unable to locate st-link\n"); return APP_RESULT_STLINK_NOT_FOUND; } - - - - + return APP_RESULT_SUCCESS; } From 380444a6fd8f4394374cb433f0e1b21f9807bebd Mon Sep 17 00:00:00 2001 From: John Hall Date: Fri, 27 Nov 2020 16:16:16 +0000 Subject: [PATCH 1047/1435] In progress. Added defines for trace debug commands. Added initial start trace method. --- src/st-trace/trace.c | 158 ++++++++++++++++++++++++++++++++++++-- src/stlink-lib/commands.h | 3 + 2 files changed, 154 insertions(+), 7 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 0427d5760..2f9bcc2ff 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -12,9 +12,12 @@ #define DEFAULT_LOGGING_LEVEL 50 #define DEBUG_LOGGING_LEVEL 100 -#define APP_RESULT_SUCCESS 0 -#define APP_RESULT_INVALID_PARAMS 1 -#define APP_RESULT_STLINK_NOT_FOUND 2 +#define APP_RESULT_SUCCESS 0 +#define APP_RESULT_INVALID_PARAMS 1 +#define APP_RESULT_STLINK_NOT_FOUND 2 +#define APP_RESULT_STLINK_MISSING_DEVICE 3 +#define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 +#define APP_RESULT_STLINK_STATE_ERROR 5 struct _st_settings_t @@ -128,10 +131,122 @@ static stlink_t* StLinkConnect(const st_settings_t* settings) { } } +// TODO: Move this to device table. +static bool IsDeviceTraceSupported(int chip_id) { + switch (chip_id) { + case STLINK_CHIPID_STM32_F4: + case STLINK_CHIPID_STM32_F4_DSI: + case STLINK_CHIPID_STM32_F4_HD: + case STLINK_CHIPID_STM32_F4_LP: + case STLINK_CHIPID_STM32_F411RE: + case STLINK_CHIPID_STM32_F4_DE: + case STLINK_CHIPID_STM32_F446: + case STLINK_CHIPID_STM32_F410: + case STLINK_CHIPID_STM32_F3: + case STLINK_CHIPID_STM32_F37x: + case STLINK_CHIPID_STM32_F412: + case STLINK_CHIPID_STM32_F413: + case STLINK_CHIPID_STM32_F3_SMALL: + case STLINK_CHIPID_STM32_F334: + case STLINK_CHIPID_STM32_F303_HIGH: + return true; + default: + return false; + } +} + +static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_board) { + struct stlink_read_reg regp = {}; + + if (stlink_force_debug(stlink)) { + return false; + } + + if (reset_board && stlink_reset(stlink)) { + return false; + } + + // The remainder of the items in this function were taken directly from https://github.com/avrhack/stlink-trace/blob/master/stlink-trace.c#L386 + + // Set DHCSR to C_HALT and C_DEBUGEN + stlink_write_debug32(stlink, 0xE000EDF0, 0xA05F0003); + + // Set TRCENA flag to enable global DWT and ITM + stlink_write_debug32(stlink, 0xE000EDFC, 0x01000000); + + // Set FP_CTRL to enable write + stlink_write_debug32(stlink, 0xE0002000, 0x00000002); + + // Set DWT_FUNCTION0 to DWT_FUNCTION3 to disable sampling + stlink_write_debug32(stlink, 0xE0001028, 0x00000000); + stlink_write_debug32(stlink, 0xE0001038, 0x00000000); + stlink_write_debug32(stlink, 0xE0001048, 0x00000000); + stlink_write_debug32(stlink, 0xE0001058, 0x00000000); + + // Clear DWT_CTRL and other registers + stlink_write_debug32(stlink, 0xE0001000, 0x00000000); + stlink_write_debug32(stlink, 0xE0001004, 0x00000000); + stlink_write_debug32(stlink, 0xE0001008, 0x00000000); + stlink_write_debug32(stlink, 0xE000100C, 0x00000000); + stlink_write_debug32(stlink, 0xE0001010, 0x00000000); + stlink_write_debug32(stlink, 0xE0001014, 0x00000000); + stlink_write_debug32(stlink, 0xE0001018, 0x00000000); + + // We should be checking these regisers. + stlink_read_reg(stlink, 15, ®p); // Read program counter + stlink_read_reg(stlink, 16, ®p); // Read xpsr register + + // Set DBGMCU_CR to enable asynchronous transmission + stlink_write_debug32(stlink, 0xE0042004, 0x00000027); + + + // STLINK_DEBUG_APIV2_START_TRACE_RX + // ???? + unsigned char txBuffer3[] = {STLINK_DEBUG_COMMAND, 0x40, 0x00, 0x10, 0x80, 0x84, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + unsigned char rxBuffer3[100]; + SendAndReceive(&txBuffer3[0], 16, &rxBuffer3[0], 64); + + + + // Set TPIU_CSPSR to enable trace port width of 2 + stlink_write_debug32(stlink, 0xE0040004, 0x00000001); + + if (core_frequency_mhz) + // Set TPIU_ACPR clock divisor + stlink_write_debug32(stlink, 0xE0040010, core_frequency_mhz / 2 - 1); + + // Set TPIU_SPPR to Asynchronous SWO (NRZ) + stlink_write_debug32(stlink, 0xE00400F0, 0x00000002); + + // Set TPIU_FFCR continuous formatting) + stlink_write_debug32(stlink, 0xE0040304, 0x00000100); + + // Unlock the ITM registers for write + stlink_write_debug32(stlink, 0xE0000FB0, 0xC5ACCE55); + + // Set sync counter + stlink_write_debug32(stlink, 0xE0000E90, 0x00000400); + + // Set ITM_TCR flags : ITMENA,TSENA ATB=0 + stlink_write_debug32(stlink, 0xE0000E80, 0x00010003); + + // Enable all trace ports in ITM_TER + stlink_write_debug32(stlink, 0xE0000E00, 0xFFFFFFFF); + + // Enable unprivileged access to trace ports 31:0 in ITM_TPR + stlink_write_debug32(stlink, 0xE0000E40, 0x0000000F); + + // Set DWT_CTRL flags) + stlink_write_debug32(stlink, 0xE0000E40, 0x400003FE); // Keil one + + // Enable tracing (DEMCR - TRCENA bit) + stlink_write_debug32(stlink, 0xE000EDFC, 0x01000000); +} + int main(int argc, char** argv) { st_settings_t settings; - stlink_t* link = NULL; + stlink_t* stlink = NULL; if (!parse_options(argc, argv, &settings)) { usage(); @@ -156,12 +271,41 @@ int main(int argc, char** argv) return APP_RESULT_SUCCESS; } - link = StLinkConnect(&settings); - if (!link) { + stlink = StLinkConnect(&settings); + if (!stlink) { ELOG("Unable to locate st-link\n"); return APP_RESULT_STLINK_NOT_FOUND; } - + + if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { + ELOG("st-link not connected\n"); + return APP_RESULT_STLINK_MISSING_DEVICE; + } + + // TODO: Check if trace is supported by stlink. + + if (!IsDeviceTraceSupported(stlink->chip_id)) { + const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); + ELOG("We do not support SWO output for device '%s'", params->description); + return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; + } + + if (!EnableTrace(stlink, settings.core_frequency_mhz, settings.reset_board)) { + ELOG("Unable to enable trace mode\n"); + return APP_RESULT_STLINK_STATE_ERROR; + } + + if (stlink_run(stlink)) { + ELOG("Unable to run device\n"); + return APP_RESULT_STLINK_STATE_ERROR; + } + + + // Read SWO output + + + stlink_close(stlink); + return APP_RESULT_SUCCESS; } diff --git a/src/stlink-lib/commands.h b/src/stlink-lib/commands.h index 0925e8e67..dac82b8e6 100644 --- a/src/stlink-lib/commands.h +++ b/src/stlink-lib/commands.h @@ -30,6 +30,9 @@ enum stlink_debug_commands { STLINK_DEBUG_APIV2_READALLREGS = 0x3A, STLINK_DEBUG_APIV2_GETLASTRWSTATUS = 0x3B, STLINK_DEBUG_APIV2_GETLASTRWSTATUS2 = 0x3E, + STLINK_DEBUG_APIV2_START_TRACE_RX = 0x40, + STLINK_DEBUG_APIV2_STOP_TRACE_RX = 0x41, + STLINK_DEBUG_APIV2_GET_TRACE_NB = 0x42, STLINK_DEBUG_ENTER_SWD = 0xa3 }; From 568b0d130a5f61e511b1063bcea68f2e0ad18c1c Mon Sep 17 00:00:00 2001 From: John Hall Date: Fri, 27 Nov 2020 09:37:50 -0800 Subject: [PATCH 1048/1435] Adding backend code to start/stop tracing and to read the incoming data. --- inc/backend.h | 4 +++ inc/stlink.h | 7 ++++ src/common.c | 16 +++++++++ src/st-trace/trace.c | 14 +++----- src/stlink-lib/sg.c | 5 ++- src/stlink-lib/usb.c | 83 +++++++++++++++++++++++++++++++++++++++++++- src/stlink-lib/usb.h | 1 + 7 files changed, 119 insertions(+), 11 deletions(-) diff --git a/inc/backend.h b/inc/backend.h index f852da05d..470702fde 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -29,6 +29,10 @@ int (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); int (*set_swdclk) (stlink_t * stl, uint16_t divisor); + int (*trace_enable) (stlink_t * sl); + int (*trace_disable) (stlink_t * sl); + int (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); + } stlink_backend_t; #endif // STLINK_BACKEND_H_ diff --git a/inc/stlink.h b/inc/stlink.h index 39f5f283c..e7aefbded 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -83,6 +83,9 @@ enum target_state { #define STLINK_V3_MAX_FREQ_NB 10 +#define STLINK_TRACE_BUF_LEN 4096 +#define STLINK_TRACE_FREQUENCY 2000000 + /* Cortex Debug Control Block */ #define DCB_DHCSR 0xE000EDF0 #define DCB_DCRSR 0xE000EDF4 @@ -261,6 +264,9 @@ int stlink_current_mode(stlink_t *sl); int stlink_force_debug(stlink_t *sl); int stlink_target_voltage(stlink_t *sl); int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); +int stlink_trace_enable(stlink_t* sl); +int stlink_trace_disable(stlink_t* sl); +int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); int stlink_erase_flash_mass(stlink_t* sl); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); @@ -303,6 +309,7 @@ int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_contr int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); + #include #include #include diff --git a/src/common.c b/src/common.c index 32c00ad3b..e340ecc71 100644 --- a/src/common.c +++ b/src/common.c @@ -1677,6 +1677,21 @@ int stlink_current_mode(stlink_t *sl) { return(STLINK_DEV_UNKNOWN_MODE); } +int stlink_trace_enable(stlink_t* sl) { + DLOG("*** stlink_trace_enable ***\n"); + return(sl->backend->trace_enable(sl)); +} + +int stlink_trace_disable(stlink_t* sl) { + DLOG("*** stlink_trace_disable ***\n"); + return(sl->backend->trace_disable(sl)); +} + +int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size) { + DLOG("*** stlink_trace_read ***\n"); + return(sl->backend->trace_read(sl, buf, size)); +} + // End of delegates.... Common code below here... @@ -4070,3 +4085,4 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr return(err); } + diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 2f9bcc2ff..0bbec903e 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -156,7 +156,6 @@ static bool IsDeviceTraceSupported(int chip_id) { } static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_board) { - struct stlink_read_reg regp = {}; if (stlink_force_debug(stlink)) { return false; @@ -193,20 +192,15 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa stlink_write_debug32(stlink, 0xE0001018, 0x00000000); // We should be checking these regisers. + struct stlink_reg regp = {}; stlink_read_reg(stlink, 15, ®p); // Read program counter stlink_read_reg(stlink, 16, ®p); // Read xpsr register // Set DBGMCU_CR to enable asynchronous transmission stlink_write_debug32(stlink, 0xE0042004, 0x00000027); - - // STLINK_DEBUG_APIV2_START_TRACE_RX - // ???? - unsigned char txBuffer3[] = {STLINK_DEBUG_COMMAND, 0x40, 0x00, 0x10, 0x80, 0x84, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; - unsigned char rxBuffer3[100]; - SendAndReceive(&txBuffer3[0], 16, &rxBuffer3[0], 64); - - + // Actually start tracing. + stlink_trace_enable(stlink); // Set TPIU_CSPSR to enable trace port width of 2 stlink_write_debug32(stlink, 0xE0040004, 0x00000001); @@ -241,6 +235,8 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa // Enable tracing (DEMCR - TRCENA bit) stlink_write_debug32(stlink, 0xE000EDFC, 0x01000000); + + return true; } int main(int argc, char** argv) diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 5cc27b1fe..f66864c44 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -944,7 +944,10 @@ static stlink_backend_t _stlink_sg_backend = { _stlink_sg_current_mode, _stlink_sg_force_debug, NULL, // target_voltage - NULL // set_swdclk + NULL, // set_swdclk + NULL, // trace_enable + NULL, // trace_disable + NULL, // trace_read }; static stlink_t* stlink_open(const int verbose) { diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 9726ddc4a..a7ebab0f3 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -972,6 +972,82 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { return(0); } +int _stlink_usb_enable_trace(stlink_t* sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + + int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; + write_uint16(&cmd[i + 0], STLINK_TRACE_BUF_LEN); + write_uint32(&cmd[i + 2], STLINK_TRACE_FREQUENCY); + + size = send_only(slu, 1, cmd, slu->cmd_len); + + if (size == -1) { + printf("[!] send_only STLINK_DEBUG_APIV2_START_TRACE_RX\n"); + return((int)size); + } + + return(0); +} + +int _stlink_usb_disable_trace(stlink_t* sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + + int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; + + size = send_only(slu, 1, cmd, slu->cmd_len); + + if (size == -1) { + printf("[!] send_only STLINK_DEBUG_APIV2_STOP_TRACE_RX\n"); + return((int)size); + } + + return(0); +} + +int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + uint32_t rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_GET_TRACE_NB; + ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + + if (send_size == -1) { + printf("[!] send_recv STLINK_DEBUG_APIV2_GET_TRACE_NB\n"); + return((int)send_size); + } + + stlink_print_data(sl); + size_t trace_count = read_uint16(sl->q_buf, 0); + DLOG("trace_count = 0x%08x\n", trace_count); + + if (trace_count > size) { + ELOG("read_trace insufficient buffer length\n"); + return -1; + } + + int res = 0; + int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); + + if (t) { + ELOG("read_trace read error\n"); + return(-1); + } + + return trace_count; +} + static stlink_backend_t _stlink_usb_backend = { _stlink_usb_close, _stlink_usb_exit_debug_mode, @@ -999,7 +1075,10 @@ static stlink_backend_t _stlink_usb_backend = { _stlink_usb_current_mode, _stlink_usb_force_debug, _stlink_usb_target_voltage, - _stlink_usb_set_swdclk + _stlink_usb_set_swdclk, + _stlink_usb_enable_trace, + _stlink_usb_disable_trace, + _stlink_usb_read_trace }; stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq) { @@ -1161,8 +1240,10 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID || desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID) { slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; + slu->ep_trace = 2 | LIBUSB_ENDPOINT_IN; } else { slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; + slu->ep_trace = 3 | LIBUSB_ENDPOINT_IN; } slu->sg_transfer_idx = 0; diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index d11f17381..717a82f6d 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -53,6 +53,7 @@ struct stlink_libusb { libusb_device_handle* usb_handle; unsigned int ep_req; unsigned int ep_rep; + unsigned int ep_trace; int protocoll; unsigned int sg_transfer_idx; unsigned int cmd_len; From 2900571f95cfaf7880b9bba0008e56fb07bea09a Mon Sep 17 00:00:00 2001 From: John Hall Date: Sat, 28 Nov 2020 17:02:49 +0000 Subject: [PATCH 1049/1435] In progress. --- src/st-trace/trace.c | 57 ++++++++++++++++++++++++-------------------- src/stlink-lib/usb.c | 4 ++-- 2 files changed, 33 insertions(+), 28 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 0bbec903e..2918fd61e 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -155,6 +155,11 @@ static bool IsDeviceTraceSupported(int chip_id) { } } +static void Write32(stlink_t* stlink, uint32_t address, uint32_t data) { + write_uint32(stlink->q_buf, data); + stlink_write_mem32(stlink, address, 4); +} + static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_board) { if (stlink_force_debug(stlink)) { @@ -168,28 +173,28 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa // The remainder of the items in this function were taken directly from https://github.com/avrhack/stlink-trace/blob/master/stlink-trace.c#L386 // Set DHCSR to C_HALT and C_DEBUGEN - stlink_write_debug32(stlink, 0xE000EDF0, 0xA05F0003); + Write32(stlink, 0xE000EDF0, 0xA05F0003); // Set TRCENA flag to enable global DWT and ITM - stlink_write_debug32(stlink, 0xE000EDFC, 0x01000000); + Write32(stlink, 0xE000EDFC, 0x01000000); // Set FP_CTRL to enable write - stlink_write_debug32(stlink, 0xE0002000, 0x00000002); + Write32(stlink, 0xE0002000, 0x00000002); // Set DWT_FUNCTION0 to DWT_FUNCTION3 to disable sampling - stlink_write_debug32(stlink, 0xE0001028, 0x00000000); - stlink_write_debug32(stlink, 0xE0001038, 0x00000000); - stlink_write_debug32(stlink, 0xE0001048, 0x00000000); - stlink_write_debug32(stlink, 0xE0001058, 0x00000000); + Write32(stlink, 0xE0001028, 0x00000000); + Write32(stlink, 0xE0001038, 0x00000000); + Write32(stlink, 0xE0001048, 0x00000000); + Write32(stlink, 0xE0001058, 0x00000000); // Clear DWT_CTRL and other registers - stlink_write_debug32(stlink, 0xE0001000, 0x00000000); - stlink_write_debug32(stlink, 0xE0001004, 0x00000000); - stlink_write_debug32(stlink, 0xE0001008, 0x00000000); - stlink_write_debug32(stlink, 0xE000100C, 0x00000000); - stlink_write_debug32(stlink, 0xE0001010, 0x00000000); - stlink_write_debug32(stlink, 0xE0001014, 0x00000000); - stlink_write_debug32(stlink, 0xE0001018, 0x00000000); + Write32(stlink, 0xE0001000, 0x00000000); + Write32(stlink, 0xE0001004, 0x00000000); + Write32(stlink, 0xE0001008, 0x00000000); + Write32(stlink, 0xE000100C, 0x00000000); + Write32(stlink, 0xE0001010, 0x00000000); + Write32(stlink, 0xE0001014, 0x00000000); + Write32(stlink, 0xE0001018, 0x00000000); // We should be checking these regisers. struct stlink_reg regp = {}; @@ -197,44 +202,44 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa stlink_read_reg(stlink, 16, ®p); // Read xpsr register // Set DBGMCU_CR to enable asynchronous transmission - stlink_write_debug32(stlink, 0xE0042004, 0x00000027); + Write32(stlink, 0xE0042004, 0x00000027); // Actually start tracing. stlink_trace_enable(stlink); // Set TPIU_CSPSR to enable trace port width of 2 - stlink_write_debug32(stlink, 0xE0040004, 0x00000001); + Write32(stlink, 0xE0040004, 0x00000001); if (core_frequency_mhz) // Set TPIU_ACPR clock divisor - stlink_write_debug32(stlink, 0xE0040010, core_frequency_mhz / 2 - 1); + Write32(stlink, 0xE0040010, core_frequency_mhz / 2 - 1); // Set TPIU_SPPR to Asynchronous SWO (NRZ) - stlink_write_debug32(stlink, 0xE00400F0, 0x00000002); + Write32(stlink, 0xE00400F0, 0x00000002); // Set TPIU_FFCR continuous formatting) - stlink_write_debug32(stlink, 0xE0040304, 0x00000100); + Write32(stlink, 0xE0040304, 0x00000100); // Unlock the ITM registers for write - stlink_write_debug32(stlink, 0xE0000FB0, 0xC5ACCE55); + Write32(stlink, 0xE0000FB0, 0xC5ACCE55); // Set sync counter - stlink_write_debug32(stlink, 0xE0000E90, 0x00000400); + Write32(stlink, 0xE0000E90, 0x00000400); // Set ITM_TCR flags : ITMENA,TSENA ATB=0 - stlink_write_debug32(stlink, 0xE0000E80, 0x00010003); + Write32(stlink, 0xE0000E80, 0x00010003); // Enable all trace ports in ITM_TER - stlink_write_debug32(stlink, 0xE0000E00, 0xFFFFFFFF); + Write32(stlink, 0xE0000E00, 0xFFFFFFFF); // Enable unprivileged access to trace ports 31:0 in ITM_TPR - stlink_write_debug32(stlink, 0xE0000E40, 0x0000000F); + Write32(stlink, 0xE0000E40, 0x0000000F); // Set DWT_CTRL flags) - stlink_write_debug32(stlink, 0xE0000E40, 0x400003FE); // Keil one + Write32(stlink, 0xE0000E40, 0x400003FE); // Keil one // Enable tracing (DEMCR - TRCENA bit) - stlink_write_debug32(stlink, 0xE000EDFC, 0x01000000); + Write32(stlink, 0xE000EDFC, 0x01000000); return true; } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index a7ebab0f3..a5d2c3678 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -977,7 +977,7 @@ int _stlink_usb_enable_trace(stlink_t* sl) { unsigned char* const cmd = sl->c_buf; ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + int i = fill_command(sl, SG_DXFER_TO_DEV, 0); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; write_uint16(&cmd[i + 0], STLINK_TRACE_BUF_LEN); @@ -998,7 +998,7 @@ int _stlink_usb_disable_trace(stlink_t* sl) { unsigned char* const cmd = sl->c_buf; ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + int i = fill_command(sl, SG_DXFER_TO_DEV, 0); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; From 737894cbe080da25c20b451298cfaadf8b0fc0fa Mon Sep 17 00:00:00 2001 From: John Hall Date: Sat, 28 Nov 2020 20:58:54 -0800 Subject: [PATCH 1050/1435] Got basic trace data transfer working. Still needs to decode the data stream. --- raspberrypi-build.sh | 20 -------- src/st-trace/trace.c | 114 ++++++++++++++++++++++++++----------------- src/stlink-lib/usb.c | 35 +++++++++---- 3 files changed, 93 insertions(+), 76 deletions(-) delete mode 100755 raspberrypi-build.sh diff --git a/raspberrypi-build.sh b/raspberrypi-build.sh deleted file mode 100755 index 7f77dab45..000000000 --- a/raspberrypi-build.sh +++ /dev/null @@ -1,20 +0,0 @@ -#!/bin/bash - -mkdir -p build/raspberry -mkdir -p build/raspberry/inc -mkdir -p build/raspberry/bin - -cat << EOF > build/raspberry/inc/version.h -#ifndef STLINK_VERSION_H_ -#define STLINK_VERSION_H_ - -#define STLINK_VERSION "1.6.1-116-g27d3-pi-dirty" -#define STLINK_VERSION_MAJOR 1 -#define STLINK_VERSION_MINOR 6 -#define STLINK_VERSION_PATCH 1 - -#endif // STLINK_VERSION_H_ -EOF - -gcc -std=gnu99 -Iinc -Isrc/stlink-lib/ -I/usr/include/libusb-1.0/ -Ibuild/raspberry/inc -DLIBUSB_API_VERSION=MINIMAL_API_VERSION -DSTLINK_HAVE_SYS_MMAN_H src/*.c src/stlink-lib/*.c src/st-trace/*.c -lusb-1.0 -o build/raspberry/bin/st-trace - diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 2918fd61e..9146dd2bc 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -4,6 +4,9 @@ #include #include #include +#include +#include +#include #include #include @@ -20,6 +23,9 @@ #define APP_RESULT_STLINK_STATE_ERROR 5 +static bool g_done = false; + + struct _st_settings_t { bool show_help; @@ -45,6 +51,10 @@ static void usage(void) { puts(" -a, --no-sync Do not wait for a sync packet"); } +static void cleanup() { + g_done = true; +} + bool parse_options(int argc, char** argv, st_settings_t *settings) { static struct option long_options[] = { @@ -161,6 +171,7 @@ static void Write32(stlink_t* stlink, uint32_t address, uint32_t data) { } static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_board) { + struct stlink_reg regp = {}; if (stlink_force_debug(stlink)) { return false; @@ -172,23 +183,14 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa // The remainder of the items in this function were taken directly from https://github.com/avrhack/stlink-trace/blob/master/stlink-trace.c#L386 - // Set DHCSR to C_HALT and C_DEBUGEN - Write32(stlink, 0xE000EDF0, 0xA05F0003); - - // Set TRCENA flag to enable global DWT and ITM - Write32(stlink, 0xE000EDFC, 0x01000000); - - // Set FP_CTRL to enable write - Write32(stlink, 0xE0002000, 0x00000002); - - // Set DWT_FUNCTION0 to DWT_FUNCTION3 to disable sampling - Write32(stlink, 0xE0001028, 0x00000000); + Write32(stlink, 0xE000EDF0, 0xA05F0003); // Set DHCSR to C_HALT and C_DEBUGEN + Write32(stlink, 0xE000EDFC, 0x01000000); // Set TRCENA flag to enable global DWT and ITM + Write32(stlink, 0xE0002000, 0x00000002); // Set FP_CTRL to enable write + Write32(stlink, 0xE0001028, 0x00000000); // Set DWT_FUNCTION0 to DWT_FUNCTION3 to disable sampling Write32(stlink, 0xE0001038, 0x00000000); Write32(stlink, 0xE0001048, 0x00000000); Write32(stlink, 0xE0001058, 0x00000000); - - // Clear DWT_CTRL and other registers - Write32(stlink, 0xE0001000, 0x00000000); + Write32(stlink, 0xE0001000, 0x00000000); // Clear DWT_CTRL and other registers Write32(stlink, 0xE0001004, 0x00000000); Write32(stlink, 0xE0001008, 0x00000000); Write32(stlink, 0xE000100C, 0x00000000); @@ -196,50 +198,60 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa Write32(stlink, 0xE0001014, 0x00000000); Write32(stlink, 0xE0001018, 0x00000000); - // We should be checking these regisers. - struct stlink_reg regp = {}; stlink_read_reg(stlink, 15, ®p); // Read program counter stlink_read_reg(stlink, 16, ®p); // Read xpsr register - // Set DBGMCU_CR to enable asynchronous transmission - Write32(stlink, 0xE0042004, 0x00000027); + Write32(stlink, 0xE0042004, 0x00000027); // Set DBGMCU_CR to enable asynchronous transmission // Actually start tracing. - stlink_trace_enable(stlink); - - // Set TPIU_CSPSR to enable trace port width of 2 - Write32(stlink, 0xE0040004, 0x00000001); + if (stlink_trace_enable(stlink)) { + return false; + } - if (core_frequency_mhz) - // Set TPIU_ACPR clock divisor - Write32(stlink, 0xE0040010, core_frequency_mhz / 2 - 1); + Write32(stlink, 0xE0040004, 0x00000001); // Set TPIU_CSPSR to enable trace port width of 2 - // Set TPIU_SPPR to Asynchronous SWO (NRZ) - Write32(stlink, 0xE00400F0, 0x00000002); + if (core_frequency_mhz) { + uint32_t clock_divisor = core_frequency_mhz / 2 - 1; + Write32(stlink, 0xE0040010, clock_divisor); // Set TPIU_ACPR clock divisor + } - // Set TPIU_FFCR continuous formatting) - Write32(stlink, 0xE0040304, 0x00000100); + Write32(stlink, 0xE00400F0, 0x00000002); // Set TPIU_SPPR to Asynchronous SWO (NRZ) + Write32(stlink, 0xE0040304, 0x00000100); // Set TPIU_FFCR continuous formatting) + Write32(stlink, 0xE0000FB0, 0xC5ACCE55); // Unlock the ITM registers for write + Write32(stlink, 0xE0000E90, 0x00000400); // Set sync counter + Write32(stlink, 0xE0000E80, 0x00010003); // Set ITM_TCR flags : ITMENA,TSENA ATB=0 + Write32(stlink, 0xE0000E00, 0xFFFFFFFF); // Enable all trace ports in ITM_TER + Write32(stlink, 0xE0000E40, 0x0000000F); // Enable unprivileged access to trace ports 31:0 in ITM_TPR + Write32(stlink, 0xE0000E40, 0x400003FE); // Set DWT_CTRL flags) + Write32(stlink, 0xE000EDFC, 0x01000000); // Enable tracing (DEMCR - TRCENA bit) - // Unlock the ITM registers for write - Write32(stlink, 0xE0000FB0, 0xC5ACCE55); + return true; +} - // Set sync counter - Write32(stlink, 0xE0000E90, 0x00000400); +static bool ReadTrace(stlink_t* stlink) { + uint8_t buffer[STLINK_TRACE_BUF_LEN]; + int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); - // Set ITM_TCR flags : ITMENA,TSENA ATB=0 - Write32(stlink, 0xE0000E80, 0x00010003); + if (length < 0) { + ELOG("Error reading trace (%d)\n", length); + return false; + } - // Enable all trace ports in ITM_TER - Write32(stlink, 0xE0000E00, 0xFFFFFFFF); + if (length == 0) { + usleep(1000); + return true; + } - // Enable unprivileged access to trace ports 31:0 in ITM_TPR - Write32(stlink, 0xE0000E40, 0x0000000F); + DLOG("Trace Length: %d\n", length); - // Set DWT_CTRL flags) - Write32(stlink, 0xE0000E40, 0x400003FE); // Keil one + printf("Data: "); + for (int i = 0; i < length; i++) + printf("%02x ", buffer[i]); + printf(" '"); + for (int i = 0; i < length; i++) + printf("%c", isprint(buffer[i]) ? buffer[i] : '?'); + printf("'\n"); - // Enable tracing (DEMCR - TRCENA bit) - Write32(stlink, 0xE000EDFC, 0x01000000); return true; } @@ -249,6 +261,10 @@ int main(int argc, char** argv) st_settings_t settings; stlink_t* stlink = NULL; + signal(SIGINT, &cleanup); + signal(SIGTERM, &cleanup); + signal(SIGSEGV, &cleanup); + if (!parse_options(argc, argv, &settings)) { usage(); return APP_RESULT_INVALID_PARAMS; @@ -278,6 +294,8 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_NOT_FOUND; } + stlink->verbose = settings.logging_level; + if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { ELOG("st-link not connected\n"); return APP_RESULT_STLINK_MISSING_DEVICE; @@ -295,16 +313,20 @@ int main(int argc, char** argv) ELOG("Unable to enable trace mode\n"); return APP_RESULT_STLINK_STATE_ERROR; } - + if (stlink_run(stlink)) { ELOG("Unable to run device\n"); return APP_RESULT_STLINK_STATE_ERROR; } + ILOG("Reading SWO Data\n"); - // Read SWO output - + while (!g_done) { + if (!ReadTrace(stlink)) + g_done = true; + } + stlink_trace_disable(stlink); stlink_close(stlink); return APP_RESULT_SUCCESS; diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index a5d2c3678..4d8d78a65 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -974,41 +974,51 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { int _stlink_usb_enable_trace(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; + uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_TO_DEV, 0); + int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; write_uint16(&cmd[i + 0], STLINK_TRACE_BUF_LEN); write_uint32(&cmd[i + 2], STLINK_TRACE_FREQUENCY); - size = send_only(slu, 1, cmd, slu->cmd_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_only STLINK_DEBUG_APIV2_START_TRACE_RX\n"); return((int)size); } + sl->q_len = (int)size; + stlink_print_data(sl); + return(0); } int _stlink_usb_disable_trace(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; + uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_TO_DEV, 0); + int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; - size = send_only(slu, 1, cmd, slu->cmd_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_only STLINK_DEBUG_APIV2_STOP_TRACE_RX\n"); return((int)size); } + sl->q_len = (int)size; + stlink_print_data(sl); + return(0); } @@ -1027,8 +1037,11 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { printf("[!] send_recv STLINK_DEBUG_APIV2_GET_TRACE_NB\n"); return((int)send_size); } + if (send_size != 2) { + printf("[!] send_recv STLINK_DEBUG_APIV2_GET_TRACE_NB %d\n", (int)send_size); + return -1; + } - stlink_print_data(sl); size_t trace_count = read_uint16(sl->q_buf, 0); DLOG("trace_count = 0x%08x\n", trace_count); @@ -1037,12 +1050,14 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { return -1; } - int res = 0; - int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); + if (trace_count != 0) { + int res = 0; + int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); - if (t) { - ELOG("read_trace read error\n"); - return(-1); + if (t) { + ELOG("read_trace read error\n"); + return(-1); + } } return trace_count; From 9c86d53341e2dd1a8b168d79bc53ccf45008638a Mon Sep 17 00:00:00 2001 From: John Hall Date: Sat, 28 Nov 2020 23:47:29 -0800 Subject: [PATCH 1051/1435] Added a state machine to parse trace output. Improved comments. --- src/st-trace/trace.c | 134 +++++++++++++++++++++++++++++++++---------- 1 file changed, 103 insertions(+), 31 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 9146dd2bc..ccb1a4828 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -15,30 +15,63 @@ #define DEFAULT_LOGGING_LEVEL 50 #define DEBUG_LOGGING_LEVEL 100 -#define APP_RESULT_SUCCESS 0 -#define APP_RESULT_INVALID_PARAMS 1 -#define APP_RESULT_STLINK_NOT_FOUND 2 -#define APP_RESULT_STLINK_MISSING_DEVICE 3 -#define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 -#define APP_RESULT_STLINK_STATE_ERROR 5 - - +#define APP_RESULT_SUCCESS 0 +#define APP_RESULT_INVALID_PARAMS 1 +#define APP_RESULT_STLINK_NOT_FOUND 2 +#define APP_RESULT_STLINK_MISSING_DEVICE 3 +#define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 +#define APP_RESULT_STLINK_STATE_ERROR 5 + +// See https://developer.arm.com/documentation/ddi0403/ed/ +#define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) +#define TRACE_OP_IS_LOCAL_TIME(c) (((c) & 0x0f) == 0x00 && ((c) & 0x70) != 0x00) +#define TRACE_OP_IS_EXTENSION(c) (((c) & 0x0b) == 0x08) +#define TRACE_OP_IS_GLOBAL_TIME(c) (((c) & 0xdf) == 0x94) +#define TRACE_OP_IS_SOURCE(c) (((c) & 0x03) != 0x00) +#define TRACE_OP_IS_SW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x00) +#define TRACE_OP_IS_HW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x04) +#define TRACE_OP_IS_TARGET_SOURCE(c) ((c) == 0x01) + +#define TRACE_OP_GET_CONTINUATION(c) ((c) & 0x80) +#define TRACE_OP_GET_SOURCE_SIZE(c) ((c) & 0x03) +#define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) + + +// We use a global flag to allow communicating to the main thread from the signal handler. static bool g_done = false; -struct _st_settings_t -{ +struct _st_settings_t { bool show_help; bool show_version; int logging_level; int core_frequency_mhz; bool reset_board; char* serial_number; - bool wait_sync; }; typedef struct _st_settings_t st_settings_t; +// We use a simple state machine to parse the trace data. +enum _trace_step { + TRACE_STEP_IDLE, + TRACE_STEP_TARGET_SOURCE, + TRACE_STEP_SKIP_FRAME, + TRACE_STEP_SKIP_4, + TRACE_STEP_SKIP_3, + TRACE_STEP_SKIP_2, + TRACE_STEP_SKIP_1, +}; +typedef enum _trace_step trace_step; + +struct _st_trace_state_t { + trace_step step; + bool overflow; + bool error; +}; +typedef struct _st_trace_state_t st_trace_state_t; + + static void usage(void) { puts("st-trace - usage:"); puts(" -h, --help Print this help"); @@ -48,7 +81,6 @@ static void usage(void) { puts(" -cXX, --clock=XX Specify the core frequency in MHz"); puts(" -n, --no-reset Do not reset board on connection"); puts(" -sXX, --serial=XX Use a specific serial number"); - puts(" -a, --no-sync Do not wait for a sync packet"); } static void cleanup() { @@ -64,7 +96,6 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { {"clock", required_argument, NULL, 'c'}, {"no-reset", no_argument, NULL, 'n'}, {"serial", required_argument, NULL, 's'}, - {"no-sync", no_argument, NULL, 'a'}, {0, 0, 0, 0}, }; int option_index = 0; @@ -76,10 +107,9 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { settings->core_frequency_mhz = 0; settings->reset_board = true; settings->serial_number = NULL; - settings->wait_sync = true; ugly_init(settings->logging_level); - while ((c = getopt_long(argc, argv, "hVv::c:ns:a", long_options, &option_index)) != -1) { + while ((c = getopt_long(argc, argv, "hVv::c:ns:", long_options, &option_index)) != -1) { switch (c) { case 'h': settings->show_help = true; @@ -104,9 +134,6 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { case 's': settings->serial_number = optarg; break; - case 'a': - settings->wait_sync = false; - break; case '?': return false; break; @@ -128,6 +155,7 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { static stlink_t* StLinkConnect(const st_settings_t* settings) { if (settings->serial_number) { + // Convert our serial number string to a binary value. char serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; size_t length = 0; for (uint32_t n = 0; n < strlen(settings->serial_number) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { @@ -135,13 +163,16 @@ static stlink_t* StLinkConnect(const st_settings_t* settings) { memcpy(buffer, settings->serial_number + n, 2); serial_number[length++] = (uint8_t)strtol(buffer, NULL, 16); } + + // Open this specific stlink. return stlink_open_usb(settings->logging_level, false, serial_number, 0); } else { + // Otherwise, open any stlink. return stlink_open_usb(settings->logging_level, false, NULL, 0); } } -// TODO: Move this to device table. +// TODO: Consider moving this to the device table. static bool IsDeviceTraceSupported(int chip_id) { switch (chip_id) { case STLINK_CHIPID_STM32_F4: @@ -228,7 +259,7 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa return true; } -static bool ReadTrace(stlink_t* stlink) { +static bool ReadTrace(stlink_t* stlink, st_trace_state_t* state) { uint8_t buffer[STLINK_TRACE_BUF_LEN]; int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); @@ -244,14 +275,55 @@ static bool ReadTrace(stlink_t* stlink) { DLOG("Trace Length: %d\n", length); - printf("Data: "); - for (int i = 0; i < length; i++) - printf("%02x ", buffer[i]); - printf(" '"); - for (int i = 0; i < length; i++) - printf("%c", isprint(buffer[i]) ? buffer[i] : '?'); - printf("'\n"); - + for (int i = 0; i < length; i++) { + uint8_t c = buffer[i]; + + // Parse the input using a state machine. + switch (state->step) + { + case TRACE_STEP_IDLE: + if (TRACE_OP_IS_TARGET_SOURCE(c)) { + state->step = TRACE_STEP_TARGET_SOURCE; + } else if (TRACE_OP_IS_SOURCE(c)) { + const trace_step kSourceSkip[] = { TRACE_STEP_IDLE, TRACE_STEP_SKIP_1, TRACE_STEP_SKIP_2, TRACE_STEP_SKIP_4 }; + const char* type = TRACE_OP_IS_SW_SOURCE(c) ? "sw" : "hw"; + uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); + uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); + WLOG("Unsupported %s source 0x%x size %d", type, addr, size); + state->step = kSourceSkip[size]; + } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_EXTENSION(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + if (TRACE_OP_GET_CONTINUATION(c)) + state->step = TRACE_STEP_SKIP_FRAME; + } else if (TRACE_OP_IS_OVERFLOW(c)) { + state->overflow = true; + } else { + WLOG("Unknown opcode 0x%02x\n", c); + if (TRACE_OP_GET_CONTINUATION(c)) + state->step = TRACE_STEP_SKIP_FRAME; + } + break; + case TRACE_STEP_TARGET_SOURCE: + putchar(c); + state->step = TRACE_STEP_IDLE; + break; + case TRACE_STEP_SKIP_FRAME: + if (TRACE_OP_GET_CONTINUATION(c) == 0) + state->step = TRACE_STEP_IDLE; + break; + case TRACE_STEP_SKIP_4: + state->step = TRACE_STEP_SKIP_3; + break; + case TRACE_STEP_SKIP_3: + state->step = TRACE_STEP_SKIP_2; + break; + case TRACE_STEP_SKIP_2: + state->step = TRACE_STEP_SKIP_1; + break; + case TRACE_STEP_SKIP_1: + state->step = TRACE_STEP_IDLE; + break; + } + } return true; } @@ -276,7 +348,6 @@ int main(int argc, char** argv) DLOG("core_frequency = %d MHz\n", settings.core_frequency_mhz); DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); DLOG("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); - DLOG("wait_sync = %s\n", settings.wait_sync ? "true" : "false"); if (settings.show_help) { usage(); @@ -319,10 +390,11 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_STATE_ERROR; } - ILOG("Reading SWO Data\n"); + ILOG("Reading.\n"); + st_trace_state_t state = {}; while (!g_done) { - if (!ReadTrace(stlink)) + if (!ReadTrace(stlink, &state)) g_done = true; } From 8793f3ceef06a394c6ea8120dbe58ddd28b42ba4 Mon Sep 17 00:00:00 2001 From: John Hall Date: Sun, 29 Nov 2020 00:25:00 -0800 Subject: [PATCH 1052/1435] Tabs to spaces --- src/st-trace/trace.c | 670 +++++++++++++++++++++---------------------- 1 file changed, 335 insertions(+), 335 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index ccb1a4828..bb516ebf0 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -15,26 +15,26 @@ #define DEFAULT_LOGGING_LEVEL 50 #define DEBUG_LOGGING_LEVEL 100 -#define APP_RESULT_SUCCESS 0 -#define APP_RESULT_INVALID_PARAMS 1 -#define APP_RESULT_STLINK_NOT_FOUND 2 -#define APP_RESULT_STLINK_MISSING_DEVICE 3 -#define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 -#define APP_RESULT_STLINK_STATE_ERROR 5 +#define APP_RESULT_SUCCESS 0 +#define APP_RESULT_INVALID_PARAMS 1 +#define APP_RESULT_STLINK_NOT_FOUND 2 +#define APP_RESULT_STLINK_MISSING_DEVICE 3 +#define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 +#define APP_RESULT_STLINK_STATE_ERROR 5 // See https://developer.arm.com/documentation/ddi0403/ed/ -#define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) -#define TRACE_OP_IS_LOCAL_TIME(c) (((c) & 0x0f) == 0x00 && ((c) & 0x70) != 0x00) -#define TRACE_OP_IS_EXTENSION(c) (((c) & 0x0b) == 0x08) -#define TRACE_OP_IS_GLOBAL_TIME(c) (((c) & 0xdf) == 0x94) -#define TRACE_OP_IS_SOURCE(c) (((c) & 0x03) != 0x00) -#define TRACE_OP_IS_SW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x00) -#define TRACE_OP_IS_HW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x04) -#define TRACE_OP_IS_TARGET_SOURCE(c) ((c) == 0x01) +#define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) +#define TRACE_OP_IS_LOCAL_TIME(c) (((c) & 0x0f) == 0x00 && ((c) & 0x70) != 0x00) +#define TRACE_OP_IS_EXTENSION(c) (((c) & 0x0b) == 0x08) +#define TRACE_OP_IS_GLOBAL_TIME(c) (((c) & 0xdf) == 0x94) +#define TRACE_OP_IS_SOURCE(c) (((c) & 0x03) != 0x00) +#define TRACE_OP_IS_SW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x00) +#define TRACE_OP_IS_HW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x04) +#define TRACE_OP_IS_TARGET_SOURCE(c) ((c) == 0x01) -#define TRACE_OP_GET_CONTINUATION(c) ((c) & 0x80) -#define TRACE_OP_GET_SOURCE_SIZE(c) ((c) & 0x03) -#define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) +#define TRACE_OP_GET_CONTINUATION(c) ((c) & 0x80) +#define TRACE_OP_GET_SOURCE_SIZE(c) ((c) & 0x03) +#define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) // We use a global flag to allow communicating to the main thread from the signal handler. @@ -42,365 +42,365 @@ static bool g_done = false; struct _st_settings_t { - bool show_help; - bool show_version; - int logging_level; - int core_frequency_mhz; - bool reset_board; - char* serial_number; + bool show_help; + bool show_version; + int logging_level; + int core_frequency_mhz; + bool reset_board; + char* serial_number; }; typedef struct _st_settings_t st_settings_t; // We use a simple state machine to parse the trace data. enum _trace_step { - TRACE_STEP_IDLE, - TRACE_STEP_TARGET_SOURCE, - TRACE_STEP_SKIP_FRAME, - TRACE_STEP_SKIP_4, - TRACE_STEP_SKIP_3, - TRACE_STEP_SKIP_2, - TRACE_STEP_SKIP_1, + TRACE_STEP_IDLE, + TRACE_STEP_TARGET_SOURCE, + TRACE_STEP_SKIP_FRAME, + TRACE_STEP_SKIP_4, + TRACE_STEP_SKIP_3, + TRACE_STEP_SKIP_2, + TRACE_STEP_SKIP_1, }; typedef enum _trace_step trace_step; struct _st_trace_state_t { - trace_step step; - bool overflow; - bool error; + trace_step step; + bool overflow; + bool error; }; typedef struct _st_trace_state_t st_trace_state_t; static void usage(void) { - puts("st-trace - usage:"); - puts(" -h, --help Print this help"); - puts(" -V, --version Print this version"); - puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); - puts(" -v, --verbose Specify a generally verbose logging"); - puts(" -cXX, --clock=XX Specify the core frequency in MHz"); - puts(" -n, --no-reset Do not reset board on connection"); - puts(" -sXX, --serial=XX Use a specific serial number"); + puts("st-trace - usage:"); + puts(" -h, --help Print this help"); + puts(" -V, --version Print this version"); + puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); + puts(" -v, --verbose Specify a generally verbose logging"); + puts(" -cXX, --clock=XX Specify the core frequency in MHz"); + puts(" -n, --no-reset Do not reset board on connection"); + puts(" -sXX, --serial=XX Use a specific serial number"); } static void cleanup() { - g_done = true; + g_done = true; } bool parse_options(int argc, char** argv, st_settings_t *settings) { - static struct option long_options[] = { - {"help", no_argument, NULL, 'h'}, - {"version", no_argument, NULL, 'V'}, - {"verbose", optional_argument, NULL, 'v'}, - {"clock", required_argument, NULL, 'c'}, - {"no-reset", no_argument, NULL, 'n'}, - {"serial", required_argument, NULL, 's'}, - {0, 0, 0, 0}, - }; - int option_index = 0; - int c; - - settings->show_help = false; - settings->show_version = false; - settings->logging_level = DEFAULT_LOGGING_LEVEL; - settings->core_frequency_mhz = 0; - settings->reset_board = true; - settings->serial_number = NULL; - ugly_init(settings->logging_level); - - while ((c = getopt_long(argc, argv, "hVv::c:ns:", long_options, &option_index)) != -1) { - switch (c) { - case 'h': - settings->show_help = true; - break; - case 'V': - settings->show_version = true; - break; - case 'v': - if (optarg) { - settings->logging_level = atoi(optarg); - } else { - settings->logging_level = DEBUG_LOGGING_LEVEL; - } - ugly_init(settings->logging_level); - break; - case 'c': - settings->core_frequency_mhz = atoi(optarg); - break; - case 'n': - settings->reset_board = false; - break; - case 's': - settings->serial_number = optarg; - break; - case '?': - return false; - break; - default: - ELOG("Unknown command line option: '%c' (0x%02x)\n", c, c); - return false; - } - } - - if (optind < argc) { - while (optind < argc) { - ELOG("Unknown command line argument: '%s'\n", argv[optind++]); - } - return false; - } - - return true; + static struct option long_options[] = { + {"help", no_argument, NULL, 'h'}, + {"version", no_argument, NULL, 'V'}, + {"verbose", optional_argument, NULL, 'v'}, + {"clock", required_argument, NULL, 'c'}, + {"no-reset", no_argument, NULL, 'n'}, + {"serial", required_argument, NULL, 's'}, + {0, 0, 0, 0}, + }; + int option_index = 0; + int c; + + settings->show_help = false; + settings->show_version = false; + settings->logging_level = DEFAULT_LOGGING_LEVEL; + settings->core_frequency_mhz = 0; + settings->reset_board = true; + settings->serial_number = NULL; + ugly_init(settings->logging_level); + + while ((c = getopt_long(argc, argv, "hVv::c:ns:", long_options, &option_index)) != -1) { + switch (c) { + case 'h': + settings->show_help = true; + break; + case 'V': + settings->show_version = true; + break; + case 'v': + if (optarg) { + settings->logging_level = atoi(optarg); + } else { + settings->logging_level = DEBUG_LOGGING_LEVEL; + } + ugly_init(settings->logging_level); + break; + case 'c': + settings->core_frequency_mhz = atoi(optarg); + break; + case 'n': + settings->reset_board = false; + break; + case 's': + settings->serial_number = optarg; + break; + case '?': + return false; + break; + default: + ELOG("Unknown command line option: '%c' (0x%02x)\n", c, c); + return false; + } + } + + if (optind < argc) { + while (optind < argc) { + ELOG("Unknown command line argument: '%s'\n", argv[optind++]); + } + return false; + } + + return true; } static stlink_t* StLinkConnect(const st_settings_t* settings) { - if (settings->serial_number) { - // Convert our serial number string to a binary value. - char serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; - size_t length = 0; - for (uint32_t n = 0; n < strlen(settings->serial_number) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { - char buffer[3] = { 0 }; - memcpy(buffer, settings->serial_number + n, 2); - serial_number[length++] = (uint8_t)strtol(buffer, NULL, 16); - } - - // Open this specific stlink. - return stlink_open_usb(settings->logging_level, false, serial_number, 0); - } else { - // Otherwise, open any stlink. - return stlink_open_usb(settings->logging_level, false, NULL, 0); - } + if (settings->serial_number) { + // Convert our serial number string to a binary value. + char serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; + size_t length = 0; + for (uint32_t n = 0; n < strlen(settings->serial_number) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { + char buffer[3] = { 0 }; + memcpy(buffer, settings->serial_number + n, 2); + serial_number[length++] = (uint8_t)strtol(buffer, NULL, 16); + } + + // Open this specific stlink. + return stlink_open_usb(settings->logging_level, false, serial_number, 0); + } else { + // Otherwise, open any stlink. + return stlink_open_usb(settings->logging_level, false, NULL, 0); + } } // TODO: Consider moving this to the device table. static bool IsDeviceTraceSupported(int chip_id) { - switch (chip_id) { - case STLINK_CHIPID_STM32_F4: - case STLINK_CHIPID_STM32_F4_DSI: - case STLINK_CHIPID_STM32_F4_HD: - case STLINK_CHIPID_STM32_F4_LP: - case STLINK_CHIPID_STM32_F411RE: - case STLINK_CHIPID_STM32_F4_DE: - case STLINK_CHIPID_STM32_F446: - case STLINK_CHIPID_STM32_F410: - case STLINK_CHIPID_STM32_F3: - case STLINK_CHIPID_STM32_F37x: - case STLINK_CHIPID_STM32_F412: - case STLINK_CHIPID_STM32_F413: - case STLINK_CHIPID_STM32_F3_SMALL: - case STLINK_CHIPID_STM32_F334: - case STLINK_CHIPID_STM32_F303_HIGH: - return true; - default: - return false; - } + switch (chip_id) { + case STLINK_CHIPID_STM32_F4: + case STLINK_CHIPID_STM32_F4_DSI: + case STLINK_CHIPID_STM32_F4_HD: + case STLINK_CHIPID_STM32_F4_LP: + case STLINK_CHIPID_STM32_F411RE: + case STLINK_CHIPID_STM32_F4_DE: + case STLINK_CHIPID_STM32_F446: + case STLINK_CHIPID_STM32_F410: + case STLINK_CHIPID_STM32_F3: + case STLINK_CHIPID_STM32_F37x: + case STLINK_CHIPID_STM32_F412: + case STLINK_CHIPID_STM32_F413: + case STLINK_CHIPID_STM32_F3_SMALL: + case STLINK_CHIPID_STM32_F334: + case STLINK_CHIPID_STM32_F303_HIGH: + return true; + default: + return false; + } } static void Write32(stlink_t* stlink, uint32_t address, uint32_t data) { - write_uint32(stlink->q_buf, data); - stlink_write_mem32(stlink, address, 4); + write_uint32(stlink->q_buf, data); + stlink_write_mem32(stlink, address, 4); } static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_board) { - struct stlink_reg regp = {}; - - if (stlink_force_debug(stlink)) { - return false; - } - - if (reset_board && stlink_reset(stlink)) { - return false; - } - - // The remainder of the items in this function were taken directly from https://github.com/avrhack/stlink-trace/blob/master/stlink-trace.c#L386 - - Write32(stlink, 0xE000EDF0, 0xA05F0003); // Set DHCSR to C_HALT and C_DEBUGEN - Write32(stlink, 0xE000EDFC, 0x01000000); // Set TRCENA flag to enable global DWT and ITM - Write32(stlink, 0xE0002000, 0x00000002); // Set FP_CTRL to enable write - Write32(stlink, 0xE0001028, 0x00000000); // Set DWT_FUNCTION0 to DWT_FUNCTION3 to disable sampling - Write32(stlink, 0xE0001038, 0x00000000); - Write32(stlink, 0xE0001048, 0x00000000); - Write32(stlink, 0xE0001058, 0x00000000); - Write32(stlink, 0xE0001000, 0x00000000); // Clear DWT_CTRL and other registers - Write32(stlink, 0xE0001004, 0x00000000); - Write32(stlink, 0xE0001008, 0x00000000); - Write32(stlink, 0xE000100C, 0x00000000); - Write32(stlink, 0xE0001010, 0x00000000); - Write32(stlink, 0xE0001014, 0x00000000); - Write32(stlink, 0xE0001018, 0x00000000); - - stlink_read_reg(stlink, 15, ®p); // Read program counter - stlink_read_reg(stlink, 16, ®p); // Read xpsr register - - Write32(stlink, 0xE0042004, 0x00000027); // Set DBGMCU_CR to enable asynchronous transmission - - // Actually start tracing. - if (stlink_trace_enable(stlink)) { - return false; - } - - Write32(stlink, 0xE0040004, 0x00000001); // Set TPIU_CSPSR to enable trace port width of 2 - - if (core_frequency_mhz) { - uint32_t clock_divisor = core_frequency_mhz / 2 - 1; - Write32(stlink, 0xE0040010, clock_divisor); // Set TPIU_ACPR clock divisor - } - - Write32(stlink, 0xE00400F0, 0x00000002); // Set TPIU_SPPR to Asynchronous SWO (NRZ) - Write32(stlink, 0xE0040304, 0x00000100); // Set TPIU_FFCR continuous formatting) - Write32(stlink, 0xE0000FB0, 0xC5ACCE55); // Unlock the ITM registers for write - Write32(stlink, 0xE0000E90, 0x00000400); // Set sync counter - Write32(stlink, 0xE0000E80, 0x00010003); // Set ITM_TCR flags : ITMENA,TSENA ATB=0 - Write32(stlink, 0xE0000E00, 0xFFFFFFFF); // Enable all trace ports in ITM_TER - Write32(stlink, 0xE0000E40, 0x0000000F); // Enable unprivileged access to trace ports 31:0 in ITM_TPR - Write32(stlink, 0xE0000E40, 0x400003FE); // Set DWT_CTRL flags) - Write32(stlink, 0xE000EDFC, 0x01000000); // Enable tracing (DEMCR - TRCENA bit) - - return true; + struct stlink_reg regp = {}; + + if (stlink_force_debug(stlink)) { + return false; + } + + if (reset_board && stlink_reset(stlink)) { + return false; + } + + // The order and values to set were taken from https://github.com/avrhack/stlink-trace/blob/master/stlink-trace.c#L386 + + Write32(stlink, 0xE000EDF0, 0xA05F0003); // Set DHCSR to C_HALT and C_DEBUGEN + Write32(stlink, 0xE000EDFC, 0x01000000); // Set TRCENA flag to enable global DWT and ITM + Write32(stlink, 0xE0002000, 0x00000002); // Set FP_CTRL to enable write + Write32(stlink, 0xE0001028, 0x00000000); // Set DWT_FUNCTION0 to DWT_FUNCTION3 to disable sampling + Write32(stlink, 0xE0001038, 0x00000000); + Write32(stlink, 0xE0001048, 0x00000000); + Write32(stlink, 0xE0001058, 0x00000000); + Write32(stlink, 0xE0001000, 0x00000000); // Clear DWT_CTRL and other registers + Write32(stlink, 0xE0001004, 0x00000000); + Write32(stlink, 0xE0001008, 0x00000000); + Write32(stlink, 0xE000100C, 0x00000000); + Write32(stlink, 0xE0001010, 0x00000000); + Write32(stlink, 0xE0001014, 0x00000000); + Write32(stlink, 0xE0001018, 0x00000000); + + stlink_read_reg(stlink, 15, ®p); // Read program counter + stlink_read_reg(stlink, 16, ®p); // Read xpsr register + + Write32(stlink, 0xE0042004, 0x00000027); // Set DBGMCU_CR to enable asynchronous transmission + + // Actually start tracing. + if (stlink_trace_enable(stlink)) { + return false; + } + + Write32(stlink, 0xE0040004, 0x00000001); // Set TPIU_CSPSR to enable trace port width of 2 + + if (core_frequency_mhz) { + uint32_t clock_divisor = core_frequency_mhz / 2 - 1; + Write32(stlink, 0xE0040010, clock_divisor); // Set TPIU_ACPR clock divisor + } + + Write32(stlink, 0xE00400F0, 0x00000002); // Set TPIU_SPPR to Asynchronous SWO (NRZ) + Write32(stlink, 0xE0040304, 0x00000100); // Set TPIU_FFCR continuous formatting) + Write32(stlink, 0xE0000FB0, 0xC5ACCE55); // Unlock the ITM registers for write + Write32(stlink, 0xE0000E90, 0x00000400); // Set sync counter + Write32(stlink, 0xE0000E80, 0x00010003); // Set ITM_TCR flags : ITMENA,TSENA ATB=0 + Write32(stlink, 0xE0000E00, 0xFFFFFFFF); // Enable all trace ports in ITM_TER + Write32(stlink, 0xE0000E40, 0x0000000F); // Enable unprivileged access to trace ports 31:0 in ITM_TPR + Write32(stlink, 0xE0000E40, 0x400003FE); // Set DWT_CTRL flags) + Write32(stlink, 0xE000EDFC, 0x01000000); // Enable tracing (DEMCR - TRCENA bit) + + return true; } static bool ReadTrace(stlink_t* stlink, st_trace_state_t* state) { - uint8_t buffer[STLINK_TRACE_BUF_LEN]; - int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); - - if (length < 0) { - ELOG("Error reading trace (%d)\n", length); - return false; - } - - if (length == 0) { - usleep(1000); - return true; - } - - DLOG("Trace Length: %d\n", length); - - for (int i = 0; i < length; i++) { - uint8_t c = buffer[i]; - - // Parse the input using a state machine. - switch (state->step) - { - case TRACE_STEP_IDLE: - if (TRACE_OP_IS_TARGET_SOURCE(c)) { - state->step = TRACE_STEP_TARGET_SOURCE; - } else if (TRACE_OP_IS_SOURCE(c)) { - const trace_step kSourceSkip[] = { TRACE_STEP_IDLE, TRACE_STEP_SKIP_1, TRACE_STEP_SKIP_2, TRACE_STEP_SKIP_4 }; - const char* type = TRACE_OP_IS_SW_SOURCE(c) ? "sw" : "hw"; - uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); - uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); - WLOG("Unsupported %s source 0x%x size %d", type, addr, size); - state->step = kSourceSkip[size]; - } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_EXTENSION(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { - if (TRACE_OP_GET_CONTINUATION(c)) - state->step = TRACE_STEP_SKIP_FRAME; - } else if (TRACE_OP_IS_OVERFLOW(c)) { - state->overflow = true; - } else { - WLOG("Unknown opcode 0x%02x\n", c); - if (TRACE_OP_GET_CONTINUATION(c)) - state->step = TRACE_STEP_SKIP_FRAME; - } - break; - case TRACE_STEP_TARGET_SOURCE: - putchar(c); - state->step = TRACE_STEP_IDLE; - break; - case TRACE_STEP_SKIP_FRAME: - if (TRACE_OP_GET_CONTINUATION(c) == 0) - state->step = TRACE_STEP_IDLE; - break; - case TRACE_STEP_SKIP_4: - state->step = TRACE_STEP_SKIP_3; - break; - case TRACE_STEP_SKIP_3: - state->step = TRACE_STEP_SKIP_2; - break; - case TRACE_STEP_SKIP_2: - state->step = TRACE_STEP_SKIP_1; - break; - case TRACE_STEP_SKIP_1: - state->step = TRACE_STEP_IDLE; - break; - } - } - - return true; + uint8_t buffer[STLINK_TRACE_BUF_LEN]; + int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); + + if (length < 0) { + ELOG("Error reading trace (%d)\n", length); + return false; + } + + if (length == 0) { + usleep(1000); + return true; + } + + DLOG("Trace Length: %d\n", length); + + for (int i = 0; i < length; i++) { + uint8_t c = buffer[i]; + + // Parse the input using a state machine. + switch (state->step) + { + case TRACE_STEP_IDLE: + if (TRACE_OP_IS_TARGET_SOURCE(c)) { + state->step = TRACE_STEP_TARGET_SOURCE; + } else if (TRACE_OP_IS_SOURCE(c)) { + const trace_step kSourceSkip[] = { TRACE_STEP_IDLE, TRACE_STEP_SKIP_1, TRACE_STEP_SKIP_2, TRACE_STEP_SKIP_4 }; + const char* type = TRACE_OP_IS_SW_SOURCE(c) ? "sw" : "hw"; + uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); + uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); + WLOG("Unsupported %s source 0x%x size %d", type, addr, size); + state->step = kSourceSkip[size]; + } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_EXTENSION(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + if (TRACE_OP_GET_CONTINUATION(c)) + state->step = TRACE_STEP_SKIP_FRAME; + } else if (TRACE_OP_IS_OVERFLOW(c)) { + state->overflow = true; + } else { + WLOG("Unknown opcode 0x%02x\n", c); + if (TRACE_OP_GET_CONTINUATION(c)) + state->step = TRACE_STEP_SKIP_FRAME; + } + break; + case TRACE_STEP_TARGET_SOURCE: + putchar(c); + state->step = TRACE_STEP_IDLE; + break; + case TRACE_STEP_SKIP_FRAME: + if (TRACE_OP_GET_CONTINUATION(c) == 0) + state->step = TRACE_STEP_IDLE; + break; + case TRACE_STEP_SKIP_4: + state->step = TRACE_STEP_SKIP_3; + break; + case TRACE_STEP_SKIP_3: + state->step = TRACE_STEP_SKIP_2; + break; + case TRACE_STEP_SKIP_2: + state->step = TRACE_STEP_SKIP_1; + break; + case TRACE_STEP_SKIP_1: + state->step = TRACE_STEP_IDLE; + break; + } + } + + return true; } int main(int argc, char** argv) { - st_settings_t settings; - stlink_t* stlink = NULL; - - signal(SIGINT, &cleanup); - signal(SIGTERM, &cleanup); - signal(SIGSEGV, &cleanup); - - if (!parse_options(argc, argv, &settings)) { - usage(); - return APP_RESULT_INVALID_PARAMS; - } - - DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); - DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); - DLOG("logging_level = %d\n", settings.logging_level); - DLOG("core_frequency = %d MHz\n", settings.core_frequency_mhz); - DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); - DLOG("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); - - if (settings.show_help) { - usage(); - return APP_RESULT_SUCCESS; - } - - if (settings.show_version) { - printf("v%s\n", STLINK_VERSION); - return APP_RESULT_SUCCESS; - } - - stlink = StLinkConnect(&settings); - if (!stlink) { - ELOG("Unable to locate st-link\n"); - return APP_RESULT_STLINK_NOT_FOUND; - } - - stlink->verbose = settings.logging_level; - - if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { - ELOG("st-link not connected\n"); - return APP_RESULT_STLINK_MISSING_DEVICE; - } - - // TODO: Check if trace is supported by stlink. - - if (!IsDeviceTraceSupported(stlink->chip_id)) { - const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); - ELOG("We do not support SWO output for device '%s'", params->description); - return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; - } - - if (!EnableTrace(stlink, settings.core_frequency_mhz, settings.reset_board)) { - ELOG("Unable to enable trace mode\n"); - return APP_RESULT_STLINK_STATE_ERROR; - } - - if (stlink_run(stlink)) { - ELOG("Unable to run device\n"); - return APP_RESULT_STLINK_STATE_ERROR; - } - - ILOG("Reading.\n"); - - st_trace_state_t state = {}; - while (!g_done) { - if (!ReadTrace(stlink, &state)) - g_done = true; - } - - stlink_trace_disable(stlink); - stlink_close(stlink); - - return APP_RESULT_SUCCESS; + st_settings_t settings; + stlink_t* stlink = NULL; + + signal(SIGINT, &cleanup); + signal(SIGTERM, &cleanup); + signal(SIGSEGV, &cleanup); + + if (!parse_options(argc, argv, &settings)) { + usage(); + return APP_RESULT_INVALID_PARAMS; + } + + DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); + DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); + DLOG("logging_level = %d\n", settings.logging_level); + DLOG("core_frequency = %d MHz\n", settings.core_frequency_mhz); + DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); + DLOG("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); + + if (settings.show_help) { + usage(); + return APP_RESULT_SUCCESS; + } + + if (settings.show_version) { + printf("v%s\n", STLINK_VERSION); + return APP_RESULT_SUCCESS; + } + + stlink = StLinkConnect(&settings); + if (!stlink) { + ELOG("Unable to locate st-link\n"); + return APP_RESULT_STLINK_NOT_FOUND; + } + + stlink->verbose = settings.logging_level; + + if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { + ELOG("st-link not connected\n"); + return APP_RESULT_STLINK_MISSING_DEVICE; + } + + // TODO: Check if trace is supported by stlink. + + if (!IsDeviceTraceSupported(stlink->chip_id)) { + const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); + ELOG("We do not support SWO output for device '%s'", params->description); + return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; + } + + if (!EnableTrace(stlink, settings.core_frequency_mhz, settings.reset_board)) { + ELOG("Unable to enable trace mode\n"); + return APP_RESULT_STLINK_STATE_ERROR; + } + + if (stlink_run(stlink)) { + ELOG("Unable to run device\n"); + return APP_RESULT_STLINK_STATE_ERROR; + } + + ILOG("Reading.\n"); + + st_trace_state_t state = {}; + while (!g_done) { + if (!ReadTrace(stlink, &state)) + g_done = true; + } + + stlink_trace_disable(stlink); + stlink_close(stlink); + + return APP_RESULT_SUCCESS; } From 3531e34636f75cc094c995416c2a5b09daf67763 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 09:08:59 -0800 Subject: [PATCH 1053/1435] Code cleanup. --- src/common.c | 1 - src/st-trace/trace.c | 145 ++++++++++++++++++++++++------------------- src/stlink-lib/usb.c | 1 - 3 files changed, 80 insertions(+), 67 deletions(-) diff --git a/src/common.c b/src/common.c index e340ecc71..78cda9318 100644 --- a/src/common.c +++ b/src/common.c @@ -1688,7 +1688,6 @@ int stlink_trace_disable(stlink_t* sl) { } int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size) { - DLOG("*** stlink_trace_read ***\n"); return(sl->backend->trace_read(sl, buf, size)); } diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index bb516ebf0..148876c7a 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -24,6 +24,7 @@ // See https://developer.arm.com/documentation/ddi0403/ed/ #define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) +#define TRACE_OP_IS_SYNC(c) ((c) == 0x00) #define TRACE_OP_IS_LOCAL_TIME(c) (((c) & 0x0f) == 0x00 && ((c) & 0x70) != 0x00) #define TRACE_OP_IS_EXTENSION(c) (((c) & 0x0b) == 0x08) #define TRACE_OP_IS_GLOBAL_TIME(c) (((c) & 0xdf) == 0x94) @@ -53,23 +54,23 @@ typedef struct _st_settings_t st_settings_t; // We use a simple state machine to parse the trace data. -enum _trace_step { - TRACE_STEP_IDLE, - TRACE_STEP_TARGET_SOURCE, - TRACE_STEP_SKIP_FRAME, - TRACE_STEP_SKIP_4, - TRACE_STEP_SKIP_3, - TRACE_STEP_SKIP_2, - TRACE_STEP_SKIP_1, +enum _trace_state { + TRACE_STATE_IDLE, + TRACE_STATE_TARGET_SOURCE, + TRACE_STATE_SKIP_FRAME, + TRACE_STATE_SKIP_4, + TRACE_STATE_SKIP_3, + TRACE_STATE_SKIP_2, + TRACE_STATE_SKIP_1, }; -typedef enum _trace_step trace_step; +typedef enum _trace_state trace_state; -struct _st_trace_state_t { - trace_step step; +struct _st_trace_t { + trace_state state; bool overflow; bool error; }; -typedef struct _st_trace_state_t st_trace_state_t; +typedef struct _st_trace_t st_trace_t; static void usage(void) { @@ -242,8 +243,9 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa Write32(stlink, 0xE0040004, 0x00000001); // Set TPIU_CSPSR to enable trace port width of 2 if (core_frequency_mhz) { - uint32_t clock_divisor = core_frequency_mhz / 2 - 1; + uint32_t clock_divisor = core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; Write32(stlink, 0xE0040010, clock_divisor); // Set TPIU_ACPR clock divisor + } else { } Write32(stlink, 0xE00400F0, 0x00000002); // Set TPIU_SPPR to Asynchronous SWO (NRZ) @@ -259,7 +261,67 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa return true; } -static bool ReadTrace(stlink_t* stlink, st_trace_state_t* state) { +static void UpdateTrace(st_trace_t* trace, uint8_t c) { + // Parse the input using a state machine. + switch (trace->state) + { + case TRACE_STATE_IDLE: + if (TRACE_OP_IS_TARGET_SOURCE(c)) { + trace->state = TRACE_STATE_TARGET_SOURCE; + } else if (TRACE_OP_IS_SOURCE(c)) { + const trace_state kSourceSkip[] = { TRACE_STATE_IDLE, TRACE_STATE_SKIP_1, TRACE_STATE_SKIP_2, TRACE_STATE_SKIP_4 }; + const char* type = TRACE_OP_IS_SW_SOURCE(c) ? "sw" : "hw"; + uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); + uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); + if (TRACE_OP_IS_SW_SOURCE(c)) + WLOG("Unsupported %s source 0x%x size %d\n", type, addr, size); + trace->state = kSourceSkip[size]; + } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_EXTENSION(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + if (TRACE_OP_GET_CONTINUATION(c)) + trace->state = TRACE_STATE_SKIP_FRAME; + } else if (TRACE_OP_IS_SYNC(c)) { + } else if (TRACE_OP_IS_OVERFLOW(c)) { + trace->overflow = true; + } else { + WLOG("Unknown opcode 0x%02x\n", c); + if (TRACE_OP_GET_CONTINUATION(c)) + trace->state = TRACE_STATE_SKIP_FRAME; + } + break; + + case TRACE_STATE_TARGET_SOURCE: + putchar(c); + trace->state = TRACE_STATE_IDLE; + break; + + case TRACE_STATE_SKIP_FRAME: + if (TRACE_OP_GET_CONTINUATION(c) == 0) + trace->state = TRACE_STATE_IDLE; + break; + + case TRACE_STATE_SKIP_4: + trace->state = TRACE_STATE_SKIP_3; + break; + + case TRACE_STATE_SKIP_3: + trace->state = TRACE_STATE_SKIP_2; + break; + + case TRACE_STATE_SKIP_2: + trace->state = TRACE_STATE_SKIP_1; + break; + + case TRACE_STATE_SKIP_1: + trace->state = TRACE_STATE_IDLE; + break; + + default: + ELOG("Invalid state %d", trace->state); + trace->state = TRACE_STATE_IDLE; + } +} + +static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { uint8_t buffer[STLINK_TRACE_BUF_LEN]; int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); @@ -274,55 +336,8 @@ static bool ReadTrace(stlink_t* stlink, st_trace_state_t* state) { } DLOG("Trace Length: %d\n", length); - for (int i = 0; i < length; i++) { - uint8_t c = buffer[i]; - - // Parse the input using a state machine. - switch (state->step) - { - case TRACE_STEP_IDLE: - if (TRACE_OP_IS_TARGET_SOURCE(c)) { - state->step = TRACE_STEP_TARGET_SOURCE; - } else if (TRACE_OP_IS_SOURCE(c)) { - const trace_step kSourceSkip[] = { TRACE_STEP_IDLE, TRACE_STEP_SKIP_1, TRACE_STEP_SKIP_2, TRACE_STEP_SKIP_4 }; - const char* type = TRACE_OP_IS_SW_SOURCE(c) ? "sw" : "hw"; - uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); - uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); - WLOG("Unsupported %s source 0x%x size %d", type, addr, size); - state->step = kSourceSkip[size]; - } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_EXTENSION(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { - if (TRACE_OP_GET_CONTINUATION(c)) - state->step = TRACE_STEP_SKIP_FRAME; - } else if (TRACE_OP_IS_OVERFLOW(c)) { - state->overflow = true; - } else { - WLOG("Unknown opcode 0x%02x\n", c); - if (TRACE_OP_GET_CONTINUATION(c)) - state->step = TRACE_STEP_SKIP_FRAME; - } - break; - case TRACE_STEP_TARGET_SOURCE: - putchar(c); - state->step = TRACE_STEP_IDLE; - break; - case TRACE_STEP_SKIP_FRAME: - if (TRACE_OP_GET_CONTINUATION(c) == 0) - state->step = TRACE_STEP_IDLE; - break; - case TRACE_STEP_SKIP_4: - state->step = TRACE_STEP_SKIP_3; - break; - case TRACE_STEP_SKIP_3: - state->step = TRACE_STEP_SKIP_2; - break; - case TRACE_STEP_SKIP_2: - state->step = TRACE_STEP_SKIP_1; - break; - case TRACE_STEP_SKIP_1: - state->step = TRACE_STEP_IDLE; - break; - } + UpdateTrace(trace, buffer[i]); } return true; @@ -376,7 +391,7 @@ int main(int argc, char** argv) if (!IsDeviceTraceSupported(stlink->chip_id)) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); - ELOG("We do not support SWO output for device '%s'", params->description); + ELOG("We do not support SWO output for device '%s'\n", params->description); return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; } @@ -392,9 +407,9 @@ int main(int argc, char** argv) ILOG("Reading.\n"); - st_trace_state_t state = {}; + st_trace_t trace = {}; while (!g_done) { - if (!ReadTrace(stlink, &state)) + if (!ReadTrace(stlink, &trace)) g_done = true; } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 4d8d78a65..db187acc5 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1043,7 +1043,6 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { } size_t trace_count = read_uint16(sl->q_buf, 0); - DLOG("trace_count = 0x%08x\n", trace_count); if (trace_count > size) { ELOG("read_trace insufficient buffer length\n"); From 0b3f39fb13ea386105a9a8bb94256fef173073f6 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 10:21:19 -0800 Subject: [PATCH 1054/1435] Checked that the trace port is configured. Added log messages to share the configuration and to tell the user what to do if it is not configured. --- src/st-trace/trace.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 148876c7a..aa8fb50c4 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -199,7 +199,16 @@ static bool IsDeviceTraceSupported(int chip_id) { static void Write32(stlink_t* stlink, uint32_t address, uint32_t data) { write_uint32(stlink->q_buf, data); - stlink_write_mem32(stlink, address, 4); + if (stlink_write_mem32(stlink, address, 4)) { + ELOG("Unable to set address 0x%08x to 0x%08x\n", address, data); + } +} + +static uint32_t Read32(stlink_t* stlink, uint32_t address) { + if (stlink_read_mem32(stlink, address, 4)) { + ELOG("Unable to read from address 0x%08x\n", address); + } + return read_uint32(stlink->q_buf, 0); } static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_board) { @@ -243,9 +252,17 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa Write32(stlink, 0xE0040004, 0x00000001); // Set TPIU_CSPSR to enable trace port width of 2 if (core_frequency_mhz) { - uint32_t clock_divisor = core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; - Write32(stlink, 0xE0040010, clock_divisor); // Set TPIU_ACPR clock divisor + uint32_t prescaler = core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; + Write32(stlink, 0xE0040010, prescaler); // Set TPIU_ACPR clock divisor + } + uint32_t prescaler = Read32(stlink, 0xE0040010); + if (prescaler) { + uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; + ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", (system_clock_speed + 500000) / 1000000); } else { + WLOG("Trace Port Interface not configured. Specify the system clock with a --clock=XX command\n"); + WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); } Write32(stlink, 0xE00400F0, 0x00000002); // Set TPIU_SPPR to Asynchronous SWO (NRZ) From acbb78d1f4674b5dfd2464c1ed2e5322a27d5370 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 10:51:28 -0800 Subject: [PATCH 1055/1435] Checking that stlink supports tracing. --- src/common.c | 5 +++++ src/st-trace/trace.c | 28 ++++++++++++++++------------ 2 files changed, 21 insertions(+), 12 deletions(-) diff --git a/src/common.c b/src/common.c index 78cda9318..bda2ccf87 100644 --- a/src/common.c +++ b/src/common.c @@ -1465,6 +1465,10 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { if (sl->version.jtag_v >= 15) { sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; } + + if (sl->version.jtag_v >= 13) { + sl->version.flags |= STLINK_F_HAS_TRACE; + } } } else { // V3 uses different version format, for reference see OpenOCD source @@ -1478,6 +1482,7 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { slv->jtag_api = STLINK_JTAG_API_V3; /* preferred API to get last R/W status */ sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + sl->version.flags |= STLINK_F_HAS_TRACE; } return; diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index aa8fb50c4..2646dead5 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -20,9 +20,10 @@ #define APP_RESULT_STLINK_NOT_FOUND 2 #define APP_RESULT_STLINK_MISSING_DEVICE 3 #define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 -#define APP_RESULT_STLINK_STATE_ERROR 5 +#define APP_RESULT_STLINK_UNSUPPORTED_LINK 5 +#define APP_RESULT_STLINK_STATE_ERROR 6 -// See https://developer.arm.com/documentation/ddi0403/ed/ +// See D4.2 of https://developer.arm.com/documentation/ddi0403/ed/ #define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) #define TRACE_OP_IS_SYNC(c) ((c) == 0x00) #define TRACE_OP_IS_LOCAL_TIME(c) (((c) & 0x0f) == 0x00 && ((c) & 0x70) != 0x00) @@ -32,7 +33,6 @@ #define TRACE_OP_IS_SW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x00) #define TRACE_OP_IS_HW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x04) #define TRACE_OP_IS_TARGET_SOURCE(c) ((c) == 0x01) - #define TRACE_OP_GET_CONTINUATION(c) ((c) & 0x80) #define TRACE_OP_GET_SOURCE_SIZE(c) ((c) & 0x03) #define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) @@ -293,7 +293,10 @@ static void UpdateTrace(st_trace_t* trace, uint8_t c) { if (TRACE_OP_IS_SW_SOURCE(c)) WLOG("Unsupported %s source 0x%x size %d\n", type, addr, size); trace->state = kSourceSkip[size]; - } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_EXTENSION(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + if (TRACE_OP_GET_CONTINUATION(c)) + trace->state = TRACE_STATE_SKIP_FRAME; + } else if (TRACE_OP_IS_EXTENSION(c)) { if (TRACE_OP_GET_CONTINUATION(c)) trace->state = TRACE_STATE_SKIP_FRAME; } else if (TRACE_OP_IS_SYNC(c)) { @@ -393,18 +396,21 @@ int main(int argc, char** argv) stlink = StLinkConnect(&settings); if (!stlink) { - ELOG("Unable to locate st-link\n"); + ELOG("Unable to locate an stlink\n"); return APP_RESULT_STLINK_NOT_FOUND; } stlink->verbose = settings.logging_level; if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { - ELOG("st-link not connected\n"); + ELOG("Your stlink is not connected to a device\n"); return APP_RESULT_STLINK_MISSING_DEVICE; } - // TODO: Check if trace is supported by stlink. + if (!(stlink->version.flags & STLINK_F_HAS_TRACE)) { + ELOG("Your stlink does not support tracing\n"); + return APP_RESULT_STLINK_UNSUPPORTED_LINK; + } if (!IsDeviceTraceSupported(stlink->chip_id)) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); @@ -422,12 +428,10 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_STATE_ERROR; } - ILOG("Reading.\n"); - + ILOG("Reading Trace\n"); st_trace_t trace = {}; - while (!g_done) { - if (!ReadTrace(stlink, &trace)) - g_done = true; + while (!g_done && ReadTrace(stlink, &trace)) { + // TODO: Check that things are roughly working. } stlink_trace_disable(stlink); From 722224e5f282dd0ee727fbf7787d7ccd745f3a01 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 11:10:59 -0800 Subject: [PATCH 1056/1435] Adding a force flag to ignore errors. --- src/st-trace/trace.c | 61 +++++++++++++++++++++++++++++++------------- 1 file changed, 43 insertions(+), 18 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 2646dead5..ef34d62e0 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -48,6 +48,7 @@ struct _st_settings_t { int logging_level; int core_frequency_mhz; bool reset_board; + bool force; char* serial_number; }; typedef struct _st_settings_t st_settings_t; @@ -82,6 +83,7 @@ static void usage(void) { puts(" -cXX, --clock=XX Specify the core frequency in MHz"); puts(" -n, --no-reset Do not reset board on connection"); puts(" -sXX, --serial=XX Use a specific serial number"); + puts(" -f, --force Ignore some errors"); } static void cleanup() { @@ -97,20 +99,23 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { {"clock", required_argument, NULL, 'c'}, {"no-reset", no_argument, NULL, 'n'}, {"serial", required_argument, NULL, 's'}, + {"force", no_argument, NULL, 'f'}, {0, 0, 0, 0}, }; int option_index = 0; int c; + bool error = false; settings->show_help = false; settings->show_version = false; settings->logging_level = DEFAULT_LOGGING_LEVEL; settings->core_frequency_mhz = 0; settings->reset_board = true; + settings->force = false; settings->serial_number = NULL; ugly_init(settings->logging_level); - while ((c = getopt_long(argc, argv, "hVv::c:ns:", long_options, &option_index)) != -1) { + while ((c = getopt_long(argc, argv, "hVv::c:ns:f", long_options, &option_index)) != -1) { switch (c) { case 'h': settings->show_help = true; @@ -132,15 +137,19 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { case 'n': settings->reset_board = false; break; + case 'f': + settings->force = true; + break; case 's': settings->serial_number = optarg; break; case '?': - return false; + error = true; break; default: ELOG("Unknown command line option: '%c' (0x%02x)\n", c, c); - return false; + error = true; + break; } } @@ -148,9 +157,12 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { while (optind < argc) { ELOG("Unknown command line argument: '%s'\n", argv[optind++]); } - return false; + error = true; } + if (error && !settings->force) + return false; + return true; } @@ -211,15 +223,19 @@ static uint32_t Read32(stlink_t* stlink, uint32_t address) { return read_uint32(stlink->q_buf, 0); } -static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_board) { +static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { struct stlink_reg regp = {}; if (stlink_force_debug(stlink)) { - return false; + ELOG("Unable to debug device\n"); + if (!settings->force) + return false; } - if (reset_board && stlink_reset(stlink)) { - return false; + if (settings->reset_board && stlink_reset(stlink)) { + ELOG("Unable to reset device\n"); + if (!settings->force) + return false; } // The order and values to set were taken from https://github.com/avrhack/stlink-trace/blob/master/stlink-trace.c#L386 @@ -246,13 +262,15 @@ static bool EnableTrace(stlink_t* stlink, int core_frequency_mhz, bool reset_boa // Actually start tracing. if (stlink_trace_enable(stlink)) { - return false; + ELOG("Unable to trace device\n"); + if (!settings->force) + return false; } Write32(stlink, 0xE0040004, 0x00000001); // Set TPIU_CSPSR to enable trace port width of 2 - if (core_frequency_mhz) { - uint32_t prescaler = core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; + if (settings->core_frequency_mhz) { + uint32_t prescaler = settings->core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; Write32(stlink, 0xE0040010, prescaler); // Set TPIU_ACPR clock divisor } uint32_t prescaler = Read32(stlink, 0xE0040010); @@ -304,6 +322,7 @@ static void UpdateTrace(st_trace_t* trace, uint8_t c) { trace->overflow = true; } else { WLOG("Unknown opcode 0x%02x\n", c); + trace->error = true; if (TRACE_OP_GET_CONTINUATION(c)) trace->state = TRACE_STATE_SKIP_FRAME; } @@ -336,7 +355,7 @@ static void UpdateTrace(st_trace_t* trace, uint8_t c) { break; default: - ELOG("Invalid state %d", trace->state); + ELOG("Invalid state %d. This should never happen\n", trace->state); trace->state = TRACE_STATE_IDLE; } } @@ -382,6 +401,7 @@ int main(int argc, char** argv) DLOG("logging_level = %d\n", settings.logging_level); DLOG("core_frequency = %d MHz\n", settings.core_frequency_mhz); DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); + DLOG("force = %s\n", settings.force ? "true" : "false"); DLOG("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); if (settings.show_help) { @@ -404,28 +424,33 @@ int main(int argc, char** argv) if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { ELOG("Your stlink is not connected to a device\n"); - return APP_RESULT_STLINK_MISSING_DEVICE; + if (!settings.force) + return APP_RESULT_STLINK_MISSING_DEVICE; } if (!(stlink->version.flags & STLINK_F_HAS_TRACE)) { ELOG("Your stlink does not support tracing\n"); - return APP_RESULT_STLINK_UNSUPPORTED_LINK; + if (!settings.force) + return APP_RESULT_STLINK_UNSUPPORTED_LINK; } if (!IsDeviceTraceSupported(stlink->chip_id)) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); ELOG("We do not support SWO output for device '%s'\n", params->description); - return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; + if (!settings.force) + return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; } - if (!EnableTrace(stlink, settings.core_frequency_mhz, settings.reset_board)) { + if (!EnableTrace(stlink, &settings)) { ELOG("Unable to enable trace mode\n"); - return APP_RESULT_STLINK_STATE_ERROR; + if (!settings.force) + return APP_RESULT_STLINK_STATE_ERROR; } if (stlink_run(stlink)) { ELOG("Unable to run device\n"); - return APP_RESULT_STLINK_STATE_ERROR; + if (!settings.force) + return APP_RESULT_STLINK_STATE_ERROR; } ILOG("Reading Trace\n"); From 3188fb48d1cbd745f437c3bd55af3a8599c0484f Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 19:39:43 -0800 Subject: [PATCH 1057/1435] Updating to use register names to make code more readable. --- inc/stlink.h | 3 ++ src/st-trace/trace.c | 124 ++++++++++++++++++++++++++++++------------- 2 files changed, 89 insertions(+), 38 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index e7aefbded..1c9f6b09a 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -105,6 +105,9 @@ enum target_state { #define S_RETIRE_ST (1 << 24) #define S_RESET_ST (1 << 25) +/* DCB_DEMCR field definitions */ +#define DEMCR_TRCENA (1 << 24) + /* Map the relevant features, quirks and workaround for specific firmware version of stlink */ #define STLINK_F_HAS_TRACE (1 << 0) #define STLINK_F_HAS_SWD_SET_FREQ (1 << 1) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index ef34d62e0..877bd4e35 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -38,6 +38,64 @@ #define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) +// Instrumentation Trace Macrocell (ITM) Registers +#define ITM_TER 0xE0000E00 // ITM Trace Enable Register +#define ITM_TPR 0xE0000E40 // ITM Trace Privilege Register +#define ITM_TCR 0xE0000E80 // ITM Trace Control Register +#define ITM_TCC 0xE0000E90 // ITM Trace Cycle Count +#define ITM_LAR 0xE0000FB0 // ITM Lock Access Register + +// ITM field definitions +#define ITM_TER_PORTS_ALL (0xFFFFFFFF) +#define ITM_TPR_PORTS_ALL (0x0F) +#define ITM_TCR_TRACE_BUS_ID_1 (0x01 << 16) +#define ITM_TCR_SWO_ENA (1 << 4) +#define ITM_TCR_DWT_ENA (1 << 3) +#define ITM_TCR_SYNC_ENA (1 << 2) +#define ITM_TCR_TS_ENA (1 << 1) +#define ITM_TCR_ITM_ENA (1 << 0) +#define ITM_LAR_KEY 0xC5ACCE55 + +// Data Watchpoint and Trace (DWT) Registers +#define DWT_CTRL 0xE0001000 // DWT Control Register +#define DWT_FUNCTION0 0xE0001028 // DWT Function Register 0 +#define DWT_FUNCTION1 0xE0001038 // DWT Function Register 1 +#define DWT_FUNCTION2 0xE0001048 // DWT Function Register 2 +#define DWT_FUNCTION3 0xE0001058 // DWT Function Register 3 + +// DWT field definitions +#define DWT_CTRL_NUM_COMP (1 << 28) +#define DWT_CTRL_CYC_TAP (1 << 9) +#define DWT_CTRL_POST_INIT (1 << 5) +#define DWT_CTRL_POST_PRESET (1 << 1) +#define DWT_CTRL_CYCCNT_ENA (1 << 0) + +// Trace Port Interface (TPI) Registers +#define TPI_CSPSR 0xE0040004 // TPI Current Parallel Port Size Register +#define TPI_ACPR 0xE0040010 // TPI Asynchronous Clock Prescaler Register +#define TPI_SPPR 0xE00400F0 // TPI Selected Pin Protocol Register +#define TPI_FFCR 0xE0040304 // TPI Formatter and Flush Control Register + +// TPI field definitions +#define TPI_TPI_CSPSR_PORT_SIZE_1 (0x01 << 0) +#define TPI_SPPR_SWO_MANCHESTER (0x01 << 0) +#define TPI_SPPR_SWO_NRZ (0x02 << 0) +#define TPI_FFCR_EN_F_CONT (0x01 << 1) +#define TPI_FFCR_F_ON_MAN (0x01 << 6) +#define TPI_FFCR_TRIG_IN (0x01 << 8) + +// Other Registers +#define FP_CTRL 0xE0002000 // Flash Patch Control Register [WHY DO WE NEED THIS?] +#define DBGMCU_CR 0xE0042004 // Debug MCU Configuration Register + +// Other register field definitions +#define FP_CTRL_KEY (1 << 1) +#define DBGMCU_CR_DBG_SLEEP (1 << 0) +#define DBGMCU_CR_DBG_STOP (1 << 1) +#define DBGMCU_CR_DBG_STANDBY (1 << 2) +#define DBGMCU_CR_TRACE_IOEN (1 << 5) +#define DBGMCU_CR_TRACE_MODE_ASYNC (0x00 << 6) + // We use a global flag to allow communicating to the main thread from the signal handler. static bool g_done = false; @@ -185,8 +243,8 @@ static stlink_t* StLinkConnect(const st_settings_t* settings) { } } -// TODO: Consider moving this to the device table. static bool IsDeviceTraceSupported(int chip_id) { + // TODO: Consider moving this to a flag in the device table. switch (chip_id) { case STLINK_CHIPID_STM32_F4: case STLINK_CHIPID_STM32_F4_DSI: @@ -224,7 +282,6 @@ static uint32_t Read32(stlink_t* stlink, uint32_t address) { } static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { - struct stlink_reg regp = {}; if (stlink_force_debug(stlink)) { ELOG("Unable to debug device\n"); @@ -238,42 +295,31 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { return false; } - // The order and values to set were taken from https://github.com/avrhack/stlink-trace/blob/master/stlink-trace.c#L386 - - Write32(stlink, 0xE000EDF0, 0xA05F0003); // Set DHCSR to C_HALT and C_DEBUGEN - Write32(stlink, 0xE000EDFC, 0x01000000); // Set TRCENA flag to enable global DWT and ITM - Write32(stlink, 0xE0002000, 0x00000002); // Set FP_CTRL to enable write - Write32(stlink, 0xE0001028, 0x00000000); // Set DWT_FUNCTION0 to DWT_FUNCTION3 to disable sampling - Write32(stlink, 0xE0001038, 0x00000000); - Write32(stlink, 0xE0001048, 0x00000000); - Write32(stlink, 0xE0001058, 0x00000000); - Write32(stlink, 0xE0001000, 0x00000000); // Clear DWT_CTRL and other registers - Write32(stlink, 0xE0001004, 0x00000000); - Write32(stlink, 0xE0001008, 0x00000000); - Write32(stlink, 0xE000100C, 0x00000000); - Write32(stlink, 0xE0001010, 0x00000000); - Write32(stlink, 0xE0001014, 0x00000000); - Write32(stlink, 0xE0001018, 0x00000000); - - stlink_read_reg(stlink, 15, ®p); // Read program counter - stlink_read_reg(stlink, 16, ®p); // Read xpsr register - - Write32(stlink, 0xE0042004, 0x00000027); // Set DBGMCU_CR to enable asynchronous transmission - - // Actually start tracing. + Write32(stlink, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); // Debug and halt the CPU + Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); // Enable tracing + Write32(stlink, FP_CTRL, FP_CTRL_KEY); // Disable flash patch unit. + Write32(stlink, DWT_FUNCTION0, 0); // Disable sampling units + Write32(stlink, DWT_FUNCTION1, 0); + Write32(stlink, DWT_FUNCTION2, 0); + Write32(stlink, DWT_FUNCTION3, 0); + Write32(stlink, DWT_CTRL, 0); // Disable other watchpoint and trace features + Write32(stlink, DBGMCU_CR, DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP | + DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_TRACE_IOEN | + DBGMCU_CR_TRACE_MODE_ASYNC); // Enable async tracing + if (stlink_trace_enable(stlink)) { - ELOG("Unable to trace device\n"); + ELOG("Unable to turn on tracing in stlink\n"); if (!settings->force) return false; } - Write32(stlink, 0xE0040004, 0x00000001); // Set TPIU_CSPSR to enable trace port width of 2 + Write32(stlink, TPI_CSPSR, TPI_TPI_CSPSR_PORT_SIZE_1); if (settings->core_frequency_mhz) { uint32_t prescaler = settings->core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; - Write32(stlink, 0xE0040010, prescaler); // Set TPIU_ACPR clock divisor + Write32(stlink, TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor } - uint32_t prescaler = Read32(stlink, 0xE0040010); + uint32_t prescaler = Read32(stlink, TPI_ACPR); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", (system_clock_speed + 500000) / 1000000); @@ -283,15 +329,17 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); } - Write32(stlink, 0xE00400F0, 0x00000002); // Set TPIU_SPPR to Asynchronous SWO (NRZ) - Write32(stlink, 0xE0040304, 0x00000100); // Set TPIU_FFCR continuous formatting) - Write32(stlink, 0xE0000FB0, 0xC5ACCE55); // Unlock the ITM registers for write - Write32(stlink, 0xE0000E90, 0x00000400); // Set sync counter - Write32(stlink, 0xE0000E80, 0x00010003); // Set ITM_TCR flags : ITMENA,TSENA ATB=0 - Write32(stlink, 0xE0000E00, 0xFFFFFFFF); // Enable all trace ports in ITM_TER - Write32(stlink, 0xE0000E40, 0x0000000F); // Enable unprivileged access to trace ports 31:0 in ITM_TPR - Write32(stlink, 0xE0000E40, 0x400003FE); // Set DWT_CTRL flags) - Write32(stlink, 0xE000EDFC, 0x01000000); // Enable tracing (DEMCR - TRCENA bit) + Write32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN | TPI_FFCR_EN_F_CONT); + Write32(stlink, TPI_SPPR, TPI_SPPR_SWO_NRZ); + Write32(stlink, ITM_LAR, ITM_LAR_KEY); // Unlocks the following registers. + Write32(stlink, ITM_TCC, 0x00000400); // Set sync counter + Write32(stlink, ITM_TCR, ITM_TCR_TRACE_BUS_ID_1 | ITM_TCR_TS_ENA | ITM_TCR_ITM_ENA); + Write32(stlink, ITM_TER, ITM_TER_PORTS_ALL); + Write32(stlink, ITM_TPR, ITM_TPR_PORTS_ALL); + Write32(stlink, DWT_CTRL, 4 * DWT_CTRL_NUM_COMP | DWT_CTRL_CYC_TAP | + 0xF * DWT_CTRL_POST_INIT | 0xF * DWT_CTRL_POST_PRESET | + DWT_CTRL_CYCCNT_ENA); + Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); // Enable tracing (again...?) return true; } From 074f061b667a2bdae8eeb26d786f88ac2920fb94 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 19:43:36 -0800 Subject: [PATCH 1058/1435] Verified sleep timer is about right. --- src/st-trace/trace.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 877bd4e35..5cafc85ec 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -141,7 +141,7 @@ static void usage(void) { puts(" -cXX, --clock=XX Specify the core frequency in MHz"); puts(" -n, --no-reset Do not reset board on connection"); puts(" -sXX, --serial=XX Use a specific serial number"); - puts(" -f, --force Ignore some errors"); + puts(" -f, --force Ignore most initialization errors"); } static void cleanup() { @@ -418,7 +418,7 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { } if (length == 0) { - usleep(1000); + usleep(1000); // Our buffer could fill in around 2ms, so sleep half that. return true; } From f51f06535eb9979456eb553a1c7724f96116e7ba Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 21:00:29 -0800 Subject: [PATCH 1059/1435] Added a check that looks at connection results after 10 seconds and displays a diagnositic message if it looks like we are not configured correctly. --- src/st-trace/trace.c | 99 ++++++++++++++++++++++++++++++++------------ 1 file changed, 73 insertions(+), 26 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 5cafc85ec..b2837dbbe 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -25,7 +26,6 @@ // See D4.2 of https://developer.arm.com/documentation/ddi0403/ed/ #define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) -#define TRACE_OP_IS_SYNC(c) ((c) == 0x00) #define TRACE_OP_IS_LOCAL_TIME(c) (((c) & 0x0f) == 0x00 && ((c) & 0x70) != 0x00) #define TRACE_OP_IS_EXTENSION(c) (((c) & 0x0b) == 0x08) #define TRACE_OP_IS_GLOBAL_TIME(c) (((c) & 0xdf) == 0x94) @@ -100,7 +100,7 @@ static bool g_done = false; -struct _st_settings_t { +typedef struct { bool show_help; bool show_version; int logging_level; @@ -108,12 +108,11 @@ struct _st_settings_t { bool reset_board; bool force; char* serial_number; -}; -typedef struct _st_settings_t st_settings_t; +} st_settings_t; // We use a simple state machine to parse the trace data. -enum _trace_state { +typedef enum { TRACE_STATE_IDLE, TRACE_STATE_TARGET_SOURCE, TRACE_STATE_SKIP_FRAME, @@ -121,15 +120,22 @@ enum _trace_state { TRACE_STATE_SKIP_3, TRACE_STATE_SKIP_2, TRACE_STATE_SKIP_1, -}; -typedef enum _trace_state trace_state; +} trace_state; + +typedef struct { + time_t start_time; + bool configuration_checked; -struct _st_trace_t { trace_state state; - bool overflow; - bool error; -}; -typedef struct _st_trace_t st_trace_t; + + uint32_t count_raw_bytes; + uint32_t count_target_data; + uint32_t count_time_packets; + uint32_t count_overflow; + uint32_t count_error; + + uint8_t unknown_opcodes[256 / 8]; +} st_trace_t; static void usage(void) { @@ -295,14 +301,14 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { return false; } - Write32(stlink, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); // Debug and halt the CPU - Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); // Enable tracing - Write32(stlink, FP_CTRL, FP_CTRL_KEY); // Disable flash patch unit. - Write32(stlink, DWT_FUNCTION0, 0); // Disable sampling units + Write32(stlink, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); + Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); + Write32(stlink, FP_CTRL, FP_CTRL_KEY); + Write32(stlink, DWT_FUNCTION0, 0); Write32(stlink, DWT_FUNCTION1, 0); Write32(stlink, DWT_FUNCTION2, 0); Write32(stlink, DWT_FUNCTION3, 0); - Write32(stlink, DWT_CTRL, 0); // Disable other watchpoint and trace features + Write32(stlink, DWT_CTRL, 0); Write32(stlink, DBGMCU_CR, DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP | DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_ASYNC); // Enable async tracing @@ -322,7 +328,8 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { uint32_t prescaler = Read32(stlink, TPI_ACPR); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; - ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", (system_clock_speed + 500000) / 1000000); + uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; + ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", system_clock_speed_mhz); } else { WLOG("Trace Port Interface not configured. Specify the system clock with a --clock=XX command\n"); WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); @@ -331,7 +338,7 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { Write32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN | TPI_FFCR_EN_F_CONT); Write32(stlink, TPI_SPPR, TPI_SPPR_SWO_NRZ); - Write32(stlink, ITM_LAR, ITM_LAR_KEY); // Unlocks the following registers. + Write32(stlink, ITM_LAR, ITM_LAR_KEY); Write32(stlink, ITM_TCC, 0x00000400); // Set sync counter Write32(stlink, ITM_TCR, ITM_TCR_TRACE_BUS_ID_1 | ITM_TCR_TS_ENA | ITM_TCR_ITM_ENA); Write32(stlink, ITM_TER, ITM_TER_PORTS_ALL); @@ -339,13 +346,14 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { Write32(stlink, DWT_CTRL, 4 * DWT_CTRL_NUM_COMP | DWT_CTRL_CYC_TAP | 0xF * DWT_CTRL_POST_INIT | 0xF * DWT_CTRL_POST_PRESET | DWT_CTRL_CYCCNT_ENA); - Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); // Enable tracing (again...?) + Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); return true; } static void UpdateTrace(st_trace_t* trace, uint8_t c) { // Parse the input using a state machine. + trace->count_raw_bytes++; switch (trace->state) { case TRACE_STATE_IDLE: @@ -360,17 +368,19 @@ static void UpdateTrace(st_trace_t* trace, uint8_t c) { WLOG("Unsupported %s source 0x%x size %d\n", type, addr, size); trace->state = kSourceSkip[size]; } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + trace->count_time_packets++; if (TRACE_OP_GET_CONTINUATION(c)) trace->state = TRACE_STATE_SKIP_FRAME; } else if (TRACE_OP_IS_EXTENSION(c)) { if (TRACE_OP_GET_CONTINUATION(c)) trace->state = TRACE_STATE_SKIP_FRAME; - } else if (TRACE_OP_IS_SYNC(c)) { } else if (TRACE_OP_IS_OVERFLOW(c)) { - trace->overflow = true; + trace->count_overflow++; } else { - WLOG("Unknown opcode 0x%02x\n", c); - trace->error = true; + if (!(trace->unknown_opcodes[c / 8] & (1 << c % 8))) + WLOG("Unknown opcode 0x%02x\n", c); + trace->unknown_opcodes[c / 8] |= (1 << c % 8); + trace->count_error++; if (TRACE_OP_GET_CONTINUATION(c)) trace->state = TRACE_STATE_SKIP_FRAME; } @@ -378,6 +388,7 @@ static void UpdateTrace(st_trace_t* trace, uint8_t c) { case TRACE_STATE_TARGET_SOURCE: putchar(c); + trace->count_target_data++; trace->state = TRACE_STATE_IDLE; break; @@ -422,7 +433,6 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { return true; } - DLOG("Trace Length: %d\n", length); for (int i = 0; i < length; i++) { UpdateTrace(trace, buffer[i]); } @@ -430,6 +440,42 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { return true; } +static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace) { + uint32_t elapsed_time_s = time(NULL) - trace->start_time; + if (trace->configuration_checked || elapsed_time_s < 10) { + return; + } + trace->configuration_checked = true; + + // Simple huristic to determine if we are configured poorly. + if (trace->count_raw_bytes < 100 || trace->count_error > 1 || trace->count_time_packets < 10) { + // Output Diagnostic Information + WLOG("****\n"); + WLOG("We do not appear to be retrieving data from the stlink correctly.\n"); + WLOG("Raw Bytes: %d\n", trace->count_raw_bytes); + WLOG("Target Data: %d\n", trace->count_target_data); + WLOG("Time Packets: %d\n", trace->count_time_packets); + WLOG("Overlow Count: %d\n", trace->count_overflow); + WLOG("Errors: %d\n", trace->count_error); + for (uint32_t i = 0; i <= 0xFF; i++) + if (trace->unknown_opcodes[i / 8] & (1 << i % 8)) + WLOG("Unknown Opcode 0x%02x\n", i); + uint32_t prescaler = Read32(stlink, TPI_ACPR); + if (prescaler) { + uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; + uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; + WLOG("Trace Port Interface configured to expect a %d MHz system clock.\n", system_clock_speed_mhz); + } else { + WLOG("Trace Port Interface not configured. Specify the system clock with a --clock=XX command\n"); + WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); + } + // TODO: Include clock configuration information here. + // TODO: Include TRACE/DEBUG register values here. + WLOG("****\n"); + } +} + int main(int argc, char** argv) { st_settings_t settings; @@ -503,8 +549,9 @@ int main(int argc, char** argv) ILOG("Reading Trace\n"); st_trace_t trace = {}; + trace.start_time = time(NULL); while (!g_done && ReadTrace(stlink, &trace)) { - // TODO: Check that things are roughly working. + CheckForConfigurationError(stlink, &trace); } stlink_trace_disable(stlink); From b8c459fd4bff00ef8bc7718d7b80cb3d706f15ba Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 21:27:29 -0800 Subject: [PATCH 1060/1435] Avoiding duplicating logs for unknown sources. --- src/st-trace/trace.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index b2837dbbe..70e80b49b 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -135,6 +135,7 @@ typedef struct { uint32_t count_error; uint8_t unknown_opcodes[256 / 8]; + uint32_t unknown_sources; } st_trace_t; @@ -364,8 +365,11 @@ static void UpdateTrace(st_trace_t* trace, uint8_t c) { const char* type = TRACE_OP_IS_SW_SOURCE(c) ? "sw" : "hw"; uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); - if (TRACE_OP_IS_SW_SOURCE(c)) - WLOG("Unsupported %s source 0x%x size %d\n", type, addr, size); + if (TRACE_OP_IS_SW_SOURCE(c)) { + if (!(trace->unknown_sources & (1 << addr))) + WLOG("Unsupported %s source 0x%x size %d\n", type, addr, size); + trace->unknown_sources |= (1 << addr); + } trace->state = kSourceSkip[size]; } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { trace->count_time_packets++; @@ -460,6 +464,9 @@ static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace) { for (uint32_t i = 0; i <= 0xFF; i++) if (trace->unknown_opcodes[i / 8] & (1 << i % 8)) WLOG("Unknown Opcode 0x%02x\n", i); + for (uint32_t i = 0; i < 32; i++) + if (trace->unknown_sources & (1 << i)) + WLOG("Unknown Source %d\n", i); uint32_t prescaler = Read32(stlink, TPI_ACPR); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; From 7ceb09dc65a3aee96d84287fc7d4a8fa35a02fe4 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 21:44:26 -0800 Subject: [PATCH 1061/1435] Avoiding reading register from check method as this seems to halt the process. --- src/st-trace/trace.c | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 70e80b49b..2ff90c8d9 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -444,7 +444,7 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { return true; } -static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace) { +static void CheckForConfigurationError(st_trace_t* trace) { uint32_t elapsed_time_s = time(NULL) - trace->start_time; if (trace->configuration_checked || elapsed_time_s < 10) { return; @@ -467,18 +467,9 @@ static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace) { for (uint32_t i = 0; i < 32; i++) if (trace->unknown_sources & (1 << i)) WLOG("Unknown Source %d\n", i); - uint32_t prescaler = Read32(stlink, TPI_ACPR); - if (prescaler) { - uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; - uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; - WLOG("Trace Port Interface configured to expect a %d MHz system clock.\n", system_clock_speed_mhz); - } else { - WLOG("Trace Port Interface not configured. Specify the system clock with a --clock=XX command\n"); - WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); - WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); - } - // TODO: Include clock configuration information here. - // TODO: Include TRACE/DEBUG register values here. + WLOG("Check that the clock frequency is set correctly. Either with the --clock=XX\n"); + WLOG("command line option, or by adding the following to your device's clock initialization:\n"); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); WLOG("****\n"); } } @@ -491,6 +482,7 @@ int main(int argc, char** argv) signal(SIGINT, &cleanup); signal(SIGTERM, &cleanup); signal(SIGSEGV, &cleanup); + signal(SIGPIPE, &cleanup); if (!parse_options(argc, argv, &settings)) { usage(); @@ -558,7 +550,7 @@ int main(int argc, char** argv) st_trace_t trace = {}; trace.start_time = time(NULL); while (!g_done && ReadTrace(stlink, &trace)) { - CheckForConfigurationError(stlink, &trace); + CheckForConfigurationError(&trace); } stlink_trace_disable(stlink); From 2e4c81e2a3552cc7a5db1657b5794507d4b68403 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 22:30:54 -0800 Subject: [PATCH 1062/1435] Was using continouous triggering wrong. --- src/st-trace/trace.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 2ff90c8d9..b4c509063 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -80,8 +80,6 @@ #define TPI_TPI_CSPSR_PORT_SIZE_1 (0x01 << 0) #define TPI_SPPR_SWO_MANCHESTER (0x01 << 0) #define TPI_SPPR_SWO_NRZ (0x02 << 0) -#define TPI_FFCR_EN_F_CONT (0x01 << 1) -#define TPI_FFCR_F_ON_MAN (0x01 << 6) #define TPI_FFCR_TRIG_IN (0x01 << 8) // Other Registers @@ -337,7 +335,7 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); } - Write32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN | TPI_FFCR_EN_F_CONT); + Write32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN); Write32(stlink, TPI_SPPR, TPI_SPPR_SWO_NRZ); Write32(stlink, ITM_LAR, ITM_LAR_KEY); Write32(stlink, ITM_TCC, 0x00000400); // Set sync counter From b88b19287b41e98ece35072ffa94e45a47b13fec Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 30 Nov 2020 22:41:47 -0800 Subject: [PATCH 1063/1435] Flushing stdout after every newline. This is needed for things to run correctly in some scripts. --- src/st-trace/trace.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index b4c509063..a50bef4ef 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -390,6 +390,8 @@ static void UpdateTrace(st_trace_t* trace, uint8_t c) { case TRACE_STATE_TARGET_SOURCE: putchar(c); + if (c == '\n') + fflush(stdout); trace->count_target_data++; trace->state = TRACE_STATE_IDLE; break; From c2356fabac30a0daac176dd0f472d48e7a74ac77 Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 09:22:07 -0800 Subject: [PATCH 1064/1435] Cleaning up code before code review. --- src/st-trace/trace.c | 138 ++++++++++++++++++++++--------------------- 1 file changed, 71 insertions(+), 67 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index a50bef4ef..08775c226 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -38,6 +38,8 @@ #define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) +// TODO: Ideally all register and field definitions would be in a common header file. + // Instrumentation Trace Macrocell (ITM) Registers #define ITM_TER 0xE0000E00 // ITM Trace Enable Register #define ITM_TPR 0xE0000E40 // ITM Trace Privilege Register @@ -83,7 +85,7 @@ #define TPI_FFCR_TRIG_IN (0x01 << 8) // Other Registers -#define FP_CTRL 0xE0002000 // Flash Patch Control Register [WHY DO WE NEED THIS?] +#define FP_CTRL 0xE0002000 // Flash Patch Control Register #define DBGMCU_CR 0xE0042004 // Debug MCU Configuration Register // Other register field definitions @@ -94,8 +96,9 @@ #define DBGMCU_CR_TRACE_IOEN (1 << 5) #define DBGMCU_CR_TRACE_MODE_ASYNC (0x00 << 6) + // We use a global flag to allow communicating to the main thread from the signal handler. -static bool g_done = false; +static bool g_abort_trace = false; typedef struct { @@ -149,8 +152,8 @@ static void usage(void) { puts(" -f, --force Ignore most initialization errors"); } -static void cleanup() { - g_done = true; +static void abort_trace() { + g_abort_trace = true; } bool parse_options(int argc, char** argv, st_settings_t *settings) { @@ -229,19 +232,21 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return true; } +static void ConvertSerialNumberTextToBinary(const char* text, char binary_out[STLINK_SERIAL_MAX_SIZE]) { + size_t length = 0; + for (uint32_t n = 0; n < strlen(text) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { + char buffer[3] = { 0 }; + memcpy(buffer, text + n, 2); + binary_out[length++] = (uint8_t)strtol(buffer, NULL, 16); + } +} + static stlink_t* StLinkConnect(const st_settings_t* settings) { if (settings->serial_number) { - // Convert our serial number string to a binary value. - char serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; - size_t length = 0; - for (uint32_t n = 0; n < strlen(settings->serial_number) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { - char buffer[3] = { 0 }; - memcpy(buffer, settings->serial_number + n, 2); - serial_number[length++] = (uint8_t)strtol(buffer, NULL, 16); - } - // Open this specific stlink. - return stlink_open_usb(settings->logging_level, false, serial_number, 0); + char binary_serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; + ConvertSerialNumberTextToBinary(settings->serial_number, binary_serial_number); + return stlink_open_usb(settings->logging_level, false, binary_serial_number, 0); } else { // Otherwise, open any stlink. return stlink_open_usb(settings->logging_level, false, NULL, 0); @@ -350,76 +355,75 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { return true; } -static void UpdateTrace(st_trace_t* trace, uint8_t c) { - // Parse the input using a state machine. +static trace_state UpdateTraceIdle(st_trace_t* trace, uint8_t c) { + if (TRACE_OP_IS_TARGET_SOURCE(c)) { + return TRACE_STATE_TARGET_SOURCE; + } + if (TRACE_OP_IS_SOURCE(c)) { + uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); + if (TRACE_OP_IS_SW_SOURCE(c)) { + uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); + if (!(trace->unknown_sources & (1 << addr))) + WLOG("Unsupported source 0x%x size %d\n", addr, size); + trace->unknown_sources |= (1 << addr); + } + if (size == 1) return TRACE_STATE_SKIP_1; + if (size == 2) return TRACE_STATE_SKIP_2; + if (size == 3) return TRACE_STATE_SKIP_4; + } + if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + trace->count_time_packets++; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; + } + if (TRACE_OP_IS_EXTENSION(c)) { + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; + } + if (TRACE_OP_IS_OVERFLOW(c)) { + trace->count_overflow++; + } + + if (!(trace->unknown_opcodes[c / 8] & (1 << c % 8))) + WLOG("Unknown opcode 0x%02x\n", c); + trace->unknown_opcodes[c / 8] |= (1 << c % 8); + + trace->count_error++; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; +} + +static trace_state UpdateTrace(st_trace_t* trace, uint8_t c) { trace->count_raw_bytes++; + + // Parse the input using a state machine. switch (trace->state) { case TRACE_STATE_IDLE: - if (TRACE_OP_IS_TARGET_SOURCE(c)) { - trace->state = TRACE_STATE_TARGET_SOURCE; - } else if (TRACE_OP_IS_SOURCE(c)) { - const trace_state kSourceSkip[] = { TRACE_STATE_IDLE, TRACE_STATE_SKIP_1, TRACE_STATE_SKIP_2, TRACE_STATE_SKIP_4 }; - const char* type = TRACE_OP_IS_SW_SOURCE(c) ? "sw" : "hw"; - uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); - uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); - if (TRACE_OP_IS_SW_SOURCE(c)) { - if (!(trace->unknown_sources & (1 << addr))) - WLOG("Unsupported %s source 0x%x size %d\n", type, addr, size); - trace->unknown_sources |= (1 << addr); - } - trace->state = kSourceSkip[size]; - } else if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { - trace->count_time_packets++; - if (TRACE_OP_GET_CONTINUATION(c)) - trace->state = TRACE_STATE_SKIP_FRAME; - } else if (TRACE_OP_IS_EXTENSION(c)) { - if (TRACE_OP_GET_CONTINUATION(c)) - trace->state = TRACE_STATE_SKIP_FRAME; - } else if (TRACE_OP_IS_OVERFLOW(c)) { - trace->count_overflow++; - } else { - if (!(trace->unknown_opcodes[c / 8] & (1 << c % 8))) - WLOG("Unknown opcode 0x%02x\n", c); - trace->unknown_opcodes[c / 8] |= (1 << c % 8); - trace->count_error++; - if (TRACE_OP_GET_CONTINUATION(c)) - trace->state = TRACE_STATE_SKIP_FRAME; - } - break; + return UpdateTraceIdle(trace, c); case TRACE_STATE_TARGET_SOURCE: putchar(c); if (c == '\n') fflush(stdout); trace->count_target_data++; - trace->state = TRACE_STATE_IDLE; - break; + return TRACE_STATE_IDLE; case TRACE_STATE_SKIP_FRAME: - if (TRACE_OP_GET_CONTINUATION(c) == 0) - trace->state = TRACE_STATE_IDLE; - break; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; case TRACE_STATE_SKIP_4: - trace->state = TRACE_STATE_SKIP_3; - break; + return TRACE_STATE_SKIP_3; case TRACE_STATE_SKIP_3: - trace->state = TRACE_STATE_SKIP_2; - break; + return TRACE_STATE_SKIP_2; case TRACE_STATE_SKIP_2: - trace->state = TRACE_STATE_SKIP_1; - break; + return TRACE_STATE_SKIP_1; case TRACE_STATE_SKIP_1: - trace->state = TRACE_STATE_IDLE; - break; + return TRACE_STATE_IDLE; default: ELOG("Invalid state %d. This should never happen\n", trace->state); - trace->state = TRACE_STATE_IDLE; + return TRACE_STATE_IDLE; } } @@ -438,7 +442,7 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { } for (int i = 0; i < length; i++) { - UpdateTrace(trace, buffer[i]); + trace->state = UpdateTrace(trace, buffer[i]); } return true; @@ -479,10 +483,10 @@ int main(int argc, char** argv) st_settings_t settings; stlink_t* stlink = NULL; - signal(SIGINT, &cleanup); - signal(SIGTERM, &cleanup); - signal(SIGSEGV, &cleanup); - signal(SIGPIPE, &cleanup); + signal(SIGINT, &abort_trace); + signal(SIGTERM, &abort_trace); + signal(SIGSEGV, &abort_trace); + signal(SIGPIPE, &abort_trace); if (!parse_options(argc, argv, &settings)) { usage(); @@ -549,7 +553,7 @@ int main(int argc, char** argv) ILOG("Reading Trace\n"); st_trace_t trace = {}; trace.start_time = time(NULL); - while (!g_done && ReadTrace(stlink, &trace)) { + while (!g_abort_trace && ReadTrace(stlink, &trace)) { CheckForConfigurationError(&trace); } From 793088f4389acf6a3883a3667d7e5fb9cb9a3d76 Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 10:25:55 -0800 Subject: [PATCH 1065/1435] Updating to use chip flags instead of multiple boolean values. --- inc/stlink.h | 2 +- src/common.c | 4 ++-- src/stlink-lib/chipid.c | 2 +- src/stlink-lib/chipid.h | 5 ++++- 4 files changed, 8 insertions(+), 5 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 1c9f6b09a..c369a133a 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -217,7 +217,7 @@ struct _stlink { enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx - bool has_dual_bank; + uint32_t chip_flags; stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() size_t flash_size; // calculated by stlink_load_device_params() diff --git a/src/common.c b/src/common.c index bda2ccf87..0325c85f9 100644 --- a/src/common.c +++ b/src/common.c @@ -868,7 +868,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); } @@ -1363,7 +1363,7 @@ int stlink_load_device_params(stlink_t *sl) { } sl->flash_type = params->flash_type; - sl->has_dual_bank = params->has_dual_bank; + sl->chip_flags = params->flags; sl->flash_pgsz = params->flash_pagesize; sl->sram_size = params->sram_size; sl->sys_base = params->bootrom_base; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index a8d160445..ca35c887e 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -593,7 +593,7 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_G4_CAT3, .description = "G4 Category-3", .flash_type = STLINK_FLASH_TYPE_G4, - .has_dual_bank = true, + .flags = CHIP_F_HAS_DUAL_BANK, .flash_size_reg = 0x1FFF75E0, // Section 47.2 .flash_pagesize = 0x800, // 2k (sec 3.3.1) // SRAM1 is 80k at 0x20000000 diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f717022ca..1573b182e 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -67,12 +67,15 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_WB55 = 0x495 }; +#define CHIP_F_HAS_DUAL_BANK (1 << 0) +#define CHIP_F_HAS_SWO_TRACING (1 << 1) + /** Chipid parameters */ struct stlink_chipid_params { uint32_t chip_id; char *description; enum stlink_flash_type flash_type; - bool has_dual_bank; + uint32_t flags; uint32_t flash_size_reg; uint32_t flash_pagesize; uint32_t sram_size; From 660dee303cd1d1dcab8bea5684d31a99dacb414c Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 10:41:40 -0800 Subject: [PATCH 1066/1435] Moved chip trace support into chipid where it belongs. --- src/st-trace/trace.c | 26 +--------- src/stlink-lib/chipid.c | 104 +++++++++++++++++++++++++++------------- 2 files changed, 73 insertions(+), 57 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 08775c226..b8a9f88cb 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -253,30 +253,6 @@ static stlink_t* StLinkConnect(const st_settings_t* settings) { } } -static bool IsDeviceTraceSupported(int chip_id) { - // TODO: Consider moving this to a flag in the device table. - switch (chip_id) { - case STLINK_CHIPID_STM32_F4: - case STLINK_CHIPID_STM32_F4_DSI: - case STLINK_CHIPID_STM32_F4_HD: - case STLINK_CHIPID_STM32_F4_LP: - case STLINK_CHIPID_STM32_F411RE: - case STLINK_CHIPID_STM32_F4_DE: - case STLINK_CHIPID_STM32_F446: - case STLINK_CHIPID_STM32_F410: - case STLINK_CHIPID_STM32_F3: - case STLINK_CHIPID_STM32_F37x: - case STLINK_CHIPID_STM32_F412: - case STLINK_CHIPID_STM32_F413: - case STLINK_CHIPID_STM32_F3_SMALL: - case STLINK_CHIPID_STM32_F334: - case STLINK_CHIPID_STM32_F303_HIGH: - return true; - default: - return false; - } -} - static void Write32(stlink_t* stlink, uint32_t address, uint32_t data) { write_uint32(stlink->q_buf, data); if (stlink_write_mem32(stlink, address, 4)) { @@ -531,7 +507,7 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_UNSUPPORTED_LINK; } - if (!IsDeviceTraceSupported(stlink->chip_id)) { + if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); ELOG("We do not support SWO output for device '%s'\n", params->description); if (!settings.force) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index ca35c887e..d136384f9 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -13,7 +13,8 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x00200000, // ! "System memory" starting address from .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 - .option_size = 0x20 + .option_size = 0x20, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // RM0385 and DS10916 document was used to find these paramaters @@ -24,7 +25,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // No flash pages .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 18 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 + .flags = CHIP_F_HAS_SWO_TRACING, }, { // RM0431 and DS document was used to find these paramaters @@ -35,7 +37,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // No flash pages .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = 0xEDC0 // "System memory" byte size in hex from DS Fig 24 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 + .flags = CHIP_F_HAS_SWO_TRACING, }, { // table 2, PM0063 .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, @@ -45,7 +48,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x400, .sram_size = 0x5000, .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .bootrom_size = 0x800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // table 1, PM0059 .chip_id = STLINK_CHIPID_STM32_F2, @@ -58,6 +62,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = 0x1FFFC000, .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // PM0063 .chip_id = STLINK_CHIPID_STM32_F1_LOW, @@ -67,7 +72,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x400, .sram_size = 0x2800, .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .bootrom_size = 0x800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4, @@ -80,6 +86,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = STM32_F4_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_DSI, @@ -89,7 +96,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, .sram_size = 0x40000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_HD, @@ -99,7 +107,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, .sram_size = 0x40000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_LP, @@ -109,7 +118,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, .sram_size = 0x10000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F411RE, @@ -119,7 +129,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, .sram_size = 0x20000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_DE, @@ -129,7 +140,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, .sram_size = 0x18000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_HIGH, @@ -139,7 +151,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0x10000, .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .bootrom_size = 0x800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This ignores the EEPROM! (and uses the page erase size, @@ -151,7 +164,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x100, .sram_size = 0x4000, .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L1_CAT2, @@ -161,7 +175,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x100, .sram_size = 0x8000, .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, @@ -171,7 +186,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x100, .sram_size = 0x8000, // not completely clear if there are some with 48k .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L1_HIGH, @@ -184,6 +200,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x1000, .option_base = STM32_L1_OPTION_BYTES_BASE, .option_size = 8, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L152_RE, @@ -193,7 +210,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x100, .sram_size = 0x14000, // not completely clear if there are some with 32k .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000 + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_CONN, @@ -203,7 +221,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0x10000, .bootrom_base = 0x1fffb000, - .bootrom_size = 0x4800 + .bootrom_size = 0x4800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // Low and Medium density VL have same chipid. RM0041 25.6.1 .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, @@ -213,7 +232,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x400, .sram_size = 0x2000, // 0x1000 for low density devices .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .bootrom_size = 0x800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. @@ -227,6 +247,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = 0x1FFFC000, .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. @@ -237,7 +258,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, .sram_size = 0x8000, .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800 + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This is STK32F303VCT6 device from STM32 F3 Discovery board. @@ -249,7 +271,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0xa000, .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .bootrom_size = 0x800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This is STK32F373VCT6 device from STM32 F373 eval board @@ -261,7 +284,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0xa000, .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .bootrom_size = 0x800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, @@ -271,7 +295,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0x8000, .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800 + .bootrom_size = 0x800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_XL, @@ -281,7 +306,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0x18000, .bootrom_base = 0x1fffe000, - .bootrom_size = 0x1800 + .bootrom_size = 0x1800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // Use this as an example for mapping future chips: @@ -317,7 +343,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, // Table 5. Flash module organization ? .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + .flags = CHIP_F_HAS_SWO_TRACING, }, { // RM0430 DocID029473 Rev 2 document was used to find these parameters @@ -329,7 +356,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector sizes, but 0x4000 is smallest) .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 only says 0x40000) .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800 // "System memory" byte size in hex from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F09X, @@ -374,7 +402,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0xa000, .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000 + .bootrom_size = 0x2000, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L0x @@ -428,7 +457,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, .sram_size = 0x3000, .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000 + .bootrom_size = 0x2000, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This is STK32F303RET6 device from STM32 F3 Nucelo board. @@ -440,7 +470,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // 4.2.1 Flash memory organization .sram_size = 0x10000, // 3.3 Embedded SRAM .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory - .bootrom_size = 0x2000 + .bootrom_size = 0x2000, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L4x6 @@ -459,6 +490,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L4RX @@ -470,7 +502,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x1000, // 4k, section 3.3, pg 97 .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 - .bootrom_size = 0x7000 // 28k (per bank), same source as base (pg 99) + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 99) + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L41X @@ -484,7 +517,8 @@ static const struct stlink_chipid_params devices[] = { // SRAM2 is 8k at 0x10000000 and 0x20008000 (DS12469, sec 3.5, page 18) .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000 // 28k, same source as base + .bootrom_size = 0x7000, // 28k, same source as base + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L43X @@ -503,6 +537,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L496X @@ -519,6 +554,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L46X @@ -533,7 +569,8 @@ static const struct stlink_chipid_params devices[] = { // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, page 68, also fig 2 on page 63) .sram_size = 0x20000, .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system memory, also fig 2 on page 63) - .bootrom_size = 0x7000 // 28k (per bank), same source as base + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L011 @@ -587,13 +624,13 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32G471/473/474/483/484 (from RM0440) .chip_id = STLINK_CHIPID_STM32_G4_CAT3, .description = "G4 Category-3", .flash_type = STLINK_FLASH_TYPE_G4, - .flags = CHIP_F_HAS_DUAL_BANK, .flash_size_reg = 0x1FFF75E0, // Section 47.2 .flash_pagesize = 0x800, // 2k (sec 3.3.1) // SRAM1 is 80k at 0x20000000 @@ -604,6 +641,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { // STM32WB55 (from RM0434) @@ -628,6 +666,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 + .flags = CHIP_F_HAS_SWO_TRACING, }, { // unknown @@ -638,7 +677,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x0, .sram_size = 0x0, .bootrom_base = 0x0, - .bootrom_size = 0x0 + .bootrom_size = 0x0, + .flags = 0, }, }; From ce7f0a157c1b66216c03977bd1e55291033b1d97 Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 10:56:40 -0800 Subject: [PATCH 1067/1435] One last cleanup before I feel this code is ready to submit for CR. --- src/st-trace/trace.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index b8a9f88cb..379c4cec1 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -97,10 +97,6 @@ #define DBGMCU_CR_TRACE_MODE_ASYNC (0x00 << 6) -// We use a global flag to allow communicating to the main thread from the signal handler. -static bool g_abort_trace = false; - - typedef struct { bool show_help; bool show_version; @@ -140,6 +136,13 @@ typedef struct { } st_trace_t; +// We use a global flag to allow communicating to the main thread from the signal handler. +static bool g_abort_trace = false; + +static void abort_trace() { + g_abort_trace = true; +} + static void usage(void) { puts("st-trace - usage:"); puts(" -h, --help Print this help"); @@ -152,10 +155,6 @@ static void usage(void) { puts(" -f, --force Ignore most initialization errors"); } -static void abort_trace() { - g_abort_trace = true; -} - bool parse_options(int argc, char** argv, st_settings_t *settings) { static struct option long_options[] = { @@ -332,9 +331,12 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { } static trace_state UpdateTraceIdle(st_trace_t* trace, uint8_t c) { + // Handle a trace byte when we are in the idle state. + if (TRACE_OP_IS_TARGET_SOURCE(c)) { return TRACE_STATE_TARGET_SOURCE; } + if (TRACE_OP_IS_SOURCE(c)) { uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); if (TRACE_OP_IS_SW_SOURCE(c)) { @@ -347,13 +349,16 @@ static trace_state UpdateTraceIdle(st_trace_t* trace, uint8_t c) { if (size == 2) return TRACE_STATE_SKIP_2; if (size == 3) return TRACE_STATE_SKIP_4; } + if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { trace->count_time_packets++; return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; } + if (TRACE_OP_IS_EXTENSION(c)) { return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; } + if (TRACE_OP_IS_OVERFLOW(c)) { trace->count_overflow++; } From 4f762501c2c333aacc3e143fd0549bbe16c442e4 Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 12:08:29 -0800 Subject: [PATCH 1068/1435] Using debug instead of write. Fixing buffer semantics. --- inc/stlink.h | 2 +- src/st-trace/trace.c | 83 +++++++++++++++++++------------------------- src/stlink-lib/usb.c | 6 ++-- 3 files changed, 40 insertions(+), 51 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index c369a133a..d40fdbb71 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -83,7 +83,7 @@ enum target_state { #define STLINK_V3_MAX_FREQ_NB 10 -#define STLINK_TRACE_BUF_LEN 4096 +#define STLINK_TRACE_BUF_LEN 2048 #define STLINK_TRACE_FREQUENCY 2000000 /* Cortex Debug Control Block */ diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 379c4cec1..868334e49 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -252,20 +252,6 @@ static stlink_t* StLinkConnect(const st_settings_t* settings) { } } -static void Write32(stlink_t* stlink, uint32_t address, uint32_t data) { - write_uint32(stlink->q_buf, data); - if (stlink_write_mem32(stlink, address, 4)) { - ELOG("Unable to set address 0x%08x to 0x%08x\n", address, data); - } -} - -static uint32_t Read32(stlink_t* stlink, uint32_t address) { - if (stlink_read_mem32(stlink, address, 4)) { - ELOG("Unable to read from address 0x%08x\n", address); - } - return read_uint32(stlink->q_buf, 0); -} - static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { if (stlink_force_debug(stlink)) { @@ -274,23 +260,23 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { return false; } - if (settings->reset_board && stlink_reset(stlink)) { + if (settings->reset_board && stlink_jtag_reset(stlink, 2)) { ELOG("Unable to reset device\n"); if (!settings->force) return false; } - Write32(stlink, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); - Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); - Write32(stlink, FP_CTRL, FP_CTRL_KEY); - Write32(stlink, DWT_FUNCTION0, 0); - Write32(stlink, DWT_FUNCTION1, 0); - Write32(stlink, DWT_FUNCTION2, 0); - Write32(stlink, DWT_FUNCTION3, 0); - Write32(stlink, DWT_CTRL, 0); - Write32(stlink, DBGMCU_CR, DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP | - DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_TRACE_IOEN | - DBGMCU_CR_TRACE_MODE_ASYNC); // Enable async tracing + stlink_write_debug32(stlink, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); + stlink_write_debug32(stlink, DCB_DEMCR, DEMCR_TRCENA); + stlink_write_debug32(stlink, FP_CTRL, FP_CTRL_KEY); + stlink_write_debug32(stlink, DWT_FUNCTION0, 0); + stlink_write_debug32(stlink, DWT_FUNCTION1, 0); + stlink_write_debug32(stlink, DWT_FUNCTION2, 0); + stlink_write_debug32(stlink, DWT_FUNCTION3, 0); + stlink_write_debug32(stlink, DWT_CTRL, 0); + stlink_write_debug32(stlink, DBGMCU_CR, DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP | + DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_TRACE_IOEN | + DBGMCU_CR_TRACE_MODE_ASYNC); // Enable async tracing if (stlink_trace_enable(stlink)) { ELOG("Unable to turn on tracing in stlink\n"); @@ -298,13 +284,26 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { return false; } - Write32(stlink, TPI_CSPSR, TPI_TPI_CSPSR_PORT_SIZE_1); + stlink_write_debug32(stlink, TPI_CSPSR, TPI_TPI_CSPSR_PORT_SIZE_1); if (settings->core_frequency_mhz) { uint32_t prescaler = settings->core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; - Write32(stlink, TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor - } - uint32_t prescaler = Read32(stlink, TPI_ACPR); + stlink_write_debug32(stlink, TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor + } + stlink_write_debug32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN); + stlink_write_debug32(stlink, TPI_SPPR, TPI_SPPR_SWO_NRZ); + stlink_write_debug32(stlink, ITM_LAR, ITM_LAR_KEY); + stlink_write_debug32(stlink, ITM_TCC, 0x00000400); // Set sync counter + stlink_write_debug32(stlink, ITM_TCR, ITM_TCR_TRACE_BUS_ID_1 | ITM_TCR_TS_ENA | ITM_TCR_ITM_ENA); + stlink_write_debug32(stlink, ITM_TER, ITM_TER_PORTS_ALL); + stlink_write_debug32(stlink, ITM_TPR, ITM_TPR_PORTS_ALL); + stlink_write_debug32(stlink, DWT_CTRL, 4 * DWT_CTRL_NUM_COMP | DWT_CTRL_CYC_TAP | + 0xF * DWT_CTRL_POST_INIT | 0xF * DWT_CTRL_POST_PRESET | + DWT_CTRL_CYCCNT_ENA); + stlink_write_debug32(stlink, DCB_DEMCR, DEMCR_TRCENA); + + uint32_t prescaler; + stlink_read_debug32(stlink, TPI_ACPR, &prescaler); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; @@ -312,21 +311,9 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { } else { WLOG("Trace Port Interface not configured. Specify the system clock with a --clock=XX command\n"); WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); - WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", STLINK_TRACE_FREQUENCY); } - Write32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN); - Write32(stlink, TPI_SPPR, TPI_SPPR_SWO_NRZ); - Write32(stlink, ITM_LAR, ITM_LAR_KEY); - Write32(stlink, ITM_TCC, 0x00000400); // Set sync counter - Write32(stlink, ITM_TCR, ITM_TCR_TRACE_BUS_ID_1 | ITM_TCR_TS_ENA | ITM_TCR_ITM_ENA); - Write32(stlink, ITM_TER, ITM_TER_PORTS_ALL); - Write32(stlink, ITM_TPR, ITM_TPR_PORTS_ALL); - Write32(stlink, DWT_CTRL, 4 * DWT_CTRL_NUM_COMP | DWT_CTRL_CYC_TAP | - 0xF * DWT_CTRL_POST_INIT | 0xF * DWT_CTRL_POST_PRESET | - DWT_CTRL_CYCCNT_ENA); - Write32(stlink, DCB_DEMCR, DEMCR_TRCENA); - return true; } @@ -417,8 +404,9 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { return false; } + DLOG("Trace Length %d\n", length); if (length == 0) { - usleep(1000); // Our buffer could fill in around 2ms, so sleep half that. + // usleep(100); return true; } @@ -525,15 +513,16 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_STATE_ERROR; } + ILOG("Reading Trace\n"); + st_trace_t trace = {}; + trace.start_time = time(NULL); + if (stlink_run(stlink)) { ELOG("Unable to run device\n"); if (!settings.force) return APP_RESULT_STLINK_STATE_ERROR; } - ILOG("Reading Trace\n"); - st_trace_t trace = {}; - trace.start_time = time(NULL); while (!g_abort_trace && ReadTrace(stlink, &trace)) { CheckForConfigurationError(&trace); } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index db187acc5..5b84bb36a 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -982,7 +982,7 @@ int _stlink_usb_enable_trace(stlink_t* sl) { int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; - write_uint16(&cmd[i + 0], STLINK_TRACE_BUF_LEN); + write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); write_uint32(&cmd[i + 2], STLINK_TRACE_FREQUENCY); size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); @@ -1053,8 +1053,8 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { int res = 0; int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); - if (t) { - ELOG("read_trace read error\n"); + if (t || res != trace_count) { + ELOG("read_trace read error %d\n", t); return(-1); } } From aaaae8a61c3bbe4753c85cbff4830fcade9bd462 Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 13:05:19 -0800 Subject: [PATCH 1069/1435] Minor change didn't compile. --- src/stlink-lib/usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 5b84bb36a..97b616532 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1053,7 +1053,7 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { int res = 0; int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); - if (t || res != trace_count) { + if (t || res != (int)trace_count) { ELOG("read_trace read error %d\n", t); return(-1); } From ac104ebabea7ad796eff2e6ebe88f22d113aeafe Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 13:47:04 -0800 Subject: [PATCH 1070/1435] Allowed configuring trace frequency. --- inc/backend.h | 2 +- inc/stlink.h | 9 ++++-- src/common.c | 6 ++-- src/st-trace/trace.c | 67 +++++++++++++++++++++++++++++--------------- src/stlink-lib/usb.c | 4 +-- 5 files changed, 57 insertions(+), 31 deletions(-) diff --git a/inc/backend.h b/inc/backend.h index 470702fde..70b3b739f 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -29,7 +29,7 @@ int (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); int (*set_swdclk) (stlink_t * stl, uint16_t divisor); - int (*trace_enable) (stlink_t * sl); + int (*trace_enable) (stlink_t * sl, uint32_t frequency); int (*trace_disable) (stlink_t * sl); int (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); diff --git a/inc/stlink.h b/inc/stlink.h index d40fdbb71..653b48e44 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -83,8 +83,10 @@ enum target_state { #define STLINK_V3_MAX_FREQ_NB 10 -#define STLINK_TRACE_BUF_LEN 2048 -#define STLINK_TRACE_FREQUENCY 2000000 +#define STLINK_TRACE_BUF_LEN 2048 +#define STLINK_V2_MAX_TRACE_FREQUENCY 2000000 +#define STLINK_V3_MAX_TRACE_FREQUENCY 24000000 +#define STLINK_DEFAULT_TRACE_FREQUENCY 2000000 /* Cortex Debug Control Block */ #define DCB_DHCSR 0xE000EDF0 @@ -214,6 +216,7 @@ struct _stlink { char serial[STLINK_SERIAL_MAX_SIZE]; int serial_size; int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR + uint32_t max_trace_freq; // set by stlink_open_usb() enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx @@ -267,7 +270,7 @@ int stlink_current_mode(stlink_t *sl); int stlink_force_debug(stlink_t *sl); int stlink_target_voltage(stlink_t *sl); int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); -int stlink_trace_enable(stlink_t* sl); +int stlink_trace_enable(stlink_t* sl, uint32_t frequency); int stlink_trace_disable(stlink_t* sl); int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); diff --git a/src/common.c b/src/common.c index 0325c85f9..ac78db089 100644 --- a/src/common.c +++ b/src/common.c @@ -1468,6 +1468,7 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { if (sl->version.jtag_v >= 13) { sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V2_MAX_TRACE_FREQUENCY; } } } else { @@ -1483,6 +1484,7 @@ void _parse_version(stlink_t *sl, stlink_version_t *slv) { /* preferred API to get last R/W status */ sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V3_MAX_TRACE_FREQUENCY; } return; @@ -1682,9 +1684,9 @@ int stlink_current_mode(stlink_t *sl) { return(STLINK_DEV_UNKNOWN_MODE); } -int stlink_trace_enable(stlink_t* sl) { +int stlink_trace_enable(stlink_t* sl, uint32_t frequency) { DLOG("*** stlink_trace_enable ***\n"); - return(sl->backend->trace_enable(sl)); + return(sl->backend->trace_enable(sl, frequency)); } int stlink_trace_disable(stlink_t* sl) { diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 868334e49..fe4e20fdc 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -22,7 +22,8 @@ #define APP_RESULT_STLINK_MISSING_DEVICE 3 #define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 #define APP_RESULT_STLINK_UNSUPPORTED_LINK 5 -#define APP_RESULT_STLINK_STATE_ERROR 6 +#define APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY 6 +#define APP_RESULT_STLINK_STATE_ERROR 7 // See D4.2 of https://developer.arm.com/documentation/ddi0403/ed/ #define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) @@ -98,13 +99,14 @@ typedef struct { - bool show_help; - bool show_version; - int logging_level; - int core_frequency_mhz; - bool reset_board; - bool force; - char* serial_number; + bool show_help; + bool show_version; + int logging_level; + uint32_t core_frequency; + uint32_t trace_frequency; + bool reset_board; + bool force; + char* serial_number; } st_settings_t; @@ -150,6 +152,7 @@ static void usage(void) { puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); puts(" -v, --verbose Specify a generally verbose logging"); puts(" -cXX, --clock=XX Specify the core frequency in MHz"); + puts(" -tXX, --trace=XX Specify the trace frequency in Hz"); puts(" -n, --no-reset Do not reset board on connection"); puts(" -sXX, --serial=XX Use a specific serial number"); puts(" -f, --force Ignore most initialization errors"); @@ -162,6 +165,7 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { {"version", no_argument, NULL, 'V'}, {"verbose", optional_argument, NULL, 'v'}, {"clock", required_argument, NULL, 'c'}, + {"trace", required_argument, NULL, 't'}, {"no-reset", no_argument, NULL, 'n'}, {"serial", required_argument, NULL, 's'}, {"force", no_argument, NULL, 'f'}, @@ -174,7 +178,8 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { settings->show_help = false; settings->show_version = false; settings->logging_level = DEFAULT_LOGGING_LEVEL; - settings->core_frequency_mhz = 0; + settings->core_frequency = 0; + settings->trace_frequency = 0; settings->reset_board = true; settings->force = false; settings->serial_number = NULL; @@ -197,7 +202,10 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { ugly_init(settings->logging_level); break; case 'c': - settings->core_frequency_mhz = atoi(optarg); + settings->core_frequency = atoi(optarg) * 1000000; + break; + case 't': + settings->trace_frequency = atoi(optarg); break; case 'n': settings->reset_board = false; @@ -252,7 +260,7 @@ static stlink_t* StLinkConnect(const st_settings_t* settings) { } } -static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { +static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings, uint32_t trace_frequency) { if (stlink_force_debug(stlink)) { ELOG("Unable to debug device\n"); @@ -278,7 +286,8 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_ASYNC); // Enable async tracing - if (stlink_trace_enable(stlink)) { + DLOG("Setting trace frequency to %d Hz.\n", trace_frequency); + if (stlink_trace_enable(stlink, trace_frequency)) { ELOG("Unable to turn on tracing in stlink\n"); if (!settings->force) return false; @@ -286,8 +295,8 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { stlink_write_debug32(stlink, TPI_CSPSR, TPI_TPI_CSPSR_PORT_SIZE_1); - if (settings->core_frequency_mhz) { - uint32_t prescaler = settings->core_frequency_mhz * 1000000 / STLINK_TRACE_FREQUENCY - 1; + if (settings->core_frequency) { + uint32_t prescaler = settings->core_frequency / trace_frequency - 1; stlink_write_debug32(stlink, TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor } stlink_write_debug32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN); @@ -305,13 +314,13 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings) { uint32_t prescaler; stlink_read_debug32(stlink, TPI_ACPR, &prescaler); if (prescaler) { - uint32_t system_clock_speed = (prescaler + 1) * STLINK_TRACE_FREQUENCY; + uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", system_clock_speed_mhz); } else { WLOG("Trace Port Interface not configured. Specify the system clock with a --clock=XX command\n"); WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); - WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", STLINK_TRACE_FREQUENCY); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); } return true; @@ -404,12 +413,14 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { return false; } - DLOG("Trace Length %d\n", length); if (length == 0) { - // usleep(100); + usleep(100); return true; } + if (length == sizeof(buffer)) { + } + for (int i = 0; i < length; i++) { trace->state = UpdateTrace(trace, buffer[i]); } @@ -417,7 +428,7 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { return true; } -static void CheckForConfigurationError(st_trace_t* trace) { +static void CheckForConfigurationError(st_trace_t* trace, uint32_t trace_frequency) { uint32_t elapsed_time_s = time(NULL) - trace->start_time; if (trace->configuration_checked || elapsed_time_s < 10) { return; @@ -442,7 +453,7 @@ static void CheckForConfigurationError(st_trace_t* trace) { WLOG("Unknown Source %d\n", i); WLOG("Check that the clock frequency is set correctly. Either with the --clock=XX\n"); WLOG("command line option, or by adding the following to your device's clock initialization:\n"); - WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / 2000000 - 1;\n"); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); WLOG("****\n"); } } @@ -465,7 +476,8 @@ int main(int argc, char** argv) DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); DLOG("logging_level = %d\n", settings.logging_level); - DLOG("core_frequency = %d MHz\n", settings.core_frequency_mhz); + DLOG("core_frequency = %d Hz\n", settings.core_frequency); + DLOG("trace_frequency = %d Hz\n", settings.trace_frequency); DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); DLOG("force = %s\n", settings.force ? "true" : "false"); DLOG("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); @@ -507,7 +519,16 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; } - if (!EnableTrace(stlink, &settings)) { + uint32_t trace_frequency = settings.trace_frequency; + if (!trace_frequency) + trace_frequency = STLINK_DEFAULT_TRACE_FREQUENCY; + if (trace_frequency > stlink->max_trace_freq) { + ELOG("Invalid trace frequency %d (max %d)\n", trace_frequency, stlink->max_trace_freq); + if (!settings.force) + return APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY; + } + + if (!EnableTrace(stlink, &settings, trace_frequency)) { ELOG("Unable to enable trace mode\n"); if (!settings.force) return APP_RESULT_STLINK_STATE_ERROR; @@ -524,7 +545,7 @@ int main(int argc, char** argv) } while (!g_abort_trace && ReadTrace(stlink, &trace)) { - CheckForConfigurationError(&trace); + CheckForConfigurationError(&trace, trace_frequency); } stlink_trace_disable(stlink); diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 97b616532..db11968a6 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -972,7 +972,7 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { return(0); } -int _stlink_usb_enable_trace(stlink_t* sl) { +int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -983,7 +983,7 @@ int _stlink_usb_enable_trace(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); - write_uint32(&cmd[i + 2], STLINK_TRACE_FREQUENCY); + write_uint32(&cmd[i + 2], frequency); size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); From a331da4df3e539c39820a4404b3a2f4ee591df84 Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 15:54:40 -0800 Subject: [PATCH 1071/1435] Improving diagnostics, especially for sw buffer overruns. --- src/st-trace/trace.c | 88 +++++++++++++++++++++++++++++++------------- 1 file changed, 62 insertions(+), 26 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index fe4e20fdc..f82a804c6 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -130,7 +130,8 @@ typedef struct { uint32_t count_raw_bytes; uint32_t count_target_data; uint32_t count_time_packets; - uint32_t count_overflow; + uint32_t count_hw_overflow; + uint32_t count_sw_overflow; uint32_t count_error; uint8_t unknown_opcodes[256 / 8]; @@ -356,7 +357,7 @@ static trace_state UpdateTraceIdle(st_trace_t* trace, uint8_t c) { } if (TRACE_OP_IS_OVERFLOW(c)) { - trace->count_overflow++; + trace->count_hw_overflow++; } if (!(trace->unknown_opcodes[c / 8] & (1 << c % 8))) @@ -419,6 +420,10 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { } if (length == sizeof(buffer)) { + if (trace->count_sw_overflow++) + DLOG("Buffer overflow.\n"); + else + WLOG("Buffer overflow. Try using a slower trace frequency.\n"); } for (int i = 0; i < length; i++) { @@ -428,7 +433,8 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { return true; } -static void CheckForConfigurationError(st_trace_t* trace, uint32_t trace_frequency) { +static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace, uint32_t trace_frequency) { + // Only check configuration one time after the first 10 seconds of running. uint32_t elapsed_time_s = time(NULL) - trace->start_time; if (trace->configuration_checked || elapsed_time_s < 10) { return; @@ -436,38 +442,68 @@ static void CheckForConfigurationError(st_trace_t* trace, uint32_t trace_frequen trace->configuration_checked = true; // Simple huristic to determine if we are configured poorly. - if (trace->count_raw_bytes < 100 || trace->count_error > 1 || trace->count_time_packets < 10) { - // Output Diagnostic Information - WLOG("****\n"); - WLOG("We do not appear to be retrieving data from the stlink correctly.\n"); - WLOG("Raw Bytes: %d\n", trace->count_raw_bytes); - WLOG("Target Data: %d\n", trace->count_target_data); - WLOG("Time Packets: %d\n", trace->count_time_packets); - WLOG("Overlow Count: %d\n", trace->count_overflow); - WLOG("Errors: %d\n", trace->count_error); - for (uint32_t i = 0; i <= 0xFF; i++) - if (trace->unknown_opcodes[i / 8] & (1 << i % 8)) - WLOG("Unknown Opcode 0x%02x\n", i); - for (uint32_t i = 0; i < 32; i++) - if (trace->unknown_sources & (1 << i)) - WLOG("Unknown Source %d\n", i); - WLOG("Check that the clock frequency is set correctly. Either with the --clock=XX\n"); - WLOG("command line option, or by adding the following to your device's clock initialization:\n"); + bool error_no_data = (trace->count_raw_bytes < 100); + bool error_bad_data = (trace->count_error > 1 || trace->count_time_packets < 10 || trace->unknown_sources > 0); + bool error_dropped_data = (trace->count_sw_overflow > 0); + + if (!error_no_data && !error_bad_data && !error_dropped_data) + return; + + WLOG("****\n"); + WLOG("We do not appear to be retrieving data from the stlink correctly.\n"); + + if (error_dropped_data) { + WLOG("Try setting a slower trace frequency with the --trace=%d command line option.\n", trace_frequency / 2); + } + + if (error_no_data || error_bad_data) { + uint32_t prescaler; + stlink_read_debug32(stlink, TPI_ACPR, &prescaler); + if (prescaler) { + uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; + uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; + WLOG("Verify the system clock is running at %d MHz.\n", system_clock_speed_mhz); + } + WLOG("Try specifying the system clock with the --clock=XX command line option.\n"); + WLOG("Try setting the trace speed in your device's clock initialization routine:\n"); WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); - WLOG("****\n"); } + + WLOG("Diagnostic Information:\n"); + WLOG("Raw Bytes: %d\n", trace->count_raw_bytes); + WLOG("Target Data: %d\n", trace->count_target_data); + WLOG("Time Packets: %d\n", trace->count_time_packets); + WLOG("Hardware Overflow Count: %d\n", trace->count_hw_overflow); + WLOG("Software Overflow Count: %d\n", trace->count_sw_overflow); + WLOG("Errors: %d\n", trace->count_error); + + char buffer[1024]; + memset(buffer, 0, sizeof(buffer)); + uint32_t offset = 0; + for (uint32_t i = 0; i <= 0xFF; i++) + if (trace->unknown_opcodes[i / 8] & (1 << i % 8)) + offset += snprintf(buffer + offset, sizeof(buffer) - offset, "%02x, ", i); + WLOG("Unknown Opcodes: %s\n", buffer); + + memset(buffer, 0, sizeof(buffer)); + offset = 0; + for (uint32_t i = 0; i < 32; i++) + if (trace->unknown_sources & (1 << i)) + offset += snprintf(buffer + offset, sizeof(buffer) - offset, "%d, ", i); + WLOG("Unknown Sources: %s\n", buffer); + + WLOG("Chip ID: 0x%04x\n", stlink->chip_id); + WLOG("****\n"); } int main(int argc, char** argv) { - st_settings_t settings; - stlink_t* stlink = NULL; - signal(SIGINT, &abort_trace); signal(SIGTERM, &abort_trace); signal(SIGSEGV, &abort_trace); signal(SIGPIPE, &abort_trace); + st_settings_t settings; if (!parse_options(argc, argv, &settings)) { usage(); return APP_RESULT_INVALID_PARAMS; @@ -492,7 +528,7 @@ int main(int argc, char** argv) return APP_RESULT_SUCCESS; } - stlink = StLinkConnect(&settings); + stlink_t* stlink = StLinkConnect(&settings); if (!stlink) { ELOG("Unable to locate an stlink\n"); return APP_RESULT_STLINK_NOT_FOUND; @@ -545,7 +581,7 @@ int main(int argc, char** argv) } while (!g_abort_trace && ReadTrace(stlink, &trace)) { - CheckForConfigurationError(&trace, trace_frequency); + CheckForConfigurationError(stlink, &trace, trace_frequency); } stlink_trace_disable(stlink); From 57f1bc791112ce2cacb3481484747b6332b537fa Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 16:28:10 -0800 Subject: [PATCH 1072/1435] Making sure TPI async prescalar is within the available range. Trying to recover from buffer overruns where we may land in the middle of trace output. --- src/st-trace/trace.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index f82a804c6..8368cee34 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -84,6 +84,7 @@ #define TPI_SPPR_SWO_MANCHESTER (0x01 << 0) #define TPI_SPPR_SWO_NRZ (0x02 << 0) #define TPI_FFCR_TRIG_IN (0x01 << 8) +#define TPI_ACPR_MAX (0x1FFF) // Other Registers #define FP_CTRL 0xE0002000 // Flash Patch Control Register @@ -112,6 +113,7 @@ typedef struct { // We use a simple state machine to parse the trace data. typedef enum { + TRACE_STATE_UNKNOWN, TRACE_STATE_IDLE, TRACE_STATE_TARGET_SOURCE, TRACE_STATE_SKIP_FRAME, @@ -298,6 +300,11 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings, uint32_ if (settings->core_frequency) { uint32_t prescaler = settings->core_frequency / trace_frequency - 1; + if (prescaler > TPI_ACPR_MAX) { + ELOG("Trace frequency prescaler %d out of range. Try setting a faster trace frequency.\n", prescaler); + if (!settings->force) + return false; + } stlink_write_debug32(stlink, TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor } stlink_write_debug32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN); @@ -372,6 +379,12 @@ static trace_state UpdateTrace(st_trace_t* trace, uint8_t c) { trace->count_raw_bytes++; // Parse the input using a state machine. + + if (trace->state == TRACE_STATE_UNKNOWN) { + if (TRACE_OP_IS_TARGET_SOURCE(c) || TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) + trace->state = TRACE_STATE_IDLE; + } + switch (trace->state) { case TRACE_STATE_IDLE: @@ -399,6 +412,9 @@ static trace_state UpdateTrace(st_trace_t* trace, uint8_t c) { case TRACE_STATE_SKIP_1: return TRACE_STATE_IDLE; + case TRACE_STATE_UNKNOWN: + return TRACE_STATE_UNKNOWN; + default: ELOG("Invalid state %d. This should never happen\n", trace->state); return TRACE_STATE_IDLE; @@ -424,6 +440,7 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { DLOG("Buffer overflow.\n"); else WLOG("Buffer overflow. Try using a slower trace frequency.\n"); + trace->state = TRACE_STATE_UNKNOWN; } for (int i = 0; i < length; i++) { From 305b7a4f2b3723af690931b11ac8e81167d14230 Mon Sep 17 00:00:00 2001 From: John Hall Date: Tue, 1 Dec 2020 16:35:40 -0800 Subject: [PATCH 1073/1435] Inproving huristic to handle cases where there is lots of valid data coming in that is starving out the time trace ops. --- src/st-trace/trace.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 8368cee34..1356ceca0 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -289,7 +289,6 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings, uint32_ DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_ASYNC); // Enable async tracing - DLOG("Setting trace frequency to %d Hz.\n", trace_frequency); if (stlink_trace_enable(stlink, trace_frequency)) { ELOG("Unable to turn on tracing in stlink\n"); if (!settings->force) @@ -330,6 +329,7 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings, uint32_ WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); } + ILOG("Trace frequency set to %d Hz.\n", trace_frequency); return true; } @@ -460,10 +460,11 @@ static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace, uint // Simple huristic to determine if we are configured poorly. bool error_no_data = (trace->count_raw_bytes < 100); - bool error_bad_data = (trace->count_error > 1 || trace->count_time_packets < 10 || trace->unknown_sources > 0); + bool error_low_data = (trace->count_time_packets < 10 && trace->count_target_data < 1000); + bool error_bad_data = (trace->count_error > 1 || trace->unknown_sources > 0); bool error_dropped_data = (trace->count_sw_overflow > 0); - if (!error_no_data && !error_bad_data && !error_dropped_data) + if (!error_no_data && !error_low_data && !error_bad_data && !error_dropped_data) return; WLOG("****\n"); @@ -473,7 +474,7 @@ static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace, uint WLOG("Try setting a slower trace frequency with the --trace=%d command line option.\n", trace_frequency / 2); } - if (error_no_data || error_bad_data) { + if (error_no_data || error_low_data || error_bad_data) { uint32_t prescaler; stlink_read_debug32(stlink, TPI_ACPR, &prescaler); if (prescaler) { From fdeb1729d68aa1949f856dc539a444c8c7a1bb06 Mon Sep 17 00:00:00 2001 From: John Hall Date: Wed, 2 Dec 2020 09:52:12 -0800 Subject: [PATCH 1074/1435] When a USB error occurs, chip-id does not appear to be initialized. --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index ac78db089..20d71df32 100644 --- a/src/common.c +++ b/src/common.c @@ -1305,7 +1305,7 @@ int stlink_load_device_params(stlink_t *sl) { DLOG("Loading device parameters....\n"); const struct stlink_chipid_params *params = NULL; stlink_core_id(sl); - uint32_t chip_id; + uint32_t chip_id = 0; uint32_t flash_size; stlink_chip_id(sl, &chip_id); From 1bbdd74c4b1b5ca7fe0bbfe367677503e20dc82d Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Sat, 5 Dec 2020 11:16:39 +0500 Subject: [PATCH 1075/1435] Fix the indentation --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 4ab43271e..b125803b8 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -109,7 +109,7 @@ set(STLINK_HEADERS src/stlink-lib/md5.h src/stlink-lib/sg.h src/stlink-lib/usb.h - src/stlink-lib/helper.h + src/stlink-lib/helper.h ) set(STLINK_SOURCE From 20e1d531153093842c6c37fec5dd4564e92934cd Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Sat, 5 Dec 2020 15:16:14 +0500 Subject: [PATCH 1076/1435] Fix the indentation --- CMakeLists.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index b125803b8..c8ab40257 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -120,7 +120,7 @@ set(STLINK_SOURCE src/stlink-lib/md5.c src/stlink-lib/sg.c src/stlink-lib/usb.c - src/stlink-lib/helper.c + src/stlink-lib/helper.c ) if (WIN32) From d6c9f8bd1103b1ad9f603e9b38ff7a73e3598c1b Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 5 Dec 2020 13:28:36 +0200 Subject: [PATCH 1077/1435] fix printf format srting --- src/st-info/info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/st-info/info.c b/src/st-info/info.c index 2e1ce0e96..0fc4d4d8a 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -76,7 +76,7 @@ static void stlink_probe(void) { printf("Found %u stlink programmers\n", (unsigned int)size); for (size_t n = 0; n < size; n++) { - if (size>1) printf("%lu.\n", n+1); + if (size > 1) printf("%u.\n", (unsigned int)n+1); stlink_print_info(stdevs[n]); } From 28c94453485a42290f0830219a1ab3a4f224111c Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 5 Dec 2020 14:10:24 +0200 Subject: [PATCH 1078/1435] fix gettimeofday for msvc --- src/win32/sys_time.c | 31 ++++++++++++++++++++++--------- src/win32/sys_time.h | 5 +---- 2 files changed, 23 insertions(+), 13 deletions(-) diff --git a/src/win32/sys_time.c b/src/win32/sys_time.c index ea7c25dda..08da60b85 100644 --- a/src/win32/sys_time.c +++ b/src/win32/sys_time.c @@ -1,20 +1,33 @@ -#include -#include - #include "sys_time.h" +#ifndef STLINK_HAVE_SYS_TIME_H + +#include + /* Simple gettimeofday implementation without converting Windows time to Linux time */ int gettimeofday(struct timeval *tv, struct timezone *tz) { FILETIME ftime; ULARGE_INTEGER ulint; + static int tzflag = 0; + + if(NULL != tv) { + GetSystemTimeAsFileTime(&ftime); + ulint.LowPart = ftime.dwLowDateTime; + ulint.HighPart = ftime.dwHighDateTime; - GetSystemTimeAsFileTime(&ftime); - ulint.LowPart = ftime.dwLowDateTime; - ulint.HighPart = ftime.dwHighDateTime; + tv->tv_sec = (long)(ulint.QuadPart / 10000000L); + tv->tv_usec = (long)(ulint.QuadPart % 10000000L); + } - tv->tv_sec = (long)(ulint.QuadPart / 10000000L); - tv->tv_usec = (long)(ulint.QuadPart % 10000000L); + if(NULL != tz) { + if (!tzflag) { + _tzset(); + tzflag++; + } + tz->tz_minuteswest = _timezone / 60; + tz->tz_dsttime = _daylight; + } return 0; - (void)tz; } +#endif //STLINK_HAVE_SYS_TIME_H diff --git a/src/win32/sys_time.h b/src/win32/sys_time.h index 87c3a42fd..39f97f739 100644 --- a/src/win32/sys_time.h +++ b/src/win32/sys_time.h @@ -5,10 +5,7 @@ #include #else -struct timeval { - long tv_sec; - long tv_usec; -}; +#include struct timezone { int tz_minuteswest; From fc9e7915fc9b783a5e0467d473645ca81ea3c97f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 5 Dec 2020 13:35:23 +0100 Subject: [PATCH 1079/1435] General Project Update - Corrected identation in reg.h - Updated README.md - Updated CHANGELOG.md - Updated list of contributors --- CHANGELOG.md | 16 +++++++- README.md | 19 ++------- contributors.txt | 8 ++-- doc/devices_boards.md | 2 +- src/stlink-lib/reg.h | 90 +++++++++++++++++++++---------------------- 5 files changed, 67 insertions(+), 68 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index d9dc64a11..4c178a4e4 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -8,7 +8,16 @@ Release date: (TBD) Features: +* Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) +* Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) * Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) +* Use SetConsoleCtrlHandler for Windows ([#1021](https://github.com/stlink-org/stlink/pull/1021)) +* Increase STM32L0 option_size to 20 ([#1046](https://github.com/stlink-org/stlink/pull/1046)) +* st-util: Add specialized memory map for STM32H7 devices ([#1060](https://github.com/stlink-org/stlink/pull/1060)) +* Support for STM32F4 option bytes ([#1062](https://github.com/stlink-org/stlink/pull/1062)) +* Link for WIN32 & APPLE with stlink-static ([#1069](https://github.com/stlink-org/stlink/pull/1069)) +* Extended support for STM32H7 ([#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) +* ITM functionality for ST-Link V2 and STM32Fxx chipsets ([#136](https://github.com/stlink-org/stlink/pull/136), [#179](https://github.com/stlink-org/stlink/pull/179), [#815](https://github.com/stlink-org/stlink/pull/815), [#1072](https://github.com/stlink-org/stlink/pull/1072)) Updates & changes: @@ -16,6 +25,7 @@ Updates & changes: * [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) * Imported debian pkg-settings ([#986](https://github.com/stlink-org/stlink/pull/986)) * Add support for FreeBSD's libusb reimplementation ([#992](https://github.com/stlink-org/stlink/pull/992), [#993](https://github.com/stlink-org/stlink/pull/993)) +* [doc] Added example for output of 'st-info --probe' ([#1007](https://github.com/stlink-org/stlink/pull/1007), [#1049](https://github.com/stlink-org/stlink/pull/1049)) Fixes: @@ -26,8 +36,10 @@ Fixes: * Fix for static linking of libssp ([#973](https://github.com/stlink-org/stlink/pull/973), [#974](https://github.com/stlink-org/stlink/pull/974)) * Fixed connect under reset for st-flash and st-util ([#983](https://github.com/stlink-org/stlink/pull/983)) * Fix for mmap() size_t overflow in st-flash ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) -* [regression] stlink-gui installation issue on Ubuntu-18.04 ([#1006](https://github.com/stlink-org/stlink/pull/1006)) -* st-util: wrong register values passed to gdb (st-link v2) ([#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027)) +* [regression] stlink-gui installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) +* st-util: wrong register values passed to gdb (st-link v2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027)) +* [doc] Fixed wrong path for rules.d folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) +* Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) v1.6.1 diff --git a/README.md b/README.md index 5be842156..350c36e34 100644 --- a/README.md +++ b/README.md @@ -23,7 +23,7 @@ The stlink library and tools are licensed under the **[BSD-3 License](LICENSE.md STLink is an open source toolset to program and debug STM32 devices and boards manufactured by STMicroelectronics. It supports several so called STLINK programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG/SWD. There are four generations available on the market which are _all_ supported by this toolset: -* **STLINK/v1** _(obsolete as of 21-11-2019, continued support by this toolset)_ +* **STLINK/v1** _[obsolete as of 21-11-2019, continued support by this toolset] *)_ - transport layer: SCSI passthru commands over USB - stand-alone programmer and present on STM32VL Discovery boards * **STLINK/v2** @@ -36,6 +36,8 @@ It supports several so called STLINK programmer boards (and clones thereof) whic - transport layer: raw USB commands - stand-alone programmer +_*)_ **Note: Support on macOS is limited to 10.13 - 10.15. Any later versions are no longer compatible with the STLINK/v1 due to technical reasons.** + On the user level there is no difference in handling or operation between these different revisions. The STlink toolset includes: @@ -112,18 +114,3 @@ When there is no executable available for your platform or you need the latest ( * Please start new forks from the develop branch, as pull requests will go into this branch as well. Please also refer to our [Contribution Guidelines](CONTRIBUTING.md). - - -# Current state of the project -## Known missing features - -Some features are currently missing from the `stlink-org/stlink` toolset. -Here we would appreciate any help and would love to welcome new contributors who want to get involved: - -* Instrumentation Trace Macro (ITM) Cell ([#136](https://github.com/stlink-org/stlink/issues/136)) -* OTP & EEPROM area programming ([#202](https://github.com/stlink-org/stlink/issues/202), [#333](https://github.com/stlink-org/stlink/issues/333), [#686](https://github.com/stlink-org/stlink/issues/686)) -* Protection bits area reading ([#346](https://github.com/stlink-org/stlink/issues/346)) -* Writing external memory connected to an STM32 controller (e.g Quad SPI NOR flash) ([#412](https://github.com/stlink-org/stlink/issues/412)) -* MCU hotplug ([#449](https://github.com/stlink-org/stlink/issues/449)) -* Writing options bytes (region) ([#458](https://github.com/stlink-org/stlink/issues/458)) -* Enhanced support for STLINKv3 programmer ([#820](https://github.com/stlink-org/stlink/issues/820)) diff --git a/contributors.txt b/contributors.txt index cc9403456..65b53aed1 100644 --- a/contributors.txt +++ b/contributors.txt @@ -7,6 +7,7 @@ Andrea Mucignat Andrew Andrianov [necromant] Andrey Yurovsky Andy Isaacson +Anton [Ant-ON] Áron Radics A. Sheaff Björn Hauffe @@ -35,7 +36,7 @@ Denis Osterland Dmitry Bravikov [bravikov] Efe Can İçöz Ethan Zonca -Fabien Chouteau +Fabien Chouteau [Fabien-Chouteau] Florian Hars Friedrich Beckmann Gabriel Górski [Glaeqen] @@ -63,6 +64,7 @@ Jim Paris Jiří Netolický Jerry Nosky [jnosky] Jochen Wilhelmy [Jochen0x90h] +Joel Bodenmann [Tectu] Johannes Taelman Jonas Danielsson Jonas Norling @@ -71,7 +73,6 @@ Karl Palsson [karlp] Kevlar Harness Kyle Manna Lari Lehtomäki -Lutz Freitag [nerdmaennchen] Martin Nowak Matteo Collina Max Chen @@ -80,7 +81,6 @@ Maxime Vincent Michael Pratt [prattmic] Michael Sparmann Mike Szczys -Miklós Márton [martonmiklos] Magnus Lundin [mlu] mux Ned Konz @@ -111,7 +111,7 @@ Simon Wright Stany Marcel Stefan Misik Sven Wegener -Joel Bodenmann [Tectu] +Timothy Lee [timothytylee] Tuomo Kaikkonen Theodore A. Roth Thomas Gärtner diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 8291f7532..4402839c5 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -50,7 +50,7 @@ Tested boards [incl. STLink programmers]: | 0x418 | STM32F105xx/107xx | x8 xB xC | | | | | F105
      F107 | | 0x420 | Medium density value | x8 xB | F100 | | | | | | 0x428 | High density Value | xC xD xE | F100 | | | | | -| 0x430 | XL-Density | xF XG | | F101 | | F103 | | +| 0x430 | XL-Density | xF xG | | F101 | | F103 | | Tested boards [incl. STLink programmers]: * STM32VL-Discovery (STM32F100RBT6) with STLink-v1 [v1, v2] diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 2e93dc5b1..fdea175d3 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -1,61 +1,61 @@ #ifndef STLINK_REG_H_ #define STLINK_REG_H_ -#define STLINK_REG_CM3_CPUID 0xE000ED00 +#define STLINK_REG_CM3_CPUID 0xE000ED00 -#define STLINK_REG_CM3_FP_CTRL 0xE0002000 -#define STLINK_REG_CM3_FP_COMPn(n) (0xE0002008 + n*4) -#define STLINK_REG_CM7_FP_LAR 0xE0000FB0 +#define STLINK_REG_CM3_FP_CTRL 0xE0002000 +#define STLINK_REG_CM3_FP_COMPn(n) (0xE0002008 + n*4) +#define STLINK_REG_CM7_FP_LAR 0xE0000FB0 #define STLINK_REG_CM7_FP_LAR_KEY 0xC5ACCE55 -#define STLINK_REG_CM3_DEMCR 0xE000EDFC -#define STLINK_REG_CM3_DEMCR_TRCENA (1 << 24) -#define STLINK_REG_CM3_DEMCR_VC_HARDERR (1 << 10) -#define STLINK_REG_CM3_DEMCR_VC_BUSERR (1 << 8) -#define STLINK_REG_CM3_DEMCR_VC_CORERESET (1 << 0) -#define STLINK_REG_CM3_DWT_COMPn(n) (0xE0001020 + n*16) -#define STLINK_REG_CM3_DWT_MASKn(n) (0xE0001024 + n*16) -#define STLINK_REG_CM3_DWT_FUNn(n) (0xE0001028 + n*16) +#define STLINK_REG_CM3_DEMCR 0xE000EDFC +#define STLINK_REG_CM3_DEMCR_TRCENA (1 << 24) +#define STLINK_REG_CM3_DEMCR_VC_HARDERR (1 << 10) +#define STLINK_REG_CM3_DEMCR_VC_BUSERR (1 << 8) +#define STLINK_REG_CM3_DEMCR_VC_CORERESET (1 << 0) +#define STLINK_REG_CM3_DWT_COMPn(n) (0xE0001020 + n*16) +#define STLINK_REG_CM3_DWT_MASKn(n) (0xE0001024 + n*16) +#define STLINK_REG_CM3_DWT_FUNn(n) (0xE0001028 + n*16) /* Cortex™-M3 Technical Reference Manual */ /* Debug Halting Control and Status Register */ -#define STLINK_REG_DFSR 0xE000ED30 -#define STLINK_REG_DFSR_HALT (1 << 0) -#define STLINK_REG_DFSR_BKPT (1 << 1) -#define STLINK_REG_DFSR_VCATCH (1 << 3) -#define STLINK_REG_DFSR_EXTERNAL (1 << 4) -#define STLINK_REG_DFSR_CLEAR 0x0000001F -#define STLINK_REG_DHCSR 0xe000edf0 -#define STLINK_REG_DHCSR_DBGKEY (0xA05F << 16) -#define STLINK_REG_DHCSR_C_DEBUGEN (1 << 0) -#define STLINK_REG_DHCSR_C_HALT (1 << 1) -#define STLINK_REG_DHCSR_C_STEP (1 << 2) -#define STLINK_REG_DHCSR_C_MASKINTS (1 << 3) -#define STLINK_REG_DHCSR_S_REGRDY (1 << 16) -#define STLINK_REG_DHCSR_S_HALT (1 << 17) -#define STLINK_REG_DHCSR_S_SLEEP (1 << 18) -#define STLINK_REG_DHCSR_S_LOCKUP (1 << 19) -#define STLINK_REG_DHCSR_S_RETIRE_ST (1 << 24) -#define STLINK_REG_DHCSR_S_RESET_ST (1 << 25) -#define STLINK_REG_DCRSR 0xe000edf4 -#define STLINK_REG_DCRDR 0xe000edf8 +#define STLINK_REG_DFSR 0xE000ED30 +#define STLINK_REG_DFSR_HALT (1 << 0) +#define STLINK_REG_DFSR_BKPT (1 << 1) +#define STLINK_REG_DFSR_VCATCH (1 << 3) +#define STLINK_REG_DFSR_EXTERNAL (1 << 4) +#define STLINK_REG_DFSR_CLEAR 0x0000001F +#define STLINK_REG_DHCSR 0xe000edf0 +#define STLINK_REG_DHCSR_DBGKEY (0xA05F << 16) +#define STLINK_REG_DHCSR_C_DEBUGEN (1 << 0) +#define STLINK_REG_DHCSR_C_HALT (1 << 1) +#define STLINK_REG_DHCSR_C_STEP (1 << 2) +#define STLINK_REG_DHCSR_C_MASKINTS (1 << 3) +#define STLINK_REG_DHCSR_S_REGRDY (1 << 16) +#define STLINK_REG_DHCSR_S_HALT (1 << 17) +#define STLINK_REG_DHCSR_S_SLEEP (1 << 18) +#define STLINK_REG_DHCSR_S_LOCKUP (1 << 19) +#define STLINK_REG_DHCSR_S_RETIRE_ST (1 << 24) +#define STLINK_REG_DHCSR_S_RESET_ST (1 << 25) +#define STLINK_REG_DCRSR 0xe000edf4 +#define STLINK_REG_DCRDR 0xe000edf8 /* Application Interrupt and Reset Control Register */ -#define STLINK_REG_AIRCR 0xe000ed0c -#define STLINK_REG_AIRCR_VECTKEY 0x05fa0000 -#define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004 -#define STLINK_REG_AIRCR_VECTRESET 0x00000001 +#define STLINK_REG_AIRCR 0xe000ed0c +#define STLINK_REG_AIRCR_VECTKEY 0x05fa0000 +#define STLINK_REG_AIRCR_SYSRESETREQ 0x00000004 +#define STLINK_REG_AIRCR_VECTRESET 0x00000001 /* ARM Cortex-M7 Processor Technical Reference Manual */ /* Cache Control and Status Register */ -#define STLINK_REG_CM7_CTR 0xE000ED7C -#define STLINK_REG_CM7_CLIDR 0xE000ED78 -#define STLINK_REG_CM7_CCR 0xE000ED14 -#define STLINK_REG_CM7_CCR_DC (1 << 16) -#define STLINK_REG_CM7_CCR_IC (1 << 17) -#define STLINK_REG_CM7_CSSELR 0xE000ED84 -#define STLINK_REG_CM7_DCCSW 0xE000EF6C -#define STLINK_REG_CM7_ICIALLU 0xE000EF50 -#define STLINK_REG_CM7_CCSIDR 0xE000ED80 +#define STLINK_REG_CM7_CTR 0xE000ED7C +#define STLINK_REG_CM7_CLIDR 0xE000ED78 +#define STLINK_REG_CM7_CCR 0xE000ED14 +#define STLINK_REG_CM7_CCR_DC (1 << 16) +#define STLINK_REG_CM7_CCR_IC (1 << 17) +#define STLINK_REG_CM7_CSSELR 0xE000ED84 +#define STLINK_REG_CM7_DCCSW 0xE000EF6C +#define STLINK_REG_CM7_ICIALLU 0xE000EF50 +#define STLINK_REG_CM7_CCSIDR 0xE000ED80 #endif // STLINK_REG_H_ From 373eee2cfebc410efc86b42524f84dc0dd536081 Mon Sep 17 00:00:00 2001 From: John Hall Date: Sat, 5 Dec 2020 10:25:14 -0800 Subject: [PATCH 1080/1435] Adding back has_dual_bank. Replacing flags field with has_swo_tracing. --- inc/backend.h | 2 +- inc/stlink.h | 6 ++- src/common.c | 5 ++- src/st-trace/trace.c | 2 +- src/stlink-lib/chipid.c | 99 +++++++++++++++++++++-------------------- src/stlink-lib/chipid.h | 5 +-- 6 files changed, 62 insertions(+), 57 deletions(-) diff --git a/inc/backend.h b/inc/backend.h index 6a0232849..ebd438127 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -28,7 +28,7 @@ int (*current_mode) (stlink_t * stl); int (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); - int (*set_swdclk) (stlink_t * stl, uint16_t divisor); + int (*set_swdclk) (stlink_t * stl, int freq_khz); int (*trace_enable) (stlink_t * sl, uint32_t frequency); int (*trace_disable) (stlink_t * sl); int (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); diff --git a/inc/stlink.h b/inc/stlink.h index 163d5d4b9..17c0bc6f4 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -220,7 +220,7 @@ struct _stlink { enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx - uint32_t chip_flags; + bool has_dual_bank; stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() size_t flash_size; // calculated by stlink_load_device_params() @@ -234,6 +234,8 @@ struct _stlink { stm32_addr_t option_base; size_t option_size; + bool has_swo_tracing; + // bootloader // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code // (see tests/sg.c) @@ -270,7 +272,7 @@ int stlink_step(stlink_t *sl); int stlink_current_mode(stlink_t *sl); int stlink_force_debug(stlink_t *sl); int stlink_target_voltage(stlink_t *sl); -int stlink_set_swdclk(stlink_t *sl, uint16_t divisor); +int stlink_set_swdclk(stlink_t *sl, int freq_khz); int stlink_trace_enable(stlink_t* sl, uint32_t frequency); int stlink_trace_disable(stlink_t* sl); int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); diff --git a/src/common.c b/src/common.c index 5e1e61e25..f2d68daf4 100644 --- a/src/common.c +++ b/src/common.c @@ -907,7 +907,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + if (sl->has_dual_bank) { cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); } @@ -1355,13 +1355,14 @@ int stlink_load_device_params(stlink_t *sl) { } sl->flash_type = params->flash_type; - sl->chip_flags = params->flags; + sl->has_dual_bank = params->has_dual_bank; sl->flash_pgsz = params->flash_pagesize; sl->sram_size = params->sram_size; sl->sys_base = params->bootrom_base; sl->sys_size = params->bootrom_size; sl->option_base = params->option_base; sl->option_size = params->option_size; + sl->has_swo_tracing = params->has_swo_tracing; // medium and low devices have the same chipid. ram size depends on flash size. // STM32F100xx datasheet Doc ID 16455 Table 2 diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 1356ceca0..6a5ccb91d 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -566,7 +566,7 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_UNSUPPORTED_LINK; } - if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { + if (!stlink->has_swo_tracing) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); ELOG("We do not support SWO output for device '%s'\n", params->description); if (!settings.force) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 1a0c305c7..cb9276c93 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -14,7 +14,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 .option_size = 0x20, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // RM0385 and DS10916 document was used to find these paramaters @@ -26,7 +26,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // RM0431 and DS document was used to find these paramaters @@ -38,7 +38,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // table 2, PM0063 .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, @@ -49,7 +49,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x5000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // table 1, PM0059 .chip_id = STLINK_CHIPID_STM32_F2, @@ -62,7 +62,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = 0x1FFFC000, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // PM0063 .chip_id = STLINK_CHIPID_STM32_F1_LOW, @@ -73,7 +73,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2800, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F4, @@ -86,7 +86,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = STM32_F4_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F4_DSI, @@ -97,7 +97,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F4_HD, @@ -108,7 +108,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F4_LP, @@ -119,7 +119,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F411RE, @@ -130,7 +130,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x20000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F4_DE, @@ -141,7 +141,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x18000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F1_HIGH, @@ -152,7 +152,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // This ignores the EEPROM! (and uses the page erase size, @@ -165,7 +165,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x4000, .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_L1_CAT2, @@ -176,7 +176,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, @@ -187,7 +187,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, // not completely clear if there are some with 48k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_L1_HIGH, @@ -200,7 +200,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x1000, .option_base = STM32_L1_OPTION_BYTES_BASE, .option_size = 8, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_L152_RE, @@ -211,7 +211,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x14000, // not completely clear if there are some with 32k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F1_CONN, @@ -222,7 +222,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1fffb000, .bootrom_size = 0x4800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // Low and Medium density VL have same chipid. RM0041 25.6.1 .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, @@ -233,7 +233,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2000, // 0x1000 for low density devices .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. @@ -247,7 +247,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = 0x1FFFC000, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. @@ -259,7 +259,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // This is STK32F303VCT6 device from STM32 F3 Discovery board. @@ -272,7 +272,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // This is STK32F373VCT6 device from STM32 F373 eval board @@ -285,7 +285,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, @@ -296,7 +296,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F1_XL, @@ -307,7 +307,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x18000, .bootrom_base = 0x1fffe000, .bootrom_size = 0x1800, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // Use this as an example for mapping future chips: @@ -319,7 +319,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // Page sizes listed in Table 4 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000 // "System memory" byte size in hex from Table 2 + .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 }, { // Use this as an example for mapping future chips: @@ -331,7 +331,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 }, { // RM0402 document was used to find these parameters @@ -344,7 +344,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // RM0430 DocID029473 Rev 2 document was used to find these parameters @@ -357,7 +357,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 only says 0x40000) .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { .chip_id = STLINK_CHIPID_STM32_F09X, @@ -367,7 +367,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 - .bootrom_size = 0x2000 // "System memory" byte size in hex from Table 2 + .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 }, { // Use this as an example for mapping future chips: @@ -379,7 +379,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 }, { // Use this as an example for mapping future chips: @@ -391,7 +391,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 }, { // STM32F30x @@ -403,7 +403,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1fffd800, .bootrom_size = 0x2000, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32L0x @@ -458,7 +458,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x3000, .bootrom_base = 0x1fffd800, .bootrom_size = 0x2000, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // This is STK32F303RET6 device from STM32 F3 Nucelo board. @@ -471,7 +471,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, // 3.3 Embedded SRAM .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory .bootrom_size = 0x2000, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32L4x6 @@ -490,7 +490,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32L4RX @@ -503,7 +503,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 99) - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STLINK_CHIPID_STM32_L41X @@ -518,7 +518,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) .bootrom_size = 0x7000, // 28k, same source as base - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STLINK_CHIPID_STM32_L43X @@ -537,7 +537,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STLINK_CHIPID_STM32_L496X @@ -554,7 +554,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STLINK_CHIPID_STM32_L46X @@ -570,7 +570,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x20000, .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system memory, also fig 2 on page 63) .bootrom_size = 0x7000, // 28k (per bank), same source as base - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32L011 @@ -581,7 +581,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x80, .sram_size = 0x2000, .bootrom_base = 0x1ff00000, - .bootrom_size = 0x2000 + .bootrom_size = 0x2000, }, { // STM32G030/031/041 (from RM0454 & RM0444) @@ -624,13 +624,14 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32G471/473/474/483/484 (from RM0440) .chip_id = STLINK_CHIPID_STM32_G4_CAT3, .description = "G4 Category-3", .flash_type = STLINK_FLASH_TYPE_G4, + .has_dual_bank = true, .flash_size_reg = 0x1FFF75E0, // Section 47.2 .flash_pagesize = 0x800, // 2k (sec 3.3.1) // SRAM1 is 80k at 0x20000000 @@ -641,7 +642,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32WB55 (from RM0434) @@ -652,7 +653,8 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x1000, // 4k .sram_size = 0x40000, .bootrom_base = 0x1fff0000, // see the memory map - .bootrom_size = 0x7000 + .bootrom_size = 0x7000, + .has_swo_tracing = true, }, { // STM32H742/743/753 (from RM0433) @@ -667,7 +669,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 - .flags = CHIP_F_HAS_SWO_TRACING, + .has_swo_tracing = true, }, { // STM32H7A3/7B3 (from RM0455) @@ -682,6 +684,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to two banks (Table 12-14) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, + .has_swo_tracing = true, }, { // STM32H72x/H73x (from RM0468) @@ -695,6 +698,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, + .has_swo_tracing = true, }, { @@ -707,7 +711,6 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x0, .bootrom_base = 0x0, .bootrom_size = 0x0, - .flags = 0, }, }; diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 1b54fe140..aab22759c 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -69,15 +69,13 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_WB55 = 0x495 }; -#define CHIP_F_HAS_DUAL_BANK (1 << 0) -#define CHIP_F_HAS_SWO_TRACING (1 << 1) /** Chipid parameters */ struct stlink_chipid_params { uint32_t chip_id; char *description; enum stlink_flash_type flash_type; - uint32_t flags; + bool has_dual_bank; uint32_t flash_size_reg; uint32_t flash_pagesize; uint32_t sram_size; @@ -85,6 +83,7 @@ struct stlink_chipid_params { uint32_t bootrom_size; uint32_t option_base; uint32_t option_size; + bool has_swo_tracing; }; const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); From 5d1f3198a4530ca87e6dc61e21fb259b0e6f8417 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Sun, 6 Dec 2020 14:09:59 +0500 Subject: [PATCH 1081/1435] Fix warning of narrowing issues --- src/stlink-lib/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index 8b2c8e8f7..32d9b6c8d 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -11,5 +11,5 @@ unsigned time_ms() { struct timeval tv; gettimeofday(&tv, NULL); - return (unsigned)tv.tv_sec * 1000 + tv.tv_usec / 1000; + return (unsigned)(tv.tv_sec * 1000 + tv.tv_usec / 1000); } From 3e9e2bb38a00e7dae1cc97c613a91d2e680cd589 Mon Sep 17 00:00:00 2001 From: John Hall Date: Sun, 6 Dec 2020 11:01:02 -0800 Subject: [PATCH 1082/1435] Adding back flag. --- inc/stlink.h | 6 +-- src/common.c | 2 +- src/st-trace/trace.c | 2 +- src/stlink-lib/chipid.c | 86 ++++++++++++++++++++--------------------- src/stlink-lib/chipid.h | 5 ++- 5 files changed, 52 insertions(+), 49 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 17c0bc6f4..b4fff334f 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -22,7 +22,7 @@ extern "C" { /* Max data transfer size */ // 6kB = max mem32_read block, 8kB sram -// #define Q_BUF_LEN 96 +// #define Q_BUF_LEN 96 #define Q_BUF_LEN (1024 * 100) // STLINK_DEBUG_RESETSYS, etc: @@ -234,8 +234,6 @@ struct _stlink { stm32_addr_t option_base; size_t option_size; - bool has_swo_tracing; - // bootloader // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code // (see tests/sg.c) @@ -243,6 +241,8 @@ struct _stlink { size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() struct stlink_version_ version; + + uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx }; int stlink_enter_swd_mode(stlink_t *sl); diff --git a/src/common.c b/src/common.c index f2d68daf4..a9e907c60 100644 --- a/src/common.c +++ b/src/common.c @@ -1362,7 +1362,7 @@ int stlink_load_device_params(stlink_t *sl) { sl->sys_size = params->bootrom_size; sl->option_base = params->option_base; sl->option_size = params->option_size; - sl->has_swo_tracing = params->has_swo_tracing; + sl->chip_flags = params->flags; // medium and low devices have the same chipid. ram size depends on flash size. // STM32F100xx datasheet Doc ID 16455 Table 2 diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 6a5ccb91d..1356ceca0 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -566,7 +566,7 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_UNSUPPORTED_LINK; } - if (!stlink->has_swo_tracing) { + if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); ELOG("We do not support SWO output for device '%s'\n", params->description); if (!settings.force) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index cb9276c93..dc3218261 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -14,7 +14,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 .option_size = 0x20, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // RM0385 and DS10916 document was used to find these paramaters @@ -26,7 +26,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // RM0431 and DS document was used to find these paramaters @@ -38,7 +38,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // table 2, PM0063 .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, @@ -49,7 +49,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x5000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // table 1, PM0059 .chip_id = STLINK_CHIPID_STM32_F2, @@ -62,7 +62,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = 0x1FFFC000, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // PM0063 .chip_id = STLINK_CHIPID_STM32_F1_LOW, @@ -73,7 +73,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2800, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4, @@ -86,7 +86,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = STM32_F4_OPTION_BYTES_BASE, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_DSI, @@ -97,7 +97,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_HD, @@ -108,7 +108,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_LP, @@ -119,7 +119,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F411RE, @@ -130,7 +130,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x20000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_DE, @@ -141,7 +141,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x18000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_HIGH, @@ -152,7 +152,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This ignores the EEPROM! (and uses the page erase size, @@ -165,7 +165,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x4000, .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L1_CAT2, @@ -176,7 +176,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, @@ -187,7 +187,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, // not completely clear if there are some with 48k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L1_HIGH, @@ -200,7 +200,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x1000, .option_base = STM32_L1_OPTION_BYTES_BASE, .option_size = 8, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_L152_RE, @@ -211,7 +211,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x14000, // not completely clear if there are some with 32k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_CONN, @@ -222,7 +222,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1fffb000, .bootrom_size = 0x4800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // Low and Medium density VL have same chipid. RM0041 25.6.1 .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, @@ -233,7 +233,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2000, // 0x1000 for low density devices .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. @@ -247,7 +247,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7800, .option_base = 0x1FFFC000, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. @@ -259,7 +259,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This is STK32F303VCT6 device from STM32 F3 Discovery board. @@ -272,7 +272,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This is STK32F373VCT6 device from STM32 F373 eval board @@ -285,7 +285,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, @@ -296,7 +296,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F1_XL, @@ -307,7 +307,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x18000, .bootrom_base = 0x1fffe000, .bootrom_size = 0x1800, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // Use this as an example for mapping future chips: @@ -344,7 +344,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // RM0430 DocID029473 Rev 2 document was used to find these parameters @@ -357,7 +357,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 only says 0x40000) .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F09X, @@ -403,7 +403,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1fffd800, .bootrom_size = 0x2000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L0x @@ -458,7 +458,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x3000, .bootrom_base = 0x1fffd800, .bootrom_size = 0x2000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // This is STK32F303RET6 device from STM32 F3 Nucelo board. @@ -471,7 +471,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, // 3.3 Embedded SRAM .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory .bootrom_size = 0x2000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L4x6 @@ -490,7 +490,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L4RX @@ -503,7 +503,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 99) - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L41X @@ -518,7 +518,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) .bootrom_size = 0x7000, // 28k, same source as base - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L43X @@ -537,7 +537,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L496X @@ -554,7 +554,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L46X @@ -570,7 +570,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x20000, .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system memory, also fig 2 on page 63) .bootrom_size = 0x7000, // 28k (per bank), same source as base - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32L011 @@ -624,7 +624,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32G471/473/474/483/484 (from RM0440) @@ -642,7 +642,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32WB55 (from RM0434) @@ -654,7 +654,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x40000, .bootrom_base = 0x1fff0000, // see the memory map .bootrom_size = 0x7000, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32H742/743/753 (from RM0433) @@ -669,7 +669,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32H7A3/7B3 (from RM0455) @@ -684,7 +684,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to two banks (Table 12-14) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { // STM32H72x/H73x (from RM0468) @@ -698,7 +698,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, - .has_swo_tracing = true, + .flags = CHIP_F_HAS_SWO_TRACING, }, { diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index aab22759c..5fee49f87 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -70,6 +70,9 @@ enum stlink_stm32_chipids { }; +#define CHIP_F_HAS_SWO_TRACING (1 << 0) + + /** Chipid parameters */ struct stlink_chipid_params { uint32_t chip_id; @@ -83,7 +86,7 @@ struct stlink_chipid_params { uint32_t bootrom_size; uint32_t option_base; uint32_t option_size; - bool has_swo_tracing; + uint32_t flags; }; const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); From 67bf3906ef509e40c8ad909489701390cab2b89d Mon Sep 17 00:00:00 2001 From: John Hall Date: Sun, 6 Dec 2020 15:56:40 -0800 Subject: [PATCH 1083/1435] Fixing funcation naming convention. --- src/st-trace/trace.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 1356ceca0..450e7c598 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -242,7 +242,7 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return true; } -static void ConvertSerialNumberTextToBinary(const char* text, char binary_out[STLINK_SERIAL_MAX_SIZE]) { +static void convert_serial_number_text_to_binary(const char* text, char binary_out[STLINK_SERIAL_MAX_SIZE]) { size_t length = 0; for (uint32_t n = 0; n < strlen(text) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { char buffer[3] = { 0 }; @@ -251,11 +251,11 @@ static void ConvertSerialNumberTextToBinary(const char* text, char binary_out[ST } } -static stlink_t* StLinkConnect(const st_settings_t* settings) { +static stlink_t* stlink_connect(const st_settings_t* settings) { if (settings->serial_number) { // Open this specific stlink. char binary_serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; - ConvertSerialNumberTextToBinary(settings->serial_number, binary_serial_number); + convert_serial_number_text_to_binary(settings->serial_number, binary_serial_number); return stlink_open_usb(settings->logging_level, false, binary_serial_number, 0); } else { // Otherwise, open any stlink. @@ -263,7 +263,7 @@ static stlink_t* StLinkConnect(const st_settings_t* settings) { } } -static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings, uint32_t trace_frequency) { +static bool enable_trace(stlink_t* stlink, const st_settings_t* settings, uint32_t trace_frequency) { if (stlink_force_debug(stlink)) { ELOG("Unable to debug device\n"); @@ -334,7 +334,7 @@ static bool EnableTrace(stlink_t* stlink, const st_settings_t* settings, uint32_ return true; } -static trace_state UpdateTraceIdle(st_trace_t* trace, uint8_t c) { +static trace_state update_trace_idle(st_trace_t* trace, uint8_t c) { // Handle a trace byte when we are in the idle state. if (TRACE_OP_IS_TARGET_SOURCE(c)) { @@ -375,7 +375,7 @@ static trace_state UpdateTraceIdle(st_trace_t* trace, uint8_t c) { return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; } -static trace_state UpdateTrace(st_trace_t* trace, uint8_t c) { +static trace_state update_trace(st_trace_t* trace, uint8_t c) { trace->count_raw_bytes++; // Parse the input using a state machine. @@ -388,7 +388,7 @@ static trace_state UpdateTrace(st_trace_t* trace, uint8_t c) { switch (trace->state) { case TRACE_STATE_IDLE: - return UpdateTraceIdle(trace, c); + return update_trace_idle(trace, c); case TRACE_STATE_TARGET_SOURCE: putchar(c); @@ -421,7 +421,7 @@ static trace_state UpdateTrace(st_trace_t* trace, uint8_t c) { } } -static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { +static bool read_trace(stlink_t* stlink, st_trace_t* trace) { uint8_t buffer[STLINK_TRACE_BUF_LEN]; int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); @@ -444,13 +444,13 @@ static bool ReadTrace(stlink_t* stlink, st_trace_t* trace) { } for (int i = 0; i < length; i++) { - trace->state = UpdateTrace(trace, buffer[i]); + trace->state = update_trace(trace, buffer[i]); } return true; } -static void CheckForConfigurationError(stlink_t* stlink, st_trace_t* trace, uint32_t trace_frequency) { +static void check_for_configuration_error(stlink_t* stlink, st_trace_t* trace, uint32_t trace_frequency) { // Only check configuration one time after the first 10 seconds of running. uint32_t elapsed_time_s = time(NULL) - trace->start_time; if (trace->configuration_checked || elapsed_time_s < 10) { @@ -546,7 +546,7 @@ int main(int argc, char** argv) return APP_RESULT_SUCCESS; } - stlink_t* stlink = StLinkConnect(&settings); + stlink_t* stlink = stlink_connect(&settings); if (!stlink) { ELOG("Unable to locate an stlink\n"); return APP_RESULT_STLINK_NOT_FOUND; @@ -582,7 +582,7 @@ int main(int argc, char** argv) return APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY; } - if (!EnableTrace(stlink, &settings, trace_frequency)) { + if (!enable_trace(stlink, &settings, trace_frequency)) { ELOG("Unable to enable trace mode\n"); if (!settings.force) return APP_RESULT_STLINK_STATE_ERROR; @@ -598,8 +598,8 @@ int main(int argc, char** argv) return APP_RESULT_STLINK_STATE_ERROR; } - while (!g_abort_trace && ReadTrace(stlink, &trace)) { - CheckForConfigurationError(stlink, &trace, trace_frequency); + while (!g_abort_trace && read_trace(stlink, &trace)) { + check_for_configuration_error(stlink, &trace, trace_frequency); } stlink_trace_disable(stlink); From 7db0477d8f3da330d429da5ea12fde7cd4a09b7e Mon Sep 17 00:00:00 2001 From: John Hall Date: Sun, 6 Dec 2020 16:01:41 -0800 Subject: [PATCH 1084/1435] Adding windows signal handler type behavior. --- src/st-trace/trace.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 450e7c598..63003df58 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -148,6 +148,13 @@ static void abort_trace() { g_abort_trace = true; } +#if defined(_WIN32) +BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { + abort_trace(); + return FALSE; +} +#endif + static void usage(void) { puts("st-trace - usage:"); puts(" -h, --help Print this help"); @@ -516,10 +523,15 @@ static void check_for_configuration_error(stlink_t* stlink, st_trace_t* trace, u int main(int argc, char** argv) { +#if defined(_WIN32) + SetConsoleCtrlHandler((PHANDLER_ROUTINE)abort_trace, TRUE); +#else signal(SIGINT, &abort_trace); signal(SIGTERM, &abort_trace); signal(SIGSEGV, &abort_trace); signal(SIGPIPE, &abort_trace); +#endif + st_settings_t settings; if (!parse_options(argc, argv, &settings)) { From dc9726cd06bfbe695993951d78943b064560a8bb Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 7 Dec 2020 09:02:00 -0800 Subject: [PATCH 1085/1435] Set abort routine wrong in windows. Found in code review. --- src/st-trace/trace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 63003df58..a01f0c522 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -524,7 +524,7 @@ static void check_for_configuration_error(stlink_t* stlink, st_trace_t* trace, u int main(int argc, char** argv) { #if defined(_WIN32) - SetConsoleCtrlHandler((PHANDLER_ROUTINE)abort_trace, TRUE); + SetConsoleCtrlHandler((PHANDLER_ROUTINE)CtrlHandler, TRUE); #else signal(SIGINT, &abort_trace); signal(SIGTERM, &abort_trace); From d1a9fd85e097ce0f03699b3b163fcc96c35e4d57 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 7 Dec 2020 10:12:23 -0800 Subject: [PATCH 1086/1435] Moved register definitions to common reg.h file. --- inc/stlink.h | 22 -------- src/st-trace/trace.c | 126 +++++++++++++------------------------------ src/stlink-lib/reg.h | 52 +++++++++++++++++- 3 files changed, 89 insertions(+), 111 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index b4fff334f..ef61fd1ba 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -88,28 +88,6 @@ enum target_state { #define STLINK_V3_MAX_TRACE_FREQUENCY 24000000 #define STLINK_DEFAULT_TRACE_FREQUENCY 2000000 -/* Cortex Debug Control Block */ -#define DCB_DHCSR 0xE000EDF0 -#define DCB_DCRSR 0xE000EDF4 -#define DCB_DCRDR 0xE000EDF8 -#define DCB_DEMCR 0xE000EDFC - -/* DCB_DHCSR bit and field definitions */ -#define DBGKEY (0xA05F << 16) -#define C_DEBUGEN (1 << 0) -#define C_HALT (1 << 1) -#define C_STEP (1 << 2) -#define C_MASKINTS (1 << 3) -#define S_REGRDY (1 << 16) -#define S_HALT (1 << 17) -#define S_SLEEP (1 << 18) -#define S_LOCKUP (1 << 19) -#define S_RETIRE_ST (1 << 24) -#define S_RESET_ST (1 << 25) - -/* DCB_DEMCR field definitions */ -#define DEMCR_TRCENA (1 << 24) - /* Map the relevant features, quirks and workaround for specific firmware version of stlink */ #define STLINK_F_HAS_TRACE (1 << 0) #define STLINK_F_HAS_SWD_SET_FREQ (1 << 1) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index a01f0c522..7f586c7c2 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -10,6 +10,7 @@ #include #include +#include #include @@ -39,66 +40,6 @@ #define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) -// TODO: Ideally all register and field definitions would be in a common header file. - -// Instrumentation Trace Macrocell (ITM) Registers -#define ITM_TER 0xE0000E00 // ITM Trace Enable Register -#define ITM_TPR 0xE0000E40 // ITM Trace Privilege Register -#define ITM_TCR 0xE0000E80 // ITM Trace Control Register -#define ITM_TCC 0xE0000E90 // ITM Trace Cycle Count -#define ITM_LAR 0xE0000FB0 // ITM Lock Access Register - -// ITM field definitions -#define ITM_TER_PORTS_ALL (0xFFFFFFFF) -#define ITM_TPR_PORTS_ALL (0x0F) -#define ITM_TCR_TRACE_BUS_ID_1 (0x01 << 16) -#define ITM_TCR_SWO_ENA (1 << 4) -#define ITM_TCR_DWT_ENA (1 << 3) -#define ITM_TCR_SYNC_ENA (1 << 2) -#define ITM_TCR_TS_ENA (1 << 1) -#define ITM_TCR_ITM_ENA (1 << 0) -#define ITM_LAR_KEY 0xC5ACCE55 - -// Data Watchpoint and Trace (DWT) Registers -#define DWT_CTRL 0xE0001000 // DWT Control Register -#define DWT_FUNCTION0 0xE0001028 // DWT Function Register 0 -#define DWT_FUNCTION1 0xE0001038 // DWT Function Register 1 -#define DWT_FUNCTION2 0xE0001048 // DWT Function Register 2 -#define DWT_FUNCTION3 0xE0001058 // DWT Function Register 3 - -// DWT field definitions -#define DWT_CTRL_NUM_COMP (1 << 28) -#define DWT_CTRL_CYC_TAP (1 << 9) -#define DWT_CTRL_POST_INIT (1 << 5) -#define DWT_CTRL_POST_PRESET (1 << 1) -#define DWT_CTRL_CYCCNT_ENA (1 << 0) - -// Trace Port Interface (TPI) Registers -#define TPI_CSPSR 0xE0040004 // TPI Current Parallel Port Size Register -#define TPI_ACPR 0xE0040010 // TPI Asynchronous Clock Prescaler Register -#define TPI_SPPR 0xE00400F0 // TPI Selected Pin Protocol Register -#define TPI_FFCR 0xE0040304 // TPI Formatter and Flush Control Register - -// TPI field definitions -#define TPI_TPI_CSPSR_PORT_SIZE_1 (0x01 << 0) -#define TPI_SPPR_SWO_MANCHESTER (0x01 << 0) -#define TPI_SPPR_SWO_NRZ (0x02 << 0) -#define TPI_FFCR_TRIG_IN (0x01 << 8) -#define TPI_ACPR_MAX (0x1FFF) - -// Other Registers -#define FP_CTRL 0xE0002000 // Flash Patch Control Register -#define DBGMCU_CR 0xE0042004 // Debug MCU Configuration Register - -// Other register field definitions -#define FP_CTRL_KEY (1 << 1) -#define DBGMCU_CR_DBG_SLEEP (1 << 0) -#define DBGMCU_CR_DBG_STOP (1 << 1) -#define DBGMCU_CR_DBG_STANDBY (1 << 2) -#define DBGMCU_CR_TRACE_IOEN (1 << 5) -#define DBGMCU_CR_TRACE_MODE_ASYNC (0x00 << 6) - - typedef struct { bool show_help; bool show_version; @@ -284,17 +225,22 @@ static bool enable_trace(stlink_t* stlink, const st_settings_t* settings, uint32 return false; } - stlink_write_debug32(stlink, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT); - stlink_write_debug32(stlink, DCB_DEMCR, DEMCR_TRCENA); - stlink_write_debug32(stlink, FP_CTRL, FP_CTRL_KEY); - stlink_write_debug32(stlink, DWT_FUNCTION0, 0); - stlink_write_debug32(stlink, DWT_FUNCTION1, 0); - stlink_write_debug32(stlink, DWT_FUNCTION2, 0); - stlink_write_debug32(stlink, DWT_FUNCTION3, 0); - stlink_write_debug32(stlink, DWT_CTRL, 0); - stlink_write_debug32(stlink, DBGMCU_CR, DBGMCU_CR_DBG_SLEEP | DBGMCU_CR_DBG_STOP | - DBGMCU_CR_DBG_STANDBY | DBGMCU_CR_TRACE_IOEN | - DBGMCU_CR_TRACE_MODE_ASYNC); // Enable async tracing + + stlink_write_debug32(stlink, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | + STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT); + stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA); + stlink_write_debug32(stlink, STLINK_REG_CM3_FP_CTRL, STLINK_REG_CM3_FP_CTRL_KEY); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION0, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION1, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION2, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION3, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL, 0); + stlink_write_debug32(stlink, STLINK_REG_DBGMCU_CR, STLINK_REG_DBGMCU_CR_DBG_SLEEP | + STLINK_REG_DBGMCU_CR_DBG_STOP | + STLINK_REG_DBGMCU_CR_DBG_STANDBY | + STLINK_REG_DBGMCU_CR_TRACE_IOEN | + STLINK_REG_DBGMCU_CR_TRACE_MODE_ASYNC); if (stlink_trace_enable(stlink, trace_frequency)) { ELOG("Unable to turn on tracing in stlink\n"); @@ -302,31 +248,35 @@ static bool enable_trace(stlink_t* stlink, const st_settings_t* settings, uint32 return false; } - stlink_write_debug32(stlink, TPI_CSPSR, TPI_TPI_CSPSR_PORT_SIZE_1); + stlink_write_debug32(stlink, STLINK_REG_TPI_CSPSR, STLINK_REG_TPI_CSPSR_PORT_SIZE_1); if (settings->core_frequency) { uint32_t prescaler = settings->core_frequency / trace_frequency - 1; - if (prescaler > TPI_ACPR_MAX) { + if (prescaler > STLINK_REG_TPI_ACPR_MAX) { ELOG("Trace frequency prescaler %d out of range. Try setting a faster trace frequency.\n", prescaler); if (!settings->force) return false; } - stlink_write_debug32(stlink, TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor - } - stlink_write_debug32(stlink, TPI_FFCR, TPI_FFCR_TRIG_IN); - stlink_write_debug32(stlink, TPI_SPPR, TPI_SPPR_SWO_NRZ); - stlink_write_debug32(stlink, ITM_LAR, ITM_LAR_KEY); - stlink_write_debug32(stlink, ITM_TCC, 0x00000400); // Set sync counter - stlink_write_debug32(stlink, ITM_TCR, ITM_TCR_TRACE_BUS_ID_1 | ITM_TCR_TS_ENA | ITM_TCR_ITM_ENA); - stlink_write_debug32(stlink, ITM_TER, ITM_TER_PORTS_ALL); - stlink_write_debug32(stlink, ITM_TPR, ITM_TPR_PORTS_ALL); - stlink_write_debug32(stlink, DWT_CTRL, 4 * DWT_CTRL_NUM_COMP | DWT_CTRL_CYC_TAP | - 0xF * DWT_CTRL_POST_INIT | 0xF * DWT_CTRL_POST_PRESET | - DWT_CTRL_CYCCNT_ENA); - stlink_write_debug32(stlink, DCB_DEMCR, DEMCR_TRCENA); + stlink_write_debug32(stlink, STLINK_REG_TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor + } + stlink_write_debug32(stlink, STLINK_REG_TPI_FFCR, STLINK_REG_TPI_FFCR_TRIG_IN); + stlink_write_debug32(stlink, STLINK_REG_TPI_SPPR, STLINK_REG_TPI_SPPR_SWO_NRZ); + stlink_write_debug32(stlink, STLINK_REG_ITM_LAR, STLINK_REG_ITM_LAR_KEY); + stlink_write_debug32(stlink, STLINK_REG_ITM_TCC, 0x00000400); // Set sync counter + stlink_write_debug32(stlink, STLINK_REG_ITM_TCR, STLINK_REG_ITM_TCR_TRACE_BUS_ID_1 | + STLINK_REG_ITM_TCR_TS_ENA | + STLINK_REG_ITM_TCR_ITM_ENA); + stlink_write_debug32(stlink, STLINK_REG_ITM_TER, STLINK_REG_ITM_TER_PORTS_ALL); + stlink_write_debug32(stlink, STLINK_REG_ITM_TPR, STLINK_REG_ITM_TPR_PORTS_ALL); + stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL, 4 * STLINK_REG_DWT_CTRL_NUM_COMP | + STLINK_REG_DWT_CTRL_CYC_TAP | + 0xF * STLINK_REG_DWT_CTRL_POST_INIT | + 0xF * STLINK_REG_DWT_CTRL_POST_PRESET | + STLINK_REG_DWT_CTRL_CYCCNT_ENA); + stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA); uint32_t prescaler; - stlink_read_debug32(stlink, TPI_ACPR, &prescaler); + stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR_MAX, &prescaler); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; @@ -483,7 +433,7 @@ static void check_for_configuration_error(stlink_t* stlink, st_trace_t* trace, u if (error_no_data || error_low_data || error_bad_data) { uint32_t prescaler; - stlink_read_debug32(stlink, TPI_ACPR, &prescaler); + stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR, &prescaler); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index fdea175d3..6d2c9f1af 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -3,8 +3,9 @@ #define STLINK_REG_CM3_CPUID 0xE000ED00 -#define STLINK_REG_CM3_FP_CTRL 0xE0002000 +#define STLINK_REG_CM3_FP_CTRL 0xE0002000 // Flash Patch Control Register #define STLINK_REG_CM3_FP_COMPn(n) (0xE0002008 + n*4) +#define STLINK_REG_CM3_FP_CTRL_KEY (1 << 1) #define STLINK_REG_CM7_FP_LAR 0xE0000FB0 #define STLINK_REG_CM7_FP_LAR_KEY 0xC5ACCE55 @@ -39,6 +40,55 @@ #define STLINK_REG_DHCSR_S_RESET_ST (1 << 25) #define STLINK_REG_DCRSR 0xe000edf4 #define STLINK_REG_DCRDR 0xe000edf8 +#define STLINK_REG_DEMCR 0xe000edfc +#define STLINK_REG_DEMCR_TRCENA (1 << 24) + +/* MCU Debug Component Registers */ +#define STLINK_REG_DBGMCU_CR 0xE0042004 // Debug MCU Configuration Register +#define STLINK_REG_DBGMCU_CR_DBG_SLEEP (1 << 0) +#define STLINK_REG_DBGMCU_CR_DBG_STOP (1 << 1) +#define STLINK_REG_DBGMCU_CR_DBG_STANDBY (1 << 2) +#define STLINK_REG_DBGMCU_CR_TRACE_IOEN (1 << 5) +#define STLINK_REG_DBGMCU_CR_TRACE_MODE_ASYNC (0x00 << 6) + +/* Data Watchpoint and Trace (DWT) Registers */ +#define STLINK_REG_DWT_CTRL 0xE0001000 // DWT Control Register +#define STLINK_REG_DWT_CTRL_NUM_COMP (1 << 28) +#define STLINK_REG_DWT_CTRL_CYC_TAP (1 << 9) +#define STLINK_REG_DWT_CTRL_POST_INIT (1 << 5) +#define STLINK_REG_DWT_CTRL_POST_PRESET (1 << 1) +#define STLINK_REG_DWT_CTRL_CYCCNT_ENA (1 << 0) +#define STLINK_REG_DWT_FUNCTION0 0xE0001028 // DWT Function Register 0 +#define STLINK_REG_DWT_FUNCTION1 0xE0001038 // DWT Function Register 1 +#define STLINK_REG_DWT_FUNCTION2 0xE0001048 // DWT Function Register 2 +#define STLINK_REG_DWT_FUNCTION3 0xE0001058 // DWT Function Register 3 + +/* Instrumentation Trace Macrocell (ITM) Registers */ +#define STLINK_REG_ITM_TER 0xE0000E00 // ITM Trace Enable Register +#define STLINK_REG_ITM_TER_PORTS_ALL (0xFFFFFFFF) +#define STLINK_REG_ITM_TPR 0xE0000E40 // ITM Trace Privilege Register +#define STLINK_REG_ITM_TPR_PORTS_ALL (0x0F) +#define STLINK_REG_ITM_TCR 0xE0000E80 // ITM Trace Control Register +#define STLINK_REG_ITM_TCR_TRACE_BUS_ID_1 (0x01 << 16) +#define STLINK_REG_ITM_TCR_SWO_ENA (1 << 4) +#define STLINK_REG_ITM_TCR_DWT_ENA (1 << 3) +#define STLINK_REG_ITM_TCR_SYNC_ENA (1 << 2) +#define STLINK_REG_ITM_TCR_TS_ENA (1 << 1) +#define STLINK_REG_ITM_TCR_ITM_ENA (1 << 0) +#define STLINK_REG_ITM_TCC 0xE0000E90 // ITM Trace Cycle Count +#define STLINK_REG_ITM_LAR 0xE0000FB0 // ITM Lock Access Register +#define STLINK_REG_ITM_LAR_KEY 0xC5ACCE55 + +/* Trace Port Interface (TPI) Registers */ +#define STLINK_REG_TPI_CSPSR 0xE0040004 // TPI Current Parallel Port Size Reg +#define STLINK_REG_TPI_CSPSR_PORT_SIZE_1 (0x01 << 0) +#define STLINK_REG_TPI_ACPR 0xE0040010 // TPI Async Clock Prescaler Register +#define STLINK_REG_TPI_ACPR_MAX (0x1FFF) +#define STLINK_REG_TPI_SPPR 0xE00400F0 // TPI Selected Pin Protocol Register +#define STLINK_REG_TPI_SPPR_SWO_MANCHESTER (0x01 << 0) +#define STLINK_REG_TPI_SPPR_SWO_NRZ (0x02 << 0) +#define STLINK_REG_TPI_FFCR 0xE0040304 // TPI Formatter and Flush Control Register +#define STLINK_REG_TPI_FFCR_TRIG_IN (0x01 << 8) /* Application Interrupt and Reset Control Register */ #define STLINK_REG_AIRCR 0xe000ed0c From 08a8474e3dea10a12a9f9b21885b8cdee0bb4a7a Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 7 Dec 2020 10:52:23 -0800 Subject: [PATCH 1087/1435] Removing unused variable warning. --- src/st-trace/trace.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 7f586c7c2..7b31900a2 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -91,6 +91,7 @@ static void abort_trace() { #if defined(_WIN32) BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { + (void)fdwCtrlType; abort_trace(); return FALSE; } From d5c63c3b111381d6d58d47f8f05ccc485fa1c494 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 7 Dec 2020 11:06:59 -0800 Subject: [PATCH 1088/1435] Moving has_dual_bank into the flags field. --- inc/stlink.h | 1 - src/common.c | 34 +++++++++++++++++----------------- src/stlink-lib/chipid.c | 9 +++------ src/stlink-lib/chipid.h | 4 ++-- 4 files changed, 22 insertions(+), 26 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index ef61fd1ba..d66cd74fb 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -198,7 +198,6 @@ struct _stlink { enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx - bool has_dual_bank; stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() size_t flash_size; // calculated by stlink_load_device_params() diff --git a/src/common.c b/src/common.c index a9e907c60..ec9f19b4a 100644 --- a/src/common.c +++ b/src/common.c @@ -511,7 +511,7 @@ static void unlock_flash(stlink_t *sl) { key_reg = STM32WB_FLASH_KEYR; } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { key_reg = FLASH_H7_KEYR1; - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { key2_reg = FLASH_H7_KEYR2; } } else { @@ -575,7 +575,7 @@ static void lock_flash(stlink_t *sl) { cr_lock_shift = STM32WB_FLASH_CR_LOCK; } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr2_reg = FLASH_H7_CR2; } cr_lock_shift = FLASH_H7_CR_LOCK; @@ -691,7 +691,7 @@ static int lock_flash_option(stlink_t *sl) { case STLINK_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - if (sl->has_dual_bank) + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) optcr2_reg = FLASH_H7_OPTCR2; break; default: @@ -759,7 +759,7 @@ static int unlock_flash_option(stlink_t *sl) { break; case STLINK_FLASH_TYPE_H7: optkey_reg = FLASH_H7_OPT_KEYR; - if (sl->has_dual_bank) + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) optkey2_reg = FLASH_H7_OPT_KEYR2; break; default: @@ -907,7 +907,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); } @@ -1034,7 +1034,7 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank)) { + (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); } @@ -1085,13 +1085,13 @@ static int check_flash_error(stlink_t *sl) break; case STLINK_FLASH_TYPE_H7: res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; } if (res) { // Clear errors stlink_write_debug32(sl, FLASH_H7_CCR1, res); - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { stlink_write_debug32(sl, FLASH_H7_CCR2, res); } } @@ -1355,7 +1355,6 @@ int stlink_load_device_params(stlink_t *sl) { } sl->flash_type = params->flash_type; - sl->has_dual_bank = params->has_dual_bank; sl->flash_pgsz = params->flash_pagesize; sl->sram_size = params->sram_size; sl->sys_base = params->bootrom_base; @@ -1378,8 +1377,9 @@ int stlink_load_device_params(stlink_t *sl) { } // H7 devices with small flash has one bank - if (sl->has_dual_bank && sl->flash_type == STLINK_FLASH_TYPE_H7) { - sl->has_dual_bank = (flash_size/sl->flash_pgsz) > 1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && sl->flash_type == STLINK_FLASH_TYPE_H7) { + if ((flash_size/sl->flash_pgsz) <= 1) + sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; } #if 0 @@ -2621,7 +2621,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_id != STLINK_CHIPID_STM32_H7AX) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); } } @@ -2630,7 +2630,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { set_flash_cr_strt(sl, BANK_1); // start erase operation, reset by hw with busy bit if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank)) { + (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 } @@ -2642,7 +2642,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { // reset the mass erase bit set_flash_cr_mer(sl, 0, BANK_1); if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank)) { + (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 0, BANK_2); } @@ -2872,13 +2872,13 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { unlock_flash_if(sl); // unlock the cr set_flash_cr_pg(sl, BANK_1); // set programming mode - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { set_flash_cr_pg(sl, BANK_2); } if (sl->chip_id != STLINK_CHIPID_STM32_H7AX) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->has_dual_bank) { + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); } } @@ -3047,7 +3047,7 @@ int stlink_flashloader_stop(stlink_t *sl) { (sl->flash_type == STLINK_FLASH_TYPE_H7)) { clear_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->has_dual_bank) { + if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { clear_flash_cr_pg(sl, BANK_2); } lock_flash(sl); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index dc3218261..425cc17d5 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -631,7 +631,6 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_G4_CAT3, .description = "G4 Category-3", .flash_type = STLINK_FLASH_TYPE_G4, - .has_dual_bank = true, .flash_size_reg = 0x1FFF75E0, // Section 47.2 .flash_pagesize = 0x800, // 2k (sec 3.3.1) // SRAM1 is 80k at 0x20000000 @@ -642,7 +641,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { // STM32WB55 (from RM0434) @@ -661,7 +660,6 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_H74XXX, .description = "H74x/H75x", .flash_type = STLINK_FLASH_TYPE_H7, - .has_dual_bank = true, .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) .flash_pagesize = 0x20000, // 128k sector (pg147) .sram_size = 0x20000, // 128k "DTCM" from Table 7 @@ -669,14 +667,13 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 - .flags = CHIP_F_HAS_SWO_TRACING, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { // STM32H7A3/7B3 (from RM0455) .chip_id = STLINK_CHIPID_STM32_H7AX, .description = "H7Ax/H7Bx", .flash_type = STLINK_FLASH_TYPE_H7, - .has_dual_bank = true, .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) .flash_pagesize = 0x2000, // 8k sector (p.146) .sram_size = 0x20000, // 128k "DTCM" (Figure 1) @@ -684,7 +681,7 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to two banks (Table 12-14) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, - .flags = CHIP_F_HAS_SWO_TRACING, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { // STM32H72x/H73x (from RM0468) diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 5fee49f87..f790e7899 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -70,7 +70,8 @@ enum stlink_stm32_chipids { }; -#define CHIP_F_HAS_SWO_TRACING (1 << 0) +#define CHIP_F_HAS_DUAL_BANK (1 << 0) +#define CHIP_F_HAS_SWO_TRACING (1 << 1) /** Chipid parameters */ @@ -78,7 +79,6 @@ struct stlink_chipid_params { uint32_t chip_id; char *description; enum stlink_flash_type flash_type; - bool has_dual_bank; uint32_t flash_size_reg; uint32_t flash_pagesize; uint32_t sram_size; From cbd2633e64b93644eeec2fefdd10729d1fa02ff2 Mon Sep 17 00:00:00 2001 From: John Hall Date: Mon, 7 Dec 2020 11:10:19 -0800 Subject: [PATCH 1089/1435] Fixing binary compatibility with the stlink structure. --- inc/stlink.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/inc/stlink.h b/inc/stlink.h index d66cd74fb..9b5e56594 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -194,7 +194,6 @@ struct _stlink { char serial[STLINK_SERIAL_MAX_SIZE]; int serial_size; int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR - uint32_t max_trace_freq; // set by stlink_open_usb() enum stlink_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx @@ -220,6 +219,8 @@ struct _stlink { struct stlink_version_ version; uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx + + uint32_t max_trace_freq; // set by stlink_open_usb() }; int stlink_enter_swd_mode(stlink_t *sl); From 4cf8b79099ca28cf97be76b5fdf60e2e83bd06d2 Mon Sep 17 00:00:00 2001 From: John Hall Date: Wed, 9 Dec 2020 14:03:18 -0800 Subject: [PATCH 1090/1435] Fixing build on clang. --- src/st-trace/trace.c | 2 +- src/stlink-lib/helper.c | 2 +- src/stlink-lib/usb.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 7b31900a2..549a1a385 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -410,7 +410,7 @@ static bool read_trace(stlink_t* stlink, st_trace_t* trace) { static void check_for_configuration_error(stlink_t* stlink, st_trace_t* trace, uint32_t trace_frequency) { // Only check configuration one time after the first 10 seconds of running. - uint32_t elapsed_time_s = time(NULL) - trace->start_time; + time_t elapsed_time_s = time(NULL) - trace->start_time; if (trace->configuration_checked || elapsed_time_s < 10) { return; } diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index 8b2c8e8f7..32d9b6c8d 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -11,5 +11,5 @@ unsigned time_ms() { struct timeval tv; gettimeofday(&tv, NULL); - return (unsigned)tv.tv_sec * 1000 + tv.tv_usec / 1000; + return (unsigned)(tv.tv_sec * 1000 + tv.tv_usec / 1000); } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index ec0720a03..caf31e280 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1109,7 +1109,7 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { return -1; } - size_t trace_count = read_uint16(sl->q_buf, 0); + uint16_t trace_count = read_uint16(sl->q_buf, 0); if (trace_count > size) { ELOG("read_trace insufficient buffer length\n"); From 95e9c36a85cefa9ca5cfa033dd9a9fe238a2f40d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 13 Dec 2020 00:04:11 +0100 Subject: [PATCH 1091/1435] General Project Update - Mention support for VS Code (Closes #1057) - Compilation with GCC 11 fails (Closes #1077) - Updated list of contributors - Updated CHANGELOG.md --- CHANGELOG.md | 2 ++ README.md | 11 ++++++----- contributors.txt | 1 + src/st-util/gdb-server.c | 2 +- 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 4c178a4e4..eed8b8546 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -40,6 +40,8 @@ Fixes: * st-util: wrong register values passed to gdb (st-link v2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027)) * [doc] Fixed wrong path for rules.d folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) * Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) +* Fixed gettimeofday for MSVC ([#1074](https://github.com/stlink-org/stlink/pull/1074)) +* Fixed compilation with GCC 11 ([#1077](https://github.com/stlink-org/stlink/pull/1077)) v1.6.1 diff --git a/README.md b/README.md index 350c36e34..6bb99b892 100644 --- a/README.md +++ b/README.md @@ -42,11 +42,11 @@ On the user level there is no difference in handling or operation between these The STlink toolset includes: -* a communication library (libstlink.a), -* a programmer and chip information tool (st-info), -* a flash manipulation tool (st-flash), -* a GDB server (st-util) and -* a GUI-Interface (stlink-gui) _[optional]_ +* `libstlink` - a communication library +* `st-info` - a programmer and chip information tool +* `st-flash` - a flash manipulation tool +* `st-util` - a GDB server (supported in Visual Studio Code / VSCodium via the [Cortex-Debug](https://github.com/Marus/cortex-debug) plugin +* `stlink-gui` - a GUI-Interface [optional]_ ## Supported operating systems and hardware combinations @@ -58,6 +58,7 @@ Supported operating systems are listed in [version_support.md](doc/version_suppo The `stlink` toolset continues to maintain backwards compatibility with the **STLINK/v1** programmer.
      Please note that on macOS this support is limited to versions 10.13 - 10.15. + ## Tutorial & HOWTO Our [tutorial](doc/tutorial.md) may help you along with some advanced tasks and additional info. diff --git a/contributors.txt b/contributors.txt index 65b53aed1..57801b9ab 100644 --- a/contributors.txt +++ b/contributors.txt @@ -64,6 +64,7 @@ Jim Paris Jiří Netolický Jerry Nosky [jnosky] Jochen Wilhelmy [Jochen0x90h] +John Hall [simplerobot] Joel Bodenmann [Tectu] Johannes Taelman Jonas Danielsson diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index c47a3a9f3..4177cef11 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -43,7 +43,7 @@ static stlink_t *connected_stlink = NULL; static bool semihosting = false; static bool serial_specified = false; -static char serialnumber[28] = {0}; +static char serialnumber[STLINK_SERIAL_MAX_SIZE] = {0}; #if defined(_WIN32) #define close_socket win32_close_socket From a66557a102d48e69feb0a9746e8e42c4baf31fe2 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 13 Dec 2020 16:58:48 +0100 Subject: [PATCH 1092/1435] [doc] STM32F103 fake chips (Closes #1024) --- doc/tutorial.md | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/doc/tutorial.md b/doc/tutorial.md index 7b8b1d461..1d20c68ee 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -78,6 +78,28 @@ to ensure that the rules actually take effect. Using the trigger command means t If the VID:PID of your device doesn't match those in any of the 3 files, then you may need to create a custom rule file to match your VID:PID. +### b) NOTE: Chinese Fake-Chips CKS32F103C8T6 or CS32F103C8T6 being marked as "STM32F103C8T6" + +In contrast to "Clone chips" which identify themselves as such by their official marking (manufacturer, model, etc.), so called "Fake chips" do not. +Instead counterfeiters try to copy the outer appearance of the original and thus are very hard to detect. +Possible malfunction then may lead to various effects and issues during operation also in in connection with this toolset. + +As of December 2019 several so called "Bluepill-Boards" with a STM32F103C8T6 appeared on the market that do not hold the original part. +In this known example one finds the counterfeited "STM32F103C8T6" MCUs to identify themselves with chip-id `0x2ba01477` instead of `0x1ba01477`. + +In the following you find some hints on how to identify your chip and track down fraud: + +* [How to Detect STM32 Fakes](https://www.cnx-software.com/2020/03/22/how-to-detect-stm32-fakes/) +* [Confirmation by STMicroelectronics](https://www.mikrocontroller.net/attachment/442839/couterfeit_STM.png) (Marking: 991KA 93 MYS 807) + +However it appears that not all counterfeited parts cause problems during operation, but some are known to not even being able to execute a basic "blinky" example binary. Further there can be problems that may not even show up or affect you directly, but somewhen later in time (or maybe never). +This demonstrates there is no guarantee for a proper working chip with equal functionality compared to the original. + +Please keep this in mind and be sceptical when facing problems with this type of boards. +Check your hardware and try to identify what you have in front of you before assuming a bug in the `stlink` toolset. + +Please let us know, if you come across any further websites or tutorials that help to identify STM32 fake chips so we can list them here to help others. + ------ ( Content below is currently unrevised and may be outdated as of Apr 2020. ) From 0b7b1f3b03814a6d09d389697cc420a9de335a3c Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 19 Dec 2020 14:41:26 +0200 Subject: [PATCH 1093/1435] fix msvc build --- CMakeLists.txt | 1 + src/st-trace/trace.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index f5c450e93..064aa06d5 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -249,6 +249,7 @@ if (MSVC) # Add getopt to sources include_directories(src/win32/getopt) set(ST-UTIL_SOURCES "${ST-UTIL_SOURCES};src/win32/getopt/getopt.c") + set(ST-TRACE_SOURCES "${ST-TRACE_SOURCES};src/win32/getopt/getopt.c") endif () add_executable(st-flash ${ST-FLASH_SOURCES}) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 549a1a385..e737e4d4a 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -552,7 +552,7 @@ int main(int argc, char** argv) } ILOG("Reading Trace\n"); - st_trace_t trace = {}; + st_trace_t trace = {0}; trace.start_time = time(NULL); if (stlink_run(stlink)) { From ffbecc4800c2053cf172cdeffa3c9772cb3d9636 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 19 Dec 2020 15:33:03 +0200 Subject: [PATCH 1094/1435] use memset for init struct --- src/st-trace/trace.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index e737e4d4a..ee35a5923 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -552,7 +552,8 @@ int main(int argc, char** argv) } ILOG("Reading Trace\n"); - st_trace_t trace = {0}; + st_trace_t trace; + memset(&trace, 0, sizeof(trace)); trace.start_time = time(NULL); if (stlink_run(stlink)) { From e8c1e8a120cafa0a773ef6b93a3617087f322650 Mon Sep 17 00:00:00 2001 From: Luuk van Dijk Date: Sun, 20 Dec 2020 22:53:00 +0100 Subject: [PATCH 1095/1435] correctly handle endianness without reference to host platform --- src/common.c | 72 ++++++++++++---------------------------------------- 1 file changed, 16 insertions(+), 56 deletions(-) diff --git a/src/common.c b/src/common.c index ec9f19b4a..aaa2462a1 100644 --- a/src/common.c +++ b/src/common.c @@ -349,49 +349,32 @@ #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 + +// Endianness +// https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html +// These functions encode and decode little endian uint16 and uint32 values. + void write_uint32(unsigned char* buf, uint32_t ui) { - if (!is_bigendian()) { // le -> le (don't swap) - buf[0] = ((unsigned char*)&ui)[0]; - buf[1] = ((unsigned char*)&ui)[1]; - buf[2] = ((unsigned char*)&ui)[2]; - buf[3] = ((unsigned char*)&ui)[3]; - } else { - buf[0] = ((unsigned char*)&ui)[3]; - buf[1] = ((unsigned char*)&ui)[2]; - buf[2] = ((unsigned char*)&ui)[1]; - buf[3] = ((unsigned char*)&ui)[0]; - } + buf[0] = ui; + buf[1] = ui >> 8; + buf[2] = ui >> 16; + buf[3] = ui >> 24; } void write_uint16(unsigned char* buf, uint16_t ui) { - if (!is_bigendian()) { // le -> le (don't swap) - buf[0] = ((unsigned char*)&ui)[0]; - buf[1] = ((unsigned char*)&ui)[1]; - } else { - buf[0] = ((unsigned char*)&ui)[1]; - buf[1] = ((unsigned char*)&ui)[0]; - } + buf[0] = ui ; + buf[1] = ui >> 8; } uint32_t read_uint32(const unsigned char *c, const int pt) { - uint32_t ui; - char *p = (char *)&ui; - - if (!is_bigendian()) { // le -> le (don't swap) - p[0] = c[pt + 0]; - p[1] = c[pt + 1]; - p[2] = c[pt + 2]; - p[3] = c[pt + 3]; - } else { - p[0] = c[pt + 3]; - p[1] = c[pt + 2]; - p[2] = c[pt + 1]; - p[3] = c[pt + 0]; - } + return ((uint32_t)c[pt]) | ((uint32_t)c[pt+1] << 8) | ((uint32_t)c[pt+2] << 16) | ((uint32_t)c[pt+3] << 24) ; +} - return(ui); +uint16_t read_uint16(const unsigned char *c, const int pt) { + return ((uint16_t)c[pt]) | ((uint16_t)c[pt+1] << 8); } + static uint32_t get_stm32l0_flash_base(stlink_t *sl) { switch (sl->chip_id) { @@ -1779,30 +1762,7 @@ int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size) { // End of delegates.... Common code below here... -// Endianness -// http://www.ibm.com/developerworks/aix/library/au-endianc/index.html -// const int i = 1; -// #define is_bigendian() ( (*(char*)&i) == 0 ) - -unsigned int is_bigendian(void) { - static volatile const unsigned int i = 1; - return(*(volatile const char*)&i == 0); -} - -uint16_t read_uint16(const unsigned char *c, const int pt) { - uint32_t ui; - char *p = (char *)&ui; - if (!is_bigendian()) { // le -> le (don't swap) - p[0] = c[pt + 0]; - p[1] = c[pt + 1]; - } else { - p[0] = c[pt + 1]; - p[1] = c[pt + 0]; - } - - return(ui); -} // same as above with entrypoint. From ddac731929b0c879a9a6dc9e17811abc88b682c3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 25 Dec 2020 23:33:20 +0100 Subject: [PATCH 1096/1435] Minor formatting fixes --- CHANGELOG.md | 4 ++-- README.md | 6 +++--- src/st-trace/trace.c | 1 - src/stlink-lib/chipid.c | 2 +- 4 files changed, 6 insertions(+), 7 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index eed8b8546..ad13e46aa 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -317,13 +317,13 @@ Major changes and added features: * Added intel hex file reading for `st-flash` ([#110](https://github.com/stlink-org/stlink/pull/110), [#157](https://github.com/stlink-org/stlink/pull/157), [#457](https://github.com/stlink-org/stlink/pull/547), [#459](https://github.com/stlink-org/stlink/pull/549)) * Added support for ARM semihosting to `st-util` ([#147](https://github.com/stlink-org/stlink/pull/147), [#227](https://github.com/stlink-org/stlink/pull/227), [#454](https://github.com/stlink-org/stlink/pull/454), [#455](https://github.com/stlink-org/stlink/pull/455)) * Added manpages (generated with pandoc from Markdown) ([#208](https://github.com/stlink-org/stlink/pull/208), [#464](https://github.com/stlink-org/stlink/pull/464), [#466](https://github.com/stlink-org/stlink/pull/466), [#467](https://github.com/stlink-org/stlink/pull/467)) -* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/stlink-org/stlink/pull/228), ([#507](https://github.com/stlink-org/stlink/pull/507), commit [#3fd0f09](https://github.com/stlink-org/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) +* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/stlink-org/stlink/pull/228), [#507](https://github.com/stlink-org/stlink/pull/507), commit [#3fd0f09](https://github.com/stlink-org/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) * Support serial numbers argument for `st-util` and `st-flash` to probe and control multiple connected programmers ([#318](https://github.com/stlink-org/stlink/pull/318), [#398](https://github.com/stlink-org/stlink/pull/398), [#541](https://github.com/stlink-org/stlink/pull/541)) * Merge st-probe tool into st-info ([#398](https://github.com/stlink-org/stlink/pull/398)) * Added support for native debian packaging ([#444](https://github.com/stlink-org/stlink/pull/444), [#472](https://github.com/stlink-org/stlink/pull/472), [#473](https://github.com/stlink-org/stlink/pull/473), [#482](https://github.com/stlink-org/stlink/pull/482), [#483](https://github.com/stlink-org/stlink/pull/483), [#484](https://github.com/stlink-org/stlink/pull/484), [#485](https://github.com/stlink-org/stlink/pull/485)) * Rewritten commandline parsing for `st-flash` ([#459](https://github.com/stlink-org/stlink/pull/459)) * Added `--reset` command to `st-flash` ([#505](https://github.com/stlink-org/stlink/pull/505)) -* st-util should detect when USB commands fail ([#525](https://github.com/stlink-org/stlink/pull/525), ([#527](https://github.com/stlink-org/stlink/pull/527), ([#528](https://github.com/stlink-org/stlink/pull/528)) +* st-util should detect when USB commands fail ([#525](https://github.com/stlink-org/stlink/pull/525), [#527](https://github.com/stlink-org/stlink/pull/527), [#528](https://github.com/stlink-org/stlink/pull/528)) Chip support added for: diff --git a/README.md b/README.md index 6bb99b892..d401f2c5d 100644 --- a/README.md +++ b/README.md @@ -42,11 +42,11 @@ On the user level there is no difference in handling or operation between these The STlink toolset includes: -* `libstlink` - a communication library * `st-info` - a programmer and chip information tool * `st-flash` - a flash manipulation tool -* `st-util` - a GDB server (supported in Visual Studio Code / VSCodium via the [Cortex-Debug](https://github.com/Marus/cortex-debug) plugin -* `stlink-gui` - a GUI-Interface [optional]_ +* `st-util` - a GDB server (supported in Visual Studio Code / VSCodium via the [Cortex-Debug](https://github.com/Marus/cortex-debug) plugin) +* `stlink-lib` - a communication library +* `stlink-gui` - a GUI-Interface _[optional]_ ## Supported operating systems and hardware combinations diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index ee35a5923..71ba6b360 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -571,4 +571,3 @@ int main(int argc, char** argv) return APP_RESULT_SUCCESS; } - diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 425cc17d5..221234bbb 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -11,7 +11,7 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // No flash pages .sram_size = 0x80000, // "SRAM" byte size in hex from .bootrom_base = 0x00200000, // ! "System memory" starting address from - .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from + .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 .option_size = 0x20, .flags = CHIP_F_HAS_SWO_TRACING, From 4bfaab0ea993fe86da9f2aef612036adcf8ef58d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 4 Jan 2021 00:53:24 +0100 Subject: [PATCH 1097/1435] Removed support for STLINK/v1 on macOS 10.13 --- README.md | 2 +- stlinkv1_macos_driver/install.sh | 5 +- .../Contents/Info.plist | 82 ------------- .../Contents/MacOS/stlink_shield_10_13 | Bin 33840 -> 0 bytes .../stlink_shield_10_13.kext/Contents/PkgInfo | 1 - .../Contents/_CodeSignature/CodeResources | 115 ------------------ .../Contents/Info.plist | 2 +- .../Contents/MacOS/stlink_shield_10_14 | Bin 33840 -> 33840 bytes .../Contents/Info.plist | 2 +- .../Contents/MacOS/stlink_shield_10_15 | Bin 33840 -> 33840 bytes .../stlink_shield.xcodeproj/project.pbxproj | 95 +-------------- .../contents.xcworkspacedata | 2 +- .../UserInterfaceState.xcuserstate | Bin 185319 -> 187405 bytes .../WorkspaceSettings.xcsettings | 6 +- .../xcschemes/stlink_shield_10.13.xcscheme | 67 ---------- .../xcschemes/xcschememanagement.plist | 34 +----- 16 files changed, 17 insertions(+), 396 deletions(-) delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/Info.plist delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/MacOS/stlink_shield_10_13 delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/PkgInfo delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/_CodeSignature/CodeResources delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.13.xcscheme diff --git a/README.md b/README.md index d401f2c5d..3799f46d2 100644 --- a/README.md +++ b/README.md @@ -36,7 +36,7 @@ It supports several so called STLINK programmer boards (and clones thereof) whic - transport layer: raw USB commands - stand-alone programmer -_*)_ **Note: Support on macOS is limited to 10.13 - 10.15. Any later versions are no longer compatible with the STLINK/v1 due to technical reasons.** +_*)_ **Note: Support on macOS is limited to 10.14 - 10.15. Any later versions are no longer compatible with the STLINK/v1 due to technical reasons.** On the user level there is no difference in handling or operation between these different revisions. diff --git a/stlinkv1_macos_driver/install.sh b/stlinkv1_macos_driver/install.sh index 19e9f141d..5716281a1 100644 --- a/stlinkv1_macos_driver/install.sh +++ b/stlinkv1_macos_driver/install.sh @@ -2,15 +2,12 @@ ISMACOS=$(sw_vers -productVersion) case $ISMACOS in -10.13*) - KEXT="stlink_shield_10_13.kext" - ;; 10.14*) KEXT="stlink_shield_10_14.kext" ;; 10.15*) KEXT="stlink_shield_10_15.kext" - ;; + ;; *) echo "OS X version not supported." exit 1 diff --git a/stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/Info.plist b/stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/Info.plist deleted file mode 100644 index fc759b362..000000000 --- a/stlinkv1_macos_driver/stlink_shield_10_13.kext/Contents/Info.plist +++ /dev/null @@ -1,82 +0,0 @@ - - - - - BuildMachineOSBuild - 18G4032 - CFBundleDevelopmentRegion - English - CFBundleIdentifier - com.libusb.stlink-shield - CFBundleInfoDictionaryVersion - 6.0 - CFBundlePackageType - KEXT - CFBundleSignature - ???? - CFBundleSupportedPlatforms - - MacOSX - - CFBundleVersion - 1.0.0 - DTCompiler - com.apple.compilers.llvm.clang.1_0 - DTPlatformBuild - 11C504 - DTPlatformVersion - GM - DTSDKBuild - 19B90 - DTSDKName - macosx10.15 - DTXcode - 1130 - DTXcodeBuild - 11C504 - IOKitPersonalities - - DeviceDriver - - CFBundleIdentifier - com.apple.kpi.iokit - IOClass - IOService - IOProviderClass - IOUSBDevice - bcdDevice - 256 - idProduct - 14148 - idVendor - 1155 - - InterfaceDriver - - CFBundleIdentifier - com.apple.kpi.iokit - IOClass - IOService - IOProviderClass - IOUSBInterface - bConfigurationValue - 1 - bInterfaceNumber - 0 - idProduct - 14148 - idVendor - 1155 - - - LSMinimumSystemVersion - 10.13 - OSBundleLibraries - - com.apple.iokit.IOUSBFamily - 1.8 - com.apple.kpi.libkern - 11.2.0 - - - diff --git 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1000 - - ^Resources/.*\.lproj/locversion.plist$ - - omit - - weight - 1100 - - ^Resources/Base\.lproj/ - - weight - 1010 - - ^version.plist$ - - - rules2 - - .*\.dSYM($|/) - - weight - 11 - - ^(.*/)?\.DS_Store$ - - omit - - weight - 2000 - - ^(Frameworks|SharedFrameworks|PlugIns|Plug-ins|XPCServices|Helpers|MacOS|Library/(Automator|Spotlight|LoginItems))/ - - nested - - weight - 10 - - ^.* - - ^Info\.plist$ - - omit - - weight - 20 - - ^PkgInfo$ - - omit - - weight - 20 - - ^Resources/ - - weight - 20 - - ^Resources/.*\.lproj/ - - optional - - weight - 1000 - - ^Resources/.*\.lproj/locversion.plist$ - - omit - - weight - 1100 - - ^Resources/Base\.lproj/ - - weight - 1010 - - ^[^/]+$ - - nested - - weight - 10 - - ^embedded\.provisionprofile$ - - weight - 20 - - ^version\.plist$ - - weight - 20 - - - - diff --git a/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist b/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist index d43deca2b..fd424ea93 100644 --- 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UseAppPreferences + UseTargetSettings + BuildSystemType + Latest CustomBuildIntermediatesPath Build/Intermediates.noindex CustomBuildLocationType @@ -13,7 +15,7 @@ DerivedDataLocationStyle Default IssueFilterStyle - ShowActiveSchemeOnly + ShowAll LiveSourceIssuesEnabled SharedBuildFolderName diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.13.xcscheme b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.13.xcscheme deleted file mode 100644 index d98dd9b97..000000000 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.13.xcscheme +++ /dev/null @@ -1,67 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist index d23112ec9..c9d1a75b6 100644 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist +++ b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist @@ -4,45 +4,15 @@ SchemeUserState - stlink_shield 10.7.xcscheme_^#shared#^_ - - orderHint - 2 - - stlink_shield copy copy.xcscheme_^#shared#^_ - - orderHint - 3 - - stlink_shield copy.xcscheme_^#shared#^_ - - orderHint - 2 - - stlink_shield.xcscheme_^#shared#^_ - - orderHint - 1 - - stlink_shield_10.13.xcscheme_^#shared#^_ - - orderHint - 0 - - stlink_shield_10.14 copy.xcscheme_^#shared#^_ - - orderHint - 4 - stlink_shield_10.14.xcscheme_^#shared#^_ orderHint - 1 + 0 stlink_shield_10.15.xcscheme_^#shared#^_ orderHint - 2 + 1 SuppressBuildableAutocreation From 9fd7e63ec2bcb79ba70521a4918bdf3bfe492adc Mon Sep 17 00:00:00 2001 From: Sebastiaan de Schaetzen Date: Thu, 14 Jan 2021 11:45:49 +0100 Subject: [PATCH 1098/1435] flash_loader: increase wait rounds for slow boards --- src/stlink-lib/flash_loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index b7726e875..b55953406 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -368,7 +368,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe * the OS uses, the wait until the error message is reduced to the same order of magnitude * as what was intended. -- REW. */ -#define WAIT_ROUNDS 30 +#define WAIT_ROUNDS 40 // wait until done (reaches breakpoint) for (i = 0; i < WAIT_ROUNDS; i++) { From 1b29c6529d8723f35afd92dd108988f996d5dcde Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 20 Feb 2021 20:26:39 +0200 Subject: [PATCH 1099/1435] check format string for log messages --- src/common.c | 64 +++++++++++++++++++-------------------- src/st-util/semihosting.c | 6 ++-- src/stlink-lib/logging.h | 16 +++++++--- src/stlink-lib/sg.c | 4 +-- src/stlink-lib/usb.c | 2 +- 5 files changed, 49 insertions(+), 43 deletions(-) diff --git a/src/common.c b/src/common.c index aaa2462a1..99049196d 100644 --- a/src/common.c +++ b/src/common.c @@ -1373,9 +1373,9 @@ int stlink_load_device_params(stlink_t *sl) { sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, (unsigned int)sl->flash_pgsz); #else - ILOG("%s: %zd KiB SRAM, %zd KiB flash in at least %zd %s pages.\n", - params->description, sl->sram_size / 1024, sl->flash_size / 1024, - (sl->flash_pgsz < 1024) ? sl->flash_pgsz : sl->flash_pgsz / 1024, + ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", + params->description, (unsigned)(sl->sram_size / 1024), (unsigned)(sl->flash_size / 1024), + (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) : (unsigned)(sl->flash_pgsz / 1024), (sl->flash_pgsz < 1024) ? "byte" : "KiB"); #endif return(0); @@ -1398,7 +1398,7 @@ int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { DLOG("*** stlink_soft_reset %s***\n", halt_on_reset?"(halt) ":""); - // halt core and enable debugging (if not already done) + // halt core and enable debugging (if not already done) // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); @@ -1585,7 +1585,7 @@ int stlink_target_voltage(stlink_t *sl) { voltage = sl->backend->target_voltage(sl); if (voltage != -1) { - DLOG("target voltage = %ldmV\n", voltage); + DLOG("target voltage = %imV\n", voltage); } else { DLOG("error reading target voltage\n"); } @@ -2201,8 +2201,8 @@ static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg* the_ int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size) { // read size bytes from addr to file - ILOG("read from address %#010x size %d\n", addr, size); - + ILOG("read from address %#010x size %u\n", addr, (unsigned)size); + int error; int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); @@ -2565,7 +2565,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { stm32_addr_t addr = (stm32_addr_t)sl->flash_base + i * (stm32_addr_t)sl->flash_pgsz; if (stlink_erase_flash_page(sl, addr) == -1) { - WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr); + WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); return(-1); } @@ -2701,7 +2701,7 @@ int stm32l1_write_half_pages( for (count = 0; count < num_half_pages; count++) { if (stlink_flash_loader_run( sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) { - WLOG("l1_stlink_flash_loader_run(%#zx) failed! == -1\n", addr + count * pagesize); + WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", addr + count * pagesize); stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); @@ -2734,7 +2734,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { (sl->flash_type == STLINK_FLASH_TYPE_F7) || (sl->flash_type == STLINK_FLASH_TYPE_L4)) { ILOG("Starting Flash write for F2/F4/F7/L4\n"); - + // Flash loader initialisation if (stlink_flash_loader_init(sl, fl) == -1) { ELOG("stlink_flash_loader_init() == -1\n"); @@ -2750,7 +2750,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { } else { voltage = stlink_target_voltage(sl); } - + if (voltage == -1) { ELOG("Failed to read Target voltage\n"); return(-1); @@ -2771,7 +2771,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { "using 8-bit flash writes\n", voltage); write_flash_cr_psiz(sl, 0, BANK_1); } - } + } // set programming mode set_flash_cr_pg(sl, BANK_1); @@ -2850,7 +2850,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { return(0); } -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len) { size_t off; if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || @@ -2860,7 +2860,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr for (off = 0; off < len;) { size_t size = len - off > buf_size ? buf_size : len - off; if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { - ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (unsigned)(addr + off)); return(-1); } @@ -2921,7 +2921,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr // write remaining word in program memory for ( ; off < len; off += sizeof(uint32_t)) { uint32_t data; - + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", (unsigned int)(off / sl->flash_pgsz), @@ -2955,7 +2955,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr DLOG("Finished unlocking flash, running loader!\n"); if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { - ELOG("stlink_flash_loader_run(%#zx) failed! == -1\n", addr + off); + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (unsigned)(addr + off)); return(-1); } @@ -3003,7 +3003,7 @@ int stlink_flashloader_stop(stlink_t *sl) { (sl->flash_type == STLINK_FLASH_TYPE_L4) || (sl->flash_type == STLINK_FLASH_TYPE_WB) || (sl->flash_type == STLINK_FLASH_TYPE_G0) || - (sl->flash_type == STLINK_FLASH_TYPE_G4) || + (sl->flash_type == STLINK_FLASH_TYPE_G4) || (sl->flash_type == STLINK_FLASH_TYPE_H7)) { clear_flash_cr_pg(sl, BANK_1); @@ -3056,9 +3056,9 @@ int stlink_write_flash( WLOG("unaligned len 0x%x -- padding with zero\n", len); len += 1; } else if (addr & (sl->flash_pgsz - 1)) { - ELOG("addr not a multiple of current pagesize (%zd bytes), not supported, " + ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " "check page start address and compare with flash module organisation " - "in related ST reference manual of your device.\n", sl->flash_pgsz); + "in related ST reference manual of your device.\n", (unsigned)(sl->flash_pgsz)); return(-1); } @@ -3071,7 +3071,7 @@ int stlink_write_flash( for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + (uint32_t)off)) { // addr must be an addr inside the page if (stlink_erase_flash_page(sl, addr + (uint32_t)off) == -1) { - ELOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); + ELOG("Failed to erase_flash_page(%#x) == -1\n", (unsigned)(addr + off)); return(-1); } @@ -3079,8 +3079,8 @@ int stlink_write_flash( page_count++; } - ILOG("Finished erasing %d pages of %d (%#x) bytes\n", - page_count, sl->flash_pgsz, sl->flash_pgsz); + ILOG("Finished erasing %d pages of %u (%#x) bytes\n", + page_count, (unsigned)(sl->flash_pgsz), (unsigned)(sl->flash_pgsz)); if (eraseonly) { return(0); } @@ -3092,7 +3092,7 @@ int stlink_write_flash( return ret; ret = stlink_flashloader_stop(sl); if (ret) - return ret; + return ret; return(stlink_verify_write_flash(sl, addr, base, len)); } @@ -3145,7 +3145,7 @@ int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, data = calloc(*size, 1); // use calloc to get NULL if out of memory if (!data) { - ELOG("Cannot allocate %d bytes\n", *size); + ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); res = -1; break; } @@ -3520,7 +3520,7 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t* base, stm32_addr_ addr = FLASH_F7_OPTCR; ILOG("No address provided, using %#10x\n", addr); } - + if ( addr == FLASH_F7_OPTCR ) { /* write option byte, ensuring we dont lock opt, and set strt bit */ stlink_write_debug32(sl, FLASH_F7_OPTCR, (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); @@ -3542,7 +3542,7 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t* base, stm32_addr_ ret = check_flash_error(sl); if (!ret) ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t*) base, addr); - + /* option bytes are reloaded at reset only, no obl. */ return ret; @@ -3899,7 +3899,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui return(-1); } - + if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { ELOG("Option bytes start address out of Option bytes range\n"); return(-1); @@ -3972,7 +3972,7 @@ static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option ILOG("Asked to write option control register 1 %#10x to %#010x.\n", option_control_register, FLASH_F7_OPTCR); //write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); //ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); - + /* write option byte, ensuring we dont lock opt, and set strt bit */ stlink_write_debug32(sl, FLASH_F7_OPTCR, (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); @@ -3981,7 +3981,7 @@ static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option ret = check_flash_error(sl); if (!ret) ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, FLASH_F7_OPTCR1); - + return ret; } @@ -3997,11 +3997,11 @@ static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t optio ILOG("Asked to write option control register 1 %#010x to %#010x.\n", option_control_register1, FLASH_F7_OPTCR1); //write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); //ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); - + /* write option byte, ensuring we dont lock opt, and set strt bit */ uint32_t current_control_register_value; stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); - + /* write option byte */ stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); stlink_write_debug32(sl, FLASH_F7_OPTCR, (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); @@ -4011,7 +4011,7 @@ static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t optio ret = check_flash_error(sl); if (!ret) ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, FLASH_F7_OPTCR1); - + return ret; } diff --git a/src/st-util/semihosting.c b/src/st-util/semihosting.c index 821dcdbbb..32169c812 100644 --- a/src/st-util/semihosting.c +++ b/src/st-util/semihosting.c @@ -256,7 +256,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - DLOG("Semihosting: write(%d, target_addr:0x%08x, %zu)\n", fd, buffer_address, + DLOG("Semihosting: write(%d, target_addr:0x%08x, %u)\n", fd, buffer_address, buffer_len); *ret = (uint32_t)write(fd, buffer, buffer_len); @@ -305,7 +305,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - DLOG("Semihosting: read(%d, target_addr:0x%08x, %zu)\n", fd, buffer_address, + DLOG("Semihosting: read(%d, target_addr:0x%08x, %u)\n", fd, buffer_address, buffer_len); read_result = read(fd, buffer, buffer_len); @@ -399,7 +399,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { fd = (int)args[0]; offset = (off_t)args[1]; - DLOG("Semihosting: lseek(%d, %d, SEEK_SET)\n", fd, offset); + DLOG("Semihosting: lseek(%d, %d, SEEK_SET)\n", fd, (int)offset); *ret = (uint32_t)lseek(fd, offset, SEEK_SET); saved_errno = errno; diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index 78562b0d9..7f3994492 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -16,8 +16,14 @@ enum ugly_loglevel { UERROR = 20 }; +#if defined(__GNUC__) +#define PRINTF_ARRT __attribute__ ((format (printf, 3, 4))) +#else +#define PRINTF_ARRT +#endif + int ugly_init(int maximum_threshold); -int ugly_log(int level, const char *tag, const char *format, ...); +int ugly_log(int level, const char *tag, const char *format, ...) PRINTF_ARRT; int ugly_libusb_log_level(enum ugly_loglevel v); #define UGLY_LOG_FILE (strstr(__FILE__, "/") != NULL ? \ @@ -27,13 +33,13 @@ int ugly_libusb_log_level(enum ugly_loglevel v); // TODO: we need to write this in a more generic way, for now this should compile // on visual studio (See http://stackoverflow.com/a/8673872/1836746) #define DLOG_HELPER(format, ...) ugly_log(UDEBUG, UGLY_LOG_FILE, format, __VA_ARGS__) -#define DLOG(...) DLOG_HELPER(__VA_ARGS__, "") +#define DLOG(...) ugly_log(UDEBUG, UGLY_LOG_FILE, __VA_ARGS__) #define ILOG_HELPER(format, ...) ugly_log(UINFO, UGLY_LOG_FILE, format, __VA_ARGS__) -#define ILOG(...) ILOG_HELPER(__VA_ARGS__, "") +#define ILOG(...) ugly_log(UINFO, UGLY_LOG_FILE, __VA_ARGS__) #define WLOG_HELPER(format, ...) ugly_log(UWARN, UGLY_LOG_FILE, format, __VA_ARGS__) -#define WLOG(...) WLOG_HELPER(__VA_ARGS__, "") +#define WLOG(...) ugly_log(UWARN, UGLY_LOG_FILE, __VA_ARGS__) #define ELOG_HELPER(format, ...) ugly_log(UERROR, UGLY_LOG_FILE, format, __VA_ARGS__) -#define ELOG(...) ELOG_HELPER(__VA_ARGS__, "") +#define ELOG(...) ugly_log(UERROR, UGLY_LOG_FILE, __VA_ARGS__) #ifdef __cplusplus } diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index f66864c44..840466e75 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -161,7 +161,7 @@ static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { } sprintf(dbugp, "]\n"); - DLOG(dbugblah); + DLOG("%s",dbugblah); return(0); } @@ -274,7 +274,7 @@ static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t } if (transferred != sizeof(sense)) { - WLOG("received unexpected amount of sense: %d != %d\n", transferred, sizeof(sense)); + WLOG("received unexpected amount of sense: %d != %u\n", transferred, (unsigned)sizeof(sense)); } uint32_t received_tag; diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index caf31e280..0168834ca 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1442,7 +1442,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { if (ret < 0) { if (ret == LIBUSB_ERROR_ACCESS) { - ELOG("Could not open USB device %#06x:%#06x, access error.\n", desc.idVendor, desc.idProduct, ret); + ELOG("Could not open USB device %#06x:%#06x, access error.\n", desc.idVendor, desc.idProduct); } else { ELOG("Failed to open USB device %#06x:%#06x, libusb error: %d)\n", desc.idVendor, desc.idProduct, ret); } From d0416149e0761f3a541b0719f76be327bec26337 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 6 Mar 2021 17:36:26 +0100 Subject: [PATCH 1100/1435] General Project Update - Updated ISSUE_TEMPLATES - Updated .gitignore --- .github/ISSUE_TEMPLATE/bug-report.md | 12 ++++++------ .github/ISSUE_TEMPLATE/feature-request.md | 14 +++++++------- .gitignore | 5 ++++- 3 files changed, 17 insertions(+), 14 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index fc30f3993..d76943d1e 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -11,13 +11,13 @@ Thank you for giving feedback to the stlink project. - [ ] I made serious effort to avoid creating duplicate or nearly similar issue -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out each of the following items appropriate to your specific problem: +In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below and edit each item individually appropriate to your specific problem. -- Programmer/board type: [enter here] (e.g Stlink /v1, /v2, /v2-clone, /v2-1) -- Operating system and version: [enter here] (e.g Linux, Mac OS X, Windows) -- **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.1.0/git-c722056) -- Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) -- Target chip (and board if applicable): [enter here] (e.g STM32F402VG) +- [ ] Programmer/board type: (e.g ST-Link/v1, ST-Link/v2, ST-Link/v2-onboard, ST-Link/v3) +- [ ] Operating system: (e.g Linux, Mac OS X, Windows (with specific version)) +- [ ] Stlink tools version and/or git commit hash: (e.g v1.1.0/git-c722056) +- [ ] Stlink commandline tool name: (e.g `st-info`, `st-flash`, `st-util`) +- [ ] Target chip (and optional board): (e.g STM32F402VG (STM32Fxxx Discovery)) Futher we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: diff --git a/.github/ISSUE_TEMPLATE/feature-request.md b/.github/ISSUE_TEMPLATE/feature-request.md index 133b895b2..c6e236ce1 100644 --- a/.github/ISSUE_TEMPLATE/feature-request.md +++ b/.github/ISSUE_TEMPLATE/feature-request.md @@ -11,15 +11,15 @@ Thank you for giving feedback to the stlink project. - [ ] I made serious effort to avoid creating duplicate or nearly similar issue -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to fill out the check boxes below by setting a 'x' into the checkboxes ( [x] ) and edit each item appropriate to your specific problem. +In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below and edit each item individually appropriate to your specific request. -- [ ] Programmer/board type: e.g Stlink/v1, Stlink/v2, Stlink/v2-onboard -- [ ] Operating system: e.g Linux, Mac OS X, Windows (with specific version) -- [ ] Stlink tools version and/or git commit hash: e.g v1.1.0/git-c722056 -- [ ] Stlink commandline tool name: e.g `st-info`, `st-flash`, `st-util` -- [ ] Target chip (and optional board): e.g STM32F402VG (STM32Fxxx Discovery) +- [ ] Programmer/board type: (e.g ST-Link/v1, ST-Link/v2, ST-Link/v2-onboard, ST-Link/v3) +- [ ] Operating system: (e.g Linux, Mac OS X, Windows (with specific version)) +- [ ] Stlink tools version and/or git commit hash: (e.g v1.1.0/git-c722056) +- [ ] Stlink commandline tool name: (e.g `st-info`, `st-flash`, `st-util`) +- [ ] Target chip (and optional board): (e.g STM32F402VG (STM32Fxxx Discovery)) -Futher we kindly ask you to describe the detected problem as detailled as possible and to add debug output if available, by using the following template: +Futher we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: Commandline-Output: diff --git a/.gitignore b/.gitignore index 09b9b33de..e753cbe42 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,8 @@ build build-mingw +.cmake/ +.vscode/ +.project + obj-* *.user* -.project From 29be2cf26a0f9dce79f544d48f30b5dfa0568b98 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 8 Mar 2021 23:24:45 +0100 Subject: [PATCH 1101/1435] General Project Update - Updated CHANGELOG.md - Minor formatting & spelling fix - Minor corrections --- CHANGELOG.md | 1 + doc/devices_boards.md | 2 +- doc/flashloaders.md | 2 +- doc/version_support.md | 2 +- 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index ad13e46aa..d304ab616 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -128,6 +128,7 @@ Fixes: * [regression] Fixed sign-compare (size != rep_len) in usb.c ([#772](https://github.com/stlink-org/stlink/pull/772), [#869](https://github.com/stlink-org/stlink/pull/869), [#872](https://github.com/stlink-org/stlink/pull/872), [#891](https://github.com/stlink-org/stlink/pull/891)) * Fixed dead loop after an unexpected unplug ([#780](https://github.com/stlink-org/stlink/pull/780), [#812](https://github.com/stlink-org/stlink/pull/812), [#913](https://github.com/stlink-org/stlink/pull/913)) * Avoid re-define of O_BINARY on Windows ([#788](https://github.com/stlink-org/stlink/pull/788)) +* Fixed stlink lock-up when not connected to a device via JTAG / SWD ([#835](https://github.com/stlink-org/stlink/pull/835), [#943](https://github.com/stlink-org/stlink/pull/943)) * Fixed st-flash manpage read example ([#858](https://github.com/stlink-org/stlink/pull/858)) * Fixed stlink support with no mass storage ([#861](https://github.com/stlink-org/stlink/pull/861)) * Make Version.cmake more error-resistant ([#872](https://github.com/stlink-org/stlink/pull/872)) diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 4402839c5..97094b972 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -53,7 +53,7 @@ Tested boards [incl. STLink programmers]: | 0x430 | XL-Density | xF xG | | F101 | | F103 | | Tested boards [incl. STLink programmers]: -* STM32VL-Discovery (STM32F100RBT6) with STLink-v1 [v1, v2] +* STM32VL-Discovery (STM32F100RBT6) with STLink-v1 [v1], [v2] * STM32F103-Bluepill: C8Tx & R8xx [v2] * Nucleo-F103RB [v2-1] * HY-STM32 (STM32F103VETx) [v1, v2] diff --git a/doc/flashloaders.md b/doc/flashloaders.md index 6a7cb3504..b1208b6f5 100644 --- a/doc/flashloaders.md +++ b/doc/flashloaders.md @@ -6,7 +6,7 @@ The on-chip FLASH of STM32 needs to be written once a byte/half word/word/double As SRAM is usually less in size than FLASH, `stlink` only flashes one page (may be less if SRAM is insufficient) at a time. The whole flashing process may consist of server launches of flashloaders. -## The flahsing process +## The flashing process 1. `st-flash` loads compiled binary of corresponding flashloader to SRAM by calling `stlink_flash_loader_init` in `src/flash_loader.c` 2. `st-flash` erases corresponding flash page by calling `stlink_erase_flash_page` in `common.c`. diff --git a/doc/version_support.md b/doc/version_support.md index 43c201101..afa2d2bd7 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -21,7 +21,7 @@ Thus no user interaction regarding libusb is necessary. | homebrew | 1.0.23 | 3.17.0 | 3.24.18
      gtk+3 | 10.12 (Sierra)- 10.15 (Catalina) | | MacPorts | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | 10.6 (Snow Leopard) - 10.15 (Catalina) | -NOTE: In order to use a STLINK/v1 programmer on macOS, versions 10.13, 10.14 or 10.15 are required. +NOTE: In order to use a STLINK/v1 programmer on macOS, versions 10.14 or 10.15 are required. ### Linux-/Unix-based: From 70f68e1c62d61c970b937b44eb438f2f49b15dc4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 10 Mar 2021 16:06:51 +0100 Subject: [PATCH 1102/1435] Updated travis CI build settings. --- .travis.yml | 285 +++++++++++++++++++++++++++++----------------------- 1 file changed, 157 insertions(+), 128 deletions(-) diff --git a/.travis.yml b/.travis.yml index 17db35765..27fbec5f8 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,140 +1,169 @@ language: c jobs: - include: - ### 64-bit builds on AMD64 ### - - os: linux - dist: bionic - env: BADGE=linux - compiler: gcc-5 - addons: - apt: - sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-5', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - - os: linux - dist: bionic - env: BADGE=linux - compiler: gcc-9 - addons: - apt: - sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - - os: linux - dist: xenial - env: BADGE=linux - compiler: clang-3.7 - addons: - apt: - sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-xenial-3.7'] - packages: ['clang-3.7', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-6.0 - addons: - apt: - sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] - packages: ['clang-6.0', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-9 - addons: - apt: - sources: ['ubuntu-toolchain-r-test'] - packages: ['clang-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] + include: + ### 64-bit builds on AMD64 ### + - os: linux + dist: bionic + env: BADGE=linux + compiler: gcc-5 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["gcc-5", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + - os: linux + dist: bionic + env: BADGE=linux + compiler: gcc-9 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["gcc-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + - os: linux + dist: focal + env: BADGE=linux + compiler: gcc-10 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + - os: linux + dist: xenial + env: BADGE=linux + compiler: clang-3.7 + addons: + apt: + sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-xenial-3.7"] + packages: ["clang-3.7", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + - os: linux + dist: bionic + env: BADGE=linux + compiler: clang-6.0 + addons: + apt: + sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-bionic-6.0"] + packages: ["clang-6.0", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + - os: linux + dist: bionic + env: BADGE=linux + compiler: clang-9 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["clang-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + - os: linux + dist: focal + env: BADGE=linux + compiler: clang-10 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - - os: linux - dist: bionic - env: BADGE=linux-mingw - name: linux-mingw - compiler: gcc-9 - addons: - apt: - sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm', 'mingw-w64'] + - os: linux + dist: bionic + env: BADGE=linux-mingw + name: linux-mingw + compiler: gcc-9 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: + ["gcc-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - ### 32-bit builds on AMD64 ### - - os: linux - dist: bionic - env: BADGE=linux - compiler: gcc-5 - addons: - apt: - sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-5', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: bionic - env: BADGE=linux - compiler: gcc-9 - addons: - apt: - sources: ['ubuntu-toolchain-r-test'] - packages: ['gcc-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: xenial - env: BADGE=linux - compiler: clang-3.7 - addons: - apt: - sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-xenial-3.7'] - packages: ['clang-3.7', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-6.0 - addons: - apt: - sources: ['ubuntu-toolchain-r-test', 'llvm-toolchain-bionic-6.0'] - packages: ['clang-6.0', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-9 - addons: - apt: - sources: ['ubuntu-toolchain-r-test'] - packages: ['clang-9', 'libusb-1.0.0-dev', 'libgtk-3-dev', 'rpm'] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + ### 32-bit builds on AMD64 ### + - os: linux + dist: bionic + env: BADGE=linux + compiler: gcc-5 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["gcc-5", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + - os: linux + dist: bionic + env: BADGE=linux + compiler: gcc-9 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["gcc-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + - os: linux + dist: focal + env: BADGE=linux + compiler: gcc-10 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + - os: linux + dist: xenial + env: BADGE=linux + compiler: clang-3.7 + addons: + apt: + sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-xenial-3.7"] + packages: ["clang-3.7", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + - os: linux + dist: bionic + env: BADGE=linux + compiler: clang-6.0 + addons: + apt: + sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-bionic-6.0"] + packages: ["clang-6.0", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + - os: linux + dist: bionic + env: BADGE=linux + compiler: clang-9 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["clang-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - os: linux + dist: focal + env: BADGE=linux + compiler: clang-10 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - ### macOS ### - - os: osx - env: BADGE=osx - compiler: gcc - addons: - homebrew: - packages: - - gcc - - libusb - - gtk+3 - - os: osx - env: BADGE=osx - compiler: clang - addons: - homebrew: - packages: - - clang - - libusb - - gtk+3 - - ### Windows ### -# - os: windows -# env: BADGE=windows -# compiler: gcc + ### macOS ### + - os: osx + env: BADGE=osx + compiler: gcc + addons: + homebrew: + packages: + - gcc + - libusb + - gtk+3 + - os: osx + env: BADGE=osx + compiler: clang + addons: + homebrew: + packages: + - clang + - libusb + - gtk+3 script: - git fetch --tags - printenv - cmake --version - if [[ "$TRAVIS_OS_NAME" == "linux" ]] || [[ "$TRAVIS_OS_NAME" == "osx" ]]; then ./.travis.sh; fi -# - if [[ "$TRAVIS_OS_NAME" == "windows" ]]; then cmd.exe /C 'mingw64-build.bat'; fi From 8429ac078a783ee6d75db6bd8741eba732959c54 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 10 Mar 2021 16:09:10 +0100 Subject: [PATCH 1103/1435] Update and correction for compiling instructions --- doc/compiling.md | 57 ++++++++++++++++++++++-------------------------- 1 file changed, 26 insertions(+), 31 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index d8cb62ebb..07193f357 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -108,54 +108,50 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma ### Building +#### Installation: + 1. Change into the project source directory: `cd stlink` 2. Run `make clean` -- required by some linux variants. 3. Run `make release` to create the _Release_ target -4. Run `make debug` to create the _Debug_ target (_optional_)
      +4. Run `make install` to full install the package with complete system integration +5. Run `make debug` to create the _Debug_ target (_optional_)
      The debug target is only necessary in order to modify the sources and to run under a debugger. +6. Run `make package`to build a Debian Package. The generated packages can be found in the subdirectory `./build/dist`. -The top level Makefile is just a handy wrapper for: +As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. -##### MinGW64: -```sh -$ mkdir build && cd build -$ cmake -DCMAKE_BUILD_TYPE=release -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw64.cmake -S .. -$ make -``` +#### Removal: -##### MinGW32: +1. Run `make uninstall` to perform a clean uninstall of the package from the system. +2. Run `make clean` to clean the build-folder within the project source and remove all compiled and linked files and libraries. -```sh -$ mkdir build && cd build -$ cmake -DCMAKE_BUILD_TYPE=release -DCMAKE_TOOLCHAIN_FILE=./cmake/linux-mingw32.cmake -S .. -$ make -``` - -As an alternative you may also install -- to a user folder e.g `$HOME` with `cd build/Release && make install DESTDIR=$HOME` -- or system wide with `cd build/Release && sudo make install`. -When installing system-wide, the dynamic library cache needs to be updated with the command `ldconfig`. +### Cross-Building for Windows +Install the following packages from your package repository: -### Build a Debian Package +* `mingw-w64` +* `mingw-w64-common` +* `mingw-w64-i686-dev` +* `mingw-w64-x86-64-dev` -To build the debian package you need the following extra packages: `devscripts debhelper`. +After following the steps for installation above, proceed with from the build dircetory itself: ```sh -$ git archive --prefix=$(git describe)/ HEAD | bzip2 --stdout > ../libstlink_$(sed -En -e "s/.*\((.*)\).*/\1/" -e "1,1 p" debian/changelog).orig.tar.bz2 -$ debuild -uc -us +$ sudo sh ./cmake/packaging/windows/generate_binaries.sh ``` +The generated zip-packages can be found in the subdirectory `./build/dist`. + -### Set permissions with udev +### Set device access permissions and the role of udev By default most distributions don't allow access to USB devices. -Therefore make sure you install udev files which are necessary to run the tools without root permissions.
      -udev rules create devices nodes and set the group of these to `stlink`. +In this context udev rules, which create devices nodes, are necessary to run the tools without root permissions. +To achieve this you need to ensure that the group `plugdev` exists and the user who is trying to access these devices is a member of this group. -The rules are located in the subdirectory `config/udev/rules.d` within the sourcefolder and are automatically installed along with `sudo make install` on linux. +Within the sourcefolder of the project, these rules are located in the subdirectory `config/udev/rules.d` and are automatically installed along with `sudo make install` on linux. Afterwards it may be necessary to reload the udev rules: ```sh @@ -164,13 +160,12 @@ $ sudo udevadm control --reload-rules $ sudo udevadm trigger ``` -Udev will now create device node files `/dev/stlinkv2_XX`, `/dev/stlinkv1_XX`.
      -You need to ensure that the group `stlink` exists and the user who is trying to access these devices is a member of this group. +udev will now create device node files, e.g. `/dev/stlinkv3_XX`, `/dev/stlinkv2_XX`, `/dev/stlinkv1_XX`. -### Note on the use of STLink-v1 programmers (legacy): +### Special note on the use of STLink/V1 programmers (legacy): -As the STLINKv1's SCSI emulation is somehow broken, the best advice possibly is to tell your operating system to completely ignore it.
      +As the STLINKV1's SCSI emulation is somehow broken, the best advice possibly is to tell your operating system to completely ignore it.
      Choose one of the following options _before_ connecting the device to your computer: * `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` From dc6310b469132b2d4210de5fa266571c81df3d82 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 10 Mar 2021 16:45:57 +0100 Subject: [PATCH 1104/1435] Updated travis CI build settings - covered active Ubuntu LTS version trees - gcc: 5 / 6 / 10 - clang: 8 / 10 --- .travis.yml | 51 ++++++++++++++++++--------------------------------- 1 file changed, 18 insertions(+), 33 deletions(-) diff --git a/.travis.yml b/.travis.yml index 27fbec5f8..4437b3148 100644 --- a/.travis.yml +++ b/.travis.yml @@ -4,7 +4,7 @@ jobs: include: ### 64-bit builds on AMD64 ### - os: linux - dist: bionic + dist: xenial env: BADGE=linux compiler: gcc-5 addons: @@ -14,11 +14,11 @@ jobs: - os: linux dist: bionic env: BADGE=linux - compiler: gcc-9 + compiler: gcc-6 addons: apt: sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + packages: ["gcc-6", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - os: linux dist: focal env: BADGE=linux @@ -30,27 +30,19 @@ jobs: - os: linux dist: xenial env: BADGE=linux - compiler: clang-3.7 + compiler: clang-8 addons: apt: sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-xenial-3.7"] - packages: ["clang-3.7", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-6.0 - addons: - apt: - sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-bionic-6.0"] - packages: ["clang-6.0", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + packages: ["clang-8", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - os: linux dist: bionic env: BADGE=linux - compiler: clang-9 + compiler: clang-10 addons: apt: sources: ["ubuntu-toolchain-r-test"] - packages: ["clang-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - os: linux dist: focal env: BADGE=linux @@ -60,20 +52,21 @@ jobs: sources: ["ubuntu-toolchain-r-test"] packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + ### cross build on AMD64 ### - os: linux - dist: bionic + dist: focal env: BADGE=linux-mingw name: linux-mingw - compiler: gcc-9 + compiler: gcc-10 addons: apt: sources: ["ubuntu-toolchain-r-test"] packages: - ["gcc-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] + ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] ### 32-bit builds on AMD64 ### - os: linux - dist: bionic + dist: xenial env: BADGE=linux compiler: gcc-5 addons: @@ -85,11 +78,11 @@ jobs: - os: linux dist: bionic env: BADGE=linux - compiler: gcc-9 + compiler: gcc-6 addons: apt: sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + packages: ["gcc-6", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] before_install: - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - os: linux @@ -105,31 +98,23 @@ jobs: - os: linux dist: xenial env: BADGE=linux - compiler: clang-3.7 + compiler: clang-8 addons: apt: sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-xenial-3.7"] - packages: ["clang-3.7", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + packages: ["clang-8", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] before_install: - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - os: linux dist: bionic env: BADGE=linux - compiler: clang-6.0 + compiler: clang-10 addons: apt: sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-bionic-6.0"] - packages: ["clang-6.0", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] before_install: - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-9 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["clang-9", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] before_install: - os: linux dist: focal From 8f9c5430cbf70192a4b3072b2ba690800cc0d306 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 10 Mar 2021 23:57:10 +0100 Subject: [PATCH 1105/1435] Updated changelog --- CHANGELOG.md | 600 +++++++++++++++++++++++++-------------------------- 1 file changed, 292 insertions(+), 308 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index d304ab616..c4adaf2ba 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,51 +1,49 @@ -stlink ChangeLog -================ +# stlink ChangeLog -v1.6.2 -====== +# v1.6.2 Release date: (TBD) Features: -* Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) -* Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) -* Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) -* Use SetConsoleCtrlHandler for Windows ([#1021](https://github.com/stlink-org/stlink/pull/1021)) -* Increase STM32L0 option_size to 20 ([#1046](https://github.com/stlink-org/stlink/pull/1046)) -* st-util: Add specialized memory map for STM32H7 devices ([#1060](https://github.com/stlink-org/stlink/pull/1060)) -* Support for STM32F4 option bytes ([#1062](https://github.com/stlink-org/stlink/pull/1062)) -* Link for WIN32 & APPLE with stlink-static ([#1069](https://github.com/stlink-org/stlink/pull/1069)) -* Extended support for STM32H7 ([#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) -* ITM functionality for ST-Link V2 and STM32Fxx chipsets ([#136](https://github.com/stlink-org/stlink/pull/136), [#179](https://github.com/stlink-org/stlink/pull/179), [#815](https://github.com/stlink-org/stlink/pull/815), [#1072](https://github.com/stlink-org/stlink/pull/1072)) +- Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) +- Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) +- Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) +- Use SetConsoleCtrlHandler for Windows ([#1021](https://github.com/stlink-org/stlink/pull/1021)) +- Increase STM32L0 `option_size` to 20 ([#1046](https://github.com/stlink-org/stlink/pull/1046)) +- `st-util`: Add specialized memory map for STM32H7 devices ([#1060](https://github.com/stlink-org/stlink/pull/1060)) +- Support for STM32F4 option bytes ([#1062](https://github.com/stlink-org/stlink/pull/1062)) +- Link for WIN32 & APPLE with stlink-static ([#1069](https://github.com/stlink-org/stlink/pull/1069)) +- Extended support for STM32H7 ([#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) +- ITM functionality for STLink/V2 and STM32Fxx chipsets ([#136](https://github.com/stlink-org/stlink/pull/136), [#179](https://github.com/stlink-org/stlink/pull/179), [#815](https://github.com/stlink-org/stlink/pull/815), [#1072](https://github.com/stlink-org/stlink/pull/1072)) Updates & changes: -* [doc] st-flash --reset parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) -* [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) -* Imported debian pkg-settings ([#986](https://github.com/stlink-org/stlink/pull/986)) -* Add support for FreeBSD's libusb reimplementation ([#992](https://github.com/stlink-org/stlink/pull/992), [#993](https://github.com/stlink-org/stlink/pull/993)) -* [doc] Added example for output of 'st-info --probe' ([#1007](https://github.com/stlink-org/stlink/pull/1007), [#1049](https://github.com/stlink-org/stlink/pull/1049)) +- [doc] `st-flash --reset` parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) +- [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) +- Imported debian pkg-settings ([#986](https://github.com/stlink-org/stlink/pull/986)) +- Add support for FreeBSD's `libusb` reimplementation ([#992](https://github.com/stlink-org/stlink/pull/992), [#993](https://github.com/stlink-org/stlink/pull/993)) +- [doc] Added example for output of `st-info --probe` ([#1007](https://github.com/stlink-org/stlink/pull/1007), [#1049](https://github.com/stlink-org/stlink/pull/1049)) Fixes: -* [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) -* cmake compile failure with external CMAKE_MODULE_PATH set ([#962](https://github.com/stlink-org/stlink/pull/962)) -* doc/man: Fixed installation directory ([#970](https://github.com/stlink-org/stlink/pull/970)) -* Fixed installation path for desktop-file and icons ([#972](https://github.com/stlink-org/stlink/pull/972)) -* Fix for static linking of libssp ([#973](https://github.com/stlink-org/stlink/pull/973), [#974](https://github.com/stlink-org/stlink/pull/974)) -* Fixed connect under reset for st-flash and st-util ([#983](https://github.com/stlink-org/stlink/pull/983)) -* Fix for mmap() size_t overflow in st-flash ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) -* [regression] stlink-gui installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) -* st-util: wrong register values passed to gdb (st-link v2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027)) -* [doc] Fixed wrong path for rules.d folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) -* Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) -* Fixed gettimeofday for MSVC ([#1074](https://github.com/stlink-org/stlink/pull/1074)) -* Fixed compilation with GCC 11 ([#1077](https://github.com/stlink-org/stlink/pull/1077)) - - -v1.6.1 -====== +- [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) +- cmake compile failure with external `CMAKE_MODULE_PATH` set ([#962](https://github.com/stlink-org/stlink/pull/962)) +- doc/man: Fixed installation directory ([#970](https://github.com/stlink-org/stlink/pull/970)) +- Fixed installation path for desktop-file and icons ([#972](https://github.com/stlink-org/stlink/pull/972)) +- Fix for static linking of `libssp` ([#973](https://github.com/stlink-org/stlink/pull/973), [#974](https://github.com/stlink-org/stlink/pull/974)) +- [regression] Fixed wrong formatting for library install path ([#978](https://github.com/stlink-org/stlink/pull/978), [#1089](https://github.com/stlink-org/stlink/pull/1089)) +- Fixed installation of header files needed for compiling with `libstlink.so.1.6.1` ([#982](https://github.com/stlink-org/stlink/pull/982)) +- Fixed `connect under reset` for `st-flash` and `st-util` ([#983](https://github.com/stlink-org/stlink/pull/983)) +- Fix for `mmap() size_t overflow` in `st-flash` ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) +- [regression] `stlink-gui` installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) +- `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027)) +- [doc] Fixed wrong path for `rules.d` folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) +- Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) +- Fixed `gettimeofday` for MSVC ([#1074](https://github.com/stlink-org/stlink/pull/1074)) +- Fixed compilation with GCC 11 ([#1077](https://github.com/stlink-org/stlink/pull/1077)) + +# v1.6.1 Release date: 2020-06-01 @@ -53,364 +51,350 @@ This release drops support for some older operating systems. Check project READM Features: -* Basic compatibility for STLink-v3 programmer ([#271](https://github.com/stlink-org/stlink/pull/271), [#863](https://github.com/stlink-org/stlink/pull/863), [#954](https://github.com/stlink-org/stlink/pull/954)) +- Basic compatibility for STLink/V3 programmer ([#271](https://github.com/stlink-org/stlink/pull/271), [#863](https://github.com/stlink-org/stlink/pull/863), [#954](https://github.com/stlink-org/stlink/pull/954)) - Added support for JTAG command API v2 & distinguish protocol versions v1 and v2 - - Compatibility with the STLink-v3 firmware which dropped support for the previous API v1 - - As of firmware version J11 the ST-LINK-V1 programmer supports API v2 commands as well -* Display programmer serial when no target is connected ([#432](https://github.com/stlink-org/stlink/pull/432), [#933](https://github.com/stlink-org/stlink/pull/933), [#943](https://github.com/stlink-org/stlink/pull/943)) -* Added connect under reset to stlink_open_usb( ) ([#577](https://github.com/stlink-org/stlink/pull/577), [#963](https://github.com/stlink-org/stlink/pull/963)) -* Support for STM32L1, SM32L4 option bytes write ([#596](https://github.com/stlink-org/stlink/pull/596), [#844](https://github.com/stlink-org/stlink/pull/844), [#847](https://github.com/stlink-org/stlink/pull/847)) -* Added CMAKEFLAGS and install target ([#804](https://github.com/stlink-org/stlink/pull/804), [#935](https://github.com/stlink-org/stlink/pull/935)) -* Support for STM32G4 ([#822](https://github.com/stlink-org/stlink/pull/822)) -* Added aliased SRAM2 region in the L496 memory map ([#824](https://github.com/stlink-org/stlink/pull/824)) -* Improved support for STM32G0 ([#825](https://github.com/stlink-org/stlink/pull/825), [#850](https://github.com/stlink-org/stlink/pull/850), [#856](https://github.com/stlink-org/stlink/pull/856), [#857](https://github.com/stlink-org/stlink/pull/857)) -* Added postinst script with 'depmod -a' for 'make package' ([#845](https://github.com/stlink-org/stlink/pull/845), [#931](https://github.com/stlink-org/stlink/pull/931)) -* Calculate checksums for flash operations ([#862](https://github.com/stlink-org/stlink/pull/862), [#924](https://github.com/stlink-org/stlink/pull/924)) -* Adjust the JTAG/SWD frequency via cmdline option ([#893](https://github.com/stlink-org/stlink/pull/893), [#953](https://github.com/stlink-org/stlink/pull/953)) -* Added usb PID and udev rules for STlink v2.1 found on Nucleo-L432KC and Nucleo-L552ze boards ([#900](https://github.com/stlink-org/stlink/pull/900)) -* STM32G0/G4 improvements ([#910](https://github.com/stlink-org/stlink/pull/910)) + - Compatibility with the STLink/V3 firmware which dropped support for the previous API v1 + - As of firmware version J11 the STLink/V1 programmer supports API v2 commands as well +- Display programmer serial when no target is connected ([#432](https://github.com/stlink-org/stlink/pull/432), [#933](https://github.com/stlink-org/stlink/pull/933), [#943](https://github.com/stlink-org/stlink/pull/943)) +- Added `connect under reset` to `stlink_open_usb( )` ([#577](https://github.com/stlink-org/stlink/pull/577), [#963](https://github.com/stlink-org/stlink/pull/963)) +- Support for STM32L1, SM32L4 option bytes write ([#596](https://github.com/stlink-org/stlink/pull/596), [#844](https://github.com/stlink-org/stlink/pull/844), [#847](https://github.com/stlink-org/stlink/pull/847)) +- Added `CMAKEFLAGS` and install target ([#804](https://github.com/stlink-org/stlink/pull/804), [#935](https://github.com/stlink-org/stlink/pull/935)) +- Support for STM32G4 ([#822](https://github.com/stlink-org/stlink/pull/822)) +- Added aliased SRAM2 region in the L496 memory map ([#824](https://github.com/stlink-org/stlink/pull/824)) +- Improved support for STM32G0 ([#825](https://github.com/stlink-org/stlink/pull/825), [#850](https://github.com/stlink-org/stlink/pull/850), [#856](https://github.com/stlink-org/stlink/pull/856), [#857](https://github.com/stlink-org/stlink/pull/857)) +- Added postinst script with `depmod -a` for `make package` ([#845](https://github.com/stlink-org/stlink/pull/845), [#931](https://github.com/stlink-org/stlink/pull/931)) +- Calculate checksums for flash operations ([#862](https://github.com/stlink-org/stlink/pull/862), [#924](https://github.com/stlink-org/stlink/pull/924)) +- Adjust the JTAG/SWD frequency via cmdline option ([#893](https://github.com/stlink-org/stlink/pull/893), [#953](https://github.com/stlink-org/stlink/pull/953)) +- Added usb PID and udev rules for STLink/V2.1 found on Nucleo-L432KC and Nucleo-L552ze boards ([#900](https://github.com/stlink-org/stlink/pull/900)) +- STM32G0/G4 improvements ([#910](https://github.com/stlink-org/stlink/pull/910)) - Enable mass erase with a flash programming check - Handle G4 Cat3 devices with configurable dual bank flash by using a helper Updates & changes: -* [doc] Updated compiling instructions ([#113](https://github.com/stlink-org/stlink/pull/113), commit [#10ae529](https://github.com/stlink-org/stlink/commit/10ae5294cd03aacfc07312010f026d3cb12ea56c)) -* Defined libusb version compatibility for supported systems via LIBUSB_API_VERSION ([#211](https://github.com/stlink-org/stlink/pull/211), [#782](https://github.com/stlink-org/stlink/pull/782), [#895](https://github.com/stlink-org/stlink/pull/895)) -* Improved argument parsing for CLI tools ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) -* [doc] Updated tutorial: macOS ST-Link-v1 detection ([#574](https://github.com/stlink-org/stlink/pull/574), [#587](https://github.com/stlink-org/stlink/pull/587)) -* Enhanced error log with file path for map_file() ([#650](https://github.com/stlink-org/stlink/pull/650), [#879](https://github.com/stlink-org/stlink/pull/879), [#921](https://github.com/stlink-org/stlink/pull/921)) -* Enhanced output for error msg "addr not a multiple of pagesize, not supported" ([#663](https://github.com/stlink-org/stlink/pull/663), [#945](https://github.com/stlink-org/stlink/pull/945)) -* Updated STLink-v1 driver for macOS ([#735](https://github.com/stlink-org/stlink/pull/735), [#964](https://github.com/stlink-org/stlink/pull/964)) -* Package distribution: Provide Windows binaries via Debian-based cross-build ([#738](https://github.com/stlink-org/stlink/pull/738), [#795](https://github.com/stlink-org/stlink/pull/795), [#798](https://github.com/stlink-org/stlink/pull/798), [#870](https://github.com/stlink-org/stlink/pull/870), [#955](https://github.com/stlink-org/stlink/pull/955)) +- [doc] Updated compiling instructions ([#113](https://github.com/stlink-org/stlink/pull/113), commit [#10ae529](https://github.com/stlink-org/stlink/commit/10ae5294cd03aacfc07312010f026d3cb12ea56c)) +- Defined `libusb` version compatibility for supported systems via `LIBUSB_API_VERSION` ([#211](https://github.com/stlink-org/stlink/pull/211), [#782](https://github.com/stlink-org/stlink/pull/782), [#895](https://github.com/stlink-org/stlink/pull/895)) +- Improved argument parsing for CLI tools ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) +- [doc] Updated tutorial: macOS STLink/V1 detection ([#574](https://github.com/stlink-org/stlink/pull/574), [#587](https://github.com/stlink-org/stlink/pull/587)) +- Enhanced error log with file path for `map_file()` ([#650](https://github.com/stlink-org/stlink/pull/650), [#879](https://github.com/stlink-org/stlink/pull/879), [#921](https://github.com/stlink-org/stlink/pull/921)) +- Enhanced output for error msg `addr not a multiple of pagesize, not supported` ([#663](https://github.com/stlink-org/stlink/pull/663), [#945](https://github.com/stlink-org/stlink/pull/945)) +- Updated STLink/V1 driver for macOS ([#735](https://github.com/stlink-org/stlink/pull/735), [#964](https://github.com/stlink-org/stlink/pull/964)) +- Package distribution: Provide Windows binaries via Debian-based cross-build ([#738](https://github.com/stlink-org/stlink/pull/738), [#795](https://github.com/stlink-org/stlink/pull/795), [#798](https://github.com/stlink-org/stlink/pull/798), [#870](https://github.com/stlink-org/stlink/pull/870), [#955](https://github.com/stlink-org/stlink/pull/955)) - [refactoring] Update, corrections & cleanup for build settings (see #955 for details) - - New cpack package-config for DEB and RPM build - - Update for travis build configuration: builds for clang -m32, clang-9, MinGW-cross on linux + - New `cpack` package-config for DEB and RPM build + - Update for travis build configuration: builds for `clang -m32`, `clang-9`, MinGW-cross on linux - Updated steps for release preparation - Project contributors now listed in separate file - - Test files & gui now use shared stlink-library -* [doc] Verify correct udev configuration for device access ([#764](https://github.com/stlink-org/stlink/pull/764)) -* Added more error info to WLOGs during probe ([#883](https://github.com/stlink-org/stlink/pull/883)) -* [doc] Added missing documentation for stlink-gui ([#884](https://github.com/stlink-org/stlink/pull/884)) -* Added check for libssp during compilation ([#885](https://github.com/stlink-org/stlink/pull/885)) -* Silenced unnecessary messages ([#886](https://github.com/stlink-org/stlink/pull/886)) -* [doc] Defined libusb & cmake version compatibility ([#896](https://github.com/stlink-org/stlink/pull/896), [#897](https://github.com/stlink-org/stlink/pull/897), [#899](https://github.com/stlink-org/stlink/pull/899), commit [#27aa888](https://github.com/stlink-org/stlink/commit/27aa88821197d3ffe82baff4e971c3488ec39899)) -* Update for STM32G471/473/474/483/484 devices ([#901](https://github.com/stlink-org/stlink/pull/901)) -* [doc] st-flash --flash=n[k][m] command line option to override device model ([#902](https://github.com/stlink-org/stlink/pull/902)) -* [refactoring] Improved cmake build process ([#912](https://github.com/stlink-org/stlink/pull/912)) - - Set up a libusb log level accordingly to verbosity ([#894](https://github.com/stlink-org/stlink/pull/894) - - [compatibility] Updated libusb to v1.0.23 ([#895](https://github.com/stlink-org/stlink/pull/895) - - Updated compiling doc & version support ([#896](https://github.com/stlink-org/stlink/pull/896), [#897](https://github.com/stlink-org/stlink/pull/897), [#899](https://github.com/stlink-org/stlink/pull/899)) + - Test files & gui now use shared `stlink-library` +- [doc] Verify correct udev configuration for device access ([#764](https://github.com/stlink-org/stlink/pull/764)) +- Added more error info to `WLOGs` during probe ([#883](https://github.com/stlink-org/stlink/pull/883)) +- [doc] Added missing documentation for stlink-gui ([#884](https://github.com/stlink-org/stlink/pull/884)) +- Added check for `libssp` during compilation ([#885](https://github.com/stlink-org/stlink/pull/885)) +- Silenced unnecessary messages ([#886](https://github.com/stlink-org/stlink/pull/886)) +- [doc] Defined `libusb` & `cmake` version compatibility ([#896](https://github.com/stlink-org/stlink/pull/896), [#897](https://github.com/stlink-org/stlink/pull/897), [#899](https://github.com/stlink-org/stlink/pull/899), commit [#27aa888](https://github.com/stlink-org/stlink/commit/27aa88821197d3ffe82baff4e971c3488ec39899)) +- Update for STM32G471/473/474/483/484 devices ([#901](https://github.com/stlink-org/stlink/pull/901)) +- [doc] `st-flash --flash=n[k][m]` command line option to override device model ([#902](https://github.com/stlink-org/stlink/pull/902)) +- [refactoring] Improved cmake build process ([#912](https://github.com/stlink-org/stlink/pull/912)) + - Set up a `libusb` log level accordingly to verbosity ([#894](https://github.com/stlink-org/stlink/pull/894) + - [compatibility] Updated `libusb` to v1.0.23 ([#895](https://github.com/stlink-org/stlink/pull/895, [#1089](https://github.com/stlink-org/stlink/pull/1089)) + - Updated compiling doc & version support ([#896](https://github.com/stlink-org/stlink/pull/896), [#897](https://github.com/stlink-org/stlink/pull/897), [#899](https://github.com/stlink-org/stlink/pull/899)) - Version requirements & pkg-maintainer - Fixed install paths in build script - - Updated C-flag -std=gnu99 to gnu11) - - Added cmake uninstall target ([#619](https://github.com/stlink-org/stlink/pull/619), [#907](https://github.com/stlink-org/stlink/pull/907)) - - Integrated module GNUInstallDirs.cmake ([#557](https://github.com/stlink-org/stlink/pull/557)) + - Updated C-flag `-std=gnu99` to `gnu11`) + - Added `cmake` uninstall target ([#619](https://github.com/stlink-org/stlink/pull/619), [#907](https://github.com/stlink-org/stlink/pull/907)) + - Integrated module `GNUInstallDirs.cmake` ([#557](https://github.com/stlink-org/stlink/pull/557)) - [doc] Defined version compatibility and installation instructions for macOS - - [refactoring] libusb detection - - Deprecated old appveyor-mingw script -* [refactoring] BSD-License-compliant rewrite of flashloader source files ([#915](https://github.com/stlink-org/stlink/pull/915), [#932](https://github.com/stlink-org/stlink/pull/932)) -* [refactoring] Overall option code rework ([#927](https://github.com/stlink-org/stlink/pull/927)) -* [refactoring] Build settings / GUI-Build on UNIX-based systems if GTK3 is detected ([#929](https://github.com/stlink-org/stlink/pull/929)) -* [refactoring] Reconfiguration of package build process ([#931](https://github.com/stlink-org/stlink/pull/931), [#936](https://github.com/stlink-org/stlink/pull/936), [#940](https://github.com/stlink-org/stlink/pull/940), commit [#9b19f92](https://github.com/stlink-org/stlink/commit/9b19f9225460472af9d98959b7217d0a840ee972)) -* [refactoring] st-util: Removed now useless v1/v2 STLink version stuff ([#934](https://github.com/stlink-org/stlink/pull/934)) -* [refactoring] Cleanup for option bytes and flash settings ([#941](https://github.com/stlink-org/stlink/pull/941)) -* Added compilation guideline for MSVC toolchain ([#942](https://github.com/stlink-org/stlink/pull/942)) -* [refactoring] Cleanup of cmake build process ([#944](https://github.com/stlink-org/stlink/pull/944), [#946](https://github.com/stlink-org/stlink/pull/946), [#947](https://github.com/stlink-org/stlink/pull/947)) - - libusb package extraction no longer requires 7zip as an external unarchiver + - [refactoring] `libusb` detection + - Deprecated old `appveyor-mingw` script +- [refactoring] BSD-License-compliant rewrite of flashloader source files ([#915](https://github.com/stlink-org/stlink/pull/915), [#932](https://github.com/stlink-org/stlink/pull/932)) +- [refactoring] Overall option code rework ([#927](https://github.com/stlink-org/stlink/pull/927)) +- [refactoring] Build settings / GUI-Build on UNIX-based systems if `GTK3` is detected ([#929](https://github.com/stlink-org/stlink/pull/929)) +- [refactoring] Reconfiguration of package build process ([#931](https://github.com/stlink-org/stlink/pull/931), [#936](https://github.com/stlink-org/stlink/pull/936), [#940](https://github.com/stlink-org/stlink/pull/940), commit [#9b19f92](https://github.com/stlink-org/stlink/commit/9b19f9225460472af9d98959b7217d0a840ee972)) +- [refactoring] `st-util`: Removed now useless v1/v2 STLink version stuff ([#934](https://github.com/stlink-org/stlink/pull/934)) +- [refactoring] Cleanup for option bytes and flash settings ([#941](https://github.com/stlink-org/stlink/pull/941)) +- Added compilation guideline for MSVC toolchain ([#942](https://github.com/stlink-org/stlink/pull/942)) +- [refactoring] Cleanup of `cmake` build process ([#944](https://github.com/stlink-org/stlink/pull/944), [#946](https://github.com/stlink-org/stlink/pull/946), [#947](https://github.com/stlink-org/stlink/pull/947)) + - `libusb` package extraction no longer requires `7zip` as an external unarchiver Fixes: -* Fixed wait-loop for flash_loader_run() ([#290](https://github.com/stlink-org/stlink/pull/290)) -* Better argument parsing for CLI tools: stlink_open_usb can address v1, v2, v3 ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) -* Clear the PG bit before setting the PER bit ([#579](https://github.com/stlink-org/stlink/pull/579), [#876](https://github.com/stlink-org/stlink/pull/876)) -* Fixed compilation issues with int length on 32-bit platforms ([#629](https://github.com/stlink-org/stlink/pull/629), [#908](https://github.com/stlink-org/stlink/pull/908)) -* Fixed st-info --probe mechanism ([#679](https://github.com/stlink-org/stlink/pull/679), [#918](https://github.com/stlink-org/stlink/pull/918)) -* [regression] Fixed sign-compare (size != rep_len) in usb.c ([#772](https://github.com/stlink-org/stlink/pull/772), [#869](https://github.com/stlink-org/stlink/pull/869), [#872](https://github.com/stlink-org/stlink/pull/872), [#891](https://github.com/stlink-org/stlink/pull/891)) -* Fixed dead loop after an unexpected unplug ([#780](https://github.com/stlink-org/stlink/pull/780), [#812](https://github.com/stlink-org/stlink/pull/812), [#913](https://github.com/stlink-org/stlink/pull/913)) -* Avoid re-define of O_BINARY on Windows ([#788](https://github.com/stlink-org/stlink/pull/788)) -* Fixed stlink lock-up when not connected to a device via JTAG / SWD ([#835](https://github.com/stlink-org/stlink/pull/835), [#943](https://github.com/stlink-org/stlink/pull/943)) -* Fixed st-flash manpage read example ([#858](https://github.com/stlink-org/stlink/pull/858)) -* Fixed stlink support with no mass storage ([#861](https://github.com/stlink-org/stlink/pull/861)) -* Make Version.cmake more error-resistant ([#872](https://github.com/stlink-org/stlink/pull/872)) -* Error return in failed probe ([#887](https://github.com/stlink-org/stlink/pull/887), [#890](https://github.com/stlink-org/stlink/pull/890)) -* Fixed broken build on 32-bit systems ([#919](https://github.com/stlink-org/stlink/pull/919), [#920](https://github.com/stlink-org/stlink/pull/920)) -* st-flash: Minor usage fix and make cmdline parsing more user friendly ([#925](https://github.com/stlink-org/stlink/pull/925)) -* [regression] Restored functionality of make test builds ([#926](https://github.com/stlink-org/stlink/pull/926), [#929](https://github.com/stlink-org/stlink/pull/929)) -* Fixed compilation error due to uninitialized cpuid ([#937](https://github.com/stlink-org/stlink/pull/937), [#938](https://github.com/stlink-org/stlink/pull/938)) -* Fixes for STM32F0 flashloader ([#958](https://github.com/stlink-org/stlink/pull/958), [#959](https://github.com/stlink-org/stlink/pull/959)) -* Set static link for libssp (stack-smashing protection) ([#960](https://github.com/stlink-org/stlink/pull/960), [#961](https://github.com/stlink-org/stlink/pull/961)) -* Fixed udev rules installing to wrong directory ([#966](https://github.com/stlink-org/stlink/pull/966)) -* Fixed formatting for options display in st-flash & st-info (commits [#c783d0e](https://github.com/stlink-org/stlink/commit/c783d0e777ccc83a7a8be26a4f4d3414e0478560) and [#562cd24](https://github.com/stlink-org/stlink/commit/562cd2496e696dbd22950925866aac662d81ee5f)) - - -v1.6.0 -====== +- Fixed wait-loop for `flash_loader_run()` ([#290](https://github.com/stlink-org/stlink/pull/290)) +- Better argument parsing for CLI tools: `stlink_open_usb` can address v1, v2, v3 ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) +- Clear the PG bit before setting the `PER` bit ([#579](https://github.com/stlink-org/stlink/pull/579), [#876](https://github.com/stlink-org/stlink/pull/876)) +- Fixed compilation issues with int length on 32-bit platforms ([#629](https://github.com/stlink-org/stlink/pull/629), [#908](https://github.com/stlink-org/stlink/pull/908)) +- Fixed `st-info --probe` mechanism ([#679](https://github.com/stlink-org/stlink/pull/679), [#918](https://github.com/stlink-org/stlink/pull/918)) +- [regression] Fixed sign-compare (`size != rep_len`) in `usb.c` ([#772](https://github.com/stlink-org/stlink/pull/772), [#869](https://github.com/stlink-org/stlink/pull/869), [#872](https://github.com/stlink-org/stlink/pull/872), [#891](https://github.com/stlink-org/stlink/pull/891)) +- Fixed dead loop after an unexpected unplug ([#780](https://github.com/stlink-org/stlink/pull/780), [#812](https://github.com/stlink-org/stlink/pull/812), [#913](https://github.com/stlink-org/stlink/pull/913)) +- Avoid re-define of `O_BINARY` on Windows ([#788](https://github.com/stlink-org/stlink/pull/788)) +- Fixed stlink lock-up when not connected to a device via JTAG / SWD ([#835](https://github.com/stlink-org/stlink/pull/835), [#943](https://github.com/stlink-org/stlink/pull/943)) +- Fixed `st-flash` manpage read example ([#858](https://github.com/stlink-org/stlink/pull/858)) +- Fixed stlink support with no mass storage ([#861](https://github.com/stlink-org/stlink/pull/861)) +- Make `version.cmake` more error-resistant ([#872](https://github.com/stlink-org/stlink/pull/872)) +- Error return in failed probe ([#887](https://github.com/stlink-org/stlink/pull/887), [#890](https://github.com/stlink-org/stlink/pull/890)) +- Fixed broken build on 32-bit systems ([#919](https://github.com/stlink-org/stlink/pull/919), [#920](https://github.com/stlink-org/stlink/pull/920)) +- `st-flash`: Minor usage fix and make cmdline parsing more user friendly ([#925](https://github.com/stlink-org/stlink/pull/925)) +- [regression] Restored functionality of make test builds ([#926](https://github.com/stlink-org/stlink/pull/926), [#929](https://github.com/stlink-org/stlink/pull/929)) +- Fixed compilation error due to uninitialized cpuid ([#937](https://github.com/stlink-org/stlink/pull/937), [#938](https://github.com/stlink-org/stlink/pull/938)) +- Fixes for STM32F0 flashloader ([#958](https://github.com/stlink-org/stlink/pull/958), [#959](https://github.com/stlink-org/stlink/pull/959)) +- Set static link for `libssp` (stack-smashing protection) ([#960](https://github.com/stlink-org/stlink/pull/960), [#961](https://github.com/stlink-org/stlink/pull/961)) +- Fixed udev rules installing to wrong directory ([#966](https://github.com/stlink-org/stlink/pull/966)) +- Fixed formatting for options display in `st-flash` & `st-info` (commits [#c783d0e](https://github.com/stlink-org/stlink/commit/c783d0e777ccc83a7a8be26a4f4d3414e0478560) and [#562cd24](https://github.com/stlink-org/stlink/commit/562cd2496e696dbd22950925866aac662d81ee5f)) + +# v1.6.0 Release date: 2020-02-20 Major changes and added features: -* Initial support for STM32L41X ([#754](https://github.com/stlink-org/stlink/pull/754), [#799](https://github.com/stlink-org/stlink/pull/799)) -* Verified support for CKS32F103C8T6 and related CKS devices with Core-ID 0x2ba01477 ([#756](https://github.com/stlink-org/stlink/pull/756), [#757](https://github.com/stlink-org/stlink/pull/757), [#805](https://github.com/stlink-org/stlink/pull/805), [#834](https://github.com/stlink-org/stlink/pull/834), Regression-Fixes: [#761](https://github.com/stlink-org/stlink/pull/761), [#766](https://github.com/stlink-org/stlink/pull/766)) -* Added preliminary support for some STM32G0 chips ([#759](https://github.com/stlink-org/stlink/pull/759), [#760](https://github.com/stlink-org/stlink/pull/760), [#797](https://github.com/stlink-org/stlink/pull/797)) -* Added support for mass erasing second bank on STM32F10x_XL ([#767](https://github.com/stlink-org/stlink/pull/767), [#768](https://github.com/stlink-org/stlink/pull/768)) -* Added call to clear PG bit after writing to flash ([#773](https://github.com/stlink-org/stlink/pull/773)) -* Added support to write option bytes for the STM32G0 ([#778](https://github.com/stlink-org/stlink/pull/778)) -* Added support for STM32WB55 chips ([#786](https://github.com/stlink-org/stlink/pull/786), [#810](https://github.com/stlink-org/stlink/pull/810), [#816](https://github.com/stlink-org/stlink/pull/816)) -* Added STLink V3SET VID:PIDs to the udev rules ([#789](https://github.com/stlink-org/stlink/pull/789)) -* Support for "STM32+Audio" v2-1 firmware ([#790](https://github.com/stlink-org/stlink/pull/790)) -* Build for Windows under Debian/Ubuntu ([#802](https://github.com/stlink-org/stlink/pull/802)) -* Allow for 64 bytes serials ([#809](https://github.com/stlink-org/stlink/pull/809)) -* Added full support for STLINK CHIP ID L4RX ([#814](https://github.com/stlink-org/stlink/pull/814), [#839](https://github.com/stlink-org/stlink/pull/839)) -* Added support for the STLink-v2.1 when flashed with no mass storage (PID 0x3752) ([#819](https://github.com/stlink-org/stlink/pull/819), [#861](https://github.com/stlink-org/stlink/pull/861)) -* Added support for writing option bytes on STM32L0xx ([#830](https://github.com/stlink-org/stlink/pull/830)) -* Added support to read and write option bytes for STM32F2 series ([#836](https://github.com/stlink-org/stlink/pull/836), [#837](https://github.com/stlink-org/stlink/pull/837)) -* Added support to read and write option bytes for STM32F446 ([#843](https://github.com/stlink-org/stlink/pull/843)) +- Initial support for STM32L41X ([#754](https://github.com/stlink-org/stlink/pull/754), [#799](https://github.com/stlink-org/stlink/pull/799)) +- Verified support for CKS32F103C8T6 and related CKS devices with Core-ID 0x2ba01477 ([#756](https://github.com/stlink-org/stlink/pull/756), [#757](https://github.com/stlink-org/stlink/pull/757), [#805](https://github.com/stlink-org/stlink/pull/805), [#834](https://github.com/stlink-org/stlink/pull/834), Regression-Fixes: [#761](https://github.com/stlink-org/stlink/pull/761), [#766](https://github.com/stlink-org/stlink/pull/766)) +- Added preliminary support for some STM32G0 chips ([#759](https://github.com/stlink-org/stlink/pull/759), [#760](https://github.com/stlink-org/stlink/pull/760), [#797](https://github.com/stlink-org/stlink/pull/797)) +- Added support for mass erasing second bank on `STM32F10x_XL` ([#767](https://github.com/stlink-org/stlink/pull/767), [#768](https://github.com/stlink-org/stlink/pull/768)) +- Added call to clear `PG` bit after writing to flash ([#773](https://github.com/stlink-org/stlink/pull/773)) +- Added support to write option bytes for the STM32G0 ([#778](https://github.com/stlink-org/stlink/pull/778)) +- Added support for STM32WB55 chips ([#786](https://github.com/stlink-org/stlink/pull/786), [#810](https://github.com/stlink-org/stlink/pull/810), [#816](https://github.com/stlink-org/stlink/pull/816)) +- Added `STLink V3SET` VID:PIDs to the udev rules ([#789](https://github.com/stlink-org/stlink/pull/789)) +- Support for `STM32+Audio` v2-1 firmware ([#790](https://github.com/stlink-org/stlink/pull/790)) +- Build for Windows under Debian/Ubuntu ([#802](https://github.com/stlink-org/stlink/pull/802)) +- Allow for 64 bytes serials ([#809](https://github.com/stlink-org/stlink/pull/809)) +- Added full support for STLINK CHIP ID L4RX ([#814](https://github.com/stlink-org/stlink/pull/814), [#839](https://github.com/stlink-org/stlink/pull/839)) +- Added support for the STLink/V2.1 when flashed with no mass storage (PID 0x3752) ([#819](https://github.com/stlink-org/stlink/pull/819), [#861](https://github.com/stlink-org/stlink/pull/861)) +- Added support for writing option bytes on STM32L0xx ([#830](https://github.com/stlink-org/stlink/pull/830)) +- Added support to read and write option bytes for STM32F2 series ([#836](https://github.com/stlink-org/stlink/pull/836), [#837](https://github.com/stlink-org/stlink/pull/837)) +- Added support to read and write option bytes for STM32F446 ([#843](https://github.com/stlink-org/stlink/pull/843)) Updates and fixes: -* Fixed "unkown chip id", piped output and st-util -v ([#107](https://github.com/stlink-org/stlink/pull/107), [#665](https://github.com/stlink-org/stlink/pull/665), [#763](https://github.com/stlink-org/stlink/pull/763)) -* Fixed an issue with versioning stuck at 1.4.0 for versions cloned with git ([#563](https://github.com/stlink-org/stlink/pull/563), [#762](https://github.com/stlink-org/stlink/pull/762), [#772](https://github.com/stlink-org/stlink/pull/772)) -* Updated STM32F3xx chip ID that covers a few different devices ([#685](https://github.com/stlink-org/stlink/pull/685), [#758](https://github.com/stlink-org/stlink/pull/758)) -* Made udev rules and modprobe conf installation optional ([#741](https://github.com/stlink-org/stlink/pull/741)) -* Fixed case when __FILE__ don't contain "/" nor "\\" ([#745](https://github.com/stlink-org/stlink/pull/745)) -* Fixed double dash issue in doc/man ([#746](https://github.com/stlink-org/stlink/pull/746), [#747](https://github.com/stlink-org/stlink/pull/747)) -* Compiling documentation: package is called libusb-1.0-0-dev on Debian ([#748](https://github.com/stlink-org/stlink/pull/748)) -* Only do bank calculation on STM32L4 devices with dual banked flash / Added chip-ID 0x464 for STM32L41xxx/L42xxx devices ([#751](https://github.com/stlink-org/stlink/pull/751)) -* Added O_BINARY option to open file ([#753](https://github.com/stlink-org/stlink/pull/753)) -* Fixed versioning when compiling from the checked out git-repo ([#762](https://github.com/stlink-org/stlink/pull/762), [#772](https://github.com/stlink-org/stlink/pull/772)) -* win32: move usleep definition to unistd.h ([#765](https://github.com/stlink-org/stlink/pull/765)) -* Fixed relative path to the UI files needed by stlink-gui-local (GUI) ([#770](https://github.com/stlink-org/stlink/pull/770), [#771](https://github.com/stlink-org/stlink/pull/771)) -* Added howto for sending NRST signal through GDB ([#774](https://github.com/stlink-org/stlink/pull/774), [#776](https://github.com/stlink-org/stlink/pull/776), [#779](https://github.com/stlink-org/stlink/pull/779)) -* Fixed package name "devscripts" in doc/compiling.md ([#775](https://github.com/stlink-org/stlink/pull/775)) -* Fixed few potential memory/resource leaks ([#803](https://github.com/stlink-org/stlink/pull/803), [#831](https://github.com/stlink-org/stlink/pull/831)) -* Updated Linux source repositories in README.md: Debian and Ubuntu ([#821](https://github.com/stlink-org/stlink/pull/821), [#835](https://github.com/stlink-org/stlink/pull/835), [#859](https://github.com/stlink-org/stlink/pull/859)) -* Do not issue JTAG reset on stlink-v1 ([#828](https://github.com/stlink-org/stlink/pull/828)) -* Fixed flash size of STM32 Discovery vl ([#829](https://github.com/stlink-org/stlink/pull/829)) -* Updated documentation on software structure ([#851](https://github.com/stlink-org/stlink/pull/851)) +- Fixed `unkown chip id`, piped output and `st-util -v` ([#107](https://github.com/stlink-org/stlink/pull/107), [#665](https://github.com/stlink-org/stlink/pull/665), [#763](https://github.com/stlink-org/stlink/pull/763)) +- Fixed an issue with versioning stuck at 1.4.0 for versions cloned with git ([#563](https://github.com/stlink-org/stlink/pull/563), [#762](https://github.com/stlink-org/stlink/pull/762), [#772](https://github.com/stlink-org/stlink/pull/772)) +- Updated STM32F3xx chip ID that covers a few different devices ([#685](https://github.com/stlink-org/stlink/pull/685), [#758](https://github.com/stlink-org/stlink/pull/758)) +- Made udev rules and modprobe conf installation optional ([#741](https://github.com/stlink-org/stlink/pull/741)) +- Fixed case when `__FILE__` doesn't contain either `/` nor `\\` ([#745](https://github.com/stlink-org/stlink/pull/745)) +- Fixed double dash issue in doc/man ([#746](https://github.com/stlink-org/stlink/pull/746), [#747](https://github.com/stlink-org/stlink/pull/747)) +- Compiling documentation: package is called `libusb-1.0-0-dev` on Debian ([#748](https://github.com/stlink-org/stlink/pull/748)) +- Only do bank calculation on STM32L4 devices with dual banked flash / Added chip-ID 0x464 for STM32L41xxx/L42xxx devices ([#751](https://github.com/stlink-org/stlink/pull/751)) +- Added `O_BINARY` option to open file ([#753](https://github.com/stlink-org/stlink/pull/753)) +- Fixed versioning when compiling from the checked out git-repo ([#762](https://github.com/stlink-org/stlink/pull/762), [#772](https://github.com/stlink-org/stlink/pull/772)) +- win32: move usleep definition to `unistd.h` ([#765](https://github.com/stlink-org/stlink/pull/765)) +- Fixed relative path to the UI files needed by `stlink-gui-local` (GUI) ([#770](https://github.com/stlink-org/stlink/pull/770), [#771](https://github.com/stlink-org/stlink/pull/771)) +- Added howto for sending `NRST` signal through GDB ([#774](https://github.com/stlink-org/stlink/pull/774), [#776](https://github.com/stlink-org/stlink/pull/776), [#779](https://github.com/stlink-org/stlink/pull/779)) +- Fixed package name `devscripts` in doc/compiling.md ([#775](https://github.com/stlink-org/stlink/pull/775)) +- Fixed few potential memory/resource leaks ([#803](https://github.com/stlink-org/stlink/pull/803), [#831](https://github.com/stlink-org/stlink/pull/831)) +- Updated Linux source repositories in README.md: Debian and Ubuntu ([#821](https://github.com/stlink-org/stlink/pull/821), [#835](https://github.com/stlink-org/stlink/pull/835), [#859](https://github.com/stlink-org/stlink/pull/859)) +- Do not issue JTAG reset on STLink/V1 ([#828](https://github.com/stlink-org/stlink/pull/828)) +- Fixed flash size of STM32 Discovery VL ([#829](https://github.com/stlink-org/stlink/pull/829)) +- Updated documentation on software structure ([#851](https://github.com/stlink-org/stlink/pull/851)) General project updates: -* Updated README.md, CHANGELOG.md and issue templates (Nightwalker-87) -* Fixed travis build config file (Nightwalker-87) -* Added CODE_OF_CONDUCT (Nightwalker-87) -* Archived page from github project wiki to doc/wiki_old.md (Nightwalker-87) +- Updated `README.md`, `CHANGELOG.md` and issue templates (Nightwalker-87) +- Fixed travis build config file (Nightwalker-87) +- Added `CODE_OF_CONDUCT` (Nightwalker-87) +- Archived page from github project wiki to doc/wiki_old.md (Nightwalker-87) - -v1.5.1 -====== +# v1.5.1 Release date: 2018-09-13 Major changes and added features: -* Added reset through AIRCR ([#540](https://github.com/stlink-org/stlink/pull/540), [#712](https://github.com/stlink-org/stlink/pull/712)) -* Added creation of icons for .desktop file ([#684](https://github.com/stlink-org/stlink/pull/684), [#708](https://github.com/stlink-org/stlink/pull/708)) -* Added desktop file for linux ([#688](https://github.com/stlink-org/stlink/pull/688)) -* Added button to export STM32 flash memory to a file ([#691](https://github.com/stlink-org/stlink/pull/691)) -* Updated libusb to 1.0.22 ([#695](https://github.com/stlink-org/stlink/pull/695)) - (related Bugs: [#438](https://github.com/stlink-org/stlink/pull/438), [#632](https://github.com/stlink-org/stlink/pull/632)) -* Added icons for STLink GUI ([#697](https://github.com/stlink-org/stlink/pull/697)) -* Added support for STM32L4R9 target ([#694](https://github.com/stlink-org/stlink/pull/694), [#699](https://github.com/stlink-org/stlink/pull/699)) -* Added memory map for STM32F411RE target ([#709](https://github.com/stlink-org/stlink/pull/709)) -* Implemented intel hex support for GTK GUI ([#713](https://github.com/stlink-org/stlink/pull/713), [#718](https://github.com/stlink-org/stlink/pull/718)) +- Added reset through `AIRCR` ([#540](https://github.com/stlink-org/stlink/pull/540), [#712](https://github.com/stlink-org/stlink/pull/712)) +- Added creation of icons for `.desktop` file ([#684](https://github.com/stlink-org/stlink/pull/684), [#708](https://github.com/stlink-org/stlink/pull/708)) +- Added desktop file for linux ([#688](https://github.com/stlink-org/stlink/pull/688)) +- Added button to export STM32 flash memory to a file ([#691](https://github.com/stlink-org/stlink/pull/691)) +- Updated `libusb` to 1.0.22 ([#695](https://github.com/stlink-org/stlink/pull/695)) - (related Bugs: [#438](https://github.com/stlink-org/stlink/pull/438), [#632](https://github.com/stlink-org/stlink/pull/632)) +- Added icons for stlink GUI ([#697](https://github.com/stlink-org/stlink/pull/697)) +- Added support for STM32L4R9 target ([#694](https://github.com/stlink-org/stlink/pull/694), [#699](https://github.com/stlink-org/stlink/pull/699)) +- Added memory map for STM32F411RE target ([#709](https://github.com/stlink-org/stlink/pull/709)) +- Implemented intel hex support for `GTK` GUI ([#713](https://github.com/stlink-org/stlink/pull/713), [#718](https://github.com/stlink-org/stlink/pull/718)) Updates and fixes: -* Fixed missing flash_loader for STM32L0x ([#269](https://github.com/stlink-org/stlink/pull/269), [#274](https://github.com/stlink-org/stlink/pull/274), [#654](https://github.com/stlink-org/stlink/pull/654), [#675](https://github.com/stlink-org/stlink/pull/675)) -* Fix for stlink library calls exit() or _exit() ([#634](https://github.com/stlink-org/stlink/pull/634), [#696](https://github.com/stlink-org/stlink/pull/696)) -* Added semihosting parameter documentation in doc/man ([#674](https://github.com/stlink-org/stlink/pull/674)) -* Fixed reference to non-exisiting st-term tool in doc/man ([#676](https://github.com/stlink-org/stlink/pull/676)) -* Fixed serial number size mismatch with stlink_open_usb() ([#680](https://github.com/stlink-org/stlink/pull/680)) -* Debian packaging, CMake and README.md fixes ([#682](https://github.com/stlink-org/stlink/pull/682), [#683](https://github.com/stlink-org/stlink/pull/683)) -* Disabled static library installation by default ([#702](https://github.com/stlink-org/stlink/pull/702)) -* Fix for libusb deprecation ([#703](https://github.com/stlink-org/stlink/pull/703), [#704](https://github.com/stlink-org/stlink/pull/704)) -* Renamed STLINK_CHIPID_STM32_L4R9 to STLINK_CHIPID_STM32_L4RX ([#706](https://github.com/stlink-org/stlink/pull/706)) -* [regression] stlink installation under Linux (Debian 9) is broken since #695 ([#700](https://github.com/stlink-org/stlink/pull/700), [#701](https://github.com/stlink-org/stlink/pull/701), [#707](https://github.com/stlink-org/stlink/pull/707)) -* Fixed flash memory map for STM32F72xxx target ([#711](https://github.com/stlink-org/stlink/pull/711)) -* Proper flash page size calculation for STM32F412xx target ([#721](https://github.com/stlink-org/stlink/pull/721)) -* Return correct value on EOF for Semihosting SYS_READ ([#726](https://github.com/stlink-org/stlink/pull/726), [#727](https://github.com/stlink-org/stlink/pull/727), [#728](https://github.com/stlink-org/stlink/pull/728), [#729](https://github.com/stlink-org/stlink/pull/729), [#730](https://github.com/stlink-org/stlink/pull/730), [#731](https://github.com/stlink-org/stlink/pull/731), [#732](https://github.com/stlink-org/stlink/pull/732)) -* FreeBSD defines LIBUSB_API_VERSION instead of LIBUSBX_API_VERSION ([#733](https://github.com/stlink-org/stlink/pull/733)) - - -v1.5.0 -====== +- Fixed missing flash_loader for STM32L0x ([#269](https://github.com/stlink-org/stlink/pull/269), [#274](https://github.com/stlink-org/stlink/pull/274), [#654](https://github.com/stlink-org/stlink/pull/654), [#675](https://github.com/stlink-org/stlink/pull/675)) +- Fix for stlink library calls `exit()` or `_exit()` ([#634](https://github.com/stlink-org/stlink/pull/634), [#696](https://github.com/stlink-org/stlink/pull/696)) +- Added semihosting parameter documentation in doc/man ([#674](https://github.com/stlink-org/stlink/pull/674)) +- Fixed reference to non-exisiting `st-term` tool in doc/man ([#676](https://github.com/stlink-org/stlink/pull/676)) +- Fixed serial number size mismatch with `stlink_open_usb()` ([#680](https://github.com/stlink-org/stlink/pull/680)) +- Debian packaging, `cmake` and `README.md` fixes ([#682](https://github.com/stlink-org/stlink/pull/682), [#683](https://github.com/stlink-org/stlink/pull/683)) +- Disabled static library installation by default ([#702](https://github.com/stlink-org/stlink/pull/702)) +- Fix for `libusb` deprecation ([#703](https://github.com/stlink-org/stlink/pull/703), [#704](https://github.com/stlink-org/stlink/pull/704)) +- Renamed `STLINK_CHIPID_STM32_L4R9` to `STLINK_CHIPID_STM32_L4RX` ([#706](https://github.com/stlink-org/stlink/pull/706)) +- [regression] stlink installation under Linux (Debian 9) is broken since #695 ([#700](https://github.com/stlink-org/stlink/pull/700), [#701](https://github.com/stlink-org/stlink/pull/701), [#707](https://github.com/stlink-org/stlink/pull/707)) +- Fixed flash memory map for STM32F72xxx target ([#711](https://github.com/stlink-org/stlink/pull/711)) +- Proper flash page size calculation for STM32F412xx target ([#721](https://github.com/stlink-org/stlink/pull/721)) +- Return correct value on `EOF` for semihosting `SYS_READ` ([#726](https://github.com/stlink-org/stlink/pull/726), [#727](https://github.com/stlink-org/stlink/pull/727), [#728](https://github.com/stlink-org/stlink/pull/728), [#729](https://github.com/stlink-org/stlink/pull/729), [#730](https://github.com/stlink-org/stlink/pull/730), [#731](https://github.com/stlink-org/stlink/pull/731), [#732](https://github.com/stlink-org/stlink/pull/732)) +- FreeBSD defines `LIBUSB_API_VERSION` instead of `LIBUSBX_API_VERSION` ([#733](https://github.com/stlink-org/stlink/pull/733)) + +# v1.5.0 Release date: 2018-02-16 Major changes and added features: -* Added support of STM32L496xx/4A6xx devices ([#615](https://github.com/stlink-org/stlink/pull/615), [#657](https://github.com/stlink-org/stlink/pull/657)) -* Added unknown chip dummy to obtain the serial of the ST-link by a call to st-info --probe ([#641](https://github.com/stlink-org/stlink/pull/641)) -* Added support for STM32F72xx (chip-ID: 0x452) devices (commit [#1969148](https://github.com/stlink-org/stlink/commit/19691485359afef1a256964afcbb8dcf4b733209)) +- Added support of STM32L496xx/4A6xx devices ([#615](https://github.com/stlink-org/stlink/pull/615), [#657](https://github.com/stlink-org/stlink/pull/657)) +- Added unknown chip dummy to obtain the serial of the STlink by a call to `st-info --probe` ([#641](https://github.com/stlink-org/stlink/pull/641)) +- Added support for STM32F72xx (chip-ID: 0x452) devices (commit [#1969148](https://github.com/stlink-org/stlink/commit/19691485359afef1a256964afcbb8dcf4b733209)) Updates and fixes: -* Fixed verification of flash error for STM32L496x device ([#617](https://github.com/stlink-org/stlink/pull/617), [#618](https://github.com/stlink-org/stlink/pull/618)) -* Updated Linux source repositories in README.md: Gentoo, Fedora and RedHat/CentOS ([#622](https://github.com/stlink-org/stlink/pull/622), [#635](https://github.com/stlink-org/stlink/pull/635)) -* Updated changelog in debian package ([#630](https://github.com/stlink-org/stlink/pull/630)) -* Added LIB_INSTALL_DIR to correct libs install on 64-bit systems ([#633](https://github.com/stlink-org/stlink/pull/633), [#636](https://github.com/stlink-org/stlink/pull/636)) -* Fixed write for microcontroller with RAM size less or equal to 32K ([#637](https://github.com/stlink-org/stlink/pull/637)) -* Fixed memory map for STM32L496xx boards ([#639](https://github.com/stlink-org/stlink/pull/639)) -* Fixed __FILE__ base name extraction ([#624](https://github.com/stlink-org/stlink/pull/624), [#628](https://github.com/stlink-org/stlink/pull/628), [#648](https://github.com/stlink-org/stlink/pull/648)) -* Added debian/triggers to run ldconfig ([#664](https://github.com/stlink-org/stlink/pull/664)) -* Fixed build on Fedora with GCC 8 ([#666](https://github.com/stlink-org/stlink/pull/666), [#667](https://github.com/stlink-org/stlink/pull/667), [#668](https://github.com/stlink-org/stlink/pull/668)) - +- Fixed verification of flash error for STM32L496x device ([#617](https://github.com/stlink-org/stlink/pull/617), [#618](https://github.com/stlink-org/stlink/pull/618)) +- Updated Linux source repositories in README.md: Gentoo, Fedora and RedHat/CentOS ([#622](https://github.com/stlink-org/stlink/pull/622), [#635](https://github.com/stlink-org/stlink/pull/635)) +- Updated changelog in debian package ([#630](https://github.com/stlink-org/stlink/pull/630)) +- Added `LIB_INSTALL_DIR` to correct libs install on 64-bit systems ([#633](https://github.com/stlink-org/stlink/pull/633), [#636](https://github.com/stlink-org/stlink/pull/636)) +- Fixed write for microcontroller with RAM size less or equal to 32K ([#637](https://github.com/stlink-org/stlink/pull/637)) +- Fixed memory map for STM32L496xx boards ([#639](https://github.com/stlink-org/stlink/pull/639)) +- Fixed `__FILE__` base name extraction ([#624](https://github.com/stlink-org/stlink/pull/624), [#628](https://github.com/stlink-org/stlink/pull/628), [#648](https://github.com/stlink-org/stlink/pull/648)) +- Added debian/triggers to run `ldconfig` ([#664](https://github.com/stlink-org/stlink/pull/664)) +- Fixed build on Fedora with GCC 8 ([#666](https://github.com/stlink-org/stlink/pull/666), [#667](https://github.com/stlink-org/stlink/pull/667), [#668](https://github.com/stlink-org/stlink/pull/668)) -v1.4.0 -====== +# v1.4.0 Release date: 2017-07-01 Major changes and added features: -* Allow building of debian package with CPack ([#554](https://github.com/stlink-org/stlink/pull/554), commit [#5b69f25](https://github.com/stlink-org/stlink/commit/5b69f25198a1a8f34e2ee48d1ad20f79447e3d55)) -* Added support for STM32L011 target ([#564](https://github.com/stlink-org/stlink/pull/564), [#565](https://github.com/stlink-org/stlink/pull/565), [#572](https://github.com/stlink-org/stlink/pull/572)) -* Added support for flashing second bank on STM32F10x_XL ([#592](https://github.com/stlink-org/stlink/pull/592)) -* Initial support to compile with Microsoft Visual Studio 2017 ([#602](https://github.com/stlink-org/stlink/pull/602)) -* Added support for STM32L452 target ([#603](https://github.com/stlink-org/stlink/pull/603), [#608](https://github.com/stlink-org/stlink/pull/608)) +- Allow building of debian package with CPack ([#554](https://github.com/stlink-org/stlink/pull/554), commit [#5b69f25](https://github.com/stlink-org/stlink/commit/5b69f25198a1a8f34e2ee48d1ad20f79447e3d55)) +- Added support for STM32L011 target ([#564](https://github.com/stlink-org/stlink/pull/564), [#565](https://github.com/stlink-org/stlink/pull/565), [#572](https://github.com/stlink-org/stlink/pull/572)) +- Added support for flashing second bank on STM32F10x_XL ([#592](https://github.com/stlink-org/stlink/pull/592)) +- Initial support to compile with Microsoft Visual Studio 2017 ([#602](https://github.com/stlink-org/stlink/pull/602)) +- Added support for STM32L452 target ([#603](https://github.com/stlink-org/stlink/pull/603), [#608](https://github.com/stlink-org/stlink/pull/608)) Updates and fixes: -* Fixed gdb-server: STM32L0xx has no FP_CTRL register for breakpoints ([#273](https://github.com/stlink-org/stlink/pull/273)) -* Added --flash=n[k][m] command line option to override device model ([#305](https://github.com/stlink-org/stlink/pull/305), [#516](https://github.com/stlink-org/stlink/pull/516), [#576](https://github.com/stlink-org/stlink/pull/576)) -* Updated libusb to 1.0.21 for Windows ([#562](https://github.com/stlink-org/stlink/pull/562)) -* Fixed low-voltage flashing on STM32F7 devices ([#566](https://github.com/stlink-org/stlink/pull/566), [#567](https://github.com/stlink-org/stlink/pull/567)) -* Fixed building with mingw64 ([#569](https://github.com/stlink-org/stlink/pull/569), [#573](https://github.com/stlink-org/stlink/pull/573), [#578](https://github.com/stlink-org/stlink/pull/578), [#582](https://github.com/stlink-org/stlink/pull/582), [#584](https://github.com/stlink-org/stlink/pull/584), [#610](https://github.com/stlink-org/stlink/pull/610), [#846](https://github.com/stlink-org/stlink/pull/846)) -* Fixed possible memory leak ([#570](https://github.com/stlink-org/stlink/pull/570), [#571](https://github.com/stlink-org/stlink/pull/571)) -* Fixed installation path for shared objects ([#581](https://github.com/stlink-org/stlink/pull/581)) -* Fixed a few -Wformat warnings ([#582](https://github.com/stlink-org/stlink/pull/582)) -* Removed unused defines in mimgw.h ([#583](https://github.com/stlink-org/stlink/pull/583)) -* Skip GTK detection when cross-compiling ([#588](https://github.com/stlink-org/stlink/pull/588)) -* Fixed compilation with GCC 7 ([#590](https://github.com/stlink-org/stlink/pull/590), [#591](https://github.com/stlink-org/stlink/pull/591)) -* Fixed flashing to 'f0 device' targets ([#594](https://github.com/stlink-org/stlink/pull/594), [#595](https://github.com/stlink-org/stlink/pull/595)) -* Fixed wrong counting when flashing ([#605](https://github.com/stlink-org/stlink/pull/605)) - - -v1.3.1 -====== +- Fixed gdb-server: STM32L0xx has no `FP_CTRL` register for breakpoints ([#273](https://github.com/stlink-org/stlink/pull/273)) +- Added `--flash=n[k][m]` command line option to override device model ([#305](https://github.com/stlink-org/stlink/pull/305), [#516](https://github.com/stlink-org/stlink/pull/516), [#576](https://github.com/stlink-org/stlink/pull/576)) +- Updated `libusb` to 1.0.21 for Windows ([#562](https://github.com/stlink-org/stlink/pull/562)) +- Fixed low-voltage flashing on STM32F7 devices ([#566](https://github.com/stlink-org/stlink/pull/566), [#567](https://github.com/stlink-org/stlink/pull/567)) +- Fixed building with mingw64 ([#569](https://github.com/stlink-org/stlink/pull/569), [#573](https://github.com/stlink-org/stlink/pull/573), [#578](https://github.com/stlink-org/stlink/pull/578), [#582](https://github.com/stlink-org/stlink/pull/582), [#584](https://github.com/stlink-org/stlink/pull/584), [#610](https://github.com/stlink-org/stlink/pull/610), [#846](https://github.com/stlink-org/stlink/pull/846)) +- Fixed possible memory leak ([#570](https://github.com/stlink-org/stlink/pull/570), [#571](https://github.com/stlink-org/stlink/pull/571)) +- Fixed installation path for shared objects ([#581](https://github.com/stlink-org/stlink/pull/581)) +- Fixed a few `-Wformat` warnings ([#582](https://github.com/stlink-org/stlink/pull/582)) +- Removed unused defines in `mingw.h` ([#583](https://github.com/stlink-org/stlink/pull/583)) +- Skip `GTK` detection when cross-compiling ([#588](https://github.com/stlink-org/stlink/pull/588)) +- Fixed compilation with GCC 7 ([#590](https://github.com/stlink-org/stlink/pull/590), [#591](https://github.com/stlink-org/stlink/pull/591)) +- Fixed flashing to `F0 device` targets ([#594](https://github.com/stlink-org/stlink/pull/594), [#595](https://github.com/stlink-org/stlink/pull/595)) +- Fixed wrong counting when flashing ([#605](https://github.com/stlink-org/stlink/pull/605)) + +# v1.3.1 Release date: 2017-02-25 Major changes and added features: -* Added support for Semihosting `SYS_READC` ([#546](https://github.com/stlink-org/stlink/pull/546)) -* Added support for STM32F413 ([#549](https://github.com/stlink-org/stlink/pull/549), [#550](https://github.com/stlink-org/stlink/pull/550), [#758](https://github.com/stlink-org/stlink/pull/758)) -* Added preliminary support for STM32L011 to see it after probe (chip-ID 0x457) ([#558](https://github.com/stlink-org/stlink/pull/558), [#598](https://github.com/stlink-org/stlink/pull/598)) +- Added support for Semihosting `SYS_READC` ([#546](https://github.com/stlink-org/stlink/pull/546)) +- Added support for STM32F413 ([#549](https://github.com/stlink-org/stlink/pull/549), [#550](https://github.com/stlink-org/stlink/pull/550), [#758](https://github.com/stlink-org/stlink/pull/758)) +- Added preliminary support for STM32L011 to see it after probe (chip-ID 0x457) ([#558](https://github.com/stlink-org/stlink/pull/558), [#598](https://github.com/stlink-org/stlink/pull/598)) Updates and fixes: -* cmake/CPackConfig.cmake: Fixup OSX zip filename -* Updated source repositories in README.md: Windows, macOS, Alpine Linux -* Compilation fixes ([#547](https://github.com/stlink-org/stlink/pull/547), [#551](https://github.com/stlink-org/stlink/pull/551), [#552](https://github.com/stlink-org/stlink/pull/552)) -* Stripped full paths to source files in log ([#548](https://github.com/stlink-org/stlink/pull/548)) -* Fixed incorrect release folder name in docs ([#560](https://github.com/stlink-org/stlink/pull/560)) -* Fixed compilation when path includes spaces ([#561](https://github.com/stlink-org/stlink/pull/561)) - +- `cmake/CPackConfig.cmake`: Fixup OSX zip filename +- Updated source repositories in README.md: Windows, macOS, Alpine Linux +- Compilation fixes ([#547](https://github.com/stlink-org/stlink/pull/547), [#551](https://github.com/stlink-org/stlink/pull/551), [#552](https://github.com/stlink-org/stlink/pull/552)) +- Stripped full paths to source files in log ([#548](https://github.com/stlink-org/stlink/pull/548)) +- Fixed incorrect release folder name in docs ([#560](https://github.com/stlink-org/stlink/pull/560)) +- Fixed compilation when path includes spaces ([#561](https://github.com/stlink-org/stlink/pull/561)) -v1.3.0 -====== +# v1.3.0 Release date: 2017-01-28 Major changes and added features: -* Deprecation of autotools (autoconf, automake) and fixed build with MinGW ([#83](https://github.com/stlink-org/stlink/pull/83), [#431](https://github.com/stlink-org/stlink/pull/431), [#434](https://github.com/stlink-org/stlink/pull/434), [#465](https://github.com/stlink-org/stlink/pull/465)) -* Added intel hex file reading for `st-flash` ([#110](https://github.com/stlink-org/stlink/pull/110), [#157](https://github.com/stlink-org/stlink/pull/157), [#457](https://github.com/stlink-org/stlink/pull/547), [#459](https://github.com/stlink-org/stlink/pull/549)) -* Added support for ARM semihosting to `st-util` ([#147](https://github.com/stlink-org/stlink/pull/147), [#227](https://github.com/stlink-org/stlink/pull/227), [#454](https://github.com/stlink-org/stlink/pull/454), [#455](https://github.com/stlink-org/stlink/pull/455)) -* Added manpages (generated with pandoc from Markdown) ([#208](https://github.com/stlink-org/stlink/pull/208), [#464](https://github.com/stlink-org/stlink/pull/464), [#466](https://github.com/stlink-org/stlink/pull/466), [#467](https://github.com/stlink-org/stlink/pull/467)) -* Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/stlink-org/stlink/pull/228), [#507](https://github.com/stlink-org/stlink/pull/507), commit [#3fd0f09](https://github.com/stlink-org/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) -* Support serial numbers argument for `st-util` and `st-flash` to probe and control multiple connected programmers ([#318](https://github.com/stlink-org/stlink/pull/318), [#398](https://github.com/stlink-org/stlink/pull/398), [#541](https://github.com/stlink-org/stlink/pull/541)) -* Merge st-probe tool into st-info ([#398](https://github.com/stlink-org/stlink/pull/398)) -* Added support for native debian packaging ([#444](https://github.com/stlink-org/stlink/pull/444), [#472](https://github.com/stlink-org/stlink/pull/472), [#473](https://github.com/stlink-org/stlink/pull/473), [#482](https://github.com/stlink-org/stlink/pull/482), [#483](https://github.com/stlink-org/stlink/pull/483), [#484](https://github.com/stlink-org/stlink/pull/484), [#485](https://github.com/stlink-org/stlink/pull/485)) -* Rewritten commandline parsing for `st-flash` ([#459](https://github.com/stlink-org/stlink/pull/459)) -* Added `--reset` command to `st-flash` ([#505](https://github.com/stlink-org/stlink/pull/505)) -* st-util should detect when USB commands fail ([#525](https://github.com/stlink-org/stlink/pull/525), [#527](https://github.com/stlink-org/stlink/pull/527), [#528](https://github.com/stlink-org/stlink/pull/528)) +- Deprecation of autotools (`autoconf`, `automake`) and fixed build with MinGW ([#83](https://github.com/stlink-org/stlink/pull/83), [#431](https://github.com/stlink-org/stlink/pull/431), [#434](https://github.com/stlink-org/stlink/pull/434), [#465](https://github.com/stlink-org/stlink/pull/465)) +- Added intel hex file reading for `st-flash` ([#110](https://github.com/stlink-org/stlink/pull/110), [#157](https://github.com/stlink-org/stlink/pull/157), [#457](https://github.com/stlink-org/stlink/pull/547), [#459](https://github.com/stlink-org/stlink/pull/549)) +- Added support for ARM semihosting to `st-util` ([#147](https://github.com/stlink-org/stlink/pull/147), [#227](https://github.com/stlink-org/stlink/pull/227), [#454](https://github.com/stlink-org/stlink/pull/454), [#455](https://github.com/stlink-org/stlink/pull/455)) +- Added manpages (generated with `pandoc` from Markdown) ([#208](https://github.com/stlink-org/stlink/pull/208), [#464](https://github.com/stlink-org/stlink/pull/464), [#466](https://github.com/stlink-org/stlink/pull/466), [#467](https://github.com/stlink-org/stlink/pull/467)) +- Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/stlink-org/stlink/pull/228), [#507](https://github.com/stlink-org/stlink/pull/507), commit [#3fd0f09](https://github.com/stlink-org/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) +- Support serial numbers argument for `st-util` and `st-flash` to probe and control multiple connected programmers ([#318](https://github.com/stlink-org/stlink/pull/318), [#398](https://github.com/stlink-org/stlink/pull/398), [#541](https://github.com/stlink-org/stlink/pull/541)) +- Merge `st-probe` tool into `st-info` ([#398](https://github.com/stlink-org/stlink/pull/398)) +- Added support for native debian packaging ([#444](https://github.com/stlink-org/stlink/pull/444), [#472](https://github.com/stlink-org/stlink/pull/472), [#473](https://github.com/stlink-org/stlink/pull/473), [#482](https://github.com/stlink-org/stlink/pull/482), [#483](https://github.com/stlink-org/stlink/pull/483), [#484](https://github.com/stlink-org/stlink/pull/484), [#485](https://github.com/stlink-org/stlink/pull/485)) +- Rewritten commandline parsing for `st-flash` ([#459](https://github.com/stlink-org/stlink/pull/459)) +- Added `--reset` command to `st-flash` ([#505](https://github.com/stlink-org/stlink/pull/505)) +- st-util should detect when USB commands fail ([#525](https://github.com/stlink-org/stlink/pull/525), [#527](https://github.com/stlink-org/stlink/pull/527), [#528](https://github.com/stlink-org/stlink/pull/528)) Chip support added for: -* STM32F401XE: Added memory map for device ([#460](https://github.com/stlink-org/stlink/pull/460)) -* STM32F410RBTx ([#418](https://github.com/stlink-org/stlink/pull/418)) -* STM32F412 ([#537](https://github.com/stlink-org/stlink/pull/537), [#538](https://github.com/stlink-org/stlink/pull/538)) -* STM32F7xx ([#324](https://github.com/stlink-org/stlink/pull/324), [#326](https://github.com/stlink-org/stlink/pull/326), [#327](https://github.com/stlink-org/stlink/pull/327), [#337](https://github.com/stlink-org/stlink/pull/337)) -* STM32F7x7x ([#433](https://github.com/stlink-org/stlink/pull/433), [#435](https://github.com/stlink-org/stlink/pull/435), [#436](https://github.com/stlink-org/stlink/pull/436), [#509](https://github.com/stlink-org/stlink/pull/509)) -* STM32L0xx Cat2 devices (chip-ID: 0x425) ([#414](https://github.com/stlink-org/stlink/pull/414)) -* STM32L0xx Cat5 devices (chip-ID: 0x447) ([#387](https://github.com/stlink-org/stlink/pull/387), [#406](https://github.com/stlink-org/stlink/pull/406)) -* STM32L4xx ([#321](https://github.com/stlink-org/stlink/pull/321)) -* STM32L432 ([#500](https://github.com/stlink-org/stlink/pull/500), [#501](https://github.com/stlink-org/stlink/pull/501)) +- STM32F401XE: Added memory map for device ([#460](https://github.com/stlink-org/stlink/pull/460)) +- STM32F410RBTx ([#418](https://github.com/stlink-org/stlink/pull/418)) +- STM32F412 ([#537](https://github.com/stlink-org/stlink/pull/537), [#538](https://github.com/stlink-org/stlink/pull/538)) +- STM32F7xx ([#324](https://github.com/stlink-org/stlink/pull/324), [#326](https://github.com/stlink-org/stlink/pull/326), [#327](https://github.com/stlink-org/stlink/pull/327), [#337](https://github.com/stlink-org/stlink/pull/337)) +- STM32F7x7x ([#433](https://github.com/stlink-org/stlink/pull/433), [#435](https://github.com/stlink-org/stlink/pull/435), [#436](https://github.com/stlink-org/stlink/pull/436), [#509](https://github.com/stlink-org/stlink/pull/509)) +- STM32L0xx Cat2 devices (chip-ID: 0x425) ([#414](https://github.com/stlink-org/stlink/pull/414)) +- STM32L0xx Cat5 devices (chip-ID: 0x447) ([#387](https://github.com/stlink-org/stlink/pull/387), [#406](https://github.com/stlink-org/stlink/pull/406)) +- STM32L4xx ([#321](https://github.com/stlink-org/stlink/pull/321)) +- STM32L432 ([#500](https://github.com/stlink-org/stlink/pull/500), [#501](https://github.com/stlink-org/stlink/pull/501)) Updates and fixes: -* Fixed "unaligned addr or size" when trying to write a program in RAM ([#323](https://github.com/stlink-org/stlink/pull/323)) -* Fixed flashing on STM32_F3_SMALL ([#325](https://github.com/stlink-org/stlink/pull/325)) -* Fixed STM32L-problem with flash loader ([#390](https://github.com/stlink-org/stlink/pull/390), [#407](https://github.com/stlink-org/stlink/pull/407), [#408](https://github.com/stlink-org/stlink/pull/408)) -* Don't read the target voltage on startup, because it crashes STM32F100 ([#423](https://github.com/stlink-org/stlink/pull/423), [#424](https://github.com/stlink-org/stlink/pull/424)) -* Added a useful error message instead of "[!] send_recv" ([#425](https://github.com/stlink-org/stlink/pull/425), [#426](https://github.com/stlink-org/stlink/pull/426)) -* Do a JTAG reset prior to reading CPU information when processor is in deep sleep ([#428](https://github.com/stlink-org/stlink/pull/428), [#430](https://github.com/stlink-org/stlink/pull/430), [#451](https://github.com/stlink-org/stlink/pull/451)) -* Fixed STM32F030 erase error ([#442](https://github.com/stlink-org/stlink/pull/442)) -* Fixed memory map for STM32F7xx ([#453](https://github.com/stlink-org/stlink/pull/453), [#456](https://github.com/stlink-org/stlink/pull/456)) -* Redesign of `st-flash` commandline options parsing ([#459](https://github.com/stlink-org/stlink/pull/459)) -* Set SWDCLK and fixed jtag_reset bug ([#462](https://github.com/stlink-org/stlink/pull/462), [#475](https://github.com/stlink-org/stlink/pull/475), [#534](https://github.com/stlink-org/stlink/pull/534)) -* doc/compiling.md: Add note about installation and ldconfig ([#478](https://github.com/stlink-org/stlink/pull/478), commit [#be66bbf](https://github.com/stlink-org/stlink/commit/be66bbf200c718904514b044ba84d64a36456218)) -* Fixed Release target to generate the man-pages with pandoc ([#479](https://github.com/stlink-org/stlink/pull/479)) -* Fixed Cygwin build ([#487](https://github.com/stlink-org/stlink/pull/487), ([#506](https://github.com/stlink-org/stlink/pull/506)) -* Reset flash mass erase (MER) bit after mass erase for safety ([#489](https://github.com/stlink-org/stlink/pull/489)) -* Wrong extract command in FindLibUSB.cmake ([#510](https://github.com/stlink-org/stlink/pull/510), [#511](https://github.com/stlink-org/stlink/pull/511)) -* Fixed compilation error on Ubuntu 16.10 ([#514](https://github.com/stlink-org/stlink/pull/514), [#525](https://github.com/stlink-org/stlink/pull/525)) - - -v1.2.0 -====== +- Fixed `unaligned addr or size` when trying to write a program in RAM ([#323](https://github.com/stlink-org/stlink/pull/323)) +- Fixed flashing on `STM32_F3_SMALL` ([#325](https://github.com/stlink-org/stlink/pull/325)) +- Fixed STM32L-problem with flash loader ([#390](https://github.com/stlink-org/stlink/pull/390), [#407](https://github.com/stlink-org/stlink/pull/407), [#408](https://github.com/stlink-org/stlink/pull/408)) +- Don't read the target voltage on startup, because it crashes STM32F100 ([#423](https://github.com/stlink-org/stlink/pull/423), [#424](https://github.com/stlink-org/stlink/pull/424)) +- Added a useful error message instead of `[!] send_recv` ([#425](https://github.com/stlink-org/stlink/pull/425), [#426](https://github.com/stlink-org/stlink/pull/426)) +- Do a JTAG reset prior to reading CPU information when processor is in deep sleep ([#428](https://github.com/stlink-org/stlink/pull/428), [#430](https://github.com/stlink-org/stlink/pull/430), [#451](https://github.com/stlink-org/stlink/pull/451)) +- Fixed STM32F030 erase error ([#442](https://github.com/stlink-org/stlink/pull/442)) +- Fixed memory map for STM32F7xx ([#453](https://github.com/stlink-org/stlink/pull/453), [#456](https://github.com/stlink-org/stlink/pull/456)) +- Redesign of `st-flash` commandline options parsing ([#459](https://github.com/stlink-org/stlink/pull/459)) +- Set `SWDCLK` and fixed `jtag_reset` bug ([#462](https://github.com/stlink-org/stlink/pull/462), [#475](https://github.com/stlink-org/stlink/pull/475), [#534](https://github.com/stlink-org/stlink/pull/534)) +- doc/compiling.md: Add note about installation and `ldconfig` ([#478](https://github.com/stlink-org/stlink/pull/478), commit [#be66bbf](https://github.com/stlink-org/stlink/commit/be66bbf200c718904514b044ba84d64a36456218)) +- Fixed Release target to generate the man-pages with `pandoc` ([#479](https://github.com/stlink-org/stlink/pull/479)) +- Fixed Cygwin build ([#487](https://github.com/stlink-org/stlink/pull/487), ([#506](https://github.com/stlink-org/stlink/pull/506)) +- Reset flash mass erase (MER) bit after mass erase for safety ([#489](https://github.com/stlink-org/stlink/pull/489)) +- Wrong extract command in `FindLibUSB.cmake` ([#510](https://github.com/stlink-org/stlink/pull/510), [#511](https://github.com/stlink-org/stlink/pull/511)) +- Fixed compilation error on Ubuntu 16.10 ([#514](https://github.com/stlink-org/stlink/pull/514), [#525](https://github.com/stlink-org/stlink/pull/525)) + +# v1.2.0 Release date: 2016-05-16 Features added: -* Added multiple stlink probing (`st-info --probe`, `st-info --hla-serial`) with printing serial in hex and OpenOCD `hla_serial` format (Jerry Jacobs) -* Added stlink usb probe API functions (Jerry Jacobs) -* Added parameter to specify one stlink v2 of many (Georg von Zengen) +- Added multiple stlink probing (`st-info --probe`, `st-info --hla-serial`) with printing serial in hex and OpenOCD `hla_serial` format (Jerry Jacobs) +- Added stlink usb probe API functions (Jerry Jacobs) +- Added parameter to specify one stlink v2 of many (Georg von Zengen) Updates and fixes: -* Refactoring/fixes of flash loader (Maxime Coquelin) -* Synchronized cache for STM32F7 (Tristan Gingold) -* Allow flashing of STM32L4 down to 1.71 V (Greg Meiste) -* Fix on STM32L4 to clear flash mass erase flags on CR (Bruno Dal Bo) -* Proper writing of page 0 of second bank for stm32l476xe (Tobias Badertscher) -* Trace the read data in stlink_read_debug32 and not the address of the variable (Tobias Badertscher) -* Mac OS X El Capitan platform support confirmation (Nikolay) -* Do not send a NUL at end of packets to gdb (Tristan Gingold) -* Correctly compute flash write size for partial pages (Dave Vandervies) -* _stlink_usb_reset use hardreset (mlundinse) -* Make sure MCU is halted before running RAM based flashloaders (mlundinse) -* Could not flash STM32_F3_SMALL (Max Chen) -* STM32F4 8-bit support for 1.8v operation (Andy Isaacson) -* Fixed STM32F2xx memory map (Nicolas Schodet) -* Memory map for STM32F42xxx and STM32F43xxx devices (Craig Lilley) -* Stm32l0x flash loader (Robin Kreis) -* Fixed segfault when programmer is already busy and NULL pointers are in the list ([#256](https://github.com/stlink-org/stlink/pull/256), [#394](https://github.com/stlink-org/stlink/pull/394)) -* Send F4 memory-map and features for STM32F429 ([#188](https://github.com/stlink-org/stlink/pull/188), [#196](https://github.com/stlink-org/stlink/pull/196), [#250](https://github.com/stlink-org/stlink/pull/250), [#251](https://github.com/stlink-org/stlink/pull/251)) (Release v1.1.0) -* Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/stlink-org/stlink/pull/218), [#288](https://github.com/stlink-org/stlink/pull/288)) (Release v1.1.0) -* Corrected flash size register address for STM32F2 devices ([#278](https://github.com/stlink-org/stlink/pull/278)) (Release v1.0.0) +- Refactoring/fixes of flash loader (Maxime Coquelin) +- Synchronized cache for STM32F7 (Tristan Gingold) +- Allow flashing of STM32L4 down to 1.71 V (Greg Meiste) +- Fix on STM32L4 to clear flash mass erase flags on CR (Bruno Dal Bo) +- Proper writing of page 0 of second bank for STM32L476xe (Tobias Badertscher) +- Trace the read data in `stlink_read_debug32` and not the address of the variable (Tobias Badertscher) +- Mac OS X El Capitan platform support confirmation (Nikolay) +- Do not send a `NULL` at end of packets to `gdb` (Tristan Gingold) +- Correctly compute flash write size for partial pages (Dave Vandervies) +- `_stlink_usb_reset` use hardreset (mlundinse) +- Make sure MCU is halted before running RAM based flashloaders (mlundinse) +- Could not flash `STM32_F3_SMALL` (Max Chen) +- STM32F4 8-bit support for 1.8v operation (Andy Isaacson) +- Fixed STM32F2xx memory map (Nicolas Schodet) +- Memory map for STM32F42xxx and STM32F43xxx devices (Craig Lilley) +- Stm32l0x flash loader (Robin Kreis) +- Fixed segfault when programmer is already busy and `NULL` pointers are in the list ([#256](https://github.com/stlink-org/stlink/pull/256), [#394](https://github.com/stlink-org/stlink/pull/394)) +- Send F4 memory-map and features for STM32F429 ([#188](https://github.com/stlink-org/stlink/pull/188), [#196](https://github.com/stlink-org/stlink/pull/196), [#250](https://github.com/stlink-org/stlink/pull/250), [#251](https://github.com/stlink-org/stlink/pull/251)) (Release v1.1.0) +- Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/stlink-org/stlink/pull/218), [#288](https://github.com/stlink-org/stlink/pull/288)) (Release v1.1.0) +- Corrected flash size register address for STM32F2 devices ([#278](https://github.com/stlink-org/stlink/pull/278)) (Release v1.0.0) Chip support added for: -* STM32L053R8 (Jean-Luc Béchennec) -* STM32F7 Support (mlundinse) -* Added STM32L4 to CHIPID #defines and devices[], flash driver and loader (Dave Vandervies) -* Basic support for STM32F446 (Pavel Kirienko) -* STM32F303 High Density -* STM32F469/STM32F479 ([#345](https://github.com/stlink-org/stlink/pull/345), [#555](https://github.com/stlink-org/stlink/pull/555)) (Release v1.2.0) -* STM32L1xx Cat.2 devices (Nicolas Schodet) -* STM32L1xx (chip-ID 0x427) ([#152](https://github.com/stlink-org/stlink/pull/152), [#163](https://github.com/stlink-org/stlink/pull/163), [#165](https://github.com/stlink-org/stlink/pull/165)) (Release v1.0.0) -* Added SIGINT handler for stlink cleanup ([#31](https://github.com/stlink-org/stlink/pull/31), [#135](https://github.com/stlink-org/stlink/pull/135)) (Release v1.0.0) +- STM32L053R8 (Jean-Luc Béchennec) +- STM32F7 Support (mlundinse) +- Added STM32L4 to CHIPID #defines and devices[], flash driver and loader (Dave Vandervies) +- Basic support for STM32F446 (Pavel Kirienko) +- STM32F303 High Density +- STM32F469/STM32F479 ([#345](https://github.com/stlink-org/stlink/pull/345), [#555](https://github.com/stlink-org/stlink/pull/555)) (Release v1.2.0) +- STM32L1xx Cat.2 devices (Nicolas Schodet) +- STM32L1xx (chip-ID 0x427) ([#152](https://github.com/stlink-org/stlink/pull/152), [#163](https://github.com/stlink-org/stlink/pull/163), [#165](https://github.com/stlink-org/stlink/pull/165)) (Release v1.0.0) +- Added `SIGINT` handler for stlink cleanup ([#31](https://github.com/stlink-org/stlink/pull/31), [#135](https://github.com/stlink-org/stlink/pull/135)) (Release v1.0.0) Board support added for: -* Nucleo-F303RE (Kyle Manna) -* Nucleo-F411RE (texane) +- Nucleo-F303RE (Kyle Manna) +- Nucleo-F411RE (texane) Build system: -* Travis: Initial support for Travis continues integration on Linux & Mac OS X (Jerry Jacobs) -* CMake: Document in README.md and add extra strict compiler flags (Jerry Jacobs) -* CMake: First stab at a cmake build (Josh Bialkowski) +- Travis: Initial support for Travis continues integration on Linux & Mac OS X (Jerry Jacobs) +- CMake: Document in README.md and add extra strict compiler flags (Jerry Jacobs) +- CMake: First stab at a `cmake` build (Josh Bialkowski) From 03793d42b6078344a9ef8ad55f1d5d0fc19e486e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 11 Mar 2021 00:52:03 +0100 Subject: [PATCH 1106/1435] [doc] Added note on gdb 'run' command (Closes #267) --- doc/tutorial.md | 70 +++++++++++++++++++++++-------------------------- 1 file changed, 33 insertions(+), 37 deletions(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index 1d20c68ee..f13c4c6f1 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -1,35 +1,37 @@ -stlink Tools Tutorial -===================== +# stlink Tools Tutorial ## Available tools and options -| Option | Tool | Description | Available
      since | -| --- | --- | --- | --- | -| --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k
      for the STM32F103C8T6 to assume 128k of flash being present. This option accepts
      decimal (128k), octal 0200k, or hex 0x80k values. Leaving the multiplier out is
      equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k"
      or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | -| --freq=n[k][m] | st-flash,
      st-util | The frequency of the SWD/JTAG interface can be specified, to override the default
      1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
      the unit `Hz` being left out. Valid frequencies are `5K, 15K, 25K, 50K, 100K,`
      `125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | -| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at
      the end of binary file. This may cause some garbage data left after a flash operation.
      This option was enabled by default in earlier releases. | v1.6.1 | -| --reset | st-flash | Trigger a reset both before and after flashing. | v1.0.0 | -| --version | st-info,
      st-flash,
      st-util | Print version information. | | -| --help | st-flash,
      st-util | Print list of available commands. _(To be added to this table.)_ | | +| Option | Tool | Description | Available
      since | +| --------------- | ------------------------------------ | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------------------- | +| --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k
      for the STM32F103C8T6 to assume 128k of flash being present. This option accepts
      decimal (128k), octal 0200k, or hex 0x80k values. Leaving the multiplier out is
      equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k"
      or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | +| --freq=n[k][m] | st-flash,
      st-util | The frequency of the SWD/JTAG interface can be specified, to override the default
      1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
      the unit `Hz` being left out. Valid frequencies are `5K, 15K, 25K, 50K, 100K,`
      `125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | +| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at
      the end of binary file. This may cause some garbage data left after a flash operation.
      This option was enabled by default in earlier releases. | v1.6.1 | +| --reset | st-flash | Trigger a reset both before and after flashing. | v1.0.0 | +| --version | st-info,
      st-flash,
      st-util | Print version information. | | +| --help | st-flash,
      st-util | Print list of available commands. _(To be added to this table.)_ | | ### st-flash: Checksum for binary files + When flashing a file, a checksum is calculated for the binary file, both in md5 and the sum algorithm. The latter is also used by the official ST-Link utility tool from STMicroelectronics as described in the document: [`UM0892 - User manual - STM32 ST-LINK utility software description`](https://www.st.com/resource/en/user_manual/cd00262073-stm32-stlink-utility-software-description-stmicroelectronics.pdf). ### stlink-gui + The `stlink` toolset also provides a GUI which is an optional feature. It is only installed if a gtk3 toolset has been detected during package installation or compilation from source. It is not available for Windows. If you prefer to have an user interface on the latter system, please use the official `ST-LINK Utility` instead. The stlink-gui offers the following features: -* Connect/disconnect to a present STlink programmer -* Display basic device information -* Select a binary file from the local filesystem to flash it to the detected device connected to the programmer -* Export the memory of the connected chip to a file which can be saved to the local filesystem -* Display of the memory address map in the main window for each, the device memory and a loaded binary file -Within the GUI main window tooltips explain the available user elements. +- Connect/disconnect to a present STlink programmer +- Display basic device information +- Select a binary file from the local filesystem to flash it to the detected device connected to the programmer +- Export the memory of the connected chip to a file which can be saved to the local filesystem +- Display of the memory address map in the main window for each, the device memory and a loaded binary file +Within the GUI main window tooltips explain the available user elements. ## Solutions to common problems + ### a) Verify if udev rules are set correctly (by Dave Hylands) To investigate, start by plugging your STLINK device into the usb port. Then run `lsusb`. You should see an entry something like the following: @@ -77,7 +79,6 @@ to ensure that the rules actually take effect. Using the trigger command means t If the VID:PID of your device doesn't match those in any of the 3 files, then you may need to create a custom rule file to match your VID:PID. - ### b) NOTE: Chinese Fake-Chips CKS32F103C8T6 or CS32F103C8T6 being marked as "STM32F103C8T6" In contrast to "Clone chips" which identify themselves as such by their official marking (manufacturer, model, etc.), so called "Fake chips" do not. @@ -89,8 +90,8 @@ In this known example one finds the counterfeited "STM32F103C8T6" MCUs to identi In the following you find some hints on how to identify your chip and track down fraud: -* [How to Detect STM32 Fakes](https://www.cnx-software.com/2020/03/22/how-to-detect-stm32-fakes/) -* [Confirmation by STMicroelectronics](https://www.mikrocontroller.net/attachment/442839/couterfeit_STM.png) (Marking: 991KA 93 MYS 807) +- [How to Detect STM32 Fakes](https://www.cnx-software.com/2020/03/22/how-to-detect-stm32-fakes/) +- [Confirmation by STMicroelectronics](https://www.mikrocontroller.net/attachment/442839/couterfeit_STM.png) (Marking: 991KA 93 MYS 807) However it appears that not all counterfeited parts cause problems during operation, but some are known to not even being able to execute a basic "blinky" example binary. Further there can be problems that may not even show up or affect you directly, but somewhen later in time (or maybe never). This demonstrates there is no guarantee for a proper working chip with equal functionality compared to the original. @@ -100,11 +101,11 @@ Check your hardware and try to identify what you have in front of you before ass Please let us know, if you come across any further websites or tutorials that help to identify STM32 fake chips so we can list them here to help others. ------- +--- + ( Content below is currently unrevised and may be outdated as of Apr 2020. ) -Using STM32 discovery kits with open source tools -======== +# Using STM32 discovery kits with open source tools This guide details the use of STMicroelectronics STM32 discovery kits in an open source environment. @@ -121,11 +122,11 @@ from any vendor. It has some good, reliable examples for each of the Discovery b Even if you don’t plan on using libopencm3, the examples they provide will help you verify that: -- Your installed toolchain is capable of compiling for cortex M3/M4 - targets -- stlink is functional -- Your arm-none-eabi-gdb is functional -- Your board is functional +- Your installed toolchain is capable of compiling for cortex M3/M4 + targets +- stlink is functional +- Your arm-none-eabi-gdb is functional +- Your board is functional A GDB server must be started to interact with the STM32 by running st-util tool : @@ -173,7 +174,6 @@ Your program should now be running, and, if you used one of the blinking examples from libopencm3, the LEDs on the board should be blinking for you. - ## Building and flashing a program If you want to simply flash binary files to arbitrary sections of @@ -207,7 +207,6 @@ $> [sudo] ./st-flash write fancy_blink.bin 0x08000000 Upon reset, the board LEDs should be blinking. - ## Using the gdb server To run the gdb server: @@ -252,7 +251,6 @@ Transfer rate: 1 KB/sec, 560 bytes/write. (gdb) continue ``` - ## Resetting the chip from GDB You may reset the chip using GDB if you want. You'll need to use `target @@ -268,6 +266,9 @@ Kill the program being debugged? (y or n) y Starting program: /home/whitequark/ST/apps/bally/firmware.elf ``` +Note that st-link does not support 'run', as it does not load arbitrary programs without explicit commands. +In order to continue, one can use 'monitor reset' to reset the MCU. + Remember that you can shorten the commands. `tar ext :4242` is good enough for GDB. @@ -277,7 +278,6 @@ If you need to send a hard reset signal through `NRST` pin, you can use the foll (gdb) monitor jtag_reset ``` - ## Disassembling THUMB code in GDB By default, the disassemble command in GDB operates in ARM mode. The programs running on CORTEX-M3 are compiled in THUMB mode. @@ -287,7 +287,6 @@ To correctly disassemble them under GDB, uses an odd address. For instance, if y (gdb) disassemble 0x20000001 ``` - ## Running programs from SRAM You can run your firmware directly from SRAM if you want to. Just link @@ -300,7 +299,6 @@ it at 0x20000000 and do It will be loaded, and pc will be adjusted to point to start of the code, if it is linked correctly (i.e. ELF has correct entry point). - ## Writing to flash The GDB stub ships with a correct memory map, including the flash area. @@ -312,18 +310,16 @@ If you would link your executable to `0x08000000` and then do then it would be written to the memory. - ## Writing Option Bytes Example to read and write option bytes (currently writing only supported for STM32G0 and STM32L0) + ``` ./st-flash --debug --reset --format binary --flash=128k read option_bytes_dump.bin 0x1FFF7800 4 ./st-flash --debug --reset --format binary --flash=128k write option_bytes_dump.bin 0x1FFF7800 ``` - -FAQ -=== +# FAQ Q: My breakpoints do not work at all or only work once. From 45e9b5ee6e8e2128b837de064ab1a84f6f24c9c3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 11 Mar 2021 14:15:37 +0100 Subject: [PATCH 1107/1435] General Project Update - Updated CHANGELOG.md - Updated list of contributors - Fixed travis CI build settings --- .travis.yml | 15 +++++++-------- CHANGELOG.md | 10 +++++++++- contributors.txt | 1 + 3 files changed, 17 insertions(+), 9 deletions(-) diff --git a/.travis.yml b/.travis.yml index 4437b3148..fefafbaf1 100644 --- a/.travis.yml +++ b/.travis.yml @@ -30,11 +30,11 @@ jobs: - os: linux dist: xenial env: BADGE=linux - compiler: clang-8 + compiler: clang addons: apt: - sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-xenial-3.7"] - packages: ["clang-8", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + sources: ["ubuntu-toolchain-r-test"] + packages: ["libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - os: linux dist: bionic env: BADGE=linux @@ -98,11 +98,11 @@ jobs: - os: linux dist: xenial env: BADGE=linux - compiler: clang-8 + compiler: clang addons: apt: - sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-xenial-3.7"] - packages: ["clang-8", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + sources: ["ubuntu-toolchain-r-test"] + packages: ["libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] before_install: - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - os: linux @@ -111,11 +111,10 @@ jobs: compiler: clang-10 addons: apt: - sources: ["ubuntu-toolchain-r-test", "llvm-toolchain-bionic-6.0"] + sources: ["ubuntu-toolchain-r-test"] packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] before_install: - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - before_install: - os: linux dist: focal env: BADGE=linux diff --git a/CHANGELOG.md b/CHANGELOG.md index c4adaf2ba..912092b65 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -16,14 +16,19 @@ Features: - Link for WIN32 & APPLE with stlink-static ([#1069](https://github.com/stlink-org/stlink/pull/1069)) - Extended support for STM32H7 ([#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) - ITM functionality for STLink/V2 and STM32Fxx chipsets ([#136](https://github.com/stlink-org/stlink/pull/136), [#179](https://github.com/stlink-org/stlink/pull/179), [#815](https://github.com/stlink-org/stlink/pull/815), [#1072](https://github.com/stlink-org/stlink/pull/1072)) +- Included ITM functionality for building with MSVC ([#1080](https://github.com/stlink-org/stlink/pull/1080)) Updates & changes: +- [doc] Added note on `(gdb) run` command (commit [#03793d4](https://github.com/stlink-org/stlink/commit/03793d42b6078344a9ef8ad55f1d5d0fc19e486e), [#276](https://github.com/stlink-org/stlink/pull/276)) - [doc] `st-flash --reset` parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) - [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) - Imported debian pkg-settings ([#986](https://github.com/stlink-org/stlink/pull/986)) - Add support for FreeBSD's `libusb` reimplementation ([#992](https://github.com/stlink-org/stlink/pull/992), [#993](https://github.com/stlink-org/stlink/pull/993)) +- [doc] Added explanation about STM32F103 fake chips (commit [#a66557a](https://github.com/stlink-org/stlink/commit/a66557a102d48e69feb0a9746e8e42c4baf31fe2), [#1024](https://github.com/stlink-org/stlink/pull/1024)) - [doc] Added example for output of `st-info --probe` ([#1007](https://github.com/stlink-org/stlink/pull/1007), [#1049](https://github.com/stlink-org/stlink/pull/1049)) +- [refactoring] Correctly handle endianness without reference to host platform ([#1081](https://github.com/stlink-org/stlink/pull/1081)) +- Check format string for log messages ([#1093](https://github.com/stlink-org/stlink/pull/1093)) Fixes: @@ -33,7 +38,7 @@ Fixes: - Fixed installation path for desktop-file and icons ([#972](https://github.com/stlink-org/stlink/pull/972)) - Fix for static linking of `libssp` ([#973](https://github.com/stlink-org/stlink/pull/973), [#974](https://github.com/stlink-org/stlink/pull/974)) - [regression] Fixed wrong formatting for library install path ([#978](https://github.com/stlink-org/stlink/pull/978), [#1089](https://github.com/stlink-org/stlink/pull/1089)) -- Fixed installation of header files needed for compiling with `libstlink.so.1.6.1` ([#982](https://github.com/stlink-org/stlink/pull/982)) +- Fixed installation of header files needed for compiling with `libstlink.so.1.6.1` (commit [#31b1fa1](https://github.com/stlink-org/stlink/commit/31b1fa16201521e2aaf464576f2f169981abede0), [#982](https://github.com/stlink-org/stlink/pull/982)) - Fixed `connect under reset` for `st-flash` and `st-util` ([#983](https://github.com/stlink-org/stlink/pull/983)) - Fix for `mmap() size_t overflow` in `st-flash` ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) - [regression] `stlink-gui` installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) @@ -41,7 +46,9 @@ Fixes: - [doc] Fixed wrong path for `rules.d` folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) - Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - Fixed `gettimeofday` for MSVC ([#1074](https://github.com/stlink-org/stlink/pull/1074)) +- Bugfixes for compilation with clang ([#1076](https://github.com/stlink-org/stlink/pull/1076), [#1078](https://github.com/stlink-org/stlink/pull/1078)) - Fixed compilation with GCC 11 ([#1077](https://github.com/stlink-org/stlink/pull/1077)) +- [regression] Flash_loader: increased wait rounds for slow boards ([#1085](https://github.com/stlink-org/stlink/pull/1085)) # v1.6.1 @@ -371,6 +378,7 @@ Updates and fixes: - Fixed STM32F2xx memory map (Nicolas Schodet) - Memory map for STM32F42xxx and STM32F43xxx devices (Craig Lilley) - Stm32l0x flash loader (Robin Kreis) +- Use libusb synchronous api ([#194](https://github.com/stlink-org/stlink/pull/194), [#374](https://github.com/stlink-org/stlink/pull/374)) - Fixed segfault when programmer is already busy and `NULL` pointers are in the list ([#256](https://github.com/stlink-org/stlink/pull/256), [#394](https://github.com/stlink-org/stlink/pull/394)) - Send F4 memory-map and features for STM32F429 ([#188](https://github.com/stlink-org/stlink/pull/188), [#196](https://github.com/stlink-org/stlink/pull/196), [#250](https://github.com/stlink-org/stlink/pull/250), [#251](https://github.com/stlink-org/stlink/pull/251)) (Release v1.1.0) - Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/stlink-org/stlink/pull/218), [#288](https://github.com/stlink-org/stlink/pull/288)) (Release v1.1.0) diff --git a/contributors.txt b/contributors.txt index 57801b9ab..38cc9cd42 100644 --- a/contributors.txt +++ b/contributors.txt @@ -74,6 +74,7 @@ Karl Palsson [karlp] Kevlar Harness Kyle Manna Lari Lehtomäki +Luuk van Dijk [lvdlvd] Martin Nowak Matteo Collina Max Chen From c0236dd12c9f07e78b73f774bf028dc102d8f04b Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Thu, 11 Mar 2021 13:22:00 -0500 Subject: [PATCH 1108/1435] Hopefully fix reading an invalid chip ID on STM32WB55 --- src/common.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/src/common.c b/src/common.c index 99049196d..242b690af 100644 --- a/src/common.c +++ b/src/common.c @@ -1222,8 +1222,34 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { int ret; if (sl->core_id == STM32H7_CORE_ID) { - // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - ret = stlink_read_debug32(sl, 0x5c001000, chip_id); + /* STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + * However, the STM32H7 is not the only chip with a JTAG + * IDCODE of 0x6ba02477, so we cannot rely solely on this info + * to select the address to read the chip id */ + + uint32_t chip_id_tmp; + // try reading from 0x5c001000 + ret = stlink_read_debug32(sl, 0x5c001000, &chip_id_tmp); + + // Extract the DEV_ID/CHIPID + uint32_t h7_chip_id = chip_id_tmp & 0xfff; + + if(ret != -1){ + // If we successfully read a H7 chip ID, return that + if((h7_chip_id == STLINK_CHIPID_STM32_H74XXX) || + (h7_chip_id == STLINK_CHIPID_STM32_H7AX) || + (h7_chip_id == STLINK_CHIPID_STM32_H72X)) { + *chip_id = chip_id_tmp; + return(ret); + } + } + + // If we had an error or were unsuccessful at reading an H7 + // series chip ID, try reading the chip ID from the default + // address + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); + + } else { // default chipid address ret = stlink_read_debug32(sl, 0xE0042000, chip_id); From eff18d81d9c64ef9eaf4972d800de09be13ff141 Mon Sep 17 00:00:00 2001 From: 2a17 Date: Thu, 11 Mar 2021 23:04:14 +0000 Subject: [PATCH 1109/1435] option byte support improved --- src/st-flash/flash_opts.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index e74ecc1ce..2ef72c12a 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -337,12 +337,27 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { if (ac == 2) { uint32_t addr; - result = get_integer_from_char_array(av[1], &addr); + result = get_integer_from_char_array(av[0], &addr); if (result != 0) { return bad_arg ("addr"); } else { o->addr = (stm32_addr_t) addr; } + uint32_t val; + result = get_integer_from_char_array(av[1], &val); + if (result != 0) { + return bad_arg ("val"); + } else { + o->val = (uint32_t) val; + } + } else { + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) { + return bad_arg ("val"); + } else { + o->val = (uint32_t) val; + } } } else if (o->area == FLASH_OPTION_BYTES_BOOT_ADD) { // expect option bytes boot address if (ac != 1) { return invalid_args("option bytes boot_add write "); } From 93c59cc5c2bacf5901ad4550bf7a9a4041369dac Mon Sep 17 00:00:00 2001 From: 2a17 Date: Thu, 11 Mar 2021 23:49:51 +0000 Subject: [PATCH 1110/1435] spelling mistake 'feature request' changed to 'bug report' in bug report template --- .github/ISSUE_TEMPLATE/bug-report.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index a1b9d65a0..0e22c2ce9 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -8,7 +8,7 @@ labels: '' Thank you for giving feedback to the stlink project. **NOTICE: Please read and follow instructions in #906 before submitting a ticket. -This feature request will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** +This bug report will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** - [ ] I made serious effort to avoid creating duplicate or nearly similar issue From 7729fea5ed2bc743c64578f9690c40fff58a9821 Mon Sep 17 00:00:00 2001 From: 2a17 Date: Fri, 12 Mar 2021 12:22:58 +0000 Subject: [PATCH 1111/1435] unused parameter removed, comment and return message updated --- src/st-flash/flash_opts.c | 36 +++++++----------------------------- 1 file changed, 7 insertions(+), 29 deletions(-) diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 2ef72c12a..2ee19bd48 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -328,36 +328,14 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { case FLASH_CMD_WRITE: // TODO: should be boot add 0 and boot add 1 uint32 - if (o->area == FLASH_OPTION_BYTES) { // expect filename and optional address - if (ac >=1 && ac <= 2) { - o->filename = av[0]; - } else { - return invalid_args("write [addr]"); - } - - if (ac == 2) { - uint32_t addr; - result = get_integer_from_char_array(av[0], &addr); - if (result != 0) { - return bad_arg ("addr"); - } else { - o->addr = (stm32_addr_t) addr; - } - uint32_t val; - result = get_integer_from_char_array(av[1], &val); - if (result != 0) { - return bad_arg ("val"); - } else { - o->val = (uint32_t) val; - } + if (o->area == FLASH_OPTION_BYTES) { // expect option byte value + if (ac != 1) { return invalid_args("option byte write "); } + uint32_t val; + result = get_integer_from_char_array(av[0], &val); + if (result != 0) { + return bad_arg ("val"); } else { - uint32_t val; - result = get_integer_from_char_array(av[0], &val); - if (result != 0) { - return bad_arg ("val"); - } else { - o->val = (uint32_t) val; - } + o->val = (uint32_t) val; } } else if (o->area == FLASH_OPTION_BYTES_BOOT_ADD) { // expect option bytes boot address if (ac != 1) { return invalid_args("option bytes boot_add write "); } From e5767681f14de9851aa970a9299930ca68b2ed92 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 12 Mar 2021 18:39:08 +0100 Subject: [PATCH 1112/1435] [doc] Corrected tutorial.md Corrected info on --freq argument (Closes #1055) --- doc/tutorial.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index f13c4c6f1..3a0f16fd9 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -5,7 +5,7 @@ | Option | Tool | Description | Available
      since | | --------------- | ------------------------------------ | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------------------- | | --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k
      for the STM32F103C8T6 to assume 128k of flash being present. This option accepts
      decimal (128k), octal 0200k, or hex 0x80k values. Leaving the multiplier out is
      equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k"
      or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | -| --freq=n[k][m] | st-flash,
      st-util | The frequency of the SWD/JTAG interface can be specified, to override the default
      1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
      the unit `Hz` being left out. Valid frequencies are `5K, 15K, 25K, 50K, 100K,`
      `125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | +| --freq=n[k][m] | st-flash | The frequency of the SWD/JTAG interface can be specified, to override the default
      1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
      the unit `Hz` being left out. Valid frequencies are: `5K, 15K, 25K, 50K, 100K,`
      `125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at
      the end of binary file. This may cause some garbage data left after a flash operation.
      This option was enabled by default in earlier releases. | v1.6.1 | | --reset | st-flash | Trigger a reset both before and after flashing. | v1.0.0 | | --version | st-info,
      st-flash,
      st-util | Print version information. | | From dd877b1883b94f4529f3765883f1ce1fe4744fa1 Mon Sep 17 00:00:00 2001 From: anton Date: Sun, 14 Mar 2021 21:09:40 +0500 Subject: [PATCH 1113/1435] Fixing support of stlink v1 --- src/stlink-lib/usb.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 0168834ca..d2b17fad6 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -301,7 +301,7 @@ int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { if (ret == -1) { return(ret); } - ret = send_only(slu, 0, data, len); + ret = send_only(slu, 1, data, len); if (ret == -1) { return(ret); } @@ -431,6 +431,8 @@ int _stlink_usb_status(stlink_t * sl) { } else { sl->core_stat = TARGET_UNKNOWN; } + } else { + sl->core_stat = TARGET_UNKNOWN; } return(0); @@ -469,19 +471,14 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { unsigned char* const cmd = sl->c_buf; ssize_t size; unsigned char* const data = sl->q_buf; - const uint32_t rep_len = sl->version.stlink_v > 1 ? 2 : 0; + const uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 2; int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; // select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). cmd[i++] = sl->version.jtag_api == STLINK_JTAG_API_V1 ? STLINK_DEBUG_APIV1_ENTER : STLINK_DEBUG_APIV2_ENTER; cmd[i++] = STLINK_DEBUG_ENTER_SWD; - - if (rep_len == 0) { - size = send_only(slu, 1, cmd, slu->cmd_len); - } else { - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { printf("[!] send_recv STLINK_DEBUG_ENTER\n"); From c39ed921e39519eb30084b22b8539d19ae5df741 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Sun, 14 Mar 2021 20:53:00 -0400 Subject: [PATCH 1114/1435] Implement changes suggested by Ant-ON to select the chipid register --- src/common.c | 36 ++++++++++++++++-------------------- src/stlink-lib/reg.h | 5 +++++ 2 files changed, 21 insertions(+), 20 deletions(-) diff --git a/src/common.c b/src/common.c index 242b690af..a064254d3 100644 --- a/src/common.c +++ b/src/common.c @@ -1227,28 +1227,24 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * IDCODE of 0x6ba02477, so we cannot rely solely on this info * to select the address to read the chip id */ - uint32_t chip_id_tmp; - // try reading from 0x5c001000 - ret = stlink_read_debug32(sl, 0x5c001000, &chip_id_tmp); - - // Extract the DEV_ID/CHIPID - uint32_t h7_chip_id = chip_id_tmp & 0xfff; - - if(ret != -1){ - // If we successfully read a H7 chip ID, return that - if((h7_chip_id == STLINK_CHIPID_STM32_H74XXX) || - (h7_chip_id == STLINK_CHIPID_STM32_H7AX) || - (h7_chip_id == STLINK_CHIPID_STM32_H72X)) { - *chip_id = chip_id_tmp; - return(ret); - } + uint32_t cpu_id; + *chip_id = 0; + ret = -1; + + // Read the CPU ID as well to determine if this really is an H7 part + if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &cpu_id)) + cpu_id = 0; + + // If it is, read the chipid from the new address + if (sl->core_id == STM32H7_CORE_ID && cpu_id == STLINK_REG_CMx_CPUID_CM7) { + // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + ret = stlink_read_debug32(sl, 0x5c001000, chip_id); } - // If we had an error or were unsuccessful at reading an H7 - // series chip ID, try reading the chip ID from the default - // address - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - + if (*chip_id == 0) { + // default chipid address + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); + } } else { // default chipid address diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 6d2c9f1af..5a796d7e1 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -3,6 +3,11 @@ #define STLINK_REG_CM3_CPUID 0xE000ED00 +#define STLINK_REG_CMx_CPUID_CM0 0x410CC200 +#define STLINK_REG_CMx_CPUID_CM3 0x412FC230 +#define STLINK_REG_CMx_CPUID_CM7 0x411FC272 + + #define STLINK_REG_CM3_FP_CTRL 0xE0002000 // Flash Patch Control Register #define STLINK_REG_CM3_FP_COMPn(n) (0xE0002008 + n*4) #define STLINK_REG_CM3_FP_CTRL_KEY (1 << 1) From 125cb2d7634d5cbc916e9c4bac6ddf80407ab605 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 17 Mar 2021 23:26:48 +0100 Subject: [PATCH 1115/1435] General Project Update - Updated CHANGELOG.md - Updated README.md - Formatting fixes -[doc] Updated tested devices & boards --- CHANGELOG.md | 10 +- README.md | 61 +++++----- doc/devices_boards.md | 253 +++++++++++++++++++++-------------------- doc/version_support.md | 112 +++++++++--------- 4 files changed, 217 insertions(+), 219 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 912092b65..cacd79eef 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -20,7 +20,7 @@ Features: Updates & changes: -- [doc] Added note on `(gdb) run` command (commit [#03793d4](https://github.com/stlink-org/stlink/commit/03793d42b6078344a9ef8ad55f1d5d0fc19e486e), [#276](https://github.com/stlink-org/stlink/pull/276)) +- [doc] Added note on `(gdb) run` command (commit [#03793d4](https://github.com/stlink-org/stlink/commit/03793d42b6078344a9ef8ad55f1d5d0fc19e486e), [#267](https://github.com/stlink-org/stlink/pull/267)) - [doc] `st-flash --reset` parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) - [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) - Imported debian pkg-settings ([#986](https://github.com/stlink-org/stlink/pull/986)) @@ -42,13 +42,17 @@ Fixes: - Fixed `connect under reset` for `st-flash` and `st-util` ([#983](https://github.com/stlink-org/stlink/pull/983)) - Fix for `mmap() size_t overflow` in `st-flash` ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) - [regression] `stlink-gui` installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) -- `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027)) +- `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027), [#1064](https://github.com/stlink-org/stlink/pull/1064), [#1065](https://github.com/stlink-org/stlink/pull/1065)) - [doc] Fixed wrong path for `rules.d` folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) - Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) +- st-util v1.6.1 does not recognize option --freq (commit [#e576768](https://github.com/stlink-org/stlink/commit/e5767681f14de9851aa970a9299930ca68b2ed92), [#1055](https://github.com/stlink-org/stlink/pull/1055)) - Fixed `gettimeofday` for MSVC ([#1074](https://github.com/stlink-org/stlink/pull/1074)) - Bugfixes for compilation with clang ([#1076](https://github.com/stlink-org/stlink/pull/1076), [#1078](https://github.com/stlink-org/stlink/pull/1078)) - Fixed compilation with GCC 11 ([#1077](https://github.com/stlink-org/stlink/pull/1077)) - [regression] Flash_loader: increased wait rounds for slow boards ([#1085](https://github.com/stlink-org/stlink/pull/1085)) +- Fixed support for writing option bytes ([#1102](https://github.com/stlink-org/stlink/pull/1102)) +- [doc] Corrected spelling mistake in bug report template ([#1103](https://github.com/stlink-org/stlink/pull/1103)) +- Fixed support for STLINK/V1 programmer ([#1045](https://github.com/stlink-org/stlink/pull/1045), [#1105](https://github.com/stlink-org/stlink/pull/1105)) # v1.6.1 @@ -380,8 +384,10 @@ Updates and fixes: - Stm32l0x flash loader (Robin Kreis) - Use libusb synchronous api ([#194](https://github.com/stlink-org/stlink/pull/194), [#374](https://github.com/stlink-org/stlink/pull/374)) - Fixed segfault when programmer is already busy and `NULL` pointers are in the list ([#256](https://github.com/stlink-org/stlink/pull/256), [#394](https://github.com/stlink-org/stlink/pull/394)) +- Fixed issue where "unknown chip id!" was seen every other time ([#352](https://github.com/stlink-org/stlink/pull/352), [#367](https://github.com/stlink-org/stlink/pull/367), [#381](https://github.com/stlink-org/stlink/pull/381)) - Send F4 memory-map and features for STM32F429 ([#188](https://github.com/stlink-org/stlink/pull/188), [#196](https://github.com/stlink-org/stlink/pull/196), [#250](https://github.com/stlink-org/stlink/pull/250), [#251](https://github.com/stlink-org/stlink/pull/251)) (Release v1.1.0) - Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/stlink-org/stlink/pull/218), [#288](https://github.com/stlink-org/stlink/pull/288)) (Release v1.1.0) +- Reset: st-flash does not work when CPU is in sleep mode ([#62](https://github.com/stlink-org/stlink/pull/62)) (Release v1.0.0) - Corrected flash size register address for STM32F2 devices ([#278](https://github.com/stlink-org/stlink/pull/278)) (Release v1.0.0) Chip support added for: diff --git a/README.md b/README.md index 3799f46d2..8a8600947 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,4 @@ -Open source version of the STMicroelectronics STlink Tools -========================================================== +# Open source version of the STMicroelectronics STlink Tools [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) [![GitHub release](https://img.shields.io/github/release/stlink-org/stlink.svg)](https://github.com/stlink-org/stlink/releases/latest) @@ -12,42 +11,40 @@ Open source version of the STMicroelectronics STlink Tools Recent new features and bugfixes can be found in the [Changelog](CHANGELOG.md) of this software project. - #### License The stlink library and tools are licensed under the **[BSD-3 License](LICENSE.md)**. - ## Introduction STLink is an open source toolset to program and debug STM32 devices and boards manufactured by STMicroelectronics. It supports several so called STLINK programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG/SWD. There are four generations available on the market which are _all_ supported by this toolset: -* **STLINK/v1** _[obsolete as of 21-11-2019, continued support by this toolset] *)_ +- **STLINK/V1** _[obsolete as of 21-11-2019, continued support by this toolset] \*)_ - transport layer: SCSI passthru commands over USB - stand-alone programmer and present on STM32VL Discovery boards -* **STLINK/v2** +- **STLINK/V2** - transport layer: raw USB commands - stand-alone programmer and present on STM32L Discovery and Nucleo boards -* **STLINK/v2-1** +- **STLINK/V2-1** - transport layer: raw USB commands - present on some STM32 Nucleo boards -* **STLINK/v3** +- **STLINK/V3** - transport layer: raw USB commands - stand-alone programmer -_*)_ **Note: Support on macOS is limited to 10.14 - 10.15. Any later versions are no longer compatible with the STLINK/v1 due to technical reasons.** +_\*)_ **Note: Support for the STLINK/V1 on macOS is limited to 10.14 - 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.** On the user level there is no difference in handling or operation between these different revisions. The STlink toolset includes: -* `st-info` - a programmer and chip information tool -* `st-flash` - a flash manipulation tool -* `st-util` - a GDB server (supported in Visual Studio Code / VSCodium via the [Cortex-Debug](https://github.com/Marus/cortex-debug) plugin) -* `stlink-lib` - a communication library -* `stlink-gui` - a GUI-Interface _[optional]_ - +- `st-info` - a programmer and chip information tool +- `st-flash` - a flash manipulation tool +- `st-trace` - a logging tool to record information on execution +- `st-util` - a GDB server (supported in Visual Studio Code / VSCodium via the [Cortex-Debug](https://github.com/Marus/cortex-debug) plugin) +- `stlink-lib` - a communication library +- `stlink-gui` - a GUI-Interface _[optional]_ ## Supported operating systems and hardware combinations @@ -58,12 +55,10 @@ Supported operating systems are listed in [version_support.md](doc/version_suppo The `stlink` toolset continues to maintain backwards compatibility with the **STLINK/v1** programmer.
      Please note that on macOS this support is limited to versions 10.13 - 10.15. - ## Tutorial & HOWTO Our [tutorial](doc/tutorial.md) may help you along with some advanced tasks and additional info. - ## Installation **Windows**: @@ -77,8 +72,8 @@ Alternatively one may compile and install from source as described in our [compi We recommend to install from: -* [homebrew](https://formulae.brew.sh/formula/stlink) or -* [MacPorts](https://ports.macports.org/port/stlink) +- [homebrew](https://formulae.brew.sh/formula/stlink) or +- [MacPorts](https://ports.macports.org/port/stlink) Alternatively one can compile and install from source as described in our [compiling manual](doc/compiling.md#macOS). @@ -88,30 +83,28 @@ We recommend to install `stlink-tools` from the package repository of the used d **Note:** As packages distributed via the [Debian](https://packages.debian.org/buster/stlink-tools) and [Ubuntu](https://packages.ubuntu.com/stlink-tools) repositories differ from our self-maintained deb-package, we recommend to use the latter instead (see link below). It provides the opportunity to handle and fix user-reported package issues directly within the project and is not redundant to any limitations deriving from external maintenance guidelines. -* Debian Linux: [(Link)](https://github.com/stlink-org/stlink/releases) -* Ubuntu Linux: [(Link)](https://github.com/stlink-org/stlink/releases) -* Arch Linux: [(Link)](https://www.archlinux.org/packages/community/x86_64/stlink) -* Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) -* Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) -* Gentoo Linux: [(Link)](https://packages.gentoo.org/packages/dev-embedded/stlink) +- Debian Linux: [(Link)](https://github.com/stlink-org/stlink/releases) +- Ubuntu Linux: [(Link)](https://github.com/stlink-org/stlink/releases) +- Arch Linux: [(Link)](https://www.archlinux.org/packages/community/x86_64/stlink) +- Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) +- Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) +- Gentoo Linux: [(Link)](https://packages.gentoo.org/packages/dev-embedded/stlink) **Other Operating Systems**: -* RedHat/CentOS 8: Users can install from [EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel8) -* FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) - +- RedHat/CentOS 8: Users can install from [EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel8) +- FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) ## Installation from source (advanced users) When there is no executable available for your platform or you need the latest (possible unstable) version you need to compile the toolset yourself. This procedure is explained in the [compiling manual](doc/compiling.md). - ## Contributing and versioning -* The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) -* Before creating a pull request, please _ALWAYS_ open a new issue for the discussion of the intended new features. Bugfixes don't require a discussion via a ticket-issue. However they should always be described in a few words as soon as they appear to help others as well. -* Contributors and/or maintainers may submit comments or request changes to patch-proposals and/or pull-requests. -* **ATTENTION: _NEVER EVER_ use the '#' character to count-up single points within a listing as '#' is _exclusively_ reserved for referencing GitHub issues and pull-requests. Otherwise you accidentally introduce false cross references within the project.** -* Please start new forks from the develop branch, as pull requests will go into this branch as well. +- The semantic versioning scheme is used. Read more at [semver.org](http://semver.org) +- Before creating a pull request, please _ALWAYS_ open a new issue for the discussion of the intended new features. Bugfixes don't require a discussion via a ticket-issue. However they should always be described in a few words as soon as they appear to help others as well. +- Contributors and/or maintainers may submit comments or request changes to patch-proposals and/or pull-requests. +- **ATTENTION: _NEVER EVER_ use the '#' character to count-up single points within a listing as '#' is _exclusively_ reserved for referencing GitHub issues and pull-requests. Otherwise you accidentally introduce false cross references within the project.** +- Please start new forks from the develop branch, as pull requests will go into this branch as well. Please also refer to our [Contribution Guidelines](CONTRIBUTING.md). diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 97094b972..6396738c4 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -1,15 +1,13 @@ -Boards supported by the STlink toolset -====================================== +# Boards supported by the STlink toolset -The following devices are supported by the STlink tools. - -All Boards are expected to work with ST-Link-v2 programmers. +The following devices are supported by the stlink toolset. +All Boards are expected to work with ST-LINK/V2 programmers. **STM32F0 / ARM Cortex M0 / Core-ID: 0x0bb11477 (STM32F0_CORE_ID)** | Chip-ID | Product-Code | -| --- | --- | +| ------- | ------------------- | | 0x440 | STM32F0**30**x**8** | | 0x442 | STM32F0**30**x**C** | | 0x444 | STM32F0**3**xx**4** | @@ -22,19 +20,19 @@ All Boards are expected to work with ST-Link-v2 programmers. | 0x448 | STM32F0**72**xx | | 0x442 | STM32F0**9**xxx | -Tested boards [incl. STLink programmers]: -* Nucleo-F030R8 [v2-1] -* Nucleo-32 [v2-1] -* STM32F0-Discovery [v2] -* STM320518-EVAL -* Nucleo-F072RB [v2-1] -* Nucleo-F091RC [v2-1] +Tested boards [incl. STLINK programmers]: +- Nucleo-F030R8 [v2-1] +- Nucleo-F072RB [v2-1] +- Nucleo-F091RC [v2-1] +- Nucleo-32 [v2-1] +- STM32F0-Discovery [v2] +- STM320518-EVAL **STM32F1 / ARM Cortex M3 / Core-ID: 0x1ba01477 (STM32F1_CORE_ID)** | Product-Code | Product Line | -| --- | --- | +| ----------------- | ----------------------- | | STM32F10**0**yyxx | Value line (V) | | STM32F10**1**yyxx | Access line (A) | | STM32F10**2**yyxx | USB Access line (USB-A) | @@ -42,86 +40,83 @@ Tested boards [incl. STLink programmers]: | STM32F10**5**yyxx | Connectivity line (C) | | STM32F10**7**yyxx | Connectivity line (C) | -| Chip-ID | Product Line | Code (yy) | V | A | USB-A | P | C | -| --- | --- | --- | --- | --- | --- | --- | --- | -| 0x412 | Low-Density | x4 x6 | F100 | F101 | F102 | F103 | | -| 0x410 | Medium Density | x8 xB | | F101 | F102 | F103 | | -| 0x414 | High density | xC xD xE | | F101 | F103 | | | +| Chip-ID | Product Line | Code (yy) | V | A | USB-A | P | C | +| ------- | -------------------- | --------- | ---- | ---- | ----- | ---- | -------------- | +| 0x412 | Low-Density | x4 x6 | F100 | F101 | F102 | F103 | | +| 0x410 | Medium Density | x8 xB | | F101 | F102 | F103 | | +| 0x414 | High density | xC xD xE | | F101 | F103 | | | | 0x418 | STM32F105xx/107xx | x8 xB xC | | | | | F105
      F107 | -| 0x420 | Medium density value | x8 xB | F100 | | | | | -| 0x428 | High density Value | xC xD xE | F100 | | | | | -| 0x430 | XL-Density | xF xG | | F101 | | F103 | | +| 0x420 | Medium density value | x8 xB | F100 | | | | | +| 0x428 | High density Value | xC xD xE | F100 | | | | | +| 0x430 | XL-Density | xF xG | | F101 | | F103 | | -Tested boards [incl. STLink programmers]: -* STM32VL-Discovery (STM32F100RBT6) with STLink-v1 [v1], [v2] -* STM32F103-Bluepill: C8Tx & R8xx [v2] -* Nucleo-F103RB [v2-1] -* HY-STM32 (STM32F103VETx) [v1, v2] -* DecaWave EVB1000 (STM32F105RCTx) [v1, v2] +Tested boards [incl. STLINK programmers]: +- STM32VL-Discovery (STM32F100RBT6) with STLINK/V1 [v1], [v2] +- STM32F103-Bluepill: C8Tx & R8xx [v2] +- Nucleo-F103RB [v2-1] +- HY-STM32 (STM32F103VETx) [v1, v2] +- DecaWave EVB1000 (STM32F105RCTx) [v1, v2] **STM32F2 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F2_CORE_ID)** -| Chip-ID | Product-Code | Product Line | -| --- | --- | --- | -| 0x411 | STM32F2yyxx | (all devices) | - +| Chip-ID | Product-Code | Product Line | +| ------- | ------------ | ------------- | +| 0x411 | STM32F2yyxx | (all devices) | **STM32F1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM3F1c_CORE_ID)** -| Product-Code | Chip-ID | STLink
      Programmer | Boards | -| --- | --- | --- | --- | -| CKS32F103C8Tx | 0x410 | v2 | "STM32"-Bluepill ( _**Fake-Marking !**_ )
      STM32F103C8T6 clone from China Key Systems (CKS) | -| CKS32F103C8Tx | 0x410 | v2 | CKS32-Bluepill (Clone)
      STM32F103C8T6 clone from China Key Systems (CKS) | - +| Product-Code | Chip-ID | STLink
      Programmer | Boards | +| ------------- | ------- | ---------------------- | ----------------------------------------------------------------------------------------------- | +| CKS32F103C8Tx | 0x410 | v2 | "STM32"-Bluepill ( _**Fake-Marking !**_ )
      STM32F103C8T6 clone from China Key Systems (CKS) | +| CKS32F103C8Tx | 0x410 | v2 | CKS32-Bluepill (Clone)
      STM32F103C8T6 clone from China Key Systems (CKS) | **STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3_CORE_ID)** -| Product-Code | Product Line | -| --- | --- | -| STM32F3**01**yyxx | Access line (A) | -| STM32F3**02**yyxx | USB & CAN line (USB/CAN) | -| STM32F3**03**yyxx | Performance line (P) | -| STM32F3**34**yy | Digital Power line (DP) | -| STM32F3**73**yy | Precision Measurement line (PM) 64k/16k / 128k/24k / 265k/32k | -| STM32F3**18**yy | General Purpose line (GP) 64k/16k | -| STM32F3**28**yy | General Purpose line (GP) 64k/16k | -| STM32F3**58**yy | General Purpose line (GP) 265k/48k | -| STM32F3**78**yy | Precision Measurement line (PM) 265k/32k | -| STM32F3**98**yy | General Purpose line (GP) 512k/80k | - -| Chip-ID | Product Line | Code (yy) | A | USB/CAN | P | others | -| --- | --- | --- | --- | --- | --- | --- | -| 0x422 | _N/A_ | xB xC | | F302 | F303 | | -| 0x422 | _N/A_ | - | | | | F358 | +| Product-Code | Product Line | +| ----------------- | ------------------------------------------------------------- | +| STM32F3**01**yyxx | Access line (A) | +| STM32F3**02**yyxx | USB & CAN line (USB/CAN) | +| STM32F3**03**yyxx | Performance line (P) | +| STM32F3**34**yy | Digital Power line (DP) | +| STM32F3**73**yy | Precision Measurement line (PM) 64k/16k / 128k/24k / 265k/32k | +| STM32F3**18**yy | General Purpose line (GP) 64k/16k | +| STM32F3**28**yy | General Purpose line (GP) 64k/16k | +| STM32F3**58**yy | General Purpose line (GP) 265k/48k | +| STM32F3**78**yy | Precision Measurement line (PM) 265k/32k | +| STM32F3**98**yy | General Purpose line (GP) 512k/80k | + +| Chip-ID | Product Line | Code (yy) | A | USB/CAN | P | others | +| ------- | ------------ | --------- | ---- | ------- | ---- | -------------- | +| 0x422 | _N/A_ | xB xC | | F302 | F303 | | +| 0x422 | _N/A_ | - | | | | F358 | | 0x432 | _N/A_ | - | | | | F373
      F378 | -| 0x438 | _N/A_ | x4 x6 x8 | | | F303 | | +| 0x438 | _N/A_ | x4 x6 x8 | | | F303 | | | 0x438 | _N/A_ | - | | | | F334
      F328 | -| 0x439 | _N/A_ | x4 x6 x8 | F301 | F302 | | | -| 0x439 | _N/A_ | - | | | | F318 | -| 0x446 | _N/A_ | xD xE | | F302 | F303 | | -| 0x446 | _N/A_ | - | | | | F398 | +| 0x439 | _N/A_ | x4 x6 x8 | F301 | F302 | | | +| 0x439 | _N/A_ | - | | | | F318 | +| 0x446 | _N/A_ | xD xE | | F302 | F303 | | +| 0x446 | _N/A_ | - | | | | F398 | -Tested boards [incl. STLink programmers]: -* Nucleo-F302K8 [v2-1] -* Nucleo-F303K8 [v2-1] -* STM32F3348-Discovery [v2-1] -* Nucleo-F334R8 [v2-1] -* STM32F303-Discovery [v2] -* Nucleo-F303RE [v2-1] +Tested boards [incl. STLINK programmers]: +- Nucleo-F302K8 [v2-1] +- Nucleo-F303K8 [v2-1] +- Nucleo-F303RE [v2-1] +- Nucleo-F334R8 [v2-1] +- STM32F303-Discovery [v2] +- STM32F3348-Discovery [v2-1] **STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3c_CORE_ID)** -| Product-Code | Chip-ID | STLink
      Programmer | Boards | -| --- | --- | --- | --- | -| GD32F303VGT6 | 0x430 | _N/A_ | STM32F303 clone from GigaDevice GD)
      _unsupported_ | - +| Product-Code | Chip-ID | STLink
      Programmer | Boards | +| ------------ | ------- | ---------------------- | ------------------------------------------------------ | +| GD32F303VGT6 | 0x430 | _N/A_ | STM32F303 clone from GigaDevice GD)
      _unsupported_ | **STM32F4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F4_CORE_ID)** | Chip-ID | Product-Code | -| --- | --- | +| ------- | ------------------- | | 0x413 | STM32F4**0**xxx | | 0x413 | STM32F4**1**xxx | | 0x419 | STM32F4**2**xxx | @@ -139,20 +134,20 @@ Tested boards [incl. STLink programmers]: | 0x463 | STM32F4**13**xx | | 0x463 | STM32F4**23**xx | -Tested boards [incl. STLink programmers]: -* STM32F407-Discovery [v2] -* 32F411E-Discovery with gyro, audio [v2] -* 32F429I-Discovery with LCD [v2] -* 32F439VIT6-Discovery [v2] (reseated MCU) -* Nucleo-F401RE [v2-1] -* Nucleo-F411RE [v2-1] -* 32F413H-Discovery [v2-1] +Tested boards [incl. STLINK programmers]: +- Nucleo-F401RE [v2-1] +- Nucleo-F411RE [v2-1] +- STM32F407-Discovery [v2] +- STM32F411E-Discovery with gyro, audio [v2] +- STM32F413H-Discovery [v2-1] +- STM32F429I-Discovery with LCD [v2] +- STM32F439VIT6-Discovery [v2] (reseated MCU) **STM32F7 / ARM Cortex M7F / Core-ID: 0x5ba02477 (STM32F7_CORE_ID)** | Chip-ID | Product-Code | -| --- | --- | +| ------- | --------------- | | 0x452 | STM32F7**2**xxx | | 0x452 | STM32F7**3**xxx | | 0x449 | STM32F7**4**xxx | @@ -160,37 +155,45 @@ Tested boards [incl. STLink programmers]: | 0x451 | STM32F7**6**xxx | | 0x451 | STM32F7**7**xxx | -Tested boards [incl. STLink programmers]: -* STM32F756NGHx evaluation board [v2-1] -* 32F769I-Discovery [v2-1] -* Nucleo-F722ZE [v2-1] -* Nucleo-F746ZG [v2-1] +Tested boards [incl. STLINK programmers]: + +- Nucleo-F722ZE [v2-1] +- Nucleo-F746ZG [v2-1] +- STM32F756NGHx evaluation board [v2-1] +- STM32F769I-Discovery [v2-1] + +**STM32H7 / ARM Cortex M7F / Core-ID: 0x6ba02477 (STM32H7_CORE_ID)** + +| Chip-ID | Product-Code | +| ------- | -------------- | +| 0x450 | STM32H74x/H75x | + +Tested boards [incl. STLINK programmers]: +- Nucleo-H745I-Q [v3] **STM32G0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32G0_CORE_ID)** | Chip-ID | Product-Code | -| --- | --- | +| ------- | --------------- | | 0x466 | STM32G0**3**xxx | | 0x466 | STM32G0**4**xxx | | 0x460 | STM32G0**7**xxx | | 0x460 | STM32G0**8**xxx | - **STM32G4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32G4_CORE_ID)** | Chip-ID | Product-Code | -| --- | --- | +| ------- | --------------- | | 0x468 | STM32G4**31**xx | | 0x468 | STM32G4**41**xx | | 0x469 | STM32G4**7**xxx | | 0x469 | STM32G4**8**xxx | - **STM32L0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32L0_CORE_ID)** | Chip-ID | Product-Code | -| --- | --- | +| ------- | --------------- | | 0x457 | STM32L0**1**xxx | | 0x457 | STM32L0**2**xxx | | 0x425 | STM32L0**31**xx | @@ -200,14 +203,14 @@ Tested boards [incl. STLink programmers]: | 0x447 | STM32L0**7**xxx | | 0x447 | STM32L0**8**xxx | -Tested boards [incl. STLink programmers]: -* Nucleo-L053R8 [v2-1] +Tested boards [incl. STLINK programmers]: +- Nucleo-L053R8 [v2-1] **STM32L1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32L1_CORE_ID)** | Chip-ID | Product-Code | -| --- | --- | +| ------- | ---------------- | | 0x416 | STM32L1xxx**6** | | 0x416 | STM32L1xxx**8** | | 0x416 | STM32L1xxx**B** | @@ -218,42 +221,42 @@ Tested boards [incl. STLink programmers]: | 0x436 | STM32L1xxx**D** | | 0x437 | STM32L1xxx**E** | -Tested boards [incl. STLink programmers]: -* Nucleo-L152RE [v2-1] -* 32L152C-Discovery [v2] +Tested boards [incl. STLINK programmers]: +- Nucleo-L152RE [v2-1] +- STM32L152C-Discovery [v2] **STM32L4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32L4_CORE_ID)** -| Chip-ID | Product-Code | -| --- | --- | -| 0x464 | STM32L4**12**xx | -| 0x464 | STM32L4**22**xx | -| 0x435 | STM32L4**3**xxx | -| 0x435 | STM32L4**4**xxx | -| 0x462 | STM32L4**5**xxx | -| 0x462 | STM32L4**6**xxx | -| 0x415 | STM32L4**7**xxx | -| 0x415 | STM32L4**8**xxx | -| 0x461 | STM32L4**96**xx | -| 0x461 | STM32L4**A6**xx | -| 0x470 | STM32L4**R**xx | -| 0x470 | STM32L4**S**xx | -| 0x471 | STM32L4**P5**xx | -| 0x471 | STM32L4**Q5**xx | - -Tested boards [incl. STLink programmers]: -* Nucleo-L432KC [v2-1] -* Nucleo-L452RE [v2-1] -* Nucleo-L476RG [v2-1] -* Nucleo-L496ZG [v2-1] -* 32L4R9I-Discovery [v2-1] - +| Chip-ID | Product-Code | +| ------- | --------------- | +| 0x464 | STM32L4**12**xx | +| 0x464 | STM32L4**22**xx | +| 0x435 | STM32L4**3**xxx | +| 0x435 | STM32L4**4**xxx | +| 0x462 | STM32L4**5**xxx | +| 0x462 | STM32L4**6**xxx | +| 0x415 | STM32L4**7**xxx | +| 0x415 | STM32L4**8**xxx | +| 0x461 | STM32L4**96**xx | +| 0x461 | STM32L4**A6**xx | +| 0x470 | STM32L4**R**xx | +| 0x470 | STM32L4**S**xx | +| 0x471 | STM32L4**P5**xx | +| 0x471 | STM32L4**Q5**xx | + +Tested boards [incl. STLINK programmers]: + +- Nucleo-L432KC [v2-1] +- Nucleo-L452RE [v2-1] +- Nucleo-L476RG [v2-1] +- Nucleo-L496ZG [v2-1] +- STM32L4R9I-Discovery [v2-1] **STM32W / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32W_CORE_ID)** -| Chip-ID | Product-Code | -| --- | --- | -| 0x495 | STM32WB**50**xx | -| 0x495 | STM32WB**55**xx | -| 0x497 | STM32WLE**5**xx | +| Chip-ID | Product-Code | +| ------- | --------------- | +| 0x495 | STM32WB**50**xx | +| 0x495 | STM32WB**55**xx | +| 0x497 | STM32WLE**5**xx | diff --git a/doc/version_support.md b/doc/version_support.md index afa2d2bd7..eca491b79 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,8 +1,7 @@ - _Source:_ pkgs.org - [libusb](https://pkgs.org/search/?q=libusb); [cmake](https://pkgs.org/search/?q=cmake); [gtk](https://pkgs.org/search/?q=gtk) (as of Apr 2020) - ## Supported Operating Systems + ### Microsoft Windows On Windows users should ensure that cmake 3.17.0 is installed.
      @@ -10,72 +9,69 @@ Up on compiling c-make will check **automatically**, whether `libusb` 1.0.20 or If this is not the case, the installation routine will download the latest version (1.0.23 at the time of writing).
      Thus no user interaction regarding libusb is necessary. -* Windows 10 -* Windows 8.1 - +- Windows 10 +- Windows 8.1 ### Apple macOS -| Package Repository | libusb
      version | cmake
      version | gtk-3
      version | Supported macOS versions | -| --- | --- | --- | --- | --- | -| homebrew | 1.0.23 | 3.17.0 | 3.24.18
      gtk+3 | 10.12 (Sierra)- 10.15 (Catalina) | -| MacPorts | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | 10.6 (Snow Leopard) - 10.15 (Catalina) | - -NOTE: In order to use a STLINK/v1 programmer on macOS, versions 10.14 or 10.15 are required. +| Package Repository | libusb
      version | cmake
      version | gtk-3
      version | Supported macOS versions | +| ------------------ | ------------------- | ------------------ | ------------------ | -------------------------------------- | +| homebrew | 1.0.23 | 3.17.0 | 3.24.18
      gtk+3 | 10.12 (Sierra)- 10.15 (Catalina) | +| MacPorts | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | 10.6 (Snow Leopard) - 10.15 (Catalina) | +NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 are required. ### Linux-/Unix-based: -| Operating System | libusb
      version | cmake
      version | gtk-3
      version | Notes | -| --- | --- | --- | --- | --- | -| Alpine Edge | 1.0.23 | 3.17.0 | 3.99.0
      gtk+3.0 | | -| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | 3.24.18
      libgtk+3 | | -| Arch Linux | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | -| Fedora Rawhide | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | named `libusbx`, but
      `libusb`-codebase is used | -| KaOS | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | -| OpenMandriva Cooker | 1.0.23 | 3.17.0 | 3.24.18
      libgtk+3.0
      lib64gtk+3.0 | | -| PCLinuxOS | 1.0.23
      lib64usb1.0 | 3.17.0 | 3.24.18
      lib64gtk+3.0 | | -| Slackware Current | 1.0.23 | 3.17.0 | 3.24.18
      gtk+3 | | -| Solus | 1.0.23 | 3.16.5 | 3.24.16
      libgtk-3 | | -| Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
      libgtk-3 | | -| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | 3.24.13
      libgtk+3.0
      lib64gtk+3.0 | | -| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
      libgtk-3 | | -| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | 3.24.16
      gtk3 | | -| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.13
      gtk+3.0 | | -| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
      libgtk-3 | | -| Mageia Cauldron | 1.0.22 | 3.17.0 | 3.24.18
      libgtk+3.0
      lib64gtk+3.0 | | -| NetBSD 9.0 | 1.0.22 | 3.16.1 | 3.24.12
      gtk+3 | | -| NetBSD 8.1 | 1.0.22 | 3.16.1 | 3.24.12
      gtk+3 | | -| NetBSD 7.2 | 1.0.22 | 3.16.1 | _N/A_ | | -| Alpine 3.10 | 1.0.22 | 3.14.5 | 3.24.8
      gtk+3.0 | | -| Fedora 31 | 1.0.22 | 3.14.5 | 3.24.12
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | -| Mageia 7.1 | 1.0.22 | 3.14.3 | 3.24.8
      libgtk+3.0
      lib64gtk+3.0 | | -| Fedora 30 | 1.0.22 | 3.14.2 | 3.24.8
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | -| Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
      libgtk-3 | | -| Alpine 3.9 | 1.0.22 | 3.13.0 | 3.24.1
      gtk+3.0 | | -| CentOS 8 | 1.0.22 | 3.11.4 | 3.22.30
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | -| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | 3.24.14
      gtk3 | | -| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | 3.22.30
      gtk3 | | -| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
      libgtk-3 | | -| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
      libgtk-3 | | -| Slackware 14.2 | **1.0.20** | 3.5.2 | 3.18.9
      gtk+3 | | -| Ubuntu 16.04 LTS (Xenial Xerus) | **1.0.20** | 3.5.1 | 3.18.9
      libgtk-3 | | -| OpenMandriva Lx 3.0 | **1.0.20** | **3.4.2** | 3.18.9
      libgtk+3.0
      lib64gtk+3.0 | | -| FreeBSD 13 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-13.0r358841
      (integrated) | -| FreeBSD 12 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-11.0r261448_4
      (integrated) | -| FreeBSD 11 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-11.0r261448_4
      (integrated) | - +| Operating System | libusb
      version | cmake
      version | gtk-3
      version | Notes | +| -------------------------------- | ----------------------- | ------------------ | ----------------------------------------- | --------------------------------------------------- | --------------------------------------------------- | +| Alpine Edge | 1.0.23 | 3.17.0 | 3.99.0
      gtk+3.0 | | +| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | 3.24.18
      libgtk+3 | | +| Arch Linux | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | +| Fedora Rawhide | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | named `libusbx`, but
      `libusb`-codebase is used | +| KaOS | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | +| OpenMandriva Cooker | 1.0.23 | 3.17.0 | 3.24.18
      libgtk+3.0
      lib64gtk+3.0 | | +| PCLinuxOS | 1.0.23
      lib64usb1.0 | 3.17.0 | 3.24.18
      lib64gtk+3.0 | | +| Slackware Current | 1.0.23 | 3.17.0 | 3.24.18
      gtk+3 | | +| Solus | 1.0.23 | 3.16.5 | 3.24.16
      libgtk-3 | | +| Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
      libgtk-3 | | +| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | 3.24.13
      libgtk+3.0
      lib64gtk+3.0 | | +| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
      libgtk-3 | | +| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | 3.24.16
      gtk3 | | +| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.13
      gtk+3.0 | | +| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
      libgtk-3 | | +| Mageia Cauldron | 1.0.22 | 3.17.0 | 3.24.18
      libgtk+3.0
      lib64gtk+3.0 | | +| NetBSD 9.0 | 1.0.22 | 3.16.1 | 3.24.12
      gtk+3 | | +| NetBSD 8.1 | 1.0.22 | 3.16.1 | 3.24.12
      gtk+3 | | +| NetBSD 7.2 | 1.0.22 | 3.16.1 | _N/A_ | | +| Alpine 3.10 | 1.0.22 | 3.14.5 | 3.24.8
      gtk+3.0 | | +| Fedora 31 | 1.0.22 | 3.14.5 | 3.24.12
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | +| Mageia 7.1 | 1.0.22 | 3.14.3 | 3.24.8
      libgtk+3.0
      lib64gtk+3.0 | | +| Fedora 30 | 1.0.22 | 3.14.2 | 3.24.8
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | +| Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
      libgtk-3 | | +| Alpine 3.9 | 1.0.22 | 3.13.0 | 3.24.1
      gtk+3.0 | | +| CentOS 8 | 1.0.22 | 3.11.4 | 3.22.30
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | +| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | 3.24.14
      gtk3 | | +| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | 3.22.30
      gtk3 | | +| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
      libgtk-3 | | +| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
      libgtk-3 | | +| Slackware 14.2 | **1.0.20** | 3.5.2 | 3.18.9
      gtk+3 | | +| Ubuntu 16.04 LTS (Xenial Xerus) | **1.0.20** | 3.5.1 | 3.18.9
      libgtk-3 | | +| OpenMandriva Lx 3.0 | **1.0.20** | **3.4.2** | 3.18.9
      libgtk+3.0
      lib64gtk+3.0 | | +| FreeBSD 13 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-13.0r358841
      (integrated) | +| FreeBSD 12 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-11.0r261448_4
      (integrated) | +| FreeBSD 11 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-11.0r261448_4
      (integrated) | ## Unsupported Operating Systems (as of Release v1.6.1) -| Operating System | libusb
      version | cmake
      version | End of
      OS-Support | Notes | -| --- | --- | --- | --- | --- | -| CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but
      `libusb`-codebase is used | -| Debian 8 (Jessie) | 1.0.**19** | 3.**0.2** | Jun 2020 | -| Ubuntu 14.04 LTS (Trusty Tahr) | 1.0.**17** | **2.8.12.2** | Apr 2019 | -| CentOS 6 | 1.0.**9** | **2.8.12.2** | Dec 2020 | named `libusbx`, but
      `libusb`-codebase is used | -| Slackware 14.1 | 1.0.**9** | **2.8.12** | | -| Slackware 14.0 | 1.0.**9** | **2.8.8** | | +| Operating System | libusb
      version | cmake
      version | End of
      OS-Support | Notes | +| ------------------------------ | ------------------- | ------------------ | ---------------------- | --------------------------------------------------- | +| CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but
      `libusb`-codebase is used | +| Debian 8 (Jessie) | 1.0.**19** | 3.**0.2** | Jun 2020 | +| Ubuntu 14.04 LTS (Trusty Tahr) | 1.0.**17** | **2.8.12.2** | Apr 2019 | +| CentOS 6 | 1.0.**9** | **2.8.12.2** | Dec 2020 | named `libusbx`, but
      `libusb`-codebase is used | +| Slackware 14.1 | 1.0.**9** | **2.8.12** | | +| Slackware 14.0 | 1.0.**9** | **2.8.8** | | _All other operating systems which are not listed are unsupported._ From dcdbd61fda443c34d416d44237799a1c6e08d018 Mon Sep 17 00:00:00 2001 From: Michael Nolan Date: Wed, 17 Mar 2021 20:02:41 -0400 Subject: [PATCH 1116/1435] Consolidate core id read code --- src/common.c | 44 ++++++++++++-------------------------------- 1 file changed, 12 insertions(+), 32 deletions(-) diff --git a/src/common.c b/src/common.c index a064254d3..5f2746e3d 100644 --- a/src/common.c +++ b/src/common.c @@ -1221,43 +1221,23 @@ int stlink_core_id(stlink_t *sl) { int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { int ret; - if (sl->core_id == STM32H7_CORE_ID) { - /* STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - * However, the STM32H7 is not the only chip with a JTAG - * IDCODE of 0x6ba02477, so we cannot rely solely on this info - * to select the address to read the chip id */ - - uint32_t cpu_id; - *chip_id = 0; - ret = -1; - - // Read the CPU ID as well to determine if this really is an H7 part - if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &cpu_id)) - cpu_id = 0; - - // If it is, read the chipid from the new address - if (sl->core_id == STM32H7_CORE_ID && cpu_id == STLINK_REG_CMx_CPUID_CM7) { - // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - ret = stlink_read_debug32(sl, 0x5c001000, chip_id); - } - - if (*chip_id == 0) { - // default chipid address - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - } + uint32_t cpu_id; + *chip_id = 0; + ret = -1; - } else { - // default chipid address - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - } + // Read the CPU ID to determine where to read the core id from + if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &cpu_id)) + cpu_id = 0; - if (ret == -1) { - return(ret); + // If the chip is an H7, read the chipid from the new address + if (sl->core_id == STM32H7_CORE_ID && cpu_id == STLINK_REG_CMx_CPUID_CM7) { + // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + ret = stlink_read_debug32(sl, 0x5c001000, chip_id); } if (*chip_id == 0) { - // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - ret = stlink_read_debug32(sl, 0x5c001000, chip_id); + // default chipid address + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); } if (*chip_id == 0) { From 9ed3d46c24c2a78d1e49474ec7529e7cd4c46d3b Mon Sep 17 00:00:00 2001 From: Tarek BOCHKATI Date: Tue, 16 Mar 2021 21:04:31 +0100 Subject: [PATCH 1117/1435] fix for stlink old DFU serial number omit the hla serial aka 'openocd serial' Only one valid serial is used which matches the serial as displayed in STM32CubeProgrammer and official ST tools. Signed-off-by: Tarek BOCHKATI --- doc/man/st-info.1 | 3 --- doc/man/st-info.md | 8 ++---- inc/stlink.h | 6 ++--- src/st-flash/flash.h | 2 +- src/st-flash/flash_opts.c | 12 +-------- src/st-info/info.c | 28 ++------------------- src/st-trace/trace.c | 19 +------------- src/st-util/gdb-server.c | 17 ++----------- src/stlink-lib/usb.c | 52 +++++++++++++++++++++++++++++++++------ src/stlink-lib/usb.h | 2 +- 10 files changed, 57 insertions(+), 92 deletions(-) diff --git a/doc/man/st-info.1 b/doc/man/st-info.1 index a0380f851..776ec7a3f 100644 --- a/doc/man/st-info.1 +++ b/doc/man/st-info.1 @@ -37,9 +37,6 @@ Display the chip ID of the device .B \-\-serial Display the serial code of the device .TP -.B \-\-hla\-serial -Display the hex escaped serial code of the device -.TP .B \-\-probe Display the summarized information of the connected programmers and devices diff --git a/doc/man/st-info.md b/doc/man/st-info.md index 9164642f2..91f9ea0b0 100644 --- a/doc/man/st-info.md +++ b/doc/man/st-info.md @@ -13,7 +13,7 @@ st-info - Provides information about connected STLink and STM32 devices # DESCRIPTION Provides information about connected STLink programmers and STM32 devices: -Serial code, OpenOCD hla-serial, flash, page size, sram, chipid, description. +Serial code, flash, page size, sram, chipid, description. The STLink device to probe can be specified via the environment variable STLINK_DEVICE on the format :. @@ -29,9 +29,6 @@ STLINK_DEVICE on the format :. \--serial : Display the serial code of the device -\--hla-serial -: Display the hex escaped serial code of the device - \--flash : Display amount of flash memory available in the device @@ -53,8 +50,7 @@ Display information about connected programmers and devices $ st-info --probe Found 1 stlink programmers - serial: 303033413030323233343338353130323334333133393339 - hla-serial: "\x30\x30\x33\x41\x30\x30\x32\x32\x33\x34\x33\x38\x35\x31\x30\x32\x33\x34\x33\x31\x33\x39\x33\x39" + serial: 57FF72067265575742132067 flash: 131072 (pagesize: 128) sram: 20480 chipid: 0x0447 diff --git a/inc/stlink.h b/inc/stlink.h index 9b5e56594..7bb1bc51e 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -79,7 +79,8 @@ enum target_state { #define STLINK_SWDCLK_15KHZ_DIVISOR 265 #define STLINK_SWDCLK_5KHZ_DIVISOR 798 -#define STLINK_SERIAL_MAX_SIZE 64 +#define STLINK_SERIAL_LENGTH 24 +#define STLINK_SERIAL_BUFFER_SIZE (STLINK_SERIAL_LENGTH + 1) #define STLINK_V3_MAX_FREQ_NB 10 @@ -191,8 +192,7 @@ struct _stlink { uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram enum target_state core_stat; // set by stlink_status() - char serial[STLINK_SERIAL_MAX_SIZE]; - int serial_size; + char serial[STLINK_SERIAL_BUFFER_SIZE]; int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR enum stlink_flash_type flash_type; diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index ca0ca2839..8a5c2ad29 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -14,7 +14,7 @@ enum flash_format {FLASH_FORMAT_BINARY = 0, FLASH_FORMAT_IHEX = 1}; enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1, FLASH_OTP = 2, FLASH_OPTION_BYTES = 3, FLASH_OPTION_BYTES_BOOT_ADD = 4, FLASH_OPTCR = 5, FLASH_OPTCR1 = 6}; struct flash_opts { enum flash_cmd cmd; - uint8_t serial[STLINK_SERIAL_MAX_SIZE]; + uint8_t serial[STLINK_SERIAL_BUFFER_SIZE]; const char* filename; stm32_addr_t addr; size_t size; diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 2ee19bd48..7d846e425 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -106,18 +106,8 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { serial = av[0] + strlen("--serial="); } - /** @todo This is not really portable, as strlen really returns size_t we need to obey - and not cast it to a signed type. */ - int j = (int)strlen(serial); - int length = j / 2; // the length of the destination-array + memcpy(o->serial, serial, STLINK_SERIAL_BUFFER_SIZE); - if (j % 2 != 0) { return(-1); } - - for (size_t k = 0; j >= 0 && k < sizeof(o->serial); ++k, j -= 2) { - char buffer[3] = {0}; - memcpy(buffer, serial + j, 2); - o->serial[length - k] = (uint8_t)strtol(buffer, NULL, 16); - } } else if (strcmp(av[0], "--area") == 0 || starts_with(av[0], "--area=")) { const char * area; diff --git a/src/st-info/info.c b/src/st-info/info.c index 0fc4d4d8a..c1ac86373 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -9,7 +9,6 @@ static void usage(void) { puts("st-info --version"); puts("st-info --probe"); puts("st-info --serial"); - puts("st-info --hla-serial"); puts("st-info --flash [--connect-under-reset]"); puts("st-info --pagesize [--connect-under-reset]"); puts("st-info --sram [--connect-under-reset]"); @@ -17,24 +16,6 @@ static void usage(void) { puts("st-info --descr [--connect-under-reset]"); } -/* Print normal or OpenOCD hla_serial with newline */ -static void stlink_print_serial(stlink_t *sl, bool openocd) { - const char *fmt; - - if (openocd) { - printf("\""); - fmt = "\\x%02x"; - } else { - fmt = "%02x"; - } - - for (int n = 0; n < sl->serial_size; n++) { printf(fmt, sl->serial[n]); } - - if (openocd) { printf("\""); } - - printf("\n"); -} - static void stlink_print_version(stlink_t *sl) { // Implementation of version printing is minimalistic // but contains all available information from sl->version @@ -53,10 +34,7 @@ static void stlink_print_info(stlink_t *sl) { printf(" version: "); stlink_print_version(sl); - printf(" serial: "); - stlink_print_serial(sl, false); - printf(" hla-serial: "); - stlink_print_serial(sl, true); + printf(" serial: %s\n", sl->serial); printf(" flash: %u (pagesize: %u)\n", (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); printf(" sram: %u\n", (uint32_t)sl->sram_size); @@ -131,9 +109,7 @@ static int print_data(int ac, char **av) { if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } if (strcmp(av[1], "--serial") == 0) { - stlink_print_serial(sl, false); - } else if (strcmp(av[1], "--hla-serial") == 0) { - stlink_print_serial(sl, true); + printf("%s\n", sl->serial); } else if (strcmp(av[1], "--flash") == 0) { printf("0x%x\n", (uint32_t)sl->flash_size); } else if (strcmp(av[1], "--pagesize") == 0) { diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 71ba6b360..3180335a0 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -191,25 +191,8 @@ bool parse_options(int argc, char** argv, st_settings_t *settings) { return true; } -static void convert_serial_number_text_to_binary(const char* text, char binary_out[STLINK_SERIAL_MAX_SIZE]) { - size_t length = 0; - for (uint32_t n = 0; n < strlen(text) && length < STLINK_SERIAL_MAX_SIZE; n += 2) { - char buffer[3] = { 0 }; - memcpy(buffer, text + n, 2); - binary_out[length++] = (uint8_t)strtol(buffer, NULL, 16); - } -} - static stlink_t* stlink_connect(const st_settings_t* settings) { - if (settings->serial_number) { - // Open this specific stlink. - char binary_serial_number[STLINK_SERIAL_MAX_SIZE] = { 0 }; - convert_serial_number_text_to_binary(settings->serial_number, binary_serial_number); - return stlink_open_usb(settings->logging_level, false, binary_serial_number, 0); - } else { - // Otherwise, open any stlink. - return stlink_open_usb(settings->logging_level, false, NULL, 0); - } + return stlink_open_usb(settings->logging_level, false, settings->serial_number, 0); } static bool enable_trace(stlink_t* stlink, const st_settings_t* settings, uint32_t trace_frequency) { diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 4177cef11..0f30c688a 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -43,7 +43,7 @@ static stlink_t *connected_stlink = NULL; static bool semihosting = false; static bool serial_specified = false; -static char serialnumber[STLINK_SERIAL_MAX_SIZE] = {0}; +static char serialnumber[STLINK_SERIAL_BUFFER_SIZE] = {0}; #if defined(_WIN32) #define close_socket win32_close_socket @@ -192,20 +192,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { break; case SERIAL_OPTION: printf("use serial %s\n", optarg); - /* TODO: This is not really portable, as strlen really returns size_t, - * we need to obey and not cast it to a signed type. - */ - int j = (int)strlen(optarg); - int length = j / 2; // the length of the destination-array - - if (j % 2 != 0) { return(-1); } - - for (size_t k = 0; j >= 0 && k < sizeof(serialnumber); ++k, j -= 2) { - char buffer[3] = {0}; - memcpy(buffer, optarg + j, 2); - serialnumber[length - k] = (uint8_t)strtol(buffer, NULL, 16); - } - + memcpy(serialnumber, optarg, STLINK_SERIAL_BUFFER_SIZE); serial_specified = true; break; } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index d2b17fad6..569815665 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1159,7 +1159,44 @@ static stlink_backend_t _stlink_usb_backend = { _stlink_usb_read_trace }; -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq) { +/* return the length of serial or (0) in case of errors */ +size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_descriptor *desc, char *serial) { + unsigned char desc_serial[(STLINK_SERIAL_LENGTH) * 2]; + + /* truncate the string in the serial buffer */ + serial[0] = '\0'; + + /* get the LANGID from String Descriptor Zero */ + int ret = libusb_get_string_descriptor(handle, 0, 0, desc_serial, sizeof(desc_serial)); + if (ret < 4) return 0; + + uint32_t langid = desc_serial[2] | (desc_serial[3] << 8); + + /* get the serial */ + ret = libusb_get_string_descriptor(handle, desc->iSerialNumber, langid, desc_serial, + sizeof(desc_serial)); + if (ret < 0) return 0; // could not read serial + + unsigned char len = desc_serial[0]; + + if (len == ((STLINK_SERIAL_LENGTH + 1) * 2)) { /* len == 50 */ + /* good ST-Link adapter */ + ret = libusb_get_string_descriptor_ascii( + handle, desc->iSerialNumber, (unsigned char *)serial, STLINK_SERIAL_BUFFER_SIZE); + if (ret < 0) return 0; + } else if (len == ((STLINK_SERIAL_LENGTH / 2 + 1) * 2)) { /* len == 26 */ + /* fix-up the buggy serial */ + for (unsigned int i = 0; i < STLINK_SERIAL_LENGTH; i += 2) + sprintf(serial + i, "%02X", desc_serial[i + 2]); + serial[STLINK_SERIAL_LENGTH] = '\0'; + } else { + return 0; + } + + return strlen(serial); +} + +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; int ret = -1; @@ -1236,15 +1273,14 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL if (ret) { continue; } // could not open device - sl->serial_size = libusb_get_string_descriptor_ascii( - handle, desc.iSerialNumber, (unsigned char *)sl->serial, sizeof(sl->serial)); + size_t serial_len = stlink_serial(handle, &desc, sl->serial); libusb_close(handle); - if (sl->serial_size < 0) { continue; } // could not read serial + if (serial_len != STLINK_SERIAL_LENGTH) { continue; } // could not read the serial // if no serial provided, or if serial match device, fixup version and protocol - if (((serial == NULL) || (*serial == 0)) || (memcmp(serial, &sl->serial, sl->serial_size) == 0)) { + if (((serial == NULL) || (*serial == 0)) || (memcmp(serial, &sl->serial, STLINK_SERIAL_LENGTH) == 0)) { if (STLINK_V1_USB_PID(desc.idProduct)) { slu->protocoll = 1; sl->version.stlink_v = 1; @@ -1433,7 +1469,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { continue; } struct libusb_device_handle* handle; - char serial[STLINK_SERIAL_MAX_SIZE] = {0, }; + char serial[STLINK_SERIAL_BUFFER_SIZE] = {0, }; ret = libusb_open(dev, &handle); @@ -1447,11 +1483,11 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { break; } - ret = libusb_get_string_descriptor_ascii(handle, desc.iSerialNumber, (unsigned char *)&serial, sizeof(serial)); + size_t serial_len = stlink_serial(handle, &desc, serial); libusb_close(handle); - if (ret < 0) { continue; } + if (serial_len != STLINK_SERIAL_LENGTH) { continue; } stlink_t *sl = stlink_open_usb(0, 1, serial, 0); diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 717a82f6d..512370a10 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -67,7 +67,7 @@ struct stlink_libusb { * @retval NULL Error while opening the stlink * @retval !NULL Stlink found and ready to use */ -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_MAX_SIZE], int freq); +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq); size_t stlink_probe_usb(stlink_t **stdevs[]); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); From d9726fa86da888f54e463b21f624ee27e208e3a0 Mon Sep 17 00:00:00 2001 From: Ant-ON Date: Wed, 17 Mar 2021 12:38:38 +0500 Subject: [PATCH 1118/1435] Updated a target resetting documentation --- doc/man/st-flash.1 | 2 +- doc/man/st-flash.md | 2 +- doc/tutorial.md | 19 ++++++++++--------- src/st-flash/flash.c | 4 ++-- 4 files changed, 14 insertions(+), 13 deletions(-) diff --git a/doc/man/st-flash.1 b/doc/man/st-flash.1 index c2654f280..086046d2c 100644 --- a/doc/man/st-flash.1 +++ b/doc/man/st-flash.1 @@ -41,7 +41,7 @@ Print version information TODO .TP --reset -TODO +Trigger a reset both before and after flashing .TP --opt Enable ignore ending empty bytes optimization diff --git a/doc/man/st-flash.md b/doc/man/st-flash.md index d5565e923..80130c8f1 100644 --- a/doc/man/st-flash.md +++ b/doc/man/st-flash.md @@ -46,7 +46,7 @@ reset : TODO \--reset -: TODO +: Trigger a reset both before and after flashing \--opt : Enable ignore ending empty bytes optimization diff --git a/doc/tutorial.md b/doc/tutorial.md index 3a0f16fd9..d4cf89ce2 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -2,14 +2,15 @@ ## Available tools and options -| Option | Tool | Description | Available
      since | -| --------------- | ------------------------------------ | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------------------- | -| --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k
      for the STM32F103C8T6 to assume 128k of flash being present. This option accepts
      decimal (128k), octal 0200k, or hex 0x80k values. Leaving the multiplier out is
      equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k"
      or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | -| --freq=n[k][m] | st-flash | The frequency of the SWD/JTAG interface can be specified, to override the default
      1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
      the unit `Hz` being left out. Valid frequencies are: `5K, 15K, 25K, 50K, 100K,`
      `125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | -| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at
      the end of binary file. This may cause some garbage data left after a flash operation.
      This option was enabled by default in earlier releases. | v1.6.1 | -| --reset | st-flash | Trigger a reset both before and after flashing. | v1.0.0 | -| --version | st-info,
      st-flash,
      st-util | Print version information. | | -| --help | st-flash,
      st-util | Print list of available commands. _(To be added to this table.)_ | | +| Option | Tool | Description | Available
      since | +| --------------------- | ------------------------------------ | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------------------- | +| --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k
      for the STM32F103C8T6 to assume 128k of flash being present. This option accepts
      decimal (128k), octal 0200k, or hex 0x80k values. Leaving the multiplier out is
      equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k"
      or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | +| --freq=n[k][m] | st-flash | The frequency of the SWD/JTAG interface can be specified, to override the default
      1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
      the unit `Hz` being left out. Valid frequencies are: `5K, 15K, 25K, 50K, 100K,`
      `125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | +| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at
      the end of binary file. This may cause some garbage data left after a flash operation.
      This option was enabled by default in earlier releases. | v1.6.1 | +| --reset | st-flash | Trigger a reset both before and after flashing. The default use the hardware reset
      through `NRST` pin. The software system reset is used if the hardware reset failed
      (`NRST` pin not connected). | v1.0.0 | +| --connect-under-reset | st-flash | Connect under reset. Option makes it possible to connect to the device before code
      executing. This is useful when the target contains a code that go device to sleep,
      disables of debug pins or other special code. | v1.6.1 | +| --version | st-info
      st-flash
      st-util | Print version information. | | +| --help | st-flash
      st-util | Print list of available commands. _(To be added to this table.)_ | | ### st-flash: Checksum for binary files @@ -272,7 +273,7 @@ In order to continue, one can use 'monitor reset' to reset the MCU. Remember that you can shorten the commands. `tar ext :4242` is good enough for GDB. -If you need to send a hard reset signal through `NRST` pin, you can use the following command: +If you need to send a reset signal, you can use the following command: ``` (gdb) monitor jtag_reset diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index d8bd8772c..447daa158 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -26,8 +26,8 @@ static void cleanup(int signum) { } static void usage(void) { - puts("command line: ./st-flash [--debug] [--reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); - puts("command line: ./st-flash [--debug] [--freq=] [--serial ] erase"); + puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); + puts("command line: ./st-flash [--debug] [--connect-under-reset] [--freq=] [--serial ] erase"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); puts(" , and : Use hex format."); puts(" : Use decimal, octal or hex (prefix 0xXXX) format, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); From ebcf04f02bcb47f0d34d0b0a4992007ee19bfe5c Mon Sep 17 00:00:00 2001 From: anton Date: Wed, 17 Mar 2021 20:32:20 +0500 Subject: [PATCH 1119/1435] flash_loader: used timeout in ms --- src/stlink-lib/flash_loader.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index b55953406..1224215e5 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -3,6 +3,7 @@ #include #include +#include #include "flash_loader.h" #define FLASH_REGS_BANK2_OFS 0x40 @@ -313,7 +314,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { struct stlink_reg rr; - int i = 0; + unsigned timeout; size_t count = 0; uint32_t flash_base = 0; const char *error = NULL; @@ -368,16 +369,19 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe * the OS uses, the wait until the error message is reduced to the same order of magnitude * as what was intended. -- REW. */ -#define WAIT_ROUNDS 40 // wait until done (reaches breakpoint) - for (i = 0; i < WAIT_ROUNDS; i++) { + timeout = time_ms() + 500; + while (time_ms() < timeout) { usleep(10000); - if (stlink_is_core_halted(sl)) { break; } + if (stlink_is_core_halted(sl)) { + timeout = 0; + break; + } } - if (i >= WAIT_ROUNDS) { + if (timeout) { error = "Flash loader run error"; goto error; } From 41bbbc2e9650f873fa562977ac89242fd4ac19fe Mon Sep 17 00:00:00 2001 From: anton Date: Thu, 18 Mar 2021 19:28:40 +0500 Subject: [PATCH 1120/1435] flash_loader: fix check BUSY flag, code simplified --- flashloaders/Makefile | 75 ++++++++---- flashloaders/cleanroom.md | 38 +++---- flashloaders/stm32f0.s | 78 +++++++------ flashloaders/stm32f4.s | 32 ++++-- flashloaders/stm32f4lv.s | 38 ++++--- flashloaders/stm32f7.s | 32 ++++-- flashloaders/stm32f7lv.s | 38 ++++--- flashloaders/stm32l0x.s | 22 ---- flashloaders/stm32l4.s | 32 ++++-- flashloaders/stm32lx.s | 26 +++-- src/stlink-lib/flash_loader.c | 207 ++++++++++++++-------------------- src/stlink-lib/reg.h | 6 + 12 files changed, 320 insertions(+), 304 deletions(-) delete mode 100644 flashloaders/stm32l0x.s diff --git a/flashloaders/Makefile b/flashloaders/Makefile index 7b17cb2a0..3517e1499 100644 --- a/flashloaders/Makefile +++ b/flashloaders/Makefile @@ -4,35 +4,60 @@ # This makefile will save your time from dealing with compile errors # Adjust CC if needed -CC = /opt/local/gcc-arm-none-eabi-8-2018-q4-major/bin/arm-none-eabi-gcc - -CFLAGS_thumb1 = -mcpu=Cortex-M0 -Tlinker.ld -ffreestanding -nostdlib -CFLAGS_thumb2 = -mcpu=Cortex-M3 -Tlinker.ld -ffreestanding -nostdlib - -all: stm32vl.o stm32f0.o stm32l.o stm32f4.o stm32f4_lv.o stm32l4.o stm32f7.o stm32f7_lv.o - -stm32vl.o: stm32f0.s - $(CC) stm32f0.s $(CFLAGS_thumb2) -o stm32vl.o -stm32f0.o: stm32f0.s - $(CC) stm32f0.s $(CFLAGS_thumb1) -o stm32f0.o -stm32l.o: stm32lx.s - $(CC) stm32lx.s $(CFLAGS_thumb2) -o stm32l.o -stm32f4.o: stm32f4.s - $(CC) stm32f4.s $(CFLAGS_thumb2) -o stm32f4.o -stm32f4_lv.o: stm32f4lv.s - $(CC) stm32f4lv.s $(CFLAGS_thumb2) -o stm32f4_lv.o -stm32l4.o: stm32l4.s - $(CC) stm32l4.s $(CFLAGS_thumb2) -o stm32l4.o -stm32f7.o: stm32f7.s - $(CC) stm32f7.s $(CFLAGS_thumb2) -o stm32f7.o -stm32f7_lv.o: stm32f7lv.s - $(CC) stm32f7lv.s $(CFLAGS_thumb2) -o stm32f7_lv.o +CROSS_COMPILE ?= /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi- -clean: - rm *.o +CC = $(CROSS_COMPILE)gcc +OBJCOPY = $(CROSS_COMPILE)objcopy + +XXD = xxd +XXDFLAGS = -i -c 4 + +CFLAGS_THUMB1 = -mcpu=Cortex-M0 -Tlinker.ld -ffreestanding -nostdlib +CFLAGS_THUMB2 = -mcpu=Cortex-M3 -Tlinker.ld -ffreestanding -nostdlib + +all: stm32vl.h stm32f0.h stm32lx.h stm32f4.h stm32f4lv.h stm32l4.h stm32f7.h stm32f7lv.h +stm32f0.h: stm32f0.s + $(CC) stm32f0.s $(CFLAGS_THUMB1) -o stm32f0.o + $(OBJCOPY) -O binary stm32f0.o stm32f0.bin + $(XXD) $(XXDFLAGS) stm32f0.bin stm32f0.h +stm32vl.h: stm32f0.s + $(CC) stm32f0.s $(CFLAGS_THUMB2) -o stm32vl.o + $(OBJCOPY) -O binary stm32vl.o stm32vl.bin + $(XXD) $(XXDFLAGS) stm32vl.bin stm32vl.h +stm32lx.h: stm32lx.s + $(CC) stm32lx.s $(CFLAGS_THUMB2) -o stm32lx.o + $(OBJCOPY) -O binary stm32lx.o stm32lx.bin + $(XXD) $(XXDFLAGS) stm32lx.bin stm32lx.h +stm32f4.h: stm32f4.s + $(CC) stm32f4.s $(CFLAGS_THUMB2) -o stm32f4.o + $(OBJCOPY) -O binary stm32f4.o stm32f4.bin + $(XXD) $(XXDFLAGS) stm32f4.bin stm32f4.h +stm32f4lv.h: stm32f4lv.s + $(CC) stm32f4lv.s $(CFLAGS_THUMB2) -o stm32f4lv.o + $(OBJCOPY) -O binary stm32f4lv.o stm32f4lv.bin + $(XXD) $(XXDFLAGS) stm32f4lv.bin stm32f4lv.h +stm32l4.h: stm32l4.s + $(CC) stm32l4.s $(CFLAGS_THUMB2) -o stm32l4.o + $(OBJCOPY) -O binary stm32l4.o stm32l4.bin + $(XXD) $(XXDFLAGS) stm32l4.bin stm32l4.h + +stm32f7.h: stm32f7.s + $(CC) stm32f7.s $(CFLAGS_THUMB2) -o stm32f7.o + $(OBJCOPY) -O binary stm32f7.o stm32f7.bin + $(XXD) $(XXDFLAGS) stm32f7.bin stm32f7.h + +stm32f7lv.h: stm32f7lv.s + $(CC) stm32f7lv.s $(CFLAGS_THUMB2) -o stm32f7lv.o + $(OBJCOPY) -O binary stm32f7lv.o stm32f7lv.bin + $(XXD) $(XXDFLAGS) stm32f7lv.bin stm32f7lv.h + +clean: + rm *.o + rm *.bin + rm *.h diff --git a/flashloaders/cleanroom.md b/flashloaders/cleanroom.md index a468efe49..b2cb9f00d 100644 --- a/flashloaders/cleanroom.md +++ b/flashloaders/cleanroom.md @@ -1,6 +1,4 @@ -Original Chinese version can be found below. - -# Clean Room Documentation English Version +# Flash Loader Documentation Code is situated in section `.text` @@ -12,11 +10,12 @@ All parameters would be passed over registers `r0`: the base address of the copy source `r1`: the base address of the copy destination -`r2`: the total word (4 bytes) count to be copied (with expeptions) +`r2`: the count of byte to be copied +`r3`: flash register offset (used to support two banks) **What the program is expected to do**: -Copy data from source to destination, after which trigger a breakpint to exit. Before exit, `r2` must be cleared to zero to indicate that the copy is done. +Copy data from source to destination, after which trigger a breakpint to exit. Before exit, `r2` must be less or equal to zero to indicate that the copy is done. **Limitation**: No stack operations are permitted. Registers ranging from `r3` to `r12` are free to use. Note that `r13` is `sp`(stack pointer), `r14` is `lr`(commonly used to store jump address), `r15` is `pc`(program counter). @@ -24,8 +23,6 @@ Copy data from source to destination, after which trigger a breakpint to exit. B ## stm32f0.s -**Exception**: `r2` stores the total half word (2 bytes) count to be copied - `flash_base`: 0x40022000 `FLASH_CR`: offset from `flash_base` is 16 @@ -37,11 +34,11 @@ Copy data from source to destination, after which trigger a breakpint to exit. B **Special requirements**: -Before every copy, read a word from FLASH_CR, set the lowest bit to 1 and write back. Copy one half word each time. +Before every copy, read a word from FLASH_CR, set the PG bit to 1 and write back. Copy one half word each time. -How to wait for the write process: read a word from FLASH_SR, loop until the content is not 1. After that, check FLASH_SR, proceed if the content is 4, otherwise exit. +How to wait for the write process: read a word from FLASH_SR, loop until the busy bit is reset. After that, FLASH_SR is check. The process is interrupted if the error bit (0x04) is set. -Exit: after the copying process and before triggering the breakpoint, clear the lowest bit in FLASH_CR. +Exit: after the copying process and before triggering the breakpoint, clear the PG bit in FLASH_CR. ## stm32f4.s @@ -56,7 +53,8 @@ Exit: after the copying process and before triggering the breakpoint, clear the **Special requirements**: Copy one word each time. -How to wait for the write process: read a half word from FLASH_SR, loop until the content is not 1. + +How to wait for the write process: read a word from FLASH_SR, loop until the busy bit is reset. ## stm32f4lv.s @@ -71,7 +69,7 @@ How to wait for the write process: read a half word from FLASH_SR, loop until th Copy one byte each time. -How to wait from the write process: read a half word from FLASH_SR, loop until the content is not 1. +How to wait from the write process: read a half word from FLASH_SR, loop until the busy bit is reset. ## stm32f7.s @@ -89,7 +87,7 @@ Mostly same with `stm32f4.s`. Require establishing a memory barrier after every Mostly same with `stm32f7.s`. Copy one byte each time. -## stm32l0x.s +## stm32lx.s **Special Requirements**: @@ -97,8 +95,6 @@ Copy one word each time. No wait for write. ## stm32l4.s -**Exception**: r2 stores the double word count to be copied. - `flash_base`: 0x40022000 `FLASH_BSY`: offset from `flash_base` is 0x12 @@ -109,14 +105,10 @@ Copy one word each time. No wait for write. Copy one double word each time (More than one registers are allowed). -How to wait for the write process: read a half word from `FLASH_BSY`, loop until the lowest bit turns non-1. - -## stm32lx.s +How to wait for the write process: read a half word from `FLASH_BSY`, loop until the busy bit is reset. -Same with stm32l0x.s. - -# 净室工程文档-原始中文版 +# 净室工程文档-原始中文版 (out of date) 代码位于的section：`.text` 编译制导添加`.syntax unified` @@ -139,8 +131,6 @@ Same with stm32l0x.s. ## stm32f0.s -例外：`r2`:拷贝half word（2字节）数 - 特殊地址定义：`flash_base`:定义为0x40022000 `FLASH_CR`: 相对`flash_base`的offset为16 @@ -230,4 +220,4 @@ Same with stm32l0x.s. ## stm32lx.s -要求与stm32l0x.s相同 \ No newline at end of file +要求与stm32l0x.s相同 diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s index f30e4bfc6..e2a4b0f00 100644 --- a/flashloaders/stm32f0.s +++ b/flashloaders/stm32f0.s @@ -1,6 +1,14 @@ .syntax unified .text + /* + * Arguments: + * r0 - source memory ptr + * r1 - target memory ptr + * r2 - count of bytes + * r3 - flash register offset + */ + .global copy copy: /* @@ -17,54 +25,56 @@ copy: */ nop nop - ldr r7, =flash_base - ldr r4, [r7] - ldr r7, =flash_off_cr - ldr r6, [r7] - adds r6, r6, r4 - ldr r7, =flash_off_sr - ldr r5, [r7] - adds r5, r5, r4 -loop: - # FLASH_CR ^= 1 + # load flash control register address + # add r3 to flash_base for support dual bank (see flash_loader.c) + ldr r7, flash_base + add r7, r7, r3 + ldr r6, flash_off_cr + add r6, r6, r7 + ldr r5, flash_off_sr + add r5, r5, r7 + + # FLASH_CR |= 0x01 (set PG) ldr r7, =0x1 - ldr r3, [r6] - orrs r3, r3, r7 - str r3, [r6] + ldr r4, [r6] + orrs r4, r4, r7 + str r4, [r6] +loop: # copy 2 bytes - ldrh r3, [r0] - strh r3, [r1] + ldrh r4, [r0] + strh r4, [r1] - ldr r7, =2 - adds r0, r0, r7 - adds r1, r1, r7 + # increment address + adds r0, r0, #0x2 + adds r1, r1, #0x2 - # wait if FLASH_SR == 1 + # BUSY flag + ldr r7, =0x01 wait: - ldr r7, =0x1 - ldr r3, [r5] - tst r3, r7 - beq wait + # get FLASH_SR + ldr r4, [r5] - # exit if FLASH_SR != 4 - ldr r7, =0x4 - tst r3, r7 + # wait until BUSY flag is reset + tst r4, r7 + bne wait + + # test PGERR or WRPRTERR flag is reset + ldr r7, =0x14 + tst r4, r7 bne exit - # loop if r2 != 0 - ldr r7, =0x1 - subs r2, r2, r7 - cmp r2, #0 - bne loop + # loop if count > 0 + subs r2, r2, #0x2 + bgt loop exit: # FLASH_CR &= ~1 ldr r7, =0x1 - ldr r3, [r6] - bics r3, r3, r7 - str r3, [r6] + ldr r4, [r6] + bics r4, r4, r7 + str r4, [r6] bkpt diff --git a/flashloaders/stm32f4.s b/flashloaders/stm32f4.s index a88ad9e02..a66c70dac 100644 --- a/flashloaders/stm32f4.s +++ b/flashloaders/stm32f4.s @@ -1,6 +1,14 @@ .syntax unified .text + /* + * Arguments: + * r0 - source memory ptr + * r1 - target memory ptr + * r2 - count of bytes + * r3 - flash register offset + */ + .global copy copy: ldr r12, flash_base @@ -9,22 +17,24 @@ copy: loop: # copy 4 bytes - ldr r3, [r0] - str r3, [r1] + ldr r4, [r0] + str r4, [r1] + # increment address add r0, r0, #4 add r1, r1, #4 - # wait if FLASH_SR == 1 wait: - ldrh r3, [r10] - tst r3, #0x1 - beq wait - - # loop if r2 != 0 - sub r2, r2, #1 - cmp r2, #0 - bne loop + # get FLASH_SR + ldrh r4, [r10] + + # wait until BUSY flag is reset + tst r4, #0x1 + bne wait + + # loop if count > 0 + subs r2, r2, #4 + bgt loop exit: bkpt diff --git a/flashloaders/stm32f4lv.s b/flashloaders/stm32f4lv.s index 41467a9ef..b8fcfa048 100644 --- a/flashloaders/stm32f4lv.s +++ b/flashloaders/stm32f4lv.s @@ -1,36 +1,40 @@ .syntax unified .text + /* + * Arguments: + * r0 - source memory ptr + * r1 - target memory ptr + * r2 - count of bytes + * r3 - flash register offset + */ + .global copy copy: ldr r12, flash_base ldr r10, flash_off_sr add r10, r10, r12 - # tip 1: original r2 indicates the count of 4 bytes need to copy, - # but we can only copy one byte each time. - # as we have no flash larger than 1GB, we do a little trick here. - # tip 2: r2 is always a power of 2 - mov r2, r2, lsl#2 - loop: # copy 1 byte - ldrb r3, [r0] - strb r3, [r1] + ldrb r4, [r0] + strb r4, [r1] + # increment address add r0, r0, #1 add r1, r1, #1 - # wait if FLASH_SR == 1 wait: - ldrh r3, [r10] - tst r3, #0x1 - beq wait - - # loop if r2 != 0 - sub r2, r2, #1 - cmp r2, #0 - bne loop + # get FLASH_SR + ldrh r4, [r10] + + # wait until BUSY flag is reset + tst r4, #0x1 + bne wait + + # loop if count > 0 + subs r2, r2, #1 + bgt loop exit: bkpt diff --git a/flashloaders/stm32f7.s b/flashloaders/stm32f7.s index 3779a5ea6..4b43cebdc 100644 --- a/flashloaders/stm32f7.s +++ b/flashloaders/stm32f7.s @@ -1,6 +1,14 @@ .syntax unified .text + /* + * Arguments: + * r0 - source memory ptr + * r1 - target memory ptr + * r2 - count of bytes + * r3 - flash register offset + */ + .global copy copy: ldr r12, flash_base @@ -9,25 +17,27 @@ copy: loop: # copy 4 bytes - ldr r3, [r0] - str r3, [r1] + ldr r4, [r0] + str r4, [r1] + # increment address add r0, r0, #4 add r1, r1, #4 # memory barrier dsb sy - # wait if FLASH_SR == 1 wait: - ldrh r3, [r10] - tst r3, #0x1 - beq wait - - # loop if r2 != 0 - sub r2, r2, #1 - cmp r2, #0 - bne loop + # get FLASH_SR + ldrh r4, [r10] + + # wait until BUSY flag is reset + tst r4, #0x1 + bne wait + + # loop if count > 0 + subs r2, r2, #4 + bgt loop exit: bkpt diff --git a/flashloaders/stm32f7lv.s b/flashloaders/stm32f7lv.s index e7b66cc2c..78ff35dbc 100644 --- a/flashloaders/stm32f7lv.s +++ b/flashloaders/stm32f7lv.s @@ -1,39 +1,43 @@ .syntax unified .text + /* + * Arguments: + * r0 - source memory ptr + * r1 - target memory ptr + * r2 - count of bytes + * r3 - flash register offset + */ + .global copy copy: ldr r12, flash_base ldr r10, flash_off_sr add r10, r10, r12 - # tip 1: original r2 indicates the count in 4 bytes need to copy, - # but we can only copy one byte each time. - # as we have no flash larger than 1GB, we do a little trick here. - # tip 2: r2 is always a power of 2 - mov r2, r2, lsl#2 - loop: # copy 1 byte - ldrb r3, [r0] - strb r3, [r1] + ldrb r4, [r0] + strb r4, [r1] + # increment address add r0, r0, #1 add r1, r1, #1 # memory barrier dsb sy - # wait if FLASH_SR == 1 wait: - ldrh r3, [r10] - tst r3, #0x1 - beq wait - - # loop if r2 != 0 - sub r2, r2, #1 - cmp r2, #0 - bne loop + # get FLASH_SR + ldrh r4, [r10] + + # wait until BUSY flag is reset + tst r4, #0x1 + bne wait + + # loop if count > 0 + subs r2, r2, #1 + bgt loop exit: bkpt diff --git a/flashloaders/stm32l0x.s b/flashloaders/stm32l0x.s deleted file mode 100644 index f9c257e2e..000000000 --- a/flashloaders/stm32l0x.s +++ /dev/null @@ -1,22 +0,0 @@ - .syntax unified - .text - - .global copy -copy: -loop: - # copy 4 bytes - ldr r3, [r0] - str r3, [r1] - - ldr r7, =4 - add r0, r0, r7 - add r1, r1, r7 - - # loop if r2 != 0 - ldr r7, =1 - subs r2, r2, r7 - cmp r2, #0 - bne loop - -exit: - bkpt diff --git a/flashloaders/stm32l4.s b/flashloaders/stm32l4.s index 32c27a057..21e926f49 100644 --- a/flashloaders/stm32l4.s +++ b/flashloaders/stm32l4.s @@ -1,6 +1,14 @@ .syntax unified .text + /* + * Arguments: + * r0 - source memory ptr + * r1 - target memory ptr + * r2 - count of bytes + * r3 - flash register offset + */ + .global copy copy: ldr r12, flash_base @@ -9,24 +17,26 @@ copy: loop: # copy 8 bytes - ldr r3, [r0] + ldr r5, [r0] ldr r4, [r0, #4] - str r3, [r1] + str r5, [r1] str r4, [r1, #4] + # increment address add r0, r0, #8 add r1, r1, #8 - # wait if FLASH_BSY[0b] == 1 wait: - ldrh r3, [r10] - tst r3, #0x1 - beq wait - - # loop if r2 != 0 - sub r2, r2, #1 - cmp r2, #0 - bne loop + # get FLASH_SR + ldr r4, [r10] + + # wait until BUSY flag is reset + tst r4, #0x10000 + bne wait + + # loop if count > 0 + subs r2, r2, #8 + bgt loop exit: bkpt diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s index f9c257e2e..69acdea7b 100644 --- a/flashloaders/stm32lx.s +++ b/flashloaders/stm32lx.s @@ -1,22 +1,28 @@ .syntax unified .text + /* + * Arguments: + * r0 - source memory ptr + * r1 - target memory ptr + * r2 - count of bytes + * r3 - flash register offset + */ + .global copy copy: loop: # copy 4 bytes - ldr r3, [r0] - str r3, [r1] + ldr r4, [r0] + str r4, [r1] - ldr r7, =4 - add r0, r0, r7 - add r1, r1, r7 + # increment address + add r0, r0, #4 + add r1, r1, #4 - # loop if r2 != 0 - ldr r7, =1 - subs r2, r2, r7 - cmp r2, #0 - bne loop + # loop if count > 0 + subs r2, r2, #4 + bgt loop exit: bkpt diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 1224215e5..5bc314b07 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -13,89 +13,72 @@ /* flashloaders/stm32f0.s -- compiled with thumb2 */ static const uint8_t loader_code_stm32vl[] = { - 0x16, 0x4f, 0x3c, 0x68, - 0x16, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x16, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, + 0x00, 0xbf, 0x00, 0xbf, + 0x0f, 0x4f, 0x1f, 0x44, + 0x0f, 0x4e, 0x3e, 0x44, + 0x0f, 0x4d, 0x3d, 0x44, 0x4f, 0xf0, 0x01, 0x07, - 0x33, 0x68, 0x3b, 0x43, - 0x33, 0x60, 0x03, 0x88, - 0x0b, 0x80, 0x4f, 0xf0, - 0x02, 0x07, 0xc0, 0x19, - 0xc9, 0x19, 0x4f, 0xf0, - 0x01, 0x07, 0x2b, 0x68, - 0x3b, 0x42, 0xfa, 0xd0, - 0x4f, 0xf0, 0x04, 0x07, - 0x3b, 0x42, 0x04, 0xd1, + 0x34, 0x68, 0x3c, 0x43, + 0x34, 0x60, 0x04, 0x88, + 0x0c, 0x80, 0x02, 0x30, + 0x02, 0x31, 0x4f, 0xf0, + 0x01, 0x07, 0x2c, 0x68, + 0x3c, 0x42, 0xfc, 0xd1, + 0x4f, 0xf0, 0x14, 0x07, + 0x3c, 0x42, 0x01, 0xd1, + 0x02, 0x3a, 0xf0, 0xdc, 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xe6, 0xd1, 0x4f, 0xf0, - 0x01, 0x07, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0x00, 0xbf, + 0x34, 0x68, 0xbc, 0x43, + 0x34, 0x60, 0x00, 0xbe, 0x00, 0x20, 0x02, 0x40, 0x10, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x00, 0x00, - 0x50, 0x00, 0x00, 0x20, - 0x54, 0x00, 0x00, 0x20, - 0x58, 0x00, 0x00, 0x20 + 0x0c, 0x00, 0x00, 0x00 }; /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ static const uint8_t loader_code_stm32f0[] = { 0xc0, 0x46, 0xc0, 0x46, - 0x13, 0x4f, 0x3c, 0x68, - 0x13, 0x4f, 0x3e, 0x68, - 0x36, 0x19, 0x13, 0x4f, - 0x3d, 0x68, 0x2d, 0x19, - 0x12, 0x4f, 0x33, 0x68, - 0x3b, 0x43, 0x33, 0x60, - 0x03, 0x88, 0x0b, 0x80, - 0x10, 0x4f, 0xc0, 0x19, - 0xc9, 0x19, 0x0e, 0x4f, - 0x2b, 0x68, 0x3b, 0x42, - 0xfb, 0xd0, 0x0e, 0x4f, - 0x3b, 0x42, 0x03, 0xd1, - 0x0a, 0x4f, 0xd2, 0x1b, - 0x00, 0x2a, 0xeb, 0xd1, - 0x08, 0x4f, 0x33, 0x68, - 0xbb, 0x43, 0x33, 0x60, - 0x00, 0xbe, 0xc0, 0x46, + 0x0d, 0x4f, 0x1f, 0x44, + 0x0d, 0x4e, 0x3e, 0x44, + 0x0d, 0x4d, 0x3d, 0x44, + 0x0d, 0x4f, 0x34, 0x68, + 0x3c, 0x43, 0x34, 0x60, + 0x04, 0x88, 0x0c, 0x80, + 0x02, 0x30, 0x02, 0x31, + 0x09, 0x4f, 0x2c, 0x68, + 0x3c, 0x42, 0xfc, 0xd1, + 0x08, 0x4f, 0x3c, 0x42, + 0x01, 0xd1, 0x02, 0x3a, + 0xf2, 0xdc, 0x05, 0x4f, + 0x34, 0x68, 0xbc, 0x43, + 0x34, 0x60, 0x00, 0xbe, 0x00, 0x20, 0x02, 0x40, 0x10, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, - 0x48, 0x00, 0x00, 0x20, - 0x4c, 0x00, 0x00, 0x20, - 0x50, 0x00, 0x00, 0x20, 0x01, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, - 0x04, 0x00, 0x00, 0x00 + 0x14, 0x00, 0x00, 0x00 }; -static const uint8_t loader_code_stm32l[] = { +static const uint8_t loader_code_stm32lx[] = { // flashloaders/stm32lx.s - - 0x03, 0x68, 0x0b, 0x60, - 0x4f, 0xf0, 0x04, 0x07, - 0x38, 0x44, 0x39, 0x44, - 0x4f, 0xf0, 0x01, 0x07, - 0xd2, 0x1b, 0x00, 0x2a, - 0xf4, 0xd1, 0x00, 0xbe, + 0x04, 0x68, 0x0c, 0x60, + 0x00, 0xf1, 0x04, 0x00, + 0x01, 0xf1, 0x04, 0x01, + 0x04, 0x3a, 0xf7, 0xdc, + 0x00, 0xbe }; static const uint8_t loader_code_stm32f4[] = { // flashloaders/stm32f4.s - - 0xdf, 0xf8, 0x28, 0xc0, - 0xdf, 0xf8, 0x28, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, + 0xdf, 0xf8, 0x24, 0xc0, + 0xdf, 0xf8, 0x24, 0xa0, + 0xe2, 0x44, 0x04, 0x68, + 0x0c, 0x60, 0x00, 0xf1, 0x04, 0x00, 0x01, 0xf1, 0x04, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0x40, 0x14, 0xf0, + 0x01, 0x0f, 0xfa, 0xd1, + 0x04, 0x3a, 0xf2, 0xdc, 0x00, 0xbe, 0x00, 0xbf, 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 @@ -103,17 +86,15 @@ static const uint8_t loader_code_stm32f4[] = { static const uint8_t loader_code_stm32f4_lv[] = { // flashloaders/stm32f4lv.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, + 0xdf, 0xf8, 0x24, 0xc0, + 0xdf, 0xf8, 0x24, 0xa0, + 0xe2, 0x44, 0x04, 0x78, + 0x0c, 0x70, 0x00, 0xf1, 0x01, 0x00, 0x01, 0xf1, 0x01, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xf0, 0xd1, + 0x00, 0x40, 0x14, 0xf0, + 0x01, 0x0f, 0xfa, 0xd1, + 0x01, 0x3a, 0xf2, 0xdc, 0x00, 0xbe, 0x00, 0xbf, 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 @@ -121,17 +102,16 @@ static const uint8_t loader_code_stm32f4_lv[] = { static const uint8_t loader_code_stm32l4[] = { // flashloaders/stm32l4.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x44, 0x68, 0x0b, 0x60, + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x05, 0x68, + 0x44, 0x68, 0x0d, 0x60, 0x4c, 0x60, 0x00, 0xf1, 0x08, 0x00, 0x01, 0xf1, - 0x08, 0x01, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, + 0x08, 0x01, 0xda, 0xf8, + 0x00, 0x40, 0x14, 0xf4, + 0x80, 0x3f, 0xfa, 0xd1, + 0x08, 0x3a, 0xf0, 0xdc, 0x00, 0xbe, 0x00, 0xbf, 0x00, 0x20, 0x02, 0x40, 0x12, 0x00, 0x00, 0x00 @@ -139,17 +119,16 @@ static const uint8_t loader_code_stm32l4[] = { static const uint8_t loader_code_stm32f7[] = { // flashloaders/stm32f7.s - 0xdf, 0xf8, 0x2c, 0xc0, - 0xdf, 0xf8, 0x2c, 0xa0, - 0xe2, 0x44, 0x03, 0x68, - 0x0b, 0x60, 0x00, 0xf1, + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x04, 0x68, + 0x0c, 0x60, 0x00, 0xf1, 0x04, 0x00, 0x01, 0xf1, 0x04, 0x01, 0xbf, 0xf3, 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0x40, 0x14, 0xf0, + 0x01, 0x0f, 0xfa, 0xd1, + 0x04, 0x3a, 0xf0, 0xdc, 0x00, 0xbe, 0x00, 0xbf, 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 @@ -157,18 +136,16 @@ static const uint8_t loader_code_stm32f7[] = { static const uint8_t loader_code_stm32f7_lv[] = { // flashloaders/stm32f7lv.s - 0xdf, 0xf8, 0x30, 0xc0, - 0xdf, 0xf8, 0x30, 0xa0, - 0xe2, 0x44, 0x4f, 0xea, - 0x82, 0x02, 0x03, 0x78, - 0x0b, 0x70, 0x00, 0xf1, + 0xdf, 0xf8, 0x28, 0xc0, + 0xdf, 0xf8, 0x28, 0xa0, + 0xe2, 0x44, 0x04, 0x78, + 0x0c, 0x70, 0x00, 0xf1, 0x01, 0x00, 0x01, 0xf1, 0x01, 0x01, 0xbf, 0xf3, 0x4f, 0x8f, 0xba, 0xf8, - 0x00, 0x30, 0x13, 0xf0, - 0x01, 0x0f, 0xfa, 0xd0, - 0xa2, 0xf1, 0x01, 0x02, - 0x00, 0x2a, 0xee, 0xd1, + 0x00, 0x40, 0x14, 0xf0, + 0x01, 0x0f, 0xfa, 0xd1, + 0x01, 0x3a, 0xf0, 0xdc, 0x00, 0xbe, 0x00, 0xbf, 0x00, 0x3c, 0x02, 0x40, 0x0e, 0x00, 0x00, 0x00 @@ -234,8 +211,8 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { // STM32l - loader_code = loader_code_stm32l; - loader_size = sizeof(loader_code_stm32l); + loader_code = loader_code_stm32lx; + loader_size = sizeof(loader_code_stm32lx); } else if (sl->core_id == STM32VL_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F1_MEDIUM || sl->chip_id == STLINK_CHIPID_STM32_F1_HIGH || @@ -315,10 +292,9 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { struct stlink_reg rr; unsigned timeout; - size_t count = 0; uint32_t flash_base = 0; const char *error = NULL; - uint32_t dhcsr, dfsr; + uint32_t dhcsr, dfsr, cfsr, hfsr; DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); @@ -329,22 +305,6 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe return(-1); } - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - count = size / sizeof(uint16_t); - - if (size % sizeof(uint16_t)) { ++count; } - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4 || - sl->flash_type == STLINK_FLASH_TYPE_L0) { - count = size / sizeof(uint32_t); - - if (size % sizeof(uint32_t)) { ++count; } - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - count = size / sizeof(uint64_t); - - if (size % sizeof(uint64_t)) { ++count; } - } - if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { flash_base = FLASH_REGS_BANK2_OFS; } @@ -352,7 +312,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe /* Setup core */ stlink_write_reg(sl, fl->buf_addr, 0); // source stlink_write_reg(sl, target, 1); // target - stlink_write_reg(sl, (uint32_t)count, 2); // count + stlink_write_reg(sl, (uint32_t)size, 2); // count stlink_write_reg(sl, flash_base, 3); // flash register base // only used on VL/F1_XL, but harmless for others stlink_write_reg(sl, fl->loader_addr, 15); // pc register @@ -376,9 +336,9 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe usleep(10000); if (stlink_is_core_halted(sl)) { - timeout = 0; - break; - } + timeout = 0; + break; + } } if (timeout) { @@ -397,11 +357,14 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe return(0); error: - dhcsr = dfsr = 0; + dhcsr = dfsr = cfsr = hfsr = 0; stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + stlink_read_debug32(sl, STLINK_REG_CFSR, &cfsr); + stlink_read_debug32(sl, STLINK_REG_HFSR, &hfsr); stlink_read_all_regs(sl, &rr); - ELOG("%s (R2 0x%08X R15 0x%08X DHCSR 0x%08X DFSR 0x%08X)\n", error, rr.r[2], rr.r[15], dhcsr, dfsr); + ELOG("%s (R2 0x%X R15 0x%X DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X)\n", error, rr.r[2], rr.r[15], dhcsr, dfsr, cfsr, hfsr); + ELOG("(R0 0x%X R1 0x%X)\n", rr.r[0], rr.r[1]); return(-1); } diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 6d2c9f1af..473231117 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -19,6 +19,12 @@ #define STLINK_REG_CM3_DWT_FUNn(n) (0xE0001028 + n*16) /* Cortex™-M3 Technical Reference Manual */ +/* Configurable Fault Status Register */ +#define STLINK_REG_CFSR 0xE000ED28 + +/* Hard Fault Status Register */ +#define STLINK_REG_HFSR 0xE000ED2C + /* Debug Halting Control and Status Register */ #define STLINK_REG_DFSR 0xE000ED30 #define STLINK_REG_DFSR_HALT (1 << 0) From 76f153035a90fc72dc075a75c3d0523c0e0f0ddb Mon Sep 17 00:00:00 2001 From: anton Date: Thu, 18 Mar 2021 23:03:10 +0500 Subject: [PATCH 1121/1435] flash_loader: disable interrupt before start --- src/common.c | 16 ++++++++++++++++ src/stlink-lib/flash_loader.c | 13 ++++++++----- 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/src/common.c b/src/common.c index 99049196d..eeccd5f5b 100644 --- a/src/common.c +++ b/src/common.c @@ -2730,6 +2730,13 @@ int stm32l1_write_half_pages( } int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { + + // force halt and disable interrupt + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | + STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_MASKINTS); + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_F7) || (sl->flash_type == STLINK_FLASH_TYPE_L4)) { @@ -2998,6 +3005,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr } int stlink_flashloader_stop(stlink_t *sl) { + uint32_t dhcsr; + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_F7) || (sl->flash_type == STLINK_FLASH_TYPE_L4) || @@ -3028,6 +3037,13 @@ int stlink_flashloader_stop(stlink_t *sl) { stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); } + // enable interrupt + if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | + STLINK_REG_DHCSR_C_DEBUGEN | + (dhcsr&(~STLINK_REG_DHCSR_C_MASKINTS))); + } + return(0); } diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 5bc314b07..9fa897ccc 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -293,7 +293,6 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe struct stlink_reg rr; unsigned timeout; uint32_t flash_base = 0; - const char *error = NULL; uint32_t dhcsr, dfsr, cfsr, hfsr; DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); @@ -342,7 +341,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe } if (timeout) { - error = "Flash loader run error"; + ELOG("Flash loader run error\n"); goto error; } @@ -350,7 +349,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe stlink_read_reg(sl, 2, &rr); if (rr.r[2] != 0) { - error = "Write error"; + ELOG("Write error\n"); goto error; } @@ -363,8 +362,12 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe stlink_read_debug32(sl, STLINK_REG_CFSR, &cfsr); stlink_read_debug32(sl, STLINK_REG_HFSR, &hfsr); stlink_read_all_regs(sl, &rr); - ELOG("%s (R2 0x%X R15 0x%X DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X)\n", error, rr.r[2], rr.r[15], dhcsr, dfsr, cfsr, hfsr); - ELOG("(R0 0x%X R1 0x%X)\n", rr.r[0], rr.r[1]); + + WLOG("Loader state: R2 0x%X R15 0x%X\n", rr.r[2], rr.r[15]); + if (dhcsr != 0x3000B || dfsr != 0x3 || cfsr || hfsr) { + WLOG("MCU state: DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X\n", + dhcsr, dfsr, cfsr, hfsr); + } return(-1); } From bc9062c6c590e603e203567b6bfe14baf4c6a0af Mon Sep 17 00:00:00 2001 From: anton Date: Fri, 19 Mar 2021 18:59:09 +0500 Subject: [PATCH 1122/1435] flash_loader: preventing unpredictable behavior when disabling interrupts --- src/common.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index eeccd5f5b..1fd023962 100644 --- a/src/common.c +++ b/src/common.c @@ -2731,7 +2731,11 @@ int stm32l1_write_half_pages( int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - // force halt and disable interrupt + // According to DDI0419C, Table C1-7 firstly force halt + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | + STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT); + // and only then disable interrupts stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | STLINK_REG_DHCSR_C_HALT | From de89563057fca8d0aaa6b6dfa8655557523507e6 Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 20 Mar 2021 14:09:52 +0500 Subject: [PATCH 1123/1435] gdb-server: added target description for all mcu --- src/st-util/gdb-server.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 4177cef11..e35e5c2e8 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -288,7 +288,7 @@ int main(int argc, char** argv) { return(0); } -static const char* const target_description_F4 = +static const char* const target_description = "" "" "" @@ -1178,13 +1178,7 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("query: %s;%s\n", queryName, params); if (!strcmp(queryName, "Supported")) { - if (sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F4_HD || - sl->core_id == STM32F7_CORE_ID) { - reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); - } else { - reply = strdup("PacketSize=3fff;qXfer:memory-map:read+"); - } + reply = strdup("PacketSize=3fff;qXfer:memory-map:read+;qXfer:features:read+"); } else if (!strcmp(queryName, "Xfer")) { char *type, *op, *__s_addr, *s_length; char *tok = params; @@ -1202,14 +1196,15 @@ int serve(stlink_t *sl, st_state_t *st) { DLOG("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", type, op, annex, addr, length); - const char* data = NULL; - - if (!strcmp(type, "memory-map") && !strcmp(op, "read")) { + const char* data; + if (strcmp(op, "read")) { + data = NULL; + } else if (!strcmp(type, "memory-map")) { data = current_memory_map; - } - - if (!strcmp(type, "features") && !strcmp(op, "read")) { - data = target_description_F4; + } else if (!strcmp(type, "features")) { + data = target_description; + } else { + data = NULL; } if (data) { @@ -1592,7 +1587,7 @@ int serve(stlink_t *sl, st_state_t *st) { reply = strdup("E00"); } - if (ret) { DLOG("p packet: stlink_read_unsupported_reg failed with id %u\n", id); } + if (ret) { DLOG("p packet: could not read register with id %u\n", id); } if (reply == NULL) { // if reply is set to "E00", skip From 9083d43d15ed53c575d48c71f6dbf31c8882b4f1 Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 20 Mar 2021 14:48:52 +0500 Subject: [PATCH 1124/1435] gdb-server: fixed initialization of flash segments --- src/st-util/gdb-server.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index e35e5c2e8..080d434b3 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -817,10 +817,11 @@ static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { } struct flash_block* new = malloc(sizeof(struct flash_block)); - new->next = flash_root; + new->next = flash_root; new->addr = addr; new->length = length; - new->data = calloc(length, 1); + new->data = malloc(length); + memset(new->data, stlink_get_erased_pattern(sl), length); flash_root = new; return(0); From 7c5ac5908cf16d1b1b8c7d355ac6856461aab3c4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 20 Mar 2021 12:18:56 +0100 Subject: [PATCH 1125/1435] Updated travis CI config for macOS --- .travis.yml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.travis.yml b/.travis.yml index fefafbaf1..5d2e5fbdf 100644 --- a/.travis.yml +++ b/.travis.yml @@ -129,6 +129,8 @@ jobs: ### macOS ### - os: osx env: BADGE=osx + osx_image: xcode12.2 + name: macOS 10.15.7 compiler: gcc addons: homebrew: @@ -138,6 +140,8 @@ jobs: - gtk+3 - os: osx env: BADGE=osx + osx_image: xcode12.2 + name: macOS 10.15.7 compiler: clang addons: homebrew: From 5e0a502df812495bfa96fa9116a19f1306152b17 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 20 Mar 2021 15:44:09 +0100 Subject: [PATCH 1126/1435] General Project Update - Updated CHANGELOG.md - Updated README.md - [doc] Official STLINK-V3 support (Closes #820, Closes #1022, Closes #1025) - Updated list of contributors - Updated info on version support - Minor formatting fixes --- CHANGELOG.md | 3 ++ README.md | 18 +++---- contributors.txt | 1 + doc/compiling.md | 113 ++++++++++++++++++++--------------------- doc/version_support.md | 80 ++++++++++++++--------------- 5 files changed, 109 insertions(+), 106 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index cacd79eef..7ca94dbc8 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -7,6 +7,7 @@ Release date: (TBD) Features: - Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) +- Official support for STLINK-V3 programmers ([#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) - Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) - Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) - Use SetConsoleCtrlHandler for Windows ([#1021](https://github.com/stlink-org/stlink/pull/1021)) @@ -32,6 +33,7 @@ Updates & changes: Fixes: +- Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) - cmake compile failure with external `CMAKE_MODULE_PATH` set ([#962](https://github.com/stlink-org/stlink/pull/962)) - doc/man: Fixed installation directory ([#970](https://github.com/stlink-org/stlink/pull/970)) @@ -53,6 +55,7 @@ Fixes: - Fixed support for writing option bytes ([#1102](https://github.com/stlink-org/stlink/pull/1102)) - [doc] Corrected spelling mistake in bug report template ([#1103](https://github.com/stlink-org/stlink/pull/1103)) - Fixed support for STLINK/V1 programmer ([#1045](https://github.com/stlink-org/stlink/pull/1045), [#1105](https://github.com/stlink-org/stlink/pull/1105)) +- Fixed STM32WB55 reading DEBUG IDCODE from the wrong address ([#1100](https://github.com/stlink-org/stlink/pull/1100), [#1101](https://github.com/stlink-org/stlink/pull/1101)) # v1.6.1 diff --git a/README.md b/README.md index 8a8600947..7ddc78005 100644 --- a/README.md +++ b/README.md @@ -17,21 +17,24 @@ The stlink library and tools are licensed under the **[BSD-3 License](LICENSE.md ## Introduction -STLink is an open source toolset to program and debug STM32 devices and boards manufactured by STMicroelectronics. +stlink is an open source toolset to program and debug STM32 devices and boards manufactured by STMicroelectronics. It supports several so called STLINK programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG/SWD. There are four generations available on the market which are _all_ supported by this toolset: - **STLINK/V1** _[obsolete as of 21-11-2019, continued support by this toolset] \*)_ - transport layer: SCSI passthru commands over USB - - stand-alone programmer and present on STM32VL Discovery boards + - stand-alone programmer + - on-board on STM32VL Discovery boards - **STLINK/V2** - transport layer: raw USB commands - - stand-alone programmer and present on STM32L Discovery and Nucleo boards + - stand-alone programmer + - on-board on STM32L Discovery and STM32 Nucleo boards - **STLINK/V2-1** - transport layer: raw USB commands - - present on some STM32 Nucleo boards -- **STLINK/V3** + - on-board on some STM32 Nucleo boards +- **STLINK-V3** - transport layer: raw USB commands - - stand-alone programmer + - stand-alone programmer (STLINK-V3SET, STLINK-V3MINI, STLINK-V3MODS) + - on-board on some STM32 Nucleo boards _\*)_ **Note: Support for the STLINK/V1 on macOS is limited to 10.14 - 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.** @@ -52,9 +55,6 @@ Currently known working combinations of programmers and targets are listed in [d Supported operating systems are listed in [version_support.md](doc/version_support.md). -The `stlink` toolset continues to maintain backwards compatibility with the **STLINK/v1** programmer.
      -Please note that on macOS this support is limited to versions 10.13 - 10.15. - ## Tutorial & HOWTO Our [tutorial](doc/tutorial.md) may help you along with some advanced tasks and additional info. diff --git a/contributors.txt b/contributors.txt index 38cc9cd42..88f1f0c89 100644 --- a/contributors.txt +++ b/contributors.txt @@ -113,6 +113,7 @@ Simon Wright Stany Marcel Stefan Misik Sven Wegener +Tarek Bochkati [tarek-bochkati] (STMicroelectronics) Timothy Lee [timothytylee] Tuomo Kaikkonen Theodore A. Roth diff --git a/doc/compiling.md b/doc/compiling.md index 07193f357..eef207f95 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -1,14 +1,14 @@ # Compiling from sources ## Microsoft Windows (10, 8.1) + ### Common Requirements On Windows users should ensure that the following software is installed: -* `git` (_optional, but recommended_) -* `cmake` (3.17.0 or later) -* `MinGW-w64` (7.0.0 or later) with GCC toolchain 8.1.0 - +- `git` (_optional, but recommended_) +- `cmake` (3.17.0 or later) +- `MinGW-w64` (7.0.0 or later) with GCC toolchain 8.1.0 ### Installation @@ -16,12 +16,14 @@ On Windows users should ensure that the following software is installed: 2. Install `cmake` from
      Ensure that you add cmake to the $PATH system variable when following the instructions by the setup assistant. 3. Install - - _EITHER_: **MinGW-w64** from (mingw-w64-install.exe)
      - - _OR_: **MSVC toolchain** from Visual Studio Build Tools 2019 + +- _EITHER_: **MinGW-w64** from (mingw-w64-install.exe)
      +- _OR_: **MSVC toolchain** from Visual Studio Build Tools 2019 + 4. Create a new destination folder at a place of your choice 5. Open the command-line (cmd.exe) and execute `cd C:\$Path-to-your-destination-folder$\` 6. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git`from the command-line (cmd.exe)
      - or download the stlink zip-sourcefolder from the Release page on GitHub + or download the stlink zip-sourcefolder from the Release page on GitHub #### MSVC toolchain - minimal installation @@ -31,15 +33,19 @@ Visual Studio IDE is not necessary, only Windows SDK & build tools are required 2. Navigate through menus as follows (might change overtime) `All downloads > Tools for Visual Studio 2019 > Build Tools for Visual Studio 2019 > Download` + 3. Start downloaded executable. After Visual Studio Installer bootstraps and main window pops up, open `Individual Components` tab, and pick - - latest build tools (eg. `MSVC v142 - VS 2019 C++ x64/x86 build tools (v14.25)`) - - latest Windows SDK (eg. `Windows 10 SDK (10.0.18362.0)`) + +- latest build tools (eg. `MSVC v142 - VS 2019 C++ x64/x86 build tools (v14.25)`) +- latest Windows SDK (eg. `Windows 10 SDK (10.0.18362.0)`) + 4. After installation finishes, you can press `Launch` button in Visual Studio Installer's main menu. - Thus you can open `Developer Command Prompt for VS 2019`. It is `cmd.exe` instance with adjusted PATHs including eg. `msbuild`. - Alternatively, you can use `Developer Powershell for VS 2019` which is the same thing for `powershell.exe`. Both are available from Start menu. - Another option is to add `msbuild` to PATH manually. Its location should be `C:\Program Files (x86)\Microsoft Visual Studio\2019\BuildTools\MSBuild\Current\Bin`. Then, it should be available from any `powershell.exe` or `cmd.exe` session. ### Building + #### MinGW-w64 1. Use the command-line to move to the `scripts` directory within the source-folder: `cd stlink\scripts\` @@ -50,7 +56,6 @@ Per default the build script (currently) uses `C:\Program Files\mingw-w64\x86_64 When installing different toolchains make sure to update the path in the `mingw64-build.bat`.
      This can be achieved by opening the .bat file with a common text editor. - #### MSVC toolchain 1. In a command prompt, change the directory to the folder where the stlink files were cloned (or unzipped) to. @@ -59,12 +64,15 @@ This can be achieved by opening the .bat file with a common text editor. This will create a solution file `stlink.sln` in the build folder. Now, you can build whole `stlink` suite using following command: + ``` msbuild /m /p:Configuration=Release stlink.sln ``` + Options: + - `/m` - compilation runs in parallel utilizing multiple cores -- `/p:Configuration=Release` - generates *Release*, optimized build. +- `/p:Configuration=Release` - generates _Release_, optimized build. Directory `\build\Release` contains final executables. (`st-util.exe` is located in `\build\src\gdbserver\Release`). @@ -79,25 +87,25 @@ It can be copied from: `\build\3rdparty\libusb-{version}\MS{arch}\ [ST-LINK drivers](https://www.st.com/en/development-tools/stsw-link009.html) are required for `stlink` to work. ## Linux + ### Common requirements Install the following packages from your package repository: -* `git` -* `gcc` or `clang` or `mingw32-gcc` or `mingw64-gcc` (C-compiler; very likely gcc is already present) -* `build-essential` (on Debian based distros (Debian, Ubuntu)) -* `cmake` (3.4.2 or later, use the latest version available from the repository) -* `rpm` (on Debian based distros (Debian, Ubuntu), needed for package build with `make package`) -* `libusb-1.0` -* `libusb-1.0-0-dev` (development headers for building) -* `libgtk-3-dev` (_optional_, needed for `stlink-gui`) -* `pandoc` (_optional_, needed for generating manpages from markdown) +- `git` +- `gcc` or `clang` or `mingw32-gcc` or `mingw64-gcc` (C-compiler; very likely gcc is already present) +- `build-essential` (on Debian based distros (Debian, Ubuntu)) +- `cmake` (3.4.2 or later, use the latest version available from the repository) +- `rpm` (on Debian based distros (Debian, Ubuntu), needed for package build with `make package`) +- `libusb-1.0` +- `libusb-1.0-0-dev` (development headers for building) +- `libgtk-3-dev` (_optional_, needed for `stlink-gui`) +- `pandoc` (_optional_, needed for generating manpages from markdown) or execute (Debian-based systems only): `apt-get install gcc build-essential cmake libusb-1.0 libusb-1.0-0-dev libgtk-3-dev pandoc` (Replace gcc with the intended C-compiler if necessary or leave out any optional package not needed.) - ### Installation 1. Open a new terminal console @@ -105,7 +113,6 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma 3. Change to this directory: `cd ~/git` 4. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git` - ### Building #### Installation: @@ -120,21 +127,19 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. - -#### Removal: +#### Removal: 1. Run `make uninstall` to perform a clean uninstall of the package from the system. 2. Run `make clean` to clean the build-folder within the project source and remove all compiled and linked files and libraries. - ### Cross-Building for Windows Install the following packages from your package repository: -* `mingw-w64` -* `mingw-w64-common` -* `mingw-w64-i686-dev` -* `mingw-w64-x86-64-dev` +- `mingw-w64` +- `mingw-w64-common` +- `mingw-w64-i686-dev` +- `mingw-w64-x86-64-dev` After following the steps for installation above, proceed with from the build dircetory itself: @@ -144,7 +149,6 @@ $ sudo sh ./cmake/packaging/windows/generate_binaries.sh The generated zip-packages can be found in the subdirectory `./build/dist`. - ### Set device access permissions and the role of udev By default most distributions don't allow access to USB devices. @@ -162,22 +166,21 @@ $ sudo udevadm trigger udev will now create device node files, e.g. `/dev/stlinkv3_XX`, `/dev/stlinkv2_XX`, `/dev/stlinkv1_XX`. - ### Special note on the use of STLink/V1 programmers (legacy): As the STLINKV1's SCSI emulation is somehow broken, the best advice possibly is to tell your operating system to completely ignore it.
      Choose one of the following options _before_ connecting the device to your computer: -* `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` -* _OR_ - 1. `echo "options usb-storage quirks=483:3744:i" >> /etc/modprobe.conf` - 2. `modprobe -r usb-storage && modprobe usb-storage` -* _OR_ - 1. `cp stlink_v1.modprobe.conf /etc/modprobe.d` - 2. `modprobe -r usb-storage && modprobe usb-storage` - +- `modprobe -r usb-storage && modprobe usb-storage quirks=483:3744:i` +- _OR_ + 1. `echo "options usb-storage quirks=483:3744:i" >> /etc/modprobe.conf` + 2. `modprobe -r usb-storage && modprobe usb-storage` +- _OR_ + 1. `cp stlink_v1.modprobe.conf /etc/modprobe.d` + 2. `modprobe -r usb-storage && modprobe usb-storage` ## macOS + ### Common requirements The best and recommended way is to install a package manager for open source software, @@ -185,21 +188,20 @@ either [homebrew](https://brew.sh) or [MacPorts](https://www.macports.org/). Then install the following dependencies from the package repository: -* `git` -* `gcc` or `llvm` (for clang) (C-compiler) -* `cmake` -* `libusb` -* `gtk+3` or `gtk3` (_optional_, needed for `stlink-gui`) +- `git` +- `gcc` or `llvm` (for clang) (C-compiler) +- `cmake` +- `libusb` +- `gtk+3` or `gtk3` (_optional_, needed for `stlink-gui`) To do this with only one simple command, type: -* for homebrew: - - with gcc: `sudo brew install git gcc cmake libusb gtk+3` or - - with clang: `sudo brew install git llvm cmake libusb gtk+3` or -* for MacPorts: - - with gcc: `sudo port install git gcc10 cmake libusb gtk3` or - - with clang: `sudo port install git llvm-10 cmake libusb gtk3` - +- for homebrew: + - with gcc: `sudo brew install git gcc cmake libusb gtk+3` or + - with clang: `sudo brew install git llvm cmake libusb gtk+3` or +- for MacPorts: + - with gcc: `sudo port install git gcc10 cmake libusb gtk3` or + - with clang: `sudo port install git llvm-10 cmake libusb gtk3` ### Installation @@ -208,7 +210,6 @@ To do this with only one simple command, type: 3. Change to this directory: `cd ~/git` 4. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git` - ### Building 1. Change into the project source directory: `cd stlink` @@ -217,14 +218,13 @@ To do this with only one simple command, type: 4. Run `make debug` to create the _Debug_ target (_optional_)
      The debug target is only necessary in order to modify the sources and to run under a debugger. - ## Build options + ### Build using a different directory for shared libs To put the compiled shared libs into a different directory during installation, you can use the cmake option `cmake -DLIB_INSTALL_DIR:PATH="/usr/lib64" ..`. - ### Standard installation directories The cmake build system of this toolset includes `GNUInstallDirs` to define GNU standard installation directories. @@ -232,8 +232,7 @@ This module provides install directory variables as defined by the GNU Coding St Below are the preset default cmake options, which apply if none of these options are redefined: -* `-DCMAKE_INSTALL_SYSCONFDIR=/etc` -* `-DCMAKE_INSTALL_PREFIX=/usr/local` - +- `-DCMAKE_INSTALL_SYSCONFDIR=/etc` +- `-DCMAKE_INSTALL_PREFIX=/usr/local` Author: nightwalker-87 diff --git a/doc/version_support.md b/doc/version_support.md index eca491b79..1edf2e19c 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -23,52 +23,52 @@ NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 a ### Linux-/Unix-based: -| Operating System | libusb
      version | cmake
      version | gtk-3
      version | Notes | -| -------------------------------- | ----------------------- | ------------------ | ----------------------------------------- | --------------------------------------------------- | --------------------------------------------------- | -| Alpine Edge | 1.0.23 | 3.17.0 | 3.99.0
      gtk+3.0 | | -| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | 3.24.18
      libgtk+3 | | -| Arch Linux | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | -| Fedora Rawhide | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | named `libusbx`, but
      `libusb`-codebase is used | -| KaOS | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | -| OpenMandriva Cooker | 1.0.23 | 3.17.0 | 3.24.18
      libgtk+3.0
      lib64gtk+3.0 | | -| PCLinuxOS | 1.0.23
      lib64usb1.0 | 3.17.0 | 3.24.18
      lib64gtk+3.0 | | -| Slackware Current | 1.0.23 | 3.17.0 | 3.24.18
      gtk+3 | | -| Solus | 1.0.23 | 3.16.5 | 3.24.16
      libgtk-3 | | -| Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
      libgtk-3 | | -| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | 3.24.13
      libgtk+3.0
      lib64gtk+3.0 | | -| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
      libgtk-3 | | -| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | 3.24.16
      gtk3 | | -| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.13
      gtk+3.0 | | -| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
      libgtk-3 | | -| Mageia Cauldron | 1.0.22 | 3.17.0 | 3.24.18
      libgtk+3.0
      lib64gtk+3.0 | | -| NetBSD 9.0 | 1.0.22 | 3.16.1 | 3.24.12
      gtk+3 | | -| NetBSD 8.1 | 1.0.22 | 3.16.1 | 3.24.12
      gtk+3 | | -| NetBSD 7.2 | 1.0.22 | 3.16.1 | _N/A_ | | -| Alpine 3.10 | 1.0.22 | 3.14.5 | 3.24.8
      gtk+3.0 | | -| Fedora 31 | 1.0.22 | 3.14.5 | 3.24.12
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | -| Mageia 7.1 | 1.0.22 | 3.14.3 | 3.24.8
      libgtk+3.0
      lib64gtk+3.0 | | -| Fedora 30 | 1.0.22 | 3.14.2 | 3.24.8
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | -| Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
      libgtk-3 | | -| Alpine 3.9 | 1.0.22 | 3.13.0 | 3.24.1
      gtk+3.0 | | -| CentOS 8 | 1.0.22 | 3.11.4 | 3.22.30
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | -| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | 3.24.14
      gtk3 | | -| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | 3.22.30
      gtk3 | | -| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
      libgtk-3 | | -| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
      libgtk-3 | | -| Slackware 14.2 | **1.0.20** | 3.5.2 | 3.18.9
      gtk+3 | | -| Ubuntu 16.04 LTS (Xenial Xerus) | **1.0.20** | 3.5.1 | 3.18.9
      libgtk-3 | | -| OpenMandriva Lx 3.0 | **1.0.20** | **3.4.2** | 3.18.9
      libgtk+3.0
      lib64gtk+3.0 | | -| FreeBSD 13 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-13.0r358841
      (integrated) | -| FreeBSD 12 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-11.0r261448_4
      (integrated) | -| FreeBSD 11 | **1.0.16** - 1.0.18 | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-11.0r261448_4
      (integrated) | +| Operating System | libusb
      version | cmake
      version | gtk-3
      version | Notes | +| -------------------------------- | ----------------------- | ------------------ | ----------------------------------------- | ----------------------------------------------------------------------------- | +| Alpine Edge | 1.0.23 | 3.17.0 | 3.99.0
      gtk+3.0 | | +| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | 3.24.18
      libgtk+3 | | +| Arch Linux | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | +| Fedora Rawhide | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | +| KaOS | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | +| OpenMandriva Cooker | 1.0.23 | 3.17.0 | 3.24.18
      libgtk+3.0
      lib64gtk+3.0 | | +| PCLinuxOS | 1.0.23
      lib64usb1.0 | 3.17.0 | 3.24.18
      lib64gtk+3.0 | | +| Slackware Current | 1.0.23 | 3.17.0 | 3.24.18
      gtk+3 | | +| Solus | 1.0.23 | 3.16.5 | 3.24.16
      libgtk-3 | | +| Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
      libgtk-3 | | +| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | 3.24.13
      libgtk+3.0
      lib64gtk+3.0 | | +| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
      libgtk-3 | | +| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | 3.24.16
      gtk3 | | +| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.13
      gtk+3.0 | | +| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
      libgtk-3 | | +| Mageia Cauldron | 1.0.22 | 3.17.0 | 3.24.18
      libgtk+3.0
      lib64gtk+3.0 | | +| NetBSD 9.0 | 1.0.22 | 3.16.1 | 3.24.12
      gtk+3 | | +| NetBSD 8.1 | 1.0.22 | 3.16.1 | 3.24.12
      gtk+3 | | +| NetBSD 7.2 | 1.0.22 | 3.16.1 | _N/A_ | | +| Alpine 3.10 | 1.0.22 | 3.14.5 | 3.24.8
      gtk+3.0 | | +| Fedora 31 | 1.0.22 | 3.14.5 | 3.24.12
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | +| Mageia 7.1 | 1.0.22 | 3.14.3 | 3.24.8
      libgtk+3.0
      lib64gtk+3.0 | | +| Fedora 30 | 1.0.22 | 3.14.2 | 3.24.8
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | +| Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
      libgtk-3 | | +| Alpine 3.9 | 1.0.22 | 3.13.0 | 3.24.1
      gtk+3.0 | | +| CentOS 8 | 1.0.22 | 3.11.4 | 3.22.30
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | +| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | 3.24.14
      gtk3 | | +| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | 3.22.30
      gtk3 | | +| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
      libgtk-3 | | +| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
      libgtk-3 | | +| Slackware 14.2 | 1.0.20 | 3.5.2 | 3.18.9
      gtk+3 | | +| Ubuntu 16.04 LTS (Xenial Xerus) | 1.0.20 | 3.5.1 | 3.18.9
      libgtk-3 | | +| OpenMandriva Lx 3.0x | 1.0.20 | **3.4.2** | 3.18.9
      libgtk+3.0
      lib64gtk+3.0 | | +| FreeBSD 13 | **1.0.16 - 1.0.18** | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-13.0r358841
      LIBUSB_API_VERSION 0x01000102
      (integrated) | +| FreeBSD 12 | **1.0.16 - 1.0.18** | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-13.0r358841
      LIBUSB_API_VERSION 0x01000102
      (integrated) | +| FreeBSD 11 | **1.0.16 - 1.0.18** | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-13.0r358841
      LIBUSB_API_VERSION 0x01000102
      (integrated) | ## Unsupported Operating Systems (as of Release v1.6.1) | Operating System | libusb
      version | cmake
      version | End of
      OS-Support | Notes | | ------------------------------ | ------------------- | ------------------ | ---------------------- | --------------------------------------------------- | | CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but
      `libusb`-codebase is used | -| Debian 8 (Jessie) | 1.0.**19** | 3.**0.2** | Jun 2020 | -| Ubuntu 14.04 LTS (Trusty Tahr) | 1.0.**17** | **2.8.12.2** | Apr 2019 | +| Debian 8 (Jessie) | 1.0.19 | **3.0.2** | Jun 2020 | +| Ubuntu 14.04 LTS (Trusty Tahr) | 1.0.17 | **2.8.12.2** | Apr 2019 | | CentOS 6 | 1.0.**9** | **2.8.12.2** | Dec 2020 | named `libusbx`, but
      `libusb`-codebase is used | | Slackware 14.1 | 1.0.**9** | **2.8.12** | | | Slackware 14.0 | 1.0.**9** | **2.8.8** | | From 7c7ce954045d9734198d7345477b94bcf58f770e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 21 Mar 2021 14:17:35 +0100 Subject: [PATCH 1127/1435] Create codeql-analysis.yml Setup for code scanning alerts --- .github/workflows/codeql-analysis.yml | 67 +++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 .github/workflows/codeql-analysis.yml diff --git a/.github/workflows/codeql-analysis.yml b/.github/workflows/codeql-analysis.yml new file mode 100644 index 000000000..202867cfc --- /dev/null +++ b/.github/workflows/codeql-analysis.yml @@ -0,0 +1,67 @@ +# For most projects, this workflow file will not need changing; you simply need +# to commit it to your repository. +# +# You may wish to alter this file to override the set of languages analyzed, +# or to provide custom queries or build logic. +# +# ******** NOTE ******** +# We have attempted to detect the languages in your repository. Please check +# the `language` matrix defined below to confirm you have the correct set of +# supported CodeQL languages. +# +name: "CodeQL" + +on: + push: + branches: [ develop, master ] + pull_request: + # The branches below must be a subset of the branches above + branches: [ develop ] + schedule: + - cron: '23 20 * * 2' + +jobs: + analyze: + name: Analyze + runs-on: ubuntu-latest + + strategy: + fail-fast: false + matrix: + language: [ 'cpp' ] + # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python' ] + # Learn more: + # https://docs.github.com/en/free-pro-team@latest/github/finding-security-vulnerabilities-and-errors-in-your-code/configuring-code-scanning#changing-the-languages-that-are-analyzed + + steps: + - name: Checkout repository + uses: actions/checkout@v2 + + # Initializes the CodeQL tools for scanning. + - name: Initialize CodeQL + uses: github/codeql-action/init@v1 + with: + languages: ${{ matrix.language }} + # If you wish to specify custom queries, you can do so here or in a config file. + # By default, queries listed here will override any specified in a config file. + # Prefix the list here with "+" to use these queries and those in the config file. + # queries: ./path/to/local/query, your-org/your-repo/queries@main + + # Autobuild attempts to build any compiled languages (C/C++, C#, or Java). + # If this step fails, then you should remove it and run the build manually (see below) + - name: Autobuild + uses: github/codeql-action/autobuild@v1 + + # ℹ️ Command-line programs to run using the OS shell. + # 📚 https://git.io/JvXDl + + # ✏️ If the Autobuild fails above, remove it and uncomment the following three lines + # and modify them (or add more) to build your code if your project + # uses a compiled language + + #- run: | + # make bootstrap + # make release + + - name: Perform CodeQL Analysis + uses: github/codeql-action/analyze@v1 From ab6094a615f31653c1f0b355e05c5a29a338aa39 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 21 Mar 2021 14:26:10 +0100 Subject: [PATCH 1128/1435] Create cmake.yml Added Github Action - CMake Workflow Build and test a CMake based project. --- .github/workflows/cmake.yml | 46 +++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 .github/workflows/cmake.yml diff --git a/.github/workflows/cmake.yml b/.github/workflows/cmake.yml new file mode 100644 index 000000000..005915e6e --- /dev/null +++ b/.github/workflows/cmake.yml @@ -0,0 +1,46 @@ +name: CMake + +on: [push] + +env: + # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.) + BUILD_TYPE: Release + +jobs: + build: + # The CMake configure and build commands are platform agnostic and should work equally + # well on Windows or Mac. You can convert this to a matrix build if you need + # cross-platform coverage. + # See: https://docs.github.com/en/free-pro-team@latest/actions/learn-github-actions/managing-complex-workflows#using-a-build-matrix + runs-on: ubuntu-latest + + steps: + - uses: actions/checkout@v2 + + - name: Create Build Environment + # Some projects don't allow in-source building, so create a separate build directory + # We'll use this as our working directory for all subsequent commands + run: cmake -E make_directory ${{github.workspace}}/build + + - name: Configure CMake + # Use a bash shell so we can use the same syntax for environment variable + # access regardless of the host operating system + shell: bash + working-directory: ${{github.workspace}}/build + # Note the current convention is to use the -S and -B options here to specify source + # and build directories, but this is only available with CMake 3.13 and higher. + # The CMake binaries on the Github Actions machines are (as of this writing) 3.12 + run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE + + - name: Build + working-directory: ${{github.workspace}}/build + shell: bash + # Execute the build. You can specify a specific target with "--target " + run: cmake --build . --config $BUILD_TYPE + + - name: Test + working-directory: ${{github.workspace}}/build + shell: bash + # Execute tests defined by the CMake configuration. + # See https://cmake.org/cmake/help/latest/manual/ctest.1.html for more detail + run: ctest -C $BUILD_TYPE From 812bc6ed4fae1078f00616d217a7b91e3480fa0f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 21 Mar 2021 14:58:45 +0100 Subject: [PATCH 1129/1435] Create c-cpp.yml Added Github Action - Make Workflow Build and test a C/C++ project using Make. --- .github/workflows/c-cpp.yml | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 .github/workflows/c-cpp.yml diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml new file mode 100644 index 000000000..e211e4e54 --- /dev/null +++ b/.github/workflows/c-cpp.yml @@ -0,0 +1,23 @@ +name: C/C++ CI + +on: + push: + branches: [ testing ] + pull_request: + branches: [ testing ] + +jobs: + build: + + runs-on: ubuntu-latest + + steps: + - uses: actions/checkout@v2 + - name: configure + run: ./configure + - name: make + run: make + - name: make check + run: make check + - name: make distcheck + run: make distcheck From c677eb2f4dfd669bec7c73f1a324e0624908968a Mon Sep 17 00:00:00 2001 From: anton Date: Tue, 23 Mar 2021 20:06:47 +0500 Subject: [PATCH 1130/1435] flash_loader: makefile simplification --- flashloaders/Makefile | 75 +++++++++++++++---------------------------- 1 file changed, 25 insertions(+), 50 deletions(-) diff --git a/flashloaders/Makefile b/flashloaders/Makefile index 3517e1499..d4ca4d22a 100644 --- a/flashloaders/Makefile +++ b/flashloaders/Makefile @@ -1,10 +1,7 @@ -# Note that according to the original GPLed code, compiling is noted to be -# as simple as gcc -c, this fails with my tests where this will lead to a wrong -# address read by the program. -# This makefile will save your time from dealing with compile errors -# Adjust CC if needed +# The flash loader code cannot be compiled by the system gcc. This +# makefile use arm-none-eabi-gcc for this purpose -CROSS_COMPILE ?= /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi- +CROSS_COMPILE ?= arm-none-eabi- CC = $(CROSS_COMPILE)gcc OBJCOPY = $(CROSS_COMPILE)objcopy @@ -12,52 +9,30 @@ OBJCOPY = $(CROSS_COMPILE)objcopy XXD = xxd XXDFLAGS = -i -c 4 -CFLAGS_THUMB1 = -mcpu=Cortex-M0 -Tlinker.ld -ffreestanding -nostdlib -CFLAGS_THUMB2 = -mcpu=Cortex-M3 -Tlinker.ld -ffreestanding -nostdlib +CFLAGS_ARMV6_M = -mcpu=Cortex-M0 -Tlinker.ld -ffreestanding -nostdlib +CFLAGS_ARMV7_M = -mcpu=Cortex-M3 -Tlinker.ld -ffreestanding -nostdlib all: stm32vl.h stm32f0.h stm32lx.h stm32f4.h stm32f4lv.h stm32l4.h stm32f7.h stm32f7lv.h + -stm32f0.h: stm32f0.s - $(CC) stm32f0.s $(CFLAGS_THUMB1) -o stm32f0.o - $(OBJCOPY) -O binary stm32f0.o stm32f0.bin - $(XXD) $(XXDFLAGS) stm32f0.bin stm32f0.h - -stm32vl.h: stm32f0.s - $(CC) stm32f0.s $(CFLAGS_THUMB2) -o stm32vl.o - $(OBJCOPY) -O binary stm32vl.o stm32vl.bin - $(XXD) $(XXDFLAGS) stm32vl.bin stm32vl.h - -stm32lx.h: stm32lx.s - $(CC) stm32lx.s $(CFLAGS_THUMB2) -o stm32lx.o - $(OBJCOPY) -O binary stm32lx.o stm32lx.bin - $(XXD) $(XXDFLAGS) stm32lx.bin stm32lx.h - -stm32f4.h: stm32f4.s - $(CC) stm32f4.s $(CFLAGS_THUMB2) -o stm32f4.o - $(OBJCOPY) -O binary stm32f4.o stm32f4.bin - $(XXD) $(XXDFLAGS) stm32f4.bin stm32f4.h - -stm32f4lv.h: stm32f4lv.s - $(CC) stm32f4lv.s $(CFLAGS_THUMB2) -o stm32f4lv.o - $(OBJCOPY) -O binary stm32f4lv.o stm32f4lv.bin - $(XXD) $(XXDFLAGS) stm32f4lv.bin stm32f4lv.h - -stm32l4.h: stm32l4.s - $(CC) stm32l4.s $(CFLAGS_THUMB2) -o stm32l4.o - $(OBJCOPY) -O binary stm32l4.o stm32l4.bin - $(XXD) $(XXDFLAGS) stm32l4.bin stm32l4.h - -stm32f7.h: stm32f7.s - $(CC) stm32f7.s $(CFLAGS_THUMB2) -o stm32f7.o - $(OBJCOPY) -O binary stm32f7.o stm32f7.bin - $(XXD) $(XXDFLAGS) stm32f7.bin stm32f7.h - -stm32f7lv.h: stm32f7lv.s - $(CC) stm32f7lv.s $(CFLAGS_THUMB2) -o stm32f7lv.o - $(OBJCOPY) -O binary stm32f7lv.o stm32f7lv.bin - $(XXD) $(XXDFLAGS) stm32f7lv.bin stm32f7lv.h +%.h: %.bin + $(XXD) $(XXDFLAGS) $< $@ + +%.bin: %.o + $(OBJCOPY) -O binary $< $@ + rm $< + +# separate rule for STM32F0 +stm32f0.o: stm32f0.s + $(CC) stm32f0.s $(CFLAGS_ARMV6_M) -o stm32f0.o + +# separate rule for STM32F1/F3 +stm32vl.o: stm32f0.s + $(CC) stm32f0.s $(CFLAGS_ARMV7_M) -o stm32vl.o + +# generic rule for all other ARMv7-M +%.o: *.s + $(CC) $< $(CFLAGS_ARMV7_M) -o $@ clean: - rm *.o - rm *.bin - rm *.h + rm -f *.h From ee2c9f508e3eaa39d72dd8d41dfe642800a4946e Mon Sep 17 00:00:00 2001 From: anton Date: Tue, 23 Mar 2021 22:33:00 +0500 Subject: [PATCH 1131/1435] Core ID reading rework --- inc/stm32.h | 7 ++++--- src/common.c | 41 ++++++++++++++++++++++++++++++++--------- src/stlink-lib/reg.h | 9 ++++++--- 3 files changed, 42 insertions(+), 15 deletions(-) diff --git a/inc/stm32.h b/inc/stm32.h index ca56a12f5..7d60ab5de 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -8,9 +8,10 @@ #define STM32_H /* Cortex core ids */ -#define STM32VL_CORE_ID 0x1ba01477 -#define STM32F7_CORE_ID 0x5ba02477 -#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 JTAG ID Code (RM0433 pg3065) +#define STM32VL_CORE_ID 0x1ba01477 +#define STM32F7_CORE_ID 0x5ba02477 +#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code +#define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 pg3065) /* Constant STM32 memory map figures */ #define STM32_FLASH_BASE ((uint32_t)0x08000000) diff --git a/src/common.c b/src/common.c index 5f2746e3d..b5bb67e9e 100644 --- a/src/common.c +++ b/src/common.c @@ -1229,20 +1229,43 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &cpu_id)) cpu_id = 0; - // If the chip is an H7, read the chipid from the new address - if (sl->core_id == STM32H7_CORE_ID && cpu_id == STLINK_REG_CMx_CPUID_CM7) { + /* + * the chip_id register in the reference manual have + * DBGMCU_IDCODE / DBG_IDCODE name + * + */ + + uint32_t part_no = STLINK_REG_CM3_CPUID_PARTNO(cpu_id); + if ((sl->core_id == STM32H7_CORE_ID || + sl->core_id == STM32H7_CORE_ID_JTAG) && + part_no == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); - } - - if (*chip_id == 0) { + } else if (part_no == STLINK_REG_CMx_CPUID_PARTNO_CM0) { + // STM32F0 (RM0091, pg914; RM0360, pg713) + // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) + // STM32G0 (RM0444, pg1367) + ret = stlink_read_debug32(sl, 0x40015800, chip_id); + } else if (part_no == STLINK_REG_CMx_CPUID_PARTNO_CM33) { + // STM32L5 (RM0438, pg2157) + ret = stlink_read_debug32(sl, 0xE0044000, chip_id); + } else /* СM3, СM4, CM7 */ { // default chipid address + + // STM32F1 (RM0008, pg1087; RM0041, pg681) + // STM32F2 (RM0033, pg1326) + // STM32F3 (RM0316, pg1095; RM0313, pg874) + // STM32F7 (RM0385, pg1676; RM0410, pg1912) + // STM32L1 (RM0038, pg861) + // STM32L4 (RM0351, pg1840; RM0394, pg1560) + // STM32G4 (RM0440, pg2086) + // STM32WB (RM0434, pg1406) ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - } - if (*chip_id == 0) { - // Try Corex M0 DBGMCU_IDCODE register address - ret = stlink_read_debug32(sl, 0x40015800, chip_id); + // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for F2/F4 + if (*chip_id == 0x411 && (cpu_id & 0xfff0) == 0xc240) { + *chip_id = 0x413; + } } return(ret); diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 5a796d7e1..73f608cb6 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -3,9 +3,12 @@ #define STLINK_REG_CM3_CPUID 0xE000ED00 -#define STLINK_REG_CMx_CPUID_CM0 0x410CC200 -#define STLINK_REG_CMx_CPUID_CM3 0x412FC230 -#define STLINK_REG_CMx_CPUID_CM7 0x411FC272 +#define STLINK_REG_CM3_CPUID_PARTNO(cpuid) ((cpuid)&STLINK_REG_CMx_CPUID_PARTNO_MASK) +#define STLINK_REG_CMx_CPUID_PARTNO_MASK 0xFFF0 +#define STLINK_REG_CMx_CPUID_PARTNO_CM0 0xC200 +#define STLINK_REG_CMx_CPUID_PARTNO_CM3 0xC230 +#define STLINK_REG_CMx_CPUID_PARTNO_CM7 0xC270 +#define STLINK_REG_CMx_CPUID_PARTNO_CM33 0xD210 #define STLINK_REG_CM3_FP_CTRL 0xE0002000 // Flash Patch Control Register From 229c721189587760db5509c59b3c02e93e7035c8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 24 Mar 2021 23:26:38 +0100 Subject: [PATCH 1132/1435] General Project Update - Added basic security policy - Updated info on version support for macOS - Updated tutorial.md > Added reference for st-info --probe command > Added section on unknown chip id error (Closes #107, Closes #568, Closes #669) > Added information on HW reset pin issue (Closes #220, Closes #238) --- CHANGELOG.md | 18 ++++++++---- SECURITY.md | 20 +++++++++++++ doc/tutorial.md | 67 ++++++++++++++++++++++++++++++++---------- doc/version_support.md | 8 ++--- 4 files changed, 87 insertions(+), 26 deletions(-) create mode 100644 SECURITY.md diff --git a/CHANGELOG.md b/CHANGELOG.md index 7ca94dbc8..e3f8e13b5 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,12 +2,13 @@ # v1.6.2 -Release date: (TBD) +Release date: (planned H1/2021) Features: +- Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) - Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) -- Official support for STLINK-V3 programmers ([#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) +- Official support for STLINK-V3 programmers (commit [#5e0a502](https://github.com/stlink-org/stlink/commit/5e0a502df812495bfa96fa9116a19f1306152b17), [#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) - Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) - Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) - Use SetConsoleCtrlHandler for Windows ([#1021](https://github.com/stlink-org/stlink/pull/1021)) @@ -15,12 +16,13 @@ Features: - `st-util`: Add specialized memory map for STM32H7 devices ([#1060](https://github.com/stlink-org/stlink/pull/1060)) - Support for STM32F4 option bytes ([#1062](https://github.com/stlink-org/stlink/pull/1062)) - Link for WIN32 & APPLE with stlink-static ([#1069](https://github.com/stlink-org/stlink/pull/1069)) -- Extended support for STM32H7 ([#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) - ITM functionality for STLink/V2 and STM32Fxx chipsets ([#136](https://github.com/stlink-org/stlink/pull/136), [#179](https://github.com/stlink-org/stlink/pull/179), [#815](https://github.com/stlink-org/stlink/pull/815), [#1072](https://github.com/stlink-org/stlink/pull/1072)) - Included ITM functionality for building with MSVC ([#1080](https://github.com/stlink-org/stlink/pull/1080)) Updates & changes: +- [doc] Added tutorial section on unknown chip id error ([#107](https://github.com/stlink-org/stlink/pull/107), [#568](https://github.com/stlink-org/stlink/pull/568), +- [doc] Updated documentation on target resetting ([#261](https://github.com/stlink-org/stlink/pull/261), [#533](https://github.com/stlink-org/stlink/pull/533), [#1107](https://github.com/stlink-org/stlink/pull/1107)) - [doc] Added note on `(gdb) run` command (commit [#03793d4](https://github.com/stlink-org/stlink/commit/03793d42b6078344a9ef8ad55f1d5d0fc19e486e), [#267](https://github.com/stlink-org/stlink/pull/267)) - [doc] `st-flash --reset` parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) - [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) @@ -33,6 +35,7 @@ Updates & changes: Fixes: +- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) - Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) - cmake compile failure with external `CMAKE_MODULE_PATH` set ([#962](https://github.com/stlink-org/stlink/pull/962)) @@ -45,8 +48,10 @@ Fixes: - Fix for `mmap() size_t overflow` in `st-flash` ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) - [regression] `stlink-gui` installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) - `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027), [#1064](https://github.com/stlink-org/stlink/pull/1064), [#1065](https://github.com/stlink-org/stlink/pull/1065)) +- GDB: Fixed problems with target description ([#1013](https://github.com/stlink-org/stlink/pull/1013), [#1088](https://github.com/stlink-org/stlink/pull/1088), [#1109](https://github.com/stlink-org/stlink/pull/1109)) - [doc] Fixed wrong path for `rules.d` folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) - Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) +- Fixed support for STLINK/V1 programmer ([#1045](https://github.com/stlink-org/stlink/pull/1045), [#1105](https://github.com/stlink-org/stlink/pull/1105)) - st-util v1.6.1 does not recognize option --freq (commit [#e576768](https://github.com/stlink-org/stlink/commit/e5767681f14de9851aa970a9299930ca68b2ed92), [#1055](https://github.com/stlink-org/stlink/pull/1055)) - Fixed `gettimeofday` for MSVC ([#1074](https://github.com/stlink-org/stlink/pull/1074)) - Bugfixes for compilation with clang ([#1076](https://github.com/stlink-org/stlink/pull/1076), [#1078](https://github.com/stlink-org/stlink/pull/1078)) @@ -54,7 +59,6 @@ Fixes: - [regression] Flash_loader: increased wait rounds for slow boards ([#1085](https://github.com/stlink-org/stlink/pull/1085)) - Fixed support for writing option bytes ([#1102](https://github.com/stlink-org/stlink/pull/1102)) - [doc] Corrected spelling mistake in bug report template ([#1103](https://github.com/stlink-org/stlink/pull/1103)) -- Fixed support for STLINK/V1 programmer ([#1045](https://github.com/stlink-org/stlink/pull/1045), [#1105](https://github.com/stlink-org/stlink/pull/1105)) - Fixed STM32WB55 reading DEBUG IDCODE from the wrong address ([#1100](https://github.com/stlink-org/stlink/pull/1100), [#1101](https://github.com/stlink-org/stlink/pull/1101)) # v1.6.1 @@ -179,8 +183,8 @@ Major changes and added features: Updates and fixes: -- Fixed `unkown chip id`, piped output and `st-util -v` ([#107](https://github.com/stlink-org/stlink/pull/107), [#665](https://github.com/stlink-org/stlink/pull/665), [#763](https://github.com/stlink-org/stlink/pull/763)) - Fixed an issue with versioning stuck at 1.4.0 for versions cloned with git ([#563](https://github.com/stlink-org/stlink/pull/563), [#762](https://github.com/stlink-org/stlink/pull/762), [#772](https://github.com/stlink-org/stlink/pull/772)) +- Fixed `unkown chip id`, piped output and `st-util -v` ([#665](https://github.com/stlink-org/stlink/pull/665), [#763](https://github.com/stlink-org/stlink/pull/763)) - Updated STM32F3xx chip ID that covers a few different devices ([#685](https://github.com/stlink-org/stlink/pull/685), [#758](https://github.com/stlink-org/stlink/pull/758)) - Made udev rules and modprobe conf installation optional ([#741](https://github.com/stlink-org/stlink/pull/741)) - Fixed case when `__FILE__` doesn't contain either `/` nor `\\` ([#745](https://github.com/stlink-org/stlink/pull/745)) @@ -385,12 +389,14 @@ Updates and fixes: - Fixed STM32F2xx memory map (Nicolas Schodet) - Memory map for STM32F42xxx and STM32F43xxx devices (Craig Lilley) - Stm32l0x flash loader (Robin Kreis) -- Use libusb synchronous api ([#194](https://github.com/stlink-org/stlink/pull/194), [#374](https://github.com/stlink-org/stlink/pull/374)) +- Modified determination of erased byte pattern when flashing ([#193](https://github.com/stlink-org/stlink/pull/193), [#377](https://github.com/stlink-org/stlink/pull/377)) +- Use libusb synchronous api ([#194](https://github.com/stlink-org/stlink/pull/194), [#225](https://github.com/stlink-org/stlink/pull/225), [#374](https://github.com/stlink-org/stlink/pull/374)) - Fixed segfault when programmer is already busy and `NULL` pointers are in the list ([#256](https://github.com/stlink-org/stlink/pull/256), [#394](https://github.com/stlink-org/stlink/pull/394)) - Fixed issue where "unknown chip id!" was seen every other time ([#352](https://github.com/stlink-org/stlink/pull/352), [#367](https://github.com/stlink-org/stlink/pull/367), [#381](https://github.com/stlink-org/stlink/pull/381)) - Send F4 memory-map and features for STM32F429 ([#188](https://github.com/stlink-org/stlink/pull/188), [#196](https://github.com/stlink-org/stlink/pull/196), [#250](https://github.com/stlink-org/stlink/pull/250), [#251](https://github.com/stlink-org/stlink/pull/251)) (Release v1.1.0) - Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/stlink-org/stlink/pull/218), [#288](https://github.com/stlink-org/stlink/pull/288)) (Release v1.1.0) - Reset: st-flash does not work when CPU is in sleep mode ([#62](https://github.com/stlink-org/stlink/pull/62)) (Release v1.0.0) +- Ensure USB device search succeeds if the matched device is at index 0 ([#126](https://github.com/stlink-org/stlink/pull/126), [#151](https://github.com/stlink-org/stlink/pull/151)) (Release v1.0.0) - Corrected flash size register address for STM32F2 devices ([#278](https://github.com/stlink-org/stlink/pull/278)) (Release v1.0.0) Chip support added for: diff --git a/SECURITY.md b/SECURITY.md new file mode 100644 index 000000000..caa2740db --- /dev/null +++ b/SECURITY.md @@ -0,0 +1,20 @@ +# Security Policy + +## Supported Versions + +The following versions of the stlink toolset are currently being supported.
      As this is a development toolset, please note that bugfixes will only be applied to the latest version. + +| Version | Supported | +| ------- | ------------------ | +| develop | :white_check_mark: | +| 1.6.x | :white_check_mark: | +| 1.5.x | :x: | +| 1.4.0 | :x: | +| 1.3.x | :x: | +| 1.2.0 | :x: | +| 1.1.0 | :x: | +| 1.0.0 | :x: | + +## Reporting a Vulnerability + +Detected vulnerabilities in the toolset should be reported by opening a regular bugreport issue. diff --git a/doc/tutorial.md b/doc/tutorial.md index d4cf89ce2..8b1220747 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -2,15 +2,16 @@ ## Available tools and options -| Option | Tool | Description | Available
      since | -| --------------------- | ------------------------------------ | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------------------- | -| --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k
      for the STM32F103C8T6 to assume 128k of flash being present. This option accepts
      decimal (128k), octal 0200k, or hex 0x80k values. Leaving the multiplier out is
      equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k"
      or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | -| --freq=n[k][m] | st-flash | The frequency of the SWD/JTAG interface can be specified, to override the default
      1800 kHz configuration. This option solely accepts decimal values (5K or 1.8M) with
      the unit `Hz` being left out. Valid frequencies are: `5K, 15K, 25K, 50K, 100K,`
      `125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | -| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at
      the end of binary file. This may cause some garbage data left after a flash operation.
      This option was enabled by default in earlier releases. | v1.6.1 | -| --reset | st-flash | Trigger a reset both before and after flashing. The default use the hardware reset
      through `NRST` pin. The software system reset is used if the hardware reset failed
      (`NRST` pin not connected). | v1.0.0 | -| --connect-under-reset | st-flash | Connect under reset. Option makes it possible to connect to the device before code
      executing. This is useful when the target contains a code that go device to sleep,
      disables of debug pins or other special code. | v1.6.1 | -| --version | st-info
      st-flash
      st-util | Print version information. | | -| --help | st-flash
      st-util | Print list of available commands. _(To be added to this table.)_ | | +| Option | Tool | Description | Available
      since | +| --------------------- | ---------------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | -------------------- | +| --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
      to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
      Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
      "k" or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | +| --freq=n[k][m] | st-flash | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
      This option solely accepts decimal values (5K or 1.8M) with the unit `Hz` being left out. Valid frequencies are:
      `5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | +| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
      This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | +| --reset | st-flash | Trigger a reset both before and after flashing. The default uses the hardware reset through `NRST` pin.
      The software reset is used if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | +| --connect-under-reset | st-flash | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
      when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | +| --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | +| --version | st-info
      st-flash
      st-util | Print version information. | v1.3.0 | +| --help | st-flash
      st-util | Print list of available commands. | | ### st-flash: Checksum for binary files @@ -102,17 +103,52 @@ Check your hardware and try to identify what you have in front of you before ass Please let us know, if you come across any further websites or tutorials that help to identify STM32 fake chips so we can list them here to help others. ---- +### c) Appearance of the warning message `WARN src/common.c: unknown chip id!` + +The chip ID is the main identifier for STM32 MCU and their specific type and provides primary information on flash and SRAM architecture. +This so called `DBGMCU_IDCODE` register is allocated either at memory address `0xE0042000` or `0x40015800`. + +A failure of chip identification results in the error `WARN src/common.c: unknown chip id!`. +There are different variants of this message that refer to different issues: + +- `unknown chip id! 0` --> _currently unknown_ +- `unknown chip id! 0x1a` --> _currently unknown_ +- `unknown chip id! 0x001f` --> _currently unknown_ +- `unknown chip id! 0x3e8` --> _currently unknown_ +- `unknown chip id! 0xa05f0000` --> _currently unknown_ +- `unknown chip id! 0x3748` --> A target chip / board cannot be detected. + 1. No target is connected --> In this case `st-info --probe` displays `chip id 0x0748` with STLINK/V2 and `chip id 0x03e8` with STLINK-V3. + 2. The chip is connected but has gone into an undefined state of operation where the SWD pins are unresponsive. --> Try to use `--connect-under-reset` while pressing the reset button on the target board. + 3. A firmware-issue prevents the programmer from normal operation. --> Ensure that your programmer runs the latest firmware version and consider to upgrade any older version by using the official firmware upgrade tool provided by STMicroelectronics. +- `unknown chip id! 0xe0042000` --> The memory register holding the information on the chip ID could not be read. The following problems may lead to this case: + 1. This problem is caused by the SWDIO and SWCLK being configured for other purpose (GPIO, etc) other than Serial Wire configuration or Jtag --> A possible solution to this is to short the `BOOT0` pin with `VDD` (1) and to reset the chip / board by the execuing `st-flash erase` in order to return the MCU back to normal operation. Afterwards `BOOT0` should be set back to `GND` (0). + 2. There is a hardware defect in the connection between the MCU and the used programmer (solder points, cables, connectors). + +### d) Understanding hardware and software reset functionality for `st-flash` and reset-related device recovery + +Typically a reset signal is sent via the reset pin `NRST`. Using `st-flash` for flashing results in the following behaviour: -( Content below is currently unrevised and may be outdated as of Apr 2020. ) +- without the `--reset` option: `st-flash write` results in one reset signal on the `NRST` line +- with the `--reset` option: `st-flash write --reset` results in two subsequent reset signals on the `NRST` line -# Using STM32 discovery kits with open source tools +Depending on the used programmer the hardware reset line is not always connected. +This is especially the case for low-cost STLINK/V2 clone programmers. +Here the SWD connector consists of only 4 pins: `VCC`, `SWCLK`, `GND` and `SWDATA`. -This guide details the use of STMicroelectronics STM32 discovery kits in an open source environment. +When the physical reset line `NRST` is not connected, a reset is initiated by software via `SWD_SWDIO/JTAG_TMS` (software reset). +Just as mentioned above, flashing is possible here eiher with and without the `--reset` option. -## Installing a GNU toolchain +Configuring the STM32 pin `JTAG_TMS/SWD_SWDIO` as an output now also prevents the SWD interface from flashing and resetting the device. +In consequence this constellation typically requires a _hard reset_ to allow for the ST-Link/V2 programmer to reconnect to the target at all. -Any toolchain supporting the cortex m3 should do. +As soon as the device is in DFU mode, the `JTAG_TMS/SWD_SWDIO` pin is left in the default state with all JTAG pins available. +Here flashing of the device is now possible with and without the `--reset` option. + +The debug command `(gdb) monitor jtag_reset` sends a _hard reset_ signal via the `NRST` pin to reset the device and allows for flashing it (again). + +--- + +( Content below is currently unrevised and may be outdated as of Mar 2021. ) ## Using the GDB server @@ -201,7 +237,6 @@ Of course, you can use this instead of the gdb server, if you prefer. Just remember to use the “.bin” image, rather than the .elf file. ``` - # write blink.bin into FLASH $> [sudo] ./st-flash write fancy_blink.bin 0x08000000 ``` diff --git a/doc/version_support.md b/doc/version_support.md index 1edf2e19c..5d2cdd375 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -14,10 +14,10 @@ Thus no user interaction regarding libusb is necessary. ### Apple macOS -| Package Repository | libusb
      version | cmake
      version | gtk-3
      version | Supported macOS versions | -| ------------------ | ------------------- | ------------------ | ------------------ | -------------------------------------- | -| homebrew | 1.0.23 | 3.17.0 | 3.24.18
      gtk+3 | 10.12 (Sierra)- 10.15 (Catalina) | -| MacPorts | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | 10.6 (Snow Leopard) - 10.15 (Catalina) | +| Package Repository | libusb
      version | cmake
      version | gtk-3
      version | Supported macOS versions | +| ------------------ | ------------------- | ------------------ | ------------------ | ------------------------ | +| homebrew | 1.0.23 | 3.17.0 | 3.24.18
      gtk+3 | 10.9 - 10.15 | +| MacPorts | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | 10.4 - 10.15 | NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 are required. From b387c93ee007a2bde37daba8198a2108ec9704e5 Mon Sep 17 00:00:00 2001 From: anton Date: Thu, 25 Mar 2021 19:25:33 +0500 Subject: [PATCH 1133/1435] Extended set of command line arguments st-info: added --freq, --hot-plug and --connect-under-reset to probe st-util: added --freq --- doc/tutorial.md | 7 ++-- src/st-flash/flash.c | 11 +++--- src/st-flash/flash.h | 2 +- src/st-flash/flash_opts.c | 57 ++++++++---------------------- src/st-info/info.c | 74 +++++++++++++++++++++------------------ src/st-util/gdb-server.c | 36 ++++++++++++------- src/stlink-lib/helper.c | 14 ++++++++ src/stlink-lib/helper.h | 2 ++ src/stlink-lib/usb.c | 19 +++++----- src/stlink-lib/usb.h | 12 +++++-- 10 files changed, 122 insertions(+), 112 deletions(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index 8b1220747..2403590ac 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -5,10 +5,11 @@ | Option | Tool | Description | Available
      since | | --------------------- | ---------------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | -------------------- | | --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
      to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
      Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
      "k" or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | -| --freq=n[k][m] | st-flash | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
      This option solely accepts decimal values (5K or 1.8M) with the unit `Hz` being left out. Valid frequencies are:
      `5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K(1.2M), 1800K(1.8M), 4000K(4M)`. | v1.6.1 | +| --freq=n[k][m] | st-info
      st-flash
      st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
      This option solely accepts decimal values (5K or 1.8M) with the unit `Hz` being left out. Valid frequencies are:
      `5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K, 1800K, 4000K(4M)`. | v1.6.1 | | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
      This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | | --reset | st-flash | Trigger a reset both before and after flashing. The default uses the hardware reset through `NRST` pin.
      The software reset is used if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | -| --connect-under-reset | st-flash | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
      when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | +| --connect-under-reset | st-info
      st-flash | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
      when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | +| --hot-plug | st-info
      st-util | Connect to the target without reset. | v1.6.2 | | --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | | --version | st-info
      st-flash
      st-util | Print version information. | v1.3.0 | | --help | st-flash
      st-util | Print list of available commands. | | @@ -262,7 +263,7 @@ There are a few options: -m, --multi Set gdb server to extended mode. st-util will continue listening for connections after disconnect. - -n, --no-reset + -n, --no-reset, --hot-plug Do not reset board on connection. ``` diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 447daa158..5a226d57b 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -26,9 +26,9 @@ static void cleanup(int signum) { } static void usage(void) { - puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); - puts("command line: ./st-flash [--debug] [--connect-under-reset] [--freq=] [--serial ] erase"); - puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); + puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); + puts("command line: ./st-flash [--debug] [--connect-under-reset] [--freq=] [--serial ] erase"); + puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); puts(" , and : Use hex format."); puts(" : Use decimal, octal or hex (prefix 0xXXX) format, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); puts(" : Can be 'binary' (default) or 'ihex', although must be specified for binary format only."); @@ -52,6 +52,7 @@ int main(int ac, char** av) { uint8_t * mem = NULL; o.size = 0; + o.connect = CONNECT_NORMAL; if (flash_get_opts(&o, ac - 1, av + 1) == -1) { printf("invalid command line\n"); @@ -61,9 +62,7 @@ int main(int ac, char** av) { printf("st-flash %s\n", STLINK_VERSION); - sl = stlink_open_usb(o.log_level, - o.connect_under_reset ? 2 : 1, - (char *)o.serial, o.freq); + sl = stlink_open_usb(o.log_level, o.connect, (char *)o.serial, o.freq); if (sl == NULL) { return(-1); } diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index 8a5c2ad29..cd08db70f 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -26,7 +26,7 @@ struct flash_opts { size_t flash_size; // --flash=n[k][m] int opt; // enable empty tail data drop optimization int freq; // --freq=n[k][m] frequency of JTAG/SWD - bool connect_under_reset; + enum connect_type connect; }; #define FLASH_OPTS_INITIALIZER {0, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 7d846e425..63774ea25 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -2,6 +2,8 @@ #include #include +#include + #include "flash.h" static bool starts_with(const char * str, const char * prefix) { @@ -140,50 +142,21 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { return(-1); } - } else if (strcmp(av[0], "--freq") == 0 || starts_with(av[0], "--freq=")) { - const char* freq; - - if (strcmp(av[0], "--freq") == 0) { - ac--; - av++; - - if (ac < 1) { - return(-1); - } + } else if (strcmp(av[0], "--freq") == 0) { + ac--; + av++; - freq = av[0]; - } else { - freq = av[0] + strlen("--freq="); + if (ac < 1) { + return(-1); } - if (strcmp(freq, "5K") == 0 || strcmp(freq, "5k") == 0) { - o->freq = 5; - } else if (strcmp(freq, "15K") == 0 || strcmp(freq, "15k") == 0) { - o->freq = 15; - } else if (strcmp(freq, "25K") == 0 || strcmp(freq, "25k") == 0) { - o->freq = 25; - } else if (strcmp(freq, "50K") == 0 || strcmp(freq, "50k") == 0) { - o->freq = 50; - } else if (strcmp(freq, "100K") == 0 || strcmp(freq, "100k") == 0) { - o->freq = 100; - } else if (strcmp(freq, "125K") == 0 || strcmp(freq, "125k") == 0) { - o->freq = 125; - } else if (strcmp(freq, "240K") == 0 || strcmp(freq, "240k") == 0) { - o->freq = 240; - } else if (strcmp(freq, "480K") == 0 || strcmp(freq, "480k") == 0) { - o->freq = 480; - } else if (strcmp(freq, "950K") == 0 || strcmp(freq, "950k") == 0) { - o->freq = 950; - } else if (strcmp(freq, "1200K") == 0 || strcmp(freq, "1200k") == 0 || - strcmp(freq, "1.2M") == 0 || strcmp(freq, "1.2m") == 0) { - o->freq = 1200; - } else if (strcmp(freq, "1800K") == 0 || strcmp(freq, "1800k") == 0 || - strcmp(freq, "1.8M") == 0 || strcmp(freq, "1.8m") == 0) { - o->freq = 1800; - } else if (strcmp(freq, "4000K") == 0 || strcmp(freq, "4000k") == 0 || - strcmp(freq, "4M") == 0 || strcmp(freq, "4m") == 0) { - o->freq = 4000; - } else { + o->freq = arg_parse_freq(av[0]); + if (o->freq < 0) { + return(-1); + } + } else if (starts_with(av[0], "--freq=")) { + o->freq = arg_parse_freq(av[0] + strlen("--freq=")); + if (o->freq < 0) { return(-1); } } else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { @@ -219,7 +192,7 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { o->flash_size = (size_t)flash_size; } } else if (strcmp(av[0], "--connect-under-reset") == 0) { - o->connect_under_reset = true; + o->connect = CONNECT_UNDER_RESET; } else { break; // non-option found diff --git a/src/st-info/info.c b/src/st-info/info.c index c1ac86373..a6b4e85c6 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -4,16 +4,17 @@ #include #include +#include static void usage(void) { puts("st-info --version"); - puts("st-info --probe"); + puts("st-info --probe [--connect-under-reset] [--hot-plug] [--freq=]"); puts("st-info --serial"); - puts("st-info --flash [--connect-under-reset]"); - puts("st-info --pagesize [--connect-under-reset]"); - puts("st-info --sram [--connect-under-reset]"); - puts("st-info --chipid [--connect-under-reset]"); - puts("st-info --descr [--connect-under-reset]"); + puts("st-info --flash [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --pagesize [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --sram [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --chipid [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --descr [--connect-under-reset] [--hot-plug] [--freq=]"); } static void stlink_print_version(stlink_t *sl) { @@ -45,11 +46,11 @@ static void stlink_print_info(stlink_t *sl) { if (params) { printf(" descr: %s\n", params->description); } } -static void stlink_probe(void) { +static void stlink_probe(enum connect_type connect, int freq) { stlink_t **stdevs; size_t size; - size = stlink_probe_usb(&stdevs); + size = stlink_probe_usb(&stdevs, connect, freq); printf("Found %u stlink programmers\n", (unsigned int)size); @@ -61,44 +62,47 @@ static void stlink_probe(void) { stlink_probe_usb_free(&stdevs, size); } -static stlink_t *stlink_open_first(bool under_reset) { +static int print_data(int ac, char **av) { stlink_t* sl = NULL; - sl = stlink_v1_open(0, 1); + enum connect_type connect = CONNECT_NORMAL; + int freq = 0; - if (sl == NULL) { - if (under_reset) { - sl = stlink_open_usb(0, 2, NULL, 0); - } else { - sl = stlink_open_usb(0, 1, NULL, 0); - } + if (strcmp(av[1], "--version") == 0) { + printf("v%s\n", STLINK_VERSION); + return(0); } - return(sl); -} + for (int i=2; i= 0) { continue; } + } + } else if (strncmp(av[i], "--freq=", 7) == 0) { + freq = arg_parse_freq(av[i] + 7); + if (freq >= 0) { continue; } + } -static int print_data(int ac, char **av) { - stlink_t* sl = NULL; - bool under_reset = false; + printf("Incorrect argument: %s\n\n", av[i]); + usage(); + return(-1); + } // probe needs all devices unclaimed if (strcmp(av[1], "--probe") == 0) { - stlink_probe(); - return(0); - } else if (strcmp(av[1], "--version") == 0) { - printf("v%s\n", STLINK_VERSION); + stlink_probe(connect, freq); return(0); } - if (ac == 3) { - if (strcmp(av[2], "--connect-under-reset") == 0) { - under_reset = true; - } else { - usage(); - return(-1); - } - } - - sl = stlink_open_first(under_reset); + // open first st-link device + sl = stlink_open_usb(0, connect, NULL, freq); if (sl == NULL) { return(-1); } diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index d7ca6d008..3dc3073e5 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -26,6 +26,7 @@ #endif #include +#include #include #include "gdb-remote.h" #include "gdb-server.h" @@ -63,7 +64,8 @@ typedef struct _st_state_t { int logging_level; int listen_port; int persistent; - int reset; + enum connect_type connect_mode; + int freq; } st_state_t; @@ -100,9 +102,9 @@ static stlink_t* do_connect(st_state_t *st) { stlink_t *sl = NULL; if (serial_specified) { - sl = stlink_open_usb(st->logging_level, st->reset, serialnumber, 0); + sl = stlink_open_usb(st->logging_level, st->connect_mode, serialnumber, st->freq); } else { - sl = stlink_open_usb(st->logging_level, st->reset, NULL, 0); + sl = stlink_open_usb(st->logging_level, st->connect_mode, NULL, st->freq); } return(sl); @@ -116,6 +118,8 @@ int parse_options(int argc, char** argv, st_state_t *st) { {"listen_port", required_argument, NULL, 'p'}, {"multi", optional_argument, NULL, 'm'}, {"no-reset", optional_argument, NULL, 'n'}, + {"hot-plug", optional_argument, NULL, 'n'}, + {"freq", optional_argument, NULL, 'F'}, {"version", no_argument, NULL, 'V'}, {"semihosting", no_argument, NULL, SEMIHOSTING_OPTION}, {"serial", required_argument, NULL, SERIAL_OPTION}, @@ -126,16 +130,16 @@ int parse_options(int argc, char** argv, st_state_t *st) { " -V, --version\t\tPrint the version\n" " -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n" " -v, --verbose\t\tSpecify generally verbose logging\n" - "\t\t\tChoose what version of stlink to use, (defaults to 2)\n" - " -1, --stlinkv1\tForce stlink version 1\n" " -p 4242, --listen_port=1234\n" "\t\t\tSet the gdb server listen port. " "(default port: " STRINGIFY(DEFAULT_GDB_LISTEN_PORT) ")\n" " -m, --multi\n" "\t\t\tSet gdb server to extended mode.\n" "\t\t\tst-util will continue listening for connections after disconnect.\n" - " -n, --no-reset\n" + " -n, --no-reset, --hot-plug\n" "\t\t\tDo not reset board on connection.\n" + " -F 1800K, --freq=1M\n" + "\t\t\tSet the frequency of the SWD/JTAG interface.\n" " --semihosting\n" "\t\t\tEnable semihosting support.\n" " --serial \n" @@ -160,7 +164,6 @@ int parse_options(int argc, char** argv, st_state_t *st) { exit(EXIT_SUCCESS); break; case 'v': - if (optarg) { st->logging_level = atoi(optarg); } else { @@ -170,7 +173,6 @@ int parse_options(int argc, char** argv, st_state_t *st) { break; case 'p': sscanf(optarg, "%i", &q); - if (q < 0) { fprintf(stderr, "Can't use a negative port to listen on: %d\n", q); exit(EXIT_FAILURE); @@ -178,11 +180,19 @@ int parse_options(int argc, char** argv, st_state_t *st) { st->listen_port = q; break; + case 'm': st->persistent = 1; break; case 'n': - st->reset = 0; + st->connect_mode = CONNECT_HOT_PLUG; + break; + case 'F': + st->freq = arg_parse_freq(optarg); + if (st->freq < 0) { + fprintf(stderr, "Can't parse a frequency: %s\n", optarg); + exit(EXIT_FAILURE); + } break; case 'V': printf("v%s\n", STLINK_VERSION); @@ -217,7 +227,7 @@ int main(int argc, char** argv) { // set defaults ... state.logging_level = DEFAULT_LOGGING_LEVEL; state.listen_port = DEFAULT_GDB_LISTEN_PORT; - state.reset = 1; // by default, reset board + state.connect_mode = CONNECT_NORMAL; // by default, reset board parse_options(argc, argv, &state); printf("st-util\n"); @@ -240,7 +250,7 @@ int main(int argc, char** argv) { signal(SIGSEGV, &cleanup); #endif - if (state.reset) { stlink_reset(sl); } + if (state.connect_mode != CONNECT_HOT_PLUG) { stlink_reset(sl); } DLOG("Chip ID is %#010x, Core ID is %#08x.\n", sl->chip_id, sl->core_id); @@ -1111,7 +1121,7 @@ int serve(stlink_t *sl, st_state_t *st) { stlink_force_debug(sl); - if (st->reset) { stlink_reset(sl); } + if (st->connect_mode != CONNECT_HOT_PLUG) { stlink_reset(sl); } init_code_breakpoints(sl); init_data_watchpoints(sl); @@ -1840,7 +1850,7 @@ int serve(stlink_t *sl, st_state_t *st) { connected_stlink = sl; - if (st->reset) { stlink_reset(sl); } + if (st->connect_mode != CONNECT_HOT_PLUG) { stlink_reset(sl); } ret = stlink_force_debug(sl); diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index 32d9b6c8d..1f0f71b8d 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -1,6 +1,7 @@ #include #include +#include #ifdef STLINK_HAVE_SYS_TIME_H #include @@ -13,3 +14,16 @@ unsigned time_ms() { gettimeofday(&tv, NULL); return (unsigned)(tv.tv_sec * 1000 + tv.tv_usec / 1000); } + +int arg_parse_freq(const char *str) { + char *tail; + int value = (int)strtol(str, &tail, 10); + + if ((tail[0] == 'm' || tail[0] == 'M') && tail[1] == '\0') { + value = value*1000; + } else if (((tail[0] != 'k' && tail[0] != 'K') || tail[1] != '\0') && tail[0] != '\0') { + return -1; + } + + return value; +} diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index 12c2ea2a7..96467377a 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -3,4 +3,6 @@ unsigned time_ms(); +int arg_parse_freq(const char *str); + #endif /* SYS_HELPER_H */ diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 569815665..ce0d672c8 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -46,7 +46,7 @@ static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, u // get abs value for comparison current_diff = (current_diff > 0) ? current_diff : -current_diff; - if ((current_diff < speed_diff) && khz >= map[i]) { + if (current_diff < speed_diff) { speed_diff = current_diff; speed_index = i; } @@ -741,6 +741,8 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { } return(0); + } else if (clk_freq) { + WLOG("ST-Link firmware does not support frequency setup\n"); } return(-1); @@ -1196,7 +1198,7 @@ size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_d return strlen(serial); } -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq) { +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; int ret = -1; @@ -1380,7 +1382,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL DLOG("JTAG/SWD freq set to %d\n", freq); stlink_set_swdclk(sl, freq); - if (reset == 2) { + if (connect == CONNECT_UNDER_RESET) { stlink_jtag_reset(sl, 0); if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } @@ -1390,10 +1392,9 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL usleep(10000); } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } - if (reset == 1) { + if (connect == CONNECT_NORMAL) { if ( sl->version.stlink_v > 1) { stlink_jtag_reset(sl, 2); } stlink_reset(sl); @@ -1420,7 +1421,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STL return(NULL); } -static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { +static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int freq) { stlink_t **_sldevs; libusb_device *dev; int i = 0; @@ -1489,7 +1490,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { if (serial_len != STLINK_SERIAL_LENGTH) { continue; } - stlink_t *sl = stlink_open_usb(0, 1, serial, 0); + stlink_t *sl = stlink_open_usb(0, connect, serial, freq); if (!sl) { ELOG("Failed to open USB device %#06x:%#06x\n", desc.idVendor, desc.idProduct); @@ -1504,7 +1505,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[]) { return(slcur); } -size_t stlink_probe_usb(stlink_t **stdevs[]) { +size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq) { libusb_device **devs; stlink_t **sldevs; @@ -1520,7 +1521,7 @@ size_t stlink_probe_usb(stlink_t **stdevs[]) { if (cnt < 0) { return(0); } - slcnt = stlink_probe_usb_devs(devs, &sldevs); + slcnt = stlink_probe_usb_devs(devs, &sldevs, connect, freq); libusb_free_device_list(devs, 1); libusb_exit(NULL); diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 512370a10..f48ef225d 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -48,6 +48,12 @@ extern "C" { #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 +enum connect_type { + CONNECT_HOT_PLUG = 0, + CONNECT_NORMAL = 1, + CONNECT_UNDER_RESET = 2, +}; + struct stlink_libusb { libusb_context* libusb_ctx; libusb_device_handle* usb_handle; @@ -62,13 +68,13 @@ struct stlink_libusb { /** * Open a stlink * @param verbose Verbosity loglevel - * @param reset Reset stlink programmer + * @param connect Type of connect to target * @param serial Serial number to search for, when NULL the first stlink found is opened (binary format) * @retval NULL Error while opening the stlink * @retval !NULL Stlink found and ready to use */ -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, int reset, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq); -size_t stlink_probe_usb(stlink_t **stdevs[]); +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq); +size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); #ifdef __cplusplus From 5b8ee390eec6e83bfb67c026248f0cffc9e84ab0 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 27 Mar 2021 12:27:43 +0200 Subject: [PATCH 1134/1435] remove abort() from lib. related to #634 --- src/common.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/src/common.c b/src/common.c index 8fae08a09..72150953b 100644 --- a/src/common.c +++ b/src/common.c @@ -980,7 +980,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { sr_reg = (bank==BANK_1)?FLASH_H7_SR1:FLASH_H7_SR2; } else { - ELOG("unsupported flash method, abort"); + ELOG("unsupported flash method, abort\n"); return(-1); } @@ -1010,7 +1010,7 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; } else { - ELOG("unsupported flash method, abort"); + ELOG("unsupported flash method, abort\n"); return(-1); } @@ -1617,9 +1617,8 @@ int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); if (len % 4 != 0) { - fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", - len % 4); - abort(); + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return(-1); } return(sl->backend->write_mem32(sl, addr, len)); @@ -1629,9 +1628,8 @@ int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_read_mem32 ***\n"); if (len % 4 != 0) { // !!! never ever: fw gives just wrong values - fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", - len % 4); - abort(); + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return(-1); } return(sl->backend->read_mem32(sl, addr, len)); @@ -1641,9 +1639,8 @@ int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem8 ***\n"); if (len > 0x40) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour - fprintf(stderr, "Error: Data length > 64: +%d byte.\n", - len); - abort(); + ELOG("Data length > 64: +%d byte.\n", len); + return(-1); } return(sl->backend->write_mem8(sl, addr, len)); From 0b7221076a9b66cfb9647e4f06d55d66229e0799 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 27 Mar 2021 11:41:09 +0100 Subject: [PATCH 1135/1435] General Project Update - Updated CHANGELOG.md - [doc] Update for GD32F303VGT6 in device list - [doc] Updated tutorial.md > Added refs for unknown chip id! 0 > Minor update for tool option table --- CHANGELOG.md | 8 ++++---- doc/devices_boards.md | 6 +++--- doc/tutorial.md | 8 +++++--- 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index e3f8e13b5..ee46901e7 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,7 +2,7 @@ # v1.6.2 -Release date: (planned H1/2021) +Release date: (planned Q2/2021) Features: @@ -21,7 +21,7 @@ Features: Updates & changes: -- [doc] Added tutorial section on unknown chip id error ([#107](https://github.com/stlink-org/stlink/pull/107), [#568](https://github.com/stlink-org/stlink/pull/568), +- [doc] Added tutorial section on unknown chip id error (commit [#229c721](https://github.com/stlink-org/stlink/commit/229c721189587760db5509c59b3c02e93e7035c8), [#107](https://github.com/stlink-org/stlink/pull/107), [#568](https://github.com/stlink-org/stlink/pull/568)) - [doc] Updated documentation on target resetting ([#261](https://github.com/stlink-org/stlink/pull/261), [#533](https://github.com/stlink-org/stlink/pull/533), [#1107](https://github.com/stlink-org/stlink/pull/1107)) - [doc] Added note on `(gdb) run` command (commit [#03793d4](https://github.com/stlink-org/stlink/commit/03793d42b6078344a9ef8ad55f1d5d0fc19e486e), [#267](https://github.com/stlink-org/stlink/pull/267)) - [doc] `st-flash --reset` parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) @@ -35,8 +35,9 @@ Updates & changes: Fixes: -- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) +- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) - Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106)) +- Use vl flashloader for all STM32F1 series ([#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) - cmake compile failure with external `CMAKE_MODULE_PATH` set ([#962](https://github.com/stlink-org/stlink/pull/962)) - doc/man: Fixed installation directory ([#970](https://github.com/stlink-org/stlink/pull/970)) @@ -50,7 +51,6 @@ Fixes: - `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027), [#1064](https://github.com/stlink-org/stlink/pull/1064), [#1065](https://github.com/stlink-org/stlink/pull/1065)) - GDB: Fixed problems with target description ([#1013](https://github.com/stlink-org/stlink/pull/1013), [#1088](https://github.com/stlink-org/stlink/pull/1088), [#1109](https://github.com/stlink-org/stlink/pull/1109)) - [doc] Fixed wrong path for `rules.d` folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) -- Use vl flashloader for all STM32F1 series ([#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - Fixed support for STLINK/V1 programmer ([#1045](https://github.com/stlink-org/stlink/pull/1045), [#1105](https://github.com/stlink-org/stlink/pull/1105)) - st-util v1.6.1 does not recognize option --freq (commit [#e576768](https://github.com/stlink-org/stlink/commit/e5767681f14de9851aa970a9299930ca68b2ed92), [#1055](https://github.com/stlink-org/stlink/pull/1055)) - Fixed `gettimeofday` for MSVC ([#1074](https://github.com/stlink-org/stlink/pull/1074)) diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 6396738c4..df4b5ed29 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -109,9 +109,9 @@ Tested boards [incl. STLINK programmers]: **STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3c_CORE_ID)** -| Product-Code | Chip-ID | STLink
      Programmer | Boards | -| ------------ | ------- | ---------------------- | ------------------------------------------------------ | -| GD32F303VGT6 | 0x430 | _N/A_ | STM32F303 clone from GigaDevice GD)
      _unsupported_ | +| Product-Code | Chip-ID | STLINK
      Programmer | Boards | +| ------------ | ------- | ---------------------- | ---------------------------------- | +| GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | **STM32F4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F4_CORE_ID)** diff --git a/doc/tutorial.md b/doc/tutorial.md index 2403590ac..37c29ab6a 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -7,7 +7,7 @@ | --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
      to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
      Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
      "k" or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | | --freq=n[k][m] | st-info
      st-flash
      st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
      This option solely accepts decimal values (5K or 1.8M) with the unit `Hz` being left out. Valid frequencies are:
      `5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K, 1800K, 4000K(4M)`. | v1.6.1 | | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
      This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | -| --reset | st-flash | Trigger a reset both before and after flashing. The default uses the hardware reset through `NRST` pin.
      The software reset is used if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | +| --reset | st-flash | Trigger a reset both before and after flashing. The default uses the hardware reset through `NRST` pin.
      A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | | --connect-under-reset | st-info
      st-flash | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
      when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | | --hot-plug | st-info
      st-util | Connect to the target without reset. | v1.6.2 | | --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | @@ -112,12 +112,14 @@ This so called `DBGMCU_IDCODE` register is allocated either at memory address `0 A failure of chip identification results in the error `WARN src/common.c: unknown chip id!`. There are different variants of this message that refer to different issues: -- `unknown chip id! 0` --> _currently unknown_ +- `unknown chip id! 0` --> Target chip (board) is unknown. + 1. Microcontroller is in stop/standby mode. + 2. The signals `DIO` and `CLK` are reversed on the SWD-Interface. - `unknown chip id! 0x1a` --> _currently unknown_ - `unknown chip id! 0x001f` --> _currently unknown_ - `unknown chip id! 0x3e8` --> _currently unknown_ - `unknown chip id! 0xa05f0000` --> _currently unknown_ -- `unknown chip id! 0x3748` --> A target chip / board cannot be detected. +- `unknown chip id! 0x3748` --> A target chip (board) cannot be detected. 1. No target is connected --> In this case `st-info --probe` displays `chip id 0x0748` with STLINK/V2 and `chip id 0x03e8` with STLINK-V3. 2. The chip is connected but has gone into an undefined state of operation where the SWD pins are unresponsive. --> Try to use `--connect-under-reset` while pressing the reset button on the target board. 3. A firmware-issue prevents the programmer from normal operation. --> Ensure that your programmer runs the latest firmware version and consider to upgrade any older version by using the official firmware upgrade tool provided by STMicroelectronics. From 36434d5785bc752465b47b5b058e33da1df90794 Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 27 Mar 2021 15:54:54 +0500 Subject: [PATCH 1136/1435] Added addition check of connected target --- src/common.c | 58 ++++++++++++++++++-------------------------- src/stlink-lib/reg.h | 12 ++++----- 2 files changed, 29 insertions(+), 41 deletions(-) diff --git a/src/common.c b/src/common.c index b5bb67e9e..f621a4b6d 100644 --- a/src/common.c +++ b/src/common.c @@ -1220,14 +1220,14 @@ int stlink_core_id(stlink_t *sl) { // do not call this procedure directly. int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { int ret; + cortex_m3_cpuid_t cpu_id; - uint32_t cpu_id; - *chip_id = 0; - ret = -1; - - // Read the CPU ID to determine where to read the core id from - if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &cpu_id)) - cpu_id = 0; + // Read the CPU ID to determine where to read the core id + if (stlink_cpu_id(sl, &cpu_id) || + cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) { + ELOG("Can not connect to target. Please use \'connect under reset\' and try again\n"); + return -1; + } /* * the chip_id register in the reference manual have @@ -1235,18 +1235,17 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * */ - uint32_t part_no = STLINK_REG_CM3_CPUID_PARTNO(cpu_id); if ((sl->core_id == STM32H7_CORE_ID || sl->core_id == STM32H7_CORE_ID_JTAG) && - part_no == STLINK_REG_CMx_CPUID_PARTNO_CM7) { + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); - } else if (part_no == STLINK_REG_CMx_CPUID_PARTNO_CM0) { + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0) { // STM32F0 (RM0091, pg914; RM0360, pg713) // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) // STM32G0 (RM0444, pg1367) ret = stlink_read_debug32(sl, 0x40015800, chip_id); - } else if (part_no == STLINK_REG_CMx_CPUID_PARTNO_CM33) { + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) { // STM32L5 (RM0438, pg2157) ret = stlink_read_debug32(sl, 0xE0044000, chip_id); } else /* СM3, СM4, CM7 */ { @@ -1261,9 +1260,16 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { // STM32G4 (RM0440, pg2086) // STM32WB (RM0434, pg1406) ret = stlink_read_debug32(sl, 0xE0042000, chip_id); + } + + if (ret || !(*chip_id)) { + *chip_id = 0; + ELOG("Could not find chip id!\n"); + } else { + *chip_id = (*chip_id) & 0xfff; // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for F2/F4 - if (*chip_id == 0x411 && (cpu_id & 0xfff0) == 0xc240) { + if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) { *chip_id = 0x413; } } @@ -1272,7 +1278,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { } /** - * Cortex m3 tech ref manual, CPUID register description + * Cortex M tech ref manual, CPUID register description * @param sl stlink context * @param cpuid pointer to the result object */ @@ -1305,26 +1311,16 @@ int stlink_load_device_params(stlink_t *sl) { DLOG("Loading device parameters....\n"); const struct stlink_chipid_params *params = NULL; stlink_core_id(sl); - uint32_t chip_id = 0; uint32_t flash_size; - stlink_chip_id(sl, &chip_id); - sl->chip_id = chip_id & 0xfff; - - // Fix chip_id for F4 rev A errata , Read CPU ID, as CoreID is the same for F2/F4 - if (sl->chip_id == 0x411) { - uint32_t cpuid; - stlink_read_debug32(sl, 0xE000ED00, &cpuid); - - if ((cpuid & 0xfff0) == 0xc240) { - sl->chip_id = 0x413; - } + if (stlink_chip_id(sl, &sl->chip_id)) { + return(-1); } params = stlink_chipid_get_params(sl->chip_id); if (params == NULL) { - WLOG("unknown chip id! %#x\n", chip_id); + WLOG("unknown chip id! %#x\n", sl->chip_id); return(-1); } @@ -1390,19 +1386,11 @@ int stlink_load_device_params(stlink_t *sl) { sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; } -#if 0 - // Old code -- REW - ILOG("Device connected is: %s, id %#x\n", params->description, chip_id); - // TODO: make note of variable page size here..... - ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %u bytes\n", - sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, - (unsigned int)sl->flash_pgsz); -#else ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", params->description, (unsigned)(sl->sram_size / 1024), (unsigned)(sl->flash_size / 1024), (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) : (unsigned)(sl->flash_pgsz / 1024), (sl->flash_pgsz < 1024) ? "byte" : "KiB"); -#endif + return(0); } diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 73f608cb6..79570aa34 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -3,12 +3,12 @@ #define STLINK_REG_CM3_CPUID 0xE000ED00 -#define STLINK_REG_CM3_CPUID_PARTNO(cpuid) ((cpuid)&STLINK_REG_CMx_CPUID_PARTNO_MASK) -#define STLINK_REG_CMx_CPUID_PARTNO_MASK 0xFFF0 -#define STLINK_REG_CMx_CPUID_PARTNO_CM0 0xC200 -#define STLINK_REG_CMx_CPUID_PARTNO_CM3 0xC230 -#define STLINK_REG_CMx_CPUID_PARTNO_CM7 0xC270 -#define STLINK_REG_CMx_CPUID_PARTNO_CM33 0xD210 +#define STLINK_REG_CMx_CPUID_PARTNO_CM0 0xC20 +#define STLINK_REG_CMx_CPUID_PARTNO_CM3 0xC23 +#define STLINK_REG_CMx_CPUID_PARTNO_CM4 0xC24 +#define STLINK_REG_CMx_CPUID_PARTNO_CM7 0xC27 +#define STLINK_REG_CMx_CPUID_PARTNO_CM33 0xD21 +#define STLINK_REG_CMx_CPUID_IMPL_ARM 0x41 #define STLINK_REG_CM3_FP_CTRL 0xE0002000 // Flash Patch Control Register From da37fec19ee378d076fae2d615ea7082d99e110e Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 27 Mar 2021 21:12:00 +0500 Subject: [PATCH 1137/1435] Applied missing changes to tests --- tests/flash.c | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-) diff --git a/tests/flash.c b/tests/flash.c index a8d479b2d..132066aba 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -131,17 +131,6 @@ static struct Test tests[] = { .freq = 5, .format = FLASH_FORMAT_BINARY } }, - { "--debug --freq=6k --reset write test.bin 0x80000000", -1, - { .cmd = FLASH_CMD_WRITE, - .serial = { 0 }, - .filename = "test.bin", - .addr = 0x80000000, - .size = 0, - .reset = 1, - .log_level = DEBUG_LOG_LEVEL, - .freq = 6, - .format = FLASH_FORMAT_BINARY } - }, { "--debug --reset read test.bin 0x80000000 1000", 0, { .cmd = FLASH_CMD_READ, .serial = { 0 }, @@ -211,10 +200,10 @@ static struct Test tests[] = { { "--debug --reset --format=binary write test.hex", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset --format=ihex write test.hex 0x80000000", -1, FLASH_OPTS_INITIALIZER }, { "--debug --reset write test.hex sometext", -1, FLASH_OPTS_INITIALIZER }, - { "--serial A1020304 erase sometext", -1, FLASH_OPTS_INITIALIZER }, - { "--serial A1020304 erase", 0, + { "--serial ABCEFF544851717867216044 erase sometext", -1, FLASH_OPTS_INITIALIZER }, + { "--serial ABCEFF544851717867216044 erase", 0, { .cmd = FLASH_CMD_ERASE, - .serial = "\xA1\x02\x03\x04", + .serial = "ABCEFF544851717867216044", .filename = NULL, .addr = 0, .size = 0, @@ -223,9 +212,9 @@ static struct Test tests[] = { .freq = 0, .format = FLASH_FORMAT_BINARY } }, - { "--serial=A1020304 erase", 0, + { "--serial=ABCEFF544851717867216044 erase", 0, { .cmd = FLASH_CMD_ERASE, - .serial = "\xA1\x02\x03\x04", + .serial = "ABCEFF544851717867216044", .filename = NULL, .addr = 0, .size = 0, From 878df31761f449e5846bb841085a320420c77c15 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 27 Mar 2021 17:46:22 +0100 Subject: [PATCH 1138/1435] Updated CI config & issue templates - Initial support for GitHub CI workflows - Cleanup for Travis CI config - Minor fixes for issue templates --- .github/ISSUE_TEMPLATE/bug-report.md | 18 +- .github/ISSUE_TEMPLATE/feature-request.md | 16 +- .github/workflows/c-cpp.yml | 334 +++++++++++++++++++++- .github/workflows/cmake.yml | 46 --- .travis.sh | 13 - .travis.yml | 2 +- README.md | 1 + 7 files changed, 338 insertions(+), 92 deletions(-) delete mode 100644 .github/workflows/cmake.yml diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index 0e22c2ce9..16e0477f0 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -1,8 +1,8 @@ --- name: "Bug Report" about: "Report a bug" -title: "[STM32 device name]: [_$YourTitle_]" -labels: '' +title: "[STM32 device name]: $YourTitle" +labels: "" --- Thank you for giving feedback to the stlink project. @@ -12,18 +12,17 @@ This bug report will be deleted without notice when not enough information is pr - [ ] I made serious effort to avoid creating duplicate or nearly similar issue -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below -and fill out each of the following items appropriate to your specific problem. +In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific problem. -- [ ] Programmer/board type: [enter here] (e.g STLink /V1, /V2, /V2-onboard, /V2-clone, /V3) +- [ ] Programmer/board type: [enter here] (e.g STLINK /V1, /V2, /V2-onboard, /V2-clone, /V3) - [ ] Operating system an version: [enter here] (e.g Linux, macOS, Windows) -- [ ] **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.6.1/git-d0416149) -- [ ] Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) +- [ ] **stlink tools version** and/or git commit hash: [enter here] (e.g v1.6.1/git-d0416149) +- [ ] stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-trace`, `st-util`) - [ ] Target chip (and board, if applicable): [enter here] (e.g STM32F103C8T6 (NUCLEO-F103RB)) -Futher we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: +Further we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: -Commandline-Output: +Commandline output: ``` OUTPUT/ERROR of the commandline tool(s) @@ -33,7 +32,6 @@ Expected/description: `short description of the expected value` - Thank you for your support. The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/feature-request.md b/.github/ISSUE_TEMPLATE/feature-request.md index 3de593aa6..ddeb79357 100644 --- a/.github/ISSUE_TEMPLATE/feature-request.md +++ b/.github/ISSUE_TEMPLATE/feature-request.md @@ -1,7 +1,7 @@ --- name: "Feature Request" about: "Suggest an idea for this project" -title: "[feature] [_$YourTitle_]" +title: "[feature] $YourTitle" labels: code/feature-request --- @@ -12,18 +12,17 @@ This feature request will be deleted without notice when not enough information - [ ] I made serious effort to avoid creating duplicate or nearly similar issue -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below -and fill out each of the following items appropriate to your specific request. +In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific request. -- [ ] Programmer/board type: [enter here] (e.g STLink /V1, /V2, /V2-onboard, /V2-clone, /V3) +- [ ] Programmer/board type: [enter here] (e.g STLINK /V1, /V2, /V2-onboard, /V2-clone, /V3) - [ ] Operating system an version: [enter here] (e.g Linux, macOS, Windows) -- [ ] **Stlink tools version** and/or git commit hash: [enter here] (e.g v1.6.1/git-d0416149) -- [ ] Stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-util`) +- [ ] **stlink tools version** and/or git commit hash: [enter here] (e.g v1.6.1/git-d0416149) +- [ ] stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-trace`, `st-util`) - [ ] Target chip (and board, if applicable): [enter here] (e.g STM32F103C8T6 (NUCLEO-F103RB)) -Futher we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: +Further we kindly ask you to describe the detected problem as detailed as possible and to add debug output if available, by using the following template: -Commandline-Output: +Commandline output: ``` OUTPUT/ERROR of the commandline tool(s) @@ -33,7 +32,6 @@ Expected/description: `short description of the expected value` - Thank you for your support. The stlink project maintainers diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index e211e4e54..c792612c2 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -2,22 +2,330 @@ name: C/C++ CI on: push: - branches: [ testing ] + branches: [develop, testing] pull_request: - branches: [ testing ] + branches: [develop, testing] jobs: - build: + job_linux_1a: + name: ubuntu-20.04 gcc + runs-on: ubuntu-20.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_2a: + name: ubuntu-18.04 gcc + runs-on: ubuntu-18.04 + steps: + - uses: actions/checkout@v2 + - name: install dependencies + run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_3a: + name: ubuntu-16.04 gcc + runs-on: ubuntu-16.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_1b: + name: ubuntu-20.04 clang + runs-on: ubuntu-20.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_2b: + name: ubuntu-18.04 clang + runs-on: ubuntu-18.04 + steps: + - uses: actions/checkout@v2 + - name: install dependencies + run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_3b: + name: ubuntu-16.04 clang + runs-on: ubuntu-16.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install clang libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_1c: + name: ubuntu-20.04 gcc 32-bit + runs-on: ubuntu-20.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_2c: + name: ubuntu-18.04 gcc 32-bit + runs-on: ubuntu-18.04 + steps: + - uses: actions/checkout@v2 + - name: install dependencies + run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_3c: + name: ubuntu-16.04 gcc 32-bit + runs-on: ubuntu-16.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + job_linux_4: + name: ubuntu-20.04 mingw64 + runs-on: ubuntu-20.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm mingw-w64 + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean + + # job_macos_1a: + # name: macos-11.0 gcc + # runs-on: macos-11.0 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: brew install gcc libusb gtk+3 + # - name: make debug + # run: make debug + # - name: make test + # run: make test + # - name: make release + # run: make release + # - name: make install + # run: make install + # - name: make package + # run: make package + # - name: make uninstall + # run: make uninstall + # - name: make clean + # run: make clean + + job_macos_2a: + name: macos-10.15 gcc + runs-on: macos-10.15 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: brew install gcc libusb gtk+3 + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean - runs-on: ubuntu-latest + # job_macos_1b: + # name: macos-11.0 clang + # runs-on: macos-11.0 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: brew install llvm libusb gtk+3 + # - name: make debug + # run: make debug + # - name: make test + # run: make test + # - name: make release + # run: make release + # - name: make install + # run: make install + # - name: make package + # run: make package + # - name: make uninstall + # run: make uninstall + # - name: make clean + # run: make clean + job_macos_2b: + name: macos-10.15 clang + runs-on: macos-10.15 steps: - - uses: actions/checkout@v2 - - name: configure - run: ./configure - - name: make - run: make - - name: make check - run: make check - - name: make distcheck - run: make distcheck + - uses: actions/checkout@v2 + - name: Install dependencies + run: brew install llvm libusb gtk+3 + - name: make debug + run: make debug + - name: make test + run: make test + - name: make release + run: make release + - name: make install + run: make install + - name: make package + run: make package + - name: make uninstall + run: make uninstall + - name: make clean + run: make clean diff --git a/.github/workflows/cmake.yml b/.github/workflows/cmake.yml deleted file mode 100644 index 005915e6e..000000000 --- a/.github/workflows/cmake.yml +++ /dev/null @@ -1,46 +0,0 @@ -name: CMake - -on: [push] - -env: - # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.) - BUILD_TYPE: Release - -jobs: - build: - # The CMake configure and build commands are platform agnostic and should work equally - # well on Windows or Mac. You can convert this to a matrix build if you need - # cross-platform coverage. - # See: https://docs.github.com/en/free-pro-team@latest/actions/learn-github-actions/managing-complex-workflows#using-a-build-matrix - runs-on: ubuntu-latest - - steps: - - uses: actions/checkout@v2 - - - name: Create Build Environment - # Some projects don't allow in-source building, so create a separate build directory - # We'll use this as our working directory for all subsequent commands - run: cmake -E make_directory ${{github.workspace}}/build - - - name: Configure CMake - # Use a bash shell so we can use the same syntax for environment variable - # access regardless of the host operating system - shell: bash - working-directory: ${{github.workspace}}/build - # Note the current convention is to use the -S and -B options here to specify source - # and build directories, but this is only available with CMake 3.13 and higher. - # The CMake binaries on the Github Actions machines are (as of this writing) 3.12 - run: cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE - - - name: Build - working-directory: ${{github.workspace}}/build - shell: bash - # Execute the build. You can specify a specific target with "--target " - run: cmake --build . --config $BUILD_TYPE - - - name: Test - working-directory: ${{github.workspace}}/build - shell: bash - # Execute tests defined by the CMake configuration. - # See https://cmake.org/cmake/help/latest/manual/ctest.1.html for more detail - run: ctest -C $BUILD_TYPE diff --git a/.travis.sh b/.travis.sh index cc0958bf5..7683af001 100755 --- a/.travis.sh +++ b/.travis.sh @@ -11,61 +11,48 @@ DIR=$PWD if [ "$TRAVIS_JOB_NAME" == "linux-mingw" ]; then echo "--> Building Release for Windows (x86-64) ..." mkdir -p build-mingw && cd build-mingw - echo "-DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR" cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && rm -rf build-mingw && cd - echo "--> Building Release for Windows (i686) ..." mkdir -p build-mingw && cd build-mingw - echo "-DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR" cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && rm -rf build-mingw && cd - elif [ "$TRAVIS_OS_NAME" == "linux" ]; then sudo apt-get update -qq || true - sudo apt-get install -qq -y --no-install-recommends libgtk-3-dev echo "--> Building Debug..." mkdir -p build/Debug && cd build/Debug - echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && cd - echo "--> Building Release with package..." mkdir -p build/Release && cd build/Release - echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make package && cd - elif [ "$TRAVIS_OS_NAME" == "osx" ]; then - brew install libusb - echo "--> Building Debug..." mkdir -p build/Debug && cd build/Debug - echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && cd - echo "--> Building Release with package..." mkdir -p build/Release && cd build/Release - echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make package && cd - else # local test-build echo "--> Building Debug..." mkdir -p build/Debug && cd build/Debug - echo "-DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install ../../ make && cd - echo "--> Building Release with package..." mkdir -p build/Release && cd build/Release - echo "-DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install" cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install ../../ make package && cd - fi diff --git a/.travis.yml b/.travis.yml index 5d2e5fbdf..e866cc6ab 100644 --- a/.travis.yml +++ b/.travis.yml @@ -146,7 +146,7 @@ jobs: addons: homebrew: packages: - - clang + - llvm - libusb - gtk+3 diff --git a/README.md b/README.md index 7ddc78005..aafba5988 100644 --- a/README.md +++ b/README.md @@ -6,6 +6,7 @@ ![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.6.1/develop) ![GitHub activity](https://img.shields.io/github/commit-activity/m/stlink-org/stlink) ![GitHub contributors](https://img.shields.io/github/contributors/stlink-org/stlink) +[![C/C++ CI](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml/badge.svg?branch=testing)](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml) [![Linux Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=linux&label=linux)](https://travis-ci.org/stlink-org/stlink) [![macOS Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=osx&label=osx)](https://travis-ci.org/stlink-org/stlink) From a5a4a687c42045a139d9950036c5adddaa317bf6 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 27 Mar 2021 21:01:31 +0100 Subject: [PATCH 1139/1435] Updated config for GitHub Actions CI workflow --- .github/workflows/c-cpp.yml | 228 ++++++++++++++++++------------------ 1 file changed, 114 insertions(+), 114 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index c792612c2..b42d001af 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -2,9 +2,9 @@ name: C/C++ CI on: push: - branches: [develop, testing] + branches: [master, develop, testing] pull_request: - branches: [develop, testing] + branches: [master, develop, testing] jobs: job_linux_1a: @@ -20,14 +20,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_2a: name: ubuntu-18.04 gcc @@ -42,14 +42,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_3a: name: ubuntu-16.04 gcc @@ -64,14 +64,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_1b: name: ubuntu-20.04 clang @@ -86,14 +86,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_2b: name: ubuntu-18.04 clang @@ -108,14 +108,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_3b: name: ubuntu-16.04 clang @@ -130,14 +130,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_1c: name: ubuntu-20.04 gcc 32-bit @@ -157,14 +157,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_2c: name: ubuntu-18.04 gcc 32-bit @@ -184,14 +184,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_3c: name: ubuntu-16.04 gcc 32-bit @@ -211,14 +211,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean job_linux_4: name: ubuntu-20.04 mingw64 @@ -233,14 +233,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean # job_macos_1a: # name: macos-11.0 gcc @@ -255,14 +255,14 @@ jobs: # run: make test # - name: make release # run: make release - # - name: make install - # run: make install - # - name: make package - # run: make package - # - name: make uninstall - # run: make uninstall - # - name: make clean - # run: make clean + # - name: sudo make install + # run: sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall + # - name: sudo make clean + # run: sudo make clean job_macos_2a: name: macos-10.15 gcc @@ -277,14 +277,14 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean # job_macos_1b: # name: macos-11.0 clang @@ -299,14 +299,14 @@ jobs: # run: make test # - name: make release # run: make release - # - name: make install - # run: make install - # - name: make package - # run: make package - # - name: make uninstall - # run: make uninstall - # - name: make clean - # run: make clean + # - name: sudo make install + # run: sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall + # - name: sudo make clean + # run: sudo make clean job_macos_2b: name: macos-10.15 clang @@ -321,11 +321,11 @@ jobs: run: make test - name: make release run: make release - - name: make install - run: make install - - name: make package - run: make package - - name: make uninstall - run: make uninstall - - name: make clean - run: make clean + - name: sudo make install + run: sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall + - name: sudo make clean + run: sudo make clean From face74262f879bba5a330c8326064a383cac2b42 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 28 Mar 2021 00:30:33 +0100 Subject: [PATCH 1140/1435] Updated config for GitHub code scanning alerts --- .github/workflows/codeql-analysis.yml | 60 ++++++++++++++------------- 1 file changed, 31 insertions(+), 29 deletions(-) diff --git a/.github/workflows/codeql-analysis.yml b/.github/workflows/codeql-analysis.yml index 202867cfc..bab5fb048 100644 --- a/.github/workflows/codeql-analysis.yml +++ b/.github/workflows/codeql-analysis.yml @@ -13,12 +13,12 @@ name: "CodeQL" on: push: - branches: [ develop, master ] + branches: [develop, master] pull_request: # The branches below must be a subset of the branches above - branches: [ develop ] + branches: [develop] schedule: - - cron: '23 20 * * 2' + - cron: "23 20 * * 2" jobs: analyze: @@ -28,40 +28,42 @@ jobs: strategy: fail-fast: false matrix: - language: [ 'cpp' ] + language: ["cpp"] # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python' ] # Learn more: # https://docs.github.com/en/free-pro-team@latest/github/finding-security-vulnerabilities-and-errors-in-your-code/configuring-code-scanning#changing-the-languages-that-are-analyzed steps: - - name: Checkout repository - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Checkout repository + uses: actions/checkout@v2 - # Initializes the CodeQL tools for scanning. - - name: Initialize CodeQL - uses: github/codeql-action/init@v1 - with: - languages: ${{ matrix.language }} - # If you wish to specify custom queries, you can do so here or in a config file. - # By default, queries listed here will override any specified in a config file. - # Prefix the list here with "+" to use these queries and those in the config file. - # queries: ./path/to/local/query, your-org/your-repo/queries@main + # Initializes the CodeQL tools for scanning. + - name: Initialize CodeQL + uses: github/codeql-action/init@v1 + with: + languages: ${{ matrix.language }} + # If you wish to specify custom queries, you can do so here or in a config file. + # By default, queries listed here will override any specified in a config file. + # Prefix the list here with "+" to use these queries and those in the config file. + # queries: ./path/to/local/query, your-org/your-repo/queries@main - # Autobuild attempts to build any compiled languages (C/C++, C#, or Java). - # If this step fails, then you should remove it and run the build manually (see below) - - name: Autobuild - uses: github/codeql-action/autobuild@v1 + # Autobuild attempts to build any compiled languages (C/C++, C#, or Java). + # If this step fails, then you should remove it and run the build manually (see below) + - name: Autobuild + uses: github/codeql-action/autobuild@v1 - # ℹ️ Command-line programs to run using the OS shell. - # 📚 https://git.io/JvXDl + # ℹ️ Command-line programs to run using the OS shell. + # 📚 https://git.io/JvXDl - # ✏️ If the Autobuild fails above, remove it and uncomment the following three lines - # and modify them (or add more) to build your code if your project - # uses a compiled language + # ✏️ If the Autobuild fails above, remove it and uncomment the following three lines + # and modify them (or add more) to build your code if your project + # uses a compiled language - #- run: | - # make bootstrap - # make release + #- run: | + # make bootstrap + # make release - - name: Perform CodeQL Analysis - uses: github/codeql-action/analyze@v1 + - name: Perform CodeQL Analysis + uses: github/codeql-action/analyze@v1 From d10a4f8def8189d4b14fad20b25b75bcf010e563 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 28 Mar 2021 00:35:03 +0100 Subject: [PATCH 1141/1435] Updated libusb to v1.0.24 --- cmake/modules/Findlibusb.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index bc613779d..b3e5c7e2b 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -75,7 +75,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) if (NOT LIBUSB_FOUND) # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) @@ -92,7 +92,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download - ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 cf3d38d2ff053ef343d10c0b8b0950c2 + ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 5c944b1c8aa9d43e026a94302d0f8ac4 ) endif () From 0496ecff48b7c122c243c4d449e44ad34e8ecba6 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 2 Apr 2021 16:43:54 +0200 Subject: [PATCH 1142/1435] Updated config for GitHub code scanning alerts --- .github/workflows/codeql-analysis.yml | 8 ++++---- README.md | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/.github/workflows/codeql-analysis.yml b/.github/workflows/codeql-analysis.yml index bab5fb048..26313ecb5 100644 --- a/.github/workflows/codeql-analysis.yml +++ b/.github/workflows/codeql-analysis.yml @@ -13,12 +13,12 @@ name: "CodeQL" on: push: - branches: [develop, master] + branches: [ testing, develop, master ] pull_request: # The branches below must be a subset of the branches above - branches: [develop] + branches: [ testing, develop ] schedule: - - cron: "23 20 * * 2" + - cron: '00 20 * * 1' jobs: analyze: @@ -28,7 +28,7 @@ jobs: strategy: fail-fast: false matrix: - language: ["cpp"] + language: [ 'cpp' ] # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python' ] # Learn more: # https://docs.github.com/en/free-pro-team@latest/github/finding-security-vulnerabilities-and-errors-in-your-code/configuring-code-scanning#changing-the-languages-that-are-analyzed diff --git a/README.md b/README.md index aafba5988..644c3fd86 100644 --- a/README.md +++ b/README.md @@ -6,6 +6,7 @@ ![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.6.1/develop) ![GitHub activity](https://img.shields.io/github/commit-activity/m/stlink-org/stlink) ![GitHub contributors](https://img.shields.io/github/contributors/stlink-org/stlink) +[![CodeQL](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml/badge.svg)](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml) [![C/C++ CI](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml/badge.svg?branch=testing)](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml) [![Linux Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=linux&label=linux)](https://travis-ci.org/stlink-org/stlink) [![macOS Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=osx&label=osx)](https://travis-ci.org/stlink-org/stlink) From eebcb1acc8a29a156276852eb730e961883a9e71 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 2 Apr 2021 18:34:31 +0200 Subject: [PATCH 1143/1435] Revert "Updated libusb to v1.0.24" This reverts commit d10a4f8def8189d4b14fad20b25b75bcf010e563. --- cmake/modules/Findlibusb.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index b3e5c7e2b..bc613779d 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -75,7 +75,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) if (NOT LIBUSB_FOUND) # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) @@ -92,7 +92,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download - ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 5c944b1c8aa9d43e026a94302d0f8ac4 + ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 cf3d38d2ff053ef343d10c0b8b0950c2 ) endif () From 32ba234b305a8fa3ffdd5cd825a72973ad94a512 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 2 Apr 2021 18:36:05 +0200 Subject: [PATCH 1144/1435] Revert "Updated libusb to v1.0.24" This reverts commit d10a4f8def8189d4b14fad20b25b75bcf010e563. --- cmake/modules/Findlibusb.cmake | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index b3e5c7e2b..bc613779d 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -75,7 +75,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) if (NOT LIBUSB_FOUND) # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) @@ -92,7 +92,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download - ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 5c944b1c8aa9d43e026a94302d0f8ac4 + ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 cf3d38d2ff053ef343d10c0b8b0950c2 ) endif () From e0f7552fc1a13990f70da863c5fdaa1f64be649f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 3 Apr 2021 14:53:16 +0200 Subject: [PATCH 1145/1435] Updated CI build configuration - Ensure clean build system for all build targets - Rearranged & renamed build jobs - Completed set of 32-bit & 64-bit builds - Updated notifications for MinGW cross build - Added macOS 10.14 build environment for Travis CI --- .github/workflows/c-cpp.yml | 387 +++++++++++++++++++-------------- .travis.sh | 4 +- .travis.yml | 177 +++++---------- cmake/modules/Findlibusb.cmake | 2 + 4 files changed, 281 insertions(+), 289 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index b42d001af..4769450ae 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -7,95 +7,145 @@ on: branches: [master, develop, testing] jobs: - job_linux_1a: - name: ubuntu-20.04 gcc - runs-on: ubuntu-20.04 + +# Linux + + job_linux_16_04_64_gcc: + name: ubuntu-16.04 gcc + runs-on: ubuntu-16.04 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_2a: - name: ubuntu-18.04 gcc - runs-on: ubuntu-18.04 + job_linux_16_04_32_gcc: + name: ubuntu-16.04 gcc 32-bit + runs-on: ubuntu-16.04 steps: - uses: actions/checkout@v2 - - name: install dependencies - run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Install dependencies + run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_3a: - name: ubuntu-16.04 gcc + job_linux_16_04_64_clang: + name: ubuntu-16.04 clang runs-on: ubuntu-16.04 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_1b: - name: ubuntu-20.04 clang - runs-on: ubuntu-20.04 + job_linux_16_04_32_clang: + name: ubuntu-16.04 clang 32-bit + runs-on: ubuntu-16.04 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_linux_18_04_64_gcc: + name: ubuntu-18.04 gcc + runs-on: ubuntu-18.04 + steps: + - uses: actions/checkout@v2 + - name: install dependencies + run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_2b: + job_linux_18_04_32_gcc: + name: ubuntu-18.04 gcc 32-bit + runs-on: ubuntu-18.04 + steps: + - uses: actions/checkout@v2 + - name: install dependencies + run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_linux_18_04_64_clang: name: ubuntu-18.04 clang runs-on: ubuntu-18.04 steps: @@ -103,43 +153,64 @@ jobs: - name: install dependencies run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_3b: - name: ubuntu-16.04 clang - runs-on: ubuntu-16.04 + job_linux_18_04_32_clang: + name: ubuntu-18.04 clang 32-bit + runs-on: ubuntu-18.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_linux_20_04_64_gcc: + name: ubuntu-20.04 gcc + runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install clang libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_1c: + job_linux_20_04_32_gcc: name: ubuntu-20.04 gcc 32-bit runs-on: ubuntu-20.04 steps: @@ -152,97 +223,106 @@ jobs: CXXFLAGS="$CXXFLAGS -m32" LDFLAGS="$LDFLAGS -m32" - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_2c: - name: ubuntu-18.04 gcc 32-bit - runs-on: ubuntu-18.04 + job_linux_20_04_64_clang: + name: ubuntu-20.04 clang + runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 - - name: install dependencies - run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm - - name: Set compiler flags - run: | - CFLAGS="$CFLAGS -m32" - CXXFLAGS="$CXXFLAGS -m32" - LDFLAGS="$LDFLAGS -m32" + - name: Install dependencies + run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_3c: - name: ubuntu-16.04 gcc 32-bit - runs-on: ubuntu-16.04 + job_linux_20_04_32_clang: + name: ubuntu-20.04 clang 32-bit + runs-on: ubuntu-20.04 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" CXXFLAGS="$CXXFLAGS -m32" LDFLAGS="$LDFLAGS -m32" - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - job_linux_4: - name: ubuntu-20.04 mingw64 - runs-on: ubuntu-20.04 +# macOS + + job_macos_10_15_gcc: + name: macos-10.15 gcc + runs-on: macos-10.15 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: brew install gcc libusb gtk+3 + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_macos_10_15_clang: + name: macos-10.15 clang + runs-on: macos-10.15 steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm mingw-w64 + run: brew install llvm libusb gtk+3 - name: make debug - run: make debug + run: sudo make clean && make debug - name: make test - run: make test + run: sudo make clean && make test - name: make release - run: make release + run: sudo make clean && make release - name: sudo make install - run: sudo make install + run: sudo make clean && sudo make install - name: sudo make package run: sudo make package - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean + run: sudo make uninstall && sudo make clean - # job_macos_1a: + # job_macos_11_gcc: # name: macos-11.0 gcc # runs-on: macos-11.0 # steps: @@ -250,43 +330,19 @@ jobs: # - name: Install dependencies # run: brew install gcc libusb gtk+3 # - name: make debug - # run: make debug + # run: sudo make clean && make debug # - name: make test - # run: make test + # run: sudo make clean && make test # - name: make release - # run: make release + # run: sudo make clean && make release # - name: sudo make install - # run: sudo make install + # run: sudo make clean && sudo make install # - name: sudo make package # run: sudo make package # - name: sudo make uninstall - # run: sudo make uninstall - # - name: sudo make clean - # run: sudo make clean + # run: sudo make uninstall && sudo make clean - job_macos_2a: - name: macos-10.15 gcc - runs-on: macos-10.15 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: brew install gcc libusb gtk+3 - - name: make debug - run: make debug - - name: make test - run: make test - - name: make release - run: make release - - name: sudo make install - run: sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean - - # job_macos_1b: + # job_macos_11_clang: # name: macos-11.0 clang # runs-on: macos-11.0 # steps: @@ -294,38 +350,31 @@ jobs: # - name: Install dependencies # run: brew install llvm libusb gtk+3 # - name: make debug - # run: make debug + # run: sudo make clean && make debug # - name: make test - # run: make test + # run: sudo make clean && make test # - name: make release - # run: make release + # run: sudo make clean && make release # - name: sudo make install - # run: sudo make install + # run: sudo make clean && sudo make install # - name: sudo make package # run: sudo make package # - name: sudo make uninstall - # run: sudo make uninstall - # - name: sudo make clean - # run: sudo make clean + # run: sudo make uninstall && sudo make clean - job_macos_2b: - name: macos-10.15 clang - runs-on: macos-10.15 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: brew install llvm libusb gtk+3 - - name: make debug - run: make debug - - name: make test - run: make test - - name: make release - run: make release - - name: sudo make install - run: sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall - - name: sudo make clean - run: sudo make clean +# Linux MinGW cross compliation + + # job_linux_20_04_cross: + # name: ubuntu-20.04 mingw64 + # runs-on: ubuntu-20.04 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm mingw-w64 + # - name: Building Release for Windows (x86-64) ... + # run: sudo mkdir -p build-mingw && cd build-mingw && sudo cmake \ + # -DCMAKE_SYSTEM_NAME=Windows \ + # -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ + # -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake \ + # -DCMAKE_INSTALL_PREFIX=$PWD/install $PWD && \ + # sudo make && sudo rm -rf build-mingw && cd - diff --git a/.travis.sh b/.travis.sh index 7683af001..de2a42372 100755 --- a/.travis.sh +++ b/.travis.sh @@ -9,13 +9,13 @@ echo "WORK DIR:$DIR" DIR=$PWD if [ "$TRAVIS_JOB_NAME" == "linux-mingw" ]; then - echo "--> Building Release for Windows (x86-64) ..." + echo "--> Building for Windows (x86-64) ..." mkdir -p build-mingw && cd build-mingw cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && rm -rf build-mingw && cd - - echo "--> Building Release for Windows (i686) ..." + echo "--> Building for Windows (i686) ..." mkdir -p build-mingw && cd build-mingw cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR diff --git a/.travis.yml b/.travis.yml index e866cc6ab..2a788fd69 100644 --- a/.travis.yml +++ b/.travis.yml @@ -2,23 +2,7 @@ language: c jobs: include: - ### 64-bit builds on AMD64 ### - - os: linux - dist: xenial - env: BADGE=linux - compiler: gcc-5 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-5", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - - os: linux - dist: bionic - env: BADGE=linux - compiler: gcc-6 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-6", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + ### 64-bit build on AMD64 ### - os: linux dist: focal env: BADGE=linux @@ -27,30 +11,18 @@ jobs: apt: sources: ["ubuntu-toolchain-r-test"] packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - - os: linux - dist: xenial - env: BADGE=linux - compiler: clang - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + + ### 32-bit build on AMD64 ### - os: linux dist: focal env: BADGE=linux - compiler: clang-10 + compiler: gcc-10 addons: apt: sources: ["ubuntu-toolchain-r-test"] - packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; ### cross build on AMD64 ### - os: linux @@ -63,92 +35,61 @@ jobs: sources: ["ubuntu-toolchain-r-test"] packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - - ### 32-bit builds on AMD64 ### - - os: linux - dist: xenial - env: BADGE=linux - compiler: gcc-5 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-5", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: bionic - env: BADGE=linux - compiler: gcc-6 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-6", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: focal - env: BADGE=linux - compiler: gcc-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: xenial - env: BADGE=linux - compiler: clang - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: bionic - env: BADGE=linux - compiler: clang-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - os: linux - dist: focal - env: BADGE=linux - compiler: clang-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["clang-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + - LDFLAGS="$LDFLAGS -NDEBUG"; ### macOS ### - - os: osx - env: BADGE=osx - osx_image: xcode12.2 - name: macOS 10.15.7 - compiler: gcc - addons: - homebrew: - packages: - - gcc - - libusb - - gtk+3 - - os: osx - env: BADGE=osx - osx_image: xcode12.2 - name: macOS 10.15.7 - compiler: clang - addons: - homebrew: - packages: - - llvm - - libusb - - gtk+3 + # - os: osx + # env: BADGE=osx + # osx_image: xcode11.3 + # name: macOS 10.14.6 gcc + # compiler: gcc + # addons: + # homebrew: + # packages: + # - gcc + # - libusb + # - gtk+3 + + # - os: osx + # env: BADGE=osx + # osx_image: xcode11.3 + # name: macOS 10.14.6 gcc 32-bit + # compiler: gcc + # addons: + # homebrew: + # packages: + # - gcc + # - libusb + # - gtk+3 + # before_install: + # - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + + # - os: osx + # env: BADGE=osx + # osx_image: xcode11.3 + # name: macOS 10.14.6 clang + # compiler: clang + # addons: + # homebrew: + # packages: + # - llvm + # - libusb + # - gtk+3 + + # - os: osx + # env: BADGE=osx + # osx_image: xcode11.3 + # name: macOS 10.14.6 clang 32-bit + # compiler: clang + # addons: + # homebrew: + # packages: + # - llvm + # - libusb + # - gtk+3 + # before_install: + # - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; script: - git fetch --tags diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index bc613779d..3082a9509 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -46,8 +46,10 @@ elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-toolchain on Debian # for MinGW/MSYS/MSVC: 64-bit or 32-bit? if (CMAKE_SIZEOF_VOID_P EQUAL 8) + message(STATUS "=== Building for Windows (x86-64) ===") set(ARCH 64) else () + message(STATUS "=== Building for Windowsm (i686) ===") set(ARCH 32) endif () From 7cfab876e73f994c95697ba1b09a0a18c2602597 Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 27 Mar 2021 19:14:37 +0500 Subject: [PATCH 1146/1435] flash_loader: fix typo in the stm32l4 loader --- flashloaders/stm32l4.s | 6 +++--- src/stlink-lib/flash_loader.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/flashloaders/stm32l4.s b/flashloaders/stm32l4.s index 21e926f49..50676be9a 100644 --- a/flashloaders/stm32l4.s +++ b/flashloaders/stm32l4.s @@ -12,7 +12,7 @@ .global copy copy: ldr r12, flash_base - ldr r10, flash_off_bsy + ldr r10, flash_off_sr add r10, r10, r12 loop: @@ -44,5 +44,5 @@ exit: .align 2 flash_base: .word 0x40022000 -flash_off_bsy: - .word 0x12 +flash_off_sr: + .word 0x10 diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 9fa897ccc..20fd6aeed 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -114,7 +114,7 @@ static const uint8_t loader_code_stm32l4[] = { 0x08, 0x3a, 0xf0, 0xdc, 0x00, 0xbe, 0x00, 0xbf, 0x00, 0x20, 0x02, 0x40, - 0x12, 0x00, 0x00, 0x00 + 0x10, 0x00, 0x00, 0x00 }; static const uint8_t loader_code_stm32f7[] = { From c0653f6595e1c564f5a762982ef0c23a00ff3dea Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 27 Mar 2021 19:17:13 +0500 Subject: [PATCH 1147/1435] flash_loader: improved handling errors --- flashloaders/Makefile | 2 +- src/stlink-lib/flash_loader.c | 19 +++++++++++++++++-- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/flashloaders/Makefile b/flashloaders/Makefile index d4ca4d22a..8b01d5293 100644 --- a/flashloaders/Makefile +++ b/flashloaders/Makefile @@ -31,7 +31,7 @@ stm32vl.o: stm32f0.s $(CC) stm32f0.s $(CFLAGS_ARMV7_M) -o stm32vl.o # generic rule for all other ARMv7-M -%.o: *.s +%.o: %.s $(CC) $< $(CFLAGS_ARMV7_M) -o $@ clean: diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 20fd6aeed..aea60f258 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -154,6 +154,7 @@ static const uint8_t loader_code_stm32f7_lv[] = { int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { size_t size = 0; + uint32_t dfsr, cfsr, hfsr; // allocate the loader in SRAM if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { @@ -165,6 +166,20 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { fl->buf_addr = fl->loader_addr + (uint32_t)size; ILOG("Successfully loaded flash loader in sram\n"); + /* Clear Fault Status Register for handling flash loader error */ + if (!stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr) && dfsr) { + ILOG("Clear DFSR\n"); + stlink_write_debug32(sl, STLINK_REG_DFSR, dfsr); + } + if (!stlink_read_debug32(sl, STLINK_REG_CFSR, &cfsr) && cfsr) { + ILOG("Clear CFSR\n"); + stlink_write_debug32(sl, STLINK_REG_CFSR, cfsr); + } + if (!stlink_read_debug32(sl, STLINK_REG_HFSR, &hfsr) && hfsr) { + ILOG("Clear HFSR\n"); + stlink_write_debug32(sl, STLINK_REG_HFSR, hfsr); + } + return(0); } @@ -348,7 +363,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe // check written byte count stlink_read_reg(sl, 2, &rr); - if (rr.r[2] != 0) { + if ((int32_t)rr.r[2] > 0) { ELOG("Write error\n"); goto error; } @@ -364,7 +379,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe stlink_read_all_regs(sl, &rr); WLOG("Loader state: R2 0x%X R15 0x%X\n", rr.r[2], rr.r[15]); - if (dhcsr != 0x3000B || dfsr != 0x3 || cfsr || hfsr) { + if (dhcsr != 0x3000B || dfsr || cfsr || hfsr) { WLOG("MCU state: DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X\n", dhcsr, dfsr, cfsr, hfsr); } From bb96d613dd78f34b112dcbc91af0363315b7d0ff Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 27 Mar 2021 19:37:20 +0500 Subject: [PATCH 1148/1435] Fix is_flash_busy on STM32F1 XL device --- src/common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/common.c b/src/common.c index a17392cf1..640f37799 100644 --- a/src/common.c +++ b/src/common.c @@ -993,7 +993,7 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { unsigned int res; if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || (sl->flash_type == STLINK_FLASH_TYPE_L0)) { sr_busy_shift = FLASH_SR_BSY; } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { @@ -1010,7 +1010,7 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; } else { - ELOG("unsupported flash method, abort\n"); + ELOG("unsupported flash method\n"); return(-1); } From be9c9dec7661f2b9e30fb26b85808bc132ee2c80 Mon Sep 17 00:00:00 2001 From: anton Date: Sun, 28 Mar 2021 21:36:12 +0500 Subject: [PATCH 1149/1435] flash_loader: fixed check of the flash loader results --- src/stlink-lib/flash_loader.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index aea60f258..992f0a827 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -363,7 +363,13 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe // check written byte count stlink_read_reg(sl, 2, &rr); - if ((int32_t)rr.r[2] > 0) { + /* The chunk size for loading is not rounded. The flash loader + * subtracts the size of the written block (1-8 bytes) from + * the remaining size each time. A negative value may mean that + * several bytes garbage has been written due to the unaligned + * firmware size. + */ + if ((int32_t)rr.r[2] > 0 || (int32_t)rr.r[2] < -7) { ELOG("Write error\n"); goto error; } From d0d52690d680d603264b90f6328e54aec4be793c Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 29 Mar 2021 19:51:55 +0500 Subject: [PATCH 1150/1435] Added error checking in the FLASH_SR register after write and erase operations --- src/common.c | 214 +++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 175 insertions(+), 39 deletions(-) diff --git a/src/common.c b/src/common.c index 640f37799..7ebbb8d11 100644 --- a/src/common.c +++ b/src/common.c @@ -159,6 +159,9 @@ // G0/G4 FLASH status register #define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) +#define STM32Gx_FLASH_SR_PROGERR (3) +#define STM32Gx_FLASH_SR_WRPERR (4) +#define STM32Gx_FLASH_SR_PGAERR (5) #define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ #define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ @@ -188,11 +191,15 @@ #define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) // WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* FLASH_CR Start */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* FLASH_CR Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ +#define STM32WB_FLASH_CR_STRT (16) /* Start */ +#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ +#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ // WB Flash status register. -#define STM32WB_FLASH_SR_BSY (16) /* FLASH_SR Busy */ +#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ +#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ +#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ +#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ +#define STM32WB_FLASH_SR_BSY (16) /* Busy */ // 32L4 register base is at FLASH_REGS_ADDR (0x40022000) #define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) @@ -201,8 +208,11 @@ #define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) #define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) +#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ +#define STM32L4_FLASH_SR_PROGERR 3 +#define STM32L4_FLASH_SR_WRPERR 4 +#define STM32L4_FLASH_SR_PGAERR 5 #define STM32L4_FLASH_SR_BSY 16 -#define STM32L4_FLASH_SR_ERRMASK 0x3f8 /* SR [9:3] */ #define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ #define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ @@ -234,7 +244,10 @@ #define STM32L0_FLASH_OPTLOCK (2) #define STM32L0_FLASH_OBL_LAUNCH (18) -#define STM32L0_FLASH_SR_ERROR_MASK 0x00003F00 +#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 +#define STM32L0_FLASH_SR_WRPERR 8 +#define STM32L0_FLASH_SR_PGAERR 9 +#define STM32L0_FLASH_SR_NOTZEROERR 16 #define FLASH_ACR_OFF ((uint32_t) 0x00) #define FLASH_PECR_OFF ((uint32_t) 0x04) @@ -287,7 +300,10 @@ #define FLASH_F4_CR_SER 1 #define FLASH_F4_CR_SNB 3 #define FLASH_F4_CR_SNB_MASK 0xf8 -#define FLASH_F4_SR_BSY 16 +#define FLASH_F4_SR_ERROR_MASK 0x000000F0 +#define FLASH_F4_SR_PGAERR 5 +#define FLASH_F4_SR_WRPERR 4 +#define FLASH_F4_SR_BSY 16 // STM32F2 #define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) @@ -980,7 +996,7 @@ static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { sr_reg = (bank==BANK_1)?FLASH_H7_SR1:FLASH_H7_SR2; } else { - ELOG("unsupported flash method, abort\n"); + ELOG("method 'read_flash_sr' is unsupported\n"); return(-1); } @@ -988,6 +1004,35 @@ static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { return(res); } +static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { + uint32_t sr_reg; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + sr_reg = (bank==BANK_1)?FLASH_SR:FLASH_SR2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + sr_reg = STM32Gx_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_reg = (bank==BANK_1)?FLASH_H7_SR1:FLASH_H7_SR2; + } else { + ELOG("method 'write_flash_sr' is unsupported\n"); + return(-1); + } + + return stlink_write_debug32(sl, sr_reg, val); +} + static inline unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; unsigned int res; @@ -1010,7 +1055,7 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; } else { - ELOG("unsupported flash method\n"); + ELOG("method 'is_flash_busy' is unsupported\n"); return(-1); } @@ -1048,43 +1093,120 @@ static void wait_flash_busy_progress(stlink_t *sl) { fprintf(stdout, "\n"); } +static void clear_flash_error(stlink_t *sl) +{ + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_F4: + write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_F7: + write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_L0: + write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_L4: + write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_H7: + write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); + } + break; + case STLINK_FLASH_TYPE_WB: + write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); + break; + default: + break; + } +} + static int check_flash_error(stlink_t *sl) { uint32_t res = 0; + uint32_t WRPERR, PROGERR, PGAERR; + + WRPERR = PROGERR = PGAERR = 0; switch (sl->flash_type) { case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_SR_WRPRT_ERR); + PROGERR = (1 << FLASH_SR_PG_ERR); + break; + case STLINK_FLASH_TYPE_F4: + res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F4_SR_WRPERR); + PGAERR = (1 << FLASH_F4_SR_PGAERR); break; case STLINK_FLASH_TYPE_F7: res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F7_SR_WRP_ERR); + PROGERR = (1 << FLASH_F7_SR_PGP_ERR); break; case STLINK_FLASH_TYPE_G0: case STLINK_FLASH_TYPE_G4: res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); + PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); + PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); break; case STLINK_FLASH_TYPE_L0: res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); + PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_L4: + res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); + PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); break; case STLINK_FLASH_TYPE_H7: res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; } - if (res) { - // Clear errors - stlink_write_debug32(sl, FLASH_H7_CCR1, res); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - stlink_write_debug32(sl, FLASH_H7_CCR2, res); - } - } + WRPERR = (1 << FLASH_H7_SR_WRPERR); + break; + case STLINK_FLASH_TYPE_WB: + res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); + PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); + PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); break; default: break; } if (res) { - ELOG("Flash programming error : %#010x\n", res); + if (WRPERR && (WRPERR&res)==WRPERR) { + ELOG("Flash memory is write protected\n"); + res &= ~WRPERR; + } else if (PROGERR && (PROGERR&res)==PROGERR) { + ELOG("Flash memory contains a non-erased value\n"); + res &= ~PROGERR; + } else if (PGAERR && (PGAERR&res)==PGAERR) { + ELOG("Invalid flash address\n"); + res &= ~PGAERR; + } + + if (res) { + ELOG("Flash programming error: %#010x\n", res); + } return(-1); } @@ -2372,12 +2494,14 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { * @return 0 on success -ve on failure */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { + // wait for ongoing op to finish + wait_flash_busy(sl); + // clear flash IO errors + clear_flash_error(sl); + if (sl->flash_type == STLINK_FLASH_TYPE_F4 || sl->flash_type == STLINK_FLASH_TYPE_F7 || sl->flash_type == STLINK_FLASH_TYPE_L4) { - // wait for ongoing op to finish - wait_flash_busy(sl); - // unlock if locked unlock_flash_if(sl); @@ -2498,7 +2622,6 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { sl->flash_type == STLINK_FLASH_TYPE_G0 || sl->flash_type == STLINK_FLASH_TYPE_G4) { uint32_t val; - wait_flash_busy(sl); // wait for any ongoing Flash operation to finish unlock_flash_if(sl); set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit @@ -2535,7 +2658,6 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE)?BANK_1:BANK_2; - wait_flash_busy(sl); unlock_flash_if(sl); clear_flash_cr_pg(sl, bank); // clear the pg bit set_flash_cr_per(sl, bank); // set the page erase bit @@ -2545,7 +2667,6 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { lock_flash(sl); } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE)?BANK_1:BANK_2; - wait_flash_busy(sl); // wait for ongoing op to finish unlock_flash_if(sl); // unlock if locked uint32_t sector = calculate_H7_sectornum(sl, flashaddr, bank);// calculate the actual page from the address write_flash_cr_snb(sl, sector, bank); // select the page to erase @@ -2557,8 +2678,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { return(-1); } - // TODO: verify the erased page - return(0); + return check_flash_error(sl); } int stlink_erase_flash_mass(stlink_t *sl) { @@ -2574,7 +2694,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { // addr must be an addr inside the page stm32_addr_t addr = (stm32_addr_t)sl->flash_base + i * (stm32_addr_t)sl->flash_pgsz; - if (stlink_erase_flash_page(sl, addr) == -1) { + if (stlink_erase_flash_page(sl, addr)) { WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); return(-1); } @@ -2586,6 +2706,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { fprintf(stdout, "\n"); } else { wait_flash_busy(sl); + clear_flash_error(sl); unlock_flash_if(sl); if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_id != STLINK_CHIPID_STM32_H7AX) { @@ -2596,7 +2717,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { } } - set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit + set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit set_flash_cr_strt(sl, BANK_1); // start erase operation, reset by hw with busy bit if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || @@ -2606,7 +2727,6 @@ int stlink_erase_flash_mass(stlink_t *sl) { } wait_flash_busy_progress(sl); - err = check_flash_error(sl); lock_flash(sl); // reset the mass erase bit @@ -2616,7 +2736,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { set_flash_cr_mer(sl, 0, BANK_2); } - // TODO: verify the erased memory + err = check_flash_error(sl); } return(err); @@ -2751,6 +2871,11 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_MASKINTS); + // wait for ongoing op to finish + wait_flash_busy(sl); + // Clear errors + clear_flash_error(sl); + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_F7) || (sl->flash_type == STLINK_FLASH_TYPE_L4)) { @@ -2801,7 +2926,6 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { sl->flash_type == STLINK_FLASH_TYPE_G4) { ILOG("Starting Flash write for WB/G0/G4\n"); - wait_flash_busy(sl); unlock_flash_if(sl); // unlock flash if necessary set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { @@ -2882,6 +3006,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr size_t size = len - off > buf_size ? buf_size : len - off; if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (unsigned)(addr + off)); + check_flash_error(sl); return(-1); } @@ -2977,6 +3102,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (unsigned)(addr + off)); + check_flash_error(sl); return(-1); } @@ -3015,7 +3141,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr return(-1); } - return(0); + return check_flash_error(sl); } int stlink_flashloader_stop(stlink_t *sl) { @@ -3405,6 +3531,8 @@ static int stlink_write_option_bytes_gx( (void)len; uint32_t data; + clear_flash_error(sl); + write_uint32((unsigned char*)&data, *(uint32_t*)(base)); WLOG("Writing option bytes %#10x to %#10x\n", data, addr); stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); @@ -3441,7 +3569,7 @@ static int stlink_write_option_bytes_l0( int ret = 0; // Clear errors - stlink_write_debug32(sl, flash_base + FLASH_SR_OFF, STM32L0_FLASH_REGS_ADDR); + clear_flash_error(sl); while (len != 0) { write_uint32((unsigned char*)&data, *(uint32_t*)(base)); // write options bytes @@ -3480,6 +3608,9 @@ static int stlink_write_option_bytes_l4( (void)addr; (void)len; + // Clear errors + clear_flash_error(sl); + // write options bytes uint32_t data; write_uint32((unsigned char*)&data, *(uint32_t*)(base)); @@ -3516,6 +3647,9 @@ static int stlink_write_option_bytes_f4( (void)addr; (void)len; + // Clear errors + clear_flash_error(sl); + write_uint32((unsigned char*)&option_byte, *(uint32_t*)(base)); // write option byte, ensuring we dont lock opt, and set strt bit @@ -3539,8 +3673,8 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t* base, stm32_addr_ uint32_t option_byte; int ret = 0; - //(void) addr; - //(void) len; + // Clear errors + clear_flash_error(sl); ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t*) (base), addr); write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); @@ -3999,9 +4133,10 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option_control_register) { int ret = 0; + // Clear errors + clear_flash_error(sl); + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", option_control_register, FLASH_F7_OPTCR); - //write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); - //ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); /* write option byte, ensuring we dont lock opt, and set strt bit */ stlink_write_debug32(sl, FLASH_F7_OPTCR, (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); @@ -4010,7 +4145,7 @@ static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option ret = check_flash_error(sl); if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, FLASH_F7_OPTCR1); + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, FLASH_F7_OPTCR); return ret; } @@ -4024,9 +4159,10 @@ static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t option_control_register1) { int ret = 0; + // Clear errors + clear_flash_error(sl); + ILOG("Asked to write option control register 1 %#010x to %#010x.\n", option_control_register1, FLASH_F7_OPTCR1); - //write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); - //ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); /* write option byte, ensuring we dont lock opt, and set strt bit */ uint32_t current_control_register_value; From 817c8ad436eada97294fa93e6cc8e57fb1be9504 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 29 Mar 2021 20:31:57 +0500 Subject: [PATCH 1151/1435] flash_loader: fixed setup PG flag in F0/VL flash loaders, code cleared --- flashloaders/stm32f0.s | 6 ++-- src/common.c | 58 ++++++++++------------------------- src/stlink-lib/flash_loader.c | 18 +++++------ 3 files changed, 26 insertions(+), 56 deletions(-) diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s index e2a4b0f00..23f1c43fe 100644 --- a/flashloaders/stm32f0.s +++ b/flashloaders/stm32f0.s @@ -35,10 +35,8 @@ copy: ldr r5, flash_off_sr add r5, r5, r7 - # FLASH_CR |= 0x01 (set PG) - ldr r7, =0x1 - ldr r4, [r6] - orrs r4, r4, r7 + # FLASH_CR = 0x01 (set PG) + ldr r4, =0x1 str r4, [r6] loop: diff --git a/src/common.c b/src/common.c index 7ebbb8d11..8585ff881 100644 --- a/src/common.c +++ b/src/common.c @@ -394,13 +394,21 @@ uint16_t read_uint16(const unsigned char *c, const int pt) { static uint32_t get_stm32l0_flash_base(stlink_t *sl) { switch (sl->chip_id) { + case STLINK_CHIPID_STM32_L0: + case STLINK_CHIPID_STM32_L0_CAT5: + case STLINK_CHIPID_STM32_L0_CAT2: + case STLINK_CHIPID_STM32_L011: + return(STM32L0_FLASH_REGS_ADDR); + case STLINK_CHIPID_STM32_L1_CAT2: case STLINK_CHIPID_STM32_L1_MEDIUM: case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS: case STLINK_CHIPID_STM32_L1_HIGH: return(STM32L1_FLASH_REGS_ADDR); + default: - return(STM32L0_FLASH_REGS_ADDR); + WLOG("Flash base use default L0 address"); + return(STM32L0_FLASH_REGS_ADDR); } } @@ -2549,16 +2557,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { uint32_t val; - uint32_t flash_regs_base; - - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - } + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); // check if the locks are set stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -2592,15 +2591,6 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // set pecr.{erase,prog} val |= (1 << 9) | (1 << 3); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); -#if 0 - /* Wait for sr.busy to be cleared - * MP: Test shows that busy bit is not set here. Perhaps, PM0062 is wrong - * and we do not need to wait here for clearing the busy bit. - */ - do { - stlink_read_debug32(sl, STM32L_FLASH_SR, &val) - } while ((val & (1 << 0)) != 0); -#endif // write 0 to the first word of the page to be erased stlink_write_debug32(sl, flashaddr, 0); @@ -2610,9 +2600,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { * Test shows that a few iterations is performed in the following loop * before busy bit is cleared. */ - do - stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - while ((val & (1 << 0)) != 0); + wait_flash_busy(sl); // reset lock bits stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -2652,7 +2640,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit - wait_flash_busy(sl); // wait for the 'busy' bit to clear + wait_flash_busy(sl); // wait for the 'busy' bit to clear clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit lock_flash(sl); } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || @@ -2664,6 +2652,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { write_flash_ar(sl, flashaddr, bank); // select the page to erase set_flash_cr_strt(sl, bank); // start erase operation, reset by hw with busy bit wait_flash_busy(sl); + clear_flash_cr_per(sl, bank); // clear the page erase bit lock_flash(sl); } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE)?BANK_1:BANK_2; @@ -2796,18 +2785,9 @@ int stm32l1_write_half_pages( unsigned int count; unsigned int num_half_pages = len / pagesize; uint32_t val; - uint32_t flash_regs_base; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); flash_loader_t fl; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - } - ILOG("Starting Half page flash write for STM32L core id\n"); /* Flash loader initialisation */ @@ -2824,9 +2804,7 @@ int stm32l1_write_half_pages( val |= (1 << FLASH_L1_PROG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - do { - stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - } while ((val & (1 << 0)) != 0); + wait_flash_busy(sl); for (count = 0; count < num_half_pages; count++) { if (stlink_flash_loader_run( @@ -2845,9 +2823,7 @@ int stm32l1_write_half_pages( fflush(stdout); } - do { - stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - } while ((val & (1 << 0)) != 0); + wait_flash_busy(sl); } stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -3096,8 +3072,6 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr // unlock and set programming mode unlock_flash_if(sl); - if (sl->flash_type != STLINK_FLASH_TYPE_F1_XL) { set_flash_cr_pg(sl, BANK_1); } - DLOG("Finished unlocking flash, running loader!\n"); if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 992f0a827..e3b1a12ea 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -14,11 +14,10 @@ /* flashloaders/stm32f0.s -- compiled with thumb2 */ static const uint8_t loader_code_stm32vl[] = { 0x00, 0xbf, 0x00, 0xbf, - 0x0f, 0x4f, 0x1f, 0x44, - 0x0f, 0x4e, 0x3e, 0x44, - 0x0f, 0x4d, 0x3d, 0x44, - 0x4f, 0xf0, 0x01, 0x07, - 0x34, 0x68, 0x3c, 0x43, + 0x0e, 0x4f, 0x1f, 0x44, + 0x0e, 0x4e, 0x3e, 0x44, + 0x0e, 0x4d, 0x3d, 0x44, + 0x4f, 0xf0, 0x01, 0x04, 0x34, 0x60, 0x04, 0x88, 0x0c, 0x80, 0x02, 0x30, 0x02, 0x31, 0x4f, 0xf0, @@ -38,11 +37,10 @@ static const uint8_t loader_code_stm32vl[] = { /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ static const uint8_t loader_code_stm32f0[] = { 0xc0, 0x46, 0xc0, 0x46, - 0x0d, 0x4f, 0x1f, 0x44, - 0x0d, 0x4e, 0x3e, 0x44, - 0x0d, 0x4d, 0x3d, 0x44, - 0x0d, 0x4f, 0x34, 0x68, - 0x3c, 0x43, 0x34, 0x60, + 0x0c, 0x4f, 0x1f, 0x44, + 0x0c, 0x4e, 0x3e, 0x44, + 0x0c, 0x4d, 0x3d, 0x44, + 0x0c, 0x4c, 0x34, 0x60, 0x04, 0x88, 0x0c, 0x80, 0x02, 0x30, 0x02, 0x31, 0x09, 0x4f, 0x2c, 0x68, From b62cdcfab70e362b34b5875ad86b31c9e6fd6c73 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 29 Mar 2021 20:40:22 +0500 Subject: [PATCH 1152/1435] Added disabling the IWDG and WWDG in halt state --- src/common.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 8585ff881..26a3b3859 100644 --- a/src/common.c +++ b/src/common.c @@ -362,6 +362,25 @@ #define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) #define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) +#define STM32F0_DBGMCU_CR 0xE0042004 +#define STM32F0_DBGMCU_CR_IWDG_STOP 8 +#define STM32F0_DBGMCU_CR_WWDG_STOP 9 + +#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 +#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 +#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 + +#define STM32L0_DBGMCU_APB1_FZ 0x40015808 +#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 +#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 + +#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 +#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 + +#define STM32WB_DBGMCU_APB1FZR1 0xE004203C +#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 +#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 + #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 @@ -1221,6 +1240,50 @@ static int check_flash_error(stlink_t *sl) return(0); } +static void stop_wdg_in_debug(stlink_t *sl) { + uint32_t dbgmcu_cr; + uint32_t set; + uint32_t value; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + case STLINK_FLASH_TYPE_G4: + dbgmcu_cr = STM32F0_DBGMCU_CR; + set = (1< halted state. int stlink_force_debug(stlink_t *sl) { DLOG("*** stlink_force_debug_mode ***\n"); - return(sl->backend->force_debug(sl)); + int res = sl->backend->force_debug(sl); + // Stop the watchdogs in the halted state for suppress target reboot + stop_wdg_in_debug(sl); + return(res); } int stlink_exit_dfu_mode(stlink_t *sl) { From b0192478c8262476ead421890b1550d6a7b72ecc Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 29 Mar 2021 20:56:03 +0500 Subject: [PATCH 1153/1435] Added disabling the DMA channels --- inc/stlink.h | 3 +- src/common.c | 83 +++++++++++++++++++++++++++++++++++++++- src/st-flash/flash.c | 13 ------- src/st-util/gdb-server.c | 2 +- src/stlink-gui/gui.c | 12 ------ 5 files changed, 84 insertions(+), 29 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 7bb1bc51e..61b8472f1 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -137,6 +137,7 @@ typedef uint32_t stm32_addr_t; typedef struct flash_loader { stm32_addr_t loader_addr; // loader sram addr stm32_addr_t buf_addr; // buffer sram address + uint32_t rcc_dma_bkp; // backup RCC DMA enable state } flash_loader_t; typedef struct _cortex_m3_cpuid_ { @@ -297,7 +298,7 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_flashloader_stop(stlink_t *sl); +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); #include #include diff --git a/src/common.c b/src/common.c index 26a3b3859..60d7ff145 100644 --- a/src/common.c +++ b/src/common.c @@ -381,6 +381,27 @@ #define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 #define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 +#define STM32F1_RCC_AHBENR 0x40021014 +#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32F4_RCC_AHB1ENR 0x40023830 +#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN + +#define STM32G0_RCC_AHBENR 0x40021038 +#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32G4_RCC_AHB1ENR 0x40021048 +#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32L0_RCC_AHBENR 0x40021030 +#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN + +#define STM32H7_RCC_AHB1ENR 0x58024538 +#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32WB_RCC_AHB1ENR 0x58000048 +#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 @@ -1284,6 +1305,58 @@ static void stop_wdg_in_debug(stlink_t *sl) { } } +static void set_dma_state(stlink_t *sl, flash_loader_t* fl, int bckpRstr) { + uint32_t rcc, rcc_dma_mask, value; + + rcc = rcc_dma_mask = value = 0; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + rcc = STM32F1_RCC_AHBENR; + rcc_dma_mask = STM32F1_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_F4: + case STLINK_FLASH_TYPE_F7: + rcc = STM32F4_RCC_AHB1ENR; + rcc_dma_mask = STM32F4_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_G0: + rcc = STM32G0_RCC_AHBENR; + rcc_dma_mask = STM32G0_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_G4: + case STLINK_FLASH_TYPE_L4: + rcc = STM32G4_RCC_AHB1ENR; + rcc_dma_mask = STM32G4_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_L0: + rcc = STM32L0_RCC_AHBENR; + rcc_dma_mask = STM32L0_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_H7: + rcc = STM32H7_RCC_AHB1ENR; + rcc_dma_mask = STM32H7_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_WB: + rcc = STM32WB_RCC_AHB1ENR; + rcc_dma_mask = STM32WB_RCC_DMAEN; + break; + default: + return; + } + + if (!stlink_read_debug32(sl, rcc, &value)) { + if (bckpRstr) { + value = (value&(~rcc_dma_mask)) | fl->rcc_dma_bkp; + } else { + fl->rcc_dma_bkp = value&rcc_dma_mask; + value &= ~rcc_dma_mask; + } + stlink_write_debug32(sl, rcc, value); + } +} + static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { stlink_write_debug32(sl, (bank==BANK_1)?FLASH_AR:FLASH_AR2, n); } @@ -2913,6 +2986,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_MASKINTS); + // disable DMA + set_dma_state(sl, fl, 0); + // wait for ongoing op to finish wait_flash_busy(sl); // Clear errors @@ -3184,7 +3260,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr return check_flash_error(sl); } -int stlink_flashloader_stop(stlink_t *sl) { +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { uint32_t dhcsr; if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || @@ -3224,6 +3300,9 @@ int stlink_flashloader_stop(stlink_t *sl) { (dhcsr&(~STLINK_REG_DHCSR_C_MASKINTS))); } + // restore DMA state + set_dma_state(sl, fl, 1); + return(0); } @@ -3286,7 +3365,7 @@ int stlink_write_flash( ret = stlink_flashloader_write(sl, &fl, addr, base, len); if (ret) return ret; - ret = stlink_flashloader_stop(sl); + ret = stlink_flashloader_stop(sl, &fl); if (ret) return ret; diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 5a226d57b..e870e116c 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -112,19 +112,6 @@ int main(int ac, char** av) { } } - // disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 - if (sl->chip_id == STLINK_CHIPID_STM32_F4) { - memset(sl->q_buf, 0, 4); - - for (int i = 0; i < 8; i++) { - stlink_write_mem32(sl, 0x40026000 + 0x10 + 0x18 * i, 4); - stlink_write_mem32(sl, 0x40026400 + 0x10 + 0x18 * i, 4); - stlink_write_mem32(sl, 0x40026000 + 0x24 + 0x18 * i, 4); - stlink_write_mem32(sl, 0x40026400 + 0x24 + 0x18 * i, 4); - - } - } - // core must be halted to use RAM based flashloaders if (stlink_force_debug(sl)) { printf("Failed to halt the core\n"); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 3dc3073e5..8d63d9ee0 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -908,7 +908,7 @@ static int flash_go(stlink_t *sl) { } } - stlink_flashloader_stop(sl); + stlink_flashloader_stop(sl, &fl); stlink_soft_reset(sl, 1 /* halt on reset */); error = 0; diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index ed38fcc7c..d264cf9a5 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -514,18 +514,6 @@ static void connect_button_cb(GtkWidget *widget, gpointer data) { stlink_enter_swd_mode(gui->sl); } - // disable DMA - Set All DMA CCR Registers to zero. - AKS 1/7/2013 - if (gui->sl->chip_id == STLINK_CHIPID_STM32_F4) { - memset(gui->sl->q_buf, 0, 4); - - for (i = 0; i < 8; i++) { - stlink_write_mem32(gui->sl, 0x40026000 + 0x10 + 0x18 * i, 4); - stlink_write_mem32(gui->sl, 0x40026400 + 0x10 + 0x18 * i, 4); - stlink_write_mem32(gui->sl, 0x40026000 + 0x24 + 0x18 * i, 4); - stlink_write_mem32(gui->sl, 0x40026400 + 0x24 + 0x18 * i, 4); - } - } - stlink_gui_set_connected(gui); } From c793ca348fab43711cc3d24e8b9956ba90ca03d3 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 29 Mar 2021 22:19:48 +0500 Subject: [PATCH 1154/1435] Fixed GUI compilation --- src/stlink-gui/gui.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index d264cf9a5..03e999b7f 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -489,7 +489,6 @@ static void stlink_gui_set_connected(STlinkGUI *gui) { static void connect_button_cb(GtkWidget *widget, gpointer data) { STlinkGUI *gui; - gint i; (void)widget; gui = STLINK_GUI(data); From 4334ce48b2c03497a6d415f8982fdb986409398c Mon Sep 17 00:00:00 2001 From: anton Date: Sun, 4 Apr 2021 11:45:21 +0500 Subject: [PATCH 1155/1435] flash_loader: added reset of IWDG If IWDG is enabled by hardware, then IWDG cannot be disabled by software --- inc/stlink.h | 1 + src/stlink-lib/flash_loader.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/inc/stlink.h b/inc/stlink.h index 61b8472f1..855e5126d 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -138,6 +138,7 @@ typedef struct flash_loader { stm32_addr_t loader_addr; // loader sram addr stm32_addr_t buf_addr; // buffer sram address uint32_t rcc_dma_bkp; // backup RCC DMA enable state + uint32_t iwdg_kr; // IWDG key register address } flash_loader_t; typedef struct _cortex_m3_cpuid_ { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index e3b1a12ea..80262cf07 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -9,6 +9,11 @@ #define FLASH_REGS_BANK2_OFS 0x40 #define FLASH_BANK2_START_ADDR 0x08080000 +#define STM32F0_WDG_KR 0x40003000 +#define STM32H7_WDG_KR 0x58004800 + +#define STM32F0_WDG_KR_KEY_RELOAD 0xAAAA + /* DO NOT MODIFY SOURCECODE DIRECTLY, EDIT ASSEMBLY FILES INSTEAD */ /* flashloaders/stm32f0.s -- compiled with thumb2 */ @@ -164,6 +169,13 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { fl->buf_addr = fl->loader_addr + (uint32_t)size; ILOG("Successfully loaded flash loader in sram\n"); + // set address of IWDG key register for reset it + if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + fl->iwdg_kr = STM32H7_WDG_KR; + } else { + fl->iwdg_kr = STM32F0_WDG_KR; + } + /* Clear Fault Status Register for handling flash loader error */ if (!stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr) && dfsr) { ILOG("Clear DFSR\n"); @@ -329,6 +341,11 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe // only used on VL/F1_XL, but harmless for others stlink_write_reg(sl, fl->loader_addr, 15); // pc register + /* Reset IWDG */ + if (fl->iwdg_kr) { + stlink_write_debug32(sl, fl->iwdg_kr, STM32F0_WDG_KR_KEY_RELOAD); + } + /* Run loader */ stlink_run(sl); From a3b1247d141592bd87fdb1f0aeec879e1b061eef Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 4 Apr 2021 23:40:10 +0200 Subject: [PATCH 1156/1435] General Project Update - Updated CHANGELOG.md - Added STLINK-V3E to supported programmers --- CHANGELOG.md | 22 ++++++++++++++-------- README.md | 2 +- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index ee46901e7..57426342a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,12 +1,14 @@ -# stlink ChangeLog +# stlink Changelog # v1.6.2 -Release date: (planned Q2/2021) +Release date: 2020-04-xx + +This release drops support for the STLINK/V1 programmer on macOS 10.13. Features: -- Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) +- Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#868](https://github.com/stlink-org/stlink/pull/868), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) - Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) - Official support for STLINK-V3 programmers (commit [#5e0a502](https://github.com/stlink-org/stlink/commit/5e0a502df812495bfa96fa9116a19f1306152b17), [#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) - Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) @@ -18,6 +20,7 @@ Features: - Link for WIN32 & APPLE with stlink-static ([#1069](https://github.com/stlink-org/stlink/pull/1069)) - ITM functionality for STLink/V2 and STM32Fxx chipsets ([#136](https://github.com/stlink-org/stlink/pull/136), [#179](https://github.com/stlink-org/stlink/pull/179), [#815](https://github.com/stlink-org/stlink/pull/815), [#1072](https://github.com/stlink-org/stlink/pull/1072)) - Included ITM functionality for building with MSVC ([#1080](https://github.com/stlink-org/stlink/pull/1080)) +- Update for CI integration (commit [#0eebc9a](https://github.com/stlink-org/stlink/commit/0eebc9a74506e84d5c460ec325ae98064a81885e), [#1118](https://github.com/stlink-org/stlink/pull/1118)) Updates & changes: @@ -32,10 +35,11 @@ Updates & changes: - [doc] Added example for output of `st-info --probe` ([#1007](https://github.com/stlink-org/stlink/pull/1007), [#1049](https://github.com/stlink-org/stlink/pull/1049)) - [refactoring] Correctly handle endianness without reference to host platform ([#1081](https://github.com/stlink-org/stlink/pull/1081)) - Check format string for log messages ([#1093](https://github.com/stlink-org/stlink/pull/1093)) +- Removed abort() from stlink-lib ([#1116](https://github.com/stlink-org/stlink/pull/1116)) Fixes: -- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) +- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) - Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106)) - Use vl flashloader for all STM32F1 series ([#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) @@ -60,6 +64,8 @@ Fixes: - Fixed support for writing option bytes ([#1102](https://github.com/stlink-org/stlink/pull/1102)) - [doc] Corrected spelling mistake in bug report template ([#1103](https://github.com/stlink-org/stlink/pull/1103)) - Fixed STM32WB55 reading DEBUG IDCODE from the wrong address ([#1100](https://github.com/stlink-org/stlink/pull/1100), [#1101](https://github.com/stlink-org/stlink/pull/1101)) +- Applied missing changes to tests ([#1119](https://github.com/stlink-org/stlink/pull/1119)) +- Improvements for Chip_ID read ([#1120](https://github.com/stlink-org/stlink/pull/1120)) # v1.6.1 @@ -216,7 +222,7 @@ Release date: 2018-09-13 Major changes and added features: -- Added reset through `AIRCR` ([#540](https://github.com/stlink-org/stlink/pull/540), [#712](https://github.com/stlink-org/stlink/pull/712)) +- Added reset through `AIRCR` ([#254](https://github.com/stlink-org/stlink/pull/254), [#540](https://github.com/stlink-org/stlink/pull/540), [#712](https://github.com/stlink-org/stlink/pull/712)) - Added creation of icons for `.desktop` file ([#684](https://github.com/stlink-org/stlink/pull/684), [#708](https://github.com/stlink-org/stlink/pull/708)) - Added desktop file for linux ([#688](https://github.com/stlink-org/stlink/pull/688)) - Added button to export STM32 flash memory to a file ([#691](https://github.com/stlink-org/stlink/pull/691)) @@ -279,7 +285,6 @@ Major changes and added features: Updates and fixes: -- Fixed gdb-server: STM32L0xx has no `FP_CTRL` register for breakpoints ([#273](https://github.com/stlink-org/stlink/pull/273)) - Added `--flash=n[k][m]` command line option to override device model ([#305](https://github.com/stlink-org/stlink/pull/305), [#516](https://github.com/stlink-org/stlink/pull/516), [#576](https://github.com/stlink-org/stlink/pull/576)) - Updated `libusb` to 1.0.21 for Windows ([#562](https://github.com/stlink-org/stlink/pull/562)) - Fixed low-voltage flashing on STM32F7 devices ([#566](https://github.com/stlink-org/stlink/pull/566), [#567](https://github.com/stlink-org/stlink/pull/567)) @@ -324,11 +329,11 @@ Major changes and added features: - Added manpages (generated with `pandoc` from Markdown) ([#208](https://github.com/stlink-org/stlink/pull/208), [#464](https://github.com/stlink-org/stlink/pull/464), [#466](https://github.com/stlink-org/stlink/pull/466), [#467](https://github.com/stlink-org/stlink/pull/467)) - Removal of undocumented `st-term` utility, which is now replaced by `st-util` ARM semihosting feature ([#228](https://github.com/stlink-org/stlink/pull/228), [#507](https://github.com/stlink-org/stlink/pull/507), commit [#3fd0f09](https://github.com/stlink-org/stlink/commit/3fd0f099782506532198473b24f643a3f68d5ff9)) - Support serial numbers argument for `st-util` and `st-flash` to probe and control multiple connected programmers ([#318](https://github.com/stlink-org/stlink/pull/318), [#398](https://github.com/stlink-org/stlink/pull/398), [#541](https://github.com/stlink-org/stlink/pull/541)) +- Added 'k' (kill) command to gdb-server, which resets the connection ([#358](https://github.com/stlink-org/stlink/pull/358), [#525](https://github.com/stlink-org/stlink/pull/525), [#527](https://github.com/stlink-org/stlink/pull/527), [#528](https://github.com/stlink-org/stlink/pull/528)) - Merge `st-probe` tool into `st-info` ([#398](https://github.com/stlink-org/stlink/pull/398)) - Added support for native debian packaging ([#444](https://github.com/stlink-org/stlink/pull/444), [#472](https://github.com/stlink-org/stlink/pull/472), [#473](https://github.com/stlink-org/stlink/pull/473), [#482](https://github.com/stlink-org/stlink/pull/482), [#483](https://github.com/stlink-org/stlink/pull/483), [#484](https://github.com/stlink-org/stlink/pull/484), [#485](https://github.com/stlink-org/stlink/pull/485)) - Rewritten commandline parsing for `st-flash` ([#459](https://github.com/stlink-org/stlink/pull/459)) - Added `--reset` command to `st-flash` ([#505](https://github.com/stlink-org/stlink/pull/505)) -- st-util should detect when USB commands fail ([#525](https://github.com/stlink-org/stlink/pull/525), [#527](https://github.com/stlink-org/stlink/pull/527), [#528](https://github.com/stlink-org/stlink/pull/528)) Chip support added for: @@ -344,12 +349,12 @@ Chip support added for: Updates and fixes: +- Do a JTAG reset prior to reading CPU information when processor is in deep sleep ([#291](https://github.com/stlink-org/stlink/pull/291), [#428](https://github.com/stlink-org/stlink/pull/428), [#430](https://github.com/stlink-org/stlink/pull/430), [#451](https://github.com/stlink-org/stlink/pull/451)) - Fixed `unaligned addr or size` when trying to write a program in RAM ([#323](https://github.com/stlink-org/stlink/pull/323)) - Fixed flashing on `STM32_F3_SMALL` ([#325](https://github.com/stlink-org/stlink/pull/325)) - Fixed STM32L-problem with flash loader ([#390](https://github.com/stlink-org/stlink/pull/390), [#407](https://github.com/stlink-org/stlink/pull/407), [#408](https://github.com/stlink-org/stlink/pull/408)) - Don't read the target voltage on startup, because it crashes STM32F100 ([#423](https://github.com/stlink-org/stlink/pull/423), [#424](https://github.com/stlink-org/stlink/pull/424)) - Added a useful error message instead of `[!] send_recv` ([#425](https://github.com/stlink-org/stlink/pull/425), [#426](https://github.com/stlink-org/stlink/pull/426)) -- Do a JTAG reset prior to reading CPU information when processor is in deep sleep ([#428](https://github.com/stlink-org/stlink/pull/428), [#430](https://github.com/stlink-org/stlink/pull/430), [#451](https://github.com/stlink-org/stlink/pull/451)) - Fixed STM32F030 erase error ([#442](https://github.com/stlink-org/stlink/pull/442)) - Fixed memory map for STM32F7xx ([#453](https://github.com/stlink-org/stlink/pull/453), [#456](https://github.com/stlink-org/stlink/pull/456)) - Redesign of `st-flash` commandline options parsing ([#459](https://github.com/stlink-org/stlink/pull/459)) @@ -392,6 +397,7 @@ Updates and fixes: - Modified determination of erased byte pattern when flashing ([#193](https://github.com/stlink-org/stlink/pull/193), [#377](https://github.com/stlink-org/stlink/pull/377)) - Use libusb synchronous api ([#194](https://github.com/stlink-org/stlink/pull/194), [#225](https://github.com/stlink-org/stlink/pull/225), [#374](https://github.com/stlink-org/stlink/pull/374)) - Fixed segfault when programmer is already busy and `NULL` pointers are in the list ([#256](https://github.com/stlink-org/stlink/pull/256), [#394](https://github.com/stlink-org/stlink/pull/394)) +- Fixed gdb-server: Cortex M0 chips have no `FP_CTRL` register for breakpoints ([#266](https://github.com/stlink-org/stlink/pull/266), [#273](https://github.com/stlink-org/stlink/pull/273), [#341](https://github.com/stlink-org/stlink/pull/341)) - Fixed issue where "unknown chip id!" was seen every other time ([#352](https://github.com/stlink-org/stlink/pull/352), [#367](https://github.com/stlink-org/stlink/pull/367), [#381](https://github.com/stlink-org/stlink/pull/381)) - Send F4 memory-map and features for STM32F429 ([#188](https://github.com/stlink-org/stlink/pull/188), [#196](https://github.com/stlink-org/stlink/pull/196), [#250](https://github.com/stlink-org/stlink/pull/250), [#251](https://github.com/stlink-org/stlink/pull/251)) (Release v1.1.0) - Added AHB3 Peripherals definition for STM32F4 ([#218](https://github.com/stlink-org/stlink/pull/218), [#288](https://github.com/stlink-org/stlink/pull/288)) (Release v1.1.0) diff --git a/README.md b/README.md index 644c3fd86..93994db49 100644 --- a/README.md +++ b/README.md @@ -36,7 +36,7 @@ It supports several so called STLINK programmer boards (and clones thereof) whic - **STLINK-V3** - transport layer: raw USB commands - stand-alone programmer (STLINK-V3SET, STLINK-V3MINI, STLINK-V3MODS) - - on-board on some STM32 Nucleo boards + - on-board on some STM32 Nucleo boards (STLINK-V3E) _\*)_ **Note: Support for the STLINK/V1 on macOS is limited to 10.14 - 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.** From 9a8e0aa6457640e27a0dbee5d994c3f8249fddf6 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 5 Apr 2021 21:15:18 +0500 Subject: [PATCH 1157/1435] Added the hot plug option to st-flash --- doc/tutorial.md | 2 +- src/st-flash/flash.c | 4 ++-- src/st-flash/flash_opts.c | 2 ++ 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index 37c29ab6a..256513bc4 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -9,7 +9,7 @@ | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
      This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | | --reset | st-flash | Trigger a reset both before and after flashing. The default uses the hardware reset through `NRST` pin.
      A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | | --connect-under-reset | st-info
      st-flash | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
      when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | -| --hot-plug | st-info
      st-util | Connect to the target without reset. | v1.6.2 | +| --hot-plug | st-info
      st-flash
      st-util | Connect to the target without reset. | v1.6.2 | | --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | | --version | st-info
      st-flash
      st-util | Print version information. | v1.3.0 | | --help | st-flash
      st-util | Print list of available commands. | | diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index e870e116c..356515ac4 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -26,8 +26,8 @@ static void cleanup(int signum) { } static void usage(void) { - puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); - puts("command line: ./st-flash [--debug] [--connect-under-reset] [--freq=] [--serial ] erase"); + puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--hot-plug] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); + puts("command line: ./st-flash [--debug] [--connect-under-reset] [--hot-plug] [--freq=] [--serial ] erase"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); puts(" , and : Use hex format."); puts(" : Use decimal, octal or hex (prefix 0xXXX) format, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 63774ea25..172a24468 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -193,6 +193,8 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { } } else if (strcmp(av[0], "--connect-under-reset") == 0) { o->connect = CONNECT_UNDER_RESET; + } else if (strcmp(av[0], "--hot-plug") == 0) { + o->connect = CONNECT_HOT_PLUG; } else { break; // non-option found From 696ea923ce7517a604d43adfe017c1cdda3b7339 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 5 Apr 2021 21:23:16 +0500 Subject: [PATCH 1158/1435] Changed the behavior of the st-flash reset option. The reset option conflicted with the connection type options (connect under reset, hot plug). Now reset of target is performed only after the completion of the firmware if the reset options is used. --- src/st-flash/flash.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 356515ac4..edb54e195 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -98,20 +98,6 @@ int main(int ac, char** av) { } } - if (o.reset) { - if (sl->version.stlink_v > 1) { - if (stlink_jtag_reset(sl, 2)) { - printf("Failed to reset JTAG\n"); - goto on_error; - } - } - - if (stlink_reset(sl)) { - printf("Failed to reset device\n"); - goto on_error; - } - } - // core must be halted to use RAM based flashloaders if (stlink_force_debug(sl)) { printf("Failed to halt the core\n"); From d3bc853209a6785a1f87a2359839e80c15735563 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 5 Apr 2021 21:53:57 +0500 Subject: [PATCH 1159/1435] Update tutorial --- doc/tutorial.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index 256513bc4..21f1498ee 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -7,7 +7,7 @@ | --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
      to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
      Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
      "k" or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | | --freq=n[k][m] | st-info
      st-flash
      st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
      This option solely accepts decimal values (5K or 1.8M) with the unit `Hz` being left out. Valid frequencies are:
      `5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K, 1800K, 4000K(4M)`. | v1.6.1 | | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
      This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | -| --reset | st-flash | Trigger a reset both before and after flashing. The default uses the hardware reset through `NRST` pin.
      A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | +| --reset | st-flash | Trigger a reset after flashing. The default uses the hardware reset through `NRST` pin.
      A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | | --connect-under-reset | st-info
      st-flash | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
      when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | | --hot-plug | st-info
      st-flash
      st-util | Connect to the target without reset. | v1.6.2 | | --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | From 4fc6344d44681a0add3bdce69ecf2d0e4e70db49 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 5 Apr 2021 22:13:17 +0500 Subject: [PATCH 1160/1435] flash_loader: fixed alignment of size of the lx loader --- src/stlink-lib/flash_loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 80262cf07..cd7096490 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -68,7 +68,7 @@ static const uint8_t loader_code_stm32lx[] = { 0x00, 0xf1, 0x04, 0x00, 0x01, 0xf1, 0x04, 0x01, 0x04, 0x3a, 0xf7, 0xdc, - 0x00, 0xbe + 0x00, 0xbe, 0x00, 0x00 }; static const uint8_t loader_code_stm32f4[] = { From 5ce54824a5ca819a7ff630b880268febb07ff3e3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 5 Apr 2021 21:55:54 +0200 Subject: [PATCH 1161/1435] Updated CI & MinGW64 cross build configuration - Moved config for macOS 10.14 to GitHub Actions (Note: preparation only, yet inactive) - Removed macOS 10.14 builds from Travis CI - Removed Linux build config from Travis CI - Split 32- & 64-bit cross builds to separate jobs - Minor fixes for MinGW64 cross build config --- .github/workflows/c-cpp.yml | 90 ++++++++++++++++++++ .travis.sh | 22 ++--- .travis.yml | 79 ++--------------- cmake/modules/Findlibusb.cmake | 18 ++-- cmake/modules/c_flags.cmake | 2 +- cmake/packaging/windows/generate_binaries.sh | 18 ++-- 6 files changed, 123 insertions(+), 106 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index 4769450ae..97f48d88d 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -282,6 +282,96 @@ jobs: # macOS + # job_macos_10_14_64_gcc: + # name: macos-10.14 gcc + # runs-on: macos-10.14 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: brew install gcc libusb gtk+3 + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean + + # job_macos_10_14_32_gcc: + # name: macos-10.14 gcc 32-bit + # runs-on: macos-10.14 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: brew install gcc libusb gtk+3 + # - name: Set compiler flags + # run: | + # CFLAGS="$CFLAGS -m32" + # CXXFLAGS="$CXXFLAGS -m32" + # LDFLAGS="$LDFLAGS -m32" + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean + + # job_macos_10_14_64_clang: + # name: macos-10.14 clang + # runs-on: macos-10.14 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: brew install llvm libusb gtk+3 + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean + + # job_macos_10_14_32_clang: + # name: macos-10.14 clang 32-bit + # runs-on: macos-10.14 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: brew install llvm libusb gtk+3 + # - name: Set compiler flags + # run: | + # CFLAGS="$CFLAGS -m32" + # CXXFLAGS="$CXXFLAGS -m32" + # LDFLAGS="$LDFLAGS -m32" + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean + job_macos_10_15_gcc: name: macos-10.15 gcc runs-on: macos-10.15 diff --git a/.travis.sh b/.travis.sh index de2a42372..e45cd3609 100755 --- a/.travis.sh +++ b/.travis.sh @@ -8,18 +8,19 @@ echo "----" echo "WORK DIR:$DIR" DIR=$PWD -if [ "$TRAVIS_JOB_NAME" == "linux-mingw" ]; then +if [ "$TRAVIS_JOB_NAME" == "linux-mingw-64" ]; then echo "--> Building for Windows (x86-64) ..." - mkdir -p build-mingw && cd build-mingw + mkdir -p build-mingw && cd build-mingw-64 cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && rm -rf build-mingw && cd - + make && rm -rf build-mingw-64 && cd - +elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then echo "--> Building for Windows (i686) ..." - mkdir -p build-mingw && cd build-mingw + mkdir -p build-mingw && cd build-mingw-32 cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && rm -rf build-mingw && cd - + make && rm -rf build-mingw-32 && cd - elif [ "$TRAVIS_OS_NAME" == "linux" ]; then sudo apt-get update -qq || true @@ -34,17 +35,6 @@ elif [ "$TRAVIS_OS_NAME" == "linux" ]; then cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make package && cd - -elif [ "$TRAVIS_OS_NAME" == "osx" ]; then - echo "--> Building Debug..." - mkdir -p build/Debug && cd build/Debug - cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && cd - - - echo "--> Building Release with package..." - mkdir -p build/Release && cd build/Release - cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make package && cd - - else # local test-build echo "--> Building Debug..." mkdir -p build/Debug && cd build/Debug diff --git a/.travis.yml b/.travis.yml index 2a788fd69..a733019a1 100644 --- a/.travis.yml +++ b/.travis.yml @@ -2,32 +2,22 @@ language: c jobs: include: - ### 64-bit build on AMD64 ### - - os: linux - dist: focal - env: BADGE=linux - compiler: gcc-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] + ### cross builds on AMD64 ### - ### 32-bit build on AMD64 ### - os: linux dist: focal - env: BADGE=linux + env: BADGE=linux-mingw-64 + name: linux-mingw compiler: gcc-10 addons: apt: sources: ["ubuntu-toolchain-r-test"] - packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm"] - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + packages: + ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - ### cross build on AMD64 ### - os: linux dist: focal - env: BADGE=linux-mingw + env: BADGE=linux-mingw-32 name: linux-mingw compiler: gcc-10 addons: @@ -35,64 +25,9 @@ jobs: sources: ["ubuntu-toolchain-r-test"] packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - before_install: - - LDFLAGS="$LDFLAGS -NDEBUG"; - - ### macOS ### - # - os: osx - # env: BADGE=osx - # osx_image: xcode11.3 - # name: macOS 10.14.6 gcc - # compiler: gcc - # addons: - # homebrew: - # packages: - # - gcc - # - libusb - # - gtk+3 - - # - os: osx - # env: BADGE=osx - # osx_image: xcode11.3 - # name: macOS 10.14.6 gcc 32-bit - # compiler: gcc - # addons: - # homebrew: - # packages: - # - gcc - # - libusb - # - gtk+3 - # before_install: - # - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - # - os: osx - # env: BADGE=osx - # osx_image: xcode11.3 - # name: macOS 10.14.6 clang - # compiler: clang - # addons: - # homebrew: - # packages: - # - llvm - # - libusb - # - gtk+3 - - # - os: osx - # env: BADGE=osx - # osx_image: xcode11.3 - # name: macOS 10.14.6 clang 32-bit - # compiler: clang - # addons: - # homebrew: - # packages: - # - llvm - # - libusb - # - gtk+3 - # before_install: - # - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; script: - git fetch --tags - printenv - cmake --version - - if [[ "$TRAVIS_OS_NAME" == "linux" ]] || [[ "$TRAVIS_OS_NAME" == "osx" ]]; then ./.travis.sh; fi + - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then ./.travis.sh; fi diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index 3082a9509..257c682ce 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -10,7 +10,7 @@ include(FindPackageHandleStandardArgs) -if (APPLE) # macOS +if (APPLE) # macOS FIND_PATH( LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr /usr/local /opt @@ -27,7 +27,7 @@ if (APPLE) message(FATAL_ERROR "No libusb library found on your system! Install libusb-1.0 from Homebrew or MacPorts") endif () -elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated into the system +elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated into the system FIND_PATH( LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr/include @@ -43,13 +43,13 @@ elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") message(FATAL_ERROR "Expected libusb library not found on your system! Verify your system integrity.") endif () -elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-toolchain on Debian - # for MinGW/MSYS/MSVC: 64-bit or 32-bit? +elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-toolchain on Debian + # MinGW/MSYS/MSVC: 64-bit or 32-bit? if (CMAKE_SIZEOF_VOID_P EQUAL 8) message(STATUS "=== Building for Windows (x86-64) ===") set(ARCH 64) else () - message(STATUS "=== Building for Windowsm (i686) ===") + message(STATUS "=== Building for Windows (i686) ===") set(ARCH 32) endif () @@ -77,14 +77,14 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) if (NOT LIBUSB_FOUND) # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/3rdparty/libusb-${LIBUSB_WIN_VERSION}) - else (EXISTS "/etc/debian_version" AND MINGW) # ... only for cross-building on Debian - set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_SOURCE_DIR}/build-mingw/${LIBUSB_WIN_ARCHIVE}) - set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_SOURCE_DIR}/build-mingw/3rdparty/libusb-${LIBUSB_WIN_VERSION}) + else (EXISTS "/etc/debian_version" AND MINGW) # ... only for cross-building on Debian + set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_SOURCE_DIR}/build-mingw-${ARCH}/${LIBUSB_WIN_ARCHIVE}) + set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_SOURCE_DIR}/build-mingw-${ARCH}/3rdparty/libusb-${LIBUSB_WIN_VERSION}) endif () # Get libusb package diff --git a/cmake/modules/c_flags.cmake b/cmake/modules/c_flags.cmake index 8291ea0ee..5ed0c4d7d 100644 --- a/cmake/modules/c_flags.cmake +++ b/cmake/modules/c_flags.cmake @@ -41,7 +41,7 @@ if (NOT CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") add_cflag_if_supported("-Wredundant-decls") endif () -if (NOT WIN32) +if (NOT (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW))) add_cflag_if_supported("-fPIC") endif () diff --git a/cmake/packaging/windows/generate_binaries.sh b/cmake/packaging/windows/generate_binaries.sh index d38f8d62f..bf2453d10 100644 --- a/cmake/packaging/windows/generate_binaries.sh +++ b/cmake/packaging/windows/generate_binaries.sh @@ -6,23 +6,25 @@ #sudo apt-get install mingw-w64 # x86_64 -mkdir build-mingw -cd build-mingw +mkdir build-mingw-64 +cd build-mingw-64 cmake -DCMAKE_SYSTEM_NAME=Windows \ -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=./cmake/modules/set_toolchain.cmake .. + -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. make package cp dist/*.zip ../build/Release/dist +make clean cd .. -rm -rf build-mingw +rm -rf build-mingw-64 # i686 -mkdir build-mingw -cd build-mingw +mkdir build-mingw-32 +cd build-mingw-32 cmake -DCMAKE_SYSTEM_NAME=Windows \ -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=./cmake/modules/set_toolchain.cmake .. + -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. make package cp dist/*.zip ../build/Release/dist +make clean cd .. -rm -rf build-mingw +rm -rf build-mingw-32 From 89a495d169a15f42d8cfd1a68c6738c984d052f8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 6 Apr 2021 00:46:44 +0200 Subject: [PATCH 1162/1435] Updated libusb to v1.0.24 Note: Due to a compilation bug in libusb v1.0.24, building of x86-64 windows binaries is currently not possible and has been deactivated. --- .gitignore | 1 + .travis.sh | 18 +++++++-------- .travis.yml | 24 ++++++++++---------- cmake/modules/Findlibusb.cmake | 6 ++--- cmake/packaging/windows/generate_binaries.sh | 24 ++++++++++---------- 5 files changed, 37 insertions(+), 36 deletions(-) diff --git a/.gitignore b/.gitignore index a07eed9ca..82c1195e4 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,6 @@ build build-mingw +build-mingw-* .project .cmake/ diff --git a/.travis.sh b/.travis.sh index e45cd3609..58cea5746 100755 --- a/.travis.sh +++ b/.travis.sh @@ -8,20 +8,20 @@ echo "----" echo "WORK DIR:$DIR" DIR=$PWD -if [ "$TRAVIS_JOB_NAME" == "linux-mingw-64" ]; then - echo "--> Building for Windows (x86-64) ..." - mkdir -p build-mingw && cd build-mingw-64 - cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && rm -rf build-mingw-64 && cd - - -elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then +if [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then echo "--> Building for Windows (i686) ..." - mkdir -p build-mingw && cd build-mingw-32 + mkdir -p build-mingw-32 && cd build-mingw-32 cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && rm -rf build-mingw-32 && cd - +# elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-64" ]; then +# echo "--> Building for Windows (x86-64) ..." +# mkdir -p build-mingw-64 && cd build-mingw-64 +# cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ +# -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR +# make && rm -rf build-mingw-64 && cd - + elif [ "$TRAVIS_OS_NAME" == "linux" ]; then sudo apt-get update -qq || true diff --git a/.travis.yml b/.travis.yml index a733019a1..307c0bfa0 100644 --- a/.travis.yml +++ b/.travis.yml @@ -4,21 +4,10 @@ jobs: include: ### cross builds on AMD64 ### - - os: linux - dist: focal - env: BADGE=linux-mingw-64 - name: linux-mingw - compiler: gcc-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: - ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - - os: linux dist: focal env: BADGE=linux-mingw-32 - name: linux-mingw + name: linux-mingw-32 compiler: gcc-10 addons: apt: @@ -26,6 +15,17 @@ jobs: packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] + # - os: linux + # dist: focal + # env: BADGE=linux-mingw-64 + # name: linux-mingw-64 + # compiler: gcc-10 + # addons: + # apt: + # sources: ["ubuntu-toolchain-r-test"] + # packages: + # ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] + script: - git fetch --tags - printenv diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index 257c682ce..99f4d56ec 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -77,7 +77,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to if (NOT LIBUSB_FOUND) # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) @@ -94,7 +94,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download - ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 cf3d38d2ff053ef343d10c0b8b0950c2 + ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 5c944b1c8aa9d43e026a94302d0f8ac4 ) endif () @@ -128,7 +128,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to set(LIBUSB_NAME libusb-1.0.lib) find_library( LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS${ARCH}/dll + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/**/MS${ARCH}/dll NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH ) diff --git a/cmake/packaging/windows/generate_binaries.sh b/cmake/packaging/windows/generate_binaries.sh index bf2453d10..5616ecb38 100644 --- a/cmake/packaging/windows/generate_binaries.sh +++ b/cmake/packaging/windows/generate_binaries.sh @@ -5,18 +5,6 @@ # Install this cross-compiler toolchain: #sudo apt-get install mingw-w64 -# x86_64 -mkdir build-mingw-64 -cd build-mingw-64 -cmake -DCMAKE_SYSTEM_NAME=Windows \ - -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. -make package -cp dist/*.zip ../build/Release/dist -make clean -cd .. -rm -rf build-mingw-64 - # i686 mkdir build-mingw-32 cd build-mingw-32 @@ -28,3 +16,15 @@ cp dist/*.zip ../build/Release/dist make clean cd .. rm -rf build-mingw-32 + +# x86_64 +# mkdir build-mingw-64 +# cd build-mingw-64 +# cmake -DCMAKE_SYSTEM_NAME=Windows \ +# -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ +# -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. +# make package +# cp dist/*.zip ../build/Release/dist +# make clean +# cd .. +# rm -rf build-mingw-64 From ee43e3b3571c8c7d253b158bbab2d330b3ef19cb Mon Sep 17 00:00:00 2001 From: anton Date: Tue, 6 Apr 2021 21:13:54 +0500 Subject: [PATCH 1163/1435] Unification of the reset function --- inc/stlink.h | 24 +++++++++-- src/common.c | 91 +++++++++++++++++++++++++++++++++++++-- src/st-flash/flash.c | 13 +----- src/st-trace/trace.c | 2 +- src/st-util/gdb-server.c | 92 +++++++++++++--------------------------- src/stlink-lib/sg.c | 2 +- src/stlink-lib/usb.c | 51 +--------------------- src/stlink-lib/usb.h | 6 --- tests/sg.c | 2 +- tests/usb.c | 2 +- 10 files changed, 145 insertions(+), 140 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 855e5126d..8fe6033d6 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -58,6 +58,11 @@ enum target_state { #define STLINK_JTAG_READDEBUG_32BIT 0x36 #define STLINK_JTAG_DRIVE_NRST 0x3C +/* NRST pin states */ +#define STLINK_JTAG_DRIVE_NRST_LOW 0x00 +#define STLINK_JTAG_DRIVE_NRST_HIGH 0x01 +#define STLINK_JTAG_DRIVE_NRST_PULSE 0x02 + #define STLINK_DEBUG_APIV2_SWD_SET_FREQ 0x43 #define STLINK_APIV3_SET_COM_FREQ 0x61 @@ -173,6 +178,19 @@ enum transport_type { TRANSPORT_TYPE_INVALID }; +enum connect_type { + CONNECT_HOT_PLUG = 0, + CONNECT_NORMAL = 1, + CONNECT_UNDER_RESET = 2, +}; + +enum reset_type { + RESET_AUTO = 0, + RESET_HARD = 1, + RESET_SOFT = 2, + RESET_SOFT_AND_HALT = 3, +}; + typedef struct _stlink stlink_t; #include @@ -231,9 +249,7 @@ int stlink_exit_debug_mode(stlink_t *sl); int stlink_exit_dfu_mode(stlink_t *sl); void stlink_close(stlink_t *sl); int stlink_core_id(stlink_t *sl); -int stlink_reset(stlink_t *sl); -int stlink_jtag_reset(stlink_t *sl, int value); -int stlink_soft_reset(stlink_t *sl, int halt_on_reset); +int stlink_reset(stlink_t *sl, enum reset_type type); int stlink_run(stlink_t *sl); int stlink_status(stlink_t *sl); int stlink_version(stlink_t *sl); @@ -301,6 +317,8 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); +int stlink_target_connect(stlink_t *sl, enum connect_type connect); + #include #include #include diff --git a/src/common.c b/src/common.c index 60d7ff145..928091eb4 100644 --- a/src/common.c +++ b/src/common.c @@ -1663,10 +1663,6 @@ int stlink_load_device_params(stlink_t *sl) { return(0); } -int stlink_reset(stlink_t *sl) { - DLOG("*** stlink_reset ***\n"); - return(sl->backend->reset(sl)); -} int stlink_jtag_reset(stlink_t *sl, int value) { DLOG("*** stlink_jtag_reset ***\n"); @@ -1742,6 +1738,59 @@ int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { return(0); } +int stlink_reset(stlink_t *sl, enum reset_type type) { + uint32_t dhcsr; + unsigned timeout; + + DLOG("*** stlink_reset ***\n"); + + if (type == RESET_AUTO) { + // clear S_RESET_ST in DHCSR register for reset state detection + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + } + + if (type == RESET_HARD || type == RESET_AUTO) { + // hardware target reset + if (sl->version.stlink_v > 1) { stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_PULSE); } + if (sl->backend->reset(sl)) { return(-1); } + usleep(10000); + } + + if (type == RESET_AUTO) { + /* Check if the S_RESET_ST bit is set in DHCSR + * This means that a reset has occurred + * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ + + dhcsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + // reset not done yet + // try reset through AIRCR so that NRST does not need to be connected + + WLOG("NRST is not connected\n"); + DLOG("Using reset through SYSRESETREQ\n"); + return stlink_soft_reset(sl, 0); + } + + // waiting for reset the S_RESET_ST bit within 500ms + timeout = time_ms() + 500; + while (time_ms() < timeout) { + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) + return(0); + } + + return(-1); + } + + if (type == RESET_SOFT || type == RESET_SOFT_AND_HALT) { + return stlink_soft_reset(sl, (type==RESET_SOFT_AND_HALT)); + } + + return(0); +} + int stlink_run(stlink_t *sl) { struct stlink_reg rr; DLOG("*** stlink_run ***\n"); @@ -4467,3 +4516,37 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr return(err); } +int stlink_target_connect(stlink_t *sl, enum connect_type connect) { + uint32_t dhcsr; + + if (connect == CONNECT_UNDER_RESET) { + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } + stlink_force_debug(sl); + + // clear S_RESET_ST in DHCSR register + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); + usleep(10000); + + // check NRST connection + dhcsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + WLOG("NRST is not connected\n"); + } + + // addition soft reset for halt before the first instruction + stlink_soft_reset(sl, 1 /* halt on reset */); + } + + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } + + if (connect == CONNECT_NORMAL) { + stlink_reset(sl, RESET_AUTO); + } + + return stlink_load_device_params(sl); +} diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index edb54e195..5eb607758 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -188,14 +188,7 @@ int main(int ac, char** av) { goto on_error; } } else if (o.cmd == CMD_RESET) { - if (sl->version.stlink_v > 1) { - if (stlink_jtag_reset(sl, 2)) { - printf("Failed to reset JTAG\n"); - goto on_error; - } - } - - if (stlink_reset(sl)) { + if (stlink_reset(sl, RESET_AUTO)) { printf("Failed to reset device\n"); goto on_error; } @@ -263,9 +256,7 @@ int main(int ac, char** av) { } if (o.reset) { - if (sl->version.stlink_v > 1) { stlink_jtag_reset(sl, 2); } - - stlink_reset(sl); + stlink_reset(sl, RESET_AUTO); } err = 0; // success diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 3180335a0..f40a9d683 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -203,7 +203,7 @@ static bool enable_trace(stlink_t* stlink, const st_settings_t* settings, uint32 return false; } - if (settings->reset_board && stlink_jtag_reset(stlink, 2)) { + if (settings->reset_board && stlink_reset(stlink, RESET_AUTO)) { ELOG("Unable to reset device\n"); if (!settings->force) return false; diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 8d63d9ee0..c2a220df3 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -42,9 +42,6 @@ #define FLASH_PAGE (sl->flash_pgsz) static stlink_t *connected_stlink = NULL; -static bool semihosting = false; -static bool serial_specified = false; -static char serialnumber[STLINK_SERIAL_BUFFER_SIZE] = {0}; #if defined(_WIN32) #define close_socket win32_close_socket @@ -57,8 +54,6 @@ static char serialnumber[STLINK_SERIAL_BUFFER_SIZE] = {0}; static const char hex[] = "0123456789abcdef"; -static const char* current_memory_map = NULL; - typedef struct _st_state_t { // things from command line, bleh int logging_level; @@ -66,6 +61,9 @@ typedef struct _st_state_t { int persistent; enum connect_type connect_mode; int freq; + char serialnumber[STLINK_SERIAL_BUFFER_SIZE]; + bool semihosting; + const char* current_memory_map; } st_state_t; @@ -97,20 +95,6 @@ BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { } #endif - -static stlink_t* do_connect(st_state_t *st) { - stlink_t *sl = NULL; - - if (serial_specified) { - sl = stlink_open_usb(st->logging_level, st->connect_mode, serialnumber, st->freq); - } else { - sl = stlink_open_usb(st->logging_level, st->connect_mode, NULL, st->freq); - } - - return(sl); -} - - int parse_options(int argc, char** argv, st_state_t *st) { static struct option long_options[] = { {"help", no_argument, NULL, 'h'}, @@ -119,6 +103,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { {"multi", optional_argument, NULL, 'm'}, {"no-reset", optional_argument, NULL, 'n'}, {"hot-plug", optional_argument, NULL, 'n'}, + {"connect-under-reset", optional_argument, NULL, 'u'}, {"freq", optional_argument, NULL, 'F'}, {"version", no_argument, NULL, 'V'}, {"semihosting", no_argument, NULL, SEMIHOSTING_OPTION}, @@ -138,6 +123,8 @@ int parse_options(int argc, char** argv, st_state_t *st) { "\t\t\tst-util will continue listening for connections after disconnect.\n" " -n, --no-reset, --hot-plug\n" "\t\t\tDo not reset board on connection.\n" + " -u, --connect-under-reset\n" + "\t\t\tConnect to the board before executing any instructions.\n" " -F 1800K, --freq=1M\n" "\t\t\tSet the frequency of the SWD/JTAG interface.\n" " --semihosting\n" @@ -182,11 +169,14 @@ int parse_options(int argc, char** argv, st_state_t *st) { break; case 'm': - st->persistent = 1; + st->persistent = true; break; case 'n': st->connect_mode = CONNECT_HOT_PLUG; break; + case 'u': + st->connect_mode = CONNECT_UNDER_RESET; + break; case 'F': st->freq = arg_parse_freq(optarg); if (st->freq < 0) { @@ -198,12 +188,11 @@ int parse_options(int argc, char** argv, st_state_t *st) { printf("v%s\n", STLINK_VERSION); exit(EXIT_SUCCESS); case SEMIHOSTING_OPTION: - semihosting = true; + st->semihosting = true; break; case SERIAL_OPTION: printf("use serial %s\n", optarg); - memcpy(serialnumber, optarg, STLINK_SERIAL_BUFFER_SIZE); - serial_specified = true; + memcpy(st->serialnumber, optarg, STLINK_SERIAL_BUFFER_SIZE); break; } @@ -232,8 +221,7 @@ int main(int argc, char** argv) { printf("st-util\n"); - sl = do_connect(&state); - + sl = stlink_open_usb(state.logging_level, state.connect_mode, state.serialnumber, state.freq); if (sl == NULL) { return(1); } if (sl->chip_id == STLINK_CHIPID_UNKNOWN) { @@ -241,7 +229,9 @@ int main(int argc, char** argv) { return(1); } + sl->verbose = 0; connected_stlink = sl; + #if defined(_WIN32) SetConsoleCtrlHandler((PHANDLER_ROUTINE) CtrlHandler, TRUE); #else @@ -250,18 +240,14 @@ int main(int argc, char** argv) { signal(SIGSEGV, &cleanup); #endif - if (state.connect_mode != CONNECT_HOT_PLUG) { stlink_reset(sl); } - DLOG("Chip ID is %#010x, Core ID is %#08x.\n", sl->chip_id, sl->core_id); - sl->verbose = 0; - current_memory_map = make_memory_map(sl); + state.current_memory_map = make_memory_map(sl); #if defined(_WIN32) WSADATA wsadata; if (WSAStartup(MAKEWORD(2, 2), &wsadata) != 0) { goto winsock_error; } - #endif init_cache(sl); @@ -865,16 +851,13 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { return(0); } -static int flash_go(stlink_t *sl) { +static int flash_go(stlink_t *sl, st_state_t *st) { int error = -1; int ret; flash_loader_t fl; - // some kinds of clock settings do not allow writing to flash. - stlink_reset(sl); + stlink_target_connect(sl, st->connect_mode); stlink_force_debug(sl); - // delay to ensure that STM32 HSI clock and others have started up fully - usleep(10000); for (struct flash_block* fb = flash_root; fb; fb = fb->next) { ILOG("flash_erase: block %08x -> %04x\n", fb->addr, fb->length); @@ -909,7 +892,7 @@ static int flash_go(stlink_t *sl) { } stlink_flashloader_stop(sl, &fl); - stlink_soft_reset(sl, 1 /* halt on reset */); + stlink_reset(sl, RESET_SOFT_AND_HALT); error = 0; error: @@ -1119,10 +1102,9 @@ int serve(stlink_t *sl, st_state_t *st) { close_socket(sock); + stlink_target_connect(sl, st->connect_mode); stlink_force_debug(sl); - if (st->connect_mode != CONNECT_HOT_PLUG) { stlink_reset(sl); } - init_code_breakpoints(sl); init_data_watchpoints(sl); @@ -1198,7 +1180,7 @@ int serve(stlink_t *sl, st_state_t *st) { if (strcmp(op, "read")) { data = NULL; } else if (!strcmp(type, "memory-map")) { - data = current_memory_map; + data = st->current_memory_map; } else if (!strcmp(type, "features")) { data = target_description; } else { @@ -1269,22 +1251,14 @@ int serve(stlink_t *sl, st_state_t *st) { } else if (!strncmp(cmd, "jtag_reset", 10)) { // jtag_reset reply = strdup("OK"); - ret = stlink_jtag_reset(sl, 0); - - if (ret) { - DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); - reply = strdup("E00"); - } - - ret = stlink_jtag_reset(sl, 1); + ret = stlink_reset(sl, RESET_HARD); if (ret) { DLOG("Rcmd: jtag_reset failed with jtag_reset\n"); reply = strdup("E00"); } ret = stlink_force_debug(sl); - if (ret) { DLOG("Rcmd: jtag_reset failed with force_debug\n"); reply = strdup("E00"); @@ -1297,14 +1271,12 @@ int serve(stlink_t *sl, st_state_t *st) { } else if (!strncmp(cmd, "reset", 5)) { // reset ret = stlink_force_debug(sl); - if (ret) { DLOG("Rcmd: reset failed with force_debug\n"); reply = strdup("E00"); } - ret = stlink_reset(sl); - + ret = stlink_reset(sl, RESET_AUTO); if (ret) { DLOG("Rcmd: reset failed with reset\n"); reply = strdup("E00"); @@ -1325,10 +1297,10 @@ int serve(stlink_t *sl, st_state_t *st) { while (isspace(*arg)) { arg++; } // skip whitespaces if (!strncmp(arg, "enable", 6) || !strncmp(arg, "1", 1)) { - semihosting = true; + st->semihosting = true; reply = strdup("OK"); } else if (!strncmp(arg, "disable", 7) || !strncmp(arg, "0", 1)) { - semihosting = false; + st->semihosting = false; reply = strdup("OK"); } else { DLOG("Rcmd: unknown semihosting arg: '%s'\n", arg); @@ -1407,7 +1379,7 @@ int serve(stlink_t *sl, st_state_t *st) { free(decoded); } else if (!strcmp(cmdName, "FlashDone")) { - if (flash_go(sl)) { + if (flash_go(sl, st)) { reply = strdup("E08"); } else { reply = strdup("OK"); @@ -1453,7 +1425,7 @@ int serve(stlink_t *sl, st_state_t *st) { int offset = 0; uint16_t insn; - if (!semihosting) { break; } + if (!st->semihosting) { break; } ret = stlink_read_all_regs (sl, ®); @@ -1821,7 +1793,7 @@ int serve(stlink_t *sl, st_state_t *st) { case 'R': { // reset the core. - ret = stlink_reset(sl); + ret = stlink_reset(sl, RESET_AUTO); if (ret) { DLOG("R packet : stlink_reset failed\n"); } init_code_breakpoints(sl); @@ -1835,25 +1807,19 @@ int serve(stlink_t *sl, st_state_t *st) { case 'k': // kill request - reset the connection itself ret = stlink_run(sl); - if (ret) { DLOG("Kill: stlink_run failed\n"); } ret = stlink_exit_debug_mode(sl); - if (ret) { DLOG("Kill: stlink_exit_debug_mode failed\n"); } stlink_close(sl); - sl = do_connect(st); - + sl = stlink_open_usb(st->logging_level, st->connect_mode, st->serialnumber, st->freq); if (sl == NULL || sl->chip_id == STLINK_CHIPID_UNKNOWN) { cleanup(0); } connected_stlink = sl; - if (st->connect_mode != CONNECT_HOT_PLUG) { stlink_reset(sl); } - ret = stlink_force_debug(sl); - if (ret) { DLOG("Kill: stlink_force_debug failed\n"); } init_cache(sl); diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 840466e75..c5946ed19 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -1114,7 +1114,7 @@ stlink_t* stlink_v1_open(const int verbose, int reset) { stlink_enter_swd_mode(sl); // now we are ready to read the parameters - if (reset) { stlink_reset(sl); } + if (reset) { stlink_reset(sl, RESET_AUTO); } stlink_load_device_params(sl); ILOG("Successfully opened a stlink v1 debugger\n"); diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index ce0d672c8..99b5f51ef 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -512,13 +512,8 @@ int _stlink_usb_reset(stlink_t * sl) { unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - uint32_t dhcsr; - unsigned timeout; int i, rep_len = 2; - // clear S_RESET_ST in DHCSR registr - _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - // send reset command i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -536,30 +531,7 @@ int _stlink_usb_reset(stlink_t * sl) { return((int)size); } - usleep(10000); - - dhcsr = 0; - _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - // reset not done yet - // try reset through AIRCR so that NRST does not need to be connected - - WLOG("NRST is not connected\n"); - DLOG("Using reset through SYSRESETREQ\n"); - return stlink_soft_reset(sl, 0); - } - - // waiting for a reset within 500ms - timeout = time_ms() + 500; - while (time_ms() < timeout) { - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) - return(0); - } - - return(-1); + return(0); } int _stlink_usb_jtag_reset(stlink_t * sl, int value) { @@ -1382,26 +1354,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, DLOG("JTAG/SWD freq set to %d\n", freq); stlink_set_swdclk(sl, freq); - if (connect == CONNECT_UNDER_RESET) { - stlink_jtag_reset(sl, 0); - - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } - - stlink_force_debug(sl); - stlink_jtag_reset(sl, 1); - usleep(10000); - } - - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } - - if (connect == CONNECT_NORMAL) { - if ( sl->version.stlink_v > 1) { stlink_jtag_reset(sl, 2); } - - stlink_reset(sl); - usleep(10000); - } - - stlink_load_device_params(sl); + stlink_target_connect(sl, connect); return(sl); on_libusb_error: diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index f48ef225d..27de32700 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -48,12 +48,6 @@ extern "C" { #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 -enum connect_type { - CONNECT_HOT_PLUG = 0, - CONNECT_NORMAL = 1, - CONNECT_UNDER_RESET = 2, -}; - struct stlink_libusb { libusb_context* libusb_ctx; libusb_device_handle* usb_handle; diff --git a/tests/sg.c b/tests/sg.c index 745df845f..7584ab5d4 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -46,7 +46,7 @@ int main(void) { // main() ripped out of old stlink-hw.c stlink_core_id(sl); stlink_status(sl); // stlink_force_debug(sl); - stlink_reset(sl); + stlink_reset(sl, RESET_AUTO); stlink_status(sl); // core system control block stlink_read_mem32(sl, 0xe000ed00, 4); diff --git a/tests/usb.c b/tests/usb.c index 03c135f00..5c5c2077d 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -93,7 +93,7 @@ int main(int ac, char** av) { stlink_status(sl); printf("-- reset\n"); - stlink_reset(sl); + stlink_reset(sl, RESET_AUTO); stlink_force_debug(sl); /* Test reg write */ stlink_write_reg(sl, 0x01234567, 3); From 6bd99d4b55cd33c7f3773eda8aadea10e1288b5e Mon Sep 17 00:00:00 2001 From: anton Date: Tue, 6 Apr 2021 22:03:52 +0500 Subject: [PATCH 1164/1435] flash_loader: fixed interrupt masking --- doc/dev/developer.txt | 7 ++++--- doc/tutorial.md | 2 +- inc/backend.h | 2 +- inc/stlink.h | 8 +++++++- src/common.c | 8 ++++---- src/st-flash/flash.c | 2 +- src/st-trace/trace.c | 2 +- src/st-util/gdb-server.c | 16 ++++++++-------- src/stlink-lib/flash_loader.c | 2 +- src/stlink-lib/sg.c | 3 ++- src/stlink-lib/usb.c | 7 +++++-- tests/sg.c | 4 ++-- tests/usb.c | 2 +- 13 files changed, 38 insertions(+), 27 deletions(-) diff --git a/doc/dev/developer.txt b/doc/dev/developer.txt index 9c4da22f7..e3091c003 100644 --- a/doc/dev/developer.txt +++ b/doc/dev/developer.txt @@ -244,18 +244,19 @@ Description: Backend: "jtag_reset" Arguments: sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() - value: 0: drive low, 1: drive high, 2: ???? + value: 0: drive low, 1: drive high, 2: pulse Return: -1 for error. 0 for success. Include: inc/stlink.h -Prototype: int stlink_run(stlink_t *sl); +Prototype: int stlink_run(stlink_t *sl, enum run_type type); Definition: src/common.c Description: Just calls the backend "run" procedure. Backend: "run" Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() + sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() + type: RUN_NORMAL - run target, RUN_FLASH_LOADER - run target with masking interrupts Return: -1 for error. 0 for success. Include: inc/stlink.h diff --git a/doc/tutorial.md b/doc/tutorial.md index 21f1498ee..71af3d45e 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -8,7 +8,7 @@ | --freq=n[k][m] | st-info
      st-flash
      st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
      This option solely accepts decimal values (5K or 1.8M) with the unit `Hz` being left out. Valid frequencies are:
      `5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K, 1800K, 4000K(4M)`. | v1.6.1 | | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
      This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | | --reset | st-flash | Trigger a reset after flashing. The default uses the hardware reset through `NRST` pin.
      A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | -| --connect-under-reset | st-info
      st-flash | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
      when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | +| --connect-under-reset | st-info
      st-flash
      st-util | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
      when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | | --hot-plug | st-info
      st-flash
      st-util | Connect to the target without reset. | v1.6.2 | | --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | | --version | st-info
      st-flash
      st-util | Print version information. | v1.3.0 | diff --git a/inc/backend.h b/inc/backend.h index ebd438127..a45dccd82 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -10,7 +10,7 @@ int (*core_id) (stlink_t * stl); int (*reset) (stlink_t * stl); int (*jtag_reset) (stlink_t * stl, int value); - int (*run) (stlink_t * stl); + int (*run) (stlink_t * stl, enum run_type type); int (*status) (stlink_t * stl); int (*version) (stlink_t *sl); int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); diff --git a/inc/stlink.h b/inc/stlink.h index 8fe6033d6..ec119c145 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -191,6 +191,12 @@ enum reset_type { RESET_SOFT_AND_HALT = 3, }; +enum run_type { + RUN_NORMAL = 0, + RUN_FLASH_LOADER = 1, +}; + + typedef struct _stlink stlink_t; #include @@ -250,7 +256,7 @@ int stlink_exit_dfu_mode(stlink_t *sl); void stlink_close(stlink_t *sl); int stlink_core_id(stlink_t *sl); int stlink_reset(stlink_t *sl, enum reset_type type); -int stlink_run(stlink_t *sl); +int stlink_run(stlink_t *sl, enum run_type type); int stlink_status(stlink_t *sl); int stlink_version(stlink_t *sl); int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); diff --git a/src/common.c b/src/common.c index 928091eb4..63086ab22 100644 --- a/src/common.c +++ b/src/common.c @@ -1791,7 +1791,7 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { return(0); } -int stlink_run(stlink_t *sl) { +int stlink_run(stlink_t *sl, enum run_type type) { struct stlink_reg rr; DLOG("*** stlink_run ***\n"); @@ -1804,7 +1804,7 @@ int stlink_run(stlink_t *sl) { stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); } - return(sl->backend->run(sl)); + return(sl->backend->run(sl, type)); } int stlink_set_swdclk(stlink_t *sl, int freq_khz) { @@ -2096,7 +2096,7 @@ int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size) { void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { stlink_write_reg(sl, addr, 15); /* pc register */ - stlink_run(sl); + stlink_run(sl, RUN_NORMAL); while (stlink_is_core_halted(sl)) { usleep(3000000); } } @@ -2258,7 +2258,7 @@ static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { // set PC to the reset routine stlink_read_debug32(sl, addr + 4, &val); stlink_write_reg(sl, val, 15); - stlink_run(sl); + stlink_run(sl, RUN_NORMAL); } int stlink_mwrite_sram(stlink_t * sl, uint8_t* data, uint32_t length, stm32_addr_t addr) { diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 5eb607758..ede0f1179 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -17,7 +17,7 @@ static void cleanup(int signum) { (void)signum; if (connected_stlink) { // switch back to mass storage mode before closing - stlink_run(connected_stlink); + stlink_run(connected_stlink, RUN_NORMAL); stlink_exit_debug_mode(connected_stlink); stlink_close(connected_stlink); } diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index f40a9d683..f28624475 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -539,7 +539,7 @@ int main(int argc, char** argv) memset(&trace, 0, sizeof(trace)); trace.start_time = time(NULL); - if (stlink_run(stlink)) { + if (stlink_run(stlink, RUN_NORMAL)) { ELOG("Unable to run device\n"); if (!settings.force) return APP_RESULT_STLINK_STATE_ERROR; diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index c2a220df3..c6d329456 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -74,7 +74,7 @@ static void init_cache(stlink_t *sl); static void _cleanup() { if (connected_stlink) { // Switch back to mass storage mode before closing - stlink_run(connected_stlink); + stlink_run(connected_stlink, RUN_NORMAL); stlink_exit_debug_mode(connected_stlink); stlink_close(connected_stlink); } @@ -252,11 +252,11 @@ int main(int argc, char** argv) { init_cache(sl); - do { // don't go beserk if serve() returns with error + do { // don't go beserk if serve() returns with error if (serve(sl, &state)) { usleep (1 * 1000); } - sl = connected_stlink; // in case serve() changed the connection - stlink_run(sl); // continue + sl = connected_stlink; // in case serve() changed the connection + stlink_run(sl, RUN_NORMAL); // continue } while (state.persistent); #if defined(_WIN32) @@ -1229,7 +1229,7 @@ int serve(stlink_t *sl, st_state_t *st) { if (!strncmp(cmd, "resume", 6)) { // resume DLOG("Rcmd: resume\n"); cache_sync(sl); - ret = stlink_run(sl); + ret = stlink_run(sl, RUN_NORMAL); if (ret) { DLOG("Rcmd: resume failed\n"); @@ -1396,7 +1396,7 @@ int serve(stlink_t *sl, st_state_t *st) { case 'c': cache_sync(sl); - ret = stlink_run(sl); + ret = stlink_run(sl, RUN_NORMAL); if (ret) { DLOG("Semihost: run failed\n"); } @@ -1466,7 +1466,7 @@ int serve(stlink_t *sl, st_state_t *st) { // continue execution cache_sync(sl); - ret = stlink_run(sl); + ret = stlink_run(sl, RUN_NORMAL); if (ret) { DLOG("Semihost: continue execution failed with stlink_run\n"); } } else { @@ -1806,7 +1806,7 @@ int serve(stlink_t *sl, st_state_t *st) { } case 'k': // kill request - reset the connection itself - ret = stlink_run(sl); + ret = stlink_run(sl, RUN_NORMAL); if (ret) { DLOG("Kill: stlink_run failed\n"); } ret = stlink_exit_debug_mode(sl); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index cd7096490..ba5efdb8e 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -347,7 +347,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe } /* Run loader */ - stlink_run(sl); + stlink_run(sl, RUN_FLASH_LOADER); /* This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. * But because this usually runs on Unix-like OSes, the 10 µs get rounded up to the "tick" diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index c5946ed19..07971284f 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -731,8 +731,9 @@ void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { } // force the core exit the debug mode. -int _stlink_sg_run(stlink_t *sl) { +int _stlink_sg_run(stlink_t *sl, enum run_type type) { struct stlink_libsg *sg = sl->backend_data; + (void)(type); //unused clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_RUNCORE; sl->q_len = 2; diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 99b5f51ef..2754db06f 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -590,14 +590,17 @@ int _stlink_usb_step(stlink_t* sl) { /** * This seems to do a good job of restarting things from the beginning? * @param sl + * @param type */ -int _stlink_usb_run(stlink_t* sl) { +int _stlink_usb_run(stlink_t* sl, enum run_type type) { struct stlink_libusb * const slu = sl->backend_data; int res; if (sl->version.jtag_api != STLINK_JTAG_API_V1) { - res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN); + res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + ((type==RUN_FLASH_LOADER)?STLINK_REG_DHCSR_C_MASKINTS:0)); return(res); } diff --git a/tests/sg.c b/tests/sg.c index 7584ab5d4..d88fbe760 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -159,7 +159,7 @@ int main(void) { // main() ripped out of old stlink-hw.c #endif #if 0 - stlink_run(sl); + stlink_run(sl, RUN_NORMAL); stlink_status(sl); stlink_force_debug(sl); stlink_status(sl); @@ -196,7 +196,7 @@ int main(void) { // main() ripped out of old stlink-hw.c #endif #if 0 - stlink_run(sl); + stlink_run(sl, RUN_NORMAL); stlink_status(sl); // back to mass mode, just in case ... stlink_exit_debug_mode(sl); diff --git a/tests/usb.c b/tests/usb.c index 5c5c2077d..742f5c578 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -111,7 +111,7 @@ int main(int ac, char** av) { stlink_step(sl); printf("-- run\n"); - stlink_run(sl); + stlink_run(sl, RUN_NORMAL); printf("-- exit_debug_mode\n"); stlink_exit_debug_mode(sl); From c2e898c9228e2b13378987354f602745e1ca7b1c Mon Sep 17 00:00:00 2001 From: anton Date: Tue, 6 Apr 2021 22:43:15 +0500 Subject: [PATCH 1165/1435] Manual NRST pulse shaping Automatic generation via argument two of the jtag_reset function seem doesn't to work --- src/common.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 63086ab22..1cb5c6db0 100644 --- a/src/common.c +++ b/src/common.c @@ -1751,7 +1751,12 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { if (type == RESET_HARD || type == RESET_AUTO) { // hardware target reset - if (sl->version.stlink_v > 1) { stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_PULSE); } + if (sl->version.stlink_v > 1) { + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(100); + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); + } if (sl->backend->reset(sl)) { return(-1); } usleep(10000); } @@ -4522,6 +4527,9 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect) { if (connect == CONNECT_UNDER_RESET) { stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(20); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } stlink_force_debug(sl); From 31738583967b89cf6416fd45a17ca8a7adfe12e2 Mon Sep 17 00:00:00 2001 From: anton Date: Wed, 7 Apr 2021 20:57:17 +0500 Subject: [PATCH 1166/1435] gdb-server: set target configuration after client connects --- src/st-util/gdb-server.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index c6d329456..006a0e3aa 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -242,16 +242,12 @@ int main(int argc, char** argv) { DLOG("Chip ID is %#010x, Core ID is %#08x.\n", sl->chip_id, sl->core_id); - state.current_memory_map = make_memory_map(sl); - #if defined(_WIN32) WSADATA wsadata; if (WSAStartup(MAKEWORD(2, 2), &wsadata) != 0) { goto winsock_error; } #endif - init_cache(sl); - do { // don't go beserk if serve() returns with error if (serve(sl, &state)) { usleep (1 * 1000); } @@ -1102,12 +1098,22 @@ int serve(stlink_t *sl, st_state_t *st) { close_socket(sock); + uint32_t chip_id = sl->chip_id; + stlink_target_connect(sl, st->connect_mode); stlink_force_debug(sl); + if (sl->chip_id != chip_id) { + WLOG("Target has changed!\n"); + } + init_code_breakpoints(sl); init_data_watchpoints(sl); + init_cache(sl); + + st->current_memory_map = make_memory_map(sl); + ILOG("GDB connected.\n"); /* From d2a2c9825a739d92f2c4b7604ca732a2c1e3161e Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 12 Apr 2021 22:34:44 +0500 Subject: [PATCH 1167/1435] Fixed chipid detection on Cortex-MO+ core --- src/common.c | 3 ++- src/stlink-lib/reg.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index a17392cf1..f230bee64 100644 --- a/src/common.c +++ b/src/common.c @@ -1240,7 +1240,8 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); - } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0) { + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0 || + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0P) { // STM32F0 (RM0091, pg914; RM0360, pg713) // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) // STM32G0 (RM0444, pg1367) diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 4849806d7..b581a269c 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -4,6 +4,7 @@ #define STLINK_REG_CM3_CPUID 0xE000ED00 #define STLINK_REG_CMx_CPUID_PARTNO_CM0 0xC20 +#define STLINK_REG_CMx_CPUID_PARTNO_CM0P 0xC60 #define STLINK_REG_CMx_CPUID_PARTNO_CM3 0xC23 #define STLINK_REG_CMx_CPUID_PARTNO_CM4 0xC24 #define STLINK_REG_CMx_CPUID_PARTNO_CM7 0xC27 From dfb00775a3e332c8575d8d5dfc86365de04ed2e3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 15 Apr 2021 22:39:24 +0200 Subject: [PATCH 1168/1435] Updated changelog --- CHANGELOG.md | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 57426342a..0ac52da73 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,6 +1,6 @@ # stlink Changelog -# v1.6.2 +# v1.7.0 Release date: 2020-04-xx @@ -8,7 +8,8 @@ This release drops support for the STLINK/V1 programmer on macOS 10.13. Features: -- Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#868](https://github.com/stlink-org/stlink/pull/868), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) +- Extended set of cmd line arguments for st-info and st-util ([#332](https://github.com/stlink-org/stlink/pull/332), [#990](https://github.com/stlink-org/stlink/pull/990), [#1091](https://github.com/stlink-org/stlink/pull/1091), [#1114](https://github.com/stlink-org/stlink/pull/1114)) +- Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#801](https://github.com/stlink-org/stlink/pull/801), [#868](https://github.com/stlink-org/stlink/pull/868), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) - Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) - Official support for STLINK-V3 programmers (commit [#5e0a502](https://github.com/stlink-org/stlink/commit/5e0a502df812495bfa96fa9116a19f1306152b17), [#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) - Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) @@ -39,7 +40,7 @@ Updates & changes: Fixes: -- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) +- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#807](https://github.com/stlink-org/stlink/pull/807), [#817](https://github.com/stlink-org/stlink/pull/817), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) - Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106)) - Use vl flashloader for all STM32F1 series ([#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) @@ -52,7 +53,7 @@ Fixes: - Fixed `connect under reset` for `st-flash` and `st-util` ([#983](https://github.com/stlink-org/stlink/pull/983)) - Fix for `mmap() size_t overflow` in `st-flash` ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) - [regression] `stlink-gui` installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) -- `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027), [#1064](https://github.com/stlink-org/stlink/pull/1064), [#1065](https://github.com/stlink-org/stlink/pull/1065)) +- `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027), [#1038](https://github.com/stlink-org/stlink/pull/1038),[#1064](https://github.com/stlink-org/stlink/pull/1064), [#1065](https://github.com/stlink-org/stlink/pull/1065)) - GDB: Fixed problems with target description ([#1013](https://github.com/stlink-org/stlink/pull/1013), [#1088](https://github.com/stlink-org/stlink/pull/1088), [#1109](https://github.com/stlink-org/stlink/pull/1109)) - [doc] Fixed wrong path for `rules.d` folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) - Fixed support for STLINK/V1 programmer ([#1045](https://github.com/stlink-org/stlink/pull/1045), [#1105](https://github.com/stlink-org/stlink/pull/1105)) @@ -61,7 +62,7 @@ Fixes: - Bugfixes for compilation with clang ([#1076](https://github.com/stlink-org/stlink/pull/1076), [#1078](https://github.com/stlink-org/stlink/pull/1078)) - Fixed compilation with GCC 11 ([#1077](https://github.com/stlink-org/stlink/pull/1077)) - [regression] Flash_loader: increased wait rounds for slow boards ([#1085](https://github.com/stlink-org/stlink/pull/1085)) -- Fixed support for writing option bytes ([#1102](https://github.com/stlink-org/stlink/pull/1102)) +- Fixed support for writing option bytes ([#1102](https://github.com/stlink-org/stlink/pull/1102), [#1128](https://github.com/stlink-org/stlink/pull/1128)) - [doc] Corrected spelling mistake in bug report template ([#1103](https://github.com/stlink-org/stlink/pull/1103)) - Fixed STM32WB55 reading DEBUG IDCODE from the wrong address ([#1100](https://github.com/stlink-org/stlink/pull/1100), [#1101](https://github.com/stlink-org/stlink/pull/1101)) - Applied missing changes to tests ([#1119](https://github.com/stlink-org/stlink/pull/1119)) @@ -75,7 +76,7 @@ This release drops support for some older operating systems. Check project READM Features: -- Basic compatibility for STLink/V3 programmer ([#271](https://github.com/stlink-org/stlink/pull/271), [#863](https://github.com/stlink-org/stlink/pull/863), [#954](https://github.com/stlink-org/stlink/pull/954)) +- Basic compatibility for STLink/V3 programmer ([#271](https://github.com/stlink-org/stlink/pull/271), [#863](https://github.com/stlink-org/stlink/pull/863), [#954](https://github.com/stlink-org/stlink/pull/954), [#1023](https://github.com/stlink-org/stlink/pull/1023)) - Added support for JTAG command API v2 & distinguish protocol versions v1 and v2 - Compatibility with the STLink/V3 firmware which dropped support for the previous API v1 - As of firmware version J11 the STLink/V1 programmer supports API v2 commands as well @@ -142,6 +143,7 @@ Updates & changes: Fixes: +- Improvements and fixes of the flash loaders, unification of the reset function ([#244](https://github.com/stlink-org/stlink/pull/244), [#382](https://github.com/stlink-org/stlink/pull/382), [#705](https://github.com/stlink-org/stlink/pull/705), [#980](https://github.com/stlink-org/stlink/pull/980), [#995](https://github.com/stlink-org/stlink/pull/995), [#1115](https://github.com/stlink-org/stlink/pull/1115), [#1117](https://github.com/stlink-org/stlink/pull/1117), [#1122](https://github.com/stlink-org/stlink/pull/1122), [#1124](https://github.com/stlink-org/stlink/pull/1124)) - Fixed wait-loop for `flash_loader_run()` ([#290](https://github.com/stlink-org/stlink/pull/290)) - Better argument parsing for CLI tools: `stlink_open_usb` can address v1, v2, v3 ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) - Clear the PG bit before setting the `PER` bit ([#579](https://github.com/stlink-org/stlink/pull/579), [#876](https://github.com/stlink-org/stlink/pull/876)) @@ -163,6 +165,7 @@ Fixes: - Set static link for `libssp` (stack-smashing protection) ([#960](https://github.com/stlink-org/stlink/pull/960), [#961](https://github.com/stlink-org/stlink/pull/961)) - Fixed udev rules installing to wrong directory ([#966](https://github.com/stlink-org/stlink/pull/966)) - Fixed formatting for options display in `st-flash` & `st-info` (commits [#c783d0e](https://github.com/stlink-org/stlink/commit/c783d0e777ccc83a7a8be26a4f4d3414e0478560) and [#562cd24](https://github.com/stlink-org/stlink/commit/562cd2496e696dbd22950925866aac662d81ee5f)) +- Fixed reading of chip ID on Cortex-M0+ core ([#1125](https://github.com/stlink-org/stlink/pull/1125), [#1126](https://github.com/stlink-org/stlink/pull/1126)) # v1.6.0 From 9c1315a73296841ed3c25b4ea9500c187ab8236d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 16 Apr 2021 00:10:20 +0200 Subject: [PATCH 1169/1435] Fixed GitHub Actions code scanning alerts --- src/common.c | 6800 ++++++++++++++++++++------------------ src/st-trace/trace.c | 990 +++--- src/stlink-lib/logging.c | 127 +- 3 files changed, 4089 insertions(+), 3828 deletions(-) diff --git a/src/common.c b/src/common.c index 57322cefd..4541aa31c 100644 --- a/src/common.c +++ b/src/common.c @@ -1,20 +1,20 @@ #define DEBUG_FLASH 0 #include +#include #include #include #include -#include #include -#include #include -#include #include +#include +#include -#include +#include #include #include -#include +#include #ifdef STLINK_HAVE_SYS_MMAN_H #include @@ -35,7 +35,8 @@ /* stm32f FPEC flash controller interface, pm0063 manual */ // TODO - all of this needs to be abstracted out.... -// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) +// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, +// August 2012) #define FLASH_REGS_ADDR 0x40022000 #define FLASH_REGS_SIZE 0x28 @@ -48,7 +49,8 @@ #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) -// STM32F10x_XL has two flash memory banks with separate registers to control the second bank. +// STM32F10x_XL has two flash memory banks with separate registers to control +// the second bank. #define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) #define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) #define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) @@ -128,113 +130,112 @@ // Mostly the same as STM32G0 chips, but there are a few extra // registers because 'cat 3' devices can have two Flash banks. #define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) -#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) -#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) -#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) -#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) -#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) -#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) -#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) -#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) -#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) -#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) +#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) +#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) +#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) +#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) +#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) +#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) +#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) +#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) +#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) +#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) +#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) // G0/G4 FLASH control register -#define STM32Gx_FLASH_CR_PG (0) /* Program */ -#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ -#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ -#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ -#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define STM32Gx_FLASH_CR_STRT (16) /* Start */ -#define STM32Gx_FLASH_CR_OPTSTRT (17) /* Start of modification of option bytes */ -#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ -#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ -#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ -#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ -#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ +#define STM32Gx_FLASH_CR_PG (0) /* Program */ +#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ +#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ +#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ +#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ +#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ +#define STM32Gx_FLASH_CR_STRT (16) /* Start */ +#define STM32Gx_FLASH_CR_OPTSTRT \ + (17) /* Start of modification of option bytes */ +#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ +#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ +#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ +#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ +#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ // G0/G4 FLASH status register #define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) -#define STM32Gx_FLASH_SR_PROGERR (3) -#define STM32Gx_FLASH_SR_WRPERR (4) -#define STM32Gx_FLASH_SR_PGAERR (5) -#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ +#define STM32Gx_FLASH_SR_PROGERR (3) +#define STM32Gx_FLASH_SR_WRPERR (4) +#define STM32Gx_FLASH_SR_PGAERR (5) +#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ +#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ // G4 FLASH option register -#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ +#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ // WB (RM0434) #define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) -#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) -#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) -#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) -#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) -#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) -#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) -#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) +#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) +#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) +#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) +#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) +#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) +#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) +#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) #define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) #define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) +#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) +#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) #define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) #define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) -#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) -#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) -#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) +#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) +#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) +#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) +#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) +#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) +#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) // WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ +#define STM32WB_FLASH_CR_STRT (16) /* Start */ +#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ +#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ // WB Flash status register. #define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ -#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ -#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ -#define STM32WB_FLASH_SR_BSY (16) /* Busy */ +#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ +#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ +#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ +#define STM32WB_FLASH_SR_BSY (16) /* Busy */ // 32L4 register base is at FLASH_REGS_ADDR (0x40022000) -#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) -#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) -#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) -#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) -#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) +#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) +#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) +#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) +#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) +#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) #define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ -#define STM32L4_FLASH_SR_PROGERR 3 -#define STM32L4_FLASH_SR_WRPERR 4 -#define STM32L4_FLASH_SR_PGAERR 5 -#define STM32L4_FLASH_SR_BSY 16 - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +#define STM32L4_FLASH_SR_PROGERR 3 +#define STM32L4_FLASH_SR_WRPERR 4 +#define STM32L4_FLASH_SR_PGAERR 5 +#define STM32L4_FLASH_SR_BSY 16 + +#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ +#define STM32L4_FLASH_CR_PG 0 /* Program */ +#define STM32L4_FLASH_CR_PER 1 /* Page erase */ +#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ +#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ +#define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ +#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ +#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ #define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ // Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | \ - (1lu << STM32L4_FLASH_CR_PER) | \ - (1lu << STM32L4_FLASH_CR_MER1) | \ - (1lu << STM32L4_FLASH_CR_MER1)) +#define STM32L4_FLASH_CR_OPBITS \ + (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ + (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) // Page is fully specified by BKER and PNB #define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) -#define STM32L4_FLASH_OPTR_DUALBANK 21 +#define STM32L4_FLASH_OPTR_DUALBANK 21 // STM32L0x flash register base and offsets RM0090 - DM00031020.pdf #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) @@ -245,21 +246,21 @@ #define STM32L0_FLASH_OBL_LAUNCH (18) #define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 -#define STM32L0_FLASH_SR_WRPERR 8 -#define STM32L0_FLASH_SR_PGAERR 9 +#define STM32L0_FLASH_SR_WRPERR 8 +#define STM32L0_FLASH_SR_PGAERR 9 #define STM32L0_FLASH_SR_NOTZEROERR 16 -#define FLASH_ACR_OFF ((uint32_t) 0x00) -#define FLASH_PECR_OFF ((uint32_t) 0x04) -#define FLASH_PDKEYR_OFF ((uint32_t) 0x08) -#define FLASH_PEKEYR_OFF ((uint32_t) 0x0c) -#define FLASH_PRGKEYR_OFF ((uint32_t) 0x10) -#define FLASH_OPTKEYR_OFF ((uint32_t) 0x14) -#define FLASH_SR_OFF ((uint32_t) 0x18) -#define FLASH_OBR_OFF ((uint32_t) 0x1c) -#define FLASH_WRPR_OFF ((uint32_t) 0x20) - -//STM32F7 +#define FLASH_ACR_OFF ((uint32_t)0x00) +#define FLASH_PECR_OFF ((uint32_t)0x04) +#define FLASH_PDKEYR_OFF ((uint32_t)0x08) +#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) +#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) +#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) +#define FLASH_SR_OFF ((uint32_t)0x18) +#define FLASH_OBR_OFF ((uint32_t)0x1c) +#define FLASH_WRPR_OFF ((uint32_t)0x20) + +// STM32F7 #define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) #define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) #define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) @@ -279,14 +280,17 @@ #define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ #define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ #define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ -#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ -#define FLASH_F7_SR_EOP 0 /* End of operation */ +#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ +#define FLASH_F7_SR_EOP 0 /* End of operation */ #define FLASH_F7_OPTCR1_BOOT_ADD0 0 #define FLASH_F7_OPTCR1_BOOT_ADD1 16 -#define FLASH_F7_SR_ERROR_MASK ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | (1 << FLASH_F7_SR_OP_ERR)) +#define FLASH_F7_SR_ERROR_MASK \ + ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ + (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ + (1 << FLASH_F7_SR_OP_ERR)) -//STM32F4 +// STM32F4 #define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) #define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) #define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) @@ -301,9 +305,9 @@ #define FLASH_F4_CR_SNB 3 #define FLASH_F4_CR_SNB_MASK 0xf8 #define FLASH_F4_SR_ERROR_MASK 0x000000F0 -#define FLASH_F4_SR_PGAERR 5 -#define FLASH_F4_SR_WRPERR 4 -#define FLASH_F4_SR_BSY 16 +#define FLASH_F4_SR_PGAERR 5 +#define FLASH_F4_SR_WRPERR 4 +#define FLASH_F4_SR_BSY 16 // STM32F2 #define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) @@ -327,15 +331,17 @@ #define FLASH_H7_CR_SER 2 #define FLASH_H7_CR_BER 3 #define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid==STLINK_CHIPID_STM32_H7AX?5:7) +#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7AX ? 5 : 7) #define FLASH_H7_CR_SNB 8 #define FLASH_H7_CR_SNB_MASK 0x700 -#define FLASH_H7_SR_QW 2 +#define FLASH_H7_SR_QW 2 #define FLASH_H7_SR_WRPERR 17 #define FLASH_H7_SR_PGSERR 18 #define FLASH_H7_SR_STRBERR 19 -#define FLASH_H7_SR_ERROR_MASK ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | (1 << FLASH_H7_SR_WRPERR)) +#define FLASH_H7_SR_ERROR_MASK \ + ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ + (1 << FLASH_H7_SR_WRPERR)) #define FLASH_H7_OPTCR_OPTLOCK 0 #define FLASH_H7_OPTCR_OPTSTART 1 @@ -362,1189 +368,1188 @@ #define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) #define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) -#define STM32F0_DBGMCU_CR 0xE0042004 -#define STM32F0_DBGMCU_CR_IWDG_STOP 8 -#define STM32F0_DBGMCU_CR_WWDG_STOP 9 +#define STM32F0_DBGMCU_CR 0xE0042004 +#define STM32F0_DBGMCU_CR_IWDG_STOP 8 +#define STM32F0_DBGMCU_CR_WWDG_STOP 9 -#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 +#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 #define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 #define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 -#define STM32L0_DBGMCU_APB1_FZ 0x40015808 -#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 -#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 +#define STM32L0_DBGMCU_APB1_FZ 0x40015808 +#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 +#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 -#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 -#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 +#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 +#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 -#define STM32WB_DBGMCU_APB1FZR1 0xE004203C +#define STM32WB_DBGMCU_APB1FZR1 0xE004203C #define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 #define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 -#define STM32F1_RCC_AHBENR 0x40021014 -#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN +#define STM32F1_RCC_AHBENR 0x40021014 +#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN -#define STM32F4_RCC_AHB1ENR 0x40023830 -#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN +#define STM32F4_RCC_AHB1ENR 0x40023830 +#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN -#define STM32G0_RCC_AHBENR 0x40021038 -#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN +#define STM32G0_RCC_AHBENR 0x40021038 +#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN -#define STM32G4_RCC_AHB1ENR 0x40021048 -#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN +#define STM32G4_RCC_AHB1ENR 0x40021048 +#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN -#define STM32L0_RCC_AHBENR 0x40021030 -#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN +#define STM32L0_RCC_AHBENR 0x40021030 +#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN -#define STM32H7_RCC_AHB1ENR 0x58024538 -#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN +#define STM32H7_RCC_AHB1ENR 0x58024538 +#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN -#define STM32WB_RCC_AHB1ENR 0x58000048 -#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN +#define STM32WB_RCC_AHB1ENR 0x58000048 +#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 - // Endianness // https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html // These functions encode and decode little endian uint16 and uint32 values. -void write_uint32(unsigned char* buf, uint32_t ui) { - buf[0] = ui; - buf[1] = ui >> 8; - buf[2] = ui >> 16; - buf[3] = ui >> 24; +void write_uint32(unsigned char *buf, uint32_t ui) { + buf[0] = ui; + buf[1] = ui >> 8; + buf[2] = ui >> 16; + buf[3] = ui >> 24; } -void write_uint16(unsigned char* buf, uint16_t ui) { - buf[0] = ui ; - buf[1] = ui >> 8; +void write_uint16(unsigned char *buf, uint16_t ui) { + buf[0] = ui; + buf[1] = ui >> 8; } uint32_t read_uint32(const unsigned char *c, const int pt) { - return ((uint32_t)c[pt]) | ((uint32_t)c[pt+1] << 8) | ((uint32_t)c[pt+2] << 16) | ((uint32_t)c[pt+3] << 24) ; + return ((uint32_t)c[pt]) | ((uint32_t)c[pt + 1] << 8) | + ((uint32_t)c[pt + 2] << 16) | ((uint32_t)c[pt + 3] << 24); } uint16_t read_uint16(const unsigned char *c, const int pt) { - return ((uint16_t)c[pt]) | ((uint16_t)c[pt+1] << 8); + return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); } +static uint32_t get_stm32l0_flash_base(stlink_t *sl) { + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_L0: + case STLINK_CHIPID_STM32_L0_CAT5: + case STLINK_CHIPID_STM32_L0_CAT2: + case STLINK_CHIPID_STM32_L011: + return (STM32L0_FLASH_REGS_ADDR); -static uint32_t get_stm32l0_flash_base(stlink_t *sl) -{ - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_L0: - case STLINK_CHIPID_STM32_L0_CAT5: - case STLINK_CHIPID_STM32_L0_CAT2: - case STLINK_CHIPID_STM32_L011: - return(STM32L0_FLASH_REGS_ADDR); - - case STLINK_CHIPID_STM32_L1_CAT2: - case STLINK_CHIPID_STM32_L1_MEDIUM: - case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS: - case STLINK_CHIPID_STM32_L1_HIGH: - return(STM32L1_FLASH_REGS_ADDR); + case STLINK_CHIPID_STM32_L1_CAT2: + case STLINK_CHIPID_STM32_L1_MEDIUM: + case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS: + case STLINK_CHIPID_STM32_L1_HIGH: + return (STM32L1_FLASH_REGS_ADDR); - default: - WLOG("Flash base use default L0 address"); - return(STM32L0_FLASH_REGS_ADDR); - } + default: + WLOG("Flash base use default L0 address"); + return (STM32L0_FLASH_REGS_ADDR); + } } static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { - uint32_t rdp; - stlink_read_debug32(sl, FLASH_WRPR, &rdp); - return(rdp & 0xff); + uint32_t rdp; + stlink_read_debug32(sl, FLASH_WRPR, &rdp); + return (rdp & 0xff); } static inline uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { - uint32_t reg, res; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - reg = (bank == BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; - } else { - reg = (bank == BANK_1)?FLASH_CR:FLASH_CR2; - } - - stlink_read_debug32(sl, reg, &res); + uint32_t reg, res; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + reg = FLASH_F4_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + reg = FLASH_F7_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + } else { + reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } + + stlink_read_debug32(sl, reg, &res); #if DEBUG_FLASH - fprintf(stdout, "CR:0x%x\n", res); + fprintf(stdout, "CR:0x%x\n", res); #endif - return(res); + return (res); } static inline unsigned int is_flash_locked(stlink_t *sl) { - /* return non zero for true */ - uint32_t cr_lock_shift; - uint32_t cr_reg; - uint32_t n; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - cr_lock_shift = FLASH_H7_CR_LOCK; - } else { - ELOG("unsupported flash method, abort\n"); - return(-1); - } - - stlink_read_debug32(sl, cr_reg, &n); - return(n & (1u << cr_lock_shift)); + /* return non zero for true */ + uint32_t cr_lock_shift; + uint32_t cr_reg; + uint32_t n; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + cr_lock_shift = STM32L0_FLASH_PELOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + cr_lock_shift = FLASH_H7_CR_LOCK; + } else { + ELOG("unsupported flash method, abort\n"); + return (-1); + } + + stlink_read_debug32(sl, cr_reg, &n); + return (n & (1u << cr_lock_shift)); } static void unlock_flash(stlink_t *sl) { - uint32_t key_reg, key2_reg = 0; - uint32_t flash_key1 = FLASH_KEY1; - uint32_t flash_key2 = FLASH_KEY2; - /* The unlock sequence consists of 2 write cycles where 2 key values are written - * to the FLASH_KEYR register. - * An invalid sequence results in a definitive lock of the FPEC block until next reset. - */ - - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { - key_reg = FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - key_reg = FLASH_KEYR; - key2_reg = FLASH_KEYR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - key_reg = FLASH_F4_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - key_reg = FLASH_F7_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; - flash_key1 = FLASH_L0_PEKEY1; - flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - key_reg = STM32L4_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - key_reg = STM32Gx_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - key_reg = STM32WB_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - key_reg = FLASH_H7_KEYR1; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - key2_reg = FLASH_H7_KEYR2; - } - } else { - ELOG("unsupported flash method, abort\n"); - return; - } + uint32_t key_reg, key2_reg = 0; + uint32_t flash_key1 = FLASH_KEY1; + uint32_t flash_key2 = FLASH_KEY2; + /* The unlock sequence consists of 2 write cycles where 2 key values are + * written to the FLASH_KEYR register. An invalid sequence results in a + * definitive lock of the FPEC block until next reset. + */ + + if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + key_reg = FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + key_reg = FLASH_KEYR; + key2_reg = FLASH_KEYR2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + key_reg = FLASH_F4_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + key_reg = FLASH_F7_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; + flash_key1 = FLASH_L0_PEKEY1; + flash_key2 = FLASH_L0_PEKEY2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + key_reg = STM32L4_FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + key_reg = STM32Gx_FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + key_reg = STM32WB_FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + key_reg = FLASH_H7_KEYR1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + key2_reg = FLASH_H7_KEYR2; + } + } else { + ELOG("unsupported flash method, abort\n"); + return; + } - stlink_write_debug32(sl, key_reg, flash_key1); - stlink_write_debug32(sl, key_reg, flash_key2); + stlink_write_debug32(sl, key_reg, flash_key1); + stlink_write_debug32(sl, key_reg, flash_key2); - if (key2_reg) { - stlink_write_debug32(sl, key2_reg, flash_key1); - stlink_write_debug32(sl, key2_reg, flash_key2); - } + if (key2_reg) { + stlink_write_debug32(sl, key2_reg, flash_key1); + stlink_write_debug32(sl, key2_reg, flash_key2); + } } /* unlock flash if already locked */ static int unlock_flash_if(stlink_t *sl) { - if (is_flash_locked(sl)) { - unlock_flash(sl); + if (is_flash_locked(sl)) { + unlock_flash(sl); - if (is_flash_locked(sl)) { - WLOG("Failed to unlock flash!\n"); - return(-1); - } + if (is_flash_locked(sl)) { + WLOG("Failed to unlock flash!\n"); + return (-1); } + } - DLOG("Successfully unlocked flash\n"); - return(0); + DLOG("Successfully unlocked flash\n"); + return (0); } static void lock_flash(stlink_t *sl) { - uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; - uint32_t cr_mask = 0xffffffffu; - - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - cr_reg = FLASH_CR; - cr2_reg = FLASH_CR2; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr2_reg = FLASH_H7_CR2; - } - cr_lock_shift = FLASH_H7_CR_LOCK; - cr_mask = ~(1u << FLASH_H7_CR_SER); - } else { - ELOG("unsupported flash method, abort\n"); - return; - } + uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; + uint32_t cr_mask = 0xffffffffu; + + if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + cr_reg = FLASH_CR; + cr2_reg = FLASH_CR2; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + cr_lock_shift = STM32L0_FLASH_PELOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + cr2_reg = FLASH_H7_CR2; + } + cr_lock_shift = FLASH_H7_CR_LOCK; + cr_mask = ~(1u << FLASH_H7_CR_SER); + } else { + ELOG("unsupported flash method, abort\n"); + return; + } - stlink_read_debug32(sl, cr_reg, &n); - n &= cr_mask; - n |= (1u << cr_lock_shift); - stlink_write_debug32(sl, cr_reg, n); + stlink_read_debug32(sl, cr_reg, &n); + n &= cr_mask; + n |= (1u << cr_lock_shift); + stlink_write_debug32(sl, cr_reg, n); - if (cr2_reg) { - n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift); - stlink_write_debug32(sl, cr2_reg, n); - } + if (cr2_reg) { + n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift); + stlink_write_debug32(sl, cr2_reg, n); + } } static bool is_flash_option_locked(stlink_t *sl) { - uint32_t optlock_shift, optcr_reg; - int active_bit_level = 1; - uint32_t n; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; /* bit is "option write enable", not lock */ - break; - case STLINK_FLASH_TYPE_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_F7: - optcr_reg = FLASH_F7_OPTCR; - optlock_shift = FLASH_F7_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_L0: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STLINK_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_WB: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; - } - - stlink_read_debug32(sl, optcr_reg, &n); - - if (active_bit_level == 0) { - return(!(n & (1u << optlock_shift))); - } - - return(n & (1u << optlock_shift)); - + uint32_t optlock_shift, optcr_reg; + int active_bit_level = 1; + uint32_t n; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; /* bit is "option write enable", not lock */ + break; + case STLINK_FLASH_TYPE_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_L0: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STLINK_FLASH_TYPE_L4: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_WB: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + break; + default: + ELOG("unsupported flash method, abort\n"); + return -1; + } + + stlink_read_debug32(sl, optcr_reg, &n); + + if (active_bit_level == 0) { + return (!(n & (1u << optlock_shift))); + } + + return (n & (1u << optlock_shift)); } static int lock_flash_option(stlink_t *sl) { - uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; - int active_bit_level = 1; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; - break; - case STLINK_FLASH_TYPE_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_F7: - optcr_reg = FLASH_F7_OPTCR; - optlock_shift = FLASH_F7_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_L0: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STLINK_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_WB: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optcr2_reg = FLASH_H7_OPTCR2; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; - } - - stlink_read_debug32(sl, optcr_reg, &n); + uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; + int active_bit_level = 1; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; + break; + case STLINK_FLASH_TYPE_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_L0: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STLINK_FLASH_TYPE_L4: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_WB: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optcr2_reg = FLASH_H7_OPTCR2; + break; + default: + ELOG("unsupported flash method, abort\n"); + return -1; + } + + stlink_read_debug32(sl, optcr_reg, &n); + + if (active_bit_level == 0) { + n &= ~(1u << optlock_shift); + } else { + n |= (1u << optlock_shift); + } + + stlink_write_debug32(sl, optcr_reg, n); + + if (optcr2_reg) { + stlink_read_debug32(sl, optcr2_reg, &n); if (active_bit_level == 0) { - n &= ~(1u << optlock_shift); + n &= ~(1u << optlock_shift); } else { - n |= (1u << optlock_shift); + n |= (1u << optlock_shift); } - stlink_write_debug32(sl, optcr_reg, n); + stlink_write_debug32(sl, optcr2_reg, n); + } - if (optcr2_reg) { - stlink_read_debug32(sl, optcr2_reg, &n); - - if (active_bit_level == 0) { - n &= ~(1u << optlock_shift); - } else { - n |= (1u << optlock_shift); - } - - stlink_write_debug32(sl, optcr2_reg, n); - } - - return(0); + return (0); } static int unlock_flash_option(stlink_t *sl) { - uint32_t optkey_reg, optkey2_reg = 0; - uint32_t optkey1 = FLASH_OPTKEY1; - uint32_t optkey2 = FLASH_OPTKEY2; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optkey_reg = FLASH_OPTKEYR; - optkey1 = FLASH_F0_OPTKEY1; - optkey2 = FLASH_F0_OPTKEY2; - break; - case STLINK_FLASH_TYPE_F4: - optkey_reg = FLASH_F4_OPT_KEYR; - break; - case STLINK_FLASH_TYPE_F7: - optkey_reg = FLASH_F7_OPT_KEYR; - break; - case STLINK_FLASH_TYPE_L0: - optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; - optkey1 = FLASH_L0_OPTKEY1; - optkey2 = FLASH_L0_OPTKEY2; - break; - case STLINK_FLASH_TYPE_L4: - optkey_reg = STM32L4_FLASH_OPTKEYR; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optkey_reg = STM32Gx_FLASH_OPTKEYR; - break; - case STLINK_FLASH_TYPE_WB: - optkey_reg = STM32WB_FLASH_OPT_KEYR; - break; - case STLINK_FLASH_TYPE_H7: - optkey_reg = FLASH_H7_OPT_KEYR; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optkey2_reg = FLASH_H7_OPT_KEYR2; - break; - default: - ELOG("unsupported flash method, abort\n"); - return(-1); - } - - stlink_write_debug32(sl, optkey_reg, optkey1); - stlink_write_debug32(sl, optkey_reg, optkey2); - - if (optkey2_reg) { - stlink_write_debug32(sl, optkey2_reg, optkey1); - stlink_write_debug32(sl, optkey2_reg, optkey2); - } - - return(0); + uint32_t optkey_reg, optkey2_reg = 0; + uint32_t optkey1 = FLASH_OPTKEY1; + uint32_t optkey2 = FLASH_OPTKEY2; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optkey_reg = FLASH_OPTKEYR; + optkey1 = FLASH_F0_OPTKEY1; + optkey2 = FLASH_F0_OPTKEY2; + break; + case STLINK_FLASH_TYPE_F4: + optkey_reg = FLASH_F4_OPT_KEYR; + break; + case STLINK_FLASH_TYPE_F7: + optkey_reg = FLASH_F7_OPT_KEYR; + break; + case STLINK_FLASH_TYPE_L0: + optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; + optkey1 = FLASH_L0_OPTKEY1; + optkey2 = FLASH_L0_OPTKEY2; + break; + case STLINK_FLASH_TYPE_L4: + optkey_reg = STM32L4_FLASH_OPTKEYR; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optkey_reg = STM32Gx_FLASH_OPTKEYR; + break; + case STLINK_FLASH_TYPE_WB: + optkey_reg = STM32WB_FLASH_OPT_KEYR; + break; + case STLINK_FLASH_TYPE_H7: + optkey_reg = FLASH_H7_OPT_KEYR; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optkey2_reg = FLASH_H7_OPT_KEYR2; + break; + default: + ELOG("unsupported flash method, abort\n"); + return (-1); + } + + stlink_write_debug32(sl, optkey_reg, optkey1); + stlink_write_debug32(sl, optkey_reg, optkey2); + + if (optkey2_reg) { + stlink_write_debug32(sl, optkey2_reg, optkey1); + stlink_write_debug32(sl, optkey2_reg, optkey2); + } + + return (0); } static int unlock_flash_option_if(stlink_t *sl) { - if (is_flash_option_locked(sl)) { - if (unlock_flash_option(sl)) { - ELOG("Could not unlock flash option!\n"); - return(-1); - } + if (is_flash_option_locked(sl)) { + if (unlock_flash_option(sl)) { + ELOG("Could not unlock flash option!\n"); + return (-1); + } - if (is_flash_option_locked(sl)) { - ELOG("Failed to unlock flash option!\n"); - return(-1); - } + if (is_flash_option_locked(sl)) { + ELOG("Failed to unlock flash option!\n"); + return (-1); } + } - DLOG("Successfully unlocked flash option\n"); - return(0); + DLOG("Successfully unlocked flash option\n"); + return (0); } static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, x; - - x = read_flash_cr(sl, bank); - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - x &= ~STM32L4_FLASH_CR_OPBITS; - x |= (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; - x |= (1 << FLASH_H7_CR_PG); - } else { - cr_reg = FLASH_CR; - x = (1 << FLASH_CR_PG); - } - - stlink_write_debug32(sl, cr_reg, x); + uint32_t cr_reg, x; + + x = read_flash_cr(sl, bank); + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + x &= ~STM32L4_FLASH_CR_OPBITS; + x |= (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + x |= (1 << FLASH_H7_CR_PG); + } else { + cr_reg = FLASH_CR; + x = (1 << FLASH_CR_PG); + } + + stlink_write_debug32(sl, cr_reg, x); } static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, n; - uint32_t bit = FLASH_CR_PG; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; - bit = FLASH_H7_CR_PG; - } else { - cr_reg = FLASH_CR; - } - - n = read_flash_cr(sl, bank) & ~(1 << bit); - stlink_write_debug32(sl, cr_reg, n); + uint32_t cr_reg, n; + uint32_t bit = FLASH_CR_PG; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + bit = FLASH_H7_CR_PG; + } else { + cr_reg = FLASH_CR; + } + + n = read_flash_cr(sl, bank) & ~(1 << bit); + stlink_write_debug32(sl, cr_reg, n); } static void set_flash_cr_per(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, val; + uint32_t cr_reg, val; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - } else { - cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; - } + if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } - stlink_read_debug32(sl, cr_reg, &val); - val |= (1 << FLASH_CR_PER); - stlink_write_debug32(sl, cr_reg, val); + stlink_read_debug32(sl, cr_reg, &val); + val |= (1 << FLASH_CR_PER); + stlink_write_debug32(sl, cr_reg, val); } static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { - uint32_t cr_reg; + uint32_t cr_reg; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - } else { - cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; - } + if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } - const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER); - stlink_write_debug32(sl, cr_reg, n); + const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER); + stlink_write_debug32(sl, cr_reg, n); } static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { - uint32_t val, cr_reg, cr_mer, cr_pg; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); - cr_pg = (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_mer = (1 << STM32Gx_FLASH_CR_MER1); - - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); - } - - cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_mer = (1 << FLASH_CR_MER); - cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; - cr_mer = (1 << FLASH_H7_CR_BER); - cr_pg = (1 << FLASH_H7_CR_PG); - } else { - cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; - cr_mer = (1 << FLASH_CR_MER); - cr_pg = (1 << FLASH_CR_PG); - } - - stlink_read_debug32(sl, cr_reg, &val); - - if (val & cr_pg) { - // STM32F030 will drop MER bit if PG was set - val &= ~cr_pg; - stlink_write_debug32(sl, cr_reg, val); - } + uint32_t val, cr_reg, cr_mer, cr_pg; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); + cr_pg = (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_mer = (1 << STM32Gx_FLASH_CR_MER1); + + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); + } + + cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + cr_mer = (1 << FLASH_H7_CR_BER); + cr_pg = (1 << FLASH_H7_CR_PG); + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); + } + + stlink_read_debug32(sl, cr_reg, &val); + + if (val & cr_pg) { + // STM32F030 will drop MER bit if PG was set + val &= ~cr_pg; + stlink_write_debug32(sl, cr_reg, val); + } - if (v) { - val |= cr_mer; - } else { - val &= ~cr_mer; - } + if (v) { + val |= cr_mer; + } else { + val &= ~cr_mer; + } - stlink_write_debug32(sl, cr_reg, val); + stlink_write_debug32(sl, cr_reg, val); } static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { - uint32_t val, cr_reg, cr_strt; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_strt = (1 << STM32L4_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_strt = (1 << STM32Gx_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_strt = (1 << STM32WB_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; - cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); - } else { - cr_reg = (bank==BANK_1)?FLASH_CR:FLASH_CR2; - cr_strt = (1 << FLASH_CR_STRT); - } - - stlink_read_debug32(sl, cr_reg, &val); - val |= cr_strt; - stlink_write_debug32(sl, cr_reg, val); + uint32_t val, cr_reg, cr_strt; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_strt = 1 << FLASH_F4_CR_STRT; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_strt = 1 << FLASH_F7_CR_STRT; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_strt = (1 << STM32L4_FLASH_CR_STRT); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_strt = (1 << STM32Gx_FLASH_CR_STRT); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_strt = (1 << STM32WB_FLASH_CR_STRT); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + cr_strt = (1 << FLASH_CR_STRT); + } + + stlink_read_debug32(sl, cr_reg, &val); + val |= cr_strt; + stlink_write_debug32(sl, cr_reg, val); } static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { - uint32_t res, sr_reg; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - sr_reg = (bank==BANK_1)?FLASH_SR:FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - sr_reg = (bank==BANK_1)?FLASH_H7_SR1:FLASH_H7_SR2; - } else { - ELOG("method 'read_flash_sr' is unsupported\n"); - return(-1); - } - - stlink_read_debug32(sl, sr_reg, &res); - return(res); + uint32_t res, sr_reg; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + sr_reg = STM32Gx_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else { + ELOG("method 'read_flash_sr' is unsupported\n"); + return (-1); + } + + stlink_read_debug32(sl, sr_reg, &res); + return (res); } static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { - uint32_t sr_reg; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - sr_reg = (bank==BANK_1)?FLASH_SR:FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - sr_reg = (bank==BANK_1)?FLASH_H7_SR1:FLASH_H7_SR2; - } else { - ELOG("method 'write_flash_sr' is unsupported\n"); - return(-1); - } - - return stlink_write_debug32(sl, sr_reg, val); + uint32_t sr_reg; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + sr_reg = STM32Gx_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else { + ELOG("method 'write_flash_sr' is unsupported\n"); + return (-1); + } + + return stlink_write_debug32(sl, sr_reg, val); } static inline unsigned int is_flash_busy(stlink_t *sl) { - uint32_t sr_busy_shift; - unsigned int res; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_L0)) { - sr_busy_shift = FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - sr_busy_shift = FLASH_F4_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - sr_busy_shift = STM32L4_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - sr_busy_shift = STM32Gx_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - sr_busy_shift = STM32WB_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - sr_busy_shift = FLASH_H7_SR_QW; - } else { - ELOG("method 'is_flash_busy' is unsupported\n"); - return(-1); - } - - res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); - - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); - } - - return(res); + uint32_t sr_busy_shift; + unsigned int res; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || + (sl->flash_type == STLINK_FLASH_TYPE_L0)) { + sr_busy_shift = FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + sr_busy_shift = FLASH_F4_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_busy_shift = FLASH_F7_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + sr_busy_shift = STM32L4_FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + sr_busy_shift = STM32Gx_FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + sr_busy_shift = STM32WB_FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_busy_shift = FLASH_H7_SR_QW; + } else { + ELOG("method 'is_flash_busy' is unsupported\n"); + return (-1); + } + + res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); + + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); + } + + return (res); } static void wait_flash_busy(stlink_t *sl) { - // TODO: add some delays here - while (is_flash_busy(sl)) - ; + // TODO: add some delays here + while (is_flash_busy(sl)) + ; } static void wait_flash_busy_progress(stlink_t *sl) { - int i = 0; - fprintf(stdout, "Mass erasing"); - fflush(stdout); - - while (is_flash_busy(sl)) { - usleep(10000); - i++; - - if (i % 100 == 0) { - fprintf(stdout, "."); - fflush(stdout); - } - } - - fprintf(stdout, "\n"); -} - -static void clear_flash_error(stlink_t *sl) -{ - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_F4: - write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_F7: - write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_L0: - write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_L4: - write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_H7: - write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); - } - break; - case STLINK_FLASH_TYPE_WB: - write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); - break; - default: - break; - } -} - -static int check_flash_error(stlink_t *sl) -{ - uint32_t res = 0; - uint32_t WRPERR, PROGERR, PGAERR; - - WRPERR = PROGERR = PGAERR = 0; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; - } - WRPERR = (1 << FLASH_SR_WRPRT_ERR); - PROGERR = (1 << FLASH_SR_PG_ERR); - break; - case STLINK_FLASH_TYPE_F4: - res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; - WRPERR = (1 << FLASH_F4_SR_WRPERR); - PGAERR = (1 << FLASH_F4_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_F7: - res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; - WRPERR = (1 << FLASH_F7_SR_WRP_ERR); - PROGERR = (1 << FLASH_F7_SR_PGP_ERR); - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); - PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); - PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_L0: - res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); - PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_L4: - res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); - PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_H7: - res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; - } - WRPERR = (1 << FLASH_H7_SR_WRPERR); - break; - case STLINK_FLASH_TYPE_WB: - res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); - PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); - PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); - break; - default: - break; + int i = 0; + fprintf(stdout, "Mass erasing"); + fflush(stdout); + + while (is_flash_busy(sl)) { + usleep(10000); + i++; + + if (i % 100 == 0) { + fprintf(stdout, "."); + fflush(stdout); + } + } + + fprintf(stdout, "\n"); +} + +static void clear_flash_error(stlink_t *sl) { + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_F4: + write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_F7: + write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_L0: + write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_L4: + write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_H7: + write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); + } + break; + case STLINK_FLASH_TYPE_WB: + write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); + break; + default: + break; + } +} + +static int check_flash_error(stlink_t *sl) { + uint32_t res = 0; + uint32_t WRPERR, PROGERR, PGAERR; + + WRPERR = PROGERR = PGAERR = 0; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_SR_WRPRT_ERR); + PROGERR = (1 << FLASH_SR_PG_ERR); + break; + case STLINK_FLASH_TYPE_F4: + res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F4_SR_WRPERR); + PGAERR = (1 << FLASH_F4_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_F7: + res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F7_SR_WRP_ERR); + PROGERR = (1 << FLASH_F7_SR_PGP_ERR); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); + PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); + PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_L0: + res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); + PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_L4: + res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); + PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_H7: + res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_H7_SR_WRPERR); + break; + case STLINK_FLASH_TYPE_WB: + res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); + PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); + PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); + break; + default: + break; + } + + if (res) { + if (WRPERR && (WRPERR & res) == WRPERR) { + ELOG("Flash memory is write protected\n"); + res &= ~WRPERR; + } else if (PROGERR && (PROGERR & res) == PROGERR) { + ELOG("Flash memory contains a non-erased value\n"); + res &= ~PROGERR; + } else if (PGAERR && (PGAERR & res) == PGAERR) { + ELOG("Invalid flash address\n"); + res &= ~PGAERR; } if (res) { - if (WRPERR && (WRPERR&res)==WRPERR) { - ELOG("Flash memory is write protected\n"); - res &= ~WRPERR; - } else if (PROGERR && (PROGERR&res)==PROGERR) { - ELOG("Flash memory contains a non-erased value\n"); - res &= ~PROGERR; - } else if (PGAERR && (PGAERR&res)==PGAERR) { - ELOG("Invalid flash address\n"); - res &= ~PGAERR; - } - - if (res) { - ELOG("Flash programming error: %#010x\n", res); - } - return(-1); + ELOG("Flash programming error: %#010x\n", res); } + return (-1); + } - return(0); + return (0); } static void stop_wdg_in_debug(stlink_t *sl) { - uint32_t dbgmcu_cr; - uint32_t set; - uint32_t value; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - case STLINK_FLASH_TYPE_G4: - dbgmcu_cr = STM32F0_DBGMCU_CR; - set = (1<flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - rcc = STM32F1_RCC_AHBENR; - rcc_dma_mask = STM32F1_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_F4: - case STLINK_FLASH_TYPE_F7: - rcc = STM32F4_RCC_AHB1ENR; - rcc_dma_mask = STM32F4_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_G0: - rcc = STM32G0_RCC_AHBENR; - rcc_dma_mask = STM32G0_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_G4: - case STLINK_FLASH_TYPE_L4: - rcc = STM32G4_RCC_AHB1ENR; - rcc_dma_mask = STM32G4_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_L0: - rcc = STM32L0_RCC_AHBENR; - rcc_dma_mask = STM32L0_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_H7: - rcc = STM32H7_RCC_AHB1ENR; - rcc_dma_mask = STM32H7_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_WB: - rcc = STM32WB_RCC_AHB1ENR; - rcc_dma_mask = STM32WB_RCC_DMAEN; - break; - default: - return; - } + uint32_t dbgmcu_cr; + uint32_t set; + uint32_t value; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + case STLINK_FLASH_TYPE_G4: + dbgmcu_cr = STM32F0_DBGMCU_CR; + set = + (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | (1 << STM32F0_DBGMCU_CR_WWDG_STOP); + break; + case STLINK_FLASH_TYPE_F4: + case STLINK_FLASH_TYPE_F7: + case STLINK_FLASH_TYPE_L4: + dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; + set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | + (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); + break; + case STLINK_FLASH_TYPE_L0: + case STLINK_FLASH_TYPE_G0: + dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; + set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | + (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); + break; + case STLINK_FLASH_TYPE_H7: + dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; + set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP); + break; + case STLINK_FLASH_TYPE_WB: + dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1; + set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) | + (1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP); + break; + default: + return; + } + + if (!stlink_read_debug32(sl, dbgmcu_cr, &value)) { + stlink_write_debug32(sl, dbgmcu_cr, value | set); + } +} + +static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { + uint32_t rcc, rcc_dma_mask, value; + + rcc = rcc_dma_mask = value = 0; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + rcc = STM32F1_RCC_AHBENR; + rcc_dma_mask = STM32F1_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_F4: + case STLINK_FLASH_TYPE_F7: + rcc = STM32F4_RCC_AHB1ENR; + rcc_dma_mask = STM32F4_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_G0: + rcc = STM32G0_RCC_AHBENR; + rcc_dma_mask = STM32G0_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_G4: + case STLINK_FLASH_TYPE_L4: + rcc = STM32G4_RCC_AHB1ENR; + rcc_dma_mask = STM32G4_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_L0: + rcc = STM32L0_RCC_AHBENR; + rcc_dma_mask = STM32L0_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_H7: + rcc = STM32H7_RCC_AHB1ENR; + rcc_dma_mask = STM32H7_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_WB: + rcc = STM32WB_RCC_AHB1ENR; + rcc_dma_mask = STM32WB_RCC_DMAEN; + break; + default: + return; + } - if (!stlink_read_debug32(sl, rcc, &value)) { - if (bckpRstr) { - value = (value&(~rcc_dma_mask)) | fl->rcc_dma_bkp; - } else { - fl->rcc_dma_bkp = value&rcc_dma_mask; - value &= ~rcc_dma_mask; - } - stlink_write_debug32(sl, rcc, value); + if (!stlink_read_debug32(sl, rcc, &value)) { + if (bckpRstr) { + value = (value & (~rcc_dma_mask)) | fl->rcc_dma_bkp; + } else { + fl->rcc_dma_bkp = value & rcc_dma_mask; + value &= ~rcc_dma_mask; } + stlink_write_debug32(sl, rcc, value); + } } static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { - stlink_write_debug32(sl, (bank==BANK_1)?FLASH_AR:FLASH_AR2, n); + stlink_write_debug32(sl, (bank == BANK_1) ? FLASH_AR : FLASH_AR2, n); } -static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n, unsigned bank) { - uint32_t cr_reg, psize_shift; - uint32_t x = read_flash_cr(sl, bank); +static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n, + unsigned bank) { + uint32_t cr_reg, psize_shift; + uint32_t x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; - psize_shift = FLASH_H7_CR_PSIZE; - } else { - cr_reg = FLASH_F4_CR; - psize_shift = 8; - } + if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + psize_shift = FLASH_H7_CR_PSIZE; + } else { + cr_reg = FLASH_F4_CR; + psize_shift = 8; + } - x &= ~(0x03 << psize_shift); - x |= (n << psize_shift); + x &= ~(0x03 << psize_shift); + x |= (n << psize_shift); #if DEBUG_FLASH - fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); + fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); #endif - stlink_write_debug32(sl, cr_reg, x); + stlink_write_debug32(sl, cr_reg, x); } static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { - uint32_t cr_reg, snb_mask, snb_shift, ser_shift; - uint32_t x = read_flash_cr(sl, bank); - - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank==BANK_1)?FLASH_H7_CR1:FLASH_H7_CR2; - snb_mask = FLASH_H7_CR_SNB_MASK; - snb_shift = FLASH_H7_CR_SNB; - ser_shift = FLASH_H7_CR_SER; - } else { - cr_reg = FLASH_F4_CR; - snb_mask = FLASH_F4_CR_SNB_MASK; - snb_shift = FLASH_F4_CR_SNB; - ser_shift = FLASH_F4_CR_SER; - } - - x &= ~snb_mask; - x |= (n << snb_shift); - x |= (1 << ser_shift); + uint32_t cr_reg, snb_mask, snb_shift, ser_shift; + uint32_t x = read_flash_cr(sl, bank); + + if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + snb_mask = FLASH_H7_CR_SNB_MASK; + snb_shift = FLASH_H7_CR_SNB; + ser_shift = FLASH_H7_CR_SER; + } else { + cr_reg = FLASH_F4_CR; + snb_mask = FLASH_F4_CR_SNB_MASK; + snb_shift = FLASH_F4_CR_SNB; + ser_shift = FLASH_F4_CR_SER; + } + + x &= ~snb_mask; + x |= (n << snb_shift); + x |= (1 << ser_shift); #if DEBUG_FLASH - fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); + fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); #endif - stlink_write_debug32(sl, cr_reg, x); + stlink_write_debug32(sl, cr_reg, x); } static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { - stlink_write_debug32(sl, STM32L4_FLASH_SR, 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); - uint32_t x = read_flash_cr(sl, BANK_1); - x &= ~STM32L4_FLASH_CR_OPBITS; - x &= ~STM32L4_FLASH_CR_PAGEMASK; - x &= ~(1 << STM32L4_FLASH_CR_MER1); - x &= ~(1 << STM32L4_FLASH_CR_MER2); - x |= (n << STM32L4_FLASH_CR_PNB); - x |= (uint32_t)(1lu << STM32L4_FLASH_CR_PER); + stlink_write_debug32(sl, STM32L4_FLASH_SR, + 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); + uint32_t x = read_flash_cr(sl, BANK_1); + x &= ~STM32L4_FLASH_CR_OPBITS; + x &= ~STM32L4_FLASH_CR_PAGEMASK; + x &= ~(1 << STM32L4_FLASH_CR_MER1); + x &= ~(1 << STM32L4_FLASH_CR_MER2); + x |= (n << STM32L4_FLASH_CR_PNB); + x |= (uint32_t)(1lu << STM32L4_FLASH_CR_PER); #if DEBUG_FLASH - fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); + fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); #endif - stlink_write_debug32(sl, STM32L4_FLASH_CR, x); + stlink_write_debug32(sl, STM32L4_FLASH_CR, x); } // Delegates to the backends... void stlink_close(stlink_t *sl) { - DLOG("*** stlink_close ***\n"); + DLOG("*** stlink_close ***\n"); - if (!sl) { - return; - } + if (!sl) { + return; + } - sl->backend->close(sl); - free(sl); + sl->backend->close(sl); + free(sl); } int stlink_exit_debug_mode(stlink_t *sl) { - int ret; + int ret; - DLOG("*** stlink_exit_debug_mode ***\n"); - ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); + DLOG("*** stlink_exit_debug_mode ***\n"); + ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); - if (ret == -1) { - return(ret); - } + if (ret == -1) { + return (ret); + } - return(sl->backend->exit_debug_mode(sl)); + return (sl->backend->exit_debug_mode(sl)); } int stlink_enter_swd_mode(stlink_t *sl) { - DLOG("*** stlink_enter_swd_mode ***\n"); - return(sl->backend->enter_swd_mode(sl)); + DLOG("*** stlink_enter_swd_mode ***\n"); + return (sl->backend->enter_swd_mode(sl)); } // Force the core into the debug mode -> halted state. int stlink_force_debug(stlink_t *sl) { - DLOG("*** stlink_force_debug_mode ***\n"); - int res = sl->backend->force_debug(sl); - // Stop the watchdogs in the halted state for suppress target reboot - stop_wdg_in_debug(sl); - return(res); + DLOG("*** stlink_force_debug_mode ***\n"); + int res = sl->backend->force_debug(sl); + // Stop the watchdogs in the halted state for suppress target reboot + stop_wdg_in_debug(sl); + return (res); } int stlink_exit_dfu_mode(stlink_t *sl) { - DLOG("*** stlink_exit_dfu_mode ***\n"); - return(sl->backend->exit_dfu_mode(sl)); + DLOG("*** stlink_exit_dfu_mode ***\n"); + return (sl->backend->exit_dfu_mode(sl)); } int stlink_core_id(stlink_t *sl) { - int ret; + int ret; - DLOG("*** stlink_core_id ***\n"); - ret = sl->backend->core_id(sl); + DLOG("*** stlink_core_id ***\n"); + ret = sl->backend->core_id(sl); - if (ret == -1) { - ELOG("Failed to read core_id\n"); - return(ret); - } + if (ret == -1) { + ELOG("Failed to read core_id\n"); + return (ret); + } - if (sl->verbose > 2) { - stlink_print_data(sl); - } + if (sl->verbose > 2) { + stlink_print_data(sl); + } - DLOG("core_id = 0x%08x\n", sl->core_id); - return(ret); + DLOG("core_id = 0x%08x\n", sl->core_id); + return (ret); } // stlink_chip_id() is called by stlink_load_device_params() // do not call this procedure directly. int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { - int ret; - cortex_m3_cpuid_t cpu_id; - - // Read the CPU ID to determine where to read the core id - if (stlink_cpu_id(sl, &cpu_id) || - cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) { - ELOG("Can not connect to target. Please use \'connect under reset\' and try again\n"); - return -1; - } - - /* - * the chip_id register in the reference manual have - * DBGMCU_IDCODE / DBG_IDCODE name - * - */ - - if ((sl->core_id == STM32H7_CORE_ID || - sl->core_id == STM32H7_CORE_ID_JTAG) && - cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { - // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - ret = stlink_read_debug32(sl, 0x5c001000, chip_id); - } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0 || - cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0P) { - // STM32F0 (RM0091, pg914; RM0360, pg713) - // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) - // STM32G0 (RM0444, pg1367) - ret = stlink_read_debug32(sl, 0x40015800, chip_id); - } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) { - // STM32L5 (RM0438, pg2157) - ret = stlink_read_debug32(sl, 0xE0044000, chip_id); - } else /* СM3, СM4, CM7 */ { - // default chipid address - - // STM32F1 (RM0008, pg1087; RM0041, pg681) - // STM32F2 (RM0033, pg1326) - // STM32F3 (RM0316, pg1095; RM0313, pg874) - // STM32F7 (RM0385, pg1676; RM0410, pg1912) - // STM32L1 (RM0038, pg861) - // STM32L4 (RM0351, pg1840; RM0394, pg1560) - // STM32G4 (RM0440, pg2086) - // STM32WB (RM0434, pg1406) - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - } - - if (ret || !(*chip_id)) { - *chip_id = 0; - ELOG("Could not find chip id!\n"); - } else { - *chip_id = (*chip_id) & 0xfff; - - // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for F2/F4 - if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) { - *chip_id = 0x413; - } - } - - return(ret); + int ret; + cortex_m3_cpuid_t cpu_id; + + // Read the CPU ID to determine where to read the core id + if (stlink_cpu_id(sl, &cpu_id) || + cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) { + ELOG("Can not connect to target. Please use \'connect under reset\' and " + "try again\n"); + return -1; + } + + /* + * the chip_id register in the reference manual have + * DBGMCU_IDCODE / DBG_IDCODE name + * + */ + + if ((sl->core_id == STM32H7_CORE_ID || sl->core_id == STM32H7_CORE_ID_JTAG) && + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { + // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + ret = stlink_read_debug32(sl, 0x5c001000, chip_id); + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0 || + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0P) { + // STM32F0 (RM0091, pg914; RM0360, pg713) + // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) + // STM32G0 (RM0444, pg1367) + ret = stlink_read_debug32(sl, 0x40015800, chip_id); + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) { + // STM32L5 (RM0438, pg2157) + ret = stlink_read_debug32(sl, 0xE0044000, chip_id); + } else /* СM3, СM4, CM7 */ { + // default chipid address + + // STM32F1 (RM0008, pg1087; RM0041, pg681) + // STM32F2 (RM0033, pg1326) + // STM32F3 (RM0316, pg1095; RM0313, pg874) + // STM32F7 (RM0385, pg1676; RM0410, pg1912) + // STM32L1 (RM0038, pg861) + // STM32L4 (RM0351, pg1840; RM0394, pg1560) + // STM32G4 (RM0440, pg2086) + // STM32WB (RM0434, pg1406) + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); + } + + if (ret || !(*chip_id)) { + *chip_id = 0; + ELOG("Could not find chip id!\n"); + } else { + *chip_id = (*chip_id) & 0xfff; + + // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for + // F2/F4 + if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) { + *chip_id = 0x413; + } + } + + return (ret); } /** @@ -1553,21 +1558,21 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * @param cpuid pointer to the result object */ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { - uint32_t raw; - - if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { - cpuid->implementer_id = 0; - cpuid->variant = 0; - cpuid->part = 0; - cpuid->revision = 0; - return(-1); - } + uint32_t raw; - cpuid->implementer_id = (raw >> 24) & 0x7f; - cpuid->variant = (raw >> 20) & 0xf; - cpuid->part = (raw >> 4) & 0xfff; - cpuid->revision = raw & 0xf; - return(0); + if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { + cpuid->implementer_id = 0; + cpuid->variant = 0; + cpuid->part = 0; + cpuid->revision = 0; + return (-1); + } + + cpuid->implementer_id = (raw >> 24) & 0x7f; + cpuid->variant = (raw >> 20) & 0xf; + cpuid->part = (raw >> 4) & 0xfff; + cpuid->revision = raw & 0xf; + return (0); } /** @@ -1576,256 +1581,269 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { * @return 0 for success, or -1 for unsupported core type. */ int stlink_load_device_params(stlink_t *sl) { - // This seems to normally work so is unnecessary info for a normal user. - // Demoted to debug. -- REW - DLOG("Loading device parameters....\n"); - const struct stlink_chipid_params *params = NULL; - stlink_core_id(sl); - uint32_t flash_size; - - if (stlink_chip_id(sl, &sl->chip_id)) { - return(-1); - } + // This seems to normally work so is unnecessary info for a normal user. + // Demoted to debug. -- REW + DLOG("Loading device parameters....\n"); + const struct stlink_chipid_params *params = NULL; + stlink_core_id(sl); + uint32_t flash_size; + + if (stlink_chip_id(sl, &sl->chip_id)) { + return (-1); + } + + params = stlink_chipid_get_params(sl->chip_id); + + if (params == NULL) { + WLOG("unknown chip id! %#x\n", sl->chip_id); + return (-1); + } + + if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { + WLOG("Invalid flash type, please check device declaration\n"); + sl->flash_size = 0; + return (0); + } + + // These are fixed... + sl->flash_base = STM32_FLASH_BASE; + sl->sram_base = STM32_SRAM_BASE; + stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size); + + if (params->flash_size_reg & 2) { + flash_size = flash_size >> 16; + } + + flash_size = flash_size & 0xffff; + + if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || + sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || + sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && + (flash_size == 0)) { + sl->flash_size = 128 * 1024; + } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { + sl->flash_size = (flash_size & 0xff) * 1024; + } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_HIGH) { + // 0 is 384k and 1 is 256k + if (flash_size == 0) { + sl->flash_size = 384 * 1024; + } else { + sl->flash_size = 256 * 1024; + } + } else { + sl->flash_size = flash_size * 1024; + } + + sl->flash_type = params->flash_type; + sl->flash_pgsz = params->flash_pagesize; + sl->sram_size = params->sram_size; + sl->sys_base = params->bootrom_base; + sl->sys_size = params->bootrom_size; + sl->option_base = params->option_base; + sl->option_size = params->option_size; + sl->chip_flags = params->flags; + + // medium and low devices have the same chipid. ram size depends on flash + // size. STM32F100xx datasheet Doc ID 16455 Table 2 + if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && + sl->flash_size < 64 * 1024) { + sl->sram_size = 0x1000; + } + + if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { + uint32_t flash_optr; + stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); + + if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { + sl->flash_pgsz <<= 1; + } + } + + // H7 devices with small flash has one bank + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && + sl->flash_type == STLINK_FLASH_TYPE_H7) { + if ((flash_size / sl->flash_pgsz) <= 1) + sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; + } + + ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", + params->description, (unsigned)(sl->sram_size / 1024), + (unsigned)(sl->flash_size / 1024), + (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) + : (unsigned)(sl->flash_pgsz / 1024), + (sl->flash_pgsz < 1024) ? "byte" : "KiB"); + + return (0); +} - params = stlink_chipid_get_params(sl->chip_id); +int stlink_jtag_reset(stlink_t *sl, int value) { + DLOG("*** stlink_jtag_reset ***\n"); + return (sl->backend->jtag_reset(sl, value)); +} - if (params == NULL) { - WLOG("unknown chip id! %#x\n", sl->chip_id); - return(-1); +int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { + int ret; + unsigned timeout; + uint32_t dhcsr, dfsr; + + DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); + + // halt core and enable debugging (if not already done) + // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_DEBUGEN); + + // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) + if (halt_on_reset) { + stlink_write_debug32( + sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); + + // clear VCATCH in the DFSR register + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); + } else { + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | + STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR); + } + + // clear S_RESET_ST in the DHCSR register + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + + // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) + ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, + STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ); + if (ret) { + ELOG("Soft reset failed: error write to AIRCR\n"); + return (ret); + } + + // waiting for a reset within 500ms + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + timeout = time_ms() + 500; + while (time_ms() < timeout) { + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + if (halt_on_reset) { + // waiting halt by the SYSRESETREQ exception + // DDI0403E, p. C1-699, Debug Fault Status Register + dfsr = 0; + stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { + continue; + } + } + timeout = 0; + break; } + } - if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { - WLOG("Invalid flash type, please check device declaration\n"); - sl->flash_size = 0; - return(0); - } + // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); - // These are fixed... - sl->flash_base = STM32_FLASH_BASE; - sl->sram_base = STM32_SRAM_BASE; - stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size); + if (timeout) { + ELOG("Soft reset failed: timeout\n"); + return (-1); + } - if (params->flash_size_reg & 2) { - flash_size = flash_size >> 16; - } + return (0); +} - flash_size = flash_size & 0xffff; - - if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || - sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && (flash_size == 0)) { - sl->flash_size = 128 * 1024; - } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { - sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_HIGH) { - // 0 is 384k and 1 is 256k - if (flash_size == 0) { - sl->flash_size = 384 * 1024; - } else { - sl->flash_size = 256 * 1024; - } - } else { - sl->flash_size = flash_size * 1024; - } +int stlink_reset(stlink_t *sl, enum reset_type type) { + uint32_t dhcsr; + unsigned timeout; + + DLOG("*** stlink_reset ***\n"); + + if (type == RESET_AUTO) { + // clear S_RESET_ST in DHCSR register for reset state detection + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + } - sl->flash_type = params->flash_type; - sl->flash_pgsz = params->flash_pagesize; - sl->sram_size = params->sram_size; - sl->sys_base = params->bootrom_base; - sl->sys_size = params->bootrom_size; - sl->option_base = params->option_base; - sl->option_size = params->option_size; - sl->chip_flags = params->flags; - - // medium and low devices have the same chipid. ram size depends on flash size. - // STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && sl->flash_size < 64 * 1024) { - sl->sram_size = 0x1000; + if (type == RESET_HARD || type == RESET_AUTO) { + // hardware target reset + if (sl->version.stlink_v > 1) { + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(100); + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); + } + if (sl->backend->reset(sl)) { + return (-1); } + usleep(10000); + } - if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { - uint32_t flash_optr; - stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); + if (type == RESET_AUTO) { + /* Check if the S_RESET_ST bit is set in DHCSR + * This means that a reset has occurred + * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ + + dhcsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + // reset not done yet + // try reset through AIRCR so that NRST does not need to be connected - if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { sl->flash_pgsz <<= 1; } + WLOG("NRST is not connected\n"); + DLOG("Using reset through SYSRESETREQ\n"); + return stlink_soft_reset(sl, 0); } - // H7 devices with small flash has one bank - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && sl->flash_type == STLINK_FLASH_TYPE_H7) { - if ((flash_size/sl->flash_pgsz) <= 1) - sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; + // waiting for reset the S_RESET_ST bit within 500ms + timeout = time_ms() + 500; + while (time_ms() < timeout) { + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) + return (0); } - ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", - params->description, (unsigned)(sl->sram_size / 1024), (unsigned)(sl->flash_size / 1024), - (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) : (unsigned)(sl->flash_pgsz / 1024), - (sl->flash_pgsz < 1024) ? "byte" : "KiB"); + return (-1); + } - return(0); + if (type == RESET_SOFT || type == RESET_SOFT_AND_HALT) { + return stlink_soft_reset(sl, (type == RESET_SOFT_AND_HALT)); + } + + return (0); } +int stlink_run(stlink_t *sl, enum run_type type) { + struct stlink_reg rr; + DLOG("*** stlink_run ***\n"); + + /* Make sure we are in Thumb mode + * Cortex-M chips don't support ARM mode instructions + * xPSR may be incorrect if the vector table has invalid data */ + stlink_read_reg(sl, 16, &rr); + if ((rr.xpsr & (1 << 24)) == 0) { + ILOG("Go to Thumb mode\n"); + stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); + } -int stlink_jtag_reset(stlink_t *sl, int value) { - DLOG("*** stlink_jtag_reset ***\n"); - return(sl->backend->jtag_reset(sl, value)); + return (sl->backend->run(sl, type)); } -int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { - int ret; - unsigned timeout; - uint32_t dhcsr, dfsr; - - DLOG("*** stlink_soft_reset %s***\n", halt_on_reset?"(halt) ":""); +int stlink_set_swdclk(stlink_t *sl, int freq_khz) { + DLOG("*** set_swdclk ***\n"); + return (sl->backend->set_swdclk(sl, freq_khz)); +} - // halt core and enable debugging (if not already done) - // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) - stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | - STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); +int stlink_status(stlink_t *sl) { + int ret; - // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) - if (halt_on_reset) { - stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, STLINK_REG_CM3_DEMCR_TRCENA | - STLINK_REG_CM3_DEMCR_VC_HARDERR | STLINK_REG_CM3_DEMCR_VC_BUSERR | - STLINK_REG_CM3_DEMCR_VC_CORERESET); - - // clear VCATCH in the DFSR register - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); - } else { - stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, STLINK_REG_CM3_DEMCR_TRCENA | - STLINK_REG_CM3_DEMCR_VC_HARDERR | STLINK_REG_CM3_DEMCR_VC_BUSERR); - } - - // clear S_RESET_ST in the DHCSR register - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - - // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) - ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | - STLINK_REG_AIRCR_SYSRESETREQ); - if (ret) { - ELOG("Soft reset failed: error write to AIRCR\n"); - return(ret); - } - - // waiting for a reset within 500ms - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - timeout = time_ms() + 500; - while (time_ms() < timeout) { - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) { - if (halt_on_reset) { - // waiting halt by the SYSRESETREQ exception - // DDI0403E, p. C1-699, Debug Fault Status Register - dfsr = 0; - stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); - if ((dfsr&STLINK_REG_DFSR_VCATCH) == 0) { - continue; - } - } - timeout = 0; - break; - } - } - - // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); - - if (timeout) { - ELOG("Soft reset failed: timeout\n"); - return(-1); - } - - return(0); -} - -int stlink_reset(stlink_t *sl, enum reset_type type) { - uint32_t dhcsr; - unsigned timeout; - - DLOG("*** stlink_reset ***\n"); - - if (type == RESET_AUTO) { - // clear S_RESET_ST in DHCSR register for reset state detection - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - } - - if (type == RESET_HARD || type == RESET_AUTO) { - // hardware target reset - if (sl->version.stlink_v > 1) { - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); - // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) - usleep(100); - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); - } - if (sl->backend->reset(sl)) { return(-1); } - usleep(10000); - } - - if (type == RESET_AUTO) { - /* Check if the S_RESET_ST bit is set in DHCSR - * This means that a reset has occurred - * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ - - dhcsr = 0; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - // reset not done yet - // try reset through AIRCR so that NRST does not need to be connected - - WLOG("NRST is not connected\n"); - DLOG("Using reset through SYSRESETREQ\n"); - return stlink_soft_reset(sl, 0); - } - - // waiting for reset the S_RESET_ST bit within 500ms - timeout = time_ms() + 500; - while (time_ms() < timeout) { - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr&STLINK_REG_DHCSR_S_RESET_ST) == 0) - return(0); - } - - return(-1); - } - - if (type == RESET_SOFT || type == RESET_SOFT_AND_HALT) { - return stlink_soft_reset(sl, (type==RESET_SOFT_AND_HALT)); - } - - return(0); -} - -int stlink_run(stlink_t *sl, enum run_type type) { - struct stlink_reg rr; - DLOG("*** stlink_run ***\n"); - - /* Make sure we are in Thumb mode - * Cortex-M chips don't support ARM mode instructions - * xPSR may be incorrect if the vector table has invalid data */ - stlink_read_reg(sl, 16, &rr); - if ((rr.xpsr & (1 << 24)) == 0) { - ILOG("Go to Thumb mode\n"); - stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); - } - - return(sl->backend->run(sl, type)); -} - -int stlink_set_swdclk(stlink_t *sl, int freq_khz) { - DLOG("*** set_swdclk ***\n"); - return(sl->backend->set_swdclk(sl, freq_khz)); -} - -int stlink_status(stlink_t *sl) { - int ret; - - DLOG("*** stlink_status ***\n"); - ret = sl->backend->status(sl); - stlink_core_stat(sl); - return(ret); -} + DLOG("*** stlink_status ***\n"); + ret = sl->backend->status(sl); + stlink_core_stat(sl); + return (ret); +} /** * Decode the version bits, originally from -sg, verified with usb @@ -1833,1109 +1851,1192 @@ int stlink_status(stlink_t *sl) { * @param slv output parsed version object */ void _parse_version(stlink_t *sl, stlink_version_t *slv) { - sl->version.flags = 0; - - if (sl->version.stlink_v < 3) { - uint32_t b0 = sl->q_buf[0]; // lsb - uint32_t b1 = sl->q_buf[1]; - uint32_t b2 = sl->q_buf[2]; - uint32_t b3 = sl->q_buf[3]; - uint32_t b4 = sl->q_buf[4]; - uint32_t b5 = sl->q_buf[5]; // msb - - // b0 b1 || b2 b3 | b4 b5 - // 4b | 6b | 6b || 2B | 2B - // stlink_v | jtag_v | swim_v || st_vid | stlink_pid - - slv->stlink_v = (b0 & 0xf0) >> 4; - slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); - slv->swim_v = b1 & 0x3f; - slv->st_vid = (b3 << 8) | b2; - slv->stlink_pid = (b5 << 8) | b4; - - // ST-LINK/V1 from J11 switch to api-v2 (and support SWD) - if (slv->stlink_v == 1) { - slv->jtag_api = slv->jtag_v > 11 ? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; - } else { - slv->jtag_api = STLINK_JTAG_API_V2; - - // preferred API to get last R/W status from J15 - if (sl->version.jtag_v >= 15) { - sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; - } - - if (sl->version.jtag_v >= 13) { - sl->version.flags |= STLINK_F_HAS_TRACE; - sl->max_trace_freq = STLINK_V2_MAX_TRACE_FREQUENCY; - } - } + sl->version.flags = 0; + + if (sl->version.stlink_v < 3) { + uint32_t b0 = sl->q_buf[0]; // lsb + uint32_t b1 = sl->q_buf[1]; + uint32_t b2 = sl->q_buf[2]; + uint32_t b3 = sl->q_buf[3]; + uint32_t b4 = sl->q_buf[4]; + uint32_t b5 = sl->q_buf[5]; // msb + + // b0 b1 || b2 b3 | b4 b5 + // 4b | 6b | 6b || 2B | 2B + // stlink_v | jtag_v | swim_v || st_vid | stlink_pid + + slv->stlink_v = (b0 & 0xf0) >> 4; + slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); + slv->swim_v = b1 & 0x3f; + slv->st_vid = (b3 << 8) | b2; + slv->stlink_pid = (b5 << 8) | b4; + + // ST-LINK/V1 from J11 switch to api-v2 (and support SWD) + if (slv->stlink_v == 1) { + slv->jtag_api = + slv->jtag_v > 11 ? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; } else { - // V3 uses different version format, for reference see OpenOCD source - // (that was written from docs available from ST under NDA): - // https://github.com/ntfreak/openocd/blob/a6dacdff58ef36fcdac00c53ec27f19de1fbce0d/src/jtag/drivers/stlink_usb.c#L965 - slv->stlink_v = sl->q_buf[0]; - slv->swim_v = sl->q_buf[1]; - slv->jtag_v = sl->q_buf[2]; - slv->st_vid = (uint32_t)((sl->q_buf[9] << 8) | sl->q_buf[8]); - slv->stlink_pid = (uint32_t)((sl->q_buf[11] << 8) | sl->q_buf[10]); - slv->jtag_api = STLINK_JTAG_API_V3; - /* preferred API to get last R/W status */ + slv->jtag_api = STLINK_JTAG_API_V2; + + // preferred API to get last R/W status from J15 + if (sl->version.jtag_v >= 15) { sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; - sl->version.flags |= STLINK_F_HAS_TRACE; - sl->max_trace_freq = STLINK_V3_MAX_TRACE_FREQUENCY; - } + } - return; + if (sl->version.jtag_v >= 13) { + sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V2_MAX_TRACE_FREQUENCY; + } + } + } else { + // V3 uses different version format, for reference see OpenOCD source + // (that was written from docs available from ST under NDA): + // https://github.com/ntfreak/openocd/blob/a6dacdff58ef36fcdac00c53ec27f19de1fbce0d/src/jtag/drivers/stlink_usb.c#L965 + slv->stlink_v = sl->q_buf[0]; + slv->swim_v = sl->q_buf[1]; + slv->jtag_v = sl->q_buf[2]; + slv->st_vid = (uint32_t)((sl->q_buf[9] << 8) | sl->q_buf[8]); + slv->stlink_pid = (uint32_t)((sl->q_buf[11] << 8) | sl->q_buf[10]); + slv->jtag_api = STLINK_JTAG_API_V3; + /* preferred API to get last R/W status */ + sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V3_MAX_TRACE_FREQUENCY; + } + + return; } int stlink_version(stlink_t *sl) { - DLOG("*** looking up stlink version\n"); + DLOG("*** looking up stlink version\n"); - if (sl->backend->version(sl)) { - return(-1); - } + if (sl->backend->version(sl)) { + return (-1); + } - _parse_version(sl, &sl->version); + _parse_version(sl, &sl->version); - DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, STLINK_USB_VID_ST); - DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); - DLOG("stlink version = 0x%x\n", sl->version.stlink_v); - DLOG("jtag version = 0x%x\n", sl->version.jtag_v); - DLOG("swim version = 0x%x\n", sl->version.swim_v); + DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, + STLINK_USB_VID_ST); + DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); + DLOG("stlink version = 0x%x\n", sl->version.stlink_v); + DLOG("jtag version = 0x%x\n", sl->version.jtag_v); + DLOG("swim version = 0x%x\n", sl->version.swim_v); - if (sl->version.jtag_v == 0) { - DLOG(" notice: the firmware doesn't support a jtag/swd interface\n"); - } + if (sl->version.jtag_v == 0) { + DLOG(" notice: the firmware doesn't support a jtag/swd interface\n"); + } - if (sl->version.swim_v == 0) { - DLOG(" notice: the firmware doesn't support a swim interface\n"); - } + if (sl->version.swim_v == 0) { + DLOG(" notice: the firmware doesn't support a swim interface\n"); + } - return(0); + return (0); } int stlink_target_voltage(stlink_t *sl) { - int voltage = -1; - DLOG("*** reading target voltage\n"); + int voltage = -1; + DLOG("*** reading target voltage\n"); - if (sl->backend->target_voltage != NULL) { - voltage = sl->backend->target_voltage(sl); + if (sl->backend->target_voltage != NULL) { + voltage = sl->backend->target_voltage(sl); - if (voltage != -1) { - DLOG("target voltage = %imV\n", voltage); - } else { - DLOG("error reading target voltage\n"); - } + if (voltage != -1) { + DLOG("target voltage = %imV\n", voltage); } else { - DLOG("reading voltage not supported by backend\n"); + DLOG("error reading target voltage\n"); } + } else { + DLOG("reading voltage not supported by backend\n"); + } - return(voltage); + return (voltage); } int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { - int ret; + int ret; - ret = sl->backend->read_debug32(sl, addr, data); - if (!ret) - DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); + ret = sl->backend->read_debug32(sl, addr, data); + if (!ret) + DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); - return(ret); + return (ret); } int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { - DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); - return sl->backend->write_debug32(sl, addr, data); + DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); + return sl->backend->write_debug32(sl, addr, data); } int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); + DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); - if (len % 4 != 0) { - ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return(-1); - } + if (len % 4 != 0) { + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return (-1); + } - return(sl->backend->write_mem32(sl, addr, len)); + return (sl->backend->write_mem32(sl, addr, len)); } int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_read_mem32 ***\n"); + DLOG("*** stlink_read_mem32 ***\n"); - if (len % 4 != 0) { // !!! never ever: fw gives just wrong values - ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return(-1); - } + if (len % 4 != 0) { // !!! never ever: fw gives just wrong values + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return (-1); + } - return(sl->backend->read_mem32(sl, addr, len)); + return (sl->backend->read_mem32(sl, addr, len)); } int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem8 ***\n"); + DLOG("*** stlink_write_mem8 ***\n"); - if (len > 0x40) { // !!! never ever: Writing more then 0x40 bytes gives unexpected behaviour - ELOG("Data length > 64: +%d byte.\n", len); - return(-1); - } + if (len > 0x40) { // !!! never ever: Writing more then 0x40 bytes gives + // unexpected behaviour + ELOG("Data length > 64: +%d byte.\n", len); + return (-1); + } - return(sl->backend->write_mem8(sl, addr, len)); + return (sl->backend->write_mem8(sl, addr, len)); } int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_regs ***\n"); - return(sl->backend->read_all_regs(sl, regp)); + DLOG("*** stlink_read_all_regs ***\n"); + return (sl->backend->read_all_regs(sl, regp)); } int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_unsupported_regs ***\n"); - return(sl->backend->read_all_unsupported_regs(sl, regp)); + DLOG("*** stlink_read_all_unsupported_regs ***\n"); + return (sl->backend->read_all_unsupported_regs(sl, regp)); } int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { - DLOG("*** stlink_write_reg\n"); - return(sl->backend->write_reg(sl, reg, idx)); + DLOG("*** stlink_write_reg\n"); + return (sl->backend->write_reg(sl, reg, idx)); } int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { - DLOG("*** stlink_read_reg\n"); - DLOG(" (%d) ***\n", r_idx); + DLOG("*** stlink_read_reg\n"); + DLOG(" (%d) ***\n", r_idx); - if (r_idx > 20 || r_idx < 0) { - fprintf(stderr, "Error: register index must be in [0..20]\n"); - return(-1); - } + if (r_idx > 20 || r_idx < 0) { + fprintf(stderr, "Error: register index must be in [0..20]\n"); + return (-1); + } - return(sl->backend->read_reg(sl, r_idx, regp)); + return (sl->backend->read_reg(sl, r_idx, regp)); } -int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { - int r_convert; +int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, + struct stlink_reg *regp) { + int r_convert; - DLOG("*** stlink_read_unsupported_reg\n"); - DLOG(" (%d) ***\n", r_idx); + DLOG("*** stlink_read_unsupported_reg\n"); + DLOG(" (%d) ***\n", r_idx); - /* Convert to values used by STLINK_REG_DCRSR */ - if (r_idx >= 0x1C && r_idx <= 0x1F) { // primask, basepri, faultmask, or control - r_convert = 0x14; - } else if (r_idx == 0x40) { // FPSCR - r_convert = 0x21; - } else if (r_idx >= 0x20 && r_idx < 0x40) { - r_convert = 0x40 + (r_idx - 0x20); - } else { - fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return(-1); - } + /* Convert to values used by STLINK_REG_DCRSR */ + if (r_idx >= 0x1C && + r_idx <= 0x1F) { // primask, basepri, faultmask, or control + r_convert = 0x14; + } else if (r_idx == 0x40) { // FPSCR + r_convert = 0x21; + } else if (r_idx >= 0x20 && r_idx < 0x40) { + r_convert = 0x40 + (r_idx - 0x20); + } else { + fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); + return (-1); + } - return(sl->backend->read_unsupported_reg(sl, r_convert, regp)); + return (sl->backend->read_unsupported_reg(sl, r_convert, regp)); } -int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct stlink_reg *regp) { - int r_convert; +int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, + struct stlink_reg *regp) { + int r_convert; - DLOG("*** stlink_write_unsupported_reg\n"); - DLOG(" (%d) ***\n", r_idx); + DLOG("*** stlink_write_unsupported_reg\n"); + DLOG(" (%d) ***\n", r_idx); - /* Convert to values used by STLINK_REG_DCRSR */ - if (r_idx >= 0x1C && r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ - r_convert = r_idx; // the backend function handles this - } else if (r_idx == 0x40) { // FPSCR - r_convert = 0x21; - } else if (r_idx >= 0x20 && r_idx < 0x40) { - r_convert = 0x40 + (r_idx - 0x20); - } else { - fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return(-1); - } + /* Convert to values used by STLINK_REG_DCRSR */ + if (r_idx >= 0x1C && + r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ + r_convert = r_idx; // the backend function handles this + } else if (r_idx == 0x40) { // FPSCR + r_convert = 0x21; + } else if (r_idx >= 0x20 && r_idx < 0x40) { + r_convert = 0x40 + (r_idx - 0x20); + } else { + fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); + return (-1); + } - return(sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); + return (sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); } bool stlink_is_core_halted(stlink_t *sl) { - stlink_status(sl); - return(sl->core_stat == TARGET_HALTED); + stlink_status(sl); + return (sl->core_stat == TARGET_HALTED); } int stlink_step(stlink_t *sl) { - DLOG("*** stlink_step ***\n"); - return(sl->backend->step(sl)); + DLOG("*** stlink_step ***\n"); + return (sl->backend->step(sl)); } int stlink_current_mode(stlink_t *sl) { - int mode = sl->backend->current_mode(sl); - - switch (mode) { - case STLINK_DEV_DFU_MODE: - DLOG("stlink current mode: dfu\n"); - return(mode); - case STLINK_DEV_DEBUG_MODE: - DLOG("stlink current mode: debug (jtag or swd)\n"); - return(mode); - case STLINK_DEV_MASS_MODE: - DLOG("stlink current mode: mass\n"); - return(mode); - } + int mode = sl->backend->current_mode(sl); - DLOG("stlink mode: unknown!\n"); - return(STLINK_DEV_UNKNOWN_MODE); -} + switch (mode) { + case STLINK_DEV_DFU_MODE: + DLOG("stlink current mode: dfu\n"); + return (mode); + case STLINK_DEV_DEBUG_MODE: + DLOG("stlink current mode: debug (jtag or swd)\n"); + return (mode); + case STLINK_DEV_MASS_MODE: + DLOG("stlink current mode: mass\n"); + return (mode); + } -int stlink_trace_enable(stlink_t* sl, uint32_t frequency) { - DLOG("*** stlink_trace_enable ***\n"); - return(sl->backend->trace_enable(sl, frequency)); + DLOG("stlink mode: unknown!\n"); + return (STLINK_DEV_UNKNOWN_MODE); } -int stlink_trace_disable(stlink_t* sl) { - DLOG("*** stlink_trace_disable ***\n"); - return(sl->backend->trace_disable(sl)); +int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { + DLOG("*** stlink_trace_enable ***\n"); + return (sl->backend->trace_enable(sl, frequency)); } -int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size) { - return(sl->backend->trace_read(sl, buf, size)); +int stlink_trace_disable(stlink_t *sl) { + DLOG("*** stlink_trace_disable ***\n"); + return (sl->backend->trace_disable(sl)); } +int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { + return (sl->backend->trace_read(sl, buf, size)); +} // End of delegates.... Common code below here... - - // same as above with entrypoint. void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { - stlink_write_reg(sl, addr, 15); /* pc register */ - stlink_run(sl, RUN_NORMAL); + stlink_write_reg(sl, addr, 15); /* pc register */ + stlink_run(sl, RUN_NORMAL); - while (stlink_is_core_halted(sl)) { usleep(3000000); } + while (stlink_is_core_halted(sl)) { + usleep(3000000); + } } - // this function is called by stlink_status() // do not call stlink_core_stat() directly, always use stlink_status() void stlink_core_stat(stlink_t *sl) { - switch (sl->core_stat ) { - case TARGET_RUNNING: - DLOG(" core status: running\n"); - return; - case TARGET_HALTED: - DLOG(" core status: halted\n"); - return; - case TARGET_RESET: - DLOG(" core status: reset\n"); - return; - case TARGET_DEBUG_RUNNING: - DLOG(" core status: debug running\n"); - return; - default: - DLOG(" core status: unknown\n"); - } + switch (sl->core_stat) { + case TARGET_RUNNING: + DLOG(" core status: running\n"); + return; + case TARGET_HALTED: + DLOG(" core status: halted\n"); + return; + case TARGET_RESET: + DLOG(" core status: reset\n"); + return; + case TARGET_DEBUG_RUNNING: + DLOG(" core status: debug running\n"); + return; + default: + DLOG(" core status: unknown\n"); + } } -void stlink_print_data(stlink_t * sl) { - if (sl->q_len <= 0 || sl->verbose < UDEBUG) { return; } +void stlink_print_data(stlink_t *sl) { + if (sl->q_len <= 0 || sl->verbose < UDEBUG) { + return; + } - if (sl->verbose > 2) { DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); } + if (sl->verbose > 2) { + DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); + } - for (int i = 0; i < sl->q_len; i++) { - if (i % 16 == 0) { - /* - if (sl->q_data_dir == Q_DATA_OUT) { - fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); - } else { - fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); - } - */ - } - //DLOG(" %02x", (unsigned int) sl->q_buf[i]); - fprintf(stderr, " %02x", (unsigned int) sl->q_buf[i]); + for (int i = 0; i < sl->q_len; i++) { + if (i % 16 == 0) { + /* + if (sl->q_data_dir == Q_DATA_OUT) { + fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); + } else { + fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); + } + */ } - //DLOG("\n\n"); - fprintf(stderr, "\n"); + // DLOG(" %02x", (unsigned int) sl->q_buf[i]); + fprintf(stderr, " %02x", (unsigned int)sl->q_buf[i]); + } + // DLOG("\n\n"); + fprintf(stderr, "\n"); } /* Memory mapped file */ typedef struct mapped_file { - uint8_t* base; - size_t len; + uint8_t *base; + size_t len; } mapped_file_t; -#define MAPPED_FILE_INITIALIZER { NULL, 0 } +#define MAPPED_FILE_INITIALIZER \ + { NULL, 0 } -static int map_file(mapped_file_t* mf, const char* path) { - int error = -1; - struct stat st; +static int map_file(mapped_file_t *mf, const char *path) { + int error = -1; + struct stat st; - const int fd = open(path, O_RDONLY | O_BINARY); + const int fd = open(path, O_RDONLY | O_BINARY); - if (fd == -1) { - fprintf(stderr, "open(%s) == -1\n", path); - return(-1); - } + if (fd == -1) { + fprintf(stderr, "open(%s) == -1\n", path); + return (-1); + } - if (fstat(fd, &st) == -1) { - fprintf(stderr, "fstat(%s) == -1\n", path); - goto on_error; - } + if (fstat(fd, &st) == -1) { + fprintf(stderr, "fstat(%s) == -1\n", path); + goto on_error; + } - if (sizeof(st.st_size) != sizeof(size_t)) { - // on 32 bit systems, check if there is an overflow - if (st.st_size > (off_t)INT32_MAX) { - fprintf(stderr, "mmap() size_t overflow for file %s\n", path); - goto on_error; - } + if (sizeof(st.st_size) != sizeof(size_t)) { + // on 32 bit systems, check if there is an overflow + if (st.st_size > (off_t)INT32_MAX) { + fprintf(stderr, "mmap() size_t overflow for file %s\n", path); + goto on_error; } + } - mf->base = (uint8_t*)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); + mf->base = + (uint8_t *)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); - if (mf->base == MAP_FAILED) { - fprintf(stderr, "mmap() == MAP_FAILED for file %s\n", path); - goto on_error; - } + if (mf->base == MAP_FAILED) { + fprintf(stderr, "mmap() == MAP_FAILED for file %s\n", path); + goto on_error; + } - mf->len = st.st_size; - error = 0; // success + mf->len = st.st_size; + error = 0; // success on_error: - close(fd); - return(error); + close(fd); + return (error); } -static void unmap_file(mapped_file_t * mf) { - munmap((void*)mf->base, mf->len); - mf->base = (unsigned char*)MAP_FAILED; - mf->len = 0; +static void unmap_file(mapped_file_t *mf) { + munmap((void *)mf->base, mf->len); + mf->base = (unsigned char *)MAP_FAILED; + mf->len = 0; } -/* Limit the block size to compare to 0x1800 as anything larger will stall the STLINK2 - * Maybe STLINK V1 needs smaller value! +/* Limit the block size to compare to 0x1800 as anything larger will stall the + * STLINK2 Maybe STLINK V1 needs smaller value! */ -static int check_file(stlink_t* sl, mapped_file_t* mf, stm32_addr_t addr) { - size_t off; - size_t n_cmp = sl->flash_pgsz; +static int check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { + size_t off; + size_t n_cmp = sl->flash_pgsz; - if ( n_cmp > 0x1800) { n_cmp = 0x1800; } + if (n_cmp > 0x1800) { + n_cmp = 0x1800; + } - for (off = 0; off < mf->len; off += n_cmp) { - size_t aligned_size; + for (off = 0; off < mf->len; off += n_cmp) { + size_t aligned_size; - size_t cmp_size = n_cmp; // adjust last page size + size_t cmp_size = n_cmp; // adjust last page size - if ((off + n_cmp) > mf->len) { cmp_size = mf->len - off; } + if ((off + n_cmp) > mf->len) { + cmp_size = mf->len - off; + } - aligned_size = cmp_size; + aligned_size = cmp_size; - if (aligned_size & (4 - 1)) { aligned_size = (cmp_size + 4) & ~(4 - 1); } + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } - stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); + stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); - if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { return(-1); } + if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { + return (-1); } + } - return(0); + return (0); } static void md5_calculate(mapped_file_t *mf) { - // calculate md5 checksum of given binary file - Md5Context md5Context; - MD5_HASH md5Hash; - Md5Initialise(&md5Context); - Md5Update(&md5Context, mf->base, (uint32_t)mf->len); - Md5Finalise(&md5Context, &md5Hash); - printf("md5 checksum: "); + // calculate md5 checksum of given binary file + Md5Context md5Context; + MD5_HASH md5Hash; + Md5Initialise(&md5Context); + Md5Update(&md5Context, mf->base, (uint32_t)mf->len); + Md5Finalise(&md5Context, &md5Hash); + printf("md5 checksum: "); - for (int i = 0; i < (int)sizeof(md5Hash); i++) { printf("%x", md5Hash.bytes[i]); } + for (int i = 0; i < (int)sizeof(md5Hash); i++) { + printf("%x", md5Hash.bytes[i]); + } - printf(", "); + printf(", "); } static void stlink_checksum(mapped_file_t *mp) { - /* checksum that backward compatible with official ST tools */ - uint32_t sum = 0; - uint8_t *mp_byte = (uint8_t *)mp->base; + /* checksum that backward compatible with official ST tools */ + uint32_t sum = 0; + uint8_t *mp_byte = (uint8_t *)mp->base; - for (size_t i = 0; i < mp->len; ++i) { sum += mp_byte[i]; } + for (size_t i = 0; i < mp->len; ++i) { + sum += mp_byte[i]; + } - printf("stlink checksum: 0x%08x\n", sum); + printf("stlink checksum: 0x%08x\n", sum); } static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { - unsigned int val; - // set stack - stlink_read_debug32(sl, addr, &val); - stlink_write_reg(sl, val, 13); - // set PC to the reset routine - stlink_read_debug32(sl, addr + 4, &val); - stlink_write_reg(sl, val, 15); - stlink_run(sl, RUN_NORMAL); -} - -int stlink_mwrite_sram(stlink_t * sl, uint8_t* data, uint32_t length, stm32_addr_t addr) { - // write the file in sram at addr - - int error = -1; - size_t off; - size_t len; - - // check addr range is inside the sram - if (addr < sl->sram_base) { - fprintf(stderr, "addr too low\n"); - goto on_error; - } else if ((addr + length) < addr) { - fprintf(stderr, "addr overruns\n"); - goto on_error; - } else if ((addr + length) > (sl->sram_base + sl->sram_size)) { - fprintf(stderr, "addr too high\n"); - goto on_error; - } else if (addr & 3) { - fprintf(stderr, "unaligned addr\n"); - goto on_error; - } - - len = length; - - if (len & 3) { len -= len & 3; } - - // do the copy by 1kB blocks - for (off = 0; off < len; off += 1024) { - size_t size = 1024; - - if ((off + size) > len) { size = len - off; } - - memcpy(sl->q_buf, data + off, size); - - if (size & 3) { size += 2; } // round size if needed - - stlink_write_mem32(sl, addr + (uint32_t)off, size); - } - - if (length > len) { - memcpy(sl->q_buf, data + len, length - len); - stlink_write_mem8(sl, addr + (uint32_t)len, length - len); - } - - - error = 0; // success - stlink_fwrite_finalize(sl, addr); + unsigned int val; + // set stack + stlink_read_debug32(sl, addr, &val); + stlink_write_reg(sl, val, 13); + // set PC to the reset routine + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); + stlink_run(sl, RUN_NORMAL); +} + +int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, + stm32_addr_t addr) { + // write the file in sram at addr + + int error = -1; + size_t off; + size_t len; + + // check addr range is inside the sram + if (addr < sl->sram_base) { + fprintf(stderr, "addr too low\n"); + goto on_error; + } else if ((addr + length) < addr) { + fprintf(stderr, "addr overruns\n"); + goto on_error; + } else if ((addr + length) > (sl->sram_base + sl->sram_size)) { + fprintf(stderr, "addr too high\n"); + goto on_error; + } else if (addr & 3) { + fprintf(stderr, "unaligned addr\n"); + goto on_error; + } + + len = length; + + if (len & 3) { + len -= len & 3; + } + + // do the copy by 1kB blocks + for (off = 0; off < len; off += 1024) { + size_t size = 1024; + + if ((off + size) > len) { + size = len - off; + } + + memcpy(sl->q_buf, data + off, size); + + if (size & 3) { + size += 2; + } // round size if needed + + stlink_write_mem32(sl, addr + (uint32_t)off, size); + } + + if (length > len) { + memcpy(sl->q_buf, data + len, length - len); + stlink_write_mem8(sl, addr + (uint32_t)len, length - len); + } + + error = 0; // success + stlink_fwrite_finalize(sl, addr); on_error: - return(error); + return (error); } -int stlink_fwrite_sram(stlink_t * sl, const char* path, stm32_addr_t addr) { - // write the file in sram at addr +int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { + // write the file in sram at addr - int error = -1; - size_t off; - size_t len; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; + int error = -1; + size_t off; + size_t len; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; - if (map_file(&mf, path) == -1) { - fprintf(stderr, "map_file() == -1\n"); - return(-1); - } + if (map_file(&mf, path) == -1) { + fprintf(stderr, "map_file() == -1\n"); + return (-1); + } - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); - - // check if addr range is inside the SRAM - if (addr < sl->sram_base) { - fprintf(stderr, "addr too low\n"); - goto on_error; - } else if ((addr + mf.len) < addr) { - fprintf(stderr, "addr overruns\n"); - goto on_error; - } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { - fprintf(stderr, "addr too high\n"); - goto on_error; - } else if (addr & 3) { - fprintf(stderr, "unaligned addr\n"); - goto on_error; - } + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); - len = mf.len; + // check if addr range is inside the SRAM + if (addr < sl->sram_base) { + fprintf(stderr, "addr too low\n"); + goto on_error; + } else if ((addr + mf.len) < addr) { + fprintf(stderr, "addr overruns\n"); + goto on_error; + } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { + fprintf(stderr, "addr too high\n"); + goto on_error; + } else if (addr & 3) { + fprintf(stderr, "unaligned addr\n"); + goto on_error; + } - if (len & 3) { len -= len & 3; } + len = mf.len; - // do the copy by 1kB blocks - for (off = 0; off < len; off += 1024) { - size_t size = 1024; + if (len & 3) { + len -= len & 3; + } - if ((off + size) > len) { size = len - off; } + // do the copy by 1kB blocks + for (off = 0; off < len; off += 1024) { + size_t size = 1024; - memcpy(sl->q_buf, mf.base + off, size); + if ((off + size) > len) { + size = len - off; + } - if (size & 3) { size += 2; } // round size if needed + memcpy(sl->q_buf, mf.base + off, size); - stlink_write_mem32(sl, addr + (uint32_t)off, size); - } + if (size & 3) { + size += 2; + } // round size if needed - if (mf.len > len) { - memcpy(sl->q_buf, mf.base + len, mf.len - len); - stlink_write_mem8(sl, addr + (uint32_t)len, mf.len - len); - } + stlink_write_mem32(sl, addr + (uint32_t)off, size); + } - // check the file has been written - if (check_file(sl, &mf, addr) == -1) { - fprintf(stderr, "check_file() == -1\n"); - goto on_error; - } + if (mf.len > len) { + memcpy(sl->q_buf, mf.base + len, mf.len - len); + stlink_write_mem8(sl, addr + (uint32_t)len, mf.len - len); + } - error = 0; // success - stlink_fwrite_finalize(sl, addr); + // check the file has been written + if (check_file(sl, &mf, addr) == -1) { + fprintf(stderr, "check_file() == -1\n"); + goto on_error; + } + + error = 0; // success + stlink_fwrite_finalize(sl, addr); on_error: - unmap_file(&mf); - return(error); + unmap_file(&mf); + return (error); } -typedef bool (*save_block_fn)(void* arg, uint8_t* block, ssize_t len); +typedef bool (*save_block_fn)(void *arg, uint8_t *block, ssize_t len); -static int stlink_read( - stlink_t* sl, stm32_addr_t addr, size_t size, save_block_fn fn, void* fn_arg) { +static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, + save_block_fn fn, void *fn_arg) { - int error = -1; + int error = -1; - if (size < 1) { size = sl->flash_size; } + if (size < 1) { + size = sl->flash_size; + } - if (size > sl->flash_size) { - size = sl->flash_size; - } + if (size > sl->flash_size) { + size = sl->flash_size; + } - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - for (size_t off = 0; off < size; off += cmp_size) { - size_t aligned_size; + for (size_t off = 0; off < size; off += cmp_size) { + size_t aligned_size; - // adjust last page size - if ((off + cmp_size) > size) { cmp_size = size - off; } + // adjust last page size + if ((off + cmp_size) > size) { + cmp_size = size - off; + } - aligned_size = cmp_size; + aligned_size = cmp_size; - if (aligned_size & (4 - 1)) { aligned_size = (cmp_size + 4) & ~(4 - 1); } + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } - stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); + stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); - if (!fn(fn_arg, sl->q_buf, aligned_size)) { goto on_error; } + if (!fn(fn_arg, sl->q_buf, aligned_size)) { + goto on_error; } + } - error = 0; // success + error = 0; // success on_error: - return(error); + return (error); } struct stlink_fread_worker_arg { - int fd; + int fd; }; -static bool stlink_fread_worker(void* arg, uint8_t* block, ssize_t len) { - struct stlink_fread_worker_arg* the_arg = (struct stlink_fread_worker_arg*)arg; +static bool stlink_fread_worker(void *arg, uint8_t *block, ssize_t len) { + struct stlink_fread_worker_arg *the_arg = + (struct stlink_fread_worker_arg *)arg; - if (write(the_arg->fd, block, len) != len) { - fprintf(stderr, "write() != aligned_size\n"); - return(false); - } else { - return(true); - } + if (write(the_arg->fd, block, len) != len) { + fprintf(stderr, "write() != aligned_size\n"); + return (false); + } else { + return (true); + } } struct stlink_fread_ihex_worker_arg { - FILE* file; - uint32_t addr; - uint32_t lba; - uint8_t buf[16]; - uint8_t buf_pos; + FILE *file; + uint32_t addr; + uint32_t lba; + uint8_t buf[16]; + uint8_t buf_pos; }; -static bool stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg* the_arg) { - uint32_t addr = the_arg->addr; - uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + (uint8_t)((addr & 0x00FF0000) >> 16); +static bool +stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { + uint32_t addr = the_arg->addr; + uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + + (uint8_t)((addr & 0x00FF0000) >> 16); - if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", (addr & 0xFFFF0000) >> 16, - (uint8_t)(0x100 - sum))) { - return(false); - } + if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", + (addr & 0xFFFF0000) >> 16, (uint8_t)(0x100 - sum))) { + return (false); + } - the_arg->lba = (addr & 0xFFFF0000); - return(true); + the_arg->lba = (addr & 0xFFFF0000); + return (true); } -static bool stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg* the_arg) { - uint8_t count = the_arg->buf_pos; +static bool +stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { + uint8_t count = the_arg->buf_pos; - if (count == 0) { return(true); } + if (count == 0) { + return (true); + } - uint32_t addr = the_arg->addr; + uint32_t addr = the_arg->addr; - if (the_arg->lba != (addr & 0xFFFF0000)) { // segment changed - if (!stlink_fread_ihex_newsegment(the_arg)) { - return(false); - } + if (the_arg->lba != (addr & 0xFFFF0000)) { // segment changed + if (!stlink_fread_ihex_newsegment(the_arg)) { + return (false); } + } - uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + (uint8_t)(addr & 0x000000FF); + uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + + (uint8_t)(addr & 0x000000FF); - if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) { - return(false); - } + if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) { + return (false); + } - for (uint8_t i = 0; i < count; ++i) { - uint8_t b = the_arg->buf[i]; - sum += b; + for (uint8_t i = 0; i < count; ++i) { + uint8_t b = the_arg->buf[i]; + sum += b; - if (2 != fprintf(the_arg->file, "%02X", b)) { - return(false); - } + if (2 != fprintf(the_arg->file, "%02X", b)) { + return (false); } + } - if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) { - return(false); - } + if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) { + return (false); + } - the_arg->addr += count; - the_arg->buf_pos = 0; + the_arg->addr += count; + the_arg->buf_pos = 0; - return(true); + return (true); } -static bool stlink_fread_ihex_init( - struct stlink_fread_ihex_worker_arg* the_arg, int fd, stm32_addr_t addr) { - the_arg->file = fdopen(fd, "w"); - the_arg->addr = addr; - the_arg->lba = 0; - the_arg->buf_pos = 0; +static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *the_arg, + int fd, stm32_addr_t addr) { + the_arg->file = fdopen(fd, "w"); + the_arg->addr = addr; + the_arg->lba = 0; + the_arg->buf_pos = 0; - return (the_arg->file != NULL); + return (the_arg->file != NULL); } -static bool stlink_fread_ihex_worker(void* arg, uint8_t* block, ssize_t len) { - struct stlink_fread_ihex_worker_arg* the_arg = (struct stlink_fread_ihex_worker_arg*)arg; - - for (ssize_t i = 0; i < len; ++i) { - if (the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full - if (!stlink_fread_ihex_writeline(the_arg)) { return(false); } - } +static bool stlink_fread_ihex_worker(void *arg, uint8_t *block, ssize_t len) { + struct stlink_fread_ihex_worker_arg *the_arg = + (struct stlink_fread_ihex_worker_arg *)arg; - the_arg->buf[the_arg->buf_pos++] = block[i]; + for (ssize_t i = 0; i < len; ++i) { + if (the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full + if (!stlink_fread_ihex_writeline(the_arg)) { + return (false); + } } - return(true); + the_arg->buf[the_arg->buf_pos++] = block[i]; + } + + return (true); } -static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg* the_arg) { - if (!stlink_fread_ihex_writeline(the_arg)) { return(false); } +static bool +stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { + if (!stlink_fread_ihex_writeline(the_arg)) { + return (false); + } - // FIXME: do we need the Start Linear Address? + // FIXME: do we need the Start Linear Address? - if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) { // EoF - return(false); - } + if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) { // EoF + return (false); + } - return (0 == fclose(the_arg->file)); + return (0 == fclose(the_arg->file)); } -int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size) { - // read size bytes from addr to file - ILOG("read from address %#010x size %u\n", addr, (unsigned)size); +int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, + stm32_addr_t addr, size_t size) { + // read size bytes from addr to file + ILOG("read from address %#010x size %u\n", addr, (unsigned)size); - int error; - int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); + int error; + int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); - if (fd == -1) { - fprintf(stderr, "open(%s) == -1\n", path); - return(-1); - } + if (fd == -1) { + fprintf(stderr, "open(%s) == -1\n", path); + return (-1); + } - if (is_ihex) { - struct stlink_fread_ihex_worker_arg arg; + if (is_ihex) { + struct stlink_fread_ihex_worker_arg arg; - if (stlink_fread_ihex_init(&arg, fd, addr)) { - error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); + if (stlink_fread_ihex_init(&arg, fd, addr)) { + error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); - if (!stlink_fread_ihex_finalize(&arg)) { error = -1; } - } else { - error = -1; - } + if (!stlink_fread_ihex_finalize(&arg)) { + error = -1; + } } else { - struct stlink_fread_worker_arg arg = { fd }; - error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); + error = -1; } + } else { + struct stlink_fread_worker_arg arg = {fd}; + error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); + } - close(fd); - return(error); + close(fd); + return (error); } -int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size) { - // write the buffer right after the loader - size_t chunk = size & ~0x3; - size_t rem = size & 0x3; +int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, + size_t size) { + // write the buffer right after the loader + size_t chunk = size & ~0x3; + size_t rem = size & 0x3; - if (chunk) { - memcpy(sl->q_buf, buf, chunk); - stlink_write_mem32(sl, fl->buf_addr, chunk); - } + if (chunk) { + memcpy(sl->q_buf, buf, chunk); + stlink_write_mem32(sl, fl->buf_addr, chunk); + } - if (rem) { - memcpy(sl->q_buf, buf + chunk, rem); - stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, rem); - } + if (rem) { + memcpy(sl->q_buf, buf + chunk, rem); + stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, rem); + } - return(0); + return (0); } uint32_t calculate_F4_sectornum(uint32_t flashaddr) { - uint32_t offset = 0; - flashaddr &= ~STM32_FLASH_BASE; // page now holding the actual flash address - - if (flashaddr >= 0x100000) { - offset = 12; - flashaddr -= 0x100000; - } - - if (flashaddr < 0x4000) { - return (offset + 0); - } else if (flashaddr < 0x8000) { - return(offset + 1); - } else if (flashaddr < 0xc000) { - return(offset + 2); - } else if (flashaddr < 0x10000) { - return(offset + 3); - } else if (flashaddr < 0x20000) { - return(offset + 4); - } else { - return(offset + (flashaddr / 0x20000) + 4); - } - + uint32_t offset = 0; + flashaddr &= ~STM32_FLASH_BASE; // page now holding the actual flash address + + if (flashaddr >= 0x100000) { + offset = 12; + flashaddr -= 0x100000; + } + + if (flashaddr < 0x4000) { + return (offset + 0); + } else if (flashaddr < 0x8000) { + return (offset + 1); + } else if (flashaddr < 0xc000) { + return (offset + 2); + } else if (flashaddr < 0x10000) { + return (offset + 3); + } else if (flashaddr < 0x20000) { + return (offset + 4); + } else { + return (offset + (flashaddr / 0x20000) + 4); + } } uint32_t calculate_F7_sectornum(uint32_t flashaddr) { - flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address - - if (flashaddr < 0x20000) { - return(flashaddr / 0x8000); - } else if (flashaddr < 0x40000) { - return(4); - } else { - return((flashaddr / 0x40000) + 4); - } + flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address + if (flashaddr < 0x20000) { + return (flashaddr / 0x8000); + } else if (flashaddr < 0x40000) { + return (4); + } else { + return ((flashaddr / 0x40000) + 4); + } } -uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, unsigned bank) { - flashaddr &= ~((bank==BANK_1)?STM32_FLASH_BASE:STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address - return(flashaddr / sl->flash_pgsz); +uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, + unsigned bank) { + flashaddr &= + ~((bank == BANK_1) + ? STM32_FLASH_BASE + : STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address + return (flashaddr / sl->flash_pgsz); } // returns BKER:PNB for the given page address uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { - uint32_t bker = 0; - uint32_t flashopt; - stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); - flashaddr -= STM32_FLASH_BASE; - - if (sl->chip_id == STLINK_CHIPID_STM32_L4 || - sl->chip_id == STLINK_CHIPID_STM32_L496X || - sl->chip_id == STLINK_CHIPID_STM32_L4RX) { - // this chip use dual banked flash - if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { - uint32_t banksize = (uint32_t)sl->flash_size / 2; - - if (flashaddr >= banksize) { - flashaddr -= banksize; - bker = 0x100; - } - } + uint32_t bker = 0; + uint32_t flashopt; + stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); + flashaddr -= STM32_FLASH_BASE; + + if (sl->chip_id == STLINK_CHIPID_STM32_L4 || + sl->chip_id == STLINK_CHIPID_STM32_L496X || + sl->chip_id == STLINK_CHIPID_STM32_L4RX) { + // this chip use dual banked flash + if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { + uint32_t banksize = (uint32_t)sl->flash_size / 2; + + if (flashaddr >= banksize) { + flashaddr -= banksize; + bker = 0x100; + } } + } - // For 1MB chips without the dual-bank option set, the page address will overflow - // into the BKER bit, which gives us the correct bank:page value. - return(bker | flashaddr / (uint32_t)sl->flash_pgsz); + // For 1MB chips without the dual-bank option set, the page address will + // overflow into the BKER bit, which gives us the correct bank:page value. + return (bker | flashaddr / (uint32_t)sl->flash_pgsz); } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { - if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || - (sl->chip_id == STLINK_CHIPID_STM32_F4) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || - (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || - (sl->chip_id == STLINK_CHIPID_STM32_F446) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || - (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || - (sl->chip_id == STLINK_CHIPID_STM32_F412)) { - uint32_t sector = calculate_F4_sectornum(flashaddr); - - if (sector >= 12) { sector -= 12; } - - if (sector < 4) { - sl->flash_pgsz = 0x4000; - } else if (sector < 5) { - sl->flash_pgsz = 0x10000; - } else { - sl->flash_pgsz = 0x20000; - } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { - uint32_t sector = calculate_F7_sectornum(flashaddr); + if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || + (sl->chip_id == STLINK_CHIPID_STM32_F4) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || + (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || + (sl->chip_id == STLINK_CHIPID_STM32_F446) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || + (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || + (sl->chip_id == STLINK_CHIPID_STM32_F412)) { + uint32_t sector = calculate_F4_sectornum(flashaddr); + + if (sector >= 12) { + sector -= 12; + } + + if (sector < 4) { + sl->flash_pgsz = 0x4000; + } else if (sector < 5) { + sl->flash_pgsz = 0x10000; + } else { + sl->flash_pgsz = 0x20000; + } + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || + sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { + uint32_t sector = calculate_F7_sectornum(flashaddr); - if (sector < 4) { - sl->flash_pgsz = 0x8000; - } else if (sector < 5) { - sl->flash_pgsz = 0x20000; - } else { - sl->flash_pgsz = 0x40000; - } + if (sector < 4) { + sl->flash_pgsz = 0x8000; + } else if (sector < 5) { + sl->flash_pgsz = 0x20000; + } else { + sl->flash_pgsz = 0x40000; } + } - return((uint32_t)sl->flash_pgsz); + return ((uint32_t)sl->flash_pgsz); } /** - * Erase a page of flash, assumes sl is fully populated with things like chip/core ids + * Erase a page of flash, assumes sl is fully populated with things like + * chip/core ids * @param sl stlink context * @param flashaddr an address in the flash page to erase * @return 0 on success -ve on failure */ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - // wait for ongoing op to finish - wait_flash_busy(sl); - // clear flash IO errors - clear_flash_error(sl); + // wait for ongoing op to finish + wait_flash_busy(sl); + // clear flash IO errors + clear_flash_error(sl); + + if (sl->flash_type == STLINK_FLASH_TYPE_F4 || + sl->flash_type == STLINK_FLASH_TYPE_F7 || + sl->flash_type == STLINK_FLASH_TYPE_L4) { + // unlock if locked + unlock_flash_if(sl); + + // select the page to erase + if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || + (sl->chip_id == STLINK_CHIPID_STM32_L43X) || + (sl->chip_id == STLINK_CHIPID_STM32_L46X) || + (sl->chip_id == STLINK_CHIPID_STM32_L496X) || + (sl->chip_id == STLINK_CHIPID_STM32_L4RX)) { + // calculate the actual bank+page from the address + uint32_t page = calculate_L4_page(sl, flashaddr); + + fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, + stlink_calculate_pagesize(sl, flashaddr)); + + write_flash_cr_bker_pnb(sl, page); + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || + sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { + // calculate the actual page from the address + uint32_t sector = calculate_F7_sectornum(flashaddr); - if (sl->flash_type == STLINK_FLASH_TYPE_F4 || - sl->flash_type == STLINK_FLASH_TYPE_F7 || - sl->flash_type == STLINK_FLASH_TYPE_L4) { - // unlock if locked - unlock_flash_if(sl); - - // select the page to erase - if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43X) || - (sl->chip_id == STLINK_CHIPID_STM32_L46X) || - (sl->chip_id == STLINK_CHIPID_STM32_L496X) || - (sl->chip_id == STLINK_CHIPID_STM32_L4RX)) { - // calculate the actual bank+page from the address - uint32_t page = calculate_L4_page(sl, flashaddr); - - fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", - page, stlink_calculate_pagesize(sl, flashaddr)); - - write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { - // calculate the actual page from the address - uint32_t sector = calculate_F7_sectornum(flashaddr); - - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", - sector, stlink_calculate_pagesize(sl, flashaddr)); - write_flash_cr_snb(sl, sector, BANK_1); - } else { - // calculate the actual page from the address - uint32_t sector = calculate_F4_sectornum(flashaddr); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, + stlink_calculate_pagesize(sl, flashaddr)); + write_flash_cr_snb(sl, sector, BANK_1); + } else { + // calculate the actual page from the address + uint32_t sector = calculate_F4_sectornum(flashaddr); - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", - sector, stlink_calculate_pagesize(sl, flashaddr)); + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, + stlink_calculate_pagesize(sl, flashaddr)); - // the SNB values for flash sectors in the second bank do not directly - // follow the values for the first bank on 2mb devices... - if (sector >= 12) { sector += 4; } + // the SNB values for flash sectors in the second bank do not directly + // follow the values for the first bank on 2mb devices... + if (sector >= 12) { + sector += 4; + } - write_flash_cr_snb(sl, sector, BANK_1); - } + write_flash_cr_snb(sl, sector, BANK_1); + } - set_flash_cr_strt(sl, BANK_1); // start erase operation - wait_flash_busy(sl); // wait for completion - lock_flash(sl); // TODO: fails to program if this is in + set_flash_cr_strt(sl, BANK_1); // start erase operation + wait_flash_busy(sl); // wait for completion + lock_flash(sl); // TODO: fails to program if this is in #if DEBUG_FLASH - fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); + fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); #endif - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - // check if the locks are set - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + // check if the locks are set + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if ((val & (1 << 0)) || (val & (1 << 1))) { - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); + if ((val & (1 << 0)) || (val & (1 << 1))) { + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY2); - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 0)) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return(-1); - } + if (val & (1 << 0)) { + WLOG("pecr.pelock not clear (%#x)\n", val); + return (-1); + } - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY2); - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 1)) { - WLOG("pecr.prglock not clear (%#x)\n", val); - return(-1); - } - } + if (val & (1 << 1)) { + WLOG("pecr.prglock not clear (%#x)\n", val); + return (-1); + } + } - // set pecr.{erase,prog} - val |= (1 << 9) | (1 << 3); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - // write 0 to the first word of the page to be erased - stlink_write_debug32(sl, flashaddr, 0); - - /* MP: It is better to wait for clearing the busy bit after issuing page - * erase command, even though PM0062 recommends to wait before it. - * Test shows that a few iterations is performed in the following loop - * before busy bit is cleared. - */ - wait_flash_busy(sl); - - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - uint32_t val; - unlock_flash_if(sl); - set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit - - // set the page to erase - if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - - // sec 3.10.5 - PNB[7:0] is offset by 3. - val &= ~(0xFF << 3); // Clear previously set page number (if any) - val |= ((flash_page & 0xFF) << 3); - - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { - uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. - val &= ~(0x3F << 3); - val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { - uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. - val &= ~(0x7F << 3); - val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } + // set pecr.{erase,prog} + val |= (1 << 9) | (1 << 3); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit - wait_flash_busy(sl); // wait for the 'busy' bit to clear - clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit - lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE)?BANK_1:BANK_2; - unlock_flash_if(sl); - clear_flash_cr_pg(sl, bank); // clear the pg bit - set_flash_cr_per(sl, bank); // set the page erase bit - write_flash_ar(sl, flashaddr, bank); // select the page to erase - set_flash_cr_strt(sl, bank); // start erase operation, reset by hw with busy bit - wait_flash_busy(sl); - clear_flash_cr_per(sl, bank); // clear the page erase bit - lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE)?BANK_1:BANK_2; - unlock_flash_if(sl); // unlock if locked - uint32_t sector = calculate_H7_sectornum(sl, flashaddr, bank);// calculate the actual page from the address - write_flash_cr_snb(sl, sector, bank); // select the page to erase - set_flash_cr_strt(sl, bank); // start erase operation - wait_flash_busy(sl); // wait for completion - lock_flash(sl); - } else { - WLOG("unknown coreid %x, page erase failed\n", sl->core_id); - return(-1); - } + // write 0 to the first word of the page to be erased + stlink_write_debug32(sl, flashaddr, 0); + + /* MP: It is better to wait for clearing the busy bit after issuing page + * erase command, even though PM0062 recommends to wait before it. + * Test shows that a few iterations is performed in the following loop + * before busy bit is cleared. + */ + wait_flash_busy(sl); + + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + uint32_t val; + unlock_flash_if(sl); + set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit + + // set the page to erase + if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + + // sec 3.10.5 - PNB[7:0] is offset by 3. + val &= ~(0xFF << 3); // Clear previously set page number (if any) + val |= ((flash_page & 0xFF) << 3); + + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. + val &= ~(0x3F << 3); + val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. + val &= ~(0x7F << 3); + val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } + + set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit + wait_flash_busy(sl); // wait for the 'busy' bit to clear + clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit + lock_flash(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || + sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + unlock_flash_if(sl); + clear_flash_cr_pg(sl, bank); // clear the pg bit + set_flash_cr_per(sl, bank); // set the page erase bit + write_flash_ar(sl, flashaddr, bank); // select the page to erase + set_flash_cr_strt(sl, + bank); // start erase operation, reset by hw with busy bit + wait_flash_busy(sl); + clear_flash_cr_per(sl, bank); // clear the page erase bit + lock_flash(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + unlock_flash_if(sl); // unlock if locked + uint32_t sector = calculate_H7_sectornum( + sl, flashaddr, bank); // calculate the actual page from the address + write_flash_cr_snb(sl, sector, bank); // select the page to erase + set_flash_cr_strt(sl, bank); // start erase operation + wait_flash_busy(sl); // wait for completion + lock_flash(sl); + } else { + WLOG("unknown coreid %x, page erase failed\n", sl->core_id); + return (-1); + } - return check_flash_error(sl); + return check_flash_error(sl); } int stlink_erase_flash_mass(stlink_t *sl) { - int err = 0; + int err = 0; - // TODO: User MER bit to mass-erase WB series. - if (sl->flash_type == STLINK_FLASH_TYPE_L0 || - sl->flash_type == STLINK_FLASH_TYPE_WB) { - // erase each page - int i = 0, num_pages = (int)(sl->flash_size / sl->flash_pgsz); + // TODO: User MER bit to mass-erase WB series. + if (sl->flash_type == STLINK_FLASH_TYPE_L0 || + sl->flash_type == STLINK_FLASH_TYPE_WB) { + // erase each page + int i = 0, num_pages = (int)(sl->flash_size / sl->flash_pgsz); - for (i = 0; i < num_pages; i++) { - // addr must be an addr inside the page - stm32_addr_t addr = (stm32_addr_t)sl->flash_base + i * (stm32_addr_t)sl->flash_pgsz; + for (i = 0; i < num_pages; i++) { + // addr must be an addr inside the page + stm32_addr_t addr = + (stm32_addr_t)sl->flash_base + i * (stm32_addr_t)sl->flash_pgsz; - if (stlink_erase_flash_page(sl, addr)) { - WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); - return(-1); - } + if (stlink_erase_flash_page(sl, addr)) { + WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); + return (-1); + } - fprintf(stdout, "-> Flash page at %5d/%5d erased\n", i, num_pages); - fflush(stdout); - } + fprintf(stdout, "-> Flash page at %5d/%5d erased\n", i, num_pages); + fflush(stdout); + } - fprintf(stdout, "\n"); - } else { - wait_flash_busy(sl); - clear_flash_error(sl); - unlock_flash_if(sl); - - if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_id != STLINK_CHIPID_STM32_H7AX) { - // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); - } - } + fprintf(stdout, "\n"); + } else { + wait_flash_busy(sl); + clear_flash_error(sl); + unlock_flash_if(sl); - set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit - set_flash_cr_strt(sl, BANK_1); // start erase operation, reset by hw with busy bit + if (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_id != STLINK_CHIPID_STM32_H7AX) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 - set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 - } + set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit + set_flash_cr_strt( + sl, BANK_1); // start erase operation, reset by hw with busy bit - wait_flash_busy_progress(sl); - lock_flash(sl); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 + set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 + } - // reset the mass erase bit - set_flash_cr_mer(sl, 0, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - set_flash_cr_mer(sl, 0, BANK_2); - } + wait_flash_busy_progress(sl); + lock_flash(sl); - err = check_flash_error(sl); + // reset the mass erase bit + set_flash_cr_mer(sl, 0, BANK_1); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + set_flash_cr_mer(sl, 0, BANK_2); } - return(err); + err = check_flash_error(sl); + } + + return (err); } -int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { - // check the contents of path are at addr +int stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { + // check the contents of path are at addr - int res; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; + int res; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; - if (map_file(&mf, path) == -1) { return(-1); } + if (map_file(&mf, path) == -1) { + return (-1); + } - res = check_file(sl, &mf, addr); - unmap_file(&mf); - return(res); + res = check_file(sl, &mf, addr); + unmap_file(&mf); + return (res); } /** @@ -2946,696 +3047,741 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { * @param length how much * @return 0 for success, -ve for failure */ -int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, unsigned length) { - size_t off; - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - ILOG("Starting verification of write complete\n"); +int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, + unsigned length) { + size_t off; + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; + ILOG("Starting verification of write complete\n"); - for (off = 0; off < length; off += cmp_size) { - size_t aligned_size; + for (off = 0; off < length; off += cmp_size) { + size_t aligned_size; - // adjust last page size - if ((off + cmp_size) > length) { cmp_size = length - off; } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { aligned_size = (cmp_size + 4) & ~(4 - 1); } - - stlink_read_mem32(sl, address + (uint32_t)off, aligned_size); - - if (memcmp(sl->q_buf, data + off, cmp_size)) { - ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); - return(-1); - } + // adjust last page size + if ((off + cmp_size) > length) { + cmp_size = length - off; } - ILOG("Flash written and verified! jolly good!\n"); - return(0); + aligned_size = cmp_size; -} - -int stm32l1_write_half_pages( - stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint32_t pagesize) { - unsigned int count; - unsigned int num_half_pages = len / pagesize; - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - flash_loader_t fl; - - ILOG("Starting Half page flash write for STM32L core id\n"); - - /* Flash loader initialisation */ - if (stlink_flash_loader_init(sl, &fl) == -1) { - WLOG("stlink_flash_loader_init() == -1\n"); - return(-1); + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); } - // unlock already done - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - val |= (1 << FLASH_L1_PROG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - wait_flash_busy(sl); - - for (count = 0; count < num_half_pages; count++) { - if (stlink_flash_loader_run( - sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize) == -1) { - WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", addr + count * pagesize); - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return(-1); - } + stlink_read_mem32(sl, address + (uint32_t)off, aligned_size); - // wait for sr.busy to be cleared - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are misleading - fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); - fflush(stdout); - } - - wait_flash_busy(sl); + if (memcmp(sl->q_buf, data + off, cmp_size)) { + ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); + return (-1); } + } - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~(1 << FLASH_L1_PROG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~(1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return(0); + ILOG("Flash written and verified! jolly good!\n"); + return (0); } -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - - // According to DDI0419C, Table C1-7 firstly force halt - stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | - STLINK_REG_DHCSR_C_DEBUGEN | - STLINK_REG_DHCSR_C_HALT); - // and only then disable interrupts - stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | - STLINK_REG_DHCSR_C_DEBUGEN | - STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_MASKINTS); - - // disable DMA - set_dma_state(sl, fl, 0); - - // wait for ongoing op to finish - wait_flash_busy(sl); - // Clear errors - clear_flash_error(sl); - - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { - ILOG("Starting Flash write for F2/F4/F7/L4\n"); - - // Flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return(-1); - } - - unlock_flash_if(sl); // first unlock the cr - - int voltage; - if (sl->version.stlink_v == 1) { - WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); - voltage = 3200; - } else { - voltage = stlink_target_voltage(sl); - } - - if (voltage == -1) { - ELOG("Failed to read Target voltage\n"); - return(-1); - } - - if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - // L4 does not have a byte-write mode - if (voltage < 1710) { - ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); - return(-1); - } - } else { - if (voltage > 2700) { - ILOG("enabling 32-bit flash writes\n"); - write_flash_cr_psiz(sl, 2, BANK_1); - } else { - ILOG("Target voltage (%d mV) too low for 32-bit flash, " - "using 8-bit flash writes\n", voltage); - write_flash_cr_psiz(sl, 0, BANK_1); - } - } - - // set programming mode - set_flash_cr_pg(sl, BANK_1); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - ILOG("Starting Flash write for WB/G0/G4\n"); - - unlock_flash_if(sl); // unlock flash if necessary - set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - ILOG("Starting Flash write for L0\n"); - - uint32_t val; - uint32_t flash_regs_base; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - } - - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); - - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 0)) { - ELOG("pecr.pelock not clear\n"); - return(-1); - } - - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); +int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len, uint32_t pagesize) { + unsigned int count; + unsigned int num_half_pages = len / pagesize; + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + flash_loader_t fl; - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 1)) { - ELOG("pecr.prglock not clear\n"); - return(-1); - } - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); - - // flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return(-1); - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - ILOG("Starting Flash write for H7\n"); + ILOG("Starting Half page flash write for STM32L core id\n"); - unlock_flash_if(sl); // unlock the cr - set_flash_cr_pg(sl, BANK_1); // set programming mode - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - set_flash_cr_pg(sl, BANK_2); - } - if (sl->chip_id != STLINK_CHIPID_STM32_H7AX) { - // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); - } - } - } else { - ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); - return(-1); - } + /* Flash loader initialisation */ + if (stlink_flash_loader_init(sl, &fl) == -1) { + WLOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } - return(0); -} - -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, - uint8_t* base, uint32_t len) { - size_t off; - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { - size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; - for (off = 0; off < len;) { - size_t size = len - off > buf_size ? buf_size : len - off; - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (unsigned)(addr + off)); - check_flash_error(sl); - return(-1); - } + // unlock already done + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << FLASH_L1_FPRG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - off += size; - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - for (off = 0; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } - - write_uint32((unsigned char*)&data, *(uint32_t*)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - fprintf(stdout, "\n"); - - // flash writes happen as 2 words at a time - if ((off / sizeof(uint32_t)) % 2 != 0) { - stlink_write_debug32(sl, addr + (uint32_t)off, 0); // write a single word of zeros - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - uint32_t val; - uint32_t flash_regs_base; - uint32_t pagesize; - - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - pagesize = L0_WRITE_BLOCK_SIZE; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - pagesize = L1_WRITE_BLOCK_SIZE; - } + val |= (1 << FLASH_L1_PROG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - off = 0; + wait_flash_busy(sl); - if (len > pagesize) { - if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) { - // this may happen on a blank device! - WLOG("\nwrite_half_pages failed == -1\n"); - } else { - off = (len / pagesize) * pagesize; - } - } + for (count = 0; count < num_half_pages; count++) { + if (stlink_flash_loader_run(sl, &fl, addr + count * pagesize, + base + count * pagesize, pagesize) == -1) { + WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", + addr + count * pagesize); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + return (-1); + } - // write remaining word in program memory - for ( ; off < len; off += sizeof(uint32_t)) { - uint32_t data; + // wait for sr.busy to be cleared + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading + fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); + fflush(stdout); + } - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } + wait_flash_busy(sl); + } - write_uint32((unsigned char*)&data, *(uint32_t*)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val &= ~(1 << FLASH_L1_PROG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val &= ~(1 << FLASH_L1_FPRG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + return (0); +} - // wait for sr.busy to be cleared - do { - stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - } while ((val & (1 << 0)) != 0); +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - // TODO: check redo write operation - } - fprintf(stdout, "\n"); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - int write_block_count = 0; - for (off = 0; off < len; off += sl->flash_pgsz) { - // adjust last write size - size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; - - // unlock and set programming mode - unlock_flash_if(sl); - - DLOG("Finished unlocking flash, running loader!\n"); - - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (unsigned)(addr + off)); - check_flash_error(sl); - return(-1); - } + // According to DDI0419C, Table C1-7 firstly force halt + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT); + // and only then disable interrupts + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_MASKINTS); + + // disable DMA + set_dma_state(sl, fl, 0); + + // wait for ongoing op to finish + wait_flash_busy(sl); + // Clear errors + clear_flash_error(sl); + + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + ILOG("Starting Flash write for F2/F4/F7/L4\n"); + + // Flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + + unlock_flash_if(sl); // first unlock the cr + + int voltage; + if (sl->version.stlink_v == 1) { + WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); + voltage = 3200; + } else { + voltage = stlink_target_voltage(sl); + } - lock_flash(sl); + if (voltage == -1) { + ELOG("Failed to read Target voltage\n"); + return (-1); + } - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are misleading - fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, - (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - for (off = 0; off < len;) { - // Program STM32H7x with 64-byte Flash words - size_t chunk = (len - off > 64) ? 64 : len - off; - memcpy(sl->q_buf, base + off, chunk); - stlink_write_mem32(sl, addr + (uint32_t)off, 64); - wait_flash_busy(sl); - - off += chunk; - - if (sl->verbose >= 1) { - // show progress - fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, (unsigned int)len); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } + if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + // L4 does not have a byte-write mode + if (voltage < 1710) { + ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); + return (-1); + } + } else { + if (voltage > 2700) { + ILOG("enabling 32-bit flash writes\n"); + write_flash_cr_psiz(sl, 2, BANK_1); + } else { + ILOG("Target voltage (%d mV) too low for 32-bit flash, " + "using 8-bit flash writes\n", + voltage); + write_flash_cr_psiz(sl, 0, BANK_1); + } + } + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + ILOG("Starting Flash write for WB/G0/G4\n"); + + unlock_flash_if(sl); // unlock flash if necessary + set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + ILOG("Starting Flash write for L0\n"); + + uint32_t val; + uint32_t flash_regs_base; + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || + sl->chip_id == STLINK_CHIPID_STM32_L011) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; } else { - return(-1); + flash_regs_base = STM32L_FLASH_REGS_ADDR; } - return check_flash_error(sl); -} + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY2); -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { - uint32_t dhcsr; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4) || - (sl->flash_type == STLINK_FLASH_TYPE_WB) || - (sl->flash_type == STLINK_FLASH_TYPE_G0) || - (sl->flash_type == STLINK_FLASH_TYPE_G4) || - (sl->flash_type == STLINK_FLASH_TYPE_H7)) { - - clear_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - clear_flash_cr_pg(sl, BANK_2); - } - lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - uint32_t val; - uint32_t flash_regs_base; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - } - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { + ELOG("pecr.pelock not clear\n"); + return (-1); + } + + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY2); + + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { + ELOG("pecr.prglock not clear\n"); + return (-1); + } + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); + + // flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + ILOG("Starting Flash write for H7\n"); + + unlock_flash_if(sl); // unlock the cr + set_flash_cr_pg(sl, BANK_1); // set programming mode + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + set_flash_cr_pg(sl, BANK_2); + } + if (sl->chip_id != STLINK_CHIPID_STM32_H7AX) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } + } else { + ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + return (-1); + } + + return (0); +} + +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, + stm32_addr_t addr, uint8_t *base, uint32_t len) { + size_t off; + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; + for (off = 0; off < len;) { + size_t size = len - off > buf_size ? buf_size : len - off; + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + off += size; + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } + + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } + fprintf(stdout, "\n"); - // enable interrupt - if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { - stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | - STLINK_REG_DHCSR_C_DEBUGEN | - (dhcsr&(~STLINK_REG_DHCSR_C_MASKINTS))); + // flash writes happen as 2 words at a time + if ((off / sizeof(uint32_t)) % 2 != 0) { + stlink_write_debug32(sl, addr + (uint32_t)off, + 0); // write a single word of zeros + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + uint32_t val; + uint32_t flash_regs_base; + uint32_t pagesize; + + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || + sl->chip_id == STLINK_CHIPID_STM32_L011) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; + pagesize = L0_WRITE_BLOCK_SIZE; + } else { + flash_regs_base = STM32L_FLASH_REGS_ADDR; + pagesize = L1_WRITE_BLOCK_SIZE; } - // restore DMA state - set_dma_state(sl, fl, 1); - - return(0); -} - -int stlink_write_flash( - stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len, uint8_t eraseonly) { - size_t off; - int ret; - flash_loader_t fl; - ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); - // check addr range is inside the flash - stlink_calculate_pagesize(sl, addr); - - if (addr < sl->flash_base) { - ELOG("addr too low %#x < %#x\n", addr, sl->flash_base); - return(-1); - } else if ((addr + len) < addr) { - ELOG("addr overruns\n"); - return(-1); - } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { - ELOG("addr too high\n"); - return(-1); - } else if (addr & 1) { - ELOG("unaligned addr 0x%x\n", addr); - return(-1); - } else if (len & 1) { - WLOG("unaligned len 0x%x -- padding with zero\n", len); - len += 1; - } else if (addr & (sl->flash_pgsz - 1)) { - ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " - "check page start address and compare with flash module organisation " - "in related ST reference manual of your device.\n", (unsigned)(sl->flash_pgsz)); - return(-1); + off = 0; + + if (len > pagesize) { + if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) { + // this may happen on a blank device! + WLOG("\nwrite_half_pages failed == -1\n"); + } else { + off = (size_t)(len / pagesize) * pagesize; + } } - // make sure we've loaded the context with the chip details - stlink_core_id(sl); + // write remaining word in program memory + for (; off < len; off += sizeof(uint32_t)) { + uint32_t data; - // Erase each page - int page_count = 0; + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } - for (off = 0; off < len; off += stlink_calculate_pagesize(sl, addr + (uint32_t)off)) { - // addr must be an addr inside the page - if (stlink_erase_flash_page(sl, addr + (uint32_t)off) == -1) { - ELOG("Failed to erase_flash_page(%#x) == -1\n", (unsigned)(addr + off)); - return(-1); - } + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); - ILOG("Flash page at addr: 0x%08lx erased\n", (unsigned long)(addr + off)); - page_count++; + // wait for sr.busy to be cleared + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); + + // TODO: check redo write operation } + fprintf(stdout, "\n"); + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + int write_block_count = 0; + for (off = 0; off < len; off += sl->flash_pgsz) { + // adjust last write size + size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; + + // unlock and set programming mode + unlock_flash_if(sl); + + DLOG("Finished unlocking flash, running loader!\n"); + + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + lock_flash(sl); + + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading + fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, + (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + for (off = 0; off < len;) { + // Program STM32H7x with 64-byte Flash words + size_t chunk = (len - off > 64) ? 64 : len - off; + memcpy(sl->q_buf, base + off, chunk); + stlink_write_mem32(sl, addr + (uint32_t)off, 64); + wait_flash_busy(sl); + + off += chunk; + + if (sl->verbose >= 1) { + // show progress + fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, + (unsigned int)len); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else { + return (-1); + } + + return check_flash_error(sl); +} - ILOG("Finished erasing %d pages of %u (%#x) bytes\n", - page_count, (unsigned)(sl->flash_pgsz), (unsigned)(sl->flash_pgsz)); +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { + uint32_t dhcsr; - if (eraseonly) { return(0); } + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4) || + (sl->flash_type == STLINK_FLASH_TYPE_WB) || + (sl->flash_type == STLINK_FLASH_TYPE_G0) || + (sl->flash_type == STLINK_FLASH_TYPE_G4) || + (sl->flash_type == STLINK_FLASH_TYPE_H7)) { - ret = stlink_flashloader_start(sl, &fl); - if (ret) - return ret; - ret = stlink_flashloader_write(sl, &fl, addr, base, len); - if (ret) - return ret; - ret = stlink_flashloader_stop(sl, &fl); - if (ret) - return ret; + clear_flash_cr_pg(sl, BANK_1); + if (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + clear_flash_cr_pg(sl, BANK_2); + } + lock_flash(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + uint32_t val; + uint32_t flash_regs_base; + if (sl->chip_id == STLINK_CHIPID_STM32_L0 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || + sl->chip_id == STLINK_CHIPID_STM32_L011) { + flash_regs_base = STM32L0_FLASH_REGS_ADDR; + } else { + flash_regs_base = STM32L_FLASH_REGS_ADDR; + } + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } + + // enable interrupt + if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); + } + + // restore DMA state + set_dma_state(sl, fl, 1); + + return (0); +} + +int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len, uint8_t eraseonly) { + size_t off; + int ret; + flash_loader_t fl; + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, + len, addr, addr); + // check addr range is inside the flash + stlink_calculate_pagesize(sl, addr); + + if (addr < sl->flash_base) { + ELOG("addr too low %#x < %#x\n", addr, sl->flash_base); + return (-1); + } else if ((addr + len) < addr) { + ELOG("addr overruns\n"); + return (-1); + } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { + ELOG("addr too high\n"); + return (-1); + } else if (addr & 1) { + ELOG("unaligned addr 0x%x\n", addr); + return (-1); + } else if (len & 1) { + WLOG("unaligned len 0x%x -- padding with zero\n", len); + len += 1; + } else if (addr & (sl->flash_pgsz - 1)) { + ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " + "check page start address and compare with flash module organisation " + "in related ST reference manual of your device.\n", + (unsigned)(sl->flash_pgsz)); + return (-1); + } + + // make sure we've loaded the context with the chip details + stlink_core_id(sl); + + // Erase each page + int page_count = 0; + + for (off = 0; off < len; + off += stlink_calculate_pagesize(sl, addr + (uint32_t)off)) { + // addr must be an addr inside the page + if (stlink_erase_flash_page(sl, addr + (uint32_t)off) == -1) { + ELOG("Failed to erase_flash_page(%#x) == -1\n", (unsigned)(addr + off)); + return (-1); + } + + ILOG("Flash page at addr: 0x%08lx erased\n", (unsigned long)(addr + off)); + page_count++; + } + + ILOG("Finished erasing %d pages of %u (%#x) bytes\n", page_count, + (unsigned)(sl->flash_pgsz), (unsigned)(sl->flash_pgsz)); + + if (eraseonly) { + return (0); + } + + ret = stlink_flashloader_start(sl, &fl); + if (ret) + return ret; + ret = stlink_flashloader_write(sl, &fl, addr, base, len); + if (ret) + return ret; + ret = stlink_flashloader_stop(sl, &fl); + if (ret) + return ret; - return(stlink_verify_write_flash(sl, addr, base, len)); + return (stlink_verify_write_flash(sl, addr, base, len)); } // TODO: length not checked -static uint8_t stlink_parse_hex(const char* hex) { - uint8_t d[2]; - - for (int i = 0; i < 2; ++i) { - char c = *(hex + i); - - if (c >= '0' && c <= '9') { - d[i] = c - '0'; - } else if (c >= 'A' && c <= 'F') { - d[i] = c - 'A' + 10; - } else if (c >= 'a' && c <= 'f') { - d[i] = c - 'a' + 10; - } else { - return(0); // error - } +static uint8_t stlink_parse_hex(const char *hex) { + uint8_t d[2]; + + for (int i = 0; i < 2; ++i) { + char c = *(hex + i); + + if (c >= '0' && c <= '9') { + d[i] = c - '0'; + } else if (c >= 'A' && c <= 'F') { + d[i] = c - 'A' + 10; + } else if (c >= 'a' && c <= 'f') { + d[i] = c - 'a' + 10; + } else { + return (0); // error } + } - return((d[0] << 4) | (d[1])); + return ((d[0] << 4) | (d[1])); } -int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, - uint32_t * begin) { - int res = 0; - *begin = UINT32_MAX; - uint8_t* data = NULL; - uint32_t end = 0; - bool eof_found = false; +int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, + size_t *size, uint32_t *begin) { + int res = 0; + *begin = UINT32_MAX; + uint8_t *data = NULL; + uint32_t end = 0; + bool eof_found = false; - for (int scan = 0; (res == 0) && (scan < 2); ++scan) { - // parse file two times - first to find memory range, second - to fill it - if (scan == 1) { - if (!eof_found) { - ELOG("No EoF recond\n"); - res = -1; - break; - } + for (int scan = 0; (res == 0) && (scan < 2); ++scan) { + // parse file two times - first to find memory range, second - to fill it + if (scan == 1) { + if (!eof_found) { + ELOG("No EoF recond\n"); + res = -1; + break; + } - if (*begin >= end) { - ELOG("No data found in file\n"); - res = -1; - break; - } + if (*begin >= end) { + ELOG("No data found in file\n"); + res = -1; + break; + } - *size = (end - *begin) + 1; - data = calloc(*size, 1); // use calloc to get NULL if out of memory + *size = (end - *begin) + 1; + data = calloc(*size, 1); // use calloc to get NULL if out of memory - if (!data) { - ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); - res = -1; - break; - } + if (!data) { + ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); + res = -1; + break; + } - memset(data, erased_pattern, *size); - } + memset(data, erased_pattern, *size); + } - FILE* file = fopen(path, "r"); + FILE *file = fopen(path, "r"); - if (!file) { - ELOG("Cannot open file\n"); - res = -1; - break; - } + if (!file) { + ELOG("Cannot open file\n"); + res = -1; + break; + } - uint32_t lba = 0; - char line[1 + 5 * 2 + 255 * 2 + 2]; + uint32_t lba = 0; + char line[1 + 5 * 2 + 255 * 2 + 2]; - while (fgets(line, sizeof(line), file)) { - if (line[0] == '\n' || line[0] == '\r') { continue; } // skip empty lines + while (fgets(line, sizeof(line), file)) { + if (line[0] == '\n' || line[0] == '\r') { + continue; + } // skip empty lines - if (line[0] != ':') { // no marker - wrong file format - ELOG("Wrong file format - no marker\n"); - res = -1; - break; - } + if (line[0] != ':') { // no marker - wrong file format + ELOG("Wrong file format - no marker\n"); + res = -1; + break; + } - size_t l = strlen(line); + size_t l = strlen(line); - while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { --l; } // trim EoL + while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { + --l; + } // trim EoL - if ((l < 11) || (l == (sizeof(line) - 1))) { // line too short or long - wrong file format - ELOG("Wrong file format - wrong line length\n"); - res = -1; - break; - } + if ((l < 11) || + (l == + (sizeof(line) - 1))) { // line too short or long - wrong file format + ELOG("Wrong file format - wrong line length\n"); + res = -1; + break; + } - uint8_t chksum = 0; // check sum + uint8_t chksum = 0; // check sum - for (size_t i = 1; i < l; i += 2) { chksum += stlink_parse_hex(line + i); } + for (size_t i = 1; i < l; i += 2) { + chksum += stlink_parse_hex(line + i); + } - if (chksum != 0) { - ELOG("Wrong file format - checksum mismatch\n"); - res = -1; - break; - } + if (chksum != 0) { + ELOG("Wrong file format - checksum mismatch\n"); + res = -1; + break; + } - uint8_t reclen = stlink_parse_hex(line + 1); + uint8_t reclen = stlink_parse_hex(line + 1); - if (((uint32_t)reclen + 5) * 2 + 1 != l) { - ELOG("Wrong file format - record length mismatch\n"); - res = -1; - break; - } + if (((uint32_t)reclen + 5) * 2 + 1 != l) { + ELOG("Wrong file format - record length mismatch\n"); + res = -1; + break; + } - uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | - ((uint16_t)stlink_parse_hex(line + 5)); - uint8_t rectype = stlink_parse_hex(line + 7); - - switch (rectype) { - case 0: /* Data */ - if (scan == 0) { - uint32_t b = lba + offset; - uint32_t e = b + reclen - 1; - - if (b < *begin) { *begin = b; } - - if (e > end) { end = e; } - } else { - for (uint8_t i = 0; i < reclen; ++i) { - uint8_t b = stlink_parse_hex(line + 9 + i * 2); - uint32_t addr = lba + offset + i; - - if (addr >= *begin && addr <= end) { data[addr - *begin] = b; } - } - } - break; - case 1: /* EoF */ - eof_found = true; - break; - case 2: /* Extended Segment Address, unexpected */ - res = -1; - break; - case 3: /* Start Segment Address, unexpected */ - res = -1; - break; - case 4: /* Extended Linear Address */ - if (reclen == 2) { - lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | - ((uint32_t)stlink_parse_hex(line + 11) << 16); - } else { - ELOG("Wrong file format - wrong LBA length\n"); - res = -1; - } - break; - case 5: /* Start Linear Address - expected, but ignore */ - break; - default: - ELOG("Wrong file format - unexpected record type %d\n", rectype); - res = -1; - } + uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | + ((uint16_t)stlink_parse_hex(line + 5)); + uint8_t rectype = stlink_parse_hex(line + 7); - if (res != 0) { break; } - } + switch (rectype) { + case 0: /* Data */ + if (scan == 0) { + uint32_t b = lba + offset; + uint32_t e = b + reclen - 1; - fclose(file); - } + if (b < *begin) { + *begin = b; + } - if (res == 0) { - *mem = data; - } else { - free(data); - } + if (e > end) { + end = e; + } + } else { + for (uint8_t i = 0; i < reclen; ++i) { + uint8_t b = stlink_parse_hex(line + 9 + i * 2); + uint32_t addr = lba + offset + i; - return(res); -} + if (addr >= *begin && addr <= end) { + data[addr - *begin] = b; + } + } + } + break; + case 1: /* EoF */ + eof_found = true; + break; + case 2: /* Extended Segment Address, unexpected */ + res = -1; + break; + case 3: /* Start Segment Address, unexpected */ + res = -1; + break; + case 4: /* Extended Linear Address */ + if (reclen == 2) { + lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | + ((uint32_t)stlink_parse_hex(line + 11) << 16); + } else { + ELOG("Wrong file format - wrong LBA length\n"); + res = -1; + } + break; + case 5: /* Start Linear Address - expected, but ignore */ + break; + default: + ELOG("Wrong file format - unexpected record type %d\n", rectype); + res = -1; + } -uint8_t stlink_get_erased_pattern(stlink_t *sl) { - if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - return(0x00); - } else { - return(0xff); + if (res != 0) { + break; + } } -} -int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr) { - /* Write the block in flash at addr */ - int err; - unsigned int num_empty, idx; - uint8_t erased_pattern = stlink_get_erased_pattern(sl); + fclose(file); + } - /* - * This optimisation may cause unexpected garbage data remaining. - * Therfore it is turned off by default. - */ - if (sl->opt) { - idx = (unsigned int)length; + if (res == 0) { + *mem = data; + } else { + free(data); + } + + return (res); +} - for (num_empty = 0; num_empty != length; ++num_empty) - if (data[--idx] != erased_pattern) { break; } +uint8_t stlink_get_erased_pattern(stlink_t *sl) { + if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + return (0x00); + } else { + return (0xff); + } +} + +int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, + stm32_addr_t addr) { + /* Write the block in flash at addr */ + int err; + unsigned int num_empty, idx; + uint8_t erased_pattern = stlink_get_erased_pattern(sl); + + /* + * This optimisation may cause unexpected garbage data remaining. + * Therfore it is turned off by default. + */ + if (sl->opt) { + idx = (unsigned int)length; + + for (num_empty = 0; num_empty != length; ++num_empty) + if (data[--idx] != erased_pattern) { + break; + } - num_empty -= (num_empty & 3); // Round down to words + num_empty -= (num_empty & 3); // Round down to words - if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); - } - } else { - num_empty = 0; + if (num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, + erased_pattern); } + } else { + num_empty = 0; + } - /* - * TODO: investigate a kind of weird behaviour here: - * If the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed. - */ - err = stlink_write_flash(sl, addr, data, - (num_empty == length) ? (uint32_t)length : (uint32_t)length - num_empty, - num_empty == length); - stlink_fwrite_finalize(sl, addr); - return(err); + /* + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. + */ + err = stlink_write_flash(sl, addr, data, + (num_empty == length) ? (uint32_t)length + : (uint32_t)length - num_empty, + num_empty == length); + stlink_fwrite_finalize(sl, addr); + return (err); } /** @@ -3645,49 +3791,53 @@ int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr * @param addr where to start writing * @return 0 on success, -ve on failure. */ -int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { - /* Write the file in flash at addr */ - int err; - unsigned int num_empty, idx; - uint8_t erased_pattern = stlink_get_erased_pattern(sl); - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); - return(-1); +int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { + /* Write the file in flash at addr */ + int err; + unsigned int num_empty, idx; + uint8_t erased_pattern = stlink_get_erased_pattern(sl); + mapped_file_t mf = MAPPED_FILE_INITIALIZER; + + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return (-1); + } + + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); + + if (sl->opt) { + idx = (unsigned int)mf.len; + + for (num_empty = 0; num_empty != mf.len; ++num_empty) { + if (mf.base[--idx] != erased_pattern) { + break; + } } - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); - - if (sl->opt) { - idx = (unsigned int)mf.len; + num_empty -= (num_empty & 3); // round down to words - for (num_empty = 0; num_empty != mf.len; ++num_empty) { - if (mf.base[--idx] != erased_pattern) { break; } - } - - num_empty -= (num_empty & 3); // round down to words - - if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); - } - } else { - num_empty = 0; + if (num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, + erased_pattern); } + } else { + num_empty = 0; + } - /* - * TODO: investigate a kind of weird behaviour here: - * If the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed. - */ - err = stlink_write_flash(sl, addr, mf.base, - (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty, - num_empty == mf.len); - stlink_fwrite_finalize(sl, addr); - unmap_file(&mf); - return(err); + /* + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. + */ + err = stlink_write_flash(sl, addr, mf.base, + (num_empty == mf.len) ? (uint32_t)mf.len + : (uint32_t)mf.len - num_empty, + num_empty == mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); + return (err); } /** @@ -3697,35 +3847,35 @@ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_gx( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - /* Write options bytes */ - uint32_t val; - int ret = 0; - (void)len; - uint32_t data; +static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + /* Write options bytes */ + uint32_t val; + int ret = 0; + (void)len; + uint32_t data; - clear_flash_error(sl); + clear_flash_error(sl); - write_uint32((unsigned char*)&data, *(uint32_t*)(base)); - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); - // Set Options Start bit - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + // Set Options Start bit + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - wait_flash_busy(sl); + wait_flash_busy(sl); - ret = check_flash_error(sl); + ret = check_flash_error(sl); - // Reload options - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + // Reload options + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - return(ret); + return (ret); } /** @@ -3735,36 +3885,39 @@ static int stlink_write_option_bytes_gx( * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l0( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - uint32_t flash_base = get_stm32l0_flash_base(sl); - uint32_t val; - uint32_t data; - int ret = 0; - - // Clear errors - clear_flash_error(sl); +static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t flash_base = get_stm32l0_flash_base(sl); + uint32_t val; + uint32_t data; + int ret = 0; - while (len != 0) { - write_uint32((unsigned char*)&data, *(uint32_t*)(base)); // write options bytes + // Clear errors + clear_flash_error(sl); - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, addr, data); - wait_flash_busy(sl); + while (len != 0) { + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes - if ((ret = check_flash_error(sl))) { break; } + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, addr, data); + wait_flash_busy(sl); - len -= 4; - addr += 4; - base += 4; + if ((ret = check_flash_error(sl))) { + break; } - // Reload options - stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); - val |= (1 << STM32L0_FLASH_OBL_LAUNCH); - stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); + len -= 4; + addr += 4; + base += 4; + } + + // Reload options + stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); + val |= (1 << STM32L0_FLASH_OBL_LAUNCH); + stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); - return(ret); + return (ret); } /** @@ -3774,67 +3927,67 @@ static int stlink_write_option_bytes_l0( * @param base option bytes to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l4( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { - uint32_t val; - int ret = 0; - (void)addr; - (void)len; + uint32_t val; + int ret = 0; + (void)addr; + (void)len; - // Clear errors - clear_flash_error(sl); + // Clear errors + clear_flash_error(sl); - // write options bytes - uint32_t data; - write_uint32((unsigned char*)&data, *(uint32_t*)(base)); - WLOG("Writing option bytes 0x%04x\n", data); - stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); + // write options bytes + uint32_t data; + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes 0x%04x\n", data); + stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); - // set options start bit - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + // set options start bit + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - wait_flash_busy(sl); - ret = check_flash_error(sl); + wait_flash_busy(sl); + ret = check_flash_error(sl); - // apply options bytes immediate - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + // apply options bytes immediate + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - return(ret); + return (ret); } - /** * Write option bytes * @param sl * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f4( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - uint32_t option_byte; - int ret = 0; - (void)addr; - (void)len; - - // Clear errors - clear_flash_error(sl); +static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t option_byte; + int ret = 0; + (void)addr; + (void)len; - write_uint32((unsigned char*)&option_byte, *(uint32_t*)(base)); + // Clear errors + clear_flash_error(sl); - // write option byte, ensuring we dont lock opt, and set strt bit - stlink_write_debug32(sl, FLASH_F4_OPTCR, - (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | (1 << FLASH_F4_OPTCR_START)); + write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); - wait_flash_busy(sl); - ret = check_flash_error(sl); + // write option byte, ensuring we dont lock opt, and set strt bit + stlink_write_debug32(sl, FLASH_F4_OPTCR, + (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | + (1 << FLASH_F4_OPTCR_START)); - // option bytes are reloaded at reset only, no obl. */ - return(ret); + wait_flash_busy(sl); + ret = check_flash_error(sl); + + // option bytes are reloaded at reset only, no obl. */ + return (ret); } /** @@ -3843,47 +3996,54 @@ static int stlink_write_option_bytes_f4( * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - uint32_t option_byte; - int ret = 0; +static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t option_byte; + int ret = 0; - // Clear errors - clear_flash_error(sl); + // Clear errors + clear_flash_error(sl); - ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t*) (base), addr); - write_uint32((unsigned char*) &option_byte, *(uint32_t*) (base)); - ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); + ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), + addr); + write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); + ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); - if ( addr == 0 ) { - addr = FLASH_F7_OPTCR; - ILOG("No address provided, using %#10x\n", addr); - } + if (addr == 0) { + addr = FLASH_F7_OPTCR; + ILOG("No address provided, using %#10x\n", addr); + } - if ( addr == FLASH_F7_OPTCR ) { - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F7_OPTCR, (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); - } else if ( addr == FLASH_F7_OPTCR1 ) { - // Read FLASH_F7_OPTCR - uint32_t oldvalue; - stlink_read_debug32(sl, FLASH_F7_OPTCR, &oldvalue); - /* write option byte */ - stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_byte); - // Write FLASH_F7_OPTCR lock and start address - stlink_write_debug32(sl, FLASH_F7_OPTCR, (oldvalue & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); - } else { - WLOG("WIP: write %#010x to address %#010x\n", option_byte, addr); - stlink_write_debug32(sl, addr, option_byte); - } + if (addr == FLASH_F7_OPTCR) { + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + } else if (addr == FLASH_F7_OPTCR1) { + // Read FLASH_F7_OPTCR + uint32_t oldvalue; + stlink_read_debug32(sl, FLASH_F7_OPTCR, &oldvalue); + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_byte); + // Write FLASH_F7_OPTCR lock and start address + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (oldvalue & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + } else { + WLOG("WIP: write %#010x to address %#010x\n", option_byte, addr); + stlink_write_debug32(sl, addr, option_byte); + } - wait_flash_busy(sl); + wait_flash_busy(sl); - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t*) base, addr); + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, + addr); - /* option bytes are reloaded at reset only, no obl. */ + /* option bytes are reloaded at reset only, no obl. */ - return ret; + return ret; } /** @@ -3894,64 +4054,67 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t* base, stm32_addr_ * @param len number of bytes to write (must be multiple of 4) * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_h7( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - uint32_t val; - uint32_t data; - - // Wait until previous flash option has completed - wait_flash_busy(sl); - - // Clear previous error - stlink_write_debug32(sl, FLASH_H7_OPTCCR, 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); - - while (len != 0) { - switch (addr) { - case FLASH_H7_REGS_ADDR + 0x20: // FLASH_OPTSR_PRG - case FLASH_H7_REGS_ADDR + 0x2c: // FLASH_PRAR_PRG1 - case FLASH_H7_REGS_ADDR + 0x34: // FLASH_SCAR_PRG1 - case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 - case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG - /* Write to FLASH_xxx_PRG registers */ - write_uint32((unsigned char*)&data, *(uint32_t*)(base)); // write options bytes - - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - - /* Skip if the value in the CUR register is identical */ - stlink_read_debug32(sl, addr - 4, &val); - if (val == data) { - break; - } - - /* Write new option byte values and start modification */ - stlink_write_debug32(sl, addr, data); - stlink_read_debug32(sl, FLASH_H7_OPTCR, &val); - val |= (1 << FLASH_H7_OPTCR_OPTSTART); - stlink_write_debug32(sl, FLASH_H7_OPTCR, val); - - /* Wait for the option bytes modification to complete */ - do { - stlink_read_debug32(sl, FLASH_H7_OPTSR_CUR, &val); - } while ((val & (1 << FLASH_H7_OPTSR_OPT_BUSY)) != 0); - - /* Check for errors */ - if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { - stlink_write_debug32(sl, FLASH_H7_OPTCCR, 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); - return -1; - } - break; - - default: - /* Skip non-programmable registers */ - break; - } +static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t val; + uint32_t data; + + // Wait until previous flash option has completed + wait_flash_busy(sl); + + // Clear previous error + stlink_write_debug32(sl, FLASH_H7_OPTCCR, + 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + + while (len != 0) { + switch (addr) { + case FLASH_H7_REGS_ADDR + 0x20: // FLASH_OPTSR_PRG + case FLASH_H7_REGS_ADDR + 0x2c: // FLASH_PRAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x34: // FLASH_SCAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 + case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG + /* Write to FLASH_xxx_PRG registers */ + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + + /* Skip if the value in the CUR register is identical */ + stlink_read_debug32(sl, addr - 4, &val); + if (val == data) { + break; + } + + /* Write new option byte values and start modification */ + stlink_write_debug32(sl, addr, data); + stlink_read_debug32(sl, FLASH_H7_OPTCR, &val); + val |= (1 << FLASH_H7_OPTCR_OPTSTART); + stlink_write_debug32(sl, FLASH_H7_OPTCR, val); + + /* Wait for the option bytes modification to complete */ + do { + stlink_read_debug32(sl, FLASH_H7_OPTSR_CUR, &val); + } while ((val & (1 << FLASH_H7_OPTSR_OPT_BUSY)) != 0); + + /* Check for errors */ + if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { + stlink_write_debug32(sl, FLASH_H7_OPTCCR, + 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + return -1; + } + break; - len -= 4; - addr += 4; - base += 4; + default: + /* Skip non-programmable registers */ + break; } - return 0; + len -= 4; + addr += 4; + base += 4; + } + + return 0; } /** @@ -3960,8 +4123,9 @@ static int stlink_write_option_bytes_h7( * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_Gx(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); +int stlink_read_option_control_register_Gx(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); } /** @@ -3970,8 +4134,8 @@ int stlink_read_option_control_register_Gx(stlink_t *sl, uint32_t* option_byte) * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_option_control_register_Gx(sl, option_byte); +int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_Gx(sl, option_byte); } /** @@ -3980,8 +4144,9 @@ int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t* option_byte) { * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f2(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); +int stlink_read_option_control_register_f2(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); } /** @@ -3990,8 +4155,8 @@ int stlink_read_option_control_register_f2(stlink_t *sl, uint32_t* option_byte) * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_option_control_register_f2(sl, option_byte); +int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f2(sl, option_byte); } /** @@ -4000,8 +4165,9 @@ int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte) { * @param option_byte value to read * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f4(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); +int stlink_read_option_control_register_f4(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); } /** @@ -4010,8 +4176,8 @@ int stlink_read_option_control_register_f4(stlink_t *sl, uint32_t* option_byte) * @param option_byte value to read * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { - return stlink_read_option_control_register_f4(sl, option_byte); +int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f4(sl, option_byte); } /** @@ -4020,9 +4186,10 @@ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte) { * @param option_byte value to read * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f7(stlink_t *sl, uint32_t* option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); - return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); +int stlink_read_option_control_register_f7(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); + return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); } /** @@ -4031,9 +4198,11 @@ int stlink_read_option_control_register_f7(stlink_t *sl, uint32_t* option_byte) * @param option_byte value to read * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t* option_byte) { - DLOG("@@@@ Read option control register 1 byte from %#10x\n", FLASH_F7_OPTCR1); - return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); +int stlink_read_option_control_register1_f7(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register 1 byte from %#10x\n", + FLASH_F7_OPTCR1); + return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); } /** @@ -4042,9 +4211,9 @@ int stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t* option_byte) * @param option_byte value to read * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t* option_byte) { - DLOG("@@@@ Read option byte boot address\n"); - return stlink_read_option_control_register1_f7(sl, option_byte); +int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option byte boot address\n"); + return stlink_read_option_control_register1_f7(sl, option_byte); } /** @@ -4056,18 +4225,22 @@ int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t* option_byte) { * Since multiple bytes can be read, we read and print all but one here * and then return the last one just like other devices */ -int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t* option_byte) { - int err = -1; - for (uint8_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { - err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), option_byte); - if (err == -1) { - return err; - } else { - printf("%08x\n", *option_byte); - } +int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { + int err = -1; + for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { + err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), + option_byte); + if (err == -1) { + return err; + } else { + printf("%08x\n", *option_byte); } + } - return stlink_read_debug32(sl, sl->option_base + (uint32_t) (sl->option_size / 4 - 1) * sizeof(uint32_t), option_byte); + return stlink_read_debug32( + sl, + sl->option_base + (uint32_t)(sl->option_size / 4 - 1) * sizeof(uint32_t), + option_byte); } /** @@ -4076,9 +4249,9 @@ int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t* option_byte) { * @param option_byte option value * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { - DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); - return stlink_read_debug32(sl, sl->option_base, option_byte); +int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); + return stlink_read_debug32(sl, sl->option_base, option_byte); } /** @@ -4087,7 +4260,8 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { * @param option_byte value to read * @return 0 on success, -ve on failure. */ -//int stlink_read_option_bytes_boot_add_generic(stlink_t *sl, uint32_t* option_byte) { +// int stlink_read_option_bytes_boot_add_generic(stlink_t *sl, uint32_t* +// option_byte) { // DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); // return stlink_read_debug32(sl, sl->option_base, option_byte); //} @@ -4098,9 +4272,11 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { * @param option_byte value to read * @return 0 on success, -ve on failure. */ -//int stlink_read_option_control_register_generic(stlink_t *sl, uint32_t* option_byte) { -// DLOG("@@@@ Read option control register byte from %#10x\n", sl->option_base); -// return stlink_read_debug32(sl, sl->option_base, option_byte); +// int stlink_read_option_control_register_generic(stlink_t *sl, uint32_t* +// option_byte) { +// DLOG("@@@@ Read option control register byte from %#10x\n", +// sl->option_base); return stlink_read_debug32(sl, sl->option_base, +// option_byte); //} /** @@ -4109,9 +4285,11 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { * @param option_byte value to read * @return 0 on success, -ve on failure. */ -//int stlink_read_option_control_register1_generic(stlink_t *sl, uint32_t* option_byte) { -// DLOG("@@@@ Read option control register 1 byte from %#10x\n", sl->option_base); -// return stlink_read_debug32(sl, sl->option_base, option_byte); +// int stlink_read_option_control_register1_generic(stlink_t *sl, uint32_t* +// option_byte) { +// DLOG("@@@@ Read option control register 1 byte from %#10x\n", +// sl->option_base); return stlink_read_debug32(sl, sl->option_base, +// option_byte); //} /** @@ -4120,28 +4298,28 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t* option_byte) { * @param option_byte option value * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return(-1); - } - - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: - return stlink_read_option_bytes_f2(sl, option_byte); - case STLINK_CHIPID_STM32_F4: - case STLINK_CHIPID_STM32_F446: - return stlink_read_option_bytes_f4(sl, option_byte); - case STLINK_CHIPID_STM32_F7XXXX: - return stlink_read_option_bytes_f7(sl, option_byte); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: - return stlink_read_option_bytes_Gx(sl, option_byte); - default: - return stlink_read_option_bytes_generic(sl, option_byte); - } +int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return (-1); + } + + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F2: + return stlink_read_option_bytes_f2(sl, option_byte); + case STLINK_CHIPID_STM32_F4: + case STLINK_CHIPID_STM32_F446: + return stlink_read_option_bytes_f4(sl, option_byte); + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_bytes_f7(sl, option_byte); + case STLINK_CHIPID_STM32_G0_CAT1: + case STLINK_CHIPID_STM32_G0_CAT2: + case STLINK_CHIPID_STM32_G4_CAT2: + case STLINK_CHIPID_STM32_G4_CAT3: + return stlink_read_option_bytes_Gx(sl, option_byte); + default: + return stlink_read_option_bytes_generic(sl, option_byte); + } } /** @@ -4150,20 +4328,20 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte) { * @param option_byte option value * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte) -{ - if (sl->option_base == 0) { - ELOG("Option bytes boot address read is currently not supported for connected chip\n"); - return -1; - } - - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F7XXXX: - return stlink_read_option_bytes_boot_add_f7(sl, option_byte); - default: - return -1; - //return stlink_read_option_bytes_boot_add_generic(sl, option_byte); - } +int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes boot address read is currently not supported for " + "connected chip\n"); + return -1; + } + + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_bytes_boot_add_f7(sl, option_byte); + default: + return -1; + // return stlink_read_option_bytes_boot_add_generic(sl, option_byte); + } } /** @@ -4172,20 +4350,19 @@ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte) * @param option_byte option value * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte) -{ - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; - } +int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F7XXXX: - return stlink_read_option_control_register_f7(sl, option_byte); - default: - return -1; - //return stlink_read_option_control_register_generic(sl, option_byte); - } + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_control_register_f7(sl, option_byte); + default: + return -1; + // return stlink_read_option_control_register_generic(sl, option_byte); + } } /** @@ -4194,20 +4371,20 @@ int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte) * @param option_byte option value * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte) -{ - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; - } - - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F7XXXX: - return stlink_read_option_control_register1_f7(sl, option_byte); - default: - return -1; - //return stlink_read_option_control_register1_generic(sl, option_byte); - } +int stlink_read_option_control_register1_32(stlink_t *sl, + uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F7XXXX: + return stlink_read_option_control_register1_f7(sl, option_byte); + default: + return -1; + // return stlink_read_option_control_register1_generic(sl, option_byte); + } } /** @@ -4216,10 +4393,11 @@ int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte) * @param option_byte value to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) -{ - WLOG("About to write option byte %#10x to %#10x.\n", option_byte, sl->option_base); - return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *) &option_byte, 4); +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { + WLOG("About to write option byte %#10x to %#10x.\n", option_byte, + sl->option_base); + return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, + 4); } /** @@ -4229,73 +4407,76 @@ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) * @param base option bytes to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { - int ret = -1; - - if (sl->option_base == 0) { - ELOG("Option bytes writing is currently not supported for connected chip\n"); - return(-1); - } - - - if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { - ELOG("Option bytes start address out of Option bytes range\n"); - return(-1); - } - - if (addr + len > sl->option_base + sl->option_size) { - ELOG("Option bytes data too long\n"); - return(-1); - } - - wait_flash_busy(sl); - - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return(-1); - } - - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return(-1); - } - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F4: - ret = stlink_write_option_bytes_f4(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_f7(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_L0: - ret = stlink_write_option_bytes_l0(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_L4: - ret = stlink_write_option_bytes_l4(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - ret = stlink_write_option_bytes_gx(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_H7: - ret = stlink_write_option_bytes_h7(sl, base, addr, len); - break; - default: - ELOG("Option bytes writing is currently not implemented for connected chip\n"); - break; - } - - if (ret) { - ELOG("Flash option write failed!\n"); - } else { - ILOG("Wrote %d option bytes to %#010x!\n", len, addr); - } - - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); - - return ret; +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len) { + int ret = -1; + + if (sl->option_base == 0) { + ELOG( + "Option bytes writing is currently not supported for connected chip\n"); + return (-1); + } + + if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { + ELOG("Option bytes start address out of Option bytes range\n"); + return (-1); + } + + if (addr + len > sl->option_base + sl->option_size) { + ELOG("Option bytes data too long\n"); + return (-1); + } + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return (-1); + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return (-1); + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F4: + ret = stlink_write_option_bytes_f4(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_f7(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_L0: + ret = stlink_write_option_bytes_l0(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_L4: + ret = stlink_write_option_bytes_l4(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + ret = stlink_write_option_bytes_gx(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_H7: + ret = stlink_write_option_bytes_h7(sl, base, addr, len); + break; + default: + ELOG("Option bytes writing is currently not implemented for connected " + "chip\n"); + break; + } + + if (ret) { + ELOG("Flash option write failed!\n"); + } else { + ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + } + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; } /** @@ -4304,24 +4485,30 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, ui * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option_control_register) { - int ret = 0; +static int +stlink_write_option_control_register_f7(stlink_t *sl, + uint32_t option_control_register) { + int ret = 0; - // Clear errors - clear_flash_error(sl); + // Clear errors + clear_flash_error(sl); - ILOG("Asked to write option control register 1 %#10x to %#010x.\n", option_control_register, FLASH_F7_OPTCR); + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", + option_control_register, FLASH_F7_OPTCR); - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F7_OPTCR, (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); - wait_flash_busy(sl); + wait_flash_busy(sl); - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, FLASH_F7_OPTCR); + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, + FLASH_F7_OPTCR); - return ret; + return ret; } /** @@ -4330,29 +4517,36 @@ static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t option_control_register1) { - int ret = 0; +static int +stlink_write_option_control_register1_f7(stlink_t *sl, + uint32_t option_control_register1) { + int ret = 0; - // Clear errors - clear_flash_error(sl); + // Clear errors + clear_flash_error(sl); - ILOG("Asked to write option control register 1 %#010x to %#010x.\n", option_control_register1, FLASH_F7_OPTCR1); + ILOG("Asked to write option control register 1 %#010x to %#010x.\n", + option_control_register1, FLASH_F7_OPTCR1); - /* write option byte, ensuring we dont lock opt, and set strt bit */ - uint32_t current_control_register_value; - stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); + /* write option byte, ensuring we dont lock opt, and set strt bit */ + uint32_t current_control_register_value; + stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); - /* write option byte */ - stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); - stlink_write_debug32(sl, FLASH_F7_OPTCR, (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | (1 << FLASH_F7_OPTCR_START)); + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); + stlink_write_debug32( + sl, FLASH_F7_OPTCR, + (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); - wait_flash_busy(sl); + wait_flash_busy(sl); - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, FLASH_F7_OPTCR1); + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, + FLASH_F7_OPTCR1); - return ret; + return ret; } /** @@ -4361,9 +4555,11 @@ static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t optio * @param option_byte value to write * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_add) { - ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); - return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); +static int +stlink_write_option_bytes_boot_add_f7(stlink_t *sl, + uint32_t option_byte_boot_add) { + ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); + return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); } /** @@ -4372,41 +4568,43 @@ static int stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_b * @param option bytes boot address to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add) -{ - int ret = -1; +int stlink_write_option_bytes_boot_add32(stlink_t *sl, + uint32_t option_bytes_boot_add) { + int ret = -1; - wait_flash_busy(sl); + wait_flash_busy(sl); - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; - } + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); - break; - default: - ELOG("Option bytes boot address writing is currently not implemented for connected chip\n"); - break; - } + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); + break; + default: + ELOG("Option bytes boot address writing is currently not implemented for " + "connected chip\n"); + break; + } - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); - return ret; + return ret; } /** @@ -4415,41 +4613,43 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boo * @param option bytes boot address to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_control_register) -{ - int ret = -1; +int stlink_write_option_control_register32(stlink_t *sl, + uint32_t option_control_register) { + int ret = -1; - wait_flash_busy(sl); + wait_flash_busy(sl); - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; - } + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: - ret = stlink_write_option_control_register_f7(sl, option_control_register); - break; - default: - ELOG("Option control register writing is currently not implemented for connected chip\n"); - break; - } + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_control_register_f7(sl, option_control_register); + break; + default: + ELOG("Option control register writing is currently not implemented for " + "connected chip\n"); + break; + } - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option control register %#010x!\n", option_control_register); + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register %#010x!\n", option_control_register); - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); - return ret; + return ret; } /** @@ -4458,40 +4658,43 @@ int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_control * @param option bytes boot address to write * @return 0 on success, -ve on failure. */ -int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_control_register1) -{ - int ret = -1; +int stlink_write_option_control_register1_32( + stlink_t *sl, uint32_t option_control_register1) { + int ret = -1; - wait_flash_busy(sl); + wait_flash_busy(sl); - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); - return -1; - } + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; - } + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: - ret = stlink_write_option_control_register1_f7(sl, option_control_register1); - break; - default: - ELOG("Option control register 1 writing is currently not implemented for connected chip\n"); - break; - } + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = + stlink_write_option_control_register1_f7(sl, option_control_register1); + break; + default: + ELOG("Option control register 1 writing is currently not implemented for " + "connected chip\n"); + break; + } - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); - lock_flash_option(sl); - lock_flash(sl); + lock_flash_option(sl); + lock_flash(sl); - return(ret); + return (ret); } /** @@ -4501,61 +4704,66 @@ int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_contr * @param addr of the memory mapped option bytes * @return 0 on success, -ve on failure. */ -int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr) { - /* Write the file in flash at addr */ - int err; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); - return(-1); - } +int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, + stm32_addr_t addr) { + /* Write the file in flash at addr */ + int err; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return (-1); + } - err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); - stlink_fwrite_finalize(sl, addr); - unmap_file(&mf); + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); - return(err); + err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); + + return (err); } int stlink_target_connect(stlink_t *sl, enum connect_type connect) { - uint32_t dhcsr; - - if (connect == CONNECT_UNDER_RESET) { - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + uint32_t dhcsr; - // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) - usleep(20); + if (connect == CONNECT_UNDER_RESET) { + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } - stlink_force_debug(sl); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(20); - // clear S_RESET_ST in DHCSR register - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { + stlink_enter_swd_mode(sl); + } + stlink_force_debug(sl); - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); - usleep(10000); + // clear S_RESET_ST in DHCSR register + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - // check NRST connection - dhcsr = 0; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - WLOG("NRST is not connected\n"); - } + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); + usleep(10000); - // addition soft reset for halt before the first instruction - stlink_soft_reset(sl, 1 /* halt on reset */); + // check NRST connection + dhcsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + WLOG("NRST is not connected\n"); } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } + // addition soft reset for halt before the first instruction + stlink_soft_reset(sl, 1 /* halt on reset */); + } - if (connect == CONNECT_NORMAL) { - stlink_reset(sl, RESET_AUTO); - } + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { + stlink_enter_swd_mode(sl); + } + + if (connect == CONNECT_NORMAL) { + stlink_reset(sl, RESET_AUTO); + } - return stlink_load_device_params(sl); + return stlink_load_device_params(sl); } diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index f28624475..a02c64701 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -1,556 +1,596 @@ +#include +#include +#include +#include #include #include #include #include -#include -#include -#include -#include -#include #include +#include -#include -#include #include - +#include +#include #define DEFAULT_LOGGING_LEVEL 50 #define DEBUG_LOGGING_LEVEL 100 -#define APP_RESULT_SUCCESS 0 -#define APP_RESULT_INVALID_PARAMS 1 -#define APP_RESULT_STLINK_NOT_FOUND 2 -#define APP_RESULT_STLINK_MISSING_DEVICE 3 -#define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 -#define APP_RESULT_STLINK_UNSUPPORTED_LINK 5 -#define APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY 6 -#define APP_RESULT_STLINK_STATE_ERROR 7 +#define APP_RESULT_SUCCESS 0 +#define APP_RESULT_INVALID_PARAMS 1 +#define APP_RESULT_STLINK_NOT_FOUND 2 +#define APP_RESULT_STLINK_MISSING_DEVICE 3 +#define APP_RESULT_STLINK_UNSUPPORTED_DEVICE 4 +#define APP_RESULT_STLINK_UNSUPPORTED_LINK 5 +#define APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY 6 +#define APP_RESULT_STLINK_STATE_ERROR 7 // See D4.2 of https://developer.arm.com/documentation/ddi0403/ed/ -#define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) -#define TRACE_OP_IS_LOCAL_TIME(c) (((c) & 0x0f) == 0x00 && ((c) & 0x70) != 0x00) -#define TRACE_OP_IS_EXTENSION(c) (((c) & 0x0b) == 0x08) -#define TRACE_OP_IS_GLOBAL_TIME(c) (((c) & 0xdf) == 0x94) -#define TRACE_OP_IS_SOURCE(c) (((c) & 0x03) != 0x00) -#define TRACE_OP_IS_SW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x00) -#define TRACE_OP_IS_HW_SOURCE(c) (((c) & 0x03) != 0x00 && ((c) & 0x04) == 0x04) -#define TRACE_OP_IS_TARGET_SOURCE(c) ((c) == 0x01) -#define TRACE_OP_GET_CONTINUATION(c) ((c) & 0x80) -#define TRACE_OP_GET_SOURCE_SIZE(c) ((c) & 0x03) -#define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) - +#define TRACE_OP_IS_OVERFLOW(c) ((c) == 0x70) +#define TRACE_OP_IS_LOCAL_TIME(c) (((c)&0x0f) == 0x00 && ((c)&0x70) != 0x00) +#define TRACE_OP_IS_EXTENSION(c) (((c)&0x0b) == 0x08) +#define TRACE_OP_IS_GLOBAL_TIME(c) (((c)&0xdf) == 0x94) +#define TRACE_OP_IS_SOURCE(c) (((c)&0x03) != 0x00) +#define TRACE_OP_IS_SW_SOURCE(c) (((c)&0x03) != 0x00 && ((c)&0x04) == 0x00) +#define TRACE_OP_IS_HW_SOURCE(c) (((c)&0x03) != 0x00 && ((c)&0x04) == 0x04) +#define TRACE_OP_IS_TARGET_SOURCE(c) ((c) == 0x01) +#define TRACE_OP_GET_CONTINUATION(c) ((c)&0x80) +#define TRACE_OP_GET_SOURCE_SIZE(c) ((c)&0x03) +#define TRACE_OP_GET_SW_SOURCE_ADDR(c) ((c) >> 3) typedef struct { - bool show_help; - bool show_version; - int logging_level; - uint32_t core_frequency; - uint32_t trace_frequency; - bool reset_board; - bool force; - char* serial_number; + bool show_help; + bool show_version; + int logging_level; + uint32_t core_frequency; + uint32_t trace_frequency; + bool reset_board; + bool force; + char *serial_number; } st_settings_t; - // We use a simple state machine to parse the trace data. typedef enum { - TRACE_STATE_UNKNOWN, - TRACE_STATE_IDLE, - TRACE_STATE_TARGET_SOURCE, - TRACE_STATE_SKIP_FRAME, - TRACE_STATE_SKIP_4, - TRACE_STATE_SKIP_3, - TRACE_STATE_SKIP_2, - TRACE_STATE_SKIP_1, + TRACE_STATE_UNKNOWN, + TRACE_STATE_IDLE, + TRACE_STATE_TARGET_SOURCE, + TRACE_STATE_SKIP_FRAME, + TRACE_STATE_SKIP_4, + TRACE_STATE_SKIP_3, + TRACE_STATE_SKIP_2, + TRACE_STATE_SKIP_1, } trace_state; typedef struct { - time_t start_time; - bool configuration_checked; + time_t start_time; + bool configuration_checked; - trace_state state; + trace_state state; - uint32_t count_raw_bytes; - uint32_t count_target_data; - uint32_t count_time_packets; - uint32_t count_hw_overflow; - uint32_t count_sw_overflow; - uint32_t count_error; + uint32_t count_raw_bytes; + uint32_t count_target_data; + uint32_t count_time_packets; + uint32_t count_hw_overflow; + uint32_t count_sw_overflow; + uint32_t count_error; - uint8_t unknown_opcodes[256 / 8]; - uint32_t unknown_sources; + uint8_t unknown_opcodes[256 / 8]; + uint32_t unknown_sources; } st_trace_t; - -// We use a global flag to allow communicating to the main thread from the signal handler. +// We use a global flag to allow communicating to the main thread from the +// signal handler. static bool g_abort_trace = false; -static void abort_trace() { - g_abort_trace = true; -} +static void abort_trace() { g_abort_trace = true; } #if defined(_WIN32) BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { - (void)fdwCtrlType; - abort_trace(); - return FALSE; + (void)fdwCtrlType; + abort_trace(); + return FALSE; } #endif static void usage(void) { - puts("st-trace - usage:"); - puts(" -h, --help Print this help"); - puts(" -V, --version Print this version"); - puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); - puts(" -v, --verbose Specify a generally verbose logging"); - puts(" -cXX, --clock=XX Specify the core frequency in MHz"); - puts(" -tXX, --trace=XX Specify the trace frequency in Hz"); - puts(" -n, --no-reset Do not reset board on connection"); - puts(" -sXX, --serial=XX Use a specific serial number"); - puts(" -f, --force Ignore most initialization errors"); + puts("st-trace - usage:"); + puts(" -h, --help Print this help"); + puts(" -V, --version Print this version"); + puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); + puts(" -v, --verbose Specify a generally verbose logging"); + puts(" -cXX, --clock=XX Specify the core frequency in MHz"); + puts(" -tXX, --trace=XX Specify the trace frequency in Hz"); + puts(" -n, --no-reset Do not reset board on connection"); + puts(" -sXX, --serial=XX Use a specific serial number"); + puts(" -f, --force Ignore most initialization errors"); } -bool parse_options(int argc, char** argv, st_settings_t *settings) { - - static struct option long_options[] = { - {"help", no_argument, NULL, 'h'}, - {"version", no_argument, NULL, 'V'}, - {"verbose", optional_argument, NULL, 'v'}, - {"clock", required_argument, NULL, 'c'}, - {"trace", required_argument, NULL, 't'}, - {"no-reset", no_argument, NULL, 'n'}, - {"serial", required_argument, NULL, 's'}, - {"force", no_argument, NULL, 'f'}, - {0, 0, 0, 0}, - }; - int option_index = 0; - int c; - bool error = false; - - settings->show_help = false; - settings->show_version = false; - settings->logging_level = DEFAULT_LOGGING_LEVEL; - settings->core_frequency = 0; - settings->trace_frequency = 0; - settings->reset_board = true; - settings->force = false; - settings->serial_number = NULL; - ugly_init(settings->logging_level); - - while ((c = getopt_long(argc, argv, "hVv::c:ns:f", long_options, &option_index)) != -1) { - switch (c) { - case 'h': - settings->show_help = true; - break; - case 'V': - settings->show_version = true; - break; - case 'v': - if (optarg) { - settings->logging_level = atoi(optarg); - } else { - settings->logging_level = DEBUG_LOGGING_LEVEL; - } - ugly_init(settings->logging_level); - break; - case 'c': - settings->core_frequency = atoi(optarg) * 1000000; - break; - case 't': - settings->trace_frequency = atoi(optarg); - break; - case 'n': - settings->reset_board = false; - break; - case 'f': - settings->force = true; - break; - case 's': - settings->serial_number = optarg; - break; - case '?': - error = true; - break; - default: - ELOG("Unknown command line option: '%c' (0x%02x)\n", c, c); - error = true; - break; - } +bool parse_options(int argc, char **argv, st_settings_t *settings) { + + static struct option long_options[] = { + {"help", no_argument, NULL, 'h'}, + {"version", no_argument, NULL, 'V'}, + {"verbose", optional_argument, NULL, 'v'}, + {"clock", required_argument, NULL, 'c'}, + {"trace", required_argument, NULL, 't'}, + {"no-reset", no_argument, NULL, 'n'}, + {"serial", required_argument, NULL, 's'}, + {"force", no_argument, NULL, 'f'}, + {0, 0, 0, 0}, + }; + int option_index = 0; + int c; + bool error = false; + + settings->show_help = false; + settings->show_version = false; + settings->logging_level = DEFAULT_LOGGING_LEVEL; + settings->core_frequency = 0; + settings->trace_frequency = 0; + settings->reset_board = true; + settings->force = false; + settings->serial_number = NULL; + ugly_init(settings->logging_level); + + while ((c = getopt_long(argc, argv, "hVv::c:ns:f", long_options, + &option_index)) != -1) { + switch (c) { + case 'h': + settings->show_help = true; + break; + case 'V': + settings->show_version = true; + break; + case 'v': + if (optarg) { + settings->logging_level = atoi(optarg); + } else { + settings->logging_level = DEBUG_LOGGING_LEVEL; + } + ugly_init(settings->logging_level); + break; + case 'c': + settings->core_frequency = atoi(optarg) * 1000000; + break; + case 't': + settings->trace_frequency = atoi(optarg); + break; + case 'n': + settings->reset_board = false; + break; + case 'f': + settings->force = true; + break; + case 's': + settings->serial_number = optarg; + break; + case '?': + error = true; + break; + default: + ELOG("Unknown command line option: '%c' (0x%02x)\n", c, c); + error = true; + break; } + } - if (optind < argc) { - while (optind < argc) { - ELOG("Unknown command line argument: '%s'\n", argv[optind++]); - } - error = true; + if (optind < argc) { + while (optind < argc) { + ELOG("Unknown command line argument: '%s'\n", argv[optind++]); } + error = true; + } - if (error && !settings->force) - return false; + if (error && !settings->force) + return false; - return true; + return true; } -static stlink_t* stlink_connect(const st_settings_t* settings) { - return stlink_open_usb(settings->logging_level, false, settings->serial_number, 0); +static stlink_t *stlink_connect(const st_settings_t *settings) { + return stlink_open_usb(settings->logging_level, false, + settings->serial_number, 0); } -static bool enable_trace(stlink_t* stlink, const st_settings_t* settings, uint32_t trace_frequency) { - - if (stlink_force_debug(stlink)) { - ELOG("Unable to debug device\n"); - if (!settings->force) - return false; - } - - if (settings->reset_board && stlink_reset(stlink, RESET_AUTO)) { - ELOG("Unable to reset device\n"); - if (!settings->force) - return false; - } - - - stlink_write_debug32(stlink, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | - STLINK_REG_DHCSR_C_DEBUGEN | - STLINK_REG_DHCSR_C_HALT); - stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA); - stlink_write_debug32(stlink, STLINK_REG_CM3_FP_CTRL, STLINK_REG_CM3_FP_CTRL_KEY); - stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION0, 0); - stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION1, 0); - stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION2, 0); - stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION3, 0); - stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL, 0); - stlink_write_debug32(stlink, STLINK_REG_DBGMCU_CR, STLINK_REG_DBGMCU_CR_DBG_SLEEP | - STLINK_REG_DBGMCU_CR_DBG_STOP | - STLINK_REG_DBGMCU_CR_DBG_STANDBY | - STLINK_REG_DBGMCU_CR_TRACE_IOEN | - STLINK_REG_DBGMCU_CR_TRACE_MODE_ASYNC); - - if (stlink_trace_enable(stlink, trace_frequency)) { - ELOG("Unable to turn on tracing in stlink\n"); - if (!settings->force) - return false; - } - - stlink_write_debug32(stlink, STLINK_REG_TPI_CSPSR, STLINK_REG_TPI_CSPSR_PORT_SIZE_1); - - if (settings->core_frequency) { - uint32_t prescaler = settings->core_frequency / trace_frequency - 1; - if (prescaler > STLINK_REG_TPI_ACPR_MAX) { - ELOG("Trace frequency prescaler %d out of range. Try setting a faster trace frequency.\n", prescaler); - if (!settings->force) - return false; - } - stlink_write_debug32(stlink, STLINK_REG_TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor - } - stlink_write_debug32(stlink, STLINK_REG_TPI_FFCR, STLINK_REG_TPI_FFCR_TRIG_IN); - stlink_write_debug32(stlink, STLINK_REG_TPI_SPPR, STLINK_REG_TPI_SPPR_SWO_NRZ); - stlink_write_debug32(stlink, STLINK_REG_ITM_LAR, STLINK_REG_ITM_LAR_KEY); - stlink_write_debug32(stlink, STLINK_REG_ITM_TCC, 0x00000400); // Set sync counter - stlink_write_debug32(stlink, STLINK_REG_ITM_TCR, STLINK_REG_ITM_TCR_TRACE_BUS_ID_1 | - STLINK_REG_ITM_TCR_TS_ENA | - STLINK_REG_ITM_TCR_ITM_ENA); - stlink_write_debug32(stlink, STLINK_REG_ITM_TER, STLINK_REG_ITM_TER_PORTS_ALL); - stlink_write_debug32(stlink, STLINK_REG_ITM_TPR, STLINK_REG_ITM_TPR_PORTS_ALL); - stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL, 4 * STLINK_REG_DWT_CTRL_NUM_COMP | - STLINK_REG_DWT_CTRL_CYC_TAP | - 0xF * STLINK_REG_DWT_CTRL_POST_INIT | - 0xF * STLINK_REG_DWT_CTRL_POST_PRESET | - STLINK_REG_DWT_CTRL_CYCCNT_ENA); - stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA); - - uint32_t prescaler; - stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR_MAX, &prescaler); - if (prescaler) { - uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; - uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; - ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", system_clock_speed_mhz); - } else { - WLOG("Trace Port Interface not configured. Specify the system clock with a --clock=XX command\n"); - WLOG("line option or set it in your device's clock initialization routine, such as with:\n"); - WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); +static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, + uint32_t trace_frequency) { + + if (stlink_force_debug(stlink)) { + ELOG("Unable to debug device\n"); + if (!settings->force) + return false; + } + + if (settings->reset_board && stlink_reset(stlink, RESET_AUTO)) { + ELOG("Unable to reset device\n"); + if (!settings->force) + return false; + } + + stlink_write_debug32(stlink, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT); + stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA); + stlink_write_debug32(stlink, STLINK_REG_CM3_FP_CTRL, + STLINK_REG_CM3_FP_CTRL_KEY); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION0, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION1, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION2, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION3, 0); + stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL, 0); + stlink_write_debug32( + stlink, STLINK_REG_DBGMCU_CR, + STLINK_REG_DBGMCU_CR_DBG_SLEEP | STLINK_REG_DBGMCU_CR_DBG_STOP | + STLINK_REG_DBGMCU_CR_DBG_STANDBY | STLINK_REG_DBGMCU_CR_TRACE_IOEN | + STLINK_REG_DBGMCU_CR_TRACE_MODE_ASYNC); + + if (stlink_trace_enable(stlink, trace_frequency)) { + ELOG("Unable to turn on tracing in stlink\n"); + if (!settings->force) + return false; + } + + stlink_write_debug32(stlink, STLINK_REG_TPI_CSPSR, + STLINK_REG_TPI_CSPSR_PORT_SIZE_1); + + if (settings->core_frequency) { + uint32_t prescaler = settings->core_frequency / trace_frequency - 1; + if (prescaler > STLINK_REG_TPI_ACPR_MAX) { + ELOG("Trace frequency prescaler %d out of range. Try setting a faster " + "trace frequency.\n", + prescaler); + if (!settings->force) + return false; } - ILOG("Trace frequency set to %d Hz.\n", trace_frequency); - - return true; + stlink_write_debug32(stlink, STLINK_REG_TPI_ACPR, + prescaler); // Set TPIU_ACPR clock divisor + } + stlink_write_debug32(stlink, STLINK_REG_TPI_FFCR, + STLINK_REG_TPI_FFCR_TRIG_IN); + stlink_write_debug32(stlink, STLINK_REG_TPI_SPPR, + STLINK_REG_TPI_SPPR_SWO_NRZ); + stlink_write_debug32(stlink, STLINK_REG_ITM_LAR, STLINK_REG_ITM_LAR_KEY); + stlink_write_debug32(stlink, STLINK_REG_ITM_TCC, + 0x00000400); // Set sync counter + stlink_write_debug32(stlink, STLINK_REG_ITM_TCR, + STLINK_REG_ITM_TCR_TRACE_BUS_ID_1 | + STLINK_REG_ITM_TCR_TS_ENA | + STLINK_REG_ITM_TCR_ITM_ENA); + stlink_write_debug32(stlink, STLINK_REG_ITM_TER, + STLINK_REG_ITM_TER_PORTS_ALL); + stlink_write_debug32(stlink, STLINK_REG_ITM_TPR, + STLINK_REG_ITM_TPR_PORTS_ALL); + stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL, + 4 * STLINK_REG_DWT_CTRL_NUM_COMP | + STLINK_REG_DWT_CTRL_CYC_TAP | + 0xF * STLINK_REG_DWT_CTRL_POST_INIT | + 0xF * STLINK_REG_DWT_CTRL_POST_PRESET | + STLINK_REG_DWT_CTRL_CYCCNT_ENA); + stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA); + + uint32_t prescaler; + stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR_MAX, &prescaler); + if (prescaler) { + uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; + uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; + ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", + system_clock_speed_mhz); + } else { + WLOG("Trace Port Interface not configured. Specify the system clock with " + "a --clock=XX command\n"); + WLOG("line option or set it in your device's clock initialization routine, " + "such as with:\n"); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); + } + ILOG("Trace frequency set to %d Hz.\n", trace_frequency); + + return true; } -static trace_state update_trace_idle(st_trace_t* trace, uint8_t c) { - // Handle a trace byte when we are in the idle state. - - if (TRACE_OP_IS_TARGET_SOURCE(c)) { - return TRACE_STATE_TARGET_SOURCE; - } - - if (TRACE_OP_IS_SOURCE(c)) { - uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); - if (TRACE_OP_IS_SW_SOURCE(c)) { - uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); - if (!(trace->unknown_sources & (1 << addr))) - WLOG("Unsupported source 0x%x size %d\n", addr, size); - trace->unknown_sources |= (1 << addr); - } - if (size == 1) return TRACE_STATE_SKIP_1; - if (size == 2) return TRACE_STATE_SKIP_2; - if (size == 3) return TRACE_STATE_SKIP_4; - } - - if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { - trace->count_time_packets++; - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; - } - - if (TRACE_OP_IS_EXTENSION(c)) { - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; - } - - if (TRACE_OP_IS_OVERFLOW(c)) { - trace->count_hw_overflow++; - } - - if (!(trace->unknown_opcodes[c / 8] & (1 << c % 8))) - WLOG("Unknown opcode 0x%02x\n", c); - trace->unknown_opcodes[c / 8] |= (1 << c % 8); - - trace->count_error++; - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; +static trace_state update_trace_idle(st_trace_t *trace, uint8_t c) { + // Handle a trace byte when we are in the idle state. + + if (TRACE_OP_IS_TARGET_SOURCE(c)) { + return TRACE_STATE_TARGET_SOURCE; + } + + if (TRACE_OP_IS_SOURCE(c)) { + uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); + if (TRACE_OP_IS_SW_SOURCE(c)) { + uint8_t addr = TRACE_OP_GET_SW_SOURCE_ADDR(c); + if (!(trace->unknown_sources & (1 << addr))) + WLOG("Unsupported source 0x%x size %d\n", addr, size); + trace->unknown_sources |= (1 << addr); + } + if (size == 1) + return TRACE_STATE_SKIP_1; + if (size == 2) + return TRACE_STATE_SKIP_2; + if (size == 3) + return TRACE_STATE_SKIP_4; + } + + if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { + trace->count_time_packets++; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME + : TRACE_STATE_IDLE; + } + + if (TRACE_OP_IS_EXTENSION(c)) { + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME + : TRACE_STATE_IDLE; + } + + if (TRACE_OP_IS_OVERFLOW(c)) { + trace->count_hw_overflow++; + } + + if (!(trace->unknown_opcodes[c / 8] & (1 << c % 8))) + WLOG("Unknown opcode 0x%02x\n", c); + trace->unknown_opcodes[c / 8] |= (1 << c % 8); + + trace->count_error++; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME + : TRACE_STATE_IDLE; } -static trace_state update_trace(st_trace_t* trace, uint8_t c) { - trace->count_raw_bytes++; +static trace_state update_trace(st_trace_t *trace, uint8_t c) { + trace->count_raw_bytes++; - // Parse the input using a state machine. + // Parse the input using a state machine. - if (trace->state == TRACE_STATE_UNKNOWN) { - if (TRACE_OP_IS_TARGET_SOURCE(c) || TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) - trace->state = TRACE_STATE_IDLE; - } + if (trace->state == TRACE_STATE_UNKNOWN) { + if (TRACE_OP_IS_TARGET_SOURCE(c) || TRACE_OP_IS_LOCAL_TIME(c) || + TRACE_OP_IS_GLOBAL_TIME(c)) + trace->state = TRACE_STATE_IDLE; + } - switch (trace->state) - { - case TRACE_STATE_IDLE: - return update_trace_idle(trace, c); + switch (trace->state) { + case TRACE_STATE_IDLE: + return update_trace_idle(trace, c); - case TRACE_STATE_TARGET_SOURCE: - putchar(c); - if (c == '\n') - fflush(stdout); - trace->count_target_data++; - return TRACE_STATE_IDLE; + case TRACE_STATE_TARGET_SOURCE: + putchar(c); + if (c == '\n') + fflush(stdout); + trace->count_target_data++; + return TRACE_STATE_IDLE; - case TRACE_STATE_SKIP_FRAME: - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; + case TRACE_STATE_SKIP_FRAME: + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME + : TRACE_STATE_IDLE; - case TRACE_STATE_SKIP_4: - return TRACE_STATE_SKIP_3; + case TRACE_STATE_SKIP_4: + return TRACE_STATE_SKIP_3; - case TRACE_STATE_SKIP_3: - return TRACE_STATE_SKIP_2; + case TRACE_STATE_SKIP_3: + return TRACE_STATE_SKIP_2; - case TRACE_STATE_SKIP_2: - return TRACE_STATE_SKIP_1; + case TRACE_STATE_SKIP_2: + return TRACE_STATE_SKIP_1; - case TRACE_STATE_SKIP_1: - return TRACE_STATE_IDLE; + case TRACE_STATE_SKIP_1: + return TRACE_STATE_IDLE; - case TRACE_STATE_UNKNOWN: - return TRACE_STATE_UNKNOWN; + case TRACE_STATE_UNKNOWN: + return TRACE_STATE_UNKNOWN; - default: - ELOG("Invalid state %d. This should never happen\n", trace->state); - return TRACE_STATE_IDLE; - } + default: + ELOG("Invalid state %d. This should never happen\n", trace->state); + return TRACE_STATE_IDLE; + } } -static bool read_trace(stlink_t* stlink, st_trace_t* trace) { - uint8_t buffer[STLINK_TRACE_BUF_LEN]; - int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); - - if (length < 0) { - ELOG("Error reading trace (%d)\n", length); - return false; - } - - if (length == 0) { - usleep(100); - return true; - } - - if (length == sizeof(buffer)) { - if (trace->count_sw_overflow++) - DLOG("Buffer overflow.\n"); - else - WLOG("Buffer overflow. Try using a slower trace frequency.\n"); - trace->state = TRACE_STATE_UNKNOWN; - } +static bool read_trace(stlink_t *stlink, st_trace_t *trace) { + uint8_t buffer[STLINK_TRACE_BUF_LEN]; + int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); - for (int i = 0; i < length; i++) { - trace->state = update_trace(trace, buffer[i]); - } + if (length < 0) { + ELOG("Error reading trace (%d)\n", length); + return false; + } + if (length == 0) { + usleep(100); return true; -} - -static void check_for_configuration_error(stlink_t* stlink, st_trace_t* trace, uint32_t trace_frequency) { - // Only check configuration one time after the first 10 seconds of running. - time_t elapsed_time_s = time(NULL) - trace->start_time; - if (trace->configuration_checked || elapsed_time_s < 10) { - return; - } - trace->configuration_checked = true; + } - // Simple huristic to determine if we are configured poorly. - bool error_no_data = (trace->count_raw_bytes < 100); - bool error_low_data = (trace->count_time_packets < 10 && trace->count_target_data < 1000); - bool error_bad_data = (trace->count_error > 1 || trace->unknown_sources > 0); - bool error_dropped_data = (trace->count_sw_overflow > 0); + if (length == sizeof(buffer)) { + if (trace->count_sw_overflow++) + DLOG("Buffer overflow.\n"); + else + WLOG("Buffer overflow. Try using a slower trace frequency.\n"); + trace->state = TRACE_STATE_UNKNOWN; + } - if (!error_no_data && !error_low_data && !error_bad_data && !error_dropped_data) - return; - - WLOG("****\n"); - WLOG("We do not appear to be retrieving data from the stlink correctly.\n"); - - if (error_dropped_data) { - WLOG("Try setting a slower trace frequency with the --trace=%d command line option.\n", trace_frequency / 2); - } + for (int i = 0; i < length; i++) { + trace->state = update_trace(trace, buffer[i]); + } - if (error_no_data || error_low_data || error_bad_data) { - uint32_t prescaler; - stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR, &prescaler); - if (prescaler) { - uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; - uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; - WLOG("Verify the system clock is running at %d MHz.\n", system_clock_speed_mhz); - } - WLOG("Try specifying the system clock with the --clock=XX command line option.\n"); - WLOG("Try setting the trace speed in your device's clock initialization routine:\n"); - WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); - } + return true; +} - WLOG("Diagnostic Information:\n"); - WLOG("Raw Bytes: %d\n", trace->count_raw_bytes); - WLOG("Target Data: %d\n", trace->count_target_data); - WLOG("Time Packets: %d\n", trace->count_time_packets); - WLOG("Hardware Overflow Count: %d\n", trace->count_hw_overflow); - WLOG("Software Overflow Count: %d\n", trace->count_sw_overflow); - WLOG("Errors: %d\n", trace->count_error); - - char buffer[1024]; - memset(buffer, 0, sizeof(buffer)); - uint32_t offset = 0; - for (uint32_t i = 0; i <= 0xFF; i++) - if (trace->unknown_opcodes[i / 8] & (1 << i % 8)) - offset += snprintf(buffer + offset, sizeof(buffer) - offset, "%02x, ", i); - WLOG("Unknown Opcodes: %s\n", buffer); - - memset(buffer, 0, sizeof(buffer)); - offset = 0; - for (uint32_t i = 0; i < 32; i++) - if (trace->unknown_sources & (1 << i)) - offset += snprintf(buffer + offset, sizeof(buffer) - offset, "%d, ", i); - WLOG("Unknown Sources: %s\n", buffer); - - WLOG("Chip ID: 0x%04x\n", stlink->chip_id); - WLOG("****\n"); +static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, + uint32_t trace_frequency) { + // Only check configuration one time after the first 10 seconds of running. + time_t elapsed_time_s = time(NULL) - trace->start_time; + if (trace->configuration_checked || elapsed_time_s < 10) { + return; + } + trace->configuration_checked = true; + + // Simple huristic to determine if we are configured poorly. + bool error_no_data = (trace->count_raw_bytes < 100); + bool error_low_data = + (trace->count_time_packets < 10 && trace->count_target_data < 1000); + bool error_bad_data = (trace->count_error > 1 || trace->unknown_sources > 0); + bool error_dropped_data = (trace->count_sw_overflow > 0); + + if (!error_no_data && !error_low_data && !error_bad_data && + !error_dropped_data) + return; + + WLOG("****\n"); + WLOG("We do not appear to be retrieving data from the stlink correctly.\n"); + + if (error_dropped_data) { + WLOG("Try setting a slower trace frequency with the --trace=%d command " + "line option.\n", + trace_frequency / 2); + } + + if (error_no_data || error_low_data || error_bad_data) { + uint32_t prescaler; + stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR, &prescaler); + if (prescaler) { + uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; + uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; + WLOG("Verify the system clock is running at %d MHz.\n", + system_clock_speed_mhz); + } + WLOG("Try specifying the system clock with the --clock=XX command line " + "option.\n"); + WLOG("Try setting the trace speed in your device's clock initialization " + "routine:\n"); + WLOG(" TPI->ACPR = HAL_RCC_GetHCLKFreq() / %d - 1;\n", trace_frequency); + } + + WLOG("Diagnostic Information:\n"); + WLOG("Raw Bytes: %d\n", trace->count_raw_bytes); + WLOG("Target Data: %d\n", trace->count_target_data); + WLOG("Time Packets: %d\n", trace->count_time_packets); + WLOG("Hardware Overflow Count: %d\n", trace->count_hw_overflow); + WLOG("Software Overflow Count: %d\n", trace->count_sw_overflow); + WLOG("Errors: %d\n", trace->count_error); + + char buffer[1024]; + memset(buffer, 0, sizeof(buffer)); + uint32_t offset = 0; + for (uint32_t i = 0; i <= 0xFF; i++) + if (trace->unknown_opcodes[i / 8] & (1 << i % 8)) { + uint32_t n = + snprintf(buffer + offset, sizeof(buffer) - offset, "%02x, ", i); + if (n >= sizeof(buffer) - offset) { + break; + } + offset += n; + } + WLOG("Unknown Opcodes: %s\n", buffer); + + memset(buffer, 0, sizeof(buffer)); + offset = 0; + for (uint32_t i = 0; i < 32; i++) + if (trace->unknown_sources & (1 << i)) { + uint32_t n = + snprintf(buffer + offset, sizeof(buffer) - offset, "%d, ", i); + if (n >= sizeof(buffer) - offset) { + break; + } + offset += n; + } + WLOG("Unknown Sources: %s\n", buffer); + + WLOG("Chip ID: 0x%04x\n", stlink->chip_id); + WLOG("****\n"); } -int main(int argc, char** argv) -{ +int main(int argc, char **argv) { #if defined(_WIN32) - SetConsoleCtrlHandler((PHANDLER_ROUTINE)CtrlHandler, TRUE); + SetConsoleCtrlHandler((PHANDLER_ROUTINE)CtrlHandler, TRUE); #else - signal(SIGINT, &abort_trace); - signal(SIGTERM, &abort_trace); - signal(SIGSEGV, &abort_trace); - signal(SIGPIPE, &abort_trace); + signal(SIGINT, &abort_trace); + signal(SIGTERM, &abort_trace); + signal(SIGSEGV, &abort_trace); + signal(SIGPIPE, &abort_trace); #endif + st_settings_t settings; + if (!parse_options(argc, argv, &settings)) { + usage(); + return APP_RESULT_INVALID_PARAMS; + } + + DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); + DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); + DLOG("logging_level = %d\n", settings.logging_level); + DLOG("core_frequency = %d Hz\n", settings.core_frequency); + DLOG("trace_frequency = %d Hz\n", settings.trace_frequency); + DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); + DLOG("force = %s\n", settings.force ? "true" : "false"); + DLOG("serial_number = %s\n", + settings.serial_number ? settings.serial_number : "any"); + + if (settings.show_help) { + usage(); + return APP_RESULT_SUCCESS; + } - st_settings_t settings; - if (!parse_options(argc, argv, &settings)) { - usage(); - return APP_RESULT_INVALID_PARAMS; - } - - DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); - DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); - DLOG("logging_level = %d\n", settings.logging_level); - DLOG("core_frequency = %d Hz\n", settings.core_frequency); - DLOG("trace_frequency = %d Hz\n", settings.trace_frequency); - DLOG("reset_board = %s\n", settings.reset_board ? "true" : "false"); - DLOG("force = %s\n", settings.force ? "true" : "false"); - DLOG("serial_number = %s\n", settings.serial_number ? settings.serial_number : "any"); - - if (settings.show_help) { - usage(); - return APP_RESULT_SUCCESS; - } - - if (settings.show_version) { - printf("v%s\n", STLINK_VERSION); - return APP_RESULT_SUCCESS; - } - - stlink_t* stlink = stlink_connect(&settings); - if (!stlink) { - ELOG("Unable to locate an stlink\n"); - return APP_RESULT_STLINK_NOT_FOUND; - } - - stlink->verbose = settings.logging_level; - - if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { - ELOG("Your stlink is not connected to a device\n"); - if (!settings.force) - return APP_RESULT_STLINK_MISSING_DEVICE; - } - - if (!(stlink->version.flags & STLINK_F_HAS_TRACE)) { - ELOG("Your stlink does not support tracing\n"); - if (!settings.force) - return APP_RESULT_STLINK_UNSUPPORTED_LINK; - } - - if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { - const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); - ELOG("We do not support SWO output for device '%s'\n", params->description); - if (!settings.force) - return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; - } - - uint32_t trace_frequency = settings.trace_frequency; - if (!trace_frequency) - trace_frequency = STLINK_DEFAULT_TRACE_FREQUENCY; - if (trace_frequency > stlink->max_trace_freq) { - ELOG("Invalid trace frequency %d (max %d)\n", trace_frequency, stlink->max_trace_freq); - if (!settings.force) - return APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY; - } - - if (!enable_trace(stlink, &settings, trace_frequency)) { - ELOG("Unable to enable trace mode\n"); - if (!settings.force) - return APP_RESULT_STLINK_STATE_ERROR; - } - - ILOG("Reading Trace\n"); - st_trace_t trace; - memset(&trace, 0, sizeof(trace)); - trace.start_time = time(NULL); - - if (stlink_run(stlink, RUN_NORMAL)) { - ELOG("Unable to run device\n"); - if (!settings.force) - return APP_RESULT_STLINK_STATE_ERROR; - } - - while (!g_abort_trace && read_trace(stlink, &trace)) { - check_for_configuration_error(stlink, &trace, trace_frequency); - } - - stlink_trace_disable(stlink); - stlink_close(stlink); - + if (settings.show_version) { + printf("v%s\n", STLINK_VERSION); return APP_RESULT_SUCCESS; + } + + stlink_t *stlink = stlink_connect(&settings); + if (!stlink) { + ELOG("Unable to locate an stlink\n"); + return APP_RESULT_STLINK_NOT_FOUND; + } + + stlink->verbose = settings.logging_level; + + if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { + ELOG("Your stlink is not connected to a device\n"); + if (!settings.force) + return APP_RESULT_STLINK_MISSING_DEVICE; + } + + if (!(stlink->version.flags & STLINK_F_HAS_TRACE)) { + ELOG("Your stlink does not support tracing\n"); + if (!settings.force) + return APP_RESULT_STLINK_UNSUPPORTED_LINK; + } + + if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { + const struct stlink_chipid_params *params = + stlink_chipid_get_params(stlink->chip_id); + ELOG("We do not support SWO output for device '%s'\n", params->description); + if (!settings.force) + return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; + } + + uint32_t trace_frequency = settings.trace_frequency; + if (!trace_frequency) + trace_frequency = STLINK_DEFAULT_TRACE_FREQUENCY; + if (trace_frequency > stlink->max_trace_freq) { + ELOG("Invalid trace frequency %d (max %d)\n", trace_frequency, + stlink->max_trace_freq); + if (!settings.force) + return APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY; + } + + if (!enable_trace(stlink, &settings, trace_frequency)) { + ELOG("Unable to enable trace mode\n"); + if (!settings.force) + return APP_RESULT_STLINK_STATE_ERROR; + } + + ILOG("Reading Trace\n"); + st_trace_t trace; + memset(&trace, 0, sizeof(trace)); + trace.start_time = time(NULL); + + if (stlink_run(stlink, RUN_NORMAL)) { + ELOG("Unable to run device\n"); + if (!settings.force) + return APP_RESULT_STLINK_STATE_ERROR; + } + + while (!g_abort_trace && read_trace(stlink, &trace)) { + check_for_configuration_error(stlink, &trace, trace_frequency); + } + + stlink_trace_disable(stlink); + stlink_close(stlink); + + return APP_RESULT_SUCCESS; } diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index ce0a2baab..87978230d 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -1,12 +1,13 @@ /* * UglyLogging * - * Slow, yet another wheel reinvented, but enough to make the rest of our code pretty enough. + * Slow, yet another wheel reinvented, but enough to make the rest of our code + * pretty enough. */ +#include #include #include #include -#include #include #include "logging.h" @@ -14,77 +15,89 @@ static int max_level = UDEBUG; int ugly_init(int maximum_threshold) { - max_level = maximum_threshold; - return(0); + max_level = maximum_threshold; + return (0); } int ugly_log(int level, const char *tag, const char *format, ...) { - if (level > max_level) { - return(0); - } + if (level > max_level) { + return (0); + } - fflush(stdout); // flush to maintain order of streams + fflush(stdout); // flush to maintain order of streams - va_list args; - va_start(args, format); - time_t mytt = time(NULL); - struct tm *tt; - tt = localtime(&mytt); - fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt->tm_year + 1900, tt->tm_mon + 1, - tt->tm_mday, tt->tm_hour, tt->tm_min, tt->tm_sec); + va_list args; + va_start(args, format); + time_t mytt = time(NULL); + struct tm *tt; + tt = localtime(&mytt); + fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt->tm_year + 1900, + tt->tm_mon + 1, tt->tm_mday, tt->tm_hour, tt->tm_min, tt->tm_sec); - switch (level) { - case UDEBUG: - fprintf(stderr, "DEBUG %s: ", tag); - break; - case UINFO: - fprintf(stderr, "INFO %s: ", tag); - break; - case UWARN: - fprintf(stderr, "WARN %s: ", tag); - break; - case UERROR: - fprintf(stderr, "ERROR %s: ", tag); - break; - default: - fprintf(stderr, "%d %s: ", level, tag); - break; - } + switch (level) { + case UDEBUG: + fprintf(stderr, "DEBUG %s: ", tag); + break; + case UINFO: + fprintf(stderr, "INFO %s: ", tag); + break; + case UWARN: + fprintf(stderr, "WARN %s: ", tag); + break; + case UERROR: + fprintf(stderr, "ERROR %s: ", tag); + break; + default: + fprintf(stderr, "%d %s: ", level, tag); + break; + } - vfprintf(stderr, format, args); - fflush(stderr); - va_end(args); - return(1); + vfprintf(stderr, format, args); + fflush(stderr); + va_end(args); + return (1); } /* * Log message levels. - * - LIBUSB_LOG_LEVEL_NONE (0) : no messages ever printed by the library (default) + * - LIBUSB_LOG_LEVEL_NONE (0) : no messages ever printed by the library + * (default) * - LIBUSB_LOG_LEVEL_ERROR (1) : error messages are printed to stderr - * - LIBUSB_LOG_LEVEL_WARNING (2) : warning and error messages are printed to stderr - * - LIBUSB_LOG_LEVEL_INFO (3) : informational messages are printed to stderr - * - LIBUSB_LOG_LEVEL_DEBUG (4) : debug and informational messages are printed to stderr + * - LIBUSB_LOG_LEVEL_WARNING (2) : warning and error messages are printed to + * stderr + * - LIBUSB_LOG_LEVEL_INFO (3) : informational messages are printed to + * stderr + * - LIBUSB_LOG_LEVEL_DEBUG (4) : debug and informational messages are + * printed to stderr */ int ugly_libusb_log_level(enum ugly_loglevel v) { #ifdef __FreeBSD__ - // FreeBSD includes its own reimplementation of libusb. - // Its libusb_set_debug() function expects a lib_debug_level - // instead of a lib_log_level and is verbose enough to drown out - // all other output. - switch (v) { - case UDEBUG: return (3); // LIBUSB_DEBUG_FUNCTION + LIBUSB_DEBUG_TRANSFER - case UINFO: return (1); // LIBUSB_DEBUG_FUNCTION only - case UWARN: return (0); // LIBUSB_DEBUG_NO - case UERROR: return (0); // LIBUSB_DEBUG_NO - } - return (0); + // FreeBSD includes its own reimplementation of libusb. + // Its libusb_set_debug() function expects a lib_debug_level + // instead of a lib_log_level and is verbose enough to drown out + // all other output. + switch (v) { + case UDEBUG: + return (3); // LIBUSB_DEBUG_FUNCTION + LIBUSB_DEBUG_TRANSFER + case UINFO: + return (1); // LIBUSB_DEBUG_FUNCTION only + case UWARN: + return (0); // LIBUSB_DEBUG_NO + case UERROR: + return (0); // LIBUSB_DEBUG_NO + } + return (0); #else - switch (v) { - case UDEBUG: return (4); - case UINFO: return (3); - case UWARN: return (2); - case UERROR: return (1); - } + switch (v) { + case UDEBUG: + return (4); + case UINFO: + return (3); + case UWARN: return (2); + case UERROR: + return (1); + } + return (2); #endif } From 553590b31b91f6edaafd75c895f0e87163037b42 Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Fri, 16 Apr 2021 19:09:06 +0200 Subject: [PATCH 1170/1435] chipid in files code --- src/st-util/gdb-server.c | 1 + src/stlink-lib/chipid.c | 192 ++++++++++++++++++++++++++++++++++++++- src/stlink-lib/chipid.h | 5 +- 3 files changed, 194 insertions(+), 4 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 006a0e3aa..797f4391b 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -220,6 +220,7 @@ int main(int argc, char** argv) { parse_options(argc, argv, &state); printf("st-util\n"); + init_chipids (NULL); sl = stlink_open_usb(state.logging_level, state.connect_mode, state.serialnumber, state.freq); if (sl == NULL) { return(1); } diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 221234bbb..e51e00201 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,7 +1,14 @@ #include #include "chipid.h" -static const struct stlink_chipid_params devices[] = { +#include +#include +#include +#include +#include +#include + +static struct stlink_chipid_params devices[] = { { // RM0410 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F7XXXX, @@ -711,8 +718,9 @@ static const struct stlink_chipid_params devices[] = { }, }; -const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { - const struct stlink_chipid_params *params = NULL; + +struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { + struct stlink_chipid_params *params = NULL; for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) if (devices[n].chip_id == chipid) { @@ -722,3 +730,181 @@ const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { return(params); } + +struct stlink_chipid_params *devicelist; + + + +void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) +{ + fprintf (fp, "# Chipid file for %s\n", dev->description); + fprintf (fp, "#\n"); + fprintf (fp, "chip_id %x\n", dev->chip_id); + fprintf (fp, "description %s\n", dev->description); + fprintf (fp, "flash_type %x\n", dev->flash_type); + fprintf (fp, "flash_pagesize %x\n", dev->flash_pagesize); + fprintf (fp, "sram_size %x\n", dev->sram_size); + fprintf (fp, "bootrom_base %x\n", dev->bootrom_base); + fprintf (fp, "bootrom_size %x\n", dev->bootrom_size); + fprintf (fp, "option_base %x\n", dev->option_base); + fprintf (fp, "option_size %x\n", dev->option_size); + fprintf (fp, "flags %x\n\n", dev->flags); +} + + + +struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { + struct stlink_chipid_params *params = NULL; + struct stlink_chipid_params *p2; + + // fprintf (stderr, "getparams: %x\n", chipid); + for (params = devicelist ; params != NULL ; params = params -> next) + if (params->chip_id == chipid) break; + + p2 = stlink_chipid_get_params_old (chipid); + + if (memcmp (p2, params, sizeof (struct stlink_chipid_params) - sizeof (struct stlink_chipid_params *)) != 0) { + //fprintf (stderr, "Error, chipid params not identical\n"); + //return NULL; + fprintf (stderr, "---------- old ------------\n"); + dump_a_chip (stderr, p2); + fprintf (stderr, "---------- new ------------\n"); + dump_a_chip (stderr, params); + } + return(params); +} + + +void process_chipfile (char *fname) +{ + FILE *fp; + char *p, buf[1025]; + char word[64], value[64]; + struct stlink_chipid_params *ts; + int nc; + + fprintf (stderr, "processing chipfile %s.\n", fname); + fp = fopen (fname, "r"); + if (!fp) { + perror (fname); + return; + } + + ts = calloc (sizeof (struct stlink_chipid_params), 1); + while (fgets (buf, 1024, fp) != NULL) { + for (p=buf;isspace (*p);p++); + if (!*p) continue; // we hit end-of-line wiht only whitespace + if (*p == '#') continue; // ignore comments. + + sscanf (p, "%s %s", word, value); + if (strcmp (word, "chip_id") == 0) { + sscanf (value, "%x", &ts->chip_id); + } else if (strcmp (word, "description") == 0) { + //ts->description = strdup (value); + buf[strlen(p)-1] = 0; // chomp newline + sscanf (p, "%*s %n", &nc); + ts->description = strdup (p+nc); + } else if (strcmp (word, "flash_type") == 0) { + sscanf (value, "%x", &ts->flash_type); + } else if (strcmp (word, "flash_size_reg") == 0) { + sscanf (value, "%x", &ts->flash_size_reg); + } else if (strcmp (word, "flash_pagesize") == 0) { + sscanf (value, "%x", &ts->flash_pagesize); + } else if (strcmp (word, "sram_size") == 0) { + sscanf (value, "%x", &ts->sram_size); + } else if (strcmp (word, "bootrom_base") == 0) { + sscanf (value, "%x", &ts->bootrom_base); + } else if (strcmp (word, "bootrom_size") == 0) { + sscanf (value, "%x", &ts->bootrom_size); + } else if (strcmp (word, "option_base") == 0) { + sscanf (value, "%x", &ts->option_base); + } else if (strcmp (word, "option_size") == 0) { + sscanf (value, "%x", &ts->option_size); + } else if (strcmp (word, "flags") == 0) { + sscanf (value, "%x", &ts->flags); + } else { + fprintf (stderr, "Unknown keyword in %s: %s\n", + fname, word); + } + } + ts->next = devicelist; + devicelist = ts; +} + + +void dump_chips (void) +{ + struct stlink_chipid_params *ts; + char *p, buf[100]; + FILE *fp; + + for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { + ts = &devices[n]; + + strcpy (buf, ts->description); + while ((p = strchr (buf, '/'))) // change slashes to underscore. + *p = '_'; + strcat (buf, ".chip"); + fp = fopen (buf, "w"); + fprintf (fp, "# Chipid file for %s\n", ts->description); + fprintf (fp, "#\n"); + fprintf (fp, "chip_id %x\n", ts->chip_id); + fprintf (fp, "description %s\n", ts->description); + fprintf (fp, "flash_type %x\n", ts->flash_type); + fprintf (fp, "flash_pagesize %x\n", ts->flash_pagesize); + fprintf (fp, "sram_size %x\n", ts->sram_size); + fprintf (fp, "bootrom_base %x\n", ts->bootrom_base); + fprintf (fp, "bootrom_size %x\n", ts->bootrom_size); + fprintf (fp, "option_base %x\n", ts->option_base); + fprintf (fp, "option_size %x\n", ts->option_size); + fprintf (fp, "flags %x\n\n", ts->flags); + fclose (fp); + } +} + + + +void init_chipids (char *dir_to_scan) +{ + DIR *d; + int nl; // namelen + struct dirent *dir; + if (!dir_to_scan) dir_to_scan = "./"; + + devicelist = NULL; + fprintf (stderr, "stlink_chipid_params %ld\n", sizeof (struct stlink_chipid_params)); + //dump_chips (); + d = opendir("."); + if (d) { + while ((dir = readdir(d)) != NULL) { + nl = strlen (dir->d_name); + if (strcmp (dir->d_name + nl - 5, ".chip") == 0) { + char buf[1024]; + sprintf (buf, "%s/%s", dir_to_scan, dir->d_name); + process_chipfile (buf); + } + } + closedir(d); + } else { + perror (dir_to_scan); + return; // XXX + } +#if 0 + { + struct stlink_chipid_params *p, *op; + int i; + p = devicelist; + for (i=0;i<5;i++, p = p->next) { + op = stlink_chipid_get_params_old (p->chip_id); + fprintf (stderr, "---------- old ------------\n"); + dump_a_chip (stderr, op); + fprintf (stderr, "---------- new ------------\n"); + dump_a_chip (stderr, p); + + } + } +#endif +} + + + diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f790e7899..d398b5c97 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -87,9 +87,12 @@ struct stlink_chipid_params { uint32_t option_base; uint32_t option_size; uint32_t flags; + struct stlink_chipid_params * next; }; -const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); + +struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); + void init_chipids (char *dir_to_scan); #ifdef __cplusplus } From 9396e4ee1e03b427b4ec501dabce8d4eb6952089 Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Fri, 16 Apr 2021 19:11:57 +0200 Subject: [PATCH 1171/1435] Added chips.zip --- src/chips.zip | Bin 0 -> 16336 bytes 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 src/chips.zip diff --git a/src/chips.zip b/src/chips.zip new file mode 100644 index 0000000000000000000000000000000000000000..e11e5cc6a4b9adb265d7aacbd718588f4720ae12 GIT binary patch literal 16336 zcmb7KcRbbK|F`!ZB_o?;T`sPX>@7)l8Cj7Xa?R{bLUt+{Wkgo83aM<8oe|Z?EFwbq zy|2Ew?^~ar`_bdv^2dFi^X#1SI+JpGe;;@lj2M=-b}nv$ zdb)%d*m|{I=JWMl<{ofj3{0FEYz&OO4{hN4G{83qF!1ig>l8+YulfSNRRV+j;QN{) zI&c95)E*E5k^3G6cL@Qt~x%CyfrCqzwtuiu^Y zgqv`-#qeE{9SC{0vlBv=mu<4VEepZVNO;A!DQ+`fS1j-5owg)^F=0QN~=EHrH(d$NPx^CZSk9dI3SA3`9a12LG=l-bd9O zt5a4@RAaEc8{eA!WA(Kz&hFRx-H)E|dlpeA6*5l*Tlrodpp|sd%b45R!OQCZoT{Gm zk7@YuoK;&g-STR#mCC?Ri#n=6o7z<6s|A5_IaWp;=69B5Z$9Z9lESh(zBQv#oY&p@ z2#y2C29s!L_YLy_2$X|JXo?6OP2yav99b}g1m~N7DCb#%kQ&YAwA~1rU_1y}>3o{8H+v;jo6|+)PTJ`FxQ_N5preeKertZp? z2>aM6QOY=|%~QkV)1Tl$>L=2aoHq8NcP9>n2rCT+*53&X zx`WfCBEq6@#ohX<^K~zN=#j_D1UOdBEWeLc5plAr{h-k*okhY4b`GWsu-RGrocMR2 zeRdnaxfsfmK(8AT8d04UC3_N|QeoyjV_r~O9M~Xjo_8jfLL+|A>`h^NG`|mr;!5t! zna@jHBIe%N1v%fwVXgIc<^>CaAgUR}UE3*MMK%9@L= z0HG>ioH!um;biaR?CHc}WqrfW()wstF&ae85E8}pv!N`l{J8T@r6jU&HiowTX*;nMaB8h~j4Mk6KWrrwNQm51=ALA}x^ik4Y z&Y2S?^1Fa-=Ttep-ci4Ntv-=AF8S8RO$l3f$qc2E4NNcx3*zlpfx!A-0fXj%gQf@+ zZl)^7{RrjkCTI?+v&i&qcgATlnC9`}$6>*+(BDA(EM9%^8U+ z`SU*p?CRxlohCZY&TSH6M{2Nsd3jG``YLZ?>m`m?gZHwT)S6OC^@uozTWGFddy^%> zZK~-Uy7aZ)z~EBN7s%zft|GhhMyLHUV}r;8n89>h++tWVc;>MxvWK1#r!g}+SSSrFcTA|aMgKN=uhLfZzvv;)1 zs0n2Vd~#*WNb`Et^cXGpB=DeytnVAXJaZg>e(b4qL$P3`UcDAqBl}BgFg<)Wwq`g$ z4JDpIQR5j45aCgxJ2({F4wT&OZSvODJkgn{ zc6Qd6v!gnx7d9d%H|ZZrIPB!#V&iQ8^5#B4a>R};b$5z-&KRTd0{KwU$88v|xTPtW z18L#nZl0zO29jyzr_oqNFyw`V)kf(3tONIk*txO7&A{x>$l0L8=v^anF$!L!sE8csDyC(ALpuHTy(7C)hM&N7xmAe=ygnM=x0@& zp50R))u$$K5(m_UmHP-hTGF0d#n~vc&fImoQBzdR&=oh@2iv;Xx9MwyiFc;?-6C-khDW zo4cGZ8b_%tQhUPh^td%W7~Ha(sb!*fv4&coF_TJFy-Xy8-(V1DR?NpG!^S$|9DRd} z@VtDnx@^LjX1~gpOgQu*ZPS3y4;9|qGFQVrc~lDrwkIDvU!UfCgo$$EOxolo5w`}M ziy6p^iXOQwh+J$xJ`2VlQ*a$UncYqy`Vf1BFwJ3MHsh7f%w8(?(@^4j%&SYX2_fCJ zl|7BR6}%11d>wN6uY}6$y3)i-3fomkBAQdO&4Rv5O}5Zsr~mp&zn1s?R6^o{)2cBM z+h#d`ogVw*=MMk(HWzOmYvDz``J>-oVIeXA)LR2X+!`3-)`+8VYmnHG_YkTkKB=7% zl7AmVW=k#XG|~qP3(CzP|F#TdmS!C7A$<0VTDZ(svpR3yyW&aG*-zT{ni1wbvb>`HZ{%Paem>7j*k>{UTe5u zM?8a;a1tdqbNRHMi8yF=z(9&;B51`kAu=GH!P)X@QQN_w%gMQw^*FCwdU?E%nyzwxZxrHGSxa=A-_5_9wjZWk*^C=hB{AhdbQSpD5>f_(#@%^S<$UKY&IpFb+3G z6P-;#M6vygUo9)7H&pwB>|7w3CYDy;ES7YAZaSiHNtl@Q`}mfcssvMw>g+;;0=8xE z6Zoj<6(UKlxU|n3ckO=ERR4;?TwZ%P^UwWXWJ3(VZTWJ#5|@;OO``P+UWpRr?Tu%m z3uNp+K6TXWBvqEZ87=xVWhS5a@F4(TfQZP4F-%zmh+)b=dWO!;KcFHWfSdlvp882I z&CE-VNs+q(J$=#r6ebP3rr&w%IvKqbr#M;En!3bBAD1uU(UR1<)mHqVeSKeHD%I$# z3@N|q)f8qSmMXI-f1qDHx-S2;F=tnJ7;EsyODoiu6 zld9uSuxdKRYxzFL^E#O%UEx~)y)9x*2g_t#MP?PILGx(A?pG1p;X0|qR#)q&49PN_ zUD(*@bTtM#$s6fRVib4Rp7q^u?Pz#^&HG-5J~e6#hHvp9N=d~1Kzbk{|KWkWfGA%S zccok81cqiNc+X|aGEt|z#!CTZV1$2xyrLVUaEM5nXaI2Bm7ij zqS&pg=+V>bc6=pU5js6%&phP zH0GiGkNhi(US)RYS8&05;X_t|ji3T9D3u`+hDRPMa282{@BQRGZ1otfMKI^1hvF$~ zKSF!-rHgGma~zjyR1+fjcvCmy`fR-k?Xrc_ z&F^xO)g4KvWOHy?uZI-|GRSCQ!XA_k7 zxu@BAY+=wm;N{{3eBR2H>*0CVn(~4ZR*#~O}BFN@czI8Z_~?L zW@4cLJ46z5?0})Bh=drTHj@)WD+C-o{^UJ|@)hmxiaiM~Tot*0PPMEjt3ilAqI~O{ z%ol^7>BZ03%S;G{aTh)*I6l)l+Ydy6=l#!<3&L(sQ52mYs24mY$kipem_^Yq;|0A? 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Wolff" Date: Fri, 16 Apr 2021 21:15:22 +0200 Subject: [PATCH 1172/1435] fixed a couple of warnings that macos compiler reports. --- src/stlink-lib/chipid.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index e51e00201..2d4237934 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -731,8 +731,7 @@ struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { return(params); } -struct stlink_chipid_params *devicelist; - +static struct stlink_chipid_params *devicelist; void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) @@ -867,7 +866,7 @@ void dump_chips (void) void init_chipids (char *dir_to_scan) { DIR *d; - int nl; // namelen + size_t nl; // namelen struct dirent *dir; if (!dir_to_scan) dir_to_scan = "./"; From e4078b118f288d869907f664eb4db42870dd4c33 Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Fri, 16 Apr 2021 21:25:44 +0200 Subject: [PATCH 1173/1435] removed unnecessary debug statement that didn't work on windows --- src/stlink-lib/chipid.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 2d4237934..e094f910f 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -871,7 +871,6 @@ void init_chipids (char *dir_to_scan) if (!dir_to_scan) dir_to_scan = "./"; devicelist = NULL; - fprintf (stderr, "stlink_chipid_params %ld\n", sizeof (struct stlink_chipid_params)); //dump_chips (); d = opendir("."); if (d) { From 6993491f90b15581668088a6e522b8fb9a3bb84e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 21 Apr 2021 00:00:33 +0200 Subject: [PATCH 1174/1435] Revert "Updated libusb to v1.0.24" This reverts commit 89a495d169a15f42d8cfd1a68c6738c984d052f8. --- .gitignore | 1 - .travis.sh | 18 +++++++-------- .travis.yml | 24 ++++++++++---------- cmake/modules/Findlibusb.cmake | 6 ++--- cmake/packaging/windows/generate_binaries.sh | 24 ++++++++++---------- 5 files changed, 36 insertions(+), 37 deletions(-) diff --git a/.gitignore b/.gitignore index 82c1195e4..a07eed9ca 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,5 @@ build build-mingw -build-mingw-* .project .cmake/ diff --git a/.travis.sh b/.travis.sh index 58cea5746..e45cd3609 100755 --- a/.travis.sh +++ b/.travis.sh @@ -8,20 +8,20 @@ echo "----" echo "WORK DIR:$DIR" DIR=$PWD -if [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then +if [ "$TRAVIS_JOB_NAME" == "linux-mingw-64" ]; then + echo "--> Building for Windows (x86-64) ..." + mkdir -p build-mingw && cd build-mingw-64 + cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ + -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR + make && rm -rf build-mingw-64 && cd - + +elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then echo "--> Building for Windows (i686) ..." - mkdir -p build-mingw-32 && cd build-mingw-32 + mkdir -p build-mingw && cd build-mingw-32 cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && rm -rf build-mingw-32 && cd - -# elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-64" ]; then -# echo "--> Building for Windows (x86-64) ..." -# mkdir -p build-mingw-64 && cd build-mingw-64 -# cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ -# -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR -# make && rm -rf build-mingw-64 && cd - - elif [ "$TRAVIS_OS_NAME" == "linux" ]; then sudo apt-get update -qq || true diff --git a/.travis.yml b/.travis.yml index 307c0bfa0..a733019a1 100644 --- a/.travis.yml +++ b/.travis.yml @@ -6,8 +6,8 @@ jobs: - os: linux dist: focal - env: BADGE=linux-mingw-32 - name: linux-mingw-32 + env: BADGE=linux-mingw-64 + name: linux-mingw compiler: gcc-10 addons: apt: @@ -15,16 +15,16 @@ jobs: packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - # - os: linux - # dist: focal - # env: BADGE=linux-mingw-64 - # name: linux-mingw-64 - # compiler: gcc-10 - # addons: - # apt: - # sources: ["ubuntu-toolchain-r-test"] - # packages: - # ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] + - os: linux + dist: focal + env: BADGE=linux-mingw-32 + name: linux-mingw + compiler: gcc-10 + addons: + apt: + sources: ["ubuntu-toolchain-r-test"] + packages: + ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] script: - git fetch --tags diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index 99f4d56ec..257c682ce 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -77,7 +77,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to if (NOT LIBUSB_FOUND) # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) @@ -94,7 +94,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download - ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 5c944b1c8aa9d43e026a94302d0f8ac4 + ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 cf3d38d2ff053ef343d10c0b8b0950c2 ) endif () @@ -128,7 +128,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to set(LIBUSB_NAME libusb-1.0.lib) find_library( LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/**/MS${ARCH}/dll + HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS${ARCH}/dll NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH ) diff --git a/cmake/packaging/windows/generate_binaries.sh b/cmake/packaging/windows/generate_binaries.sh index 5616ecb38..bf2453d10 100644 --- a/cmake/packaging/windows/generate_binaries.sh +++ b/cmake/packaging/windows/generate_binaries.sh @@ -5,6 +5,18 @@ # Install this cross-compiler toolchain: #sudo apt-get install mingw-w64 +# x86_64 +mkdir build-mingw-64 +cd build-mingw-64 +cmake -DCMAKE_SYSTEM_NAME=Windows \ + -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ + -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. +make package +cp dist/*.zip ../build/Release/dist +make clean +cd .. +rm -rf build-mingw-64 + # i686 mkdir build-mingw-32 cd build-mingw-32 @@ -16,15 +28,3 @@ cp dist/*.zip ../build/Release/dist make clean cd .. rm -rf build-mingw-32 - -# x86_64 -# mkdir build-mingw-64 -# cd build-mingw-64 -# cmake -DCMAKE_SYSTEM_NAME=Windows \ -# -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ -# -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. -# make package -# cp dist/*.zip ../build/Release/dist -# make clean -# cd .. -# rm -rf build-mingw-64 From c115ab2e0fcc3103e2ceb848c18b12641cfe7d0e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 24 Apr 2021 14:16:29 +0200 Subject: [PATCH 1175/1435] General Project Update - Formatting fixes - Commented CI build setting for Ubuntu 16.04 - Updated CHANGELOG.md --- .github/workflows/c-cpp.yml | 210 +++++++++++---------- CHANGELOG.md | 4 +- inc/stm32.h | 31 ++-- src/stlink-lib/chipid.c | 353 ++++++++++++++++++++---------------- 4 files changed, 323 insertions(+), 275 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index 97f48d88d..ef9e5f172 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -7,98 +7,97 @@ on: branches: [master, develop, testing] jobs: + # Linux -# Linux - - job_linux_16_04_64_gcc: - name: ubuntu-16.04 gcc - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean + # job_linux_16_04_64_gcc: + # name: ubuntu-16.04 gcc + # runs-on: ubuntu-16.04 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean - job_linux_16_04_32_gcc: - name: ubuntu-16.04 gcc 32-bit - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: Set compiler flags - run: | - CFLAGS="$CFLAGS -m32" - CXXFLAGS="$CXXFLAGS -m32" - LDFLAGS="$LDFLAGS -m32" - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean + # job_linux_16_04_32_gcc: + # name: ubuntu-16.04 gcc 32-bit + # runs-on: ubuntu-16.04 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + # - name: Set compiler flags + # run: | + # CFLAGS="$CFLAGS -m32" + # CXXFLAGS="$CXXFLAGS -m32" + # LDFLAGS="$LDFLAGS -m32" + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean - job_linux_16_04_64_clang: - name: ubuntu-16.04 clang - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean + # job_linux_16_04_64_clang: + # name: ubuntu-16.04 clang + # runs-on: ubuntu-16.04 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean - job_linux_16_04_32_clang: - name: ubuntu-16.04 clang 32-bit - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: Set compiler flags - run: | - CFLAGS="$CFLAGS -m32" - CXXFLAGS="$CXXFLAGS -m32" - LDFLAGS="$LDFLAGS -m32" - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean + # job_linux_16_04_32_clang: + # name: ubuntu-16.04 clang 32-bit + # runs-on: ubuntu-16.04 + # steps: + # - uses: actions/checkout@v2 + # - name: Install dependencies + # run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm + # - name: Set compiler flags + # run: | + # CFLAGS="$CFLAGS -m32" + # CXXFLAGS="$CXXFLAGS -m32" + # LDFLAGS="$LDFLAGS -m32" + # - name: make debug + # run: sudo make clean && make debug + # - name: make test + # run: sudo make clean && make test + # - name: make release + # run: sudo make clean && make release + # - name: sudo make install + # run: sudo make clean && sudo make install + # - name: sudo make package + # run: sudo make package + # - name: sudo make uninstall + # run: sudo make uninstall && sudo make clean job_linux_18_04_64_gcc: name: ubuntu-18.04 gcc @@ -144,7 +143,7 @@ jobs: run: sudo make package - name: sudo make uninstall run: sudo make uninstall && sudo make clean - + job_linux_18_04_64_clang: name: ubuntu-18.04 clang runs-on: ubuntu-18.04 @@ -280,7 +279,7 @@ jobs: - name: sudo make uninstall run: sudo make uninstall && sudo make clean -# macOS + # macOS # job_macos_10_14_64_gcc: # name: macos-10.14 gcc @@ -411,7 +410,6 @@ jobs: run: sudo make package - name: sudo make uninstall run: sudo make uninstall && sudo make clean - # job_macos_11_gcc: # name: macos-11.0 gcc # runs-on: macos-11.0 @@ -431,7 +429,6 @@ jobs: # run: sudo make package # - name: sudo make uninstall # run: sudo make uninstall && sudo make clean - # job_macos_11_clang: # name: macos-11.0 clang # runs-on: macos-11.0 @@ -451,20 +448,19 @@ jobs: # run: sudo make package # - name: sudo make uninstall # run: sudo make uninstall && sudo make clean - # Linux MinGW cross compliation - # job_linux_20_04_cross: - # name: ubuntu-20.04 mingw64 - # runs-on: ubuntu-20.04 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm mingw-w64 - # - name: Building Release for Windows (x86-64) ... - # run: sudo mkdir -p build-mingw && cd build-mingw && sudo cmake \ - # -DCMAKE_SYSTEM_NAME=Windows \ - # -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ - # -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake \ - # -DCMAKE_INSTALL_PREFIX=$PWD/install $PWD && \ - # sudo make && sudo rm -rf build-mingw && cd - +# job_linux_20_04_cross: +# name: ubuntu-20.04 mingw64 +# runs-on: ubuntu-20.04 +# steps: +# - uses: actions/checkout@v2 +# - name: Install dependencies +# run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm mingw-w64 +# - name: Building Release for Windows (x86-64) ... +# run: sudo mkdir -p build-mingw && cd build-mingw && sudo cmake \ +# -DCMAKE_SYSTEM_NAME=Windows \ +# -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ +# -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake \ +# -DCMAKE_INSTALL_PREFIX=$PWD/install $PWD && \ +# sudo make && sudo rm -rf build-mingw && cd - diff --git a/CHANGELOG.md b/CHANGELOG.md index 0ac52da73..a3e7dbafc 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -41,7 +41,7 @@ Updates & changes: Fixes: - Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#807](https://github.com/stlink-org/stlink/pull/807), [#817](https://github.com/stlink-org/stlink/pull/817), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) -- Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106)) +- Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106), [#1121](https://github.com/stlink-org/stlink/pull/1121)) - Use vl flashloader for all STM32F1 series ([#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) - cmake compile failure with external `CMAKE_MODULE_PATH` set ([#962](https://github.com/stlink-org/stlink/pull/962)) @@ -165,7 +165,7 @@ Fixes: - Set static link for `libssp` (stack-smashing protection) ([#960](https://github.com/stlink-org/stlink/pull/960), [#961](https://github.com/stlink-org/stlink/pull/961)) - Fixed udev rules installing to wrong directory ([#966](https://github.com/stlink-org/stlink/pull/966)) - Fixed formatting for options display in `st-flash` & `st-info` (commits [#c783d0e](https://github.com/stlink-org/stlink/commit/c783d0e777ccc83a7a8be26a4f4d3414e0478560) and [#562cd24](https://github.com/stlink-org/stlink/commit/562cd2496e696dbd22950925866aac662d81ee5f)) -- Fixed reading of chip ID on Cortex-M0+ core ([#1125](https://github.com/stlink-org/stlink/pull/1125), [#1126](https://github.com/stlink-org/stlink/pull/1126)) +- Fixed reading of chip ID on Cortex-M0+ core ([#1125](https://github.com/stlink-org/stlink/pull/1125), [#1126](https://github.com/stlink-org/stlink/pull/1126), [#1133](https://github.com/stlink-org/stlink/pull/1133)) # v1.6.0 diff --git a/inc/stm32.h b/inc/stm32.h index 7d60ab5de..21da2f563 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -8,24 +8,31 @@ #define STM32_H /* Cortex core ids */ -#define STM32VL_CORE_ID 0x1ba01477 -#define STM32F7_CORE_ID 0x5ba02477 -#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code +#define STM32VL_CORE_ID 0x1ba01477 +#define STM32F7_CORE_ID 0x5ba02477 +#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code #define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 pg3065) /* Constant STM32 memory map figures */ -#define STM32_FLASH_BASE ((uint32_t)0x08000000) -#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) -#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) -#define STM32_SRAM_BASE ((uint32_t)0x20000000) -#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) -#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) -#define STM32_L0_CATx_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_SRAM_BASE ((uint32_t)0x20000000) +#define STM32_FLASH_BASE ((uint32_t)0x08000000) +#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) +#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) + #define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) -#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) -#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023C14) #define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C) +#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) +#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) + +#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) + +#define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) +#define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) +#define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) +#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) + #endif // STM32_H diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 221234bbb..187a6d957 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -7,12 +7,15 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F7XXXX, .description = "F76xxx", .flash_type = STLINK_FLASH_TYPE_F7, - .flash_size_reg = 0x1ff0f442, // section 45.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, // ! "System memory" starting address from - .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from - .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 + .flash_size_reg = 0x1ff0f442, // section 45.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x80000, // "SRAM" byte size in hex from + .bootrom_base = 0x00200000, // ! "System memory" starting address from + .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from + .option_base = + STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option + // bytes, writing uses FLASH_F7_OPTCR + // and FLASH_F7_OPTCR1 .option_size = 0x20, .flags = CHIP_F_HAS_SWO_TRACING, }, @@ -21,11 +24,13 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F7, .description = "F7xx", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 41.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 + .flash_size_reg = 0x1ff0f442, // section 41.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 + .bootrom_base = + 0x00100000, // "System memory" starting address from DS Fig 18 + .bootrom_size = + 0xEDC0, // "System memory" byte size in hex from DS Fig 18 .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -33,14 +38,17 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F72XXX, .description = "F72x/F73x", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff07a22, // section 35.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 + .flash_size_reg = 0x1ff07a22, // section 35.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 + .bootrom_base = + 0x00100000, // "System memory" starting address from DS Fig 24 + .bootrom_size = + 0xEDC0, // "System memory" byte size in hex from DS Fig 24 .flags = CHIP_F_HAS_SWO_TRACING, }, - { // table 2, PM0063 + { + // table 2, PM0063 .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, .description = "F1xx Medium-density", .flash_type = STLINK_FLASH_TYPE_F0, @@ -51,11 +59,12 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x800, .flags = CHIP_F_HAS_SWO_TRACING, }, - { // table 1, PM0059 + { + // table 1, PM0059 .chip_id = STLINK_CHIPID_STM32_F2, .description = "F2xx", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, // as in RM0033 Rev 5 + .flash_size_reg = 0x1fff7a22, // as in RM0033 Rev 5 .flash_pagesize = 0x20000, .sram_size = 0x20000, .bootrom_base = 0x1fff0000, @@ -64,7 +73,8 @@ static const struct stlink_chipid_params devices[] = { .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, - { // PM0063 + { + // PM0063 .chip_id = STLINK_CHIPID_STM32_F1_LOW, .description = "F1 Low-density device", .flash_type = STLINK_FLASH_TYPE_F0, @@ -79,7 +89,7 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F4, .description = "F4xx", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 .flash_pagesize = 0x4000, .sram_size = 0x30000, .bootrom_base = 0x1fff0000, @@ -92,7 +102,7 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F4_DSI, .description = "F46x/F47x", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 .flash_pagesize = 0x4000, .sram_size = 0x40000, .bootrom_base = 0x1fff0000, @@ -103,7 +113,7 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F4_HD, .description = "F42x/F43x", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 .flash_pagesize = 0x4000, .sram_size = 0x40000, .bootrom_base = 0x1fff0000, @@ -224,7 +234,8 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x4800, .flags = CHIP_F_HAS_SWO_TRACING, }, - { // Low and Medium density VL have same chipid. RM0041 25.6.1 + { + // Low and Medium density VL have same chipid. RM0041 25.6.1 .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, .description = "F1xx Value Line", .flash_type = STLINK_FLASH_TYPE_F0, @@ -315,11 +326,12 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F0_CAN, .description = "F07x", .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 - .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 + .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = + 0x1fffC800, // "System memory" starting address from Table 2 + .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 }, { // Use this as an example for mapping future chips: @@ -327,11 +339,12 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F0, .description = "F0xx", .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = + 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 }, { // RM0402 document was used to find these parameters @@ -339,11 +352,12 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F412, .description = "F412", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) - .flash_pagesize = 0x4000, // Table 5. Flash module organization ? - .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) + .flash_pagesize = 0x4000, // Table 5. Flash module organization ? + .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 + .bootrom_base = + 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -352,22 +366,27 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F413, .description = "F413", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 - .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector sizes, but 0x4000 is smallest) - .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 only says 0x40000) - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 + .flash_pagesize = + 0x4000, // Table 5. Flash module organization (variable sector + // sizes, but 0x4000 is smallest) + .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 + // only says 0x40000) + .bootrom_base = + 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F09X, .description = "F09X", .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) - .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) - .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 - .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) + .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) + .bootrom_base = + 0x1fffd800, // "System memory" starting address from Table 2 + .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 }, { // Use this as an example for mapping future chips: @@ -375,11 +394,12 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F04, .description = "F04x", .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 + .bootrom_base = + 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 }, { // Use this as an example for mapping future chips: @@ -387,11 +407,12 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F0_SMALL, .description = "F0xx small", .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = + 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 }, { // STM32F30x @@ -416,7 +437,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2000, .bootrom_base = 0x1ff0000, .bootrom_size = 0x1000, - .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_base = STM32_L0_OPTION_BYTES_BASE, .option_size = 20, }, { @@ -430,7 +451,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x5000, .bootrom_base = 0x1ff0000, .bootrom_size = 0x2000, - .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_base = STM32_L0_OPTION_BYTES_BASE, .option_size = 20, }, { @@ -444,7 +465,7 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2000, .bootrom_base = 0x1ff0000, .bootrom_size = 0x1000, - .option_base = STM32_L0_CATx_OPTION_BYTES_BASE, + .option_base = STM32_L0_OPTION_BYTES_BASE, .option_size = 20, }, { @@ -466,10 +487,10 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_F303_HIGH, .description = "F303 high density", .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register - .flash_pagesize = 0x800, // 4.2.1 Flash memory organization - .sram_size = 0x10000, // 3.3 Embedded SRAM - .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory + .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register + .flash_pagesize = 0x800, // 4.2.1 Flash memory organization + .sram_size = 0x10000, // 3.3 Embedded SRAM + .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory .bootrom_size = 0x2000, .flags = CHIP_F_HAS_SWO_TRACING, }, @@ -479,15 +500,18 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L4, .description = "L4xx", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 - // and tables 4-6 on pages 79-81) - // SRAM1 is "up to" 96k in the standard Cortex-M memory map; - // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) + .flash_size_reg = + 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = + 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 + // and tables 4-6 on pages 79-81) + // SRAM1 is "up to" 96k in the standard Cortex-M memory map; + // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base + .bootrom_base = + 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, @@ -498,11 +522,13 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L4RX, .description = "L4Rx", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 97 - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 99) + .flash_size_reg = + 0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 97 + .sram_size = + 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 99) .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -511,13 +537,16 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L41X, .description = "L41x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, sec 47.2, page 1586) - .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) - // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 (DS12469, sec 3.5, page 18) - .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) - .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000, // 28k, same source as base + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, + // sec 47.2, page 1586) + .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) + // SRAM1 is 32k at 0x20000000 + // SRAM2 is 8k at 0x10000000 and 0x20008000 + // (DS12469, sec 3.5, page 18) + .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) + .bootrom_base = + 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) + .bootrom_size = 0x7000, // 28k, same source as base .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -526,15 +555,18 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L43X, .description = "L43x/L44x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 - // and tables 7-8 on pages 75-76) - // SRAM1 is "up to" 64k in the standard Cortex-M memory map; - // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) + .flash_size_reg = + 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) + .flash_pagesize = + 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 + // and tables 7-8 on pages 75-76) + // SRAM1 is "up to" 64k in the standard Cortex-M memory map; + // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) .sram_size = 0xc000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base + .bootrom_base = + 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, @@ -545,13 +577,15 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L496X, .description = "L496x/L4A6x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) - // SRAM1 is 256k at 0x20000000 - // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) - .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) - .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000, // 28k (per bank), same source as base + .flash_size_reg = + 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) + .flash_pagesize = + 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) + // SRAM1 is 256k at 0x20000000 + // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) + .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) + .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) + .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, @@ -562,14 +596,18 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L46X, .description = "L45x/46x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 - // and tables 7 on pages 73-74) - // SRAM1 is 128k at 0x20000000; - // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, page 68, also fig 2 on page 63) + .flash_size_reg = + 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) + .flash_pagesize = + 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 + // and tables 7 on pages 73-74) + // SRAM1 is 128k at 0x20000000; + // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, + // page 68, also fig 2 on page 63) .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system memory, also fig 2 on page 63) - .bootrom_size = 0x7000, // 28k (per bank), same source as base + .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system + // memory, also fig 2 on page 63) + .bootrom_size = 0x7000, // 28k (per bank), same source as base .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -588,11 +626,11 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_G0_CAT1, .description = "G030/G031/G041", .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x2000, // 8k (sec 2.3) + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x2000, // 8k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) + .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, }, @@ -601,11 +639,11 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_G0_CAT2, .description = "G070/G071/G081", .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x9000, // 36k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, }, @@ -614,14 +652,15 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_G4_CAT2, .description = "G4 Category-2", .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 16k at 0x20000000 - // SRAM2 is 6k at 0x20014000 - // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x8000, // 32k (sec 2.4) + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = + 0x800, // 2k (sec 3.3.1) + // SRAM1 is 16k at 0x20000000 + // SRAM2 is 6k at 0x20014000 + // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x8000, // 32k (sec 2.4) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) + .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, @@ -631,14 +670,15 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_G4_CAT3, .description = "G4 Category-3", .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 80k at 0x20000000 - // SRAM2 is 16k at 0x20014000 - // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x18000, // 128k (sec 2.4) + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = + 0x800, // 2k (sec 3.3.1) + // SRAM1 is 80k at 0x20000000 + // SRAM2 is 16k at 0x20014000 + // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x18000, // 128k (sec 2.4) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) + .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, @@ -649,7 +689,7 @@ static const struct stlink_chipid_params devices[] = { .description = "WB55", .flash_type = STLINK_FLASH_TYPE_WB, .flash_size_reg = 0x1FFF75E0, - .flash_pagesize = 0x1000, // 4k + .flash_pagesize = 0x1000, // 4k .sram_size = 0x40000, .bootrom_base = 0x1fff0000, // see the memory map .bootrom_size = 0x7000, @@ -660,13 +700,15 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_H74XXX, .description = "H74x/H75x", .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) - .flash_pagesize = 0x20000, // 128k sector (pg147) - .sram_size = 0x20000, // 128k "DTCM" from Table 7 - .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 - .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 + .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) + .flash_pagesize = 0x20000, // 128k sector (pg147) + .sram_size = 0x20000, // 128k "DTCM" from Table 7 + .bootrom_base = + 0x1ff00000, // "System memory" starting address from Table 7 + .bootrom_size = + 0x20000, // "System memory" byte size in hex from Table 7 .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 + .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { @@ -674,11 +716,13 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_H7AX, .description = "H7Ax/H7Bx", .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) - .flash_pagesize = 0x2000, // 8k sector (p.146) - .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 12-14) - .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to two banks (Table 12-14) + .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) + .flash_pagesize = 0x2000, // 8k sector (p.146) + .sram_size = 0x20000, // 128k "DTCM" (Figure 1) + .bootrom_base = + 0x1FF00000, // "System memory" starting address (Table 12-14) + .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to + // two banks (Table 12-14) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, @@ -688,11 +732,12 @@ static const struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_H72X, .description = "H72x/H73x", .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) - .flash_pagesize = 0x20000, // 128k sector (p.152) - .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 6) - .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) + .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) + .flash_pagesize = 0x20000, // 128k sector (p.152) + .sram_size = 0x20000, // 128k "DTCM" (Figure 1) + .bootrom_base = + 0x1FF00000, // "System memory" starting address (Table 6) + .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, .flags = CHIP_F_HAS_SWO_TRACING, @@ -712,13 +757,13 @@ static const struct stlink_chipid_params devices[] = { }; const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { - const struct stlink_chipid_params *params = NULL; + const struct stlink_chipid_params *params = NULL; - for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) - if (devices[n].chip_id == chipid) { - params = &devices[n]; - break; - } + for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) + if (devices[n].chip_id == chipid) { + params = &devices[n]; + break; + } - return(params); + return (params); } From b97296be8f22421b5beb21a4462bf8e515f74ab8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 24 Apr 2021 22:47:02 +0200 Subject: [PATCH 1176/1435] Release v1.7.0 --- .gitignore | 3 ++- .version | 2 +- CHANGELOG.md | 12 ++++++------ README.md | 4 ++-- cmake/packaging/windows/generate_binaries.sh | 4 ++-- 5 files changed, 13 insertions(+), 12 deletions(-) diff --git a/.gitignore b/.gitignore index a07eed9ca..1a5fd5ab1 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,6 @@ build -build-mingw +build-mingw-32 +build-mingw-64 .project .cmake/ diff --git a/.version b/.version index 9c6d6293b..bd8bf882d 100644 --- a/.version +++ b/.version @@ -1 +1 @@ -1.6.1 +1.7.0 diff --git a/CHANGELOG.md b/CHANGELOG.md index a3e7dbafc..9f63eca81 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,14 +2,14 @@ # v1.7.0 -Release date: 2020-04-xx +Release date: 2021-04-25 This release drops support for the STLINK/V1 programmer on macOS 10.13. Features: - Extended set of cmd line arguments for st-info and st-util ([#332](https://github.com/stlink-org/stlink/pull/332), [#990](https://github.com/stlink-org/stlink/pull/990), [#1091](https://github.com/stlink-org/stlink/pull/1091), [#1114](https://github.com/stlink-org/stlink/pull/1114)) -- Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#801](https://github.com/stlink-org/stlink/pull/801), [#868](https://github.com/stlink-org/stlink/pull/868), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) +- Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#801](https://github.com/stlink-org/stlink/pull/801), [#868](https://github.com/stlink-org/stlink/pull/868), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) - Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) - Official support for STLINK-V3 programmers (commit [#5e0a502](https://github.com/stlink-org/stlink/commit/5e0a502df812495bfa96fa9116a19f1306152b17), [#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) - Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) @@ -40,7 +40,8 @@ Updates & changes: Fixes: -- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#807](https://github.com/stlink-org/stlink/pull/807), [#817](https://github.com/stlink-org/stlink/pull/817), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) +- Improvements and fixes of the flash loaders, unification of the reset function ([#244](https://github.com/stlink-org/stlink/pull/244), [#382](https://github.com/stlink-org/stlink/pull/382), [#705](https://github.com/stlink-org/stlink/pull/705), [#980](https://github.com/stlink-org/stlink/pull/980), [#995](https://github.com/stlink-org/stlink/pull/995), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1115](https://github.com/stlink-org/stlink/pull/1115), [#1117](https://github.com/stlink-org/stlink/pull/1117), [#1122](https://github.com/stlink-org/stlink/pull/1122), [#1124](https://github.com/stlink-org/stlink/pull/1124)) +- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#807](https://github.com/stlink-org/stlink/pull/807), [#817](https://github.com/stlink-org/stlink/pull/817), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) - Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106), [#1121](https://github.com/stlink-org/stlink/pull/1121)) - Use vl flashloader for all STM32F1 series ([#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) @@ -53,7 +54,7 @@ Fixes: - Fixed `connect under reset` for `st-flash` and `st-util` ([#983](https://github.com/stlink-org/stlink/pull/983)) - Fix for `mmap() size_t overflow` in `st-flash` ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) - [regression] `stlink-gui` installation issue on Ubuntu-18.04 ([#1001](https://github.com/stlink-org/stlink/pull/1001), [#1004](https://github.com/stlink-org/stlink/pull/1004), [#1006](https://github.com/stlink-org/stlink/pull/1006)) -- `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027), [#1038](https://github.com/stlink-org/stlink/pull/1038),[#1064](https://github.com/stlink-org/stlink/pull/1064), [#1065](https://github.com/stlink-org/stlink/pull/1065)) +- `st-util`: wrong register values passed to `gdb` (STLink/V2) ([#1002](https://github.com/stlink-org/stlink/pull/1002), [#1011](https://github.com/stlink-org/stlink/pull/1011), [#1026](https://github.com/stlink-org/stlink/pull/1026), [#1027](https://github.com/stlink-org/stlink/pull/1027), [#1038](https://github.com/stlink-org/stlink/pull/1038), [#1064](https://github.com/stlink-org/stlink/pull/1064), [#1065](https://github.com/stlink-org/stlink/pull/1065)) - GDB: Fixed problems with target description ([#1013](https://github.com/stlink-org/stlink/pull/1013), [#1088](https://github.com/stlink-org/stlink/pull/1088), [#1109](https://github.com/stlink-org/stlink/pull/1109)) - [doc] Fixed wrong path for `rules.d` folder ([#1020](https://github.com/stlink-org/stlink/pull/1020)) - Fixed support for STLINK/V1 programmer ([#1045](https://github.com/stlink-org/stlink/pull/1045), [#1105](https://github.com/stlink-org/stlink/pull/1105)) @@ -66,7 +67,7 @@ Fixes: - [doc] Corrected spelling mistake in bug report template ([#1103](https://github.com/stlink-org/stlink/pull/1103)) - Fixed STM32WB55 reading DEBUG IDCODE from the wrong address ([#1100](https://github.com/stlink-org/stlink/pull/1100), [#1101](https://github.com/stlink-org/stlink/pull/1101)) - Applied missing changes to tests ([#1119](https://github.com/stlink-org/stlink/pull/1119)) -- Improvements for Chip_ID read ([#1120](https://github.com/stlink-org/stlink/pull/1120)) +- Improvements for Chip_ID read ([#1008](https://github.com/stlink-org/stlink/pull/1008), [#1120](https://github.com/stlink-org/stlink/pull/1120)) # v1.6.1 @@ -143,7 +144,6 @@ Updates & changes: Fixes: -- Improvements and fixes of the flash loaders, unification of the reset function ([#244](https://github.com/stlink-org/stlink/pull/244), [#382](https://github.com/stlink-org/stlink/pull/382), [#705](https://github.com/stlink-org/stlink/pull/705), [#980](https://github.com/stlink-org/stlink/pull/980), [#995](https://github.com/stlink-org/stlink/pull/995), [#1115](https://github.com/stlink-org/stlink/pull/1115), [#1117](https://github.com/stlink-org/stlink/pull/1117), [#1122](https://github.com/stlink-org/stlink/pull/1122), [#1124](https://github.com/stlink-org/stlink/pull/1124)) - Fixed wait-loop for `flash_loader_run()` ([#290](https://github.com/stlink-org/stlink/pull/290)) - Better argument parsing for CLI tools: `stlink_open_usb` can address v1, v2, v3 ([#378](https://github.com/stlink-org/stlink/pull/378), [#922](https://github.com/stlink-org/stlink/pull/922)) - Clear the PG bit before setting the `PER` bit ([#579](https://github.com/stlink-org/stlink/pull/579), [#876](https://github.com/stlink-org/stlink/pull/876)) diff --git a/README.md b/README.md index 93994db49..600879580 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) [![GitHub release](https://img.shields.io/github/release/stlink-org/stlink.svg)](https://github.com/stlink-org/stlink/releases/latest) [![Downloads](https://img.shields.io/github/downloads/stlink-org/stlink/total)](https://github.com/stlink-org/stlink/releases/latest) -![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.6.1/develop) +![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.7.0/develop) ![GitHub activity](https://img.shields.io/github/commit-activity/m/stlink-org/stlink) ![GitHub contributors](https://img.shields.io/github/contributors/stlink-org/stlink) [![CodeQL](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml/badge.svg)](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml) @@ -66,7 +66,7 @@ Our [tutorial](doc/tutorial.md) may help you along with some advanced tasks and **Windows**: As of Release v1.6.1 stand-alone Windows binaries are made available (again) on the release page of the project. -Please ensure to select the correct version for your system (i686 or x86_64). The archive file can be unzipped to any desired location as it does not contain any hardcoded paths. However we suggest to move the unzipped application folder to `C:\Program Files\` on 32-bit systems and to `C:\Program Files (x86)\` on 64-bit systems (the toolset is a 32-bit). +Please ensure to select the correct version for your system (i686 or x86_64). The archive file can be unzipped to any desired location as it does not contain any hardcoded paths. However we suggest to move the unzipped application folder to `C:\Program Files\` on 32-bit systems and to `C:\Program Files (x86)\` on 64-bit systems (the toolset is 32-bit). Alternatively one may compile and install from source as described in our [compiling manual](doc/compiling.md#Windows). diff --git a/cmake/packaging/windows/generate_binaries.sh b/cmake/packaging/windows/generate_binaries.sh index bf2453d10..f3642c316 100644 --- a/cmake/packaging/windows/generate_binaries.sh +++ b/cmake/packaging/windows/generate_binaries.sh @@ -12,7 +12,7 @@ cmake -DCMAKE_SYSTEM_NAME=Windows \ -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. make package -cp dist/*.zip ../build/Release/dist +sudo cp dist/*.zip ../build/Release/dist make clean cd .. rm -rf build-mingw-64 @@ -24,7 +24,7 @@ cmake -DCMAKE_SYSTEM_NAME=Windows \ -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ -DCMAKE_TOOLCHAIN_FILE=./../cmake/modules/set_toolchain.cmake .. make package -cp dist/*.zip ../build/Release/dist +sudo cp dist/*.zip ../build/Release/dist make clean cd .. rm -rf build-mingw-32 From 80c31a15a4ae447e0e300b5564a7c61f839f8b7f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 25 Apr 2021 01:43:12 +0200 Subject: [PATCH 1177/1435] General Project Update - Updated issue templates - Updated CONTRIBUTING.md (Closes #906) - Updated changelogs for deb and rpm packages - Updated CHANGELOG.md --- .github/ISSUE_TEMPLATE/bug-report.md | 17 +++++++++-------- .github/ISSUE_TEMPLATE/feature-request.md | 17 +++++++++-------- CHANGELOG.md | 12 ++++++++++++ CONTRIBUTING.md | 11 +++++++++++ cmake/packaging/deb/changelog | 6 ++++++ cmake/packaging/rpm/changelog | 3 +++ doc/release.md | 2 +- 7 files changed, 51 insertions(+), 17 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index 16e0477f0..c733c2c2e 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -5,14 +5,19 @@ title: "[STM32 device name]: $YourTitle" labels: "" --- -Thank you for giving feedback to the stlink project. +**Thank you for giving feedback to the stlink project.** -**NOTICE: Please read and follow instructions in #906 before submitting a ticket. -This bug report will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** +--- + +**NOTE: In order to offer sufficient and the best possible support, please read /CONTRIBUTING.md and follow the given instructions _before_ submitting a ticket.** + +**Bug reports and/or feature requests will be deleted, if they violate our contribution guidelines and if no issue-template is used!** Thank you for your support. + +--- - [ ] I made serious effort to avoid creating duplicate or nearly similar issue -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific problem. +In order to allow developers to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific problem. - [ ] Programmer/board type: [enter here] (e.g STLINK /V1, /V2, /V2-onboard, /V2-clone, /V3) - [ ] Operating system an version: [enter here] (e.g Linux, macOS, Windows) @@ -31,7 +36,3 @@ OUTPUT/ERROR of the commandline tool(s) Expected/description: `short description of the expected value` - -Thank you for your support. - -The stlink project maintainers diff --git a/.github/ISSUE_TEMPLATE/feature-request.md b/.github/ISSUE_TEMPLATE/feature-request.md index ddeb79357..d57dbefed 100644 --- a/.github/ISSUE_TEMPLATE/feature-request.md +++ b/.github/ISSUE_TEMPLATE/feature-request.md @@ -5,14 +5,19 @@ title: "[feature] $YourTitle" labels: code/feature-request --- -Thank you for giving feedback to the stlink project. +**Thank you for giving feedback to the stlink project.** -**NOTICE: Please read and follow instructions in #906 before submitting a ticket. -This feature request will be deleted without notice when not enough information is provided! So please ensure that all fields are filled out.** +--- + +**NOTE: In order to offer sufficient and the best possible support, please read /CONTRIBUTING.md and follow the given instructions _before_ submitting a ticket.** + +**Bug reports and/or feature requests will be deleted, if they violate our contribution guidelines and if no issue-template is used!** Thank you for your support. + +--- - [ ] I made serious effort to avoid creating duplicate or nearly similar issue -In order to allow developers and other contributors to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific request. +In order to allow developers to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific request. - [ ] Programmer/board type: [enter here] (e.g STLINK /V1, /V2, /V2-onboard, /V2-clone, /V3) - [ ] Operating system an version: [enter here] (e.g Linux, macOS, Windows) @@ -31,7 +36,3 @@ OUTPUT/ERROR of the commandline tool(s) Expected/description: `short description of the expected value` - -Thank you for your support. - -The stlink project maintainers diff --git a/CHANGELOG.md b/CHANGELOG.md index 9f63eca81..1b003d97e 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,5 +1,17 @@ # stlink Changelog +# v1.7.1 + +Release date: 2021-xx-xx + +Features: + +Updates & changes: + +- Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) + +Fixes: + # v1.7.0 Release date: 2021-04-25 diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index a9bb02661..6c1842aca 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -12,6 +12,17 @@ We love your input! We want to make contributing to this project as easy and tra We use GitHub to host code, to track issues and feature requests, as well as accept pull requests. Report a bug by [opening a new issue]() with one of the available templates. It's that easy! +**NOTE: In order to offer sufficient and the best possible support, please read and follow the instructions below before submitting a ticket:** + +1) If using a ST-Link-v2 programmer: Convince yourself that it is recognised as an USB device by your computer, thus reporting device and manufacturer ID. Use a diagnostic tool to probe for enumerated USB devices, e.g [`lsusb -v`](https://linux.die.net/man/8/lsusb) on unix-based systems. +2) **Use the [ST-Link firmware upgrade tool](https://www.st.com/en/development-tools/stsw-link007.html) based on Java to read out the current firmware version and update to the latest available version. This also works for _non-genuine_ ST programmers and boards.** +3) Try to make sure you have a working toolchain before starting to build. +4) **Update to the _latest_ release version or maybe even use the `develop` branch.** +5) Search for your problem in the available open issues, _before_ opening a new ticket. +6) Make sure to **use the available issue templates** to submit a bug-report or a feature-request. **Do not replace the prepared text, edit the placeholders instead. _Describe_ your problem.** +7) Avoid to add new comments to closed issues unless they confirm a solution already available. +8) Don't comment on tickets which do not specifically address your device or hardware - open a new ticket instead. +9) Consider if you can help to solve other issues (e.g. you have the same hardware) ## Coding conventions To read code written by other contributors can turn out to be quite demanding - a variable which seems to self-explaining, may appear cryptic to other readers. If you plan to contribute, please take this into account and feel encouraged to help others understand your code. In order to help you along, we have composed some contribution guidelines for this project. As this project already has a history you may find parts in the codebase that do not seem to comply with these guidelines, but we are trying to improve continuosly. However we can do even better, if every contributor considers the following points: diff --git a/cmake/packaging/deb/changelog b/cmake/packaging/deb/changelog index 24bb0152b..4d4d86c2b 100644 --- a/cmake/packaging/deb/changelog +++ b/cmake/packaging/deb/changelog @@ -1,3 +1,9 @@ +stlink (1.7.0) unstable; urgency=medium + + * Release v1.7.0 + + -- Nightwalker-87 Sun, 25 Apr 2021 00:00:00 +0100 + stlink (1.6.1) unstable; urgency=medium * Initial cpack-based package release for Debian/Ubuntu diff --git a/cmake/packaging/rpm/changelog b/cmake/packaging/rpm/changelog index 564bd95ae..3d1c76996 100644 --- a/cmake/packaging/rpm/changelog +++ b/cmake/packaging/rpm/changelog @@ -1,2 +1,5 @@ +* Sun Apr 25 2021 Nightwalker-87 - 1.7.0 +- Release v1.7.0 + * Mon Jun 01 2020 Nightwalker-87 - 1.6.1 - Initial cpack-based RPM package release diff --git a/doc/release.md b/doc/release.md index b44183b80..a67fcd743 100644 --- a/doc/release.md +++ b/doc/release.md @@ -3,7 +3,7 @@ Release This document describes the necessary steps for developers to create a release: -1. Update `CHANGELOG.md` +1. Update `CHANGELOG.md`, `cmake/packaging/deb/changelog` & `cmake/packaging/rpm/changelog` 2. Update `.version` with semantic version: `x.x.x` 3. Update `README.md` with semantic version `x.x.x` in commits badge 4. Create and push git tag and commits `git tag x.x.x` From 2b3a31609cc25a8248cab9beb2d19f5818f1d3ab Mon Sep 17 00:00:00 2001 From: anton Date: Sun, 25 Apr 2021 12:25:15 +0500 Subject: [PATCH 1178/1435] Moved set the PG flag from loader to code --- flashloaders/stm32f0.s | 14 ------------- src/common.c | 18 +++++++++++++--- src/stlink-lib/flash_loader.c | 39 +++++++++++++---------------------- 3 files changed, 29 insertions(+), 42 deletions(-) diff --git a/flashloaders/stm32f0.s b/flashloaders/stm32f0.s index 23f1c43fe..76bfd9b95 100644 --- a/flashloaders/stm32f0.s +++ b/flashloaders/stm32f0.s @@ -30,15 +30,9 @@ copy: # add r3 to flash_base for support dual bank (see flash_loader.c) ldr r7, flash_base add r7, r7, r3 - ldr r6, flash_off_cr - add r6, r6, r7 ldr r5, flash_off_sr add r5, r5, r7 - # FLASH_CR = 0x01 (set PG) - ldr r4, =0x1 - str r4, [r6] - loop: # copy 2 bytes ldrh r4, [r0] @@ -68,18 +62,10 @@ wait: bgt loop exit: - # FLASH_CR &= ~1 - ldr r7, =0x1 - ldr r4, [r6] - bics r4, r4, r7 - str r4, [r6] - bkpt .align 2 flash_base: .word 0x40022000 -flash_off_cr: - .word 0x10 flash_off_sr: .word 0x0c diff --git a/src/common.c b/src/common.c index 4541aa31c..fcd54e93e 100644 --- a/src/common.c +++ b/src/common.c @@ -3257,6 +3257,15 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { ELOG("stlink_flash_loader_init() == -1\n"); return (-1); } + + // unlock flash + unlock_flash_if(sl); + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + set_flash_cr_pg(sl, BANK_2); + } } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { ILOG("Starting Flash write for H7\n"); @@ -3437,7 +3446,9 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { uint32_t dhcsr; - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || + (sl->flash_type == STLINK_FLASH_TYPE_F4) || (sl->flash_type == STLINK_FLASH_TYPE_F7) || (sl->flash_type == STLINK_FLASH_TYPE_L4) || (sl->flash_type == STLINK_FLASH_TYPE_WB) || @@ -3446,8 +3457,9 @@ int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { (sl->flash_type == STLINK_FLASH_TYPE_H7)) { clear_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + if ((sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || + sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { clear_flash_cr_pg(sl, BANK_2); } lock_flash(sl); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index ba5efdb8e..c9e7661e9 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -19,44 +19,33 @@ /* flashloaders/stm32f0.s -- compiled with thumb2 */ static const uint8_t loader_code_stm32vl[] = { 0x00, 0xbf, 0x00, 0xbf, - 0x0e, 0x4f, 0x1f, 0x44, - 0x0e, 0x4e, 0x3e, 0x44, - 0x0e, 0x4d, 0x3d, 0x44, - 0x4f, 0xf0, 0x01, 0x04, - 0x34, 0x60, 0x04, 0x88, - 0x0c, 0x80, 0x02, 0x30, - 0x02, 0x31, 0x4f, 0xf0, - 0x01, 0x07, 0x2c, 0x68, - 0x3c, 0x42, 0xfc, 0xd1, - 0x4f, 0xf0, 0x14, 0x07, - 0x3c, 0x42, 0x01, 0xd1, - 0x02, 0x3a, 0xf0, 0xdc, + 0x09, 0x4f, 0x1f, 0x44, + 0x09, 0x4d, 0x3d, 0x44, + 0x04, 0x88, 0x0c, 0x80, + 0x02, 0x30, 0x02, 0x31, 0x4f, 0xf0, 0x01, 0x07, - 0x34, 0x68, 0xbc, 0x43, - 0x34, 0x60, 0x00, 0xbe, + 0x2c, 0x68, 0x3c, 0x42, + 0xfc, 0xd1, 0x4f, 0xf0, + 0x14, 0x07, 0x3c, 0x42, + 0x01, 0xd1, 0x02, 0x3a, + 0xf0, 0xdc, 0x00, 0xbe, 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00 }; /* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ static const uint8_t loader_code_stm32f0[] = { 0xc0, 0x46, 0xc0, 0x46, - 0x0c, 0x4f, 0x1f, 0x44, - 0x0c, 0x4e, 0x3e, 0x44, - 0x0c, 0x4d, 0x3d, 0x44, - 0x0c, 0x4c, 0x34, 0x60, + 0x08, 0x4f, 0x1f, 0x44, + 0x08, 0x4d, 0x3d, 0x44, 0x04, 0x88, 0x0c, 0x80, 0x02, 0x30, 0x02, 0x31, - 0x09, 0x4f, 0x2c, 0x68, + 0x06, 0x4f, 0x2c, 0x68, 0x3c, 0x42, 0xfc, 0xd1, - 0x08, 0x4f, 0x3c, 0x42, + 0x05, 0x4f, 0x3c, 0x42, 0x01, 0xd1, 0x02, 0x3a, - 0xf2, 0xdc, 0x05, 0x4f, - 0x34, 0x68, 0xbc, 0x43, - 0x34, 0x60, 0x00, 0xbe, + 0xf2, 0xdc, 0x00, 0xbe, 0x00, 0x20, 0x02, 0x40, - 0x10, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00 From 498d11b12be197392b8939d82549941beb87c52a Mon Sep 17 00:00:00 2001 From: anton Date: Sun, 25 Apr 2021 12:25:45 +0500 Subject: [PATCH 1179/1435] Moved the interrupt masking into flash loader init function --- src/common.c | 11 ----------- src/stlink-lib/flash_loader.c | 11 +++++++++++ 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/common.c b/src/common.c index fcd54e93e..d694ace8f 100644 --- a/src/common.c +++ b/src/common.c @@ -3137,17 +3137,6 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - - // According to DDI0419C, Table C1-7 firstly force halt - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - STLINK_REG_DHCSR_C_HALT); - // and only then disable interrupts - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_MASKINTS); - // disable DMA set_dma_state(sl, fl, 0); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index c9e7661e9..4ec91258b 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -148,6 +148,17 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { size_t size = 0; uint32_t dfsr, cfsr, hfsr; + /* Interrupt masking. + * According to DDI0419C, Table C1-7 firstly force halt */ + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT); + /* and only then disable interrupts */ + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_MASKINTS); + // allocate the loader in SRAM if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { WLOG("Failed to write flash loader to sram!\n"); From c959f348132ab3607a9ca8a23348f8d961e7852b Mon Sep 17 00:00:00 2001 From: anton Date: Sun, 25 Apr 2021 12:34:02 +0500 Subject: [PATCH 1180/1435] Added support for writing option bytes of F0/F1/F3 targets --- src/common.c | 185 ++++++++++++++++++++++++++++++++++++++-- src/stlink-lib/chipid.c | 36 +++++++- 2 files changed, 212 insertions(+), 9 deletions(-) diff --git a/src/common.c b/src/common.c index d694ace8f..7ddd37032 100644 --- a/src/common.c +++ b/src/common.c @@ -87,9 +87,11 @@ #define FLASH_CR_PER 1 #define FLASH_CR_MER 2 #define FLASH_CR_OPTPG 4 +#define FLASH_CR_OPTER 5 #define FLASH_CR_STRT 6 #define FLASH_CR_LOCK 7 #define FLASH_CR_OPTWRE 9 +#define FLASH_CR_OBL_LAUNCH 13 #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) #define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) @@ -3841,6 +3843,64 @@ int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { return (err); } +/** + * Write option bytes + * @param sl + * @param base option bytes to write + * @param addr of the memory mapped option bytes + * @param len of options bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f0( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { + int ret = 0; + + if (len < 12 || addr != STM32_F0_OPTION_BYTES_BASE) { + WLOG("Only full write of option bytes area is supported\n"); + return -1; + } + + clear_flash_error(sl); + + WLOG("Erasing option bytes\n"); + + /* erase option bytes */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_OPTWRE)); + ret = stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_STRT) | (1 << FLASH_CR_OPTWRE)); + if (ret) { + return ret; + } + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (ret) { + return ret; + } + + WLOG("Writing option bytes to %#10x\n", addr); + + /* Set the Option PG bit to enable programming */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTPG) | (1 << FLASH_CR_OPTWRE)); + + /* Use flash loader for write OP + * because flash memory writable by half word */ + flash_loader_t fl; + ret = stlink_flash_loader_init(sl, &fl); + if (ret) { + return ret; + } + ret = stlink_flash_loader_run(sl, &fl, addr, base, len); + if (ret) { + return ret; + } + + /* Reload option bytes */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OBL_LAUNCH)); + + return check_flash_error(sl); +} + /** * Write option bytes * @param sl @@ -4193,6 +4253,18 @@ int stlink_read_option_control_register_f7(stlink_t *sl, return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); } +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f0(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); + return stlink_read_debug32(sl, FLASH_OBR, option_byte); +} + /** * Read option bytes * @param sl @@ -4336,8 +4408,8 @@ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { return -1; } - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F7XXXX: + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: return stlink_read_option_bytes_boot_add_f7(sl, option_byte); default: return -1; @@ -4357,12 +4429,14 @@ int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { return -1; } - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F7XXXX: + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + return stlink_read_option_control_register_f0(sl, option_byte); + case STLINK_FLASH_TYPE_F7: return stlink_read_option_control_register_f7(sl, option_byte); default: return -1; - // return stlink_read_option_control_register_generic(sl, option_byte); } } @@ -4379,8 +4453,8 @@ int stlink_read_option_control_register1_32(stlink_t *sl, return -1; } - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F7XXXX: + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: return stlink_read_option_control_register1_f7(sl, option_byte); default: return -1; @@ -4442,6 +4516,10 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + ret = stlink_write_option_bytes_f0(sl, base, addr, len); + break; case STLINK_FLASH_TYPE_F4: ret = stlink_write_option_bytes_f4(sl, base, addr, len); break; @@ -4512,6 +4590,95 @@ stlink_write_option_control_register_f7(stlink_t *sl, return ret; } + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register_f0(stlink_t *sl, + uint32_t option_control_register) { + int ret = 0; + uint16_t opt_val[8]; + unsigned protection, optiondata; + uint16_t user_options, user_data, rdp; + unsigned option_offset, user_data_offset; + + ILOG("Asked to write option control register %#10x to %#010x.\n", + option_control_register, FLASH_OBR); + + /* Clear errors */ + clear_flash_error(sl); + + /* Retrieve current values */ + ret = stlink_read_debug32(sl, FLASH_OBR, &optiondata); + if (ret) { + return ret; + } + ret = stlink_read_debug32(sl, FLASH_WRPR, &protection); + if (ret) { + return ret; + } + + /* Translate OBR value to flash store structure + * F0: RM0091, Option byte description, pp. 75-78 + * F1: PM0075, Option byte description, pp. 19-22 + * F3: RM0316, Option byte description, pp. 85-87 */ + switch(sl->chip_id) + { + case 0x422: /* STM32F30x */ + case 0x432: /* STM32F37x */ + case 0x438: /* STM32F303x6/8 and STM32F328 */ + case 0x446: /* STM32F303xD/E and STM32F398xE */ + case 0x439: /* stm32f302x6/8 */ + case 0x440: /* stm32f05x */ + case 0x444: /* stm32f03x */ + case 0x445: /* stm32f04x */ + case 0x448: /* stm32f07x */ + case 0x442: /* stm32f09x */ + option_offset = 6; + user_data_offset = 16; + rdp = 0x55AA; + break; + default: + option_offset = 0; + user_data_offset = 10; + rdp = 0x5AA5; + break; + } + + user_options = (option_control_register >> option_offset >> 2) & 0xFFFF; + user_data = (option_control_register >> user_data_offset) & 0xFFFF; + +#define VAL_WITH_COMPLEMENT(v) (uint16_t)(((v)&0xFF) | (((~(v))<<8)&0xFF00)) + + opt_val[0] = (option_control_register & (1 << 1/*OPT_READOUT*/)) ? 0xFFFF : rdp; + opt_val[1] = VAL_WITH_COMPLEMENT(user_options); + opt_val[2] = VAL_WITH_COMPLEMENT(user_data); + opt_val[3] = VAL_WITH_COMPLEMENT(user_data >> 8); + opt_val[4] = VAL_WITH_COMPLEMENT(protection); + opt_val[5] = VAL_WITH_COMPLEMENT(protection >> 8); + opt_val[6] = VAL_WITH_COMPLEMENT(protection >> 16); + opt_val[7] = VAL_WITH_COMPLEMENT(protection >> 24); + +#undef VAL_WITH_COMPLEMENT + + /* Write bytes and check errors */ + ret = stlink_write_option_bytes_f0(sl, (uint8_t*)opt_val, STM32_F0_OPTION_BYTES_BASE, sizeof(opt_val)); + if (ret) + return ret; + + ret = check_flash_error(sl); + if (!ret) { + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, + FLASH_OBR); + } + + return ret; +} + /** * Write option bytes * @param sl @@ -4632,6 +4799,10 @@ int stlink_write_option_control_register32(stlink_t *sl, } switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + ret = stlink_write_option_control_register_f0(sl, option_control_register); + break; case STLINK_FLASH_TYPE_F7: ret = stlink_write_option_control_register_f7(sl, option_control_register); break; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 187a6d957..3d4339526 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -57,6 +57,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x5000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -83,6 +85,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2800, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -162,6 +166,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -232,6 +238,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, .bootrom_base = 0x1fffb000, .bootrom_size = 0x4800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -244,6 +252,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x2000, // 0x1000 for low density devices .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -283,6 +293,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -296,6 +308,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -307,6 +321,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x8000, .bootrom_base = 0x1ffff000, .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -332,12 +348,14 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, }, { // Use this as an example for mapping future chips: // RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F0, - .description = "F0xx", + .description = "F05x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 @@ -345,6 +363,8 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, }, { // RM0402 document was used to find these parameters @@ -387,6 +407,8 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, }, { // Use this as an example for mapping future chips: @@ -400,12 +422,14 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, }, { // Use this as an example for mapping future chips: // RM0091 document was used to find these paramaters .chip_id = STLINK_CHIPID_STM32_F0_SMALL, - .description = "F0xx small", + .description = "F03x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 @@ -413,6 +437,8 @@ static const struct stlink_chipid_params devices[] = { .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, }, { // STM32F30x @@ -424,6 +450,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0xa000, .bootrom_base = 0x1fffd800, .bootrom_size = 0x2000, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -479,6 +507,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x3000, .bootrom_base = 0x1fffd800, .bootrom_size = 0x2000, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -492,6 +522,8 @@ static const struct stlink_chipid_params devices[] = { .sram_size = 0x10000, // 3.3 Embedded SRAM .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory .bootrom_size = 0x2000, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { From eeaef981a5dcf6bec6d9b6cada398abcf34b8737 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 25 Apr 2021 19:58:09 +0200 Subject: [PATCH 1181/1435] Re-enabled GitHub Actions CI for Ubuntu 16.04 --- .github/workflows/c-cpp.yml | 174 ++++++++++++++++++------------------ 1 file changed, 88 insertions(+), 86 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index ef9e5f172..f68a9e53c 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -9,95 +9,95 @@ on: jobs: # Linux - # job_linux_16_04_64_gcc: - # name: ubuntu-16.04 gcc - # runs-on: ubuntu-16.04 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean + job_linux_16_04_64_gcc: + name: ubuntu-16.04 gcc + runs-on: ubuntu-16.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean - # job_linux_16_04_32_gcc: - # name: ubuntu-16.04 gcc 32-bit - # runs-on: ubuntu-16.04 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm - # - name: Set compiler flags - # run: | - # CFLAGS="$CFLAGS -m32" - # CXXFLAGS="$CXXFLAGS -m32" - # LDFLAGS="$LDFLAGS -m32" - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean + job_linux_16_04_32_gcc: + name: ubuntu-16.04 gcc 32-bit + runs-on: ubuntu-16.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean - # job_linux_16_04_64_clang: - # name: ubuntu-16.04 clang - # runs-on: ubuntu-16.04 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean + job_linux_16_04_64_clang: + name: ubuntu-16.04 clang + runs-on: ubuntu-16.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean - # job_linux_16_04_32_clang: - # name: ubuntu-16.04 clang 32-bit - # runs-on: ubuntu-16.04 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm - # - name: Set compiler flags - # run: | - # CFLAGS="$CFLAGS -m32" - # CXXFLAGS="$CXXFLAGS -m32" - # LDFLAGS="$LDFLAGS -m32" - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean + job_linux_16_04_32_clang: + name: ubuntu-16.04 clang 32-bit + runs-on: ubuntu-16.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean job_linux_18_04_64_gcc: name: ubuntu-18.04 gcc @@ -410,6 +410,7 @@ jobs: run: sudo make package - name: sudo make uninstall run: sudo make uninstall && sudo make clean + # job_macos_11_gcc: # name: macos-11.0 gcc # runs-on: macos-11.0 @@ -448,6 +449,7 @@ jobs: # run: sudo make package # - name: sudo make uninstall # run: sudo make uninstall && sudo make clean + # Linux MinGW cross compliation # job_linux_20_04_cross: From 1e8333e8ac8b7767a83bde6e3e43cd90f3fe0faf Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 25 Apr 2021 20:39:12 +0200 Subject: [PATCH 1182/1435] Fix for failed merge conflict resolve --- src/stlink-lib/chipid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index c505ed23a..f260af168 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -763,8 +763,8 @@ static struct stlink_chipid_params devices[] = { }, }; -const struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { - const struct stlink_chipid_params *params = NULL; +struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { + struct stlink_chipid_params *params = NULL; for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) if (devices[n].chip_id == chipid) { From 939998de76a904d82ba8248baacf4fc26d98badc Mon Sep 17 00:00:00 2001 From: anton Date: Tue, 27 Apr 2021 19:46:28 +0500 Subject: [PATCH 1183/1435] Fixed security warning --- src/stlink-lib/logging.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index 87978230d..d7ce13473 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -29,10 +29,10 @@ int ugly_log(int level, const char *tag, const char *format, ...) { va_list args; va_start(args, format); time_t mytt = time(NULL); - struct tm *tt; - tt = localtime(&mytt); - fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt->tm_year + 1900, - tt->tm_mon + 1, tt->tm_mday, tt->tm_hour, tt->tm_min, tt->tm_sec); + struct tm tt; + localtime_r(&mytt, &tt); + fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt.tm_year + 1900, + tt.tm_mon + 1, tt.tm_mday, tt.tm_hour, tt.tm_min, tt.tm_sec); switch (level) { case UDEBUG: From b652bc48549009a9d85ce7b1fc2449c146c05ae4 Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Wed, 28 Apr 2021 17:31:34 +0200 Subject: [PATCH 1184/1435] Chips files in the right place in the sources --- config/chips/F04x.chip | 13 +++++++++++++ config/chips/F07x.chip | 13 +++++++++++++ config/chips/F09X.chip | 13 +++++++++++++ config/chips/F0xx small.chip | 13 +++++++++++++ config/chips/F0xx.chip | 13 +++++++++++++ config/chips/F1 Connectivity line.chip | 13 +++++++++++++ config/chips/F1 Low-density device.chip | 13 +++++++++++++ config/chips/F1xx High-density value line.chip | 13 +++++++++++++ config/chips/F1xx High-density.chip | 13 +++++++++++++ config/chips/F1xx Medium-density.chip | 13 +++++++++++++ config/chips/F1xx Value Line.chip | 13 +++++++++++++ config/chips/F1xx XL-density.chip | 13 +++++++++++++ config/chips/F2xx.chip | 13 +++++++++++++ config/chips/F303 high density.chip | 13 +++++++++++++ config/chips/F334 medium density.chip | 13 +++++++++++++ config/chips/F3xx small.chip | 13 +++++++++++++ config/chips/F3xx.chip | 13 +++++++++++++ config/chips/F410.chip | 13 +++++++++++++ config/chips/F412.chip | 13 +++++++++++++ config/chips/F413.chip | 13 +++++++++++++ config/chips/F42x_F43x.chip | 13 +++++++++++++ config/chips/F446.chip | 13 +++++++++++++ config/chips/F46x_F47x.chip | 13 +++++++++++++ config/chips/F4xx (Dynamic Efficency).chip | 13 +++++++++++++ config/chips/F4xx (low power).chip | 13 +++++++++++++ config/chips/F4xx.chip | 13 +++++++++++++ config/chips/F72x_F73x.chip | 13 +++++++++++++ config/chips/F76xxx.chip | 13 +++++++++++++ config/chips/F7xx.chip | 13 +++++++++++++ config/chips/G030_G031_G041.chip | 13 +++++++++++++ config/chips/G070_G071_G081.chip | 13 +++++++++++++ config/chips/G4 Category-2.chip | 13 +++++++++++++ config/chips/G4 Category-3.chip | 13 +++++++++++++ config/chips/H72x_H73x.chip | 13 +++++++++++++ config/chips/H74x_H75x.chip | 13 +++++++++++++ config/chips/H7Ax_H7Bx.chip | 13 +++++++++++++ config/chips/L011.chip | 13 +++++++++++++ config/chips/L0x3.chip | 13 +++++++++++++ config/chips/L0xx Category 2.chip | 13 +++++++++++++ config/chips/L0xx Category 5.chip | 13 +++++++++++++ config/chips/L152RE.chip | 13 +++++++++++++ config/chips/L1xx Cat.2.chip | 13 +++++++++++++ config/chips/L1xx High-density.chip | 13 +++++++++++++ config/chips/L1xx Medium-Plus-density.chip | 13 +++++++++++++ config/chips/L1xx Medium-density.chip | 13 +++++++++++++ config/chips/L41x.chip | 13 +++++++++++++ config/chips/L43x_L44x.chip | 13 +++++++++++++ config/chips/L45x_46x.chip | 13 +++++++++++++ config/chips/L496x_L4A6x.chip | 13 +++++++++++++ config/chips/L4Rx.chip | 13 +++++++++++++ config/chips/L4xx.chip | 13 +++++++++++++ config/chips/WB55.chip | 13 +++++++++++++ config/chips/stm32f411re.chip | 13 +++++++++++++ config/chips/unknown device.chip | 13 +++++++++++++ src/chips.zip | Bin 16336 -> 0 bytes 55 files changed, 702 insertions(+) create mode 100644 config/chips/F04x.chip create mode 100644 config/chips/F07x.chip create mode 100644 config/chips/F09X.chip create mode 100644 config/chips/F0xx small.chip create mode 100644 config/chips/F0xx.chip create mode 100644 config/chips/F1 Connectivity line.chip create mode 100644 config/chips/F1 Low-density device.chip create mode 100644 config/chips/F1xx High-density value line.chip create mode 100644 config/chips/F1xx High-density.chip create mode 100644 config/chips/F1xx Medium-density.chip create mode 100644 config/chips/F1xx Value Line.chip create mode 100644 config/chips/F1xx XL-density.chip create mode 100644 config/chips/F2xx.chip create mode 100644 config/chips/F303 high density.chip create mode 100644 config/chips/F334 medium density.chip create mode 100644 config/chips/F3xx small.chip create mode 100644 config/chips/F3xx.chip create mode 100644 config/chips/F410.chip create mode 100644 config/chips/F412.chip create mode 100644 config/chips/F413.chip create mode 100644 config/chips/F42x_F43x.chip create mode 100644 config/chips/F446.chip create mode 100644 config/chips/F46x_F47x.chip create mode 100644 config/chips/F4xx (Dynamic Efficency).chip create mode 100644 config/chips/F4xx (low power).chip create mode 100644 config/chips/F4xx.chip create mode 100644 config/chips/F72x_F73x.chip create mode 100644 config/chips/F76xxx.chip create mode 100644 config/chips/F7xx.chip create mode 100644 config/chips/G030_G031_G041.chip create mode 100644 config/chips/G070_G071_G081.chip create mode 100644 config/chips/G4 Category-2.chip create mode 100644 config/chips/G4 Category-3.chip create mode 100644 config/chips/H72x_H73x.chip create mode 100644 config/chips/H74x_H75x.chip create mode 100644 config/chips/H7Ax_H7Bx.chip create mode 100644 config/chips/L011.chip create mode 100644 config/chips/L0x3.chip create mode 100644 config/chips/L0xx Category 2.chip create mode 100644 config/chips/L0xx Category 5.chip create mode 100644 config/chips/L152RE.chip create mode 100644 config/chips/L1xx Cat.2.chip create mode 100644 config/chips/L1xx High-density.chip create mode 100644 config/chips/L1xx Medium-Plus-density.chip create mode 100644 config/chips/L1xx Medium-density.chip create mode 100644 config/chips/L41x.chip create mode 100644 config/chips/L43x_L44x.chip create mode 100644 config/chips/L45x_46x.chip create mode 100644 config/chips/L496x_L4A6x.chip create mode 100644 config/chips/L4Rx.chip create mode 100644 config/chips/L4xx.chip create mode 100644 config/chips/WB55.chip create mode 100644 config/chips/stm32f411re.chip create mode 100644 config/chips/unknown device.chip delete mode 100644 src/chips.zip diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip new file mode 100644 index 000000000..72db26f8c --- /dev/null +++ b/config/chips/F04x.chip @@ -0,0 +1,13 @@ +# Chipid file for F04x +# +chip_id 445 +description F04x +flash_type 1 +flash_pagesize 400 +sram_size 1800 +bootrom_base 1fffec00 +bootrom_size c00 +option_base 0 +option_size 0 +flags 0 + diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip new file mode 100644 index 000000000..cfedfa76f --- /dev/null +++ b/config/chips/F07x.chip @@ -0,0 +1,13 @@ +# Chipid file for F07x +# +chip_id 448 +description F07x +flash_type 1 +flash_pagesize 800 +sram_size 4000 +bootrom_base 1fffc800 +bootrom_size 3000 +option_base 0 +option_size 0 +flags 0 + diff --git a/config/chips/F09X.chip b/config/chips/F09X.chip new file mode 100644 index 000000000..a622cf2f5 --- /dev/null +++ b/config/chips/F09X.chip @@ -0,0 +1,13 @@ +# Chipid file for F09X +# +chip_id 442 +description F09X +flash_type 1 +flash_pagesize 800 +sram_size 8000 +bootrom_base 1fffd800 +bootrom_size 2000 +option_base 0 +option_size 0 +flags 0 + diff --git a/config/chips/F0xx small.chip b/config/chips/F0xx small.chip new file mode 100644 index 000000000..65aea58ac --- /dev/null +++ b/config/chips/F0xx small.chip @@ -0,0 +1,13 @@ +# Chipid file for F0xx small +# +chip_id 444 +description F0xx small +flash_type 1 +flash_pagesize 400 +sram_size 1000 +bootrom_base 1fffec00 +bootrom_size c00 +option_base 0 +option_size 0 +flags 0 + diff --git a/config/chips/F0xx.chip b/config/chips/F0xx.chip new file mode 100644 index 000000000..5a5529412 --- /dev/null +++ b/config/chips/F0xx.chip @@ -0,0 +1,13 @@ +# Chipid file for F0xx +# +chip_id 440 +description F0xx +flash_type 1 +flash_pagesize 400 +sram_size 2000 +bootrom_base 1fffec00 +bootrom_size c00 +option_base 0 +option_size 0 +flags 0 + diff --git a/config/chips/F1 Connectivity line.chip b/config/chips/F1 Connectivity line.chip new file mode 100644 index 000000000..676fd1945 --- /dev/null +++ b/config/chips/F1 Connectivity line.chip @@ -0,0 +1,13 @@ +# Chipid file for F1 Connectivity line +# +chip_id 418 +description F1 Connectivity line +flash_type 1 +flash_pagesize 800 +sram_size 10000 +bootrom_base 1fffb000 +bootrom_size 4800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F1 Low-density device.chip b/config/chips/F1 Low-density device.chip new file mode 100644 index 000000000..dcb5e279e --- /dev/null +++ b/config/chips/F1 Low-density device.chip @@ -0,0 +1,13 @@ +# Chipid file for F1 Low-density device +# +chip_id 412 +description F1 Low-density device +flash_type 1 +flash_pagesize 400 +sram_size 2800 +bootrom_base 1ffff000 +bootrom_size 800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F1xx High-density value line.chip b/config/chips/F1xx High-density value line.chip new file mode 100644 index 000000000..f30014122 --- /dev/null +++ b/config/chips/F1xx High-density value line.chip @@ -0,0 +1,13 @@ +# Chipid file for F1xx High-density value line +# +chip_id 428 +description F1xx High-density value line +flash_type 1 +flash_pagesize 800 +sram_size 8000 +bootrom_base 1ffff000 +bootrom_size 800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F1xx High-density.chip b/config/chips/F1xx High-density.chip new file mode 100644 index 000000000..ed02e691a --- /dev/null +++ b/config/chips/F1xx High-density.chip @@ -0,0 +1,13 @@ +# Chipid file for F1xx High-density +# +chip_id 414 +description F1xx High-density +flash_type 1 +flash_pagesize 800 +sram_size 10000 +bootrom_base 1ffff000 +bootrom_size 800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F1xx Medium-density.chip b/config/chips/F1xx Medium-density.chip new file mode 100644 index 000000000..32266b74e --- /dev/null +++ b/config/chips/F1xx Medium-density.chip @@ -0,0 +1,13 @@ +# Chipid file for F1xx Medium-density +# +chip_id 410 +description F1xx Medium-density +flash_type 1 +flash_pagesize 400 +sram_size 5000 +bootrom_base 1ffff000 +bootrom_size 800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F1xx Value Line.chip b/config/chips/F1xx Value Line.chip new file mode 100644 index 000000000..929b95496 --- /dev/null +++ b/config/chips/F1xx Value Line.chip @@ -0,0 +1,13 @@ +# Chipid file for F1xx Value Line +# +chip_id 420 +description F1xx Value Line +flash_type 1 +flash_pagesize 400 +sram_size 2000 +bootrom_base 1ffff000 +bootrom_size 800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F1xx XL-density.chip b/config/chips/F1xx XL-density.chip new file mode 100644 index 000000000..a7125a429 --- /dev/null +++ b/config/chips/F1xx XL-density.chip @@ -0,0 +1,13 @@ +# Chipid file for F1xx XL-density +# +chip_id 430 +description F1xx XL-density +flash_type 2 +flash_pagesize 800 +sram_size 18000 +bootrom_base 1fffe000 +bootrom_size 1800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip new file mode 100644 index 000000000..b31be46f3 --- /dev/null +++ b/config/chips/F2xx.chip @@ -0,0 +1,13 @@ +# Chipid file for F2xx +# +chip_id 411 +description F2xx +flash_type 3 +flash_pagesize 20000 +sram_size 20000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 1fffc000 +option_size 4 +flags 2 + diff --git a/config/chips/F303 high density.chip b/config/chips/F303 high density.chip new file mode 100644 index 000000000..716c37c1e --- /dev/null +++ b/config/chips/F303 high density.chip @@ -0,0 +1,13 @@ +# Chipid file for F303 high density +# +chip_id 446 +description F303 high density +flash_type 1 +flash_pagesize 800 +sram_size 10000 +bootrom_base 1fffd800 +bootrom_size 2000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F334 medium density.chip b/config/chips/F334 medium density.chip new file mode 100644 index 000000000..424f1063c --- /dev/null +++ b/config/chips/F334 medium density.chip @@ -0,0 +1,13 @@ +# Chipid file for F334 medium density +# +chip_id 438 +description F334 medium density +flash_type 1 +flash_pagesize 800 +sram_size 3000 +bootrom_base 1fffd800 +bootrom_size 2000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F3xx small.chip b/config/chips/F3xx small.chip new file mode 100644 index 000000000..7f6f5159c --- /dev/null +++ b/config/chips/F3xx small.chip @@ -0,0 +1,13 @@ +# Chipid file for F3xx small +# +chip_id 439 +description F3xx small +flash_type 1 +flash_pagesize 800 +sram_size a000 +bootrom_base 1fffd800 +bootrom_size 2000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F3xx.chip b/config/chips/F3xx.chip new file mode 100644 index 000000000..4195f9007 --- /dev/null +++ b/config/chips/F3xx.chip @@ -0,0 +1,13 @@ +# Chipid file for F3xx +# +chip_id 432 +description F3xx +flash_type 1 +flash_pagesize 800 +sram_size a000 +bootrom_base 1ffff000 +bootrom_size 800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F410.chip b/config/chips/F410.chip new file mode 100644 index 000000000..3fb1b3d2a --- /dev/null +++ b/config/chips/F410.chip @@ -0,0 +1,13 @@ +# Chipid file for F410 +# +chip_id 458 +description F410 +flash_type 3 +flash_pagesize 4000 +sram_size 8000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F412.chip b/config/chips/F412.chip new file mode 100644 index 000000000..138e6c273 --- /dev/null +++ b/config/chips/F412.chip @@ -0,0 +1,13 @@ +# Chipid file for F412 +# +chip_id 441 +description F412 +flash_type 3 +flash_pagesize 4000 +sram_size 40000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F413.chip b/config/chips/F413.chip new file mode 100644 index 000000000..305a808dc --- /dev/null +++ b/config/chips/F413.chip @@ -0,0 +1,13 @@ +# Chipid file for F413 +# +chip_id 463 +description F413 +flash_type 3 +flash_pagesize 4000 +sram_size 50000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip new file mode 100644 index 000000000..c279a0e1d --- /dev/null +++ b/config/chips/F42x_F43x.chip @@ -0,0 +1,13 @@ +# Chipid file for F42x/F43x +# +chip_id 419 +description F42x/F43x +flash_type 3 +flash_pagesize 4000 +sram_size 40000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F446.chip b/config/chips/F446.chip new file mode 100644 index 000000000..6f372c067 --- /dev/null +++ b/config/chips/F446.chip @@ -0,0 +1,13 @@ +# Chipid file for F446 +# +chip_id 421 +description F446 +flash_type 3 +flash_pagesize 20000 +sram_size 20000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 1fffc000 +option_size 4 +flags 2 + diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip new file mode 100644 index 000000000..6d03bbea2 --- /dev/null +++ b/config/chips/F46x_F47x.chip @@ -0,0 +1,13 @@ +# Chipid file for F46x/F47x +# +chip_id 434 +description F46x/F47x +flash_type 3 +flash_pagesize 4000 +sram_size 40000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F4xx (Dynamic Efficency).chip b/config/chips/F4xx (Dynamic Efficency).chip new file mode 100644 index 000000000..fda012826 --- /dev/null +++ b/config/chips/F4xx (Dynamic Efficency).chip @@ -0,0 +1,13 @@ +# Chipid file for F4xx (Dynamic Efficency) +# +chip_id 433 +description F4xx (Dynamic Efficency) +flash_type 3 +flash_pagesize 4000 +sram_size 18000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F4xx (low power).chip b/config/chips/F4xx (low power).chip new file mode 100644 index 000000000..db9e99ffa --- /dev/null +++ b/config/chips/F4xx (low power).chip @@ -0,0 +1,13 @@ +# Chipid file for F4xx (low power) +# +chip_id 423 +description F4xx (low power) +flash_type 3 +flash_pagesize 4000 +sram_size 10000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F4xx.chip b/config/chips/F4xx.chip new file mode 100644 index 000000000..a9dd110c5 --- /dev/null +++ b/config/chips/F4xx.chip @@ -0,0 +1,13 @@ +# Chipid file for F4xx +# +chip_id 413 +description F4xx +flash_type 3 +flash_pagesize 4000 +sram_size 30000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 40023c14 +option_size 4 +flags 2 + diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip new file mode 100644 index 000000000..a673b04f0 --- /dev/null +++ b/config/chips/F72x_F73x.chip @@ -0,0 +1,13 @@ +# Chipid file for F72x/F73x +# +chip_id 452 +description F72x/F73x +flash_type 3 +flash_pagesize 800 +sram_size 40000 +bootrom_base 100000 +bootrom_size edc0 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/F76xxx.chip b/config/chips/F76xxx.chip new file mode 100644 index 000000000..c8f9ee108 --- /dev/null +++ b/config/chips/F76xxx.chip @@ -0,0 +1,13 @@ +# Chipid file for F76xxx +# +chip_id 451 +description F76xxx +flash_type 4 +flash_pagesize 800 +sram_size 80000 +bootrom_base 200000 +bootrom_size edc0 +option_base 1fff0000 +option_size 20 +flags 2 + diff --git a/config/chips/F7xx.chip b/config/chips/F7xx.chip new file mode 100644 index 000000000..c704ce2e2 --- /dev/null +++ b/config/chips/F7xx.chip @@ -0,0 +1,13 @@ +# Chipid file for F7xx +# +chip_id 449 +description F7xx +flash_type 3 +flash_pagesize 800 +sram_size 50000 +bootrom_base 100000 +bootrom_size edc0 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/G030_G031_G041.chip b/config/chips/G030_G031_G041.chip new file mode 100644 index 000000000..c6553904e --- /dev/null +++ b/config/chips/G030_G031_G041.chip @@ -0,0 +1,13 @@ +# Chipid file for G030/G031/G041 +# +chip_id 466 +description G030/G031/G041 +flash_type 7 +flash_pagesize 800 +sram_size 2000 +bootrom_base 1fff0000 +bootrom_size 2000 +option_base 1fff7800 +option_size 4 +flags 0 + diff --git a/config/chips/G070_G071_G081.chip b/config/chips/G070_G071_G081.chip new file mode 100644 index 000000000..ab57bbd27 --- /dev/null +++ b/config/chips/G070_G071_G081.chip @@ -0,0 +1,13 @@ +# Chipid file for G070/G071/G081 +# +chip_id 460 +description G070/G071/G081 +flash_type 7 +flash_pagesize 800 +sram_size 9000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 1fff7800 +option_size 4 +flags 0 + diff --git a/config/chips/G4 Category-2.chip b/config/chips/G4 Category-2.chip new file mode 100644 index 000000000..400152cd6 --- /dev/null +++ b/config/chips/G4 Category-2.chip @@ -0,0 +1,13 @@ +# Chipid file for G4 Category-2 +# +chip_id 468 +description G4 Category-2 +flash_type 8 +flash_pagesize 800 +sram_size 8000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 1ffff800 +option_size 4 +flags 2 + diff --git a/config/chips/G4 Category-3.chip b/config/chips/G4 Category-3.chip new file mode 100644 index 000000000..f8ea053f7 --- /dev/null +++ b/config/chips/G4 Category-3.chip @@ -0,0 +1,13 @@ +# Chipid file for G4 Category-3 +# +chip_id 469 +description G4 Category-3 +flash_type 8 +flash_pagesize 800 +sram_size 18000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 1ffff800 +option_size 4 +flags 3 + diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip new file mode 100644 index 000000000..e63c855c8 --- /dev/null +++ b/config/chips/H72x_H73x.chip @@ -0,0 +1,13 @@ +# Chipid file for H72x/H73x +# +chip_id 483 +description H72x/H73x +flash_type a +flash_pagesize 20000 +sram_size 20000 +bootrom_base 1ff00000 +bootrom_size 20000 +option_base 5200201c +option_size 2c +flags 2 + diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip new file mode 100644 index 000000000..24e85ff66 --- /dev/null +++ b/config/chips/H74x_H75x.chip @@ -0,0 +1,13 @@ +# Chipid file for H74x/H75x +# +chip_id 450 +description H74x/H75x +flash_type a +flash_pagesize 20000 +sram_size 20000 +bootrom_base 1ff00000 +bootrom_size 20000 +option_base 5200201c +option_size 2c +flags 3 + diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip new file mode 100644 index 000000000..bffd23603 --- /dev/null +++ b/config/chips/H7Ax_H7Bx.chip @@ -0,0 +1,13 @@ +# Chipid file for H7Ax/H7Bx +# +chip_id 480 +description H7Ax/H7Bx +flash_type a +flash_pagesize 2000 +sram_size 20000 +bootrom_base 1ff00000 +bootrom_size 20000 +option_base 5200201c +option_size 2c +flags 3 + diff --git a/config/chips/L011.chip b/config/chips/L011.chip new file mode 100644 index 000000000..02223ddcf --- /dev/null +++ b/config/chips/L011.chip @@ -0,0 +1,13 @@ +# Chipid file for L011 +# +chip_id 457 +description L011 +flash_type 5 +flash_pagesize 80 +sram_size 2000 +bootrom_base 1ff00000 +bootrom_size 2000 +option_base 0 +option_size 0 +flags 0 + diff --git a/config/chips/L0x3.chip b/config/chips/L0x3.chip new file mode 100644 index 000000000..60d75e863 --- /dev/null +++ b/config/chips/L0x3.chip @@ -0,0 +1,13 @@ +# Chipid file for L0x3 +# +chip_id 417 +description L0x3 +flash_type 5 +flash_pagesize 80 +sram_size 2000 +bootrom_base 1ff0000 +bootrom_size 1000 +option_base 1ff80000 +option_size 14 +flags 0 + diff --git a/config/chips/L0xx Category 2.chip b/config/chips/L0xx Category 2.chip new file mode 100644 index 000000000..1cb9e1307 --- /dev/null +++ b/config/chips/L0xx Category 2.chip @@ -0,0 +1,13 @@ +# Chipid file for L0xx Category 2 +# +chip_id 425 +description L0xx Category 2 +flash_type 5 +flash_pagesize 80 +sram_size 2000 +bootrom_base 1ff0000 +bootrom_size 1000 +option_base 1ff80000 +option_size 14 +flags 0 + diff --git a/config/chips/L0xx Category 5.chip b/config/chips/L0xx Category 5.chip new file mode 100644 index 000000000..35df2fb02 --- /dev/null +++ b/config/chips/L0xx Category 5.chip @@ -0,0 +1,13 @@ +# Chipid file for L0xx Category 5 +# +chip_id 447 +description L0xx Category 5 +flash_type 5 +flash_pagesize 80 +sram_size 5000 +bootrom_base 1ff0000 +bootrom_size 2000 +option_base 1ff80000 +option_size 14 +flags 0 + diff --git a/config/chips/L152RE.chip b/config/chips/L152RE.chip new file mode 100644 index 000000000..ec9d24442 --- /dev/null +++ b/config/chips/L152RE.chip @@ -0,0 +1,13 @@ +# Chipid file for L152RE +# +chip_id 437 +description L152RE +flash_type 5 +flash_pagesize 100 +sram_size 14000 +bootrom_base 1ff00000 +bootrom_size 1000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/L1xx Cat.2.chip b/config/chips/L1xx Cat.2.chip new file mode 100644 index 000000000..7a3080c60 --- /dev/null +++ b/config/chips/L1xx Cat.2.chip @@ -0,0 +1,13 @@ +# Chipid file for L1xx Cat.2 +# +chip_id 429 +description L1xx Cat.2 +flash_type 5 +flash_pagesize 100 +sram_size 8000 +bootrom_base 1ff00000 +bootrom_size 1000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/L1xx High-density.chip b/config/chips/L1xx High-density.chip new file mode 100644 index 000000000..4f6c85929 --- /dev/null +++ b/config/chips/L1xx High-density.chip @@ -0,0 +1,13 @@ +# Chipid file for L1xx High-density +# +chip_id 436 +description L1xx High-density +flash_type 5 +flash_pagesize 100 +sram_size c000 +bootrom_base 1ff00000 +bootrom_size 1000 +option_base 1ff80000 +option_size 8 +flags 2 + diff --git a/config/chips/L1xx Medium-Plus-density.chip b/config/chips/L1xx Medium-Plus-density.chip new file mode 100644 index 000000000..30ce11e92 --- /dev/null +++ b/config/chips/L1xx Medium-Plus-density.chip @@ -0,0 +1,13 @@ +# Chipid file for L1xx Medium-Plus-density +# +chip_id 427 +description L1xx Medium-Plus-density +flash_type 5 +flash_pagesize 100 +sram_size 8000 +bootrom_base 1ff00000 +bootrom_size 1000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/L1xx Medium-density.chip b/config/chips/L1xx Medium-density.chip new file mode 100644 index 000000000..a1817c5d6 --- /dev/null +++ b/config/chips/L1xx Medium-density.chip @@ -0,0 +1,13 @@ +# Chipid file for L1xx Medium-density +# +chip_id 416 +description L1xx Medium-density +flash_type 5 +flash_pagesize 100 +sram_size 4000 +bootrom_base 1ff00000 +bootrom_size 1000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/L41x.chip b/config/chips/L41x.chip new file mode 100644 index 000000000..008c9bfa2 --- /dev/null +++ b/config/chips/L41x.chip @@ -0,0 +1,13 @@ +# Chipid file for L41x +# +chip_id 464 +description L41x +flash_type 6 +flash_pagesize 800 +sram_size a000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip new file mode 100644 index 000000000..1d956c15e --- /dev/null +++ b/config/chips/L43x_L44x.chip @@ -0,0 +1,13 @@ +# Chipid file for L43x/L44x +# +chip_id 435 +description L43x/L44x +flash_type 6 +flash_pagesize 800 +sram_size c000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 1fff7800 +option_size 4 +flags 2 + diff --git a/config/chips/L45x_46x.chip b/config/chips/L45x_46x.chip new file mode 100644 index 000000000..438821fcc --- /dev/null +++ b/config/chips/L45x_46x.chip @@ -0,0 +1,13 @@ +# Chipid file for L45x/46x +# +chip_id 462 +description L45x/46x +flash_type 6 +flash_pagesize 800 +sram_size 20000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip new file mode 100644 index 000000000..b607e18cc --- /dev/null +++ b/config/chips/L496x_L4A6x.chip @@ -0,0 +1,13 @@ +# Chipid file for L496x/L4A6x +# +chip_id 461 +description L496x/L4A6x +flash_type 6 +flash_pagesize 800 +sram_size 40000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 1fff7800 +option_size 4 +flags 2 + diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip new file mode 100644 index 000000000..e42aba017 --- /dev/null +++ b/config/chips/L4Rx.chip @@ -0,0 +1,13 @@ +# Chipid file for L4Rx +# +chip_id 470 +description L4Rx +flash_type 6 +flash_pagesize 1000 +sram_size a0000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/L4xx.chip b/config/chips/L4xx.chip new file mode 100644 index 000000000..10ec24455 --- /dev/null +++ b/config/chips/L4xx.chip @@ -0,0 +1,13 @@ +# Chipid file for L4xx +# +chip_id 415 +description L4xx +flash_type 6 +flash_pagesize 800 +sram_size 18000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 1fff7800 +option_size 4 +flags 2 + diff --git a/config/chips/WB55.chip b/config/chips/WB55.chip new file mode 100644 index 000000000..bdc0d4449 --- /dev/null +++ b/config/chips/WB55.chip @@ -0,0 +1,13 @@ +# Chipid file for WB55 +# +chip_id 495 +description WB55 +flash_type 9 +flash_pagesize 1000 +sram_size 40000 +bootrom_base 1fff0000 +bootrom_size 7000 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/stm32f411re.chip b/config/chips/stm32f411re.chip new file mode 100644 index 000000000..ef889c139 --- /dev/null +++ b/config/chips/stm32f411re.chip @@ -0,0 +1,13 @@ +# Chipid file for stm32f411re +# +chip_id 431 +description stm32f411re +flash_type 3 +flash_pagesize 4000 +sram_size 20000 +bootrom_base 1fff0000 +bootrom_size 7800 +option_base 0 +option_size 0 +flags 2 + diff --git a/config/chips/unknown device.chip b/config/chips/unknown device.chip new file mode 100644 index 000000000..63ba47a30 --- /dev/null +++ b/config/chips/unknown device.chip @@ -0,0 +1,13 @@ +# Chipid file for unknown device +# +chip_id 0 +description unknown device +flash_type 0 +flash_pagesize 0 +sram_size 0 +bootrom_base 0 +bootrom_size 0 +option_base 0 +option_size 0 +flags 0 + diff --git a/src/chips.zip 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Wolff" Date: Wed, 28 Apr 2021 18:41:16 +0200 Subject: [PATCH 1185/1435] Moved the chips files to our own etc directory. --- CMakeLists.txt | 8 ++++++++ src/st-util/gdb-server.c | 3 +-- src/stlink-lib/chipid.c | 4 ++-- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 064aa06d5..feca0431a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -9,6 +9,11 @@ set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) +set(CMAKE_STLINK_ETC_DIR etc) +set(CMAKE_ETC_CHIPS_DIR ${CMAKE_STLINK_ETC_DIR}/stlink/chips) +set(CMAKE_ETC_CHIPS_DIR_ABS ${CMAKE_INSTALL_PREFIX}/${CMAKE_ETC_CHIPS_DIR}) +add_definitions( -DETC_STLINK_DIR="${CMAKE_ETC_CHIPS_DIR_ABS}" ) + ### # General project settings @@ -274,6 +279,9 @@ install(TARGETS st-info DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-util DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-trace DESTINATION ${CMAKE_INSTALL_BINDIR}) +file(GLOB CHIP_FILES ${CMAKE_SOURCE_DIR}/config/chips/*.chip) +install(FILES ${CHIP_FILES} DESTINATION ${CMAKE_ETC_CHIPS_DIR}) + ### # Device configuration (Linux only) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 797f4391b..6fe8774f7 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -219,8 +219,7 @@ int main(int argc, char** argv) { state.connect_mode = CONNECT_NORMAL; // by default, reset board parse_options(argc, argv, &state); - printf("st-util\n"); - init_chipids (NULL); + init_chipids (ETC_STLINK_DIR); sl = stlink_open_usb(state.logging_level, state.connect_mode, state.serialnumber, state.freq); if (sl == NULL) { return(1); } diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index e094f910f..bcb017740 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -782,7 +782,7 @@ void process_chipfile (char *fname) struct stlink_chipid_params *ts; int nc; - fprintf (stderr, "processing chipfile %s.\n", fname); + //fprintf (stderr, "processing chipfile %s.\n", fname); fp = fopen (fname, "r"); if (!fp) { perror (fname); @@ -872,7 +872,7 @@ void init_chipids (char *dir_to_scan) devicelist = NULL; //dump_chips (); - d = opendir("."); + d = opendir(dir_to_scan); if (d) { while ((dir = readdir(d)) != NULL) { nl = strlen (dir->d_name); From 7ee9fbcbd3c2e74253249f92ebfbb28204d131e4 Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Wed, 28 Apr 2021 18:52:43 +0200 Subject: [PATCH 1186/1435] Added init to other programs --- src/st-flash/flash.c | 1 + src/st-info/info.c | 2 ++ src/st-trace/trace.c | 2 ++ src/st-util/gdb-server.c | 2 ++ src/stlink-gui/gui.c | 2 ++ 5 files changed, 9 insertions(+) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index ede0f1179..cbcd00f47 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -61,6 +61,7 @@ int main(int ac, char** av) { } printf("st-flash %s\n", STLINK_VERSION); + init_chipids (ETC_STLINK_DIR); sl = stlink_open_usb(o.log_level, o.connect, (char *)o.serial, o.freq); diff --git a/src/st-info/info.c b/src/st-info/info.c index a6b4e85c6..7e3e47374 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -146,6 +146,8 @@ int main(int ac, char** av) { return(-1); } + init_chipids (ETC_STLINK_DIR); + err = print_data(ac, av); return(err); diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index a02c64701..754a55c72 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -509,6 +509,8 @@ int main(int argc, char **argv) { usage(); return APP_RESULT_INVALID_PARAMS; } + init_chipids (ETC_STLINK_DIR); + DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 6fe8774f7..49daa9799 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -219,6 +219,8 @@ int main(int argc, char** argv) { state.connect_mode = CONNECT_NORMAL; // by default, reset board parse_options(argc, argv, &state); + printf("st-util %s\n", STLINK_VERSION); + init_chipids (ETC_STLINK_DIR); sl = stlink_open_usb(state.logging_level, state.connect_mode, state.serialnumber, state.freq); diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index 03e999b7f..354ca1088 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -894,6 +894,8 @@ int main(int argc, char **argv) { gtk_init(&argc, &argv); + init_chipids (ETC_STLINK_DIR); + gui = g_object_new(STLINK_TYPE_GUI, NULL); stlink_gui_build_ui(gui); stlink_gui_init_dnd(gui); From 7e7bd7403efbcf5761465b003ed17ab09a74202f Mon Sep 17 00:00:00 2001 From: anton Date: Thu, 29 Apr 2021 22:47:18 +0500 Subject: [PATCH 1187/1435] Using localtime instead safe variant in case of compiler below C11 --- src/stlink-lib/logging.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index d7ce13473..817f3d68e 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -8,6 +8,7 @@ #include #include #include +#define __STDC_WANT_LIB_EXT1__ 1 #include #include "logging.h" @@ -29,10 +30,22 @@ int ugly_log(int level, const char *tag, const char *format, ...) { va_list args; va_start(args, format); time_t mytt = time(NULL); + + struct tm *ptt; +#if defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 201112L) // C11 struct tm tt; + ptt = &tt; +# if defined (_WIN32) || defined(__STDC_LIB_EXT1__) + localtime_s(&tt, &mytt); +# else localtime_r(&mytt, &tt); - fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", tt.tm_year + 1900, - tt.tm_mon + 1, tt.tm_mday, tt.tm_hour, tt.tm_min, tt.tm_sec); +# endif +#else + ptt = localtime(&mytt); +#endif + + fprintf(stderr, "%d-%02d-%02dT%02d:%02d:%02d ", ptt->tm_year + 1900, + ptt->tm_mon + 1, ptt->tm_mday, ptt->tm_hour, ptt->tm_min, ptt->tm_sec); switch (level) { case UDEBUG: From a06d13552da5884bd994fddf2655db243e3a6a48 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 2 May 2021 20:38:40 +0200 Subject: [PATCH 1188/1435] General Project Update - [doc] Minor spelling fixes. - [doc] Updated tool options in tutorial.md - [doc] Clean-up in tutorial.md - Corrected memory size supplements - [doc] Addtional link on STM32 Clone MCUs --- README.md | 2 +- doc/tutorial.md | 76 ++++++++-------------------------------- src/st-flash/flash.c | 6 ++-- src/st-flash/flash.h | 4 +-- src/st-info/info.c | 12 +++---- src/st-util/gdb-server.c | 4 +-- src/stlink-lib/helper.c | 4 +-- tests/flash.c | 2 +- 8 files changed, 31 insertions(+), 79 deletions(-) diff --git a/README.md b/README.md index 600879580..acc2441f8 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -# Open source version of the STMicroelectronics STlink Tools +# Open source version of the STMicroelectronics STLINK Tools [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) [![GitHub release](https://img.shields.io/github/release/stlink-org/stlink.svg)](https://github.com/stlink-org/stlink/releases/latest) diff --git a/doc/tutorial.md b/doc/tutorial.md index 71af3d45e..f8f0cbb05 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -4,8 +4,9 @@ | Option | Tool | Description | Available
      since | | --------------------- | ---------------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | -------------------- | -| --flash=n[k][m] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
      to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
      Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
      "k" or "m" to multiply the given value by 1k (1024) or 1M respectively. | v1.4.0 | -| --freq=n[k][m] | st-info
      st-flash
      st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
      This option solely accepts decimal values (5K or 1.8M) with the unit `Hz` being left out. Valid frequencies are:
      `5K, 15K, 25K, 50K, 100K, 125K, 240K, 480K, 950K, 1200K, 1800K, 4000K(4M)`. | v1.6.1 | +| --flash=n[k, M] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
      to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
      Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
      "k" or "M" to multiply the given value by 1k (1024) or 1M (1024 x 1024) respectively.
      One can read arbitary addresses of memory out to a binary file with: `st-flash read out.bin 0x8000000 4096`.
      In this example `4096 bytes` are read and subsequently written to `out.bin`.
      Binary files (here: `in.bin`) are written into flash memory with: `st-flash write in.bin 0x8000000` | v1.4.0 | +| --format | st-flash | Specify file image format to read or write. Valid formats are `binary` and `ihex`. | v1.3.0 +| --freq=n[k, M] | st-info
      st-flash
      st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
      This option solely accepts decimal values with the unit `Hz` being left out. Valid frequencies are:
      `5k, 15k, 25k, 50k, 100k, 125k, 240k, 480k, 950k, 1200k (1.2M), 1800k (1.8M), 4000k (4M)`. | v1.6.1 | | --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
      This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | | --reset | st-flash | Trigger a reset after flashing. The default uses the hardware reset through `NRST` pin.
      A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | | --connect-under-reset | st-info
      st-flash
      st-util | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
      when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | @@ -14,10 +15,19 @@ | --version | st-info
      st-flash
      st-util | Print version information. | v1.3.0 | | --help | st-flash
      st-util | Print list of available commands. | | +### Reading & Writing Option Bytes + +Example to read and write option bytes: + +``` +./st-flash --debug read option_bytes_dump.bin 0x1FFF7800 4 +./st-flash --debug write option_bytes_dump.bin 0x1FFF7800 +``` + ### st-flash: Checksum for binary files When flashing a file, a checksum is calculated for the binary file, both in md5 and the sum algorithm. -The latter is also used by the official ST-Link utility tool from STMicroelectronics as described in the document: [`UM0892 - User manual - STM32 ST-LINK utility software description`](https://www.st.com/resource/en/user_manual/cd00262073-stm32-stlink-utility-software-description-stmicroelectronics.pdf). +The latter is also used by the official ST-LINK utility tool from STMicroelectronics as described in the document: [`UM0892 - User manual STM32 ST-LINK utility software description`](https://www.st.com/resource/en/user_manual/cd00262073-stm32-stlink-utility-software-description-stmicroelectronics.pdf). ### stlink-gui @@ -95,6 +105,7 @@ In the following you find some hints on how to identify your chip and track down - [How to Detect STM32 Fakes](https://www.cnx-software.com/2020/03/22/how-to-detect-stm32-fakes/) - [Confirmation by STMicroelectronics](https://www.mikrocontroller.net/attachment/442839/couterfeit_STM.png) (Marking: 991KA 93 MYS 807) +- [STM32 Clones: The Good, The Bad And The Ugly](https://hackaday.com/2020/10/22/stm32-clones-the-good-the-bad-and-the-ugly/) However it appears that not all counterfeited parts cause problems during operation, but some are known to not even being able to execute a basic "blinky" example binary. Further there can be problems that may not even show up or affect you directly, but somewhen later in time (or maybe never). This demonstrates there is no guarantee for a proper working chip with equal functionality compared to the original. @@ -115,10 +126,6 @@ There are different variants of this message that refer to different issues: - `unknown chip id! 0` --> Target chip (board) is unknown. 1. Microcontroller is in stop/standby mode. 2. The signals `DIO` and `CLK` are reversed on the SWD-Interface. -- `unknown chip id! 0x1a` --> _currently unknown_ -- `unknown chip id! 0x001f` --> _currently unknown_ -- `unknown chip id! 0x3e8` --> _currently unknown_ -- `unknown chip id! 0xa05f0000` --> _currently unknown_ - `unknown chip id! 0x3748` --> A target chip (board) cannot be detected. 1. No target is connected --> In this case `st-info --probe` displays `chip id 0x0748` with STLINK/V2 and `chip id 0x03e8` with STLINK-V3. 2. The chip is connected but has gone into an undefined state of operation where the SWD pins are unresponsive. --> Try to use `--connect-under-reset` while pressing the reset button on the target board. @@ -214,38 +221,6 @@ Your program should now be running, and, if you used one of the blinking examples from libopencm3, the LEDs on the board should be blinking for you. -## Building and flashing a program - -If you want to simply flash binary files to arbitrary sections of -memory, or read arbitary addresses of memory out to a binary file, use -the st-flash tool, as shown below: - -``` -# stlink command to read 4096 from flash into out.bin -$> ./st-flash read out.bin 0x8000000 4096 - -# stlinkv command to write the file in.bin into flash -$> ./st-flash write in.bin 0x8000000 -``` - -It is also possible to write a hexfile which is more convinient: - -``` -$> ./st-flash --format ihex write myapp.hex -``` - -#### - -Of course, you can use this instead of the gdb server, if you prefer. -Just remember to use the “.bin” image, rather than the .elf file. - -``` -# write blink.bin into FLASH -$> [sudo] ./st-flash write fancy_blink.bin 0x08000000 -``` - -Upon reset, the board LEDs should be blinking. - ## Using the gdb server To run the gdb server: @@ -348,26 +323,3 @@ If you would link your executable to `0x08000000` and then do ``` then it would be written to the memory. - -## Writing Option Bytes - -Example to read and write option bytes (currently writing only supported for STM32G0 and STM32L0) - -``` -./st-flash --debug --reset --format binary --flash=128k read option_bytes_dump.bin 0x1FFF7800 4 -./st-flash --debug --reset --format binary --flash=128k write option_bytes_dump.bin 0x1FFF7800 -``` - -# FAQ - -Q: My breakpoints do not work at all or only work once. - -A: Optimizations can cause severe instruction reordering. For example, if you are doing something like `REG = 0x100;' in a loop, the code may be split into two parts: loading 0x100 into some intermediate register and moving that value to REG. When you set up a breakpoint, GDB will hook to the first instruction, which may be called only once if there are enough unused registers. In my experience, -O3 causes that frequently. - -Q: At some point I use GDB command `next', and it hangs. - -A: Sometimes when you will try to use GDB `next` command to skip a loop, it will use a rather inefficient single-stepping way of doing that. Set up a breakpoint manually in that case and do `continue`. - -Q: Load command does not work in GDB. - -A: Some people report XML/EXPAT is not enabled by default when compiling GDB. Memory map parsing thus fail. Use --enable-expat. diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index ede0f1179..a94d78254 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -26,9 +26,9 @@ static void cleanup(int signum) { } static void usage(void) { - puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--hot-plug] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); - puts("command line: ./st-flash [--debug] [--connect-under-reset] [--hot-plug] [--freq=] [--serial ] erase"); - puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); + puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--hot-plug] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); + puts("command line: ./st-flash [--debug] [--connect-under-reset] [--hot-plug] [--freq=] [--serial ] erase"); + puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); puts(" , and : Use hex format."); puts(" : Use decimal, octal or hex (prefix 0xXXX) format, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); puts(" : Can be 'binary' (default) or 'ihex', although must be specified for binary format only."); diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index cd08db70f..f3d431d65 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -23,9 +23,9 @@ struct flash_opts { enum flash_format format; enum flash_area area; uint32_t val; - size_t flash_size; // --flash=n[k][m] + size_t flash_size; // --flash=n[k, M] int opt; // enable empty tail data drop optimization - int freq; // --freq=n[k][m] frequency of JTAG/SWD + int freq; // --freq=n[k, M] frequency of JTAG/SWD enum connect_type connect; }; diff --git a/src/st-info/info.c b/src/st-info/info.c index a6b4e85c6..a9551cd49 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -8,13 +8,13 @@ static void usage(void) { puts("st-info --version"); - puts("st-info --probe [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --probe [--connect-under-reset] [--hot-plug] [--freq=]"); puts("st-info --serial"); - puts("st-info --flash [--connect-under-reset] [--hot-plug] [--freq=]"); - puts("st-info --pagesize [--connect-under-reset] [--hot-plug] [--freq=]"); - puts("st-info --sram [--connect-under-reset] [--hot-plug] [--freq=]"); - puts("st-info --chipid [--connect-under-reset] [--hot-plug] [--freq=]"); - puts("st-info --descr [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --flash [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --pagesize [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --sram [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --chipid [--connect-under-reset] [--hot-plug] [--freq=]"); + puts("st-info --descr [--connect-under-reset] [--hot-plug] [--freq=]"); } static void stlink_print_version(stlink_t *sl) { diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 006a0e3aa..83d8c3746 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -113,7 +113,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { const char * help_str = "%s - usage:\n\n" " -h, --help\t\tPrint this help\n" " -V, --version\t\tPrint the version\n" - " -vXX, --verbose=XX\tSpecify a specific verbosity level (0..99)\n" + " -vXX, --verbose=XX\tSpecify a specific verbosity level (0...99)\n" " -v, --verbose\t\tSpecify generally verbose logging\n" " -p 4242, --listen_port=1234\n" "\t\t\tSet the gdb server listen port. " @@ -125,7 +125,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { "\t\t\tDo not reset board on connection.\n" " -u, --connect-under-reset\n" "\t\t\tConnect to the board before executing any instructions.\n" - " -F 1800K, --freq=1M\n" + " -F 1800k, --freq=1M\n" "\t\t\tSet the frequency of the SWD/JTAG interface.\n" " --semihosting\n" "\t\t\tEnable semihosting support.\n" diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index 1f0f71b8d..15e6397bf 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -19,9 +19,9 @@ int arg_parse_freq(const char *str) { char *tail; int value = (int)strtol(str, &tail, 10); - if ((tail[0] == 'm' || tail[0] == 'M') && tail[1] == '\0') { + if (tail[0] == 'M' && tail[1] == '\0') { value = value*1000; - } else if (((tail[0] != 'k' && tail[0] != 'K') || tail[1] != '\0') && tail[0] != '\0') { + } else if ((tail[0] != 'k' || tail[1] != '\0') && tail[0] != '\0') { return -1; } diff --git a/tests/flash.c b/tests/flash.c index 132066aba..1140566af 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -109,7 +109,7 @@ static struct Test tests[] = { .freq = 5, .format = FLASH_FORMAT_BINARY } }, - { "--debug --freq 15K --reset write test.bin 0x80000000", 0, + { "--debug --freq 15k --reset write test.bin 0x80000000", 0, { .cmd = FLASH_CMD_WRITE, .serial = { 0 }, .filename = "test.bin", From afad37cc7e80efb1dc460bd9edd0b974d1cce449 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 3 May 2021 22:27:27 +0200 Subject: [PATCH 1189/1435] Added Travis CI build test for macOS 10.14 --- .travis.sh | 4 +--- .travis.yml | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 56 insertions(+), 4 deletions(-) diff --git a/.travis.sh b/.travis.sh index e45cd3609..a156db203 100755 --- a/.travis.sh +++ b/.travis.sh @@ -22,9 +22,7 @@ elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make && rm -rf build-mingw-32 && cd - -elif [ "$TRAVIS_OS_NAME" == "linux" ]; then - sudo apt-get update -qq || true - +elif [ "$TRAVIS_OS_NAME" == "osx" ]; then echo "--> Building Debug..." mkdir -p build/Debug && cd build/Debug cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR diff --git a/.travis.yml b/.travis.yml index a733019a1..c54c0c6f4 100644 --- a/.travis.yml +++ b/.travis.yml @@ -26,8 +26,62 @@ jobs: packages: ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] + ### macOS ### + + - os: osx + env: BADGE=osx + osx_image: xcode10.3 + name: macOS 10.14.4 gcc + compiler: gcc + addons: + homebrew: + packages: + - gcc + - libusb + - gtk+3 + + - os: osx + env: BADGE=osx + osx_image: xcode10.3 + name: macOS 10.14.4 gcc 32-bit + compiler: gcc + addons: + homebrew: + packages: + - gcc + - libusb + - gtk+3 + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + + - os: osx + env: BADGE=osx + osx_image: xcode10.3 + name: macOS 10.14.4 clang + compiler: clang + addons: + homebrew: + packages: + - clang + - libusb + - gtk+3 + + - os: osx + env: BADGE=osx + osx_image: xcode10.3 + name: macOS 10.14.4 clang 32-bit + compiler: gcc + addons: + homebrew: + packages: + - clang + - libusb + - gtk+3 + before_install: + - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + script: - git fetch --tags - printenv - cmake --version - - if [[ "$TRAVIS_OS_NAME" == "linux" ]]; then ./.travis.sh; fi + - if [[ "$TRAVIS_OS_NAME" == "linux" ]] || [[ "$TRAVIS_OS_NAME" == "osx" ]]; then ./.travis.sh; fi From df69dfa93c77aaeefd1d011f400343c18a836a6b Mon Sep 17 00:00:00 2001 From: Jipeng Zhang Date: Sun, 9 May 2021 23:42:00 -0700 Subject: [PATCH 1190/1435] add chipids of STM32G0B0/G0B1/G0C1/G050/G051/G061 --- src/stlink-lib/chipid.c | 32 +++++++++++++++++++++++++++++--- src/stlink-lib/chipid.h | 2 ++ 2 files changed, 31 insertions(+), 3 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 187a6d957..46cfc267f 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -630,12 +630,12 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // 2k (sec 3.2) .sram_size = 0x2000, // 8k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) + .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 5 on RM0444 & table 4 on RM0454) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, }, { - // STM32G071/081 (from RM0444) + // STM32G070/071/081 (from RM0454 & RM0444) .chip_id = STLINK_CHIPID_STM32_G0_CAT2, .description = "G070/G071/G081", .flash_type = STLINK_FLASH_TYPE_G0, @@ -643,7 +643,33 @@ static const struct stlink_chipid_params devices[] = { .flash_pagesize = 0x800, // 2k (sec 3.2) .sram_size = 0x9000, // 36k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 3 on RM0444 & table 3 on RM0454) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G0B0/0B1/0C1 (from RM0454 & RM0444) + .chip_id = STLINK_CHIPID_STM32_G0_CAT3, + .description = "G0B0/G0B1/G0C1", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x24000, // 144k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2 on RM0444 & table 2 on RM0454) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G050/051/061 (from RM0454 & RM0444) + .chip_id = STLINK_CHIPID_STM32_G0_CAT4, + .description = "G050/G051/G061", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x4800, // 18k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 4 on RM0444 & table 4 on RM0454) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, }, diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f790e7899..bb575a287 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -56,11 +56,13 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_H74XXX = 0x450, /* Found on page 3189 in the RM0433*/ STLINK_CHIPID_STM32_F7XXXX = 0x451, STLINK_CHIPID_STM32_F72XXX = 0x452, /* ID found on the NucleoF722ZE board */ + STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G050/G051/G061 found on RM0444/RM0454 */ STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ STLINK_CHIPID_STM32_F413 = 0x463, STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ + STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B0/G0B1/G0C1 found on RM0444/RM0454 */ STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ STLINK_CHIPID_STM32_G4_CAT3 = 0x469, STLINK_CHIPID_STM32_L4RX = 0x470, /* ID found on the STM32L4R9I-DISCO board */ From f02618c53c3d312aad8bb1cf8f0fb369b1af6ba3 Mon Sep 17 00:00:00 2001 From: Kristie Simpson Date: Tue, 11 May 2021 08:45:05 -0600 Subject: [PATCH 1191/1435] Adding option byte info for STM32F411XX --- src/common.c | 2 +- src/st-util/gdb-server.c | 2 +- src/stlink-lib/chipid.c | 6 ++++-- src/stlink-lib/chipid.h | 2 +- src/stlink-lib/flash_loader.c | 2 +- 5 files changed, 8 insertions(+), 6 deletions(-) diff --git a/src/common.c b/src/common.c index 7ddd37032..80190f756 100644 --- a/src/common.c +++ b/src/common.c @@ -2739,7 +2739,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || - (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || + (sl->chip_id == STLINK_CHIPID_STM32_F411XX) || (sl->chip_id == STLINK_CHIPID_STM32_F446) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 83d8c3746..6b68c8143 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -533,7 +533,7 @@ char* make_memory_map(stlink_t *sl) { if (sl->chip_id == STLINK_CHIPID_STM32_F4 || sl->chip_id == STLINK_CHIPID_STM32_F446 || - sl->chip_id == STLINK_CHIPID_STM32_F411RE) { + sl->chip_id == STLINK_CHIPID_STM32_F411XX) { strcpy(map, memory_map_template_F4); } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) { strcpy(map, memory_map_template_F4_DE); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 3d4339526..3a653701d 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -136,14 +136,16 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_F411RE, - .description = "stm32f411re", + .chip_id = STLINK_CHIPID_STM32_F411XX, + .description = "STM32F411xC/E", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x20000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, + .option_base = STM32_F4_OPTION_BYTES_BASE, + .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f790e7899..23aca5bd2 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -32,7 +32,7 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F1_VL_HIGH = 0x428, STLINK_CHIPID_STM32_L1_CAT2 = 0x429, STLINK_CHIPID_STM32_F1_XL = 0x430, - STLINK_CHIPID_STM32_F411RE = 0x431, + STLINK_CHIPID_STM32_F411XX = 0x431, STLINK_CHIPID_STM32_F37x = 0x432, STLINK_CHIPID_STM32_F4_DE = 0x433, STLINK_CHIPID_STM32_F4_DSI = 0x434, diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 4ec91258b..d492716db 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -260,7 +260,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_F4_HD || sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || sl->chip_id == STLINK_CHIPID_STM32_F410 || - sl->chip_id == STLINK_CHIPID_STM32_F411RE || + sl->chip_id == STLINK_CHIPID_STM32_F411XX || sl->chip_id == STLINK_CHIPID_STM32_F412 || sl->chip_id == STLINK_CHIPID_STM32_F413 || sl->chip_id == STLINK_CHIPID_STM32_F446) { From aa5dd2ccd2413d0fc6ea2f5035ec3d11119239ac Mon Sep 17 00:00:00 2001 From: anton Date: Thu, 13 May 2021 23:06:02 +0500 Subject: [PATCH 1192/1435] Reworked connection under reset --- src/common.c | 17 +++++++++++------ src/st-flash/flash.c | 2 +- src/stlink-lib/usb.c | 11 ++++++++++- 3 files changed, 22 insertions(+), 8 deletions(-) diff --git a/src/common.c b/src/common.c index 80190f756..556008d4d 100644 --- a/src/common.c +++ b/src/common.c @@ -4902,21 +4902,26 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect) { uint32_t dhcsr; if (connect == CONNECT_UNDER_RESET) { + stlink_enter_swd_mode(sl); + stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + stlink_force_debug(sl); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) usleep(20); - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { - stlink_enter_swd_mode(sl); - } - stlink_force_debug(sl); - // clear S_RESET_ST in DHCSR register stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); - usleep(10000); + + // try to halted core after reset + unsigned timeout = time_ms() + 10; + while (time_ms() < timeout) { + sl->backend->force_debug(sl); + usleep(100); + } // check NRST connection dhcsr = 0; diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index a94d78254..262784e1e 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -68,7 +68,7 @@ int main(int ac, char** av) { if (sl->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { printf("Failed to connect to target\n"); - return(-1); + goto on_error; } if ( o.flash_size != 0u && o.flash_size != sl->flash_size ) { diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 2754db06f..1d26508eb 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1343,11 +1343,20 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, // initialize stlink version (sl->version) stlink_version(sl); - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { + int mode = stlink_current_mode(sl); + if (mode == STLINK_DEV_DFU_MODE) { // this seems to work, and is unnecessary information for the user. // demoted to debug -- REW DLOG("-- exit_dfu_mode\n"); stlink_exit_dfu_mode(sl); + } else if (mode == STLINK_DEV_DEBUG_MODE && + connect == CONNECT_UNDER_RESET) { + // for the connect under reset only + // OpenOСD says (official documentation is not available) that + // the NRST pin must be pull down before selecting the SWD/JTAG mode + WLOG("-- exit_debug_mode\n"); + stlink_exit_debug_mode(sl); + _stlink_usb_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); } sl->freq = freq; From 616fd437d48044ddffad729f818960cabfd53911 Mon Sep 17 00:00:00 2001 From: anton Date: Fri, 14 May 2021 21:49:17 +0500 Subject: [PATCH 1193/1435] Removed warning that could mislead the user --- src/common.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/common.c b/src/common.c index 556008d4d..3931a8b42 100644 --- a/src/common.c +++ b/src/common.c @@ -1926,11 +1926,7 @@ int stlink_version(stlink_t *sl) { DLOG("swim version = 0x%x\n", sl->version.swim_v); if (sl->version.jtag_v == 0) { - DLOG(" notice: the firmware doesn't support a jtag/swd interface\n"); - } - - if (sl->version.swim_v == 0) { - DLOG(" notice: the firmware doesn't support a swim interface\n"); + WLOG(" warning: stlink doesn't support JTAG/SWD interface\n"); } return (0); From 22fba0249fe51bdcae607101c5b8a637345eeca8 Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 15 May 2021 22:32:57 +0500 Subject: [PATCH 1194/1435] Cleaned up code, made minor fixes --- inc/stlink.h | 31 +++------------- src/common.c | 48 +++++++++++++------------ src/st-flash/flash.c | 14 -------- src/st-info/info.c | 9 ----- src/stlink-gui/gui.c | 13 +------ src/stlink-lib/commands.h | 22 ++++++++++-- src/stlink-lib/sg.c | 8 ++--- src/stlink-lib/usb.c | 76 ++++++++++++++++++--------------------- 8 files changed, 89 insertions(+), 132 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index ec119c145..3bc518c87 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -25,7 +25,7 @@ extern "C" { // #define Q_BUF_LEN 96 #define Q_BUF_LEN (1024 * 100) -// STLINK_DEBUG_RESETSYS, etc: +/* Statuses of core */ enum target_state { TARGET_UNKNOWN = 0, TARGET_RUNNING = 1, @@ -37,38 +37,15 @@ enum target_state { #define STLINK_CORE_RUNNING 0x80 #define STLINK_CORE_HALTED 0x81 -#define STLINK_GET_VERSION 0xF1 -#define STLINK_GET_CURRENT_MODE 0xF5 -#define STLINK_GET_TARGET_VOLTAGE 0xF7 - -#define STLINK_DEBUG_COMMAND 0xF2 -#define STLINK_DFU_COMMAND 0xF3 -#define STLINK_DFU_EXIT 0x07 - -// STLINK_GET_CURRENT_MODE +/* STLINK modes */ #define STLINK_DEV_DFU_MODE 0x00 #define STLINK_DEV_MASS_MODE 0x01 #define STLINK_DEV_DEBUG_MODE 0x02 #define STLINK_DEV_UNKNOWN_MODE -1 -// TODO - possible poor names... -#define STLINK_SWD_ENTER 0x30 -#define STLINK_SWD_READCOREID 0x32 // TBD -#define STLINK_JTAG_WRITEDEBUG_32BIT 0x35 -#define STLINK_JTAG_READDEBUG_32BIT 0x36 -#define STLINK_JTAG_DRIVE_NRST 0x3C - /* NRST pin states */ -#define STLINK_JTAG_DRIVE_NRST_LOW 0x00 -#define STLINK_JTAG_DRIVE_NRST_HIGH 0x01 -#define STLINK_JTAG_DRIVE_NRST_PULSE 0x02 - -#define STLINK_DEBUG_APIV2_SWD_SET_FREQ 0x43 - -#define STLINK_APIV3_SET_COM_FREQ 0x61 -#define STLINK_APIV3_GET_COM_FREQ 0x62 - -#define STLINK_APIV3_GET_VERSION_EX 0xFB +#define STLINK_DEBUG_APIV2_DRIVE_NRST_LOW 0x00 +#define STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH 0x01 /* Baud rate divisors for SWDCLK */ #define STLINK_SWDCLK_4MHZ_DIVISOR 0 diff --git a/src/common.c b/src/common.c index 3931a8b42..ee91fa487 100644 --- a/src/common.c +++ b/src/common.c @@ -1275,8 +1275,8 @@ static void stop_wdg_in_debug(stlink_t *sl) { case STLINK_FLASH_TYPE_F1_XL: case STLINK_FLASH_TYPE_G4: dbgmcu_cr = STM32F0_DBGMCU_CR; - set = - (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | (1 << STM32F0_DBGMCU_CR_WWDG_STOP); + set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | + (1 << STM32F0_DBGMCU_CR_WWDG_STOP); break; case STLINK_FLASH_TYPE_F4: case STLINK_FLASH_TYPE_F7: @@ -1441,13 +1441,14 @@ void stlink_close(stlink_t *sl) { } int stlink_exit_debug_mode(stlink_t *sl) { - int ret; - DLOG("*** stlink_exit_debug_mode ***\n"); - ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); - if (ret == -1) { - return (ret); + if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN) { + // stop debugging if the target has been identified + int ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); + if (ret == -1) { + return (ret); + } } return (sl->backend->exit_debug_mode(sl)); @@ -1462,9 +1463,12 @@ int stlink_enter_swd_mode(stlink_t *sl) { int stlink_force_debug(stlink_t *sl) { DLOG("*** stlink_force_debug_mode ***\n"); int res = sl->backend->force_debug(sl); + if (res) { + return (res); + } // Stop the watchdogs in the halted state for suppress target reboot stop_wdg_in_debug(sl); - return (res); + return (0); } int stlink_exit_dfu_mode(stlink_t *sl) { @@ -1540,6 +1544,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { if (ret || !(*chip_id)) { *chip_id = 0; + ret = ret?:-1; ELOG("Could not find chip id!\n"); } else { *chip_id = (*chip_id) & 0xfff; @@ -1771,10 +1776,10 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { if (type == RESET_HARD || type == RESET_AUTO) { // hardware target reset if (sl->version.stlink_v > 1) { - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) usleep(100); - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); } if (sl->backend->reset(sl)) { return (-1); @@ -4895,24 +4900,21 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, } int stlink_target_connect(stlink_t *sl, enum connect_type connect) { - uint32_t dhcsr; - if (connect == CONNECT_UNDER_RESET) { stlink_enter_swd_mode(sl); - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); - stlink_force_debug(sl); + // try to halt the core before reset + // this is useful if the NRST pin is not connected + sl->backend->force_debug(sl); // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) usleep(20); - // clear S_RESET_ST in DHCSR register - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - - stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); - // try to halted core after reset + // try to halt the core after reset unsigned timeout = time_ms() + 10; while (time_ms() < timeout) { sl->backend->force_debug(sl); @@ -4920,7 +4922,7 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect) { } // check NRST connection - dhcsr = 0; + uint32_t dhcsr = 0; stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { WLOG("NRST is not connected\n"); @@ -4930,8 +4932,10 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect) { stlink_soft_reset(sl, 1 /* halt on reset */); } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { - stlink_enter_swd_mode(sl); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE && + stlink_enter_swd_mode(sl)) { + printf("Failed to enter SWD mode\n"); + return -1; } if (connect == CONNECT_NORMAL) { diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 262784e1e..be1ef60c2 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -84,20 +84,6 @@ int main(int ac, char** av) { signal(SIGTERM, &cleanup); signal(SIGSEGV, &cleanup); - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { - if (stlink_exit_dfu_mode(sl)) { - printf("Failed to exit DFU mode\n"); - goto on_error; - } - } - - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { - if (stlink_enter_swd_mode(sl)) { - printf("Failed to enter SWD mode\n"); - goto on_error; - } - } - // core must be halted to use RAM based flashloaders if (stlink_force_debug(sl)) { printf("Failed to halt the core\n"); diff --git a/src/st-info/info.c b/src/st-info/info.c index a9551cd49..7eda5d6ff 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -42,7 +42,6 @@ static void stlink_print_info(stlink_t *sl) { printf(" chipid: 0x%.4x\n", sl->chip_id); params = stlink_chipid_get_params(sl->chip_id); - if (params) { printf(" descr: %s\n", params->description); } } @@ -103,15 +102,8 @@ static int print_data(int ac, char **av) { // open first st-link device sl = stlink_open_usb(0, connect, NULL, freq); - if (sl == NULL) { return(-1); } - sl->verbose = 0; - - if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { stlink_exit_dfu_mode(sl); } - - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { stlink_enter_swd_mode(sl); } - if (strcmp(av[1], "--serial") == 0) { printf("%s\n", sl->serial); } else if (strcmp(av[1], "--flash") == 0) { @@ -124,7 +116,6 @@ static int print_data(int ac, char **av) { printf("0x%.4x\n", sl->chip_id); } else if (strcmp(av[1], "--descr") == 0) { const struct stlink_chipid_params *params = stlink_chipid_get_params(sl->chip_id); - if (params == NULL) { return(-1); } printf("%s\n", params->description); diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index 03e999b7f..653428735 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -495,24 +495,13 @@ static void connect_button_cb(GtkWidget *widget, gpointer data) { if (gui->sl != NULL) { return; } - gui->sl = stlink_v1_open(0, 1); // try version 1 then version 2 - - if (gui->sl == NULL) { gui->sl = stlink_open_usb(0, 1, NULL, 0); } + gui->sl = stlink_open_usb(0, 1, NULL, 0); if (gui->sl == NULL) { stlink_gui_set_info_error_message(gui, "Failed to connect to STLink."); return; } - // code below taken from flash/main.c, refactoring might be in order - if (stlink_current_mode(gui->sl) == STLINK_DEV_DFU_MODE) { - stlink_exit_dfu_mode(gui->sl); - } - - if (stlink_current_mode(gui->sl) != STLINK_DEV_DEBUG_MODE) { - stlink_enter_swd_mode(gui->sl); - } - stlink_gui_set_connected(gui); } diff --git a/src/stlink-lib/commands.h b/src/stlink-lib/commands.h index dac82b8e6..136adf80e 100644 --- a/src/stlink-lib/commands.h +++ b/src/stlink-lib/commands.h @@ -1,8 +1,17 @@ #ifndef STLINK_COMMANDS_H_ #define STLINK_COMMANDS_H_ +enum stlink_commands { + STLINK_GET_VERSION = 0xF1, + STLINK_DEBUG_COMMAND = 0xF2, + STLINK_DFU_COMMAND = 0xF3, + STLINK_GET_CURRENT_MODE = 0xF5, + STLINK_GET_TARGET_VOLTAGE = 0xF7, + STLINK_GET_VERSION_APIV3 = 0xFB +}; + enum stlink_debug_commands { - STLINK_DEBUG_ENTER_JTAG = 0x00, + STLINK_DEBUG_ENTER_JTAG_RESET = 0x00, STLINK_DEBUG_GETSTATUS = 0x01, STLINK_DEBUG_FORCEDEBUG = 0x02, STLINK_DEBUG_APIV1_RESETSYS = 0x03, @@ -29,11 +38,20 @@ enum stlink_debug_commands { STLINK_DEBUG_APIV2_READDEBUGREG = 0x36, STLINK_DEBUG_APIV2_READALLREGS = 0x3A, STLINK_DEBUG_APIV2_GETLASTRWSTATUS = 0x3B, + STLINK_DEBUG_APIV2_DRIVE_NRST = 0x3C, STLINK_DEBUG_APIV2_GETLASTRWSTATUS2 = 0x3E, STLINK_DEBUG_APIV2_START_TRACE_RX = 0x40, STLINK_DEBUG_APIV2_STOP_TRACE_RX = 0x41, STLINK_DEBUG_APIV2_GET_TRACE_NB = 0x42, - STLINK_DEBUG_ENTER_SWD = 0xa3 + STLINK_DEBUG_APIV2_SWD_SET_FREQ = 0x43, + STLINK_DEBUG_APIV3_SET_COM_FREQ = 0x61, + STLINK_DEBUG_APIV3_GET_COM_FREQ = 0x62, + STLINK_DEBUG_ENTER_SWD = 0xa3, + STLINK_DEBUG_ENTER_JTAG_NO_RESET = 0xa4, +}; + +enum stlink_dfu_commands { + STLINK_DFU_EXIT = 0x07 }; #endif // STLINK_COMMANDS_H_ diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 07971284f..18792c89f 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -470,7 +470,7 @@ int _stlink_sg_enter_jtag_mode(stlink_t *sl) { DLOG("\n*** stlink_enter_jtag_mode ***\n"); clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_ENTER; - sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_JTAG; + sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_JTAG_RESET; sl->q_len = 0; return(stlink_q(sl)); } @@ -570,7 +570,7 @@ int _stlink_sg_reset(stlink_t *sl) { int _stlink_sg_jtag_reset(stlink_t *sl, int value) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); - sg->cdb_cmd_blk[1] = STLINK_JTAG_DRIVE_NRST; + sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV2_DRIVE_NRST; sg->cdb_cmd_blk[2] = (value) ? 0 : 1; sl->q_len = 3; sg->q_addr = 2; @@ -876,7 +876,7 @@ int _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { int _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); - sg->cdb_cmd_blk[1] = STLINK_JTAG_WRITEDEBUG_32BIT; + sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; // 2-5: addr write_uint32(sg->cdb_cmd_blk + 2, addr); write_uint32(sg->cdb_cmd_blk + 6, data); @@ -888,7 +888,7 @@ int _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { int _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); - sg->cdb_cmd_blk[1] = STLINK_JTAG_READDEBUG_32BIT; + sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV2_READDEBUGREG; // 2-5: addr write_uint32(sg->cdb_cmd_blk + 2, addr); sl->q_len = 8; diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 1d26508eb..bbdc2c27b 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -158,30 +158,24 @@ int _stlink_usb_version(stlink_t *sl) { unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - uint32_t rep_len = 6; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_GET_VERSION; - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); - - if (size == -1) { - printf("[!] send_recv STLINK_GET_VERSION\n"); - return((int)size); - } + uint32_t rep_len; + int i; - /* STLINK-V3 requires a specific command */ if (sl->version.stlink_v == 3) { + // STLINK-V3 version is determined by another command rep_len = 12; i = fill_command(sl, SG_DXFER_FROM_DEV, 16); - cmd[i++] = STLINK_APIV3_GET_VERSION_EX; - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + cmd[i++] = STLINK_GET_VERSION_APIV3; + } else { + rep_len = 6; + i = fill_command(sl, SG_DXFER_FROM_DEV, 6); + cmd[i++] = STLINK_GET_VERSION; + } - if (size != (ssize_t)rep_len) { - printf("[!] send_recv STLINK_APIV3_GET_VERSION_EX\n"); - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + if (size != (ssize_t)rep_len) { + printf("[!] send_recv STLINK_GET_VERSION\n"); + return((int)size); } return(0); @@ -225,12 +219,12 @@ int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_JTAG_READDEBUG_32BIT; + cmd[i++] = STLINK_DEBUG_APIV2_READDEBUGREG; write_uint32(&cmd[i], addr); size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); if (size == -1) { - printf("[!] send_recv STLINK_JTAG_READDEBUG_32BIT\n"); + printf("[!] send_recv STLINK_DEBUG_APIV2_READDEBUGREG\n"); return((int)size); } @@ -248,13 +242,13 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_JTAG_WRITEDEBUG_32BIT; + cmd[i++] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; write_uint32(&cmd[i], addr); write_uint32(&cmd[i + 4], data); size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); if (size == -1) { - printf("[!] send_recv STLINK_JTAG_WRITEDEBUG_32BIT\n"); + printf("[!] send_recv STLINK_DEBUG_APIV2_WRITEDEBUGREG\n"); return((int)size); } @@ -543,12 +537,12 @@ int _stlink_usb_jtag_reset(stlink_t * sl, int value) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_JTAG_DRIVE_NRST; + cmd[i++] = STLINK_DEBUG_APIV2_DRIVE_NRST; cmd[i++] = value; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); if (size == -1) { - printf("[!] send_recv STLINK_JTAG_DRIVE_NRST\n"); + printf("[!] send_recv STLINK_DEBUG_APIV2_DRIVE_NRST\n"); return((int)size); } @@ -675,7 +669,7 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { i = fill_command(sl, SG_DXFER_FROM_DEV, 16); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_APIV3_GET_COM_FREQ; + cmd[i++] = STLINK_DEBUG_APIV3_GET_COM_FREQ; cmd[i++] = 0; // SWD mode size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52); @@ -694,13 +688,13 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { // Set to zero all the next entries for (i = speeds_size; i < STLINK_V3_MAX_FREQ_NB; i++) map[i] = 0; - if (!clk_freq) clk_freq = 1800; // set default frequency + if (!clk_freq) clk_freq = 1000; // set default frequency speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); i = fill_command(sl, SG_DXFER_FROM_DEV, 16); cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_APIV3_SET_COM_FREQ; + cmd[i++] = STLINK_DEBUG_APIV3_SET_COM_FREQ; cmd[i++] = 0; // SWD mode cmd[i++] = 0; cmd[i++] = (uint8_t)((map[speed_index] >> 0) & 0xFF); @@ -1180,10 +1174,9 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, int config; sl = calloc(1, sizeof(stlink_t)); - slu = calloc(1, sizeof(struct stlink_libusb)); - if (sl == NULL) { goto on_malloc_error; } + slu = calloc(1, sizeof(struct stlink_libusb)); if (slu == NULL) { goto on_malloc_error; } ugly_init(verbose); @@ -1345,18 +1338,20 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, int mode = stlink_current_mode(sl); if (mode == STLINK_DEV_DFU_MODE) { - // this seems to work, and is unnecessary information for the user. - // demoted to debug -- REW DLOG("-- exit_dfu_mode\n"); - stlink_exit_dfu_mode(sl); - } else if (mode == STLINK_DEV_DEBUG_MODE && - connect == CONNECT_UNDER_RESET) { + _stlink_usb_exit_dfu_mode(sl); + } + + if (connect == CONNECT_UNDER_RESET) { // for the connect under reset only // OpenOСD says (official documentation is not available) that // the NRST pin must be pull down before selecting the SWD/JTAG mode - WLOG("-- exit_debug_mode\n"); - stlink_exit_debug_mode(sl); - _stlink_usb_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); + if (mode == STLINK_DEV_DEBUG_MODE) { + DLOG("-- exit_debug_mode\n"); + _stlink_usb_exit_dfu_mode(sl); + } + + _stlink_usb_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); } sl->freq = freq; @@ -1364,7 +1359,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, // should be done at this speed too // set the stlink clock speed (default is 1800kHz) DLOG("JTAG/SWD freq set to %d\n", freq); - stlink_set_swdclk(sl, freq); + _stlink_usb_set_swdclk(sl, freq); stlink_target_connect(sl, connect); return(sl); @@ -1374,13 +1369,10 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, return(NULL); on_error: - if (slu->libusb_ctx) { libusb_exit(slu->libusb_ctx); } on_malloc_error: - if (sl != NULL) { free(sl); } - if (slu != NULL) { free(slu); } return(NULL); From ebba0f35e2ca971b929d8bd19484ec30cc54eabe Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 16 May 2021 18:26:52 +0200 Subject: [PATCH 1195/1435] General Project Update - [doc] Updated steps for release procedure - [doc] Removed outdated lists of supported devices - [doc] Updated list of supported OS - [doc] Updated version requirements - Cleanup for libusb installation routine on Windows - Updated list of contributors - Updated CHANGELOG.md - Updated README.md --- CHANGELOG.md | 7 ++ CMakeLists.txt | 2 +- README.md | 4 +- cmake/modules/Findlibusb.cmake | 22 ------ contributors.txt | 3 +- doc/devices_boards.md | 64 +----------------- doc/release.md | 8 ++- doc/version_support.md | 119 +++++++++++++++++++-------------- 8 files changed, 86 insertions(+), 143 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 1b003d97e..b43d58da7 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -4,8 +4,15 @@ Release date: 2021-xx-xx +This release drops support for some older operating systems. Check project README for details. +Updated system requirements: Raised minimum version for `cmake` to 3.7.2. + Features: +- Support for writing option bytes on STM32F0/F1/F3 ([#346](https://github.com/stlink-org/stlink/pull/346), [#458](https://github.com/stlink-org/stlink/pull/458), [#808](https://github.com/stlink-org/stlink/pull/808), [#1084](https://github.com/stlink-org/stlink/pull/1084), [#1112](https://github.com/stlink-org/stlink/pull/1112)) +- Added chip-IDs for STM32G0B0/G0B1/G0C1/G050/G051/G061 ([#1140](https://github.com/stlink-org/stlink/pull/1140)) +- Added option byte info for STM32F411XX ([#1141](https://github.com/stlink-org/stlink/pull/1141)) + Updates & changes: - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) diff --git a/CMakeLists.txt b/CMakeLists.txt index 064aa06d5..4bd76ebfb 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,7 +2,7 @@ # General cmake settings ### -cmake_minimum_required(VERSION 3.4.2) +cmake_minimum_required(VERSION 3.7.2) cmake_policy(SET CMP0042 NEW) set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) diff --git a/README.md b/README.md index acc2441f8..0b124d21d 100644 --- a/README.md +++ b/README.md @@ -53,9 +53,9 @@ The STlink toolset includes: ## Supported operating systems and hardware combinations -Currently known working combinations of programmers and targets are listed in [devices_boards.md](doc/devices_boards.md). +Currently known working MCU targets are listed in [devices_boards.md](doc/devices_boards.md). -Supported operating systems are listed in [version_support.md](doc/version_support.md). +A list of supported operating can be found in [version_support.md](doc/version_support.md). ## Tutorial & HOWTO diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index 257c682ce..d861bdd5f 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -54,28 +54,6 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to endif () if (WIN32 AND NOT EXISTS "/etc/debian_version") # Skip this for Debian... - FIND_PATH( - LIBUSB_INCLUDE_DIR NAMES libusb.h - HINTS /usr /usr/local /opt - PATH_SUFFIXES libusb-1.0 - ) - - if (MINGW OR MSYS) - set(LIBUSB_NAME usb-1.0) - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW${ARCH}/static - ) - else (MSVC) - set(LIBUSB_NAME libusb-1.0.lib) - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS ${LIBUSB_WIN_OUTPUT_FOLDER}/MS${ARCH}/dll - ) - endif () - endif () - - if (NOT LIBUSB_FOUND) # Preparations for installing libusb library set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) diff --git a/contributors.txt b/contributors.txt index 88f1f0c89..e7fc0f601 100644 --- a/contributors.txt +++ b/contributors.txt @@ -40,7 +40,7 @@ Fabien Chouteau [Fabien-Chouteau] Florian Hars Friedrich Beckmann Gabriel Górski [Glaeqen] -Geoffrey Brown +Geoffrey Brown [geoffreymbrown] George Talusan [gtalusan] Georg von Zengen Giuseppe Barba @@ -100,6 +100,7 @@ Peter Torelli [petertorelli] Peter Zotov Petteri Aimonen Piotr Haber +[RafaelLeeImg] Rene Hopf [rene-dev] Robin Kreis Roger Wolff [rewolff] diff --git a/doc/devices_boards.md b/doc/devices_boards.md index df4b5ed29..6548bc734 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -1,9 +1,7 @@ -# Boards supported by the STlink toolset +# MCUs supported by the STlink toolset The following devices are supported by the stlink toolset. -All Boards are expected to work with ST-LINK/V2 programmers. - **STM32F0 / ARM Cortex M0 / Core-ID: 0x0bb11477 (STM32F0_CORE_ID)** | Chip-ID | Product-Code | @@ -20,14 +18,6 @@ All Boards are expected to work with ST-LINK/V2 programmers. | 0x448 | STM32F0**72**xx | | 0x442 | STM32F0**9**xxx | -Tested boards [incl. STLINK programmers]: - -- Nucleo-F030R8 [v2-1] -- Nucleo-F072RB [v2-1] -- Nucleo-F091RC [v2-1] -- Nucleo-32 [v2-1] -- STM32F0-Discovery [v2] -- STM320518-EVAL **STM32F1 / ARM Cortex M3 / Core-ID: 0x1ba01477 (STM32F1_CORE_ID)** @@ -50,11 +40,8 @@ Tested boards [incl. STLINK programmers]: | 0x428 | High density Value | xC xD xE | F100 | | | | | | 0x430 | XL-Density | xF xG | | F101 | | F103 | | -Tested boards [incl. STLINK programmers]: +Tested non-official ST boards [incl. STLINK programmers]: -- STM32VL-Discovery (STM32F100RBT6) with STLINK/V1 [v1], [v2] -- STM32F103-Bluepill: C8Tx & R8xx [v2] -- Nucleo-F103RB [v2-1] - HY-STM32 (STM32F103VETx) [v1, v2] - DecaWave EVB1000 (STM32F105RCTx) [v1, v2] @@ -98,15 +85,6 @@ Tested boards [incl. STLINK programmers]: | 0x446 | _N/A_ | xD xE | | F302 | F303 | | | 0x446 | _N/A_ | - | | | | F398 | -Tested boards [incl. STLINK programmers]: - -- Nucleo-F302K8 [v2-1] -- Nucleo-F303K8 [v2-1] -- Nucleo-F303RE [v2-1] -- Nucleo-F334R8 [v2-1] -- STM32F303-Discovery [v2] -- STM32F3348-Discovery [v2-1] - **STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3c_CORE_ID)** | Product-Code | Chip-ID | STLINK
      Programmer | Boards | @@ -134,16 +112,6 @@ Tested boards [incl. STLINK programmers]: | 0x463 | STM32F4**13**xx | | 0x463 | STM32F4**23**xx | -Tested boards [incl. STLINK programmers]: - -- Nucleo-F401RE [v2-1] -- Nucleo-F411RE [v2-1] -- STM32F407-Discovery [v2] -- STM32F411E-Discovery with gyro, audio [v2] -- STM32F413H-Discovery [v2-1] -- STM32F429I-Discovery with LCD [v2] -- STM32F439VIT6-Discovery [v2] (reseated MCU) - **STM32F7 / ARM Cortex M7F / Core-ID: 0x5ba02477 (STM32F7_CORE_ID)** | Chip-ID | Product-Code | @@ -155,23 +123,12 @@ Tested boards [incl. STLINK programmers]: | 0x451 | STM32F7**6**xxx | | 0x451 | STM32F7**7**xxx | -Tested boards [incl. STLINK programmers]: - -- Nucleo-F722ZE [v2-1] -- Nucleo-F746ZG [v2-1] -- STM32F756NGHx evaluation board [v2-1] -- STM32F769I-Discovery [v2-1] - **STM32H7 / ARM Cortex M7F / Core-ID: 0x6ba02477 (STM32H7_CORE_ID)** | Chip-ID | Product-Code | | ------- | -------------- | | 0x450 | STM32H74x/H75x | -Tested boards [incl. STLINK programmers]: - -- Nucleo-H745I-Q [v3] - **STM32G0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32G0_CORE_ID)** | Chip-ID | Product-Code | @@ -203,10 +160,6 @@ Tested boards [incl. STLINK programmers]: | 0x447 | STM32L0**7**xxx | | 0x447 | STM32L0**8**xxx | -Tested boards [incl. STLINK programmers]: - -- Nucleo-L053R8 [v2-1] - **STM32L1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32L1_CORE_ID)** | Chip-ID | Product-Code | @@ -221,11 +174,6 @@ Tested boards [incl. STLINK programmers]: | 0x436 | STM32L1xxx**D** | | 0x437 | STM32L1xxx**E** | -Tested boards [incl. STLINK programmers]: - -- Nucleo-L152RE [v2-1] -- STM32L152C-Discovery [v2] - **STM32L4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32L4_CORE_ID)** | Chip-ID | Product-Code | @@ -245,14 +193,6 @@ Tested boards [incl. STLINK programmers]: | 0x471 | STM32L4**P5**xx | | 0x471 | STM32L4**Q5**xx | -Tested boards [incl. STLINK programmers]: - -- Nucleo-L432KC [v2-1] -- Nucleo-L452RE [v2-1] -- Nucleo-L476RG [v2-1] -- Nucleo-L496ZG [v2-1] -- STM32L4R9I-Discovery [v2-1] - **STM32W / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32W_CORE_ID)** | Chip-ID | Product-Code | diff --git a/doc/release.md b/doc/release.md index a67fcd743..6321e8ab2 100644 --- a/doc/release.md +++ b/doc/release.md @@ -6,6 +6,8 @@ This document describes the necessary steps for developers to create a release: 1. Update `CHANGELOG.md`, `cmake/packaging/deb/changelog` & `cmake/packaging/rpm/changelog` 2. Update `.version` with semantic version: `x.x.x` 3. Update `README.md` with semantic version `x.x.x` in commits badge -4. Create and push git tag and commits `git tag x.x.x` -5. Create binary packages (.rpm / .deb / .zip) with `make package && sh ./cmake/packaging/windows/generate_binaries.sh` -6. Upload packages to the [release page](https://github.com/stlink-org/stlink/releases) of this project +4. Merge `develop` into `master` +5. Create and push git tag and commits `git tag x.x.x` +6. Create binary packages (.rpm / .deb / .zip) with `make package && sh ./cmake/packaging/windows/generate_binaries.sh` +7. Upload packages to the [release page](https://github.com/stlink-org/stlink/releases) of this project +8. Merge `master` into `develop` diff --git a/doc/version_support.md b/doc/version_support.md index 5d2cdd375..6aafc8112 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,13 +1,11 @@ -_Source:_ pkgs.org - [libusb](https://pkgs.org/search/?q=libusb); [cmake](https://pkgs.org/search/?q=cmake); [gtk](https://pkgs.org/search/?q=gtk) (as of Apr 2020) +_Source:_ pkgs.org - [libusb](https://pkgs.org/search/?q=libusb); [cmake](https://pkgs.org/search/?q=cmake); [gtk](https://pkgs.org/search/?q=gtk) (as of May 2021) ## Supported Operating Systems ### Microsoft Windows -On Windows users should ensure that cmake 3.17.0 is installed.
      -Up on compiling c-make will check **automatically**, whether `libusb` 1.0.20 or later is present.
      -If this is not the case, the installation routine will download the latest version (1.0.23 at the time of writing).
      -Thus no user interaction regarding libusb is necessary. +On Windows users should ensure that cmake 3.17.0 or any later version is installed.
      +Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb` (1.0.23 at the time of writing). - Windows 10 - Windows 8.1 @@ -23,55 +21,72 @@ NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 a ### Linux-/Unix-based: -| Operating System | libusb
      version | cmake
      version | gtk-3
      version | Notes | -| -------------------------------- | ----------------------- | ------------------ | ----------------------------------------- | ----------------------------------------------------------------------------- | -| Alpine Edge | 1.0.23 | 3.17.0 | 3.99.0
      gtk+3.0 | | -| ALT Linux Sisyphus | 1.0.23 | 3.17.0 | 3.24.18
      libgtk+3 | | -| Arch Linux | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | -| Fedora Rawhide | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | -| KaOS | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | | -| OpenMandriva Cooker | 1.0.23 | 3.17.0 | 3.24.18
      libgtk+3.0
      lib64gtk+3.0 | | -| PCLinuxOS | 1.0.23
      lib64usb1.0 | 3.17.0 | 3.24.18
      lib64gtk+3.0 | | -| Slackware Current | 1.0.23 | 3.17.0 | 3.24.18
      gtk+3 | | -| Solus | 1.0.23 | 3.16.5 | 3.24.16
      libgtk-3 | | -| Debian Sid | 1.0.23 | 3.16.3 | 3.24.18
      libgtk-3 | | -| OpenMandriva Lx 4.1 | 1.0.23 | 3.16.3 | 3.24.13
      libgtk+3.0
      lib64gtk+3.0 | | -| Ubuntu 20.04 LTS (Focal Fossa) | 1.0.23 | 3.16.3 | 3.24.17
      libgtk-3 | | -| openSUSE Tumbleweed | 1.0.23 | 3.16.2 | 3.24.16
      gtk3 | | -| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.13
      gtk+3.0 | | -| Ubuntu 19.10 (Eoan Ermine) | 1.0.23 | 3.13.4 | 3.24.12
      libgtk-3 | | -| Mageia Cauldron | 1.0.22 | 3.17.0 | 3.24.18
      libgtk+3.0
      lib64gtk+3.0 | | -| NetBSD 9.0 | 1.0.22 | 3.16.1 | 3.24.12
      gtk+3 | | -| NetBSD 8.1 | 1.0.22 | 3.16.1 | 3.24.12
      gtk+3 | | -| NetBSD 7.2 | 1.0.22 | 3.16.1 | _N/A_ | | -| Alpine 3.10 | 1.0.22 | 3.14.5 | 3.24.8
      gtk+3.0 | | -| Fedora 31 | 1.0.22 | 3.14.5 | 3.24.12
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | -| Mageia 7.1 | 1.0.22 | 3.14.3 | 3.24.8
      libgtk+3.0
      lib64gtk+3.0 | | -| Fedora 30 | 1.0.22 | 3.14.2 | 3.24.8
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | -| Debian 10 (Buster) | 1.0.22 | 3.13.4 | 3.24.5
      libgtk-3 | | -| Alpine 3.9 | 1.0.22 | 3.13.0 | 3.24.1
      gtk+3.0 | | -| CentOS 8 | 1.0.22 | 3.11.4 | 3.22.30
      gtk3 | named `libusbx`, but
      `libusb`-codebase is used | -| openSUSE Leap 15.2 | 1.0.21 | 3.15.5 | 3.24.14
      gtk3 | | -| openSUSE Leap 15.1 | 1.0.21 | 3.10.2 | 3.22.30
      gtk3 | | -| Ubuntu 18.04 LTS (Bionic Beaver) | 1.0.21 | 3.10.2 | 3.22.30
      libgtk-3 | | -| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | 3.22.11
      libgtk-3 | | -| Slackware 14.2 | 1.0.20 | 3.5.2 | 3.18.9
      gtk+3 | | -| Ubuntu 16.04 LTS (Xenial Xerus) | 1.0.20 | 3.5.1 | 3.18.9
      libgtk-3 | | -| OpenMandriva Lx 3.0x | 1.0.20 | **3.4.2** | 3.18.9
      libgtk+3.0
      lib64gtk+3.0 | | -| FreeBSD 13 | **1.0.16 - 1.0.18** | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-13.0r358841
      LIBUSB_API_VERSION 0x01000102
      (integrated) | -| FreeBSD 12 | **1.0.16 - 1.0.18** | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-13.0r358841
      LIBUSB_API_VERSION 0x01000102
      (integrated) | -| FreeBSD 11 | **1.0.16 - 1.0.18** | 3.15.5 | 3.24.10
      gtk3 | linux_libusb-13.0r358841
      LIBUSB_API_VERSION 0x01000102
      (integrated) | +| Operating System | libusb | cmake | gtk-3 | Notes | +| ------------------------- | ------------------ | --------- | ----------- | ----------------------------- | +| Arch Linux | 1.0.24 | 3.20.2 | 3.24.29 | | +| Fedora Rawhide [x64] | 1.0.24 (`libusbx`) | 3.20.2 | 3.24.29 | | +| KaOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| Mageia Cauldron | 1.0.24 | 3.20.2 | 3.24.29 | | +| OpenMandriva Cooker | 1.0.24 | 3.20.2 | 3.24.29 | | +| OpenMandriva Rolling | 1.0.24 | 3.20.2 | 3.24.29 | | +| PCLinuxOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| Slackware Current | 1.0.24 | 3.20.2 | 3.24.28 | | +| Solus [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| openSUSE Tumbleweed [x64] | 1.0.24 | 3.20.1 | 3.24.29 | | +| ALT Linux Sisyphus | 1.0.24 | 3.19.7 | 3.24.29 | | +| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | +| NetBSD 9.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | +| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | | +| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | | +| Debian Sid | 1.0.24 | 3.18.4 | 3.24.24 | | +| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | +| Ubuntu 21.04 (Hirsute) | 1.0.24 | 3.18.4 | 3.24.25 | | +| Fedora 33 [x64] | 1.0.23 (`libusbx`) | 3.18.3 | 3.24.23 | | +| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.18.2 | **3.22.30** | | +| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | | +| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | | +| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.17.0 | 3.24.**14** | | +| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | +| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | +| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.**11** | | +| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.**13** | | +| Mageia 7.1 | 1.0.**22** | 3.14.3 | 3.24.**8** | | +| Debian 10 (Buster) | 1.0.**22** | 3.13.4 | 3.24.**5** | | +| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.11.4 | 3.24.32 | | +| CentOS 8 [x64] | 1.0.23 (`libusbx`) | 3.11.4 | **3.22.30** | | +| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.10.2 | **3.22.30** | | +| Debian 9 (Stretch) | 1.0.**21** | **3.7.2** | **3.22.11** | | +| | | | | | +| FreeBSD 13.x | 1.0.**16 - 18** | 3.20.2 | 3.24.27 | LIBUSB_API_VERSION 0x01000102 | +| FreeBSD 12.x | 1.0.**16 - 18** | 3.19.6 | 3.24.27 | LIBUSB_API_VERSION 0x01000102 | +| FreeBSD 11.x | 1.0.**16 - 18** | 3.15.5 | 3.24.27 | LIBUSB_API_VERSION 0x01000102 | -## Unsupported Operating Systems (as of Release v1.6.1) +## Unsupported Operating Systems (as of Release v1.7.1) -| Operating System | libusb
      version | cmake
      version | End of
      OS-Support | Notes | -| ------------------------------ | ------------------- | ------------------ | ---------------------- | --------------------------------------------------- | -| CentOS 7 | 1.0.21 | **2.8.12.2** | | named `libusbx`, but
      `libusb`-codebase is used | -| Debian 8 (Jessie) | 1.0.19 | **3.0.2** | Jun 2020 | -| Ubuntu 14.04 LTS (Trusty Tahr) | 1.0.17 | **2.8.12.2** | Apr 2019 | -| CentOS 6 | 1.0.**9** | **2.8.12.2** | Dec 2020 | named `libusbx`, but
      `libusb`-codebase is used | -| Slackware 14.1 | 1.0.**9** | **2.8.12** | | -| Slackware 14.0 | 1.0.**9** | **2.8.8** | | +Systems with highlighted versions remain compatible with this toolset. + +| Operating System | libusb | cmake | End of
      OS-Support | +| ------------------------- | ---------------------- | ---------- | ---------------------- | +| Fedora 32 [x64] | **1.0.23** (`libusbx`) | **3.17.0** | May 2021 | +| Ubuntu 20.10 (Groovy) | **1.0.23** | **3.16.3** | Jul 2021 | +| NetBSD 7.x | **1.0.22** | **3.16.1** | Jun 2020 | +| Alpine 3.10 | **1.0.22** | **3.14.5** | May 2021 | +| Fedora 31 [x64] | **1.0.22** (`libusbx`) | **3.14.5** | Nov 2020 | +| Ubuntu 19.10 (Eoan) | **1.0.23** | **3.13.4** | Jul 2020 | +| Fedora 30 | **1.0.22** (`libusbx`) | **3.14.2** | May 2020 | +| Alpine 3.9 | **1.0.22** | **3.13.0** | Jan 2021 | +| openSUSE Leap 15.1 [x64] | **1.0.21** | **3.10.2** | Feb 2021 | +| Slackware 14.2 | 1.0.20 | 3.5.2 | | +| Ubuntu 16.04 LTS (Xenial) | 1.0.20 | 3.5.1 | Apr 2021 | +| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | +| Debian 8 (Jessie) | 1.0.19 | 3.0.2 | Jun 2020 | +| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | | +| Ubuntu 14.04 LTS (Trusty) | 1.0.17 | 2.8.12.2 | Apr 2019 | +| CentOS 6 | 1.0.9 (`libusbx`) | 2.8.12.2 | Dec 2020 | +| Slackware 14.1 | 1.0.9 | 2.8.12 | | +| Slackware 14.0 | 1.0.9 | 2.8.8 | | _All other operating systems which are not listed are unsupported._ From 03ad4a434d4d6496a05885ddce9568b5884a2c2d Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 17 May 2021 00:20:54 +0500 Subject: [PATCH 1196/1435] Added checking the command execution status --- inc/stlink.h | 13 +++ src/common.c | 23 +++-- src/stlink-lib/usb.c | 211 ++++++++++++++++++++++--------------------- 3 files changed, 132 insertions(+), 115 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 3bc518c87..69a4799f5 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -83,6 +83,19 @@ enum target_state { #define STLINK_F_HAS_DPBANKSEL (1 << 8) #define STLINK_F_HAS_RW8_512BYTES (1 << 9) +/* Error code */ +#define STLINK_DEBUG_ERR_OK 0x80 +#define STLINK_DEBUG_ERR_FAULT 0x81 +#define STLINK_DEBUG_ERR_AP_WAIT 0x10 +#define STLINK_DEBUG_ERR_AP_FAULT 0x11 +#define STLINK_DEBUG_ERR_AP_ERROR 0x12 +#define STLINK_DEBUG_ERR_DP_WAIT 0x14 +#define STLINK_DEBUG_ERR_DP_FAULT 0x15 +#define STLINK_DEBUG_ERR_DP_ERROR 0x16 + +#define CMD_NO_RETRY 0 +#define CMD_USE_RETRY 3 + #define C_BUF_LEN 32 enum stlink_flash_type { diff --git a/src/common.c b/src/common.c index ee91fa487..661ee34ec 100644 --- a/src/common.c +++ b/src/common.c @@ -1443,12 +1443,10 @@ void stlink_close(stlink_t *sl) { int stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); - if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN) { + if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN && + sl->core_stat != TARGET_RESET) { // stop debugging if the target has been identified - int ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); - if (ret == -1) { - return (ret); - } + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); } return (sl->backend->exit_debug_mode(sl)); @@ -1684,7 +1682,7 @@ int stlink_load_device_params(stlink_t *sl) { } int stlink_jtag_reset(stlink_t *sl, int value) { - DLOG("*** stlink_jtag_reset ***\n"); + DLOG("*** stlink_jtag_reset %d ***\n", value); return (sl->backend->jtag_reset(sl, value)); } @@ -1768,6 +1766,8 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { DLOG("*** stlink_reset ***\n"); + sl->core_stat = TARGET_RESET; + if (type == RESET_AUTO) { // clear S_RESET_ST in DHCSR register for reset state detection stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); @@ -1781,9 +1781,7 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { usleep(100); stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); } - if (sl->backend->reset(sl)) { - return (-1); - } + sl->backend->reset(sl); usleep(10000); } @@ -1793,8 +1791,8 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ dhcsr = 0; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) { // reset not done yet // try reset through AIRCR so that NRST does not need to be connected @@ -1808,8 +1806,9 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { while (time_ms() < timeout) { dhcsr = STLINK_REG_DHCSR_S_RESET_ST; stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { return (0); + } } return (-1); diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index bbdc2c27b..5e17189c6 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -84,50 +84,80 @@ void _stlink_usb_close(stlink_t* sl) { } ssize_t send_recv(struct stlink_libusb* handle, int terminate, - unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, size_t rxsize) { + unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, + size_t rxsize, bool check_error, int retry_cnt) { // Note: txbuf and rxbuf can point to the same area - int res = 0; - int t; + int res, t, retry = 0; + int cmd = read_uint16(txbuf, (handle->protocoll == 1)?15:0); - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int)txsize, &res, 3000); - - if (t) { - printf("[!] send_recv send request failed: %s\n", libusb_error_name(t)); - return(-1); - } else if ((size_t)res != txsize) { - printf("[!] send_recv send request wrote %u bytes (instead of %u).\n", - (unsigned int)res, (unsigned int)txsize); - } - - if (rxsize != 0) { - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int)rxsize, &res, 3000); + while (1) { + res = 0; + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int)txsize, &res, 3000); if (t) { - printf("[!] send_recv read reply failed: %s\n", libusb_error_name(t)); + ELOG("[!] send_recv send request failed: %s (command 0x%02X)\n", libusb_error_name(t), cmd); return(-1); + } else if ((size_t)res != txsize) { + ELOG("[!] send_recv send request wrote %u bytes, instead of %u (command 0x%02X)\n", + (unsigned int)res, (unsigned int)txsize, cmd); } - } - if ((handle->protocoll == 1) && terminate) { - // read the SG reply - unsigned char sg_buf[13]; - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); + if (rxsize != 0) { + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int)rxsize, &res, 3000); - if (t) { - printf("[!] send_recv read storage failed: %s\n", libusb_error_name(t)); - return(-1); + if (t) { + ELOG("[!] send_recv read reply failed: %s (command 0x%02X)\n", libusb_error_name(t), cmd); + return(-1); + } + + /* Checking the command execution status stored in the first byte of the response */ + if (handle->protocoll != 1 && check_error && + rxbuf[0] != STLINK_DEBUG_ERR_OK) { + switch(rxbuf[0]) { + case STLINK_DEBUG_ERR_AP_WAIT: + case STLINK_DEBUG_ERR_DP_WAIT: + if (retry < retry_cnt) { + unsigned int delay_us = (1<sg_transfer_idx++; - } + if ((handle->protocoll == 1) && terminate) { + // read the SG reply + unsigned char sg_buf[13]; + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); + + if (t) { + ELOG("[!] send_recv read storage failed: %s (command 0x%02X)\n", libusb_error_name(t), cmd); + return(-1); + } + + // The STLink doesn't seem to evaluate the sequence number. + handle->sg_transfer_idx++; + } - return(res); + return(res); + } } static inline int send_only(struct stlink_libusb* handle, int terminate, unsigned char* txbuf, size_t txsize) { - return((int)send_recv(handle, terminate, txbuf, txsize, NULL, 0)); + return((int)send_recv(handle, terminate, txbuf, txsize, NULL, 0, false, CMD_NO_RETRY)); } @@ -149,7 +179,6 @@ static int fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t cmd[i++] = 0; // logical unit cmd[i++] = 0xa; // command length } - return(i); } @@ -172,9 +201,8 @@ int _stlink_usb_version(stlink_t *sl) { cmd[i++] = STLINK_GET_VERSION; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_USE_RETRY); if (size != (ssize_t)rep_len) { - printf("[!] send_recv STLINK_GET_VERSION\n"); return((int)size); } @@ -193,10 +221,9 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { cmd[i++] = STLINK_GET_TARGET_VOLTAGE; - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, false, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_GET_TARGET_VOLTAGE\n"); + if (size < 0) { return(-1); } else if (size != 8) { printf("[!] wrong length STLINK_GET_TARGET_VOLTAGE\n"); @@ -221,10 +248,9 @@ int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_READDEBUGREG; write_uint32(&cmd[i], addr); - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_APIV2_READDEBUGREG\n"); + if (size < 0) { return((int)size); } @@ -245,10 +271,9 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { cmd[i++] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; write_uint32(&cmd[i], addr); write_uint32(&cmd[i + 4], data); - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_APIV2_WRITEDEBUGREG\n"); + if (size < 0) { return((int)size); } @@ -269,10 +294,10 @@ int _stlink_usb_get_rw_status(stlink_t *sl) { if (sl->version.flags & STLINK_F_HAS_GETLASTRWSTATUS2) { cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS2; - ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 12); + ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 12, true, CMD_NO_RETRY); } else { cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS; - ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2); + ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2, true, CMD_NO_RETRY); } if (ret < 0) { return(-1); } @@ -334,10 +359,9 @@ int _stlink_usb_current_mode(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_GET_CURRENT_MODE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_GET_CURRENT_MODE\n"); + if (size < 0) { return(-1); } @@ -362,10 +386,9 @@ int _stlink_usb_core_id(stlink_t * sl) { offset = 4; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_READCOREID\n"); + if (size < 0) { return(-1); } @@ -408,10 +431,9 @@ int _stlink_usb_status(stlink_t * sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_GETSTATUS; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_GETSTATUS\n"); + if (size < 0) { return((int)size); } @@ -450,10 +472,9 @@ int _stlink_usb_force_debug(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_FORCEDEBUG; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_FORCEDEBUG\n"); + if (size < 0) { return((int)size); } @@ -472,10 +493,9 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { // select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). cmd[i++] = sl->version.jtag_api == STLINK_JTAG_API_V1 ? STLINK_DEBUG_APIV1_ENTER : STLINK_DEBUG_APIV2_ENTER; cmd[i++] = STLINK_DEBUG_ENTER_SWD; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_ENTER\n"); + if (size < 0) { return((int)size); } @@ -518,10 +538,9 @@ int _stlink_usb_reset(stlink_t * sl) { cmd[i++] = STLINK_DEBUG_APIV2_RESETSYS; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_RESETSYS\n"); + if (size < 0) { return((int)size); } @@ -539,10 +558,9 @@ int _stlink_usb_jtag_reset(stlink_t * sl, int value) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_DRIVE_NRST; cmd[i++] = value; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_APIV2_DRIVE_NRST\n"); + if (size < 0) { return((int)size); } @@ -571,10 +589,9 @@ int _stlink_usb_step(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_STEPCORE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_STEPCORE\n"); + if (size < 0) { return((int)size); } @@ -607,10 +624,9 @@ int _stlink_usb_run(stlink_t* sl, enum run_type type) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_RUNCORE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_RUNCORE\n"); + if (size < 0) { return((int)size); } @@ -655,10 +671,9 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { cmd[i++] = STLINK_DEBUG_APIV2_SWD_SET_FREQ; cmd[i++] = clk_divisor & 0xFF; cmd[i++] = (clk_divisor >> 8) & 0xFF; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_APIV2_SWD_SET_FREQ\n"); + if (size < 0) { return((int)size); } @@ -671,10 +686,9 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV3_GET_COM_FREQ; cmd[i++] = 0; // SWD mode - size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52, true, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_APIV3_GET_COM_FREQ\n"); + if (size < 0) { return((int)size); } @@ -702,10 +716,9 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { cmd[i++] = (uint8_t)((map[speed_index] >> 16) & 0xFF); cmd[i++] = (uint8_t)((map[speed_index] >> 24) & 0xFF); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8, true, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_APIV3_SET_COM_FREQ\n"); + if (size < 0) { return((int)size); } @@ -747,10 +760,9 @@ int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { cmd[i++] = STLINK_DEBUG_READMEM_32BIT; write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, len, false, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_READMEM_32BIT\n"); + if (size < 0) { return((int)size); } @@ -776,10 +788,9 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { cmd[i++] = STLINK_DEBUG_APIV2_READALLREGS; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_READALLREGS\n"); + if (size < 0) { return((int)size); } @@ -827,10 +838,9 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { } cmd[i++] = (uint8_t)r_idx; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_READREG\n"); + if (size < 0) { return((int)size); } @@ -994,10 +1004,9 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { cmd[i++] = idx; write_uint32(&cmd[i], reg); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - if (size == -1) { - printf("[!] send_recv STLINK_DEBUG_WRITEREG\n"); + if (size < 0) { return((int)size); } @@ -1020,10 +1029,9 @@ int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); write_uint32(&cmd[i + 2], frequency); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_only STLINK_DEBUG_APIV2_START_TRACE_RX\n"); + if (size < 0) { return((int)size); } @@ -1044,10 +1052,9 @@ int _stlink_usb_disable_trace(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); - if (size == -1) { - printf("[!] send_only STLINK_DEBUG_APIV2_STOP_TRACE_RX\n"); + if (size < 0) { return((int)size); } @@ -1066,14 +1073,12 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_GET_TRACE_NB; - ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len); + ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_NO_RETRY); - if (send_size == -1) { - printf("[!] send_recv STLINK_DEBUG_APIV2_GET_TRACE_NB\n"); + if (send_size < 0) { return((int)send_size); - } - if (send_size != 2) { - printf("[!] send_recv STLINK_DEBUG_APIV2_GET_TRACE_NB %d\n", (int)send_size); + } else if (send_size != 2) { + ELOG("STLINK_DEBUG_APIV2_GET_TRACE_NB reply size %d\n", (int)send_size); return -1; } From 620b52995667e5c39e8260e579e76b8d6d1a4fc5 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 16 May 2021 22:27:14 +0200 Subject: [PATCH 1197/1435] Aligned naming scheme for chip-ID files --- config/chips/F04x.chip | 4 +- config/chips/F07x.chip | 4 +- config/chips/{F09X.chip => F09x.chip} | 6 +- config/chips/F0xx small.chip | 4 +- config/chips/F0xx.chip | 4 +- ...1xx XL-density.chip => F1 XL-density.chip} | 6 +- ...ty line.chip => F1 connectivity line.chip} | 6 +- ...High-density.chip => F1 high-density.chip} | 6 +- ...ensity device.chip => F1 low-density.chip} | 6 +- ...um-density.chip => F1 medium-density.chip} | 6 +- ...e.chip => F1 value line high-density.chip} | 6 +- ...1xx Value Line.chip => F1 value line.chip} | 6 +- config/chips/{F2xx.chip => F2.chip} | 6 +- config/chips/F303 high density.chip | 4 +- config/chips/F334 medium density.chip | 4 +- config/chips/{F3xx.chip => F37x.chip} | 6 +- config/chips/F3xx small.chip | 4 +- config/chips/F410.chip | 4 +- .../chips/{stm32f411re.chip => F411xx.chip} | 6 +- config/chips/F412.chip | 4 +- config/chips/F413.chip | 4 +- config/chips/F42x_F43x.chip | 4 +- config/chips/F446.chip | 4 +- config/chips/F46x_F47x.chip | 4 +- ...ncy).chip => F4xx dynamic efficiency.chip} | 6 +- ...x (low power).chip => F4xx low power.chip} | 6 +- config/chips/F4xx.chip | 4 +- config/chips/F72x_F73x.chip | 4 +- config/chips/F76xxx.chip | 4 +- config/chips/F7xx.chip | 4 +- config/chips/G030_G031_G041.chip | 4 +- config/chips/G070_G071_G081.chip | 4 +- .../{G4 Category-2.chip => G4 cat2.chip} | 6 +- .../{G4 Category-3.chip => G4 cat3.chip} | 6 +- config/chips/H72x_H73x.chip | 4 +- config/chips/H74x_H75x.chip | 4 +- config/chips/H7Ax_H7Bx.chip | 4 +- config/chips/L011.chip | 4 +- config/chips/L0x3.chip | 4 +- .../{L0xx Category 2.chip => L0xx cat2.chip} | 6 +- .../{L0xx Category 5.chip => L0xx cat5.chip} | 6 +- config/chips/L152RE.chip | 4 +- .../chips/{L1xx Cat.2.chip => L1xx cat2.chip} | 6 +- ...gh-density.chip => L1xx high-density.chip} | 6 +- ...-density.chip => L1xx medium-density.chip} | 6 +- ...ity.chip => L1xx medium-plus-density.chip} | 6 +- config/chips/L41x.chip | 4 +- config/chips/L43x_L44x.chip | 4 +- .../chips/{L45x_46x.chip => L45x_L46x.chip} | 6 +- config/chips/L496x_L4A6x.chip | 4 +- config/chips/L4Rx.chip | 4 +- config/chips/L4xx.chip | 4 +- config/chips/WB55.chip | 4 +- config/chips/unknown device.chip | 4 +- config/udev/rules.d/49-stlinkv1.rules | 2 +- config/udev/rules.d/49-stlinkv2-1.rules | 2 +- config/udev/rules.d/49-stlinkv2.rules | 2 +- doc/tutorial.md | 26 +-- src/common.c | 56 +++--- src/st-util/gdb-server.c | 10 +- src/stlink-lib/chipid.c | 177 +++++++++--------- src/stlink-lib/chipid.h | 66 ++++--- src/stlink-lib/flash_loader.c | 42 ++--- 63 files changed, 319 insertions(+), 324 deletions(-) rename config/chips/{F09X.chip => F09x.chip} (69%) rename config/chips/{F1xx XL-density.chip => F1 XL-density.chip} (62%) rename config/chips/{F1 Connectivity line.chip => F1 connectivity line.chip} (59%) rename config/chips/{F1xx High-density.chip => F1 high-density.chip} (60%) rename config/chips/{F1 Low-density device.chip => F1 low-density.chip} (58%) rename config/chips/{F1xx Medium-density.chip => F1 medium-density.chip} (59%) rename config/chips/{F1xx High-density value line.chip => F1 value line high-density.chip} (54%) rename config/chips/{F1xx Value Line.chip => F1 value line.chip} (62%) rename config/chips/{F2xx.chip => F2.chip} (71%) rename config/chips/{F3xx.chip => F37x.chip} (69%) rename config/chips/{stm32f411re.chip => F411xx.chip} (65%) rename config/chips/{F4xx (Dynamic Efficency).chip => F4xx dynamic efficiency.chip} (57%) rename config/chips/{F4xx (low power).chip => F4xx low power.chip} (61%) rename config/chips/{G4 Category-2.chip => G4 cat2.chip} (64%) rename config/chips/{G4 Category-3.chip => G4 cat3.chip} (64%) rename config/chips/{L0xx Category 2.chip => L0xx cat2.chip} (63%) rename config/chips/{L0xx Category 5.chip => L0xx cat5.chip} (63%) rename config/chips/{L1xx Cat.2.chip => L1xx cat2.chip} (65%) rename config/chips/{L1xx High-density.chip => L1xx high-density.chip} (62%) rename config/chips/{L1xx Medium-density.chip => L1xx medium-density.chip} (59%) rename config/chips/{L1xx Medium-Plus-density.chip => L1xx medium-plus-density.chip} (57%) rename config/chips/{L45x_46x.chip => L45x_L46x.chip} (66%) diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 72db26f8c..059ae5bc6 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -1,8 +1,8 @@ -# Chipid file for F04x +# Chip-ID file for F04x # chip_id 445 description F04x -flash_type 1 +flash_type 1 flash_pagesize 400 sram_size 1800 bootrom_base 1fffec00 diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index cfedfa76f..ba839baed 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -1,8 +1,8 @@ -# Chipid file for F07x +# Chip-ID file for F07x # chip_id 448 description F07x -flash_type 1 +flash_type 1 flash_pagesize 800 sram_size 4000 bootrom_base 1fffc800 diff --git a/config/chips/F09X.chip b/config/chips/F09x.chip similarity index 69% rename from config/chips/F09X.chip rename to config/chips/F09x.chip index a622cf2f5..727fc1fa4 100644 --- a/config/chips/F09X.chip +++ b/config/chips/F09x.chip @@ -1,8 +1,8 @@ -# Chipid file for F09X +# Chip-ID file for F09x # chip_id 442 -description F09X -flash_type 1 +description F09x +flash_type 1 flash_pagesize 800 sram_size 8000 bootrom_base 1fffd800 diff --git a/config/chips/F0xx small.chip b/config/chips/F0xx small.chip index 65aea58ac..efa51c284 100644 --- a/config/chips/F0xx small.chip +++ b/config/chips/F0xx small.chip @@ -1,8 +1,8 @@ -# Chipid file for F0xx small +# Chip-ID file for F0xx small # chip_id 444 description F0xx small -flash_type 1 +flash_type 1 flash_pagesize 400 sram_size 1000 bootrom_base 1fffec00 diff --git a/config/chips/F0xx.chip b/config/chips/F0xx.chip index 5a5529412..9c0f60bd9 100644 --- a/config/chips/F0xx.chip +++ b/config/chips/F0xx.chip @@ -1,8 +1,8 @@ -# Chipid file for F0xx +# Chip-ID file for F0xx # chip_id 440 description F0xx -flash_type 1 +flash_type 1 flash_pagesize 400 sram_size 2000 bootrom_base 1fffec00 diff --git a/config/chips/F1xx XL-density.chip b/config/chips/F1 XL-density.chip similarity index 62% rename from config/chips/F1xx XL-density.chip rename to config/chips/F1 XL-density.chip index a7125a429..70cdfd3bb 100644 --- a/config/chips/F1xx XL-density.chip +++ b/config/chips/F1 XL-density.chip @@ -1,8 +1,8 @@ -# Chipid file for F1xx XL-density +# Chip-ID file for F1 XL-density # chip_id 430 -description F1xx XL-density -flash_type 2 +description F1 XL-density +flash_type 2 flash_pagesize 800 sram_size 18000 bootrom_base 1fffe000 diff --git a/config/chips/F1 Connectivity line.chip b/config/chips/F1 connectivity line.chip similarity index 59% rename from config/chips/F1 Connectivity line.chip rename to config/chips/F1 connectivity line.chip index 676fd1945..14678112d 100644 --- a/config/chips/F1 Connectivity line.chip +++ b/config/chips/F1 connectivity line.chip @@ -1,8 +1,8 @@ -# Chipid file for F1 Connectivity line +# Chip-ID file for F1 connectivity line # chip_id 418 -description F1 Connectivity line -flash_type 1 +description F1 connectivity line +flash_type 1 flash_pagesize 800 sram_size 10000 bootrom_base 1fffb000 diff --git a/config/chips/F1xx High-density.chip b/config/chips/F1 high-density.chip similarity index 60% rename from config/chips/F1xx High-density.chip rename to config/chips/F1 high-density.chip index ed02e691a..3d4cff724 100644 --- a/config/chips/F1xx High-density.chip +++ b/config/chips/F1 high-density.chip @@ -1,8 +1,8 @@ -# Chipid file for F1xx High-density +# Chip-ID file for F1 high-density # chip_id 414 -description F1xx High-density -flash_type 1 +description F1 high-density +flash_type 1 flash_pagesize 800 sram_size 10000 bootrom_base 1ffff000 diff --git a/config/chips/F1 Low-density device.chip b/config/chips/F1 low-density.chip similarity index 58% rename from config/chips/F1 Low-density device.chip rename to config/chips/F1 low-density.chip index dcb5e279e..9905ce405 100644 --- a/config/chips/F1 Low-density device.chip +++ b/config/chips/F1 low-density.chip @@ -1,8 +1,8 @@ -# Chipid file for F1 Low-density device +# Chip-ID file for F1 low-density # chip_id 412 -description F1 Low-density device -flash_type 1 +description F1 low-density +flash_type 1 flash_pagesize 400 sram_size 2800 bootrom_base 1ffff000 diff --git a/config/chips/F1xx Medium-density.chip b/config/chips/F1 medium-density.chip similarity index 59% rename from config/chips/F1xx Medium-density.chip rename to config/chips/F1 medium-density.chip index 32266b74e..00af4f18d 100644 --- a/config/chips/F1xx Medium-density.chip +++ b/config/chips/F1 medium-density.chip @@ -1,8 +1,8 @@ -# Chipid file for F1xx Medium-density +# Chip-ID file for F1 medium-density # chip_id 410 -description F1xx Medium-density -flash_type 1 +description F1 medium-density +flash_type 1 flash_pagesize 400 sram_size 5000 bootrom_base 1ffff000 diff --git a/config/chips/F1xx High-density value line.chip b/config/chips/F1 value line high-density.chip similarity index 54% rename from config/chips/F1xx High-density value line.chip rename to config/chips/F1 value line high-density.chip index f30014122..c076e284c 100644 --- a/config/chips/F1xx High-density value line.chip +++ b/config/chips/F1 value line high-density.chip @@ -1,8 +1,8 @@ -# Chipid file for F1xx High-density value line +# Chip-ID file for F1 value line high-density # chip_id 428 -description F1xx High-density value line -flash_type 1 +description F1 value line high-density +flash_type 1 flash_pagesize 800 sram_size 8000 bootrom_base 1ffff000 diff --git a/config/chips/F1xx Value Line.chip b/config/chips/F1 value line.chip similarity index 62% rename from config/chips/F1xx Value Line.chip rename to config/chips/F1 value line.chip index 929b95496..8356357b0 100644 --- a/config/chips/F1xx Value Line.chip +++ b/config/chips/F1 value line.chip @@ -1,8 +1,8 @@ -# Chipid file for F1xx Value Line +# Chip-ID file for F1 value line # chip_id 420 -description F1xx Value Line -flash_type 1 +description F1 value line +flash_type 1 flash_pagesize 400 sram_size 2000 bootrom_base 1ffff000 diff --git a/config/chips/F2xx.chip b/config/chips/F2.chip similarity index 71% rename from config/chips/F2xx.chip rename to config/chips/F2.chip index b31be46f3..8830363d2 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2.chip @@ -1,8 +1,8 @@ -# Chipid file for F2xx +# Chip-ID file for F2 # chip_id 411 -description F2xx -flash_type 3 +description F2 +flash_type 3 flash_pagesize 20000 sram_size 20000 bootrom_base 1fff0000 diff --git a/config/chips/F303 high density.chip b/config/chips/F303 high density.chip index 716c37c1e..e8b57ee24 100644 --- a/config/chips/F303 high density.chip +++ b/config/chips/F303 high density.chip @@ -1,8 +1,8 @@ -# Chipid file for F303 high density +# Chip-ID file for F303 high density # chip_id 446 description F303 high density -flash_type 1 +flash_type 1 flash_pagesize 800 sram_size 10000 bootrom_base 1fffd800 diff --git a/config/chips/F334 medium density.chip b/config/chips/F334 medium density.chip index 424f1063c..460e22a67 100644 --- a/config/chips/F334 medium density.chip +++ b/config/chips/F334 medium density.chip @@ -1,8 +1,8 @@ -# Chipid file for F334 medium density +# Chip-ID file for F334 medium density # chip_id 438 description F334 medium density -flash_type 1 +flash_type 1 flash_pagesize 800 sram_size 3000 bootrom_base 1fffd800 diff --git a/config/chips/F3xx.chip b/config/chips/F37x.chip similarity index 69% rename from config/chips/F3xx.chip rename to config/chips/F37x.chip index 4195f9007..424209a03 100644 --- a/config/chips/F3xx.chip +++ b/config/chips/F37x.chip @@ -1,8 +1,8 @@ -# Chipid file for F3xx +# Chip-ID file for F37x # chip_id 432 -description F3xx -flash_type 1 +description F37x +flash_type 1 flash_pagesize 800 sram_size a000 bootrom_base 1ffff000 diff --git a/config/chips/F3xx small.chip b/config/chips/F3xx small.chip index 7f6f5159c..91722905c 100644 --- a/config/chips/F3xx small.chip +++ b/config/chips/F3xx small.chip @@ -1,8 +1,8 @@ -# Chipid file for F3xx small +# Chip-ID file for F3xx small # chip_id 439 description F3xx small -flash_type 1 +flash_type 1 flash_pagesize 800 sram_size a000 bootrom_base 1fffd800 diff --git a/config/chips/F410.chip b/config/chips/F410.chip index 3fb1b3d2a..53f01c669 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -1,8 +1,8 @@ -# Chipid file for F410 +# Chip-ID file for F410 # chip_id 458 description F410 -flash_type 3 +flash_type 3 flash_pagesize 4000 sram_size 8000 bootrom_base 1fff0000 diff --git a/config/chips/stm32f411re.chip b/config/chips/F411xx.chip similarity index 65% rename from config/chips/stm32f411re.chip rename to config/chips/F411xx.chip index ef889c139..26390d0e6 100644 --- a/config/chips/stm32f411re.chip +++ b/config/chips/F411xx.chip @@ -1,8 +1,8 @@ -# Chipid file for stm32f411re +# Chip-ID file for F411xx # chip_id 431 -description stm32f411re -flash_type 3 +description F411xx +flash_type 3 flash_pagesize 4000 sram_size 20000 bootrom_base 1fff0000 diff --git a/config/chips/F412.chip b/config/chips/F412.chip index 138e6c273..e78b81ee1 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -1,8 +1,8 @@ -# Chipid file for F412 +# Chip-ID file for F412 # chip_id 441 description F412 -flash_type 3 +flash_type 3 flash_pagesize 4000 sram_size 40000 bootrom_base 1fff0000 diff --git a/config/chips/F413.chip b/config/chips/F413.chip index 305a808dc..4ea974f2c 100644 --- a/config/chips/F413.chip +++ b/config/chips/F413.chip @@ -1,8 +1,8 @@ -# Chipid file for F413 +# Chip-ID file for F413 # chip_id 463 description F413 -flash_type 3 +flash_type 3 flash_pagesize 4000 sram_size 50000 bootrom_base 1fff0000 diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index c279a0e1d..2073486cf 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -1,8 +1,8 @@ -# Chipid file for F42x/F43x +# Chip-ID file for F42x/F43x # chip_id 419 description F42x/F43x -flash_type 3 +flash_type 3 flash_pagesize 4000 sram_size 40000 bootrom_base 1fff0000 diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 6f372c067..7d2ded465 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -1,8 +1,8 @@ -# Chipid file for F446 +# Chip-ID file for F446 # chip_id 421 description F446 -flash_type 3 +flash_type 3 flash_pagesize 20000 sram_size 20000 bootrom_base 1fff0000 diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index 6d03bbea2..75e1ea045 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -1,8 +1,8 @@ -# Chipid file for F46x/F47x +# Chip-ID file for F46x/F47x # chip_id 434 description F46x/F47x -flash_type 3 +flash_type 3 flash_pagesize 4000 sram_size 40000 bootrom_base 1fff0000 diff --git a/config/chips/F4xx (Dynamic Efficency).chip b/config/chips/F4xx dynamic efficiency.chip similarity index 57% rename from config/chips/F4xx (Dynamic Efficency).chip rename to config/chips/F4xx dynamic efficiency.chip index fda012826..33bfa23c2 100644 --- a/config/chips/F4xx (Dynamic Efficency).chip +++ b/config/chips/F4xx dynamic efficiency.chip @@ -1,8 +1,8 @@ -# Chipid file for F4xx (Dynamic Efficency) +# Chip-ID file for F4xx dynamic efficiency # chip_id 433 -description F4xx (Dynamic Efficency) -flash_type 3 +description F4xx dynamic efficiency +flash_type 3 flash_pagesize 4000 sram_size 18000 bootrom_base 1fff0000 diff --git a/config/chips/F4xx (low power).chip b/config/chips/F4xx low power.chip similarity index 61% rename from config/chips/F4xx (low power).chip rename to config/chips/F4xx low power.chip index db9e99ffa..f52595d5d 100644 --- a/config/chips/F4xx (low power).chip +++ b/config/chips/F4xx low power.chip @@ -1,8 +1,8 @@ -# Chipid file for F4xx (low power) +# Chip-ID file for F4xx low power # chip_id 423 -description F4xx (low power) -flash_type 3 +description F4xx low power +flash_type 3 flash_pagesize 4000 sram_size 10000 bootrom_base 1fff0000 diff --git a/config/chips/F4xx.chip b/config/chips/F4xx.chip index a9dd110c5..70f298b79 100644 --- a/config/chips/F4xx.chip +++ b/config/chips/F4xx.chip @@ -1,8 +1,8 @@ -# Chipid file for F4xx +# Chip-ID file for F4xx # chip_id 413 description F4xx -flash_type 3 +flash_type 3 flash_pagesize 4000 sram_size 30000 bootrom_base 1fff0000 diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index a673b04f0..ba275bb0b 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -1,8 +1,8 @@ -# Chipid file for F72x/F73x +# Chip-ID file for F72x/F73x # chip_id 452 description F72x/F73x -flash_type 3 +flash_type 3 flash_pagesize 800 sram_size 40000 bootrom_base 100000 diff --git a/config/chips/F76xxx.chip b/config/chips/F76xxx.chip index c8f9ee108..7f8cfdaf0 100644 --- a/config/chips/F76xxx.chip +++ b/config/chips/F76xxx.chip @@ -1,8 +1,8 @@ -# Chipid file for F76xxx +# Chip-ID file for F76xxx # chip_id 451 description F76xxx -flash_type 4 +flash_type 4 flash_pagesize 800 sram_size 80000 bootrom_base 200000 diff --git a/config/chips/F7xx.chip b/config/chips/F7xx.chip index c704ce2e2..c031b5f4a 100644 --- a/config/chips/F7xx.chip +++ b/config/chips/F7xx.chip @@ -1,8 +1,8 @@ -# Chipid file for F7xx +# Chip-ID file for F7xx # chip_id 449 description F7xx -flash_type 3 +flash_type 3 flash_pagesize 800 sram_size 50000 bootrom_base 100000 diff --git a/config/chips/G030_G031_G041.chip b/config/chips/G030_G031_G041.chip index c6553904e..a1c42f58f 100644 --- a/config/chips/G030_G031_G041.chip +++ b/config/chips/G030_G031_G041.chip @@ -1,8 +1,8 @@ -# Chipid file for G030/G031/G041 +# Chip-ID file for G030/G031/G041 # chip_id 466 description G030/G031/G041 -flash_type 7 +flash_type 7 flash_pagesize 800 sram_size 2000 bootrom_base 1fff0000 diff --git a/config/chips/G070_G071_G081.chip b/config/chips/G070_G071_G081.chip index ab57bbd27..58eb16b16 100644 --- a/config/chips/G070_G071_G081.chip +++ b/config/chips/G070_G071_G081.chip @@ -1,8 +1,8 @@ -# Chipid file for G070/G071/G081 +# Chip-ID file for G070/G071/G081 # chip_id 460 description G070/G071/G081 -flash_type 7 +flash_type 7 flash_pagesize 800 sram_size 9000 bootrom_base 1fff0000 diff --git a/config/chips/G4 Category-2.chip b/config/chips/G4 cat2.chip similarity index 64% rename from config/chips/G4 Category-2.chip rename to config/chips/G4 cat2.chip index 400152cd6..309cbb83f 100644 --- a/config/chips/G4 Category-2.chip +++ b/config/chips/G4 cat2.chip @@ -1,8 +1,8 @@ -# Chipid file for G4 Category-2 +# Chip-ID file for G4 cat2 # chip_id 468 -description G4 Category-2 -flash_type 8 +description G4 cat2 +flash_type 8 flash_pagesize 800 sram_size 8000 bootrom_base 1fff0000 diff --git a/config/chips/G4 Category-3.chip b/config/chips/G4 cat3.chip similarity index 64% rename from config/chips/G4 Category-3.chip rename to config/chips/G4 cat3.chip index f8ea053f7..357522b31 100644 --- a/config/chips/G4 Category-3.chip +++ b/config/chips/G4 cat3.chip @@ -1,8 +1,8 @@ -# Chipid file for G4 Category-3 +# Chip-ID file for G4 cat3 # chip_id 469 -description G4 Category-3 -flash_type 8 +description G4 cat3 +flash_type 8 flash_pagesize 800 sram_size 18000 bootrom_base 1fff0000 diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index e63c855c8..43c8ae67b 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -1,8 +1,8 @@ -# Chipid file for H72x/H73x +# Chip-ID file for H72x/H73x # chip_id 483 description H72x/H73x -flash_type a +flash_type a flash_pagesize 20000 sram_size 20000 bootrom_base 1ff00000 diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 24e85ff66..c4d374e60 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -1,8 +1,8 @@ -# Chipid file for H74x/H75x +# Chip-ID file for H74x/H75x # chip_id 450 description H74x/H75x -flash_type a +flash_type a flash_pagesize 20000 sram_size 20000 bootrom_base 1ff00000 diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index bffd23603..b17631385 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -1,8 +1,8 @@ -# Chipid file for H7Ax/H7Bx +# Chip-ID file for H7Ax/H7Bx # chip_id 480 description H7Ax/H7Bx -flash_type a +flash_type a flash_pagesize 2000 sram_size 20000 bootrom_base 1ff00000 diff --git a/config/chips/L011.chip b/config/chips/L011.chip index 02223ddcf..6d8298848 100644 --- a/config/chips/L011.chip +++ b/config/chips/L011.chip @@ -1,8 +1,8 @@ -# Chipid file for L011 +# Chip-ID file for L011 # chip_id 457 description L011 -flash_type 5 +flash_type 5 flash_pagesize 80 sram_size 2000 bootrom_base 1ff00000 diff --git a/config/chips/L0x3.chip b/config/chips/L0x3.chip index 60d75e863..4bfc318c0 100644 --- a/config/chips/L0x3.chip +++ b/config/chips/L0x3.chip @@ -1,8 +1,8 @@ -# Chipid file for L0x3 +# Chip-ID file for L0x3 # chip_id 417 description L0x3 -flash_type 5 +flash_type 5 flash_pagesize 80 sram_size 2000 bootrom_base 1ff0000 diff --git a/config/chips/L0xx Category 2.chip b/config/chips/L0xx cat2.chip similarity index 63% rename from config/chips/L0xx Category 2.chip rename to config/chips/L0xx cat2.chip index 1cb9e1307..8b24634cf 100644 --- a/config/chips/L0xx Category 2.chip +++ b/config/chips/L0xx cat2.chip @@ -1,8 +1,8 @@ -# Chipid file for L0xx Category 2 +# Chip-ID file for L0xx cat2 # chip_id 425 -description L0xx Category 2 -flash_type 5 +description L0xx cat2 +flash_type 5 flash_pagesize 80 sram_size 2000 bootrom_base 1ff0000 diff --git a/config/chips/L0xx Category 5.chip b/config/chips/L0xx cat5.chip similarity index 63% rename from config/chips/L0xx Category 5.chip rename to config/chips/L0xx cat5.chip index 35df2fb02..b52f97363 100644 --- a/config/chips/L0xx Category 5.chip +++ b/config/chips/L0xx cat5.chip @@ -1,8 +1,8 @@ -# Chipid file for L0xx Category 5 +# Chip-ID file for L0xx cat5 # chip_id 447 -description L0xx Category 5 -flash_type 5 +description L0xx cat5 +flash_type 5 flash_pagesize 80 sram_size 5000 bootrom_base 1ff0000 diff --git a/config/chips/L152RE.chip b/config/chips/L152RE.chip index ec9d24442..c073ade93 100644 --- a/config/chips/L152RE.chip +++ b/config/chips/L152RE.chip @@ -1,8 +1,8 @@ -# Chipid file for L152RE +# Chip-ID file for L152RE # chip_id 437 description L152RE -flash_type 5 +flash_type 5 flash_pagesize 100 sram_size 14000 bootrom_base 1ff00000 diff --git a/config/chips/L1xx Cat.2.chip b/config/chips/L1xx cat2.chip similarity index 65% rename from config/chips/L1xx Cat.2.chip rename to config/chips/L1xx cat2.chip index 7a3080c60..dd89c981c 100644 --- a/config/chips/L1xx Cat.2.chip +++ b/config/chips/L1xx cat2.chip @@ -1,8 +1,8 @@ -# Chipid file for L1xx Cat.2 +# Chip-ID file for L1xx cat2 # chip_id 429 -description L1xx Cat.2 -flash_type 5 +description L1xx cat2 +flash_type 5 flash_pagesize 100 sram_size 8000 bootrom_base 1ff00000 diff --git a/config/chips/L1xx High-density.chip b/config/chips/L1xx high-density.chip similarity index 62% rename from config/chips/L1xx High-density.chip rename to config/chips/L1xx high-density.chip index 4f6c85929..8e5b0cd44 100644 --- a/config/chips/L1xx High-density.chip +++ b/config/chips/L1xx high-density.chip @@ -1,8 +1,8 @@ -# Chipid file for L1xx High-density +# Chip-ID file for L1xx high-density # chip_id 436 -description L1xx High-density -flash_type 5 +description L1xx high-density +flash_type 5 flash_pagesize 100 sram_size c000 bootrom_base 1ff00000 diff --git a/config/chips/L1xx Medium-density.chip b/config/chips/L1xx medium-density.chip similarity index 59% rename from config/chips/L1xx Medium-density.chip rename to config/chips/L1xx medium-density.chip index a1817c5d6..feb53b846 100644 --- a/config/chips/L1xx Medium-density.chip +++ b/config/chips/L1xx medium-density.chip @@ -1,8 +1,8 @@ -# Chipid file for L1xx Medium-density +# Chip-ID file for L1xx medium-density # chip_id 416 -description L1xx Medium-density -flash_type 5 +description L1xx medium-density +flash_type 5 flash_pagesize 100 sram_size 4000 bootrom_base 1ff00000 diff --git a/config/chips/L1xx Medium-Plus-density.chip b/config/chips/L1xx medium-plus-density.chip similarity index 57% rename from config/chips/L1xx Medium-Plus-density.chip rename to config/chips/L1xx medium-plus-density.chip index 30ce11e92..bdce4adc2 100644 --- a/config/chips/L1xx Medium-Plus-density.chip +++ b/config/chips/L1xx medium-plus-density.chip @@ -1,8 +1,8 @@ -# Chipid file for L1xx Medium-Plus-density +# Chip-ID file for L1xx medium-plus-density # chip_id 427 -description L1xx Medium-Plus-density -flash_type 5 +description L1xx medium-plus-density +flash_type 5 flash_pagesize 100 sram_size 8000 bootrom_base 1ff00000 diff --git a/config/chips/L41x.chip b/config/chips/L41x.chip index 008c9bfa2..a05034af4 100644 --- a/config/chips/L41x.chip +++ b/config/chips/L41x.chip @@ -1,8 +1,8 @@ -# Chipid file for L41x +# Chip-ID file for L41x # chip_id 464 description L41x -flash_type 6 +flash_type 6 flash_pagesize 800 sram_size a000 bootrom_base 1fff0000 diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index 1d956c15e..4c41ac69b 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -1,8 +1,8 @@ -# Chipid file for L43x/L44x +# Chip-ID file for L43x/L44x # chip_id 435 description L43x/L44x -flash_type 6 +flash_type 6 flash_pagesize 800 sram_size c000 bootrom_base 1fff0000 diff --git a/config/chips/L45x_46x.chip b/config/chips/L45x_L46x.chip similarity index 66% rename from config/chips/L45x_46x.chip rename to config/chips/L45x_L46x.chip index 438821fcc..da1594995 100644 --- a/config/chips/L45x_46x.chip +++ b/config/chips/L45x_L46x.chip @@ -1,8 +1,8 @@ -# Chipid file for L45x/46x +# Chip-ID file for L45x/L46x # chip_id 462 -description L45x/46x -flash_type 6 +description L45x/L46x +flash_type 6 flash_pagesize 800 sram_size 20000 bootrom_base 1fff0000 diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index b607e18cc..9bfcdb366 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -1,8 +1,8 @@ -# Chipid file for L496x/L4A6x +# Chip-ID file for L496x/L4A6x # chip_id 461 description L496x/L4A6x -flash_type 6 +flash_type 6 flash_pagesize 800 sram_size 40000 bootrom_base 1fff0000 diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index e42aba017..a9b082128 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -1,8 +1,8 @@ -# Chipid file for L4Rx +# Chip-ID file for L4Rx # chip_id 470 description L4Rx -flash_type 6 +flash_type 6 flash_pagesize 1000 sram_size a0000 bootrom_base 1fff0000 diff --git a/config/chips/L4xx.chip b/config/chips/L4xx.chip index 10ec24455..b66df6b31 100644 --- a/config/chips/L4xx.chip +++ b/config/chips/L4xx.chip @@ -1,8 +1,8 @@ -# Chipid file for L4xx +# Chip-ID file for L4xx # chip_id 415 description L4xx -flash_type 6 +flash_type 6 flash_pagesize 800 sram_size 18000 bootrom_base 1fff0000 diff --git a/config/chips/WB55.chip b/config/chips/WB55.chip index bdc0d4449..4ad4d08d0 100644 --- a/config/chips/WB55.chip +++ b/config/chips/WB55.chip @@ -1,8 +1,8 @@ -# Chipid file for WB55 +# Chip-ID file for WB55 # chip_id 495 description WB55 -flash_type 9 +flash_type 9 flash_pagesize 1000 sram_size 40000 bootrom_base 1fff0000 diff --git a/config/chips/unknown device.chip b/config/chips/unknown device.chip index 63ba47a30..ea4fe5f02 100644 --- a/config/chips/unknown device.chip +++ b/config/chips/unknown device.chip @@ -1,8 +1,8 @@ -# Chipid file for unknown device +# Chip-ID file for unknown device # chip_id 0 description unknown device -flash_type 0 +flash_type 0 flash_pagesize 0 sram_size 0 bootrom_base 0 diff --git a/config/udev/rules.d/49-stlinkv1.rules b/config/udev/rules.d/49-stlinkv1.rules index d474d6a40..9b30f1f09 100644 --- a/config/udev/rules.d/49-stlinkv1.rules +++ b/config/udev/rules.d/49-stlinkv1.rules @@ -1,4 +1,4 @@ -# stm32 discovery boards, with onboard st/linkv1 +# STM32 discovery boards, with onboard st/linkv1 # ie, STM32VL SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3744", \ diff --git a/config/udev/rules.d/49-stlinkv2-1.rules b/config/udev/rules.d/49-stlinkv2-1.rules index b89b84012..ef51f4e88 100644 --- a/config/udev/rules.d/49-stlinkv2-1.rules +++ b/config/udev/rules.d/49-stlinkv2-1.rules @@ -1,4 +1,4 @@ -# stm32 nucleo boards, with onboard st/linkv2-1 +# STM32 nucleo boards, with onboard st/linkv2-1 # ie, STM32F0, STM32F4. # STM32VL has st/linkv1, which is quite different diff --git a/config/udev/rules.d/49-stlinkv2.rules b/config/udev/rules.d/49-stlinkv2.rules index a11215c57..b4c388464 100644 --- a/config/udev/rules.d/49-stlinkv2.rules +++ b/config/udev/rules.d/49-stlinkv2.rules @@ -1,4 +1,4 @@ -# stm32 discovery boards, with onboard st/linkv2 +# STM32 discovery boards, with onboard st/linkv2 # ie, STM32L, STM32F4. # STM32VL has st/linkv1, which is quite different diff --git a/doc/tutorial.md b/doc/tutorial.md index f8f0cbb05..7e0b3901b 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -2,18 +2,18 @@ ## Available tools and options -| Option | Tool | Description | Available
      since | -| --------------------- | ---------------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | -------------------- | +| Option | Tool | Description | Available
      since | +| --------------------- | ---------------------------------- | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------------------- | | --flash=n[k, M] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
      to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
      Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
      "k" or "M" to multiply the given value by 1k (1024) or 1M (1024 x 1024) respectively.
      One can read arbitary addresses of memory out to a binary file with: `st-flash read out.bin 0x8000000 4096`.
      In this example `4096 bytes` are read and subsequently written to `out.bin`.
      Binary files (here: `in.bin`) are written into flash memory with: `st-flash write in.bin 0x8000000` | v1.4.0 | -| --format | st-flash | Specify file image format to read or write. Valid formats are `binary` and `ihex`. | v1.3.0 -| --freq=n[k, M] | st-info
      st-flash
      st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
      This option solely accepts decimal values with the unit `Hz` being left out. Valid frequencies are:
      `5k, 15k, 25k, 50k, 100k, 125k, 240k, 480k, 950k, 1200k (1.2M), 1800k (1.8M), 4000k (4M)`. | v1.6.1 | -| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
      This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | -| --reset | st-flash | Trigger a reset after flashing. The default uses the hardware reset through `NRST` pin.
      A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | -| --connect-under-reset | st-info
      st-flash
      st-util | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
      when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | -| --hot-plug | st-info
      st-flash
      st-util | Connect to the target without reset. | v1.6.2 | -| --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | -| --version | st-info
      st-flash
      st-util | Print version information. | v1.3.0 | -| --help | st-flash
      st-util | Print list of available commands. | | +| --format | st-flash | Specify file image format to read or write. Valid formats are `binary` and `ihex`. | v1.3.0 | +| --freq=n[k, M] | st-info
      st-flash
      st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
      This option solely accepts decimal values with the unit `Hz` being left out. Valid frequencies are:
      `5k, 15k, 25k, 50k, 100k, 125k, 240k, 480k, 950k, 1200k (1.2M), 1800k (1.8M), 4000k (4M)`. | v1.6.1 | +| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
      This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | +| --reset | st-flash | Trigger a reset after flashing. The default uses the hardware reset through `NRST` pin.
      A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | +| --connect-under-reset | st-info
      st-flash
      st-util | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
      when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | +| --hot-plug | st-info
      st-flash
      st-util | Connect to the target without reset. | v1.6.2 | +| --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | +| --version | st-info
      st-flash
      st-util | Print version information. | v1.3.0 | +| --help | st-flash
      st-util | Print list of available commands. | | ### Reading & Writing Option Bytes @@ -65,9 +65,9 @@ crw-rw-rw- 1 root root 189, 528 Jan 24 17:52 /dev/bus/usb/005/017 which is world writable (this is from the `MODE:="0666"` below). I have several files in my `/etc/udev/rules.d` directory. In this particular case, the `49-stlinkv2-1.rules` file contains the following: ``` -# stm32 nucleo boards, with onboard st/linkv2-1 +# STM32 nucleo boards, with onboard STLINK/V2-1 # ie, STM32F0, STM32F4. -# STM32VL has st/linkv1, which is quite different +# STM32VL has STLINK/V1, which is quite different SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ MODE:="0666", \ diff --git a/src/common.c b/src/common.c index 80190f756..49a048039 100644 --- a/src/common.c +++ b/src/common.c @@ -333,7 +333,7 @@ #define FLASH_H7_CR_SER 2 #define FLASH_H7_CR_BER 3 #define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7AX ? 5 : 7) +#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7Ax ? 5 : 7) #define FLASH_H7_CR_SNB 8 #define FLASH_H7_CR_SNB_MASK 0x700 @@ -447,9 +447,9 @@ static uint32_t get_stm32l0_flash_base(stlink_t *sl) { return (STM32L0_FLASH_REGS_ADDR); case STLINK_CHIPID_STM32_L1_CAT2: - case STLINK_CHIPID_STM32_L1_MEDIUM: - case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS: - case STLINK_CHIPID_STM32_L1_HIGH: + case STLINK_CHIPID_STM32_L1_MD: + case STLINK_CHIPID_STM32_L1_MD_PLUS: + case STLINK_CHIPID_STM32_L1_MD_PLUS_HD: return (STM32L1_FLASH_REGS_ADDR); default: @@ -1618,14 +1618,14 @@ int stlink_load_device_params(stlink_t *sl) { flash_size = flash_size & 0xffff; - if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || - sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && + if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MD || + sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || + sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS) && (flash_size == 0)) { sl->flash_size = 128 * 1024; } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_HIGH) { + } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_MD_PLUS_HD) { // 0 is 384k and 1 is 256k if (flash_size == 0) { sl->flash_size = 384 * 1024; @@ -1647,7 +1647,7 @@ int stlink_load_device_params(stlink_t *sl) { // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && + if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { sl->sram_size = 0x1000; } @@ -2715,8 +2715,8 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { flashaddr -= STM32_FLASH_BASE; if (sl->chip_id == STLINK_CHIPID_STM32_L4 || - sl->chip_id == STLINK_CHIPID_STM32_L496X || - sl->chip_id == STLINK_CHIPID_STM32_L4RX) { + sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x || + sl->chip_id == STLINK_CHIPID_STM32_L4Rx) { // this chip use dual banked flash if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { uint32_t banksize = (uint32_t)sl->flash_size / 2; @@ -2739,10 +2739,10 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || - (sl->chip_id == STLINK_CHIPID_STM32_F411XX) || + (sl->chip_id == STLINK_CHIPID_STM32_F411xx) || (sl->chip_id == STLINK_CHIPID_STM32_F446) || (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || - (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || + (sl->chip_id == STLINK_CHIPID_STM32_F72xxx) || (sl->chip_id == STLINK_CHIPID_STM32_F412)) { uint32_t sector = calculate_F4_sectornum(flashaddr); @@ -2758,7 +2758,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { sl->flash_pgsz = 0x20000; } } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { + sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { uint32_t sector = calculate_F7_sectornum(flashaddr); if (sector < 4) { @@ -2794,10 +2794,10 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // select the page to erase if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43X) || - (sl->chip_id == STLINK_CHIPID_STM32_L46X) || - (sl->chip_id == STLINK_CHIPID_STM32_L496X) || - (sl->chip_id == STLINK_CHIPID_STM32_L4RX)) { + (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || + (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || + (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) || + (sl->chip_id == STLINK_CHIPID_STM32_L4Rx)) { // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); @@ -2806,7 +2806,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { write_flash_cr_bker_pnb(sl, page); } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { + sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { // calculate the actual page from the address uint32_t sector = calculate_F7_sectornum(flashaddr); @@ -2990,7 +2990,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { unlock_flash_if(sl); if (sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_id != STLINK_CHIPID_STM32_H7AX) { + sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -3265,7 +3265,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { set_flash_cr_pg(sl, BANK_2); } - if (sl->chip_id != STLINK_CHIPID_STM32_H7AX) { + if (sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -4383,7 +4383,7 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { case STLINK_CHIPID_STM32_F4: case STLINK_CHIPID_STM32_F446: return stlink_read_option_bytes_f4(sl, option_byte); - case STLINK_CHIPID_STM32_F7XXXX: + case STLINK_CHIPID_STM32_F76xxx: return stlink_read_option_bytes_f7(sl, option_byte); case STLINK_CHIPID_STM32_G0_CAT1: case STLINK_CHIPID_STM32_G0_CAT2: @@ -4632,12 +4632,12 @@ stlink_write_option_control_register_f0(stlink_t *sl, case 0x432: /* STM32F37x */ case 0x438: /* STM32F303x6/8 and STM32F328 */ case 0x446: /* STM32F303xD/E and STM32F398xE */ - case 0x439: /* stm32f302x6/8 */ - case 0x440: /* stm32f05x */ - case 0x444: /* stm32f03x */ - case 0x445: /* stm32f04x */ - case 0x448: /* stm32f07x */ - case 0x442: /* stm32f09x */ + case 0x439: /* STM32F302x6/8 */ + case 0x440: /* STM32F05x */ + case 0x444: /* STM32F03x */ + case 0x445: /* STM32F04x */ + case 0x448: /* STM32F07x */ + case 0x442: /* STM32F09x */ option_offset = 6; user_data_offset = 16; rdp = 0x55AA; diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 87c6c77e1..27ed81da4 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -535,14 +535,14 @@ char* make_memory_map(stlink_t *sl) { if (sl->chip_id == STLINK_CHIPID_STM32_F4 || sl->chip_id == STLINK_CHIPID_STM32_F446 || - sl->chip_id == STLINK_CHIPID_STM32_F411XX) { + sl->chip_id == STLINK_CHIPID_STM32_F411xx) { strcpy(map, memory_map_template_F4); } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) { strcpy(map, memory_map_template_F4_DE); } else if (sl->core_id == STM32F7_CORE_ID) { snprintf(map, sz, memory_map_template_F7, (unsigned int)sl->sram_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_H74XXX) { + } else if (sl->chip_id == STLINK_CHIPID_STM32_H74xxx) { snprintf(map, sz, memory_map_template_H7, (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); @@ -556,12 +556,12 @@ char* make_memory_map(stlink_t *sl) { (unsigned int)sl->sys_base, (unsigned int)sl->sys_size); } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43X) || - (sl->chip_id == STLINK_CHIPID_STM32_L46X)) { + (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || + (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x)) { snprintf(map, sz, memory_map_template_L4, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_L496X) { + } else if (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) { snprintf(map, sz, memory_map_template_L496, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 8ef6e17c2..a9f19a155 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -11,7 +11,7 @@ static struct stlink_chipid_params devices[] = { { // RM0410 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F7XXXX, + .chip_id = STLINK_CHIPID_STM32_F76xxx, .description = "F76xxx", .flash_type = STLINK_FLASH_TYPE_F7, .flash_size_reg = 0x1ff0f442, // section 45.2 @@ -42,7 +42,7 @@ static struct stlink_chipid_params devices[] = { }, { // RM0431 and DS document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F72XXX, + .chip_id = STLINK_CHIPID_STM32_F72xxx, .description = "F72x/F73x", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1ff07a22, // section 35.2 @@ -56,7 +56,7 @@ static struct stlink_chipid_params devices[] = { }, { // table 2, PM0063 - .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, + .chip_id = STLINK_CHIPID_STM32_F1_MD, .description = "F1xx Medium-density", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, @@ -84,7 +84,7 @@ static struct stlink_chipid_params devices[] = { }, { // PM0063 - .chip_id = STLINK_CHIPID_STM32_F1_LOW, + .chip_id = STLINK_CHIPID_STM32_F1_LD, .description = "F1 Low-density device", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, @@ -143,7 +143,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_F411XX, + .chip_id = STLINK_CHIPID_STM32_F411xx, .description = "STM32F411xC/E", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, @@ -167,7 +167,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_F1_HIGH, + .chip_id = STLINK_CHIPID_STM32_F1_HD, .description = "F1xx High-density", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, @@ -182,7 +182,7 @@ static struct stlink_chipid_params devices[] = { { // This ignores the EEPROM! (and uses the page erase size, // not the sector write protection...) - .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM, + .chip_id = STLINK_CHIPID_STM32_L1_MD, .description = "L1xx Medium-density", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, @@ -204,7 +204,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, + .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS, .description = "L1xx Medium-Plus-density", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, @@ -215,7 +215,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_L1_HIGH, + .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS_HD, .description = "L1xx High-density", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, @@ -253,7 +253,7 @@ static struct stlink_chipid_params devices[] = { }, { // Low and Medium density VL have same chipid. RM0041 25.6.1 - .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, + .chip_id = STLINK_CHIPID_STM32_F1_VL_MD_LD, .description = "F1xx Value Line", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, @@ -322,7 +322,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, + .chip_id = STLINK_CHIPID_STM32_F1_VL_HD, .description = "F1xx High-density value line", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, @@ -335,7 +335,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_F1_XL, + .chip_id = STLINK_CHIPID_STM32_F1_XLD, .description = "F1xx XL-density", .flash_type = STLINK_FLASH_TYPE_F1_XL, .flash_size_reg = 0x1ffff7e0, @@ -407,7 +407,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - .chip_id = STLINK_CHIPID_STM32_F09X, + .chip_id = STLINK_CHIPID_STM32_F09x, .description = "F09X", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) @@ -437,7 +437,7 @@ static struct stlink_chipid_params devices[] = { { // Use this as an example for mapping future chips: // RM0091 document was used to find these paramaters - .chip_id = STLINK_CHIPID_STM32_F0_SMALL, + .chip_id = STLINK_CHIPID_STM32_F0xx_SMALL, .description = "F03x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) @@ -451,7 +451,7 @@ static struct stlink_chipid_params devices[] = { }, { // STM32F30x - .chip_id = STLINK_CHIPID_STM32_F3_SMALL, + .chip_id = STLINK_CHIPID_STM32_F3xx_SMALL, .description = "F3xx small", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, @@ -523,7 +523,7 @@ static struct stlink_chipid_params devices[] = { { // This is STK32F303RET6 device from STM32 F3 Nucelo board. // Support based on DM00043574.pdf (RM0316) document rev 5. - .chip_id = STLINK_CHIPID_STM32_F303_HIGH, + .chip_id = STLINK_CHIPID_STM32_F303_HD, .description = "F303 high density", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register @@ -560,7 +560,7 @@ static struct stlink_chipid_params devices[] = { { // STM32L4RX // From DM00310109.pdf - .chip_id = STLINK_CHIPID_STM32_L4RX, + .chip_id = STLINK_CHIPID_STM32_L4Rx, .description = "L4Rx", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = @@ -573,9 +573,9 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L41X + // STLINK_CHIPID_STM32_L41x_L42x // From RM0394 Rev 4 and DS12469 Rev 5 - .chip_id = STLINK_CHIPID_STM32_L41X, + .chip_id = STLINK_CHIPID_STM32_L41x_L42x, .description = "L41x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, @@ -591,9 +591,9 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L43X + // STLINK_CHIPID_STM32_L43x_L44x // From RM0392. - .chip_id = STLINK_CHIPID_STM32_L43X, + .chip_id = STLINK_CHIPID_STM32_L43x_L44x, .description = "L43x/L44x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = @@ -613,9 +613,9 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L496X + // STLINK_CHIPID_STM32_L496x_L4A6x // Support based on en.DM00083560.pdf (RM0351) document rev 5. - .chip_id = STLINK_CHIPID_STM32_L496X, + .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, .description = "L496x/L4A6x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = @@ -632,9 +632,9 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L46X + // STLINK_CHIPID_STM32_L45x_L46x // From RM0394 (updated version of RM0392?). - .chip_id = STLINK_CHIPID_STM32_L46X, + .chip_id = STLINK_CHIPID_STM32_L45x_L46x, .description = "L45x/46x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = @@ -764,7 +764,7 @@ static struct stlink_chipid_params devices[] = { }, { // STM32H742/743/753 (from RM0433) - .chip_id = STLINK_CHIPID_STM32_H74XXX, + .chip_id = STLINK_CHIPID_STM32_H74xxx, .description = "H74x/H75x", .flash_type = STLINK_FLASH_TYPE_H7, .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) @@ -780,7 +780,7 @@ static struct stlink_chipid_params devices[] = { }, { // STM32H7A3/7B3 (from RM0455) - .chip_id = STLINK_CHIPID_STM32_H7AX, + .chip_id = STLINK_CHIPID_STM32_H7Ax, .description = "H7Ax/H7Bx", .flash_type = STLINK_FLASH_TYPE_H7, .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) @@ -796,7 +796,7 @@ static struct stlink_chipid_params devices[] = { }, { // STM32H72x/H73x (from RM0468) - .chip_id = STLINK_CHIPID_STM32_H72X, + .chip_id = STLINK_CHIPID_STM32_H72x, .description = "H72x/H73x", .flash_type = STLINK_FLASH_TYPE_H7, .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) @@ -840,18 +840,18 @@ static struct stlink_chipid_params *devicelist; void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { - fprintf (fp, "# Chipid file for %s\n", dev->description); - fprintf (fp, "#\n"); - fprintf (fp, "chip_id %x\n", dev->chip_id); - fprintf (fp, "description %s\n", dev->description); - fprintf (fp, "flash_type %x\n", dev->flash_type); - fprintf (fp, "flash_pagesize %x\n", dev->flash_pagesize); - fprintf (fp, "sram_size %x\n", dev->sram_size); - fprintf (fp, "bootrom_base %x\n", dev->bootrom_base); - fprintf (fp, "bootrom_size %x\n", dev->bootrom_size); - fprintf (fp, "option_base %x\n", dev->option_base); - fprintf (fp, "option_size %x\n", dev->option_size); - fprintf (fp, "flags %x\n\n", dev->flags); + fprintf(fp, "# Chip-ID file for %s\n", dev->description); + fprintf(fp, "#\n"); + fprintf(fp, "chip_id %x\n", dev->chip_id); + fprintf(fp, "description %s\n", dev->description); + fprintf(fp, "flash_type %x\n", dev->flash_type); + fprintf(fp, "flash_pagesize %x\n", dev->flash_pagesize); + fprintf(fp, "sram_size %x\n", dev->sram_size); + fprintf(fp, "bootrom_base %x\n", dev->bootrom_base); + fprintf(fp, "bootrom_size %x\n", dev->bootrom_size); + fprintf(fp, "option_base %x\n", dev->option_base); + fprintf(fp, "option_size %x\n", dev->option_size); + fprintf(fp, "flags %x\n\n", dev->flags); } @@ -864,21 +864,21 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { for (params = devicelist ; params != NULL ; params = params -> next) if (params->chip_id == chipid) break; - p2 = stlink_chipid_get_params_old (chipid); + p2 = stlink_chipid_get_params_old(chipid); - if (memcmp (p2, params, sizeof (struct stlink_chipid_params) - sizeof (struct stlink_chipid_params *)) != 0) { + if (memcmp(p2, params, sizeof (struct stlink_chipid_params) - sizeof (struct stlink_chipid_params *)) != 0) { //fprintf (stderr, "Error, chipid params not identical\n"); //return NULL; - fprintf (stderr, "---------- old ------------\n"); - dump_a_chip (stderr, p2); - fprintf (stderr, "---------- new ------------\n"); - dump_a_chip (stderr, params); + fprintf(stderr, "---------- old ------------\n"); + dump_a_chip(stderr, p2); + fprintf(stderr, "---------- new ------------\n"); + dump_a_chip(stderr, params); } return(params); } -void process_chipfile (char *fname) +void process_chipfile(char *fname) { FILE *fp; char *p, buf[1025]; @@ -887,44 +887,44 @@ void process_chipfile (char *fname) int nc; //fprintf (stderr, "processing chipfile %s.\n", fname); - fp = fopen (fname, "r"); + fp = fopen(fname, "r"); if (!fp) { - perror (fname); + perror(fname); return; } - ts = calloc (sizeof (struct stlink_chipid_params), 1); - while (fgets (buf, 1024, fp) != NULL) { + ts = calloc(sizeof (struct stlink_chipid_params), 1); + while (fgets(buf, 1024, fp) != NULL) { for (p=buf;isspace (*p);p++); if (!*p) continue; // we hit end-of-line wiht only whitespace if (*p == '#') continue; // ignore comments. - sscanf (p, "%s %s", word, value); - if (strcmp (word, "chip_id") == 0) { - sscanf (value, "%x", &ts->chip_id); + sscanf(p, "%s %s", word, value); + if (strcmp(word, "chip_id") == 0) { + sscanf(value, "%x", &ts->chip_id); } else if (strcmp (word, "description") == 0) { //ts->description = strdup (value); buf[strlen(p)-1] = 0; // chomp newline - sscanf (p, "%*s %n", &nc); - ts->description = strdup (p+nc); + sscanf(p, "%*s %n", &nc); + ts->description = strdup(p+nc); } else if (strcmp (word, "flash_type") == 0) { - sscanf (value, "%x", &ts->flash_type); + sscanf(value, "%x", &ts->flash_type); } else if (strcmp (word, "flash_size_reg") == 0) { - sscanf (value, "%x", &ts->flash_size_reg); + sscanf(value, "%x", &ts->flash_size_reg); } else if (strcmp (word, "flash_pagesize") == 0) { - sscanf (value, "%x", &ts->flash_pagesize); + sscanf(value, "%x", &ts->flash_pagesize); } else if (strcmp (word, "sram_size") == 0) { - sscanf (value, "%x", &ts->sram_size); + sscanf(value, "%x", &ts->sram_size); } else if (strcmp (word, "bootrom_base") == 0) { - sscanf (value, "%x", &ts->bootrom_base); + sscanf(value, "%x", &ts->bootrom_base); } else if (strcmp (word, "bootrom_size") == 0) { - sscanf (value, "%x", &ts->bootrom_size); + sscanf(value, "%x", &ts->bootrom_size); } else if (strcmp (word, "option_base") == 0) { - sscanf (value, "%x", &ts->option_base); + sscanf(value, "%x", &ts->option_base); } else if (strcmp (word, "option_size") == 0) { - sscanf (value, "%x", &ts->option_size); + sscanf(value, "%x", &ts->option_size); } else if (strcmp (word, "flags") == 0) { - sscanf (value, "%x", &ts->flags); + sscanf(value, "%x", &ts->flags); } else { fprintf (stderr, "Unknown keyword in %s: %s\n", fname, word); @@ -934,7 +934,6 @@ void process_chipfile (char *fname) devicelist = ts; } - void dump_chips (void) { struct stlink_chipid_params *ts; @@ -944,30 +943,28 @@ void dump_chips (void) for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { ts = &devices[n]; - strcpy (buf, ts->description); - while ((p = strchr (buf, '/'))) // change slashes to underscore. + strcpy(buf, ts->description); + while ((p = strchr(buf, '/'))) // change slashes to underscore. *p = '_'; - strcat (buf, ".chip"); - fp = fopen (buf, "w"); - fprintf (fp, "# Chipid file for %s\n", ts->description); - fprintf (fp, "#\n"); - fprintf (fp, "chip_id %x\n", ts->chip_id); - fprintf (fp, "description %s\n", ts->description); - fprintf (fp, "flash_type %x\n", ts->flash_type); - fprintf (fp, "flash_pagesize %x\n", ts->flash_pagesize); - fprintf (fp, "sram_size %x\n", ts->sram_size); - fprintf (fp, "bootrom_base %x\n", ts->bootrom_base); - fprintf (fp, "bootrom_size %x\n", ts->bootrom_size); - fprintf (fp, "option_base %x\n", ts->option_base); - fprintf (fp, "option_size %x\n", ts->option_size); - fprintf (fp, "flags %x\n\n", ts->flags); - fclose (fp); + strcat(buf, ".chip"); + fp = fopen(buf, "w"); + fprintf(fp, "# Chip-ID file for %s\n", ts->description); + fprintf(fp, "#\n"); + fprintf(fp, "chip_id %x\n", ts->chip_id); + fprintf(fp, "description %s\n", ts->description); + fprintf(fp, "flash_type %x\n", ts->flash_type); + fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); + fprintf(fp, "sram_size %x\n", ts->sram_size); + fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); + fprintf(fp, "bootrom_size %x\n", ts->bootrom_size); + fprintf(fp, "option_base %x\n", ts->option_base); + fprintf(fp, "option_size %x\n", ts->option_size); + fprintf(fp, "flags %x\n\n", ts->flags); + fclose(fp); } } - - -void init_chipids (char *dir_to_scan) +void init_chipids(char *dir_to_scan) { DIR *d; size_t nl; // namelen @@ -979,11 +976,11 @@ void init_chipids (char *dir_to_scan) d = opendir(dir_to_scan); if (d) { while ((dir = readdir(d)) != NULL) { - nl = strlen (dir->d_name); - if (strcmp (dir->d_name + nl - 5, ".chip") == 0) { + nl = strlen(dir->d_name); + if (strcmp(dir->d_name + nl - 5, ".chip") == 0) { char buf[1024]; - sprintf (buf, "%s/%s", dir_to_scan, dir->d_name); - process_chipfile (buf); + sprintf(buf, "%s/%s", dir_to_scan, dir->d_name); + process_chipfile(buf); } } closedir(d); diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f80c06732..f1342dd61 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -13,68 +13,66 @@ extern "C" { enum stlink_stm32_chipids { STLINK_CHIPID_UNKNOWN = 0x000, - STLINK_CHIPID_STM32_F1_MEDIUM = 0x410, + STLINK_CHIPID_STM32_F1_MD = 0x410, /* medium density */ STLINK_CHIPID_STM32_F2 = 0x411, - STLINK_CHIPID_STM32_F1_LOW = 0x412, + STLINK_CHIPID_STM32_F1_LD = 0x412, /* low density */ STLINK_CHIPID_STM32_F4 = 0x413, - STLINK_CHIPID_STM32_F1_HIGH = 0x414, + STLINK_CHIPID_STM32_F1_HD = 0x414, /* high density */ STLINK_CHIPID_STM32_L4 = 0x415, - STLINK_CHIPID_STM32_L1_MEDIUM = 0x416, + STLINK_CHIPID_STM32_L1_MD = 0x416, /* medium density */ STLINK_CHIPID_STM32_L0 = 0x417, - STLINK_CHIPID_STM32_F1_CONN = 0x418, - STLINK_CHIPID_STM32_F4_HD = 0x419, - STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW = 0x420, + STLINK_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */ + STLINK_CHIPID_STM32_F4_HD = 0x419, /* high density */ + STLINK_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */ STLINK_CHIPID_STM32_F446 = 0x421, STLINK_CHIPID_STM32_F3 = 0x422, STLINK_CHIPID_STM32_F4_LP = 0x423, STLINK_CHIPID_STM32_L0_CAT2 = 0x425, - STLINK_CHIPID_STM32_L1_MEDIUM_PLUS = 0x427, /* assigned to some L1 "Medium-plus" chips */ - STLINK_CHIPID_STM32_F1_VL_HIGH = 0x428, + STLINK_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */ + STLINK_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */ STLINK_CHIPID_STM32_L1_CAT2 = 0x429, - STLINK_CHIPID_STM32_F1_XL = 0x430, - STLINK_CHIPID_STM32_F411XX = 0x431, + STLINK_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */ + STLINK_CHIPID_STM32_F411xx = 0x431, STLINK_CHIPID_STM32_F37x = 0x432, STLINK_CHIPID_STM32_F4_DE = 0x433, STLINK_CHIPID_STM32_F4_DSI = 0x434, - STLINK_CHIPID_STM32_L43X = 0x435, /* covers STM32L43xxx and STM32L44xxx devices */ - STLINK_CHIPID_STM32_L496X = 0x461, /* covers STM32L496xx and STM32L4A6xx devices */ - STLINK_CHIPID_STM32_L46X = 0x462, /* covers STM32L45xxx and STM32L46xxx devices */ - STLINK_CHIPID_STM32_L41X = 0x464, /* covers STM32L41xxx and STM32L42xxx devices */ - STLINK_CHIPID_STM32_L1_HIGH = 0x436, /* assigned to some L1 "Medium-Plus" and "High" chips */ + STLINK_CHIPID_STM32_L43x_L44x = 0x435, + STLINK_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ STLINK_CHIPID_STM32_L152_RE = 0x437, STLINK_CHIPID_STM32_F334 = 0x438, - STLINK_CHIPID_STM32_F3_SMALL = 0x439, + STLINK_CHIPID_STM32_F3xx_SMALL = 0x439, STLINK_CHIPID_STM32_F0 = 0x440, STLINK_CHIPID_STM32_F412 = 0x441, - STLINK_CHIPID_STM32_F09X = 0x442, - STLINK_CHIPID_STM32_F0_SMALL = 0x444, + STLINK_CHIPID_STM32_F09x = 0x442, + STLINK_CHIPID_STM32_F0xx_SMALL = 0x444, STLINK_CHIPID_STM32_F04 = 0x445, - STLINK_CHIPID_STM32_F303_HIGH = 0x446, + STLINK_CHIPID_STM32_F303_HD = 0x446, /* high density */ STLINK_CHIPID_STM32_L0_CAT5 = 0x447, STLINK_CHIPID_STM32_F0_CAN = 0x448, STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the NucleoF746ZG board */ - STLINK_CHIPID_STM32_H74XXX = 0x450, /* Found on page 3189 in the RM0433*/ - STLINK_CHIPID_STM32_F7XXXX = 0x451, - STLINK_CHIPID_STM32_F72XXX = 0x452, /* ID found on the NucleoF722ZE board */ - STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G050/G051/G061 found on RM0444/RM0454 */ + STLINK_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */ + STLINK_CHIPID_STM32_F76xxx = 0x451, + STLINK_CHIPID_STM32_F72xxx = 0x452, /* ID found on the NucleoF722ZE board */ + STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G050/G051/G061 found in RM0444/RM0454 */ STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ + STLINK_CHIPID_STM32_L496x_L4A6x = 0x461, + STLINK_CHIPID_STM32_L45x_L46x = 0x462, STLINK_CHIPID_STM32_F413 = 0x463, + STLINK_CHIPID_STM32_L41x_L42x = 0x464, STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ - STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B0/G0B1/G0C1 found on RM0444/RM0454 */ - STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ + STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B0/G0B1/G0C1 found in RM0444/RM0454 */ + STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, s46.6.1 "MCU device ID code" */ STLINK_CHIPID_STM32_G4_CAT3 = 0x469, - STLINK_CHIPID_STM32_L4RX = 0x470, /* ID found on the STM32L4R9I-DISCO board */ - STLINK_CHIPID_STM32_H7AX = 0x480, /* RM0455, p. 2863 */ - STLINK_CHIPID_STM32_H72X = 0x483, /* RM0468, p. 3199 */ + STLINK_CHIPID_STM32_L4Rx = 0x470, /* ID found on the STM32L4R9I-DISCO board */ + STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ + STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ STLINK_CHIPID_STM32_WB55 = 0x495 }; - -#define CHIP_F_HAS_DUAL_BANK (1 << 0) -#define CHIP_F_HAS_SWO_TRACING (1 << 1) - +#define CHIP_F_HAS_DUAL_BANK (1 << 0) +#define CHIP_F_HAS_SWO_TRACING (1 << 1) /** Chipid parameters */ struct stlink_chipid_params { @@ -94,7 +92,7 @@ struct stlink_chipid_params { struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); - void init_chipids (char *dir_to_scan); + void init_chipids(char *dir_to_scan); #ifdef __cplusplus } diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index d492716db..9a1e86681 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -227,10 +227,10 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || + if (sl->chip_id == STLINK_CHIPID_STM32_L1_MD || sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS || - sl->chip_id == STLINK_CHIPID_STM32_L1_HIGH || + sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS || + sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS_HD || sl->chip_id == STLINK_CHIPID_STM32_L152_RE || sl->chip_id == STLINK_CHIPID_STM32_L011 || sl->chip_id == STLINK_CHIPID_STM32_L0 || @@ -239,16 +239,16 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code = loader_code_stm32lx; loader_size = sizeof(loader_code_stm32lx); } else if (sl->core_id == STM32VL_CORE_ID || - sl->chip_id == STLINK_CHIPID_STM32_F1_MEDIUM || - sl->chip_id == STLINK_CHIPID_STM32_F1_HIGH || - sl->chip_id == STLINK_CHIPID_STM32_F1_LOW || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_HIGH || - sl->chip_id == STLINK_CHIPID_STM32_F1_XL || + sl->chip_id == STLINK_CHIPID_STM32_F1_MD || + sl->chip_id == STLINK_CHIPID_STM32_F1_HD || + sl->chip_id == STLINK_CHIPID_STM32_F1_LD || + sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || + sl->chip_id == STLINK_CHIPID_STM32_F1_VL_HD || + sl->chip_id == STLINK_CHIPID_STM32_F1_XLD || sl->chip_id == STLINK_CHIPID_STM32_F1_CONN || sl->chip_id == STLINK_CHIPID_STM32_F3 || - sl->chip_id == STLINK_CHIPID_STM32_F3_SMALL || - sl->chip_id == STLINK_CHIPID_STM32_F303_HIGH || + sl->chip_id == STLINK_CHIPID_STM32_F3xx_SMALL || + sl->chip_id == STLINK_CHIPID_STM32_F303_HD || sl->chip_id == STLINK_CHIPID_STM32_F37x || sl->chip_id == STLINK_CHIPID_STM32_F334) { loader_code = loader_code_stm32vl; @@ -260,7 +260,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_F4_HD || sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || sl->chip_id == STLINK_CHIPID_STM32_F410 || - sl->chip_id == STLINK_CHIPID_STM32_F411XX || + sl->chip_id == STLINK_CHIPID_STM32_F411xx || sl->chip_id == STLINK_CHIPID_STM32_F412 || sl->chip_id == STLINK_CHIPID_STM32_F413 || sl->chip_id == STLINK_CHIPID_STM32_F446) { @@ -273,8 +273,8 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* if (retval == -1) { return(retval); } } else if (sl->core_id == STM32F7_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F7XXXX || - sl->chip_id == STLINK_CHIPID_STM32_F72XXX) { + sl->chip_id == STLINK_CHIPID_STM32_F76xxx || + sl->chip_id == STLINK_CHIPID_STM32_F72xxx) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, @@ -285,16 +285,16 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || sl->chip_id == STLINK_CHIPID_STM32_F04 || sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || - sl->chip_id == STLINK_CHIPID_STM32_F0_SMALL || - sl->chip_id == STLINK_CHIPID_STM32_F09X) { + sl->chip_id == STLINK_CHIPID_STM32_F0xx_SMALL || + sl->chip_id == STLINK_CHIPID_STM32_F09x) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L41X) || - (sl->chip_id == STLINK_CHIPID_STM32_L43X) || - (sl->chip_id == STLINK_CHIPID_STM32_L46X) || - (sl->chip_id == STLINK_CHIPID_STM32_L4RX) || - (sl->chip_id == STLINK_CHIPID_STM32_L496X)) { + (sl->chip_id == STLINK_CHIPID_STM32_L41x_L42x) || + (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || + (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || + (sl->chip_id == STLINK_CHIPID_STM32_L4Rx) || + (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x)) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { From 9d93531ac1a014eddd5efe3b1ca7bde8ec3bcc73 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Tue, 18 May 2021 19:46:45 +0530 Subject: [PATCH 1198/1435] cmake: Install shared libraries in proper directories. This fixes the installation of DLL file in mingw. --- CMakeLists.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 4bd76ebfb..43c5dbac1 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -194,8 +194,11 @@ else () target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB}) endif () -install(TARGETS ${STLINK_LIB_SHARED} DESTINATION ${STLINK_LIBRARY_PATH}) - +install(TARGETS ${STLINK_LIB_SHARED} + ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH} + LIBRARY DESTINATION ${STLINK_LIBRARY_PATH} + RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} + ) ### # Static library From 553713d911e07fe6e02e907e2c9ab2b012f28d32 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Tue, 18 May 2021 19:47:33 +0530 Subject: [PATCH 1199/1435] win32: Fix socket fd type. --- src/win32/win32_socket.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/win32/win32_socket.c b/src/win32/win32_socket.c index 9138a7679..bfdcac5ce 100644 --- a/src/win32/win32_socket.c +++ b/src/win32/win32_socket.c @@ -70,7 +70,7 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { if (rc > 0) { for ( i = 0; i < nfds; ++i) { - int fd = fds[i].fd; + SOCKET fd = fds[i].fd; if (fds[i].events & (POLLIN | POLLPRI) && FD_ISSET(fd, &ifds)) { fds[i].revents |= POLLIN; From a9adf9cb29d90af9d53c8adef673bcdc7d2490ae Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 18 May 2021 22:53:33 +0200 Subject: [PATCH 1200/1435] General Project Update - Updated CHANGELOG.md - Updated CI configs for macOS 11 & 10.14 --- .travis.yml | 34 +++++++++++++++++++++++++++++----- CHANGELOG.md | 10 ++++++---- doc/version_support.md | 4 ++-- 3 files changed, 37 insertions(+), 11 deletions(-) diff --git a/.travis.yml b/.travis.yml index c54c0c6f4..469094892 100644 --- a/.travis.yml +++ b/.travis.yml @@ -30,7 +30,7 @@ jobs: - os: osx env: BADGE=osx - osx_image: xcode10.3 + osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile name: macOS 10.14.4 gcc compiler: gcc addons: @@ -42,7 +42,7 @@ jobs: - os: osx env: BADGE=osx - osx_image: xcode10.3 + osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile name: macOS 10.14.4 gcc 32-bit compiler: gcc addons: @@ -56,7 +56,7 @@ jobs: - os: osx env: BADGE=osx - osx_image: xcode10.3 + osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile name: macOS 10.14.4 clang compiler: clang addons: @@ -68,9 +68,9 @@ jobs: - os: osx env: BADGE=osx - osx_image: xcode10.3 + osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile name: macOS 10.14.4 clang 32-bit - compiler: gcc + compiler: clang addons: homebrew: packages: @@ -80,6 +80,30 @@ jobs: before_install: - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; + - os: osx + env: BADGE=osx + osx_image: xcode12.5 + name: macOS 11.3 gcc + compiler: gcc + addons: + homebrew: + packages: + - gcc + - libusb + - gtk+3 + + - os: osx + env: BADGE=osx + osx_image: xcode12.5 + name: macOS 11.3 clang + compiler: clang + addons: + homebrew: + packages: + - clang + - libusb + - gtk+3 + script: - git fetch --tags - printenv diff --git a/CHANGELOG.md b/CHANGELOG.md index b43d58da7..5314ea912 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -16,8 +16,10 @@ Features: Updates & changes: - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) +- Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation ([#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) Fixes: +- cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) # v1.7.0 @@ -59,10 +61,10 @@ Updates & changes: Fixes: -- Improvements and fixes of the flash loaders, unification of the reset function ([#244](https://github.com/stlink-org/stlink/pull/244), [#382](https://github.com/stlink-org/stlink/pull/382), [#705](https://github.com/stlink-org/stlink/pull/705), [#980](https://github.com/stlink-org/stlink/pull/980), [#995](https://github.com/stlink-org/stlink/pull/995), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1115](https://github.com/stlink-org/stlink/pull/1115), [#1117](https://github.com/stlink-org/stlink/pull/1117), [#1122](https://github.com/stlink-org/stlink/pull/1122), [#1124](https://github.com/stlink-org/stlink/pull/1124)) -- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#807](https://github.com/stlink-org/stlink/pull/807), [#817](https://github.com/stlink-org/stlink/pull/817), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) +- Improvements and fixes of the flash loaders, unification of the reset function ([#244](https://github.com/stlink-org/stlink/pull/244), [#382](https://github.com/stlink-org/stlink/pull/382), [#705](https://github.com/stlink-org/stlink/pull/705), [#724](https://github.com/stlink-org/stlink/pull/724), [#980](https://github.com/stlink-org/stlink/pull/980), [#995](https://github.com/stlink-org/stlink/pull/995), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1115](https://github.com/stlink-org/stlink/pull/1115), [#1117](https://github.com/stlink-org/stlink/pull/1117), [#1122](https://github.com/stlink-org/stlink/pull/1122), [#1124](https://github.com/stlink-org/stlink/pull/1124)) +- Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#724](https://github.com/stlink-org/stlink/pull/724), [#807](https://github.com/stlink-org/stlink/pull/807), [#817](https://github.com/stlink-org/stlink/pull/817), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) - Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106), [#1121](https://github.com/stlink-org/stlink/pull/1121)) -- Use vl flashloader for all STM32F1 series ([#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) +- Use vl flashloader for all STM32F1 series ([#724](https://github.com/stlink-org/stlink/pull/724), [#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) - cmake compile failure with external `CMAKE_MODULE_PATH` set ([#962](https://github.com/stlink-org/stlink/pull/962)) - doc/man: Fixed installation directory ([#970](https://github.com/stlink-org/stlink/pull/970)) @@ -264,7 +266,7 @@ Updates and fixes: - Debian packaging, `cmake` and `README.md` fixes ([#682](https://github.com/stlink-org/stlink/pull/682), [#683](https://github.com/stlink-org/stlink/pull/683)) - Disabled static library installation by default ([#702](https://github.com/stlink-org/stlink/pull/702)) - Fix for `libusb` deprecation ([#703](https://github.com/stlink-org/stlink/pull/703), [#704](https://github.com/stlink-org/stlink/pull/704)) -- Renamed `STLINK_CHIPID_STM32_L4R9` to `STLINK_CHIPID_STM32_L4RX` ([#706](https://github.com/stlink-org/stlink/pull/706)) +- Renamed `STLINK_CHIPID_STM32_L4R9` to `STLINK_CHIPID_STM32_L4Rx` ([#706](https://github.com/stlink-org/stlink/pull/706)) - [regression] stlink installation under Linux (Debian 9) is broken since #695 ([#700](https://github.com/stlink-org/stlink/pull/700), [#701](https://github.com/stlink-org/stlink/pull/701), [#707](https://github.com/stlink-org/stlink/pull/707)) - Fixed flash memory map for STM32F72xxx target ([#711](https://github.com/stlink-org/stlink/pull/711)) - Proper flash page size calculation for STM32F412xx target ([#721](https://github.com/stlink-org/stlink/pull/721)) diff --git a/doc/version_support.md b/doc/version_support.md index 6aafc8112..408c1be85 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -14,8 +14,8 @@ Up on compiling c-make will **automatically** download and install the latest co | Package Repository | libusb
      version | cmake
      version | gtk-3
      version | Supported macOS versions | | ------------------ | ------------------- | ------------------ | ------------------ | ------------------------ | -| homebrew | 1.0.23 | 3.17.0 | 3.24.18
      gtk+3 | 10.9 - 10.15 | -| MacPorts | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | 10.4 - 10.15 | +| homebrew | 1.0.23 | 3.17.0 | 3.24.18
      gtk+3 | 10.9 - 11.x | +| MacPorts | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | 10.4 - 11.x | NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 are required. From eafb4d17925296cf8c31f4309294c424d7174186 Mon Sep 17 00:00:00 2001 From: Jonathan Giles Date: Wed, 19 May 2021 10:40:40 -0400 Subject: [PATCH 1201/1435] Change description of chip id 0x0457 to L01x/L02x. --- src/stlink-lib/chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 13d065a27..711bf24b0 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -647,7 +647,7 @@ static const struct stlink_chipid_params devices[] = { { // STM32L011 .chip_id = STLINK_CHIPID_STM32_L011, - .description = "L011", + .description = "L01x/L02x", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, From 69239406344fbfe14b80af1cad8b91c3dea01950 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 21 May 2021 14:50:11 +0200 Subject: [PATCH 1202/1435] Corrected CHANGELOG.md --- CHANGELOG.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 5314ea912..57ed15e98 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -89,6 +89,7 @@ Fixes: - Fixed STM32WB55 reading DEBUG IDCODE from the wrong address ([#1100](https://github.com/stlink-org/stlink/pull/1100), [#1101](https://github.com/stlink-org/stlink/pull/1101)) - Applied missing changes to tests ([#1119](https://github.com/stlink-org/stlink/pull/1119)) - Improvements for Chip_ID read ([#1008](https://github.com/stlink-org/stlink/pull/1008), [#1120](https://github.com/stlink-org/stlink/pull/1120)) +- Fixed reading of chip ID on Cortex-M0+ core ([#1017](https://github.com/stlink-org/stlink/pull/1017), [#1125](https://github.com/stlink-org/stlink/pull/1125), [#1126](https://github.com/stlink-org/stlink/pull/1126), [#1133](https://github.com/stlink-org/stlink/pull/1133)) # v1.6.1 @@ -186,7 +187,6 @@ Fixes: - Set static link for `libssp` (stack-smashing protection) ([#960](https://github.com/stlink-org/stlink/pull/960), [#961](https://github.com/stlink-org/stlink/pull/961)) - Fixed udev rules installing to wrong directory ([#966](https://github.com/stlink-org/stlink/pull/966)) - Fixed formatting for options display in `st-flash` & `st-info` (commits [#c783d0e](https://github.com/stlink-org/stlink/commit/c783d0e777ccc83a7a8be26a4f4d3414e0478560) and [#562cd24](https://github.com/stlink-org/stlink/commit/562cd2496e696dbd22950925866aac662d81ee5f)) -- Fixed reading of chip ID on Cortex-M0+ core ([#1125](https://github.com/stlink-org/stlink/pull/1125), [#1126](https://github.com/stlink-org/stlink/pull/1126), [#1133](https://github.com/stlink-org/stlink/pull/1133)) # v1.6.0 From cab9fc4210ac090da6b7e45d91ffd300549a9436 Mon Sep 17 00:00:00 2001 From: anton Date: Sat, 22 May 2021 23:40:36 +0500 Subject: [PATCH 1203/1435] Improved command error messages --- inc/stlink.h | 8 +- src/common.c | 3 - src/stlink-lib/usb.c | 238 +++++++++++++++---------------------------- 3 files changed, 88 insertions(+), 161 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 69a4799f5..f70060b05 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -86,6 +86,8 @@ enum target_state { /* Error code */ #define STLINK_DEBUG_ERR_OK 0x80 #define STLINK_DEBUG_ERR_FAULT 0x81 +#define STLINK_DEBUG_ERR_WRITE 0x0c +#define STLINK_DEBUG_ERR_WRITE_VERIFY 0x0d #define STLINK_DEBUG_ERR_AP_WAIT 0x10 #define STLINK_DEBUG_ERR_AP_FAULT 0x11 #define STLINK_DEBUG_ERR_AP_ERROR 0x12 @@ -93,8 +95,10 @@ enum target_state { #define STLINK_DEBUG_ERR_DP_FAULT 0x15 #define STLINK_DEBUG_ERR_DP_ERROR 0x16 -#define CMD_NO_RETRY 0 -#define CMD_USE_RETRY 3 +#define CMD_CHECK_NO 0 +#define CMD_CHECK_REP_LEN 1 +#define CMD_CHECK_STATUS 2 +#define CMD_CHECK_RETRY 3 /* check status and retry if wait error */ #define C_BUF_LEN 32 diff --git a/src/common.c b/src/common.c index 661ee34ec..6333ff408 100644 --- a/src/common.c +++ b/src/common.c @@ -2301,9 +2301,6 @@ static void stlink_checksum(mapped_file_t *mp) { static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { unsigned int val; - // set stack - stlink_read_debug32(sl, addr, &val); - stlink_write_reg(sl, val, 13); // set PC to the reset routine stlink_read_debug32(sl, addr + 4, &val); stlink_write_reg(sl, val, 15); diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 5e17189c6..a58681702 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -85,56 +85,62 @@ void _stlink_usb_close(stlink_t* sl) { ssize_t send_recv(struct stlink_libusb* handle, int terminate, unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, - size_t rxsize, bool check_error, int retry_cnt) { + size_t rxsize, int check_error, const char *cmd) { // Note: txbuf and rxbuf can point to the same area int res, t, retry = 0; - int cmd = read_uint16(txbuf, (handle->protocoll == 1)?15:0); while (1) { res = 0; t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int)txsize, &res, 3000); if (t) { - ELOG("[!] send_recv send request failed: %s (command 0x%02X)\n", libusb_error_name(t), cmd); + ELOG("%s send request failed: %s\n", cmd, libusb_error_name(t)); return(-1); } else if ((size_t)res != txsize) { - ELOG("[!] send_recv send request wrote %u bytes, instead of %u (command 0x%02X)\n", - (unsigned int)res, (unsigned int)txsize, cmd); + ELOG("%s send request wrote %u bytes, instead of %u\n", + cmd, (unsigned int)res, (unsigned int)txsize); } if (rxsize != 0) { t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int)rxsize, &res, 3000); if (t) { - ELOG("[!] send_recv read reply failed: %s (command 0x%02X)\n", libusb_error_name(t), cmd); + ELOG("%s read reply failed: %s\n", cmd, libusb_error_name(t)); return(-1); } /* Checking the command execution status stored in the first byte of the response */ - if (handle->protocoll != 1 && check_error && + if (handle->protocoll != 1 && check_error >= CMD_CHECK_STATUS && rxbuf[0] != STLINK_DEBUG_ERR_OK) { switch(rxbuf[0]) { case STLINK_DEBUG_ERR_AP_WAIT: case STLINK_DEBUG_ERR_DP_WAIT: - if (retry < retry_cnt) { + if (check_error == CMD_CHECK_RETRY && retry < 3) { unsigned int delay_us = (1<protocoll == 1) && terminate) { @@ -143,7 +149,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); if (t) { - ELOG("[!] send_recv read storage failed: %s (command 0x%02X)\n", libusb_error_name(t), cmd); + ELOG("stlink: %s read storage failed: %s\n", cmd, libusb_error_name(t)); return(-1); } @@ -156,8 +162,9 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, } static inline int send_only(struct stlink_libusb* handle, int terminate, - unsigned char* txbuf, size_t txsize) { - return((int)send_recv(handle, terminate, txbuf, txsize, NULL, 0, false, CMD_NO_RETRY)); + unsigned char* txbuf, size_t txsize, + const char *cmd) { + return((int)send_recv(handle, terminate, txbuf, txsize, NULL, 0, CMD_CHECK_NO, cmd)); } @@ -201,12 +208,9 @@ int _stlink_usb_version(stlink_t *sl) { cmd[i++] = STLINK_GET_VERSION; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_USE_RETRY); - if (size != (ssize_t)rep_len) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_REP_LEN, "GET_VERSION"); - return(0); + return(size<0?-1:0); } int32_t _stlink_usb_target_voltage(stlink_t *sl) { @@ -221,13 +225,10 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { cmd[i++] = STLINK_GET_TARGET_VOLTAGE; - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, false, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_REP_LEN, "GET_TARGET_VOLTAGE"); if (size < 0) { return(-1); - } else if (size != 8) { - printf("[!] wrong length STLINK_GET_TARGET_VOLTAGE\n"); - return(-1); } factor = (rdata[3] << 24) | (rdata[2] << 16) | (rdata[1] << 8) | (rdata[0] << 0); @@ -248,10 +249,10 @@ int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_READDEBUGREG; write_uint32(&cmd[i], addr); - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, true, CMD_USE_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "READDEBUGREG"); if (size < 0) { - return((int)size); + return(-1); } *data = read_uint32(rdata, 4); @@ -271,13 +272,9 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { cmd[i++] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; write_uint32(&cmd[i], addr); write_uint32(&cmd[i + 4], data); - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, true, CMD_USE_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "WRITEDEBUGREG"); - if (size < 0) { - return((int)size); - } - - return(0); + return(size<0?-1:0); } int _stlink_usb_get_rw_status(stlink_t *sl) { @@ -294,15 +291,13 @@ int _stlink_usb_get_rw_status(stlink_t *sl) { if (sl->version.flags & STLINK_F_HAS_GETLASTRWSTATUS2) { cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS2; - ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 12, true, CMD_NO_RETRY); + ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 12, CMD_CHECK_STATUS, "GETLASTRWSTATUS2"); } else { cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS; - ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2, true, CMD_NO_RETRY); + ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2, CMD_CHECK_STATUS, "GETLASTRWSTATUS"); } - if (ret < 0) { return(-1); } - - return(0); + return(ret<0?-1:0); } int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -316,11 +311,11 @@ int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { cmd[i++] = STLINK_DEBUG_WRITEMEM_32BIT; write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); - ret = send_only(slu, 0, cmd, slu->cmd_len); + ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_32BIT"); if (ret == -1) { return(ret); } - ret = send_only(slu, 1, data, len); + ret = send_only(slu, 1, data, len, "WRITEMEM_32BIT"); if (ret == -1) { return(ret); } @@ -338,11 +333,11 @@ int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { cmd[i++] = STLINK_DEBUG_WRITEMEM_8BIT; write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); - ret = send_only(slu, 0, cmd, slu->cmd_len); + ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_32BIT"); if (ret == -1) { return(ret); } - ret = send_only(slu, 1, data, len); + ret = send_only(slu, 1, data, len, "WRITEMEM_32BIT"); if (ret == -1) { return(ret); } @@ -359,7 +354,7 @@ int _stlink_usb_current_mode(stlink_t * sl) { int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_GET_CURRENT_MODE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_CURRENT_MODE"); if (size < 0) { return(-1); @@ -386,7 +381,7 @@ int _stlink_usb_core_id(stlink_t * sl) { offset = 4; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READ_IDCODES"); if (size < 0) { return(-1); @@ -431,15 +426,9 @@ int _stlink_usb_status(stlink_t * sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_GETSTATUS; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_NO_RETRY); - - if (size < 0) { - return((int)size); - } - - sl->q_len = (int)size; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GETSTATUS"); - if (sl->q_len > 1) { + if (size > 1) { if (sl->q_buf[0] == STLINK_CORE_RUNNING) { sl->core_stat = TARGET_RUNNING; } else if (sl->q_buf[0] == STLINK_CORE_HALTED) { @@ -451,7 +440,7 @@ int _stlink_usb_status(stlink_t * sl) { sl->core_stat = TARGET_UNKNOWN; } - return(0); + return(size<0?-1:0); } int _stlink_usb_force_debug(stlink_t *sl) { @@ -472,13 +461,9 @@ int _stlink_usb_force_debug(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_FORCEDEBUG; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - - if (size < 0) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "FORCEDEBUG"); - return(0); + return(size<0?-1:0); } int _stlink_usb_enter_swd_mode(stlink_t * sl) { @@ -493,13 +478,9 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { // select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). cmd[i++] = sl->version.jtag_api == STLINK_JTAG_API_V1 ? STLINK_DEBUG_APIV1_ENTER : STLINK_DEBUG_APIV2_ENTER; cmd[i++] = STLINK_DEBUG_ENTER_SWD; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - - if (size < 0) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "ENTER_SWD"); - return(0); + return(size<0?-1:0); } int _stlink_usb_exit_dfu_mode(stlink_t* sl) { @@ -510,14 +491,9 @@ int _stlink_usb_exit_dfu_mode(stlink_t* sl) { cmd[i++] = STLINK_DFU_COMMAND; cmd[i++] = STLINK_DFU_EXIT; - size = send_only(slu, 1, cmd, slu->cmd_len); + size = send_only(slu, 1, cmd, slu->cmd_len, "DFU_EXIT"); - if (size == -1) { - printf("[!] send_recv STLINK_DFU_EXIT\n"); - return((int)size); - } - - return(0); + return(size<0?-1:0); } @@ -538,13 +514,9 @@ int _stlink_usb_reset(stlink_t * sl) { cmd[i++] = STLINK_DEBUG_APIV2_RESETSYS; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - - if (size < 0) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RESETSYS"); - return(0); + return(size<0?-1:0); } int _stlink_usb_jtag_reset(stlink_t * sl, int value) { @@ -558,13 +530,9 @@ int _stlink_usb_jtag_reset(stlink_t * sl, int value) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_DRIVE_NRST; cmd[i++] = value; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "DRIVE_NRST"); - if (size < 0) { - return((int)size); - } - - return(0); + return(size<0?-1:0); } @@ -589,13 +557,9 @@ int _stlink_usb_step(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_STEPCORE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "STEPCORE"); - if (size < 0) { - return((int)size); - } - - return(0); + return(size<0?-1:0); } /** @@ -624,13 +588,9 @@ int _stlink_usb_run(stlink_t* sl, enum run_type type) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_RUNCORE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - - if (size < 0) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RUNCORE"); - return(0); + return(size<0?-1:0); } int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { @@ -671,13 +631,9 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { cmd[i++] = STLINK_DEBUG_APIV2_SWD_SET_FREQ; cmd[i++] = clk_divisor & 0xFF; cmd[i++] = (clk_divisor >> 8) & 0xFF; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - - if (size < 0) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "SWD_SET_FREQ"); - return(0); + return(size<0?-1:0); } else if (sl->version.stlink_v == 3) { int speed_index; uint32_t map[STLINK_V3_MAX_FREQ_NB]; @@ -686,10 +642,10 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV3_GET_COM_FREQ; cmd[i++] = 0; // SWD mode - size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52, true, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52, CMD_CHECK_STATUS, "GET_COM_FREQ"); if (size < 0) { - return((int)size); + return(-1); } int speeds_size = data[8]; @@ -716,13 +672,9 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { cmd[i++] = (uint8_t)((map[speed_index] >> 16) & 0xFF); cmd[i++] = (uint8_t)((map[speed_index] >> 24) & 0xFF); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8, true, CMD_NO_RETRY); - - if (size < 0) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8, CMD_CHECK_STATUS, "SET_COM_FREQ"); - return(0); + return(size<0?-1:0); } else if (clk_freq) { WLOG("ST-Link firmware does not support frequency setup\n"); } @@ -739,14 +691,9 @@ int _stlink_usb_exit_debug_mode(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_EXIT; - size = send_only(slu, 1, cmd, slu->cmd_len); - - if (size == -1) { - printf("[!] send_only STLINK_DEBUG_EXIT\n"); - return((int)size); - } + size = send_only(slu, 1, cmd, slu->cmd_len, "DEBUG_EXIT"); - return(0); + return(size<0?-1:0); } int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -760,10 +707,10 @@ int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { cmd[i++] = STLINK_DEBUG_READMEM_32BIT; write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, len, false, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, len, CMD_CHECK_NO, "READMEM_32BIT"); if (size < 0) { - return((int)size); + return(-1); } sl->q_len = (int)size; @@ -788,10 +735,10 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { cmd[i++] = STLINK_DEBUG_APIV2_READALLREGS; } - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READALLREGS"); if (size < 0) { - return((int)size); + return(-1); } /* V1: regs data from offset 0 */ @@ -838,10 +785,10 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { } cmd[i++] = (uint8_t)r_idx; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "READREG"); if (size < 0) { - return((int)size); + return(-1); } sl->q_len = (int)size; @@ -1004,16 +951,9 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { cmd[i++] = idx; write_uint32(&cmd[i], reg); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_USE_RETRY); - - if (size < 0) { - return((int)size); - } + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "WRITEREG"); - sl->q_len = (int)size; - stlink_print_data(sl); - - return(0); + return(size<0?-1:0); } int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { @@ -1029,16 +969,9 @@ int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); write_uint32(&cmd[i + 2], frequency); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "START_TRACE_RX"); - if (size < 0) { - return((int)size); - } - - sl->q_len = (int)size; - stlink_print_data(sl); - - return(0); + return(size<0?-1:0); } int _stlink_usb_disable_trace(stlink_t* sl) { @@ -1052,16 +985,9 @@ int _stlink_usb_disable_trace(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, true, CMD_NO_RETRY); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "STOP_TRACE_RX"); - if (size < 0) { - return((int)size); - } - - sl->q_len = (int)size; - stlink_print_data(sl); - - return(0); + return(size<0?-1:0); } int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { @@ -1073,13 +999,13 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_GET_TRACE_NB; - ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, false, CMD_NO_RETRY); + ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_TRACE_NB"); if (send_size < 0) { - return((int)send_size); + return(-1); } else if (send_size != 2) { ELOG("STLINK_DEBUG_APIV2_GET_TRACE_NB reply size %d\n", (int)send_size); - return -1; + return(-1); } uint16_t trace_count = read_uint16(sl->q_buf, 0); From 90887edb2eef946d3bd0bda7769a95c076667f7b Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Sun, 23 May 2021 08:42:36 +0200 Subject: [PATCH 1204/1435] removed debug dump --- src/stlink-lib/chipid.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 51da33322..02f117416 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -806,6 +806,7 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { p2 = stlink_chipid_get_params_old (chipid); +#if 1 if (memcmp (p2, params, sizeof (struct stlink_chipid_params) - sizeof (struct stlink_chipid_params *)) != 0) { //fprintf (stderr, "Error, chipid params not identical\n"); //return NULL; @@ -814,6 +815,7 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { fprintf (stderr, "---------- new ------------\n"); dump_a_chip (stderr, params); } +#endif return(params); } From d5b901b89957641a46ef4865620f989bf94e01d6 Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Sun, 23 May 2021 08:52:36 +0200 Subject: [PATCH 1205/1435] removed filename-spaces --- config/chips/{F0xx small.chip => F0xx_small.chip} | 0 config/chips/{F1 XL-density.chip => F1_XL-density.chip} | 0 .../{F1 connectivity line.chip => F1_connectivity_line.chip} | 0 config/chips/{F1 high-density.chip => F1_high-density.chip} | 0 config/chips/{F1 low-density.chip => F1_low-density.chip} | 0 config/chips/{F1 medium-density.chip => F1_medium-density.chip} | 0 config/chips/{F1 value line.chip => F1_value_line.chip} | 0 ...lue line high-density.chip => F1_value_line_high-density.chip} | 0 config/chips/{F303 high density.chip => F303_high_density.chip} | 0 .../chips/{F334 medium density.chip => F334_medium_density.chip} | 0 ...{F4xx dynamic efficiency.chip => F4xx_dynamic_efficiency.chip} | 0 config/chips/{F4xx low power.chip => F4xx_low_power.chip} | 0 config/chips/{G4 cat2.chip => G4_cat2.chip} | 0 config/chips/{G4 cat3.chip => G4_cat3.chip} | 0 config/chips/{L0xx cat2.chip => L0xx_cat2.chip} | 0 config/chips/{L0xx cat5.chip => L0xx_cat5.chip} | 0 config/chips/{L1xx cat2.chip => L1xx_cat2.chip} | 0 config/chips/{L1xx high-density.chip => L1xx_high-density.chip} | 0 .../chips/{L1xx medium-density.chip => L1xx_medium-density.chip} | 0 ...1xx medium-plus-density.chip => L1xx_medium-plus-density.chip} | 0 config/chips/{unknown device.chip => unknown_device.chip} | 0 21 files changed, 0 insertions(+), 0 deletions(-) rename config/chips/{F0xx small.chip => F0xx_small.chip} (100%) rename config/chips/{F1 XL-density.chip => F1_XL-density.chip} (100%) rename config/chips/{F1 connectivity line.chip => F1_connectivity_line.chip} (100%) rename config/chips/{F1 high-density.chip => F1_high-density.chip} (100%) rename config/chips/{F1 low-density.chip => F1_low-density.chip} (100%) rename config/chips/{F1 medium-density.chip => F1_medium-density.chip} (100%) rename config/chips/{F1 value line.chip => F1_value_line.chip} (100%) rename config/chips/{F1 value line high-density.chip => F1_value_line_high-density.chip} (100%) rename config/chips/{F303 high density.chip => F303_high_density.chip} (100%) rename config/chips/{F334 medium density.chip => F334_medium_density.chip} (100%) rename config/chips/{F4xx dynamic efficiency.chip => F4xx_dynamic_efficiency.chip} (100%) rename config/chips/{F4xx low power.chip => F4xx_low_power.chip} (100%) rename config/chips/{G4 cat2.chip => G4_cat2.chip} (100%) rename config/chips/{G4 cat3.chip => G4_cat3.chip} (100%) rename config/chips/{L0xx cat2.chip => L0xx_cat2.chip} (100%) rename config/chips/{L0xx cat5.chip => L0xx_cat5.chip} (100%) rename config/chips/{L1xx cat2.chip => L1xx_cat2.chip} (100%) rename config/chips/{L1xx high-density.chip => L1xx_high-density.chip} (100%) rename config/chips/{L1xx medium-density.chip => L1xx_medium-density.chip} (100%) rename config/chips/{L1xx medium-plus-density.chip => L1xx_medium-plus-density.chip} (100%) rename config/chips/{unknown device.chip => unknown_device.chip} (100%) diff --git a/config/chips/F0xx small.chip b/config/chips/F0xx_small.chip similarity index 100% rename from config/chips/F0xx small.chip rename to config/chips/F0xx_small.chip diff --git a/config/chips/F1 XL-density.chip b/config/chips/F1_XL-density.chip similarity index 100% rename from config/chips/F1 XL-density.chip rename to config/chips/F1_XL-density.chip diff --git a/config/chips/F1 connectivity line.chip b/config/chips/F1_connectivity_line.chip similarity index 100% rename from config/chips/F1 connectivity line.chip rename to config/chips/F1_connectivity_line.chip diff --git a/config/chips/F1 high-density.chip b/config/chips/F1_high-density.chip similarity index 100% rename from config/chips/F1 high-density.chip rename to config/chips/F1_high-density.chip diff --git a/config/chips/F1 low-density.chip b/config/chips/F1_low-density.chip similarity index 100% rename from config/chips/F1 low-density.chip rename to config/chips/F1_low-density.chip diff --git a/config/chips/F1 medium-density.chip b/config/chips/F1_medium-density.chip similarity index 100% rename from config/chips/F1 medium-density.chip rename to config/chips/F1_medium-density.chip diff --git a/config/chips/F1 value line.chip b/config/chips/F1_value_line.chip similarity index 100% rename from config/chips/F1 value line.chip rename to config/chips/F1_value_line.chip diff --git a/config/chips/F1 value line high-density.chip b/config/chips/F1_value_line_high-density.chip similarity index 100% rename from config/chips/F1 value line high-density.chip rename to config/chips/F1_value_line_high-density.chip diff --git a/config/chips/F303 high density.chip b/config/chips/F303_high_density.chip similarity index 100% rename from config/chips/F303 high density.chip rename to config/chips/F303_high_density.chip diff --git a/config/chips/F334 medium density.chip b/config/chips/F334_medium_density.chip similarity index 100% rename from config/chips/F334 medium density.chip rename to config/chips/F334_medium_density.chip diff --git a/config/chips/F4xx dynamic efficiency.chip b/config/chips/F4xx_dynamic_efficiency.chip similarity index 100% rename from config/chips/F4xx dynamic efficiency.chip rename to config/chips/F4xx_dynamic_efficiency.chip diff --git a/config/chips/F4xx low power.chip b/config/chips/F4xx_low_power.chip similarity index 100% rename from config/chips/F4xx low power.chip rename to config/chips/F4xx_low_power.chip diff --git a/config/chips/G4 cat2.chip b/config/chips/G4_cat2.chip similarity index 100% rename from config/chips/G4 cat2.chip rename to config/chips/G4_cat2.chip diff --git a/config/chips/G4 cat3.chip b/config/chips/G4_cat3.chip similarity index 100% rename from config/chips/G4 cat3.chip rename to config/chips/G4_cat3.chip diff --git a/config/chips/L0xx cat2.chip b/config/chips/L0xx_cat2.chip similarity index 100% rename from config/chips/L0xx cat2.chip rename to config/chips/L0xx_cat2.chip diff --git a/config/chips/L0xx cat5.chip b/config/chips/L0xx_cat5.chip similarity index 100% rename from config/chips/L0xx cat5.chip rename to config/chips/L0xx_cat5.chip diff --git a/config/chips/L1xx cat2.chip b/config/chips/L1xx_cat2.chip similarity index 100% rename from config/chips/L1xx cat2.chip rename to config/chips/L1xx_cat2.chip diff --git a/config/chips/L1xx high-density.chip b/config/chips/L1xx_high-density.chip similarity index 100% rename from config/chips/L1xx high-density.chip rename to config/chips/L1xx_high-density.chip diff --git a/config/chips/L1xx medium-density.chip b/config/chips/L1xx_medium-density.chip similarity index 100% rename from config/chips/L1xx medium-density.chip rename to config/chips/L1xx_medium-density.chip diff --git a/config/chips/L1xx medium-plus-density.chip b/config/chips/L1xx_medium-plus-density.chip similarity index 100% rename from config/chips/L1xx medium-plus-density.chip rename to config/chips/L1xx_medium-plus-density.chip diff --git a/config/chips/unknown device.chip b/config/chips/unknown_device.chip similarity index 100% rename from config/chips/unknown device.chip rename to config/chips/unknown_device.chip From 157c587b93fb8e0f46696610b6f78d4a24609ef9 Mon Sep 17 00:00:00 2001 From: "R.E. Wolff" Date: Sun, 23 May 2021 10:50:43 +0200 Subject: [PATCH 1206/1435] cleanup integer handling in chipid and text flags --- config/chips/F04x.chip | 14 ++--- config/chips/F07x.chip | 14 ++--- config/chips/F09x.chip | 14 ++--- config/chips/F0xx.chip | 14 ++--- config/chips/F0xx_small.chip | 14 ++--- config/chips/F1_XL-density.chip | 14 ++--- config/chips/F1_connectivity_line.chip | 14 ++--- config/chips/F1_high-density.chip | 14 ++--- config/chips/F1_low-density.chip | 14 ++--- config/chips/F1_medium-density.chip | 14 ++--- config/chips/F1_value_line.chip | 14 ++--- config/chips/F1_value_line_high-density.chip | 14 ++--- config/chips/F2.chip | 14 ++--- config/chips/F303_high_density.chip | 14 ++--- config/chips/F334_medium_density.chip | 14 ++--- config/chips/F37x.chip | 14 ++--- config/chips/F3xx_small.chip | 14 ++--- config/chips/F410.chip | 14 ++--- config/chips/F411xx.chip | 14 ++--- config/chips/F412.chip | 14 ++--- config/chips/F413.chip | 14 ++--- config/chips/F42x_F43x.chip | 14 ++--- config/chips/F446.chip | 14 ++--- config/chips/F46x_F47x.chip | 14 ++--- config/chips/F4xx.chip | 14 ++--- config/chips/F4xx_dynamic_efficiency.chip | 14 ++--- config/chips/F4xx_low_power.chip | 14 ++--- config/chips/F72x_F73x.chip | 14 ++--- config/chips/F76xxx.chip | 14 ++--- config/chips/F7xx.chip | 14 ++--- config/chips/G030_G031_G041.chip | 14 ++--- config/chips/G070_G071_G081.chip | 14 ++--- config/chips/G4_cat2.chip | 14 ++--- config/chips/G4_cat3.chip | 14 ++--- config/chips/H72x_H73x.chip | 16 +++--- config/chips/H74x_H75x.chip | 16 +++--- config/chips/H7Ax_H7Bx.chip | 16 +++--- config/chips/L011.chip | 14 ++--- config/chips/L0x3.chip | 16 +++--- config/chips/L0xx_cat2.chip | 14 ++--- config/chips/L0xx_cat5.chip | 14 ++--- config/chips/L152RE.chip | 14 ++--- config/chips/L1xx_cat2.chip | 14 ++--- config/chips/L1xx_high-density.chip | 14 ++--- config/chips/L1xx_medium-density.chip | 14 ++--- config/chips/L1xx_medium-plus-density.chip | 14 ++--- config/chips/L41x.chip | 14 ++--- config/chips/L43x_L44x.chip | 14 ++--- config/chips/L45x_L46x.chip | 14 ++--- config/chips/L496x_L4A6x.chip | 14 ++--- config/chips/L4Rx.chip | 14 ++--- config/chips/L4xx.chip | 14 ++--- config/chips/WB55.chip | 14 ++--- config/chips/unknown_device.chip | 14 ++--- src/stlink-lib/chipid.c | 56 +++++++++++++------- 55 files changed, 418 insertions(+), 402 deletions(-) diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 059ae5bc6..b42d420fa 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -1,13 +1,13 @@ # Chip-ID file for F04x # -chip_id 445 +chip_id 0x445 description F04x flash_type 1 flash_pagesize 400 -sram_size 1800 -bootrom_base 1fffec00 -bootrom_size c00 -option_base 0 -option_size 0 -flags 0 +sram_size 0x1800 +bootrom_base 0x1fffec00 +bootrom_size 0xc00 +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index ba839baed..d8c71f0ea 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -1,13 +1,13 @@ # Chip-ID file for F07x # -chip_id 448 +chip_id 0x448 description F07x flash_type 1 flash_pagesize 800 -sram_size 4000 -bootrom_base 1fffc800 -bootrom_size 3000 -option_base 0 -option_size 0 -flags 0 +sram_size 0x4000 +bootrom_base 0x1fffc800 +bootrom_size 0x3000 +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index 727fc1fa4..ca97d53e4 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -1,13 +1,13 @@ # Chip-ID file for F09x # -chip_id 442 +chip_id 0x442 description F09x flash_type 1 flash_pagesize 800 -sram_size 8000 -bootrom_base 1fffd800 -bootrom_size 2000 -option_base 0 -option_size 0 -flags 0 +sram_size 0x8000 +bootrom_base 0x1fffd800 +bootrom_size 0x2000 +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/F0xx.chip b/config/chips/F0xx.chip index 9c0f60bd9..a1700eef3 100644 --- a/config/chips/F0xx.chip +++ b/config/chips/F0xx.chip @@ -1,13 +1,13 @@ # Chip-ID file for F0xx # -chip_id 440 +chip_id 0x440 description F0xx flash_type 1 flash_pagesize 400 -sram_size 2000 -bootrom_base 1fffec00 -bootrom_size c00 -option_base 0 -option_size 0 -flags 0 +sram_size 0x2000 +bootrom_base 0x1fffec00 +bootrom_size 0xc00 +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/F0xx_small.chip b/config/chips/F0xx_small.chip index efa51c284..3ab256feb 100644 --- a/config/chips/F0xx_small.chip +++ b/config/chips/F0xx_small.chip @@ -1,13 +1,13 @@ # Chip-ID file for F0xx small # -chip_id 444 +chip_id 0x444 description F0xx small flash_type 1 flash_pagesize 400 -sram_size 1000 -bootrom_base 1fffec00 -bootrom_size c00 -option_base 0 -option_size 0 -flags 0 +sram_size 0x1000 +bootrom_base 0x1fffec00 +bootrom_size 0xc00 +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/F1_XL-density.chip b/config/chips/F1_XL-density.chip index 70cdfd3bb..97bb580e3 100644 --- a/config/chips/F1_XL-density.chip +++ b/config/chips/F1_XL-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for F1 XL-density # -chip_id 430 +chip_id 0x430 description F1 XL-density flash_type 2 flash_pagesize 800 -sram_size 18000 -bootrom_base 1fffe000 -bootrom_size 1800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x18000 +bootrom_base 0x1fffe000 +bootrom_size 0x1800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F1_connectivity_line.chip b/config/chips/F1_connectivity_line.chip index 14678112d..a030fd58d 100644 --- a/config/chips/F1_connectivity_line.chip +++ b/config/chips/F1_connectivity_line.chip @@ -1,13 +1,13 @@ # Chip-ID file for F1 connectivity line # -chip_id 418 +chip_id 0x418 description F1 connectivity line flash_type 1 flash_pagesize 800 -sram_size 10000 -bootrom_base 1fffb000 -bootrom_size 4800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x10000 +bootrom_base 0x1fffb000 +bootrom_size 0x4800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F1_high-density.chip b/config/chips/F1_high-density.chip index 3d4cff724..00e4942b0 100644 --- a/config/chips/F1_high-density.chip +++ b/config/chips/F1_high-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for F1 high-density # -chip_id 414 +chip_id 0x414 description F1 high-density flash_type 1 flash_pagesize 800 -sram_size 10000 -bootrom_base 1ffff000 -bootrom_size 800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x10000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F1_low-density.chip b/config/chips/F1_low-density.chip index 9905ce405..1562c7589 100644 --- a/config/chips/F1_low-density.chip +++ b/config/chips/F1_low-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for F1 low-density # -chip_id 412 +chip_id 0x412 description F1 low-density flash_type 1 flash_pagesize 400 -sram_size 2800 -bootrom_base 1ffff000 -bootrom_size 800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x2800 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F1_medium-density.chip b/config/chips/F1_medium-density.chip index 00af4f18d..1f3d89234 100644 --- a/config/chips/F1_medium-density.chip +++ b/config/chips/F1_medium-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for F1 medium-density # -chip_id 410 +chip_id 0x410 description F1 medium-density flash_type 1 flash_pagesize 400 -sram_size 5000 -bootrom_base 1ffff000 -bootrom_size 800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x5000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F1_value_line.chip b/config/chips/F1_value_line.chip index 8356357b0..d9f04f00a 100644 --- a/config/chips/F1_value_line.chip +++ b/config/chips/F1_value_line.chip @@ -1,13 +1,13 @@ # Chip-ID file for F1 value line # -chip_id 420 +chip_id 0x420 description F1 value line flash_type 1 flash_pagesize 400 -sram_size 2000 -bootrom_base 1ffff000 -bootrom_size 800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x2000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F1_value_line_high-density.chip b/config/chips/F1_value_line_high-density.chip index c076e284c..2ecf6b4f5 100644 --- a/config/chips/F1_value_line_high-density.chip +++ b/config/chips/F1_value_line_high-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for F1 value line high-density # -chip_id 428 +chip_id 0x428 description F1 value line high-density flash_type 1 flash_pagesize 800 -sram_size 8000 -bootrom_base 1ffff000 -bootrom_size 800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x8000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F2.chip b/config/chips/F2.chip index 8830363d2..098ddc863 100644 --- a/config/chips/F2.chip +++ b/config/chips/F2.chip @@ -1,13 +1,13 @@ # Chip-ID file for F2 # -chip_id 411 +chip_id 0x411 description F2 flash_type 3 flash_pagesize 20000 -sram_size 20000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 1fffc000 -option_size 4 -flags 2 +sram_size 0x20000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x1fffc000 +option_size 0x4 +flags swo diff --git a/config/chips/F303_high_density.chip b/config/chips/F303_high_density.chip index e8b57ee24..19cc2ad2a 100644 --- a/config/chips/F303_high_density.chip +++ b/config/chips/F303_high_density.chip @@ -1,13 +1,13 @@ # Chip-ID file for F303 high density # -chip_id 446 +chip_id 0x446 description F303 high density flash_type 1 flash_pagesize 800 -sram_size 10000 -bootrom_base 1fffd800 -bootrom_size 2000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x10000 +bootrom_base 0x1fffd800 +bootrom_size 0x2000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F334_medium_density.chip b/config/chips/F334_medium_density.chip index 460e22a67..ba4cf9688 100644 --- a/config/chips/F334_medium_density.chip +++ b/config/chips/F334_medium_density.chip @@ -1,13 +1,13 @@ # Chip-ID file for F334 medium density # -chip_id 438 +chip_id 0x438 description F334 medium density flash_type 1 flash_pagesize 800 -sram_size 3000 -bootrom_base 1fffd800 -bootrom_size 2000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x3000 +bootrom_base 0x1fffd800 +bootrom_size 0x2000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index 424209a03..d0081e68a 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -1,13 +1,13 @@ # Chip-ID file for F37x # -chip_id 432 +chip_id 0x432 description F37x flash_type 1 flash_pagesize 800 -sram_size a000 -bootrom_base 1ffff000 -bootrom_size 800 -option_base 0 -option_size 0 -flags 2 +sram_size 0xa000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F3xx_small.chip b/config/chips/F3xx_small.chip index 91722905c..34d1940ac 100644 --- a/config/chips/F3xx_small.chip +++ b/config/chips/F3xx_small.chip @@ -1,13 +1,13 @@ # Chip-ID file for F3xx small # -chip_id 439 +chip_id 0x439 description F3xx small flash_type 1 flash_pagesize 800 -sram_size a000 -bootrom_base 1fffd800 -bootrom_size 2000 -option_base 0 -option_size 0 -flags 2 +sram_size 0xa000 +bootrom_base 0x1fffd800 +bootrom_size 0x2000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F410.chip b/config/chips/F410.chip index 53f01c669..3cd382845 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -1,13 +1,13 @@ # Chip-ID file for F410 # -chip_id 458 +chip_id 0x458 description F410 flash_type 3 flash_pagesize 4000 -sram_size 8000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x8000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F411xx.chip b/config/chips/F411xx.chip index 26390d0e6..301e6cb91 100644 --- a/config/chips/F411xx.chip +++ b/config/chips/F411xx.chip @@ -1,13 +1,13 @@ # Chip-ID file for F411xx # -chip_id 431 +chip_id 0x431 description F411xx flash_type 3 flash_pagesize 4000 -sram_size 20000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x20000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F412.chip b/config/chips/F412.chip index e78b81ee1..186a43427 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -1,13 +1,13 @@ # Chip-ID file for F412 # -chip_id 441 +chip_id 0x441 description F412 flash_type 3 flash_pagesize 4000 -sram_size 40000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x40000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F413.chip b/config/chips/F413.chip index 4ea974f2c..367344aaa 100644 --- a/config/chips/F413.chip +++ b/config/chips/F413.chip @@ -1,13 +1,13 @@ # Chip-ID file for F413 # -chip_id 463 +chip_id 0x463 description F413 flash_type 3 flash_pagesize 4000 -sram_size 50000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x50000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 2073486cf..4557a731c 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -1,13 +1,13 @@ # Chip-ID file for F42x/F43x # -chip_id 419 +chip_id 0x419 description F42x/F43x flash_type 3 flash_pagesize 4000 -sram_size 40000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x40000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 7d2ded465..9f7ae0bc5 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -1,13 +1,13 @@ # Chip-ID file for F446 # -chip_id 421 +chip_id 0x421 description F446 flash_type 3 flash_pagesize 20000 -sram_size 20000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 1fffc000 -option_size 4 -flags 2 +sram_size 0x20000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x1fffc000 +option_size 0x4 +flags swo diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index 75e1ea045..8ae43eb2e 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -1,13 +1,13 @@ # Chip-ID file for F46x/F47x # -chip_id 434 +chip_id 0x434 description F46x/F47x flash_type 3 flash_pagesize 4000 -sram_size 40000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x40000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F4xx.chip b/config/chips/F4xx.chip index 70f298b79..17ec62d68 100644 --- a/config/chips/F4xx.chip +++ b/config/chips/F4xx.chip @@ -1,13 +1,13 @@ # Chip-ID file for F4xx # -chip_id 413 +chip_id 0x413 description F4xx flash_type 3 flash_pagesize 4000 -sram_size 30000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 40023c14 -option_size 4 -flags 2 +sram_size 0x30000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x40023c14 +option_size 0x4 +flags swo diff --git a/config/chips/F4xx_dynamic_efficiency.chip b/config/chips/F4xx_dynamic_efficiency.chip index 33bfa23c2..6d06bcb8e 100644 --- a/config/chips/F4xx_dynamic_efficiency.chip +++ b/config/chips/F4xx_dynamic_efficiency.chip @@ -1,13 +1,13 @@ # Chip-ID file for F4xx dynamic efficiency # -chip_id 433 +chip_id 0x433 description F4xx dynamic efficiency flash_type 3 flash_pagesize 4000 -sram_size 18000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x18000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F4xx_low_power.chip b/config/chips/F4xx_low_power.chip index f52595d5d..ad8c3ce90 100644 --- a/config/chips/F4xx_low_power.chip +++ b/config/chips/F4xx_low_power.chip @@ -1,13 +1,13 @@ # Chip-ID file for F4xx low power # -chip_id 423 +chip_id 0x423 description F4xx low power flash_type 3 flash_pagesize 4000 -sram_size 10000 -bootrom_base 1fff0000 -bootrom_size 7800 -option_base 0 -option_size 0 -flags 2 +sram_size 0x10000 +bootrom_base 0x1fff0000 +bootrom_size 0x7800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index ba275bb0b..b6f706994 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -1,13 +1,13 @@ # Chip-ID file for F72x/F73x # -chip_id 452 +chip_id 0x452 description F72x/F73x flash_type 3 flash_pagesize 800 -sram_size 40000 -bootrom_base 100000 -bootrom_size edc0 -option_base 0 -option_size 0 -flags 2 +sram_size 0x40000 +bootrom_base 0x100000 +bootrom_size 0xedc0 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F76xxx.chip b/config/chips/F76xxx.chip index 7f8cfdaf0..49ac1ec21 100644 --- a/config/chips/F76xxx.chip +++ b/config/chips/F76xxx.chip @@ -1,13 +1,13 @@ # Chip-ID file for F76xxx # -chip_id 451 +chip_id 0x451 description F76xxx flash_type 4 flash_pagesize 800 -sram_size 80000 -bootrom_base 200000 -bootrom_size edc0 -option_base 1fff0000 -option_size 20 -flags 2 +sram_size 0x80000 +bootrom_base 0x200000 +bootrom_size 0xedc0 +option_base 0x1fff0000 +option_size 0x20 +flags swo diff --git a/config/chips/F7xx.chip b/config/chips/F7xx.chip index c031b5f4a..87420f2ab 100644 --- a/config/chips/F7xx.chip +++ b/config/chips/F7xx.chip @@ -1,13 +1,13 @@ # Chip-ID file for F7xx # -chip_id 449 +chip_id 0x449 description F7xx flash_type 3 flash_pagesize 800 -sram_size 50000 -bootrom_base 100000 -bootrom_size edc0 -option_base 0 -option_size 0 -flags 2 +sram_size 0x50000 +bootrom_base 0x100000 +bootrom_size 0xedc0 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/G030_G031_G041.chip b/config/chips/G030_G031_G041.chip index a1c42f58f..7d47e7aed 100644 --- a/config/chips/G030_G031_G041.chip +++ b/config/chips/G030_G031_G041.chip @@ -1,13 +1,13 @@ # Chip-ID file for G030/G031/G041 # -chip_id 466 +chip_id 0x466 description G030/G031/G041 flash_type 7 flash_pagesize 800 -sram_size 2000 -bootrom_base 1fff0000 -bootrom_size 2000 -option_base 1fff7800 -option_size 4 -flags 0 +sram_size 0x2000 +bootrom_base 0x1fff0000 +bootrom_size 0x2000 +option_base 0x1fff7800 +option_size 0x4 +flags none diff --git a/config/chips/G070_G071_G081.chip b/config/chips/G070_G071_G081.chip index 58eb16b16..9905fc682 100644 --- a/config/chips/G070_G071_G081.chip +++ b/config/chips/G070_G071_G081.chip @@ -1,13 +1,13 @@ # Chip-ID file for G070/G071/G081 # -chip_id 460 +chip_id 0x460 description G070/G071/G081 flash_type 7 flash_pagesize 800 -sram_size 9000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 1fff7800 -option_size 4 -flags 0 +sram_size 0x9000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1fff7800 +option_size 0x4 +flags none diff --git a/config/chips/G4_cat2.chip b/config/chips/G4_cat2.chip index 309cbb83f..47745e715 100644 --- a/config/chips/G4_cat2.chip +++ b/config/chips/G4_cat2.chip @@ -1,13 +1,13 @@ # Chip-ID file for G4 cat2 # -chip_id 468 +chip_id 0x468 description G4 cat2 flash_type 8 flash_pagesize 800 -sram_size 8000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 1ffff800 -option_size 4 -flags 2 +sram_size 0x8000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1ffff800 +option_size 0x4 +flags swo diff --git a/config/chips/G4_cat3.chip b/config/chips/G4_cat3.chip index 357522b31..f883b9176 100644 --- a/config/chips/G4_cat3.chip +++ b/config/chips/G4_cat3.chip @@ -1,13 +1,13 @@ # Chip-ID file for G4 cat3 # -chip_id 469 +chip_id 0x469 description G4 cat3 flash_type 8 flash_pagesize 800 -sram_size 18000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 1ffff800 -option_size 4 -flags 3 +sram_size 0x18000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1ffff800 +option_size 0x4 +flags dualbank swo diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index 43c8ae67b..81c1b71c9 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -1,13 +1,13 @@ # Chip-ID file for H72x/H73x # -chip_id 483 +chip_id 0x483 description H72x/H73x -flash_type a +flash_type 10 flash_pagesize 20000 -sram_size 20000 -bootrom_base 1ff00000 -bootrom_size 20000 -option_base 5200201c -option_size 2c -flags 2 +sram_size 0x20000 +bootrom_base 0x1ff00000 +bootrom_size 0x20000 +option_base 0x5200201c +option_size 0x2c +flags swo diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index c4d374e60..7753cfe03 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -1,13 +1,13 @@ # Chip-ID file for H74x/H75x # -chip_id 450 +chip_id 0x450 description H74x/H75x -flash_type a +flash_type 10 flash_pagesize 20000 -sram_size 20000 -bootrom_base 1ff00000 -bootrom_size 20000 -option_base 5200201c -option_size 2c -flags 3 +sram_size 0x20000 +bootrom_base 0x1ff00000 +bootrom_size 0x20000 +option_base 0x5200201c +option_size 0x2c +flags dualbank swo diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index b17631385..df6c13726 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -1,13 +1,13 @@ # Chip-ID file for H7Ax/H7Bx # -chip_id 480 +chip_id 0x480 description H7Ax/H7Bx -flash_type a +flash_type 10 flash_pagesize 2000 -sram_size 20000 -bootrom_base 1ff00000 -bootrom_size 20000 -option_base 5200201c -option_size 2c -flags 3 +sram_size 0x20000 +bootrom_base 0x1ff00000 +bootrom_size 0x20000 +option_base 0x5200201c +option_size 0x2c +flags dualbank swo diff --git a/config/chips/L011.chip b/config/chips/L011.chip index 6d8298848..2f1fa7b56 100644 --- a/config/chips/L011.chip +++ b/config/chips/L011.chip @@ -1,13 +1,13 @@ # Chip-ID file for L011 # -chip_id 457 +chip_id 0x457 description L011 flash_type 5 flash_pagesize 80 -sram_size 2000 -bootrom_base 1ff00000 -bootrom_size 2000 -option_base 0 -option_size 0 -flags 0 +sram_size 0x2000 +bootrom_base 0x1ff00000 +bootrom_size 0x2000 +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/L0x3.chip b/config/chips/L0x3.chip index 4bfc318c0..cbdc6cace 100644 --- a/config/chips/L0x3.chip +++ b/config/chips/L0x3.chip @@ -1,13 +1,13 @@ # Chip-ID file for L0x3 # -chip_id 417 +chip_id 0x417 description L0x3 flash_type 5 -flash_pagesize 80 -sram_size 2000 -bootrom_base 1ff0000 -bootrom_size 1000 -option_base 1ff80000 -option_size 14 -flags 0 +flash_pagesize 0x80 +sram_size 0x2000 +bootrom_base 0x1ff0000 +bootrom_size 0x1000 +option_base 0x1ff80000 +option_size 0x14 +flags none diff --git a/config/chips/L0xx_cat2.chip b/config/chips/L0xx_cat2.chip index 8b24634cf..43a301b27 100644 --- a/config/chips/L0xx_cat2.chip +++ b/config/chips/L0xx_cat2.chip @@ -1,13 +1,13 @@ # Chip-ID file for L0xx cat2 # -chip_id 425 +chip_id 0x425 description L0xx cat2 flash_type 5 flash_pagesize 80 -sram_size 2000 -bootrom_base 1ff0000 -bootrom_size 1000 -option_base 1ff80000 -option_size 14 -flags 0 +sram_size 0x2000 +bootrom_base 0x1ff0000 +bootrom_size 0x1000 +option_base 0x1ff80000 +option_size 0x14 +flags none diff --git a/config/chips/L0xx_cat5.chip b/config/chips/L0xx_cat5.chip index b52f97363..8ab0a50f8 100644 --- a/config/chips/L0xx_cat5.chip +++ b/config/chips/L0xx_cat5.chip @@ -1,13 +1,13 @@ # Chip-ID file for L0xx cat5 # -chip_id 447 +chip_id 0x447 description L0xx cat5 flash_type 5 flash_pagesize 80 -sram_size 5000 -bootrom_base 1ff0000 -bootrom_size 2000 -option_base 1ff80000 -option_size 14 -flags 0 +sram_size 0x5000 +bootrom_base 0x1ff0000 +bootrom_size 0x2000 +option_base 0x1ff80000 +option_size 0x14 +flags none diff --git a/config/chips/L152RE.chip b/config/chips/L152RE.chip index c073ade93..ebe012c5a 100644 --- a/config/chips/L152RE.chip +++ b/config/chips/L152RE.chip @@ -1,13 +1,13 @@ # Chip-ID file for L152RE # -chip_id 437 +chip_id 0x437 description L152RE flash_type 5 flash_pagesize 100 -sram_size 14000 -bootrom_base 1ff00000 -bootrom_size 1000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x14000 +bootrom_base 0x1ff00000 +bootrom_size 0x1000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L1xx_cat2.chip b/config/chips/L1xx_cat2.chip index dd89c981c..02012078a 100644 --- a/config/chips/L1xx_cat2.chip +++ b/config/chips/L1xx_cat2.chip @@ -1,13 +1,13 @@ # Chip-ID file for L1xx cat2 # -chip_id 429 +chip_id 0x429 description L1xx cat2 flash_type 5 flash_pagesize 100 -sram_size 8000 -bootrom_base 1ff00000 -bootrom_size 1000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x8000 +bootrom_base 0x1ff00000 +bootrom_size 0x1000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L1xx_high-density.chip b/config/chips/L1xx_high-density.chip index 8e5b0cd44..130b4e456 100644 --- a/config/chips/L1xx_high-density.chip +++ b/config/chips/L1xx_high-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for L1xx high-density # -chip_id 436 +chip_id 0x436 description L1xx high-density flash_type 5 flash_pagesize 100 -sram_size c000 -bootrom_base 1ff00000 -bootrom_size 1000 -option_base 1ff80000 -option_size 8 -flags 2 +sram_size 0xc000 +bootrom_base 0x1ff00000 +bootrom_size 0x1000 +option_base 0x1ff80000 +option_size 0x8 +flags swo diff --git a/config/chips/L1xx_medium-density.chip b/config/chips/L1xx_medium-density.chip index feb53b846..409b4dacc 100644 --- a/config/chips/L1xx_medium-density.chip +++ b/config/chips/L1xx_medium-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for L1xx medium-density # -chip_id 416 +chip_id 0x416 description L1xx medium-density flash_type 5 flash_pagesize 100 -sram_size 4000 -bootrom_base 1ff00000 -bootrom_size 1000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x4000 +bootrom_base 0x1ff00000 +bootrom_size 0x1000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L1xx_medium-plus-density.chip b/config/chips/L1xx_medium-plus-density.chip index bdce4adc2..374f2e914 100644 --- a/config/chips/L1xx_medium-plus-density.chip +++ b/config/chips/L1xx_medium-plus-density.chip @@ -1,13 +1,13 @@ # Chip-ID file for L1xx medium-plus-density # -chip_id 427 +chip_id 0x427 description L1xx medium-plus-density flash_type 5 flash_pagesize 100 -sram_size 8000 -bootrom_base 1ff00000 -bootrom_size 1000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x8000 +bootrom_base 0x1ff00000 +bootrom_size 0x1000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L41x.chip b/config/chips/L41x.chip index a05034af4..cf51b4b02 100644 --- a/config/chips/L41x.chip +++ b/config/chips/L41x.chip @@ -1,13 +1,13 @@ # Chip-ID file for L41x # -chip_id 464 +chip_id 0x464 description L41x flash_type 6 flash_pagesize 800 -sram_size a000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 0 -option_size 0 -flags 2 +sram_size 0xa000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index 4c41ac69b..1953a6a99 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -1,13 +1,13 @@ # Chip-ID file for L43x/L44x # -chip_id 435 +chip_id 0x435 description L43x/L44x flash_type 6 flash_pagesize 800 -sram_size c000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 1fff7800 -option_size 4 -flags 2 +sram_size 0xc000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1fff7800 +option_size 0x4 +flags swo diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index da1594995..79a90fcac 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -1,13 +1,13 @@ # Chip-ID file for L45x/L46x # -chip_id 462 +chip_id 0x462 description L45x/L46x flash_type 6 flash_pagesize 800 -sram_size 20000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x20000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 9bfcdb366..f94c0c582 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -1,13 +1,13 @@ # Chip-ID file for L496x/L4A6x # -chip_id 461 +chip_id 0x461 description L496x/L4A6x flash_type 6 flash_pagesize 800 -sram_size 40000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 1fff7800 -option_size 4 -flags 2 +sram_size 0x40000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1fff7800 +option_size 0x4 +flags swo diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index a9b082128..355f22470 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -1,13 +1,13 @@ # Chip-ID file for L4Rx # -chip_id 470 +chip_id 0x470 description L4Rx flash_type 6 flash_pagesize 1000 -sram_size a0000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 0 -option_size 0 -flags 2 +sram_size 0xa0000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L4xx.chip b/config/chips/L4xx.chip index b66df6b31..3360a446e 100644 --- a/config/chips/L4xx.chip +++ b/config/chips/L4xx.chip @@ -1,13 +1,13 @@ # Chip-ID file for L4xx # -chip_id 415 +chip_id 0x415 description L4xx flash_type 6 flash_pagesize 800 -sram_size 18000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 1fff7800 -option_size 4 -flags 2 +sram_size 0x18000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1fff7800 +option_size 0x4 +flags swo diff --git a/config/chips/WB55.chip b/config/chips/WB55.chip index 4ad4d08d0..9cf1d4380 100644 --- a/config/chips/WB55.chip +++ b/config/chips/WB55.chip @@ -1,13 +1,13 @@ # Chip-ID file for WB55 # -chip_id 495 +chip_id 0x495 description WB55 flash_type 9 flash_pagesize 1000 -sram_size 40000 -bootrom_base 1fff0000 -bootrom_size 7000 -option_base 0 -option_size 0 -flags 2 +sram_size 0x40000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index ea4fe5f02..2235d0072 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -1,13 +1,13 @@ # Chip-ID file for unknown device # -chip_id 0 +chip_id 0x0 description unknown device flash_type 0 flash_pagesize 0 -sram_size 0 -bootrom_base 0 -bootrom_size 0 -option_base 0 -option_size 0 -flags 0 +sram_size 0x0 +bootrom_base 0x0 +bootrom_size 0x0 +option_base 0x0 +option_size 0x0 +flags none diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 1543041c2..772a722aa 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -8,6 +8,13 @@ #include #include +// This is the old chipid "database". +// It is kept here for now to be able to compare the +// result between the "old code" and the "new code". +// For now if you need to change something, please +// change it both here and in the corresponding +// config/chips/*.chip file. + static struct stlink_chipid_params devices[] = { { // RM0410 document was used to find these paramaters @@ -842,16 +849,16 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "# Chip-ID file for %s\n", dev->description); fprintf(fp, "#\n"); - fprintf(fp, "chip_id %x\n", dev->chip_id); + fprintf(fp, "chip_id 0x%x\n", dev->chip_id); fprintf(fp, "description %s\n", dev->description); - fprintf(fp, "flash_type %x\n", dev->flash_type); - fprintf(fp, "flash_pagesize %x\n", dev->flash_pagesize); - fprintf(fp, "sram_size %x\n", dev->sram_size); - fprintf(fp, "bootrom_base %x\n", dev->bootrom_base); - fprintf(fp, "bootrom_size %x\n", dev->bootrom_size); - fprintf(fp, "option_base %x\n", dev->option_base); - fprintf(fp, "option_size %x\n", dev->option_size); - fprintf(fp, "flags %x\n\n", dev->flags); + fprintf(fp, "flash_type %d\n", dev->flash_type); + fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); + fprintf(fp, "sram_size 0x%x\n", dev->sram_size); + fprintf(fp, "bootrom_base 0x%x\n", dev->bootrom_base); + fprintf(fp, "bootrom_size 0x%x\n", dev->bootrom_size); + fprintf(fp, "option_base 0x%x\n", dev->option_base); + fprintf(fp, "option_size 0x%x\n", dev->option_size); + fprintf(fp, "flags %d\n\n", dev->flags); } @@ -883,10 +890,10 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { void process_chipfile(char *fname) { FILE *fp; - char *p, buf[1025]; + char *p, *pp, buf[1025]; char word[64], value[64]; struct stlink_chipid_params *ts; - int nc; + int nc, ival; //fprintf (stderr, "processing chipfile %s.\n", fname); fp = fopen(fname, "r"); @@ -902,30 +909,39 @@ void process_chipfile(char *fname) if (*p == '#') continue; // ignore comments. sscanf(p, "%s %s", word, value); + ival = atoi (value); if (strcmp(word, "chip_id") == 0) { - sscanf(value, "%x", &ts->chip_id); + ts->chip_id = ival; } else if (strcmp (word, "description") == 0) { //ts->description = strdup (value); buf[strlen(p)-1] = 0; // chomp newline sscanf(p, "%*s %n", &nc); ts->description = strdup(p+nc); } else if (strcmp (word, "flash_type") == 0) { - sscanf(value, "%x", &ts->flash_type); + ts->flash_type = ival; } else if (strcmp (word, "flash_size_reg") == 0) { - sscanf(value, "%x", &ts->flash_size_reg); + ts->flash_size_reg = ival; } else if (strcmp (word, "flash_pagesize") == 0) { - sscanf(value, "%x", &ts->flash_pagesize); + ts->flash_pagesize = ival; } else if (strcmp (word, "sram_size") == 0) { - sscanf(value, "%x", &ts->sram_size); + ts->sram_size = ival; } else if (strcmp (word, "bootrom_base") == 0) { - sscanf(value, "%x", &ts->bootrom_base); + ts->bootrom_base = ival; } else if (strcmp (word, "bootrom_size") == 0) { - sscanf(value, "%x", &ts->bootrom_size); + ts->bootrom_size = ival; } else if (strcmp (word, "option_base") == 0) { - sscanf(value, "%x", &ts->option_base); + ts->option_base = ival; } else if (strcmp (word, "option_size") == 0) { - sscanf(value, "%x", &ts->option_size); + ts->option_size = ival; } else if (strcmp (word, "flags") == 0) { + pp = strtok (p, " \t\n"); + while ((pp = strtok (NULL, " \t\n")) ) { + if (strcmp (pp, "none") == 0) ts->flags = 0; // not necessary: calloc did this already. + else if (strcmp (pp, "dualbank") == 0) ts->flags |= CHIP_F_HAS_DUAL_BANK; + else if (strcmp (pp, "swo") == 0) ts->flags |= CHIP_F_HAS_SWO_TRACING; + else fprintf (stderr, "Unknown flags word in %s: '%s'\n", + fname, pp); + } sscanf(value, "%x", &ts->flags); } else { fprintf (stderr, "Unknown keyword in %s: %s\n", From f88509130505748831ded417031a14cd033bdb63 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 24 May 2021 12:13:56 +0200 Subject: [PATCH 1207/1435] General Project Update - Updated CHANGELOG.md - Updated GitHub security policy - [doc] Updated steps for release procedure - [doc] Updated list of supported OS - Removed old clang_analyze script - Minor fix in travis build script --- .travis.sh | 6 +++--- CHANGELOG.md | 1 + SECURITY.md | 3 ++- doc/release.md | 1 + doc/version_support.md | 6 +++--- run_clang_analyze.sh | 9 --------- 6 files changed, 10 insertions(+), 16 deletions(-) delete mode 100755 run_clang_analyze.sh diff --git a/.travis.sh b/.travis.sh index a156db203..d8c5377de 100755 --- a/.travis.sh +++ b/.travis.sh @@ -23,12 +23,12 @@ elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then make && rm -rf build-mingw-32 && cd - elif [ "$TRAVIS_OS_NAME" == "osx" ]; then - echo "--> Building Debug..." + echo "--> make debug..." mkdir -p build/Debug && cd build/Debug cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && cd - + make debug && cd - - echo "--> Building Release with package..." + echo "--> make package..." mkdir -p build/Release && cd build/Release cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR make package && cd - diff --git a/CHANGELOG.md b/CHANGELOG.md index 57ed15e98..b711f3890 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -17,6 +17,7 @@ Updates & changes: - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation ([#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) +- Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) diff --git a/SECURITY.md b/SECURITY.md index caa2740db..9ace47066 100644 --- a/SECURITY.md +++ b/SECURITY.md @@ -7,7 +7,8 @@ The following versions of the stlink toolset are currently being supported.
      +On Windows users should ensure that cmake 3.20.2 or any later version is installed.
      Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb` (1.0.23 at the time of writing). - Windows 10 @@ -14,8 +14,8 @@ Up on compiling c-make will **automatically** download and install the latest co | Package Repository | libusb
      version | cmake
      version | gtk-3
      version | Supported macOS versions | | ------------------ | ------------------- | ------------------ | ------------------ | ------------------------ | -| homebrew | 1.0.23 | 3.17.0 | 3.24.18
      gtk+3 | 10.9 - 11.x | -| MacPorts | 1.0.23 | 3.17.0 | 3.24.18
      gtk3 | 10.4 - 11.x | +| homebrew | 1.0.24 | 3.20.2 | 3.24.29
      gtk+3 | 10.9 - 11.x | +| MacPorts | 1.0.24 | 3.20.2 | 3.24.29
      gtk3 | 10.4 - 11.x | NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 are required. diff --git a/run_clang_analyze.sh b/run_clang_analyze.sh deleted file mode 100755 index fd1b78b55..000000000 --- a/run_clang_analyze.sh +++ /dev/null @@ -1,9 +0,0 @@ -#!/bin/bash -# Run this hacky script in project root directory to start clang static analysis. -# Adjust ccc-analyzer path if necessary - -CCC_ANALYZER=/usr/share/clang/scan-build-3.5/ccc-analyzer -mkdir -p build-clang-analyze/reports -cd build-clang-analyze -cmake -DCMAKE_C_COMPILER=${CCC_ANALYZER} $* .. -scan-build -o ./reports --keep-empty make From 9eb81e1e0adc6a5bf7a1c68cbbaf3fd35ec85be0 Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 24 May 2021 21:35:02 +0500 Subject: [PATCH 1208/1435] Expanded and revised list of chips --- src/stlink-lib/chipid.c | 326 +++++++++++++++++++++++++--------------- src/stlink-lib/chipid.h | 18 ++- 2 files changed, 213 insertions(+), 131 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 711bf24b0..283f6faec 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -3,26 +3,28 @@ static const struct stlink_chipid_params devices[] = { { - // RM0410 document was used to find these paramaters + // STM32F76x/F77x + // RM0410 .chip_id = STLINK_CHIPID_STM32_F7XXXX, - .description = "F76xxx", + .description = "F76x/F77x", .flash_type = STLINK_FLASH_TYPE_F7, .flash_size_reg = 0x1ff0f442, // section 45.2 .flash_pagesize = 0x800, // No flash pages .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, // ! "System memory" starting address from - .bootrom_size = 0xEDC0, // ! @todo "System memory" byte size in hex from + .bootrom_base = 0x00200000, // "System memory" starting address from + .bootrom_size = 0xEDC0, .option_base = STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option // bytes, writing uses FLASH_F7_OPTCR // and FLASH_F7_OPTCR1 .option_size = 0x20, - .flags = CHIP_F_HAS_SWO_TRACING, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // RM0385 and DS10916 document was used to find these paramaters + // STM32F74x/F75x + // RM0385, DS10916 .chip_id = STLINK_CHIPID_STM32_F7, - .description = "F7xx", + .description = "F74x/F75x", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1ff0f442, // section 41.2 .flash_pagesize = 0x800, // No flash pages @@ -34,7 +36,8 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // RM0431 and DS document was used to find these paramaters + // STM32F72x/F73x + // RM0431 .chip_id = STLINK_CHIPID_STM32_F72XXX, .description = "F72x/F73x", .flash_type = STLINK_FLASH_TYPE_F4, @@ -48,25 +51,27 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // table 2, PM0063 + // STM32F1xx medium-density devices + // RM0008 .chip_id = STLINK_CHIPID_STM32_F1_MEDIUM, - .description = "F1xx Medium-density", + .description = "F1xx MD", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, .sram_size = 0x5000, - .bootrom_base = 0x1ffff000, + .bootrom_base = 0x1ffff000, // 2.3.3 "Embedded Flash memory" .bootrom_size = 0x800, .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // table 1, PM0059 + // STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx + // RM0033 (rev 5) .chip_id = STLINK_CHIPID_STM32_F2, .description = "F2xx", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, // as in RM0033 Rev 5 + .flash_size_reg = 0x1fff7a22, .flash_pagesize = 0x20000, .sram_size = 0x20000, .bootrom_base = 0x1fff0000, @@ -76,9 +81,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // PM0063 + // STM32F1xx low-density devices + // RM0008 .chip_id = STLINK_CHIPID_STM32_F1_LOW, - .description = "F1 Low-density device", + .description = "F1xx LD", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, @@ -90,10 +96,12 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F4x5/F4x7 + // RM0090 (rev 2) .chip_id = STLINK_CHIPID_STM32_F4, - .description = "F4xx", + .description = "F4x5/F4x7", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x30000, .bootrom_base = 0x1fff0000, @@ -103,10 +111,12 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F46x/F47x + // RM0090 (rev 2) .chip_id = STLINK_CHIPID_STM32_F4_DSI, .description = "F46x/F47x", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x40000, .bootrom_base = 0x1fff0000, @@ -114,10 +124,12 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F42x/F43x + // RM0090 (rev 2) .chip_id = STLINK_CHIPID_STM32_F4_HD, .description = "F42x/F43x", .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // As in rm0090 since Rev 2 + .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x40000, .bootrom_base = 0x1fff0000, @@ -126,7 +138,7 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_F4_LP, - .description = "F4xx (low power)", + .description = "F401xB/C", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, @@ -137,20 +149,18 @@ static const struct stlink_chipid_params devices[] = { }, { .chip_id = STLINK_CHIPID_STM32_F411XX, - .description = "STM32F411xC/E", + .description = "F411xC/E", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, .sram_size = 0x20000, .bootrom_base = 0x1fff0000, .bootrom_size = 0x7800, - .option_base = STM32_F4_OPTION_BYTES_BASE, - .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { .chip_id = STLINK_CHIPID_STM32_F4_DE, - .description = "F4xx (Dynamic Efficency)", + .description = "F401xD/E", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, .flash_pagesize = 0x4000, @@ -160,8 +170,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F1xx high-density devices + // RM0008 .chip_id = STLINK_CHIPID_STM32_F1_HIGH, - .description = "F1xx High-density", + .description = "F1xx HD", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -173,47 +185,53 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // This ignores the EEPROM! (and uses the page erase size, - // not the sector write protection...) + // STM32L100/L15x/L16x Cat.1 + // RM0038 .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM, - .description = "L1xx Medium-density", + .description = "L1xx Cat.1", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, .flash_pagesize = 0x100, - .sram_size = 0x4000, + .sram_size = 0x4000, // up to 16k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32L100/L15x/L16x Cat.2 + // RM0038 .chip_id = STLINK_CHIPID_STM32_L1_CAT2, .description = "L1xx Cat.2", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8004c, .flash_pagesize = 0x100, - .sram_size = 0x8000, + .sram_size = 0x8000, // up to 32k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32L100/L15x/L16x Cat.3 + // RM0038 .chip_id = STLINK_CHIPID_STM32_L1_MEDIUM_PLUS, - .description = "L1xx Medium-Plus-density", + .description = "L1xx Cat.3", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, - .sram_size = 0x8000, // not completely clear if there are some with 48k + .sram_size = 0x8000, // up to 32k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32L100/L15x/L16x Cat.4 + // RM0038 .chip_id = STLINK_CHIPID_STM32_L1_HIGH, - .description = "L1xx High-density", + .description = "L1xx Cat.4", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, - .sram_size = 0xC000, // not completely clear if there are some with 32k + .sram_size = 0xC000, // up to 48k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, .option_base = STM32_L1_OPTION_BYTES_BASE, @@ -221,19 +239,23 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32L100/L15x/L16x Cat.5 + // RM0038 .chip_id = STLINK_CHIPID_STM32_L152_RE, - .description = "L152RE", + .description = "L1xx Cat.5", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff800cc, .flash_pagesize = 0x100, - .sram_size = 0x14000, // not completely clear if there are some with 32k + .sram_size = 0x14000, // up to 80k .bootrom_base = 0x1ff00000, .bootrom_size = 0x1000, .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F1xx connectivity devices + // RM0008 .chip_id = STLINK_CHIPID_STM32_F1_CONN, - .description = "F1 Connectivity line", + .description = "F1xx CL", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -245,9 +267,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // Low and Medium density VL have same chipid. RM0041 25.6.1 + // STM32F1xx low- and medium-density value line devices + // RM0041 .chip_id = STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW, - .description = "F1xx Value Line", + .description = "F1xx VL", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x400, @@ -259,7 +282,8 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F446x family. Support based on DM00135183.pdf (RM0390) document. + // STM32F446x family + // RM0390 .chip_id = STLINK_CHIPID_STM32_F446, .description = "F446", .flash_type = STLINK_FLASH_TYPE_F4, @@ -273,7 +297,8 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F410 MCUs. Support based on DM00180366.pdf (RM0401) document. + // STM32F410 + // RM0401 .chip_id = STLINK_CHIPID_STM32_F410, .description = "F410", .flash_type = STLINK_FLASH_TYPE_F4, @@ -285,10 +310,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // This is STK32F303VCT6 device from STM32 F3 Discovery board. - // Support based on DM00043574.pdf (RM0316) document. + // STM32F303xB/C, STM32F358, STM32F302xBxC + // RM0316, RM0365 .chip_id = STLINK_CHIPID_STM32_F3, - .description = "F3xx", + .description = "F302/F303/F358", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, @@ -300,10 +325,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // This is STK32F373VCT6 device from STM32 F373 eval board - // Support based on 303 above (37x and 30x have same memory map) + // STM32F373Cx/Rx/Vx, STM32F378Cx/Rx/Vx + // RM0313 .chip_id = STLINK_CHIPID_STM32_F37x, - .description = "F3xx", + .description = "F37x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, @@ -315,8 +340,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F1xx high-density value line devices + // RM0041 .chip_id = STLINK_CHIPID_STM32_F1_VL_HIGH, - .description = "F1xx High-density value line", + .description = "F1xx HD VL", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -328,8 +355,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F1xx XL-density devices + // RM0008 .chip_id = STLINK_CHIPID_STM32_F1_XL, - .description = "F1xx XL-density", + .description = "F1xx XL", .flash_type = STLINK_FLASH_TYPE_F1_XL, .flash_size_reg = 0x1ffff7e0, .flash_pagesize = 0x800, @@ -339,8 +368,8 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // Use this as an example for mapping future chips: - // RM0091 document was used to find these paramaters + // STM32F07x + // RM0091 .chip_id = STLINK_CHIPID_STM32_F0_CAN, .description = "F07x", .flash_type = STLINK_FLASH_TYPE_F0, @@ -354,8 +383,8 @@ static const struct stlink_chipid_params devices[] = { .option_size = 16, }, { - // Use this as an example for mapping future chips: - // RM0091 document was used to find these paramaters + // STM32F05x + // RM0091 .chip_id = STLINK_CHIPID_STM32_F0, .description = "F05x", .flash_type = STLINK_FLASH_TYPE_F0, @@ -369,8 +398,8 @@ static const struct stlink_chipid_params devices[] = { .option_size = 16, }, { - // RM0402 document was used to find these parameters - // Table 4. + // STM32F412 + // RM0402 .chip_id = STLINK_CHIPID_STM32_F412, .description = "F412", .flash_type = STLINK_FLASH_TYPE_F4, @@ -383,10 +412,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // RM0430 DocID029473 Rev 2 document was used to find these parameters - // Figure 2, Table 4, Table 5, Section 35.2 + // STM32F413/F423 + // RM0430 (rev 2) .chip_id = STLINK_CHIPID_STM32_F413, - .description = "F413", + .description = "F413/F423", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 .flash_pagesize = @@ -400,8 +429,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { + // STM32F09x + // RM0091 .chip_id = STLINK_CHIPID_STM32_F09X, - .description = "F09X", + .description = "F09x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) @@ -413,8 +444,8 @@ static const struct stlink_chipid_params devices[] = { .option_size = 16, }, { - // Use this as an example for mapping future chips: - // RM0091 document was used to find these paramaters + // STM32F04x + // RM0091 .chip_id = STLINK_CHIPID_STM32_F04, .description = "F04x", .flash_type = STLINK_FLASH_TYPE_F0, @@ -428,8 +459,8 @@ static const struct stlink_chipid_params devices[] = { .option_size = 16, }, { - // Use this as an example for mapping future chips: - // RM0091 document was used to find these paramaters + // STM32F03x + // RM0091 .chip_id = STLINK_CHIPID_STM32_F0_SMALL, .description = "F03x", .flash_type = STLINK_FLASH_TYPE_F0, @@ -443,9 +474,10 @@ static const struct stlink_chipid_params devices[] = { .option_size = 16, }, { - // STM32F30x + // STM32F301x6/8, STM32F318x8, STM32F302x6x8 + // RM0366, RM0365 .chip_id = STLINK_CHIPID_STM32_F3_SMALL, - .description = "F3xx small", + .description = "F301/F302/F318", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, @@ -457,10 +489,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L0x - // RM0367,RM0377 documents was used to find these parameters + // STM32L0xx Category 3 + // RM0367, RM0377, RM0451 .chip_id = STLINK_CHIPID_STM32_L0, - .description = "L0x3", + .description = "L0xx Cat.3", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, @@ -472,9 +504,9 @@ static const struct stlink_chipid_params devices[] = { }, { // STM32L0x Category 5 - // RM0367,RM0377 documents was used to find these parameters + // RM0367, RM0377, RM0451 .chip_id = STLINK_CHIPID_STM32_L0_CAT5, - .description = "L0xx Category 5", + .description = "L0xx Cat.5", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, @@ -483,12 +515,13 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x2000, .option_base = STM32_L0_OPTION_BYTES_BASE, .option_size = 20, + .flags = CHIP_F_HAS_DUAL_BANK, }, { // STM32L0x Category 2 - // RM0367,RM0377 documents was used to find these parameters + // RM0367, RM0377 .chip_id = STLINK_CHIPID_STM32_L0_CAT2, - .description = "L0xx Category 2", + .description = "L0xx Cat.2", .flash_type = STLINK_FLASH_TYPE_L0, .flash_size_reg = 0x1ff8007c, .flash_pagesize = 0x80, @@ -499,10 +532,10 @@ static const struct stlink_chipid_params devices[] = { .option_size = 20, }, { - // STM32F334, STM32F303x6/8, and STM32F328 - // From RM0364 and RM0316 + // STM32F334, STM32F303x6/8, STM32F328 + // RM0364, RM0316 .chip_id = STLINK_CHIPID_STM32_F334, - .description = "F334 medium density", // (RM0316 sec 33.6.1) + .description = "F303/F328/F334", // (RM0316 sec 33.6.1) .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, .flash_pagesize = 0x800, @@ -514,10 +547,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // This is STK32F303RET6 device from STM32 F3 Nucelo board. - // Support based on DM00043574.pdf (RM0316) document rev 5. + // STM32F303xD/E, STM32F398xE, STM32F302xD/E + // RM0316 (rev 5), RM0365 .chip_id = STLINK_CHIPID_STM32_F303_HIGH, - .description = "F303 high density", + .description = "F302/F303/F398", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register .flash_pagesize = 0x800, // 4.2.1 Flash memory organization @@ -529,10 +562,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L4x6 - // From RM0351. + // STM32L47x/L48x + // RM0351 .chip_id = STLINK_CHIPID_STM32_L4, - .description = "L4xx", + .description = "L47x/L48x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) @@ -552,24 +585,41 @@ static const struct stlink_chipid_params devices[] = { }, { // STM32L4RX - // From DM00310109.pdf + // RM0432 .chip_id = STLINK_CHIPID_STM32_L4RX, - .description = "L4Rx", + .description = "L4Rx/L4Sx", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = - 0x1fff75e0, // "Flash size data register" (sec 52.2, page 2049) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 97 + 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + //TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 99 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 99) - .flags = CHIP_F_HAS_SWO_TRACING, + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L4PX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4PX, + .description = "L4Px", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = + 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + //TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = + 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { // STLINK_CHIPID_STM32_L41X - // From RM0394 Rev 4 and DS12469 Rev 5 + // RM0394 (rev 4), DS12469 (rev 5) .chip_id = STLINK_CHIPID_STM32_L41X, - .description = "L41x", + .description = "L41x/L42x", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, // sec 47.2, page 1586) @@ -585,7 +635,7 @@ static const struct stlink_chipid_params devices[] = { }, { // STLINK_CHIPID_STM32_L43X - // From RM0392. + // RM0392 .chip_id = STLINK_CHIPID_STM32_L43X, .description = "L43x/L44x", .flash_type = STLINK_FLASH_TYPE_L4, @@ -607,9 +657,9 @@ static const struct stlink_chipid_params devices[] = { }, { // STLINK_CHIPID_STM32_L496X - // Support based on en.DM00083560.pdf (RM0351) document rev 5. + // RM0351 (rev 5) .chip_id = STLINK_CHIPID_STM32_L496X, - .description = "L496x/L4A6x", + .description = "L49x/L4Ax", .flash_type = STLINK_FLASH_TYPE_L4, .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) @@ -626,7 +676,7 @@ static const struct stlink_chipid_params devices[] = { }, { // STLINK_CHIPID_STM32_L46X - // From RM0394 (updated version of RM0392?). + // RM0394 (updated version of RM0392?) .chip_id = STLINK_CHIPID_STM32_L46X, .description = "L45x/46x", .flash_type = STLINK_FLASH_TYPE_L4, @@ -645,7 +695,8 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L011 + // STM32L0xx Category 1 + // RM0451, RM0377 .chip_id = STLINK_CHIPID_STM32_L011, .description = "L01x/L02x", .flash_type = STLINK_FLASH_TYPE_L0, @@ -656,61 +707,67 @@ static const struct stlink_chipid_params devices[] = { .bootrom_size = 0x2000, }, { - // STM32G030/031/041 (from RM0454 & RM0444) + // STM32G030/031/041 + // RM0454, RM0444 .chip_id = STLINK_CHIPID_STM32_G0_CAT1, - .description = "G030/G031/G041", + .description = "G03x/G04x", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2k (sec 3.2) .sram_size = 0x2000, // 8k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 5 on RM0444 & table 4 on RM0454) + .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, }, { - // STM32G070/071/081 (from RM0454 & RM0444) + // STM32G071/081 + // RM0444 .chip_id = STLINK_CHIPID_STM32_G0_CAT2, - .description = "G070/G071/G081", + .description = "G07x/G08x", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2k (sec 3.2) .sram_size = 0x9000, // 36k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 3 on RM0444 & table 3 on RM0454) + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, - }, + }, { - // STM32G0B0/0B1/0C1 (from RM0454 & RM0444) + // STM32G0B1/G0C1 + // RM0444 .chip_id = STLINK_CHIPID_STM32_G0_CAT3, - .description = "G0B0/G0B1/G0C1", + .description = "G0Bx/G0Cx", .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x24000, // 144k (sec 2.3) + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x9000, // 36k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2 on RM0444 & table 2 on RM0454) + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_DUAL_BANK, }, { - // STM32G050/051/061 (from RM0454 & RM0444) + // STM32G051/G061 + // RM0444 .chip_id = STLINK_CHIPID_STM32_G0_CAT4, - .description = "G050/G051/G061", + .description = "G05x/G06x", .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x4800, // 18k (sec 2.3) + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x9000, // 36k (sec 2.3) .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 4 on RM0444 & table 4 on RM0454) + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, }, { - // STM32G431/441 (from RM0440) + // STM32G431/441 + // RM0440 .chip_id = STLINK_CHIPID_STM32_G4_CAT2, - .description = "G4 Category-2", + .description = "G43x/G44x", .flash_type = STLINK_FLASH_TYPE_G4, .flash_size_reg = 0x1FFF75E0, // Section 47.2 .flash_pagesize = @@ -726,9 +783,10 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32G471/473/474/483/484 (from RM0440) + // STM32G471/473/474/483/484 + // RM0440 .chip_id = STLINK_CHIPID_STM32_G4_CAT3, - .description = "G4 Category-3", + .description = "G47x/G48x", .flash_type = STLINK_FLASH_TYPE_G4, .flash_size_reg = 0x1FFF75E0, // Section 47.2 .flash_pagesize = @@ -736,7 +794,7 @@ static const struct stlink_chipid_params devices[] = { // SRAM1 is 80k at 0x20000000 // SRAM2 is 16k at 0x20014000 // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x18000, // 128k (sec 2.4) + .sram_size = 0x20000, // 128k (sec 2.4) .bootrom_base = 0x1fff0000, .bootrom_size = 0x7000, // 28k (table 2) .option_base = STM32_G4_OPTION_BYTES_BASE, @@ -744,9 +802,29 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // STM32WB55 (from RM0434) + // STM32G491/G4A1 + // RM0440 + .chip_id = STLINK_CHIPID_STM32_G4_CAT4, + .description = "G49x/G4Ax", + .flash_type = STLINK_FLASH_TYPE_G4, + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = + 0x800, // 2k (sec 3.3.1) + // SRAM1 is 80k at 0x20000000 + // SRAM2 is 16k at 0x20014000 + // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x1C000, // 112k (sec 2.4) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32WB55xx, STM32WB35xx, STM32WB50CG/30CE + // RM0434, RM0471 .chip_id = STLINK_CHIPID_STM32_WB55, - .description = "WB55", + .description = "WB5x/3x", .flash_type = STLINK_FLASH_TYPE_WB, .flash_size_reg = 0x1FFF75E0, .flash_pagesize = 0x1000, // 4k @@ -772,7 +850,8 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // STM32H7A3/7B3 (from RM0455) + // STM32H7A3/7B3 + // RM0455 .chip_id = STLINK_CHIPID_STM32_H7AX, .description = "H7Ax/H7Bx", .flash_type = STLINK_FLASH_TYPE_H7, @@ -788,7 +867,8 @@ static const struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // STM32H72x/H73x (from RM0468) + // STM32H72x/H73x + // RM0468 .chip_id = STLINK_CHIPID_STM32_H72X, .description = "H72x/H73x", .flash_type = STLINK_FLASH_TYPE_H7, diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 16a6a5797..b240ecf72 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -37,9 +37,6 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F4_DE = 0x433, STLINK_CHIPID_STM32_F4_DSI = 0x434, STLINK_CHIPID_STM32_L43X = 0x435, /* covers STM32L43xxx and STM32L44xxx devices */ - STLINK_CHIPID_STM32_L496X = 0x461, /* covers STM32L496xx and STM32L4A6xx devices */ - STLINK_CHIPID_STM32_L46X = 0x462, /* covers STM32L45xxx and STM32L46xxx devices */ - STLINK_CHIPID_STM32_L41X = 0x464, /* covers STM32L41xxx and STM32L42xxx devices */ STLINK_CHIPID_STM32_L1_HIGH = 0x436, /* assigned to some L1 "Medium-Plus" and "High" chips */ STLINK_CHIPID_STM32_L152_RE = 0x437, STLINK_CHIPID_STM32_F334 = 0x438, @@ -52,20 +49,25 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F303_HIGH = 0x446, STLINK_CHIPID_STM32_L0_CAT5 = 0x447, STLINK_CHIPID_STM32_F0_CAN = 0x448, - STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the NucleoF746ZG board */ + STLINK_CHIPID_STM32_F7 = 0x449, STLINK_CHIPID_STM32_H74XXX = 0x450, /* Found on page 3189 in the RM0433*/ STLINK_CHIPID_STM32_F7XXXX = 0x451, - STLINK_CHIPID_STM32_F72XXX = 0x452, /* ID found on the NucleoF722ZE board */ - STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G050/G051/G061 found on RM0444/RM0454 */ + STLINK_CHIPID_STM32_F72XXX = 0x452, + STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */ STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ + STLINK_CHIPID_STM32_L496X = 0x461, /* covers STM32L496xx and STM32L4A6xx devices */ + STLINK_CHIPID_STM32_L46X = 0x462, /* covers STM32L45xxx and STM32L46xxx devices */ STLINK_CHIPID_STM32_F413 = 0x463, + STLINK_CHIPID_STM32_L41X = 0x464, /* covers STM32L41xxx and STM32L42xxx devices */ STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ - STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B0/G0B1/G0C1 found on RM0444/RM0454 */ + STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */ STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* See: RM 0440 s46.6.1 "MCU device ID code" */ STLINK_CHIPID_STM32_G4_CAT3 = 0x469, - STLINK_CHIPID_STM32_L4RX = 0x470, /* ID found on the STM32L4R9I-DISCO board */ + STLINK_CHIPID_STM32_L4RX = 0x470, /* RM0432, p. 2247 */ + STLINK_CHIPID_STM32_L4PX = 0x471, /* RM0432, p. 2247 */ + STLINK_CHIPID_STM32_G4_CAT4 = 0x479, STLINK_CHIPID_STM32_H7AX = 0x480, /* RM0455, p. 2863 */ STLINK_CHIPID_STM32_H72X = 0x483, /* RM0468, p. 3199 */ STLINK_CHIPID_STM32_WB55 = 0x495 From b93f8b220467247af799f6c094cc08972422ae3d Mon Sep 17 00:00:00 2001 From: anton Date: Mon, 24 May 2021 23:10:26 +0500 Subject: [PATCH 1209/1435] Added half page write fallback for stm32L0/L1 --- src/common.c | 55 ++++++++++++++++++++++++++------------------ src/stlink-lib/usb.c | 6 +++++ 2 files changed, 38 insertions(+), 23 deletions(-) diff --git a/src/common.c b/src/common.c index 6333ff408..2d200ba27 100644 --- a/src/common.c +++ b/src/common.c @@ -1994,13 +1994,6 @@ int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem8 ***\n"); - - if (len > 0x40) { // !!! never ever: Writing more then 0x40 bytes gives - // unexpected behaviour - ELOG("Data length > 64: +%d byte.\n", len); - return (-1); - } - return (sl->backend->write_mem8(sl, addr, len)); } @@ -3080,11 +3073,13 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize) { - unsigned int count; + unsigned int count, size; unsigned int num_half_pages = len / pagesize; uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); flash_loader_t fl; + bool use_loader = false; + int ret = 0; ILOG("Starting Half page flash write for STM32L core id\n"); @@ -3105,17 +3100,34 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, wait_flash_busy(sl); for (count = 0; count < num_half_pages; count++) { - if (stlink_flash_loader_run(sl, &fl, addr + count * pagesize, - base + count * pagesize, pagesize) == -1) { + if (use_loader) { + ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, + base + count * pagesize, pagesize); + if (ret && count == 0) { + /* It seems that stm32lx devices have a problem when it is blank */ + WLOG("Failed to use flash loader, fallback to soft write\n"); + use_loader = false; + } + } + if (!use_loader) { + if ((pagesize%64) != 0) { + ELOG("Page size not supported\n"); + break; + } + ret = 0; + for (size = 0; size < pagesize && !ret; size += 64) + { + memcpy(sl->q_buf, base + count * pagesize + size, 64); + ret = stlink_write_mem8(sl, addr + count * pagesize + size, 64); + } + } + + if (ret) { WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", addr + count * pagesize); - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return (-1); + break; } - // wait for sr.busy to be cleared if (sl->verbose >= 1) { // show progress; writing procedure is slow and previous errors are // misleading @@ -3123,16 +3135,14 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, fflush(stdout); } + // wait for sr.busy to be cleared wait_flash_busy(sl); } stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~(1 << FLASH_L1_PROG); + val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~(1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return (0); + return (ret); } int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { @@ -3341,9 +3351,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, off = 0; if (len > pagesize) { - if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) { - // this may happen on a blank device! - WLOG("\nwrite_half_pages failed == -1\n"); + if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { + return (-1); } else { off = (size_t)(len / pagesize) * pagesize; } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index a58681702..1d50bb202 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -328,6 +328,12 @@ int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { unsigned char* const cmd = sl->c_buf; int i, ret; + if ((sl->version.jtag_api < STLINK_JTAG_API_V3 && len > 64) || + (sl->version.jtag_api >= STLINK_JTAG_API_V3 && len > 512)) { + ELOG("WRITEMEM_32BIT: bulk packet limits exceeded (data len %d byte)\n", len); + return (-1); + } + i = fill_command(sl, SG_DXFER_TO_DEV, 0); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_WRITEMEM_8BIT; From 293db13e1daa2c77295a3460a0d46d0ffbd7c82b Mon Sep 17 00:00:00 2001 From: anton Date: Tue, 25 May 2021 22:25:29 +0500 Subject: [PATCH 1210/1435] Changed the half page write fallback to 32 bit write mode --- src/common.c | 36 ++++++++++++++++-------------------- 1 file changed, 16 insertions(+), 20 deletions(-) diff --git a/src/common.c b/src/common.c index 2d200ba27..d2387d08b 100644 --- a/src/common.c +++ b/src/common.c @@ -3073,27 +3073,18 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize) { - unsigned int count, size; + unsigned int count, off; unsigned int num_half_pages = len / pagesize; - uint32_t val; + uint32_t val, data; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); flash_loader_t fl; - bool use_loader = false; + bool use_loader = true; int ret = 0; - ILOG("Starting Half page flash write for STM32L core id\n"); - - /* Flash loader initialisation */ - if (stlink_flash_loader_init(sl, &fl) == -1) { - WLOG("stlink_flash_loader_init() == -1\n"); - return (-1); - } - - // unlock already done + // enable half page write stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << FLASH_L1_FPRG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - val |= (1 << FLASH_L1_PROG); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); @@ -3110,15 +3101,11 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } } if (!use_loader) { - if ((pagesize%64) != 0) { - ELOG("Page size not supported\n"); - break; - } ret = 0; - for (size = 0; size < pagesize && !ret; size += 64) + for (off = 0; off < pagesize && !ret; off += 4) { - memcpy(sl->q_buf, base + count * pagesize + size, 64); - ret = stlink_write_mem8(sl, addr + count * pagesize + size, 64); + write_uint32((unsigned char *)&data, *(uint32_t *)(base + count * pagesize + off)); + ret = stlink_write_debug32(sl, addr + count * pagesize + off, data); } } @@ -3139,6 +3126,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, wait_flash_busy(sl); } + // disable half page write stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); @@ -3246,6 +3234,12 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { ELOG("pecr.prglock not clear\n"); return (-1); } + + /* Flash loader initialisation */ + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); @@ -3348,6 +3342,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, pagesize = L1_WRITE_BLOCK_SIZE; } + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + off = 0; if (len > pagesize) { From 9acf539c70e35643be2dc63b0789ff86d878615a Mon Sep 17 00:00:00 2001 From: anton Date: Wed, 26 May 2021 23:04:39 +0500 Subject: [PATCH 1211/1435] Optimizing the half page write fallback --- src/common.c | 23 ++++++++++++----------- src/stlink-lib/flash_loader.c | 10 +++++++--- src/stlink-lib/usb.c | 32 +++++++++++++++++++------------- 3 files changed, 38 insertions(+), 27 deletions(-) diff --git a/src/common.c b/src/common.c index d2387d08b..6d81bf743 100644 --- a/src/common.c +++ b/src/common.c @@ -2636,20 +2636,21 @@ int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, size_t size) { // write the buffer right after the loader + int ret = 0; size_t chunk = size & ~0x3; size_t rem = size & 0x3; if (chunk) { memcpy(sl->q_buf, buf, chunk); - stlink_write_mem32(sl, fl->buf_addr, chunk); + ret = stlink_write_mem32(sl, fl->buf_addr, chunk); } - if (rem) { + if (rem && !ret) { memcpy(sl->q_buf, buf + chunk, rem); - stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, rem); + ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, rem); } - return (0); + return (ret); } uint32_t calculate_F4_sectornum(uint32_t flashaddr) { @@ -3075,7 +3076,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize) { unsigned int count, off; unsigned int num_half_pages = len / pagesize; - uint32_t val, data; + uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); flash_loader_t fl; bool use_loader = true; @@ -3102,10 +3103,10 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } if (!use_loader) { ret = 0; - for (off = 0; off < pagesize && !ret; off += 4) - { - write_uint32((unsigned char *)&data, *(uint32_t *)(base + count * pagesize + off)); - ret = stlink_write_debug32(sl, addr + count * pagesize + off, data); + for (off = 0; off < pagesize && !ret; off += 64) { + size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; + memcpy(sl->q_buf, base + count * pagesize + off, chunk); + ret = stlink_write_mem32(sl, addr + count * pagesize + off, chunk); } } @@ -3237,8 +3238,8 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { /* Flash loader initialisation */ if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return (-1); + // L0/L1 have fallback to soft write + WLOG("stlink_flash_loader_init() == -1\n"); } } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index d492716db..355223146 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -14,7 +14,13 @@ #define STM32F0_WDG_KR_KEY_RELOAD 0xAAAA -/* DO NOT MODIFY SOURCECODE DIRECTLY, EDIT ASSEMBLY FILES INSTEAD */ +/* !!! + * !!! DO NOT MODIFY FLASH LOADERS DIRECTLY! + * !!! + * + * Edit assembly files in the '/flashloaders' instead. The sizes of binary + * flash loaders must be aligned by 4 (it's written by stlink_write_mem32) + */ /* flashloaders/stm32f0.s -- compiled with thumb2 */ static const uint8_t loader_code_stm32vl[] = { @@ -322,9 +328,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); - // TODO: This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { - // IMPOSSIBLE! ELOG("write_buffer_to_sram() == -1\n"); return(-1); } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 1d50bb202..5e5f042d5 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -122,16 +122,16 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, retry++; continue; } - WLOG("%s wait error (0x%02X)\n", cmd, rxbuf[0]); + DLOG("%s wait error (0x%02X)\n", cmd, rxbuf[0]); break; - case STLINK_DEBUG_ERR_FAULT: WLOG("%s response fault\n", cmd); break; - case STLINK_DEBUG_ERR_AP_FAULT: WLOG("%s access port fault\n", cmd); break; - case STLINK_DEBUG_ERR_DP_FAULT: WLOG("%s debug port fault\n", cmd); break; - case STLINK_DEBUG_ERR_AP_ERROR: WLOG("%s access port error\n", cmd); break; - case STLINK_DEBUG_ERR_DP_ERROR: WLOG("%s debug port error\n", cmd); break; - case STLINK_DEBUG_ERR_WRITE_VERIFY: WLOG("%s verification error\n", cmd); break; - case STLINK_DEBUG_ERR_WRITE: WLOG("%s write error\n", cmd); break; - default: WLOG("%s error (0x%02X)\n", cmd, rxbuf[0]); break; + case STLINK_DEBUG_ERR_FAULT: DLOG("%s response fault\n", cmd); break; + case STLINK_DEBUG_ERR_AP_FAULT: DLOG("%s access port fault\n", cmd); break; + case STLINK_DEBUG_ERR_DP_FAULT: DLOG("%s debug port fault\n", cmd); break; + case STLINK_DEBUG_ERR_AP_ERROR: DLOG("%s access port error\n", cmd); break; + case STLINK_DEBUG_ERR_DP_ERROR: DLOG("%s debug port error\n", cmd); break; + case STLINK_DEBUG_ERR_WRITE_VERIFY: DLOG("%s verification error\n", cmd); break; + case STLINK_DEBUG_ERR_WRITE: DLOG("%s write error\n", cmd); break; + default: DLOG("%s error (0x%02X)\n", cmd, rxbuf[0]); break; } return(-1); @@ -149,7 +149,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); if (t) { - ELOG("stlink: %s read storage failed: %s\n", cmd, libusb_error_name(t)); + ELOG("%s read storage failed: %s\n", cmd, libusb_error_name(t)); return(-1); } @@ -306,6 +306,12 @@ int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { unsigned char* const cmd = sl->c_buf; int i, ret; + if ((sl->version.jtag_api < STLINK_JTAG_API_V3 && len > 64) || + (sl->version.jtag_api >= STLINK_JTAG_API_V3 && len > 512)) { + ELOG("WRITEMEM_32BIT: bulk packet limits exceeded (data len %d byte)\n", len); + return (-1); + } + i = fill_command(sl, SG_DXFER_TO_DEV, len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_WRITEMEM_32BIT; @@ -330,7 +336,7 @@ int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { if ((sl->version.jtag_api < STLINK_JTAG_API_V3 && len > 64) || (sl->version.jtag_api >= STLINK_JTAG_API_V3 && len > 512)) { - ELOG("WRITEMEM_32BIT: bulk packet limits exceeded (data len %d byte)\n", len); + ELOG("WRITEMEM_8BIT: bulk packet limits exceeded (data len %d byte)\n", len); return (-1); } @@ -339,11 +345,11 @@ int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { cmd[i++] = STLINK_DEBUG_WRITEMEM_8BIT; write_uint32(&cmd[i], addr); write_uint16(&cmd[i + 4], len); - ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_32BIT"); + ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_8BIT"); if (ret == -1) { return(ret); } - ret = send_only(slu, 1, data, len, "WRITEMEM_32BIT"); + ret = send_only(slu, 1, data, len, "WRITEMEM_8BIT"); if (ret == -1) { return(ret); } From 1d35f95ae088472aad3d246800da34b01a7ed720 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 26 May 2021 23:16:59 +0200 Subject: [PATCH 1212/1435] Updated chip-id descriptions --- src/stlink-lib/chipid.h | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f1342dd61..75288093a 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -49,23 +49,25 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_F303_HD = 0x446, /* high density */ STLINK_CHIPID_STM32_L0_CAT5 = 0x447, STLINK_CHIPID_STM32_F0_CAN = 0x448, - STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the NucleoF746ZG board */ + STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the Nucleo F746ZG board */ STLINK_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */ STLINK_CHIPID_STM32_F76xxx = 0x451, - STLINK_CHIPID_STM32_F72xxx = 0x452, /* ID found on the NucleoF722ZE board */ - STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G050/G051/G061 found in RM0444/RM0454 */ + STLINK_CHIPID_STM32_F72xxx = 0x452, /* ID found on the Nucleo F722ZE board */ + STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */ STLINK_CHIPID_STM32_L011 = 0x457, STLINK_CHIPID_STM32_F410 = 0x458, - STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/081 */ + STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */ STLINK_CHIPID_STM32_L496x_L4A6x = 0x461, STLINK_CHIPID_STM32_L45x_L46x = 0x462, STLINK_CHIPID_STM32_F413 = 0x463, STLINK_CHIPID_STM32_L41x_L42x = 0x464, - STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/041 */ - STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B0/G0B1/G0C1 found in RM0444/RM0454 */ + STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */ + STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */ STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, s46.6.1 "MCU device ID code" */ STLINK_CHIPID_STM32_G4_CAT3 = 0x469, - STLINK_CHIPID_STM32_L4Rx = 0x470, /* ID found on the STM32L4R9I-DISCO board */ + STLINK_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p. 2247, found on the STM32L4R9I-DISCO board */ + STLINK_CHIPID_STM32_L4PX = 0x471, /* RM0432, p. 2247 */ + STLINK_CHIPID_STM32_G4_CAT4 = 0x479, STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ STLINK_CHIPID_STM32_WB55 = 0x495 From 4949c23771b8348d33719a4275e04861e5068135 Mon Sep 17 00:00:00 2001 From: Anton Date: Fri, 28 May 2021 09:04:57 +0500 Subject: [PATCH 1213/1435] Fixed clear the H7 dual bank flag --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index 80190f756..f347fbc46 100644 --- a/src/common.c +++ b/src/common.c @@ -1664,7 +1664,7 @@ int stlink_load_device_params(stlink_t *sl) { // H7 devices with small flash has one bank if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && sl->flash_type == STLINK_FLASH_TYPE_H7) { - if ((flash_size / sl->flash_pgsz) <= 1) + if ((sl->flash_size / sl->flash_pgsz) <= 1) sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; } From 2e6c909c3e1b32340bdc4f2d2fee4bcdfc0a15f1 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 May 2021 23:51:12 +0200 Subject: [PATCH 1214/1435] General Project Update - Removed GitHub-CI VE for Ubuntu 16.04 (deprecated) - Minor fixes for some comments --- .github/workflows/c-cpp.yml | 90 ----------------------------------- doc/devices_boards.md | 2 +- src/stlink-lib/flash_loader.c | 2 +- 3 files changed, 2 insertions(+), 92 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index f68a9e53c..ee06d5469 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -9,96 +9,6 @@ on: jobs: # Linux - job_linux_16_04_64_gcc: - name: ubuntu-16.04 gcc - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - job_linux_16_04_32_gcc: - name: ubuntu-16.04 gcc 32-bit - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install gcc-5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: Set compiler flags - run: | - CFLAGS="$CFLAGS -m32" - CXXFLAGS="$CXXFLAGS -m32" - LDFLAGS="$LDFLAGS -m32" - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - job_linux_16_04_64_clang: - name: ubuntu-16.04 clang - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - job_linux_16_04_32_clang: - name: ubuntu-16.04 clang 32-bit - runs-on: ubuntu-16.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt-get install clang-3.5 libusb-1.0.0-dev libgtk-3-dev rpm - - name: Set compiler flags - run: | - CFLAGS="$CFLAGS -m32" - CXXFLAGS="$CXXFLAGS -m32" - LDFLAGS="$LDFLAGS -m32" - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - job_linux_18_04_64_gcc: name: ubuntu-18.04 gcc runs-on: ubuntu-18.04 diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 6548bc734..d93ec7a81 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -51,7 +51,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | ------- | ------------ | ------------- | | 0x411 | STM32F2yyxx | (all devices) | -**STM32F1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM3F1c_CORE_ID)** +**STM32F1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F1c_CORE_ID)** | Product-Code | Chip-ID | STLink
      Programmer | Boards | | ------------- | ------- | ---------------------- | ----------------------------------------------------------------------------------------------- | diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index d492716db..f013772e3 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -235,7 +235,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STLINK_CHIPID_STM32_L011 || sl->chip_id == STLINK_CHIPID_STM32_L0 || sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { // STM32l + sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { loader_code = loader_code_stm32lx; loader_size = sizeof(loader_code_stm32lx); } else if (sl->core_id == STM32VL_CORE_ID || From 007f39333e884b00c01939eb81757dd0d42c3507 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 31 May 2021 23:35:37 +0200 Subject: [PATCH 1215/1435] Corrected false character in some defines --- src/stlink-lib/chipid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 6fbfce696..8f8f91a9c 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -866,7 +866,7 @@ static struct stlink_chipid_params devices[] = { { // STM32H7A3/7B3 // RM0455 - .chip_id = STLINK_CHIPID_STM32_H7AX, + .chip_id = STLINK_CHIPID_STM32_H7Ax, .description = "H7Ax/H7Bx", .flash_type = STLINK_FLASH_TYPE_H7, .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) @@ -883,7 +883,7 @@ static struct stlink_chipid_params devices[] = { { // STM32H72x/H73x // RM0468 - .chip_id = STLINK_CHIPID_STM32_H72X, + .chip_id = STLINK_CHIPID_STM32_H72x, .description = "H72x/H73x", .flash_type = STLINK_FLASH_TYPE_H7, .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) From 93db93a0ad6ff058d45ef1cccd3a7ece800a5aa4 Mon Sep 17 00:00:00 2001 From: Gustavo Date: Sun, 6 Jun 2021 13:03:59 +0200 Subject: [PATCH 1216/1435] fix for 'libusb_devices were leaked' when no stlink was found --- src/stlink-lib/usb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 2754db06f..68e6302b9 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1273,6 +1273,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, if (cnt < 0) { WLOG ("Couldn't find %s ST-Link devices\n", (devBus && devAddr) ? "matched" : "any"); + libusb_free_device_list(list, 1); goto on_error; } else { ret = libusb_open(list[cnt], &slu->usb_handle); From ca896108eedde4a1a4c1ce00a1917771757bf514 Mon Sep 17 00:00:00 2001 From: Gustavo Date: Tue, 15 Jun 2021 20:45:19 +0200 Subject: [PATCH 1217/1435] fix for when the device list was not initialized --- src/stlink-lib/usb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 68e6302b9..9f83ace4a 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1203,7 +1203,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, libusb_set_option(slu->libusb_ctx, LIBUSB_OPTION_LOG_LEVEL, ugly_libusb_log_level(verbose)); #endif - libusb_device **list; + libusb_device **list = NULL; // TODO: We should use ssize_t and use it as a counter if > 0. // As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) int cnt = (int)libusb_get_device_list(slu->libusb_ctx, &list); @@ -1232,7 +1232,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, ILOG("bus %03d dev %03d\n", devBus, devAddr); } - while (cnt--) { + while (cnt-- > 0) { struct libusb_device_handle *handle; libusb_get_device_descriptor(list[cnt], &desc); From aa70b89b6e33eac460b9e7d0a73231d8a438ee10 Mon Sep 17 00:00:00 2001 From: anton Date: Wed, 23 Jun 2021 22:06:16 +0500 Subject: [PATCH 1218/1435] WRITEMEM_32BIT: removed checks limit --- src/stlink-lib/usb.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 5e5f042d5..0a4cfb489 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -306,12 +306,6 @@ int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { unsigned char* const cmd = sl->c_buf; int i, ret; - if ((sl->version.jtag_api < STLINK_JTAG_API_V3 && len > 64) || - (sl->version.jtag_api >= STLINK_JTAG_API_V3 && len > 512)) { - ELOG("WRITEMEM_32BIT: bulk packet limits exceeded (data len %d byte)\n", len); - return (-1); - } - i = fill_command(sl, SG_DXFER_TO_DEV, len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_WRITEMEM_32BIT; From 88398228a747a72831bcd7e515a965b84a13e79c Mon Sep 17 00:00:00 2001 From: c-grant <60671494+c-grant@users.noreply.github.com> Date: Tue, 13 Jul 2021 22:10:04 -0400 Subject: [PATCH 1219/1435] Update gdb-server.c --- src/st-util/gdb-server.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 6b68c8143..10aaea93a 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -501,6 +501,24 @@ static const char* const memory_map_template_H7 = " " // bootrom ""; +static const char* const memory_map_template_H72X3X = + "" + "" + "" + " " // ITCMRAM 64kB + Optional remap + " " // DTCMRAM 128kB + " " // RAM D1 320kB + " " // RAM D2 23kB + " " // RAM D3 16kB + " " // Backup RAM 4kB + " " + " 0x%x" + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + ""; static const char* const memory_map_template_F4_DE = "" @@ -563,7 +581,11 @@ char* make_memory_map(stlink_t *sl) { snprintf(map, sz, memory_map_template_L496, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else { + } else if (sl->chip_id == STLINK_CHIPID_STM32_H72X) { + snprintf(map, sz, memory_map_template_H72X3X, + (unsigned int)sl->flash_size, + (unsigned int)sl->flash_pgsz); + } else { snprintf(map, sz, memory_map_template, (unsigned int)sl->flash_size, (unsigned int)sl->sram_size, From 2a3c57747fd0caefca37f81f55be43ad175ffa2d Mon Sep 17 00:00:00 2001 From: Anton Date: Thu, 15 Jul 2021 15:59:35 +0500 Subject: [PATCH 1220/1435] Fixed get flash base address for STM32L152RE --- src/common.c | 43 +++++++++---------------------------------- 1 file changed, 9 insertions(+), 34 deletions(-) diff --git a/src/common.c b/src/common.c index f347fbc46..6cec3fde1 100644 --- a/src/common.c +++ b/src/common.c @@ -241,7 +241,6 @@ // STM32L0x flash register base and offsets RM0090 - DM00031020.pdf #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32L1_FLASH_REGS_ADDR ((uint32_t)0x40023c00) #define STM32L0_FLASH_PELOCK (0) #define STM32L0_FLASH_OPTLOCK (2) @@ -450,10 +449,11 @@ static uint32_t get_stm32l0_flash_base(stlink_t *sl) { case STLINK_CHIPID_STM32_L1_MEDIUM: case STLINK_CHIPID_STM32_L1_MEDIUM_PLUS: case STLINK_CHIPID_STM32_L1_HIGH: - return (STM32L1_FLASH_REGS_ADDR); + case STLINK_CHIPID_STM32_L152_RE: + return (STM32L_FLASH_REGS_ADDR); default: - WLOG("Flash base use default L0 address"); + WLOG("Flash base use default L0 address\n"); return (STM32L0_FLASH_REGS_ADDR); } } @@ -3204,15 +3204,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { ILOG("Starting Flash write for L0\n"); uint32_t val; - uint32_t flash_regs_base; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - } + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); // disable pecr protection stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, @@ -3327,19 +3319,9 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, } } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { uint32_t val; - uint32_t flash_regs_base; - uint32_t pagesize; - - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - pagesize = L0_WRITE_BLOCK_SIZE; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - pagesize = L1_WRITE_BLOCK_SIZE; - } + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? + L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; off = 0; @@ -3456,15 +3438,8 @@ int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { lock_flash(sl); } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { uint32_t val; - uint32_t flash_regs_base; - if (sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L011) { - flash_regs_base = STM32L0_FLASH_REGS_ADDR; - } else { - flash_regs_base = STM32L_FLASH_REGS_ADDR; - } + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + // reset lock bits stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); From 6e0dbfe97250b6ecba1f86c14d91d01c159b812c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 16 Jun 2021 13:12:19 +0200 Subject: [PATCH 1221/1435] Removed Travis CI integration Free Trial plan is no longer usable as credits are used up. --- .travis.sh | 46 ---------------------- .travis.yml | 111 ---------------------------------------------------- 2 files changed, 157 deletions(-) delete mode 100755 .travis.sh delete mode 100644 .travis.yml diff --git a/.travis.sh b/.travis.sh deleted file mode 100755 index d8c5377de..000000000 --- a/.travis.sh +++ /dev/null @@ -1,46 +0,0 @@ -#!/bin/bash -echo "-- C compilers available" -ls -1 /usr/bin/gcc* -ls -1 /usr/bin/clang* -ls -1 /usr/bin/scan-build* -echo "----" - -echo "WORK DIR:$DIR" -DIR=$PWD - -if [ "$TRAVIS_JOB_NAME" == "linux-mingw-64" ]; then - echo "--> Building for Windows (x86-64) ..." - mkdir -p build-mingw && cd build-mingw-64 - cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=x86_64-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && rm -rf build-mingw-64 && cd - - -elif [ "$TRAVIS_JOB_NAME" == "linux-mingw-32" ]; then - echo "--> Building for Windows (i686) ..." - mkdir -p build-mingw && cd build-mingw-32 - cmake -DCMAKE_SYSTEM_NAME=Windows -DTOOLCHAIN_PREFIX=i686-w64-mingw32 \ - -DCMAKE_TOOLCHAIN_FILE=$PWD/../cmake/modules/set_toolchain.cmake -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make && rm -rf build-mingw-32 && cd - - -elif [ "$TRAVIS_OS_NAME" == "osx" ]; then - echo "--> make debug..." - mkdir -p build/Debug && cd build/Debug - cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make debug && cd - - - echo "--> make package..." - mkdir -p build/Release && cd build/Release - cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install $DIR - make package && cd - - -else # local test-build - echo "--> Building Debug..." - mkdir -p build/Debug && cd build/Debug - cmake -DCMAKE_BUILD_TYPE=Debug -DCMAKE_INSTALL_PREFIX=$PWD/install ../../ - make && cd - - - echo "--> Building Release with package..." - mkdir -p build/Release && cd build/Release - cmake -DCMAKE_BUILD_TYPE=Release -DCMAKE_INSTALL_PREFIX=$PWD/install ../../ - make package && cd - -fi diff --git a/.travis.yml b/.travis.yml deleted file mode 100644 index 469094892..000000000 --- a/.travis.yml +++ /dev/null @@ -1,111 +0,0 @@ -language: c - -jobs: - include: - ### cross builds on AMD64 ### - - - os: linux - dist: focal - env: BADGE=linux-mingw-64 - name: linux-mingw - compiler: gcc-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: - ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - - - os: linux - dist: focal - env: BADGE=linux-mingw-32 - name: linux-mingw - compiler: gcc-10 - addons: - apt: - sources: ["ubuntu-toolchain-r-test"] - packages: - ["gcc-10", "libusb-1.0.0-dev", "libgtk-3-dev", "rpm", "mingw-w64"] - - ### macOS ### - - - os: osx - env: BADGE=osx - osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile - name: macOS 10.14.4 gcc - compiler: gcc - addons: - homebrew: - packages: - - gcc - - libusb - - gtk+3 - - - os: osx - env: BADGE=osx - osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile - name: macOS 10.14.4 gcc 32-bit - compiler: gcc - addons: - homebrew: - packages: - - gcc - - libusb - - gtk+3 - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - - os: osx - env: BADGE=osx - osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile - name: macOS 10.14.4 clang - compiler: clang - addons: - homebrew: - packages: - - clang - - libusb - - gtk+3 - - - os: osx - env: BADGE=osx - osx_image: xcode10.3 # xcode11.3 to xcode11.3.1 fail to compile - name: macOS 10.14.4 clang 32-bit - compiler: clang - addons: - homebrew: - packages: - - clang - - libusb - - gtk+3 - before_install: - - CFLAGS="$CFLAGS -m32"; CXXFLAGS="$CXXFLAGS -m32"; LDFLAGS="$LDFLAGS -m32"; - - - os: osx - env: BADGE=osx - osx_image: xcode12.5 - name: macOS 11.3 gcc - compiler: gcc - addons: - homebrew: - packages: - - gcc - - libusb - - gtk+3 - - - os: osx - env: BADGE=osx - osx_image: xcode12.5 - name: macOS 11.3 clang - compiler: clang - addons: - homebrew: - packages: - - clang - - libusb - - gtk+3 - -script: - - git fetch --tags - - printenv - - cmake --version - - if [[ "$TRAVIS_OS_NAME" == "linux" ]] || [[ "$TRAVIS_OS_NAME" == "osx" ]]; then ./.travis.sh; fi From a52e1bc5489e23f3c1071c6912820efacaa3b22c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 16 Jul 2021 16:00:27 +0200 Subject: [PATCH 1222/1435] Minor bugfixes --- src/common.c | 2 +- src/st-util/gdb-server.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/common.c b/src/common.c index 354075d8d..1457d640c 100644 --- a/src/common.c +++ b/src/common.c @@ -449,7 +449,7 @@ static uint32_t get_stm32l0_flash_base(stlink_t *sl) { case STLINK_CHIPID_STM32_L1_MD: case STLINK_CHIPID_STM32_L1_MD_PLUS: case STLINK_CHIPID_STM32_L1_MD_PLUS_HD: - return (STM32L1_FLASH_REGS_ADDR); + return (STM32L_FLASH_REGS_ADDR); default: WLOG("Flash base use default L0 address\n"); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 2f5ff1143..653c7bcec 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -503,7 +503,7 @@ static const char* const memory_map_template_H7 = " " // bootrom ""; -static const char* const memory_map_template_H72X3X = +static const char* const memory_map_template_H72x3x = "" "" @@ -583,8 +583,8 @@ char* make_memory_map(stlink_t *sl) { snprintf(map, sz, memory_map_template_L496, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_H72X) { - snprintf(map, sz, memory_map_template_H72X3X, + } else if (sl->chip_id == STLINK_CHIPID_STM32_H72x) { + snprintf(map, sz, memory_map_template_H72x3x, (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); } else { From 1dd94a16a8090f17d9c595daf1e899d95c0511ab Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Wed, 28 Jul 2021 16:26:33 +0200 Subject: [PATCH 1223/1435] Do not segfault if cannot find chip in config files stlink_chipid_get_params() used to segfault on memcmp() when struct stlink_chipid_params *params was NULL. This could happen if either: - there were no chip config files (*.chip), or - process_chipfile() failed to parse chip_id from the chip config files. The latter case is caused by the usage of atoi() to parse the chip id. Since the chip id is stored in hex, atoi() returns 0; such id cannot be matched to any actual chip. The segfault occurs on commit a52e1bc5489e23f3c1071c6912820efacaa3b22c, in file src/stlink-lib/chipid.c:957 (https://github.com/stlink-org/stlink/blob/a52e1bc5489e23f3c1071c6912820efacaa3b22c/src/stlink-lib/chipid.c#L957). Check if params is NULL, in such case, set it to p2, which should not be NULL as long as struct stlink_chipid_params devices[] exists. May fix (workaround) #1163. --- src/stlink-lib/chipid.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 8f8f91a9c..ebc3f4e20 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -954,7 +954,9 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { p2 = stlink_chipid_get_params_old(chipid); #if 1 - if (memcmp (p2, params, sizeof (struct stlink_chipid_params) - sizeof (struct stlink_chipid_params *)) != 0) { + if (params == NULL) { + params = p2; + } else if (memcmp (p2, params, sizeof (struct stlink_chipid_params) - sizeof (struct stlink_chipid_params *)) != 0) { //fprintf (stderr, "Error, chipid params not identical\n"); //return NULL; fprintf(stderr, "---------- old ------------\n"); From 35156b186d7915db52a7fef802d3d10be37bae0b Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Wed, 28 Jul 2021 18:47:25 +0200 Subject: [PATCH 1224/1435] Drop execute bits from source code files --- src/stlink-lib/md5.c | 0 src/stlink-lib/md5.h | 0 2 files changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 src/stlink-lib/md5.c mode change 100755 => 100644 src/stlink-lib/md5.h diff --git a/src/stlink-lib/md5.c b/src/stlink-lib/md5.c old mode 100755 new mode 100644 diff --git a/src/stlink-lib/md5.h b/src/stlink-lib/md5.h old mode 100755 new mode 100644 From 26a63c11a4125b7c5b3a2677f342cf13c37f1244 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 28 Jul 2021 22:03:03 +0200 Subject: [PATCH 1225/1435] [doc] Updated list of devices & boards (Closes #1164) --- doc/devices_boards.md | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/doc/devices_boards.md b/doc/devices_boards.md index d93ec7a81..26bad9150 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -125,9 +125,12 @@ Tested non-official ST boards [incl. STLINK programmers]: **STM32H7 / ARM Cortex M7F / Core-ID: 0x6ba02477 (STM32H7_CORE_ID)** -| Chip-ID | Product-Code | -| ------- | -------------- | -| 0x450 | STM32H74x/H75x | +| Chip-ID | Product-Code | +| ------- | ------------- | +| 0x450 | STM32H7**4**x | +| 0x450 | STM32H7**5**x | +| 0x480 | STM32H7**A**x | +| 0x480 | STM32H7**B**x | **STM32G0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32G0_CORE_ID)** @@ -146,6 +149,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x468 | STM32G4**41**xx | | 0x469 | STM32G4**7**xxx | | 0x469 | STM32G4**8**xxx | +| 0x479 | STM32G4**91**xx | **STM32L0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32L0_CORE_ID)** From b4245eadd0877546a5287a0365211d2d5c24273f Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Thu, 29 Jul 2021 15:46:53 +0200 Subject: [PATCH 1226/1435] Use proper Markdown headers for supported MCUs Use actual level 2 headers[1] instead of emulating them with bold/strong tags[2]. [1]: https://spec.commonmark.org/0.29/#atx-headings [2]: https://spec.commonmark.org/0.29/#emphasis-and-strong-emphasis --- doc/devices_boards.md | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 26bad9150..a8a366448 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -2,7 +2,7 @@ The following devices are supported by the stlink toolset. -**STM32F0 / ARM Cortex M0 / Core-ID: 0x0bb11477 (STM32F0_CORE_ID)** +## STM32F0 / ARM Cortex M0 / Core-ID: 0x0bb11477 (STM32F0_CORE_ID) | Chip-ID | Product-Code | | ------- | ------------------- | @@ -19,7 +19,7 @@ The following devices are supported by the stlink toolset. | 0x442 | STM32F0**9**xxx | -**STM32F1 / ARM Cortex M3 / Core-ID: 0x1ba01477 (STM32F1_CORE_ID)** +## STM32F1 / ARM Cortex M3 / Core-ID: 0x1ba01477 (STM32F1_CORE_ID) | Product-Code | Product Line | | ----------------- | ----------------------- | @@ -45,20 +45,20 @@ Tested non-official ST boards [incl. STLINK programmers]: - HY-STM32 (STM32F103VETx) [v1, v2] - DecaWave EVB1000 (STM32F105RCTx) [v1, v2] -**STM32F2 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F2_CORE_ID)** +## STM32F2 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F2_CORE_ID) | Chip-ID | Product-Code | Product Line | | ------- | ------------ | ------------- | | 0x411 | STM32F2yyxx | (all devices) | -**STM32F1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F1c_CORE_ID)** +## STM32F1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F1c_CORE_ID) | Product-Code | Chip-ID | STLink
      Programmer | Boards | | ------------- | ------- | ---------------------- | ----------------------------------------------------------------------------------------------- | | CKS32F103C8Tx | 0x410 | v2 | "STM32"-Bluepill ( _**Fake-Marking !**_ )
      STM32F103C8T6 clone from China Key Systems (CKS) | | CKS32F103C8Tx | 0x410 | v2 | CKS32-Bluepill (Clone)
      STM32F103C8T6 clone from China Key Systems (CKS) | -**STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3_CORE_ID)** +## STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3_CORE_ID) | Product-Code | Product Line | | ----------------- | ------------------------------------------------------------- | @@ -85,13 +85,13 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x446 | _N/A_ | xD xE | | F302 | F303 | | | 0x446 | _N/A_ | - | | | | F398 | -**STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3c_CORE_ID)** +## STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3c_CORE_ID) | Product-Code | Chip-ID | STLINK
      Programmer | Boards | | ------------ | ------- | ---------------------- | ---------------------------------- | | GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | -**STM32F4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F4_CORE_ID)** +## STM32F4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F4_CORE_ID) | Chip-ID | Product-Code | | ------- | ------------------- | @@ -112,7 +112,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x463 | STM32F4**13**xx | | 0x463 | STM32F4**23**xx | -**STM32F7 / ARM Cortex M7F / Core-ID: 0x5ba02477 (STM32F7_CORE_ID)** +## STM32F7 / ARM Cortex M7F / Core-ID: 0x5ba02477 (STM32F7_CORE_ID) | Chip-ID | Product-Code | | ------- | --------------- | @@ -123,7 +123,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x451 | STM32F7**6**xxx | | 0x451 | STM32F7**7**xxx | -**STM32H7 / ARM Cortex M7F / Core-ID: 0x6ba02477 (STM32H7_CORE_ID)** +## STM32H7 / ARM Cortex M7F / Core-ID: 0x6ba02477 (STM32H7_CORE_ID) | Chip-ID | Product-Code | | ------- | ------------- | @@ -132,7 +132,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x480 | STM32H7**A**x | | 0x480 | STM32H7**B**x | -**STM32G0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32G0_CORE_ID)** +## STM32G0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32G0_CORE_ID) | Chip-ID | Product-Code | | ------- | --------------- | @@ -141,7 +141,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x460 | STM32G0**7**xxx | | 0x460 | STM32G0**8**xxx | -**STM32G4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32G4_CORE_ID)** +## STM32G4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32G4_CORE_ID) | Chip-ID | Product-Code | | ------- | --------------- | @@ -151,7 +151,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x469 | STM32G4**8**xxx | | 0x479 | STM32G4**91**xx | -**STM32L0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32L0_CORE_ID)** +## STM32L0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32L0_CORE_ID) | Chip-ID | Product-Code | | ------- | --------------- | @@ -164,7 +164,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x447 | STM32L0**7**xxx | | 0x447 | STM32L0**8**xxx | -**STM32L1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32L1_CORE_ID)** +## STM32L1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32L1_CORE_ID) | Chip-ID | Product-Code | | ------- | ---------------- | @@ -178,7 +178,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x436 | STM32L1xxx**D** | | 0x437 | STM32L1xxx**E** | -**STM32L4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32L4_CORE_ID)** +## STM32L4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32L4_CORE_ID) | Chip-ID | Product-Code | | ------- | --------------- | @@ -197,7 +197,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x471 | STM32L4**P5**xx | | 0x471 | STM32L4**Q5**xx | -**STM32W / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32W_CORE_ID)** +## STM32W / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32W_CORE_ID) | Chip-ID | Product-Code | | ------- | --------------- | From e4b17475d179b37e60b686027d338891641effc1 Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Thu, 29 Jul 2021 21:48:53 +0200 Subject: [PATCH 1227/1435] Fix parsing hex numbers in chip config files MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit process_chipfile() used to improperly parse hex numbers in chip config files (*.chip), because it used atoi(), which read all such numbers as 0. This resulted, among other issues, in chip_id being set to 0 for all read chips. Such chip id could not match any actual MCU. Replace the atoi() calls with sscanf(…, "%i", …), where %i should match integers in base 10, 8 and 16, depending on the number prefix. --- src/stlink-lib/chipid.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 8f8f91a9c..2e99c580e 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -973,7 +973,7 @@ void process_chipfile(char *fname) char *p, *pp, buf[1025]; char word[64], value[64]; struct stlink_chipid_params *ts; - int nc, ival; + int nc; //fprintf (stderr, "processing chipfile %s.\n", fname); fp = fopen(fname, "r"); @@ -989,30 +989,39 @@ void process_chipfile(char *fname) if (*p == '#') continue; // ignore comments. sscanf(p, "%s %s", word, value); - ival = atoi (value); if (strcmp(word, "chip_id") == 0) { - ts->chip_id = ival; + if (sscanf(value, "%i", &ts->chip_id) < 1) + fprintf(stderr, "Failed to parse chip id\n"); } else if (strcmp (word, "description") == 0) { //ts->description = strdup (value); buf[strlen(p)-1] = 0; // chomp newline sscanf(p, "%*s %n", &nc); ts->description = strdup(p+nc); } else if (strcmp (word, "flash_type") == 0) { - ts->flash_type = ival; + // may set invalid flash types (not defined in enum stlink_flash_type) + if (sscanf(value, "%i", (int *) &ts->flash_type) < 1) + fprintf(stderr, "Failed to parse flash type\n"); } else if (strcmp (word, "flash_size_reg") == 0) { - ts->flash_size_reg = ival; + if (sscanf(value, "%i", &ts->flash_size_reg) < 1) + fprintf(stderr, "Failed to parse flash size reg\n"); } else if (strcmp (word, "flash_pagesize") == 0) { - ts->flash_pagesize = ival; + if (sscanf(value, "%i", &ts->flash_pagesize) < 1) + fprintf(stderr, "Failed to parse flash page size\n"); } else if (strcmp (word, "sram_size") == 0) { - ts->sram_size = ival; + if (sscanf(value, "%i", &ts->sram_size) < 1) + fprintf(stderr, "Failed to parse SRAM size\n"); } else if (strcmp (word, "bootrom_base") == 0) { - ts->bootrom_base = ival; + if (sscanf(value, "%i", &ts->bootrom_base) < 1) + fprintf(stderr, "Failed to parse BootROM base\n"); } else if (strcmp (word, "bootrom_size") == 0) { - ts->bootrom_size = ival; + if (sscanf(value, "%i", &ts->bootrom_size) < 1) + fprintf(stderr, "Failed to parse BootROM size\n"); } else if (strcmp (word, "option_base") == 0) { - ts->option_base = ival; + if (sscanf(value, "%i", &ts->option_base) < 1) + fprintf(stderr, "Failed to parse option base\n"); } else if (strcmp (word, "option_size") == 0) { - ts->option_size = ival; + if (sscanf(value, "%i", &ts->option_size) < 1) + fprintf(stderr, "Failed to parse option size\n"); } else if (strcmp (word, "flags") == 0) { pp = strtok (p, " \t\n"); while ((pp = strtok (NULL, " \t\n")) ) { From 929af2b047b7dfc54750842100a285646fb4a417 Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Fri, 30 Jul 2021 10:14:17 +0200 Subject: [PATCH 1228/1435] Add a constant for the valid flash types range Add a STLINK_FLASH_TYPE_MAX constant that can be used to check if a flash type (an integer) is in the range of valid enum stlink_flash_type values. --- inc/stlink.h | 1 + 1 file changed, 1 insertion(+) diff --git a/inc/stlink.h b/inc/stlink.h index f70060b05..81dc7902e 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -114,6 +114,7 @@ enum stlink_flash_type { STLINK_FLASH_TYPE_G4, STLINK_FLASH_TYPE_WB, STLINK_FLASH_TYPE_H7, + STLINK_FLASH_TYPE_MAX, }; struct stlink_reg { From ebac01c8d4e436f45afcc35c4452ffdb3750a13f Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Fri, 30 Jul 2021 10:18:02 +0200 Subject: [PATCH 1229/1435] Warn if chip config file contains unrecognized flash type --- src/stlink-lib/chipid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 2e99c580e..5080ef756 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -998,9 +998,10 @@ void process_chipfile(char *fname) sscanf(p, "%*s %n", &nc); ts->description = strdup(p+nc); } else if (strcmp (word, "flash_type") == 0) { - // may set invalid flash types (not defined in enum stlink_flash_type) if (sscanf(value, "%i", (int *) &ts->flash_type) < 1) fprintf(stderr, "Failed to parse flash type\n"); + else if (ts->flash_type <= STLINK_FLASH_TYPE_UNKNOWN || ts->flash_type >= STLINK_FLASH_TYPE_MAX) + fprintf(stderr, "Unrecognized flash type\n"); } else if (strcmp (word, "flash_size_reg") == 0) { if (sscanf(value, "%i", &ts->flash_size_reg) < 1) fprintf(stderr, "Failed to parse flash size reg\n"); From 1e674cff1a3557969b9dd55db9d13d9d40c2de93 Mon Sep 17 00:00:00 2001 From: Sam Bazley Date: Sun, 1 Aug 2021 21:36:40 +0100 Subject: [PATCH 1230/1435] Correct flash_pagesize to use hex format --- config/chips/F04x.chip | 2 +- config/chips/F07x.chip | 2 +- config/chips/F09x.chip | 2 +- config/chips/F0xx.chip | 2 +- config/chips/F0xx_small.chip | 2 +- config/chips/F1_XL-density.chip | 2 +- config/chips/F1_connectivity_line.chip | 2 +- config/chips/F1_high-density.chip | 2 +- config/chips/F1_low-density.chip | 2 +- config/chips/F1_medium-density.chip | 2 +- config/chips/F1_value_line.chip | 2 +- config/chips/F1_value_line_high-density.chip | 2 +- config/chips/F2.chip | 2 +- config/chips/F303_high_density.chip | 2 +- config/chips/F334_medium_density.chip | 2 +- config/chips/F37x.chip | 2 +- config/chips/F3xx_small.chip | 2 +- config/chips/F410.chip | 2 +- config/chips/F411xx.chip | 2 +- config/chips/F412.chip | 2 +- config/chips/F413.chip | 2 +- config/chips/F42x_F43x.chip | 2 +- config/chips/F446.chip | 2 +- config/chips/F46x_F47x.chip | 2 +- config/chips/F4xx.chip | 2 +- config/chips/F4xx_dynamic_efficiency.chip | 2 +- config/chips/F4xx_low_power.chip | 2 +- config/chips/F72x_F73x.chip | 2 +- config/chips/F76xxx.chip | 2 +- config/chips/F7xx.chip | 2 +- config/chips/G030_G031_G041.chip | 2 +- config/chips/G070_G071_G081.chip | 2 +- config/chips/G4_cat2.chip | 2 +- config/chips/G4_cat3.chip | 2 +- config/chips/H72x_H73x.chip | 2 +- config/chips/H74x_H75x.chip | 2 +- config/chips/H7Ax_H7Bx.chip | 2 +- config/chips/L011.chip | 2 +- config/chips/L0xx_cat2.chip | 2 +- config/chips/L0xx_cat5.chip | 2 +- config/chips/L152RE.chip | 2 +- config/chips/L1xx_cat2.chip | 2 +- config/chips/L1xx_high-density.chip | 2 +- config/chips/L1xx_medium-density.chip | 2 +- config/chips/L1xx_medium-plus-density.chip | 2 +- config/chips/L41x.chip | 2 +- config/chips/L43x_L44x.chip | 2 +- config/chips/L45x_L46x.chip | 2 +- config/chips/L496x_L4A6x.chip | 2 +- config/chips/L4Rx.chip | 2 +- config/chips/L4xx.chip | 2 +- config/chips/WB55.chip | 2 +- config/chips/unknown_device.chip | 2 +- 53 files changed, 53 insertions(+), 53 deletions(-) diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index b42d420fa..033c034e2 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -3,7 +3,7 @@ chip_id 0x445 description F04x flash_type 1 -flash_pagesize 400 +flash_pagesize 0x400 sram_size 0x1800 bootrom_base 0x1fffec00 bootrom_size 0xc00 diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index d8c71f0ea..dd697af40 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -3,7 +3,7 @@ chip_id 0x448 description F07x flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x4000 bootrom_base 0x1fffc800 bootrom_size 0x3000 diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index ca97d53e4..adb000030 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -3,7 +3,7 @@ chip_id 0x442 description F09x flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x8000 bootrom_base 0x1fffd800 bootrom_size 0x2000 diff --git a/config/chips/F0xx.chip b/config/chips/F0xx.chip index a1700eef3..309bbee34 100644 --- a/config/chips/F0xx.chip +++ b/config/chips/F0xx.chip @@ -3,7 +3,7 @@ chip_id 0x440 description F0xx flash_type 1 -flash_pagesize 400 +flash_pagesize 0x400 sram_size 0x2000 bootrom_base 0x1fffec00 bootrom_size 0xc00 diff --git a/config/chips/F0xx_small.chip b/config/chips/F0xx_small.chip index 3ab256feb..0a8ec265e 100644 --- a/config/chips/F0xx_small.chip +++ b/config/chips/F0xx_small.chip @@ -3,7 +3,7 @@ chip_id 0x444 description F0xx small flash_type 1 -flash_pagesize 400 +flash_pagesize 0x400 sram_size 0x1000 bootrom_base 0x1fffec00 bootrom_size 0xc00 diff --git a/config/chips/F1_XL-density.chip b/config/chips/F1_XL-density.chip index 97bb580e3..3b3c95ab0 100644 --- a/config/chips/F1_XL-density.chip +++ b/config/chips/F1_XL-density.chip @@ -3,7 +3,7 @@ chip_id 0x430 description F1 XL-density flash_type 2 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x18000 bootrom_base 0x1fffe000 bootrom_size 0x1800 diff --git a/config/chips/F1_connectivity_line.chip b/config/chips/F1_connectivity_line.chip index a030fd58d..b6fd9c93a 100644 --- a/config/chips/F1_connectivity_line.chip +++ b/config/chips/F1_connectivity_line.chip @@ -3,7 +3,7 @@ chip_id 0x418 description F1 connectivity line flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x10000 bootrom_base 0x1fffb000 bootrom_size 0x4800 diff --git a/config/chips/F1_high-density.chip b/config/chips/F1_high-density.chip index 00e4942b0..f88413fc8 100644 --- a/config/chips/F1_high-density.chip +++ b/config/chips/F1_high-density.chip @@ -3,7 +3,7 @@ chip_id 0x414 description F1 high-density flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x10000 bootrom_base 0x1ffff000 bootrom_size 0x800 diff --git a/config/chips/F1_low-density.chip b/config/chips/F1_low-density.chip index 1562c7589..3995cad96 100644 --- a/config/chips/F1_low-density.chip +++ b/config/chips/F1_low-density.chip @@ -3,7 +3,7 @@ chip_id 0x412 description F1 low-density flash_type 1 -flash_pagesize 400 +flash_pagesize 0x400 sram_size 0x2800 bootrom_base 0x1ffff000 bootrom_size 0x800 diff --git a/config/chips/F1_medium-density.chip b/config/chips/F1_medium-density.chip index 1f3d89234..25cbec2dc 100644 --- a/config/chips/F1_medium-density.chip +++ b/config/chips/F1_medium-density.chip @@ -3,7 +3,7 @@ chip_id 0x410 description F1 medium-density flash_type 1 -flash_pagesize 400 +flash_pagesize 0x400 sram_size 0x5000 bootrom_base 0x1ffff000 bootrom_size 0x800 diff --git a/config/chips/F1_value_line.chip b/config/chips/F1_value_line.chip index d9f04f00a..5515d9acd 100644 --- a/config/chips/F1_value_line.chip +++ b/config/chips/F1_value_line.chip @@ -3,7 +3,7 @@ chip_id 0x420 description F1 value line flash_type 1 -flash_pagesize 400 +flash_pagesize 0x400 sram_size 0x2000 bootrom_base 0x1ffff000 bootrom_size 0x800 diff --git a/config/chips/F1_value_line_high-density.chip b/config/chips/F1_value_line_high-density.chip index 2ecf6b4f5..6a49c2699 100644 --- a/config/chips/F1_value_line_high-density.chip +++ b/config/chips/F1_value_line_high-density.chip @@ -3,7 +3,7 @@ chip_id 0x428 description F1 value line high-density flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x8000 bootrom_base 0x1ffff000 bootrom_size 0x800 diff --git a/config/chips/F2.chip b/config/chips/F2.chip index 098ddc863..31a4d34a8 100644 --- a/config/chips/F2.chip +++ b/config/chips/F2.chip @@ -3,7 +3,7 @@ chip_id 0x411 description F2 flash_type 3 -flash_pagesize 20000 +flash_pagesize 0x20000 sram_size 0x20000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F303_high_density.chip b/config/chips/F303_high_density.chip index 19cc2ad2a..afbdf63b5 100644 --- a/config/chips/F303_high_density.chip +++ b/config/chips/F303_high_density.chip @@ -3,7 +3,7 @@ chip_id 0x446 description F303 high density flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x10000 bootrom_base 0x1fffd800 bootrom_size 0x2000 diff --git a/config/chips/F334_medium_density.chip b/config/chips/F334_medium_density.chip index ba4cf9688..365931a01 100644 --- a/config/chips/F334_medium_density.chip +++ b/config/chips/F334_medium_density.chip @@ -3,7 +3,7 @@ chip_id 0x438 description F334 medium density flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x3000 bootrom_base 0x1fffd800 bootrom_size 0x2000 diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index d0081e68a..5d5723b14 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -3,7 +3,7 @@ chip_id 0x432 description F37x flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0xa000 bootrom_base 0x1ffff000 bootrom_size 0x800 diff --git a/config/chips/F3xx_small.chip b/config/chips/F3xx_small.chip index 34d1940ac..31fd136a8 100644 --- a/config/chips/F3xx_small.chip +++ b/config/chips/F3xx_small.chip @@ -3,7 +3,7 @@ chip_id 0x439 description F3xx small flash_type 1 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0xa000 bootrom_base 0x1fffd800 bootrom_size 0x2000 diff --git a/config/chips/F410.chip b/config/chips/F410.chip index 3cd382845..ae199d9c4 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -3,7 +3,7 @@ chip_id 0x458 description F410 flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x8000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F411xx.chip b/config/chips/F411xx.chip index 301e6cb91..e41288de7 100644 --- a/config/chips/F411xx.chip +++ b/config/chips/F411xx.chip @@ -3,7 +3,7 @@ chip_id 0x431 description F411xx flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x20000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F412.chip b/config/chips/F412.chip index 186a43427..3212a340c 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -3,7 +3,7 @@ chip_id 0x441 description F412 flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x40000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F413.chip b/config/chips/F413.chip index 367344aaa..94813647f 100644 --- a/config/chips/F413.chip +++ b/config/chips/F413.chip @@ -3,7 +3,7 @@ chip_id 0x463 description F413 flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x50000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 4557a731c..3184d0d4f 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -3,7 +3,7 @@ chip_id 0x419 description F42x/F43x flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x40000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 9f7ae0bc5..86cee6a56 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -3,7 +3,7 @@ chip_id 0x421 description F446 flash_type 3 -flash_pagesize 20000 +flash_pagesize 0x20000 sram_size 0x20000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index 8ae43eb2e..ee5f6a5a7 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -3,7 +3,7 @@ chip_id 0x434 description F46x/F47x flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x40000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F4xx.chip b/config/chips/F4xx.chip index 17ec62d68..1c6d087a5 100644 --- a/config/chips/F4xx.chip +++ b/config/chips/F4xx.chip @@ -3,7 +3,7 @@ chip_id 0x413 description F4xx flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x30000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F4xx_dynamic_efficiency.chip b/config/chips/F4xx_dynamic_efficiency.chip index 6d06bcb8e..02a886c26 100644 --- a/config/chips/F4xx_dynamic_efficiency.chip +++ b/config/chips/F4xx_dynamic_efficiency.chip @@ -3,7 +3,7 @@ chip_id 0x433 description F4xx dynamic efficiency flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x18000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F4xx_low_power.chip b/config/chips/F4xx_low_power.chip index ad8c3ce90..7c1cc1243 100644 --- a/config/chips/F4xx_low_power.chip +++ b/config/chips/F4xx_low_power.chip @@ -3,7 +3,7 @@ chip_id 0x423 description F4xx low power flash_type 3 -flash_pagesize 4000 +flash_pagesize 0x4000 sram_size 0x10000 bootrom_base 0x1fff0000 bootrom_size 0x7800 diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index b6f706994..2836040ac 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -3,7 +3,7 @@ chip_id 0x452 description F72x/F73x flash_type 3 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x40000 bootrom_base 0x100000 bootrom_size 0xedc0 diff --git a/config/chips/F76xxx.chip b/config/chips/F76xxx.chip index 49ac1ec21..ef17fc557 100644 --- a/config/chips/F76xxx.chip +++ b/config/chips/F76xxx.chip @@ -3,7 +3,7 @@ chip_id 0x451 description F76xxx flash_type 4 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x80000 bootrom_base 0x200000 bootrom_size 0xedc0 diff --git a/config/chips/F7xx.chip b/config/chips/F7xx.chip index 87420f2ab..b6e3774f7 100644 --- a/config/chips/F7xx.chip +++ b/config/chips/F7xx.chip @@ -3,7 +3,7 @@ chip_id 0x449 description F7xx flash_type 3 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x50000 bootrom_base 0x100000 bootrom_size 0xedc0 diff --git a/config/chips/G030_G031_G041.chip b/config/chips/G030_G031_G041.chip index 7d47e7aed..16a9a79ff 100644 --- a/config/chips/G030_G031_G041.chip +++ b/config/chips/G030_G031_G041.chip @@ -3,7 +3,7 @@ chip_id 0x466 description G030/G031/G041 flash_type 7 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x2000 bootrom_base 0x1fff0000 bootrom_size 0x2000 diff --git a/config/chips/G070_G071_G081.chip b/config/chips/G070_G071_G081.chip index 9905fc682..7fb81eb1f 100644 --- a/config/chips/G070_G071_G081.chip +++ b/config/chips/G070_G071_G081.chip @@ -3,7 +3,7 @@ chip_id 0x460 description G070/G071/G081 flash_type 7 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x9000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/G4_cat2.chip b/config/chips/G4_cat2.chip index 47745e715..ea144114d 100644 --- a/config/chips/G4_cat2.chip +++ b/config/chips/G4_cat2.chip @@ -3,7 +3,7 @@ chip_id 0x468 description G4 cat2 flash_type 8 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x8000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/G4_cat3.chip b/config/chips/G4_cat3.chip index f883b9176..7e34e001c 100644 --- a/config/chips/G4_cat3.chip +++ b/config/chips/G4_cat3.chip @@ -3,7 +3,7 @@ chip_id 0x469 description G4 cat3 flash_type 8 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x18000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index 81c1b71c9..df20037d3 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -3,7 +3,7 @@ chip_id 0x483 description H72x/H73x flash_type 10 -flash_pagesize 20000 +flash_pagesize 0x20000 sram_size 0x20000 bootrom_base 0x1ff00000 bootrom_size 0x20000 diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 7753cfe03..7a4bc86e3 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -3,7 +3,7 @@ chip_id 0x450 description H74x/H75x flash_type 10 -flash_pagesize 20000 +flash_pagesize 0x20000 sram_size 0x20000 bootrom_base 0x1ff00000 bootrom_size 0x20000 diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index df6c13726..b9202bd1a 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -3,7 +3,7 @@ chip_id 0x480 description H7Ax/H7Bx flash_type 10 -flash_pagesize 2000 +flash_pagesize 0x2000 sram_size 0x20000 bootrom_base 0x1ff00000 bootrom_size 0x20000 diff --git a/config/chips/L011.chip b/config/chips/L011.chip index 2f1fa7b56..719185558 100644 --- a/config/chips/L011.chip +++ b/config/chips/L011.chip @@ -3,7 +3,7 @@ chip_id 0x457 description L011 flash_type 5 -flash_pagesize 80 +flash_pagesize 0x80 sram_size 0x2000 bootrom_base 0x1ff00000 bootrom_size 0x2000 diff --git a/config/chips/L0xx_cat2.chip b/config/chips/L0xx_cat2.chip index 43a301b27..cdcff81cc 100644 --- a/config/chips/L0xx_cat2.chip +++ b/config/chips/L0xx_cat2.chip @@ -3,7 +3,7 @@ chip_id 0x425 description L0xx cat2 flash_type 5 -flash_pagesize 80 +flash_pagesize 0x80 sram_size 0x2000 bootrom_base 0x1ff0000 bootrom_size 0x1000 diff --git a/config/chips/L0xx_cat5.chip b/config/chips/L0xx_cat5.chip index 8ab0a50f8..2c755a0d8 100644 --- a/config/chips/L0xx_cat5.chip +++ b/config/chips/L0xx_cat5.chip @@ -3,7 +3,7 @@ chip_id 0x447 description L0xx cat5 flash_type 5 -flash_pagesize 80 +flash_pagesize 0x80 sram_size 0x5000 bootrom_base 0x1ff0000 bootrom_size 0x2000 diff --git a/config/chips/L152RE.chip b/config/chips/L152RE.chip index ebe012c5a..4d9658ee9 100644 --- a/config/chips/L152RE.chip +++ b/config/chips/L152RE.chip @@ -3,7 +3,7 @@ chip_id 0x437 description L152RE flash_type 5 -flash_pagesize 100 +flash_pagesize 0x100 sram_size 0x14000 bootrom_base 0x1ff00000 bootrom_size 0x1000 diff --git a/config/chips/L1xx_cat2.chip b/config/chips/L1xx_cat2.chip index 02012078a..7f949923e 100644 --- a/config/chips/L1xx_cat2.chip +++ b/config/chips/L1xx_cat2.chip @@ -3,7 +3,7 @@ chip_id 0x429 description L1xx cat2 flash_type 5 -flash_pagesize 100 +flash_pagesize 0x100 sram_size 0x8000 bootrom_base 0x1ff00000 bootrom_size 0x1000 diff --git a/config/chips/L1xx_high-density.chip b/config/chips/L1xx_high-density.chip index 130b4e456..409c04062 100644 --- a/config/chips/L1xx_high-density.chip +++ b/config/chips/L1xx_high-density.chip @@ -3,7 +3,7 @@ chip_id 0x436 description L1xx high-density flash_type 5 -flash_pagesize 100 +flash_pagesize 0x100 sram_size 0xc000 bootrom_base 0x1ff00000 bootrom_size 0x1000 diff --git a/config/chips/L1xx_medium-density.chip b/config/chips/L1xx_medium-density.chip index 409b4dacc..f77c19cac 100644 --- a/config/chips/L1xx_medium-density.chip +++ b/config/chips/L1xx_medium-density.chip @@ -3,7 +3,7 @@ chip_id 0x416 description L1xx medium-density flash_type 5 -flash_pagesize 100 +flash_pagesize 0x100 sram_size 0x4000 bootrom_base 0x1ff00000 bootrom_size 0x1000 diff --git a/config/chips/L1xx_medium-plus-density.chip b/config/chips/L1xx_medium-plus-density.chip index 374f2e914..da557e3c8 100644 --- a/config/chips/L1xx_medium-plus-density.chip +++ b/config/chips/L1xx_medium-plus-density.chip @@ -3,7 +3,7 @@ chip_id 0x427 description L1xx medium-plus-density flash_type 5 -flash_pagesize 100 +flash_pagesize 0x100 sram_size 0x8000 bootrom_base 0x1ff00000 bootrom_size 0x1000 diff --git a/config/chips/L41x.chip b/config/chips/L41x.chip index cf51b4b02..5b491ccd4 100644 --- a/config/chips/L41x.chip +++ b/config/chips/L41x.chip @@ -3,7 +3,7 @@ chip_id 0x464 description L41x flash_type 6 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0xa000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index 1953a6a99..383c42f3f 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -3,7 +3,7 @@ chip_id 0x435 description L43x/L44x flash_type 6 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0xc000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index 79a90fcac..8b5f91ec3 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -3,7 +3,7 @@ chip_id 0x462 description L45x/L46x flash_type 6 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x20000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index f94c0c582..57f539db3 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -3,7 +3,7 @@ chip_id 0x461 description L496x/L4A6x flash_type 6 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x40000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index 355f22470..11780ce27 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -3,7 +3,7 @@ chip_id 0x470 description L4Rx flash_type 6 -flash_pagesize 1000 +flash_pagesize 0x1000 sram_size 0xa0000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/L4xx.chip b/config/chips/L4xx.chip index 3360a446e..c665c245f 100644 --- a/config/chips/L4xx.chip +++ b/config/chips/L4xx.chip @@ -3,7 +3,7 @@ chip_id 0x415 description L4xx flash_type 6 -flash_pagesize 800 +flash_pagesize 0x800 sram_size 0x18000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/WB55.chip b/config/chips/WB55.chip index 9cf1d4380..585b576bc 100644 --- a/config/chips/WB55.chip +++ b/config/chips/WB55.chip @@ -3,7 +3,7 @@ chip_id 0x495 description WB55 flash_type 9 -flash_pagesize 1000 +flash_pagesize 0x1000 sram_size 0x40000 bootrom_base 0x1fff0000 bootrom_size 0x7000 diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index 2235d0072..c71206951 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -3,7 +3,7 @@ chip_id 0x0 description unknown device flash_type 0 -flash_pagesize 0 +flash_pagesize 0x0 sram_size 0x0 bootrom_base 0x0 bootrom_size 0x0 From fe48a98cb1802732edb117fe60cd9b2fa0689145 Mon Sep 17 00:00:00 2001 From: Sam Bazley Date: Sun, 1 Aug 2021 21:25:06 +0100 Subject: [PATCH 1231/1435] Add STM32WLEx support --- config/chips/WLE.chip | 13 +++++++++++++ src/stlink-lib/chipid.c | 12 ++++++++++++ src/stlink-lib/chipid.h | 3 ++- 3 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 config/chips/WLE.chip diff --git a/config/chips/WLE.chip b/config/chips/WLE.chip new file mode 100644 index 000000000..dbdf66d59 --- /dev/null +++ b/config/chips/WLE.chip @@ -0,0 +1,13 @@ +# Chip-ID file for WLE +# +chip_id 0x497 +description WLE +flash_type 9 +flash_pagesize 0x800 +sram_size 0x10000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x0 +option_size 0x0 +flags swo + diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 212328f86..28e4e91e9 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -847,6 +847,18 @@ static struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, .flags = CHIP_F_HAS_SWO_TRACING, }, + { + // STM32WLEx + .chip_id = STLINK_CHIPID_STM32_WLE, + .description = "WLEx", + .flash_type = STLINK_FLASH_TYPE_WB, + .flash_size_reg = 0x1FFF75E0, + .flash_pagesize = 0x800, // 2k + .sram_size = 0x10000, + .bootrom_base = 0x1fff0000, // see the memory map + .bootrom_size = 0x7000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, { // STM32H742/743/753 (from RM0433) .chip_id = STLINK_CHIPID_STM32_H74xxx, diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 75288093a..20cfcf52d 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -70,7 +70,8 @@ enum stlink_stm32_chipids { STLINK_CHIPID_STM32_G4_CAT4 = 0x479, STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ - STLINK_CHIPID_STM32_WB55 = 0x495 + STLINK_CHIPID_STM32_WB55 = 0x495, + STLINK_CHIPID_STM32_WLE = 0x497 }; #define CHIP_F_HAS_DUAL_BANK (1 << 0) From 41d7ca710eace2b52b5e224a9f238be151477004 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Fri, 13 Aug 2021 20:02:26 +0300 Subject: [PATCH 1232/1435] fix compilation for MSVC --- CMakeLists.txt | 5 +++++ src/common.c | 2 +- src/stlink-lib/chipid.c | 45 ++++++++++++++++++++++++++++++++++++----- 3 files changed, 46 insertions(+), 6 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 09e0a1bac..5c8aaa60c 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -75,6 +75,11 @@ if (STLINK_HAVE_UNISTD_H) add_definitions(-DSTLINK_HAVE_UNISTD_H) endif () +CHECK_INCLUDE_FILE(dirent.h STLINK_HAVE_DIRENT_H) +if (STLINK_HAVE_DIRENT_H) + add_definitions(-DSTLINK_HAVE_DIRENT_H) +endif () + if (MSVC) # Use string.h rather than strings.h and disable annoying warnings add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) diff --git a/src/common.c b/src/common.c index 1457d640c..af96b70b8 100644 --- a/src/common.c +++ b/src/common.c @@ -1541,7 +1541,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { if (ret || !(*chip_id)) { *chip_id = 0; - ret = ret?:-1; + ret = ret?ret:-1; ELOG("Could not find chip id!\n"); } else { *chip_id = (*chip_id) & 0xfff; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 28e4e91e9..0ed774218 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,7 +1,6 @@ #include #include "chipid.h" -#include #include #include #include @@ -962,7 +961,7 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { // fprintf (stderr, "getparams: %x\n", chipid); for (params = devicelist ; params != NULL ; params = params -> next) if (params->chip_id == chipid) break; - + p2 = stlink_chipid_get_params_old(chipid); #if 1 @@ -1061,7 +1060,7 @@ void dump_chips (void) struct stlink_chipid_params *ts; char *p, buf[100]; FILE *fp; - + for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { ts = &devices[n]; @@ -1086,7 +1085,9 @@ void dump_chips (void) } } -void init_chipids(char *dir_to_scan) +#if defined(STLINK_HAVE_DIRENT_H) +#include +void init_chipids(char *dir_to_scan) { DIR *d; size_t nl; // namelen @@ -1121,11 +1122,45 @@ void init_chipids(char *dir_to_scan) dump_a_chip (stderr, op); fprintf (stderr, "---------- new ------------\n"); dump_a_chip (stderr, p); - + } } #endif } +#endif //STLINK_HAVE_DIRENT_H + +#if defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) +#include +#include +void init_chipids(char *dir_to_scan) +{ + HANDLE hFind = INVALID_HANDLE_VALUE; + WIN32_FIND_DATAA ffd; + char file_pattern[MAX_PATH] = {0}; + char filepath[MAX_PATH] = {0}; + StringCchCopyA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), dir_to_scan); + if (FAILED(StringCchCatA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), "\\*.chip"))) { + ELOG("Path to chips's dir too long.\n"); + return; + }; + hFind = FindFirstFileA(file_pattern, &ffd); + if (INVALID_HANDLE_VALUE == hFind){ + ELOG("Can't find any chip description file in %s.\n", file_pattern); + return; + } + + do { + memset(filepath, 0, STLINK_ARRAY_SIZE(filepath)); + StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), "\\"); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), ffd.cFileName); + process_chipfile(filepath); + } while(FindNextFileA(hFind, &ffd) != 0); + + FindClose(hFind); +} +#endif //defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) + From af384e96930f09e5032f79afca03155d86e9759a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 13 Aug 2021 21:23:00 +0200 Subject: [PATCH 1233/1435] Update src/stlink-lib/chipid.c Co-authored-by: Grzegorz Szymaszek --- src/stlink-lib/chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 0ed774218..bd5a7b9e2 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1155,7 +1155,7 @@ void init_chipids(char *dir_to_scan) StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), "\\"); StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), ffd.cFileName); process_chipfile(filepath); - } while(FindNextFileA(hFind, &ffd) != 0); + } while (FindNextFileA(hFind, &ffd) != 0); FindClose(hFind); } From 274be86616801d65cdc0e1f1bf380c98a7aa5b85 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Fri, 13 Aug 2021 22:40:24 +0300 Subject: [PATCH 1234/1435] Update src/stlink-lib/chipid.c Co-authored-by: Grzegorz Szymaszek --- src/stlink-lib/chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index bd5a7b9e2..d7e7f1328 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1144,7 +1144,7 @@ void init_chipids(char *dir_to_scan) return; }; hFind = FindFirstFileA(file_pattern, &ffd); - if (INVALID_HANDLE_VALUE == hFind){ + if (INVALID_HANDLE_VALUE == hFind) { ELOG("Can't find any chip description file in %s.\n", file_pattern); return; } From 9ec951c008b84f89debd69929a0aba6d1e4f4a22 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Fri, 13 Aug 2021 23:18:46 +0300 Subject: [PATCH 1235/1435] uncrustify chipid.c --- src/stlink-lib/chipid.c | 554 ++++++++++++++++++++-------------------- 1 file changed, 276 insertions(+), 278 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index d7e7f1328..dcf677909 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,18 +1,18 @@ #include #include "chipid.h" -#include -#include +#include +#include #include #include #include -// This is the old chipid "database". +// This is the old chipid "database". // It is kept here for now to be able to compare the -// result between the "old code" and the "new code". -// For now if you need to change something, please -// change it both here and in the corresponding -// config/chips/*.chip file. +// result between the "old code" and the "new code". +// For now if you need to change something, please +// change it both here and in the corresponding +// config/chips/*.chip file. static struct stlink_chipid_params devices[] = { { @@ -26,10 +26,9 @@ static struct stlink_chipid_params devices[] = { .sram_size = 0x80000, // "SRAM" byte size in hex from .bootrom_base = 0x00200000, // "System memory" starting address from .bootrom_size = 0xEDC0, - .option_base = - STM32_F7_OPTION_BYTES_BASE, // Used for reading back the option - // bytes, writing uses FLASH_F7_OPTCR - // and FLASH_F7_OPTCR1 + .option_base = STM32_F7_OPTION_BYTES_BASE, /* Used for reading back the option + bytes, writing uses FLASH_F7_OPTCR + and FLASH_F7_OPTCR1 */ .option_size = 0x20, .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, @@ -42,10 +41,8 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ff0f442, // section 41.2 .flash_pagesize = 0x800, // No flash pages .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 - .bootrom_base = - 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = - 0xEDC0, // "System memory" byte size in hex from DS Fig 18 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -57,10 +54,8 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ff07a22, // section 35.2 .flash_pagesize = 0x800, // No flash pages .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 - .bootrom_base = - 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = - 0xEDC0, // "System memory" byte size in hex from DS Fig 24 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 .flags = CHIP_F_HAS_SWO_TRACING, }, { @@ -323,7 +318,7 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F303xB/C, STM32F358, STM32F302xBxC + // STM32F303xB/C, STM32F358, STM32F302xBxC // RM0316, RM0365 .chip_id = STLINK_CHIPID_STM32_F3, .description = "F302/F303/F358", @@ -389,8 +384,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = - 0x1fffC800, // "System memory" starting address from Table 2 + .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, @@ -404,8 +398,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = - 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, @@ -419,8 +412,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) .flash_pagesize = 0x4000, // Table 5. Flash module organization ? .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 - .bootrom_base = - 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 .flags = CHIP_F_HAS_SWO_TRACING, }, @@ -431,13 +423,11 @@ static struct stlink_chipid_params devices[] = { .description = "F413/F423", .flash_type = STLINK_FLASH_TYPE_F4, .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 - .flash_pagesize = - 0x4000, // Table 5. Flash module organization (variable sector - // sizes, but 0x4000 is smallest) + .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector + // sizes, but 0x4000 is smallest) .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 // only says 0x40000) - .bootrom_base = - 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 .flags = CHIP_F_HAS_SWO_TRACING, }, @@ -450,8 +440,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) - .bootrom_base = - 0x1fffd800, // "System memory" starting address from Table 2 + .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, @@ -465,8 +454,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 - .bootrom_base = - 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, @@ -480,8 +468,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = - 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, @@ -580,17 +567,14 @@ static struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L4, .description = "L47x/L48x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = - 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = - 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 + .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 // and tables 4-6 on pages 79-81) // SRAM1 is "up to" 96k in the standard Cortex-M memory map; // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for // sizes; table 2, page 74 for SRAM2 location) .sram_size = 0x18000, - .bootrom_base = - 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, @@ -602,12 +586,10 @@ static struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L4Rx, .description = "L4Rx", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = - 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - //TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = - 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, @@ -618,12 +600,10 @@ static struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L4PX, .description = "L4Px", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = - 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - //TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = - 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, @@ -638,11 +618,10 @@ static struct stlink_chipid_params devices[] = { // sec 47.2, page 1586) .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 - // (DS12469, sec 3.5, page 18) + // SRAM2 is 8k at 0x10000000 and 0x20008000 + // (DS12469, sec 3.5, page 18) .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) - .bootrom_base = - 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) + .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) .bootrom_size = 0x7000, // 28k, same source as base .flags = CHIP_F_HAS_SWO_TRACING, }, @@ -652,17 +631,14 @@ static struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L43x_L44x, .description = "L43x/L44x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = - 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = - 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 // and tables 7-8 on pages 75-76) // SRAM1 is "up to" 64k in the standard Cortex-M memory map; // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for // sizes; table 2, page 74 for SRAM2 location) .sram_size = 0xc000, - .bootrom_base = - 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) .bootrom_size = 0x7000, // 28k (per bank), same source as base .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, @@ -674,10 +650,8 @@ static struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, .description = "L496x/L4A6x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = - 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = - 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) + .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) // SRAM1 is 256k at 0x20000000 // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) @@ -693,10 +667,8 @@ static struct stlink_chipid_params devices[] = { .chip_id = STLINK_CHIPID_STM32_L45x_L46x, .description = "L45x/46x", .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = - 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = - 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 // and tables 7 on pages 73-74) // SRAM1 is 128k at 0x20000000; // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, @@ -783,8 +755,7 @@ static struct stlink_chipid_params devices[] = { .description = "G43x/G44x", .flash_type = STLINK_FLASH_TYPE_G4, .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = - 0x800, // 2k (sec 3.3.1) + .flash_pagesize = 0x800, // 2k (sec 3.3.1) // SRAM1 is 16k at 0x20000000 // SRAM2 is 6k at 0x20014000 // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 @@ -802,8 +773,7 @@ static struct stlink_chipid_params devices[] = { .description = "G47x/G48x", .flash_type = STLINK_FLASH_TYPE_G4, .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = - 0x800, // 2k (sec 3.3.1) + .flash_pagesize = 0x800, // 2k (sec 3.3.1) // SRAM1 is 80k at 0x20000000 // SRAM2 is 16k at 0x20014000 // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 @@ -821,8 +791,7 @@ static struct stlink_chipid_params devices[] = { .description = "G49x/G4Ax", .flash_type = STLINK_FLASH_TYPE_G4, .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = - 0x800, // 2k (sec 3.3.1) + .flash_pagesize = 0x800, // 2k (sec 3.3.1) // SRAM1 is 80k at 0x20000000 // SRAM2 is 16k at 0x20014000 // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 @@ -866,10 +835,8 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) .flash_pagesize = 0x20000, // 128k sector (pg147) .sram_size = 0x20000, // 128k "DTCM" from Table 7 - .bootrom_base = - 0x1ff00000, // "System memory" starting address from Table 7 - .bootrom_size = - 0x20000, // "System memory" byte size in hex from Table 7 + .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 + .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, @@ -883,8 +850,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) .flash_pagesize = 0x2000, // 8k sector (p.146) .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = - 0x1FF00000, // "System memory" starting address (Table 12-14) + .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 12-14) .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to // two banks (Table 12-14) .option_base = STM32_H7_OPTION_BYTES_BASE, @@ -900,8 +866,7 @@ static struct stlink_chipid_params devices[] = { .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) .flash_pagesize = 0x20000, // 128k sector (p.152) .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = - 0x1FF00000, // "System memory" starting address (Table 6) + .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 6) .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) .option_base = STM32_H7_OPTION_BYTES_BASE, .option_size = 44, @@ -922,209 +887,239 @@ static struct stlink_chipid_params devices[] = { }; struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { - struct stlink_chipid_params *params = NULL; + struct stlink_chipid_params *params = NULL; - for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) - if (devices[n].chip_id == chipid) { - params = &devices[n]; - break; - } + for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) + if (devices[n].chip_id == chipid) { + params = &devices[n]; + break; + } - return (params); + return (params); } static struct stlink_chipid_params *devicelist; - -void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) -{ - fprintf(fp, "# Chip-ID file for %s\n", dev->description); - fprintf(fp, "#\n"); - fprintf(fp, "chip_id 0x%x\n", dev->chip_id); - fprintf(fp, "description %s\n", dev->description); - fprintf(fp, "flash_type %d\n", dev->flash_type); - fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); - fprintf(fp, "sram_size 0x%x\n", dev->sram_size); - fprintf(fp, "bootrom_base 0x%x\n", dev->bootrom_base); - fprintf(fp, "bootrom_size 0x%x\n", dev->bootrom_size); - fprintf(fp, "option_base 0x%x\n", dev->option_base); - fprintf(fp, "option_size 0x%x\n", dev->option_size); - fprintf(fp, "flags %d\n\n", dev->flags); +void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { + fprintf(fp, "# Chip-ID file for %s\n", dev->description); + fprintf(fp, "#\n"); + fprintf(fp, "chip_id 0x%x\n", dev->chip_id); + fprintf(fp, "description %s\n", dev->description); + fprintf(fp, "flash_type %d\n", dev->flash_type); + fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); + fprintf(fp, "sram_size 0x%x\n", dev->sram_size); + fprintf(fp, "bootrom_base 0x%x\n", dev->bootrom_base); + fprintf(fp, "bootrom_size 0x%x\n", dev->bootrom_size); + fprintf(fp, "option_base 0x%x\n", dev->option_base); + fprintf(fp, "option_size 0x%x\n", dev->option_size); + fprintf(fp, "flags %d\n\n", dev->flags); } - - struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { - struct stlink_chipid_params *params = NULL; - struct stlink_chipid_params *p2; + struct stlink_chipid_params *params = NULL; + struct stlink_chipid_params *p2; - // fprintf (stderr, "getparams: %x\n", chipid); - for (params = devicelist ; params != NULL ; params = params -> next) - if (params->chip_id == chipid) break; + //fprintf (stderr, "getparams: %x\n", chipid); + for (params = devicelist; params != NULL; params = params->next) + if (params->chip_id == chipid) { + break; + } - p2 = stlink_chipid_get_params_old(chipid); + p2 = stlink_chipid_get_params_old(chipid); #if 1 - if (params == NULL) { - params = p2; - } else if (memcmp (p2, params, sizeof (struct stlink_chipid_params) - sizeof (struct stlink_chipid_params *)) != 0) { - //fprintf (stderr, "Error, chipid params not identical\n"); - //return NULL; - fprintf(stderr, "---------- old ------------\n"); - dump_a_chip(stderr, p2); - fprintf(stderr, "---------- new ------------\n"); - dump_a_chip(stderr, params); - } + if (params == NULL) { + params = p2; + } else if (memcmp (p2, params, sizeof(struct stlink_chipid_params) - sizeof(struct stlink_chipid_params *)) != 0) { + // fprintf (stderr, "Error, chipid params not identical\n"); + // return NULL; + fprintf(stderr, "---------- old ------------\n"); + dump_a_chip(stderr, p2); + fprintf(stderr, "---------- new ------------\n"); + dump_a_chip(stderr, params); + } #endif - return(params); + return(params); } +void process_chipfile(char *fname) { + FILE *fp; + char *p, *pp, buf[1025]; + char word[64], value[64]; + struct stlink_chipid_params *ts; + int nc; + + // fprintf (stderr, "processing chipfile %s.\n", fname); + fp = fopen(fname, "r"); -void process_chipfile(char *fname) -{ - FILE *fp; - char *p, *pp, buf[1025]; - char word[64], value[64]; - struct stlink_chipid_params *ts; - int nc; + if (!fp) { + perror(fname); + return; + } - //fprintf (stderr, "processing chipfile %s.\n", fname); - fp = fopen(fname, "r"); - if (!fp) { - perror(fname); - return; - } + ts = calloc(sizeof(struct stlink_chipid_params), 1); - ts = calloc(sizeof (struct stlink_chipid_params), 1); - while (fgets(buf, 1024, fp) != NULL) { - for (p=buf;isspace (*p);p++); - if (!*p) continue; // we hit end-of-line wiht only whitespace - if (*p == '#') continue; // ignore comments. + while (fgets(buf, 1024, fp) != NULL) { + for (p = buf; isspace (*p); p++); - sscanf(p, "%s %s", word, value); - if (strcmp(word, "chip_id") == 0) { - if (sscanf(value, "%i", &ts->chip_id) < 1) - fprintf(stderr, "Failed to parse chip id\n"); - } else if (strcmp (word, "description") == 0) { - //ts->description = strdup (value); - buf[strlen(p)-1] = 0; // chomp newline - sscanf(p, "%*s %n", &nc); - ts->description = strdup(p+nc); - } else if (strcmp (word, "flash_type") == 0) { - if (sscanf(value, "%i", (int *) &ts->flash_type) < 1) - fprintf(stderr, "Failed to parse flash type\n"); - else if (ts->flash_type <= STLINK_FLASH_TYPE_UNKNOWN || ts->flash_type >= STLINK_FLASH_TYPE_MAX) - fprintf(stderr, "Unrecognized flash type\n"); - } else if (strcmp (word, "flash_size_reg") == 0) { - if (sscanf(value, "%i", &ts->flash_size_reg) < 1) - fprintf(stderr, "Failed to parse flash size reg\n"); - } else if (strcmp (word, "flash_pagesize") == 0) { - if (sscanf(value, "%i", &ts->flash_pagesize) < 1) - fprintf(stderr, "Failed to parse flash page size\n"); - } else if (strcmp (word, "sram_size") == 0) { - if (sscanf(value, "%i", &ts->sram_size) < 1) - fprintf(stderr, "Failed to parse SRAM size\n"); - } else if (strcmp (word, "bootrom_base") == 0) { - if (sscanf(value, "%i", &ts->bootrom_base) < 1) - fprintf(stderr, "Failed to parse BootROM base\n"); - } else if (strcmp (word, "bootrom_size") == 0) { - if (sscanf(value, "%i", &ts->bootrom_size) < 1) - fprintf(stderr, "Failed to parse BootROM size\n"); - } else if (strcmp (word, "option_base") == 0) { - if (sscanf(value, "%i", &ts->option_base) < 1) - fprintf(stderr, "Failed to parse option base\n"); - } else if (strcmp (word, "option_size") == 0) { - if (sscanf(value, "%i", &ts->option_size) < 1) - fprintf(stderr, "Failed to parse option size\n"); - } else if (strcmp (word, "flags") == 0) { - pp = strtok (p, " \t\n"); - while ((pp = strtok (NULL, " \t\n")) ) { - if (strcmp (pp, "none") == 0) ts->flags = 0; // not necessary: calloc did this already. - else if (strcmp (pp, "dualbank") == 0) ts->flags |= CHIP_F_HAS_DUAL_BANK; - else if (strcmp (pp, "swo") == 0) ts->flags |= CHIP_F_HAS_SWO_TRACING; - else fprintf (stderr, "Unknown flags word in %s: '%s'\n", - fname, pp); - } - sscanf(value, "%x", &ts->flags); - } else { - fprintf (stderr, "Unknown keyword in %s: %s\n", - fname, word); + if (!*p) { + continue; // we hit end-of-line wiht only whitespace + } + + if (*p == '#') { + continue; // ignore comments. + } + + sscanf(p, "%s %s", word, value); + + if (strcmp(word, "chip_id") == 0) { + if (sscanf(value, "%i", &ts->chip_id) < 1) { + fprintf(stderr, "Failed to parse chip id\n"); + } + } else if (strcmp (word, "description") == 0) { + // ts->description = strdup (value); + buf[strlen(p) - 1] = 0; // chomp newline + sscanf(p, "%*s %n", &nc); + ts->description = strdup(p + nc); + } else if (strcmp (word, "flash_type") == 0) { + if (sscanf(value, "%i", (int *)&ts->flash_type) < 1) { + fprintf(stderr, "Failed to parse flash type\n"); + } else if (ts->flash_type <= STLINK_FLASH_TYPE_UNKNOWN || ts->flash_type >= STLINK_FLASH_TYPE_MAX) { + fprintf(stderr, "Unrecognized flash type\n"); + } + } else if (strcmp (word, "flash_size_reg") == 0) { + if (sscanf(value, "%i", &ts->flash_size_reg) < 1) { + fprintf(stderr, "Failed to parse flash size reg\n"); + } + } else if (strcmp (word, "flash_pagesize") == 0) { + if (sscanf(value, "%i", &ts->flash_pagesize) < 1) { + fprintf(stderr, "Failed to parse flash page size\n"); + } + } else if (strcmp (word, "sram_size") == 0) { + if (sscanf(value, "%i", &ts->sram_size) < 1) { + fprintf(stderr, "Failed to parse SRAM size\n"); + } + } else if (strcmp (word, "bootrom_base") == 0) { + if (sscanf(value, "%i", &ts->bootrom_base) < 1) { + fprintf(stderr, "Failed to parse BootROM base\n"); + } + } else if (strcmp (word, "bootrom_size") == 0) { + if (sscanf(value, "%i", &ts->bootrom_size) < 1) { + fprintf(stderr, "Failed to parse BootROM size\n"); + } + } else if (strcmp (word, "option_base") == 0) { + if (sscanf(value, "%i", &ts->option_base) < 1) { + fprintf(stderr, "Failed to parse option base\n"); + } + } else if (strcmp (word, "option_size") == 0) { + if (sscanf(value, "%i", &ts->option_size) < 1) { + fprintf(stderr, "Failed to parse option size\n"); + } + } else if (strcmp (word, "flags") == 0) { + pp = strtok (p, " \t\n"); + + while ((pp = strtok (NULL, " \t\n"))) { + if (strcmp (pp, "none") == 0) { + ts->flags = 0; // not necessary: calloc did this already. + } else if (strcmp (pp, "dualbank") == 0) { + ts->flags |= CHIP_F_HAS_DUAL_BANK; + } else if (strcmp (pp, "swo") == 0) { + ts->flags |= CHIP_F_HAS_SWO_TRACING; + } else { + fprintf (stderr, "Unknown flags word in %s: '%s'\n", + fname, pp); + } + } + + sscanf(value, "%x", &ts->flags); + } else { + fprintf (stderr, "Unknown keyword in %s: %s\n", + fname, word); + } } - } - ts->next = devicelist; - devicelist = ts; + + ts->next = devicelist; + devicelist = ts; } -void dump_chips (void) -{ - struct stlink_chipid_params *ts; - char *p, buf[100]; - FILE *fp; +void dump_chips (void) { + struct stlink_chipid_params *ts; + char *p, buf[100]; + FILE *fp; - for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { - ts = &devices[n]; + for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { + ts = &devices[n]; - strcpy(buf, ts->description); - while ((p = strchr(buf, '/'))) // change slashes to underscore. - *p = '_'; - strcat(buf, ".chip"); - fp = fopen(buf, "w"); - fprintf(fp, "# Chip-ID file for %s\n", ts->description); - fprintf(fp, "#\n"); - fprintf(fp, "chip_id %x\n", ts->chip_id); - fprintf(fp, "description %s\n", ts->description); - fprintf(fp, "flash_type %x\n", ts->flash_type); - fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); - fprintf(fp, "sram_size %x\n", ts->sram_size); - fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); - fprintf(fp, "bootrom_size %x\n", ts->bootrom_size); - fprintf(fp, "option_base %x\n", ts->option_base); - fprintf(fp, "option_size %x\n", ts->option_size); - fprintf(fp, "flags %x\n\n", ts->flags); - fclose(fp); - } + strcpy(buf, ts->description); + + while ((p = strchr(buf, '/'))) // change slashes to underscore. + *p = '_'; + + strcat(buf, ".chip"); + fp = fopen(buf, "w"); + fprintf(fp, "# Chip-ID file for %s\n", ts->description); + fprintf(fp, "#\n"); + fprintf(fp, "chip_id %x\n", ts->chip_id); + fprintf(fp, "description %s\n", ts->description); + fprintf(fp, "flash_type %x\n", ts->flash_type); + fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); + fprintf(fp, "sram_size %x\n", ts->sram_size); + fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); + fprintf(fp, "bootrom_size %x\n", ts->bootrom_size); + fprintf(fp, "option_base %x\n", ts->option_base); + fprintf(fp, "option_size %x\n", ts->option_size); + fprintf(fp, "flags %x\n\n", ts->flags); + fclose(fp); + } } #if defined(STLINK_HAVE_DIRENT_H) #include -void init_chipids(char *dir_to_scan) -{ - DIR *d; - size_t nl; // namelen - struct dirent *dir; - if (!dir_to_scan) dir_to_scan = "./"; +void init_chipids(char *dir_to_scan) { + DIR *d; + size_t nl; // namelen + struct dirent *dir; + + if (!dir_to_scan) { + dir_to_scan = "./"; + } - devicelist = NULL; - //dump_chips (); - d = opendir(dir_to_scan); - if (d) { - while ((dir = readdir(d)) != NULL) { - nl = strlen(dir->d_name); - if (strcmp(dir->d_name + nl - 5, ".chip") == 0) { - char buf[1024]; - sprintf(buf, "%s/%s", dir_to_scan, dir->d_name); - process_chipfile(buf); - } + devicelist = NULL; + // dump_chips (); + d = opendir(dir_to_scan); + + if (d) { + while ((dir = readdir(d)) != NULL) { + nl = strlen(dir->d_name); + + if (strcmp(dir->d_name + nl - 5, ".chip") == 0) { + char buf[1024]; + sprintf(buf, "%s/%s", dir_to_scan, dir->d_name); + process_chipfile(buf); + } + } + + closedir(d); + } else { + perror (dir_to_scan); + return; // XXX } - closedir(d); - } else { - perror (dir_to_scan); - return; // XXX - } + #if 0 - { - struct stlink_chipid_params *p, *op; - int i; - p = devicelist; - for (i=0;i<5;i++, p = p->next) { - op = stlink_chipid_get_params_old (p->chip_id); - fprintf (stderr, "---------- old ------------\n"); - dump_a_chip (stderr, op); - fprintf (stderr, "---------- new ------------\n"); - dump_a_chip (stderr, p); + { + struct stlink_chipid_params *p, *op; + int i; + p = devicelist; + for (i = 0; i < 5; i++, p = p->next) { + op = stlink_chipid_get_params_old (p->chip_id); + fprintf (stderr, "---------- old ------------\n"); + dump_a_chip (stderr, op); + fprintf (stderr, "---------- new ------------\n"); + dump_a_chip (stderr, p); + + } } - } #endif } #endif //STLINK_HAVE_DIRENT_H @@ -1132,32 +1127,35 @@ void init_chipids(char *dir_to_scan) #if defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) #include #include -void init_chipids(char *dir_to_scan) -{ - HANDLE hFind = INVALID_HANDLE_VALUE; - WIN32_FIND_DATAA ffd; - char file_pattern[MAX_PATH] = {0}; - char filepath[MAX_PATH] = {0}; - StringCchCopyA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), dir_to_scan); - if (FAILED(StringCchCatA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), "\\*.chip"))) { - ELOG("Path to chips's dir too long.\n"); - return; - }; - hFind = FindFirstFileA(file_pattern, &ffd); - if (INVALID_HANDLE_VALUE == hFind) { - ELOG("Can't find any chip description file in %s.\n", file_pattern); - return; - } +void init_chipids(char *dir_to_scan) { + HANDLE hFind = INVALID_HANDLE_VALUE; + WIN32_FIND_DATAA ffd; + char file_pattern[MAX_PATH] = {0}; + char filepath[MAX_PATH] = {0}; + StringCchCopyA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), dir_to_scan); + + if (FAILED(StringCchCatA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), "\\*.chip"))) { + ELOG("Path to chips's dir too long.\n"); + return; + } + + ; + hFind = FindFirstFileA(file_pattern, &ffd); + + if (INVALID_HANDLE_VALUE == hFind) { + ELOG("Can't find any chip description file in %s.\n", file_pattern); + return; + } - do { - memset(filepath, 0, STLINK_ARRAY_SIZE(filepath)); - StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); - StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), "\\"); - StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), ffd.cFileName); - process_chipfile(filepath); - } while (FindNextFileA(hFind, &ffd) != 0); + do { + memset(filepath, 0, STLINK_ARRAY_SIZE(filepath)); + StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), "\\"); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), ffd.cFileName); + process_chipfile(filepath); + } while (FindNextFileA(hFind, &ffd) != 0); - FindClose(hFind); + FindClose(hFind); } #endif //defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) From e5152c45c3f9b27116be9d9d07250e6088d85c5a Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Fri, 13 Aug 2021 23:22:50 +0300 Subject: [PATCH 1236/1435] chipid.c: drop empty lines at end --- src/stlink-lib/chipid.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index dcf677909..42e4e92ae 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1158,7 +1158,3 @@ void init_chipids(char *dir_to_scan) { FindClose(hFind); } #endif //defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) - - - - From 03153d083c46d33295e5bd905d08c35472a21048 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sat, 14 Aug 2021 10:57:13 +0300 Subject: [PATCH 1237/1435] removed redundant array --- src/stlink-lib/chipid.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 42e4e92ae..d51a0edcb 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1130,28 +1130,26 @@ void init_chipids(char *dir_to_scan) { void init_chipids(char *dir_to_scan) { HANDLE hFind = INVALID_HANDLE_VALUE; WIN32_FIND_DATAA ffd; - char file_pattern[MAX_PATH] = {0}; char filepath[MAX_PATH] = {0}; - StringCchCopyA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), dir_to_scan); + StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); - if (FAILED(StringCchCatA(file_pattern, STLINK_ARRAY_SIZE(file_pattern), "\\*.chip"))) { + if (FAILED(StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), "\\*.chip"))) { ELOG("Path to chips's dir too long.\n"); return; } - ; - hFind = FindFirstFileA(file_pattern, &ffd); + hFind = FindFirstFileA(filepath, &ffd); if (INVALID_HANDLE_VALUE == hFind) { - ELOG("Can't find any chip description file in %s.\n", file_pattern); + ELOG("Can't find any chip description file in %s.\n", filepath); return; } do { memset(filepath, 0, STLINK_ARRAY_SIZE(filepath)); StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); - StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), "\\"); - StringCchCatA(filepath, STLINK_ARRAY_SIZE(file_pattern), ffd.cFileName); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), "\\"); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), ffd.cFileName); process_chipfile(filepath); } while (FindNextFileA(hFind, &ffd) != 0); From bef3321ea45e939003ef7802bdd2d3368f57b676 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sun, 15 Aug 2021 12:18:46 +0300 Subject: [PATCH 1238/1435] Fixes few warnings for msvc about type conversion with possible lost data. --- src/common.c | 28 ++++++++++++++-------------- src/st-flash/flash.c | 10 +++++----- src/st-util/gdb-server.c | 22 +++++++++++----------- src/stlink-lib/flash_loader.c | 14 +++++++------- 4 files changed, 37 insertions(+), 37 deletions(-) diff --git a/src/common.c b/src/common.c index af96b70b8..601fac0b6 100644 --- a/src/common.c +++ b/src/common.c @@ -424,8 +424,8 @@ void write_uint32(unsigned char *buf, uint32_t ui) { } void write_uint16(unsigned char *buf, uint16_t ui) { - buf[0] = ui; - buf[1] = ui >> 8; + buf[0] = (uint8_t)ui; + buf[1] = (uint8_t)(ui >> 8); } uint32_t read_uint32(const unsigned char *c, const int pt) { @@ -1274,7 +1274,7 @@ static void stop_wdg_in_debug(stlink_t *sl) { case STLINK_FLASH_TYPE_F1_XL: case STLINK_FLASH_TYPE_G4: dbgmcu_cr = STM32F0_DBGMCU_CR; - set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | + set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | (1 << STM32F0_DBGMCU_CR_WWDG_STOP); break; case STLINK_FLASH_TYPE_F4: @@ -1442,7 +1442,7 @@ void stlink_close(stlink_t *sl) { int stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); - if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN && + if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN && sl->core_stat != TARGET_RESET) { // stop debugging if the target has been identified stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); @@ -2253,7 +2253,7 @@ static int check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { aligned_size = (cmp_size + 4) & ~(4 - 1); } - stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); + stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { return (-1); @@ -2342,12 +2342,12 @@ int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, size += 2; } // round size if needed - stlink_write_mem32(sl, addr + (uint32_t)off, size); + stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); } if (length > len) { memcpy(sl->q_buf, data + len, length - len); - stlink_write_mem8(sl, addr + (uint32_t)len, length - len); + stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(length - len)); } error = 0; // success @@ -2409,12 +2409,12 @@ int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { size += 2; } // round size if needed - stlink_write_mem32(sl, addr + (uint32_t)off, size); + stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); } if (mf.len > len) { memcpy(sl->q_buf, mf.base + len, mf.len - len); - stlink_write_mem8(sl, addr + (uint32_t)len, mf.len - len); + stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(mf.len - len)); } // check the file has been written @@ -2462,7 +2462,7 @@ static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, aligned_size = (cmp_size + 4) & ~(4 - 1); } - stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); + stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); if (!fn(fn_arg, sl->q_buf, aligned_size)) { goto on_error; @@ -2641,12 +2641,12 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, if (chunk) { memcpy(sl->q_buf, buf, chunk); - ret = stlink_write_mem32(sl, fl->buf_addr, chunk); + ret = stlink_write_mem32(sl, fl->buf_addr, (uint16_t)chunk); } if (rem && !ret) { memcpy(sl->q_buf, buf + chunk, rem); - ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, rem); + ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, (uint16_t)rem); } return (ret); @@ -3059,7 +3059,7 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, aligned_size = (cmp_size + 4) & ~(4 - 1); } - stlink_read_mem32(sl, address + (uint32_t)off, aligned_size); + stlink_read_mem32(sl, address + (uint32_t)off, (uint16_t)aligned_size); if (memcmp(sl->q_buf, data + off, cmp_size)) { ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); @@ -3105,7 +3105,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, for (off = 0; off < pagesize && !ret; off += 64) { size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; memcpy(sl->q_buf, base + count * pagesize + off, chunk); - ret = stlink_write_mem32(sl, addr + count * pagesize + off, chunk); + ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); } } diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 814c981b4..ef184239f 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -152,15 +152,15 @@ int main(int ac, char** av) { } } else if (o.area == FLASH_OPTCR) { DLOG("@@@@ Write %d (%0#10x) to option control register\n", o.val, o.val); - + err = stlink_write_option_control_register32(sl, o.val); } else if (o.area == FLASH_OPTCR1) { DLOG("@@@@ Write %d (%0#10x) to option control register 1\n", o.val, o.val); - + err = stlink_write_option_control_register1_32(sl, o.val); } else if (o.area == FLASH_OPTION_BYTES_BOOT_ADD) { DLOG("@@@@ Write %d (%0#10x) to option bytes boot address\n", o.val, o.val); - + err = stlink_write_option_bytes_boot_add32(sl, o.val); } else { err = -1; @@ -194,9 +194,9 @@ int main(int ac, char** av) { goto on_error; } } else if (o.area == FLASH_OPTION_BYTES) { - uint8_t remaining_option_length = sl->option_size / 4; + size_t remaining_option_length = sl->option_size / 4; DLOG("@@@@ Read %d (%#x) option bytes from %#10x\n", remaining_option_length, remaining_option_length, sl->option_base); - + if (NULL != o.filename) { if (0 == o.size) { o.size = sl->option_size; diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 653c7bcec..a651014c0 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -124,7 +124,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { " -n, --no-reset, --hot-plug\n" "\t\t\tDo not reset board on connection.\n" " -u, --connect-under-reset\n" - "\t\t\tConnect to the board before executing any instructions.\n" + "\t\t\tConnect to the board before executing any instructions.\n" " -F 1800k, --freq=1M\n" "\t\t\tSet the frequency of the SWD/JTAG interface.\n" " --semihosting\n" @@ -167,7 +167,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { st->listen_port = q; break; - + case 'm': st->persistent = true; break; @@ -586,7 +586,7 @@ char* make_memory_map(stlink_t *sl) { } else if (sl->chip_id == STLINK_CHIPID_STM32_H72x) { snprintf(map, sz, memory_map_template_H72x3x, (unsigned int)sl->flash_size, - (unsigned int)sl->flash_pgsz); + (unsigned int)sl->flash_pgsz); } else { snprintf(map, sz, memory_map_template, (unsigned int)sl->flash_size, @@ -726,7 +726,7 @@ static void init_code_breakpoints(stlink_t *sl) { // IHI0029D, p. 48, Lock Access Register stlink_write_debug32(sl, STLINK_REG_CM7_FP_LAR, STLINK_REG_CM7_FP_LAR_KEY); } - + for (int i = 0; i < code_break_num; i++) { code_breaks[i].type = 0; stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(i), 0); @@ -757,7 +757,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { type = CODE_BREAK_REMAP; fpb_addr = addr; } - + int id = -1; for (int i = 0; i < code_break_num; i++) if (fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { @@ -778,7 +778,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { bp->type |= type; else bp->type &= ~type; - + // DDI0403E, p. 759, FP_COMPn register description mask = ((bp->type&0x03) << 30) | bp->addr | 1; @@ -936,7 +936,7 @@ struct cache_level_desc { struct cache_desc_t { unsigned used; - + // minimal line size in bytes unsigned int dminline; unsigned int iminline; @@ -988,7 +988,7 @@ static void init_cache (stlink_t *sl) { cache_desc.used = 1; cache_desc.dminline = 4 << ((ctr >> 16) & 0x0f); cache_desc.iminline = 4 << (ctr & 0x0f); - + stlink_read_debug32(sl, STLINK_REG_CM7_CLIDR, &clidr); cache_desc.louu = (clidr >> 27) & 7; @@ -1698,7 +1698,7 @@ int serve(stlink_t *sl, st_state_t *st) { for (unsigned int i = 0; i < align_count; i++) { char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; - uint8_t byte = strtoul(hextmp, NULL, 16); + uint8_t byte = (uint8_t)strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; } @@ -1714,7 +1714,7 @@ int serve(stlink_t *sl, st_state_t *st) { for (unsigned int i = 0; i < aligned_count; i++) { char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; - uint8_t byte = strtoul(hextmp, NULL, 16); + uint8_t byte = (uint8_t)strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; } @@ -1728,7 +1728,7 @@ int serve(stlink_t *sl, st_state_t *st) { if (count) { for (unsigned int i = 0; i < count; i++) { char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; - uint8_t byte = strtoul(hextmp, NULL, 16); + uint8_t byte = (uint8_t)strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; } diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index d2bf32563..f683c4d65 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -17,8 +17,8 @@ /* !!! * !!! DO NOT MODIFY FLASH LOADERS DIRECTLY! * !!! - * - * Edit assembly files in the '/flashloaders' instead. The sizes of binary + * + * Edit assembly files in the '/flashloaders' instead. The sizes of binary * flash loaders must be aligned by 4 (it's written by stlink_write_mem32) */ @@ -310,7 +310,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* } memcpy(sl->q_buf, loader_code, loader_size); - int ret = stlink_write_mem32(sl, sl->sram_base, loader_size); + int ret = stlink_write_mem32(sl, sl->sram_base, (uint16_t)loader_size); if (ret) { return(ret); } @@ -382,10 +382,10 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe // check written byte count stlink_read_reg(sl, 2, &rr); - /* The chunk size for loading is not rounded. The flash loader - * subtracts the size of the written block (1-8 bytes) from - * the remaining size each time. A negative value may mean that - * several bytes garbage has been written due to the unaligned + /* The chunk size for loading is not rounded. The flash loader + * subtracts the size of the written block (1-8 bytes) from + * the remaining size each time. A negative value may mean that + * several bytes garbage has been written due to the unaligned * firmware size. */ if ((int32_t)rr.r[2] > 0 || (int32_t)rr.r[2] < -7) { From 698b97bbddd4505c3fa4e0af366484e29b2739e4 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Sun, 15 Aug 2021 12:30:09 +0300 Subject: [PATCH 1239/1435] fixes printf format formating --- src/st-flash/flash.c | 5 ++++- src/stlink-lib/flash_loader.c | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index ef184239f..51702b683 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -195,7 +195,10 @@ int main(int ac, char** av) { } } else if (o.area == FLASH_OPTION_BYTES) { size_t remaining_option_length = sl->option_size / 4; - DLOG("@@@@ Read %d (%#x) option bytes from %#10x\n", remaining_option_length, remaining_option_length, sl->option_base); + DLOG("@@@@ Read %u (%#x) option bytes from %#10x\n", + (unsigned)remaining_option_length, + (unsigned)remaining_option_length, + sl->option_base); if (NULL != o.filename) { if (0 == o.size) { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index f683c4d65..7076a2cfa 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -280,7 +280,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* } else if (sl->core_id == STM32F7_CORE_ID || sl->chip_id == STLINK_CHIPID_STM32_F7 || sl->chip_id == STLINK_CHIPID_STM32_F76xxx || - sl->chip_id == STLINK_CHIPID_STM32_F72xxx) { + sl->chip_id == STLINK_CHIPID_STM32_F72xxx) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, From e768f737cd9f97097370cedbc3061aaf606bd700 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 15 Aug 2021 14:10:49 +0100 Subject: [PATCH 1240/1435] Bump Standards-Version to 4.5.1, no changes --- debian/control | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian/control b/debian/control index 3ac6af91f..e28f7c5b5 100644 --- a/debian/control +++ b/debian/control @@ -2,7 +2,7 @@ Source: stlink Priority: optional Maintainer: Luca Boccassi Build-Depends: debhelper-compat (= 12), cmake (>= 3.4.2), libusb-1.0-0-dev, libgtk-3-dev -Standards-Version: 4.5.0 +Standards-Version: 4.5.1 Rules-Requires-Root: no Section: electronics Homepage: https://github.com/stlink-org/stlink From 1fab90289ffabcda7c3123ee7106cc032c2c619e Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 15 Aug 2021 14:11:09 +0100 Subject: [PATCH 1241/1435] Bump debhelper-compat to 13, no changes --- debian/control | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/debian/control b/debian/control index e28f7c5b5..faed0302c 100644 --- a/debian/control +++ b/debian/control @@ -1,7 +1,7 @@ Source: stlink Priority: optional Maintainer: Luca Boccassi -Build-Depends: debhelper-compat (= 12), cmake (>= 3.4.2), libusb-1.0-0-dev, libgtk-3-dev +Build-Depends: debhelper-compat (= 13), cmake (>= 3.4.2), libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.5.1 Rules-Requires-Root: no Section: electronics From 607d1d3b854b0dc3fb84455f6efa21dffc578fe4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 15 Aug 2021 15:14:45 +0200 Subject: [PATCH 1242/1435] General Project Update - Updated CHANGELOG.md - Updated list of contributors --- CHANGELOG.md | 18 +++++++++++++++++- contributors.txt | 1 + 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index b711f3890..9bbb41a98 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -12,15 +12,31 @@ Features: - Support for writing option bytes on STM32F0/F1/F3 ([#346](https://github.com/stlink-org/stlink/pull/346), [#458](https://github.com/stlink-org/stlink/pull/458), [#808](https://github.com/stlink-org/stlink/pull/808), [#1084](https://github.com/stlink-org/stlink/pull/1084), [#1112](https://github.com/stlink-org/stlink/pull/1112)) - Added chip-IDs for STM32G0B0/G0B1/G0C1/G050/G051/G061 ([#1140](https://github.com/stlink-org/stlink/pull/1140)) - Added option byte info for STM32F411XX ([#1141](https://github.com/stlink-org/stlink/pull/1141)) +- Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) +- [STM32H72X/3X]: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) +- Added support for STM32WLEx ([#1173](https://github.com/stlink-org/stlink/pull/1173)) Updates & changes: +- [refactoring] Moved chip-specific parameters into separate files ([#237](https://github.com/stlink-org/stlink/pull/237), [#1129](https://github.com/stlink-org/stlink/pull/1129)) - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation ([#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) +- Drop execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) +- Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) +- Removed redundant array ([#1178](https://github.com/stlink-org/stlink/pull/1178)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) +- Fixed clearance of the H7 dual bank flag ([#1146](https://github.com/stlink-org/stlink/pull/1146), [#1147](https://github.com/stlink-org/stlink/pull/1147)) +- Fix for 'libusb_devices were leaked' when no ST-LINK programmer was found ([#1150](https://github.com/stlink-org/stlink/pull/1150)) +- Set of fixes and improvements ([#1154](https://github.com/stlink-org/stlink/pull/1154)) +- Removed limit check for WRITEMEM_32BIT ([#1157](https://github.com/stlink-org/stlink/pull/1157)) +- Fixed get_stm32l0_flash_base address for STM32L152RE ([#1161](https://github.com/stlink-org/stlink/pull/1161), [#1162](https://github.com/stlink-org/stlink/pull/1162)) +- Fixed segfault if chip was not found in chip config files ([#1138](https://github.com/stlink-org/stlink/pull/1138), [#1163](https://github.com/stlink-org/stlink/pull/1163), [#1165](https://github.com/stlink-org/stlink/pull/1165), [#1166](https://github.com/stlink-org/stlink/pull/1166), [#1170](https://github.com/stlink-org/stlink/pull/1170)) +- Fixed parsing hex numbers in chip config files ([#1169](https://github.com/stlink-org/stlink/pull/1169)) +- Corrected flash_pagesize to use hex format ([#1172](https://github.com/stlink-org/stlink/pull/1172)) +- Fixed compilation for MSVC ([#1176](https://github.com/stlink-org/stlink/pull/1176)) # v1.7.0 @@ -65,6 +81,7 @@ Fixes: - Improvements and fixes of the flash loaders, unification of the reset function ([#244](https://github.com/stlink-org/stlink/pull/244), [#382](https://github.com/stlink-org/stlink/pull/382), [#705](https://github.com/stlink-org/stlink/pull/705), [#724](https://github.com/stlink-org/stlink/pull/724), [#980](https://github.com/stlink-org/stlink/pull/980), [#995](https://github.com/stlink-org/stlink/pull/995), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1115](https://github.com/stlink-org/stlink/pull/1115), [#1117](https://github.com/stlink-org/stlink/pull/1117), [#1122](https://github.com/stlink-org/stlink/pull/1122), [#1124](https://github.com/stlink-org/stlink/pull/1124)) - Flash loader rework ([#356](https://github.com/stlink-org/stlink/pull/356), [#556](https://github.com/stlink-org/stlink/pull/556), [#593](https://github.com/stlink-org/stlink/pull/593), [#597](https://github.com/stlink-org/stlink/pull/597), [#607](https://github.com/stlink-org/stlink/pull/607), [#612](https://github.com/stlink-org/stlink/pull/612), [#638](https://github.com/stlink-org/stlink/pull/638), [#661](https://github.com/stlink-org/stlink/pull/661), [#690](https://github.com/stlink-org/stlink/pull/690), [#724](https://github.com/stlink-org/stlink/pull/724), [#807](https://github.com/stlink-org/stlink/pull/807), [#817](https://github.com/stlink-org/stlink/pull/817), [#818](https://github.com/stlink-org/stlink/pull/818), [#854](https://github.com/stlink-org/stlink/pull/854), [#868](https://github.com/stlink-org/stlink/pull/868), [#967](https://github.com/stlink-org/stlink/pull/967), [#979](https://github.com/stlink-org/stlink/pull/979), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1043](https://github.com/stlink-org/stlink/pull/1043), [#1054](https://github.com/stlink-org/stlink/pull/1054), [#1092](https://github.com/stlink-org/stlink/pull/1092), [#1105](https://github.com/stlink-org/stlink/pull/1105), [#1113](https://github.com/stlink-org/stlink/pull/1113)) - Fixed old DFU serial number for STLINK programmers ([#417](https://github.com/stlink-org/stlink/pull/417), [#494](https://github.com/stlink-org/stlink/pull/494), [#1106](https://github.com/stlink-org/stlink/pull/1106), [#1121](https://github.com/stlink-org/stlink/pull/1121)) +- Improvements for Chip_ID read ([#620](https://github.com/stlink-org/stlink/pull/620), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1120](https://github.com/stlink-org/stlink/pull/1120)) - Use vl flashloader for all STM32F1 series ([#724](https://github.com/stlink-org/stlink/pull/724), [#769](https://github.com/stlink-org/stlink/pull/769), [#1041](https://github.com/stlink-org/stlink/pull/1041), [#1044](https://github.com/stlink-org/stlink/pull/1044)) - [regression] Changed timeout on flash write ([#787](https://github.com/stlink-org/stlink/pull/787), [#981](https://github.com/stlink-org/stlink/pull/981), [#987](https://github.com/stlink-org/stlink/pull/987)) - cmake compile failure with external `CMAKE_MODULE_PATH` set ([#962](https://github.com/stlink-org/stlink/pull/962)) @@ -89,7 +106,6 @@ Fixes: - [doc] Corrected spelling mistake in bug report template ([#1103](https://github.com/stlink-org/stlink/pull/1103)) - Fixed STM32WB55 reading DEBUG IDCODE from the wrong address ([#1100](https://github.com/stlink-org/stlink/pull/1100), [#1101](https://github.com/stlink-org/stlink/pull/1101)) - Applied missing changes to tests ([#1119](https://github.com/stlink-org/stlink/pull/1119)) -- Improvements for Chip_ID read ([#1008](https://github.com/stlink-org/stlink/pull/1008), [#1120](https://github.com/stlink-org/stlink/pull/1120)) - Fixed reading of chip ID on Cortex-M0+ core ([#1017](https://github.com/stlink-org/stlink/pull/1017), [#1125](https://github.com/stlink-org/stlink/pull/1125), [#1126](https://github.com/stlink-org/stlink/pull/1126), [#1133](https://github.com/stlink-org/stlink/pull/1133)) # v1.6.1 diff --git a/contributors.txt b/contributors.txt index e7fc0f601..bcaa0b538 100644 --- a/contributors.txt +++ b/contributors.txt @@ -46,6 +46,7 @@ Georg von Zengen Giuseppe Barba Greg Alexander [galexander1] Greg Meiste [meisteg] +Grzegorz Szymaszek [gszy] Guillaume Revaillot [grevaillot] Hakkavélin Halt Hammerzeit From 30396b2803697617e2087c4f4b2a66187b58902c Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 15 Aug 2021 14:31:09 +0100 Subject: [PATCH 1243/1435] Drop guipath.patch and refresh cross.patch for v1.7.0 --- debian/patches/cross.patch | 12 ++++++------ debian/patches/guipath.patch | 11 ----------- debian/patches/series | 1 - 3 files changed, 6 insertions(+), 18 deletions(-) delete mode 100644 debian/patches/guipath.patch diff --git a/debian/patches/cross.patch b/debian/patches/cross.patch index 8d927ba4b..d55e9f9d2 100644 --- a/debian/patches/cross.patch +++ b/debian/patches/cross.patch @@ -1,11 +1,11 @@ ---- stlink-1.6.1+ds.orig/CMakeLists.txt -+++ stlink-1.6.1+ds/CMakeLists.txt -@@ -48,7 +48,7 @@ - find_package(libusb REQUIRED) +--- a/src/stlink-gui/CMakeLists.txt ++++ b/src/stlink-gui/CMakeLists.txt +@@ -2,7 +2,7 @@ + # Build GUI + ### - ## Package configuration (pkg-config) on unix-based systems -if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) +if (NOT WIN32) - #add_subdirectory(cmake/pkgconfig) find_package(PkgConfig) pkg_check_modules(GTK3 gtk+-3.0) + diff --git a/debian/patches/guipath.patch b/debian/patches/guipath.patch deleted file mode 100644 index d3effc92b..000000000 --- a/debian/patches/guipath.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/src/stlink-gui/CMakeLists.txt -+++ b/src/stlink-gui/CMakeLists.txt -@@ -32,7 +32,7 @@ - add_executable(stlink-gui ${GUI_SOURCES}) - install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_BINDIR}) - set_target_properties(stlink-gui PROPERTIES -- COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_PREFIX}/bin") -+ COMPILE_DEFINITIONS STLINK_UI_DIR="/usr/share/stlink") - target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) - install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_BINDIR}) - diff --git a/debian/patches/series b/debian/patches/series index b3c28e7e1..def274a02 100644 --- a/debian/patches/series +++ b/debian/patches/series @@ -1,2 +1 @@ -guipath.patch cross.patch From 78b510ee3da0087033529956f5bc2d81359bc121 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 15 Aug 2021 14:38:00 +0100 Subject: [PATCH 1244/1435] Update install files, paths have been fixed upstream --- debian/stlink-gui.install | 6 +++--- debian/stlink-tools.manpages | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/debian/stlink-gui.install b/debian/stlink-gui.install index 5620a25e5..1474d7f8c 100644 --- a/debian/stlink-gui.install +++ b/debian/stlink-gui.install @@ -1,4 +1,4 @@ /usr/bin/stlink-gui -/usr/bin/stlink-gui.ui /usr/share/stlink/ -/usr/share/stlink/applications/stlink-gui.desktop /usr/share/applications/ -/usr/share/stlink/icons/hicolor/scalable/apps/stlink-gui.svg /usr/share/icons/hicolor/scalable/apps/stlink-gui.svg +/usr/share/applications/stlink-gui.desktop +/usr/share/icons/hicolor/scalable/apps/stlink-gui.svg +/usr/share/stlink/stlink-gui.ui diff --git a/debian/stlink-tools.manpages b/debian/stlink-tools.manpages index 049509abe..68112ddf2 100644 --- a/debian/stlink-tools.manpages +++ b/debian/stlink-tools.manpages @@ -1,3 +1,3 @@ -usr/share/stlink/man/man1/st-flash.1 -usr/share/stlink/man/man1/st-info.1 -usr/share/stlink/man/man1/st-util.1 +usr/share/man/man1/st-flash.1 +usr/share/man/man1/st-info.1 +usr/share/man/man1/st-util.1 From 9e3fac499e4a7c854f3cb691d29d10f7f8091eb5 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 15 Aug 2021 14:43:43 +0100 Subject: [PATCH 1245/1435] Update symbols file for 1.7.0 --- debian/libstlink1.symbols | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/debian/libstlink1.symbols b/debian/libstlink1.symbols index 159f27d0f..bc4e62f0e 100644 --- a/debian/libstlink1.symbols +++ b/debian/libstlink1.symbols @@ -29,6 +29,8 @@ libstlink.so.1 libstlink1 #MINVER# _stlink_usb_close@Base 1.5.0 _stlink_usb_core_id@Base 1.5.0 _stlink_usb_current_mode@Base 1.5.0 + _stlink_usb_disable_trace@Base 1.7.0 + _stlink_usb_enable_trace@Base 1.7.0 _stlink_usb_enter_swd_mode@Base 1.5.0 _stlink_usb_exit_debug_mode@Base 1.5.0 _stlink_usb_exit_dfu_mode@Base 1.5.0 @@ -40,6 +42,7 @@ libstlink.so.1 libstlink1 #MINVER# _stlink_usb_read_debug32@Base 1.5.0 _stlink_usb_read_mem32@Base 1.5.0 _stlink_usb_read_reg@Base 1.5.0 + _stlink_usb_read_trace@Base 1.7.0 _stlink_usb_read_unsupported_reg@Base 1.5.0 _stlink_usb_reset@Base 1.5.0 _stlink_usb_run@Base 1.5.0 @@ -54,10 +57,12 @@ libstlink.so.1 libstlink1 #MINVER# _stlink_usb_write_mem8@Base 1.5.0 _stlink_usb_write_reg@Base 1.5.0 _stlink_usb_write_unsupported_reg@Base 1.5.0 + arg_parse_freq@Base 1.7.0 calculate_F4_sectornum@Base 1.5.0 calculate_F7_sectornum@Base 1.5.0 + calculate_H7_sectornum@Base 1.7.0 calculate_L4_page@Base 1.5.0 - is_bigendian@Base 1.5.0 +#MISSING: 1.7.0# is_bigendian@Base 1.5.0 read_uint16@Base 1.5.0 read_uint32@Base 1.5.0 send_recv@Base 1.5.0 @@ -81,6 +86,9 @@ libstlink.so.1 libstlink1 #MINVER# stlink_flash_loader_init@Base 1.5.0 stlink_flash_loader_run@Base 1.5.0 stlink_flash_loader_write_to_sram@Base 1.5.0 + stlink_flashloader_start@Base 1.7.0 + stlink_flashloader_stop@Base 1.7.0 + stlink_flashloader_write@Base 1.7.0 stlink_force_debug@Base 1.5.0 stlink_fread@Base 1.5.0 stlink_fwrite_flash@Base 1.5.0 @@ -105,20 +113,36 @@ libstlink.so.1 libstlink1 #MINVER# stlink_read_mem32@Base 1.5.0 stlink_read_option_bytes32@Base 1.6.1 stlink_read_option_bytes_Gx@Base 1.6.1 + stlink_read_option_bytes_boot_add32@Base 1.7.0 + stlink_read_option_bytes_boot_add_f7@Base 1.7.0 stlink_read_option_bytes_f2@Base 1.6.0 stlink_read_option_bytes_f4@Base 1.6.0 + stlink_read_option_bytes_f7@Base 1.7.0 stlink_read_option_bytes_generic@Base 1.6.1 + stlink_read_option_control_register1_32@Base 1.7.0 + stlink_read_option_control_register1_f7@Base 1.7.0 + stlink_read_option_control_register32@Base 1.7.0 + stlink_read_option_control_register_Gx@Base 1.7.0 + stlink_read_option_control_register_f2@Base 1.7.0 + stlink_read_option_control_register_f4@Base 1.7.0 + stlink_read_option_control_register_f7@Base 1.7.0 stlink_read_reg@Base 1.5.0 stlink_read_unsupported_reg@Base 1.5.0 stlink_reset@Base 1.5.0 stlink_run@Base 1.5.0 stlink_run_at@Base 1.5.0 + stlink_serial@Base 1.7.0 stlink_set_hw_bp@Base 1.5.0 stlink_set_swdclk@Base 1.5.0 + stlink_soft_reset@Base 1.7.0 stlink_stat@Base 1.5.0 stlink_status@Base 1.5.0 stlink_step@Base 1.5.0 + stlink_target_connect@Base 1.7.0 stlink_target_voltage@Base 1.5.0 + stlink_trace_disable@Base 1.7.0 + stlink_trace_enable@Base 1.7.0 + stlink_trace_read@Base 1.7.0 stlink_v1_open@Base 1.5.0 stlink_v1_open_inner@Base 1.5.0 stlink_verify_write_flash@Base 1.5.0 @@ -130,9 +154,13 @@ libstlink.so.1 libstlink1 #MINVER# stlink_write_mem8@Base 1.5.0 stlink_write_option_bytes32@Base 1.6.1 stlink_write_option_bytes@Base 1.6.0 + stlink_write_option_bytes_boot_add32@Base 1.7.0 + stlink_write_option_control_register1_32@Base 1.7.0 + stlink_write_option_control_register32@Base 1.7.0 stlink_write_reg@Base 1.5.0 stlink_write_unsupported_reg@Base 1.5.0 stm32l1_write_half_pages@Base 1.5.0 + time_ms@Base 1.7.0 ugly_init@Base 1.5.0 ugly_libusb_log_level@Base 1.6.1 ugly_log@Base 1.5.0 From 4f40a424567e7f114753ac3ef56ba7e8b4d644a0 Mon Sep 17 00:00:00 2001 From: Luca Boccassi Date: Sun, 15 Aug 2021 14:24:44 +0100 Subject: [PATCH 1246/1435] Update changelog for 1.7.0+ds-1 --- debian/changelog | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/debian/changelog b/debian/changelog index ac046a5f4..7a7b4e54a 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,13 @@ +stlink (1.7.0+ds-1) unstable; urgency=medium + + * Merge tag 'v1.7.0' into debian. (Closes: #984356) + * Bump Standards-Version to 4.5.1, no changes. + * Bump debhelper-compat to 13, no changes. + * Update install files, paths have been fixed upstream. + * Update symbols file for 1.7.0. + + -- Luca Boccassi Sun, 15 Aug 2021 14:23:25 +0100 + stlink (1.6.1+ds-3) unstable; urgency=medium * Add cross.patch to fix cross-compilation. Thanks Helmut! (Closes: From e662da00ca294c874655c65cffae3edde97343e5 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 22 Aug 2021 12:44:01 +0200 Subject: [PATCH 1247/1435] Updated debian pkg config for distribution --- debian/.gitignore | 4 +- debian/control | 36 +++-- debian/copyright | 128 +----------------- debian/patches/cross.patch | 11 -- debian/patches/series | 1 - ...ink-dev.install => stlink-lib-dev.install} | 0 ...{libstlink1.install => stlink-lib.install} | 0 ...{libstlink1.symbols => stlink-lib.symbols} | 2 +- debian/stlink.pc.in | 2 +- src/stlink-gui/CMakeLists.txt | 2 +- 10 files changed, 28 insertions(+), 158 deletions(-) delete mode 100644 debian/patches/cross.patch delete mode 100644 debian/patches/series rename debian/{libstlink-dev.install => stlink-lib-dev.install} (100%) rename debian/{libstlink1.install => stlink-lib.install} (100%) rename debian/{libstlink1.symbols => stlink-lib.symbols} (99%) diff --git a/debian/.gitignore b/debian/.gitignore index 7624d1c9b..6531851ff 100644 --- a/debian/.gitignore +++ b/debian/.gitignore @@ -1,8 +1,8 @@ .debhelper -files -debhelper-build-stamp *.log *.substvars +debhelper-build-stamp +files libstlink-dev libstlink stlink-gui diff --git a/debian/control b/debian/control index faed0302c..c3e654ec5 100644 --- a/debian/control +++ b/debian/control @@ -9,44 +9,40 @@ Homepage: https://github.com/stlink-org/stlink Vcs-Git: https://github.com/bluca/stlink.git -b debian Vcs-Browser: https://github.com/bluca/stlink -Package: libstlink-dev +Package: stlink-lib-dev Section: libdevel Architecture: linux-any Multi-Arch: same -Depends: libstlink1 (= ${binary:Version}), ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Depends: stlink-lib (= ${binary:Version}), ${misc:Depends} +Replaces: libstlink-dev (<< 1.7.0+ds-1) +Breaks: libstlink-dev (<< 1.7.0+ds-1) +Description: Open source version of the STMicroelectronics STLINK Tools . - This package contains the development files for stlink. + This package contains development files for stlink. -Package: libstlink1 +Package: stlink-lib Section: libs Architecture: linux-any Multi-Arch: same Depends: ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Replaces: libstlink1 (<< 1.7.0+ds-1) +Breaks: libstlink1 (<< 1.7.0+ds-1) +Description: Open source version of the STMicroelectronics STLINK Tools . This package contains the shared library for stlink. Package: stlink-tools Architecture: linux-any -Depends: libstlink1 (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Depends: stlink-lib (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} +Description: Open source version of the STMicroelectronics STLINK Tools . - This package contains commandline utilities for stlink, and modprobe and - udev rules. + This package contains commandline utilities for stlink, as well as modprobe + and udev rules. Package: stlink-gui Architecture: linux-any -Depends: libstlink1 (= ${binary:Version}), stlink-tools (= ${binary:Version}), +Depends: stlink-lib (= ${binary:Version}), stlink-tools (= ${binary:Version}), ${shlibs:Depends}, ${misc:Depends} -Description: OpenSource ST-Link tools replacement. - Flashing tools for STMicroelectronics STM32VL and STM32L. The transport layers - STLINKv1 and STLINKv2 are supported. +Description: Open source version of the STMicroelectronics STLINK Tools . This package contains a GUI tool for stlink. diff --git a/debian/copyright b/debian/copyright index 1a0febd9c..b7f9c3106 100644 --- a/debian/copyright +++ b/debian/copyright @@ -1,132 +1,18 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink -Upstream-Contact: Andrew 'Necromant' Andrianov +Upstream-Contact: Nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Source: https://github.com/stlink-org/stlink Comment: Upstream tarball has been repackaged to remove binary OSX kernel drivers that are of unknown license and of no use to Debian. Files-Excluded: stlinkv1_macos_driver Files: * -Copyright: 2011-2018 agpanarin - 2011-2018 Alexey Cherevatenko - 2011-2018 Anatoli - 2011-2018 Andrea Mucignat - 2011-2018 Andrew 'Necromant' Andrianov - 2011-2018 Andrey Yurovsky - 2011-2018 Andy Isaacson - 2011-2018 Áron RADICS - 2011-2018 A Sheaff - 2011-2018 Björn Hauffe - 2011-2018 bob - 2011-2018 Breton M. Saunders - 2011-2018 Bruno Dal Bo - 2011-2018 Burns - 2011-2018 Chris Dew - 2011-2018 Chris Hiszpanski - 2011-2018 Chris Li - 2011-2018 Chris Samuelson - 2011-2018 Christophe Levantis - 2011-2018 Craig Lilley - 2011-2018 dandev37 - 2011-2018 Dan Hepler - 2011-2018 Daniel Campoverde [alx741] - 2011-2018 Daniel O'Connor - 2011-2018 Dave Flogeras - 2011-2018 Dave Murphy - 2011-2018 Dave Vandervies - 2011-2018 Denis Fokin - 2011-2018 Denis Osterland - 2011-2018 Dmitry Bravikov - 2011-2018 Efe Can İçöz - 2011-2018 Ethan Zonca - 2011-2018 Fabien Chouteau - 2011-2018 Fabien Le Mentec - 2011-2018 fhars - 2011-2018 Friedrich Beckmann - 2011-2018 Geoffrey Brown - 2011-2018 George Talusan - 2011-2018 Georg von Zengen - 2011-2018 giuseppe barba - 2011-2018 Greg Alexander - 2011-2018 Greg Meiste - 2011-2018 Hakkavélin - 2011-2018 htk - 2011-2018 Ian Griffiths <6thimage@gmail.com> - 2011-2018 Jack Peel - 2011-2018 Jakub Tyszkowski - 2011-2018 Jan Sarenik - 2011-2018 Jean-Luc Béchennec - 2011-2018 Jean-Marie Lemetayer - 2011-2018 Jeff Kent - 2011-2018 Jeffrey Nelson - 2011-2018 Jens Hoffmann - 2011-2018 Jerome Lambourg - 2011-2018 Jerry Jacobs - 2011-2018 Jim Paris - 2011-2018 Jiří Netolický - 2011-2018 jnosky - 2011-2018 jnosky - 2011-2018 JohannesTaelman - 2011-2018 Jonas Danielsson - 2011-2018 Jonas Norling - 2011-2018 Josh Bialkowski - 2011-2018 Karl Palsson - 2011-2018 kevin - 2011-2018 Kyle Manna - 2011-2018 Lari Lehtomäki - 2011-2018 le mentec fabien - 2011-2018 Martin Nowak - 2011-2018 Matteo Collina - 2011-2018 Max Chen - 2011-2018 Maxime Coquelin - 2011-2018 Maxime Vincent - 2011-2018 Michael Pratt - 2011-2018 Michael Sparmann - 2011-2018 Mike Szczys - 2011-2018 mlundinse - 2011-2018 mux - 2011-2018 Ned Konz - 2011-2018 Nic McDonald - 2011-2018 Nicolas Schodet - 2011-2018 Nikolay - 2011-2018 nullsub - 2011-2018 Olivier Croquette - 2011-2018 Olivier Gay - 2011-2018 Onno Kortmann - 2011-2018 orangeudav - 2011-2018 Pavel Kirienko - 2011-2018 Pekka Nikander - 2011-2018 Pete - 2011-2018 Peter Zotov - 2011-2018 Petteri Aimonen - 2011-2018 Piotr Haber - 2011-2018 Rene Hopf - 2011-2018 Robin Kreis - 2011-2018 Rob Spanton - 2011-2018 Rytis Karpuska - 2011-2018 Sean Simmons - 2011-2018 Sergey Alirzaev - 2011-2018 Simon Wright - 2011-2018 Stany MARCEL - 2011-2018 Stefan Misik - 2011-2018 Sven Wegener - 2011-2018 Tectu - 2011-2018 tekaikko - 2011-2018 texane - 2011-2018 Theodore A. Roth - 2011-2018 Thomas Gärtner - 2011-2018 Tobias Badertscher - 2011-2018 Tom de Boer - 2011-2018 Tristan Gingold - 2011-2018 Uli Köhler - 2011-2018 Uwe Bonnes - 2011-2018 Vadim Kaushan - 2011-2018 Vegard Storheil Eriksen - 2011-2018 Viacheslav Dobromyslov - 2011-2018 Victor Mayoral Vilches - 2011-2018 Wojciech A. Koszek - 2011-2018 Woodrow Douglass - 2011-2018 The "Capt'ns Missing Link" Authors. +Copyright: 2011-2021 The stlink project maintainers + Martin Capitanio + Fabien Lementec + Jerry Jacobs + Nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> + and many other contributors... License: BSD-3-clause Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions diff --git a/debian/patches/cross.patch b/debian/patches/cross.patch deleted file mode 100644 index d55e9f9d2..000000000 --- a/debian/patches/cross.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/src/stlink-gui/CMakeLists.txt -+++ b/src/stlink-gui/CMakeLists.txt -@@ -2,7 +2,7 @@ - # Build GUI - ### - --if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) -+if (NOT WIN32) - find_package(PkgConfig) - pkg_check_modules(GTK3 gtk+-3.0) - diff --git a/debian/patches/series b/debian/patches/series deleted file mode 100644 index def274a02..000000000 --- a/debian/patches/series +++ /dev/null @@ -1 +0,0 @@ -cross.patch diff --git a/debian/libstlink-dev.install b/debian/stlink-lib-dev.install similarity index 100% rename from debian/libstlink-dev.install rename to debian/stlink-lib-dev.install diff --git a/debian/libstlink1.install b/debian/stlink-lib.install similarity index 100% rename from debian/libstlink1.install rename to debian/stlink-lib.install diff --git a/debian/libstlink1.symbols b/debian/stlink-lib.symbols similarity index 99% rename from debian/libstlink1.symbols rename to debian/stlink-lib.symbols index bc4e62f0e..9fb371d64 100644 --- a/debian/libstlink1.symbols +++ b/debian/stlink-lib.symbols @@ -1,4 +1,4 @@ -libstlink.so.1 libstlink1 #MINVER# +stlink-lib.so.1 stlink-lib #MINVER# Md5Calculate@Base 1.6.1 Md5Finalise@Base 1.6.1 Md5Initialise@Base 1.6.1 diff --git a/debian/stlink.pc.in b/debian/stlink.pc.in index 7fde2d968..b5f994bad 100644 --- a/debian/stlink.pc.in +++ b/debian/stlink.pc.in @@ -3,7 +3,7 @@ includedir=${prefix}/include/stlink libdir=${prefix}/lib/@DEB_HOST_MULTIARCH@ Name: stlink -Description: Open source version of the STMicroelectronics Stlink Tools +Description: Open source version of the STMicroelectronics STLINK Tools Version: @VERSION@ Requires: libusb-1.0 Libs: -L${libdir} -lstlink diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 22a22f59d..80e3762c3 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -2,7 +2,7 @@ # Build GUI ### -if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) +if (NOT WIN32) find_package(PkgConfig) pkg_check_modules(GTK3 gtk+-3.0) From c8fc6561fead79ad49c09d82bab864745086792c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 29 Aug 2021 15:08:54 +0200 Subject: [PATCH 1248/1435] Bugfixes - Corrected paths for chip-id files (Closes #1180) - Fixed 32-bit build (Closes #985) (Closes #1175) - Patch for GitHub Actions Workflow (Ubuntu) --- .github/workflows/c-cpp.yml | 106 ++------------------------ .github/workflows/codeql-analysis.yml | 2 +- CMakeLists.txt | 13 ++-- src/common.c | 4 +- 4 files changed, 18 insertions(+), 107 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index ee06d5469..442b3ba43 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -15,7 +15,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: install dependencies - run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -35,7 +35,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: install dependencies - run: sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -60,7 +60,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: install dependencies - run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -80,7 +80,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -105,7 +105,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -125,7 +125,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -150,7 +150,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -170,7 +170,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -191,96 +191,6 @@ jobs: # macOS - # job_macos_10_14_64_gcc: - # name: macos-10.14 gcc - # runs-on: macos-10.14 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: brew install gcc libusb gtk+3 - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean - - # job_macos_10_14_32_gcc: - # name: macos-10.14 gcc 32-bit - # runs-on: macos-10.14 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: brew install gcc libusb gtk+3 - # - name: Set compiler flags - # run: | - # CFLAGS="$CFLAGS -m32" - # CXXFLAGS="$CXXFLAGS -m32" - # LDFLAGS="$LDFLAGS -m32" - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean - - # job_macos_10_14_64_clang: - # name: macos-10.14 clang - # runs-on: macos-10.14 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: brew install llvm libusb gtk+3 - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean - - # job_macos_10_14_32_clang: - # name: macos-10.14 clang 32-bit - # runs-on: macos-10.14 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: brew install llvm libusb gtk+3 - # - name: Set compiler flags - # run: | - # CFLAGS="$CFLAGS -m32" - # CXXFLAGS="$CXXFLAGS -m32" - # LDFLAGS="$LDFLAGS -m32" - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean - job_macos_10_15_gcc: name: macos-10.15 gcc runs-on: macos-10.15 diff --git a/.github/workflows/codeql-analysis.yml b/.github/workflows/codeql-analysis.yml index 26313ecb5..55a21294f 100644 --- a/.github/workflows/codeql-analysis.yml +++ b/.github/workflows/codeql-analysis.yml @@ -35,7 +35,7 @@ jobs: steps: - name: Install dependencies - run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm - name: Checkout repository uses: actions/checkout@v2 diff --git a/CMakeLists.txt b/CMakeLists.txt index 5c8aaa60c..fd17d47cc 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -9,11 +9,6 @@ set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) -set(CMAKE_STLINK_ETC_DIR etc) -set(CMAKE_ETC_CHIPS_DIR ${CMAKE_STLINK_ETC_DIR}/stlink/chips) -set(CMAKE_ETC_CHIPS_DIR_ABS ${CMAKE_INSTALL_PREFIX}/${CMAKE_ETC_CHIPS_DIR}) -add_definitions( -DETC_STLINK_DIR="${CMAKE_ETC_CHIPS_DIR_ABS}" ) - ### # General project settings @@ -23,6 +18,11 @@ project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics ST-LINK Tools") include(GNUInstallDirs) # Define GNU standard installation directories +## MCU configuration files +set(CMAKE_CHIPS_SUBDIR stlink/chips) +set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_PREFIX}/${CMAKE_CHIPS_SUBDIR}) +add_definitions( -DETC_STLINK_DIR="${CMAKE_CHIPS_DIR}" ) + ## Determine project version include(${CMAKE_MODULE_PATH}/get_version.cmake) @@ -287,8 +287,9 @@ install(TARGETS st-info DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-util DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-trace DESTINATION ${CMAKE_INSTALL_BINDIR}) +# Install MCU configuration files file(GLOB CHIP_FILES ${CMAKE_SOURCE_DIR}/config/chips/*.chip) -install(FILES ${CHIP_FILES} DESTINATION ${CMAKE_ETC_CHIPS_DIR}) +install(FILES ${CHIP_FILES} DESTINATION ${CMAKE_CHIPS_DIR}) ### diff --git a/src/common.c b/src/common.c index 601fac0b6..c40f6aa79 100644 --- a/src/common.c +++ b/src/common.c @@ -2199,7 +2199,7 @@ static int map_file(mapped_file_t *mf, const char *path) { if (sizeof(st.st_size) != sizeof(size_t)) { // on 32 bit systems, check if there is an overflow - if (st.st_size > (off_t)INT32_MAX) { + if (st.st_size > (off_t)SSIZE_MAX) { fprintf(stderr, "mmap() size_t overflow for file %s\n", path); goto on_error; } @@ -2213,7 +2213,7 @@ static int map_file(mapped_file_t *mf, const char *path) { goto on_error; } - mf->len = st.st_size; + mf->len = (size_t)st.st_size; error = 0; // success on_error: From e51309f8428c4f1eea3ef1840c4fd5116c64279c Mon Sep 17 00:00:00 2001 From: Grzegorz Szymaszek Date: Sat, 21 Aug 2021 16:43:26 +0200 Subject: [PATCH 1249/1435] Update chip config files from the library structs In general, the chip config files should be kept in sync with the old library structs. Regenerate the files (using an ad hoc script) from the current library. The file name is generated from the chip description, all non-alphanumeric characters are replaced with underscores. It turns out some files have to have their names changed. --- config/chips/{F0xx_small.chip => F03x.chip} | 8 ++++---- config/chips/F04x.chip | 4 ++-- config/chips/{F0xx.chip => F05x.chip} | 8 ++++---- config/chips/F07x.chip | 4 ++-- config/chips/F09x.chip | 4 ++-- ..._low-density.chip => F1_Low_density_device.chip} | 8 ++++---- config/chips/F1_value_line_high-density.chip | 13 ------------- .../{F1_connectivity_line.chip => F1xx_CL.chip} | 8 ++++---- ...{F1_high-density.chip => F1xx_High_density.chip} | 8 ++++---- config/chips/F1xx_High_density_value_line.chip | 13 +++++++++++++ ...medium-density.chip => F1xx_Medium_density.chip} | 8 ++++---- .../{F1_value_line.chip => F1xx_Value_Line.chip} | 8 ++++---- .../{F1_XL-density.chip => F1xx_XL_density.chip} | 4 ++-- config/chips/{F2.chip => F2xx.chip} | 4 ++-- .../chips/{F3xx_small.chip => F301_F302_F318.chip} | 8 ++++---- config/chips/F302_F303_F358.chip | 13 +++++++++++++ ...F334_medium_density.chip => F303_F328_F334.chip} | 8 ++++---- config/chips/F303_high_density.chip | 4 ++-- config/chips/F37x.chip | 4 ++-- config/chips/{F4xx_low_power.chip => F401xB_C.chip} | 4 ++-- .../{F4xx_dynamic_efficiency.chip => F401xD_E.chip} | 4 ++-- config/chips/{F411xx.chip => F411xC_E.chip} | 4 ++-- config/chips/{F413.chip => F413_F423.chip} | 4 ++-- config/chips/{F4xx.chip => F4x5_F4x7.chip} | 4 ++-- config/chips/{F7xx.chip => F74x_F75x.chip} | 4 ++-- config/chips/{F76xxx.chip => F76x_F77x.chip} | 6 +++--- .../chips/{G030_G031_G041.chip => G03x_G04x.chip} | 4 ++-- config/chips/G05x_G06x.chip | 13 +++++++++++++ .../chips/{G070_G071_G081.chip => G07x_G08x.chip} | 4 ++-- config/chips/G0Bx_G0Cx.chip | 13 +++++++++++++ config/chips/{G4_cat2.chip => G43x_G44x.chip} | 4 ++-- config/chips/{G4_cat3.chip => G47x_G48x.chip} | 6 +++--- config/chips/G49x_G4Ax.chip | 13 +++++++++++++ config/chips/{L011.chip => L01x_L02x.chip} | 4 ++-- config/chips/{L0xx_cat2.chip => L0xx_Cat_2.chip} | 4 ++-- config/chips/{L0x3.chip => L0xx_Cat_3.chip} | 4 ++-- config/chips/{L0xx_cat5.chip => L0xx_Cat_5.chip} | 6 +++--- .../{L1xx_medium-density.chip => L1xx_Cat_1.chip} | 4 ++-- config/chips/{L1xx_cat2.chip => L1xx_Cat_2.chip} | 4 ++-- ...1xx_medium-plus-density.chip => L1xx_Cat_3.chip} | 4 ++-- .../{L1xx_high-density.chip => L1xx_Cat_4.chip} | 4 ++-- config/chips/{L152RE.chip => L1xx_Cat_5.chip} | 4 ++-- config/chips/{L41x.chip => L41x_L42x.chip} | 4 ++-- config/chips/{L45x_L46x.chip => L45x_46x.chip} | 4 ++-- config/chips/{L4xx.chip => L47x_L48x.chip} | 4 ++-- config/chips/L4Px.chip | 13 +++++++++++++ config/chips/L4Rx.chip | 2 +- config/chips/{WB55.chip => WB5x_3x.chip} | 4 ++-- config/chips/{WLE.chip => WLEx.chip} | 4 ++-- 49 files changed, 182 insertions(+), 117 deletions(-) rename config/chips/{F0xx_small.chip => F03x.chip} (58%) rename config/chips/{F0xx.chip => F05x.chip} (60%) rename config/chips/{F1_low-density.chip => F1_Low_density_device.chip} (51%) delete mode 100644 config/chips/F1_value_line_high-density.chip rename config/chips/{F1_connectivity_line.chip => F1xx_CL.chip} (53%) rename config/chips/{F1_high-density.chip => F1xx_High_density.chip} (53%) create mode 100644 config/chips/F1xx_High_density_value_line.chip rename config/chips/{F1_medium-density.chip => F1xx_Medium_density.chip} (52%) rename config/chips/{F1_value_line.chip => F1xx_Value_Line.chip} (54%) rename config/chips/{F1_XL-density.chip => F1xx_XL_density.chip} (71%) rename config/chips/{F2.chip => F2xx.chip} (80%) rename config/chips/{F3xx_small.chip => F301_F302_F318.chip} (54%) create mode 100644 config/chips/F302_F303_F358.chip rename config/chips/{F334_medium_density.chip => F303_F328_F334.chip} (54%) rename config/chips/{F4xx_low_power.chip => F401xB_C.chip} (71%) rename config/chips/{F4xx_dynamic_efficiency.chip => F401xD_E.chip} (66%) rename config/chips/{F411xx.chip => F411xC_E.chip} (76%) rename config/chips/{F413.chip => F413_F423.chip} (75%) rename config/chips/{F4xx.chip => F4x5_F4x7.chip} (76%) rename config/chips/{F7xx.chip => F74x_F75x.chip} (75%) rename config/chips/{F76xxx.chip => F76x_F77x.chip} (68%) rename config/chips/{G030_G031_G041.chip => G03x_G04x.chip} (72%) create mode 100644 config/chips/G05x_G06x.chip rename config/chips/{G070_G071_G081.chip => G07x_G08x.chip} (72%) create mode 100644 config/chips/G0Bx_G0Cx.chip rename config/chips/{G4_cat2.chip => G43x_G44x.chip} (75%) rename config/chips/{G4_cat3.chip => G47x_G48x.chip} (68%) create mode 100644 config/chips/G49x_G4Ax.chip rename config/chips/{L011.chip => L01x_L02x.chip} (75%) rename config/chips/{L0xx_cat2.chip => L0xx_Cat_2.chip} (75%) rename config/chips/{L0x3.chip => L0xx_Cat_3.chip} (75%) rename config/chips/{L0xx_cat5.chip => L0xx_Cat_5.chip} (68%) rename config/chips/{L1xx_medium-density.chip => L1xx_Cat_1.chip} (68%) rename config/chips/{L1xx_cat2.chip => L1xx_Cat_2.chip} (74%) rename config/chips/{L1xx_medium-plus-density.chip => L1xx_Cat_3.chip} (65%) rename config/chips/{L1xx_high-density.chip => L1xx_Cat_4.chip} (70%) rename config/chips/{L152RE.chip => L1xx_Cat_5.chip} (74%) rename config/chips/{L41x.chip => L41x_L42x.chip} (75%) rename config/chips/{L45x_L46x.chip => L45x_46x.chip} (75%) rename config/chips/{L4xx.chip => L47x_L48x.chip} (76%) create mode 100644 config/chips/L4Px.chip rename config/chips/{WB55.chip => WB5x_3x.chip} (76%) rename config/chips/{WLE.chip => WLEx.chip} (79%) diff --git a/config/chips/F0xx_small.chip b/config/chips/F03x.chip similarity index 58% rename from config/chips/F0xx_small.chip rename to config/chips/F03x.chip index 0a8ec265e..eed78e4e2 100644 --- a/config/chips/F0xx_small.chip +++ b/config/chips/F03x.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F0xx small +# Chip-ID file for F03x # chip_id 0x444 -description F0xx small +description F03x flash_type 1 flash_pagesize 0x400 sram_size 0x1000 bootrom_base 0x1fffec00 bootrom_size 0xc00 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags none diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 033c034e2..1f2a2043e 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -7,7 +7,7 @@ flash_pagesize 0x400 sram_size 0x1800 bootrom_base 0x1fffec00 bootrom_size 0xc00 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags none diff --git a/config/chips/F0xx.chip b/config/chips/F05x.chip similarity index 60% rename from config/chips/F0xx.chip rename to config/chips/F05x.chip index 309bbee34..787adb6bf 100644 --- a/config/chips/F0xx.chip +++ b/config/chips/F05x.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F0xx +# Chip-ID file for F05x # chip_id 0x440 -description F0xx +description F05x flash_type 1 flash_pagesize 0x400 sram_size 0x2000 bootrom_base 0x1fffec00 bootrom_size 0xc00 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags none diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index dd697af40..e893a5457 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -7,7 +7,7 @@ flash_pagesize 0x800 sram_size 0x4000 bootrom_base 0x1fffc800 bootrom_size 0x3000 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags none diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index adb000030..267a2612f 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -7,7 +7,7 @@ flash_pagesize 0x800 sram_size 0x8000 bootrom_base 0x1fffd800 bootrom_size 0x2000 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags none diff --git a/config/chips/F1_low-density.chip b/config/chips/F1_Low_density_device.chip similarity index 51% rename from config/chips/F1_low-density.chip rename to config/chips/F1_Low_density_device.chip index 3995cad96..33fa03e1b 100644 --- a/config/chips/F1_low-density.chip +++ b/config/chips/F1_Low_density_device.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F1 low-density +# Chip-ID file for F1 Low-density device # chip_id 0x412 -description F1 low-density +description F1 Low-density device flash_type 1 flash_pagesize 0x400 sram_size 0x2800 bootrom_base 0x1ffff000 bootrom_size 0x800 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F1_value_line_high-density.chip b/config/chips/F1_value_line_high-density.chip deleted file mode 100644 index 6a49c2699..000000000 --- a/config/chips/F1_value_line_high-density.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1 value line high-density -# -chip_id 0x428 -description F1 value line high-density -flash_type 1 -flash_pagesize 0x800 -sram_size 0x8000 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F1_connectivity_line.chip b/config/chips/F1xx_CL.chip similarity index 53% rename from config/chips/F1_connectivity_line.chip rename to config/chips/F1xx_CL.chip index b6fd9c93a..c2a3b2e69 100644 --- a/config/chips/F1_connectivity_line.chip +++ b/config/chips/F1xx_CL.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F1 connectivity line +# Chip-ID file for F1xx CL # chip_id 0x418 -description F1 connectivity line +description F1xx CL flash_type 1 flash_pagesize 0x800 sram_size 0x10000 bootrom_base 0x1fffb000 bootrom_size 0x4800 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F1_high-density.chip b/config/chips/F1xx_High_density.chip similarity index 53% rename from config/chips/F1_high-density.chip rename to config/chips/F1xx_High_density.chip index f88413fc8..1deb5f01b 100644 --- a/config/chips/F1_high-density.chip +++ b/config/chips/F1xx_High_density.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F1 high-density +# Chip-ID file for F1xx High-density # chip_id 0x414 -description F1 high-density +description F1xx High-density flash_type 1 flash_pagesize 0x800 sram_size 0x10000 bootrom_base 0x1ffff000 bootrom_size 0x800 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F1xx_High_density_value_line.chip b/config/chips/F1xx_High_density_value_line.chip new file mode 100644 index 000000000..9e467c9d7 --- /dev/null +++ b/config/chips/F1xx_High_density_value_line.chip @@ -0,0 +1,13 @@ +# Chip-ID file for F1xx High-density value line +# +chip_id 0x428 +description F1xx High-density value line +flash_type 1 +flash_pagesize 0x800 +sram_size 0x8000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x1ffff800 +option_size 0x10 +flags swo + diff --git a/config/chips/F1_medium-density.chip b/config/chips/F1xx_Medium_density.chip similarity index 52% rename from config/chips/F1_medium-density.chip rename to config/chips/F1xx_Medium_density.chip index 25cbec2dc..a6d81d6f6 100644 --- a/config/chips/F1_medium-density.chip +++ b/config/chips/F1xx_Medium_density.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F1 medium-density +# Chip-ID file for F1xx Medium-density # chip_id 0x410 -description F1 medium-density +description F1xx Medium-density flash_type 1 flash_pagesize 0x400 sram_size 0x5000 bootrom_base 0x1ffff000 bootrom_size 0x800 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F1_value_line.chip b/config/chips/F1xx_Value_Line.chip similarity index 54% rename from config/chips/F1_value_line.chip rename to config/chips/F1xx_Value_Line.chip index 5515d9acd..463cc2d9c 100644 --- a/config/chips/F1_value_line.chip +++ b/config/chips/F1xx_Value_Line.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F1 value line +# Chip-ID file for F1xx Value Line # chip_id 0x420 -description F1 value line +description F1xx Value Line flash_type 1 flash_pagesize 0x400 sram_size 0x2000 bootrom_base 0x1ffff000 bootrom_size 0x800 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F1_XL-density.chip b/config/chips/F1xx_XL_density.chip similarity index 71% rename from config/chips/F1_XL-density.chip rename to config/chips/F1xx_XL_density.chip index 3b3c95ab0..318efbff0 100644 --- a/config/chips/F1_XL-density.chip +++ b/config/chips/F1xx_XL_density.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F1 XL-density +# Chip-ID file for F1xx XL-density # chip_id 0x430 -description F1 XL-density +description F1xx XL-density flash_type 2 flash_pagesize 0x800 sram_size 0x18000 diff --git a/config/chips/F2.chip b/config/chips/F2xx.chip similarity index 80% rename from config/chips/F2.chip rename to config/chips/F2xx.chip index 31a4d34a8..30808f1aa 100644 --- a/config/chips/F2.chip +++ b/config/chips/F2xx.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F2 +# Chip-ID file for F2xx # chip_id 0x411 -description F2 +description F2xx flash_type 3 flash_pagesize 0x20000 sram_size 0x20000 diff --git a/config/chips/F3xx_small.chip b/config/chips/F301_F302_F318.chip similarity index 54% rename from config/chips/F3xx_small.chip rename to config/chips/F301_F302_F318.chip index 31fd136a8..429c836b4 100644 --- a/config/chips/F3xx_small.chip +++ b/config/chips/F301_F302_F318.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F3xx small +# Chip-ID file for F301/F302/F318 # chip_id 0x439 -description F3xx small +description F301/F302/F318 flash_type 1 flash_pagesize 0x800 sram_size 0xa000 bootrom_base 0x1fffd800 bootrom_size 0x2000 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F302_F303_F358.chip b/config/chips/F302_F303_F358.chip new file mode 100644 index 000000000..ffd1491ff --- /dev/null +++ b/config/chips/F302_F303_F358.chip @@ -0,0 +1,13 @@ +# Chip-ID file for F302/F303/F358 +# +chip_id 0x422 +description F302/F303/F358 +flash_type 1 +flash_pagesize 0x800 +sram_size 0xa000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x1ffff800 +option_size 0x10 +flags swo + diff --git a/config/chips/F334_medium_density.chip b/config/chips/F303_F328_F334.chip similarity index 54% rename from config/chips/F334_medium_density.chip rename to config/chips/F303_F328_F334.chip index 365931a01..5df2a9bbb 100644 --- a/config/chips/F334_medium_density.chip +++ b/config/chips/F303_F328_F334.chip @@ -1,13 +1,13 @@ -# Chip-ID file for F334 medium density +# Chip-ID file for F303/F328/F334 # chip_id 0x438 -description F334 medium density +description F303/F328/F334 flash_type 1 flash_pagesize 0x800 sram_size 0x3000 bootrom_base 0x1fffd800 bootrom_size 0x2000 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F303_high_density.chip b/config/chips/F303_high_density.chip index afbdf63b5..748c27cbc 100644 --- a/config/chips/F303_high_density.chip +++ b/config/chips/F303_high_density.chip @@ -7,7 +7,7 @@ flash_pagesize 0x800 sram_size 0x10000 bootrom_base 0x1fffd800 bootrom_size 0x2000 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index 5d5723b14..92201657d 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -7,7 +7,7 @@ flash_pagesize 0x800 sram_size 0xa000 bootrom_base 0x1ffff000 bootrom_size 0x800 -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 +option_size 0x10 flags swo diff --git a/config/chips/F4xx_low_power.chip b/config/chips/F401xB_C.chip similarity index 71% rename from config/chips/F4xx_low_power.chip rename to config/chips/F401xB_C.chip index 7c1cc1243..09e998dba 100644 --- a/config/chips/F4xx_low_power.chip +++ b/config/chips/F401xB_C.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F4xx low power +# Chip-ID file for F401xB/C # chip_id 0x423 -description F4xx low power +description F401xB/C flash_type 3 flash_pagesize 0x4000 sram_size 0x10000 diff --git a/config/chips/F4xx_dynamic_efficiency.chip b/config/chips/F401xD_E.chip similarity index 66% rename from config/chips/F4xx_dynamic_efficiency.chip rename to config/chips/F401xD_E.chip index 02a886c26..5b70d7d86 100644 --- a/config/chips/F4xx_dynamic_efficiency.chip +++ b/config/chips/F401xD_E.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F4xx dynamic efficiency +# Chip-ID file for F401xD/E # chip_id 0x433 -description F4xx dynamic efficiency +description F401xD/E flash_type 3 flash_pagesize 0x4000 sram_size 0x18000 diff --git a/config/chips/F411xx.chip b/config/chips/F411xC_E.chip similarity index 76% rename from config/chips/F411xx.chip rename to config/chips/F411xC_E.chip index e41288de7..d344489c5 100644 --- a/config/chips/F411xx.chip +++ b/config/chips/F411xC_E.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F411xx +# Chip-ID file for F411xC/E # chip_id 0x431 -description F411xx +description F411xC/E flash_type 3 flash_pagesize 0x4000 sram_size 0x20000 diff --git a/config/chips/F413.chip b/config/chips/F413_F423.chip similarity index 75% rename from config/chips/F413.chip rename to config/chips/F413_F423.chip index 94813647f..647775eeb 100644 --- a/config/chips/F413.chip +++ b/config/chips/F413_F423.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F413 +# Chip-ID file for F413/F423 # chip_id 0x463 -description F413 +description F413/F423 flash_type 3 flash_pagesize 0x4000 sram_size 0x50000 diff --git a/config/chips/F4xx.chip b/config/chips/F4x5_F4x7.chip similarity index 76% rename from config/chips/F4xx.chip rename to config/chips/F4x5_F4x7.chip index 1c6d087a5..b19e4a5b3 100644 --- a/config/chips/F4xx.chip +++ b/config/chips/F4x5_F4x7.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F4xx +# Chip-ID file for F4x5/F4x7 # chip_id 0x413 -description F4xx +description F4x5/F4x7 flash_type 3 flash_pagesize 0x4000 sram_size 0x30000 diff --git a/config/chips/F7xx.chip b/config/chips/F74x_F75x.chip similarity index 75% rename from config/chips/F7xx.chip rename to config/chips/F74x_F75x.chip index b6e3774f7..0604b299d 100644 --- a/config/chips/F7xx.chip +++ b/config/chips/F74x_F75x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F7xx +# Chip-ID file for F74x/F75x # chip_id 0x449 -description F7xx +description F74x/F75x flash_type 3 flash_pagesize 0x800 sram_size 0x50000 diff --git a/config/chips/F76xxx.chip b/config/chips/F76x_F77x.chip similarity index 68% rename from config/chips/F76xxx.chip rename to config/chips/F76x_F77x.chip index ef17fc557..304c99191 100644 --- a/config/chips/F76xxx.chip +++ b/config/chips/F76x_F77x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for F76xxx +# Chip-ID file for F76x/F77x # chip_id 0x451 -description F76xxx +description F76x/F77x flash_type 4 flash_pagesize 0x800 sram_size 0x80000 @@ -9,5 +9,5 @@ bootrom_base 0x200000 bootrom_size 0xedc0 option_base 0x1fff0000 option_size 0x20 -flags swo +flags dualbank swo diff --git a/config/chips/G030_G031_G041.chip b/config/chips/G03x_G04x.chip similarity index 72% rename from config/chips/G030_G031_G041.chip rename to config/chips/G03x_G04x.chip index 16a9a79ff..7c5a00c58 100644 --- a/config/chips/G030_G031_G041.chip +++ b/config/chips/G03x_G04x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for G030/G031/G041 +# Chip-ID file for G03x/G04x # chip_id 0x466 -description G030/G031/G041 +description G03x/G04x flash_type 7 flash_pagesize 0x800 sram_size 0x2000 diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip new file mode 100644 index 000000000..45295ec6e --- /dev/null +++ b/config/chips/G05x_G06x.chip @@ -0,0 +1,13 @@ +# Chip-ID file for G05x/G06x +# +chip_id 0x456 +description G05x/G06x +flash_type 7 +flash_pagesize 0x800 +sram_size 0x9000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1fff7800 +option_size 0x4 +flags none + diff --git a/config/chips/G070_G071_G081.chip b/config/chips/G07x_G08x.chip similarity index 72% rename from config/chips/G070_G071_G081.chip rename to config/chips/G07x_G08x.chip index 7fb81eb1f..7bddcd82c 100644 --- a/config/chips/G070_G071_G081.chip +++ b/config/chips/G07x_G08x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for G070/G071/G081 +# Chip-ID file for G07x/G08x # chip_id 0x460 -description G070/G071/G081 +description G07x/G08x flash_type 7 flash_pagesize 0x800 sram_size 0x9000 diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip new file mode 100644 index 000000000..98e503569 --- /dev/null +++ b/config/chips/G0Bx_G0Cx.chip @@ -0,0 +1,13 @@ +# Chip-ID file for G0Bx/G0Cx +# +chip_id 0x467 +description G0Bx/G0Cx +flash_type 7 +flash_pagesize 0x800 +sram_size 0x9000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1fff7800 +option_size 0x4 +flags dualbank + diff --git a/config/chips/G4_cat2.chip b/config/chips/G43x_G44x.chip similarity index 75% rename from config/chips/G4_cat2.chip rename to config/chips/G43x_G44x.chip index ea144114d..033f1dd80 100644 --- a/config/chips/G4_cat2.chip +++ b/config/chips/G43x_G44x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for G4 cat2 +# Chip-ID file for G43x/G44x # chip_id 0x468 -description G4 cat2 +description G43x/G44x flash_type 8 flash_pagesize 0x800 sram_size 0x8000 diff --git a/config/chips/G4_cat3.chip b/config/chips/G47x_G48x.chip similarity index 68% rename from config/chips/G4_cat3.chip rename to config/chips/G47x_G48x.chip index 7e34e001c..fa331650f 100644 --- a/config/chips/G4_cat3.chip +++ b/config/chips/G47x_G48x.chip @@ -1,10 +1,10 @@ -# Chip-ID file for G4 cat3 +# Chip-ID file for G47x/G48x # chip_id 0x469 -description G4 cat3 +description G47x/G48x flash_type 8 flash_pagesize 0x800 -sram_size 0x18000 +sram_size 0x20000 bootrom_base 0x1fff0000 bootrom_size 0x7000 option_base 0x1ffff800 diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip new file mode 100644 index 000000000..b764572db --- /dev/null +++ b/config/chips/G49x_G4Ax.chip @@ -0,0 +1,13 @@ +# Chip-ID file for G49x/G4Ax +# +chip_id 0x479 +description G49x/G4Ax +flash_type 8 +flash_pagesize 0x800 +sram_size 0x1c000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x1ffff800 +option_size 0x4 +flags swo + diff --git a/config/chips/L011.chip b/config/chips/L01x_L02x.chip similarity index 75% rename from config/chips/L011.chip rename to config/chips/L01x_L02x.chip index 719185558..c3d2074b9 100644 --- a/config/chips/L011.chip +++ b/config/chips/L01x_L02x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L011 +# Chip-ID file for L01x/L02x # chip_id 0x457 -description L011 +description L01x/L02x flash_type 5 flash_pagesize 0x80 sram_size 0x2000 diff --git a/config/chips/L0xx_cat2.chip b/config/chips/L0xx_Cat_2.chip similarity index 75% rename from config/chips/L0xx_cat2.chip rename to config/chips/L0xx_Cat_2.chip index cdcff81cc..47183b8ef 100644 --- a/config/chips/L0xx_cat2.chip +++ b/config/chips/L0xx_Cat_2.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L0xx cat2 +# Chip-ID file for L0xx Cat.2 # chip_id 0x425 -description L0xx cat2 +description L0xx Cat.2 flash_type 5 flash_pagesize 0x80 sram_size 0x2000 diff --git a/config/chips/L0x3.chip b/config/chips/L0xx_Cat_3.chip similarity index 75% rename from config/chips/L0x3.chip rename to config/chips/L0xx_Cat_3.chip index cbdc6cace..6d9fcc105 100644 --- a/config/chips/L0x3.chip +++ b/config/chips/L0xx_Cat_3.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L0x3 +# Chip-ID file for L0xx Cat.3 # chip_id 0x417 -description L0x3 +description L0xx Cat.3 flash_type 5 flash_pagesize 0x80 sram_size 0x2000 diff --git a/config/chips/L0xx_cat5.chip b/config/chips/L0xx_Cat_5.chip similarity index 68% rename from config/chips/L0xx_cat5.chip rename to config/chips/L0xx_Cat_5.chip index 2c755a0d8..545c1c2ef 100644 --- a/config/chips/L0xx_cat5.chip +++ b/config/chips/L0xx_Cat_5.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L0xx cat5 +# Chip-ID file for L0xx Cat.5 # chip_id 0x447 -description L0xx cat5 +description L0xx Cat.5 flash_type 5 flash_pagesize 0x80 sram_size 0x5000 @@ -9,5 +9,5 @@ bootrom_base 0x1ff0000 bootrom_size 0x2000 option_base 0x1ff80000 option_size 0x14 -flags none +flags dualbank diff --git a/config/chips/L1xx_medium-density.chip b/config/chips/L1xx_Cat_1.chip similarity index 68% rename from config/chips/L1xx_medium-density.chip rename to config/chips/L1xx_Cat_1.chip index f77c19cac..6c8b211c4 100644 --- a/config/chips/L1xx_medium-density.chip +++ b/config/chips/L1xx_Cat_1.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L1xx medium-density +# Chip-ID file for L1xx Cat.1 # chip_id 0x416 -description L1xx medium-density +description L1xx Cat.1 flash_type 5 flash_pagesize 0x100 sram_size 0x4000 diff --git a/config/chips/L1xx_cat2.chip b/config/chips/L1xx_Cat_2.chip similarity index 74% rename from config/chips/L1xx_cat2.chip rename to config/chips/L1xx_Cat_2.chip index 7f949923e..1ff71edef 100644 --- a/config/chips/L1xx_cat2.chip +++ b/config/chips/L1xx_Cat_2.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L1xx cat2 +# Chip-ID file for L1xx Cat.2 # chip_id 0x429 -description L1xx cat2 +description L1xx Cat.2 flash_type 5 flash_pagesize 0x100 sram_size 0x8000 diff --git a/config/chips/L1xx_medium-plus-density.chip b/config/chips/L1xx_Cat_3.chip similarity index 65% rename from config/chips/L1xx_medium-plus-density.chip rename to config/chips/L1xx_Cat_3.chip index da557e3c8..f417e07f9 100644 --- a/config/chips/L1xx_medium-plus-density.chip +++ b/config/chips/L1xx_Cat_3.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L1xx medium-plus-density +# Chip-ID file for L1xx Cat.3 # chip_id 0x427 -description L1xx medium-plus-density +description L1xx Cat.3 flash_type 5 flash_pagesize 0x100 sram_size 0x8000 diff --git a/config/chips/L1xx_high-density.chip b/config/chips/L1xx_Cat_4.chip similarity index 70% rename from config/chips/L1xx_high-density.chip rename to config/chips/L1xx_Cat_4.chip index 409c04062..dbf7869ad 100644 --- a/config/chips/L1xx_high-density.chip +++ b/config/chips/L1xx_Cat_4.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L1xx high-density +# Chip-ID file for L1xx Cat.4 # chip_id 0x436 -description L1xx high-density +description L1xx Cat.4 flash_type 5 flash_pagesize 0x100 sram_size 0xc000 diff --git a/config/chips/L152RE.chip b/config/chips/L1xx_Cat_5.chip similarity index 74% rename from config/chips/L152RE.chip rename to config/chips/L1xx_Cat_5.chip index 4d9658ee9..12342d14f 100644 --- a/config/chips/L152RE.chip +++ b/config/chips/L1xx_Cat_5.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L152RE +# Chip-ID file for L1xx Cat.5 # chip_id 0x437 -description L152RE +description L1xx Cat.5 flash_type 5 flash_pagesize 0x100 sram_size 0x14000 diff --git a/config/chips/L41x.chip b/config/chips/L41x_L42x.chip similarity index 75% rename from config/chips/L41x.chip rename to config/chips/L41x_L42x.chip index 5b491ccd4..3e086e159 100644 --- a/config/chips/L41x.chip +++ b/config/chips/L41x_L42x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L41x +# Chip-ID file for L41x/L42x # chip_id 0x464 -description L41x +description L41x/L42x flash_type 6 flash_pagesize 0x800 sram_size 0xa000 diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_46x.chip similarity index 75% rename from config/chips/L45x_L46x.chip rename to config/chips/L45x_46x.chip index 8b5f91ec3..943b275d5 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_46x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L45x/L46x +# Chip-ID file for L45x/46x # chip_id 0x462 -description L45x/L46x +description L45x/46x flash_type 6 flash_pagesize 0x800 sram_size 0x20000 diff --git a/config/chips/L4xx.chip b/config/chips/L47x_L48x.chip similarity index 76% rename from config/chips/L4xx.chip rename to config/chips/L47x_L48x.chip index c665c245f..7069229f3 100644 --- a/config/chips/L4xx.chip +++ b/config/chips/L47x_L48x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for L4xx +# Chip-ID file for L47x/L48x # chip_id 0x415 -description L4xx +description L47x/L48x flash_type 6 flash_pagesize 0x800 sram_size 0x18000 diff --git a/config/chips/L4Px.chip b/config/chips/L4Px.chip new file mode 100644 index 000000000..3e0fbea50 --- /dev/null +++ b/config/chips/L4Px.chip @@ -0,0 +1,13 @@ +# Chip-ID file for L4Px +# +chip_id 0x471 +description L4Px +flash_type 6 +flash_pagesize 0x1000 +sram_size 0xa0000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x0 +option_size 0x0 +flags dualbank swo + diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index 11780ce27..a9a26f419 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -9,5 +9,5 @@ bootrom_base 0x1fff0000 bootrom_size 0x7000 option_base 0x0 option_size 0x0 -flags swo +flags dualbank swo diff --git a/config/chips/WB55.chip b/config/chips/WB5x_3x.chip similarity index 76% rename from config/chips/WB55.chip rename to config/chips/WB5x_3x.chip index 585b576bc..0627bdeec 100644 --- a/config/chips/WB55.chip +++ b/config/chips/WB5x_3x.chip @@ -1,7 +1,7 @@ -# Chip-ID file for WB55 +# Chip-ID file for WB5x/3x # chip_id 0x495 -description WB55 +description WB5x/3x flash_type 9 flash_pagesize 0x1000 sram_size 0x40000 diff --git a/config/chips/WLE.chip b/config/chips/WLEx.chip similarity index 79% rename from config/chips/WLE.chip rename to config/chips/WLEx.chip index dbdf66d59..19d0678e5 100644 --- a/config/chips/WLE.chip +++ b/config/chips/WLEx.chip @@ -1,7 +1,7 @@ -# Chip-ID file for WLE +# Chip-ID file for WLEx # chip_id 0x497 -description WLE +description WLEx flash_type 9 flash_pagesize 0x800 sram_size 0x10000 From 0489af7d4d40ae32413fb449d064dad49ba227ee Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 29 Aug 2021 18:08:18 +0200 Subject: [PATCH 1250/1435] General Project Update - [doc] Updated version requirements - Updated CHANGELOG.md --- CHANGELOG.md | 4 ++ doc/version_support.md | 95 ++++++++++++++++++++++-------------------- 2 files changed, 54 insertions(+), 45 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 9bbb41a98..06f995d21 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -25,6 +25,7 @@ Updates & changes: - Drop execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) - Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) - Removed redundant array ([#1178](https://github.com/stlink-org/stlink/pull/1178)) +- Updated chip config files from the library structs ([#1181](https://github.com/stlink-org/stlink/pull/1181)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) @@ -37,6 +38,9 @@ Fixes: - Fixed parsing hex numbers in chip config files ([#1169](https://github.com/stlink-org/stlink/pull/1169)) - Corrected flash_pagesize to use hex format ([#1172](https://github.com/stlink-org/stlink/pull/1172)) - Fixed compilation for MSVC ([#1176](https://github.com/stlink-org/stlink/pull/1176)) +- Fixed few warnings for msvc about type conversion with possible lost data ([#1179](https://github.com/stlink-org/stlink/pull/1179)) +- st-flash and other utilities search for chip files in the wrong directory ([#1180](https://github.com/stlink-org/stlink/pull/1180), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) +- Fixed broken build on 32 bit systems ([#985](https://github.com/stlink-org/stlink/pull/985), [#1175](https://github.com/stlink-org/stlink/pull/1175), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) # v1.7.0 diff --git a/doc/version_support.md b/doc/version_support.md index bf4bc1e5e..2c5df7461 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -21,47 +21,51 @@ NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 a ### Linux-/Unix-based: -| Operating System | libusb | cmake | gtk-3 | Notes | -| ------------------------- | ------------------ | --------- | ----------- | ----------------------------- | -| Arch Linux | 1.0.24 | 3.20.2 | 3.24.29 | | -| Fedora Rawhide [x64] | 1.0.24 (`libusbx`) | 3.20.2 | 3.24.29 | | -| KaOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| Mageia Cauldron | 1.0.24 | 3.20.2 | 3.24.29 | | -| OpenMandriva Cooker | 1.0.24 | 3.20.2 | 3.24.29 | | -| OpenMandriva Rolling | 1.0.24 | 3.20.2 | 3.24.29 | | -| PCLinuxOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| Slackware Current | 1.0.24 | 3.20.2 | 3.24.28 | | -| Solus [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| openSUSE Tumbleweed [x64] | 1.0.24 | 3.20.1 | 3.24.29 | | -| ALT Linux Sisyphus | 1.0.24 | 3.19.7 | 3.24.29 | | -| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | -| NetBSD 9.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | -| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | | -| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | | -| Debian Sid | 1.0.24 | 3.18.4 | 3.24.24 | | -| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | -| Ubuntu 21.04 (Hirsute) | 1.0.24 | 3.18.4 | 3.24.25 | | -| Fedora 33 [x64] | 1.0.23 (`libusbx`) | 3.18.3 | 3.24.23 | | -| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.18.2 | **3.22.30** | | -| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | | -| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | | -| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.17.0 | 3.24.**14** | | -| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | -| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | -| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.**11** | | -| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.**13** | | -| Mageia 7.1 | 1.0.**22** | 3.14.3 | 3.24.**8** | | -| Debian 10 (Buster) | 1.0.**22** | 3.13.4 | 3.24.**5** | | -| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.11.4 | 3.24.32 | | -| CentOS 8 [x64] | 1.0.23 (`libusbx`) | 3.11.4 | **3.22.30** | | -| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.10.2 | **3.22.30** | | -| Debian 9 (Stretch) | 1.0.**21** | **3.7.2** | **3.22.11** | | -| | | | | | -| FreeBSD 13.x | 1.0.**16 - 18** | 3.20.2 | 3.24.27 | LIBUSB_API_VERSION 0x01000102 | -| FreeBSD 12.x | 1.0.**16 - 18** | 3.19.6 | 3.24.27 | LIBUSB_API_VERSION 0x01000102 | -| FreeBSD 11.x | 1.0.**16 - 18** | 3.15.5 | 3.24.27 | LIBUSB_API_VERSION 0x01000102 | +| Operating System | libusb | cmake | gtk-3 | Notes | +| ------------------------- | -------------------------------- | --------- | ----------- | ------------------------ | +| Debian Sid | 1.0.24 | 3.18.4 | 3.24.24 | | +| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | +| Debian 10 (Buster) | 1.0.**22** | 3.13.4 | 3.24.**5** | | +| Debian 9 (Stretch) | 1.0.**21** | **3.7.2** | **3.22.11** | End of Support: Jun 2022 | +| | | | | | +| Ubuntu 21.04 (Hirsute) | 1.0.24 | 3.18.4 | 3.24.25 | End of Support: Jan 2022 | +| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | +| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.10.2 | **3.22.30** | End of Support: Apr 2023 | +| | | | | | +| Fedora Rawhide [x64] | 1.0.24 (`libusbx`) | 3.20.2 | 3.24.29 | | +| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | +| Fedora 33 [x64] | 1.0.23 (`libusbx`) | 3.18.3 | 3.24.23 | | +| | | | | | +| openSUSE Tumbleweed [x64] | 1.0.24 | 3.20.1 | 3.24.29 | | +| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | | +| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.17.0 | 3.24.**14** | End of Support: Dec 2021 | +| | | | | | +| Alpine 3.14 | 1.0.24 | 3.20.3 | 4.2.1 | | +| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | +| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | +| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.**13** | End of Support: Nov 2021 | +| | | | | | +| FreeBSD 13.x | 1.0.**16 - 18** (API 0x01000102) | 3.20.2 | 3.24.27 | | +| FreeBSD 12.x | 1.0.**16 - 18** (API 0x01000102) | 3.19.6 | 3.24.27 | | +| FreeBSD 11.x | 1.0.**16 - 18** (API 0x01000102) | 3.15.5 | 3.24.27 | End of Support: Sep 2021 | +| | | | | | +| Arch Linux | 1.0.24 | 3.20.2 | 3.24.29 | | +| KaOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| Mageia Cauldron | 1.0.24 | 3.20.2 | 3.24.29 | | +| OpenMandriva Cooker | 1.0.24 | 3.20.2 | 3.24.29 | | +| PCLinuxOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| Slackware Current | 1.0.24 | 3.20.2 | 3.24.28 | | +| Solus [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| ALT Linux Sisyphus | 1.0.24 | 3.19.7 | 3.24.29 | | +| NetBSD 9.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | +| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | +| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.18.2 | **3.22.30** | | +| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | +| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.**11** | | +| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.11.4 | 3.24.32 | | +| CentOS 8 [x64] | 1.0.23 (`libusbx`) | 3.11.4 | **3.22.30** | End of Support: Dec 2021 | ## Unsupported Operating Systems (as of Release v1.7.1) @@ -74,17 +78,18 @@ Systems with highlighted versions remain compatible with this toolset. | NetBSD 7.x | **1.0.22** | **3.16.1** | Jun 2020 | | Alpine 3.10 | **1.0.22** | **3.14.5** | May 2021 | | Fedora 31 [x64] | **1.0.22** (`libusbx`) | **3.14.5** | Nov 2020 | -| Ubuntu 19.10 (Eoan) | **1.0.23** | **3.13.4** | Jul 2020 | +| Mageia 7.1 | **1.0.22** | **3.14.3** | Jun 2021 | | Fedora 30 | **1.0.22** (`libusbx`) | **3.14.2** | May 2020 | +| Ubuntu 19.10 (Eoan) | **1.0.23** | **3.13.4** | Jul 2020 | | Alpine 3.9 | **1.0.22** | **3.13.0** | Jan 2021 | -| openSUSE Leap 15.1 [x64] | **1.0.21** | **3.10.2** | Feb 2021 | +| openSUSE Leap 15.1 [x64] | **1.0.21** | **3.10.2** | Jan 2021 | | Slackware 14.2 | 1.0.20 | 3.5.2 | | | Ubuntu 16.04 LTS (Xenial) | 1.0.20 | 3.5.1 | Apr 2021 | | OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | | Debian 8 (Jessie) | 1.0.19 | 3.0.2 | Jun 2020 | -| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | | +| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | | Ubuntu 14.04 LTS (Trusty) | 1.0.17 | 2.8.12.2 | Apr 2019 | -| CentOS 6 | 1.0.9 (`libusbx`) | 2.8.12.2 | Dec 2020 | +| CentOS 6 | 1.0.9 (`libusbx`) | 2.8.12.2 | Nov 2020 | | Slackware 14.1 | 1.0.9 | 2.8.12 | | | Slackware 14.0 | 1.0.9 | 2.8.8 | | From 7c582b75260fc2af16541d6b1c762ecc5817c906 Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Wed, 1 Sep 2021 07:55:26 +0300 Subject: [PATCH 1251/1435] define SSIZE_MAX if not defined --- src/win32/unistd/unistd.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index ac9d0add3..389c44664 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -51,6 +51,9 @@ */ #define ssize_t int +#ifndef SSIZE_MAX +#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 2147483647 : 9223372036854775807) +#endif #define STDIN_FILENO 0 #define STDOUT_FILENO 1 From 95ccd02207f7ba9b3323726bf16478879d956de1 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Tue, 7 Sep 2021 23:12:46 +0100 Subject: [PATCH 1252/1435] Add support for V3 devices with no MSD Add support for ST-Link V3 devices without MSD that identify using USB PID 0x3754. This PID has been observed on a Nucleo board where MSD was disabled. --- src/stlink-lib/usb.c | 3 ++- src/stlink-lib/usb.h | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 58a07f1a6..e07918800 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1260,7 +1260,8 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER || desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID || desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID || - desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID) { + desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID || + desc.idProduct == STLINK_USB_PID_STLINK_V3_NO_MSD_PID) { slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; slu->ep_trace = 2 | LIBUSB_ENDPOINT_IN; } else { diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 27de32700..c6b71ba4e 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -26,6 +26,7 @@ extern "C" { #define STLINK_USB_PID_STLINK_V3E_PID 0x374e #define STLINK_USB_PID_STLINK_V3S_PID 0x374f #define STLINK_USB_PID_STLINK_V3_2VCP_PID 0x3753 +#define STLINK_USB_PID_STLINK_V3_NO_MSD_PID 0x3754 #define STLINK_V1_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK) @@ -38,7 +39,8 @@ extern "C" { #define STLINK_V3_USB_PID(pid) ((pid) == STLINK_USB_PID_STLINK_V3_USBLOADER || \ (pid) == STLINK_USB_PID_STLINK_V3E_PID || \ (pid) == STLINK_USB_PID_STLINK_V3S_PID || \ - (pid) == STLINK_USB_PID_STLINK_V3_2VCP_PID) + (pid) == STLINK_USB_PID_STLINK_V3_2VCP_PID || \ + (pid) == STLINK_USB_PID_STLINK_V3_NO_MSD_PID) #define STLINK_SUPPORTED_USB_PID(pid) (STLINK_V1_USB_PID(pid) || \ STLINK_V2_USB_PID(pid) || \ From 6471a60460a4659134cf80d8864a022dc09b8447 Mon Sep 17 00:00:00 2001 From: pcnorden <7767295+pcnorden@users.noreply.github.com> Date: Wed, 8 Sep 2021 17:20:58 +0200 Subject: [PATCH 1253/1435] Changed broken link to new address of udev rules Changed and checked that it should work with the new link. Also changed the number of files to 4 since there are 4 udev rule files in the directory. --- doc/tutorial.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index 7e0b3901b..955f85611 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -81,7 +81,7 @@ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ and the `idVendor` of `0483` and `idProduct` of `374b` matches the vendor id from the `lsusb` output. -Make sure that you have all 3 files from here: https://github.com/stlink-org/stlink/tree/master/etc/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing excisting files in `/etc/udev/ruled.d` you should run the following: +Make sure that you have all 4 files from here: https://github.com/stlink-org/stlink/tree/master/config/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing excisting files in `/etc/udev/ruled.d` you should run the following: ``` sudo udevadm control --reload-rules From 478cf82aed3463566ba34399b8a283f7e57b3fcc Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Wed, 8 Sep 2021 22:09:24 +0100 Subject: [PATCH 1254/1435] Include flash_size_reg in chipid params dumps --- src/stlink-lib/chipid.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index d51a0edcb..0fc1270a2 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -906,6 +906,7 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "chip_id 0x%x\n", dev->chip_id); fprintf(fp, "description %s\n", dev->description); fprintf(fp, "flash_type %d\n", dev->flash_type); + fprintf(fp, "flash_size_reg 0x%x\n", dev->flash_size_reg); fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); fprintf(fp, "sram_size 0x%x\n", dev->sram_size); fprintf(fp, "bootrom_base 0x%x\n", dev->bootrom_base); From c676779988c65658cf3e67a60f46f767dfa4421a Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Wed, 8 Sep 2021 22:10:25 +0100 Subject: [PATCH 1255/1435] Fix incorrect chipid params comparison The current chipid params comparison code is based on a simple memcmp. This doesn't work since the structure contains a string pointer. Replace it with a simple field-by-field comparison. --- src/stlink-lib/chipid.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 0fc1270a2..3e89ec0c1 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -916,6 +916,22 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "flags %d\n\n", dev->flags); } +static int chipid_params_eq(struct stlink_chipid_params *p1, struct stlink_chipid_params *p2) +{ + return p1->chip_id == p2->chip_id && + p1->description && p2->description && + strcmp(p1->description, p2->description) == 0 && + p1->flash_type == p2->flash_type && + p1->flash_size_reg == p2->flash_size_reg && + p1->flash_pagesize == p2->flash_pagesize && + p1->sram_size == p2->sram_size && + p1->bootrom_base == p2->bootrom_base && + p1->bootrom_size == p2->bootrom_size && + p1->option_base == p2->option_base && + p1->option_size == p2->option_size && + p1->flags == p2->flags; +} + struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { struct stlink_chipid_params *params = NULL; struct stlink_chipid_params *p2; @@ -931,7 +947,7 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { #if 1 if (params == NULL) { params = p2; - } else if (memcmp (p2, params, sizeof(struct stlink_chipid_params) - sizeof(struct stlink_chipid_params *)) != 0) { + } else if (!chipid_params_eq(params, p2)) { // fprintf (stderr, "Error, chipid params not identical\n"); // return NULL; fprintf(stderr, "---------- old ------------\n"); From b29a740b15df4c44258db4e3ae8bfba6676b851d Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Wed, 8 Sep 2021 22:11:59 +0100 Subject: [PATCH 1256/1435] Silence warning chipid files with STLINK_FLASH_TYPE_UNKNOWN The chipid configuration parser currently emits a warning when it encounters a file with the flash type set to STLINK_FLASH_TYPE_UNKNOWN. In practice, this means that the warning will always be printed since 'unknown_device.chip' uses this value. Make STLINK_FLASH_TYPE_UNKNOWN a permitted value in the config file parser. --- src/stlink-lib/chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 3e89ec0c1..74e1a1647 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1001,7 +1001,7 @@ void process_chipfile(char *fname) { } else if (strcmp (word, "flash_type") == 0) { if (sscanf(value, "%i", (int *)&ts->flash_type) < 1) { fprintf(stderr, "Failed to parse flash type\n"); - } else if (ts->flash_type <= STLINK_FLASH_TYPE_UNKNOWN || ts->flash_type >= STLINK_FLASH_TYPE_MAX) { + } else if (ts->flash_type < STLINK_FLASH_TYPE_UNKNOWN || ts->flash_type >= STLINK_FLASH_TYPE_MAX) { fprintf(stderr, "Unrecognized flash type\n"); } } else if (strcmp (word, "flash_size_reg") == 0) { From 4d556ce150e4048beb6fb6e886b29e2f8962e690 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 16 Sep 2021 00:57:54 +0200 Subject: [PATCH 1257/1435] Update src/stlink-lib/chipid.c Co-authored-by: Grzegorz Szymaszek --- src/stlink-lib/chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 74e1a1647..43a55a495 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -916,7 +916,7 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "flags %d\n\n", dev->flags); } -static int chipid_params_eq(struct stlink_chipid_params *p1, struct stlink_chipid_params *p2) +static int chipid_params_eq(const struct stlink_chipid_params *p1, const struct stlink_chipid_params *p2) { return p1->chip_id == p2->chip_id && p1->description && p2->description && From ce8e1c4942eace3d7d84e770a9401a21b41f72af Mon Sep 17 00:00:00 2001 From: c-grant <60671494+c-grant@users.noreply.github.com> Date: Thu, 4 Nov 2021 21:50:12 -0400 Subject: [PATCH 1258/1435] Update gdb-server.c --- src/st-util/gdb-server.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index a651014c0..ad39ab14a 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -518,6 +518,8 @@ static const char* const memory_map_template_H72x3x = " 0x%x" "       " " " // peripheral regs + " " // External Memory + " " // External device " " // cortex regs " " // bootrom ""; From e94b5db1b474268785a856e0859d21d6e2967a79 Mon Sep 17 00:00:00 2001 From: c-grant <60671494+c-grant@users.noreply.github.com> Date: Fri, 5 Nov 2021 23:45:52 -0400 Subject: [PATCH 1259/1435] Update gdb-server.c --- src/st-util/gdb-server.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index ad39ab14a..81c0aa83a 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -513,13 +513,13 @@ static const char* const memory_map_template_H72x3x = " " // RAM D1 320kB " " // RAM D2 23kB " " // RAM D3 16kB - " " // Backup RAM 4kB + " " // Backup RAM 4kB " " " 0x%x" " " " " // peripheral regs " " // External Memory - " " // External device + " " // External device " " // cortex regs " " // bootrom ""; From f95aec79944c9963daa932a2af51838e396ff77c Mon Sep 17 00:00:00 2001 From: Jan Bramkamp Date: Wed, 24 Nov 2021 01:45:24 +0100 Subject: [PATCH 1260/1435] Teach cmake to find libusb-1.0 port/pkg on OpenBSD On OpenBSD libusb is provided by the libusb1 port/package. --- cmake/modules/Findlibusb.cmake | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index d861bdd5f..cd52026f5 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -43,6 +43,23 @@ elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is message(FATAL_ERROR "Expected libusb library not found on your system! Verify your system integrity.") endif () +elseif (CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") # OpenBSD; libusb-1.0 is available from ports + FIND_PATH( + LIBUSB_INCLUDE_DIR NAMES libusb.h + HINTS /usr/local/include + PATH_SUFFIXES libusb-1.0 + ) + set(LIBUSB_NAME usb-1.0) + find_library( + LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} + HINTS /usr/local + ) + FIND_PACKAGE_HANDLE_STANDARD_ARGS(libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) + mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) + if (NOT LIBUSB_FOUND) + message(FATAL_ERROR "No libusb-1.0 library found on your system! Install libusb-1.0 from ports or packages.") + endif () + elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-toolchain on Debian # MinGW/MSYS/MSVC: 64-bit or 32-bit? if (CMAKE_SIZEOF_VOID_P EQUAL 8) From 8dfebbe5898f4245b044c72330d3f2e2adf5177a Mon Sep 17 00:00:00 2001 From: Jan Bramkamp Date: Wed, 24 Nov 2021 01:48:12 +0100 Subject: [PATCH 1261/1435] Define the MINIMUM_API_LEVEL for OpenBSD Every platform has to declare the minimum libusb API level required by libstlink on it. --- src/stlink-lib/libusb_settings.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index fea28237b..a2dfc6d26 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -31,6 +31,8 @@ #if defined (__FreeBSD__) #define MINIMAL_API_VERSION 0x01000102 // v1.0.16 +#elif defined (__OpenBSD__) + #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 #elif defined (__linux__) #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 #elif defined (__APPLE__) From 60edcf811b89f9eef9aac431095582f9b8fa6be4 Mon Sep 17 00:00:00 2001 From: Crest da Zoltral Date: Thu, 23 Dec 2021 20:27:38 +0100 Subject: [PATCH 1262/1435] Include SSIZE_MAX from limits.h The existing includes don't pull in limits.h on FreeBSD breaking the build on FreeBSD. --- src/common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/common.c b/src/common.c index c40f6aa79..bdd6f5bab 100644 --- a/src/common.c +++ b/src/common.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include From 2b106912c9b06e4c434f2c20b7897953e70dc5d3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 1 Jan 2022 20:24:59 +0100 Subject: [PATCH 1263/1435] Added user review to README.md --- README.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/README.md b/README.md index 0b124d21d..7f797a7d9 100644 --- a/README.md +++ b/README.md @@ -110,3 +110,9 @@ When there is no executable available for your platform or you need the latest ( - Please start new forks from the develop branch, as pull requests will go into this branch as well. Please also refer to our [Contribution Guidelines](CONTRIBUTING.md). + +## User Reviews + +*I hope it's not to out of topic, but I've been so frustrated with AVR related things on OpenBSD, the fact that stlink built out of the box without needing to touch anything was so relieving. Literally made my whole weekend better! +I take it's thanks to @Crest and also to the stlink-org team (@Nightwalker-87 and @xor-gate it seems) to have made a software that's not unfriendly to the "fringe" OSes. +Thank you <3"* - nbonfils, 11.12.2021 \ No newline at end of file From 0d02a46a8f013d4f4d6ce9f163a0625710ff27c2 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 2 Jan 2022 22:51:30 +0100 Subject: [PATCH 1264/1435] [refactoring] Clean-up for chipid files - Spelling fix in tutorial.md - REN param description --> dev_type - ADD param ref_manual_id - CHNG stlink_chipid_params - MV old chipids to chipid_db_old.h - Updated chipid files (F1, F2, WB, WLE) --- config/chips/F1_Low_density_device.chip | 13 - config/chips/F1xx_CL.chip | 14 +- config/chips/F1xx_HD.chip | 14 + config/chips/F1xx_High_density.chip | 13 - .../chips/F1xx_High_density_value_line.chip | 13 - config/chips/F1xx_LD.chip | 14 + config/chips/F1xx_MD.chip | 14 + config/chips/F1xx_Medium_density.chip | 13 - config/chips/F1xx_VL_HD.chip | 14 + config/chips/F1xx_VL_MD_LD.chip | 14 + config/chips/F1xx_Value_Line.chip | 13 - config/chips/F1xx_XLD.chip | 14 + config/chips/F1xx_XL_density.chip | 13 - config/chips/F2xx.chip | 15 +- config/chips/WB5x_3x.chip | 13 - config/chips/WBx5_WBx0.chip | 14 + config/chips/WLEx.chip | 13 +- config/chips/unknown_device.chip | 9 +- doc/tutorial.md | 2 +- src/common.c | 2 +- src/st-info/info.c | 4 +- src/st-trace/trace.c | 2 +- src/stlink-gui/gui.c | 2 +- src/stlink-lib/chipid.c | 936 +----------------- src/stlink-lib/chipid.h | 4 +- src/stlink-lib/chipid_db_old.h | 879 ++++++++++++++++ 26 files changed, 1037 insertions(+), 1034 deletions(-) delete mode 100644 config/chips/F1_Low_density_device.chip create mode 100644 config/chips/F1xx_HD.chip delete mode 100644 config/chips/F1xx_High_density.chip delete mode 100644 config/chips/F1xx_High_density_value_line.chip create mode 100644 config/chips/F1xx_LD.chip create mode 100644 config/chips/F1xx_MD.chip delete mode 100644 config/chips/F1xx_Medium_density.chip create mode 100644 config/chips/F1xx_VL_HD.chip create mode 100644 config/chips/F1xx_VL_MD_LD.chip delete mode 100644 config/chips/F1xx_Value_Line.chip create mode 100644 config/chips/F1xx_XLD.chip delete mode 100644 config/chips/F1xx_XL_density.chip delete mode 100644 config/chips/WB5x_3x.chip create mode 100644 config/chips/WBx5_WBx0.chip create mode 100644 src/stlink-lib/chipid_db_old.h diff --git a/config/chips/F1_Low_density_device.chip b/config/chips/F1_Low_density_device.chip deleted file mode 100644 index 33fa03e1b..000000000 --- a/config/chips/F1_Low_density_device.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1 Low-density device -# -chip_id 0x412 -description F1 Low-density device -flash_type 1 -flash_pagesize 0x400 -sram_size 0x2800 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index c2a3b2e69..6282bc2ee 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -1,13 +1,15 @@ -# Chip-ID file for F1xx CL +# Chip-ID file for STM32F1xx CL device # -chip_id 0x418 -description F1xx CL -flash_type 1 +dev_type STM32F1xx Connectivity Line device +ref_manual_id 0008 +chip_id 0x418 // STLINK_CHIPID_STM32_F1_CONN +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 sram_size 0x10000 bootrom_base 0x1fffb000 bootrom_size 0x4800 -option_base 0x1ffff800 -option_size 0x10 +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 flags swo diff --git a/config/chips/F1xx_HD.chip b/config/chips/F1xx_HD.chip new file mode 100644 index 000000000..72ad9fa75 --- /dev/null +++ b/config/chips/F1xx_HD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F1xx high density device +# +dev_type F1xx high density device +ref_manual_id 0008 +chip_id 0x414 // STLINK_CHIPID_STM32_F1_HD +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x800 +sram_size 0x10000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 +flags swo diff --git a/config/chips/F1xx_High_density.chip b/config/chips/F1xx_High_density.chip deleted file mode 100644 index 1deb5f01b..000000000 --- a/config/chips/F1xx_High_density.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1xx High-density -# -chip_id 0x414 -description F1xx High-density -flash_type 1 -flash_pagesize 0x800 -sram_size 0x10000 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F1xx_High_density_value_line.chip b/config/chips/F1xx_High_density_value_line.chip deleted file mode 100644 index 9e467c9d7..000000000 --- a/config/chips/F1xx_High_density_value_line.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1xx High-density value line -# -chip_id 0x428 -description F1xx High-density value line -flash_type 1 -flash_pagesize 0x800 -sram_size 0x8000 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F1xx_LD.chip b/config/chips/F1xx_LD.chip new file mode 100644 index 000000000..8a3682755 --- /dev/null +++ b/config/chips/F1xx_LD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F1 low density device +# +dev_type STM32F1xx low density device +ref_manual_id 0008 +chip_id 0x412 // STLINK_CHIPID_STM32_F1_LD +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x400 +sram_size 0x2800 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 +flags swo diff --git a/config/chips/F1xx_MD.chip b/config/chips/F1xx_MD.chip new file mode 100644 index 000000000..f3da99493 --- /dev/null +++ b/config/chips/F1xx_MD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F1xx medium density device +# +dev_type STM32F1xx medium density device +ref_manual_id 0008 +chip_id 0x410 // STLINK_CHIPID_STM32_F1_MD +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x400 +sram_size 0x5000 +bootrom_base 0x1ffff000 // Section 2.3.3 "Embedded Flash memory" +bootrom_size 0x800 +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 +flags swo diff --git a/config/chips/F1xx_Medium_density.chip b/config/chips/F1xx_Medium_density.chip deleted file mode 100644 index a6d81d6f6..000000000 --- a/config/chips/F1xx_Medium_density.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1xx Medium-density -# -chip_id 0x410 -description F1xx Medium-density -flash_type 1 -flash_pagesize 0x400 -sram_size 0x5000 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F1xx_VL_HD.chip b/config/chips/F1xx_VL_HD.chip new file mode 100644 index 000000000..f46945a94 --- /dev/null +++ b/config/chips/F1xx_VL_HD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F1xx high density Value Line device +# +dev_type STM32F1xx Value Line high density device +ref_manual_id 0041 +chip_id 0x428 // STLINK_CHIPID_STM32_F1_VL_HD +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x800 +sram_size 0x8000 +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 +flags swo diff --git a/config/chips/F1xx_VL_MD_LD.chip b/config/chips/F1xx_VL_MD_LD.chip new file mode 100644 index 000000000..2bff05b82 --- /dev/null +++ b/config/chips/F1xx_VL_MD_LD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STMF1xx Value Line medium & low density device +# +dev_type STM32F1xx Value Line medium & low density device +ref_manual_id 0041 +chip_id 0x420 // STLINK_CHIPID_STM32_F1_VL_MD_LD +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x400 +sram_size 0x2000 // 0x1000 for low density devices +bootrom_base 0x1ffff000 +bootrom_size 0x800 +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 +flags swo diff --git a/config/chips/F1xx_Value_Line.chip b/config/chips/F1xx_Value_Line.chip deleted file mode 100644 index 463cc2d9c..000000000 --- a/config/chips/F1xx_Value_Line.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1xx Value Line -# -chip_id 0x420 -description F1xx Value Line -flash_type 1 -flash_pagesize 0x400 -sram_size 0x2000 -bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip new file mode 100644 index 000000000..90264ce0f --- /dev/null +++ b/config/chips/F1xx_XLD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F1xx XL density device +# +dev_type STM32F1xx XL density device +ref_manual_id 0008 +chip_id 0x430 // STLINK_CHIPID_STM32_F1_XLD +flash_type 2 // STLINK_FLASH_TYPE_F1_XL +flash_size_reg 0x1ffff7e0 +flash_pagesize 0x800 +sram_size 0x18000 +bootrom_base 0x1fffe000 +bootrom_size 0x1800 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F1xx_XL_density.chip b/config/chips/F1xx_XL_density.chip deleted file mode 100644 index 318efbff0..000000000 --- a/config/chips/F1xx_XL_density.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F1xx XL-density -# -chip_id 0x430 -description F1xx XL-density -flash_type 2 -flash_pagesize 0x800 -sram_size 0x18000 -bootrom_base 0x1fffe000 -bootrom_size 0x1800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip index 30808f1aa..ce2e9e698 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2xx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F2xx +# Chip-ID file for STM32F2xx device (STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx) # -chip_id 0x411 -description F2xx -flash_type 3 +dev_type STM32F2xx device +ref_manual_id 0033 +chip_id 0x411 // STLINK_CHIPID_STM32_F2 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 sram_size 0x20000 bootrom_base 0x1fff0000 bootrom_size 0x7800 -option_base 0x1fffc000 -option_size 0x4 +option_base 0x1fffc000 // STM32_F2_OPTION_BYTES_BASE +option_size 0x4 // 4 flags swo - diff --git a/config/chips/WB5x_3x.chip b/config/chips/WB5x_3x.chip deleted file mode 100644 index 0627bdeec..000000000 --- a/config/chips/WB5x_3x.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for WB5x/3x -# -chip_id 0x495 -description WB5x/3x -flash_type 9 -flash_pagesize 0x1000 -sram_size 0x40000 -bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/WBx5_WBx0.chip b/config/chips/WBx5_WBx0.chip new file mode 100644 index 000000000..5bd2501e6 --- /dev/null +++ b/config/chips/WBx5_WBx0.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32WBx0 device (STM32WB55xx, STM32WB35xx, STM32WB50CG, STM32WB30CE) +# +dev_type STM32WBx0 device +ref_manual_id 0434 // also RM0471 +chip_id 0x495 // STLINK_CHIPID_STM32_WB55 +flash_type 9 // STLINK_FLASH_TYPE_WB +flash_size_reg 0x1fff75e0 +flash_pagesize 0x1000 // 4k +sram_size 0x40000 +bootrom_base 0x1fff0000 +bootrom_size 0x7000 +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/WLEx.chip b/config/chips/WLEx.chip index 19d0678e5..e9b6248f6 100644 --- a/config/chips/WLEx.chip +++ b/config/chips/WLEx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for WLEx +# Chip-ID file for STM32WLEx device # -chip_id 0x497 -description WLEx -flash_type 9 -flash_pagesize 0x800 +dev_type STM32WLEx device +ref_manual_id 0033 +chip_id 0x497 // STLINK_CHIPID_STM32_WLE +flash_type 9 // STLINK_FLASH_TYPE_WB +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2k sram_size 0x10000 bootrom_base 0x1fff0000 bootrom_size 0x7000 option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index c71206951..8f3772e53 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -1,8 +1,10 @@ # Chip-ID file for unknown device # -chip_id 0x0 -description unknown device -flash_type 0 +dev_type unknown device +ref_manual_id 0000 +chip_id 0x0 // STLINK_CHIPID_UNKNOWN +flash_type 0 // STLINK_FLASH_TYPE_UNKNOWN +flash_size_reg 0x0 flash_pagesize 0x0 sram_size 0x0 bootrom_base 0x0 @@ -10,4 +12,3 @@ bootrom_size 0x0 option_base 0x0 option_size 0x0 flags none - diff --git a/doc/tutorial.md b/doc/tutorial.md index 7e0b3901b..9ca6bef5b 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -81,7 +81,7 @@ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ and the `idVendor` of `0483` and `idProduct` of `374b` matches the vendor id from the `lsusb` output. -Make sure that you have all 3 files from here: https://github.com/stlink-org/stlink/tree/master/etc/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing excisting files in `/etc/udev/ruled.d` you should run the following: +Make sure that you have all 3 files from here: https://github.com/stlink-org/stlink/tree/master/etc/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing existing files in `/etc/udev/ruled.d` you should run the following: ``` sudo udevadm control --reload-rules diff --git a/src/common.c b/src/common.c index c40f6aa79..9bfbfc52b 100644 --- a/src/common.c +++ b/src/common.c @@ -1671,7 +1671,7 @@ int stlink_load_device_params(stlink_t *sl) { } ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", - params->description, (unsigned)(sl->sram_size / 1024), + params->dev_type, (unsigned)(sl->sram_size / 1024), (unsigned)(sl->flash_size / 1024), (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) : (unsigned)(sl->flash_pgsz / 1024), diff --git a/src/st-info/info.c b/src/st-info/info.c index ceb406cda..416d27f56 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -42,7 +42,7 @@ static void stlink_print_info(stlink_t *sl) { printf(" chipid: 0x%.4x\n", sl->chip_id); params = stlink_chipid_get_params(sl->chip_id); - if (params) { printf(" descr: %s\n", params->description); } + if (params) { printf(" dev-type: %s\n", params->dev_type); } } static void stlink_probe(enum connect_type connect, int freq) { @@ -118,7 +118,7 @@ static int print_data(int ac, char **av) { const struct stlink_chipid_params *params = stlink_chipid_get_params(sl->chip_id); if (params == NULL) { return(-1); } - printf("%s\n", params->description); + printf("%s\n", params->dev_type); } if (sl) { diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 754a55c72..46304d7d9 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -555,7 +555,7 @@ int main(int argc, char **argv) { if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); - ELOG("We do not support SWO output for device '%s'\n", params->description); + ELOG("We do not support SWO output for device '%s'\n", params->dev_type); if (!settings.force) return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; } diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index f9de46f37..387d3ac68 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -429,7 +429,7 @@ static gchar *dev_format_chip_id(guint32 chip_id) { if (!params) { return(g_strdup_printf("0x%x", chip_id)); } - return(g_strdup(params->description)); + return(g_strdup(params->dev_type)); } static gchar *dev_format_mem_size(gsize flash_size) { diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index d51a0edcb..a991e0921 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,5 +1,6 @@ #include #include "chipid.h" +#include "chipid_db_old.h" #include #include @@ -7,884 +8,6 @@ #include #include -// This is the old chipid "database". -// It is kept here for now to be able to compare the -// result between the "old code" and the "new code". -// For now if you need to change something, please -// change it both here and in the corresponding -// config/chips/*.chip file. - -static struct stlink_chipid_params devices[] = { - { - // STM32F76x/F77x - // RM0410 - .chip_id = STLINK_CHIPID_STM32_F76xxx, - .description = "F76x/F77x", - .flash_type = STLINK_FLASH_TYPE_F7, - .flash_size_reg = 0x1ff0f442, // section 45.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, // "System memory" starting address from - .bootrom_size = 0xEDC0, - .option_base = STM32_F7_OPTION_BYTES_BASE, /* Used for reading back the option - bytes, writing uses FLASH_F7_OPTCR - and FLASH_F7_OPTCR1 */ - .option_size = 0x20, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F74x/F75x - // RM0385, DS10916 - .chip_id = STLINK_CHIPID_STM32_F7, - .description = "F74x/F75x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 41.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F72x/F73x - // RM0431 - .chip_id = STLINK_CHIPID_STM32_F72xxx, - .description = "F72x/F73x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff07a22, // section 35.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx medium-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_MD, - .description = "F1xx Medium-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x5000, - .bootrom_base = 0x1ffff000, // 2.3.3 "Embedded Flash memory" - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx - // RM0033 (rev 5) - .chip_id = STLINK_CHIPID_STM32_F2, - .description = "F2xx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx low-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_LD, - .description = "F1 Low-density device", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2800, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F4x5/F4x7 - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4, - .description = "F4x5/F4x7", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x30000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = STM32_F4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F46x/F47x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_DSI, - .description = "F46x/F47x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F42x/F43x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_HD, - .description = "F42x/F43x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_LP, - .description = "F401xB/C", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F411xx, - .description = "F411xC/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_DE, - .description = "F401xD/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx high-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_HD, - .description = "F1xx High-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.1 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD, - .description = "L1xx Cat.1", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x4000, // up to 16k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.2 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_CAT2, - .description = "L1xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x8000, // up to 32k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.3 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS, - .description = "L1xx Cat.3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x8000, // up to 32k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.4 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS_HD, - .description = "L1xx Cat.4", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0xC000, // up to 48k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .option_base = STM32_L1_OPTION_BYTES_BASE, - .option_size = 8, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.5 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L152_RE, - .description = "L1xx Cat.5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x14000, // up to 80k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx connectivity devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_CONN, - .description = "F1xx CL", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1fffb000, - .bootrom_size = 0x4800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx low- and medium-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_MD_LD, - .description = "F1xx Value Line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2000, // 0x1000 for low density devices - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F446x family - // RM0390 - .chip_id = STLINK_CHIPID_STM32_F446, - .description = "F446", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F410 - // RM0401 - .chip_id = STLINK_CHIPID_STM32_F410, - .description = "F410", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x4000, - .sram_size = 0x8000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F303xB/C, STM32F358, STM32F302xBxC - // RM0316, RM0365 - .chip_id = STLINK_CHIPID_STM32_F3, - .description = "F302/F303/F358", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F373Cx/Rx/Vx, STM32F378Cx/Rx/Vx - // RM0313 - .chip_id = STLINK_CHIPID_STM32_F37x, - .description = "F37x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx high-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_HD, - .description = "F1xx High-density value line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x8000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx XL-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_XLD, - .description = "F1xx XL-density", - .flash_type = STLINK_FLASH_TYPE_F1_XL, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x18000, - .bootrom_base = 0x1fffe000, - .bootrom_size = 0x1800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F07x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0_CAN, - .description = "F07x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 - .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F05x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0, - .description = "F05x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F412 - // RM0402 - .chip_id = STLINK_CHIPID_STM32_F412, - .description = "F412", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) - .flash_pagesize = 0x4000, // Table 5. Flash module organization ? - .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F413/F423 - // RM0430 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F413, - .description = "F413/F423", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 - .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector - // sizes, but 0x4000 is smallest) - .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 - // only says 0x40000) - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F09x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F09x, - .description = "F09x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) - .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) - .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 - .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F04x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F04, - .description = "F04x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F03x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0xx_SMALL, - .description = "F03x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F301x6/8, STM32F302x6x8, STM32F318x8 - // RM0366, RM0365 - .chip_id = STLINK_CHIPID_STM32_F3xx_SMALL, - .description = "F301/F302/F318", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L0xx Category 3 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0, - .description = "L0xx Cat.3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - }, - { - // STM32L0x Category 5 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0_CAT5, - .description = "L0xx Cat.5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x5000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x2000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - .flags = CHIP_F_HAS_DUAL_BANK, - }, - { - // STM32L0x Category 2 - // RM0367, RM0377 - .chip_id = STLINK_CHIPID_STM32_L0_CAT2, - .description = "L0xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - }, - { - // STM32F334, STM32F303x6/8, STM32F328 - // RM0364, RM0316 - .chip_id = STLINK_CHIPID_STM32_F334, - .description = "F303/F328/F334", // (RM0316 sec 33.6.1) - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0x3000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F303xD/E, STM32F398xE, STM32F302xD/E - // RM0316 (rev 5), RM0365 - .chip_id = STLINK_CHIPID_STM32_F303_HD, - .description = "F303 high density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register - .flash_pagesize = 0x800, // 4.2.1 Flash memory organization - .sram_size = 0x10000, // 3.3 Embedded SRAM - .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory - .bootrom_size = 0x2000, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L47x/L48x - // RM0351 - .chip_id = STLINK_CHIPID_STM32_L4, - .description = "L47x/L48x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 - // and tables 4-6 on pages 79-81) - // SRAM1 is "up to" 96k in the standard Cortex-M memory map; - // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L4RX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4Rx, - .description = "L4Rx", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L4PX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4PX, - .description = "L4Px", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L41x_L42x - // RM0394 (rev 4), DS12469 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L41x_L42x, - .description = "L41x/L42x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, - // sec 47.2, page 1586) - .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) - // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 - // (DS12469, sec 3.5, page 18) - .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) - .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000, // 28k, same source as base - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L43x_L44x - // RM0392 - .chip_id = STLINK_CHIPID_STM32_L43x_L44x, - .description = "L43x/L44x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 - // and tables 7-8 on pages 75-76) - // SRAM1 is "up to" 64k in the standard Cortex-M memory map; - // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0xc000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L496x_L4A6x - // RM0351 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, - .description = "L496x/L4A6x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) - // SRAM1 is 256k at 0x20000000 - // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) - .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) - .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L45x_L46x - // RM0394 (updated version of RM0392?) - .chip_id = STLINK_CHIPID_STM32_L45x_L46x, - .description = "L45x/46x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 - // and tables 7 on pages 73-74) - // SRAM1 is 128k at 0x20000000; - // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, - // page 68, also fig 2 on page 63) - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system - // memory, also fig 2 on page 63) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L0xx Category 1 - // RM0451, RM0377 - .chip_id = STLINK_CHIPID_STM32_L011, - .description = "L01x/L02x", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x2000, - }, - { - // STM32G030/031/041 - // RM0454, RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT1, - .description = "G03x/G04x", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x2000, // 8k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G071/081 - // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT2, - .description = "G07x/G08x", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G0B1/G0C1 - // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT3, - .description = "G0Bx/G0Cx", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_DUAL_BANK, - }, - { - // STM32G051/G061 - // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT4, - .description = "G05x/G06x", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G431/441 - // RM0440 - .chip_id = STLINK_CHIPID_STM32_G4_CAT2, - .description = "G43x/G44x", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 16k at 0x20000000 - // SRAM2 is 6k at 0x20014000 - // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x8000, // 32k (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32G471/473/474/483/484 - // RM0440 - .chip_id = STLINK_CHIPID_STM32_G4_CAT3, - .description = "G47x/G48x", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 80k at 0x20000000 - // SRAM2 is 16k at 0x20014000 - // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x20000, // 128k (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32G491/G4A1 - // RM0440 - .chip_id = STLINK_CHIPID_STM32_G4_CAT4, - .description = "G49x/G4Ax", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 80k at 0x20000000 - // SRAM2 is 16k at 0x20014000 - // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x1C000, // 112k (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32WB55xx, STM32WB35xx, STM32WB50CG/30CE - // RM0434, RM0471 - .chip_id = STLINK_CHIPID_STM32_WB55, - .description = "WB5x/3x", - .flash_type = STLINK_FLASH_TYPE_WB, - .flash_size_reg = 0x1FFF75E0, - .flash_pagesize = 0x1000, // 4k - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, // see the memory map - .bootrom_size = 0x7000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32WLEx - .chip_id = STLINK_CHIPID_STM32_WLE, - .description = "WLEx", - .flash_type = STLINK_FLASH_TYPE_WB, - .flash_size_reg = 0x1FFF75E0, - .flash_pagesize = 0x800, // 2k - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, // see the memory map - .bootrom_size = 0x7000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32H742/743/753 (from RM0433) - .chip_id = STLINK_CHIPID_STM32_H74xxx, - .description = "H74x/H75x", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) - .flash_pagesize = 0x20000, // 128k sector (pg147) - .sram_size = 0x20000, // 128k "DTCM" from Table 7 - .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 - .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32H7A3/7B3 - // RM0455 - .chip_id = STLINK_CHIPID_STM32_H7Ax, - .description = "H7Ax/H7Bx", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) - .flash_pagesize = 0x2000, // 8k sector (p.146) - .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 12-14) - .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to - // two banks (Table 12-14) - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32H72x/H73x - // RM0468 - .chip_id = STLINK_CHIPID_STM32_H72x, - .description = "H72x/H73x", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) - .flash_pagesize = 0x20000, // 128k sector (p.152) - .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 6) - .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - - { - // unknown - .chip_id = STLINK_CHIPID_UNKNOWN, - .description = "unknown device", - .flash_type = STLINK_FLASH_TYPE_UNKNOWN, - .flash_size_reg = 0x0, - .flash_pagesize = 0x0, - .sram_size = 0x0, - .bootrom_base = 0x0, - .bootrom_size = 0x0, - }, -}; struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { struct stlink_chipid_params *params = NULL; @@ -901,11 +24,12 @@ struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { static struct stlink_chipid_params *devicelist; void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { - fprintf(fp, "# Chip-ID file for %s\n", dev->description); + fprintf(fp, "# Device Type: %s\n", dev->dev_type); + fprintf(fp, "# Reference Manual: RM%s\n", dev->ref_manual_id); fprintf(fp, "#\n"); fprintf(fp, "chip_id 0x%x\n", dev->chip_id); - fprintf(fp, "description %s\n", dev->description); fprintf(fp, "flash_type %d\n", dev->flash_type); + fprintf(fp, "flash_size_reg %x\n", dev->flash_size_reg); fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); fprintf(fp, "sram_size 0x%x\n", dev->sram_size); fprintf(fp, "bootrom_base 0x%x\n", dev->bootrom_base); @@ -919,7 +43,6 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { struct stlink_chipid_params *params = NULL; struct stlink_chipid_params *p2; - //fprintf (stderr, "getparams: %x\n", chipid); for (params = devicelist; params != NULL; params = params->next) if (params->chip_id == chipid) { break; @@ -949,7 +72,7 @@ void process_chipfile(char *fname) { struct stlink_chipid_params *ts; int nc; - // fprintf (stderr, "processing chipfile %s.\n", fname); + // fprintf (stderr, "processing chip-id file %s.\n", fname); fp = fopen(fname, "r"); if (!fp) { @@ -963,28 +86,33 @@ void process_chipfile(char *fname) { for (p = buf; isspace (*p); p++); if (!*p) { - continue; // we hit end-of-line wiht only whitespace + continue; // we hit end-of-line with only whitespace } if (*p == '#') { - continue; // ignore comments. + continue; // ignore comments } sscanf(p, "%s %s", word, value); - if (strcmp(word, "chip_id") == 0) { - if (sscanf(value, "%i", &ts->chip_id) < 1) { - fprintf(stderr, "Failed to parse chip id\n"); - } - } else if (strcmp (word, "description") == 0) { - // ts->description = strdup (value); + if (strcmp (word, "dev_type") == 0) { + // ts->dev_type = strdup (value); buf[strlen(p) - 1] = 0; // chomp newline sscanf(p, "%*s %n", &nc); - ts->description = strdup(p + nc); + ts->dev_type = strdup(p + nc); + } else if (strcmp (word, "ref_manual_id") == 0) { + // ts->ref_manual_id = strdup (value); + buf[strlen(p) - 1] = 0; // chomp newline + sscanf(p, "%*s %n", &nc); + ts->ref_manual_id = strdup(p + nc); + } else if (strcmp(word, "chip_id") == 0) { + if (sscanf(value, "%i", &ts->chip_id) < 1) { + fprintf(stderr, "Failed to parse chip-id\n"); + } } else if (strcmp (word, "flash_type") == 0) { if (sscanf(value, "%i", (int *)&ts->flash_type) < 1) { fprintf(stderr, "Failed to parse flash type\n"); - } else if (ts->flash_type <= STLINK_FLASH_TYPE_UNKNOWN || ts->flash_type >= STLINK_FLASH_TYPE_MAX) { + } else if ((ts->flash_type < STLINK_FLASH_TYPE_UNKNOWN) || (ts->flash_type >= STLINK_FLASH_TYPE_MAX)) { fprintf(stderr, "Unrecognized flash type\n"); } } else if (strcmp (word, "flash_size_reg") == 0) { @@ -1050,18 +178,19 @@ void dump_chips (void) { for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { ts = &devices[n]; - strcpy(buf, ts->description); + strcpy(buf, ts->dev_type); while ((p = strchr(buf, '/'))) // change slashes to underscore. *p = '_'; strcat(buf, ".chip"); fp = fopen(buf, "w"); - fprintf(fp, "# Chip-ID file for %s\n", ts->description); + fprintf(fp, "# Device Type: %s\n", ts->dev_type); + fprintf(fp, "# Reference Manual: RM%s\n", ts->ref_manual_id); fprintf(fp, "#\n"); fprintf(fp, "chip_id %x\n", ts->chip_id); - fprintf(fp, "description %s\n", ts->description); fprintf(fp, "flash_type %x\n", ts->flash_type); + fprintf(fp, "flash_size_reg %x\n", ts->flash_size_reg); fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); fprintf(fp, "sram_size %x\n", ts->sram_size); fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); @@ -1104,23 +233,6 @@ void init_chipids(char *dir_to_scan) { perror (dir_to_scan); return; // XXX } - -#if 0 - { - struct stlink_chipid_params *p, *op; - int i; - p = devicelist; - - for (i = 0; i < 5; i++, p = p->next) { - op = stlink_chipid_get_params_old (p->chip_id); - fprintf (stderr, "---------- old ------------\n"); - dump_a_chip (stderr, op); - fprintf (stderr, "---------- new ------------\n"); - dump_a_chip (stderr, p); - - } - } -#endif } #endif //STLINK_HAVE_DIRENT_H diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 20cfcf52d..426c22428 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -79,8 +79,9 @@ enum stlink_stm32_chipids { /** Chipid parameters */ struct stlink_chipid_params { + char *dev_type; + char *ref_manual_id; uint32_t chip_id; - char *description; enum stlink_flash_type flash_type; uint32_t flash_size_reg; uint32_t flash_pagesize; @@ -93,7 +94,6 @@ struct stlink_chipid_params { struct stlink_chipid_params * next; }; - struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); void init_chipids(char *dir_to_scan); diff --git a/src/stlink-lib/chipid_db_old.h b/src/stlink-lib/chipid_db_old.h new file mode 100644 index 000000000..bc6491ad4 --- /dev/null +++ b/src/stlink-lib/chipid_db_old.h @@ -0,0 +1,879 @@ +// This is the old chipid "database". +// It is kept here for now to be able to compare the +// result between the "old code" and the "new code". +// For now if you need to change something, please +// change it both here and in the corresponding +// config/chips/*.chip file. + +static struct stlink_chipid_params devices[] = { + { + // STM32F76x/F77x + // RM0410 + .chip_id = STLINK_CHIPID_STM32_F76xxx, + .dev_type = "F76x/F77x", + .flash_type = STLINK_FLASH_TYPE_F7, + .flash_size_reg = 0x1ff0f442, // section 45.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x80000, // "SRAM" byte size in hex from + .bootrom_base = 0x00200000, // "System memory" starting address from + .bootrom_size = 0xEDC0, + .option_base = STM32_F7_OPTION_BYTES_BASE, /* Used for reading back the option + bytes, writing uses FLASH_F7_OPTCR + and FLASH_F7_OPTCR1 */ + .option_size = 0x20, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F74x/F75x + // RM0385, DS10916 + .chip_id = STLINK_CHIPID_STM32_F7, + .dev_type = "F74x/F75x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff0f442, // section 41.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F72x/F73x + // RM0431 + .chip_id = STLINK_CHIPID_STM32_F72xxx, + .dev_type = "F72x/F73x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff07a22, // section 35.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F4x5/F4x7 + // RM0090 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F4, + .dev_type = "F4x5/F4x7", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = STM32_F4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F46x/F47x + // RM0090 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F4_DSI, + .dev_type = "F46x/F47x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F42x/F43x + // RM0090 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F4_HD, + .dev_type = "F42x/F43x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_LP, + .dev_type = "F401xB/C", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x10000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + .chip_id = STLINK_CHIPID_STM32_F411xx, + .dev_type = "F411xC/E", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_DE, + .dev_type = "F401xD/E", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.1 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_MD, + .dev_type = "L1xx Cat.1", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x4000, // up to 16k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.2 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_CAT2, + .dev_type = "L1xx Cat.2", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x8000, // up to 32k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.3 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS, + .dev_type = "L1xx Cat.3", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x8000, // up to 32k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.4 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS_HD, + .dev_type = "L1xx Cat.4", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0xC000, // up to 48k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .option_base = STM32_L1_OPTION_BYTES_BASE, + .option_size = 8, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.5 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L152_RE, + .dev_type = "L1xx Cat.5", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x14000, // up to 80k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F446x family + // RM0390 + .chip_id = STLINK_CHIPID_STM32_F446, + .dev_type = "F446", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F410 + // RM0401 + .chip_id = STLINK_CHIPID_STM32_F410, + .dev_type = "F410", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x4000, + .sram_size = 0x8000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F303xB/C, STM32F358, STM32F302xBxC + // RM0316, RM0365 + .chip_id = STLINK_CHIPID_STM32_F3, + .dev_type = "F302/F303/F358", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F373Cx/Rx/Vx, STM32F378Cx/Rx/Vx + // RM0313 + .chip_id = STLINK_CHIPID_STM32_F37x, + .dev_type = "F37x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F07x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F0_CAN, + .dev_type = "F07x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 + .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 + .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F05x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F0, + .dev_type = "F05x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F412 + // RM0402 + .chip_id = STLINK_CHIPID_STM32_F412, + .dev_type = "F412", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) + .flash_pagesize = 0x4000, // Table 5. Flash module organization ? + .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F413/F423 + // RM0430 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F413, + .dev_type = "F413/F423", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 + .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector + // sizes, but 0x4000 is smallest) + .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 + // only says 0x40000) + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F09x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F09x, + .dev_type = "F09x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) + .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) + .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 + .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F04x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F04, + .dev_type = "F04x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F03x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F0xx_SMALL, + .dev_type = "F03x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F301x6/8, STM32F302x6x8, STM32F318x8 + // RM0366, RM0365 + .chip_id = STLINK_CHIPID_STM32_F3xx_SMALL, + .dev_type = "F301/F302/F318", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1fffd800, + .bootrom_size = 0x2000, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L0xx Category 3 + // RM0367, RM0377, RM0451 + .chip_id = STLINK_CHIPID_STM32_L0, + .dev_type = "L0xx Cat.3", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000, + .option_base = STM32_L0_OPTION_BYTES_BASE, + .option_size = 20, + }, + { + // STM32L0x Category 5 + // RM0367, RM0377, RM0451 + .chip_id = STLINK_CHIPID_STM32_L0_CAT5, + .dev_type = "L0xx Cat.5", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x5000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x2000, + .option_base = STM32_L0_OPTION_BYTES_BASE, + .option_size = 20, + .flags = CHIP_F_HAS_DUAL_BANK, + }, + { + // STM32L0x Category 2 + // RM0367, RM0377 + .chip_id = STLINK_CHIPID_STM32_L0_CAT2, + .dev_type = "L0xx Cat.2", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000, + .option_base = STM32_L0_OPTION_BYTES_BASE, + .option_size = 20, + }, + { + // STM32F334, STM32F303x6/8, STM32F328 + // RM0364, RM0316 + .chip_id = STLINK_CHIPID_STM32_F334, + .dev_type = "F303/F328/F334", // (RM0316 sec 33.6.1) + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0x3000, + .bootrom_base = 0x1fffd800, + .bootrom_size = 0x2000, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F303xD/E, STM32F398xE, STM32F302xD/E + // RM0316 (rev 5), RM0365 + .chip_id = STLINK_CHIPID_STM32_F303_HD, + .dev_type = "F303 high density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register + .flash_pagesize = 0x800, // 4.2.1 Flash memory organization + .sram_size = 0x10000, // 3.3 Embedded SRAM + .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory + .bootrom_size = 0x2000, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L47x/L48x + // RM0351 + .chip_id = STLINK_CHIPID_STM32_L4, + .dev_type = "L47x/L48x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 + // and tables 4-6 on pages 79-81) + // SRAM1 is "up to" 96k in the standard Cortex-M memory map; + // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L4RX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4Rx, + .dev_type = "L4Rx", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L4PX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4PX, + .dev_type = "L4Px", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L41x_L42x + // RM0394 (rev 4), DS12469 (rev 5) + .chip_id = STLINK_CHIPID_STM32_L41x_L42x, + .dev_type = "L41x/L42x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, + // sec 47.2, page 1586) + .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) + // SRAM1 is 32k at 0x20000000 + // SRAM2 is 8k at 0x10000000 and 0x20008000 + // (DS12469, sec 3.5, page 18) + .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) + .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) + .bootrom_size = 0x7000, // 28k, same source as base + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L43x_L44x + // RM0392 + .chip_id = STLINK_CHIPID_STM32_L43x_L44x, + .dev_type = "L43x/L44x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 + // and tables 7-8 on pages 75-76) + // SRAM1 is "up to" 64k in the standard Cortex-M memory map; + // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0xc000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L496x_L4A6x + // RM0351 (rev 5) + .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, + .dev_type = "L496x/L4A6x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) + .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) + // SRAM1 is 256k at 0x20000000 + // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) + .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) + .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L45x_L46x + // RM0394 (updated version of RM0392?) + .chip_id = STLINK_CHIPID_STM32_L45x_L46x, + .dev_type = "L45x/46x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 + // and tables 7 on pages 73-74) + // SRAM1 is 128k at 0x20000000; + // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, + // page 68, also fig 2 on page 63) + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system + // memory, also fig 2 on page 63) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L0xx Category 1 + // RM0451, RM0377 + .chip_id = STLINK_CHIPID_STM32_L011, + .dev_type = "L01x/L02x", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x2000, + }, + { + // STM32G030/031/041 + // RM0454, RM0444 + .chip_id = STLINK_CHIPID_STM32_G0_CAT1, + .dev_type = "G03x/G04x", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x2000, // 8k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G071/081 + // RM0444 + .chip_id = STLINK_CHIPID_STM32_G0_CAT2, + .dev_type = "G07x/G08x", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x9000, // 36k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G0B1/G0C1 + // RM0444 + .chip_id = STLINK_CHIPID_STM32_G0_CAT3, + .dev_type = "G0Bx/G0Cx", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x9000, // 36k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_DUAL_BANK, + }, + { + // STM32G051/G061 + // RM0444 + .chip_id = STLINK_CHIPID_STM32_G0_CAT4, + .dev_type = "G05x/G06x", + .flash_type = STLINK_FLASH_TYPE_G0, + .flash_size_reg = 0x1FFF75E0, // Section 38.2 + .flash_pagesize = 0x800, // 2k (sec 3.2) + .sram_size = 0x9000, // 36k (sec 2.3) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) + .option_base = STM32_G0_OPTION_BYTES_BASE, + .option_size = 4, + }, + { + // STM32G431/441 + // RM0440 + .chip_id = STLINK_CHIPID_STM32_G4_CAT2, + .dev_type = "G43x/G44x", + .flash_type = STLINK_FLASH_TYPE_G4, + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = 0x800, // 2k (sec 3.3.1) + // SRAM1 is 16k at 0x20000000 + // SRAM2 is 6k at 0x20014000 + // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x8000, // 32k (sec 2.4) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32G471/473/474/483/484 + // RM0440 + .chip_id = STLINK_CHIPID_STM32_G4_CAT3, + .dev_type = "G47x/G48x", + .flash_type = STLINK_FLASH_TYPE_G4, + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = 0x800, // 2k (sec 3.3.1) + // SRAM1 is 80k at 0x20000000 + // SRAM2 is 16k at 0x20014000 + // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x20000, // 128k (sec 2.4) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32G491/G4A1 + // RM0440 + .chip_id = STLINK_CHIPID_STM32_G4_CAT4, + .dev_type = "G49x/G4Ax", + .flash_type = STLINK_FLASH_TYPE_G4, + .flash_size_reg = 0x1FFF75E0, // Section 47.2 + .flash_pagesize = 0x800, // 2k (sec 3.3.1) + // SRAM1 is 80k at 0x20000000 + // SRAM2 is 16k at 0x20014000 + // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 + .sram_size = 0x1C000, // 112k (sec 2.4) + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7000, // 28k (table 2) + .option_base = STM32_G4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32H742/743/753 (from RM0433) + .chip_id = STLINK_CHIPID_STM32_H74xxx, + .dev_type = "H74x/H75x", + .flash_type = STLINK_FLASH_TYPE_H7, + .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) + .flash_pagesize = 0x20000, // 128k sector (pg147) + .sram_size = 0x20000, // 128k "DTCM" from Table 7 + .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 + .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 + .option_base = STM32_H7_OPTION_BYTES_BASE, + .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32H7A3/7B3 + // RM0455 + .chip_id = STLINK_CHIPID_STM32_H7Ax, + .dev_type = "H7Ax/H7Bx", + .flash_type = STLINK_FLASH_TYPE_H7, + .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) + .flash_pagesize = 0x2000, // 8k sector (p.146) + .sram_size = 0x20000, // 128k "DTCM" (Figure 1) + .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 12-14) + .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to + // two banks (Table 12-14) + .option_base = STM32_H7_OPTION_BYTES_BASE, + .option_size = 44, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32H72x/H73x + // RM0468 + .chip_id = STLINK_CHIPID_STM32_H72x, + .dev_type = "H72x/H73x", + .flash_type = STLINK_FLASH_TYPE_H7, + .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) + .flash_pagesize = 0x20000, // 128k sector (p.152) + .sram_size = 0x20000, // 128k "DTCM" (Figure 1) + .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 6) + .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) + .option_base = STM32_H7_OPTION_BYTES_BASE, + .option_size = 44, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + + + { + // STM32F1xx medium-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_MD, + .dev_type = "F1xx Medium-density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x5000, + .bootrom_base = 0x1ffff000, // 2.3.3 "Embedded Flash memory" + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx + // RM0033 (rev 5) + .chip_id = STLINK_CHIPID_STM32_F2, + .dev_type = "F2xx", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx low-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_LD, + .dev_type = "F1 Low-density device", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2800, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx high-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_HD, + .dev_type = "F1xx High-density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx connectivity devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_CONN, + .dev_type = "F1xx CL", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1fffb000, + .bootrom_size = 0x4800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx low- and medium-density value line devices + // RM0041 + .chip_id = STLINK_CHIPID_STM32_F1_VL_MD_LD, + .dev_type = "F1xx Value Line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2000, // 0x1000 for low density devices + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx high-density value line devices + // RM0041 + .chip_id = STLINK_CHIPID_STM32_F1_VL_HD, + .dev_type = "F1xx High-density value line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x8000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx XL-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_XLD, + .dev_type = "F1xx XL-density", + .flash_type = STLINK_FLASH_TYPE_F1_XL, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x18000, + .bootrom_base = 0x1fffe000, + .bootrom_size = 0x1800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32WB55xx, STM32WB35xx, STM32WB50CG/30CE + // RM0434, RM0471 + .chip_id = STLINK_CHIPID_STM32_WB55, + .dev_type = "WB5x/3x", + .flash_type = STLINK_FLASH_TYPE_WB, + .flash_size_reg = 0x1FFF75E0, + .flash_pagesize = 0x1000, // 4k + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, // see the memory map + .bootrom_size = 0x7000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32WLEx + .chip_id = STLINK_CHIPID_STM32_WLE, + .dev_type = "WLEx", + .flash_type = STLINK_FLASH_TYPE_WB, + .flash_size_reg = 0x1FFF75E0, + .flash_pagesize = 0x800, // 2k + .sram_size = 0x10000, + .bootrom_base = 0x1fff0000, // see the memory map + .bootrom_size = 0x7000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // unknown + .chip_id = STLINK_CHIPID_UNKNOWN, + .dev_type = "unknown device", + .flash_type = STLINK_FLASH_TYPE_UNKNOWN, + .flash_size_reg = 0x0, + .flash_pagesize = 0x0, + .sram_size = 0x0, + .bootrom_base = 0x0, + .bootrom_size = 0x0, + }, +}; \ No newline at end of file From 89f54e088417cacdf937f92e7a5e5f55728e03c7 Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Wed, 5 Jan 2022 13:51:47 +0400 Subject: [PATCH 1265/1435] Update usb.c --- src/stlink-lib/usb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index e07918800..793a1f68d 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1221,6 +1221,8 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, libusb_free_device_list(list, 1); +// libusb_kernel_driver_active is not available on Windows. +#if !defined(_WIN32) if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { ret = libusb_detach_kernel_driver(slu->usb_handle, 0); @@ -1229,6 +1231,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, goto on_libusb_error; } } +#endif if (libusb_get_configuration(slu->usb_handle, &config)) { // this may fail for a previous configured device From ab5c47b6cec32a3f0b80708cc8f2d7a1821dd512 Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Thu, 6 Jan 2022 20:19:01 +0400 Subject: [PATCH 1266/1435] Update usb.c (correct typo) There are 2 calls _stlink_usb_exit_dfu_mode In usb.c (at lines 1284 and 1293) and no single call _stlink_usb_exit_debug_mode. Apparently typo on line 1293 --- src/stlink-lib/usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 793a1f68d..65e8f4e25 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1290,7 +1290,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, // the NRST pin must be pull down before selecting the SWD/JTAG mode if (mode == STLINK_DEV_DEBUG_MODE) { DLOG("-- exit_debug_mode\n"); - _stlink_usb_exit_dfu_mode(sl); + _stlink_usb_exit_debug_mode(sl); } _stlink_usb_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); From e62b9e1f2a1b6dea7e9ccb053c14c2c6ad0b57d7 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 6 Jan 2022 19:30:49 +0100 Subject: [PATCH 1267/1435] [refactoring] Clean-up & update for chipid files - F0, F1, F2, F3, F4, F7 - G0, G4 - H7 - L0, L5, U5 - WB, WL --- config/chips/F03x.chip | 21 +- config/chips/F04x.chip | 21 +- config/chips/F05x.chip | 21 +- config/chips/F07x.chip | 21 +- config/chips/F09x.chip | 20 +- config/chips/F1xx_CL.chip | 12 +- config/chips/F1xx_HD.chip | 10 +- config/chips/F1xx_LD.chip | 10 +- config/chips/F1xx_MD.chip | 12 +- config/chips/F1xx_VL_HD.chip | 10 +- config/chips/F1xx_VL_MD_LD.chip | 10 +- config/chips/F1xx_XLD.chip | 12 +- config/chips/F2xx.chip | 12 +- config/chips/F301_F302_F318.chip | 21 +- config/chips/F302_F303_F358.chip | 21 +- config/chips/F302_F303_F398_HD.chip | 14 + config/chips/F303_F328_F334.chip | 21 +- config/chips/F303_high_density.chip | 13 - config/chips/F37x.chip | 21 +- config/chips/F401xB_C.chip | 13 - config/chips/F401xB_xC.chip | 14 + config/chips/F401xD_E.chip | 13 - config/chips/F401xD_xE.chip | 14 + config/chips/F410.chip | 17 +- config/chips/F411xC_E.chip | 13 - config/chips/F411xC_xE.chip | 14 + config/chips/F412.chip | 17 +- config/chips/F413_F423.chip | 17 +- config/chips/F42x_F43x.chip | 17 +- config/chips/F446.chip | 21 +- config/chips/F46x_F47x.chip | 17 +- config/chips/F4x5_F4x7.chip | 21 +- config/chips/F72x_F73x.chip | 21 +- config/chips/F74x_F75x.chip | 21 +- config/chips/F76x_F77x.chip | 23 +- config/chips/G03x_G04x.chip | 21 +- config/chips/G05x_G06x.chip | 21 +- config/chips/G07x_G08x.chip | 21 +- config/chips/G0Bx_G0Cx.chip | 21 +- config/chips/G43x_G44x.chip | 21 +- config/chips/G47x_G48x.chip | 23 +- config/chips/G49x_G4Ax.chip | 21 +- config/chips/H72x_H73x.chip | 21 +- config/chips/H74x_H75x.chip | 23 +- config/chips/H7Ax_H7Bx.chip | 23 +- config/chips/L01x_L02x.chip | 13 - config/chips/L0xx_Cat_2.chip | 13 - config/chips/L0xx_Cat_3.chip | 13 - config/chips/L0xx_Cat_5.chip | 13 - config/chips/L0xxx_Cat_1.chip | 14 + config/chips/L0xxx_Cat_2.chip | 14 + config/chips/L0xxx_Cat_3.chip | 14 + config/chips/L0xxx_Cat_5.chip | 14 + config/chips/L5x5.chip | 15 + config/chips/U5x5.chip | 15 + config/chips/WBx0_WBx5.chip | 14 + config/chips/WBx5_WBx0.chip | 14 - config/chips/{WLEx.chip => WLx5.chip} | 12 +- config/chips/unknown_device.chip | 2 +- inc/stm32.h | 13 +- src/stlink-lib/chipid.c | 12 +- src/stlink-lib/chipid_db_old.h | 1023 +++++++++++++------------ 62 files changed, 1047 insertions(+), 973 deletions(-) create mode 100644 config/chips/F302_F303_F398_HD.chip delete mode 100644 config/chips/F303_high_density.chip delete mode 100644 config/chips/F401xB_C.chip create mode 100644 config/chips/F401xB_xC.chip delete mode 100644 config/chips/F401xD_E.chip create mode 100644 config/chips/F401xD_xE.chip delete mode 100644 config/chips/F411xC_E.chip create mode 100644 config/chips/F411xC_xE.chip delete mode 100644 config/chips/L01x_L02x.chip delete mode 100644 config/chips/L0xx_Cat_2.chip delete mode 100644 config/chips/L0xx_Cat_3.chip delete mode 100644 config/chips/L0xx_Cat_5.chip create mode 100644 config/chips/L0xxx_Cat_1.chip create mode 100644 config/chips/L0xxx_Cat_2.chip create mode 100644 config/chips/L0xxx_Cat_3.chip create mode 100644 config/chips/L0xxx_Cat_5.chip create mode 100644 config/chips/L5x5.chip create mode 100644 config/chips/U5x5.chip create mode 100644 config/chips/WBx0_WBx5.chip delete mode 100644 config/chips/WBx5_WBx0.chip rename config/chips/{WLEx.chip => WLx5.chip} (54%) diff --git a/config/chips/F03x.chip b/config/chips/F03x.chip index eed78e4e2..ea7fdb9e2 100644 --- a/config/chips/F03x.chip +++ b/config/chips/F03x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F03x +# Chip-ID file for STM32F03x device # -chip_id 0x444 -description F03x -flash_type 1 -flash_pagesize 0x400 -sram_size 0x1000 +dev_type STM32F03x +ref_manual_id 0091 +chip_id 0x444 // STLINK_CHIPID_STM32_F0xx_SMALL +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x400 // 1 KB +sram_size 0x1000 // 4 KB bootrom_base 0x1fffec00 -bootrom_size 0xc00 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0xc00 // 3 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 1f2a2043e..3e702585b 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F04x +# Chip-ID file for STM32F04x device # -chip_id 0x445 -description F04x -flash_type 1 -flash_pagesize 0x400 -sram_size 0x1800 +dev_type STM32F04x +ref_manual_id 0091 +chip_id 0x445 // STLINK_CHIPID_STM32_F04 +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x400 // 1 KB +sram_size 0x1800 // 6 KB bootrom_base 0x1fffec00 -bootrom_size 0xc00 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0xc00 // 3 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F05x.chip b/config/chips/F05x.chip index 787adb6bf..1a4f61386 100644 --- a/config/chips/F05x.chip +++ b/config/chips/F05x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F05x +# Chip-ID file for STM32F05x device # -chip_id 0x440 -description F05x -flash_type 1 -flash_pagesize 0x400 -sram_size 0x2000 +dev_type STM32F05x +ref_manual_id 0091 +chip_id 0x440 // STLINK_CHIPID_STM32_F0 +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x400 // 1 KB +sram_size 0x2000 // 8 KB bootrom_base 0x1fffec00 -bootrom_size 0xc00 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0xc00 // 3 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index e893a5457..2a577b7b4 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F07x +# Chip-ID file for STM32F07x device # -chip_id 0x448 -description F07x -flash_type 1 -flash_pagesize 0x800 -sram_size 0x4000 +dev_type STM32F07x +ref_manual_id 0091 +chip_id 0x448 // STLINK_CHIPID_STM32_F0_CAN +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x4000 // 16 KB bootrom_base 0x1fffc800 -bootrom_size 0x3000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x3000 // 12 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none - diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index 267a2612f..9f419893e 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -1,13 +1,15 @@ -# Chip-ID file for F09x +# Chip-ID file for STM32F09x device # -chip_id 0x442 -description F09x -flash_type 1 -flash_pagesize 0x800 -sram_size 0x8000 +dev_type STM32F09x +ref_manual_id 0091 +chip_id 0x442 // STLINK_CHIPID_STM32_F09x +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x8000 // 32 KB bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags none diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index 6282bc2ee..4c8bb0b8d 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -1,15 +1,15 @@ -# Chip-ID file for STM32F1xx CL device +# Chip-ID file for STM32F1xx Connectivity Line device # -dev_type STM32F1xx Connectivity Line device +dev_type STM32F1xx_CL ref_manual_id 0008 chip_id 0x418 // STLINK_CHIPID_STM32_F1_CONN flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x800 -sram_size 0x10000 +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB bootrom_base 0x1fffb000 -bootrom_size 0x4800 +bootrom_size 0x4800 // 18 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_HD.chip b/config/chips/F1xx_HD.chip index 72ad9fa75..18757029a 100644 --- a/config/chips/F1xx_HD.chip +++ b/config/chips/F1xx_HD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32F1xx high density device # -dev_type F1xx high density device +dev_type F1xx_HD ref_manual_id 0008 chip_id 0x414 // STLINK_CHIPID_STM32_F1_HD flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x800 -sram_size 0x10000 +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 +bootrom_size 0x800 // 2 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_LD.chip b/config/chips/F1xx_LD.chip index 8a3682755..8a8f5867d 100644 --- a/config/chips/F1xx_LD.chip +++ b/config/chips/F1xx_LD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32F1 low density device # -dev_type STM32F1xx low density device +dev_type STM32F1xx_LD ref_manual_id 0008 chip_id 0x412 // STLINK_CHIPID_STM32_F1_LD flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x400 -sram_size 0x2800 +flash_pagesize 0x400 // 1 KB +sram_size 0x2800 // 10 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 +bootrom_size 0x800 // 2 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_MD.chip b/config/chips/F1xx_MD.chip index f3da99493..be492f54a 100644 --- a/config/chips/F1xx_MD.chip +++ b/config/chips/F1xx_MD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32F1xx medium density device # -dev_type STM32F1xx medium density device +dev_type STM32F1xx_MD ref_manual_id 0008 chip_id 0x410 // STLINK_CHIPID_STM32_F1_MD flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x400 -sram_size 0x5000 -bootrom_base 0x1ffff000 // Section 2.3.3 "Embedded Flash memory" -bootrom_size 0x800 +flash_pagesize 0x400 // 1 KB +sram_size 0x5000 // 20 KB +bootrom_base 0x1ffff000 +bootrom_size 0x800 // 2 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_VL_HD.chip b/config/chips/F1xx_VL_HD.chip index f46945a94..f5ca6b023 100644 --- a/config/chips/F1xx_VL_HD.chip +++ b/config/chips/F1xx_VL_HD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32F1xx high density Value Line device # -dev_type STM32F1xx Value Line high density device +dev_type STM32F1xx_VL_HD ref_manual_id 0041 chip_id 0x428 // STLINK_CHIPID_STM32_F1_VL_HD flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x800 -sram_size 0x8000 +flash_pagesize 0x800 // 2 KB +sram_size 0x8000 // 32 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 +bootrom_size 0x800 // 2 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_VL_MD_LD.chip b/config/chips/F1xx_VL_MD_LD.chip index 2bff05b82..e79668c70 100644 --- a/config/chips/F1xx_VL_MD_LD.chip +++ b/config/chips/F1xx_VL_MD_LD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STMF1xx Value Line medium & low density device # -dev_type STM32F1xx Value Line medium & low density device +dev_type STM32F1xx_VL_MD_LD ref_manual_id 0041 chip_id 0x420 // STLINK_CHIPID_STM32_F1_VL_MD_LD flash_type 1 // STLINK_FLASH_TYPE_F0 flash_size_reg 0x1ffff7e0 -flash_pagesize 0x400 -sram_size 0x2000 // 0x1000 for low density devices +flash_pagesize 0x400 // 1 KB +sram_size 0x2000 // 8 KB /* 0x1000 for low density devices */ bootrom_base 0x1ffff000 -bootrom_size 0x800 +bootrom_size 0x800 // 2 KB option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE -option_size 0x10 // 16 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip index 90264ce0f..d7d8cf2b7 100644 --- a/config/chips/F1xx_XLD.chip +++ b/config/chips/F1xx_XLD.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32F1xx XL density device # -dev_type STM32F1xx XL density device +dev_type STM32F1xx_XLD ref_manual_id 0008 -chip_id 0x430 // STLINK_CHIPID_STM32_F1_XLD -flash_type 2 // STLINK_FLASH_TYPE_F1_XL +chip_id 0x430 // STLINK_CHIPID_STM32_F1_XLD +flash_type 2 // STLINK_FLASH_TYPE_F1_XL flash_size_reg 0x1ffff7e0 -flash_pagesize 0x800 -sram_size 0x18000 +flash_pagesize 0x800 // 2 KB +sram_size 0x18000 // 96 KB bootrom_base 0x1fffe000 -bootrom_size 0x1800 +bootrom_size 0x1800 // 6 KB option_base 0x0 option_size 0x0 flags swo diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip index ce2e9e698..67c225af5 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2xx.chip @@ -1,14 +1,14 @@ -# Chip-ID file for STM32F2xx device (STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx) +# Chip-ID file for STM32F2xx device # -dev_type STM32F2xx device +dev_type STM32F2xx ref_manual_id 0033 chip_id 0x411 // STLINK_CHIPID_STM32_F2 flash_type 3 // STLINK_FLASH_TYPE_F4 flash_size_reg 0x1fff7a22 -flash_pagesize 0x20000 -sram_size 0x20000 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x1fffc000 // STM32_F2_OPTION_BYTES_BASE -option_size 0x4 // 4 +option_size 0x4 // 4 B flags swo diff --git a/config/chips/F301_F302_F318.chip b/config/chips/F301_F302_F318.chip index 429c836b4..ee71dfe90 100644 --- a/config/chips/F301_F302_F318.chip +++ b/config/chips/F301_F302_F318.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F301/F302/F318 +# Chip-ID file for STM32F3xx device (F301x6/8, F302x6x8, F318x8) # -chip_id 0x439 -description F301/F302/F318 -flash_type 1 -flash_pagesize 0x800 -sram_size 0xa000 +dev_type STM32F301_F302_F318 +ref_manual_id 0365 // also RM0366 +chip_id 0x439 // STLINK_CHIPID_STM32_F3xx_SMALL +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0xa000 // 40 KB bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F302_F303_F358.chip b/config/chips/F302_F303_F358.chip index ffd1491ff..64d0651f2 100644 --- a/config/chips/F302_F303_F358.chip +++ b/config/chips/F302_F303_F358.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F302/F303/F358 +# Chip-ID file for STM32F3xx device (F302xBxC, F303xB/C, F358) # -chip_id 0x422 -description F302/F303/F358 -flash_type 1 -flash_pagesize 0x800 -sram_size 0xa000 +dev_type STM32F302_F303_358 +ref_manual_id 0365 // also RM0316 +chip_id 0x422 // STLINK_CHIPID_STM32_F3 +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0xa000 // 40 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x800 // 2 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F302_F303_F398_HD.chip b/config/chips/F302_F303_F398_HD.chip new file mode 100644 index 000000000..eaf36b74c --- /dev/null +++ b/config/chips/F302_F303_F398_HD.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F3xx high density device (F302xD/E, F303xD/E, F398xE) +# +dev_type STM32F302_F303_F398_HD +ref_manual_id 0365 // also RM0316 (Rev 5) +chip_id 0x446 // STLINK_CHIPID_STM32_F303_HD +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB +bootrom_base 0x1fffd800 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B +flags swo diff --git a/config/chips/F303_F328_F334.chip b/config/chips/F303_F328_F334.chip index 5df2a9bbb..2ecdbfb71 100644 --- a/config/chips/F303_F328_F334.chip +++ b/config/chips/F303_F328_F334.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F303/F328/F334 +# Chip-ID file for STM32F3xx device (F303x6/8, F328, F334) # -chip_id 0x438 -description F303/F328/F334 -flash_type 1 -flash_pagesize 0x800 -sram_size 0x3000 +dev_type STM32F303_F328_F334 +ref_manual_id 0364 // also RM0316 +chip_id 0x438 // STLINK_CHIPID_STM32_F334 +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0x3000 // 12 KB bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x2000 // 8 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F303_high_density.chip b/config/chips/F303_high_density.chip deleted file mode 100644 index 748c27cbc..000000000 --- a/config/chips/F303_high_density.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F303 high density -# -chip_id 0x446 -description F303 high density -flash_type 1 -flash_pagesize 0x800 -sram_size 0x10000 -bootrom_base 0x1fffd800 -bootrom_size 0x2000 -option_base 0x1ffff800 -option_size 0x10 -flags swo - diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index 92201657d..1bd7ac421 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F37x +# Chip-ID file for STM32F37x device # -chip_id 0x432 -description F37x -flash_type 1 -flash_pagesize 0x800 -sram_size 0xa000 +dev_type STM32F37x +ref_manual_id 0313 +chip_id 0x432 // STLINK_CHIPID_STM32_F37x +flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_size_reg 0x1ffff7cc +flash_pagesize 0x800 // 2 KB +sram_size 0xa000 // 40 KB bootrom_base 0x1ffff000 -bootrom_size 0x800 -option_base 0x1ffff800 -option_size 0x10 +bootrom_size 0x800 // 2 KB +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo - diff --git a/config/chips/F401xB_C.chip b/config/chips/F401xB_C.chip deleted file mode 100644 index 09e998dba..000000000 --- a/config/chips/F401xB_C.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F401xB/C -# -chip_id 0x423 -description F401xB/C -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x10000 -bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F401xB_xC.chip b/config/chips/F401xB_xC.chip new file mode 100644 index 000000000..fc93c2f1a --- /dev/null +++ b/config/chips/F401xB_xC.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F401xB/xC device +# +dev_type STM32F401xB_xC +ref_manual_id 0368 +chip_id 0x423 // STLINK_CHIPID_STM32_F4_LP +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x10000 // 64 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7800 // 30 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F401xD_E.chip b/config/chips/F401xD_E.chip deleted file mode 100644 index 5b70d7d86..000000000 --- a/config/chips/F401xD_E.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F401xD/E -# -chip_id 0x433 -description F401xD/E -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x18000 -bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip new file mode 100644 index 000000000..e31d5eace --- /dev/null +++ b/config/chips/F401xD_xE.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F401xD/xE device +# +dev_type STM32F401xD_xE +ref_manual_id 0368 +chip_id 0x433 // STLINK_CHIPID_STM32_F4_DE +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x18000 // 96 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7800 // 30 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F410.chip b/config/chips/F410.chip index ae199d9c4..a8a7fbad0 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F410 +# Chip-ID file for STM32F410 device # -chip_id 0x458 -description F410 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x8000 +dev_type STM32F410 +ref_manual_id 0401 +chip_id 0x458 // STLINK_CHIPID_STM32_F410 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x8000 // 32 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F411xC_E.chip b/config/chips/F411xC_E.chip deleted file mode 100644 index d344489c5..000000000 --- a/config/chips/F411xC_E.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for F411xC/E -# -chip_id 0x431 -description F411xC/E -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x20000 -bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/F411xC_xE.chip b/config/chips/F411xC_xE.chip new file mode 100644 index 000000000..cf2cbd2c1 --- /dev/null +++ b/config/chips/F411xC_xE.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32F411xC/xE device +# +dev_type STM32F411xC_xE +ref_manual_id 0383 +chip_id 0x431 // STLINK_CHIPID_STM32_F411xx +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x20000 // 128 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7800 // 30 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/F412.chip b/config/chips/F412.chip index 3212a340c..4c866a3c5 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F412 +# Chip-ID file for STM32F412 device # -chip_id 0x441 -description F412 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x40000 +dev_type STM32F412 +ref_manual_id 0402 +chip_id 0x441 // STLINK_CHIPID_STM32_F412 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x40000 // 256 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F413_F423.chip b/config/chips/F413_F423.chip index 647775eeb..81ca585f6 100644 --- a/config/chips/F413_F423.chip +++ b/config/chips/F413_F423.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F413/F423 +# Chip-ID file for STM32F413 / STM32F423 device # -chip_id 0x463 -description F413/F423 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x50000 +dev_type STM32F413_F423 +ref_manual_id 0430 // RM0430 (Rev 2) +chip_id 0x463 // STLINK_CHIPID_STM32_F413 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x50000 // 320 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 3184d0d4f..2ec8fb8e8 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F42x/F43x +# Chip-ID file for STM32F42x / STM32F43x device # -chip_id 0x419 -description F42x/F43x -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x40000 +dev_type STM32F42x_F43x +ref_manual_id 0090 // RM0090 (Rev. 2) +chip_id 0x463 // STLINK_CHIPID_STM32_F4_HD +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x40000 // 256 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 86cee6a56..8cebe358e 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F446 +# Chip-ID file for STM32F446 device # -chip_id 0x421 -description F446 -flash_type 3 -flash_pagesize 0x20000 -sram_size 0x20000 +dev_type STM32F446 +ref_manual_id 0390 +chip_id 0x421 // STLINK_CHIPID_STM32_F446 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x1fffc000 -option_size 0x4 +bootrom_size 0x7800 // 30 KB +option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index ee5f6a5a7..2e4055f2c 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F46x/F47x +# Chip-ID file for STM32F46x / STM32F47x device # -chip_id 0x434 -description F46x/F47x -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x40000 +dev_type STM32F46x_F47x +ref_manual_id 0090 // RM0090 (Rev. 2) +chip_id 0x434 // STLINK_CHIPID_STM32_F4_DSI +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x40000 // 256 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 +bootrom_size 0x7800 // 30 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/F4x5_F4x7.chip b/config/chips/F4x5_F4x7.chip index b19e4a5b3..9313c8ae1 100644 --- a/config/chips/F4x5_F4x7.chip +++ b/config/chips/F4x5_F4x7.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F4x5/F4x7 +# Chip-ID file for STM32F4x5 / STM32F4x7 device # -chip_id 0x413 -description F4x5/F4x7 -flash_type 3 -flash_pagesize 0x4000 -sram_size 0x30000 +dev_type STM32F4x5_F4x7 +ref_manual_id 0090 // RM0090 (Rev. 2) +chip_id 0x413 // STLINK_CHIPID_STM32_F4 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1fff7a22 +flash_pagesize 0x4000 // 16 KB +sram_size 0x30000 // 192 KB bootrom_base 0x1fff0000 -bootrom_size 0x7800 -option_base 0x40023c14 -option_size 0x4 +bootrom_size 0x7800 // 30 KB +option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index 2836040ac..37dcd1234 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F72x/F73x +# Chip-ID file for STM32F72x / STM32F73x device # -chip_id 0x452 -description F72x/F73x -flash_type 3 -flash_pagesize 0x800 -sram_size 0x40000 +dev_type STM32F72x_F73x +ref_manual_id 0431 +chip_id 0x452 // STLINK_CHIPID_STM32_F72xxx +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1ff07a22 +flash_pagesize 0x800 // 2 KB +sram_size 0x40000 // 256 KB bootrom_base 0x100000 -bootrom_size 0xedc0 -option_base 0x0 -option_size 0x0 +bootrom_size 0xedc0 // 59.4375 KB +option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE +option_size 0x20 // 32 B flags swo - diff --git a/config/chips/F74x_F75x.chip b/config/chips/F74x_F75x.chip index 0604b299d..96cc95217 100644 --- a/config/chips/F74x_F75x.chip +++ b/config/chips/F74x_F75x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F74x/F75x +# Chip-ID file for STM32F74x / STM32F75x device # -chip_id 0x449 -description F74x/F75x -flash_type 3 -flash_pagesize 0x800 -sram_size 0x50000 +dev_type STM32F74x_F75x +ref_manual_id 0385 +chip_id 0x449 // STLINK_CHIPID_STM32_F7 +flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_size_reg 0x1ff0f442 +flash_pagesize 0x800 // 2 KB +sram_size 0x50000 // 320 KB bootrom_base 0x100000 -bootrom_size 0xedc0 -option_base 0x0 -option_size 0x0 +bootrom_size 0xedc0 // 59.4375 KB +option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE +option_size 0x20 // 32 B flags swo - diff --git a/config/chips/F76x_F77x.chip b/config/chips/F76x_F77x.chip index 304c99191..a93aba2be 100644 --- a/config/chips/F76x_F77x.chip +++ b/config/chips/F76x_F77x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for F76x/F77x +# Chip-ID file for STM32F76x / STM32F77x device # -chip_id 0x451 -description F76x/F77x -flash_type 4 -flash_pagesize 0x800 -sram_size 0x80000 +dev_type STM32F76x_F77x +ref_manual_id 0410 +chip_id 0x451 // STLINK_CHIPID_STM32_F76xxx +flash_type 4 // STLINK_FLASH_TYPE_F7 +flash_size_reg 0x1ff0f442 +flash_pagesize 0x800 // 2 KB +sram_size 0x80000 // 512 KB bootrom_base 0x200000 -bootrom_size 0xedc0 -option_base 0x1fff0000 -option_size 0x20 -flags dualbank swo - +bootrom_size 0xedc0 // 59.4375 KB +option_base 0x1fff0000 // STM32_F7_OPTION_BYTES_BASE /* Used for reading back option bytes, writing uses FLASH_F7_OPTCR and FLASH_F7_OPTCR1 */ +option_size 0x20 // 32 B +flags swo dualbank diff --git a/config/chips/G03x_G04x.chip b/config/chips/G03x_G04x.chip index 7c5a00c58..a21a9898f 100644 --- a/config/chips/G03x_G04x.chip +++ b/config/chips/G03x_G04x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G03x/G04x +# Chip-ID file for STM32G030 / STM32G031 / STM32G041 device # -chip_id 0x466 -description G03x/G04x -flash_type 7 -flash_pagesize 0x800 -sram_size 0x2000 +dev_type STM32G03x_G04x +ref_manual_id 0444 // also RM454 +chip_id 0x466 // STLINK_CHIPID_STM32_G0_CAT1 +flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x2000 // 8 KB bootrom_base 0x1fff0000 -bootrom_size 0x2000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x2000 // 8 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags none - diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index 45295ec6e..89af0825c 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G05x/G06x +# Chip-ID file for STM32G05x / STM32G06x device # -chip_id 0x456 -description G05x/G06x -flash_type 7 -flash_pagesize 0x800 -sram_size 0x9000 +dev_type STM32G05x_G06x +ref_manual_id 0444 +chip_id 0x456 // STLINK_CHIPID_STM32_G0_CAT4 +flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x9000 // 36 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags none - diff --git a/config/chips/G07x_G08x.chip b/config/chips/G07x_G08x.chip index 7bddcd82c..c54de398f 100644 --- a/config/chips/G07x_G08x.chip +++ b/config/chips/G07x_G08x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G07x/G08x +# Chip-ID file for STM32G07x / STM32G08x device # -chip_id 0x460 -description G07x/G08x -flash_type 7 -flash_pagesize 0x800 -sram_size 0x9000 +dev_type STM32G07x_G08x +ref_manual_id 0444 +chip_id 0x460 // STLINK_CHIPID_STM32_G0_CAT2 +flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x9000 // 36 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags none - diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index 98e503569..d8e0eb042 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G0Bx/G0Cx +# Chip-ID file for STM32G0Bx / STM32G0Cx device # -chip_id 0x467 -description G0Bx/G0Cx -flash_type 7 -flash_pagesize 0x800 -sram_size 0x9000 +dev_type STM32G0Bx_G0Cx +ref_manual_id 0444 +chip_id 0x467 // STLINK_CHIPID_STM32_G0_CAT3 +flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x9000 // 36 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags dualbank - diff --git a/config/chips/G43x_G44x.chip b/config/chips/G43x_G44x.chip index 033f1dd80..455d65b8c 100644 --- a/config/chips/G43x_G44x.chip +++ b/config/chips/G43x_G44x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G43x/G44x +# Chip-ID file for STM32G43x / STM32G44x device # -chip_id 0x468 -description G43x/G44x -flash_type 8 -flash_pagesize 0x800 -sram_size 0x8000 +dev_type STM32G43x_G44x +ref_manual_id 0440 +chip_id 0x468 // STLINK_CHIPID_STM32_G4_CAT2 +flash_type 8 // STLINK_FLASH_TYPE_G4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x8000 // 32 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1ffff800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/G47x_G48x.chip b/config/chips/G47x_G48x.chip index fa331650f..250905c68 100644 --- a/config/chips/G47x_G48x.chip +++ b/config/chips/G47x_G48x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G47x/G48x +# Chip-ID file for STM32G47x / STM32G48x device # -chip_id 0x469 -description G47x/G48x -flash_type 8 -flash_pagesize 0x800 -sram_size 0x20000 +dev_type STM32G47x_G48x +ref_manual_id 0440 +chip_id 0x469 // STLINK_CHIPID_STM32_G4_CAT3 +flash_type 8 // STLINK_FLASH_TYPE_G4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x20000 // 128 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1ffff800 -option_size 0x4 -flags dualbank swo - +bootrom_size 0x7000 // 28 KB +option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE +option_size 0x4 // 4 B +flags swo dualbank diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip index b764572db..9702541a8 100644 --- a/config/chips/G49x_G4Ax.chip +++ b/config/chips/G49x_G4Ax.chip @@ -1,13 +1,14 @@ -# Chip-ID file for G49x/G4Ax +# Chip-ID file for STM32G49x / STM32G4Ax device # -chip_id 0x479 -description G49x/G4Ax -flash_type 8 -flash_pagesize 0x800 -sram_size 0x1c000 +dev_type STM32G49x_G4Ax +ref_manual_id 0440 +chip_id 0x479 // STLINK_CHIPID_STM32_G4_CAT4 +flash_type 8 // STLINK_FLASH_TYPE_G4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x1c000 // 112 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1ffff800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index df20037d3..183c7d197 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for H72x/H73x +# Chip-ID file for STM32H72x / STM32H73x device # -chip_id 0x483 -description H72x/H73x -flash_type 10 -flash_pagesize 0x20000 -sram_size 0x20000 +dev_type STM32H72x_H73x +ref_manual_id 0468 +chip_id 0x483 // STLINK_CHIPID_STM32_H72x +flash_type 10 // STLINK_FLASH_TYPE_H7 +flash_size_reg 0x1ff1e880 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB "DTCM" bootrom_base 0x1ff00000 -bootrom_size 0x20000 -option_base 0x5200201c -option_size 0x2c +bootrom_size 0x20000 // 128 KB +option_base 0x5200201c // STM32_H7_OPTION_BYTES_BASE +option_size 0x2c // 44 B flags swo - diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 7a4bc86e3..2e543b197 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for H74x/H75x +# Chip-ID file for STM32H74x / STM32H75x device # -chip_id 0x450 -description H74x/H75x -flash_type 10 -flash_pagesize 0x20000 -sram_size 0x20000 +dev_type STM32H74x_H75x +ref_manual_id 0433 +chip_id 0x450 // STLINK_CHIPID_STM32_H74xxx +flash_type 10 // STLINK_FLASH_TYPE_H7 +flash_size_reg 0x1ff1e880 +flash_pagesize 0x20000 // 128 KB +sram_size 0x20000 // 128 KB "DTCM" bootrom_base 0x1ff00000 -bootrom_size 0x20000 -option_base 0x5200201c -option_size 0x2c -flags dualbank swo - +bootrom_size 0x20000 // 128 KB +option_base 0x5200201c // STM32_H7_OPTION_BYTES_BASE +option_size 0x2c // 44 B /* FLASH_OPTSR_CUR to FLASH_BOOT_PRGR */ +flags swo dualbank diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index b9202bd1a..b5fe72119 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for H7Ax/H7Bx +# Chip-ID file for STM32H7Ax / STM32H7Bx device # -chip_id 0x480 -description H7Ax/H7Bx -flash_type 10 -flash_pagesize 0x2000 -sram_size 0x20000 +dev_type STM32H7Ax_H7Bx +ref_manual_id 0455 +chip_id 0x480 // STLINK_CHIPID_STM32_H7Ax +flash_type 10 // STLINK_FLASH_TYPE_H7 +flash_size_reg 0x08fff80c +flash_pagesize 0x2000 // 8 KB +sram_size 0x20000 // 128 KB "DTCM" bootrom_base 0x1ff00000 -bootrom_size 0x20000 -option_base 0x5200201c -option_size 0x2c -flags dualbank swo - +bootrom_size 0x20000 // 128 KB +option_base 0x5200201c // STM32_H7_OPTION_BYTES_BASE +option_size 0x2c // 44 B +flags swo dualbank diff --git a/config/chips/L01x_L02x.chip b/config/chips/L01x_L02x.chip deleted file mode 100644 index c3d2074b9..000000000 --- a/config/chips/L01x_L02x.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L01x/L02x -# -chip_id 0x457 -description L01x/L02x -flash_type 5 -flash_pagesize 0x80 -sram_size 0x2000 -bootrom_base 0x1ff00000 -bootrom_size 0x2000 -option_base 0x0 -option_size 0x0 -flags none - diff --git a/config/chips/L0xx_Cat_2.chip b/config/chips/L0xx_Cat_2.chip deleted file mode 100644 index 47183b8ef..000000000 --- a/config/chips/L0xx_Cat_2.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L0xx Cat.2 -# -chip_id 0x425 -description L0xx Cat.2 -flash_type 5 -flash_pagesize 0x80 -sram_size 0x2000 -bootrom_base 0x1ff0000 -bootrom_size 0x1000 -option_base 0x1ff80000 -option_size 0x14 -flags none - diff --git a/config/chips/L0xx_Cat_3.chip b/config/chips/L0xx_Cat_3.chip deleted file mode 100644 index 6d9fcc105..000000000 --- a/config/chips/L0xx_Cat_3.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L0xx Cat.3 -# -chip_id 0x417 -description L0xx Cat.3 -flash_type 5 -flash_pagesize 0x80 -sram_size 0x2000 -bootrom_base 0x1ff0000 -bootrom_size 0x1000 -option_base 0x1ff80000 -option_size 0x14 -flags none - diff --git a/config/chips/L0xx_Cat_5.chip b/config/chips/L0xx_Cat_5.chip deleted file mode 100644 index 545c1c2ef..000000000 --- a/config/chips/L0xx_Cat_5.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L0xx Cat.5 -# -chip_id 0x447 -description L0xx Cat.5 -flash_type 5 -flash_pagesize 0x80 -sram_size 0x5000 -bootrom_base 0x1ff0000 -bootrom_size 0x2000 -option_base 0x1ff80000 -option_size 0x14 -flags dualbank - diff --git a/config/chips/L0xxx_Cat_1.chip b/config/chips/L0xxx_Cat_1.chip new file mode 100644 index 000000000..1dd8a1acb --- /dev/null +++ b/config/chips/L0xxx_Cat_1.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.1) device (L010x3 / L010x4 / L011x / L021x) +# +dev_type STM32L0xxx_Cat_1 +ref_manual_id 0451 // also RM0377 +chip_id 0x457 // STLINK_CHIPID_STM32_L011 +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x2000 // 8 KB +bootrom_base 0x1ff00000 +bootrom_size 0x2000 // 8 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags none diff --git a/config/chips/L0xxx_Cat_2.chip b/config/chips/L0xxx_Cat_2.chip new file mode 100644 index 000000000..58d6439ba --- /dev/null +++ b/config/chips/L0xxx_Cat_2.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.2) device (L010x6 / L031x / L041x) +# +dev_type STM32L0xxx_Cat_2 +ref_manual_id 0451 // also RM0377 +chip_id 0x425 // STLINK_CHIPID_STM32_L0_CAT2 +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x2000 // 8 KB +bootrom_base 0x1ff00000 +bootrom_size 0x1000 // 4 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags none diff --git a/config/chips/L0xxx_Cat_3.chip b/config/chips/L0xxx_Cat_3.chip new file mode 100644 index 000000000..406c1a037 --- /dev/null +++ b/config/chips/L0xxx_Cat_3.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.3) device (L010x8 / L051x / L053x / L063x) +# +dev_type STM32L0xxx_Cat_3 +ref_manual_id 0451 // also RM0367 & RM0377 +chip_id 0x417 // STLINK_CHIPID_STM32_L0 +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x2000 // 8 KB +bootrom_base 0x1ff00000 +bootrom_size 0x1000 // 4 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags none diff --git a/config/chips/L0xxx_Cat_5.chip b/config/chips/L0xxx_Cat_5.chip new file mode 100644 index 000000000..1a0c387a7 --- /dev/null +++ b/config/chips/L0xxx_Cat_5.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L0xxx (Cat.5) device (L010xB / L071x / L081x / L073x / L083x) +# +dev_type STM32L0xxx_Cat_5 +ref_manual_id 0451 // also RM0367 & RM0377 +chip_id 0x447 // STLINK_CHIPID_STM32_L0_CAT5 +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8007c +flash_pagesize 0x80 // 128 B +sram_size 0x5000 // 20 KB +bootrom_base 0x1ff00000 +bootrom_size 0x2000 // 8 KB +option_base 0x1ff80000 // STM32_L0_OPTION_BYTES_BASE +option_size 0x20 // 32 B +flags dualbank diff --git a/config/chips/L5x5.chip b/config/chips/L5x5.chip new file mode 100644 index 000000000..ce268148b --- /dev/null +++ b/config/chips/L5x5.chip @@ -0,0 +1,15 @@ +# Chip-ID file for STM32L5x2 device +# +dev_type STM32L5x2 +ref_manual_id 0438 +chip_id 0x0 // (temporary setting only!) +flash_type 0 // (temporary setting only!) +flash_size_reg 0x0bfa07a0 +flash_pagesize 0x2000 // 8 KB +sram_size 0x40000 // 256 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags none + diff --git a/config/chips/U5x5.chip b/config/chips/U5x5.chip new file mode 100644 index 000000000..177359cc3 --- /dev/null +++ b/config/chips/U5x5.chip @@ -0,0 +1,15 @@ +# Chip-ID file for STM32U5x5 device +# +dev_type STM32U5x5 +ref_manual_id 0456 +chip_id 0x0 // (temporary setting only!) +flash_type 0 // (temporary setting only!) +flash_size_reg 0x0bfa07a0 +flash_pagesize 0x2000 // 8 KB +sram_size 0xc4800 // 786 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags none + diff --git a/config/chips/WBx0_WBx5.chip b/config/chips/WBx0_WBx5.chip new file mode 100644 index 000000000..ba5fee778 --- /dev/null +++ b/config/chips/WBx0_WBx5.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32WBx0 / STM32WBx5 device +# +dev_type STM32WBx0_WBx5 +ref_manual_id 0434 // also RM0471 +chip_id 0x495 // STLINK_CHIPID_STM32_WB55 +flash_type 9 // STLINK_FLASH_TYPE_WB +flash_size_reg 0x1fff75e0 +flash_pagesize 0x1000 // 4 KB +sram_size 0x40000 // 256 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff8000 +option_size 0x80 // 128 B +flags swo diff --git a/config/chips/WBx5_WBx0.chip b/config/chips/WBx5_WBx0.chip deleted file mode 100644 index 5bd2501e6..000000000 --- a/config/chips/WBx5_WBx0.chip +++ /dev/null @@ -1,14 +0,0 @@ -# Chip-ID file for STM32WBx0 device (STM32WB55xx, STM32WB35xx, STM32WB50CG, STM32WB30CE) -# -dev_type STM32WBx0 device -ref_manual_id 0434 // also RM0471 -chip_id 0x495 // STLINK_CHIPID_STM32_WB55 -flash_type 9 // STLINK_FLASH_TYPE_WB -flash_size_reg 0x1fff75e0 -flash_pagesize 0x1000 // 4k -sram_size 0x40000 -bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x0 -option_size 0x0 -flags swo diff --git a/config/chips/WLEx.chip b/config/chips/WLx5.chip similarity index 54% rename from config/chips/WLEx.chip rename to config/chips/WLx5.chip index e9b6248f6..2dc9ce648 100644 --- a/config/chips/WLEx.chip +++ b/config/chips/WLx5.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32WLEx device # -dev_type STM32WLEx device +dev_type STM32WLEx ref_manual_id 0033 chip_id 0x497 // STLINK_CHIPID_STM32_WLE flash_type 9 // STLINK_FLASH_TYPE_WB flash_size_reg 0x1fff75e0 -flash_pagesize 0x800 // 2k -sram_size 0x10000 +flash_pagesize 0x800 // 2 KB +sram_size 0x10000 // 64 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x0 -option_size 0x0 +bootrom_size 0x7000 // 28 KB +option_base 0x1fffc000 +option_size 0x10 // 16 B flags swo diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index 8f3772e53..1b74f22fa 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -1,6 +1,6 @@ # Chip-ID file for unknown device # -dev_type unknown device +dev_type unknown ref_manual_id 0000 chip_id 0x0 // STLINK_CHIPID_UNKNOWN flash_type 0 // STLINK_FLASH_TYPE_UNKNOWN diff --git a/inc/stm32.h b/inc/stm32.h index 21da2f563..15e0ff147 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -16,19 +16,24 @@ /* Constant STM32 memory map figures */ #define STM32_SRAM_BASE ((uint32_t)0x20000000) #define STM32_FLASH_BASE ((uint32_t)0x08000000) + #define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) + #define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) -#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023C14) -#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) + #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C) +#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) + +#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) + #define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) #define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) -#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) -#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) #define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) #define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 3dd82a1b2..213d43f8c 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -28,8 +28,8 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "# Reference Manual: RM%s\n", dev->ref_manual_id); fprintf(fp, "#\n"); fprintf(fp, "chip_id 0x%x\n", dev->chip_id); - fprintf(fp, "flash_type %d\n", dev->flash_type); - fprintf(fp, "flash_size_reg %x\n", dev->flash_size_reg); + fprintf(fp, "flash_type %d\n", dev->flash_type); + fprintf(fp, "flash_size_reg 0x%x\n", dev->flash_size_reg); fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); fprintf(fp, "sram_size 0x%x\n", dev->sram_size); fprintf(fp, "bootrom_base 0x%x\n", dev->bootrom_base); @@ -42,8 +42,8 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { static int chipid_params_eq(const struct stlink_chipid_params *p1, const struct stlink_chipid_params *p2) { return p1->chip_id == p2->chip_id && - p1->description && p2->description && - strcmp(p1->description, p2->description) == 0 && + p1->dev_type && p2->dev_type && + strcmp(p1->dev_type, p2->dev_type) == 0 && p1->flash_type == p2->flash_type && p1->flash_size_reg == p2->flash_size_reg && p1->flash_pagesize == p2->flash_pagesize && @@ -205,8 +205,8 @@ void dump_chips (void) { fprintf(fp, "# Reference Manual: RM%s\n", ts->ref_manual_id); fprintf(fp, "#\n"); fprintf(fp, "chip_id %x\n", ts->chip_id); - fprintf(fp, "flash_type %x\n", ts->flash_type); - fprintf(fp, "flash_size_reg %x\n", ts->flash_size_reg); + fprintf(fp, "flash_type %x\n", ts->flash_type); + fprintf(fp, "flash_size_reg %x\n", ts->flash_size_reg); fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); fprintf(fp, "sram_size %x\n", ts->sram_size); fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); diff --git a/src/stlink-lib/chipid_db_old.h b/src/stlink-lib/chipid_db_old.h index bc6491ad4..b86b13289 100644 --- a/src/stlink-lib/chipid_db_old.h +++ b/src/stlink-lib/chipid_db_old.h @@ -6,123 +6,6 @@ // config/chips/*.chip file. static struct stlink_chipid_params devices[] = { - { - // STM32F76x/F77x - // RM0410 - .chip_id = STLINK_CHIPID_STM32_F76xxx, - .dev_type = "F76x/F77x", - .flash_type = STLINK_FLASH_TYPE_F7, - .flash_size_reg = 0x1ff0f442, // section 45.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, // "System memory" starting address from - .bootrom_size = 0xEDC0, - .option_base = STM32_F7_OPTION_BYTES_BASE, /* Used for reading back the option - bytes, writing uses FLASH_F7_OPTCR - and FLASH_F7_OPTCR1 */ - .option_size = 0x20, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F74x/F75x - // RM0385, DS10916 - .chip_id = STLINK_CHIPID_STM32_F7, - .dev_type = "F74x/F75x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 41.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F72x/F73x - // RM0431 - .chip_id = STLINK_CHIPID_STM32_F72xxx, - .dev_type = "F72x/F73x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff07a22, // section 35.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F4x5/F4x7 - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4, - .dev_type = "F4x5/F4x7", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x30000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = STM32_F4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F46x/F47x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_DSI, - .dev_type = "F46x/F47x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F42x/F43x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_HD, - .dev_type = "F42x/F43x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_LP, - .dev_type = "F401xB/C", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F411xx, - .dev_type = "F411xC/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_DE, - .dev_type = "F401xD/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, { // STM32L100/L15x/L16x Cat.1 // RM0038 @@ -191,130 +74,137 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F446x family - // RM0390 - .chip_id = STLINK_CHIPID_STM32_F446, - .dev_type = "F446", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, + // STM32L47x/L48x + // RM0351 + .chip_id = STLINK_CHIPID_STM32_L4, + .dev_type = "L47x/L48x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 + // and tables 4-6 on pages 79-81) + // SRAM1 is "up to" 96k in the standard Cortex-M memory map; + // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F410 - // RM0401 - .chip_id = STLINK_CHIPID_STM32_F410, - .dev_type = "F410", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x4000, - .sram_size = 0x8000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L4RX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4Rx, + .dev_type = "L4Rx", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // STM32F303xB/C, STM32F358, STM32F302xBxC - // RM0316, RM0365 - .chip_id = STLINK_CHIPID_STM32_F3, - .dev_type = "F302/F303/F358", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L4PX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4PX, + .dev_type = "L4Px", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // STM32F373Cx/Rx/Vx, STM32F378Cx/Rx/Vx - // RM0313 - .chip_id = STLINK_CHIPID_STM32_F37x, - .dev_type = "F37x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, + // STLINK_CHIPID_STM32_L41x_L42x + // RM0394 (rev 4), DS12469 (rev 5) + .chip_id = STLINK_CHIPID_STM32_L41x_L42x, + .dev_type = "L41x/L42x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, + // sec 47.2, page 1586) + .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) + // SRAM1 is 32k at 0x20000000 + // SRAM2 is 8k at 0x10000000 and 0x20008000 + // (DS12469, sec 3.5, page 18) + .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) + .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) + .bootrom_size = 0x7000, // 28k, same source as base .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F07x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0_CAN, - .dev_type = "F07x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 - .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, + // STLINK_CHIPID_STM32_L43x_L44x + // RM0392 + .chip_id = STLINK_CHIPID_STM32_L43x_L44x, + .dev_type = "L43x/L44x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 + // and tables 7-8 on pages 75-76) + // SRAM1 is "up to" 64k in the standard Cortex-M memory map; + // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0xc000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F05x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0, - .dev_type = "F05x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F412 - // RM0402 - .chip_id = STLINK_CHIPID_STM32_F412, - .dev_type = "F412", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) - .flash_pagesize = 0x4000, // Table 5. Flash module organization ? - .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + // STLINK_CHIPID_STM32_L496x_L4A6x + // RM0351 (rev 5) + .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, + .dev_type = "L496x/L4A6x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) + .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) + // SRAM1 is 256k at 0x20000000 + // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) + .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) + .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F413/F423 - // RM0430 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F413, - .dev_type = "F413/F423", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 - .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector - // sizes, but 0x4000 is smallest) - .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 - // only says 0x40000) - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + // STLINK_CHIPID_STM32_L45x_L46x + // RM0394 (updated version of RM0392?) + .chip_id = STLINK_CHIPID_STM32_L45x_L46x, + .dev_type = "L45x/46x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 + // and tables 7 on pages 73-74) + // SRAM1 is 128k at 0x20000000; + // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, + // page 68, also fig 2 on page 63) + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system + // memory, also fig 2 on page 63) + .bootrom_size = 0x7000, // 28k (per bank), same source as base .flags = CHIP_F_HAS_SWO_TRACING, }, +// ######################################################################## +// ######################################################################## +// ######################################################################## { - // STM32F09x + // STM32F03x // RM0091 - .chip_id = STLINK_CHIPID_STM32_F09x, - .dev_type = "F09x", + .chip_id = STLINK_CHIPID_STM32_F0xx_SMALL, + .dev_type = "F03x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) - .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) - .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 - .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 + .flash_pagesize = 0x400, // Page sizes listed in Table 4 + .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 + .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, }, @@ -333,19 +223,165 @@ static struct stlink_chipid_params devices[] = { .option_size = 16, }, { - // STM32F03x + // STM32F05x // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0xx_SMALL, - .dev_type = "F03x", + .chip_id = STLINK_CHIPID_STM32_F0, + .dev_type = "F05x", .flash_type = STLINK_FLASH_TYPE_F0, .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 + .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, }, + { + // STM32F07x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F0_CAN, + .dev_type = "F07x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 + .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 + .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 + .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F09x + // RM0091 + .chip_id = STLINK_CHIPID_STM32_F09x, + .dev_type = "F09x", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) + .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) + .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) + .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 + .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + }, + { + // STM32F1xx low- and medium-density value line devices + // RM0041 + .chip_id = STLINK_CHIPID_STM32_F1_VL_MD_LD, + .dev_type = "F1xx Value Line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2000, // 0x1000 for low density devices + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx high-density value line devices + // RM0041 + .chip_id = STLINK_CHIPID_STM32_F1_VL_HD, + .dev_type = "F1xx High-density value line", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x8000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx low-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_LD, + .dev_type = "F1 Low-density device", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2800, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx medium-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_MD, + .dev_type = "F1xx Medium-density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x5000, + .bootrom_base = 0x1ffff000, // 2.3.3 "Embedded Flash memory" + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx high-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_HD, + .dev_type = "F1xx High-density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx XL-density devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_XLD, + .dev_type = "F1xx XL-density", + .flash_type = STLINK_FLASH_TYPE_F1_XL, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x18000, + .bootrom_base = 0x1fffe000, + .bootrom_size = 0x1800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F1xx connectivity devices + // RM0008 + .chip_id = STLINK_CHIPID_STM32_F1_CONN, + .dev_type = "F1xx CL", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1fffb000, + .bootrom_size = 0x4800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx + // RM0033 (rev 5) + .chip_id = STLINK_CHIPID_STM32_F2, + .dev_type = "F2xx", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, { // STM32F301x6/8, STM32F302x6x8, STM32F318x8 // RM0366, RM0365 @@ -362,50 +398,37 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L0xx Category 3 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0, - .dev_type = "L0xx Cat.3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, + // STM32F302xBxC, STM32F303xB/C, STM32F358 + // RM0316, RM0365 + .chip_id = STLINK_CHIPID_STM32_F3, + .dev_type = "F302/F303/F358", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L0x Category 5 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0_CAT5, - .dev_type = "L0xx Cat.5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x5000, - .bootrom_base = 0x1ff0000, + // STM32F302xD/E, STM32F303xD/E, STM32F398xE, + // RM0316 (rev 5), RM0365 + .chip_id = STLINK_CHIPID_STM32_F303_HD, + .dev_type = "F303 high density", + .flash_type = STLINK_FLASH_TYPE_F0, + .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register + .flash_pagesize = 0x800, // 4.2.1 Flash memory organization + .sram_size = 0x10000, // 3.3 Embedded SRAM + .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory .bootrom_size = 0x2000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - .flags = CHIP_F_HAS_DUAL_BANK, - }, - { - // STM32L0x Category 2 - // RM0367, RM0377 - .chip_id = STLINK_CHIPID_STM32_L0_CAT2, - .dev_type = "L0xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, + .option_base = STM32_F0_OPTION_BYTES_BASE, + .option_size = 16, + .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F334, STM32F303x6/8, STM32F328 + // STM32F303x6/8, STM32F328, STM32F334 // RM0364, RM0316 .chip_id = STLINK_CHIPID_STM32_F334, .dev_type = "F303/F328/F334", // (RM0316 sec 33.6.1) @@ -420,149 +443,192 @@ static struct stlink_chipid_params devices[] = { .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32F303xD/E, STM32F398xE, STM32F302xD/E - // RM0316 (rev 5), RM0365 - .chip_id = STLINK_CHIPID_STM32_F303_HD, - .dev_type = "F303 high density", + // STM32F373Cx/Rx/Vx, STM32F378Cx/Rx/Vx + // RM0313 + .chip_id = STLINK_CHIPID_STM32_F37x, + .dev_type = "F37x", .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register - .flash_pagesize = 0x800, // 4.2.1 Flash memory organization - .sram_size = 0x10000, // 3.3 Embedded SRAM - .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory - .bootrom_size = 0x2000, + .flash_size_reg = 0x1ffff7cc, + .flash_pagesize = 0x800, + .sram_size = 0xa000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800, .option_base = STM32_F0_OPTION_BYTES_BASE, .option_size = 16, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L47x/L48x - // RM0351 - .chip_id = STLINK_CHIPID_STM32_L4, - .dev_type = "L47x/L48x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 - // and tables 4-6 on pages 79-81) - // SRAM1 is "up to" 96k in the standard Cortex-M memory map; - // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) + .chip_id = STLINK_CHIPID_STM32_F4_LP, + .dev_type = "F401xB/C", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x10000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + .chip_id = STLINK_CHIPID_STM32_F4_DE, + .dev_type = "F401xD/E", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L4RX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4Rx, - .dev_type = "L4Rx", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + // STM32F410 + // RM0401 + .chip_id = STLINK_CHIPID_STM32_F410, + .dev_type = "F410", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x4000, + .sram_size = 0x8000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L4PX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4PX, - .dev_type = "L4Px", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + .chip_id = STLINK_CHIPID_STM32_F411xx, + .dev_type = "F411xC/E", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L41x_L42x - // RM0394 (rev 4), DS12469 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L41x_L42x, - .dev_type = "L41x/L42x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, - // sec 47.2, page 1586) - .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) - // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 - // (DS12469, sec 3.5, page 18) - .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) - .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000, // 28k, same source as base + // STM32F412 + // RM0402 + .chip_id = STLINK_CHIPID_STM32_F412, + .dev_type = "F412", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) + .flash_pagesize = 0x4000, // Table 5. Flash module organization ? + .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L43x_L44x - // RM0392 - .chip_id = STLINK_CHIPID_STM32_L43x_L44x, - .dev_type = "L43x/L44x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 - // and tables 7-8 on pages 75-76) - // SRAM1 is "up to" 64k in the standard Cortex-M memory map; - // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0xc000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, + // STM32F413/F423 + // RM0430 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F413, + .dev_type = "F413/F423", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 + .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector + // sizes, but 0x4000 is smallest) + .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 + // only says 0x40000) + .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 + .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F42x/F43x + // RM0090 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F4_HD, + .dev_type = "F42x/F43x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F446x family + // RM0390 + .chip_id = STLINK_CHIPID_STM32_F446, + .dev_type = "F446", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1fff7a22, + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = 0x1FFFC000, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L496x_L4A6x - // RM0351 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, - .dev_type = "L496x/L4A6x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) - // SRAM1 is 256k at 0x20000000 - // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) - .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) - .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, + // STM32F46x/F47x + // RM0090 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F4_DSI, + .dev_type = "F46x/F47x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x40000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F4x5/F4x7 + // RM0090 (rev 2) + .chip_id = STLINK_CHIPID_STM32_F4, + .dev_type = "F4x5/F4x7", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1FFF7A22, + .flash_pagesize = 0x4000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800, + .option_base = STM32_F4_OPTION_BYTES_BASE, .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STLINK_CHIPID_STM32_L45x_L46x - // RM0394 (updated version of RM0392?) - .chip_id = STLINK_CHIPID_STM32_L45x_L46x, - .dev_type = "L45x/46x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 - // and tables 7 on pages 73-74) - // SRAM1 is 128k at 0x20000000; - // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, - // page 68, also fig 2 on page 63) - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system - // memory, also fig 2 on page 63) - .bootrom_size = 0x7000, // 28k (per bank), same source as base + // STM32F72x/F73x + // RM0431 + .chip_id = STLINK_CHIPID_STM32_F72xxx, + .dev_type = "F72x/F73x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff07a22, // section 35.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32F74x/F75x + // RM0385, DS10916 + .chip_id = STLINK_CHIPID_STM32_F7, + .dev_type = "F74x/F75x", + .flash_type = STLINK_FLASH_TYPE_F4, + .flash_size_reg = 0x1ff0f442, // section 41.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 + .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 + .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 .flags = CHIP_F_HAS_SWO_TRACING, }, { - // STM32L0xx Category 1 - // RM0451, RM0377 - .chip_id = STLINK_CHIPID_STM32_L011, - .dev_type = "L01x/L02x", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x2000, + // STM32F76x/F77x + // RM0410 + .chip_id = STLINK_CHIPID_STM32_F76xxx, + .dev_type = "F76x/F77x", + .flash_type = STLINK_FLASH_TYPE_F7, + .flash_size_reg = 0x1ff0f442, // section 45.2 + .flash_pagesize = 0x800, // No flash pages + .sram_size = 0x80000, // "SRAM" byte size in hex from + .bootrom_base = 0x00200000, // "System memory" starting address from + .bootrom_size = 0xEDC0, + .option_base = STM32_F7_OPTION_BYTES_BASE, /* Used for reading back the option + bytes, writing uses FLASH_F7_OPTCR + and FLASH_F7_OPTCR1 */ + .option_size = 0x20, + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { // STM32G030/031/041 @@ -579,10 +645,10 @@ static struct stlink_chipid_params devices[] = { .option_size = 4, }, { - // STM32G071/081 + // STM32G051/G061 // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT2, - .dev_type = "G07x/G08x", + .chip_id = STLINK_CHIPID_STM32_G0_CAT4, + .dev_type = "G05x/G06x", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2k (sec 3.2) @@ -593,10 +659,10 @@ static struct stlink_chipid_params devices[] = { .option_size = 4, }, { - // STM32G0B1/G0C1 + // STM32G071/081 // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT3, - .dev_type = "G0Bx/G0Cx", + .chip_id = STLINK_CHIPID_STM32_G0_CAT2, + .dev_type = "G07x/G08x", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2k (sec 3.2) @@ -605,13 +671,12 @@ static struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, - .flags = CHIP_F_HAS_DUAL_BANK, }, { - // STM32G051/G061 + // STM32G0B1/G0C1 // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT4, - .dev_type = "G05x/G06x", + .chip_id = STLINK_CHIPID_STM32_G0_CAT3, + .dev_type = "G0Bx/G0Cx", .flash_type = STLINK_FLASH_TYPE_G0, .flash_size_reg = 0x1FFF75E0, // Section 38.2 .flash_pagesize = 0x800, // 2k (sec 3.2) @@ -620,6 +685,7 @@ static struct stlink_chipid_params devices[] = { .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) .option_base = STM32_G0_OPTION_BYTES_BASE, .option_size = 4, + .flags = CHIP_F_HAS_DUAL_BANK, }, { // STM32G431/441 @@ -675,20 +741,6 @@ static struct stlink_chipid_params devices[] = { .option_size = 4, .flags = CHIP_F_HAS_SWO_TRACING, }, - { - // STM32H742/743/753 (from RM0433) - .chip_id = STLINK_CHIPID_STM32_H74xxx, - .dev_type = "H74x/H75x", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) - .flash_pagesize = 0x20000, // 128k sector (pg147) - .sram_size = 0x20000, // 128k "DTCM" from Table 7 - .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 - .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, { // STM32H7A3/7B3 // RM0455 @@ -720,125 +772,74 @@ static struct stlink_chipid_params devices[] = { .option_size = 44, .flags = CHIP_F_HAS_SWO_TRACING, }, - - - { - // STM32F1xx medium-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_MD, - .dev_type = "F1xx Medium-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x5000, - .bootrom_base = 0x1ffff000, // 2.3.3 "Embedded Flash memory" - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx - // RM0033 (rev 5) - .chip_id = STLINK_CHIPID_STM32_F2, - .dev_type = "F2xx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx low-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_LD, - .dev_type = "F1 Low-density device", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2800, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, { - // STM32F1xx high-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_HD, - .dev_type = "F1xx High-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32H742/743/753 (from RM0433) + .chip_id = STLINK_CHIPID_STM32_H74xxx, + .dev_type = "H74x/H75x", + .flash_type = STLINK_FLASH_TYPE_H7, + .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) + .flash_pagesize = 0x20000, // 128k sector (pg147) + .sram_size = 0x20000, // 128k "DTCM" from Table 7 + .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 + .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 + .option_base = STM32_H7_OPTION_BYTES_BASE, + .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, }, { - // STM32F1xx connectivity devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_CONN, - .dev_type = "F1xx CL", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1fffb000, - .bootrom_size = 0x4800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L0xx Category 1 + // RM0451, RM0377 + .chip_id = STLINK_CHIPID_STM32_L011, + .dev_type = "L01x/L02x", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x2000, }, { - // STM32F1xx low- and medium-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_MD_LD, - .dev_type = "F1xx Value Line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2000, // 0x1000 for low density devices - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L0x Category 2 + // RM0367, RM0377 + .chip_id = STLINK_CHIPID_STM32_L0_CAT2, + .dev_type = "L0xx Cat.2", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000, + .option_base = STM32_L0_OPTION_BYTES_BASE, + .option_size = 20, }, { - // STM32F1xx high-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_HD, - .dev_type = "F1xx High-density value line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x8000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L0xx Category 3 + // RM0367, RM0377, RM0451 + .chip_id = STLINK_CHIPID_STM32_L0, + .dev_type = "L0xx Cat.3", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x2000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x1000, + .option_base = STM32_L0_OPTION_BYTES_BASE, + .option_size = 20, }, { - // STM32F1xx XL-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_XLD, - .dev_type = "F1xx XL-density", - .flash_type = STLINK_FLASH_TYPE_F1_XL, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x18000, - .bootrom_base = 0x1fffe000, - .bootrom_size = 0x1800, - .flags = CHIP_F_HAS_SWO_TRACING, + // STM32L0x Category 5 + // RM0367, RM0377, RM0451 + .chip_id = STLINK_CHIPID_STM32_L0_CAT5, + .dev_type = "L0xx Cat.5", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8007c, + .flash_pagesize = 0x80, + .sram_size = 0x5000, + .bootrom_base = 0x1ff0000, + .bootrom_size = 0x2000, + .option_base = STM32_L0_OPTION_BYTES_BASE, + .option_size = 20, + .flags = CHIP_F_HAS_DUAL_BANK, }, { // STM32WB55xx, STM32WB35xx, STM32WB50CG/30CE From f55dd8d08f5cd414b9569b8d16a0f7841cec6db9 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 6 Jan 2022 21:24:29 +0100 Subject: [PATCH 1268/1435] [refactoring] Clean-up for chipid files (L1, L4) --- config/chips/L1xx_Cat_1.chip | 17 +- config/chips/L1xx_Cat_2.chip | 17 +- config/chips/L1xx_Cat_3.chip | 17 +- config/chips/L1xx_Cat_4.chip | 21 +- config/chips/L1xx_Cat_5.chip | 17 +- config/chips/L41x_L42x.chip | 17 +- config/chips/L43x_L44x.chip | 21 +- config/chips/L45x_46x.chip | 13 -- config/chips/L45x_L46x.chip | 14 ++ config/chips/L47x_L48x.chip | 21 +- config/chips/L496x_L4A6x.chip | 21 +- config/chips/L4Px.chip | 19 +- config/chips/L4Rx.chip | 19 +- src/stlink-lib/chipid_db_old.h | 373 ++++++++++++++++----------------- 14 files changed, 308 insertions(+), 299 deletions(-) delete mode 100644 config/chips/L45x_46x.chip create mode 100644 config/chips/L45x_L46x.chip diff --git a/config/chips/L1xx_Cat_1.chip b/config/chips/L1xx_Cat_1.chip index 6c8b211c4..1d0b9282f 100644 --- a/config/chips/L1xx_Cat_1.chip +++ b/config/chips/L1xx_Cat_1.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L1xx Cat.1 +# Chip-ID file for STM32L1xx (Cat.1) device (L100C6 / L100R8 / L100RB) # -chip_id 0x416 -description L1xx Cat.1 -flash_type 5 -flash_pagesize 0x100 -sram_size 0x4000 +dev_type STM32L1xx_Cat_1 +ref_manual_id 0038 +chip_id 0x416 // STLINK_CHIPID_STM32_L1_MD +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8004c +flash_pagesize 0x100 // 128 B +sram_size 0x4000 // 16 KB bootrom_base 0x1ff00000 -bootrom_size 0x1000 +bootrom_size 0x1000 // 4 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/L1xx_Cat_2.chip b/config/chips/L1xx_Cat_2.chip index 1ff71edef..f311e702c 100644 --- a/config/chips/L1xx_Cat_2.chip +++ b/config/chips/L1xx_Cat_2.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L1xx Cat.2 +# Chip-ID file for STM32L1xx (Cat.2) device (L100C6-A / L100R8-A / L100RB-A) # -chip_id 0x429 -description L1xx Cat.2 -flash_type 5 -flash_pagesize 0x100 -sram_size 0x8000 +dev_type STM32L1xx_Cat_2 +ref_manual_id 0038 +chip_id 0x429 // STLINK_CHIPID_STM32_L1_CAT2 +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff8004c +flash_pagesize 0x100 // 128 B +sram_size 0x8000 // 32 KB bootrom_base 0x1ff00000 -bootrom_size 0x1000 +bootrom_size 0x1000 // 4 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/L1xx_Cat_3.chip b/config/chips/L1xx_Cat_3.chip index f417e07f9..e6ecaf49e 100644 --- a/config/chips/L1xx_Cat_3.chip +++ b/config/chips/L1xx_Cat_3.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L1xx Cat.3 +# Chip-ID file for STM32L1xx (Cat.3) device (L100RC / L15xxC) # -chip_id 0x427 -description L1xx Cat.3 -flash_type 5 -flash_pagesize 0x100 -sram_size 0x8000 +dev_type STM32L1xx_Cat_3 +ref_manual_id 0038 +chip_id 0x427 // STLINK_CHIPID_STM32_L1_MD_PLUS +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff800cc +flash_pagesize 0x100 // 128 B +sram_size 0x8000 // 32 KB bootrom_base 0x1ff00000 -bootrom_size 0x1000 +bootrom_size 0x1000 // 4 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/L1xx_Cat_4.chip b/config/chips/L1xx_Cat_4.chip index dbf7869ad..8ed0e004a 100644 --- a/config/chips/L1xx_Cat_4.chip +++ b/config/chips/L1xx_Cat_4.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L1xx Cat.4 +# Chip-ID file for STM32L1xx (Cat.4) device (L15xxD / L162xD) # -chip_id 0x436 -description L1xx Cat.4 -flash_type 5 -flash_pagesize 0x100 -sram_size 0xc000 +dev_type STM32L1xx_Cat_4 +ref_manual_id 0038 +chip_id 0x436 // STLINK_CHIPID_STM32_L1_MD_PLUS_HD +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff800cc +flash_pagesize 0x100 // 128 B +sram_size 0xc000 // 48 KB bootrom_base 0x1ff00000 -bootrom_size 0x1000 -option_base 0x1ff80000 -option_size 0x8 +bootrom_size 0x1000 // 4 KB +option_base 0x1ff80000 // STM32_L1_OPTION_BYTES_BASE +option_size 0x8 // 8 B flags swo - diff --git a/config/chips/L1xx_Cat_5.chip b/config/chips/L1xx_Cat_5.chip index 12342d14f..75cebd94c 100644 --- a/config/chips/L1xx_Cat_5.chip +++ b/config/chips/L1xx_Cat_5.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L1xx Cat.5 +# Chip-ID file for STM32L1xx (Cat.5) device (L15xxE / L162xE) # -chip_id 0x437 -description L1xx Cat.5 -flash_type 5 -flash_pagesize 0x100 -sram_size 0x14000 +dev_type STM32L1xx_Cat_5 +ref_manual_id 0038 +chip_id 0x437 // STLINK_CHIPID_STM32_L152_RE +flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_size_reg 0x1ff800cc +flash_pagesize 0x100 // 128 B +sram_size 0x14000 // 80 KB bootrom_base 0x1ff00000 -bootrom_size 0x1000 +bootrom_size 0x1000 // 4 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/L41x_L42x.chip b/config/chips/L41x_L42x.chip index 3e086e159..97d0939ab 100644 --- a/config/chips/L41x_L42x.chip +++ b/config/chips/L41x_L42x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L41x/L42x +# Chip-ID file for STM32L41x / STM32L42x device # -chip_id 0x464 -description L41x/L42x -flash_type 6 -flash_pagesize 0x800 -sram_size 0xa000 +dev_type STM32L41x_L42x +ref_manual_id 0394 +chip_id 0x464 // STLINK_CHIPID_STM32_L41x_L42x +flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0xa000 // 40 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 +bootrom_size 0x7000 // 28 KB option_base 0x0 option_size 0x0 flags swo - diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index 383c42f3f..369fdfa1e 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L43x/L44x +# Chip-ID file for STM32L43x / STM32L44x device # -chip_id 0x435 -description L43x/L44x -flash_type 6 -flash_pagesize 0x800 -sram_size 0xc000 +dev_type STM32L41x_L42x +ref_manual_id 0392 +chip_id 0x435 // STLINK_CHIPID_STM32_L43x_L44x +flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0xc000 // 48 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/L45x_46x.chip b/config/chips/L45x_46x.chip deleted file mode 100644 index 943b275d5..000000000 --- a/config/chips/L45x_46x.chip +++ /dev/null @@ -1,13 +0,0 @@ -# Chip-ID file for L45x/46x -# -chip_id 0x462 -description L45x/46x -flash_type 6 -flash_pagesize 0x800 -sram_size 0x20000 -bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x0 -option_size 0x0 -flags swo - diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip new file mode 100644 index 000000000..2d1cda441 --- /dev/null +++ b/config/chips/L45x_L46x.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L45x / STM32L46x device +# +dev_type STM32L45x_L46x +ref_manual_id 0394 +chip_id 0x462 // STLINK_CHIPID_STM32_L45x_L46x +flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x20000 // 128 KB +bootrom_base 0x1fff0000 +bootrom_size 0x7000 // 28 KB +option_base 0x0 +option_size 0x0 +flags swo diff --git a/config/chips/L47x_L48x.chip b/config/chips/L47x_L48x.chip index 7069229f3..4af25cf5c 100644 --- a/config/chips/L47x_L48x.chip +++ b/config/chips/L47x_L48x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L47x/L48x +# Chip-ID file for STM32L47x / STM32L48x device # -chip_id 0x415 -description L47x/L48x -flash_type 6 -flash_pagesize 0x800 -sram_size 0x18000 +dev_type STM32L47x_L48x +ref_manual_id 0351 +chip_id 0x415 // STLINK_CHIPID_STM32_L4 +flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x18000 // 96 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 57f539db3..822914c96 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L496x/L4A6x +# Chip-ID file for STM32L496x / STM32L4A6x device # -chip_id 0x461 -description L496x/L4A6x -flash_type 6 -flash_pagesize 0x800 -sram_size 0x40000 +dev_type STM32L496x_L4A6x +ref_manual_id 0351 +chip_id 0x461 // STLINK_CHIPID_STM32_L496x_L4A6x +flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x800 // 2 KB +sram_size 0x40000 // 256 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 -option_base 0x1fff7800 -option_size 0x4 +bootrom_size 0x7000 // 28 KB +option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo - diff --git a/config/chips/L4Px.chip b/config/chips/L4Px.chip index 3e0fbea50..8366621e2 100644 --- a/config/chips/L4Px.chip +++ b/config/chips/L4Px.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L4Px +# Chip-ID file for STM32L4Px device # -chip_id 0x471 -description L4Px -flash_type 6 -flash_pagesize 0x1000 -sram_size 0xa0000 +dev_type STM32L4Px +ref_manual_id 0432 +chip_id 0x471 // STLINK_CHIPID_STM32_L4PX +flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x1000 // 4 KB +sram_size 0xa0000 // 640 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 +bootrom_size 0x7000 // 28 KB option_base 0x0 option_size 0x0 -flags dualbank swo - +flags swo diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index a9a26f419..734f39199 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -1,13 +1,14 @@ -# Chip-ID file for L4Rx +# Chip-ID file for STM32L4Rx device # -chip_id 0x470 -description L4Rx -flash_type 6 -flash_pagesize 0x1000 -sram_size 0xa0000 +dev_type STM32L4Rx +ref_manual_id 0432 +chip_id 0x470 // STLINK_CHIPID_STM32_L4RX +flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_size_reg 0x1fff75e0 +flash_pagesize 0x1000 // 4 KB +sram_size 0xa0000 // 640 KB bootrom_base 0x1fff0000 -bootrom_size 0x7000 +bootrom_size 0x7000 // 28 KB option_base 0x0 option_size 0x0 -flags dualbank swo - +flags swo diff --git a/src/stlink-lib/chipid_db_old.h b/src/stlink-lib/chipid_db_old.h index b86b13289..7acfef409 100644 --- a/src/stlink-lib/chipid_db_old.h +++ b/src/stlink-lib/chipid_db_old.h @@ -6,194 +6,6 @@ // config/chips/*.chip file. static struct stlink_chipid_params devices[] = { - { - // STM32L100/L15x/L16x Cat.1 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD, - .dev_type = "L1xx Cat.1", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x4000, // up to 16k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.2 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_CAT2, - .dev_type = "L1xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x8000, // up to 32k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.3 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS, - .dev_type = "L1xx Cat.3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x8000, // up to 32k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.4 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS_HD, - .dev_type = "L1xx Cat.4", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0xC000, // up to 48k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .option_base = STM32_L1_OPTION_BYTES_BASE, - .option_size = 8, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.5 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L152_RE, - .dev_type = "L1xx Cat.5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x14000, // up to 80k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L47x/L48x - // RM0351 - .chip_id = STLINK_CHIPID_STM32_L4, - .dev_type = "L47x/L48x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 - // and tables 4-6 on pages 79-81) - // SRAM1 is "up to" 96k in the standard Cortex-M memory map; - // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L4RX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4Rx, - .dev_type = "L4Rx", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L4PX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4PX, - .dev_type = "L4Px", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L41x_L42x - // RM0394 (rev 4), DS12469 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L41x_L42x, - .dev_type = "L41x/L42x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, - // sec 47.2, page 1586) - .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) - // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 - // (DS12469, sec 3.5, page 18) - .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) - .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000, // 28k, same source as base - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L43x_L44x - // RM0392 - .chip_id = STLINK_CHIPID_STM32_L43x_L44x, - .dev_type = "L43x/L44x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 - // and tables 7-8 on pages 75-76) - // SRAM1 is "up to" 64k in the standard Cortex-M memory map; - // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0xc000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L496x_L4A6x - // RM0351 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, - .dev_type = "L496x/L4A6x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) - // SRAM1 is 256k at 0x20000000 - // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) - .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) - .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L45x_L46x - // RM0394 (updated version of RM0392?) - .chip_id = STLINK_CHIPID_STM32_L45x_L46x, - .dev_type = "L45x/46x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 - // and tables 7 on pages 73-74) - // SRAM1 is 128k at 0x20000000; - // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, - // page 68, also fig 2 on page 63) - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system - // memory, also fig 2 on page 63) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .flags = CHIP_F_HAS_SWO_TRACING, - }, -// ######################################################################## -// ######################################################################## -// ######################################################################## { // STM32F03x // RM0091 @@ -841,6 +653,191 @@ static struct stlink_chipid_params devices[] = { .option_size = 20, .flags = CHIP_F_HAS_DUAL_BANK, }, + { + // STM32L100/L15x/L16x Cat.1 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_MD, + .dev_type = "L1xx Cat.1", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x4000, // up to 16k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.2 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_CAT2, + .dev_type = "L1xx Cat.2", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x8000, // up to 32k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.3 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS, + .dev_type = "L1xx Cat.3", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x8000, // up to 32k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.4 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS_HD, + .dev_type = "L1xx Cat.4", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0xC000, // up to 48k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .option_base = STM32_L1_OPTION_BYTES_BASE, + .option_size = 8, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L100/L15x/L16x Cat.5 + // RM0038 + .chip_id = STLINK_CHIPID_STM32_L152_RE, + .dev_type = "L1xx Cat.5", + .flash_type = STLINK_FLASH_TYPE_L0, + .flash_size_reg = 0x1ff800cc, + .flash_pagesize = 0x100, + .sram_size = 0x14000, // up to 80k + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L41x_L42x + // RM0394 (rev 4), DS12469 (rev 5) + .chip_id = STLINK_CHIPID_STM32_L41x_L42x, + .dev_type = "L41x/L42x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, + // sec 47.2, page 1586) + .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) + // SRAM1 is 32k at 0x20000000 + // SRAM2 is 8k at 0x10000000 and 0x20008000 + // (DS12469, sec 3.5, page 18) + .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) + .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) + .bootrom_size = 0x7000, // 28k, same source as base + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L43x_L44x + // RM0392 + .chip_id = STLINK_CHIPID_STM32_L43x_L44x, + .dev_type = "L43x/L44x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 + // and tables 7-8 on pages 75-76) + // SRAM1 is "up to" 64k in the standard Cortex-M memory map; + // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0xc000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L45x_L46x + // RM0394 (updated version of RM0392?) + .chip_id = STLINK_CHIPID_STM32_L45x_L46x, + .dev_type = "L45x/46x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 + // and tables 7 on pages 73-74) + // SRAM1 is 128k at 0x20000000; + // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, + // page 68, also fig 2 on page 63) + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system + // memory, also fig 2 on page 63) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L47x/L48x + // RM0351 + .chip_id = STLINK_CHIPID_STM32_L4, + .dev_type = "L47x/L48x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) + .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 + // and tables 4-6 on pages 79-81) + // SRAM1 is "up to" 96k in the standard Cortex-M memory map; + // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for + // sizes; table 2, page 74 for SRAM2 location) + .sram_size = 0x18000, + .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STLINK_CHIPID_STM32_L496x_L4A6x + // RM0351 (rev 5) + .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, + .dev_type = "L496x/L4A6x", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) + .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) + // SRAM1 is 256k at 0x20000000 + // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) + .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) + .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) + .bootrom_size = 0x7000, // 28k (per bank), same source as base + .option_base = STM32_L4_OPTION_BYTES_BASE, + .option_size = 4, + .flags = CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L4PX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4PX, + .dev_type = "L4Px", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, + { + // STM32L4RX + // RM0432 + .chip_id = STLINK_CHIPID_STM32_L4Rx, + .dev_type = "L4Rx", + .flash_type = STLINK_FLASH_TYPE_L4, + .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) + .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 + // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size + .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 + .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 + .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) + .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, + }, { // STM32WB55xx, STM32WB35xx, STM32WB50CG/30CE // RM0434, RM0471 From 4132973ddfcf48abb3046d0f15c2ec4321a43891 Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Fri, 7 Jan 2022 00:45:25 +0400 Subject: [PATCH 1269/1435] usb.c refactoring request: remove getenv("STLINK_DEVICE") There is no enironment variable "STLINK_DEVICE" in user system, and program do not set it. So I removed all code which works with it. --- src/stlink-lib/usb.c | 36 ++---------------------------------- 1 file changed, 2 insertions(+), 34 deletions(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 65e8f4e25..2e99e82be 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1134,33 +1134,8 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, #endif libusb_device **list = NULL; - // TODO: We should use ssize_t and use it as a counter if > 0. - // As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) - int cnt = (int)libusb_get_device_list(slu->libusb_ctx, &list); + ssize_t cnt = libusb_get_device_list(slu->libusb_ctx, &list); struct libusb_device_descriptor desc; - int devBus = 0; - int devAddr = 0; - - // TODO: Reading a environment variable in a usb open function is not very nice, this should - // be refactored and moved into the CLI tools, and instead of giving USB_BUS:USB_ADDR a real - // stlink serial string should be passed to this function. Probably people are using this - // but this is very odd because as programmer can change to multiple busses and it is better - // to detect them based on serial. - char *device = getenv("STLINK_DEVICE"); - - if (device) { - char *c = strchr(device, ':'); - - if (c == NULL) { - WLOG("STLINK_DEVICE must be : format\n"); - goto on_error; - } - - devBus = atoi(device); - *c++ = 0; - devAddr = atoi(c); - ILOG("bus %03d dev %03d\n", devBus, devAddr); - } while (cnt-- > 0) { struct libusb_device_handle *handle; @@ -1169,13 +1144,6 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, if (desc.idVendor != STLINK_USB_VID_ST) { continue; } - if (devBus && devAddr) { - if ((libusb_get_bus_number(list[cnt]) != devBus) || - (libusb_get_device_address(list[cnt]) != devAddr)) { - continue; - } - } - ret = libusb_open(list[cnt], &handle); if (ret) { continue; } // could not open device @@ -1202,7 +1170,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, } if (cnt < 0) { - WLOG ("Couldn't find %s ST-Link devices\n", (devBus && devAddr) ? "matched" : "any"); + WLOG ("Couldn't find any ST-Link devices\n"); libusb_free_device_list(list, 1); goto on_error; } else { From 42790f3f169e10d51dfe4bb982d64b24389a62ab Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Tue, 21 Dec 2021 09:48:10 +1300 Subject: [PATCH 1270/1435] st-flash erase addr size --- inc/stlink.h | 1 + src/common.c | 24 +++++++++++++++--------- src/st-flash/flash.c | 7 +++++-- src/st-flash/flash_opts.c | 19 ++++++++++++++++++- 4 files changed, 39 insertions(+), 12 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 81dc7902e..852e95e42 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -274,6 +274,7 @@ int stlink_trace_enable(stlink_t* sl, uint32_t frequency); int stlink_trace_disable(stlink_t* sl); int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); int stlink_erase_flash_mass(stlink_t* sl); +int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); uint8_t stlink_get_erased_pattern(stlink_t *sl); diff --git a/src/common.c b/src/common.c index bdd6f5bab..fb5e431fa 100644 --- a/src/common.c +++ b/src/common.c @@ -2951,19 +2951,13 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { return check_flash_error(sl); } -int stlink_erase_flash_mass(stlink_t *sl) { - int err = 0; - - // TODO: User MER bit to mass-erase WB series. - if (sl->flash_type == STLINK_FLASH_TYPE_L0 || - sl->flash_type == STLINK_FLASH_TYPE_WB) { +int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size) { // erase each page - int i = 0, num_pages = (int)(sl->flash_size / sl->flash_pgsz); - + int i = 0, num_pages = (int)(size / sl->flash_pgsz); for (i = 0; i < num_pages; i++) { // addr must be an addr inside the page stm32_addr_t addr = - (stm32_addr_t)sl->flash_base + i * (stm32_addr_t)sl->flash_pgsz; + (stm32_addr_t)base_addr + i * (stm32_addr_t)sl->flash_pgsz; if (stlink_erase_flash_page(sl, addr)) { WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); @@ -2975,6 +2969,18 @@ int stlink_erase_flash_mass(stlink_t *sl) { } fprintf(stdout, "\n"); + return 0; +} + +int stlink_erase_flash_mass(stlink_t *sl) { + int err = 0; + + // TODO: User MER bit to mass-erase WB series. + if (sl->flash_type == STLINK_FLASH_TYPE_L0 || + sl->flash_type == STLINK_FLASH_TYPE_WB) { + + stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size); + } else { wait_flash_busy(sl); clear_flash_error(sl); diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 51702b683..b4b596cfc 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -27,7 +27,7 @@ static void cleanup(int signum) { static void usage(void) { puts("command line: ./st-flash [--debug] [--reset] [--connect-under-reset] [--hot-plug] [--opt] [--serial ] [--format ] [--flash=] [--freq=] [--area=] {read|write} [path] [addr] [size]"); - puts("command line: ./st-flash [--debug] [--connect-under-reset] [--hot-plug] [--freq=] [--serial ] erase"); + puts("command line: ./st-flash [--debug] [--connect-under-reset] [--hot-plug] [--freq=] [--serial ] erase [addr] [size]"); puts("command line: ./st-flash [--debug] [--freq=] [--serial ] reset"); puts(" , and : Use hex format."); puts(" : Use decimal, octal or hex (prefix 0xXXX) format, optionally followed by k=KB, or m=MB (eg. --flash=128k)"); @@ -168,7 +168,10 @@ int main(int ac, char** av) { goto on_error; } } else if (o.cmd == FLASH_CMD_ERASE) { - err = stlink_erase_flash_mass(sl); + if (o.size != 0 && o.addr >= sl->flash_base && (o.addr + o.size) <= (sl->flash_base + sl->flash_size)) + err = stlink_erase_flash_section(sl, o.addr, o.size); + else + err = stlink_erase_flash_mass(sl); if (err == -1) { printf("stlink_erase_flash_mass() == -1\n"); diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 172a24468..984156aa3 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -234,7 +234,24 @@ int flash_get_opts(struct flash_opts* o, int ac, char** av) { return(-1); case FLASH_CMD_ERASE: // no more arguments expected - if (ac != 0) { return(-1); } + if (ac != 0 && ac != 2) { return(-1); } + if (ac == 2) { + uint32_t address; + result = get_integer_from_char_array(av[0], &address); + if (result != 0) { + return bad_arg ("addr"); + } else { + o->addr = (stm32_addr_t) address; + } + + uint32_t size; + result = get_integer_from_char_array(av[1], &size); + if (result != 0) { + return bad_arg ("size"); + } else { + o->size = (size_t) size; + } + } break; From b519c63e500de3d146132ffafb67d058d9ecf974 Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Sun, 9 Jan 2022 19:02:22 +0400 Subject: [PATCH 1271/1435] #1214 issue fix Error in file size comparizon. Due to type casting, instead of compare file size with max. singed int value, it compares with -1. Then function returns with error message. --- src/common.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/common.c b/src/common.c index bdd6f5bab..99fdde325 100644 --- a/src/common.c +++ b/src/common.c @@ -27,6 +27,10 @@ #define O_BINARY 0 #endif +#ifndef MAX_FILE_SIZE +#define MAX_FILE_SIZE (1<<20) // signed long int max value +#endif + #ifdef _MSC_VER #define __attribute__(x) #endif @@ -2200,8 +2204,9 @@ static int map_file(mapped_file_t *mf, const char *path) { if (sizeof(st.st_size) != sizeof(size_t)) { // on 32 bit systems, check if there is an overflow - if (st.st_size > (off_t)SSIZE_MAX) { - fprintf(stderr, "mmap() size_t overflow for file %s\n", path); + if (st.st_size > (off_t)MAX_FILE_SIZE /*1 GB*/ ) { + // limit file size to 1 GB + fprintf(stderr, "mmap() file %s too big\n", path); goto on_error; } } From 14498bb3c011c70d5ba66f26de2a8c11eed68b8d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 9 Jan 2022 16:39:54 +0100 Subject: [PATCH 1272/1435] Restructuring of STM32 definitions - Moved enum stlink_stm32_chipids to stm32.h - Moved additional MCU defines to stlink.h - Minor formatting improvements - Commented comparison for old/new chipid db --- inc/stlink.h | 4 ++ inc/stm32.h | 118 ++++++++++++++++++++++++++++++++-------- src/stlink-lib/chipid.c | 69 +++++++++++------------ src/stlink-lib/chipid.h | 77 ++------------------------ 4 files changed, 139 insertions(+), 129 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 81dc7902e..d7cc0006e 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -83,6 +83,10 @@ enum target_state { #define STLINK_F_HAS_DPBANKSEL (1 << 8) #define STLINK_F_HAS_RW8_512BYTES (1 << 9) +/* Additional MCU features */ +#define CHIP_F_HAS_DUAL_BANK (1 << 0) +#define CHIP_F_HAS_SWO_TRACING (1 << 1) + /* Error code */ #define STLINK_DEBUG_ERR_OK 0x80 #define STLINK_DEBUG_ERR_FAULT 0x81 diff --git a/inc/stm32.h b/inc/stm32.h index 15e0ff147..7a5e983a4 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -7,37 +7,111 @@ #ifndef STM32_H #define STM32_H -/* Cortex core ids */ -#define STM32VL_CORE_ID 0x1ba01477 -#define STM32F7_CORE_ID 0x5ba02477 -#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code -#define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 pg3065) +/* Cortex-M core ids */ +#define STM32VL_CORE_ID 0x1ba01477 +#define STM32F7_CORE_ID 0x5ba02477 +#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code +#define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 p.3065) -/* Constant STM32 memory map figures */ -#define STM32_SRAM_BASE ((uint32_t)0x20000000) -#define STM32_FLASH_BASE ((uint32_t)0x08000000) -#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) +/* Constant STM32 memory address */ +#define STM32_SRAM_BASE ((uint32_t)0x20000000) +#define STM32_FLASH_BASE ((uint32_t)0x08000000) -#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) +#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) +#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) -#define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023C14) -#define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201C) +/* Constant STM32 option bytes base memory address */ +#define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14) -#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) -#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1FF80000) +#define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201c) -#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1FFF0000) +#define STM32_L0_OPTION_BYTES_BASE ((uint32_t)0x1ff80000) +#define STM32_L1_OPTION_BYTES_BASE ((uint32_t)0x1ff80000) -#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) -#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1FFF7800) +#define STM32_F7_OPTION_BYTES_BASE ((uint32_t)0x1fff0000) -#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1FFFC000) +#define STM32_G0_OPTION_BYTES_BASE ((uint32_t)0x1fff7800) +#define STM32_L4_OPTION_BYTES_BASE ((uint32_t)0x1fff7800) -#define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) -#define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) -#define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) -#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) +#define STM32_F2_OPTION_BYTES_BASE ((uint32_t)0x1fffc000) + +#define STM32_F0_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) +#define STM32_F1_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) +#define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) +#define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) + + +/* + * Chip IDs + * See DBGMCU_IDCODE register (0xE0042000) in appropriate programming manual + */ + +// stm32 chipids, only lower 12 bits... + +enum stlink_stm32_chipids { + STLINK_CHIPID_UNKNOWN = 0x000, + + STLINK_CHIPID_STM32_F1_MD = 0x410, /* medium density */ + STLINK_CHIPID_STM32_F2 = 0x411, + STLINK_CHIPID_STM32_F1_LD = 0x412, /* low density */ + STLINK_CHIPID_STM32_F4 = 0x413, + STLINK_CHIPID_STM32_F1_HD = 0x414, /* high density */ + STLINK_CHIPID_STM32_L4 = 0x415, + STLINK_CHIPID_STM32_L1_MD = 0x416, /* medium density */ + STLINK_CHIPID_STM32_L0 = 0x417, + STLINK_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */ + STLINK_CHIPID_STM32_F4_HD = 0x419, /* high density */ + STLINK_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */ + STLINK_CHIPID_STM32_F446 = 0x421, + STLINK_CHIPID_STM32_F3 = 0x422, + STLINK_CHIPID_STM32_F4_LP = 0x423, + STLINK_CHIPID_STM32_L0_CAT2 = 0x425, + STLINK_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */ + STLINK_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */ + STLINK_CHIPID_STM32_L1_CAT2 = 0x429, + STLINK_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */ + STLINK_CHIPID_STM32_F411xx = 0x431, + STLINK_CHIPID_STM32_F37x = 0x432, + STLINK_CHIPID_STM32_F4_DE = 0x433, + STLINK_CHIPID_STM32_F4_DSI = 0x434, + STLINK_CHIPID_STM32_L43x_L44x = 0x435, + STLINK_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ + STLINK_CHIPID_STM32_L152_RE = 0x437, + STLINK_CHIPID_STM32_F334 = 0x438, + STLINK_CHIPID_STM32_F3xx_SMALL = 0x439, + STLINK_CHIPID_STM32_F0 = 0x440, + STLINK_CHIPID_STM32_F412 = 0x441, + STLINK_CHIPID_STM32_F09x = 0x442, + STLINK_CHIPID_STM32_F0xx_SMALL = 0x444, + STLINK_CHIPID_STM32_F04 = 0x445, + STLINK_CHIPID_STM32_F303_HD = 0x446, /* high density */ + STLINK_CHIPID_STM32_L0_CAT5 = 0x447, + STLINK_CHIPID_STM32_F0_CAN = 0x448, + STLINK_CHIPID_STM32_F7 = 0x449, /* Nucleo F746ZG board */ + STLINK_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */ + STLINK_CHIPID_STM32_F76xxx = 0x451, + STLINK_CHIPID_STM32_F72xxx = 0x452, /* Nucleo F722ZE board */ + STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */ + STLINK_CHIPID_STM32_L011 = 0x457, + STLINK_CHIPID_STM32_F410 = 0x458, + STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */ + STLINK_CHIPID_STM32_L496x_L4A6x = 0x461, + STLINK_CHIPID_STM32_L45x_L46x = 0x462, + STLINK_CHIPID_STM32_F413 = 0x463, + STLINK_CHIPID_STM32_L41x_L42x = 0x464, + STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */ + STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */ + STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ + STLINK_CHIPID_STM32_G4_CAT3 = 0x469, + STLINK_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ + STLINK_CHIPID_STM32_L4PX = 0x471, /* RM0432, p.2247 */ + STLINK_CHIPID_STM32_G4_CAT4 = 0x479, + STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ + STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ + STLINK_CHIPID_STM32_WB55 = 0x495, + STLINK_CHIPID_STM32_WLE = 0x497, +}; #endif // STM32_H diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 213d43f8c..e3556ca57 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -39,45 +39,46 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "flags %d\n\n", dev->flags); } -static int chipid_params_eq(const struct stlink_chipid_params *p1, const struct stlink_chipid_params *p2) -{ - return p1->chip_id == p2->chip_id && - p1->dev_type && p2->dev_type && - strcmp(p1->dev_type, p2->dev_type) == 0 && - p1->flash_type == p2->flash_type && - p1->flash_size_reg == p2->flash_size_reg && - p1->flash_pagesize == p2->flash_pagesize && - p1->sram_size == p2->sram_size && - p1->bootrom_base == p2->bootrom_base && - p1->bootrom_size == p2->bootrom_size && - p1->option_base == p2->option_base && - p1->option_size == p2->option_size && - p1->flags == p2->flags; -} - -struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid) { +// static int chipid_params_eq(const struct stlink_chipid_params *p1, const struct stlink_chipid_params *p2) +// { +// return p1->chip_id == p2->chip_id && +// p1->dev_type && p2->dev_type && +// strcmp(p1->dev_type, p2->dev_type) == 0 && +// p1->flash_type == p2->flash_type && +// p1->flash_size_reg == p2->flash_size_reg && +// p1->flash_pagesize == p2->flash_pagesize && +// p1->sram_size == p2->sram_size && +// p1->bootrom_base == p2->bootrom_base && +// p1->bootrom_size == p2->bootrom_size && +// p1->option_base == p2->option_base && +// p1->option_size == p2->option_size && +// p1->flags == p2->flags; +// } + +struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { struct stlink_chipid_params *params = NULL; - struct stlink_chipid_params *p2; - +// struct stlink_chipid_params *p2; for (params = devicelist; params != NULL; params = params->next) - if (params->chip_id == chipid) { + if (params->chip_id == chip_id) { + fprintf(stderr, "\ndetected chip_id parametres\n\n"); + dump_a_chip(stderr, params); break; } - p2 = stlink_chipid_get_params_old(chipid); - -#if 1 - if (params == NULL) { - params = p2; - } else if (!chipid_params_eq(params, p2)) { - // fprintf (stderr, "Error, chipid params not identical\n"); - // return NULL; - fprintf(stderr, "---------- old ------------\n"); - dump_a_chip(stderr, p2); - fprintf(stderr, "---------- new ------------\n"); - dump_a_chip(stderr, params); - } -#endif +// p2 = stlink_chipid_get_params_old(chipid); + +// #if 1 +// if (params == NULL) { +// params = p2; +// } else if (!chipid_params_eq(params, p2)) { +// // fprintf (stderr, "Error, chipid params not identical\n"); +// // return NULL; +// fprintf(stderr, "---------- old ------------\n"); +// dump_a_chip(stderr, p2); +// fprintf(stderr, "---------- new ------------\n"); +// dump_a_chip(stderr, params); +// } +// #endif return(params); } diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 426c22428..e821f0b57 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -1,83 +1,14 @@ #ifndef STLINK_CHIPID_H_ #define STLINK_CHIPID_H_ +#include +#include + #ifdef __cplusplus extern "C" { #endif -/** - * Chip IDs are explained in the appropriate programming manual for the - * DBGMCU_IDCODE register (0xE0042000) - * stm32 chipids, only lower 12 bits... - */ -enum stlink_stm32_chipids { - STLINK_CHIPID_UNKNOWN = 0x000, - - STLINK_CHIPID_STM32_F1_MD = 0x410, /* medium density */ - STLINK_CHIPID_STM32_F2 = 0x411, - STLINK_CHIPID_STM32_F1_LD = 0x412, /* low density */ - STLINK_CHIPID_STM32_F4 = 0x413, - STLINK_CHIPID_STM32_F1_HD = 0x414, /* high density */ - STLINK_CHIPID_STM32_L4 = 0x415, - STLINK_CHIPID_STM32_L1_MD = 0x416, /* medium density */ - STLINK_CHIPID_STM32_L0 = 0x417, - STLINK_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */ - STLINK_CHIPID_STM32_F4_HD = 0x419, /* high density */ - STLINK_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */ - STLINK_CHIPID_STM32_F446 = 0x421, - STLINK_CHIPID_STM32_F3 = 0x422, - STLINK_CHIPID_STM32_F4_LP = 0x423, - STLINK_CHIPID_STM32_L0_CAT2 = 0x425, - STLINK_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */ - STLINK_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */ - STLINK_CHIPID_STM32_L1_CAT2 = 0x429, - STLINK_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */ - STLINK_CHIPID_STM32_F411xx = 0x431, - STLINK_CHIPID_STM32_F37x = 0x432, - STLINK_CHIPID_STM32_F4_DE = 0x433, - STLINK_CHIPID_STM32_F4_DSI = 0x434, - STLINK_CHIPID_STM32_L43x_L44x = 0x435, - STLINK_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ - STLINK_CHIPID_STM32_L152_RE = 0x437, - STLINK_CHIPID_STM32_F334 = 0x438, - STLINK_CHIPID_STM32_F3xx_SMALL = 0x439, - STLINK_CHIPID_STM32_F0 = 0x440, - STLINK_CHIPID_STM32_F412 = 0x441, - STLINK_CHIPID_STM32_F09x = 0x442, - STLINK_CHIPID_STM32_F0xx_SMALL = 0x444, - STLINK_CHIPID_STM32_F04 = 0x445, - STLINK_CHIPID_STM32_F303_HD = 0x446, /* high density */ - STLINK_CHIPID_STM32_L0_CAT5 = 0x447, - STLINK_CHIPID_STM32_F0_CAN = 0x448, - STLINK_CHIPID_STM32_F7 = 0x449, /* ID found on the Nucleo F746ZG board */ - STLINK_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */ - STLINK_CHIPID_STM32_F76xxx = 0x451, - STLINK_CHIPID_STM32_F72xxx = 0x452, /* ID found on the Nucleo F722ZE board */ - STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */ - STLINK_CHIPID_STM32_L011 = 0x457, - STLINK_CHIPID_STM32_F410 = 0x458, - STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */ - STLINK_CHIPID_STM32_L496x_L4A6x = 0x461, - STLINK_CHIPID_STM32_L45x_L46x = 0x462, - STLINK_CHIPID_STM32_F413 = 0x463, - STLINK_CHIPID_STM32_L41x_L42x = 0x464, - STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */ - STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */ - STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, s46.6.1 "MCU device ID code" */ - STLINK_CHIPID_STM32_G4_CAT3 = 0x469, - STLINK_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p. 2247, found on the STM32L4R9I-DISCO board */ - STLINK_CHIPID_STM32_L4PX = 0x471, /* RM0432, p. 2247 */ - STLINK_CHIPID_STM32_G4_CAT4 = 0x479, - STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ - STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ - STLINK_CHIPID_STM32_WB55 = 0x495, - STLINK_CHIPID_STM32_WLE = 0x497 -}; - -#define CHIP_F_HAS_DUAL_BANK (1 << 0) -#define CHIP_F_HAS_SWO_TRACING (1 << 1) - -/** Chipid parameters */ +/** Chipid parametres */ struct stlink_chipid_params { char *dev_type; char *ref_manual_id; From 5cde863c0382d92ca0d6ea027a7a3b24926a44e0 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 9 Jan 2022 21:52:55 +0100 Subject: [PATCH 1273/1435] Switch-over to new chip-files --- inc/stlink.h | 26 +++++----- src/stlink-lib/chipid.c | 86 +++++++++++++++++----------------- src/stlink-lib/chipid_db_old.h | 4 +- 3 files changed, 59 insertions(+), 57 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index d7cc0006e..0c1ca73a4 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -106,19 +106,21 @@ enum target_state { #define C_BUF_LEN 32 +/* Old flash type definitions */ +// TODO: Transition to the new defines in stm32.h enum stlink_flash_type { - STLINK_FLASH_TYPE_UNKNOWN = 0, - STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */ - STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank, apparently */ - STLINK_FLASH_TYPE_F4, // used by f2, f4 */ - STLINK_FLASH_TYPE_F7, - STLINK_FLASH_TYPE_L0, // l0, l1 */ - STLINK_FLASH_TYPE_L4, // l4, l4+ */ - STLINK_FLASH_TYPE_G0, - STLINK_FLASH_TYPE_G4, - STLINK_FLASH_TYPE_WB, - STLINK_FLASH_TYPE_H7, - STLINK_FLASH_TYPE_MAX, + /* 0 */ STLINK_FLASH_TYPE_UNKNOWN = 0, + /* 1 */ STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */ + /* 2 */ STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank */ + /* 3 */ STLINK_FLASH_TYPE_F4, // used by f2, f4 */ + /* 4 */ STLINK_FLASH_TYPE_F7, + /* 5 */ STLINK_FLASH_TYPE_L0, // l0, l1 */ + /* 6 */ STLINK_FLASH_TYPE_L4, // l4, l4+ */ + /* 7 */ STLINK_FLASH_TYPE_G0, + /* 8 */ STLINK_FLASH_TYPE_G4, + /* 9 */ STLINK_FLASH_TYPE_WB, + /* 10 */ STLINK_FLASH_TYPE_H7, + /* 11 */ STLINK_FLASH_TYPE_MAX, }; struct stlink_reg { diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index e3556ca57..4ab83ba3d 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,6 +1,6 @@ #include #include "chipid.h" -#include "chipid_db_old.h" +//#include "chipid_db_old.h" #include #include @@ -9,17 +9,17 @@ #include -struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { - struct stlink_chipid_params *params = NULL; +// struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { +// struct stlink_chipid_params *params = NULL; - for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) - if (devices[n].chip_id == chipid) { - params = &devices[n]; - break; - } +// for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) +// if (devices[n].chip_id == chipid) { +// params = &devices[n]; +// break; +// } - return (params); -} +// return (params); +// } static struct stlink_chipid_params *devicelist; @@ -165,7 +165,7 @@ void process_chipfile(char *fname) { while ((pp = strtok (NULL, " \t\n"))) { if (strcmp (pp, "none") == 0) { - ts->flags = 0; // not necessary: calloc did this already. + // NOP } else if (strcmp (pp, "dualbank") == 0) { ts->flags |= CHIP_F_HAS_DUAL_BANK; } else if (strcmp (pp, "swo") == 0) { @@ -187,37 +187,37 @@ void process_chipfile(char *fname) { devicelist = ts; } -void dump_chips (void) { - struct stlink_chipid_params *ts; - char *p, buf[100]; - FILE *fp; - - for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { - ts = &devices[n]; - - strcpy(buf, ts->dev_type); - - while ((p = strchr(buf, '/'))) // change slashes to underscore. - *p = '_'; - - strcat(buf, ".chip"); - fp = fopen(buf, "w"); - fprintf(fp, "# Device Type: %s\n", ts->dev_type); - fprintf(fp, "# Reference Manual: RM%s\n", ts->ref_manual_id); - fprintf(fp, "#\n"); - fprintf(fp, "chip_id %x\n", ts->chip_id); - fprintf(fp, "flash_type %x\n", ts->flash_type); - fprintf(fp, "flash_size_reg %x\n", ts->flash_size_reg); - fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); - fprintf(fp, "sram_size %x\n", ts->sram_size); - fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); - fprintf(fp, "bootrom_size %x\n", ts->bootrom_size); - fprintf(fp, "option_base %x\n", ts->option_base); - fprintf(fp, "option_size %x\n", ts->option_size); - fprintf(fp, "flags %x\n\n", ts->flags); - fclose(fp); - } -} +// void dump_chips (void) { +// struct stlink_chipid_params *ts; +// char *p, buf[100]; +// FILE *fp; + +// for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { +// ts = &devices[n]; + +// strcpy(buf, ts->dev_type); + +// while ((p = strchr(buf, '/'))) // change slashes to underscore. +// *p = '_'; + +// strcat(buf, ".chip"); +// fp = fopen(buf, "w"); +// fprintf(fp, "# Device Type: %s\n", ts->dev_type); +// fprintf(fp, "# Reference Manual: RM%s\n", ts->ref_manual_id); +// fprintf(fp, "#\n"); +// fprintf(fp, "chip_id %x\n", ts->chip_id); +// fprintf(fp, "flash_type %x\n", ts->flash_type); +// fprintf(fp, "flash_size_reg %x\n", ts->flash_size_reg); +// fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); +// fprintf(fp, "sram_size %x\n", ts->sram_size); +// fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); +// fprintf(fp, "bootrom_size %x\n", ts->bootrom_size); +// fprintf(fp, "option_base %x\n", ts->option_base); +// fprintf(fp, "option_size %x\n", ts->option_size); +// fprintf(fp, "flags %x\n\n", ts->flags); +// fclose(fp); +// } +// } #if defined(STLINK_HAVE_DIRENT_H) #include @@ -248,7 +248,7 @@ void init_chipids(char *dir_to_scan) { closedir(d); } else { perror (dir_to_scan); - return; // XXX + return; } } #endif //STLINK_HAVE_DIRENT_H diff --git a/src/stlink-lib/chipid_db_old.h b/src/stlink-lib/chipid_db_old.h index 7acfef409..6578e35be 100644 --- a/src/stlink-lib/chipid_db_old.h +++ b/src/stlink-lib/chipid_db_old.h @@ -5,7 +5,7 @@ // change it both here and in the corresponding // config/chips/*.chip file. -static struct stlink_chipid_params devices[] = { +//static struct stlink_chipid_params devices[] = { { // STM32F03x // RM0091 @@ -874,4 +874,4 @@ static struct stlink_chipid_params devices[] = { .bootrom_base = 0x0, .bootrom_size = 0x0, }, -}; \ No newline at end of file +//}; \ No newline at end of file From 9b07c1dc191181b2d4311b2767a5731db1526f0c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 9 Jan 2022 22:55:56 +0100 Subject: [PATCH 1274/1435] Transition to new enum stm32_flash_type --- config/chips/F03x.chip | 2 +- config/chips/F04x.chip | 2 +- config/chips/F05x.chip | 2 +- config/chips/F07x.chip | 2 +- config/chips/F09x.chip | 2 +- config/chips/F1xx_CL.chip | 2 +- config/chips/F1xx_HD.chip | 2 +- config/chips/F1xx_LD.chip | 2 +- config/chips/F1xx_MD.chip | 2 +- config/chips/F1xx_VL_HD.chip | 2 +- config/chips/F1xx_VL_MD_LD.chip | 2 +- config/chips/F1xx_XLD.chip | 2 +- config/chips/F2xx.chip | 2 +- config/chips/F301_F302_F318.chip | 2 +- config/chips/F302_F303_F358.chip | 2 +- config/chips/F302_F303_F398_HD.chip | 2 +- config/chips/F303_F328_F334.chip | 2 +- config/chips/F37x.chip | 2 +- config/chips/F401xB_xC.chip | 2 +- config/chips/F401xD_xE.chip | 2 +- config/chips/F410.chip | 2 +- config/chips/F411xC_xE.chip | 2 +- config/chips/F412.chip | 2 +- config/chips/F413_F423.chip | 2 +- config/chips/F42x_F43x.chip | 2 +- config/chips/F446.chip | 2 +- config/chips/F46x_F47x.chip | 2 +- config/chips/F4x5_F4x7.chip | 2 +- config/chips/F72x_F73x.chip | 2 +- config/chips/F74x_F75x.chip | 2 +- config/chips/F76x_F77x.chip | 2 +- config/chips/G03x_G04x.chip | 2 +- config/chips/G05x_G06x.chip | 2 +- config/chips/G07x_G08x.chip | 2 +- config/chips/G0Bx_G0Cx.chip | 2 +- config/chips/G43x_G44x.chip | 2 +- config/chips/G47x_G48x.chip | 2 +- config/chips/G49x_G4Ax.chip | 2 +- config/chips/H72x_H73x.chip | 2 +- config/chips/H74x_H75x.chip | 2 +- config/chips/H7Ax_H7Bx.chip | 2 +- config/chips/L0xxx_Cat_1.chip | 2 +- config/chips/L0xxx_Cat_2.chip | 2 +- config/chips/L0xxx_Cat_3.chip | 2 +- config/chips/L0xxx_Cat_5.chip | 2 +- config/chips/L1xx_Cat_1.chip | 2 +- config/chips/L1xx_Cat_2.chip | 2 +- config/chips/L1xx_Cat_3.chip | 2 +- config/chips/L1xx_Cat_4.chip | 2 +- config/chips/L1xx_Cat_5.chip | 2 +- config/chips/L41x_L42x.chip | 2 +- config/chips/L43x_L44x.chip | 2 +- config/chips/L45x_L46x.chip | 2 +- config/chips/L47x_L48x.chip | 2 +- config/chips/L496x_L4A6x.chip | 2 +- config/chips/L4Px.chip | 2 +- config/chips/L4Rx.chip | 2 +- config/chips/L5x5.chip | 2 +- config/chips/U5x5.chip | 2 +- config/chips/WBx0_WBx5.chip | 2 +- config/chips/WLx5.chip | 2 +- config/chips/unknown_device.chip | 2 +- inc/stlink.h | 5 +- inc/stm32.h | 18 + src/common.c | 505 ++++++++++++++-------------- src/st-flash/flash.c | 3 +- src/stlink-lib/chipid.c | 2 +- src/stlink-lib/chipid.h | 2 +- src/stlink-lib/flash_loader.c | 5 +- 69 files changed, 343 insertions(+), 321 deletions(-) diff --git a/config/chips/F03x.chip b/config/chips/F03x.chip index ea7fdb9e2..d19e6a657 100644 --- a/config/chips/F03x.chip +++ b/config/chips/F03x.chip @@ -3,7 +3,7 @@ dev_type STM32F03x ref_manual_id 0091 chip_id 0x444 // STLINK_CHIPID_STM32_F0xx_SMALL -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB sram_size 0x1000 // 4 KB diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 3e702585b..7012d6d7e 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -3,7 +3,7 @@ dev_type STM32F04x ref_manual_id 0091 chip_id 0x445 // STLINK_CHIPID_STM32_F04 -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB sram_size 0x1800 // 6 KB diff --git a/config/chips/F05x.chip b/config/chips/F05x.chip index 1a4f61386..e987cf725 100644 --- a/config/chips/F05x.chip +++ b/config/chips/F05x.chip @@ -3,7 +3,7 @@ dev_type STM32F05x ref_manual_id 0091 chip_id 0x440 // STLINK_CHIPID_STM32_F0 -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB sram_size 0x2000 // 8 KB diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index 2a577b7b4..0f7513e1b 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -3,7 +3,7 @@ dev_type STM32F07x ref_manual_id 0091 chip_id 0x448 // STLINK_CHIPID_STM32_F0_CAN -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x4000 // 16 KB diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index 9f419893e..3d3cc8c89 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -3,7 +3,7 @@ dev_type STM32F09x ref_manual_id 0091 chip_id 0x442 // STLINK_CHIPID_STM32_F09x -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index 4c8bb0b8d..eb417132a 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_CL ref_manual_id 0008 chip_id 0x418 // STLINK_CHIPID_STM32_F1_CONN -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F1xx_HD.chip b/config/chips/F1xx_HD.chip index 18757029a..5def8ebb9 100644 --- a/config/chips/F1xx_HD.chip +++ b/config/chips/F1xx_HD.chip @@ -3,7 +3,7 @@ dev_type F1xx_HD ref_manual_id 0008 chip_id 0x414 // STLINK_CHIPID_STM32_F1_HD -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F1xx_LD.chip b/config/chips/F1xx_LD.chip index 8a8f5867d..33efe063a 100644 --- a/config/chips/F1xx_LD.chip +++ b/config/chips/F1xx_LD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_LD ref_manual_id 0008 chip_id 0x412 // STLINK_CHIPID_STM32_F1_LD -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB sram_size 0x2800 // 10 KB diff --git a/config/chips/F1xx_MD.chip b/config/chips/F1xx_MD.chip index be492f54a..5b250d9cd 100644 --- a/config/chips/F1xx_MD.chip +++ b/config/chips/F1xx_MD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_MD ref_manual_id 0008 chip_id 0x410 // STLINK_CHIPID_STM32_F1_MD -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB sram_size 0x5000 // 20 KB diff --git a/config/chips/F1xx_VL_HD.chip b/config/chips/F1xx_VL_HD.chip index f5ca6b023..1ceade91a 100644 --- a/config/chips/F1xx_VL_HD.chip +++ b/config/chips/F1xx_VL_HD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_VL_HD ref_manual_id 0041 chip_id 0x428 // STLINK_CHIPID_STM32_F1_VL_HD -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/F1xx_VL_MD_LD.chip b/config/chips/F1xx_VL_MD_LD.chip index e79668c70..3f577f74e 100644 --- a/config/chips/F1xx_VL_MD_LD.chip +++ b/config/chips/F1xx_VL_MD_LD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_VL_MD_LD ref_manual_id 0041 chip_id 0x420 // STLINK_CHIPID_STM32_F1_VL_MD_LD -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB sram_size 0x2000 // 8 KB /* 0x1000 for low density devices */ diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip index d7d8cf2b7..964105747 100644 --- a/config/chips/F1xx_XLD.chip +++ b/config/chips/F1xx_XLD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_XLD ref_manual_id 0008 chip_id 0x430 // STLINK_CHIPID_STM32_F1_XLD -flash_type 2 // STLINK_FLASH_TYPE_F1_XL +flash_type 2 // STM32_FLASH_TYPE_F1_XL flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x18000 // 96 KB diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip index 67c225af5..4cb99b2fc 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2xx.chip @@ -3,7 +3,7 @@ dev_type STM32F2xx ref_manual_id 0033 chip_id 0x411 // STLINK_CHIPID_STM32_F2 -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/F301_F302_F318.chip b/config/chips/F301_F302_F318.chip index ee71dfe90..b35de12bf 100644 --- a/config/chips/F301_F302_F318.chip +++ b/config/chips/F301_F302_F318.chip @@ -3,7 +3,7 @@ dev_type STM32F301_F302_F318 ref_manual_id 0365 // also RM0366 chip_id 0x439 // STLINK_CHIPID_STM32_F3xx_SMALL -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/F302_F303_F358.chip b/config/chips/F302_F303_F358.chip index 64d0651f2..6226ca8e8 100644 --- a/config/chips/F302_F303_F358.chip +++ b/config/chips/F302_F303_F358.chip @@ -3,7 +3,7 @@ dev_type STM32F302_F303_358 ref_manual_id 0365 // also RM0316 chip_id 0x422 // STLINK_CHIPID_STM32_F3 -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/F302_F303_F398_HD.chip b/config/chips/F302_F303_F398_HD.chip index eaf36b74c..b4ad3aed8 100644 --- a/config/chips/F302_F303_F398_HD.chip +++ b/config/chips/F302_F303_F398_HD.chip @@ -3,7 +3,7 @@ dev_type STM32F302_F303_F398_HD ref_manual_id 0365 // also RM0316 (Rev 5) chip_id 0x446 // STLINK_CHIPID_STM32_F303_HD -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F303_F328_F334.chip b/config/chips/F303_F328_F334.chip index 2ecdbfb71..010c3b622 100644 --- a/config/chips/F303_F328_F334.chip +++ b/config/chips/F303_F328_F334.chip @@ -3,7 +3,7 @@ dev_type STM32F303_F328_F334 ref_manual_id 0364 // also RM0316 chip_id 0x438 // STLINK_CHIPID_STM32_F334 -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x3000 // 12 KB diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index 1bd7ac421..9ca9d72f8 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -3,7 +3,7 @@ dev_type STM32F37x ref_manual_id 0313 chip_id 0x432 // STLINK_CHIPID_STM32_F37x -flash_type 1 // STLINK_FLASH_TYPE_F0 +flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/F401xB_xC.chip b/config/chips/F401xB_xC.chip index fc93c2f1a..e1f37d94b 100644 --- a/config/chips/F401xB_xC.chip +++ b/config/chips/F401xB_xC.chip @@ -3,7 +3,7 @@ dev_type STM32F401xB_xC ref_manual_id 0368 chip_id 0x423 // STLINK_CHIPID_STM32_F4_LP -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip index e31d5eace..f03661495 100644 --- a/config/chips/F401xD_xE.chip +++ b/config/chips/F401xD_xE.chip @@ -3,7 +3,7 @@ dev_type STM32F401xD_xE ref_manual_id 0368 chip_id 0x433 // STLINK_CHIPID_STM32_F4_DE -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x18000 // 96 KB diff --git a/config/chips/F410.chip b/config/chips/F410.chip index a8a7fbad0..6f7727921 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -3,7 +3,7 @@ dev_type STM32F410 ref_manual_id 0401 chip_id 0x458 // STLINK_CHIPID_STM32_F410 -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/F411xC_xE.chip b/config/chips/F411xC_xE.chip index cf2cbd2c1..5d624b7d9 100644 --- a/config/chips/F411xC_xE.chip +++ b/config/chips/F411xC_xE.chip @@ -3,7 +3,7 @@ dev_type STM32F411xC_xE ref_manual_id 0383 chip_id 0x431 // STLINK_CHIPID_STM32_F411xx -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/F412.chip b/config/chips/F412.chip index 4c866a3c5..bd18ec2ea 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -3,7 +3,7 @@ dev_type STM32F412 ref_manual_id 0402 chip_id 0x441 // STLINK_CHIPID_STM32_F412 -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F413_F423.chip b/config/chips/F413_F423.chip index 81ca585f6..c7e036a2d 100644 --- a/config/chips/F413_F423.chip +++ b/config/chips/F413_F423.chip @@ -3,7 +3,7 @@ dev_type STM32F413_F423 ref_manual_id 0430 // RM0430 (Rev 2) chip_id 0x463 // STLINK_CHIPID_STM32_F413 -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x50000 // 320 KB diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 2ec8fb8e8..cbb77e152 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -3,7 +3,7 @@ dev_type STM32F42x_F43x ref_manual_id 0090 // RM0090 (Rev. 2) chip_id 0x463 // STLINK_CHIPID_STM32_F4_HD -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 8cebe358e..2ac868ddd 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -3,7 +3,7 @@ dev_type STM32F446 ref_manual_id 0390 chip_id 0x421 // STLINK_CHIPID_STM32_F446 -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index 2e4055f2c..e8d66cbd7 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -3,7 +3,7 @@ dev_type STM32F46x_F47x ref_manual_id 0090 // RM0090 (Rev. 2) chip_id 0x434 // STLINK_CHIPID_STM32_F4_DSI -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F4x5_F4x7.chip b/config/chips/F4x5_F4x7.chip index 9313c8ae1..d75f74103 100644 --- a/config/chips/F4x5_F4x7.chip +++ b/config/chips/F4x5_F4x7.chip @@ -3,7 +3,7 @@ dev_type STM32F4x5_F4x7 ref_manual_id 0090 // RM0090 (Rev. 2) chip_id 0x413 // STLINK_CHIPID_STM32_F4 -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x30000 // 192 KB diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index 37dcd1234..c0f2df155 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -3,7 +3,7 @@ dev_type STM32F72x_F73x ref_manual_id 0431 chip_id 0x452 // STLINK_CHIPID_STM32_F72xxx -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff07a22 flash_pagesize 0x800 // 2 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F74x_F75x.chip b/config/chips/F74x_F75x.chip index 96cc95217..fa0b6ddc2 100644 --- a/config/chips/F74x_F75x.chip +++ b/config/chips/F74x_F75x.chip @@ -3,7 +3,7 @@ dev_type STM32F74x_F75x ref_manual_id 0385 chip_id 0x449 // STLINK_CHIPID_STM32_F7 -flash_type 3 // STLINK_FLASH_TYPE_F4 +flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB sram_size 0x50000 // 320 KB diff --git a/config/chips/F76x_F77x.chip b/config/chips/F76x_F77x.chip index a93aba2be..c1a5a9cf2 100644 --- a/config/chips/F76x_F77x.chip +++ b/config/chips/F76x_F77x.chip @@ -3,7 +3,7 @@ dev_type STM32F76x_F77x ref_manual_id 0410 chip_id 0x451 // STLINK_CHIPID_STM32_F76xxx -flash_type 4 // STLINK_FLASH_TYPE_F7 +flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB sram_size 0x80000 // 512 KB diff --git a/config/chips/G03x_G04x.chip b/config/chips/G03x_G04x.chip index a21a9898f..aee016e0d 100644 --- a/config/chips/G03x_G04x.chip +++ b/config/chips/G03x_G04x.chip @@ -3,7 +3,7 @@ dev_type STM32G03x_G04x ref_manual_id 0444 // also RM454 chip_id 0x466 // STLINK_CHIPID_STM32_G0_CAT1 -flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x2000 // 8 KB diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index 89af0825c..f92cad889 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -3,7 +3,7 @@ dev_type STM32G05x_G06x ref_manual_id 0444 chip_id 0x456 // STLINK_CHIPID_STM32_G0_CAT4 -flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x9000 // 36 KB diff --git a/config/chips/G07x_G08x.chip b/config/chips/G07x_G08x.chip index c54de398f..29f527e73 100644 --- a/config/chips/G07x_G08x.chip +++ b/config/chips/G07x_G08x.chip @@ -3,7 +3,7 @@ dev_type STM32G07x_G08x ref_manual_id 0444 chip_id 0x460 // STLINK_CHIPID_STM32_G0_CAT2 -flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x9000 // 36 KB diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index d8e0eb042..67254fbbd 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -3,7 +3,7 @@ dev_type STM32G0Bx_G0Cx ref_manual_id 0444 chip_id 0x467 // STLINK_CHIPID_STM32_G0_CAT3 -flash_type 7 // STLINK_FLASH_TYPE_G0 +flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x9000 // 36 KB diff --git a/config/chips/G43x_G44x.chip b/config/chips/G43x_G44x.chip index 455d65b8c..b33a1a0f8 100644 --- a/config/chips/G43x_G44x.chip +++ b/config/chips/G43x_G44x.chip @@ -3,7 +3,7 @@ dev_type STM32G43x_G44x ref_manual_id 0440 chip_id 0x468 // STLINK_CHIPID_STM32_G4_CAT2 -flash_type 8 // STLINK_FLASH_TYPE_G4 +flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/G47x_G48x.chip b/config/chips/G47x_G48x.chip index 250905c68..abf6a6f2d 100644 --- a/config/chips/G47x_G48x.chip +++ b/config/chips/G47x_G48x.chip @@ -3,7 +3,7 @@ dev_type STM32G47x_G48x ref_manual_id 0440 chip_id 0x469 // STLINK_CHIPID_STM32_G4_CAT3 -flash_type 8 // STLINK_FLASH_TYPE_G4 +flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip index 9702541a8..3d8110f19 100644 --- a/config/chips/G49x_G4Ax.chip +++ b/config/chips/G49x_G4Ax.chip @@ -3,7 +3,7 @@ dev_type STM32G49x_G4Ax ref_manual_id 0440 chip_id 0x479 // STLINK_CHIPID_STM32_G4_CAT4 -flash_type 8 // STLINK_FLASH_TYPE_G4 +flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x1c000 // 112 KB diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index 183c7d197..1417cdb27 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -3,7 +3,7 @@ dev_type STM32H72x_H73x ref_manual_id 0468 chip_id 0x483 // STLINK_CHIPID_STM32_H72x -flash_type 10 // STLINK_FLASH_TYPE_H7 +flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB "DTCM" diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 2e543b197..53a3e921a 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -3,7 +3,7 @@ dev_type STM32H74x_H75x ref_manual_id 0433 chip_id 0x450 // STLINK_CHIPID_STM32_H74xxx -flash_type 10 // STLINK_FLASH_TYPE_H7 +flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB "DTCM" diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index b5fe72119..516c4260e 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -3,7 +3,7 @@ dev_type STM32H7Ax_H7Bx ref_manual_id 0455 chip_id 0x480 // STLINK_CHIPID_STM32_H7Ax -flash_type 10 // STLINK_FLASH_TYPE_H7 +flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x08fff80c flash_pagesize 0x2000 // 8 KB sram_size 0x20000 // 128 KB "DTCM" diff --git a/config/chips/L0xxx_Cat_1.chip b/config/chips/L0xxx_Cat_1.chip index 1dd8a1acb..6dc227024 100644 --- a/config/chips/L0xxx_Cat_1.chip +++ b/config/chips/L0xxx_Cat_1.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_1 ref_manual_id 0451 // also RM0377 chip_id 0x457 // STLINK_CHIPID_STM32_L011 -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_2.chip b/config/chips/L0xxx_Cat_2.chip index 58d6439ba..74a3d6157 100644 --- a/config/chips/L0xxx_Cat_2.chip +++ b/config/chips/L0xxx_Cat_2.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_2 ref_manual_id 0451 // also RM0377 chip_id 0x425 // STLINK_CHIPID_STM32_L0_CAT2 -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_3.chip b/config/chips/L0xxx_Cat_3.chip index 406c1a037..0cfcc53bb 100644 --- a/config/chips/L0xxx_Cat_3.chip +++ b/config/chips/L0xxx_Cat_3.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_3 ref_manual_id 0451 // also RM0367 & RM0377 chip_id 0x417 // STLINK_CHIPID_STM32_L0 -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_5.chip b/config/chips/L0xxx_Cat_5.chip index 1a0c387a7..cbb1e6632 100644 --- a/config/chips/L0xxx_Cat_5.chip +++ b/config/chips/L0xxx_Cat_5.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_5 ref_manual_id 0451 // also RM0367 & RM0377 chip_id 0x447 // STLINK_CHIPID_STM32_L0_CAT5 -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x5000 // 20 KB diff --git a/config/chips/L1xx_Cat_1.chip b/config/chips/L1xx_Cat_1.chip index 1d0b9282f..cecc32996 100644 --- a/config/chips/L1xx_Cat_1.chip +++ b/config/chips/L1xx_Cat_1.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_1 ref_manual_id 0038 chip_id 0x416 // STLINK_CHIPID_STM32_L1_MD -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B sram_size 0x4000 // 16 KB diff --git a/config/chips/L1xx_Cat_2.chip b/config/chips/L1xx_Cat_2.chip index f311e702c..1981d58a5 100644 --- a/config/chips/L1xx_Cat_2.chip +++ b/config/chips/L1xx_Cat_2.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_2 ref_manual_id 0038 chip_id 0x429 // STLINK_CHIPID_STM32_L1_CAT2 -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B sram_size 0x8000 // 32 KB diff --git a/config/chips/L1xx_Cat_3.chip b/config/chips/L1xx_Cat_3.chip index e6ecaf49e..1d551c8a4 100644 --- a/config/chips/L1xx_Cat_3.chip +++ b/config/chips/L1xx_Cat_3.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_3 ref_manual_id 0038 chip_id 0x427 // STLINK_CHIPID_STM32_L1_MD_PLUS -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B sram_size 0x8000 // 32 KB diff --git a/config/chips/L1xx_Cat_4.chip b/config/chips/L1xx_Cat_4.chip index 8ed0e004a..1e9cfe91c 100644 --- a/config/chips/L1xx_Cat_4.chip +++ b/config/chips/L1xx_Cat_4.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_4 ref_manual_id 0038 chip_id 0x436 // STLINK_CHIPID_STM32_L1_MD_PLUS_HD -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B sram_size 0xc000 // 48 KB diff --git a/config/chips/L1xx_Cat_5.chip b/config/chips/L1xx_Cat_5.chip index 75cebd94c..a51356d7a 100644 --- a/config/chips/L1xx_Cat_5.chip +++ b/config/chips/L1xx_Cat_5.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_5 ref_manual_id 0038 chip_id 0x437 // STLINK_CHIPID_STM32_L152_RE -flash_type 5 // STLINK_FLASH_TYPE_L0 +flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B sram_size 0x14000 // 80 KB diff --git a/config/chips/L41x_L42x.chip b/config/chips/L41x_L42x.chip index 97d0939ab..2de859b0c 100644 --- a/config/chips/L41x_L42x.chip +++ b/config/chips/L41x_L42x.chip @@ -3,7 +3,7 @@ dev_type STM32L41x_L42x ref_manual_id 0394 chip_id 0x464 // STLINK_CHIPID_STM32_L41x_L42x -flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index 369fdfa1e..2dad90844 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -3,7 +3,7 @@ dev_type STM32L41x_L42x ref_manual_id 0392 chip_id 0x435 // STLINK_CHIPID_STM32_L43x_L44x -flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0xc000 // 48 KB diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index 2d1cda441..f856e1315 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -3,7 +3,7 @@ dev_type STM32L45x_L46x ref_manual_id 0394 chip_id 0x462 // STLINK_CHIPID_STM32_L45x_L46x -flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/L47x_L48x.chip b/config/chips/L47x_L48x.chip index 4af25cf5c..51257a37c 100644 --- a/config/chips/L47x_L48x.chip +++ b/config/chips/L47x_L48x.chip @@ -3,7 +3,7 @@ dev_type STM32L47x_L48x ref_manual_id 0351 chip_id 0x415 // STLINK_CHIPID_STM32_L4 -flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x18000 // 96 KB diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 822914c96..32d75b571 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -3,7 +3,7 @@ dev_type STM32L496x_L4A6x ref_manual_id 0351 chip_id 0x461 // STLINK_CHIPID_STM32_L496x_L4A6x -flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/L4Px.chip b/config/chips/L4Px.chip index 8366621e2..ff3f05b81 100644 --- a/config/chips/L4Px.chip +++ b/config/chips/L4Px.chip @@ -3,7 +3,7 @@ dev_type STM32L4Px ref_manual_id 0432 chip_id 0x471 // STLINK_CHIPID_STM32_L4PX -flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0xa0000 // 640 KB diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index 734f39199..535e282c9 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -3,7 +3,7 @@ dev_type STM32L4Rx ref_manual_id 0432 chip_id 0x470 // STLINK_CHIPID_STM32_L4RX -flash_type 6 // STLINK_FLASH_TYPE_L4 +flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0xa0000 // 640 KB diff --git a/config/chips/L5x5.chip b/config/chips/L5x5.chip index ce268148b..9a5b2fdbf 100644 --- a/config/chips/L5x5.chip +++ b/config/chips/L5x5.chip @@ -3,7 +3,7 @@ dev_type STM32L5x2 ref_manual_id 0438 chip_id 0x0 // (temporary setting only!) -flash_type 0 // (temporary setting only!) +flash_type 10 // (temporary setting only!) flash_size_reg 0x0bfa07a0 flash_pagesize 0x2000 // 8 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/U5x5.chip b/config/chips/U5x5.chip index 177359cc3..55dfdaf7d 100644 --- a/config/chips/U5x5.chip +++ b/config/chips/U5x5.chip @@ -3,7 +3,7 @@ dev_type STM32U5x5 ref_manual_id 0456 chip_id 0x0 // (temporary setting only!) -flash_type 0 // (temporary setting only!) +flash_type 10 // (temporary setting only!) flash_size_reg 0x0bfa07a0 flash_pagesize 0x2000 // 8 KB sram_size 0xc4800 // 786 KB diff --git a/config/chips/WBx0_WBx5.chip b/config/chips/WBx0_WBx5.chip index ba5fee778..5fa76ec75 100644 --- a/config/chips/WBx0_WBx5.chip +++ b/config/chips/WBx0_WBx5.chip @@ -3,7 +3,7 @@ dev_type STM32WBx0_WBx5 ref_manual_id 0434 // also RM0471 chip_id 0x495 // STLINK_CHIPID_STM32_WB55 -flash_type 9 // STLINK_FLASH_TYPE_WB +flash_type 11 // STM32_FLASH_TYPE_WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/WLx5.chip b/config/chips/WLx5.chip index 2dc9ce648..62ff4f72f 100644 --- a/config/chips/WLx5.chip +++ b/config/chips/WLx5.chip @@ -3,7 +3,7 @@ dev_type STM32WLEx ref_manual_id 0033 chip_id 0x497 // STLINK_CHIPID_STM32_WLE -flash_type 9 // STLINK_FLASH_TYPE_WB +flash_type 11 // STM32_FLASH_TYPE_WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index 1b74f22fa..512211092 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -3,7 +3,7 @@ dev_type unknown ref_manual_id 0000 chip_id 0x0 // STLINK_CHIPID_UNKNOWN -flash_type 0 // STLINK_FLASH_TYPE_UNKNOWN +flash_type 0 // STM32_FLASH_TYPE_UNKNOWN flash_size_reg 0x0 flash_pagesize 0x0 sram_size 0x0 diff --git a/inc/stlink.h b/inc/stlink.h index 0c1ca73a4..b387881ae 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -200,6 +200,7 @@ enum run_type { typedef struct _stlink stlink_t; +#include #include struct _stlink { @@ -222,8 +223,8 @@ struct _stlink { char serial[STLINK_SERIAL_BUFFER_SIZE]; int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR - enum stlink_flash_type flash_type; - // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STLINK_FLASH_TYPE_xxx + enum stm32_flash_type flash_type; + // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STM32_FLASH_TYPE_xx stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() size_t flash_size; // calculated by stlink_load_device_params() diff --git a/inc/stm32.h b/inc/stm32.h index 7a5e983a4..280a61107 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -13,6 +13,24 @@ #define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code #define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 p.3065) +/* STM32 flash types */ +// New flash type definitions must go before STM32_FLASH_TYPE_UNDEFINED +// with the latter updated to the highest enum value. +enum stm32_flash_type { + STM32_FLASH_TYPE_UNKNOWN = 0, + STM32_FLASH_TYPE_F0_F1_F3 = 1, + STM32_FLASH_TYPE_F1_XL = 2, + STM32_FLASH_TYPE_F2_F4 = 3, + STM32_FLASH_TYPE_F7 = 4, + STM32_FLASH_TYPE_G0 = 5, // 7 + STM32_FLASH_TYPE_G4 = 6, // 8 + STM32_FLASH_TYPE_H7 = 7, // 10 + STM32_FLASH_TYPE_L0_L1 = 8, // 5 + STM32_FLASH_TYPE_L4_L4P = 9, // 6 + STM32_FLASH_TYPE_L5_U5 = 10, // new + STM32_FLASH_TYPE_WB_WL = 11, // 9 + STM32_FLASH_TYPE_UNDEFINED = 12, // max. value exceeded +}; /* Constant STM32 memory address */ #define STM32_SRAM_BASE ((uint32_t)0x20000000) diff --git a/src/common.c b/src/common.c index 48ff6120b..e73955f31 100644 --- a/src/common.c +++ b/src/common.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #ifdef STLINK_HAVE_SYS_MMAN_H @@ -467,18 +468,18 @@ static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { static inline uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { uint32_t reg, res; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; } else { reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; @@ -498,30 +499,30 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { uint32_t cr_reg; uint32_t n; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; cr_lock_shift = FLASH_H7_CR_LOCK; } else { @@ -542,27 +543,27 @@ static void unlock_flash(stlink_t *sl) { * definitive lock of the FPEC block until next reset. */ - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { key_reg = FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { key_reg = FLASH_KEYR; key2_reg = FLASH_KEYR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { key_reg = FLASH_F4_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { key_reg = FLASH_F7_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; flash_key1 = FLASH_L0_PEKEY1; flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { key_reg = STM32L4_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { key_reg = STM32Gx_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { key_reg = STM32WB_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { key_reg = FLASH_H7_KEYR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { key2_reg = FLASH_H7_KEYR2; @@ -600,33 +601,33 @@ static void lock_flash(stlink_t *sl) { uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; uint32_t cr_mask = 0xffffffffu; - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { cr_reg = FLASH_CR; cr2_reg = FLASH_CR2; cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr2_reg = FLASH_H7_CR2; @@ -655,38 +656,38 @@ static bool is_flash_option_locked(stlink_t *sl) { uint32_t n; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; optlock_shift = FLASH_CR_OPTWRE; active_bit_level = 0; /* bit is "option write enable", not lock */ break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: optcr_reg = FLASH_F4_OPTCR; optlock_shift = FLASH_F4_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: optcr_reg = STM32Gx_FLASH_CR; optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; optlock_shift = FLASH_H7_OPTCR_OPTLOCK; break; @@ -709,38 +710,38 @@ static int lock_flash_option(stlink_t *sl) { int active_bit_level = 1; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; optlock_shift = FLASH_CR_OPTWRE; active_bit_level = 0; break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: optcr_reg = FLASH_F4_OPTCR; optlock_shift = FLASH_F4_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: optcr_reg = STM32Gx_FLASH_CR; optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; optlock_shift = FLASH_H7_OPTCR_OPTLOCK; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) @@ -782,34 +783,34 @@ static int unlock_flash_option(stlink_t *sl) { uint32_t optkey2 = FLASH_OPTKEY2; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: optkey_reg = FLASH_OPTKEYR; optkey1 = FLASH_F0_OPTKEY1; optkey2 = FLASH_F0_OPTKEY2; break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: optkey_reg = FLASH_F4_OPT_KEYR; break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: optkey_reg = FLASH_F7_OPT_KEYR; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; optkey1 = FLASH_L0_OPTKEY1; optkey2 = FLASH_L0_OPTKEY2; break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: optkey_reg = STM32L4_FLASH_OPTKEYR; break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: optkey_reg = STM32Gx_FLASH_OPTKEYR; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: optkey_reg = STM32WB_FLASH_OPT_KEYR; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: optkey_reg = FLASH_H7_OPT_KEYR; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) optkey2_reg = FLASH_H7_OPT_KEYR2; @@ -852,24 +853,24 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; x |= (1 << FLASH_H7_CR_PG); } else { @@ -884,18 +885,18 @@ static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { uint32_t cr_reg, n; uint32_t bit = FLASH_CR_PG; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; bit = FLASH_H7_CR_PG; } else { @@ -909,10 +910,10 @@ static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { static void set_flash_cr_per(stlink_t *sl, unsigned bank) { uint32_t cr_reg, val; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; @@ -926,10 +927,10 @@ static void set_flash_cr_per(stlink_t *sl, unsigned bank) { static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { uint32_t cr_reg; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; @@ -942,20 +943,20 @@ static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { uint32_t val, cr_reg, cr_mer, cr_pg; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); cr_pg = (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); @@ -964,11 +965,11 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { } cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_mer = (1 << FLASH_H7_CR_BER); cr_pg = (1 << FLASH_H7_CR_PG); @@ -998,23 +999,23 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { uint32_t val, cr_reg, cr_strt; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_strt = (1 << STM32L4_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_strt = (1 << STM32Gx_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_strt = (1 << STM32WB_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); } else { @@ -1030,23 +1031,23 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { uint32_t res, sr_reg; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; } else { ELOG("method 'read_flash_sr' is unsupported\n"); @@ -1060,23 +1061,23 @@ static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { uint32_t sr_reg; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; } else { ELOG("method 'write_flash_sr' is unsupported\n"); @@ -1090,22 +1091,22 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; unsigned int res; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_L0)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { sr_busy_shift = FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_busy_shift = FLASH_F4_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { sr_busy_shift = STM32L4_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { sr_busy_shift = STM32Gx_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_busy_shift = STM32WB_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; } else { ELOG("method 'is_flash_busy' is unsupported\n"); @@ -1114,8 +1115,8 @@ static inline unsigned int is_flash_busy(stlink_t *sl) { res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); } @@ -1149,32 +1150,32 @@ static void wait_flash_busy_progress(stlink_t *sl) { static void clear_flash_error(stlink_t *sl) { switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: + case STM32_FLASH_TYPE_F0_F1_F3: write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); } break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); break; default: @@ -1189,52 +1190,52 @@ static int check_flash_error(stlink_t *sl) { WRPERR = PROGERR = PGAERR = 0; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; } WRPERR = (1 << FLASH_SR_WRPRT_ERR); PROGERR = (1 << FLASH_SR_PG_ERR); break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; WRPERR = (1 << FLASH_F4_SR_WRPERR); PGAERR = (1 << FLASH_F4_SR_PGAERR); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; WRPERR = (1 << FLASH_F7_SR_WRP_ERR); PROGERR = (1 << FLASH_F7_SR_PGP_ERR); break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; } WRPERR = (1 << FLASH_H7_SR_WRPERR); break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); @@ -1271,31 +1272,31 @@ static void stop_wdg_in_debug(stlink_t *sl) { uint32_t value; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_G4: dbgmcu_cr = STM32F0_DBGMCU_CR; set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | (1 << STM32F0_DBGMCU_CR_WWDG_STOP); break; - case STLINK_FLASH_TYPE_F4: - case STLINK_FLASH_TYPE_F7: - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_F2_F4: + case STM32_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_L4_L4P: dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); break; - case STLINK_FLASH_TYPE_L0: - case STLINK_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_L0_L1: + case STM32_FLASH_TYPE_G0: dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP); break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1; set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) | (1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP); @@ -1315,34 +1316,34 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { rcc = rcc_dma_mask = value = 0; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: rcc = STM32F1_RCC_AHBENR; rcc_dma_mask = STM32F1_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_F4: - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F2_F4: + case STM32_FLASH_TYPE_F7: rcc = STM32F4_RCC_AHB1ENR; rcc_dma_mask = STM32F4_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G0: rcc = STM32G0_RCC_AHBENR; rcc_dma_mask = STM32G0_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_G4: - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_L4_L4P: rcc = STM32G4_RCC_AHB1ENR; rcc_dma_mask = STM32G4_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: rcc = STM32L0_RCC_AHBENR; rcc_dma_mask = STM32L0_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: rcc = STM32H7_RCC_AHB1ENR; rcc_dma_mask = STM32H7_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: rcc = STM32WB_RCC_AHB1ENR; rcc_dma_mask = STM32WB_RCC_DMAEN; break; @@ -1370,7 +1371,7 @@ static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n, uint32_t cr_reg, psize_shift; uint32_t x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; psize_shift = FLASH_H7_CR_PSIZE; } else { @@ -1390,7 +1391,7 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { uint32_t cr_reg, snb_mask, snb_shift, ser_shift; uint32_t x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; snb_mask = FLASH_H7_CR_SNB_MASK; snb_shift = FLASH_H7_CR_SNB; @@ -1443,7 +1444,7 @@ void stlink_close(stlink_t *sl) { int stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); - if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN && + if (sl->flash_type != STM32_FLASH_TYPE_UNKNOWN && sl->core_stat != TARGET_RESET) { // stop debugging if the target has been identified stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); @@ -1604,7 +1605,7 @@ int stlink_load_device_params(stlink_t *sl) { return (-1); } - if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { + if (params->flash_type == STM32_FLASH_TYPE_UNKNOWN) { WLOG("Invalid flash type, please check device declaration\n"); sl->flash_size = 0; return (0); @@ -1666,7 +1667,7 @@ int stlink_load_device_params(stlink_t *sl) { // H7 devices with small flash has one bank if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && - sl->flash_type == STLINK_FLASH_TYPE_H7) { + sl->flash_type == STM32_FLASH_TYPE_H7) { if ((sl->flash_size / sl->flash_pgsz) <= 1) sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; } @@ -2777,9 +2778,9 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // clear flash IO errors clear_flash_error(sl); - if (sl->flash_type == STLINK_FLASH_TYPE_F4 || - sl->flash_type == STLINK_FLASH_TYPE_F7 || - sl->flash_type == STLINK_FLASH_TYPE_L4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4 || + sl->flash_type == STM32_FLASH_TYPE_F7 || + sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { // unlock if locked unlock_flash_if(sl); @@ -2826,7 +2827,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); #endif - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); @@ -2882,15 +2883,15 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { uint32_t val; unlock_flash_if(sl); set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit // set the page to erase - if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); @@ -2900,7 +2901,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val |= ((flash_page & 0xFF) << 3); stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -2908,7 +2909,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val &= ~(0x3F << 3); val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G4) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -2922,8 +2923,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { wait_flash_busy(sl); // wait for the 'busy' bit to clear clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); clear_flash_cr_pg(sl, bank); // clear the pg bit @@ -2934,7 +2935,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { wait_flash_busy(sl); clear_flash_cr_per(sl, bank); // clear the page erase bit lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); // unlock if locked uint32_t sector = calculate_H7_sectornum( @@ -2955,8 +2956,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { int err = 0; // TODO: User MER bit to mass-erase WB series. - if (sl->flash_type == STLINK_FLASH_TYPE_L0 || - sl->flash_type == STLINK_FLASH_TYPE_WB) { + if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || + sl->flash_type == STM32_FLASH_TYPE_WB_WL) { // erase each page int i = 0, num_pages = (int)(sl->flash_size / sl->flash_pgsz); @@ -2980,7 +2981,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { clear_flash_error(sl); unlock_flash_if(sl); - if (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); @@ -2993,8 +2994,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { set_flash_cr_strt( sl, BANK_1); // start erase operation, reset by hw with busy bit - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 @@ -3005,8 +3006,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { // reset the mass erase bit set_flash_cr_mer(sl, 0, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 0, BANK_2); } @@ -3143,9 +3144,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // Clear errors clear_flash_error(sl); - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { ILOG("Starting Flash write for F2/F4/F7/L4\n"); // Flash loader initialisation @@ -3169,7 +3170,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { return (-1); } - if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { // L4 does not have a byte-write mode if (voltage < 1710) { ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); @@ -3189,14 +3190,14 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // set programming mode set_flash_cr_pg(sl, BANK_1); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { ILOG("Starting Flash write for WB/G0/G4\n"); unlock_flash_if(sl); // unlock flash if necessary set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { ILOG("Starting Flash write for L0\n"); uint32_t val; @@ -3233,8 +3234,8 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // L0/L1 have fallback to soft write WLOG("stlink_flash_loader_init() == -1\n"); } - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); // flash loader initialisation @@ -3248,10 +3249,10 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // set programming mode set_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { set_flash_cr_pg(sl, BANK_2); } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { ILOG("Starting Flash write for H7\n"); unlock_flash_if(sl); // unlock the cr @@ -3277,9 +3278,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { size_t off; - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; for (off = 0; off < len;) { size_t size = len - off > buf_size ? buf_size : len - off; @@ -3293,9 +3294,9 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, off += size; } - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; @@ -3319,7 +3320,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, 0); // write a single word of zeros wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? @@ -3359,8 +3360,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, // TODO: check redo write operation } fprintf(stdout, "\n"); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { int write_block_count = 0; for (off = 0; off < len; off += sl->flash_pgsz) { // adjust last write size @@ -3392,7 +3393,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if (sl->verbose >= 1) { fprintf(stdout, "\n"); } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { for (off = 0; off < len;) { // Program STM32H7x with 64-byte Flash words size_t chunk = (len - off > 64) ? 64 : len - off; @@ -3422,24 +3423,24 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { uint32_t dhcsr; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4) || - (sl->flash_type == STLINK_FLASH_TYPE_WB) || - (sl->flash_type == STLINK_FLASH_TYPE_G0) || - (sl->flash_type == STLINK_FLASH_TYPE_G4) || - (sl->flash_type == STLINK_FLASH_TYPE_H7)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) || + (sl->flash_type == STM32_FLASH_TYPE_WB_WL) || + (sl->flash_type == STM32_FLASH_TYPE_G0) || + (sl->flash_type == STM32_FLASH_TYPE_G4) || + (sl->flash_type == STM32_FLASH_TYPE_H7)) { clear_flash_cr_pg(sl, BANK_1); - if ((sl->flash_type == STLINK_FLASH_TYPE_H7 && + if ((sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { clear_flash_cr_pg(sl, BANK_2); } lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); @@ -3716,7 +3717,7 @@ int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, } uint8_t stlink_get_erased_pattern(stlink_t *sl) { - if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { return (0x00); } else { return (0xff); @@ -4387,7 +4388,7 @@ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: return stlink_read_option_bytes_boot_add_f7(sl, option_byte); default: return -1; @@ -4408,10 +4409,10 @@ int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: return stlink_read_option_control_register_f0(sl, option_byte); - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: return stlink_read_option_control_register_f7(sl, option_byte); default: return -1; @@ -4432,7 +4433,7 @@ int stlink_read_option_control_register1_32(stlink_t *sl, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: return stlink_read_option_control_register1_f7(sl, option_byte); default: return -1; @@ -4494,27 +4495,27 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_bytes_f0(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: ret = stlink_write_option_bytes_f4(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_bytes_f7(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: ret = stlink_write_option_bytes_l0(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: ret = stlink_write_option_bytes_l4(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: ret = stlink_write_option_bytes_gx(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: ret = stlink_write_option_bytes_h7(sl, base, addr, len); break; default: @@ -4732,7 +4733,7 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); break; default: @@ -4777,11 +4778,11 @@ int stlink_write_option_control_register32(stlink_t *sl, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_control_register_f0(sl, option_control_register); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_control_register_f7(sl, option_control_register); break; default: @@ -4826,7 +4827,7 @@ int stlink_write_option_control_register1_32( } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_control_register1_f7(sl, option_control_register1); break; diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 51702b683..dfc972c4e 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -8,6 +8,7 @@ #include #include +#include #include #include "flash.h" @@ -67,7 +68,7 @@ int main(int ac, char** av) { if (sl == NULL) { return(-1); } - if (sl->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { + if (sl->flash_type == STM32_FLASH_TYPE_UNKNOWN) { printf("Failed to connect to target\n"); goto on_error; } diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 4ab83ba3d..78233ec1c 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -129,7 +129,7 @@ void process_chipfile(char *fname) { } else if (strcmp (word, "flash_type") == 0) { if (sscanf(value, "%i", (int *)&ts->flash_type) < 1) { fprintf(stderr, "Failed to parse flash type\n"); - } else if ((ts->flash_type < STLINK_FLASH_TYPE_UNKNOWN) || (ts->flash_type >= STLINK_FLASH_TYPE_MAX)) { + } else if ((ts->flash_type < STM32_FLASH_TYPE_UNKNOWN) || (ts->flash_type >= STM32_FLASH_TYPE_UNDEFINED)) { fprintf(stderr, "Unrecognized flash type\n"); } } else if (strcmp (word, "flash_size_reg") == 0) { diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index e821f0b57..86cd49ddb 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -13,7 +13,7 @@ struct stlink_chipid_params { char *dev_type; char *ref_manual_id; uint32_t chip_id; - enum stlink_flash_type flash_type; + enum stm32_flash_type flash_type; uint32_t flash_size_reg; uint32_t flash_pagesize; uint32_t sram_size; diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 7076a2cfa..6b318dc46 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include "flash_loader.h" @@ -176,7 +177,7 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { ILOG("Successfully loaded flash loader in sram\n"); // set address of IWDG key register for reset it - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + if (sl->flash_type == STM32_FLASH_TYPE_H7) { fl->iwdg_kr = STM32H7_WDG_KR; } else { fl->iwdg_kr = STM32F0_WDG_KR; @@ -333,7 +334,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe return(-1); } - if ((sl->flash_type == STLINK_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { flash_base = FLASH_REGS_BANK2_OFS; } From 115f7c846adf612c1ee818713530dbf17287ed9b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 9 Jan 2022 23:53:30 +0100 Subject: [PATCH 1275/1435] Transition to new enum stm32_chipids --- config/chips/F03x.chip | 2 +- config/chips/F04x.chip | 2 +- config/chips/F05x.chip | 2 +- config/chips/F07x.chip | 2 +- config/chips/F09x.chip | 2 +- config/chips/F1xx_CL.chip | 2 +- config/chips/F1xx_HD.chip | 2 +- config/chips/F1xx_LD.chip | 2 +- config/chips/F1xx_MD.chip | 2 +- config/chips/F1xx_VL_HD.chip | 2 +- config/chips/F1xx_VL_MD_LD.chip | 2 +- config/chips/F1xx_XLD.chip | 2 +- config/chips/F2xx.chip | 2 +- config/chips/F301_F302_F318.chip | 2 +- config/chips/F302_F303_F358.chip | 2 +- config/chips/F302_F303_F398_HD.chip | 2 +- config/chips/F303_F328_F334.chip | 2 +- config/chips/F37x.chip | 2 +- config/chips/F401xB_xC.chip | 2 +- config/chips/F401xD_xE.chip | 2 +- config/chips/F410.chip | 2 +- config/chips/F411xC_xE.chip | 2 +- config/chips/F412.chip | 2 +- config/chips/F413_F423.chip | 2 +- config/chips/F42x_F43x.chip | 2 +- config/chips/F446.chip | 2 +- config/chips/F46x_F47x.chip | 2 +- config/chips/F4x5_F4x7.chip | 2 +- config/chips/F72x_F73x.chip | 2 +- config/chips/F74x_F75x.chip | 2 +- config/chips/F76x_F77x.chip | 2 +- config/chips/G03x_G04x.chip | 2 +- config/chips/G05x_G06x.chip | 2 +- config/chips/G07x_G08x.chip | 2 +- config/chips/G0Bx_G0Cx.chip | 2 +- config/chips/G43x_G44x.chip | 2 +- config/chips/G47x_G48x.chip | 2 +- config/chips/G49x_G4Ax.chip | 2 +- config/chips/H72x_H73x.chip | 2 +- config/chips/H74x_H75x.chip | 2 +- config/chips/H7Ax_H7Bx.chip | 2 +- config/chips/L0xxx_Cat_1.chip | 2 +- config/chips/L0xxx_Cat_2.chip | 2 +- config/chips/L0xxx_Cat_3.chip | 2 +- config/chips/L0xxx_Cat_5.chip | 2 +- config/chips/L1xx_Cat_1.chip | 2 +- config/chips/L1xx_Cat_2.chip | 2 +- config/chips/L1xx_Cat_3.chip | 2 +- config/chips/L1xx_Cat_4.chip | 2 +- config/chips/L1xx_Cat_5.chip | 2 +- config/chips/L41x_L42x.chip | 2 +- config/chips/L43x_L44x.chip | 2 +- config/chips/L45x_L46x.chip | 2 +- config/chips/L47x_L48x.chip | 2 +- config/chips/L496x_L4A6x.chip | 2 +- config/chips/L4Px.chip | 2 +- config/chips/L4Rx.chip | 2 +- config/chips/WBx0_WBx5.chip | 2 +- config/chips/WLx5.chip | 2 +- config/chips/unknown_device.chip | 2 +- inc/stlink.h | 32 +- inc/stm32.h | 142 +++-- src/common.c | 96 +-- src/st-trace/trace.c | 2 +- src/st-util/gdb-server.c | 28 +- src/stlink-lib/chipid_db_old.h | 877 ---------------------------- src/stlink-lib/flash_loader.c | 92 +-- 67 files changed, 254 insertions(+), 1135 deletions(-) delete mode 100644 src/stlink-lib/chipid_db_old.h diff --git a/config/chips/F03x.chip b/config/chips/F03x.chip index d19e6a657..3b4ff2a74 100644 --- a/config/chips/F03x.chip +++ b/config/chips/F03x.chip @@ -2,7 +2,7 @@ # dev_type STM32F03x ref_manual_id 0091 -chip_id 0x444 // STLINK_CHIPID_STM32_F0xx_SMALL +chip_id 0x444 // STM32_CHIPID_STM32_F0xx_SMALL flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 7012d6d7e..267c93765 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -2,7 +2,7 @@ # dev_type STM32F04x ref_manual_id 0091 -chip_id 0x445 // STLINK_CHIPID_STM32_F04 +chip_id 0x445 // STM32_CHIPID_STM32_F04 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F05x.chip b/config/chips/F05x.chip index e987cf725..dc511e1a2 100644 --- a/config/chips/F05x.chip +++ b/config/chips/F05x.chip @@ -2,7 +2,7 @@ # dev_type STM32F05x ref_manual_id 0091 -chip_id 0x440 // STLINK_CHIPID_STM32_F0 +chip_id 0x440 // STM32_CHIPID_STM32_F0 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index 0f7513e1b..b12ef1bab 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -2,7 +2,7 @@ # dev_type STM32F07x ref_manual_id 0091 -chip_id 0x448 // STLINK_CHIPID_STM32_F0_CAN +chip_id 0x448 // STM32_CHIPID_STM32_F0_CAN flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index 3d3cc8c89..97f1a1a75 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -2,7 +2,7 @@ # dev_type STM32F09x ref_manual_id 0091 -chip_id 0x442 // STLINK_CHIPID_STM32_F09x +chip_id 0x442 // STM32_CHIPID_STM32_F09x flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index eb417132a..dd316dca3 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_CL ref_manual_id 0008 -chip_id 0x418 // STLINK_CHIPID_STM32_F1_CONN +chip_id 0x418 // STM32_CHIPID_STM32_F1_CONN flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_HD.chip b/config/chips/F1xx_HD.chip index 5def8ebb9..696b284ba 100644 --- a/config/chips/F1xx_HD.chip +++ b/config/chips/F1xx_HD.chip @@ -2,7 +2,7 @@ # dev_type F1xx_HD ref_manual_id 0008 -chip_id 0x414 // STLINK_CHIPID_STM32_F1_HD +chip_id 0x414 // STM32_CHIPID_STM32_F1_HD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_LD.chip b/config/chips/F1xx_LD.chip index 33efe063a..898af4c8c 100644 --- a/config/chips/F1xx_LD.chip +++ b/config/chips/F1xx_LD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_LD ref_manual_id 0008 -chip_id 0x412 // STLINK_CHIPID_STM32_F1_LD +chip_id 0x412 // STM32_CHIPID_STM32_F1_LD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F1xx_MD.chip b/config/chips/F1xx_MD.chip index 5b250d9cd..a611f3f2d 100644 --- a/config/chips/F1xx_MD.chip +++ b/config/chips/F1xx_MD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_MD ref_manual_id 0008 -chip_id 0x410 // STLINK_CHIPID_STM32_F1_MD +chip_id 0x410 // STM32_CHIPID_STM32_F1_MD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F1xx_VL_HD.chip b/config/chips/F1xx_VL_HD.chip index 1ceade91a..d59fa4814 100644 --- a/config/chips/F1xx_VL_HD.chip +++ b/config/chips/F1xx_VL_HD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_VL_HD ref_manual_id 0041 -chip_id 0x428 // STLINK_CHIPID_STM32_F1_VL_HD +chip_id 0x428 // STM32_CHIPID_STM32_F1_VL_HD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_VL_MD_LD.chip b/config/chips/F1xx_VL_MD_LD.chip index 3f577f74e..aac2244fd 100644 --- a/config/chips/F1xx_VL_MD_LD.chip +++ b/config/chips/F1xx_VL_MD_LD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_VL_MD_LD ref_manual_id 0041 -chip_id 0x420 // STLINK_CHIPID_STM32_F1_VL_MD_LD +chip_id 0x420 // STM32_CHIPID_STM32_F1_VL_MD_LD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip index 964105747..7627dd883 100644 --- a/config/chips/F1xx_XLD.chip +++ b/config/chips/F1xx_XLD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_XLD ref_manual_id 0008 -chip_id 0x430 // STLINK_CHIPID_STM32_F1_XLD +chip_id 0x430 // STM32_CHIPID_STM32_F1_XLD flash_type 2 // STM32_FLASH_TYPE_F1_XL flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip index 4cb99b2fc..5e6aac5a0 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2xx.chip @@ -2,7 +2,7 @@ # dev_type STM32F2xx ref_manual_id 0033 -chip_id 0x411 // STLINK_CHIPID_STM32_F2 +chip_id 0x411 // STM32_CHIPID_STM32_F2 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/F301_F302_F318.chip b/config/chips/F301_F302_F318.chip index b35de12bf..3a3d8bb45 100644 --- a/config/chips/F301_F302_F318.chip +++ b/config/chips/F301_F302_F318.chip @@ -2,7 +2,7 @@ # dev_type STM32F301_F302_F318 ref_manual_id 0365 // also RM0366 -chip_id 0x439 // STLINK_CHIPID_STM32_F3xx_SMALL +chip_id 0x439 // STM32_CHIPID_STM32_F3xx_SMALL flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F302_F303_F358.chip b/config/chips/F302_F303_F358.chip index 6226ca8e8..922387292 100644 --- a/config/chips/F302_F303_F358.chip +++ b/config/chips/F302_F303_F358.chip @@ -2,7 +2,7 @@ # dev_type STM32F302_F303_358 ref_manual_id 0365 // also RM0316 -chip_id 0x422 // STLINK_CHIPID_STM32_F3 +chip_id 0x422 // STM32_CHIPID_STM32_F3 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F302_F303_F398_HD.chip b/config/chips/F302_F303_F398_HD.chip index b4ad3aed8..44cec8a6d 100644 --- a/config/chips/F302_F303_F398_HD.chip +++ b/config/chips/F302_F303_F398_HD.chip @@ -2,7 +2,7 @@ # dev_type STM32F302_F303_F398_HD ref_manual_id 0365 // also RM0316 (Rev 5) -chip_id 0x446 // STLINK_CHIPID_STM32_F303_HD +chip_id 0x446 // STM32_CHIPID_STM32_F303_HD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F303_F328_F334.chip b/config/chips/F303_F328_F334.chip index 010c3b622..fb77e3117 100644 --- a/config/chips/F303_F328_F334.chip +++ b/config/chips/F303_F328_F334.chip @@ -2,7 +2,7 @@ # dev_type STM32F303_F328_F334 ref_manual_id 0364 // also RM0316 -chip_id 0x438 // STLINK_CHIPID_STM32_F334 +chip_id 0x438 // STM32_CHIPID_STM32_F334 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index 9ca9d72f8..5363da8fa 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -2,7 +2,7 @@ # dev_type STM32F37x ref_manual_id 0313 -chip_id 0x432 // STLINK_CHIPID_STM32_F37x +chip_id 0x432 // STM32_CHIPID_STM32_F37x flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F401xB_xC.chip b/config/chips/F401xB_xC.chip index e1f37d94b..e75b27d09 100644 --- a/config/chips/F401xB_xC.chip +++ b/config/chips/F401xB_xC.chip @@ -2,7 +2,7 @@ # dev_type STM32F401xB_xC ref_manual_id 0368 -chip_id 0x423 // STLINK_CHIPID_STM32_F4_LP +chip_id 0x423 // STM32_CHIPID_STM32_F4_LP flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip index f03661495..022d5072a 100644 --- a/config/chips/F401xD_xE.chip +++ b/config/chips/F401xD_xE.chip @@ -2,7 +2,7 @@ # dev_type STM32F401xD_xE ref_manual_id 0368 -chip_id 0x433 // STLINK_CHIPID_STM32_F4_DE +chip_id 0x433 // STM32_CHIPID_STM32_F4_DE flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F410.chip b/config/chips/F410.chip index 6f7727921..84c9c00bf 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -2,7 +2,7 @@ # dev_type STM32F410 ref_manual_id 0401 -chip_id 0x458 // STLINK_CHIPID_STM32_F410 +chip_id 0x458 // STM32_CHIPID_STM32_F410 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F411xC_xE.chip b/config/chips/F411xC_xE.chip index 5d624b7d9..d028a874c 100644 --- a/config/chips/F411xC_xE.chip +++ b/config/chips/F411xC_xE.chip @@ -2,7 +2,7 @@ # dev_type STM32F411xC_xE ref_manual_id 0383 -chip_id 0x431 // STLINK_CHIPID_STM32_F411xx +chip_id 0x431 // STM32_CHIPID_STM32_F411xx flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F412.chip b/config/chips/F412.chip index bd18ec2ea..b4c1cb418 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -2,7 +2,7 @@ # dev_type STM32F412 ref_manual_id 0402 -chip_id 0x441 // STLINK_CHIPID_STM32_F412 +chip_id 0x441 // STM32_CHIPID_STM32_F412 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F413_F423.chip b/config/chips/F413_F423.chip index c7e036a2d..f042bce76 100644 --- a/config/chips/F413_F423.chip +++ b/config/chips/F413_F423.chip @@ -2,7 +2,7 @@ # dev_type STM32F413_F423 ref_manual_id 0430 // RM0430 (Rev 2) -chip_id 0x463 // STLINK_CHIPID_STM32_F413 +chip_id 0x463 // STM32_CHIPID_STM32_F413 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index cbb77e152..69aff7c88 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -2,7 +2,7 @@ # dev_type STM32F42x_F43x ref_manual_id 0090 // RM0090 (Rev. 2) -chip_id 0x463 // STLINK_CHIPID_STM32_F4_HD +chip_id 0x463 // STM32_CHIPID_STM32_F4_HD flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 2ac868ddd..5fa2edbcb 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -2,7 +2,7 @@ # dev_type STM32F446 ref_manual_id 0390 -chip_id 0x421 // STLINK_CHIPID_STM32_F446 +chip_id 0x421 // STM32_CHIPID_STM32_F446 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index e8d66cbd7..e8364ead5 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -2,7 +2,7 @@ # dev_type STM32F46x_F47x ref_manual_id 0090 // RM0090 (Rev. 2) -chip_id 0x434 // STLINK_CHIPID_STM32_F4_DSI +chip_id 0x434 // STM32_CHIPID_STM32_F4_DSI flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F4x5_F4x7.chip b/config/chips/F4x5_F4x7.chip index d75f74103..e78b552c4 100644 --- a/config/chips/F4x5_F4x7.chip +++ b/config/chips/F4x5_F4x7.chip @@ -2,7 +2,7 @@ # dev_type STM32F4x5_F4x7 ref_manual_id 0090 // RM0090 (Rev. 2) -chip_id 0x413 // STLINK_CHIPID_STM32_F4 +chip_id 0x413 // STM32_CHIPID_STM32_F4 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index c0f2df155..5e1131d2e 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -2,7 +2,7 @@ # dev_type STM32F72x_F73x ref_manual_id 0431 -chip_id 0x452 // STLINK_CHIPID_STM32_F72xxx +chip_id 0x452 // STM32_CHIPID_STM32_F72xxx flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff07a22 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F74x_F75x.chip b/config/chips/F74x_F75x.chip index fa0b6ddc2..391ae124d 100644 --- a/config/chips/F74x_F75x.chip +++ b/config/chips/F74x_F75x.chip @@ -2,7 +2,7 @@ # dev_type STM32F74x_F75x ref_manual_id 0385 -chip_id 0x449 // STLINK_CHIPID_STM32_F7 +chip_id 0x449 // STM32_CHIPID_STM32_F7 flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F76x_F77x.chip b/config/chips/F76x_F77x.chip index c1a5a9cf2..bb87dce7a 100644 --- a/config/chips/F76x_F77x.chip +++ b/config/chips/F76x_F77x.chip @@ -2,7 +2,7 @@ # dev_type STM32F76x_F77x ref_manual_id 0410 -chip_id 0x451 // STLINK_CHIPID_STM32_F76xxx +chip_id 0x451 // STM32_CHIPID_STM32_F76xxx flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G03x_G04x.chip b/config/chips/G03x_G04x.chip index aee016e0d..4a7e11fcd 100644 --- a/config/chips/G03x_G04x.chip +++ b/config/chips/G03x_G04x.chip @@ -2,7 +2,7 @@ # dev_type STM32G03x_G04x ref_manual_id 0444 // also RM454 -chip_id 0x466 // STLINK_CHIPID_STM32_G0_CAT1 +chip_id 0x466 // STM32_CHIPID_STM32_G0_CAT1 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index f92cad889..81f97b58d 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -2,7 +2,7 @@ # dev_type STM32G05x_G06x ref_manual_id 0444 -chip_id 0x456 // STLINK_CHIPID_STM32_G0_CAT4 +chip_id 0x456 // STM32_CHIPID_STM32_G0_CAT4 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G07x_G08x.chip b/config/chips/G07x_G08x.chip index 29f527e73..cac804a78 100644 --- a/config/chips/G07x_G08x.chip +++ b/config/chips/G07x_G08x.chip @@ -2,7 +2,7 @@ # dev_type STM32G07x_G08x ref_manual_id 0444 -chip_id 0x460 // STLINK_CHIPID_STM32_G0_CAT2 +chip_id 0x460 // STM32_CHIPID_STM32_G0_CAT2 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index 67254fbbd..845cf8280 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -2,7 +2,7 @@ # dev_type STM32G0Bx_G0Cx ref_manual_id 0444 -chip_id 0x467 // STLINK_CHIPID_STM32_G0_CAT3 +chip_id 0x467 // STM32_CHIPID_STM32_G0_CAT3 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G43x_G44x.chip b/config/chips/G43x_G44x.chip index b33a1a0f8..6b19d4fb4 100644 --- a/config/chips/G43x_G44x.chip +++ b/config/chips/G43x_G44x.chip @@ -2,7 +2,7 @@ # dev_type STM32G43x_G44x ref_manual_id 0440 -chip_id 0x468 // STLINK_CHIPID_STM32_G4_CAT2 +chip_id 0x468 // STM32_CHIPID_STM32_G4_CAT2 flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G47x_G48x.chip b/config/chips/G47x_G48x.chip index abf6a6f2d..d3330da59 100644 --- a/config/chips/G47x_G48x.chip +++ b/config/chips/G47x_G48x.chip @@ -2,7 +2,7 @@ # dev_type STM32G47x_G48x ref_manual_id 0440 -chip_id 0x469 // STLINK_CHIPID_STM32_G4_CAT3 +chip_id 0x469 // STM32_CHIPID_STM32_G4_CAT3 flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip index 3d8110f19..a39237142 100644 --- a/config/chips/G49x_G4Ax.chip +++ b/config/chips/G49x_G4Ax.chip @@ -2,7 +2,7 @@ # dev_type STM32G49x_G4Ax ref_manual_id 0440 -chip_id 0x479 // STLINK_CHIPID_STM32_G4_CAT4 +chip_id 0x479 // STM32_CHIPID_STM32_G4_CAT4 flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index 1417cdb27..998aa9812 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -2,7 +2,7 @@ # dev_type STM32H72x_H73x ref_manual_id 0468 -chip_id 0x483 // STLINK_CHIPID_STM32_H72x +chip_id 0x483 // STM32_CHIPID_STM32_H72x flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 53a3e921a..0bfea13a4 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -2,7 +2,7 @@ # dev_type STM32H74x_H75x ref_manual_id 0433 -chip_id 0x450 // STLINK_CHIPID_STM32_H74xxx +chip_id 0x450 // STM32_CHIPID_STM32_H74xxx flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index 516c4260e..2e784193c 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -2,7 +2,7 @@ # dev_type STM32H7Ax_H7Bx ref_manual_id 0455 -chip_id 0x480 // STLINK_CHIPID_STM32_H7Ax +chip_id 0x480 // STM32_CHIPID_STM32_H7Ax flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x08fff80c flash_pagesize 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_1.chip b/config/chips/L0xxx_Cat_1.chip index 6dc227024..4b108b4f4 100644 --- a/config/chips/L0xxx_Cat_1.chip +++ b/config/chips/L0xxx_Cat_1.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_1 ref_manual_id 0451 // also RM0377 -chip_id 0x457 // STLINK_CHIPID_STM32_L011 +chip_id 0x457 // STM32_CHIPID_STM32_L011 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L0xxx_Cat_2.chip b/config/chips/L0xxx_Cat_2.chip index 74a3d6157..5665e8df1 100644 --- a/config/chips/L0xxx_Cat_2.chip +++ b/config/chips/L0xxx_Cat_2.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_2 ref_manual_id 0451 // also RM0377 -chip_id 0x425 // STLINK_CHIPID_STM32_L0_CAT2 +chip_id 0x425 // STM32_CHIPID_STM32_L0_CAT2 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L0xxx_Cat_3.chip b/config/chips/L0xxx_Cat_3.chip index 0cfcc53bb..e8cd7c685 100644 --- a/config/chips/L0xxx_Cat_3.chip +++ b/config/chips/L0xxx_Cat_3.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_3 ref_manual_id 0451 // also RM0367 & RM0377 -chip_id 0x417 // STLINK_CHIPID_STM32_L0 +chip_id 0x417 // STM32_CHIPID_STM32_L0 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L0xxx_Cat_5.chip b/config/chips/L0xxx_Cat_5.chip index cbb1e6632..284057091 100644 --- a/config/chips/L0xxx_Cat_5.chip +++ b/config/chips/L0xxx_Cat_5.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_5 ref_manual_id 0451 // also RM0367 & RM0377 -chip_id 0x447 // STLINK_CHIPID_STM32_L0_CAT5 +chip_id 0x447 // STM32_CHIPID_STM32_L0_CAT5 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L1xx_Cat_1.chip b/config/chips/L1xx_Cat_1.chip index cecc32996..f6a11288f 100644 --- a/config/chips/L1xx_Cat_1.chip +++ b/config/chips/L1xx_Cat_1.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_1 ref_manual_id 0038 -chip_id 0x416 // STLINK_CHIPID_STM32_L1_MD +chip_id 0x416 // STM32_CHIPID_STM32_L1_MD flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_2.chip b/config/chips/L1xx_Cat_2.chip index 1981d58a5..c8c796111 100644 --- a/config/chips/L1xx_Cat_2.chip +++ b/config/chips/L1xx_Cat_2.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_2 ref_manual_id 0038 -chip_id 0x429 // STLINK_CHIPID_STM32_L1_CAT2 +chip_id 0x429 // STM32_CHIPID_STM32_L1_CAT2 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_3.chip b/config/chips/L1xx_Cat_3.chip index 1d551c8a4..f2615f952 100644 --- a/config/chips/L1xx_Cat_3.chip +++ b/config/chips/L1xx_Cat_3.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_3 ref_manual_id 0038 -chip_id 0x427 // STLINK_CHIPID_STM32_L1_MD_PLUS +chip_id 0x427 // STM32_CHIPID_STM32_L1_MD_PLUS flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_4.chip b/config/chips/L1xx_Cat_4.chip index 1e9cfe91c..6a1df1267 100644 --- a/config/chips/L1xx_Cat_4.chip +++ b/config/chips/L1xx_Cat_4.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_4 ref_manual_id 0038 -chip_id 0x436 // STLINK_CHIPID_STM32_L1_MD_PLUS_HD +chip_id 0x436 // STM32_CHIPID_STM32_L1_MD_PLUS_HD flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_5.chip b/config/chips/L1xx_Cat_5.chip index a51356d7a..4fccd99da 100644 --- a/config/chips/L1xx_Cat_5.chip +++ b/config/chips/L1xx_Cat_5.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_5 ref_manual_id 0038 -chip_id 0x437 // STLINK_CHIPID_STM32_L152_RE +chip_id 0x437 // STM32_CHIPID_STM32_L152_RE flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B diff --git a/config/chips/L41x_L42x.chip b/config/chips/L41x_L42x.chip index 2de859b0c..40085d828 100644 --- a/config/chips/L41x_L42x.chip +++ b/config/chips/L41x_L42x.chip @@ -2,7 +2,7 @@ # dev_type STM32L41x_L42x ref_manual_id 0394 -chip_id 0x464 // STLINK_CHIPID_STM32_L41x_L42x +chip_id 0x464 // STM32_CHIPID_STM32_L41x_L42x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index 2dad90844..22045c372 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -2,7 +2,7 @@ # dev_type STM32L41x_L42x ref_manual_id 0392 -chip_id 0x435 // STLINK_CHIPID_STM32_L43x_L44x +chip_id 0x435 // STM32_CHIPID_STM32_L43x_L44x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index f856e1315..99e9beca1 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -2,7 +2,7 @@ # dev_type STM32L45x_L46x ref_manual_id 0394 -chip_id 0x462 // STLINK_CHIPID_STM32_L45x_L46x +chip_id 0x462 // STM32_CHIPID_STM32_L45x_L46x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L47x_L48x.chip b/config/chips/L47x_L48x.chip index 51257a37c..44e5282ce 100644 --- a/config/chips/L47x_L48x.chip +++ b/config/chips/L47x_L48x.chip @@ -2,7 +2,7 @@ # dev_type STM32L47x_L48x ref_manual_id 0351 -chip_id 0x415 // STLINK_CHIPID_STM32_L4 +chip_id 0x415 // STM32_CHIPID_STM32_L4 flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 32d75b571..b983eb9eb 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -2,7 +2,7 @@ # dev_type STM32L496x_L4A6x ref_manual_id 0351 -chip_id 0x461 // STLINK_CHIPID_STM32_L496x_L4A6x +chip_id 0x461 // STM32_CHIPID_STM32_L496x_L4A6x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L4Px.chip b/config/chips/L4Px.chip index ff3f05b81..41805c768 100644 --- a/config/chips/L4Px.chip +++ b/config/chips/L4Px.chip @@ -2,7 +2,7 @@ # dev_type STM32L4Px ref_manual_id 0432 -chip_id 0x471 // STLINK_CHIPID_STM32_L4PX +chip_id 0x471 // STM32_CHIPID_STM32_L4PX flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index 535e282c9..d0495f083 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -2,7 +2,7 @@ # dev_type STM32L4Rx ref_manual_id 0432 -chip_id 0x470 // STLINK_CHIPID_STM32_L4RX +chip_id 0x470 // STM32_CHIPID_STM32_L4RX flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB diff --git a/config/chips/WBx0_WBx5.chip b/config/chips/WBx0_WBx5.chip index 5fa76ec75..e34c70815 100644 --- a/config/chips/WBx0_WBx5.chip +++ b/config/chips/WBx0_WBx5.chip @@ -2,7 +2,7 @@ # dev_type STM32WBx0_WBx5 ref_manual_id 0434 // also RM0471 -chip_id 0x495 // STLINK_CHIPID_STM32_WB55 +chip_id 0x495 // STM32_CHIPID_STM32_WB55 flash_type 11 // STM32_FLASH_TYPE_WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB diff --git a/config/chips/WLx5.chip b/config/chips/WLx5.chip index 62ff4f72f..b27e03dfe 100644 --- a/config/chips/WLx5.chip +++ b/config/chips/WLx5.chip @@ -2,7 +2,7 @@ # dev_type STM32WLEx ref_manual_id 0033 -chip_id 0x497 // STLINK_CHIPID_STM32_WLE +chip_id 0x497 // STM32_CHIPID_STM32_WLE flash_type 11 // STM32_FLASH_TYPE_WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index 512211092..bc50e7a00 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -2,7 +2,7 @@ # dev_type unknown ref_manual_id 0000 -chip_id 0x0 // STLINK_CHIPID_UNKNOWN +chip_id 0x0 // STM32_CHIPID_UNKNOWN flash_type 0 // STM32_FLASH_TYPE_UNKNOWN flash_size_reg 0x0 flash_pagesize 0x0 diff --git a/inc/stlink.h b/inc/stlink.h index b387881ae..f6bd5cb0d 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -106,22 +106,22 @@ enum target_state { #define C_BUF_LEN 32 -/* Old flash type definitions */ -// TODO: Transition to the new defines in stm32.h -enum stlink_flash_type { - /* 0 */ STLINK_FLASH_TYPE_UNKNOWN = 0, - /* 1 */ STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */ - /* 2 */ STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank */ - /* 3 */ STLINK_FLASH_TYPE_F4, // used by f2, f4 */ - /* 4 */ STLINK_FLASH_TYPE_F7, - /* 5 */ STLINK_FLASH_TYPE_L0, // l0, l1 */ - /* 6 */ STLINK_FLASH_TYPE_L4, // l4, l4+ */ - /* 7 */ STLINK_FLASH_TYPE_G0, - /* 8 */ STLINK_FLASH_TYPE_G4, - /* 9 */ STLINK_FLASH_TYPE_WB, - /* 10 */ STLINK_FLASH_TYPE_H7, - /* 11 */ STLINK_FLASH_TYPE_MAX, -}; +// /* Old flash type definitions */ +// // TODO: Transition to the new defines in stm32.h +// enum stlink_flash_type { +// /* 0 */ STLINK_FLASH_TYPE_UNKNOWN = 0, +// /* 1 */ STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */ +// /* 2 */ STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank */ +// /* 3 */ STLINK_FLASH_TYPE_F4, // used by f2, f4 */ +// /* 4 */ STLINK_FLASH_TYPE_F7, +// /* 5 */ STLINK_FLASH_TYPE_L0, // l0, l1 */ +// /* 6 */ STLINK_FLASH_TYPE_L4, // l4, l4+ */ +// /* 7 */ STLINK_FLASH_TYPE_G0, +// /* 8 */ STLINK_FLASH_TYPE_G4, +// /* 9 */ STLINK_FLASH_TYPE_WB, +// /* 10 */ STLINK_FLASH_TYPE_H7, +// /* 11 */ STLINK_FLASH_TYPE_MAX, +// }; struct stlink_reg { uint32_t r[16]; diff --git a/inc/stm32.h b/inc/stm32.h index 280a61107..8dff2a7d7 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -1,7 +1,7 @@ /* * File: stm32.h * - * STM32-specific defines + * STM32-specific defines & identification parametres */ #ifndef STM32_H @@ -32,6 +32,74 @@ enum stm32_flash_type { STM32_FLASH_TYPE_UNDEFINED = 12, // max. value exceeded }; +/* STM32 chip-ids */ +// See DBGMCU_IDCODE register (0xE0042000) in appropriate programming manual +// stm32 chipids, only lower 12 bits... + +enum stm32_chipids { + STM32_CHIPID_UNKNOWN = 0x000, + + STM32_CHIPID_STM32_F1_MD = 0x410, /* medium density */ + STM32_CHIPID_STM32_F2 = 0x411, + STM32_CHIPID_STM32_F1_LD = 0x412, /* low density */ + STM32_CHIPID_STM32_F4 = 0x413, + STM32_CHIPID_STM32_F1_HD = 0x414, /* high density */ + STM32_CHIPID_STM32_L4 = 0x415, + STM32_CHIPID_STM32_L1_MD = 0x416, /* medium density */ + STM32_CHIPID_STM32_L0 = 0x417, + STM32_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */ + STM32_CHIPID_STM32_F4_HD = 0x419, /* high density */ + STM32_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */ + STM32_CHIPID_STM32_F446 = 0x421, + STM32_CHIPID_STM32_F3 = 0x422, + STM32_CHIPID_STM32_F4_LP = 0x423, + STM32_CHIPID_STM32_L0_CAT2 = 0x425, + STM32_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */ + STM32_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */ + STM32_CHIPID_STM32_L1_CAT2 = 0x429, + STM32_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */ + STM32_CHIPID_STM32_F411xx = 0x431, + STM32_CHIPID_STM32_F37x = 0x432, + STM32_CHIPID_STM32_F4_DE = 0x433, + STM32_CHIPID_STM32_F4_DSI = 0x434, + STM32_CHIPID_STM32_L43x_L44x = 0x435, + STM32_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ + STM32_CHIPID_STM32_L152_RE = 0x437, + STM32_CHIPID_STM32_F334 = 0x438, + STM32_CHIPID_STM32_F3xx_SMALL = 0x439, + STM32_CHIPID_STM32_F0 = 0x440, + STM32_CHIPID_STM32_F412 = 0x441, + STM32_CHIPID_STM32_F09x = 0x442, + STM32_CHIPID_STM32_F0xx_SMALL = 0x444, + STM32_CHIPID_STM32_F04 = 0x445, + STM32_CHIPID_STM32_F303_HD = 0x446, /* high density */ + STM32_CHIPID_STM32_L0_CAT5 = 0x447, + STM32_CHIPID_STM32_F0_CAN = 0x448, + STM32_CHIPID_STM32_F7 = 0x449, /* Nucleo F746ZG board */ + STM32_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */ + STM32_CHIPID_STM32_F76xxx = 0x451, + STM32_CHIPID_STM32_F72xxx = 0x452, /* Nucleo F722ZE board */ + STM32_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */ + STM32_CHIPID_STM32_L011 = 0x457, + STM32_CHIPID_STM32_F410 = 0x458, + STM32_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */ + STM32_CHIPID_STM32_L496x_L4A6x = 0x461, + STM32_CHIPID_STM32_L45x_L46x = 0x462, + STM32_CHIPID_STM32_F413 = 0x463, + STM32_CHIPID_STM32_L41x_L42x = 0x464, + STM32_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */ + STM32_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */ + STM32_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ + STM32_CHIPID_STM32_G4_CAT3 = 0x469, + STM32_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ + STM32_CHIPID_STM32_L4PX = 0x471, /* RM0432, p.2247 */ + STM32_CHIPID_STM32_G4_CAT4 = 0x479, + STM32_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ + STM32_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ + STM32_CHIPID_STM32_WB55 = 0x495, + STM32_CHIPID_STM32_WLE = 0x497, +}; + /* Constant STM32 memory address */ #define STM32_SRAM_BASE ((uint32_t)0x20000000) #define STM32_FLASH_BASE ((uint32_t)0x08000000) @@ -60,76 +128,4 @@ enum stm32_flash_type { #define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) #define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) - -/* - * Chip IDs - * See DBGMCU_IDCODE register (0xE0042000) in appropriate programming manual - */ - -// stm32 chipids, only lower 12 bits... - -enum stlink_stm32_chipids { - STLINK_CHIPID_UNKNOWN = 0x000, - - STLINK_CHIPID_STM32_F1_MD = 0x410, /* medium density */ - STLINK_CHIPID_STM32_F2 = 0x411, - STLINK_CHIPID_STM32_F1_LD = 0x412, /* low density */ - STLINK_CHIPID_STM32_F4 = 0x413, - STLINK_CHIPID_STM32_F1_HD = 0x414, /* high density */ - STLINK_CHIPID_STM32_L4 = 0x415, - STLINK_CHIPID_STM32_L1_MD = 0x416, /* medium density */ - STLINK_CHIPID_STM32_L0 = 0x417, - STLINK_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */ - STLINK_CHIPID_STM32_F4_HD = 0x419, /* high density */ - STLINK_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */ - STLINK_CHIPID_STM32_F446 = 0x421, - STLINK_CHIPID_STM32_F3 = 0x422, - STLINK_CHIPID_STM32_F4_LP = 0x423, - STLINK_CHIPID_STM32_L0_CAT2 = 0x425, - STLINK_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */ - STLINK_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */ - STLINK_CHIPID_STM32_L1_CAT2 = 0x429, - STLINK_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */ - STLINK_CHIPID_STM32_F411xx = 0x431, - STLINK_CHIPID_STM32_F37x = 0x432, - STLINK_CHIPID_STM32_F4_DE = 0x433, - STLINK_CHIPID_STM32_F4_DSI = 0x434, - STLINK_CHIPID_STM32_L43x_L44x = 0x435, - STLINK_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ - STLINK_CHIPID_STM32_L152_RE = 0x437, - STLINK_CHIPID_STM32_F334 = 0x438, - STLINK_CHIPID_STM32_F3xx_SMALL = 0x439, - STLINK_CHIPID_STM32_F0 = 0x440, - STLINK_CHIPID_STM32_F412 = 0x441, - STLINK_CHIPID_STM32_F09x = 0x442, - STLINK_CHIPID_STM32_F0xx_SMALL = 0x444, - STLINK_CHIPID_STM32_F04 = 0x445, - STLINK_CHIPID_STM32_F303_HD = 0x446, /* high density */ - STLINK_CHIPID_STM32_L0_CAT5 = 0x447, - STLINK_CHIPID_STM32_F0_CAN = 0x448, - STLINK_CHIPID_STM32_F7 = 0x449, /* Nucleo F746ZG board */ - STLINK_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */ - STLINK_CHIPID_STM32_F76xxx = 0x451, - STLINK_CHIPID_STM32_F72xxx = 0x452, /* Nucleo F722ZE board */ - STLINK_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */ - STLINK_CHIPID_STM32_L011 = 0x457, - STLINK_CHIPID_STM32_F410 = 0x458, - STLINK_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */ - STLINK_CHIPID_STM32_L496x_L4A6x = 0x461, - STLINK_CHIPID_STM32_L45x_L46x = 0x462, - STLINK_CHIPID_STM32_F413 = 0x463, - STLINK_CHIPID_STM32_L41x_L42x = 0x464, - STLINK_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */ - STLINK_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */ - STLINK_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ - STLINK_CHIPID_STM32_G4_CAT3 = 0x469, - STLINK_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ - STLINK_CHIPID_STM32_L4PX = 0x471, /* RM0432, p.2247 */ - STLINK_CHIPID_STM32_G4_CAT4 = 0x479, - STLINK_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ - STLINK_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ - STLINK_CHIPID_STM32_WB55 = 0x495, - STLINK_CHIPID_STM32_WLE = 0x497, -}; - #endif // STM32_H diff --git a/src/common.c b/src/common.c index e73955f31..5a6d0d86b 100644 --- a/src/common.c +++ b/src/common.c @@ -334,7 +334,7 @@ #define FLASH_H7_CR_SER 2 #define FLASH_H7_CR_BER 3 #define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7Ax ? 5 : 7) +#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_STM32_H7Ax ? 5 : 7) #define FLASH_H7_CR_SNB 8 #define FLASH_H7_CR_SNB_MASK 0x700 @@ -441,16 +441,16 @@ uint16_t read_uint16(const unsigned char *c, const int pt) { static uint32_t get_stm32l0_flash_base(stlink_t *sl) { switch (sl->chip_id) { - case STLINK_CHIPID_STM32_L0: - case STLINK_CHIPID_STM32_L0_CAT5: - case STLINK_CHIPID_STM32_L0_CAT2: - case STLINK_CHIPID_STM32_L011: + case STM32_CHIPID_STM32_L0: + case STM32_CHIPID_STM32_L0_CAT5: + case STM32_CHIPID_STM32_L0_CAT2: + case STM32_CHIPID_STM32_L011: return (STM32L0_FLASH_REGS_ADDR); - case STLINK_CHIPID_STM32_L1_CAT2: - case STLINK_CHIPID_STM32_L1_MD: - case STLINK_CHIPID_STM32_L1_MD_PLUS: - case STLINK_CHIPID_STM32_L1_MD_PLUS_HD: + case STM32_CHIPID_STM32_L1_CAT2: + case STM32_CHIPID_STM32_L1_MD: + case STM32_CHIPID_STM32_L1_MD_PLUS: + case STM32_CHIPID_STM32_L1_MD_PLUS_HD: return (STM32L_FLASH_REGS_ADDR); default: @@ -1622,14 +1622,14 @@ int stlink_load_device_params(stlink_t *sl) { flash_size = flash_size & 0xffff; - if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MD || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || - sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS) && + if ((sl->chip_id == STM32_CHIPID_STM32_L1_MD || + sl->chip_id == STM32_CHIPID_STM32_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_STM32_L1_MD_PLUS) && (flash_size == 0)) { sl->flash_size = 128 * 1024; - } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { + } else if (sl->chip_id == STM32_CHIPID_STM32_L1_CAT2) { sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_MD_PLUS_HD) { + } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_STM32_L1_MD_PLUS_HD) { // 0 is 384k and 1 is 256k if (flash_size == 0) { sl->flash_size = 384 * 1024; @@ -1651,12 +1651,12 @@ int stlink_load_device_params(stlink_t *sl) { // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD && + if (sl->chip_id == STM32_CHIPID_STM32_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { sl->sram_size = 0x1000; } - if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { + if (sl->chip_id == STM32_CHIPID_STM32_G4_CAT3) { uint32_t flash_optr; stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); @@ -2706,9 +2706,9 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); flashaddr -= STM32_FLASH_BASE; - if (sl->chip_id == STLINK_CHIPID_STM32_L4 || - sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x || - sl->chip_id == STLINK_CHIPID_STM32_L4Rx) { + if (sl->chip_id == STM32_CHIPID_STM32_L4 || + sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x || + sl->chip_id == STM32_CHIPID_STM32_L4Rx) { // this chip use dual banked flash if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { uint32_t banksize = (uint32_t)sl->flash_size / 2; @@ -2726,16 +2726,16 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { - if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || - (sl->chip_id == STLINK_CHIPID_STM32_F4) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || - (sl->chip_id == STLINK_CHIPID_STM32_F411xx) || - (sl->chip_id == STLINK_CHIPID_STM32_F446) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || - (sl->chip_id == STLINK_CHIPID_STM32_F72xxx) || - (sl->chip_id == STLINK_CHIPID_STM32_F412)) { + if ((sl->chip_id == STM32_CHIPID_STM32_F2) || + (sl->chip_id == STM32_CHIPID_STM32_F4) || + (sl->chip_id == STM32_CHIPID_STM32_F4_DE) || + (sl->chip_id == STM32_CHIPID_STM32_F4_LP) || + (sl->chip_id == STM32_CHIPID_STM32_F4_HD) || + (sl->chip_id == STM32_CHIPID_STM32_F411xx) || + (sl->chip_id == STM32_CHIPID_STM32_F446) || + (sl->chip_id == STM32_CHIPID_STM32_F4_DSI) || + (sl->chip_id == STM32_CHIPID_STM32_F72xxx) || + (sl->chip_id == STM32_CHIPID_STM32_F412)) { uint32_t sector = calculate_F4_sectornum(flashaddr); if (sector >= 12) { @@ -2749,8 +2749,8 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { } else { sl->flash_pgsz = 0x20000; } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { + } else if (sl->chip_id == STM32_CHIPID_STM32_F7 || + sl->chip_id == STM32_CHIPID_STM32_F76xxx) { uint32_t sector = calculate_F7_sectornum(flashaddr); if (sector < 4) { @@ -2785,11 +2785,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { unlock_flash_if(sl); // select the page to erase - if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || - (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) || - (sl->chip_id == STLINK_CHIPID_STM32_L4Rx)) { + if ((sl->chip_id == STM32_CHIPID_STM32_L4) || + (sl->chip_id == STM32_CHIPID_STM32_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_STM32_L45x_L46x) || + (sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x) || + (sl->chip_id == STM32_CHIPID_STM32_L4Rx)) { // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); @@ -2797,8 +2797,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { + } else if (sl->chip_id == STM32_CHIPID_STM32_F7 || + sl->chip_id == STM32_CHIPID_STM32_F76xxx) { // calculate the actual page from the address uint32_t sector = calculate_F7_sectornum(flashaddr); @@ -2982,7 +2982,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { unlock_flash_if(sl); if (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { + sl->chip_id != STM32_CHIPID_STM32_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -3260,7 +3260,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { set_flash_cr_pg(sl, BANK_2); } - if (sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { + if (sl->chip_id != STM32_CHIPID_STM32_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -4357,17 +4357,17 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: + case STM32_CHIPID_STM32_F2: return stlink_read_option_bytes_f2(sl, option_byte); - case STLINK_CHIPID_STM32_F4: - case STLINK_CHIPID_STM32_F446: + case STM32_CHIPID_STM32_F4: + case STM32_CHIPID_STM32_F446: return stlink_read_option_bytes_f4(sl, option_byte); - case STLINK_CHIPID_STM32_F76xxx: + case STM32_CHIPID_STM32_F76xxx: return stlink_read_option_bytes_f7(sl, option_byte); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: + case STM32_CHIPID_STM32_G0_CAT1: + case STM32_CHIPID_STM32_G0_CAT2: + case STM32_CHIPID_STM32_G4_CAT2: + case STM32_CHIPID_STM32_G4_CAT3: return stlink_read_option_bytes_Gx(sl, option_byte); default: return stlink_read_option_bytes_generic(sl, option_byte); diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 46304d7d9..28a585071 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -540,7 +540,7 @@ int main(int argc, char **argv) { stlink->verbose = settings.logging_level; - if (stlink->chip_id == STLINK_CHIPID_UNKNOWN) { + if (stlink->chip_id == STM32_CHIPID_UNKNOWN) { ELOG("Your stlink is not connected to a device\n"); if (!settings.force) return APP_RESULT_STLINK_MISSING_DEVICE; diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 81c0aa83a..4babef0cc 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -226,7 +226,7 @@ int main(int argc, char** argv) { sl = stlink_open_usb(state.logging_level, state.connect_mode, state.serialnumber, state.freq); if (sl == NULL) { return(1); } - if (sl->chip_id == STLINK_CHIPID_UNKNOWN) { + if (sl->chip_id == STM32_CHIPID_UNKNOWN) { ELOG("Unsupported Target (Chip ID is %#010x, Core ID is %#010x).\n", sl->chip_id, sl->core_id); return(1); } @@ -553,39 +553,39 @@ char* make_memory_map(stlink_t *sl) { char* map = malloc(sz); map[0] = '\0'; - if (sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F446 || - sl->chip_id == STLINK_CHIPID_STM32_F411xx) { + if (sl->chip_id == STM32_CHIPID_STM32_F4 || + sl->chip_id == STM32_CHIPID_STM32_F446 || + sl->chip_id == STM32_CHIPID_STM32_F411xx) { strcpy(map, memory_map_template_F4); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) { + } else if (sl->chip_id == STM32_CHIPID_STM32_F4_DE) { strcpy(map, memory_map_template_F4_DE); } else if (sl->core_id == STM32F7_CORE_ID) { snprintf(map, sz, memory_map_template_F7, (unsigned int)sl->sram_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_H74xxx) { + } else if (sl->chip_id == STM32_CHIPID_STM32_H74xxx) { snprintf(map, sz, memory_map_template_H7, (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) { + } else if (sl->chip_id == STM32_CHIPID_STM32_F4_HD) { strcpy(map, memory_map_template_F4_HD); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F2) { + } else if (sl->chip_id == STM32_CHIPID_STM32_F2) { snprintf(map, sz, memory_map_template_F2, (unsigned int)sl->flash_size, (unsigned int)sl->sram_size, (unsigned int)sl->flash_size - 0x20000, (unsigned int)sl->sys_base, (unsigned int)sl->sys_size); - } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x)) { + } else if ((sl->chip_id == STM32_CHIPID_STM32_L4) || + (sl->chip_id == STM32_CHIPID_STM32_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_STM32_L45x_L46x)) { snprintf(map, sz, memory_map_template_L4, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) { + } else if (sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x) { snprintf(map, sz, memory_map_template_L496, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id == STLINK_CHIPID_STM32_H72x) { + } else if (sl->chip_id == STM32_CHIPID_STM32_H72x) { snprintf(map, sz, memory_map_template_H72x3x, (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); @@ -1847,7 +1847,7 @@ int serve(stlink_t *sl, st_state_t *st) { stlink_close(sl); sl = stlink_open_usb(st->logging_level, st->connect_mode, st->serialnumber, st->freq); - if (sl == NULL || sl->chip_id == STLINK_CHIPID_UNKNOWN) { cleanup(0); } + if (sl == NULL || sl->chip_id == STM32_CHIPID_UNKNOWN) { cleanup(0); } connected_stlink = sl; diff --git a/src/stlink-lib/chipid_db_old.h b/src/stlink-lib/chipid_db_old.h deleted file mode 100644 index 6578e35be..000000000 --- a/src/stlink-lib/chipid_db_old.h +++ /dev/null @@ -1,877 +0,0 @@ -// This is the old chipid "database". -// It is kept here for now to be able to compare the -// result between the "old code" and the "new code". -// For now if you need to change something, please -// change it both here and in the corresponding -// config/chips/*.chip file. - -//static struct stlink_chipid_params devices[] = { - { - // STM32F03x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0xx_SMALL, - .dev_type = "F03x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F04x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F04, - .dev_type = "F04x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x1800, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F05x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0, - .dev_type = "F05x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x400, // Page sizes listed in Table 4 - .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2 - .bootrom_size = 0xC00, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F07x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F0_CAN, - .dev_type = "F07x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 - .sram_size = 0x4000, // "SRAM" byte size in hex from Table 2 - .bootrom_base = 0x1fffC800, // "System memory" starting address from Table 2 - .bootrom_size = 0x3000, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F09x - // RM0091 - .chip_id = STLINK_CHIPID_STM32_F09x, - .dev_type = "F09x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735) - .flash_pagesize = 0x800, // Page sizes listed in Table 4 (pg 56) - .sram_size = 0x8000, // "SRAM" byte size in hex from Table 2 (pg 50) - .bootrom_base = 0x1fffd800, // "System memory" starting address from Table 2 - .bootrom_size = 0x2000, // "System memory" byte size in hex from Table 2 - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - }, - { - // STM32F1xx low- and medium-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_MD_LD, - .dev_type = "F1xx Value Line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2000, // 0x1000 for low density devices - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx high-density value line devices - // RM0041 - .chip_id = STLINK_CHIPID_STM32_F1_VL_HD, - .dev_type = "F1xx High-density value line", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x8000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx low-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_LD, - .dev_type = "F1 Low-density device", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x2800, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx medium-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_MD, - .dev_type = "F1xx Medium-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x400, - .sram_size = 0x5000, - .bootrom_base = 0x1ffff000, // 2.3.3 "Embedded Flash memory" - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx high-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_HD, - .dev_type = "F1xx High-density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx XL-density devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_XLD, - .dev_type = "F1xx XL-density", - .flash_type = STLINK_FLASH_TYPE_F1_XL, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x18000, - .bootrom_base = 0x1fffe000, - .bootrom_size = 0x1800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F1xx connectivity devices - // RM0008 - .chip_id = STLINK_CHIPID_STM32_F1_CONN, - .dev_type = "F1xx CL", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7e0, - .flash_pagesize = 0x800, - .sram_size = 0x10000, - .bootrom_base = 0x1fffb000, - .bootrom_size = 0x4800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F205xx, STM32F207xx, STM32F215xx, STM32F217xx - // RM0033 (rev 5) - .chip_id = STLINK_CHIPID_STM32_F2, - .dev_type = "F2xx", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F301x6/8, STM32F302x6x8, STM32F318x8 - // RM0366, RM0365 - .chip_id = STLINK_CHIPID_STM32_F3xx_SMALL, - .dev_type = "F301/F302/F318", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F302xBxC, STM32F303xB/C, STM32F358 - // RM0316, RM0365 - .chip_id = STLINK_CHIPID_STM32_F3, - .dev_type = "F302/F303/F358", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F302xD/E, STM32F303xD/E, STM32F398xE, - // RM0316 (rev 5), RM0365 - .chip_id = STLINK_CHIPID_STM32_F303_HD, - .dev_type = "F303 high density", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, // 34.2.1 Flash size data register - .flash_pagesize = 0x800, // 4.2.1 Flash memory organization - .sram_size = 0x10000, // 3.3 Embedded SRAM - .bootrom_base = 0x1fffd800, // 3.3.2 / Table 4 System Memory - .bootrom_size = 0x2000, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F303x6/8, STM32F328, STM32F334 - // RM0364, RM0316 - .chip_id = STLINK_CHIPID_STM32_F334, - .dev_type = "F303/F328/F334", // (RM0316 sec 33.6.1) - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0x3000, - .bootrom_base = 0x1fffd800, - .bootrom_size = 0x2000, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F373Cx/Rx/Vx, STM32F378Cx/Rx/Vx - // RM0313 - .chip_id = STLINK_CHIPID_STM32_F37x, - .dev_type = "F37x", - .flash_type = STLINK_FLASH_TYPE_F0, - .flash_size_reg = 0x1ffff7cc, - .flash_pagesize = 0x800, - .sram_size = 0xa000, - .bootrom_base = 0x1ffff000, - .bootrom_size = 0x800, - .option_base = STM32_F0_OPTION_BYTES_BASE, - .option_size = 16, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_LP, - .dev_type = "F401xB/C", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F4_DE, - .dev_type = "F401xD/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F410 - // RM0401 - .chip_id = STLINK_CHIPID_STM32_F410, - .dev_type = "F410", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x4000, - .sram_size = 0x8000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - .chip_id = STLINK_CHIPID_STM32_F411xx, - .dev_type = "F411xC/E", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F412 - // RM0402 - .chip_id = STLINK_CHIPID_STM32_F412, - .dev_type = "F412", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" (pg1135) - .flash_pagesize = 0x4000, // Table 5. Flash module organization ? - .sram_size = 0x40000, // "SRAM" byte size in hex from Table 4 - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F413/F423 - // RM0430 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F413, - .dev_type = "F413/F423", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, // "Flash size data register" Section 35.2 - .flash_pagesize = 0x4000, // Table 5. Flash module organization (variable sector - // sizes, but 0x4000 is smallest) - .sram_size = 0x50000, // "SRAM" byte size in hex from Figure 2 (Table 4 - // only says 0x40000) - .bootrom_base = 0x1FFF0000, // "System memory" starting address from Table 4 - .bootrom_size = 0x7800, // "System memory" byte size in hex from Table 4 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F42x/F43x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_HD, - .dev_type = "F42x/F43x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F446x family - // RM0390 - .chip_id = STLINK_CHIPID_STM32_F446, - .dev_type = "F446", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1fff7a22, - .flash_pagesize = 0x20000, - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = 0x1FFFC000, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F46x/F47x - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4_DSI, - .dev_type = "F46x/F47x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F4x5/F4x7 - // RM0090 (rev 2) - .chip_id = STLINK_CHIPID_STM32_F4, - .dev_type = "F4x5/F4x7", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1FFF7A22, - .flash_pagesize = 0x4000, - .sram_size = 0x30000, - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7800, - .option_base = STM32_F4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F72x/F73x - // RM0431 - .chip_id = STLINK_CHIPID_STM32_F72xxx, - .dev_type = "F72x/F73x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff07a22, // section 35.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x40000, // "SRAM" byte size in hex from DS Fig 24 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 24 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 24 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F74x/F75x - // RM0385, DS10916 - .chip_id = STLINK_CHIPID_STM32_F7, - .dev_type = "F74x/F75x", - .flash_type = STLINK_FLASH_TYPE_F4, - .flash_size_reg = 0x1ff0f442, // section 41.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x50000, // "SRAM" byte size in hex from DS Fig 18 - .bootrom_base = 0x00100000, // "System memory" starting address from DS Fig 18 - .bootrom_size = 0xEDC0, // "System memory" byte size in hex from DS Fig 18 - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32F76x/F77x - // RM0410 - .chip_id = STLINK_CHIPID_STM32_F76xxx, - .dev_type = "F76x/F77x", - .flash_type = STLINK_FLASH_TYPE_F7, - .flash_size_reg = 0x1ff0f442, // section 45.2 - .flash_pagesize = 0x800, // No flash pages - .sram_size = 0x80000, // "SRAM" byte size in hex from - .bootrom_base = 0x00200000, // "System memory" starting address from - .bootrom_size = 0xEDC0, - .option_base = STM32_F7_OPTION_BYTES_BASE, /* Used for reading back the option - bytes, writing uses FLASH_F7_OPTCR - and FLASH_F7_OPTCR1 */ - .option_size = 0x20, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32G030/031/041 - // RM0454, RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT1, - .dev_type = "G03x/G04x", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x2000, // 8k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x2000, // 8k (sec 2.2.2 table 3) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G051/G061 - // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT4, - .dev_type = "G05x/G06x", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G071/081 - // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT2, - .dev_type = "G07x/G08x", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - }, - { - // STM32G0B1/G0C1 - // RM0444 - .chip_id = STLINK_CHIPID_STM32_G0_CAT3, - .dev_type = "G0Bx/G0Cx", - .flash_type = STLINK_FLASH_TYPE_G0, - .flash_size_reg = 0x1FFF75E0, // Section 38.2 - .flash_pagesize = 0x800, // 2k (sec 3.2) - .sram_size = 0x9000, // 36k (sec 2.3) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (sec 2.2.2 table 2) - .option_base = STM32_G0_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_DUAL_BANK, - }, - { - // STM32G431/441 - // RM0440 - .chip_id = STLINK_CHIPID_STM32_G4_CAT2, - .dev_type = "G43x/G44x", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 16k at 0x20000000 - // SRAM2 is 6k at 0x20014000 - // SRAM3/CCM is 10k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x8000, // 32k (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32G471/473/474/483/484 - // RM0440 - .chip_id = STLINK_CHIPID_STM32_G4_CAT3, - .dev_type = "G47x/G48x", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 80k at 0x20000000 - // SRAM2 is 16k at 0x20014000 - // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x20000, // 128k (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32G491/G4A1 - // RM0440 - .chip_id = STLINK_CHIPID_STM32_G4_CAT4, - .dev_type = "G49x/G4Ax", - .flash_type = STLINK_FLASH_TYPE_G4, - .flash_size_reg = 0x1FFF75E0, // Section 47.2 - .flash_pagesize = 0x800, // 2k (sec 3.3.1) - // SRAM1 is 80k at 0x20000000 - // SRAM2 is 16k at 0x20014000 - // SRAM3/CCM is 32k at 0x10000000, aliased at 0x20018000 - .sram_size = 0x1C000, // 112k (sec 2.4) - .bootrom_base = 0x1fff0000, - .bootrom_size = 0x7000, // 28k (table 2) - .option_base = STM32_G4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32H7A3/7B3 - // RM0455 - .chip_id = STLINK_CHIPID_STM32_H7Ax, - .dev_type = "H7Ax/H7Bx", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x08FFF80C, // "Flash size register" (p.2949) - .flash_pagesize = 0x2000, // 8k sector (p.146) - .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 12-14) - .bootrom_size = 0x20000, // "System memory" byte size in hex splitted to - // two banks (Table 12-14) - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32H72x/H73x - // RM0468 - .chip_id = STLINK_CHIPID_STM32_H72x, - .dev_type = "H72x/H73x", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1FF1E880, // "Flash size register" (p.3286) - .flash_pagesize = 0x20000, // 128k sector (p.152) - .sram_size = 0x20000, // 128k "DTCM" (Figure 1) - .bootrom_base = 0x1FF00000, // "System memory" starting address (Table 6) - .bootrom_size = 0x20000, // "System memory" byte size in hex (Table 6) - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32H742/743/753 (from RM0433) - .chip_id = STLINK_CHIPID_STM32_H74xxx, - .dev_type = "H74x/H75x", - .flash_type = STLINK_FLASH_TYPE_H7, - .flash_size_reg = 0x1ff1e880, // "Flash size register" (pg3272) - .flash_pagesize = 0x20000, // 128k sector (pg147) - .sram_size = 0x20000, // 128k "DTCM" from Table 7 - .bootrom_base = 0x1ff00000, // "System memory" starting address from Table 7 - .bootrom_size = 0x20000, // "System memory" byte size in hex from Table 7 - .option_base = STM32_H7_OPTION_BYTES_BASE, - .option_size = 44, // FLASH_OPTSR_CUR to FLASH_BOOT_PRGR from Table 28 - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L0xx Category 1 - // RM0451, RM0377 - .chip_id = STLINK_CHIPID_STM32_L011, - .dev_type = "L01x/L02x", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x2000, - }, - { - // STM32L0x Category 2 - // RM0367, RM0377 - .chip_id = STLINK_CHIPID_STM32_L0_CAT2, - .dev_type = "L0xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - }, - { - // STM32L0xx Category 3 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0, - .dev_type = "L0xx Cat.3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x2000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x1000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - }, - { - // STM32L0x Category 5 - // RM0367, RM0377, RM0451 - .chip_id = STLINK_CHIPID_STM32_L0_CAT5, - .dev_type = "L0xx Cat.5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8007c, - .flash_pagesize = 0x80, - .sram_size = 0x5000, - .bootrom_base = 0x1ff0000, - .bootrom_size = 0x2000, - .option_base = STM32_L0_OPTION_BYTES_BASE, - .option_size = 20, - .flags = CHIP_F_HAS_DUAL_BANK, - }, - { - // STM32L100/L15x/L16x Cat.1 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD, - .dev_type = "L1xx Cat.1", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x4000, // up to 16k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.2 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_CAT2, - .dev_type = "L1xx Cat.2", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff8004c, - .flash_pagesize = 0x100, - .sram_size = 0x8000, // up to 32k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.3 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS, - .dev_type = "L1xx Cat.3", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x8000, // up to 32k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.4 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L1_MD_PLUS_HD, - .dev_type = "L1xx Cat.4", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0xC000, // up to 48k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .option_base = STM32_L1_OPTION_BYTES_BASE, - .option_size = 8, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L100/L15x/L16x Cat.5 - // RM0038 - .chip_id = STLINK_CHIPID_STM32_L152_RE, - .dev_type = "L1xx Cat.5", - .flash_type = STLINK_FLASH_TYPE_L0, - .flash_size_reg = 0x1ff800cc, - .flash_pagesize = 0x100, - .sram_size = 0x14000, // up to 80k - .bootrom_base = 0x1ff00000, - .bootrom_size = 0x1000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L41x_L42x - // RM0394 (rev 4), DS12469 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L41x_L42x, - .dev_type = "L41x/L42x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (RM0394, - // sec 47.2, page 1586) - .flash_pagesize = 0x800, // 2k (DS12469, sec 3.4, page 17) - // SRAM1 is 32k at 0x20000000 - // SRAM2 is 8k at 0x10000000 and 0x20008000 - // (DS12469, sec 3.5, page 18) - .sram_size = 0xa000, // 40k (DS12469, sec 3.5, page 18) - .bootrom_base = 0x1fff0000, // System Memory (RM0394, sec 3.3.1, table 8) - .bootrom_size = 0x7000, // 28k, same source as base - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L43x_L44x - // RM0392 - .chip_id = STLINK_CHIPID_STM32_L43x_L44x, - .dev_type = "L43x/L44x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 43.2, page 1410) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 74; also appears in sec 3.3.1 - // and tables 7-8 on pages 75-76) - // SRAM1 is "up to" 64k in the standard Cortex-M memory map; - // SRAM2 is 16k mapped at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0xc000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L45x_L46x - // RM0394 (updated version of RM0392?) - .chip_id = STLINK_CHIPID_STM32_L45x_L46x, - .dev_type = "L45x/46x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 45.2, page 1463) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 73; also appears in sec 3.3.1 - // and tables 7 on pages 73-74) - // SRAM1 is 128k at 0x20000000; - // SRAM2 is 32k mapped at 0x10000000 (sec 2.4.2, table 3-4, - // page 68, also fig 2 on page 63) - .sram_size = 0x20000, - .bootrom_base = 0x1fff0000, // Tables 6, pages 71-72 (Bank 1 system - // memory, also fig 2 on page 63) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L47x/L48x - // RM0351 - .chip_id = STLINK_CHIPID_STM32_L4, - .dev_type = "L47x/L48x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1FFF75e0, // "Flash size data register" (sec 45.2, page 1671) - .flash_pagesize = 0x800, // 2k (sec 3.2, page 78; also appears in sec 3.3.1 - // and tables 4-6 on pages 79-81) - // SRAM1 is "up to" 96k in the standard Cortex-M memory map; - // SRAM2 is 32k mapped at at 0x10000000 (sec 2.3, page 73 for - // sizes; table 2, page 74 for SRAM2 location) - .sram_size = 0x18000, - .bootrom_base = 0x1fff0000, // Tables 4-6, pages 80-81 (Bank 1 system memory) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STLINK_CHIPID_STM32_L496x_L4A6x - // RM0351 (rev 5) - .chip_id = STLINK_CHIPID_STM32_L496x_L4A6x, - .dev_type = "L496x/L4A6x", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 49.2, page 1809) - .flash_pagesize = 0x800, // Page erase (2 Kbyte) (sec 3.2, page 93) - // SRAM1 is 256k at 0x20000000 - // SRAM2 is 64k at 0x20040000 (sec 2.2.1, fig 2, page 74) - .sram_size = 0x40000, // Embedded SRAM (sec 2.4, page 84) - .bootrom_base = 0x1fff0000, // System Memory (Bank 1) (sec 3.3.1) - .bootrom_size = 0x7000, // 28k (per bank), same source as base - .option_base = STM32_L4_OPTION_BYTES_BASE, - .option_size = 4, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L4PX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4PX, - .dev_type = "L4Px", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32L4RX - // RM0432 - .chip_id = STLINK_CHIPID_STM32_L4Rx, - .dev_type = "L4Rx", - .flash_type = STLINK_FLASH_TYPE_L4, - .flash_size_reg = 0x1fff75e0, // "Flash size data register" (sec 58.2, page 2274) - .flash_pagesize = 0x1000, // 4k, section 3.3, pg 117-120 - // TODO: flash_pagesize can be 8k depend on the dual-bank mode and flash size - .sram_size = 0xa0000, // 192k (SRAM1) + 64k SRAM2 + 384k SRAM3 = 640k, or 0xA0000 - .bootrom_base = 0x1fff0000, // 3.3.1, pg 117 - .bootrom_size = 0x7000, // 28k (per bank), same source as base (pg 117) - .flags = CHIP_F_HAS_DUAL_BANK | CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32WB55xx, STM32WB35xx, STM32WB50CG/30CE - // RM0434, RM0471 - .chip_id = STLINK_CHIPID_STM32_WB55, - .dev_type = "WB5x/3x", - .flash_type = STLINK_FLASH_TYPE_WB, - .flash_size_reg = 0x1FFF75E0, - .flash_pagesize = 0x1000, // 4k - .sram_size = 0x40000, - .bootrom_base = 0x1fff0000, // see the memory map - .bootrom_size = 0x7000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // STM32WLEx - .chip_id = STLINK_CHIPID_STM32_WLE, - .dev_type = "WLEx", - .flash_type = STLINK_FLASH_TYPE_WB, - .flash_size_reg = 0x1FFF75E0, - .flash_pagesize = 0x800, // 2k - .sram_size = 0x10000, - .bootrom_base = 0x1fff0000, // see the memory map - .bootrom_size = 0x7000, - .flags = CHIP_F_HAS_SWO_TRACING, - }, - { - // unknown - .chip_id = STLINK_CHIPID_UNKNOWN, - .dev_type = "unknown device", - .flash_type = STLINK_FLASH_TYPE_UNKNOWN, - .flash_size_reg = 0x0, - .flash_pagesize = 0x0, - .sram_size = 0x0, - .bootrom_base = 0x0, - .bootrom_size = 0x0, - }, -//}; \ No newline at end of file diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 6b318dc46..1796c388c 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -234,43 +234,43 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STLINK_CHIPID_STM32_L1_MD || - sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2 || - sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS || - sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS_HD || - sl->chip_id == STLINK_CHIPID_STM32_L152_RE || - sl->chip_id == STLINK_CHIPID_STM32_L011 || - sl->chip_id == STLINK_CHIPID_STM32_L0 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2) { + if (sl->chip_id == STM32_CHIPID_STM32_L1_MD || + sl->chip_id == STM32_CHIPID_STM32_L1_CAT2 || + sl->chip_id == STM32_CHIPID_STM32_L1_MD_PLUS || + sl->chip_id == STM32_CHIPID_STM32_L1_MD_PLUS_HD || + sl->chip_id == STM32_CHIPID_STM32_L152_RE || + sl->chip_id == STM32_CHIPID_STM32_L011 || + sl->chip_id == STM32_CHIPID_STM32_L0 || + sl->chip_id == STM32_CHIPID_STM32_L0_CAT5 || + sl->chip_id == STM32_CHIPID_STM32_L0_CAT2) { loader_code = loader_code_stm32lx; loader_size = sizeof(loader_code_stm32lx); } else if (sl->core_id == STM32VL_CORE_ID || - sl->chip_id == STLINK_CHIPID_STM32_F1_MD || - sl->chip_id == STLINK_CHIPID_STM32_F1_HD || - sl->chip_id == STLINK_CHIPID_STM32_F1_LD || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_HD || - sl->chip_id == STLINK_CHIPID_STM32_F1_XLD || - sl->chip_id == STLINK_CHIPID_STM32_F1_CONN || - sl->chip_id == STLINK_CHIPID_STM32_F3 || - sl->chip_id == STLINK_CHIPID_STM32_F3xx_SMALL || - sl->chip_id == STLINK_CHIPID_STM32_F303_HD || - sl->chip_id == STLINK_CHIPID_STM32_F37x || - sl->chip_id == STLINK_CHIPID_STM32_F334) { + sl->chip_id == STM32_CHIPID_STM32_F1_MD || + sl->chip_id == STM32_CHIPID_STM32_F1_HD || + sl->chip_id == STM32_CHIPID_STM32_F1_LD || + sl->chip_id == STM32_CHIPID_STM32_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_STM32_F1_VL_HD || + sl->chip_id == STM32_CHIPID_STM32_F1_XLD || + sl->chip_id == STM32_CHIPID_STM32_F1_CONN || + sl->chip_id == STM32_CHIPID_STM32_F3 || + sl->chip_id == STM32_CHIPID_STM32_F3xx_SMALL || + sl->chip_id == STM32_CHIPID_STM32_F303_HD || + sl->chip_id == STM32_CHIPID_STM32_F37x || + sl->chip_id == STM32_CHIPID_STM32_F334) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F2 || - sl->chip_id == STLINK_CHIPID_STM32_F4 || - sl->chip_id == STLINK_CHIPID_STM32_F4_DE || - sl->chip_id == STLINK_CHIPID_STM32_F4_LP || - sl->chip_id == STLINK_CHIPID_STM32_F4_HD || - sl->chip_id == STLINK_CHIPID_STM32_F4_DSI || - sl->chip_id == STLINK_CHIPID_STM32_F410 || - sl->chip_id == STLINK_CHIPID_STM32_F411xx || - sl->chip_id == STLINK_CHIPID_STM32_F412 || - sl->chip_id == STLINK_CHIPID_STM32_F413 || - sl->chip_id == STLINK_CHIPID_STM32_F446) { + } else if (sl->chip_id == STM32_CHIPID_STM32_F2 || + sl->chip_id == STM32_CHIPID_STM32_F4 || + sl->chip_id == STM32_CHIPID_STM32_F4_DE || + sl->chip_id == STM32_CHIPID_STM32_F4_LP || + sl->chip_id == STM32_CHIPID_STM32_F4_HD || + sl->chip_id == STM32_CHIPID_STM32_F4_DSI || + sl->chip_id == STM32_CHIPID_STM32_F410 || + sl->chip_id == STM32_CHIPID_STM32_F411xx || + sl->chip_id == STM32_CHIPID_STM32_F412 || + sl->chip_id == STM32_CHIPID_STM32_F413 || + sl->chip_id == STM32_CHIPID_STM32_F446) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, @@ -279,9 +279,9 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* if (retval == -1) { return(retval); } } else if (sl->core_id == STM32F7_CORE_ID || - sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx || - sl->chip_id == STLINK_CHIPID_STM32_F72xxx) { + sl->chip_id == STM32_CHIPID_STM32_F7 || + sl->chip_id == STM32_CHIPID_STM32_F76xxx || + sl->chip_id == STM32_CHIPID_STM32_F72xxx) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, @@ -289,19 +289,19 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code_stm32f7_lv, sizeof(loader_code_stm32f7_lv)); if (retval == -1) { return(retval); } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F0 || - sl->chip_id == STLINK_CHIPID_STM32_F04 || - sl->chip_id == STLINK_CHIPID_STM32_F0_CAN || - sl->chip_id == STLINK_CHIPID_STM32_F0xx_SMALL || - sl->chip_id == STLINK_CHIPID_STM32_F09x) { + } else if (sl->chip_id == STM32_CHIPID_STM32_F0 || + sl->chip_id == STM32_CHIPID_STM32_F04 || + sl->chip_id == STM32_CHIPID_STM32_F0_CAN || + sl->chip_id == STM32_CHIPID_STM32_F0xx_SMALL || + sl->chip_id == STM32_CHIPID_STM32_F09x) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); - } else if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L41x_L42x) || - (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || - (sl->chip_id == STLINK_CHIPID_STM32_L4Rx) || - (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x)) { + } else if ((sl->chip_id == STM32_CHIPID_STM32_L4) || + (sl->chip_id == STM32_CHIPID_STM32_L41x_L42x) || + (sl->chip_id == STM32_CHIPID_STM32_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_STM32_L45x_L46x) || + (sl->chip_id == STM32_CHIPID_STM32_L4Rx) || + (sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x)) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { From d3bf1453fd8c2f57faaa91bec01f24f0b00af347 Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Mon, 10 Jan 2022 09:49:41 +1300 Subject: [PATCH 1276/1435] Get each page size before erasing --- src/common.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/src/common.c b/src/common.c index fb5e431fa..de22ad851 100644 --- a/src/common.c +++ b/src/common.c @@ -2952,24 +2952,25 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size) { - // erase each page - int i = 0, num_pages = (int)(size / sl->flash_pgsz); - for (i = 0; i < num_pages; i++) { - // addr must be an addr inside the page - stm32_addr_t addr = - (stm32_addr_t)base_addr + i * (stm32_addr_t)sl->flash_pgsz; - - if (stlink_erase_flash_page(sl, addr)) { - WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); - return (-1); - } + stm32_addr_t addr = (stm32_addr_t)base_addr; - fprintf(stdout, "-> Flash page at %5d/%5d erased\n", i, num_pages); - fflush(stdout); + do { + size_t page_size = stlink_calculate_pagesize(sl, addr); + + if (stlink_erase_flash_page(sl, addr)) { + WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); + return (-1); } - fprintf(stdout, "\n"); - return 0; + fprintf(stdout, "-> Flash page at %#x erased (size: %#lx)\n", addr, page_size); + fflush(stdout); + + // check the next page is within the range to erase + addr += page_size; + } while (addr < (base_addr + size)); + + fprintf(stdout, "\n"); + return 0; } int stlink_erase_flash_mass(stlink_t *sl) { From 8a1535e2d2589a6594026b07ee3f4490533de692 Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Mon, 10 Jan 2022 10:26:14 +1300 Subject: [PATCH 1277/1435] Check parameters validity --- src/common.c | 5 +++++ src/st-flash/flash.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index de22ad851..ec44f2f9c 100644 --- a/src/common.c +++ b/src/common.c @@ -2952,6 +2952,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size) { + if (base_addr < sl->flash_base || (base_addr + size) > (sl->flash_base + sl->flash_size)) { + ELOG("Invalid address or flash size\n"); + return (-1); + } + stm32_addr_t addr = (stm32_addr_t)base_addr; do { diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index b4b596cfc..b1cdd02b7 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -168,7 +168,7 @@ int main(int ac, char** av) { goto on_error; } } else if (o.cmd == FLASH_CMD_ERASE) { - if (o.size != 0 && o.addr >= sl->flash_base && (o.addr + o.size) <= (sl->flash_base + sl->flash_size)) + if (o.size > 0 && o.addr > 0) err = stlink_erase_flash_section(sl, o.addr, o.size); else err = stlink_erase_flash_mass(sl); From f277fdb67750033716101ec0d0c48add46c5e075 Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Mon, 10 Jan 2022 12:51:44 +1300 Subject: [PATCH 1278/1435] Make sure address and size are each aligned with a page --- src/common.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index ec44f2f9c..a5d008abd 100644 --- a/src/common.c +++ b/src/common.c @@ -2957,11 +2957,26 @@ int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size return (-1); } - stm32_addr_t addr = (stm32_addr_t)base_addr; + stm32_addr_t addr = sl->flash_base; + + // Make sure the requested address is aligned with the beginning of a page + while (addr < base_addr) { + addr += stlink_calculate_pagesize(sl, addr); + } + if (addr != base_addr) { + ELOG("The address to erase is not aligned with the beginning of a page\n"); + return -1; + } do { size_t page_size = stlink_calculate_pagesize(sl, addr); + // Check if we are going further than the requested size + if ((addr + page_size) > (base_addr + size)) { + ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); + return -1; + } + if (stlink_erase_flash_page(sl, addr)) { WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); return (-1); From 1e7d89fc1323f26cd566e059639448e21d66e638 Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Mon, 10 Jan 2022 20:24:29 +0400 Subject: [PATCH 1279/1435] Removing env. var. STLINK_DEVICE from docs In #1210 from codebase was removed functionality to specify ST-LINK by environment variable. This still mentioned in documentation, so I updated it. --- doc/man/st-flash.md | 5 ++--- doc/man/st-info.md | 3 --- doc/man/st-util.1 | 2 -- doc/man/st-util.md | 3 +-- doc/tutorial.md | 3 +-- 5 files changed, 4 insertions(+), 12 deletions(-) diff --git a/doc/man/st-flash.md b/doc/man/st-flash.md index 80130c8f1..9b2cfcad5 100644 --- a/doc/man/st-flash.md +++ b/doc/man/st-flash.md @@ -20,8 +20,7 @@ You can use this instead of st-util(1) if you prefer, but remember to use the Use hexadecimal format for the *ADDR* and *SIZE*. -The STLink device to use can be specified using the --serial parameter, or via -the environment variable STLINK_DEVICE on the format :. +The STLink device to use can be specified using the --serial parameter. # COMMANDS @@ -52,7 +51,7 @@ reset : Enable ignore ending empty bytes optimization \--serial *iSerial* -: TODO +: Serial number of ST-LINK device to use \--flash=fsize : Where fsize is the size in decimal, octal, or hex followed by an optional multiplier diff --git a/doc/man/st-info.md b/doc/man/st-info.md index 91f9ea0b0..2cca61f83 100644 --- a/doc/man/st-info.md +++ b/doc/man/st-info.md @@ -15,9 +15,6 @@ st-info - Provides information about connected STLink and STM32 devices Provides information about connected STLink programmers and STM32 devices: Serial code, flash, page size, sram, chipid, description. -The STLink device to probe can be specified via the environment variable -STLINK_DEVICE on the format :. - # OPTIONS \--version diff --git a/doc/man/st-util.1 b/doc/man/st-util.1 index 9b46b4d65..2f718bb2b 100644 --- a/doc/man/st-util.1 +++ b/doc/man/st-util.1 @@ -19,8 +19,6 @@ option, the default \f[B]4242\f[R] port will be used. Stlink version 2 is used by default unless the option \f[B]\[en]stlinkv1\f[R] is given. .PP -The STLinkV2 device to use can be specified in the environment variable -STLINK_DEVICE on the format :. .SH OPTIONS .TP .B \-h, \-\-help diff --git a/doc/man/st-util.md b/doc/man/st-util.md index 9a54fb309..62f850203 100644 --- a/doc/man/st-util.md +++ b/doc/man/st-util.md @@ -17,8 +17,7 @@ Run the main binary of the local package (src/main.rs). If a port number is not specified using the **--listen_port** option, the default **4242** port will be used. -The STLink device to use can be specified using the --serial parameter, or via -the environment variable STLINK_DEVICE on the format :. +The STLink device to use can be specified using the --serial parameter. # OPTIONS diff --git a/doc/tutorial.md b/doc/tutorial.md index 955f85611..685325c37 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -244,8 +244,7 @@ There are a few options: Do not reset board on connection. ``` -The STLink device to use can be specified using the --serial parameter, or via -the environment variable STLINK_DEVICE on the format :. +The STLink device to use can be specified using the --serial parameter. Then, in your project directory, someting like this... (remember, you need to run an _ARM_ gdb, not an x86 gdb) From 77b3319fc91120cc7d053e14363c41eb123c8fa3 Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Thu, 13 Jan 2022 09:12:39 +1300 Subject: [PATCH 1280/1435] Use stlink_erase_flash_section in stlink_write_flash --- src/common.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/src/common.c b/src/common.c index a5d008abd..af2222c5b 100644 --- a/src/common.c +++ b/src/common.c @@ -3491,7 +3491,6 @@ int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint8_t eraseonly) { - size_t off; int ret; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, @@ -3525,23 +3524,8 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, // make sure we've loaded the context with the chip details stlink_core_id(sl); - // Erase each page - int page_count = 0; - - for (off = 0; off < len; - off += stlink_calculate_pagesize(sl, addr + (uint32_t)off)) { - // addr must be an addr inside the page - if (stlink_erase_flash_page(sl, addr + (uint32_t)off) == -1) { - ELOG("Failed to erase_flash_page(%#x) == -1\n", (unsigned)(addr + off)); - return (-1); - } - - ILOG("Flash page at addr: 0x%08lx erased\n", (unsigned long)(addr + off)); - page_count++; - } - - ILOG("Finished erasing %d pages of %u (%#x) bytes\n", page_count, - (unsigned)(sl->flash_pgsz), (unsigned)(sl->flash_pgsz)); + // Erase this section of the flash + stlink_erase_flash_section(sl, addr, len); if (eraseonly) { return (0); From a2a04dd1b79b5f8c00002d4a914dc3a82f04ea82 Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Thu, 13 Jan 2022 09:22:14 +1300 Subject: [PATCH 1281/1435] Update log --- src/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/common.c b/src/common.c index af2222c5b..4e276d23b 100644 --- a/src/common.c +++ b/src/common.c @@ -2953,7 +2953,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size) { if (base_addr < sl->flash_base || (base_addr + size) > (sl->flash_base + sl->flash_size)) { - ELOG("Invalid address or flash size\n"); + ELOG("Invalid address or size\n"); return (-1); } From 8667990506da8642344adb5da7f1b76c9d6cbfec Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Thu, 13 Jan 2022 11:41:14 +1300 Subject: [PATCH 1282/1435] Allow to completely erase a page when size is not aligned --- inc/stlink.h | 2 +- src/common.c | 13 ++++++++----- src/st-flash/flash.c | 2 +- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 852e95e42..083b3466c 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -274,7 +274,7 @@ int stlink_trace_enable(stlink_t* sl, uint32_t frequency); int stlink_trace_disable(stlink_t* sl); int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); int stlink_erase_flash_mass(stlink_t* sl); -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size); +int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size); int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); uint8_t stlink_get_erased_pattern(stlink_t *sl); diff --git a/src/common.c b/src/common.c index 4e276d23b..f72cad582 100644 --- a/src/common.c +++ b/src/common.c @@ -2951,7 +2951,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { return check_flash_error(sl); } -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size) { +int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { if (base_addr < sl->flash_base || (base_addr + size) > (sl->flash_base + sl->flash_size)) { ELOG("Invalid address or size\n"); return (-1); @@ -2971,8 +2971,8 @@ int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size do { size_t page_size = stlink_calculate_pagesize(sl, addr); - // Check if we are going further than the requested size - if ((addr + page_size) > (base_addr + size)) { + // Check if size is aligned with a page, unless we want to completely erase the last page + if ((addr + page_size) > (base_addr + size) && !align_size) { ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); return -1; } @@ -3000,7 +3000,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { if (sl->flash_type == STLINK_FLASH_TYPE_L0 || sl->flash_type == STLINK_FLASH_TYPE_WB) { - stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size); + err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); } else { wait_flash_busy(sl); @@ -3525,7 +3525,10 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, stlink_core_id(sl); // Erase this section of the flash - stlink_erase_flash_section(sl, addr, len); + if (stlink_erase_flash_section(sl, addr, len, true) < 0) { + ELOG("Failed to erase the flash prior to writing\n"); + return (-1); + } if (eraseonly) { return (0); diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index b1cdd02b7..6ac2ba48b 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -169,7 +169,7 @@ int main(int ac, char** av) { } } else if (o.cmd == FLASH_CMD_ERASE) { if (o.size > 0 && o.addr > 0) - err = stlink_erase_flash_section(sl, o.addr, o.size); + err = stlink_erase_flash_section(sl, o.addr, o.size, false); else err = stlink_erase_flash_mass(sl); From 2c62079ed1d07c9236c08cc1f0e6cf118dd4fb4a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 14 Jan 2022 00:17:44 +0100 Subject: [PATCH 1283/1435] Removed stlink/v1 support for macOS 10.14 --- CHANGELOG.md | 2 +- README.md | 2 +- doc/version_support.md | 2 +- stlinkv1_macos_driver/install.sh | 3 - .../Contents/Info.plist | 82 ------------- .../Contents/MacOS/stlink_shield_10_14 | Bin 33840 -> 0 bytes .../stlink_shield_10_14.kext/Contents/PkgInfo | 1 - .../Contents/_CodeSignature/CodeResources | 115 ------------------ .../stlink_shield.xcodeproj/project.pbxproj | 50 -------- 9 files changed, 3 insertions(+), 254 deletions(-) delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/MacOS/stlink_shield_10_14 delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/PkgInfo delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/_CodeSignature/CodeResources diff --git a/CHANGELOG.md b/CHANGELOG.md index 06f995d21..039ca7848 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,7 +2,7 @@ # v1.7.1 -Release date: 2021-xx-xx +Release date: 2022-xx-xx This release drops support for some older operating systems. Check project README for details. Updated system requirements: Raised minimum version for `cmake` to 3.7.2. diff --git a/README.md b/README.md index 7f797a7d9..bc491189e 100644 --- a/README.md +++ b/README.md @@ -38,7 +38,7 @@ It supports several so called STLINK programmer boards (and clones thereof) whic - stand-alone programmer (STLINK-V3SET, STLINK-V3MINI, STLINK-V3MODS) - on-board on some STM32 Nucleo boards (STLINK-V3E) -_\*)_ **Note: Support for the STLINK/V1 on macOS is limited to 10.14 - 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.** +_\*)_ *Note: Support for the STLINK/V1 on macOS is limited to 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.* On the user level there is no difference in handling or operation between these different revisions. diff --git a/doc/version_support.md b/doc/version_support.md index 2c5df7461..4eeb5074a 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -17,7 +17,7 @@ Up on compiling c-make will **automatically** download and install the latest co | homebrew | 1.0.24 | 3.20.2 | 3.24.29
      gtk+3 | 10.9 - 11.x | | MacPorts | 1.0.24 | 3.20.2 | 3.24.29
      gtk3 | 10.4 - 11.x | -NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 are required. +NOTE: In order to use a STLINK/V1 programmer on macOS, version 10.15 is required. ### Linux-/Unix-based: diff --git a/stlinkv1_macos_driver/install.sh b/stlinkv1_macos_driver/install.sh index 5716281a1..f9878bd46 100644 --- a/stlinkv1_macos_driver/install.sh +++ b/stlinkv1_macos_driver/install.sh @@ -2,9 +2,6 @@ ISMACOS=$(sw_vers -productVersion) case $ISMACOS in -10.14*) - KEXT="stlink_shield_10_14.kext" - ;; 10.15*) KEXT="stlink_shield_10_15.kext" ;; diff --git a/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist b/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist deleted file mode 100644 index fd424ea93..000000000 --- a/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist +++ /dev/null @@ -1,82 +0,0 @@ - - - - - BuildMachineOSBuild - 18G7016 - CFBundleDevelopmentRegion - English - CFBundleIdentifier - com.libusb.stlink-shield - CFBundleInfoDictionaryVersion - 6.0 - CFBundlePackageType - KEXT - CFBundleSignature - ???? - CFBundleSupportedPlatforms - - MacOSX - - CFBundleVersion - 1.0.0 - DTCompiler - com.apple.compilers.llvm.clang.1_0 - DTPlatformBuild - 11C504 - DTPlatformVersion - GM - DTSDKBuild - 19B90 - DTSDKName - macosx10.15 - DTXcode - 1130 - DTXcodeBuild - 11C504 - IOKitPersonalities - - DeviceDriver - - CFBundleIdentifier - com.apple.kpi.iokit - IOClass - IOService - IOProviderClass - IOUSBDevice - bcdDevice - 256 - idProduct - 14148 - idVendor - 1155 - - InterfaceDriver - - CFBundleIdentifier - com.apple.kpi.iokit - IOClass - IOService - IOProviderClass - IOUSBInterface - bConfigurationValue - 1 - bInterfaceNumber - 0 - idProduct - 14148 - idVendor - 1155 - - - LSMinimumSystemVersion - 10.14 - OSBundleLibraries - - com.apple.iokit.IOUSBFamily - 1.8 - com.apple.kpi.libkern - 11.2.0 - - - diff --git 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10 - - ^embedded\.provisionprofile$ - - weight - 20 - - ^version\.plist$ - - weight - 20 - - - - diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj index 4f2b80254..373600c64 100644 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj +++ b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj @@ -8,7 +8,6 @@ /* Begin PBXFileReference section */ 8CD33C31149BB80D0033D618 /* Info.plist */ = {isa = PBXFileReference; lastKnownFileType = text.plist.xml; path = Info.plist; sourceTree = ""; }; - 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = stlink_shield_10_14.kext; sourceTree = BUILT_PRODUCTS_DIR; }; 8F90850924786F39009109AD /* stlink_shield_10_15.kext */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = stlink_shield_10_15.kext; sourceTree = BUILT_PRODUCTS_DIR; }; /* End PBXFileReference section */ @@ -34,7 +33,6 @@ 19C28FB6FE9D52B211CA2CBB /* Products */ = { isa = PBXGroup; children = ( - 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */, 8F90850924786F39009109AD /* stlink_shield_10_15.kext */, ); name = Products; @@ -60,26 +58,6 @@ /* End PBXHeadersBuildPhase section */ /* Begin PBXNativeTarget section */ - 8F9084F324786F0F009109AD /* stlink_shield_10_14 */ = { - isa = PBXNativeTarget; - buildConfigurationList = 8F9084FA24786F0F009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_14" */; - buildPhases = ( - 8F9084F424786F0F009109AD /* ShellScript */, - 8F9084F524786F0F009109AD /* Headers */, - 8F9084F624786F0F009109AD /* Resources */, - 8F9084F824786F0F009109AD /* Sources */, - 8F9084F924786F0F009109AD /* ShellScript */, - ); - buildRules = ( - ); - dependencies = ( - ); - name = stlink_shield_10_14; - productInstallPath = "$(SYSTEM_LIBRARY_DIR)/Extensions"; - productName = NanosMouse; - productReference = 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */; - productType = "com.apple.product-type.kernel-extension.iokit"; - }; 8F9084FF24786F39009109AD /* stlink_shield_10_15 */ = { isa = PBXNativeTarget; buildConfigurationList = 8F90850624786F39009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_15" */; @@ -120,7 +98,6 @@ projectDirPath = ""; projectRoot = ""; targets = ( - 8F9084F324786F0F009109AD /* stlink_shield_10_14 */, 8F9084FF24786F39009109AD /* stlink_shield_10_15 */, ); }; @@ -458,24 +435,6 @@ }; name = Release; }; - 8F9084FB24786F0F009109AD /* Debug */ = { - isa = XCBuildConfiguration; - buildSettings = { - CODE_SIGN_IDENTITY = "-"; - MACOSX_DEPLOYMENT_TARGET = 10.14; - PRODUCT_NAME = "$(TARGET_NAME)"; - }; - name = Debug; - }; - 8F9084FC24786F0F009109AD /* Release */ = { - isa = XCBuildConfiguration; - buildSettings = { - CODE_SIGN_IDENTITY = "-"; - MACOSX_DEPLOYMENT_TARGET = 10.14; - PRODUCT_NAME = "$(TARGET_NAME)"; - }; - name = Release; - }; 8F90850724786F39009109AD /* Debug */ = { isa = XCBuildConfiguration; buildSettings = { @@ -506,15 +465,6 @@ defaultConfigurationIsVisible = 0; defaultConfigurationName = Release; }; - 8F9084FA24786F0F009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_14" */ = { - isa = XCConfigurationList; - buildConfigurations = ( - 8F9084FB24786F0F009109AD /* Debug */, - 8F9084FC24786F0F009109AD /* Release */, - ); - defaultConfigurationIsVisible = 0; - defaultConfigurationName = Release; - }; 8F90850624786F39009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_15" */ = { isa = XCConfigurationList; buildConfigurations = ( From 74957efc9dafb3569c4ef4d0ab9d9007d7989af4 Mon Sep 17 00:00:00 2001 From: Antoine Faure Date: Fri, 14 Jan 2022 14:50:35 +1300 Subject: [PATCH 1284/1435] Factorize address checks --- inc/stlink.h | 2 ++ src/common.c | 55 +++++++++++++++++++++++++++++++++------------------- 2 files changed, 37 insertions(+), 20 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 083b3466c..df13aa7c9 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -289,6 +289,8 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); +int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); +int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); uint16_t read_uint16(const unsigned char *c, const int pt); void stlink_core_stat(stlink_t *sl); void stlink_print_data(stlink_t *sl); diff --git a/src/common.c b/src/common.c index f72cad582..6cbd217ef 100644 --- a/src/common.c +++ b/src/common.c @@ -2951,23 +2951,47 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { return check_flash_error(sl); } -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { - if (base_addr < sl->flash_base || (base_addr + size) > (sl->flash_base + sl->flash_size)) { - ELOG("Invalid address or size\n"); +// Check if an address and size are within the flash +int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { + if (addr < sl->flash_base || addr >= (sl->flash_base + sl->flash_size)) { + ELOG("Invalid address, it should be within 0x%08x - 0x%08lx\n", sl->flash_base, (sl->flash_base + sl->flash_size -1)); + return (-1); + } + if ((addr + size) > (sl->flash_base + sl->flash_size)) { + ELOG("The size exceeds the size of the flash (0x%08lx bytes available)\n", (sl->flash_base + sl->flash_size - addr)); return (-1); } + return 0; +} - stm32_addr_t addr = sl->flash_base; +// Check if an address is aligned with the beginning of a page +int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { + stm32_addr_t page = sl->flash_base; - // Make sure the requested address is aligned with the beginning of a page - while (addr < base_addr) { - addr += stlink_calculate_pagesize(sl, addr); + while (page < addr) { + page += stlink_calculate_pagesize(sl, page); } - if (addr != base_addr) { + + if (page != addr) { + return -1; + } + + return 0; +} + +int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { + // Check the address and size validity + if (stlink_check_address_range_validity(sl, base_addr, size) < 0) { + return -1; + } + + // Make sure the requested address is aligned with the beginning of a page + if (stlink_check_address_alignment(sl, base_addr) < 0) { ELOG("The address to erase is not aligned with the beginning of a page\n"); return -1; } + stm32_addr_t addr = base_addr; do { size_t page_size = stlink_calculate_pagesize(sl, addr); @@ -3498,22 +3522,13 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, // check addr range is inside the flash stlink_calculate_pagesize(sl, addr); - if (addr < sl->flash_base) { - ELOG("addr too low %#x < %#x\n", addr, sl->flash_base); - return (-1); - } else if ((addr + len) < addr) { - ELOG("addr overruns\n"); - return (-1); - } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { - ELOG("addr too high\n"); - return (-1); - } else if (addr & 1) { - ELOG("unaligned addr 0x%x\n", addr); + // Check the address and size validity + if (stlink_check_address_range_validity(sl, addr, len) < 0) { return (-1); } else if (len & 1) { WLOG("unaligned len 0x%x -- padding with zero\n", len); len += 1; - } else if (addr & (sl->flash_pgsz - 1)) { + } else if (stlink_check_address_alignment(sl, addr) < 0) { ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " "check page start address and compare with flash module organisation " "in related ST reference manual of your device.\n", From c854df5edd1285c1016e6181bcd54acf6f2e0bcd Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 15 Jan 2022 01:58:42 +0100 Subject: [PATCH 1285/1435] Updated MCU core-ids --- doc/devices_boards.md | 30 +++++++++++++++--------------- inc/stm32.h | 33 +++++++++++++++++++++------------ src/common.c | 2 +- src/st-util/gdb-server.c | 2 +- src/stlink-lib/flash_loader.c | 4 ++-- 5 files changed, 40 insertions(+), 31 deletions(-) diff --git a/doc/devices_boards.md b/doc/devices_boards.md index a8a366448..63569881a 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -2,7 +2,7 @@ The following devices are supported by the stlink toolset. -## STM32F0 / ARM Cortex M0 / Core-ID: 0x0bb11477 (STM32F0_CORE_ID) +## STM32F0 / ARM Cortex M0 | Chip-ID | Product-Code | | ------- | ------------------- | @@ -19,7 +19,7 @@ The following devices are supported by the stlink toolset. | 0x442 | STM32F0**9**xxx | -## STM32F1 / ARM Cortex M3 / Core-ID: 0x1ba01477 (STM32F1_CORE_ID) +## STM32F1 / ARM Cortex M3 | Product-Code | Product Line | | ----------------- | ----------------------- | @@ -45,20 +45,20 @@ Tested non-official ST boards [incl. STLINK programmers]: - HY-STM32 (STM32F103VETx) [v1, v2] - DecaWave EVB1000 (STM32F105RCTx) [v1, v2] -## STM32F2 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F2_CORE_ID) +## STM32F2 / ARM Cortex M3 | Chip-ID | Product-Code | Product Line | | ------- | ------------ | ------------- | | 0x411 | STM32F2yyxx | (all devices) | -## STM32F1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32F1c_CORE_ID) +## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) | Product-Code | Chip-ID | STLink
      Programmer | Boards | | ------------- | ------- | ---------------------- | ----------------------------------------------------------------------------------------------- | | CKS32F103C8Tx | 0x410 | v2 | "STM32"-Bluepill ( _**Fake-Marking !**_ )
      STM32F103C8T6 clone from China Key Systems (CKS) | | CKS32F103C8Tx | 0x410 | v2 | CKS32-Bluepill (Clone)
      STM32F103C8T6 clone from China Key Systems (CKS) | -## STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3_CORE_ID) +## STM32F3 / ARM Cortex M4F | Product-Code | Product Line | | ----------------- | ------------------------------------------------------------- | @@ -85,13 +85,13 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x446 | _N/A_ | xD xE | | F302 | F303 | | | 0x446 | _N/A_ | - | | | | F398 | -## STM32F3 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F3c_CORE_ID) +## STM32F3 Clone / ARM Cortex M4F (Core-ID: 0x2ba01477) | Product-Code | Chip-ID | STLINK
      Programmer | Boards | | ------------ | ------- | ---------------------- | ---------------------------------- | | GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | -## STM32F4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32F4_CORE_ID) +## STM32F4 / ARM Cortex M4F | Chip-ID | Product-Code | | ------- | ------------------- | @@ -112,7 +112,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x463 | STM32F4**13**xx | | 0x463 | STM32F4**23**xx | -## STM32F7 / ARM Cortex M7F / Core-ID: 0x5ba02477 (STM32F7_CORE_ID) +## STM32F7 / ARM Cortex M7F | Chip-ID | Product-Code | | ------- | --------------- | @@ -123,7 +123,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x451 | STM32F7**6**xxx | | 0x451 | STM32F7**7**xxx | -## STM32H7 / ARM Cortex M7F / Core-ID: 0x6ba02477 (STM32H7_CORE_ID) +## STM32H7 / ARM Cortex M7F | Chip-ID | Product-Code | | ------- | ------------- | @@ -132,7 +132,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x480 | STM32H7**A**x | | 0x480 | STM32H7**B**x | -## STM32G0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32G0_CORE_ID) +## STM32G0 / ARM Cortex M0+ | Chip-ID | Product-Code | | ------- | --------------- | @@ -141,7 +141,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x460 | STM32G0**7**xxx | | 0x460 | STM32G0**8**xxx | -## STM32G4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32G4_CORE_ID) +## STM32G4 / ARM Cortex M4F | Chip-ID | Product-Code | | ------- | --------------- | @@ -151,7 +151,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x469 | STM32G4**8**xxx | | 0x479 | STM32G4**91**xx | -## STM32L0 / ARM Cortex M0+ / Core-ID: 0x0bc11477 (STM32L0_CORE_ID) +## STM32L0 / ARM Cortex M0+ | Chip-ID | Product-Code | | ------- | --------------- | @@ -164,7 +164,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x447 | STM32L0**7**xxx | | 0x447 | STM32L0**8**xxx | -## STM32L1 / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32L1_CORE_ID) +## STM32L1 / ARM Cortex M3 | Chip-ID | Product-Code | | ------- | ---------------- | @@ -178,7 +178,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x436 | STM32L1xxx**D** | | 0x437 | STM32L1xxx**E** | -## STM32L4 / ARM Cortex M4F / Core-ID: 0x2ba01477 (STM32L4_CORE_ID) +## STM32L4 / ARM Cortex M4F | Chip-ID | Product-Code | | ------- | --------------- | @@ -197,7 +197,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x471 | STM32L4**P5**xx | | 0x471 | STM32L4**Q5**xx | -## STM32W / ARM Cortex M3 / Core-ID: 0x2ba01477 (STM32W_CORE_ID) +## STM32W / ARM Cortex M3 | Chip-ID | Product-Code | | ------- | --------------- | diff --git a/inc/stm32.h b/inc/stm32.h index 8dff2a7d7..d6faff12e 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -7,11 +7,20 @@ #ifndef STM32_H #define STM32_H -/* Cortex-M core ids */ -#define STM32VL_CORE_ID 0x1ba01477 -#define STM32F7_CORE_ID 0x5ba02477 -#define STM32H7_CORE_ID 0x6ba02477 // STM32H7 SWD ID Code -#define STM32H7_CORE_ID_JTAG 0x6ba00477 // STM32H7 JTAG ID Code (RM0433 p.3065) +/* Cortex-M core ids (CPUTAPID) */ +#define STM32_CORE_ID_M3_F2_JTAG 0x0ba00477 // unused // F2 JTAG (RM0033 p.1326) +//#define STM32_CORE_ID_M33_JTAG 0x0ba04477 // unused // L5 JTAG +#define STM32_CORE_ID_M0 0x0bb11477 // unused // F0 +#define STM32_CORE_ID_M0P 0x0bc11477 // unused // L0, G0 +#define STM32_CORE_ID_M33 0x0be01477 // unused // L5 SWD (RM0351 p.2029) +#define STM32_CORE_ID_M33_JTAG 0x0be02477 // unused // L5 JTAG (RM0438 p.2029) +#define STM32_CORE_ID_M3_F1 0x1ba01477 // F1 (RM0008 p.1092) +#define STM32_CORE_ID_M4F_L4 0x1ba01477 // unused // L4 (RM0351 p.1845) +#define STM32_CORE_ID_M4F_F4 0x2ba01477 // unused // F4 (RM0090 p.1695) +#define STM32_CORE_ID_M4F_F4_JTAG 0x4ba00477 // unused // F4 JTAG (RM090 p.1691) +#define STM32_CORE_ID_M7_F7 0x5ba02477 // F7 +#define STM32_CORE_ID_M7_H7 0x6ba02477 // H7 +#define STM32_CORE_ID_M7_H7_JTAG 0x6ba00477 // H7 JTAG (RM0433 p.3065) /* STM32 flash types */ // New flash type definitions must go before STM32_FLASH_TYPE_UNDEFINED @@ -22,13 +31,13 @@ enum stm32_flash_type { STM32_FLASH_TYPE_F1_XL = 2, STM32_FLASH_TYPE_F2_F4 = 3, STM32_FLASH_TYPE_F7 = 4, - STM32_FLASH_TYPE_G0 = 5, // 7 - STM32_FLASH_TYPE_G4 = 6, // 8 - STM32_FLASH_TYPE_H7 = 7, // 10 - STM32_FLASH_TYPE_L0_L1 = 8, // 5 - STM32_FLASH_TYPE_L4_L4P = 9, // 6 - STM32_FLASH_TYPE_L5_U5 = 10, // new - STM32_FLASH_TYPE_WB_WL = 11, // 9 + STM32_FLASH_TYPE_G0 = 5, + STM32_FLASH_TYPE_G4 = 6, + STM32_FLASH_TYPE_H7 = 7, + STM32_FLASH_TYPE_L0_L1 = 8, + STM32_FLASH_TYPE_L4_L4P = 9, + STM32_FLASH_TYPE_L5_U5 = 10, + STM32_FLASH_TYPE_WB_WL = 11, STM32_FLASH_TYPE_UNDEFINED = 12, // max. value exceeded }; diff --git a/src/common.c b/src/common.c index 5a6d0d86b..5a9c43c96 100644 --- a/src/common.c +++ b/src/common.c @@ -1514,7 +1514,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * */ - if ((sl->core_id == STM32H7_CORE_ID || sl->core_id == STM32H7_CORE_ID_JTAG) && + if ((sl->core_id == STM32_CORE_ID_M7_H7 || sl->core_id == STM32_CORE_ID_M7_H7_JTAG) && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 4babef0cc..19819a6cb 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -559,7 +559,7 @@ char* make_memory_map(stlink_t *sl) { strcpy(map, memory_map_template_F4); } else if (sl->chip_id == STM32_CHIPID_STM32_F4_DE) { strcpy(map, memory_map_template_F4_DE); - } else if (sl->core_id == STM32F7_CORE_ID) { + } else if (sl->core_id == STM32_CORE_ID_M7_F7) { snprintf(map, sz, memory_map_template_F7, (unsigned int)sl->sram_size); } else if (sl->chip_id == STM32_CHIPID_STM32_H74xxx) { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 1796c388c..ad52d6567 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -245,7 +245,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STM32_CHIPID_STM32_L0_CAT2) { loader_code = loader_code_stm32lx; loader_size = sizeof(loader_code_stm32lx); - } else if (sl->core_id == STM32VL_CORE_ID || + } else if (sl->core_id == STM32_CORE_ID_M3_F1 || sl->chip_id == STM32_CHIPID_STM32_F1_MD || sl->chip_id == STM32_CHIPID_STM32_F1_HD || sl->chip_id == STM32_CHIPID_STM32_F1_LD || @@ -278,7 +278,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code_stm32f4_lv, sizeof(loader_code_stm32f4_lv)); if (retval == -1) { return(retval); } - } else if (sl->core_id == STM32F7_CORE_ID || + } else if (sl->core_id == STM32_CORE_ID_M7_F7 || sl->chip_id == STM32_CHIPID_STM32_F7 || sl->chip_id == STM32_CHIPID_STM32_F76xxx || sl->chip_id == STM32_CHIPID_STM32_F72xxx) { From 3be2c70a675e1cfec5d1a6c35621dcc1d1517566 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 16 Jan 2022 18:10:01 +0100 Subject: [PATCH 1286/1435] General Project Update - [doc] Updated system requirements -> cmake >= 3.10.2 -> libusb >= 1.0.21 (except for FreeBSD) -> gtk >= 3.22.30 - Updated CHANGELOG.md - Updated list of contributors --- CHANGELOG.md | 16 ++- CMakeLists.txt | 2 +- cmake/modules/Findlibusb.cmake | 2 +- cmake/packaging/cpack_config.cmake | 2 +- cmake/packaging/deb/control | 2 +- contributors.txt | 3 + doc/compiling.md | 4 +- doc/version_support.md | 153 +++++++++++++++-------------- 8 files changed, 103 insertions(+), 81 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 039ca7848..d744ff564 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -5,7 +5,11 @@ Release date: 2022-xx-xx This release drops support for some older operating systems. Check project README for details. -Updated system requirements: Raised minimum version for `cmake` to 3.7.2. + +Updated system requirements: +- `cmake` >= 3.10.2 +- `libusb` >= 1.0.21 +- `libgtk-dev` >= 3.22.30 Features: @@ -15,6 +19,9 @@ Features: - Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) - [STM32H72X/3X]: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) - Added support for STM32WLEx ([#1173](https://github.com/stlink-org/stlink/pull/1173)) +- Added support for STLINK-V3 devices with no MSD ([#1185](https://github.com/stlink-org/stlink/pull/1185)) +- Updated gdb-server.c to allow external memory access on STM32H73xx ([#1196](https://github.com/stlink-org/stlink/pull/1196), [#1197](https://github.com/stlink-org/stlink/pull/1197)) +- Erase addr size / section of the flash memory with st-flash ([#1213](https://github.com/stlink-org/stlink/pull/1213)) Updates & changes: @@ -22,10 +29,12 @@ Updates & changes: - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation ([#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) -- Drop execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) +- Dropped execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) - Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) - Removed redundant array ([#1178](https://github.com/stlink-org/stlink/pull/1178)) - Updated chip config files from the library structs ([#1181](https://github.com/stlink-org/stlink/pull/1181)) +- [doc] Corrected file path in tutorial ([#1186](https://github.com/stlink-org/stlink/pull/1186)) +- Improved chipid checks and printouts ([#1188](https://github.com/stlink-org/stlink/pull/1188)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) @@ -41,6 +50,9 @@ Fixes: - Fixed few warnings for msvc about type conversion with possible lost data ([#1179](https://github.com/stlink-org/stlink/pull/1179)) - st-flash and other utilities search for chip files in the wrong directory ([#1180](https://github.com/stlink-org/stlink/pull/1180), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) - Fixed broken build on 32 bit systems ([#985](https://github.com/stlink-org/stlink/pull/985), [#1175](https://github.com/stlink-org/stlink/pull/1175), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) +- Define 'SSIZE_MAX' if not defined ([#1183](https://github.com/stlink-org/stlink/pull/1183)) +- Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) +- Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) # v1.7.0 diff --git a/CMakeLists.txt b/CMakeLists.txt index fd17d47cc..66bf34e3e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,7 +2,7 @@ # General cmake settings ### -cmake_minimum_required(VERSION 3.7.2) +cmake_minimum_required(VERSION 3.10.2) cmake_policy(SET CMP0042 NEW) set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index cd52026f5..bc04f848d 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -72,7 +72,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to if (WIN32 AND NOT EXISTS "/etc/debian_version") # Skip this for Debian... # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index acd5630fa..587ff5fb5 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -53,7 +53,7 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av set(CPACK_DEBIAN_PACKAGE_RELEASE "1") # CPACK_DEBIAN_PACKAGE_ARCHITECTURE --> Default: Output of dpkg --print-architecture - set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.4.2), libusb-1.0-0-dev (>= 1.0.20)") + set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.10.2), libusb-1.0-0-dev (>= 1.0.21)") set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Nightwalker-87 ") # CPACK_DEBIAN_PACKAGE_DESCRIPTION --> Default: CPACK_DEBIAN_PACKAGE_DESCRIPTION (as it is set) # CPACK_DEBIAN_PACKAGE_SECTION --> Default: “devel” diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index ef51a6cea..7c8d13e47 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -1,7 +1,7 @@ Source: stlink Priority: optional Maintainer: Nightwalker-87 -Build-Depends: cmake, dh-cmake, debhelper (>= 9), libusb-1.0-0-dev, libgtk-3-dev +Build-Depends: cmake (>= 3.10.2), dh-cmake, debhelper (>= 9), libusb-1.0-0-dev (>= 1.0.21), libgtk-3-dev (>= 3.22.30) Standards-Version: 4.5.0 Rules-Requires-Root: no Section: electronics diff --git a/contributors.txt b/contributors.txt index bcaa0b538..cffef89f6 100644 --- a/contributors.txt +++ b/contributors.txt @@ -7,6 +7,8 @@ Andrea Mucignat Andrew Andrianov [necromant] Andrey Yurovsky Andy Isaacson +Andreas Sandberg [andysan] +Antoine Faure [antoinefaure] Anton [Ant-ON] Áron Radics A. Sheaff @@ -24,6 +26,7 @@ Chris Samuelson Christian Deussen [nullsub] Christophe Levantis Craig Lilley +Crest [Crest] Dan Dev Dan Hepler Daniel Campoverde [alx741] diff --git a/doc/compiling.md b/doc/compiling.md index eef207f95..0931c278a 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -7,7 +7,7 @@ On Windows users should ensure that the following software is installed: - `git` (_optional, but recommended_) -- `cmake` (3.17.0 or later) +- `cmake` - `MinGW-w64` (7.0.0 or later) with GCC toolchain 8.1.0 ### Installation @@ -95,7 +95,7 @@ Install the following packages from your package repository: - `git` - `gcc` or `clang` or `mingw32-gcc` or `mingw64-gcc` (C-compiler; very likely gcc is already present) - `build-essential` (on Debian based distros (Debian, Ubuntu)) -- `cmake` (3.4.2 or later, use the latest version available from the repository) +- `cmake` - `rpm` (on Debian based distros (Debian, Ubuntu), needed for package build with `make package`) - `libusb-1.0` - `libusb-1.0-0-dev` (development headers for building) diff --git a/doc/version_support.md b/doc/version_support.md index 4eeb5074a..d7ba5c102 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,97 +1,104 @@ -_Source:_ pkgs.org - [libusb](https://pkgs.org/search/?q=libusb); [cmake](https://pkgs.org/search/?q=cmake); [gtk](https://pkgs.org/search/?q=gtk) (as of May 2021) +_Source:_ [pkgs.org](https://pkgs.org/search) - libusb, cmake, gtk, libgtk) (as of Jan 2022) ## Supported Operating Systems ### Microsoft Windows -On Windows users should ensure that cmake 3.20.2 or any later version is installed.
      -Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb` (1.0.23 at the time of writing). +On Windows users should ensure that cmake **3.10.2** or any later version is installed.
      +Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb`. - Windows 10 - Windows 8.1 ### Apple macOS -| Package Repository | libusb
      version | cmake
      version | gtk-3
      version | Supported macOS versions | -| ------------------ | ------------------- | ------------------ | ------------------ | ------------------------ | -| homebrew | 1.0.24 | 3.20.2 | 3.24.29
      gtk+3 | 10.9 - 11.x | -| MacPorts | 1.0.24 | 3.20.2 | 3.24.29
      gtk3 | 10.4 - 11.x | +| Package Repository | libusb | cmake | gtk-3-dev | Supported macOS versions | +| ------------------ | ------ | ------ | ------------------ | ------------------------ | +| homebrew | 1.0.24 | 3.22.1 | 3.24.30
      gtk+3 | **10.10 - 12.x** | +| MacPorts | 1.0.24 | 3.22.1 | 3.24.31
      gtk3 | **10.4 - 12.x** | NOTE: In order to use a STLINK/V1 programmer on macOS, version 10.15 is required. ### Linux-/Unix-based: -| Operating System | libusb | cmake | gtk-3 | Notes | -| ------------------------- | -------------------------------- | --------- | ----------- | ------------------------ | -| Debian Sid | 1.0.24 | 3.18.4 | 3.24.24 | | -| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | -| Debian 10 (Buster) | 1.0.**22** | 3.13.4 | 3.24.**5** | | -| Debian 9 (Stretch) | 1.0.**21** | **3.7.2** | **3.22.11** | End of Support: Jun 2022 | -| | | | | | -| Ubuntu 21.04 (Hirsute) | 1.0.24 | 3.18.4 | 3.24.25 | End of Support: Jan 2022 | -| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | -| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.10.2 | **3.22.30** | End of Support: Apr 2023 | -| | | | | | -| Fedora Rawhide [x64] | 1.0.24 (`libusbx`) | 3.20.2 | 3.24.29 | | -| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | -| Fedora 33 [x64] | 1.0.23 (`libusbx`) | 3.18.3 | 3.24.23 | | -| | | | | | -| openSUSE Tumbleweed [x64] | 1.0.24 | 3.20.1 | 3.24.29 | | -| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | | -| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.17.0 | 3.24.**14** | End of Support: Dec 2021 | -| | | | | | -| Alpine 3.14 | 1.0.24 | 3.20.3 | 4.2.1 | | -| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | -| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | -| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.**13** | End of Support: Nov 2021 | -| | | | | | -| FreeBSD 13.x | 1.0.**16 - 18** (API 0x01000102) | 3.20.2 | 3.24.27 | | -| FreeBSD 12.x | 1.0.**16 - 18** (API 0x01000102) | 3.19.6 | 3.24.27 | | -| FreeBSD 11.x | 1.0.**16 - 18** (API 0x01000102) | 3.15.5 | 3.24.27 | End of Support: Sep 2021 | -| | | | | | -| Arch Linux | 1.0.24 | 3.20.2 | 3.24.29 | | -| KaOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| Mageia Cauldron | 1.0.24 | 3.20.2 | 3.24.29 | | -| OpenMandriva Cooker | 1.0.24 | 3.20.2 | 3.24.29 | | -| PCLinuxOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| Slackware Current | 1.0.24 | 3.20.2 | 3.24.28 | | -| Solus [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| ALT Linux Sisyphus | 1.0.24 | 3.19.7 | 3.24.29 | | -| NetBSD 9.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | -| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | -| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.18.2 | **3.22.30** | | -| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | -| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.**11** | | -| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.11.4 | 3.24.32 | | -| CentOS 8 [x64] | 1.0.23 (`libusbx`) | 3.11.4 | **3.22.30** | End of Support: Dec 2021 | +| Operating System | libusb | cmake | libgtk-dev | Notes | +| ------------------------- | ------------------------------ | ---------- | ----------- | ------------------------ | +| Debian Sid | 1.0.24 | 3.22.1 | 3.24.31 | | +| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | +| Debian 10 (Buster) | 1.0.**22** | **3.13.4** | 3.24.**5** | | +| | | | | | +| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | +| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | **3.10.2** | 3.**22.30** | End of Support: Apr 2023 | +| | | | | | +| Fedora Rawhide [x64] | 1.0.24 | 3.22.3 | 3.24.31 | | +| Fedora 35 [x64] | 1.0.24 | 3.21.3 | 3.24.30 | | +| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | +| | | | | | +| openSUSE Tumbleweed [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | +| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | End of Support: Dec 2022 | +| | | | | | +| Alpine 3.15 | 1.0.24 | 3.21.3 | 3.24.30 | | +| Alpine 3.14 | 1.0.24 | 3.20.3 | 3.24.28 | | +| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | +| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | +| | | | | | +| FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | +| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | +| | | | | | +| NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | +| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| | | | | | +| CentOS 9 Stream [x64] | 1.0.24 (`libusbx`) | 3.20.3 | 3.24.30 | | +| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | +| | | | | | +| ALT Linux Sisyphus | 1.0.24 | 3.22.1 | 3.24.31 | | +| ALT Linux P10 | 1.0.24 | 3.20.5 | 3.24.31 | | +| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.29 | | +| | | | | | +| OpenMandriva Rolling | 1.0.24 | 3.22.1 | 3.24.31 | | +| OpenMandriva Cooker | 1.0.24 | 3.22.1 | 3.24.31 | | +| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | +| | | | | | +| Arch Linux | 1.0.24 | 3.22.1 | - | | +| KaOS [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | +| Mageia Cauldron | 1.0.24 | 3.22.1 | 3.24.31 | | +| PCLinuxOS [x64] | ? | 3.22.1 | 3.24.31 | | +| Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | +| Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | +| Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | +| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | +| Rocky Linux 8 [x64] | 1.0.23 | 3.20.2 | 3.**22.30** | | +| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | +| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | ## Unsupported Operating Systems (as of Release v1.7.1) Systems with highlighted versions remain compatible with this toolset. -| Operating System | libusb | cmake | End of
      OS-Support | -| ------------------------- | ---------------------- | ---------- | ---------------------- | -| Fedora 32 [x64] | **1.0.23** (`libusbx`) | **3.17.0** | May 2021 | -| Ubuntu 20.10 (Groovy) | **1.0.23** | **3.16.3** | Jul 2021 | -| NetBSD 7.x | **1.0.22** | **3.16.1** | Jun 2020 | -| Alpine 3.10 | **1.0.22** | **3.14.5** | May 2021 | -| Fedora 31 [x64] | **1.0.22** (`libusbx`) | **3.14.5** | Nov 2020 | -| Mageia 7.1 | **1.0.22** | **3.14.3** | Jun 2021 | -| Fedora 30 | **1.0.22** (`libusbx`) | **3.14.2** | May 2020 | -| Ubuntu 19.10 (Eoan) | **1.0.23** | **3.13.4** | Jul 2020 | -| Alpine 3.9 | **1.0.22** | **3.13.0** | Jan 2021 | -| openSUSE Leap 15.1 [x64] | **1.0.21** | **3.10.2** | Jan 2021 | -| Slackware 14.2 | 1.0.20 | 3.5.2 | | -| Ubuntu 16.04 LTS (Xenial) | 1.0.20 | 3.5.1 | Apr 2021 | -| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | -| Debian 8 (Jessie) | 1.0.19 | 3.0.2 | Jun 2020 | -| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | -| Ubuntu 14.04 LTS (Trusty) | 1.0.17 | 2.8.12.2 | Apr 2019 | -| CentOS 6 | 1.0.9 (`libusbx`) | 2.8.12.2 | Nov 2020 | -| Slackware 14.1 | 1.0.9 | 2.8.12 | | -| Slackware 14.0 | 1.0.9 | 2.8.8 | | +| Operating System | libusb | cmake | End of
      OS-Support | +| ------------------------ | ------------------------------ | ---------- | ---------------------- | +| CentOS 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | +| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | +| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | +| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | +| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | +| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | +| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | +| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | +| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | +| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | +| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | +| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | +| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | +| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | +| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | +| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | +| Debian 9 (Stretch) | 1.0.**21** | 3.7.2 | Jun 2022 | +| Slackware 14.2 | 1.0.20 | 3.5.2 | | +| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | +| CentOS 7 [x64] | 1.0.**21** (`libusbx`) | 2.8.12.2 | Jun 2024 | +| Slackware 14.1 | 1.0.9 | 2.8.12 | | +| Slackware 14.0 | 1.0.9 | 2.8.8 | | _All other operating systems which are not listed are unsupported._ From 75092952226682788c394e12c2b90ec121b2054a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 16 Jan 2022 19:31:22 +0100 Subject: [PATCH 1287/1435] [refactoring] Clean-up for headers & defines - Removed additional extern "C" linkage specs - Removed commented sections - Moved out further device specific defines - Renamed defines STM32_CHIP_ID_* --- config/chips/F03x.chip | 2 +- config/chips/F04x.chip | 2 +- config/chips/F05x.chip | 2 +- config/chips/F07x.chip | 2 +- config/chips/F09x.chip | 2 +- config/chips/F1xx_CL.chip | 2 +- config/chips/F1xx_HD.chip | 2 +- config/chips/F1xx_LD.chip | 2 +- config/chips/F1xx_MD.chip | 2 +- config/chips/F1xx_VL_HD.chip | 2 +- config/chips/F1xx_VL_MD_LD.chip | 2 +- config/chips/F1xx_XLD.chip | 2 +- config/chips/F2xx.chip | 2 +- config/chips/F301_F302_F318.chip | 2 +- config/chips/F302_F303_F358.chip | 2 +- config/chips/F302_F303_F398_HD.chip | 2 +- config/chips/F303_F328_F334.chip | 2 +- config/chips/F37x.chip | 2 +- config/chips/F401xB_xC.chip | 2 +- config/chips/F401xD_xE.chip | 2 +- config/chips/F410.chip | 2 +- config/chips/F411xC_xE.chip | 2 +- config/chips/F412.chip | 2 +- config/chips/F413_F423.chip | 2 +- config/chips/F42x_F43x.chip | 2 +- config/chips/F446.chip | 2 +- config/chips/F46x_F47x.chip | 2 +- config/chips/F4x5_F4x7.chip | 2 +- config/chips/F72x_F73x.chip | 2 +- config/chips/F74x_F75x.chip | 2 +- config/chips/F76x_F77x.chip | 2 +- config/chips/G03x_G04x.chip | 2 +- config/chips/G05x_G06x.chip | 2 +- config/chips/G07x_G08x.chip | 2 +- config/chips/G0Bx_G0Cx.chip | 2 +- config/chips/G43x_G44x.chip | 2 +- config/chips/G47x_G48x.chip | 2 +- config/chips/G49x_G4Ax.chip | 2 +- config/chips/H72x_H73x.chip | 2 +- config/chips/H74x_H75x.chip | 2 +- config/chips/H7Ax_H7Bx.chip | 2 +- config/chips/L0xxx_Cat_1.chip | 2 +- config/chips/L0xxx_Cat_2.chip | 2 +- config/chips/L0xxx_Cat_3.chip | 2 +- config/chips/L0xxx_Cat_5.chip | 2 +- config/chips/L1xx_Cat_1.chip | 2 +- config/chips/L1xx_Cat_2.chip | 2 +- config/chips/L1xx_Cat_3.chip | 2 +- config/chips/L1xx_Cat_4.chip | 2 +- config/chips/L1xx_Cat_5.chip | 2 +- config/chips/L41x_L42x.chip | 2 +- config/chips/L43x_L44x.chip | 2 +- config/chips/L45x_L46x.chip | 2 +- config/chips/L47x_L48x.chip | 2 +- config/chips/L496x_L4A6x.chip | 2 +- config/chips/L4Px.chip | 2 +- config/chips/L4Rx.chip | 2 +- config/chips/WBx0_WBx5.chip | 2 +- config/chips/WLx5.chip | 2 +- inc/stlink.h | 17 - inc/stm32.h | 514 ++++++++++++++++++++++++---- src/common.c | 473 +++---------------------- src/st-util/gdb-server.c | 24 +- src/stlink-lib/chipid.c | 74 ---- src/stlink-lib/chipid.h | 6 - src/stlink-lib/flash_loader.c | 92 ++--- src/stlink-lib/flash_loader.h | 6 - src/stlink-lib/sg.h | 6 - src/stlink-lib/usb.h | 6 - src/win32/mmap.h | 6 - src/win32/sys_time.h | 7 - 71 files changed, 612 insertions(+), 737 deletions(-) diff --git a/config/chips/F03x.chip b/config/chips/F03x.chip index 3b4ff2a74..c0a6e5200 100644 --- a/config/chips/F03x.chip +++ b/config/chips/F03x.chip @@ -2,7 +2,7 @@ # dev_type STM32F03x ref_manual_id 0091 -chip_id 0x444 // STM32_CHIPID_STM32_F0xx_SMALL +chip_id 0x444 // STM32_CHIPID_F0xx_SMALL flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 267c93765..9b2ee5586 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -2,7 +2,7 @@ # dev_type STM32F04x ref_manual_id 0091 -chip_id 0x445 // STM32_CHIPID_STM32_F04 +chip_id 0x445 // STM32_CHIPID_F04 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F05x.chip b/config/chips/F05x.chip index dc511e1a2..c32ba0b46 100644 --- a/config/chips/F05x.chip +++ b/config/chips/F05x.chip @@ -2,7 +2,7 @@ # dev_type STM32F05x ref_manual_id 0091 -chip_id 0x440 // STM32_CHIPID_STM32_F0 +chip_id 0x440 // STM32_CHIPID_F0 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index b12ef1bab..5ba832058 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -2,7 +2,7 @@ # dev_type STM32F07x ref_manual_id 0091 -chip_id 0x448 // STM32_CHIPID_STM32_F0_CAN +chip_id 0x448 // STM32_CHIPID_F0_CAN flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index 97f1a1a75..ca987123d 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -2,7 +2,7 @@ # dev_type STM32F09x ref_manual_id 0091 -chip_id 0x442 // STM32_CHIPID_STM32_F09x +chip_id 0x442 // STM32_CHIPID_F09x flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index dd316dca3..0f56362f0 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_CL ref_manual_id 0008 -chip_id 0x418 // STM32_CHIPID_STM32_F1_CONN +chip_id 0x418 // STM32_CHIPID_F1_CONN flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_HD.chip b/config/chips/F1xx_HD.chip index 696b284ba..2af8582e6 100644 --- a/config/chips/F1xx_HD.chip +++ b/config/chips/F1xx_HD.chip @@ -2,7 +2,7 @@ # dev_type F1xx_HD ref_manual_id 0008 -chip_id 0x414 // STM32_CHIPID_STM32_F1_HD +chip_id 0x414 // STM32_CHIPID_F1_HD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_LD.chip b/config/chips/F1xx_LD.chip index 898af4c8c..ffd34fd4a 100644 --- a/config/chips/F1xx_LD.chip +++ b/config/chips/F1xx_LD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_LD ref_manual_id 0008 -chip_id 0x412 // STM32_CHIPID_STM32_F1_LD +chip_id 0x412 // STM32_CHIPID_F1_LD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F1xx_MD.chip b/config/chips/F1xx_MD.chip index a611f3f2d..f27a7a062 100644 --- a/config/chips/F1xx_MD.chip +++ b/config/chips/F1xx_MD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_MD ref_manual_id 0008 -chip_id 0x410 // STM32_CHIPID_STM32_F1_MD +chip_id 0x410 // STM32_CHIPID_F1_MD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F1xx_VL_HD.chip b/config/chips/F1xx_VL_HD.chip index d59fa4814..4f2566949 100644 --- a/config/chips/F1xx_VL_HD.chip +++ b/config/chips/F1xx_VL_HD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_VL_HD ref_manual_id 0041 -chip_id 0x428 // STM32_CHIPID_STM32_F1_VL_HD +chip_id 0x428 // STM32_CHIPID_F1_VL_HD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F1xx_VL_MD_LD.chip b/config/chips/F1xx_VL_MD_LD.chip index aac2244fd..1705bc8e3 100644 --- a/config/chips/F1xx_VL_MD_LD.chip +++ b/config/chips/F1xx_VL_MD_LD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_VL_MD_LD ref_manual_id 0041 -chip_id 0x420 // STM32_CHIPID_STM32_F1_VL_MD_LD +chip_id 0x420 // STM32_CHIPID_F1_VL_MD_LD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip index 7627dd883..37c900f28 100644 --- a/config/chips/F1xx_XLD.chip +++ b/config/chips/F1xx_XLD.chip @@ -2,7 +2,7 @@ # dev_type STM32F1xx_XLD ref_manual_id 0008 -chip_id 0x430 // STM32_CHIPID_STM32_F1_XLD +chip_id 0x430 // STM32_CHIPID_F1_XLD flash_type 2 // STM32_FLASH_TYPE_F1_XL flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip index 5e6aac5a0..314df7d6d 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2xx.chip @@ -2,7 +2,7 @@ # dev_type STM32F2xx ref_manual_id 0033 -chip_id 0x411 // STM32_CHIPID_STM32_F2 +chip_id 0x411 // STM32_CHIPID_F2 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/F301_F302_F318.chip b/config/chips/F301_F302_F318.chip index 3a3d8bb45..f620364b2 100644 --- a/config/chips/F301_F302_F318.chip +++ b/config/chips/F301_F302_F318.chip @@ -2,7 +2,7 @@ # dev_type STM32F301_F302_F318 ref_manual_id 0365 // also RM0366 -chip_id 0x439 // STM32_CHIPID_STM32_F3xx_SMALL +chip_id 0x439 // STM32_CHIPID_F3xx_SMALL flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F302_F303_F358.chip b/config/chips/F302_F303_F358.chip index 922387292..e48370159 100644 --- a/config/chips/F302_F303_F358.chip +++ b/config/chips/F302_F303_F358.chip @@ -2,7 +2,7 @@ # dev_type STM32F302_F303_358 ref_manual_id 0365 // also RM0316 -chip_id 0x422 // STM32_CHIPID_STM32_F3 +chip_id 0x422 // STM32_CHIPID_F3 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F302_F303_F398_HD.chip b/config/chips/F302_F303_F398_HD.chip index 44cec8a6d..181fdfa72 100644 --- a/config/chips/F302_F303_F398_HD.chip +++ b/config/chips/F302_F303_F398_HD.chip @@ -2,7 +2,7 @@ # dev_type STM32F302_F303_F398_HD ref_manual_id 0365 // also RM0316 (Rev 5) -chip_id 0x446 // STM32_CHIPID_STM32_F303_HD +chip_id 0x446 // STM32_CHIPID_F303_HD flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F303_F328_F334.chip b/config/chips/F303_F328_F334.chip index fb77e3117..069de07fb 100644 --- a/config/chips/F303_F328_F334.chip +++ b/config/chips/F303_F328_F334.chip @@ -2,7 +2,7 @@ # dev_type STM32F303_F328_F334 ref_manual_id 0364 // also RM0316 -chip_id 0x438 // STM32_CHIPID_STM32_F334 +chip_id 0x438 // STM32_CHIPID_F334 flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index 5363da8fa..dfe59af0f 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -2,7 +2,7 @@ # dev_type STM32F37x ref_manual_id 0313 -chip_id 0x432 // STM32_CHIPID_STM32_F37x +chip_id 0x432 // STM32_CHIPID_F37x flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F401xB_xC.chip b/config/chips/F401xB_xC.chip index e75b27d09..d961e82b0 100644 --- a/config/chips/F401xB_xC.chip +++ b/config/chips/F401xB_xC.chip @@ -2,7 +2,7 @@ # dev_type STM32F401xB_xC ref_manual_id 0368 -chip_id 0x423 // STM32_CHIPID_STM32_F4_LP +chip_id 0x423 // STM32_CHIPID_F4_LP flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip index 022d5072a..1b58cb5ad 100644 --- a/config/chips/F401xD_xE.chip +++ b/config/chips/F401xD_xE.chip @@ -2,7 +2,7 @@ # dev_type STM32F401xD_xE ref_manual_id 0368 -chip_id 0x433 // STM32_CHIPID_STM32_F4_DE +chip_id 0x433 // STM32_CHIPID_F4_DE flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F410.chip b/config/chips/F410.chip index 84c9c00bf..55dbb749d 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -2,7 +2,7 @@ # dev_type STM32F410 ref_manual_id 0401 -chip_id 0x458 // STM32_CHIPID_STM32_F410 +chip_id 0x458 // STM32_CHIPID_F410 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F411xC_xE.chip b/config/chips/F411xC_xE.chip index d028a874c..51081d338 100644 --- a/config/chips/F411xC_xE.chip +++ b/config/chips/F411xC_xE.chip @@ -2,7 +2,7 @@ # dev_type STM32F411xC_xE ref_manual_id 0383 -chip_id 0x431 // STM32_CHIPID_STM32_F411xx +chip_id 0x431 // STM32_CHIPID_F411xx flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F412.chip b/config/chips/F412.chip index b4c1cb418..6e7aefd19 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -2,7 +2,7 @@ # dev_type STM32F412 ref_manual_id 0402 -chip_id 0x441 // STM32_CHIPID_STM32_F412 +chip_id 0x441 // STM32_CHIPID_F412 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F413_F423.chip b/config/chips/F413_F423.chip index f042bce76..3a865d304 100644 --- a/config/chips/F413_F423.chip +++ b/config/chips/F413_F423.chip @@ -2,7 +2,7 @@ # dev_type STM32F413_F423 ref_manual_id 0430 // RM0430 (Rev 2) -chip_id 0x463 // STM32_CHIPID_STM32_F413 +chip_id 0x463 // STM32_CHIPID_F413 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 69aff7c88..64f459064 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -2,7 +2,7 @@ # dev_type STM32F42x_F43x ref_manual_id 0090 // RM0090 (Rev. 2) -chip_id 0x463 // STM32_CHIPID_STM32_F4_HD +chip_id 0x463 // STM32_CHIPID_F4_HD flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 5fa2edbcb..51ee52517 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -2,7 +2,7 @@ # dev_type STM32F446 ref_manual_id 0390 -chip_id 0x421 // STM32_CHIPID_STM32_F446 +chip_id 0x421 // STM32_CHIPID_F446 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index e8364ead5..4d3931091 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -2,7 +2,7 @@ # dev_type STM32F46x_F47x ref_manual_id 0090 // RM0090 (Rev. 2) -chip_id 0x434 // STM32_CHIPID_STM32_F4_DSI +chip_id 0x434 // STM32_CHIPID_F4_DSI flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F4x5_F4x7.chip b/config/chips/F4x5_F4x7.chip index e78b552c4..f65281272 100644 --- a/config/chips/F4x5_F4x7.chip +++ b/config/chips/F4x5_F4x7.chip @@ -2,7 +2,7 @@ # dev_type STM32F4x5_F4x7 ref_manual_id 0090 // RM0090 (Rev. 2) -chip_id 0x413 // STM32_CHIPID_STM32_F4 +chip_id 0x413 // STM32_CHIPID_F4 flash_type 3 // STM32_FLASH_TYPE_F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index 5e1131d2e..acd411bed 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -2,7 +2,7 @@ # dev_type STM32F72x_F73x ref_manual_id 0431 -chip_id 0x452 // STM32_CHIPID_STM32_F72xxx +chip_id 0x452 // STM32_CHIPID_F72xxx flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff07a22 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F74x_F75x.chip b/config/chips/F74x_F75x.chip index 391ae124d..e081da39d 100644 --- a/config/chips/F74x_F75x.chip +++ b/config/chips/F74x_F75x.chip @@ -2,7 +2,7 @@ # dev_type STM32F74x_F75x ref_manual_id 0385 -chip_id 0x449 // STM32_CHIPID_STM32_F7 +chip_id 0x449 // STM32_CHIPID_F7 flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/F76x_F77x.chip b/config/chips/F76x_F77x.chip index bb87dce7a..c6d04ff78 100644 --- a/config/chips/F76x_F77x.chip +++ b/config/chips/F76x_F77x.chip @@ -2,7 +2,7 @@ # dev_type STM32F76x_F77x ref_manual_id 0410 -chip_id 0x451 // STM32_CHIPID_STM32_F76xxx +chip_id 0x451 // STM32_CHIPID_F76xxx flash_type 4 // STM32_FLASH_TYPE_F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G03x_G04x.chip b/config/chips/G03x_G04x.chip index 4a7e11fcd..fd6dc3bcf 100644 --- a/config/chips/G03x_G04x.chip +++ b/config/chips/G03x_G04x.chip @@ -2,7 +2,7 @@ # dev_type STM32G03x_G04x ref_manual_id 0444 // also RM454 -chip_id 0x466 // STM32_CHIPID_STM32_G0_CAT1 +chip_id 0x466 // STM32_CHIPID_G0_CAT1 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index 81f97b58d..ce5e52de4 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -2,7 +2,7 @@ # dev_type STM32G05x_G06x ref_manual_id 0444 -chip_id 0x456 // STM32_CHIPID_STM32_G0_CAT4 +chip_id 0x456 // STM32_CHIPID_G0_CAT4 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G07x_G08x.chip b/config/chips/G07x_G08x.chip index cac804a78..7a10fc052 100644 --- a/config/chips/G07x_G08x.chip +++ b/config/chips/G07x_G08x.chip @@ -2,7 +2,7 @@ # dev_type STM32G07x_G08x ref_manual_id 0444 -chip_id 0x460 // STM32_CHIPID_STM32_G0_CAT2 +chip_id 0x460 // STM32_CHIPID_G0_CAT2 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index 845cf8280..6ab8ca55a 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -2,7 +2,7 @@ # dev_type STM32G0Bx_G0Cx ref_manual_id 0444 -chip_id 0x467 // STM32_CHIPID_STM32_G0_CAT3 +chip_id 0x467 // STM32_CHIPID_G0_CAT3 flash_type 5 // STM32_FLASH_TYPE_G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G43x_G44x.chip b/config/chips/G43x_G44x.chip index 6b19d4fb4..a7eb86d34 100644 --- a/config/chips/G43x_G44x.chip +++ b/config/chips/G43x_G44x.chip @@ -2,7 +2,7 @@ # dev_type STM32G43x_G44x ref_manual_id 0440 -chip_id 0x468 // STM32_CHIPID_STM32_G4_CAT2 +chip_id 0x468 // STM32_CHIPID_G4_CAT2 flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G47x_G48x.chip b/config/chips/G47x_G48x.chip index d3330da59..1b2b386fd 100644 --- a/config/chips/G47x_G48x.chip +++ b/config/chips/G47x_G48x.chip @@ -2,7 +2,7 @@ # dev_type STM32G47x_G48x ref_manual_id 0440 -chip_id 0x469 // STM32_CHIPID_STM32_G4_CAT3 +chip_id 0x469 // STM32_CHIPID_G4_CAT3 flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip index a39237142..1defbfff8 100644 --- a/config/chips/G49x_G4Ax.chip +++ b/config/chips/G49x_G4Ax.chip @@ -2,7 +2,7 @@ # dev_type STM32G49x_G4Ax ref_manual_id 0440 -chip_id 0x479 // STM32_CHIPID_STM32_G4_CAT4 +chip_id 0x479 // STM32_CHIPID_G4_CAT4 flash_type 6 // STM32_FLASH_TYPE_G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index 998aa9812..50925fdcd 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -2,7 +2,7 @@ # dev_type STM32H72x_H73x ref_manual_id 0468 -chip_id 0x483 // STM32_CHIPID_STM32_H72x +chip_id 0x483 // STM32_CHIPID_H72x flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 0bfea13a4..20bfcd2cb 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -2,7 +2,7 @@ # dev_type STM32H74x_H75x ref_manual_id 0433 -chip_id 0x450 // STM32_CHIPID_STM32_H74xxx +chip_id 0x450 // STM32_CHIPID_H74xxx flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index 2e784193c..b31e4fb88 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -2,7 +2,7 @@ # dev_type STM32H7Ax_H7Bx ref_manual_id 0455 -chip_id 0x480 // STM32_CHIPID_STM32_H7Ax +chip_id 0x480 // STM32_CHIPID_H7Ax flash_type 7 // STM32_FLASH_TYPE_H7 flash_size_reg 0x08fff80c flash_pagesize 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_1.chip b/config/chips/L0xxx_Cat_1.chip index 4b108b4f4..d612143d5 100644 --- a/config/chips/L0xxx_Cat_1.chip +++ b/config/chips/L0xxx_Cat_1.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_1 ref_manual_id 0451 // also RM0377 -chip_id 0x457 // STM32_CHIPID_STM32_L011 +chip_id 0x457 // STM32_CHIPID_L011 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L0xxx_Cat_2.chip b/config/chips/L0xxx_Cat_2.chip index 5665e8df1..49d3e8b07 100644 --- a/config/chips/L0xxx_Cat_2.chip +++ b/config/chips/L0xxx_Cat_2.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_2 ref_manual_id 0451 // also RM0377 -chip_id 0x425 // STM32_CHIPID_STM32_L0_CAT2 +chip_id 0x425 // STM32_CHIPID_L0_CAT2 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L0xxx_Cat_3.chip b/config/chips/L0xxx_Cat_3.chip index e8cd7c685..c1b6c3bf4 100644 --- a/config/chips/L0xxx_Cat_3.chip +++ b/config/chips/L0xxx_Cat_3.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_3 ref_manual_id 0451 // also RM0367 & RM0377 -chip_id 0x417 // STM32_CHIPID_STM32_L0 +chip_id 0x417 // STM32_CHIPID_L0 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L0xxx_Cat_5.chip b/config/chips/L0xxx_Cat_5.chip index 284057091..94e14dfe0 100644 --- a/config/chips/L0xxx_Cat_5.chip +++ b/config/chips/L0xxx_Cat_5.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_5 ref_manual_id 0451 // also RM0367 & RM0377 -chip_id 0x447 // STM32_CHIPID_STM32_L0_CAT5 +chip_id 0x447 // STM32_CHIPID_L0_CAT5 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L1xx_Cat_1.chip b/config/chips/L1xx_Cat_1.chip index f6a11288f..16f2ff8c9 100644 --- a/config/chips/L1xx_Cat_1.chip +++ b/config/chips/L1xx_Cat_1.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_1 ref_manual_id 0038 -chip_id 0x416 // STM32_CHIPID_STM32_L1_MD +chip_id 0x416 // STM32_CHIPID_L1_MD flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_2.chip b/config/chips/L1xx_Cat_2.chip index c8c796111..82d7dfe44 100644 --- a/config/chips/L1xx_Cat_2.chip +++ b/config/chips/L1xx_Cat_2.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_2 ref_manual_id 0038 -chip_id 0x429 // STM32_CHIPID_STM32_L1_CAT2 +chip_id 0x429 // STM32_CHIPID_L1_CAT2 flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_3.chip b/config/chips/L1xx_Cat_3.chip index f2615f952..2241e5bde 100644 --- a/config/chips/L1xx_Cat_3.chip +++ b/config/chips/L1xx_Cat_3.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_3 ref_manual_id 0038 -chip_id 0x427 // STM32_CHIPID_STM32_L1_MD_PLUS +chip_id 0x427 // STM32_CHIPID_L1_MD_PLUS flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_4.chip b/config/chips/L1xx_Cat_4.chip index 6a1df1267..7933d7121 100644 --- a/config/chips/L1xx_Cat_4.chip +++ b/config/chips/L1xx_Cat_4.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_4 ref_manual_id 0038 -chip_id 0x436 // STM32_CHIPID_STM32_L1_MD_PLUS_HD +chip_id 0x436 // STM32_CHIPID_L1_MD_PLUS_HD flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B diff --git a/config/chips/L1xx_Cat_5.chip b/config/chips/L1xx_Cat_5.chip index 4fccd99da..0e95e54e8 100644 --- a/config/chips/L1xx_Cat_5.chip +++ b/config/chips/L1xx_Cat_5.chip @@ -2,7 +2,7 @@ # dev_type STM32L1xx_Cat_5 ref_manual_id 0038 -chip_id 0x437 // STM32_CHIPID_STM32_L152_RE +chip_id 0x437 // STM32_CHIPID_L152_RE flash_type 8 // STM32_FLASH_TYPE_L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B diff --git a/config/chips/L41x_L42x.chip b/config/chips/L41x_L42x.chip index 40085d828..726645552 100644 --- a/config/chips/L41x_L42x.chip +++ b/config/chips/L41x_L42x.chip @@ -2,7 +2,7 @@ # dev_type STM32L41x_L42x ref_manual_id 0394 -chip_id 0x464 // STM32_CHIPID_STM32_L41x_L42x +chip_id 0x464 // STM32_CHIPID_L41x_L42x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index 22045c372..baba13e55 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -2,7 +2,7 @@ # dev_type STM32L41x_L42x ref_manual_id 0392 -chip_id 0x435 // STM32_CHIPID_STM32_L43x_L44x +chip_id 0x435 // STM32_CHIPID_L43x_L44x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index 99e9beca1..8886633e2 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -2,7 +2,7 @@ # dev_type STM32L45x_L46x ref_manual_id 0394 -chip_id 0x462 // STM32_CHIPID_STM32_L45x_L46x +chip_id 0x462 // STM32_CHIPID_L45x_L46x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L47x_L48x.chip b/config/chips/L47x_L48x.chip index 44e5282ce..df96ee2fb 100644 --- a/config/chips/L47x_L48x.chip +++ b/config/chips/L47x_L48x.chip @@ -2,7 +2,7 @@ # dev_type STM32L47x_L48x ref_manual_id 0351 -chip_id 0x415 // STM32_CHIPID_STM32_L4 +chip_id 0x415 // STM32_CHIPID_L4 flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index b983eb9eb..0f4bd285d 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -2,7 +2,7 @@ # dev_type STM32L496x_L4A6x ref_manual_id 0351 -chip_id 0x461 // STM32_CHIPID_STM32_L496x_L4A6x +chip_id 0x461 // STM32_CHIPID_L496x_L4A6x flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/config/chips/L4Px.chip b/config/chips/L4Px.chip index 41805c768..2d1a59806 100644 --- a/config/chips/L4Px.chip +++ b/config/chips/L4Px.chip @@ -2,7 +2,7 @@ # dev_type STM32L4Px ref_manual_id 0432 -chip_id 0x471 // STM32_CHIPID_STM32_L4PX +chip_id 0x471 // STM32_CHIPID_L4PX flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index d0495f083..f0593a97e 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -2,7 +2,7 @@ # dev_type STM32L4Rx ref_manual_id 0432 -chip_id 0x470 // STM32_CHIPID_STM32_L4RX +chip_id 0x470 // STM32_CHIPID_L4RX flash_type 9 // STM32_FLASH_TYPE_L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB diff --git a/config/chips/WBx0_WBx5.chip b/config/chips/WBx0_WBx5.chip index e34c70815..3d27edd6d 100644 --- a/config/chips/WBx0_WBx5.chip +++ b/config/chips/WBx0_WBx5.chip @@ -2,7 +2,7 @@ # dev_type STM32WBx0_WBx5 ref_manual_id 0434 // also RM0471 -chip_id 0x495 // STM32_CHIPID_STM32_WB55 +chip_id 0x495 // STM32_CHIPID_WB55 flash_type 11 // STM32_FLASH_TYPE_WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB diff --git a/config/chips/WLx5.chip b/config/chips/WLx5.chip index b27e03dfe..9669fe27f 100644 --- a/config/chips/WLx5.chip +++ b/config/chips/WLx5.chip @@ -2,7 +2,7 @@ # dev_type STM32WLEx ref_manual_id 0033 -chip_id 0x497 // STM32_CHIPID_STM32_WLE +chip_id 0x497 // STM32_CHIPID_WLE flash_type 11 // STM32_FLASH_TYPE_WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB diff --git a/inc/stlink.h b/inc/stlink.h index f6bd5cb0d..4899533ec 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -106,23 +106,6 @@ enum target_state { #define C_BUF_LEN 32 -// /* Old flash type definitions */ -// // TODO: Transition to the new defines in stm32.h -// enum stlink_flash_type { -// /* 0 */ STLINK_FLASH_TYPE_UNKNOWN = 0, -// /* 1 */ STLINK_FLASH_TYPE_F0, // used by f0, f1 (except f1xl),f3. */ -// /* 2 */ STLINK_FLASH_TYPE_F1_XL, // f0 flash with dual bank */ -// /* 3 */ STLINK_FLASH_TYPE_F4, // used by f2, f4 */ -// /* 4 */ STLINK_FLASH_TYPE_F7, -// /* 5 */ STLINK_FLASH_TYPE_L0, // l0, l1 */ -// /* 6 */ STLINK_FLASH_TYPE_L4, // l4, l4+ */ -// /* 7 */ STLINK_FLASH_TYPE_G0, -// /* 8 */ STLINK_FLASH_TYPE_G4, -// /* 9 */ STLINK_FLASH_TYPE_WB, -// /* 10 */ STLINK_FLASH_TYPE_H7, -// /* 11 */ STLINK_FLASH_TYPE_MAX, -// }; - struct stlink_reg { uint32_t r[16]; uint32_t s[32]; diff --git a/inc/stm32.h b/inc/stm32.h index d6faff12e..2e8ed6889 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -48,75 +48,67 @@ enum stm32_flash_type { enum stm32_chipids { STM32_CHIPID_UNKNOWN = 0x000, - STM32_CHIPID_STM32_F1_MD = 0x410, /* medium density */ - STM32_CHIPID_STM32_F2 = 0x411, - STM32_CHIPID_STM32_F1_LD = 0x412, /* low density */ - STM32_CHIPID_STM32_F4 = 0x413, - STM32_CHIPID_STM32_F1_HD = 0x414, /* high density */ - STM32_CHIPID_STM32_L4 = 0x415, - STM32_CHIPID_STM32_L1_MD = 0x416, /* medium density */ - STM32_CHIPID_STM32_L0 = 0x417, - STM32_CHIPID_STM32_F1_CONN = 0x418, /* connectivity line */ - STM32_CHIPID_STM32_F4_HD = 0x419, /* high density */ - STM32_CHIPID_STM32_F1_VL_MD_LD = 0x420, /* value line medium & low density */ - STM32_CHIPID_STM32_F446 = 0x421, - STM32_CHIPID_STM32_F3 = 0x422, - STM32_CHIPID_STM32_F4_LP = 0x423, - STM32_CHIPID_STM32_L0_CAT2 = 0x425, - STM32_CHIPID_STM32_L1_MD_PLUS = 0x427, /* medium density plus */ - STM32_CHIPID_STM32_F1_VL_HD = 0x428, /* value line high density */ - STM32_CHIPID_STM32_L1_CAT2 = 0x429, - STM32_CHIPID_STM32_F1_XLD = 0x430, /* extra low density plus */ - STM32_CHIPID_STM32_F411xx = 0x431, - STM32_CHIPID_STM32_F37x = 0x432, - STM32_CHIPID_STM32_F4_DE = 0x433, - STM32_CHIPID_STM32_F4_DSI = 0x434, - STM32_CHIPID_STM32_L43x_L44x = 0x435, - STM32_CHIPID_STM32_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ - STM32_CHIPID_STM32_L152_RE = 0x437, - STM32_CHIPID_STM32_F334 = 0x438, - STM32_CHIPID_STM32_F3xx_SMALL = 0x439, - STM32_CHIPID_STM32_F0 = 0x440, - STM32_CHIPID_STM32_F412 = 0x441, - STM32_CHIPID_STM32_F09x = 0x442, - STM32_CHIPID_STM32_F0xx_SMALL = 0x444, - STM32_CHIPID_STM32_F04 = 0x445, - STM32_CHIPID_STM32_F303_HD = 0x446, /* high density */ - STM32_CHIPID_STM32_L0_CAT5 = 0x447, - STM32_CHIPID_STM32_F0_CAN = 0x448, - STM32_CHIPID_STM32_F7 = 0x449, /* Nucleo F746ZG board */ - STM32_CHIPID_STM32_H74xxx = 0x450, /* RM0433, p.3189 */ - STM32_CHIPID_STM32_F76xxx = 0x451, - STM32_CHIPID_STM32_F72xxx = 0x452, /* Nucleo F722ZE board */ - STM32_CHIPID_STM32_G0_CAT4 = 0x456, /* G051/G061 */ - STM32_CHIPID_STM32_L011 = 0x457, - STM32_CHIPID_STM32_F410 = 0x458, - STM32_CHIPID_STM32_G0_CAT2 = 0x460, /* G070/G071/G081 */ - STM32_CHIPID_STM32_L496x_L4A6x = 0x461, - STM32_CHIPID_STM32_L45x_L46x = 0x462, - STM32_CHIPID_STM32_F413 = 0x463, - STM32_CHIPID_STM32_L41x_L42x = 0x464, - STM32_CHIPID_STM32_G0_CAT1 = 0x466, /* G030/G031/G041 */ - STM32_CHIPID_STM32_G0_CAT3 = 0x467, /* G0B1/G0C1 */ - STM32_CHIPID_STM32_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ - STM32_CHIPID_STM32_G4_CAT3 = 0x469, - STM32_CHIPID_STM32_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ - STM32_CHIPID_STM32_L4PX = 0x471, /* RM0432, p.2247 */ - STM32_CHIPID_STM32_G4_CAT4 = 0x479, - STM32_CHIPID_STM32_H7Ax = 0x480, /* RM0455, p.2863 */ - STM32_CHIPID_STM32_H72x = 0x483, /* RM0468, p.3199 */ - STM32_CHIPID_STM32_WB55 = 0x495, - STM32_CHIPID_STM32_WLE = 0x497, + STM32_CHIPID_F1_MD = 0x410, /* medium density */ + STM32_CHIPID_F2 = 0x411, + STM32_CHIPID_F1_LD = 0x412, /* low density */ + STM32_CHIPID_F4 = 0x413, + STM32_CHIPID_F1_HD = 0x414, /* high density */ + STM32_CHIPID_L4 = 0x415, + STM32_CHIPID_L1_MD = 0x416, /* medium density */ + STM32_CHIPID_L0 = 0x417, + STM32_CHIPID_F1_CONN = 0x418, /* connectivity line */ + STM32_CHIPID_F4_HD = 0x419, /* high density */ + STM32_CHIPID_F1_VL_MD_LD = 0x420, /* value line medium & low density */ + STM32_CHIPID_F446 = 0x421, + STM32_CHIPID_F3 = 0x422, + STM32_CHIPID_F4_LP = 0x423, + STM32_CHIPID_L0_CAT2 = 0x425, + STM32_CHIPID_L1_MD_PLUS = 0x427, /* medium density plus */ + STM32_CHIPID_F1_VL_HD = 0x428, /* value line high density */ + STM32_CHIPID_L1_CAT2 = 0x429, + STM32_CHIPID_F1_XLD = 0x430, /* extra low density plus */ + STM32_CHIPID_F411xx = 0x431, + STM32_CHIPID_F37x = 0x432, + STM32_CHIPID_F4_DE = 0x433, + STM32_CHIPID_F4_DSI = 0x434, + STM32_CHIPID_L43x_L44x = 0x435, + STM32_CHIPID_L1_MD_PLUS_HD = 0x436, /* medium density plus & high density */ + STM32_CHIPID_L152_RE = 0x437, + STM32_CHIPID_F334 = 0x438, + STM32_CHIPID_F3xx_SMALL = 0x439, + STM32_CHIPID_F0 = 0x440, + STM32_CHIPID_F412 = 0x441, + STM32_CHIPID_F09x = 0x442, + STM32_CHIPID_F0xx_SMALL = 0x444, + STM32_CHIPID_F04 = 0x445, + STM32_CHIPID_F303_HD = 0x446, /* high density */ + STM32_CHIPID_L0_CAT5 = 0x447, + STM32_CHIPID_F0_CAN = 0x448, + STM32_CHIPID_F7 = 0x449, /* Nucleo F746ZG board */ + STM32_CHIPID_H74xxx = 0x450, /* RM0433, p.3189 */ + STM32_CHIPID_F76xxx = 0x451, + STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ + STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ + STM32_CHIPID_L011 = 0x457, + STM32_CHIPID_F410 = 0x458, + STM32_CHIPID_G0_CAT2 = 0x460, /* G070/G071/G081 */ + STM32_CHIPID_L496x_L4A6x = 0x461, + STM32_CHIPID_L45x_L46x = 0x462, + STM32_CHIPID_F413 = 0x463, + STM32_CHIPID_L41x_L42x = 0x464, + STM32_CHIPID_G0_CAT1 = 0x466, /* G030/G031/G041 */ + STM32_CHIPID_G0_CAT3 = 0x467, /* G0B1/G0C1 */ + STM32_CHIPID_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ + STM32_CHIPID_G4_CAT3 = 0x469, + STM32_CHIPID_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ + STM32_CHIPID_L4PX = 0x471, /* RM0432, p.2247 */ + STM32_CHIPID_G4_CAT4 = 0x479, + STM32_CHIPID_H7Ax = 0x480, /* RM0455, p.2863 */ + STM32_CHIPID_H72x = 0x483, /* RM0468, p.3199 */ + STM32_CHIPID_WB55 = 0x495, + STM32_CHIPID_WLE = 0x497, }; -/* Constant STM32 memory address */ -#define STM32_SRAM_BASE ((uint32_t)0x20000000) -#define STM32_FLASH_BASE ((uint32_t)0x08000000) - -#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) -#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) - - /* Constant STM32 option bytes base memory address */ #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14) @@ -137,4 +129,392 @@ enum stm32_chipids { #define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) #define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1ffff800) +/* ============ */ +/* Old defines from common.c are below */ +/* ============ */ + +/* Constant STM32 memory address */ +#define STM32_SRAM_BASE ((uint32_t)0x20000000) +#define STM32_FLASH_BASE ((uint32_t)0x08000000) + +#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) +#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) + +/* stm32f FPEC flash controller interface, pm0063 manual */ +// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) +#define FLASH_REGS_ADDR 0x40022000 +#define FLASH_REGS_SIZE 0x28 + +#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) +#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) +#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) +#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) +#define FLASH_CR (FLASH_REGS_ADDR + 0x10) +#define FLASH_AR (FLASH_REGS_ADDR + 0x14) +#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) +#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) + +// STM32F10x_XL has two flash memory banks with separate registers to control +// the second bank. +#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) +#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) +#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) +#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) + +// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... +#define FLASH_RDPTR_KEY 0x00a5 +#define FLASH_KEY1 0x45670123 +#define FLASH_KEY2 0xcdef89ab + +#define FLASH_L0_PRGKEY1 0x8c9daebf +#define FLASH_L0_PRGKEY2 0x13141516 + +#define FLASH_L0_PEKEY1 0x89abcdef +#define FLASH_L0_PEKEY2 0x02030405 + +#define FLASH_OPTKEY1 0x08192A3B +#define FLASH_OPTKEY2 0x4C5D6E7F + +#define FLASH_F0_OPTKEY1 0x45670123 +#define FLASH_F0_OPTKEY2 0xCDEF89AB + +#define FLASH_L0_OPTKEY1 0xFBEAD9C8 +#define FLASH_L0_OPTKEY2 0x24252627 + +#define FLASH_SR_BSY 0 +#define FLASH_SR_PG_ERR 2 +#define FLASH_SR_WRPRT_ERR 4 +#define FLASH_SR_EOP 5 + +#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) + +#define FLASH_CR_PG 0 +#define FLASH_CR_PER 1 +#define FLASH_CR_MER 2 +#define FLASH_CR_OPTPG 4 +#define FLASH_CR_OPTER 5 +#define FLASH_CR_STRT 6 +#define FLASH_CR_LOCK 7 +#define FLASH_CR_OPTWRE 9 +#define FLASH_CR_OBL_LAUNCH 13 + +#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) +#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) +#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) +#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) +#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) +#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) +#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) +#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) +#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) +#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) +#define FLASH_L1_FPRG 10 +#define FLASH_L1_PROG 3 + +// Flash registers common to STM32G0 and STM32G4 series. +#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) +#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) +#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) +#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) +#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) +#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) +#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) + +// G0 (RM0444 Table 1, sec 3.7) +// Mostly the same as G4 chips, but the notation +// varies a bit after the 'OPTR' register. +#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) +#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) +#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) +#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) +#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) +#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) +#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) +#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) + +// G4 (RM0440 Table 17, sec 3.7.19) +// Mostly the same as STM32G0 chips, but there are a few extra +// registers because 'cat 3' devices can have two Flash banks. +#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) +#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) +#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) +#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) +#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) +#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) +#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) +#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) +#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) +#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) +#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) +#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) + +// G0/G4 FLASH control register +#define STM32Gx_FLASH_CR_PG (0) /* Program */ +#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ +#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ +#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ +#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ +#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ +#define STM32Gx_FLASH_CR_STRT (16) /* Start */ +#define STM32Gx_FLASH_CR_OPTSTRT \ + (17) /* Start of modification of option bytes */ +#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ +#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ +#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ +#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ +#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ + +// G0/G4 FLASH status register +#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) +#define STM32Gx_FLASH_SR_PROGERR (3) +#define STM32Gx_FLASH_SR_WRPERR (4) +#define STM32Gx_FLASH_SR_PGAERR (5) +#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ +#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ + +// G4 FLASH option register +#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ + +// WB (RM0434) +#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) +#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) +#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) +#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) +#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) +#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) +#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) +#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) +#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) +#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) +#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) +#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) +#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) +#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) +#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) +#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) +#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) +#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) +#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) +#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) + +// WB Flash control register. +#define STM32WB_FLASH_CR_STRT (16) /* Start */ +#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ +#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ +// WB Flash status register. +#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ +#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ +#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ +#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ +#define STM32WB_FLASH_SR_BSY (16) /* Busy */ + +// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) +#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) +#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) +#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) +#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) +#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) + +#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ +#define STM32L4_FLASH_SR_PROGERR 3 +#define STM32L4_FLASH_SR_WRPERR 4 +#define STM32L4_FLASH_SR_PGAERR 5 +#define STM32L4_FLASH_SR_BSY 16 + +#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ +#define STM32L4_FLASH_CR_PG 0 /* Program */ +#define STM32L4_FLASH_CR_PER 1 /* Page erase */ +#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ +#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ +#define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ +#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ +#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ +// Bits requesting flash operations (useful when we want to clear them) +#define STM32L4_FLASH_CR_OPBITS \ + (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ + (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) +// Page is fully specified by BKER and PNB +#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) + +#define STM32L4_FLASH_OPTR_DUALBANK 21 + +// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf +#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) + +#define STM32L0_FLASH_PELOCK (0) +#define STM32L0_FLASH_OPTLOCK (2) +#define STM32L0_FLASH_OBL_LAUNCH (18) + +#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 +#define STM32L0_FLASH_SR_WRPERR 8 +#define STM32L0_FLASH_SR_PGAERR 9 +#define STM32L0_FLASH_SR_NOTZEROERR 16 + +#define FLASH_ACR_OFF ((uint32_t)0x00) +#define FLASH_PECR_OFF ((uint32_t)0x04) +#define FLASH_PDKEYR_OFF ((uint32_t)0x08) +#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) +#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) +#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) +#define FLASH_SR_OFF ((uint32_t)0x18) +#define FLASH_OBR_OFF ((uint32_t)0x1c) +#define FLASH_WRPR_OFF ((uint32_t)0x20) + +// STM32F7 +#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) +#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) +#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) +#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) +#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) +#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) +#define FLASH_F7_OPTCR_LOCK 0 +#define FLASH_F7_OPTCR_START 1 +#define FLASH_F7_CR_STRT 16 +#define FLASH_F7_CR_LOCK 31 +#define FLASH_F7_CR_SER 1 +#define FLASH_F7_CR_SNB 3 +#define FLASH_F7_CR_SNB_MASK 0xf8 +#define FLASH_F7_SR_BSY 16 +#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ +#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ +#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ +#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ +#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ +#define FLASH_F7_SR_EOP 0 /* End of operation */ +#define FLASH_F7_OPTCR1_BOOT_ADD0 0 +#define FLASH_F7_OPTCR1_BOOT_ADD1 16 + +#define FLASH_F7_SR_ERROR_MASK \ + ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ + (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ + (1 << FLASH_F7_SR_OP_ERR)) + +// STM32F4 +#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) +#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) +#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) +#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) +#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) +#define FLASH_F4_OPTCR_LOCK 0 +#define FLASH_F4_OPTCR_START 1 +#define FLASH_F4_CR_STRT 16 +#define FLASH_F4_CR_LOCK 31 +#define FLASH_F4_CR_SER 1 +#define FLASH_F4_CR_SNB 3 +#define FLASH_F4_CR_SNB_MASK 0xf8 +#define FLASH_F4_SR_ERROR_MASK 0x000000F0 +#define FLASH_F4_SR_PGAERR 5 +#define FLASH_F4_SR_WRPERR 4 +#define FLASH_F4_SR_BSY 16 + +// STM32F2 +#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) +#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) +#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) +#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) +#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) +#define FLASH_F2_OPT_LOCK_BIT (1u << 0) +#define FLASH_F2_CR_STRT 16 +#define FLASH_F2_CR_LOCK 31 + +#define FLASH_F2_CR_SER 1 +#define FLASH_F2_CR_SNB 3 +#define FLASH_F2_CR_SNB_MASK 0x78 +#define FLASH_F2_SR_BSY 16 + +// STM32H7xx +#define FLASH_H7_CR_LOCK 0 +#define FLASH_H7_CR_PG 1 +#define FLASH_H7_CR_SER 2 +#define FLASH_H7_CR_BER 3 +#define FLASH_H7_CR_PSIZE 4 +#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7) +#define FLASH_H7_CR_SNB 8 +#define FLASH_H7_CR_SNB_MASK 0x700 + +#define FLASH_H7_SR_QW 2 +#define FLASH_H7_SR_WRPERR 17 +#define FLASH_H7_SR_PGSERR 18 +#define FLASH_H7_SR_STRBERR 19 +#define FLASH_H7_SR_ERROR_MASK \ + ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ + (1 << FLASH_H7_SR_WRPERR)) + +#define FLASH_H7_OPTCR_OPTLOCK 0 +#define FLASH_H7_OPTCR_OPTSTART 1 +#define FLASH_H7_OPTCR_MER 4 + +#define FLASH_H7_OPTSR_OPT_BUSY 0 +#define FLASH_H7_OPTSR_OPTCHANGEERR 30 + +#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 + +#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) +#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) +#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) +#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) +#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) +#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) +#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) +#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) +#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) +#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) +#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) +#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) +#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) +#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) + +#define STM32F0_DBGMCU_CR 0xE0042004 +#define STM32F0_DBGMCU_CR_IWDG_STOP 8 +#define STM32F0_DBGMCU_CR_WWDG_STOP 9 + +#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 +#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 +#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 + +#define STM32L0_DBGMCU_APB1_FZ 0x40015808 +#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 +#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 + +#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 +#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 + +#define STM32WB_DBGMCU_APB1FZR1 0xE004203C +#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 +#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 + +#define STM32F1_RCC_AHBENR 0x40021014 +#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32F4_RCC_AHB1ENR 0x40023830 +#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN + +#define STM32G0_RCC_AHBENR 0x40021038 +#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32G4_RCC_AHB1ENR 0x40021048 +#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32L0_RCC_AHBENR 0x40021030 +#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN + +#define STM32H7_RCC_AHB1ENR 0x58024538 +#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32WB_RCC_AHB1ENR 0x58000048 +#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define L1_WRITE_BLOCK_SIZE 0x80 +#define L0_WRITE_BLOCK_SIZE 0x40 + #endif // STM32_H diff --git a/src/common.c b/src/common.c index 5a9c43c96..bdd38b21a 100644 --- a/src/common.c +++ b/src/common.c @@ -35,384 +35,7 @@ #define BANK_1 0 #define BANK_2 1 -/* stm32f FPEC flash controller interface, pm0063 manual */ -// TODO - all of this needs to be abstracted out.... -// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, -// August 2012) -#define FLASH_REGS_ADDR 0x40022000 -#define FLASH_REGS_SIZE 0x28 - -#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) -#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) -#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) -#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) -#define FLASH_CR (FLASH_REGS_ADDR + 0x10) -#define FLASH_AR (FLASH_REGS_ADDR + 0x14) -#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) -#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) - -// STM32F10x_XL has two flash memory banks with separate registers to control -// the second bank. -#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) -#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) -#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) -#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) - -// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... -#define FLASH_RDPTR_KEY 0x00a5 -#define FLASH_KEY1 0x45670123 -#define FLASH_KEY2 0xcdef89ab - -#define FLASH_L0_PRGKEY1 0x8c9daebf -#define FLASH_L0_PRGKEY2 0x13141516 - -#define FLASH_L0_PEKEY1 0x89abcdef -#define FLASH_L0_PEKEY2 0x02030405 - -#define FLASH_OPTKEY1 0x08192A3B -#define FLASH_OPTKEY2 0x4C5D6E7F - -#define FLASH_F0_OPTKEY1 0x45670123 -#define FLASH_F0_OPTKEY2 0xCDEF89AB - -#define FLASH_L0_OPTKEY1 0xFBEAD9C8 -#define FLASH_L0_OPTKEY2 0x24252627 - -#define FLASH_SR_BSY 0 -#define FLASH_SR_PG_ERR 2 -#define FLASH_SR_WRPRT_ERR 4 -#define FLASH_SR_EOP 5 - -#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) - -#define FLASH_CR_PG 0 -#define FLASH_CR_PER 1 -#define FLASH_CR_MER 2 -#define FLASH_CR_OPTPG 4 -#define FLASH_CR_OPTER 5 -#define FLASH_CR_STRT 6 -#define FLASH_CR_LOCK 7 -#define FLASH_CR_OPTWRE 9 -#define FLASH_CR_OBL_LAUNCH 13 - -#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) -#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) -#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) -#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) -#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) -#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) -#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) -#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) -#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) -#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) -#define FLASH_L1_FPRG 10 -#define FLASH_L1_PROG 3 - -// Flash registers common to STM32G0 and STM32G4 series. -#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) -#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) -#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) -#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) -#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) -#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) -#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) - -// G0 (RM0444 Table 1, sec 3.7) -// Mostly the same as G4 chips, but the notation -// varies a bit after the 'OPTR' register. -#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) -#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) -#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) -#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) -#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) -#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) -#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) - -// G4 (RM0440 Table 17, sec 3.7.19) -// Mostly the same as STM32G0 chips, but there are a few extra -// registers because 'cat 3' devices can have two Flash banks. -#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) -#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) -#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) -#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) -#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) -#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) -#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) -#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) -#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) -#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) -#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) - -// G0/G4 FLASH control register -#define STM32Gx_FLASH_CR_PG (0) /* Program */ -#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ -#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ -#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ -#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define STM32Gx_FLASH_CR_STRT (16) /* Start */ -#define STM32Gx_FLASH_CR_OPTSTRT \ - (17) /* Start of modification of option bytes */ -#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ -#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ -#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ -#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ -#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ - -// G0/G4 FLASH status register -#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) -#define STM32Gx_FLASH_SR_PROGERR (3) -#define STM32Gx_FLASH_SR_WRPERR (4) -#define STM32Gx_FLASH_SR_PGAERR (5) -#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ - -// G4 FLASH option register -#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ - -// WB (RM0434) -#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) -#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) -#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) -#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) -#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) -#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) -#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) -#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) -#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) -#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) -#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) - -// WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ -// WB Flash status register. -#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ -#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ -#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ -#define STM32WB_FLASH_SR_BSY (16) /* Busy */ - -// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) -#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) -#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) -#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) -#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) -#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) - -#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ -#define STM32L4_FLASH_SR_PROGERR 3 -#define STM32L4_FLASH_SR_WRPERR 4 -#define STM32L4_FLASH_SR_PGAERR 5 -#define STM32L4_FLASH_SR_BSY 16 - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ -#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ -// Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ - (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) -// Page is fully specified by BKER and PNB -#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) - -#define STM32L4_FLASH_OPTR_DUALBANK 21 - -// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf -#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) - -#define STM32L0_FLASH_PELOCK (0) -#define STM32L0_FLASH_OPTLOCK (2) -#define STM32L0_FLASH_OBL_LAUNCH (18) - -#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 -#define STM32L0_FLASH_SR_WRPERR 8 -#define STM32L0_FLASH_SR_PGAERR 9 -#define STM32L0_FLASH_SR_NOTZEROERR 16 - -#define FLASH_ACR_OFF ((uint32_t)0x00) -#define FLASH_PECR_OFF ((uint32_t)0x04) -#define FLASH_PDKEYR_OFF ((uint32_t)0x08) -#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) -#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) -#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) -#define FLASH_SR_OFF ((uint32_t)0x18) -#define FLASH_OBR_OFF ((uint32_t)0x1c) -#define FLASH_WRPR_OFF ((uint32_t)0x20) - -// STM32F7 -#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) -#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) -#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) -#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) -#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) -#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) -#define FLASH_F7_OPTCR_LOCK 0 -#define FLASH_F7_OPTCR_START 1 -#define FLASH_F7_CR_STRT 16 -#define FLASH_F7_CR_LOCK 31 -#define FLASH_F7_CR_SER 1 -#define FLASH_F7_CR_SNB 3 -#define FLASH_F7_CR_SNB_MASK 0xf8 -#define FLASH_F7_SR_BSY 16 -#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ -#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ -#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ -#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ -#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ -#define FLASH_F7_SR_EOP 0 /* End of operation */ -#define FLASH_F7_OPTCR1_BOOT_ADD0 0 -#define FLASH_F7_OPTCR1_BOOT_ADD1 16 - -#define FLASH_F7_SR_ERROR_MASK \ - ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ - (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ - (1 << FLASH_F7_SR_OP_ERR)) - -// STM32F4 -#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) -#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) -#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) -#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) -#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) -#define FLASH_F4_OPTCR_LOCK 0 -#define FLASH_F4_OPTCR_START 1 -#define FLASH_F4_CR_STRT 16 -#define FLASH_F4_CR_LOCK 31 -#define FLASH_F4_CR_SER 1 -#define FLASH_F4_CR_SNB 3 -#define FLASH_F4_CR_SNB_MASK 0xf8 -#define FLASH_F4_SR_ERROR_MASK 0x000000F0 -#define FLASH_F4_SR_PGAERR 5 -#define FLASH_F4_SR_WRPERR 4 -#define FLASH_F4_SR_BSY 16 - -// STM32F2 -#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) -#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) -#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) -#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) -#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) -#define FLASH_F2_OPT_LOCK_BIT (1u << 0) -#define FLASH_F2_CR_STRT 16 -#define FLASH_F2_CR_LOCK 31 - -#define FLASH_F2_CR_SER 1 -#define FLASH_F2_CR_SNB 3 -#define FLASH_F2_CR_SNB_MASK 0x78 -#define FLASH_F2_SR_BSY 16 - -// STM32H7xx -#define FLASH_H7_CR_LOCK 0 -#define FLASH_H7_CR_PG 1 -#define FLASH_H7_CR_SER 2 -#define FLASH_H7_CR_BER 3 -#define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_STM32_H7Ax ? 5 : 7) -#define FLASH_H7_CR_SNB 8 -#define FLASH_H7_CR_SNB_MASK 0x700 - -#define FLASH_H7_SR_QW 2 -#define FLASH_H7_SR_WRPERR 17 -#define FLASH_H7_SR_PGSERR 18 -#define FLASH_H7_SR_STRBERR 19 -#define FLASH_H7_SR_ERROR_MASK \ - ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ - (1 << FLASH_H7_SR_WRPERR)) - -#define FLASH_H7_OPTCR_OPTLOCK 0 -#define FLASH_H7_OPTCR_OPTSTART 1 -#define FLASH_H7_OPTCR_MER 4 - -#define FLASH_H7_OPTSR_OPT_BUSY 0 -#define FLASH_H7_OPTSR_OPTCHANGEERR 30 - -#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 - -#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) -#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) -#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) -#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) -#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) -#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) -#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) -#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) -#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) -#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) -#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) -#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) -#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) -#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) -#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) - -#define STM32F0_DBGMCU_CR 0xE0042004 -#define STM32F0_DBGMCU_CR_IWDG_STOP 8 -#define STM32F0_DBGMCU_CR_WWDG_STOP 9 - -#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 -#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 -#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 - -#define STM32L0_DBGMCU_APB1_FZ 0x40015808 -#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 -#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 - -#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 -#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 - -#define STM32WB_DBGMCU_APB1FZR1 0xE004203C -#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 -#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 - -#define STM32F1_RCC_AHBENR 0x40021014 -#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32F4_RCC_AHB1ENR 0x40023830 -#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN - -#define STM32G0_RCC_AHBENR 0x40021038 -#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32G4_RCC_AHB1ENR 0x40021048 -#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32L0_RCC_AHBENR 0x40021030 -#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN - -#define STM32H7_RCC_AHB1ENR 0x58024538 -#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32WB_RCC_AHB1ENR 0x58000048 -#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define L1_WRITE_BLOCK_SIZE 0x80 -#define L0_WRITE_BLOCK_SIZE 0x40 + // Endianness // https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html @@ -441,16 +64,16 @@ uint16_t read_uint16(const unsigned char *c, const int pt) { static uint32_t get_stm32l0_flash_base(stlink_t *sl) { switch (sl->chip_id) { - case STM32_CHIPID_STM32_L0: - case STM32_CHIPID_STM32_L0_CAT5: - case STM32_CHIPID_STM32_L0_CAT2: - case STM32_CHIPID_STM32_L011: + case STM32_CHIPID_L0: + case STM32_CHIPID_L0_CAT5: + case STM32_CHIPID_L0_CAT2: + case STM32_CHIPID_L011: return (STM32L0_FLASH_REGS_ADDR); - case STM32_CHIPID_STM32_L1_CAT2: - case STM32_CHIPID_STM32_L1_MD: - case STM32_CHIPID_STM32_L1_MD_PLUS: - case STM32_CHIPID_STM32_L1_MD_PLUS_HD: + case STM32_CHIPID_L1_CAT2: + case STM32_CHIPID_L1_MD: + case STM32_CHIPID_L1_MD_PLUS: + case STM32_CHIPID_L1_MD_PLUS_HD: return (STM32L_FLASH_REGS_ADDR); default: @@ -1622,14 +1245,14 @@ int stlink_load_device_params(stlink_t *sl) { flash_size = flash_size & 0xffff; - if ((sl->chip_id == STM32_CHIPID_STM32_L1_MD || - sl->chip_id == STM32_CHIPID_STM32_F1_VL_MD_LD || - sl->chip_id == STM32_CHIPID_STM32_L1_MD_PLUS) && + if ((sl->chip_id == STM32_CHIPID_L1_MD || + sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_L1_MD_PLUS) && (flash_size == 0)) { sl->flash_size = 128 * 1024; - } else if (sl->chip_id == STM32_CHIPID_STM32_L1_CAT2) { + } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_STM32_L1_MD_PLUS_HD) { + } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_MD_PLUS_HD) { // 0 is 384k and 1 is 256k if (flash_size == 0) { sl->flash_size = 384 * 1024; @@ -1651,12 +1274,12 @@ int stlink_load_device_params(stlink_t *sl) { // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STM32_CHIPID_STM32_F1_VL_MD_LD && + if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { sl->sram_size = 0x1000; } - if (sl->chip_id == STM32_CHIPID_STM32_G4_CAT3) { + if (sl->chip_id == STM32_CHIPID_G4_CAT3) { uint32_t flash_optr; stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); @@ -2706,9 +2329,9 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); flashaddr -= STM32_FLASH_BASE; - if (sl->chip_id == STM32_CHIPID_STM32_L4 || - sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x || - sl->chip_id == STM32_CHIPID_STM32_L4Rx) { + if (sl->chip_id == STM32_CHIPID_L4 || + sl->chip_id == STM32_CHIPID_L496x_L4A6x || + sl->chip_id == STM32_CHIPID_L4Rx) { // this chip use dual banked flash if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { uint32_t banksize = (uint32_t)sl->flash_size / 2; @@ -2726,16 +2349,16 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { } uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { - if ((sl->chip_id == STM32_CHIPID_STM32_F2) || - (sl->chip_id == STM32_CHIPID_STM32_F4) || - (sl->chip_id == STM32_CHIPID_STM32_F4_DE) || - (sl->chip_id == STM32_CHIPID_STM32_F4_LP) || - (sl->chip_id == STM32_CHIPID_STM32_F4_HD) || - (sl->chip_id == STM32_CHIPID_STM32_F411xx) || - (sl->chip_id == STM32_CHIPID_STM32_F446) || - (sl->chip_id == STM32_CHIPID_STM32_F4_DSI) || - (sl->chip_id == STM32_CHIPID_STM32_F72xxx) || - (sl->chip_id == STM32_CHIPID_STM32_F412)) { + if ((sl->chip_id == STM32_CHIPID_F2) || + (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || + (sl->chip_id == STM32_CHIPID_F4_HD) || + (sl->chip_id == STM32_CHIPID_F411xx) || + (sl->chip_id == STM32_CHIPID_F446) || + (sl->chip_id == STM32_CHIPID_F4_DSI) || + (sl->chip_id == STM32_CHIPID_F72xxx) || + (sl->chip_id == STM32_CHIPID_F412)) { uint32_t sector = calculate_F4_sectornum(flashaddr); if (sector >= 12) { @@ -2749,8 +2372,8 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { } else { sl->flash_pgsz = 0x20000; } - } else if (sl->chip_id == STM32_CHIPID_STM32_F7 || - sl->chip_id == STM32_CHIPID_STM32_F76xxx) { + } else if (sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx) { uint32_t sector = calculate_F7_sectornum(flashaddr); if (sector < 4) { @@ -2785,11 +2408,11 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { unlock_flash_if(sl); // select the page to erase - if ((sl->chip_id == STM32_CHIPID_STM32_L4) || - (sl->chip_id == STM32_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STM32_CHIPID_STM32_L45x_L46x) || - (sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x) || - (sl->chip_id == STM32_CHIPID_STM32_L4Rx)) { + if ((sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_L45x_L46x) || + (sl->chip_id == STM32_CHIPID_L496x_L4A6x) || + (sl->chip_id == STM32_CHIPID_L4Rx)) { // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); @@ -2797,8 +2420,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STM32_CHIPID_STM32_F7 || - sl->chip_id == STM32_CHIPID_STM32_F76xxx) { + } else if (sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx) { // calculate the actual page from the address uint32_t sector = calculate_F7_sectornum(flashaddr); @@ -2982,7 +2605,7 @@ int stlink_erase_flash_mass(stlink_t *sl) { unlock_flash_if(sl); if (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_id != STM32_CHIPID_STM32_H7Ax) { + sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -3260,7 +2883,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { set_flash_cr_pg(sl, BANK_2); } - if (sl->chip_id != STM32_CHIPID_STM32_H7Ax) { + if (sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -4357,17 +3980,17 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->chip_id) { - case STM32_CHIPID_STM32_F2: + case STM32_CHIPID_F2: return stlink_read_option_bytes_f2(sl, option_byte); - case STM32_CHIPID_STM32_F4: - case STM32_CHIPID_STM32_F446: + case STM32_CHIPID_F4: + case STM32_CHIPID_F446: return stlink_read_option_bytes_f4(sl, option_byte); - case STM32_CHIPID_STM32_F76xxx: + case STM32_CHIPID_F76xxx: return stlink_read_option_bytes_f7(sl, option_byte); - case STM32_CHIPID_STM32_G0_CAT1: - case STM32_CHIPID_STM32_G0_CAT2: - case STM32_CHIPID_STM32_G4_CAT2: - case STM32_CHIPID_STM32_G4_CAT3: + case STM32_CHIPID_G0_CAT1: + case STM32_CHIPID_G0_CAT2: + case STM32_CHIPID_G4_CAT2: + case STM32_CHIPID_G4_CAT3: return stlink_read_option_bytes_Gx(sl, option_byte); default: return stlink_read_option_bytes_generic(sl, option_byte); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 19819a6cb..2b6875d9f 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -553,39 +553,39 @@ char* make_memory_map(stlink_t *sl) { char* map = malloc(sz); map[0] = '\0'; - if (sl->chip_id == STM32_CHIPID_STM32_F4 || - sl->chip_id == STM32_CHIPID_STM32_F446 || - sl->chip_id == STM32_CHIPID_STM32_F411xx) { + if (sl->chip_id == STM32_CHIPID_F4 || + sl->chip_id == STM32_CHIPID_F446 || + sl->chip_id == STM32_CHIPID_F411xx) { strcpy(map, memory_map_template_F4); - } else if (sl->chip_id == STM32_CHIPID_STM32_F4_DE) { + } else if (sl->chip_id == STM32_CHIPID_F4_DE) { strcpy(map, memory_map_template_F4_DE); } else if (sl->core_id == STM32_CORE_ID_M7_F7) { snprintf(map, sz, memory_map_template_F7, (unsigned int)sl->sram_size); - } else if (sl->chip_id == STM32_CHIPID_STM32_H74xxx) { + } else if (sl->chip_id == STM32_CHIPID_H74xxx) { snprintf(map, sz, memory_map_template_H7, (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); - } else if (sl->chip_id == STM32_CHIPID_STM32_F4_HD) { + } else if (sl->chip_id == STM32_CHIPID_F4_HD) { strcpy(map, memory_map_template_F4_HD); - } else if (sl->chip_id == STM32_CHIPID_STM32_F2) { + } else if (sl->chip_id == STM32_CHIPID_F2) { snprintf(map, sz, memory_map_template_F2, (unsigned int)sl->flash_size, (unsigned int)sl->sram_size, (unsigned int)sl->flash_size - 0x20000, (unsigned int)sl->sys_base, (unsigned int)sl->sys_size); - } else if ((sl->chip_id == STM32_CHIPID_STM32_L4) || - (sl->chip_id == STM32_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STM32_CHIPID_STM32_L45x_L46x)) { + } else if ((sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_L45x_L46x)) { snprintf(map, sz, memory_map_template_L4, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x) { + } else if (sl->chip_id == STM32_CHIPID_L496x_L4A6x) { snprintf(map, sz, memory_map_template_L496, (unsigned int)sl->flash_size, (unsigned int)sl->flash_size); - } else if (sl->chip_id == STM32_CHIPID_STM32_H72x) { + } else if (sl->chip_id == STM32_CHIPID_H72x) { snprintf(map, sz, memory_map_template_H72x3x, (unsigned int)sl->flash_size, (unsigned int)sl->flash_pgsz); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 78233ec1c..c8147229b 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -9,18 +9,6 @@ #include -// struct stlink_chipid_params *stlink_chipid_get_params_old(uint32_t chipid) { -// struct stlink_chipid_params *params = NULL; - -// for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) -// if (devices[n].chip_id == chipid) { -// params = &devices[n]; -// break; -// } - -// return (params); -// } - static struct stlink_chipid_params *devicelist; void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { @@ -39,22 +27,6 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { fprintf(fp, "flags %d\n\n", dev->flags); } -// static int chipid_params_eq(const struct stlink_chipid_params *p1, const struct stlink_chipid_params *p2) -// { -// return p1->chip_id == p2->chip_id && -// p1->dev_type && p2->dev_type && -// strcmp(p1->dev_type, p2->dev_type) == 0 && -// p1->flash_type == p2->flash_type && -// p1->flash_size_reg == p2->flash_size_reg && -// p1->flash_pagesize == p2->flash_pagesize && -// p1->sram_size == p2->sram_size && -// p1->bootrom_base == p2->bootrom_base && -// p1->bootrom_size == p2->bootrom_size && -// p1->option_base == p2->option_base && -// p1->option_size == p2->option_size && -// p1->flags == p2->flags; -// } - struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { struct stlink_chipid_params *params = NULL; // struct stlink_chipid_params *p2; @@ -65,20 +37,6 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { break; } -// p2 = stlink_chipid_get_params_old(chipid); - -// #if 1 -// if (params == NULL) { -// params = p2; -// } else if (!chipid_params_eq(params, p2)) { -// // fprintf (stderr, "Error, chipid params not identical\n"); -// // return NULL; -// fprintf(stderr, "---------- old ------------\n"); -// dump_a_chip(stderr, p2); -// fprintf(stderr, "---------- new ------------\n"); -// dump_a_chip(stderr, params); -// } -// #endif return(params); } @@ -187,38 +145,6 @@ void process_chipfile(char *fname) { devicelist = ts; } -// void dump_chips (void) { -// struct stlink_chipid_params *ts; -// char *p, buf[100]; -// FILE *fp; - -// for (size_t n = 0; n < STLINK_ARRAY_SIZE(devices); n++) { -// ts = &devices[n]; - -// strcpy(buf, ts->dev_type); - -// while ((p = strchr(buf, '/'))) // change slashes to underscore. -// *p = '_'; - -// strcat(buf, ".chip"); -// fp = fopen(buf, "w"); -// fprintf(fp, "# Device Type: %s\n", ts->dev_type); -// fprintf(fp, "# Reference Manual: RM%s\n", ts->ref_manual_id); -// fprintf(fp, "#\n"); -// fprintf(fp, "chip_id %x\n", ts->chip_id); -// fprintf(fp, "flash_type %x\n", ts->flash_type); -// fprintf(fp, "flash_size_reg %x\n", ts->flash_size_reg); -// fprintf(fp, "flash_pagesize %x\n", ts->flash_pagesize); -// fprintf(fp, "sram_size %x\n", ts->sram_size); -// fprintf(fp, "bootrom_base %x\n", ts->bootrom_base); -// fprintf(fp, "bootrom_size %x\n", ts->bootrom_size); -// fprintf(fp, "option_base %x\n", ts->option_base); -// fprintf(fp, "option_size %x\n", ts->option_size); -// fprintf(fp, "flags %x\n\n", ts->flags); -// fclose(fp); -// } -// } - #if defined(STLINK_HAVE_DIRENT_H) #include void init_chipids(char *dir_to_scan) { diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 86cd49ddb..8efcd653e 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -4,9 +4,6 @@ #include #include -#ifdef __cplusplus -extern "C" { -#endif /** Chipid parametres */ struct stlink_chipid_params { @@ -28,8 +25,5 @@ struct stlink_chipid_params { struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); void init_chipids(char *dir_to_scan); -#ifdef __cplusplus -} -#endif #endif // STLINK_CHIPID_H_ diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index ad52d6567..92b6f0f4b 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -234,43 +234,43 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* const uint8_t* loader_code; size_t loader_size; - if (sl->chip_id == STM32_CHIPID_STM32_L1_MD || - sl->chip_id == STM32_CHIPID_STM32_L1_CAT2 || - sl->chip_id == STM32_CHIPID_STM32_L1_MD_PLUS || - sl->chip_id == STM32_CHIPID_STM32_L1_MD_PLUS_HD || - sl->chip_id == STM32_CHIPID_STM32_L152_RE || - sl->chip_id == STM32_CHIPID_STM32_L011 || - sl->chip_id == STM32_CHIPID_STM32_L0 || - sl->chip_id == STM32_CHIPID_STM32_L0_CAT5 || - sl->chip_id == STM32_CHIPID_STM32_L0_CAT2) { + if (sl->chip_id == STM32_CHIPID_L1_MD || + sl->chip_id == STM32_CHIPID_L1_CAT2 || + sl->chip_id == STM32_CHIPID_L1_MD_PLUS || + sl->chip_id == STM32_CHIPID_L1_MD_PLUS_HD || + sl->chip_id == STM32_CHIPID_L152_RE || + sl->chip_id == STM32_CHIPID_L011 || + sl->chip_id == STM32_CHIPID_L0 || + sl->chip_id == STM32_CHIPID_L0_CAT5 || + sl->chip_id == STM32_CHIPID_L0_CAT2) { loader_code = loader_code_stm32lx; loader_size = sizeof(loader_code_stm32lx); } else if (sl->core_id == STM32_CORE_ID_M3_F1 || - sl->chip_id == STM32_CHIPID_STM32_F1_MD || - sl->chip_id == STM32_CHIPID_STM32_F1_HD || - sl->chip_id == STM32_CHIPID_STM32_F1_LD || - sl->chip_id == STM32_CHIPID_STM32_F1_VL_MD_LD || - sl->chip_id == STM32_CHIPID_STM32_F1_VL_HD || - sl->chip_id == STM32_CHIPID_STM32_F1_XLD || - sl->chip_id == STM32_CHIPID_STM32_F1_CONN || - sl->chip_id == STM32_CHIPID_STM32_F3 || - sl->chip_id == STM32_CHIPID_STM32_F3xx_SMALL || - sl->chip_id == STM32_CHIPID_STM32_F303_HD || - sl->chip_id == STM32_CHIPID_STM32_F37x || - sl->chip_id == STM32_CHIPID_STM32_F334) { + sl->chip_id == STM32_CHIPID_F1_MD || + sl->chip_id == STM32_CHIPID_F1_HD || + sl->chip_id == STM32_CHIPID_F1_LD || + sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_F1_VL_HD || + sl->chip_id == STM32_CHIPID_F1_XLD || + sl->chip_id == STM32_CHIPID_F1_CONN || + sl->chip_id == STM32_CHIPID_F3 || + sl->chip_id == STM32_CHIPID_F3xx_SMALL || + sl->chip_id == STM32_CHIPID_F303_HD || + sl->chip_id == STM32_CHIPID_F37x || + sl->chip_id == STM32_CHIPID_F334) { loader_code = loader_code_stm32vl; loader_size = sizeof(loader_code_stm32vl); - } else if (sl->chip_id == STM32_CHIPID_STM32_F2 || - sl->chip_id == STM32_CHIPID_STM32_F4 || - sl->chip_id == STM32_CHIPID_STM32_F4_DE || - sl->chip_id == STM32_CHIPID_STM32_F4_LP || - sl->chip_id == STM32_CHIPID_STM32_F4_HD || - sl->chip_id == STM32_CHIPID_STM32_F4_DSI || - sl->chip_id == STM32_CHIPID_STM32_F410 || - sl->chip_id == STM32_CHIPID_STM32_F411xx || - sl->chip_id == STM32_CHIPID_STM32_F412 || - sl->chip_id == STM32_CHIPID_STM32_F413 || - sl->chip_id == STM32_CHIPID_STM32_F446) { + } else if (sl->chip_id == STM32_CHIPID_F2 || + sl->chip_id == STM32_CHIPID_F4 || + sl->chip_id == STM32_CHIPID_F4_DE || + sl->chip_id == STM32_CHIPID_F4_LP || + sl->chip_id == STM32_CHIPID_F4_HD || + sl->chip_id == STM32_CHIPID_F4_DSI || + sl->chip_id == STM32_CHIPID_F410 || + sl->chip_id == STM32_CHIPID_F411xx || + sl->chip_id == STM32_CHIPID_F412 || + sl->chip_id == STM32_CHIPID_F413 || + sl->chip_id == STM32_CHIPID_F446) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, @@ -279,9 +279,9 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* if (retval == -1) { return(retval); } } else if (sl->core_id == STM32_CORE_ID_M7_F7 || - sl->chip_id == STM32_CHIPID_STM32_F7 || - sl->chip_id == STM32_CHIPID_STM32_F76xxx || - sl->chip_id == STM32_CHIPID_STM32_F72xxx) { + sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx || + sl->chip_id == STM32_CHIPID_F72xxx) { int retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, @@ -289,19 +289,19 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code_stm32f7_lv, sizeof(loader_code_stm32f7_lv)); if (retval == -1) { return(retval); } - } else if (sl->chip_id == STM32_CHIPID_STM32_F0 || - sl->chip_id == STM32_CHIPID_STM32_F04 || - sl->chip_id == STM32_CHIPID_STM32_F0_CAN || - sl->chip_id == STM32_CHIPID_STM32_F0xx_SMALL || - sl->chip_id == STM32_CHIPID_STM32_F09x) { + } else if (sl->chip_id == STM32_CHIPID_F0 || + sl->chip_id == STM32_CHIPID_F04 || + sl->chip_id == STM32_CHIPID_F0_CAN || + sl->chip_id == STM32_CHIPID_F0xx_SMALL || + sl->chip_id == STM32_CHIPID_F09x) { loader_code = loader_code_stm32f0; loader_size = sizeof(loader_code_stm32f0); - } else if ((sl->chip_id == STM32_CHIPID_STM32_L4) || - (sl->chip_id == STM32_CHIPID_STM32_L41x_L42x) || - (sl->chip_id == STM32_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STM32_CHIPID_STM32_L45x_L46x) || - (sl->chip_id == STM32_CHIPID_STM32_L4Rx) || - (sl->chip_id == STM32_CHIPID_STM32_L496x_L4A6x)) { + } else if ((sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_L41x_L42x) || + (sl->chip_id == STM32_CHIPID_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_L45x_L46x) || + (sl->chip_id == STM32_CHIPID_L4Rx) || + (sl->chip_id == STM32_CHIPID_L496x_L4A6x)) { loader_code = loader_code_stm32l4; loader_size = sizeof(loader_code_stm32l4); } else { diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 29fd5b068..bac99bdb4 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -12,16 +12,10 @@ #include -#ifdef __cplusplus -extern "C" { -#endif int stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); -#ifdef __cplusplus -} -#endif #endif // STLINK_FLASH_LOADER_H_ diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index f34b2e122..4161d3967 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -9,9 +9,6 @@ #include #include -#ifdef __cplusplus -extern "C" { -#endif /* Device access */ #define RDWR 0 @@ -60,8 +57,5 @@ struct stlink_libsg { stlink_t* stlink_v1_open(const int verbose, int reset); -#ifdef __cplusplus -} -#endif #endif // STLINK_SG_H diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index c6b71ba4e..d04ef2dca 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -12,9 +12,6 @@ #include #include "logging.h" -#ifdef __cplusplus -extern "C" { -#endif #define STLINK_USB_VID_ST 0x0483 #define STLINK_USB_PID_STLINK 0x3744 @@ -73,8 +70,5 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); -#ifdef __cplusplus -} -#endif #endif // STLINK_USB_H diff --git a/src/win32/mmap.h b/src/win32/mmap.h index 1f2e756cb..67558b0cc 100644 --- a/src/win32/mmap.h +++ b/src/win32/mmap.h @@ -13,16 +13,10 @@ #define MAP_ANONYMOUS (1 << 5) #define MAP_FAILED ((void *)-1) -#ifdef __cplusplus -extern "C" { -#endif void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); int munmap(void *addr, size_t len); -#ifdef __cplusplus -} -#endif #endif /* HAVE_SYS_MMAN_H */ diff --git a/src/win32/sys_time.h b/src/win32/sys_time.h index 39f97f739..3f35390c3 100644 --- a/src/win32/sys_time.h +++ b/src/win32/sys_time.h @@ -12,15 +12,8 @@ struct timezone { int tz_dsttime; }; -#ifdef __cplusplus -extern "C" { -#endif - int gettimeofday(struct timeval *tv, struct timezone *tz); -#ifdef __cplusplus -} -#endif #endif /* STLINK_HAVE_SYS_TIME_H */ From a5d644160b071fb0ef8f79d38043a3c1299ee750 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 16 Jan 2022 20:28:53 +0100 Subject: [PATCH 1288/1435] Fixed define names and removed old include. --- src/common.c | 4 ++-- src/stlink-lib/chipid.c | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/common.c b/src/common.c index 1a6c89c63..08f2c5dc1 100644 --- a/src/common.c +++ b/src/common.c @@ -2645,8 +2645,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { int err = 0; // TODO: User MER bit to mass-erase WB series. - if (sl->flash_type == STLINK_FLASH_TYPE_L0_L1 || - sl->flash_type == STLINK_FLASH_TYPE_WB_WL) { + if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || + sl->flash_type == STM32_FLASH_TYPE_WB_WL) { err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index c8147229b..dbfd2882d 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,6 +1,5 @@ #include #include "chipid.h" -//#include "chipid_db_old.h" #include #include From 80b05c547e34a214ffd9171e600051e8474a9f0a Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 17 Jan 2022 00:39:57 +0100 Subject: [PATCH 1289/1435] Updated MCU core-ids --- inc/stm32.h | 52 +++++++++++++++++++++++++---------- src/common.c | 2 +- src/st-util/gdb-server.c | 2 +- src/stlink-lib/flash_loader.c | 4 +-- 4 files changed, 42 insertions(+), 18 deletions(-) diff --git a/inc/stm32.h b/inc/stm32.h index 2e8ed6889..56176bd6f 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -7,20 +7,44 @@ #ifndef STM32_H #define STM32_H -/* Cortex-M core ids (CPUTAPID) */ -#define STM32_CORE_ID_M3_F2_JTAG 0x0ba00477 // unused // F2 JTAG (RM0033 p.1326) -//#define STM32_CORE_ID_M33_JTAG 0x0ba04477 // unused // L5 JTAG -#define STM32_CORE_ID_M0 0x0bb11477 // unused // F0 -#define STM32_CORE_ID_M0P 0x0bc11477 // unused // L0, G0 -#define STM32_CORE_ID_M33 0x0be01477 // unused // L5 SWD (RM0351 p.2029) -#define STM32_CORE_ID_M33_JTAG 0x0be02477 // unused // L5 JTAG (RM0438 p.2029) -#define STM32_CORE_ID_M3_F1 0x1ba01477 // F1 (RM0008 p.1092) -#define STM32_CORE_ID_M4F_L4 0x1ba01477 // unused // L4 (RM0351 p.1845) -#define STM32_CORE_ID_M4F_F4 0x2ba01477 // unused // F4 (RM0090 p.1695) -#define STM32_CORE_ID_M4F_F4_JTAG 0x4ba00477 // unused // F4 JTAG (RM090 p.1691) -#define STM32_CORE_ID_M7_F7 0x5ba02477 // F7 -#define STM32_CORE_ID_M7_H7 0x6ba02477 // H7 -#define STM32_CORE_ID_M7_H7_JTAG 0x6ba00477 // H7 JTAG (RM0433 p.3065) +/* STM32 Cortex-M core ids (CPUTAPID) */ +#define STM32_CORE_ID_M0_SWD 0x0bb11477 // (RM0091 Section 32.5.3) F0 SW-DP + // (RM0444 Section 40.5.3) G0 SW-DP + +#define STM32_CORE_ID_M0P_SWD 0x0bc11477 // (RM0385 Section 27.5.3) L0 SW-DP + +#define STM32_CORE_ID_M3_r1p1_SWD 0x1ba01477 // (RM0008 Section 31.8.3) F1 SW-DP +#define STM32_CORE_ID_M3_r1p1_JTAG 0x3ba00477 // (RM0008 Section 31.6.3) F1 JTAG + +#define STM32_CORE_ID_M3_r2p0_SWD 0x2ba01477 // (RM0033 Section 32.8.3) F2 SW-DP + // (RM0038 Section 30.8.3) L1 SW-DP +#define STM32_CORE_ID_M3_r2p0_JTAG 0x0ba00477 // (RM0033 Section 32.6.3) F2 JTAG + // (RM0038 Section 30.6.2) L1 JTAG + +#define STM32_CORE_ID_M4_r0p1_SWD 0x1ba01477 // (RM0316 Section 33.8.3) F3 SW-DP + // (RM0351 Section 48.8.3) L4 SW-DP + // (RM0432 Section 57.8.3) L4+ SW-DP +#define STM32_CORE_ID_M4_r0p1_JTAG 0x4ba00477 // (RM0316 Section 33.6.3) F3 JTAG + // (RM0351 Section 48.6.3) L4 JTAG + // (RM0432 Section 57.6.3) L4+ JTAG + +#define STM32_CORE_ID_M4F_r0p1_SWD 0x2ba01477 // (RM0090 Section 38.8.3) F4 SW-DP + // (RM0090 Section 47.8.3) G4 SW-DP +#define STM32_CORE_ID_M4F_r0p1_JTAG 0x4ba00477 // (RM0090 Section 38.6.3) F4 JTAG + // (RM0090 Section 47.6.3) G4 JTAG + +#define STM32_CORE_ID_M7F_SWD 0x5ba02477 // (RM0385 Section 40.8.3) F7 SW-DP +#define STM32_CORE_ID_M7F_JTAG 0x5ba00477 // (RM0385 Section 40.6.3) F7 JTAG + +#define STM32_CORE_ID_M7F_H7_SWD 0x6ba02477 // (RM0433 Section 60.4.1) H7 SW-DP +#define STM32_CORE_ID_M7F_H7_JTAG 0x6ba00477 // (RM0433 Section 60.4.1) H7 JTAG + +#define STM32_CORE_ID_M33_SWD 0x0be02477 // (RM0438 Section 52.2.10) L5 SW-DP + // (RM0456 Section 65.3.3) U5 SW-DP +#define STM32_CORE_ID_M33_JTAGD 0x0be01477 // (RM0438 Section 52.2.10) L5 JTAG-DP + // (RM0456 Section 65.3.3) U5 JTAG-DP +#define STM32_CORE_ID_M33_JTAG 0x0ba04477 // (RM0438 Section 52.2.8) L5 JTAG + // (RM0456 Section 56.3.1) U5 JTAG /* STM32 flash types */ // New flash type definitions must go before STM32_FLASH_TYPE_UNDEFINED diff --git a/src/common.c b/src/common.c index 08f2c5dc1..266722b91 100644 --- a/src/common.c +++ b/src/common.c @@ -1137,7 +1137,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * */ - if ((sl->core_id == STM32_CORE_ID_M7_H7 || sl->core_id == STM32_CORE_ID_M7_H7_JTAG) && + if ((sl->core_id == STM32_CORE_ID_M7F_H7_SWD || sl->core_id == STM32_CORE_ID_M7F_H7_JTAG) && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 2b6875d9f..4f7a1fe2e 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -559,7 +559,7 @@ char* make_memory_map(stlink_t *sl) { strcpy(map, memory_map_template_F4); } else if (sl->chip_id == STM32_CHIPID_F4_DE) { strcpy(map, memory_map_template_F4_DE); - } else if (sl->core_id == STM32_CORE_ID_M7_F7) { + } else if (sl->core_id == STM32_CORE_ID_M7F_SWD) { snprintf(map, sz, memory_map_template_F7, (unsigned int)sl->sram_size); } else if (sl->chip_id == STM32_CHIPID_H74xxx) { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 92b6f0f4b..2b47c1114 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -245,7 +245,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STM32_CHIPID_L0_CAT2) { loader_code = loader_code_stm32lx; loader_size = sizeof(loader_code_stm32lx); - } else if (sl->core_id == STM32_CORE_ID_M3_F1 || + } else if (sl->core_id == STM32_CORE_ID_M3_r1p1_SWD || sl->chip_id == STM32_CHIPID_F1_MD || sl->chip_id == STM32_CHIPID_F1_HD || sl->chip_id == STM32_CHIPID_F1_LD || @@ -278,7 +278,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* loader_code_stm32f4_lv, sizeof(loader_code_stm32f4_lv)); if (retval == -1) { return(retval); } - } else if (sl->core_id == STM32_CORE_ID_M7_F7 || + } else if (sl->core_id == STM32_CORE_ID_M7F_SWD || sl->chip_id == STM32_CHIPID_F7 || sl->chip_id == STM32_CHIPID_F76xxx || sl->chip_id == STM32_CHIPID_F72xxx) { From e5ff479d4829843d04fe51931256ac095ad4c0b8 Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Thu, 20 Jan 2022 12:54:14 +0400 Subject: [PATCH 1290/1435] #1216 refactoring of common.c File divided to some parts. Functions with "flash" in names extracted to common_flash.c, with "option" extracted to option.c etc. Removed unnecessary headers. Removed one single function which was used nowhere. And so on. Project built under Windows and seems to be working. --- CMakeLists.txt | 10 +- inc/stlink.h | 6 +- inc/stm32flash.h | 340 +++++++++++ src/calculate.c | 74 +++ src/calculate.h | 15 + src/common.h | 15 + src/common_flash.c | 1374 ++++++++++++++++++++++++++++++++++++++++++++ src/common_flash.h | 27 + src/flashloader.c | 481 ++++++++++++++++ src/map_file.c | 57 ++ src/map_file.h | 28 + src/option.c | 1026 +++++++++++++++++++++++++++++++++ src/read_write.c | 142 +++++ 13 files changed, 3592 insertions(+), 3 deletions(-) create mode 100644 inc/stm32flash.h create mode 100644 src/calculate.c create mode 100644 src/calculate.h create mode 100644 src/common.h create mode 100644 src/common_flash.c create mode 100644 src/common_flash.h create mode 100644 src/flashloader.c create mode 100644 src/map_file.c create mode 100644 src/map_file.h create mode 100644 src/option.c create mode 100644 src/read_write.c diff --git a/CMakeLists.txt b/CMakeLists.txt index 66bf34e3e..a3338df71 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,7 +2,7 @@ # General cmake settings ### -cmake_minimum_required(VERSION 3.10.2) +cmake_minimum_required(VERSION 3.7.2) cmake_policy(SET CMP0042 NEW) set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) @@ -110,6 +110,8 @@ add_subdirectory(inc) set(STLINK_HEADERS inc/backend.h inc/stlink.h + src/common_flash.h + src/calculate.h src/stlink-lib/commands.h src/stlink-lib/libusb_settings.h src/stlink-lib/reg.h @@ -123,7 +125,13 @@ set(STLINK_HEADERS ) set(STLINK_SOURCE + src/read_write.c src/common.c + src/option.c + src/common_flash.c + src/map_file.c + src/flashloader.c + src/calculate.c src/stlink-lib/chipid.c src/stlink-lib/flash_loader.c src/stlink-lib/logging.c diff --git a/inc/stlink.h b/inc/stlink.h index df13aa7c9..a8a52458d 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -1,3 +1,4 @@ + /* * File: stlink.h * @@ -13,6 +14,7 @@ #include #include "stm32.h" +#include "stm32flash.h" #ifdef __cplusplus extern "C" { @@ -284,7 +286,7 @@ int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_ int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); -int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); +//int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); @@ -292,7 +294,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); uint16_t read_uint16(const unsigned char *c, const int pt); -void stlink_core_stat(stlink_t *sl); +//void stlink_core_stat(stlink_t *sl); void stlink_print_data(stlink_t *sl); unsigned int is_bigendian(void); uint32_t read_uint32(const unsigned char *c, const int pt); diff --git a/inc/stm32flash.h b/inc/stm32flash.h new file mode 100644 index 000000000..01c76946c --- /dev/null +++ b/inc/stm32flash.h @@ -0,0 +1,340 @@ +#ifndef STM32FLASH_H +#define STM32FLASH_H + +/* stm32f FPEC flash controller interface, pm0063 manual */ +// TODO - all of this needs to be abstracted out.... +// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, +// August 2012) +#define FLASH_REGS_ADDR 0x40022000 +#define FLASH_REGS_SIZE 0x28 + +#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) +#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) +#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) +#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) +#define FLASH_CR (FLASH_REGS_ADDR + 0x10) +#define FLASH_AR (FLASH_REGS_ADDR + 0x14) +#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) +#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) + +// STM32F10x_XL has two flash memory banks with separate registers to control +// the second bank. +#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) +#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) +#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) +#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) + +// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... +#define FLASH_RDPTR_KEY 0x00a5 +#define FLASH_KEY1 0x45670123 +#define FLASH_KEY2 0xcdef89ab + +#define FLASH_L0_PRGKEY1 0x8c9daebf +#define FLASH_L0_PRGKEY2 0x13141516 + +#define FLASH_L0_PEKEY1 0x89abcdef +#define FLASH_L0_PEKEY2 0x02030405 + +#define FLASH_OPTKEY1 0x08192A3B +#define FLASH_OPTKEY2 0x4C5D6E7F + +#define FLASH_F0_OPTKEY1 0x45670123 +#define FLASH_F0_OPTKEY2 0xCDEF89AB + +#define FLASH_L0_OPTKEY1 0xFBEAD9C8 +#define FLASH_L0_OPTKEY2 0x24252627 + +#define FLASH_SR_BSY 0 +#define FLASH_SR_PG_ERR 2 +#define FLASH_SR_WRPRT_ERR 4 +#define FLASH_SR_EOP 5 + +#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) + +#define FLASH_CR_PG 0 +#define FLASH_CR_PER 1 +#define FLASH_CR_MER 2 +#define FLASH_CR_OPTPG 4 +#define FLASH_CR_OPTER 5 +#define FLASH_CR_STRT 6 +#define FLASH_CR_LOCK 7 +#define FLASH_CR_OPTWRE 9 +#define FLASH_CR_OBL_LAUNCH 13 + +#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) +#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) +#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) +#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) +#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) +#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) +#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) +#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) +#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) +#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) +#define FLASH_L1_FPRG 10 +#define FLASH_L1_PROG 3 + +// Flash registers common to STM32G0 and STM32G4 series. +#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) +#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) +#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) +#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) +#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) +#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) +#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) + +// G0 (RM0444 Table 1, sec 3.7) +// Mostly the same as G4 chips, but the notation +// varies a bit after the 'OPTR' register. +#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) +#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) +#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) +#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) +#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) +#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) +#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) +#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) + +// G4 (RM0440 Table 17, sec 3.7.19) +// Mostly the same as STM32G0 chips, but there are a few extra +// registers because 'cat 3' devices can have two Flash banks. +#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) +#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) +#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) +#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) +#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) +#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) +#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) +#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) +#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) +#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) +#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) +#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) + +// G0/G4 FLASH control register +#define STM32Gx_FLASH_CR_PG (0) /* Program */ +#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ +#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ +#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ +#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ +#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ +#define STM32Gx_FLASH_CR_STRT (16) /* Start */ +#define STM32Gx_FLASH_CR_OPTSTRT \ + (17) /* Start of modification of option bytes */ +#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ +#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ +#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ +#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ +#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ + +// G0/G4 FLASH status register +#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) +#define STM32Gx_FLASH_SR_PROGERR (3) +#define STM32Gx_FLASH_SR_WRPERR (4) +#define STM32Gx_FLASH_SR_PGAERR (5) +#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ +#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ + +// G4 FLASH option register +#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ + +// WB (RM0434) +#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) +#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) +#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) +#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) +#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) +#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) +#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) +#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) +#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) +#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) +#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) +#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) +#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) +#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) +#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) +#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) +#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) +#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) +#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) +#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) + +// WB Flash control register. +#define STM32WB_FLASH_CR_STRT (16) /* Start */ +#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ +#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ +// WB Flash status register. +#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ +#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ +#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ +#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ +#define STM32WB_FLASH_SR_BSY (16) /* Busy */ + +// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) +#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) +#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) +#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) +#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) +#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) + +#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ +#define STM32L4_FLASH_SR_PROGERR 3 +#define STM32L4_FLASH_SR_WRPERR 4 +#define STM32L4_FLASH_SR_PGAERR 5 +#define STM32L4_FLASH_SR_BSY 16 + +#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ +#define STM32L4_FLASH_CR_PG 0 /* Program */ +#define STM32L4_FLASH_CR_PER 1 /* Page erase */ +#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ +#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ +#define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ +#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ +#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ +// Bits requesting flash operations (useful when we want to clear them) +#define STM32L4_FLASH_CR_OPBITS \ + (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ + (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) +// Page is fully specified by BKER and PNB +#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) + +#define STM32L4_FLASH_OPTR_DUALBANK 21 + +// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf +#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) + +#define STM32L0_FLASH_PELOCK (0) +#define STM32L0_FLASH_OPTLOCK (2) +#define STM32L0_FLASH_OBL_LAUNCH (18) + +#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 +#define STM32L0_FLASH_SR_WRPERR 8 +#define STM32L0_FLASH_SR_PGAERR 9 +#define STM32L0_FLASH_SR_NOTZEROERR 16 + +#define FLASH_ACR_OFF ((uint32_t)0x00) +#define FLASH_PECR_OFF ((uint32_t)0x04) +#define FLASH_PDKEYR_OFF ((uint32_t)0x08) +#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) +#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) +#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) +#define FLASH_SR_OFF ((uint32_t)0x18) +#define FLASH_OBR_OFF ((uint32_t)0x1c) +#define FLASH_WRPR_OFF ((uint32_t)0x20) + +// STM32F7 +#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) +#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) +#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) +#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) +#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) +#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) +#define FLASH_F7_OPTCR_LOCK 0 +#define FLASH_F7_OPTCR_START 1 +#define FLASH_F7_CR_STRT 16 +#define FLASH_F7_CR_LOCK 31 +#define FLASH_F7_CR_SER 1 +#define FLASH_F7_CR_SNB 3 +#define FLASH_F7_CR_SNB_MASK 0xf8 +#define FLASH_F7_SR_BSY 16 +#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ +#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ +#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ +#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ +#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ +#define FLASH_F7_SR_EOP 0 /* End of operation */ +#define FLASH_F7_OPTCR1_BOOT_ADD0 0 +#define FLASH_F7_OPTCR1_BOOT_ADD1 16 + +#define FLASH_F7_SR_ERROR_MASK \ + ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ + (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ + (1 << FLASH_F7_SR_OP_ERR)) + +// STM32F4 +#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) +#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) +#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) +#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) +#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) +#define FLASH_F4_OPTCR_LOCK 0 +#define FLASH_F4_OPTCR_START 1 +#define FLASH_F4_CR_STRT 16 +#define FLASH_F4_CR_LOCK 31 +#define FLASH_F4_CR_SER 1 +#define FLASH_F4_CR_SNB 3 +#define FLASH_F4_CR_SNB_MASK 0xf8 +#define FLASH_F4_SR_ERROR_MASK 0x000000F0 +#define FLASH_F4_SR_PGAERR 5 +#define FLASH_F4_SR_WRPERR 4 +#define FLASH_F4_SR_BSY 16 + +// STM32F2 +#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) +#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) +#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) +#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) +#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) +#define FLASH_F2_OPT_LOCK_BIT (1u << 0) +#define FLASH_F2_CR_STRT 16 +#define FLASH_F2_CR_LOCK 31 + +#define FLASH_F2_CR_SER 1 +#define FLASH_F2_CR_SNB 3 +#define FLASH_F2_CR_SNB_MASK 0x78 +#define FLASH_F2_SR_BSY 16 + +// STM32H7xx +#define FLASH_H7_CR_LOCK 0 +#define FLASH_H7_CR_PG 1 +#define FLASH_H7_CR_SER 2 +#define FLASH_H7_CR_BER 3 +#define FLASH_H7_CR_PSIZE 4 +#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7Ax ? 5 : 7) +#define FLASH_H7_CR_SNB 8 +#define FLASH_H7_CR_SNB_MASK 0x700 + +#define FLASH_H7_SR_QW 2 +#define FLASH_H7_SR_WRPERR 17 +#define FLASH_H7_SR_PGSERR 18 +#define FLASH_H7_SR_STRBERR 19 +#define FLASH_H7_SR_ERROR_MASK \ + ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ + (1 << FLASH_H7_SR_WRPERR)) + +#define FLASH_H7_OPTCR_OPTLOCK 0 +#define FLASH_H7_OPTCR_OPTSTART 1 +#define FLASH_H7_OPTCR_MER 4 + +#define FLASH_H7_OPTSR_OPT_BUSY 0 +#define FLASH_H7_OPTSR_OPTCHANGEERR 30 + +#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 + +#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) +#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) +#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) +#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) +#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) +#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) +#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) +#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) +#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) +#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) +#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) +#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) +#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) +#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) + +#endif // STM32FLASH_H \ No newline at end of file diff --git a/src/calculate.c b/src/calculate.c new file mode 100644 index 000000000..22f6e3a5b --- /dev/null +++ b/src/calculate.c @@ -0,0 +1,74 @@ +#include +#include "calculate.h" +#include "common_flash.h" + +uint32_t calculate_F4_sectornum(uint32_t flashaddr) { + uint32_t offset = 0; + flashaddr &= ~STM32_FLASH_BASE; // page now holding the actual flash address + + if (flashaddr >= 0x100000) { + offset = 12; + flashaddr -= 0x100000; + } + + if (flashaddr < 0x4000) { + return (offset + 0); + } else if (flashaddr < 0x8000) { + return (offset + 1); + } else if (flashaddr < 0xc000) { + return (offset + 2); + } else if (flashaddr < 0x10000) { + return (offset + 3); + } else if (flashaddr < 0x20000) { + return (offset + 4); + } else { + return (offset + (flashaddr / 0x20000) + 4); + } +} + +uint32_t calculate_F7_sectornum(uint32_t flashaddr) { + flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address + + if (flashaddr < 0x20000) { + return (flashaddr / 0x8000); + } else if (flashaddr < 0x40000) { + return (4); + } else { + return ((flashaddr / 0x40000) + 4); + } +} + +uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, + unsigned bank) { + flashaddr &= + ~((bank == BANK_1) + ? STM32_FLASH_BASE + : STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address + return (flashaddr / sl->flash_pgsz); +} + +// returns BKER:PNB for the given page address +uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { + uint32_t bker = 0; + uint32_t flashopt; + stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); + flashaddr -= STM32_FLASH_BASE; + + if (sl->chip_id == STLINK_CHIPID_STM32_L4 || + sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x || + sl->chip_id == STLINK_CHIPID_STM32_L4Rx) { + // this chip use dual banked flash + if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { + uint32_t banksize = (uint32_t)sl->flash_size / 2; + + if (flashaddr >= banksize) { + flashaddr -= banksize; + bker = 0x100; + } + } + } + + // For 1MB chips without the dual-bank option set, the page address will + // overflow into the BKER bit, which gives us the correct bank:page value. + return (bker | flashaddr / (uint32_t)sl->flash_pgsz); +} diff --git a/src/calculate.h b/src/calculate.h new file mode 100644 index 000000000..68c1fb988 --- /dev/null +++ b/src/calculate.h @@ -0,0 +1,15 @@ +/* + * File: calculate.h + * + * TODO: add a description + */ + +#ifndef CALCULATE_H +#define CALCULATE_H + +uint32_t calculate_F4_sectornum(uint32_t); +uint32_t calculate_F7_sectornum(uint32_t); +uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, unsigned); +uint32_t calculate_L4_page(stlink_t *, uint32_t); + +#endif // CALCULATE_H diff --git a/src/common.h b/src/common.h new file mode 100644 index 000000000..6c22d58c0 --- /dev/null +++ b/src/common.h @@ -0,0 +1,15 @@ +/* + * File: common.h + * + * TODO: add a description + */ + +#ifndef COMMON_H +#define COMMON_H + +int check_file(stlink_t *, mapped_file_t *, stm32_addr_t); +void md5_calculate(mapped_file_t *); +void stlink_checksum(mapped_file_t *); +void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); + +#endif // COMMON_H diff --git a/src/common_flash.c b/src/common_flash.c new file mode 100644 index 000000000..4f7f46257 --- /dev/null +++ b/src/common_flash.c @@ -0,0 +1,1374 @@ +#include +#include +#include +#include "calculate.h" +#include "common_flash.h" +#include "map_file.h" +#include "common.h" + +#define DEBUG_FLASH 0 + +uint32_t get_stm32l0_flash_base(stlink_t *sl) { + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_L0: + case STLINK_CHIPID_STM32_L0_CAT5: + case STLINK_CHIPID_STM32_L0_CAT2: + case STLINK_CHIPID_STM32_L011: + return (STM32L0_FLASH_REGS_ADDR); + + case STLINK_CHIPID_STM32_L1_CAT2: + case STLINK_CHIPID_STM32_L1_MD: + case STLINK_CHIPID_STM32_L1_MD_PLUS: + case STLINK_CHIPID_STM32_L1_MD_PLUS_HD: + return (STM32L_FLASH_REGS_ADDR); + + default: + WLOG("Flash base use default L0 address\n"); + return (STM32L0_FLASH_REGS_ADDR); + } +} + +uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { + uint32_t reg, res; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + reg = FLASH_F4_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + reg = FLASH_F7_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + } else { + reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } + + stlink_read_debug32(sl, reg, &res); + +#if DEBUG_FLASH + fprintf(stdout, "CR:0x%x\n", res); +#endif + return (res); +} + +void lock_flash(stlink_t *sl) { + uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; + uint32_t cr_mask = 0xffffffffu; + + if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + cr_reg = FLASH_CR; + cr2_reg = FLASH_CR2; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + cr_lock_shift = STM32L0_FLASH_PELOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + cr2_reg = FLASH_H7_CR2; + } + cr_lock_shift = FLASH_H7_CR_LOCK; + cr_mask = ~(1u << FLASH_H7_CR_SER); + } else { + ELOG("unsupported flash method, abort\n"); + return; + } + + stlink_read_debug32(sl, cr_reg, &n); + n &= cr_mask; + n |= (1u << cr_lock_shift); + stlink_write_debug32(sl, cr_reg, n); + + if (cr2_reg) { + n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift); + stlink_write_debug32(sl, cr2_reg, n); + } +} + +static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { + uint32_t sr_reg; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + sr_reg = STM32Gx_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else { + ELOG("method 'write_flash_sr' is unsupported\n"); + return (-1); + } + + return stlink_write_debug32(sl, sr_reg, val); +} + +void clear_flash_error(stlink_t *sl) { + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_F4: + write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_F7: + write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_L0: + write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_L4: + write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); + break; + case STLINK_FLASH_TYPE_H7: + write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); + } + break; + case STLINK_FLASH_TYPE_WB: + write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); + break; + default: + break; + } +} + +uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { + uint32_t res, sr_reg; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + sr_reg = STM32Gx_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else { + ELOG("method 'read_flash_sr' is unsupported\n"); + return (-1); + } + + stlink_read_debug32(sl, sr_reg, &res); + return (res); +} + +unsigned int is_flash_busy(stlink_t *sl) { + uint32_t sr_busy_shift; + unsigned int res; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || + (sl->flash_type == STLINK_FLASH_TYPE_L0)) { + sr_busy_shift = FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + sr_busy_shift = FLASH_F4_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + sr_busy_shift = FLASH_F7_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + sr_busy_shift = STM32L4_FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + sr_busy_shift = STM32Gx_FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + sr_busy_shift = STM32WB_FLASH_SR_BSY; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + sr_busy_shift = FLASH_H7_SR_QW; + } else { + ELOG("method 'is_flash_busy' is unsupported\n"); + return (-1); + } + + res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); + + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); + } + + return (res); +} + +void wait_flash_busy(stlink_t *sl) { + // TODO: add some delays here + while (is_flash_busy(sl)) + ; +} + +int check_flash_error(stlink_t *sl) { + uint32_t res = 0; + uint32_t WRPERR, PROGERR, PGAERR; + + WRPERR = PROGERR = PGAERR = 0; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_SR_WRPRT_ERR); + PROGERR = (1 << FLASH_SR_PG_ERR); + break; + case STLINK_FLASH_TYPE_F4: + res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F4_SR_WRPERR); + PGAERR = (1 << FLASH_F4_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_F7: + res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F7_SR_WRP_ERR); + PROGERR = (1 << FLASH_F7_SR_PGP_ERR); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); + PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); + PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_L0: + res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); + PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_L4: + res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); + PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); + break; + case STLINK_FLASH_TYPE_H7: + res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_H7_SR_WRPERR); + break; + case STLINK_FLASH_TYPE_WB: + res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); + PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); + PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); + break; + default: + break; + } + + if (res) { + if (WRPERR && (WRPERR & res) == WRPERR) { + ELOG("Flash memory is write protected\n"); + res &= ~WRPERR; + } else if (PROGERR && (PROGERR & res) == PROGERR) { + ELOG("Flash memory contains a non-erased value\n"); + res &= ~PROGERR; + } else if (PGAERR && (PGAERR & res) == PGAERR) { + ELOG("Invalid flash address\n"); + res &= ~PGAERR; + } + + if (res) { + ELOG("Flash programming error: %#010x\n", res); + } + return (-1); + } + + return (0); +} + +static inline unsigned int is_flash_locked(stlink_t *sl) { + /* return non zero for true */ + uint32_t cr_lock_shift; + uint32_t cr_reg; + uint32_t n; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + cr_lock_shift = STM32L0_FLASH_PELOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + cr_lock_shift = FLASH_H7_CR_LOCK; + } else { + ELOG("unsupported flash method, abort\n"); + return (-1); + } + + stlink_read_debug32(sl, cr_reg, &n); + return (n & (1u << cr_lock_shift)); +} + +static void unlock_flash(stlink_t *sl) { + uint32_t key_reg, key2_reg = 0; + uint32_t flash_key1 = FLASH_KEY1; + uint32_t flash_key2 = FLASH_KEY2; + /* The unlock sequence consists of 2 write cycles where 2 key values are + * written to the FLASH_KEYR register. An invalid sequence results in a + * definitive lock of the FPEC block until next reset. + */ + + if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + key_reg = FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + key_reg = FLASH_KEYR; + key2_reg = FLASH_KEYR2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + key_reg = FLASH_F4_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + key_reg = FLASH_F7_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; + flash_key1 = FLASH_L0_PEKEY1; + flash_key2 = FLASH_L0_PEKEY2; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + key_reg = STM32L4_FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + key_reg = STM32Gx_FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + key_reg = STM32WB_FLASH_KEYR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + key_reg = FLASH_H7_KEYR1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + key2_reg = FLASH_H7_KEYR2; + } + } else { + ELOG("unsupported flash method, abort\n"); + return; + } + + stlink_write_debug32(sl, key_reg, flash_key1); + stlink_write_debug32(sl, key_reg, flash_key2); + + if (key2_reg) { + stlink_write_debug32(sl, key2_reg, flash_key1); + stlink_write_debug32(sl, key2_reg, flash_key2); + } +} + +/* unlock flash if already locked */ +int unlock_flash_if(stlink_t *sl) { + if (is_flash_locked(sl)) { + unlock_flash(sl); + + if (is_flash_locked(sl)) { + WLOG("Failed to unlock flash!\n"); + return (-1); + } + } + + DLOG("Successfully unlocked flash\n"); + return (0); +} + +int lock_flash_option(stlink_t *sl) { + uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; + int active_bit_level = 1; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; + break; + case STLINK_FLASH_TYPE_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_L0: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STLINK_FLASH_TYPE_L4: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_WB: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optcr2_reg = FLASH_H7_OPTCR2; + break; + default: + ELOG("unsupported flash method, abort\n"); + return -1; + } + + stlink_read_debug32(sl, optcr_reg, &n); + + if (active_bit_level == 0) { + n &= ~(1u << optlock_shift); + } else { + n |= (1u << optlock_shift); + } + + stlink_write_debug32(sl, optcr_reg, n); + + if (optcr2_reg) { + stlink_read_debug32(sl, optcr2_reg, &n); + + if (active_bit_level == 0) { + n &= ~(1u << optlock_shift); + } else { + n |= (1u << optlock_shift); + } + + stlink_write_debug32(sl, optcr2_reg, n); + } + + return (0); +} + +static bool is_flash_option_locked(stlink_t *sl) { + uint32_t optlock_shift, optcr_reg; + int active_bit_level = 1; + uint32_t n; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; /* bit is "option write enable", not lock */ + break; + case STLINK_FLASH_TYPE_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; + case STLINK_FLASH_TYPE_L0: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STLINK_FLASH_TYPE_L4: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_WB: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + case STLINK_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + break; + default: + ELOG("unsupported flash method, abort\n"); + return -1; + } + + stlink_read_debug32(sl, optcr_reg, &n); + + if (active_bit_level == 0) { + return (!(n & (1u << optlock_shift))); + } + + return (n & (1u << optlock_shift)); +} + +static int unlock_flash_option(stlink_t *sl) { + uint32_t optkey_reg, optkey2_reg = 0; + uint32_t optkey1 = FLASH_OPTKEY1; + uint32_t optkey2 = FLASH_OPTKEY2; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + optkey_reg = FLASH_OPTKEYR; + optkey1 = FLASH_F0_OPTKEY1; + optkey2 = FLASH_F0_OPTKEY2; + break; + case STLINK_FLASH_TYPE_F4: + optkey_reg = FLASH_F4_OPT_KEYR; + break; + case STLINK_FLASH_TYPE_F7: + optkey_reg = FLASH_F7_OPT_KEYR; + break; + case STLINK_FLASH_TYPE_L0: + optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; + optkey1 = FLASH_L0_OPTKEY1; + optkey2 = FLASH_L0_OPTKEY2; + break; + case STLINK_FLASH_TYPE_L4: + optkey_reg = STM32L4_FLASH_OPTKEYR; + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + optkey_reg = STM32Gx_FLASH_OPTKEYR; + break; + case STLINK_FLASH_TYPE_WB: + optkey_reg = STM32WB_FLASH_OPT_KEYR; + break; + case STLINK_FLASH_TYPE_H7: + optkey_reg = FLASH_H7_OPT_KEYR; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optkey2_reg = FLASH_H7_OPT_KEYR2; + break; + default: + ELOG("unsupported flash method, abort\n"); + return (-1); + } + + stlink_write_debug32(sl, optkey_reg, optkey1); + stlink_write_debug32(sl, optkey_reg, optkey2); + + if (optkey2_reg) { + stlink_write_debug32(sl, optkey2_reg, optkey1); + stlink_write_debug32(sl, optkey2_reg, optkey2); + } + + return (0); +} + +int unlock_flash_option_if(stlink_t *sl) { + if (is_flash_option_locked(sl)) { + if (unlock_flash_option(sl)) { + ELOG("Could not unlock flash option!\n"); + return (-1); + } + + if (is_flash_option_locked(sl)) { + ELOG("Failed to unlock flash option!\n"); + return (-1); + } + } + + DLOG("Successfully unlocked flash option\n"); + return (0); +} + +void write_flash_cr_psiz(stlink_t *sl, uint32_t n, + unsigned bank) { + uint32_t cr_reg, psize_shift; + uint32_t x = read_flash_cr(sl, bank); + + if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + psize_shift = FLASH_H7_CR_PSIZE; + } else { + cr_reg = FLASH_F4_CR; + psize_shift = 8; + } + + x &= ~(0x03 << psize_shift); + x |= (n << psize_shift); +#if DEBUG_FLASH + fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, cr_reg, x); +} + +void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { + uint32_t cr_reg, n; + uint32_t bit = FLASH_CR_PG; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + bit = FLASH_H7_CR_PG; + } else { + cr_reg = FLASH_CR; + } + + n = read_flash_cr(sl, bank) & ~(1 << bit); + stlink_write_debug32(sl, cr_reg, n); +} +/* ------------------------------------------------------------------------ */ + +static void wait_flash_busy_progress(stlink_t *sl) { + int i = 0; + fprintf(stdout, "Mass erasing"); + fflush(stdout); + + while (is_flash_busy(sl)) { + usleep(10000); + i++; + + if (i % 100 == 0) { + fprintf(stdout, "."); + fflush(stdout); + } + } + + fprintf(stdout, "\n"); +} + +static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { + stlink_write_debug32(sl, (bank == BANK_1) ? FLASH_AR : FLASH_AR2, n); +} + +static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { + uint32_t cr_reg, snb_mask, snb_shift, ser_shift; + uint32_t x = read_flash_cr(sl, bank); + + if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + snb_mask = FLASH_H7_CR_SNB_MASK; + snb_shift = FLASH_H7_CR_SNB; + ser_shift = FLASH_H7_CR_SER; + } else { + cr_reg = FLASH_F4_CR; + snb_mask = FLASH_F4_CR_SNB_MASK; + snb_shift = FLASH_F4_CR_SNB; + ser_shift = FLASH_F4_CR_SER; + } + + x &= ~snb_mask; + x |= (n << snb_shift); + x |= (1 << ser_shift); +#if DEBUG_FLASH + fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, cr_reg, x); +} + +static void set_flash_cr_per(stlink_t *sl, unsigned bank) { + uint32_t cr_reg, val; + + if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } + + stlink_read_debug32(sl, cr_reg, &val); + val |= (1 << FLASH_CR_PER); + stlink_write_debug32(sl, cr_reg, val); +} + +static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { + uint32_t cr_reg; + + if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } + + const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER); + stlink_write_debug32(sl, cr_reg, n); +} + +static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { + stlink_write_debug32(sl, STM32L4_FLASH_SR, + 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); + uint32_t x = read_flash_cr(sl, BANK_1); + x &= ~STM32L4_FLASH_CR_OPBITS; + x &= ~STM32L4_FLASH_CR_PAGEMASK; + x &= ~(1 << STM32L4_FLASH_CR_MER1); + x &= ~(1 << STM32L4_FLASH_CR_MER2); + x |= (n << STM32L4_FLASH_CR_PNB); + x |= (uint32_t)(1lu << STM32L4_FLASH_CR_PER); +#if DEBUG_FLASH + fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, STM32L4_FLASH_CR, x); +} + +static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { + uint32_t val, cr_reg, cr_strt; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_strt = 1 << FLASH_F4_CR_STRT; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_strt = 1 << FLASH_F7_CR_STRT; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_strt = (1 << STM32L4_FLASH_CR_STRT); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_strt = (1 << STM32Gx_FLASH_CR_STRT); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_strt = (1 << STM32WB_FLASH_CR_STRT); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + cr_strt = (1 << FLASH_CR_STRT); + } + + stlink_read_debug32(sl, cr_reg, &val); + val |= cr_strt; + stlink_write_debug32(sl, cr_reg, val); +} + +static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { + uint32_t val, cr_reg, cr_mer, cr_pg; + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); + cr_pg = (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_mer = (1 << STM32Gx_FLASH_CR_MER1); + + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); + } + + cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + cr_mer = (1 << FLASH_H7_CR_BER); + cr_pg = (1 << FLASH_H7_CR_PG); + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); + } + + stlink_read_debug32(sl, cr_reg, &val); + + if (val & cr_pg) { + // STM32F030 will drop MER bit if PG was set + val &= ~cr_pg; + stlink_write_debug32(sl, cr_reg, val); + } + + if (v) { + val |= cr_mer; + } else { + val &= ~cr_mer; + } + + stlink_write_debug32(sl, cr_reg, val); +} + +/** + * Erase a page of flash, assumes sl is fully populated with things like + * chip/core ids + * @param sl stlink context + * @param flashaddr an address in the flash page to erase + * @return 0 on success -ve on failure + */ +int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { + // wait for ongoing op to finish + wait_flash_busy(sl); + // clear flash IO errors + clear_flash_error(sl); + + if (sl->flash_type == STLINK_FLASH_TYPE_F4 || + sl->flash_type == STLINK_FLASH_TYPE_F7 || + sl->flash_type == STLINK_FLASH_TYPE_L4) { + // unlock if locked + unlock_flash_if(sl); + + // select the page to erase + if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || + (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || + (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || + (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) || + (sl->chip_id == STLINK_CHIPID_STM32_L4Rx)) { + // calculate the actual bank+page from the address + uint32_t page = calculate_L4_page(sl, flashaddr); + + fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, + stlink_calculate_pagesize(sl, flashaddr)); + + write_flash_cr_bker_pnb(sl, page); + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || + sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { + // calculate the actual page from the address + uint32_t sector = calculate_F7_sectornum(flashaddr); + + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, + stlink_calculate_pagesize(sl, flashaddr)); + write_flash_cr_snb(sl, sector, BANK_1); + } else { + // calculate the actual page from the address + uint32_t sector = calculate_F4_sectornum(flashaddr); + + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, + stlink_calculate_pagesize(sl, flashaddr)); + + // the SNB values for flash sectors in the second bank do not directly + // follow the values for the first bank on 2mb devices... + if (sector >= 12) { + sector += 4; + } + + write_flash_cr_snb(sl, sector, BANK_1); + } + + set_flash_cr_strt(sl, BANK_1); // start erase operation + wait_flash_busy(sl); // wait for completion + lock_flash(sl); // TODO: fails to program if this is in +#if DEBUG_FLASH + fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); +#endif + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // check if the locks are set + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + + if ((val & (1 << 0)) || (val & (1 << 1))) { + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY2); + + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + + if (val & (1 << 0)) { + WLOG("pecr.pelock not clear (%#x)\n", val); + return (-1); + } + + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY2); + + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + + if (val & (1 << 1)) { + WLOG("pecr.prglock not clear (%#x)\n", val); + return (-1); + } + } + + // set pecr.{erase,prog} + val |= (1 << 9) | (1 << 3); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + + // write 0 to the first word of the page to be erased + stlink_write_debug32(sl, flashaddr, 0); + + /* MP: It is better to wait for clearing the busy bit after issuing page + * erase command, even though PM0062 recommends to wait before it. + * Test shows that a few iterations is performed in the following loop + * before busy bit is cleared. + */ + wait_flash_busy(sl); + + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + uint32_t val; + unlock_flash_if(sl); + set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit + + // set the page to erase + if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + + // sec 3.10.5 - PNB[7:0] is offset by 3. + val &= ~(0xFF << 3); // Clear previously set page number (if any) + val |= ((flash_page & 0xFF) << 3); + + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. + val &= ~(0x3F << 3); + val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. + val &= ~(0x7F << 3); + val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } + + set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit + wait_flash_busy(sl); // wait for the 'busy' bit to clear + clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit + lock_flash(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || + sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + unlock_flash_if(sl); + clear_flash_cr_pg(sl, bank); // clear the pg bit + set_flash_cr_per(sl, bank); // set the page erase bit + write_flash_ar(sl, flashaddr, bank); // select the page to erase + set_flash_cr_strt(sl, + bank); // start erase operation, reset by hw with busy bit + wait_flash_busy(sl); + clear_flash_cr_per(sl, bank); // clear the page erase bit + lock_flash(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + unlock_flash_if(sl); // unlock if locked + uint32_t sector = calculate_H7_sectornum( + sl, flashaddr, bank); // calculate the actual page from the address + write_flash_cr_snb(sl, sector, bank); // select the page to erase + set_flash_cr_strt(sl, bank); // start erase operation + wait_flash_busy(sl); // wait for completion + lock_flash(sl); + } else { + WLOG("unknown coreid %x, page erase failed\n", sl->core_id); + return (-1); + } + + return check_flash_error(sl); +} + +int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { + // Check the address and size validity + if (stlink_check_address_range_validity(sl, base_addr, size) < 0) { + return -1; + } + + // Make sure the requested address is aligned with the beginning of a page + if (stlink_check_address_alignment(sl, base_addr) < 0) { + ELOG("The address to erase is not aligned with the beginning of a page\n"); + return -1; + } + + stm32_addr_t addr = base_addr; + do { + long unsigned int page_size = stlink_calculate_pagesize(sl, addr); + + // Check if size is aligned with a page, unless we want to completely erase the last page + if ((addr + page_size) > (base_addr + size) && !align_size) { + ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); + return -1; + } + + if (stlink_erase_flash_page(sl, addr)) { + WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); + return (-1); + } + + fprintf(stdout, "-> Flash page at %#x erased (size: %#lx)\n", addr, page_size); + fflush(stdout); + + // check the next page is within the range to erase + addr += page_size; + } while (addr < (base_addr + size)); + + fprintf(stdout, "\n"); + return 0; +} + +int stlink_erase_flash_mass(stlink_t *sl) { + int err = 0; + + // TODO: User MER bit to mass-erase WB series. + if (sl->flash_type == STLINK_FLASH_TYPE_L0 || + sl->flash_type == STLINK_FLASH_TYPE_WB) { + + err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); + + } else { + wait_flash_busy(sl); + clear_flash_error(sl); + unlock_flash_if(sl); + + if (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } + + set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit + set_flash_cr_strt( + sl, BANK_1); // start erase operation, reset by hw with busy bit + + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 + set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 + } + + wait_flash_busy_progress(sl); + lock_flash(sl); + + // reset the mass erase bit + set_flash_cr_mer(sl, 0, BANK_1); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || + (sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + set_flash_cr_mer(sl, 0, BANK_2); + } + + err = check_flash_error(sl); + } + + return (err); +} + +int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, + stm32_addr_t addr) { + /* Write the block in flash at addr */ + int err; + unsigned int num_empty, idx; + uint8_t erased_pattern = stlink_get_erased_pattern(sl); + + /* + * This optimisation may cause unexpected garbage data remaining. + * Therfore it is turned off by default. + */ + if (sl->opt) { + idx = (unsigned int)length; + + for (num_empty = 0; num_empty != length; ++num_empty) + if (data[--idx] != erased_pattern) { + break; + } + + num_empty -= (num_empty & 3); // Round down to words + + if (num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, + erased_pattern); + } + } else { + num_empty = 0; + } + + /* + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. + */ + err = stlink_write_flash(sl, addr, data, + (num_empty == length) ? (uint32_t)length + : (uint32_t)length - num_empty, + num_empty == length); + stlink_fwrite_finalize(sl, addr); + return (err); +} + +/** + * Write the given binary file into flash at address "addr" + * @param sl + * @param path readable file path, should be binary image + * @param addr where to start writing + * @return 0 on success, -ve on failure. + */ +int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { + /* Write the file in flash at addr */ + int err; + unsigned int num_empty, idx; + uint8_t erased_pattern = stlink_get_erased_pattern(sl); + mapped_file_t mf = MAPPED_FILE_INITIALIZER; + + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return (-1); + } + + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); + + if (sl->opt) { + idx = (unsigned int)mf.len; + + for (num_empty = 0; num_empty != mf.len; ++num_empty) { + if (mf.base[--idx] != erased_pattern) { + break; + } + } + + num_empty -= (num_empty & 3); // round down to words + + if (num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, + erased_pattern); + } + } else { + num_empty = 0; + } + + /* + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. + */ + err = stlink_write_flash(sl, addr, mf.base, + (num_empty == mf.len) ? (uint32_t)mf.len + : (uint32_t)mf.len - num_empty, + num_empty == mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); + return (err); +} + + +int stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { + // check the contents of path are at addr + + int res; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; + + if (map_file(&mf, path) == -1) { + return (-1); + } + + res = check_file(sl, &mf, addr); + unmap_file(&mf); + return (res); +} + +/** + * Verify addr..addr+len is binary identical to base...base+len + * @param sl stlink context + * @param address stm device address + * @param data host side buffer to check against + * @param length how much + * @return 0 for success, -ve for failure + */ +int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, + unsigned length) { + size_t off; + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; + ILOG("Starting verification of write complete\n"); + + for (off = 0; off < length; off += cmp_size) { + size_t aligned_size; + + // adjust last page size + if ((off + cmp_size) > length) { + cmp_size = length - off; + } + + aligned_size = cmp_size; + + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } + + stlink_read_mem32(sl, address + (uint32_t)off, (uint16_t)aligned_size); + + if (memcmp(sl->q_buf, data + off, cmp_size)) { + ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); + return (-1); + } + } + + ILOG("Flash written and verified! jolly good!\n"); + return (0); +} + +// Check if an address and size are within the flash +int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { + long unsigned int logvar; + if (addr < sl->flash_base || addr >= (sl->flash_base + sl->flash_size)) { + logvar = sl->flash_base + sl->flash_size - 1; + ELOG("Invalid address, it should be within 0x%08x - 0x%08lx\n", sl->flash_base, logvar); + return (-1); + } + if ((addr + size) > (sl->flash_base + sl->flash_size)) { + logvar = sl->flash_base + sl->flash_size - addr; + ELOG("The size exceeds the size of the flash (0x%08lx bytes available)\n", logvar); + return (-1); + } + return 0; +} + +// Check if an address is aligned with the beginning of a page +int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { + stm32_addr_t page = sl->flash_base; + + while (page < addr) { + page += stlink_calculate_pagesize(sl, page); + } + + if (page != addr) { + return -1; + } + + return 0; +} + +int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len, uint8_t eraseonly) { + int ret; + flash_loader_t fl; + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, + len, addr, addr); + // check addr range is inside the flash + stlink_calculate_pagesize(sl, addr); + + // Check the address and size validity + if (stlink_check_address_range_validity(sl, addr, len) < 0) { + return (-1); + } else if (len & 1) { + WLOG("unaligned len 0x%x -- padding with zero\n", len); + len += 1; + } else if (stlink_check_address_alignment(sl, addr) < 0) { + ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " + "check page start address and compare with flash module organisation " + "in related ST reference manual of your device.\n", + (unsigned)(sl->flash_pgsz)); + return (-1); + } + + // make sure we've loaded the context with the chip details + stlink_core_id(sl); + + // Erase this section of the flash + if (stlink_erase_flash_section(sl, addr, len, true) < 0) { + ELOG("Failed to erase the flash prior to writing\n"); + return (-1); + } + + if (eraseonly) { + return (0); + } + + ret = stlink_flashloader_start(sl, &fl); + if (ret) + return ret; + ret = stlink_flashloader_write(sl, &fl, addr, base, len); + if (ret) + return ret; + ret = stlink_flashloader_stop(sl, &fl); + if (ret) + return ret; + + return (stlink_verify_write_flash(sl, addr, base, len)); +} diff --git a/src/common_flash.h b/src/common_flash.h new file mode 100644 index 000000000..70a6f0e04 --- /dev/null +++ b/src/common_flash.h @@ -0,0 +1,27 @@ +/* + * File: common_flash.h + * + * TODO: add a description + */ + +#ifndef COMMON_FLASH_H +#define COMMON_FLASH_H + +void lock_flash(stlink_t *); +void clear_flash_error(stlink_t *); +void wait_flash_busy(stlink_t *); +int check_flash_error(stlink_t *); +int unlock_flash_if(stlink_t *); +int lock_flash_option(stlink_t *); +int unlock_flash_option_if(stlink_t *); +void write_flash_cr_psiz(stlink_t *, uint32_t, unsigned); +void clear_flash_cr_pg(stlink_t *, unsigned); + +// TODO: move to private defines if possible + +#define BANK_1 0 +#define BANK_2 1 + +uint32_t read_flash_cr(stlink_t *, unsigned); +uint32_t get_stm32l0_flash_base(stlink_t *); +#endif // STLINK_H diff --git a/src/flashloader.c b/src/flashloader.c new file mode 100644 index 000000000..df14e506c --- /dev/null +++ b/src/flashloader.c @@ -0,0 +1,481 @@ +#include +#include +#include "common_flash.h" + +#define L1_WRITE_BLOCK_SIZE 0x80 +#define L0_WRITE_BLOCK_SIZE 0x40 + +int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len, uint32_t pagesize) { + unsigned int count, off; + unsigned int num_half_pages = len / pagesize; + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + flash_loader_t fl; + bool use_loader = true; + int ret = 0; + + // enable half page write + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << FLASH_L1_FPRG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + val |= (1 << FLASH_L1_PROG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + + wait_flash_busy(sl); + + for (count = 0; count < num_half_pages; count++) { + if (use_loader) { + ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, + base + count * pagesize, pagesize); + if (ret && count == 0) { + /* It seems that stm32lx devices have a problem when it is blank */ + WLOG("Failed to use flash loader, fallback to soft write\n"); + use_loader = false; + } + } + if (!use_loader) { + ret = 0; + for (off = 0; off < pagesize && !ret; off += 64) { + size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; + memcpy(sl->q_buf, base + count * pagesize + off, chunk); + ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); + } + } + + if (ret) { + WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", + addr + count * pagesize); + break; + } + + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading + fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); + fflush(stdout); + } + + // wait for sr.busy to be cleared + wait_flash_busy(sl); + } + + // disable half page write + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + return (ret); +} + +static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { + uint32_t cr_reg, x; + + x = read_flash_cr(sl, bank); + + if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + cr_reg = FLASH_F4_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + x &= ~STM32L4_FLASH_CR_OPBITS; + x |= (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + cr_reg = STM32WB_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + x |= (1 << FLASH_H7_CR_PG); + } else { + cr_reg = FLASH_CR; + x = (1 << FLASH_CR_PG); + } + + stlink_write_debug32(sl, cr_reg, x); +} + +static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { + uint32_t rcc, rcc_dma_mask, value; + + rcc = rcc_dma_mask = value = 0; + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + rcc = STM32F1_RCC_AHBENR; + rcc_dma_mask = STM32F1_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_F4: + case STLINK_FLASH_TYPE_F7: + rcc = STM32F4_RCC_AHB1ENR; + rcc_dma_mask = STM32F4_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_G0: + rcc = STM32G0_RCC_AHBENR; + rcc_dma_mask = STM32G0_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_G4: + case STLINK_FLASH_TYPE_L4: + rcc = STM32G4_RCC_AHB1ENR; + rcc_dma_mask = STM32G4_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_L0: + rcc = STM32L0_RCC_AHBENR; + rcc_dma_mask = STM32L0_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_H7: + rcc = STM32H7_RCC_AHB1ENR; + rcc_dma_mask = STM32H7_RCC_DMAEN; + break; + case STLINK_FLASH_TYPE_WB: + rcc = STM32WB_RCC_AHB1ENR; + rcc_dma_mask = STM32WB_RCC_DMAEN; + break; + default: + return; + } + + if (!stlink_read_debug32(sl, rcc, &value)) { + if (bckpRstr) { + value = (value & (~rcc_dma_mask)) | fl->rcc_dma_bkp; + } else { + fl->rcc_dma_bkp = value & rcc_dma_mask; + value &= ~rcc_dma_mask; + } + stlink_write_debug32(sl, rcc, value); + } +} + +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { + // disable DMA + set_dma_state(sl, fl, 0); + + // wait for ongoing op to finish + wait_flash_busy(sl); + // Clear errors + clear_flash_error(sl); + + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + ILOG("Starting Flash write for F2/F4/F7/L4\n"); + + // Flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + + unlock_flash_if(sl); // first unlock the cr + + int voltage; + if (sl->version.stlink_v == 1) { + WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); + voltage = 3200; + } else { + voltage = stlink_target_voltage(sl); + } + + if (voltage == -1) { + ELOG("Failed to read Target voltage\n"); + return (-1); + } + + if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + // L4 does not have a byte-write mode + if (voltage < 1710) { + ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); + return (-1); + } + } else { + if (voltage > 2700) { + ILOG("enabling 32-bit flash writes\n"); + write_flash_cr_psiz(sl, 2, BANK_1); + } else { + ILOG("Target voltage (%d mV) too low for 32-bit flash, " + "using 8-bit flash writes\n", + voltage); + write_flash_cr_psiz(sl, 0, BANK_1); + } + } + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + ILOG("Starting Flash write for WB/G0/G4\n"); + + unlock_flash_if(sl); // unlock flash if necessary + set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + ILOG("Starting Flash write for L0\n"); + + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY2); + + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { + ELOG("pecr.pelock not clear\n"); + return (-1); + } + + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY2); + + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { + ELOG("pecr.prglock not clear\n"); + return (-1); + } + + /* Flash loader initialisation */ + if (stlink_flash_loader_init(sl, fl) == -1) { + // L0/L1 have fallback to soft write + WLOG("stlink_flash_loader_init() == -1\n"); + } + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); + + // flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + + // unlock flash + unlock_flash_if(sl); + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + set_flash_cr_pg(sl, BANK_2); + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + ILOG("Starting Flash write for H7\n"); + + unlock_flash_if(sl); // unlock the cr + set_flash_cr_pg(sl, BANK_1); // set programming mode + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + set_flash_cr_pg(sl, BANK_2); + } + if (sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } + } else { + ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + return (-1); + } + + return (0); +} + +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, + stm32_addr_t addr, uint8_t *base, uint32_t len) { + size_t off; + if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; + for (off = 0; off < len;) { + size_t size = len - off > buf_size ? buf_size : len - off; + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + off += size; + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || + sl->flash_type == STLINK_FLASH_TYPE_G0 || + sl->flash_type == STLINK_FLASH_TYPE_G4) { + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } + + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + } + fprintf(stdout, "\n"); + + // flash writes happen as 2 words at a time + if ((off / sizeof(uint32_t)) % 2 != 0) { + stlink_write_debug32(sl, addr + (uint32_t)off, + 0); // write a single word of zeros + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? + L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; + + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + + off = 0; + + if (len > pagesize) { + if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { + return (-1); + } else { + off = (size_t)(len / pagesize) * pagesize; + } + } + + // write remaining word in program memory + for (; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } + + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + + // wait for sr.busy to be cleared + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); + + // TODO: check redo write operation + } + fprintf(stdout, "\n"); + } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + int write_block_count = 0; + for (off = 0; off < len; off += sl->flash_pgsz) { + // adjust last write size + size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; + + // unlock and set programming mode + unlock_flash_if(sl); + + DLOG("Finished unlocking flash, running loader!\n"); + + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + lock_flash(sl); + + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading + fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, + (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + for (off = 0; off < len;) { + // Program STM32H7x with 64-byte Flash words + size_t chunk = (len - off > 64) ? 64 : len - off; + memcpy(sl->q_buf, base + off, chunk); + stlink_write_mem32(sl, addr + (uint32_t)off, 64); + wait_flash_busy(sl); + + off += chunk; + + if (sl->verbose >= 1) { + // show progress + fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, + (unsigned int)len); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else { + return (-1); + } + + return check_flash_error(sl); +} + +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { + uint32_t dhcsr; + + if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || + (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || + (sl->flash_type == STLINK_FLASH_TYPE_F4) || + (sl->flash_type == STLINK_FLASH_TYPE_F7) || + (sl->flash_type == STLINK_FLASH_TYPE_L4) || + (sl->flash_type == STLINK_FLASH_TYPE_WB) || + (sl->flash_type == STLINK_FLASH_TYPE_G0) || + (sl->flash_type == STLINK_FLASH_TYPE_G4) || + (sl->flash_type == STLINK_FLASH_TYPE_H7)) { + + clear_flash_cr_pg(sl, BANK_1); + if ((sl->flash_type == STLINK_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || + sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + clear_flash_cr_pg(sl, BANK_2); + } + lock_flash(sl); + } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } + + // enable interrupt + if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); + } + + // restore DMA state + set_dma_state(sl, fl, 1); + + return (0); +} diff --git a/src/map_file.c b/src/map_file.c new file mode 100644 index 000000000..5282fae27 --- /dev/null +++ b/src/map_file.c @@ -0,0 +1,57 @@ +#include +#include +#include +#include + +#include "map_file.h" + +#ifndef MAX_FILE_SIZE +#define MAX_FILE_SIZE (1<<20) // 1 GB max file size +#endif + +int map_file(mapped_file_t *mf, const char *path) { + int error = -1; + struct stat st; + + const int fd = open(path, O_RDONLY | O_BINARY); + + if (fd == -1) { + fprintf(stderr, "open(%s) == -1\n", path); + return (-1); + } + + if (fstat(fd, &st) == -1) { + fprintf(stderr, "fstat(%s) == -1\n", path); + goto on_error; + } + + if (sizeof(st.st_size) != sizeof(size_t)) { + // on 32 bit systems, check if there is an overflow + if (st.st_size > (off_t)MAX_FILE_SIZE /*1 GB*/ ) { + // limit file size to 1 GB + fprintf(stderr, "mmap() size_t overflow for file %s\n", path); + goto on_error; + } + } + + mf->base = + (uint8_t *)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); + + if (mf->base == MAP_FAILED) { + fprintf(stderr, "mmap() == MAP_FAILED for file %s\n", path); + goto on_error; + } + + mf->len = (size_t)st.st_size; + error = 0; // success + +on_error: + close(fd); + return (error); +} + +void unmap_file(mapped_file_t *mf) { + munmap((void *)mf->base, mf->len); + mf->base = (unsigned char *)MAP_FAILED; + mf->len = 0; +} diff --git a/src/map_file.h b/src/map_file.h new file mode 100644 index 000000000..b35f24ad0 --- /dev/null +++ b/src/map_file.h @@ -0,0 +1,28 @@ +/* + * File: map_file.h + * + * TODO: add a description + */ + +#ifndef MAP_FILE_H +#define MAP_FILE_H + +#ifdef STLINK_HAVE_SYS_MMAN_H +#include +#else +#include +#endif + +/* Memory mapped file */ +typedef struct mapped_file { + uint8_t *base; + size_t len; +} mapped_file_t; + +#define MAPPED_FILE_INITIALIZER \ + { NULL, 0 } + +int map_file(mapped_file_t *, const char *); +void unmap_file(mapped_file_t *); + +#endif // MAP_FILE_H diff --git a/src/option.c b/src/option.c new file mode 100644 index 000000000..b70f7a533 --- /dev/null +++ b/src/option.c @@ -0,0 +1,1026 @@ +#include +#include +#include "common_flash.h" +#include "map_file.h" +#include "common.h" + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_Gx(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_Gx(sl, option_byte); +} + +/** + * Read first option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); + return stlink_read_debug32(sl, sl->option_base, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f2(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f2(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f4(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f4(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + * + * Since multiple bytes can be read, we read and print all but one here + * and then return the last one just like other devices + */ +int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { + int err = -1; + for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { + err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), + option_byte); + if (err == -1) { + return err; + } else { + printf("%08x\n", *option_byte); + } + } + + return stlink_read_debug32( + sl, + sl->option_base + (uint32_t)(sl->option_size / 4 - 1) * sizeof(uint32_t), + option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return (-1); + } + + switch (sl->chip_id) { + case STLINK_CHIPID_STM32_F2: + return stlink_read_option_bytes_f2(sl, option_byte); + case STLINK_CHIPID_STM32_F4: + case STLINK_CHIPID_STM32_F446: + return stlink_read_option_bytes_f4(sl, option_byte); + case STLINK_CHIPID_STM32_F76xxx: + return stlink_read_option_bytes_f7(sl, option_byte); + case STLINK_CHIPID_STM32_G0_CAT1: + case STLINK_CHIPID_STM32_G0_CAT2: + case STLINK_CHIPID_STM32_G4_CAT2: + case STLINK_CHIPID_STM32_G4_CAT3: + return stlink_read_option_bytes_Gx(sl, option_byte); + default: + return stlink_read_option_bytes_generic(sl, option_byte); + } +} + + +/** + * Write option bytes + * @param sl + * @param base option bytes to write + * @param addr of the memory mapped option bytes + * @param len of options bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f0( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { + int ret = 0; + + if (len < 12 || addr != STM32_F0_OPTION_BYTES_BASE) { + WLOG("Only full write of option bytes area is supported\n"); + return -1; + } + + clear_flash_error(sl); + + WLOG("Erasing option bytes\n"); + + /* erase option bytes */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_OPTWRE)); + ret = stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_STRT) | (1 << FLASH_CR_OPTWRE)); + if (ret) { + return ret; + } + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (ret) { + return ret; + } + + WLOG("Writing option bytes to %#10x\n", addr); + + /* Set the Option PG bit to enable programming */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTPG) | (1 << FLASH_CR_OPTWRE)); + + /* Use flash loader for write OP + * because flash memory writable by half word */ + flash_loader_t fl; + ret = stlink_flash_loader_init(sl, &fl); + if (ret) { + return ret; + } + ret = stlink_flash_loader_run(sl, &fl, addr, base, len); + if (ret) { + return ret; + } + + /* Reload option bytes */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OBL_LAUNCH)); + + return check_flash_error(sl); +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + /* Write options bytes */ + uint32_t val; + int ret = 0; + (void)len; + uint32_t data; + + clear_flash_error(sl); + + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); + + // Set Options Start bit + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + + // Reload options + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t flash_base = get_stm32l0_flash_base(sl); + uint32_t val; + uint32_t data; + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + while (len != 0) { + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, addr, data); + wait_flash_busy(sl); + + if ((ret = check_flash_error(sl))) { + break; + } + + len -= 4; + addr += 4; + base += 4; + } + + // Reload options + stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); + val |= (1 << STM32L0_FLASH_OBL_LAUNCH); + stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); + + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + + uint32_t val; + int ret = 0; + (void)addr; + (void)len; + + // Clear errors + clear_flash_error(sl); + + // write options bytes + uint32_t data; + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes 0x%04x\n", data); + stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); + + // set options start bit + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + + wait_flash_busy(sl); + ret = check_flash_error(sl); + + // apply options bytes immediate + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t option_byte; + int ret = 0; + (void)addr; + (void)len; + + // Clear errors + clear_flash_error(sl); + + write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); + + // write option byte, ensuring we dont lock opt, and set strt bit + stlink_write_debug32(sl, FLASH_F4_OPTCR, + (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | + (1 << FLASH_F4_OPTCR_START)); + + wait_flash_busy(sl); + ret = check_flash_error(sl); + + // option bytes are reloaded at reset only, no obl. */ + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t option_byte; + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), + addr); + write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); + ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); + + if (addr == 0) { + addr = FLASH_F7_OPTCR; + ILOG("No address provided, using %#10x\n", addr); + } + + if (addr == FLASH_F7_OPTCR) { + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + } else if (addr == FLASH_F7_OPTCR1) { + // Read FLASH_F7_OPTCR + uint32_t oldvalue; + stlink_read_debug32(sl, FLASH_F7_OPTCR, &oldvalue); + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_byte); + // Write FLASH_F7_OPTCR lock and start address + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (oldvalue & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + } else { + WLOG("WIP: write %#010x to address %#010x\n", option_byte, addr); + stlink_write_debug32(sl, addr, option_byte); + } + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, + addr); + + /* option bytes are reloaded at reset only, no obl. */ + + return ret; +} + +/** + * Write STM32H7xx option bytes + * @param sl + * @param base option bytes to write + * @param addr of the memory mapped option bytes + * @param len number of bytes to write (must be multiple of 4) + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t val; + uint32_t data; + + // Wait until previous flash option has completed + wait_flash_busy(sl); + + // Clear previous error + stlink_write_debug32(sl, FLASH_H7_OPTCCR, + 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + + while (len != 0) { + switch (addr) { + case FLASH_H7_REGS_ADDR + 0x20: // FLASH_OPTSR_PRG + case FLASH_H7_REGS_ADDR + 0x2c: // FLASH_PRAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x34: // FLASH_SCAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 + case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG + /* Write to FLASH_xxx_PRG registers */ + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + + /* Skip if the value in the CUR register is identical */ + stlink_read_debug32(sl, addr - 4, &val); + if (val == data) { + break; + } + + /* Write new option byte values and start modification */ + stlink_write_debug32(sl, addr, data); + stlink_read_debug32(sl, FLASH_H7_OPTCR, &val); + val |= (1 << FLASH_H7_OPTCR_OPTSTART); + stlink_write_debug32(sl, FLASH_H7_OPTCR, val); + + /* Wait for the option bytes modification to complete */ + do { + stlink_read_debug32(sl, FLASH_H7_OPTSR_CUR, &val); + } while ((val & (1 << FLASH_H7_OPTSR_OPT_BUSY)) != 0); + + /* Check for errors */ + if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { + stlink_write_debug32(sl, FLASH_H7_OPTCCR, + 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + return -1; + } + break; + + default: + /* Skip non-programmable registers */ + break; + } + + len -= 4; + addr += 4; + base += 4; + } + + return 0; +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len) { + int ret = -1; + + if (sl->option_base == 0) { + ELOG( + "Option bytes writing is currently not supported for connected chip\n"); + return (-1); + } + + if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { + ELOG("Option bytes start address out of Option bytes range\n"); + return (-1); + } + + if (addr + len > sl->option_base + sl->option_size) { + ELOG("Option bytes data too long\n"); + return (-1); + } + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return (-1); + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return (-1); + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + ret = stlink_write_option_bytes_f0(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_F4: + ret = stlink_write_option_bytes_f4(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_f7(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_L0: + ret = stlink_write_option_bytes_l0(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_L4: + ret = stlink_write_option_bytes_l4(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_G0: + case STLINK_FLASH_TYPE_G4: + ret = stlink_write_option_bytes_gx(sl, base, addr, len); + break; + case STLINK_FLASH_TYPE_H7: + ret = stlink_write_option_bytes_h7(sl, base, addr, len); + break; + default: + ELOG("Option bytes writing is currently not implemented for connected " + "chip\n"); + break; + } + + if (ret) { + ELOG("Flash option write failed!\n"); + } else { + ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + } + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register_f0(stlink_t *sl, + uint32_t option_control_register) { + int ret = 0; + uint16_t opt_val[8]; + unsigned protection, optiondata; + uint16_t user_options, user_data, rdp; + unsigned option_offset, user_data_offset; + + ILOG("Asked to write option control register %#10x to %#010x.\n", + option_control_register, FLASH_OBR); + + /* Clear errors */ + clear_flash_error(sl); + + /* Retrieve current values */ + ret = stlink_read_debug32(sl, FLASH_OBR, &optiondata); + if (ret) { + return ret; + } + ret = stlink_read_debug32(sl, FLASH_WRPR, &protection); + if (ret) { + return ret; + } + + /* Translate OBR value to flash store structure + * F0: RM0091, Option byte description, pp. 75-78 + * F1: PM0075, Option byte description, pp. 19-22 + * F3: RM0316, Option byte description, pp. 85-87 */ + switch(sl->chip_id) + { + case 0x422: /* STM32F30x */ + case 0x432: /* STM32F37x */ + case 0x438: /* STM32F303x6/8 and STM32F328 */ + case 0x446: /* STM32F303xD/E and STM32F398xE */ + case 0x439: /* STM32F302x6/8 */ + case 0x440: /* STM32F05x */ + case 0x444: /* STM32F03x */ + case 0x445: /* STM32F04x */ + case 0x448: /* STM32F07x */ + case 0x442: /* STM32F09x */ + option_offset = 6; + user_data_offset = 16; + rdp = 0x55AA; + break; + default: + option_offset = 0; + user_data_offset = 10; + rdp = 0x5AA5; + break; + } + + user_options = (option_control_register >> option_offset >> 2) & 0xFFFF; + user_data = (option_control_register >> user_data_offset) & 0xFFFF; + +#define VAL_WITH_COMPLEMENT(v) (uint16_t)(((v)&0xFF) | (((~(v))<<8)&0xFF00)) + + opt_val[0] = (option_control_register & (1 << 1/*OPT_READOUT*/)) ? 0xFFFF : rdp; + opt_val[1] = VAL_WITH_COMPLEMENT(user_options); + opt_val[2] = VAL_WITH_COMPLEMENT(user_data); + opt_val[3] = VAL_WITH_COMPLEMENT(user_data >> 8); + opt_val[4] = VAL_WITH_COMPLEMENT(protection); + opt_val[5] = VAL_WITH_COMPLEMENT(protection >> 8); + opt_val[6] = VAL_WITH_COMPLEMENT(protection >> 16); + opt_val[7] = VAL_WITH_COMPLEMENT(protection >> 24); + +#undef VAL_WITH_COMPLEMENT + + /* Write bytes and check errors */ + ret = stlink_write_option_bytes_f0(sl, (uint8_t*)opt_val, STM32_F0_OPTION_BYTES_BASE, sizeof(opt_val)); + if (ret) + return ret; + + ret = check_flash_error(sl); + if (!ret) { + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, + FLASH_OBR); + } + + return ret; +} + + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register1_f7(stlink_t *sl, + uint32_t option_control_register1) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#010x to %#010x.\n", + option_control_register1, FLASH_F7_OPTCR1); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + uint32_t current_control_register_value; + stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); + + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); + stlink_write_debug32( + sl, FLASH_F7_OPTCR, + (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, + FLASH_F7_OPTCR1); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register_f7(stlink_t *sl, + uint32_t option_control_register) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", + option_control_register, FLASH_F7_OPTCR); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, + FLASH_F7_OPTCR); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_control_register32(stlink_t *sl, + uint32_t option_control_register) { + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + ret = stlink_write_option_control_register_f0(sl, option_control_register); + break; + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_control_register_f7(sl, option_control_register); + break; + default: + ELOG("Option control register writing is currently not implemented for " + "connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register %#010x!\n", option_control_register); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_control_register1_32( + stlink_t *sl, uint32_t option_control_register1) { + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = + stlink_write_option_control_register1_f7(sl, option_control_register1); + break; + default: + ELOG("Option control register 1 writing is currently not implemented for " + "connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); + + lock_flash_option(sl); + lock_flash(sl); + + return (ret); +} + + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_bytes_boot_add_f7(stlink_t *sl, + uint32_t option_byte_boot_add) { + ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); + return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes_boot_add32(stlink_t *sl, + uint32_t option_bytes_boot_add) { + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); + break; + default: + ELOG("Option bytes boot address writing is currently not implemented for " + "connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { + WLOG("About to write option byte %#10x to %#10x.\n", option_byte, + sl->option_base); + return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, + 4); +} + +/** + * Write the given binary file with option bytes + * @param sl + * @param path readable file path, should be binary image + * @param addr of the memory mapped option bytes + * @return 0 on success, -ve on failure. + */ +int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, + stm32_addr_t addr) { + /* Write the file in flash at addr */ + int err; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; + + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return (-1); + } + + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); + + err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); + + return (err); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register1_f7(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register 1 byte from %#10x\n", + FLASH_F7_OPTCR1); + return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register1_32(stlink_t *sl, + uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + return stlink_read_option_control_register1_f7(sl, option_byte); + default: + return -1; + // return stlink_read_option_control_register1_generic(sl, option_byte); + } +} + + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option byte boot address\n"); + return stlink_read_option_control_register1_f7(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes boot address read is currently not supported for " + "connected chip\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F7: + return stlink_read_option_bytes_boot_add_f7(sl, option_byte); + default: + return -1; + // return stlink_read_option_bytes_boot_add_generic(sl, option_byte); + } +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f7(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); + return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f0(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); + return stlink_read_debug32(sl, FLASH_OBR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->flash_type) { + case STLINK_FLASH_TYPE_F0: + case STLINK_FLASH_TYPE_F1_XL: + return stlink_read_option_control_register_f0(sl, option_byte); + case STLINK_FLASH_TYPE_F7: + return stlink_read_option_control_register_f7(sl, option_byte); + default: + return -1; + } +} diff --git a/src/read_write.c b/src/read_write.c new file mode 100644 index 000000000..adcda6f3b --- /dev/null +++ b/src/read_write.c @@ -0,0 +1,142 @@ +#include +#include + +// Endianness +// https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html +// These functions encode and decode little endian uint16 and uint32 values. + +void write_uint32(unsigned char *buf, uint32_t ui) { + buf[0] = ui; + buf[1] = ui >> 8; + buf[2] = ui >> 16; + buf[3] = ui >> 24; +} + +void write_uint16(unsigned char *buf, uint16_t ui) { + buf[0] = (uint8_t)ui; + buf[1] = (uint8_t)(ui >> 8); +} + +uint32_t read_uint32(const unsigned char *c, const int pt) { + return ((uint32_t)c[pt]) | ((uint32_t)c[pt + 1] << 8) | + ((uint32_t)c[pt + 2] << 16) | ((uint32_t)c[pt + 3] << 24); +} + +uint16_t read_uint16(const unsigned char *c, const int pt) { + return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); +} + +int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { + int ret; + + ret = sl->backend->read_debug32(sl, addr, data); + if (!ret) + DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); + + return (ret); +} + +int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { + DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); + return sl->backend->write_debug32(sl, addr, data); +} + +int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); + + if (len % 4 != 0) { + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return (-1); + } + + return (sl->backend->write_mem32(sl, addr, len)); +} + +int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_read_mem32 ***\n"); + + if (len % 4 != 0) { // !!! never ever: fw gives just wrong values + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return (-1); + } + + return (sl->backend->read_mem32(sl, addr, len)); +} + +int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_write_mem8 ***\n"); + return (sl->backend->write_mem8(sl, addr, len)); +} + +int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { + DLOG("*** stlink_read_all_regs ***\n"); + return (sl->backend->read_all_regs(sl, regp)); +} + +int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { + DLOG("*** stlink_read_all_unsupported_regs ***\n"); + return (sl->backend->read_all_unsupported_regs(sl, regp)); +} + +int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { + DLOG("*** stlink_write_reg\n"); + return (sl->backend->write_reg(sl, reg, idx)); +} + +int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { + DLOG("*** stlink_read_reg\n"); + DLOG(" (%d) ***\n", r_idx); + + if (r_idx > 20 || r_idx < 0) { + fprintf(stderr, "Error: register index must be in [0..20]\n"); + return (-1); + } + + return (sl->backend->read_reg(sl, r_idx, regp)); +} + +int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, + struct stlink_reg *regp) { + int r_convert; + + DLOG("*** stlink_read_unsupported_reg\n"); + DLOG(" (%d) ***\n", r_idx); + + /* Convert to values used by STLINK_REG_DCRSR */ + if (r_idx >= 0x1C && + r_idx <= 0x1F) { // primask, basepri, faultmask, or control + r_convert = 0x14; + } else if (r_idx == 0x40) { // FPSCR + r_convert = 0x21; + } else if (r_idx >= 0x20 && r_idx < 0x40) { + r_convert = 0x40 + (r_idx - 0x20); + } else { + fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); + return (-1); + } + + return (sl->backend->read_unsupported_reg(sl, r_convert, regp)); +} + +int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, + struct stlink_reg *regp) { + int r_convert; + + DLOG("*** stlink_write_unsupported_reg\n"); + DLOG(" (%d) ***\n", r_idx); + + /* Convert to values used by STLINK_REG_DCRSR */ + if (r_idx >= 0x1C && + r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ + r_convert = r_idx; // the backend function handles this + } else if (r_idx == 0x40) { // FPSCR + r_convert = 0x21; + } else if (r_idx >= 0x20 && r_idx < 0x40) { + r_convert = 0x40 + (r_idx - 0x20); + } else { + fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); + return (-1); + } + + return (sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); +} From 4ce20d07e0fedd103a0f24f583ea591f8eb12694 Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Thu, 20 Jan 2022 13:46:42 +0400 Subject: [PATCH 1291/1435] stlink-org#1216 refactoring of common.c File divided to some parts. Functions with "flash" in names extracted to common_flash.c, with "option" extracted to option.c etc. Removed unnecessary headers. Removed one single function which was used nowhere. And so on. Project built under Windows and seems to be working. --- src/common.c | 5701 +++++++++----------------------------------- src/common_flash.c | 1 + src/flashloader.c | 1 + src/map_file.c | 7 + src/option.c | 1 + src/read_write.c | 1 + 6 files changed, 1090 insertions(+), 4622 deletions(-) diff --git a/src/common.c b/src/common.c index 6cbd217ef..0f8117fea 100644 --- a/src/common.c +++ b/src/common.c @@ -1,27 +1,17 @@ -#define DEBUG_FLASH 0 -#include -#include -#include -#include -#include - -#include +#include #include -#include #include #include #include - -#include -#include +#include +#include #include +#include #include - -#ifdef STLINK_HAVE_SYS_MMAN_H -#include -#else -#include -#endif +#include "common_flash.h" +#include "calculate.h" +#include "map_file.h" +#include "common.h" #ifndef O_BINARY #define O_BINARY 0 @@ -31,4922 +21,1389 @@ #define __attribute__(x) #endif -#define BANK_1 0 -#define BANK_2 1 - -/* stm32f FPEC flash controller interface, pm0063 manual */ -// TODO - all of this needs to be abstracted out.... -// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, -// August 2012) -#define FLASH_REGS_ADDR 0x40022000 -#define FLASH_REGS_SIZE 0x28 - -#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) -#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) -#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) -#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) -#define FLASH_CR (FLASH_REGS_ADDR + 0x10) -#define FLASH_AR (FLASH_REGS_ADDR + 0x14) -#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) -#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) - -// STM32F10x_XL has two flash memory banks with separate registers to control -// the second bank. -#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) -#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) -#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) -#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) - -// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... -#define FLASH_RDPTR_KEY 0x00a5 -#define FLASH_KEY1 0x45670123 -#define FLASH_KEY2 0xcdef89ab - -#define FLASH_L0_PRGKEY1 0x8c9daebf -#define FLASH_L0_PRGKEY2 0x13141516 - -#define FLASH_L0_PEKEY1 0x89abcdef -#define FLASH_L0_PEKEY2 0x02030405 - -#define FLASH_OPTKEY1 0x08192A3B -#define FLASH_OPTKEY2 0x4C5D6E7F - -#define FLASH_F0_OPTKEY1 0x45670123 -#define FLASH_F0_OPTKEY2 0xCDEF89AB - -#define FLASH_L0_OPTKEY1 0xFBEAD9C8 -#define FLASH_L0_OPTKEY2 0x24252627 - -#define FLASH_SR_BSY 0 -#define FLASH_SR_PG_ERR 2 -#define FLASH_SR_WRPRT_ERR 4 -#define FLASH_SR_EOP 5 - -#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) - -#define FLASH_CR_PG 0 -#define FLASH_CR_PER 1 -#define FLASH_CR_MER 2 -#define FLASH_CR_OPTPG 4 -#define FLASH_CR_OPTER 5 -#define FLASH_CR_STRT 6 -#define FLASH_CR_LOCK 7 -#define FLASH_CR_OPTWRE 9 -#define FLASH_CR_OBL_LAUNCH 13 - -#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) -#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) -#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) -#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) -#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) -#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) -#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) -#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) -#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) -#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) -#define FLASH_L1_FPRG 10 -#define FLASH_L1_PROG 3 - -// Flash registers common to STM32G0 and STM32G4 series. -#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) -#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) -#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) -#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) -#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) -#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) -#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) - -// G0 (RM0444 Table 1, sec 3.7) -// Mostly the same as G4 chips, but the notation -// varies a bit after the 'OPTR' register. -#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) -#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) -#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) -#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) -#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) -#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) -#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) - -// G4 (RM0440 Table 17, sec 3.7.19) -// Mostly the same as STM32G0 chips, but there are a few extra -// registers because 'cat 3' devices can have two Flash banks. -#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) -#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) -#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) -#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) -#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) -#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) -#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) -#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) -#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) -#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) -#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) - -// G0/G4 FLASH control register -#define STM32Gx_FLASH_CR_PG (0) /* Program */ -#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ -#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ -#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ -#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define STM32Gx_FLASH_CR_STRT (16) /* Start */ -#define STM32Gx_FLASH_CR_OPTSTRT \ - (17) /* Start of modification of option bytes */ -#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ -#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ -#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ -#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ -#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ - -// G0/G4 FLASH status register -#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) -#define STM32Gx_FLASH_SR_PROGERR (3) -#define STM32Gx_FLASH_SR_WRPERR (4) -#define STM32Gx_FLASH_SR_PGAERR (5) -#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ - -// G4 FLASH option register -#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ - -// WB (RM0434) -#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) -#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) -#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) -#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) -#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) -#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) -#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) -#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) -#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) -#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) -#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) - -// WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ -// WB Flash status register. -#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ -#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ -#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ -#define STM32WB_FLASH_SR_BSY (16) /* Busy */ - -// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) -#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) -#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) -#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) -#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) -#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) - -#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ -#define STM32L4_FLASH_SR_PROGERR 3 -#define STM32L4_FLASH_SR_WRPERR 4 -#define STM32L4_FLASH_SR_PGAERR 5 -#define STM32L4_FLASH_SR_BSY 16 - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ -#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ -// Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ - (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) -// Page is fully specified by BKER and PNB -#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) - -#define STM32L4_FLASH_OPTR_DUALBANK 21 - -// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf -#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) - -#define STM32L0_FLASH_PELOCK (0) -#define STM32L0_FLASH_OPTLOCK (2) -#define STM32L0_FLASH_OBL_LAUNCH (18) - -#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 -#define STM32L0_FLASH_SR_WRPERR 8 -#define STM32L0_FLASH_SR_PGAERR 9 -#define STM32L0_FLASH_SR_NOTZEROERR 16 - -#define FLASH_ACR_OFF ((uint32_t)0x00) -#define FLASH_PECR_OFF ((uint32_t)0x04) -#define FLASH_PDKEYR_OFF ((uint32_t)0x08) -#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) -#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) -#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) -#define FLASH_SR_OFF ((uint32_t)0x18) -#define FLASH_OBR_OFF ((uint32_t)0x1c) -#define FLASH_WRPR_OFF ((uint32_t)0x20) - -// STM32F7 -#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) -#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) -#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) -#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) -#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) -#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) -#define FLASH_F7_OPTCR_LOCK 0 -#define FLASH_F7_OPTCR_START 1 -#define FLASH_F7_CR_STRT 16 -#define FLASH_F7_CR_LOCK 31 -#define FLASH_F7_CR_SER 1 -#define FLASH_F7_CR_SNB 3 -#define FLASH_F7_CR_SNB_MASK 0xf8 -#define FLASH_F7_SR_BSY 16 -#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ -#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ -#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ -#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ -#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ -#define FLASH_F7_SR_EOP 0 /* End of operation */ -#define FLASH_F7_OPTCR1_BOOT_ADD0 0 -#define FLASH_F7_OPTCR1_BOOT_ADD1 16 - -#define FLASH_F7_SR_ERROR_MASK \ - ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ - (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ - (1 << FLASH_F7_SR_OP_ERR)) - -// STM32F4 -#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) -#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) -#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) -#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) -#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) -#define FLASH_F4_OPTCR_LOCK 0 -#define FLASH_F4_OPTCR_START 1 -#define FLASH_F4_CR_STRT 16 -#define FLASH_F4_CR_LOCK 31 -#define FLASH_F4_CR_SER 1 -#define FLASH_F4_CR_SNB 3 -#define FLASH_F4_CR_SNB_MASK 0xf8 -#define FLASH_F4_SR_ERROR_MASK 0x000000F0 -#define FLASH_F4_SR_PGAERR 5 -#define FLASH_F4_SR_WRPERR 4 -#define FLASH_F4_SR_BSY 16 - -// STM32F2 -#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) -#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) -#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) -#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) -#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) -#define FLASH_F2_OPT_LOCK_BIT (1u << 0) -#define FLASH_F2_CR_STRT 16 -#define FLASH_F2_CR_LOCK 31 - -#define FLASH_F2_CR_SER 1 -#define FLASH_F2_CR_SNB 3 -#define FLASH_F2_CR_SNB_MASK 0x78 -#define FLASH_F2_SR_BSY 16 - -// STM32H7xx -#define FLASH_H7_CR_LOCK 0 -#define FLASH_H7_CR_PG 1 -#define FLASH_H7_CR_SER 2 -#define FLASH_H7_CR_BER 3 -#define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7Ax ? 5 : 7) -#define FLASH_H7_CR_SNB 8 -#define FLASH_H7_CR_SNB_MASK 0x700 - -#define FLASH_H7_SR_QW 2 -#define FLASH_H7_SR_WRPERR 17 -#define FLASH_H7_SR_PGSERR 18 -#define FLASH_H7_SR_STRBERR 19 -#define FLASH_H7_SR_ERROR_MASK \ - ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ - (1 << FLASH_H7_SR_WRPERR)) - -#define FLASH_H7_OPTCR_OPTLOCK 0 -#define FLASH_H7_OPTCR_OPTSTART 1 -#define FLASH_H7_OPTCR_MER 4 - -#define FLASH_H7_OPTSR_OPT_BUSY 0 -#define FLASH_H7_OPTSR_OPTCHANGEERR 30 - -#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 - -#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) -#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) -#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) -#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) -#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) -#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) -#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) -#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) -#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) -#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) -#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) -#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) -#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) -#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) -#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) - -#define STM32F0_DBGMCU_CR 0xE0042004 -#define STM32F0_DBGMCU_CR_IWDG_STOP 8 -#define STM32F0_DBGMCU_CR_WWDG_STOP 9 - -#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 -#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 -#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 - -#define STM32L0_DBGMCU_APB1_FZ 0x40015808 -#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 -#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 - -#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 -#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 - -#define STM32WB_DBGMCU_APB1FZR1 0xE004203C -#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 -#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 - -#define STM32F1_RCC_AHBENR 0x40021014 -#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32F4_RCC_AHB1ENR 0x40023830 -#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN - -#define STM32G0_RCC_AHBENR 0x40021038 -#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32G4_RCC_AHB1ENR 0x40021048 -#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32L0_RCC_AHBENR 0x40021030 -#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN - -#define STM32H7_RCC_AHB1ENR 0x58024538 -#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32WB_RCC_AHB1ENR 0x58000048 -#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define L1_WRITE_BLOCK_SIZE 0x80 -#define L0_WRITE_BLOCK_SIZE 0x40 - -// Endianness -// https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html -// These functions encode and decode little endian uint16 and uint32 values. - -void write_uint32(unsigned char *buf, uint32_t ui) { - buf[0] = ui; - buf[1] = ui >> 8; - buf[2] = ui >> 16; - buf[3] = ui >> 24; -} +// Private structs and functions defines +struct stlink_fread_worker_arg { + int fd; +}; -void write_uint16(unsigned char *buf, uint16_t ui) { - buf[0] = (uint8_t)ui; - buf[1] = (uint8_t)(ui >> 8); -} +struct stlink_fread_ihex_worker_arg { + FILE *file; + uint32_t addr; + uint32_t lba; + uint8_t buf[16]; + uint8_t buf_pos; +}; -uint32_t read_uint32(const unsigned char *c, const int pt) { - return ((uint32_t)c[pt]) | ((uint32_t)c[pt + 1] << 8) | - ((uint32_t)c[pt + 2] << 16) | ((uint32_t)c[pt + 3] << 24); -} +typedef bool (*save_block_fn)(void *arg, uint8_t *block, ssize_t len); -uint16_t read_uint16(const unsigned char *c, const int pt) { - return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); -} +static void stop_wdg_in_debug(stlink_t *); +int stlink_jtag_reset(stlink_t *, int); +int stlink_soft_reset(stlink_t *, int); +void _parse_version(stlink_t *, stlink_version_t *); +static uint8_t stlink_parse_hex(const char *); +static int stlink_read(stlink_t *, stm32_addr_t, size_t, save_block_fn, void *); +static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *, int, stm32_addr_t); +static bool stlink_fread_ihex_worker(void *, uint8_t *, ssize_t); +static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *); +static bool stlink_fread_worker(void *, uint8_t *, ssize_t); +// End of private structs and functions defines + +// Functions below are defined in stlink.h (see line num before function) +// 252 +void stlink_close(stlink_t *sl) { + DLOG("*** stlink_close ***\n"); -static uint32_t get_stm32l0_flash_base(stlink_t *sl) { - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_L0: - case STLINK_CHIPID_STM32_L0_CAT5: - case STLINK_CHIPID_STM32_L0_CAT2: - case STLINK_CHIPID_STM32_L011: - return (STM32L0_FLASH_REGS_ADDR); + if (!sl) { + return; + } - case STLINK_CHIPID_STM32_L1_CAT2: - case STLINK_CHIPID_STM32_L1_MD: - case STLINK_CHIPID_STM32_L1_MD_PLUS: - case STLINK_CHIPID_STM32_L1_MD_PLUS_HD: - return (STM32L_FLASH_REGS_ADDR); + sl->backend->close(sl); + free(sl); +} +// 250 +int stlink_exit_debug_mode(stlink_t *sl) { + DLOG("*** stlink_exit_debug_mode ***\n"); - default: - WLOG("Flash base use default L0 address\n"); - return (STM32L0_FLASH_REGS_ADDR); + if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN && + sl->core_stat != TARGET_RESET) { + // stop debugging if the target has been identified + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); } -} -static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { - uint32_t rdp; - stlink_read_debug32(sl, FLASH_WRPR, &rdp); - return (rdp & 0xff); + return (sl->backend->exit_debug_mode(sl)); } - -static inline uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { - uint32_t reg, res; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - } else { - reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; +//248 +int stlink_enter_swd_mode(stlink_t *sl) { + DLOG("*** stlink_enter_swd_mode ***\n"); + return (sl->backend->enter_swd_mode(sl)); +} +// 271 +// Force the core into the debug mode -> halted state. +int stlink_force_debug(stlink_t *sl) { + DLOG("*** stlink_force_debug_mode ***\n"); + int res = sl->backend->force_debug(sl); + if (res) { + return (res); } + // Stop the watchdogs in the halted state for suppress target reboot + stop_wdg_in_debug(sl); + return (0); +} +// 251 +int stlink_exit_dfu_mode(stlink_t *sl) { + DLOG("*** stlink_exit_dfu_mode ***\n"); + return (sl->backend->exit_dfu_mode(sl)); +} +// 253 +int stlink_core_id(stlink_t *sl) { + int ret; - stlink_read_debug32(sl, reg, &res); + DLOG("*** stlink_core_id ***\n"); + ret = sl->backend->core_id(sl); -#if DEBUG_FLASH - fprintf(stdout, "CR:0x%x\n", res); -#endif - return (res); -} + if (ret == -1) { + ELOG("Failed to read core_id\n"); + return (ret); + } -static inline unsigned int is_flash_locked(stlink_t *sl) { - /* return non zero for true */ - uint32_t cr_lock_shift; - uint32_t cr_reg; - uint32_t n; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - cr_lock_shift = FLASH_H7_CR_LOCK; - } else { - ELOG("unsupported flash method, abort\n"); - return (-1); + if (sl->verbose > 2) { + stlink_print_data(sl); } - stlink_read_debug32(sl, cr_reg, &n); - return (n & (1u << cr_lock_shift)); + DLOG("core_id = 0x%08x\n", sl->core_id); + return (ret); } +// 287 +// stlink_chip_id() is called by stlink_load_device_params() +// do not call this procedure directly. +int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { + int ret; + cortex_m3_cpuid_t cpu_id; -static void unlock_flash(stlink_t *sl) { - uint32_t key_reg, key2_reg = 0; - uint32_t flash_key1 = FLASH_KEY1; - uint32_t flash_key2 = FLASH_KEY2; - /* The unlock sequence consists of 2 write cycles where 2 key values are - * written to the FLASH_KEYR register. An invalid sequence results in a - * definitive lock of the FPEC block until next reset. - */ - - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { - key_reg = FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - key_reg = FLASH_KEYR; - key2_reg = FLASH_KEYR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - key_reg = FLASH_F4_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - key_reg = FLASH_F7_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; - flash_key1 = FLASH_L0_PEKEY1; - flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - key_reg = STM32L4_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - key_reg = STM32Gx_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - key_reg = STM32WB_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - key_reg = FLASH_H7_KEYR1; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - key2_reg = FLASH_H7_KEYR2; - } - } else { - ELOG("unsupported flash method, abort\n"); - return; + // Read the CPU ID to determine where to read the core id + if (stlink_cpu_id(sl, &cpu_id) || + cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) { + ELOG("Can not connect to target. Please use \'connect under reset\' and " + "try again\n"); + return -1; } - stlink_write_debug32(sl, key_reg, flash_key1); - stlink_write_debug32(sl, key_reg, flash_key2); + /* + * the chip_id register in the reference manual have + * DBGMCU_IDCODE / DBG_IDCODE name + * + */ + + if ((sl->core_id == STM32H7_CORE_ID || sl->core_id == STM32H7_CORE_ID_JTAG) && + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { + // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + ret = stlink_read_debug32(sl, 0x5c001000, chip_id); + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0 || + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0P) { + // STM32F0 (RM0091, pg914; RM0360, pg713) + // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) + // STM32G0 (RM0444, pg1367) + ret = stlink_read_debug32(sl, 0x40015800, chip_id); + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) { + // STM32L5 (RM0438, pg2157) + ret = stlink_read_debug32(sl, 0xE0044000, chip_id); + } else /* СM3, СM4, CM7 */ { + // default chipid address - if (key2_reg) { - stlink_write_debug32(sl, key2_reg, flash_key1); - stlink_write_debug32(sl, key2_reg, flash_key2); + // STM32F1 (RM0008, pg1087; RM0041, pg681) + // STM32F2 (RM0033, pg1326) + // STM32F3 (RM0316, pg1095; RM0313, pg874) + // STM32F7 (RM0385, pg1676; RM0410, pg1912) + // STM32L1 (RM0038, pg861) + // STM32L4 (RM0351, pg1840; RM0394, pg1560) + // STM32G4 (RM0440, pg2086) + // STM32WB (RM0434, pg1406) + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); } -} -/* unlock flash if already locked */ -static int unlock_flash_if(stlink_t *sl) { - if (is_flash_locked(sl)) { - unlock_flash(sl); + if (ret || !(*chip_id)) { + *chip_id = 0; + ret = ret?ret:-1; + ELOG("Could not find chip id!\n"); + } else { + *chip_id = (*chip_id) & 0xfff; - if (is_flash_locked(sl)) { - WLOG("Failed to unlock flash!\n"); - return (-1); + // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for + // F2/F4 + if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) { + *chip_id = 0x413; } } - DLOG("Successfully unlocked flash\n"); - return (0); + return (ret); } +// 288 +/** + * Cortex M tech ref manual, CPUID register description + * @param sl stlink context + * @param cpuid pointer to the result object + */ +int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { + uint32_t raw; -static void lock_flash(stlink_t *sl) { - uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; - uint32_t cr_mask = 0xffffffffu; - - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - cr_reg = FLASH_CR; - cr2_reg = FLASH_CR2; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr2_reg = FLASH_H7_CR2; - } - cr_lock_shift = FLASH_H7_CR_LOCK; - cr_mask = ~(1u << FLASH_H7_CR_SER); - } else { - ELOG("unsupported flash method, abort\n"); - return; + if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { + cpuid->implementer_id = 0; + cpuid->variant = 0; + cpuid->part = 0; + cpuid->revision = 0; + return (-1); } - stlink_read_debug32(sl, cr_reg, &n); - n &= cr_mask; - n |= (1u << cr_lock_shift); - stlink_write_debug32(sl, cr_reg, n); - - if (cr2_reg) { - n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift); - stlink_write_debug32(sl, cr2_reg, n); - } + cpuid->implementer_id = (raw >> 24) & 0x7f; + cpuid->variant = (raw >> 20) & 0xf; + cpuid->part = (raw >> 4) & 0xfff; + cpuid->revision = raw & 0xf; + return (0); } +// 303 +/** + * Reads and decodes the flash parameters, as dynamically as possible + * @param sl + * @return 0 for success, or -1 for unsupported core type. + */ +int stlink_load_device_params(stlink_t *sl) { + // This seems to normally work so is unnecessary info for a normal user. + // Demoted to debug. -- REW + DLOG("Loading device parameters....\n"); + const struct stlink_chipid_params *params = NULL; + stlink_core_id(sl); + uint32_t flash_size; -static bool is_flash_option_locked(stlink_t *sl) { - uint32_t optlock_shift, optcr_reg; - int active_bit_level = 1; - uint32_t n; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; /* bit is "option write enable", not lock */ - break; - case STLINK_FLASH_TYPE_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_F7: - optcr_reg = FLASH_F7_OPTCR; - optlock_shift = FLASH_F7_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_L0: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STLINK_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_WB: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; + if (stlink_chip_id(sl, &sl->chip_id)) { + return (-1); } - stlink_read_debug32(sl, optcr_reg, &n); + params = stlink_chipid_get_params(sl->chip_id); - if (active_bit_level == 0) { - return (!(n & (1u << optlock_shift))); + if (params == NULL) { + WLOG("unknown chip id! %#x\n", sl->chip_id); + return (-1); } - return (n & (1u << optlock_shift)); -} - -static int lock_flash_option(stlink_t *sl) { - uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; - int active_bit_level = 1; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; - break; - case STLINK_FLASH_TYPE_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_F7: - optcr_reg = FLASH_F7_OPTCR; - optlock_shift = FLASH_F7_OPTCR_LOCK; - break; - case STLINK_FLASH_TYPE_L0: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STLINK_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_WB: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - case STLINK_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optcr2_reg = FLASH_H7_OPTCR2; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; + if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { + WLOG("Invalid flash type, please check device declaration\n"); + sl->flash_size = 0; + return (0); } - stlink_read_debug32(sl, optcr_reg, &n); + // These are fixed... + sl->flash_base = STM32_FLASH_BASE; + sl->sram_base = STM32_SRAM_BASE; + stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size); - if (active_bit_level == 0) { - n &= ~(1u << optlock_shift); - } else { - n |= (1u << optlock_shift); + if (params->flash_size_reg & 2) { + flash_size = flash_size >> 16; } - stlink_write_debug32(sl, optcr_reg, n); - - if (optcr2_reg) { - stlink_read_debug32(sl, optcr2_reg, &n); + flash_size = flash_size & 0xffff; - if (active_bit_level == 0) { - n &= ~(1u << optlock_shift); + if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MD || + sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || + sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS) && + (flash_size == 0)) { + sl->flash_size = 128 * 1024; + } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { + sl->flash_size = (flash_size & 0xff) * 1024; + } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_MD_PLUS_HD) { + // 0 is 384k and 1 is 256k + if (flash_size == 0) { + sl->flash_size = 384 * 1024; } else { - n |= (1u << optlock_shift); + sl->flash_size = 256 * 1024; } - - stlink_write_debug32(sl, optcr2_reg, n); + } else { + sl->flash_size = flash_size * 1024; } - return (0); -} - -static int unlock_flash_option(stlink_t *sl) { - uint32_t optkey_reg, optkey2_reg = 0; - uint32_t optkey1 = FLASH_OPTKEY1; - uint32_t optkey2 = FLASH_OPTKEY2; - - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - optkey_reg = FLASH_OPTKEYR; - optkey1 = FLASH_F0_OPTKEY1; - optkey2 = FLASH_F0_OPTKEY2; - break; - case STLINK_FLASH_TYPE_F4: - optkey_reg = FLASH_F4_OPT_KEYR; - break; - case STLINK_FLASH_TYPE_F7: - optkey_reg = FLASH_F7_OPT_KEYR; - break; - case STLINK_FLASH_TYPE_L0: - optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; - optkey1 = FLASH_L0_OPTKEY1; - optkey2 = FLASH_L0_OPTKEY2; - break; - case STLINK_FLASH_TYPE_L4: - optkey_reg = STM32L4_FLASH_OPTKEYR; - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - optkey_reg = STM32Gx_FLASH_OPTKEYR; - break; - case STLINK_FLASH_TYPE_WB: - optkey_reg = STM32WB_FLASH_OPT_KEYR; - break; - case STLINK_FLASH_TYPE_H7: - optkey_reg = FLASH_H7_OPT_KEYR; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optkey2_reg = FLASH_H7_OPT_KEYR2; - break; - default: - ELOG("unsupported flash method, abort\n"); - return (-1); - } - - stlink_write_debug32(sl, optkey_reg, optkey1); - stlink_write_debug32(sl, optkey_reg, optkey2); + sl->flash_type = params->flash_type; + sl->flash_pgsz = params->flash_pagesize; + sl->sram_size = params->sram_size; + sl->sys_base = params->bootrom_base; + sl->sys_size = params->bootrom_size; + sl->option_base = params->option_base; + sl->option_size = params->option_size; + sl->chip_flags = params->flags; - if (optkey2_reg) { - stlink_write_debug32(sl, optkey2_reg, optkey1); - stlink_write_debug32(sl, optkey2_reg, optkey2); + // medium and low devices have the same chipid. ram size depends on flash + // size. STM32F100xx datasheet Doc ID 16455 Table 2 + if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD && + sl->flash_size < 64 * 1024) { + sl->sram_size = 0x1000; } - return (0); -} + if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { + uint32_t flash_optr; + stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); -static int unlock_flash_option_if(stlink_t *sl) { - if (is_flash_option_locked(sl)) { - if (unlock_flash_option(sl)) { - ELOG("Could not unlock flash option!\n"); - return (-1); + if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { + sl->flash_pgsz <<= 1; } + } - if (is_flash_option_locked(sl)) { - ELOG("Failed to unlock flash option!\n"); - return (-1); - } + // H7 devices with small flash has one bank + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && + sl->flash_type == STLINK_FLASH_TYPE_H7) { + if ((sl->flash_size / sl->flash_pgsz) <= 1) + sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; } - DLOG("Successfully unlocked flash option\n"); + ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", + params->description, (unsigned)(sl->sram_size / 1024), + (unsigned)(sl->flash_size / 1024), + (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) + : (unsigned)(sl->flash_pgsz / 1024), + (sl->flash_pgsz < 1024) ? "byte" : "KiB"); + return (0); } +// 254 +int stlink_reset(stlink_t *sl, enum reset_type type) { + uint32_t dhcsr; + unsigned timeout; -static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, x; - - x = read_flash_cr(sl, bank); - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - x &= ~STM32L4_FLASH_CR_OPBITS; - x |= (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - x |= (1 << FLASH_H7_CR_PG); - } else { - cr_reg = FLASH_CR; - x = (1 << FLASH_CR_PG); - } + DLOG("*** stlink_reset ***\n"); - stlink_write_debug32(sl, cr_reg, x); -} + sl->core_stat = TARGET_RESET; -static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, n; - uint32_t bit = FLASH_CR_PG; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - bit = FLASH_H7_CR_PG; - } else { - cr_reg = FLASH_CR; + if (type == RESET_AUTO) { + // clear S_RESET_ST in DHCSR register for reset state detection + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); } - n = read_flash_cr(sl, bank) & ~(1 << bit); - stlink_write_debug32(sl, cr_reg, n); -} - -static void set_flash_cr_per(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, val; - - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + if (type == RESET_HARD || type == RESET_AUTO) { + // hardware target reset + if (sl->version.stlink_v > 1) { + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(100); + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); + } + sl->backend->reset(sl); + usleep(10000); } - stlink_read_debug32(sl, cr_reg, &val); - val |= (1 << FLASH_CR_PER); - stlink_write_debug32(sl, cr_reg, val); -} - -static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { - uint32_t cr_reg; + if (type == RESET_AUTO) { + /* Check if the S_RESET_ST bit is set in DHCSR + * This means that a reset has occurred + * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; - } + dhcsr = 0; + int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) { + // reset not done yet + // try reset through AIRCR so that NRST does not need to be connected - const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER); - stlink_write_debug32(sl, cr_reg, n); -} + WLOG("NRST is not connected\n"); + DLOG("Using reset through SYSRESETREQ\n"); + return stlink_soft_reset(sl, 0); + } -static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { - uint32_t val, cr_reg, cr_mer, cr_pg; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); - cr_pg = (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_mer = (1 << STM32Gx_FLASH_CR_MER1); - - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); + // waiting for reset the S_RESET_ST bit within 500ms + timeout = time_ms() + 500; + while (time_ms() < timeout) { + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + return (0); + } } - cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_mer = (1 << FLASH_CR_MER); - cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - cr_mer = (1 << FLASH_H7_CR_BER); - cr_pg = (1 << FLASH_H7_CR_PG); - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; - cr_mer = (1 << FLASH_CR_MER); - cr_pg = (1 << FLASH_CR_PG); + return (-1); } - stlink_read_debug32(sl, cr_reg, &val); - - if (val & cr_pg) { - // STM32F030 will drop MER bit if PG was set - val &= ~cr_pg; - stlink_write_debug32(sl, cr_reg, val); + if (type == RESET_SOFT || type == RESET_SOFT_AND_HALT) { + return stlink_soft_reset(sl, (type == RESET_SOFT_AND_HALT)); } - if (v) { - val |= cr_mer; - } else { - val &= ~cr_mer; + return (0); +} +// 255 +int stlink_run(stlink_t *sl, enum run_type type) { + struct stlink_reg rr; + DLOG("*** stlink_run ***\n"); + + /* Make sure we are in Thumb mode + * Cortex-M chips don't support ARM mode instructions + * xPSR may be incorrect if the vector table has invalid data */ + stlink_read_reg(sl, 16, &rr); + if ((rr.xpsr & (1 << 24)) == 0) { + ILOG("Go to Thumb mode\n"); + stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); } - stlink_write_debug32(sl, cr_reg, val); + return (sl->backend->run(sl, type)); } - -static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { - uint32_t val, cr_reg, cr_strt; - - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - cr_reg = FLASH_F4_CR; - cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_strt = (1 << STM32L4_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_strt = (1 << STM32Gx_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - cr_reg = STM32WB_FLASH_CR; - cr_strt = (1 << STM32WB_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; - cr_strt = (1 << FLASH_CR_STRT); +// 273 +int stlink_set_swdclk(stlink_t *sl, int freq_khz) { + DLOG("*** set_swdclk ***\n"); + return (sl->backend->set_swdclk(sl, freq_khz)); +} +// 293 +// this function is called by stlink_status() +// do not call stlink_core_stat() directly, always use stlink_status() +void stlink_core_stat(stlink_t *sl) { + switch (sl->core_stat) { + case TARGET_RUNNING: + DLOG(" core status: running\n"); + return; + case TARGET_HALTED: + DLOG(" core status: halted\n"); + return; + case TARGET_RESET: + DLOG(" core status: reset\n"); + return; + case TARGET_DEBUG_RUNNING: + DLOG(" core status: debug running\n"); + return; + default: + DLOG(" core status: unknown\n"); } +} +// 256 +int stlink_status(stlink_t *sl) { + int ret; - stlink_read_debug32(sl, cr_reg, &val); - val |= cr_strt; - stlink_write_debug32(sl, cr_reg, val); + DLOG("*** stlink_status ***\n"); + ret = sl->backend->status(sl); + stlink_core_stat(sl); + return (ret); } +// 257 +int stlink_version(stlink_t *sl) { + DLOG("*** looking up stlink version\n"); -static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { - uint32_t res, sr_reg; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; - } else { - ELOG("method 'read_flash_sr' is unsupported\n"); + if (sl->backend->version(sl)) { return (-1); } - stlink_read_debug32(sl, sr_reg, &res); - return (res); -} + _parse_version(sl, &sl->version); -static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { - uint32_t sr_reg; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; - } else { - ELOG("method 'write_flash_sr' is unsupported\n"); - return (-1); + DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, + STLINK_USB_VID_ST); + DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); + DLOG("stlink version = 0x%x\n", sl->version.stlink_v); + DLOG("jtag version = 0x%x\n", sl->version.jtag_v); + DLOG("swim version = 0x%x\n", sl->version.swim_v); + + if (sl->version.jtag_v == 0) { + WLOG(" warning: stlink doesn't support JTAG/SWD interface\n"); } - return stlink_write_debug32(sl, sr_reg, val); + return (0); } +// 272 +int stlink_target_voltage(stlink_t *sl) { + int voltage = -1; + DLOG("*** reading target voltage\n"); -static inline unsigned int is_flash_busy(stlink_t *sl) { - uint32_t sr_busy_shift; - unsigned int res; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_L0)) { - sr_busy_shift = FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { - sr_busy_shift = FLASH_F4_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { - sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - sr_busy_shift = STM32L4_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - sr_busy_shift = STM32Gx_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - sr_busy_shift = STM32WB_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - sr_busy_shift = FLASH_H7_SR_QW; + if (sl->backend->target_voltage != NULL) { + voltage = sl->backend->target_voltage(sl); + + if (voltage != -1) { + DLOG("target voltage = %imV\n", voltage); + } else { + DLOG("error reading target voltage\n"); + } } else { - ELOG("method 'is_flash_busy' is unsupported\n"); - return (-1); + DLOG("reading voltage not supported by backend\n"); } - res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); + return (voltage); +} +// 299 +bool stlink_is_core_halted(stlink_t *sl) { + stlink_status(sl); + return (sl->core_stat == TARGET_HALTED); +} +// 269 +int stlink_step(stlink_t *sl) { + DLOG("*** stlink_step ***\n"); + return (sl->backend->step(sl)); +} +// 270 +int stlink_current_mode(stlink_t *sl) { + int mode = sl->backend->current_mode(sl); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); + switch (mode) { + case STLINK_DEV_DFU_MODE: + DLOG("stlink current mode: dfu\n"); + return (mode); + case STLINK_DEV_DEBUG_MODE: + DLOG("stlink current mode: debug (jtag or swd)\n"); + return (mode); + case STLINK_DEV_MASS_MODE: + DLOG("stlink current mode: mass\n"); + return (mode); } - return (res); + DLOG("stlink mode: unknown!\n"); + return (STLINK_DEV_UNKNOWN_MODE); } - -static void wait_flash_busy(stlink_t *sl) { - // TODO: add some delays here - while (is_flash_busy(sl)) - ; +// 274 +int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { + DLOG("*** stlink_trace_enable ***\n"); + return (sl->backend->trace_enable(sl, frequency)); } +// 275 +int stlink_trace_disable(stlink_t *sl) { + DLOG("*** stlink_trace_disable ***\n"); + return (sl->backend->trace_disable(sl)); +} +// 276 +int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { + return (sl->backend->trace_read(sl, buf, size)); +} +// 294 +void stlink_print_data(stlink_t *sl) { + if (sl->q_len <= 0 || sl->verbose < UDEBUG) { + return; + } -static void wait_flash_busy_progress(stlink_t *sl) { - int i = 0; - fprintf(stdout, "Mass erasing"); - fflush(stdout); - - while (is_flash_busy(sl)) { - usleep(10000); - i++; + if (sl->verbose > 2) { + DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); + } - if (i % 100 == 0) { - fprintf(stdout, "."); - fflush(stdout); + for (int i = 0; i < sl->q_len; i++) { + if (i % 16 == 0) { + /* + if (sl->q_data_dir == Q_DATA_OUT) { + fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); + } else { + fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); + } + */ } + // DLOG(" %02x", (unsigned int) sl->q_buf[i]); + fprintf(stderr, " %02x", (unsigned int)sl->q_buf[i]); } - - fprintf(stdout, "\n"); -} - -static void clear_flash_error(stlink_t *sl) { - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_F4: - write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_F7: - write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_L0: - write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_L4: - write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); - break; - case STLINK_FLASH_TYPE_H7: - write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); - } - break; - case STLINK_FLASH_TYPE_WB: - write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); - break; - default: - break; - } + // DLOG("\n\n"); + fprintf(stderr, "\n"); } +// 283 +int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, + stm32_addr_t addr) { + // write the file in sram at addr -static int check_flash_error(stlink_t *sl) { - uint32_t res = 0; - uint32_t WRPERR, PROGERR, PGAERR; + int error = -1; + size_t off; + size_t len; - WRPERR = PROGERR = PGAERR = 0; + // check addr range is inside the sram + if (addr < sl->sram_base) { + fprintf(stderr, "addr too low\n"); + goto on_error; + } else if ((addr + length) < addr) { + fprintf(stderr, "addr overruns\n"); + goto on_error; + } else if ((addr + length) > (sl->sram_base + sl->sram_size)) { + fprintf(stderr, "addr too high\n"); + goto on_error; + } else if (addr & 3) { + fprintf(stderr, "unaligned addr\n"); + goto on_error; + } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; - } - WRPERR = (1 << FLASH_SR_WRPRT_ERR); - PROGERR = (1 << FLASH_SR_PG_ERR); - break; - case STLINK_FLASH_TYPE_F4: - res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; - WRPERR = (1 << FLASH_F4_SR_WRPERR); - PGAERR = (1 << FLASH_F4_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_F7: - res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; - WRPERR = (1 << FLASH_F7_SR_WRP_ERR); - PROGERR = (1 << FLASH_F7_SR_PGP_ERR); - break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); - PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); - PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_L0: - res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); - PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_L4: - res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); - PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); - break; - case STLINK_FLASH_TYPE_H7: - res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; - } - WRPERR = (1 << FLASH_H7_SR_WRPERR); - break; - case STLINK_FLASH_TYPE_WB: - res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); - PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); - PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); - break; - default: - break; + len = length; + + if (len & 3) { + len -= len & 3; } - if (res) { - if (WRPERR && (WRPERR & res) == WRPERR) { - ELOG("Flash memory is write protected\n"); - res &= ~WRPERR; - } else if (PROGERR && (PROGERR & res) == PROGERR) { - ELOG("Flash memory contains a non-erased value\n"); - res &= ~PROGERR; - } else if (PGAERR && (PGAERR & res) == PGAERR) { - ELOG("Invalid flash address\n"); - res &= ~PGAERR; - } + // do the copy by 1kB blocks + for (off = 0; off < len; off += 1024) { + size_t size = 1024; - if (res) { - ELOG("Flash programming error: %#010x\n", res); + if ((off + size) > len) { + size = len - off; } - return (-1); - } - return (0); -} + memcpy(sl->q_buf, data + off, size); -static void stop_wdg_in_debug(stlink_t *sl) { - uint32_t dbgmcu_cr; - uint32_t set; - uint32_t value; + if (size & 3) { + size += 2; + } // round size if needed - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - case STLINK_FLASH_TYPE_G4: - dbgmcu_cr = STM32F0_DBGMCU_CR; - set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | - (1 << STM32F0_DBGMCU_CR_WWDG_STOP); - break; - case STLINK_FLASH_TYPE_F4: - case STLINK_FLASH_TYPE_F7: - case STLINK_FLASH_TYPE_L4: - dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; - set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | - (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); - break; - case STLINK_FLASH_TYPE_L0: - case STLINK_FLASH_TYPE_G0: - dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; - set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | - (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); - break; - case STLINK_FLASH_TYPE_H7: - dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; - set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP); - break; - case STLINK_FLASH_TYPE_WB: - dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1; - set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) | - (1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP); - break; - default: - return; + stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); } - if (!stlink_read_debug32(sl, dbgmcu_cr, &value)) { - stlink_write_debug32(sl, dbgmcu_cr, value | set); + if (length > len) { + memcpy(sl->q_buf, data + len, length - len); + stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(length - len)); } -} -static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { - uint32_t rcc, rcc_dma_mask, value; + error = 0; // success + stlink_fwrite_finalize(sl, addr); - rcc = rcc_dma_mask = value = 0; +on_error: + return (error); +} +//284 +int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { + // write the file in sram at addr - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - rcc = STM32F1_RCC_AHBENR; - rcc_dma_mask = STM32F1_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_F4: - case STLINK_FLASH_TYPE_F7: - rcc = STM32F4_RCC_AHB1ENR; - rcc_dma_mask = STM32F4_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_G0: - rcc = STM32G0_RCC_AHBENR; - rcc_dma_mask = STM32G0_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_G4: - case STLINK_FLASH_TYPE_L4: - rcc = STM32G4_RCC_AHB1ENR; - rcc_dma_mask = STM32G4_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_L0: - rcc = STM32L0_RCC_AHBENR; - rcc_dma_mask = STM32L0_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_H7: - rcc = STM32H7_RCC_AHB1ENR; - rcc_dma_mask = STM32H7_RCC_DMAEN; - break; - case STLINK_FLASH_TYPE_WB: - rcc = STM32WB_RCC_AHB1ENR; - rcc_dma_mask = STM32WB_RCC_DMAEN; - break; - default: - return; - } + int error = -1; + size_t off; + size_t len; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; - if (!stlink_read_debug32(sl, rcc, &value)) { - if (bckpRstr) { - value = (value & (~rcc_dma_mask)) | fl->rcc_dma_bkp; - } else { - fl->rcc_dma_bkp = value & rcc_dma_mask; - value &= ~rcc_dma_mask; - } - stlink_write_debug32(sl, rcc, value); + if (map_file(&mf, path) == -1) { + fprintf(stderr, "map_file() == -1\n"); + return (-1); } -} -static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { - stlink_write_debug32(sl, (bank == BANK_1) ? FLASH_AR : FLASH_AR2, n); -} - -static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n, - unsigned bank) { - uint32_t cr_reg, psize_shift; - uint32_t x = read_flash_cr(sl, bank); + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - psize_shift = FLASH_H7_CR_PSIZE; - } else { - cr_reg = FLASH_F4_CR; - psize_shift = 8; + // check if addr range is inside the SRAM + if (addr < sl->sram_base) { + fprintf(stderr, "addr too low\n"); + goto on_error; + } else if ((addr + mf.len) < addr) { + fprintf(stderr, "addr overruns\n"); + goto on_error; + } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { + fprintf(stderr, "addr too high\n"); + goto on_error; + } else if (addr & 3) { + fprintf(stderr, "unaligned addr\n"); + goto on_error; } - x &= ~(0x03 << psize_shift); - x |= (n << psize_shift); -#if DEBUG_FLASH - fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); -#endif - stlink_write_debug32(sl, cr_reg, x); -} - -static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { - uint32_t cr_reg, snb_mask, snb_shift, ser_shift; - uint32_t x = read_flash_cr(sl, bank); + len = mf.len; - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - snb_mask = FLASH_H7_CR_SNB_MASK; - snb_shift = FLASH_H7_CR_SNB; - ser_shift = FLASH_H7_CR_SER; - } else { - cr_reg = FLASH_F4_CR; - snb_mask = FLASH_F4_CR_SNB_MASK; - snb_shift = FLASH_F4_CR_SNB; - ser_shift = FLASH_F4_CR_SER; + if (len & 3) { + len -= len & 3; } - x &= ~snb_mask; - x |= (n << snb_shift); - x |= (1 << ser_shift); -#if DEBUG_FLASH - fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); -#endif - stlink_write_debug32(sl, cr_reg, x); -} + // do the copy by 1kB blocks + for (off = 0; off < len; off += 1024) { + size_t size = 1024; -static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { - stlink_write_debug32(sl, STM32L4_FLASH_SR, - 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); - uint32_t x = read_flash_cr(sl, BANK_1); - x &= ~STM32L4_FLASH_CR_OPBITS; - x &= ~STM32L4_FLASH_CR_PAGEMASK; - x &= ~(1 << STM32L4_FLASH_CR_MER1); - x &= ~(1 << STM32L4_FLASH_CR_MER2); - x |= (n << STM32L4_FLASH_CR_PNB); - x |= (uint32_t)(1lu << STM32L4_FLASH_CR_PER); -#if DEBUG_FLASH - fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); -#endif - stlink_write_debug32(sl, STM32L4_FLASH_CR, x); -} + if ((off + size) > len) { + size = len - off; + } -// Delegates to the backends... + memcpy(sl->q_buf, mf.base + off, size); -void stlink_close(stlink_t *sl) { - DLOG("*** stlink_close ***\n"); + if (size & 3) { + size += 2; + } // round size if needed - if (!sl) { - return; + stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); } - sl->backend->close(sl); - free(sl); -} - -int stlink_exit_debug_mode(stlink_t *sl) { - DLOG("*** stlink_exit_debug_mode ***\n"); + if (mf.len > len) { + memcpy(sl->q_buf, mf.base + len, mf.len - len); + stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(mf.len - len)); + } - if (sl->flash_type != STLINK_FLASH_TYPE_UNKNOWN && - sl->core_stat != TARGET_RESET) { - // stop debugging if the target has been identified - stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); + // check the file has been written + if (check_file(sl, &mf, addr) == -1) { + fprintf(stderr, "check_file() == -1\n"); + goto on_error; } - return (sl->backend->exit_debug_mode(sl)); -} + error = 0; // success + stlink_fwrite_finalize(sl, addr); -int stlink_enter_swd_mode(stlink_t *sl) { - DLOG("*** stlink_enter_swd_mode ***\n"); - return (sl->backend->enter_swd_mode(sl)); +on_error: + unmap_file(&mf); + return (error); } +// 302 +int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, + stm32_addr_t addr, size_t size) { + // read size bytes from addr to file + ILOG("read from address %#010x size %u\n", addr, (unsigned)size); -// Force the core into the debug mode -> halted state. -int stlink_force_debug(stlink_t *sl) { - DLOG("*** stlink_force_debug_mode ***\n"); - int res = sl->backend->force_debug(sl); - if (res) { - return (res); - } - // Stop the watchdogs in the halted state for suppress target reboot - stop_wdg_in_debug(sl); - return (0); -} - -int stlink_exit_dfu_mode(stlink_t *sl) { - DLOG("*** stlink_exit_dfu_mode ***\n"); - return (sl->backend->exit_dfu_mode(sl)); -} - -int stlink_core_id(stlink_t *sl) { - int ret; - - DLOG("*** stlink_core_id ***\n"); - ret = sl->backend->core_id(sl); - - if (ret == -1) { - ELOG("Failed to read core_id\n"); - return (ret); - } - - if (sl->verbose > 2) { - stlink_print_data(sl); - } - - DLOG("core_id = 0x%08x\n", sl->core_id); - return (ret); -} - -// stlink_chip_id() is called by stlink_load_device_params() -// do not call this procedure directly. -int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { - int ret; - cortex_m3_cpuid_t cpu_id; - - // Read the CPU ID to determine where to read the core id - if (stlink_cpu_id(sl, &cpu_id) || - cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) { - ELOG("Can not connect to target. Please use \'connect under reset\' and " - "try again\n"); - return -1; - } - - /* - * the chip_id register in the reference manual have - * DBGMCU_IDCODE / DBG_IDCODE name - * - */ - - if ((sl->core_id == STM32H7_CORE_ID || sl->core_id == STM32H7_CORE_ID_JTAG) && - cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { - // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - ret = stlink_read_debug32(sl, 0x5c001000, chip_id); - } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0 || - cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0P) { - // STM32F0 (RM0091, pg914; RM0360, pg713) - // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) - // STM32G0 (RM0444, pg1367) - ret = stlink_read_debug32(sl, 0x40015800, chip_id); - } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) { - // STM32L5 (RM0438, pg2157) - ret = stlink_read_debug32(sl, 0xE0044000, chip_id); - } else /* СM3, СM4, CM7 */ { - // default chipid address - - // STM32F1 (RM0008, pg1087; RM0041, pg681) - // STM32F2 (RM0033, pg1326) - // STM32F3 (RM0316, pg1095; RM0313, pg874) - // STM32F7 (RM0385, pg1676; RM0410, pg1912) - // STM32L1 (RM0038, pg861) - // STM32L4 (RM0351, pg1840; RM0394, pg1560) - // STM32G4 (RM0440, pg2086) - // STM32WB (RM0434, pg1406) - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - } - - if (ret || !(*chip_id)) { - *chip_id = 0; - ret = ret?ret:-1; - ELOG("Could not find chip id!\n"); - } else { - *chip_id = (*chip_id) & 0xfff; - - // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for - // F2/F4 - if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) { - *chip_id = 0x413; - } - } - - return (ret); -} - -/** - * Cortex M tech ref manual, CPUID register description - * @param sl stlink context - * @param cpuid pointer to the result object - */ -int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { - uint32_t raw; - - if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { - cpuid->implementer_id = 0; - cpuid->variant = 0; - cpuid->part = 0; - cpuid->revision = 0; - return (-1); - } - - cpuid->implementer_id = (raw >> 24) & 0x7f; - cpuid->variant = (raw >> 20) & 0xf; - cpuid->part = (raw >> 4) & 0xfff; - cpuid->revision = raw & 0xf; - return (0); -} - -/** - * Reads and decodes the flash parameters, as dynamically as possible - * @param sl - * @return 0 for success, or -1 for unsupported core type. - */ -int stlink_load_device_params(stlink_t *sl) { - // This seems to normally work so is unnecessary info for a normal user. - // Demoted to debug. -- REW - DLOG("Loading device parameters....\n"); - const struct stlink_chipid_params *params = NULL; - stlink_core_id(sl); - uint32_t flash_size; - - if (stlink_chip_id(sl, &sl->chip_id)) { - return (-1); - } - - params = stlink_chipid_get_params(sl->chip_id); - - if (params == NULL) { - WLOG("unknown chip id! %#x\n", sl->chip_id); - return (-1); - } - - if (params->flash_type == STLINK_FLASH_TYPE_UNKNOWN) { - WLOG("Invalid flash type, please check device declaration\n"); - sl->flash_size = 0; - return (0); - } - - // These are fixed... - sl->flash_base = STM32_FLASH_BASE; - sl->sram_base = STM32_SRAM_BASE; - stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size); - - if (params->flash_size_reg & 2) { - flash_size = flash_size >> 16; - } - - flash_size = flash_size & 0xffff; - - if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MD || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || - sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS) && - (flash_size == 0)) { - sl->flash_size = 128 * 1024; - } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { - sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_MD_PLUS_HD) { - // 0 is 384k and 1 is 256k - if (flash_size == 0) { - sl->flash_size = 384 * 1024; - } else { - sl->flash_size = 256 * 1024; - } - } else { - sl->flash_size = flash_size * 1024; - } - - sl->flash_type = params->flash_type; - sl->flash_pgsz = params->flash_pagesize; - sl->sram_size = params->sram_size; - sl->sys_base = params->bootrom_base; - sl->sys_size = params->bootrom_size; - sl->option_base = params->option_base; - sl->option_size = params->option_size; - sl->chip_flags = params->flags; - - // medium and low devices have the same chipid. ram size depends on flash - // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD && - sl->flash_size < 64 * 1024) { - sl->sram_size = 0x1000; - } - - if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { - uint32_t flash_optr; - stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); - - if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { - sl->flash_pgsz <<= 1; - } - } - - // H7 devices with small flash has one bank - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && - sl->flash_type == STLINK_FLASH_TYPE_H7) { - if ((sl->flash_size / sl->flash_pgsz) <= 1) - sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; - } - - ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", - params->description, (unsigned)(sl->sram_size / 1024), - (unsigned)(sl->flash_size / 1024), - (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) - : (unsigned)(sl->flash_pgsz / 1024), - (sl->flash_pgsz < 1024) ? "byte" : "KiB"); - - return (0); -} - -int stlink_jtag_reset(stlink_t *sl, int value) { - DLOG("*** stlink_jtag_reset %d ***\n", value); - return (sl->backend->jtag_reset(sl, value)); -} - -int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { - int ret; - unsigned timeout; - uint32_t dhcsr, dfsr; - - DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); - - // halt core and enable debugging (if not already done) - // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_DEBUGEN); - - // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) - if (halt_on_reset) { - stlink_write_debug32( - sl, STLINK_REG_CM3_DEMCR, - STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | - STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); - - // clear VCATCH in the DFSR register - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); - } else { - stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, - STLINK_REG_CM3_DEMCR_TRCENA | - STLINK_REG_CM3_DEMCR_VC_HARDERR | - STLINK_REG_CM3_DEMCR_VC_BUSERR); - } - - // clear S_RESET_ST in the DHCSR register - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - - // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) - ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, - STLINK_REG_AIRCR_VECTKEY | - STLINK_REG_AIRCR_SYSRESETREQ); - if (ret) { - ELOG("Soft reset failed: error write to AIRCR\n"); - return (ret); - } - - // waiting for a reset within 500ms - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - timeout = time_ms() + 500; - while (time_ms() < timeout) { - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - if (halt_on_reset) { - // waiting halt by the SYSRESETREQ exception - // DDI0403E, p. C1-699, Debug Fault Status Register - dfsr = 0; - stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); - if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { - continue; - } - } - timeout = 0; - break; - } - } - - // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); - - if (timeout) { - ELOG("Soft reset failed: timeout\n"); - return (-1); - } - - return (0); -} - -int stlink_reset(stlink_t *sl, enum reset_type type) { - uint32_t dhcsr; - unsigned timeout; - - DLOG("*** stlink_reset ***\n"); - - sl->core_stat = TARGET_RESET; - - if (type == RESET_AUTO) { - // clear S_RESET_ST in DHCSR register for reset state detection - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - } - - if (type == RESET_HARD || type == RESET_AUTO) { - // hardware target reset - if (sl->version.stlink_v > 1) { - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); - // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) - usleep(100); - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); - } - sl->backend->reset(sl); - usleep(10000); - } - - if (type == RESET_AUTO) { - /* Check if the S_RESET_ST bit is set in DHCSR - * This means that a reset has occurred - * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ - - dhcsr = 0; - int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) { - // reset not done yet - // try reset through AIRCR so that NRST does not need to be connected - - WLOG("NRST is not connected\n"); - DLOG("Using reset through SYSRESETREQ\n"); - return stlink_soft_reset(sl, 0); - } - - // waiting for reset the S_RESET_ST bit within 500ms - timeout = time_ms() + 500; - while (time_ms() < timeout) { - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - return (0); - } - } - - return (-1); - } - - if (type == RESET_SOFT || type == RESET_SOFT_AND_HALT) { - return stlink_soft_reset(sl, (type == RESET_SOFT_AND_HALT)); - } - - return (0); -} - -int stlink_run(stlink_t *sl, enum run_type type) { - struct stlink_reg rr; - DLOG("*** stlink_run ***\n"); - - /* Make sure we are in Thumb mode - * Cortex-M chips don't support ARM mode instructions - * xPSR may be incorrect if the vector table has invalid data */ - stlink_read_reg(sl, 16, &rr); - if ((rr.xpsr & (1 << 24)) == 0) { - ILOG("Go to Thumb mode\n"); - stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); - } - - return (sl->backend->run(sl, type)); -} - -int stlink_set_swdclk(stlink_t *sl, int freq_khz) { - DLOG("*** set_swdclk ***\n"); - return (sl->backend->set_swdclk(sl, freq_khz)); -} - -int stlink_status(stlink_t *sl) { - int ret; - - DLOG("*** stlink_status ***\n"); - ret = sl->backend->status(sl); - stlink_core_stat(sl); - return (ret); -} - -/** - * Decode the version bits, originally from -sg, verified with usb - * @param sl stlink context, assumed to contain valid data in the buffer - * @param slv output parsed version object - */ -void _parse_version(stlink_t *sl, stlink_version_t *slv) { - sl->version.flags = 0; - - if (sl->version.stlink_v < 3) { - uint32_t b0 = sl->q_buf[0]; // lsb - uint32_t b1 = sl->q_buf[1]; - uint32_t b2 = sl->q_buf[2]; - uint32_t b3 = sl->q_buf[3]; - uint32_t b4 = sl->q_buf[4]; - uint32_t b5 = sl->q_buf[5]; // msb - - // b0 b1 || b2 b3 | b4 b5 - // 4b | 6b | 6b || 2B | 2B - // stlink_v | jtag_v | swim_v || st_vid | stlink_pid - - slv->stlink_v = (b0 & 0xf0) >> 4; - slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); - slv->swim_v = b1 & 0x3f; - slv->st_vid = (b3 << 8) | b2; - slv->stlink_pid = (b5 << 8) | b4; - - // ST-LINK/V1 from J11 switch to api-v2 (and support SWD) - if (slv->stlink_v == 1) { - slv->jtag_api = - slv->jtag_v > 11 ? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; - } else { - slv->jtag_api = STLINK_JTAG_API_V2; - - // preferred API to get last R/W status from J15 - if (sl->version.jtag_v >= 15) { - sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; - } - - if (sl->version.jtag_v >= 13) { - sl->version.flags |= STLINK_F_HAS_TRACE; - sl->max_trace_freq = STLINK_V2_MAX_TRACE_FREQUENCY; - } - } - } else { - // V3 uses different version format, for reference see OpenOCD source - // (that was written from docs available from ST under NDA): - // https://github.com/ntfreak/openocd/blob/a6dacdff58ef36fcdac00c53ec27f19de1fbce0d/src/jtag/drivers/stlink_usb.c#L965 - slv->stlink_v = sl->q_buf[0]; - slv->swim_v = sl->q_buf[1]; - slv->jtag_v = sl->q_buf[2]; - slv->st_vid = (uint32_t)((sl->q_buf[9] << 8) | sl->q_buf[8]); - slv->stlink_pid = (uint32_t)((sl->q_buf[11] << 8) | sl->q_buf[10]); - slv->jtag_api = STLINK_JTAG_API_V3; - /* preferred API to get last R/W status */ - sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; - sl->version.flags |= STLINK_F_HAS_TRACE; - sl->max_trace_freq = STLINK_V3_MAX_TRACE_FREQUENCY; - } - - return; -} - -int stlink_version(stlink_t *sl) { - DLOG("*** looking up stlink version\n"); - - if (sl->backend->version(sl)) { - return (-1); - } - - _parse_version(sl, &sl->version); - - DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, - STLINK_USB_VID_ST); - DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); - DLOG("stlink version = 0x%x\n", sl->version.stlink_v); - DLOG("jtag version = 0x%x\n", sl->version.jtag_v); - DLOG("swim version = 0x%x\n", sl->version.swim_v); - - if (sl->version.jtag_v == 0) { - WLOG(" warning: stlink doesn't support JTAG/SWD interface\n"); - } - - return (0); -} - -int stlink_target_voltage(stlink_t *sl) { - int voltage = -1; - DLOG("*** reading target voltage\n"); - - if (sl->backend->target_voltage != NULL) { - voltage = sl->backend->target_voltage(sl); - - if (voltage != -1) { - DLOG("target voltage = %imV\n", voltage); - } else { - DLOG("error reading target voltage\n"); - } - } else { - DLOG("reading voltage not supported by backend\n"); - } - - return (voltage); -} - -int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { - int ret; - - ret = sl->backend->read_debug32(sl, addr, data); - if (!ret) - DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); - - return (ret); -} - -int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { - DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); - return sl->backend->write_debug32(sl, addr, data); -} - -int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); - - if (len % 4 != 0) { - ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return (-1); - } - - return (sl->backend->write_mem32(sl, addr, len)); -} - -int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_read_mem32 ***\n"); - - if (len % 4 != 0) { // !!! never ever: fw gives just wrong values - ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return (-1); - } - - return (sl->backend->read_mem32(sl, addr, len)); -} - -int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem8 ***\n"); - return (sl->backend->write_mem8(sl, addr, len)); -} - -int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_regs ***\n"); - return (sl->backend->read_all_regs(sl, regp)); -} - -int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_unsupported_regs ***\n"); - return (sl->backend->read_all_unsupported_regs(sl, regp)); -} - -int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { - DLOG("*** stlink_write_reg\n"); - return (sl->backend->write_reg(sl, reg, idx)); -} - -int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { - DLOG("*** stlink_read_reg\n"); - DLOG(" (%d) ***\n", r_idx); - - if (r_idx > 20 || r_idx < 0) { - fprintf(stderr, "Error: register index must be in [0..20]\n"); - return (-1); - } - - return (sl->backend->read_reg(sl, r_idx, regp)); -} - -int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, - struct stlink_reg *regp) { - int r_convert; - - DLOG("*** stlink_read_unsupported_reg\n"); - DLOG(" (%d) ***\n", r_idx); - - /* Convert to values used by STLINK_REG_DCRSR */ - if (r_idx >= 0x1C && - r_idx <= 0x1F) { // primask, basepri, faultmask, or control - r_convert = 0x14; - } else if (r_idx == 0x40) { // FPSCR - r_convert = 0x21; - } else if (r_idx >= 0x20 && r_idx < 0x40) { - r_convert = 0x40 + (r_idx - 0x20); - } else { - fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return (-1); - } - - return (sl->backend->read_unsupported_reg(sl, r_convert, regp)); -} - -int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, - struct stlink_reg *regp) { - int r_convert; - - DLOG("*** stlink_write_unsupported_reg\n"); - DLOG(" (%d) ***\n", r_idx); - - /* Convert to values used by STLINK_REG_DCRSR */ - if (r_idx >= 0x1C && - r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ - r_convert = r_idx; // the backend function handles this - } else if (r_idx == 0x40) { // FPSCR - r_convert = 0x21; - } else if (r_idx >= 0x20 && r_idx < 0x40) { - r_convert = 0x40 + (r_idx - 0x20); - } else { - fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return (-1); - } - - return (sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); -} - -bool stlink_is_core_halted(stlink_t *sl) { - stlink_status(sl); - return (sl->core_stat == TARGET_HALTED); -} - -int stlink_step(stlink_t *sl) { - DLOG("*** stlink_step ***\n"); - return (sl->backend->step(sl)); -} - -int stlink_current_mode(stlink_t *sl) { - int mode = sl->backend->current_mode(sl); - - switch (mode) { - case STLINK_DEV_DFU_MODE: - DLOG("stlink current mode: dfu\n"); - return (mode); - case STLINK_DEV_DEBUG_MODE: - DLOG("stlink current mode: debug (jtag or swd)\n"); - return (mode); - case STLINK_DEV_MASS_MODE: - DLOG("stlink current mode: mass\n"); - return (mode); - } - - DLOG("stlink mode: unknown!\n"); - return (STLINK_DEV_UNKNOWN_MODE); -} - -int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { - DLOG("*** stlink_trace_enable ***\n"); - return (sl->backend->trace_enable(sl, frequency)); -} - -int stlink_trace_disable(stlink_t *sl) { - DLOG("*** stlink_trace_disable ***\n"); - return (sl->backend->trace_disable(sl)); -} - -int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { - return (sl->backend->trace_read(sl, buf, size)); -} - -// End of delegates.... Common code below here... - -// same as above with entrypoint. - -void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { - stlink_write_reg(sl, addr, 15); /* pc register */ - stlink_run(sl, RUN_NORMAL); - - while (stlink_is_core_halted(sl)) { - usleep(3000000); - } -} - -// this function is called by stlink_status() -// do not call stlink_core_stat() directly, always use stlink_status() -void stlink_core_stat(stlink_t *sl) { - switch (sl->core_stat) { - case TARGET_RUNNING: - DLOG(" core status: running\n"); - return; - case TARGET_HALTED: - DLOG(" core status: halted\n"); - return; - case TARGET_RESET: - DLOG(" core status: reset\n"); - return; - case TARGET_DEBUG_RUNNING: - DLOG(" core status: debug running\n"); - return; - default: - DLOG(" core status: unknown\n"); - } -} - -void stlink_print_data(stlink_t *sl) { - if (sl->q_len <= 0 || sl->verbose < UDEBUG) { - return; - } - - if (sl->verbose > 2) { - DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); - } - - for (int i = 0; i < sl->q_len; i++) { - if (i % 16 == 0) { - /* - if (sl->q_data_dir == Q_DATA_OUT) { - fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); - } else { - fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); - } - */ - } - // DLOG(" %02x", (unsigned int) sl->q_buf[i]); - fprintf(stderr, " %02x", (unsigned int)sl->q_buf[i]); - } - // DLOG("\n\n"); - fprintf(stderr, "\n"); -} - -/* Memory mapped file */ -typedef struct mapped_file { - uint8_t *base; - size_t len; -} mapped_file_t; - -#define MAPPED_FILE_INITIALIZER \ - { NULL, 0 } - -static int map_file(mapped_file_t *mf, const char *path) { - int error = -1; - struct stat st; - - const int fd = open(path, O_RDONLY | O_BINARY); - - if (fd == -1) { - fprintf(stderr, "open(%s) == -1\n", path); - return (-1); - } - - if (fstat(fd, &st) == -1) { - fprintf(stderr, "fstat(%s) == -1\n", path); - goto on_error; - } - - if (sizeof(st.st_size) != sizeof(size_t)) { - // on 32 bit systems, check if there is an overflow - if (st.st_size > (off_t)SSIZE_MAX) { - fprintf(stderr, "mmap() size_t overflow for file %s\n", path); - goto on_error; - } - } - - mf->base = - (uint8_t *)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); - - if (mf->base == MAP_FAILED) { - fprintf(stderr, "mmap() == MAP_FAILED for file %s\n", path); - goto on_error; - } - - mf->len = (size_t)st.st_size; - error = 0; // success - -on_error: - close(fd); - return (error); -} - -static void unmap_file(mapped_file_t *mf) { - munmap((void *)mf->base, mf->len); - mf->base = (unsigned char *)MAP_FAILED; - mf->len = 0; -} - -/* Limit the block size to compare to 0x1800 as anything larger will stall the - * STLINK2 Maybe STLINK V1 needs smaller value! - */ -static int check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { - size_t off; - size_t n_cmp = sl->flash_pgsz; - - if (n_cmp > 0x1800) { - n_cmp = 0x1800; - } - - for (off = 0; off < mf->len; off += n_cmp) { - size_t aligned_size; - - size_t cmp_size = n_cmp; // adjust last page size - - if ((off + n_cmp) > mf->len) { - cmp_size = mf->len - off; - } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { - aligned_size = (cmp_size + 4) & ~(4 - 1); - } - - stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - - if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { - return (-1); - } - } - - return (0); -} - -static void md5_calculate(mapped_file_t *mf) { - // calculate md5 checksum of given binary file - Md5Context md5Context; - MD5_HASH md5Hash; - Md5Initialise(&md5Context); - Md5Update(&md5Context, mf->base, (uint32_t)mf->len); - Md5Finalise(&md5Context, &md5Hash); - printf("md5 checksum: "); - - for (int i = 0; i < (int)sizeof(md5Hash); i++) { - printf("%x", md5Hash.bytes[i]); - } - - printf(", "); -} - -static void stlink_checksum(mapped_file_t *mp) { - /* checksum that backward compatible with official ST tools */ - uint32_t sum = 0; - uint8_t *mp_byte = (uint8_t *)mp->base; - - for (size_t i = 0; i < mp->len; ++i) { - sum += mp_byte[i]; - } - - printf("stlink checksum: 0x%08x\n", sum); -} - -static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { - unsigned int val; - // set PC to the reset routine - stlink_read_debug32(sl, addr + 4, &val); - stlink_write_reg(sl, val, 15); - stlink_run(sl, RUN_NORMAL); -} - -int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, - stm32_addr_t addr) { - // write the file in sram at addr - - int error = -1; - size_t off; - size_t len; - - // check addr range is inside the sram - if (addr < sl->sram_base) { - fprintf(stderr, "addr too low\n"); - goto on_error; - } else if ((addr + length) < addr) { - fprintf(stderr, "addr overruns\n"); - goto on_error; - } else if ((addr + length) > (sl->sram_base + sl->sram_size)) { - fprintf(stderr, "addr too high\n"); - goto on_error; - } else if (addr & 3) { - fprintf(stderr, "unaligned addr\n"); - goto on_error; - } - - len = length; - - if (len & 3) { - len -= len & 3; - } - - // do the copy by 1kB blocks - for (off = 0; off < len; off += 1024) { - size_t size = 1024; - - if ((off + size) > len) { - size = len - off; - } - - memcpy(sl->q_buf, data + off, size); - - if (size & 3) { - size += 2; - } // round size if needed - - stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); - } - - if (length > len) { - memcpy(sl->q_buf, data + len, length - len); - stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(length - len)); - } - - error = 0; // success - stlink_fwrite_finalize(sl, addr); - -on_error: - return (error); -} - -int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { - // write the file in sram at addr - - int error = -1; - size_t off; - size_t len; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - fprintf(stderr, "map_file() == -1\n"); - return (-1); - } - - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); - - // check if addr range is inside the SRAM - if (addr < sl->sram_base) { - fprintf(stderr, "addr too low\n"); - goto on_error; - } else if ((addr + mf.len) < addr) { - fprintf(stderr, "addr overruns\n"); - goto on_error; - } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { - fprintf(stderr, "addr too high\n"); - goto on_error; - } else if (addr & 3) { - fprintf(stderr, "unaligned addr\n"); - goto on_error; - } - - len = mf.len; - - if (len & 3) { - len -= len & 3; - } - - // do the copy by 1kB blocks - for (off = 0; off < len; off += 1024) { - size_t size = 1024; - - if ((off + size) > len) { - size = len - off; - } - - memcpy(sl->q_buf, mf.base + off, size); - - if (size & 3) { - size += 2; - } // round size if needed - - stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); - } - - if (mf.len > len) { - memcpy(sl->q_buf, mf.base + len, mf.len - len); - stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(mf.len - len)); - } - - // check the file has been written - if (check_file(sl, &mf, addr) == -1) { - fprintf(stderr, "check_file() == -1\n"); - goto on_error; - } - - error = 0; // success - stlink_fwrite_finalize(sl, addr); - -on_error: - unmap_file(&mf); - return (error); -} - -typedef bool (*save_block_fn)(void *arg, uint8_t *block, ssize_t len); - -static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, - save_block_fn fn, void *fn_arg) { - - int error = -1; - - if (size < 1) { - size = sl->flash_size; - } - - if (size > sl->flash_size) { - size = sl->flash_size; - } - - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - - for (size_t off = 0; off < size; off += cmp_size) { - size_t aligned_size; - - // adjust last page size - if ((off + cmp_size) > size) { - cmp_size = size - off; - } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { - aligned_size = (cmp_size + 4) & ~(4 - 1); - } - - stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - - if (!fn(fn_arg, sl->q_buf, aligned_size)) { - goto on_error; - } - } - - error = 0; // success - -on_error: - return (error); -} - -struct stlink_fread_worker_arg { - int fd; -}; - -static bool stlink_fread_worker(void *arg, uint8_t *block, ssize_t len) { - struct stlink_fread_worker_arg *the_arg = - (struct stlink_fread_worker_arg *)arg; - - if (write(the_arg->fd, block, len) != len) { - fprintf(stderr, "write() != aligned_size\n"); - return (false); - } else { - return (true); - } -} - -struct stlink_fread_ihex_worker_arg { - FILE *file; - uint32_t addr; - uint32_t lba; - uint8_t buf[16]; - uint8_t buf_pos; -}; - -static bool -stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { - uint32_t addr = the_arg->addr; - uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + - (uint8_t)((addr & 0x00FF0000) >> 16); - - if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", - (addr & 0xFFFF0000) >> 16, (uint8_t)(0x100 - sum))) { - return (false); - } - - the_arg->lba = (addr & 0xFFFF0000); - return (true); -} - -static bool -stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { - uint8_t count = the_arg->buf_pos; - - if (count == 0) { - return (true); - } - - uint32_t addr = the_arg->addr; - - if (the_arg->lba != (addr & 0xFFFF0000)) { // segment changed - if (!stlink_fread_ihex_newsegment(the_arg)) { - return (false); - } - } - - uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + - (uint8_t)(addr & 0x000000FF); - - if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) { - return (false); - } - - for (uint8_t i = 0; i < count; ++i) { - uint8_t b = the_arg->buf[i]; - sum += b; - - if (2 != fprintf(the_arg->file, "%02X", b)) { - return (false); - } - } - - if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) { - return (false); - } - - the_arg->addr += count; - the_arg->buf_pos = 0; - - return (true); -} - -static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *the_arg, - int fd, stm32_addr_t addr) { - the_arg->file = fdopen(fd, "w"); - the_arg->addr = addr; - the_arg->lba = 0; - the_arg->buf_pos = 0; - - return (the_arg->file != NULL); -} - -static bool stlink_fread_ihex_worker(void *arg, uint8_t *block, ssize_t len) { - struct stlink_fread_ihex_worker_arg *the_arg = - (struct stlink_fread_ihex_worker_arg *)arg; - - for (ssize_t i = 0; i < len; ++i) { - if (the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full - if (!stlink_fread_ihex_writeline(the_arg)) { - return (false); - } - } - - the_arg->buf[the_arg->buf_pos++] = block[i]; - } - - return (true); -} - -static bool -stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { - if (!stlink_fread_ihex_writeline(the_arg)) { - return (false); - } - - // FIXME: do we need the Start Linear Address? - - if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) { // EoF - return (false); - } - - return (0 == fclose(the_arg->file)); -} - -int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, - stm32_addr_t addr, size_t size) { - // read size bytes from addr to file - ILOG("read from address %#010x size %u\n", addr, (unsigned)size); - - int error; - int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); - - if (fd == -1) { - fprintf(stderr, "open(%s) == -1\n", path); - return (-1); - } - - if (is_ihex) { - struct stlink_fread_ihex_worker_arg arg; - - if (stlink_fread_ihex_init(&arg, fd, addr)) { - error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); - - if (!stlink_fread_ihex_finalize(&arg)) { - error = -1; - } - } else { - error = -1; - } - } else { - struct stlink_fread_worker_arg arg = {fd}; - error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); - } - - close(fd); - return (error); -} - -int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, - size_t size) { - // write the buffer right after the loader - int ret = 0; - size_t chunk = size & ~0x3; - size_t rem = size & 0x3; - - if (chunk) { - memcpy(sl->q_buf, buf, chunk); - ret = stlink_write_mem32(sl, fl->buf_addr, (uint16_t)chunk); - } - - if (rem && !ret) { - memcpy(sl->q_buf, buf + chunk, rem); - ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, (uint16_t)rem); - } - - return (ret); -} - -uint32_t calculate_F4_sectornum(uint32_t flashaddr) { - uint32_t offset = 0; - flashaddr &= ~STM32_FLASH_BASE; // page now holding the actual flash address - - if (flashaddr >= 0x100000) { - offset = 12; - flashaddr -= 0x100000; - } - - if (flashaddr < 0x4000) { - return (offset + 0); - } else if (flashaddr < 0x8000) { - return (offset + 1); - } else if (flashaddr < 0xc000) { - return (offset + 2); - } else if (flashaddr < 0x10000) { - return (offset + 3); - } else if (flashaddr < 0x20000) { - return (offset + 4); - } else { - return (offset + (flashaddr / 0x20000) + 4); - } -} - -uint32_t calculate_F7_sectornum(uint32_t flashaddr) { - flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address - - if (flashaddr < 0x20000) { - return (flashaddr / 0x8000); - } else if (flashaddr < 0x40000) { - return (4); - } else { - return ((flashaddr / 0x40000) + 4); - } -} - -uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, - unsigned bank) { - flashaddr &= - ~((bank == BANK_1) - ? STM32_FLASH_BASE - : STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address - return (flashaddr / sl->flash_pgsz); -} - -// returns BKER:PNB for the given page address -uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { - uint32_t bker = 0; - uint32_t flashopt; - stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); - flashaddr -= STM32_FLASH_BASE; - - if (sl->chip_id == STLINK_CHIPID_STM32_L4 || - sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x || - sl->chip_id == STLINK_CHIPID_STM32_L4Rx) { - // this chip use dual banked flash - if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { - uint32_t banksize = (uint32_t)sl->flash_size / 2; - - if (flashaddr >= banksize) { - flashaddr -= banksize; - bker = 0x100; - } - } - } - - // For 1MB chips without the dual-bank option set, the page address will - // overflow into the BKER bit, which gives us the correct bank:page value. - return (bker | flashaddr / (uint32_t)sl->flash_pgsz); -} - -uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { - if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || - (sl->chip_id == STLINK_CHIPID_STM32_F4) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || - (sl->chip_id == STLINK_CHIPID_STM32_F411xx) || - (sl->chip_id == STLINK_CHIPID_STM32_F446) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || - (sl->chip_id == STLINK_CHIPID_STM32_F72xxx) || - (sl->chip_id == STLINK_CHIPID_STM32_F412)) { - uint32_t sector = calculate_F4_sectornum(flashaddr); - - if (sector >= 12) { - sector -= 12; - } - - if (sector < 4) { - sl->flash_pgsz = 0x4000; - } else if (sector < 5) { - sl->flash_pgsz = 0x10000; - } else { - sl->flash_pgsz = 0x20000; - } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { - uint32_t sector = calculate_F7_sectornum(flashaddr); - - if (sector < 4) { - sl->flash_pgsz = 0x8000; - } else if (sector < 5) { - sl->flash_pgsz = 0x20000; - } else { - sl->flash_pgsz = 0x40000; - } - } - - return ((uint32_t)sl->flash_pgsz); -} - -/** - * Erase a page of flash, assumes sl is fully populated with things like - * chip/core ids - * @param sl stlink context - * @param flashaddr an address in the flash page to erase - * @return 0 on success -ve on failure - */ -int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - // wait for ongoing op to finish - wait_flash_busy(sl); - // clear flash IO errors - clear_flash_error(sl); - - if (sl->flash_type == STLINK_FLASH_TYPE_F4 || - sl->flash_type == STLINK_FLASH_TYPE_F7 || - sl->flash_type == STLINK_FLASH_TYPE_L4) { - // unlock if locked - unlock_flash_if(sl); - - // select the page to erase - if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || - (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) || - (sl->chip_id == STLINK_CHIPID_STM32_L4Rx)) { - // calculate the actual bank+page from the address - uint32_t page = calculate_L4_page(sl, flashaddr); - - fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, - stlink_calculate_pagesize(sl, flashaddr)); - - write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { - // calculate the actual page from the address - uint32_t sector = calculate_F7_sectornum(flashaddr); - - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, - stlink_calculate_pagesize(sl, flashaddr)); - write_flash_cr_snb(sl, sector, BANK_1); - } else { - // calculate the actual page from the address - uint32_t sector = calculate_F4_sectornum(flashaddr); - - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, - stlink_calculate_pagesize(sl, flashaddr)); - - // the SNB values for flash sectors in the second bank do not directly - // follow the values for the first bank on 2mb devices... - if (sector >= 12) { - sector += 4; - } - - write_flash_cr_snb(sl, sector, BANK_1); - } - - set_flash_cr_strt(sl, BANK_1); // start erase operation - wait_flash_busy(sl); // wait for completion - lock_flash(sl); // TODO: fails to program if this is in -#if DEBUG_FLASH - fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); -#endif - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // check if the locks are set - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if ((val & (1 << 0)) || (val & (1 << 1))) { - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY2); - - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if (val & (1 << 0)) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return (-1); - } - - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY2); - - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if (val & (1 << 1)) { - WLOG("pecr.prglock not clear (%#x)\n", val); - return (-1); - } - } - - // set pecr.{erase,prog} - val |= (1 << 9) | (1 << 3); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - // write 0 to the first word of the page to be erased - stlink_write_debug32(sl, flashaddr, 0); - - /* MP: It is better to wait for clearing the busy bit after issuing page - * erase command, even though PM0062 recommends to wait before it. - * Test shows that a few iterations is performed in the following loop - * before busy bit is cleared. - */ - wait_flash_busy(sl); - - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - uint32_t val; - unlock_flash_if(sl); - set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit - - // set the page to erase - if (sl->flash_type == STLINK_FLASH_TYPE_WB) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - - // sec 3.10.5 - PNB[7:0] is offset by 3. - val &= ~(0xFF << 3); // Clear previously set page number (if any) - val |= ((flash_page & 0xFF) << 3); - - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. - val &= ~(0x3F << 3); - val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. - val &= ~(0x7F << 3); - val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } - - set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit - wait_flash_busy(sl); // wait for the 'busy' bit to clear - clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit - lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; - unlock_flash_if(sl); - clear_flash_cr_pg(sl, bank); // clear the pg bit - set_flash_cr_per(sl, bank); // set the page erase bit - write_flash_ar(sl, flashaddr, bank); // select the page to erase - set_flash_cr_strt(sl, - bank); // start erase operation, reset by hw with busy bit - wait_flash_busy(sl); - clear_flash_cr_per(sl, bank); // clear the page erase bit - lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; - unlock_flash_if(sl); // unlock if locked - uint32_t sector = calculate_H7_sectornum( - sl, flashaddr, bank); // calculate the actual page from the address - write_flash_cr_snb(sl, sector, bank); // select the page to erase - set_flash_cr_strt(sl, bank); // start erase operation - wait_flash_busy(sl); // wait for completion - lock_flash(sl); - } else { - WLOG("unknown coreid %x, page erase failed\n", sl->core_id); - return (-1); - } - - return check_flash_error(sl); -} - -// Check if an address and size are within the flash -int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { - if (addr < sl->flash_base || addr >= (sl->flash_base + sl->flash_size)) { - ELOG("Invalid address, it should be within 0x%08x - 0x%08lx\n", sl->flash_base, (sl->flash_base + sl->flash_size -1)); - return (-1); - } - if ((addr + size) > (sl->flash_base + sl->flash_size)) { - ELOG("The size exceeds the size of the flash (0x%08lx bytes available)\n", (sl->flash_base + sl->flash_size - addr)); - return (-1); - } - return 0; -} - -// Check if an address is aligned with the beginning of a page -int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { - stm32_addr_t page = sl->flash_base; - - while (page < addr) { - page += stlink_calculate_pagesize(sl, page); - } - - if (page != addr) { - return -1; - } - - return 0; -} - -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { - // Check the address and size validity - if (stlink_check_address_range_validity(sl, base_addr, size) < 0) { - return -1; - } - - // Make sure the requested address is aligned with the beginning of a page - if (stlink_check_address_alignment(sl, base_addr) < 0) { - ELOG("The address to erase is not aligned with the beginning of a page\n"); - return -1; - } - - stm32_addr_t addr = base_addr; - do { - size_t page_size = stlink_calculate_pagesize(sl, addr); - - // Check if size is aligned with a page, unless we want to completely erase the last page - if ((addr + page_size) > (base_addr + size) && !align_size) { - ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); - return -1; - } - - if (stlink_erase_flash_page(sl, addr)) { - WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); - return (-1); - } - - fprintf(stdout, "-> Flash page at %#x erased (size: %#lx)\n", addr, page_size); - fflush(stdout); - - // check the next page is within the range to erase - addr += page_size; - } while (addr < (base_addr + size)); - - fprintf(stdout, "\n"); - return 0; -} - -int stlink_erase_flash_mass(stlink_t *sl) { - int err = 0; - - // TODO: User MER bit to mass-erase WB series. - if (sl->flash_type == STLINK_FLASH_TYPE_L0 || - sl->flash_type == STLINK_FLASH_TYPE_WB) { - - err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); - - } else { - wait_flash_busy(sl); - clear_flash_error(sl); - unlock_flash_if(sl); - - if (sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { - // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); - } - } - - set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit - set_flash_cr_strt( - sl, BANK_1); // start erase operation, reset by hw with busy bit - - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 - set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 - } - - wait_flash_busy_progress(sl); - lock_flash(sl); - - // reset the mass erase bit - set_flash_cr_mer(sl, 0, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - set_flash_cr_mer(sl, 0, BANK_2); - } - - err = check_flash_error(sl); - } - - return (err); -} - -int stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { - // check the contents of path are at addr - - int res; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - return (-1); - } - - res = check_file(sl, &mf, addr); - unmap_file(&mf); - return (res); -} - -/** - * Verify addr..addr+len is binary identical to base...base+len - * @param sl stlink context - * @param address stm device address - * @param data host side buffer to check against - * @param length how much - * @return 0 for success, -ve for failure - */ -int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, - unsigned length) { - size_t off; - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - ILOG("Starting verification of write complete\n"); - - for (off = 0; off < length; off += cmp_size) { - size_t aligned_size; - - // adjust last page size - if ((off + cmp_size) > length) { - cmp_size = length - off; - } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { - aligned_size = (cmp_size + 4) & ~(4 - 1); - } - - stlink_read_mem32(sl, address + (uint32_t)off, (uint16_t)aligned_size); - - if (memcmp(sl->q_buf, data + off, cmp_size)) { - ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); - return (-1); - } - } - - ILOG("Flash written and verified! jolly good!\n"); - return (0); -} - -int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len, uint32_t pagesize) { - unsigned int count, off; - unsigned int num_half_pages = len / pagesize; - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - flash_loader_t fl; - bool use_loader = true; - int ret = 0; - - // enable half page write - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - val |= (1 << FLASH_L1_PROG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - wait_flash_busy(sl); - - for (count = 0; count < num_half_pages; count++) { - if (use_loader) { - ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, - base + count * pagesize, pagesize); - if (ret && count == 0) { - /* It seems that stm32lx devices have a problem when it is blank */ - WLOG("Failed to use flash loader, fallback to soft write\n"); - use_loader = false; - } - } - if (!use_loader) { - ret = 0; - for (off = 0; off < pagesize && !ret; off += 64) { - size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; - memcpy(sl->q_buf, base + count * pagesize + off, chunk); - ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); - } - } - - if (ret) { - WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", - addr + count * pagesize); - break; - } - - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading - fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); - fflush(stdout); - } - - // wait for sr.busy to be cleared - wait_flash_busy(sl); - } - - // disable half page write - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return (ret); -} - -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - // disable DMA - set_dma_state(sl, fl, 0); - - // wait for ongoing op to finish - wait_flash_busy(sl); - // Clear errors - clear_flash_error(sl); - - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { - ILOG("Starting Flash write for F2/F4/F7/L4\n"); - - // Flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return (-1); - } - - unlock_flash_if(sl); // first unlock the cr - - int voltage; - if (sl->version.stlink_v == 1) { - WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); - voltage = 3200; - } else { - voltage = stlink_target_voltage(sl); - } - - if (voltage == -1) { - ELOG("Failed to read Target voltage\n"); - return (-1); - } - - if (sl->flash_type == STLINK_FLASH_TYPE_L4) { - // L4 does not have a byte-write mode - if (voltage < 1710) { - ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); - return (-1); - } - } else { - if (voltage > 2700) { - ILOG("enabling 32-bit flash writes\n"); - write_flash_cr_psiz(sl, 2, BANK_1); - } else { - ILOG("Target voltage (%d mV) too low for 32-bit flash, " - "using 8-bit flash writes\n", - voltage); - write_flash_cr_psiz(sl, 0, BANK_1); - } - } - - // set programming mode - set_flash_cr_pg(sl, BANK_1); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - ILOG("Starting Flash write for WB/G0/G4\n"); - - unlock_flash_if(sl); // unlock flash if necessary - set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - ILOG("Starting Flash write for L0\n"); - - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY2); - - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 0)) { - ELOG("pecr.pelock not clear\n"); - return (-1); - } - - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY2); - - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 1)) { - ELOG("pecr.prglock not clear\n"); - return (-1); - } - - /* Flash loader initialisation */ - if (stlink_flash_loader_init(sl, fl) == -1) { - // L0/L1 have fallback to soft write - WLOG("stlink_flash_loader_init() == -1\n"); - } - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); - - // flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return (-1); - } - - // unlock flash - unlock_flash_if(sl); - - // set programming mode - set_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - set_flash_cr_pg(sl, BANK_2); - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - ILOG("Starting Flash write for H7\n"); - - unlock_flash_if(sl); // unlock the cr - set_flash_cr_pg(sl, BANK_1); // set programming mode - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - set_flash_cr_pg(sl, BANK_2); - } - if (sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { - // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); - } - } - } else { - ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); - return (-1); - } - - return (0); -} - -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, - stm32_addr_t addr, uint8_t *base, uint32_t len) { - size_t off; - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { - size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; - for (off = 0; off < len;) { - size_t size = len - off > buf_size ? buf_size : len - off; - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); - check_flash_error(sl); - return (-1); - } - - off += size; - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - for (off = 0; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } - - write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - fprintf(stdout, "\n"); - - // flash writes happen as 2 words at a time - if ((off / sizeof(uint32_t)) % 2 != 0) { - stlink_write_debug32(sl, addr + (uint32_t)off, - 0); // write a single word of zeros - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? - L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; - - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - - off = 0; - - if (len > pagesize) { - if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { - return (-1); - } else { - off = (size_t)(len / pagesize) * pagesize; - } - } - - // write remaining word in program memory - for (; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } - - write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); - - // wait for sr.busy to be cleared - do { - stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - } while ((val & (1 << 0)) != 0); - - // TODO: check redo write operation - } - fprintf(stdout, "\n"); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { - int write_block_count = 0; - for (off = 0; off < len; off += sl->flash_pgsz) { - // adjust last write size - size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; - - // unlock and set programming mode - unlock_flash_if(sl); - - DLOG("Finished unlocking flash, running loader!\n"); - - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); - check_flash_error(sl); - return (-1); - } - - lock_flash(sl); - - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading - fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, - (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { - for (off = 0; off < len;) { - // Program STM32H7x with 64-byte Flash words - size_t chunk = (len - off > 64) ? 64 : len - off; - memcpy(sl->q_buf, base + off, chunk); - stlink_write_mem32(sl, addr + (uint32_t)off, 64); - wait_flash_busy(sl); - - off += chunk; - - if (sl->verbose >= 1) { - // show progress - fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, - (unsigned int)len); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } - } else { - return (-1); - } - - return check_flash_error(sl); -} - -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { - uint32_t dhcsr; - - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4) || - (sl->flash_type == STLINK_FLASH_TYPE_WB) || - (sl->flash_type == STLINK_FLASH_TYPE_G0) || - (sl->flash_type == STLINK_FLASH_TYPE_G4) || - (sl->flash_type == STLINK_FLASH_TYPE_H7)) { - - clear_flash_cr_pg(sl, BANK_1); - if ((sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { - clear_flash_cr_pg(sl, BANK_2); - } - lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } - - // enable interrupt - if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); - } - - // restore DMA state - set_dma_state(sl, fl, 1); - - return (0); -} - -int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len, uint8_t eraseonly) { - int ret; - flash_loader_t fl; - ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, - len, addr, addr); - // check addr range is inside the flash - stlink_calculate_pagesize(sl, addr); - - // Check the address and size validity - if (stlink_check_address_range_validity(sl, addr, len) < 0) { - return (-1); - } else if (len & 1) { - WLOG("unaligned len 0x%x -- padding with zero\n", len); - len += 1; - } else if (stlink_check_address_alignment(sl, addr) < 0) { - ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " - "check page start address and compare with flash module organisation " - "in related ST reference manual of your device.\n", - (unsigned)(sl->flash_pgsz)); - return (-1); - } - - // make sure we've loaded the context with the chip details - stlink_core_id(sl); - - // Erase this section of the flash - if (stlink_erase_flash_section(sl, addr, len, true) < 0) { - ELOG("Failed to erase the flash prior to writing\n"); - return (-1); - } - - if (eraseonly) { - return (0); - } - - ret = stlink_flashloader_start(sl, &fl); - if (ret) - return ret; - ret = stlink_flashloader_write(sl, &fl, addr, base, len); - if (ret) - return ret; - ret = stlink_flashloader_stop(sl, &fl); - if (ret) - return ret; - - return (stlink_verify_write_flash(sl, addr, base, len)); -} - -// TODO: length not checked -static uint8_t stlink_parse_hex(const char *hex) { - uint8_t d[2]; - - for (int i = 0; i < 2; ++i) { - char c = *(hex + i); - - if (c >= '0' && c <= '9') { - d[i] = c - '0'; - } else if (c >= 'A' && c <= 'F') { - d[i] = c - 'A' + 10; - } else if (c >= 'a' && c <= 'f') { - d[i] = c - 'a' + 10; - } else { - return (0); // error - } - } - - return ((d[0] << 4) | (d[1])); -} - -int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, - size_t *size, uint32_t *begin) { - int res = 0; - *begin = UINT32_MAX; - uint8_t *data = NULL; - uint32_t end = 0; - bool eof_found = false; - - for (int scan = 0; (res == 0) && (scan < 2); ++scan) { - // parse file two times - first to find memory range, second - to fill it - if (scan == 1) { - if (!eof_found) { - ELOG("No EoF recond\n"); - res = -1; - break; - } - - if (*begin >= end) { - ELOG("No data found in file\n"); - res = -1; - break; - } - - *size = (end - *begin) + 1; - data = calloc(*size, 1); // use calloc to get NULL if out of memory - - if (!data) { - ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); - res = -1; - break; - } - - memset(data, erased_pattern, *size); - } - - FILE *file = fopen(path, "r"); - - if (!file) { - ELOG("Cannot open file\n"); - res = -1; - break; - } - - uint32_t lba = 0; - char line[1 + 5 * 2 + 255 * 2 + 2]; - - while (fgets(line, sizeof(line), file)) { - if (line[0] == '\n' || line[0] == '\r') { - continue; - } // skip empty lines - - if (line[0] != ':') { // no marker - wrong file format - ELOG("Wrong file format - no marker\n"); - res = -1; - break; - } - - size_t l = strlen(line); - - while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { - --l; - } // trim EoL - - if ((l < 11) || - (l == - (sizeof(line) - 1))) { // line too short or long - wrong file format - ELOG("Wrong file format - wrong line length\n"); - res = -1; - break; - } - - uint8_t chksum = 0; // check sum - - for (size_t i = 1; i < l; i += 2) { - chksum += stlink_parse_hex(line + i); - } - - if (chksum != 0) { - ELOG("Wrong file format - checksum mismatch\n"); - res = -1; - break; - } - - uint8_t reclen = stlink_parse_hex(line + 1); - - if (((uint32_t)reclen + 5) * 2 + 1 != l) { - ELOG("Wrong file format - record length mismatch\n"); - res = -1; - break; - } - - uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | - ((uint16_t)stlink_parse_hex(line + 5)); - uint8_t rectype = stlink_parse_hex(line + 7); - - switch (rectype) { - case 0: /* Data */ - if (scan == 0) { - uint32_t b = lba + offset; - uint32_t e = b + reclen - 1; - - if (b < *begin) { - *begin = b; - } - - if (e > end) { - end = e; - } - } else { - for (uint8_t i = 0; i < reclen; ++i) { - uint8_t b = stlink_parse_hex(line + 9 + i * 2); - uint32_t addr = lba + offset + i; - - if (addr >= *begin && addr <= end) { - data[addr - *begin] = b; - } - } - } - break; - case 1: /* EoF */ - eof_found = true; - break; - case 2: /* Extended Segment Address, unexpected */ - res = -1; - break; - case 3: /* Start Segment Address, unexpected */ - res = -1; - break; - case 4: /* Extended Linear Address */ - if (reclen == 2) { - lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | - ((uint32_t)stlink_parse_hex(line + 11) << 16); - } else { - ELOG("Wrong file format - wrong LBA length\n"); - res = -1; - } - break; - case 5: /* Start Linear Address - expected, but ignore */ - break; - default: - ELOG("Wrong file format - unexpected record type %d\n", rectype); - res = -1; - } - - if (res != 0) { - break; - } - } - - fclose(file); - } - - if (res == 0) { - *mem = data; - } else { - free(data); - } - - return (res); -} - -uint8_t stlink_get_erased_pattern(stlink_t *sl) { - if (sl->flash_type == STLINK_FLASH_TYPE_L0) { - return (0x00); - } else { - return (0xff); - } -} - -int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, - stm32_addr_t addr) { - /* Write the block in flash at addr */ - int err; - unsigned int num_empty, idx; - uint8_t erased_pattern = stlink_get_erased_pattern(sl); - - /* - * This optimisation may cause unexpected garbage data remaining. - * Therfore it is turned off by default. - */ - if (sl->opt) { - idx = (unsigned int)length; - - for (num_empty = 0; num_empty != length; ++num_empty) - if (data[--idx] != erased_pattern) { - break; - } - - num_empty -= (num_empty & 3); // Round down to words - - if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, - erased_pattern); - } - } else { - num_empty = 0; - } - - /* - * TODO: investigate a kind of weird behaviour here: - * If the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed. - */ - err = stlink_write_flash(sl, addr, data, - (num_empty == length) ? (uint32_t)length - : (uint32_t)length - num_empty, - num_empty == length); - stlink_fwrite_finalize(sl, addr); - return (err); -} - -/** - * Write the given binary file into flash at address "addr" - * @param sl - * @param path readable file path, should be binary image - * @param addr where to start writing - * @return 0 on success, -ve on failure. - */ -int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { - /* Write the file in flash at addr */ - int err; - unsigned int num_empty, idx; - uint8_t erased_pattern = stlink_get_erased_pattern(sl); - mapped_file_t mf = MAPPED_FILE_INITIALIZER; + int error; + int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); + if (fd == -1) { + fprintf(stderr, "open(%s) == -1\n", path); return (-1); } - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); + if (is_ihex) { + struct stlink_fread_ihex_worker_arg arg; - if (sl->opt) { - idx = (unsigned int)mf.len; + if (stlink_fread_ihex_init(&arg, fd, addr)) { + error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); - for (num_empty = 0; num_empty != mf.len; ++num_empty) { - if (mf.base[--idx] != erased_pattern) { - break; + if (!stlink_fread_ihex_finalize(&arg)) { + error = -1; } - } - - num_empty -= (num_empty & 3); // round down to words - - if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, - erased_pattern); + } else { + error = -1; } } else { - num_empty = 0; + struct stlink_fread_worker_arg arg = {fd}; + error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); } - /* - * TODO: investigate a kind of weird behaviour here: - * If the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed. - */ - err = stlink_write_flash(sl, addr, mf.base, - (num_empty == mf.len) ? (uint32_t)mf.len - : (uint32_t)mf.len - num_empty, - num_empty == mf.len); - stlink_fwrite_finalize(sl, addr); - unmap_file(&mf); - return (err); + close(fd); + return (error); } - -/** - * Write option bytes - * @param sl - * @param base option bytes to write - * @param addr of the memory mapped option bytes - * @param len of options bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_f0( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { +// 300 +int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, + size_t size) { + // write the buffer right after the loader int ret = 0; + size_t chunk = size & ~0x3; + size_t rem = size & 0x3; - if (len < 12 || addr != STM32_F0_OPTION_BYTES_BASE) { - WLOG("Only full write of option bytes area is supported\n"); - return -1; - } - - clear_flash_error(sl); - - WLOG("Erasing option bytes\n"); - - /* erase option bytes */ - stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_OPTWRE)); - ret = stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_STRT) | (1 << FLASH_CR_OPTWRE)); - if (ret) { - return ret; - } - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - if (ret) { - return ret; - } - - WLOG("Writing option bytes to %#10x\n", addr); - - /* Set the Option PG bit to enable programming */ - stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTPG) | (1 << FLASH_CR_OPTWRE)); - - /* Use flash loader for write OP - * because flash memory writable by half word */ - flash_loader_t fl; - ret = stlink_flash_loader_init(sl, &fl); - if (ret) { - return ret; - } - ret = stlink_flash_loader_run(sl, &fl, addr, base, len); - if (ret) { - return ret; + if (chunk) { + memcpy(sl->q_buf, buf, chunk); + ret = stlink_write_mem32(sl, fl->buf_addr, (uint16_t)chunk); } - /* Reload option bytes */ - stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OBL_LAUNCH)); - - return check_flash_error(sl); -} - -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - /* Write options bytes */ - uint32_t val; - int ret = 0; - (void)len; - uint32_t data; - - clear_flash_error(sl); - - write_uint32((unsigned char *)&data, *(uint32_t *)(base)); - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); - - // Set Options Start bit - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - - // Reload options - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - - return (ret); -} - -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t flash_base = get_stm32l0_flash_base(sl); - uint32_t val; - uint32_t data; - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - while (len != 0) { - write_uint32((unsigned char *)&data, - *(uint32_t *)(base)); // write options bytes - - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, addr, data); - wait_flash_busy(sl); - - if ((ret = check_flash_error(sl))) { - break; - } - - len -= 4; - addr += 4; - base += 4; + if (rem && !ret) { + memcpy(sl->q_buf, buf + chunk, rem); + ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, (uint16_t)rem); } - // Reload options - stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); - val |= (1 << STM32L0_FLASH_OBL_LAUNCH); - stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); - - return (ret); -} - -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - - uint32_t val; - int ret = 0; - (void)addr; - (void)len; - - // Clear errors - clear_flash_error(sl); - - // write options bytes - uint32_t data; - write_uint32((unsigned char *)&data, *(uint32_t *)(base)); - WLOG("Writing option bytes 0x%04x\n", data); - stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); - - // set options start bit - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - - wait_flash_busy(sl); - ret = check_flash_error(sl); - - // apply options bytes immediate - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - - return (ret); -} - -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t option_byte; - int ret = 0; - (void)addr; - (void)len; - - // Clear errors - clear_flash_error(sl); - - write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); - - // write option byte, ensuring we dont lock opt, and set strt bit - stlink_write_debug32(sl, FLASH_F4_OPTCR, - (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | - (1 << FLASH_F4_OPTCR_START)); - - wait_flash_busy(sl); - ret = check_flash_error(sl); - - // option bytes are reloaded at reset only, no obl. */ return (ret); } +// 291 +uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { + if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || + (sl->chip_id == STLINK_CHIPID_STM32_F4) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || + (sl->chip_id == STLINK_CHIPID_STM32_F411xx) || + (sl->chip_id == STLINK_CHIPID_STM32_F446) || + (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || + (sl->chip_id == STLINK_CHIPID_STM32_F72xxx) || + (sl->chip_id == STLINK_CHIPID_STM32_F412)) { + uint32_t sector = calculate_F4_sectornum(flashaddr); -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t option_byte; - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), - addr); - write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); - ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); + if (sector >= 12) { + sector -= 12; + } - if (addr == 0) { - addr = FLASH_F7_OPTCR; - ILOG("No address provided, using %#10x\n", addr); - } + if (sector < 4) { + sl->flash_pgsz = 0x4000; + } else if (sector < 5) { + sl->flash_pgsz = 0x10000; + } else { + sl->flash_pgsz = 0x20000; + } + } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || + sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { + uint32_t sector = calculate_F7_sectornum(flashaddr); - if (addr == FLASH_F7_OPTCR) { - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F7_OPTCR, - (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); - } else if (addr == FLASH_F7_OPTCR1) { - // Read FLASH_F7_OPTCR - uint32_t oldvalue; - stlink_read_debug32(sl, FLASH_F7_OPTCR, &oldvalue); - /* write option byte */ - stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_byte); - // Write FLASH_F7_OPTCR lock and start address - stlink_write_debug32(sl, FLASH_F7_OPTCR, - (oldvalue & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); - } else { - WLOG("WIP: write %#010x to address %#010x\n", option_byte, addr); - stlink_write_debug32(sl, addr, option_byte); + if (sector < 4) { + sl->flash_pgsz = 0x8000; + } else if (sector < 5) { + sl->flash_pgsz = 0x20000; + } else { + sl->flash_pgsz = 0x40000; + } } - wait_flash_busy(sl); - - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, - addr); - - /* option bytes are reloaded at reset only, no obl. */ - - return ret; + return ((uint32_t)sl->flash_pgsz); } +// 279 +int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, + size_t *size, uint32_t *begin) { + int res = 0; + *begin = UINT32_MAX; + uint8_t *data = NULL; + uint32_t end = 0; + bool eof_found = false; -/** - * Write STM32H7xx option bytes - * @param sl - * @param base option bytes to write - * @param addr of the memory mapped option bytes - * @param len number of bytes to write (must be multiple of 4) - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t val; - uint32_t data; - - // Wait until previous flash option has completed - wait_flash_busy(sl); - - // Clear previous error - stlink_write_debug32(sl, FLASH_H7_OPTCCR, - 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); - - while (len != 0) { - switch (addr) { - case FLASH_H7_REGS_ADDR + 0x20: // FLASH_OPTSR_PRG - case FLASH_H7_REGS_ADDR + 0x2c: // FLASH_PRAR_PRG1 - case FLASH_H7_REGS_ADDR + 0x34: // FLASH_SCAR_PRG1 - case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 - case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG - /* Write to FLASH_xxx_PRG registers */ - write_uint32((unsigned char *)&data, - *(uint32_t *)(base)); // write options bytes - - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - - /* Skip if the value in the CUR register is identical */ - stlink_read_debug32(sl, addr - 4, &val); - if (val == data) { + for (int scan = 0; (res == 0) && (scan < 2); ++scan) { + // parse file two times - first to find memory range, second - to fill it + if (scan == 1) { + if (!eof_found) { + ELOG("No EoF recond\n"); + res = -1; break; } - /* Write new option byte values and start modification */ - stlink_write_debug32(sl, addr, data); - stlink_read_debug32(sl, FLASH_H7_OPTCR, &val); - val |= (1 << FLASH_H7_OPTCR_OPTSTART); - stlink_write_debug32(sl, FLASH_H7_OPTCR, val); - - /* Wait for the option bytes modification to complete */ - do { - stlink_read_debug32(sl, FLASH_H7_OPTSR_CUR, &val); - } while ((val & (1 << FLASH_H7_OPTSR_OPT_BUSY)) != 0); - - /* Check for errors */ - if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { - stlink_write_debug32(sl, FLASH_H7_OPTCCR, - 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); - return -1; + if (*begin >= end) { + ELOG("No data found in file\n"); + res = -1; + break; } - break; - - default: - /* Skip non-programmable registers */ - break; - } - - len -= 4; - addr += 4; - base += 4; - } - return 0; -} + *size = (end - *begin) + 1; + data = calloc(*size, 1); // use calloc to get NULL if out of memory -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_Gx(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); -} + if (!data) { + ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_Gx(sl, option_byte); -} + memset(data, erased_pattern, *size); + } -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f2(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); -} + FILE *file = fopen(path, "r"); -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_f2(sl, option_byte); -} + if (!file) { + ELOG("Cannot open file\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f4(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); -} + uint32_t lba = 0; + char line[1 + 5 * 2 + 255 * 2 + 2]; -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_f4(sl, option_byte); -} + while (fgets(line, sizeof(line), file)) { + if (line[0] == '\n' || line[0] == '\r') { + continue; + } // skip empty lines -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f7(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); - return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); -} + if (line[0] != ':') { // no marker - wrong file format + ELOG("Wrong file format - no marker\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f0(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); - return stlink_read_debug32(sl, FLASH_OBR, option_byte); -} + size_t l = strlen(line); -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register1_f7(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register 1 byte from %#10x\n", - FLASH_F7_OPTCR1); - return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); -} + while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { + --l; + } // trim EoL -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { - DLOG("@@@@ Read option byte boot address\n"); - return stlink_read_option_control_register1_f7(sl, option_byte); -} + if ((l < 11) || + (l == + (sizeof(line) - 1))) { // line too short or long - wrong file format + ELOG("Wrong file format - wrong line length\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - * - * Since multiple bytes can be read, we read and print all but one here - * and then return the last one just like other devices - */ -int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { - int err = -1; - for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { - err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), - option_byte); - if (err == -1) { - return err; - } else { - printf("%08x\n", *option_byte); - } - } + uint8_t chksum = 0; // check sum - return stlink_read_debug32( - sl, - sl->option_base + (uint32_t)(sl->option_size / 4 - 1) * sizeof(uint32_t), - option_byte); -} + for (size_t i = 1; i < l; i += 2) { + chksum += stlink_parse_hex(line + i); + } -/** - * Read first option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { - DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); - return stlink_read_debug32(sl, sl->option_base, option_byte); -} + if (chksum != 0) { + ELOG("Wrong file format - checksum mismatch\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -// int stlink_read_option_bytes_boot_add_generic(stlink_t *sl, uint32_t* -// option_byte) { -// DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); -// return stlink_read_debug32(sl, sl->option_base, option_byte); -//} + uint8_t reclen = stlink_parse_hex(line + 1); -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -// int stlink_read_option_control_register_generic(stlink_t *sl, uint32_t* -// option_byte) { -// DLOG("@@@@ Read option control register byte from %#10x\n", -// sl->option_base); return stlink_read_debug32(sl, sl->option_base, -// option_byte); -//} + if (((uint32_t)reclen + 5) * 2 + 1 != l) { + ELOG("Wrong file format - record length mismatch\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -// int stlink_read_option_control_register1_generic(stlink_t *sl, uint32_t* -// option_byte) { -// DLOG("@@@@ Read option control register 1 byte from %#10x\n", -// sl->option_base); return stlink_read_debug32(sl, sl->option_base, -// option_byte); -//} + uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | + ((uint16_t)stlink_parse_hex(line + 5)); + uint8_t rectype = stlink_parse_hex(line + 7); -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return (-1); - } + switch (rectype) { + case 0: /* Data */ + if (scan == 0) { + uint32_t b = lba + offset; + uint32_t e = b + reclen - 1; - switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: - return stlink_read_option_bytes_f2(sl, option_byte); - case STLINK_CHIPID_STM32_F4: - case STLINK_CHIPID_STM32_F446: - return stlink_read_option_bytes_f4(sl, option_byte); - case STLINK_CHIPID_STM32_F76xxx: - return stlink_read_option_bytes_f7(sl, option_byte); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: - return stlink_read_option_bytes_Gx(sl, option_byte); - default: - return stlink_read_option_bytes_generic(sl, option_byte); - } -} + if (b < *begin) { + *begin = b; + } -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes boot address read is currently not supported for " - "connected chip\n"); - return -1; - } + if (e > end) { + end = e; + } + } else { + for (uint8_t i = 0; i < reclen; ++i) { + uint8_t b = stlink_parse_hex(line + 9 + i * 2); + uint32_t addr = lba + offset + i; - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: - return stlink_read_option_bytes_boot_add_f7(sl, option_byte); - default: - return -1; - // return stlink_read_option_bytes_boot_add_generic(sl, option_byte); - } -} + if (addr >= *begin && addr <= end) { + data[addr - *begin] = b; + } + } + } + break; + case 1: /* EoF */ + eof_found = true; + break; + case 2: /* Extended Segment Address, unexpected */ + res = -1; + break; + case 3: /* Start Segment Address, unexpected */ + res = -1; + break; + case 4: /* Extended Linear Address */ + if (reclen == 2) { + lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | + ((uint32_t)stlink_parse_hex(line + 11) << 16); + } else { + ELOG("Wrong file format - wrong LBA length\n"); + res = -1; + } + break; + case 5: /* Start Linear Address - expected, but ignore */ + break; + default: + ELOG("Wrong file format - unexpected record type %d\n", rectype); + res = -1; + } -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; - } + if (res != 0) { + break; + } + } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - return stlink_read_option_control_register_f0(sl, option_byte); - case STLINK_FLASH_TYPE_F7: - return stlink_read_option_control_register_f7(sl, option_byte); - default: - return -1; + fclose(file); } -} -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register1_32(stlink_t *sl, - uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; + if (res == 0) { + *mem = data; + } else { + free(data); } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: - return stlink_read_option_control_register1_f7(sl, option_byte); - default: - return -1; - // return stlink_read_option_control_register1_generic(sl, option_byte); + return (res); +} +// 280 +uint8_t stlink_get_erased_pattern(stlink_t *sl) { + if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + return (0x00); + } else { + return (0xff); } } +// 322 +int stlink_target_connect(stlink_t *sl, enum connect_type connect) { + if (connect == CONNECT_UNDER_RESET) { + stlink_enter_swd_mode(sl); -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { - WLOG("About to write option byte %#10x to %#10x.\n", option_byte, - sl->option_base); - return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, - 4); -} + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len) { - int ret = -1; + // try to halt the core before reset + // this is useful if the NRST pin is not connected + sl->backend->force_debug(sl); - if (sl->option_base == 0) { - ELOG( - "Option bytes writing is currently not supported for connected chip\n"); - return (-1); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(20); + + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); + + // try to halt the core after reset + unsigned timeout = time_ms() + 10; + while (time_ms() < timeout) { + sl->backend->force_debug(sl); + usleep(100); + } + + // check NRST connection + uint32_t dhcsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + WLOG("NRST is not connected\n"); + } + + // addition soft reset for halt before the first instruction + stlink_soft_reset(sl, 1 /* halt on reset */); } - if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { - ELOG("Option bytes start address out of Option bytes range\n"); - return (-1); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE && + stlink_enter_swd_mode(sl)) { + printf("Failed to enter SWD mode\n"); + return -1; } - if (addr + len > sl->option_base + sl->option_size) { - ELOG("Option bytes data too long\n"); - return (-1); + if (connect == CONNECT_NORMAL) { + stlink_reset(sl, RESET_AUTO); } - wait_flash_busy(sl); + return stlink_load_device_params(sl); +} - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return (-1); - } +// End of delegates.... functions below are private to this module +// same as above with entrypoint. - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return (-1); - } +static void stop_wdg_in_debug(stlink_t *sl) { + uint32_t dbgmcu_cr; + uint32_t set; + uint32_t value; switch (sl->flash_type) { case STLINK_FLASH_TYPE_F0: case STLINK_FLASH_TYPE_F1_XL: - ret = stlink_write_option_bytes_f0(sl, base, addr, len); + case STLINK_FLASH_TYPE_G4: + dbgmcu_cr = STM32F0_DBGMCU_CR; + set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | + (1 << STM32F0_DBGMCU_CR_WWDG_STOP); break; case STLINK_FLASH_TYPE_F4: - ret = stlink_write_option_bytes_f4(sl, base, addr, len); - break; case STLINK_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_f7(sl, base, addr, len); - break; - case STLINK_FLASH_TYPE_L0: - ret = stlink_write_option_bytes_l0(sl, base, addr, len); - break; case STLINK_FLASH_TYPE_L4: - ret = stlink_write_option_bytes_l4(sl, base, addr, len); + dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; + set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | + (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); break; + case STLINK_FLASH_TYPE_L0: case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: - ret = stlink_write_option_bytes_gx(sl, base, addr, len); + dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; + set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | + (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); break; case STLINK_FLASH_TYPE_H7: - ret = stlink_write_option_bytes_h7(sl, base, addr, len); + dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; + set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP); break; - default: - ELOG("Option bytes writing is currently not implemented for connected " - "chip\n"); + case STLINK_FLASH_TYPE_WB: + dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1; + set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) | + (1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP); break; + default: + return; } - if (ret) { - ELOG("Flash option write failed!\n"); - } else { - ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + if (!stlink_read_debug32(sl, dbgmcu_cr, &value)) { + stlink_write_debug32(sl, dbgmcu_cr, value | set); } +} - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); - - return ret; +int stlink_jtag_reset(stlink_t *sl, int value) { + DLOG("*** stlink_jtag_reset %d ***\n", value); + return (sl->backend->jtag_reset(sl, value)); } -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_control_register_f7(stlink_t *sl, - uint32_t option_control_register) { - int ret = 0; +int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { + int ret; + unsigned timeout; + uint32_t dhcsr, dfsr; + + DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); + + // halt core and enable debugging (if not already done) + // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_DEBUGEN); - // Clear errors - clear_flash_error(sl); + // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) + if (halt_on_reset) { + stlink_write_debug32( + sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); - ILOG("Asked to write option control register 1 %#10x to %#010x.\n", - option_control_register, FLASH_F7_OPTCR); + // clear VCATCH in the DFSR register + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); + } else { + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | + STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR); + } - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F7_OPTCR, - (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); + // clear S_RESET_ST in the DHCSR register + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - wait_flash_busy(sl); + // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) + ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, + STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ); + if (ret) { + ELOG("Soft reset failed: error write to AIRCR\n"); + return (ret); + } - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, - FLASH_F7_OPTCR); + // waiting for a reset within 500ms + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + timeout = time_ms() + 500; + while (time_ms() < timeout) { + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + if (halt_on_reset) { + // waiting halt by the SYSRESETREQ exception + // DDI0403E, p. C1-699, Debug Fault Status Register + dfsr = 0; + stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { + continue; + } + } + timeout = 0; + break; + } + } - return ret; -} + // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); + if (timeout) { + ELOG("Soft reset failed: timeout\n"); + return (-1); + } + return (0); +} /** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. + * Decode the version bits, originally from -sg, verified with usb + * @param sl stlink context, assumed to contain valid data in the buffer + * @param slv output parsed version object */ -static int -stlink_write_option_control_register_f0(stlink_t *sl, - uint32_t option_control_register) { - int ret = 0; - uint16_t opt_val[8]; - unsigned protection, optiondata; - uint16_t user_options, user_data, rdp; - unsigned option_offset, user_data_offset; +void _parse_version(stlink_t *sl, stlink_version_t *slv) { + sl->version.flags = 0; + + if (sl->version.stlink_v < 3) { + uint32_t b0 = sl->q_buf[0]; // lsb + uint32_t b1 = sl->q_buf[1]; + uint32_t b2 = sl->q_buf[2]; + uint32_t b3 = sl->q_buf[3]; + uint32_t b4 = sl->q_buf[4]; + uint32_t b5 = sl->q_buf[5]; // msb - ILOG("Asked to write option control register %#10x to %#010x.\n", - option_control_register, FLASH_OBR); + // b0 b1 || b2 b3 | b4 b5 + // 4b | 6b | 6b || 2B | 2B + // stlink_v | jtag_v | swim_v || st_vid | stlink_pid - /* Clear errors */ - clear_flash_error(sl); + slv->stlink_v = (b0 & 0xf0) >> 4; + slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); + slv->swim_v = b1 & 0x3f; + slv->st_vid = (b3 << 8) | b2; + slv->stlink_pid = (b5 << 8) | b4; - /* Retrieve current values */ - ret = stlink_read_debug32(sl, FLASH_OBR, &optiondata); - if (ret) { - return ret; + // ST-LINK/V1 from J11 switch to api-v2 (and support SWD) + if (slv->stlink_v == 1) { + slv->jtag_api = + slv->jtag_v > 11 ? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; + } else { + slv->jtag_api = STLINK_JTAG_API_V2; + + // preferred API to get last R/W status from J15 + if (sl->version.jtag_v >= 15) { + sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + } + + if (sl->version.jtag_v >= 13) { + sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V2_MAX_TRACE_FREQUENCY; + } + } + } else { + // V3 uses different version format, for reference see OpenOCD source + // (that was written from docs available from ST under NDA): + // https://github.com/ntfreak/openocd/blob/a6dacdff58ef36fcdac00c53ec27f19de1fbce0d/src/jtag/drivers/stlink_usb.c#L965 + slv->stlink_v = sl->q_buf[0]; + slv->swim_v = sl->q_buf[1]; + slv->jtag_v = sl->q_buf[2]; + slv->st_vid = (uint32_t)((sl->q_buf[9] << 8) | sl->q_buf[8]); + slv->stlink_pid = (uint32_t)((sl->q_buf[11] << 8) | sl->q_buf[10]); + slv->jtag_api = STLINK_JTAG_API_V3; + /* preferred API to get last R/W status */ + sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V3_MAX_TRACE_FREQUENCY; } - ret = stlink_read_debug32(sl, FLASH_WRPR, &protection); - if (ret) { - return ret; + + return; +} + +void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { + stlink_write_reg(sl, addr, 15); /* pc register */ + stlink_run(sl, RUN_NORMAL); + + while (stlink_is_core_halted(sl)) { + usleep(3000000); } +} - /* Translate OBR value to flash store structure - * F0: RM0091, Option byte description, pp. 75-78 - * F1: PM0075, Option byte description, pp. 19-22 - * F3: RM0316, Option byte description, pp. 85-87 */ - switch(sl->chip_id) - { - case 0x422: /* STM32F30x */ - case 0x432: /* STM32F37x */ - case 0x438: /* STM32F303x6/8 and STM32F328 */ - case 0x446: /* STM32F303xD/E and STM32F398xE */ - case 0x439: /* STM32F302x6/8 */ - case 0x440: /* STM32F05x */ - case 0x444: /* STM32F03x */ - case 0x445: /* STM32F04x */ - case 0x448: /* STM32F07x */ - case 0x442: /* STM32F09x */ - option_offset = 6; - user_data_offset = 16; - rdp = 0x55AA; - break; - default: - option_offset = 0; - user_data_offset = 10; - rdp = 0x5AA5; - break; +/* Limit the block size to compare to 0x1800 as anything larger will stall the + * STLINK2 Maybe STLINK V1 needs smaller value! + */ +int check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { + size_t off; + size_t n_cmp = sl->flash_pgsz; + + if (n_cmp > 0x1800) { + n_cmp = 0x1800; } - user_options = (option_control_register >> option_offset >> 2) & 0xFFFF; - user_data = (option_control_register >> user_data_offset) & 0xFFFF; + for (off = 0; off < mf->len; off += n_cmp) { + size_t aligned_size; + + size_t cmp_size = n_cmp; // adjust last page size -#define VAL_WITH_COMPLEMENT(v) (uint16_t)(((v)&0xFF) | (((~(v))<<8)&0xFF00)) + if ((off + n_cmp) > mf->len) { + cmp_size = mf->len - off; + } - opt_val[0] = (option_control_register & (1 << 1/*OPT_READOUT*/)) ? 0xFFFF : rdp; - opt_val[1] = VAL_WITH_COMPLEMENT(user_options); - opt_val[2] = VAL_WITH_COMPLEMENT(user_data); - opt_val[3] = VAL_WITH_COMPLEMENT(user_data >> 8); - opt_val[4] = VAL_WITH_COMPLEMENT(protection); - opt_val[5] = VAL_WITH_COMPLEMENT(protection >> 8); - opt_val[6] = VAL_WITH_COMPLEMENT(protection >> 16); - opt_val[7] = VAL_WITH_COMPLEMENT(protection >> 24); + aligned_size = cmp_size; -#undef VAL_WITH_COMPLEMENT + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } - /* Write bytes and check errors */ - ret = stlink_write_option_bytes_f0(sl, (uint8_t*)opt_val, STM32_F0_OPTION_BYTES_BASE, sizeof(opt_val)); - if (ret) - return ret; + stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - ret = check_flash_error(sl); - if (!ret) { - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, - FLASH_OBR); + if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { + return (-1); + } } - return ret; + return (0); } -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_control_register1_f7(stlink_t *sl, - uint32_t option_control_register1) { - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - ILOG("Asked to write option control register 1 %#010x to %#010x.\n", - option_control_register1, FLASH_F7_OPTCR1); +void md5_calculate(mapped_file_t *mf) { + // calculate md5 checksum of given binary file + Md5Context md5Context; + MD5_HASH md5Hash; + Md5Initialise(&md5Context); + Md5Update(&md5Context, mf->base, (uint32_t)mf->len); + Md5Finalise(&md5Context, &md5Hash); + printf("md5 checksum: "); - /* write option byte, ensuring we dont lock opt, and set strt bit */ - uint32_t current_control_register_value; - stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); + for (int i = 0; i < (int)sizeof(md5Hash); i++) { + printf("%x", md5Hash.bytes[i]); + } - /* write option byte */ - stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); - stlink_write_debug32( - sl, FLASH_F7_OPTCR, - (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); + printf(", "); +} - wait_flash_busy(sl); +void stlink_checksum(mapped_file_t *mp) { + /* checksum that backward compatible with official ST tools */ + uint32_t sum = 0; + uint8_t *mp_byte = (uint8_t *)mp->base; - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, - FLASH_F7_OPTCR1); + for (size_t i = 0; i < mp->len; ++i) { + sum += mp_byte[i]; + } - return ret; + printf("stlink checksum: 0x%08x\n", sum); } -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_bytes_boot_add_f7(stlink_t *sl, - uint32_t option_byte_boot_add) { - ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); - return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); +void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { + unsigned int val; + // set PC to the reset routine + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); + stlink_run(sl, RUN_NORMAL); } -/** - * Write option bytes - * @param sl - * @param option bytes boot address to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_bytes_boot_add32(stlink_t *sl, - uint32_t option_bytes_boot_add) { - int ret = -1; - - wait_flash_busy(sl); +static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, + save_block_fn fn, void *fn_arg) { - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return -1; - } + int error = -1; - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; + if (size < 1) { + size = sl->flash_size; } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); - break; - default: - ELOG("Option bytes boot address writing is currently not implemented for " - "connected chip\n"); - break; + if (size > sl->flash_size) { + size = sl->flash_size; } - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); + for (size_t off = 0; off < size; off += cmp_size) { + size_t aligned_size; - return ret; -} + // adjust last page size + if ((off + cmp_size) > size) { + cmp_size = size - off; + } -/** - * Write option bytes - * @param sl - * @param option bytes boot address to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_control_register32(stlink_t *sl, - uint32_t option_control_register) { - int ret = -1; + aligned_size = cmp_size; - wait_flash_busy(sl); + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return -1; - } + stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; + if (!fn(fn_arg, sl->q_buf, aligned_size)) { + goto on_error; + } } - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: - ret = stlink_write_option_control_register_f0(sl, option_control_register); - break; - case STLINK_FLASH_TYPE_F7: - ret = stlink_write_option_control_register_f7(sl, option_control_register); - break; - default: - ELOG("Option control register writing is currently not implemented for " - "connected chip\n"); - break; - } + error = 0; // success - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option control register %#010x!\n", option_control_register); +on_error: + return (error); +} - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); +static bool stlink_fread_worker(void *arg, uint8_t *block, ssize_t len) { + struct stlink_fread_worker_arg *the_arg = + (struct stlink_fread_worker_arg *)arg; - return ret; + if (write(the_arg->fd, block, len) != len) { + fprintf(stderr, "write() != aligned_size\n"); + return (false); + } else { + return (true); + } } -/** - * Write option bytes - * @param sl - * @param option bytes boot address to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_control_register1_32( - stlink_t *sl, uint32_t option_control_register1) { - int ret = -1; +// TODO: length not checked +static uint8_t stlink_parse_hex(const char *hex) { + uint8_t d[2]; - wait_flash_busy(sl); + for (int i = 0; i < 2; ++i) { + char c = *(hex + i); - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return -1; + if (c >= '0' && c <= '9') { + d[i] = c - '0'; + } else if (c >= 'A' && c <= 'F') { + d[i] = c - 'A' + 10; + } else if (c >= 'a' && c <= 'f') { + d[i] = c - 'a' + 10; + } else { + return (0); // error + } } - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; - } + return ((d[0] << 4) | (d[1])); +} - switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: - ret = - stlink_write_option_control_register1_f7(sl, option_control_register1); - break; - default: - ELOG("Option control register 1 writing is currently not implemented for " - "connected chip\n"); - break; +static bool +stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { + uint32_t addr = the_arg->addr; + uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + + (uint8_t)((addr & 0x00FF0000) >> 16); + + if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", + (addr & 0xFFFF0000) >> 16, (uint8_t)(0x100 - sum))) { + return (false); } - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); + the_arg->lba = (addr & 0xFFFF0000); + return (true); +} - lock_flash_option(sl); - lock_flash(sl); +static bool +stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { + uint8_t count = the_arg->buf_pos; - return (ret); -} + if (count == 0) { + return (true); + } -/** - * Write the given binary file with option bytes - * @param sl - * @param path readable file path, should be binary image - * @param addr of the memory mapped option bytes - * @return 0 on success, -ve on failure. - */ -int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, - stm32_addr_t addr) { - /* Write the file in flash at addr */ - int err; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; + uint32_t addr = the_arg->addr; - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); - return (-1); + if (the_arg->lba != (addr & 0xFFFF0000)) { // segment changed + if (!stlink_fread_ihex_newsegment(the_arg)) { + return (false); + } } - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); + uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + + (uint8_t)(addr & 0x000000FF); - err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); - stlink_fwrite_finalize(sl, addr); - unmap_file(&mf); + if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) { + return (false); + } - return (err); -} + for (uint8_t i = 0; i < count; ++i) { + uint8_t b = the_arg->buf[i]; + sum += b; -int stlink_target_connect(stlink_t *sl, enum connect_type connect) { - if (connect == CONNECT_UNDER_RESET) { - stlink_enter_swd_mode(sl); + if (2 != fprintf(the_arg->file, "%02X", b)) { + return (false); + } + } - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); + if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) { + return (false); + } - // try to halt the core before reset - // this is useful if the NRST pin is not connected - sl->backend->force_debug(sl); + the_arg->addr += count; + the_arg->buf_pos = 0; - // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) - usleep(20); + return (true); +} - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); +static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *the_arg, + int fd, stm32_addr_t addr) { + the_arg->file = fdopen(fd, "w"); + the_arg->addr = addr; + the_arg->lba = 0; + the_arg->buf_pos = 0; - // try to halt the core after reset - unsigned timeout = time_ms() + 10; - while (time_ms() < timeout) { - sl->backend->force_debug(sl); - usleep(100); - } + return (the_arg->file != NULL); +} - // check NRST connection - uint32_t dhcsr = 0; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - WLOG("NRST is not connected\n"); +static bool stlink_fread_ihex_worker(void *arg, uint8_t *block, ssize_t len) { + struct stlink_fread_ihex_worker_arg *the_arg = + (struct stlink_fread_ihex_worker_arg *)arg; + + for (ssize_t i = 0; i < len; ++i) { + if (the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full + if (!stlink_fread_ihex_writeline(the_arg)) { + return (false); + } } - // addition soft reset for halt before the first instruction - stlink_soft_reset(sl, 1 /* halt on reset */); + the_arg->buf[the_arg->buf_pos++] = block[i]; } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE && - stlink_enter_swd_mode(sl)) { - printf("Failed to enter SWD mode\n"); - return -1; + return (true); +} + +static bool +stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { + if (!stlink_fread_ihex_writeline(the_arg)) { + return (false); } - if (connect == CONNECT_NORMAL) { - stlink_reset(sl, RESET_AUTO); + // FIXME: do we need the Start Linear Address? + + if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) { // EoF + return (false); } - return stlink_load_device_params(sl); + return (0 == fclose(the_arg->file)); } diff --git a/src/common_flash.c b/src/common_flash.c index 4f7f46257..1f438c74f 100644 --- a/src/common_flash.c +++ b/src/common_flash.c @@ -1,6 +1,7 @@ #include #include #include +#include #include "calculate.h" #include "common_flash.h" #include "map_file.h" diff --git a/src/flashloader.c b/src/flashloader.c index df14e506c..f84e16ef0 100644 --- a/src/flashloader.c +++ b/src/flashloader.c @@ -1,4 +1,5 @@ #include +#include #include #include "common_flash.h" diff --git a/src/map_file.c b/src/map_file.c index 5282fae27..cb7d4f525 100644 --- a/src/map_file.c +++ b/src/map_file.c @@ -1,10 +1,17 @@ #include #include #include +#include // for close #include +#include + #include "map_file.h" +#ifndef O_BINARY +#define O_BINARY 0 +#endif + #ifndef MAX_FILE_SIZE #define MAX_FILE_SIZE (1<<20) // 1 GB max file size #endif diff --git a/src/option.c b/src/option.c index b70f7a533..ed9ee4f39 100644 --- a/src/option.c +++ b/src/option.c @@ -1,4 +1,5 @@ #include +#include #include #include "common_flash.h" #include "map_file.h" diff --git a/src/read_write.c b/src/read_write.c index adcda6f3b..efaa5a25f 100644 --- a/src/read_write.c +++ b/src/read_write.c @@ -1,4 +1,5 @@ #include +#include #include // Endianness From 8d96e769f32d1c85be913f77e6aab4b1d84b80b1 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 20 Jan 2022 23:19:10 +0100 Subject: [PATCH 1292/1435] Updated device parametres - Human-readable FLASH_TYPE in .chip files - Added enum for STM32_CORE_IDs --- config/chips/F03x.chip | 2 +- config/chips/F04x.chip | 2 +- config/chips/F05x.chip | 2 +- config/chips/F07x.chip | 2 +- config/chips/F09x.chip | 2 +- config/chips/F1xx_CL.chip | 2 +- config/chips/F1xx_HD.chip | 2 +- config/chips/F1xx_LD.chip | 2 +- config/chips/F1xx_MD.chip | 2 +- config/chips/F1xx_VL_HD.chip | 2 +- config/chips/F1xx_VL_MD_LD.chip | 2 +- config/chips/F1xx_XLD.chip | 2 +- config/chips/F2xx.chip | 2 +- config/chips/F301_F302_F318.chip | 2 +- config/chips/F302_F303_F358.chip | 2 +- config/chips/F302_F303_F398_HD.chip | 2 +- config/chips/F303_F328_F334.chip | 2 +- config/chips/F37x.chip | 2 +- config/chips/F401xB_xC.chip | 2 +- config/chips/F401xD_xE.chip | 2 +- config/chips/F410.chip | 2 +- config/chips/F411xC_xE.chip | 2 +- config/chips/F412.chip | 2 +- config/chips/F413_F423.chip | 2 +- config/chips/F42x_F43x.chip | 2 +- config/chips/F446.chip | 2 +- config/chips/F46x_F47x.chip | 2 +- config/chips/F4x5_F4x7.chip | 2 +- config/chips/F72x_F73x.chip | 2 +- config/chips/F74x_F75x.chip | 2 +- config/chips/F76x_F77x.chip | 2 +- config/chips/G03x_G04x.chip | 2 +- config/chips/G05x_G06x.chip | 2 +- config/chips/G07x_G08x.chip | 2 +- config/chips/G0Bx_G0Cx.chip | 2 +- config/chips/G43x_G44x.chip | 2 +- config/chips/G47x_G48x.chip | 2 +- config/chips/G49x_G4Ax.chip | 2 +- config/chips/H72x_H73x.chip | 2 +- config/chips/H74x_H75x.chip | 2 +- config/chips/H7Ax_H7Bx.chip | 2 +- config/chips/L0xxx_Cat_1.chip | 2 +- config/chips/L0xxx_Cat_2.chip | 2 +- config/chips/L0xxx_Cat_3.chip | 2 +- config/chips/L0xxx_Cat_5.chip | 2 +- config/chips/L1xx_Cat_1.chip | 2 +- config/chips/L1xx_Cat_2.chip | 2 +- config/chips/L1xx_Cat_3.chip | 2 +- config/chips/L1xx_Cat_4.chip | 2 +- config/chips/L1xx_Cat_5.chip | 2 +- config/chips/L41x_L42x.chip | 2 +- config/chips/L43x_L44x.chip | 2 +- config/chips/L45x_L46x.chip | 2 +- config/chips/L47x_L48x.chip | 2 +- config/chips/L496x_L4A6x.chip | 2 +- config/chips/L4Px.chip | 2 +- config/chips/L4Rx.chip | 2 +- config/chips/{L5x5.chip => L5x5.chip.txt} | 2 +- config/chips/{U5x5.chip => U5x5.chip.txt} | 2 +- config/chips/WBx0_WBx5.chip | 2 +- config/chips/WLx5.chip | 2 +- config/chips/unknown_device.chip | 2 +- inc/stm32.h | 49 +++++++----------- src/stlink-lib/chipid.c | 63 +++++++++++++++-------- 64 files changed, 123 insertions(+), 113 deletions(-) rename config/chips/{L5x5.chip => L5x5.chip.txt} (85%) rename config/chips/{U5x5.chip => U5x5.chip.txt} (85%) diff --git a/config/chips/F03x.chip b/config/chips/F03x.chip index c0a6e5200..84543dc23 100644 --- a/config/chips/F03x.chip +++ b/config/chips/F03x.chip @@ -3,7 +3,7 @@ dev_type STM32F03x ref_manual_id 0091 chip_id 0x444 // STM32_CHIPID_F0xx_SMALL -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB sram_size 0x1000 // 4 KB diff --git a/config/chips/F04x.chip b/config/chips/F04x.chip index 9b2ee5586..322e61e51 100644 --- a/config/chips/F04x.chip +++ b/config/chips/F04x.chip @@ -3,7 +3,7 @@ dev_type STM32F04x ref_manual_id 0091 chip_id 0x445 // STM32_CHIPID_F04 -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB sram_size 0x1800 // 6 KB diff --git a/config/chips/F05x.chip b/config/chips/F05x.chip index c32ba0b46..3ba9566eb 100644 --- a/config/chips/F05x.chip +++ b/config/chips/F05x.chip @@ -3,7 +3,7 @@ dev_type STM32F05x ref_manual_id 0091 chip_id 0x440 // STM32_CHIPID_F0 -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x400 // 1 KB sram_size 0x2000 // 8 KB diff --git a/config/chips/F07x.chip b/config/chips/F07x.chip index 5ba832058..4b1465ca6 100644 --- a/config/chips/F07x.chip +++ b/config/chips/F07x.chip @@ -3,7 +3,7 @@ dev_type STM32F07x ref_manual_id 0091 chip_id 0x448 // STM32_CHIPID_F0_CAN -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x4000 // 16 KB diff --git a/config/chips/F09x.chip b/config/chips/F09x.chip index ca987123d..eb6dec428 100644 --- a/config/chips/F09x.chip +++ b/config/chips/F09x.chip @@ -3,7 +3,7 @@ dev_type STM32F09x ref_manual_id 0091 chip_id 0x442 // STM32_CHIPID_F09x -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index 0f56362f0..d774412e1 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_CL ref_manual_id 0008 chip_id 0x418 // STM32_CHIPID_F1_CONN -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F1xx_HD.chip b/config/chips/F1xx_HD.chip index 2af8582e6..f454e2a1c 100644 --- a/config/chips/F1xx_HD.chip +++ b/config/chips/F1xx_HD.chip @@ -3,7 +3,7 @@ dev_type F1xx_HD ref_manual_id 0008 chip_id 0x414 // STM32_CHIPID_F1_HD -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F1xx_LD.chip b/config/chips/F1xx_LD.chip index ffd34fd4a..50f115148 100644 --- a/config/chips/F1xx_LD.chip +++ b/config/chips/F1xx_LD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_LD ref_manual_id 0008 chip_id 0x412 // STM32_CHIPID_F1_LD -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB sram_size 0x2800 // 10 KB diff --git a/config/chips/F1xx_MD.chip b/config/chips/F1xx_MD.chip index f27a7a062..17af311c1 100644 --- a/config/chips/F1xx_MD.chip +++ b/config/chips/F1xx_MD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_MD ref_manual_id 0008 chip_id 0x410 // STM32_CHIPID_F1_MD -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB sram_size 0x5000 // 20 KB diff --git a/config/chips/F1xx_VL_HD.chip b/config/chips/F1xx_VL_HD.chip index 4f2566949..c77e013ce 100644 --- a/config/chips/F1xx_VL_HD.chip +++ b/config/chips/F1xx_VL_HD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_VL_HD ref_manual_id 0041 chip_id 0x428 // STM32_CHIPID_F1_VL_HD -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/F1xx_VL_MD_LD.chip b/config/chips/F1xx_VL_MD_LD.chip index 1705bc8e3..467fb786f 100644 --- a/config/chips/F1xx_VL_MD_LD.chip +++ b/config/chips/F1xx_VL_MD_LD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_VL_MD_LD ref_manual_id 0041 chip_id 0x420 // STM32_CHIPID_F1_VL_MD_LD -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7e0 flash_pagesize 0x400 // 1 KB sram_size 0x2000 // 8 KB /* 0x1000 for low density devices */ diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip index 37c900f28..622bd9d02 100644 --- a/config/chips/F1xx_XLD.chip +++ b/config/chips/F1xx_XLD.chip @@ -3,7 +3,7 @@ dev_type STM32F1xx_XLD ref_manual_id 0008 chip_id 0x430 // STM32_CHIPID_F1_XLD -flash_type 2 // STM32_FLASH_TYPE_F1_XL +flash_type F1_XL flash_size_reg 0x1ffff7e0 flash_pagesize 0x800 // 2 KB sram_size 0x18000 // 96 KB diff --git a/config/chips/F2xx.chip b/config/chips/F2xx.chip index 314df7d6d..30ea174ee 100644 --- a/config/chips/F2xx.chip +++ b/config/chips/F2xx.chip @@ -3,7 +3,7 @@ dev_type STM32F2xx ref_manual_id 0033 chip_id 0x411 // STM32_CHIPID_F2 -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/F301_F302_F318.chip b/config/chips/F301_F302_F318.chip index f620364b2..408f1435e 100644 --- a/config/chips/F301_F302_F318.chip +++ b/config/chips/F301_F302_F318.chip @@ -3,7 +3,7 @@ dev_type STM32F301_F302_F318 ref_manual_id 0365 // also RM0366 chip_id 0x439 // STM32_CHIPID_F3xx_SMALL -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/F302_F303_F358.chip b/config/chips/F302_F303_F358.chip index e48370159..08c6dc371 100644 --- a/config/chips/F302_F303_F358.chip +++ b/config/chips/F302_F303_F358.chip @@ -3,7 +3,7 @@ dev_type STM32F302_F303_358 ref_manual_id 0365 // also RM0316 chip_id 0x422 // STM32_CHIPID_F3 -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/F302_F303_F398_HD.chip b/config/chips/F302_F303_F398_HD.chip index 181fdfa72..7b254c486 100644 --- a/config/chips/F302_F303_F398_HD.chip +++ b/config/chips/F302_F303_F398_HD.chip @@ -3,7 +3,7 @@ dev_type STM32F302_F303_F398_HD ref_manual_id 0365 // also RM0316 (Rev 5) chip_id 0x446 // STM32_CHIPID_F303_HD -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F303_F328_F334.chip b/config/chips/F303_F328_F334.chip index 069de07fb..daf299cea 100644 --- a/config/chips/F303_F328_F334.chip +++ b/config/chips/F303_F328_F334.chip @@ -3,7 +3,7 @@ dev_type STM32F303_F328_F334 ref_manual_id 0364 // also RM0316 chip_id 0x438 // STM32_CHIPID_F334 -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0x3000 // 12 KB diff --git a/config/chips/F37x.chip b/config/chips/F37x.chip index dfe59af0f..ac249f24f 100644 --- a/config/chips/F37x.chip +++ b/config/chips/F37x.chip @@ -3,7 +3,7 @@ dev_type STM32F37x ref_manual_id 0313 chip_id 0x432 // STM32_CHIPID_F37x -flash_type 1 // STM32_FLASH_TYPE_F0_F1_F3 +flash_type F0_F1_F3 flash_size_reg 0x1ffff7cc flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/F401xB_xC.chip b/config/chips/F401xB_xC.chip index d961e82b0..1022f0fe9 100644 --- a/config/chips/F401xB_xC.chip +++ b/config/chips/F401xB_xC.chip @@ -3,7 +3,7 @@ dev_type STM32F401xB_xC ref_manual_id 0368 chip_id 0x423 // STM32_CHIPID_F4_LP -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip index 1b58cb5ad..39748a604 100644 --- a/config/chips/F401xD_xE.chip +++ b/config/chips/F401xD_xE.chip @@ -3,7 +3,7 @@ dev_type STM32F401xD_xE ref_manual_id 0368 chip_id 0x433 // STM32_CHIPID_F4_DE -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x18000 // 96 KB diff --git a/config/chips/F410.chip b/config/chips/F410.chip index 55dbb749d..5c19450f6 100644 --- a/config/chips/F410.chip +++ b/config/chips/F410.chip @@ -3,7 +3,7 @@ dev_type STM32F410 ref_manual_id 0401 chip_id 0x458 // STM32_CHIPID_F410 -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/F411xC_xE.chip b/config/chips/F411xC_xE.chip index 51081d338..ce93aea26 100644 --- a/config/chips/F411xC_xE.chip +++ b/config/chips/F411xC_xE.chip @@ -3,7 +3,7 @@ dev_type STM32F411xC_xE ref_manual_id 0383 chip_id 0x431 // STM32_CHIPID_F411xx -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/F412.chip b/config/chips/F412.chip index 6e7aefd19..a04268349 100644 --- a/config/chips/F412.chip +++ b/config/chips/F412.chip @@ -3,7 +3,7 @@ dev_type STM32F412 ref_manual_id 0402 chip_id 0x441 // STM32_CHIPID_F412 -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F413_F423.chip b/config/chips/F413_F423.chip index 3a865d304..bb5dd5880 100644 --- a/config/chips/F413_F423.chip +++ b/config/chips/F413_F423.chip @@ -3,7 +3,7 @@ dev_type STM32F413_F423 ref_manual_id 0430 // RM0430 (Rev 2) chip_id 0x463 // STM32_CHIPID_F413 -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x50000 // 320 KB diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 64f459064..4452780b3 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -3,7 +3,7 @@ dev_type STM32F42x_F43x ref_manual_id 0090 // RM0090 (Rev. 2) chip_id 0x463 // STM32_CHIPID_F4_HD -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F446.chip b/config/chips/F446.chip index 51ee52517..e4d0bdec2 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -3,7 +3,7 @@ dev_type STM32F446 ref_manual_id 0390 chip_id 0x421 // STM32_CHIPID_F446 -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/F46x_F47x.chip b/config/chips/F46x_F47x.chip index 4d3931091..f20715ded 100644 --- a/config/chips/F46x_F47x.chip +++ b/config/chips/F46x_F47x.chip @@ -3,7 +3,7 @@ dev_type STM32F46x_F47x ref_manual_id 0090 // RM0090 (Rev. 2) chip_id 0x434 // STM32_CHIPID_F4_DSI -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F4x5_F4x7.chip b/config/chips/F4x5_F4x7.chip index f65281272..586ff0b8f 100644 --- a/config/chips/F4x5_F4x7.chip +++ b/config/chips/F4x5_F4x7.chip @@ -3,7 +3,7 @@ dev_type STM32F4x5_F4x7 ref_manual_id 0090 // RM0090 (Rev. 2) chip_id 0x413 // STM32_CHIPID_F4 -flash_type 3 // STM32_FLASH_TYPE_F2_F4 +flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB sram_size 0x30000 // 192 KB diff --git a/config/chips/F72x_F73x.chip b/config/chips/F72x_F73x.chip index acd411bed..04af2bb3e 100644 --- a/config/chips/F72x_F73x.chip +++ b/config/chips/F72x_F73x.chip @@ -3,7 +3,7 @@ dev_type STM32F72x_F73x ref_manual_id 0431 chip_id 0x452 // STM32_CHIPID_F72xxx -flash_type 4 // STM32_FLASH_TYPE_F7 +flash_type F7 flash_size_reg 0x1ff07a22 flash_pagesize 0x800 // 2 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/F74x_F75x.chip b/config/chips/F74x_F75x.chip index e081da39d..0664bb2d0 100644 --- a/config/chips/F74x_F75x.chip +++ b/config/chips/F74x_F75x.chip @@ -3,7 +3,7 @@ dev_type STM32F74x_F75x ref_manual_id 0385 chip_id 0x449 // STM32_CHIPID_F7 -flash_type 4 // STM32_FLASH_TYPE_F7 +flash_type F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB sram_size 0x50000 // 320 KB diff --git a/config/chips/F76x_F77x.chip b/config/chips/F76x_F77x.chip index c6d04ff78..dfc983254 100644 --- a/config/chips/F76x_F77x.chip +++ b/config/chips/F76x_F77x.chip @@ -3,7 +3,7 @@ dev_type STM32F76x_F77x ref_manual_id 0410 chip_id 0x451 // STM32_CHIPID_F76xxx -flash_type 4 // STM32_FLASH_TYPE_F7 +flash_type F7 flash_size_reg 0x1ff0f442 flash_pagesize 0x800 // 2 KB sram_size 0x80000 // 512 KB diff --git a/config/chips/G03x_G04x.chip b/config/chips/G03x_G04x.chip index fd6dc3bcf..a414b52ab 100644 --- a/config/chips/G03x_G04x.chip +++ b/config/chips/G03x_G04x.chip @@ -3,7 +3,7 @@ dev_type STM32G03x_G04x ref_manual_id 0444 // also RM454 chip_id 0x466 // STM32_CHIPID_G0_CAT1 -flash_type 5 // STM32_FLASH_TYPE_G0 +flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x2000 // 8 KB diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index ce5e52de4..ae074e584 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -3,7 +3,7 @@ dev_type STM32G05x_G06x ref_manual_id 0444 chip_id 0x456 // STM32_CHIPID_G0_CAT4 -flash_type 5 // STM32_FLASH_TYPE_G0 +flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x9000 // 36 KB diff --git a/config/chips/G07x_G08x.chip b/config/chips/G07x_G08x.chip index 7a10fc052..82b3992c2 100644 --- a/config/chips/G07x_G08x.chip +++ b/config/chips/G07x_G08x.chip @@ -3,7 +3,7 @@ dev_type STM32G07x_G08x ref_manual_id 0444 chip_id 0x460 // STM32_CHIPID_G0_CAT2 -flash_type 5 // STM32_FLASH_TYPE_G0 +flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x9000 // 36 KB diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index 6ab8ca55a..f21fd65a0 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -3,7 +3,7 @@ dev_type STM32G0Bx_G0Cx ref_manual_id 0444 chip_id 0x467 // STM32_CHIPID_G0_CAT3 -flash_type 5 // STM32_FLASH_TYPE_G0 +flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x9000 // 36 KB diff --git a/config/chips/G43x_G44x.chip b/config/chips/G43x_G44x.chip index a7eb86d34..26d1b2f1f 100644 --- a/config/chips/G43x_G44x.chip +++ b/config/chips/G43x_G44x.chip @@ -3,7 +3,7 @@ dev_type STM32G43x_G44x ref_manual_id 0440 chip_id 0x468 // STM32_CHIPID_G4_CAT2 -flash_type 6 // STM32_FLASH_TYPE_G4 +flash_type G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x8000 // 32 KB diff --git a/config/chips/G47x_G48x.chip b/config/chips/G47x_G48x.chip index 1b2b386fd..707727aca 100644 --- a/config/chips/G47x_G48x.chip +++ b/config/chips/G47x_G48x.chip @@ -3,7 +3,7 @@ dev_type STM32G47x_G48x ref_manual_id 0440 chip_id 0x469 // STM32_CHIPID_G4_CAT3 -flash_type 6 // STM32_FLASH_TYPE_G4 +flash_type G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip index 1defbfff8..3e8aacf4b 100644 --- a/config/chips/G49x_G4Ax.chip +++ b/config/chips/G49x_G4Ax.chip @@ -3,7 +3,7 @@ dev_type STM32G49x_G4Ax ref_manual_id 0440 chip_id 0x479 // STM32_CHIPID_G4_CAT4 -flash_type 6 // STM32_FLASH_TYPE_G4 +flash_type G4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x1c000 // 112 KB diff --git a/config/chips/H72x_H73x.chip b/config/chips/H72x_H73x.chip index 50925fdcd..194b740d4 100644 --- a/config/chips/H72x_H73x.chip +++ b/config/chips/H72x_H73x.chip @@ -3,7 +3,7 @@ dev_type STM32H72x_H73x ref_manual_id 0468 chip_id 0x483 // STM32_CHIPID_H72x -flash_type 7 // STM32_FLASH_TYPE_H7 +flash_type H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB "DTCM" diff --git a/config/chips/H74x_H75x.chip b/config/chips/H74x_H75x.chip index 20bfcd2cb..2b829f792 100644 --- a/config/chips/H74x_H75x.chip +++ b/config/chips/H74x_H75x.chip @@ -3,7 +3,7 @@ dev_type STM32H74x_H75x ref_manual_id 0433 chip_id 0x450 // STM32_CHIPID_H74xxx -flash_type 7 // STM32_FLASH_TYPE_H7 +flash_type H7 flash_size_reg 0x1ff1e880 flash_pagesize 0x20000 // 128 KB sram_size 0x20000 // 128 KB "DTCM" diff --git a/config/chips/H7Ax_H7Bx.chip b/config/chips/H7Ax_H7Bx.chip index b31e4fb88..0f66d2c77 100644 --- a/config/chips/H7Ax_H7Bx.chip +++ b/config/chips/H7Ax_H7Bx.chip @@ -3,7 +3,7 @@ dev_type STM32H7Ax_H7Bx ref_manual_id 0455 chip_id 0x480 // STM32_CHIPID_H7Ax -flash_type 7 // STM32_FLASH_TYPE_H7 +flash_type H7 flash_size_reg 0x08fff80c flash_pagesize 0x2000 // 8 KB sram_size 0x20000 // 128 KB "DTCM" diff --git a/config/chips/L0xxx_Cat_1.chip b/config/chips/L0xxx_Cat_1.chip index d612143d5..2cce4e23c 100644 --- a/config/chips/L0xxx_Cat_1.chip +++ b/config/chips/L0xxx_Cat_1.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_1 ref_manual_id 0451 // also RM0377 chip_id 0x457 // STM32_CHIPID_L011 -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_2.chip b/config/chips/L0xxx_Cat_2.chip index 49d3e8b07..aae0fac7b 100644 --- a/config/chips/L0xxx_Cat_2.chip +++ b/config/chips/L0xxx_Cat_2.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_2 ref_manual_id 0451 // also RM0377 chip_id 0x425 // STM32_CHIPID_L0_CAT2 -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_3.chip b/config/chips/L0xxx_Cat_3.chip index c1b6c3bf4..a04dc8376 100644 --- a/config/chips/L0xxx_Cat_3.chip +++ b/config/chips/L0xxx_Cat_3.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_3 ref_manual_id 0451 // also RM0367 & RM0377 chip_id 0x417 // STM32_CHIPID_L0 -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x2000 // 8 KB diff --git a/config/chips/L0xxx_Cat_5.chip b/config/chips/L0xxx_Cat_5.chip index 94e14dfe0..22cbb200a 100644 --- a/config/chips/L0xxx_Cat_5.chip +++ b/config/chips/L0xxx_Cat_5.chip @@ -3,7 +3,7 @@ dev_type STM32L0xxx_Cat_5 ref_manual_id 0451 // also RM0367 & RM0377 chip_id 0x447 // STM32_CHIPID_L0_CAT5 -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B sram_size 0x5000 // 20 KB diff --git a/config/chips/L1xx_Cat_1.chip b/config/chips/L1xx_Cat_1.chip index 16f2ff8c9..b1b3e85e7 100644 --- a/config/chips/L1xx_Cat_1.chip +++ b/config/chips/L1xx_Cat_1.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_1 ref_manual_id 0038 chip_id 0x416 // STM32_CHIPID_L1_MD -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B sram_size 0x4000 // 16 KB diff --git a/config/chips/L1xx_Cat_2.chip b/config/chips/L1xx_Cat_2.chip index 82d7dfe44..695f60d7f 100644 --- a/config/chips/L1xx_Cat_2.chip +++ b/config/chips/L1xx_Cat_2.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_2 ref_manual_id 0038 chip_id 0x429 // STM32_CHIPID_L1_CAT2 -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff8004c flash_pagesize 0x100 // 128 B sram_size 0x8000 // 32 KB diff --git a/config/chips/L1xx_Cat_3.chip b/config/chips/L1xx_Cat_3.chip index 2241e5bde..43e21f517 100644 --- a/config/chips/L1xx_Cat_3.chip +++ b/config/chips/L1xx_Cat_3.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_3 ref_manual_id 0038 chip_id 0x427 // STM32_CHIPID_L1_MD_PLUS -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B sram_size 0x8000 // 32 KB diff --git a/config/chips/L1xx_Cat_4.chip b/config/chips/L1xx_Cat_4.chip index 7933d7121..a36118937 100644 --- a/config/chips/L1xx_Cat_4.chip +++ b/config/chips/L1xx_Cat_4.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_4 ref_manual_id 0038 chip_id 0x436 // STM32_CHIPID_L1_MD_PLUS_HD -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B sram_size 0xc000 // 48 KB diff --git a/config/chips/L1xx_Cat_5.chip b/config/chips/L1xx_Cat_5.chip index 0e95e54e8..a487b22bc 100644 --- a/config/chips/L1xx_Cat_5.chip +++ b/config/chips/L1xx_Cat_5.chip @@ -3,7 +3,7 @@ dev_type STM32L1xx_Cat_5 ref_manual_id 0038 chip_id 0x437 // STM32_CHIPID_L152_RE -flash_type 8 // STM32_FLASH_TYPE_L0_L1 +flash_type L0_L1 flash_size_reg 0x1ff800cc flash_pagesize 0x100 // 128 B sram_size 0x14000 // 80 KB diff --git a/config/chips/L41x_L42x.chip b/config/chips/L41x_L42x.chip index 726645552..11e545bb7 100644 --- a/config/chips/L41x_L42x.chip +++ b/config/chips/L41x_L42x.chip @@ -3,7 +3,7 @@ dev_type STM32L41x_L42x ref_manual_id 0394 chip_id 0x464 // STM32_CHIPID_L41x_L42x -flash_type 9 // STM32_FLASH_TYPE_L4_L4P +flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index baba13e55..f0a959693 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -3,7 +3,7 @@ dev_type STM32L41x_L42x ref_manual_id 0392 chip_id 0x435 // STM32_CHIPID_L43x_L44x -flash_type 9 // STM32_FLASH_TYPE_L4_L4P +flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0xc000 // 48 KB diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index 8886633e2..267122f87 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -3,7 +3,7 @@ dev_type STM32L45x_L46x ref_manual_id 0394 chip_id 0x462 // STM32_CHIPID_L45x_L46x -flash_type 9 // STM32_FLASH_TYPE_L4_L4P +flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/L47x_L48x.chip b/config/chips/L47x_L48x.chip index df96ee2fb..421663e58 100644 --- a/config/chips/L47x_L48x.chip +++ b/config/chips/L47x_L48x.chip @@ -3,7 +3,7 @@ dev_type STM32L47x_L48x ref_manual_id 0351 chip_id 0x415 // STM32_CHIPID_L4 -flash_type 9 // STM32_FLASH_TYPE_L4_L4P +flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x18000 // 96 KB diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 0f4bd285d..df1f084ff 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -3,7 +3,7 @@ dev_type STM32L496x_L4A6x ref_manual_id 0351 chip_id 0x461 // STM32_CHIPID_L496x_L4A6x -flash_type 9 // STM32_FLASH_TYPE_L4_L4P +flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/L4Px.chip b/config/chips/L4Px.chip index 2d1a59806..39788eabe 100644 --- a/config/chips/L4Px.chip +++ b/config/chips/L4Px.chip @@ -3,7 +3,7 @@ dev_type STM32L4Px ref_manual_id 0432 chip_id 0x471 // STM32_CHIPID_L4PX -flash_type 9 // STM32_FLASH_TYPE_L4_L4P +flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0xa0000 // 640 KB diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index f0593a97e..b5c2d0d80 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -3,7 +3,7 @@ dev_type STM32L4Rx ref_manual_id 0432 chip_id 0x470 // STM32_CHIPID_L4RX -flash_type 9 // STM32_FLASH_TYPE_L4_L4P +flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0xa0000 // 640 KB diff --git a/config/chips/L5x5.chip b/config/chips/L5x5.chip.txt similarity index 85% rename from config/chips/L5x5.chip rename to config/chips/L5x5.chip.txt index 9a5b2fdbf..ce268148b 100644 --- a/config/chips/L5x5.chip +++ b/config/chips/L5x5.chip.txt @@ -3,7 +3,7 @@ dev_type STM32L5x2 ref_manual_id 0438 chip_id 0x0 // (temporary setting only!) -flash_type 10 // (temporary setting only!) +flash_type 0 // (temporary setting only!) flash_size_reg 0x0bfa07a0 flash_pagesize 0x2000 // 8 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/U5x5.chip b/config/chips/U5x5.chip.txt similarity index 85% rename from config/chips/U5x5.chip rename to config/chips/U5x5.chip.txt index 55dfdaf7d..177359cc3 100644 --- a/config/chips/U5x5.chip +++ b/config/chips/U5x5.chip.txt @@ -3,7 +3,7 @@ dev_type STM32U5x5 ref_manual_id 0456 chip_id 0x0 // (temporary setting only!) -flash_type 10 // (temporary setting only!) +flash_type 0 // (temporary setting only!) flash_size_reg 0x0bfa07a0 flash_pagesize 0x2000 // 8 KB sram_size 0xc4800 // 786 KB diff --git a/config/chips/WBx0_WBx5.chip b/config/chips/WBx0_WBx5.chip index 3d27edd6d..2747386f8 100644 --- a/config/chips/WBx0_WBx5.chip +++ b/config/chips/WBx0_WBx5.chip @@ -3,7 +3,7 @@ dev_type STM32WBx0_WBx5 ref_manual_id 0434 // also RM0471 chip_id 0x495 // STM32_CHIPID_WB55 -flash_type 11 // STM32_FLASH_TYPE_WB_WL +flash_type WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/WLx5.chip b/config/chips/WLx5.chip index 9669fe27f..5bc9d90dc 100644 --- a/config/chips/WLx5.chip +++ b/config/chips/WLx5.chip @@ -3,7 +3,7 @@ dev_type STM32WLEx ref_manual_id 0033 chip_id 0x497 // STM32_CHIPID_WLE -flash_type 11 // STM32_FLASH_TYPE_WB_WL +flash_type WB_WL flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB diff --git a/config/chips/unknown_device.chip b/config/chips/unknown_device.chip index bc50e7a00..4eb0c6cbf 100644 --- a/config/chips/unknown_device.chip +++ b/config/chips/unknown_device.chip @@ -3,7 +3,7 @@ dev_type unknown ref_manual_id 0000 chip_id 0x0 // STM32_CHIPID_UNKNOWN -flash_type 0 // STM32_FLASH_TYPE_UNKNOWN +flash_type UNKNOWN flash_size_reg 0x0 flash_pagesize 0x0 sram_size 0x0 diff --git a/inc/stm32.h b/inc/stm32.h index 56176bd6f..d6bbe506c 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -8,47 +8,39 @@ #define STM32_H /* STM32 Cortex-M core ids (CPUTAPID) */ -#define STM32_CORE_ID_M0_SWD 0x0bb11477 // (RM0091 Section 32.5.3) F0 SW-DP +enum stm32_core_id { + STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP // (RM0444 Section 40.5.3) G0 SW-DP - -#define STM32_CORE_ID_M0P_SWD 0x0bc11477 // (RM0385 Section 27.5.3) L0 SW-DP - -#define STM32_CORE_ID_M3_r1p1_SWD 0x1ba01477 // (RM0008 Section 31.8.3) F1 SW-DP -#define STM32_CORE_ID_M3_r1p1_JTAG 0x3ba00477 // (RM0008 Section 31.6.3) F1 JTAG - -#define STM32_CORE_ID_M3_r2p0_SWD 0x2ba01477 // (RM0033 Section 32.8.3) F2 SW-DP + STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0385 Section 27.5.3) L0 SW-DP + STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP + STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG + STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP // (RM0038 Section 30.8.3) L1 SW-DP -#define STM32_CORE_ID_M3_r2p0_JTAG 0x0ba00477 // (RM0033 Section 32.6.3) F2 JTAG + STM32_CORE_ID_M3_r2p0_JTAG = 0x0ba00477, // (RM0033 Section 32.6.3) F2 JTAG // (RM0038 Section 30.6.2) L1 JTAG - -#define STM32_CORE_ID_M4_r0p1_SWD 0x1ba01477 // (RM0316 Section 33.8.3) F3 SW-DP + STM32_CORE_ID_M4_r0p1_SWD = 0x1ba01477, // (RM0316 Section 33.8.3) F3 SW-DP // (RM0351 Section 48.8.3) L4 SW-DP // (RM0432 Section 57.8.3) L4+ SW-DP -#define STM32_CORE_ID_M4_r0p1_JTAG 0x4ba00477 // (RM0316 Section 33.6.3) F3 JTAG + STM32_CORE_ID_M4_r0p1_JTAG = 0x4ba00477, // (RM0316 Section 33.6.3) F3 JTAG // (RM0351 Section 48.6.3) L4 JTAG // (RM0432 Section 57.6.3) L4+ JTAG - -#define STM32_CORE_ID_M4F_r0p1_SWD 0x2ba01477 // (RM0090 Section 38.8.3) F4 SW-DP + STM32_CORE_ID_M4F_r0p1_SWD = 0x2ba01477, // (RM0090 Section 38.8.3) F4 SW-DP // (RM0090 Section 47.8.3) G4 SW-DP -#define STM32_CORE_ID_M4F_r0p1_JTAG 0x4ba00477 // (RM0090 Section 38.6.3) F4 JTAG + STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG // (RM0090 Section 47.6.3) G4 JTAG - -#define STM32_CORE_ID_M7F_SWD 0x5ba02477 // (RM0385 Section 40.8.3) F7 SW-DP -#define STM32_CORE_ID_M7F_JTAG 0x5ba00477 // (RM0385 Section 40.6.3) F7 JTAG - -#define STM32_CORE_ID_M7F_H7_SWD 0x6ba02477 // (RM0433 Section 60.4.1) H7 SW-DP -#define STM32_CORE_ID_M7F_H7_JTAG 0x6ba00477 // (RM0433 Section 60.4.1) H7 JTAG - -#define STM32_CORE_ID_M33_SWD 0x0be02477 // (RM0438 Section 52.2.10) L5 SW-DP + STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP + STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG + STM32_CORE_ID_M7F_H7_SWD = 0x6ba02477, // (RM0433 Section 60.4.1) H7 SW-DP + STM32_CORE_ID_M7F_H7_JTAG = 0x6ba00477, // (RM0433 Section 60.4.1) H7 JTAG + STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP // (RM0456 Section 65.3.3) U5 SW-DP -#define STM32_CORE_ID_M33_JTAGD 0x0be01477 // (RM0438 Section 52.2.10) L5 JTAG-DP + STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP // (RM0456 Section 65.3.3) U5 JTAG-DP -#define STM32_CORE_ID_M33_JTAG 0x0ba04477 // (RM0438 Section 52.2.8) L5 JTAG + STM32_CORE_ID_M33_JTAG = 0x0ba04477, // (RM0438 Section 52.2.8) L5 JTAG // (RM0456 Section 56.3.1) U5 JTAG +}; /* STM32 flash types */ -// New flash type definitions must go before STM32_FLASH_TYPE_UNDEFINED -// with the latter updated to the highest enum value. enum stm32_flash_type { STM32_FLASH_TYPE_UNKNOWN = 0, STM32_FLASH_TYPE_F0_F1_F3 = 1, @@ -62,7 +54,6 @@ enum stm32_flash_type { STM32_FLASH_TYPE_L4_L4P = 9, STM32_FLASH_TYPE_L5_U5 = 10, STM32_FLASH_TYPE_WB_WL = 11, - STM32_FLASH_TYPE_UNDEFINED = 12, // max. value exceeded }; /* STM32 chip-ids */ @@ -70,7 +61,7 @@ enum stm32_flash_type { // stm32 chipids, only lower 12 bits... enum stm32_chipids { - STM32_CHIPID_UNKNOWN = 0x000, + STM32_CHIPID_UNKNOWN = 0x000, STM32_CHIPID_F1_MD = 0x410, /* medium density */ STM32_CHIPID_F2 = 0x411, diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index dbfd2882d..e68f6e371 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,3 +1,4 @@ +#include #include #include "chipid.h" @@ -7,7 +8,6 @@ #include #include - static struct stlink_chipid_params *devicelist; void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { @@ -28,7 +28,6 @@ void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { struct stlink_chipid_params *params = NULL; -// struct stlink_chipid_params *p2; for (params = devicelist; params != NULL; params = params->next) if (params->chip_id == chip_id) { fprintf(stderr, "\ndetected chip_id parametres\n\n"); @@ -74,7 +73,7 @@ void process_chipfile(char *fname) { buf[strlen(p) - 1] = 0; // chomp newline sscanf(p, "%*s %n", &nc); ts->dev_type = strdup(p + nc); - } else if (strcmp (word, "ref_manual_id") == 0) { + } else if (strcmp(word, "ref_manual_id") == 0) { // ts->ref_manual_id = strdup (value); buf[strlen(p) - 1] = 0; // chomp newline sscanf(p, "%*s %n", &nc); @@ -83,59 +82,80 @@ void process_chipfile(char *fname) { if (sscanf(value, "%i", &ts->chip_id) < 1) { fprintf(stderr, "Failed to parse chip-id\n"); } - } else if (strcmp (word, "flash_type") == 0) { - if (sscanf(value, "%i", (int *)&ts->flash_type) < 1) { - fprintf(stderr, "Failed to parse flash type\n"); - } else if ((ts->flash_type < STM32_FLASH_TYPE_UNKNOWN) || (ts->flash_type >= STM32_FLASH_TYPE_UNDEFINED)) { - fprintf(stderr, "Unrecognized flash type\n"); + } else if (strcmp(word, "flash_type") == 0) { + if (strcmp(value, "F0_F1_F3") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; + } else if (strcmp(value, "F1_XL") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F1_XL; + } else if (strcmp(value, "F2_F4") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F2_F4; + } else if (strcmp(value, "F7") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F7; + } else if (strcmp(value, "G0") == 0) { + ts->flash_type = STM32_FLASH_TYPE_G0; + } else if (strcmp(value, "G4") == 0) { + ts->flash_type = STM32_FLASH_TYPE_G4; + } else if (strcmp(value, "H7") == 0) { + ts->flash_type = STM32_FLASH_TYPE_H7; + } else if (strcmp(value, "L0_L1") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L0_L1; + } else if (strcmp(value, "L4_L4P") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L4_L4P; + } else if (strcmp(value, "L5_U5") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L5_U5; + } else if (strcmp(value, "WB_WL") == 0) { + ts->flash_type = STM32_FLASH_TYPE_WB_WL; + } else { + ts->flash_type = STM32_FLASH_TYPE_UNKNOWN; + fprintf(stderr, "Failed to parse flash type or unrecognized flash type\n"); } - } else if (strcmp (word, "flash_size_reg") == 0) { + } else if (strcmp(word, "flash_size_reg") == 0) { if (sscanf(value, "%i", &ts->flash_size_reg) < 1) { fprintf(stderr, "Failed to parse flash size reg\n"); } - } else if (strcmp (word, "flash_pagesize") == 0) { + } else if (strcmp(word, "flash_pagesize") == 0) { if (sscanf(value, "%i", &ts->flash_pagesize) < 1) { fprintf(stderr, "Failed to parse flash page size\n"); } - } else if (strcmp (word, "sram_size") == 0) { + } else if (strcmp(word, "sram_size") == 0) { if (sscanf(value, "%i", &ts->sram_size) < 1) { fprintf(stderr, "Failed to parse SRAM size\n"); } - } else if (strcmp (word, "bootrom_base") == 0) { + } else if (strcmp(word, "bootrom_base") == 0) { if (sscanf(value, "%i", &ts->bootrom_base) < 1) { fprintf(stderr, "Failed to parse BootROM base\n"); } - } else if (strcmp (word, "bootrom_size") == 0) { + } else if (strcmp(word, "bootrom_size") == 0) { if (sscanf(value, "%i", &ts->bootrom_size) < 1) { fprintf(stderr, "Failed to parse BootROM size\n"); } - } else if (strcmp (word, "option_base") == 0) { + } else if (strcmp(word, "option_base") == 0) { if (sscanf(value, "%i", &ts->option_base) < 1) { fprintf(stderr, "Failed to parse option base\n"); } - } else if (strcmp (word, "option_size") == 0) { + } else if (strcmp(word, "option_size") == 0) { if (sscanf(value, "%i", &ts->option_size) < 1) { fprintf(stderr, "Failed to parse option size\n"); } - } else if (strcmp (word, "flags") == 0) { + } else if (strcmp(word, "flags") == 0) { pp = strtok (p, " \t\n"); while ((pp = strtok (NULL, " \t\n"))) { - if (strcmp (pp, "none") == 0) { + if (strcmp(pp, "none") == 0) { // NOP - } else if (strcmp (pp, "dualbank") == 0) { + } else if (strcmp(pp, "dualbank") == 0) { ts->flags |= CHIP_F_HAS_DUAL_BANK; - } else if (strcmp (pp, "swo") == 0) { + } else if (strcmp(pp, "swo") == 0) { ts->flags |= CHIP_F_HAS_SWO_TRACING; } else { - fprintf (stderr, "Unknown flags word in %s: '%s'\n", + fprintf(stderr, "Unknown flags word in %s: '%s'\n", fname, pp); } } sscanf(value, "%x", &ts->flags); } else { - fprintf (stderr, "Unknown keyword in %s: %s\n", + fprintf(stderr, "Unknown keyword in %s: %s\n", fname, word); } } @@ -156,7 +176,6 @@ void init_chipids(char *dir_to_scan) { } devicelist = NULL; - // dump_chips (); d = opendir(dir_to_scan); if (d) { From fecd2baeae8afc4c69d3dce19ab99fff5ee37bef Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Fri, 21 Jan 2022 23:26:44 +0400 Subject: [PATCH 1293/1435] Refactoring common.c Added forgotten defines --- inc/stm32.h | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/inc/stm32.h b/inc/stm32.h index 21da2f563..17b27918c 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -35,4 +35,44 @@ #define STM32_F3_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) #define STM32_G4_OPTION_BYTES_BASE ((uint32_t)0x1FFFF800) +#define STM32F0_DBGMCU_CR 0xE0042004 +#define STM32F0_DBGMCU_CR_IWDG_STOP 8 +#define STM32F0_DBGMCU_CR_WWDG_STOP 9 + +#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 +#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 +#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 + +#define STM32L0_DBGMCU_APB1_FZ 0x40015808 +#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 +#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 + +#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 +#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 + +#define STM32WB_DBGMCU_APB1FZR1 0xE004203C +#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 +#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 + +#define STM32F1_RCC_AHBENR 0x40021014 +#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32F4_RCC_AHB1ENR 0x40023830 +#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN + +#define STM32G0_RCC_AHBENR 0x40021038 +#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32G4_RCC_AHB1ENR 0x40021048 +#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32L0_RCC_AHBENR 0x40021030 +#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN + +#define STM32H7_RCC_AHB1ENR 0x58024538 +#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +#define STM32WB_RCC_AHB1ENR 0x58000048 +#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + #endif // STM32_H From da3d9e3f1e1a6d116df5830cf506f30ff56196b3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 21 Jan 2022 21:31:54 +0100 Subject: [PATCH 1294/1435] Formatting and whitespace clean-up --- src/stlink-lib/chipid.c | 1 + src/stlink-lib/chipid.h | 2 -- src/stlink-lib/flash_loader.c | 18 +++++++++--------- src/stlink-lib/flash_loader.h | 3 +-- src/stlink-lib/libusb_settings.h | 28 +++++++++++++--------------- src/stlink-lib/logging.c | 1 + src/stlink-lib/sg.c | 1 - src/stlink-lib/sg.h | 2 -- src/stlink-lib/usb.h | 2 +- src/win32/mmap.h | 2 -- src/win32/sys_time.c | 1 + src/win32/sys_time.h | 1 - src/win32/win32_socket.c | 6 ++++-- src/win32/win32_socket.h | 6 ++++-- 14 files changed, 35 insertions(+), 39 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index e68f6e371..06e8571aa 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -228,4 +228,5 @@ void init_chipids(char *dir_to_scan) { FindClose(hFind); } + #endif //defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 8efcd653e..458e7c3e2 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -4,7 +4,6 @@ #include #include - /** Chipid parametres */ struct stlink_chipid_params { char *dev_type; @@ -25,5 +24,4 @@ struct stlink_chipid_params { struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); void init_chipids(char *dir_to_scan); - #endif // STLINK_CHIPID_H_ diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 2b47c1114..94978a51f 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -7,17 +7,16 @@ #include #include "flash_loader.h" -#define FLASH_REGS_BANK2_OFS 0x40 -#define FLASH_BANK2_START_ADDR 0x08080000 +#define FLASH_REGS_BANK2_OFS 0x40 +#define FLASH_BANK2_START_ADDR 0x08080000 #define STM32F0_WDG_KR 0x40003000 #define STM32H7_WDG_KR 0x58004800 #define STM32F0_WDG_KR_KEY_RELOAD 0xAAAA -/* !!! - * !!! DO NOT MODIFY FLASH LOADERS DIRECTLY! - * !!! +/* + * !!! DO NOT MODIFY FLASH LOADERS DIRECTLY !!! * * Edit assembly files in the '/flashloaders' instead. The sizes of binary * flash loaders must be aligned by 4 (it's written by stlink_write_mem32) @@ -155,8 +154,7 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { size_t size = 0; uint32_t dfsr, cfsr, hfsr; - /* Interrupt masking. - * According to DDI0419C, Table C1-7 firstly force halt */ + /* Interrupt masking according to DDI0419C, Table C1-7 firstly force halt */ stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | STLINK_REG_DHCSR_C_HALT); @@ -354,7 +352,8 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe /* Run loader */ stlink_run(sl, RUN_FLASH_LOADER); -/* This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. +/* + * This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. * But because this usually runs on Unix-like OSes, the 10 µs get rounded up to the "tick" * (actually almost two ticks) of the system. 1 ms. Thus, the ten thousand attempts, when * "something goes wrong" that requires the error message "flash loader run error" would wait @@ -383,7 +382,8 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe // check written byte count stlink_read_reg(sl, 2, &rr); - /* The chunk size for loading is not rounded. The flash loader + /* + * The chunk size for loading is not rounded. The flash loader * subtracts the size of the written block (1-8 bytes) from * the remaining size each time. A negative value may mean that * several bytes garbage has been written due to the unaligned diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index bac99bdb4..85b92bef3 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -4,6 +4,7 @@ * This should contain all the common top level stlink interfaces, * regardless of how the backend does the work.... */ + #ifndef STLINK_FLASH_LOADER_H_ #define STLINK_FLASH_LOADER_H_ @@ -12,10 +13,8 @@ #include - int stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); - #endif // STLINK_FLASH_LOADER_H_ diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index a2dfc6d26..cc44736f9 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -4,21 +4,19 @@ #include /* - - libusb ver | LIBUSB_API_VERSION - -----------+-------------------- - v1.0.13 | 0x01000100 - v1.0.14 | 0x010000FF - v1.0.15 | 0x01000101 - v1.0.16 | 0x01000102 - v1.0.17 | 0x01000102 - v1.0.18 | 0x01000102 - v1.0.19 | 0x01000103 - v1.0.20 | 0x01000104 - v1.0.21 | 0x01000105 - v1.0.22 | 0x01000106 - v1.0.23 | 0x01000107 - + * libusb ver | LIBUSB_API_VERSION + * -----------+-------------------- + * v1.0.13 | 0x01000100 + * v1.0.14 | 0x010000FF + * v1.0.15 | 0x01000101 + * v1.0.16 | 0x01000102 + * v1.0.17 | 0x01000102 + * v1.0.18 | 0x01000102 + * v1.0.19 | 0x01000103 + * v1.0.20 | 0x01000104 + * v1.0.21 | 0x01000105 + * v1.0.22 | 0x01000106 + * v1.0.23 | 0x01000107 */ #if defined (__FreeBSD__) diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index 817f3d68e..79924fc20 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -4,6 +4,7 @@ * Slow, yet another wheel reinvented, but enough to make the rest of our code * pretty enough. */ + #include #include #include diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 18792c89f..feab40c13 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -74,7 +74,6 @@ * part to an existing options line for usb-storage). */ - #define __USE_GNU #include #include diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index 4161d3967..212d03b27 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -9,7 +9,6 @@ #include #include - /* Device access */ #define RDWR 0 #define RO 1 @@ -57,5 +56,4 @@ struct stlink_libsg { stlink_t* stlink_v1_open(const int verbose, int reset); - #endif // STLINK_SG_H diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index d04ef2dca..885e8cfc5 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -66,9 +66,9 @@ struct stlink_libusb { * @retval NULL Error while opening the stlink * @retval !NULL Stlink found and ready to use */ + stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq); size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); - #endif // STLINK_USB_H diff --git a/src/win32/mmap.h b/src/win32/mmap.h index 67558b0cc..06079a9bc 100644 --- a/src/win32/mmap.h +++ b/src/win32/mmap.h @@ -13,11 +13,9 @@ #define MAP_ANONYMOUS (1 << 5) #define MAP_FAILED ((void *)-1) - void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); int munmap(void *addr, size_t len); - #endif /* HAVE_SYS_MMAN_H */ #endif /* STLINK_MMAP_H */ diff --git a/src/win32/sys_time.c b/src/win32/sys_time.c index 08da60b85..422731b3f 100644 --- a/src/win32/sys_time.c +++ b/src/win32/sys_time.c @@ -30,4 +30,5 @@ int gettimeofday(struct timeval *tv, struct timezone *tz) { return 0; } + #endif //STLINK_HAVE_SYS_TIME_H diff --git a/src/win32/sys_time.h b/src/win32/sys_time.h index 3f35390c3..d314509b7 100644 --- a/src/win32/sys_time.h +++ b/src/win32/sys_time.h @@ -14,7 +14,6 @@ struct timezone { int gettimeofday(struct timeval *tv, struct timezone *tz); - #endif /* STLINK_HAVE_SYS_TIME_H */ #endif /* STLINK_TIME_H */ diff --git a/src/win32/win32_socket.c b/src/win32/win32_socket.c index bfdcac5ce..3f4d28bbd 100644 --- a/src/win32/win32_socket.c +++ b/src/win32/win32_socket.c @@ -123,7 +123,8 @@ static void set_socket_errno(int winsock_err) { } } -/* A wrapper around the socket() function. +/* + * A wrapper around the socket() function. * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ @@ -135,7 +136,8 @@ SOCKET win32_socket(int domain, int type, int protocol) { return(fd); } -/* A wrapper around the connect() function. +/* + * A wrapper around the connect() function. * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ diff --git a/src/win32/win32_socket.h b/src/win32/win32_socket.h index 5f8f09589..614046a6f 100644 --- a/src/win32/win32_socket.h +++ b/src/win32/win32_socket.h @@ -20,7 +20,8 @@ #pragma warning(pop) #endif -/* winsock doesn't feature poll(), so there is a version implemented in terms of select() in win32_socket.c. +/* + * winsock doesn't feature poll(), so there is a version implemented in terms of select() in win32_socket.c. * The following definitions are copied from linux man pages. * A poll() macro is defined to call the version in win32_socket.c. */ @@ -40,7 +41,8 @@ struct pollfd { #endif #define poll(x, y, z) win32_poll(x, y, z) -/* These wrappers do nothing special except set the global errno variable if an error occurs +/* + * These wrappers do nothing special except set the global errno variable if an error occurs * (winsock doesn't do this by default). * They set errno to unix-like values (i.e. WSAEWOULDBLOCK is mapped to EAGAIN), * so code outside of this file "shouldn't" have to worry about winsock specific error handling. From 3f5d9bd0f616060f284aced40fbc8153ef0c0801 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 23 Jan 2022 13:13:57 +0100 Subject: [PATCH 1295/1435] Bugfixes and minor additions - Fixed wrong chip id for F42x_F43x boards. - Added support note for STM32 clones. - Minor formatting improvements. - Updated libusb API_VERSION list. --- config/chips/F42x_F43x.chip | 2 +- doc/devices_boards.md | 4 ++-- src/st-info/info.c | 8 +++----- src/stlink-lib/libusb_settings.h | 1 + src/stlink-lib/usb.h | 1 - 5 files changed, 7 insertions(+), 9 deletions(-) diff --git a/config/chips/F42x_F43x.chip b/config/chips/F42x_F43x.chip index 4452780b3..9dc81a120 100644 --- a/config/chips/F42x_F43x.chip +++ b/config/chips/F42x_F43x.chip @@ -2,7 +2,7 @@ # dev_type STM32F42x_F43x ref_manual_id 0090 // RM0090 (Rev. 2) -chip_id 0x463 // STM32_CHIPID_F4_HD +chip_id 0x419 // STM32_CHIPID_F4_HD flash_type F2_F4 flash_size_reg 0x1fff7a22 flash_pagesize 0x4000 // 16 KB diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 63569881a..51b9a0739 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -51,7 +51,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | ------- | ------------ | ------------- | | 0x411 | STM32F2yyxx | (all devices) | -## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) +## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) [may work, but without support!] | Product-Code | Chip-ID | STLink
      Programmer | Boards | | ------------- | ------- | ---------------------- | ----------------------------------------------------------------------------------------------- | @@ -85,7 +85,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | 0x446 | _N/A_ | xD xE | | F302 | F303 | | | 0x446 | _N/A_ | - | | | | F398 | -## STM32F3 Clone / ARM Cortex M4F (Core-ID: 0x2ba01477) +## STM32F3 Clone / ARM Cortex M4F (Core-ID: 0x2ba01477) [may work, but without support!] | Product-Code | Chip-ID | STLINK
      Programmer | Boards | | ------------ | ------- | ---------------------- | ---------------------------------- | diff --git a/src/st-info/info.c b/src/st-info/info.c index 416d27f56..618046ddd 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -33,13 +33,11 @@ static void stlink_print_info(stlink_t *sl) { if (!sl) { return; } - printf(" version: "); - stlink_print_version(sl); + printf(" version: "); stlink_print_version(sl); printf(" serial: %s\n", sl->serial); - printf(" flash: %u (pagesize: %u)\n", - (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); + printf(" flash: %u (pagesize: %u)\n", (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); printf(" sram: %u\n", (uint32_t)sl->sram_size); - printf(" chipid: 0x%.4x\n", sl->chip_id); + printf(" chipid: 0x%.3x\n", sl->chip_id); params = stlink_chipid_get_params(sl->chip_id); if (params) { printf(" dev-type: %s\n", params->dev_type); } diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index cc44736f9..c7562e290 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -17,6 +17,7 @@ * v1.0.21 | 0x01000105 * v1.0.22 | 0x01000106 * v1.0.23 | 0x01000107 + * v1.0.24 | 0x01000108 */ #if defined (__FreeBSD__) diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 885e8cfc5..3f4b71e51 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -12,7 +12,6 @@ #include #include "logging.h" - #define STLINK_USB_VID_ST 0x0483 #define STLINK_USB_PID_STLINK 0x3744 #define STLINK_USB_PID_STLINK_32L 0x3748 From f6cfd1bfe3eb50b90befe03293808727c66cb8bd Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Sun, 23 Jan 2022 23:22:05 +0400 Subject: [PATCH 1296/1435] user gszy comment Comment was: removing the MAX_FILE_SIZE ifdef/define/endif, replacing the st.st_size > (off_t)SSIZE_MAX test with st.st_size > (intmax_t) SIZE_MAX, perhaps removing the sizeof(st.st_size) != sizeof(size_t) test as well. done here --- src/common.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/src/common.c b/src/common.c index 32f718c02..d562f0f00 100644 --- a/src/common.c +++ b/src/common.c @@ -27,10 +27,6 @@ #define O_BINARY 0 #endif -#ifndef MAX_FILE_SIZE -#define MAX_FILE_SIZE (1<<20) // signed long int max value -#endif - #ifdef _MSC_VER #define __attribute__(x) #endif @@ -2202,15 +2198,12 @@ static int map_file(mapped_file_t *mf, const char *path) { goto on_error; } - if (sizeof(st.st_size) != sizeof(size_t)) { - // on 32 bit systems, check if there is an overflow - if (st.st_size > (off_t)MAX_FILE_SIZE /*1 GB*/ ) { - // limit file size to 1 GB - fprintf(stderr, "mmap() file %s too big\n", path); - goto on_error; - } + if (st.st_size > (intmax_t) SIZE_MAX ) { + fprintf(stderr, "mmap() file %s too big\n", path); + goto on_error; } + mf->base = (uint8_t *)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); From d0ed1253cea96e286d02470f0c2d90d5cb352465 Mon Sep 17 00:00:00 2001 From: hydroconstructor <96923701+hydroconstructor@users.noreply.github.com> Date: Sun, 23 Jan 2022 23:28:07 +0400 Subject: [PATCH 1297/1435] Update doc/man/st-util.1 Co-authored-by: Grzegorz Szymaszek --- doc/man/st-util.1 | 1 - 1 file changed, 1 deletion(-) diff --git a/doc/man/st-util.1 b/doc/man/st-util.1 index 2f718bb2b..bb2e36f5c 100644 --- a/doc/man/st-util.1 +++ b/doc/man/st-util.1 @@ -18,7 +18,6 @@ option, the default \f[B]4242\f[R] port will be used. .PP Stlink version 2 is used by default unless the option \f[B]\[en]stlinkv1\f[R] is given. -.PP .SH OPTIONS .TP .B \-h, \-\-help From 618a03a5dfe4a91d4174dba1b2bfcdcf75ae4d7d Mon Sep 17 00:00:00 2001 From: hydroconstructor Date: Sat, 29 Jan 2022 00:36:16 +0400 Subject: [PATCH 1298/1435] common c refactor Try to resolve conflicts with chipid_cleanup branch --- CHANGELOG.md | 18 +- CMakeLists.txt | 10 +- README.md | 2 +- cmake/modules/Findlibusb.cmake | 2 +- cmake/packaging/cpack_config.cmake | 2 +- cmake/packaging/deb/control | 2 +- contributors.txt | 3 - doc/compiling.md | 4 +- doc/version_support.md | 155 +- inc/stlink.h | 8 +- inc/stm32.h | 345 +- inc/stm32flash.h | 338 ++ src/calculate.c | 74 + src/calculate.h | 15 + src/common.c | 5380 ++++------------- src/common.h | 15 + src/common_flash.c | 1375 +++++ src/common_flash.h | 27 + src/flashloader.c | 482 ++ src/map_file.c | 62 + src/map_file.h | 32 + src/option.c | 1027 ++++ src/read_write.c | 143 + src/stlink-lib/chipid.h | 5 +- src/stlink-lib/usb.c | 41 +- src/stlink-lib/usb.c.bak | 1410 +++++ src/win32/unistd/unistd.h | 2 +- src/win32/unistd/unistd.h.bak | 76 + ...1\201\320\260\320\275\320\270\320\265.txt" | 129 + stlinkv1_macos_driver/install.sh | 3 + .../Contents/Info.plist | 82 + .../Contents/MacOS/stlink_shield_10_14 | Bin 0 -> 33840 bytes .../stlink_shield_10_14.kext/Contents/PkgInfo | 1 + .../Contents/_CodeSignature/CodeResources | 115 + .../stlink_shield.xcodeproj/project.pbxproj | 50 + 35 files changed, 6671 insertions(+), 4764 deletions(-) create mode 100644 inc/stm32flash.h create mode 100644 src/calculate.c create mode 100644 src/calculate.h create mode 100644 src/common.h create mode 100644 src/common_flash.c create mode 100644 src/common_flash.h create mode 100644 src/flashloader.c create mode 100644 src/map_file.c create mode 100644 src/map_file.h create mode 100644 src/option.c create mode 100644 src/read_write.c create mode 100644 src/stlink-lib/usb.c.bak create mode 100644 src/win32/unistd/unistd.h.bak create mode 100644 "src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" create mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist create mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/MacOS/stlink_shield_10_14 create mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/PkgInfo create mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/_CodeSignature/CodeResources diff --git a/CHANGELOG.md b/CHANGELOG.md index d744ff564..06f995d21 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,14 +2,10 @@ # v1.7.1 -Release date: 2022-xx-xx +Release date: 2021-xx-xx This release drops support for some older operating systems. Check project README for details. - -Updated system requirements: -- `cmake` >= 3.10.2 -- `libusb` >= 1.0.21 -- `libgtk-dev` >= 3.22.30 +Updated system requirements: Raised minimum version for `cmake` to 3.7.2. Features: @@ -19,9 +15,6 @@ Features: - Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) - [STM32H72X/3X]: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) - Added support for STM32WLEx ([#1173](https://github.com/stlink-org/stlink/pull/1173)) -- Added support for STLINK-V3 devices with no MSD ([#1185](https://github.com/stlink-org/stlink/pull/1185)) -- Updated gdb-server.c to allow external memory access on STM32H73xx ([#1196](https://github.com/stlink-org/stlink/pull/1196), [#1197](https://github.com/stlink-org/stlink/pull/1197)) -- Erase addr size / section of the flash memory with st-flash ([#1213](https://github.com/stlink-org/stlink/pull/1213)) Updates & changes: @@ -29,12 +22,10 @@ Updates & changes: - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation ([#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) -- Dropped execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) +- Drop execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) - Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) - Removed redundant array ([#1178](https://github.com/stlink-org/stlink/pull/1178)) - Updated chip config files from the library structs ([#1181](https://github.com/stlink-org/stlink/pull/1181)) -- [doc] Corrected file path in tutorial ([#1186](https://github.com/stlink-org/stlink/pull/1186)) -- Improved chipid checks and printouts ([#1188](https://github.com/stlink-org/stlink/pull/1188)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) @@ -50,9 +41,6 @@ Fixes: - Fixed few warnings for msvc about type conversion with possible lost data ([#1179](https://github.com/stlink-org/stlink/pull/1179)) - st-flash and other utilities search for chip files in the wrong directory ([#1180](https://github.com/stlink-org/stlink/pull/1180), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) - Fixed broken build on 32 bit systems ([#985](https://github.com/stlink-org/stlink/pull/985), [#1175](https://github.com/stlink-org/stlink/pull/1175), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) -- Define 'SSIZE_MAX' if not defined ([#1183](https://github.com/stlink-org/stlink/pull/1183)) -- Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) -- Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) # v1.7.0 diff --git a/CMakeLists.txt b/CMakeLists.txt index 66bf34e3e..a3338df71 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,7 +2,7 @@ # General cmake settings ### -cmake_minimum_required(VERSION 3.10.2) +cmake_minimum_required(VERSION 3.7.2) cmake_policy(SET CMP0042 NEW) set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) @@ -110,6 +110,8 @@ add_subdirectory(inc) set(STLINK_HEADERS inc/backend.h inc/stlink.h + src/common_flash.h + src/calculate.h src/stlink-lib/commands.h src/stlink-lib/libusb_settings.h src/stlink-lib/reg.h @@ -123,7 +125,13 @@ set(STLINK_HEADERS ) set(STLINK_SOURCE + src/read_write.c src/common.c + src/option.c + src/common_flash.c + src/map_file.c + src/flashloader.c + src/calculate.c src/stlink-lib/chipid.c src/stlink-lib/flash_loader.c src/stlink-lib/logging.c diff --git a/README.md b/README.md index bc491189e..7f797a7d9 100644 --- a/README.md +++ b/README.md @@ -38,7 +38,7 @@ It supports several so called STLINK programmer boards (and clones thereof) whic - stand-alone programmer (STLINK-V3SET, STLINK-V3MINI, STLINK-V3MODS) - on-board on some STM32 Nucleo boards (STLINK-V3E) -_\*)_ *Note: Support for the STLINK/V1 on macOS is limited to 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.* +_\*)_ **Note: Support for the STLINK/V1 on macOS is limited to 10.14 - 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.** On the user level there is no difference in handling or operation between these different revisions. diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index bc04f848d..cd52026f5 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -72,7 +72,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to if (WIN32 AND NOT EXISTS "/etc/debian_version") # Skip this for Debian... # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index 587ff5fb5..acd5630fa 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -53,7 +53,7 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av set(CPACK_DEBIAN_PACKAGE_RELEASE "1") # CPACK_DEBIAN_PACKAGE_ARCHITECTURE --> Default: Output of dpkg --print-architecture - set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.10.2), libusb-1.0-0-dev (>= 1.0.21)") + set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.4.2), libusb-1.0-0-dev (>= 1.0.20)") set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Nightwalker-87 ") # CPACK_DEBIAN_PACKAGE_DESCRIPTION --> Default: CPACK_DEBIAN_PACKAGE_DESCRIPTION (as it is set) # CPACK_DEBIAN_PACKAGE_SECTION --> Default: “devel” diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index 7c8d13e47..ef51a6cea 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -1,7 +1,7 @@ Source: stlink Priority: optional Maintainer: Nightwalker-87 -Build-Depends: cmake (>= 3.10.2), dh-cmake, debhelper (>= 9), libusb-1.0-0-dev (>= 1.0.21), libgtk-3-dev (>= 3.22.30) +Build-Depends: cmake, dh-cmake, debhelper (>= 9), libusb-1.0-0-dev, libgtk-3-dev Standards-Version: 4.5.0 Rules-Requires-Root: no Section: electronics diff --git a/contributors.txt b/contributors.txt index cffef89f6..bcaa0b538 100644 --- a/contributors.txt +++ b/contributors.txt @@ -7,8 +7,6 @@ Andrea Mucignat Andrew Andrianov [necromant] Andrey Yurovsky Andy Isaacson -Andreas Sandberg [andysan] -Antoine Faure [antoinefaure] Anton [Ant-ON] Áron Radics A. Sheaff @@ -26,7 +24,6 @@ Chris Samuelson Christian Deussen [nullsub] Christophe Levantis Craig Lilley -Crest [Crest] Dan Dev Dan Hepler Daniel Campoverde [alx741] diff --git a/doc/compiling.md b/doc/compiling.md index 0931c278a..eef207f95 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -7,7 +7,7 @@ On Windows users should ensure that the following software is installed: - `git` (_optional, but recommended_) -- `cmake` +- `cmake` (3.17.0 or later) - `MinGW-w64` (7.0.0 or later) with GCC toolchain 8.1.0 ### Installation @@ -95,7 +95,7 @@ Install the following packages from your package repository: - `git` - `gcc` or `clang` or `mingw32-gcc` or `mingw64-gcc` (C-compiler; very likely gcc is already present) - `build-essential` (on Debian based distros (Debian, Ubuntu)) -- `cmake` +- `cmake` (3.4.2 or later, use the latest version available from the repository) - `rpm` (on Debian based distros (Debian, Ubuntu), needed for package build with `make package`) - `libusb-1.0` - `libusb-1.0-0-dev` (development headers for building) diff --git a/doc/version_support.md b/doc/version_support.md index d7ba5c102..2c5df7461 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,104 +1,97 @@ -_Source:_ [pkgs.org](https://pkgs.org/search) - libusb, cmake, gtk, libgtk) (as of Jan 2022) +_Source:_ pkgs.org - [libusb](https://pkgs.org/search/?q=libusb); [cmake](https://pkgs.org/search/?q=cmake); [gtk](https://pkgs.org/search/?q=gtk) (as of May 2021) ## Supported Operating Systems ### Microsoft Windows -On Windows users should ensure that cmake **3.10.2** or any later version is installed.
      -Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb`. +On Windows users should ensure that cmake 3.20.2 or any later version is installed.
      +Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb` (1.0.23 at the time of writing). - Windows 10 - Windows 8.1 ### Apple macOS -| Package Repository | libusb | cmake | gtk-3-dev | Supported macOS versions | -| ------------------ | ------ | ------ | ------------------ | ------------------------ | -| homebrew | 1.0.24 | 3.22.1 | 3.24.30
      gtk+3 | **10.10 - 12.x** | -| MacPorts | 1.0.24 | 3.22.1 | 3.24.31
      gtk3 | **10.4 - 12.x** | +| Package Repository | libusb
      version | cmake
      version | gtk-3
      version | Supported macOS versions | +| ------------------ | ------------------- | ------------------ | ------------------ | ------------------------ | +| homebrew | 1.0.24 | 3.20.2 | 3.24.29
      gtk+3 | 10.9 - 11.x | +| MacPorts | 1.0.24 | 3.20.2 | 3.24.29
      gtk3 | 10.4 - 11.x | -NOTE: In order to use a STLINK/V1 programmer on macOS, version 10.15 is required. +NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 are required. ### Linux-/Unix-based: -| Operating System | libusb | cmake | libgtk-dev | Notes | -| ------------------------- | ------------------------------ | ---------- | ----------- | ------------------------ | -| Debian Sid | 1.0.24 | 3.22.1 | 3.24.31 | | -| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | -| Debian 10 (Buster) | 1.0.**22** | **3.13.4** | 3.24.**5** | | -| | | | | | -| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | -| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | **3.10.2** | 3.**22.30** | End of Support: Apr 2023 | -| | | | | | -| Fedora Rawhide [x64] | 1.0.24 | 3.22.3 | 3.24.31 | | -| Fedora 35 [x64] | 1.0.24 | 3.21.3 | 3.24.30 | | -| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | -| | | | | | -| openSUSE Tumbleweed [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | -| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | End of Support: Dec 2022 | -| | | | | | -| Alpine 3.15 | 1.0.24 | 3.21.3 | 3.24.30 | | -| Alpine 3.14 | 1.0.24 | 3.20.3 | 3.24.28 | | -| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | -| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | -| | | | | | -| FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | -| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | -| | | | | | -| NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | -| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| | | | | | -| CentOS 9 Stream [x64] | 1.0.24 (`libusbx`) | 3.20.3 | 3.24.30 | | -| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | -| | | | | | -| ALT Linux Sisyphus | 1.0.24 | 3.22.1 | 3.24.31 | | -| ALT Linux P10 | 1.0.24 | 3.20.5 | 3.24.31 | | -| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.29 | | -| | | | | | -| OpenMandriva Rolling | 1.0.24 | 3.22.1 | 3.24.31 | | -| OpenMandriva Cooker | 1.0.24 | 3.22.1 | 3.24.31 | | -| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | -| | | | | | -| Arch Linux | 1.0.24 | 3.22.1 | - | | -| KaOS [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | -| Mageia Cauldron | 1.0.24 | 3.22.1 | 3.24.31 | | -| PCLinuxOS [x64] | ? | 3.22.1 | 3.24.31 | | -| Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | -| Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | -| Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | -| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | -| Rocky Linux 8 [x64] | 1.0.23 | 3.20.2 | 3.**22.30** | | -| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | -| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | +| Operating System | libusb | cmake | gtk-3 | Notes | +| ------------------------- | -------------------------------- | --------- | ----------- | ------------------------ | +| Debian Sid | 1.0.24 | 3.18.4 | 3.24.24 | | +| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | +| Debian 10 (Buster) | 1.0.**22** | 3.13.4 | 3.24.**5** | | +| Debian 9 (Stretch) | 1.0.**21** | **3.7.2** | **3.22.11** | End of Support: Jun 2022 | +| | | | | | +| Ubuntu 21.04 (Hirsute) | 1.0.24 | 3.18.4 | 3.24.25 | End of Support: Jan 2022 | +| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | +| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.10.2 | **3.22.30** | End of Support: Apr 2023 | +| | | | | | +| Fedora Rawhide [x64] | 1.0.24 (`libusbx`) | 3.20.2 | 3.24.29 | | +| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | +| Fedora 33 [x64] | 1.0.23 (`libusbx`) | 3.18.3 | 3.24.23 | | +| | | | | | +| openSUSE Tumbleweed [x64] | 1.0.24 | 3.20.1 | 3.24.29 | | +| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | | +| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.17.0 | 3.24.**14** | End of Support: Dec 2021 | +| | | | | | +| Alpine 3.14 | 1.0.24 | 3.20.3 | 4.2.1 | | +| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | +| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | +| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.**13** | End of Support: Nov 2021 | +| | | | | | +| FreeBSD 13.x | 1.0.**16 - 18** (API 0x01000102) | 3.20.2 | 3.24.27 | | +| FreeBSD 12.x | 1.0.**16 - 18** (API 0x01000102) | 3.19.6 | 3.24.27 | | +| FreeBSD 11.x | 1.0.**16 - 18** (API 0x01000102) | 3.15.5 | 3.24.27 | End of Support: Sep 2021 | +| | | | | | +| Arch Linux | 1.0.24 | 3.20.2 | 3.24.29 | | +| KaOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| Mageia Cauldron | 1.0.24 | 3.20.2 | 3.24.29 | | +| OpenMandriva Cooker | 1.0.24 | 3.20.2 | 3.24.29 | | +| PCLinuxOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| Slackware Current | 1.0.24 | 3.20.2 | 3.24.28 | | +| Solus [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | +| ALT Linux Sisyphus | 1.0.24 | 3.19.7 | 3.24.29 | | +| NetBSD 9.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | +| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | +| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.18.2 | **3.22.30** | | +| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | +| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.**11** | | +| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.11.4 | 3.24.32 | | +| CentOS 8 [x64] | 1.0.23 (`libusbx`) | 3.11.4 | **3.22.30** | End of Support: Dec 2021 | ## Unsupported Operating Systems (as of Release v1.7.1) Systems with highlighted versions remain compatible with this toolset. -| Operating System | libusb | cmake | End of
      OS-Support | -| ------------------------ | ------------------------------ | ---------- | ---------------------- | -| CentOS 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | -| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | -| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | -| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | -| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | -| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | -| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | -| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | -| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | -| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | -| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | -| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | -| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | -| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | -| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | -| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | -| Debian 9 (Stretch) | 1.0.**21** | 3.7.2 | Jun 2022 | -| Slackware 14.2 | 1.0.20 | 3.5.2 | | -| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | -| CentOS 7 [x64] | 1.0.**21** (`libusbx`) | 2.8.12.2 | Jun 2024 | -| Slackware 14.1 | 1.0.9 | 2.8.12 | | -| Slackware 14.0 | 1.0.9 | 2.8.8 | | +| Operating System | libusb | cmake | End of
      OS-Support | +| ------------------------- | ---------------------- | ---------- | ---------------------- | +| Fedora 32 [x64] | **1.0.23** (`libusbx`) | **3.17.0** | May 2021 | +| Ubuntu 20.10 (Groovy) | **1.0.23** | **3.16.3** | Jul 2021 | +| NetBSD 7.x | **1.0.22** | **3.16.1** | Jun 2020 | +| Alpine 3.10 | **1.0.22** | **3.14.5** | May 2021 | +| Fedora 31 [x64] | **1.0.22** (`libusbx`) | **3.14.5** | Nov 2020 | +| Mageia 7.1 | **1.0.22** | **3.14.3** | Jun 2021 | +| Fedora 30 | **1.0.22** (`libusbx`) | **3.14.2** | May 2020 | +| Ubuntu 19.10 (Eoan) | **1.0.23** | **3.13.4** | Jul 2020 | +| Alpine 3.9 | **1.0.22** | **3.13.0** | Jan 2021 | +| openSUSE Leap 15.1 [x64] | **1.0.21** | **3.10.2** | Jan 2021 | +| Slackware 14.2 | 1.0.20 | 3.5.2 | | +| Ubuntu 16.04 LTS (Xenial) | 1.0.20 | 3.5.1 | Apr 2021 | +| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | +| Debian 8 (Jessie) | 1.0.19 | 3.0.2 | Jun 2020 | +| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | +| Ubuntu 14.04 LTS (Trusty) | 1.0.17 | 2.8.12.2 | Apr 2019 | +| CentOS 6 | 1.0.9 (`libusbx`) | 2.8.12.2 | Nov 2020 | +| Slackware 14.1 | 1.0.9 | 2.8.12 | | +| Slackware 14.0 | 1.0.9 | 2.8.8 | | _All other operating systems which are not listed are unsupported._ diff --git a/inc/stlink.h b/inc/stlink.h index 2d0fa5007..e3fd632f2 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -1,6 +1,5 @@ /* * File: stlink.h - * * This should contain all the common top level stlink interfaces, * regardless of how the backend does the work.... */ @@ -13,6 +12,7 @@ #include #include "stm32.h" +#include "stm32flash.h" #ifdef __cplusplus extern "C" { @@ -183,7 +183,7 @@ enum run_type { typedef struct _stlink stlink_t; -#include +#include // Is it really need? #include struct _stlink { @@ -274,7 +274,7 @@ int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_ int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); -int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); +//int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); @@ -282,7 +282,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); uint16_t read_uint16(const unsigned char *c, const int pt); -void stlink_core_stat(stlink_t *sl); +//void stlink_core_stat(stlink_t *sl); void stlink_print_data(stlink_t *sl); unsigned int is_bigendian(void); uint32_t read_uint32(const unsigned char *c, const int pt); diff --git a/inc/stm32.h b/inc/stm32.h index d6bbe506c..19ba3fca0 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -149,345 +149,11 @@ enum stm32_chipids { /* ============ */ /* Constant STM32 memory address */ -#define STM32_SRAM_BASE ((uint32_t)0x20000000) -#define STM32_FLASH_BASE ((uint32_t)0x08000000) +#define STM32_SRAM_BASE ((uint32_t)0x20000000) +#define STM32_FLASH_BASE ((uint32_t)0x08000000) -#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) -#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) - -/* stm32f FPEC flash controller interface, pm0063 manual */ -// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) -#define FLASH_REGS_ADDR 0x40022000 -#define FLASH_REGS_SIZE 0x28 - -#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) -#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) -#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) -#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) -#define FLASH_CR (FLASH_REGS_ADDR + 0x10) -#define FLASH_AR (FLASH_REGS_ADDR + 0x14) -#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) -#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) - -// STM32F10x_XL has two flash memory banks with separate registers to control -// the second bank. -#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) -#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) -#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) -#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) - -// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... -#define FLASH_RDPTR_KEY 0x00a5 -#define FLASH_KEY1 0x45670123 -#define FLASH_KEY2 0xcdef89ab - -#define FLASH_L0_PRGKEY1 0x8c9daebf -#define FLASH_L0_PRGKEY2 0x13141516 - -#define FLASH_L0_PEKEY1 0x89abcdef -#define FLASH_L0_PEKEY2 0x02030405 - -#define FLASH_OPTKEY1 0x08192A3B -#define FLASH_OPTKEY2 0x4C5D6E7F - -#define FLASH_F0_OPTKEY1 0x45670123 -#define FLASH_F0_OPTKEY2 0xCDEF89AB - -#define FLASH_L0_OPTKEY1 0xFBEAD9C8 -#define FLASH_L0_OPTKEY2 0x24252627 - -#define FLASH_SR_BSY 0 -#define FLASH_SR_PG_ERR 2 -#define FLASH_SR_WRPRT_ERR 4 -#define FLASH_SR_EOP 5 - -#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) - -#define FLASH_CR_PG 0 -#define FLASH_CR_PER 1 -#define FLASH_CR_MER 2 -#define FLASH_CR_OPTPG 4 -#define FLASH_CR_OPTER 5 -#define FLASH_CR_STRT 6 -#define FLASH_CR_LOCK 7 -#define FLASH_CR_OPTWRE 9 -#define FLASH_CR_OBL_LAUNCH 13 - -#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) -#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) -#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) -#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) -#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) -#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) -#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) -#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) -#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) -#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) -#define FLASH_L1_FPRG 10 -#define FLASH_L1_PROG 3 - -// Flash registers common to STM32G0 and STM32G4 series. -#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) -#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) -#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) -#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) -#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) -#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) -#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) - -// G0 (RM0444 Table 1, sec 3.7) -// Mostly the same as G4 chips, but the notation -// varies a bit after the 'OPTR' register. -#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) -#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) -#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) -#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) -#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) -#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) -#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) - -// G4 (RM0440 Table 17, sec 3.7.19) -// Mostly the same as STM32G0 chips, but there are a few extra -// registers because 'cat 3' devices can have two Flash banks. -#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) -#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) -#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) -#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) -#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) -#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) -#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) -#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) -#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) -#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) -#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) - -// G0/G4 FLASH control register -#define STM32Gx_FLASH_CR_PG (0) /* Program */ -#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ -#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ -#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ -#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define STM32Gx_FLASH_CR_STRT (16) /* Start */ -#define STM32Gx_FLASH_CR_OPTSTRT \ - (17) /* Start of modification of option bytes */ -#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ -#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ -#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ -#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ -#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ - -// G0/G4 FLASH status register -#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) -#define STM32Gx_FLASH_SR_PROGERR (3) -#define STM32Gx_FLASH_SR_WRPERR (4) -#define STM32Gx_FLASH_SR_PGAERR (5) -#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ - -// G4 FLASH option register -#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ - -// WB (RM0434) -#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) -#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) -#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) -#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) -#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) -#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) -#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) -#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) -#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) -#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) -#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) - -// WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ -// WB Flash status register. -#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ -#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ -#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ -#define STM32WB_FLASH_SR_BSY (16) /* Busy */ - -// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) -#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) -#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) -#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) -#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) -#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) - -#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ -#define STM32L4_FLASH_SR_PROGERR 3 -#define STM32L4_FLASH_SR_WRPERR 4 -#define STM32L4_FLASH_SR_PGAERR 5 -#define STM32L4_FLASH_SR_BSY 16 - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ -#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ -// Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ - (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) -// Page is fully specified by BKER and PNB -#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) - -#define STM32L4_FLASH_OPTR_DUALBANK 21 - -// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf -#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) - -#define STM32L0_FLASH_PELOCK (0) -#define STM32L0_FLASH_OPTLOCK (2) -#define STM32L0_FLASH_OBL_LAUNCH (18) - -#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 -#define STM32L0_FLASH_SR_WRPERR 8 -#define STM32L0_FLASH_SR_PGAERR 9 -#define STM32L0_FLASH_SR_NOTZEROERR 16 - -#define FLASH_ACR_OFF ((uint32_t)0x00) -#define FLASH_PECR_OFF ((uint32_t)0x04) -#define FLASH_PDKEYR_OFF ((uint32_t)0x08) -#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) -#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) -#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) -#define FLASH_SR_OFF ((uint32_t)0x18) -#define FLASH_OBR_OFF ((uint32_t)0x1c) -#define FLASH_WRPR_OFF ((uint32_t)0x20) - -// STM32F7 -#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) -#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) -#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) -#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) -#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) -#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) -#define FLASH_F7_OPTCR_LOCK 0 -#define FLASH_F7_OPTCR_START 1 -#define FLASH_F7_CR_STRT 16 -#define FLASH_F7_CR_LOCK 31 -#define FLASH_F7_CR_SER 1 -#define FLASH_F7_CR_SNB 3 -#define FLASH_F7_CR_SNB_MASK 0xf8 -#define FLASH_F7_SR_BSY 16 -#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ -#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ -#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ -#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ -#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ -#define FLASH_F7_SR_EOP 0 /* End of operation */ -#define FLASH_F7_OPTCR1_BOOT_ADD0 0 -#define FLASH_F7_OPTCR1_BOOT_ADD1 16 - -#define FLASH_F7_SR_ERROR_MASK \ - ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ - (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ - (1 << FLASH_F7_SR_OP_ERR)) - -// STM32F4 -#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) -#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) -#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) -#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) -#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) -#define FLASH_F4_OPTCR_LOCK 0 -#define FLASH_F4_OPTCR_START 1 -#define FLASH_F4_CR_STRT 16 -#define FLASH_F4_CR_LOCK 31 -#define FLASH_F4_CR_SER 1 -#define FLASH_F4_CR_SNB 3 -#define FLASH_F4_CR_SNB_MASK 0xf8 -#define FLASH_F4_SR_ERROR_MASK 0x000000F0 -#define FLASH_F4_SR_PGAERR 5 -#define FLASH_F4_SR_WRPERR 4 -#define FLASH_F4_SR_BSY 16 - -// STM32F2 -#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) -#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) -#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) -#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) -#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) -#define FLASH_F2_OPT_LOCK_BIT (1u << 0) -#define FLASH_F2_CR_STRT 16 -#define FLASH_F2_CR_LOCK 31 - -#define FLASH_F2_CR_SER 1 -#define FLASH_F2_CR_SNB 3 -#define FLASH_F2_CR_SNB_MASK 0x78 -#define FLASH_F2_SR_BSY 16 - -// STM32H7xx -#define FLASH_H7_CR_LOCK 0 -#define FLASH_H7_CR_PG 1 -#define FLASH_H7_CR_SER 2 -#define FLASH_H7_CR_BER 3 -#define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7) -#define FLASH_H7_CR_SNB 8 -#define FLASH_H7_CR_SNB_MASK 0x700 - -#define FLASH_H7_SR_QW 2 -#define FLASH_H7_SR_WRPERR 17 -#define FLASH_H7_SR_PGSERR 18 -#define FLASH_H7_SR_STRBERR 19 -#define FLASH_H7_SR_ERROR_MASK \ - ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ - (1 << FLASH_H7_SR_WRPERR)) - -#define FLASH_H7_OPTCR_OPTLOCK 0 -#define FLASH_H7_OPTCR_OPTSTART 1 -#define FLASH_H7_OPTCR_MER 4 - -#define FLASH_H7_OPTSR_OPT_BUSY 0 -#define FLASH_H7_OPTSR_OPTCHANGEERR 30 - -#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 - -#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) -#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) -#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) -#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) -#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) -#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) -#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) -#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) -#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) -#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) -#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) -#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) -#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) -#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) -#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) +#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) +#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) #define STM32F0_DBGMCU_CR 0xE0042004 #define STM32F0_DBGMCU_CR_IWDG_STOP 8 @@ -529,7 +195,4 @@ enum stm32_chipids { #define STM32WB_RCC_AHB1ENR 0x58000048 #define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN -#define L1_WRITE_BLOCK_SIZE 0x80 -#define L0_WRITE_BLOCK_SIZE 0x40 - #endif // STM32_H diff --git a/inc/stm32flash.h b/inc/stm32flash.h new file mode 100644 index 000000000..c28d67c28 --- /dev/null +++ b/inc/stm32flash.h @@ -0,0 +1,338 @@ +#ifndef STM32FLASH_H +#define STM32FLASH_H + +/* stm32f FPEC flash controller interface, pm0063 manual */ +// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) +#define FLASH_REGS_ADDR 0x40022000 +#define FLASH_REGS_SIZE 0x28 + +#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) +#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) +#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) +#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) +#define FLASH_CR (FLASH_REGS_ADDR + 0x10) +#define FLASH_AR (FLASH_REGS_ADDR + 0x14) +#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) +#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) + +// STM32F10x_XL has two flash memory banks with separate registers to control +// the second bank. +#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) +#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) +#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) +#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) + +// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... +#define FLASH_RDPTR_KEY 0x00a5 +#define FLASH_KEY1 0x45670123 +#define FLASH_KEY2 0xcdef89ab + +#define FLASH_L0_PRGKEY1 0x8c9daebf +#define FLASH_L0_PRGKEY2 0x13141516 + +#define FLASH_L0_PEKEY1 0x89abcdef +#define FLASH_L0_PEKEY2 0x02030405 + +#define FLASH_OPTKEY1 0x08192A3B +#define FLASH_OPTKEY2 0x4C5D6E7F + +#define FLASH_F0_OPTKEY1 0x45670123 +#define FLASH_F0_OPTKEY2 0xCDEF89AB + +#define FLASH_L0_OPTKEY1 0xFBEAD9C8 +#define FLASH_L0_OPTKEY2 0x24252627 + +#define FLASH_SR_BSY 0 +#define FLASH_SR_PG_ERR 2 +#define FLASH_SR_WRPRT_ERR 4 +#define FLASH_SR_EOP 5 + +#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) + +#define FLASH_CR_PG 0 +#define FLASH_CR_PER 1 +#define FLASH_CR_MER 2 +#define FLASH_CR_OPTPG 4 +#define FLASH_CR_OPTER 5 +#define FLASH_CR_STRT 6 +#define FLASH_CR_LOCK 7 +#define FLASH_CR_OPTWRE 9 +#define FLASH_CR_OBL_LAUNCH 13 + +#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) +#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) +#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) +#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) +#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) +#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) +#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) +#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) +#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) +#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) +#define FLASH_L1_FPRG 10 +#define FLASH_L1_PROG 3 + +// Flash registers common to STM32G0 and STM32G4 series. +#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) +#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) +#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) +#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) +#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) +#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) +#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) + +// G0 (RM0444 Table 1, sec 3.7) +// Mostly the same as G4 chips, but the notation +// varies a bit after the 'OPTR' register. +#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) +#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) +#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) +#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) +#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) +#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) +#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) +#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) + +// G4 (RM0440 Table 17, sec 3.7.19) +// Mostly the same as STM32G0 chips, but there are a few extra +// registers because 'cat 3' devices can have two Flash banks. +#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) +#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) +#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) +#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) +#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) +#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) +#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) +#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) +#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) +#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) +#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) +#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) + +// G0/G4 FLASH control register +#define STM32Gx_FLASH_CR_PG (0) /* Program */ +#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ +#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ +#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ +#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ +#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ +#define STM32Gx_FLASH_CR_STRT (16) /* Start */ +#define STM32Gx_FLASH_CR_OPTSTRT \ + (17) /* Start of modification of option bytes */ +#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ +#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ +#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ +#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ +#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ + +// G0/G4 FLASH status register +#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) +#define STM32Gx_FLASH_SR_PROGERR (3) +#define STM32Gx_FLASH_SR_WRPERR (4) +#define STM32Gx_FLASH_SR_PGAERR (5) +#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ +#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ + +// G4 FLASH option register +#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ + +// WB (RM0434) +#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) +#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) +#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) +#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) +#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) +#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) +#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) +#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) +#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) +#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) +#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) +#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) +#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) +#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) +#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) +#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) +#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) +#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) +#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) +#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) + +// WB Flash control register. +#define STM32WB_FLASH_CR_STRT (16) /* Start */ +#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ +#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ +// WB Flash status register. +#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ +#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ +#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ +#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ +#define STM32WB_FLASH_SR_BSY (16) /* Busy */ + +// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) +#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) +#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) +#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) +#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) +#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) + +#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ +#define STM32L4_FLASH_SR_PROGERR 3 +#define STM32L4_FLASH_SR_WRPERR 4 +#define STM32L4_FLASH_SR_PGAERR 5 +#define STM32L4_FLASH_SR_BSY 16 + +#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ +#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ +#define STM32L4_FLASH_CR_PG 0 /* Program */ +#define STM32L4_FLASH_CR_PER 1 /* Page erase */ +#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ +#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ +#define STM32L4_FLASH_CR_STRT 16 /* Start command */ +#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ +#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ +#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ +#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ +// Bits requesting flash operations (useful when we want to clear them) +#define STM32L4_FLASH_CR_OPBITS \ + (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ + (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) +// Page is fully specified by BKER and PNB +#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) + +#define STM32L4_FLASH_OPTR_DUALBANK 21 + +// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf +#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) + +#define STM32L0_FLASH_PELOCK (0) +#define STM32L0_FLASH_OPTLOCK (2) +#define STM32L0_FLASH_OBL_LAUNCH (18) + +#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 +#define STM32L0_FLASH_SR_WRPERR 8 +#define STM32L0_FLASH_SR_PGAERR 9 +#define STM32L0_FLASH_SR_NOTZEROERR 16 + +#define FLASH_ACR_OFF ((uint32_t)0x00) +#define FLASH_PECR_OFF ((uint32_t)0x04) +#define FLASH_PDKEYR_OFF ((uint32_t)0x08) +#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) +#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) +#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) +#define FLASH_SR_OFF ((uint32_t)0x18) +#define FLASH_OBR_OFF ((uint32_t)0x1c) +#define FLASH_WRPR_OFF ((uint32_t)0x20) + +// STM32F7 +#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) +#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) +#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) +#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) +#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) +#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) +#define FLASH_F7_OPTCR_LOCK 0 +#define FLASH_F7_OPTCR_START 1 +#define FLASH_F7_CR_STRT 16 +#define FLASH_F7_CR_LOCK 31 +#define FLASH_F7_CR_SER 1 +#define FLASH_F7_CR_SNB 3 +#define FLASH_F7_CR_SNB_MASK 0xf8 +#define FLASH_F7_SR_BSY 16 +#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ +#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ +#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ +#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ +#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ +#define FLASH_F7_SR_EOP 0 /* End of operation */ +#define FLASH_F7_OPTCR1_BOOT_ADD0 0 +#define FLASH_F7_OPTCR1_BOOT_ADD1 16 + +#define FLASH_F7_SR_ERROR_MASK \ + ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ + (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ + (1 << FLASH_F7_SR_OP_ERR)) + +// STM32F4 +#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) +#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) +#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) +#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) +#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) +#define FLASH_F4_OPTCR_LOCK 0 +#define FLASH_F4_OPTCR_START 1 +#define FLASH_F4_CR_STRT 16 +#define FLASH_F4_CR_LOCK 31 +#define FLASH_F4_CR_SER 1 +#define FLASH_F4_CR_SNB 3 +#define FLASH_F4_CR_SNB_MASK 0xf8 +#define FLASH_F4_SR_ERROR_MASK 0x000000F0 +#define FLASH_F4_SR_PGAERR 5 +#define FLASH_F4_SR_WRPERR 4 +#define FLASH_F4_SR_BSY 16 + +// STM32F2 +#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) +#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) +#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) +#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) +#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) +#define FLASH_F2_OPT_LOCK_BIT (1u << 0) +#define FLASH_F2_CR_STRT 16 +#define FLASH_F2_CR_LOCK 31 + +#define FLASH_F2_CR_SER 1 +#define FLASH_F2_CR_SNB 3 +#define FLASH_F2_CR_SNB_MASK 0x78 +#define FLASH_F2_SR_BSY 16 + +// STM32H7xx +#define FLASH_H7_CR_LOCK 0 +#define FLASH_H7_CR_PG 1 +#define FLASH_H7_CR_SER 2 +#define FLASH_H7_CR_BER 3 +#define FLASH_H7_CR_PSIZE 4 +#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7) +#define FLASH_H7_CR_SNB 8 +#define FLASH_H7_CR_SNB_MASK 0x700 + +#define FLASH_H7_SR_QW 2 +#define FLASH_H7_SR_WRPERR 17 +#define FLASH_H7_SR_PGSERR 18 +#define FLASH_H7_SR_STRBERR 19 +#define FLASH_H7_SR_ERROR_MASK \ + ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ + (1 << FLASH_H7_SR_WRPERR)) + +#define FLASH_H7_OPTCR_OPTLOCK 0 +#define FLASH_H7_OPTCR_OPTSTART 1 +#define FLASH_H7_OPTCR_MER 4 + +#define FLASH_H7_OPTSR_OPT_BUSY 0 +#define FLASH_H7_OPTSR_OPTCHANGEERR 30 + +#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 + +#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) +#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) +#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) +#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) +#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) +#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) +#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) +#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) +#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) +#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) +#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) +#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) +#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) +#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) + +#endif // STM32FLASH_H diff --git a/src/calculate.c b/src/calculate.c new file mode 100644 index 000000000..ed3b65873 --- /dev/null +++ b/src/calculate.c @@ -0,0 +1,74 @@ +#include +#include "calculate.h" +#include "common_flash.h" + +uint32_t calculate_F4_sectornum(uint32_t flashaddr) { + uint32_t offset = 0; + flashaddr &= ~STM32_FLASH_BASE; // page now holding the actual flash address + + if (flashaddr >= 0x100000) { + offset = 12; + flashaddr -= 0x100000; + } + + if (flashaddr < 0x4000) { + return (offset + 0); + } else if (flashaddr < 0x8000) { + return (offset + 1); + } else if (flashaddr < 0xc000) { + return (offset + 2); + } else if (flashaddr < 0x10000) { + return (offset + 3); + } else if (flashaddr < 0x20000) { + return (offset + 4); + } else { + return (offset + (flashaddr / 0x20000) + 4); + } +} + +uint32_t calculate_F7_sectornum(uint32_t flashaddr) { + flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address + + if (flashaddr < 0x20000) { + return (flashaddr / 0x8000); + } else if (flashaddr < 0x40000) { + return (4); + } else { + return ((flashaddr / 0x40000) + 4); + } +} + +uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, + unsigned bank) { + flashaddr &= + ~((bank == BANK_1) + ? STM32_FLASH_BASE + : STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address + return (flashaddr / sl->flash_pgsz); +} + +// returns BKER:PNB for the given page address +uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { + uint32_t bker = 0; + uint32_t flashopt; + stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); + flashaddr -= STM32_FLASH_BASE; + + if (sl->chip_id == STM32_CHIPID_L4 || + sl->chip_id == STM32_CHIPID_L496x_L4A6x || + sl->chip_id == STM32_CHIPID_L4Rx) { + // this chip use dual banked flash + if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { + uint32_t banksize = (uint32_t)sl->flash_size / 2; + + if (flashaddr >= banksize) { + flashaddr -= banksize; + bker = 0x100; + } + } + } + + // For 1MB chips without the dual-bank option set, the page address will + // overflow into the BKER bit, which gives us the correct bank:page value. + return (bker | flashaddr / (uint32_t)sl->flash_pgsz); +} diff --git a/src/calculate.h b/src/calculate.h new file mode 100644 index 000000000..68c1fb988 --- /dev/null +++ b/src/calculate.h @@ -0,0 +1,15 @@ +/* + * File: calculate.h + * + * TODO: add a description + */ + +#ifndef CALCULATE_H +#define CALCULATE_H + +uint32_t calculate_F4_sectornum(uint32_t); +uint32_t calculate_F7_sectornum(uint32_t); +uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, unsigned); +uint32_t calculate_L4_page(stlink_t *, uint32_t); + +#endif // CALCULATE_H diff --git a/src/common.c b/src/common.c index 266722b91..97f41a533 100644 --- a/src/common.c +++ b/src/common.c @@ -1,4576 +1,1406 @@ -#define DEBUG_FLASH 0 -#include -#include -#include -#include -#include - -#include +#include #include -#include #include #include #include - -#include -#include +#include #include -#include #include - -#ifdef STLINK_HAVE_SYS_MMAN_H -#include -#else -#include -#endif - -#ifndef O_BINARY -#define O_BINARY 0 -#endif +#include +#include +#include +#include "common_flash.h" +#include "calculate.h" +#include "map_file.h" +#include "common.h" #ifdef _MSC_VER #define __attribute__(x) #endif -#define BANK_1 0 -#define BANK_2 1 +// Private structs and functions defines +struct stlink_fread_worker_arg { + int fd; +}; +struct stlink_fread_ihex_worker_arg { + FILE *file; + uint32_t addr; + uint32_t lba; + uint8_t buf[16]; + uint8_t buf_pos; +}; +typedef bool (*save_block_fn)(void *arg, uint8_t *block, ssize_t len); -// Endianness -// https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html -// These functions encode and decode little endian uint16 and uint32 values. +static void stop_wdg_in_debug(stlink_t *); +int stlink_jtag_reset(stlink_t *, int); +int stlink_soft_reset(stlink_t *, int); +void _parse_version(stlink_t *, stlink_version_t *); +static uint8_t stlink_parse_hex(const char *); +static int stlink_read(stlink_t *, stm32_addr_t, size_t, save_block_fn, void *); +static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *, int, stm32_addr_t); +static bool stlink_fread_ihex_worker(void *, uint8_t *, ssize_t); +static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *); +static bool stlink_fread_worker(void *, uint8_t *, ssize_t); +// End of private structs and functions defines + +// Functions below are defined in stlink.h (see line num before function) +// 252 +void stlink_close(stlink_t *sl) { + DLOG("*** stlink_close ***\n"); -void write_uint32(unsigned char *buf, uint32_t ui) { - buf[0] = ui; - buf[1] = ui >> 8; - buf[2] = ui >> 16; - buf[3] = ui >> 24; -} + if (!sl) { + return; + } -void write_uint16(unsigned char *buf, uint16_t ui) { - buf[0] = (uint8_t)ui; - buf[1] = (uint8_t)(ui >> 8); + sl->backend->close(sl); + free(sl); } +// 250 +int stlink_exit_debug_mode(stlink_t *sl) { + DLOG("*** stlink_exit_debug_mode ***\n"); -uint32_t read_uint32(const unsigned char *c, const int pt) { - return ((uint32_t)c[pt]) | ((uint32_t)c[pt + 1] << 8) | - ((uint32_t)c[pt + 2] << 16) | ((uint32_t)c[pt + 3] << 24); -} + if (sl->flash_type != STM32_FLASH_TYPE_UNKNOWN && + sl->core_stat != TARGET_RESET) { + // stop debugging if the target has been identified + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); + } -uint16_t read_uint16(const unsigned char *c, const int pt) { - return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); + return (sl->backend->exit_debug_mode(sl)); } - -static uint32_t get_stm32l0_flash_base(stlink_t *sl) { - switch (sl->chip_id) { - case STM32_CHIPID_L0: - case STM32_CHIPID_L0_CAT5: - case STM32_CHIPID_L0_CAT2: - case STM32_CHIPID_L011: - return (STM32L0_FLASH_REGS_ADDR); - - case STM32_CHIPID_L1_CAT2: - case STM32_CHIPID_L1_MD: - case STM32_CHIPID_L1_MD_PLUS: - case STM32_CHIPID_L1_MD_PLUS_HD: - return (STM32L_FLASH_REGS_ADDR); - - default: - WLOG("Flash base use default L0 address\n"); - return (STM32L0_FLASH_REGS_ADDR); +//248 +int stlink_enter_swd_mode(stlink_t *sl) { + DLOG("*** stlink_enter_swd_mode ***\n"); + return (sl->backend->enter_swd_mode(sl)); +} +// 271 +// Force the core into the debug mode -> halted state. +int stlink_force_debug(stlink_t *sl) { + DLOG("*** stlink_force_debug_mode ***\n"); + int res = sl->backend->force_debug(sl); + if (res) { + return (res); } + // Stop the watchdogs in the halted state for suppress target reboot + stop_wdg_in_debug(sl); + return (0); } - -static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { - uint32_t rdp; - stlink_read_debug32(sl, FLASH_WRPR, &rdp); - return (rdp & 0xff); +// 251 +int stlink_exit_dfu_mode(stlink_t *sl) { + DLOG("*** stlink_exit_dfu_mode ***\n"); + return (sl->backend->exit_dfu_mode(sl)); } +// 253 +int stlink_core_id(stlink_t *sl) { + int ret; -static inline uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { - uint32_t reg, res; - - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - reg = FLASH_F4_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - reg = FLASH_F7_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - } else { - reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; - } - - stlink_read_debug32(sl, reg, &res); + DLOG("*** stlink_core_id ***\n"); + ret = sl->backend->core_id(sl); -#if DEBUG_FLASH - fprintf(stdout, "CR:0x%x\n", res); -#endif - return (res); -} + if (ret == -1) { + ELOG("Failed to read core_id\n"); + return (ret); + } -static inline unsigned int is_flash_locked(stlink_t *sl) { - /* return non zero for true */ - uint32_t cr_lock_shift; - uint32_t cr_reg; - uint32_t n; - - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - cr_lock_shift = FLASH_H7_CR_LOCK; - } else { - ELOG("unsupported flash method, abort\n"); - return (-1); + if (sl->verbose > 2) { + stlink_print_data(sl); } - stlink_read_debug32(sl, cr_reg, &n); - return (n & (1u << cr_lock_shift)); + DLOG("core_id = 0x%08x\n", sl->core_id); + return (ret); } -static void unlock_flash(stlink_t *sl) { - uint32_t key_reg, key2_reg = 0; - uint32_t flash_key1 = FLASH_KEY1; - uint32_t flash_key2 = FLASH_KEY2; - /* The unlock sequence consists of 2 write cycles where 2 key values are - * written to the FLASH_KEYR register. An invalid sequence results in a - * definitive lock of the FPEC block until next reset. - */ +// stlink_chip_id() is called by stlink_load_device_params() +// do not call this procedure directly. +int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { + int ret; + cortex_m3_cpuid_t cpu_id; - if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { - key_reg = FLASH_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - key_reg = FLASH_KEYR; - key2_reg = FLASH_KEYR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - key_reg = FLASH_F4_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - key_reg = FLASH_F7_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; - flash_key1 = FLASH_L0_PEKEY1; - flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - key_reg = STM32L4_FLASH_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - key_reg = STM32Gx_FLASH_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - key_reg = STM32WB_FLASH_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - key_reg = FLASH_H7_KEYR1; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - key2_reg = FLASH_H7_KEYR2; - } - } else { - ELOG("unsupported flash method, abort\n"); - return; + // Read the CPU ID to determine where to read the core id + if (stlink_cpu_id(sl, &cpu_id) || + cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) { + ELOG("Can not connect to target. Please use \'connect under reset\' and " + "try again\n"); + return -1; } - stlink_write_debug32(sl, key_reg, flash_key1); - stlink_write_debug32(sl, key_reg, flash_key2); - - if (key2_reg) { - stlink_write_debug32(sl, key2_reg, flash_key1); - stlink_write_debug32(sl, key2_reg, flash_key2); - } -} + /* + * the chip_id register in the reference manual have + * DBGMCU_IDCODE / DBG_IDCODE name + * + */ -/* unlock flash if already locked */ -static int unlock_flash_if(stlink_t *sl) { - if (is_flash_locked(sl)) { - unlock_flash(sl); + if ((sl->core_id == STM32_CORE_ID_M7F_H7_SWD || sl->core_id == STM32_CORE_ID_M7F_H7_JTAG) && + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { + // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) + ret = stlink_read_debug32(sl, 0x5c001000, chip_id); + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0 || + cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0P) { + // STM32F0 (RM0091, pg914; RM0360, pg713) + // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) + // STM32G0 (RM0444, pg1367) + ret = stlink_read_debug32(sl, 0x40015800, chip_id); + } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) { + // STM32L5 (RM0438, pg2157) + ret = stlink_read_debug32(sl, 0xE0044000, chip_id); + } else /* СM3, СM4, CM7 */ { + // default chipid address - if (is_flash_locked(sl)) { - WLOG("Failed to unlock flash!\n"); - return (-1); - } + // STM32F1 (RM0008, pg1087; RM0041, pg681) + // STM32F2 (RM0033, pg1326) + // STM32F3 (RM0316, pg1095; RM0313, pg874) + // STM32F7 (RM0385, pg1676; RM0410, pg1912) + // STM32L1 (RM0038, pg861) + // STM32L4 (RM0351, pg1840; RM0394, pg1560) + // STM32G4 (RM0440, pg2086) + // STM32WB (RM0434, pg1406) + ret = stlink_read_debug32(sl, 0xE0042000, chip_id); } - DLOG("Successfully unlocked flash\n"); - return (0); -} + if (ret || !(*chip_id)) { + *chip_id = 0; + ret = ret?ret:-1; + ELOG("Could not find chip id!\n"); + } else { + *chip_id = (*chip_id) & 0xfff; -static void lock_flash(stlink_t *sl) { - uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; - uint32_t cr_mask = 0xffffffffu; - - if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - cr_reg = FLASH_CR; - cr2_reg = FLASH_CR2; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr2_reg = FLASH_H7_CR2; + // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for + // F2/F4 + if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) { + *chip_id = 0x413; } - cr_lock_shift = FLASH_H7_CR_LOCK; - cr_mask = ~(1u << FLASH_H7_CR_SER); - } else { - ELOG("unsupported flash method, abort\n"); - return; } - stlink_read_debug32(sl, cr_reg, &n); - n &= cr_mask; - n |= (1u << cr_lock_shift); - stlink_write_debug32(sl, cr_reg, n); - - if (cr2_reg) { - n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift); - stlink_write_debug32(sl, cr2_reg, n); - } + return (ret); } -static bool is_flash_option_locked(stlink_t *sl) { - uint32_t optlock_shift, optcr_reg; - int active_bit_level = 1; - uint32_t n; - - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; /* bit is "option write enable", not lock */ - break; - case STM32_FLASH_TYPE_F2_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STM32_FLASH_TYPE_F7: - optcr_reg = FLASH_F7_OPTCR; - optlock_shift = FLASH_F7_OPTCR_LOCK; - break; - case STM32_FLASH_TYPE_L0_L1: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STM32_FLASH_TYPE_L4_L4P: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STM32_FLASH_TYPE_WB_WL: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - case STM32_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; - } - - stlink_read_debug32(sl, optcr_reg, &n); +/** + * Cortex M tech ref manual, CPUID register description + * @param sl stlink context + * @param cpuid pointer to the result object + */ +int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { + uint32_t raw; - if (active_bit_level == 0) { - return (!(n & (1u << optlock_shift))); + if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { + cpuid->implementer_id = 0; + cpuid->variant = 0; + cpuid->part = 0; + cpuid->revision = 0; + return (-1); } - return (n & (1u << optlock_shift)); + cpuid->implementer_id = (raw >> 24) & 0x7f; + cpuid->variant = (raw >> 20) & 0xf; + cpuid->part = (raw >> 4) & 0xfff; + cpuid->revision = raw & 0xf; + return (0); } +// 303 +/** + * Reads and decodes the flash parameters, as dynamically as possible + * @param sl + * @return 0 for success, or -1 for unsupported core type. + */ + int stlink_load_device_params(stlink_t *sl) { + // This seems to normally work so is unnecessary info for a normal user. + // Demoted to debug. -- REW + DLOG("Loading device parameters....\n"); + const struct stlink_chipid_params *params = NULL; + stlink_core_id(sl); + uint32_t flash_size; + + if (stlink_chip_id(sl, &sl->chip_id)) { + return (-1); + } + + params = stlink_chipid_get_params(sl->chip_id); + + if (params == NULL) { + WLOG("unknown chip id! %#x\n", sl->chip_id); + return (-1); + } + + if (params->flash_type == STM32_FLASH_TYPE_UNKNOWN) { + WLOG("Invalid flash type, please check device declaration\n"); + sl->flash_size = 0; + return (0); + } + + // These are fixed... + sl->flash_base = STM32_FLASH_BASE; + sl->sram_base = STM32_SRAM_BASE; + stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size); + + if (params->flash_size_reg & 2) { + flash_size = flash_size >> 16; + } + + flash_size = flash_size & 0xffff; + + if ((sl->chip_id == STM32_CHIPID_L1_MD || + sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_L1_MD_PLUS) && + (flash_size == 0)) { + sl->flash_size = 128 * 1024; + } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { + sl->flash_size = (flash_size & 0xff) * 1024; + } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_MD_PLUS_HD) { + // 0 is 384k and 1 is 256k + if (flash_size == 0) { + sl->flash_size = 384 * 1024; + } else { + sl->flash_size = 256 * 1024; + } + } else { + sl->flash_size = flash_size * 1024; + } + + sl->flash_type = params->flash_type; + sl->flash_pgsz = params->flash_pagesize; + sl->sram_size = params->sram_size; + sl->sys_base = params->bootrom_base; + sl->sys_size = params->bootrom_size; + sl->option_base = params->option_base; + sl->option_size = params->option_size; + sl->chip_flags = params->flags; + + // medium and low devices have the same chipid. ram size depends on flash + // size. STM32F100xx datasheet Doc ID 16455 Table 2 + if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && + sl->flash_size < 64 * 1024) { + sl->sram_size = 0x1000; + } + + if (sl->chip_id == STM32_CHIPID_G4_CAT3) { + uint32_t flash_optr; + stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); + + if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { + sl->flash_pgsz <<= 1; + } + } + + // H7 devices with small flash has one bank + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && + sl->flash_type == STM32_FLASH_TYPE_H7) { + if ((sl->flash_size / sl->flash_pgsz) <= 1) + sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; + } + + ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", + params->dev_type, (unsigned)(sl->sram_size / 1024), + (unsigned)(sl->flash_size / 1024), + (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) + : (unsigned)(sl->flash_pgsz / 1024), + (sl->flash_pgsz < 1024) ? "byte" : "KiB"); + + return (0); + } -static int lock_flash_option(stlink_t *sl) { - uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; - int active_bit_level = 1; +int stlink_reset(stlink_t *sl, enum reset_type type) { + uint32_t dhcsr; + unsigned timeout; - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; - optlock_shift = FLASH_CR_OPTWRE; - active_bit_level = 0; - break; - case STM32_FLASH_TYPE_F2_F4: - optcr_reg = FLASH_F4_OPTCR; - optlock_shift = FLASH_F4_OPTCR_LOCK; - break; - case STM32_FLASH_TYPE_F7: - optcr_reg = FLASH_F7_OPTCR; - optlock_shift = FLASH_F7_OPTCR_LOCK; - break; - case STM32_FLASH_TYPE_L0_L1: - optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; - break; - case STM32_FLASH_TYPE_L4_L4P: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; - break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; - break; - case STM32_FLASH_TYPE_WB_WL: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; - break; - case STM32_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optcr2_reg = FLASH_H7_OPTCR2; - break; - default: - ELOG("unsupported flash method, abort\n"); - return -1; - } + DLOG("*** stlink_reset ***\n"); - stlink_read_debug32(sl, optcr_reg, &n); + sl->core_stat = TARGET_RESET; - if (active_bit_level == 0) { - n &= ~(1u << optlock_shift); - } else { - n |= (1u << optlock_shift); + if (type == RESET_AUTO) { + // clear S_RESET_ST in DHCSR register for reset state detection + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); } - stlink_write_debug32(sl, optcr_reg, n); - - if (optcr2_reg) { - stlink_read_debug32(sl, optcr2_reg, &n); - - if (active_bit_level == 0) { - n &= ~(1u << optlock_shift); - } else { - n |= (1u << optlock_shift); + if (type == RESET_HARD || type == RESET_AUTO) { + // hardware target reset + if (sl->version.stlink_v > 1) { + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(100); + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); } - - stlink_write_debug32(sl, optcr2_reg, n); + sl->backend->reset(sl); + usleep(10000); } - return (0); -} + if (type == RESET_AUTO) { + /* Check if the S_RESET_ST bit is set in DHCSR + * This means that a reset has occurred + * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ -static int unlock_flash_option(stlink_t *sl) { - uint32_t optkey_reg, optkey2_reg = 0; - uint32_t optkey1 = FLASH_OPTKEY1; - uint32_t optkey2 = FLASH_OPTKEY2; + dhcsr = 0; + int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) { + // reset not done yet + // try reset through AIRCR so that NRST does not need to be connected + + WLOG("NRST is not connected\n"); + DLOG("Using reset through SYSRESETREQ\n"); + return stlink_soft_reset(sl, 0); + } + + // waiting for reset the S_RESET_ST bit within 500ms + timeout = time_ms() + 500; + while (time_ms() < timeout) { + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + return (0); + } + } - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - optkey_reg = FLASH_OPTKEYR; - optkey1 = FLASH_F0_OPTKEY1; - optkey2 = FLASH_F0_OPTKEY2; - break; - case STM32_FLASH_TYPE_F2_F4: - optkey_reg = FLASH_F4_OPT_KEYR; - break; - case STM32_FLASH_TYPE_F7: - optkey_reg = FLASH_F7_OPT_KEYR; - break; - case STM32_FLASH_TYPE_L0_L1: - optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; - optkey1 = FLASH_L0_OPTKEY1; - optkey2 = FLASH_L0_OPTKEY2; - break; - case STM32_FLASH_TYPE_L4_L4P: - optkey_reg = STM32L4_FLASH_OPTKEYR; - break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - optkey_reg = STM32Gx_FLASH_OPTKEYR; - break; - case STM32_FLASH_TYPE_WB_WL: - optkey_reg = STM32WB_FLASH_OPT_KEYR; - break; - case STM32_FLASH_TYPE_H7: - optkey_reg = FLASH_H7_OPT_KEYR; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optkey2_reg = FLASH_H7_OPT_KEYR2; - break; - default: - ELOG("unsupported flash method, abort\n"); return (-1); } - stlink_write_debug32(sl, optkey_reg, optkey1); - stlink_write_debug32(sl, optkey_reg, optkey2); - - if (optkey2_reg) { - stlink_write_debug32(sl, optkey2_reg, optkey1); - stlink_write_debug32(sl, optkey2_reg, optkey2); + if (type == RESET_SOFT || type == RESET_SOFT_AND_HALT) { + return stlink_soft_reset(sl, (type == RESET_SOFT_AND_HALT)); } return (0); } +// 255 +int stlink_run(stlink_t *sl, enum run_type type) { + struct stlink_reg rr; + DLOG("*** stlink_run ***\n"); -static int unlock_flash_option_if(stlink_t *sl) { - if (is_flash_option_locked(sl)) { - if (unlock_flash_option(sl)) { - ELOG("Could not unlock flash option!\n"); - return (-1); - } - - if (is_flash_option_locked(sl)) { - ELOG("Failed to unlock flash option!\n"); - return (-1); - } + /* Make sure we are in Thumb mode + * Cortex-M chips don't support ARM mode instructions + * xPSR may be incorrect if the vector table has invalid data */ + stlink_read_reg(sl, 16, &rr); + if ((rr.xpsr & (1 << 24)) == 0) { + ILOG("Go to Thumb mode\n"); + stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); } - DLOG("Successfully unlocked flash option\n"); - return (0); + return (sl->backend->run(sl, type)); } - -static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, x; - - x = read_flash_cr(sl, bank); - - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - cr_reg = STM32L4_FLASH_CR; - x &= ~STM32L4_FLASH_CR_OPBITS; - x |= (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - x |= (1 << FLASH_H7_CR_PG); - } else { - cr_reg = FLASH_CR; - x = (1 << FLASH_CR_PG); +// 273 +int stlink_set_swdclk(stlink_t *sl, int freq_khz) { + DLOG("*** set_swdclk ***\n"); + return (sl->backend->set_swdclk(sl, freq_khz)); +} +// 293 +// this function is called by stlink_status() +// do not call stlink_core_stat() directly, always use stlink_status() +void stlink_core_stat(stlink_t *sl) { + switch (sl->core_stat) { + case TARGET_RUNNING: + DLOG(" core status: running\n"); + return; + case TARGET_HALTED: + DLOG(" core status: halted\n"); + return; + case TARGET_RESET: + DLOG(" core status: reset\n"); + return; + case TARGET_DEBUG_RUNNING: + DLOG(" core status: debug running\n"); + return; + default: + DLOG(" core status: unknown\n"); } +} +// 256 +int stlink_status(stlink_t *sl) { + int ret; - stlink_write_debug32(sl, cr_reg, x); + DLOG("*** stlink_status ***\n"); + ret = sl->backend->status(sl); + stlink_core_stat(sl); + return (ret); } +// 257 +int stlink_version(stlink_t *sl) { + DLOG("*** looking up stlink version\n"); -static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, n; - uint32_t bit = FLASH_CR_PG; - - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - cr_reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - bit = FLASH_H7_CR_PG; - } else { - cr_reg = FLASH_CR; + if (sl->backend->version(sl)) { + return (-1); } - n = read_flash_cr(sl, bank) & ~(1 << bit); - stlink_write_debug32(sl, cr_reg, n); -} + _parse_version(sl, &sl->version); -static void set_flash_cr_per(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, val; + DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, + STLINK_USB_VID_ST); + DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); + DLOG("stlink version = 0x%x\n", sl->version.stlink_v); + DLOG("jtag version = 0x%x\n", sl->version.jtag_v); + DLOG("swim version = 0x%x\n", sl->version.swim_v); - if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + if (sl->version.jtag_v == 0) { + WLOG(" warning: stlink doesn't support JTAG/SWD interface\n"); } - stlink_read_debug32(sl, cr_reg, &val); - val |= (1 << FLASH_CR_PER); - stlink_write_debug32(sl, cr_reg, val); + return (0); } +// 272 +int stlink_target_voltage(stlink_t *sl) { + int voltage = -1; + DLOG("*** reading target voltage\n"); -static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { - uint32_t cr_reg; + if (sl->backend->target_voltage != NULL) { + voltage = sl->backend->target_voltage(sl); - if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; + if (voltage != -1) { + DLOG("target voltage = %imV\n", voltage); + } else { + DLOG("error reading target voltage\n"); + } } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + DLOG("reading voltage not supported by backend\n"); } - const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER); - stlink_write_debug32(sl, cr_reg, n); + return (voltage); } +// 299 +bool stlink_is_core_halted(stlink_t *sl) { + stlink_status(sl); + return (sl->core_stat == TARGET_HALTED); +} +// 269 +int stlink_step(stlink_t *sl) { + DLOG("*** stlink_step ***\n"); + return (sl->backend->step(sl)); +} +// 270 +int stlink_current_mode(stlink_t *sl) { + int mode = sl->backend->current_mode(sl); -static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { - uint32_t val, cr_reg, cr_mer, cr_pg; - - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - cr_reg = STM32L4_FLASH_CR; - cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); - cr_pg = (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_mer = (1 << STM32Gx_FLASH_CR_MER1); - - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); - } - - cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_mer = (1 << FLASH_CR_MER); - cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - cr_mer = (1 << FLASH_H7_CR_BER); - cr_pg = (1 << FLASH_H7_CR_PG); - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; - cr_mer = (1 << FLASH_CR_MER); - cr_pg = (1 << FLASH_CR_PG); + switch (mode) { + case STLINK_DEV_DFU_MODE: + DLOG("stlink current mode: dfu\n"); + return (mode); + case STLINK_DEV_DEBUG_MODE: + DLOG("stlink current mode: debug (jtag or swd)\n"); + return (mode); + case STLINK_DEV_MASS_MODE: + DLOG("stlink current mode: mass\n"); + return (mode); } - stlink_read_debug32(sl, cr_reg, &val); - - if (val & cr_pg) { - // STM32F030 will drop MER bit if PG was set - val &= ~cr_pg; - stlink_write_debug32(sl, cr_reg, val); + DLOG("stlink mode: unknown!\n"); + return (STLINK_DEV_UNKNOWN_MODE); +} +// 274 +int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { + DLOG("*** stlink_trace_enable ***\n"); + return (sl->backend->trace_enable(sl, frequency)); +} +// 275 +int stlink_trace_disable(stlink_t *sl) { + DLOG("*** stlink_trace_disable ***\n"); + return (sl->backend->trace_disable(sl)); +} +// 276 +int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { + return (sl->backend->trace_read(sl, buf, size)); +} +// 294 +void stlink_print_data(stlink_t *sl) { + if (sl->q_len <= 0 || sl->verbose < UDEBUG) { + return; } - if (v) { - val |= cr_mer; - } else { - val &= ~cr_mer; + if (sl->verbose > 2) { + DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); } - stlink_write_debug32(sl, cr_reg, val); + for (int i = 0; i < sl->q_len; i++) { + if (i % 16 == 0) { + /* + if (sl->q_data_dir == Q_DATA_OUT) { + fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); + } else { + fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); + } + */ + } + // DLOG(" %02x", (unsigned int) sl->q_buf[i]); + fprintf(stderr, " %02x", (unsigned int)sl->q_buf[i]); + } + // DLOG("\n\n"); + fprintf(stderr, "\n"); } +// 283 +int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, + stm32_addr_t addr) { + // write the file in sram at addr -static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { - uint32_t val, cr_reg, cr_strt; - - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - cr_reg = STM32L4_FLASH_CR; - cr_strt = (1 << STM32L4_FLASH_CR_STRT); - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_strt = (1 << STM32Gx_FLASH_CR_STRT); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_strt = (1 << STM32WB_FLASH_CR_STRT); - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; - cr_strt = (1 << FLASH_CR_STRT); + int error = -1; + size_t off; + size_t len; + + // check addr range is inside the sram + if (addr < sl->sram_base) { + fprintf(stderr, "addr too low\n"); + goto on_error; + } else if ((addr + length) < addr) { + fprintf(stderr, "addr overruns\n"); + goto on_error; + } else if ((addr + length) > (sl->sram_base + sl->sram_size)) { + fprintf(stderr, "addr too high\n"); + goto on_error; + } else if (addr & 3) { + fprintf(stderr, "unaligned addr\n"); + goto on_error; } - stlink_read_debug32(sl, cr_reg, &val); - val |= cr_strt; - stlink_write_debug32(sl, cr_reg, val); -} + len = length; -static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { - uint32_t res, sr_reg; - - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; - } else { - ELOG("method 'read_flash_sr' is unsupported\n"); - return (-1); + if (len & 3) { + len -= len & 3; } - stlink_read_debug32(sl, sr_reg, &res); - return (res); -} + // do the copy by 1kB blocks + for (off = 0; off < len; off += 1024) { + size_t size = 1024; -static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { - uint32_t sr_reg; - - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; - } else { - ELOG("method 'write_flash_sr' is unsupported\n"); - return (-1); - } + if ((off + size) > len) { + size = len - off; + } - return stlink_write_debug32(sl, sr_reg, val); -} + memcpy(sl->q_buf, data + off, size); -static inline unsigned int is_flash_busy(stlink_t *sl) { - uint32_t sr_busy_shift; - unsigned int res; - - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || - (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { - sr_busy_shift = FLASH_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - sr_busy_shift = FLASH_F4_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - sr_busy_shift = STM32L4_FLASH_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - sr_busy_shift = STM32Gx_FLASH_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_busy_shift = STM32WB_FLASH_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - sr_busy_shift = FLASH_H7_SR_QW; - } else { - ELOG("method 'is_flash_busy' is unsupported\n"); - return (-1); - } + if (size & 3) { + size += 2; + } // round size if needed - res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); + stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); + } - if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || - (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); + if (length > len) { + memcpy(sl->q_buf, data + len, length - len); + stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(length - len)); } - return (res); -} + error = 0; // success + stlink_fwrite_finalize(sl, addr); -static void wait_flash_busy(stlink_t *sl) { - // TODO: add some delays here - while (is_flash_busy(sl)) - ; +on_error: + return (error); } +//284 +int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { + // write the file in sram at addr -static void wait_flash_busy_progress(stlink_t *sl) { - int i = 0; - fprintf(stdout, "Mass erasing"); - fflush(stdout); - - while (is_flash_busy(sl)) { - usleep(10000); - i++; + int error = -1; + size_t off; + size_t len; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; - if (i % 100 == 0) { - fprintf(stdout, "."); - fflush(stdout); - } + if (map_file(&mf, path) == -1) { + fprintf(stderr, "map_file() == -1\n"); + return (-1); } - fprintf(stdout, "\n"); -} + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); -static void clear_flash_error(stlink_t *sl) { - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); - break; - case STM32_FLASH_TYPE_F2_F4: - write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); - break; - case STM32_FLASH_TYPE_F7: - write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); - break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); - break; - case STM32_FLASH_TYPE_L0_L1: - write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); - break; - case STM32_FLASH_TYPE_L4_L4P: - write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); - break; - case STM32_FLASH_TYPE_H7: - write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); - } - break; - case STM32_FLASH_TYPE_WB_WL: - write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); - break; - default: - break; + // check if addr range is inside the SRAM + if (addr < sl->sram_base) { + fprintf(stderr, "addr too low\n"); + goto on_error; + } else if ((addr + mf.len) < addr) { + fprintf(stderr, "addr overruns\n"); + goto on_error; + } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { + fprintf(stderr, "addr too high\n"); + goto on_error; + } else if (addr & 3) { + fprintf(stderr, "unaligned addr\n"); + goto on_error; } -} - -static int check_flash_error(stlink_t *sl) { - uint32_t res = 0; - uint32_t WRPERR, PROGERR, PGAERR; - WRPERR = PROGERR = PGAERR = 0; + len = mf.len; - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; - if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; - } - WRPERR = (1 << FLASH_SR_WRPRT_ERR); - PROGERR = (1 << FLASH_SR_PG_ERR); - break; - case STM32_FLASH_TYPE_F2_F4: - res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; - WRPERR = (1 << FLASH_F4_SR_WRPERR); - PGAERR = (1 << FLASH_F4_SR_PGAERR); - break; - case STM32_FLASH_TYPE_F7: - res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; - WRPERR = (1 << FLASH_F7_SR_WRP_ERR); - PROGERR = (1 << FLASH_F7_SR_PGP_ERR); - break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); - PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); - PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); - break; - case STM32_FLASH_TYPE_L0_L1: - res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); - PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); - break; - case STM32_FLASH_TYPE_L4_L4P: - res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); - PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); - break; - case STM32_FLASH_TYPE_H7: - res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; - } - WRPERR = (1 << FLASH_H7_SR_WRPERR); - break; - case STM32_FLASH_TYPE_WB_WL: - res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); - PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); - PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); - break; - default: - break; + if (len & 3) { + len -= len & 3; } - if (res) { - if (WRPERR && (WRPERR & res) == WRPERR) { - ELOG("Flash memory is write protected\n"); - res &= ~WRPERR; - } else if (PROGERR && (PROGERR & res) == PROGERR) { - ELOG("Flash memory contains a non-erased value\n"); - res &= ~PROGERR; - } else if (PGAERR && (PGAERR & res) == PGAERR) { - ELOG("Invalid flash address\n"); - res &= ~PGAERR; - } + // do the copy by 1kB blocks + for (off = 0; off < len; off += 1024) { + size_t size = 1024; - if (res) { - ELOG("Flash programming error: %#010x\n", res); + if ((off + size) > len) { + size = len - off; } - return (-1); - } - return (0); -} + memcpy(sl->q_buf, mf.base + off, size); -static void stop_wdg_in_debug(stlink_t *sl) { - uint32_t dbgmcu_cr; - uint32_t set; - uint32_t value; + if (size & 3) { + size += 2; + } // round size if needed - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - case STM32_FLASH_TYPE_G4: - dbgmcu_cr = STM32F0_DBGMCU_CR; - set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | - (1 << STM32F0_DBGMCU_CR_WWDG_STOP); - break; - case STM32_FLASH_TYPE_F2_F4: - case STM32_FLASH_TYPE_F7: - case STM32_FLASH_TYPE_L4_L4P: - dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; - set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | - (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); - break; - case STM32_FLASH_TYPE_L0_L1: - case STM32_FLASH_TYPE_G0: - dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; - set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | - (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); - break; - case STM32_FLASH_TYPE_H7: - dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; - set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP); - break; - case STM32_FLASH_TYPE_WB_WL: - dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1; - set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) | - (1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP); - break; - default: - return; + stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); } - if (!stlink_read_debug32(sl, dbgmcu_cr, &value)) { - stlink_write_debug32(sl, dbgmcu_cr, value | set); + if (mf.len > len) { + memcpy(sl->q_buf, mf.base + len, mf.len - len); + stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(mf.len - len)); } -} -static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { - uint32_t rcc, rcc_dma_mask, value; - - rcc = rcc_dma_mask = value = 0; - - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - rcc = STM32F1_RCC_AHBENR; - rcc_dma_mask = STM32F1_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_F2_F4: - case STM32_FLASH_TYPE_F7: - rcc = STM32F4_RCC_AHB1ENR; - rcc_dma_mask = STM32F4_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_G0: - rcc = STM32G0_RCC_AHBENR; - rcc_dma_mask = STM32G0_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_G4: - case STM32_FLASH_TYPE_L4_L4P: - rcc = STM32G4_RCC_AHB1ENR; - rcc_dma_mask = STM32G4_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_L0_L1: - rcc = STM32L0_RCC_AHBENR; - rcc_dma_mask = STM32L0_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_H7: - rcc = STM32H7_RCC_AHB1ENR; - rcc_dma_mask = STM32H7_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_WB_WL: - rcc = STM32WB_RCC_AHB1ENR; - rcc_dma_mask = STM32WB_RCC_DMAEN; - break; - default: - return; + // check the file has been written + if (check_file(sl, &mf, addr) == -1) { + fprintf(stderr, "check_file() == -1\n"); + goto on_error; } - if (!stlink_read_debug32(sl, rcc, &value)) { - if (bckpRstr) { - value = (value & (~rcc_dma_mask)) | fl->rcc_dma_bkp; - } else { - fl->rcc_dma_bkp = value & rcc_dma_mask; - value &= ~rcc_dma_mask; - } - stlink_write_debug32(sl, rcc, value); - } -} + error = 0; // success + stlink_fwrite_finalize(sl, addr); -static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { - stlink_write_debug32(sl, (bank == BANK_1) ? FLASH_AR : FLASH_AR2, n); +on_error: + unmap_file(&mf); + return (error); } +// 302 +int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, + stm32_addr_t addr, size_t size) { + // read size bytes from addr to file + ILOG("read from address %#010x size %u\n", addr, (unsigned)size); -static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n, - unsigned bank) { - uint32_t cr_reg, psize_shift; - uint32_t x = read_flash_cr(sl, bank); + int error; + int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); - if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - psize_shift = FLASH_H7_CR_PSIZE; - } else { - cr_reg = FLASH_F4_CR; - psize_shift = 8; + if (fd == -1) { + fprintf(stderr, "open(%s) == -1\n", path); + return (-1); } - x &= ~(0x03 << psize_shift); - x |= (n << psize_shift); -#if DEBUG_FLASH - fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); -#endif - stlink_write_debug32(sl, cr_reg, x); -} + if (is_ihex) { + struct stlink_fread_ihex_worker_arg arg; -static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { - uint32_t cr_reg, snb_mask, snb_shift, ser_shift; - uint32_t x = read_flash_cr(sl, bank); + if (stlink_fread_ihex_init(&arg, fd, addr)) { + error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); - if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - snb_mask = FLASH_H7_CR_SNB_MASK; - snb_shift = FLASH_H7_CR_SNB; - ser_shift = FLASH_H7_CR_SER; + if (!stlink_fread_ihex_finalize(&arg)) { + error = -1; + } + } else { + error = -1; + } } else { - cr_reg = FLASH_F4_CR; - snb_mask = FLASH_F4_CR_SNB_MASK; - snb_shift = FLASH_F4_CR_SNB; - ser_shift = FLASH_F4_CR_SER; + struct stlink_fread_worker_arg arg = {fd}; + error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); } - x &= ~snb_mask; - x |= (n << snb_shift); - x |= (1 << ser_shift); -#if DEBUG_FLASH - fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); -#endif - stlink_write_debug32(sl, cr_reg, x); -} - -static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { - stlink_write_debug32(sl, STM32L4_FLASH_SR, - 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); - uint32_t x = read_flash_cr(sl, BANK_1); - x &= ~STM32L4_FLASH_CR_OPBITS; - x &= ~STM32L4_FLASH_CR_PAGEMASK; - x &= ~(1 << STM32L4_FLASH_CR_MER1); - x &= ~(1 << STM32L4_FLASH_CR_MER2); - x |= (n << STM32L4_FLASH_CR_PNB); - x |= (uint32_t)(1lu << STM32L4_FLASH_CR_PER); -#if DEBUG_FLASH - fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); -#endif - stlink_write_debug32(sl, STM32L4_FLASH_CR, x); + close(fd); + return (error); } +// 300 +int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, + size_t size) { + // write the buffer right after the loader + int ret = 0; + size_t chunk = size & ~0x3; + size_t rem = size & 0x3; -// Delegates to the backends... - -void stlink_close(stlink_t *sl) { - DLOG("*** stlink_close ***\n"); + if (chunk) { + memcpy(sl->q_buf, buf, chunk); + ret = stlink_write_mem32(sl, fl->buf_addr, (uint16_t)chunk); + } - if (!sl) { - return; + if (rem && !ret) { + memcpy(sl->q_buf, buf + chunk, rem); + ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, (uint16_t)rem); } - sl->backend->close(sl); - free(sl); + return (ret); } +// 291 +uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { + if ((sl->chip_id == STM32_CHIPID_F2) || + (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || + (sl->chip_id == STM32_CHIPID_F4_HD) || + (sl->chip_id == STM32_CHIPID_F411xx) || + (sl->chip_id == STM32_CHIPID_F446) || + (sl->chip_id == STM32_CHIPID_F4_DSI) || + (sl->chip_id == STM32_CHIPID_F72xxx) || + (sl->chip_id == STM32_CHIPID_F412)) { + uint32_t sector = calculate_F4_sectornum(flashaddr); -int stlink_exit_debug_mode(stlink_t *sl) { - DLOG("*** stlink_exit_debug_mode ***\n"); + if (sector >= 12) { + sector -= 12; + } - if (sl->flash_type != STM32_FLASH_TYPE_UNKNOWN && - sl->core_stat != TARGET_RESET) { - // stop debugging if the target has been identified - stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); + if (sector < 4) { + sl->flash_pgsz = 0x4000; + } else if (sector < 5) { + sl->flash_pgsz = 0x10000; + } else { + sl->flash_pgsz = 0x20000; + } + } else if (sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx) { + uint32_t sector = calculate_F7_sectornum(flashaddr); + + if (sector < 4) { + sl->flash_pgsz = 0x8000; + } else if (sector < 5) { + sl->flash_pgsz = 0x20000; + } else { + sl->flash_pgsz = 0x40000; + } } - return (sl->backend->exit_debug_mode(sl)); + return ((uint32_t)sl->flash_pgsz); } +// 279 +int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, + size_t *size, uint32_t *begin) { + int res = 0; + *begin = UINT32_MAX; + uint8_t *data = NULL; + uint32_t end = 0; + bool eof_found = false; -int stlink_enter_swd_mode(stlink_t *sl) { - DLOG("*** stlink_enter_swd_mode ***\n"); - return (sl->backend->enter_swd_mode(sl)); -} + for (int scan = 0; (res == 0) && (scan < 2); ++scan) { + // parse file two times - first to find memory range, second - to fill it + if (scan == 1) { + if (!eof_found) { + ELOG("No EoF recond\n"); + res = -1; + break; + } -// Force the core into the debug mode -> halted state. -int stlink_force_debug(stlink_t *sl) { - DLOG("*** stlink_force_debug_mode ***\n"); - int res = sl->backend->force_debug(sl); - if (res) { - return (res); - } - // Stop the watchdogs in the halted state for suppress target reboot - stop_wdg_in_debug(sl); - return (0); -} - -int stlink_exit_dfu_mode(stlink_t *sl) { - DLOG("*** stlink_exit_dfu_mode ***\n"); - return (sl->backend->exit_dfu_mode(sl)); -} - -int stlink_core_id(stlink_t *sl) { - int ret; - - DLOG("*** stlink_core_id ***\n"); - ret = sl->backend->core_id(sl); - - if (ret == -1) { - ELOG("Failed to read core_id\n"); - return (ret); - } - - if (sl->verbose > 2) { - stlink_print_data(sl); - } - - DLOG("core_id = 0x%08x\n", sl->core_id); - return (ret); -} - -// stlink_chip_id() is called by stlink_load_device_params() -// do not call this procedure directly. -int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { - int ret; - cortex_m3_cpuid_t cpu_id; - - // Read the CPU ID to determine where to read the core id - if (stlink_cpu_id(sl, &cpu_id) || - cpu_id.implementer_id != STLINK_REG_CMx_CPUID_IMPL_ARM) { - ELOG("Can not connect to target. Please use \'connect under reset\' and " - "try again\n"); - return -1; - } - - /* - * the chip_id register in the reference manual have - * DBGMCU_IDCODE / DBG_IDCODE name - * - */ - - if ((sl->core_id == STM32_CORE_ID_M7F_H7_SWD || sl->core_id == STM32_CORE_ID_M7F_H7_JTAG) && - cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { - // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) - ret = stlink_read_debug32(sl, 0x5c001000, chip_id); - } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0 || - cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM0P) { - // STM32F0 (RM0091, pg914; RM0360, pg713) - // STM32L0 (RM0377, pg813; RM0367, pg915; RM0376, pg917) - // STM32G0 (RM0444, pg1367) - ret = stlink_read_debug32(sl, 0x40015800, chip_id); - } else if (cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM33) { - // STM32L5 (RM0438, pg2157) - ret = stlink_read_debug32(sl, 0xE0044000, chip_id); - } else /* СM3, СM4, CM7 */ { - // default chipid address - - // STM32F1 (RM0008, pg1087; RM0041, pg681) - // STM32F2 (RM0033, pg1326) - // STM32F3 (RM0316, pg1095; RM0313, pg874) - // STM32F7 (RM0385, pg1676; RM0410, pg1912) - // STM32L1 (RM0038, pg861) - // STM32L4 (RM0351, pg1840; RM0394, pg1560) - // STM32G4 (RM0440, pg2086) - // STM32WB (RM0434, pg1406) - ret = stlink_read_debug32(sl, 0xE0042000, chip_id); - } - - if (ret || !(*chip_id)) { - *chip_id = 0; - ret = ret?ret:-1; - ELOG("Could not find chip id!\n"); - } else { - *chip_id = (*chip_id) & 0xfff; - - // Fix chip_id for F4 rev A errata, read CPU ID, as CoreID is the same for - // F2/F4 - if (*chip_id == 0x411 && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM4) { - *chip_id = 0x413; - } - } - - return (ret); -} - -/** - * Cortex M tech ref manual, CPUID register description - * @param sl stlink context - * @param cpuid pointer to the result object - */ -int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { - uint32_t raw; - - if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { - cpuid->implementer_id = 0; - cpuid->variant = 0; - cpuid->part = 0; - cpuid->revision = 0; - return (-1); - } - - cpuid->implementer_id = (raw >> 24) & 0x7f; - cpuid->variant = (raw >> 20) & 0xf; - cpuid->part = (raw >> 4) & 0xfff; - cpuid->revision = raw & 0xf; - return (0); -} - -/** - * Reads and decodes the flash parameters, as dynamically as possible - * @param sl - * @return 0 for success, or -1 for unsupported core type. - */ -int stlink_load_device_params(stlink_t *sl) { - // This seems to normally work so is unnecessary info for a normal user. - // Demoted to debug. -- REW - DLOG("Loading device parameters....\n"); - const struct stlink_chipid_params *params = NULL; - stlink_core_id(sl); - uint32_t flash_size; - - if (stlink_chip_id(sl, &sl->chip_id)) { - return (-1); - } - - params = stlink_chipid_get_params(sl->chip_id); - - if (params == NULL) { - WLOG("unknown chip id! %#x\n", sl->chip_id); - return (-1); - } - - if (params->flash_type == STM32_FLASH_TYPE_UNKNOWN) { - WLOG("Invalid flash type, please check device declaration\n"); - sl->flash_size = 0; - return (0); - } - - // These are fixed... - sl->flash_base = STM32_FLASH_BASE; - sl->sram_base = STM32_SRAM_BASE; - stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size); - - if (params->flash_size_reg & 2) { - flash_size = flash_size >> 16; - } - - flash_size = flash_size & 0xffff; - - if ((sl->chip_id == STM32_CHIPID_L1_MD || - sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || - sl->chip_id == STM32_CHIPID_L1_MD_PLUS) && - (flash_size == 0)) { - sl->flash_size = 128 * 1024; - } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { - sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_MD_PLUS_HD) { - // 0 is 384k and 1 is 256k - if (flash_size == 0) { - sl->flash_size = 384 * 1024; - } else { - sl->flash_size = 256 * 1024; - } - } else { - sl->flash_size = flash_size * 1024; - } - - sl->flash_type = params->flash_type; - sl->flash_pgsz = params->flash_pagesize; - sl->sram_size = params->sram_size; - sl->sys_base = params->bootrom_base; - sl->sys_size = params->bootrom_size; - sl->option_base = params->option_base; - sl->option_size = params->option_size; - sl->chip_flags = params->flags; - - // medium and low devices have the same chipid. ram size depends on flash - // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && - sl->flash_size < 64 * 1024) { - sl->sram_size = 0x1000; - } - - if (sl->chip_id == STM32_CHIPID_G4_CAT3) { - uint32_t flash_optr; - stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); - - if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { - sl->flash_pgsz <<= 1; - } - } - - // H7 devices with small flash has one bank - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && - sl->flash_type == STM32_FLASH_TYPE_H7) { - if ((sl->flash_size / sl->flash_pgsz) <= 1) - sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; - } - - ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", - params->dev_type, (unsigned)(sl->sram_size / 1024), - (unsigned)(sl->flash_size / 1024), - (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) - : (unsigned)(sl->flash_pgsz / 1024), - (sl->flash_pgsz < 1024) ? "byte" : "KiB"); - - return (0); -} - -int stlink_jtag_reset(stlink_t *sl, int value) { - DLOG("*** stlink_jtag_reset %d ***\n", value); - return (sl->backend->jtag_reset(sl, value)); -} - -int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { - int ret; - unsigned timeout; - uint32_t dhcsr, dfsr; - - DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); - - // halt core and enable debugging (if not already done) - // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_DEBUGEN); - - // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) - if (halt_on_reset) { - stlink_write_debug32( - sl, STLINK_REG_CM3_DEMCR, - STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | - STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); - - // clear VCATCH in the DFSR register - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); - } else { - stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, - STLINK_REG_CM3_DEMCR_TRCENA | - STLINK_REG_CM3_DEMCR_VC_HARDERR | - STLINK_REG_CM3_DEMCR_VC_BUSERR); - } - - // clear S_RESET_ST in the DHCSR register - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - - // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) - ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, - STLINK_REG_AIRCR_VECTKEY | - STLINK_REG_AIRCR_SYSRESETREQ); - if (ret) { - ELOG("Soft reset failed: error write to AIRCR\n"); - return (ret); - } - - // waiting for a reset within 500ms - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - timeout = time_ms() + 500; - while (time_ms() < timeout) { - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - if (halt_on_reset) { - // waiting halt by the SYSRESETREQ exception - // DDI0403E, p. C1-699, Debug Fault Status Register - dfsr = 0; - stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); - if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { - continue; - } - } - timeout = 0; - break; - } - } - - // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); - - if (timeout) { - ELOG("Soft reset failed: timeout\n"); - return (-1); - } - - return (0); -} - -int stlink_reset(stlink_t *sl, enum reset_type type) { - uint32_t dhcsr; - unsigned timeout; - - DLOG("*** stlink_reset ***\n"); - - sl->core_stat = TARGET_RESET; - - if (type == RESET_AUTO) { - // clear S_RESET_ST in DHCSR register for reset state detection - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - } - - if (type == RESET_HARD || type == RESET_AUTO) { - // hardware target reset - if (sl->version.stlink_v > 1) { - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); - // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) - usleep(100); - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); - } - sl->backend->reset(sl); - usleep(10000); - } - - if (type == RESET_AUTO) { - /* Check if the S_RESET_ST bit is set in DHCSR - * This means that a reset has occurred - * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ - - dhcsr = 0; - int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) { - // reset not done yet - // try reset through AIRCR so that NRST does not need to be connected - - WLOG("NRST is not connected\n"); - DLOG("Using reset through SYSRESETREQ\n"); - return stlink_soft_reset(sl, 0); - } - - // waiting for reset the S_RESET_ST bit within 500ms - timeout = time_ms() + 500; - while (time_ms() < timeout) { - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - return (0); - } - } - - return (-1); - } - - if (type == RESET_SOFT || type == RESET_SOFT_AND_HALT) { - return stlink_soft_reset(sl, (type == RESET_SOFT_AND_HALT)); - } - - return (0); -} - -int stlink_run(stlink_t *sl, enum run_type type) { - struct stlink_reg rr; - DLOG("*** stlink_run ***\n"); - - /* Make sure we are in Thumb mode - * Cortex-M chips don't support ARM mode instructions - * xPSR may be incorrect if the vector table has invalid data */ - stlink_read_reg(sl, 16, &rr); - if ((rr.xpsr & (1 << 24)) == 0) { - ILOG("Go to Thumb mode\n"); - stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); - } - - return (sl->backend->run(sl, type)); -} - -int stlink_set_swdclk(stlink_t *sl, int freq_khz) { - DLOG("*** set_swdclk ***\n"); - return (sl->backend->set_swdclk(sl, freq_khz)); -} - -int stlink_status(stlink_t *sl) { - int ret; - - DLOG("*** stlink_status ***\n"); - ret = sl->backend->status(sl); - stlink_core_stat(sl); - return (ret); -} - -/** - * Decode the version bits, originally from -sg, verified with usb - * @param sl stlink context, assumed to contain valid data in the buffer - * @param slv output parsed version object - */ -void _parse_version(stlink_t *sl, stlink_version_t *slv) { - sl->version.flags = 0; - - if (sl->version.stlink_v < 3) { - uint32_t b0 = sl->q_buf[0]; // lsb - uint32_t b1 = sl->q_buf[1]; - uint32_t b2 = sl->q_buf[2]; - uint32_t b3 = sl->q_buf[3]; - uint32_t b4 = sl->q_buf[4]; - uint32_t b5 = sl->q_buf[5]; // msb - - // b0 b1 || b2 b3 | b4 b5 - // 4b | 6b | 6b || 2B | 2B - // stlink_v | jtag_v | swim_v || st_vid | stlink_pid - - slv->stlink_v = (b0 & 0xf0) >> 4; - slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); - slv->swim_v = b1 & 0x3f; - slv->st_vid = (b3 << 8) | b2; - slv->stlink_pid = (b5 << 8) | b4; - - // ST-LINK/V1 from J11 switch to api-v2 (and support SWD) - if (slv->stlink_v == 1) { - slv->jtag_api = - slv->jtag_v > 11 ? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; - } else { - slv->jtag_api = STLINK_JTAG_API_V2; - - // preferred API to get last R/W status from J15 - if (sl->version.jtag_v >= 15) { - sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; - } - - if (sl->version.jtag_v >= 13) { - sl->version.flags |= STLINK_F_HAS_TRACE; - sl->max_trace_freq = STLINK_V2_MAX_TRACE_FREQUENCY; - } - } - } else { - // V3 uses different version format, for reference see OpenOCD source - // (that was written from docs available from ST under NDA): - // https://github.com/ntfreak/openocd/blob/a6dacdff58ef36fcdac00c53ec27f19de1fbce0d/src/jtag/drivers/stlink_usb.c#L965 - slv->stlink_v = sl->q_buf[0]; - slv->swim_v = sl->q_buf[1]; - slv->jtag_v = sl->q_buf[2]; - slv->st_vid = (uint32_t)((sl->q_buf[9] << 8) | sl->q_buf[8]); - slv->stlink_pid = (uint32_t)((sl->q_buf[11] << 8) | sl->q_buf[10]); - slv->jtag_api = STLINK_JTAG_API_V3; - /* preferred API to get last R/W status */ - sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; - sl->version.flags |= STLINK_F_HAS_TRACE; - sl->max_trace_freq = STLINK_V3_MAX_TRACE_FREQUENCY; - } - - return; -} - -int stlink_version(stlink_t *sl) { - DLOG("*** looking up stlink version\n"); - - if (sl->backend->version(sl)) { - return (-1); - } - - _parse_version(sl, &sl->version); - - DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, - STLINK_USB_VID_ST); - DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); - DLOG("stlink version = 0x%x\n", sl->version.stlink_v); - DLOG("jtag version = 0x%x\n", sl->version.jtag_v); - DLOG("swim version = 0x%x\n", sl->version.swim_v); - - if (sl->version.jtag_v == 0) { - WLOG(" warning: stlink doesn't support JTAG/SWD interface\n"); - } - - return (0); -} - -int stlink_target_voltage(stlink_t *sl) { - int voltage = -1; - DLOG("*** reading target voltage\n"); - - if (sl->backend->target_voltage != NULL) { - voltage = sl->backend->target_voltage(sl); - - if (voltage != -1) { - DLOG("target voltage = %imV\n", voltage); - } else { - DLOG("error reading target voltage\n"); - } - } else { - DLOG("reading voltage not supported by backend\n"); - } - - return (voltage); -} - -int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { - int ret; - - ret = sl->backend->read_debug32(sl, addr, data); - if (!ret) - DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); - - return (ret); -} - -int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { - DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); - return sl->backend->write_debug32(sl, addr, data); -} - -int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); - - if (len % 4 != 0) { - ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return (-1); - } - - return (sl->backend->write_mem32(sl, addr, len)); -} - -int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_read_mem32 ***\n"); - - if (len % 4 != 0) { // !!! never ever: fw gives just wrong values - ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); - return (-1); - } - - return (sl->backend->read_mem32(sl, addr, len)); -} - -int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem8 ***\n"); - return (sl->backend->write_mem8(sl, addr, len)); -} - -int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_regs ***\n"); - return (sl->backend->read_all_regs(sl, regp)); -} - -int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_unsupported_regs ***\n"); - return (sl->backend->read_all_unsupported_regs(sl, regp)); -} - -int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { - DLOG("*** stlink_write_reg\n"); - return (sl->backend->write_reg(sl, reg, idx)); -} - -int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { - DLOG("*** stlink_read_reg\n"); - DLOG(" (%d) ***\n", r_idx); - - if (r_idx > 20 || r_idx < 0) { - fprintf(stderr, "Error: register index must be in [0..20]\n"); - return (-1); - } - - return (sl->backend->read_reg(sl, r_idx, regp)); -} - -int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, - struct stlink_reg *regp) { - int r_convert; - - DLOG("*** stlink_read_unsupported_reg\n"); - DLOG(" (%d) ***\n", r_idx); - - /* Convert to values used by STLINK_REG_DCRSR */ - if (r_idx >= 0x1C && - r_idx <= 0x1F) { // primask, basepri, faultmask, or control - r_convert = 0x14; - } else if (r_idx == 0x40) { // FPSCR - r_convert = 0x21; - } else if (r_idx >= 0x20 && r_idx < 0x40) { - r_convert = 0x40 + (r_idx - 0x20); - } else { - fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return (-1); - } - - return (sl->backend->read_unsupported_reg(sl, r_convert, regp)); -} - -int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, - struct stlink_reg *regp) { - int r_convert; - - DLOG("*** stlink_write_unsupported_reg\n"); - DLOG(" (%d) ***\n", r_idx); - - /* Convert to values used by STLINK_REG_DCRSR */ - if (r_idx >= 0x1C && - r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ - r_convert = r_idx; // the backend function handles this - } else if (r_idx == 0x40) { // FPSCR - r_convert = 0x21; - } else if (r_idx >= 0x20 && r_idx < 0x40) { - r_convert = 0x40 + (r_idx - 0x20); - } else { - fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); - return (-1); - } - - return (sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); -} - -bool stlink_is_core_halted(stlink_t *sl) { - stlink_status(sl); - return (sl->core_stat == TARGET_HALTED); -} - -int stlink_step(stlink_t *sl) { - DLOG("*** stlink_step ***\n"); - return (sl->backend->step(sl)); -} - -int stlink_current_mode(stlink_t *sl) { - int mode = sl->backend->current_mode(sl); - - switch (mode) { - case STLINK_DEV_DFU_MODE: - DLOG("stlink current mode: dfu\n"); - return (mode); - case STLINK_DEV_DEBUG_MODE: - DLOG("stlink current mode: debug (jtag or swd)\n"); - return (mode); - case STLINK_DEV_MASS_MODE: - DLOG("stlink current mode: mass\n"); - return (mode); - } - - DLOG("stlink mode: unknown!\n"); - return (STLINK_DEV_UNKNOWN_MODE); -} - -int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { - DLOG("*** stlink_trace_enable ***\n"); - return (sl->backend->trace_enable(sl, frequency)); -} - -int stlink_trace_disable(stlink_t *sl) { - DLOG("*** stlink_trace_disable ***\n"); - return (sl->backend->trace_disable(sl)); -} - -int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { - return (sl->backend->trace_read(sl, buf, size)); -} - -// End of delegates.... Common code below here... - -// same as above with entrypoint. - -void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { - stlink_write_reg(sl, addr, 15); /* pc register */ - stlink_run(sl, RUN_NORMAL); - - while (stlink_is_core_halted(sl)) { - usleep(3000000); - } -} - -// this function is called by stlink_status() -// do not call stlink_core_stat() directly, always use stlink_status() -void stlink_core_stat(stlink_t *sl) { - switch (sl->core_stat) { - case TARGET_RUNNING: - DLOG(" core status: running\n"); - return; - case TARGET_HALTED: - DLOG(" core status: halted\n"); - return; - case TARGET_RESET: - DLOG(" core status: reset\n"); - return; - case TARGET_DEBUG_RUNNING: - DLOG(" core status: debug running\n"); - return; - default: - DLOG(" core status: unknown\n"); - } -} - -void stlink_print_data(stlink_t *sl) { - if (sl->q_len <= 0 || sl->verbose < UDEBUG) { - return; - } - - if (sl->verbose > 2) { - DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); - } - - for (int i = 0; i < sl->q_len; i++) { - if (i % 16 == 0) { - /* - if (sl->q_data_dir == Q_DATA_OUT) { - fprintf(stdout, "\n<- 0x%08x ", sl->q_addr + i); - } else { - fprintf(stdout, "\n-> 0x%08x ", sl->q_addr + i); - } - */ - } - // DLOG(" %02x", (unsigned int) sl->q_buf[i]); - fprintf(stderr, " %02x", (unsigned int)sl->q_buf[i]); - } - // DLOG("\n\n"); - fprintf(stderr, "\n"); -} - -/* Memory mapped file */ -typedef struct mapped_file { - uint8_t *base; - size_t len; -} mapped_file_t; - -#define MAPPED_FILE_INITIALIZER \ - { NULL, 0 } - -static int map_file(mapped_file_t *mf, const char *path) { - int error = -1; - struct stat st; - - const int fd = open(path, O_RDONLY | O_BINARY); - - if (fd == -1) { - fprintf(stderr, "open(%s) == -1\n", path); - return (-1); - } - - if (fstat(fd, &st) == -1) { - fprintf(stderr, "fstat(%s) == -1\n", path); - goto on_error; - } - - if (sizeof(st.st_size) != sizeof(size_t)) { - // on 32 bit systems, check if there is an overflow - if (st.st_size > (off_t)SSIZE_MAX) { - fprintf(stderr, "mmap() size_t overflow for file %s\n", path); - goto on_error; - } - } - - mf->base = - (uint8_t *)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); - - if (mf->base == MAP_FAILED) { - fprintf(stderr, "mmap() == MAP_FAILED for file %s\n", path); - goto on_error; - } - - mf->len = (size_t)st.st_size; - error = 0; // success - -on_error: - close(fd); - return (error); -} - -static void unmap_file(mapped_file_t *mf) { - munmap((void *)mf->base, mf->len); - mf->base = (unsigned char *)MAP_FAILED; - mf->len = 0; -} - -/* Limit the block size to compare to 0x1800 as anything larger will stall the - * STLINK2 Maybe STLINK V1 needs smaller value! - */ -static int check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { - size_t off; - size_t n_cmp = sl->flash_pgsz; - - if (n_cmp > 0x1800) { - n_cmp = 0x1800; - } - - for (off = 0; off < mf->len; off += n_cmp) { - size_t aligned_size; - - size_t cmp_size = n_cmp; // adjust last page size - - if ((off + n_cmp) > mf->len) { - cmp_size = mf->len - off; - } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { - aligned_size = (cmp_size + 4) & ~(4 - 1); - } - - stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - - if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { - return (-1); - } - } - - return (0); -} - -static void md5_calculate(mapped_file_t *mf) { - // calculate md5 checksum of given binary file - Md5Context md5Context; - MD5_HASH md5Hash; - Md5Initialise(&md5Context); - Md5Update(&md5Context, mf->base, (uint32_t)mf->len); - Md5Finalise(&md5Context, &md5Hash); - printf("md5 checksum: "); - - for (int i = 0; i < (int)sizeof(md5Hash); i++) { - printf("%x", md5Hash.bytes[i]); - } - - printf(", "); -} - -static void stlink_checksum(mapped_file_t *mp) { - /* checksum that backward compatible with official ST tools */ - uint32_t sum = 0; - uint8_t *mp_byte = (uint8_t *)mp->base; - - for (size_t i = 0; i < mp->len; ++i) { - sum += mp_byte[i]; - } - - printf("stlink checksum: 0x%08x\n", sum); -} - -static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { - unsigned int val; - // set PC to the reset routine - stlink_read_debug32(sl, addr + 4, &val); - stlink_write_reg(sl, val, 15); - stlink_run(sl, RUN_NORMAL); -} - -int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, - stm32_addr_t addr) { - // write the file in sram at addr - - int error = -1; - size_t off; - size_t len; - - // check addr range is inside the sram - if (addr < sl->sram_base) { - fprintf(stderr, "addr too low\n"); - goto on_error; - } else if ((addr + length) < addr) { - fprintf(stderr, "addr overruns\n"); - goto on_error; - } else if ((addr + length) > (sl->sram_base + sl->sram_size)) { - fprintf(stderr, "addr too high\n"); - goto on_error; - } else if (addr & 3) { - fprintf(stderr, "unaligned addr\n"); - goto on_error; - } - - len = length; - - if (len & 3) { - len -= len & 3; - } - - // do the copy by 1kB blocks - for (off = 0; off < len; off += 1024) { - size_t size = 1024; - - if ((off + size) > len) { - size = len - off; - } - - memcpy(sl->q_buf, data + off, size); - - if (size & 3) { - size += 2; - } // round size if needed - - stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); - } - - if (length > len) { - memcpy(sl->q_buf, data + len, length - len); - stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(length - len)); - } - - error = 0; // success - stlink_fwrite_finalize(sl, addr); - -on_error: - return (error); -} - -int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { - // write the file in sram at addr - - int error = -1; - size_t off; - size_t len; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - fprintf(stderr, "map_file() == -1\n"); - return (-1); - } - - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); - - // check if addr range is inside the SRAM - if (addr < sl->sram_base) { - fprintf(stderr, "addr too low\n"); - goto on_error; - } else if ((addr + mf.len) < addr) { - fprintf(stderr, "addr overruns\n"); - goto on_error; - } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { - fprintf(stderr, "addr too high\n"); - goto on_error; - } else if (addr & 3) { - fprintf(stderr, "unaligned addr\n"); - goto on_error; - } - - len = mf.len; - - if (len & 3) { - len -= len & 3; - } - - // do the copy by 1kB blocks - for (off = 0; off < len; off += 1024) { - size_t size = 1024; - - if ((off + size) > len) { - size = len - off; - } - - memcpy(sl->q_buf, mf.base + off, size); - - if (size & 3) { - size += 2; - } // round size if needed - - stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); - } - - if (mf.len > len) { - memcpy(sl->q_buf, mf.base + len, mf.len - len); - stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(mf.len - len)); - } - - // check the file has been written - if (check_file(sl, &mf, addr) == -1) { - fprintf(stderr, "check_file() == -1\n"); - goto on_error; - } - - error = 0; // success - stlink_fwrite_finalize(sl, addr); - -on_error: - unmap_file(&mf); - return (error); -} - -typedef bool (*save_block_fn)(void *arg, uint8_t *block, ssize_t len); - -static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, - save_block_fn fn, void *fn_arg) { - - int error = -1; - - if (size < 1) { - size = sl->flash_size; - } - - if (size > sl->flash_size) { - size = sl->flash_size; - } - - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - - for (size_t off = 0; off < size; off += cmp_size) { - size_t aligned_size; - - // adjust last page size - if ((off + cmp_size) > size) { - cmp_size = size - off; - } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { - aligned_size = (cmp_size + 4) & ~(4 - 1); - } - - stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - - if (!fn(fn_arg, sl->q_buf, aligned_size)) { - goto on_error; - } - } - - error = 0; // success - -on_error: - return (error); -} - -struct stlink_fread_worker_arg { - int fd; -}; - -static bool stlink_fread_worker(void *arg, uint8_t *block, ssize_t len) { - struct stlink_fread_worker_arg *the_arg = - (struct stlink_fread_worker_arg *)arg; - - if (write(the_arg->fd, block, len) != len) { - fprintf(stderr, "write() != aligned_size\n"); - return (false); - } else { - return (true); - } -} - -struct stlink_fread_ihex_worker_arg { - FILE *file; - uint32_t addr; - uint32_t lba; - uint8_t buf[16]; - uint8_t buf_pos; -}; - -static bool -stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { - uint32_t addr = the_arg->addr; - uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + - (uint8_t)((addr & 0x00FF0000) >> 16); - - if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", - (addr & 0xFFFF0000) >> 16, (uint8_t)(0x100 - sum))) { - return (false); - } - - the_arg->lba = (addr & 0xFFFF0000); - return (true); -} - -static bool -stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { - uint8_t count = the_arg->buf_pos; - - if (count == 0) { - return (true); - } - - uint32_t addr = the_arg->addr; - - if (the_arg->lba != (addr & 0xFFFF0000)) { // segment changed - if (!stlink_fread_ihex_newsegment(the_arg)) { - return (false); - } - } - - uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + - (uint8_t)(addr & 0x000000FF); - - if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) { - return (false); - } - - for (uint8_t i = 0; i < count; ++i) { - uint8_t b = the_arg->buf[i]; - sum += b; - - if (2 != fprintf(the_arg->file, "%02X", b)) { - return (false); - } - } - - if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) { - return (false); - } - - the_arg->addr += count; - the_arg->buf_pos = 0; - - return (true); -} - -static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *the_arg, - int fd, stm32_addr_t addr) { - the_arg->file = fdopen(fd, "w"); - the_arg->addr = addr; - the_arg->lba = 0; - the_arg->buf_pos = 0; - - return (the_arg->file != NULL); -} - -static bool stlink_fread_ihex_worker(void *arg, uint8_t *block, ssize_t len) { - struct stlink_fread_ihex_worker_arg *the_arg = - (struct stlink_fread_ihex_worker_arg *)arg; - - for (ssize_t i = 0; i < len; ++i) { - if (the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full - if (!stlink_fread_ihex_writeline(the_arg)) { - return (false); - } - } - - the_arg->buf[the_arg->buf_pos++] = block[i]; - } - - return (true); -} - -static bool -stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { - if (!stlink_fread_ihex_writeline(the_arg)) { - return (false); - } - - // FIXME: do we need the Start Linear Address? - - if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) { // EoF - return (false); - } - - return (0 == fclose(the_arg->file)); -} - -int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, - stm32_addr_t addr, size_t size) { - // read size bytes from addr to file - ILOG("read from address %#010x size %u\n", addr, (unsigned)size); - - int error; - int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); - - if (fd == -1) { - fprintf(stderr, "open(%s) == -1\n", path); - return (-1); - } - - if (is_ihex) { - struct stlink_fread_ihex_worker_arg arg; - - if (stlink_fread_ihex_init(&arg, fd, addr)) { - error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); - - if (!stlink_fread_ihex_finalize(&arg)) { - error = -1; - } - } else { - error = -1; - } - } else { - struct stlink_fread_worker_arg arg = {fd}; - error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); - } - - close(fd); - return (error); -} - -int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, - size_t size) { - // write the buffer right after the loader - int ret = 0; - size_t chunk = size & ~0x3; - size_t rem = size & 0x3; - - if (chunk) { - memcpy(sl->q_buf, buf, chunk); - ret = stlink_write_mem32(sl, fl->buf_addr, (uint16_t)chunk); - } - - if (rem && !ret) { - memcpy(sl->q_buf, buf + chunk, rem); - ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, (uint16_t)rem); - } - - return (ret); -} - -uint32_t calculate_F4_sectornum(uint32_t flashaddr) { - uint32_t offset = 0; - flashaddr &= ~STM32_FLASH_BASE; // page now holding the actual flash address - - if (flashaddr >= 0x100000) { - offset = 12; - flashaddr -= 0x100000; - } - - if (flashaddr < 0x4000) { - return (offset + 0); - } else if (flashaddr < 0x8000) { - return (offset + 1); - } else if (flashaddr < 0xc000) { - return (offset + 2); - } else if (flashaddr < 0x10000) { - return (offset + 3); - } else if (flashaddr < 0x20000) { - return (offset + 4); - } else { - return (offset + (flashaddr / 0x20000) + 4); - } -} - -uint32_t calculate_F7_sectornum(uint32_t flashaddr) { - flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address - - if (flashaddr < 0x20000) { - return (flashaddr / 0x8000); - } else if (flashaddr < 0x40000) { - return (4); - } else { - return ((flashaddr / 0x40000) + 4); - } -} - -uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, - unsigned bank) { - flashaddr &= - ~((bank == BANK_1) - ? STM32_FLASH_BASE - : STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address - return (flashaddr / sl->flash_pgsz); -} - -// returns BKER:PNB for the given page address -uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { - uint32_t bker = 0; - uint32_t flashopt; - stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); - flashaddr -= STM32_FLASH_BASE; - - if (sl->chip_id == STM32_CHIPID_L4 || - sl->chip_id == STM32_CHIPID_L496x_L4A6x || - sl->chip_id == STM32_CHIPID_L4Rx) { - // this chip use dual banked flash - if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { - uint32_t banksize = (uint32_t)sl->flash_size / 2; - - if (flashaddr >= banksize) { - flashaddr -= banksize; - bker = 0x100; - } - } - } - - // For 1MB chips without the dual-bank option set, the page address will - // overflow into the BKER bit, which gives us the correct bank:page value. - return (bker | flashaddr / (uint32_t)sl->flash_pgsz); -} - -uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { - if ((sl->chip_id == STM32_CHIPID_F2) || - (sl->chip_id == STM32_CHIPID_F4) || - (sl->chip_id == STM32_CHIPID_F4_DE) || - (sl->chip_id == STM32_CHIPID_F4_LP) || - (sl->chip_id == STM32_CHIPID_F4_HD) || - (sl->chip_id == STM32_CHIPID_F411xx) || - (sl->chip_id == STM32_CHIPID_F446) || - (sl->chip_id == STM32_CHIPID_F4_DSI) || - (sl->chip_id == STM32_CHIPID_F72xxx) || - (sl->chip_id == STM32_CHIPID_F412)) { - uint32_t sector = calculate_F4_sectornum(flashaddr); - - if (sector >= 12) { - sector -= 12; - } - - if (sector < 4) { - sl->flash_pgsz = 0x4000; - } else if (sector < 5) { - sl->flash_pgsz = 0x10000; - } else { - sl->flash_pgsz = 0x20000; - } - } else if (sl->chip_id == STM32_CHIPID_F7 || - sl->chip_id == STM32_CHIPID_F76xxx) { - uint32_t sector = calculate_F7_sectornum(flashaddr); - - if (sector < 4) { - sl->flash_pgsz = 0x8000; - } else if (sector < 5) { - sl->flash_pgsz = 0x20000; - } else { - sl->flash_pgsz = 0x40000; - } - } - - return ((uint32_t)sl->flash_pgsz); -} - -/** - * Erase a page of flash, assumes sl is fully populated with things like - * chip/core ids - * @param sl stlink context - * @param flashaddr an address in the flash page to erase - * @return 0 on success -ve on failure - */ -int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - // wait for ongoing op to finish - wait_flash_busy(sl); - // clear flash IO errors - clear_flash_error(sl); - - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4 || - sl->flash_type == STM32_FLASH_TYPE_F7 || - sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - // unlock if locked - unlock_flash_if(sl); - - // select the page to erase - if ((sl->chip_id == STM32_CHIPID_L4) || - (sl->chip_id == STM32_CHIPID_L43x_L44x) || - (sl->chip_id == STM32_CHIPID_L45x_L46x) || - (sl->chip_id == STM32_CHIPID_L496x_L4A6x) || - (sl->chip_id == STM32_CHIPID_L4Rx)) { - // calculate the actual bank+page from the address - uint32_t page = calculate_L4_page(sl, flashaddr); - - fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, - stlink_calculate_pagesize(sl, flashaddr)); - - write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STM32_CHIPID_F7 || - sl->chip_id == STM32_CHIPID_F76xxx) { - // calculate the actual page from the address - uint32_t sector = calculate_F7_sectornum(flashaddr); - - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, - stlink_calculate_pagesize(sl, flashaddr)); - write_flash_cr_snb(sl, sector, BANK_1); - } else { - // calculate the actual page from the address - uint32_t sector = calculate_F4_sectornum(flashaddr); - - fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, - stlink_calculate_pagesize(sl, flashaddr)); - - // the SNB values for flash sectors in the second bank do not directly - // follow the values for the first bank on 2mb devices... - if (sector >= 12) { - sector += 4; - } - - write_flash_cr_snb(sl, sector, BANK_1); - } - - set_flash_cr_strt(sl, BANK_1); // start erase operation - wait_flash_busy(sl); // wait for completion - lock_flash(sl); // TODO: fails to program if this is in -#if DEBUG_FLASH - fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); -#endif - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // check if the locks are set - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if ((val & (1 << 0)) || (val & (1 << 1))) { - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY2); - - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if (val & (1 << 0)) { - WLOG("pecr.pelock not clear (%#x)\n", val); - return (-1); - } - - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY2); - - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - - if (val & (1 << 1)) { - WLOG("pecr.prglock not clear (%#x)\n", val); - return (-1); - } - } - - // set pecr.{erase,prog} - val |= (1 << 9) | (1 << 3); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - // write 0 to the first word of the page to be erased - stlink_write_debug32(sl, flashaddr, 0); - - /* MP: It is better to wait for clearing the busy bit after issuing page - * erase command, even though PM0062 recommends to wait before it. - * Test shows that a few iterations is performed in the following loop - * before busy bit is cleared. - */ - wait_flash_busy(sl); - - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - uint32_t val; - unlock_flash_if(sl); - set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit - - // set the page to erase - if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - - // sec 3.10.5 - PNB[7:0] is offset by 3. - val &= ~(0xFF << 3); // Clear previously set page number (if any) - val |= ((flash_page & 0xFF) << 3); - - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - } else if (sl->flash_type == STM32_FLASH_TYPE_G0) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. - val &= ~(0x3F << 3); - val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } else if (sl->flash_type == STM32_FLASH_TYPE_G4) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. - val &= ~(0x7F << 3); - val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } - - set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit - wait_flash_busy(sl); // wait for the 'busy' bit to clear - clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit - lock_flash(sl); - } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || - sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; - unlock_flash_if(sl); - clear_flash_cr_pg(sl, bank); // clear the pg bit - set_flash_cr_per(sl, bank); // set the page erase bit - write_flash_ar(sl, flashaddr, bank); // select the page to erase - set_flash_cr_strt(sl, - bank); // start erase operation, reset by hw with busy bit - wait_flash_busy(sl); - clear_flash_cr_per(sl, bank); // clear the page erase bit - lock_flash(sl); - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; - unlock_flash_if(sl); // unlock if locked - uint32_t sector = calculate_H7_sectornum( - sl, flashaddr, bank); // calculate the actual page from the address - write_flash_cr_snb(sl, sector, bank); // select the page to erase - set_flash_cr_strt(sl, bank); // start erase operation - wait_flash_busy(sl); // wait for completion - lock_flash(sl); - } else { - WLOG("unknown coreid %x, page erase failed\n", sl->core_id); - return (-1); - } - - return check_flash_error(sl); -} - -// Check if an address and size are within the flash -int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { - if (addr < sl->flash_base || addr >= (sl->flash_base + sl->flash_size)) { - ELOG("Invalid address, it should be within 0x%08x - 0x%08lx\n", sl->flash_base, (sl->flash_base + sl->flash_size -1)); - return (-1); - } - if ((addr + size) > (sl->flash_base + sl->flash_size)) { - ELOG("The size exceeds the size of the flash (0x%08lx bytes available)\n", (sl->flash_base + sl->flash_size - addr)); - return (-1); - } - return 0; -} - -// Check if an address is aligned with the beginning of a page -int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { - stm32_addr_t page = sl->flash_base; - - while (page < addr) { - page += stlink_calculate_pagesize(sl, page); - } - - if (page != addr) { - return -1; - } - - return 0; -} - -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { - // Check the address and size validity - if (stlink_check_address_range_validity(sl, base_addr, size) < 0) { - return -1; - } - - // Make sure the requested address is aligned with the beginning of a page - if (stlink_check_address_alignment(sl, base_addr) < 0) { - ELOG("The address to erase is not aligned with the beginning of a page\n"); - return -1; - } - - stm32_addr_t addr = base_addr; - do { - size_t page_size = stlink_calculate_pagesize(sl, addr); - - // Check if size is aligned with a page, unless we want to completely erase the last page - if ((addr + page_size) > (base_addr + size) && !align_size) { - ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); - return -1; - } - - if (stlink_erase_flash_page(sl, addr)) { - WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); - return (-1); - } - - fprintf(stdout, "-> Flash page at %#x erased (size: %#lx)\n", addr, page_size); - fflush(stdout); - - // check the next page is within the range to erase - addr += page_size; - } while (addr < (base_addr + size)); - - fprintf(stdout, "\n"); - return 0; -} - -int stlink_erase_flash_mass(stlink_t *sl) { - int err = 0; - - // TODO: User MER bit to mass-erase WB series. - if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || - sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - - err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); - - } else { - wait_flash_busy(sl); - clear_flash_error(sl); - unlock_flash_if(sl); - - if (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_id != STM32_CHIPID_H7Ax) { - // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); - } - } - - set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit - set_flash_cr_strt( - sl, BANK_1); // start erase operation, reset by hw with busy bit - - if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || - (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 - set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 - } - - wait_flash_busy_progress(sl); - lock_flash(sl); - - // reset the mass erase bit - set_flash_cr_mer(sl, 0, BANK_1); - if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || - (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { - set_flash_cr_mer(sl, 0, BANK_2); - } - - err = check_flash_error(sl); - } - - return (err); -} - -int stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { - // check the contents of path are at addr - - int res; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - return (-1); - } - - res = check_file(sl, &mf, addr); - unmap_file(&mf); - return (res); -} - -/** - * Verify addr..addr+len is binary identical to base...base+len - * @param sl stlink context - * @param address stm device address - * @param data host side buffer to check against - * @param length how much - * @return 0 for success, -ve for failure - */ -int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, - unsigned length) { - size_t off; - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - ILOG("Starting verification of write complete\n"); - - for (off = 0; off < length; off += cmp_size) { - size_t aligned_size; - - // adjust last page size - if ((off + cmp_size) > length) { - cmp_size = length - off; - } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { - aligned_size = (cmp_size + 4) & ~(4 - 1); - } - - stlink_read_mem32(sl, address + (uint32_t)off, (uint16_t)aligned_size); - - if (memcmp(sl->q_buf, data + off, cmp_size)) { - ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); - return (-1); - } - } - - ILOG("Flash written and verified! jolly good!\n"); - return (0); -} - -int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len, uint32_t pagesize) { - unsigned int count, off; - unsigned int num_half_pages = len / pagesize; - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - flash_loader_t fl; - bool use_loader = true; - int ret = 0; - - // enable half page write - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - val |= (1 << FLASH_L1_PROG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - wait_flash_busy(sl); - - for (count = 0; count < num_half_pages; count++) { - if (use_loader) { - ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, - base + count * pagesize, pagesize); - if (ret && count == 0) { - /* It seems that stm32lx devices have a problem when it is blank */ - WLOG("Failed to use flash loader, fallback to soft write\n"); - use_loader = false; - } - } - if (!use_loader) { - ret = 0; - for (off = 0; off < pagesize && !ret; off += 64) { - size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; - memcpy(sl->q_buf, base + count * pagesize + off, chunk); - ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); - } - } - - if (ret) { - WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", - addr + count * pagesize); - break; - } - - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading - fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); - fflush(stdout); - } - - // wait for sr.busy to be cleared - wait_flash_busy(sl); - } - - // disable half page write - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return (ret); -} - -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - // disable DMA - set_dma_state(sl, fl, 0); - - // wait for ongoing op to finish - wait_flash_busy(sl); - // Clear errors - clear_flash_error(sl); - - if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { - ILOG("Starting Flash write for F2/F4/F7/L4\n"); - - // Flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return (-1); - } - - unlock_flash_if(sl); // first unlock the cr - - int voltage; - if (sl->version.stlink_v == 1) { - WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); - voltage = 3200; - } else { - voltage = stlink_target_voltage(sl); - } - - if (voltage == -1) { - ELOG("Failed to read Target voltage\n"); - return (-1); - } - - if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { - // L4 does not have a byte-write mode - if (voltage < 1710) { - ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); - return (-1); - } - } else { - if (voltage > 2700) { - ILOG("enabling 32-bit flash writes\n"); - write_flash_cr_psiz(sl, 2, BANK_1); - } else { - ILOG("Target voltage (%d mV) too low for 32-bit flash, " - "using 8-bit flash writes\n", - voltage); - write_flash_cr_psiz(sl, 0, BANK_1); - } - } - - // set programming mode - set_flash_cr_pg(sl, BANK_1); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - ILOG("Starting Flash write for WB/G0/G4\n"); - - unlock_flash_if(sl); // unlock flash if necessary - set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - ILOG("Starting Flash write for L0\n"); - - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY2); - - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 0)) { - ELOG("pecr.pelock not clear\n"); - return (-1); - } - - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY2); - - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 1)) { - ELOG("pecr.prglock not clear\n"); - return (-1); - } - - /* Flash loader initialisation */ - if (stlink_flash_loader_init(sl, fl) == -1) { - // L0/L1 have fallback to soft write - WLOG("stlink_flash_loader_init() == -1\n"); - } - } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); - - // flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return (-1); - } - - // unlock flash - unlock_flash_if(sl); - - // set programming mode - set_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - set_flash_cr_pg(sl, BANK_2); - } - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - ILOG("Starting Flash write for H7\n"); - - unlock_flash_if(sl); // unlock the cr - set_flash_cr_pg(sl, BANK_1); // set programming mode - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - set_flash_cr_pg(sl, BANK_2); - } - if (sl->chip_id != STM32_CHIPID_H7Ax) { - // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); - } - } - } else { - ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); - return (-1); - } - - return (0); -} - -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, - stm32_addr_t addr, uint8_t *base, uint32_t len) { - size_t off; - if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { - size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; - for (off = 0; off < len;) { - size_t size = len - off > buf_size ? buf_size : len - off; - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); - check_flash_error(sl); - return (-1); - } - - off += size; - } - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - for (off = 0; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } - - write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - fprintf(stdout, "\n"); - - // flash writes happen as 2 words at a time - if ((off / sizeof(uint32_t)) % 2 != 0) { - stlink_write_debug32(sl, addr + (uint32_t)off, - 0); // write a single word of zeros - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? - L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; - - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - - off = 0; - - if (len > pagesize) { - if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { - return (-1); - } else { - off = (size_t)(len / pagesize) * pagesize; - } - } - - // write remaining word in program memory - for (; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } - - write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); - - // wait for sr.busy to be cleared - do { - stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - } while ((val & (1 << 0)) != 0); - - // TODO: check redo write operation - } - fprintf(stdout, "\n"); - } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - int write_block_count = 0; - for (off = 0; off < len; off += sl->flash_pgsz) { - // adjust last write size - size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; - - // unlock and set programming mode - unlock_flash_if(sl); - - DLOG("Finished unlocking flash, running loader!\n"); - - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); - check_flash_error(sl); - return (-1); - } - - lock_flash(sl); - - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading - fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, - (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - for (off = 0; off < len;) { - // Program STM32H7x with 64-byte Flash words - size_t chunk = (len - off > 64) ? 64 : len - off; - memcpy(sl->q_buf, base + off, chunk); - stlink_write_mem32(sl, addr + (uint32_t)off, 64); - wait_flash_busy(sl); - - off += chunk; - - if (sl->verbose >= 1) { - // show progress - fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, - (unsigned int)len); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } - } else { - return (-1); - } - - return check_flash_error(sl); -} - -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { - uint32_t dhcsr; - - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || - (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) || - (sl->flash_type == STM32_FLASH_TYPE_WB_WL) || - (sl->flash_type == STM32_FLASH_TYPE_G0) || - (sl->flash_type == STM32_FLASH_TYPE_G4) || - (sl->flash_type == STM32_FLASH_TYPE_H7)) { - - clear_flash_cr_pg(sl, BANK_1); - if ((sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || - sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - clear_flash_cr_pg(sl, BANK_2); - } - lock_flash(sl); - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } - - // enable interrupt - if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); - } - - // restore DMA state - set_dma_state(sl, fl, 1); - - return (0); -} - -int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len, uint8_t eraseonly) { - int ret; - flash_loader_t fl; - ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, - len, addr, addr); - // check addr range is inside the flash - stlink_calculate_pagesize(sl, addr); - - // Check the address and size validity - if (stlink_check_address_range_validity(sl, addr, len) < 0) { - return (-1); - } else if (len & 1) { - WLOG("unaligned len 0x%x -- padding with zero\n", len); - len += 1; - } else if (stlink_check_address_alignment(sl, addr) < 0) { - ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " - "check page start address and compare with flash module organisation " - "in related ST reference manual of your device.\n", - (unsigned)(sl->flash_pgsz)); - return (-1); - } - - // make sure we've loaded the context with the chip details - stlink_core_id(sl); - - // Erase this section of the flash - if (stlink_erase_flash_section(sl, addr, len, true) < 0) { - ELOG("Failed to erase the flash prior to writing\n"); - return (-1); - } - - if (eraseonly) { - return (0); - } - - ret = stlink_flashloader_start(sl, &fl); - if (ret) - return ret; - ret = stlink_flashloader_write(sl, &fl, addr, base, len); - if (ret) - return ret; - ret = stlink_flashloader_stop(sl, &fl); - if (ret) - return ret; - - return (stlink_verify_write_flash(sl, addr, base, len)); -} - -// TODO: length not checked -static uint8_t stlink_parse_hex(const char *hex) { - uint8_t d[2]; - - for (int i = 0; i < 2; ++i) { - char c = *(hex + i); - - if (c >= '0' && c <= '9') { - d[i] = c - '0'; - } else if (c >= 'A' && c <= 'F') { - d[i] = c - 'A' + 10; - } else if (c >= 'a' && c <= 'f') { - d[i] = c - 'a' + 10; - } else { - return (0); // error - } - } - - return ((d[0] << 4) | (d[1])); -} - -int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, - size_t *size, uint32_t *begin) { - int res = 0; - *begin = UINT32_MAX; - uint8_t *data = NULL; - uint32_t end = 0; - bool eof_found = false; - - for (int scan = 0; (res == 0) && (scan < 2); ++scan) { - // parse file two times - first to find memory range, second - to fill it - if (scan == 1) { - if (!eof_found) { - ELOG("No EoF recond\n"); - res = -1; - break; - } - - if (*begin >= end) { - ELOG("No data found in file\n"); - res = -1; - break; - } - - *size = (end - *begin) + 1; - data = calloc(*size, 1); // use calloc to get NULL if out of memory - - if (!data) { - ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); - res = -1; - break; - } - - memset(data, erased_pattern, *size); - } - - FILE *file = fopen(path, "r"); - - if (!file) { - ELOG("Cannot open file\n"); - res = -1; - break; - } - - uint32_t lba = 0; - char line[1 + 5 * 2 + 255 * 2 + 2]; - - while (fgets(line, sizeof(line), file)) { - if (line[0] == '\n' || line[0] == '\r') { - continue; - } // skip empty lines - - if (line[0] != ':') { // no marker - wrong file format - ELOG("Wrong file format - no marker\n"); - res = -1; - break; - } - - size_t l = strlen(line); - - while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { - --l; - } // trim EoL - - if ((l < 11) || - (l == - (sizeof(line) - 1))) { // line too short or long - wrong file format - ELOG("Wrong file format - wrong line length\n"); - res = -1; - break; - } - - uint8_t chksum = 0; // check sum - - for (size_t i = 1; i < l; i += 2) { - chksum += stlink_parse_hex(line + i); - } - - if (chksum != 0) { - ELOG("Wrong file format - checksum mismatch\n"); - res = -1; - break; - } - - uint8_t reclen = stlink_parse_hex(line + 1); - - if (((uint32_t)reclen + 5) * 2 + 1 != l) { - ELOG("Wrong file format - record length mismatch\n"); - res = -1; - break; - } - - uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | - ((uint16_t)stlink_parse_hex(line + 5)); - uint8_t rectype = stlink_parse_hex(line + 7); - - switch (rectype) { - case 0: /* Data */ - if (scan == 0) { - uint32_t b = lba + offset; - uint32_t e = b + reclen - 1; - - if (b < *begin) { - *begin = b; - } - - if (e > end) { - end = e; - } - } else { - for (uint8_t i = 0; i < reclen; ++i) { - uint8_t b = stlink_parse_hex(line + 9 + i * 2); - uint32_t addr = lba + offset + i; - - if (addr >= *begin && addr <= end) { - data[addr - *begin] = b; - } - } - } - break; - case 1: /* EoF */ - eof_found = true; - break; - case 2: /* Extended Segment Address, unexpected */ - res = -1; - break; - case 3: /* Start Segment Address, unexpected */ - res = -1; - break; - case 4: /* Extended Linear Address */ - if (reclen == 2) { - lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | - ((uint32_t)stlink_parse_hex(line + 11) << 16); - } else { - ELOG("Wrong file format - wrong LBA length\n"); - res = -1; - } - break; - case 5: /* Start Linear Address - expected, but ignore */ - break; - default: - ELOG("Wrong file format - unexpected record type %d\n", rectype); - res = -1; - } - - if (res != 0) { - break; - } - } - - fclose(file); - } - - if (res == 0) { - *mem = data; - } else { - free(data); - } - - return (res); -} - -uint8_t stlink_get_erased_pattern(stlink_t *sl) { - if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - return (0x00); - } else { - return (0xff); - } -} - -int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, - stm32_addr_t addr) { - /* Write the block in flash at addr */ - int err; - unsigned int num_empty, idx; - uint8_t erased_pattern = stlink_get_erased_pattern(sl); - - /* - * This optimisation may cause unexpected garbage data remaining. - * Therfore it is turned off by default. - */ - if (sl->opt) { - idx = (unsigned int)length; - - for (num_empty = 0; num_empty != length; ++num_empty) - if (data[--idx] != erased_pattern) { - break; - } - - num_empty -= (num_empty & 3); // Round down to words - - if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, - erased_pattern); - } - } else { - num_empty = 0; - } - - /* - * TODO: investigate a kind of weird behaviour here: - * If the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed. - */ - err = stlink_write_flash(sl, addr, data, - (num_empty == length) ? (uint32_t)length - : (uint32_t)length - num_empty, - num_empty == length); - stlink_fwrite_finalize(sl, addr); - return (err); -} - -/** - * Write the given binary file into flash at address "addr" - * @param sl - * @param path readable file path, should be binary image - * @param addr where to start writing - * @return 0 on success, -ve on failure. - */ -int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { - /* Write the file in flash at addr */ - int err; - unsigned int num_empty, idx; - uint8_t erased_pattern = stlink_get_erased_pattern(sl); - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); - return (-1); - } - - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); - - if (sl->opt) { - idx = (unsigned int)mf.len; - - for (num_empty = 0; num_empty != mf.len; ++num_empty) { - if (mf.base[--idx] != erased_pattern) { - break; - } - } - - num_empty -= (num_empty & 3); // round down to words - - if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, - erased_pattern); - } - } else { - num_empty = 0; - } - - /* - * TODO: investigate a kind of weird behaviour here: - * If the file is identified to be all-empty and four-bytes aligned, - * still flash the whole file even if ignoring message is printed. - */ - err = stlink_write_flash(sl, addr, mf.base, - (num_empty == mf.len) ? (uint32_t)mf.len - : (uint32_t)mf.len - num_empty, - num_empty == mf.len); - stlink_fwrite_finalize(sl, addr); - unmap_file(&mf); - return (err); -} - -/** - * Write option bytes - * @param sl - * @param base option bytes to write - * @param addr of the memory mapped option bytes - * @param len of options bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_f0( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { - int ret = 0; - - if (len < 12 || addr != STM32_F0_OPTION_BYTES_BASE) { - WLOG("Only full write of option bytes area is supported\n"); - return -1; - } - - clear_flash_error(sl); - - WLOG("Erasing option bytes\n"); - - /* erase option bytes */ - stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_OPTWRE)); - ret = stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_STRT) | (1 << FLASH_CR_OPTWRE)); - if (ret) { - return ret; - } - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - if (ret) { - return ret; - } - - WLOG("Writing option bytes to %#10x\n", addr); - - /* Set the Option PG bit to enable programming */ - stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTPG) | (1 << FLASH_CR_OPTWRE)); - - /* Use flash loader for write OP - * because flash memory writable by half word */ - flash_loader_t fl; - ret = stlink_flash_loader_init(sl, &fl); - if (ret) { - return ret; - } - ret = stlink_flash_loader_run(sl, &fl, addr, base, len); - if (ret) { - return ret; - } - - /* Reload option bytes */ - stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OBL_LAUNCH)); - - return check_flash_error(sl); -} - -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - /* Write options bytes */ - uint32_t val; - int ret = 0; - (void)len; - uint32_t data; - - clear_flash_error(sl); - - write_uint32((unsigned char *)&data, *(uint32_t *)(base)); - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); - - // Set Options Start bit - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - - // Reload options - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - - return (ret); -} - -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t flash_base = get_stm32l0_flash_base(sl); - uint32_t val; - uint32_t data; - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - while (len != 0) { - write_uint32((unsigned char *)&data, - *(uint32_t *)(base)); // write options bytes - - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, addr, data); - wait_flash_busy(sl); - - if ((ret = check_flash_error(sl))) { - break; - } - - len -= 4; - addr += 4; - base += 4; - } - - // Reload options - stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); - val |= (1 << STM32L0_FLASH_OBL_LAUNCH); - stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); - - return (ret); -} - -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - - uint32_t val; - int ret = 0; - (void)addr; - (void)len; - - // Clear errors - clear_flash_error(sl); - - // write options bytes - uint32_t data; - write_uint32((unsigned char *)&data, *(uint32_t *)(base)); - WLOG("Writing option bytes 0x%04x\n", data); - stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); - - // set options start bit - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - - wait_flash_busy(sl); - ret = check_flash_error(sl); - - // apply options bytes immediate - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - - return (ret); -} - -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t option_byte; - int ret = 0; - (void)addr; - (void)len; - - // Clear errors - clear_flash_error(sl); - - write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); - - // write option byte, ensuring we dont lock opt, and set strt bit - stlink_write_debug32(sl, FLASH_F4_OPTCR, - (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | - (1 << FLASH_F4_OPTCR_START)); - - wait_flash_busy(sl); - ret = check_flash_error(sl); - - // option bytes are reloaded at reset only, no obl. */ - return (ret); -} - -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t option_byte; - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), - addr); - write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); - ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); - - if (addr == 0) { - addr = FLASH_F7_OPTCR; - ILOG("No address provided, using %#10x\n", addr); - } - - if (addr == FLASH_F7_OPTCR) { - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F7_OPTCR, - (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); - } else if (addr == FLASH_F7_OPTCR1) { - // Read FLASH_F7_OPTCR - uint32_t oldvalue; - stlink_read_debug32(sl, FLASH_F7_OPTCR, &oldvalue); - /* write option byte */ - stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_byte); - // Write FLASH_F7_OPTCR lock and start address - stlink_write_debug32(sl, FLASH_F7_OPTCR, - (oldvalue & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); - } else { - WLOG("WIP: write %#010x to address %#010x\n", option_byte, addr); - stlink_write_debug32(sl, addr, option_byte); - } - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, - addr); - - /* option bytes are reloaded at reset only, no obl. */ - - return ret; -} - -/** - * Write STM32H7xx option bytes - * @param sl - * @param base option bytes to write - * @param addr of the memory mapped option bytes - * @param len number of bytes to write (must be multiple of 4) - * @return 0 on success, -ve on failure. - */ -static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t val; - uint32_t data; - - // Wait until previous flash option has completed - wait_flash_busy(sl); - - // Clear previous error - stlink_write_debug32(sl, FLASH_H7_OPTCCR, - 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); - - while (len != 0) { - switch (addr) { - case FLASH_H7_REGS_ADDR + 0x20: // FLASH_OPTSR_PRG - case FLASH_H7_REGS_ADDR + 0x2c: // FLASH_PRAR_PRG1 - case FLASH_H7_REGS_ADDR + 0x34: // FLASH_SCAR_PRG1 - case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 - case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG - /* Write to FLASH_xxx_PRG registers */ - write_uint32((unsigned char *)&data, - *(uint32_t *)(base)); // write options bytes - - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - - /* Skip if the value in the CUR register is identical */ - stlink_read_debug32(sl, addr - 4, &val); - if (val == data) { + if (*begin >= end) { + ELOG("No data found in file\n"); + res = -1; break; } - /* Write new option byte values and start modification */ - stlink_write_debug32(sl, addr, data); - stlink_read_debug32(sl, FLASH_H7_OPTCR, &val); - val |= (1 << FLASH_H7_OPTCR_OPTSTART); - stlink_write_debug32(sl, FLASH_H7_OPTCR, val); - - /* Wait for the option bytes modification to complete */ - do { - stlink_read_debug32(sl, FLASH_H7_OPTSR_CUR, &val); - } while ((val & (1 << FLASH_H7_OPTSR_OPT_BUSY)) != 0); - - /* Check for errors */ - if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { - stlink_write_debug32(sl, FLASH_H7_OPTCCR, - 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); - return -1; + *size = (end - *begin) + 1; + data = calloc(*size, 1); // use calloc to get NULL if out of memory + + if (!data) { + ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); + res = -1; + break; } - break; - default: - /* Skip non-programmable registers */ - break; + memset(data, erased_pattern, *size); } - len -= 4; - addr += 4; - base += 4; - } - - return 0; -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_Gx(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_Gx(sl, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f2(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_f2(sl, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f4(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); -} + FILE *file = fopen(path, "r"); -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_f4(sl, option_byte); -} + if (!file) { + ELOG("Cannot open file\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f7(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); - return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); -} + uint32_t lba = 0; + char line[1 + 5 * 2 + 255 * 2 + 2]; -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f0(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); - return stlink_read_debug32(sl, FLASH_OBR, option_byte); -} + while (fgets(line, sizeof(line), file)) { + if (line[0] == '\n' || line[0] == '\r') { + continue; + } // skip empty lines -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register1_f7(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register 1 byte from %#10x\n", - FLASH_F7_OPTCR1); - return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); -} + if (line[0] != ':') { // no marker - wrong file format + ELOG("Wrong file format - no marker\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { - DLOG("@@@@ Read option byte boot address\n"); - return stlink_read_option_control_register1_f7(sl, option_byte); -} + size_t l = strlen(line); -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - * - * Since multiple bytes can be read, we read and print all but one here - * and then return the last one just like other devices - */ -int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { - int err = -1; - for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { - err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), - option_byte); - if (err == -1) { - return err; - } else { - printf("%08x\n", *option_byte); - } - } + while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { + --l; + } // trim EoL - return stlink_read_debug32( - sl, - sl->option_base + (uint32_t)(sl->option_size / 4 - 1) * sizeof(uint32_t), - option_byte); -} + if ((l < 11) || + (l == + (sizeof(line) - 1))) { // line too short or long - wrong file format + ELOG("Wrong file format - wrong line length\n"); + res = -1; + break; + } -/** - * Read first option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { - DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); - return stlink_read_debug32(sl, sl->option_base, option_byte); -} + uint8_t chksum = 0; // check sum -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -// int stlink_read_option_bytes_boot_add_generic(stlink_t *sl, uint32_t* -// option_byte) { -// DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); -// return stlink_read_debug32(sl, sl->option_base, option_byte); -//} + for (size_t i = 1; i < l; i += 2) { + chksum += stlink_parse_hex(line + i); + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -// int stlink_read_option_control_register_generic(stlink_t *sl, uint32_t* -// option_byte) { -// DLOG("@@@@ Read option control register byte from %#10x\n", -// sl->option_base); return stlink_read_debug32(sl, sl->option_base, -// option_byte); -//} + if (chksum != 0) { + ELOG("Wrong file format - checksum mismatch\n"); + res = -1; + break; + } -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -// int stlink_read_option_control_register1_generic(stlink_t *sl, uint32_t* -// option_byte) { -// DLOG("@@@@ Read option control register 1 byte from %#10x\n", -// sl->option_base); return stlink_read_debug32(sl, sl->option_base, -// option_byte); -//} + uint8_t reclen = stlink_parse_hex(line + 1); -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return (-1); - } + if (((uint32_t)reclen + 5) * 2 + 1 != l) { + ELOG("Wrong file format - record length mismatch\n"); + res = -1; + break; + } - switch (sl->chip_id) { - case STM32_CHIPID_F2: - return stlink_read_option_bytes_f2(sl, option_byte); - case STM32_CHIPID_F4: - case STM32_CHIPID_F446: - return stlink_read_option_bytes_f4(sl, option_byte); - case STM32_CHIPID_F76xxx: - return stlink_read_option_bytes_f7(sl, option_byte); - case STM32_CHIPID_G0_CAT1: - case STM32_CHIPID_G0_CAT2: - case STM32_CHIPID_G4_CAT2: - case STM32_CHIPID_G4_CAT3: - return stlink_read_option_bytes_Gx(sl, option_byte); - default: - return stlink_read_option_bytes_generic(sl, option_byte); - } -} + uint16_t offset = ((uint16_t)stlink_parse_hex(line + 3) << 8) | + ((uint16_t)stlink_parse_hex(line + 5)); + uint8_t rectype = stlink_parse_hex(line + 7); -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes boot address read is currently not supported for " - "connected chip\n"); - return -1; - } + switch (rectype) { + case 0: /* Data */ + if (scan == 0) { + uint32_t b = lba + offset; + uint32_t e = b + reclen - 1; - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F7: - return stlink_read_option_bytes_boot_add_f7(sl, option_byte); - default: - return -1; - // return stlink_read_option_bytes_boot_add_generic(sl, option_byte); - } -} + if (b < *begin) { + *begin = b; + } -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; - } + if (e > end) { + end = e; + } + } else { + for (uint8_t i = 0; i < reclen; ++i) { + uint8_t b = stlink_parse_hex(line + 9 + i * 2); + uint32_t addr = lba + offset + i; - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - return stlink_read_option_control_register_f0(sl, option_byte); - case STM32_FLASH_TYPE_F7: - return stlink_read_option_control_register_f7(sl, option_byte); - default: - return -1; - } -} + if (addr >= *begin && addr <= end) { + data[addr - *begin] = b; + } + } + } + break; + case 1: /* EoF */ + eof_found = true; + break; + case 2: /* Extended Segment Address, unexpected */ + res = -1; + break; + case 3: /* Start Segment Address, unexpected */ + res = -1; + break; + case 4: /* Extended Linear Address */ + if (reclen == 2) { + lba = ((uint32_t)stlink_parse_hex(line + 9) << 24) | + ((uint32_t)stlink_parse_hex(line + 11) << 16); + } else { + ELOG("Wrong file format - wrong LBA length\n"); + res = -1; + } + break; + case 5: /* Start Linear Address - expected, but ignore */ + break; + default: + ELOG("Wrong file format - unexpected record type %d\n", rectype); + res = -1; + } -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register1_32(stlink_t *sl, - uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; + if (res != 0) { + break; + } + } + + fclose(file); } - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F7: - return stlink_read_option_control_register1_f7(sl, option_byte); - default: - return -1; - // return stlink_read_option_control_register1_generic(sl, option_byte); + if (res == 0) { + *mem = data; + } else { + free(data); } + + return (res); } -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { - WLOG("About to write option byte %#10x to %#10x.\n", option_byte, - sl->option_base); - return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, - 4); +uint8_t stlink_get_erased_pattern(stlink_t *sl) { + if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + return (0x00); + } else { + return (0xff); + } } -/** - * Write option bytes - * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len) { - int ret = -1; +int stlink_target_connect(stlink_t *sl, enum connect_type connect) { + if (connect == CONNECT_UNDER_RESET) { + stlink_enter_swd_mode(sl); - if (sl->option_base == 0) { - ELOG( - "Option bytes writing is currently not supported for connected chip\n"); - return (-1); + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); + + // try to halt the core before reset + // this is useful if the NRST pin is not connected + sl->backend->force_debug(sl); + + // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) + usleep(20); + + stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); + + // try to halt the core after reset + unsigned timeout = time_ms() + 10; + while (time_ms() < timeout) { + sl->backend->force_debug(sl); + usleep(100); + } + + // check NRST connection + uint32_t dhcsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + WLOG("NRST is not connected\n"); + } + + // addition soft reset for halt before the first instruction + stlink_soft_reset(sl, 1 /* halt on reset */); } - if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { - ELOG("Option bytes start address out of Option bytes range\n"); - return (-1); + if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE && + stlink_enter_swd_mode(sl)) { + printf("Failed to enter SWD mode\n"); + return -1; } - if (addr + len > sl->option_base + sl->option_size) { - ELOG("Option bytes data too long\n"); - return (-1); + if (connect == CONNECT_NORMAL) { + stlink_reset(sl, RESET_AUTO); } - wait_flash_busy(sl); + return stlink_load_device_params(sl); +} - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return (-1); - } +// End of delegates.... functions below are private to this module +// same as above with entrypoint. - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return (-1); - } +static void stop_wdg_in_debug(stlink_t *sl) { + uint32_t dbgmcu_cr; + uint32_t set; + uint32_t value; switch (sl->flash_type) { case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: - ret = stlink_write_option_bytes_f0(sl, base, addr, len); + case STM32_FLASH_TYPE_G4: + dbgmcu_cr = STM32F0_DBGMCU_CR; + set = (1 << STM32F0_DBGMCU_CR_IWDG_STOP) | + (1 << STM32F0_DBGMCU_CR_WWDG_STOP); break; case STM32_FLASH_TYPE_F2_F4: - ret = stlink_write_option_bytes_f4(sl, base, addr, len); - break; case STM32_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_f7(sl, base, addr, len); - break; - case STM32_FLASH_TYPE_L0_L1: - ret = stlink_write_option_bytes_l0(sl, base, addr, len); - break; case STM32_FLASH_TYPE_L4_L4P: - ret = stlink_write_option_bytes_l4(sl, base, addr, len); + dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; + set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | + (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); break; + case STM32_FLASH_TYPE_L0_L1: case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - ret = stlink_write_option_bytes_gx(sl, base, addr, len); + dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; + set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | + (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); break; case STM32_FLASH_TYPE_H7: - ret = stlink_write_option_bytes_h7(sl, base, addr, len); + dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; + set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP); break; - default: - ELOG("Option bytes writing is currently not implemented for connected " - "chip\n"); + case STM32_FLASH_TYPE_WB_WL: + dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1; + set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) | + (1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP); break; + default: + return; } - if (ret) { - ELOG("Flash option write failed!\n"); - } else { - ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + if (!stlink_read_debug32(sl, dbgmcu_cr, &value)) { + stlink_write_debug32(sl, dbgmcu_cr, value | set); } +} - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); - - return ret; +int stlink_jtag_reset(stlink_t *sl, int value) { + DLOG("*** stlink_jtag_reset %d ***\n", value); + return (sl->backend->jtag_reset(sl, value)); } -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_control_register_f7(stlink_t *sl, - uint32_t option_control_register) { - int ret = 0; +int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { + int ret; + unsigned timeout; + uint32_t dhcsr, dfsr; + + DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); + + // halt core and enable debugging (if not already done) + // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_DEBUGEN); - // Clear errors - clear_flash_error(sl); + // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) + if (halt_on_reset) { + stlink_write_debug32( + sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); - ILOG("Asked to write option control register 1 %#10x to %#010x.\n", - option_control_register, FLASH_F7_OPTCR); + // clear VCATCH in the DFSR register + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); + } else { + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | + STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR); + } - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F7_OPTCR, - (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); + // clear S_RESET_ST in the DHCSR register + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - wait_flash_busy(sl); + // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) + ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, + STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ); + if (ret) { + ELOG("Soft reset failed: error write to AIRCR\n"); + return (ret); + } - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, - FLASH_F7_OPTCR); + // waiting for a reset within 500ms + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + timeout = time_ms() + 500; + while (time_ms() < timeout) { + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + if (halt_on_reset) { + // waiting halt by the SYSRESETREQ exception + // DDI0403E, p. C1-699, Debug Fault Status Register + dfsr = 0; + stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { + continue; + } + } + timeout = 0; + break; + } + } - return ret; -} + // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); + if (timeout) { + ELOG("Soft reset failed: timeout\n"); + return (-1); + } + return (0); +} /** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. + * Decode the version bits, originally from -sg, verified with usb + * @param sl stlink context, assumed to contain valid data in the buffer + * @param slv output parsed version object */ -static int -stlink_write_option_control_register_f0(stlink_t *sl, - uint32_t option_control_register) { - int ret = 0; - uint16_t opt_val[8]; - unsigned protection, optiondata; - uint16_t user_options, user_data, rdp; - unsigned option_offset, user_data_offset; +void _parse_version(stlink_t *sl, stlink_version_t *slv) { + sl->version.flags = 0; + + if (sl->version.stlink_v < 3) { + uint32_t b0 = sl->q_buf[0]; // lsb + uint32_t b1 = sl->q_buf[1]; + uint32_t b2 = sl->q_buf[2]; + uint32_t b3 = sl->q_buf[3]; + uint32_t b4 = sl->q_buf[4]; + uint32_t b5 = sl->q_buf[5]; // msb - ILOG("Asked to write option control register %#10x to %#010x.\n", - option_control_register, FLASH_OBR); + // b0 b1 || b2 b3 | b4 b5 + // 4b | 6b | 6b || 2B | 2B + // stlink_v | jtag_v | swim_v || st_vid | stlink_pid - /* Clear errors */ - clear_flash_error(sl); + slv->stlink_v = (b0 & 0xf0) >> 4; + slv->jtag_v = ((b0 & 0x0f) << 2) | ((b1 & 0xc0) >> 6); + slv->swim_v = b1 & 0x3f; + slv->st_vid = (b3 << 8) | b2; + slv->stlink_pid = (b5 << 8) | b4; - /* Retrieve current values */ - ret = stlink_read_debug32(sl, FLASH_OBR, &optiondata); - if (ret) { - return ret; + // ST-LINK/V1 from J11 switch to api-v2 (and support SWD) + if (slv->stlink_v == 1) { + slv->jtag_api = + slv->jtag_v > 11 ? STLINK_JTAG_API_V2 : STLINK_JTAG_API_V1; + } else { + slv->jtag_api = STLINK_JTAG_API_V2; + + // preferred API to get last R/W status from J15 + if (sl->version.jtag_v >= 15) { + sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + } + + if (sl->version.jtag_v >= 13) { + sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V2_MAX_TRACE_FREQUENCY; + } + } + } else { + // V3 uses different version format, for reference see OpenOCD source + // (that was written from docs available from ST under NDA): + // https://github.com/ntfreak/openocd/blob/a6dacdff58ef36fcdac00c53ec27f19de1fbce0d/src/jtag/drivers/stlink_usb.c#L965 + slv->stlink_v = sl->q_buf[0]; + slv->swim_v = sl->q_buf[1]; + slv->jtag_v = sl->q_buf[2]; + slv->st_vid = (uint32_t)((sl->q_buf[9] << 8) | sl->q_buf[8]); + slv->stlink_pid = (uint32_t)((sl->q_buf[11] << 8) | sl->q_buf[10]); + slv->jtag_api = STLINK_JTAG_API_V3; + /* preferred API to get last R/W status */ + sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; + sl->version.flags |= STLINK_F_HAS_TRACE; + sl->max_trace_freq = STLINK_V3_MAX_TRACE_FREQUENCY; } - ret = stlink_read_debug32(sl, FLASH_WRPR, &protection); - if (ret) { - return ret; + + return; +} + +void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { + stlink_write_reg(sl, addr, 15); /* pc register */ + stlink_run(sl, RUN_NORMAL); + + while (stlink_is_core_halted(sl)) { + usleep(3000000); } +} - /* Translate OBR value to flash store structure - * F0: RM0091, Option byte description, pp. 75-78 - * F1: PM0075, Option byte description, pp. 19-22 - * F3: RM0316, Option byte description, pp. 85-87 */ - switch(sl->chip_id) - { - case 0x422: /* STM32F30x */ - case 0x432: /* STM32F37x */ - case 0x438: /* STM32F303x6/8 and STM32F328 */ - case 0x446: /* STM32F303xD/E and STM32F398xE */ - case 0x439: /* STM32F302x6/8 */ - case 0x440: /* STM32F05x */ - case 0x444: /* STM32F03x */ - case 0x445: /* STM32F04x */ - case 0x448: /* STM32F07x */ - case 0x442: /* STM32F09x */ - option_offset = 6; - user_data_offset = 16; - rdp = 0x55AA; - break; - default: - option_offset = 0; - user_data_offset = 10; - rdp = 0x5AA5; - break; +/* Limit the block size to compare to 0x1800 as anything larger will stall the + * STLINK2 Maybe STLINK V1 needs smaller value! + */ +int check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { + size_t off; + size_t n_cmp = sl->flash_pgsz; + + if (n_cmp > 0x1800) { + n_cmp = 0x1800; } - user_options = (option_control_register >> option_offset >> 2) & 0xFFFF; - user_data = (option_control_register >> user_data_offset) & 0xFFFF; + for (off = 0; off < mf->len; off += n_cmp) { + size_t aligned_size; + + size_t cmp_size = n_cmp; // adjust last page size -#define VAL_WITH_COMPLEMENT(v) (uint16_t)(((v)&0xFF) | (((~(v))<<8)&0xFF00)) + if ((off + n_cmp) > mf->len) { + cmp_size = mf->len - off; + } - opt_val[0] = (option_control_register & (1 << 1/*OPT_READOUT*/)) ? 0xFFFF : rdp; - opt_val[1] = VAL_WITH_COMPLEMENT(user_options); - opt_val[2] = VAL_WITH_COMPLEMENT(user_data); - opt_val[3] = VAL_WITH_COMPLEMENT(user_data >> 8); - opt_val[4] = VAL_WITH_COMPLEMENT(protection); - opt_val[5] = VAL_WITH_COMPLEMENT(protection >> 8); - opt_val[6] = VAL_WITH_COMPLEMENT(protection >> 16); - opt_val[7] = VAL_WITH_COMPLEMENT(protection >> 24); + aligned_size = cmp_size; -#undef VAL_WITH_COMPLEMENT + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } - /* Write bytes and check errors */ - ret = stlink_write_option_bytes_f0(sl, (uint8_t*)opt_val, STM32_F0_OPTION_BYTES_BASE, sizeof(opt_val)); - if (ret) - return ret; + stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - ret = check_flash_error(sl); - if (!ret) { - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, - FLASH_OBR); + if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { + return (-1); + } } - return ret; + return (0); } -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_control_register1_f7(stlink_t *sl, - uint32_t option_control_register1) { - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - ILOG("Asked to write option control register 1 %#010x to %#010x.\n", - option_control_register1, FLASH_F7_OPTCR1); +void md5_calculate(mapped_file_t *mf) { + // calculate md5 checksum of given binary file + Md5Context md5Context; + MD5_HASH md5Hash; + Md5Initialise(&md5Context); + Md5Update(&md5Context, mf->base, (uint32_t)mf->len); + Md5Finalise(&md5Context, &md5Hash); + printf("md5 checksum: "); - /* write option byte, ensuring we dont lock opt, and set strt bit */ - uint32_t current_control_register_value; - stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); + for (int i = 0; i < (int)sizeof(md5Hash); i++) { + printf("%x", md5Hash.bytes[i]); + } - /* write option byte */ - stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); - stlink_write_debug32( - sl, FLASH_F7_OPTCR, - (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); + printf(", "); +} - wait_flash_busy(sl); +void stlink_checksum(mapped_file_t *mp) { + /* checksum that backward compatible with official ST tools */ + uint32_t sum = 0; + uint8_t *mp_byte = (uint8_t *)mp->base; - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, - FLASH_F7_OPTCR1); + for (size_t i = 0; i < mp->len; ++i) { + sum += mp_byte[i]; + } - return ret; + printf("stlink checksum: 0x%08x\n", sum); } -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_bytes_boot_add_f7(stlink_t *sl, - uint32_t option_byte_boot_add) { - ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); - return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); +void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { + unsigned int val; + // set PC to the reset routine + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); + stlink_run(sl, RUN_NORMAL); } -/** - * Write option bytes - * @param sl - * @param option bytes boot address to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_bytes_boot_add32(stlink_t *sl, - uint32_t option_bytes_boot_add) { - int ret = -1; - - wait_flash_busy(sl); +static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, + save_block_fn fn, void *fn_arg) { - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return -1; - } + int error = -1; - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; + if (size < 1) { + size = sl->flash_size; } - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); - break; - default: - ELOG("Option bytes boot address writing is currently not implemented for " - "connected chip\n"); - break; + if (size > sl->flash_size) { + size = sl->flash_size; } - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); + for (size_t off = 0; off < size; off += cmp_size) { + size_t aligned_size; - return ret; -} + // adjust last page size + if ((off + cmp_size) > size) { + cmp_size = size - off; + } -/** - * Write option bytes - * @param sl - * @param option bytes boot address to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_control_register32(stlink_t *sl, - uint32_t option_control_register) { - int ret = -1; + aligned_size = cmp_size; - wait_flash_busy(sl); + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return -1; - } + stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; + if (!fn(fn_arg, sl->q_buf, aligned_size)) { + goto on_error; + } } - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - ret = stlink_write_option_control_register_f0(sl, option_control_register); - break; - case STM32_FLASH_TYPE_F7: - ret = stlink_write_option_control_register_f7(sl, option_control_register); - break; - default: - ELOG("Option control register writing is currently not implemented for " - "connected chip\n"); - break; - } + error = 0; // success - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option control register %#010x!\n", option_control_register); +on_error: + return (error); +} - /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); +static bool stlink_fread_worker(void *arg, uint8_t *block, ssize_t len) { + struct stlink_fread_worker_arg *the_arg = + (struct stlink_fread_worker_arg *)arg; - return ret; + if (write(the_arg->fd, block, len) != len) { + fprintf(stderr, "write() != aligned_size\n"); + return (false); + } else { + return (true); + } } -/** - * Write option bytes - * @param sl - * @param option bytes boot address to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_control_register1_32( - stlink_t *sl, uint32_t option_control_register1) { - int ret = -1; +// TODO: length not checked +static uint8_t stlink_parse_hex(const char *hex) { + uint8_t d[2]; - wait_flash_busy(sl); + for (int i = 0; i < 2; ++i) { + char c = *(hex + i); - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return -1; + if (c >= '0' && c <= '9') { + d[i] = c - '0'; + } else if (c >= 'A' && c <= 'F') { + d[i] = c - 'A' + 10; + } else if (c >= 'a' && c <= 'f') { + d[i] = c - 'a' + 10; + } else { + return (0); // error + } } - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); - return -1; - } + return ((d[0] << 4) | (d[1])); +} - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F7: - ret = - stlink_write_option_control_register1_f7(sl, option_control_register1); - break; - default: - ELOG("Option control register 1 writing is currently not implemented for " - "connected chip\n"); - break; +static bool +stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { + uint32_t addr = the_arg->addr; + uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + + (uint8_t)((addr & 0x00FF0000) >> 16); + + if (17 != fprintf(the_arg->file, ":02000004%04X%02X\r\n", + (addr & 0xFFFF0000) >> 16, (uint8_t)(0x100 - sum))) { + return (false); } - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); + the_arg->lba = (addr & 0xFFFF0000); + return (true); +} - lock_flash_option(sl); - lock_flash(sl); +static bool +stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { + uint8_t count = the_arg->buf_pos; - return (ret); -} + if (count == 0) { + return (true); + } -/** - * Write the given binary file with option bytes - * @param sl - * @param path readable file path, should be binary image - * @param addr of the memory mapped option bytes - * @return 0 on success, -ve on failure. - */ -int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, - stm32_addr_t addr) { - /* Write the file in flash at addr */ - int err; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; + uint32_t addr = the_arg->addr; - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); - return (-1); + if (the_arg->lba != (addr & 0xFFFF0000)) { // segment changed + if (!stlink_fread_ihex_newsegment(the_arg)) { + return (false); + } } - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); + uint8_t sum = count + (uint8_t)((addr & 0x0000FF00) >> 8) + + (uint8_t)(addr & 0x000000FF); - err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); - stlink_fwrite_finalize(sl, addr); - unmap_file(&mf); + if (9 != fprintf(the_arg->file, ":%02X%04X00", count, (addr & 0x0000FFFF))) { + return (false); + } - return (err); -} + for (uint8_t i = 0; i < count; ++i) { + uint8_t b = the_arg->buf[i]; + sum += b; -int stlink_target_connect(stlink_t *sl, enum connect_type connect) { - if (connect == CONNECT_UNDER_RESET) { - stlink_enter_swd_mode(sl); + if (2 != fprintf(the_arg->file, "%02X", b)) { + return (false); + } + } - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); + if (4 != fprintf(the_arg->file, "%02X\r\n", (uint8_t)(0x100 - sum))) { + return (false); + } - // try to halt the core before reset - // this is useful if the NRST pin is not connected - sl->backend->force_debug(sl); + the_arg->addr += count; + the_arg->buf_pos = 0; - // minimum reset pulse duration of 20 us (RM0008, 8.1.2 Power reset) - usleep(20); + return (true); +} - stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); +static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *the_arg, + int fd, stm32_addr_t addr) { + the_arg->file = fdopen(fd, "w"); + the_arg->addr = addr; + the_arg->lba = 0; + the_arg->buf_pos = 0; - // try to halt the core after reset - unsigned timeout = time_ms() + 10; - while (time_ms() < timeout) { - sl->backend->force_debug(sl); - usleep(100); - } + return (the_arg->file != NULL); +} - // check NRST connection - uint32_t dhcsr = 0; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - WLOG("NRST is not connected\n"); +static bool stlink_fread_ihex_worker(void *arg, uint8_t *block, ssize_t len) { + struct stlink_fread_ihex_worker_arg *the_arg = + (struct stlink_fread_ihex_worker_arg *)arg; + + for (ssize_t i = 0; i < len; ++i) { + if (the_arg->buf_pos == sizeof(the_arg->buf)) { // line is full + if (!stlink_fread_ihex_writeline(the_arg)) { + return (false); + } } - // addition soft reset for halt before the first instruction - stlink_soft_reset(sl, 1 /* halt on reset */); + the_arg->buf[the_arg->buf_pos++] = block[i]; } - if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE && - stlink_enter_swd_mode(sl)) { - printf("Failed to enter SWD mode\n"); - return -1; + return (true); +} + +static bool +stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { + if (!stlink_fread_ihex_writeline(the_arg)) { + return (false); } - if (connect == CONNECT_NORMAL) { - stlink_reset(sl, RESET_AUTO); + // FIXME: do we need the Start Linear Address? + + if (13 != fprintf(the_arg->file, ":00000001FF\r\n")) { // EoF + return (false); } - return stlink_load_device_params(sl); + return (0 == fclose(the_arg->file)); } diff --git a/src/common.h b/src/common.h new file mode 100644 index 000000000..6c22d58c0 --- /dev/null +++ b/src/common.h @@ -0,0 +1,15 @@ +/* + * File: common.h + * + * TODO: add a description + */ + +#ifndef COMMON_H +#define COMMON_H + +int check_file(stlink_t *, mapped_file_t *, stm32_addr_t); +void md5_calculate(mapped_file_t *); +void stlink_checksum(mapped_file_t *); +void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); + +#endif // COMMON_H diff --git a/src/common_flash.c b/src/common_flash.c new file mode 100644 index 000000000..e2a9ebbc3 --- /dev/null +++ b/src/common_flash.c @@ -0,0 +1,1375 @@ +#include +#include +#include +#include +#include "calculate.h" +#include "common_flash.h" +#include "map_file.h" +#include "common.h" + +#define DEBUG_FLASH 0 + +uint32_t get_stm32l0_flash_base(stlink_t *sl) { + switch (sl->chip_id) { + case STM32_CHIPID_L0: + case STM32_CHIPID_L0_CAT5: + case STM32_CHIPID_L0_CAT2: + case STM32_CHIPID_L011: + return (STM32L0_FLASH_REGS_ADDR); + + case STM32_CHIPID_L1_CAT2: + case STM32_CHIPID_L1_MD: + case STM32_CHIPID_L1_MD_PLUS: + case STM32_CHIPID_L1_MD_PLUS_HD: + return (STM32L_FLASH_REGS_ADDR); + + default: + WLOG("Flash base use default L0 address\n"); + return (STM32L0_FLASH_REGS_ADDR); + } +} + +uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { + uint32_t reg, res; + + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + reg = FLASH_F4_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + reg = FLASH_F7_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + } else { + reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } + + stlink_read_debug32(sl, reg, &res); + +#if DEBUG_FLASH + fprintf(stdout, "CR:0x%x\n", res); +#endif + return (res); +} + +void lock_flash(stlink_t *sl) { + uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; + uint32_t cr_mask = 0xffffffffu; + + if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + cr_reg = FLASH_CR; + cr2_reg = FLASH_CR2; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + cr_lock_shift = STM32L0_FLASH_PELOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + cr_reg = STM32L4_FLASH_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + cr2_reg = FLASH_H7_CR2; + } + cr_lock_shift = FLASH_H7_CR_LOCK; + cr_mask = ~(1u << FLASH_H7_CR_SER); + } else { + ELOG("unsupported flash method, abort\n"); + return; + } + + stlink_read_debug32(sl, cr_reg, &n); + n &= cr_mask; + n |= (1u << cr_lock_shift); + stlink_write_debug32(sl, cr_reg, n); + + if (cr2_reg) { + n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift); + stlink_write_debug32(sl, cr2_reg, n); + } +} + +static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { + uint32_t sr_reg; + + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + sr_reg = STM32Gx_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else { + ELOG("method 'write_flash_sr' is unsupported\n"); + return (-1); + } + + return stlink_write_debug32(sl, sr_reg, val); +} + +void clear_flash_error(stlink_t *sl) { + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); + break; + case STM32_FLASH_TYPE_F2_F4: + write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); + break; + case STM32_FLASH_TYPE_F7: + write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); + break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); + break; + case STM32_FLASH_TYPE_L0_L1: + write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); + break; + case STM32_FLASH_TYPE_L4_L4P: + write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); + break; + case STM32_FLASH_TYPE_H7: + write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); + } + break; + case STM32_FLASH_TYPE_WB_WL: + write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); + break; + default: + break; + } +} + +uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { + uint32_t res, sr_reg; + + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + sr_reg = FLASH_F4_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + sr_reg = FLASH_F7_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + sr_reg = STM32Gx_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sr_reg = STM32WB_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else { + ELOG("method 'read_flash_sr' is unsupported\n"); + return (-1); + } + + stlink_read_debug32(sl, sr_reg, &res); + return (res); +} + +unsigned int is_flash_busy(stlink_t *sl) { + uint32_t sr_busy_shift; + unsigned int res; + + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { + sr_busy_shift = FLASH_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + sr_busy_shift = FLASH_F4_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + sr_busy_shift = FLASH_F7_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + sr_busy_shift = STM32L4_FLASH_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + sr_busy_shift = STM32Gx_FLASH_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sr_busy_shift = STM32WB_FLASH_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + sr_busy_shift = FLASH_H7_SR_QW; + } else { + ELOG("method 'is_flash_busy' is unsupported\n"); + return (-1); + } + + res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); + + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); + } + + return (res); +} + +void wait_flash_busy(stlink_t *sl) { + // TODO: add some delays here + while (is_flash_busy(sl)) + ; +} + +int check_flash_error(stlink_t *sl) { + uint32_t res = 0; + uint32_t WRPERR, PROGERR, PGAERR; + + WRPERR = PROGERR = PGAERR = 0; + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_SR_WRPRT_ERR); + PROGERR = (1 << FLASH_SR_PG_ERR); + break; + case STM32_FLASH_TYPE_F2_F4: + res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F4_SR_WRPERR); + PGAERR = (1 << FLASH_F4_SR_PGAERR); + break; + case STM32_FLASH_TYPE_F7: + res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; + WRPERR = (1 << FLASH_F7_SR_WRP_ERR); + PROGERR = (1 << FLASH_F7_SR_PGP_ERR); + break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); + PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); + PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); + break; + case STM32_FLASH_TYPE_L0_L1: + res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); + PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); + break; + case STM32_FLASH_TYPE_L4_L4P: + res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); + PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); + PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); + break; + case STM32_FLASH_TYPE_H7: + res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_H7_SR_WRPERR); + break; + case STM32_FLASH_TYPE_WB_WL: + res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; + WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); + PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); + PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); + break; + default: + break; + } + + if (res) { + if (WRPERR && (WRPERR & res) == WRPERR) { + ELOG("Flash memory is write protected\n"); + res &= ~WRPERR; + } else if (PROGERR && (PROGERR & res) == PROGERR) { + ELOG("Flash memory contains a non-erased value\n"); + res &= ~PROGERR; + } else if (PGAERR && (PGAERR & res) == PGAERR) { + ELOG("Invalid flash address\n"); + res &= ~PGAERR; + } + + if (res) { + ELOG("Flash programming error: %#010x\n", res); + } + return (-1); + } + + return (0); +} + +static inline unsigned int is_flash_locked(stlink_t *sl) { + /* return non zero for true */ + uint32_t cr_lock_shift; + uint32_t cr_reg; + uint32_t n; + + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + cr_lock_shift = FLASH_F4_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + cr_lock_shift = STM32L0_FLASH_PELOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + cr_reg = STM32L4_FLASH_CR; + cr_lock_shift = STM32L4_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + cr_lock_shift = STM32WB_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + cr_lock_shift = FLASH_H7_CR_LOCK; + } else { + ELOG("unsupported flash method, abort\n"); + return (-1); + } + + stlink_read_debug32(sl, cr_reg, &n); + return (n & (1u << cr_lock_shift)); +} + +static void unlock_flash(stlink_t *sl) { + uint32_t key_reg, key2_reg = 0; + uint32_t flash_key1 = FLASH_KEY1; + uint32_t flash_key2 = FLASH_KEY2; + /* The unlock sequence consists of 2 write cycles where 2 key values are + * written to the FLASH_KEYR register. An invalid sequence results in a + * definitive lock of the FPEC block until next reset. + */ + + if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + key_reg = FLASH_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + key_reg = FLASH_KEYR; + key2_reg = FLASH_KEYR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + key_reg = FLASH_F4_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + key_reg = FLASH_F7_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; + flash_key1 = FLASH_L0_PEKEY1; + flash_key2 = FLASH_L0_PEKEY2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + key_reg = STM32L4_FLASH_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + key_reg = STM32Gx_FLASH_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + key_reg = STM32WB_FLASH_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + key_reg = FLASH_H7_KEYR1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + key2_reg = FLASH_H7_KEYR2; + } + } else { + ELOG("unsupported flash method, abort\n"); + return; + } + + stlink_write_debug32(sl, key_reg, flash_key1); + stlink_write_debug32(sl, key_reg, flash_key2); + + if (key2_reg) { + stlink_write_debug32(sl, key2_reg, flash_key1); + stlink_write_debug32(sl, key2_reg, flash_key2); + } +} + +/* unlock flash if already locked */ +int unlock_flash_if(stlink_t *sl) { + if (is_flash_locked(sl)) { + unlock_flash(sl); + + if (is_flash_locked(sl)) { + WLOG("Failed to unlock flash!\n"); + return (-1); + } + } + + DLOG("Successfully unlocked flash\n"); + return (0); +} + +int lock_flash_option(stlink_t *sl) { + uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; + int active_bit_level = 1; + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; + break; + case STM32_FLASH_TYPE_F2_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STM32_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; + case STM32_FLASH_TYPE_L0_L1: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STM32_FLASH_TYPE_L4_L4P: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_WB_WL: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optcr2_reg = FLASH_H7_OPTCR2; + break; + default: + ELOG("unsupported flash method, abort\n"); + return -1; + } + + stlink_read_debug32(sl, optcr_reg, &n); + + if (active_bit_level == 0) { + n &= ~(1u << optlock_shift); + } else { + n |= (1u << optlock_shift); + } + + stlink_write_debug32(sl, optcr_reg, n); + + if (optcr2_reg) { + stlink_read_debug32(sl, optcr2_reg, &n); + + if (active_bit_level == 0) { + n &= ~(1u << optlock_shift); + } else { + n |= (1u << optlock_shift); + } + + stlink_write_debug32(sl, optcr2_reg, n); + } + + return (0); +} + +static bool is_flash_option_locked(stlink_t *sl) { + uint32_t optlock_shift, optcr_reg; + int active_bit_level = 1; + uint32_t n; + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; + optlock_shift = FLASH_CR_OPTWRE; + active_bit_level = 0; /* bit is "option write enable", not lock */ + break; + case STM32_FLASH_TYPE_F2_F4: + optcr_reg = FLASH_F4_OPTCR; + optlock_shift = FLASH_F4_OPTCR_LOCK; + break; + case STM32_FLASH_TYPE_F7: + optcr_reg = FLASH_F7_OPTCR; + optlock_shift = FLASH_F7_OPTCR_LOCK; + break; + case STM32_FLASH_TYPE_L0_L1: + optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; + optlock_shift = STM32L0_FLASH_OPTLOCK; + break; + case STM32_FLASH_TYPE_L4_L4P: + optcr_reg = STM32L4_FLASH_CR; + optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_WB_WL: + optcr_reg = STM32WB_FLASH_CR; + optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + break; + default: + ELOG("unsupported flash method, abort\n"); + return -1; + } + + stlink_read_debug32(sl, optcr_reg, &n); + + if (active_bit_level == 0) { + return (!(n & (1u << optlock_shift))); + } + + return (n & (1u << optlock_shift)); +} + +static int unlock_flash_option(stlink_t *sl) { + uint32_t optkey_reg, optkey2_reg = 0; + uint32_t optkey1 = FLASH_OPTKEY1; + uint32_t optkey2 = FLASH_OPTKEY2; + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + optkey_reg = FLASH_OPTKEYR; + optkey1 = FLASH_F0_OPTKEY1; + optkey2 = FLASH_F0_OPTKEY2; + break; + case STM32_FLASH_TYPE_F2_F4: + optkey_reg = FLASH_F4_OPT_KEYR; + break; + case STM32_FLASH_TYPE_F7: + optkey_reg = FLASH_F7_OPT_KEYR; + break; + case STM32_FLASH_TYPE_L0_L1: + optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; + optkey1 = FLASH_L0_OPTKEY1; + optkey2 = FLASH_L0_OPTKEY2; + break; + case STM32_FLASH_TYPE_L4_L4P: + optkey_reg = STM32L4_FLASH_OPTKEYR; + break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + optkey_reg = STM32Gx_FLASH_OPTKEYR; + break; + case STM32_FLASH_TYPE_WB_WL: + optkey_reg = STM32WB_FLASH_OPT_KEYR; + break; + case STM32_FLASH_TYPE_H7: + optkey_reg = FLASH_H7_OPT_KEYR; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optkey2_reg = FLASH_H7_OPT_KEYR2; + break; + default: + ELOG("unsupported flash method, abort\n"); + return (-1); + } + + stlink_write_debug32(sl, optkey_reg, optkey1); + stlink_write_debug32(sl, optkey_reg, optkey2); + + if (optkey2_reg) { + stlink_write_debug32(sl, optkey2_reg, optkey1); + stlink_write_debug32(sl, optkey2_reg, optkey2); + } + + return (0); +} + +int unlock_flash_option_if(stlink_t *sl) { + if (is_flash_option_locked(sl)) { + if (unlock_flash_option(sl)) { + ELOG("Could not unlock flash option!\n"); + return (-1); + } + + if (is_flash_option_locked(sl)) { + ELOG("Failed to unlock flash option!\n"); + return (-1); + } + } + + DLOG("Successfully unlocked flash option\n"); + return (0); +} + +void write_flash_cr_psiz(stlink_t *sl, uint32_t n, + unsigned bank) { + uint32_t cr_reg, psize_shift; + uint32_t x = read_flash_cr(sl, bank); + + if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + psize_shift = FLASH_H7_CR_PSIZE; + } else { + cr_reg = FLASH_F4_CR; + psize_shift = 8; + } + + x &= ~(0x03 << psize_shift); + x |= (n << psize_shift); +#if DEBUG_FLASH + fprintf(stdout, "PSIZ:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, cr_reg, x); +} + +void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { + uint32_t cr_reg, n; + uint32_t bit = FLASH_CR_PG; + + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + cr_reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + bit = FLASH_H7_CR_PG; + } else { + cr_reg = FLASH_CR; + } + + n = read_flash_cr(sl, bank) & ~(1 << bit); + stlink_write_debug32(sl, cr_reg, n); +} +/* ------------------------------------------------------------------------ */ + +static void wait_flash_busy_progress(stlink_t *sl) { + int i = 0; + fprintf(stdout, "Mass erasing"); + fflush(stdout); + + while (is_flash_busy(sl)) { + usleep(10000); + i++; + + if (i % 100 == 0) { + fprintf(stdout, "."); + fflush(stdout); + } + } + + fprintf(stdout, "\n"); +} + +static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { + stlink_write_debug32(sl, (bank == BANK_1) ? FLASH_AR : FLASH_AR2, n); +} + +static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { + uint32_t cr_reg, snb_mask, snb_shift, ser_shift; + uint32_t x = read_flash_cr(sl, bank); + + if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + snb_mask = FLASH_H7_CR_SNB_MASK; + snb_shift = FLASH_H7_CR_SNB; + ser_shift = FLASH_H7_CR_SER; + } else { + cr_reg = FLASH_F4_CR; + snb_mask = FLASH_F4_CR_SNB_MASK; + snb_shift = FLASH_F4_CR_SNB; + ser_shift = FLASH_F4_CR_SER; + } + + x &= ~snb_mask; + x |= (n << snb_shift); + x |= (1 << ser_shift); +#if DEBUG_FLASH + fprintf(stdout, "SNB:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, cr_reg, x); +} + +static void set_flash_cr_per(stlink_t *sl, unsigned bank) { + uint32_t cr_reg, val; + + if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } + + stlink_read_debug32(sl, cr_reg, &val); + val |= (1 << FLASH_CR_PER); + stlink_write_debug32(sl, cr_reg, val); +} + +static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { + uint32_t cr_reg; + + if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + } + + const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER); + stlink_write_debug32(sl, cr_reg, n); +} + +static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { + stlink_write_debug32(sl, STM32L4_FLASH_SR, + 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); + uint32_t x = read_flash_cr(sl, BANK_1); + x &= ~STM32L4_FLASH_CR_OPBITS; + x &= ~STM32L4_FLASH_CR_PAGEMASK; + x &= ~(1 << STM32L4_FLASH_CR_MER1); + x &= ~(1 << STM32L4_FLASH_CR_MER2); + x |= (n << STM32L4_FLASH_CR_PNB); + x |= (uint32_t)(1lu << STM32L4_FLASH_CR_PER); +#if DEBUG_FLASH + fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); +#endif + stlink_write_debug32(sl, STM32L4_FLASH_CR, x); +} + +static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { + uint32_t val, cr_reg, cr_strt; + + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + cr_strt = 1 << FLASH_F4_CR_STRT; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_strt = 1 << FLASH_F7_CR_STRT; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + cr_reg = STM32L4_FLASH_CR; + cr_strt = (1 << STM32L4_FLASH_CR_STRT); + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_strt = (1 << STM32Gx_FLASH_CR_STRT); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + cr_strt = (1 << STM32WB_FLASH_CR_STRT); + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + cr_strt = (1 << FLASH_CR_STRT); + } + + stlink_read_debug32(sl, cr_reg, &val); + val |= cr_strt; + stlink_write_debug32(sl, cr_reg, val); +} + +static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { + uint32_t val, cr_reg, cr_mer, cr_pg; + + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + cr_reg = STM32L4_FLASH_CR; + cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); + cr_pg = (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_mer = (1 << STM32Gx_FLASH_CR_MER1); + + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); + } + + cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + cr_mer = (1 << FLASH_H7_CR_BER); + cr_pg = (1 << FLASH_H7_CR_PG); + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); + } + + stlink_read_debug32(sl, cr_reg, &val); + + if (val & cr_pg) { + // STM32F030 will drop MER bit if PG was set + val &= ~cr_pg; + stlink_write_debug32(sl, cr_reg, val); + } + + if (v) { + val |= cr_mer; + } else { + val &= ~cr_mer; + } + + stlink_write_debug32(sl, cr_reg, val); +} + +/** + * Erase a page of flash, assumes sl is fully populated with things like + * chip/core ids + * @param sl stlink context + * @param flashaddr an address in the flash page to erase + * @return 0 on success -ve on failure + */ +int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { + // wait for ongoing op to finish + wait_flash_busy(sl); + // clear flash IO errors + clear_flash_error(sl); + + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4 || + sl->flash_type == STM32_FLASH_TYPE_F7 || + sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + // unlock if locked + unlock_flash_if(sl); + + // select the page to erase + if ((sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_L45x_L46x) || + (sl->chip_id == STM32_CHIPID_L496x_L4A6x) || + (sl->chip_id == STM32_CHIPID_L4Rx)) { + // calculate the actual bank+page from the address + uint32_t page = calculate_L4_page(sl, flashaddr); + + fprintf(stderr, "EraseFlash - Page:0x%x Size:0x%x ", page, + stlink_calculate_pagesize(sl, flashaddr)); + + write_flash_cr_bker_pnb(sl, page); + } else if (sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx) { + // calculate the actual page from the address + uint32_t sector = calculate_F7_sectornum(flashaddr); + + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, + stlink_calculate_pagesize(sl, flashaddr)); + write_flash_cr_snb(sl, sector, BANK_1); + } else { + // calculate the actual page from the address + uint32_t sector = calculate_F4_sectornum(flashaddr); + + fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, + stlink_calculate_pagesize(sl, flashaddr)); + + // the SNB values for flash sectors in the second bank do not directly + // follow the values for the first bank on 2mb devices... + if (sector >= 12) { + sector += 4; + } + + write_flash_cr_snb(sl, sector, BANK_1); + } + + set_flash_cr_strt(sl, BANK_1); // start erase operation + wait_flash_busy(sl); // wait for completion + lock_flash(sl); // TODO: fails to program if this is in +#if DEBUG_FLASH + fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); +#endif + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // check if the locks are set + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + + if ((val & (1 << 0)) || (val & (1 << 1))) { + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY2); + + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + + if (val & (1 << 0)) { + WLOG("pecr.pelock not clear (%#x)\n", val); + return (-1); + } + + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY2); + + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + + if (val & (1 << 1)) { + WLOG("pecr.prglock not clear (%#x)\n", val); + return (-1); + } + } + + // set pecr.{erase,prog} + val |= (1 << 9) | (1 << 3); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + + // write 0 to the first word of the page to be erased + stlink_write_debug32(sl, flashaddr, 0); + + /* MP: It is better to wait for clearing the busy bit after issuing page + * erase command, even though PM0062 recommends to wait before it. + * Test shows that a few iterations is performed in the following loop + * before busy bit is cleared. + */ + wait_flash_busy(sl); + + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + uint32_t val; + unlock_flash_if(sl); + set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit + + // set the page to erase + if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + + // sec 3.10.5 - PNB[7:0] is offset by 3. + val &= ~(0xFF << 3); // Clear previously set page number (if any) + val |= ((flash_page & 0xFF) << 3); + + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + } else if (sl->flash_type == STM32_FLASH_TYPE_G0) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. + val &= ~(0x3F << 3); + val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } else if (sl->flash_type == STM32_FLASH_TYPE_G4) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. + val &= ~(0x7F << 3); + val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } + + set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit + wait_flash_busy(sl); // wait for the 'busy' bit to clear + clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit + lock_flash(sl); + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + unlock_flash_if(sl); + clear_flash_cr_pg(sl, bank); // clear the pg bit + set_flash_cr_per(sl, bank); // set the page erase bit + write_flash_ar(sl, flashaddr, bank); // select the page to erase + set_flash_cr_strt(sl, + bank); // start erase operation, reset by hw with busy bit + wait_flash_busy(sl); + clear_flash_cr_per(sl, bank); // clear the page erase bit + lock_flash(sl); + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + unlock_flash_if(sl); // unlock if locked + uint32_t sector = calculate_H7_sectornum( + sl, flashaddr, bank); // calculate the actual page from the address + write_flash_cr_snb(sl, sector, bank); // select the page to erase + set_flash_cr_strt(sl, bank); // start erase operation + wait_flash_busy(sl); // wait for completion + lock_flash(sl); + } else { + WLOG("unknown coreid %x, page erase failed\n", sl->core_id); + return (-1); + } + + return check_flash_error(sl); +} + +int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { + // Check the address and size validity + if (stlink_check_address_range_validity(sl, base_addr, size) < 0) { + return -1; + } + + // Make sure the requested address is aligned with the beginning of a page + if (stlink_check_address_alignment(sl, base_addr) < 0) { + ELOG("The address to erase is not aligned with the beginning of a page\n"); + return -1; + } + + stm32_addr_t addr = base_addr; + do { + long unsigned int page_size = stlink_calculate_pagesize(sl, addr); + + // Check if size is aligned with a page, unless we want to completely erase the last page + if ((addr + page_size) > (base_addr + size) && !align_size) { + ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); + return -1; + } + + if (stlink_erase_flash_page(sl, addr)) { + WLOG("Failed to erase_flash_page(%#x) == -1\n", addr); + return (-1); + } + + fprintf(stdout, "-> Flash page at %#x erased (size: %#lx)\n", addr, page_size); + fflush(stdout); + + // check the next page is within the range to erase + addr += page_size; + } while (addr < (base_addr + size)); + + fprintf(stdout, "\n"); + return 0; +} + +int stlink_erase_flash_mass(stlink_t *sl) { + int err = 0; + + // TODO: User MER bit to mass-erase WB series. + if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || + sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + + err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); + + } else { + wait_flash_busy(sl); + clear_flash_error(sl); + unlock_flash_if(sl); + + if (sl->flash_type == STM32_FLASH_TYPE_H7 && + sl->chip_id != STM32_CHIPID_H7Ax) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } + + set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit + set_flash_cr_strt( + sl, BANK_1); // start erase operation, reset by hw with busy bit + + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 + set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 + } + + wait_flash_busy_progress(sl); + lock_flash(sl); + + // reset the mass erase bit + set_flash_cr_mer(sl, 0, BANK_1); + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + set_flash_cr_mer(sl, 0, BANK_2); + } + + err = check_flash_error(sl); + } + + return (err); +} + +int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, + stm32_addr_t addr) { + /* Write the block in flash at addr */ + int err; + unsigned int num_empty, idx; + uint8_t erased_pattern = stlink_get_erased_pattern(sl); + + /* + * This optimisation may cause unexpected garbage data remaining. + * Therfore it is turned off by default. + */ + if (sl->opt) { + idx = (unsigned int)length; + + for (num_empty = 0; num_empty != length; ++num_empty) + if (data[--idx] != erased_pattern) { + break; + } + + num_empty -= (num_empty & 3); // Round down to words + + if (num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, + erased_pattern); + } + } else { + num_empty = 0; + } + + /* + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. + */ + err = stlink_write_flash(sl, addr, data, + (num_empty == length) ? (uint32_t)length + : (uint32_t)length - num_empty, + num_empty == length); + stlink_fwrite_finalize(sl, addr); + return (err); +} + +/** + * Write the given binary file into flash at address "addr" + * @param sl + * @param path readable file path, should be binary image + * @param addr where to start writing + * @return 0 on success, -ve on failure. + */ +int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { + /* Write the file in flash at addr */ + int err; + unsigned int num_empty, idx; + uint8_t erased_pattern = stlink_get_erased_pattern(sl); + mapped_file_t mf = MAPPED_FILE_INITIALIZER; + + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return (-1); + } + + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); + + if (sl->opt) { + idx = (unsigned int)mf.len; + + for (num_empty = 0; num_empty != mf.len; ++num_empty) { + if (mf.base[--idx] != erased_pattern) { + break; + } + } + + num_empty -= (num_empty & 3); // round down to words + + if (num_empty != 0) { + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, + erased_pattern); + } + } else { + num_empty = 0; + } + + /* + * TODO: investigate a kind of weird behaviour here: + * If the file is identified to be all-empty and four-bytes aligned, + * still flash the whole file even if ignoring message is printed. + */ + err = stlink_write_flash(sl, addr, mf.base, + (num_empty == mf.len) ? (uint32_t)mf.len + : (uint32_t)mf.len - num_empty, + num_empty == mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); + return (err); +} + + +int stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { + // check the contents of path are at addr + + int res; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; + + if (map_file(&mf, path) == -1) { + return (-1); + } + + res = check_file(sl, &mf, addr); + unmap_file(&mf); + return (res); +} + +/** + * Verify addr..addr+len is binary identical to base...base+len + * @param sl stlink context + * @param address stm device address + * @param data host side buffer to check against + * @param length how much + * @return 0 for success, -ve for failure + */ +int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, + unsigned length) { + size_t off; + size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; + ILOG("Starting verification of write complete\n"); + + for (off = 0; off < length; off += cmp_size) { + size_t aligned_size; + + // adjust last page size + if ((off + cmp_size) > length) { + cmp_size = length - off; + } + + aligned_size = cmp_size; + + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } + + stlink_read_mem32(sl, address + (uint32_t)off, (uint16_t)aligned_size); + + if (memcmp(sl->q_buf, data + off, cmp_size)) { + ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); + return (-1); + } + } + + ILOG("Flash written and verified! jolly good!\n"); + return (0); +} + +// Check if an address and size are within the flash +int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { + long unsigned int logvar; + if (addr < sl->flash_base || addr >= (sl->flash_base + sl->flash_size)) { + logvar = sl->flash_base + sl->flash_size - 1; + ELOG("Invalid address, it should be within 0x%08x - 0x%08lx\n", sl->flash_base, logvar); + return (-1); + } + if ((addr + size) > (sl->flash_base + sl->flash_size)) { + logvar = sl->flash_base + sl->flash_size - addr; + ELOG("The size exceeds the size of the flash (0x%08lx bytes available)\n", logvar); + return (-1); + } + return 0; +} + +// Check if an address is aligned with the beginning of a page +int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { + stm32_addr_t page = sl->flash_base; + + while (page < addr) { + page += stlink_calculate_pagesize(sl, page); + } + + if (page != addr) { + return -1; + } + + return 0; +} + +int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len, uint8_t eraseonly) { + int ret; + flash_loader_t fl; + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, + len, addr, addr); + // check addr range is inside the flash + stlink_calculate_pagesize(sl, addr); + + // Check the address and size validity + if (stlink_check_address_range_validity(sl, addr, len) < 0) { + return (-1); + } else if (len & 1) { + WLOG("unaligned len 0x%x -- padding with zero\n", len); + len += 1; + } else if (stlink_check_address_alignment(sl, addr) < 0) { + ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " + "check page start address and compare with flash module organisation " + "in related ST reference manual of your device.\n", + (unsigned)(sl->flash_pgsz)); + return (-1); + } + + // make sure we've loaded the context with the chip details + stlink_core_id(sl); + + // Erase this section of the flash + if (stlink_erase_flash_section(sl, addr, len, true) < 0) { + ELOG("Failed to erase the flash prior to writing\n"); + return (-1); + } + + if (eraseonly) { + return (0); + } + + ret = stlink_flashloader_start(sl, &fl); + if (ret) + return ret; + ret = stlink_flashloader_write(sl, &fl, addr, base, len); + if (ret) + return ret; + ret = stlink_flashloader_stop(sl, &fl); + if (ret) + return ret; + + return (stlink_verify_write_flash(sl, addr, base, len)); +} diff --git a/src/common_flash.h b/src/common_flash.h new file mode 100644 index 000000000..70a6f0e04 --- /dev/null +++ b/src/common_flash.h @@ -0,0 +1,27 @@ +/* + * File: common_flash.h + * + * TODO: add a description + */ + +#ifndef COMMON_FLASH_H +#define COMMON_FLASH_H + +void lock_flash(stlink_t *); +void clear_flash_error(stlink_t *); +void wait_flash_busy(stlink_t *); +int check_flash_error(stlink_t *); +int unlock_flash_if(stlink_t *); +int lock_flash_option(stlink_t *); +int unlock_flash_option_if(stlink_t *); +void write_flash_cr_psiz(stlink_t *, uint32_t, unsigned); +void clear_flash_cr_pg(stlink_t *, unsigned); + +// TODO: move to private defines if possible + +#define BANK_1 0 +#define BANK_2 1 + +uint32_t read_flash_cr(stlink_t *, unsigned); +uint32_t get_stm32l0_flash_base(stlink_t *); +#endif // STLINK_H diff --git a/src/flashloader.c b/src/flashloader.c new file mode 100644 index 000000000..ce230d7ab --- /dev/null +++ b/src/flashloader.c @@ -0,0 +1,482 @@ +#include +#include +#include +#include "common_flash.h" + +#define L1_WRITE_BLOCK_SIZE 0x80 +#define L0_WRITE_BLOCK_SIZE 0x40 + +int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len, uint32_t pagesize) { + unsigned int count, off; + unsigned int num_half_pages = len / pagesize; + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + flash_loader_t fl; + bool use_loader = true; + int ret = 0; + + // enable half page write + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << FLASH_L1_FPRG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + val |= (1 << FLASH_L1_PROG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + + wait_flash_busy(sl); + + for (count = 0; count < num_half_pages; count++) { + if (use_loader) { + ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, + base + count * pagesize, pagesize); + if (ret && count == 0) { + /* It seems that stm32lx devices have a problem when it is blank */ + WLOG("Failed to use flash loader, fallback to soft write\n"); + use_loader = false; + } + } + if (!use_loader) { + ret = 0; + for (off = 0; off < pagesize && !ret; off += 64) { + size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; + memcpy(sl->q_buf, base + count * pagesize + off, chunk); + ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); + } + } + + if (ret) { + WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", + addr + count * pagesize); + break; + } + + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading + fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); + fflush(stdout); + } + + // wait for sr.busy to be cleared + wait_flash_busy(sl); + } + + // disable half page write + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + return (ret); +} + +static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { + uint32_t cr_reg, x; + + x = read_flash_cr(sl, bank); + + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + cr_reg = STM32L4_FLASH_CR; + x &= ~STM32L4_FLASH_CR_OPBITS; + x |= (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + x |= (1 << FLASH_H7_CR_PG); + } else { + cr_reg = FLASH_CR; + x = (1 << FLASH_CR_PG); + } + + stlink_write_debug32(sl, cr_reg, x); +} + +static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { + uint32_t rcc, rcc_dma_mask, value; + + rcc = rcc_dma_mask = value = 0; + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + rcc = STM32F1_RCC_AHBENR; + rcc_dma_mask = STM32F1_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_F2_F4: + case STM32_FLASH_TYPE_F7: + rcc = STM32F4_RCC_AHB1ENR; + rcc_dma_mask = STM32F4_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_G0: + rcc = STM32G0_RCC_AHBENR; + rcc_dma_mask = STM32G0_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_L4_L4P: + rcc = STM32G4_RCC_AHB1ENR; + rcc_dma_mask = STM32G4_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_L0_L1: + rcc = STM32L0_RCC_AHBENR; + rcc_dma_mask = STM32L0_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_H7: + rcc = STM32H7_RCC_AHB1ENR; + rcc_dma_mask = STM32H7_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_WB_WL: + rcc = STM32WB_RCC_AHB1ENR; + rcc_dma_mask = STM32WB_RCC_DMAEN; + break; + default: + return; + } + + if (!stlink_read_debug32(sl, rcc, &value)) { + if (bckpRstr) { + value = (value & (~rcc_dma_mask)) | fl->rcc_dma_bkp; + } else { + fl->rcc_dma_bkp = value & rcc_dma_mask; + value &= ~rcc_dma_mask; + } + stlink_write_debug32(sl, rcc, value); + } +} + +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { + // disable DMA + set_dma_state(sl, fl, 0); + + // wait for ongoing op to finish + wait_flash_busy(sl); + // Clear errors + clear_flash_error(sl); + + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { + ILOG("Starting Flash write for F2/F4/F7/L4\n"); + + // Flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + + unlock_flash_if(sl); // first unlock the cr + + int voltage; + if (sl->version.stlink_v == 1) { + WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); + voltage = 3200; + } else { + voltage = stlink_target_voltage(sl); + } + + if (voltage == -1) { + ELOG("Failed to read Target voltage\n"); + return (-1); + } + + if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + // L4 does not have a byte-write mode + if (voltage < 1710) { + ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); + return (-1); + } + } else { + if (voltage > 2700) { + ILOG("enabling 32-bit flash writes\n"); + write_flash_cr_psiz(sl, 2, BANK_1); + } else { + ILOG("Target voltage (%d mV) too low for 32-bit flash, " + "using 8-bit flash writes\n", + voltage); + write_flash_cr_psiz(sl, 0, BANK_1); + } + } + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + ILOG("Starting Flash write for WB/G0/G4\n"); + + unlock_flash_if(sl); // unlock flash if necessary + set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + ILOG("Starting Flash write for L0\n"); + + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY2); + + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { + ELOG("pecr.pelock not clear\n"); + return (-1); + } + + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY2); + + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { + ELOG("pecr.prglock not clear\n"); + return (-1); + } + + /* Flash loader initialisation */ + if (stlink_flash_loader_init(sl, fl) == -1) { + // L0/L1 have fallback to soft write + WLOG("stlink_flash_loader_init() == -1\n"); + } + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); + + // flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + + // unlock flash + unlock_flash_if(sl); + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + set_flash_cr_pg(sl, BANK_2); + } + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + ILOG("Starting Flash write for H7\n"); + + unlock_flash_if(sl); // unlock the cr + set_flash_cr_pg(sl, BANK_1); // set programming mode + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + set_flash_cr_pg(sl, BANK_2); + } + if (sl->chip_id != STM32_CHIPID_H7Ax) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } + } else { + ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + return (-1); + } + + return (0); +} + +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, + stm32_addr_t addr, uint8_t *base, uint32_t len) { + size_t off; + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { + size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; + for (off = 0; off < len;) { + size_t size = len - off > buf_size ? buf_size : len - off; + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + off += size; + } + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } + + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + } + fprintf(stdout, "\n"); + + // flash writes happen as 2 words at a time + if ((off / sizeof(uint32_t)) % 2 != 0) { + stlink_write_debug32(sl, addr + (uint32_t)off, + 0); // write a single word of zeros + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + } + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? + L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; + + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + + off = 0; + + if (len > pagesize) { + if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { + return (-1); + } else { + off = (size_t)(len / pagesize) * pagesize; + } + } + + // write remaining word in program memory + for (; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } + + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + + // wait for sr.busy to be cleared + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); + + // TODO: check redo write operation + } + fprintf(stdout, "\n"); + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + int write_block_count = 0; + for (off = 0; off < len; off += sl->flash_pgsz) { + // adjust last write size + size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; + + // unlock and set programming mode + unlock_flash_if(sl); + + DLOG("Finished unlocking flash, running loader!\n"); + + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + lock_flash(sl); + + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading + fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, + (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + for (off = 0; off < len;) { + // Program STM32H7x with 64-byte Flash words + size_t chunk = (len - off > 64) ? 64 : len - off; + memcpy(sl->q_buf, base + off, chunk); + stlink_write_mem32(sl, addr + (uint32_t)off, 64); + wait_flash_busy(sl); + + off += chunk; + + if (sl->verbose >= 1) { + // show progress + fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, + (unsigned int)len); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else { + return (-1); + } + + return check_flash_error(sl); +} + +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { + uint32_t dhcsr; + + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) || + (sl->flash_type == STM32_FLASH_TYPE_WB_WL) || + (sl->flash_type == STM32_FLASH_TYPE_G0) || + (sl->flash_type == STM32_FLASH_TYPE_G4) || + (sl->flash_type == STM32_FLASH_TYPE_H7)) { + + clear_flash_cr_pg(sl, BANK_1); + if ((sl->flash_type == STM32_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + clear_flash_cr_pg(sl, BANK_2); + } + lock_flash(sl); + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } + + // enable interrupt + if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); + } + + // restore DMA state + set_dma_state(sl, fl, 1); + + return (0); +} diff --git a/src/map_file.c b/src/map_file.c new file mode 100644 index 000000000..17697c1da --- /dev/null +++ b/src/map_file.c @@ -0,0 +1,62 @@ +#include +#include +#include +#include +#include + +#include "map_file.h" + +#ifndef MAX_FILE_SIZE +#define MAX_FILE_SIZE (1<<20) // 1 GB max file size +#endif + +#ifndef O_BINARY +#define O_BINARY 0 +#endif + +int map_file(mapped_file_t *mf, const char *path) { + int error = -1; + struct stat st; + + const int fd = open(path, O_RDONLY | O_BINARY); + + if (fd == -1) { + fprintf(stderr, "open(%s) == -1\n", path); + return (-1); + } + + if (fstat(fd, &st) == -1) { + fprintf(stderr, "fstat(%s) == -1\n", path); + goto on_error; + } + + if (sizeof(st.st_size) != sizeof(size_t)) { + // on 32 bit systems, check if there is an overflow + if (st.st_size > (off_t)MAX_FILE_SIZE /*1 GB*/ ) { + // limit file size to 1 GB + fprintf(stderr, "mmap() size_t overflow for file %s\n", path); + goto on_error; + } + } + + mf->base = + (uint8_t *)mmap(NULL, (size_t)(st.st_size), PROT_READ, MAP_SHARED, fd, 0); + + if (mf->base == MAP_FAILED) { + fprintf(stderr, "mmap() == MAP_FAILED for file %s\n", path); + goto on_error; + } + + mf->len = (size_t)st.st_size; + error = 0; // success + +on_error: + close(fd); + return (error); +} + +void unmap_file(mapped_file_t *mf) { + munmap((void *)mf->base, mf->len); + mf->base = (unsigned char *)MAP_FAILED; + mf->len = 0; +} diff --git a/src/map_file.h b/src/map_file.h new file mode 100644 index 000000000..9cdd745e6 --- /dev/null +++ b/src/map_file.h @@ -0,0 +1,32 @@ +/* + * File: map_file.h + * + * TODO: add a description + */ + +#ifndef MAP_FILE_H +#define MAP_FILE_H + +#ifndef O_BINARY +#define O_BINARY 0 +#endif + +#ifdef STLINK_HAVE_SYS_MMAN_H +#include +#else +#include +#endif + +/* Memory mapped file */ +typedef struct mapped_file { + uint8_t *base; + size_t len; +} mapped_file_t; + +#define MAPPED_FILE_INITIALIZER \ + { NULL, 0 } + +int map_file(mapped_file_t *, const char *); +void unmap_file(mapped_file_t *); + +#endif // MAP_FILE_H diff --git a/src/option.c b/src/option.c new file mode 100644 index 000000000..bd792b4a9 --- /dev/null +++ b/src/option.c @@ -0,0 +1,1027 @@ +#include +#include +#include +#include "common_flash.h" +#include "map_file.h" +#include "common.h" + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_Gx(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_Gx(sl, option_byte); +} + +/** + * Read first option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); + return stlink_read_debug32(sl, sl->option_base, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f2(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f2(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f4(stlink_t *sl, + uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f4(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + * + * Since multiple bytes can be read, we read and print all but one here + * and then return the last one just like other devices + */ +int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { + int err = -1; + for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { + err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), + option_byte); + if (err == -1) { + return err; + } else { + printf("%08x\n", *option_byte); + } + } + + return stlink_read_debug32( + sl, + sl->option_base + (uint32_t)(sl->option_size / 4 - 1) * sizeof(uint32_t), + option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return (-1); + } + + switch (sl->chip_id) { + case STM32_CHIPID_F2: + return stlink_read_option_bytes_f2(sl, option_byte); + case STM32_CHIPID_F4: + case STM32_CHIPID_F446: + return stlink_read_option_bytes_f4(sl, option_byte); + case STM32_CHIPID_F76xxx: + return stlink_read_option_bytes_f7(sl, option_byte); + case STM32_CHIPID_G0_CAT1: + case STM32_CHIPID_G0_CAT2: + case STM32_CHIPID_G4_CAT2: + case STM32_CHIPID_G4_CAT3: + return stlink_read_option_bytes_Gx(sl, option_byte); + default: + return stlink_read_option_bytes_generic(sl, option_byte); + } +} + + +/** + * Write option bytes + * @param sl + * @param base option bytes to write + * @param addr of the memory mapped option bytes + * @param len of options bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f0( + stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { + int ret = 0; + + if (len < 12 || addr != STM32_F0_OPTION_BYTES_BASE) { + WLOG("Only full write of option bytes area is supported\n"); + return -1; + } + + clear_flash_error(sl); + + WLOG("Erasing option bytes\n"); + + /* erase option bytes */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_OPTWRE)); + ret = stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTER) | (1 << FLASH_CR_STRT) | (1 << FLASH_CR_OPTWRE)); + if (ret) { + return ret; + } + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (ret) { + return ret; + } + + WLOG("Writing option bytes to %#10x\n", addr); + + /* Set the Option PG bit to enable programming */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OPTPG) | (1 << FLASH_CR_OPTWRE)); + + /* Use flash loader for write OP + * because flash memory writable by half word */ + flash_loader_t fl; + ret = stlink_flash_loader_init(sl, &fl); + if (ret) { + return ret; + } + ret = stlink_flash_loader_run(sl, &fl, addr, base, len); + if (ret) { + return ret; + } + + /* Reload option bytes */ + stlink_write_debug32(sl, FLASH_CR, (1 << FLASH_CR_OBL_LAUNCH)); + + return check_flash_error(sl); +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + /* Write options bytes */ + uint32_t val; + int ret = 0; + (void)len; + uint32_t data; + + clear_flash_error(sl); + + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); + + // Set Options Start bit + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + + // Reload options + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t flash_base = get_stm32l0_flash_base(sl); + uint32_t val; + uint32_t data; + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + while (len != 0) { + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, addr, data); + wait_flash_busy(sl); + + if ((ret = check_flash_error(sl))) { + break; + } + + len -= 4; + addr += 4; + base += 4; + } + + // Reload options + stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); + val |= (1 << STM32L0_FLASH_OBL_LAUNCH); + stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); + + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + + uint32_t val; + int ret = 0; + (void)addr; + (void)len; + + // Clear errors + clear_flash_error(sl); + + // write options bytes + uint32_t data; + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes 0x%04x\n", data); + stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); + + // set options start bit + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + + wait_flash_busy(sl); + ret = check_flash_error(sl); + + // apply options bytes immediate + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t option_byte; + int ret = 0; + (void)addr; + (void)len; + + // Clear errors + clear_flash_error(sl); + + write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); + + // write option byte, ensuring we dont lock opt, and set strt bit + stlink_write_debug32(sl, FLASH_F4_OPTCR, + (option_byte & ~(1 << FLASH_F4_OPTCR_LOCK)) | + (1 << FLASH_F4_OPTCR_START)); + + wait_flash_busy(sl); + ret = check_flash_error(sl); + + // option bytes are reloaded at reset only, no obl. */ + return (ret); +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t option_byte; + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), + addr); + write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); + ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); + + if (addr == 0) { + addr = FLASH_F7_OPTCR; + ILOG("No address provided, using %#10x\n", addr); + } + + if (addr == FLASH_F7_OPTCR) { + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (option_byte & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + } else if (addr == FLASH_F7_OPTCR1) { + // Read FLASH_F7_OPTCR + uint32_t oldvalue; + stlink_read_debug32(sl, FLASH_F7_OPTCR, &oldvalue); + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_byte); + // Write FLASH_F7_OPTCR lock and start address + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (oldvalue & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + } else { + WLOG("WIP: write %#010x to address %#010x\n", option_byte, addr); + stlink_write_debug32(sl, addr, option_byte); + } + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, + addr); + + /* option bytes are reloaded at reset only, no obl. */ + + return ret; +} + +/** + * Write STM32H7xx option bytes + * @param sl + * @param base option bytes to write + * @param addr of the memory mapped option bytes + * @param len number of bytes to write (must be multiple of 4) + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + uint32_t val; + uint32_t data; + + // Wait until previous flash option has completed + wait_flash_busy(sl); + + // Clear previous error + stlink_write_debug32(sl, FLASH_H7_OPTCCR, + 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + + while (len != 0) { + switch (addr) { + case FLASH_H7_REGS_ADDR + 0x20: // FLASH_OPTSR_PRG + case FLASH_H7_REGS_ADDR + 0x2c: // FLASH_PRAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x34: // FLASH_SCAR_PRG1 + case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 + case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG + /* Write to FLASH_xxx_PRG registers */ + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + + /* Skip if the value in the CUR register is identical */ + stlink_read_debug32(sl, addr - 4, &val); + if (val == data) { + break; + } + + /* Write new option byte values and start modification */ + stlink_write_debug32(sl, addr, data); + stlink_read_debug32(sl, FLASH_H7_OPTCR, &val); + val |= (1 << FLASH_H7_OPTCR_OPTSTART); + stlink_write_debug32(sl, FLASH_H7_OPTCR, val); + + /* Wait for the option bytes modification to complete */ + do { + stlink_read_debug32(sl, FLASH_H7_OPTSR_CUR, &val); + } while ((val & (1 << FLASH_H7_OPTSR_OPT_BUSY)) != 0); + + /* Check for errors */ + if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { + stlink_write_debug32(sl, FLASH_H7_OPTCCR, + 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + return -1; + } + break; + + default: + /* Skip non-programmable registers */ + break; + } + + len -= 4; + addr += 4; + base += 4; + } + + return 0; +} + +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len) { + int ret = -1; + + if (sl->option_base == 0) { + ELOG( + "Option bytes writing is currently not supported for connected chip\n"); + return (-1); + } + + if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { + ELOG("Option bytes start address out of Option bytes range\n"); + return (-1); + } + + if (addr + len > sl->option_base + sl->option_size) { + ELOG("Option bytes data too long\n"); + return (-1); + } + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return (-1); + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return (-1); + } + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + ret = stlink_write_option_bytes_f0(sl, base, addr, len); + break; + case STM32_FLASH_TYPE_F2_F4: + ret = stlink_write_option_bytes_f4(sl, base, addr, len); + break; + case STM32_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_f7(sl, base, addr, len); + break; + case STM32_FLASH_TYPE_L0_L1: + ret = stlink_write_option_bytes_l0(sl, base, addr, len); + break; + case STM32_FLASH_TYPE_L4_L4P: + ret = stlink_write_option_bytes_l4(sl, base, addr, len); + break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + ret = stlink_write_option_bytes_gx(sl, base, addr, len); + break; + case STM32_FLASH_TYPE_H7: + ret = stlink_write_option_bytes_h7(sl, base, addr, len); + break; + default: + ELOG("Option bytes writing is currently not implemented for connected " + "chip\n"); + break; + } + + if (ret) { + ELOG("Flash option write failed!\n"); + } else { + ILOG("Wrote %d option bytes to %#010x!\n", len, addr); + } + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register_f0(stlink_t *sl, + uint32_t option_control_register) { + int ret = 0; + uint16_t opt_val[8]; + unsigned protection, optiondata; + uint16_t user_options, user_data, rdp; + unsigned option_offset, user_data_offset; + + ILOG("Asked to write option control register %#10x to %#010x.\n", + option_control_register, FLASH_OBR); + + /* Clear errors */ + clear_flash_error(sl); + + /* Retrieve current values */ + ret = stlink_read_debug32(sl, FLASH_OBR, &optiondata); + if (ret) { + return ret; + } + ret = stlink_read_debug32(sl, FLASH_WRPR, &protection); + if (ret) { + return ret; + } + + /* Translate OBR value to flash store structure + * F0: RM0091, Option byte description, pp. 75-78 + * F1: PM0075, Option byte description, pp. 19-22 + * F3: RM0316, Option byte description, pp. 85-87 */ + switch(sl->chip_id) + { + case 0x422: /* STM32F30x */ + case 0x432: /* STM32F37x */ + case 0x438: /* STM32F303x6/8 and STM32F328 */ + case 0x446: /* STM32F303xD/E and STM32F398xE */ + case 0x439: /* STM32F302x6/8 */ + case 0x440: /* STM32F05x */ + case 0x444: /* STM32F03x */ + case 0x445: /* STM32F04x */ + case 0x448: /* STM32F07x */ + case 0x442: /* STM32F09x */ + option_offset = 6; + user_data_offset = 16; + rdp = 0x55AA; + break; + default: + option_offset = 0; + user_data_offset = 10; + rdp = 0x5AA5; + break; + } + + user_options = (option_control_register >> option_offset >> 2) & 0xFFFF; + user_data = (option_control_register >> user_data_offset) & 0xFFFF; + +#define VAL_WITH_COMPLEMENT(v) (uint16_t)(((v)&0xFF) | (((~(v))<<8)&0xFF00)) + + opt_val[0] = (option_control_register & (1 << 1/*OPT_READOUT*/)) ? 0xFFFF : rdp; + opt_val[1] = VAL_WITH_COMPLEMENT(user_options); + opt_val[2] = VAL_WITH_COMPLEMENT(user_data); + opt_val[3] = VAL_WITH_COMPLEMENT(user_data >> 8); + opt_val[4] = VAL_WITH_COMPLEMENT(protection); + opt_val[5] = VAL_WITH_COMPLEMENT(protection >> 8); + opt_val[6] = VAL_WITH_COMPLEMENT(protection >> 16); + opt_val[7] = VAL_WITH_COMPLEMENT(protection >> 24); + +#undef VAL_WITH_COMPLEMENT + + /* Write bytes and check errors */ + ret = stlink_write_option_bytes_f0(sl, (uint8_t*)opt_val, STM32_F0_OPTION_BYTES_BASE, sizeof(opt_val)); + if (ret) + return ret; + + ret = check_flash_error(sl); + if (!ret) { + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, + FLASH_OBR); + } + + return ret; +} + + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register1_f7(stlink_t *sl, + uint32_t option_control_register1) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#010x to %#010x.\n", + option_control_register1, FLASH_F7_OPTCR1); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + uint32_t current_control_register_value; + stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); + + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); + stlink_write_debug32( + sl, FLASH_F7_OPTCR, + (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, + FLASH_F7_OPTCR1); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register_f7(stlink_t *sl, + uint32_t option_control_register) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", + option_control_register, FLASH_F7_OPTCR); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, + FLASH_F7_OPTCR); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_control_register32(stlink_t *sl, + uint32_t option_control_register) { + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + ret = stlink_write_option_control_register_f0(sl, option_control_register); + break; + case STM32_FLASH_TYPE_F7: + ret = stlink_write_option_control_register_f7(sl, option_control_register); + break; + default: + ELOG("Option control register writing is currently not implemented for " + "connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register %#010x!\n", option_control_register); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_control_register1_32( + stlink_t *sl, uint32_t option_control_register1) { + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F7: + ret = + stlink_write_option_control_register1_f7(sl, option_control_register1); + break; + default: + ELOG("Option control register 1 writing is currently not implemented for " + "connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); + + lock_flash_option(sl); + lock_flash(sl); + + return (ret); +} + + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_bytes_boot_add_f7(stlink_t *sl, + uint32_t option_byte_boot_add) { + ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); + return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); +} + +/** + * Write option bytes + * @param sl + * @param option bytes boot address to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes_boot_add32(stlink_t *sl, + uint32_t option_bytes_boot_add) { + int ret = -1; + + wait_flash_busy(sl); + + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } + + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); + return -1; + } + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F7: + ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); + break; + default: + ELOG("Option bytes boot address writing is currently not implemented for " + "connected chip\n"); + break; + } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; +} + +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { + WLOG("About to write option byte %#10x to %#10x.\n", option_byte, + sl->option_base); + return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, + 4); +} + +/** + * Write the given binary file with option bytes + * @param sl + * @param path readable file path, should be binary image + * @param addr of the memory mapped option bytes + * @return 0 on success, -ve on failure. + */ +int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, + stm32_addr_t addr) { + /* Write the file in flash at addr */ + int err; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; + + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return (-1); + } + + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); + + err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); + + return (err); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register1_f7(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register 1 byte from %#10x\n", + FLASH_F7_OPTCR1); + return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register1_32(stlink_t *sl, + uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F7: + return stlink_read_option_control_register1_f7(sl, option_byte); + default: + return -1; + // return stlink_read_option_control_register1_generic(sl, option_byte); + } +} + + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option byte boot address\n"); + return stlink_read_option_control_register1_f7(sl, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes boot address read is currently not supported for " + "connected chip\n"); + return -1; + } + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F7: + return stlink_read_option_bytes_boot_add_f7(sl, option_byte); + default: + return -1; + // return stlink_read_option_bytes_boot_add_generic(sl, option_byte); + } +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f7(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); + return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f0(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); + return stlink_read_debug32(sl, FLASH_OBR, option_byte); +} + +/** + * Read option bytes + * @param sl + * @param option_byte option value + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + return stlink_read_option_control_register_f0(sl, option_byte); + case STM32_FLASH_TYPE_F7: + return stlink_read_option_control_register_f7(sl, option_byte); + default: + return -1; + } +} diff --git a/src/read_write.c b/src/read_write.c new file mode 100644 index 000000000..f20d76aab --- /dev/null +++ b/src/read_write.c @@ -0,0 +1,143 @@ +#include +#include +#include + +// Endianness +// https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html +// These functions encode and decode little endian uint16 and uint32 values. + +void write_uint32(unsigned char *buf, uint32_t ui) { + buf[0] = ui; + buf[1] = ui >> 8; + buf[2] = ui >> 16; + buf[3] = ui >> 24; +} + +void write_uint16(unsigned char *buf, uint16_t ui) { + buf[0] = (uint8_t)ui; + buf[1] = (uint8_t)(ui >> 8); +} + +uint32_t read_uint32(const unsigned char *c, const int pt) { + return ((uint32_t)c[pt]) | ((uint32_t)c[pt + 1] << 8) | + ((uint32_t)c[pt + 2] << 16) | ((uint32_t)c[pt + 3] << 24); +} + +uint16_t read_uint16(const unsigned char *c, const int pt) { + return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); +} + +int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { + int ret; + + ret = sl->backend->read_debug32(sl, addr, data); + if (!ret) + DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); + + return (ret); +} + +int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { + DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); + return sl->backend->write_debug32(sl, addr, data); +} + +int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); + + if (len % 4 != 0) { + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return (-1); + } + + return (sl->backend->write_mem32(sl, addr, len)); +} + +int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_read_mem32 ***\n"); + + if (len % 4 != 0) { // !!! never ever: fw gives just wrong values + ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); + return (-1); + } + + return (sl->backend->read_mem32(sl, addr, len)); +} + +int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_write_mem8 ***\n"); + return (sl->backend->write_mem8(sl, addr, len)); +} + +int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { + DLOG("*** stlink_read_all_regs ***\n"); + return (sl->backend->read_all_regs(sl, regp)); +} + +int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { + DLOG("*** stlink_read_all_unsupported_regs ***\n"); + return (sl->backend->read_all_unsupported_regs(sl, regp)); +} + +int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { + DLOG("*** stlink_write_reg\n"); + return (sl->backend->write_reg(sl, reg, idx)); +} + +int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { + DLOG("*** stlink_read_reg\n"); + DLOG(" (%d) ***\n", r_idx); + + if (r_idx > 20 || r_idx < 0) { + fprintf(stderr, "Error: register index must be in [0..20]\n"); + return (-1); + } + + return (sl->backend->read_reg(sl, r_idx, regp)); +} + +int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, + struct stlink_reg *regp) { + int r_convert; + + DLOG("*** stlink_read_unsupported_reg\n"); + DLOG(" (%d) ***\n", r_idx); + + /* Convert to values used by STLINK_REG_DCRSR */ + if (r_idx >= 0x1C && + r_idx <= 0x1F) { // primask, basepri, faultmask, or control + r_convert = 0x14; + } else if (r_idx == 0x40) { // FPSCR + r_convert = 0x21; + } else if (r_idx >= 0x20 && r_idx < 0x40) { + r_convert = 0x40 + (r_idx - 0x20); + } else { + fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); + return (-1); + } + + return (sl->backend->read_unsupported_reg(sl, r_convert, regp)); +} + +int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, + struct stlink_reg *regp) { + int r_convert; + + DLOG("*** stlink_write_unsupported_reg\n"); + DLOG(" (%d) ***\n", r_idx); + + /* Convert to values used by STLINK_REG_DCRSR */ + if (r_idx >= 0x1C && + r_idx <= 0x1F) { /* primask, basepri, faultmask, or control */ + r_convert = r_idx; // the backend function handles this + } else if (r_idx == 0x40) { // FPSCR + r_convert = 0x21; + } else if (r_idx >= 0x20 && r_idx < 0x40) { + r_convert = 0x40 + (r_idx - 0x20); + } else { + fprintf(stderr, "Error: register address must be in [0x1C..0x40]\n"); + return (-1); + } + + return (sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); +} diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 458e7c3e2..f8e1b3444 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -4,7 +4,8 @@ #include #include -/** Chipid parametres */ + +/** Chipid parameters */ struct stlink_chipid_params { char *dev_type; char *ref_manual_id; @@ -22,6 +23,6 @@ struct stlink_chipid_params { }; struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); - void init_chipids(char *dir_to_scan); + void init_chipids(char *dir_to_scan); #endif // STLINK_CHIPID_H_ diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index e07918800..2e99e82be 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1134,33 +1134,8 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, #endif libusb_device **list = NULL; - // TODO: We should use ssize_t and use it as a counter if > 0. - // As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) - int cnt = (int)libusb_get_device_list(slu->libusb_ctx, &list); + ssize_t cnt = libusb_get_device_list(slu->libusb_ctx, &list); struct libusb_device_descriptor desc; - int devBus = 0; - int devAddr = 0; - - // TODO: Reading a environment variable in a usb open function is not very nice, this should - // be refactored and moved into the CLI tools, and instead of giving USB_BUS:USB_ADDR a real - // stlink serial string should be passed to this function. Probably people are using this - // but this is very odd because as programmer can change to multiple busses and it is better - // to detect them based on serial. - char *device = getenv("STLINK_DEVICE"); - - if (device) { - char *c = strchr(device, ':'); - - if (c == NULL) { - WLOG("STLINK_DEVICE must be : format\n"); - goto on_error; - } - - devBus = atoi(device); - *c++ = 0; - devAddr = atoi(c); - ILOG("bus %03d dev %03d\n", devBus, devAddr); - } while (cnt-- > 0) { struct libusb_device_handle *handle; @@ -1169,13 +1144,6 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, if (desc.idVendor != STLINK_USB_VID_ST) { continue; } - if (devBus && devAddr) { - if ((libusb_get_bus_number(list[cnt]) != devBus) || - (libusb_get_device_address(list[cnt]) != devAddr)) { - continue; - } - } - ret = libusb_open(list[cnt], &handle); if (ret) { continue; } // could not open device @@ -1202,7 +1170,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, } if (cnt < 0) { - WLOG ("Couldn't find %s ST-Link devices\n", (devBus && devAddr) ? "matched" : "any"); + WLOG ("Couldn't find any ST-Link devices\n"); libusb_free_device_list(list, 1); goto on_error; } else { @@ -1221,6 +1189,8 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, libusb_free_device_list(list, 1); +// libusb_kernel_driver_active is not available on Windows. +#if !defined(_WIN32) if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { ret = libusb_detach_kernel_driver(slu->usb_handle, 0); @@ -1229,6 +1199,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, goto on_libusb_error; } } +#endif if (libusb_get_configuration(slu->usb_handle, &config)) { // this may fail for a previous configured device @@ -1287,7 +1258,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, // the NRST pin must be pull down before selecting the SWD/JTAG mode if (mode == STLINK_DEV_DEBUG_MODE) { DLOG("-- exit_debug_mode\n"); - _stlink_usb_exit_dfu_mode(sl); + _stlink_usb_exit_debug_mode(sl); } _stlink_usb_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); diff --git a/src/stlink-lib/usb.c.bak b/src/stlink-lib/usb.c.bak new file mode 100644 index 000000000..32ceff71f --- /dev/null +++ b/src/stlink-lib/usb.c.bak @@ -0,0 +1,1410 @@ +#include +#include +#include +#include +#include + +#if !defined(_MSC_VER) +#include +#endif + +#include +#include +#include + +#if defined(_WIN32) +#include +#endif + +#include +#include +#include "usb.h" + +enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; + +static inline uint32_t le_to_h_u32(const uint8_t* buf) { + return((uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24)); +} + +static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, uint32_t khz) { + unsigned int i; + int speed_index = -1; + int speed_diff = INT_MAX; + int last_valid_speed = -1; + bool match = true; + + for (i = 0; i < map_size; i++) { + if (!map[i]) { continue; } + + last_valid_speed = i; + + if (khz == map[i]) { + speed_index = i; + break; + } else { + int current_diff = khz - map[i]; + // get abs value for comparison + current_diff = (current_diff > 0) ? current_diff : -current_diff; + + if (current_diff < speed_diff) { + speed_diff = current_diff; + speed_index = i; + } + } + } + + if (speed_index == -1) { + // This will only be here if we cannot match the slow speed. + // Use the slowest speed we support. + speed_index = last_valid_speed; + match = false; + } else if (i == map_size) { + match = false; + } + + if (!match) { + ILOG("Unable to match requested speed %d kHz, using %d kHz\n", khz, map[speed_index]); + } + + return(speed_index); +} + +void _stlink_usb_close(stlink_t* sl) { + if (!sl) { return; } + + struct stlink_libusb * const handle = sl->backend_data; + + // maybe we couldn't even get the usb device? + if (handle != NULL) { + if (handle->usb_handle != NULL) { libusb_close(handle->usb_handle); } + + libusb_exit(handle->libusb_ctx); + free(handle); + } +} + +ssize_t send_recv(struct stlink_libusb* handle, int terminate, + unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, + size_t rxsize, int check_error, const char *cmd) { + // Note: txbuf and rxbuf can point to the same area + int res, t, retry = 0; + + while (1) { + res = 0; + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int)txsize, &res, 3000); + + if (t) { + ELOG("%s send request failed: %s\n", cmd, libusb_error_name(t)); + return(-1); + } else if ((size_t)res != txsize) { + ELOG("%s send request wrote %u bytes, instead of %u\n", + cmd, (unsigned int)res, (unsigned int)txsize); + } + + if (rxsize != 0) { + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int)rxsize, &res, 3000); + + if (t) { + ELOG("%s read reply failed: %s\n", cmd, libusb_error_name(t)); + return(-1); + } + + /* Checking the command execution status stored in the first byte of the response */ + if (handle->protocoll != 1 && check_error >= CMD_CHECK_STATUS && + rxbuf[0] != STLINK_DEBUG_ERR_OK) { + switch(rxbuf[0]) { + case STLINK_DEBUG_ERR_AP_WAIT: + case STLINK_DEBUG_ERR_DP_WAIT: + if (check_error == CMD_CHECK_RETRY && retry < 3) { + unsigned int delay_us = (1<protocoll == 1) && terminate) { + // read the SG reply + unsigned char sg_buf[13]; + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); + + if (t) { + ELOG("%s read storage failed: %s\n", cmd, libusb_error_name(t)); + return(-1); + } + + // The STLink doesn't seem to evaluate the sequence number. + handle->sg_transfer_idx++; + } + + return(res); + } +} + +static inline int send_only(struct stlink_libusb* handle, int terminate, + unsigned char* txbuf, size_t txsize, + const char *cmd) { + return((int)send_recv(handle, terminate, txbuf, txsize, NULL, 0, CMD_CHECK_NO, cmd)); +} + + +static int fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t len) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + int i = 0; + memset(cmd, 0, sizeof(sl->c_buf)); + + if (slu->protocoll == 1) { + cmd[i++] = 'U'; + cmd[i++] = 'S'; + cmd[i++] = 'B'; + cmd[i++] = 'C'; + write_uint32(&cmd[i], slu->sg_transfer_idx); + write_uint32(&cmd[i + 4], len); + i += 8; + cmd[i++] = (dir == SG_DXFER_FROM_DEV) ? 0x80 : 0; + cmd[i++] = 0; // logical unit + cmd[i++] = 0xa; // command length + } + return(i); +} + +int _stlink_usb_version(stlink_t *sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + uint32_t rep_len; + int i; + + if (sl->version.stlink_v == 3) { + // STLINK-V3 version is determined by another command + rep_len = 12; + i = fill_command(sl, SG_DXFER_FROM_DEV, 16); + cmd[i++] = STLINK_GET_VERSION_APIV3; + } else { + rep_len = 6; + i = fill_command(sl, SG_DXFER_FROM_DEV, 6); + cmd[i++] = STLINK_GET_VERSION; + } + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_REP_LEN, "GET_VERSION"); + + return(size<0?-1:0); +} + +int32_t _stlink_usb_target_voltage(stlink_t *sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const rdata = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + uint32_t rep_len = 8; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + uint32_t factor, reading; + int voltage; + + cmd[i++] = STLINK_GET_TARGET_VOLTAGE; + + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_REP_LEN, "GET_TARGET_VOLTAGE"); + + if (size < 0) { + return(-1); + } + + factor = (rdata[3] << 24) | (rdata[2] << 16) | (rdata[1] << 8) | (rdata[0] << 0); + reading = (rdata[7] << 24) | (rdata[6] << 16) | (rdata[5] << 8) | (rdata[4] << 0); + voltage = 2400 * reading / factor; + + return(voltage); +} + +int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const rdata = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + const int rep_len = 8; + + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_READDEBUGREG; + write_uint32(&cmd[i], addr); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "READDEBUGREG"); + + if (size < 0) { + return(-1); + } + + *data = read_uint32(rdata, 4); + + return(0); +} + +int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const rdata = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + const int rep_len = 2; + + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; + write_uint32(&cmd[i], addr); + write_uint32(&cmd[i + 4], data); + size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "WRITEDEBUGREG"); + + return(size<0?-1:0); +} + +int _stlink_usb_get_rw_status(stlink_t *sl) { + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return(0); } + + unsigned char* const rdata = sl->q_buf; + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + int i; + int16_t ret = 0; + + i = fill_command(sl, SG_DXFER_FROM_DEV, 12); + cmd[i++] = STLINK_DEBUG_COMMAND; + + if (sl->version.flags & STLINK_F_HAS_GETLASTRWSTATUS2) { + cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS2; + ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 12, CMD_CHECK_STATUS, "GETLASTRWSTATUS2"); + } else { + cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS; + ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2, CMD_CHECK_STATUS, "GETLASTRWSTATUS"); + } + + return(ret<0?-1:0); +} + +int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + int i, ret; + + i = fill_command(sl, SG_DXFER_TO_DEV, len); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_WRITEMEM_32BIT; + write_uint32(&cmd[i], addr); + write_uint16(&cmd[i + 4], len); + ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_32BIT"); + + if (ret == -1) { return(ret); } + + ret = send_only(slu, 1, data, len, "WRITEMEM_32BIT"); + + if (ret == -1) { return(ret); } + + return(_stlink_usb_get_rw_status(sl)); +} + +int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + int i, ret; + + if ((sl->version.jtag_api < STLINK_JTAG_API_V3 && len > 64) || + (sl->version.jtag_api >= STLINK_JTAG_API_V3 && len > 512)) { + ELOG("WRITEMEM_8BIT: bulk packet limits exceeded (data len %d byte)\n", len); + return (-1); + } + + i = fill_command(sl, SG_DXFER_TO_DEV, 0); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_WRITEMEM_8BIT; + write_uint32(&cmd[i], addr); + write_uint16(&cmd[i + 4], len); + ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_8BIT"); + + if (ret == -1) { return(ret); } + + ret = send_only(slu, 1, data, len, "WRITEMEM_8BIT"); + + if (ret == -1) { return(ret); } + + return(0); +} + + +int _stlink_usb_current_mode(stlink_t * sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + unsigned char* const data = sl->q_buf; + ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_GET_CURRENT_MODE; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_CURRENT_MODE"); + + if (size < 0) { + return(-1); + } + + return(sl->q_buf[0]); +} + +int _stlink_usb_core_id(stlink_t * sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + unsigned char* const data = sl->q_buf; + ssize_t size; + int offset, rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 12; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { + cmd[i++] = STLINK_DEBUG_READCOREID; + offset = 0; + } else { + cmd[i++] = STLINK_DEBUG_APIV2_READ_IDCODES; + offset = 4; + } + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READ_IDCODES"); + + if (size < 0) { + return(-1); + } + + sl->core_id = read_uint32(data, offset); + + return(0); +} + +int _stlink_usb_status_v2(stlink_t *sl) { + int result; + uint32_t status = 0; + + result = _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &status); + DLOG("core status: %08X\n", status); + + if (result != 0) { + sl->core_stat = TARGET_UNKNOWN; + } else { + if (status & STLINK_REG_DHCSR_C_HALT) { + sl->core_stat = TARGET_HALTED; + } else if (status & STLINK_REG_DHCSR_S_RESET_ST) { + sl->core_stat = TARGET_RESET; + } else { + sl->core_stat = TARGET_RUNNING; + } + } + + return(result); +} + +int _stlink_usb_status(stlink_t * sl) { + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { return(_stlink_usb_status_v2(sl)); } + + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_GETSTATUS; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GETSTATUS"); + + if (size > 1) { + if (sl->q_buf[0] == STLINK_CORE_RUNNING) { + sl->core_stat = TARGET_RUNNING; + } else if (sl->q_buf[0] == STLINK_CORE_HALTED) { + sl->core_stat = TARGET_HALTED; + } else { + sl->core_stat = TARGET_UNKNOWN; + } + } else { + sl->core_stat = TARGET_UNKNOWN; + } + + return(size<0?-1:0); +} + +int _stlink_usb_force_debug(stlink_t *sl) { + struct stlink_libusb *slu = sl->backend_data; + + int res; + + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { + res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); + return(res); + } + + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_FORCEDEBUG; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "FORCEDEBUG"); + + return(size<0?-1:0); +} + +int _stlink_usb_enter_swd_mode(stlink_t * sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + unsigned char* const data = sl->q_buf; + const uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + // select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). + cmd[i++] = sl->version.jtag_api == STLINK_JTAG_API_V1 ? STLINK_DEBUG_APIV1_ENTER : STLINK_DEBUG_APIV2_ENTER; + cmd[i++] = STLINK_DEBUG_ENTER_SWD; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "ENTER_SWD"); + + return(size<0?-1:0); +} + +int _stlink_usb_exit_dfu_mode(stlink_t* sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + + cmd[i++] = STLINK_DFU_COMMAND; + cmd[i++] = STLINK_DFU_EXIT; + size = send_only(slu, 1, cmd, slu->cmd_len, "DFU_EXIT"); + + return(size<0?-1:0); +} + + +int _stlink_usb_reset(stlink_t * sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int i, rep_len = 2; + + // send reset command + i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + cmd[i++] = STLINK_DEBUG_COMMAND; + + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { + cmd[i++] = STLINK_DEBUG_APIV1_RESETSYS; + } else { + cmd[i++] = STLINK_DEBUG_APIV2_RESETSYS; + } + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RESETSYS"); + + return(size<0?-1:0); +} + +int _stlink_usb_jtag_reset(stlink_t * sl, int value) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_DRIVE_NRST; + cmd[i++] = value; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "DRIVE_NRST"); + + return(size<0?-1:0); +} + + +int _stlink_usb_step(stlink_t* sl) { + struct stlink_libusb * const slu = sl->backend_data; + + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { + // emulates the JTAG v1 API by using DHCSR + _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN); + _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_STEP | + STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN); + return _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_DEBUGEN); + } + + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_STEPCORE; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "STEPCORE"); + + return(size<0?-1:0); +} + +/** + * This seems to do a good job of restarting things from the beginning? + * @param sl + * @param type + */ +int _stlink_usb_run(stlink_t* sl, enum run_type type) { + struct stlink_libusb * const slu = sl->backend_data; + + int res; + + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { + res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + ((type==RUN_FLASH_LOADER)?STLINK_REG_DHCSR_C_MASKINTS:0)); + return(res); + } + + + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_RUNCORE; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RUNCORE"); + + return(size<0?-1:0); +} + +int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int rep_len = 2; + int i; + + // clock speed only supported by stlink/v2 and for firmware >= 22 + if (sl->version.stlink_v == 2 && sl->version.jtag_v >= 22) { + uint16_t clk_divisor; + if (clk_freq) { + const uint32_t map[] = {5, 15, 25, 50, 100, 125, 240, 480, 950, 1200, 1800, 4000}; + int speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); + switch (map[speed_index]) { + case 5: clk_divisor = STLINK_SWDCLK_5KHZ_DIVISOR; break; + case 15: clk_divisor = STLINK_SWDCLK_15KHZ_DIVISOR; break; + case 25: clk_divisor = STLINK_SWDCLK_25KHZ_DIVISOR; break; + case 50: clk_divisor = STLINK_SWDCLK_50KHZ_DIVISOR; break; + case 100: clk_divisor = STLINK_SWDCLK_100KHZ_DIVISOR; break; + case 125: clk_divisor = STLINK_SWDCLK_125KHZ_DIVISOR; break; + case 240: clk_divisor = STLINK_SWDCLK_240KHZ_DIVISOR; break; + case 480: clk_divisor = STLINK_SWDCLK_480KHZ_DIVISOR; break; + case 950: clk_divisor = STLINK_SWDCLK_950KHZ_DIVISOR; break; + case 1200: clk_divisor = STLINK_SWDCLK_1P2MHZ_DIVISOR; break; + default: + case 1800: clk_divisor = STLINK_SWDCLK_1P8MHZ_DIVISOR; break; + case 4000: clk_divisor = STLINK_SWDCLK_4MHZ_DIVISOR; break; + } + } else + clk_divisor = STLINK_SWDCLK_1P8MHZ_DIVISOR; + + i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_SWD_SET_FREQ; + cmd[i++] = clk_divisor & 0xFF; + cmd[i++] = (clk_divisor >> 8) & 0xFF; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "SWD_SET_FREQ"); + + return(size<0?-1:0); + } else if (sl->version.stlink_v == 3) { + int speed_index; + uint32_t map[STLINK_V3_MAX_FREQ_NB]; + i = fill_command(sl, SG_DXFER_FROM_DEV, 16); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV3_GET_COM_FREQ; + cmd[i++] = 0; // SWD mode + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52, CMD_CHECK_STATUS, "GET_COM_FREQ"); + + if (size < 0) { + return(-1); + } + + int speeds_size = data[8]; + if (speeds_size > STLINK_V3_MAX_FREQ_NB) { + speeds_size = STLINK_V3_MAX_FREQ_NB; + } + + for (i = 0; i < speeds_size; i++) map[i] = le_to_h_u32(&data[12 + 4 * i]); + + // Set to zero all the next entries + for (i = speeds_size; i < STLINK_V3_MAX_FREQ_NB; i++) map[i] = 0; + + if (!clk_freq) clk_freq = 1000; // set default frequency + speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); + + i = fill_command(sl, SG_DXFER_FROM_DEV, 16); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV3_SET_COM_FREQ; + cmd[i++] = 0; // SWD mode + cmd[i++] = 0; + cmd[i++] = (uint8_t)((map[speed_index] >> 0) & 0xFF); + cmd[i++] = (uint8_t)((map[speed_index] >> 8) & 0xFF); + cmd[i++] = (uint8_t)((map[speed_index] >> 16) & 0xFF); + cmd[i++] = (uint8_t)((map[speed_index] >> 24) & 0xFF); + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8, CMD_CHECK_STATUS, "SET_COM_FREQ"); + + return(size<0?-1:0); + } else if (clk_freq) { + WLOG("ST-Link firmware does not support frequency setup\n"); + } + + return(-1); +} + +int _stlink_usb_exit_debug_mode(stlink_t *sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_EXIT; + + size = send_only(slu, 1, cmd, slu->cmd_len, "DEBUG_EXIT"); + + return(size<0?-1:0); +} + +int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + int i = fill_command(sl, SG_DXFER_FROM_DEV, len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_READMEM_32BIT; + write_uint32(&cmd[i], addr); + write_uint16(&cmd[i + 4], len); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, len, CMD_CHECK_NO, "READMEM_32BIT"); + + if (size < 0) { + return(-1); + } + + sl->q_len = (int)size; + stlink_print_data(sl); + + return(0); +} + +int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const cmd = sl->c_buf; + unsigned char* const data = sl->q_buf; + ssize_t size; + uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 84 : 88; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { + cmd[i++] = STLINK_DEBUG_APIV1_READALLREGS; + } else { + cmd[i++] = STLINK_DEBUG_APIV2_READALLREGS; + } + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READALLREGS"); + + if (size < 0) { + return(-1); + } + + /* V1: regs data from offset 0 */ + /* V2: status at offset 0, regs data from offset 4 */ + int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; + sl->q_len = (int)size; + stlink_print_data(sl); + + for (i = 0; i < 16; i++) regp->r[i] = read_uint32(sl->q_buf, reg_offset + i * 4); + + regp->xpsr = read_uint32(sl->q_buf, reg_offset + 64); + regp->main_sp = read_uint32(sl->q_buf, reg_offset + 68); + regp->process_sp = read_uint32(sl->q_buf, reg_offset + 72); + regp->rw = read_uint32(sl->q_buf, reg_offset + 76); + regp->rw2 = read_uint32(sl->q_buf, reg_offset + 80); + + if (sl->verbose < 2) { return(0); } + + DLOG("xpsr = 0x%08x\n", regp->xpsr); + DLOG("main_sp = 0x%08x\n", regp->main_sp); + DLOG("process_sp = 0x%08x\n", regp->process_sp); + DLOG("rw = 0x%08x\n", regp->rw); + DLOG("rw2 = 0x%08x\n", regp->rw2); + + return(0); +} + +int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + uint32_t r; + uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 8; + int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { + cmd[i++] = STLINK_DEBUG_APIV1_READREG; + } else { + cmd[i++] = STLINK_DEBUG_APIV2_READREG; + } + + cmd[i++] = (uint8_t)r_idx; + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "READREG"); + + if (size < 0) { + return(-1); + } + + sl->q_len = (int)size; + stlink_print_data(sl); + r = read_uint32(sl->q_buf, reg_offset); + DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); + + switch (r_idx) { + case 16: + regp->xpsr = r; + break; + case 17: + regp->main_sp = r; + break; + case 18: + regp->process_sp = r; + break; + case 19: + regp->rw = r; // XXX ?(primask, basemask etc.) + break; + case 20: + regp->rw2 = r; // XXX ?(primask, basemask etc.) + break; + default: + regp->r[r_idx] = r; + } + + return(0); +} + +/* See section C1.6 of the ARMv7-M Architecture Reference Manual */ +int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { + uint32_t r; + int ret; + + sl->q_buf[0] = (unsigned char)r_idx; + + for (int i = 1; i < 4; i++) sl->q_buf[i] = 0; + + ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); + + if (ret == -1) { return(ret); } + + ret = _stlink_usb_read_mem32(sl, STLINK_REG_DCRDR, 4); + + if (ret == -1) { return(ret); } + + r = read_uint32(sl->q_buf, 0); + DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); + + switch (r_idx) { + case 0x14: + regp->primask = (uint8_t)(r & 0xFF); + regp->basepri = (uint8_t)((r >> 8) & 0xFF); + regp->faultmask = (uint8_t)((r >> 16) & 0xFF); + regp->control = (uint8_t)((r >> 24) & 0xFF); + break; + case 0x21: + regp->fpscr = r; + break; + default: + regp->s[r_idx - 0x40] = r; + break; + } + + return(0); +} + +int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { + int ret; + + ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); + + if (ret == -1) { return(ret); } + + ret = _stlink_usb_read_unsupported_reg(sl, 0x21, regp); + + if (ret == -1) { return(ret); } + + for (int i = 0; i < 32; i++) { + ret = _stlink_usb_read_unsupported_reg(sl, 0x40 + i, regp); + + if (ret == -1) { return(ret); } + } + + return(0); +} + +/* See section C1.6 of the ARMv7-M Architecture Reference Manual */ +int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct stlink_reg *regp) { + int ret; + + if (r_idx >= 0x1C && r_idx <= 0x1F) { // primask, basepri, faultmask, or control + /* These are held in the same register */ + ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); + + if (ret == -1) { return(ret); } + + val = (uint8_t)(val >> 24); + + switch (r_idx) { + case 0x1C: /* control */ + val = (((uint32_t)val) << 24) | + (((uint32_t)regp->faultmask) << 16) | + (((uint32_t)regp->basepri) << 8) | + ((uint32_t)regp->primask); + break; + case 0x1D: /* faultmask */ + val = (((uint32_t)regp->control) << 24) | + (((uint32_t)val) << 16) | + (((uint32_t)regp->basepri) << 8) | + ((uint32_t)regp->primask); + break; + case 0x1E: /* basepri */ + val = (((uint32_t)regp->control) << 24) | + (((uint32_t)regp->faultmask) << 16) | + (((uint32_t)val) << 8) | + ((uint32_t)regp->primask); + break; + case 0x1F: /* primask */ + val = (((uint32_t)regp->control) << 24) | + (((uint32_t)regp->faultmask) << 16) | + (((uint32_t)regp->basepri) << 8) | + ((uint32_t)val); + break; + } + + r_idx = 0x14; + } + + write_uint32(sl->q_buf, val); + + ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRDR, 4); + + if (ret == -1) { return(ret); } + + sl->q_buf[0] = (unsigned char)r_idx; + sl->q_buf[1] = 0; + sl->q_buf[2] = 0x01; + sl->q_buf[3] = 0; + + return(_stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4)); +} + +int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + uint32_t rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { + cmd[i++] = STLINK_DEBUG_APIV1_WRITEREG; + } else { + cmd[i++] = STLINK_DEBUG_APIV2_WRITEREG; + } + + cmd[i++] = idx; + write_uint32(&cmd[i], reg); + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "WRITEREG"); + + return(size<0?-1:0); +} + +int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + uint32_t rep_len = 2; + + int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; + write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); + write_uint32(&cmd[i + 2], frequency); + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "START_TRACE_RX"); + + return(size<0?-1:0); +} + +int _stlink_usb_disable_trace(stlink_t* sl) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + ssize_t size; + uint32_t rep_len = 2; + + int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; + + size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "STOP_TRACE_RX"); + + return(size<0?-1:0); +} + +int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { + struct stlink_libusb * const slu = sl->backend_data; + unsigned char* const data = sl->q_buf; + unsigned char* const cmd = sl->c_buf; + uint32_t rep_len = 2; + int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + + cmd[i++] = STLINK_DEBUG_COMMAND; + cmd[i++] = STLINK_DEBUG_APIV2_GET_TRACE_NB; + ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_TRACE_NB"); + + if (send_size < 0) { + return(-1); + } else if (send_size != 2) { + ELOG("STLINK_DEBUG_APIV2_GET_TRACE_NB reply size %d\n", (int)send_size); + return(-1); + } + + uint16_t trace_count = read_uint16(sl->q_buf, 0); + + if (trace_count > size) { + ELOG("read_trace insufficient buffer length\n"); + return -1; + } + + if (trace_count != 0) { + int res = 0; + int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); + + if (t || res != (int)trace_count) { + ELOG("read_trace read error %d\n", t); + return(-1); + } + } + + return trace_count; +} + +static stlink_backend_t _stlink_usb_backend = { + _stlink_usb_close, + _stlink_usb_exit_debug_mode, + _stlink_usb_enter_swd_mode, + NULL, // don't enter_jtag_mode here... + _stlink_usb_exit_dfu_mode, + _stlink_usb_core_id, + _stlink_usb_reset, + _stlink_usb_jtag_reset, + _stlink_usb_run, + _stlink_usb_status, + _stlink_usb_version, + _stlink_usb_read_debug32, + _stlink_usb_read_mem32, + _stlink_usb_write_debug32, + _stlink_usb_write_mem32, + _stlink_usb_write_mem8, + _stlink_usb_read_all_regs, + _stlink_usb_read_reg, + _stlink_usb_read_all_unsupported_regs, + _stlink_usb_read_unsupported_reg, + _stlink_usb_write_unsupported_reg, + _stlink_usb_write_reg, + _stlink_usb_step, + _stlink_usb_current_mode, + _stlink_usb_force_debug, + _stlink_usb_target_voltage, + _stlink_usb_set_swdclk, + _stlink_usb_enable_trace, + _stlink_usb_disable_trace, + _stlink_usb_read_trace +}; + +/* return the length of serial or (0) in case of errors */ +size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_descriptor *desc, char *serial) { + unsigned char desc_serial[(STLINK_SERIAL_LENGTH) * 2]; + + /* truncate the string in the serial buffer */ + serial[0] = '\0'; + + /* get the LANGID from String Descriptor Zero */ + int ret = libusb_get_string_descriptor(handle, 0, 0, desc_serial, sizeof(desc_serial)); + if (ret < 4) return 0; + + uint32_t langid = desc_serial[2] | (desc_serial[3] << 8); + + /* get the serial */ + ret = libusb_get_string_descriptor(handle, desc->iSerialNumber, langid, desc_serial, + sizeof(desc_serial)); + if (ret < 0) return 0; // could not read serial + + unsigned char len = desc_serial[0]; + + if (len == ((STLINK_SERIAL_LENGTH + 1) * 2)) { /* len == 50 */ + /* good ST-Link adapter */ + ret = libusb_get_string_descriptor_ascii( + handle, desc->iSerialNumber, (unsigned char *)serial, STLINK_SERIAL_BUFFER_SIZE); + if (ret < 0) return 0; + } else if (len == ((STLINK_SERIAL_LENGTH / 2 + 1) * 2)) { /* len == 26 */ + /* fix-up the buggy serial */ + for (unsigned int i = 0; i < STLINK_SERIAL_LENGTH; i += 2) + sprintf(serial + i, "%02X", desc_serial[i + 2]); + serial[STLINK_SERIAL_LENGTH] = '\0'; + } else { + return 0; + } + + return strlen(serial); +} + +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq) { + stlink_t* sl = NULL; + struct stlink_libusb* slu = NULL; + int ret = -1; + int config; + + sl = calloc(1, sizeof(stlink_t)); + if (sl == NULL) { goto on_malloc_error; } + + slu = calloc(1, sizeof(struct stlink_libusb)); + if (slu == NULL) { goto on_malloc_error; } + + ugly_init(verbose); + sl->backend = &_stlink_usb_backend; + sl->backend_data = slu; + + sl->core_stat = TARGET_UNKNOWN; + + if (libusb_init(&(slu->libusb_ctx))) { + WLOG("failed to init libusb context, wrong version of libraries?\n"); + goto on_error; + } + +#if LIBUSB_API_VERSION < 0x01000106 + libusb_set_debug(slu->libusb_ctx, ugly_libusb_log_level(verbose)); +#else + libusb_set_option(slu->libusb_ctx, LIBUSB_OPTION_LOG_LEVEL, ugly_libusb_log_level(verbose)); +#endif + + libusb_device **list = NULL; + // TODO: We should use ssize_t and use it as a counter if > 0. + // As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) + ssize_t cnt = libusb_get_device_list(slu->libusb_ctx, &list); + struct libusb_device_descriptor desc; + + while (cnt-- > 0) { + struct libusb_device_handle *handle; + + libusb_get_device_descriptor(list[cnt], &desc); + + if (desc.idVendor != STLINK_USB_VID_ST) { continue; } + + ret = libusb_open(list[cnt], &handle); + + if (ret) { continue; } // could not open device + + size_t serial_len = stlink_serial(handle, &desc, sl->serial); + + libusb_close(handle); + + if (serial_len != STLINK_SERIAL_LENGTH) { continue; } // could not read the serial + + // if no serial provided, or if serial match device, fixup version and protocol + if (((serial == NULL) || (*serial == 0)) || (memcmp(serial, &sl->serial, STLINK_SERIAL_LENGTH) == 0)) { + if (STLINK_V1_USB_PID(desc.idProduct)) { + slu->protocoll = 1; + sl->version.stlink_v = 1; + } else if (STLINK_V2_USB_PID(desc.idProduct) || STLINK_V2_1_USB_PID(desc.idProduct)) { + sl->version.stlink_v = 2; + } else if (STLINK_V3_USB_PID(desc.idProduct)) { + sl->version.stlink_v = 3; + } + + break; + } + } + + if (cnt < 0) { + WLOG ("Couldn't find any ST-Link devices\n"); + libusb_free_device_list(list, 1); + goto on_error; + } else { + ret = libusb_open(list[cnt], &slu->usb_handle); + + if (ret != 0) { + WLOG("Error %d (%s) opening ST-Link v%d device %03d:%03d\n", ret, + strerror(errno), + sl->version.stlink_v, + libusb_get_bus_number(list[cnt]), + libusb_get_device_address(list[cnt])); + libusb_free_device_list(list, 1); + goto on_error; + } + } + + libusb_free_device_list(list, 1); + +// libusb_kernel_driver_active is not available on Windows. +#if !defined(_WIN32) + if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { + ret = libusb_detach_kernel_driver(slu->usb_handle, 0); + + if (ret < 0) { + WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-ret)); + goto on_libusb_error; + } + } +#endif + + if (libusb_get_configuration(slu->usb_handle, &config)) { + // this may fail for a previous configured device + WLOG("libusb_get_configuration()\n"); + goto on_libusb_error; + } + + if (config != 1) { + printf("setting new configuration (%d -> 1)\n", config); + + if (libusb_set_configuration(slu->usb_handle, 1)) { + // this may fail for a previous configured device + WLOG("libusb_set_configuration() failed\n"); + goto on_libusb_error; + } + } + + if (libusb_claim_interface(slu->usb_handle, 0)) { + WLOG("Stlink usb device found, but unable to claim (probably already in use?)\n"); + goto on_libusb_error; + } + + // TODO: Could use the scanning technique from STM8 code here... + slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; + + if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO || + desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO || + desc.idProduct == STLINK_USB_PID_STLINK_V2_1 || + desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER || + desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID || + desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID || + desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID || + desc.idProduct == STLINK_USB_PID_STLINK_V3_NO_MSD_PID) { + slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; + slu->ep_trace = 2 | LIBUSB_ENDPOINT_IN; + } else { + slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; + slu->ep_trace = 3 | LIBUSB_ENDPOINT_IN; + } + + slu->sg_transfer_idx = 0; + slu->cmd_len = (slu->protocoll == 1) ? STLINK_SG_SIZE : STLINK_CMD_SIZE; + + // initialize stlink version (sl->version) + stlink_version(sl); + + int mode = stlink_current_mode(sl); + if (mode == STLINK_DEV_DFU_MODE) { + DLOG("-- exit_dfu_mode\n"); + _stlink_usb_exit_dfu_mode(sl); + } + + if (connect == CONNECT_UNDER_RESET) { + // for the connect under reset only + // OpenOСD says (official documentation is not available) that + // the NRST pin must be pull down before selecting the SWD/JTAG mode + if (mode == STLINK_DEV_DEBUG_MODE) { + DLOG("-- exit_debug_mode\n"); + _stlink_usb_exit_debug_mode(sl); + } + + _stlink_usb_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); + } + + sl->freq = freq; + // set the speed before entering the mode as the chip discovery phase + // should be done at this speed too + // set the stlink clock speed (default is 1800kHz) + DLOG("JTAG/SWD freq set to %d\n", freq); + _stlink_usb_set_swdclk(sl, freq); + + stlink_target_connect(sl, connect); + return(sl); + +on_libusb_error: + stlink_close(sl); + return(NULL); + +on_error: + if (slu->libusb_ctx) { libusb_exit(slu->libusb_ctx); } + +on_malloc_error: + if (sl != NULL) { free(sl); } + if (slu != NULL) { free(slu); } + + return(NULL); +} + +static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int freq) { + stlink_t **_sldevs; + libusb_device *dev; + int i = 0; + size_t slcnt = 0; + size_t slcur = 0; + + /* Count STLINKs */ + while ((dev = devs[i++]) != NULL) { + struct libusb_device_descriptor desc; + int ret = libusb_get_device_descriptor(dev, &desc); + + if (ret < 0) { + WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); + break; + } + + if (desc.idVendor != STLINK_USB_VID_ST) { continue; } + + if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { + WLOG("skipping ST device : %#04x:%#04x)\n", desc.idVendor, desc.idProduct); + continue; + } + + slcnt++; + } + + _sldevs = calloc(slcnt, sizeof(stlink_t *)); // allocate list of pointers + + if (!_sldevs) { + *sldevs = NULL; + return(0); + } + + /* Open STLINKS and attach them to list */ + i = 0; + + while ((dev = devs[i++]) != NULL) { + struct libusb_device_descriptor desc; + int ret = libusb_get_device_descriptor(dev, &desc); + + if (ret < 0) { + WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); + break; + } + + if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { continue; } + + struct libusb_device_handle* handle; + char serial[STLINK_SERIAL_BUFFER_SIZE] = {0, }; + + ret = libusb_open(dev, &handle); + + if (ret < 0) { + if (ret == LIBUSB_ERROR_ACCESS) { + ELOG("Could not open USB device %#06x:%#06x, access error.\n", desc.idVendor, desc.idProduct); + } else { + ELOG("Failed to open USB device %#06x:%#06x, libusb error: %d)\n", desc.idVendor, desc.idProduct, ret); + } + + break; + } + + size_t serial_len = stlink_serial(handle, &desc, serial); + + libusb_close(handle); + + if (serial_len != STLINK_SERIAL_LENGTH) { continue; } + + stlink_t *sl = stlink_open_usb(0, connect, serial, freq); + + if (!sl) { + ELOG("Failed to open USB device %#06x:%#06x\n", desc.idVendor, desc.idProduct); + continue; + } + + _sldevs[slcur++] = sl; + } + + *sldevs = _sldevs; + + return(slcur); +} + +size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq) { + libusb_device **devs; + stlink_t **sldevs; + + size_t slcnt = 0; + int r; + ssize_t cnt; + + r = libusb_init(NULL); + + if (r < 0) { return(0); } + + cnt = libusb_get_device_list(NULL, &devs); + + if (cnt < 0) { return(0); } + + slcnt = stlink_probe_usb_devs(devs, &sldevs, connect, freq); + libusb_free_device_list(devs, 1); + + libusb_exit(NULL); + + *stdevs = sldevs; + + return(slcnt); +} + +void stlink_probe_usb_free(stlink_t ***stdevs, size_t size) { + if (stdevs == NULL || *stdevs == NULL || size == 0) { return; } + + for (size_t n = 0; n < size; n++) { stlink_close((*stdevs)[n]); } + + free(*stdevs); + *stdevs = NULL; +} diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index 389c44664..cb6da4b8a 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -52,7 +52,7 @@ #define ssize_t int #ifndef SSIZE_MAX -#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 2147483647 : 9223372036854775807) +#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 1073741824 : ‭4611686018427387904‬) #endif #define STDIN_FILENO 0 diff --git a/src/win32/unistd/unistd.h.bak b/src/win32/unistd/unistd.h.bak new file mode 100644 index 000000000..47967e45e --- /dev/null +++ b/src/win32/unistd/unistd.h.bak @@ -0,0 +1,76 @@ +#ifndef _UNISTD_H +#define _UNISTD_H 1 + +/* + * This file intended to serve as a drop-in replacement for unistd.h on Windows + * Please add functionality as needed. + */ + +#include +#include + +#if defined(_MSC_VER) +#pragma warning(push) +#pragma warning(disable: 4820) +#endif + +#include + +#if defined(_MSC_VER) +#pragma warning(pop) +#endif + +#include // getopt at: https://gist.github.com/ashelly/7776712 +#include // for getpid() and the exec..() family +#include // for _getcwd() and _chdir() + +#define srandom srand +#define random rand + +/* Values for the second argument to access. These may be OR'd together. */ +#define R_OK 4 // Test for read permission +#define W_OK 2 // Test for write permission +// #define X_OK 1 // execute permission - unsupported in windows +#define F_OK 0 // Test for existence + +#define access _access +#define dup2 _dup2 +#define execve _execve +#define ftruncate _chsize +#define unlink _unlink +#define fileno _fileno +#define getcwd _getcwd +#define chdir _chdir +#define isatty _isatty +#define lseek _lseek + +/* + * Read, write, and close are NOT being defined here, + * because while there are file handle specific versions for Windows, they probably don't work for sockets. + * You need to look at your app and consider whether to call e.g. closesocket(). + */ + +#define ssize_t int +#ifndef SSIZE_MAX +//#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 2147483647 : 9223372036854775807) +#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 1073741824 : ‭4611686018427387904‬) +#endif + +#define STDIN_FILENO 0 +#define STDOUT_FILENO 1 +#define STDERR_FILENO 2 +// should be in some equivalent to +typedef __int8 int8_t; +typedef __int16 int16_t; +typedef __int32 int32_t; +typedef __int64 int64_t; +typedef unsigned __int8 uint8_t; +typedef unsigned __int16 uint16_t; +typedef unsigned __int32 uint32_t; +typedef unsigned __int64 uint64_t; + +#ifndef STLINK_HAVE_UNISTD_H +int usleep(unsigned int waitTime); +#endif + +#endif // _UNISTD_H diff --git "a/src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" "b/src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" new file mode 100644 index 000000000..d4111a8b2 --- /dev/null +++ "b/src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" @@ -0,0 +1,129 @@ +--------------------------------------------------------------------------------- +Файл info.c: + +main: +- проверяю количество параметров +- инициализирую список структур devicelist, объявленный в файле chipid.c +- вызываю функцию print_data (и передаю ей параметры программы). + +print_data: +Смотрю, какие параметры переданы программе. +Если параметр --probe - вызываю функцию stlink_probe с параметрами по умолчанию +(connect: NORMAL, freq: 0) + +stlink_probe: +Объявляю список структур для каждого подключенного ST-LINK'a +(stdevs: указатель на список указателей, указывающих на структуры). +Вызываю stlink_probe_usb с параметрами: +- адрес stdevs'а (тройной указатель), +- connect, +- freq + +Функция stlink_probe_usb заполняет stdevs и возвращает его размер. +Для каждого указателя вызываю функцию stlink_print_info. + +Потом освобождаю память, отведённую под stdevs. + +stlink_print_info: просто печатаю в терминал информацию из переданной структуры +ST-LINK'а. + +--------------------------------------------------------------------------------- +Файл usb.c: + +stlink_probe_usb: +Инициализирую libusb +Получаю список USB-устройств (libusb_get_device_list). +Для полученного списка вызываю функцию stlink_probe_usb_devs. +Передаю ей: +- указатель на список указателей на структуры libusb_device (двойной указатель) devs +- адрес указателя на список указателей на структуры ST-LINK (тройной указатель) sldevs +- connect, freq. +Потом освобождаю память, занятую структурами libusb_device. +Список указателей на структуры ST-LINK возвращаю на выход (в функцию stlink_probe). + +stlink_probe_usb_devs: +Определяю количество подключенных ST-LINK'ов: +Прохожу по списку USB-устройств. +Для каждого USB-устройства получаю дескриптор desc. +Если в дескрипторе указаны idVendor и idProduct, соответствующие ST-LINK'у - увеличиваю счётчик. +Выделяю память под нужное количество структур ST-LINK'ов. + +Ещё раз прохожу по списку USB-устройств и получаю дескриптор каждого. +Если idProduct соответствует ST-LINK'у: +- открываю ST-LINK (libusb_open), +- читаю его серийник (stlink_serial); +- закрываю (libusb_close). + +Если длина серийника правильная - открываю его функцией stlink_open_usb. +Она возвращает ссылку на структуру stlink_t. Пристёгиваю эту ссылку к списку структур. +Перехожу к следюущему USB-устройству. Потом записываю ссылку на список структур stlink_t +в указатель и возвращаю количество структур по списку. + +stlink_serial: +Получаю дескриптор нулевой строки USB-устройства, беру из него LANGID (libusb_get_string_descriptor). +Получаю дескриптор строки серийника (для него нужен LANGID) (libusb_get_string_descriptor). +Если серийник длиной 50 символов - беру его же в формате ascii. +Если серийник длиной 26 символов - для каждого символа выполняю строку: +sprintf(serial + i, "%02X", desc_serial[i + 2]) +В конце ставлю ноль. +Возвращаю длину серийника и сам серийник, записанный в память по адресу из параметра. + +stlink_open_usb: +Выделяю в куче память под структуры sl (stlink_t) и slu (stlink_libusb). +Записываю в sl ссылку на список каких-то функций и ссылку на slu, указываю статус ядра +целевого MCU: TARGET_UNKNOWN. +Инициализирую libusb с контекстом, указываю LOG_LEVEL. +Получаю список USB-устройств. +Для каждого устройства получаю дескриптор и проверяю его idVendor. +Открываю устройство и пытаюсь получить серийник. +Если не получил серийник либо получил серийник, соответствующий заданному в параметре - +- выставляю в структуре sl версию и протокол по idProduct, после чего заканчиваю просмотр +устройств USB. + +Просмотрев все устройства, открываю найденный ST-LINK и освобождаю память, занятую +списком USB-устройств. + +Читаю конфигурацию ST-LINK'а, потом устанавливаю её. Делаю заявку на интерфейс (libusb_claim_interface). +Потом выставляю поля ep_rep, ep_req, ep_trace, sg_transfer_idx и cmd_len. +Инициализирую версию ST-LINK'а (stlink_version). +Получаю режим работы ST-LINK'а. Если он в режиме dfu - выхожу из него. +Если CONNECT_UNDER_RESET: выхожу из debug mode, если в нём. Выполняю JTAG reset. +Выставляю поле freq по параметру функции, устанавливаю SWD clock (_stlink_usb_set_swdclk). +Выполняю stlink_target_connect и возвращаю структуру sl. + +_stlink_usb_version: +Заполняю структуру stlink командой fill_command (по-разному для ST-LINK v. 3 и предыдущих версий) +Выполняю функцию send_recv + + +_stlink_usb_current_mode: +Заполняю структуру stlink командой fill_command, ставлю в i-тую позицию команду STLINK_GET_CURRENT_MODE +Вызываю функцию send_recv +Возвращаю первый символ буфера, или -1 при ошибке. + +_stlink_usb_exit_debug_mode, _stlink_usb_exit_debug_mode: +Заполняю структуру stlink командой fill_command, ставлю в i-тую позицию команды: +STLINK_DFU_COMMAND +STLINK_DFU_EXIT +Вызываю функцию send_only +Возвращаю 0, или -1 при ошибке. +То же самое для debug + +fill_command: +Для ST-LINK v. 1 заполняю поле c_buf структуры stlink. Для всех остальных заполняю его нулями. + +send_recv: +Отправляю функцией libusb_bulk_transfer данные в параметре txbuf и команду в cmd. +Проверяю ответ на ошибки и если указан rxsize - принимаю данные той же функцией. +Возвращаю количество принятого после проверки на ошибки. + +--------------------------------------------------------------------------------- +Файл common.c: + +stlink_version: +Запускаю функцию version из backend (вызывается _stlink_usb_version из usb.c) +Выполняю _parse_version. + +stlink_current_mode: +возвращаю результат выполнения функции sl->backend->current_mode(sl) после проверки на ошибки. +При этом запускается функция _stlink_usb_current_mode. \ No newline at end of file diff --git a/stlinkv1_macos_driver/install.sh b/stlinkv1_macos_driver/install.sh index f9878bd46..5716281a1 100644 --- a/stlinkv1_macos_driver/install.sh +++ b/stlinkv1_macos_driver/install.sh @@ -2,6 +2,9 @@ ISMACOS=$(sw_vers -productVersion) case $ISMACOS in +10.14*) + KEXT="stlink_shield_10_14.kext" + ;; 10.15*) KEXT="stlink_shield_10_15.kext" ;; diff --git a/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist b/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist new file mode 100644 index 000000000..fd424ea93 --- /dev/null +++ b/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist @@ -0,0 +1,82 @@ + + + + + BuildMachineOSBuild + 18G7016 + CFBundleDevelopmentRegion + English + CFBundleIdentifier + com.libusb.stlink-shield + CFBundleInfoDictionaryVersion + 6.0 + CFBundlePackageType + KEXT + CFBundleSignature + ???? + CFBundleSupportedPlatforms + + MacOSX + + CFBundleVersion + 1.0.0 + DTCompiler + com.apple.compilers.llvm.clang.1_0 + DTPlatformBuild + 11C504 + DTPlatformVersion + GM + DTSDKBuild + 19B90 + DTSDKName + macosx10.15 + DTXcode + 1130 + DTXcodeBuild + 11C504 + IOKitPersonalities + + DeviceDriver + + CFBundleIdentifier + com.apple.kpi.iokit + IOClass + IOService + IOProviderClass + IOUSBDevice + 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nested + + weight + 10 + + ^.* + + ^Info\.plist$ + + omit + + weight + 20 + + ^PkgInfo$ + + omit + + weight + 20 + + ^Resources/ + + weight + 20 + + ^Resources/.*\.lproj/ + + optional + + weight + 1000 + + ^Resources/.*\.lproj/locversion.plist$ + + omit + + weight + 1100 + + ^Resources/Base\.lproj/ + + weight + 1010 + + ^[^/]+$ + + nested + + weight + 10 + + ^embedded\.provisionprofile$ + + weight + 20 + + ^version\.plist$ + + weight + 20 + + + + diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj index 373600c64..4f2b80254 100644 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj +++ b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj @@ -8,6 +8,7 @@ /* Begin PBXFileReference section */ 8CD33C31149BB80D0033D618 /* Info.plist */ = {isa = PBXFileReference; lastKnownFileType = text.plist.xml; path = Info.plist; sourceTree = ""; }; + 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = stlink_shield_10_14.kext; sourceTree = BUILT_PRODUCTS_DIR; }; 8F90850924786F39009109AD /* stlink_shield_10_15.kext */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = stlink_shield_10_15.kext; sourceTree = BUILT_PRODUCTS_DIR; }; /* End PBXFileReference section */ @@ -33,6 +34,7 @@ 19C28FB6FE9D52B211CA2CBB /* Products */ = { isa = PBXGroup; children = ( + 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */, 8F90850924786F39009109AD /* stlink_shield_10_15.kext */, ); name = Products; @@ -58,6 +60,26 @@ /* End PBXHeadersBuildPhase section */ /* Begin PBXNativeTarget section */ + 8F9084F324786F0F009109AD /* stlink_shield_10_14 */ = { + isa = PBXNativeTarget; + buildConfigurationList = 8F9084FA24786F0F009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_14" */; + buildPhases = ( + 8F9084F424786F0F009109AD /* ShellScript */, + 8F9084F524786F0F009109AD /* Headers */, + 8F9084F624786F0F009109AD /* Resources */, + 8F9084F824786F0F009109AD /* Sources */, + 8F9084F924786F0F009109AD /* ShellScript */, + ); + buildRules = ( + ); + dependencies = ( + ); + name = stlink_shield_10_14; + productInstallPath = "$(SYSTEM_LIBRARY_DIR)/Extensions"; + productName = NanosMouse; + productReference = 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */; + productType = "com.apple.product-type.kernel-extension.iokit"; + }; 8F9084FF24786F39009109AD /* stlink_shield_10_15 */ = { isa = PBXNativeTarget; buildConfigurationList = 8F90850624786F39009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_15" */; @@ -98,6 +120,7 @@ projectDirPath = ""; projectRoot = ""; targets = ( + 8F9084F324786F0F009109AD /* stlink_shield_10_14 */, 8F9084FF24786F39009109AD /* stlink_shield_10_15 */, ); }; @@ -435,6 +458,24 @@ }; name = Release; }; + 8F9084FB24786F0F009109AD /* Debug */ = { + isa = XCBuildConfiguration; + buildSettings = { + CODE_SIGN_IDENTITY = "-"; + MACOSX_DEPLOYMENT_TARGET = 10.14; + PRODUCT_NAME = "$(TARGET_NAME)"; + }; + name = Debug; + }; + 8F9084FC24786F0F009109AD /* Release */ = { + isa = XCBuildConfiguration; + buildSettings = { + CODE_SIGN_IDENTITY = "-"; + MACOSX_DEPLOYMENT_TARGET = 10.14; + PRODUCT_NAME = "$(TARGET_NAME)"; + }; + name = Release; + }; 8F90850724786F39009109AD /* Debug */ = { isa = XCBuildConfiguration; buildSettings = { @@ -465,6 +506,15 @@ defaultConfigurationIsVisible = 0; defaultConfigurationName = Release; }; + 8F9084FA24786F0F009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_14" */ = { + isa = XCConfigurationList; + buildConfigurations = ( + 8F9084FB24786F0F009109AD /* Debug */, + 8F9084FC24786F0F009109AD /* Release */, + ); + defaultConfigurationIsVisible = 0; + defaultConfigurationName = Release; + }; 8F90850624786F39009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_15" */ = { isa = XCConfigurationList; buildConfigurations = ( From 5b320357a64458d102e190e4aeff2d58a3011e60 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 29 Jan 2022 17:56:26 +0100 Subject: [PATCH 1299/1435] Minor formatting fixes & clean-up --- CMakeLists.txt | 6 +- src/calculate.h | 2 +- src/common.h | 2 +- src/common_flash.h | 2 +- src/map_file.h | 2 +- src/{option.c => option_bytes.c} | 0 ...1\201\320\260\320\275\320\270\320\265.txt" | 129 ------------------ 7 files changed, 7 insertions(+), 136 deletions(-) rename src/{option.c => option_bytes.c} (100%) delete mode 100644 "src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" diff --git a/CMakeLists.txt b/CMakeLists.txt index a3338df71..abfc0be47 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,7 +2,7 @@ # General cmake settings ### -cmake_minimum_required(VERSION 3.7.2) +cmake_minimum_required(VERSION 3.10.2) cmake_policy(SET CMP0042 NEW) set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) @@ -127,8 +127,8 @@ set(STLINK_HEADERS set(STLINK_SOURCE src/read_write.c src/common.c - src/option.c - src/common_flash.c + src/option_bytes.c + src/common_flash.c src/map_file.c src/flashloader.c src/calculate.c diff --git a/src/calculate.h b/src/calculate.h index 68c1fb988..64dfb51b2 100644 --- a/src/calculate.h +++ b/src/calculate.h @@ -1,7 +1,7 @@ /* * File: calculate.h * - * TODO: add a description + * Calculation of sector numbers and pages */ #ifndef CALCULATE_H diff --git a/src/common.h b/src/common.h index 6c22d58c0..dd6cf95b2 100644 --- a/src/common.h +++ b/src/common.h @@ -1,7 +1,7 @@ /* * File: common.h * - * TODO: add a description + * General helper functions */ #ifndef COMMON_H diff --git a/src/common_flash.h b/src/common_flash.h index 70a6f0e04..3b6b0404a 100644 --- a/src/common_flash.h +++ b/src/common_flash.h @@ -1,7 +1,7 @@ /* * File: common_flash.h * - * TODO: add a description + * Flash operations */ #ifndef COMMON_FLASH_H diff --git a/src/map_file.h b/src/map_file.h index 9cdd745e6..f50a201f0 100644 --- a/src/map_file.h +++ b/src/map_file.h @@ -1,7 +1,7 @@ /* * File: map_file.h * - * TODO: add a description + * File mapping */ #ifndef MAP_FILE_H diff --git a/src/option.c b/src/option_bytes.c similarity index 100% rename from src/option.c rename to src/option_bytes.c diff --git "a/src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" "b/src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" deleted file mode 100644 index d4111a8b2..000000000 --- "a/src/\320\236\320\277\320\270\321\201\320\260\320\275\320\270\320\265.txt" +++ /dev/null @@ -1,129 +0,0 @@ ---------------------------------------------------------------------------------- -Файл info.c: - -main: -- проверяю количество параметров -- инициализирую список структур devicelist, объявленный в файле chipid.c -- вызываю функцию print_data (и передаю ей параметры программы). - -print_data: -Смотрю, какие параметры переданы программе. -Если параметр --probe - вызываю функцию stlink_probe с параметрами по умолчанию -(connect: NORMAL, freq: 0) - -stlink_probe: -Объявляю список структур для каждого подключенного ST-LINK'a -(stdevs: указатель на список указателей, указывающих на структуры). -Вызываю stlink_probe_usb с параметрами: -- адрес stdevs'а (тройной указатель), -- connect, -- freq - -Функция stlink_probe_usb заполняет stdevs и возвращает его размер. -Для каждого указателя вызываю функцию stlink_print_info. - -Потом освобождаю память, отведённую под stdevs. - -stlink_print_info: просто печатаю в терминал информацию из переданной структуры -ST-LINK'а. - ---------------------------------------------------------------------------------- -Файл usb.c: - -stlink_probe_usb: -Инициализирую libusb -Получаю список USB-устройств (libusb_get_device_list). -Для полученного списка вызываю функцию stlink_probe_usb_devs. -Передаю ей: -- указатель на список указателей на структуры libusb_device (двойной указатель) devs -- адрес указателя на список указателей на структуры ST-LINK (тройной указатель) sldevs -- connect, freq. -Потом освобождаю память, занятую структурами libusb_device. -Список указателей на структуры ST-LINK возвращаю на выход (в функцию stlink_probe). - -stlink_probe_usb_devs: -Определяю количество подключенных ST-LINK'ов: -Прохожу по списку USB-устройств. -Для каждого USB-устройства получаю дескриптор desc. -Если в дескрипторе указаны idVendor и idProduct, соответствующие ST-LINK'у - увеличиваю счётчик. -Выделяю память под нужное количество структур ST-LINK'ов. - -Ещё раз прохожу по списку USB-устройств и получаю дескриптор каждого. -Если idProduct соответствует ST-LINK'у: -- открываю ST-LINK (libusb_open), -- читаю его серийник (stlink_serial); -- закрываю (libusb_close). - -Если длина серийника правильная - открываю его функцией stlink_open_usb. -Она возвращает ссылку на структуру stlink_t. Пристёгиваю эту ссылку к списку структур. -Перехожу к следюущему USB-устройству. Потом записываю ссылку на список структур stlink_t -в указатель и возвращаю количество структур по списку. - -stlink_serial: -Получаю дескриптор нулевой строки USB-устройства, беру из него LANGID (libusb_get_string_descriptor). -Получаю дескриптор строки серийника (для него нужен LANGID) (libusb_get_string_descriptor). -Если серийник длиной 50 символов - беру его же в формате ascii. -Если серийник длиной 26 символов - для каждого символа выполняю строку: -sprintf(serial + i, "%02X", desc_serial[i + 2]) -В конце ставлю ноль. -Возвращаю длину серийника и сам серийник, записанный в память по адресу из параметра. - -stlink_open_usb: -Выделяю в куче память под структуры sl (stlink_t) и slu (stlink_libusb). -Записываю в sl ссылку на список каких-то функций и ссылку на slu, указываю статус ядра -целевого MCU: TARGET_UNKNOWN. -Инициализирую libusb с контекстом, указываю LOG_LEVEL. -Получаю список USB-устройств. -Для каждого устройства получаю дескриптор и проверяю его idVendor. -Открываю устройство и пытаюсь получить серийник. -Если не получил серийник либо получил серийник, соответствующий заданному в параметре - -- выставляю в структуре sl версию и протокол по idProduct, после чего заканчиваю просмотр -устройств USB. - -Просмотрев все устройства, открываю найденный ST-LINK и освобождаю память, занятую -списком USB-устройств. - -Читаю конфигурацию ST-LINK'а, потом устанавливаю её. Делаю заявку на интерфейс (libusb_claim_interface). -Потом выставляю поля ep_rep, ep_req, ep_trace, sg_transfer_idx и cmd_len. -Инициализирую версию ST-LINK'а (stlink_version). -Получаю режим работы ST-LINK'а. Если он в режиме dfu - выхожу из него. -Если CONNECT_UNDER_RESET: выхожу из debug mode, если в нём. Выполняю JTAG reset. -Выставляю поле freq по параметру функции, устанавливаю SWD clock (_stlink_usb_set_swdclk). -Выполняю stlink_target_connect и возвращаю структуру sl. - -_stlink_usb_version: -Заполняю структуру stlink командой fill_command (по-разному для ST-LINK v. 3 и предыдущих версий) -Выполняю функцию send_recv - - -_stlink_usb_current_mode: -Заполняю структуру stlink командой fill_command, ставлю в i-тую позицию команду STLINK_GET_CURRENT_MODE -Вызываю функцию send_recv -Возвращаю первый символ буфера, или -1 при ошибке. - -_stlink_usb_exit_debug_mode, _stlink_usb_exit_debug_mode: -Заполняю структуру stlink командой fill_command, ставлю в i-тую позицию команды: -STLINK_DFU_COMMAND -STLINK_DFU_EXIT -Вызываю функцию send_only -Возвращаю 0, или -1 при ошибке. -То же самое для debug - -fill_command: -Для ST-LINK v. 1 заполняю поле c_buf структуры stlink. Для всех остальных заполняю его нулями. - -send_recv: -Отправляю функцией libusb_bulk_transfer данные в параметре txbuf и команду в cmd. -Проверяю ответ на ошибки и если указан rxsize - принимаю данные той же функцией. -Возвращаю количество принятого после проверки на ошибки. - ---------------------------------------------------------------------------------- -Файл common.c: - -stlink_version: -Запускаю функцию version из backend (вызывается _stlink_usb_version из usb.c) -Выполняю _parse_version. - -stlink_current_mode: -возвращаю результат выполнения функции sl->backend->current_mode(sl) после проверки на ошибки. -При этом запускается функция _stlink_usb_current_mode. \ No newline at end of file From d98d3a50edbbf984b1fe842908e1420d26c3ff0f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 29 Jan 2022 17:56:26 +0100 Subject: [PATCH 1300/1435] Minor formatting fixes & clean-up --- CMakeLists.txt | 6 +++--- src/calculate.h | 2 +- src/common.h | 2 +- src/common_flash.h | 2 +- src/map_file.h | 2 +- src/{option.c => option_bytes.c} | 0 6 files changed, 7 insertions(+), 7 deletions(-) rename src/{option.c => option_bytes.c} (100%) diff --git a/CMakeLists.txt b/CMakeLists.txt index a3338df71..abfc0be47 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -2,7 +2,7 @@ # General cmake settings ### -cmake_minimum_required(VERSION 3.7.2) +cmake_minimum_required(VERSION 3.10.2) cmake_policy(SET CMP0042 NEW) set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/cmake/modules) set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) @@ -127,8 +127,8 @@ set(STLINK_HEADERS set(STLINK_SOURCE src/read_write.c src/common.c - src/option.c - src/common_flash.c + src/option_bytes.c + src/common_flash.c src/map_file.c src/flashloader.c src/calculate.c diff --git a/src/calculate.h b/src/calculate.h index 68c1fb988..64dfb51b2 100644 --- a/src/calculate.h +++ b/src/calculate.h @@ -1,7 +1,7 @@ /* * File: calculate.h * - * TODO: add a description + * Calculation of sector numbers and pages */ #ifndef CALCULATE_H diff --git a/src/common.h b/src/common.h index 6c22d58c0..dd6cf95b2 100644 --- a/src/common.h +++ b/src/common.h @@ -1,7 +1,7 @@ /* * File: common.h * - * TODO: add a description + * General helper functions */ #ifndef COMMON_H diff --git a/src/common_flash.h b/src/common_flash.h index 70a6f0e04..3b6b0404a 100644 --- a/src/common_flash.h +++ b/src/common_flash.h @@ -1,7 +1,7 @@ /* * File: common_flash.h * - * TODO: add a description + * Flash operations */ #ifndef COMMON_FLASH_H diff --git a/src/map_file.h b/src/map_file.h index b35f24ad0..08cf98b6c 100644 --- a/src/map_file.h +++ b/src/map_file.h @@ -1,7 +1,7 @@ /* * File: map_file.h * - * TODO: add a description + * File mapping */ #ifndef MAP_FILE_H diff --git a/src/option.c b/src/option_bytes.c similarity index 100% rename from src/option.c rename to src/option_bytes.c From e2dcf074d51aaf2ec2a77617475a8a5e8ffebd6f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 29 Jan 2022 19:33:19 +0100 Subject: [PATCH 1301/1435] Fixed defines (CHIPID + COREID) & duplicates --- inc/stm32.h | 374 --------------------------------------------- inc/stm32flash.h | 4 +- src/calculate.c | 6 +- src/common.c | 46 +++--- src/common_flash.c | 368 ++++++++++++++++++++++---------------------- src/flashloader.c | 104 ++++++------- src/option_bytes.c | 54 +++---- 7 files changed, 291 insertions(+), 665 deletions(-) diff --git a/inc/stm32.h b/inc/stm32.h index 08cd3cd2a..d764e2f97 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -155,340 +155,6 @@ enum stm32_chipids { #define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) #define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) -/* stm32f FPEC flash controller interface, pm0063 manual */ -// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) -#define FLASH_REGS_ADDR 0x40022000 -#define FLASH_REGS_SIZE 0x28 - -#define FLASH_ACR (FLASH_REGS_ADDR + 0x00) -#define FLASH_KEYR (FLASH_REGS_ADDR + 0x04) -#define FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x08) -#define FLASH_SR (FLASH_REGS_ADDR + 0x0c) -#define FLASH_CR (FLASH_REGS_ADDR + 0x10) -#define FLASH_AR (FLASH_REGS_ADDR + 0x14) -#define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) -#define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) - -// STM32F10x_XL has two flash memory banks with separate registers to control -// the second bank. -#define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) -#define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) -#define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) -#define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) - -// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... -#define FLASH_RDPTR_KEY 0x00a5 -#define FLASH_KEY1 0x45670123 -#define FLASH_KEY2 0xcdef89ab - -#define FLASH_L0_PRGKEY1 0x8c9daebf -#define FLASH_L0_PRGKEY2 0x13141516 - -#define FLASH_L0_PEKEY1 0x89abcdef -#define FLASH_L0_PEKEY2 0x02030405 - -#define FLASH_OPTKEY1 0x08192A3B -#define FLASH_OPTKEY2 0x4C5D6E7F - -#define FLASH_F0_OPTKEY1 0x45670123 -#define FLASH_F0_OPTKEY2 0xCDEF89AB - -#define FLASH_L0_OPTKEY1 0xFBEAD9C8 -#define FLASH_L0_OPTKEY2 0x24252627 - -#define FLASH_SR_BSY 0 -#define FLASH_SR_PG_ERR 2 -#define FLASH_SR_WRPRT_ERR 4 -#define FLASH_SR_EOP 5 - -#define FLASH_SR_ERROR_MASK ((1 << FLASH_SR_PG_ERR) | (1 << FLASH_SR_WRPRT_ERR)) - -#define FLASH_CR_PG 0 -#define FLASH_CR_PER 1 -#define FLASH_CR_MER 2 -#define FLASH_CR_OPTPG 4 -#define FLASH_CR_OPTER 5 -#define FLASH_CR_STRT 6 -#define FLASH_CR_LOCK 7 -#define FLASH_CR_OPTWRE 9 -#define FLASH_CR_OBL_LAUNCH 13 - -#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) -#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) -#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) -#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) -#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) -#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) -#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) -#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) -#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) -#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) -#define FLASH_L1_FPRG 10 -#define FLASH_L1_PROG 3 - -// Flash registers common to STM32G0 and STM32G4 series. -#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) -#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) -#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) -#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) -#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) -#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) -#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) - -// G0 (RM0444 Table 1, sec 3.7) -// Mostly the same as G4 chips, but the notation -// varies a bit after the 'OPTR' register. -#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) -#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) -#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) -#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) -#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) -#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) -#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) - -// G4 (RM0440 Table 17, sec 3.7.19) -// Mostly the same as STM32G0 chips, but there are a few extra -// registers because 'cat 3' devices can have two Flash banks. -#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) -#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) -#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) -#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) -#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) -#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) -#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) -#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) -#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) -#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) -#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) - -// G0/G4 FLASH control register -#define STM32Gx_FLASH_CR_PG (0) /* Program */ -#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ -#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ -#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ -#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define STM32Gx_FLASH_CR_STRT (16) /* Start */ -#define STM32Gx_FLASH_CR_OPTSTRT \ - (17) /* Start of modification of option bytes */ -#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ -#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ -#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ -#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ -#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ - -// G0/G4 FLASH status register -#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) -#define STM32Gx_FLASH_SR_PROGERR (3) -#define STM32Gx_FLASH_SR_WRPERR (4) -#define STM32Gx_FLASH_SR_PGAERR (5) -#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ - -// G4 FLASH option register -#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ - -// WB (RM0434) -#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) -#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) -#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) -#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) -#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) -#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) -#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) -#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) -#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) -#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) -#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) - -// WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ -// WB Flash status register. -#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ -#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ -#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ -#define STM32WB_FLASH_SR_BSY (16) /* Busy */ - -// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) -#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) -#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) -#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) -#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) -#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) - -#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ -#define STM32L4_FLASH_SR_PROGERR 3 -#define STM32L4_FLASH_SR_WRPERR 4 -#define STM32L4_FLASH_SR_PGAERR 5 -#define STM32L4_FLASH_SR_BSY 16 - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ -#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ -// Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ - (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) -// Page is fully specified by BKER and PNB -#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) - -#define STM32L4_FLASH_OPTR_DUALBANK 21 - -// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf -#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) - -#define STM32L0_FLASH_PELOCK (0) -#define STM32L0_FLASH_OPTLOCK (2) -#define STM32L0_FLASH_OBL_LAUNCH (18) - -#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 -#define STM32L0_FLASH_SR_WRPERR 8 -#define STM32L0_FLASH_SR_PGAERR 9 -#define STM32L0_FLASH_SR_NOTZEROERR 16 - -#define FLASH_ACR_OFF ((uint32_t)0x00) -#define FLASH_PECR_OFF ((uint32_t)0x04) -#define FLASH_PDKEYR_OFF ((uint32_t)0x08) -#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) -#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) -#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) -#define FLASH_SR_OFF ((uint32_t)0x18) -#define FLASH_OBR_OFF ((uint32_t)0x1c) -#define FLASH_WRPR_OFF ((uint32_t)0x20) - -// STM32F7 -#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) -#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) -#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) -#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) -#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) -#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) -#define FLASH_F7_OPTCR_LOCK 0 -#define FLASH_F7_OPTCR_START 1 -#define FLASH_F7_CR_STRT 16 -#define FLASH_F7_CR_LOCK 31 -#define FLASH_F7_CR_SER 1 -#define FLASH_F7_CR_SNB 3 -#define FLASH_F7_CR_SNB_MASK 0xf8 -#define FLASH_F7_SR_BSY 16 -#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ -#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ -#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ -#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ -#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ -#define FLASH_F7_SR_EOP 0 /* End of operation */ -#define FLASH_F7_OPTCR1_BOOT_ADD0 0 -#define FLASH_F7_OPTCR1_BOOT_ADD1 16 - -#define FLASH_F7_SR_ERROR_MASK \ - ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ - (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ - (1 << FLASH_F7_SR_OP_ERR)) - -// STM32F4 -#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) -#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) -#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) -#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) -#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) -#define FLASH_F4_OPTCR_LOCK 0 -#define FLASH_F4_OPTCR_START 1 -#define FLASH_F4_CR_STRT 16 -#define FLASH_F4_CR_LOCK 31 -#define FLASH_F4_CR_SER 1 -#define FLASH_F4_CR_SNB 3 -#define FLASH_F4_CR_SNB_MASK 0xf8 -#define FLASH_F4_SR_ERROR_MASK 0x000000F0 -#define FLASH_F4_SR_PGAERR 5 -#define FLASH_F4_SR_WRPERR 4 -#define FLASH_F4_SR_BSY 16 - -// STM32F2 -#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) -#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) -#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) -#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) -#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) -#define FLASH_F2_OPT_LOCK_BIT (1u << 0) -#define FLASH_F2_CR_STRT 16 -#define FLASH_F2_CR_LOCK 31 - -#define FLASH_F2_CR_SER 1 -#define FLASH_F2_CR_SNB 3 -#define FLASH_F2_CR_SNB_MASK 0x78 -#define FLASH_F2_SR_BSY 16 - -// STM32H7xx -#define FLASH_H7_CR_LOCK 0 -#define FLASH_H7_CR_PG 1 -#define FLASH_H7_CR_SER 2 -#define FLASH_H7_CR_BER 3 -#define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7) -#define FLASH_H7_CR_SNB 8 -#define FLASH_H7_CR_SNB_MASK 0x700 - -#define FLASH_H7_SR_QW 2 -#define FLASH_H7_SR_WRPERR 17 -#define FLASH_H7_SR_PGSERR 18 -#define FLASH_H7_SR_STRBERR 19 -#define FLASH_H7_SR_ERROR_MASK \ - ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ - (1 << FLASH_H7_SR_WRPERR)) - -#define FLASH_H7_OPTCR_OPTLOCK 0 -#define FLASH_H7_OPTCR_OPTSTART 1 -#define FLASH_H7_OPTCR_MER 4 - -#define FLASH_H7_OPTSR_OPT_BUSY 0 -#define FLASH_H7_OPTSR_OPTCHANGEERR 30 - -#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 - -#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) -#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) -#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) -#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) -#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) -#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) -#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) -#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) -#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) -#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) -#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) -#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) -#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) -#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) -#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) - #define STM32F0_DBGMCU_CR 0xE0042004 #define STM32F0_DBGMCU_CR_IWDG_STOP 8 #define STM32F0_DBGMCU_CR_WWDG_STOP 9 @@ -532,44 +198,4 @@ enum stm32_chipids { #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 -#define STM32F0_DBGMCU_CR 0xE0042004 -#define STM32F0_DBGMCU_CR_IWDG_STOP 8 -#define STM32F0_DBGMCU_CR_WWDG_STOP 9 - -#define STM32F4_DBGMCU_APB1FZR1 0xE0042008 -#define STM32F4_DBGMCU_APB1FZR1_WWDG_STOP 11 -#define STM32F4_DBGMCU_APB1FZR1_IWDG_STOP 12 - -#define STM32L0_DBGMCU_APB1_FZ 0x40015808 -#define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 -#define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 - -#define STM32H7_DBGMCU_APB1HFZ 0x5C001054 -#define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 - -#define STM32WB_DBGMCU_APB1FZR1 0xE004203C -#define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 -#define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 - -#define STM32F1_RCC_AHBENR 0x40021014 -#define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32F4_RCC_AHB1ENR 0x40023830 -#define STM32F4_RCC_DMAEN 0x00600000 // DMA2EN | DMA1EN - -#define STM32G0_RCC_AHBENR 0x40021038 -#define STM32G0_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32G4_RCC_AHB1ENR 0x40021048 -#define STM32G4_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32L0_RCC_AHBENR 0x40021030 -#define STM32L0_RCC_DMAEN 0x00000001 // DMAEN - -#define STM32H7_RCC_AHB1ENR 0x58024538 -#define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -#define STM32WB_RCC_AHB1ENR 0x58000048 -#define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - #endif // STM32_H diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 01c76946c..73d1bbc21 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -300,7 +300,7 @@ #define FLASH_H7_CR_SER 2 #define FLASH_H7_CR_BER 3 #define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STLINK_CHIPID_STM32_H7Ax ? 5 : 7) +#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7) #define FLASH_H7_CR_SNB 8 #define FLASH_H7_CR_SNB_MASK 0x700 @@ -337,4 +337,4 @@ #define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) #define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) -#endif // STM32FLASH_H \ No newline at end of file +#endif // STM32FLASH_H diff --git a/src/calculate.c b/src/calculate.c index 22f6e3a5b..ed3b65873 100644 --- a/src/calculate.c +++ b/src/calculate.c @@ -54,9 +54,9 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); flashaddr -= STM32_FLASH_BASE; - if (sl->chip_id == STLINK_CHIPID_STM32_L4 || - sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x || - sl->chip_id == STLINK_CHIPID_STM32_L4Rx) { + if (sl->chip_id == STM32_CHIPID_L4 || + sl->chip_id == STM32_CHIPID_L496x_L4A6x || + sl->chip_id == STM32_CHIPID_L4Rx) { // this chip use dual banked flash if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { uint32_t banksize = (uint32_t)sl->flash_size / 2; diff --git a/src/common.c b/src/common.c index 7b4f1e14b..4e5052522 100644 --- a/src/common.c +++ b/src/common.c @@ -134,7 +134,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * */ - if ((sl->core_id == STM32H7_CORE_ID || sl->core_id == STM32H7_CORE_ID_JTAG) && + if ((sl->core_id == STM32_CORE_ID_M7F_H7_SWD || sl->core_id == STM32_CORE_ID_M7F_H7_JTAG) && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); @@ -242,14 +242,14 @@ int stlink_load_device_params(stlink_t *sl) { flash_size = flash_size & 0xffff; - if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MD || - sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD || - sl->chip_id == STLINK_CHIPID_STM32_L1_MD_PLUS) && + if ((sl->chip_id == STM32_CHIPID_L1_MD || + sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_L1_MD_PLUS) && (flash_size == 0)) { sl->flash_size = 128 * 1024; - } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { + } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { sl->flash_size = (flash_size & 0xff) * 1024; - } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_MD_PLUS_HD) { + } else if ((sl->chip_id & 0xFFF) == STM32_CHIPID_L1_MD_PLUS_HD) { // 0 is 384k and 1 is 256k if (flash_size == 0) { sl->flash_size = 384 * 1024; @@ -271,12 +271,12 @@ int stlink_load_device_params(stlink_t *sl) { // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MD_LD && + if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { sl->sram_size = 0x1000; } - if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { + if (sl->chip_id == STM32_CHIPID_G4_CAT3) { uint32_t flash_optr; stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); @@ -293,7 +293,7 @@ int stlink_load_device_params(stlink_t *sl) { } ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", - params->description, (unsigned)(sl->sram_size / 1024), + params->dev_type, (unsigned)(sl->sram_size / 1024), (unsigned)(sl->flash_size / 1024), (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) : (unsigned)(sl->flash_pgsz / 1024), @@ -712,16 +712,16 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, } // 291 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { - if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || - (sl->chip_id == STLINK_CHIPID_STM32_F4) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || - (sl->chip_id == STLINK_CHIPID_STM32_F411xx) || - (sl->chip_id == STLINK_CHIPID_STM32_F446) || - (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || - (sl->chip_id == STLINK_CHIPID_STM32_F72xxx) || - (sl->chip_id == STLINK_CHIPID_STM32_F412)) { + if ((sl->chip_id == STM32_CHIPID_F2) || + (sl->chip_id == STM32_CHIPID_F4) || + (sl->chip_id == STM32_CHIPID_F4_DE) || + (sl->chip_id == STM32_CHIPID_F4_LP) || + (sl->chip_id == STM32_CHIPID_F4_HD) || + (sl->chip_id == STM32_CHIPID_F411xx) || + (sl->chip_id == STM32_CHIPID_F446) || + (sl->chip_id == STM32_CHIPID_F4_DSI) || + (sl->chip_id == STM32_CHIPID_F72xxx) || + (sl->chip_id == STM32_CHIPID_F412)) { uint32_t sector = calculate_F4_sectornum(flashaddr); if (sector >= 12) { @@ -735,8 +735,8 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { } else { sl->flash_pgsz = 0x20000; } - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { + } else if (sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx) { uint32_t sector = calculate_F7_sectornum(flashaddr); if (sector < 4) { @@ -984,7 +984,7 @@ static void stop_wdg_in_debug(stlink_t *sl) { break; case STM32_FLASH_TYPE_F2_F4: case STM32_FLASH_TYPE_F7: - case STM32_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); @@ -999,7 +999,7 @@ static void stop_wdg_in_debug(stlink_t *sl) { dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; set = (1 << STM32H7_DBGMCU_APB1HFZ_IWDG_STOP); break; - case STM32_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: dbgmcu_cr = STM32WB_DBGMCU_APB1FZR1; set = (1 << STM32WB_DBGMCU_APB1FZR1_IWDG_STOP) | (1 << STM32WB_DBGMCU_APB1FZR1_WWDG_STOP); diff --git a/src/common_flash.c b/src/common_flash.c index 1f438c74f..e2a9ebbc3 100644 --- a/src/common_flash.c +++ b/src/common_flash.c @@ -11,16 +11,16 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { switch (sl->chip_id) { - case STLINK_CHIPID_STM32_L0: - case STLINK_CHIPID_STM32_L0_CAT5: - case STLINK_CHIPID_STM32_L0_CAT2: - case STLINK_CHIPID_STM32_L011: + case STM32_CHIPID_L0: + case STM32_CHIPID_L0_CAT5: + case STM32_CHIPID_L0_CAT2: + case STM32_CHIPID_L011: return (STM32L0_FLASH_REGS_ADDR); - case STLINK_CHIPID_STM32_L1_CAT2: - case STLINK_CHIPID_STM32_L1_MD: - case STLINK_CHIPID_STM32_L1_MD_PLUS: - case STLINK_CHIPID_STM32_L1_MD_PLUS_HD: + case STM32_CHIPID_L1_CAT2: + case STM32_CHIPID_L1_MD: + case STM32_CHIPID_L1_MD_PLUS: + case STM32_CHIPID_L1_MD_PLUS_HD: return (STM32L_FLASH_REGS_ADDR); default: @@ -32,18 +32,18 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { uint32_t reg, res; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; } else { reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; @@ -61,33 +61,33 @@ void lock_flash(stlink_t *sl) { uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; uint32_t cr_mask = 0xffffffffu; - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { cr_reg = FLASH_CR; cr2_reg = FLASH_CR2; cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr2_reg = FLASH_H7_CR2; @@ -113,23 +113,23 @@ void lock_flash(stlink_t *sl) { static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { uint32_t sr_reg; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; } else { ELOG("method 'write_flash_sr' is unsupported\n"); @@ -141,32 +141,32 @@ static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { void clear_flash_error(stlink_t *sl) { switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: + case STM32_FLASH_TYPE_F0_F1_F3: write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); } break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); break; default: @@ -177,23 +177,23 @@ void clear_flash_error(stlink_t *sl) { uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { uint32_t res, sr_reg; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { sr_reg = STM32L4_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_reg = STM32WB_FLASH_SR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; } else { ELOG("method 'read_flash_sr' is unsupported\n"); @@ -208,22 +208,22 @@ unsigned int is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; unsigned int res; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_L0)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { sr_busy_shift = FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_busy_shift = FLASH_F4_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { sr_busy_shift = STM32L4_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { sr_busy_shift = STM32Gx_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_busy_shift = STM32WB_FLASH_SR_BSY; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; } else { ELOG("method 'is_flash_busy' is unsupported\n"); @@ -232,8 +232,8 @@ unsigned int is_flash_busy(stlink_t *sl) { res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); } @@ -254,52 +254,52 @@ int check_flash_error(stlink_t *sl) { WRPERR = PROGERR = PGAERR = 0; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; } WRPERR = (1 << FLASH_SR_WRPRT_ERR); PROGERR = (1 << FLASH_SR_PG_ERR); break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; WRPERR = (1 << FLASH_F4_SR_WRPERR); PGAERR = (1 << FLASH_F4_SR_PGAERR); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; WRPERR = (1 << FLASH_F7_SR_WRP_ERR); PROGERR = (1 << FLASH_F7_SR_PGP_ERR); break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; } WRPERR = (1 << FLASH_H7_SR_WRPERR); break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); @@ -336,30 +336,30 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { uint32_t cr_reg; uint32_t n; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_lock_shift = FLASH_F4_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_lock_shift = STM32Gx_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; cr_lock_shift = FLASH_H7_CR_LOCK; } else { @@ -380,27 +380,27 @@ static void unlock_flash(stlink_t *sl) { * definitive lock of the FPEC block until next reset. */ - if (sl->flash_type == STLINK_FLASH_TYPE_F0) { + if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { key_reg = FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { key_reg = FLASH_KEYR; key2_reg = FLASH_KEYR2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { key_reg = FLASH_F4_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { key_reg = FLASH_F7_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; flash_key1 = FLASH_L0_PEKEY1; flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { key_reg = STM32L4_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { key_reg = STM32Gx_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { key_reg = STM32WB_FLASH_KEYR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { key_reg = FLASH_H7_KEYR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { key2_reg = FLASH_H7_KEYR2; @@ -439,38 +439,38 @@ int lock_flash_option(stlink_t *sl) { int active_bit_level = 1; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; optlock_shift = FLASH_CR_OPTWRE; active_bit_level = 0; break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: optcr_reg = FLASH_F4_OPTCR; optlock_shift = FLASH_F4_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: optcr_reg = STM32Gx_FLASH_CR; optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; optlock_shift = FLASH_H7_OPTCR_OPTLOCK; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) @@ -512,38 +512,38 @@ static bool is_flash_option_locked(stlink_t *sl) { uint32_t n; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; optlock_shift = FLASH_CR_OPTWRE; active_bit_level = 0; /* bit is "option write enable", not lock */ break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: optcr_reg = FLASH_F4_OPTCR; optlock_shift = FLASH_F4_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: optcr_reg = STM32Gx_FLASH_CR; optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; optlock_shift = FLASH_H7_OPTCR_OPTLOCK; break; @@ -567,34 +567,34 @@ static int unlock_flash_option(stlink_t *sl) { uint32_t optkey2 = FLASH_OPTKEY2; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: optkey_reg = FLASH_OPTKEYR; optkey1 = FLASH_F0_OPTKEY1; optkey2 = FLASH_F0_OPTKEY2; break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: optkey_reg = FLASH_F4_OPT_KEYR; break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: optkey_reg = FLASH_F7_OPT_KEYR; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; optkey1 = FLASH_L0_OPTKEY1; optkey2 = FLASH_L0_OPTKEY2; break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: optkey_reg = STM32L4_FLASH_OPTKEYR; break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: optkey_reg = STM32Gx_FLASH_OPTKEYR; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: optkey_reg = STM32WB_FLASH_OPT_KEYR; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: optkey_reg = FLASH_H7_OPT_KEYR; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) optkey2_reg = FLASH_H7_OPT_KEYR2; @@ -637,7 +637,7 @@ void write_flash_cr_psiz(stlink_t *sl, uint32_t n, uint32_t cr_reg, psize_shift; uint32_t x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; psize_shift = FLASH_H7_CR_PSIZE; } else { @@ -657,18 +657,18 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { uint32_t cr_reg, n; uint32_t bit = FLASH_CR_PG; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; bit = FLASH_H7_CR_PG; } else { @@ -706,7 +706,7 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { uint32_t cr_reg, snb_mask, snb_shift, ser_shift; uint32_t x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; snb_mask = FLASH_H7_CR_SNB_MASK; snb_shift = FLASH_H7_CR_SNB; @@ -730,10 +730,10 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { static void set_flash_cr_per(stlink_t *sl, unsigned bank) { uint32_t cr_reg, val; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; @@ -747,10 +747,10 @@ static void set_flash_cr_per(stlink_t *sl, unsigned bank) { static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { uint32_t cr_reg; - if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; @@ -779,23 +779,23 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { uint32_t val, cr_reg, cr_strt; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_strt = (1 << STM32L4_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_strt = (1 << STM32Gx_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_strt = (1 << STM32WB_FLASH_CR_STRT); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); } else { @@ -811,20 +811,20 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { uint32_t val, cr_reg, cr_mer, cr_pg; - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); cr_pg = (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); @@ -833,11 +833,11 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { } cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_mer = (1 << FLASH_H7_CR_BER); cr_pg = (1 << FLASH_H7_CR_PG); @@ -877,18 +877,18 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // clear flash IO errors clear_flash_error(sl); - if (sl->flash_type == STLINK_FLASH_TYPE_F4 || - sl->flash_type == STLINK_FLASH_TYPE_F7 || - sl->flash_type == STLINK_FLASH_TYPE_L4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4 || + sl->flash_type == STM32_FLASH_TYPE_F7 || + sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { // unlock if locked unlock_flash_if(sl); // select the page to erase - if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || - (sl->chip_id == STLINK_CHIPID_STM32_L43x_L44x) || - (sl->chip_id == STLINK_CHIPID_STM32_L45x_L46x) || - (sl->chip_id == STLINK_CHIPID_STM32_L496x_L4A6x) || - (sl->chip_id == STLINK_CHIPID_STM32_L4Rx)) { + if ((sl->chip_id == STM32_CHIPID_L4) || + (sl->chip_id == STM32_CHIPID_L43x_L44x) || + (sl->chip_id == STM32_CHIPID_L45x_L46x) || + (sl->chip_id == STM32_CHIPID_L496x_L4A6x) || + (sl->chip_id == STM32_CHIPID_L4Rx)) { // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); @@ -896,8 +896,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_calculate_pagesize(sl, flashaddr)); write_flash_cr_bker_pnb(sl, page); - } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || - sl->chip_id == STLINK_CHIPID_STM32_F76xxx) { + } else if (sl->chip_id == STM32_CHIPID_F7 || + sl->chip_id == STM32_CHIPID_F76xxx) { // calculate the actual page from the address uint32_t sector = calculate_F7_sectornum(flashaddr); @@ -926,7 +926,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { #if DEBUG_FLASH fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); #endif - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); @@ -982,15 +982,15 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { uint32_t val; unlock_flash_if(sl); set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit // set the page to erase - if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); @@ -1000,7 +1000,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val |= ((flash_page & 0xFF) << 3); stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -1008,7 +1008,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val &= ~(0x3F << 3); val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G4) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -1022,8 +1022,8 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { wait_flash_busy(sl); // wait for the 'busy' bit to clear clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); clear_flash_cr_pg(sl, bank); // clear the pg bit @@ -1034,7 +1034,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { wait_flash_busy(sl); clear_flash_cr_per(sl, bank); // clear the page erase bit lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); // unlock if locked uint32_t sector = calculate_H7_sectornum( @@ -1093,8 +1093,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { int err = 0; // TODO: User MER bit to mass-erase WB series. - if (sl->flash_type == STLINK_FLASH_TYPE_L0 || - sl->flash_type == STLINK_FLASH_TYPE_WB) { + if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || + sl->flash_type == STM32_FLASH_TYPE_WB_WL) { err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); @@ -1103,8 +1103,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { clear_flash_error(sl); unlock_flash_if(sl); - if (sl->flash_type == STLINK_FLASH_TYPE_H7 && - sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { + if (sl->flash_type == STM32_FLASH_TYPE_H7 && + sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -1116,8 +1116,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { set_flash_cr_strt( sl, BANK_1); // start erase operation, reset by hw with busy bit - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 @@ -1128,8 +1128,8 @@ int stlink_erase_flash_mass(stlink_t *sl) { // reset the mass erase bit set_flash_cr_mer(sl, 0, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || - (sl->flash_type == STLINK_FLASH_TYPE_H7 && + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 0, BANK_2); } diff --git a/src/flashloader.c b/src/flashloader.c index f84e16ef0..e4c7d7200 100644 --- a/src/flashloader.c +++ b/src/flashloader.c @@ -73,24 +73,24 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { x = read_flash_cr(sl, bank); - if (sl->flash_type == STLINK_FLASH_TYPE_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; x |= (1 << FLASH_H7_CR_PG); } else { @@ -107,34 +107,34 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { rcc = rcc_dma_mask = value = 0; switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: rcc = STM32F1_RCC_AHBENR; rcc_dma_mask = STM32F1_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_F4: - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F2_F4: + case STM32_FLASH_TYPE_F7: rcc = STM32F4_RCC_AHB1ENR; rcc_dma_mask = STM32F4_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G0: rcc = STM32G0_RCC_AHBENR; rcc_dma_mask = STM32G0_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_G4: - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_L4_L4P: rcc = STM32G4_RCC_AHB1ENR; rcc_dma_mask = STM32G4_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: rcc = STM32L0_RCC_AHBENR; rcc_dma_mask = STM32L0_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: rcc = STM32H7_RCC_AHB1ENR; rcc_dma_mask = STM32H7_RCC_DMAEN; break; - case STLINK_FLASH_TYPE_WB: + case STM32_FLASH_TYPE_WB_WL: rcc = STM32WB_RCC_AHB1ENR; rcc_dma_mask = STM32WB_RCC_DMAEN; break; @@ -162,9 +162,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // Clear errors clear_flash_error(sl); - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { ILOG("Starting Flash write for F2/F4/F7/L4\n"); // Flash loader initialisation @@ -188,7 +188,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { return (-1); } - if (sl->flash_type == STLINK_FLASH_TYPE_L4) { + if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { // L4 does not have a byte-write mode if (voltage < 1710) { ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); @@ -208,14 +208,14 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // set programming mode set_flash_cr_pg(sl, BANK_1); - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { ILOG("Starting Flash write for WB/G0/G4\n"); unlock_flash_if(sl); // unlock flash if necessary set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { ILOG("Starting Flash write for L0\n"); uint32_t val; @@ -252,8 +252,8 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // L0/L1 have fallback to soft write WLOG("stlink_flash_loader_init() == -1\n"); } - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); // flash loader initialisation @@ -267,10 +267,10 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // set programming mode set_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { set_flash_cr_pg(sl, BANK_2); } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { ILOG("Starting Flash write for H7\n"); unlock_flash_if(sl); // unlock the cr @@ -278,7 +278,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { set_flash_cr_pg(sl, BANK_2); } - if (sl->chip_id != STLINK_CHIPID_STM32_H7Ax) { + if (sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -296,9 +296,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { size_t off; - if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; for (off = 0; off < len;) { size_t size = len - off > buf_size ? buf_size : len - off; @@ -312,9 +312,9 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, off += size; } - } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || - sl->flash_type == STLINK_FLASH_TYPE_G0 || - sl->flash_type == STLINK_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; @@ -338,7 +338,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, 0); // write a single word of zeros wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? @@ -378,8 +378,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, // TODO: check redo write operation } fprintf(stdout, "\n"); - } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { int write_block_count = 0; for (off = 0; off < len; off += sl->flash_pgsz) { // adjust last write size @@ -411,7 +411,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if (sl->verbose >= 1) { fprintf(stdout, "\n"); } - } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { for (off = 0; off < len;) { // Program STM32H7x with 64-byte Flash words size_t chunk = (len - off > 64) ? 64 : len - off; @@ -441,24 +441,24 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { uint32_t dhcsr; - if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || - (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || - (sl->flash_type == STLINK_FLASH_TYPE_F4) || - (sl->flash_type == STLINK_FLASH_TYPE_F7) || - (sl->flash_type == STLINK_FLASH_TYPE_L4) || - (sl->flash_type == STLINK_FLASH_TYPE_WB) || - (sl->flash_type == STLINK_FLASH_TYPE_G0) || - (sl->flash_type == STLINK_FLASH_TYPE_G4) || - (sl->flash_type == STLINK_FLASH_TYPE_H7)) { + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) || + (sl->flash_type == STM32_FLASH_TYPE_WB_WL) || + (sl->flash_type == STM32_FLASH_TYPE_G0) || + (sl->flash_type == STM32_FLASH_TYPE_G4) || + (sl->flash_type == STM32_FLASH_TYPE_H7)) { clear_flash_cr_pg(sl, BANK_1); - if ((sl->flash_type == STLINK_FLASH_TYPE_H7 && + if ((sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || - sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { clear_flash_cr_pg(sl, BANK_2); } lock_flash(sl); - } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); diff --git a/src/option_bytes.c b/src/option_bytes.c index ed9ee4f39..f5d8c00a0 100644 --- a/src/option_bytes.c +++ b/src/option_bytes.c @@ -119,17 +119,17 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->chip_id) { - case STLINK_CHIPID_STM32_F2: + case STM32_CHIPID_F2: return stlink_read_option_bytes_f2(sl, option_byte); - case STLINK_CHIPID_STM32_F4: - case STLINK_CHIPID_STM32_F446: + case STM32_CHIPID_F4: + case STM32_CHIPID_F446: return stlink_read_option_bytes_f4(sl, option_byte); - case STLINK_CHIPID_STM32_F76xxx: + case STM32_CHIPID_F76xxx: return stlink_read_option_bytes_f7(sl, option_byte); - case STLINK_CHIPID_STM32_G0_CAT1: - case STLINK_CHIPID_STM32_G0_CAT2: - case STLINK_CHIPID_STM32_G4_CAT2: - case STLINK_CHIPID_STM32_G4_CAT3: + case STM32_CHIPID_G0_CAT1: + case STM32_CHIPID_G0_CAT2: + case STM32_CHIPID_G4_CAT2: + case STM32_CHIPID_G4_CAT3: return stlink_read_option_bytes_Gx(sl, option_byte); default: return stlink_read_option_bytes_generic(sl, option_byte); @@ -513,27 +513,27 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_bytes_f0(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_F4: + case STM32_FLASH_TYPE_F2_F4: ret = stlink_write_option_bytes_f4(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_bytes_f7(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_L0: + case STM32_FLASH_TYPE_L0_L1: ret = stlink_write_option_bytes_l0(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_L4: + case STM32_FLASH_TYPE_L4_L4P: ret = stlink_write_option_bytes_l4(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_G0: - case STLINK_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: ret = stlink_write_option_bytes_gx(sl, base, addr, len); break; - case STLINK_FLASH_TYPE_H7: + case STM32_FLASH_TYPE_H7: ret = stlink_write_option_bytes_h7(sl, base, addr, len); break; default: @@ -739,11 +739,11 @@ int stlink_write_option_control_register32(stlink_t *sl, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_control_register_f0(sl, option_control_register); break; - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_control_register_f7(sl, option_control_register); break; default: @@ -788,7 +788,7 @@ int stlink_write_option_control_register1_32( } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_control_register1_f7(sl, option_control_register1); break; @@ -847,7 +847,7 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); break; default: @@ -937,7 +937,7 @@ int stlink_read_option_control_register1_32(stlink_t *sl, } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: return stlink_read_option_control_register1_f7(sl, option_byte); default: return -1; @@ -971,7 +971,7 @@ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: return stlink_read_option_bytes_boot_add_f7(sl, option_byte); default: return -1; @@ -1016,10 +1016,10 @@ int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->flash_type) { - case STLINK_FLASH_TYPE_F0: - case STLINK_FLASH_TYPE_F1_XL: + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: return stlink_read_option_control_register_f0(sl, option_byte); - case STLINK_FLASH_TYPE_F7: + case STM32_FLASH_TYPE_F7: return stlink_read_option_control_register_f7(sl, option_byte); default: return -1; From 935c6af9b48fe5fbe730c6801cf3720a4d8ae3f4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 Jan 2022 14:54:46 +0100 Subject: [PATCH 1302/1435] Updated description for F1 CL chip --- config/chips/F1xx_CL.chip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/chips/F1xx_CL.chip b/config/chips/F1xx_CL.chip index d774412e1..45f06d386 100644 --- a/config/chips/F1xx_CL.chip +++ b/config/chips/F1xx_CL.chip @@ -1,4 +1,4 @@ -# Chip-ID file for STM32F1xx Connectivity Line device +# Chip-ID file for STM32F1xx Connectivity Line device (F105 / F107) # dev_type STM32F1xx_CL ref_manual_id 0008 From 0011064797cd710f9b684e07c0083b5464e9a031 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 Jan 2022 15:47:55 +0100 Subject: [PATCH 1303/1435] Rolled-back deletion of recent changes --- CHANGELOG.md | 18 +- README.md | 2 +- cmake/modules/Findlibusb.cmake | 2 +- cmake/packaging/cpack_config.cmake | 2 +- cmake/packaging/deb/control | 2 +- contributors.txt | 3 + doc/compiling.md | 4 +- doc/version_support.md | 155 +- inc/stlink.h | 3 +- inc/stm32.h | 8 +- src/stlink-lib/chipid.h | 3 +- src/stlink-lib/usb.c.bak | 1410 ----------------- src/win32/unistd/unistd.h | 2 +- src/win32/unistd/unistd.h.bak | 76 - stlinkv1_macos_driver/install.sh | 3 - .../Contents/Info.plist | 82 - .../Contents/MacOS/stlink_shield_10_14 | Bin 33840 -> 0 bytes .../stlink_shield_10_14.kext/Contents/PkgInfo | 1 - .../Contents/_CodeSignature/CodeResources | 115 -- .../stlink_shield.xcodeproj/project.pbxproj | 50 - 20 files changed, 113 insertions(+), 1828 deletions(-) delete mode 100644 src/stlink-lib/usb.c.bak delete mode 100644 src/win32/unistd/unistd.h.bak delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/MacOS/stlink_shield_10_14 delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/PkgInfo delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/_CodeSignature/CodeResources diff --git a/CHANGELOG.md b/CHANGELOG.md index 06f995d21..71188afb0 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,10 +2,14 @@ # v1.7.1 -Release date: 2021-xx-xx +Release date: 2022-xx-xx This release drops support for some older operating systems. Check project README for details. -Updated system requirements: Raised minimum version for `cmake` to 3.7.2. + +Updated system requirements: +- `cmake` >= 3.10.2 +- `libusb` >= 1.0.21 +- `libgtk-dev` >= 3.22.30 Features: @@ -15,6 +19,9 @@ Features: - Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) - [STM32H72X/3X]: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) - Added support for STM32WLEx ([#1173](https://github.com/stlink-org/stlink/pull/1173)) +- Added support for STLINK-V3 devices with no MSD ([#1185](https://github.com/stlink-org/stlink/pull/1185)) +- Updated gdb-server.c to allow external memory access on STM32H73xx ([#1196](https://github.com/stlink-org/stlink/pull/1196), [#1197](https://github.com/stlink-org/stlink/pull/1197)) +- Erase addr size / section of the flash memory with st-flash ([#1213](https://github.com/stlink-org/stlink/pull/1213)) Updates & changes: @@ -22,10 +29,12 @@ Updates & changes: - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation ([#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) -- Drop execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) +- Dropped execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) - Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) - Removed redundant array ([#1178](https://github.com/stlink-org/stlink/pull/1178)) - Updated chip config files from the library structs ([#1181](https://github.com/stlink-org/stlink/pull/1181)) +- [doc] Corrected file path in tutorial ([#1186](https://github.com/stlink-org/stlink/pull/1186)) +- Improved chipid checks and printouts ([#1188](https://github.com/stlink-org/stlink/pull/1188)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) @@ -41,6 +50,9 @@ Fixes: - Fixed few warnings for msvc about type conversion with possible lost data ([#1179](https://github.com/stlink-org/stlink/pull/1179)) - st-flash and other utilities search for chip files in the wrong directory ([#1180](https://github.com/stlink-org/stlink/pull/1180), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) - Fixed broken build on 32 bit systems ([#985](https://github.com/stlink-org/stlink/pull/985), [#1175](https://github.com/stlink-org/stlink/pull/1175), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) +- Define 'SSIZE_MAX' if not defined ([#1183](https://github.com/stlink-org/stlink/pull/1183)) +- Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) +- Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) # v1.7.0 diff --git a/README.md b/README.md index 7f797a7d9..bc491189e 100644 --- a/README.md +++ b/README.md @@ -38,7 +38,7 @@ It supports several so called STLINK programmer boards (and clones thereof) whic - stand-alone programmer (STLINK-V3SET, STLINK-V3MINI, STLINK-V3MODS) - on-board on some STM32 Nucleo boards (STLINK-V3E) -_\*)_ **Note: Support for the STLINK/V1 on macOS is limited to 10.14 - 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.** +_\*)_ *Note: Support for the STLINK/V1 on macOS is limited to 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.* On the user level there is no difference in handling or operation between these different revisions. diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index cd52026f5..bc04f848d 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -72,7 +72,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to if (WIN32 AND NOT EXISTS "/etc/debian_version") # Skip this for Debian... # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.23) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index acd5630fa..587ff5fb5 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -53,7 +53,7 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av set(CPACK_DEBIAN_PACKAGE_RELEASE "1") # CPACK_DEBIAN_PACKAGE_ARCHITECTURE --> Default: Output of dpkg --print-architecture - set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.4.2), libusb-1.0-0-dev (>= 1.0.20)") + set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.10.2), libusb-1.0-0-dev (>= 1.0.21)") set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Nightwalker-87 ") # CPACK_DEBIAN_PACKAGE_DESCRIPTION --> Default: CPACK_DEBIAN_PACKAGE_DESCRIPTION (as it is set) # CPACK_DEBIAN_PACKAGE_SECTION --> Default: “devel” diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index ef51a6cea..7c8d13e47 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -1,7 +1,7 @@ Source: stlink Priority: optional Maintainer: Nightwalker-87 -Build-Depends: cmake, dh-cmake, debhelper (>= 9), libusb-1.0-0-dev, libgtk-3-dev +Build-Depends: cmake (>= 3.10.2), dh-cmake, debhelper (>= 9), libusb-1.0-0-dev (>= 1.0.21), libgtk-3-dev (>= 3.22.30) Standards-Version: 4.5.0 Rules-Requires-Root: no Section: electronics diff --git a/contributors.txt b/contributors.txt index bcaa0b538..cffef89f6 100644 --- a/contributors.txt +++ b/contributors.txt @@ -7,6 +7,8 @@ Andrea Mucignat Andrew Andrianov [necromant] Andrey Yurovsky Andy Isaacson +Andreas Sandberg [andysan] +Antoine Faure [antoinefaure] Anton [Ant-ON] Áron Radics A. Sheaff @@ -24,6 +26,7 @@ Chris Samuelson Christian Deussen [nullsub] Christophe Levantis Craig Lilley +Crest [Crest] Dan Dev Dan Hepler Daniel Campoverde [alx741] diff --git a/doc/compiling.md b/doc/compiling.md index eef207f95..0931c278a 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -7,7 +7,7 @@ On Windows users should ensure that the following software is installed: - `git` (_optional, but recommended_) -- `cmake` (3.17.0 or later) +- `cmake` - `MinGW-w64` (7.0.0 or later) with GCC toolchain 8.1.0 ### Installation @@ -95,7 +95,7 @@ Install the following packages from your package repository: - `git` - `gcc` or `clang` or `mingw32-gcc` or `mingw64-gcc` (C-compiler; very likely gcc is already present) - `build-essential` (on Debian based distros (Debian, Ubuntu)) -- `cmake` (3.4.2 or later, use the latest version available from the repository) +- `cmake` - `rpm` (on Debian based distros (Debian, Ubuntu), needed for package build with `make package`) - `libusb-1.0` - `libusb-1.0-0-dev` (development headers for building) diff --git a/doc/version_support.md b/doc/version_support.md index 2c5df7461..d7ba5c102 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,97 +1,104 @@ -_Source:_ pkgs.org - [libusb](https://pkgs.org/search/?q=libusb); [cmake](https://pkgs.org/search/?q=cmake); [gtk](https://pkgs.org/search/?q=gtk) (as of May 2021) +_Source:_ [pkgs.org](https://pkgs.org/search) - libusb, cmake, gtk, libgtk) (as of Jan 2022) ## Supported Operating Systems ### Microsoft Windows -On Windows users should ensure that cmake 3.20.2 or any later version is installed.
      -Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb` (1.0.23 at the time of writing). +On Windows users should ensure that cmake **3.10.2** or any later version is installed.
      +Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb`. - Windows 10 - Windows 8.1 ### Apple macOS -| Package Repository | libusb
      version | cmake
      version | gtk-3
      version | Supported macOS versions | -| ------------------ | ------------------- | ------------------ | ------------------ | ------------------------ | -| homebrew | 1.0.24 | 3.20.2 | 3.24.29
      gtk+3 | 10.9 - 11.x | -| MacPorts | 1.0.24 | 3.20.2 | 3.24.29
      gtk3 | 10.4 - 11.x | +| Package Repository | libusb | cmake | gtk-3-dev | Supported macOS versions | +| ------------------ | ------ | ------ | ------------------ | ------------------------ | +| homebrew | 1.0.24 | 3.22.1 | 3.24.30
      gtk+3 | **10.10 - 12.x** | +| MacPorts | 1.0.24 | 3.22.1 | 3.24.31
      gtk3 | **10.4 - 12.x** | -NOTE: In order to use a STLINK/V1 programmer on macOS, versions 10.14 or 10.15 are required. +NOTE: In order to use a STLINK/V1 programmer on macOS, version 10.15 is required. ### Linux-/Unix-based: -| Operating System | libusb | cmake | gtk-3 | Notes | -| ------------------------- | -------------------------------- | --------- | ----------- | ------------------------ | -| Debian Sid | 1.0.24 | 3.18.4 | 3.24.24 | | -| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | -| Debian 10 (Buster) | 1.0.**22** | 3.13.4 | 3.24.**5** | | -| Debian 9 (Stretch) | 1.0.**21** | **3.7.2** | **3.22.11** | End of Support: Jun 2022 | -| | | | | | -| Ubuntu 21.04 (Hirsute) | 1.0.24 | 3.18.4 | 3.24.25 | End of Support: Jan 2022 | -| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | -| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.10.2 | **3.22.30** | End of Support: Apr 2023 | -| | | | | | -| Fedora Rawhide [x64] | 1.0.24 (`libusbx`) | 3.20.2 | 3.24.29 | | -| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | -| Fedora 33 [x64] | 1.0.23 (`libusbx`) | 3.18.3 | 3.24.23 | | -| | | | | | -| openSUSE Tumbleweed [x64] | 1.0.24 | 3.20.1 | 3.24.29 | | -| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | | -| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.17.0 | 3.24.**14** | End of Support: Dec 2021 | -| | | | | | -| Alpine 3.14 | 1.0.24 | 3.20.3 | 4.2.1 | | -| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | -| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | -| Alpine 3.11 | 1.0.23 | 3.15.5 | 3.24.**13** | End of Support: Nov 2021 | -| | | | | | -| FreeBSD 13.x | 1.0.**16 - 18** (API 0x01000102) | 3.20.2 | 3.24.27 | | -| FreeBSD 12.x | 1.0.**16 - 18** (API 0x01000102) | 3.19.6 | 3.24.27 | | -| FreeBSD 11.x | 1.0.**16 - 18** (API 0x01000102) | 3.15.5 | 3.24.27 | End of Support: Sep 2021 | -| | | | | | -| Arch Linux | 1.0.24 | 3.20.2 | 3.24.29 | | -| KaOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| Mageia Cauldron | 1.0.24 | 3.20.2 | 3.24.29 | | -| OpenMandriva Cooker | 1.0.24 | 3.20.2 | 3.24.29 | | -| PCLinuxOS [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| Slackware Current | 1.0.24 | 3.20.2 | 3.24.28 | | -| Solus [x64] | 1.0.24 | 3.20.2 | 3.24.29 | | -| ALT Linux Sisyphus | 1.0.24 | 3.19.7 | 3.24.29 | | -| NetBSD 9.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | -| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | -| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.18.2 | **3.22.30** | | -| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | -| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.**11** | | -| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.11.4 | 3.24.32 | | -| CentOS 8 [x64] | 1.0.23 (`libusbx`) | 3.11.4 | **3.22.30** | End of Support: Dec 2021 | +| Operating System | libusb | cmake | libgtk-dev | Notes | +| ------------------------- | ------------------------------ | ---------- | ----------- | ------------------------ | +| Debian Sid | 1.0.24 | 3.22.1 | 3.24.31 | | +| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | +| Debian 10 (Buster) | 1.0.**22** | **3.13.4** | 3.24.**5** | | +| | | | | | +| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | +| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | **3.10.2** | 3.**22.30** | End of Support: Apr 2023 | +| | | | | | +| Fedora Rawhide [x64] | 1.0.24 | 3.22.3 | 3.24.31 | | +| Fedora 35 [x64] | 1.0.24 | 3.21.3 | 3.24.30 | | +| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | +| | | | | | +| openSUSE Tumbleweed [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | +| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | End of Support: Dec 2022 | +| | | | | | +| Alpine 3.15 | 1.0.24 | 3.21.3 | 3.24.30 | | +| Alpine 3.14 | 1.0.24 | 3.20.3 | 3.24.28 | | +| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | +| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | +| | | | | | +| FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | +| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | +| | | | | | +| NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | +| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | +| | | | | | +| CentOS 9 Stream [x64] | 1.0.24 (`libusbx`) | 3.20.3 | 3.24.30 | | +| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | +| | | | | | +| ALT Linux Sisyphus | 1.0.24 | 3.22.1 | 3.24.31 | | +| ALT Linux P10 | 1.0.24 | 3.20.5 | 3.24.31 | | +| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.29 | | +| | | | | | +| OpenMandriva Rolling | 1.0.24 | 3.22.1 | 3.24.31 | | +| OpenMandriva Cooker | 1.0.24 | 3.22.1 | 3.24.31 | | +| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | +| | | | | | +| Arch Linux | 1.0.24 | 3.22.1 | - | | +| KaOS [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | +| Mageia Cauldron | 1.0.24 | 3.22.1 | 3.24.31 | | +| PCLinuxOS [x64] | ? | 3.22.1 | 3.24.31 | | +| Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | +| Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | +| Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | +| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | +| Rocky Linux 8 [x64] | 1.0.23 | 3.20.2 | 3.**22.30** | | +| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | +| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | ## Unsupported Operating Systems (as of Release v1.7.1) Systems with highlighted versions remain compatible with this toolset. -| Operating System | libusb | cmake | End of
      OS-Support | -| ------------------------- | ---------------------- | ---------- | ---------------------- | -| Fedora 32 [x64] | **1.0.23** (`libusbx`) | **3.17.0** | May 2021 | -| Ubuntu 20.10 (Groovy) | **1.0.23** | **3.16.3** | Jul 2021 | -| NetBSD 7.x | **1.0.22** | **3.16.1** | Jun 2020 | -| Alpine 3.10 | **1.0.22** | **3.14.5** | May 2021 | -| Fedora 31 [x64] | **1.0.22** (`libusbx`) | **3.14.5** | Nov 2020 | -| Mageia 7.1 | **1.0.22** | **3.14.3** | Jun 2021 | -| Fedora 30 | **1.0.22** (`libusbx`) | **3.14.2** | May 2020 | -| Ubuntu 19.10 (Eoan) | **1.0.23** | **3.13.4** | Jul 2020 | -| Alpine 3.9 | **1.0.22** | **3.13.0** | Jan 2021 | -| openSUSE Leap 15.1 [x64] | **1.0.21** | **3.10.2** | Jan 2021 | -| Slackware 14.2 | 1.0.20 | 3.5.2 | | -| Ubuntu 16.04 LTS (Xenial) | 1.0.20 | 3.5.1 | Apr 2021 | -| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | -| Debian 8 (Jessie) | 1.0.19 | 3.0.2 | Jun 2020 | -| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | -| Ubuntu 14.04 LTS (Trusty) | 1.0.17 | 2.8.12.2 | Apr 2019 | -| CentOS 6 | 1.0.9 (`libusbx`) | 2.8.12.2 | Nov 2020 | -| Slackware 14.1 | 1.0.9 | 2.8.12 | | -| Slackware 14.0 | 1.0.9 | 2.8.8 | | +| Operating System | libusb | cmake | End of
      OS-Support | +| ------------------------ | ------------------------------ | ---------- | ---------------------- | +| CentOS 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | +| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | +| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | +| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | +| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | +| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | +| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | +| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | +| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | +| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | +| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | +| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | +| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | +| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | +| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | +| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | +| Debian 9 (Stretch) | 1.0.**21** | 3.7.2 | Jun 2022 | +| Slackware 14.2 | 1.0.20 | 3.5.2 | | +| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | +| CentOS 7 [x64] | 1.0.**21** (`libusbx`) | 2.8.12.2 | Jun 2024 | +| Slackware 14.1 | 1.0.9 | 2.8.12 | | +| Slackware 14.0 | 1.0.9 | 2.8.8 | | _All other operating systems which are not listed are unsupported._ diff --git a/inc/stlink.h b/inc/stlink.h index 7dfd8a71e..17601fda8 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -1,6 +1,7 @@ /* * File: stlink.h + * * This should contain all the common top level stlink interfaces, * regardless of how the backend does the work.... */ @@ -184,7 +185,7 @@ enum run_type { typedef struct _stlink stlink_t; -#include // Is it really need? +#include #include struct _stlink { diff --git a/inc/stm32.h b/inc/stm32.h index 19ba3fca0..473f65a56 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -149,11 +149,11 @@ enum stm32_chipids { /* ============ */ /* Constant STM32 memory address */ -#define STM32_SRAM_BASE ((uint32_t)0x20000000) -#define STM32_FLASH_BASE ((uint32_t)0x08000000) +#define STM32_SRAM_BASE ((uint32_t)0x20000000) +#define STM32_FLASH_BASE ((uint32_t)0x08000000) -#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) -#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) +#define STM32_F1_FLASH_BANK2_BASE ((uint32_t)0x08080000) +#define STM32_H7_FLASH_BANK2_BASE ((uint32_t)0x08100000) #define STM32F0_DBGMCU_CR 0xE0042004 #define STM32F0_DBGMCU_CR_IWDG_STOP 8 diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index f8e1b3444..1eae2cc34 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -4,8 +4,7 @@ #include #include - -/** Chipid parameters */ +/* Chipid parametres */ struct stlink_chipid_params { char *dev_type; char *ref_manual_id; diff --git a/src/stlink-lib/usb.c.bak b/src/stlink-lib/usb.c.bak deleted file mode 100644 index 32ceff71f..000000000 --- a/src/stlink-lib/usb.c.bak +++ /dev/null @@ -1,1410 +0,0 @@ -#include -#include -#include -#include -#include - -#if !defined(_MSC_VER) -#include -#endif - -#include -#include -#include - -#if defined(_WIN32) -#include -#endif - -#include -#include -#include "usb.h" - -enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; - -static inline uint32_t le_to_h_u32(const uint8_t* buf) { - return((uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24)); -} - -static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, uint32_t khz) { - unsigned int i; - int speed_index = -1; - int speed_diff = INT_MAX; - int last_valid_speed = -1; - bool match = true; - - for (i = 0; i < map_size; i++) { - if (!map[i]) { continue; } - - last_valid_speed = i; - - if (khz == map[i]) { - speed_index = i; - break; - } else { - int current_diff = khz - map[i]; - // get abs value for comparison - current_diff = (current_diff > 0) ? current_diff : -current_diff; - - if (current_diff < speed_diff) { - speed_diff = current_diff; - speed_index = i; - } - } - } - - if (speed_index == -1) { - // This will only be here if we cannot match the slow speed. - // Use the slowest speed we support. - speed_index = last_valid_speed; - match = false; - } else if (i == map_size) { - match = false; - } - - if (!match) { - ILOG("Unable to match requested speed %d kHz, using %d kHz\n", khz, map[speed_index]); - } - - return(speed_index); -} - -void _stlink_usb_close(stlink_t* sl) { - if (!sl) { return; } - - struct stlink_libusb * const handle = sl->backend_data; - - // maybe we couldn't even get the usb device? - if (handle != NULL) { - if (handle->usb_handle != NULL) { libusb_close(handle->usb_handle); } - - libusb_exit(handle->libusb_ctx); - free(handle); - } -} - -ssize_t send_recv(struct stlink_libusb* handle, int terminate, - unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, - size_t rxsize, int check_error, const char *cmd) { - // Note: txbuf and rxbuf can point to the same area - int res, t, retry = 0; - - while (1) { - res = 0; - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int)txsize, &res, 3000); - - if (t) { - ELOG("%s send request failed: %s\n", cmd, libusb_error_name(t)); - return(-1); - } else if ((size_t)res != txsize) { - ELOG("%s send request wrote %u bytes, instead of %u\n", - cmd, (unsigned int)res, (unsigned int)txsize); - } - - if (rxsize != 0) { - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int)rxsize, &res, 3000); - - if (t) { - ELOG("%s read reply failed: %s\n", cmd, libusb_error_name(t)); - return(-1); - } - - /* Checking the command execution status stored in the first byte of the response */ - if (handle->protocoll != 1 && check_error >= CMD_CHECK_STATUS && - rxbuf[0] != STLINK_DEBUG_ERR_OK) { - switch(rxbuf[0]) { - case STLINK_DEBUG_ERR_AP_WAIT: - case STLINK_DEBUG_ERR_DP_WAIT: - if (check_error == CMD_CHECK_RETRY && retry < 3) { - unsigned int delay_us = (1<protocoll == 1) && terminate) { - // read the SG reply - unsigned char sg_buf[13]; - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, sg_buf, 13, &res, 3000); - - if (t) { - ELOG("%s read storage failed: %s\n", cmd, libusb_error_name(t)); - return(-1); - } - - // The STLink doesn't seem to evaluate the sequence number. - handle->sg_transfer_idx++; - } - - return(res); - } -} - -static inline int send_only(struct stlink_libusb* handle, int terminate, - unsigned char* txbuf, size_t txsize, - const char *cmd) { - return((int)send_recv(handle, terminate, txbuf, txsize, NULL, 0, CMD_CHECK_NO, cmd)); -} - - -static int fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t len) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - int i = 0; - memset(cmd, 0, sizeof(sl->c_buf)); - - if (slu->protocoll == 1) { - cmd[i++] = 'U'; - cmd[i++] = 'S'; - cmd[i++] = 'B'; - cmd[i++] = 'C'; - write_uint32(&cmd[i], slu->sg_transfer_idx); - write_uint32(&cmd[i + 4], len); - i += 8; - cmd[i++] = (dir == SG_DXFER_FROM_DEV) ? 0x80 : 0; - cmd[i++] = 0; // logical unit - cmd[i++] = 0xa; // command length - } - return(i); -} - -int _stlink_usb_version(stlink_t *sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - uint32_t rep_len; - int i; - - if (sl->version.stlink_v == 3) { - // STLINK-V3 version is determined by another command - rep_len = 12; - i = fill_command(sl, SG_DXFER_FROM_DEV, 16); - cmd[i++] = STLINK_GET_VERSION_APIV3; - } else { - rep_len = 6; - i = fill_command(sl, SG_DXFER_FROM_DEV, 6); - cmd[i++] = STLINK_GET_VERSION; - } - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_REP_LEN, "GET_VERSION"); - - return(size<0?-1:0); -} - -int32_t _stlink_usb_target_voltage(stlink_t *sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const rdata = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - uint32_t rep_len = 8; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - uint32_t factor, reading; - int voltage; - - cmd[i++] = STLINK_GET_TARGET_VOLTAGE; - - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_REP_LEN, "GET_TARGET_VOLTAGE"); - - if (size < 0) { - return(-1); - } - - factor = (rdata[3] << 24) | (rdata[2] << 16) | (rdata[1] << 8) | (rdata[0] << 0); - reading = (rdata[7] << 24) | (rdata[6] << 16) | (rdata[5] << 8) | (rdata[4] << 0); - voltage = 2400 * reading / factor; - - return(voltage); -} - -int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const rdata = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - const int rep_len = 8; - - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV2_READDEBUGREG; - write_uint32(&cmd[i], addr); - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "READDEBUGREG"); - - if (size < 0) { - return(-1); - } - - *data = read_uint32(rdata, 4); - - return(0); -} - -int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const rdata = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - const int rep_len = 2; - - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; - write_uint32(&cmd[i], addr); - write_uint32(&cmd[i + 4], data); - size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "WRITEDEBUGREG"); - - return(size<0?-1:0); -} - -int _stlink_usb_get_rw_status(stlink_t *sl) { - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return(0); } - - unsigned char* const rdata = sl->q_buf; - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - int i; - int16_t ret = 0; - - i = fill_command(sl, SG_DXFER_FROM_DEV, 12); - cmd[i++] = STLINK_DEBUG_COMMAND; - - if (sl->version.flags & STLINK_F_HAS_GETLASTRWSTATUS2) { - cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS2; - ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 12, CMD_CHECK_STATUS, "GETLASTRWSTATUS2"); - } else { - cmd[i++] = STLINK_DEBUG_APIV2_GETLASTRWSTATUS; - ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2, CMD_CHECK_STATUS, "GETLASTRWSTATUS"); - } - - return(ret<0?-1:0); -} - -int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - int i, ret; - - i = fill_command(sl, SG_DXFER_TO_DEV, len); - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_WRITEMEM_32BIT; - write_uint32(&cmd[i], addr); - write_uint16(&cmd[i + 4], len); - ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_32BIT"); - - if (ret == -1) { return(ret); } - - ret = send_only(slu, 1, data, len, "WRITEMEM_32BIT"); - - if (ret == -1) { return(ret); } - - return(_stlink_usb_get_rw_status(sl)); -} - -int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - int i, ret; - - if ((sl->version.jtag_api < STLINK_JTAG_API_V3 && len > 64) || - (sl->version.jtag_api >= STLINK_JTAG_API_V3 && len > 512)) { - ELOG("WRITEMEM_8BIT: bulk packet limits exceeded (data len %d byte)\n", len); - return (-1); - } - - i = fill_command(sl, SG_DXFER_TO_DEV, 0); - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_WRITEMEM_8BIT; - write_uint32(&cmd[i], addr); - write_uint16(&cmd[i + 4], len); - ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_8BIT"); - - if (ret == -1) { return(ret); } - - ret = send_only(slu, 1, data, len, "WRITEMEM_8BIT"); - - if (ret == -1) { return(ret); } - - return(0); -} - - -int _stlink_usb_current_mode(stlink_t * sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - unsigned char* const data = sl->q_buf; - ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_GET_CURRENT_MODE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_CURRENT_MODE"); - - if (size < 0) { - return(-1); - } - - return(sl->q_buf[0]); -} - -int _stlink_usb_core_id(stlink_t * sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - unsigned char* const data = sl->q_buf; - ssize_t size; - int offset, rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 12; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { - cmd[i++] = STLINK_DEBUG_READCOREID; - offset = 0; - } else { - cmd[i++] = STLINK_DEBUG_APIV2_READ_IDCODES; - offset = 4; - } - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READ_IDCODES"); - - if (size < 0) { - return(-1); - } - - sl->core_id = read_uint32(data, offset); - - return(0); -} - -int _stlink_usb_status_v2(stlink_t *sl) { - int result; - uint32_t status = 0; - - result = _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &status); - DLOG("core status: %08X\n", status); - - if (result != 0) { - sl->core_stat = TARGET_UNKNOWN; - } else { - if (status & STLINK_REG_DHCSR_C_HALT) { - sl->core_stat = TARGET_HALTED; - } else if (status & STLINK_REG_DHCSR_S_RESET_ST) { - sl->core_stat = TARGET_RESET; - } else { - sl->core_stat = TARGET_RUNNING; - } - } - - return(result); -} - -int _stlink_usb_status(stlink_t * sl) { - if (sl->version.jtag_api != STLINK_JTAG_API_V1) { return(_stlink_usb_status_v2(sl)); } - - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_GETSTATUS; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GETSTATUS"); - - if (size > 1) { - if (sl->q_buf[0] == STLINK_CORE_RUNNING) { - sl->core_stat = TARGET_RUNNING; - } else if (sl->q_buf[0] == STLINK_CORE_HALTED) { - sl->core_stat = TARGET_HALTED; - } else { - sl->core_stat = TARGET_UNKNOWN; - } - } else { - sl->core_stat = TARGET_UNKNOWN; - } - - return(size<0?-1:0); -} - -int _stlink_usb_force_debug(stlink_t *sl) { - struct stlink_libusb *slu = sl->backend_data; - - int res; - - if (sl->version.jtag_api != STLINK_JTAG_API_V1) { - res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); - return(res); - } - - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_FORCEDEBUG; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "FORCEDEBUG"); - - return(size<0?-1:0); -} - -int _stlink_usb_enter_swd_mode(stlink_t * sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - unsigned char* const data = sl->q_buf; - const uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - // select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). - cmd[i++] = sl->version.jtag_api == STLINK_JTAG_API_V1 ? STLINK_DEBUG_APIV1_ENTER : STLINK_DEBUG_APIV2_ENTER; - cmd[i++] = STLINK_DEBUG_ENTER_SWD; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "ENTER_SWD"); - - return(size<0?-1:0); -} - -int _stlink_usb_exit_dfu_mode(stlink_t* sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); - - cmd[i++] = STLINK_DFU_COMMAND; - cmd[i++] = STLINK_DFU_EXIT; - size = send_only(slu, 1, cmd, slu->cmd_len, "DFU_EXIT"); - - return(size<0?-1:0); -} - - -int _stlink_usb_reset(stlink_t * sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int i, rep_len = 2; - - // send reset command - i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - cmd[i++] = STLINK_DEBUG_COMMAND; - - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { - cmd[i++] = STLINK_DEBUG_APIV1_RESETSYS; - } else { - cmd[i++] = STLINK_DEBUG_APIV2_RESETSYS; - } - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RESETSYS"); - - return(size<0?-1:0); -} - -int _stlink_usb_jtag_reset(stlink_t * sl, int value) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV2_DRIVE_NRST; - cmd[i++] = value; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "DRIVE_NRST"); - - return(size<0?-1:0); -} - - -int _stlink_usb_step(stlink_t* sl) { - struct stlink_libusb * const slu = sl->backend_data; - - if (sl->version.jtag_api != STLINK_JTAG_API_V1) { - // emulates the JTAG v1 API by using DHCSR - _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN); - _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_STEP | - STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN); - return _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_DEBUGEN); - } - - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_STEPCORE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "STEPCORE"); - - return(size<0?-1:0); -} - -/** - * This seems to do a good job of restarting things from the beginning? - * @param sl - * @param type - */ -int _stlink_usb_run(stlink_t* sl, enum run_type type) { - struct stlink_libusb * const slu = sl->backend_data; - - int res; - - if (sl->version.jtag_api != STLINK_JTAG_API_V1) { - res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - ((type==RUN_FLASH_LOADER)?STLINK_REG_DHCSR_C_MASKINTS:0)); - return(res); - } - - - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_RUNCORE; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RUNCORE"); - - return(size<0?-1:0); -} - -int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int rep_len = 2; - int i; - - // clock speed only supported by stlink/v2 and for firmware >= 22 - if (sl->version.stlink_v == 2 && sl->version.jtag_v >= 22) { - uint16_t clk_divisor; - if (clk_freq) { - const uint32_t map[] = {5, 15, 25, 50, 100, 125, 240, 480, 950, 1200, 1800, 4000}; - int speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); - switch (map[speed_index]) { - case 5: clk_divisor = STLINK_SWDCLK_5KHZ_DIVISOR; break; - case 15: clk_divisor = STLINK_SWDCLK_15KHZ_DIVISOR; break; - case 25: clk_divisor = STLINK_SWDCLK_25KHZ_DIVISOR; break; - case 50: clk_divisor = STLINK_SWDCLK_50KHZ_DIVISOR; break; - case 100: clk_divisor = STLINK_SWDCLK_100KHZ_DIVISOR; break; - case 125: clk_divisor = STLINK_SWDCLK_125KHZ_DIVISOR; break; - case 240: clk_divisor = STLINK_SWDCLK_240KHZ_DIVISOR; break; - case 480: clk_divisor = STLINK_SWDCLK_480KHZ_DIVISOR; break; - case 950: clk_divisor = STLINK_SWDCLK_950KHZ_DIVISOR; break; - case 1200: clk_divisor = STLINK_SWDCLK_1P2MHZ_DIVISOR; break; - default: - case 1800: clk_divisor = STLINK_SWDCLK_1P8MHZ_DIVISOR; break; - case 4000: clk_divisor = STLINK_SWDCLK_4MHZ_DIVISOR; break; - } - } else - clk_divisor = STLINK_SWDCLK_1P8MHZ_DIVISOR; - - i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV2_SWD_SET_FREQ; - cmd[i++] = clk_divisor & 0xFF; - cmd[i++] = (clk_divisor >> 8) & 0xFF; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "SWD_SET_FREQ"); - - return(size<0?-1:0); - } else if (sl->version.stlink_v == 3) { - int speed_index; - uint32_t map[STLINK_V3_MAX_FREQ_NB]; - i = fill_command(sl, SG_DXFER_FROM_DEV, 16); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV3_GET_COM_FREQ; - cmd[i++] = 0; // SWD mode - size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52, CMD_CHECK_STATUS, "GET_COM_FREQ"); - - if (size < 0) { - return(-1); - } - - int speeds_size = data[8]; - if (speeds_size > STLINK_V3_MAX_FREQ_NB) { - speeds_size = STLINK_V3_MAX_FREQ_NB; - } - - for (i = 0; i < speeds_size; i++) map[i] = le_to_h_u32(&data[12 + 4 * i]); - - // Set to zero all the next entries - for (i = speeds_size; i < STLINK_V3_MAX_FREQ_NB; i++) map[i] = 0; - - if (!clk_freq) clk_freq = 1000; // set default frequency - speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); - - i = fill_command(sl, SG_DXFER_FROM_DEV, 16); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV3_SET_COM_FREQ; - cmd[i++] = 0; // SWD mode - cmd[i++] = 0; - cmd[i++] = (uint8_t)((map[speed_index] >> 0) & 0xFF); - cmd[i++] = (uint8_t)((map[speed_index] >> 8) & 0xFF); - cmd[i++] = (uint8_t)((map[speed_index] >> 16) & 0xFF); - cmd[i++] = (uint8_t)((map[speed_index] >> 24) & 0xFF); - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8, CMD_CHECK_STATUS, "SET_COM_FREQ"); - - return(size<0?-1:0); - } else if (clk_freq) { - WLOG("ST-Link firmware does not support frequency setup\n"); - } - - return(-1); -} - -int _stlink_usb_exit_debug_mode(stlink_t *sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_EXIT; - - size = send_only(slu, 1, cmd, slu->cmd_len, "DEBUG_EXIT"); - - return(size<0?-1:0); -} - -int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_READMEM_32BIT; - write_uint32(&cmd[i], addr); - write_uint16(&cmd[i + 4], len); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, len, CMD_CHECK_NO, "READMEM_32BIT"); - - if (size < 0) { - return(-1); - } - - sl->q_len = (int)size; - stlink_print_data(sl); - - return(0); -} - -int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const cmd = sl->c_buf; - unsigned char* const data = sl->q_buf; - ssize_t size; - uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 84 : 88; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { - cmd[i++] = STLINK_DEBUG_APIV1_READALLREGS; - } else { - cmd[i++] = STLINK_DEBUG_APIV2_READALLREGS; - } - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READALLREGS"); - - if (size < 0) { - return(-1); - } - - /* V1: regs data from offset 0 */ - /* V2: status at offset 0, regs data from offset 4 */ - int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; - sl->q_len = (int)size; - stlink_print_data(sl); - - for (i = 0; i < 16; i++) regp->r[i] = read_uint32(sl->q_buf, reg_offset + i * 4); - - regp->xpsr = read_uint32(sl->q_buf, reg_offset + 64); - regp->main_sp = read_uint32(sl->q_buf, reg_offset + 68); - regp->process_sp = read_uint32(sl->q_buf, reg_offset + 72); - regp->rw = read_uint32(sl->q_buf, reg_offset + 76); - regp->rw2 = read_uint32(sl->q_buf, reg_offset + 80); - - if (sl->verbose < 2) { return(0); } - - DLOG("xpsr = 0x%08x\n", regp->xpsr); - DLOG("main_sp = 0x%08x\n", regp->main_sp); - DLOG("process_sp = 0x%08x\n", regp->process_sp); - DLOG("rw = 0x%08x\n", regp->rw); - DLOG("rw2 = 0x%08x\n", regp->rw2); - - return(0); -} - -int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - uint32_t r; - uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 8; - int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { - cmd[i++] = STLINK_DEBUG_APIV1_READREG; - } else { - cmd[i++] = STLINK_DEBUG_APIV2_READREG; - } - - cmd[i++] = (uint8_t)r_idx; - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "READREG"); - - if (size < 0) { - return(-1); - } - - sl->q_len = (int)size; - stlink_print_data(sl); - r = read_uint32(sl->q_buf, reg_offset); - DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); - - switch (r_idx) { - case 16: - regp->xpsr = r; - break; - case 17: - regp->main_sp = r; - break; - case 18: - regp->process_sp = r; - break; - case 19: - regp->rw = r; // XXX ?(primask, basemask etc.) - break; - case 20: - regp->rw2 = r; // XXX ?(primask, basemask etc.) - break; - default: - regp->r[r_idx] = r; - } - - return(0); -} - -/* See section C1.6 of the ARMv7-M Architecture Reference Manual */ -int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { - uint32_t r; - int ret; - - sl->q_buf[0] = (unsigned char)r_idx; - - for (int i = 1; i < 4; i++) sl->q_buf[i] = 0; - - ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); - - if (ret == -1) { return(ret); } - - ret = _stlink_usb_read_mem32(sl, STLINK_REG_DCRDR, 4); - - if (ret == -1) { return(ret); } - - r = read_uint32(sl->q_buf, 0); - DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); - - switch (r_idx) { - case 0x14: - regp->primask = (uint8_t)(r & 0xFF); - regp->basepri = (uint8_t)((r >> 8) & 0xFF); - regp->faultmask = (uint8_t)((r >> 16) & 0xFF); - regp->control = (uint8_t)((r >> 24) & 0xFF); - break; - case 0x21: - regp->fpscr = r; - break; - default: - regp->s[r_idx - 0x40] = r; - break; - } - - return(0); -} - -int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { - int ret; - - ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); - - if (ret == -1) { return(ret); } - - ret = _stlink_usb_read_unsupported_reg(sl, 0x21, regp); - - if (ret == -1) { return(ret); } - - for (int i = 0; i < 32; i++) { - ret = _stlink_usb_read_unsupported_reg(sl, 0x40 + i, regp); - - if (ret == -1) { return(ret); } - } - - return(0); -} - -/* See section C1.6 of the ARMv7-M Architecture Reference Manual */ -int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct stlink_reg *regp) { - int ret; - - if (r_idx >= 0x1C && r_idx <= 0x1F) { // primask, basepri, faultmask, or control - /* These are held in the same register */ - ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); - - if (ret == -1) { return(ret); } - - val = (uint8_t)(val >> 24); - - switch (r_idx) { - case 0x1C: /* control */ - val = (((uint32_t)val) << 24) | - (((uint32_t)regp->faultmask) << 16) | - (((uint32_t)regp->basepri) << 8) | - ((uint32_t)regp->primask); - break; - case 0x1D: /* faultmask */ - val = (((uint32_t)regp->control) << 24) | - (((uint32_t)val) << 16) | - (((uint32_t)regp->basepri) << 8) | - ((uint32_t)regp->primask); - break; - case 0x1E: /* basepri */ - val = (((uint32_t)regp->control) << 24) | - (((uint32_t)regp->faultmask) << 16) | - (((uint32_t)val) << 8) | - ((uint32_t)regp->primask); - break; - case 0x1F: /* primask */ - val = (((uint32_t)regp->control) << 24) | - (((uint32_t)regp->faultmask) << 16) | - (((uint32_t)regp->basepri) << 8) | - ((uint32_t)val); - break; - } - - r_idx = 0x14; - } - - write_uint32(sl->q_buf, val); - - ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRDR, 4); - - if (ret == -1) { return(ret); } - - sl->q_buf[0] = (unsigned char)r_idx; - sl->q_buf[1] = 0; - sl->q_buf[2] = 0x01; - sl->q_buf[3] = 0; - - return(_stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4)); -} - -int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { - cmd[i++] = STLINK_DEBUG_APIV1_WRITEREG; - } else { - cmd[i++] = STLINK_DEBUG_APIV2_WRITEREG; - } - - cmd[i++] = idx; - write_uint32(&cmd[i], reg); - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "WRITEREG"); - - return(size<0?-1:0); -} - -int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - uint32_t rep_len = 2; - - int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; - write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); - write_uint32(&cmd[i + 2], frequency); - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "START_TRACE_RX"); - - return(size<0?-1:0); -} - -int _stlink_usb_disable_trace(stlink_t* sl) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - ssize_t size; - uint32_t rep_len = 2; - - int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; - - size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "STOP_TRACE_RX"); - - return(size<0?-1:0); -} - -int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { - struct stlink_libusb * const slu = sl->backend_data; - unsigned char* const data = sl->q_buf; - unsigned char* const cmd = sl->c_buf; - uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); - - cmd[i++] = STLINK_DEBUG_COMMAND; - cmd[i++] = STLINK_DEBUG_APIV2_GET_TRACE_NB; - ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_TRACE_NB"); - - if (send_size < 0) { - return(-1); - } else if (send_size != 2) { - ELOG("STLINK_DEBUG_APIV2_GET_TRACE_NB reply size %d\n", (int)send_size); - return(-1); - } - - uint16_t trace_count = read_uint16(sl->q_buf, 0); - - if (trace_count > size) { - ELOG("read_trace insufficient buffer length\n"); - return -1; - } - - if (trace_count != 0) { - int res = 0; - int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); - - if (t || res != (int)trace_count) { - ELOG("read_trace read error %d\n", t); - return(-1); - } - } - - return trace_count; -} - -static stlink_backend_t _stlink_usb_backend = { - _stlink_usb_close, - _stlink_usb_exit_debug_mode, - _stlink_usb_enter_swd_mode, - NULL, // don't enter_jtag_mode here... - _stlink_usb_exit_dfu_mode, - _stlink_usb_core_id, - _stlink_usb_reset, - _stlink_usb_jtag_reset, - _stlink_usb_run, - _stlink_usb_status, - _stlink_usb_version, - _stlink_usb_read_debug32, - _stlink_usb_read_mem32, - _stlink_usb_write_debug32, - _stlink_usb_write_mem32, - _stlink_usb_write_mem8, - _stlink_usb_read_all_regs, - _stlink_usb_read_reg, - _stlink_usb_read_all_unsupported_regs, - _stlink_usb_read_unsupported_reg, - _stlink_usb_write_unsupported_reg, - _stlink_usb_write_reg, - _stlink_usb_step, - _stlink_usb_current_mode, - _stlink_usb_force_debug, - _stlink_usb_target_voltage, - _stlink_usb_set_swdclk, - _stlink_usb_enable_trace, - _stlink_usb_disable_trace, - _stlink_usb_read_trace -}; - -/* return the length of serial or (0) in case of errors */ -size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_descriptor *desc, char *serial) { - unsigned char desc_serial[(STLINK_SERIAL_LENGTH) * 2]; - - /* truncate the string in the serial buffer */ - serial[0] = '\0'; - - /* get the LANGID from String Descriptor Zero */ - int ret = libusb_get_string_descriptor(handle, 0, 0, desc_serial, sizeof(desc_serial)); - if (ret < 4) return 0; - - uint32_t langid = desc_serial[2] | (desc_serial[3] << 8); - - /* get the serial */ - ret = libusb_get_string_descriptor(handle, desc->iSerialNumber, langid, desc_serial, - sizeof(desc_serial)); - if (ret < 0) return 0; // could not read serial - - unsigned char len = desc_serial[0]; - - if (len == ((STLINK_SERIAL_LENGTH + 1) * 2)) { /* len == 50 */ - /* good ST-Link adapter */ - ret = libusb_get_string_descriptor_ascii( - handle, desc->iSerialNumber, (unsigned char *)serial, STLINK_SERIAL_BUFFER_SIZE); - if (ret < 0) return 0; - } else if (len == ((STLINK_SERIAL_LENGTH / 2 + 1) * 2)) { /* len == 26 */ - /* fix-up the buggy serial */ - for (unsigned int i = 0; i < STLINK_SERIAL_LENGTH; i += 2) - sprintf(serial + i, "%02X", desc_serial[i + 2]); - serial[STLINK_SERIAL_LENGTH] = '\0'; - } else { - return 0; - } - - return strlen(serial); -} - -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq) { - stlink_t* sl = NULL; - struct stlink_libusb* slu = NULL; - int ret = -1; - int config; - - sl = calloc(1, sizeof(stlink_t)); - if (sl == NULL) { goto on_malloc_error; } - - slu = calloc(1, sizeof(struct stlink_libusb)); - if (slu == NULL) { goto on_malloc_error; } - - ugly_init(verbose); - sl->backend = &_stlink_usb_backend; - sl->backend_data = slu; - - sl->core_stat = TARGET_UNKNOWN; - - if (libusb_init(&(slu->libusb_ctx))) { - WLOG("failed to init libusb context, wrong version of libraries?\n"); - goto on_error; - } - -#if LIBUSB_API_VERSION < 0x01000106 - libusb_set_debug(slu->libusb_ctx, ugly_libusb_log_level(verbose)); -#else - libusb_set_option(slu->libusb_ctx, LIBUSB_OPTION_LOG_LEVEL, ugly_libusb_log_level(verbose)); -#endif - - libusb_device **list = NULL; - // TODO: We should use ssize_t and use it as a counter if > 0. - // As per libusb API: ssize_t libusb_get_device_list (libusb_context *ctx, libusb_device ***list) - ssize_t cnt = libusb_get_device_list(slu->libusb_ctx, &list); - struct libusb_device_descriptor desc; - - while (cnt-- > 0) { - struct libusb_device_handle *handle; - - libusb_get_device_descriptor(list[cnt], &desc); - - if (desc.idVendor != STLINK_USB_VID_ST) { continue; } - - ret = libusb_open(list[cnt], &handle); - - if (ret) { continue; } // could not open device - - size_t serial_len = stlink_serial(handle, &desc, sl->serial); - - libusb_close(handle); - - if (serial_len != STLINK_SERIAL_LENGTH) { continue; } // could not read the serial - - // if no serial provided, or if serial match device, fixup version and protocol - if (((serial == NULL) || (*serial == 0)) || (memcmp(serial, &sl->serial, STLINK_SERIAL_LENGTH) == 0)) { - if (STLINK_V1_USB_PID(desc.idProduct)) { - slu->protocoll = 1; - sl->version.stlink_v = 1; - } else if (STLINK_V2_USB_PID(desc.idProduct) || STLINK_V2_1_USB_PID(desc.idProduct)) { - sl->version.stlink_v = 2; - } else if (STLINK_V3_USB_PID(desc.idProduct)) { - sl->version.stlink_v = 3; - } - - break; - } - } - - if (cnt < 0) { - WLOG ("Couldn't find any ST-Link devices\n"); - libusb_free_device_list(list, 1); - goto on_error; - } else { - ret = libusb_open(list[cnt], &slu->usb_handle); - - if (ret != 0) { - WLOG("Error %d (%s) opening ST-Link v%d device %03d:%03d\n", ret, - strerror(errno), - sl->version.stlink_v, - libusb_get_bus_number(list[cnt]), - libusb_get_device_address(list[cnt])); - libusb_free_device_list(list, 1); - goto on_error; - } - } - - libusb_free_device_list(list, 1); - -// libusb_kernel_driver_active is not available on Windows. -#if !defined(_WIN32) - if (libusb_kernel_driver_active(slu->usb_handle, 0) == 1) { - ret = libusb_detach_kernel_driver(slu->usb_handle, 0); - - if (ret < 0) { - WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-ret)); - goto on_libusb_error; - } - } -#endif - - if (libusb_get_configuration(slu->usb_handle, &config)) { - // this may fail for a previous configured device - WLOG("libusb_get_configuration()\n"); - goto on_libusb_error; - } - - if (config != 1) { - printf("setting new configuration (%d -> 1)\n", config); - - if (libusb_set_configuration(slu->usb_handle, 1)) { - // this may fail for a previous configured device - WLOG("libusb_set_configuration() failed\n"); - goto on_libusb_error; - } - } - - if (libusb_claim_interface(slu->usb_handle, 0)) { - WLOG("Stlink usb device found, but unable to claim (probably already in use?)\n"); - goto on_libusb_error; - } - - // TODO: Could use the scanning technique from STM8 code here... - slu->ep_rep = 1 /* ep rep */ | LIBUSB_ENDPOINT_IN; - - if (desc.idProduct == STLINK_USB_PID_STLINK_NUCLEO || - desc.idProduct == STLINK_USB_PID_STLINK_32L_AUDIO || - desc.idProduct == STLINK_USB_PID_STLINK_V2_1 || - desc.idProduct == STLINK_USB_PID_STLINK_V3_USBLOADER || - desc.idProduct == STLINK_USB_PID_STLINK_V3E_PID || - desc.idProduct == STLINK_USB_PID_STLINK_V3S_PID || - desc.idProduct == STLINK_USB_PID_STLINK_V3_2VCP_PID || - desc.idProduct == STLINK_USB_PID_STLINK_V3_NO_MSD_PID) { - slu->ep_req = 1 /* ep req */ | LIBUSB_ENDPOINT_OUT; - slu->ep_trace = 2 | LIBUSB_ENDPOINT_IN; - } else { - slu->ep_req = 2 /* ep req */ | LIBUSB_ENDPOINT_OUT; - slu->ep_trace = 3 | LIBUSB_ENDPOINT_IN; - } - - slu->sg_transfer_idx = 0; - slu->cmd_len = (slu->protocoll == 1) ? STLINK_SG_SIZE : STLINK_CMD_SIZE; - - // initialize stlink version (sl->version) - stlink_version(sl); - - int mode = stlink_current_mode(sl); - if (mode == STLINK_DEV_DFU_MODE) { - DLOG("-- exit_dfu_mode\n"); - _stlink_usb_exit_dfu_mode(sl); - } - - if (connect == CONNECT_UNDER_RESET) { - // for the connect under reset only - // OpenOСD says (official documentation is not available) that - // the NRST pin must be pull down before selecting the SWD/JTAG mode - if (mode == STLINK_DEV_DEBUG_MODE) { - DLOG("-- exit_debug_mode\n"); - _stlink_usb_exit_debug_mode(sl); - } - - _stlink_usb_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_LOW); - } - - sl->freq = freq; - // set the speed before entering the mode as the chip discovery phase - // should be done at this speed too - // set the stlink clock speed (default is 1800kHz) - DLOG("JTAG/SWD freq set to %d\n", freq); - _stlink_usb_set_swdclk(sl, freq); - - stlink_target_connect(sl, connect); - return(sl); - -on_libusb_error: - stlink_close(sl); - return(NULL); - -on_error: - if (slu->libusb_ctx) { libusb_exit(slu->libusb_ctx); } - -on_malloc_error: - if (sl != NULL) { free(sl); } - if (slu != NULL) { free(slu); } - - return(NULL); -} - -static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int freq) { - stlink_t **_sldevs; - libusb_device *dev; - int i = 0; - size_t slcnt = 0; - size_t slcur = 0; - - /* Count STLINKs */ - while ((dev = devs[i++]) != NULL) { - struct libusb_device_descriptor desc; - int ret = libusb_get_device_descriptor(dev, &desc); - - if (ret < 0) { - WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); - break; - } - - if (desc.idVendor != STLINK_USB_VID_ST) { continue; } - - if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { - WLOG("skipping ST device : %#04x:%#04x)\n", desc.idVendor, desc.idProduct); - continue; - } - - slcnt++; - } - - _sldevs = calloc(slcnt, sizeof(stlink_t *)); // allocate list of pointers - - if (!_sldevs) { - *sldevs = NULL; - return(0); - } - - /* Open STLINKS and attach them to list */ - i = 0; - - while ((dev = devs[i++]) != NULL) { - struct libusb_device_descriptor desc; - int ret = libusb_get_device_descriptor(dev, &desc); - - if (ret < 0) { - WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); - break; - } - - if (!STLINK_SUPPORTED_USB_PID(desc.idProduct)) { continue; } - - struct libusb_device_handle* handle; - char serial[STLINK_SERIAL_BUFFER_SIZE] = {0, }; - - ret = libusb_open(dev, &handle); - - if (ret < 0) { - if (ret == LIBUSB_ERROR_ACCESS) { - ELOG("Could not open USB device %#06x:%#06x, access error.\n", desc.idVendor, desc.idProduct); - } else { - ELOG("Failed to open USB device %#06x:%#06x, libusb error: %d)\n", desc.idVendor, desc.idProduct, ret); - } - - break; - } - - size_t serial_len = stlink_serial(handle, &desc, serial); - - libusb_close(handle); - - if (serial_len != STLINK_SERIAL_LENGTH) { continue; } - - stlink_t *sl = stlink_open_usb(0, connect, serial, freq); - - if (!sl) { - ELOG("Failed to open USB device %#06x:%#06x\n", desc.idVendor, desc.idProduct); - continue; - } - - _sldevs[slcur++] = sl; - } - - *sldevs = _sldevs; - - return(slcur); -} - -size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq) { - libusb_device **devs; - stlink_t **sldevs; - - size_t slcnt = 0; - int r; - ssize_t cnt; - - r = libusb_init(NULL); - - if (r < 0) { return(0); } - - cnt = libusb_get_device_list(NULL, &devs); - - if (cnt < 0) { return(0); } - - slcnt = stlink_probe_usb_devs(devs, &sldevs, connect, freq); - libusb_free_device_list(devs, 1); - - libusb_exit(NULL); - - *stdevs = sldevs; - - return(slcnt); -} - -void stlink_probe_usb_free(stlink_t ***stdevs, size_t size) { - if (stdevs == NULL || *stdevs == NULL || size == 0) { return; } - - for (size_t n = 0; n < size; n++) { stlink_close((*stdevs)[n]); } - - free(*stdevs); - *stdevs = NULL; -} diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index cb6da4b8a..389c44664 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -52,7 +52,7 @@ #define ssize_t int #ifndef SSIZE_MAX -#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 1073741824 : ‭4611686018427387904‬) +#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 2147483647 : 9223372036854775807) #endif #define STDIN_FILENO 0 diff --git a/src/win32/unistd/unistd.h.bak b/src/win32/unistd/unistd.h.bak deleted file mode 100644 index 47967e45e..000000000 --- a/src/win32/unistd/unistd.h.bak +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef _UNISTD_H -#define _UNISTD_H 1 - -/* - * This file intended to serve as a drop-in replacement for unistd.h on Windows - * Please add functionality as needed. - */ - -#include -#include - -#if defined(_MSC_VER) -#pragma warning(push) -#pragma warning(disable: 4820) -#endif - -#include - -#if defined(_MSC_VER) -#pragma warning(pop) -#endif - -#include // getopt at: https://gist.github.com/ashelly/7776712 -#include // for getpid() and the exec..() family -#include // for _getcwd() and _chdir() - -#define srandom srand -#define random rand - -/* Values for the second argument to access. These may be OR'd together. */ -#define R_OK 4 // Test for read permission -#define W_OK 2 // Test for write permission -// #define X_OK 1 // execute permission - unsupported in windows -#define F_OK 0 // Test for existence - -#define access _access -#define dup2 _dup2 -#define execve _execve -#define ftruncate _chsize -#define unlink _unlink -#define fileno _fileno -#define getcwd _getcwd -#define chdir _chdir -#define isatty _isatty -#define lseek _lseek - -/* - * Read, write, and close are NOT being defined here, - * because while there are file handle specific versions for Windows, they probably don't work for sockets. - * You need to look at your app and consider whether to call e.g. closesocket(). - */ - -#define ssize_t int -#ifndef SSIZE_MAX -//#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 2147483647 : 9223372036854775807) -#define SSIZE_MAX ((sizeof(ssize_t) == 4) ? 1073741824 : ‭4611686018427387904‬) -#endif - -#define STDIN_FILENO 0 -#define STDOUT_FILENO 1 -#define STDERR_FILENO 2 -// should be in some equivalent to -typedef __int8 int8_t; -typedef __int16 int16_t; -typedef __int32 int32_t; -typedef __int64 int64_t; -typedef unsigned __int8 uint8_t; -typedef unsigned __int16 uint16_t; -typedef unsigned __int32 uint32_t; -typedef unsigned __int64 uint64_t; - -#ifndef STLINK_HAVE_UNISTD_H -int usleep(unsigned int waitTime); -#endif - -#endif // _UNISTD_H diff --git a/stlinkv1_macos_driver/install.sh b/stlinkv1_macos_driver/install.sh index 5716281a1..f9878bd46 100644 --- a/stlinkv1_macos_driver/install.sh +++ b/stlinkv1_macos_driver/install.sh @@ -2,9 +2,6 @@ ISMACOS=$(sw_vers -productVersion) case $ISMACOS in -10.14*) - KEXT="stlink_shield_10_14.kext" - ;; 10.15*) KEXT="stlink_shield_10_15.kext" ;; diff --git a/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist b/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist deleted file mode 100644 index fd424ea93..000000000 --- a/stlinkv1_macos_driver/stlink_shield_10_14.kext/Contents/Info.plist +++ /dev/null @@ -1,82 +0,0 @@ - - - - - BuildMachineOSBuild - 18G7016 - CFBundleDevelopmentRegion - English - CFBundleIdentifier - com.libusb.stlink-shield - CFBundleInfoDictionaryVersion - 6.0 - CFBundlePackageType - KEXT - CFBundleSignature - ???? - CFBundleSupportedPlatforms - - MacOSX - - CFBundleVersion - 1.0.0 - DTCompiler - com.apple.compilers.llvm.clang.1_0 - DTPlatformBuild - 11C504 - DTPlatformVersion - GM - DTSDKBuild - 19B90 - DTSDKName - macosx10.15 - DTXcode - 1130 - DTXcodeBuild - 11C504 - IOKitPersonalities - - DeviceDriver - - CFBundleIdentifier - com.apple.kpi.iokit - IOClass - IOService - IOProviderClass - IOUSBDevice - bcdDevice - 256 - idProduct - 14148 - idVendor - 1155 - - InterfaceDriver - - CFBundleIdentifier - com.apple.kpi.iokit - IOClass - IOService - IOProviderClass - IOUSBInterface - bConfigurationValue - 1 - bInterfaceNumber - 0 - idProduct - 14148 - idVendor - 1155 - - - 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zXw5i-S^Q?r*Ump=zW?jTUwH49?P1TCBVNA!H;@+`i zx9!V|hQGDJ|JEP3T>0)Be>eJqSk*4Lw$!ngQKJ{18 z*E%nJJpae{N30uAdi0KsMOPG^xZSZ!dMwa?&bo==CmRjtm(QqpuJ8I6+h2aY>GkN)Ri8Y(zj5ZJ9Y_AO+kfc7Ref*2 zbIRJevgxUH|N6+A`<~oTaNl)rKaly6!Le<}n_bs>X1~5+ - - - - files - - files2 - - rules - - ^Resources/ - - ^Resources/.*\.lproj/ - - optional - - weight - 1000 - - ^Resources/.*\.lproj/locversion.plist$ - - omit - - weight - 1100 - - ^Resources/Base\.lproj/ - - weight - 1010 - - ^version.plist$ - - - rules2 - - .*\.dSYM($|/) - - weight - 11 - - ^(.*/)?\.DS_Store$ - - omit - - weight - 2000 - - ^(Frameworks|SharedFrameworks|PlugIns|Plug-ins|XPCServices|Helpers|MacOS|Library/(Automator|Spotlight|LoginItems))/ - - nested - - weight - 10 - - ^.* - - ^Info\.plist$ - - omit - - weight - 20 - - ^PkgInfo$ - - omit - - weight - 20 - - ^Resources/ - - weight - 20 - - ^Resources/.*\.lproj/ - - optional - - weight - 1000 - - ^Resources/.*\.lproj/locversion.plist$ - - omit - - weight - 1100 - - ^Resources/Base\.lproj/ - - weight - 1010 - - ^[^/]+$ - - nested - - weight - 10 - - ^embedded\.provisionprofile$ - - weight - 20 - - ^version\.plist$ - - weight - 20 - - - - diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj index 4f2b80254..373600c64 100644 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj +++ b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj @@ -8,7 +8,6 @@ /* Begin PBXFileReference section */ 8CD33C31149BB80D0033D618 /* Info.plist */ = {isa = PBXFileReference; lastKnownFileType = text.plist.xml; path = Info.plist; sourceTree = ""; }; - 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = stlink_shield_10_14.kext; sourceTree = BUILT_PRODUCTS_DIR; }; 8F90850924786F39009109AD /* stlink_shield_10_15.kext */ = {isa = PBXFileReference; explicitFileType = wrapper.cfbundle; includeInIndex = 0; path = stlink_shield_10_15.kext; sourceTree = BUILT_PRODUCTS_DIR; }; /* End PBXFileReference section */ @@ -34,7 +33,6 @@ 19C28FB6FE9D52B211CA2CBB /* Products */ = { isa = PBXGroup; children = ( - 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */, 8F90850924786F39009109AD /* stlink_shield_10_15.kext */, ); name = Products; @@ -60,26 +58,6 @@ /* End PBXHeadersBuildPhase section */ /* Begin PBXNativeTarget section */ - 8F9084F324786F0F009109AD /* stlink_shield_10_14 */ = { - isa = PBXNativeTarget; - buildConfigurationList = 8F9084FA24786F0F009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_14" */; - buildPhases = ( - 8F9084F424786F0F009109AD /* ShellScript */, - 8F9084F524786F0F009109AD /* Headers */, - 8F9084F624786F0F009109AD /* Resources */, - 8F9084F824786F0F009109AD /* Sources */, - 8F9084F924786F0F009109AD /* ShellScript */, - ); - buildRules = ( - ); - dependencies = ( - ); - name = stlink_shield_10_14; - productInstallPath = "$(SYSTEM_LIBRARY_DIR)/Extensions"; - productName = NanosMouse; - productReference = 8F9084FD24786F0F009109AD /* stlink_shield_10_14.kext */; - productType = "com.apple.product-type.kernel-extension.iokit"; - }; 8F9084FF24786F39009109AD /* stlink_shield_10_15 */ = { isa = PBXNativeTarget; buildConfigurationList = 8F90850624786F39009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_15" */; @@ -120,7 +98,6 @@ projectDirPath = ""; projectRoot = ""; targets = ( - 8F9084F324786F0F009109AD /* stlink_shield_10_14 */, 8F9084FF24786F39009109AD /* stlink_shield_10_15 */, ); }; @@ -458,24 +435,6 @@ }; name = Release; }; - 8F9084FB24786F0F009109AD /* Debug */ = { - isa = XCBuildConfiguration; - buildSettings = { - CODE_SIGN_IDENTITY = "-"; - MACOSX_DEPLOYMENT_TARGET = 10.14; - PRODUCT_NAME = "$(TARGET_NAME)"; - }; - name = Debug; - }; - 8F9084FC24786F0F009109AD /* Release */ = { - isa = XCBuildConfiguration; - buildSettings = { - CODE_SIGN_IDENTITY = "-"; - MACOSX_DEPLOYMENT_TARGET = 10.14; - PRODUCT_NAME = "$(TARGET_NAME)"; - }; - name = Release; - }; 8F90850724786F39009109AD /* Debug */ = { isa = XCBuildConfiguration; buildSettings = { @@ -506,15 +465,6 @@ defaultConfigurationIsVisible = 0; defaultConfigurationName = Release; }; - 8F9084FA24786F0F009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_14" */ = { - isa = XCConfigurationList; - buildConfigurations = ( - 8F9084FB24786F0F009109AD /* Debug */, - 8F9084FC24786F0F009109AD /* Release */, - ); - defaultConfigurationIsVisible = 0; - defaultConfigurationName = Release; - }; 8F90850624786F39009109AD /* Build configuration list for PBXNativeTarget "stlink_shield_10_15" */ = { isa = XCConfigurationList; buildConfigurations = ( From cf6bdbfe4ba9fa3dd4ea58b81a3d290a39c2a55a Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Mon, 31 Jan 2022 13:01:06 +0200 Subject: [PATCH 1304/1435] set C standart through cmake variables, remove redundant -Ox options --- CMakeLists.txt | 4 ++++ cmake/modules/c_flags.cmake | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index abfc0be47..52c00ea29 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -9,6 +9,10 @@ set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib) set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin) +set(CMAKE_C_STANDARD 11) +set(CMAKE_C_STANDARD_REQUIRED ON) +set(CMAKE_C_EXTENSIONS ON) + ### # General project settings diff --git a/cmake/modules/c_flags.cmake b/cmake/modules/c_flags.cmake index 5ed0c4d7d..44052bba8 100644 --- a/cmake/modules/c_flags.cmake +++ b/cmake/modules/c_flags.cmake @@ -17,8 +17,6 @@ function(add_cflag_if_supported flag) endif () endfunction() -add_cflag_if_supported("-std=gnu11") -add_cflag_if_supported("-std=gnu18") add_cflag_if_supported("-Wall") add_cflag_if_supported("-Wextra") add_cflag_if_supported("-Wshadow") @@ -47,8 +45,6 @@ endif () if (${CMAKE_BUILD_TYPE} MATCHES "Debug") add_cflag_if_supported("-ggdb") - add_cflag_if_supported("-O0") else () - add_cflag_if_supported("-O2") add_cflag_if_supported("-Werror") endif () From 978462d048bbb74842c75dcc0539e8c28da3ebb1 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 4 Feb 2022 21:53:00 +0100 Subject: [PATCH 1305/1435] Updated libusb to v1.0.25 (macOS + Windows) --- cmake/modules/Findlibusb.cmake | 2 +- doc/version_support.md | 4 ++-- src/stlink-lib/libusb_settings.h | 9 +++++---- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index bc04f848d..de3712eca 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -72,7 +72,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to if (WIN32 AND NOT EXISTS "/etc/debian_version") # Skip this for Debian... # Preparations for installing libusb library - set(LIBUSB_WIN_VERSION 1.0.24) # set libusb version + set(LIBUSB_WIN_VERSION 1.0.25) # set libusb version set(LIBUSB_WIN_ARCHIVE libusb-${LIBUSB_WIN_VERSION}.7z) if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) diff --git a/doc/version_support.md b/doc/version_support.md index d7ba5c102..01d9dddb1 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -14,8 +14,8 @@ Up on compiling c-make will **automatically** download and install the latest co | Package Repository | libusb | cmake | gtk-3-dev | Supported macOS versions | | ------------------ | ------ | ------ | ------------------ | ------------------------ | -| homebrew | 1.0.24 | 3.22.1 | 3.24.30
      gtk+3 | **10.10 - 12.x** | -| MacPorts | 1.0.24 | 3.22.1 | 3.24.31
      gtk3 | **10.4 - 12.x** | +| homebrew | 1.0.25 | 3.22.1 | 3.24.30
      gtk+3 | **10.10 - 12.x** | +| MacPorts | 1.0.25 | 3.22.1 | 3.24.31
      gtk3 | **10.4 - 12.x** | NOTE: In order to use a STLINK/V1 programmer on macOS, version 10.15 is required. diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index c7562e290..2a595238a 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -18,6 +18,7 @@ * v1.0.22 | 0x01000106 * v1.0.23 | 0x01000107 * v1.0.24 | 0x01000108 + * v1.0.25 | 0x01000109 */ #if defined (__FreeBSD__) @@ -31,13 +32,13 @@ #if defined (__FreeBSD__) #define MINIMAL_API_VERSION 0x01000102 // v1.0.16 #elif defined (__OpenBSD__) - #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 + #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 #elif defined (__linux__) - #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 + #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 #elif defined (__APPLE__) - #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 + #define MINIMAL_API_VERSION 0x01000109 // v1.0.25 #elif defined (_WIN32) - #define MINIMAL_API_VERSION 0x01000104 // v1.0.20 + #define MINIMAL_API_VERSION 0x01000109 // v1.0.25 #endif #if (LIBUSB_API_VERSION < MINIMAL_API_VERSION) From 468b1d2daa853b975c33ab69876c486734f2c6a7 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 4 Feb 2022 22:24:42 +0100 Subject: [PATCH 1306/1435] [libusb] Added Security framework for macOS --- CMakeLists.txt | 6 ++++-- cmake/packaging/cpack_config.cmake | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 52c00ea29..67f76ec08 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -209,7 +209,8 @@ if (APPLE) # ... with Apple macOS libraries find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) find_library(IOKit IOKit) - target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB} ${ObjC} ${CoreFoundation} ${IOKit}) + find_library(Security Security) + target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB} ${ObjC} ${CoreFoundation} ${IOKit} ${Security}) elseif (WIN32) # ... with Windows libraries target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB} wsock32 ws2_32) else () @@ -251,7 +252,8 @@ if (APPLE) # ... with Apple macOS libraries find_library(ObjC objc) find_library(CoreFoundation CoreFoundation) find_library(IOKit IOKit) - target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB} ${ObjC} ${CoreFoundation} ${IOKit}) + find_library(Security Security) + target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB} ${ObjC} ${CoreFoundation} ${IOKit} ${Security}) elseif (WIN32) # ... with Windows libraries target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB} wsock32 ws2_32) else () diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index 587ff5fb5..a4f1ae073 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -17,7 +17,7 @@ set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist") if (APPLE) # macOS set(CPACK_GENERATOR "ZIP") - set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-macosx-amd64") + set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-macos-amd64") set(CPACK_INSTALL_PREFIX "") elseif (WIN32 AND (NOT EXISTS "/etc/debian_version")) # Windows From 77fff346aa9d075e7fd01668d8418818f9c262ac Mon Sep 17 00:00:00 2001 From: Alex Klimaj Date: Tue, 15 Feb 2022 22:28:19 -0700 Subject: [PATCH 1307/1435] Add writing and reading STM32WL option bytes --- config/chips/WLx5.chip | 2 +- inc/stm32flash.h | 8 +-- src/option_bytes.c | 108 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 114 insertions(+), 4 deletions(-) diff --git a/config/chips/WLx5.chip b/config/chips/WLx5.chip index 5bc9d90dc..8337b0aee 100644 --- a/config/chips/WLx5.chip +++ b/config/chips/WLx5.chip @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB sram_size 0x10000 // 64 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB -option_base 0x1fffc000 +option_base 0x1fff7800 option_size 0x10 // 16 B flags swo diff --git a/inc/stm32flash.h b/inc/stm32flash.h index c28d67c28..7e96d3f70 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -162,9 +162,11 @@ #define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) // WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ +#define STM32WB_FLASH_CR_STRT (16) /* Start */ +#define STM32WB_FLASH_CR_OPTSTRT (17) /* Start writing option bytes */ +#define STM32WB_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ +#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ // WB Flash status register. #define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ #define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ diff --git a/src/option_bytes.c b/src/option_bytes.c index f5d8c00a0..c1a418232 100644 --- a/src/option_bytes.c +++ b/src/option_bytes.c @@ -472,6 +472,57 @@ static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, return 0; } +/** + * Write option bytes + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes to write + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_wb(stlink_t *sl, uint8_t *base, + stm32_addr_t addr, uint32_t len) { + /* Write options bytes */ + uint32_t val; + int ret = 0; + (void)len; + uint32_t data; + + clear_flash_error(sl); + + while (len != 0) { + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, addr, data); + wait_flash_busy(sl); + + if ((ret = check_flash_error(sl))) { + break; + } + + len -= 4; + addr += 4; + base += 4; + } + + // Set Options Start bit + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + val |= (1 << STM32WB_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + + // Reload options + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + val |= (1 << STM32WB_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + + return (ret); +} + /** * Write option bytes * @param sl @@ -536,6 +587,9 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, case STM32_FLASH_TYPE_H7: ret = stlink_write_option_bytes_h7(sl, base, addr, len); break; + case STM32_FLASH_TYPE_WB_WL: + ret = stlink_write_option_bytes_wb(sl, base, addr, len); + break; default: ELOG("Option bytes writing is currently not implemented for connected " "chip\n"); @@ -715,6 +769,42 @@ stlink_write_option_control_register_f7(stlink_t *sl, return ret; } +/** + * Write option bytes + * @param sl + * @param option_byte value to write + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_control_register_wb(stlink_t *sl, + uint32_t option_control_register) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", + option_control_register, STM32WB_FLASH_OPTR); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, STM32WB_FLASH_OPTR, option_control_register); + + wait_flash_busy(sl); + + // Set Options Start bit + uint32_t val = (1 << STM32WB_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, + STM32WB_FLASH_OPTR); + + return ret; +} + /** * Write option bytes * @param sl @@ -746,6 +836,10 @@ int stlink_write_option_control_register32(stlink_t *sl, case STM32_FLASH_TYPE_F7: ret = stlink_write_option_control_register_f7(sl, option_control_register); break; + case STM32_FLASH_TYPE_WB_WL: + ret = + stlink_write_option_control_register_wb(sl, option_control_register); + break; default: ELOG("Option control register writing is currently not implemented for " "connected chip\n"); @@ -1003,6 +1097,18 @@ int stlink_read_option_control_register_f0(stlink_t *sl, return stlink_read_debug32(sl, FLASH_OBR, option_byte); } +/** + * Read option bytes + * @param sl + * @param option_byte value to read + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_wb(stlink_t *sl, + uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", STM32WB_FLASH_OPTR); + return stlink_read_debug32(sl, STM32WB_FLASH_OPTR, option_byte); +} + /** * Read option bytes * @param sl @@ -1021,6 +1127,8 @@ int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { return stlink_read_option_control_register_f0(sl, option_byte); case STM32_FLASH_TYPE_F7: return stlink_read_option_control_register_f7(sl, option_byte); + case STM32_FLASH_TYPE_WB_WL: + return stlink_read_option_control_register_wb(sl, option_byte); default: return -1; } From a6939cb9d491d8e3aa2aa54d0e35fb72519b7d8f Mon Sep 17 00:00:00 2001 From: Lucas Sinn Date: Tue, 8 Mar 2022 11:21:23 +0100 Subject: [PATCH 1308/1435] init chipids only when actually interacting with device --- src/st-info/info.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/st-info/info.c b/src/st-info/info.c index 618046ddd..a939a03cf 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -29,7 +29,6 @@ static void stlink_print_version(stlink_t *sl) { } static void stlink_print_info(stlink_t *sl) { - const struct stlink_chipid_params *params = NULL; if (!sl) { return; } @@ -38,9 +37,6 @@ static void stlink_print_info(stlink_t *sl) { printf(" flash: %u (pagesize: %u)\n", (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); printf(" sram: %u\n", (uint32_t)sl->sram_size); printf(" chipid: 0x%.3x\n", sl->chip_id); - - params = stlink_chipid_get_params(sl->chip_id); - if (params) { printf(" dev-type: %s\n", params->dev_type); } } static void stlink_probe(enum connect_type connect, int freq) { @@ -69,6 +65,8 @@ static int print_data(int ac, char **av) { return(0); } + init_chipids(ETC_STLINK_DIR); + for (int i=2; i Date: Tue, 8 Mar 2022 11:24:06 +0100 Subject: [PATCH 1309/1435] optimized processing of chipidfile 'moved chip dump to stdout instead of stderr' 'closing open fd after file is fully read' 'reduced file read buffer size' --- src/stlink-lib/chipid.c | 44 ++++++++++++++++++----------------------- 1 file changed, 19 insertions(+), 25 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 06e8571aa..8fcaa4100 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -30,8 +30,8 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { struct stlink_chipid_params *params = NULL; for (params = devicelist; params != NULL; params = params->next) if (params->chip_id == chip_id) { - fprintf(stderr, "\ndetected chip_id parametres\n\n"); - dump_a_chip(stderr, params); + fprintf(stdout, "\ndetected chip_id parametres\n\n"); + dump_a_chip(stdout, params); break; } @@ -40,7 +40,7 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { void process_chipfile(char *fname) { FILE *fp; - char *p, *pp, buf[1025]; + char *p, buf[128]; char word[64], value[64]; struct stlink_chipid_params *ts; int nc; @@ -55,29 +55,23 @@ void process_chipfile(char *fname) { ts = calloc(sizeof(struct stlink_chipid_params), 1); - while (fgets(buf, 1024, fp) != NULL) { - for (p = buf; isspace (*p); p++); + while (fgets(buf, sizeof(buf), fp) != NULL) { - if (!*p) { - continue; // we hit end-of-line with only whitespace - } - - if (*p == '#') { + if(strncmp(buf, "#", strlen("#")) == 0) continue; // ignore comments - } - sscanf(p, "%s %s", word, value); + sscanf(buf, "%s %s", word, value); if (strcmp (word, "dev_type") == 0) { // ts->dev_type = strdup (value); - buf[strlen(p) - 1] = 0; // chomp newline - sscanf(p, "%*s %n", &nc); - ts->dev_type = strdup(p + nc); + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + ts->dev_type = strdup(buf + nc); } else if (strcmp(word, "ref_manual_id") == 0) { // ts->ref_manual_id = strdup (value); - buf[strlen(p) - 1] = 0; // chomp newline - sscanf(p, "%*s %n", &nc); - ts->ref_manual_id = strdup(p + nc); + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + ts->ref_manual_id = strdup(buf + nc); } else if (strcmp(word, "chip_id") == 0) { if (sscanf(value, "%i", &ts->chip_id) < 1) { fprintf(stderr, "Failed to parse chip-id\n"); @@ -138,18 +132,18 @@ void process_chipfile(char *fname) { fprintf(stderr, "Failed to parse option size\n"); } } else if (strcmp(word, "flags") == 0) { - pp = strtok (p, " \t\n"); + p = strtok (buf, " \t\n"); - while ((pp = strtok (NULL, " \t\n"))) { - if (strcmp(pp, "none") == 0) { + while ((p = strtok (NULL, " \t\n"))) { + if (strcmp(p, "none") == 0) { // NOP - } else if (strcmp(pp, "dualbank") == 0) { + } else if (strcmp(p, "dualbank") == 0) { ts->flags |= CHIP_F_HAS_DUAL_BANK; - } else if (strcmp(pp, "swo") == 0) { + } else if (strcmp(p, "swo") == 0) { ts->flags |= CHIP_F_HAS_SWO_TRACING; } else { fprintf(stderr, "Unknown flags word in %s: '%s'\n", - fname, pp); + fname, p); } } @@ -159,7 +153,7 @@ void process_chipfile(char *fname) { fname, word); } } - + fclose(fp); ts->next = devicelist; devicelist = ts; } From 564434297cfadcea44eb3c275bc4d95c5f210d1d Mon Sep 17 00:00:00 2001 From: Lucas Sinn Date: Mon, 14 Mar 2022 12:47:23 +0100 Subject: [PATCH 1310/1435] readded get chipid parameters on print info --- src/st-info/info.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/st-info/info.c b/src/st-info/info.c index a939a03cf..d02653bc5 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -29,7 +29,7 @@ static void stlink_print_version(stlink_t *sl) { } static void stlink_print_info(stlink_t *sl) { - + const struct stlink_chipid_params *params = NULL; if (!sl) { return; } printf(" version: "); stlink_print_version(sl); @@ -37,6 +37,9 @@ static void stlink_print_info(stlink_t *sl) { printf(" flash: %u (pagesize: %u)\n", (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); printf(" sram: %u\n", (uint32_t)sl->sram_size); printf(" chipid: 0x%.3x\n", sl->chip_id); + + params = stlink_chipid_get_params(sl->chip_id); + if (params) { printf(" dev-type: %s\n", params->dev_type); } } static void stlink_probe(enum connect_type connect, int freq) { From a99a626e6948b684515fe068e7b01b53b74c4678 Mon Sep 17 00:00:00 2001 From: Lucas Sinn Date: Mon, 14 Mar 2022 12:48:47 +0100 Subject: [PATCH 1311/1435] moved dump_a_chip to debug output, minor code style fix --- src/stlink-lib/chipid.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 8fcaa4100..02b610bb1 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -10,28 +10,28 @@ static struct stlink_chipid_params *devicelist; -void dump_a_chip (FILE *fp, struct stlink_chipid_params *dev) { - fprintf(fp, "# Device Type: %s\n", dev->dev_type); - fprintf(fp, "# Reference Manual: RM%s\n", dev->ref_manual_id); - fprintf(fp, "#\n"); - fprintf(fp, "chip_id 0x%x\n", dev->chip_id); - fprintf(fp, "flash_type %d\n", dev->flash_type); - fprintf(fp, "flash_size_reg 0x%x\n", dev->flash_size_reg); - fprintf(fp, "flash_pagesize 0x%x\n", dev->flash_pagesize); - fprintf(fp, "sram_size 0x%x\n", dev->sram_size); - fprintf(fp, "bootrom_base 0x%x\n", dev->bootrom_base); - fprintf(fp, "bootrom_size 0x%x\n", dev->bootrom_size); - fprintf(fp, "option_base 0x%x\n", dev->option_base); - fprintf(fp, "option_size 0x%x\n", dev->option_size); - fprintf(fp, "flags %d\n\n", dev->flags); +void dump_a_chip (struct stlink_chipid_params *dev) { + DLOG("# Device Type: %s\n", dev->dev_type); + DLOG("# Reference Manual: RM%s\n", dev->ref_manual_id); + DLOG("#\n"); + DLOG("chip_id 0x%x\n", dev->chip_id); + DLOG("flash_type %d\n", dev->flash_type); + DLOG("flash_size_reg 0x%x\n", dev->flash_size_reg); + DLOG("flash_pagesize 0x%x\n", dev->flash_pagesize); + DLOG("sram_size 0x%x\n", dev->sram_size); + DLOG("bootrom_base 0x%x\n", dev->bootrom_base); + DLOG("bootrom_size 0x%x\n", dev->bootrom_size); + DLOG("option_base 0x%x\n", dev->option_base); + DLOG("option_size 0x%x\n", dev->option_size); + DLOG("flags %d\n\n", dev->flags); } struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { struct stlink_chipid_params *params = NULL; for (params = devicelist; params != NULL; params = params->next) if (params->chip_id == chip_id) { - fprintf(stdout, "\ndetected chip_id parametres\n\n"); - dump_a_chip(stdout, params); + DLOG("detected chip_id parameters\n\n"); + dump_a_chip(params); break; } @@ -57,7 +57,7 @@ void process_chipfile(char *fname) { while (fgets(buf, sizeof(buf), fp) != NULL) { - if(strncmp(buf, "#", strlen("#")) == 0) + if (strncmp(buf, "#", strlen("#")) == 0) continue; // ignore comments sscanf(buf, "%s %s", word, value); From 86a37544f1c3e98c36432dd8df85c99536ea9acf Mon Sep 17 00:00:00 2001 From: Lucas Sinn Date: Mon, 14 Mar 2022 13:00:07 +0100 Subject: [PATCH 1312/1435] added option_base, option_size for F401xD_xE --- config/chips/F401xD_xE.chip | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip index 39748a604..f817175f4 100644 --- a/config/chips/F401xD_xE.chip +++ b/config/chips/F401xD_xE.chip @@ -9,6 +9,6 @@ flash_pagesize 0x4000 // 16 KB sram_size 0x18000 // 96 KB bootrom_base 0x1fff0000 bootrom_size 0x7800 // 30 KB -option_base 0x0 -option_size 0x0 +option_base 0x40023C14 +option_size 0x4 flags swo From 3b328b26bd5eb0e07f78b8ba48e10c2581a1239a Mon Sep 17 00:00:00 2001 From: Lucas Sinn Date: Wed, 16 Mar 2022 09:31:19 +0100 Subject: [PATCH 1313/1435] adding additional check if .chip files contain empty lines --- src/stlink-lib/chipid.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 02b610bb1..fe60ebf64 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -60,6 +60,10 @@ void process_chipfile(char *fname) { if (strncmp(buf, "#", strlen("#")) == 0) continue; // ignore comments + if ((strncmp(buf, "\n", strlen("\n")) == 0) || + (strncmp(buf, " ", strlen(" ")) == 0)) + continue; // ignore empty lines + sscanf(buf, "%s %s", word, value); if (strcmp (word, "dev_type") == 0) { From 8dfb7973e712ab2ed982cd241f9240ac9e432da7 Mon Sep 17 00:00:00 2001 From: Lucas Sinn Date: Mon, 28 Mar 2022 09:18:30 +0200 Subject: [PATCH 1314/1435] made chipfile buffer size bigger --- src/stlink-lib/chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index fe60ebf64..e36c150a6 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -40,7 +40,7 @@ struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { void process_chipfile(char *fname) { FILE *fp; - char *p, buf[128]; + char *p, buf[256]; char word[64], value[64]; struct stlink_chipid_params *ts; int nc; From a5696f2668105aa7ae3f61f77193423617c25099 Mon Sep 17 00:00:00 2001 From: simon-wh Date: Fri, 20 May 2022 11:01:32 +0200 Subject: [PATCH 1315/1435] Define option byte properties for F1xx_XLD --- config/chips/F1xx_XLD.chip | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/config/chips/F1xx_XLD.chip b/config/chips/F1xx_XLD.chip index 622bd9d02..4f8c9ee27 100644 --- a/config/chips/F1xx_XLD.chip +++ b/config/chips/F1xx_XLD.chip @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB sram_size 0x18000 // 96 KB bootrom_base 0x1fffe000 bootrom_size 0x1800 // 6 KB -option_base 0x0 -option_size 0x0 +option_base 0x1ffff800 // STM32_F0_OPTION_BYTES_BASE +option_size 0x10 // 16 B flags swo From 9a7805ede51839cb8d76074c595997045c5c1e95 Mon Sep 17 00:00:00 2001 From: simon-wh Date: Fri, 20 May 2022 11:02:50 +0200 Subject: [PATCH 1316/1435] Include GD32F303CGT6 in devices_boards.md --- doc/devices_boards.md | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 51b9a0739..1a5099b72 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -90,6 +90,7 @@ Tested non-official ST boards [incl. STLINK programmers]: | Product-Code | Chip-ID | STLINK
      Programmer | Boards | | ------------ | ------- | ---------------------- | ---------------------------------- | | GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | +| GD32F303CGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | ## STM32F4 / ARM Cortex M4F From f8d1603be40ddf6ed0701061f4aef8bdcc227070 Mon Sep 17 00:00:00 2001 From: John Hall Date: Wed, 8 Jun 2022 13:48:13 -0700 Subject: [PATCH 1317/1435] Updating to allow frequency units for clock and trace flags. Making sure trace frequency is not less than 1/5 of the system frequency. Showing minimum and maximum available trace speed when out of range. Making sure MCU is stopped after reset to avoid missing data. Making sure variables are intiallized. --- src/st-trace/trace.c | 84 ++++++++++++++++++++++++++++++++++---------- 1 file changed, 65 insertions(+), 19 deletions(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 28a585071..8c36ae6f0 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -98,13 +98,52 @@ static void usage(void) { puts(" -V, --version Print this version"); puts(" -vXX, --verbose=XX Specify a specific verbosity level (0..99)"); puts(" -v, --verbose Specify a generally verbose logging"); - puts(" -cXX, --clock=XX Specify the core frequency in MHz"); - puts(" -tXX, --trace=XX Specify the trace frequency in Hz"); + puts(" -cXX, --clock=XX Specify the core frequency, optionally followed by"); + puts(" k=kHz, m=MHz, or g=GHz (eg. --clock=180m)"); + puts(" -tXX, --trace=XX Specify the trace frequency, optionally followed by"); + puts(" k=kHz, m=MHz, or g=GHz (eg. --trace=2m)"); puts(" -n, --no-reset Do not reset board on connection"); puts(" -sXX, --serial=XX Use a specific serial number"); puts(" -f, --force Ignore most initialization errors"); } +static bool parse_frequency(char* text, uint32_t* result) +{ + if (text == NULL) { + ELOG("Invalid frequency.\n"); + return false; + } + + char* suffix = text; + double value = strtod(text, &suffix); + + if (value == 0.0) { + ELOG("Invalid frequency.\n"); + return false; + } + + double scale = 1.0; + if (*suffix == 'k') + scale = 1000; + else if (*suffix == 'm') + scale = 1000000; + else if (*suffix == 'g') + scale = 1000000000; + else if (*suffix != '\0') { + ELOG("Unknown frequency suffix '%s'.\n", suffix); + return false; + } + + value *= scale; + if (value <= 0 || value > 0xFFFFFFFFul) { + ELOG("Frequency is out of valid range.\n"); + return false; + } + + *result = (uint32_t)value; + return true; +} + bool parse_options(int argc, char **argv, st_settings_t *settings) { static struct option long_options[] = { @@ -150,10 +189,12 @@ bool parse_options(int argc, char **argv, st_settings_t *settings) { ugly_init(settings->logging_level); break; case 'c': - settings->core_frequency = atoi(optarg) * 1000000; + if (!parse_frequency(optarg, &settings->core_frequency)) + error = true; break; case 't': - settings->trace_frequency = atoi(optarg); + if (!parse_frequency(optarg, &settings->trace_frequency)) + error = true; break; case 'n': settings->reset_board = false; @@ -200,8 +241,7 @@ static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, if (!settings->force) return false; } - - if (settings->reset_board && stlink_reset(stlink, RESET_AUTO)) { + if (settings->reset_board && stlink_reset(stlink, RESET_SOFT_AND_HALT)) { ELOG("Unable to reset device\n"); if (!settings->force) return false; @@ -268,13 +308,12 @@ static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, STLINK_REG_DWT_CTRL_CYCCNT_ENA); stlink_write_debug32(stlink, STLINK_REG_DEMCR, STLINK_REG_DEMCR_TRCENA); - uint32_t prescaler; - stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR_MAX, &prescaler); + uint32_t prescaler = 0; + stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR, &prescaler); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; - uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; - ILOG("Trace Port Interface configured to expect a %d MHz system clock.\n", - system_clock_speed_mhz); + ILOG("Trace Port Interface configured to expect a %d Hz system clock.\n", + system_clock_speed); } else { WLOG("Trace Port Interface not configured. Specify the system clock with " "a --clock=XX command\n"); @@ -440,13 +479,12 @@ static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, } if (error_no_data || error_low_data || error_bad_data) { - uint32_t prescaler; + uint32_t prescaler = 0; stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR, &prescaler); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; - uint32_t system_clock_speed_mhz = (system_clock_speed + 500000) / 1000000; - WLOG("Verify the system clock is running at %d MHz.\n", - system_clock_speed_mhz); + WLOG("Verify the system clock is running at %d Hz.\n", + system_clock_speed); } WLOG("Try specifying the system clock with the --clock=XX command line " "option.\n"); @@ -511,7 +549,6 @@ int main(int argc, char **argv) { } init_chipids (ETC_STLINK_DIR); - DLOG("show_help = %s\n", settings.show_help ? "true" : "false"); DLOG("show_version = %s\n", settings.show_version ? "true" : "false"); DLOG("logging_level = %d\n", settings.logging_level); @@ -563,9 +600,18 @@ int main(int argc, char **argv) { uint32_t trace_frequency = settings.trace_frequency; if (!trace_frequency) trace_frequency = STLINK_DEFAULT_TRACE_FREQUENCY; - if (trace_frequency > stlink->max_trace_freq) { - ELOG("Invalid trace frequency %d (max %d)\n", trace_frequency, - stlink->max_trace_freq); + uint32_t max_trace_freq = stlink->max_trace_freq; + uint32_t min_trace_freq = 0; + + if (settings.core_frequency != 0) { + if (max_trace_freq > settings.core_frequency / 5) + max_trace_freq = settings.core_frequency / 5; + min_trace_freq = settings.core_frequency / (STLINK_REG_TPI_ACPR_MAX + 1); + } + if (trace_frequency > max_trace_freq || + trace_frequency < min_trace_freq) { + ELOG("Invalid trace frequency %d (min %d max %d)\n", trace_frequency, + min_trace_freq, max_trace_freq); if (!settings.force) return APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY; } From 0729558f2c9a5354b3d259cf887b9801678282b0 Mon Sep 17 00:00:00 2001 From: bauen1 Date: Mon, 9 May 2022 22:10:54 +0200 Subject: [PATCH 1318/1435] L4Rx: fix option byte address --- config/chips/L4Rx.chip | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index b5c2d0d80..428a0c21e 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -9,6 +9,6 @@ flash_pagesize 0x1000 // 4 KB sram_size 0xa0000 // 640 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB -option_base 0x0 -option_size 0x0 +option_base 0x1ff00000 +option_size 0x4 // 4 B flags swo From 54e82342f9b4f2e504fce501e30ab10045e8a166 Mon Sep 17 00:00:00 2001 From: simon-wh Date: Thu, 30 Jun 2022 17:55:27 +0100 Subject: [PATCH 1319/1435] Fix writing to 'BANK_2' in flash type F1_XL --- src/flashloader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/flashloader.c b/src/flashloader.c index e4c7d7200..5592db477 100644 --- a/src/flashloader.c +++ b/src/flashloader.c @@ -94,7 +94,7 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; x |= (1 << FLASH_H7_CR_PG); } else { - cr_reg = FLASH_CR; + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; x = (1 << FLASH_CR_PG); } From 8956051ed5fc8ea124f48259e935aa90d9d95108 Mon Sep 17 00:00:00 2001 From: Jeroen de Bruijn Date: Thu, 14 Jul 2022 11:57:01 +0200 Subject: [PATCH 1320/1435] add `make install` to the MacOS building instructions This is required to get the `chips` directory in place. References #1237. --- doc/compiling.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/doc/compiling.md b/doc/compiling.md index 0931c278a..ec98fa5d5 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -215,7 +215,8 @@ To do this with only one simple command, type: 1. Change into the project source directory: `cd stlink` 2. Run `make clean` to clean remnants of any previous builds. 3. Run `make release` to create the _Release_ target -4. Run `make debug` to create the _Debug_ target (_optional_)
      +4. Run `make install` to full install the package with complete system integration. This might require sudo permissions. +5. Run `make debug` to create the _Debug_ target (_optional_)
      The debug target is only necessary in order to modify the sources and to run under a debugger. ## Build options From 9f0521016c415e58ce9bd27fd865b33d84aca980 Mon Sep 17 00:00:00 2001 From: Jeroen de Bruijn Date: Thu, 14 Jul 2022 16:34:51 +0200 Subject: [PATCH 1321/1435] add optional installation folder for macOS to compiling documentation --- doc/compiling.md | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index ec98fa5d5..ec9d572ff 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -120,12 +120,12 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma 1. Change into the project source directory: `cd stlink` 2. Run `make clean` -- required by some linux variants. 3. Run `make release` to create the _Release_ target -4. Run `make install` to full install the package with complete system integration +4. Run `make install` to full install the package with complete system integration. This might require sudo permissions. 5. Run `make debug` to create the _Debug_ target (_optional_)
      The debug target is only necessary in order to modify the sources and to run under a debugger. 6. Run `make package`to build a Debian Package. The generated packages can be found in the subdirectory `./build/dist`. -As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. +> **Note** As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. #### Removal: @@ -219,6 +219,8 @@ To do this with only one simple command, type: 5. Run `make debug` to create the _Debug_ target (_optional_)
      The debug target is only necessary in order to modify the sources and to run under a debugger. +> **Note** As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. + ## Build options ### Build using a different directory for shared libs From 87b21219a295e5080dcaf9e4b9ca38866eb14b5c Mon Sep 17 00:00:00 2001 From: Jeroen de Bruijn Date: Fri, 15 Jul 2022 08:16:57 +0200 Subject: [PATCH 1322/1435] remove note block from compiling docs note --- doc/compiling.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index ec9d572ff..a82941e8a 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -125,7 +125,7 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma The debug target is only necessary in order to modify the sources and to run under a debugger. 6. Run `make package`to build a Debian Package. The generated packages can be found in the subdirectory `./build/dist`. -> **Note** As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. +As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. #### Removal: @@ -219,7 +219,7 @@ To do this with only one simple command, type: 5. Run `make debug` to create the _Debug_ target (_optional_)
      The debug target is only necessary in order to modify the sources and to run under a debugger. -> **Note** As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. +As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. ## Build options From 0e734a541b96dbf92be7b12c35cc7b2ce5e46569 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Mon, 22 Aug 2022 10:47:05 +0200 Subject: [PATCH 1323/1435] src/common_flash: fix flash regs addr for STM32L152RET6 --- src/common_flash.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/common_flash.c b/src/common_flash.c index e2a9ebbc3..72a36a288 100644 --- a/src/common_flash.c +++ b/src/common_flash.c @@ -21,6 +21,7 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { case STM32_CHIPID_L1_MD: case STM32_CHIPID_L1_MD_PLUS: case STM32_CHIPID_L1_MD_PLUS_HD: + case STM32_CHIPID_L152_RE: return (STM32L_FLASH_REGS_ADDR); default: From c94b74e56a1522766937440c51a89a2cd968aeb2 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Thu, 25 Aug 2022 19:18:31 +0200 Subject: [PATCH 1324/1435] stm32l1: fix flash, dbgmcu and rcc registers --- inc/stm32.h | 7 +++++++ inc/stm32flash.h | 4 ++++ src/common.c | 12 +++++++++--- src/common_flash.c | 15 ++++++++++++--- src/flashloader.c | 9 +++++++-- 5 files changed, 39 insertions(+), 8 deletions(-) diff --git a/inc/stm32.h b/inc/stm32.h index 473f65a56..2d533eca2 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -167,6 +167,10 @@ enum stm32_chipids { #define STM32L0_DBGMCU_APB1_FZ_WWDG_STOP 11 #define STM32L0_DBGMCU_APB1_FZ_IWDG_STOP 12 +#define STM32L1_DBGMCU_APB1_FZ 0xE0042008 +#define STM32L1_DBGMCU_APB1_FZ_WWDG_STOP 11 +#define STM32L1_DBGMCU_APB1_FZ_IWDG_STOP 12 + #define STM32H7_DBGMCU_APB1HFZ 0x5C001054 #define STM32H7_DBGMCU_APB1HFZ_IWDG_STOP 18 @@ -189,6 +193,9 @@ enum stm32_chipids { #define STM32L0_RCC_AHBENR 0x40021030 #define STM32L0_RCC_DMAEN 0x00000001 // DMAEN +#define STM32L1_RCC_AHBENR 0x4002381C +#define STM32L1_RCC_DMAEN 0x30000000 // DMA2EN | DMA1EN + #define STM32H7_RCC_AHB1ENR 0x58024538 #define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 7e96d3f70..5e7ad2e4a 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -219,6 +219,10 @@ #define STM32L0_FLASH_SR_PGAERR 9 #define STM32L0_FLASH_SR_NOTZEROERR 16 +#define STM32L1_FLASH_SR_ERROR_MASK 0x00003F00 +#define STM32L1_FLASH_SR_WRPERR 8 +#define STM32L1_FLASH_SR_PGAERR 9 + #define FLASH_ACR_OFF ((uint32_t)0x00) #define FLASH_PECR_OFF ((uint32_t)0x04) #define FLASH_PDKEYR_OFF ((uint32_t)0x08) diff --git a/src/common.c b/src/common.c index c49830154..d360b5d03 100644 --- a/src/common.c +++ b/src/common.c @@ -991,9 +991,15 @@ static void stop_wdg_in_debug(stlink_t *sl) { break; case STM32_FLASH_TYPE_L0_L1: case STM32_FLASH_TYPE_G0: - dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; - set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | - (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); + if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { + dbgmcu_cr = STM32L1_DBGMCU_APB1_FZ; + set = (1 << STM32L1_DBGMCU_APB1_FZ_IWDG_STOP) | + (1 << STM32L1_DBGMCU_APB1_FZ_WWDG_STOP); + } else { + dbgmcu_cr = STM32L0_DBGMCU_APB1_FZ; + set = (1 << STM32L0_DBGMCU_APB1_FZ_IWDG_STOP) | + (1 << STM32L0_DBGMCU_APB1_FZ_WWDG_STOP); + } break; case STM32_FLASH_TYPE_H7: dbgmcu_cr = STM32H7_DBGMCU_APB1HFZ; diff --git a/src/common_flash.c b/src/common_flash.c index e2a9ebbc3..df2619cad 100644 --- a/src/common_flash.c +++ b/src/common_flash.c @@ -155,7 +155,11 @@ void clear_flash_error(stlink_t *sl) { write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); break; case STM32_FLASH_TYPE_L0_L1: - write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); + if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { + write_flash_sr(sl, BANK_1, STM32L1_FLASH_SR_ERROR_MASK); + } else { + write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); + } break; case STM32_FLASH_TYPE_L4_L4P: write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); @@ -281,9 +285,14 @@ int check_flash_error(stlink_t *sl) { PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); break; case STM32_FLASH_TYPE_L0_L1: - res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; + res = read_flash_sr(sl, BANK_1); + if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { + res &= STM32L1_FLASH_SR_ERROR_MASK; + } else { + res &= STM32L0_FLASH_SR_ERROR_MASK; + PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); + } WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); break; case STM32_FLASH_TYPE_L4_L4P: diff --git a/src/flashloader.c b/src/flashloader.c index 5592db477..b9c26bf4c 100644 --- a/src/flashloader.c +++ b/src/flashloader.c @@ -127,8 +127,13 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { rcc_dma_mask = STM32G4_RCC_DMAEN; break; case STM32_FLASH_TYPE_L0_L1: - rcc = STM32L0_RCC_AHBENR; - rcc_dma_mask = STM32L0_RCC_DMAEN; + if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { + rcc = STM32L1_RCC_AHBENR; + rcc_dma_mask = STM32L1_RCC_DMAEN; + } else { + rcc = STM32L0_RCC_AHBENR; + rcc_dma_mask = STM32L0_RCC_DMAEN; + } break; case STM32_FLASH_TYPE_H7: rcc = STM32H7_RCC_AHB1ENR; From 43498dedf651260ef34197e512d35e3ad7142401 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 27 Aug 2022 12:23:02 +0200 Subject: [PATCH 1325/1435] General Project Update - Closes #1263. - Updated CHANGELOG.md - Updated list of contributors --- CHANGELOG.md | 14 +++++++++++++- contributors.txt | 3 +++ doc/compiling.md | 8 ++++++-- 3 files changed, 22 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 71188afb0..629b53233 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -22,12 +22,16 @@ Features: - Added support for STLINK-V3 devices with no MSD ([#1185](https://github.com/stlink-org/stlink/pull/1185)) - Updated gdb-server.c to allow external memory access on STM32H73xx ([#1196](https://github.com/stlink-org/stlink/pull/1196), [#1197](https://github.com/stlink-org/stlink/pull/1197)) - Erase addr size / section of the flash memory with st-flash ([#1213](https://github.com/stlink-org/stlink/pull/1213)) +- Added writing and reading for STM32WL option bytes ([#1226](https://github.com/stlink-org/stlink/pull/1226), [#1227](https://github.com/stlink-org/stlink/pull/1227)) +- Added parametres option_base, option_size for F401xD_xE ([#1235](https://github.com/stlink-org/stlink/pull/1235)) +- Added support for option bytes to F1xx_XLD (GD32F30x) ([#1250](https://github.com/stlink-org/stlink/pull/1250)) +- Added option byte address for L4Rx devices ([#1254](https://github.com/stlink-org/stlink/pull/1254)) Updates & changes: - [refactoring] Moved chip-specific parameters into separate files ([#237](https://github.com/stlink-org/stlink/pull/237), [#1129](https://github.com/stlink-org/stlink/pull/1129)) - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) -- Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation ([#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) +- Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation (commit [#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) - Dropped execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) - Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) @@ -35,6 +39,10 @@ Updates & changes: - Updated chip config files from the library structs ([#1181](https://github.com/stlink-org/stlink/pull/1181)) - [doc] Corrected file path in tutorial ([#1186](https://github.com/stlink-org/stlink/pull/1186)) - Improved chipid checks and printouts ([#1188](https://github.com/stlink-org/stlink/pull/1188)) +- [refactoring] Sourcefile 'common.c' ([#1218](https://github.com/stlink-org/stlink/pull/1218), [#1220](https://github.com/stlink-org/stlink/pull/1220)) +- Set C standard through cmake variables ([#1221](https://github.com/stlink-org/stlink/pull/1221)) +- [doc] Added make install to the macOS compiling instructions ([#1259](https://github.com/stlink-org/stlink/pull/1259)) +- [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), (commit [#2926648](https://github.com/stlink-org/stlink/commit/2926648be78f32919c0624bf1060b17fffde8b0d)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) @@ -53,6 +61,10 @@ Fixes: - Define 'SSIZE_MAX' if not defined ([#1183](https://github.com/stlink-org/stlink/pull/1183)) - Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) - Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) +- Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214) +- st-trace: Fixed clock issues ([#1251](https://github.com/stlink-org/stlink/pull/1251), [#1252](https://github.com/stlink-org/stlink/pull/1252)) +- Fixed flash regs addr for STM32L152RET6 in common_flash.c ([#1265](https://github.com/stlink-org/stlink/pull/1265)) +- Fixed flash, dbgmcu and rcc registers for STM32L1 ([#1266](https://github.com/stlink-org/stlink/pull/1266)) # v1.7.0 diff --git a/contributors.txt b/contributors.txt index cffef89f6..2425ae7f0 100644 --- a/contributors.txt +++ b/contributors.txt @@ -51,8 +51,10 @@ Greg Alexander [galexander1] Greg Meiste [meisteg] Grzegorz Szymaszek [gszy] Guillaume Revaillot [grevaillot] +Gwenhael Goavec-Merou [trabucayre] Hakkavélin Halt Hammerzeit +[hydroconstructor] htk Ian Griffiths Jack Peel @@ -115,6 +117,7 @@ Sean Simmons Sergey Alirzaev Simon Derr [sderr] Simon Wright +[simplerobot] Stany Marcel Stefan Misik Sven Wegener diff --git a/doc/compiling.md b/doc/compiling.md index a82941e8a..5d32385bd 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -119,7 +119,7 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma 1. Change into the project source directory: `cd stlink` 2. Run `make clean` -- required by some linux variants. -3. Run `make release` to create the _Release_ target +3. Run `make release` to create the _Release_ target. 4. Run `make install` to full install the package with complete system integration. This might require sudo permissions. 5. Run `make debug` to create the _Debug_ target (_optional_)
      The debug target is only necessary in order to modify the sources and to run under a debugger. @@ -127,6 +127,10 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. +### How to avoid the error message: "Can not open shared object file" + +When installing system-wide (`sudo make install`) the dynamic library cache needs to be updated with the command `ldconfig`. + #### Removal: 1. Run `make uninstall` to perform a clean uninstall of the package from the system. @@ -216,7 +220,7 @@ To do this with only one simple command, type: 2. Run `make clean` to clean remnants of any previous builds. 3. Run `make release` to create the _Release_ target 4. Run `make install` to full install the package with complete system integration. This might require sudo permissions. -5. Run `make debug` to create the _Debug_ target (_optional_)
      +5. Run `make debug` to create the _Debug_ target. (_optional_)
      The debug target is only necessary in order to modify the sources and to run under a debugger. As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. From 8835d387f21755ddb20699c9cece82cf52d54249 Mon Sep 17 00:00:00 2001 From: Robert Jenssen Date: Mon, 29 Aug 2022 10:23:59 +1000 Subject: [PATCH 1326/1435] Fix compilation with gcc-12 --- cmake/modules/c_flags.cmake | 1 + 1 file changed, 1 insertion(+) diff --git a/cmake/modules/c_flags.cmake b/cmake/modules/c_flags.cmake index 44052bba8..6e22d4ff3 100644 --- a/cmake/modules/c_flags.cmake +++ b/cmake/modules/c_flags.cmake @@ -20,6 +20,7 @@ endfunction() add_cflag_if_supported("-Wall") add_cflag_if_supported("-Wextra") add_cflag_if_supported("-Wshadow") +add_cflag_if_supported("-O") add_cflag_if_supported("-D_FORTIFY_SOURCE=2") add_cflag_if_supported("-fstrict-aliasing") add_cflag_if_supported("-Wundef") From 2087711c23d38280ad5f69c39f23e06e19f8f214 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 23 Oct 2022 20:22:16 +0200 Subject: [PATCH 1327/1435] General Project Update - Updated CHANGELOG.md - Updated README.md - Removed support for macOS (Closes #1269) --- .github/ISSUE_TEMPLATE/bug-report.md | 2 +- .github/workflows/c-cpp.yml | 82 --- CHANGELOG.md | 3 +- README.md | 14 +- cmake/modules/Findlibusb.cmake | 19 +- cmake/packaging/cpack_config.cmake | 7 +- cmake/packaging/deb/copyright | 1 - doc/compiling.md | 42 -- doc/dev/app-example/CMakeLists.txt | 3 +- doc/version_support.md | 9 - src/win32/getopt/getopt.c | 2 +- stlinkv1_macos_driver/Makefile | 58 --- stlinkv1_macos_driver/README.md | 39 -- stlinkv1_macos_driver/install.sh | 16 - .../Contents/Info.plist | 82 --- .../Contents/MacOS/stlink_shield_10_15 | Bin 33840 -> 0 bytes .../stlink_shield_10_15.kext/Contents/PkgInfo | 1 - .../Contents/_CodeSignature/CodeResources | 115 ----- .../stlink_shield_xcode/Info.plist | 60 --- .../stlink_shield.xcodeproj/project.pbxproj | 480 ------------------ .../contents.xcworkspacedata | 7 - .../xcshareddata/IDEWorkspaceChecks.plist | 8 - .../xcshareddata/WorkspaceSettings.xcsettings | 8 - .../UserInterfaceState.xcuserstate | Bin 187405 -> 0 bytes .../WorkspaceSettings.xcsettings | 24 - .../xcschemes/stlink_shield_10.14.xcscheme | 67 --- .../xcschemes/stlink_shield_10.15.xcscheme | 67 --- .../xcschemes/xcschememanagement.plist | 37 -- 28 files changed, 8 insertions(+), 1245 deletions(-) delete mode 100644 stlinkv1_macos_driver/Makefile delete mode 100644 stlinkv1_macos_driver/README.md delete mode 100644 stlinkv1_macos_driver/install.sh delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/Info.plist delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/MacOS/stlink_shield_10_15 delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/PkgInfo delete mode 100644 stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/_CodeSignature/CodeResources delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/Info.plist delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.pbxproj delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/contents.xcworkspacedata delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/xcshareddata/IDEWorkspaceChecks.plist delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/xcshareddata/WorkspaceSettings.xcsettings delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/xcuserdata/vm-user.xcuserdatad/UserInterfaceState.xcuserstate delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/project.xcworkspace/xcuserdata/vm-user.xcuserdatad/WorkspaceSettings.xcsettings delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.14.xcscheme delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.15.xcscheme delete mode 100644 stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist diff --git a/.github/ISSUE_TEMPLATE/bug-report.md b/.github/ISSUE_TEMPLATE/bug-report.md index c733c2c2e..690bceb3e 100644 --- a/.github/ISSUE_TEMPLATE/bug-report.md +++ b/.github/ISSUE_TEMPLATE/bug-report.md @@ -20,7 +20,7 @@ labels: "" In order to allow developers to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific problem. - [ ] Programmer/board type: [enter here] (e.g STLINK /V1, /V2, /V2-onboard, /V2-clone, /V3) -- [ ] Operating system an version: [enter here] (e.g Linux, macOS, Windows) +- [ ] Operating system an version: [enter here] (e.g Linux, Windows) - [ ] **stlink tools version** and/or git commit hash: [enter here] (e.g v1.6.1/git-d0416149) - [ ] stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-trace`, `st-util`) - [ ] Target chip (and board, if applicable): [enter here] (e.g STM32F103C8T6 (NUCLEO-F103RB)) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index 442b3ba43..8e798269b 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -188,88 +188,6 @@ jobs: run: sudo make package - name: sudo make uninstall run: sudo make uninstall && sudo make clean - - # macOS - - job_macos_10_15_gcc: - name: macos-10.15 gcc - runs-on: macos-10.15 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: brew install gcc libusb gtk+3 - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - job_macos_10_15_clang: - name: macos-10.15 clang - runs-on: macos-10.15 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: brew install llvm libusb gtk+3 - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - # job_macos_11_gcc: - # name: macos-11.0 gcc - # runs-on: macos-11.0 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: brew install gcc libusb gtk+3 - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean - # job_macos_11_clang: - # name: macos-11.0 clang - # runs-on: macos-11.0 - # steps: - # - uses: actions/checkout@v2 - # - name: Install dependencies - # run: brew install llvm libusb gtk+3 - # - name: make debug - # run: sudo make clean && make debug - # - name: make test - # run: sudo make clean && make test - # - name: make release - # run: sudo make clean && make release - # - name: sudo make install - # run: sudo make clean && sudo make install - # - name: sudo make package - # run: sudo make package - # - name: sudo make uninstall - # run: sudo make uninstall && sudo make clean - # Linux MinGW cross compliation # job_linux_20_04_cross: diff --git a/CHANGELOG.md b/CHANGELOG.md index 629b53233..f48840c3f 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -42,7 +42,7 @@ Updates & changes: - [refactoring] Sourcefile 'common.c' ([#1218](https://github.com/stlink-org/stlink/pull/1218), [#1220](https://github.com/stlink-org/stlink/pull/1220)) - Set C standard through cmake variables ([#1221](https://github.com/stlink-org/stlink/pull/1221)) - [doc] Added make install to the macOS compiling instructions ([#1259](https://github.com/stlink-org/stlink/pull/1259)) -- [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), (commit [#2926648](https://github.com/stlink-org/stlink/commit/2926648be78f32919c0624bf1060b17fffde8b0d)) +- [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), (commit [#43498de](https://github.com/stlink-org/stlink/commit/43498dedf651260ef34197e512d35e3ad7142401)) Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) @@ -63,6 +63,7 @@ Fixes: - Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) - Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214) - st-trace: Fixed clock issues ([#1251](https://github.com/stlink-org/stlink/pull/1251), [#1252](https://github.com/stlink-org/stlink/pull/1252)) +- Fixed compilation with gcc-12 ([#1257](https://github.com/stlink-org/stlink/pull/1257), [#1267](https://github.com/stlink-org/stlink/pull/1267)) - Fixed flash regs addr for STM32L152RET6 in common_flash.c ([#1265](https://github.com/stlink-org/stlink/pull/1265)) - Fixed flash, dbgmcu and rcc registers for STM32L1 ([#1266](https://github.com/stlink-org/stlink/pull/1266)) diff --git a/README.md b/README.md index bc491189e..b889de389 100644 --- a/README.md +++ b/README.md @@ -9,7 +9,6 @@ [![CodeQL](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml/badge.svg)](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml) [![C/C++ CI](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml/badge.svg?branch=testing)](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml) [![Linux Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=linux&label=linux)](https://travis-ci.org/stlink-org/stlink) -[![macOS Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=osx&label=osx)](https://travis-ci.org/stlink-org/stlink) Recent new features and bugfixes can be found in the [Changelog](CHANGELOG.md) of this software project. @@ -22,7 +21,7 @@ The stlink library and tools are licensed under the **[BSD-3 License](LICENSE.md stlink is an open source toolset to program and debug STM32 devices and boards manufactured by STMicroelectronics. It supports several so called STLINK programmer boards (and clones thereof) which use a microcontroller chip to translate commands from USB to JTAG/SWD. There are four generations available on the market which are _all_ supported by this toolset: -- **STLINK/V1** _[obsolete as of 21-11-2019, continued support by this toolset] \*)_ +- **STLINK/V1** _[obsolete as of 21-11-2019, continued support by this toolset]_ - transport layer: SCSI passthru commands over USB - stand-alone programmer - on-board on STM32VL Discovery boards @@ -38,8 +37,6 @@ It supports several so called STLINK programmer boards (and clones thereof) whic - stand-alone programmer (STLINK-V3SET, STLINK-V3MINI, STLINK-V3MODS) - on-board on some STM32 Nucleo boards (STLINK-V3E) -_\*)_ *Note: Support for the STLINK/V1 on macOS is limited to 10.15. Due to the deprecation and removal of macOS Kernel Extensions (KEXT) there will be no support for this programmer on macOS 11 or any later version.* - On the user level there is no difference in handling or operation between these different revisions. The STlink toolset includes: @@ -70,15 +67,6 @@ Please ensure to select the correct version for your system (i686 or x86_64). Th Alternatively one may compile and install from source as described in our [compiling manual](doc/compiling.md#Windows). -**macOS**: - -We recommend to install from: - -- [homebrew](https://formulae.brew.sh/formula/stlink) or -- [MacPorts](https://ports.macports.org/port/stlink) - -Alternatively one can compile and install from source as described in our [compiling manual](doc/compiling.md#macOS). - **Linux**: We recommend to install `stlink-tools` from the package repository of the used distribution: diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index de3712eca..7442c8cc4 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -10,24 +10,7 @@ include(FindPackageHandleStandardArgs) -if (APPLE) # macOS - FIND_PATH( - LIBUSB_INCLUDE_DIR NAMES libusb.h - HINTS /usr /usr/local /opt - PATH_SUFFIXES libusb-1.0 - ) - set(LIBUSB_NAME libusb-1.0.a) - find_library( - LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} - HINTS /usr /usr/local /opt - ) - FIND_PACKAGE_HANDLE_STANDARD_ARGS(libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) - mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) - if (NOT LIBUSB_FOUND) - message(FATAL_ERROR "No libusb library found on your system! Install libusb-1.0 from Homebrew or MacPorts") - endif () - -elseif (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated into the system +if (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is integrated into the system FIND_PATH( LIBUSB_INCLUDE_DIR NAMES libusb.h HINTS /usr/include diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index a4f1ae073..8766fb2e0 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -15,12 +15,7 @@ set(CPACK_SET_DESTDIR "ON") file(MAKE_DIRECTORY ${CMAKE_BINARY_DIR}/dist) set(CPACK_OUTPUT_FILE_PREFIX "${CMAKE_BINARY_DIR}/dist") -if (APPLE) # macOS - set(CPACK_GENERATOR "ZIP") - set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-macos-amd64") - set(CPACK_INSTALL_PREFIX "") - -elseif (WIN32 AND (NOT EXISTS "/etc/debian_version")) # Windows +if (WIN32 AND (NOT EXISTS "/etc/debian_version")) # Windows set(CPACK_GENERATOR "ZIP") set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-win32") set(CPACK_INSTALL_PREFIX "") diff --git a/cmake/packaging/deb/copyright b/cmake/packaging/deb/copyright index f5dfdc51b..c8ff30973 100644 --- a/cmake/packaging/deb/copyright +++ b/cmake/packaging/deb/copyright @@ -2,7 +2,6 @@ Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ Upstream-Name: stlink Upstream-Contact: Nightwalker-87 Source: https://github.com/stlink-org/stlink -Files-Excluded: stlinkv1_macos_driver Files: * Copyright: 2011-2020 stlink-org diff --git a/doc/compiling.md b/doc/compiling.md index 5d32385bd..5f6852a93 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -183,48 +183,6 @@ Choose one of the following options _before_ connecting the device to your compu 1. `cp stlink_v1.modprobe.conf /etc/modprobe.d` 2. `modprobe -r usb-storage && modprobe usb-storage` -## macOS - -### Common requirements - -The best and recommended way is to install a package manager for open source software, -either [homebrew](https://brew.sh) or [MacPorts](https://www.macports.org/). - -Then install the following dependencies from the package repository: - -- `git` -- `gcc` or `llvm` (for clang) (C-compiler) -- `cmake` -- `libusb` -- `gtk+3` or `gtk3` (_optional_, needed for `stlink-gui`) - -To do this with only one simple command, type: - -- for homebrew: - - with gcc: `sudo brew install git gcc cmake libusb gtk+3` or - - with clang: `sudo brew install git llvm cmake libusb gtk+3` or -- for MacPorts: - - with gcc: `sudo port install git gcc10 cmake libusb gtk3` or - - with clang: `sudo port install git llvm-10 cmake libusb gtk3` - -### Installation - -1. Open a new terminal window -2. Create a new destination folder at a place of your choice e.g. at `~/git`: `mkdir $HOME/git` -3. Change to this directory: `cd ~/git` -4. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git` - -### Building - -1. Change into the project source directory: `cd stlink` -2. Run `make clean` to clean remnants of any previous builds. -3. Run `make release` to create the _Release_ target -4. Run `make install` to full install the package with complete system integration. This might require sudo permissions. -5. Run `make debug` to create the _Debug_ target. (_optional_)
      - The debug target is only necessary in order to modify the sources and to run under a debugger. - -As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. - ## Build options ### Build using a different directory for shared libs diff --git a/doc/dev/app-example/CMakeLists.txt b/doc/dev/app-example/CMakeLists.txt index 5f71a5d4f..69ba2090e 100644 --- a/doc/dev/app-example/CMakeLists.txt +++ b/doc/dev/app-example/CMakeLists.txt @@ -1,6 +1,5 @@ # Warning: This example assumes that you are building on a host with pkg-config available (e.g. linux). -# The logic required to build under windows/mingw and/or mac was intentionally omitted to keep this -# CMakeLists as small as possible. +# The logic required to build under windows/mingw was intentionally omitted to keep this CMakeLists as small as possible. cmake_minimum_required(VERSION 3.4.2) diff --git a/doc/version_support.md b/doc/version_support.md index 01d9dddb1..0f1849697 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -10,15 +10,6 @@ Up on compiling c-make will **automatically** download and install the latest co - Windows 10 - Windows 8.1 -### Apple macOS - -| Package Repository | libusb | cmake | gtk-3-dev | Supported macOS versions | -| ------------------ | ------ | ------ | ------------------ | ------------------------ | -| homebrew | 1.0.25 | 3.22.1 | 3.24.30
      gtk+3 | **10.10 - 12.x** | -| MacPorts | 1.0.25 | 3.22.1 | 3.24.31
      gtk3 | **10.4 - 12.x** | - -NOTE: In order to use a STLINK/V1 programmer on macOS, version 10.15 is required. - ### Linux-/Unix-based: | Operating System | libusb | cmake | libgtk-dev | Notes | diff --git a/src/win32/getopt/getopt.c b/src/win32/getopt/getopt.c index 85e8804d8..ff0a2fd91 100644 --- a/src/win32/getopt/getopt.c +++ b/src/win32/getopt/getopt.c @@ -179,7 +179,7 @@ int getopt_long(int argc, if (match->has_arg == required_argument) { /* Only scan the next argv for required arguments. Behavior is not - specified, but has been observed with Ubuntu and macOS. */ + specified, but has been observed with Ubuntu. */ if (optarg == NULL && ++optind < argc) { optarg = argv[optind]; } if (optarg == NULL) { retval = ':'; } diff --git a/stlinkv1_macos_driver/Makefile b/stlinkv1_macos_driver/Makefile deleted file mode 100644 index e6ba6309b..000000000 --- a/stlinkv1_macos_driver/Makefile +++ /dev/null @@ -1,58 +0,0 @@ -### -# Makefile for STlink-v1 support -### - -VPATH=src - -SOURCES_LIB=common.c usb.c sg.c logging.c -OBJS_LIB=$(SOURCES_LIB:.c=.o) -TEST_PROGRAMS=test-flash test-sg test-usb -LDFLAGS=-L. -lstlink -lusb-1.0 - -CFLAGS+=-g -CFLAGS+=-DDEBUG=1 -CFLAGS+=-std=gnu11 -CFLAGS+=-Wall -Wextra - - -LIBRARY=libstlink.a - -all: $(LIBRARY) flash gdbserver $(TEST_PROGRAMS) - -$(LIBRARY): $(OBJS_LIB) - @echo "objs are $(OBJS_LIB)" - $(AR) -cr $@ $^ - @echo "Compilation of library completed." - - -test_sg: test_sg.o $(LIBRARY) - @echo "building test_sg" - $(CC) test_sg.o $(LDFLAGS) -o $@ - -test_usb: test_usb.o $(LIBRARY) - @echo "building test_usb" - $(CC) test_usb.o $(LDFLAGS) -o $@ - @echo "done linking" - -%.o: %.c - @echo "building $^ into $@" - $(CC) $(CFLAGS) -c $^ -o $@ - @echo "done compiling" - -clean: - rm -rf $(OBJS_LIB) - rm -rf $(LIBRARY) - rm -rf test-flash* test-sg* test-usb* - $(MAKE) -C flash clean - $(MAKE) -C gdbserver clean - -flash: - $(MAKE) -C flash - -gdbserver: - $(MAKE) -C gdbserver CONFIG_USE_LIBSG="$(CONFIG_USE_LIBSG)" - -macos_stlink_shield: - ./install.sh - -.PHONY: clean all flash gdbserver diff --git a/stlinkv1_macos_driver/README.md b/stlinkv1_macos_driver/README.md deleted file mode 100644 index e0f9256e8..000000000 --- a/stlinkv1_macos_driver/README.md +++ /dev/null @@ -1,39 +0,0 @@ -# Installation instructions for STLINK/v1 driver - -When connecting to the STLINK/v1 on macOS via USB, the system claims the programmer as a SCSI device. Thus libusb is not able to initialise and establish a connection to it. To solve this issue Marco Cassinerio (marco.cassinerio@gmail.com) has created a so called "codeless driver" which claims the device. It is of higher priority then the default apple mass storage driver, what allows the device to be accessed through libusb. - -To make use of this alternative approach one needs to go through the following steps: - -1) Configure System Integrity Protection (SIP) - -The above system security setting introduced by Apple with OS X El Capitan (10.11) in 2015 is active per default -and prevents the operating system amongst other things to load unsigned Kernel Extension Modules (kext). -Thus the STLINK/v1 driver supplied with the tools, which installs as a kext, remains not functional, -until SIP is fully deactivated. Without SIP-deactivation, st-util would fail to detect a STLINK/v1 device later on. - -In order to deactivate SIP, boot into the recovery mode and run ```csrutil disable``` in a terminal console window. - -2) Reboot the system. - -3) Install the macOS Kernel Extension (kext) (ST-Link-v1 driver): - - Open a terminal console and navigate to this subdirectory `/stlinkv1_macos_driver` - - Use the command ```sudo sh ./install.sh``` to install the appropiate kext for your system version. - This should result in the following output: - -``` -Requesting load of /Library/Extensions/stlink_shield.kext. -/Library/Extensions/stlink_shield.kext loaded successfully (or already loaded). -``` -4) Reboot the system. - -5) Verify correct detection of the STLINK/v1 device with the following input: `st-util -1` -You should then see a similar output like in this example: - -``` -INFO common.c: Loading device parameters.... -INFO common.c: Device connected is: F1 High-density device, id 0x10036414 -INFO common.c: SRAM size: 0x10000 bytes (64 KiB), Flash: 0x80000 bytes (512 KiB) in pages of 2048 bytes -INFO sg.c: Successfully opened a stlink v1 debugger -INFO gdb-server.c: Chip ID is 00000414, Core ID is 1ba01477. -INFO gdb-server.c: Listening at *:4242... -``` diff --git a/stlinkv1_macos_driver/install.sh b/stlinkv1_macos_driver/install.sh deleted file mode 100644 index f9878bd46..000000000 --- a/stlinkv1_macos_driver/install.sh +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/bash - -ISMACOS=$(sw_vers -productVersion) -case $ISMACOS in -10.15*) - KEXT="stlink_shield_10_15.kext" - ;; -*) - echo "OS X version not supported." - exit 1 - ;; -esac -chown -R root:wheel $KEXT/ -cp -R $KEXT /Library/Extensions/stlink_shield.kext -kextload -v /Library/Extensions/stlink_shield.kext -touch /Library/Extensions diff --git a/stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/Info.plist b/stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/Info.plist deleted file mode 100644 index 2077b9c8a..000000000 --- a/stlinkv1_macos_driver/stlink_shield_10_15.kext/Contents/Info.plist +++ /dev/null @@ -1,82 +0,0 @@ - - - - - BuildMachineOSBuild - 18G7016 - CFBundleDevelopmentRegion - English - CFBundleIdentifier - com.libusb.stlink-shield - CFBundleInfoDictionaryVersion - 6.0 - CFBundlePackageType - KEXT - CFBundleSignature - ???? - CFBundleSupportedPlatforms - - MacOSX - - CFBundleVersion - 1.0.0 - DTCompiler - com.apple.compilers.llvm.clang.1_0 - DTPlatformBuild - 11C504 - DTPlatformVersion - GM - DTSDKBuild - 19B90 - DTSDKName - macosx10.15 - DTXcode - 1130 - DTXcodeBuild - 11C504 - IOKitPersonalities - - DeviceDriver - - CFBundleIdentifier - com.apple.kpi.iokit - IOClass - IOService - IOProviderClass - IOUSBDevice - bcdDevice - 256 - idProduct - 14148 - idVendor - 1155 - - InterfaceDriver - - CFBundleIdentifier - com.apple.kpi.iokit - IOClass - IOService - IOProviderClass - IOUSBInterface - bConfigurationValue - 1 - bInterfaceNumber - 0 - idProduct - 14148 - idVendor - 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- IssueFilterStyle - ShowAll - LiveSourceIssuesEnabled - - SharedBuildFolderName - Build - - diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.14.xcscheme b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.14.xcscheme deleted file mode 100644 index 79299d7a5..000000000 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.14.xcscheme +++ /dev/null @@ -1,67 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.15.xcscheme b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.15.xcscheme deleted file mode 100644 index e72a90366..000000000 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcshareddata/xcschemes/stlink_shield_10.15.xcscheme +++ /dev/null @@ -1,67 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist b/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist deleted file mode 100644 index c9d1a75b6..000000000 --- a/stlinkv1_macos_driver/stlink_shield_xcode/stlink_shield.xcodeproj/xcuserdata/vm-user.xcuserdatad/xcschemes/xcschememanagement.plist +++ /dev/null @@ -1,37 +0,0 @@ - - - - - SchemeUserState - - stlink_shield_10.14.xcscheme_^#shared#^_ - - orderHint - 0 - - stlink_shield_10.15.xcscheme_^#shared#^_ - - orderHint - 1 - - - SuppressBuildableAutocreation - - 8F9084E724786F0B009109AD - - primary - - - 8F9084F324786F0F009109AD - - primary - - - 8F9084FF24786F39009109AD - - primary - - - - - From ff8114895a9fc32cae6a9374e58eac6256d68183 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 23 Oct 2022 20:40:43 +0200 Subject: [PATCH 1328/1435] Corrected sram_size for L496x/L4A6x devices (Closes #1268) --- config/chips/L496x_L4A6x.chip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index df1f084ff..6657d5484 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -6,7 +6,7 @@ chip_id 0x461 // STM32_CHIPID_L496x_L4A6x flash_type L4_L4P flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB -sram_size 0x40000 // 256 KB +sram_size 0x50000 // 320 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE From f93adb92f2e4ecf05a9361cb723c98693586929d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 24 Oct 2022 01:49:03 +0200 Subject: [PATCH 1329/1435] Fixes for project compilation - Cleanup for CMakeLists.txt - [doc] Added list of cmake path variables - Fixed stlink-gui install path (Closes #1270) (Closes #1271) - Replaced path variable for chips directory --- CMakeLists.txt | 105 +++++++++++++++++++---------- cmake/packaging/cpack_config.cmake | 2 +- doc/man/CMakeLists.txt | 2 +- src/st-flash/flash.c | 2 +- src/st-info/info.c | 2 +- src/st-trace/trace.c | 2 +- src/st-util/gdb-server.c | 2 +- src/stlink-gui/CMakeLists.txt | 10 +-- src/stlink-gui/gui.c | 2 +- tests/CMakeLists.txt | 2 +- 10 files changed, 83 insertions(+), 48 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 67f76ec08..94721f213 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -13,22 +13,69 @@ set(CMAKE_C_STANDARD 11) set(CMAKE_C_STANDARD_REQUIRED ON) set(CMAKE_C_EXTENSIONS ON) +### +# +# Default cmake directories: +# +# | Target Type | GNUInstallDirs Variable | Built-In Default | +# | --- | --- | --- | +# | RUNTIME | ${CMAKE_INSTALL_BINDIR} | bin | +# | LIBRARY | ${CMAKE_INSTALL_LIBDIR} | lib | +# | ARCHIVE | ${CMAKE_INSTALL_LIBDIR} | lib | +# | PRIVATE_HEADER | ${CMAKE_INSTALL_INCLUDEDIR} | include | +# | PUBLIC_HEADER | ${CMAKE_INSTALL_INCLUDEDIR} | include | +# | FILE_SET (type HEADERS) | ${CMAKE_INSTALL_INCLUDEDIR} | include | +# +# | TYPE Argument | GNUInstallDirs Variable | Built-In Default | +# | --- | --- | --- | +# | BIN | ${CMAKE_INSTALL_BINDIR} | bin | +# | SBIN | ${CMAKE_INSTALL_SBINDIR} | sbin | +# | LIB | ${CMAKE_INSTALL_LIBDIR} | lib | +# | INCLUDE | ${CMAKE_INSTALL_INCLUDEDIR} | include | +# | SYSCONF | ${CMAKE_INSTALL_SYSCONFDIR} | etc | +# | SHAREDSTATE | ${CMAKE_INSTALL_SHARESTATEDIR} | com | +# | LOCALSTATE | ${CMAKE_INSTALL_LOCALSTATEDIR} | var | +# | RUNSTATE | ${CMAKE_INSTALL_RUNSTATEDIR} | /run | +# | DATA | ${CMAKE_INSTALL_DATADIR} | | +# | INFO | ${CMAKE_INSTALL_INFODIR} | /info | +# | LOCALE | ${CMAKE_INSTALL_LOCALEDIR} | /locale | +# | MAN | ${CMAKE_INSTALL_MANDIR} | /man | +# | DOC | ${CMAKE_INSTALL_DOCDIR} | /doc | +# +# ${CMAKE_BINARY_DIR} +# This is the full path to the top level of the current CMake build tree. +# For an in-source build, this would be the same as CMAKE_SOURCE_DIR. +# +# ${CMAKE_SOURCE_DIR} +# This is the full path to the top level of the current CMake source tree. +# For an in-source build, this would be the same as CMAKE_BINARY_DIR. +# +# ${CMAKE_CURRENT_BINARY_DIR} +# The path to the binary directory currently being processed. +# This is the full path to the build directory that is currently being processed by cmake. +# Each directory added by add_subdirectory() will create a binary directory in the build tree, +# and as it is being processed this variable will be set. +# For in-source builds this is the current source directory being processed. +# +# ${CMAKE_CURRENT_SOURCE_DIR} +# The path to the source directory currently being processed. +# This is the full path to the source directory that is currently being processed by cmake. +# +### + ### -# General project settings +# General Project Settings ### project(stlink C) set(PROJECT_DESCRIPTION "Open source version of the STMicroelectronics ST-LINK Tools") -include(GNUInstallDirs) # Define GNU standard installation directories +include(${CMAKE_MODULE_PATH}/get_version.cmake) # Determine project version -## MCU configuration files -set(CMAKE_CHIPS_SUBDIR stlink/chips) -set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_PREFIX}/${CMAKE_CHIPS_SUBDIR}) -add_definitions( -DETC_STLINK_DIR="${CMAKE_CHIPS_DIR}" ) +include(GNUInstallDirs) # Define GNU standard installation directories -## Determine project version -include(${CMAKE_MODULE_PATH}/get_version.cmake) +# Define install directory /usr/share +set(CMAKE_INSTALL_SHAREDIR /usr/share/) ## Set C build flags if (NOT MSVC) @@ -178,8 +225,6 @@ endif () # Libraries ### -set(STLINK_LIBRARY_PATH ${CMAKE_INSTALL_LIBDIR} CACHE PATH "Main library install directory") - # Set the environment variable LD_LIBRARY_PATH to point to /usr/local/lib (per default). execute_process(COMMAND bash -c "export LD_LIBRARY_PATH=${CMAKE_INSTALL_LIBDIR}") @@ -205,21 +250,15 @@ set_target_properties(${STLINK_LIB_SHARED} PROPERTIES ) # Link shared library -if (APPLE) # ... with Apple macOS libraries - find_library(ObjC objc) - find_library(CoreFoundation CoreFoundation) - find_library(IOKit IOKit) - find_library(Security Security) - target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB} ${ObjC} ${CoreFoundation} ${IOKit} ${Security}) -elseif (WIN32) # ... with Windows libraries +if (WIN32) # ... with Windows libraries target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB} wsock32 ws2_32) else () target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB}) endif () install(TARGETS ${STLINK_LIB_SHARED} - ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH} - LIBRARY DESTINATION ${STLINK_LIBRARY_PATH} + ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} + LIBRARY DESTINATION ${CMAKE_INSTALL_LIBDIR} RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} ) @@ -248,19 +287,13 @@ set_target_properties(${STLINK_LIB_STATIC} PROPERTIES ) # Link static library -if (APPLE) # ... with Apple macOS libraries - find_library(ObjC objc) - find_library(CoreFoundation CoreFoundation) - find_library(IOKit IOKit) - find_library(Security Security) - target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB} ${ObjC} ${CoreFoundation} ${IOKit} ${Security}) -elseif (WIN32) # ... with Windows libraries +if (WIN32) # ... with Windows libraries target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB} wsock32 ws2_32) else () target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB}) endif () -install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${STLINK_LIBRARY_PATH}) +install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}) ### @@ -284,7 +317,7 @@ add_executable(st-info ${ST-INFO_SOURCES}) add_executable(st-util ${ST-UTIL_SOURCES}) add_executable(st-trace ${ST-TRACE_SOURCES}) -if (WIN32 OR APPLE) +if (WIN32) target_link_libraries(st-flash ${STLINK_LIB_STATIC} ${SSP_LIB}) target_link_libraries(st-info ${STLINK_LIB_STATIC} ${SSP_LIB}) target_link_libraries(st-util ${STLINK_LIB_STATIC} ${SSP_LIB}) @@ -301,10 +334,6 @@ install(TARGETS st-info DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-util DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-trace DESTINATION ${CMAKE_INSTALL_BINDIR}) -# Install MCU configuration files -file(GLOB CHIP_FILES ${CMAKE_SOURCE_DIR}/config/chips/*.chip) -install(FILES ${CHIP_FILES} DESTINATION ${CMAKE_CHIPS_DIR}) - ### # Device configuration (Linux only) @@ -326,13 +355,19 @@ endif () # Additional build tasks ### -add_subdirectory(src/stlink-gui) # contains subordinate CMakeLists to build GUI -add_subdirectory(tests) # contains subordinate CMakeLists to build test executables -add_subdirectory(cmake/packaging) # contains subordinate CMakeLists to build packages +# MCU configuration files +set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}/chips) +add_definitions( -DSTLINK_CHIPS_DIR="${CMAKE_CHIPS_DIR}" ) +file(GLOB CHIP_FILES ${CMAKE_SOURCE_DIR}/config/chips/*.chip) +install(FILES ${CHIP_FILES} DESTINATION ${CMAKE_CHIPS_DIR}) +# Documentation / manpages option(STLINK_GENERATE_MANPAGES "Generate manpages with pandoc" OFF) add_subdirectory(doc/man) # contains subordinate CMakeLists to generate manpages +add_subdirectory(src/stlink-gui) # contains subordinate CMakeLists to build GUI +add_subdirectory(tests) # contains subordinate CMakeLists to build test executables +add_subdirectory(cmake/packaging) # contains subordinate CMakeLists to build packages ### # Uninstall target diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index 8766fb2e0..55a859189 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -20,7 +20,7 @@ if (WIN32 AND (NOT EXISTS "/etc/debian_version")) # Wi set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-win32") set(CPACK_INSTALL_PREFIX "") -elseif (WIN32) # Windows cross-build on Debian/Ubuntu +elseif (WIN32) # Windows cross-build on Debian/Ubuntu set(CPACK_GENERATOR "ZIP") set(CPACK_PACKAGE_FILE_NAME "${PROJECT_NAME}-${PROJECT_VERSION}-${TOOLCHAIN_PREFIX}") set(CPACK_INSTALL_PREFIX "") diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 9b3c50764..1b7d6501f 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -30,7 +30,7 @@ foreach (manpage ${MANPAGES}) endif () if (f AND NOT WIN32) - install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATAROOTDIR}/man/man1) + install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATADIR}/man/man1) unset(f) endif () endforeach () diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index a9952dd34..058501ad6 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -62,7 +62,7 @@ int main(int ac, char** av) { } printf("st-flash %s\n", STLINK_VERSION); - init_chipids (ETC_STLINK_DIR); + init_chipids (STLINK_CHIPS_DIR); sl = stlink_open_usb(o.log_level, o.connect, (char *)o.serial, o.freq); diff --git a/src/st-info/info.c b/src/st-info/info.c index d02653bc5..9963606e3 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -68,7 +68,7 @@ static int print_data(int ac, char **av) { return(0); } - init_chipids(ETC_STLINK_DIR); + init_chipids(STLINK_CHIPS_DIR); for (int i=2; i Date: Sun, 13 Nov 2022 17:51:07 -0800 Subject: [PATCH 1330/1435] Update CMakeLists.txt --- CMakeLists.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 94721f213..4048928bb 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -74,8 +74,8 @@ include(${CMAKE_MODULE_PATH}/get_version.cmake) # Determine project version include(GNUInstallDirs) # Define GNU standard installation directories -# Define install directory /usr/share -set(CMAKE_INSTALL_SHAREDIR /usr/share/) +# Define install directory /usr/local/share [the new MacOS does not allow changes to /usr/share ] +set(CMAKE_INSTALL_SHAREDIR /usr/local/share/) ## Set C build flags if (NOT MSVC) From 0d96e362696c5b9be0f98ea3187bbfcca12dfd66 Mon Sep 17 00:00:00 2001 From: Wingman Shen Date: Sun, 13 Nov 2022 17:53:59 -0800 Subject: [PATCH 1331/1435] Update README.md --- README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index b889de389..571db49fd 100644 --- a/README.md +++ b/README.md @@ -84,6 +84,7 @@ We recommend to install `stlink-tools` from the package repository of the used d - RedHat/CentOS 8: Users can install from [EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel8) - FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) +- MacOS: Users can open a terminal window and then follow the same procedure as for installing on Linux ## Installation from source (advanced users) @@ -103,4 +104,4 @@ Please also refer to our [Contribution Guidelines](CONTRIBUTING.md). *I hope it's not to out of topic, but I've been so frustrated with AVR related things on OpenBSD, the fact that stlink built out of the box without needing to touch anything was so relieving. Literally made my whole weekend better! I take it's thanks to @Crest and also to the stlink-org team (@Nightwalker-87 and @xor-gate it seems) to have made a software that's not unfriendly to the "fringe" OSes. -Thank you <3"* - nbonfils, 11.12.2021 \ No newline at end of file +Thank you <3"* - nbonfils, 11.12.2021 From eb35054ea646ef80b1d57cd3a26bc00583f38d08 Mon Sep 17 00:00:00 2001 From: Angel Iglesias Date: Tue, 22 Nov 2022 10:28:49 +0100 Subject: [PATCH 1332/1435] config: udev: Add rule for the V3 MINIE programmer --- config/udev/rules.d/49-stlinkv3.rules | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/config/udev/rules.d/49-stlinkv3.rules b/config/udev/rules.d/49-stlinkv3.rules index 5161947a9..98c33eddf 100644 --- a/config/udev/rules.d/49-stlinkv3.rules +++ b/config/udev/rules.d/49-stlinkv3.rules @@ -7,7 +7,12 @@ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3752", \ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3753", \ MODE:="0666", \ SYMLINK+="stlinkv3_%n" - + +# STLink V3SET MINIE +SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3754", \ + MODE:="0666", \ + SYMLINK+="stlinkv3_%n" + # STLink V3SET SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374d", \ MODE:="0666", \ From 44ec93d80c191ad22cdecf974d3cc345db654de6 Mon Sep 17 00:00:00 2001 From: Wingman Date: Sat, 3 Dec 2022 05:11:59 -0800 Subject: [PATCH 1333/1435] add if-clause for macOS --- CMakeLists.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 4048928bb..124f12f5a 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -74,8 +74,17 @@ include(${CMAKE_MODULE_PATH}/get_version.cmake) # Determine project version include(GNUInstallDirs) # Define GNU standard installation directories -# Define install directory /usr/local/share [the new MacOS does not allow changes to /usr/share ] -set(CMAKE_INSTALL_SHAREDIR /usr/local/share/) +# Define install directory /usr/local/share [not /usr/share on MacOS] +cmake_host_system_information(RESULT OS_NAME QUERY OS_NAME) +message(STATUS "Checking for OS_NAME: ${OS_NAME}") + +if (OS_NAME STREQUAL "macOS") + message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/local/share)") + set(CMAKE_INSTALL_SHAREDIR /usr/local/share/) +else () + message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/share)") + set(CMAKE_INSTALL_SHAREDIR /usr/share/) +endif () ## Set C build flags if (NOT MSVC) From 33430783b3b18ab88ff89d10d7a2a24dadae2472 Mon Sep 17 00:00:00 2001 From: Marcus Lindemann Date: Sun, 4 Dec 2022 18:11:51 +0100 Subject: [PATCH 1334/1435] [#1] fFix GUI compilation fail on OpenBSD i386 Explicitely convert from goffset to gsize with prior overflow check. Implicit conversion is forbidden by compiler settings. --- src/stlink-gui/gui.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index a58d59247..d7e74c547 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -301,7 +301,14 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { if (gui->file_mem.memory) { g_free(gui->file_mem.memory); } - gui->file_mem.size = g_file_info_get_size(file_info); + goffset file_size = g_file_info_get_size(file_info); + + if (G_MAXSIZE < file_size) { + stlink_gui_set_info_error_message(gui, "File too large."); + goto out_input; + } + + gui->file_mem.size = (gsize) file_info; gui->file_mem.memory = g_malloc(gui->file_mem.size); for (off = 0; off < (gint)gui->file_mem.size; off += MEM_READ_SIZE) { From 014907144840b8a45f3dabd83b6b07b0c0cad72b Mon Sep 17 00:00:00 2001 From: Marcus Lindemann Date: Sun, 4 Dec 2022 18:11:51 +0100 Subject: [PATCH 1335/1435] Fix GUI compilation fail on OpenBSD i386 Explicitely convert from goffset to gsize with prior overflow check. Implicit conversion is forbidden by compiler settings. --- src/stlink-gui/gui.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index a58d59247..d7e74c547 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -301,7 +301,14 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { if (gui->file_mem.memory) { g_free(gui->file_mem.memory); } - gui->file_mem.size = g_file_info_get_size(file_info); + goffset file_size = g_file_info_get_size(file_info); + + if (G_MAXSIZE < file_size) { + stlink_gui_set_info_error_message(gui, "File too large."); + goto out_input; + } + + gui->file_mem.size = (gsize) file_info; gui->file_mem.memory = g_malloc(gui->file_mem.size); for (off = 0; off < (gint)gui->file_mem.size; off += MEM_READ_SIZE) { From d063c1159f0574f143edb42b2a5f05a3f0b20044 Mon Sep 17 00:00:00 2001 From: Marcus Lindemann Date: Sun, 4 Dec 2022 18:11:51 +0100 Subject: [PATCH 1336/1435] Fix GUI compilation fail on OpenBSD i386 Explicitely convert from goffset to gsize with prior overflow check. Implicit conversion is forbidden by compiler settings. --- src/stlink-gui/gui.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index a58d59247..b45f5f126 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -301,7 +301,14 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { if (gui->file_mem.memory) { g_free(gui->file_mem.memory); } - gui->file_mem.size = g_file_info_get_size(file_info); + goffset file_size = g_file_info_get_size(file_info); + + if ((0 > file_size) && (G_MAXSIZE <= file_size)) { + stlink_gui_set_info_error_message(gui, "File too large."); + goto out_input; + } + + gui->file_mem.size = (gsize) file_info; gui->file_mem.memory = g_malloc(gui->file_mem.size); for (off = 0; off < (gint)gui->file_mem.size; off += MEM_READ_SIZE) { From 53e9252cc0c5b348ee7d9cc954c2752168658e34 Mon Sep 17 00:00:00 2001 From: Marcus Lindemann Date: Sun, 4 Dec 2022 18:11:51 +0100 Subject: [PATCH 1337/1435] Resolve merge conflict for diverging branch. Explicitely convert from goffset to gsize with prior overflow check. Implicit conversion is forbidden by compiler settings. --- src/stlink-gui/gui.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index d7e74c547..b45f5f126 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -303,7 +303,7 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { goffset file_size = g_file_info_get_size(file_info); - if (G_MAXSIZE < file_size) { + if ((0 > file_size) && (G_MAXSIZE <= file_size)) { stlink_gui_set_info_error_message(gui, "File too large."); goto out_input; } From 32fc9f11ef044c27bf48b091e9463c3c9f466271 Mon Sep 17 00:00:00 2001 From: Marcus Lindemann Date: Tue, 6 Dec 2022 21:41:07 +0100 Subject: [PATCH 1338/1435] Fix resulting compilation error on Ubuntu --- src/stlink-gui/gui.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index b45f5f126..2bf1f9d32 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -303,7 +303,7 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { goffset file_size = g_file_info_get_size(file_info); - if ((0 > file_size) && (G_MAXSIZE <= file_size)) { + if ((0 > file_size) && ((goffset)G_MAXSIZE <= file_size)) { stlink_gui_set_info_error_message(gui, "File too large."); goto out_input; } From a4105f4ce89a110bd3b1fd168e194f8690f43ee6 Mon Sep 17 00:00:00 2001 From: Phil Date: Sun, 18 Dec 2022 16:27:40 +0100 Subject: [PATCH 1339/1435] Adding device ID for GD32F303VET6 --- doc/devices_boards.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 1a5099b72..06f58fe21 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -89,8 +89,9 @@ Tested non-official ST boards [incl. STLINK programmers]: | Product-Code | Chip-ID | STLINK
      Programmer | Boards | | ------------ | ------- | ---------------------- | ---------------------------------- | -| GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | | GD32F303CGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | +| GD32F303VET6 | 0x414 | [v2] | STM32F303 clone from GigaDevice GD | +| GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | ## STM32F4 / ARM Cortex M4F From 194e6e9c6b9f3f1c40bf5c6b724aff8087fb443e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 28 Dec 2022 22:21:47 +0100 Subject: [PATCH 1340/1435] General project clean-up - Removed orphaned old dev-documentation - Rearranged src files belonging to stlink-lib - Revised & sorted option byte source code - Updated devices_boards.md --- CMakeLists.txt | 18 +- doc/dev/app-example/CMakeLists.txt | 22 - doc/dev/app-example/README.md | 2 - doc/dev/app-example/main.c | 28 - doc/dev/developer.txt | 411 --------- doc/dev/pkg-config/CMakeLists.txt | 15 - doc/dev/pkg-config/pkgconfig.pc.cmake | 11 - doc/devices_boards.md | 7 +- inc/stlink.h | 17 - src/st-flash/flash.c | 1 + src/st-util/gdb-server.c | 1 + src/{ => stlink-lib}/calculate.c | 0 src/{ => stlink-lib}/calculate.h | 0 src/{ => stlink-lib}/common.c | 0 src/{ => stlink-lib}/common.h | 0 src/{ => stlink-lib}/common_flash.c | 1 + src/{ => stlink-lib}/common_flash.h | 0 src/stlink-lib/flash_loader.h | 5 +- src/{ => stlink-lib}/flashloader.c | 1 + src/stlink-lib/flashloader.h | 13 + src/{ => stlink-lib}/map_file.c | 0 src/{ => stlink-lib}/map_file.h | 0 src/{ => stlink-lib}/option_bytes.c | 1210 ++++++++++++------------- src/stlink-lib/option_bytes.h | 21 + src/{ => stlink-lib}/read_write.c | 0 25 files changed, 644 insertions(+), 1140 deletions(-) delete mode 100644 doc/dev/app-example/CMakeLists.txt delete mode 100644 doc/dev/app-example/README.md delete mode 100644 doc/dev/app-example/main.c delete mode 100644 doc/dev/developer.txt delete mode 100644 doc/dev/pkg-config/CMakeLists.txt delete mode 100644 doc/dev/pkg-config/pkgconfig.pc.cmake rename src/{ => stlink-lib}/calculate.c (100%) rename src/{ => stlink-lib}/calculate.h (100%) rename src/{ => stlink-lib}/common.c (100%) rename src/{ => stlink-lib}/common.h (100%) rename src/{ => stlink-lib}/common_flash.c (99%) rename src/{ => stlink-lib}/common_flash.h (100%) rename src/{ => stlink-lib}/flashloader.c (99%) create mode 100644 src/stlink-lib/flashloader.h rename src/{ => stlink-lib}/map_file.c (100%) rename src/{ => stlink-lib}/map_file.h (100%) rename src/{ => stlink-lib}/option_bytes.c (73%) create mode 100644 src/stlink-lib/option_bytes.h rename src/{ => stlink-lib}/read_write.c (100%) diff --git a/CMakeLists.txt b/CMakeLists.txt index 124f12f5a..3a22fdedc 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -170,8 +170,8 @@ add_subdirectory(inc) set(STLINK_HEADERS inc/backend.h inc/stlink.h - src/common_flash.h - src/calculate.h + src/stlink-lib/common_flash.h + src/stlink-lib/calculate.h src/stlink-lib/commands.h src/stlink-lib/libusb_settings.h src/stlink-lib/reg.h @@ -185,13 +185,13 @@ set(STLINK_HEADERS ) set(STLINK_SOURCE - src/read_write.c - src/common.c - src/option_bytes.c - src/common_flash.c - src/map_file.c - src/flashloader.c - src/calculate.c + src/stlink-lib/read_write.c + src/stlink-lib/common.c + src/stlink-lib/option_bytes.c + src/stlink-lib/common_flash.c + src/stlink-lib/map_file.c + src/stlink-lib/flashloader.c + src/stlink-lib/calculate.c src/stlink-lib/chipid.c src/stlink-lib/flash_loader.c src/stlink-lib/logging.c diff --git a/doc/dev/app-example/CMakeLists.txt b/doc/dev/app-example/CMakeLists.txt deleted file mode 100644 index 69ba2090e..000000000 --- a/doc/dev/app-example/CMakeLists.txt +++ /dev/null @@ -1,22 +0,0 @@ -# Warning: This example assumes that you are building on a host with pkg-config available (e.g. linux). -# The logic required to build under windows/mingw was intentionally omitted to keep this CMakeLists as small as possible. - -cmake_minimum_required(VERSION 3.4.2) - -project(st-hello) -set(PROJECT_VERSION 0.1) - -set(SRCS main.c) - -include_directories(${STLINK_INCLUDE_DIRS}) - -find_package(PkgConfig) -pkg_check_modules(STLINK REQUIRED stlink) - -set(CMAKE_C_FLAGS " ${STLINK_CFLAGS_OTHER} -Wall -Werror") - -add_executable(${PROJECT_NAME} ${SRCS}) - -target_link_libraries(${PROJECT_NAME} ${STLINK_LIBRARIES}) - -install(TARGETS ${PROJECT_NAME} DESTINATION ${CMAKE_INSTALL_BINDIR}) diff --git a/doc/dev/app-example/README.md b/doc/dev/app-example/README.md deleted file mode 100644 index f3a0bf9bb..000000000 --- a/doc/dev/app-example/README.md +++ /dev/null @@ -1,2 +0,0 @@ -This is a simple standalone application example that uses libstlink. -It can be used as a boilerplate for app development. diff --git a/doc/dev/app-example/main.c b/doc/dev/app-example/main.c deleted file mode 100644 index b8e64b259..000000000 --- a/doc/dev/app-example/main.c +++ /dev/null @@ -1,28 +0,0 @@ -#include -#include -#include - -static stlink_t *stlink_open_first(void) { - stlink_t* sl = NULL; - sl = stlink_v1_open(0, 1); - if (sl == NULL) - sl = stlink_open_usb(0, 1, NULL); - - return sl; -} - - -int main() { - stlink_t* sl = NULL; - sl = stlink_open_first(); - - if (sl == NULL) { - fprintf(stderr, "Failed to open stlink device ;(\n"); - exit(1); - } - - fprintf(stderr, "STlink device opened, that's cool!\n"); - stlink_close(sl); - - return 0; -} diff --git a/doc/dev/developer.txt b/doc/dev/developer.txt deleted file mode 100644 index e3091c003..000000000 --- a/doc/dev/developer.txt +++ /dev/null @@ -1,411 +0,0 @@ -=== Compilation with pkg-config === - -In order to use pkg-config for development purposes, add the following lines to the toplevel CMakeLists.txt file: - -### -# Additional build tasks -### - -## Package configuration (pkg-config) on unix-based systems -if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) - add_subdirectory(doc/dev/pkg-config) # external tool pkg-config -endif () - -=== Target Identification === - -The following information is available about the target: -- chip id: 0xE0042000 or 0x40015800, primary information to derive flash and sram architection -- core id: Result from the STLINK_DEBUGREADCOREID call, additionally used for flash/sram architection -- cpu id: 0xE000ED00 (CMSIS System Control Block CPU ID), not used in stlink - - -=== Backend === - -The "backend" implements the interface to the adapter hardware. -There are two backends for two different adapters: "sg" (stlink v1?) and "usb" (stlink v2?). - - - -Include stlink/backend.h - typedef struct _stlink_backend { - void (*close) (stlink_t * sl); - int (*exit_debug_mode) (stlink_t * sl); - int (*enter_swd_mode) (stlink_t * sl); - int (*enter_jtag_mode) (stlink_t * stl); - int (*exit_dfu_mode) (stlink_t * stl); - int (*core_id) (stlink_t * stl); - int (*reset) (stlink_t * stl); - int (*jtag_reset) (stlink_t * stl, int value); - int (*run) (stlink_t * stl); - int (*status) (stlink_t * stl); - int (*version) (stlink_t *sl); - int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); - int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); - int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*read_all_regs) (stlink_t *sl, struct stlink_reg * regp); - int (*read_reg) (stlink_t *sl, int r_idx, struct stlink_reg * regp); - int (*read_all_unsupported_regs) (stlink_t *sl, struct stlink_reg *regp); - int (*read_unsupported_reg) (stlink_t *sl, int r_idx, struct stlink_reg *regp); - int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, struct stlink_reg *regp); - int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); - int (*step) (stlink_t * stl); - int (*current_mode) (stlink_t * stl); - int (*force_debug) (stlink_t *sl); - int32_t (*target_voltage) (stlink_t *sl); - int (*set_swdclk) (stlink_t * stl, uint16_t divisor); - } stlink_backend_t; - -Descriptions below describe the actions of the usb.h backend: - -void (*close) (stlink_t * sl); -int (*exit_debug_mode) (stlink_t * sl); - __stlink_usb_exit_debug_mode: Send STLINK_DEBUG_EXIT - returns -1 or 0 - -int (*enter_swd_mode) (stlink_t * sl); - _stlink_usb_enter_swd_mode: Send STLINK_DEBUG_ENTER+STLINK_DEBUG_ENTER_SWD - returns -1 or 0 - -int (*enter_jtag_mode) (stlink_t * stl); - -int (*exit_dfu_mode) (stlink_t * stl); - _stlink_usb_exit_dfu_mode: Send STLINK_DFU_EXIT - returns -1 or 0 - -int (*core_id) (stlink_t * stl); - _stlink_usb_core_id: Assign the result from STLINK_DEBUG_READCOREID to stl->core_id - returns -1 or 0 - -int (*reset) (stlink_t * stl); - _stlink_usb_reset: Send STLINK_DEBUG_RESETSYS and reset via AIRCR - AIRCR is part of the CMSIS System Control Block (SCB), which is located in - the System Control Space at 0xE000ED0C - returns -1 or 0 ? - -int (*jtag_reset) (stlink_t * stl, int value); - _stlink_usb_jtag_reset: Send STLINK_JTAG_DRIVE_NRST. - "value" is sent as argument for STLINK_JTAG_DRIVE_NRST and probably contains - the status of the NRST line (0: low, 1: high). Also the value 2 is used in the software. - returns -1 or 0 - -int (*run) (stlink_t * stl); - _stlink_usb_run: Send STLINK_DEBUG_RUNCORE - returns -1 or 0 - -int (*status) (stlink_t * stl); - _stlink_usb_status: Assign the result from STLINK_DEBUG_GETSTATUS to stl->q_len - returns -1 or 0 - -int (*version) (stlink_t *sl); - _stlink_usb_version: Read version with STLINK_GET_VERSION. - Result is stored in sl->q_buf (6 bytes????) - returns -1 or 0 - -int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); - _stlink_usb_read_debug32: Send STLINK_JTAG_READDEBUG_32BIT - to read 32 bits from "addr". The result data is stored at "*data". - returns -1 or 0 - -int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - _stlink_usb_read_mem32: Use STLINK_DEBUG_READMEM_32BIT - to read "len" bytes from "addr" - Result is returned in sl->q_buf, sl->q_len returns the size of the data (should be - equal to "len"???). - returns -1 or 0 - -int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); - _stlink_usb_write_debug32: Use STLINK_JTAG_WRITEDEBUG_32BIT - to store "data" at "addr" - returns -1 or 0 - -int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - _stlink_usb_write_mem32: Use STLINK_DEBUG_WRITEMEM_32BIT to - send data stored in sl->q_buf to the target at "addr". - "len" is the size data (???? not clear whether this are bytes ) - returns -1 or 0 - -int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); - _stlink_usb_write_mem8: Use STLINK_DEBUG_WRITEMEM_8BIT to - send data stored in sl->q_buf to the target at "addr". - "len" is the size in bytes (probably). - returns -1 or 0 - -int (*read_all_regs) (stlink_t *sl, struct stlink_reg * regp); - _stlink_usb_read_all_regs: Send STLINK_DEBUG_READALLREGS to read - all register values and store them into *regp; - returns -1 or 0 - -int (*read_reg) (stlink_t *sl, int r_idx, struct stlink_reg * regp); - _stlink_usb_read_reg: Send STLINK_DEBUG_READREG to read specific register "r_idx". - The result is then stored in *regp in the correct register. - Example if "r_idx" is 18, then the result is stored in regp->process_sp - returns -1 or 0 - -int (*read_all_unsupported_regs) (stlink_t *sl, struct stlink_reg *regp); - _stlink_usb_read_all_unsupported_regs: Calls "_stlink_usb_read_unsupported_reg" - (see below) to read all registers. - returns -1 or 0 - -int (*read_unsupported_reg) (stlink_t *sl, int r_idx, struct stlink_reg *regp); - _stlink_usb_read_unsupported_reg Use DCRSR and DCRDR to access some - of the internal registers (primask, basepri, faultmask, control, fpscr). - Also will fill regp->s (???) for some specific "r_idx" values. - WARNING: Some r_idx values may lead to a out of array bound problem in C. - returns -1 or 0 - -int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, struct stlink_reg *regp); - _stlink_usb_write_unsupported_reg: - Updates one of the following registers: - primask (idx=0x1c), basepri (idx=0x1d), faultmask (idx=0x1e), control (idx=0x1f) - The new value is given as "value" as fn argument. - Corresponding values are refreshed in regp, however the old value for is kept in regp: - If basepri has to be updated (idx=0x1d), then all register values are fetched and - basepri is updated in the core, but not in *regp (BUG???). - returns -1 or 0 - -int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); - _stlink_usb_write_reg: Use STLINK_DEBUG_WRITEREG to update register "idx" - with value "reg". - returns -1 or 0 - -int (*step) (stlink_t * stl); - _stlink_usb_step: Send STLINK_DEBUG_STEPCORE - returns -1 or 0 - -int (*current_mode) (stlink_t * stl); - _stlink_usb_current_mode: Send STLINK_GET_CURRENT_MODE and return - the current mode. - returns -1 or the value for the current mode. - Modes probably are: - STLINK_DEV_DFU_MODE 0x00 - STLINK_DEV_MASS_MODE 0x01 - STLINK_DEV_DEBUG_MODE 0x02 - -int (*force_debug) (stlink_t *sl); - _stlink_usb_force_debug: Sends STLINK_DEBUG_FORCEDEBUG. No other side effects - returns -1 or 0 - -int32_t (*target_voltage) (stlink_t *sl); - _stlink_usb_target_voltage: Send STLINK_GET_TARGET_VOLTAGE - returns -1 or the target voltage. (??? dimension is not clear...) - -int (*set_swdclk) (stlink_t * stl, uint16_t divisor); - _stlink_usb_set_swdclk: Send STLINK_DEBUG_APIV2_SWD_SET_FREQ and "divisor" value - returns -1 or 0 - - -=== Other Functions === - - -Include: stlink.h - - -Prototype: void stlink_close(stlink_t *sl); -Include: inc/stlink.h -Definition: src/common.c -Description: - Calls the backend "close" procedure and frees 'sl' -Backend: "close" -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() -Return: - - -Include: inc/stlink.h -Prototype: int stlink_core_id(stlink_t *sl); -Definition: src/common.c -Description: - Calls the backend "core_id", calls stlink_print_data() on higher verbose levels. - Assigns the core id returned by STLINK_DEBUGREADCOREID to sl->core_id - Only some specific core ids are used: See include/stm32.h - Usage includes the selection of the correct flash algorithm. -Backend: "core_id" -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() -Return: -1 for error. 0 for success. - -Include: inc/stlink.h -Prototype: int stlink_reset(stlink_t *sl); -Definition: src/common.c -Description: - Just calls the backend "reset" procedure (reset via STLINK_DEBUG_RESETSYS - and reset via AIRCR register at 0xE000ED0C) -Backend: "reset" -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() -Return: -1 for error. 0 for success. - -Include: inc/stlink.h -Prototype: int stlink_jtag_reset(stlink_t *sl, int value); -Definition: src/common.c -Description: - Just calls the backend "jtag_reset" procedure -Backend: "jtag_reset" -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() - value: 0: drive low, 1: drive high, 2: pulse -Return: -1 for error. 0 for success. - - -Include: inc/stlink.h -Prototype: int stlink_run(stlink_t *sl, enum run_type type); -Definition: src/common.c -Description: - Just calls the backend "run" procedure. -Backend: "run" -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() - type: RUN_NORMAL - run target, RUN_FLASH_LOADER - run target with masking interrupts -Return: -1 for error. 0 for success. - -Include: inc/stlink.h -Prototype: int stlink_status(stlink_t *sl); -Definition: src/common.c -Description: - Calls the backend "status" procedure and the procedure "stlink_core_stat()" to - store the status in "sl->core_stat". Possible value for "sl->core_stat" are: - STLINK_CORE_RUNNING - STLINK_CORE_HALTED - STLINK_CORE_STAT_UNKNOWN -Backend: "status" -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() -Return: -1 for error. 0 for success. - - -Include: inc/stlink.h -Prototype: int stlink_version(stlink_t *sl); -Definition: src/common.c -Description: - Calls the backend "version" procedure, parses the result and puts the result into sl->version - This version probably refers to the version of the adapter. -Backend: "version" -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() -Return: -1 for error. 0 for success. - - - int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); - int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); - int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); - int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); - int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); - int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); - int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); - int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); - int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); - int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, struct stlink_reg *regp); - int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); - int stlink_step(stlink_t *sl); - int stlink_current_mode(stlink_t *sl); - int stlink_force_debug(stlink_t *sl); - int stlink_target_voltage(stlink_t *sl); - int stlink_set_swdclk(stlink_t *sl, int freq_khz); - - int stlink_erase_flash_mass(stlink_t* sl); - int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); - int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); - uint8_t stlink_get_erased_pattern(stlink_t *sl); - int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); - int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_fwrite_option_bytes_32bit(stlink_t *sl,uint32_t val); - int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); - int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); - int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); - -Include: inc/stlink.h -Prototype: int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); -Definition: src/common.c -Description: - Tries to read out the chip id via memory read from the device. - Note: sl->chip_id is NOT updated by this procedure. Instead this happens in stlink_load_device_params(): - Do not call this function, but instead call stlink_load_device_params() -Backend: - -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() - chip_id: Pointer. Result is stored via this pointer. -Return: -1 for error. 0 for success. - - -Include: inc/stlink.h -Prototype: int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); -Definition: src/common.c -Description: - Reads the CPU id from STLINK_REG_CM3_CPUID (0xE000ED00, first value of - the SCB, system control block) and splits this into - cpuid->implementer_id - cpuid->variant - cpuid->part - cpuid->revision - The result is not used in the tools, but only in the usb test program. -Backend: - -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() - cpuid: Pointer. Result is stored via this pointer. -Return: -1 for error. 0 for success. - - - - - int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); - uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); - uint16_t read_uint16(const unsigned char *c, const int pt); - void stlink_core_stat(stlink_t *sl); - - -Include: inc/stlink.h -Prototype: void stlink_print_data(stlink_t *sl); -Definition: src/common.c -Description: - If debug logging is enabled: Print the HEX content of the q_buf array. - q_buf will contain the result of the last "backend" command. -Backend: - -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() -Return: - - - - unsigned int is_bigendian(void); - uint32_t read_uint32(const unsigned char *c, const int pt); - void write_uint32(unsigned char* buf, uint32_t ui); - void write_uint16(unsigned char* buf, uint16_t ui); - bool stlink_is_core_halted(stlink_t *sl); - int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); - int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); - int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); - - -Include: inc/stlink.h -Prototype: int stlink_load_device_params(stlink_t *sl); -Definition: src/common.c -Description: - This is one of the most important procedures. It will get all the device info - and store the results in the "sl" structure. Many other procedures will depend - on this information. - The identification is based on the stlink_chip_id() result and the flash_size register value -Backend: - -Arguments: - sl: Pointer to the stlink data structure, returned by stlink_v1_open() or stlink_open_usb() -Return: -1 for error. 0 for success. - - int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t* option_byte); - int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t* option_byte); - - -Include "flash_loader.h" - -int stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); -int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); -int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); - - -Inlcude "sg.h" -stlink_t* stlink_v1_open(const int verbose, int reset); - -Include "usb.h" - -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, bool reset, char serial[STLINK_SERIAL_MAX_SIZE]); -size_t stlink_probe_usb(stlink_t **stdevs[]); -void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); diff --git a/doc/dev/pkg-config/CMakeLists.txt b/doc/dev/pkg-config/CMakeLists.txt deleted file mode 100644 index 53870fee4..000000000 --- a/doc/dev/pkg-config/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -set(PKG_CONFIG_LIBDIR "\${prefix}/lib/\${deb_host_multiarch}") -set(PKG_CONFIG_INCLUDEDIR "\${prefix}/include/\${deb_host_multiarch}/${PROJECT_NAME}") -set(PKG_CONFIG_LIBS "-L\${libdir} -l:libstlink.so.${PROJECT_VERSION_MAJOR}") -set(PKG_CONFIG_CFLAGS "-I\${includedir}") -set(PKG_CONFIG_REQUIRES "libusb-1.0") - -configure_file( - "${CMAKE_CURRENT_SOURCE_DIR}/pkgconfig.pc.cmake" - "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" - ) - -install( - FILES "${CMAKE_CURRENT_BINARY_DIR}/${PROJECT_NAME}.pc" - DESTINATION ${STLINK_LIBRARY_PATH}/pkgconfig - ) diff --git a/doc/dev/pkg-config/pkgconfig.pc.cmake b/doc/dev/pkg-config/pkgconfig.pc.cmake deleted file mode 100644 index 4f881daec..000000000 --- a/doc/dev/pkg-config/pkgconfig.pc.cmake +++ /dev/null @@ -1,11 +0,0 @@ -prefix=${CMAKE_INSTALL_PREFIX} -deb_host_multiarch=${CMAKE_LIBRARY_PATH} -libdir=${PKG_CONFIG_LIBDIR} -includedir=${PKG_CONFIG_INCLUDEDIR} - -Name: ${PROJECT_NAME} -Description: ${PROJECT_DESCRIPTION} -Version: ${PROJECT_VERSION} -Libs: ${PKG_CONFIG_LIBS} -Cflags: ${PKG_CONFIG_CFLAGS} -Requires: ${PKG_CONFIG_REQUIRES} diff --git a/doc/devices_boards.md b/doc/devices_boards.md index 1a5099b72..feab9ffa9 100644 --- a/doc/devices_boards.md +++ b/doc/devices_boards.md @@ -53,10 +53,9 @@ Tested non-official ST boards [incl. STLINK programmers]: ## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) [may work, but without support!] -| Product-Code | Chip-ID | STLink
      Programmer | Boards | -| ------------- | ------- | ---------------------- | ----------------------------------------------------------------------------------------------- | -| CKS32F103C8Tx | 0x410 | v2 | "STM32"-Bluepill ( _**Fake-Marking !**_ )
      STM32F103C8T6 clone from China Key Systems (CKS) | -| CKS32F103C8Tx | 0x410 | v2 | CKS32-Bluepill (Clone)
      STM32F103C8T6 clone from China Key Systems (CKS) | +| Product-Code | Chip-ID | STLink
      Programmer | Boards | +| ------------- | ------- | ---------------------- | ------------------------------------------------------------------------------------------------------------------------------------ | +| CKS32F103C8Tx | 0x410 | v2 | STM32F103C8T6 clone from China Key Systems (CKS) either as
      CKS32-Bluepill or even as "STM32"-Bluepill with _**Fake-Marking !**_ | ## STM32F3 / ARM Cortex M4F diff --git a/inc/stlink.h b/inc/stlink.h index 17601fda8..b9379e03d 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -296,23 +296,6 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); int stlink_load_device_params(stlink_t *sl); -int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte); - -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); -int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); -int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_control_register); -int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_control_register1); - -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); - -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); - int stlink_target_connect(stlink_t *sl, enum connect_type connect); #include diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 058501ad6..0985c75c2 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -11,6 +11,7 @@ #include #include #include "flash.h" +#include "option_bytes.h" static stlink_t *connected_stlink = NULL; diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index cef79ddc1..802e23c06 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -28,6 +28,7 @@ #include #include #include +#include "flashloader.h" #include "gdb-remote.h" #include "gdb-server.h" #include "semihosting.h" diff --git a/src/calculate.c b/src/stlink-lib/calculate.c similarity index 100% rename from src/calculate.c rename to src/stlink-lib/calculate.c diff --git a/src/calculate.h b/src/stlink-lib/calculate.h similarity index 100% rename from src/calculate.h rename to src/stlink-lib/calculate.h diff --git a/src/common.c b/src/stlink-lib/common.c similarity index 100% rename from src/common.c rename to src/stlink-lib/common.c diff --git a/src/common.h b/src/stlink-lib/common.h similarity index 100% rename from src/common.h rename to src/stlink-lib/common.h diff --git a/src/common_flash.c b/src/stlink-lib/common_flash.c similarity index 99% rename from src/common_flash.c rename to src/stlink-lib/common_flash.c index 17352974c..b21929ddf 100644 --- a/src/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -3,6 +3,7 @@ #include #include #include "calculate.h" +#include "flashloader.h" #include "common_flash.h" #include "map_file.h" #include "common.h" diff --git a/src/common_flash.h b/src/stlink-lib/common_flash.h similarity index 100% rename from src/common_flash.h rename to src/stlink-lib/common_flash.h diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 85b92bef3..368b6ab8b 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -1,8 +1,7 @@ /* - * File: stlink.h + * File: flash_loader.h * - * This should contain all the common top level stlink interfaces, - * regardless of how the backend does the work.... + * Flash loader */ #ifndef STLINK_FLASH_LOADER_H_ diff --git a/src/flashloader.c b/src/stlink-lib/flashloader.c similarity index 99% rename from src/flashloader.c rename to src/stlink-lib/flashloader.c index b9c26bf4c..abb140fdd 100644 --- a/src/flashloader.c +++ b/src/stlink-lib/flashloader.c @@ -1,6 +1,7 @@ #include #include #include +#include "flashloader.h" #include "common_flash.h" #define L1_WRITE_BLOCK_SIZE 0x80 diff --git a/src/stlink-lib/flashloader.h b/src/stlink-lib/flashloader.h new file mode 100644 index 000000000..ff16d183c --- /dev/null +++ b/src/stlink-lib/flashloader.h @@ -0,0 +1,13 @@ +/* + * File: flashloader.h + * + * Flash loader + */ + +#include +#include + +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); + diff --git a/src/map_file.c b/src/stlink-lib/map_file.c similarity index 100% rename from src/map_file.c rename to src/stlink-lib/map_file.c diff --git a/src/map_file.h b/src/stlink-lib/map_file.h similarity index 100% rename from src/map_file.h rename to src/stlink-lib/map_file.h diff --git a/src/option_bytes.c b/src/stlink-lib/option_bytes.c similarity index 73% rename from src/option_bytes.c rename to src/stlink-lib/option_bytes.c index c1a418232..44cd3930b 100644 --- a/src/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -1,152 +1,32 @@ #include #include #include +#include "option_bytes.h" #include "common_flash.h" #include "map_file.h" #include "common.h" -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_Gx(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_Gx(sl, option_byte); -} - -/** - * Read first option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { - DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); - return stlink_read_debug32(sl, sl->option_base, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f2(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_f2(sl, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f4(stlink_t *sl, - uint32_t *option_byte) { - return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_option_control_register_f4(sl, option_byte); -} /** - * Read option bytes + * Read option control register F0 * @param sl - * @param option_byte value to read + * @param option_byte * @return 0 on success, -ve on failure. - * - * Since multiple bytes can be read, we read and print all but one here - * and then return the last one just like other devices */ -int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { - int err = -1; - for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { - err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), - option_byte); - if (err == -1) { - return err; - } else { - printf("%08x\n", *option_byte); - } - } - - return stlink_read_debug32( - sl, - sl->option_base + (uint32_t)(sl->option_size / 4 - 1) * sizeof(uint32_t), - option_byte); -} - -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); - return (-1); - } - - switch (sl->chip_id) { - case STM32_CHIPID_F2: - return stlink_read_option_bytes_f2(sl, option_byte); - case STM32_CHIPID_F4: - case STM32_CHIPID_F446: - return stlink_read_option_bytes_f4(sl, option_byte); - case STM32_CHIPID_F76xxx: - return stlink_read_option_bytes_f7(sl, option_byte); - case STM32_CHIPID_G0_CAT1: - case STM32_CHIPID_G0_CAT2: - case STM32_CHIPID_G4_CAT2: - case STM32_CHIPID_G4_CAT3: - return stlink_read_option_bytes_Gx(sl, option_byte); - default: - return stlink_read_option_bytes_generic(sl, option_byte); - } +int stlink_read_option_control_register_f0(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); + return stlink_read_debug32(sl, FLASH_OBR, option_byte); } - /** - * Write option bytes + * Write option bytes F0 * @param sl - * @param base option bytes to write * @param addr of the memory mapped option bytes - * @param len of options bytes to write + * @param base option bytes + * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f0( - stlink_t *sl, uint8_t* base, stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_f0(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { int ret = 0; if (len < 12 || addr != STM32_F0_OPTION_BYTES_BASE) { @@ -196,133 +76,139 @@ static int stlink_write_option_bytes_f0( } /** - * Write option bytes + * Write option control register F0 * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write + * @param option_cr * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - /* Write options bytes */ - uint32_t val; +static int stlink_write_option_control_register_f0(stlink_t *sl, uint32_t option_cr) { int ret = 0; - (void)len; - uint32_t data; + uint16_t opt_val[8]; + unsigned protection, optiondata; + uint16_t user_options, user_data, rdp; + unsigned option_offset, user_data_offset; + + ILOG("Asked to write option control register %#10x to %#010x.\n", option_cr, FLASH_OBR); + /* Clear errors */ clear_flash_error(sl); - write_uint32((unsigned char *)&data, *(uint32_t *)(base)); - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); + /* Retrieve current values */ + ret = stlink_read_debug32(sl, FLASH_OBR, &optiondata); + if (ret) { + return ret; + } + ret = stlink_read_debug32(sl, FLASH_WRPR, &protection); + if (ret) { + return ret; + } - // Set Options Start bit - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + /* Translate OBR value to flash store structure + * F0: RM0091, Option byte description, pp. 75-78 + * F1: PM0075, Option byte description, pp. 19-22 + * F3: RM0316, Option byte description, pp. 85-87 */ + switch(sl->chip_id) + { + case 0x422: /* STM32F30x */ + case 0x432: /* STM32F37x */ + case 0x438: /* STM32F303x6/8 and STM32F328 */ + case 0x446: /* STM32F303xD/E and STM32F398xE */ + case 0x439: /* STM32F302x6/8 */ + case 0x440: /* STM32F05x */ + case 0x444: /* STM32F03x */ + case 0x445: /* STM32F04x */ + case 0x448: /* STM32F07x */ + case 0x442: /* STM32F09x */ + option_offset = 6; + user_data_offset = 16; + rdp = 0x55AA; + break; + default: + option_offset = 0; + user_data_offset = 10; + rdp = 0x5AA5; + break; + } - wait_flash_busy(sl); + user_options = (option_cr >> option_offset >> 2) & 0xFFFF; + user_data = (option_cr >> user_data_offset) & 0xFFFF; - ret = check_flash_error(sl); +#define VAL_WITH_COMPLEMENT(v) (uint16_t)(((v)&0xFF) | (((~(v))<<8)&0xFF00)) - // Reload options - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + opt_val[0] = (option_cr & (1 << 1/*OPT_READOUT*/)) ? 0xFFFF : rdp; + opt_val[1] = VAL_WITH_COMPLEMENT(user_options); + opt_val[2] = VAL_WITH_COMPLEMENT(user_data); + opt_val[3] = VAL_WITH_COMPLEMENT(user_data >> 8); + opt_val[4] = VAL_WITH_COMPLEMENT(protection); + opt_val[5] = VAL_WITH_COMPLEMENT(protection >> 8); + opt_val[6] = VAL_WITH_COMPLEMENT(protection >> 16); + opt_val[7] = VAL_WITH_COMPLEMENT(protection >> 24); - return (ret); +#undef VAL_WITH_COMPLEMENT + + /* Write bytes and check errors */ + ret = stlink_write_option_bytes_f0(sl, STM32_F0_OPTION_BYTES_BASE, (uint8_t*)opt_val, sizeof(opt_val)); + if (ret) + return ret; + + ret = check_flash_error(sl); + if (!ret) { + ILOG("Wrote option bytes %#010x to %#010x!\n", option_cr, + FLASH_OBR); + } + + return ret; } /** - * Write option bytes + * Read option control register F2 * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write + * @param option_byte * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - uint32_t flash_base = get_stm32l0_flash_base(sl); - uint32_t val; - uint32_t data; - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - while (len != 0) { - write_uint32((unsigned char *)&data, - *(uint32_t *)(base)); // write options bytes - - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, addr, data); - wait_flash_busy(sl); - - if ((ret = check_flash_error(sl))) { - break; - } - - len -= 4; - addr += 4; - base += 4; - } - - // Reload options - stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); - val |= (1 << STM32L0_FLASH_OBL_LAUNCH); - stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); - - return (ret); +int stlink_read_option_control_register_f2(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); } /** - * Write option bytes + * Read option bytes F2 * @param sl - * @param addr of the memory mapped option bytes - * @param base option bytes to write + * @param option_byte * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { - - uint32_t val; - int ret = 0; - (void)addr; - (void)len; - - // Clear errors - clear_flash_error(sl); - - // write options bytes - uint32_t data; - write_uint32((unsigned char *)&data, *(uint32_t *)(base)); - WLOG("Writing option bytes 0x%04x\n", data); - stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); - - // set options start bit - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); - - wait_flash_busy(sl); - ret = check_flash_error(sl); +int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f2(sl, option_byte); +} - // apply options bytes immediate - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); +/** + * Read option control register F4 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f4(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); +} - return (ret); +/** + * Read option bytes F4 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_f4(sl, option_byte); } /** - * Write option bytes + * Write option bytes F4 * @param sl - * @param option_byte value to write + * @param addr of the memory mapped option bytes + * @param base option bytes + * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_f4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t option_byte; int ret = 0; (void)addr; @@ -346,13 +232,40 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t *base, } /** - * Write option bytes + * Read option bytes F7 * @param sl - * @param option_byte value to write + * @param option_byte * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { +// Since multiple bytes can be read, we read and print all, but one here +// and then return the last one just like other devices. +int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { + int err = -1; + for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { + err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), + option_byte); + if (err == -1) { + return err; + } else { + printf("%08x\n", *option_byte); + } + } + + return stlink_read_debug32( + sl, + sl->option_base + (uint32_t)(sl->option_size / 4 - 1) * sizeof(uint32_t), + option_byte); +} + +/** + * Write option bytes F7 + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes + * @param len of option bytes + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t option_byte; int ret = 0; @@ -392,25 +305,193 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t *base, wait_flash_busy(sl); ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, - addr); + if (!ret) + ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, + addr); + + /* option bytes are reloaded at reset only, no obl. */ + + return ret; +} + +/** + * Read option control register F7 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_f7(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); + return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); +} + +/** + * Write option control register F7 + * @param sl + * @param option_cr + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option_cr) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", + option_cr, FLASH_F7_OPTCR); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, FLASH_F7_OPTCR, + (option_cr & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_cr, + FLASH_F7_OPTCR); + + return ret; +} + +/** + * Read option control register1 F7 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option control register 1 byte from %#10x\n", + FLASH_F7_OPTCR1); + return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); +} + +/** + * Write option control register1 F7 + * @param sl + * @param option_cr1 + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t option_cr1) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#010x to %#010x.\n", + option_cr1, FLASH_F7_OPTCR1); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + uint32_t current_control_register_value; + stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); + + /* write option byte */ + stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_cr1); + stlink_write_debug32( + sl, FLASH_F7_OPTCR, + (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | + (1 << FLASH_F7_OPTCR_START)); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_cr1, FLASH_F7_OPTCR1); + + return ret; +} + +/** + * Read option bytes boot address F7 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option byte boot address\n"); + return stlink_read_option_control_register1_f7(sl, option_byte); +} + +/** + * Write option bytes boot address F7 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +static int +stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_add) { + ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); + return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); +} + +/** + * Read option control register Gx + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_gx(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); +} + +/** + * Read option bytes Gx + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_gx(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_gx(sl, option_byte); +} + +/** + * Write option bytes Gx + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes + * @param len of option bytes + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_gx(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { + /* Write options bytes */ + uint32_t val; + int ret = 0; + (void)len; + uint32_t data; + + clear_flash_error(sl); + + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); + + // Set Options Start bit + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); - /* option bytes are reloaded at reset only, no obl. */ + // Reload options + stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); - return ret; + return (ret); } /** - * Write STM32H7xx option bytes + * Write option bytes H7 * @param sl - * @param base option bytes to write * @param addr of the memory mapped option bytes - * @param len number of bytes to write (must be multiple of 4) + * @param base option bytes + * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t val; uint32_t data; @@ -473,14 +554,96 @@ static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, } /** - * Write option bytes + * Write option bytes L0 + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes + * @param len of option bytes + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_l0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { + uint32_t flash_base = get_stm32l0_flash_base(sl); + uint32_t val; + uint32_t data; + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + while (len != 0) { + write_uint32((unsigned char *)&data, + *(uint32_t *)(base)); // write options bytes + + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, addr, data); + wait_flash_busy(sl); + + if ((ret = check_flash_error(sl))) { + break; + } + + len -= 4; + addr += 4; + base += 4; + } + + // Reload options + stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); + val |= (1 << STM32L0_FLASH_OBL_LAUNCH); + stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); + + return (ret); +} + +/** + * Write option bytes L4 + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes + * @param len of option bytes + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_bytes_l4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { + + uint32_t val; + int ret = 0; + (void)addr; + (void)len; + + // Clear errors + clear_flash_error(sl); + + // write options bytes + uint32_t data; + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes 0x%04x\n", data); + stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); + + // set options start bit + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + + wait_flash_busy(sl); + ret = check_flash_error(sl); + + // apply options bytes immediate + stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); + val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); + stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + + return (ret); +} + +/** + * Write option bytes WB * @param sl * @param addr of the memory mapped option bytes - * @param base option bytes to write + * @param base option bytes + * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_wb(stlink_t *sl, uint8_t *base, - stm32_addr_t addr, uint32_t len) { +static int stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { /* Write options bytes */ uint32_t val; int ret = 0; @@ -490,8 +653,7 @@ static int stlink_write_option_bytes_wb(stlink_t *sl, uint8_t *base, clear_flash_error(sl); while (len != 0) { - write_uint32((unsigned char *)&data, - *(uint32_t *)(base)); // write options bytes + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); // write options bytes WLOG("Writing option bytes %#10x to %#10x\n", data, addr); stlink_write_debug32(sl, addr, data); @@ -523,15 +685,71 @@ static int stlink_write_option_bytes_wb(stlink_t *sl, uint8_t *base, return (ret); } +/** + * Read option control register WB + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_control_register_wb(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option control register byte from %#10x\n", STM32WB_FLASH_OPTR); + return stlink_read_debug32(sl, STM32WB_FLASH_OPTR, option_byte); +} + +/** + * Write option control register WB + * @param sl + * @param option_cr + * @return 0 on success, -ve on failure. + */ +static int stlink_write_option_control_register_wb(stlink_t *sl, uint32_t option_cr) { + int ret = 0; + + // Clear errors + clear_flash_error(sl); + + ILOG("Asked to write option control register 1 %#10x to %#010x.\n", + option_cr, STM32WB_FLASH_OPTR); + + /* write option byte, ensuring we dont lock opt, and set strt bit */ + stlink_write_debug32(sl, STM32WB_FLASH_OPTR, option_cr); + + wait_flash_busy(sl); + + // Set Options Start bit + uint32_t val = (1 << STM32WB_FLASH_CR_OPTSTRT); + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + if (!ret) + ILOG("Wrote option bytes %#010x to %#010x!\n", option_cr, STM32WB_FLASH_OPTR); + + return ret; +} + +/** + * Read option bytes generic + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { + DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); + return stlink_read_debug32(sl, sl->option_base, option_byte); +} + + /** * Write option bytes * @param sl * @param addr of the memory mapped option bytes - * @param base option bytes to write + * @param base option bytes + * @param len of option bytes * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len) { +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { int ret = -1; if (sl->option_base == 0) { @@ -566,29 +784,29 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, switch (sl->flash_type) { case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: - ret = stlink_write_option_bytes_f0(sl, base, addr, len); + ret = stlink_write_option_bytes_f0(sl, addr, base, len); break; case STM32_FLASH_TYPE_F2_F4: - ret = stlink_write_option_bytes_f4(sl, base, addr, len); + ret = stlink_write_option_bytes_f4(sl, addr, base, len); break; case STM32_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_f7(sl, base, addr, len); + ret = stlink_write_option_bytes_f7(sl, addr, base, len); break; case STM32_FLASH_TYPE_L0_L1: - ret = stlink_write_option_bytes_l0(sl, base, addr, len); + ret = stlink_write_option_bytes_l0(sl, addr, base, len); break; case STM32_FLASH_TYPE_L4_L4P: - ret = stlink_write_option_bytes_l4(sl, base, addr, len); + ret = stlink_write_option_bytes_l4(sl, addr, base, len); break; case STM32_FLASH_TYPE_G0: case STM32_FLASH_TYPE_G4: - ret = stlink_write_option_bytes_gx(sl, base, addr, len); + ret = stlink_write_option_bytes_gx(sl, addr, base, len); break; case STM32_FLASH_TYPE_H7: - ret = stlink_write_option_bytes_h7(sl, base, addr, len); + ret = stlink_write_option_bytes_h7(sl, addr, base, len); break; case STM32_FLASH_TYPE_WB_WL: - ret = stlink_write_option_bytes_wb(sl, base, addr, len); + ret = stlink_write_option_bytes_wb(sl, addr, base, len); break; default: ELOG("Option bytes writing is currently not implemented for connected " @@ -603,216 +821,72 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } /* Re-lock flash. */ - lock_flash_option(sl); - lock_flash(sl); - - return ret; -} - - -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_control_register_f0(stlink_t *sl, - uint32_t option_control_register) { - int ret = 0; - uint16_t opt_val[8]; - unsigned protection, optiondata; - uint16_t user_options, user_data, rdp; - unsigned option_offset, user_data_offset; - - ILOG("Asked to write option control register %#10x to %#010x.\n", - option_control_register, FLASH_OBR); - - /* Clear errors */ - clear_flash_error(sl); - - /* Retrieve current values */ - ret = stlink_read_debug32(sl, FLASH_OBR, &optiondata); - if (ret) { - return ret; - } - ret = stlink_read_debug32(sl, FLASH_WRPR, &protection); - if (ret) { - return ret; - } - - /* Translate OBR value to flash store structure - * F0: RM0091, Option byte description, pp. 75-78 - * F1: PM0075, Option byte description, pp. 19-22 - * F3: RM0316, Option byte description, pp. 85-87 */ - switch(sl->chip_id) - { - case 0x422: /* STM32F30x */ - case 0x432: /* STM32F37x */ - case 0x438: /* STM32F303x6/8 and STM32F328 */ - case 0x446: /* STM32F303xD/E and STM32F398xE */ - case 0x439: /* STM32F302x6/8 */ - case 0x440: /* STM32F05x */ - case 0x444: /* STM32F03x */ - case 0x445: /* STM32F04x */ - case 0x448: /* STM32F07x */ - case 0x442: /* STM32F09x */ - option_offset = 6; - user_data_offset = 16; - rdp = 0x55AA; - break; - default: - option_offset = 0; - user_data_offset = 10; - rdp = 0x5AA5; - break; - } - - user_options = (option_control_register >> option_offset >> 2) & 0xFFFF; - user_data = (option_control_register >> user_data_offset) & 0xFFFF; - -#define VAL_WITH_COMPLEMENT(v) (uint16_t)(((v)&0xFF) | (((~(v))<<8)&0xFF00)) - - opt_val[0] = (option_control_register & (1 << 1/*OPT_READOUT*/)) ? 0xFFFF : rdp; - opt_val[1] = VAL_WITH_COMPLEMENT(user_options); - opt_val[2] = VAL_WITH_COMPLEMENT(user_data); - opt_val[3] = VAL_WITH_COMPLEMENT(user_data >> 8); - opt_val[4] = VAL_WITH_COMPLEMENT(protection); - opt_val[5] = VAL_WITH_COMPLEMENT(protection >> 8); - opt_val[6] = VAL_WITH_COMPLEMENT(protection >> 16); - opt_val[7] = VAL_WITH_COMPLEMENT(protection >> 24); - -#undef VAL_WITH_COMPLEMENT - - /* Write bytes and check errors */ - ret = stlink_write_option_bytes_f0(sl, (uint8_t*)opt_val, STM32_F0_OPTION_BYTES_BASE, sizeof(opt_val)); - if (ret) - return ret; - - ret = check_flash_error(sl); - if (!ret) { - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, - FLASH_OBR); - } - - return ret; -} - - -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_control_register1_f7(stlink_t *sl, - uint32_t option_control_register1) { - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - ILOG("Asked to write option control register 1 %#010x to %#010x.\n", - option_control_register1, FLASH_F7_OPTCR1); - - /* write option byte, ensuring we dont lock opt, and set strt bit */ - uint32_t current_control_register_value; - stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); - - /* write option byte */ - stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); - stlink_write_debug32( - sl, FLASH_F7_OPTCR, - (current_control_register_value & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register1, - FLASH_F7_OPTCR1); + lock_flash_option(sl); + lock_flash(sl); return ret; } /** - * Write option bytes + * Write the given binary file with option bytes * @param sl - * @param option_byte value to write + * @param path readable file path, should be binary image + * @param addr of the memory mapped option bytes * @return 0 on success, -ve on failure. */ -static int -stlink_write_option_control_register_f7(stlink_t *sl, - uint32_t option_control_register) { - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - ILOG("Asked to write option control register 1 %#10x to %#010x.\n", - option_control_register, FLASH_F7_OPTCR); +int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, stm32_addr_t addr) { + /* Write the file in flash at addr */ + int err; + mapped_file_t mf = MAPPED_FILE_INITIALIZER; - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, FLASH_F7_OPTCR, - (option_control_register & ~(1 << FLASH_F7_OPTCR_LOCK)) | - (1 << FLASH_F7_OPTCR_START)); + if (map_file(&mf, path) == -1) { + ELOG("map_file() == -1\n"); + return (-1); + } - wait_flash_busy(sl); + printf("file %s ", path); + md5_calculate(&mf); + stlink_checksum(&mf); - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, - FLASH_F7_OPTCR); + err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); + stlink_fwrite_finalize(sl, addr); + unmap_file(&mf); - return ret; + return (err); } /** - * Write option bytes + * Read option control register 32 * @param sl - * @param option_byte value to write + * @param option_byte * @return 0 on success, -ve on failure. */ -static int -stlink_write_option_control_register_wb(stlink_t *sl, - uint32_t option_control_register) { - int ret = 0; - - // Clear errors - clear_flash_error(sl); - - ILOG("Asked to write option control register 1 %#10x to %#010x.\n", - option_control_register, STM32WB_FLASH_OPTR); - - /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, STM32WB_FLASH_OPTR, option_control_register); - - wait_flash_busy(sl); - - // Set Options Start bit - uint32_t val = (1 << STM32WB_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_control_register, - STM32WB_FLASH_OPTR); +int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); + return -1; + } - return ret; + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + return stlink_read_option_control_register_f0(sl, option_byte); + case STM32_FLASH_TYPE_F7: + return stlink_read_option_control_register_f7(sl, option_byte); + case STM32_FLASH_TYPE_WB_WL: + return stlink_read_option_control_register_wb(sl, option_byte); + default: + return -1; + } } /** - * Write option bytes + * Write option control register 32 * @param sl - * @param option bytes boot address to write + * @param option_cr * @return 0 on success, -ve on failure. */ -int stlink_write_option_control_register32(stlink_t *sl, - uint32_t option_control_register) { +int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) { int ret = -1; wait_flash_busy(sl); @@ -831,14 +905,14 @@ int stlink_write_option_control_register32(stlink_t *sl, switch (sl->flash_type) { case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: - ret = stlink_write_option_control_register_f0(sl, option_control_register); + ret = stlink_write_option_control_register_f0(sl, option_cr); break; case STM32_FLASH_TYPE_F7: - ret = stlink_write_option_control_register_f7(sl, option_control_register); + ret = stlink_write_option_control_register_f7(sl, option_cr); break; case STM32_FLASH_TYPE_WB_WL: ret = - stlink_write_option_control_register_wb(sl, option_control_register); + stlink_write_option_control_register_wb(sl, option_cr); break; default: ELOG("Option control register writing is currently not implemented for " @@ -849,7 +923,7 @@ int stlink_write_option_control_register32(stlink_t *sl, if (ret) ELOG("Flash option write failed!\n"); else - ILOG("Wrote option control register %#010x!\n", option_control_register); + ILOG("Wrote option control register %#010x!\n", option_cr); /* Re-lock flash. */ lock_flash_option(sl); @@ -859,72 +933,33 @@ int stlink_write_option_control_register32(stlink_t *sl, } /** - * Write option bytes + * Read option control register1 32 * @param sl - * @param option bytes boot address to write + * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_write_option_control_register1_32( - stlink_t *sl, uint32_t option_control_register1) { - int ret = -1; - - wait_flash_busy(sl); - - if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); - return -1; - } - - if (unlock_flash_option_if(sl)) { - ELOG("Flash option unlock failed!\n"); +int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t *option_byte) { + if (sl->option_base == 0) { + ELOG("Option bytes read is currently not supported for connected chip\n"); return -1; } switch (sl->flash_type) { case STM32_FLASH_TYPE_F7: - ret = - stlink_write_option_control_register1_f7(sl, option_control_register1); - break; + return stlink_read_option_control_register1_f7(sl, option_byte); default: - ELOG("Option control register 1 writing is currently not implemented for " - "connected chip\n"); - break; + return -1; + // return stlink_read_option_control_register1_generic(sl, option_byte); } - - if (ret) - ELOG("Flash option write failed!\n"); - else - ILOG("Wrote option control register 1 %#010x!\n", option_control_register1); - - lock_flash_option(sl); - lock_flash(sl); - - return (ret); -} - - -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -static int -stlink_write_option_bytes_boot_add_f7(stlink_t *sl, - uint32_t option_byte_boot_add) { - ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); - return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); } /** - * Write option bytes + * Write option control register1 32 * @param sl - * @param option bytes boot address to write + * @param option_cr * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes_boot_add32(stlink_t *sl, - uint32_t option_bytes_boot_add) { +int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1) { int ret = -1; wait_flash_busy(sl); @@ -942,10 +977,11 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, switch (sl->flash_type) { case STM32_FLASH_TYPE_F7: - ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); + ret = + stlink_write_option_control_register1_f7(sl, option_cr1); break; default: - ELOG("Option bytes boot address writing is currently not implemented for " + ELOG("Option control register 1 writing is currently not implemented for " "connected chip\n"); break; } @@ -953,108 +989,63 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, if (ret) ELOG("Flash option write failed!\n"); else - ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + ILOG("Wrote option control register 1 %#010x!\n", option_cr1); - /* Re-lock flash. */ lock_flash_option(sl); lock_flash(sl); - return ret; -} - -/** - * Write option bytes - * @param sl - * @param option_byte value to write - * @return 0 on success, -ve on failure. - */ -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { - WLOG("About to write option byte %#10x to %#10x.\n", option_byte, - sl->option_base); - return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, - 4); -} - -/** - * Write the given binary file with option bytes - * @param sl - * @param path readable file path, should be binary image - * @param addr of the memory mapped option bytes - * @return 0 on success, -ve on failure. - */ -int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, - stm32_addr_t addr) { - /* Write the file in flash at addr */ - int err; - mapped_file_t mf = MAPPED_FILE_INITIALIZER; - - if (map_file(&mf, path) == -1) { - ELOG("map_file() == -1\n"); - return (-1); - } - - printf("file %s ", path); - md5_calculate(&mf); - stlink_checksum(&mf); - - err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); - stlink_fwrite_finalize(sl, addr); - unmap_file(&mf); - - return (err); -} - -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register1_f7(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register 1 byte from %#10x\n", - FLASH_F7_OPTCR1); - return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); + return (ret); } /** - * Read option bytes + * Read option bytes 32 * @param sl - * @param option_byte option value + * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register1_32(stlink_t *sl, - uint32_t *option_byte) { +int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { if (sl->option_base == 0) { ELOG("Option bytes read is currently not supported for connected chip\n"); - return -1; + return (-1); } - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F7: - return stlink_read_option_control_register1_f7(sl, option_byte); + switch (sl->chip_id) { + case STM32_CHIPID_F2: + return stlink_read_option_bytes_f2(sl, option_byte); + case STM32_CHIPID_F4: + case STM32_CHIPID_F446: + return stlink_read_option_bytes_f4(sl, option_byte); + case STM32_CHIPID_F76xxx: + return stlink_read_option_bytes_f7(sl, option_byte); + case STM32_CHIPID_G0_CAT1: + return stlink_read_option_bytes_gx(sl, option_byte); + case STM32_CHIPID_G0_CAT2: + return stlink_read_option_bytes_gx(sl, option_byte); + case STM32_CHIPID_G4_CAT2: + return stlink_read_option_bytes_gx(sl, option_byte); + case STM32_CHIPID_G4_CAT3: + return stlink_read_option_bytes_gx(sl, option_byte); default: - return -1; - // return stlink_read_option_control_register1_generic(sl, option_byte); + return stlink_read_option_bytes_generic(sl, option_byte); } } - /** - * Read option bytes + * Write option bytes 32 * @param sl - * @param option_byte value to read + * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { - DLOG("@@@@ Read option byte boot address\n"); - return stlink_read_option_control_register1_f7(sl, option_byte); +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { + WLOG("About to write option byte %#10x to %#10x.\n", option_byte, + sl->option_base); + return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, 4); } /** - * Read option bytes + * Read option bytes boot address 32 * @param sl - * @param option_byte option value + * @param option_byte * @return 0 on success, -ve on failure. */ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { @@ -1074,62 +1065,45 @@ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { } /** - * Read option bytes + * Write option bytes boot address 32 * @param sl - * @param option_byte value to read + * @param option_bytes_boot_add * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f7(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); - return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); -} +int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add) { + int ret = -1; -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_f0(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); - return stlink_read_debug32(sl, FLASH_OBR, option_byte); -} + wait_flash_busy(sl); -/** - * Read option bytes - * @param sl - * @param option_byte value to read - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register_wb(stlink_t *sl, - uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", STM32WB_FLASH_OPTR); - return stlink_read_debug32(sl, STM32WB_FLASH_OPTR, option_byte); -} + if (unlock_flash_if(sl)) { + ELOG("Flash unlock failed! System reset required to be able to unlock it " + "again!\n"); + return -1; + } -/** - * Read option bytes - * @param sl - * @param option_byte option value - * @return 0 on success, -ve on failure. - */ -int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { - if (sl->option_base == 0) { - ELOG("Option bytes read is currently not supported for connected chip\n"); + if (unlock_flash_option_if(sl)) { + ELOG("Flash option unlock failed!\n"); return -1; } switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - return stlink_read_option_control_register_f0(sl, option_byte); case STM32_FLASH_TYPE_F7: - return stlink_read_option_control_register_f7(sl, option_byte); - case STM32_FLASH_TYPE_WB_WL: - return stlink_read_option_control_register_wb(sl, option_byte); + ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); + break; default: - return -1; + ELOG("Option bytes boot address writing is currently not implemented for " + "connected chip\n"); + break; } + + if (ret) + ELOG("Flash option write failed!\n"); + else + ILOG("Wrote option bytes boot address %#010x!\n", option_bytes_boot_add); + + /* Re-lock flash. */ + lock_flash_option(sl); + lock_flash(sl); + + return ret; } diff --git a/src/stlink-lib/option_bytes.h b/src/stlink-lib/option_bytes.h new file mode 100644 index 000000000..b9f88c508 --- /dev/null +++ b/src/stlink-lib/option_bytes.h @@ -0,0 +1,21 @@ +/* + * File: option_bytes.h + * + * Read and write option bytes and option control registers + */ + +#include +#include + +int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); +int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); +int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte); +int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte); + +int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); +int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); +int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr); +int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1); + +int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); diff --git a/src/read_write.c b/src/stlink-lib/read_write.c similarity index 100% rename from src/read_write.c rename to src/stlink-lib/read_write.c From aee9a47e3551d3cac9449ef1cceed30ecdcff133 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 30 Dec 2022 18:01:06 +0100 Subject: [PATCH 1341/1435] General fixes and improvements - Bugfix: "Failed to parse flash type or unrecognized flash type" (Closes #1240) (Closes #1242) (Closes #1290) (Closes #1291) - Updated README.md on OS-support - Updated version_support.md - Removed remnants of macOS support in CMakeLists.txt - Minor code formatting fixes - Updated CHANGELOG.md --- CHANGELOG.md | 17 +++-- CMakeLists.txt | 10 +-- README.md | 8 +-- doc/version_support.md | 154 +++++++++++++++++++++------------------- src/st-flash/flash.c | 24 ++++--- src/st-trace/trace.c | 3 +- src/stlink-lib/chipid.c | 28 ++++++-- src/stlink-lib/common.c | 2 +- 8 files changed, 134 insertions(+), 112 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index f48840c3f..82656d50b 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,7 +2,7 @@ # v1.7.1 -Release date: 2022-xx-xx +Release date: 2023-xx-xx This release drops support for some older operating systems. Check project README for details. @@ -18,7 +18,7 @@ Features: - Added option byte info for STM32F411XX ([#1141](https://github.com/stlink-org/stlink/pull/1141)) - Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) - [STM32H72X/3X]: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) -- Added support for STM32WLEx ([#1173](https://github.com/stlink-org/stlink/pull/1173)) +- Added support for STM32WLEx ([#1173](https://github.com/stlink-org/stlink/pull/1173), [#1273](https://github.com/stlink-org/stlink/pull/1273)) - Added support for STLINK-V3 devices with no MSD ([#1185](https://github.com/stlink-org/stlink/pull/1185)) - Updated gdb-server.c to allow external memory access on STM32H73xx ([#1196](https://github.com/stlink-org/stlink/pull/1196), [#1197](https://github.com/stlink-org/stlink/pull/1197)) - Erase addr size / section of the flash memory with st-flash ([#1213](https://github.com/stlink-org/stlink/pull/1213)) @@ -26,10 +26,12 @@ Features: - Added parametres option_base, option_size for F401xD_xE ([#1235](https://github.com/stlink-org/stlink/pull/1235)) - Added support for option bytes to F1xx_XLD (GD32F30x) ([#1250](https://github.com/stlink-org/stlink/pull/1250)) - Added option byte address for L4Rx devices ([#1254](https://github.com/stlink-org/stlink/pull/1254)) +- Added udev-rule rule for the STLink v3 MINIE programmer ([#1274](https://github.com/stlink-org/stlink/pull/1274), [#1281](https://github.com/stlink-org/stlink/pull/1281)) Updates & changes: - [refactoring] Moved chip-specific parameters into separate files ([#237](https://github.com/stlink-org/stlink/pull/237), [#1129](https://github.com/stlink-org/stlink/pull/1129)) +- [refactoring] General maintenance for code structure ([#903](https://github.com/stlink-org/stlink/pull/903), [#1090](https://github.com/stlink-org/stlink/pull/1090), [#1199](https://github.com/stlink-org/stlink/pull/1199), [#1212](https://github.com/stlink-org/stlink/pull/1212), [#1216](https://github.com/stlink-org/stlink/pull/1216)) - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation (commit [#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) @@ -45,6 +47,7 @@ Updates & changes: - [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), (commit [#43498de](https://github.com/stlink-org/stlink/commit/43498dedf651260ef34197e512d35e3ad7142401)) Fixes: +- cmake: Install shared libraries in proper directories ([#1098](https://github.com/stlink-org/stlink/pull/1098), [#1138](https://github.com/stlink-org/stlink/pull/1138), [#1154](https://github.com/stlink-org/stlink/pull/1154)) - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) - Fixed clearance of the H7 dual bank flag ([#1146](https://github.com/stlink-org/stlink/pull/1146), [#1147](https://github.com/stlink-org/stlink/pull/1147)) - Fix for 'libusb_devices were leaked' when no ST-LINK programmer was found ([#1150](https://github.com/stlink-org/stlink/pull/1150)) @@ -66,6 +69,10 @@ Fixes: - Fixed compilation with gcc-12 ([#1257](https://github.com/stlink-org/stlink/pull/1257), [#1267](https://github.com/stlink-org/stlink/pull/1267)) - Fixed flash regs addr for STM32L152RET6 in common_flash.c ([#1265](https://github.com/stlink-org/stlink/pull/1265)) - Fixed flash, dbgmcu and rcc registers for STM32L1 ([#1266](https://github.com/stlink-org/stlink/pull/1266)) +- Fixed compilation with gcc-12 ([#1257](https://github.com/stlink-org/stlink/pull/1257), [#1267](https://github.com/stlink-org/stlink/pull/1267)) +- Fixes for project compilation ([#1270](https://github.com/stlink-org/stlink/pull/1270), [#1271](https://github.com/stlink-org/stlink/pull/1271), [#1283](https://github.com/stlink-org/stlink/pull/1283), [#1286](https://github.com/stlink-org/stlink/pull/1286),commit [#f93adb9](https://github.com/stlink-org/stlink/commit/f93adb92f2e4ecf05a9361cb723c98693586929d)) +- [compilation] Corrected path to stlink/chips subdirectory ([#1276](https://github.com/stlink-org/stlink/pull/1276), [#1279](https://github.com/stlink-org/stlink/pull/1279)) +- [compilation] Fixed GUI compilation failure on OpenBSD i386 ([#1284](https://github.com/stlink-org/stlink/pull/1284)) # v1.7.0 @@ -96,7 +103,7 @@ Updates & changes: - [doc] Updated documentation on target resetting ([#261](https://github.com/stlink-org/stlink/pull/261), [#533](https://github.com/stlink-org/stlink/pull/533), [#1107](https://github.com/stlink-org/stlink/pull/1107)) - [doc] Added note on `(gdb) run` command (commit [#03793d4](https://github.com/stlink-org/stlink/commit/03793d42b6078344a9ef8ad55f1d5d0fc19e486e), [#267](https://github.com/stlink-org/stlink/pull/267)) - [doc] `st-flash --reset` parameter (one solution for #356) ([#642](https://github.com/stlink-org/stlink/pull/642)) -- [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864), [#976](https://github.com/stlink-org/stlink/pull/976), [#978](https://github.com/stlink-org/stlink/pull/978)) +- [refactoring] General maintenance ([#864](https://github.com/stlink-org/stlink/pull/864). [#978](https://github.com/stlink-org/stlink/pull/978)) - Imported debian pkg-settings ([#986](https://github.com/stlink-org/stlink/pull/986)) - Add support for FreeBSD's `libusb` reimplementation ([#992](https://github.com/stlink-org/stlink/pull/992), [#993](https://github.com/stlink-org/stlink/pull/993)) - [doc] Added explanation about STM32F103 fake chips (commit [#a66557a](https://github.com/stlink-org/stlink/commit/a66557a102d48e69feb0a9746e8e42c4baf31fe2), [#1024](https://github.com/stlink-org/stlink/pull/1024)) @@ -117,7 +124,7 @@ Fixes: - doc/man: Fixed installation directory ([#970](https://github.com/stlink-org/stlink/pull/970)) - Fixed installation path for desktop-file and icons ([#972](https://github.com/stlink-org/stlink/pull/972)) - Fix for static linking of `libssp` ([#973](https://github.com/stlink-org/stlink/pull/973), [#974](https://github.com/stlink-org/stlink/pull/974)) -- [regression] Fixed wrong formatting for library install path ([#978](https://github.com/stlink-org/stlink/pull/978), [#1089](https://github.com/stlink-org/stlink/pull/1089)) +- [regression] Fixed wrong formatting for library install path ([#978](https://github.com/stlink-org/stlink/pull/978), [#1089](https://github.com/stlink-org/stlink/pull/1089), [#1277](https://github.com/stlink-org/stlink/pull/1277)) - Fixed installation of header files needed for compiling with `libstlink.so.1.6.1` (commit [#31b1fa1](https://github.com/stlink-org/stlink/commit/31b1fa16201521e2aaf464576f2f169981abede0), [#982](https://github.com/stlink-org/stlink/pull/982)) - Fixed `connect under reset` for `st-flash` and `st-util` ([#983](https://github.com/stlink-org/stlink/pull/983)) - Fix for `mmap() size_t overflow` in `st-flash` ([#988](https://github.com/stlink-org/stlink/pull/988), [#989](https://github.com/stlink-org/stlink/pull/989)) @@ -190,7 +197,7 @@ Updates & changes: - [doc] `st-flash --flash=n[k][m]` command line option to override device model ([#902](https://github.com/stlink-org/stlink/pull/902)) - [refactoring] Improved cmake build process ([#912](https://github.com/stlink-org/stlink/pull/912)) - Set up a `libusb` log level accordingly to verbosity ([#894](https://github.com/stlink-org/stlink/pull/894) - - [compatibility] Updated `libusb` to v1.0.23 ([#895](https://github.com/stlink-org/stlink/pull/895, [#1089](https://github.com/stlink-org/stlink/pull/1089)) + - [compatibility] Updated `libusb` to v1.0.23 ([#895](https://github.com/stlink-org/stlink/pull/895) - Updated compiling doc & version support ([#896](https://github.com/stlink-org/stlink/pull/896), [#897](https://github.com/stlink-org/stlink/pull/897), [#899](https://github.com/stlink-org/stlink/pull/899)) - Version requirements & pkg-maintainer - Fixed install paths in build script diff --git a/CMakeLists.txt b/CMakeLists.txt index 3a22fdedc..f7bbe6f12 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -78,13 +78,9 @@ include(GNUInstallDirs) # Define GNU standard installation directories cmake_host_system_information(RESULT OS_NAME QUERY OS_NAME) message(STATUS "Checking for OS_NAME: ${OS_NAME}") -if (OS_NAME STREQUAL "macOS") - message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/local/share)") - set(CMAKE_INSTALL_SHAREDIR /usr/local/share/) -else () - message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/share)") - set(CMAKE_INSTALL_SHAREDIR /usr/share/) -endif () +message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/share)") +set(CMAKE_INSTALL_SHAREDIR /usr/share/) + ## Set C build flags if (NOT MSVC) diff --git a/README.md b/README.md index 571db49fd..9a36f0fbb 100644 --- a/README.md +++ b/README.md @@ -67,7 +67,7 @@ Please ensure to select the correct version for your system (i686 or x86_64). Th Alternatively one may compile and install from source as described in our [compiling manual](doc/compiling.md#Windows). -**Linux**: +**Linux / Unix**: We recommend to install `stlink-tools` from the package repository of the used distribution: @@ -78,13 +78,7 @@ We recommend to install `stlink-tools` from the package repository of the used d - Arch Linux: [(Link)](https://www.archlinux.org/packages/community/x86_64/stlink) - Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) - Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) -- Gentoo Linux: [(Link)](https://packages.gentoo.org/packages/dev-embedded/stlink) - -**Other Operating Systems**: - -- RedHat/CentOS 8: Users can install from [EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel8) - FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) -- MacOS: Users can open a terminal window and then follow the same procedure as for installing on Linux ## Installation from source (advanced users) diff --git a/doc/version_support.md b/doc/version_support.md index 0f1849697..593c86549 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -8,88 +8,94 @@ On Windows users should ensure that cmake **3.10.2** or any later version is ins Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb`. - Windows 10 -- Windows 8.1 +- Windows 11 ### Linux-/Unix-based: -| Operating System | libusb | cmake | libgtk-dev | Notes | -| ------------------------- | ------------------------------ | ---------- | ----------- | ------------------------ | -| Debian Sid | 1.0.24 | 3.22.1 | 3.24.31 | | -| Debian 11 (Bullseye) | 1.0.24 | 3.18.4 | 3.24.24 | | -| Debian 10 (Buster) | 1.0.**22** | **3.13.4** | 3.24.**5** | | -| | | | | | -| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.16.3 | 3.24.**18** | | -| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | **3.10.2** | 3.**22.30** | End of Support: Apr 2023 | -| | | | | | -| Fedora Rawhide [x64] | 1.0.24 | 3.22.3 | 3.24.31 | | -| Fedora 35 [x64] | 1.0.24 | 3.21.3 | 3.24.30 | | -| Fedora 34 [x64] | 1.0.24 (`libusbx`) | 3.19.7 | 3.24.28 | | -| | | | | | -| openSUSE Tumbleweed [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | -| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.17.0 | 3.24.20 | End of Support: Dec 2022 | -| | | | | | -| Alpine 3.15 | 1.0.24 | 3.21.3 | 3.24.30 | | -| Alpine 3.14 | 1.0.24 | 3.20.3 | 3.24.28 | | -| Alpine 3.13 | 1.0.24 | 3.18.4 | 3.24.23 | End of Support: Nov 2022 | -| Alpine 3.12 | 1.0.23 | 3.17.2 | 3.24.22 | End of Support: May 2022 | -| | | | | | -| FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | -| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | -| | | | | | -| NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | -| NetBSD 8.x | 1.0.24 | 3.19.7 | 3.24.27 | | -| | | | | | -| CentOS 9 Stream [x64] | 1.0.24 (`libusbx`) | 3.20.3 | 3.24.30 | | -| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | -| | | | | | -| ALT Linux Sisyphus | 1.0.24 | 3.22.1 | 3.24.31 | | -| ALT Linux P10 | 1.0.24 | 3.20.5 | 3.24.31 | | -| ALT Linux P9 | 1.0.**22** | 3.16.3 | 3.24.29 | | -| | | | | | -| OpenMandriva Rolling | 1.0.24 | 3.22.1 | 3.24.31 | | -| OpenMandriva Cooker | 1.0.24 | 3.22.1 | 3.24.31 | | -| OpenMandriva Lx 4.2 | 1.0.24 | 3.19.3 | 3.24.24 | | -| | | | | | -| Arch Linux | 1.0.24 | 3.22.1 | - | | -| KaOS [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | -| Mageia Cauldron | 1.0.24 | 3.22.1 | 3.24.31 | | -| PCLinuxOS [x64] | ? | 3.22.1 | 3.24.31 | | -| Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | -| Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | -| Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | -| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | -| Rocky Linux 8 [x64] | 1.0.23 | 3.20.2 | 3.**22.30** | | -| Mageia 8 | 1.0.24 | 3.19.2 | 3.24.24 | End of Support: Aug 2022 | -| Adélie 1.0 | 1.0.23 | 3.16.4 | 3.24.23 | | +Maintained versions of: +- Debian +- Ubuntu +- Fedora +- openSUSE +- OpenMandriva +- Arch Linux +- FreeBSD +- NetBSD + +Other Linux-/Unix-based Operating Systems: + +| Operating System | libusb | cmake | libgtk-dev | Notes | +| ------------------------ | ------------------------------ | ---------- | ----------- | ------------------------ | +| Debian Sid | 1.0.24 | 3.22.1 | 3.24.31 | | +| Debian 11 (Bullseye) | 1.0.24 | 3.**18.4** | 3.24.24 | | +| Debian 10 (Buster) | 1.0.**22** | 3.**13.4** | 3.24.**5** | | +| | | | | | +| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.**16.3** | 3.24.**18** | | +| | | | | | +| Alpine 3.15 | 1.0.24 | 3.21.3 | 3.24.30 | End of Support: Nov 2023 | +| Alpine 3.14 | 1.0.24 | 3.20.3 | 3.24.28 | End of Support: May 2023 | +| | | | | | +| FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | +| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | +| | | | | | +| NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | +| NetBSD 8.x | 1.0.24 | 3.**19.7** | 3.24.27 | | +| | | | | | +| CentOS 9 Stream [x64] | 1.0.24 (`libusbx`) | 3.20.3 | 3.24.30 | | +| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | +| | | | | | +| ALT Linux Sisyphus | 1.0.24 | 3.22.1 | 3.24.31 | | +| ALT Linux P10 | 1.0.24 | 3.20.5 | 3.24.31 | | +| ALT Linux P9 | 1.0.**22** | 3.**16.3** | 3.24.29 | | +| | | | | | +| OpenMandriva Rolling | 1.0.24 | 3.22.1 | 3.24.31 | | +| OpenMandriva Cooker | 1.0.24 | 3.22.1 | 3.24.31 | | +| OpenMandriva Lx 4.2 | 1.0.24 | 3.**19.3** | 3.24.24 | | +| | | | | | +| Arch Linux | 1.0.24 | 3.22.1 | - | | +| KaOS [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | +| Mageia Cauldron | 1.0.24 | 3.22.1 | 3.24.31 | | +| PCLinuxOS [x64] | (?) | 3.22.1 | 3.24.31 | | +| Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | +| Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | +| Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | +| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | +| Rocky Linux 8 [x64] | 1.0.23 | 3.20.2 | 3.**22.30** | | +| Adélie 1.0 | 1.0.23 | 3.**16.4** | 3.24.23 | | ## Unsupported Operating Systems (as of Release v1.7.1) Systems with highlighted versions remain compatible with this toolset. -| Operating System | libusb | cmake | End of
      OS-Support | -| ------------------------ | ------------------------------ | ---------- | ---------------------- | -| CentOS 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | -| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | -| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | -| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | -| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | -| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | -| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | -| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | -| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | -| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | -| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | -| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | -| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | -| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | -| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | -| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | -| Debian 9 (Stretch) | 1.0.**21** | 3.7.2 | Jun 2022 | -| Slackware 14.2 | 1.0.20 | 3.5.2 | | -| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | -| CentOS 7 [x64] | 1.0.**21** (`libusbx`) | 2.8.12.2 | Jun 2024 | -| Slackware 14.1 | 1.0.9 | 2.8.12 | | -| Slackware 14.0 | 1.0.9 | 2.8.8 | | +| Operating System | libusb | cmake | End of
      OS-Support | +| ------------------------- | ------------------------------ | ---------- | ---------------------- | +| Fedora 35 [x64] | 1.0.**24** | 3.**21.3** | Dec 2022 | +| CentOS 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | +| Fedora 34 [x64] | 1.0.**24** (`libusbx`) | 3.**19.7** | Jun 2022 | +| Mageia 8 | 1.0.**24** | 3.**19.2** | Aug 2022 | +| Alpine 3.13 | 1.0.**24** | 3.**18.4** | Nov 2022 | +| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | +| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | +| Alpine 3.12 | 1.0.**23** | 3.**17.2** | May 2022 | +| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.**17.0** | Dec 2022 | +| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | +| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | +| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | +| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | +| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | +| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | +| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | +| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | +| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | +| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | +| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | +| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | +| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.**10.2** | **Apr 2023** | +| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | +| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | Jun 2022 | +| Slackware 14.2 | 1.0.20 | 3.5.2 | | +| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | +| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | _All other operating systems which are not listed are unsupported._ diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 0985c75c2..4b8e37fef 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -71,6 +71,7 @@ int main(int ac, char** av) { if (sl->flash_type == STM32_FLASH_TYPE_UNKNOWN) { printf("Failed to connect to target\n"); + fprintf(stderr, "Failed to parse flash type or unrecognized flash type\n"); goto on_error; } @@ -98,8 +99,10 @@ int main(int ac, char** av) { goto on_error; } - if (o.cmd == FLASH_CMD_WRITE) { // write + if (o.cmd == FLASH_CMD_WRITE) { size_t size = 0; + + // write if (o.format == FLASH_FORMAT_IHEX) { err = stlink_parse_ihex(o.filename, stlink_get_erased_pattern(sl), &mem, &size, &o.addr); @@ -108,8 +111,7 @@ int main(int ac, char** av) { goto on_error; } } - if ((o.addr >= sl->flash_base) && - (o.addr < sl->flash_base + sl->flash_size)) { + if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { if (o.format == FLASH_FORMAT_IHEX) { err = stlink_mwrite_flash(sl, mem, (uint32_t)size, o.addr); } else { @@ -120,8 +122,7 @@ int main(int ac, char** av) { printf("stlink_fwrite_flash() == -1\n"); goto on_error; } - } else if ((o.addr >= sl->sram_base) && - (o.addr < sl->sram_base + sl->sram_size)) { + } else if ((o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { if (o.format == FLASH_FORMAT_IHEX) { err = stlink_mwrite_sram(sl, mem, (uint32_t)size, o.addr); } else { @@ -132,8 +133,7 @@ int main(int ac, char** av) { printf("stlink_fwrite_sram() == -1\n"); goto on_error; } - } else if ((o.addr >= sl->option_base) && - (o.addr < sl->option_base + sl->option_size)) { + } else if ((o.addr >= sl->option_base) && (o.addr < sl->option_base + sl->option_size)) { err = stlink_fwrite_option_bytes(sl, o.filename, o.addr); if (err == -1) { @@ -170,11 +170,11 @@ int main(int ac, char** av) { goto on_error; } } else if (o.cmd == FLASH_CMD_ERASE) { - if (o.size > 0 && o.addr > 0) + if (o.size > 0 && o.addr > 0) { err = stlink_erase_flash_section(sl, o.addr, o.size, false); - else + } else { err = stlink_erase_flash_mass(sl); - + } if (err == -1) { printf("stlink_erase_flash_mass() == -1\n"); goto on_error; @@ -184,7 +184,9 @@ int main(int ac, char** av) { printf("Failed to reset device\n"); goto on_error; } - } else { // read + } else { + + // read if ((o.area == FLASH_MAIN_MEMORY) || (o.area == FLASH_SYSTEM_MEMORY)) { if ((o.size == 0) && (o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { o.size = sl->flash_size; diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 9fcf8e358..83bfeac8c 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -171,8 +171,7 @@ bool parse_options(int argc, char **argv, st_settings_t *settings) { settings->serial_number = NULL; ugly_init(settings->logging_level); - while ((c = getopt_long(argc, argv, "hVv::c:ns:f", long_options, - &option_index)) != -1) { + while ((c = getopt_long(argc, argv, "hVv::c:ns:f", long_options, &option_index)) != -1) { switch (c) { case 'h': settings->show_help = true; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index e36c150a6..7ff6c77a9 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -67,20 +67,22 @@ void process_chipfile(char *fname) { sscanf(buf, "%s %s", word, value); if (strcmp (word, "dev_type") == 0) { - // ts->dev_type = strdup (value); buf[strlen(buf) - 1] = 0; // chomp newline sscanf(buf, "%*s %n", &nc); ts->dev_type = strdup(buf + nc); } else if (strcmp(word, "ref_manual_id") == 0) { - // ts->ref_manual_id = strdup (value); buf[strlen(buf) - 1] = 0; // chomp newline sscanf(buf, "%*s %n", &nc); ts->ref_manual_id = strdup(buf + nc); } else if (strcmp(word, "chip_id") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->chip_id) < 1) { fprintf(stderr, "Failed to parse chip-id\n"); } } else if (strcmp(word, "flash_type") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (strcmp(value, "F0_F1_F3") == 0) { ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; } else if (strcmp(value, "F1_XL") == 0) { @@ -105,37 +107,52 @@ void process_chipfile(char *fname) { ts->flash_type = STM32_FLASH_TYPE_WB_WL; } else { ts->flash_type = STM32_FLASH_TYPE_UNKNOWN; - fprintf(stderr, "Failed to parse flash type or unrecognized flash type\n"); } } else if (strcmp(word, "flash_size_reg") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->flash_size_reg) < 1) { fprintf(stderr, "Failed to parse flash size reg\n"); } } else if (strcmp(word, "flash_pagesize") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->flash_pagesize) < 1) { fprintf(stderr, "Failed to parse flash page size\n"); } } else if (strcmp(word, "sram_size") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->sram_size) < 1) { fprintf(stderr, "Failed to parse SRAM size\n"); } } else if (strcmp(word, "bootrom_base") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->bootrom_base) < 1) { fprintf(stderr, "Failed to parse BootROM base\n"); } } else if (strcmp(word, "bootrom_size") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->bootrom_size) < 1) { fprintf(stderr, "Failed to parse BootROM size\n"); } } else if (strcmp(word, "option_base") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->option_base) < 1) { fprintf(stderr, "Failed to parse option base\n"); } } else if (strcmp(word, "option_size") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); if (sscanf(value, "%i", &ts->option_size) < 1) { fprintf(stderr, "Failed to parse option size\n"); } } else if (strcmp(word, "flags") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); p = strtok (buf, " \t\n"); while ((p = strtok (NULL, " \t\n"))) { @@ -153,8 +170,7 @@ void process_chipfile(char *fname) { sscanf(value, "%x", &ts->flags); } else { - fprintf(stderr, "Unknown keyword in %s: %s\n", - fname, word); + fprintf(stderr, "Unknown keyword in %s: %s\n", fname, word); } } fclose(fp); @@ -164,6 +180,7 @@ void process_chipfile(char *fname) { #if defined(STLINK_HAVE_DIRENT_H) #include + void init_chipids(char *dir_to_scan) { DIR *d; size_t nl; // namelen @@ -198,6 +215,7 @@ void init_chipids(char *dir_to_scan) { #if defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) #include #include + void init_chipids(char *dir_to_scan) { HANDLE hFind = INVALID_HANDLE_VALUE; WIN32_FIND_DATAA ffd; diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index d360b5d03..041b55f64 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -414,7 +414,7 @@ int stlink_status(stlink_t *sl) { } // 257 int stlink_version(stlink_t *sl) { - DLOG("*** looking up stlink version\n"); + DLOG("*** looking up stlink version ***\n"); if (sl->backend->version(sl)) { return (-1); From dfff59d39f8a3c7cc68e3281b72d237baa109751 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 31 Dec 2022 14:49:39 +0100 Subject: [PATCH 1342/1435] Added support for STM32L4Q5 (Closes #1224) --- config/chips/L41x_L42x.chip | 2 +- config/chips/L43x_L44x.chip | 2 +- config/chips/L45x_L46x.chip | 2 +- config/chips/L47x_L48x.chip | 2 +- config/chips/L496x_L4A6x.chip | 2 +- config/chips/{L4Px.chip => L4Px_L4Qx.chip} | 10 +++---- config/chips/L4Rx.chip | 2 +- config/chips/L5x5.chip.txt | 15 ---------- inc/stm32.h | 2 +- src/stlink-lib/chipid.c | 2 +- src/stlink-lib/common.c | 2 +- src/stlink-lib/common_flash.c | 32 +++++++++++----------- src/stlink-lib/flashloader.c | 12 ++++---- src/stlink-lib/option_bytes.c | 2 +- 14 files changed, 37 insertions(+), 52 deletions(-) rename config/chips/{L4Px.chip => L4Px_L4Qx.chip} (62%) delete mode 100644 config/chips/L5x5.chip.txt diff --git a/config/chips/L41x_L42x.chip b/config/chips/L41x_L42x.chip index 11e545bb7..18730b4a2 100644 --- a/config/chips/L41x_L42x.chip +++ b/config/chips/L41x_L42x.chip @@ -3,7 +3,7 @@ dev_type STM32L41x_L42x ref_manual_id 0394 chip_id 0x464 // STM32_CHIPID_L41x_L42x -flash_type L4_L4P +flash_type L4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0xa000 // 40 KB diff --git a/config/chips/L43x_L44x.chip b/config/chips/L43x_L44x.chip index f0a959693..1e4b593ed 100644 --- a/config/chips/L43x_L44x.chip +++ b/config/chips/L43x_L44x.chip @@ -3,7 +3,7 @@ dev_type STM32L41x_L42x ref_manual_id 0392 chip_id 0x435 // STM32_CHIPID_L43x_L44x -flash_type L4_L4P +flash_type L4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0xc000 // 48 KB diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index 267122f87..cbe948c1f 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -3,7 +3,7 @@ dev_type STM32L45x_L46x ref_manual_id 0394 chip_id 0x462 // STM32_CHIPID_L45x_L46x -flash_type L4_L4P +flash_type L4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x20000 // 128 KB diff --git a/config/chips/L47x_L48x.chip b/config/chips/L47x_L48x.chip index 421663e58..5475ee77b 100644 --- a/config/chips/L47x_L48x.chip +++ b/config/chips/L47x_L48x.chip @@ -3,7 +3,7 @@ dev_type STM32L47x_L48x ref_manual_id 0351 chip_id 0x415 // STM32_CHIPID_L4 -flash_type L4_L4P +flash_type L4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x18000 // 96 KB diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 6657d5484..24788c092 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -3,7 +3,7 @@ dev_type STM32L496x_L4A6x ref_manual_id 0351 chip_id 0x461 // STM32_CHIPID_L496x_L4A6x -flash_type L4_L4P +flash_type L4 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB sram_size 0x50000 // 320 KB diff --git a/config/chips/L4Px.chip b/config/chips/L4Px_L4Qx.chip similarity index 62% rename from config/chips/L4Px.chip rename to config/chips/L4Px_L4Qx.chip index 39788eabe..881fd8188 100644 --- a/config/chips/L4Px.chip +++ b/config/chips/L4Px_L4Qx.chip @@ -1,14 +1,14 @@ -# Chip-ID file for STM32L4Px device +# Chip-ID file for STM32L4Px / STM32L4Qx device # -dev_type STM32L4Px +dev_type STM32L4Px_L4Qx ref_manual_id 0432 chip_id 0x471 // STM32_CHIPID_L4PX -flash_type L4_L4P +flash_type L4 flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0xa0000 // 640 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB -option_base 0x0 -option_size 0x0 +option_base 0x1ff00000 +option_size 0x4 // 4 B flags swo diff --git a/config/chips/L4Rx.chip b/config/chips/L4Rx.chip index 428a0c21e..80cd02d55 100644 --- a/config/chips/L4Rx.chip +++ b/config/chips/L4Rx.chip @@ -3,7 +3,7 @@ dev_type STM32L4Rx ref_manual_id 0432 chip_id 0x470 // STM32_CHIPID_L4RX -flash_type L4_L4P +flash_type L4 flash_size_reg 0x1fff75e0 flash_pagesize 0x1000 // 4 KB sram_size 0xa0000 // 640 KB diff --git a/config/chips/L5x5.chip.txt b/config/chips/L5x5.chip.txt deleted file mode 100644 index ce268148b..000000000 --- a/config/chips/L5x5.chip.txt +++ /dev/null @@ -1,15 +0,0 @@ -# Chip-ID file for STM32L5x2 device -# -dev_type STM32L5x2 -ref_manual_id 0438 -chip_id 0x0 // (temporary setting only!) -flash_type 0 // (temporary setting only!) -flash_size_reg 0x0bfa07a0 -flash_pagesize 0x2000 // 8 KB -sram_size 0x40000 // 256 KB -bootrom_base 0x0bf90000 -bootrom_size 0x8000 // 32 KB -option_base 0x0 -option_size 0x0 -flags none - diff --git a/inc/stm32.h b/inc/stm32.h index 2d533eca2..856d6e4bd 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -51,7 +51,7 @@ enum stm32_flash_type { STM32_FLASH_TYPE_G4 = 6, STM32_FLASH_TYPE_H7 = 7, STM32_FLASH_TYPE_L0_L1 = 8, - STM32_FLASH_TYPE_L4_L4P = 9, + STM32_FLASH_TYPE_L4 = 9, STM32_FLASH_TYPE_L5_U5 = 10, STM32_FLASH_TYPE_WB_WL = 11, }; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 7ff6c77a9..51a1200ad 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -100,7 +100,7 @@ void process_chipfile(char *fname) { } else if (strcmp(value, "L0_L1") == 0) { ts->flash_type = STM32_FLASH_TYPE_L0_L1; } else if (strcmp(value, "L4_L4P") == 0) { - ts->flash_type = STM32_FLASH_TYPE_L4_L4P; + ts->flash_type = STM32_FLASH_TYPE_L4; } else if (strcmp(value, "L5_U5") == 0) { ts->flash_type = STM32_FLASH_TYPE_L5_U5; } else if (strcmp(value, "WB_WL") == 0) { diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 041b55f64..34a8ac573 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -984,7 +984,7 @@ static void stop_wdg_in_debug(stlink_t *sl) { break; case STM32_FLASH_TYPE_F2_F4: case STM32_FLASH_TYPE_F7: - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: dbgmcu_cr = STM32F4_DBGMCU_APB1FZR1; set = (1 << STM32F4_DBGMCU_APB1FZR1_IWDG_STOP) | (1 << STM32F4_DBGMCU_APB1FZR1_WWDG_STOP); diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index b21929ddf..0ed4734ad 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -38,7 +38,7 @@ uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { reg = FLASH_F7_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { reg = STM32L4_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { @@ -79,7 +79,7 @@ void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || @@ -124,7 +124,7 @@ static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { sr_reg = FLASH_F4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { sr_reg = STM32L4_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { @@ -163,7 +163,7 @@ void clear_flash_error(stlink_t *sl) { write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); } break; - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); break; case STM32_FLASH_TYPE_H7: @@ -192,7 +192,7 @@ uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { sr_reg = FLASH_F4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { sr_reg = STM32L4_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { @@ -222,7 +222,7 @@ unsigned int is_flash_busy(stlink_t *sl) { sr_busy_shift = FLASH_F4_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { sr_busy_shift = STM32L4_FLASH_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { @@ -297,7 +297,7 @@ int check_flash_error(stlink_t *sl) { WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); break; - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); @@ -360,7 +360,7 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || @@ -404,7 +404,7 @@ static void unlock_flash(stlink_t *sl) { key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; flash_key1 = FLASH_L0_PEKEY1; flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { key_reg = STM32L4_FLASH_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { @@ -468,7 +468,7 @@ int lock_flash_option(stlink_t *sl) { optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; break; - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; @@ -541,7 +541,7 @@ static bool is_flash_option_locked(stlink_t *sl) { optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; break; - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; @@ -595,7 +595,7 @@ static int unlock_flash_option(stlink_t *sl) { optkey1 = FLASH_L0_OPTKEY1; optkey2 = FLASH_L0_OPTKEY2; break; - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: optkey_reg = STM32L4_FLASH_OPTKEYR; break; case STM32_FLASH_TYPE_G0: @@ -672,7 +672,7 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { cr_reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { @@ -796,7 +796,7 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_strt = (1 << STM32L4_FLASH_CR_STRT); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || @@ -830,7 +830,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { cr_reg = FLASH_F7_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); cr_pg = (1 << STM32L4_FLASH_CR_PG); @@ -890,7 +890,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if (sl->flash_type == STM32_FLASH_TYPE_F2_F4 || sl->flash_type == STM32_FLASH_TYPE_F7 || - sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + sl->flash_type == STM32_FLASH_TYPE_L4) { // unlock if locked unlock_flash_if(sl); diff --git a/src/stlink-lib/flashloader.c b/src/stlink-lib/flashloader.c index abb140fdd..d9542ebbc 100644 --- a/src/stlink-lib/flashloader.c +++ b/src/stlink-lib/flashloader.c @@ -80,7 +80,7 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= (1 << STM32L4_FLASH_CR_PG); @@ -123,7 +123,7 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { rcc_dma_mask = STM32G0_RCC_DMAEN; break; case STM32_FLASH_TYPE_G4: - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: rcc = STM32G4_RCC_AHB1ENR; rcc_dma_mask = STM32G4_RCC_DMAEN; break; @@ -170,7 +170,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { + (sl->flash_type == STM32_FLASH_TYPE_L4)) { ILOG("Starting Flash write for F2/F4/F7/L4\n"); // Flash loader initialisation @@ -194,7 +194,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { return (-1); } - if (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) { + if (sl->flash_type == STM32_FLASH_TYPE_L4) { // L4 does not have a byte-write mode if (voltage < 1710) { ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); @@ -304,7 +304,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, size_t off; if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4_L4P)) { + (sl->flash_type == STM32_FLASH_TYPE_L4)) { size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; for (off = 0; off < len;) { size_t size = len - off > buf_size ? buf_size : len - off; @@ -451,7 +451,7 @@ int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4_L4P) || + (sl->flash_type == STM32_FLASH_TYPE_L4) || (sl->flash_type == STM32_FLASH_TYPE_WB_WL) || (sl->flash_type == STM32_FLASH_TYPE_G0) || (sl->flash_type == STM32_FLASH_TYPE_G4) || diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 44cd3930b..3d332f49d 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -795,7 +795,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ui case STM32_FLASH_TYPE_L0_L1: ret = stlink_write_option_bytes_l0(sl, addr, base, len); break; - case STM32_FLASH_TYPE_L4_L4P: + case STM32_FLASH_TYPE_L4: ret = stlink_write_option_bytes_l4(sl, addr, base, len); break; case STM32_FLASH_TYPE_G0: From f025d756b7781cfb15c0aab15e47deddf5c17f7d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 1 Jan 2023 13:20:02 +0100 Subject: [PATCH 1343/1435] Minor corrections regarding os support --- .github/ISSUE_TEMPLATE/feature-request.md | 2 +- CMakeLists.txt | 2 +- doc/compiling.md | 2 +- src/stlink-lib/libusb_settings.h | 3 +-- 4 files changed, 4 insertions(+), 5 deletions(-) diff --git a/.github/ISSUE_TEMPLATE/feature-request.md b/.github/ISSUE_TEMPLATE/feature-request.md index d57dbefed..b16cbf92b 100644 --- a/.github/ISSUE_TEMPLATE/feature-request.md +++ b/.github/ISSUE_TEMPLATE/feature-request.md @@ -20,7 +20,7 @@ labels: code/feature-request In order to allow developers to isolate and target your respective issue, please take some time to select the check boxes below and fill out each of the following items appropriate to your specific request. - [ ] Programmer/board type: [enter here] (e.g STLINK /V1, /V2, /V2-onboard, /V2-clone, /V3) -- [ ] Operating system an version: [enter here] (e.g Linux, macOS, Windows) +- [ ] Operating system an version: [enter here] (e.g Linux, Windows) - [ ] **stlink tools version** and/or git commit hash: [enter here] (e.g v1.6.1/git-d0416149) - [ ] stlink commandline tool name: [enter here] (e.g `st-info`, `st-flash`, `st-trace`, `st-util`) - [ ] Target chip (and board, if applicable): [enter here] (e.g STM32F103C8T6 (NUCLEO-F103RB)) diff --git a/CMakeLists.txt b/CMakeLists.txt index f7bbe6f12..b25291992 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -74,7 +74,7 @@ include(${CMAKE_MODULE_PATH}/get_version.cmake) # Determine project version include(GNUInstallDirs) # Define GNU standard installation directories -# Define install directory /usr/local/share [not /usr/share on MacOS] +# Define install directory /usr/local/share cmake_host_system_information(RESULT OS_NAME QUERY OS_NAME) message(STATUS "Checking for OS_NAME: ${OS_NAME}") diff --git a/doc/compiling.md b/doc/compiling.md index 5f6852a93..eec46bb3d 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -1,6 +1,6 @@ # Compiling from sources -## Microsoft Windows (10, 8.1) +## Microsoft Windows (10, 11) ### Common Requirements diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index 2a595238a..ee690e0b1 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -19,6 +19,7 @@ * v1.0.23 | 0x01000107 * v1.0.24 | 0x01000108 * v1.0.25 | 0x01000109 + * v1.0.26 | 0x01000110 */ #if defined (__FreeBSD__) @@ -35,8 +36,6 @@ #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 #elif defined (__linux__) #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 -#elif defined (__APPLE__) - #define MINIMAL_API_VERSION 0x01000109 // v1.0.25 #elif defined (_WIN32) #define MINIMAL_API_VERSION 0x01000109 // v1.0.25 #endif From b60a03540402bb71a318c6303ad4199ef5c25983 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 1 Jan 2023 13:32:14 +0100 Subject: [PATCH 1344/1435] Initial support for STM32 L5 & U5 devices (References: #1005 #1096 #1247) --- config/chips/L5x5.chip | 14 + config/chips/{U5x5.chip.txt => U5x5.chip} | 9 +- inc/stm32.h | 8 + inc/stm32flash.h | 39 ++- src/st-flash/flash.c | 1 + src/stlink-lib/common.c | 198 +++++++------- src/stlink-lib/common_flash.c | 300 ++++++++++++++-------- src/stlink-lib/flashloader.c | 29 ++- src/stlink-lib/option_bytes.c | 33 +-- 9 files changed, 392 insertions(+), 239 deletions(-) create mode 100644 config/chips/L5x5.chip rename config/chips/{U5x5.chip.txt => U5x5.chip} (52%) diff --git a/config/chips/L5x5.chip b/config/chips/L5x5.chip new file mode 100644 index 000000000..0f205a62b --- /dev/null +++ b/config/chips/L5x5.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32L5x2xx device +# +dev_type STM32L5x2xx +ref_manual_id 0438 +chip_id 0x472 // STM32_CHIPID_L5x2xx +flash_type L5_U5 +flash_size_reg 0x0bfa05e0 +flash_pagesize 0x1000 // 4 KB +sram_size 0x40000 // 256 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags dualbank diff --git a/config/chips/U5x5.chip.txt b/config/chips/U5x5.chip similarity index 52% rename from config/chips/U5x5.chip.txt rename to config/chips/U5x5.chip index 177359cc3..be19d04af 100644 --- a/config/chips/U5x5.chip.txt +++ b/config/chips/U5x5.chip @@ -2,14 +2,13 @@ # dev_type STM32U5x5 ref_manual_id 0456 -chip_id 0x0 // (temporary setting only!) -flash_type 0 // (temporary setting only!) +chip_id 0x482 // STM32_CHIPID_U5x5 +flash_type L5_U5 flash_size_reg 0x0bfa07a0 -flash_pagesize 0x2000 // 8 KB +flash_pagesize 0x200000 // 2048 KB sram_size 0xc4800 // 786 KB bootrom_base 0x0bf90000 -bootrom_size 0x8000 // 32 KB +bootrom_size 0x10000 // 64 KB option_base 0x0 option_size 0x0 flags none - diff --git a/inc/stm32.h b/inc/stm32.h index 856d6e4bd..8557c9ce7 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -117,8 +117,10 @@ enum stm32_chipids { STM32_CHIPID_G4_CAT3 = 0x469, STM32_CHIPID_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ STM32_CHIPID_L4PX = 0x471, /* RM0432, p.2247 */ + STM32_CHIPID_L5x2xx = 0x472, /* RM0438, p.2157 */ STM32_CHIPID_G4_CAT4 = 0x479, STM32_CHIPID_H7Ax = 0x480, /* RM0455, p.2863 */ + STM32_CHIPID_U5x5 = 0x482, /* RM0456, p.2991 */ STM32_CHIPID_H72x = 0x483, /* RM0468, p.3199 */ STM32_CHIPID_WB55 = 0x495, STM32_CHIPID_WLE = 0x497, @@ -196,10 +198,16 @@ enum stm32_chipids { #define STM32L1_RCC_AHBENR 0x4002381C #define STM32L1_RCC_DMAEN 0x30000000 // DMA2EN | DMA1EN +#define STM32L5_RCC_AHB1ENR 0x40021048 // RM0438, p. 91,377 +#define STM32L5_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN // RM0438, p. 378 + #define STM32H7_RCC_AHB1ENR 0x58024538 #define STM32H7_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN #define STM32WB_RCC_AHB1ENR 0x58000048 #define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN +#define STM32L5_PWR_CR1 0x40007000 // RM0438, p. 93,324 +#define STM32L5_PWR_CR1_VOS 8 + #endif // STM32_H diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 5e7ad2e4a..07f824837 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -72,7 +72,7 @@ #define FLASH_L1_FPRG 10 #define FLASH_L1_PROG 3 -// Flash registers common to STM32G0 and STM32G4 series. +// Flash registers common to STM32G0 and STM32G4 series (RM0440, p. 146) #define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) #define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) #define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) @@ -207,6 +207,43 @@ #define STM32L4_FLASH_OPTR_DUALBANK 21 +// Flash registers common to STM32L5 series (RM0438, p. 241) +#define STM32L5_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define STM32L5_FLASH_ACR (STM32L5_FLASH_REGS_ADDR + 0x00) +#define STM32L5_FLASH_NSKEYR (STM32L5_FLASH_REGS_ADDR + 0x08) +#define STM32L5_FLASH_OPTKEYR (STM32L5_FLASH_REGS_ADDR + 0x10) +#define STM32L5_FLASH_NSSR (STM32L5_FLASH_REGS_ADDR + 0x20) +#define STM32L5_FLASH_NSCR (STM32L5_FLASH_REGS_ADDR + 0x28) +#define STM32L5_FLASH_ECCR (STM32L5_FLASH_REGS_ADDR + 0x30) +#define STM32L5_FLASH_OPTR (STM32L5_FLASH_REGS_ADDR + 0x40) + +// FLASH_NSCR (RM0438, p. 242) +#define STM32L5_FLASH_NSCR_NSPG 0 /* Program */ +#define STM32L5_FLASH_NSCR_NSPER 1 /* Page erase */ +#define STM32L5_FLASH_NSCR_NSMER1 2 /* Bank 1 erase */ +#define STM32L5_FLASH_NSCR_NSPNB 3 /* Page number (7 bits) */ +#define STM32L5_FLASH_NSCR_NSBKER 11 /* Bank select for page erase */ +#define STM32L5_FLASH_NSCR_NSMER2 15 /* Bank 2 erase */ +#define STM32L5_FLASH_NSCR_NSSTRT 16 /* Start command */ +#define STM32L5_FLASH_NSCR_NSOPTSTRT 17 /* Start writing option bytes */ +#define STM32L5_FLASH_NSCR_NSEOPIE 24 +#define STM32L5_FLASH_NSCR_NSERRIE 25 +#define STM32L5_FLASH_NSCR_OBL_LAUNCH 27 /* Option bytes reload */ +#define STM32L5_FLASH_NSCR_OPTLOCK 30 /* Lock option bytes */ +#define STM32L5_FLASH_NSCR_NSLOCK 31 /* Lock control register */ + +// FLASH_NSSR (RM0438, p. 241) +#define STM32L5_FLASH_NSSR_NSEOP 0 /* End of Operation */ +#define STM32L5_FLASH_NSSR_NSOPERR 1 +#define STM32L5_FLASH_NSSR_NSPROGERR 3 +#define STM32L5_FLASH_NSSR_NSWRPERR 4 +#define STM32L5_FLASH_NSSR_NSPGAERR 5 +#define STM32L5_FLASH_NSSR_NSSIZERR 6 +#define STM32L5_FLASH_NSSR_NSPGSERR 7 +#define STM32L5_FLASH_NSSR_OPTWERR 12 +#define STM32L5_FLASH_NSSR_BSY 16 /* Busy */ +#define STM32L5_FLASH_NSSR_ERROR_MASK (0x20fa) + // STM32L0x flash register base and offsets RM0090 - DM00031020.pdf #define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 4b8e37fef..cef0b639f 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -254,6 +254,7 @@ int main(int ac, char** av) { if (o.reset) { stlink_reset(sl, RESET_AUTO); + stlink_run(sl, RUN_NORMAL); } err = 0; // success diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 34a8ac573..fe5574706 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -62,6 +62,7 @@ void stlink_close(stlink_t *sl) { sl->backend->close(sl); free(sl); } + // 250 int stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); @@ -74,11 +75,13 @@ int stlink_exit_debug_mode(stlink_t *sl) { return (sl->backend->exit_debug_mode(sl)); } + //248 int stlink_enter_swd_mode(stlink_t *sl) { DLOG("*** stlink_enter_swd_mode ***\n"); return (sl->backend->enter_swd_mode(sl)); } + // 271 // Force the core into the debug mode -> halted state. int stlink_force_debug(stlink_t *sl) { @@ -91,11 +94,13 @@ int stlink_force_debug(stlink_t *sl) { stop_wdg_in_debug(sl); return (0); } + // 251 int stlink_exit_dfu_mode(stlink_t *sl) { DLOG("*** stlink_exit_dfu_mode ***\n"); return (sl->backend->exit_dfu_mode(sl)); } + // 253 int stlink_core_id(stlink_t *sl) { int ret; @@ -115,6 +120,7 @@ int stlink_core_id(stlink_t *sl) { DLOG("core_id = 0x%08x\n", sl->core_id); return (ret); } + // 287 // stlink_chip_id() is called by stlink_load_device_params() // do not call this procedure directly. @@ -132,7 +138,6 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { /* * the chip_id register in the reference manual have * DBGMCU_IDCODE / DBG_IDCODE name - * */ if ((sl->core_id == STM32_CORE_ID_M7F_H7_SWD || sl->core_id == STM32_CORE_ID_M7F_H7_JTAG) && @@ -178,6 +183,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { return (ret); } + // 288 /** * Cortex M tech ref manual, CPUID register description @@ -201,6 +207,7 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { cpuid->revision = raw & 0xf; return (0); } + // 303 /** * Reads and decodes the flash parameters, as dynamically as possible @@ -300,6 +307,7 @@ int stlink_load_device_params(stlink_t *sl) { return (0); } + // 254 int stlink_reset(stlink_t *sl, enum reset_type type) { uint32_t dhcsr; @@ -361,6 +369,81 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { return (0); } + +int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { + int ret; + unsigned timeout; + uint32_t dhcsr, dfsr; + + DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); + + // halt core and enable debugging (if not already done) + // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | + STLINK_REG_DHCSR_C_DEBUGEN); + + // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) + if (halt_on_reset) { + stlink_write_debug32( + sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); + + // clear VCATCH in the DFSR register + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); + } else { + stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, + STLINK_REG_CM3_DEMCR_TRCENA | + STLINK_REG_CM3_DEMCR_VC_HARDERR | + STLINK_REG_CM3_DEMCR_VC_BUSERR); + } + + // clear S_RESET_ST in the DHCSR register + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + + // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) + ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, + STLINK_REG_AIRCR_VECTKEY | + STLINK_REG_AIRCR_SYSRESETREQ); + if (ret) { + ELOG("Soft reset failed: error write to AIRCR\n"); + return (ret); + } + + // waiting for a reset within 500ms + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + timeout = time_ms() + 500; + while (time_ms() < timeout) { + // DDI0337E, p. 10-4, Debug Halting Control and Status Register + dhcsr = STLINK_REG_DHCSR_S_RESET_ST; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { + if (halt_on_reset) { + // waiting halt by the SYSRESETREQ exception + // DDI0403E, p. C1-699, Debug Fault Status Register + dfsr = 0; + stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { + continue; + } + } + timeout = 0; + break; + } + } + + // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) + stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); + + if (timeout) { + ELOG("Soft reset failed: timeout\n"); + return (-1); + } + + return (0); +} + // 255 int stlink_run(stlink_t *sl, enum run_type type) { struct stlink_reg rr; @@ -377,11 +460,13 @@ int stlink_run(stlink_t *sl, enum run_type type) { return (sl->backend->run(sl, type)); } + // 273 int stlink_set_swdclk(stlink_t *sl, int freq_khz) { DLOG("*** set_swdclk ***\n"); return (sl->backend->set_swdclk(sl, freq_khz)); } + // 293 // this function is called by stlink_status() // do not call stlink_core_stat() directly, always use stlink_status() @@ -403,6 +488,7 @@ void stlink_core_stat(stlink_t *sl) { DLOG(" core status: unknown\n"); } } + // 256 int stlink_status(stlink_t *sl) { int ret; @@ -412,6 +498,7 @@ int stlink_status(stlink_t *sl) { stlink_core_stat(sl); return (ret); } + // 257 int stlink_version(stlink_t *sl) { DLOG("*** looking up stlink version ***\n"); @@ -435,6 +522,7 @@ int stlink_version(stlink_t *sl) { return (0); } + // 272 int stlink_target_voltage(stlink_t *sl) { int voltage = -1; @@ -454,16 +542,19 @@ int stlink_target_voltage(stlink_t *sl) { return (voltage); } + // 299 bool stlink_is_core_halted(stlink_t *sl) { stlink_status(sl); return (sl->core_stat == TARGET_HALTED); } + // 269 int stlink_step(stlink_t *sl) { DLOG("*** stlink_step ***\n"); return (sl->backend->step(sl)); } + // 270 int stlink_current_mode(stlink_t *sl) { int mode = sl->backend->current_mode(sl); @@ -483,20 +574,24 @@ int stlink_current_mode(stlink_t *sl) { DLOG("stlink mode: unknown!\n"); return (STLINK_DEV_UNKNOWN_MODE); } + // 274 int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { DLOG("*** stlink_trace_enable ***\n"); return (sl->backend->trace_enable(sl, frequency)); } + // 275 int stlink_trace_disable(stlink_t *sl) { DLOG("*** stlink_trace_disable ***\n"); return (sl->backend->trace_disable(sl)); } + // 276 int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { return (sl->backend->trace_read(sl, buf, size)); } + // 294 void stlink_print_data(stlink_t *sl) { if (sl->q_len <= 0 || sl->verbose < UDEBUG) { @@ -523,9 +618,9 @@ void stlink_print_data(stlink_t *sl) { // DLOG("\n\n"); fprintf(stderr, "\n"); } + // 283 -int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, - stm32_addr_t addr) { +int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr) { // write the file in sram at addr int error = -1; @@ -581,6 +676,7 @@ int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, on_error: return (error); } + //284 int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { // write the file in sram at addr @@ -655,9 +751,9 @@ int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { unmap_file(&mf); return (error); } + // 302 -int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, - stm32_addr_t addr, size_t size) { +int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t addr, size_t size) { // read size bytes from addr to file ILOG("read from address %#010x size %u\n", addr, (unsigned)size); @@ -689,9 +785,9 @@ int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, close(fd); return (error); } + // 300 -int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, - size_t size) { +int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, size_t size) { // write the buffer right after the loader int ret = 0; size_t chunk = size & ~0x3; @@ -709,6 +805,7 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, return (ret); } + // 291 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { if ((sl->chip_id == STM32_CHIPID_F2) || @@ -749,6 +846,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { return ((uint32_t)sl->flash_pgsz); } + // 279 int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, size_t *size, uint32_t *begin) { @@ -910,6 +1008,7 @@ int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, return (res); } + // 280 uint8_t stlink_get_erased_pattern(stlink_t *sl) { if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { @@ -1024,79 +1123,6 @@ int stlink_jtag_reset(stlink_t *sl, int value) { return (sl->backend->jtag_reset(sl, value)); } -int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { - int ret; - unsigned timeout; - uint32_t dhcsr, dfsr; - - DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); - - // halt core and enable debugging (if not already done) - // C_DEBUGEN is required to Halt on reset (DDI0337E, p. 10-6) - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_DEBUGEN); - - // enable Halt on reset by set VC_CORERESET and TRCENA (DDI0337E, p. 10-10) - if (halt_on_reset) { - stlink_write_debug32( - sl, STLINK_REG_CM3_DEMCR, - STLINK_REG_CM3_DEMCR_TRCENA | STLINK_REG_CM3_DEMCR_VC_HARDERR | - STLINK_REG_CM3_DEMCR_VC_BUSERR | STLINK_REG_CM3_DEMCR_VC_CORERESET); - - // clear VCATCH in the DFSR register - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); - } else { - stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, - STLINK_REG_CM3_DEMCR_TRCENA | - STLINK_REG_CM3_DEMCR_VC_HARDERR | - STLINK_REG_CM3_DEMCR_VC_BUSERR); - } - - // clear S_RESET_ST in the DHCSR register - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - - // soft reset (core reset) by SYSRESETREQ (DDI0337E, p. 8-23) - ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, - STLINK_REG_AIRCR_VECTKEY | - STLINK_REG_AIRCR_SYSRESETREQ); - if (ret) { - ELOG("Soft reset failed: error write to AIRCR\n"); - return (ret); - } - - // waiting for a reset within 500ms - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - timeout = time_ms() + 500; - while (time_ms() < timeout) { - // DDI0337E, p. 10-4, Debug Halting Control and Status Register - dhcsr = STLINK_REG_DHCSR_S_RESET_ST; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0) { - if (halt_on_reset) { - // waiting halt by the SYSRESETREQ exception - // DDI0403E, p. C1-699, Debug Fault Status Register - dfsr = 0; - stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); - if ((dfsr & STLINK_REG_DFSR_VCATCH) == 0) { - continue; - } - } - timeout = 0; - break; - } - } - - // reset DFSR register. DFSR is power-on reset only (DDI0337H, p. 7-5) - stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); - - if (timeout) { - ELOG("Soft reset failed: timeout\n"); - return (-1); - } - - return (0); -} /** * Decode the version bits, originally from -sg, verified with usb * @param sl stlink context, assumed to contain valid data in the buffer @@ -1283,8 +1309,7 @@ static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, } static bool stlink_fread_worker(void *arg, uint8_t *block, ssize_t len) { - struct stlink_fread_worker_arg *the_arg = - (struct stlink_fread_worker_arg *)arg; + struct stlink_fread_worker_arg *the_arg = (struct stlink_fread_worker_arg *)arg; if (write(the_arg->fd, block, len) != len) { fprintf(stderr, "write() != aligned_size\n"); @@ -1315,8 +1340,7 @@ static uint8_t stlink_parse_hex(const char *hex) { return ((d[0] << 4) | (d[1])); } -static bool -stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { +static bool stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { uint32_t addr = the_arg->addr; uint8_t sum = 2 + 4 + (uint8_t)((addr & 0xFF000000) >> 24) + (uint8_t)((addr & 0x00FF0000) >> 16); @@ -1330,8 +1354,7 @@ stlink_fread_ihex_newsegment(struct stlink_fread_ihex_worker_arg *the_arg) { return (true); } -static bool -stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { +static bool stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the_arg) { uint8_t count = the_arg->buf_pos; if (count == 0) { @@ -1399,8 +1422,7 @@ static bool stlink_fread_ihex_worker(void *arg, uint8_t *block, ssize_t len) { return (true); } -static bool -stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { +static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *the_arg) { if (!stlink_fread_ihex_writeline(the_arg)) { return (false); } diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 0ed4734ad..5b8075ea7 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -38,15 +38,17 @@ uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { reg = FLASH_F7_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - reg = STM32L4_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - reg = STM32WB_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + reg = STM32L5_FLASH_NSCR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + reg = STM32WB_FLASH_CR; } else { reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; } @@ -60,7 +62,7 @@ uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { } void lock_flash(stlink_t *sl) { - uint32_t cr_lock_shift, cr_reg, n, cr2_reg = 0; + uint32_t cr_lock_shift = 0, cr_reg = 0, n = 0, cr2_reg = 0; uint32_t cr_mask = 0xffffffffu; if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { @@ -76,21 +78,24 @@ void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + cr_lock_shift = STM32L5_FLASH_NSCR_NSLOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr2_reg = FLASH_H7_CR2; } @@ -118,21 +123,23 @@ static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_reg = STM32WB_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + sr_reg = STM32L5_FLASH_NSSR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sr_reg = STM32WB_FLASH_SR; } else { ELOG("method 'write_flash_sr' is unsupported\n"); return (-1); @@ -156,6 +163,12 @@ void clear_flash_error(stlink_t *sl) { case STM32_FLASH_TYPE_G4: write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); break; + case STM32_FLASH_TYPE_H7: + write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); + } + break; case STM32_FLASH_TYPE_L0_L1: if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { write_flash_sr(sl, BANK_1, STM32L1_FLASH_SR_ERROR_MASK); @@ -166,11 +179,8 @@ void clear_flash_error(stlink_t *sl) { case STM32_FLASH_TYPE_L4: write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); break; - case STM32_FLASH_TYPE_H7: - write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); - } + case STM32_FLASH_TYPE_L5_U5: + write_flash_sr(sl, BANK_1, STM32L5_FLASH_NSSR_ERROR_MASK); break; case STM32_FLASH_TYPE_WB_WL: write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); @@ -186,21 +196,23 @@ uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_reg = FLASH_F7_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = STM32Gx_FLASH_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_reg = STM32WB_FLASH_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + sr_reg = STM32L4_FLASH_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + sr_reg = STM32L5_FLASH_NSSR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sr_reg = STM32WB_FLASH_SR; } else { ELOG("method 'read_flash_sr' is unsupported\n"); return (-1); @@ -222,15 +234,17 @@ unsigned int is_flash_busy(stlink_t *sl) { sr_busy_shift = FLASH_F4_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { sr_busy_shift = FLASH_F7_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - sr_busy_shift = STM32L4_FLASH_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { sr_busy_shift = STM32Gx_FLASH_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_busy_shift = STM32WB_FLASH_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + sr_busy_shift = STM32L4_FLASH_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + sr_busy_shift = STM32L5_FLASH_NSSR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sr_busy_shift = STM32WB_FLASH_SR_BSY; } else { ELOG("method 'is_flash_busy' is unsupported\n"); return (-1); @@ -286,6 +300,13 @@ int check_flash_error(stlink_t *sl) { PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); break; + case STM32_FLASH_TYPE_H7: + res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; + } + WRPERR = (1 << FLASH_H7_SR_WRPERR); + break; case STM32_FLASH_TYPE_L0_L1: res = read_flash_sr(sl, BANK_1); if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { @@ -303,12 +324,11 @@ int check_flash_error(stlink_t *sl) { PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); break; - case STM32_FLASH_TYPE_H7: - res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; - } - WRPERR = (1 << FLASH_H7_SR_WRPERR); + case STM32_FLASH_TYPE_L5_U5: + res = read_flash_sr(sl, BANK_1) & STM32L5_FLASH_NSSR_ERROR_MASK; + WRPERR = (1 << STM32L5_FLASH_NSSR_NSWRPERR); + PROGERR = (1 << STM32L5_FLASH_NSSR_NSPROGERR); + PGAERR = (1 << STM32L5_FLASH_NSSR_NSPGAERR); break; case STM32_FLASH_TYPE_WB_WL: res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; @@ -357,22 +377,25 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_lock_shift = FLASH_F7_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = FLASH_H7_CR1; + cr_lock_shift = FLASH_H7_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = STM32L0_FLASH_PELOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = STM32L4_FLASH_CR; cr_lock_shift = STM32L4_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + cr_lock_shift = STM32L5_FLASH_NSCR_NSLOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; cr_lock_shift = STM32WB_FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = FLASH_H7_CR1; - cr_lock_shift = FLASH_H7_CR_LOCK; } else { ELOG("unsupported flash method, abort\n"); return (-1); @@ -400,22 +423,32 @@ static void unlock_flash(stlink_t *sl) { key_reg = FLASH_F4_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { key_reg = FLASH_F7_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; - flash_key1 = FLASH_L0_PEKEY1; - flash_key2 = FLASH_L0_PEKEY2; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - key_reg = STM32L4_FLASH_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { key_reg = STM32Gx_FLASH_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - key_reg = STM32WB_FLASH_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { key_reg = FLASH_H7_KEYR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { key2_reg = FLASH_H7_KEYR2; } + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; + flash_key1 = FLASH_L0_PEKEY1; + flash_key2 = FLASH_L0_PEKEY2; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + key_reg = STM32L4_FLASH_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + // Set voltage scaling to range 0 to perform flash operations (RM0438 p. 183) + uint32_t mask = (0b11 << STM32L5_PWR_CR1_VOS); + uint32_t val; + stlink_read_debug32(sl, STM32L5_PWR_CR1, &val); + if ((val & mask) > (1 << STM32L5_PWR_CR1_VOS)) { + val &= ~mask; + stlink_write_debug32(sl, STM32L5_PWR_CR1, val); + } + key_reg = STM32L5_FLASH_NSKEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + key_reg = STM32WB_FLASH_KEYR; } else { ELOG("unsupported flash method, abort\n"); return; @@ -464,6 +497,17 @@ int lock_flash_option(stlink_t *sl) { optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optcr2_reg = FLASH_H7_OPTCR2; + break; case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; @@ -472,21 +516,14 @@ int lock_flash_option(stlink_t *sl) { optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + case STM32_FLASH_TYPE_L5_U5: + optcr_reg = STM32L5_FLASH_NSCR; + optlock_shift = STM32L5_FLASH_NSCR_OPTLOCK; break; case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optcr2_reg = FLASH_H7_OPTCR2; - break; default: ELOG("unsupported flash method, abort\n"); return -1; @@ -537,6 +574,15 @@ static bool is_flash_option_locked(stlink_t *sl) { optcr_reg = FLASH_F7_OPTCR; optlock_shift = FLASH_F7_OPTCR_LOCK; break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + optcr_reg = STM32Gx_FLASH_CR; + optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + break; + case STM32_FLASH_TYPE_H7: + optcr_reg = FLASH_H7_OPTCR; + optlock_shift = FLASH_H7_OPTCR_OPTLOCK; + break; case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; optlock_shift = STM32L0_FLASH_OPTLOCK; @@ -545,19 +591,14 @@ static bool is_flash_option_locked(stlink_t *sl) { optcr_reg = STM32L4_FLASH_CR; optlock_shift = STM32L4_FLASH_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + case STM32_FLASH_TYPE_L5_U5: + optcr_reg = STM32L5_FLASH_NSCR; + optlock_shift = STM32L5_FLASH_NSCR_OPTLOCK; break; case STM32_FLASH_TYPE_WB_WL: optcr_reg = STM32WB_FLASH_CR; optlock_shift = STM32WB_FLASH_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_H7: - optcr_reg = FLASH_H7_OPTCR; - optlock_shift = FLASH_H7_OPTCR_OPTLOCK; - break; default: ELOG("unsupported flash method, abort\n"); return -1; @@ -590,6 +631,15 @@ static int unlock_flash_option(stlink_t *sl) { case STM32_FLASH_TYPE_F7: optkey_reg = FLASH_F7_OPT_KEYR; break; + case STM32_FLASH_TYPE_G0: + case STM32_FLASH_TYPE_G4: + optkey_reg = STM32Gx_FLASH_OPTKEYR; + break; + case STM32_FLASH_TYPE_H7: + optkey_reg = FLASH_H7_OPT_KEYR; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) + optkey2_reg = FLASH_H7_OPT_KEYR2; + break; case STM32_FLASH_TYPE_L0_L1: optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; optkey1 = FLASH_L0_OPTKEY1; @@ -598,18 +648,12 @@ static int unlock_flash_option(stlink_t *sl) { case STM32_FLASH_TYPE_L4: optkey_reg = STM32L4_FLASH_OPTKEYR; break; - case STM32_FLASH_TYPE_G0: - case STM32_FLASH_TYPE_G4: - optkey_reg = STM32Gx_FLASH_OPTKEYR; + case STM32_FLASH_TYPE_L5_U5: + optkey_reg = STM32L5_FLASH_OPTKEYR; break; case STM32_FLASH_TYPE_WB_WL: optkey_reg = STM32WB_FLASH_OPT_KEYR; break; - case STM32_FLASH_TYPE_H7: - optkey_reg = FLASH_H7_OPT_KEYR; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) - optkey2_reg = FLASH_H7_OPT_KEYR2; - break; default: ELOG("unsupported flash method, abort\n"); return (-1); @@ -672,16 +716,18 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { cr_reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; bit = FLASH_H7_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; } else { cr_reg = FLASH_CR; } @@ -744,6 +790,8 @@ static void set_flash_cr_per(stlink_t *sl, unsigned bank) { if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { @@ -761,6 +809,8 @@ static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = STM32WB_FLASH_CR; } else { @@ -796,19 +846,22 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; cr_strt = 1 << FLASH_F7_CR_STRT; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_strt = (1 << STM32L4_FLASH_CR_STRT); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_strt = (1 << STM32Gx_FLASH_CR_STRT); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_strt = (1 << STM32WB_FLASH_CR_STRT); } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_strt = (1 << STM32L4_FLASH_CR_STRT); + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + cr_strt = (1 << STM32L5_FLASH_NSCR_NSSTRT); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + cr_strt = (1 << STM32WB_FLASH_CR_STRT); } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; cr_strt = (1 << FLASH_CR_STRT); @@ -830,28 +883,30 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { cr_reg = FLASH_F7_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); - cr_pg = (1 << STM32L4_FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; cr_mer = (1 << STM32Gx_FLASH_CR_MER1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); } - - cr_pg = (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_mer = (1 << FLASH_H7_CR_BER); cr_pg = (1 << FLASH_H7_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); + cr_pg = (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + cr_mer = (1 << STM32L5_FLASH_NSCR_NSMER1) | (1 << STM32L5_FLASH_NSCR_NSMER2); + cr_pg = (1 << STM32L5_FLASH_NSCR_NSPG); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + cr_mer = (1 << FLASH_CR_MER); + cr_pg = (1 << FLASH_CR_PG); } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; cr_mer = (1 << FLASH_CR_MER); @@ -993,25 +1048,16 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); val |= (1 << 0) | (1 << 1) | (1 << 2); stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5 || + sl->flash_type == STM32_FLASH_TYPE_WB_WL) { uint32_t val; unlock_flash_if(sl); set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit // set the page to erase - if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - - // sec 3.10.5 - PNB[7:0] is offset by 3. - val &= ~(0xFF << 3); // Clear previously set page number (if any) - val |= ((flash_page & 0xFF) << 3); - - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); - } else if (sl->flash_type == STM32_FLASH_TYPE_G0) { + if (sl->flash_type == STM32_FLASH_TYPE_G0) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); @@ -1027,6 +1073,34 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val &= ~(0x7F << 3); val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + uint32_t flash_page; + stlink_read_debug32(sl, STM32L5_FLASH_NSCR, &val); + if (sl->flash_pgsz == 0x800 && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) { + flash_page = (flashaddr - STM32_FLASH_BASE - sl->flash_size/2) / + (uint32_t)(sl->flash_pgsz); + // set bank 2 for erasure + val |= (1 << STM32L5_FLASH_NSCR_NSBKER); + } else { + flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + // set bank 1 for erasure + val &= ~(1 << STM32L5_FLASH_NSCR_NSBKER); + } + // sec 6.9.9 + val &= ~(0x7F << 3); + val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); + stlink_write_debug32(sl, STM32L5_FLASH_NSCR, val); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + uint32_t flash_page = + ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + + // sec 3.10.5 - PNB[7:0] is offset by 3. + val &= ~(0xFF << 3); // Clear previously set page number (if any) + val |= ((flash_page & 0xFF) << 3); + + stlink_write_debug32(sl, STM32WB_FLASH_CR, val); } set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit diff --git a/src/stlink-lib/flashloader.c b/src/stlink-lib/flashloader.c index d9542ebbc..7164983cd 100644 --- a/src/stlink-lib/flashloader.c +++ b/src/stlink-lib/flashloader.c @@ -46,8 +46,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } if (ret) { - WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", - addr + count * pagesize); + WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", addr + count * pagesize); break; } @@ -84,6 +83,9 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { cr_reg = STM32L4_FLASH_CR; x &= ~STM32L4_FLASH_CR_OPBITS; x |= (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = STM32Gx_FLASH_CR; @@ -136,6 +138,10 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { rcc_dma_mask = STM32L0_RCC_DMAEN; } break; + case STM32_FLASH_TYPE_L5_U5: + rcc = STM32L5_RCC_AHB1ENR; + rcc_dma_mask = STM32L5_RCC_DMAEN; + break; case STM32_FLASH_TYPE_H7: rcc = STM32H7_RCC_AHB1ENR; rcc_dma_mask = STM32H7_RCC_DMAEN; @@ -216,8 +222,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { set_flash_cr_pg(sl, BANK_1); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - ILOG("Starting Flash write for WB/G0/G4\n"); + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + ILOG("Starting Flash write for WB/G0/G4/L5/U5\n"); unlock_flash_if(sl); // unlock flash if necessary set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit @@ -320,14 +327,15 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, } } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5) { DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(off / sl->flash_pgsz + 1), (unsigned int)(len / sl->flash_pgsz)); fflush(stdout); } @@ -368,7 +376,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz), + (unsigned int)(off / sl->flash_pgsz + 1), (unsigned int)(len / sl->flash_pgsz)); fflush(stdout); } @@ -451,11 +459,12 @@ int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4) || - (sl->flash_type == STM32_FLASH_TYPE_WB_WL) || (sl->flash_type == STM32_FLASH_TYPE_G0) || (sl->flash_type == STM32_FLASH_TYPE_G4) || - (sl->flash_type == STM32_FLASH_TYPE_H7)) { + (sl->flash_type == STM32_FLASH_TYPE_H7) || + (sl->flash_type == STM32_FLASH_TYPE_L4) || + (sl->flash_type == STM32_FLASH_TYPE_L5_U5) || + (sl->flash_type == STM32_FLASH_TYPE_WB_WL)) { clear_flash_cr_pg(sl, BANK_1); if ((sl->flash_type == STM32_FLASH_TYPE_H7 && diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 3d332f49d..2d4898001 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -510,8 +510,7 @@ static int stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t case FLASH_H7_REGS_ADDR + 0x3c: // FLASH_WPSN_PRG1 case FLASH_H7_REGS_ADDR + 0x44: // FLASH_BOOT_PRG /* Write to FLASH_xxx_PRG registers */ - write_uint32((unsigned char *)&data, - *(uint32_t *)(base)); // write options bytes + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); // write options bytes WLOG("Writing option bytes %#10x to %#10x\n", data, addr); @@ -534,8 +533,7 @@ static int stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t /* Check for errors */ if ((val & (1 << FLASH_H7_OPTSR_OPTCHANGEERR)) != 0) { - stlink_write_debug32(sl, FLASH_H7_OPTCCR, - 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); + stlink_write_debug32(sl, FLASH_H7_OPTCCR, 1 << FLASH_H7_OPTCCR_CLR_OPTCHANGEERR); return -1; } break; @@ -753,8 +751,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ui int ret = -1; if (sl->option_base == 0) { - ELOG( - "Option bytes writing is currently not supported for connected chip\n"); + ELOG("Option bytes writing is currently not supported for connected chip\n"); return (-1); } @@ -771,8 +768,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ui wait_flash_busy(sl); if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); return (-1); } @@ -809,8 +805,7 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ui ret = stlink_write_option_bytes_wb(sl, addr, base, len); break; default: - ELOG("Option bytes writing is currently not implemented for connected " - "chip\n"); + ELOG("Option bytes writing is currently not implemented for connected chip\n"); break; } @@ -892,8 +887,7 @@ int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) { wait_flash_busy(sl); if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); return -1; } @@ -915,8 +909,7 @@ int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) { stlink_write_option_control_register_wb(sl, option_cr); break; default: - ELOG("Option control register writing is currently not implemented for " - "connected chip\n"); + ELOG("Option control register writing is currently not implemented for connected chip\n"); break; } @@ -965,8 +958,7 @@ int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1) wait_flash_busy(sl); if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); return -1; } @@ -1050,8 +1042,7 @@ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { */ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { if (sl->option_base == 0) { - ELOG("Option bytes boot address read is currently not supported for " - "connected chip\n"); + ELOG("Option bytes boot address read is currently not supported for connected chip\n"); return -1; } @@ -1076,8 +1067,7 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boo wait_flash_busy(sl); if (unlock_flash_if(sl)) { - ELOG("Flash unlock failed! System reset required to be able to unlock it " - "again!\n"); + ELOG("Flash unlock failed! System reset required to be able to unlock it again!\n"); return -1; } @@ -1091,8 +1081,7 @@ int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boo ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); break; default: - ELOG("Option bytes boot address writing is currently not implemented for " - "connected chip\n"); + ELOG("Option bytes boot address writing is currently not implemented for connected chip\n"); break; } From 893523d74ed83abf26b994cb7e608f87b39bfda0 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 1 Jan 2023 16:27:13 +0100 Subject: [PATCH 1345/1435] Updated CHANGELOG.md --- CHANGELOG.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 82656d50b..ddd795c37 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -17,7 +17,7 @@ Features: - Added chip-IDs for STM32G0B0/G0B1/G0C1/G050/G051/G061 ([#1140](https://github.com/stlink-org/stlink/pull/1140)) - Added option byte info for STM32F411XX ([#1141](https://github.com/stlink-org/stlink/pull/1141)) - Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) -- [STM32H72X/3X]: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) +- STM32H72X/3X: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) - Added support for STM32WLEx ([#1173](https://github.com/stlink-org/stlink/pull/1173), [#1273](https://github.com/stlink-org/stlink/pull/1273)) - Added support for STLINK-V3 devices with no MSD ([#1185](https://github.com/stlink-org/stlink/pull/1185)) - Updated gdb-server.c to allow external memory access on STM32H73xx ([#1196](https://github.com/stlink-org/stlink/pull/1196), [#1197](https://github.com/stlink-org/stlink/pull/1197)) @@ -51,7 +51,7 @@ Fixes: - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) - Fixed clearance of the H7 dual bank flag ([#1146](https://github.com/stlink-org/stlink/pull/1146), [#1147](https://github.com/stlink-org/stlink/pull/1147)) - Fix for 'libusb_devices were leaked' when no ST-LINK programmer was found ([#1150](https://github.com/stlink-org/stlink/pull/1150)) -- Set of fixes and improvements ([#1154](https://github.com/stlink-org/stlink/pull/1154)) +- Set of fixes and improvements ([#1153](https://github.com/stlink-org/stlink/pull/1153), [#1154](https://github.com/stlink-org/stlink/pull/1154)) - Removed limit check for WRITEMEM_32BIT ([#1157](https://github.com/stlink-org/stlink/pull/1157)) - Fixed get_stm32l0_flash_base address for STM32L152RE ([#1161](https://github.com/stlink-org/stlink/pull/1161), [#1162](https://github.com/stlink-org/stlink/pull/1162)) - Fixed segfault if chip was not found in chip config files ([#1138](https://github.com/stlink-org/stlink/pull/1138), [#1163](https://github.com/stlink-org/stlink/pull/1163), [#1165](https://github.com/stlink-org/stlink/pull/1165), [#1166](https://github.com/stlink-org/stlink/pull/1166), [#1170](https://github.com/stlink-org/stlink/pull/1170)) @@ -65,7 +65,7 @@ Fixes: - Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) - Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) - Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214) -- st-trace: Fixed clock issues ([#1251](https://github.com/stlink-org/stlink/pull/1251), [#1252](https://github.com/stlink-org/stlink/pull/1252)) +- st-trace: Fixed clock issues ([#1248](https://github.com/stlink-org/stlink/pull/1248), [#1251](https://github.com/stlink-org/stlink/pull/1251), [#1252](https://github.com/stlink-org/stlink/pull/1252)) - Fixed compilation with gcc-12 ([#1257](https://github.com/stlink-org/stlink/pull/1257), [#1267](https://github.com/stlink-org/stlink/pull/1267)) - Fixed flash regs addr for STM32L152RET6 in common_flash.c ([#1265](https://github.com/stlink-org/stlink/pull/1265)) - Fixed flash, dbgmcu and rcc registers for STM32L1 ([#1266](https://github.com/stlink-org/stlink/pull/1266)) From 54e4bc5251933bbd6206d3548918e52a1b85d66c Mon Sep 17 00:00:00 2001 From: John Hall Date: Sun, 1 Jan 2023 16:01:58 -0800 Subject: [PATCH 1346/1435] Updating windows signal handling to not terminate the application before cleanup. --- src/st-trace/trace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 9fcf8e358..e0bf3c88d 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -88,7 +88,7 @@ static void abort_trace() { g_abort_trace = true; } BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { (void)fdwCtrlType; abort_trace(); - return FALSE; + return TRUE; } #endif From 750a92cdc40ef33d0e3fc7208da9c30496d22aae Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 2 Jan 2023 11:59:26 +0100 Subject: [PATCH 1347/1435] Log message improvements for st-flash --- src/st-flash/flash.c | 1 + src/stlink-lib/common.c | 8 +++----- src/stlink-lib/common_flash.c | 2 +- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index cef0b639f..39b31f219 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -179,6 +179,7 @@ int main(int ac, char** av) { printf("stlink_erase_flash_mass() == -1\n"); goto on_error; } + printf("Mass erase completed successfully.\n"); } else if (o.cmd == CMD_RESET) { if (stlink_reset(sl, RESET_AUTO)) { printf("Failed to reset device\n"); diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index fe5574706..cb037fb2f 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -342,11 +342,9 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { dhcsr = 0; int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) { - // reset not done yet - // try reset through AIRCR so that NRST does not need to be connected - - WLOG("NRST is not connected\n"); - DLOG("Using reset through SYSRESETREQ\n"); + // reset not done yet --> try reset through AIRCR so that NRST does not need to be connected + ILOG("NRST is not connected --> using software reset via AIRCR\n"); + DLOG("NRST not connected --> Reset through SYSRESETREQ\n"); return stlink_soft_reset(sl, 0); } diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 5b8075ea7..e84b307eb 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -739,7 +739,7 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { static void wait_flash_busy_progress(stlink_t *sl) { int i = 0; - fprintf(stdout, "Mass erasing"); + fprintf(stdout, "Mass erasing..."); fflush(stdout); while (is_flash_busy(sl)) { From 2a8a36efba2cf6bae3506f0d92c24ebea46674ba Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 2 Jan 2023 12:21:18 +0100 Subject: [PATCH 1348/1435] Updated GitHub Actions C/C++ CI workflow --- .github/workflows/c-cpp.yml | 106 +++++++++++++++++++++++++++++++++--- 1 file changed, 98 insertions(+), 8 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index 8e798269b..fe07c6e44 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -15,7 +15,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: install dependencies - run: sudo apt update && sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-8 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -35,7 +35,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: install dependencies - run: sudo apt update && sudo apt-get install gcc-6 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install gcc-8 libusb-1.0.0-dev libgtk-3-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -150,7 +150,7 @@ jobs: steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install clang-12 libusb-1.0.0-dev libgtk-3-dev rpm - name: make debug run: sudo make clean && make debug - name: make test @@ -170,7 +170,97 @@ jobs: steps: - uses: actions/checkout@v2 - name: Install dependencies - run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm + run: sudo apt update && sudo apt-get install clang-12 libusb-1.0.0-dev libgtk-3-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_linux_22_04_64_gcc: + name: ubuntu-22.04 gcc + runs-on: ubuntu-22.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt update && sudo apt-get install gcc-12 libusb-1.0.0-dev libgtk-4-dev rpm + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_linux_22_04_32_gcc: + name: ubuntu-22.04 gcc 32-bit + runs-on: ubuntu-22.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt update && sudo apt-get install gcc-12 libusb-1.0.0-dev libgtk-4-dev rpm + - name: Set compiler flags + run: | + CFLAGS="$CFLAGS -m32" + CXXFLAGS="$CXXFLAGS -m32" + LDFLAGS="$LDFLAGS -m32" + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_linux_22_04_64_clang: + name: ubuntu-22.04 clang + runs-on: ubuntu-22.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt update && sudo apt-get install clang-14 libusb-1.0.0-dev libgtk-4-dev rpm + - name: make debug + run: sudo make clean && make debug + - name: make test + run: sudo make clean && make test + - name: make release + run: sudo make clean && make release + - name: sudo make install + run: sudo make clean && sudo make install + - name: sudo make package + run: sudo make package + - name: sudo make uninstall + run: sudo make uninstall && sudo make clean + + job_linux_22_04_32_clang: + name: ubuntu-22.04 clang 32-bit + runs-on: ubuntu-22.04 + steps: + - uses: actions/checkout@v2 + - name: Install dependencies + run: sudo apt update && sudo apt-get install clang-14 libusb-1.0.0-dev libgtk-4-dev rpm - name: Set compiler flags run: | CFLAGS="$CFLAGS -m32" @@ -190,13 +280,13 @@ jobs: run: sudo make uninstall && sudo make clean # Linux MinGW cross compliation -# job_linux_20_04_cross: -# name: ubuntu-20.04 mingw64 -# runs-on: ubuntu-20.04 +# job_linux_22_04_cross: +# name: ubuntu-22.04 mingw64 +# runs-on: ubuntu-22.04 # steps: # - uses: actions/checkout@v2 # - name: Install dependencies -# run: sudo apt-get install gcc-10 libusb-1.0.0-dev libgtk-3-dev rpm mingw-w64 +# run: sudo apt-get install gcc-12 libusb-1.0.0-dev libgtk-4-dev rpm mingw-w64 # - name: Building Release for Windows (x86-64) ... # run: sudo mkdir -p build-mingw && cd build-mingw && sudo cmake \ # -DCMAKE_SYSTEM_NAME=Windows \ From 61ff09e5274d46a46ae58bc4ffe44fe90a887ea6 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 14 Jan 2023 12:14:35 +0100 Subject: [PATCH 1349/1435] [doc] End of support for macOS (Closes #1296) --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 571db49fd..661a60764 100644 --- a/README.md +++ b/README.md @@ -84,7 +84,7 @@ We recommend to install `stlink-tools` from the package repository of the used d - RedHat/CentOS 8: Users can install from [EPEL repository](https://src.fedoraproject.org/rpms/stlink/branch/epel8) - FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) -- MacOS: Users can open a terminal window and then follow the same procedure as for installing on Linux +- MacOS: **Support for macOS will end with v1.7.1.** Please use v1.7.0 (current ***master*** branch) and the related documentation instead. ## Installation from source (advanced users) From 82fb1cc773bd481c93c8b7260e1d64cb020f20b9 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 15 Jan 2023 14:14:25 +0100 Subject: [PATCH 1350/1435] Updated header files in CMakeLists.txt --- CMakeLists.txt | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index b25291992..7d8bce8cf 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -166,35 +166,41 @@ add_subdirectory(inc) set(STLINK_HEADERS inc/backend.h inc/stlink.h - src/stlink-lib/common_flash.h + inc/stm32.h + inc/stm32flash.h src/stlink-lib/calculate.h - src/stlink-lib/commands.h - src/stlink-lib/libusb_settings.h - src/stlink-lib/reg.h src/stlink-lib/chipid.h + src/stlink-lib/commands.h + src/stlink-lib/common_flash.h + src/stlink-lib/common.h src/stlink-lib/flash_loader.h + src/stlink-lib/flashloader.h + src/stlink-lib/helper.h + src/stlink-lib/libusb_settings.h src/stlink-lib/logging.h + src/stlink-lib/map_file.h src/stlink-lib/md5.h + src/stlink-lib/option_bytes.h + src/stlink-lib/reg.h src/stlink-lib/sg.h src/stlink-lib/usb.h - src/stlink-lib/helper.h ) set(STLINK_SOURCE - src/stlink-lib/read_write.c - src/stlink-lib/common.c - src/stlink-lib/option_bytes.c - src/stlink-lib/common_flash.c - src/stlink-lib/map_file.c - src/stlink-lib/flashloader.c src/stlink-lib/calculate.c src/stlink-lib/chipid.c + src/stlink-lib/common_flash.c + src/stlink-lib/common.c src/stlink-lib/flash_loader.c + src/stlink-lib/flashloader.c + src/stlink-lib/helper.c src/stlink-lib/logging.c + src/stlink-lib/map_file.c src/stlink-lib/md5.c + src/stlink-lib/option_bytes.c + src/stlink-lib/read_write.c src/stlink-lib/sg.c src/stlink-lib/usb.c - src/stlink-lib/helper.c ) if (WIN32) From 1bec78c4289ec82f8e43565d610489e8782d5ce6 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 15 Jan 2023 14:20:48 +0100 Subject: [PATCH 1351/1435] Updated libusb checksum for WIN32 --- cmake/modules/Findlibusb.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index 7442c8cc4..fbbda5ba3 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -72,7 +72,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to message(STATUS "downloading libusb ${LIBUSB_WIN_VERSION}") file(DOWNLOAD https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download - ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 cf3d38d2ff053ef343d10c0b8b0950c2 + ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 aabe177bde869bfad34278335eaf8955 ) endif () From c18293a82e9fa98c34f99f31217959c554197738 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 13 Feb 2023 23:59:11 +0100 Subject: [PATCH 1352/1435] Minor fixes - Updated Standards-Version for deb-package - Fix for strcmp(value, "L4") in chipid.c - Minor formatting fixes --- cmake/packaging/deb/control | 2 +- src/stlink-lib/chipid.c | 422 ++++++++++++++++++------------------ 2 files changed, 212 insertions(+), 212 deletions(-) diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index 7c8d13e47..2ed3b6b11 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -2,7 +2,7 @@ Source: stlink Priority: optional Maintainer: Nightwalker-87 Build-Depends: cmake (>= 3.10.2), dh-cmake, debhelper (>= 9), libusb-1.0-0-dev (>= 1.0.21), libgtk-3-dev (>= 3.22.30) -Standards-Version: 4.5.0 +Standards-Version: 4.6.2 Rules-Requires-Root: no Section: electronics Homepage: https://github.com/stlink-org/stlink diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 51a1200ad..075c19c17 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,248 +1,248 @@ -#include -#include #include "chipid.h" +#include +#include -#include +#include #include #include -#include #include +#include static struct stlink_chipid_params *devicelist; -void dump_a_chip (struct stlink_chipid_params *dev) { - DLOG("# Device Type: %s\n", dev->dev_type); - DLOG("# Reference Manual: RM%s\n", dev->ref_manual_id); - DLOG("#\n"); - DLOG("chip_id 0x%x\n", dev->chip_id); - DLOG("flash_type %d\n", dev->flash_type); - DLOG("flash_size_reg 0x%x\n", dev->flash_size_reg); - DLOG("flash_pagesize 0x%x\n", dev->flash_pagesize); - DLOG("sram_size 0x%x\n", dev->sram_size); - DLOG("bootrom_base 0x%x\n", dev->bootrom_base); - DLOG("bootrom_size 0x%x\n", dev->bootrom_size); - DLOG("option_base 0x%x\n", dev->option_base); - DLOG("option_size 0x%x\n", dev->option_size); - DLOG("flags %d\n\n", dev->flags); +void dump_a_chip(struct stlink_chipid_params *dev) { + DLOG("# Device Type: %s\n", dev->dev_type); + DLOG("# Reference Manual: RM%s\n", dev->ref_manual_id); + DLOG("#\n"); + DLOG("chip_id 0x%x\n", dev->chip_id); + DLOG("flash_type %d\n", dev->flash_type); + DLOG("flash_size_reg 0x%x\n", dev->flash_size_reg); + DLOG("flash_pagesize 0x%x\n", dev->flash_pagesize); + DLOG("sram_size 0x%x\n", dev->sram_size); + DLOG("bootrom_base 0x%x\n", dev->bootrom_base); + DLOG("bootrom_size 0x%x\n", dev->bootrom_size); + DLOG("option_base 0x%x\n", dev->option_base); + DLOG("option_size 0x%x\n", dev->option_size); + DLOG("flags %d\n\n", dev->flags); } struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { - struct stlink_chipid_params *params = NULL; - for (params = devicelist; params != NULL; params = params->next) - if (params->chip_id == chip_id) { - DLOG("detected chip_id parameters\n\n"); - dump_a_chip(params); - break; - } + struct stlink_chipid_params *params = NULL; + for (params = devicelist; params != NULL; params = params->next) + if (params->chip_id == chip_id) { + DLOG("detected chip_id parameters\n\n"); + dump_a_chip(params); + break; + } - return(params); + return (params); } void process_chipfile(char *fname) { - FILE *fp; - char *p, buf[256]; - char word[64], value[64]; - struct stlink_chipid_params *ts; - int nc; - - // fprintf (stderr, "processing chip-id file %s.\n", fname); - fp = fopen(fname, "r"); - - if (!fp) { - perror(fname); - return; - } - - ts = calloc(sizeof(struct stlink_chipid_params), 1); - - while (fgets(buf, sizeof(buf), fp) != NULL) { - - if (strncmp(buf, "#", strlen("#")) == 0) - continue; // ignore comments - - if ((strncmp(buf, "\n", strlen("\n")) == 0) || - (strncmp(buf, " ", strlen(" ")) == 0)) - continue; // ignore empty lines - - sscanf(buf, "%s %s", word, value); - - if (strcmp (word, "dev_type") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - ts->dev_type = strdup(buf + nc); - } else if (strcmp(word, "ref_manual_id") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - ts->ref_manual_id = strdup(buf + nc); - } else if (strcmp(word, "chip_id") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->chip_id) < 1) { - fprintf(stderr, "Failed to parse chip-id\n"); - } - } else if (strcmp(word, "flash_type") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (strcmp(value, "F0_F1_F3") == 0) { - ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; - } else if (strcmp(value, "F1_XL") == 0) { - ts->flash_type = STM32_FLASH_TYPE_F1_XL; - } else if (strcmp(value, "F2_F4") == 0) { - ts->flash_type = STM32_FLASH_TYPE_F2_F4; - } else if (strcmp(value, "F7") == 0) { - ts->flash_type = STM32_FLASH_TYPE_F7; - } else if (strcmp(value, "G0") == 0) { - ts->flash_type = STM32_FLASH_TYPE_G0; - } else if (strcmp(value, "G4") == 0) { - ts->flash_type = STM32_FLASH_TYPE_G4; - } else if (strcmp(value, "H7") == 0) { - ts->flash_type = STM32_FLASH_TYPE_H7; - } else if (strcmp(value, "L0_L1") == 0) { - ts->flash_type = STM32_FLASH_TYPE_L0_L1; - } else if (strcmp(value, "L4_L4P") == 0) { - ts->flash_type = STM32_FLASH_TYPE_L4; - } else if (strcmp(value, "L5_U5") == 0) { - ts->flash_type = STM32_FLASH_TYPE_L5_U5; - } else if (strcmp(value, "WB_WL") == 0) { - ts->flash_type = STM32_FLASH_TYPE_WB_WL; - } else { - ts->flash_type = STM32_FLASH_TYPE_UNKNOWN; - } - } else if (strcmp(word, "flash_size_reg") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->flash_size_reg) < 1) { - fprintf(stderr, "Failed to parse flash size reg\n"); - } - } else if (strcmp(word, "flash_pagesize") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->flash_pagesize) < 1) { - fprintf(stderr, "Failed to parse flash page size\n"); - } - } else if (strcmp(word, "sram_size") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->sram_size) < 1) { - fprintf(stderr, "Failed to parse SRAM size\n"); - } - } else if (strcmp(word, "bootrom_base") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->bootrom_base) < 1) { - fprintf(stderr, "Failed to parse BootROM base\n"); - } - } else if (strcmp(word, "bootrom_size") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->bootrom_size) < 1) { - fprintf(stderr, "Failed to parse BootROM size\n"); - } - } else if (strcmp(word, "option_base") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->option_base) < 1) { - fprintf(stderr, "Failed to parse option base\n"); - } - } else if (strcmp(word, "option_size") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - if (sscanf(value, "%i", &ts->option_size) < 1) { - fprintf(stderr, "Failed to parse option size\n"); - } - } else if (strcmp(word, "flags") == 0) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - p = strtok (buf, " \t\n"); - - while ((p = strtok (NULL, " \t\n"))) { - if (strcmp(p, "none") == 0) { - // NOP - } else if (strcmp(p, "dualbank") == 0) { - ts->flags |= CHIP_F_HAS_DUAL_BANK; - } else if (strcmp(p, "swo") == 0) { - ts->flags |= CHIP_F_HAS_SWO_TRACING; - } else { - fprintf(stderr, "Unknown flags word in %s: '%s'\n", - fname, p); - } - } - - sscanf(value, "%x", &ts->flags); + FILE *fp; + char *p, buf[256]; + char word[64], value[64]; + struct stlink_chipid_params *ts; + int nc; + + // fprintf (stderr, "processing chip-id file %s.\n", fname); + fp = fopen(fname, "r"); + + if (!fp) { + perror(fname); + return; + } + + ts = calloc(sizeof(struct stlink_chipid_params), 1); + + while (fgets(buf, sizeof(buf), fp) != NULL) { + + if (strncmp(buf, "#", strlen("#")) == 0) + continue; // ignore comments + + if ((strncmp(buf, "\n", strlen("\n")) == 0) || + (strncmp(buf, " ", strlen(" ")) == 0)) + continue; // ignore empty lines + + sscanf(buf, "%s %s", word, value); + + if (strcmp(word, "dev_type") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + ts->dev_type = strdup(buf + nc); + } else if (strcmp(word, "ref_manual_id") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + ts->ref_manual_id = strdup(buf + nc); + } else if (strcmp(word, "chip_id") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->chip_id) < 1) { + fprintf(stderr, "Failed to parse chip-id\n"); + } + } else if (strcmp(word, "flash_type") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (strcmp(value, "F0_F1_F3") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; + } else if (strcmp(value, "F1_XL") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F1_XL; + } else if (strcmp(value, "F2_F4") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F2_F4; + } else if (strcmp(value, "F7") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F7; + } else if (strcmp(value, "G0") == 0) { + ts->flash_type = STM32_FLASH_TYPE_G0; + } else if (strcmp(value, "G4") == 0) { + ts->flash_type = STM32_FLASH_TYPE_G4; + } else if (strcmp(value, "H7") == 0) { + ts->flash_type = STM32_FLASH_TYPE_H7; + } else if (strcmp(value, "L0_L1") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L0_L1; + } else if (strcmp(value, "L4") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L4; + } else if (strcmp(value, "L5_U5") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L5_U5; + } else if (strcmp(value, "WB_WL") == 0) { + ts->flash_type = STM32_FLASH_TYPE_WB_WL; + } else { + ts->flash_type = STM32_FLASH_TYPE_UNKNOWN; + } + } else if (strcmp(word, "flash_size_reg") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->flash_size_reg) < 1) { + fprintf(stderr, "Failed to parse flash size reg\n"); + } + } else if (strcmp(word, "flash_pagesize") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->flash_pagesize) < 1) { + fprintf(stderr, "Failed to parse flash page size\n"); + } + } else if (strcmp(word, "sram_size") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->sram_size) < 1) { + fprintf(stderr, "Failed to parse SRAM size\n"); + } + } else if (strcmp(word, "bootrom_base") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->bootrom_base) < 1) { + fprintf(stderr, "Failed to parse BootROM base\n"); + } + } else if (strcmp(word, "bootrom_size") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->bootrom_size) < 1) { + fprintf(stderr, "Failed to parse BootROM size\n"); + } + } else if (strcmp(word, "option_base") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->option_base) < 1) { + fprintf(stderr, "Failed to parse option base\n"); + } + } else if (strcmp(word, "option_size") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->option_size) < 1) { + fprintf(stderr, "Failed to parse option size\n"); + } + } else if (strcmp(word, "flags") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + p = strtok(buf, " \t\n"); + + while ((p = strtok(NULL, " \t\n"))) { + if (strcmp(p, "none") == 0) { + // NOP + } else if (strcmp(p, "dualbank") == 0) { + ts->flags |= CHIP_F_HAS_DUAL_BANK; + } else if (strcmp(p, "swo") == 0) { + ts->flags |= CHIP_F_HAS_SWO_TRACING; } else { - fprintf(stderr, "Unknown keyword in %s: %s\n", fname, word); + fprintf(stderr, "Unknown flags word in %s: '%s'\n", fname, p); } + } + + sscanf(value, "%x", &ts->flags); + } else { + fprintf(stderr, "Unknown keyword in %s: %s\n", fname, word); } - fclose(fp); - ts->next = devicelist; - devicelist = ts; + } + fclose(fp); + ts->next = devicelist; + devicelist = ts; } #if defined(STLINK_HAVE_DIRENT_H) #include void init_chipids(char *dir_to_scan) { - DIR *d; - size_t nl; // namelen - struct dirent *dir; - - if (!dir_to_scan) { - dir_to_scan = "./"; + DIR *d; + size_t nl; // namelen + struct dirent *dir; + + if (!dir_to_scan) { + dir_to_scan = "./"; + } + + devicelist = NULL; + d = opendir(dir_to_scan); + + if (d) { + while ((dir = readdir(d)) != NULL) { + nl = strlen(dir->d_name); + + if (strcmp(dir->d_name + nl - 5, ".chip") == 0) { + char buf[1024]; + sprintf(buf, "%s/%s", dir_to_scan, dir->d_name); + process_chipfile(buf); + } } - devicelist = NULL; - d = opendir(dir_to_scan); - - if (d) { - while ((dir = readdir(d)) != NULL) { - nl = strlen(dir->d_name); - - if (strcmp(dir->d_name + nl - 5, ".chip") == 0) { - char buf[1024]; - sprintf(buf, "%s/%s", dir_to_scan, dir->d_name); - process_chipfile(buf); - } - } - - closedir(d); - } else { - perror (dir_to_scan); - return; - } + closedir(d); + } else { + perror(dir_to_scan); + return; + } } -#endif //STLINK_HAVE_DIRENT_H +#endif // STLINK_HAVE_DIRENT_H #if defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) #include #include void init_chipids(char *dir_to_scan) { - HANDLE hFind = INVALID_HANDLE_VALUE; - WIN32_FIND_DATAA ffd; - char filepath[MAX_PATH] = {0}; + HANDLE hFind = INVALID_HANDLE_VALUE; + WIN32_FIND_DATAA ffd; + char filepath[MAX_PATH] = {0}; + StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); + + if (FAILED( + StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), "\\*.chip"))) { + ELOG("Path to chips's dir too long.\n"); + return; + } + + hFind = FindFirstFileA(filepath, &ffd); + + if (INVALID_HANDLE_VALUE == hFind) { + ELOG("Can't find any chip description file in %s.\n", filepath); + return; + } + + do { + memset(filepath, 0, STLINK_ARRAY_SIZE(filepath)); StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), "\\"); + StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), ffd.cFileName); + process_chipfile(filepath); + } while (FindNextFileA(hFind, &ffd) != 0); - if (FAILED(StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), "\\*.chip"))) { - ELOG("Path to chips's dir too long.\n"); - return; - } - - hFind = FindFirstFileA(filepath, &ffd); - - if (INVALID_HANDLE_VALUE == hFind) { - ELOG("Can't find any chip description file in %s.\n", filepath); - return; - } - - do { - memset(filepath, 0, STLINK_ARRAY_SIZE(filepath)); - StringCchCopyA(filepath, STLINK_ARRAY_SIZE(filepath), dir_to_scan); - StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), "\\"); - StringCchCatA(filepath, STLINK_ARRAY_SIZE(filepath), ffd.cFileName); - process_chipfile(filepath); - } while (FindNextFileA(hFind, &ffd) != 0); - - FindClose(hFind); + FindClose(hFind); } -#endif //defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) +#endif // defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) From 2ff79959f4a8f17c64ca30552e86f35bf89f0fa0 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 18 Mar 2023 21:19:15 +0100 Subject: [PATCH 1353/1435] Minor fixes & additions - Corrected flash_pagesize for STM32U5 - Updated STM32 core IDs - Added chip-id file for STM32H5 devices --- config/chips/H5xx.chip | 14 ++++++++++ config/chips/U5x5.chip | 2 +- inc/stm32.h | 61 +++++++++++++++++++++-------------------- src/stlink-lib/common.c | 2 +- 4 files changed, 48 insertions(+), 31 deletions(-) create mode 100644 config/chips/H5xx.chip diff --git a/config/chips/H5xx.chip b/config/chips/H5xx.chip new file mode 100644 index 000000000..a1c438999 --- /dev/null +++ b/config/chips/H5xx.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32H5xx device +# +dev_type STM32H5xx +ref_manual_id 0481 +chip_id 0x484 // STM32_CHIPID_H5xx +flash_type L5_U5 // ? +flash_size_reg 0x08fff80c +flash_pagesize 0x2000 // 8 KB +sram_size 0xa0000 // 640 KB +bootrom_base 0x0bf80000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags dualbank diff --git a/config/chips/U5x5.chip b/config/chips/U5x5.chip index be19d04af..5f71436ef 100644 --- a/config/chips/U5x5.chip +++ b/config/chips/U5x5.chip @@ -5,7 +5,7 @@ ref_manual_id 0456 chip_id 0x482 // STM32_CHIPID_U5x5 flash_type L5_U5 flash_size_reg 0x0bfa07a0 -flash_pagesize 0x200000 // 2048 KB +flash_pagesize 0x2000 // 8 KB sram_size 0xc4800 // 786 KB bootrom_base 0x0bf90000 bootrom_size 0x10000 // 64 KB diff --git a/inc/stm32.h b/inc/stm32.h index 8557c9ce7..746f4c0f3 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -9,35 +9,37 @@ /* STM32 Cortex-M core ids (CPUTAPID) */ enum stm32_core_id { - STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP - // (RM0444 Section 40.5.3) G0 SW-DP - STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0385 Section 27.5.3) L0 SW-DP - STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP - STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG - STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP - // (RM0038 Section 30.8.3) L1 SW-DP - STM32_CORE_ID_M3_r2p0_JTAG = 0x0ba00477, // (RM0033 Section 32.6.3) F2 JTAG - // (RM0038 Section 30.6.2) L1 JTAG - STM32_CORE_ID_M4_r0p1_SWD = 0x1ba01477, // (RM0316 Section 33.8.3) F3 SW-DP - // (RM0351 Section 48.8.3) L4 SW-DP - // (RM0432 Section 57.8.3) L4+ SW-DP - STM32_CORE_ID_M4_r0p1_JTAG = 0x4ba00477, // (RM0316 Section 33.6.3) F3 JTAG - // (RM0351 Section 48.6.3) L4 JTAG - // (RM0432 Section 57.6.3) L4+ JTAG - STM32_CORE_ID_M4F_r0p1_SWD = 0x2ba01477, // (RM0090 Section 38.8.3) F4 SW-DP - // (RM0090 Section 47.8.3) G4 SW-DP - STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG - // (RM0090 Section 47.6.3) G4 JTAG - STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP - STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG - STM32_CORE_ID_M7F_H7_SWD = 0x6ba02477, // (RM0433 Section 60.4.1) H7 SW-DP - STM32_CORE_ID_M7F_H7_JTAG = 0x6ba00477, // (RM0433 Section 60.4.1) H7 JTAG - STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP - // (RM0456 Section 65.3.3) U5 SW-DP - STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP - // (RM0456 Section 65.3.3) U5 JTAG-DP - STM32_CORE_ID_M33_JTAG = 0x0ba04477, // (RM0438 Section 52.2.8) L5 JTAG - // (RM0456 Section 56.3.1) U5 JTAG + STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP + // (RM0444 Section 40.5.3) G0 SW-DP + STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0385 Section 27.5.3) L0 SW-DP + STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP + STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG + STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP + // (RM0038 Section 30.8.3) L1 SW-DP + STM32_CORE_ID_M3_r2p0_JTAG = 0x0ba00477, // (RM0033 Section 32.6.3) F2 JTAG + // (RM0038 Section 30.6.2) L1 JTAG + STM32_CORE_ID_M4_r0p1_SWD = 0x1ba01477, // (RM0316 Section 33.8.3) F3 SW-DP + // (RM0351 Section 48.8.3) L4 SW-DP + // (RM0432 Section 57.8.3) L4+ SW-DP + STM32_CORE_ID_M4_r0p1_JTAG = 0x4ba00477, // (RM0316 Section 33.6.3) F3 JTAG + // (RM0351 Section 48.6.3) L4 JTAG + // (RM0432 Section 57.6.3) L4+ JTAG + STM32_CORE_ID_M4F_r0p1_SWD = 0x2ba01477, // (RM0090 Section 38.8.3) F4 SW-DP + // (RM0090 Section 47.8.3) G4 SW-DP + STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG + // (RM0090 Section 47.6.3) G4 JTAG + STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP + STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG + STM32_CORE_ID_M7F_M33_SWD = 0x6ba02477, // (RM0481 Section 58.3.3) H5 SW-DP + // (RM0433 Section 60.4.1) H7 SW-DP + STM32_CORE_ID_M7F_M33_JTAG = 0x6ba00477, // (RM0481 Section 58.3.1) H5 JTAG + // (RM0433 Section 60.4.1) H7 SW-DP + STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP + // (RM0456 Section 65.3.3) U5 SW-DP + STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP + // (RM0456 Section 65.3.3) U5 JTAG-DP + STM32_CORE_ID_M33_JTAG = 0x0ba04477, // (RM0438 Section 52.2.8) L5 JTAG + // (RM0456 Section 56.3.1) U5 JTAG }; /* STM32 flash types */ @@ -122,6 +124,7 @@ enum stm32_chipids { STM32_CHIPID_H7Ax = 0x480, /* RM0455, p.2863 */ STM32_CHIPID_U5x5 = 0x482, /* RM0456, p.2991 */ STM32_CHIPID_H72x = 0x483, /* RM0468, p.3199 */ + STM32_CHIPID_H5xx = 0x484, /* RM0481, p.3085 */ STM32_CHIPID_WB55 = 0x495, STM32_CHIPID_WLE = 0x497, }; diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index cb037fb2f..65d292235 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -140,7 +140,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * DBGMCU_IDCODE / DBG_IDCODE name */ - if ((sl->core_id == STM32_CORE_ID_M7F_H7_SWD || sl->core_id == STM32_CORE_ID_M7F_H7_JTAG) && + if ((sl->core_id == STM32_CORE_ID_M7F_M33_SWD || sl->core_id == STM32_CORE_ID_M7F_M33_JTAG) && cpu_id.part == STLINK_REG_CMx_CPUID_PARTNO_CM7) { // STM32H7 chipid in 0x5c001000 (RM0433 pg3189) ret = stlink_read_debug32(sl, 0x5c001000, chip_id); From 186e38a0faac5f546f8b378e625ebe177baf281d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 18 Mar 2023 21:53:27 +0100 Subject: [PATCH 1354/1435] Minor fixes & additions - [doc] Update on OS version support - Minor fixes for G0-series from #1293 - [doc] Added core-IDs for WB/WL-series - [doc] Correction for G0/L0-series core-IDs - Set option_size to 128 B for G0-series (#1194) --- config/chips/F401xD_xE.chip | 4 +- config/chips/F446.chip | 2 +- config/chips/G03x_G04x.chip | 2 +- config/chips/G05x_G06x.chip | 6 +-- config/chips/G07x_G08x.chip | 4 +- config/chips/G0Bx_G0Cx.chip | 6 +-- doc/version_support.md | 60 ++++++++++++++--------------- inc/stm32.h | 72 ++++++++++++++++++----------------- src/stlink-lib/common.c | 3 +- src/stlink-lib/option_bytes.c | 9 ++--- 10 files changed, 83 insertions(+), 85 deletions(-) diff --git a/config/chips/F401xD_xE.chip b/config/chips/F401xD_xE.chip index f817175f4..e90f4a78e 100644 --- a/config/chips/F401xD_xE.chip +++ b/config/chips/F401xD_xE.chip @@ -9,6 +9,6 @@ flash_pagesize 0x4000 // 16 KB sram_size 0x18000 // 96 KB bootrom_base 0x1fff0000 bootrom_size 0x7800 // 30 KB -option_base 0x40023C14 -option_size 0x4 +option_base 0x40023C14 // STM32_F4_OPTION_BYTES_BASE +option_size 0x4 // 4 B flags swo diff --git a/config/chips/F446.chip b/config/chips/F446.chip index e4d0bdec2..25f22d9b6 100644 --- a/config/chips/F446.chip +++ b/config/chips/F446.chip @@ -10,5 +10,5 @@ sram_size 0x20000 // 128 KB bootrom_base 0x1fff0000 bootrom_size 0x7800 // 30 KB option_base 0x40023c14 // STM32_F4_OPTION_BYTES_BASE -option_size 0x4 // 4 B +option_size 0x10 // 16 B flags swo diff --git a/config/chips/G03x_G04x.chip b/config/chips/G03x_G04x.chip index a414b52ab..2010940c7 100644 --- a/config/chips/G03x_G04x.chip +++ b/config/chips/G03x_G04x.chip @@ -10,5 +10,5 @@ sram_size 0x2000 // 8 KB bootrom_base 0x1fff0000 bootrom_size 0x2000 // 8 KB option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE -option_size 0x4 // 4 B +option_size 0x80 // 128 B flags none diff --git a/config/chips/G05x_G06x.chip b/config/chips/G05x_G06x.chip index ae074e584..ba556b53a 100644 --- a/config/chips/G05x_G06x.chip +++ b/config/chips/G05x_G06x.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32G05x / STM32G06x device # dev_type STM32G05x_G06x -ref_manual_id 0444 +ref_manual_id 0444 // also RM454 chip_id 0x456 // STM32_CHIPID_G0_CAT4 flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB -sram_size 0x9000 // 36 KB +sram_size 0x4800 // 18 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE -option_size 0x4 // 4 B +option_size 0x80 // 128 B flags none diff --git a/config/chips/G07x_G08x.chip b/config/chips/G07x_G08x.chip index 82b3992c2..60a6bec7a 100644 --- a/config/chips/G07x_G08x.chip +++ b/config/chips/G07x_G08x.chip @@ -1,7 +1,7 @@ # Chip-ID file for STM32G07x / STM32G08x device # dev_type STM32G07x_G08x -ref_manual_id 0444 +ref_manual_id 0444 // also RM454 chip_id 0x460 // STM32_CHIPID_G0_CAT2 flash_type G0 flash_size_reg 0x1fff75e0 @@ -10,5 +10,5 @@ sram_size 0x9000 // 36 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE -option_size 0x4 // 4 B +option_size 0x80 // 128 B flags none diff --git a/config/chips/G0Bx_G0Cx.chip b/config/chips/G0Bx_G0Cx.chip index f21fd65a0..a9bae1f08 100644 --- a/config/chips/G0Bx_G0Cx.chip +++ b/config/chips/G0Bx_G0Cx.chip @@ -1,14 +1,14 @@ # Chip-ID file for STM32G0Bx / STM32G0Cx device # dev_type STM32G0Bx_G0Cx -ref_manual_id 0444 +ref_manual_id 0444 // also RM454 chip_id 0x467 // STM32_CHIPID_G0_CAT3 flash_type G0 flash_size_reg 0x1fff75e0 flash_pagesize 0x800 // 2 KB -sram_size 0x9000 // 36 KB +sram_size 0x24000 // 144 KB bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_G0_OPTION_BYTES_BASE -option_size 0x4 // 4 B +option_size 0x80 // 128 B flags dualbank diff --git a/doc/version_support.md b/doc/version_support.md index 593c86549..e7d8f444b 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -59,43 +59,41 @@ Other Linux-/Unix-based Operating Systems: | Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | | Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | | Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | -| AlmaLinux 8 | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | -| Rocky Linux 8 [x64] | 1.0.23 | 3.20.2 | 3.**22.30** | | | Adélie 1.0 | 1.0.23 | 3.**16.4** | 3.24.23 | | ## Unsupported Operating Systems (as of Release v1.7.1) Systems with highlighted versions remain compatible with this toolset. -| Operating System | libusb | cmake | End of
      OS-Support | -| ------------------------- | ------------------------------ | ---------- | ---------------------- | -| Fedora 35 [x64] | 1.0.**24** | 3.**21.3** | Dec 2022 | -| CentOS 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | -| Fedora 34 [x64] | 1.0.**24** (`libusbx`) | 3.**19.7** | Jun 2022 | -| Mageia 8 | 1.0.**24** | 3.**19.2** | Aug 2022 | -| Alpine 3.13 | 1.0.**24** | 3.**18.4** | Nov 2022 | -| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | -| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | -| Alpine 3.12 | 1.0.**23** | 3.**17.2** | May 2022 | -| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.**17.0** | Dec 2022 | -| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | -| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | -| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | -| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | -| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | -| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | -| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | -| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | -| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | -| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | -| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | -| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | -| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.**10.2** | **Apr 2023** | -| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | -| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | Jun 2022 | -| Slackware 14.2 | 1.0.20 | 3.5.2 | | -| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | -| CentOS 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | +| Operating System | libusb | cmake | End of
      OS-Support | +| ---------------------------------------- | ------------------------------ | ---------- | ---------------------- | +| Fedora 35 [x64] | 1.0.**24** | 3.**21.3** | Dec 2022 | +| CentOS / Rocky Linux / AlmaLinux 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | +| Fedora 34 [x64] | 1.0.**24** (`libusbx`) | 3.**19.7** | Jun 2022 | +| Mageia 8 | 1.0.**24** | 3.**19.2** | Aug 2022 | +| Alpine 3.13 | 1.0.**24** | 3.**18.4** | Nov 2022 | +| Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | +| Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | +| Alpine 3.12 | 1.0.**23** | 3.**17.2** | May 2022 | +| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.**17.0** | Dec 2022 | +| Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | +| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | +| Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | +| NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | +| Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | +| FreeBSD 11.x | 1.0.**16-18** (API 0x01000102) | 3.**15.5** | Sep 2021 | +| Alpine 3.10 | 1.0.**22** | 3.**14.5** | May 2021 | +| Fedora 31 [x64] | 1.0.**22**(`libusbx`) | 3.**14.5** | Nov 2020 | +| Mageia 7.1 | 1.0.**22** | 3.**14.3** | Jun 2021 | +| Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | +| Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | +| Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | +| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.**10.2** | **Apr 2023** | +| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | +| Debian 9 (Stretch) | 1.0.21 | 3.7.2 | Jun 2022 | +| Slackware 14.2 | 1.0.20 | 3.5.2 | | +| OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | +| CentOS / Rocky Linux / AlmaLinux 7 [x64] | 1.0.21 (`libusbx`) | 2.8.12.2 | Jun 2024 | _All other operating systems which are not listed are unsupported._ diff --git a/inc/stm32.h b/inc/stm32.h index 746f4c0f3..92770bd44 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -9,37 +9,41 @@ /* STM32 Cortex-M core ids (CPUTAPID) */ enum stm32_core_id { - STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP - // (RM0444 Section 40.5.3) G0 SW-DP - STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0385 Section 27.5.3) L0 SW-DP - STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP - STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG - STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP - // (RM0038 Section 30.8.3) L1 SW-DP - STM32_CORE_ID_M3_r2p0_JTAG = 0x0ba00477, // (RM0033 Section 32.6.3) F2 JTAG - // (RM0038 Section 30.6.2) L1 JTAG - STM32_CORE_ID_M4_r0p1_SWD = 0x1ba01477, // (RM0316 Section 33.8.3) F3 SW-DP - // (RM0351 Section 48.8.3) L4 SW-DP - // (RM0432 Section 57.8.3) L4+ SW-DP - STM32_CORE_ID_M4_r0p1_JTAG = 0x4ba00477, // (RM0316 Section 33.6.3) F3 JTAG - // (RM0351 Section 48.6.3) L4 JTAG - // (RM0432 Section 57.6.3) L4+ JTAG - STM32_CORE_ID_M4F_r0p1_SWD = 0x2ba01477, // (RM0090 Section 38.8.3) F4 SW-DP - // (RM0090 Section 47.8.3) G4 SW-DP - STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG - // (RM0090 Section 47.6.3) G4 JTAG - STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP - STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG - STM32_CORE_ID_M7F_M33_SWD = 0x6ba02477, // (RM0481 Section 58.3.3) H5 SW-DP - // (RM0433 Section 60.4.1) H7 SW-DP - STM32_CORE_ID_M7F_M33_JTAG = 0x6ba00477, // (RM0481 Section 58.3.1) H5 JTAG - // (RM0433 Section 60.4.1) H7 SW-DP - STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP - // (RM0456 Section 65.3.3) U5 SW-DP - STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP - // (RM0456 Section 65.3.3) U5 JTAG-DP - STM32_CORE_ID_M33_JTAG = 0x0ba04477, // (RM0438 Section 52.2.8) L5 JTAG - // (RM0456 Section 56.3.1) U5 JTAG + STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP + STM32_CORE_ID_M0P_SWD = 0x0bc11477, // (RM0444 Section 40.5.3) G0 SW-DP + // (RM0377 Section 27.5.3) L0 SW-DP + STM32_CORE_ID_M3_r1p1_SWD = 0x1ba01477, // (RM0008 Section 31.8.3) F1 SW-DP + STM32_CORE_ID_M3_r1p1_JTAG = 0x3ba00477, // (RM0008 Section 31.6.3) F1 JTAG + STM32_CORE_ID_M3_r2p0_SWD = 0x2ba01477, // (RM0033 Section 32.8.3) F2 SW-DP + // (RM0038 Section 30.8.3) L1 SW-DP + STM32_CORE_ID_M3_r2p0_JTAG = 0x0ba00477, // (RM0033 Section 32.6.3) F2 JTAG + // (RM0038 Section 30.6.2) L1 JTAG + STM32_CORE_ID_M4_r0p1_SWD = 0x1ba01477, // (RM0316 Section 33.8.3) F3 SW-DP + // (RM0351 Section 48.8.3) L4 SW-DP + // (RM0432 Section 57.8.3) L4+ SW-DP + STM32_CORE_ID_M4_r0p1_JTAG = 0x4ba00477, // (RM0316 Section 33.6.3) F3 JTAG + // (RM0351 Section 48.6.3) L4 JTAG + // (RM0432 Section 57.6.3) L4+ JTAG + STM32_CORE_ID_M4F_r0p1_SWD = 0x2ba01477, // (RM0090 Section 38.8.3) F4 SW-DP + // (RM0090 Section 47.8.3) G4 SW-DP + STM32_CORE_ID_M4F_r0p1_JTAG = 0x4ba00477, // (RM0090 Section 38.6.3) F4 JTAG + // (RM0090 Section 47.6.3) G4 JTAG + STM32_CORE_ID_M7F_SWD = 0x5ba02477, // (RM0385 Section 40.8.3) F7 SW-DP + // (RM0473 Section 33.4.4) WB SW-DP + // (RM0453 Section 38.4.1) WL SW-DP + STM32_CORE_ID_M7F_JTAG = 0x5ba00477, // (RM0385 Section 40.6.3) F7 JTAG + STM32_CORE_ID_M7F_M33_SWD = 0x6ba02477, // (RM0481 Section 58.3.3) H5 SW-DP + // (RM0433 Section 60.4.1) H7 SW-DP + STM32_CORE_ID_M7F_M33_JTAG = 0x6ba00477, // (RM0481 Section 58.3.1) H5 JTAG + // (RM0433 Section 60.4.1) H7 JTAG + // (RM0473 Section 33.4.1) WB JTAG + // (RM0453 Section 38.3.8) WL JTAG + STM32_CORE_ID_M33_SWD = 0x0be02477, // (RM0438 Section 52.2.10) L5 SW-DP + // (RM0456 Section 65.3.3) U5 SW-DP + STM32_CORE_ID_M33_JTAGD = 0x0be01477, // (RM0438 Section 52.2.10) L5 JTAG-DP + // (RM0456 Section 65.3.3) U5 JTAG-DP + STM32_CORE_ID_M33_JTAG = 0x0ba04477, // (RM0438 Section 52.2.8) L5 JTAG + // (RM0456 Section 56.3.1) U5 JTAG }; /* STM32 flash types */ @@ -108,13 +112,13 @@ enum stm32_chipids { STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ STM32_CHIPID_L011 = 0x457, STM32_CHIPID_F410 = 0x458, - STM32_CHIPID_G0_CAT2 = 0x460, /* G070/G071/G081 */ + STM32_CHIPID_G0_CAT2 = 0x460, /* G07x/G08x */ STM32_CHIPID_L496x_L4A6x = 0x461, STM32_CHIPID_L45x_L46x = 0x462, STM32_CHIPID_F413 = 0x463, STM32_CHIPID_L41x_L42x = 0x464, - STM32_CHIPID_G0_CAT1 = 0x466, /* G030/G031/G041 */ - STM32_CHIPID_G0_CAT3 = 0x467, /* G0B1/G0C1 */ + STM32_CHIPID_G0_CAT1 = 0x466, /* G03x/G04x */ + STM32_CHIPID_G0_CAT3 = 0x467, /* G0Bx/G0Cx */ STM32_CHIPID_G4_CAT2 = 0x468, /* RM0440, section 46.6.1 "MCU device ID code" */ STM32_CHIPID_G4_CAT3 = 0x469, STM32_CHIPID_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 65d292235..ccce342a4 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -279,8 +279,7 @@ int stlink_load_device_params(stlink_t *sl) { // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 - if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && - sl->flash_size < 64 * 1024) { + if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { sl->sram_size = 0x1000; } diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 2d4898001..32becc5cf 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -242,8 +242,7 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, stm32_addr_t addr, uint8_t int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { int err = -1; for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { - err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), - option_byte); + err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), option_byte); if (err == -1) { return err; } else { @@ -272,8 +271,7 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t // Clear errors clear_flash_error(sl); - ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), - addr); + ILOG("Asked to write option byte %#10x to %#010x.\n", *(uint32_t *)(base), addr); write_uint32((unsigned char *)&option_byte, *(uint32_t *)(base)); ILOG("Write %d option bytes %#010x to %#010x!\n", len, option_byte, addr); @@ -306,8 +304,7 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t ret = check_flash_error(sl); if (!ret) - ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, - addr); + ILOG("Wrote %d option bytes %#010x to %#010x!\n", len, *(uint32_t *)base, addr); /* option bytes are reloaded at reset only, no obl. */ From 21633df34ae0bf4a0f9aae3ad5271965160b40f8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 19 Mar 2023 15:43:37 +0100 Subject: [PATCH 1355/1435] Minor compilation fixes - Corrected install path for gui executable - Changed directory for chip-id files --- CMakeLists.txt | 4 ++-- src/stlink-gui/CMakeLists.txt | 9 +-------- src/stlink-lib/flashloader.c | 3 +-- 3 files changed, 4 insertions(+), 12 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 7d8bce8cf..4ce0ee126 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -78,8 +78,8 @@ include(GNUInstallDirs) # Define GNU standard installation directories cmake_host_system_information(RESULT OS_NAME QUERY OS_NAME) message(STATUS "Checking for OS_NAME: ${OS_NAME}") -message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/share)") -set(CMAKE_INSTALL_SHAREDIR /usr/share/) +message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/local/share)") +set(CMAKE_INSTALL_SHAREDIR /usr/local/share/) ## Set C build flags diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index d2edf0d9f..fb4478bdc 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -24,19 +24,12 @@ if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) set(GUI_SOURCES gui.c gui.h) - ## stlink-gui-local - add_executable(stlink-gui-local ${GUI_SOURCES}) - file(COPY stlink-gui.ui DESTINATION ${CMAKE_BINARY_DIR}/bin) - set_target_properties(stlink-gui-local PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_BINARY_DIR}/bin") - target_link_libraries(stlink-gui-local ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) - ## stlink-gui add_executable(stlink-gui ${GUI_SOURCES}) install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}) set_target_properties(stlink-gui PROPERTIES COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) - install(TARGETS stlink-gui DESTINATION ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}) + install(TARGETS stlink-gui DESTINATION ${CMAKE_BINDIR}) endif () endif () diff --git a/src/stlink-lib/flashloader.c b/src/stlink-lib/flashloader.c index 7164983cd..4adf93a86 100644 --- a/src/stlink-lib/flashloader.c +++ b/src/stlink-lib/flashloader.c @@ -51,8 +51,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, } if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading + // show progress; writing procedure is slow and previous errors are misleading fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); fflush(stdout); } From e93fa5798bfc247faa9ae55e217286f0491d2602 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 19 Mar 2023 18:46:22 +0100 Subject: [PATCH 1356/1435] Updated CHANGELOG.md --- CHANGELOG.md | 17 +++++++++++------ src/st-flash/flash.c | 7 +++++++ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index ddd795c37..551a4ba09 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -31,7 +31,7 @@ Features: Updates & changes: - [refactoring] Moved chip-specific parameters into separate files ([#237](https://github.com/stlink-org/stlink/pull/237), [#1129](https://github.com/stlink-org/stlink/pull/1129)) -- [refactoring] General maintenance for code structure ([#903](https://github.com/stlink-org/stlink/pull/903), [#1090](https://github.com/stlink-org/stlink/pull/1090), [#1199](https://github.com/stlink-org/stlink/pull/1199), [#1212](https://github.com/stlink-org/stlink/pull/1212), [#1216](https://github.com/stlink-org/stlink/pull/1216)) +- [refactoring] General maintenance for code structure ([#903](https://github.com/stlink-org/stlink/pull/903), [#1090](https://github.com/stlink-org/stlink/pull/1090), [#1199](https://github.com/stlink-org/stlink/pull/1199), [#1212](https://github.com/stlink-org/stlink/pull/1212), [#1216](https://github.com/stlink-org/stlink/pull/1216), [#1228](https://github.com/stlink-org/stlink/pull/1228)) - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation (commit [#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) @@ -44,9 +44,12 @@ Updates & changes: - [refactoring] Sourcefile 'common.c' ([#1218](https://github.com/stlink-org/stlink/pull/1218), [#1220](https://github.com/stlink-org/stlink/pull/1220)) - Set C standard through cmake variables ([#1221](https://github.com/stlink-org/stlink/pull/1221)) - [doc] Added make install to the macOS compiling instructions ([#1259](https://github.com/stlink-org/stlink/pull/1259)) -- [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), (commit [#43498de](https://github.com/stlink-org/stlink/commit/43498dedf651260ef34197e512d35e3ad7142401)) +- [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), commit [#43498de](https://github.com/stlink-org/stlink/commit/43498dedf651260ef34197e512d35e3ad7142401)) +- End of support for macOS ([#1269](https://github.com/stlink-org/stlink/pull/1269), [#1296](https://github.com/stlink-org/stlink/pull/1296), commit [#61ff09e](https://github.com/stlink-org/stlink/commit/61ff09e5274d46a46ae58bc4ffe44fe90a887ea6)) +- [doc] Added device ID for GD32F303VET6 ([#1288](https://github.com/stlink-org/stlink/pull/1288)) Fixes: + - cmake: Install shared libraries in proper directories ([#1098](https://github.com/stlink-org/stlink/pull/1098), [#1138](https://github.com/stlink-org/stlink/pull/1138), [#1154](https://github.com/stlink-org/stlink/pull/1154)) - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) - Fixed clearance of the H7 dual bank flag ([#1146](https://github.com/stlink-org/stlink/pull/1146), [#1147](https://github.com/stlink-org/stlink/pull/1147)) @@ -64,13 +67,15 @@ Fixes: - Define 'SSIZE_MAX' if not defined ([#1183](https://github.com/stlink-org/stlink/pull/1183)) - Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) - Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) -- Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214) +- Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214)) +- General fixes and improvements ([#1240](https://github.com/stlink-org/stlink/pull/1240), [#1242](https://github.com/stlink-org/stlink/pull/1242), [#1290](https://github.com/stlink-org/stlink/pull/1290), [#1291](https://github.com/stlink-org/stlink/pull/1291), [#1295](https://github.com/stlink-org/stlink/pull/1295)) +- Fixes for project compilation ([#1241](https://github.com/stlink-org/stlink/pull/1241), [#1271](https://github.com/stlink-org/stlink/pull/1271), [#1283](https://github.com/stlink-org/stlink/pull/1283), [#1286](https://github.com/stlink-org/stlink/pull/1286),commit [#f93adb9](https://github.com/stlink-org/stlink/commit/f93adb92f2e4ecf05a9361cb723c98693586929d)) - st-trace: Fixed clock issues ([#1248](https://github.com/stlink-org/stlink/pull/1248), [#1251](https://github.com/stlink-org/stlink/pull/1251), [#1252](https://github.com/stlink-org/stlink/pull/1252)) - Fixed compilation with gcc-12 ([#1257](https://github.com/stlink-org/stlink/pull/1257), [#1267](https://github.com/stlink-org/stlink/pull/1267)) - Fixed flash regs addr for STM32L152RET6 in common_flash.c ([#1265](https://github.com/stlink-org/stlink/pull/1265)) - Fixed flash, dbgmcu and rcc registers for STM32L1 ([#1266](https://github.com/stlink-org/stlink/pull/1266)) -- Fixed compilation with gcc-12 ([#1257](https://github.com/stlink-org/stlink/pull/1257), [#1267](https://github.com/stlink-org/stlink/pull/1267)) -- Fixes for project compilation ([#1270](https://github.com/stlink-org/stlink/pull/1270), [#1271](https://github.com/stlink-org/stlink/pull/1271), [#1283](https://github.com/stlink-org/stlink/pull/1283), [#1286](https://github.com/stlink-org/stlink/pull/1286),commit [#f93adb9](https://github.com/stlink-org/stlink/commit/f93adb92f2e4ecf05a9361cb723c98693586929d)) +- Fixed incorrect SRAM size for L496x and L4A6x ([#1268](https://github.com/stlink-org/stlink/pull/1268), commit [#ff81148](https://github.com/stlink-org/stlink/commit/ff8114895a9fc32cae6a9374e58eac6256d68183)) +- Fixed st-trace reconnect on Windows ([#1272](https://github.com/stlink-org/stlink/pull/1272), [#1292](https://github.com/stlink-org/stlink/pull/1292)) - [compilation] Corrected path to stlink/chips subdirectory ([#1276](https://github.com/stlink-org/stlink/pull/1276), [#1279](https://github.com/stlink-org/stlink/pull/1279)) - [compilation] Fixed GUI compilation failure on OpenBSD i386 ([#1284](https://github.com/stlink-org/stlink/pull/1284)) @@ -84,7 +89,7 @@ Features: - Extended set of cmd line arguments for st-info and st-util ([#332](https://github.com/stlink-org/stlink/pull/332), [#990](https://github.com/stlink-org/stlink/pull/990), [#1091](https://github.com/stlink-org/stlink/pull/1091), [#1114](https://github.com/stlink-org/stlink/pull/1114)) - Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#801](https://github.com/stlink-org/stlink/pull/801), [#868](https://github.com/stlink-org/stlink/pull/868), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) -- Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052)) +- Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052), [#1184](https://github.com/stlink-org/stlink/pull/1184)) - Official support for STLINK-V3 programmers (commit [#5e0a502](https://github.com/stlink-org/stlink/commit/5e0a502df812495bfa96fa9116a19f1306152b17), [#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) - Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) - Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 39b31f219..3b25dc214 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -169,7 +169,10 @@ int main(int ac, char** av) { printf("Unknown memory region\n"); goto on_error; } + } else if (o.cmd == FLASH_CMD_ERASE) { + + // erase if (o.size > 0 && o.addr > 0) { err = stlink_erase_flash_section(sl, o.addr, o.size, false); } else { @@ -180,11 +183,15 @@ int main(int ac, char** av) { goto on_error; } printf("Mass erase completed successfully.\n"); + } else if (o.cmd == CMD_RESET) { + + // reset if (stlink_reset(sl, RESET_AUTO)) { printf("Failed to reset device\n"); goto on_error; } + } else { // read From 8af1dcb71e870e3c8f20e28bb123e10808696e55 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 4 Apr 2023 23:32:51 +0200 Subject: [PATCH 1357/1435] Minor changes & fixes - Simplified listing of supported devices - Corrected #define STM32L5_PWR_CR1_VOS - Check the return code of stlink_read_debug32 - Fix for flash register reading on L5x2 devices --- doc/devices_boards.md | 207 ---------------------------------- doc/supported devices.md | 59 ++++++++++ inc/stm32.h | 2 +- src/stlink-lib/common.c | 9 ++ src/stlink-lib/common_flash.c | 3 +- 5 files changed, 70 insertions(+), 210 deletions(-) delete mode 100644 doc/devices_boards.md create mode 100644 doc/supported devices.md diff --git a/doc/devices_boards.md b/doc/devices_boards.md deleted file mode 100644 index 13aa0361a..000000000 --- a/doc/devices_boards.md +++ /dev/null @@ -1,207 +0,0 @@ -# MCUs supported by the STlink toolset - -The following devices are supported by the stlink toolset. - -## STM32F0 / ARM Cortex M0 - -| Chip-ID | Product-Code | -| ------- | ------------------- | -| 0x440 | STM32F0**30**x**8** | -| 0x442 | STM32F0**30**x**C** | -| 0x444 | STM32F0**3**xx**4** | -| 0x444 | STM32F0**3**xx**6** | -| 0x445 | STM32F0**4**xxx | -| 0x440 | STM32F0**5**xxx | -| 0x445 | STM32F0**70**x**6** | -| 0x448 | STM32F0**70**x**B** | -| 0x448 | STM32F0**71**xx | -| 0x448 | STM32F0**72**xx | -| 0x442 | STM32F0**9**xxx | - - -## STM32F1 / ARM Cortex M3 - -| Product-Code | Product Line | -| ----------------- | ----------------------- | -| STM32F10**0**yyxx | Value line (V) | -| STM32F10**1**yyxx | Access line (A) | -| STM32F10**2**yyxx | USB Access line (USB-A) | -| STM32F10**3**yyxx | Performance line (P) | -| STM32F10**5**yyxx | Connectivity line (C) | -| STM32F10**7**yyxx | Connectivity line (C) | - -| Chip-ID | Product Line | Code (yy) | V | A | USB-A | P | C | -| ------- | -------------------- | --------- | ---- | ---- | ----- | ---- | -------------- | -| 0x412 | Low-Density | x4 x6 | F100 | F101 | F102 | F103 | | -| 0x410 | Medium Density | x8 xB | | F101 | F102 | F103 | | -| 0x414 | High density | xC xD xE | | F101 | F103 | | | -| 0x418 | STM32F105xx/107xx | x8 xB xC | | | | | F105
      F107 | -| 0x420 | Medium density value | x8 xB | F100 | | | | | -| 0x428 | High density Value | xC xD xE | F100 | | | | | -| 0x430 | XL-Density | xF xG | | F101 | | F103 | | - -Tested non-official ST boards [incl. STLINK programmers]: - -- HY-STM32 (STM32F103VETx) [v1, v2] -- DecaWave EVB1000 (STM32F105RCTx) [v1, v2] - -## STM32F2 / ARM Cortex M3 - -| Chip-ID | Product-Code | Product Line | -| ------- | ------------ | ------------- | -| 0x411 | STM32F2yyxx | (all devices) | - -## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) [may work, but without support!] - -| Product-Code | Chip-ID | STLink
      Programmer | Boards | -| ------------- | ------- | ---------------------- | ------------------------------------------------------------------------------------------------------------------------------------ | -| CKS32F103C8Tx | 0x410 | v2 | STM32F103C8T6 clone from China Key Systems (CKS) either as
      CKS32-Bluepill or even as "STM32"-Bluepill with _**Fake-Marking !**_ | - -## STM32F3 / ARM Cortex M4F - -| Product-Code | Product Line | -| ----------------- | ------------------------------------------------------------- | -| STM32F3**01**yyxx | Access line (A) | -| STM32F3**02**yyxx | USB & CAN line (USB/CAN) | -| STM32F3**03**yyxx | Performance line (P) | -| STM32F3**34**yy | Digital Power line (DP) | -| STM32F3**73**yy | Precision Measurement line (PM) 64k/16k / 128k/24k / 265k/32k | -| STM32F3**18**yy | General Purpose line (GP) 64k/16k | -| STM32F3**28**yy | General Purpose line (GP) 64k/16k | -| STM32F3**58**yy | General Purpose line (GP) 265k/48k | -| STM32F3**78**yy | Precision Measurement line (PM) 265k/32k | -| STM32F3**98**yy | General Purpose line (GP) 512k/80k | - -| Chip-ID | Product Line | Code (yy) | A | USB/CAN | P | others | -| ------- | ------------ | --------- | ---- | ------- | ---- | -------------- | -| 0x422 | _N/A_ | xB xC | | F302 | F303 | | -| 0x422 | _N/A_ | - | | | | F358 | -| 0x432 | _N/A_ | - | | | | F373
      F378 | -| 0x438 | _N/A_ | x4 x6 x8 | | | F303 | | -| 0x438 | _N/A_ | - | | | | F334
      F328 | -| 0x439 | _N/A_ | x4 x6 x8 | F301 | F302 | | | -| 0x439 | _N/A_ | - | | | | F318 | -| 0x446 | _N/A_ | xD xE | | F302 | F303 | | -| 0x446 | _N/A_ | - | | | | F398 | - -## STM32F3 Clone / ARM Cortex M4F (Core-ID: 0x2ba01477) [may work, but without support!] - -| Product-Code | Chip-ID | STLINK
      Programmer | Boards | -| ------------ | ------- | ---------------------- | ---------------------------------- | -| GD32F303CGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | -| GD32F303VET6 | 0x414 | [v2] | STM32F303 clone from GigaDevice GD | -| GD32F303VGT6 | 0x430 | [v2] | STM32F303 clone from GigaDevice GD | - -## STM32F4 / ARM Cortex M4F - -| Chip-ID | Product-Code | -| ------- | ------------------- | -| 0x413 | STM32F4**0**xxx | -| 0x413 | STM32F4**1**xxx | -| 0x419 | STM32F4**2**xxx | -| 0x419 | STM32F4**3**xxx | -| 0x423 | STM32F4**01**x**B** | -| 0x423 | STM32F4**01**x**C** | -| 0x433 | STM32F4**01**x**D** | -| 0x433 | STM32F4**01**x**E** | -| 0x458 | STM32F4**10**xx | -| 0x431 | STM32F4**11**xx | -| 0x441 | STM32F4**12**xx | -| 0x421 | STM32F4**46**xx | -| 0x434 | STM32F4**69**xx | -| 0x434 | STM32F4**79**xx | -| 0x463 | STM32F4**13**xx | -| 0x463 | STM32F4**23**xx | - -## STM32F7 / ARM Cortex M7F - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x452 | STM32F7**2**xxx | -| 0x452 | STM32F7**3**xxx | -| 0x449 | STM32F7**4**xxx | -| 0x449 | STM32F7**5**xxx | -| 0x451 | STM32F7**6**xxx | -| 0x451 | STM32F7**7**xxx | - -## STM32H7 / ARM Cortex M7F - -| Chip-ID | Product-Code | -| ------- | ------------- | -| 0x450 | STM32H7**4**x | -| 0x450 | STM32H7**5**x | -| 0x480 | STM32H7**A**x | -| 0x480 | STM32H7**B**x | - -## STM32G0 / ARM Cortex M0+ - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x466 | STM32G0**3**xxx | -| 0x466 | STM32G0**4**xxx | -| 0x460 | STM32G0**7**xxx | -| 0x460 | STM32G0**8**xxx | - -## STM32G4 / ARM Cortex M4F - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x468 | STM32G4**31**xx | -| 0x468 | STM32G4**41**xx | -| 0x469 | STM32G4**7**xxx | -| 0x469 | STM32G4**8**xxx | -| 0x479 | STM32G4**91**xx | - -## STM32L0 / ARM Cortex M0+ - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x457 | STM32L0**1**xxx | -| 0x457 | STM32L0**2**xxx | -| 0x425 | STM32L0**31**xx | -| 0x425 | STM32L0**41**xx | -| 0x417 | STM32L0**5**xxx | -| 0x417 | STM32L0**6**xxx | -| 0x447 | STM32L0**7**xxx | -| 0x447 | STM32L0**8**xxx | - -## STM32L1 / ARM Cortex M3 - -| Chip-ID | Product-Code | -| ------- | ---------------- | -| 0x416 | STM32L1xxx**6** | -| 0x416 | STM32L1xxx**8** | -| 0x416 | STM32L1xxx**B** | -| 0x429 | STM32L1xxx**6A** | -| 0x429 | STM32L1xxx**8A** | -| 0x429 | STM32L1xxx**BA** | -| 0x427 | STM32L1xxx**C** | -| 0x436 | STM32L1xxx**D** | -| 0x437 | STM32L1xxx**E** | - -## STM32L4 / ARM Cortex M4F - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x464 | STM32L4**12**xx | -| 0x464 | STM32L4**22**xx | -| 0x435 | STM32L4**3**xxx | -| 0x435 | STM32L4**4**xxx | -| 0x462 | STM32L4**5**xxx | -| 0x462 | STM32L4**6**xxx | -| 0x415 | STM32L4**7**xxx | -| 0x415 | STM32L4**8**xxx | -| 0x461 | STM32L4**96**xx | -| 0x461 | STM32L4**A6**xx | -| 0x470 | STM32L4**R**xx | -| 0x470 | STM32L4**S**xx | -| 0x471 | STM32L4**P5**xx | -| 0x471 | STM32L4**Q5**xx | - -## STM32W / ARM Cortex M3 - -| Chip-ID | Product-Code | -| ------- | --------------- | -| 0x495 | STM32WB**50**xx | -| 0x495 | STM32WB**55**xx | -| 0x497 | STM32WLE**5**xx | diff --git a/doc/supported devices.md b/doc/supported devices.md new file mode 100644 index 000000000..2e96dcd39 --- /dev/null +++ b/doc/supported devices.md @@ -0,0 +1,59 @@ +# MCUs supported by the STlink toolset + +A list of devices supported by the stlink toolset can be found in */inc/stm32.h*. +More commonly these are: + +| Product-Family | ARM Cortex Core | Product Line | +| -------------- | --------------- | ---------------------------------------------------------- | +| STM32F0 | M0 | | +| STM32G0 | M0+ | | +| STM32L0 | M0+ | | +| STM32F10**0** | M3 | Value line | +| STM32F10**1** | M3 | Access line | +| STM32F10**2** | M3 | USB Access line | +| STM32F10**3** | M3 | Performance line | +| STM32F10**5** | M3 | Connectivity line | +| STM32F10**7** | M3 | Connectivity line | +| STM32L1 | M3 | | +| STM32F2 | M3 | | +| STM32F3**01** | M4F | Access line | +| STM32F3**02** | M4F | USB & CAN line | +| STM32F3**03** | M4F | Performance line | +| STM32F3**34** | M4F | Digital Power line | +| STM32F3**73** | M4F | Precision Measurement line (64k/16k / 128k/24k / 265k/32k) | +| STM32F3**18** | M4F | General Purpose line (64k/16k) | +| STM32F3**28** | M4F | General Purpose line (64k/16k) | +| STM32F3**58** | M4F | General Purpose line (265k/48k) | +| STM32F3**78** | M4F | Precision Measurement line (265k/32k) | +| STM32F3**98** | M4F | General Purpose line (512k/80k) | +| STM32F4 | M4F | | +| STM32G4 | M4F | | +| STM32L4 | M4F | | +| STM32F7 | M4F | | +| STM32H7 | M4F | | +| STM32WB | M4F | | +| STM32WL | M4 | | + + +# Chinese Clone-Chips [may work, but without support!] + +## STM32F1 Clone / ARM Cortex M3 (Core-ID: 0x2ba01477) (mostly on Bluepill-Boards) + +**(!) Attention:** Some MCUs may come with with _**Fake-STM32-Marking !**_ + +**(!) Attention:** The Core-ID of these MCUs is in conflict with the one of the original STM32F1-devices. + +| Product-Code | Chip-ID | Comment | +| ------------- | ------- | ------------------------------------------------------------------------- | +| CKS32F103C8T6 | 0x410 | STM32F103C8T6 clone from China Key Systems (CKS) | +| CH32F103C8T6 | 0x410 | STM32F103C8T6 clone from Nanjing Qinheng Microelectronics Co., Ltd. (WCH) | + +## STM32F3 Clone / ARM Cortex M4F (Core-ID: 0x2ba01477) + +**(!) Attention:** The Chip-IDs of these MCUs are in conflict with such of original STM32F1-devices. + +| Product-Code | Chip-ID | Comment | +| ------------ | ------- | ------------------------------------ | +| GD32F303VET6 | 0x414 | STM32F303 clone from GigaDevice (GD) | +| GD32F303CGT6 | 0x430 | STM32F303 clone from GigaDevice (GD) | +| GD32F303VGT6 | 0x430 | STM32F303 clone from GigaDevice (GD) | diff --git a/inc/stm32.h b/inc/stm32.h index 92770bd44..d3c4e5512 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -215,6 +215,6 @@ enum stm32_chipids { #define STM32WB_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN #define STM32L5_PWR_CR1 0x40007000 // RM0438, p. 93,324 -#define STM32L5_PWR_CR1_VOS 8 +#define STM32L5_PWR_CR1_VOS 9 #endif // STM32_H diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index ccce342a4..e7c2392c1 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -292,6 +292,15 @@ int stlink_load_device_params(stlink_t *sl) { } } + if (sl->chip_id == STM32_CHIPID_L5x2xx) { + uint32_t flash_optr; + stlink_read_debug32(sl, STM32L5_FLASH_OPTR, &flash_optr); + + if (sl->flash_size == 512*1024 && (flash_optr & (1 << 22)) != 0) { + sl->flash_pgsz = 0x800; + } + } + // H7 devices with small flash has one bank if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && sl->flash_type == STM32_FLASH_TYPE_H7) { diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index e84b307eb..000f9279d 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -441,8 +441,7 @@ static void unlock_flash(stlink_t *sl) { // Set voltage scaling to range 0 to perform flash operations (RM0438 p. 183) uint32_t mask = (0b11 << STM32L5_PWR_CR1_VOS); uint32_t val; - stlink_read_debug32(sl, STM32L5_PWR_CR1, &val); - if ((val & mask) > (1 << STM32L5_PWR_CR1_VOS)) { + if (!stlink_read_debug32(sl, STM32L5_PWR_CR1, &val) && (val & mask) > (1 << STM32L5_PWR_CR1_VOS)) { val &= ~mask; stlink_write_debug32(sl, STM32L5_PWR_CR1, val); } From 5946076723d77f4283b7e5483c74d66c12f43c76 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 4 Apr 2023 23:54:56 +0200 Subject: [PATCH 1358/1435] General maintenance - Updated pkg-version requirements - Updated version_support.md - Removed Ubuntu 18.04 from GH workflow --- .github/workflows/c-cpp.yml | 90 ------------------------------ cmake/packaging/cpack_config.cmake | 2 +- cmake/packaging/deb/control | 2 +- doc/version_support.md | 12 ++-- 4 files changed, 8 insertions(+), 98 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index fe07c6e44..72163fdf7 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -9,96 +9,6 @@ on: jobs: # Linux - job_linux_18_04_64_gcc: - name: ubuntu-18.04 gcc - runs-on: ubuntu-18.04 - steps: - - uses: actions/checkout@v2 - - name: install dependencies - run: sudo apt update && sudo apt-get install gcc-8 libusb-1.0.0-dev libgtk-3-dev rpm - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - job_linux_18_04_32_gcc: - name: ubuntu-18.04 gcc 32-bit - runs-on: ubuntu-18.04 - steps: - - uses: actions/checkout@v2 - - name: install dependencies - run: sudo apt update && sudo apt-get install gcc-8 libusb-1.0.0-dev libgtk-3-dev rpm - - name: Set compiler flags - run: | - CFLAGS="$CFLAGS -m32" - CXXFLAGS="$CXXFLAGS -m32" - LDFLAGS="$LDFLAGS -m32" - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - job_linux_18_04_64_clang: - name: ubuntu-18.04 clang - runs-on: ubuntu-18.04 - steps: - - uses: actions/checkout@v2 - - name: install dependencies - run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - - job_linux_18_04_32_clang: - name: ubuntu-18.04 clang 32-bit - runs-on: ubuntu-18.04 - steps: - - uses: actions/checkout@v2 - - name: Install dependencies - run: sudo apt update && sudo apt-get install clang-10 libusb-1.0.0-dev libgtk-3-dev rpm - - name: Set compiler flags - run: | - CFLAGS="$CFLAGS -m32" - CXXFLAGS="$CXXFLAGS -m32" - LDFLAGS="$LDFLAGS -m32" - - name: make debug - run: sudo make clean && make debug - - name: make test - run: sudo make clean && make test - - name: make release - run: sudo make clean && make release - - name: sudo make install - run: sudo make clean && sudo make install - - name: sudo make package - run: sudo make package - - name: sudo make uninstall - run: sudo make uninstall && sudo make clean - job_linux_20_04_64_gcc: name: ubuntu-20.04 gcc runs-on: ubuntu-20.04 diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index 55a859189..57d4803d7 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -48,7 +48,7 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av set(CPACK_DEBIAN_PACKAGE_RELEASE "1") # CPACK_DEBIAN_PACKAGE_ARCHITECTURE --> Default: Output of dpkg --print-architecture - set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.10.2), libusb-1.0-0-dev (>= 1.0.21)") + set(CPACK_DEBIAN_PACKAGE_DEPENDS "pkg-config, build-essential, debhelper (>=9), cmake (>= 3.13.0), libusb-1.0-0-dev (>= 1.0.22)") set(CPACK_DEBIAN_PACKAGE_MAINTAINER "Nightwalker-87 ") # CPACK_DEBIAN_PACKAGE_DESCRIPTION --> Default: CPACK_DEBIAN_PACKAGE_DESCRIPTION (as it is set) # CPACK_DEBIAN_PACKAGE_SECTION --> Default: “devel” diff --git a/cmake/packaging/deb/control b/cmake/packaging/deb/control index 2ed3b6b11..7c2ab8fe7 100644 --- a/cmake/packaging/deb/control +++ b/cmake/packaging/deb/control @@ -1,7 +1,7 @@ Source: stlink Priority: optional Maintainer: Nightwalker-87 -Build-Depends: cmake (>= 3.10.2), dh-cmake, debhelper (>= 9), libusb-1.0-0-dev (>= 1.0.21), libgtk-3-dev (>= 3.22.30) +Build-Depends: cmake (>= 3.13.0), dh-cmake, debhelper (>= 9), libusb-1.0-0-dev (>= 1.0.22), libgtk-3-dev (>= 3.22.30) Standards-Version: 4.6.2 Rules-Requires-Root: no Section: electronics diff --git a/doc/version_support.md b/doc/version_support.md index e7d8f444b..43924e502 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,10 +1,10 @@ -_Source:_ [pkgs.org](https://pkgs.org/search) - libusb, cmake, gtk, libgtk) (as of Jan 2022) +_Source:_ [pkgs.org](https://pkgs.org/search) - libusb, cmake, gtk, libgtk (as of Apr 2023) ## Supported Operating Systems ### Microsoft Windows -On Windows users should ensure that cmake **3.10.2** or any later version is installed.
      +On Windows users should ensure that cmake **3.13.0** or any later version is installed.
      Up on compiling c-make will **automatically** download and install the latest compatible version of `libusb`. - Windows 10 @@ -61,7 +61,7 @@ Other Linux-/Unix-based Operating Systems: | Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | | Adélie 1.0 | 1.0.23 | 3.**16.4** | 3.24.23 | | -## Unsupported Operating Systems (as of Release v1.7.1) +## Unsupported Operating Systems (as of Release v1.8.0) Systems with highlighted versions remain compatible with this toolset. @@ -77,7 +77,7 @@ Systems with highlighted versions remain compatible with this toolset. | Alpine 3.12 | 1.0.**23** | 3.**17.2** | May 2022 | | openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.**17.0** | Dec 2022 | | Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | -| openSUSE Leap 15.2 [x64] | 1.0.**21** | 3.**17.0** | Dec 2021 | +| openSUSE Leap 15.2 [x64] | 1.0.21 | 3.**17.0** | Dec 2021 | | Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | | NetBSD 7.x | 1.0.**22** | 3.**16.1** | Jun 2020 | | Alpine 3.11 | 1.0.**23** | 3.**15.5** | Nov 2021 | @@ -88,8 +88,8 @@ Systems with highlighted versions remain compatible with this toolset. | Fedora 30 | 1.0.**22**(`libusbx`) | 3.**14.2** | May 2020 | | Ubuntu 19.10 (Eoan) | 1.0.**23** | 3.**13.4** | Jul 2020 | | Alpine 3.9 | 1.0.**22** | 3.**13.0** | Jan 2021 | -| Ubuntu 18.04 LTS (Bionic) | 1.0.**21** | 3.**10.2** | **Apr 2023** | -| openSUSE Leap 15.1 [x64] | 1.0.**21** | 3.**10.2** | Jan 2021 | +| Ubuntu 18.04 LTS (Bionic) | 1.0.21 | 3.10.2 | Apr 2023 | +| openSUSE Leap 15.1 [x64] | 1.0.21 | 3.10.2 | Jan 2021 | | Debian 9 (Stretch) | 1.0.21 | 3.7.2 | Jun 2022 | | Slackware 14.2 | 1.0.20 | 3.5.2 | | | OpenMandriva Lx 3.0x | 1.0.20 | 3.4.2 | | From 982408e6ee4504b9eac3e679fc94e2d6c95e02e4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 5 Apr 2023 21:33:49 +0200 Subject: [PATCH 1359/1435] Fixes regarding version support - Updated version_support.md - Updated version requirements for libusb --- config/chips/{L5x5.chip => L5x5xx.chip} | 0 doc/version_support.md | 3 ++- src/stlink-lib/libusb_settings.h | 4 ++-- 3 files changed, 4 insertions(+), 3 deletions(-) rename config/chips/{L5x5.chip => L5x5xx.chip} (100%) diff --git a/config/chips/L5x5.chip b/config/chips/L5x5xx.chip similarity index 100% rename from config/chips/L5x5.chip rename to config/chips/L5x5xx.chip diff --git a/doc/version_support.md b/doc/version_support.md index 43924e502..358e65fb9 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -21,6 +21,7 @@ Maintained versions of: - Arch Linux - FreeBSD - NetBSD +- OpenBSD Other Linux-/Unix-based Operating Systems: @@ -75,7 +76,7 @@ Systems with highlighted versions remain compatible with this toolset. | Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | | Fedora 33 [x64] | 1.0.**23** (`libusbx`) | 3.**18.3** | Nov 2021 | | Alpine 3.12 | 1.0.**23** | 3.**17.2** | May 2022 | -| openSUSE Leap 15.3 [x64] | 1.0.**21** | 3.**17.0** | Dec 2022 | +| openSUSE Leap 15.3 [x64] | 1.0.21 | 3.**17.0** | Dec 2022 | | Fedora 32 [x64] | 1.0.**23** (`libusbx`) | 3.**17.0** | May 2021 | | openSUSE Leap 15.2 [x64] | 1.0.21 | 3.**17.0** | Dec 2021 | | Ubuntu 20.10 (Groovy) | 1.0.**23** | 3.**16.3** | Jul 2021 | diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index ee690e0b1..3777f720b 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -33,9 +33,9 @@ #if defined (__FreeBSD__) #define MINIMAL_API_VERSION 0x01000102 // v1.0.16 #elif defined (__OpenBSD__) - #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 + #define MINIMAL_API_VERSION 0x01000106 // v1.0.22 #elif defined (__linux__) - #define MINIMAL_API_VERSION 0x01000105 // v1.0.21 + #define MINIMAL_API_VERSION 0x01000106 // v1.0.22 #elif defined (_WIN32) #define MINIMAL_API_VERSION 0x01000109 // v1.0.25 #endif From 1d301a5498433900250fe2a8c0e10dfb7f44d7a4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 7 Apr 2023 23:33:28 +0200 Subject: [PATCH 1360/1435] Fix for option byte read (Closes #1156) --- src/st-flash/flash.c | 38 ++++++++++++++++++++++------------- src/st-util/semihosting.c | 9 +++++---- src/stlink-lib/common.c | 15 ++++++++------ src/stlink-lib/option_bytes.c | 3 --- 4 files changed, 38 insertions(+), 27 deletions(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 3b25dc214..d7d17f66f 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -1,17 +1,22 @@ /* Simple wrapper around the stlink_flash_write function */ -// TODO - this should be done as just a simple flag to the st-util command line... - -#include #include #include #include + +#include +#include #include +#include #include #include + +#include +#include +#include + #include "flash.h" -#include "option_bytes.h" static stlink_t *connected_stlink = NULL; @@ -215,20 +220,25 @@ int main(int ac, char** av) { (unsigned)remaining_option_length, sl->option_base); - if (NULL != o.filename) { - if (0 == o.size) { - o.size = sl->option_size; + uint32_t option_byte = 0; + err = stlink_read_option_bytes32(sl, &option_byte); + if (err == -1) { + printf("could not read option bytes (%d)\n", err); + goto on_error; + } else if (NULL != o.filename) { + int fd = open(o.filename, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); + if (fd == -1) { + fprintf(stderr, "open(%s) == -1\n", o.filename); + goto on_error; } - err = stlink_fread(sl, o.filename, o.format == FLASH_FORMAT_IHEX, sl->option_base, o.size); - } else { - uint32_t option_byte = 0; - err = stlink_read_option_bytes32(sl, &option_byte); + err = (uint32_t)write(fd, &option_byte, 4); if (err == -1) { - printf("could not read option bytes (%d)\n", err); + printf("could not write buffer to file (%d)\n", err); goto on_error; - } else { - printf("%08x\n", option_byte); } + close(fd); + } else { + printf("%08x\n", option_byte); } } else if (o.area == FLASH_OPTION_BYTES_BOOT_ADD) { uint32_t option_byte = 0; diff --git a/src/st-util/semihosting.c b/src/st-util/semihosting.c index 32169c812..f603f6224 100644 --- a/src/st-util/semihosting.c +++ b/src/st-util/semihosting.c @@ -1,11 +1,13 @@ #include +#include #include + +#include #include #include -#include -#include #include + #include #include "semihosting.h" @@ -256,8 +258,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - DLOG("Semihosting: write(%d, target_addr:0x%08x, %u)\n", fd, buffer_address, - buffer_len); + DLOG("Semihosting: write(%d, target_addr:0x%08x, %u)\n", fd, buffer_address, buffer_len); *ret = (uint32_t)write(fd, buffer, buffer_len); saved_errno = errno; diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index e7c2392c1..fac97278e 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -1,18 +1,21 @@ -#include +#include +#include +#include + #include +#include #include #include #include -#include -#include -#include -#include + #include #include -#include "common_flash.h" #include "calculate.h" +#include "common_flash.h" #include "map_file.h" +#include "md5.h" + #include "common.h" #ifndef O_BINARY diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 32becc5cf..9cbdd097b 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -1007,11 +1007,8 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { case STM32_CHIPID_F76xxx: return stlink_read_option_bytes_f7(sl, option_byte); case STM32_CHIPID_G0_CAT1: - return stlink_read_option_bytes_gx(sl, option_byte); case STM32_CHIPID_G0_CAT2: - return stlink_read_option_bytes_gx(sl, option_byte); case STM32_CHIPID_G4_CAT2: - return stlink_read_option_bytes_gx(sl, option_byte); case STM32_CHIPID_G4_CAT3: return stlink_read_option_bytes_gx(sl, option_byte); default: From 1745bf5193c4d3186d4f6fde59cc86e9bad6e61b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 8 Apr 2023 02:16:48 +0200 Subject: [PATCH 1361/1435] [doc] Human-readable flash_type in chip-id files (Closes #1155) --- src/stlink-lib/chipid.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 075c19c17..3d122a02e 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -83,6 +83,7 @@ void process_chipfile(char *fname) { } else if (strcmp(word, "flash_type") == 0) { buf[strlen(buf) - 1] = 0; // chomp newline sscanf(buf, "%*s %n", &nc); + // Match human readable flash_type with enum stm32_flash_type { }. if (strcmp(value, "F0_F1_F3") == 0) { ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; } else if (strcmp(value, "F1_XL") == 0) { From 39f306feaa932729c06a3f546721f3659886f46c Mon Sep 17 00:00:00 2001 From: Nicolas signed-log FORMICHELLA Date: Sat, 15 Apr 2023 08:02:19 +0200 Subject: [PATCH 1362/1435] Fix broken doc link --- doc/tutorial.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index e694bf8d0..7e87a7bd9 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -81,7 +81,7 @@ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ and the `idVendor` of `0483` and `idProduct` of `374b` matches the vendor id from the `lsusb` output. -Make sure that you have all 3 files from here: https://github.com/stlink-org/stlink/tree/master/etc/udev/rules.d in your `/etc/udev/rules.d` directory. After copying new files or editing existing files in `/etc/udev/ruled.d` you should run the following: +Make sure that you have all 3 files from [/config/udev/rules.d](https://github.com/stlink-org/stlink/tree/master/config/udev/rules.d) in your `/etc/udev/rules.d` directory. After copying new files or editing existing files in `/etc/udev/ruled.d` you should run the following: ``` sudo udevadm control --reload-rules From 0a5cad7ee8e6950f8816b654b41d6bbaa96f6846 Mon Sep 17 00:00:00 2001 From: Mingjie Shen Date: Sat, 22 Apr 2023 00:03:54 -0400 Subject: [PATCH 1363/1435] Fix unbounded write of sscanf Format string "%s" that does not control the length of data written may overflow. --- src/stlink-lib/chipid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 3d122a02e..44d93fedd 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -64,7 +64,7 @@ void process_chipfile(char *fname) { (strncmp(buf, " ", strlen(" ")) == 0)) continue; // ignore empty lines - sscanf(buf, "%s %s", word, value); + sscanf(buf, "%63s %63s", word, value); if (strcmp(word, "dev_type") == 0) { buf[strlen(buf) - 1] = 0; // chomp newline From 98902c271ef20564e95b73cf8e0ee4a8600a8bd1 Mon Sep 17 00:00:00 2001 From: Mingjie Shen Date: Sat, 22 Apr 2023 00:53:29 -0400 Subject: [PATCH 1364/1435] Add null check for return value of stlink_chipid_get_params() Pass a null pointer to "%s" is undefined behaviour. --- src/st-trace/trace.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 20e04c080..8c6e3c62b 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -591,7 +591,8 @@ int main(int argc, char **argv) { if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); - ELOG("We do not support SWO output for device '%s'\n", params->dev_type); + ELOG("We do not support SWO output for device '%s'\n", + params ? params->dev_type : ""); if (!settings.force) return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; } From 8f97e62708f5eff3e66669976d17cd0ecbf29125 Mon Sep 17 00:00:00 2001 From: Mingjie Shen Date: Sat, 22 Apr 2023 18:10:31 -0400 Subject: [PATCH 1365/1435] Check return values of sscanf() Failing to check that a call to 'scanf' actually writes to an output variable can lead to unexpected behavior at reading time. --- src/st-util/gdb-server.c | 6 ++++-- src/stlink-lib/chipid.c | 5 ++++- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 802e23c06..d64073cf7 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -160,8 +160,10 @@ int parse_options(int argc, char** argv, st_state_t *st) { break; case 'p': - sscanf(optarg, "%i", &q); - if (q < 0) { + if (sscanf(optarg, "%i", &q) != 1) { + fprintf(stderr, "Invalid port %s\n", optarg); + exit(EXIT_FAILURE); + } else if (q < 0) { fprintf(stderr, "Can't use a negative port to listen on: %d\n", q); exit(EXIT_FAILURE); } diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 44d93fedd..347d89e14 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -64,7 +64,10 @@ void process_chipfile(char *fname) { (strncmp(buf, " ", strlen(" ")) == 0)) continue; // ignore empty lines - sscanf(buf, "%63s %63s", word, value); + if (sscanf(buf, "%63s %63s", word, value) != 2) { + fprintf(stderr, "Failed to read keyword or value\n"); + continue; + } if (strcmp(word, "dev_type") == 0) { buf[strlen(buf) - 1] = 0; // chomp newline From 222ff4716520a815f0c3ed7360f93227a080e64a Mon Sep 17 00:00:00 2001 From: Oleksiy Slyshyk Date: Fri, 28 Apr 2023 17:59:47 +0300 Subject: [PATCH 1366/1435] fix warn in a few *.cmake --- cmake/modules/Findlibusb.cmake | 4 ++-- cmake/modules/get_version.cmake | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index fbbda5ba3..6f0a21da6 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -60,7 +60,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to if (WIN32 AND NOT EXISTS "/etc/debian_version") # ... on native Windows systems set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_BINARY_DIR}/${LIBUSB_WIN_ARCHIVE}) set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_BINARY_DIR}/3rdparty/libusb-${LIBUSB_WIN_VERSION}) - else (EXISTS "/etc/debian_version" AND MINGW) # ... only for cross-building on Debian + elseif (EXISTS "/etc/debian_version" AND MINGW) # ... only for cross-building on Debian set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_SOURCE_DIR}/build-mingw-${ARCH}/${LIBUSB_WIN_ARCHIVE}) set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_SOURCE_DIR}/build-mingw-${ARCH}/3rdparty/libusb-${LIBUSB_WIN_VERSION}) endif () @@ -102,7 +102,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to NO_CMAKE_FIND_ROOT_PATH ) - else (MSVC) + elseif (MSVC) set(LIBUSB_NAME libusb-1.0.lib) find_library( LIBUSB_LIBRARY NAMES ${LIBUSB_NAME} diff --git a/cmake/modules/get_version.cmake b/cmake/modules/get_version.cmake index 70fbde816..8211d9c84 100644 --- a/cmake/modules/get_version.cmake +++ b/cmake/modules/get_version.cmake @@ -55,7 +55,7 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") message(STATUS "Rewrite ${PROJECT_SOURCE_DIR}/.version with ${__version_str}!") endif () - else (NOT EXISTS "${PROJECT_SOURCE_DIR}/.version") + elseif (NOT EXISTS "${PROJECT_SOURCE_DIR}/.version") # No local .version file found: Create a new one... file(WRITE "${PROJECT_SOURCE_DIR}/.version" ${__version_str}) From 1775184084f189409d91522e1d14f8d5fb84b61e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 Apr 2023 14:31:50 +0200 Subject: [PATCH 1367/1435] General Project Update - Updated CHANGELOG.md - Updated README.md - Merged flash loader source files --- CHANGELOG.md | 13 +- CMakeLists.txt | 2 - README.md | 1 - src/st-util/gdb-server.c | 2 +- src/stlink-lib/common_flash.c | 2 +- src/stlink-lib/flash_loader.c | 500 +++++++++++++++++++++++++++++++++- src/stlink-lib/flash_loader.h | 5 + src/stlink-lib/flashloader.c | 496 --------------------------------- src/stlink-lib/flashloader.h | 13 - 9 files changed, 517 insertions(+), 517 deletions(-) delete mode 100644 src/stlink-lib/flashloader.c delete mode 100644 src/stlink-lib/flashloader.h diff --git a/CHANGELOG.md b/CHANGELOG.md index 551a4ba09..c930999cd 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,10 +1,11 @@ # stlink Changelog -# v1.7.1 +# v1.8.0 Release date: 2023-xx-xx -This release drops support for some older operating systems. Check project README for details. +This release drops support for macOS and some older operating systems. Check project README for details. +Removed Travis CI integration as it is no longer functional. Updated system requirements: - `cmake` >= 3.10.2 @@ -14,6 +15,7 @@ Updated system requirements: Features: - Support for writing option bytes on STM32F0/F1/F3 ([#346](https://github.com/stlink-org/stlink/pull/346), [#458](https://github.com/stlink-org/stlink/pull/458), [#808](https://github.com/stlink-org/stlink/pull/808), [#1084](https://github.com/stlink-org/stlink/pull/1084), [#1112](https://github.com/stlink-org/stlink/pull/1112)) +- Initial support for STM32 L5 & U5 devices and minor changes ([#1005](https://github.com/stlink-org/stlink/pull/1005), [#1096](https://github.com/stlink-org/stlink/pull/1096), [#1247](https://github.com/stlink-org/stlink/pull/1247), [#1300](https://github.com/stlink-org/stlink/pull/1300), [#1301](https://github.com/stlink-org/stlink/pull/1301)) - Added chip-IDs for STM32G0B0/G0B1/G0C1/G050/G051/G061 ([#1140](https://github.com/stlink-org/stlink/pull/1140)) - Added option byte info for STM32F411XX ([#1141](https://github.com/stlink-org/stlink/pull/1141)) - Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) @@ -22,6 +24,7 @@ Features: - Added support for STLINK-V3 devices with no MSD ([#1185](https://github.com/stlink-org/stlink/pull/1185)) - Updated gdb-server.c to allow external memory access on STM32H73xx ([#1196](https://github.com/stlink-org/stlink/pull/1196), [#1197](https://github.com/stlink-org/stlink/pull/1197)) - Erase addr size / section of the flash memory with st-flash ([#1213](https://github.com/stlink-org/stlink/pull/1213)) +- Added support for STM32L4Q5 ([#1224](https://github.com/stlink-org/stlink/pull/1224), [#1295](https://github.com/stlink-org/stlink/pull/1295)) - Added writing and reading for STM32WL option bytes ([#1226](https://github.com/stlink-org/stlink/pull/1226), [#1227](https://github.com/stlink-org/stlink/pull/1227)) - Added parametres option_base, option_size for F401xD_xE ([#1235](https://github.com/stlink-org/stlink/pull/1235)) - Added support for option bytes to F1xx_XLD (GD32F30x) ([#1250](https://github.com/stlink-org/stlink/pull/1250)) @@ -35,6 +38,7 @@ Updates & changes: - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation (commit [#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) +- [doc] Human-readable flash_type in chip-id files ([#1155](https://github.com/stlink-org/stlink/pull/1155), commit [#1745bf5](https://github.com/stlink-org/stlink/commit/1745bf5193c4d3186d4f6fde59cc86e9bad6e61b)) - Dropped execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) - Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) - Removed redundant array ([#1178](https://github.com/stlink-org/stlink/pull/1178)) @@ -58,6 +62,7 @@ Fixes: - Removed limit check for WRITEMEM_32BIT ([#1157](https://github.com/stlink-org/stlink/pull/1157)) - Fixed get_stm32l0_flash_base address for STM32L152RE ([#1161](https://github.com/stlink-org/stlink/pull/1161), [#1162](https://github.com/stlink-org/stlink/pull/1162)) - Fixed segfault if chip was not found in chip config files ([#1138](https://github.com/stlink-org/stlink/pull/1138), [#1163](https://github.com/stlink-org/stlink/pull/1163), [#1165](https://github.com/stlink-org/stlink/pull/1165), [#1166](https://github.com/stlink-org/stlink/pull/1166), [#1170](https://github.com/stlink-org/stlink/pull/1170)) +- Fixed parsing hex numbers in chip config files ([#1156](https://github.com/stlink-org/stlink/pull/1156), commit [#1d301a5](https://github.com/stlink-org/stlink/commit/1d301a5498433900250fe2a8c0e10dfb7f44d7a4)) - Fixed parsing hex numbers in chip config files ([#1169](https://github.com/stlink-org/stlink/pull/1169)) - Corrected flash_pagesize to use hex format ([#1172](https://github.com/stlink-org/stlink/pull/1172)) - Fixed compilation for MSVC ([#1176](https://github.com/stlink-org/stlink/pull/1176)) @@ -65,6 +70,7 @@ Fixes: - st-flash and other utilities search for chip files in the wrong directory ([#1180](https://github.com/stlink-org/stlink/pull/1180), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) - Fixed broken build on 32 bit systems ([#985](https://github.com/stlink-org/stlink/pull/985), [#1175](https://github.com/stlink-org/stlink/pull/1175), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) - Define 'SSIZE_MAX' if not defined ([#1183](https://github.com/stlink-org/stlink/pull/1183)) +- STM32G031G8: BOOT_LOCK is not possible to change on option bytes address 0x1FFF7870 ([#1194](https://github.com/stlink-org/stlink/pull/1194)) - Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) - Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) - Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214)) @@ -78,6 +84,9 @@ Fixes: - Fixed st-trace reconnect on Windows ([#1272](https://github.com/stlink-org/stlink/pull/1272), [#1292](https://github.com/stlink-org/stlink/pull/1292)) - [compilation] Corrected path to stlink/chips subdirectory ([#1276](https://github.com/stlink-org/stlink/pull/1276), [#1279](https://github.com/stlink-org/stlink/pull/1279)) - [compilation] Fixed GUI compilation failure on OpenBSD i386 ([#1284](https://github.com/stlink-org/stlink/pull/1284)) +- Fixed unbounded write and check return values of sscanf ([#1306](https://github.com/stlink-org/stlink/pull/1306)) +- Added null check for return value of stlink_chipid_get_params() ([#1307](https://github.com/stlink-org/stlink/pull/1307)) +- Fixed warning in a few *.cmake files ([#1309](https://github.com/stlink-org/stlink/pull/1309)) # v1.7.0 diff --git a/CMakeLists.txt b/CMakeLists.txt index 4ce0ee126..bce4def8f 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -174,7 +174,6 @@ set(STLINK_HEADERS src/stlink-lib/common_flash.h src/stlink-lib/common.h src/stlink-lib/flash_loader.h - src/stlink-lib/flashloader.h src/stlink-lib/helper.h src/stlink-lib/libusb_settings.h src/stlink-lib/logging.h @@ -192,7 +191,6 @@ set(STLINK_SOURCE src/stlink-lib/common_flash.c src/stlink-lib/common.c src/stlink-lib/flash_loader.c - src/stlink-lib/flashloader.c src/stlink-lib/helper.c src/stlink-lib/logging.c src/stlink-lib/map_file.c diff --git a/README.md b/README.md index 3101fb560..0e846b336 100644 --- a/README.md +++ b/README.md @@ -8,7 +8,6 @@ ![GitHub contributors](https://img.shields.io/github/contributors/stlink-org/stlink) [![CodeQL](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml/badge.svg)](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml) [![C/C++ CI](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml/badge.svg?branch=testing)](https://github.com/stlink-org/stlink/actions/workflows/c-cpp.yml) -[![Linux Status](https://img.shields.io/travis/stlink-org/stlink/master?env=BADGE=linux&label=linux)](https://travis-ci.org/stlink-org/stlink) Recent new features and bugfixes can be found in the [Changelog](CHANGELOG.md) of this software project. diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index d64073cf7..99cc0170b 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -28,7 +28,7 @@ #include #include #include -#include "flashloader.h" +#include "flash_loader.h" #include "gdb-remote.h" #include "gdb-server.h" #include "semihosting.h" diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 000f9279d..740c93690 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -3,7 +3,7 @@ #include #include #include "calculate.h" -#include "flashloader.h" +#include "flash_loader.h" #include "common_flash.h" #include "map_file.h" #include "common.h" diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 94978a51f..852ba6c20 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -6,6 +6,7 @@ #include #include #include "flash_loader.h" +#include "common_flash.h" #define FLASH_REGS_BANK2_OFS 0x40 #define FLASH_BANK2_START_ADDR 0x08080000 @@ -386,7 +387,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe * The chunk size for loading is not rounded. The flash loader * subtracts the size of the written block (1-8 bytes) from * the remaining size each time. A negative value may mean that - * several bytes garbage has been written due to the unaligned + * several bytes garbage have been written due to the unaligned * firmware size. */ if ((int32_t)rr.r[2] > 0 || (int32_t)rr.r[2] < -7) { @@ -412,3 +413,500 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe return(-1); } + + +/* ================================================== + * === Content from old source file flashloader.c === + * ================================================== + */ + +#define L1_WRITE_BLOCK_SIZE 0x80 +#define L0_WRITE_BLOCK_SIZE 0x40 + +int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, + uint32_t len, uint32_t pagesize) { + unsigned int count, off; + unsigned int num_half_pages = len / pagesize; + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + flash_loader_t fl; + bool use_loader = true; + int ret = 0; + + // enable half page write + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << FLASH_L1_FPRG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + val |= (1 << FLASH_L1_PROG); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + + wait_flash_busy(sl); + + for (count = 0; count < num_half_pages; count++) { + if (use_loader) { + ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, + base + count * pagesize, pagesize); + if (ret && count == 0) { + /* It seems that stm32lx devices have a problem when it is blank */ + WLOG("Failed to use flash loader, fallback to soft write\n"); + use_loader = false; + } + } + if (!use_loader) { + ret = 0; + for (off = 0; off < pagesize && !ret; off += 64) { + size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; + memcpy(sl->q_buf, base + count * pagesize + off, chunk); + ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); + } + } + + if (ret) { + WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", addr + count * pagesize); + break; + } + + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are misleading + fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); + fflush(stdout); + } + + // wait for sr.busy to be cleared + wait_flash_busy(sl); + } + + // disable half page write + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + return (ret); +} + +static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { + uint32_t cr_reg, x; + + x = read_flash_cr(sl, bank); + + if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; + x |= 1 << FLASH_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + cr_reg = STM32L4_FLASH_CR; + x &= ~STM32L4_FLASH_CR_OPBITS; + x |= (1 << STM32L4_FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + cr_reg = STM32L5_FLASH_NSCR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = STM32Gx_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + cr_reg = STM32WB_FLASH_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; + x |= (1 << FLASH_H7_CR_PG); + } else { + cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; + x = (1 << FLASH_CR_PG); + } + + stlink_write_debug32(sl, cr_reg, x); +} + +static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { + uint32_t rcc, rcc_dma_mask, value; + + rcc = rcc_dma_mask = value = 0; + + switch (sl->flash_type) { + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + rcc = STM32F1_RCC_AHBENR; + rcc_dma_mask = STM32F1_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_F2_F4: + case STM32_FLASH_TYPE_F7: + rcc = STM32F4_RCC_AHB1ENR; + rcc_dma_mask = STM32F4_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_G0: + rcc = STM32G0_RCC_AHBENR; + rcc_dma_mask = STM32G0_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_G4: + case STM32_FLASH_TYPE_L4: + rcc = STM32G4_RCC_AHB1ENR; + rcc_dma_mask = STM32G4_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_L0_L1: + if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { + rcc = STM32L1_RCC_AHBENR; + rcc_dma_mask = STM32L1_RCC_DMAEN; + } else { + rcc = STM32L0_RCC_AHBENR; + rcc_dma_mask = STM32L0_RCC_DMAEN; + } + break; + case STM32_FLASH_TYPE_L5_U5: + rcc = STM32L5_RCC_AHB1ENR; + rcc_dma_mask = STM32L5_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_H7: + rcc = STM32H7_RCC_AHB1ENR; + rcc_dma_mask = STM32H7_RCC_DMAEN; + break; + case STM32_FLASH_TYPE_WB_WL: + rcc = STM32WB_RCC_AHB1ENR; + rcc_dma_mask = STM32WB_RCC_DMAEN; + break; + default: + return; + } + + if (!stlink_read_debug32(sl, rcc, &value)) { + if (bckpRstr) { + value = (value & (~rcc_dma_mask)) | fl->rcc_dma_bkp; + } else { + fl->rcc_dma_bkp = value & rcc_dma_mask; + value &= ~rcc_dma_mask; + } + stlink_write_debug32(sl, rcc, value); + } +} + +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { + // disable DMA + set_dma_state(sl, fl, 0); + + // wait for ongoing op to finish + wait_flash_busy(sl); + // Clear errors + clear_flash_error(sl); + + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4)) { + ILOG("Starting Flash write for F2/F4/F7/L4\n"); + + // Flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + + unlock_flash_if(sl); // first unlock the cr + + int voltage; + if (sl->version.stlink_v == 1) { + WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); + voltage = 3200; + } else { + voltage = stlink_target_voltage(sl); + } + + if (voltage == -1) { + ELOG("Failed to read Target voltage\n"); + return (-1); + } + + if (sl->flash_type == STM32_FLASH_TYPE_L4) { + // L4 does not have a byte-write mode + if (voltage < 1710) { + ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); + return (-1); + } + } else { + if (voltage > 2700) { + ILOG("enabling 32-bit flash writes\n"); + write_flash_cr_psiz(sl, 2, BANK_1); + } else { + ILOG("Target voltage (%d mV) too low for 32-bit flash, " + "using 8-bit flash writes\n", + voltage); + write_flash_cr_psiz(sl, 0, BANK_1); + } + } + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + ILOG("Starting Flash write for WB/G0/G4/L5/U5\n"); + + unlock_flash_if(sl); // unlock flash if necessary + set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + ILOG("Starting Flash write for L0\n"); + + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // disable pecr protection + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, + FLASH_L0_PEKEY2); + + // check pecr.pelock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 0)) { + ELOG("pecr.pelock not clear\n"); + return (-1); + } + + // unlock program memory + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, + FLASH_L0_PRGKEY2); + + // check pecr.prglock is cleared + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + if (val & (1 << 1)) { + ELOG("pecr.prglock not clear\n"); + return (-1); + } + + /* Flash loader initialisation */ + if (stlink_flash_loader_init(sl, fl) == -1) { + // L0/L1 have fallback to soft write + WLOG("stlink_flash_loader_init() == -1\n"); + } + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); + + // flash loader initialisation + if (stlink_flash_loader_init(sl, fl) == -1) { + ELOG("stlink_flash_loader_init() == -1\n"); + return (-1); + } + + // unlock flash + unlock_flash_if(sl); + + // set programming mode + set_flash_cr_pg(sl, BANK_1); + if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + set_flash_cr_pg(sl, BANK_2); + } + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + ILOG("Starting Flash write for H7\n"); + + unlock_flash_if(sl); // unlock the cr + set_flash_cr_pg(sl, BANK_1); // set programming mode + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + set_flash_cr_pg(sl, BANK_2); + } + if (sl->chip_id != STM32_CHIPID_H7Ax) { + // set parallelism + write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + } + } + } else { + ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + return (-1); + } + + return (0); +} + +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, + stm32_addr_t addr, uint8_t *base, uint32_t len) { + size_t off; + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4)) { + size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; + for (off = 0; off < len;) { + size_t size = len - off > buf_size ? buf_size : len - off; + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + off += size; + } + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz + 1), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } + + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + } + fprintf(stdout, "\n"); + + // flash writes happen as 2 words at a time + if ((off / sizeof(uint32_t)) % 2 != 0) { + stlink_write_debug32(sl, addr + (uint32_t)off, + 0); // write a single word of zeros + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + } + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? + L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; + + DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + + off = 0; + + if (len > pagesize) { + if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { + return (-1); + } else { + off = (size_t)(len / pagesize) * pagesize; + } + } + + // write remaining word in program memory + for (; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { + fprintf(stdout, "\r%3u/%3u pages written", + (unsigned int)(off / sl->flash_pgsz + 1), + (unsigned int)(len / sl->flash_pgsz)); + fflush(stdout); + } + + write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + stlink_write_debug32(sl, addr + (uint32_t)off, data); + + // wait for sr.busy to be cleared + do { + stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); + } while ((val & (1 << 0)) != 0); + + // TODO: check redo write operation + } + fprintf(stdout, "\n"); + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + int write_block_count = 0; + for (off = 0; off < len; off += sl->flash_pgsz) { + // adjust last write size + size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; + + // unlock and set programming mode + unlock_flash_if(sl); + + DLOG("Finished unlocking flash, running loader!\n"); + + if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, + size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", + (unsigned)(addr + off)); + check_flash_error(sl); + return (-1); + } + + lock_flash(sl); + + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading + fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, + (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { + for (off = 0; off < len;) { + // Program STM32H7x with 64-byte Flash words + size_t chunk = (len - off > 64) ? 64 : len - off; + memcpy(sl->q_buf, base + off, chunk); + stlink_write_mem32(sl, addr + (uint32_t)off, 64); + wait_flash_busy(sl); + + off += chunk; + + if (sl->verbose >= 1) { + // show progress + fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, + (unsigned int)len); + fflush(stdout); + } + } + if (sl->verbose >= 1) { + fprintf(stdout, "\n"); + } + } else { + return (-1); + } + + return check_flash_error(sl); +} + +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { + uint32_t dhcsr; + + if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_G0) || + (sl->flash_type == STM32_FLASH_TYPE_G4) || + (sl->flash_type == STM32_FLASH_TYPE_H7) || + (sl->flash_type == STM32_FLASH_TYPE_L4) || + (sl->flash_type == STM32_FLASH_TYPE_L5_U5) || + (sl->flash_type == STM32_FLASH_TYPE_WB_WL)) { + + clear_flash_cr_pg(sl, BANK_1); + if ((sl->flash_type == STM32_FLASH_TYPE_H7 && + sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + clear_flash_cr_pg(sl, BANK_2); + } + lock_flash(sl); + } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + uint32_t val; + uint32_t flash_regs_base = get_stm32l0_flash_base(sl); + + // reset lock bits + stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); + val |= (1 << 0) | (1 << 1) | (1 << 2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); + } + + // enable interrupt + if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { + stlink_write_debug32(sl, STLINK_REG_DHCSR, + STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); + } + + // restore DMA state + set_dma_state(sl, fl, 1); + + return (0); +} diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 368b6ab8b..0d39a9a48 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -7,6 +7,7 @@ #ifndef STLINK_FLASH_LOADER_H_ #define STLINK_FLASH_LOADER_H_ +#include #include #include @@ -16,4 +17,8 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); +int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); +int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); + #endif // STLINK_FLASH_LOADER_H_ diff --git a/src/stlink-lib/flashloader.c b/src/stlink-lib/flashloader.c deleted file mode 100644 index 4adf93a86..000000000 --- a/src/stlink-lib/flashloader.c +++ /dev/null @@ -1,496 +0,0 @@ -#include -#include -#include -#include "flashloader.h" -#include "common_flash.h" - -#define L1_WRITE_BLOCK_SIZE 0x80 -#define L0_WRITE_BLOCK_SIZE 0x40 - -int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len, uint32_t pagesize) { - unsigned int count, off; - unsigned int num_half_pages = len / pagesize; - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - flash_loader_t fl; - bool use_loader = true; - int ret = 0; - - // enable half page write - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << FLASH_L1_FPRG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - val |= (1 << FLASH_L1_PROG); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - - wait_flash_busy(sl); - - for (count = 0; count < num_half_pages; count++) { - if (use_loader) { - ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, - base + count * pagesize, pagesize); - if (ret && count == 0) { - /* It seems that stm32lx devices have a problem when it is blank */ - WLOG("Failed to use flash loader, fallback to soft write\n"); - use_loader = false; - } - } - if (!use_loader) { - ret = 0; - for (off = 0; off < pagesize && !ret; off += 64) { - size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; - memcpy(sl->q_buf, base + count * pagesize + off, chunk); - ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); - } - } - - if (ret) { - WLOG("l1_stlink_flash_loader_run(%#x) failed! == -1\n", addr + count * pagesize); - break; - } - - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are misleading - fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); - fflush(stdout); - } - - // wait for sr.busy to be cleared - wait_flash_busy(sl); - } - - // disable half page write - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val &= ~((1 << FLASH_L1_FPRG) | (1 << FLASH_L1_PROG)); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - return (ret); -} - -static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { - uint32_t cr_reg, x; - - x = read_flash_cr(sl, bank); - - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; - x |= 1 << FLASH_CR_PG; - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - x &= ~STM32L4_FLASH_CR_OPBITS; - x |= (1 << STM32L4_FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; - x |= (1 << FLASH_H7_CR_PG); - } else { - cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; - x = (1 << FLASH_CR_PG); - } - - stlink_write_debug32(sl, cr_reg, x); -} - -static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { - uint32_t rcc, rcc_dma_mask, value; - - rcc = rcc_dma_mask = value = 0; - - switch (sl->flash_type) { - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - rcc = STM32F1_RCC_AHBENR; - rcc_dma_mask = STM32F1_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_F2_F4: - case STM32_FLASH_TYPE_F7: - rcc = STM32F4_RCC_AHB1ENR; - rcc_dma_mask = STM32F4_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_G0: - rcc = STM32G0_RCC_AHBENR; - rcc_dma_mask = STM32G0_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_G4: - case STM32_FLASH_TYPE_L4: - rcc = STM32G4_RCC_AHB1ENR; - rcc_dma_mask = STM32G4_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_L0_L1: - if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { - rcc = STM32L1_RCC_AHBENR; - rcc_dma_mask = STM32L1_RCC_DMAEN; - } else { - rcc = STM32L0_RCC_AHBENR; - rcc_dma_mask = STM32L0_RCC_DMAEN; - } - break; - case STM32_FLASH_TYPE_L5_U5: - rcc = STM32L5_RCC_AHB1ENR; - rcc_dma_mask = STM32L5_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_H7: - rcc = STM32H7_RCC_AHB1ENR; - rcc_dma_mask = STM32H7_RCC_DMAEN; - break; - case STM32_FLASH_TYPE_WB_WL: - rcc = STM32WB_RCC_AHB1ENR; - rcc_dma_mask = STM32WB_RCC_DMAEN; - break; - default: - return; - } - - if (!stlink_read_debug32(sl, rcc, &value)) { - if (bckpRstr) { - value = (value & (~rcc_dma_mask)) | fl->rcc_dma_bkp; - } else { - fl->rcc_dma_bkp = value & rcc_dma_mask; - value &= ~rcc_dma_mask; - } - stlink_write_debug32(sl, rcc, value); - } -} - -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - // disable DMA - set_dma_state(sl, fl, 0); - - // wait for ongoing op to finish - wait_flash_busy(sl); - // Clear errors - clear_flash_error(sl); - - if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4)) { - ILOG("Starting Flash write for F2/F4/F7/L4\n"); - - // Flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return (-1); - } - - unlock_flash_if(sl); // first unlock the cr - - int voltage; - if (sl->version.stlink_v == 1) { - WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); - voltage = 3200; - } else { - voltage = stlink_target_voltage(sl); - } - - if (voltage == -1) { - ELOG("Failed to read Target voltage\n"); - return (-1); - } - - if (sl->flash_type == STM32_FLASH_TYPE_L4) { - // L4 does not have a byte-write mode - if (voltage < 1710) { - ELOG("Target voltage (%d mV) too low for flash writes!\n", voltage); - return (-1); - } - } else { - if (voltage > 2700) { - ILOG("enabling 32-bit flash writes\n"); - write_flash_cr_psiz(sl, 2, BANK_1); - } else { - ILOG("Target voltage (%d mV) too low for 32-bit flash, " - "using 8-bit flash writes\n", - voltage); - write_flash_cr_psiz(sl, 0, BANK_1); - } - } - - // set programming mode - set_flash_cr_pg(sl, BANK_1); - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - ILOG("Starting Flash write for WB/G0/G4/L5/U5\n"); - - unlock_flash_if(sl); // unlock flash if necessary - set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - ILOG("Starting Flash write for L0\n"); - - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY2); - - // check pecr.pelock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 0)) { - ELOG("pecr.pelock not clear\n"); - return (-1); - } - - // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY2); - - // check pecr.prglock is cleared - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - if (val & (1 << 1)) { - ELOG("pecr.prglock not clear\n"); - return (-1); - } - - /* Flash loader initialisation */ - if (stlink_flash_loader_init(sl, fl) == -1) { - // L0/L1 have fallback to soft write - WLOG("stlink_flash_loader_init() == -1\n"); - } - } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - ILOG("Starting Flash write for VL/F0/F3/F1_XL\n"); - - // flash loader initialisation - if (stlink_flash_loader_init(sl, fl) == -1) { - ELOG("stlink_flash_loader_init() == -1\n"); - return (-1); - } - - // unlock flash - unlock_flash_if(sl); - - // set programming mode - set_flash_cr_pg(sl, BANK_1); - if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - set_flash_cr_pg(sl, BANK_2); - } - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - ILOG("Starting Flash write for H7\n"); - - unlock_flash_if(sl); // unlock the cr - set_flash_cr_pg(sl, BANK_1); // set programming mode - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - set_flash_cr_pg(sl, BANK_2); - } - if (sl->chip_id != STM32_CHIPID_H7Ax) { - // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); - } - } - } else { - ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); - return (-1); - } - - return (0); -} - -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, - stm32_addr_t addr, uint8_t *base, uint32_t len) { - size_t off; - if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4)) { - size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; - for (off = 0; off < len;) { - size_t size = len - off > buf_size ? buf_size : len - off; - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); - check_flash_error(sl); - return (-1); - } - - off += size; - } - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - for (off = 0; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz + 1), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } - - write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - fprintf(stdout, "\n"); - - // flash writes happen as 2 words at a time - if ((off / sizeof(uint32_t)) % 2 != 0) { - stlink_write_debug32(sl, addr + (uint32_t)off, - 0); // write a single word of zeros - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear - } - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? - L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; - - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); - - off = 0; - - if (len > pagesize) { - if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { - return (-1); - } else { - off = (size_t)(len / pagesize) * pagesize; - } - } - - // write remaining word in program memory - for (; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz + 1), - (unsigned int)(len / sl->flash_pgsz)); - fflush(stdout); - } - - write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); - - // wait for sr.busy to be cleared - do { - stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); - } while ((val & (1 << 0)) != 0); - - // TODO: check redo write operation - } - fprintf(stdout, "\n"); - } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - int write_block_count = 0; - for (off = 0; off < len; off += sl->flash_pgsz) { - // adjust last write size - size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; - - // unlock and set programming mode - unlock_flash_if(sl); - - DLOG("Finished unlocking flash, running loader!\n"); - - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); - check_flash_error(sl); - return (-1); - } - - lock_flash(sl); - - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading - fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, - (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } - } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - for (off = 0; off < len;) { - // Program STM32H7x with 64-byte Flash words - size_t chunk = (len - off > 64) ? 64 : len - off; - memcpy(sl->q_buf, base + off, chunk); - stlink_write_mem32(sl, addr + (uint32_t)off, 64); - wait_flash_busy(sl); - - off += chunk; - - if (sl->verbose >= 1) { - // show progress - fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, - (unsigned int)len); - fflush(stdout); - } - } - if (sl->verbose >= 1) { - fprintf(stdout, "\n"); - } - } else { - return (-1); - } - - return check_flash_error(sl); -} - -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { - uint32_t dhcsr; - - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || - (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_G0) || - (sl->flash_type == STM32_FLASH_TYPE_G4) || - (sl->flash_type == STM32_FLASH_TYPE_H7) || - (sl->flash_type == STM32_FLASH_TYPE_L4) || - (sl->flash_type == STM32_FLASH_TYPE_L5_U5) || - (sl->flash_type == STM32_FLASH_TYPE_WB_WL)) { - - clear_flash_cr_pg(sl, BANK_1); - if ((sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || - sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - clear_flash_cr_pg(sl, BANK_2); - } - lock_flash(sl); - } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - uint32_t val; - uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - - // reset lock bits - stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); - val |= (1 << 0) | (1 << 1) | (1 << 2); - stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); - } - - // enable interrupt - if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); - } - - // restore DMA state - set_dma_state(sl, fl, 1); - - return (0); -} diff --git a/src/stlink-lib/flashloader.h b/src/stlink-lib/flashloader.h deleted file mode 100644 index ff16d183c..000000000 --- a/src/stlink-lib/flashloader.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * File: flashloader.h - * - * Flash loader - */ - -#include -#include - -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); - From ab286988b4135067b7c45d40f8e15e6b2f69d7a0 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 Apr 2023 18:52:14 +0200 Subject: [PATCH 1368/1435] Corrected preprocessor header includes --- inc/backend.h | 6 +++--- inc/stlink.h | 6 +++--- inc/stm32.h | 6 +++--- inc/stm32flash.h | 6 +++--- inc/version.h.in | 6 +++--- src/st-flash/flash.h | 6 +++--- src/st-util/gdb-remote.h | 6 +++--- src/st-util/gdb-server.h | 6 +++--- src/st-util/semihosting.h | 6 +++--- src/stlink-gui/gui.h | 6 +++--- src/stlink-lib/calculate.h | 6 +++--- src/stlink-lib/chipid.h | 6 +++--- src/stlink-lib/commands.h | 6 +++--- src/stlink-lib/common.h | 6 +++--- src/stlink-lib/common_flash.h | 7 ++++--- src/stlink-lib/flash_loader.h | 6 +++--- src/stlink-lib/helper.h | 6 +++--- src/stlink-lib/libusb_settings.h | 6 +++--- src/stlink-lib/logging.h | 6 +++--- src/stlink-lib/map_file.h | 6 +++--- src/stlink-lib/md5.h | 11 +++++++++++ src/stlink-lib/option_bytes.h | 5 +++++ src/stlink-lib/reg.h | 6 +++--- src/stlink-lib/sg.h | 6 +++--- src/stlink-lib/usb.h | 6 +++--- src/win32/getopt/getopt.h | 6 +++--- src/win32/mmap.h | 8 ++++---- src/win32/sys_time.h | 10 ++++++---- src/win32/unistd/unistd.h | 6 +++--- 29 files changed, 102 insertions(+), 83 deletions(-) diff --git a/inc/backend.h b/inc/backend.h index a45dccd82..abbf4bbf0 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -1,5 +1,5 @@ -#ifndef STLINK_BACKEND_H_ -#define STLINK_BACKEND_H_ +#ifndef BACKEND_H_ +#define BACKEND_H_ typedef struct _stlink_backend { void (*close) (stlink_t * sl); @@ -34,4 +34,4 @@ int (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); } stlink_backend_t; -#endif // STLINK_BACKEND_H_ +#endif // BACKEND_H_ diff --git a/inc/stlink.h b/inc/stlink.h index b9379e03d..2a192876f 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -6,8 +6,8 @@ * regardless of how the backend does the work.... */ -#ifndef STLINK_H -#define STLINK_H +#ifndef STLINK_H_ +#define STLINK_H_ #include #include @@ -311,4 +311,4 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect); } #endif -#endif // STLINK_H +#endif // STLINK_H_ diff --git a/inc/stm32.h b/inc/stm32.h index d3c4e5512..abc7f1ded 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -4,8 +4,8 @@ * STM32-specific defines & identification parametres */ -#ifndef STM32_H -#define STM32_H +#ifndef STM32_H_ +#define STM32_H_ /* STM32 Cortex-M core ids (CPUTAPID) */ enum stm32_core_id { @@ -217,4 +217,4 @@ enum stm32_chipids { #define STM32L5_PWR_CR1 0x40007000 // RM0438, p. 93,324 #define STM32L5_PWR_CR1_VOS 9 -#endif // STM32_H +#endif // STM32_H_ diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 07f824837..f5f662cb6 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -1,5 +1,5 @@ -#ifndef STM32FLASH_H -#define STM32FLASH_H +#ifndef STM32FLASH_H_ +#define STM32FLASH_H_ /* stm32f FPEC flash controller interface, pm0063 manual */ // STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) @@ -378,4 +378,4 @@ #define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) #define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) -#endif // STM32FLASH_H +#endif // STM32FLASH_H_ diff --git a/inc/version.h.in b/inc/version.h.in index 66159e0e5..b5ccd6e31 100644 --- a/inc/version.h.in +++ b/inc/version.h.in @@ -1,9 +1,9 @@ -#ifndef STLINK_VERSION_H_ -#define STLINK_VERSION_H_ +#ifndef VERSION_H_ +#define VERSION_H_ #define STLINK_VERSION "@PROJECT_VERSION@" #define STLINK_VERSION_MAJOR @PROJECT_VERSION_MAJOR@ #define STLINK_VERSION_MINOR @PROJECT_VERSION_MINOR@ #define STLINK_VERSION_PATCH @PROJECT_VERSION_PATCH@ -#endif // STLINK_VERSION_H_ +#endif // VERSION_H_ diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index f3d431d65..aab57878f 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -1,5 +1,5 @@ -#ifndef STLINK_TOOLS_FLASH_H_ -#define STLINK_TOOLS_FLASH_H_ +#ifndef FLASH_H_ +#define FLASH_H_ #include @@ -33,4 +33,4 @@ struct flash_opts { int flash_get_opts(struct flash_opts* o, int ac, char** av); -#endif // STLINK_FLASH_H_ +#endif // FLASH_H_ diff --git a/src/st-util/gdb-remote.h b/src/st-util/gdb-remote.h index 6e76746b7..bcf1dbd01 100644 --- a/src/st-util/gdb-remote.h +++ b/src/st-util/gdb-remote.h @@ -1,8 +1,8 @@ -#ifndef _GDB_REMOTE_H_ -#define _GDB_REMOTE_H_ +#ifndef GDB_REMOTE_H_ +#define GDB_REMOTE_H_ int gdb_send_packet(int fd, char* data); int gdb_recv_packet(int fd, char** buffer); int gdb_check_for_interrupt(int fd); -#endif // _GDB_REMOTE_H_ +#endif // GDB_REMOTE_H_ diff --git a/src/st-util/gdb-server.h b/src/st-util/gdb-server.h index b50a7941d..3fbb16dad 100644 --- a/src/st-util/gdb-server.h +++ b/src/st-util/gdb-server.h @@ -1,5 +1,5 @@ -#ifndef _GDB_SERVER_H -#define _GDB_SERVER_H +#ifndef GDB_SERVER_H_ +#define GDB_SERVER_H_ #define STRINGIFY_inner(name) #name #define STRINGIFY(name) STRINGIFY_inner(name) @@ -8,4 +8,4 @@ #define DEBUG_LOGGING_LEVEL 100 #define DEFAULT_GDB_LISTEN_PORT 4242 -#endif // _GDB_SERVER_H +#endif // GDB_SERVER_H_ diff --git a/src/st-util/semihosting.h b/src/st-util/semihosting.h index 8c1ac15f0..2e34b4307 100644 --- a/src/st-util/semihosting.h +++ b/src/st-util/semihosting.h @@ -1,5 +1,5 @@ -#ifndef _SEMIHOSTING_H_ -#define _SEMIHOSTING_H_ +#ifndef SEMIHOSTING_H_ +#define SEMIHOSTING_H_ #include @@ -31,4 +31,4 @@ int do_semihosting(stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret); -#endif // _SEMIHOSTING_H_ +#endif // SEMIHOSTING_H_ diff --git a/src/stlink-gui/gui.h b/src/stlink-gui/gui.h index b3d5dfff8..f29ee5031 100644 --- a/src/stlink-gui/gui.h +++ b/src/stlink-gui/gui.h @@ -1,5 +1,5 @@ -#ifndef __STLINK_GUI_H__ -#define __STLINK_GUI_H__ +#ifndef GUI_H_ +#define GUI_H_ #include @@ -89,4 +89,4 @@ struct _STlinkGUIClass { GType stlink_gui_get_type(void); int export_to_file(const char*filename, const struct mem_t flash_mem); -#endif // __STLINK_GUI_H__ +#endif // GUI_H_ diff --git a/src/stlink-lib/calculate.h b/src/stlink-lib/calculate.h index 64dfb51b2..beb064297 100644 --- a/src/stlink-lib/calculate.h +++ b/src/stlink-lib/calculate.h @@ -4,12 +4,12 @@ * Calculation of sector numbers and pages */ -#ifndef CALCULATE_H -#define CALCULATE_H +#ifndef CALCULATE_H_ +#define CALCULATE_H_ uint32_t calculate_F4_sectornum(uint32_t); uint32_t calculate_F7_sectornum(uint32_t); uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, unsigned); uint32_t calculate_L4_page(stlink_t *, uint32_t); -#endif // CALCULATE_H +#endif // CALCULATE_H_ diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 1eae2cc34..b93a3f2d6 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -1,5 +1,5 @@ -#ifndef STLINK_CHIPID_H_ -#define STLINK_CHIPID_H_ +#ifndef CHIPID_H_ +#define CHIPID_H_ #include #include @@ -24,4 +24,4 @@ struct stlink_chipid_params { struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); void init_chipids(char *dir_to_scan); -#endif // STLINK_CHIPID_H_ +#endif // CHIPID_H_ diff --git a/src/stlink-lib/commands.h b/src/stlink-lib/commands.h index 136adf80e..4fa919858 100644 --- a/src/stlink-lib/commands.h +++ b/src/stlink-lib/commands.h @@ -1,5 +1,5 @@ -#ifndef STLINK_COMMANDS_H_ -#define STLINK_COMMANDS_H_ +#ifndef COMMANDS_H_ +#define COMMANDS_H_ enum stlink_commands { STLINK_GET_VERSION = 0xF1, @@ -54,4 +54,4 @@ enum stlink_dfu_commands { STLINK_DFU_EXIT = 0x07 }; -#endif // STLINK_COMMANDS_H_ +#endif // COMMANDS_H_ diff --git a/src/stlink-lib/common.h b/src/stlink-lib/common.h index dd6cf95b2..902493610 100644 --- a/src/stlink-lib/common.h +++ b/src/stlink-lib/common.h @@ -4,12 +4,12 @@ * General helper functions */ -#ifndef COMMON_H -#define COMMON_H +#ifndef COMMON_H_ +#define COMMON_H_ int check_file(stlink_t *, mapped_file_t *, stm32_addr_t); void md5_calculate(mapped_file_t *); void stlink_checksum(mapped_file_t *); void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); -#endif // COMMON_H +#endif // COMMON_H_ diff --git a/src/stlink-lib/common_flash.h b/src/stlink-lib/common_flash.h index 3b6b0404a..269f8196e 100644 --- a/src/stlink-lib/common_flash.h +++ b/src/stlink-lib/common_flash.h @@ -4,8 +4,8 @@ * Flash operations */ -#ifndef COMMON_FLASH_H -#define COMMON_FLASH_H +#ifndef COMMON_FLASH_H_ +#define COMMON_FLASH_H_ void lock_flash(stlink_t *); void clear_flash_error(stlink_t *); @@ -24,4 +24,5 @@ void clear_flash_cr_pg(stlink_t *, unsigned); uint32_t read_flash_cr(stlink_t *, unsigned); uint32_t get_stm32l0_flash_base(stlink_t *); -#endif // STLINK_H + +#endif // COMMON_FLASH_H_ diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 0d39a9a48..781fab74a 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -4,8 +4,8 @@ * Flash loader */ -#ifndef STLINK_FLASH_LOADER_H_ -#define STLINK_FLASH_LOADER_H_ +#ifndef FLASH_LOADER_H_ +#define FLASH_LOADER_H_ #include #include @@ -21,4 +21,4 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); -#endif // STLINK_FLASH_LOADER_H_ +#endif // FLASH_LOADER_H_ diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index 96467377a..58023aff2 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -1,8 +1,8 @@ -#ifndef SYS_HELPER_H -#define SYS_HELPER_H +#ifndef HELPER_H_ +#define HELPER_H_ unsigned time_ms(); int arg_parse_freq(const char *str); -#endif /* SYS_HELPER_H */ +#endif // HELPER_H_ diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index 3777f720b..639f9e4a4 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -1,5 +1,5 @@ -#ifndef LIBUSB_SETTINGS_H -#define LIBUSB_SETTINGS_H +#ifndef LIBUSB_SETTINGS_H_ +#define LIBUSB_SETTINGS_H_ #include @@ -44,4 +44,4 @@ #error unsupported libusb version #endif -#endif // LIBUSB_SETTINGS_H +#endif // LIBUSB_SETTINGS_H_ diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index 7f3994492..7510d573e 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -2,8 +2,8 @@ * Ugly, low performance, configurable level, logging "framework" */ -#ifndef UGLYLOGGING_H -#define UGLYLOGGING_H +#ifndef LOGGING_H_ +#define LOGGING_H_ #ifdef __cplusplus extern "C" { @@ -45,4 +45,4 @@ int ugly_libusb_log_level(enum ugly_loglevel v); } #endif -#endif // UGLYLOGGING_H +#endif // LOGGING_H_ diff --git a/src/stlink-lib/map_file.h b/src/stlink-lib/map_file.h index f50a201f0..d69f6c3b5 100644 --- a/src/stlink-lib/map_file.h +++ b/src/stlink-lib/map_file.h @@ -4,8 +4,8 @@ * File mapping */ -#ifndef MAP_FILE_H -#define MAP_FILE_H +#ifndef MAP_FILE_H_ +#define MAP_FILE_H_ #ifndef O_BINARY #define O_BINARY 0 @@ -29,4 +29,4 @@ typedef struct mapped_file { int map_file(mapped_file_t *, const char *); void unmap_file(mapped_file_t *); -#endif // MAP_FILE_H +#endif // MAP_FILE_H_ diff --git a/src/stlink-lib/md5.h b/src/stlink-lib/md5.h index a69d7fc6b..7b853a4f6 100644 --- a/src/stlink-lib/md5.h +++ b/src/stlink-lib/md5.h @@ -5,6 +5,15 @@ * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org */ +/* + * File: md5.h + * + * MD5 hash function + */ + +#ifndef MD5_H_ +#define MD5_H_ + #pragma once #include @@ -61,3 +70,5 @@ void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */ * Calculates the MD5 hash of the buffer. */ void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */); + +#endif // MD5_H_ \ No newline at end of file diff --git a/src/stlink-lib/option_bytes.h b/src/stlink-lib/option_bytes.h index b9f88c508..481a69f0a 100644 --- a/src/stlink-lib/option_bytes.h +++ b/src/stlink-lib/option_bytes.h @@ -4,6 +4,9 @@ * Read and write option bytes and option control registers */ +#ifndef OPTION_BYTES_H_ +#define OPTION_BYTES_H_ + #include #include @@ -19,3 +22,5 @@ int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1); int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); + +#endif // OPTION_BYTES_H_ \ No newline at end of file diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index b581a269c..2046f8a6a 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -1,5 +1,5 @@ -#ifndef STLINK_REG_H_ -#define STLINK_REG_H_ +#ifndef REG_H_ +#define REG_H_ #define STLINK_REG_CM3_CPUID 0xE000ED00 @@ -123,4 +123,4 @@ #define STLINK_REG_CM7_ICIALLU 0xE000EF50 #define STLINK_REG_CM7_CCSIDR 0xE000ED80 -#endif // STLINK_REG_H_ +#endif // REG_H_ diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index 212d03b27..e30043fcc 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -3,8 +3,8 @@ * Author: karl */ -#ifndef STLINK_SG_H -#define STLINK_SG_H +#ifndef SG_H_ +#define SG_H_ #include #include @@ -56,4 +56,4 @@ struct stlink_libsg { stlink_t* stlink_v1_open(const int verbose, int reset); -#endif // STLINK_SG_H +#endif // SG_H_ diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 3f4b71e51..ff6f9088e 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -3,8 +3,8 @@ * Author: karl */ -#ifndef STLINK_USB_H -#define STLINK_USB_H +#ifndef USB_H_ +#define USB_H_ #include @@ -70,4 +70,4 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); -#endif // STLINK_USB_H +#endif // USB_H_ diff --git a/src/win32/getopt/getopt.h b/src/win32/getopt/getopt.h index 3aaf73bed..2a1bd735b 100644 --- a/src/win32/getopt/getopt.h +++ b/src/win32/getopt/getopt.h @@ -1,5 +1,5 @@ -#ifndef INCLUDED_GETOPT_PORT_H -#define INCLUDED_GETOPT_PORT_H +#ifndef GETOPT_H_ +#define GETOPT_H_ #if defined(__cplusplus) extern "C" { @@ -38,4 +38,4 @@ int getopt_long(int argc, } #endif -#endif // INCLUDED_GETOPT_PORT_H +#endif // GETOPT_H_ diff --git a/src/win32/mmap.h b/src/win32/mmap.h index 06079a9bc..ff01f4286 100644 --- a/src/win32/mmap.h +++ b/src/win32/mmap.h @@ -1,5 +1,5 @@ -#ifndef STLINK_MMAP_H -#define STLINK_MMAP_H +#ifndef MMAP_H_ +#define MMAP_H_ #ifdef STLINK_HAVE_SYS_MMAN_H #include @@ -16,6 +16,6 @@ void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); int munmap(void *addr, size_t len); -#endif /* HAVE_SYS_MMAN_H */ +#endif // STLINK_HAVE_SYS_MMAN_H -#endif /* STLINK_MMAP_H */ +#endif // MMAP_H_ diff --git a/src/win32/sys_time.h b/src/win32/sys_time.h index d314509b7..cb767fc31 100644 --- a/src/win32/sys_time.h +++ b/src/win32/sys_time.h @@ -1,8 +1,10 @@ -#ifndef STLINK_TIME_H -#define STLINK_TIME_H +#ifndef SYS_TIME_H_ +#define SYS_TIME_H_ #ifdef STLINK_HAVE_SYS_TIME_H + #include + #else #include @@ -14,6 +16,6 @@ struct timezone { int gettimeofday(struct timeval *tv, struct timezone *tz); -#endif /* STLINK_HAVE_SYS_TIME_H */ +#endif // STLINK_HAVE_SYS_TIME_H -#endif /* STLINK_TIME_H */ +#endif // SYS_TIME_H_ diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index 389c44664..b8a3db746 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -1,5 +1,5 @@ -#ifndef _UNISTD_H -#define _UNISTD_H 1 +#ifndef UNISTD_H_ +#define UNISTD_H_ /* * This file intended to serve as a drop-in replacement for unistd.h on Windows @@ -72,4 +72,4 @@ typedef unsigned __int64 uint64_t; int usleep(unsigned int waitTime); #endif -#endif // _UNISTD_H +#endif // UNISTD_H_ From 7c2c953ff6051c2adfdd5aa8f312bc98f9cb627c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 Apr 2023 19:21:17 +0200 Subject: [PATCH 1369/1435] Unified chipid enum naming for L0 series --- config/chips/L0xxx_Cat_1.chip | 2 +- config/chips/L0xxx_Cat_3.chip | 2 +- inc/stm32.h | 4 ++-- src/stlink-lib/common_flash.c | 6 +++--- src/stlink-lib/flash_loader.c | 8 ++++---- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/config/chips/L0xxx_Cat_1.chip b/config/chips/L0xxx_Cat_1.chip index 2cce4e23c..2c6bea0eb 100644 --- a/config/chips/L0xxx_Cat_1.chip +++ b/config/chips/L0xxx_Cat_1.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_1 ref_manual_id 0451 // also RM0377 -chip_id 0x457 // STM32_CHIPID_L011 +chip_id 0x457 // STM32_CHIPID_L0_CAT1 flash_type L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/config/chips/L0xxx_Cat_3.chip b/config/chips/L0xxx_Cat_3.chip index a04dc8376..e6ad3586a 100644 --- a/config/chips/L0xxx_Cat_3.chip +++ b/config/chips/L0xxx_Cat_3.chip @@ -2,7 +2,7 @@ # dev_type STM32L0xxx_Cat_3 ref_manual_id 0451 // also RM0367 & RM0377 -chip_id 0x417 // STM32_CHIPID_L0 +chip_id 0x417 // STM32_CHIPID_L0_CAT3 flash_type L0_L1 flash_size_reg 0x1ff8007c flash_pagesize 0x80 // 128 B diff --git a/inc/stm32.h b/inc/stm32.h index abc7f1ded..ab80ff25e 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -76,7 +76,7 @@ enum stm32_chipids { STM32_CHIPID_F1_HD = 0x414, /* high density */ STM32_CHIPID_L4 = 0x415, STM32_CHIPID_L1_MD = 0x416, /* medium density */ - STM32_CHIPID_L0 = 0x417, + STM32_CHIPID_L0_CAT3 = 0x417, STM32_CHIPID_F1_CONN = 0x418, /* connectivity line */ STM32_CHIPID_F4_HD = 0x419, /* high density */ STM32_CHIPID_F1_VL_MD_LD = 0x420, /* value line medium & low density */ @@ -110,7 +110,7 @@ enum stm32_chipids { STM32_CHIPID_F76xxx = 0x451, STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ - STM32_CHIPID_L011 = 0x457, + STM32_CHIPID_L0_CAT1 = 0x457, STM32_CHIPID_F410 = 0x458, STM32_CHIPID_G0_CAT2 = 0x460, /* G07x/G08x */ STM32_CHIPID_L496x_L4A6x = 0x461, diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 740c93690..dbae1c694 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -12,10 +12,10 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { switch (sl->chip_id) { - case STM32_CHIPID_L0: - case STM32_CHIPID_L0_CAT5: + case STM32_CHIPID_L0_CAT1: case STM32_CHIPID_L0_CAT2: - case STM32_CHIPID_L011: + case STM32_CHIPID_L0_CAT3: + case STM32_CHIPID_L0_CAT5: return (STM32L0_FLASH_REGS_ADDR); case STM32_CHIPID_L1_CAT2: diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 852ba6c20..c46392cbe 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -238,10 +238,10 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STM32_CHIPID_L1_MD_PLUS || sl->chip_id == STM32_CHIPID_L1_MD_PLUS_HD || sl->chip_id == STM32_CHIPID_L152_RE || - sl->chip_id == STM32_CHIPID_L011 || - sl->chip_id == STM32_CHIPID_L0 || - sl->chip_id == STM32_CHIPID_L0_CAT5 || - sl->chip_id == STM32_CHIPID_L0_CAT2) { + sl->chip_id == STM32_CHIPID_L0_CAT1 || + sl->chip_id == STM32_CHIPID_L0_CAT2 || + sl->chip_id == STM32_CHIPID_L0_CAT3 || + sl->chip_id == STM32_CHIPID_L0_CAT5) { loader_code = loader_code_stm32lx; loader_size = sizeof(loader_code_stm32lx); } else if (sl->core_id == STM32_CORE_ID_M3_r1p1_SWD || From 823187216afbaccfcfe07da4c3c5739b65820239 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 Apr 2023 20:46:37 +0200 Subject: [PATCH 1370/1435] st-flash: auto-reset after mass erase --- flashloaders/Makefile | 4 ++-- flashloaders/linker.ld | 4 ++-- src/st-flash/flash.c | 6 ++++++ src/stlink-lib/flash_loader.c | 2 +- 4 files changed, 11 insertions(+), 5 deletions(-) diff --git a/flashloaders/Makefile b/flashloaders/Makefile index 8b01d5293..68ce5a881 100644 --- a/flashloaders/Makefile +++ b/flashloaders/Makefile @@ -1,5 +1,5 @@ -# The flash loader code cannot be compiled by the system gcc. This -# makefile use arm-none-eabi-gcc for this purpose +# The flash loader code cannot be compiled by the system gcc. +# This makefile uses arm-none-eabi-gcc for this purpose. CROSS_COMPILE ?= arm-none-eabi- diff --git a/flashloaders/linker.ld b/flashloaders/linker.ld index 7267fe10f..2d8c192ce 100644 --- a/flashloaders/linker.ld +++ b/flashloaders/linker.ld @@ -1,9 +1,9 @@ /* Entry Point */ -ENTRY( copy ) +ENTRY(copy) /* Specify the memory areas */ MEMORY { - RAM ( xrw) : ORIGIN = 0x20000000 , LENGTH = 64K + RAM (xrw) : ORIGIN = 0x20000000 , LENGTH = 64K } diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index d7d17f66f..bbb52d80c 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -188,6 +188,12 @@ int main(int ac, char** av) { goto on_error; } printf("Mass erase completed successfully.\n"); + + // reset after erase + if (stlink_reset(sl, RESET_AUTO)) { + printf("Failed to reset device\n"); + goto on_error; + } } else if (o.cmd == CMD_RESET) { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index c46392cbe..ebdf0a44e 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -391,7 +391,7 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe * firmware size. */ if ((int32_t)rr.r[2] > 0 || (int32_t)rr.r[2] < -7) { - ELOG("Write error\n"); + ELOG("Flash loader write error\n"); goto error; } From 800c8616fbc8115716258b2140b667a643beadc8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 30 Apr 2023 22:32:59 +0200 Subject: [PATCH 1371/1435] Unified #define names for STM32 devices --- inc/stm32flash.h | 320 +++++++++++++++++----------------- src/stlink-lib/calculate.c | 4 +- src/stlink-lib/common.c | 8 +- src/stlink-lib/common_flash.c | 278 ++++++++++++++--------------- src/stlink-lib/flash_loader.c | 16 +- src/stlink-lib/option_bytes.c | 58 +++--- 6 files changed, 342 insertions(+), 342 deletions(-) diff --git a/inc/stm32flash.h b/inc/stm32flash.h index f5f662cb6..ccbc0289d 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -59,206 +59,206 @@ #define FLASH_CR_OPTWRE 9 #define FLASH_CR_OBL_LAUNCH 13 -#define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) -#define STM32L_FLASH_ACR (STM32L_FLASH_REGS_ADDR + 0x00) -#define STM32L_FLASH_PECR (STM32L_FLASH_REGS_ADDR + 0x04) -#define STM32L_FLASH_PDKEYR (STM32L_FLASH_REGS_ADDR + 0x08) -#define STM32L_FLASH_PEKEYR (STM32L_FLASH_REGS_ADDR + 0x0c) -#define STM32L_FLASH_PRGKEYR (STM32L_FLASH_REGS_ADDR + 0x10) -#define STM32L_FLASH_OPTKEYR (STM32L_FLASH_REGS_ADDR + 0x14) -#define STM32L_FLASH_SR (STM32L_FLASH_REGS_ADDR + 0x18) -#define STM32L_FLASH_OBR (STM32L_FLASH_REGS_ADDR + 0x1c) -#define STM32L_FLASH_WRPR (STM32L_FLASH_REGS_ADDR + 0x20) +#define FLASH_Lx_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_Lx_ACR (FLASH_Lx_REGS_ADDR + 0x00) +#define FLASH_Lx_PECR (FLASH_Lx_REGS_ADDR + 0x04) +#define FLASH_Lx_PDKEYR (FLASH_Lx_REGS_ADDR + 0x08) +#define FLASH_Lx_PEKEYR (FLASH_Lx_REGS_ADDR + 0x0c) +#define FLASH_Lx_PRGKEYR (FLASH_Lx_REGS_ADDR + 0x10) +#define FLASH_Lx_OPTKEYR (FLASH_Lx_REGS_ADDR + 0x14) +#define FLASH_Lx_SR (FLASH_Lx_REGS_ADDR + 0x18) +#define FLASH_Lx_OBR (FLASH_Lx_REGS_ADDR + 0x1c) +#define FLASH_Lx_WRPR (FLASH_Lx_REGS_ADDR + 0x20) #define FLASH_L1_FPRG 10 #define FLASH_L1_PROG 3 // Flash registers common to STM32G0 and STM32G4 series (RM0440, p. 146) -#define STM32Gx_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32Gx_FLASH_ACR (STM32Gx_FLASH_REGS_ADDR + 0x00) -#define STM32Gx_FLASH_KEYR (STM32Gx_FLASH_REGS_ADDR + 0x08) -#define STM32Gx_FLASH_OPTKEYR (STM32Gx_FLASH_REGS_ADDR + 0x0c) -#define STM32Gx_FLASH_SR (STM32Gx_FLASH_REGS_ADDR + 0x10) -#define STM32Gx_FLASH_CR (STM32Gx_FLASH_REGS_ADDR + 0x14) -#define STM32Gx_FLASH_ECCR (STM32Gx_FLASH_REGS_ADDR + 0x18) -#define STM32Gx_FLASH_OPTR (STM32Gx_FLASH_REGS_ADDR + 0x20) +#define FLASH_Gx_REGS_ADDR ((uint32_t)0x40022000) +#define FLASH_Gx_ACR (FLASH_Gx_REGS_ADDR + 0x00) +#define FLASH_Gx_KEYR (FLASH_Gx_REGS_ADDR + 0x08) +#define FLASH_Gx_OPTKEYR (FLASH_Gx_REGS_ADDR + 0x0c) +#define FLASH_Gx_SR (FLASH_Gx_REGS_ADDR + 0x10) +#define FLASH_Gx_CR (FLASH_Gx_REGS_ADDR + 0x14) +#define FLASH_Gx_ECCR (FLASH_Gx_REGS_ADDR + 0x18) +#define FLASH_Gx_OPTR (FLASH_Gx_REGS_ADDR + 0x20) // G0 (RM0444 Table 1, sec 3.7) // Mostly the same as G4 chips, but the notation // varies a bit after the 'OPTR' register. -#define STM32G0_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G0_FLASH_PCROP1ASR (STM32G0_FLASH_REGS_ADDR + 0x24) -#define STM32G0_FLASH_PCROP1AER (STM32G0_FLASH_REGS_ADDR + 0x28) -#define STM32G0_FLASH_WRP1AR (STM32G0_FLASH_REGS_ADDR + 0x2C) -#define STM32G0_FLASH_WRP1BR (STM32G0_FLASH_REGS_ADDR + 0x30) -#define STM32G0_FLASH_PCROP1BSR (STM32G0_FLASH_REGS_ADDR + 0x34) -#define STM32G0_FLASH_PCROP1BER (STM32G0_FLASH_REGS_ADDR + 0x38) -#define STM32G0_FLASH_SECR (STM32G0_FLASH_REGS_ADDR + 0x80) +#define FLASH_G0_REGS_ADDR (FLASH_Gx_REGS_ADDR) +#define FLASH_G0_PCROP1ASR (FLASH_G0_REGS_ADDR + 0x24) +#define FLASH_G0_PCROP1AER (FLASH_G0_REGS_ADDR + 0x28) +#define FLASH_G0_WRP1AR (FLASH_G0_REGS_ADDR + 0x2C) +#define FLASH_G0_WRP1BR (FLASH_G0_REGS_ADDR + 0x30) +#define FLASH_G0_PCROP1BSR (FLASH_G0_REGS_ADDR + 0x34) +#define FLASH_G0_PCROP1BER (FLASH_G0_REGS_ADDR + 0x38) +#define FLASH_G0_SECR (FLASH_G0_REGS_ADDR + 0x80) // G4 (RM0440 Table 17, sec 3.7.19) // Mostly the same as STM32G0 chips, but there are a few extra // registers because 'cat 3' devices can have two Flash banks. -#define STM32G4_FLASH_REGS_ADDR (STM32Gx_FLASH_REGS_ADDR) -#define STM32G4_FLASH_PDKEYR (STM32G4_FLASH_REGS_ADDR + 0x04) -#define STM32G4_FLASH_PCROP1SR (STM32G4_FLASH_REGS_ADDR + 0x24) -#define STM32G4_FLASH_PCROP1ER (STM32G4_FLASH_REGS_ADDR + 0x28) -#define STM32G4_FLASH_WRP1AR (STM32G4_FLASH_REGS_ADDR + 0x2C) -#define STM32G4_FLASH_WRP1BR (STM32G4_FLASH_REGS_ADDR + 0x30) -#define STM32G4_FLASH_PCROP2SR (STM32G4_FLASH_REGS_ADDR + 0x44) -#define STM32G4_FLASH_PCROP2ER (STM32G4_FLASH_REGS_ADDR + 0x48) -#define STM32G4_FLASH_WRP2AR (STM32G4_FLASH_REGS_ADDR + 0x4C) -#define STM32G4_FLASH_WRP2BR (STM32G4_FLASH_REGS_ADDR + 0x50) -#define STM32G4_FLASH_SEC1R (STM32G4_FLASH_REGS_ADDR + 0x70) -#define STM32G4_FLASH_SEC2R (STM32G4_FLASH_REGS_ADDR + 0x74) +#define FLASH_G4_REGS_ADDR (FLASH_Gx_REGS_ADDR) +#define FLASH_G4_PDKEYR (FLASH_G4_REGS_ADDR + 0x04) +#define FLASH_G4_PCROP1SR (FLASH_G4_REGS_ADDR + 0x24) +#define FLASH_G4_PCROP1ER (FLASH_G4_REGS_ADDR + 0x28) +#define FLASH_G4_WRP1AR (FLASH_G4_REGS_ADDR + 0x2C) +#define FLASH_G4_WRP1BR (FLASH_G4_REGS_ADDR + 0x30) +#define FLASH_G4_PCROP2SR (FLASH_G4_REGS_ADDR + 0x44) +#define FLASH_G4_PCROP2ER (FLASH_G4_REGS_ADDR + 0x48) +#define FLASH_G4_WRP2AR (FLASH_G4_REGS_ADDR + 0x4C) +#define FLASH_G4_WRP2BR (FLASH_G4_REGS_ADDR + 0x50) +#define FLASH_G4_SEC1R (FLASH_G4_REGS_ADDR + 0x70) +#define FLASH_G4_SEC2R (FLASH_G4_REGS_ADDR + 0x74) // G0/G4 FLASH control register -#define STM32Gx_FLASH_CR_PG (0) /* Program */ -#define STM32Gx_FLASH_CR_PER (1) /* Page erase */ -#define STM32Gx_FLASH_CR_MER1 (2) /* Mass erase */ -#define STM32Gx_FLASH_CR_PNB (3) /* Page number */ -#define STM32G0_FLASH_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define STM32G4_FLASH_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define STM32Gx_FLASH_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define STM32Gx_FLASH_CR_STRT (16) /* Start */ -#define STM32Gx_FLASH_CR_OPTSTRT \ +#define FLASH_Gx_CR_PG (0) /* Program */ +#define FLASH_Gx_CR_PER (1) /* Page erase */ +#define FLASH_Gx_CR_MER1 (2) /* Mass erase */ +#define FLASH_Gx_CR_PNB (3) /* Page number */ +#define FLASH_G0_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ +#define FLASH_G4_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define FLASH_Gx_CR_MER2 (15) /* Mass erase (2nd bank)*/ +#define FLASH_Gx_CR_STRT (16) /* Start */ +#define FLASH_Gx_CR_OPTSTRT \ (17) /* Start of modification of option bytes */ -#define STM32Gx_FLASH_CR_FSTPG (18) /* Fast programming */ -#define STM32Gx_FLASH_CR_EOPIE (24) /* End of operation interrupt enable */ -#define STM32Gx_FLASH_CR_ERRIE (25) /* Error interrupt enable */ -#define STM32Gx_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32Gx_FLASH_CR_OPTLOCK (30) /* Options Lock */ -#define STM32Gx_FLASH_CR_LOCK (31) /* FLASH_CR Lock */ +#define FLASH_Gx_CR_FSTPG (18) /* Fast programming */ +#define FLASH_Gx_CR_EOPIE (24) /* End of operation interrupt enable */ +#define FLASH_Gx_CR_ERRIE (25) /* Error interrupt enable */ +#define FLASH_Gx_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define FLASH_Gx_CR_OPTLOCK (30) /* Options Lock */ +#define FLASH_Gx_CR_LOCK (31) /* FLASH_CR Lock */ // G0/G4 FLASH status register -#define STM32Gx_FLASH_SR_ERROR_MASK (0x3fa) -#define STM32Gx_FLASH_SR_PROGERR (3) -#define STM32Gx_FLASH_SR_WRPERR (4) -#define STM32Gx_FLASH_SR_PGAERR (5) -#define STM32Gx_FLASH_SR_BSY (16) /* FLASH_SR Busy */ -#define STM32Gx_FLASH_SR_EOP (0) /* FLASH_EOP End of Operation */ +#define FLASH_Gx_SR_ERROR_MASK (0x3fa) +#define FLASH_Gx_SR_PROGERR (3) +#define FLASH_Gx_SR_WRPERR (4) +#define FLASH_Gx_SR_PGAERR (5) +#define FLASH_Gx_SR_BSY (16) /* FLASH_SR Busy */ +#define FLASH_Gx_SR_EOP (0) /* FLASH_EOP End of Operation */ // G4 FLASH option register -#define STM32G4_FLASH_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ +#define FLASH_G4_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ // WB (RM0434) -#define STM32WB_FLASH_REGS_ADDR ((uint32_t)0x58004000) -#define STM32WB_FLASH_ACR (STM32WB_FLASH_REGS_ADDR + 0x00) -#define STM32WB_FLASH_KEYR (STM32WB_FLASH_REGS_ADDR + 0x08) -#define STM32WB_FLASH_OPT_KEYR (STM32WB_FLASH_REGS_ADDR + 0x0C) -#define STM32WB_FLASH_SR (STM32WB_FLASH_REGS_ADDR + 0x10) -#define STM32WB_FLASH_CR (STM32WB_FLASH_REGS_ADDR + 0x14) -#define STM32WB_FLASH_ECCR (STM32WB_FLASH_REGS_ADDR + 0x18) -#define STM32WB_FLASH_OPTR (STM32WB_FLASH_REGS_ADDR + 0x20) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASH_REGS_ADDR + 0x24) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASH_REGS_ADDR + 0x28) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASH_REGS_ADDR + 0x2C) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASH_REGS_ADDR + 0x30) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASH_REGS_ADDR + 0x34) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASH_REGS_ADDR + 0x38) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASH_REGS_ADDR + 0x3C) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASH_REGS_ADDR + 0x5C) -#define STM32WB_FLASH_C2SR (STM32WB_FLASH_REGS_ADDR + 0x60) -#define STM32WB_FLASH_C2CR (STM32WB_FLASH_REGS_ADDR + 0x64) -#define STM32WB_FLASH_SFR (STM32WB_FLASH_REGS_ADDR + 0x80) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASH_REGS_ADDR + 0x84) +#define FLASH_WB_REGS_ADDR ((uint32_t)0x58004000) +#define FLASH_WB_ACR (FLASH_WB_REGS_ADDR + 0x00) +#define FLASH_WB_KEYR (FLASH_WB_REGS_ADDR + 0x08) +#define FLASH_WB_OPT_KEYR (FLASH_WB_REGS_ADDR + 0x0C) +#define FLASH_WB_SR (FLASH_WB_REGS_ADDR + 0x10) +#define FLASH_WB_CR (FLASH_WB_REGS_ADDR + 0x14) +#define FLASH_WB_ECCR (FLASH_WB_REGS_ADDR + 0x18) +#define FLASH_WB_OPTR (FLASH_WB_REGS_ADDR + 0x20) +#define FLASH_WB_PCROP1ASR (FLASH_WB_REGS_ADDR + 0x24) +#define FLASH_WB_PCROP1AER (FLASH_WB_REGS_ADDR + 0x28) +#define FLASH_WB_WRP1AR (FLASH_WB_REGS_ADDR + 0x2C) +#define FLASH_WB_WRP1BR (FLASH_WB_REGS_ADDR + 0x30) +#define FLASH_WB_PCROP1BSR (FLASH_WB_REGS_ADDR + 0x34) +#define FLASH_WB_PCROP1BER (FLASH_WB_REGS_ADDR + 0x38) +#define FLASH_WB_IPCCBR (FLASH_WB_REGS_ADDR + 0x3C) +#define FLASH_WB_C2ACR (FLASH_WB_REGS_ADDR + 0x5C) +#define FLASH_WB_C2SR (FLASH_WB_REGS_ADDR + 0x60) +#define FLASH_WB_C2CR (FLASH_WB_REGS_ADDR + 0x64) +#define FLASH_WB_SFR (FLASH_WB_REGS_ADDR + 0x80) +#define FLASH_WB_SRRVR (FLASH_WB_REGS_ADDR + 0x84) // WB Flash control register. -#define STM32WB_FLASH_CR_STRT (16) /* Start */ -#define STM32WB_FLASH_CR_OPTSTRT (17) /* Start writing option bytes */ -#define STM32WB_FLASH_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define STM32WB_FLASH_CR_OPTLOCK (30) /* Option Lock */ -#define STM32WB_FLASH_CR_LOCK (31) /* Lock */ +#define FLASH_WB_CR_STRT (16) /* Start */ +#define FLASH_WB_CR_OPTSTRT (17) /* Start writing option bytes */ +#define FLASH_WB_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define FLASH_WB_CR_OPTLOCK (30) /* Option Lock */ +#define FLASH_WB_CR_LOCK (31) /* Lock */ // WB Flash status register. -#define STM32WB_FLASH_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define STM32WB_FLASH_SR_PROGERR (3) /* Programming alignment error */ -#define STM32WB_FLASH_SR_WRPERR (4) /* Write protection error */ -#define STM32WB_FLASH_SR_PGAERR (5) /* Programming error */ -#define STM32WB_FLASH_SR_BSY (16) /* Busy */ +#define FLASH_WB_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ +#define FLASH_WB_SR_PROGERR (3) /* Programming alignment error */ +#define FLASH_WB_SR_WRPERR (4) /* Write protection error */ +#define FLASH_WB_SR_PGAERR (5) /* Programming error */ +#define FLASH_WB_SR_BSY (16) /* Busy */ // 32L4 register base is at FLASH_REGS_ADDR (0x40022000) -#define STM32L4_FLASH_KEYR (FLASH_REGS_ADDR + 0x08) -#define STM32L4_FLASH_OPTKEYR (FLASH_REGS_ADDR + 0x0C) -#define STM32L4_FLASH_SR (FLASH_REGS_ADDR + 0x10) -#define STM32L4_FLASH_CR (FLASH_REGS_ADDR + 0x14) -#define STM32L4_FLASH_OPTR (FLASH_REGS_ADDR + 0x20) - -#define STM32L4_FLASH_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ -#define STM32L4_FLASH_SR_PROGERR 3 -#define STM32L4_FLASH_SR_WRPERR 4 -#define STM32L4_FLASH_SR_PGAERR 5 -#define STM32L4_FLASH_SR_BSY 16 - -#define STM32L4_FLASH_CR_LOCK 31 /* Lock control register */ -#define STM32L4_FLASH_CR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L4_FLASH_CR_PG 0 /* Program */ -#define STM32L4_FLASH_CR_PER 1 /* Page erase */ -#define STM32L4_FLASH_CR_MER1 2 /* Bank 1 erase */ -#define STM32L4_FLASH_CR_MER2 15 /* Bank 2 erase */ -#define STM32L4_FLASH_CR_STRT 16 /* Start command */ -#define STM32L4_FLASH_CR_OPTSTRT 17 /* Start writing option bytes */ -#define STM32L4_FLASH_CR_BKER 11 /* Bank select for page erase */ -#define STM32L4_FLASH_CR_PNB 3 /* Page number (8 bits) */ -#define STM32L4_FLASH_CR_OBL_LAUNCH 27 /* Option bytes reload */ +#define FLASH_L4_KEYR (FLASH_REGS_ADDR + 0x08) +#define FLASH_L4_OPTKEYR (FLASH_REGS_ADDR + 0x0C) +#define FLASH_L4_SR (FLASH_REGS_ADDR + 0x10) +#define FLASH_L4_CR (FLASH_REGS_ADDR + 0x14) +#define FLASH_L4_OPTR (FLASH_REGS_ADDR + 0x20) + +#define FLASH_L4_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ +#define FLASH_L4_SR_PROGERR 3 +#define FLASH_L4_SR_WRPERR 4 +#define FLASH_L4_SR_PGAERR 5 +#define FLASH_L4_SR_BSY 16 + +#define FLASH_L4_CR_LOCK 31 /* Lock control register */ +#define FLASH_L4_CR_OPTLOCK 30 /* Lock option bytes */ +#define FLASH_L4_CR_PG 0 /* Program */ +#define FLASH_L4_CR_PER 1 /* Page erase */ +#define FLASH_L4_CR_MER1 2 /* Bank 1 erase */ +#define FLASH_L4_CR_MER2 15 /* Bank 2 erase */ +#define FLASH_L4_CR_STRT 16 /* Start command */ +#define FLASH_L4_CR_OPTSTRT 17 /* Start writing option bytes */ +#define FLASH_L4_CR_BKER 11 /* Bank select for page erase */ +#define FLASH_L4_CR_PNB 3 /* Page number (8 bits) */ +#define FLASH_L4_CR_OBL_LAUNCH 27 /* Option bytes reload */ // Bits requesting flash operations (useful when we want to clear them) -#define STM32L4_FLASH_CR_OPBITS \ - (uint32_t)((1lu << STM32L4_FLASH_CR_PG) | (1lu << STM32L4_FLASH_CR_PER) | \ - (1lu << STM32L4_FLASH_CR_MER1) | (1lu << STM32L4_FLASH_CR_MER1)) +#define FLASH_L4_CR_OPBITS \ + (uint32_t)((1lu << FLASH_L4_CR_PG) | (1lu << FLASH_L4_CR_PER) | \ + (1lu << FLASH_L4_CR_MER1) | (1lu << FLASH_L4_CR_MER1)) // Page is fully specified by BKER and PNB -#define STM32L4_FLASH_CR_PAGEMASK (uint32_t)(0x1fflu << STM32L4_FLASH_CR_PNB) +#define FLASH_L4_CR_PAGEMASK (uint32_t)(0x1fflu << FLASH_L4_CR_PNB) -#define STM32L4_FLASH_OPTR_DUALBANK 21 +#define FLASH_L4_OPTR_DUALBANK 21 // Flash registers common to STM32L5 series (RM0438, p. 241) -#define STM32L5_FLASH_REGS_ADDR ((uint32_t)0x40022000) -#define STM32L5_FLASH_ACR (STM32L5_FLASH_REGS_ADDR + 0x00) -#define STM32L5_FLASH_NSKEYR (STM32L5_FLASH_REGS_ADDR + 0x08) -#define STM32L5_FLASH_OPTKEYR (STM32L5_FLASH_REGS_ADDR + 0x10) -#define STM32L5_FLASH_NSSR (STM32L5_FLASH_REGS_ADDR + 0x20) -#define STM32L5_FLASH_NSCR (STM32L5_FLASH_REGS_ADDR + 0x28) -#define STM32L5_FLASH_ECCR (STM32L5_FLASH_REGS_ADDR + 0x30) -#define STM32L5_FLASH_OPTR (STM32L5_FLASH_REGS_ADDR + 0x40) +#define FLASH_L5_REGS_ADDR ((uint32_t)0x40022000) +#define FLASH_L5_ACR (FLASH_L5_REGS_ADDR + 0x00) +#define FLASH_L5_NSKEYR (FLASH_L5_REGS_ADDR + 0x08) +#define FLASH_L5_OPTKEYR (FLASH_L5_REGS_ADDR + 0x10) +#define FLASH_L5_NSSR (FLASH_L5_REGS_ADDR + 0x20) +#define FLASH_L5_NSCR (FLASH_L5_REGS_ADDR + 0x28) +#define FLASH_L5_ECCR (FLASH_L5_REGS_ADDR + 0x30) +#define FLASH_L5_OPTR (FLASH_L5_REGS_ADDR + 0x40) // FLASH_NSCR (RM0438, p. 242) -#define STM32L5_FLASH_NSCR_NSPG 0 /* Program */ -#define STM32L5_FLASH_NSCR_NSPER 1 /* Page erase */ -#define STM32L5_FLASH_NSCR_NSMER1 2 /* Bank 1 erase */ -#define STM32L5_FLASH_NSCR_NSPNB 3 /* Page number (7 bits) */ -#define STM32L5_FLASH_NSCR_NSBKER 11 /* Bank select for page erase */ -#define STM32L5_FLASH_NSCR_NSMER2 15 /* Bank 2 erase */ -#define STM32L5_FLASH_NSCR_NSSTRT 16 /* Start command */ -#define STM32L5_FLASH_NSCR_NSOPTSTRT 17 /* Start writing option bytes */ -#define STM32L5_FLASH_NSCR_NSEOPIE 24 -#define STM32L5_FLASH_NSCR_NSERRIE 25 -#define STM32L5_FLASH_NSCR_OBL_LAUNCH 27 /* Option bytes reload */ -#define STM32L5_FLASH_NSCR_OPTLOCK 30 /* Lock option bytes */ -#define STM32L5_FLASH_NSCR_NSLOCK 31 /* Lock control register */ +#define FLASH_L5_NSCR_NSPG 0 /* Program */ +#define FLASH_L5_NSCR_NSPER 1 /* Page erase */ +#define FLASH_L5_NSCR_NSMER1 2 /* Bank 1 erase */ +#define FLASH_L5_NSCR_NSPNB 3 /* Page number (7 bits) */ +#define FLASH_L5_NSCR_NSBKER 11 /* Bank select for page erase */ +#define FLASH_L5_NSCR_NSMER2 15 /* Bank 2 erase */ +#define FLASH_L5_NSCR_NSSTRT 16 /* Start command */ +#define FLASH_L5_NSCR_NSOPTSTRT 17 /* Start writing option bytes */ +#define FLASH_L5_NSCR_NSEOPIE 24 +#define FLASH_L5_NSCR_NSERRIE 25 +#define FLASH_L5_NSCR_OBL_LAUNCH 27 /* Option bytes reload */ +#define FLASH_L5_NSCR_OPTLOCK 30 /* Lock option bytes */ +#define FLASH_L5_NSCR_NSLOCK 31 /* Lock control register */ // FLASH_NSSR (RM0438, p. 241) -#define STM32L5_FLASH_NSSR_NSEOP 0 /* End of Operation */ -#define STM32L5_FLASH_NSSR_NSOPERR 1 -#define STM32L5_FLASH_NSSR_NSPROGERR 3 -#define STM32L5_FLASH_NSSR_NSWRPERR 4 -#define STM32L5_FLASH_NSSR_NSPGAERR 5 -#define STM32L5_FLASH_NSSR_NSSIZERR 6 -#define STM32L5_FLASH_NSSR_NSPGSERR 7 -#define STM32L5_FLASH_NSSR_OPTWERR 12 -#define STM32L5_FLASH_NSSR_BSY 16 /* Busy */ -#define STM32L5_FLASH_NSSR_ERROR_MASK (0x20fa) +#define FLASH_L5_NSSR_NSEOP 0 /* End of Operation */ +#define FLASH_L5_NSSR_NSOPERR 1 +#define FLASH_L5_NSSR_NSPROGERR 3 +#define FLASH_L5_NSSR_NSWRPERR 4 +#define FLASH_L5_NSSR_NSPGAERR 5 +#define FLASH_L5_NSSR_NSSIZERR 6 +#define FLASH_L5_NSSR_NSPGSERR 7 +#define FLASH_L5_NSSR_OPTWERR 12 +#define FLASH_L5_NSSR_BSY 16 /* Busy */ +#define FLASH_L5_NSSR_ERROR_MASK (0x20fa) // STM32L0x flash register base and offsets RM0090 - DM00031020.pdf -#define STM32L0_FLASH_REGS_ADDR ((uint32_t)0x40022000) +#define FLASH_L0_REGS_ADDR ((uint32_t)0x40022000) -#define STM32L0_FLASH_PELOCK (0) -#define STM32L0_FLASH_OPTLOCK (2) -#define STM32L0_FLASH_OBL_LAUNCH (18) +#define FLASH_L0_PELOCK (0) +#define FLASH_L0_OPTLOCK (2) +#define FLASH_L0_OBL_LAUNCH (18) -#define STM32L0_FLASH_SR_ERROR_MASK 0x00013F00 -#define STM32L0_FLASH_SR_WRPERR 8 -#define STM32L0_FLASH_SR_PGAERR 9 -#define STM32L0_FLASH_SR_NOTZEROERR 16 +#define FLASH_L0_SR_ERROR_MASK 0x00013F00 +#define FLASH_L0_SR_WRPERR 8 +#define FLASH_L0_SR_PGAERR 9 +#define FLASH_L0_SR_NOTZEROERR 16 -#define STM32L1_FLASH_SR_ERROR_MASK 0x00003F00 -#define STM32L1_FLASH_SR_WRPERR 8 -#define STM32L1_FLASH_SR_PGAERR 9 +#define FLASH_L1_SR_ERROR_MASK 0x00003F00 +#define FLASH_L1_SR_WRPERR 8 +#define FLASH_L1_SR_PGAERR 9 #define FLASH_ACR_OFF ((uint32_t)0x00) #define FLASH_PECR_OFF ((uint32_t)0x04) diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index ed3b65873..ddab5ed08 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -51,14 +51,14 @@ uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { uint32_t bker = 0; uint32_t flashopt; - stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); + stlink_read_debug32(sl, FLASH_L4_OPTR, &flashopt); flashaddr -= STM32_FLASH_BASE; if (sl->chip_id == STM32_CHIPID_L4 || sl->chip_id == STM32_CHIPID_L496x_L4A6x || sl->chip_id == STM32_CHIPID_L4Rx) { // this chip use dual banked flash - if (flashopt & (uint32_t)(1lu << STM32L4_FLASH_OPTR_DUALBANK)) { + if (flashopt & (uint32_t)(1lu << FLASH_L4_OPTR_DUALBANK)) { uint32_t banksize = (uint32_t)sl->flash_size / 2; if (flashaddr >= banksize) { diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index fac97278e..f2d60ce45 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -288,16 +288,16 @@ int stlink_load_device_params(stlink_t *sl) { if (sl->chip_id == STM32_CHIPID_G4_CAT3) { uint32_t flash_optr; - stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); + stlink_read_debug32(sl, FLASH_Gx_OPTR, &flash_optr); - if (!(flash_optr & (1 << STM32G4_FLASH_OPTR_DBANK))) { + if (!(flash_optr & (1 << FLASH_G4_OPTR_DBANK))) { sl->flash_pgsz <<= 1; } } if (sl->chip_id == STM32_CHIPID_L5x2xx) { uint32_t flash_optr; - stlink_read_debug32(sl, STM32L5_FLASH_OPTR, &flash_optr); + stlink_read_debug32(sl, FLASH_L5_OPTR, &flash_optr); if (sl->flash_size == 512*1024 && (flash_optr & (1 << 22)) != 0) { sl->flash_pgsz = 0x800; @@ -1099,7 +1099,7 @@ static void stop_wdg_in_debug(stlink_t *sl) { break; case STM32_FLASH_TYPE_L0_L1: case STM32_FLASH_TYPE_G0: - if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { + if (get_stm32l0_flash_base(sl) == FLASH_Lx_REGS_ADDR) { dbgmcu_cr = STM32L1_DBGMCU_APB1_FZ; set = (1 << STM32L1_DBGMCU_APB1_FZ_IWDG_STOP) | (1 << STM32L1_DBGMCU_APB1_FZ_WWDG_STOP); diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index dbae1c694..dc33fdfcb 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -16,18 +16,18 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { case STM32_CHIPID_L0_CAT2: case STM32_CHIPID_L0_CAT3: case STM32_CHIPID_L0_CAT5: - return (STM32L0_FLASH_REGS_ADDR); + return (FLASH_L0_REGS_ADDR); case STM32_CHIPID_L1_CAT2: case STM32_CHIPID_L1_MD: case STM32_CHIPID_L1_MD_PLUS: case STM32_CHIPID_L1_MD_PLUS_HD: case STM32_CHIPID_L152_RE: - return (STM32L_FLASH_REGS_ADDR); + return (FLASH_Lx_REGS_ADDR); default: WLOG("Flash base use default L0 address\n"); - return (STM32L0_FLASH_REGS_ADDR); + return (FLASH_L0_REGS_ADDR); } } @@ -40,15 +40,15 @@ uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { reg = FLASH_F7_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - reg = STM32Gx_FLASH_CR; + reg = FLASH_Gx_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - reg = STM32L4_FLASH_CR; + reg = FLASH_L4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - reg = STM32L5_FLASH_NSCR; + reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - reg = STM32WB_FLASH_CR; + reg = FLASH_WB_CR; } else { reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; } @@ -80,22 +80,22 @@ void lock_flash(stlink_t *sl) { cr_lock_shift = FLASH_F7_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + cr_reg = FLASH_Gx_CR; + cr_lock_shift = FLASH_Gx_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; + cr_lock_shift = FLASH_L0_PELOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; + cr_reg = FLASH_L4_CR; + cr_lock_shift = FLASH_L4_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; - cr_lock_shift = STM32L5_FLASH_NSCR_NSLOCK; + cr_reg = FLASH_L5_NSCR; + cr_lock_shift = FLASH_L5_NSCR_NSLOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; + cr_reg = FLASH_WB_CR; + cr_lock_shift = FLASH_WB_CR_LOCK; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { cr2_reg = FLASH_H7_CR2; } @@ -129,17 +129,17 @@ static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { sr_reg = FLASH_F7_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; + sr_reg = FLASH_Gx_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; + sr_reg = FLASH_L4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - sr_reg = STM32L5_FLASH_NSSR; + sr_reg = FLASH_L5_NSSR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_reg = STM32WB_FLASH_SR; + sr_reg = FLASH_WB_SR; } else { ELOG("method 'write_flash_sr' is unsupported\n"); return (-1); @@ -161,7 +161,7 @@ void clear_flash_error(stlink_t *sl) { break; case STM32_FLASH_TYPE_G0: case STM32_FLASH_TYPE_G4: - write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); + write_flash_sr(sl, BANK_1, FLASH_Gx_SR_ERROR_MASK); break; case STM32_FLASH_TYPE_H7: write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); @@ -170,20 +170,20 @@ void clear_flash_error(stlink_t *sl) { } break; case STM32_FLASH_TYPE_L0_L1: - if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { - write_flash_sr(sl, BANK_1, STM32L1_FLASH_SR_ERROR_MASK); + if (get_stm32l0_flash_base(sl) == FLASH_Lx_REGS_ADDR) { + write_flash_sr(sl, BANK_1, FLASH_L1_SR_ERROR_MASK); } else { - write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); + write_flash_sr(sl, BANK_1, FLASH_L0_SR_ERROR_MASK); } break; case STM32_FLASH_TYPE_L4: - write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); + write_flash_sr(sl, BANK_1, FLASH_L4_SR_ERROR_MASK); break; case STM32_FLASH_TYPE_L5_U5: - write_flash_sr(sl, BANK_1, STM32L5_FLASH_NSSR_ERROR_MASK); + write_flash_sr(sl, BANK_1, FLASH_L5_NSSR_ERROR_MASK); break; case STM32_FLASH_TYPE_WB_WL: - write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); + write_flash_sr(sl, BANK_1, FLASH_WB_SR_ERROR_MASK); break; default: break; @@ -202,17 +202,17 @@ uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { sr_reg = FLASH_F7_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - sr_reg = STM32Gx_FLASH_SR; + sr_reg = FLASH_Gx_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_reg = (bank == BANK_1) ? FLASH_H7_SR1 : FLASH_H7_SR2; } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - sr_reg = STM32L4_FLASH_SR; + sr_reg = FLASH_L4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - sr_reg = STM32L5_FLASH_NSSR; + sr_reg = FLASH_L5_NSSR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_reg = STM32WB_FLASH_SR; + sr_reg = FLASH_WB_SR; } else { ELOG("method 'read_flash_sr' is unsupported\n"); return (-1); @@ -236,15 +236,15 @@ unsigned int is_flash_busy(stlink_t *sl) { sr_busy_shift = FLASH_F7_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - sr_busy_shift = STM32Gx_FLASH_SR_BSY; + sr_busy_shift = FLASH_Gx_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { sr_busy_shift = FLASH_H7_SR_QW; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - sr_busy_shift = STM32L4_FLASH_SR_BSY; + sr_busy_shift = FLASH_L4_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - sr_busy_shift = STM32L5_FLASH_NSSR_BSY; + sr_busy_shift = FLASH_L5_NSSR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - sr_busy_shift = STM32WB_FLASH_SR_BSY; + sr_busy_shift = FLASH_WB_SR_BSY; } else { ELOG("method 'is_flash_busy' is unsupported\n"); return (-1); @@ -295,10 +295,10 @@ int check_flash_error(stlink_t *sl) { break; case STM32_FLASH_TYPE_G0: case STM32_FLASH_TYPE_G4: - res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32Gx_FLASH_SR_WRPERR); - PROGERR = (1 << STM32Gx_FLASH_SR_PROGERR); - PGAERR = (1 << STM32Gx_FLASH_SR_PGAERR); + res = read_flash_sr(sl, BANK_1) & FLASH_Gx_SR_ERROR_MASK; + WRPERR = (1 << FLASH_Gx_SR_WRPERR); + PROGERR = (1 << FLASH_Gx_SR_PROGERR); + PGAERR = (1 << FLASH_Gx_SR_PGAERR); break; case STM32_FLASH_TYPE_H7: res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; @@ -309,32 +309,32 @@ int check_flash_error(stlink_t *sl) { break; case STM32_FLASH_TYPE_L0_L1: res = read_flash_sr(sl, BANK_1); - if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { - res &= STM32L1_FLASH_SR_ERROR_MASK; + if (get_stm32l0_flash_base(sl) == FLASH_Lx_REGS_ADDR) { + res &= FLASH_L1_SR_ERROR_MASK; } else { - res &= STM32L0_FLASH_SR_ERROR_MASK; - PROGERR = (1 << STM32L0_FLASH_SR_NOTZEROERR); + res &= FLASH_L0_SR_ERROR_MASK; + PROGERR = (1 << FLASH_L0_SR_NOTZEROERR); } - WRPERR = (1 << STM32L0_FLASH_SR_WRPERR); - PGAERR = (1 << STM32L0_FLASH_SR_PGAERR); + WRPERR = (1 << FLASH_L0_SR_WRPERR); + PGAERR = (1 << FLASH_L0_SR_PGAERR); break; case STM32_FLASH_TYPE_L4: - res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32L4_FLASH_SR_WRPERR); - PROGERR = (1 << STM32L4_FLASH_SR_PROGERR); - PGAERR = (1 << STM32L4_FLASH_SR_PGAERR); + res = read_flash_sr(sl, BANK_1) & FLASH_L4_SR_ERROR_MASK; + WRPERR = (1 << FLASH_L4_SR_WRPERR); + PROGERR = (1 << FLASH_L4_SR_PROGERR); + PGAERR = (1 << FLASH_L4_SR_PGAERR); break; case STM32_FLASH_TYPE_L5_U5: - res = read_flash_sr(sl, BANK_1) & STM32L5_FLASH_NSSR_ERROR_MASK; - WRPERR = (1 << STM32L5_FLASH_NSSR_NSWRPERR); - PROGERR = (1 << STM32L5_FLASH_NSSR_NSPROGERR); - PGAERR = (1 << STM32L5_FLASH_NSSR_NSPGAERR); + res = read_flash_sr(sl, BANK_1) & FLASH_L5_NSSR_ERROR_MASK; + WRPERR = (1 << FLASH_L5_NSSR_NSWRPERR); + PROGERR = (1 << FLASH_L5_NSSR_NSPROGERR); + PGAERR = (1 << FLASH_L5_NSSR_NSPGAERR); break; case STM32_FLASH_TYPE_WB_WL: - res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; - WRPERR = (1 << STM32WB_FLASH_SR_WRPERR); - PROGERR = (1 << STM32WB_FLASH_SR_PROGERR); - PGAERR = (1 << STM32WB_FLASH_SR_PGAERR); + res = read_flash_sr(sl, BANK_1) & FLASH_WB_SR_ERROR_MASK; + WRPERR = (1 << FLASH_WB_SR_WRPERR); + PROGERR = (1 << FLASH_WB_SR_PROGERR); + PGAERR = (1 << FLASH_WB_SR_PGAERR); break; default: break; @@ -379,23 +379,23 @@ static inline unsigned int is_flash_locked(stlink_t *sl) { cr_lock_shift = FLASH_F7_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_lock_shift = STM32Gx_FLASH_CR_LOCK; + cr_reg = FLASH_Gx_CR; + cr_lock_shift = FLASH_Gx_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; cr_lock_shift = FLASH_H7_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - cr_lock_shift = STM32L0_FLASH_PELOCK; + cr_lock_shift = FLASH_L0_PELOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_lock_shift = STM32L4_FLASH_CR_LOCK; + cr_reg = FLASH_L4_CR; + cr_lock_shift = FLASH_L4_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; - cr_lock_shift = STM32L5_FLASH_NSCR_NSLOCK; + cr_reg = FLASH_L5_NSCR; + cr_lock_shift = FLASH_L5_NSCR_NSLOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_lock_shift = STM32WB_FLASH_CR_LOCK; + cr_reg = FLASH_WB_CR; + cr_lock_shift = FLASH_WB_CR_LOCK; } else { ELOG("unsupported flash method, abort\n"); return (-1); @@ -425,7 +425,7 @@ static void unlock_flash(stlink_t *sl) { key_reg = FLASH_F7_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - key_reg = STM32Gx_FLASH_KEYR; + key_reg = FLASH_Gx_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { key_reg = FLASH_H7_KEYR1; if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -436,7 +436,7 @@ static void unlock_flash(stlink_t *sl) { flash_key1 = FLASH_L0_PEKEY1; flash_key2 = FLASH_L0_PEKEY2; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - key_reg = STM32L4_FLASH_KEYR; + key_reg = FLASH_L4_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { // Set voltage scaling to range 0 to perform flash operations (RM0438 p. 183) uint32_t mask = (0b11 << STM32L5_PWR_CR1_VOS); @@ -445,9 +445,9 @@ static void unlock_flash(stlink_t *sl) { val &= ~mask; stlink_write_debug32(sl, STM32L5_PWR_CR1, val); } - key_reg = STM32L5_FLASH_NSKEYR; + key_reg = FLASH_L5_NSKEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - key_reg = STM32WB_FLASH_KEYR; + key_reg = FLASH_WB_KEYR; } else { ELOG("unsupported flash method, abort\n"); return; @@ -498,8 +498,8 @@ int lock_flash_option(stlink_t *sl) { break; case STM32_FLASH_TYPE_G0: case STM32_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + optcr_reg = FLASH_Gx_CR; + optlock_shift = FLASH_Gx_CR_OPTLOCK; break; case STM32_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; @@ -509,19 +509,19 @@ int lock_flash_option(stlink_t *sl) { break; case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; + optlock_shift = FLASH_L0_OPTLOCK; break; case STM32_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + optcr_reg = FLASH_L4_CR; + optlock_shift = FLASH_L4_CR_OPTLOCK; break; case STM32_FLASH_TYPE_L5_U5: - optcr_reg = STM32L5_FLASH_NSCR; - optlock_shift = STM32L5_FLASH_NSCR_OPTLOCK; + optcr_reg = FLASH_L5_NSCR; + optlock_shift = FLASH_L5_NSCR_OPTLOCK; break; case STM32_FLASH_TYPE_WB_WL: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + optcr_reg = FLASH_WB_CR; + optlock_shift = FLASH_WB_CR_OPTLOCK; break; default: ELOG("unsupported flash method, abort\n"); @@ -575,8 +575,8 @@ static bool is_flash_option_locked(stlink_t *sl) { break; case STM32_FLASH_TYPE_G0: case STM32_FLASH_TYPE_G4: - optcr_reg = STM32Gx_FLASH_CR; - optlock_shift = STM32Gx_FLASH_CR_OPTLOCK; + optcr_reg = FLASH_Gx_CR; + optlock_shift = FLASH_Gx_CR_OPTLOCK; break; case STM32_FLASH_TYPE_H7: optcr_reg = FLASH_H7_OPTCR; @@ -584,19 +584,19 @@ static bool is_flash_option_locked(stlink_t *sl) { break; case STM32_FLASH_TYPE_L0_L1: optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; - optlock_shift = STM32L0_FLASH_OPTLOCK; + optlock_shift = FLASH_L0_OPTLOCK; break; case STM32_FLASH_TYPE_L4: - optcr_reg = STM32L4_FLASH_CR; - optlock_shift = STM32L4_FLASH_CR_OPTLOCK; + optcr_reg = FLASH_L4_CR; + optlock_shift = FLASH_L4_CR_OPTLOCK; break; case STM32_FLASH_TYPE_L5_U5: - optcr_reg = STM32L5_FLASH_NSCR; - optlock_shift = STM32L5_FLASH_NSCR_OPTLOCK; + optcr_reg = FLASH_L5_NSCR; + optlock_shift = FLASH_L5_NSCR_OPTLOCK; break; case STM32_FLASH_TYPE_WB_WL: - optcr_reg = STM32WB_FLASH_CR; - optlock_shift = STM32WB_FLASH_CR_OPTLOCK; + optcr_reg = FLASH_WB_CR; + optlock_shift = FLASH_WB_CR_OPTLOCK; break; default: ELOG("unsupported flash method, abort\n"); @@ -632,7 +632,7 @@ static int unlock_flash_option(stlink_t *sl) { break; case STM32_FLASH_TYPE_G0: case STM32_FLASH_TYPE_G4: - optkey_reg = STM32Gx_FLASH_OPTKEYR; + optkey_reg = FLASH_Gx_OPTKEYR; break; case STM32_FLASH_TYPE_H7: optkey_reg = FLASH_H7_OPT_KEYR; @@ -645,13 +645,13 @@ static int unlock_flash_option(stlink_t *sl) { optkey2 = FLASH_L0_OPTKEY2; break; case STM32_FLASH_TYPE_L4: - optkey_reg = STM32L4_FLASH_OPTKEYR; + optkey_reg = FLASH_L4_OPTKEYR; break; case STM32_FLASH_TYPE_L5_U5: - optkey_reg = STM32L5_FLASH_OPTKEYR; + optkey_reg = FLASH_L5_OPTKEYR; break; case STM32_FLASH_TYPE_WB_WL: - optkey_reg = STM32WB_FLASH_OPT_KEYR; + optkey_reg = FLASH_WB_OPT_KEYR; break; default: ELOG("unsupported flash method, abort\n"); @@ -717,16 +717,16 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { cr_reg = FLASH_F7_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; + cr_reg = FLASH_Gx_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; bit = FLASH_H7_CR_PG; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; + cr_reg = FLASH_L4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; + cr_reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; + cr_reg = FLASH_WB_CR; } else { cr_reg = FLASH_CR; } @@ -788,11 +788,11 @@ static void set_flash_cr_per(stlink_t *sl, unsigned bank) { if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; + cr_reg = FLASH_Gx_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; + cr_reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; + cr_reg = FLASH_WB_CR; } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; } @@ -807,11 +807,11 @@ static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; + cr_reg = FLASH_Gx_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; + cr_reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; + cr_reg = FLASH_WB_CR; } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; } @@ -821,19 +821,19 @@ static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { } static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { - stlink_write_debug32(sl, STM32L4_FLASH_SR, - 0xFFFFFFFF & ~(1 << STM32L4_FLASH_SR_BSY)); + stlink_write_debug32(sl, FLASH_L4_SR, + 0xFFFFFFFF & ~(1 << FLASH_L4_SR_BSY)); uint32_t x = read_flash_cr(sl, BANK_1); - x &= ~STM32L4_FLASH_CR_OPBITS; - x &= ~STM32L4_FLASH_CR_PAGEMASK; - x &= ~(1 << STM32L4_FLASH_CR_MER1); - x &= ~(1 << STM32L4_FLASH_CR_MER2); - x |= (n << STM32L4_FLASH_CR_PNB); - x |= (uint32_t)(1lu << STM32L4_FLASH_CR_PER); + x &= ~FLASH_L4_CR_OPBITS; + x &= ~FLASH_L4_CR_PAGEMASK; + x &= ~(1 << FLASH_L4_CR_MER1); + x &= ~(1 << FLASH_L4_CR_MER2); + x |= (n << FLASH_L4_CR_PNB); + x |= (uint32_t)(1lu << FLASH_L4_CR_PER); #if DEBUG_FLASH fprintf(stdout, "BKER:PNB:0x%x 0x%x\n", x, n); #endif - stlink_write_debug32(sl, STM32L4_FLASH_CR, x); + stlink_write_debug32(sl, FLASH_L4_CR, x); } static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { @@ -847,20 +847,20 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { cr_strt = 1 << FLASH_F7_CR_STRT; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_strt = (1 << STM32Gx_FLASH_CR_STRT); + cr_reg = FLASH_Gx_CR; + cr_strt = (1 << FLASH_Gx_CR_STRT); } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_strt = (1 << STM32L4_FLASH_CR_STRT); + cr_reg = FLASH_L4_CR; + cr_strt = (1 << FLASH_L4_CR_STRT); } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; - cr_strt = (1 << STM32L5_FLASH_NSCR_NSSTRT); + cr_reg = FLASH_L5_NSCR; + cr_strt = (1 << FLASH_L5_NSCR_NSSTRT); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; - cr_strt = (1 << STM32WB_FLASH_CR_STRT); + cr_reg = FLASH_WB_CR; + cr_strt = (1 << FLASH_WB_CR_STRT); } else { cr_reg = (bank == BANK_1) ? FLASH_CR : FLASH_CR2; cr_strt = (1 << FLASH_CR_STRT); @@ -884,10 +884,10 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { cr_pg = 1 << FLASH_CR_PG; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; - cr_mer = (1 << STM32Gx_FLASH_CR_MER1); + cr_reg = FLASH_Gx_CR; + cr_mer = (1 << FLASH_Gx_CR_MER1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr_mer |= (1 << STM32Gx_FLASH_CR_MER2); + cr_mer |= (1 << FLASH_Gx_CR_MER2); } cr_pg = (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { @@ -895,15 +895,15 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { cr_mer = (1 << FLASH_H7_CR_BER); cr_pg = (1 << FLASH_H7_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - cr_mer = (1 << STM32L4_FLASH_CR_MER1) | (1 << STM32L4_FLASH_CR_MER2); - cr_pg = (1 << STM32L4_FLASH_CR_PG); + cr_reg = FLASH_L4_CR; + cr_mer = (1 << FLASH_L4_CR_MER1) | (1 << FLASH_L4_CR_MER2); + cr_pg = (1 << FLASH_L4_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; - cr_mer = (1 << STM32L5_FLASH_NSCR_NSMER1) | (1 << STM32L5_FLASH_NSCR_NSMER2); - cr_pg = (1 << STM32L5_FLASH_NSCR_NSPG); + cr_reg = FLASH_L5_NSCR; + cr_mer = (1 << FLASH_L5_NSCR_NSMER1) | (1 << FLASH_L5_NSCR_NSMER2); + cr_pg = (1 << FLASH_L5_NSCR_NSPG); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; + cr_reg = FLASH_WB_CR; cr_mer = (1 << FLASH_CR_MER); cr_pg = (1 << FLASH_CR_PG); } else { @@ -1059,47 +1059,47 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if (sl->flash_type == STM32_FLASH_TYPE_G0) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + stlink_read_debug32(sl, FLASH_Gx_CR, &val); // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. val &= ~(0x3F << 3); val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + stlink_write_debug32(sl, FLASH_Gx_CR, val); } else if (sl->flash_type == STM32_FLASH_TYPE_G4) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); + stlink_read_debug32(sl, FLASH_Gx_CR, &val); // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. val &= ~(0x7F << 3); val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + stlink_write_debug32(sl, FLASH_Gx_CR, val); } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { uint32_t flash_page; - stlink_read_debug32(sl, STM32L5_FLASH_NSCR, &val); + stlink_read_debug32(sl, FLASH_L5_NSCR, &val); if (sl->flash_pgsz == 0x800 && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) { flash_page = (flashaddr - STM32_FLASH_BASE - sl->flash_size/2) / (uint32_t)(sl->flash_pgsz); // set bank 2 for erasure - val |= (1 << STM32L5_FLASH_NSCR_NSBKER); + val |= (1 << FLASH_L5_NSCR_NSBKER); } else { flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); // set bank 1 for erasure - val &= ~(1 << STM32L5_FLASH_NSCR_NSBKER); + val &= ~(1 << FLASH_L5_NSCR_NSBKER); } // sec 6.9.9 val &= ~(0x7F << 3); val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); - stlink_write_debug32(sl, STM32L5_FLASH_NSCR, val); + stlink_write_debug32(sl, FLASH_L5_NSCR, val); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); + stlink_read_debug32(sl, FLASH_WB_CR, &val); // sec 3.10.5 - PNB[7:0] is offset by 3. val &= ~(0xFF << 3); // Clear previously set page number (if any) val |= ((flash_page & 0xFF) << 3); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + stlink_write_debug32(sl, FLASH_WB_CR, val); } set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index ebdf0a44e..f0ce9be42 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -495,18 +495,18 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { cr_reg = FLASH_F7_CR; x |= 1 << FLASH_CR_PG; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = STM32L4_FLASH_CR; - x &= ~STM32L4_FLASH_CR_OPBITS; - x |= (1 << STM32L4_FLASH_CR_PG); + cr_reg = FLASH_L4_CR; + x &= ~FLASH_L4_CR_OPBITS; + x |= (1 << FLASH_L4_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - cr_reg = STM32L5_FLASH_NSCR; + cr_reg = FLASH_L5_NSCR; x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = STM32Gx_FLASH_CR; + cr_reg = FLASH_Gx_CR; x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - cr_reg = STM32WB_FLASH_CR; + cr_reg = FLASH_WB_CR; x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; @@ -545,7 +545,7 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { rcc_dma_mask = STM32G4_RCC_DMAEN; break; case STM32_FLASH_TYPE_L0_L1: - if (get_stm32l0_flash_base(sl) == STM32L_FLASH_REGS_ADDR) { + if (get_stm32l0_flash_base(sl) == FLASH_Lx_REGS_ADDR) { rcc = STM32L1_RCC_AHBENR; rcc_dma_mask = STM32L1_RCC_DMAEN; } else { @@ -770,7 +770,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - uint32_t pagesize = (flash_regs_base==STM32L0_FLASH_REGS_ADDR)? + uint32_t pagesize = (flash_regs_base == FLASH_L0_REGS_ADDR)? L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 9cbdd097b..f5932a7b9 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -429,7 +429,7 @@ stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_ad * @return 0 on success, -ve on failure. */ int stlink_read_option_control_register_gx(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); + return stlink_read_debug32(sl, FLASH_Gx_OPTR, option_byte); } /** @@ -461,21 +461,21 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, stm32_addr_t addr, uint8_t write_uint32((unsigned char *)&data, *(uint32_t *)(base)); WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); + stlink_write_debug32(sl, FLASH_Gx_OPTR, data); // Set Options Start bit - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + stlink_read_debug32(sl, FLASH_Gx_CR, &val); + val |= (1 << FLASH_Gx_CR_OPTSTRT); + stlink_write_debug32(sl, FLASH_Gx_CR, val); wait_flash_busy(sl); ret = check_flash_error(sl); // Reload options - stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); - val |= (1 << STM32Gx_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); + stlink_read_debug32(sl, FLASH_Gx_CR, &val); + val |= (1 << FLASH_Gx_CR_OBL_LAUNCH); + stlink_write_debug32(sl, FLASH_Gx_CR, val); return (ret); } @@ -584,7 +584,7 @@ static int stlink_write_option_bytes_l0(stlink_t *sl, stm32_addr_t addr, uint8_t // Reload options stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); - val |= (1 << STM32L0_FLASH_OBL_LAUNCH); + val |= (1 << FLASH_L0_OBL_LAUNCH); stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); return (ret); @@ -612,20 +612,20 @@ static int stlink_write_option_bytes_l4(stlink_t *sl, stm32_addr_t addr, uint8_t uint32_t data; write_uint32((unsigned char *)&data, *(uint32_t *)(base)); WLOG("Writing option bytes 0x%04x\n", data); - stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); + stlink_write_debug32(sl, FLASH_L4_OPTR, data); // set options start bit - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + stlink_read_debug32(sl, FLASH_L4_CR, &val); + val |= (1 << FLASH_L4_CR_OPTSTRT); + stlink_write_debug32(sl, FLASH_L4_CR, val); wait_flash_busy(sl); ret = check_flash_error(sl); // apply options bytes immediate - stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); - val |= (1 << STM32L4_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32L4_FLASH_CR, val); + stlink_read_debug32(sl, FLASH_L4_CR, &val); + val |= (1 << FLASH_L4_CR_OBL_LAUNCH); + stlink_write_debug32(sl, FLASH_L4_CR, val); return (ret); } @@ -664,18 +664,18 @@ static int stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uint8_t } // Set Options Start bit - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - val |= (1 << STM32WB_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + stlink_read_debug32(sl, FLASH_WB_CR, &val); + val |= (1 << FLASH_WB_CR_OPTSTRT); + stlink_write_debug32(sl, FLASH_WB_CR, val); wait_flash_busy(sl); ret = check_flash_error(sl); // Reload options - stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); - val |= (1 << STM32WB_FLASH_CR_OBL_LAUNCH); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + stlink_read_debug32(sl, FLASH_WB_CR, &val); + val |= (1 << FLASH_WB_CR_OBL_LAUNCH); + stlink_write_debug32(sl, FLASH_WB_CR, val); return (ret); } @@ -687,8 +687,8 @@ static int stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uint8_t * @return 0 on success, -ve on failure. */ int stlink_read_option_control_register_wb(stlink_t *sl, uint32_t *option_byte) { - DLOG("@@@@ Read option control register byte from %#10x\n", STM32WB_FLASH_OPTR); - return stlink_read_debug32(sl, STM32WB_FLASH_OPTR, option_byte); + DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_WB_OPTR); + return stlink_read_debug32(sl, FLASH_WB_OPTR, option_byte); } /** @@ -704,22 +704,22 @@ static int stlink_write_option_control_register_wb(stlink_t *sl, uint32_t option clear_flash_error(sl); ILOG("Asked to write option control register 1 %#10x to %#010x.\n", - option_cr, STM32WB_FLASH_OPTR); + option_cr, FLASH_WB_OPTR); /* write option byte, ensuring we dont lock opt, and set strt bit */ - stlink_write_debug32(sl, STM32WB_FLASH_OPTR, option_cr); + stlink_write_debug32(sl, FLASH_WB_OPTR, option_cr); wait_flash_busy(sl); // Set Options Start bit - uint32_t val = (1 << STM32WB_FLASH_CR_OPTSTRT); - stlink_write_debug32(sl, STM32WB_FLASH_CR, val); + uint32_t val = (1 << FLASH_WB_CR_OPTSTRT); + stlink_write_debug32(sl, FLASH_WB_CR, val); wait_flash_busy(sl); ret = check_flash_error(sl); if (!ret) - ILOG("Wrote option bytes %#010x to %#010x!\n", option_cr, STM32WB_FLASH_OPTR); + ILOG("Wrote option bytes %#010x to %#010x!\n", option_cr, FLASH_WB_OPTR); return ret; } From 5621d541d9b175e0fb6d1354fedd1da5ff5c1902 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 3 May 2023 13:55:19 +0200 Subject: [PATCH 1372/1435] Resorted #defines in stm32flash.h --- inc/stm32flash.h | 498 ++++++++++++++++++---------------- src/stlink-lib/common.c | 3 +- src/stlink-lib/common_flash.c | 2 +- src/stlink-lib/flash_loader.c | 4 +- 4 files changed, 269 insertions(+), 238 deletions(-) diff --git a/inc/stm32flash.h b/inc/stm32flash.h index ccbc0289d..12d2f5a7b 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -1,8 +1,8 @@ #ifndef STM32FLASH_H_ #define STM32FLASH_H_ -/* stm32f FPEC flash controller interface, pm0063 manual */ -// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev 2, August 2012) +/* STM32Fx FPEC flash controller interface, PM0063 manual */ +// STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev.2, Aug 2012) #define FLASH_REGS_ADDR 0x40022000 #define FLASH_REGS_SIZE 0x28 @@ -15,32 +15,19 @@ #define FLASH_OBR (FLASH_REGS_ADDR + 0x1c) #define FLASH_WRPR (FLASH_REGS_ADDR + 0x20) -// STM32F10x_XL has two flash memory banks with separate registers to control -// the second bank. +// STM32F10x_XL has two flash memory banks +// with separate registers to control the second bank. #define FLASH_KEYR2 (FLASH_REGS_ADDR + 0x44) #define FLASH_SR2 (FLASH_REGS_ADDR + 0x4c) #define FLASH_CR2 (FLASH_REGS_ADDR + 0x50) #define FLASH_AR2 (FLASH_REGS_ADDR + 0x54) -// For STM32F05x, the RDPTR_KEY may be wrong, but as it is not used anywhere... #define FLASH_RDPTR_KEY 0x00a5 #define FLASH_KEY1 0x45670123 #define FLASH_KEY2 0xcdef89ab -#define FLASH_L0_PRGKEY1 0x8c9daebf -#define FLASH_L0_PRGKEY2 0x13141516 - -#define FLASH_L0_PEKEY1 0x89abcdef -#define FLASH_L0_PEKEY2 0x02030405 - -#define FLASH_OPTKEY1 0x08192A3B -#define FLASH_OPTKEY2 0x4C5D6E7F - -#define FLASH_F0_OPTKEY1 0x45670123 -#define FLASH_F0_OPTKEY2 0xCDEF89AB - -#define FLASH_L0_OPTKEY1 0xFBEAD9C8 -#define FLASH_L0_OPTKEY2 0x24252627 +#define FLASH_OPTKEY1 0x08192a3b +#define FLASH_OPTKEY2 0x4c5d6e7f #define FLASH_SR_BSY 0 #define FLASH_SR_PG_ERR 2 @@ -59,20 +46,99 @@ #define FLASH_CR_OPTWRE 9 #define FLASH_CR_OBL_LAUNCH 13 -#define FLASH_Lx_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_Lx_ACR (FLASH_Lx_REGS_ADDR + 0x00) -#define FLASH_Lx_PECR (FLASH_Lx_REGS_ADDR + 0x04) -#define FLASH_Lx_PDKEYR (FLASH_Lx_REGS_ADDR + 0x08) -#define FLASH_Lx_PEKEYR (FLASH_Lx_REGS_ADDR + 0x0c) -#define FLASH_Lx_PRGKEYR (FLASH_Lx_REGS_ADDR + 0x10) -#define FLASH_Lx_OPTKEYR (FLASH_Lx_REGS_ADDR + 0x14) -#define FLASH_Lx_SR (FLASH_Lx_REGS_ADDR + 0x18) -#define FLASH_Lx_OBR (FLASH_Lx_REGS_ADDR + 0x1c) -#define FLASH_Lx_WRPR (FLASH_Lx_REGS_ADDR + 0x20) -#define FLASH_L1_FPRG 10 -#define FLASH_L1_PROG 3 +#define FLASH_ACR_OFF ((uint32_t)0x00) +#define FLASH_PECR_OFF ((uint32_t)0x04) +#define FLASH_PDKEYR_OFF ((uint32_t)0x08) +#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) +#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) +#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) +#define FLASH_SR_OFF ((uint32_t)0x18) +#define FLASH_OBR_OFF ((uint32_t)0x1c) +#define FLASH_WRPR_OFF ((uint32_t)0x20) + +// == STM32F0 == +#define FLASH_F0_OPTKEY1 0x45670123 +#define FLASH_F0_OPTKEY2 0xcdef89ab + +// == STM32F2 == +#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) +#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) +#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) +#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) +#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) +#define FLASH_F2_OPT_LOCK_BIT (1u << 0) + +// F2 Flash control register +#define FLASH_F2_CR_STRT 16 +#define FLASH_F2_CR_LOCK 31 +#define FLASH_F2_CR_SER 1 +#define FLASH_F2_CR_SNB 3 +#define FLASH_F2_CR_SNB_MASK 0x78 + +// F2 Flash status register +#define FLASH_F2_SR_BSY 16 + +// == STM32F4 == +// F4 Flash registers +#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) +#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) +#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) +#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) +#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) +#define FLASH_F4_OPTCR_LOCK 0 +#define FLASH_F4_OPTCR_START 1 + +// F4 Flash control register +#define FLASH_F4_CR_STRT 16 +#define FLASH_F4_CR_LOCK 31 +#define FLASH_F4_CR_SER 1 +#define FLASH_F4_CR_SNB 3 +#define FLASH_F4_CR_SNB_MASK 0xf8 + +// F4 Flash status register +#define FLASH_F4_SR_ERROR_MASK 0x000000F0 +#define FLASH_F4_SR_PGAERR 5 +#define FLASH_F4_SR_WRPERR 4 +#define FLASH_F4_SR_BSY 16 -// Flash registers common to STM32G0 and STM32G4 series (RM0440, p. 146) +// == STM32F7 == +// F7 Flash registers +#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) +#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) +#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) +#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) +#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) +#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) +#define FLASH_F7_OPTCR_LOCK 0 +#define FLASH_F7_OPTCR_START 1 +#define FLASH_F7_OPTCR1_BOOT_ADD0 0 +#define FLASH_F7_OPTCR1_BOOT_ADD1 16 + +// F7 Flash control register +#define FLASH_F7_CR_STRT 16 +#define FLASH_F7_CR_LOCK 31 +#define FLASH_F7_CR_SER 1 +#define FLASH_F7_CR_SNB 3 +#define FLASH_F7_CR_SNB_MASK 0xf8 + +// F7 Flash status register +#define FLASH_F7_SR_BSY 16 +#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ +#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ +#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ +#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ +#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ +#define FLASH_F7_SR_EOP 0 /* End of operation */ +#define FLASH_F7_SR_ERROR_MASK \ + ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ + (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ + (1 << FLASH_F7_SR_OP_ERR)) + +// == STM32G0/G4 == +// G0/G4 Flash registers (RM0440, p.146) #define FLASH_Gx_REGS_ADDR ((uint32_t)0x40022000) #define FLASH_Gx_ACR (FLASH_Gx_REGS_ADDR + 0x00) #define FLASH_Gx_KEYR (FLASH_Gx_REGS_ADDR + 0x08) @@ -82,111 +148,171 @@ #define FLASH_Gx_ECCR (FLASH_Gx_REGS_ADDR + 0x18) #define FLASH_Gx_OPTR (FLASH_Gx_REGS_ADDR + 0x20) -// G0 (RM0444 Table 1, sec 3.7) +// G0/G4 Flash control register +#define FLASH_Gx_CR_PG (0) /* Program */ +#define FLASH_Gx_CR_PER (1) /* Page erase */ +#define FLASH_Gx_CR_MER1 (2) /* Mass erase */ +#define FLASH_Gx_CR_PNB (3) /* Page number */ +#define FLASH_G0_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ +#define FLASH_G4_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ +#define FLASH_Gx_CR_MER2 (15) /* Mass erase (2nd bank)*/ +#define FLASH_Gx_CR_STRT (16) /* Start */ +#define FLASH_Gx_CR_OPTSTRT (17) /* Start of modification of option bytes */ +#define FLASH_Gx_CR_FSTPG (18) /* Fast programming */ +#define FLASH_Gx_CR_EOPIE (24) /* End of operation interrupt enable */ +#define FLASH_Gx_CR_ERRIE (25) /* Error interrupt enable */ +#define FLASH_Gx_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define FLASH_Gx_CR_OPTLOCK (30) /* Options Lock */ +#define FLASH_Gx_CR_LOCK (31) /* FLASH_CR Lock */ + +// G0/G4 Flash status register +#define FLASH_Gx_SR_ERROR_MASK (0x3fa) +#define FLASH_Gx_SR_PROGERR (3) +#define FLASH_Gx_SR_WRPERR (4) +#define FLASH_Gx_SR_PGAERR (5) +#define FLASH_Gx_SR_BSY (16) /* FLASH_SR Busy */ +#define FLASH_Gx_SR_EOP (0) /* FLASH_EOP End of Operation */ + +// == STM32G0 == (RM0444 Table 1, sec. 3.7) // Mostly the same as G4 chips, but the notation // varies a bit after the 'OPTR' register. #define FLASH_G0_REGS_ADDR (FLASH_Gx_REGS_ADDR) #define FLASH_G0_PCROP1ASR (FLASH_G0_REGS_ADDR + 0x24) #define FLASH_G0_PCROP1AER (FLASH_G0_REGS_ADDR + 0x28) -#define FLASH_G0_WRP1AR (FLASH_G0_REGS_ADDR + 0x2C) +#define FLASH_G0_WRP1AR (FLASH_G0_REGS_ADDR + 0x2c) #define FLASH_G0_WRP1BR (FLASH_G0_REGS_ADDR + 0x30) #define FLASH_G0_PCROP1BSR (FLASH_G0_REGS_ADDR + 0x34) #define FLASH_G0_PCROP1BER (FLASH_G0_REGS_ADDR + 0x38) #define FLASH_G0_SECR (FLASH_G0_REGS_ADDR + 0x80) -// G4 (RM0440 Table 17, sec 3.7.19) -// Mostly the same as STM32G0 chips, but there are a few extra -// registers because 'cat 3' devices can have two Flash banks. +// == STM32G4 == (RM0440 Table 17, sec. 3.7.19) + +#define FLASH_G4_OPTR_DBANK (22) /* FLASH option register FLASH_OPTR Dual-Bank Mode */ + +// There are a few extra registers because 'cat 3' devices can have +// two Flash banks. #define FLASH_G4_REGS_ADDR (FLASH_Gx_REGS_ADDR) #define FLASH_G4_PDKEYR (FLASH_G4_REGS_ADDR + 0x04) #define FLASH_G4_PCROP1SR (FLASH_G4_REGS_ADDR + 0x24) #define FLASH_G4_PCROP1ER (FLASH_G4_REGS_ADDR + 0x28) -#define FLASH_G4_WRP1AR (FLASH_G4_REGS_ADDR + 0x2C) +#define FLASH_G4_WRP1AR (FLASH_G4_REGS_ADDR + 0x2c) #define FLASH_G4_WRP1BR (FLASH_G4_REGS_ADDR + 0x30) #define FLASH_G4_PCROP2SR (FLASH_G4_REGS_ADDR + 0x44) #define FLASH_G4_PCROP2ER (FLASH_G4_REGS_ADDR + 0x48) -#define FLASH_G4_WRP2AR (FLASH_G4_REGS_ADDR + 0x4C) +#define FLASH_G4_WRP2AR (FLASH_G4_REGS_ADDR + 0x4c) #define FLASH_G4_WRP2BR (FLASH_G4_REGS_ADDR + 0x50) #define FLASH_G4_SEC1R (FLASH_G4_REGS_ADDR + 0x70) #define FLASH_G4_SEC2R (FLASH_G4_REGS_ADDR + 0x74) -// G0/G4 FLASH control register -#define FLASH_Gx_CR_PG (0) /* Program */ -#define FLASH_Gx_CR_PER (1) /* Page erase */ -#define FLASH_Gx_CR_MER1 (2) /* Mass erase */ -#define FLASH_Gx_CR_PNB (3) /* Page number */ -#define FLASH_G0_CR_PNG_LEN (5) /* STM32G0: 5 page number bits */ -#define FLASH_G4_CR_PNG_LEN (7) /* STM32G4: 7 page number bits */ -#define FLASH_Gx_CR_MER2 (15) /* Mass erase (2nd bank)*/ -#define FLASH_Gx_CR_STRT (16) /* Start */ -#define FLASH_Gx_CR_OPTSTRT \ - (17) /* Start of modification of option bytes */ -#define FLASH_Gx_CR_FSTPG (18) /* Fast programming */ -#define FLASH_Gx_CR_EOPIE (24) /* End of operation interrupt enable */ -#define FLASH_Gx_CR_ERRIE (25) /* Error interrupt enable */ -#define FLASH_Gx_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define FLASH_Gx_CR_OPTLOCK (30) /* Options Lock */ -#define FLASH_Gx_CR_LOCK (31) /* FLASH_CR Lock */ +// == STM32H7 == +// H7 Flash registers +#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) +#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) +#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) +#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) +#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) +#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) +#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) +#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) +#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) +#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) +#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) +#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) +#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) +#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) +#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) -// G0/G4 FLASH status register -#define FLASH_Gx_SR_ERROR_MASK (0x3fa) -#define FLASH_Gx_SR_PROGERR (3) -#define FLASH_Gx_SR_WRPERR (4) -#define FLASH_Gx_SR_PGAERR (5) -#define FLASH_Gx_SR_BSY (16) /* FLASH_SR Busy */ -#define FLASH_Gx_SR_EOP (0) /* FLASH_EOP End of Operation */ +#define FLASH_H7_OPTCR_OPTLOCK 0 +#define FLASH_H7_OPTCR_OPTSTART 1 +#define FLASH_H7_OPTCR_MER 4 -// G4 FLASH option register -#define FLASH_G4_OPTR_DBANK (22) /* FLASH_OPTR Dual Bank Mode */ +#define FLASH_H7_OPTSR_OPT_BUSY 0 +#define FLASH_H7_OPTSR_OPTCHANGEERR 30 -// WB (RM0434) -#define FLASH_WB_REGS_ADDR ((uint32_t)0x58004000) -#define FLASH_WB_ACR (FLASH_WB_REGS_ADDR + 0x00) -#define FLASH_WB_KEYR (FLASH_WB_REGS_ADDR + 0x08) -#define FLASH_WB_OPT_KEYR (FLASH_WB_REGS_ADDR + 0x0C) -#define FLASH_WB_SR (FLASH_WB_REGS_ADDR + 0x10) -#define FLASH_WB_CR (FLASH_WB_REGS_ADDR + 0x14) -#define FLASH_WB_ECCR (FLASH_WB_REGS_ADDR + 0x18) -#define FLASH_WB_OPTR (FLASH_WB_REGS_ADDR + 0x20) -#define FLASH_WB_PCROP1ASR (FLASH_WB_REGS_ADDR + 0x24) -#define FLASH_WB_PCROP1AER (FLASH_WB_REGS_ADDR + 0x28) -#define FLASH_WB_WRP1AR (FLASH_WB_REGS_ADDR + 0x2C) -#define FLASH_WB_WRP1BR (FLASH_WB_REGS_ADDR + 0x30) -#define FLASH_WB_PCROP1BSR (FLASH_WB_REGS_ADDR + 0x34) -#define FLASH_WB_PCROP1BER (FLASH_WB_REGS_ADDR + 0x38) -#define FLASH_WB_IPCCBR (FLASH_WB_REGS_ADDR + 0x3C) -#define FLASH_WB_C2ACR (FLASH_WB_REGS_ADDR + 0x5C) -#define FLASH_WB_C2SR (FLASH_WB_REGS_ADDR + 0x60) -#define FLASH_WB_C2CR (FLASH_WB_REGS_ADDR + 0x64) -#define FLASH_WB_SFR (FLASH_WB_REGS_ADDR + 0x80) -#define FLASH_WB_SRRVR (FLASH_WB_REGS_ADDR + 0x84) +#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 -// WB Flash control register. -#define FLASH_WB_CR_STRT (16) /* Start */ -#define FLASH_WB_CR_OPTSTRT (17) /* Start writing option bytes */ -#define FLASH_WB_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ -#define FLASH_WB_CR_OPTLOCK (30) /* Option Lock */ -#define FLASH_WB_CR_LOCK (31) /* Lock */ -// WB Flash status register. -#define FLASH_WB_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define FLASH_WB_SR_PROGERR (3) /* Programming alignment error */ -#define FLASH_WB_SR_WRPERR (4) /* Write protection error */ -#define FLASH_WB_SR_PGAERR (5) /* Programming error */ -#define FLASH_WB_SR_BSY (16) /* Busy */ +// H7 Flash control register +#define FLASH_H7_CR_LOCK 0 +#define FLASH_H7_CR_PG 1 +#define FLASH_H7_CR_SER 2 +#define FLASH_H7_CR_BER 3 +#define FLASH_H7_CR_PSIZE 4 +#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7) +#define FLASH_H7_CR_SNB 8 +#define FLASH_H7_CR_SNB_MASK 0x700 -// 32L4 register base is at FLASH_REGS_ADDR (0x40022000) +// H7 Flash status register +#define FLASH_H7_SR_QW 2 +#define FLASH_H7_SR_WRPERR 17 +#define FLASH_H7_SR_PGSERR 18 +#define FLASH_H7_SR_STRBERR 19 +#define FLASH_H7_SR_ERROR_MASK \ + ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ + (1 << FLASH_H7_SR_WRPERR)) + +// == STM32L0/L1/L4/L5 == +// Lx Flash registers +#define FLASH_Lx_REGS_ADDR ((uint32_t)0x40023c00) +#define FLASH_Lx_ACR (FLASH_Lx_REGS_ADDR + 0x00) +#define FLASH_Lx_PECR (FLASH_Lx_REGS_ADDR + 0x04) +#define FLASH_Lx_PDKEYR (FLASH_Lx_REGS_ADDR + 0x08) +#define FLASH_Lx_PEKEYR (FLASH_Lx_REGS_ADDR + 0x0c) +#define FLASH_Lx_PRGKEYR (FLASH_Lx_REGS_ADDR + 0x10) +#define FLASH_Lx_OPTKEYR (FLASH_Lx_REGS_ADDR + 0x14) +#define FLASH_Lx_SR (FLASH_Lx_REGS_ADDR + 0x18) +#define FLASH_Lx_OBR (FLASH_Lx_REGS_ADDR + 0x1c) +#define FLASH_Lx_WRPR (FLASH_Lx_REGS_ADDR + 0x20) + +// == STM32L0 == +// L0 Flash registers +#define FLASH_L0_PEKEY1 0x89abcdef +#define FLASH_L0_PEKEY2 0x02030405 + +#define FLASH_L0_PRGKEY1 0x8c9daebf +#define FLASH_L0_PRGKEY2 0x13141516 + +#define FLASH_L0_OPTKEY1 0xFBEAD9C8 +#define FLASH_L0_OPTKEY2 0x24252627 + +#define FLASH_L0_REGS_ADDR ((uint32_t)0x40022000) + +#define FLASH_L0_PELOCK (0) +#define FLASH_L0_OPTLOCK (2) +#define FLASH_L0_OBL_LAUNCH (18) + +// L0 Flash status register +#define FLASH_L0_SR_ERROR_MASK 0x00013f00 +#define FLASH_L0_SR_WRPERR 8 +#define FLASH_L0_SR_PGAERR 9 +#define FLASH_L0_SR_NOTZEROERR 16 + +// == STM32L1 == +// L1 Flash registers +#define FLASH_L1_FPRG 10 +#define FLASH_L1_PROG 3 + +// L1 Flash status register +#define FLASH_L1_SR_ERROR_MASK 0x00003f00 +#define FLASH_L1_SR_WRPERR 8 +#define FLASH_L1_SR_PGAERR 9 + +// == STM32L4 == +// L4 Flash registers +// L4 register base is at FLASH_REGS_ADDR (0x40022000) #define FLASH_L4_KEYR (FLASH_REGS_ADDR + 0x08) -#define FLASH_L4_OPTKEYR (FLASH_REGS_ADDR + 0x0C) +#define FLASH_L4_OPTKEYR (FLASH_REGS_ADDR + 0x0c) #define FLASH_L4_SR (FLASH_REGS_ADDR + 0x10) #define FLASH_L4_CR (FLASH_REGS_ADDR + 0x14) #define FLASH_L4_OPTR (FLASH_REGS_ADDR + 0x20) +// L4 Flash status register #define FLASH_L4_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ #define FLASH_L4_SR_PROGERR 3 #define FLASH_L4_SR_WRPERR 4 #define FLASH_L4_SR_PGAERR 5 #define FLASH_L4_SR_BSY 16 +// L4 Flash control register #define FLASH_L4_CR_LOCK 31 /* Lock control register */ #define FLASH_L4_CR_OPTLOCK 30 /* Lock option bytes */ #define FLASH_L4_CR_PG 0 /* Program */ @@ -207,7 +333,8 @@ #define FLASH_L4_OPTR_DUALBANK 21 -// Flash registers common to STM32L5 series (RM0438, p. 241) +// == STM32L5 == (RM0438, p.241) +// L5 Flash registers #define FLASH_L5_REGS_ADDR ((uint32_t)0x40022000) #define FLASH_L5_ACR (FLASH_L5_REGS_ADDR + 0x00) #define FLASH_L5_NSKEYR (FLASH_L5_REGS_ADDR + 0x08) @@ -217,7 +344,7 @@ #define FLASH_L5_ECCR (FLASH_L5_REGS_ADDR + 0x30) #define FLASH_L5_OPTR (FLASH_L5_REGS_ADDR + 0x40) -// FLASH_NSCR (RM0438, p. 242) +// FLASH_NSCR control registers (RM0438, p. 242) #define FLASH_L5_NSCR_NSPG 0 /* Program */ #define FLASH_L5_NSCR_NSPER 1 /* Page erase */ #define FLASH_L5_NSCR_NSMER1 2 /* Bank 1 erase */ @@ -232,7 +359,7 @@ #define FLASH_L5_NSCR_OPTLOCK 30 /* Lock option bytes */ #define FLASH_L5_NSCR_NSLOCK 31 /* Lock control register */ -// FLASH_NSSR (RM0438, p. 241) +// FLASH_NSSR status register (RM0438, p. 241) #define FLASH_L5_NSSR_NSEOP 0 /* End of Operation */ #define FLASH_L5_NSSR_NSOPERR 1 #define FLASH_L5_NSSR_NSPROGERR 3 @@ -244,138 +371,41 @@ #define FLASH_L5_NSSR_BSY 16 /* Busy */ #define FLASH_L5_NSSR_ERROR_MASK (0x20fa) -// STM32L0x flash register base and offsets RM0090 - DM00031020.pdf -#define FLASH_L0_REGS_ADDR ((uint32_t)0x40022000) - -#define FLASH_L0_PELOCK (0) -#define FLASH_L0_OPTLOCK (2) -#define FLASH_L0_OBL_LAUNCH (18) - -#define FLASH_L0_SR_ERROR_MASK 0x00013F00 -#define FLASH_L0_SR_WRPERR 8 -#define FLASH_L0_SR_PGAERR 9 -#define FLASH_L0_SR_NOTZEROERR 16 - -#define FLASH_L1_SR_ERROR_MASK 0x00003F00 -#define FLASH_L1_SR_WRPERR 8 -#define FLASH_L1_SR_PGAERR 9 - -#define FLASH_ACR_OFF ((uint32_t)0x00) -#define FLASH_PECR_OFF ((uint32_t)0x04) -#define FLASH_PDKEYR_OFF ((uint32_t)0x08) -#define FLASH_PEKEYR_OFF ((uint32_t)0x0c) -#define FLASH_PRGKEYR_OFF ((uint32_t)0x10) -#define FLASH_OPTKEYR_OFF ((uint32_t)0x14) -#define FLASH_SR_OFF ((uint32_t)0x18) -#define FLASH_OBR_OFF ((uint32_t)0x1c) -#define FLASH_WRPR_OFF ((uint32_t)0x20) - -// STM32F7 -#define FLASH_F7_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F7_KEYR (FLASH_F7_REGS_ADDR + 0x04) -#define FLASH_F7_OPT_KEYR (FLASH_F7_REGS_ADDR + 0x08) -#define FLASH_F7_SR (FLASH_F7_REGS_ADDR + 0x0c) -#define FLASH_F7_CR (FLASH_F7_REGS_ADDR + 0x10) -#define FLASH_F7_OPTCR (FLASH_F7_REGS_ADDR + 0x14) -#define FLASH_F7_OPTCR1 (FLASH_F7_REGS_ADDR + 0x18) -#define FLASH_F7_OPTCR_LOCK 0 -#define FLASH_F7_OPTCR_START 1 -#define FLASH_F7_CR_STRT 16 -#define FLASH_F7_CR_LOCK 31 -#define FLASH_F7_CR_SER 1 -#define FLASH_F7_CR_SNB 3 -#define FLASH_F7_CR_SNB_MASK 0xf8 -#define FLASH_F7_SR_BSY 16 -#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ -#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ -#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ -#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ -#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ -#define FLASH_F7_SR_EOP 0 /* End of operation */ -#define FLASH_F7_OPTCR1_BOOT_ADD0 0 -#define FLASH_F7_OPTCR1_BOOT_ADD1 16 - -#define FLASH_F7_SR_ERROR_MASK \ - ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ - (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ - (1 << FLASH_F7_SR_OP_ERR)) - -// STM32F4 -#define FLASH_F4_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F4_KEYR (FLASH_F4_REGS_ADDR + 0x04) -#define FLASH_F4_OPT_KEYR (FLASH_F4_REGS_ADDR + 0x08) -#define FLASH_F4_SR (FLASH_F4_REGS_ADDR + 0x0c) -#define FLASH_F4_CR (FLASH_F4_REGS_ADDR + 0x10) -#define FLASH_F4_OPTCR (FLASH_F4_REGS_ADDR + 0x14) -#define FLASH_F4_OPTCR_LOCK 0 -#define FLASH_F4_OPTCR_START 1 -#define FLASH_F4_CR_STRT 16 -#define FLASH_F4_CR_LOCK 31 -#define FLASH_F4_CR_SER 1 -#define FLASH_F4_CR_SNB 3 -#define FLASH_F4_CR_SNB_MASK 0xf8 -#define FLASH_F4_SR_ERROR_MASK 0x000000F0 -#define FLASH_F4_SR_PGAERR 5 -#define FLASH_F4_SR_WRPERR 4 -#define FLASH_F4_SR_BSY 16 - -// STM32F2 -#define FLASH_F2_REGS_ADDR ((uint32_t)0x40023c00) -#define FLASH_F2_KEYR (FLASH_F2_REGS_ADDR + 0x04) -#define FLASH_F2_OPT_KEYR (FLASH_F2_REGS_ADDR + 0x08) -#define FLASH_F2_SR (FLASH_F2_REGS_ADDR + 0x0c) -#define FLASH_F2_CR (FLASH_F2_REGS_ADDR + 0x10) -#define FLASH_F2_OPT_CR (FLASH_F2_REGS_ADDR + 0x14) -#define FLASH_F2_OPT_LOCK_BIT (1u << 0) -#define FLASH_F2_CR_STRT 16 -#define FLASH_F2_CR_LOCK 31 - -#define FLASH_F2_CR_SER 1 -#define FLASH_F2_CR_SNB 3 -#define FLASH_F2_CR_SNB_MASK 0x78 -#define FLASH_F2_SR_BSY 16 - -// STM32H7xx -#define FLASH_H7_CR_LOCK 0 -#define FLASH_H7_CR_PG 1 -#define FLASH_H7_CR_SER 2 -#define FLASH_H7_CR_BER 3 -#define FLASH_H7_CR_PSIZE 4 -#define FLASH_H7_CR_START(chipid) (chipid == STM32_CHIPID_H7Ax ? 5 : 7) -#define FLASH_H7_CR_SNB 8 -#define FLASH_H7_CR_SNB_MASK 0x700 - -#define FLASH_H7_SR_QW 2 -#define FLASH_H7_SR_WRPERR 17 -#define FLASH_H7_SR_PGSERR 18 -#define FLASH_H7_SR_STRBERR 19 -#define FLASH_H7_SR_ERROR_MASK \ - ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ - (1 << FLASH_H7_SR_WRPERR)) - -#define FLASH_H7_OPTCR_OPTLOCK 0 -#define FLASH_H7_OPTCR_OPTSTART 1 -#define FLASH_H7_OPTCR_MER 4 - -#define FLASH_H7_OPTSR_OPT_BUSY 0 -#define FLASH_H7_OPTSR_OPTCHANGEERR 30 +// == STM32WB == (RM0434) +// WB Flash registers +#define FLASH_WB_REGS_ADDR ((uint32_t)0x58004000) +#define FLASH_WB_ACR (FLASH_WB_REGS_ADDR + 0x00) +#define FLASH_WB_KEYR (FLASH_WB_REGS_ADDR + 0x08) +#define FLASH_WB_OPT_KEYR (FLASH_WB_REGS_ADDR + 0x0c) +#define FLASH_WB_SR (FLASH_WB_REGS_ADDR + 0x10) +#define FLASH_WB_CR (FLASH_WB_REGS_ADDR + 0x14) +#define FLASH_WB_ECCR (FLASH_WB_REGS_ADDR + 0x18) +#define FLASH_WB_OPTR (FLASH_WB_REGS_ADDR + 0x20) +#define FLASH_WB_PCROP1ASR (FLASH_WB_REGS_ADDR + 0x24) +#define FLASH_WB_PCROP1AER (FLASH_WB_REGS_ADDR + 0x28) +#define FLASH_WB_WRP1AR (FLASH_WB_REGS_ADDR + 0x2c) +#define FLASH_WB_WRP1BR (FLASH_WB_REGS_ADDR + 0x30) +#define FLASH_WB_PCROP1BSR (FLASH_WB_REGS_ADDR + 0x34) +#define FLASH_WB_PCROP1BER (FLASH_WB_REGS_ADDR + 0x38) +#define FLASH_WB_IPCCBR (FLASH_WB_REGS_ADDR + 0x3c) +#define FLASH_WB_C2ACR (FLASH_WB_REGS_ADDR + 0x5c) +#define FLASH_WB_C2SR (FLASH_WB_REGS_ADDR + 0x60) +#define FLASH_WB_C2CR (FLASH_WB_REGS_ADDR + 0x64) +#define FLASH_WB_SFR (FLASH_WB_REGS_ADDR + 0x80) +#define FLASH_WB_SRRVR (FLASH_WB_REGS_ADDR + 0x84) -#define FLASH_H7_OPTCCR_CLR_OPTCHANGEERR 30 +// WB Flash control register +#define FLASH_WB_CR_STRT (16) /* Start */ +#define FLASH_WB_CR_OPTSTRT (17) /* Start writing option bytes */ +#define FLASH_WB_CR_OBL_LAUNCH (27) /* Forces the option byte loading */ +#define FLASH_WB_CR_OPTLOCK (30) /* Option Lock */ +#define FLASH_WB_CR_LOCK (31) /* Lock */ -#define FLASH_H7_REGS_ADDR ((uint32_t)0x52002000) -#define FLASH_H7_KEYR1 (FLASH_H7_REGS_ADDR + 0x04) -#define FLASH_H7_KEYR2 (FLASH_H7_REGS_ADDR + 0x104) -#define FLASH_H7_OPT_KEYR (FLASH_H7_REGS_ADDR + 0x08) -#define FLASH_H7_OPT_KEYR2 (FLASH_H7_REGS_ADDR + 0x108) -#define FLASH_H7_CR1 (FLASH_H7_REGS_ADDR + 0x0c) -#define FLASH_H7_CR2 (FLASH_H7_REGS_ADDR + 0x10c) -#define FLASH_H7_SR1 (FLASH_H7_REGS_ADDR + 0x10) -#define FLASH_H7_SR2 (FLASH_H7_REGS_ADDR + 0x110) -#define FLASH_H7_CCR1 (FLASH_H7_REGS_ADDR + 0x14) -#define FLASH_H7_CCR2 (FLASH_H7_REGS_ADDR + 0x114) -#define FLASH_H7_OPTCR (FLASH_H7_REGS_ADDR + 0x18) -#define FLASH_H7_OPTCR2 (FLASH_H7_REGS_ADDR + 0x118) -#define FLASH_H7_OPTSR_CUR (FLASH_H7_REGS_ADDR + 0x1c) -#define FLASH_H7_OPTCCR (FLASH_H7_REGS_ADDR + 0x24) +// WB Flash status register +#define FLASH_WB_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ +#define FLASH_WB_SR_PROGERR (3) /* Programming alignment error */ +#define FLASH_WB_SR_WRPERR (4) /* Write protection error */ +#define FLASH_WB_SR_PGAERR (5) /* Programming error */ +#define FLASH_WB_SR_BSY (16) /* Busy */ #endif // STM32FLASH_H_ diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index f2d60ce45..8e4b9a716 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -348,7 +348,8 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { if (type == RESET_AUTO) { /* Check if the S_RESET_ST bit is set in DHCSR * This means that a reset has occurred - * DDI0337E, p. 10-4, Debug Halting Control and Status Register */ + * DDI0337E, p. 10-4, Debug Halting Control and Status Register + */ dhcsr = 0; int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index dc33fdfcb..a74d88b16 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1154,7 +1154,7 @@ int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size // Check if size is aligned with a page, unless we want to completely erase the last page if ((addr + page_size) > (base_addr + size) && !align_size) { ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); - return -1; + return (-1); } if (stlink_erase_flash_page(sl, addr)) { diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index f0ce9be42..231a5d4d6 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -708,9 +708,9 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { } if (sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + write_flash_cr_psiz(sl, 3 /* 64bit */, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); + write_flash_cr_psiz(sl, 3 /* 64bit */, BANK_2); } } } else { From b1c4de647c9cbea8483e742262a30f1b308e881f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 3 May 2023 14:02:26 +0200 Subject: [PATCH 1373/1435] Naming convention for header includes --- inc/backend.h | 6 +++--- inc/stlink.h | 6 +++--- inc/stm32.h | 6 +++--- inc/stm32flash.h | 6 +++--- inc/version.h.in | 6 +++--- src/st-flash/flash.h | 6 +++--- src/st-util/gdb-remote.h | 6 +++--- src/st-util/gdb-server.h | 6 +++--- src/st-util/semihosting.h | 6 +++--- src/stlink-gui/gui.h | 6 +++--- src/stlink-lib/calculate.h | 6 +++--- src/stlink-lib/chipid.h | 6 +++--- src/stlink-lib/commands.h | 6 +++--- src/stlink-lib/common.h | 6 +++--- src/stlink-lib/common_flash.h | 6 +++--- src/stlink-lib/flash_loader.h | 6 +++--- src/stlink-lib/helper.h | 6 +++--- src/stlink-lib/libusb_settings.h | 6 +++--- src/stlink-lib/logging.h | 6 +++--- src/stlink-lib/map_file.h | 6 +++--- src/stlink-lib/md5.h | 6 +++--- src/stlink-lib/option_bytes.h | 6 +++--- src/stlink-lib/reg.h | 6 +++--- src/stlink-lib/sg.h | 6 +++--- src/stlink-lib/usb.h | 6 +++--- src/win32/getopt/getopt.h | 6 +++--- src/win32/mmap.h | 6 +++--- src/win32/sys_time.h | 6 +++--- src/win32/unistd/unistd.h | 6 +++--- 29 files changed, 87 insertions(+), 87 deletions(-) diff --git a/inc/backend.h b/inc/backend.h index abbf4bbf0..75c569fcf 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -1,5 +1,5 @@ -#ifndef BACKEND_H_ -#define BACKEND_H_ +#ifndef BACKEND_H +#define BACKEND_H typedef struct _stlink_backend { void (*close) (stlink_t * sl); @@ -34,4 +34,4 @@ int (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); } stlink_backend_t; -#endif // BACKEND_H_ +#endif // BACKEND_H diff --git a/inc/stlink.h b/inc/stlink.h index 2a192876f..b9379e03d 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -6,8 +6,8 @@ * regardless of how the backend does the work.... */ -#ifndef STLINK_H_ -#define STLINK_H_ +#ifndef STLINK_H +#define STLINK_H #include #include @@ -311,4 +311,4 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect); } #endif -#endif // STLINK_H_ +#endif // STLINK_H diff --git a/inc/stm32.h b/inc/stm32.h index ab80ff25e..f91269a34 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -4,8 +4,8 @@ * STM32-specific defines & identification parametres */ -#ifndef STM32_H_ -#define STM32_H_ +#ifndef STM32_H +#define STM32_H /* STM32 Cortex-M core ids (CPUTAPID) */ enum stm32_core_id { @@ -217,4 +217,4 @@ enum stm32_chipids { #define STM32L5_PWR_CR1 0x40007000 // RM0438, p. 93,324 #define STM32L5_PWR_CR1_VOS 9 -#endif // STM32_H_ +#endif // STM32_H diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 12d2f5a7b..5cb0ee1df 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -1,5 +1,5 @@ -#ifndef STM32FLASH_H_ -#define STM32FLASH_H_ +#ifndef STM32FLASH_H +#define STM32FLASH_H /* STM32Fx FPEC flash controller interface, PM0063 manual */ // STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev.2, Aug 2012) @@ -408,4 +408,4 @@ #define FLASH_WB_SR_PGAERR (5) /* Programming error */ #define FLASH_WB_SR_BSY (16) /* Busy */ -#endif // STM32FLASH_H_ +#endif // STM32FLASH_H diff --git a/inc/version.h.in b/inc/version.h.in index b5ccd6e31..39020c0ba 100644 --- a/inc/version.h.in +++ b/inc/version.h.in @@ -1,9 +1,9 @@ -#ifndef VERSION_H_ -#define VERSION_H_ +#ifndef VERSION_H +#define VERSION_H #define STLINK_VERSION "@PROJECT_VERSION@" #define STLINK_VERSION_MAJOR @PROJECT_VERSION_MAJOR@ #define STLINK_VERSION_MINOR @PROJECT_VERSION_MINOR@ #define STLINK_VERSION_PATCH @PROJECT_VERSION_PATCH@ -#endif // VERSION_H_ +#endif // VERSION_H diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index aab57878f..4aa6033f8 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -1,5 +1,5 @@ -#ifndef FLASH_H_ -#define FLASH_H_ +#ifndef FLASH_H +#define FLASH_H #include @@ -33,4 +33,4 @@ struct flash_opts { int flash_get_opts(struct flash_opts* o, int ac, char** av); -#endif // FLASH_H_ +#endif // FLASH_H diff --git a/src/st-util/gdb-remote.h b/src/st-util/gdb-remote.h index bcf1dbd01..03d6aea10 100644 --- a/src/st-util/gdb-remote.h +++ b/src/st-util/gdb-remote.h @@ -1,8 +1,8 @@ -#ifndef GDB_REMOTE_H_ -#define GDB_REMOTE_H_ +#ifndef GDB_REMOTE_H +#define GDB_REMOTE_H int gdb_send_packet(int fd, char* data); int gdb_recv_packet(int fd, char** buffer); int gdb_check_for_interrupt(int fd); -#endif // GDB_REMOTE_H_ +#endif // GDB_REMOTE_H diff --git a/src/st-util/gdb-server.h b/src/st-util/gdb-server.h index 3fbb16dad..03c37e416 100644 --- a/src/st-util/gdb-server.h +++ b/src/st-util/gdb-server.h @@ -1,5 +1,5 @@ -#ifndef GDB_SERVER_H_ -#define GDB_SERVER_H_ +#ifndef GDB_SERVER_H +#define GDB_SERVER_H #define STRINGIFY_inner(name) #name #define STRINGIFY(name) STRINGIFY_inner(name) @@ -8,4 +8,4 @@ #define DEBUG_LOGGING_LEVEL 100 #define DEFAULT_GDB_LISTEN_PORT 4242 -#endif // GDB_SERVER_H_ +#endif // GDB_SERVER_H diff --git a/src/st-util/semihosting.h b/src/st-util/semihosting.h index 2e34b4307..e7ddfcd97 100644 --- a/src/st-util/semihosting.h +++ b/src/st-util/semihosting.h @@ -1,5 +1,5 @@ -#ifndef SEMIHOSTING_H_ -#define SEMIHOSTING_H_ +#ifndef SEMIHOSTING_H +#define SEMIHOSTING_H #include @@ -31,4 +31,4 @@ int do_semihosting(stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret); -#endif // SEMIHOSTING_H_ +#endif // SEMIHOSTING_H diff --git a/src/stlink-gui/gui.h b/src/stlink-gui/gui.h index f29ee5031..08519ea56 100644 --- a/src/stlink-gui/gui.h +++ b/src/stlink-gui/gui.h @@ -1,5 +1,5 @@ -#ifndef GUI_H_ -#define GUI_H_ +#ifndef GUI_H +#define GUI_H #include @@ -89,4 +89,4 @@ struct _STlinkGUIClass { GType stlink_gui_get_type(void); int export_to_file(const char*filename, const struct mem_t flash_mem); -#endif // GUI_H_ +#endif // GUI_H diff --git a/src/stlink-lib/calculate.h b/src/stlink-lib/calculate.h index beb064297..64dfb51b2 100644 --- a/src/stlink-lib/calculate.h +++ b/src/stlink-lib/calculate.h @@ -4,12 +4,12 @@ * Calculation of sector numbers and pages */ -#ifndef CALCULATE_H_ -#define CALCULATE_H_ +#ifndef CALCULATE_H +#define CALCULATE_H uint32_t calculate_F4_sectornum(uint32_t); uint32_t calculate_F7_sectornum(uint32_t); uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, unsigned); uint32_t calculate_L4_page(stlink_t *, uint32_t); -#endif // CALCULATE_H_ +#endif // CALCULATE_H diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index b93a3f2d6..d6afc4525 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -1,5 +1,5 @@ -#ifndef CHIPID_H_ -#define CHIPID_H_ +#ifndef CHIPID_H +#define CHIPID_H #include #include @@ -24,4 +24,4 @@ struct stlink_chipid_params { struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); void init_chipids(char *dir_to_scan); -#endif // CHIPID_H_ +#endif // CHIPID_H diff --git a/src/stlink-lib/commands.h b/src/stlink-lib/commands.h index 4fa919858..5f0904971 100644 --- a/src/stlink-lib/commands.h +++ b/src/stlink-lib/commands.h @@ -1,5 +1,5 @@ -#ifndef COMMANDS_H_ -#define COMMANDS_H_ +#ifndef COMMANDS_H +#define COMMANDS_H enum stlink_commands { STLINK_GET_VERSION = 0xF1, @@ -54,4 +54,4 @@ enum stlink_dfu_commands { STLINK_DFU_EXIT = 0x07 }; -#endif // COMMANDS_H_ +#endif // COMMANDS_H diff --git a/src/stlink-lib/common.h b/src/stlink-lib/common.h index 902493610..dd6cf95b2 100644 --- a/src/stlink-lib/common.h +++ b/src/stlink-lib/common.h @@ -4,12 +4,12 @@ * General helper functions */ -#ifndef COMMON_H_ -#define COMMON_H_ +#ifndef COMMON_H +#define COMMON_H int check_file(stlink_t *, mapped_file_t *, stm32_addr_t); void md5_calculate(mapped_file_t *); void stlink_checksum(mapped_file_t *); void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); -#endif // COMMON_H_ +#endif // COMMON_H diff --git a/src/stlink-lib/common_flash.h b/src/stlink-lib/common_flash.h index 269f8196e..aa92b2143 100644 --- a/src/stlink-lib/common_flash.h +++ b/src/stlink-lib/common_flash.h @@ -4,8 +4,8 @@ * Flash operations */ -#ifndef COMMON_FLASH_H_ -#define COMMON_FLASH_H_ +#ifndef COMMON_FLASH_H +#define COMMON_FLASH_H void lock_flash(stlink_t *); void clear_flash_error(stlink_t *); @@ -25,4 +25,4 @@ void clear_flash_cr_pg(stlink_t *, unsigned); uint32_t read_flash_cr(stlink_t *, unsigned); uint32_t get_stm32l0_flash_base(stlink_t *); -#endif // COMMON_FLASH_H_ +#endif // COMMON_FLASH_H diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 781fab74a..51448395f 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -4,8 +4,8 @@ * Flash loader */ -#ifndef FLASH_LOADER_H_ -#define FLASH_LOADER_H_ +#ifndef FLASH_LOADER_H +#define FLASH_LOADER_H #include #include @@ -21,4 +21,4 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); -#endif // FLASH_LOADER_H_ +#endif // FLASH_LOADER_H diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index 58023aff2..cf45bbf43 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -1,8 +1,8 @@ -#ifndef HELPER_H_ -#define HELPER_H_ +#ifndef HELPER_H +#define HELPER_H unsigned time_ms(); int arg_parse_freq(const char *str); -#endif // HELPER_H_ +#endif // HELPER_H diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index 639f9e4a4..3777f720b 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -1,5 +1,5 @@ -#ifndef LIBUSB_SETTINGS_H_ -#define LIBUSB_SETTINGS_H_ +#ifndef LIBUSB_SETTINGS_H +#define LIBUSB_SETTINGS_H #include @@ -44,4 +44,4 @@ #error unsupported libusb version #endif -#endif // LIBUSB_SETTINGS_H_ +#endif // LIBUSB_SETTINGS_H diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index 7510d573e..893a02c24 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -2,8 +2,8 @@ * Ugly, low performance, configurable level, logging "framework" */ -#ifndef LOGGING_H_ -#define LOGGING_H_ +#ifndef LOGGING_H +#define LOGGING_H #ifdef __cplusplus extern "C" { @@ -45,4 +45,4 @@ int ugly_libusb_log_level(enum ugly_loglevel v); } #endif -#endif // LOGGING_H_ +#endif // LOGGING_H diff --git a/src/stlink-lib/map_file.h b/src/stlink-lib/map_file.h index d69f6c3b5..f50a201f0 100644 --- a/src/stlink-lib/map_file.h +++ b/src/stlink-lib/map_file.h @@ -4,8 +4,8 @@ * File mapping */ -#ifndef MAP_FILE_H_ -#define MAP_FILE_H_ +#ifndef MAP_FILE_H +#define MAP_FILE_H #ifndef O_BINARY #define O_BINARY 0 @@ -29,4 +29,4 @@ typedef struct mapped_file { int map_file(mapped_file_t *, const char *); void unmap_file(mapped_file_t *); -#endif // MAP_FILE_H_ +#endif // MAP_FILE_H diff --git a/src/stlink-lib/md5.h b/src/stlink-lib/md5.h index 7b853a4f6..23c5d971b 100644 --- a/src/stlink-lib/md5.h +++ b/src/stlink-lib/md5.h @@ -11,8 +11,8 @@ * MD5 hash function */ -#ifndef MD5_H_ -#define MD5_H_ +#ifndef MD5_H +#define MD5_H #pragma once @@ -71,4 +71,4 @@ void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */ */ void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */); -#endif // MD5_H_ \ No newline at end of file +#endif // MD5_H \ No newline at end of file diff --git a/src/stlink-lib/option_bytes.h b/src/stlink-lib/option_bytes.h index 481a69f0a..9c81fba8a 100644 --- a/src/stlink-lib/option_bytes.h +++ b/src/stlink-lib/option_bytes.h @@ -4,8 +4,8 @@ * Read and write option bytes and option control registers */ -#ifndef OPTION_BYTES_H_ -#define OPTION_BYTES_H_ +#ifndef OPTION_BYTES_H +#define OPTION_BYTES_H #include #include @@ -23,4 +23,4 @@ int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1); int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); -#endif // OPTION_BYTES_H_ \ No newline at end of file +#endif // OPTION_BYTES_H \ No newline at end of file diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/reg.h index 2046f8a6a..c2976d050 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/reg.h @@ -1,5 +1,5 @@ -#ifndef REG_H_ -#define REG_H_ +#ifndef REG_H +#define REG_H #define STLINK_REG_CM3_CPUID 0xE000ED00 @@ -123,4 +123,4 @@ #define STLINK_REG_CM7_ICIALLU 0xE000EF50 #define STLINK_REG_CM7_CCSIDR 0xE000ED80 -#endif // REG_H_ +#endif // REG_H diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index e30043fcc..5ba809f59 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -3,8 +3,8 @@ * Author: karl */ -#ifndef SG_H_ -#define SG_H_ +#ifndef SG_H +#define SG_H #include #include @@ -56,4 +56,4 @@ struct stlink_libsg { stlink_t* stlink_v1_open(const int verbose, int reset); -#endif // SG_H_ +#endif // SG_H diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index ff6f9088e..8c98bcaf4 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -3,8 +3,8 @@ * Author: karl */ -#ifndef USB_H_ -#define USB_H_ +#ifndef USB_H +#define USB_H #include @@ -70,4 +70,4 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); -#endif // USB_H_ +#endif // USB_H diff --git a/src/win32/getopt/getopt.h b/src/win32/getopt/getopt.h index 2a1bd735b..b1dd35ef1 100644 --- a/src/win32/getopt/getopt.h +++ b/src/win32/getopt/getopt.h @@ -1,5 +1,5 @@ -#ifndef GETOPT_H_ -#define GETOPT_H_ +#ifndef GETOPT_H +#define GETOPT_H #if defined(__cplusplus) extern "C" { @@ -38,4 +38,4 @@ int getopt_long(int argc, } #endif -#endif // GETOPT_H_ +#endif // GETOPT_H diff --git a/src/win32/mmap.h b/src/win32/mmap.h index ff01f4286..c6390aede 100644 --- a/src/win32/mmap.h +++ b/src/win32/mmap.h @@ -1,5 +1,5 @@ -#ifndef MMAP_H_ -#define MMAP_H_ +#ifndef MMAP_H +#define MMAP_H #ifdef STLINK_HAVE_SYS_MMAN_H #include @@ -18,4 +18,4 @@ int munmap(void *addr, size_t len); #endif // STLINK_HAVE_SYS_MMAN_H -#endif // MMAP_H_ +#endif // MMAP_H diff --git a/src/win32/sys_time.h b/src/win32/sys_time.h index cb767fc31..98ecaddfc 100644 --- a/src/win32/sys_time.h +++ b/src/win32/sys_time.h @@ -1,5 +1,5 @@ -#ifndef SYS_TIME_H_ -#define SYS_TIME_H_ +#ifndef SYS_TIME_H +#define SYS_TIME_H #ifdef STLINK_HAVE_SYS_TIME_H @@ -18,4 +18,4 @@ int gettimeofday(struct timeval *tv, struct timezone *tz); #endif // STLINK_HAVE_SYS_TIME_H -#endif // SYS_TIME_H_ +#endif // SYS_TIME_H diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index b8a3db746..5f2b5433b 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -1,5 +1,5 @@ -#ifndef UNISTD_H_ -#define UNISTD_H_ +#ifndef UNISTD_H +#define UNISTD_H /* * This file intended to serve as a drop-in replacement for unistd.h on Windows @@ -72,4 +72,4 @@ typedef unsigned __int64 uint64_t; int usleep(unsigned int waitTime); #endif -#endif // UNISTD_H_ +#endif // UNISTD_H From e4b2594b5a0700a43c68fcbe2aa0c91b5a62cec3 Mon Sep 17 00:00:00 2001 From: Andras Gemes Date: Fri, 5 May 2023 15:39:04 +0200 Subject: [PATCH 1374/1435] Fixed broken links --- README.md | 2 +- doc/tutorial.md | 2 +- doc/version_support.md | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 0e846b336..b6fca5fe2 100644 --- a/README.md +++ b/README.md @@ -49,7 +49,7 @@ The STlink toolset includes: ## Supported operating systems and hardware combinations -Currently known working MCU targets are listed in [devices_boards.md](doc/devices_boards.md). +Currently known working MCU targets are listed in [supported devices.md](). A list of supported operating can be found in [version_support.md](doc/version_support.md). diff --git a/doc/tutorial.md b/doc/tutorial.md index 7e87a7bd9..53ecabe7d 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -104,7 +104,7 @@ In this known example one finds the counterfeited "STM32F103C8T6" MCUs to identi In the following you find some hints on how to identify your chip and track down fraud: - [How to Detect STM32 Fakes](https://www.cnx-software.com/2020/03/22/how-to-detect-stm32-fakes/) -- [Confirmation by STMicroelectronics](https://www.mikrocontroller.net/attachment/442839/couterfeit_STM.png) (Marking: 991KA 93 MYS 807) +- [Confirmation by STMicroelectronics](https://www.mikrocontroller.net/attachment/442839/couterfeit_STM.PNG) (Marking: 991KA 93 MYS 807) - [STM32 Clones: The Good, The Bad And The Ugly](https://hackaday.com/2020/10/22/stm32-clones-the-good-the-bad-and-the-ugly/) However it appears that not all counterfeited parts cause problems during operation, but some are known to not even being able to execute a basic "blinky" example binary. Further there can be problems that may not even show up or affect you directly, but somewhen later in time (or maybe never). diff --git a/doc/version_support.md b/doc/version_support.md index 358e65fb9..022fb5e4d 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -1,4 +1,4 @@ -_Source:_ [pkgs.org](https://pkgs.org/search) - libusb, cmake, gtk, libgtk (as of Apr 2023) +_Source:_ [pkgs.org](https://pkgs.org) - libusb, cmake, gtk, libgtk (as of Apr 2023) ## Supported Operating Systems From 623570e3cc6e8b577c25dd8c23840ad688358f9c Mon Sep 17 00:00:00 2001 From: Andras Gemes Date: Sun, 7 May 2023 12:39:03 +0200 Subject: [PATCH 1375/1435] Renamed 'supported devices.md' to 'supported_devices.md' --- README.md | 2 +- doc/{supported devices.md => supported_devices.md} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename doc/{supported devices.md => supported_devices.md} (100%) diff --git a/README.md b/README.md index b6fca5fe2..e103ac301 100644 --- a/README.md +++ b/README.md @@ -49,7 +49,7 @@ The STlink toolset includes: ## Supported operating systems and hardware combinations -Currently known working MCU targets are listed in [supported devices.md](). +Currently known working MCU targets are listed in [supported_devices.md](doc/supported_devices.md). A list of supported operating can be found in [version_support.md](doc/version_support.md). diff --git a/doc/supported devices.md b/doc/supported_devices.md similarity index 100% rename from doc/supported devices.md rename to doc/supported_devices.md From 5e85fd063908f89499180c28fe5e9ba74868b272 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 8 May 2023 02:05:55 +0200 Subject: [PATCH 1376/1435] Replace data types with fixed width typedefs (C99) - Unified variable types (Closes #909) short --> int16_t unsigned short --> uint16_t int --> int32_t unsigned int --> uint32_t long --> int32_t unsigned long --> uint32_t long long --> int64_t unsigned long long --> uint64_t - Added missing header includes --- inc/backend.h | 58 ++++---- inc/stlink.h | 108 +++++++-------- inc/stm32.h | 2 + inc/stm32flash.h | 2 + src/st-flash/flash.c | 15 +- src/st-flash/flash.h | 10 +- src/st-flash/flash_opts.c | 15 +- src/st-info/info.c | 17 +-- src/st-trace/trace.c | 15 +- src/st-util/gdb-remote.c | 18 +-- src/st-util/gdb-remote.h | 8 +- src/st-util/gdb-server.c | 251 +++++++++++++++++----------------- src/st-util/semihosting.c | 57 ++++---- src/st-util/semihosting.h | 4 +- src/stlink-gui/gui.c | 8 +- src/stlink-gui/gui.h | 3 +- src/stlink-lib/calculate.c | 4 +- src/stlink-lib/calculate.h | 2 + src/stlink-lib/chipid.c | 11 +- src/stlink-lib/chipid.h | 2 + src/stlink-lib/common.c | 133 +++++++++--------- src/stlink-lib/common.h | 7 +- src/stlink-lib/common_flash.c | 108 ++++++++------- src/stlink-lib/common_flash.h | 10 +- src/stlink-lib/flash_loader.c | 67 ++++----- src/stlink-lib/flash_loader.h | 14 +- src/stlink-lib/helper.c | 13 +- src/stlink-lib/helper.h | 6 +- src/stlink-lib/logging.c | 9 +- src/stlink-lib/logging.h | 8 +- src/stlink-lib/map_file.c | 15 +- src/stlink-lib/map_file.h | 4 +- src/stlink-lib/md5.c | 3 +- src/stlink-lib/option_bytes.c | 116 ++++++++-------- src/stlink-lib/option_bytes.h | 22 +-- src/stlink-lib/read_write.c | 34 ++--- src/stlink-lib/sg.c | 126 ++++++++--------- src/stlink-lib/sg.h | 16 ++- src/stlink-lib/usb.c | 238 ++++++++++++++++---------------- src/stlink-lib/usb.h | 19 +-- src/win32/getopt/getopt.c | 23 ++-- src/win32/getopt/getopt.h | 18 +-- src/win32/mmap.c | 9 +- src/win32/mmap.h | 6 +- src/win32/sys_time.c | 10 +- src/win32/sys_time.h | 8 +- src/win32/unistd/unistd.h | 5 +- src/win32/win32_socket.c | 40 +++--- src/win32/win32_socket.h | 24 ++-- tests/flash.c | 9 +- tests/sg.c | 7 +- tests/usb.c | 7 +- 52 files changed, 908 insertions(+), 836 deletions(-) diff --git a/inc/backend.h b/inc/backend.h index 75c569fcf..a9a7d6e03 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -1,37 +1,39 @@ #ifndef BACKEND_H #define BACKEND_H +#include + typedef struct _stlink_backend { void (*close) (stlink_t * sl); - int (*exit_debug_mode) (stlink_t * sl); - int (*enter_swd_mode) (stlink_t * sl); - int (*enter_jtag_mode) (stlink_t * stl); - int (*exit_dfu_mode) (stlink_t * stl); - int (*core_id) (stlink_t * stl); - int (*reset) (stlink_t * stl); - int (*jtag_reset) (stlink_t * stl, int value); - int (*run) (stlink_t * stl, enum run_type type); - int (*status) (stlink_t * stl); - int (*version) (stlink_t *sl); - int (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); - int (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); - int (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); - int (*read_all_regs) (stlink_t *sl, struct stlink_reg * regp); - int (*read_reg) (stlink_t *sl, int r_idx, struct stlink_reg * regp); - int (*read_all_unsupported_regs) (stlink_t *sl, struct stlink_reg *regp); - int (*read_unsupported_reg) (stlink_t *sl, int r_idx, struct stlink_reg *regp); - int (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, struct stlink_reg *regp); - int (*write_reg) (stlink_t *sl, uint32_t reg, int idx); - int (*step) (stlink_t * stl); - int (*current_mode) (stlink_t * stl); - int (*force_debug) (stlink_t *sl); + int32_t (*exit_debug_mode) (stlink_t * sl); + int32_t (*enter_swd_mode) (stlink_t * sl); + int32_t (*enter_jtag_mode) (stlink_t * stl); + int32_t (*exit_dfu_mode) (stlink_t * stl); + int32_t (*core_id) (stlink_t * stl); + int32_t (*reset) (stlink_t * stl); + int32_t (*jtag_reset) (stlink_t * stl, int32_t value); + int32_t (*run) (stlink_t * stl, enum run_type type); + int32_t (*status) (stlink_t * stl); + int32_t (*version) (stlink_t *sl); + int32_t (*read_debug32) (stlink_t *sl, uint32_t addr, uint32_t *data); + int32_t (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + int32_t (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data); + int32_t (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len); + int32_t (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len); + int32_t (*read_all_regs) (stlink_t *sl, struct stlink_reg * regp); + int32_t (*read_reg) (stlink_t *sl, int32_t r_idx, struct stlink_reg * regp); + int32_t (*read_all_unsupported_regs) (stlink_t *sl, struct stlink_reg *regp); + int32_t (*read_unsupported_reg) (stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); + int32_t (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int32_t idx, struct stlink_reg *regp); + int32_t (*write_reg) (stlink_t *sl, uint32_t reg, int32_t idx); + int32_t (*step) (stlink_t * stl); + int32_t (*current_mode) (stlink_t * stl); + int32_t (*force_debug) (stlink_t *sl); int32_t (*target_voltage) (stlink_t *sl); - int (*set_swdclk) (stlink_t * stl, int freq_khz); - int (*trace_enable) (stlink_t * sl, uint32_t frequency); - int (*trace_disable) (stlink_t * sl); - int (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); + int32_t (*set_swdclk) (stlink_t * stl, int32_t freq_khz); + int32_t (*trace_enable) (stlink_t * sl, uint32_t frequency); + int32_t (*trace_disable) (stlink_t * sl); + int32_t (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); } stlink_backend_t; #endif // BACKEND_H diff --git a/inc/stlink.h b/inc/stlink.h index b9379e03d..ca07a6a89 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -196,17 +196,17 @@ struct _stlink { unsigned char c_buf[C_BUF_LEN]; // data transferred from or to device unsigned char q_buf[Q_BUF_LEN]; - int q_len; + int32_t q_len; // transport layer verboseness: 0 for no debug info, 10 for lots - int verbose; - int opt; + int32_t verbose; + int32_t opt; uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram enum target_state core_stat; // set by stlink_status() char serial[STLINK_SERIAL_BUFFER_SIZE]; - int freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR + int32_t freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR enum stm32_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STM32_FLASH_TYPE_xx @@ -236,67 +236,67 @@ struct _stlink { uint32_t max_trace_freq; // set by stlink_open_usb() }; -int stlink_enter_swd_mode(stlink_t *sl); -int stlink_enter_jtag_mode(stlink_t *sl); -int stlink_exit_debug_mode(stlink_t *sl); -int stlink_exit_dfu_mode(stlink_t *sl); +int32_t stlink_enter_swd_mode(stlink_t *sl); +int32_t stlink_enter_jtag_mode(stlink_t *sl); +int32_t stlink_exit_debug_mode(stlink_t *sl); +int32_t stlink_exit_dfu_mode(stlink_t *sl); void stlink_close(stlink_t *sl); -int stlink_core_id(stlink_t *sl); -int stlink_reset(stlink_t *sl, enum reset_type type); -int stlink_run(stlink_t *sl, enum run_type type); -int stlink_status(stlink_t *sl); -int stlink_version(stlink_t *sl); -int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); -int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); -int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); -int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); -int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); -int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); -int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); -int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); -int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp); -int stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, struct stlink_reg *regp); -int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx); -int stlink_step(stlink_t *sl); -int stlink_current_mode(stlink_t *sl); -int stlink_force_debug(stlink_t *sl); -int stlink_target_voltage(stlink_t *sl); -int stlink_set_swdclk(stlink_t *sl, int freq_khz); -int stlink_trace_enable(stlink_t* sl, uint32_t frequency); -int stlink_trace_disable(stlink_t* sl); -int stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); -int stlink_erase_flash_mass(stlink_t* sl); -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size); -int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); -int stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); +int32_t stlink_core_id(stlink_t *sl); +int32_t stlink_reset(stlink_t *sl, enum reset_type type); +int32_t stlink_run(stlink_t *sl, enum run_type type); +int32_t stlink_status(stlink_t *sl); +int32_t stlink_version(stlink_t *sl); +int32_t stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); +int32_t stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); +int32_t stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); +int32_t stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); +int32_t stlink_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t stlink_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int32_t r_idx, struct stlink_reg *regp); +int32_t stlink_write_reg(stlink_t *sl, uint32_t reg, int32_t idx); +int32_t stlink_step(stlink_t *sl); +int32_t stlink_current_mode(stlink_t *sl); +int32_t stlink_force_debug(stlink_t *sl); +int32_t stlink_target_voltage(stlink_t *sl); +int32_t stlink_set_swdclk(stlink_t *sl, int32_t freq_khz); +int32_t stlink_trace_enable(stlink_t* sl, uint32_t frequency); +int32_t stlink_trace_disable(stlink_t* sl); +int32_t stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); +int32_t stlink_erase_flash_mass(stlink_t* sl); +int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size); +int32_t stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); +int32_t stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); uint8_t stlink_get_erased_pattern(stlink_t *sl); -int stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); -int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); -int stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); -int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); -int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); +int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); +int32_t stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); +int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); +int32_t stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); +int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); -//int stlink_chip_id(stlink_t *sl, uint32_t *chip_id); -int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); +//int32_t stlink_chip_id(stlink_t *sl, uint32_t *chip_id); +int32_t stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); -int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); +int32_t stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); -int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); -int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); -uint16_t read_uint16(const unsigned char *c, const int pt); +int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); +int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); +uint16_t read_uint16(const unsigned char *c, const int32_t pt); //void stlink_core_stat(stlink_t *sl); void stlink_print_data(stlink_t *sl); -unsigned int is_bigendian(void); -uint32_t read_uint32(const unsigned char *c, const int pt); +uint32_t is_bigendian(void); +uint32_t read_uint32(const unsigned char *c, const int32_t pt); void write_uint32(unsigned char* buf, uint32_t ui); void write_uint16(unsigned char* buf, uint16_t ui); bool stlink_is_core_halted(stlink_t *sl); -int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); -int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); -int stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); -int stlink_load_device_params(stlink_t *sl); +int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); +int32_t write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); +int32_t stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); +int32_t stlink_load_device_params(stlink_t *sl); -int stlink_target_connect(stlink_t *sl, enum connect_type connect); +int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect); #include #include diff --git a/inc/stm32.h b/inc/stm32.h index f91269a34..eee1b0433 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -7,6 +7,8 @@ #ifndef STM32_H #define STM32_H +#include + /* STM32 Cortex-M core ids (CPUTAPID) */ enum stm32_core_id { STM32_CORE_ID_M0_SWD = 0x0bb11477, // (RM0091 Section 32.5.3) F0 SW-DP diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 5cb0ee1df..69c6206ee 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -1,6 +1,8 @@ #ifndef STM32FLASH_H #define STM32FLASH_H +#include + /* STM32Fx FPEC flash controller interface, PM0063 manual */ // STM32F05x is identical, based on RM0091 (DM00031936, Doc ID 018940 Rev.2, Aug 2012) #define FLASH_REGS_ADDR 0x40022000 diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index bbb52d80c..6b4a10cfc 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -1,6 +1,7 @@ /* Simple wrapper around the stlink_flash_write function */ #include +#include #include #include @@ -20,7 +21,7 @@ static stlink_t *connected_stlink = NULL; -static void cleanup(int signum) { +static void cleanup(int32_t signum) { (void)signum; if (connected_stlink) { // switch back to mass storage mode before closing @@ -52,10 +53,10 @@ static void usage(void) { puts("example write option control register1 byte: ./st-flash --area=optcr1 write 0xXXXXXXXX"); } -int main(int ac, char** av) { +int32_t main(int32_t ac, char** av) { stlink_t* sl = NULL; struct flash_opts o; - int err = -1; + int32_t err = -1; uint8_t * mem = NULL; o.size = 0; @@ -82,7 +83,7 @@ int main(int ac, char** av) { if ( o.flash_size != 0u && o.flash_size != sl->flash_size ) { sl->flash_size = o.flash_size; - printf("Forcing flash size: --flash=0x%08X\n", (unsigned int)sl->flash_size); + printf("Forcing flash size: --flash=0x%08X\n", (uint32_t)sl->flash_size); } sl->verbose = o.log_level; @@ -222,8 +223,8 @@ int main(int ac, char** av) { } else if (o.area == FLASH_OPTION_BYTES) { size_t remaining_option_length = sl->option_size / 4; DLOG("@@@@ Read %u (%#x) option bytes from %#10x\n", - (unsigned)remaining_option_length, - (unsigned)remaining_option_length, + (uint32_t)remaining_option_length, + (uint32_t)remaining_option_length, sl->option_base); uint32_t option_byte = 0; @@ -232,7 +233,7 @@ int main(int ac, char** av) { printf("could not read option bytes (%d)\n", err); goto on_error; } else if (NULL != o.filename) { - int fd = open(o.filename, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); + int32_t fd = open(o.filename, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); if (fd == -1) { fprintf(stderr, "open(%s) == -1\n", o.filename); goto on_error; diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index 4aa6033f8..1a509a660 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -18,19 +18,19 @@ struct flash_opts { const char* filename; stm32_addr_t addr; size_t size; - int reset; - int log_level; + int32_t reset; + int32_t log_level; enum flash_format format; enum flash_area area; uint32_t val; size_t flash_size; // --flash=n[k, M] - int opt; // enable empty tail data drop optimization - int freq; // --freq=n[k, M] frequency of JTAG/SWD + int32_t opt; // enable empty tail data drop optimization + int32_t freq; // --freq=n[k, M] frequency of JTAG/SWD enum connect_type connect; }; #define FLASH_OPTS_INITIALIZER {0, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} -int flash_get_opts(struct flash_opts* o, int ac, char** av); +int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av); #endif // FLASH_H diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 984156aa3..e133d52c7 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -1,3 +1,4 @@ +#include #include #include #include @@ -18,7 +19,7 @@ static bool starts_with(const char * str, const char * prefix) { // support decimal, hexadecimal, octal, binary format like 0xff 12 1k 1M, 0b1001 // negative numbers are not supported // return 0 if success else return -1 -static int get_long_integer_from_char_array (const char *const str, uint64_t *read_value) { +static int32_t get_long_integer_from_char_array (const char *const str, uint64_t *read_value) { uint64_t value; char *tail; @@ -50,9 +51,9 @@ static int get_long_integer_from_char_array (const char *const str, uint64_t *re // support decimal, hexadecimal, octal, binary format like 0xff 12 1k 1M, 0b1001 // negative numbers are not supported // return 0 if success else return -1 -static int get_integer_from_char_array (const char *const str, uint32_t *read_value) { +static int32_t get_integer_from_char_array (const char *const str, uint32_t *read_value) { uint64_t value; - int result = get_long_integer_from_char_array (str, &value); + int32_t result = get_long_integer_from_char_array (str, &value); if (result != 0) { return(result); @@ -65,24 +66,24 @@ static int get_integer_from_char_array (const char *const str, uint32_t *read_va } } -static int invalid_args(const char *expected) { +static int32_t invalid_args(const char *expected) { fprintf(stderr, "*** Error: Expected args for this command: %s\n", expected); return(-1); } -static int bad_arg(const char *arg) { +static int32_t bad_arg(const char *arg) { fprintf(stderr, "*** Error: Invalid value for %s\n", arg); return(-1); } -int flash_get_opts(struct flash_opts* o, int ac, char** av) { +int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { // defaults memset(o, 0, sizeof(*o)); o->log_level = STND_LOG_LEVEL; // options - int result; + int32_t result; while (ac >= 1) { if (strcmp(av[0], "--version") == 0) { diff --git a/src/st-info/info.c b/src/st-info/info.c index 9963606e3..86a1c2d8f 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -1,4 +1,5 @@ #include +#include #include #include #include @@ -42,26 +43,26 @@ static void stlink_print_info(stlink_t *sl) { if (params) { printf(" dev-type: %s\n", params->dev_type); } } -static void stlink_probe(enum connect_type connect, int freq) { +static void stlink_probe(enum connect_type connect, int32_t freq) { stlink_t **stdevs; size_t size; size = stlink_probe_usb(&stdevs, connect, freq); - printf("Found %u stlink programmers\n", (unsigned int)size); + printf("Found %u stlink programmers\n", (uint32_t)size); for (size_t n = 0; n < size; n++) { - if (size > 1) printf("%u.\n", (unsigned int)n+1); + if (size > 1) printf("%u.\n", (uint32_t)n+1); stlink_print_info(stdevs[n]); } stlink_probe_usb_free(&stdevs, size); } -static int print_data(int ac, char **av) { +static int32_t print_data(int32_t ac, char **av) { stlink_t* sl = NULL; enum connect_type connect = CONNECT_NORMAL; - int freq = 0; + int32_t freq = 0; if (strcmp(av[1], "--version") == 0) { printf("v%s\n", STLINK_VERSION); @@ -70,7 +71,7 @@ static int print_data(int ac, char **av) { init_chipids(STLINK_CHIPS_DIR); - for (int i=2; i #include #include +#include #include #include #include @@ -41,7 +42,7 @@ typedef struct { bool show_help; bool show_version; - int logging_level; + int32_t logging_level; uint32_t core_frequency; uint32_t trace_frequency; bool reset_board; @@ -144,7 +145,7 @@ static bool parse_frequency(char* text, uint32_t* result) return true; } -bool parse_options(int argc, char **argv, st_settings_t *settings) { +bool parse_options(int32_t argc, char **argv, st_settings_t *settings) { static struct option long_options[] = { {"help", no_argument, NULL, 'h'}, @@ -157,8 +158,8 @@ bool parse_options(int argc, char **argv, st_settings_t *settings) { {"force", no_argument, NULL, 'f'}, {0, 0, 0, 0}, }; - int option_index = 0; - int c; + int32_t option_index = 0; + int32_t c; bool error = false; settings->show_help = false; @@ -421,7 +422,7 @@ static trace_state update_trace(st_trace_t *trace, uint8_t c) { static bool read_trace(stlink_t *stlink, st_trace_t *trace) { uint8_t buffer[STLINK_TRACE_BUF_LEN]; - int length = stlink_trace_read(stlink, buffer, sizeof(buffer)); + int32_t length = stlink_trace_read(stlink, buffer, sizeof(buffer)); if (length < 0) { ELOG("Error reading trace (%d)\n", length); @@ -441,7 +442,7 @@ static bool read_trace(stlink_t *stlink, st_trace_t *trace) { trace->state = TRACE_STATE_UNKNOWN; } - for (int i = 0; i < length; i++) { + for (int32_t i = 0; i < length; i++) { trace->state = update_trace(trace, buffer[i]); } @@ -531,7 +532,7 @@ static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, WLOG("****\n"); } -int main(int argc, char **argv) { +int32_t main(int32_t argc, char **argv) { #if defined(_WIN32) SetConsoleCtrlHandler((PHANDLER_ROUTINE)CtrlHandler, TRUE); #else diff --git a/src/st-util/gdb-remote.c b/src/st-util/gdb-remote.c index bdf8afd24..7d0f2c731 100644 --- a/src/st-util/gdb-remote.c +++ b/src/st-util/gdb-remote.c @@ -5,8 +5,8 @@ #include #include -#include #include +#include #if defined(_WIN32) #include @@ -19,9 +19,9 @@ static const char hex[] = "0123456789abcdef"; -int gdb_send_packet(int fd, char* data) { - unsigned int data_length = (unsigned int)strlen(data); - int length = data_length + 4; +int32_t gdb_send_packet(int32_t fd, char* data) { + uint32_t data_length = (uint32_t)strlen(data); + int32_t length = data_length + 4; char* packet = malloc(length); // '$' data (hex) '#' cksum (hex) memset(packet, 0, length); @@ -30,7 +30,7 @@ int gdb_send_packet(int fd, char* data) { uint8_t cksum = 0; - for (unsigned int i = 0; i < data_length; i++) { + for (uint32_t i = 0; i < data_length; i++) { packet[i + 1] = data[i]; cksum += data[i]; } @@ -61,12 +61,12 @@ int gdb_send_packet(int fd, char* data) { #define ALLOC_STEP 1024 -int gdb_recv_packet(int fd, char** buffer) { - unsigned packet_size = ALLOC_STEP + 1, packet_idx = 0; +int32_t gdb_recv_packet(int32_t fd, char** buffer) { + uint32_t packet_size = ALLOC_STEP + 1, packet_idx = 0; uint8_t cksum = 0; char recv_cksum[3] = {0}; char* packet_buffer = malloc(packet_size); - unsigned state; + uint32_t state; if (packet_buffer == NULL) { return(-2); @@ -167,7 +167,7 @@ int gdb_recv_packet(int fd, char** buffer) { * As we use the mode with ACK, in a (very unlikely) situation of a packet lost * because of this skipping, it will be resent anyway. */ -int gdb_check_for_interrupt(int fd) { +int32_t gdb_check_for_interrupt(int32_t fd) { struct pollfd pfd; pfd.fd = fd; pfd.events = POLLIN; diff --git a/src/st-util/gdb-remote.h b/src/st-util/gdb-remote.h index 03d6aea10..ec990455b 100644 --- a/src/st-util/gdb-remote.h +++ b/src/st-util/gdb-remote.h @@ -1,8 +1,10 @@ #ifndef GDB_REMOTE_H #define GDB_REMOTE_H -int gdb_send_packet(int fd, char* data); -int gdb_recv_packet(int fd, char** buffer); -int gdb_check_for_interrupt(int fd); +#include + +int32_t gdb_send_packet(int32_t fd, char* data); +int32_t gdb_recv_packet(int32_t fd, char** buffer); +int32_t gdb_check_for_interrupt(int32_t fd); #endif // GDB_REMOTE_H diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 99cc0170b..557a24f5f 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -57,18 +58,18 @@ static const char hex[] = "0123456789abcdef"; typedef struct _st_state_t { // things from command line, bleh - int logging_level; - int listen_port; - int persistent; + int32_t logging_level; + int32_t listen_port; + int32_t persistent; enum connect_type connect_mode; - int freq; + int32_t freq; char serialnumber[STLINK_SERIAL_BUFFER_SIZE]; bool semihosting; const char* current_memory_map; } st_state_t; -int serve(stlink_t *sl, st_state_t *st); +int32_t serve(stlink_t *sl, st_state_t *st); char* make_memory_map(stlink_t *sl); static void init_cache(stlink_t *sl); @@ -81,7 +82,7 @@ static void _cleanup() { } } -static void cleanup(int signum) { +static void cleanup(int32_t signum) { printf("Receive signal %i. Exiting...\n", signum); _cleanup(); exit(1); @@ -90,13 +91,13 @@ static void cleanup(int signum) { #if defined(_WIN32) BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { - printf("Receive signal %i. Exiting...\r\n", (int)fdwCtrlType); + printf("Receive signal %i. Exiting...\r\n", (int32_t)fdwCtrlType); _cleanup(); return FALSE; } #endif -int parse_options(int argc, char** argv, st_state_t *st) { +int32_t parse_options(int32_t argc, char** argv, st_state_t *st) { static struct option long_options[] = { {"help", no_argument, NULL, 'h'}, {"verbose", optional_argument, NULL, 'v'}, @@ -139,9 +140,9 @@ int parse_options(int argc, char** argv, st_state_t *st) { ; - int option_index = 0; - int c; - int q; + int32_t option_index = 0; + int32_t c; + int32_t q; while ((c = getopt_long(argc, argv, "hv::p:mn", long_options, &option_index)) != -1) switch (c) { @@ -211,7 +212,7 @@ int parse_options(int argc, char** argv, st_state_t *st) { return(0); } -int main(int argc, char** argv) { +int32_t main(int32_t argc, char** argv) { stlink_t *sl = NULL; st_state_t state; memset(&state, 0, sizeof(state)); @@ -564,42 +565,42 @@ char* make_memory_map(stlink_t *sl) { strcpy(map, memory_map_template_F4_DE); } else if (sl->core_id == STM32_CORE_ID_M7F_SWD) { snprintf(map, sz, memory_map_template_F7, - (unsigned int)sl->sram_size); + (uint32_t)sl->sram_size); } else if (sl->chip_id == STM32_CHIPID_H74xxx) { snprintf(map, sz, memory_map_template_H7, - (unsigned int)sl->flash_size, - (unsigned int)sl->flash_pgsz); + (uint32_t)sl->flash_size, + (uint32_t)sl->flash_pgsz); } else if (sl->chip_id == STM32_CHIPID_F4_HD) { strcpy(map, memory_map_template_F4_HD); } else if (sl->chip_id == STM32_CHIPID_F2) { snprintf(map, sz, memory_map_template_F2, - (unsigned int)sl->flash_size, - (unsigned int)sl->sram_size, - (unsigned int)sl->flash_size - 0x20000, - (unsigned int)sl->sys_base, - (unsigned int)sl->sys_size); + (uint32_t)sl->flash_size, + (uint32_t)sl->sram_size, + (uint32_t)sl->flash_size - 0x20000, + (uint32_t)sl->sys_base, + (uint32_t)sl->sys_size); } else if ((sl->chip_id == STM32_CHIPID_L4) || (sl->chip_id == STM32_CHIPID_L43x_L44x) || (sl->chip_id == STM32_CHIPID_L45x_L46x)) { snprintf(map, sz, memory_map_template_L4, - (unsigned int)sl->flash_size, - (unsigned int)sl->flash_size); + (uint32_t)sl->flash_size, + (uint32_t)sl->flash_size); } else if (sl->chip_id == STM32_CHIPID_L496x_L4A6x) { snprintf(map, sz, memory_map_template_L496, - (unsigned int)sl->flash_size, - (unsigned int)sl->flash_size); + (uint32_t)sl->flash_size, + (uint32_t)sl->flash_size); } else if (sl->chip_id == STM32_CHIPID_H72x) { snprintf(map, sz, memory_map_template_H72x3x, - (unsigned int)sl->flash_size, - (unsigned int)sl->flash_pgsz); + (uint32_t)sl->flash_size, + (uint32_t)sl->flash_pgsz); } else { snprintf(map, sz, memory_map_template, - (unsigned int)sl->flash_size, - (unsigned int)sl->sram_size, - (unsigned int)sl->flash_size, - (unsigned int)sl->flash_pgsz, - (unsigned int)sl->sys_base, - (unsigned int)sl->sys_size); + (uint32_t)sl->flash_size, + (uint32_t)sl->sram_size, + (uint32_t)sl->flash_size, + (uint32_t)sl->flash_pgsz, + (uint32_t)sl->sys_base, + (uint32_t)sl->sys_size); } return(map); @@ -627,14 +628,14 @@ static void init_data_watchpoints(stlink_t *sl) { stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, data); // make sure all watchpoints are cleared - for (int i = 0; i < DATA_WATCH_NUM; i++) { + for (int32_t i = 0; i < DATA_WATCH_NUM; i++) { data_watches[i].fun = WATCHDISABLED; stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), 0); } } -static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr, unsigned int len) { - int i = 0; +static int32_t add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr, uint32_t len) { + int32_t i = 0; uint32_t mask, dummy; // computer mask @@ -678,8 +679,8 @@ static int add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t addr return(-1); } -static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { - int i; +static int32_t delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { + int32_t i; for (i = 0; i < DATA_WATCH_NUM; i++) { if ((data_watches[i].addr == addr) && (data_watches[i].fun != WATCHDISABLED)) { @@ -697,9 +698,9 @@ static int delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { return(-1); } -static int code_break_num; -static int code_lit_num; -static int code_break_rev; +static int32_t code_break_num; +static int32_t code_lit_num; +static int32_t code_break_rev; #define CODE_BREAK_NUM_MAX 15 #define CODE_BREAK_LOW 0x01 #define CODE_BREAK_HIGH 0x02 @@ -709,13 +710,13 @@ static int code_break_rev; struct code_hw_breakpoint { stm32_addr_t addr; - int type; + int32_t type; }; static struct code_hw_breakpoint code_breaks[CODE_BREAK_NUM_MAX]; static void init_code_breakpoints(stlink_t *sl) { - unsigned int val; + uint32_t val; memset(sl->q_buf, 0, 4); stlink_write_debug32(sl, STLINK_REG_CM3_FP_CTRL, 0x03 /* KEY | ENABLE */); stlink_read_debug32(sl, STLINK_REG_CM3_FP_CTRL, &val); @@ -732,22 +733,22 @@ static void init_code_breakpoints(stlink_t *sl) { stlink_write_debug32(sl, STLINK_REG_CM7_FP_LAR, STLINK_REG_CM7_FP_LAR_KEY); } - for (int i = 0; i < code_break_num; i++) { + for (int32_t i = 0; i < code_break_num; i++) { code_breaks[i].type = 0; stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(i), 0); } } -static int has_breakpoint(stm32_addr_t addr) { - for (int i = 0; i < code_break_num; i++) +static int32_t has_breakpoint(stm32_addr_t addr) { + for (int32_t i = 0; i < code_break_num; i++) if (code_breaks[i].addr == addr) { return(1); } return(0); } -static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { +static int32_t update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int32_t set) { uint32_t mask; - int type; + int32_t type; stm32_addr_t fpb_addr; if (addr & 1) { @@ -763,8 +764,8 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { fpb_addr = addr; } - int id = -1; - for (int i = 0; i < code_break_num; i++) + int32_t id = -1; + for (int32_t i = 0; i < code_break_num; i++) if (fpb_addr == code_breaks[i].addr || (set && code_breaks[i].type == 0)) { id = i; break; @@ -802,7 +803,7 @@ static int update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int set) { struct flash_block { stm32_addr_t addr; - unsigned length; + uint32_t length; uint8_t* data; struct flash_block* next; @@ -810,7 +811,7 @@ struct flash_block { static struct flash_block* flash_root; -static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { +static int32_t flash_add_block(stm32_addr_t addr, uint32_t length, stlink_t *sl) { if (addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) { ELOG("flash_add_block: incorrect bounds\n"); @@ -835,8 +836,8 @@ static int flash_add_block(stm32_addr_t addr, unsigned length, stlink_t *sl) { return(0); } -static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { - unsigned int fit_blocks = 0, fit_length = 0; +static int32_t flash_populate(stm32_addr_t addr, uint8_t* data, uint32_t length) { + uint32_t fit_blocks = 0, fit_length = 0; for (struct flash_block* fb = flash_root; fb; fb = fb->next) { /* @@ -848,13 +849,13 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { * a < Y && b > x */ - unsigned X = fb->addr, Y = fb->addr + fb->length; - unsigned a = addr, b = addr + length; + uint32_t X = fb->addr, Y = fb->addr + fb->length; + uint32_t a = addr, b = addr + length; if (a < Y && b > X) { // from start of the block - unsigned start = (a > X ? a : X) - X; - unsigned end = (b > Y ? Y : b) - X; + uint32_t start = (a > X ? a : X) - X; + uint32_t end = (b > Y ? Y : b) - X; memcpy(fb->data + start, data, end - start); @@ -876,9 +877,9 @@ static int flash_populate(stm32_addr_t addr, uint8_t* data, unsigned length) { return(0); } -static int flash_go(stlink_t *sl, st_state_t *st) { - int error = -1; - int ret; +static int32_t flash_go(stlink_t *sl, st_state_t *st) { + int32_t error = -1; + int32_t ret; flash_loader_t fl; stlink_target_connect(sl, st->connect_mode); @@ -904,13 +905,13 @@ static int flash_go(stlink_t *sl, st_state_t *st) { ILOG("flash_do: block %08x -> %04x\n", fb->addr, fb->length); for (stm32_addr_t page = fb->addr; page < fb->addr + fb->length; page += (uint32_t)FLASH_PAGE) { - unsigned length = fb->length - (page - fb->addr); + uint32_t length = fb->length - (page - fb->addr); // update FLASH_PAGE stlink_calculate_pagesize(sl, page); ILOG("flash_do: page %08x\n", page); - unsigned len = (length > FLASH_PAGE) ? (unsigned int)FLASH_PAGE : length; + uint32_t len = (length > FLASH_PAGE) ? (uint32_t)FLASH_PAGE : length; ret = stlink_flashloader_write(sl, &fl, page, fb->data + (page - fb->addr), len); if (ret) { goto error; } } @@ -933,21 +934,21 @@ static int flash_go(stlink_t *sl, st_state_t *st) { } struct cache_level_desc { - unsigned int nsets; - unsigned int nways; - unsigned int log2_nways; - unsigned int width; + uint32_t nsets; + uint32_t nways; + uint32_t log2_nways; + uint32_t width; }; struct cache_desc_t { - unsigned used; + uint32_t used; // minimal line size in bytes - unsigned int dminline; - unsigned int iminline; + uint32_t dminline; + uint32_t iminline; // last level of unification (uniprocessor) - unsigned int louu; + uint32_t louu; struct cache_level_desc icache[7]; struct cache_level_desc dcache[7]; @@ -956,8 +957,8 @@ struct cache_desc_t { static struct cache_desc_t cache_desc; // return the smallest R so that V <= (1 << R); not performance critical -static unsigned ceil_log2(unsigned v) { - unsigned res; +static uint32_t ceil_log2(uint32_t v) { + uint32_t res; for (res = 0; (1U << res) < v; res++); @@ -965,8 +966,8 @@ static unsigned ceil_log2(unsigned v) { } static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) { - unsigned int ccsidr; - unsigned int log2_nsets; + uint32_t ccsidr; + uint32_t log2_nsets; stlink_read_debug32(sl, STLINK_REG_CM7_CCSIDR, &ccsidr); desc->nsets = ((ccsidr >> 13) & 0x3fff) + 1; @@ -979,10 +980,10 @@ static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) { } static void init_cache (stlink_t *sl) { - unsigned int clidr; - unsigned int ccr; - unsigned int ctr; - int i; + uint32_t clidr; + uint32_t ccr; + uint32_t ctr; + int32_t i; // Check have cache stlink_read_debug32(sl, STLINK_REG_CM7_CTR, &ctr); @@ -1006,7 +1007,7 @@ static void init_cache (stlink_t *sl) { cache_desc.dminline, cache_desc.iminline); for (i = 0; i < 7; i++) { - unsigned int ct = (clidr >> (3 * i)) & 0x07; + uint32_t ct = (clidr >> (3 * i)) & 0x07; cache_desc.dcache[i].width = 0; cache_desc.icache[i].width = 0; @@ -1024,19 +1025,19 @@ static void init_cache (stlink_t *sl) { } } -static void cache_flush(stlink_t *sl, unsigned ccr) { - int level; +static void cache_flush(stlink_t *sl, uint32_t ccr) { + int32_t level; if (ccr & STLINK_REG_CM7_CCR_DC) { for (level = cache_desc.louu - 1; level >= 0; level--) { struct cache_level_desc *desc = &cache_desc.dcache[level]; - unsigned addr; - unsigned max_addr = 1 << desc->width; - unsigned way_sh = 32 - desc->log2_nways; + uint32_t addr; + uint32_t max_addr = 1 << desc->width; + uint32_t way_sh = 32 - desc->log2_nways; // D-cache clean by set-ways. for (addr = (level << 1); addr < max_addr; addr += cache_desc.dminline) { - unsigned int way; + uint32_t way; for (way = 0; way < desc->nways; way++) { stlink_write_debug32(sl, STLINK_REG_CM7_DCCSW, addr | (way << way_sh)); @@ -1051,9 +1052,9 @@ static void cache_flush(stlink_t *sl, unsigned ccr) { } } -static int cache_modified; +static int32_t cache_modified; -static void cache_change(stm32_addr_t start, unsigned count) { +static void cache_change(stm32_addr_t start, uint32_t count) { if (count == 0) { return; } (void)start; @@ -1061,7 +1062,7 @@ static void cache_change(stm32_addr_t start, unsigned count) { } static void cache_sync(stlink_t *sl) { - unsigned ccr; + uint32_t ccr; if (!cache_desc.used) { return; } @@ -1074,7 +1075,7 @@ static void cache_sync(stlink_t *sl) { static size_t unhexify(const char *in, char *out, size_t out_count) { size_t i; - unsigned int c; + uint32_t c; for (i = 0; i < out_count; i++) { if (sscanf(in + (2 * i), "%02x", &c) != 1) { return(i); } @@ -1085,7 +1086,7 @@ static size_t unhexify(const char *in, char *out, size_t out_count) { return(i); } -int serve(stlink_t *sl, st_state_t *st) { +int32_t serve(stlink_t *sl, st_state_t *st) { SOCKET sock = socket(AF_INET, SOCK_STREAM, 0); if (!IS_SOCK_VALID(sock)) { @@ -1093,7 +1094,7 @@ int serve(stlink_t *sl, st_state_t *st) { return(1); } - unsigned int val = 1; + uint32_t val = 1; setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val)); struct sockaddr_in serv_addr; @@ -1149,16 +1150,16 @@ int serve(stlink_t *sl, st_state_t *st) { * To allow resetting the chip from GDB it is required to emulate attaching * and detaching to target. */ - unsigned int attached = 1; + uint32_t attached = 1; // if a critical error is detected, break from the loop - int critical_error = 0; - int ret; + int32_t critical_error = 0; + int32_t ret; while (1) { ret = 0; char* packet; - int status = gdb_recv_packet(client, &packet); + int32_t status = gdb_recv_packet(client, &packet); if (status < 0) { ELOG("cannot recv: %d\n", status); @@ -1186,7 +1187,7 @@ int serve(stlink_t *sl, st_state_t *st) { params = separator + 1; } - unsigned queryNameLength = (unsigned int)(separator - &packet[1]); + uint32_t queryNameLength = (uint32_t)(separator - &packet[1]); char* queryName = calloc(queryNameLength + 1, 1); strncpy(queryName, &packet[1], queryNameLength); @@ -1205,8 +1206,8 @@ int serve(stlink_t *sl, st_state_t *st) { __s_addr = strsep(&tok, ","); s_length = tok; - unsigned addr = (unsigned int)strtoul(__s_addr, NULL, 16), - length = (unsigned int)strtoul(s_length, NULL, 16); + uint32_t addr = (uint32_t)strtoul(__s_addr, NULL, 16), + length = (uint32_t)strtoul(s_length, NULL, 16); DLOG("Xfer: type:%s;op:%s;annex:%s;addr:%d;length:%d\n", type, op, annex, addr, length); @@ -1223,7 +1224,7 @@ int serve(stlink_t *sl, st_state_t *st) { } if (data) { - unsigned data_length = (unsigned int)strlen(data); + uint32_t data_length = (uint32_t)strlen(data); if (addr + length > data_length) { length = data_length - addr; } @@ -1366,8 +1367,8 @@ int serve(stlink_t *sl, st_state_t *st) { __s_addr = strsep(&tok, ","); s_length = tok; - unsigned addr = (unsigned int)strtoul(__s_addr, NULL, 16), - length = (unsigned int)strtoul(s_length, NULL, 16); + uint32_t addr = (uint32_t)strtoul(__s_addr, NULL, 16), + length = (uint32_t)strtoul(s_length, NULL, 16); DLOG("FlashErase: addr:%08x,len:%04x\n", addr, length); @@ -1384,15 +1385,15 @@ int serve(stlink_t *sl, st_state_t *st) { __s_addr = strsep(&tok, ":"); data = tok; - unsigned addr = (unsigned int)strtoul(__s_addr, NULL, 16); - unsigned data_length = status - (unsigned int)(data - packet); + uint32_t addr = (uint32_t)strtoul(__s_addr, NULL, 16); + uint32_t data_length = status - (uint32_t)(data - packet); // Length of decoded data cannot be more than encoded, as escapes are removed. // Additional byte is reserved for alignment fix. uint8_t *decoded = calloc(data_length + 1, 1); - unsigned dec_index = 0; + uint32_t dec_index = 0; - for (unsigned int i = 0; i < data_length; i++) { + for (uint32_t i = 0; i < data_length; i++) { if (data[i] == 0x7d) { i++; decoded[dec_index++] = data[i] ^ 0x20; @@ -1457,7 +1458,7 @@ int serve(stlink_t *sl, st_state_t *st) { struct stlink_reg reg; stm32_addr_t pc; stm32_addr_t addr; - int offset = 0; + int32_t offset = 0; uint16_t insn; if (!st->semihosting) { break; } @@ -1547,15 +1548,15 @@ int serve(stlink_t *sl, st_state_t *st) { reply = calloc(8 * 16 + 1, 1); - for (int i = 0; i < 16; i++) { + for (int32_t i = 0; i < 16; i++) { sprintf(&reply[i * 8], "%08x", (uint32_t)htonl(regp.r[i])); } break; case 'p': { - unsigned id = (unsigned int)strtoul(&packet[1], NULL, 16); - unsigned myreg = 0xDEADDEAD; + uint32_t id = (uint32_t)strtoul(&packet[1], NULL, 16); + uint32_t myreg = 0xDEADDEAD; if (id < 16) { ret = stlink_read_reg(sl, id, ®p); @@ -1607,8 +1608,8 @@ int serve(stlink_t *sl, st_state_t *st) { char* s_reg = &packet[1]; char* s_value = strstr(&packet[1], "=") + 1; - unsigned reg = (unsigned int)strtoul(s_reg, NULL, 16); - unsigned value = (unsigned int)strtoul(s_value, NULL, 16); + uint32_t reg = (uint32_t)strtoul(s_reg, NULL, 16); + uint32_t value = (uint32_t)strtoul(s_value, NULL, 16); if (reg < 16) { @@ -1645,7 +1646,7 @@ int serve(stlink_t *sl, st_state_t *st) { case 'G': - for (int i = 0; i < 16; i++) { + for (int32_t i = 0; i < 16; i++) { char str[9] = {0}; strncpy(str, &packet[1 + i * 8], 8); uint32_t reg = (uint32_t)strtoul(str, NULL, 16); @@ -1662,12 +1663,12 @@ int serve(stlink_t *sl, st_state_t *st) { char* s_count = strstr(&packet[1], ",") + 1; stm32_addr_t start = (stm32_addr_t)strtoul(s_start, NULL, 16); - unsigned count = (unsigned int)strtoul(s_count, NULL, 16); + uint32_t count = (uint32_t)strtoul(s_count, NULL, 16); - unsigned adj_start = start % 4; - unsigned count_rnd = (count + adj_start + 4 - 1) / 4 * 4; + uint32_t adj_start = start % 4; + uint32_t count_rnd = (count + adj_start + 4 - 1) / 4 * 4; - if (count_rnd > sl->flash_pgsz) { count_rnd = (unsigned int)sl->flash_pgsz; } + if (count_rnd > sl->flash_pgsz) { count_rnd = (uint32_t)sl->flash_pgsz; } if (count_rnd > 0x1800) { count_rnd = 0x1800; } @@ -1679,7 +1680,7 @@ int serve(stlink_t *sl, st_state_t *st) { reply = calloc(count * 2 + 1, 1); - for (unsigned int i = 0; i < count; i++) { + for (uint32_t i = 0; i < count; i++) { reply[i * 2 + 0] = hex[sl->q_buf[i + adj_start] >> 4]; reply[i * 2 + 1] = hex[sl->q_buf[i + adj_start] & 0xf]; } @@ -1693,15 +1694,15 @@ int serve(stlink_t *sl, st_state_t *st) { char* hexdata = strstr(packet, ":") + 1; stm32_addr_t start = (stm32_addr_t)strtoul(s_start, NULL, 16); - unsigned count = (unsigned int)strtoul(s_count, NULL, 16); - int err = 0; + uint32_t count = (uint32_t)strtoul(s_count, NULL, 16); + int32_t err = 0; if (start % 4) { - unsigned align_count = 4 - start % 4; + uint32_t align_count = 4 - start % 4; if (align_count > count) { align_count = count; } - for (unsigned int i = 0; i < align_count; i++) { + for (uint32_t i = 0; i < align_count; i++) { char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; uint8_t byte = (uint8_t)strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; @@ -1715,9 +1716,9 @@ int serve(stlink_t *sl, st_state_t *st) { } if (count - count % 4) { - unsigned aligned_count = count - count % 4; + uint32_t aligned_count = count - count % 4; - for (unsigned int i = 0; i < aligned_count; i++) { + for (uint32_t i = 0; i < aligned_count; i++) { char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; uint8_t byte = (uint8_t)strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; @@ -1731,7 +1732,7 @@ int serve(stlink_t *sl, st_state_t *st) { } if (count) { - for (unsigned int i = 0; i < count; i++) { + for (uint32_t i = 0; i < count; i++) { char hextmp[3] = { hexdata[i * 2], hexdata[i * 2 + 1], 0 }; uint8_t byte = (uint8_t)strtoul(hextmp, NULL, 16); sl->q_buf[i] = byte; @@ -1871,7 +1872,7 @@ int serve(stlink_t *sl, st_state_t *st) { if (reply) { DLOG("send: %s\n", reply); - int result = gdb_send_packet(client, reply); + int32_t result = gdb_send_packet(client, reply); if (result != 0) { ELOG("cannot send: %d\n", result); diff --git a/src/st-util/semihosting.c b/src/st-util/semihosting.c index f603f6224..93a6cf7cc 100644 --- a/src/st-util/semihosting.c +++ b/src/st-util/semihosting.c @@ -1,4 +1,5 @@ #include +#include #include #include @@ -11,9 +12,9 @@ #include #include "semihosting.h" -static int mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { - int offset = addr % 4; - int len = 4; +static int32_t mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { + int32_t offset = addr % 4; + int32_t len = 4; if (sl == NULL || data == NULL) { return(-1); } @@ -25,9 +26,9 @@ static int mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { } #ifdef UNUSED -static int mem_read_u16(stlink_t *sl, uint32_t addr, uint16_t *data) { - int offset = addr % 4; - int len = (offset > 2 ? 8 : 4); +static int32_t mem_read_u16(stlink_t *sl, uint32_t addr, uint16_t *data) { + int32_t offset = addr % 4; + int32_t len = (offset > 2 ? 8 : 4); if (sl == NULL || data == NULL) { return(-1); } @@ -38,9 +39,9 @@ static int mem_read_u16(stlink_t *sl, uint32_t addr, uint16_t *data) { return(0); } -static int mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) { - int offset = addr % 4; - int len = (offset > 0 ? 8 : 4); +static int32_t mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) { + int32_t offset = addr % 4; + int32_t len = (offset > 0 ? 8 : 4); if (sl == NULL || data == NULL) { return(-1); } @@ -52,9 +53,9 @@ static int mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) { } #endif -static int mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { - int offset = addr % 4; - int read_len = len + offset; +static int32_t mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { + int32_t offset = addr % 4; + int32_t read_len = len + offset; if (sl == NULL || data == NULL) { return(-1); } @@ -68,7 +69,7 @@ static int mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { return(0); } -static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { +static int32_t mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { /* Note: this function can write more than it is asked to! * If addr is not an even 32 bit boundary, or len is not a multiple of 4. * If only 32 bit values can be written to the target, then this function should read @@ -78,8 +79,8 @@ static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { * Just return when the length is zero avoiding unneeded work. */ if (len == 0) { return(0); } - int offset = addr % 4; - int write_len = len + offset; + int32_t offset = addr % 4; + int32_t write_len = len + offset; if (sl == NULL || data == NULL) { return(-1); } @@ -112,7 +113,7 @@ static int mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { #define O_BINARY 0 #endif -static int open_mode_flags[12] = { +static int32_t open_mode_flags[12] = { O_RDONLY, O_RDONLY | O_BINARY, O_RDWR, @@ -127,9 +128,9 @@ static int open_mode_flags[12] = { O_RDWR | O_CREAT | O_APPEND | O_BINARY }; -static int saved_errno = 0; +static int32_t saved_errno = 0; -int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { +int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (sl == NULL || ret == NULL) { return(-1); } @@ -200,7 +201,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { case SEMIHOST_SYS_CLOSE: { uint32_t args[1]; - int fd; + int32_t fd; if (mem_read(sl, r1, args, sizeof(args)) != 0) { DLOG("Semihosting SYS_CLOSE error: cannot read args from target memory\n"); @@ -208,7 +209,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - fd = (int)args[0]; + fd = (int32_t)args[0]; DLOG("Semihosting: close(%d)\n", fd); @@ -222,7 +223,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { { uint32_t args[3]; uint32_t buffer_address; - int fd; + int32_t fd; uint32_t buffer_len; void *buffer; @@ -232,7 +233,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - fd = (int)args[0]; + fd = (int32_t)args[0]; buffer_address = args[1]; buffer_len = args[2]; @@ -277,7 +278,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { { uint32_t args[3]; uint32_t buffer_address; - int fd; + int32_t fd; uint32_t buffer_len; void *buffer; ssize_t read_result; @@ -288,7 +289,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - fd = (int)args[0]; + fd = (int32_t)args[0]; buffer_address = args[1]; buffer_len = args[2]; @@ -388,7 +389,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { case SEMIHOST_SYS_SEEK: { uint32_t args[2]; - int fd; + int32_t fd; off_t offset; if (mem_read(sl, r1, args, sizeof(args)) != 0) { @@ -397,10 +398,10 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - fd = (int)args[0]; + fd = (int32_t)args[0]; offset = (off_t)args[1]; - DLOG("Semihosting: lseek(%d, %d, SEEK_SET)\n", fd, (int)offset); + DLOG("Semihosting: lseek(%d, %d, SEEK_SET)\n", fd, (int32_t)offset); *ret = (uint32_t)lseek(fd, offset, SEEK_SET); saved_errno = errno; @@ -437,7 +438,7 @@ int do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { return(-1); } - for (int i = 0; i < WRITE0_BUFFER_SIZE; i++) { + for (int32_t i = 0; i < WRITE0_BUFFER_SIZE; i++) { if (buf[i] == 0) { return(0); } fprintf(stderr, "%c", buf[i]); diff --git a/src/st-util/semihosting.h b/src/st-util/semihosting.h index e7ddfcd97..fd3990ba2 100644 --- a/src/st-util/semihosting.h +++ b/src/st-util/semihosting.h @@ -1,6 +1,8 @@ #ifndef SEMIHOSTING_H #define SEMIHOSTING_H +#include + #include #define SEMIHOST_SYS_OPEN 0x01 @@ -29,6 +31,6 @@ #define SEMIHOST_SYS_ELAPSED 0x30 #define SEMIHOST_SYS_TICKFREQ 0x31 -int do_semihosting(stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret); +int32_t do_semihosting(stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret); #endif // SEMIHOSTING_H diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index 2bf1f9d32..f0426f577 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -263,7 +263,7 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { uint8_t* mem = NULL; size_t size = 0; uint32_t begin = 0; - int res = stlink_parse_ihex(gui->filename, 0, &mem, &size, &begin); + int32_t res = stlink_parse_ihex(gui->filename, 0, &mem, &size, &begin); if (res == 0) { if (gui->file_mem.memory) { @@ -440,7 +440,7 @@ static gchar *dev_format_chip_id(guint32 chip_id) { } static gchar *dev_format_mem_size(gsize flash_size) { - return(g_strdup_printf("%u kB", (unsigned int)(flash_size / 1024))); + return(g_strdup_printf("%u kB", (uint32_t)(flash_size / 1024))); } @@ -640,7 +640,7 @@ static void flash_button_cb(GtkWidget *widget, gpointer data) { } } -int export_to_file(const char*filename, const struct mem_t flash_mem) { +int32_t export_to_file(const char*filename, const struct mem_t flash_mem) { printf("%s\n", filename); FILE * f = fopen(filename, "w"); @@ -885,7 +885,7 @@ static void stlink_gui_build_ui(STlinkGUI *gui) { stlink_gui_set_disconnected(gui); } -int main(int argc, char **argv) { +int32_t main(int32_t argc, char **argv) { STlinkGUI *gui; gtk_init(&argc, &argv); diff --git a/src/stlink-gui/gui.h b/src/stlink-gui/gui.h index 08519ea56..2d7f31913 100644 --- a/src/stlink-gui/gui.h +++ b/src/stlink-gui/gui.h @@ -1,6 +1,7 @@ #ifndef GUI_H #define GUI_H +#include #include #define STLINK_TYPE_GUI (stlink_gui_get_type()) @@ -87,6 +88,6 @@ struct _STlinkGUIClass { }; GType stlink_gui_get_type(void); -int export_to_file(const char*filename, const struct mem_t flash_mem); +int32_t export_to_file(const char*filename, const struct mem_t flash_mem); #endif // GUI_H diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index ddab5ed08..132875a66 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -1,3 +1,5 @@ +#include + #include #include "calculate.h" #include "common_flash.h" @@ -39,7 +41,7 @@ uint32_t calculate_F7_sectornum(uint32_t flashaddr) { } uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, - unsigned bank) { + uint32_t bank) { flashaddr &= ~((bank == BANK_1) ? STM32_FLASH_BASE diff --git a/src/stlink-lib/calculate.h b/src/stlink-lib/calculate.h index 64dfb51b2..bdff782ae 100644 --- a/src/stlink-lib/calculate.h +++ b/src/stlink-lib/calculate.h @@ -7,6 +7,8 @@ #ifndef CALCULATE_H #define CALCULATE_H +#include + uint32_t calculate_F4_sectornum(uint32_t); uint32_t calculate_F7_sectornum(uint32_t); uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, unsigned); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 347d89e14..7e99a8730 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,13 +1,14 @@ -#include "chipid.h" -#include -#include - #include #include #include +#include #include #include +#include "chipid.h" +#include +#include + static struct stlink_chipid_params *devicelist; void dump_a_chip(struct stlink_chipid_params *dev) { @@ -43,7 +44,7 @@ void process_chipfile(char *fname) { char *p, buf[256]; char word[64], value[64]; struct stlink_chipid_params *ts; - int nc; + int32_t nc; // fprintf (stderr, "processing chip-id file %s.\n", fname); fp = fopen(fname, "r"); diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index d6afc4525..9eaac722d 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -1,6 +1,8 @@ #ifndef CHIPID_H #define CHIPID_H +#include + #include #include diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 8e4b9a716..cb87f5f36 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -1,16 +1,15 @@ +#include #include #include #include - +#include #include #include #include #include -#include #include #include - #include "calculate.h" #include "common_flash.h" #include "map_file.h" @@ -28,7 +27,7 @@ // Private structs and functions defines struct stlink_fread_worker_arg { - int fd; + int32_t fd; }; struct stlink_fread_ihex_worker_arg { @@ -42,12 +41,12 @@ struct stlink_fread_ihex_worker_arg { typedef bool (*save_block_fn)(void *arg, uint8_t *block, ssize_t len); static void stop_wdg_in_debug(stlink_t *); -int stlink_jtag_reset(stlink_t *, int); -int stlink_soft_reset(stlink_t *, int); +int32_t stlink_jtag_reset(stlink_t *, int); +int32_t stlink_soft_reset(stlink_t *, int); void _parse_version(stlink_t *, stlink_version_t *); static uint8_t stlink_parse_hex(const char *); -static int stlink_read(stlink_t *, stm32_addr_t, size_t, save_block_fn, void *); -static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *, int, stm32_addr_t); +static int32_t stlink_read(stlink_t *, stm32_addr_t, size_t, save_block_fn, void *); +static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *, int32_t, stm32_addr_t); static bool stlink_fread_ihex_worker(void *, uint8_t *, ssize_t); static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *); static bool stlink_fread_worker(void *, uint8_t *, ssize_t); @@ -67,7 +66,7 @@ void stlink_close(stlink_t *sl) { } // 250 -int stlink_exit_debug_mode(stlink_t *sl) { +int32_t stlink_exit_debug_mode(stlink_t *sl) { DLOG("*** stlink_exit_debug_mode ***\n"); if (sl->flash_type != STM32_FLASH_TYPE_UNKNOWN && @@ -80,16 +79,16 @@ int stlink_exit_debug_mode(stlink_t *sl) { } //248 -int stlink_enter_swd_mode(stlink_t *sl) { +int32_t stlink_enter_swd_mode(stlink_t *sl) { DLOG("*** stlink_enter_swd_mode ***\n"); return (sl->backend->enter_swd_mode(sl)); } // 271 // Force the core into the debug mode -> halted state. -int stlink_force_debug(stlink_t *sl) { +int32_t stlink_force_debug(stlink_t *sl) { DLOG("*** stlink_force_debug_mode ***\n"); - int res = sl->backend->force_debug(sl); + int32_t res = sl->backend->force_debug(sl); if (res) { return (res); } @@ -99,14 +98,14 @@ int stlink_force_debug(stlink_t *sl) { } // 251 -int stlink_exit_dfu_mode(stlink_t *sl) { +int32_t stlink_exit_dfu_mode(stlink_t *sl) { DLOG("*** stlink_exit_dfu_mode ***\n"); return (sl->backend->exit_dfu_mode(sl)); } // 253 -int stlink_core_id(stlink_t *sl) { - int ret; +int32_t stlink_core_id(stlink_t *sl) { + int32_t ret; DLOG("*** stlink_core_id ***\n"); ret = sl->backend->core_id(sl); @@ -127,8 +126,8 @@ int stlink_core_id(stlink_t *sl) { // 287 // stlink_chip_id() is called by stlink_load_device_params() // do not call this procedure directly. -int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { - int ret; +int32_t stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { + int32_t ret; cortex_m3_cpuid_t cpu_id; // Read the CPU ID to determine where to read the core id @@ -193,7 +192,7 @@ int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { * @param sl stlink context * @param cpuid pointer to the result object */ -int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { +int32_t stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { uint32_t raw; if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { @@ -217,7 +216,7 @@ int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { * @param sl * @return 0 for success, or -1 for unsupported core type. */ -int stlink_load_device_params(stlink_t *sl) { +int32_t stlink_load_device_params(stlink_t *sl) { // This seems to normally work so is unnecessary info for a normal user. // Demoted to debug. -- REW DLOG("Loading device parameters....\n"); @@ -312,17 +311,17 @@ int stlink_load_device_params(stlink_t *sl) { } ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", - params->dev_type, (unsigned)(sl->sram_size / 1024), (unsigned)(sl->flash_size / 1024), - (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) : (unsigned)(sl->flash_pgsz / 1024), + params->dev_type, (uint32_t)(sl->sram_size / 1024), (uint32_t)(sl->flash_size / 1024), + (sl->flash_pgsz < 1024) ? (uint32_t)(sl->flash_pgsz) : (uint32_t)(sl->flash_pgsz / 1024), (sl->flash_pgsz < 1024) ? "byte" : "KiB"); return (0); } // 254 -int stlink_reset(stlink_t *sl, enum reset_type type) { +int32_t stlink_reset(stlink_t *sl, enum reset_type type) { uint32_t dhcsr; - unsigned timeout; + uint32_t timeout; DLOG("*** stlink_reset ***\n"); @@ -352,7 +351,7 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { */ dhcsr = 0; - int res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + int32_t res = stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); if ((dhcsr & STLINK_REG_DHCSR_S_RESET_ST) == 0 && !res) { // reset not done yet --> try reset through AIRCR so that NRST does not need to be connected ILOG("NRST is not connected --> using software reset via AIRCR\n"); @@ -380,9 +379,9 @@ int stlink_reset(stlink_t *sl, enum reset_type type) { return (0); } -int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { - int ret; - unsigned timeout; +int32_t stlink_soft_reset(stlink_t *sl, int32_t halt_on_reset) { + int32_t ret; + uint32_t timeout; uint32_t dhcsr, dfsr; DLOG("*** stlink_soft_reset %s***\n", halt_on_reset ? "(halt) " : ""); @@ -455,7 +454,7 @@ int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { } // 255 -int stlink_run(stlink_t *sl, enum run_type type) { +int32_t stlink_run(stlink_t *sl, enum run_type type) { struct stlink_reg rr; DLOG("*** stlink_run ***\n"); @@ -472,7 +471,7 @@ int stlink_run(stlink_t *sl, enum run_type type) { } // 273 -int stlink_set_swdclk(stlink_t *sl, int freq_khz) { +int32_t stlink_set_swdclk(stlink_t *sl, int32_t freq_khz) { DLOG("*** set_swdclk ***\n"); return (sl->backend->set_swdclk(sl, freq_khz)); } @@ -500,8 +499,8 @@ void stlink_core_stat(stlink_t *sl) { } // 256 -int stlink_status(stlink_t *sl) { - int ret; +int32_t stlink_status(stlink_t *sl) { + int32_t ret; DLOG("*** stlink_status ***\n"); ret = sl->backend->status(sl); @@ -510,7 +509,7 @@ int stlink_status(stlink_t *sl) { } // 257 -int stlink_version(stlink_t *sl) { +int32_t stlink_version(stlink_t *sl) { DLOG("*** looking up stlink version ***\n"); if (sl->backend->version(sl)) { @@ -534,8 +533,8 @@ int stlink_version(stlink_t *sl) { } // 272 -int stlink_target_voltage(stlink_t *sl) { - int voltage = -1; +int32_t stlink_target_voltage(stlink_t *sl) { + int32_t voltage = -1; DLOG("*** reading target voltage\n"); if (sl->backend->target_voltage != NULL) { @@ -560,14 +559,14 @@ bool stlink_is_core_halted(stlink_t *sl) { } // 269 -int stlink_step(stlink_t *sl) { +int32_t stlink_step(stlink_t *sl) { DLOG("*** stlink_step ***\n"); return (sl->backend->step(sl)); } // 270 -int stlink_current_mode(stlink_t *sl) { - int mode = sl->backend->current_mode(sl); +int32_t stlink_current_mode(stlink_t *sl) { + int32_t mode = sl->backend->current_mode(sl); switch (mode) { case STLINK_DEV_DFU_MODE: @@ -586,19 +585,19 @@ int stlink_current_mode(stlink_t *sl) { } // 274 -int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { +int32_t stlink_trace_enable(stlink_t *sl, uint32_t frequency) { DLOG("*** stlink_trace_enable ***\n"); return (sl->backend->trace_enable(sl, frequency)); } // 275 -int stlink_trace_disable(stlink_t *sl) { +int32_t stlink_trace_disable(stlink_t *sl) { DLOG("*** stlink_trace_disable ***\n"); return (sl->backend->trace_disable(sl)); } // 276 -int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { +int32_t stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { return (sl->backend->trace_read(sl, buf, size)); } @@ -612,7 +611,7 @@ void stlink_print_data(stlink_t *sl) { DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); } - for (int i = 0; i < sl->q_len; i++) { + for (int32_t i = 0; i < sl->q_len; i++) { if (i % 16 == 0) { /* if (sl->q_data_dir == Q_DATA_OUT) { @@ -622,18 +621,18 @@ void stlink_print_data(stlink_t *sl) { } */ } - // DLOG(" %02x", (unsigned int) sl->q_buf[i]); - fprintf(stderr, " %02x", (unsigned int)sl->q_buf[i]); + // DLOG(" %02x", (uint32_t) sl->q_buf[i]); + fprintf(stderr, " %02x", (uint32_t)sl->q_buf[i]); } // DLOG("\n\n"); fprintf(stderr, "\n"); } // 283 -int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr) { +int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr) { // write the file in sram at addr - int error = -1; + int32_t error = -1; size_t off; size_t len; @@ -688,10 +687,10 @@ int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_ } //284 -int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { +int32_t stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { // write the file in sram at addr - int error = -1; + int32_t error = -1; size_t off; size_t len; mapped_file_t mf = MAPPED_FILE_INITIALIZER; @@ -763,12 +762,12 @@ int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { } // 302 -int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t addr, size_t size) { +int32_t stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t addr, size_t size) { // read size bytes from addr to file - ILOG("read from address %#010x size %u\n", addr, (unsigned)size); + ILOG("read from address %#010x size %u\n", addr, (uint32_t)size); - int error; - int fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); + int32_t error; + int32_t fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); if (fd == -1) { fprintf(stderr, "open(%s) == -1\n", path); @@ -797,9 +796,9 @@ int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t addr } // 300 -int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, size_t size) { +int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, size_t size) { // write the buffer right after the loader - int ret = 0; + int32_t ret = 0; size_t chunk = size & ~0x3; size_t rem = size & 0x3; @@ -858,15 +857,15 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { } // 279 -int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, +int32_t stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, size_t *size, uint32_t *begin) { - int res = 0; + int32_t res = 0; *begin = UINT32_MAX; uint8_t *data = NULL; uint32_t end = 0; bool eof_found = false; - for (int scan = 0; (res == 0) && (scan < 2); ++scan) { + for (int32_t scan = 0; (res == 0) && (scan < 2); ++scan) { // parse file two times - first to find memory range, second - to fill it if (scan == 1) { if (!eof_found) { @@ -885,7 +884,7 @@ int stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, data = calloc(*size, 1); // use calloc to get NULL if out of memory if (!data) { - ELOG("Cannot allocate %u bytes\n", (unsigned)(*size)); + ELOG("Cannot allocate %u bytes\n", (uint32_t)(*size)); res = -1; break; } @@ -1029,7 +1028,7 @@ uint8_t stlink_get_erased_pattern(stlink_t *sl) { } // 322 -int stlink_target_connect(stlink_t *sl, enum connect_type connect) { +int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect) { if (connect == CONNECT_UNDER_RESET) { stlink_enter_swd_mode(sl); @@ -1045,7 +1044,7 @@ int stlink_target_connect(stlink_t *sl, enum connect_type connect) { stlink_jtag_reset(sl, STLINK_DEBUG_APIV2_DRIVE_NRST_HIGH); // try to halt the core after reset - unsigned timeout = time_ms() + 10; + uint32_t timeout = time_ms() + 10; while (time_ms() < timeout) { sl->backend->force_debug(sl); usleep(100); @@ -1128,7 +1127,7 @@ static void stop_wdg_in_debug(stlink_t *sl) { } } -int stlink_jtag_reset(stlink_t *sl, int value) { +int32_t stlink_jtag_reset(stlink_t *sl, int32_t value) { DLOG("*** stlink_jtag_reset %d ***\n", value); return (sl->backend->jtag_reset(sl, value)); } @@ -1207,7 +1206,7 @@ void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { /* Limit the block size to compare to 0x1800 as anything larger will stall the * STLINK2 Maybe STLINK V1 needs smaller value! */ -int check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { +int32_t check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { size_t off; size_t n_cmp = sl->flash_pgsz; @@ -1249,7 +1248,7 @@ void md5_calculate(mapped_file_t *mf) { Md5Finalise(&md5Context, &md5Hash); printf("md5 checksum: "); - for (int i = 0; i < (int)sizeof(md5Hash); i++) { + for (int32_t i = 0; i < (int32_t)sizeof(md5Hash); i++) { printf("%x", md5Hash.bytes[i]); } @@ -1269,17 +1268,17 @@ void stlink_checksum(mapped_file_t *mp) { } void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { - unsigned int val; + uint32_t val; // set PC to the reset routine stlink_read_debug32(sl, addr + 4, &val); stlink_write_reg(sl, val, 15); stlink_run(sl, RUN_NORMAL); } -static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, +static int32_t stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, save_block_fn fn, void *fn_arg) { - int error = -1; + int32_t error = -1; if (size < 1) { size = sl->flash_size; @@ -1333,7 +1332,7 @@ static bool stlink_fread_worker(void *arg, uint8_t *block, ssize_t len) { static uint8_t stlink_parse_hex(const char *hex) { uint8_t d[2]; - for (int i = 0; i < 2; ++i) { + for (int32_t i = 0; i < 2; ++i) { char c = *(hex + i); if (c >= '0' && c <= '9') { @@ -1406,7 +1405,7 @@ static bool stlink_fread_ihex_writeline(struct stlink_fread_ihex_worker_arg *the } static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *the_arg, - int fd, stm32_addr_t addr) { + int32_t fd, stm32_addr_t addr) { the_arg->file = fdopen(fd, "w"); the_arg->addr = addr; the_arg->lba = 0; diff --git a/src/stlink-lib/common.h b/src/stlink-lib/common.h index dd6cf95b2..c60b49199 100644 --- a/src/stlink-lib/common.h +++ b/src/stlink-lib/common.h @@ -7,7 +7,12 @@ #ifndef COMMON_H #define COMMON_H -int check_file(stlink_t *, mapped_file_t *, stm32_addr_t); +#include + +#include "map_file.h" +#include "md5.h" + +int32_t check_file(stlink_t *, mapped_file_t *, stm32_addr_t); void md5_calculate(mapped_file_t *); void stlink_checksum(mapped_file_t *); void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index a74d88b16..e2a394946 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1,7 +1,9 @@ +#include #include -#include #include #include + +#include #include "calculate.h" #include "flash_loader.h" #include "common_flash.h" @@ -31,7 +33,7 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { } } -uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { +uint32_t read_flash_cr(stlink_t *sl, uint32_t bank) { uint32_t reg, res; if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { @@ -117,7 +119,7 @@ void lock_flash(stlink_t *sl) { } } -static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { +static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) { uint32_t sr_reg; if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || @@ -190,7 +192,7 @@ void clear_flash_error(stlink_t *sl) { } } -uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { +uint32_t read_flash_sr(stlink_t *sl, uint32_t bank) { uint32_t res, sr_reg; if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || @@ -222,9 +224,9 @@ uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { return (res); } -unsigned int is_flash_busy(stlink_t *sl) { +uint32_t is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; - unsigned int res; + uint32_t res; if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || @@ -267,7 +269,7 @@ void wait_flash_busy(stlink_t *sl) { ; } -int check_flash_error(stlink_t *sl) { +int32_t check_flash_error(stlink_t *sl) { uint32_t res = 0; uint32_t WRPERR, PROGERR, PGAERR; @@ -361,7 +363,7 @@ int check_flash_error(stlink_t *sl) { return (0); } -static inline unsigned int is_flash_locked(stlink_t *sl) { +static inline uint32_t is_flash_locked(stlink_t *sl) { /* return non zero for true */ uint32_t cr_lock_shift; uint32_t cr_reg; @@ -463,7 +465,7 @@ static void unlock_flash(stlink_t *sl) { } /* unlock flash if already locked */ -int unlock_flash_if(stlink_t *sl) { +int32_t unlock_flash_if(stlink_t *sl) { if (is_flash_locked(sl)) { unlock_flash(sl); @@ -477,9 +479,9 @@ int unlock_flash_if(stlink_t *sl) { return (0); } -int lock_flash_option(stlink_t *sl) { +int32_t lock_flash_option(stlink_t *sl) { uint32_t optlock_shift, optcr_reg, n, optcr2_reg = 0; - int active_bit_level = 1; + int32_t active_bit_level = 1; switch (sl->flash_type) { case STM32_FLASH_TYPE_F0_F1_F3: @@ -555,7 +557,7 @@ int lock_flash_option(stlink_t *sl) { static bool is_flash_option_locked(stlink_t *sl) { uint32_t optlock_shift, optcr_reg; - int active_bit_level = 1; + int32_t active_bit_level = 1; uint32_t n; switch (sl->flash_type) { @@ -612,7 +614,7 @@ static bool is_flash_option_locked(stlink_t *sl) { return (n & (1u << optlock_shift)); } -static int unlock_flash_option(stlink_t *sl) { +static int32_t unlock_flash_option(stlink_t *sl) { uint32_t optkey_reg, optkey2_reg = 0; uint32_t optkey1 = FLASH_OPTKEY1; uint32_t optkey2 = FLASH_OPTKEY2; @@ -669,7 +671,7 @@ static int unlock_flash_option(stlink_t *sl) { return (0); } -int unlock_flash_option_if(stlink_t *sl) { +int32_t unlock_flash_option_if(stlink_t *sl) { if (is_flash_option_locked(sl)) { if (unlock_flash_option(sl)) { ELOG("Could not unlock flash option!\n"); @@ -687,7 +689,7 @@ int unlock_flash_option_if(stlink_t *sl) { } void write_flash_cr_psiz(stlink_t *sl, uint32_t n, - unsigned bank) { + uint32_t bank) { uint32_t cr_reg, psize_shift; uint32_t x = read_flash_cr(sl, bank); @@ -707,7 +709,7 @@ void write_flash_cr_psiz(stlink_t *sl, uint32_t n, stlink_write_debug32(sl, cr_reg, x); } -void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { +void clear_flash_cr_pg(stlink_t *sl, uint32_t bank) { uint32_t cr_reg, n; uint32_t bit = FLASH_CR_PG; @@ -737,7 +739,7 @@ void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { /* ------------------------------------------------------------------------ */ static void wait_flash_busy_progress(stlink_t *sl) { - int i = 0; + int32_t i = 0; fprintf(stdout, "Mass erasing..."); fflush(stdout); @@ -754,11 +756,11 @@ static void wait_flash_busy_progress(stlink_t *sl) { fprintf(stdout, "\n"); } -static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { +static inline void write_flash_ar(stlink_t *sl, uint32_t n, uint32_t bank) { stlink_write_debug32(sl, (bank == BANK_1) ? FLASH_AR : FLASH_AR2, n); } -static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { +static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, uint32_t bank) { uint32_t cr_reg, snb_mask, snb_shift, ser_shift; uint32_t x = read_flash_cr(sl, bank); @@ -783,7 +785,7 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { stlink_write_debug32(sl, cr_reg, x); } -static void set_flash_cr_per(stlink_t *sl, unsigned bank) { +static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { uint32_t cr_reg, val; if (sl->flash_type == STM32_FLASH_TYPE_G0 || @@ -802,7 +804,7 @@ static void set_flash_cr_per(stlink_t *sl, unsigned bank) { stlink_write_debug32(sl, cr_reg, val); } -static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { +static void clear_flash_cr_per(stlink_t *sl, uint32_t bank) { uint32_t cr_reg; if (sl->flash_type == STM32_FLASH_TYPE_G0 || @@ -836,7 +838,7 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { stlink_write_debug32(sl, FLASH_L4_CR, x); } -static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { +static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { uint32_t val, cr_reg, cr_strt; if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { @@ -871,7 +873,7 @@ static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { stlink_write_debug32(sl, cr_reg, val); } -static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { +static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank) { uint32_t val, cr_reg, cr_mer, cr_pg; if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { @@ -936,7 +938,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { * @param flashaddr an address in the flash page to erase * @return 0 on success -ve on failure */ -int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { +int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // wait for ongoing op to finish wait_flash_busy(sl); // clear flash IO errors @@ -1108,7 +1110,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { lock_flash(sl); } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - unsigned bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + uint32_t bank = (flashaddr < STM32_F1_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); clear_flash_cr_pg(sl, bank); // clear the pg bit set_flash_cr_per(sl, bank); // set the page erase bit @@ -1119,7 +1121,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { clear_flash_cr_per(sl, bank); // clear the page erase bit lock_flash(sl); } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { - unsigned bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; + uint32_t bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); // unlock if locked uint32_t sector = calculate_H7_sectornum( sl, flashaddr, bank); // calculate the actual page from the address @@ -1135,7 +1137,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { return check_flash_error(sl); } -int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { +int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { // Check the address and size validity if (stlink_check_address_range_validity(sl, base_addr, size) < 0) { return -1; @@ -1149,11 +1151,11 @@ int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size stm32_addr_t addr = base_addr; do { - long unsigned int page_size = stlink_calculate_pagesize(sl, addr); + uint32_t page_size = stlink_calculate_pagesize(sl, addr); // Check if size is aligned with a page, unless we want to completely erase the last page if ((addr + page_size) > (base_addr + size) && !align_size) { - ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#lx\n", addr, page_size); + ELOG("Invalid size (not aligned with a page). Page size at address %#x is %#x\n", addr, page_size); return (-1); } @@ -1162,7 +1164,7 @@ int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size return (-1); } - fprintf(stdout, "-> Flash page at %#x erased (size: %#lx)\n", addr, page_size); + fprintf(stdout, "-> Flash page at %#x erased (size: %#x)\n", addr, page_size); fflush(stdout); // check the next page is within the range to erase @@ -1173,8 +1175,8 @@ int stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size return 0; } -int stlink_erase_flash_mass(stlink_t *sl) { - int err = 0; +int32_t stlink_erase_flash_mass(stlink_t *sl) { + int32_t err = 0; // TODO: User MER bit to mass-erase WB series. if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || @@ -1224,11 +1226,11 @@ int stlink_erase_flash_mass(stlink_t *sl) { return (err); } -int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, +int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr) { /* Write the block in flash at addr */ - int err; - unsigned int num_empty, idx; + int32_t err; + uint32_t num_empty, idx; uint8_t erased_pattern = stlink_get_erased_pattern(sl); /* @@ -1236,7 +1238,7 @@ int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, * Therfore it is turned off by default. */ if (sl->opt) { - idx = (unsigned int)length; + idx = (uint32_t)length; for (num_empty = 0; num_empty != length; ++num_empty) if (data[--idx] != erased_pattern) { @@ -1273,10 +1275,10 @@ int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, * @param addr where to start writing * @return 0 on success, -ve on failure. */ -int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { +int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { /* Write the file in flash at addr */ - int err; - unsigned int num_empty, idx; + int32_t err; + uint32_t num_empty, idx; uint8_t erased_pattern = stlink_get_erased_pattern(sl); mapped_file_t mf = MAPPED_FILE_INITIALIZER; @@ -1290,7 +1292,7 @@ int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { stlink_checksum(&mf); if (sl->opt) { - idx = (unsigned int)mf.len; + idx = (uint32_t)mf.len; for (num_empty = 0; num_empty != mf.len; ++num_empty) { if (mf.base[--idx] != erased_pattern) { @@ -1323,10 +1325,10 @@ int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { } -int stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { +int32_t stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { // check the contents of path are at addr - int res; + int32_t res; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { @@ -1346,8 +1348,8 @@ int stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { * @param length how much * @return 0 for success, -ve for failure */ -int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, - unsigned length) { +int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, + uint32_t length) { size_t off; size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; ILOG("Starting verification of write complete\n"); @@ -1369,7 +1371,7 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, stlink_read_mem32(sl, address + (uint32_t)off, (uint16_t)aligned_size); if (memcmp(sl->q_buf, data + off, cmp_size)) { - ELOG("Verification of flash failed at offset: %u\n", (unsigned int)off); + ELOG("Verification of flash failed at offset: %u\n", (uint32_t)off); return (-1); } } @@ -1379,23 +1381,23 @@ int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, } // Check if an address and size are within the flash -int stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { - long unsigned int logvar; +int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { + uint32_t logvar; if (addr < sl->flash_base || addr >= (sl->flash_base + sl->flash_size)) { logvar = sl->flash_base + sl->flash_size - 1; - ELOG("Invalid address, it should be within 0x%08x - 0x%08lx\n", sl->flash_base, logvar); + ELOG("Invalid address, it should be within 0x%08x - 0x%08x\n", sl->flash_base, logvar); return (-1); } if ((addr + size) > (sl->flash_base + sl->flash_size)) { logvar = sl->flash_base + sl->flash_size - addr; - ELOG("The size exceeds the size of the flash (0x%08lx bytes available)\n", logvar); + ELOG("The size exceeds the size of the flash (0x%08x bytes available)\n", logvar); return (-1); } return 0; } // Check if an address is aligned with the beginning of a page -int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { +int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { stm32_addr_t page = sl->flash_base; while (page < addr) { @@ -1409,9 +1411,9 @@ int stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { return 0; } -int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, +int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint8_t eraseonly) { - int ret; + int32_t ret; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); @@ -1428,7 +1430,7 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " "check page start address and compare with flash module organisation " "in related ST reference manual of your device.\n", - (unsigned)(sl->flash_pgsz)); + (uint32_t)(sl->flash_pgsz)); return (-1); } diff --git a/src/stlink-lib/common_flash.h b/src/stlink-lib/common_flash.h index aa92b2143..04e9134b5 100644 --- a/src/stlink-lib/common_flash.h +++ b/src/stlink-lib/common_flash.h @@ -7,13 +7,15 @@ #ifndef COMMON_FLASH_H #define COMMON_FLASH_H +#include + void lock_flash(stlink_t *); void clear_flash_error(stlink_t *); void wait_flash_busy(stlink_t *); -int check_flash_error(stlink_t *); -int unlock_flash_if(stlink_t *); -int lock_flash_option(stlink_t *); -int unlock_flash_option_if(stlink_t *); +int32_t check_flash_error(stlink_t *); +int32_t unlock_flash_if(stlink_t *); +int32_t lock_flash_option(stlink_t *); +int32_t unlock_flash_option_if(stlink_t *); void write_flash_cr_psiz(stlink_t *, uint32_t, unsigned); void clear_flash_cr_pg(stlink_t *, unsigned); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 231a5d4d6..99a8260f7 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -1,3 +1,4 @@ +#include #include #include #include @@ -151,7 +152,7 @@ static const uint8_t loader_code_stm32f7_lv[] = { }; -int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { +int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { size_t size = 0; uint32_t dfsr, cfsr, hfsr; @@ -199,18 +200,18 @@ int stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { return(0); } -static int loader_v_dependent_assignment(stlink_t *sl, +static int32_t loader_v_dependent_assignment(stlink_t *sl, const uint8_t **loader_code, size_t *loader_size, const uint8_t *high_v_loader, size_t high_v_loader_size, const uint8_t *low_v_loader, size_t low_v_loader_size) { - int retval = 0; + int32_t retval = 0; if ( sl->version.stlink_v == 1) { printf("STLINK V1 cannot read voltage, defaulting to 32-bit writes\n"); *loader_code = high_v_loader; *loader_size = high_v_loader_size; } else { - int voltage = stlink_target_voltage(sl); + int32_t voltage = stlink_target_voltage(sl); if (voltage == -1) { retval = -1; @@ -229,7 +230,7 @@ static int loader_v_dependent_assignment(stlink_t *sl, return(retval); } -int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { +int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { const uint8_t* loader_code; size_t loader_size; @@ -270,7 +271,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STM32_CHIPID_F412 || sl->chip_id == STM32_CHIPID_F413 || sl->chip_id == STM32_CHIPID_F446) { - int retval; + int32_t retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f4, sizeof(loader_code_stm32f4), @@ -281,7 +282,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* sl->chip_id == STM32_CHIPID_F7 || sl->chip_id == STM32_CHIPID_F76xxx || sl->chip_id == STM32_CHIPID_F72xxx) { - int retval; + int32_t retval; retval = loader_v_dependent_assignment(sl, &loader_code, &loader_size, loader_code_stm32f7, sizeof(loader_code_stm32f7), @@ -310,7 +311,7 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* } memcpy(sl->q_buf, loader_code, loader_size); - int ret = stlink_write_mem32(sl, sl->sram_base, (uint16_t)loader_size); + int32_t ret = stlink_write_mem32(sl, sl->sram_base, (uint16_t)loader_size); if (ret) { return(ret); } @@ -320,13 +321,13 @@ int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* return(0); // success } -int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { +int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { struct stlink_reg rr; - unsigned timeout; + uint32_t timeout; uint32_t flash_base = 0; uint32_t dhcsr, dfsr, cfsr, hfsr; - DLOG("Running flash loader, write address:%#x, size: %u\n", target, (unsigned int)size); + DLOG("Running flash loader, write address:%#x, size: %u\n", target, (uint32_t)size); if (write_buffer_to_sram(sl, fl, buf, size) == -1) { ELOG("write_buffer_to_sram() == -1\n"); @@ -423,15 +424,15 @@ int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t targe #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 -int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, +int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize) { - unsigned int count, off; - unsigned int num_half_pages = len / pagesize; + uint32_t count, off; + uint32_t num_half_pages = len / pagesize; uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); flash_loader_t fl; bool use_loader = true; - int ret = 0; + int32_t ret = 0; // enable half page write stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -483,7 +484,7 @@ int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, return (ret); } -static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { +static void set_flash_cr_pg(stlink_t *sl, uint32_t bank) { uint32_t cr_reg, x; x = read_flash_cr(sl, bank); @@ -519,7 +520,7 @@ static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { stlink_write_debug32(sl, cr_reg, x); } -static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { +static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr) { uint32_t rcc, rcc_dma_mask, value; rcc = rcc_dma_mask = value = 0; @@ -580,7 +581,7 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { } } -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { +int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { // disable DMA set_dma_state(sl, fl, 0); @@ -602,7 +603,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { unlock_flash_if(sl); // first unlock the cr - int voltage; + int32_t voltage; if (sl->version.stlink_v == 1) { WLOG("STLINK V1 cannot read voltage, use default voltage 3.2V\n"); voltage = 3200; @@ -721,7 +722,7 @@ int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { return (0); } -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, +int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { size_t off; if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || @@ -733,7 +734,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); + (uint32_t)(addr + off)); check_flash_error(sl); return (-1); } @@ -744,14 +745,14 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + DLOG("Starting %3u page write\r\n", (uint32_t)(len / sl->flash_pgsz)); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz + 1), - (unsigned int)(len / sl->flash_pgsz)); + (uint32_t)(off / sl->flash_pgsz + 1), + (uint32_t)(len / sl->flash_pgsz)); fflush(stdout); } @@ -773,7 +774,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, uint32_t pagesize = (flash_regs_base == FLASH_L0_REGS_ADDR)? L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; - DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); + DLOG("Starting %3u page write\r\n", (uint32_t)(len / sl->flash_pgsz)); off = 0; @@ -791,8 +792,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { fprintf(stdout, "\r%3u/%3u pages written", - (unsigned int)(off / sl->flash_pgsz + 1), - (unsigned int)(len / sl->flash_pgsz)); + (uint32_t)(off / sl->flash_pgsz + 1), + (uint32_t)(len / sl->flash_pgsz)); fflush(stdout); } @@ -809,7 +810,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, fprintf(stdout, "\n"); } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - int write_block_count = 0; + int32_t write_block_count = 0; for (off = 0; off < len; off += sl->flash_pgsz) { // adjust last write size size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; @@ -822,7 +823,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, size) == -1) { ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (unsigned)(addr + off)); + (uint32_t)(addr + off)); check_flash_error(sl); return (-1); } @@ -833,7 +834,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, // show progress; writing procedure is slow and previous errors are // misleading fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, - (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); + (uint32_t)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); fflush(stdout); } } @@ -852,8 +853,8 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, if (sl->verbose >= 1) { // show progress - fprintf(stdout, "\r%u/%u bytes written", (unsigned int)off, - (unsigned int)len); + fprintf(stdout, "\r%u/%u bytes written", (uint32_t)off, + (uint32_t)len); fflush(stdout); } } @@ -867,7 +868,7 @@ int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, return check_flash_error(sl); } -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { +int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { uint32_t dhcsr; if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 51448395f..5b7b0945d 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -7,18 +7,18 @@ #ifndef FLASH_LOADER_H #define FLASH_LOADER_H -#include #include +#include #include #include -int stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); -int stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); -int stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); +int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); +int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); +int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); -int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); -int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); +int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); +int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); #endif // FLASH_LOADER_H diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index 15e6397bf..a6155925f 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -1,23 +1,24 @@ -#include - #include +#include #include +#include "helper.h" + #ifdef STLINK_HAVE_SYS_TIME_H #include #else #include #endif -unsigned time_ms() { +uint32_t time_ms() { struct timeval tv; gettimeofday(&tv, NULL); - return (unsigned)(tv.tv_sec * 1000 + tv.tv_usec / 1000); + return (uint32_t)(tv.tv_sec * 1000 + tv.tv_usec / 1000); } -int arg_parse_freq(const char *str) { +int32_t arg_parse_freq(const char *str) { char *tail; - int value = (int)strtol(str, &tail, 10); + int32_t value = (int32_t)strtol(str, &tail, 10); if (tail[0] == 'M' && tail[1] == '\0') { value = value*1000; diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index cf45bbf43..dbd760a52 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -1,8 +1,10 @@ #ifndef HELPER_H #define HELPER_H -unsigned time_ms(); +#include -int arg_parse_freq(const char *str); +uint32_t time_ms(); + +int32_t arg_parse_freq(const char *str); #endif // HELPER_H diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index 79924fc20..a64ec4ef2 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #define __STDC_WANT_LIB_EXT1__ 1 @@ -14,14 +15,14 @@ #include "logging.h" -static int max_level = UDEBUG; +static int32_t max_level = UDEBUG; -int ugly_init(int maximum_threshold) { +int32_t ugly_init(int32_t maximum_threshold) { max_level = maximum_threshold; return (0); } -int ugly_log(int level, const char *tag, const char *format, ...) { +int32_t ugly_log(int32_t level, const char *tag, const char *format, ...) { if (level > max_level) { return (0); } @@ -84,7 +85,7 @@ int ugly_log(int level, const char *tag, const char *format, ...) { * - LIBUSB_LOG_LEVEL_DEBUG (4) : debug and informational messages are * printed to stderr */ -int ugly_libusb_log_level(enum ugly_loglevel v) { +int32_t ugly_libusb_log_level(enum ugly_loglevel v) { #ifdef __FreeBSD__ // FreeBSD includes its own reimplementation of libusb. // Its libusb_set_debug() function expects a lib_debug_level diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index 893a02c24..471933096 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -5,6 +5,8 @@ #ifndef LOGGING_H #define LOGGING_H +#include + #ifdef __cplusplus extern "C" { #endif @@ -22,9 +24,9 @@ enum ugly_loglevel { #define PRINTF_ARRT #endif -int ugly_init(int maximum_threshold); -int ugly_log(int level, const char *tag, const char *format, ...) PRINTF_ARRT; -int ugly_libusb_log_level(enum ugly_loglevel v); +int32_t ugly_init(int32_t maximum_threshold); +int32_t ugly_log(int32_t level, const char *tag, const char *format, ...) PRINTF_ARRT; +int32_t ugly_libusb_log_level(enum ugly_loglevel v); #define UGLY_LOG_FILE (strstr(__FILE__, "/") != NULL ? \ strrchr(__FILE__, '/') + 1 : strstr(__FILE__, "\\") != NULL ? \ diff --git a/src/stlink-lib/map_file.c b/src/stlink-lib/map_file.c index 3bb7555d5..bb83ff7be 100644 --- a/src/stlink-lib/map_file.c +++ b/src/stlink-lib/map_file.c @@ -1,11 +1,12 @@ #include -#include -#include +#include #include -#include -#include +#include +#include +#include "logging.h" #include "map_file.h" +#include "md5.h" #ifndef O_BINARY #define O_BINARY 0 @@ -15,11 +16,11 @@ #define MAX_FILE_SIZE (1<<20) // 1 GB max file size #endif -int map_file(mapped_file_t *mf, const char *path) { - int error = -1; +int32_t map_file(mapped_file_t *mf, const char *path) { + int32_t error = -1; struct stat st; - const int fd = open(path, O_RDONLY | O_BINARY); + const int32_t fd = open(path, O_RDONLY | O_BINARY); if (fd == -1) { fprintf(stderr, "open(%s) == -1\n", path); diff --git a/src/stlink-lib/map_file.h b/src/stlink-lib/map_file.h index f50a201f0..b33ebf5db 100644 --- a/src/stlink-lib/map_file.h +++ b/src/stlink-lib/map_file.h @@ -7,6 +7,8 @@ #ifndef MAP_FILE_H #define MAP_FILE_H +#include + #ifndef O_BINARY #define O_BINARY 0 #endif @@ -26,7 +28,7 @@ typedef struct mapped_file { #define MAPPED_FILE_INITIALIZER \ { NULL, 0 } -int map_file(mapped_file_t *, const char *); +int32_t map_file(mapped_file_t *, const char *); void unmap_file(mapped_file_t *); #endif // MAP_FILE_H diff --git a/src/stlink-lib/md5.c b/src/stlink-lib/md5.c index 4c353bfd6..19ec86b91 100644 --- a/src/stlink-lib/md5.c +++ b/src/stlink-lib/md5.c @@ -5,6 +5,7 @@ * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org */ +#include #include #include "md5.h" @@ -205,7 +206,7 @@ void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */ } if ( BufferSize >= 64 ) { - Buffer = TransformFunction( Context, Buffer, BufferSize & ~(unsigned long)0x3f ); + Buffer = TransformFunction( Context, Buffer, BufferSize & ~(uint32_t)0x3f ); BufferSize &= 0x3f; } diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index f5932a7b9..e2d966b7a 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -1,10 +1,12 @@ +#include #include #include + #include -#include "option_bytes.h" +#include "common.h" #include "common_flash.h" #include "map_file.h" -#include "common.h" +#include "option_bytes.h" /** @@ -13,7 +15,7 @@ * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f0(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register_f0(stlink_t *sl, uint32_t *option_byte) { DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_OBR); return stlink_read_debug32(sl, FLASH_OBR, option_byte); } @@ -26,8 +28,8 @@ int stlink_read_option_control_register_f0(stlink_t *sl, uint32_t *option_byte) * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f0(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { - int ret = 0; +static int32_t stlink_write_option_bytes_f0(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len) { + int32_t ret = 0; if (len < 12 || addr != STM32_F0_OPTION_BYTES_BASE) { WLOG("Only full write of option bytes area is supported\n"); @@ -81,12 +83,12 @@ static int stlink_write_option_bytes_f0(stlink_t *sl, stm32_addr_t addr, uint8_t * @param option_cr * @return 0 on success, -ve on failure. */ -static int stlink_write_option_control_register_f0(stlink_t *sl, uint32_t option_cr) { - int ret = 0; +static int32_t stlink_write_option_control_register_f0(stlink_t *sl, uint32_t option_cr) { + int32_t ret = 0; uint16_t opt_val[8]; - unsigned protection, optiondata; + uint32_t protection, optiondata; uint16_t user_options, user_data, rdp; - unsigned option_offset, user_data_offset; + uint32_t option_offset, user_data_offset; ILOG("Asked to write option control register %#10x to %#010x.\n", option_cr, FLASH_OBR); @@ -166,7 +168,7 @@ static int stlink_write_option_control_register_f0(stlink_t *sl, uint32_t option * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f2(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register_f2(stlink_t *sl, uint32_t *option_byte) { return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); } @@ -176,7 +178,7 @@ int stlink_read_option_control_register_f2(stlink_t *sl, uint32_t *option_byte) * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { return stlink_read_option_control_register_f2(sl, option_byte); } @@ -186,7 +188,7 @@ int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f4(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register_f4(stlink_t *sl, uint32_t *option_byte) { return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); } @@ -196,7 +198,7 @@ int stlink_read_option_control_register_f4(stlink_t *sl, uint32_t *option_byte) * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { return stlink_read_option_control_register_f4(sl, option_byte); } @@ -208,9 +210,9 @@ int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +static int32_t stlink_write_option_bytes_f4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t option_byte; - int ret = 0; + int32_t ret = 0; (void)addr; (void)len; @@ -237,10 +239,10 @@ static int stlink_write_option_bytes_f4(stlink_t *sl, stm32_addr_t addr, uint8_t * @param option_byte * @return 0 on success, -ve on failure. */ -// Since multiple bytes can be read, we read and print all, but one here +// Since multiple bytes can be read, we read and print32_t all, but one here // and then return the last one just like other devices. -int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { - int err = -1; +int32_t stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { + int32_t err = -1; for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), option_byte); if (err == -1) { @@ -264,9 +266,9 @@ int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +static int32_t stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t option_byte; - int ret = 0; + int32_t ret = 0; // Clear errors clear_flash_error(sl); @@ -317,7 +319,7 @@ static int stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_f7(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register_f7(stlink_t *sl, uint32_t *option_byte) { DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_F7_OPTCR); return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); } @@ -328,8 +330,8 @@ int stlink_read_option_control_register_f7(stlink_t *sl, uint32_t *option_byte) * @param option_cr * @return 0 on success, -ve on failure. */ -static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option_cr) { - int ret = 0; +static int32_t stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option_cr) { + int32_t ret = 0; // Clear errors clear_flash_error(sl); @@ -358,7 +360,7 @@ static int stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t *option_byte) { DLOG("@@@@ Read option control register 1 byte from %#10x\n", FLASH_F7_OPTCR1); return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); @@ -370,8 +372,8 @@ int stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t *option_byte) * @param option_cr1 * @return 0 on success, -ve on failure. */ -static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t option_cr1) { - int ret = 0; +static int32_t stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t option_cr1) { + int32_t ret = 0; // Clear errors clear_flash_error(sl); @@ -405,7 +407,7 @@ static int stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t optio * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { DLOG("@@@@ Read option byte boot address\n"); return stlink_read_option_control_register1_f7(sl, option_byte); } @@ -428,7 +430,7 @@ stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_ad * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_gx(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register_gx(stlink_t *sl, uint32_t *option_byte) { return stlink_read_debug32(sl, FLASH_Gx_OPTR, option_byte); } @@ -438,7 +440,7 @@ int stlink_read_option_control_register_gx(stlink_t *sl, uint32_t *option_byte) * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_gx(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_bytes_gx(stlink_t *sl, uint32_t *option_byte) { return stlink_read_option_control_register_gx(sl, option_byte); } @@ -450,10 +452,10 @@ int stlink_read_option_bytes_gx(stlink_t *sl, uint32_t *option_byte) { * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_gx(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +static int32_t stlink_write_option_bytes_gx(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { /* Write options bytes */ uint32_t val; - int ret = 0; + int32_t ret = 0; (void)len; uint32_t data; @@ -488,7 +490,7 @@ static int stlink_write_option_bytes_gx(stlink_t *sl, stm32_addr_t addr, uint8_t * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +static int32_t stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t val; uint32_t data; @@ -556,11 +558,11 @@ static int stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +static int32_t stlink_write_option_bytes_l0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t flash_base = get_stm32l0_flash_base(sl); uint32_t val; uint32_t data; - int ret = 0; + int32_t ret = 0; // Clear errors clear_flash_error(sl); @@ -598,10 +600,10 @@ static int stlink_write_option_bytes_l0(stlink_t *sl, stm32_addr_t addr, uint8_t * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_l4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +static int32_t stlink_write_option_bytes_l4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t val; - int ret = 0; + int32_t ret = 0; (void)addr; (void)len; @@ -638,10 +640,10 @@ static int stlink_write_option_bytes_l4(stlink_t *sl, stm32_addr_t addr, uint8_t * @param len of option bytes * @return 0 on success, -ve on failure. */ -static int stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +static int32_t stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { /* Write options bytes */ uint32_t val; - int ret = 0; + int32_t ret = 0; (void)len; uint32_t data; @@ -686,7 +688,7 @@ static int stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uint8_t * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register_wb(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register_wb(stlink_t *sl, uint32_t *option_byte) { DLOG("@@@@ Read option control register byte from %#10x\n", FLASH_WB_OPTR); return stlink_read_debug32(sl, FLASH_WB_OPTR, option_byte); } @@ -697,8 +699,8 @@ int stlink_read_option_control_register_wb(stlink_t *sl, uint32_t *option_byte) * @param option_cr * @return 0 on success, -ve on failure. */ -static int stlink_write_option_control_register_wb(stlink_t *sl, uint32_t option_cr) { - int ret = 0; +static int32_t stlink_write_option_control_register_wb(stlink_t *sl, uint32_t option_cr) { + int32_t ret = 0; // Clear errors clear_flash_error(sl); @@ -730,7 +732,7 @@ static int stlink_write_option_control_register_wb(stlink_t *sl, uint32_t option * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); return stlink_read_debug32(sl, sl->option_base, option_byte); } @@ -744,8 +746,8 @@ int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { * @param len of option bytes * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { - int ret = -1; +int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { + int32_t ret = -1; if (sl->option_base == 0) { ELOG("Option bytes writing is currently not supported for connected chip\n"); @@ -826,9 +828,9 @@ int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, ui * @param addr of the memory mapped option bytes * @return 0 on success, -ve on failure. */ -int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, stm32_addr_t addr) { +int32_t stlink_fwrite_option_bytes(stlink_t *sl, const char *path, stm32_addr_t addr) { /* Write the file in flash at addr */ - int err; + int32_t err; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { @@ -853,7 +855,7 @@ int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, stm32_addr_t addr * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { if (sl->option_base == 0) { ELOG("Option bytes read is currently not supported for connected chip\n"); return -1; @@ -878,8 +880,8 @@ int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { * @param option_cr * @return 0 on success, -ve on failure. */ -int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) { - int ret = -1; +int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) { + int32_t ret = -1; wait_flash_busy(sl); @@ -928,7 +930,7 @@ int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) { * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_control_register1_32(stlink_t *sl, uint32_t *option_byte) { if (sl->option_base == 0) { ELOG("Option bytes read is currently not supported for connected chip\n"); return -1; @@ -949,8 +951,8 @@ int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t *option_byte) * @param option_cr * @return 0 on success, -ve on failure. */ -int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1) { - int ret = -1; +int32_t stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1) { + int32_t ret = -1; wait_flash_busy(sl); @@ -992,7 +994,7 @@ int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1) * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { if (sl->option_base == 0) { ELOG("Option bytes read is currently not supported for connected chip\n"); return (-1); @@ -1022,7 +1024,7 @@ int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { +int32_t stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { WLOG("About to write option byte %#10x to %#10x.\n", option_byte, sl->option_base); return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, 4); @@ -1034,7 +1036,7 @@ int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { * @param option_byte * @return 0 on success, -ve on failure. */ -int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { +int32_t stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { if (sl->option_base == 0) { ELOG("Option bytes boot address read is currently not supported for connected chip\n"); return -1; @@ -1055,8 +1057,8 @@ int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { * @param option_bytes_boot_add * @return 0 on success, -ve on failure. */ -int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add) { - int ret = -1; +int32_t stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add) { + int32_t ret = -1; wait_flash_busy(sl); diff --git a/src/stlink-lib/option_bytes.h b/src/stlink-lib/option_bytes.h index 9c81fba8a..c0a1c9a6d 100644 --- a/src/stlink-lib/option_bytes.h +++ b/src/stlink-lib/option_bytes.h @@ -7,20 +7,22 @@ #ifndef OPTION_BYTES_H #define OPTION_BYTES_H +#include #include + #include -int stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte); -int stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte); +int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); +int32_t stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); +int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte); +int32_t stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte); -int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); -int stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); -int stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr); -int stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1); +int32_t stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); +int32_t stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); +int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr); +int32_t stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1); -int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); +int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int32_t stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); #endif // OPTION_BYTES_H \ No newline at end of file diff --git a/src/stlink-lib/read_write.c b/src/stlink-lib/read_write.c index efaa5a25f..f9c060bb2 100644 --- a/src/stlink-lib/read_write.c +++ b/src/stlink-lib/read_write.c @@ -1,5 +1,7 @@ +#include #include #include + #include // Endianness @@ -18,17 +20,17 @@ void write_uint16(unsigned char *buf, uint16_t ui) { buf[1] = (uint8_t)(ui >> 8); } -uint32_t read_uint32(const unsigned char *c, const int pt) { +uint32_t read_uint32(const unsigned char *c, const int32_t pt) { return ((uint32_t)c[pt]) | ((uint32_t)c[pt + 1] << 8) | ((uint32_t)c[pt + 2] << 16) | ((uint32_t)c[pt + 3] << 24); } -uint16_t read_uint16(const unsigned char *c, const int pt) { +uint16_t read_uint16(const unsigned char *c, const int32_t pt) { return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); } -int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { - int ret; +int32_t stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { + int32_t ret; ret = sl->backend->read_debug32(sl, addr, data); if (!ret) @@ -37,12 +39,12 @@ int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { return (ret); } -int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { +int32_t stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { DLOG("*** stlink_write_debug32 %#010x to %#010x\n", data, addr); return sl->backend->write_debug32(sl, addr, data); } -int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); if (len % 4 != 0) { @@ -53,7 +55,7 @@ int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { return (sl->backend->write_mem32(sl, addr, len)); } -int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_read_mem32 ***\n"); if (len % 4 != 0) { // !!! never ever: fw gives just wrong values @@ -64,27 +66,27 @@ int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { return (sl->backend->read_mem32(sl, addr, len)); } -int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { DLOG("*** stlink_write_mem8 ***\n"); return (sl->backend->write_mem8(sl, addr, len)); } -int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { +int32_t stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("*** stlink_read_all_regs ***\n"); return (sl->backend->read_all_regs(sl, regp)); } -int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { +int32_t stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("*** stlink_read_all_unsupported_regs ***\n"); return (sl->backend->read_all_unsupported_regs(sl, regp)); } -int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { +int32_t stlink_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { DLOG("*** stlink_write_reg\n"); return (sl->backend->write_reg(sl, reg, idx)); } -int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { +int32_t stlink_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { DLOG("*** stlink_read_reg\n"); DLOG(" (%d) ***\n", r_idx); @@ -96,9 +98,9 @@ int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { return (sl->backend->read_reg(sl, r_idx, regp)); } -int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, +int32_t stlink_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { - int r_convert; + int32_t r_convert; DLOG("*** stlink_read_unsupported_reg\n"); DLOG(" (%d) ***\n", r_idx); @@ -119,9 +121,9 @@ int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, return (sl->backend->read_unsupported_reg(sl, r_convert, regp)); } -int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, +int32_t stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_idx, struct stlink_reg *regp) { - int r_convert; + int32_t r_convert; DLOG("*** stlink_write_unsupported_reg\n"); DLOG(" (%d) ***\n", r_idx); diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index feab40c13..c0f79c7cf 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -75,10 +75,12 @@ */ #define __USE_GNU + #include +#include #include -#include #include +#include #include #include @@ -109,12 +111,12 @@ void _stlink_sg_close(stlink_t *sl) { } } -static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, uint32_t *tag) { +static int32_t get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, uint32_t *tag) { unsigned char csw[13]; memset(csw, 0, sizeof(csw)); - int transferred; - int ret; - int try = 0; + int32_t transferred; + int32_t ret; + int32_t try = 0; do { ret = libusb_bulk_transfer(handle, endpoint, (unsigned char *)&csw, sizeof(csw), @@ -150,13 +152,13 @@ static int get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t end return(rstatus); } -static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { +static int32_t dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { char dbugblah[100]; char *dbugp = dbugblah; dbugp += sprintf(dbugp, "Sending CDB ["); for (uint8_t i = 0; i < cdb_len; i++) { - dbugp += sprintf(dbugp, " %#02x", (unsigned int)cdb[i]); + dbugp += sprintf(dbugp, " %#02x", (uint32_t)cdb[i]); } sprintf(dbugp, "]\n"); @@ -175,7 +177,7 @@ static int dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { * @param expected_rx_size * @return */ -int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, +int32_t send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, uint8_t *cdb, uint8_t cdb_length, uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { DLOG("Sending usb m-s cmd: cdblen:%d, rxsize=%d\n", cdb_length, expected_rx_size); @@ -185,10 +187,10 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint if (tag == 0) { tag = 1; } - int try = 0; - int ret = 0; - int real_transferred; - int i = 0; + int32_t try = 0; + int32_t ret = 0; + int32_t real_transferred; + int32_t i = 0; uint8_t c_buf[STLINK_SG_SIZE]; // tag is allegedly ignored... TODO - verify @@ -209,7 +211,7 @@ int send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint assert(cdb_length <= CDB_SL); memcpy(&(c_buf[i]), cdb, cdb_length); - int sending_length = STLINK_SG_SIZE; + int32_t sending_length = STLINK_SG_SIZE; // send.... do { @@ -254,9 +256,9 @@ static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t } unsigned char sense[REQUEST_SENSE_LENGTH]; - int transferred; - int ret; - int try = 0; + int32_t transferred; + int32_t ret; + int32_t try = 0; do { ret = libusb_bulk_transfer(handle, endpoint_in, sense, sizeof(sense), @@ -273,11 +275,11 @@ static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t } if (transferred != sizeof(sense)) { - WLOG("received unexpected amount of sense: %d != %u\n", transferred, (unsigned)sizeof(sense)); + WLOG("received unexpected amount of sense: %d != %u\n", transferred, (uint32_t)sizeof(sense)); } uint32_t received_tag; - int status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); + int32_t status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); if (status != 0) { WLOG("receiving sense failed with status: %02x\n", status); @@ -301,11 +303,11 @@ static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t * @param length how much to send * @return number of bytes actually sent, or -1 for failures. */ -int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, - unsigned char endpoint_in, unsigned char *cbuf, unsigned int length) { - int ret; - int real_transferred; - int try = 0; +int32_t send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, + unsigned char endpoint_in, unsigned char *cbuf, uint32_t length) { + int32_t ret; + int32_t real_transferred; + int32_t try = 0; do { ret = libusb_bulk_transfer(handle, endpoint_out, cbuf, length, @@ -324,7 +326,7 @@ int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, // now, swallow up the status, so that things behave nicely... uint32_t received_tag; // -ve is for my errors, 0 is good, +ve is libusb sense status bytes - int status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); + int32_t status = get_usb_mass_storage_status(handle, endpoint_in, &received_tag); if (status < 0) { WLOG("receiving status failed: %d\n", status); @@ -343,7 +345,7 @@ int send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, return(real_transferred); } -int stlink_q(stlink_t *sl) { +int32_t stlink_q(stlink_t *sl) { struct stlink_libsg* sg = sl->backend_data; // uint8_t cdb_len = 6; // FIXME varies!!! uint8_t cdb_len = 10; // FIXME varies!!! @@ -355,10 +357,10 @@ int stlink_q(stlink_t *sl) { // now wait for our response... // length copied from stlink-usb... - int rx_length = sl->q_len; - int try = 0; - int real_transferred; - int ret; + int32_t rx_length = sl->q_len; + int32_t try = 0; + int32_t real_transferred; + int32_t ret; if (rx_length > 0) { do { @@ -382,7 +384,7 @@ int stlink_q(stlink_t *sl) { uint32_t received_tag; // -ve is for my errors, 0 is good, +ve is libusb sense status bytes - int status = get_usb_mass_storage_status(sg->usb_handle, sg->ep_rep, &received_tag); + int32_t status = get_usb_mass_storage_status(sg->usb_handle, sg->ep_rep, &received_tag); if (status < 0) { WLOG("receiving status failed: %d\n", status); @@ -428,7 +430,7 @@ void stlink_stat(stlink_t *stl, char *txt) { } } -int _stlink_sg_version(stlink_t *stl) { +int32_t _stlink_sg_version(stlink_t *stl) { struct stlink_libsg *sl = stl->backend_data; clear_cdb(sl); sl->cdb_cmd_blk[0] = STLINK_GET_VERSION; @@ -440,7 +442,7 @@ int _stlink_sg_version(stlink_t *stl) { // Get stlink mode: // STLINK_DEV_DFU_MODE || STLINK_DEV_MASS_MODE || STLINK_DEV_DEBUG_MODE // usb dfu || usb mass || jtag or swd -int _stlink_sg_current_mode(stlink_t *stl) { +int32_t _stlink_sg_current_mode(stlink_t *stl) { struct stlink_libsg *sl = stl->backend_data; clear_cdb(sl); sl->cdb_cmd_blk[0] = STLINK_GET_CURRENT_MODE; @@ -453,7 +455,7 @@ int _stlink_sg_current_mode(stlink_t *stl) { } // exit the mass mode and enter the swd debug mode. -int _stlink_sg_enter_swd_mode(stlink_t *sl) { +int32_t _stlink_sg_enter_swd_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_ENTER; @@ -464,7 +466,7 @@ int _stlink_sg_enter_swd_mode(stlink_t *sl) { // exit the mass mode and enter the jtag debug mode. // (jtag is disabled in the discovery's stlink firmware) -int _stlink_sg_enter_jtag_mode(stlink_t *sl) { +int32_t _stlink_sg_enter_jtag_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_enter_jtag_mode ***\n"); clear_cdb(sg); @@ -476,7 +478,7 @@ int _stlink_sg_enter_jtag_mode(stlink_t *sl) { // XXX kernel driver performs reset, the device temporally disappears // Suspect this is no longer the case when we have ignore on? RECHECK -int _stlink_sg_exit_dfu_mode(stlink_t *sl) { +int32_t _stlink_sg_exit_dfu_mode(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_exit_dfu_mode ***\n"); clear_cdb(sg); @@ -529,9 +531,9 @@ int _stlink_sg_exit_dfu_mode(stlink_t *sl) { */ } -int _stlink_sg_core_id(stlink_t *sl) { +int32_t _stlink_sg_core_id(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; - int ret; + int32_t ret; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_READCOREID; sl->q_len = 4; @@ -545,7 +547,7 @@ int _stlink_sg_core_id(stlink_t *sl) { } // arm-core reset -> halted state. -int _stlink_sg_reset(stlink_t *sl) { +int32_t _stlink_sg_reset(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_RESETSYS; @@ -566,7 +568,7 @@ int _stlink_sg_reset(stlink_t *sl) { } // arm-core reset -> halted state. -int _stlink_sg_jtag_reset(stlink_t *sl, int value) { +int32_t _stlink_sg_jtag_reset(stlink_t *sl, int32_t value) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV2_DRIVE_NRST; @@ -582,7 +584,7 @@ int _stlink_sg_jtag_reset(stlink_t *sl, int value) { } // arm-core status: halted or running. -int _stlink_sg_status(stlink_t *sl) { +int32_t _stlink_sg_status(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_GETSTATUS; @@ -592,7 +594,7 @@ int _stlink_sg_status(stlink_t *sl) { } // force the core into the debug mode -> halted state. -int _stlink_sg_force_debug(stlink_t *sl) { +int32_t _stlink_sg_force_debug(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_FORCEDEBUG; @@ -606,7 +608,7 @@ int _stlink_sg_force_debug(stlink_t *sl) { } // read all arm-core registers. -int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { +int32_t _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -622,7 +624,7 @@ int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { // 0-3 | 4-7 | ... | 60-63 | 64-67 | 68-71 | 72-75 | 76-79 | 80-83 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 - for (int i = 0; i < 16; i++) { + for (int32_t i = 0; i < 16; i++) { regp->r[i] = read_uint32(sl->q_buf, 4 * i); if (sl->verbose > 1) { DLOG("r%2d = 0x%08x\n", i, regp->r[i]); } @@ -649,7 +651,7 @@ int _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 -int _stlink_sg_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { +int32_t _stlink_sg_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_READREG; @@ -694,7 +696,7 @@ int _stlink_sg_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 -int _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int idx) { +int32_t _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_WRITEREG; @@ -730,7 +732,7 @@ void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr) { } // force the core exit the debug mode. -int _stlink_sg_run(stlink_t *sl, enum run_type type) { +int32_t _stlink_sg_run(stlink_t *sl, enum run_type type) { struct stlink_libsg *sg = sl->backend_data; (void)(type); //unused clear_cdb(sg); @@ -746,7 +748,7 @@ int _stlink_sg_run(stlink_t *sl, enum run_type type) { } // step the arm-core. -int _stlink_sg_step(stlink_t *sl) { +int32_t _stlink_sg_step(stlink_t *sl) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_STEPCORE; @@ -761,7 +763,7 @@ int _stlink_sg_step(stlink_t *sl) { // TODO: test and make delegate! // see Cortex-M3 Technical Reference Manual -void stlink_set_hw_bp(stlink_t *sl, int fp_nr, uint32_t addr, int fp) { +void stlink_set_hw_bp(stlink_t *sl, int32_t fp_nr, uint32_t addr, int32_t fp) { DLOG("\n*** stlink_set_hw_bp ***\n"); struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); @@ -779,7 +781,7 @@ void stlink_set_hw_bp(stlink_t *sl, int fp_nr, uint32_t addr, int fp) { } // TODO: test and make delegate! -void stlink_clr_hw_bp(stlink_t *sl, int fp_nr) { +void stlink_clr_hw_bp(stlink_t *sl, int32_t fp_nr) { struct stlink_libsg *sg = sl->backend_data; DLOG("\n*** stlink_clr_hw_bp ***\n"); clear_cdb(sg); @@ -792,7 +794,7 @@ void stlink_clr_hw_bp(stlink_t *sl, int fp_nr) { } // read a "len" bytes to the sl->q_buf from the memory, max 6kB (6144 bytes) -int _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_READMEM_32BIT; @@ -816,9 +818,9 @@ int _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { } // write a "len" bytes from the sl->q_buf to the memory, max 64 Bytes. -int _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; - int ret; + int32_t ret; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_WRITEMEM_8BIT; @@ -844,9 +846,9 @@ int _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { } // write a "len" bytes from the sl->q_buf to the memory, max Q_BUF_LEN bytes. -int _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libsg *sg = sl->backend_data; - int ret; + int32_t ret; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_WRITEMEM_32BIT; @@ -872,7 +874,7 @@ int _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { } // write one DWORD data to memory -int _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { +int32_t _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; @@ -884,7 +886,7 @@ int _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { } // read one DWORD data from memory -int _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { +int32_t _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { struct stlink_libsg *sg = sl->backend_data; clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV2_READDEBUGREG; @@ -899,7 +901,7 @@ int _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { } // exit the jtag or swd mode and enter the mass mode. -int _stlink_sg_exit_debug_mode(stlink_t *stl) { +int32_t _stlink_sg_exit_debug_mode(stlink_t *stl) { if (stl) { struct stlink_libsg* sl = stl->backend_data; clear_cdb(sl); @@ -950,7 +952,7 @@ static stlink_backend_t _stlink_sg_backend = { NULL, // trace_read }; -static stlink_t* stlink_open(const int verbose) { +static stlink_t* stlink_open(const int32_t verbose) { stlink_t *sl = malloc(sizeof(stlink_t)); struct stlink_libsg *slsg = malloc(sizeof(struct stlink_libsg)); @@ -993,7 +995,7 @@ static stlink_t* stlink_open(const int verbose) { // TODO: Could read the interface config descriptor, and assert lots of the assumptions // assumption: numInterfaces is always 1... if (libusb_kernel_driver_active(slsg->usb_handle, 0) == 1) { - int r = libusb_detach_kernel_driver(slsg->usb_handle, 0); + int32_t r = libusb_detach_kernel_driver(slsg->usb_handle, 0); if (r < 0) { WLOG("libusb_detach_kernel_driver(() error %s\n", strerror(-r)); @@ -1007,7 +1009,7 @@ static stlink_t* stlink_open(const int verbose) { DLOG("Kernel driver was successfully detached\n"); } - int config; + int32_t config; if (libusb_get_configuration(slsg->usb_handle, &config)) { /* this may fail for a previous configured device */ @@ -1062,7 +1064,7 @@ static stlink_t* stlink_open(const int verbose) { } -stlink_t* stlink_v1_open_inner(const int verbose) { +stlink_t* stlink_v1_open_inner(const int32_t verbose) { ugly_init(verbose); stlink_t *sl = stlink_open(verbose); @@ -1105,7 +1107,7 @@ stlink_t* stlink_v1_open_inner(const int verbose) { return(sl); } -stlink_t* stlink_v1_open(const int verbose, int reset) { +stlink_t* stlink_v1_open(const int32_t verbose, int32_t reset) { stlink_t *sl = stlink_v1_open_inner(verbose); if (sl == NULL) { return(NULL); } diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index 5ba809f59..d4792c49a 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -6,8 +6,10 @@ #ifndef SG_H #define SG_H +#include + #include -#include +#include "libusb_settings.h" /* Device access */ #define RDWR 0 @@ -35,15 +37,15 @@ struct stlink_libsg { libusb_context* libusb_ctx; libusb_device_handle *usb_handle; - unsigned ep_rep; - unsigned ep_req; + uint32_t ep_rep; + uint32_t ep_req; - int sg_fd; - int do_scsi_pt_err; + int32_t sg_fd; + int32_t do_scsi_pt_err; unsigned char cdb_cmd_blk[CDB_SL]; - int q_data_dir; // Q_DATA_IN, Q_DATA_OUT + int32_t q_data_dir; // Q_DATA_IN, Q_DATA_OUT // the start of the query data in the device memory space uint32_t q_addr; @@ -54,6 +56,6 @@ struct stlink_libsg { struct stlink_reg reg; }; -stlink_t* stlink_v1_open(const int verbose, int reset); +stlink_t* stlink_v1_open(const int32_t verbose, int32_t reset); #endif // SG_H diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 2e99e82be..d404c2e94 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1,8 +1,8 @@ +#include +#include #include #include #include -#include -#include #if !defined(_MSC_VER) #include @@ -17,7 +17,7 @@ #endif #include -#include +#include "helper.h" #include "usb.h" enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; @@ -26,11 +26,11 @@ static inline uint32_t le_to_h_u32(const uint8_t* buf) { return((uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24)); } -static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, uint32_t khz) { - unsigned int i; - int speed_index = -1; - int speed_diff = INT_MAX; - int last_valid_speed = -1; +static int32_t _stlink_match_speed_map(const uint32_t *map, uint32_t map_size, uint32_t khz) { + uint32_t i; + int32_t speed_index = -1; + int32_t speed_diff = INT_MAX; + int32_t last_valid_speed = -1; bool match = true; for (i = 0; i < map_size; i++) { @@ -42,7 +42,7 @@ static int _stlink_match_speed_map(const uint32_t *map, unsigned int map_size, u speed_index = i; break; } else { - int current_diff = khz - map[i]; + int32_t current_diff = khz - map[i]; // get abs value for comparison current_diff = (current_diff > 0) ? current_diff : -current_diff; @@ -83,26 +83,26 @@ void _stlink_usb_close(stlink_t* sl) { } } -ssize_t send_recv(struct stlink_libusb* handle, int terminate, +ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, - size_t rxsize, int check_error, const char *cmd) { + size_t rxsize, int32_t check_error, const char *cmd) { // Note: txbuf and rxbuf can point to the same area - int res, t, retry = 0; + int32_t res, t, retry = 0; while (1) { res = 0; - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int)txsize, &res, 3000); + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_req, txbuf, (int32_t)txsize, &res, 3000); if (t) { ELOG("%s send request failed: %s\n", cmd, libusb_error_name(t)); return(-1); } else if ((size_t)res != txsize) { ELOG("%s send request wrote %u bytes, instead of %u\n", - cmd, (unsigned int)res, (unsigned int)txsize); + cmd, (uint32_t)res, (uint32_t)txsize); } if (rxsize != 0) { - t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int)rxsize, &res, 3000); + t = libusb_bulk_transfer(handle->usb_handle, handle->ep_rep, rxbuf, (int32_t)rxsize, &res, 3000); if (t) { ELOG("%s read reply failed: %s\n", cmd, libusb_error_name(t)); @@ -116,7 +116,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int terminate, case STLINK_DEBUG_ERR_AP_WAIT: case STLINK_DEBUG_ERR_DP_WAIT: if (check_error == CMD_CHECK_RETRY && retry < 3) { - unsigned int delay_us = (1<backend_data; unsigned char* const cmd = sl->c_buf; - int i = 0; + int32_t i = 0; memset(cmd, 0, sizeof(sl->c_buf)); if (slu->protocoll == 1) { @@ -189,13 +189,13 @@ static int fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t return(i); } -int _stlink_usb_version(stlink_t *sl) { +int32_t _stlink_usb_version(stlink_t *sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t rep_len; - int i; + int32_t i; if (sl->version.stlink_v == 3) { // STLINK-V3 version is determined by another command @@ -219,9 +219,9 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t rep_len = 8; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); uint32_t factor, reading; - int voltage; + int32_t voltage; cmd[i++] = STLINK_GET_TARGET_VOLTAGE; @@ -238,14 +238,14 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { return(voltage); } -int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { +int32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const rdata = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - const int rep_len = 8; + const int32_t rep_len = 8; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_READDEBUGREG; write_uint32(&cmd[i], addr); @@ -260,14 +260,14 @@ int _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { return(0); } -int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { +int32_t _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const rdata = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - const int rep_len = 2; + const int32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_WRITEDEBUGREG; write_uint32(&cmd[i], addr); @@ -277,13 +277,13 @@ int _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { return(size<0?-1:0); } -int _stlink_usb_get_rw_status(stlink_t *sl) { +int32_t _stlink_usb_get_rw_status(stlink_t *sl) { if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return(0); } unsigned char* const rdata = sl->q_buf; struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; - int i; + int32_t i; int16_t ret = 0; i = fill_command(sl, SG_DXFER_FROM_DEV, 12); @@ -300,11 +300,11 @@ int _stlink_usb_get_rw_status(stlink_t *sl) { return(ret<0?-1:0); } -int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; - int i, ret; + int32_t i, ret; i = fill_command(sl, SG_DXFER_TO_DEV, len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -322,11 +322,11 @@ int _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { return(_stlink_usb_get_rw_status(sl)); } -int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; - int i, ret; + int32_t i, ret; if ((sl->version.jtag_api < STLINK_JTAG_API_V3 && len > 64) || (sl->version.jtag_api >= STLINK_JTAG_API_V3 && len > 512)) { @@ -351,13 +351,13 @@ int _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { } -int _stlink_usb_current_mode(stlink_t * sl) { +int32_t _stlink_usb_current_mode(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; unsigned char* const data = sl->q_buf; ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t rep_len = 2; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_GET_CURRENT_MODE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_CURRENT_MODE"); @@ -369,13 +369,13 @@ int _stlink_usb_current_mode(stlink_t * sl) { return(sl->q_buf[0]); } -int _stlink_usb_core_id(stlink_t * sl) { +int32_t _stlink_usb_core_id(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; unsigned char* const data = sl->q_buf; ssize_t size; - int offset, rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 12; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t offset, rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 12; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -398,8 +398,8 @@ int _stlink_usb_core_id(stlink_t * sl) { return(0); } -int _stlink_usb_status_v2(stlink_t *sl) { - int result; +int32_t _stlink_usb_status_v2(stlink_t *sl) { + int32_t result; uint32_t status = 0; result = _stlink_usb_read_debug32(sl, STLINK_REG_DHCSR, &status); @@ -420,15 +420,15 @@ int _stlink_usb_status_v2(stlink_t *sl) { return(result); } -int _stlink_usb_status(stlink_t * sl) { +int32_t _stlink_usb_status(stlink_t * sl) { if (sl->version.jtag_api != STLINK_JTAG_API_V1) { return(_stlink_usb_status_v2(sl)); } struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t rep_len = 2; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_GETSTATUS; @@ -449,10 +449,10 @@ int _stlink_usb_status(stlink_t * sl) { return(size<0?-1:0); } -int _stlink_usb_force_debug(stlink_t *sl) { +int32_t _stlink_usb_force_debug(stlink_t *sl) { struct stlink_libusb *slu = sl->backend_data; - int res; + int32_t res; if (sl->version.jtag_api != STLINK_JTAG_API_V1) { res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); @@ -462,8 +462,8 @@ int _stlink_usb_force_debug(stlink_t *sl) { unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t rep_len = 2; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_FORCEDEBUG; @@ -472,13 +472,13 @@ int _stlink_usb_force_debug(stlink_t *sl) { return(size<0?-1:0); } -int _stlink_usb_enter_swd_mode(stlink_t * sl) { +int32_t _stlink_usb_enter_swd_mode(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; ssize_t size; unsigned char* const data = sl->q_buf; const uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; // select correct API-Version for entering SWD mode: V1 API (0x20) or V2 API (0x30). @@ -489,11 +489,11 @@ int _stlink_usb_enter_swd_mode(stlink_t * sl) { return(size<0?-1:0); } -int _stlink_usb_exit_dfu_mode(stlink_t* sl) { +int32_t _stlink_usb_exit_dfu_mode(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, 0); cmd[i++] = STLINK_DFU_COMMAND; cmd[i++] = STLINK_DFU_EXIT; @@ -503,12 +503,12 @@ int _stlink_usb_exit_dfu_mode(stlink_t* sl) { } -int _stlink_usb_reset(stlink_t * sl) { +int32_t _stlink_usb_reset(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int i, rep_len = 2; + int32_t i, rep_len = 2; // send reset command i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); @@ -525,13 +525,13 @@ int _stlink_usb_reset(stlink_t * sl) { return(size<0?-1:0); } -int _stlink_usb_jtag_reset(stlink_t * sl, int value) { +int32_t _stlink_usb_jtag_reset(stlink_t * sl, int32_t value) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t rep_len = 2; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_DRIVE_NRST; @@ -542,7 +542,7 @@ int _stlink_usb_jtag_reset(stlink_t * sl, int value) { } -int _stlink_usb_step(stlink_t* sl) { +int32_t _stlink_usb_step(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; if (sl->version.jtag_api != STLINK_JTAG_API_V1) { @@ -558,8 +558,8 @@ int _stlink_usb_step(stlink_t* sl) { unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t rep_len = 2; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_STEPCORE; @@ -573,10 +573,10 @@ int _stlink_usb_step(stlink_t* sl) { * @param sl * @param type */ -int _stlink_usb_run(stlink_t* sl, enum run_type type) { +int32_t _stlink_usb_run(stlink_t* sl, enum run_type type) { struct stlink_libusb * const slu = sl->backend_data; - int res; + int32_t res; if (sl->version.jtag_api != STLINK_JTAG_API_V1) { res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, @@ -589,8 +589,8 @@ int _stlink_usb_run(stlink_t* sl, enum run_type type) { unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t rep_len = 2; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_RUNCORE; @@ -599,20 +599,20 @@ int _stlink_usb_run(stlink_t* sl, enum run_type type) { return(size<0?-1:0); } -int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { +int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int rep_len = 2; - int i; + int32_t rep_len = 2; + int32_t i; // clock speed only supported by stlink/v2 and for firmware >= 22 if (sl->version.stlink_v == 2 && sl->version.jtag_v >= 22) { uint16_t clk_divisor; if (clk_freq) { const uint32_t map[] = {5, 15, 25, 50, 100, 125, 240, 480, 950, 1200, 1800, 4000}; - int speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); + int32_t speed_index = _stlink_match_speed_map(map, STLINK_ARRAY_SIZE(map), clk_freq); switch (map[speed_index]) { case 5: clk_divisor = STLINK_SWDCLK_5KHZ_DIVISOR; break; case 15: clk_divisor = STLINK_SWDCLK_15KHZ_DIVISOR; break; @@ -641,7 +641,7 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { return(size<0?-1:0); } else if (sl->version.stlink_v == 3) { - int speed_index; + int32_t speed_index; uint32_t map[STLINK_V3_MAX_FREQ_NB]; i = fill_command(sl, SG_DXFER_FROM_DEV, 16); @@ -654,7 +654,7 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { return(-1); } - int speeds_size = data[8]; + int32_t speeds_size = data[8]; if (speeds_size > STLINK_V3_MAX_FREQ_NB) { speeds_size = STLINK_V3_MAX_FREQ_NB; } @@ -688,11 +688,11 @@ int _stlink_usb_set_swdclk(stlink_t* sl, int clk_freq) { return(-1); } -int _stlink_usb_exit_debug_mode(stlink_t *sl) { +int32_t _stlink_usb_exit_debug_mode(stlink_t *sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, 0); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, 0); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_EXIT; @@ -702,12 +702,12 @@ int _stlink_usb_exit_debug_mode(stlink_t *sl) { return(size<0?-1:0); } -int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { +int32_t _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; - int i = fill_command(sl, SG_DXFER_FROM_DEV, len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_READMEM_32BIT; @@ -719,19 +719,19 @@ int _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { return(-1); } - sl->q_len = (int)size; + sl->q_len = (int32_t)size; stlink_print_data(sl); return(0); } -int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { +int32_t _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; unsigned char* const data = sl->q_buf; ssize_t size; uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 84 : 88; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -749,8 +749,8 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { /* V1: regs data from offset 0 */ /* V2: status at offset 0, regs data from offset 4 */ - int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; - sl->q_len = (int)size; + int32_t reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; + sl->q_len = (int32_t)size; stlink_print_data(sl); for (i = 0; i < 16; i++) regp->r[i] = read_uint32(sl->q_buf, reg_offset + i * 4); @@ -772,15 +772,15 @@ int _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { return(0); } -int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { +int32_t _stlink_usb_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t r; uint32_t rep_len = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 4 : 8; - int reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t reg_offset = sl->version.jtag_api == STLINK_JTAG_API_V1 ? 0 : 4; + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -797,7 +797,7 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { return(-1); } - sl->q_len = (int)size; + sl->q_len = (int32_t)size; stlink_print_data(sl); r = read_uint32(sl->q_buf, reg_offset); DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); @@ -826,13 +826,13 @@ int _stlink_usb_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ -int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { +int32_t _stlink_usb_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { uint32_t r; - int ret; + int32_t ret; sl->q_buf[0] = (unsigned char)r_idx; - for (int i = 1; i < 4; i++) sl->q_buf[i] = 0; + for (int32_t i = 1; i < 4; i++) sl->q_buf[i] = 0; ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); @@ -863,8 +863,8 @@ int _stlink_usb_read_unsupported_reg(stlink_t *sl, int r_idx, struct stlink_reg return(0); } -int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { - int ret; +int32_t _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { + int32_t ret; ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); @@ -874,7 +874,7 @@ int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) if (ret == -1) { return(ret); } - for (int i = 0; i < 32; i++) { + for (int32_t i = 0; i < 32; i++) { ret = _stlink_usb_read_unsupported_reg(sl, 0x40 + i, regp); if (ret == -1) { return(ret); } @@ -884,8 +884,8 @@ int _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ -int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, struct stlink_reg *regp) { - int ret; +int32_t _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_idx, struct stlink_reg *regp) { + int32_t ret; if (r_idx >= 0x1C && r_idx <= 0x1F) { // primask, basepri, faultmask, or control /* These are held in the same register */ @@ -939,13 +939,13 @@ int _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, str return(_stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4)); } -int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { +int32_t _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; @@ -962,14 +962,14 @@ int _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int idx) { return(size<0?-1:0); } -int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { +int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); @@ -980,14 +980,14 @@ int _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { return(size<0?-1:0); } -int _stlink_usb_disable_trace(stlink_t* sl) { +int32_t _stlink_usb_disable_trace(stlink_t* sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_STOP_TRACE_RX; @@ -996,12 +996,12 @@ int _stlink_usb_disable_trace(stlink_t* sl) { return(size<0?-1:0); } -int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { +int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; uint32_t rep_len = 2; - int i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); + int32_t i = fill_command(sl, SG_DXFER_FROM_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_GET_TRACE_NB; @@ -1010,7 +1010,7 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { if (send_size < 0) { return(-1); } else if (send_size != 2) { - ELOG("STLINK_DEBUG_APIV2_GET_TRACE_NB reply size %d\n", (int)send_size); + ELOG("STLINK_DEBUG_APIV2_GET_TRACE_NB reply size %d\n", (int32_t)send_size); return(-1); } @@ -1022,10 +1022,10 @@ int _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { } if (trace_count != 0) { - int res = 0; - int t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); + int32_t res = 0; + int32_t t = libusb_bulk_transfer(slu->usb_handle, slu->ep_trace, buf, trace_count, &res, 3000); - if (t || res != (int)trace_count) { + if (t || res != (int32_t)trace_count) { ELOG("read_trace read error %d\n", t); return(-1); } @@ -1075,7 +1075,7 @@ size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_d serial[0] = '\0'; /* get the LANGID from String Descriptor Zero */ - int ret = libusb_get_string_descriptor(handle, 0, 0, desc_serial, sizeof(desc_serial)); + int32_t ret = libusb_get_string_descriptor(handle, 0, 0, desc_serial, sizeof(desc_serial)); if (ret < 4) return 0; uint32_t langid = desc_serial[2] | (desc_serial[3] << 8); @@ -1094,7 +1094,7 @@ size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_d if (ret < 0) return 0; } else if (len == ((STLINK_SERIAL_LENGTH / 2 + 1) * 2)) { /* len == 26 */ /* fix-up the buggy serial */ - for (unsigned int i = 0; i < STLINK_SERIAL_LENGTH; i += 2) + for (uint32_t i = 0; i < STLINK_SERIAL_LENGTH; i += 2) sprintf(serial + i, "%02X", desc_serial[i + 2]); serial[STLINK_SERIAL_LENGTH] = '\0'; } else { @@ -1104,11 +1104,11 @@ size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_d return strlen(serial); } -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq) { +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int32_t freq) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; - int ret = -1; - int config; + int32_t ret = -1; + int32_t config; sl = calloc(1, sizeof(stlink_t)); if (sl == NULL) { goto on_malloc_error; } @@ -1246,7 +1246,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, // initialize stlink version (sl->version) stlink_version(sl); - int mode = stlink_current_mode(sl); + int32_t mode = stlink_current_mode(sl); if (mode == STLINK_DEV_DFU_MODE) { DLOG("-- exit_dfu_mode\n"); _stlink_usb_exit_dfu_mode(sl); @@ -1288,17 +1288,17 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, return(NULL); } -static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int freq) { +static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int32_t freq) { stlink_t **_sldevs; libusb_device *dev; - int i = 0; + int32_t i = 0; size_t slcnt = 0; size_t slcur = 0; /* Count STLINKs */ while ((dev = devs[i++]) != NULL) { struct libusb_device_descriptor desc; - int ret = libusb_get_device_descriptor(dev, &desc); + int32_t ret = libusb_get_device_descriptor(dev, &desc); if (ret < 0) { WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); @@ -1327,7 +1327,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], e while ((dev = devs[i++]) != NULL) { struct libusb_device_descriptor desc; - int ret = libusb_get_device_descriptor(dev, &desc); + int32_t ret = libusb_get_device_descriptor(dev, &desc); if (ret < 0) { WLOG("failed to get libusb device descriptor (libusb error: %d)\n", ret); @@ -1372,12 +1372,12 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], e return(slcur); } -size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq) { +size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t freq) { libusb_device **devs; stlink_t **sldevs; size_t slcnt = 0; - int r; + int32_t r; ssize_t cnt; r = libusb_init(NULL); diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 8c98bcaf4..b5c1835ec 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -7,9 +7,10 @@ #define USB_H #include +#include #include -#include +#include "libusb_settings.h" #include "logging.h" #define STLINK_USB_VID_ST 0x0483 @@ -49,12 +50,12 @@ struct stlink_libusb { libusb_context* libusb_ctx; libusb_device_handle* usb_handle; - unsigned int ep_req; - unsigned int ep_rep; - unsigned int ep_trace; - int protocoll; - unsigned int sg_transfer_idx; - unsigned int cmd_len; + uint32_t ep_req; + uint32_t ep_rep; + uint32_t ep_trace; + int32_t protocoll; + uint32_t sg_transfer_idx; + uint32_t cmd_len; }; /** @@ -66,8 +67,8 @@ struct stlink_libusb { * @retval !NULL Stlink found and ready to use */ -stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int freq); -size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int freq); +stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int32_t freq); +size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t freq); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); #endif // USB_H diff --git a/src/win32/getopt/getopt.c b/src/win32/getopt/getopt.c index ff0a2fd91..7bc8d2d20 100644 --- a/src/win32/getopt/getopt.c +++ b/src/win32/getopt/getopt.c @@ -1,18 +1,19 @@ #include +#include #include #include "getopt.h" #if !defined(_MSC_VER) -const int no_argument = 0; -const int required_argument = 1; -const int optional_argument = 2; +const int32_t no_argument = 0; +const int32_t required_argument = 1; +const int32_t optional_argument = 2; #endif char* optarg; -int optopt; -int optind = 1; // The variable optind [...] shall be initialized to 1 by the system -int opterr; +int32_t optopt; +int32_t optind = 1; // The variable optind [...] shall be initialized to 1 by the system +int32_t opterr; static char* optcursor = NULL; @@ -24,8 +25,8 @@ static char* optcursor = NULL; * [2] http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html * [3] http://www.freebsd.org/cgi/man.cgi?query=getopt&sektion=3&manpath=FreeBSD+9.0-RELEASE */ -int getopt(int argc, char* const argv[], const char* optstring) { - int optchar = -1; +int32_t getopt(int32_t argc, char* const argv[], const char* optstring) { + int32_t optchar = -1; const char* optdecl = NULL; optarg = NULL; @@ -125,17 +126,17 @@ int getopt(int argc, char* const argv[], const char* optstring) { } /* Implementation based on http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html */ -int getopt_long(int argc, +int32_t getopt_long(int32_t argc, char* const argv[], const char* optstring, const struct option* longopts, int* longindex) { const struct option* o = longopts; const struct option* match = NULL; - int num_matches = 0; + int32_t num_matches = 0; size_t argument_name_length = 0; const char* current_argument = NULL; - int retval = -1; + int32_t retval = -1; optarg = NULL; optopt = 0; diff --git a/src/win32/getopt/getopt.h b/src/win32/getopt/getopt.h index b1dd35ef1..4f21e69dc 100644 --- a/src/win32/getopt/getopt.h +++ b/src/win32/getopt/getopt.h @@ -1,6 +1,8 @@ #ifndef GETOPT_H #define GETOPT_H +#include + #if defined(__cplusplus) extern "C" { #endif @@ -11,24 +13,24 @@ extern "C" { #define required_argument 1 #define optional_argument 2 #else -extern const int no_argument; -extern const int required_argument; -extern const int optional_argument; +extern const int32_t no_argument; +extern const int32_t required_argument; +extern const int32_t optional_argument; #endif extern char* optarg; -extern int optind, opterr, optopt; +extern int32_t optind, opterr, optopt; struct option { const char* name; - int has_arg; + int32_t has_arg; int* flag; - int val; + int32_t val; }; -int getopt(int argc, char* const argv[], const char* optstring); +int32_t getopt(int32_t argc, char* const argv[], const char* optstring); -int getopt_long(int argc, +int32_t getopt_long(int32_t argc, char* const argv[], const char* optstring, const struct option* longopts, diff --git a/src/win32/mmap.c b/src/win32/mmap.c index d702a78f6..ea8a3cb37 100644 --- a/src/win32/mmap.c +++ b/src/win32/mmap.c @@ -1,11 +1,12 @@ -#include -#include +#include #include +#include #include +#include #include "mmap.h" -void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offset) { +void *mmap (void *addr, size_t len, int32_t prot, int32_t flags, int32_t fd, int64_t offset) { void *buf; ssize_t count; @@ -31,7 +32,7 @@ void *mmap (void *addr, size_t len, int prot, int flags, int fd, long long offse (void)flags; } -int munmap (void *addr, size_t len) { +int32_t munmap (void *addr, size_t len) { free (addr); return(0); (void)len; diff --git a/src/win32/mmap.h b/src/win32/mmap.h index c6390aede..e8bbab0bc 100644 --- a/src/win32/mmap.h +++ b/src/win32/mmap.h @@ -1,6 +1,8 @@ #ifndef MMAP_H #define MMAP_H +#include + #ifdef STLINK_HAVE_SYS_MMAN_H #include #else @@ -13,8 +15,8 @@ #define MAP_ANONYMOUS (1 << 5) #define MAP_FAILED ((void *)-1) -void *mmap(void *addr, size_t len, int prot, int flags, int fd, long long offset); -int munmap(void *addr, size_t len); +void *mmap(void *addr, size_t len, int32_t prot, int32_t flags, int32_t fd, int64_t offset); +int32_t munmap(void *addr, size_t len); #endif // STLINK_HAVE_SYS_MMAN_H diff --git a/src/win32/sys_time.c b/src/win32/sys_time.c index 422731b3f..a09d8df67 100644 --- a/src/win32/sys_time.c +++ b/src/win32/sys_time.c @@ -1,3 +1,5 @@ +#include + #include "sys_time.h" #ifndef STLINK_HAVE_SYS_TIME_H @@ -5,18 +7,18 @@ #include /* Simple gettimeofday implementation without converting Windows time to Linux time */ -int gettimeofday(struct timeval *tv, struct timezone *tz) { +int32_t gettimeofday(struct timeval *tv, struct timezone *tz) { FILETIME ftime; ULARGE_INTEGER ulint; - static int tzflag = 0; + static int32_t tzflag = 0; if(NULL != tv) { GetSystemTimeAsFileTime(&ftime); ulint.LowPart = ftime.dwLowDateTime; ulint.HighPart = ftime.dwHighDateTime; - tv->tv_sec = (long)(ulint.QuadPart / 10000000L); - tv->tv_usec = (long)(ulint.QuadPart % 10000000L); + tv->tv_sec = (int32_t)(ulint.QuadPart / 10000000L); + tv->tv_usec = (int32_t)(ulint.QuadPart % 10000000L); } if(NULL != tz) { diff --git a/src/win32/sys_time.h b/src/win32/sys_time.h index 98ecaddfc..ca6e0a761 100644 --- a/src/win32/sys_time.h +++ b/src/win32/sys_time.h @@ -1,6 +1,8 @@ #ifndef SYS_TIME_H #define SYS_TIME_H +#include + #ifdef STLINK_HAVE_SYS_TIME_H #include @@ -10,11 +12,11 @@ #include struct timezone { - int tz_minuteswest; - int tz_dsttime; + int32_t tz_minuteswest; + int32_t tz_dsttime; }; -int gettimeofday(struct timeval *tv, struct timezone *tz); +int32_t gettimeofday(struct timeval *tv, struct timezone *tz); #endif // STLINK_HAVE_SYS_TIME_H diff --git a/src/win32/unistd/unistd.h b/src/win32/unistd/unistd.h index 5f2b5433b..d61b75b67 100644 --- a/src/win32/unistd/unistd.h +++ b/src/win32/unistd/unistd.h @@ -6,8 +6,9 @@ * Please add functionality as needed. */ -#include +#include #include +#include #if defined(_MSC_VER) #pragma warning(push) @@ -69,7 +70,7 @@ typedef unsigned __int32 uint32_t; typedef unsigned __int64 uint64_t; #ifndef STLINK_HAVE_UNISTD_H -int usleep(unsigned int waitTime); +int32_t usleep(uint32_t waitTime); #endif #endif // UNISTD_H diff --git a/src/win32/win32_socket.c b/src/win32/win32_socket.c index 3f4d28bbd..46b4532a7 100644 --- a/src/win32/win32_socket.c +++ b/src/win32/win32_socket.c @@ -1,5 +1,7 @@ #if defined(_WIN32) +#include + #include "win32_socket.h" #undef socket @@ -11,11 +13,11 @@ #include #include -int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { +int32_t win32_poll(struct pollfd *fds, uint32_t nfds, int32_t timo) { struct timeval timeout, *toptr; fd_set ifds, ofds, efds, *ip, *op; - unsigned int i; - int rc; + uint32_t i; + int32_t rc; #ifdef _MSC_VER #pragma warning(disable: 4548) @@ -99,7 +101,7 @@ int win32_poll(struct pollfd *fds, unsigned int nfds, int timo) { return(rc); } -static void set_connect_errno(int winsock_err) { +static void set_connect_errno(int32_t winsock_err) { switch (winsock_err) { case WSAEINVAL: case WSAEALREADY: @@ -112,7 +114,7 @@ static void set_connect_errno(int winsock_err) { } } -static void set_socket_errno(int winsock_err) { +static void set_socket_errno(int32_t winsock_err) { switch (winsock_err) { case WSAEWOULDBLOCK: errno = EAGAIN; @@ -128,7 +130,7 @@ static void set_socket_errno(int winsock_err) { * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ -SOCKET win32_socket(int domain, int type, int protocol) { +SOCKET win32_socket(int32_t domain, int32_t type, int32_t protocol) { SOCKET fd = socket(domain, type, protocol); if (fd == INVALID_SOCKET) { set_socket_errno(WSAGetLastError()); } @@ -141,8 +143,8 @@ SOCKET win32_socket(int domain, int type, int protocol) { * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ -int win32_connect(SOCKET fd, struct sockaddr *addr, socklen_t addr_len) { - int rc = connect(fd, addr, addr_len); +int32_t win32_connect(SOCKET fd, struct sockaddr *addr, socklen_t addr_len) { + int32_t rc = connect(fd, addr, addr_len); assert(rc == 0 || rc == SOCKET_ERROR); if (rc == SOCKET_ERROR) { set_connect_errno(WSAGetLastError()); } @@ -169,8 +171,8 @@ SOCKET win32_accept(SOCKET fd, struct sockaddr *addr, socklen_t *addr_len) { * The purpose of this wrapper is to ensure that the global errno symbol is set if an error occurs, * even if we are using winsock. */ -int win32_shutdown(SOCKET fd, int mode) { - int rc = shutdown(fd, mode); +int32_t win32_shutdown(SOCKET fd, int32_t mode) { + int32_t rc = shutdown(fd, mode); assert(rc == 0 || rc == SOCKET_ERROR); if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } @@ -178,24 +180,24 @@ int win32_shutdown(SOCKET fd, int mode) { return(rc); } -int win32_close_socket(SOCKET fd) { - int rc = closesocket(fd); +int32_t win32_close_socket(SOCKET fd) { + int32_t rc = closesocket(fd); if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } return(rc); } -ssize_t win32_write_socket(SOCKET fd, void *buf, int n) { - int rc = send(fd, buf, n, 0); +ssize_t win32_write_socket(SOCKET fd, void *buf, int32_t n) { + int32_t rc = send(fd, buf, n, 0); if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } return(rc); } -ssize_t win32_read_socket(SOCKET fd, void *buf, int n) { - int rc = recv(fd, buf, n, 0); +ssize_t win32_read_socket(SOCKET fd, void *buf, int32_t n) { + int32_t rc = recv(fd, buf, n, 0); if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } @@ -205,7 +207,7 @@ ssize_t win32_read_socket(SOCKET fd, void *buf, int n) { char * win32_strtok_r(char *s, const char *delim, char **lasts) { register char *spanp; - register int c, sc; + register int32_t c, sc; char *tok; @@ -254,7 +256,7 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) { char *win32_strsep (char **stringp, const char *delim) { register char *s; register const char *spanp; - register int c, sc; + register int32_t c, sc; char *tok; if ((s = *stringp) == NULL) { @@ -284,7 +286,7 @@ char *win32_strsep (char **stringp, const char *delim) { } #ifndef STLINK_HAVE_UNISTD_H -int usleep(unsigned int waitTime) { +int32_t usleep(uint32_t waitTime) { if (waitTime >= 1000) { /* Don't do long busy-waits. * However much it seems like the QPC code would be more accurate, diff --git a/src/win32/win32_socket.h b/src/win32/win32_socket.h index 614046a6f..e7ea398e9 100644 --- a/src/win32/win32_socket.h +++ b/src/win32/win32_socket.h @@ -1,5 +1,7 @@ #if defined(_WIN32) +#include + #define _USE_W32_SOCKETS 1 #if defined(_MSC_VER) @@ -35,8 +37,8 @@ #define POLLNVAL 0x0020 /* Invalid request: fd not open */ struct pollfd { SOCKET fd; /* file descriptor */ - short events; /* requested events */ - short revents; /* returned events */ + int16_t events; /* requested events */ + int16_t revents; /* returned events */ }; #endif #define poll(x, y, z) win32_poll(x, y, z) @@ -54,15 +56,15 @@ struct pollfd { #define read(x, y, z) win32_read_socket(x, y, z) #define write(x, y, z) win32_write_socket(x, y, z) -/* Winsock uses int instead of the usual socklen_t */ -typedef int socklen_t; +/* Winsock uses int32_t instead of the usual socklen_t */ +typedef int32_t socklen_t; -int win32_poll(struct pollfd *, unsigned int, int); -SOCKET win32_socket(int, int, int); -int win32_connect(SOCKET, struct sockaddr*, socklen_t); +int32_t win32_poll(struct pollfd *, uint32_t, int); +SOCKET win32_socket(int32_t, int32_t, int); +int32_t win32_connect(SOCKET, struct sockaddr*, socklen_t); SOCKET win32_accept(SOCKET, struct sockaddr*, socklen_t *); -int win32_shutdown(SOCKET, int); -int win32_close_socket(SOCKET fd); +int32_t win32_shutdown(SOCKET, int); +int32_t win32_close_socket(SOCKET fd); #define strtok_r(x, y, z) win32_strtok_r(x, y, z) #define strsep(x,y) win32_strsep(x,y) @@ -70,7 +72,7 @@ int win32_close_socket(SOCKET fd); char *win32_strtok_r(char *s, const char *delim, char **lasts); char *win32_strsep(char **stringp, const char *delim); -ssize_t win32_read_socket(SOCKET fd, void *buf, int n); -ssize_t win32_write_socket(SOCKET fd, void *buf, int n); +ssize_t win32_read_socket(SOCKET fd, void *buf, int32_t n); +ssize_t win32_write_socket(SOCKET fd, void *buf, int32_t n); #endif // defined(_WIN32) diff --git a/tests/flash.c b/tests/flash.c index 1140566af..f66428dcd 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -1,3 +1,4 @@ +#include #include #include #include @@ -11,7 +12,7 @@ struct Test { const char * cmd_line; - int res; + int32_t res; struct flash_opts opts; }; @@ -32,7 +33,7 @@ static bool cmp_mem(const uint8_t * s1, const uint8_t * s2, size_t size) { } static bool execute_test(const struct Test * test) { - int ac = 0; + int32_t ac = 0; char* av[32]; /* parse (tokenize) the test command line */ @@ -53,7 +54,7 @@ static bool execute_test(const struct Test * test) { /* Call */ struct flash_opts opts; - int res = flash_get_opts(&opts, ac, av); + int32_t res = flash_get_opts(&opts, ac, av); /* Compare results */ bool ret = (res == test->res); @@ -225,7 +226,7 @@ static struct Test tests[] = { }, }; -int main() { +int32_t main() { bool allOk = true; for (size_t i = 0; i < sizeof(tests) / sizeof(tests[0]); ++i) diff --git a/tests/sg.c b/tests/sg.c index d88fbe760..cd601b6d6 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -1,3 +1,4 @@ +#include #include #include #include @@ -24,7 +25,7 @@ static void __attribute__((unused)) mark_buf(stlink_t *sl) { } -int main(void) { // main() ripped out of old stlink-hw.c +int32_t main(void) { // main() ripped out of old stlink-hw.c /* Avoid unused parameter warning */ // set scpi lib debug level: 0 for no debug info, 10 for lots fputs( @@ -81,7 +82,7 @@ int main(void) { // main() ripped out of old stlink-hw.c memset(sl->q_buf, 0, sizeof(sl->q_buf)); - for (int i = 0; i < 100; i++) { + for (int32_t i = 0; i < 100; i++) { write_uint32(sl->q_buf, LED_BLUE | LED_GREEN); stlink_write_mem32(sl, GPIOC_ODR, 4); // stlink_read_mem32(sl, 0x4001100c, 4); @@ -184,7 +185,7 @@ int main(void) { // main() ripped out of old stlink-hw.c #if 0 /* check file contents */ fputs("\n+++++++ check flash memory\n\n", stderr); { - const int res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000); + const int32_t res = stlink_fcheck_flash(sl, "/tmp/foobar", 0x08000000); printf("_____ stlink_fcheck_flash() == %d\n", res); } #endif diff --git a/tests/usb.c b/tests/usb.c index 742f5c578..2d928e5f0 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -1,17 +1,18 @@ +#include #include +#include #include -#include static void usage(void) { puts("test-usb --reset"); puts("test-usb --no-reset"); } -int main(int ac, char** av) { +int32_t main(int32_t ac, char** av) { stlink_t* sl; struct stlink_reg regs; - int reset = 0; + int32_t reset = 0; if (ac == 2) { if (strcmp(av[1], "--reset") == 0) From 92ad99fe35d03adbe411eba5afabbb30c0c734b4 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 7 Jun 2023 22:01:56 +0200 Subject: [PATCH 1377/1435] Minor fixes & additions - G49x_G4Ax & WLEx: Added dualbank support - G49x_G4Ax: Added option byte support - Minor formatting improvements - Replaced leftovers for non-fixed length types --- config/chips/G49x_G4Ax.chip | 2 +- config/chips/{WLx5.chip => WLEx.chip} | 2 +- src/stlink-lib/common.c | 11 +- src/stlink-lib/common_flash.c | 3 +- src/stlink-lib/flash_loader.c | 141 +++++++++++++------------- src/stlink-lib/flash_loader.h | 12 ++- src/stlink-lib/option_bytes.c | 1 + src/win32/win32_socket.h | 6 +- 8 files changed, 92 insertions(+), 86 deletions(-) rename config/chips/{WLx5.chip => WLEx.chip} (95%) diff --git a/config/chips/G49x_G4Ax.chip b/config/chips/G49x_G4Ax.chip index 3e8aacf4b..079dc01ae 100644 --- a/config/chips/G49x_G4Ax.chip +++ b/config/chips/G49x_G4Ax.chip @@ -11,4 +11,4 @@ bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1ffff800 // STM32_G4_OPTION_BYTES_BASE option_size 0x4 // 4 B -flags swo +flags swo dualbank diff --git a/config/chips/WLx5.chip b/config/chips/WLEx.chip similarity index 95% rename from config/chips/WLx5.chip rename to config/chips/WLEx.chip index 8337b0aee..265514211 100644 --- a/config/chips/WLx5.chip +++ b/config/chips/WLEx.chip @@ -11,4 +11,4 @@ bootrom_base 0x1fff0000 bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 option_size 0x10 // 16 B -flags swo +flags swo dualbank diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index cb87f5f36..43d2b9a9e 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -41,8 +41,8 @@ struct stlink_fread_ihex_worker_arg { typedef bool (*save_block_fn)(void *arg, uint8_t *block, ssize_t len); static void stop_wdg_in_debug(stlink_t *); -int32_t stlink_jtag_reset(stlink_t *, int); -int32_t stlink_soft_reset(stlink_t *, int); +int32_t stlink_jtag_reset(stlink_t *, int32_t); +int32_t stlink_soft_reset(stlink_t *, int32_t); void _parse_version(stlink_t *, stlink_version_t *); static uint8_t stlink_parse_hex(const char *); static int32_t stlink_read(stlink_t *, stm32_addr_t, size_t, save_block_fn, void *); @@ -253,8 +253,8 @@ int32_t stlink_load_device_params(stlink_t *sl) { flash_size = flash_size & 0xffff; if ((sl->chip_id == STM32_CHIPID_L1_MD || - sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || - sl->chip_id == STM32_CHIPID_L1_MD_PLUS) && + sl->chip_id == STM32_CHIPID_F1_VL_MD_LD || + sl->chip_id == STM32_CHIPID_L1_MD_PLUS) && (flash_size == 0)) { sl->flash_size = 128 * 1024; } else if (sl->chip_id == STM32_CHIPID_L1_CAT2) { @@ -285,7 +285,8 @@ int32_t stlink_load_device_params(stlink_t *sl) { sl->sram_size = 0x1000; } - if (sl->chip_id == STM32_CHIPID_G4_CAT3) { + if (sl->chip_id == STM32_CHIPID_G4_CAT3 || + sl->chip_id == STM32_CHIPID_G4_CAT4) { uint32_t flash_optr; stlink_read_debug32(sl, FLASH_Gx_OPTR, &flash_optr); diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index e2a394946..31ea02c07 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1348,8 +1348,7 @@ int32_t stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { * @param length how much * @return 0 for success, -ve for failure */ -int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, - uint32_t length) { +int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length) { size_t off; size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; ILOG("Starting verification of write complete\n"); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 99a8260f7..23b2713a8 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -24,7 +24,7 @@ * flash loaders must be aligned by 4 (it's written by stlink_write_mem32) */ -/* flashloaders/stm32f0.s -- compiled with thumb2 */ +// flashloaders/stm32f0.s -- compiled with thumb2 static const uint8_t loader_code_stm32vl[] = { 0x00, 0xbf, 0x00, 0xbf, 0x09, 0x4f, 0x1f, 0x44, @@ -41,7 +41,7 @@ static const uint8_t loader_code_stm32vl[] = { 0x0c, 0x00, 0x00, 0x00 }; -/* flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored */ +// flashloaders/stm32f0.s -- thumb1 only, same sequence as for STM32VL, bank ignored static const uint8_t loader_code_stm32f0[] = { 0xc0, 0x46, 0xc0, 0x46, 0x08, 0x4f, 0x1f, 0x44, @@ -59,8 +59,8 @@ static const uint8_t loader_code_stm32f0[] = { 0x14, 0x00, 0x00, 0x00 }; +// flashloaders/stm32lx.s static const uint8_t loader_code_stm32lx[] = { - // flashloaders/stm32lx.s 0x04, 0x68, 0x0c, 0x60, 0x00, 0xf1, 0x04, 0x00, 0x01, 0xf1, 0x04, 0x01, @@ -68,8 +68,8 @@ static const uint8_t loader_code_stm32lx[] = { 0x00, 0xbe, 0x00, 0x00 }; +// flashloaders/stm32f4.s static const uint8_t loader_code_stm32f4[] = { - // flashloaders/stm32f4.s 0xdf, 0xf8, 0x24, 0xc0, 0xdf, 0xf8, 0x24, 0xa0, 0xe2, 0x44, 0x04, 0x68, @@ -84,8 +84,8 @@ static const uint8_t loader_code_stm32f4[] = { 0x0e, 0x00, 0x00, 0x00 }; +// flashloaders/stm32f4lv.s static const uint8_t loader_code_stm32f4_lv[] = { - // flashloaders/stm32f4lv.s 0xdf, 0xf8, 0x24, 0xc0, 0xdf, 0xf8, 0x24, 0xa0, 0xe2, 0x44, 0x04, 0x78, @@ -100,8 +100,8 @@ static const uint8_t loader_code_stm32f4_lv[] = { 0x0e, 0x00, 0x00, 0x00 }; +// flashloaders/stm32l4.s static const uint8_t loader_code_stm32l4[] = { - // flashloaders/stm32l4.s 0xdf, 0xf8, 0x28, 0xc0, 0xdf, 0xf8, 0x28, 0xa0, 0xe2, 0x44, 0x05, 0x68, @@ -117,8 +117,8 @@ static const uint8_t loader_code_stm32l4[] = { 0x10, 0x00, 0x00, 0x00 }; +// flashloaders/stm32f7.s static const uint8_t loader_code_stm32f7[] = { - // flashloaders/stm32f7.s 0xdf, 0xf8, 0x28, 0xc0, 0xdf, 0xf8, 0x28, 0xa0, 0xe2, 0x44, 0x04, 0x68, @@ -134,8 +134,8 @@ static const uint8_t loader_code_stm32f7[] = { 0x0e, 0x00, 0x00, 0x00 }; +// flashloaders/stm32f7lv.s static const uint8_t loader_code_stm32f7_lv[] = { - // flashloaders/stm32f7lv.s 0xdf, 0xf8, 0x28, 0xc0, 0xdf, 0xf8, 0x28, 0xa0, 0xe2, 0x44, 0x04, 0x78, @@ -201,9 +201,9 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { } static int32_t loader_v_dependent_assignment(stlink_t *sl, - const uint8_t **loader_code, size_t *loader_size, - const uint8_t *high_v_loader, size_t high_v_loader_size, - const uint8_t *low_v_loader, size_t low_v_loader_size) { + const uint8_t **loader_code, size_t *loader_size, + const uint8_t *high_v_loader, size_t high_v_loader_size, + const uint8_t *low_v_loader, size_t low_v_loader_size) { int32_t retval = 0; if ( sl->version.stlink_v == 1) { @@ -338,21 +338,21 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t flash_base = FLASH_REGS_BANK2_OFS; } - /* Setup core */ - stlink_write_reg(sl, fl->buf_addr, 0); // source - stlink_write_reg(sl, target, 1); // target - stlink_write_reg(sl, (uint32_t)size, 2); // count - stlink_write_reg(sl, flash_base, 3); // flash register base - // only used on VL/F1_XL, but harmless for others - stlink_write_reg(sl, fl->loader_addr, 15); // pc register + /* Setup core */ + stlink_write_reg(sl, fl->buf_addr, 0); // source + stlink_write_reg(sl, target, 1); // target + stlink_write_reg(sl, (uint32_t)size, 2); // count + stlink_write_reg(sl, flash_base, 3); // flash register base + // only used on VL/F1_XL, but harmless for others + stlink_write_reg(sl, fl->loader_addr, 15); // pc register - /* Reset IWDG */ - if (fl->iwdg_kr) { - stlink_write_debug32(sl, fl->iwdg_kr, STM32F0_WDG_KR_KEY_RELOAD); - } + /* Reset IWDG */ + if (fl->iwdg_kr) { + stlink_write_debug32(sl, fl->iwdg_kr, STM32F0_WDG_KR_KEY_RELOAD); + } - /* Run loader */ - stlink_run(sl, RUN_FLASH_LOADER); + /* Run loader */ + stlink_run(sl, RUN_FLASH_LOADER); /* * This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. @@ -365,67 +365,63 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t * as what was intended. -- REW. */ - // wait until done (reaches breakpoint) - timeout = time_ms() + 500; - while (time_ms() < timeout) { - usleep(10000); - - if (stlink_is_core_halted(sl)) { - timeout = 0; - break; - } - } + // wait until done (reaches breakpoint) + timeout = time_ms() + 500; + while (time_ms() < timeout) { + usleep(10000); - if (timeout) { - ELOG("Flash loader run error\n"); - goto error; - } + if (stlink_is_core_halted(sl)) { + timeout = 0; + break; + } + } - // check written byte count - stlink_read_reg(sl, 2, &rr); + if (timeout) { + ELOG("Flash loader run error\n"); + goto error; + } - /* - * The chunk size for loading is not rounded. The flash loader - * subtracts the size of the written block (1-8 bytes) from - * the remaining size each time. A negative value may mean that - * several bytes garbage have been written due to the unaligned - * firmware size. - */ - if ((int32_t)rr.r[2] > 0 || (int32_t)rr.r[2] < -7) { - ELOG("Flash loader write error\n"); - goto error; - } + // check written byte count + stlink_read_reg(sl, 2, &rr); + + /* + * The chunk size for loading is not rounded. The flash loader + * subtracts the size of the written block (1-8 bytes) from + * the remaining size each time. A negative value may mean that + * several bytes garbage have been written due to the unaligned + * firmware size. + */ + if ((int32_t)rr.r[2] > 0 || (int32_t)rr.r[2] < -7) { + ELOG("Flash loader write error\n"); + goto error; + } - return(0); + return(0); -error: - dhcsr = dfsr = cfsr = hfsr = 0; - stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); - stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); - stlink_read_debug32(sl, STLINK_REG_CFSR, &cfsr); - stlink_read_debug32(sl, STLINK_REG_HFSR, &hfsr); - stlink_read_all_regs(sl, &rr); + error: + dhcsr = dfsr = cfsr = hfsr = 0; + stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); + stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); + stlink_read_debug32(sl, STLINK_REG_CFSR, &cfsr); + stlink_read_debug32(sl, STLINK_REG_HFSR, &hfsr); + stlink_read_all_regs(sl, &rr); - WLOG("Loader state: R2 0x%X R15 0x%X\n", rr.r[2], rr.r[15]); - if (dhcsr != 0x3000B || dfsr || cfsr || hfsr) { - WLOG("MCU state: DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X\n", - dhcsr, dfsr, cfsr, hfsr); - } + WLOG("Loader state: R2 0x%X R15 0x%X\n", rr.r[2], rr.r[15]); + if (dhcsr != 0x3000B || dfsr || cfsr || hfsr) { + WLOG("MCU state: DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X\n", + dhcsr, dfsr, cfsr, hfsr); + } - return(-1); + return(-1); } -/* ================================================== - * === Content from old source file flashloader.c === - * ================================================== - */ +/* === Content from old source file flashloader.c === */ #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 -int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len, uint32_t pagesize) { +int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize) { uint32_t count, off; uint32_t num_half_pages = len / pagesize; uint32_t val; @@ -722,8 +718,7 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { return (0); } -int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, - stm32_addr_t addr, uint8_t *base, uint32_t len) { +int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { size_t off; if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 5b7b0945d..46cacba30 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -14,11 +14,21 @@ #include int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); +static int32_t loader_v_dependent_assignment(stlink_t *sl, + const uint8_t **loader_code, size_t *loader_size, + const uint8_t *high_v_loader, size_t high_v_loader_size, + const uint8_t *low_v_loader, size_t low_v_loader_size); int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); + +/* === Functions from old header file flashloader.h === */ + +int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize); +static void set_flash_cr_pg(stlink_t *sl, uint32_t bank); +static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr); int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); -int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t* base, uint32_t len); +int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len); int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); #endif // FLASH_LOADER_H diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index e2d966b7a..3300ee15e 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -1012,6 +1012,7 @@ int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { case STM32_CHIPID_G0_CAT2: case STM32_CHIPID_G4_CAT2: case STM32_CHIPID_G4_CAT3: + case STM32_CHIPID_G4_CAT4: return stlink_read_option_bytes_gx(sl, option_byte); default: return stlink_read_option_bytes_generic(sl, option_byte); diff --git a/src/win32/win32_socket.h b/src/win32/win32_socket.h index e7ea398e9..fb622f546 100644 --- a/src/win32/win32_socket.h +++ b/src/win32/win32_socket.h @@ -59,11 +59,11 @@ struct pollfd { /* Winsock uses int32_t instead of the usual socklen_t */ typedef int32_t socklen_t; -int32_t win32_poll(struct pollfd *, uint32_t, int); -SOCKET win32_socket(int32_t, int32_t, int); +int32_t win32_poll(struct pollfd *, uint32_t, int32_t); +SOCKET win32_socket(int32_t, int32_t, int32_t); int32_t win32_connect(SOCKET, struct sockaddr*, socklen_t); SOCKET win32_accept(SOCKET, struct sockaddr*, socklen_t *); -int32_t win32_shutdown(SOCKET, int); +int32_t win32_shutdown(SOCKET, int32_t); int32_t win32_close_socket(SOCKET fd); #define strtok_r(x, y, z) win32_strtok_r(x, y, z) From c8eaebc58eb7b027ab53c16ef4e8ad6fd72a10d7 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 7 Jun 2023 22:44:59 +0200 Subject: [PATCH 1378/1435] Improvents for library documentation - Renamed header file reg.h to register.h - Added unified header comments for files - [doc] flash_loader.h: // Static functions --- CMakeLists.txt | 2 +- inc/stlink.h | 6 ++---- src/st-trace/trace.c | 2 +- src/stlink-lib/calculate.c | 6 ++++++ src/stlink-lib/chipid.c | 6 ++++++ src/stlink-lib/chipid.h | 6 ++++++ src/stlink-lib/commands.h | 6 ++++++ src/stlink-lib/common_flash.c | 6 ++++++ src/stlink-lib/flash_loader.c | 6 ++++++ src/stlink-lib/flash_loader.h | 14 +++++++------- src/stlink-lib/helper.c | 6 ++++++ src/stlink-lib/helper.h | 6 ++++++ src/stlink-lib/libusb_settings.h | 6 ++++++ src/stlink-lib/logging.c | 3 +-- src/stlink-lib/map_file.c | 6 ++++++ src/stlink-lib/md5.c | 6 ++++++ src/stlink-lib/option_bytes.c | 6 ++++++ src/stlink-lib/{reg.h => register.h} | 10 ++++++++-- src/stlink-lib/sg.c | 6 ++++++ src/stlink-lib/sg.h | 5 +++-- src/stlink-lib/usb.c | 6 ++++++ src/stlink-lib/usb.h | 5 +++-- 22 files changed, 110 insertions(+), 21 deletions(-) rename src/stlink-lib/{reg.h => register.h} (98%) diff --git a/CMakeLists.txt b/CMakeLists.txt index bce4def8f..4ff18b815 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -180,7 +180,7 @@ set(STLINK_HEADERS src/stlink-lib/map_file.h src/stlink-lib/md5.h src/stlink-lib/option_bytes.h - src/stlink-lib/reg.h + src/stlink-lib/register.h src/stlink-lib/sg.h src/stlink-lib/usb.h ) diff --git a/inc/stlink.h b/inc/stlink.h index ca07a6a89..2ed34a074 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -1,9 +1,7 @@ - /* * File: stlink.h * - * This should contain all the common top level stlink interfaces, - * regardless of how the backend does the work.... + * All common top level stlink interfaces, regardless of how the backend does the work.... */ #ifndef STLINK_H @@ -300,7 +298,7 @@ int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect); #include #include -#include +#include #include #include #include diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 8b148f463..ccbd74e16 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -11,7 +11,7 @@ #include #include -#include +#include #include #define DEFAULT_LOGGING_LEVEL 50 diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index 132875a66..2a708b551 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -1,3 +1,9 @@ +/* + * File: calculate.c + * + * Calculation of sector numbers and pages + */ + #include #include diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 7e99a8730..65ca2842a 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -1,3 +1,9 @@ +/* + * File: chipid.c + * + * Chip-ID parametres + */ + #include #include #include diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 9eaac722d..9955811fa 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -1,3 +1,9 @@ +/* + * File: chipid.h + * + * Chip-ID parametres + */ + #ifndef CHIPID_H #define CHIPID_H diff --git a/src/stlink-lib/commands.h b/src/stlink-lib/commands.h index 5f0904971..64cecce16 100644 --- a/src/stlink-lib/commands.h +++ b/src/stlink-lib/commands.h @@ -1,3 +1,9 @@ +/* + * File: commands.h + * + * stlink commands + */ + #ifndef COMMANDS_H #define COMMANDS_H diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 31ea02c07..d2063851f 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1,3 +1,9 @@ +/* + * File: common_flash.c + * + * Flash operations + */ + #include #include #include diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 23b2713a8..0f171d223 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -1,3 +1,9 @@ +/* + * File: flash_loader.c + * + * Flash loaders + */ + #include #include #include diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 46cacba30..8888875a7 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -1,7 +1,7 @@ /* * File: flash_loader.h * - * Flash loader + * Flash loaders */ #ifndef FLASH_LOADER_H @@ -14,10 +14,10 @@ #include int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); -static int32_t loader_v_dependent_assignment(stlink_t *sl, - const uint8_t **loader_code, size_t *loader_size, - const uint8_t *high_v_loader, size_t high_v_loader_size, - const uint8_t *low_v_loader, size_t low_v_loader_size); +// static int32_t loader_v_dependent_assignment(stlink_t *sl, +// const uint8_t **loader_code, size_t *loader_size, +// const uint8_t *high_v_loader, size_t high_v_loader_size, +// const uint8_t *low_v_loader, size_t low_v_loader_size); int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); @@ -25,8 +25,8 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t /* === Functions from old header file flashloader.h === */ int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize); -static void set_flash_cr_pg(stlink_t *sl, uint32_t bank); -static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr); +// static void set_flash_cr_pg(stlink_t *sl, uint32_t bank); +// static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr); int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len); int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl); diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index a6155925f..d7420691a 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -1,3 +1,9 @@ +/* + * File: helper.c + * + * General helper functions + */ + #include #include #include diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index dbd760a52..43a96368d 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -1,3 +1,9 @@ +/* + * File: helper.h + * + * General helper functions + */ + #ifndef HELPER_H #define HELPER_H diff --git a/src/stlink-lib/libusb_settings.h b/src/stlink-lib/libusb_settings.h index 3777f720b..b0a51ad31 100644 --- a/src/stlink-lib/libusb_settings.h +++ b/src/stlink-lib/libusb_settings.h @@ -1,3 +1,9 @@ +/* + * File: libusb_settings.h + * + * Settings for libusb library + */ + #ifndef LIBUSB_SETTINGS_H #define LIBUSB_SETTINGS_H diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index a64ec4ef2..1463eb925 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -1,8 +1,7 @@ /* * UglyLogging * - * Slow, yet another wheel reinvented, but enough to make the rest of our code - * pretty enough. + * Slow, yet another wheel reinvented, but enough to make the rest of our code pretty enough. */ #include diff --git a/src/stlink-lib/map_file.c b/src/stlink-lib/map_file.c index bb83ff7be..cfd2d1876 100644 --- a/src/stlink-lib/map_file.c +++ b/src/stlink-lib/map_file.c @@ -1,3 +1,9 @@ +/* + * File: map_file.c + * + * File mapping + */ + #include #include #include diff --git a/src/stlink-lib/md5.c b/src/stlink-lib/md5.c index 19ec86b91..f7af43ac3 100644 --- a/src/stlink-lib/md5.c +++ b/src/stlink-lib/md5.c @@ -5,6 +5,12 @@ * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org */ +/* + * File: md5.c + * + * MD5 hash function + */ + #include #include diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 3300ee15e..6a12333cd 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -1,3 +1,9 @@ +/* + * File: option_bytes.c + * + * Read and write option bytes and option control registers + */ + #include #include #include diff --git a/src/stlink-lib/reg.h b/src/stlink-lib/register.h similarity index 98% rename from src/stlink-lib/reg.h rename to src/stlink-lib/register.h index c2976d050..7b63154c8 100644 --- a/src/stlink-lib/reg.h +++ b/src/stlink-lib/register.h @@ -1,5 +1,11 @@ -#ifndef REG_H -#define REG_H +/* + * File: register.h + * + * Common STM32 registers + */ + +#ifndef REGISTER_H +#define REGISTER_H #define STLINK_REG_CM3_CPUID 0xE000ED00 diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index c0f79c7cf..7c16a5336 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -74,6 +74,12 @@ * part to an existing options line for usb-storage). */ +/* + * File: sg.c + * + * + */ + #define __USE_GNU #include diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index d4792c49a..ce69f7a09 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -1,6 +1,7 @@ /* - * File: sg.h - * Author: karl + * File: sg.h + * + * */ #ifndef SG_H diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index d404c2e94..e9f45574f 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1,3 +1,9 @@ +/* + * File: usb.c + * + * + */ + #include #include #include diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index b5c1835ec..55d506c5b 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -1,6 +1,7 @@ /* - * File: usb.h - * Author: karl + * File: usb.h + * + * */ #ifndef USB_H From dbe13dedae12059fe5ee7b80848d564f82151f0e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 7 Jun 2023 23:12:00 +0200 Subject: [PATCH 1379/1435] [doc] Added header comments for lib modules - common.c/.h - sg.c/.h - usb.c/.h --- src/stlink-lib/common.c | 9 +++++++++ src/stlink-lib/common.h | 5 ++++- src/stlink-lib/sg.c | 2 ++ src/stlink-lib/sg.h | 2 ++ src/stlink-lib/usb.c | 2 +- src/stlink-lib/usb.h | 2 +- 6 files changed, 19 insertions(+), 3 deletions(-) diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 43d2b9a9e..479aa4943 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -1,3 +1,12 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ +/* TODO: This file should be split up into new or existing modules. */ + +/* + * File: common.c + * + * + */ + #include #include #include diff --git a/src/stlink-lib/common.h b/src/stlink-lib/common.h index c60b49199..1f7e0804d 100644 --- a/src/stlink-lib/common.h +++ b/src/stlink-lib/common.h @@ -1,7 +1,10 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ +/* TODO: This file should be split up into new or existing modules. */ + /* * File: common.h * - * General helper functions + * */ #ifndef COMMON_H diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 7c16a5336..4db8c6164 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + /* * Copyright (c) 2010 "Capt'ns Missing Link" Authors. All rights reserved. * Use of this source code is governed by a BSD-style diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index ce69f7a09..1ab433142 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS HEADER FILE IS TO BE VERIFIED (07.06.2023) == */ + /* * File: sg.h * diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index e9f45574f..9dc4a0ebd 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -1,7 +1,7 @@ /* * File: usb.c * - * + * USB commands & interaction with ST-LINK devices */ #include diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 55d506c5b..83c0c2481 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -1,7 +1,7 @@ /* * File: usb.h * - * + * USB commands & interaction with ST-LINK devices */ #ifndef USB_H From 67ae7a12d8636795f08f1004bf5cd26f596e1eee Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 9 Jun 2023 01:16:18 +0200 Subject: [PATCH 1380/1435] Added comments for testing modules --- README.md | 2 +- tests/flash.c | 2 ++ tests/sg.c | 2 ++ tests/usb.c | 2 ++ 4 files changed, 7 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index e103ac301..6d188f0df 100644 --- a/README.md +++ b/README.md @@ -78,7 +78,7 @@ We recommend to install `stlink-tools` from the package repository of the used d - Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) - Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) - FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) -- MacOS: **Support for macOS will end with v1.7.1.** Please use v1.7.0 (current ***master*** branch) and the related documentation instead. +- MacOS: **Support for macOS will end with v1.8.0.** Please use v1.7.0 (current ***master*** branch) and the related documentation instead. ## Installation from source (advanced users) diff --git a/tests/flash.c b/tests/flash.c index f66428dcd..a40be0c74 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + #include #include #include diff --git a/tests/sg.c b/tests/sg.c index cd601b6d6..32dcd9a62 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + #include #include #include diff --git a/tests/usb.c b/tests/usb.c index 2d928e5f0..56f0d9c1f 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + #include #include #include From be2e7e3883646eadbda4e2a56bdb21f84c06444d Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 9 Jun 2023 01:28:22 +0200 Subject: [PATCH 1381/1435] [refactoring] Clean-up for stlink-lib - Ensure proper function declaration - Moved some functions to related modules - Checked & revised header includes - Renamed "md5" to "lib_md5" - New source file "md5" --- CMakeLists.txt | 3 +- inc/stlink.h | 18 +-- src/st-util/gdb-server.c | 3 +- src/stlink-gui/gui.c | 1 + src/stlink-lib/calculate.c | 1 + src/stlink-lib/chipid.c | 13 +- src/stlink-lib/chipid.h | 3 - src/stlink-lib/common.c | 86 +--------- src/stlink-lib/common.h | 23 --- src/stlink-lib/common_flash.c | 32 ++-- src/stlink-lib/common_flash.h | 43 +++-- src/stlink-lib/flash_loader.c | 9 +- src/stlink-lib/flash_loader.h | 4 - src/stlink-lib/helper.c | 15 +- src/stlink-lib/helper.h | 2 + src/stlink-lib/lib_md5.c | 280 ++++++++++++++++++++++++++++++++ src/stlink-lib/lib_md5.h | 68 ++++++++ src/stlink-lib/logging.c | 12 +- src/stlink-lib/logging.h | 3 + src/stlink-lib/map_file.c | 46 +++++- src/stlink-lib/map_file.h | 1 + src/stlink-lib/md5.c | 293 +++------------------------------- src/stlink-lib/md5.h | 63 +------- src/stlink-lib/option_bytes.c | 8 +- src/stlink-lib/option_bytes.h | 3 - src/stlink-lib/read_write.c | 2 + src/stlink-lib/sg.c | 14 +- src/stlink-lib/sg.h | 3 +- src/stlink-lib/usb.c | 25 +-- src/stlink-lib/usb.h | 2 - 30 files changed, 554 insertions(+), 525 deletions(-) delete mode 100644 src/stlink-lib/common.h create mode 100644 src/stlink-lib/lib_md5.c create mode 100644 src/stlink-lib/lib_md5.h diff --git a/CMakeLists.txt b/CMakeLists.txt index 4ff18b815..2a82ea983 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -172,10 +172,10 @@ set(STLINK_HEADERS src/stlink-lib/chipid.h src/stlink-lib/commands.h src/stlink-lib/common_flash.h - src/stlink-lib/common.h src/stlink-lib/flash_loader.h src/stlink-lib/helper.h src/stlink-lib/libusb_settings.h + src/stlink-lib/lib_md5.h src/stlink-lib/logging.h src/stlink-lib/map_file.h src/stlink-lib/md5.h @@ -194,6 +194,7 @@ set(STLINK_SOURCE src/stlink-lib/helper.c src/stlink-lib/logging.c src/stlink-lib/map_file.c + src/stlink-lib/lib_md5.c src/stlink-lib/md5.c src/stlink-lib/option_bytes.c src/stlink-lib/read_write.c diff --git a/inc/stlink.h b/inc/stlink.h index 2ed34a074..b2516c90c 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -11,8 +11,8 @@ #include #include -#include "stm32.h" -#include "stm32flash.h" +#include +#include #ifdef __cplusplus extern "C" { @@ -263,24 +263,13 @@ int32_t stlink_set_swdclk(stlink_t *sl, int32_t freq_khz); int32_t stlink_trace_enable(stlink_t* sl, uint32_t frequency); int32_t stlink_trace_disable(stlink_t* sl); int32_t stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); -int32_t stlink_erase_flash_mass(stlink_t* sl); -int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size); -int32_t stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length, uint8_t eraseonly); int32_t stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); uint8_t stlink_get_erased_pattern(stlink_t *sl); -int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); -int32_t stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr); int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); int32_t stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); -int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); - //int32_t stlink_chip_id(stlink_t *sl, uint32_t *chip_id); int32_t stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid); - -int32_t stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr); uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr); -int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); -int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); uint16_t read_uint16(const unsigned char *c, const int32_t pt); //void stlink_core_stat(stlink_t *sl); void stlink_print_data(stlink_t *sl); @@ -293,7 +282,6 @@ int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* bu int32_t write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int32_t stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); int32_t stlink_load_device_params(stlink_t *sl); - int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect); #include @@ -301,8 +289,8 @@ int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect); #include #include #include -#include #include +#include #include #ifdef __cplusplus diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 557a24f5f..431e37eec 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -29,7 +29,8 @@ #include #include #include -#include "flash_loader.h" +#include +#include #include "gdb-remote.h" #include "gdb-server.h" #include "semihosting.h" diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index f0426f577..f1e9382d0 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -5,6 +5,7 @@ #include #include +#include #include "gui.h" #define MEM_READ_SIZE 1024 diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index 2a708b551..b13a1c961 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -8,6 +8,7 @@ #include #include "calculate.h" + #include "common_flash.h" uint32_t calculate_F4_sectornum(uint32_t flashaddr) { diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 65ca2842a..c622abcbb 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -4,16 +4,19 @@ * Chip-ID parametres */ -#include -#include -#include #include +#include #include #include -#include "chipid.h" -#include #include +#include +#include "chipid.h" + +#include "logging.h" + +// #include // TODO: Check use +// #include // TODO: Check use static struct stlink_chipid_params *devicelist; diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 9955811fa..d7319f569 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -9,9 +9,6 @@ #include -#include -#include - /* Chipid parametres */ struct stlink_chipid_params { char *dev_type; diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 479aa4943..d6477281d 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -13,18 +13,20 @@ #include #include #include -#include -#include -#include +// #include // TODO: Check use +// #include // TODO: Check use #include -#include + #include "calculate.h" +#include "chipid.h" #include "common_flash.h" +#include "helper.h" +#include "logging.h" #include "map_file.h" #include "md5.h" - -#include "common.h" +#include "register.h" +#include "usb.h" #ifndef O_BINARY #define O_BINARY 0 @@ -1213,78 +1215,6 @@ void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { } } -/* Limit the block size to compare to 0x1800 as anything larger will stall the - * STLINK2 Maybe STLINK V1 needs smaller value! - */ -int32_t check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { - size_t off; - size_t n_cmp = sl->flash_pgsz; - - if (n_cmp > 0x1800) { - n_cmp = 0x1800; - } - - for (off = 0; off < mf->len; off += n_cmp) { - size_t aligned_size; - - size_t cmp_size = n_cmp; // adjust last page size - - if ((off + n_cmp) > mf->len) { - cmp_size = mf->len - off; - } - - aligned_size = cmp_size; - - if (aligned_size & (4 - 1)) { - aligned_size = (cmp_size + 4) & ~(4 - 1); - } - - stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); - - if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { - return (-1); - } - } - - return (0); -} - -void md5_calculate(mapped_file_t *mf) { - // calculate md5 checksum of given binary file - Md5Context md5Context; - MD5_HASH md5Hash; - Md5Initialise(&md5Context); - Md5Update(&md5Context, mf->base, (uint32_t)mf->len); - Md5Finalise(&md5Context, &md5Hash); - printf("md5 checksum: "); - - for (int32_t i = 0; i < (int32_t)sizeof(md5Hash); i++) { - printf("%x", md5Hash.bytes[i]); - } - - printf(", "); -} - -void stlink_checksum(mapped_file_t *mp) { - /* checksum that backward compatible with official ST tools */ - uint32_t sum = 0; - uint8_t *mp_byte = (uint8_t *)mp->base; - - for (size_t i = 0; i < mp->len; ++i) { - sum += mp_byte[i]; - } - - printf("stlink checksum: 0x%08x\n", sum); -} - -void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { - uint32_t val; - // set PC to the reset routine - stlink_read_debug32(sl, addr + 4, &val); - stlink_write_reg(sl, val, 15); - stlink_run(sl, RUN_NORMAL); -} - static int32_t stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, save_block_fn fn, void *fn_arg) { diff --git a/src/stlink-lib/common.h b/src/stlink-lib/common.h deleted file mode 100644 index 1f7e0804d..000000000 --- a/src/stlink-lib/common.h +++ /dev/null @@ -1,23 +0,0 @@ -/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ -/* TODO: This file should be split up into new or existing modules. */ - -/* - * File: common.h - * - * - */ - -#ifndef COMMON_H -#define COMMON_H - -#include - -#include "map_file.h" -#include "md5.h" - -int32_t check_file(stlink_t *, mapped_file_t *, stm32_addr_t); -void md5_calculate(mapped_file_t *); -void stlink_checksum(mapped_file_t *); -void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); - -#endif // COMMON_H diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index d2063851f..6ade87311 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -5,16 +5,19 @@ */ #include + #include -#include #include +#include #include +#include "common_flash.h" + #include "calculate.h" #include "flash_loader.h" -#include "common_flash.h" +#include "logging.h" #include "map_file.h" -#include "common.h" +#include "md5.h" #define DEBUG_FLASH 0 @@ -742,6 +745,7 @@ void clear_flash_cr_pg(stlink_t *sl, uint32_t bank) { n = read_flash_cr(sl, bank) & ~(1 << bit); stlink_write_debug32(sl, cr_reg, n); } + /* ------------------------------------------------------------------------ */ static void wait_flash_busy_progress(stlink_t *sl) { @@ -1170,7 +1174,7 @@ int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t return (-1); } - fprintf(stdout, "-> Flash page at %#x erased (size: %#x)\n", addr, page_size); + fprintf(stdout, "-> Flash page at %#x erased (size: %#x)\r", addr, page_size); fflush(stdout); // check the next page is within the range to erase @@ -1232,8 +1236,7 @@ int32_t stlink_erase_flash_mass(stlink_t *sl) { return (err); } -int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, - stm32_addr_t addr) { +int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr) { /* Write the block in flash at addr */ int32_t err; uint32_t num_empty, idx; @@ -1416,12 +1419,10 @@ int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { return 0; } -int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, - uint32_t len, uint8_t eraseonly) { +int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint8_t eraseonly) { int32_t ret; flash_loader_t fl; - ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, - len, addr, addr); + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); // check addr range is inside the flash stlink_calculate_pagesize(sl, addr); @@ -1438,6 +1439,9 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, (uint32_t)(sl->flash_pgsz)); return (-1); } + if ((len % 16 <= 8) & (sl->flash_type == STM32_FLASH_TYPE_L5_U5)) { + len += 8; + } // make sure we've loaded the context with the chip details stlink_core_id(sl); @@ -1464,3 +1468,11 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, return (stlink_verify_write_flash(sl, addr, base, len)); } + +void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { + uint32_t val; + // set PC to the reset routine + stlink_read_debug32(sl, addr + 4, &val); + stlink_write_reg(sl, val, 15); + stlink_run(sl, RUN_NORMAL); +} diff --git a/src/stlink-lib/common_flash.h b/src/stlink-lib/common_flash.h index 04e9134b5..092bdcbf4 100644 --- a/src/stlink-lib/common_flash.h +++ b/src/stlink-lib/common_flash.h @@ -9,22 +9,45 @@ #include +#define BANK_1 0 +#define BANK_2 1 + +uint32_t get_stm32l0_flash_base(stlink_t *); +uint32_t read_flash_cr(stlink_t *, uint32_t); void lock_flash(stlink_t *); +// static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val); void clear_flash_error(stlink_t *); +uint32_t read_flash_sr(stlink_t *sl, uint32_t bank); +uint32_t is_flash_busy(stlink_t *sl); void wait_flash_busy(stlink_t *); int32_t check_flash_error(stlink_t *); +// static inline uint32_t is_flash_locked(stlink_t *sl); +// static void unlock_flash(stlink_t *sl); int32_t unlock_flash_if(stlink_t *); int32_t lock_flash_option(stlink_t *); +// static bool is_flash_option_locked(stlink_t *sl); +// static int32_t unlock_flash_option(stlink_t *sl); int32_t unlock_flash_option_if(stlink_t *); -void write_flash_cr_psiz(stlink_t *, uint32_t, unsigned); -void clear_flash_cr_pg(stlink_t *, unsigned); - -// TODO: move to private defines if possible - -#define BANK_1 0 -#define BANK_2 1 - -uint32_t read_flash_cr(stlink_t *, unsigned); -uint32_t get_stm32l0_flash_base(stlink_t *); +void write_flash_cr_psiz(stlink_t *, uint32_t, uint32_t); +void clear_flash_cr_pg(stlink_t *, uint32_t); +// static void wait_flash_busy_progress(stlink_t *sl); +// static inline void write_flash_ar(stlink_t *sl, uint32_t n, uint32_t bank); +// static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, uint32_t bank); +// static void set_flash_cr_per(stlink_t *sl, uint32_t bank); +// static void clear_flash_cr_per(stlink_t *sl, uint32_t bank); +// static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n); +// static void set_flash_cr_strt(stlink_t *sl, uint32_t bank); +// static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank); +int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr); +int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size); +int32_t stlink_erase_flash_mass(stlink_t *sl); +int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr); +int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr); +int32_t stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr); +int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); +int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); +int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); +int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint8_t eraseonly); +void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); #endif // COMMON_FLASH_H diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 0f171d223..3472e2a61 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -11,9 +11,12 @@ #include #include -#include #include "flash_loader.h" + #include "common_flash.h" +#include "helper.h" +#include "logging.h" +#include "register.h" #define FLASH_REGS_BANK2_OFS 0x40 #define FLASH_BANK2_START_ADDR 0x08080000 @@ -757,7 +760,9 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t fflush(stdout); } - write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + // write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); + data = 0; + memcpy(&data, base + off, (len - off) < 4 ? (len - off) : 4); stlink_write_debug32(sl, addr + (uint32_t)off, data); wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 8888875a7..61a2a0c19 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -8,10 +8,6 @@ #define FLASH_LOADER_H #include -#include -#include - -#include int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); // static int32_t loader_v_dependent_assignment(stlink_t *sl, diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index d7420691a..97d6eb316 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -1,21 +1,22 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + /* * File: helper.c * * General helper functions */ - -#include -#include -#include - -#include "helper.h" - #ifdef STLINK_HAVE_SYS_TIME_H #include #else #include #endif +#include +#include +#include + +#include "helper.h" + uint32_t time_ms() { struct timeval tv; gettimeofday(&tv, NULL); diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index 43a96368d..a42fd480e 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + /* * File: helper.h * diff --git a/src/stlink-lib/lib_md5.c b/src/stlink-lib/lib_md5.c new file mode 100644 index 000000000..42f337ac3 --- /dev/null +++ b/src/stlink-lib/lib_md5.c @@ -0,0 +1,280 @@ +/* + * WjCryptLib_Md5 (https://github.com/WaterJuice/WjCryptLib) + * Implementation of MD5 hash function. Originally written by Alexander Peslyak. + * Modified by WaterJuice retaining Public Domain license. + * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org + */ + +#include +#include + +#include "lib_md5.h" + +/* INTERNAL FUNCTIONS */ + +/* F, G, H, I + * + * The basic MD5 functions. + * F and G are optimised compared to their RFC 1321 definitions for architectures + * that lack an AND-NOT instruction, just like in Colin Plumb's implementation. + */ +#define F( x, y, z ) ((z) ^ ((x) & ((y) ^ (z)))) +#define G( x, y, z ) ((y) ^ ((z) & ((x) ^ (y)))) +#define H( x, y, z ) ((x) ^ (y) ^ (z)) +#define I( x, y, z ) ((y) ^ ((x) | ~(z))) + +/* STEP: The MD5 transformation for all four rounds. */ +#define STEP( f, a, b, c, d, x, t, s ) \ + (a) += f((b), (c), (d)) + (x) + (t); \ + (a) = (((a) << (s)) | (((a) & 0xffffffff) >> (32 - (s)))); \ + (a) += (b); + +/* TransformFunction + * This processes one or more 64-byte data blocks, but does NOT update the bit counters. + * There are no alignment requirements. + */ +static void* TransformFunction(Md5Context* ctx, void const* data, uintmax_t size) { + uint8_t* ptr; + uint32_t a; + uint32_t b; + uint32_t c; + uint32_t d; + uint32_t saved_a; + uint32_t saved_b; + uint32_t saved_c; + uint32_t saved_d; + + #define GET(n) (ctx->block[(n)]) + #define SET(n) (ctx->block[(n)] = ((uint32_t)ptr[(n) * 4 + 0] << 0) | \ + ((uint32_t)ptr[(n) * 4 + 1] << 8) | \ + ((uint32_t)ptr[(n) * 4 + 2] << 16) | \ + ((uint32_t)ptr[(n) * 4 + 3] << 24)) + + ptr = (uint8_t*)data; + + a = ctx->a; + b = ctx->b; + c = ctx->c; + d = ctx->d; + + do { + saved_a = a; + saved_b = b; + saved_c = c; + saved_d = d; + + // Round 1 + STEP( F, a, b, c, d, SET(0), 0xd76aa478, 7 ) + STEP( F, d, a, b, c, SET(1), 0xe8c7b756, 12 ) + STEP( F, c, d, a, b, SET(2), 0x242070db, 17 ) + STEP( F, b, c, d, a, SET(3), 0xc1bdceee, 22 ) + STEP( F, a, b, c, d, SET(4), 0xf57c0faf, 7 ) + STEP( F, d, a, b, c, SET(5), 0x4787c62a, 12 ) + STEP( F, c, d, a, b, SET(6), 0xa8304613, 17 ) + STEP( F, b, c, d, a, SET(7), 0xfd469501, 22 ) + STEP( F, a, b, c, d, SET(8 ), 0x698098d8, 7 ) + STEP( F, d, a, b, c, SET(9 ), 0x8b44f7af, 12 ) + STEP( F, c, d, a, b, SET(10 ), 0xffff5bb1, 17 ) + STEP( F, b, c, d, a, SET(11 ), 0x895cd7be, 22 ) + STEP( F, a, b, c, d, SET(12 ), 0x6b901122, 7 ) + STEP( F, d, a, b, c, SET(13 ), 0xfd987193, 12 ) + STEP( F, c, d, a, b, SET(14 ), 0xa679438e, 17 ) + STEP( F, b, c, d, a, SET(15 ), 0x49b40821, 22 ) + + // Round 2 + STEP( G, a, b, c, d, GET(1), 0xf61e2562, 5 ) + STEP( G, d, a, b, c, GET(6), 0xc040b340, 9 ) + STEP( G, c, d, a, b, GET(11), 0x265e5a51, 14 ) + STEP( G, b, c, d, a, GET(0), 0xe9b6c7aa, 20 ) + STEP( G, a, b, c, d, GET(5), 0xd62f105d, 5 ) + STEP( G, d, a, b, c, GET(10), 0x02441453, 9 ) + STEP( G, c, d, a, b, GET(15), 0xd8a1e681, 14 ) + STEP( G, b, c, d, a, GET(4), 0xe7d3fbc8, 20 ) + STEP( G, a, b, c, d, GET(9), 0x21e1cde6, 5 ) + STEP( G, d, a, b, c, GET(14), 0xc33707d6, 9 ) + STEP( G, c, d, a, b, GET(3), 0xf4d50d87, 14 ) + STEP( G, b, c, d, a, GET(8), 0x455a14ed, 20 ) + STEP( G, a, b, c, d, GET(13), 0xa9e3e905, 5 ) + STEP( G, d, a, b, c, GET(2), 0xfcefa3f8, 9 ) + STEP( G, c, d, a, b, GET(7), 0x676f02d9, 14 ) + STEP( G, b, c, d, a, GET(12), 0x8d2a4c8a, 20 ) + + // Round 3 + STEP( H, a, b, c, d, GET(5), 0xfffa3942, 4 ) + STEP( H, d, a, b, c, GET(8), 0x8771f681, 11 ) + STEP( H, c, d, a, b, GET(11), 0x6d9d6122, 16 ) + STEP( H, b, c, d, a, GET(14), 0xfde5380c, 23 ) + STEP( H, a, b, c, d, GET(1), 0xa4beea44, 4 ) + STEP( H, d, a, b, c, GET(4), 0x4bdecfa9, 11 ) + STEP( H, c, d, a, b, GET(7), 0xf6bb4b60, 16 ) + STEP( H, b, c, d, a, GET(10), 0xbebfbc70, 23 ) + STEP( H, a, b, c, d, GET(13), 0x289b7ec6, 4 ) + STEP( H, d, a, b, c, GET(0), 0xeaa127fa, 11 ) + STEP( H, c, d, a, b, GET(3), 0xd4ef3085, 16 ) + STEP( H, b, c, d, a, GET(6), 0x04881d05, 23 ) + STEP( H, a, b, c, d, GET(9), 0xd9d4d039, 4 ) + STEP( H, d, a, b, c, GET(12), 0xe6db99e5, 11 ) + STEP( H, c, d, a, b, GET(15), 0x1fa27cf8, 16 ) + STEP( H, b, c, d, a, GET(2), 0xc4ac5665, 23 ) + + // Round 4 + STEP( I, a, b, c, d, GET(0), 0xf4292244, 6 ) + STEP( I, d, a, b, c, GET(7), 0x432aff97, 10 ) + STEP( I, c, d, a, b, GET(14), 0xab9423a7, 15 ) + STEP( I, b, c, d, a, GET(5), 0xfc93a039, 21 ) + STEP( I, a, b, c, d, GET(12), 0x655b59c3, 6 ) + STEP( I, d, a, b, c, GET(3), 0x8f0ccc92, 10 ) + STEP( I, c, d, a, b, GET(10), 0xffeff47d, 15 ) + STEP( I, b, c, d, a, GET(1), 0x85845dd1, 21 ) + STEP( I, a, b, c, d, GET(8), 0x6fa87e4f, 6 ) + STEP( I, d, a, b, c, GET(15), 0xfe2ce6e0, 10 ) + STEP( I, c, d, a, b, GET(6), 0xa3014314, 15 ) + STEP( I, b, c, d, a, GET(13), 0x4e0811a1, 21 ) + STEP( I, a, b, c, d, GET(4), 0xf7537e82, 6 ) + STEP( I, d, a, b, c, GET(11), 0xbd3af235, 10 ) + STEP( I, c, d, a, b, GET(2), 0x2ad7d2bb, 15 ) + STEP( I, b, c, d, a, GET(9), 0xeb86d391, 21 ) + + a += saved_a; + b += saved_b; + c += saved_c; + d += saved_d; + + ptr += 64; + } while ( size -= 64 ); + + ctx->a = a; + ctx->b = b; + ctx->c = c; + ctx->d = d; + + #undef GET + #undef SET + + return(ptr); +} + +/* EXPORTED FUNCTIONS */ + +/* Md5Initialise + * Initialises an MD5 Context. + * Use this to initialise/reset a context. + */ +void Md5Initialise(Md5Context* Context /* [out] */) { + Context->a = 0x67452301; + Context->b = 0xefcdab89; + Context->c = 0x98badcfe; + Context->d = 0x10325476; + + Context->lo = 0; + Context->hi = 0; +} + +/* Md5Update + * Adds data to the MD5 context. + * This will process the data and update the internal state of the context. + * Keep on calling this function until all the data has been added. + * Then call Md5Finalise to calculate the hash. + */ +void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */) { + uint32_t saved_lo; + uint32_t used; + uint32_t free; + + saved_lo = Context->lo; + + if ((Context->lo = (saved_lo + BufferSize) & 0x1fffffff) < saved_lo) { + Context->hi++; + } + + Context->hi += (uint32_t)(BufferSize >> 29); + + used = saved_lo & 0x3f; + + if ( used ) { + free = 64 - used; + + if ( BufferSize < free ) { + memcpy( &Context->buffer[used], Buffer, BufferSize ); + return; + } + + memcpy( &Context->buffer[used], Buffer, free ); + Buffer = (uint8_t*)Buffer + free; + BufferSize -= free; + TransformFunction(Context, Context->buffer, 64); + } + + if ( BufferSize >= 64 ) { + Buffer = TransformFunction( Context, Buffer, BufferSize & ~(uint32_t)0x3f ); + BufferSize &= 0x3f; + } + + memcpy( Context->buffer, Buffer, BufferSize ); +} + +/* Md5Finalise + * Performs the final calculation of the hash and returns the digest + * (16 byte buffer containing 128bit hash). + * After calling this, Md5Initialised must be used to reuse the context. + */ +void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */) { + uint32_t used; + uint32_t free; + + used = Context->lo & 0x3f; + + Context->buffer[used++] = 0x80; + + free = 64 - used; + + if (free < 8) { + memset( &Context->buffer[used], 0, free ); + TransformFunction( Context, Context->buffer, 64 ); + used = 0; + free = 64; + } + + memset( &Context->buffer[used], 0, free - 8 ); + + Context->lo <<= 3; + Context->buffer[56] = (uint8_t)(Context->lo); + Context->buffer[57] = (uint8_t)(Context->lo >> 8); + Context->buffer[58] = (uint8_t)(Context->lo >> 16); + Context->buffer[59] = (uint8_t)(Context->lo >> 24); + Context->buffer[60] = (uint8_t)(Context->hi); + Context->buffer[61] = (uint8_t)(Context->hi >> 8); + Context->buffer[62] = (uint8_t)(Context->hi >> 16); + Context->buffer[63] = (uint8_t)(Context->hi >> 24); + + TransformFunction( Context, Context->buffer, 64 ); + + Digest->bytes[0] = (uint8_t)(Context->a); + Digest->bytes[1] = (uint8_t)(Context->a >> 8); + Digest->bytes[2] = (uint8_t)(Context->a >> 16); + Digest->bytes[3] = (uint8_t)(Context->a >> 24); + Digest->bytes[4] = (uint8_t)(Context->b); + Digest->bytes[5] = (uint8_t)(Context->b >> 8); + Digest->bytes[6] = (uint8_t)(Context->b >> 16); + Digest->bytes[7] = (uint8_t)(Context->b >> 24); + Digest->bytes[8] = (uint8_t)(Context->c); + Digest->bytes[9] = (uint8_t)(Context->c >> 8); + Digest->bytes[10] = (uint8_t)(Context->c >> 16); + Digest->bytes[11] = (uint8_t)(Context->c >> 24); + Digest->bytes[12] = (uint8_t)(Context->d); + Digest->bytes[13] = (uint8_t)(Context->d >> 8); + Digest->bytes[14] = (uint8_t)(Context->d >> 16); + Digest->bytes[15] = (uint8_t)(Context->d >> 24); +} + +/* Md5Calculate + * Combines Md5Initialise, Md5Update, and Md5Finalise into one function. + * Calculates the MD5 hash of the buffer. + */ +void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */) { + Md5Context context; + + Md5Initialise( &context ); + Md5Update( &context, Buffer, BufferSize ); + Md5Finalise( &context, Digest ); +} diff --git a/src/stlink-lib/lib_md5.h b/src/stlink-lib/lib_md5.h new file mode 100644 index 000000000..abe1131ae --- /dev/null +++ b/src/stlink-lib/lib_md5.h @@ -0,0 +1,68 @@ +/* + * WjCryptLib_Md5 (https://github.com/WaterJuice/WjCryptLib) + * Implementation of MD5 hash function. Originally written by Alexander Peslyak. + * Modified by WaterJuice retaining Public Domain license. + * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org + */ + +#ifndef LIB_MD5_H +#define LIB_MD5_H + +#pragma once + +#include +#include + +/* TYPES */ + +/* Md5Context + * This must be initialised using Md5Initialised. + * Do not modify the contents of this structure directly. + */ +typedef struct { + uint32_t lo; + uint32_t hi; + uint32_t a; + uint32_t b; + uint32_t c; + uint32_t d; + uint8_t buffer[64]; + uint32_t block[16]; +} Md5Context; + +#define MD5_HASH_SIZE (128 / 8) + +typedef struct { + uint8_t bytes [MD5_HASH_SIZE]; +} MD5_HASH; + +/* PUBLIC FUNCTIONS */ + +/* Md5Initialise + * Initialises an MD5 Context. + * Use this to initialise/reset a context. + */ +void Md5Initialise(Md5Context* Context /* [out] */); + +/* Md5Update + * Adds data to the MD5 context. + * This will process the data and update the internal state of the context. + * Keep on calling this function until all the data has been added. + * Then call Md5Finalise to calculate the hash. + */ +void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */); + +/* Md5Finalise + * Performs the final calculation of the hash and returns the digest + * (16 byte buffer containing 128bit hash). + * After calling this, Md5Initialised must be used to reuse the context. + */ +void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */); + +/* Md5Calculate + * Combines Md5Initialise, Md5Update, and Md5Finalise into one function. + * Calculates the MD5 hash of the buffer. + */ +void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */); + +#endif // LIB_MD5_H \ No newline at end of file diff --git a/src/stlink-lib/logging.c b/src/stlink-lib/logging.c index 1463eb925..92092f3d0 100644 --- a/src/stlink-lib/logging.c +++ b/src/stlink-lib/logging.c @@ -1,15 +1,15 @@ /* - * UglyLogging + * File: logging.c * - * Slow, yet another wheel reinvented, but enough to make the rest of our code pretty enough. + * UglyLogging: Slow, yet another wheel reinvented, but enough to make the rest of our code pretty enough. */ -#include -#include +#define __STDC_WANT_LIB_EXT1__ 1 + #include #include -#include -#define __STDC_WANT_LIB_EXT1__ 1 + +#include #include #include "logging.h" diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index 471933096..d07db797d 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -1,4 +1,7 @@ /* + * File: logging.h + * + * UglyLogging: Slow, yet another wheel reinvented, but enough to make the rest of our code pretty enough. * Ugly, low performance, configurable level, logging "framework" */ diff --git a/src/stlink-lib/map_file.c b/src/stlink-lib/map_file.c index cfd2d1876..5e3d14a5d 100644 --- a/src/stlink-lib/map_file.c +++ b/src/stlink-lib/map_file.c @@ -4,24 +4,62 @@ * File mapping */ -#include #include +#include +#include + +#include #include #include #include -#include "logging.h" #include "map_file.h" -#include "md5.h" #ifndef O_BINARY #define O_BINARY 0 #endif +// 1 GB max file size #ifndef MAX_FILE_SIZE -#define MAX_FILE_SIZE (1<<20) // 1 GB max file size +#define MAX_FILE_SIZE (1<<20) #endif +/* Limit the block size to compare to 0x1800 as anything larger will stall the + * STLINK2 Maybe STLINK V1 needs smaller value! + */ +int32_t check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { + size_t off; + size_t n_cmp = sl->flash_pgsz; + + if (n_cmp > 0x1800) { + n_cmp = 0x1800; + } + + for (off = 0; off < mf->len; off += n_cmp) { + size_t aligned_size; + + size_t cmp_size = n_cmp; // adjust last page size + + if ((off + n_cmp) > mf->len) { + cmp_size = mf->len - off; + } + + aligned_size = cmp_size; + + if (aligned_size & (4 - 1)) { + aligned_size = (cmp_size + 4) & ~(4 - 1); + } + + stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); + + if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { + return (-1); + } + } + + return (0); +} + int32_t map_file(mapped_file_t *mf, const char *path) { int32_t error = -1; struct stat st; diff --git a/src/stlink-lib/map_file.h b/src/stlink-lib/map_file.h index b33ebf5db..ddedad93c 100644 --- a/src/stlink-lib/map_file.h +++ b/src/stlink-lib/map_file.h @@ -28,6 +28,7 @@ typedef struct mapped_file { #define MAPPED_FILE_INITIALIZER \ { NULL, 0 } +int32_t check_file(stlink_t *, mapped_file_t *, stm32_addr_t); int32_t map_file(mapped_file_t *, const char *); void unmap_file(mapped_file_t *); diff --git a/src/stlink-lib/md5.c b/src/stlink-lib/md5.c index f7af43ac3..070d9af91 100644 --- a/src/stlink-lib/md5.c +++ b/src/stlink-lib/md5.c @@ -1,10 +1,3 @@ -/* - * WjCryptLib_Md5 (https://github.com/WaterJuice/WjCryptLib) - * Implementation of MD5 hash function. Originally written by Alexander Peslyak. - * Modified by WaterJuice retaining Public Domain license. - * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org - */ - /* * File: md5.c * @@ -12,275 +5,37 @@ */ #include -#include +#include #include "md5.h" -/* INTERNAL FUNCTIONS */ - -/* F, G, H, I - * - * The basic MD5 functions. - * F and G are optimised compared to their RFC 1321 definitions for architectures - * that lack an AND-NOT instruction, just like in Colin Plumb's implementation. - */ -#define F( x, y, z ) ((z) ^ ((x) & ((y) ^ (z)))) -#define G( x, y, z ) ((y) ^ ((z) & ((x) ^ (y)))) -#define H( x, y, z ) ((x) ^ (y) ^ (z)) -#define I( x, y, z ) ((y) ^ ((x) | ~(z))) - -/* STEP: The MD5 transformation for all four rounds. */ -#define STEP( f, a, b, c, d, x, t, s ) \ - (a) += f((b), (c), (d)) + (x) + (t); \ - (a) = (((a) << (s)) | (((a) & 0xffffffff) >> (32 - (s)))); \ - (a) += (b); - -/* TransformFunction - * This processes one or more 64-byte data blocks, but does NOT update the bit counters. - * There are no alignment requirements. - */ -static void* TransformFunction(Md5Context* ctx, void const* data, uintmax_t size) { - uint8_t* ptr; - uint32_t a; - uint32_t b; - uint32_t c; - uint32_t d; - uint32_t saved_a; - uint32_t saved_b; - uint32_t saved_c; - uint32_t saved_d; - - #define GET(n) (ctx->block[(n)]) - #define SET(n) (ctx->block[(n)] = ((uint32_t)ptr[(n) * 4 + 0] << 0) | \ - ((uint32_t)ptr[(n) * 4 + 1] << 8) | \ - ((uint32_t)ptr[(n) * 4 + 2] << 16) | \ - ((uint32_t)ptr[(n) * 4 + 3] << 24)) - - ptr = (uint8_t*)data; - - a = ctx->a; - b = ctx->b; - c = ctx->c; - d = ctx->d; - - do { - saved_a = a; - saved_b = b; - saved_c = c; - saved_d = d; - - // Round 1 - STEP( F, a, b, c, d, SET(0), 0xd76aa478, 7 ) - STEP( F, d, a, b, c, SET(1), 0xe8c7b756, 12 ) - STEP( F, c, d, a, b, SET(2), 0x242070db, 17 ) - STEP( F, b, c, d, a, SET(3), 0xc1bdceee, 22 ) - STEP( F, a, b, c, d, SET(4), 0xf57c0faf, 7 ) - STEP( F, d, a, b, c, SET(5), 0x4787c62a, 12 ) - STEP( F, c, d, a, b, SET(6), 0xa8304613, 17 ) - STEP( F, b, c, d, a, SET(7), 0xfd469501, 22 ) - STEP( F, a, b, c, d, SET(8 ), 0x698098d8, 7 ) - STEP( F, d, a, b, c, SET(9 ), 0x8b44f7af, 12 ) - STEP( F, c, d, a, b, SET(10 ), 0xffff5bb1, 17 ) - STEP( F, b, c, d, a, SET(11 ), 0x895cd7be, 22 ) - STEP( F, a, b, c, d, SET(12 ), 0x6b901122, 7 ) - STEP( F, d, a, b, c, SET(13 ), 0xfd987193, 12 ) - STEP( F, c, d, a, b, SET(14 ), 0xa679438e, 17 ) - STEP( F, b, c, d, a, SET(15 ), 0x49b40821, 22 ) - - // Round 2 - STEP( G, a, b, c, d, GET(1), 0xf61e2562, 5 ) - STEP( G, d, a, b, c, GET(6), 0xc040b340, 9 ) - STEP( G, c, d, a, b, GET(11), 0x265e5a51, 14 ) - STEP( G, b, c, d, a, GET(0), 0xe9b6c7aa, 20 ) - STEP( G, a, b, c, d, GET(5), 0xd62f105d, 5 ) - STEP( G, d, a, b, c, GET(10), 0x02441453, 9 ) - STEP( G, c, d, a, b, GET(15), 0xd8a1e681, 14 ) - STEP( G, b, c, d, a, GET(4), 0xe7d3fbc8, 20 ) - STEP( G, a, b, c, d, GET(9), 0x21e1cde6, 5 ) - STEP( G, d, a, b, c, GET(14), 0xc33707d6, 9 ) - STEP( G, c, d, a, b, GET(3), 0xf4d50d87, 14 ) - STEP( G, b, c, d, a, GET(8), 0x455a14ed, 20 ) - STEP( G, a, b, c, d, GET(13), 0xa9e3e905, 5 ) - STEP( G, d, a, b, c, GET(2), 0xfcefa3f8, 9 ) - STEP( G, c, d, a, b, GET(7), 0x676f02d9, 14 ) - STEP( G, b, c, d, a, GET(12), 0x8d2a4c8a, 20 ) - - // Round 3 - STEP( H, a, b, c, d, GET(5), 0xfffa3942, 4 ) - STEP( H, d, a, b, c, GET(8), 0x8771f681, 11 ) - STEP( H, c, d, a, b, GET(11), 0x6d9d6122, 16 ) - STEP( H, b, c, d, a, GET(14), 0xfde5380c, 23 ) - STEP( H, a, b, c, d, GET(1), 0xa4beea44, 4 ) - STEP( H, d, a, b, c, GET(4), 0x4bdecfa9, 11 ) - STEP( H, c, d, a, b, GET(7), 0xf6bb4b60, 16 ) - STEP( H, b, c, d, a, GET(10), 0xbebfbc70, 23 ) - STEP( H, a, b, c, d, GET(13), 0x289b7ec6, 4 ) - STEP( H, d, a, b, c, GET(0), 0xeaa127fa, 11 ) - STEP( H, c, d, a, b, GET(3), 0xd4ef3085, 16 ) - STEP( H, b, c, d, a, GET(6), 0x04881d05, 23 ) - STEP( H, a, b, c, d, GET(9), 0xd9d4d039, 4 ) - STEP( H, d, a, b, c, GET(12), 0xe6db99e5, 11 ) - STEP( H, c, d, a, b, GET(15), 0x1fa27cf8, 16 ) - STEP( H, b, c, d, a, GET(2), 0xc4ac5665, 23 ) - - // Round 4 - STEP( I, a, b, c, d, GET(0), 0xf4292244, 6 ) - STEP( I, d, a, b, c, GET(7), 0x432aff97, 10 ) - STEP( I, c, d, a, b, GET(14), 0xab9423a7, 15 ) - STEP( I, b, c, d, a, GET(5), 0xfc93a039, 21 ) - STEP( I, a, b, c, d, GET(12), 0x655b59c3, 6 ) - STEP( I, d, a, b, c, GET(3), 0x8f0ccc92, 10 ) - STEP( I, c, d, a, b, GET(10), 0xffeff47d, 15 ) - STEP( I, b, c, d, a, GET(1), 0x85845dd1, 21 ) - STEP( I, a, b, c, d, GET(8), 0x6fa87e4f, 6 ) - STEP( I, d, a, b, c, GET(15), 0xfe2ce6e0, 10 ) - STEP( I, c, d, a, b, GET(6), 0xa3014314, 15 ) - STEP( I, b, c, d, a, GET(13), 0x4e0811a1, 21 ) - STEP( I, a, b, c, d, GET(4), 0xf7537e82, 6 ) - STEP( I, d, a, b, c, GET(11), 0xbd3af235, 10 ) - STEP( I, c, d, a, b, GET(2), 0x2ad7d2bb, 15 ) - STEP( I, b, c, d, a, GET(9), 0xeb86d391, 21 ) - - a += saved_a; - b += saved_b; - c += saved_c; - d += saved_d; - - ptr += 64; - } while ( size -= 64 ); - - ctx->a = a; - ctx->b = b; - ctx->c = c; - ctx->d = d; - - #undef GET - #undef SET - - return(ptr); -} - -/* EXPORTED FUNCTIONS */ +#include "map_file.h" +#include "lib_md5.h" -/* Md5Initialise - * Initialises an MD5 Context. - * Use this to initialise/reset a context. - */ -void Md5Initialise(Md5Context* Context /* [out] */) { - Context->a = 0x67452301; - Context->b = 0xefcdab89; - Context->c = 0x98badcfe; - Context->d = 0x10325476; - - Context->lo = 0; - Context->hi = 0; -} - -/* Md5Update - * Adds data to the MD5 context. - * This will process the data and update the internal state of the context. - * Keep on calling this function until all the data has been added. - * Then call Md5Finalise to calculate the hash. - */ -void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */) { - uint32_t saved_lo; - uint32_t used; - uint32_t free; - - saved_lo = Context->lo; - - if ((Context->lo = (saved_lo + BufferSize) & 0x1fffffff) < saved_lo) { - Context->hi++; - } - - Context->hi += (uint32_t)(BufferSize >> 29); - - used = saved_lo & 0x3f; - - if ( used ) { - free = 64 - used; - - if ( BufferSize < free ) { - memcpy( &Context->buffer[used], Buffer, BufferSize ); - return; - } - - memcpy( &Context->buffer[used], Buffer, free ); - Buffer = (uint8_t*)Buffer + free; - BufferSize -= free; - TransformFunction(Context, Context->buffer, 64); - } +void md5_calculate(mapped_file_t *mf) { + // calculate md5 checksum of given binary file + Md5Context md5Context; + MD5_HASH md5Hash; + Md5Initialise(&md5Context); + Md5Update(&md5Context, mf->base, (uint32_t)mf->len); + Md5Finalise(&md5Context, &md5Hash); + printf("md5 checksum: "); - if ( BufferSize >= 64 ) { - Buffer = TransformFunction( Context, Buffer, BufferSize & ~(uint32_t)0x3f ); - BufferSize &= 0x3f; - } + for (int32_t i = 0; i < (int32_t)sizeof(md5Hash); i++) { + printf("%x", md5Hash.bytes[i]); + } - memcpy( Context->buffer, Buffer, BufferSize ); + printf(", "); } -/* Md5Finalise - * Performs the final calculation of the hash and returns the digest - * (16 byte buffer containing 128bit hash). - * After calling this, Md5Initialised must be used to reuse the context. - */ -void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */) { - uint32_t used; - uint32_t free; - - used = Context->lo & 0x3f; - - Context->buffer[used++] = 0x80; - - free = 64 - used; - - if (free < 8) { - memset( &Context->buffer[used], 0, free ); - TransformFunction( Context, Context->buffer, 64 ); - used = 0; - free = 64; - } - - memset( &Context->buffer[used], 0, free - 8 ); +void stlink_checksum(mapped_file_t *mp) { + /* checksum that backward compatible with official ST tools */ + uint32_t sum = 0; + uint8_t *mp_byte = (uint8_t *)mp->base; - Context->lo <<= 3; - Context->buffer[56] = (uint8_t)(Context->lo); - Context->buffer[57] = (uint8_t)(Context->lo >> 8); - Context->buffer[58] = (uint8_t)(Context->lo >> 16); - Context->buffer[59] = (uint8_t)(Context->lo >> 24); - Context->buffer[60] = (uint8_t)(Context->hi); - Context->buffer[61] = (uint8_t)(Context->hi >> 8); - Context->buffer[62] = (uint8_t)(Context->hi >> 16); - Context->buffer[63] = (uint8_t)(Context->hi >> 24); + for (size_t i = 0; i < mp->len; ++i) { + sum += mp_byte[i]; + } - TransformFunction( Context, Context->buffer, 64 ); - - Digest->bytes[0] = (uint8_t)(Context->a); - Digest->bytes[1] = (uint8_t)(Context->a >> 8); - Digest->bytes[2] = (uint8_t)(Context->a >> 16); - Digest->bytes[3] = (uint8_t)(Context->a >> 24); - Digest->bytes[4] = (uint8_t)(Context->b); - Digest->bytes[5] = (uint8_t)(Context->b >> 8); - Digest->bytes[6] = (uint8_t)(Context->b >> 16); - Digest->bytes[7] = (uint8_t)(Context->b >> 24); - Digest->bytes[8] = (uint8_t)(Context->c); - Digest->bytes[9] = (uint8_t)(Context->c >> 8); - Digest->bytes[10] = (uint8_t)(Context->c >> 16); - Digest->bytes[11] = (uint8_t)(Context->c >> 24); - Digest->bytes[12] = (uint8_t)(Context->d); - Digest->bytes[13] = (uint8_t)(Context->d >> 8); - Digest->bytes[14] = (uint8_t)(Context->d >> 16); - Digest->bytes[15] = (uint8_t)(Context->d >> 24); -} - -/* Md5Calculate - * Combines Md5Initialise, Md5Update, and Md5Finalise into one function. - * Calculates the MD5 hash of the buffer. - */ -void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */) { - Md5Context context; - - Md5Initialise( &context ); - Md5Update( &context, Buffer, BufferSize ); - Md5Finalise( &context, Digest ); -} + printf("stlink checksum: 0x%08x\n", sum); +} \ No newline at end of file diff --git a/src/stlink-lib/md5.h b/src/stlink-lib/md5.h index 23c5d971b..eb36d64cc 100644 --- a/src/stlink-lib/md5.h +++ b/src/stlink-lib/md5.h @@ -1,10 +1,3 @@ -/* - * WjCryptLib_Md5 (https://github.com/WaterJuice/WjCryptLib) - * Implementation of MD5 hash function. Originally written by Alexander Peslyak. - * Modified by WaterJuice retaining Public Domain license. - * This is free and unencumbered software released into the public domain - June 2013 - waterjuice.org - */ - /* * File: md5.h * @@ -14,61 +7,11 @@ #ifndef MD5_H #define MD5_H -#pragma once - #include -#include - -/* TYPES */ - -/* Md5Context - * This must be initialised using Md5Initialised. - * Do not modify the contents of this structure directly. - */ -typedef struct { - uint32_t lo; - uint32_t hi; - uint32_t a; - uint32_t b; - uint32_t c; - uint32_t d; - uint8_t buffer[64]; - uint32_t block[16]; -} Md5Context; - -#define MD5_HASH_SIZE (128 / 8) -typedef struct { - uint8_t bytes [MD5_HASH_SIZE]; -} MD5_HASH; +#include "map_file.h" -/* PUBLIC FUNCTIONS */ - -/* Md5Initialise - * Initialises an MD5 Context. - * Use this to initialise/reset a context. - */ -void Md5Initialise(Md5Context* Context /* [out] */); - -/* Md5Update - * Adds data to the MD5 context. - * This will process the data and update the internal state of the context. - * Keep on calling this function until all the data has been added. - * Then call Md5Finalise to calculate the hash. - */ -void Md5Update(Md5Context* Context /* [in out] */, void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */); - -/* Md5Finalise - * Performs the final calculation of the hash and returns the digest - * (16 byte buffer containing 128bit hash). - * After calling this, Md5Initialised must be used to reuse the context. - */ -void Md5Finalise(Md5Context* Context /* [in out] */, MD5_HASH* Digest /* [in] */); - -/* Md5Calculate - * Combines Md5Initialise, Md5Update, and Md5Finalise into one function. - * Calculates the MD5 hash of the buffer. - */ -void Md5Calculate(void const* Buffer /* [in] */, uint32_t BufferSize /* [in] */, MD5_HASH* Digest /* [in] */); +void md5_calculate(mapped_file_t *); +void stlink_checksum(mapped_file_t *); #endif // MD5_H \ No newline at end of file diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 6a12333cd..624d43a0a 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -9,11 +9,13 @@ #include #include -#include "common.h" -#include "common_flash.h" -#include "map_file.h" #include "option_bytes.h" +#include "common_flash.h" +#include "flash_loader.h" +#include "logging.h" +#include "map_file.h" +#include "md5.h" /** * Read option control register F0 diff --git a/src/stlink-lib/option_bytes.h b/src/stlink-lib/option_bytes.h index c0a1c9a6d..a58ea3857 100644 --- a/src/stlink-lib/option_bytes.h +++ b/src/stlink-lib/option_bytes.h @@ -8,9 +8,6 @@ #define OPTION_BYTES_H #include -#include - -#include int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); int32_t stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); diff --git a/src/stlink-lib/read_write.c b/src/stlink-lib/read_write.c index f9c060bb2..6ee697d66 100644 --- a/src/stlink-lib/read_write.c +++ b/src/stlink-lib/read_write.c @@ -4,6 +4,8 @@ #include +#include "logging.h" + // Endianness // https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html // These functions encode and decode little endian uint16 and uint32 values. diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 4db8c6164..860b92b70 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -1,5 +1,3 @@ -/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ - /* * Copyright (c) 2010 "Capt'ns Missing Link" Authors. All rights reserved. * Use of this source code is governed by a BSD-style @@ -84,17 +82,21 @@ #define __USE_GNU -#include #include #include #include #include -#include +#include +// #include -#include -#include "logging.h" #include "sg.h" +#include "commands.h" +#include "logging.h" +#include "register.h" +#include "usb.h" +// #include + #define STLINK_OK 0x80 #define STLINK_FALSE 0x81 diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index 1ab433142..cc3ea725e 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -1,5 +1,3 @@ -/* == nightwalker-87: TODO: CONTENT AND USE OF THIS HEADER FILE IS TO BE VERIFIED (07.06.2023) == */ - /* * File: sg.h * @@ -12,6 +10,7 @@ #include #include + #include "libusb_settings.h" /* Device access */ diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 9dc4a0ebd..907a32190 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -4,28 +4,31 @@ * USB commands & interaction with ST-LINK devices */ -#include -#include -#include -#include -#include - #if !defined(_MSC_VER) #include #endif -#include -#include -#include - #if defined(_WIN32) #include #endif +#include +#include +#include +#include + +#include +#include +#include +#include + #include -#include "helper.h" #include "usb.h" +#include "commands.h" +#include "logging.h" +#include "register.h" + enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; static inline uint32_t le_to_h_u32(const uint8_t* buf) { diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index 83c0c2481..b99e46f53 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -7,10 +7,8 @@ #ifndef USB_H #define USB_H -#include #include -#include #include "libusb_settings.h" #include "logging.h" From fc990648c4a0b91bdea539e699248f59d1157f51 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 9 Jun 2023 12:55:25 +0200 Subject: [PATCH 1382/1435] [refactoring] Clean-up for stlink-lib - Ensure proper function declaration - Checked & revised header includes --- src/stlink-lib/calculate.h | 2 -- src/stlink-lib/chipid.c | 1 + src/stlink-lib/chipid.h | 7 +++-- src/stlink-lib/common_flash.h | 2 -- src/stlink-lib/flash_loader.h | 2 -- src/stlink-lib/helper.c | 5 ++-- src/stlink-lib/helper.h | 5 ---- src/stlink-lib/lib_md5.c | 1 + src/stlink-lib/lib_md5.h | 3 -- src/stlink-lib/logging.h | 10 +++---- src/stlink-lib/map_file.h | 6 ++-- src/stlink-lib/md5.c | 1 + src/stlink-lib/md5.h | 2 -- src/stlink-lib/option_bytes.c | 3 +- src/stlink-lib/option_bytes.h | 44 +++++++++++++++++++++------- src/stlink-lib/register.h | 2 +- src/stlink-lib/sg.c | 12 ++++---- src/stlink-lib/sg.h | 42 +++++++++++++++++++++++++++ src/stlink-lib/usb.c | 27 ++++++++++-------- src/stlink-lib/usb.h | 54 +++++++++++++++++++++++++++++------ 20 files changed, 159 insertions(+), 72 deletions(-) diff --git a/src/stlink-lib/calculate.h b/src/stlink-lib/calculate.h index bdff782ae..64dfb51b2 100644 --- a/src/stlink-lib/calculate.h +++ b/src/stlink-lib/calculate.h @@ -7,8 +7,6 @@ #ifndef CALCULATE_H #define CALCULATE_H -#include - uint32_t calculate_F4_sectornum(uint32_t); uint32_t calculate_F7_sectornum(uint32_t); uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, unsigned); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index c622abcbb..a4abf90d8 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -223,6 +223,7 @@ void init_chipids(char *dir_to_scan) { return; } } + #endif // STLINK_HAVE_DIRENT_H #if defined(_WIN32) && !defined(STLINK_HAVE_DIRENT_H) diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index d7319f569..a72a40be9 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -7,8 +7,6 @@ #ifndef CHIPID_H #define CHIPID_H -#include - /* Chipid parametres */ struct stlink_chipid_params { char *dev_type; @@ -27,6 +25,9 @@ struct stlink_chipid_params { }; struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); - void init_chipids(char *dir_to_scan); + +void dump_a_chip(struct stlink_chipid_params *dev); +void process_chipfile(char *fname); +void init_chipids(char *dir_to_scan); #endif // CHIPID_H diff --git a/src/stlink-lib/common_flash.h b/src/stlink-lib/common_flash.h index 092bdcbf4..fd1e51b9d 100644 --- a/src/stlink-lib/common_flash.h +++ b/src/stlink-lib/common_flash.h @@ -7,8 +7,6 @@ #ifndef COMMON_FLASH_H #define COMMON_FLASH_H -#include - #define BANK_1 0 #define BANK_2 1 diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 61a2a0c19..06eb53d12 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -7,8 +7,6 @@ #ifndef FLASH_LOADER_H #define FLASH_LOADER_H -#include - int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); // static int32_t loader_v_dependent_assignment(stlink_t *sl, // const uint8_t **loader_code, size_t *loader_size, diff --git a/src/stlink-lib/helper.c b/src/stlink-lib/helper.c index 97d6eb316..1e756f1de 100644 --- a/src/stlink-lib/helper.c +++ b/src/stlink-lib/helper.c @@ -1,15 +1,14 @@ -/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ - /* * File: helper.c * * General helper functions */ + #ifdef STLINK_HAVE_SYS_TIME_H #include #else #include -#endif +#endif // STLINK_HAVE_SYS_TIME_H #include #include diff --git a/src/stlink-lib/helper.h b/src/stlink-lib/helper.h index a42fd480e..ef374a5b6 100644 --- a/src/stlink-lib/helper.h +++ b/src/stlink-lib/helper.h @@ -1,5 +1,3 @@ -/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ - /* * File: helper.h * @@ -9,10 +7,7 @@ #ifndef HELPER_H #define HELPER_H -#include - uint32_t time_ms(); - int32_t arg_parse_freq(const char *str); #endif // HELPER_H diff --git a/src/stlink-lib/lib_md5.c b/src/stlink-lib/lib_md5.c index 42f337ac3..71703273c 100644 --- a/src/stlink-lib/lib_md5.c +++ b/src/stlink-lib/lib_md5.c @@ -6,6 +6,7 @@ */ #include +#include #include #include "lib_md5.h" diff --git a/src/stlink-lib/lib_md5.h b/src/stlink-lib/lib_md5.h index abe1131ae..7275fd0bd 100644 --- a/src/stlink-lib/lib_md5.h +++ b/src/stlink-lib/lib_md5.h @@ -10,9 +10,6 @@ #pragma once -#include -#include - /* TYPES */ /* Md5Context diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index d07db797d..cb49a7af3 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -8,11 +8,9 @@ #ifndef LOGGING_H #define LOGGING_H -#include - #ifdef __cplusplus extern "C" { -#endif +#endif // __cplusplus enum ugly_loglevel { UDEBUG = 90, @@ -25,7 +23,7 @@ enum ugly_loglevel { #define PRINTF_ARRT __attribute__ ((format (printf, 3, 4))) #else #define PRINTF_ARRT -#endif +#endif // __GNUC__ int32_t ugly_init(int32_t maximum_threshold); int32_t ugly_log(int32_t level, const char *tag, const char *format, ...) PRINTF_ARRT; @@ -48,6 +46,6 @@ int32_t ugly_libusb_log_level(enum ugly_loglevel v); #ifdef __cplusplus } -#endif +#endif // __cplusplus -#endif // LOGGING_H +#endif // LOGGING_H diff --git a/src/stlink-lib/map_file.h b/src/stlink-lib/map_file.h index ddedad93c..ba50e25e9 100644 --- a/src/stlink-lib/map_file.h +++ b/src/stlink-lib/map_file.h @@ -7,17 +7,15 @@ #ifndef MAP_FILE_H #define MAP_FILE_H -#include - #ifndef O_BINARY #define O_BINARY 0 -#endif +#endif // O_BINARY #ifdef STLINK_HAVE_SYS_MMAN_H #include #else #include -#endif +#endif // STLINK_HAVE_SYS_MMAN_H /* Memory mapped file */ typedef struct mapped_file { diff --git a/src/stlink-lib/md5.c b/src/stlink-lib/md5.c index 070d9af91..9481acf0f 100644 --- a/src/stlink-lib/md5.c +++ b/src/stlink-lib/md5.c @@ -5,6 +5,7 @@ */ #include +#include #include #include "md5.h" diff --git a/src/stlink-lib/md5.h b/src/stlink-lib/md5.h index eb36d64cc..f5591e2c3 100644 --- a/src/stlink-lib/md5.h +++ b/src/stlink-lib/md5.h @@ -7,8 +7,6 @@ #ifndef MD5_H #define MD5_H -#include - #include "map_file.h" void md5_calculate(mapped_file_t *); diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 624d43a0a..c84ace348 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -426,8 +426,7 @@ int32_t stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte * @param option_byte * @return 0 on success, -ve on failure. */ -static int -stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_add) { +static int32_t stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_add) { ILOG("Asked to write option byte boot add %#010x.\n", option_byte_boot_add); return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); } diff --git a/src/stlink-lib/option_bytes.h b/src/stlink-lib/option_bytes.h index a58ea3857..ffeef8a0f 100644 --- a/src/stlink-lib/option_bytes.h +++ b/src/stlink-lib/option_bytes.h @@ -7,19 +7,41 @@ #ifndef OPTION_BYTES_H #define OPTION_BYTES_H -#include - +int32_t stlink_read_option_control_register_f0(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_bytes_f0(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); +// static int32_t stlink_write_option_control_register_f0(stlink_t *sl, uint32_t option_cr); +int32_t stlink_read_option_control_register_f2(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_read_option_control_register_f4(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_bytes_f4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +int32_t stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_bytes_f7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +int32_t stlink_read_option_control_register_f7(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_control_register_f7(stlink_t *sl, uint32_t option_cr); +int32_t stlink_read_option_control_register1_f7(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_control_register1_f7(stlink_t *sl, uint32_t option_cr1); +int32_t stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_bytes_boot_add_f7(stlink_t *sl, uint32_t option_byte_boot_add); +int32_t stlink_read_option_control_register_gx(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_read_option_bytes_gx(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_bytes_gx(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +// static int32_t stlink_write_option_bytes_h7(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +// static int32_t stlink_write_option_bytes_l0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +// static int32_t stlink_write_option_bytes_l4(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +// static int32_t stlink_write_option_bytes_wb(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +int32_t stlink_read_option_control_register_wb(stlink_t *sl, uint32_t *option_byte); +// static int32_t stlink_write_option_control_register_wb(stlink_t *sl, uint32_t option_cr); +int32_t stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); +int32_t stlink_fwrite_option_bytes(stlink_t *sl, const char *path, stm32_addr_t addr); +int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr); +int32_t stlink_read_option_control_register1_32(stlink_t *sl, uint32_t *option_byte); +int32_t stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1); int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t* option_byte); -int32_t stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); -int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t* option_byte); -int32_t stlink_read_option_control_register1_32(stlink_t *sl, uint32_t* option_byte); - int32_t stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); +int32_t stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); int32_t stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); -int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr); -int32_t stlink_write_option_control_register1_32(stlink_t *sl, uint32_t option_cr1); - -int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t* base, uint32_t len); -int32_t stlink_fwrite_option_bytes(stlink_t *sl, const char* path, stm32_addr_t addr); #endif // OPTION_BYTES_H \ No newline at end of file diff --git a/src/stlink-lib/register.h b/src/stlink-lib/register.h index 7b63154c8..f1e9574cd 100644 --- a/src/stlink-lib/register.h +++ b/src/stlink-lib/register.h @@ -129,4 +129,4 @@ #define STLINK_REG_CM7_ICIALLU 0xE000EF50 #define STLINK_REG_CM7_CCSIDR 0xE000ED80 -#endif // REG_H +#endif // REGISTER_H diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 860b92b70..0aa7a0d68 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + /* * Copyright (c) 2010 "Capt'ns Missing Link" Authors. All rights reserved. * Use of this source code is governed by a BSD-style @@ -87,7 +89,7 @@ #include #include #include -// #include +// #include // TODO: Check use #include "sg.h" @@ -95,7 +97,7 @@ #include "logging.h" #include "register.h" #include "usb.h" -// #include +// #include // TODO: Check use #define STLINK_OK 0x80 #define STLINK_FALSE 0x81 @@ -150,6 +152,7 @@ static int32_t get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t uint32_t rsig = read_uint32(csw, 0); uint32_t rtag = read_uint32(csw, 4); /* uint32_t residue = read_uint32(csw, 8); */ + #define USB_CSW_SIGNATURE 0x53425355 // 'U' 'S' 'B' 'S' (reversed) if (rsig != USB_CSW_SIGNATURE) { @@ -187,9 +190,8 @@ static int32_t dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { * @param expected_rx_size * @return */ -int32_t send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, - uint8_t *cdb, uint8_t cdb_length, - uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { +int32_t send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, uint8_t *cdb, uint8_t cdb_length, + uint8_t lun, uint8_t flags, uint32_t expected_rx_size) { DLOG("Sending usb m-s cmd: cdblen:%d, rxsize=%d\n", cdb_length, expected_rx_size); dump_CDB_command(cdb, cdb_length); diff --git a/src/stlink-lib/sg.h b/src/stlink-lib/sg.h index cc3ea725e..b10d0f6f0 100644 --- a/src/stlink-lib/sg.h +++ b/src/stlink-lib/sg.h @@ -1,3 +1,5 @@ +/* == nightwalker-87: TODO: CONTENT AND USE OF THIS SOURCE FILE IS TO BE VERIFIED (07.06.2023) == */ + /* * File: sg.h * @@ -58,6 +60,46 @@ struct stlink_libsg { struct stlink_reg reg; }; +// static void clear_cdb(struct stlink_libsg *sl); +void _stlink_sg_close(stlink_t *sl); +// static int32_t get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t endpoint, uint32_t *tag); +// static int32_t dump_CDB_command(uint8_t *cdb, uint8_t cdb_len); +int32_t send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endpoint_out, uint8_t *cdb, uint8_t cdb_length, + uint8_t lun, uint8_t flags, uint32_t expected_rx_size); +// static void get_sense(libusb_device_handle *handle, uint8_t endpoint_in, uint8_t endpoint_out); +int32_t send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_out, + unsigned char endpoint_in, unsigned char *cbuf, uint32_t length); +int32_t stlink_q(stlink_t *sl); +void stlink_stat(stlink_t *stl, char *txt); +int32_t _stlink_sg_version(stlink_t *stl); +int32_t _stlink_sg_current_mode(stlink_t *stl); +int32_t _stlink_sg_enter_swd_mode(stlink_t *sl); +int32_t _stlink_sg_enter_jtag_mode(stlink_t *sl); +int32_t _stlink_sg_exit_dfu_mode(stlink_t *sl); +int32_t _stlink_sg_core_id(stlink_t *sl); +int32_t _stlink_sg_reset(stlink_t *sl); +int32_t _stlink_sg_jtag_reset(stlink_t *sl, int32_t value); +int32_t _stlink_sg_status(stlink_t *sl); +int32_t _stlink_sg_force_debug(stlink_t *sl); +int32_t _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp); +int32_t _stlink_sg_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int32_t idx); +void stlink_write_dreg(stlink_t *sl, uint32_t reg, uint32_t addr); +int32_t _stlink_sg_run(stlink_t *sl, enum run_type type); +int32_t _stlink_sg_step(stlink_t *sl); +void stlink_set_hw_bp(stlink_t *sl, int32_t fp_nr, uint32_t addr, int32_t fp); +void stlink_clr_hw_bp(stlink_t *sl, int32_t fp_nr); +int32_t _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); +int32_t _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); +int32_t _stlink_sg_exit_debug_mode(stlink_t *stl); + +// static stlink_backend_t _stlink_sg_backend = { }; + +// static stlink_t* stlink_open(const int32_t verbose); +stlink_t* stlink_v1_open_inner(const int32_t verbose); stlink_t* stlink_v1_open(const int32_t verbose, int32_t reset); #endif // SG_H diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 907a32190..fc1dcbb4e 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -6,11 +6,11 @@ #if !defined(_MSC_VER) #include -#endif +#endif // _MSC_VER #if defined(_WIN32) #include -#endif +#endif // _WIN32 #include #include @@ -29,8 +29,6 @@ #include "logging.h" #include "register.h" -enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; - static inline uint32_t le_to_h_u32(const uint8_t* buf) { return((uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24)); } @@ -92,9 +90,8 @@ void _stlink_usb_close(stlink_t* sl) { } } -ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, - unsigned char* txbuf, size_t txsize, unsigned char* rxbuf, - size_t rxsize, int32_t check_error, const char *cmd) { +ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, size_t txsize, + unsigned char* rxbuf, size_t rxsize, int32_t check_error, const char *cmd) { // Note: txbuf and rxbuf can point to the same area int32_t res, t, retry = 0; @@ -170,9 +167,8 @@ ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, } } -static inline int32_t send_only(struct stlink_libusb* handle, int32_t terminate, - unsigned char* txbuf, size_t txsize, - const char *cmd) { +static inline int32_t send_only(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, + size_t txsize, const char *cmd) { return((int32_t)send_recv(handle, terminate, txbuf, txsize, NULL, 0, CMD_CHECK_NO, cmd)); } @@ -359,7 +355,6 @@ int32_t _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { return(0); } - int32_t _stlink_usb_current_mode(stlink_t * sl) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const cmd = sl->c_buf; @@ -1113,6 +1108,14 @@ size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_d return strlen(serial); } +/** + * Open a stlink + * @param verbose Verbosity loglevel + * @param connect Type of connect to target + * @param serial Serial number to search for, when NULL the first stlink found is opened (binary format) + * @retval NULL Error while opening the stlink + * @retval !NULL Stlink found and ready to use + */ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int32_t freq) { stlink_t* sl = NULL; struct stlink_libusb* slu = NULL; @@ -1208,7 +1211,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, goto on_libusb_error; } } -#endif +#endif // NOT _WIN32 if (libusb_get_configuration(slu->usb_handle, &config)) { // this may fail for a previous configured device diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index b99e46f53..dd30cc529 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -46,6 +46,8 @@ #define STLINK_SG_SIZE 31 #define STLINK_CMD_SIZE 16 +enum SCSI_Generic_Direction {SG_DXFER_TO_DEV = 0, SG_DXFER_FROM_DEV = 0x80}; + struct stlink_libusb { libusb_context* libusb_ctx; libusb_device_handle* usb_handle; @@ -57,16 +59,50 @@ struct stlink_libusb { uint32_t cmd_len; }; -/** - * Open a stlink - * @param verbose Verbosity loglevel - * @param connect Type of connect to target - * @param serial Serial number to search for, when NULL the first stlink found is opened (binary format) - * @retval NULL Error while opening the stlink - * @retval !NULL Stlink found and ready to use - */ - +// static inline uint32_t le_to_h_u32(const uint8_t* buf); +// static int32_t _stlink_match_speed_map(const uint32_t *map, uint32_t map_size, uint32_t khz); +void _stlink_usb_close(stlink_t* sl); +ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, size_t txsize, + unsigned char* rxbuf, size_t rxsize, int32_t check_error, const char *cmd); +// static inline int32_t send_only(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, +// size_t txsize, const char *cmd); +// static int32_t fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t len); +int32_t _stlink_usb_version(stlink_t *sl); +int32_t _stlink_usb_target_voltage(stlink_t *sl); +int32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); +int32_t _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); +int32_t _stlink_usb_get_rw_status(stlink_t *sl); +int32_t _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_usb_current_mode(stlink_t * sl); +int32_t _stlink_usb_core_id(stlink_t * sl); +int32_t _stlink_usb_status_v2(stlink_t *sl); +int32_t _stlink_usb_status(stlink_t * sl); +int32_t _stlink_usb_force_debug(stlink_t *sl); +int32_t _stlink_usb_enter_swd_mode(stlink_t * sl); +int32_t _stlink_usb_exit_dfu_mode(stlink_t* sl); +int32_t _stlink_usb_reset(stlink_t * sl); +int32_t _stlink_usb_jtag_reset(stlink_t * sl, int32_t value); +int32_t _stlink_usb_step(stlink_t* sl); +int32_t _stlink_usb_run(stlink_t* sl, enum run_type type); +int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq); +int32_t _stlink_usb_exit_debug_mode(stlink_t *sl); +int32_t _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp); +int32_t _stlink_usb_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t _stlink_usb_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); +int32_t _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_idx, struct stlink_reg *regp); +int32_t _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int32_t idx); +int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency); +int32_t _stlink_usb_disable_trace(stlink_t* sl); +int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size); + +// static stlink_backend_t _stlink_usb_backend = { }; + +size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_descriptor *desc, char *serial); stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int32_t freq); +// static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int32_t freq); size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t freq); void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); From efc5c3713d3124a1e8c6189a6cab960c700a50b9 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 9 Jun 2023 14:51:57 +0200 Subject: [PATCH 1383/1435] Fixed flash-write/verify error (Closes #1303) --- src/stlink-lib/common_flash.c | 3 --- src/stlink-lib/flash_loader.c | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 6ade87311..194fa7aab 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1439,9 +1439,6 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 (uint32_t)(sl->flash_pgsz)); return (-1); } - if ((len % 16 <= 8) & (sl->flash_type == STM32_FLASH_TYPE_L5_U5)) { - len += 8; - } // make sure we've loaded the context with the chip details stlink_core_id(sl); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 3472e2a61..2bac1ace0 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -474,7 +474,7 @@ int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, if (sl->verbose >= 1) { // show progress; writing procedure is slow and previous errors are misleading - fprintf(stdout, "\r%3u/%u halfpages written", count + 1, num_half_pages); + fprintf(stdout, "\r%3u/%3u halfpages written", count + 1, num_half_pages); fflush(stdout); } From 755c20c08ea026549439a97be2351540069c7f9e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 10 Jun 2023 20:07:19 +0200 Subject: [PATCH 1384/1435] Replace data types with fixed width typedefs (C99) - Unified variable type: size_t --> uint32_t - Removed unnecessary explicit casts - Minor formatting fixes --- inc/backend.h | 2 +- inc/stlink.h | 18 +++--- src/st-flash/flash.c | 14 ++--- src/st-flash/flash.h | 4 +- src/st-flash/flash_opts.c | 12 ++-- src/st-info/info.c | 18 +++--- src/st-util/gdb-server.c | 54 +++++++++--------- src/stlink-gui/gui.c | 2 +- src/stlink-lib/calculate.c | 7 +-- src/stlink-lib/calculate.h | 2 +- src/stlink-lib/chipid.c | 2 +- src/stlink-lib/common.c | 61 ++++++++++---------- src/stlink-lib/common_flash.c | 47 +++++++--------- src/stlink-lib/common_flash.h | 4 +- src/stlink-lib/flash_loader.c | 103 ++++++++++++++-------------------- src/stlink-lib/flash_loader.h | 10 ++-- src/stlink-lib/map_file.c | 12 ++-- src/stlink-lib/map_file.h | 2 +- src/stlink-lib/md5.c | 2 +- src/stlink-lib/option_bytes.h | 2 +- src/stlink-lib/read_write.c | 2 +- src/stlink-lib/sg.c | 2 +- src/stlink-lib/usb.c | 24 ++++---- src/stlink-lib/usb.h | 12 ++-- src/win32/getopt/getopt.c | 2 +- src/win32/mmap.c | 4 +- src/win32/mmap.h | 4 +- tests/flash.c | 4 +- 28 files changed, 200 insertions(+), 232 deletions(-) diff --git a/inc/backend.h b/inc/backend.h index a9a7d6e03..6b9c9c0a8 100644 --- a/inc/backend.h +++ b/inc/backend.h @@ -33,7 +33,7 @@ int32_t (*set_swdclk) (stlink_t * stl, int32_t freq_khz); int32_t (*trace_enable) (stlink_t * sl, uint32_t frequency); int32_t (*trace_disable) (stlink_t * sl); - int32_t (*trace_read) (stlink_t * sl, uint8_t* buf, size_t size); + int32_t (*trace_read) (stlink_t * sl, uint8_t* buf, uint32_t size); } stlink_backend_t; #endif // BACKEND_H diff --git a/inc/stlink.h b/inc/stlink.h index b2516c90c..d5d036725 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -210,22 +210,22 @@ struct _stlink { // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STM32_FLASH_TYPE_xx stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() - size_t flash_size; // calculated by stlink_load_device_params() - size_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() + uint32_t flash_size; // calculated by stlink_load_device_params() + uint32_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() /* sram settings */ stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() - size_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() + uint32_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() /* option settings */ stm32_addr_t option_base; - size_t option_size; + uint32_t option_size; // bootloader // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code // (see tests/sg.c) stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() - size_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() + uint32_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() struct stlink_version_ version; @@ -262,8 +262,8 @@ int32_t stlink_target_voltage(stlink_t *sl); int32_t stlink_set_swdclk(stlink_t *sl, int32_t freq_khz); int32_t stlink_trace_enable(stlink_t* sl, uint32_t frequency); int32_t stlink_trace_disable(stlink_t* sl); -int32_t stlink_trace_read(stlink_t* sl, uint8_t* buf, size_t size); -int32_t stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, size_t * size, uint32_t * begin); +int32_t stlink_trace_read(stlink_t* sl, uint8_t* buf, uint32_t size); +int32_t stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t * * mem, uint32_t * size, uint32_t * begin); uint8_t stlink_get_erased_pattern(stlink_t *sl); int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); int32_t stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr); @@ -278,9 +278,9 @@ uint32_t read_uint32(const unsigned char *c, const int32_t pt); void write_uint32(unsigned char* buf, uint32_t ui); void write_uint16(unsigned char* buf, uint16_t ui); bool stlink_is_core_halted(stlink_t *sl); -int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size); +int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, uint32_t size); int32_t write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); -int32_t stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, size_t size); +int32_t stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t addr, uint32_t size); int32_t stlink_load_device_params(stlink_t *sl); int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect); diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 6b4a10cfc..9a648bd63 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -83,7 +83,7 @@ int32_t main(int32_t ac, char** av) { if ( o.flash_size != 0u && o.flash_size != sl->flash_size ) { sl->flash_size = o.flash_size; - printf("Forcing flash size: --flash=0x%08X\n", (uint32_t)sl->flash_size); + printf("Forcing flash size: --flash=0x%08X\n", sl->flash_size); } sl->verbose = o.log_level; @@ -106,7 +106,7 @@ int32_t main(int32_t ac, char** av) { } if (o.cmd == FLASH_CMD_WRITE) { - size_t size = 0; + uint32_t size = 0; // write if (o.format == FLASH_FORMAT_IHEX) { @@ -119,7 +119,7 @@ int32_t main(int32_t ac, char** av) { } if ((o.addr >= sl->flash_base) && (o.addr < sl->flash_base + sl->flash_size)) { if (o.format == FLASH_FORMAT_IHEX) { - err = stlink_mwrite_flash(sl, mem, (uint32_t)size, o.addr); + err = stlink_mwrite_flash(sl, mem, size, o.addr); } else { err = stlink_fwrite_flash(sl, o.filename, o.addr); } @@ -130,7 +130,7 @@ int32_t main(int32_t ac, char** av) { } } else if ((o.addr >= sl->sram_base) && (o.addr < sl->sram_base + sl->sram_size)) { if (o.format == FLASH_FORMAT_IHEX) { - err = stlink_mwrite_sram(sl, mem, (uint32_t)size, o.addr); + err = stlink_mwrite_sram(sl, mem, size, o.addr); } else { err = stlink_fwrite_sram(sl, o.filename, o.addr); } @@ -221,10 +221,10 @@ int32_t main(int32_t ac, char** av) { goto on_error; } } else if (o.area == FLASH_OPTION_BYTES) { - size_t remaining_option_length = sl->option_size / 4; + uint32_t remaining_option_length = sl->option_size / 4; DLOG("@@@@ Read %u (%#x) option bytes from %#10x\n", - (uint32_t)remaining_option_length, - (uint32_t)remaining_option_length, + remaining_option_length, + remaining_option_length, sl->option_base); uint32_t option_byte = 0; diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index 1a509a660..84c171158 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -17,13 +17,13 @@ struct flash_opts { uint8_t serial[STLINK_SERIAL_BUFFER_SIZE]; const char* filename; stm32_addr_t addr; - size_t size; + uint32_t size; int32_t reset; int32_t log_level; enum flash_format format; enum flash_area area; uint32_t val; - size_t flash_size; // --flash=n[k, M] + uint32_t flash_size; // --flash=n[k, M] int32_t opt; // enable empty tail data drop optimization int32_t freq; // --freq=n[k, M] frequency of JTAG/SWD enum connect_type connect; diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index e133d52c7..35763ad50 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -8,7 +8,7 @@ #include "flash.h" static bool starts_with(const char * str, const char * prefix) { - size_t n = strlen(prefix); + uint32_t n = strlen(prefix); if (strlen(str) < n) { return(false); } @@ -61,7 +61,7 @@ static int32_t get_integer_from_char_array (const char *const str, uint32_t *rea fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, cannot convert to int32_t\n"); return(-1); } else { - *read_value = (uint32_t)value; + *read_value = value; return(0); } } @@ -318,7 +318,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { if (result != 0) { return bad_arg ("val"); } else { - o->val = (uint32_t) val; + o->val = val; } } else if (o->area == FLASH_OPTION_BYTES_BOOT_ADD) { // expect option bytes boot address if (ac != 1) { return invalid_args("option bytes boot_add write "); } @@ -329,7 +329,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { if (result != 0) { return(bad_arg ("val")); } else { - o->val = (uint32_t)val; + o->val = val; } } else if (o->area == FLASH_OPTCR) { // expect option control register value if (ac != 1) { return invalid_args("option control register write "); } @@ -340,7 +340,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { if (result != 0) { return bad_arg ("val"); } else { - o->val = (uint32_t) val; + o->val = val; } } else if (o->area == FLASH_OPTCR1) { // expect option control register 1 value if (ac != 1) { return invalid_args("option control register 1 write "); } @@ -350,7 +350,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { if (result != 0) { return bad_arg ("val"); } else { - o->val = (uint32_t) val; + o->val = val; } } else if (o->format == FLASH_FORMAT_BINARY) { // expect filename and addr if (ac != 2) { return invalid_args("write "); } diff --git a/src/st-info/info.c b/src/st-info/info.c index 86a1c2d8f..b6ec0ccd2 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -35,8 +35,8 @@ static void stlink_print_info(stlink_t *sl) { printf(" version: "); stlink_print_version(sl); printf(" serial: %s\n", sl->serial); - printf(" flash: %u (pagesize: %u)\n", (uint32_t)sl->flash_size, (uint32_t)sl->flash_pgsz); - printf(" sram: %u\n", (uint32_t)sl->sram_size); + printf(" flash: %u (pagesize: %u)\n", sl->flash_size, sl->flash_pgsz); + printf(" sram: %u\n", sl->sram_size); printf(" chipid: 0x%.3x\n", sl->chip_id); params = stlink_chipid_get_params(sl->chip_id); @@ -45,14 +45,14 @@ static void stlink_print_info(stlink_t *sl) { static void stlink_probe(enum connect_type connect, int32_t freq) { stlink_t **stdevs; - size_t size; + uint32_t size; size = stlink_probe_usb(&stdevs, connect, freq); - printf("Found %u stlink programmers\n", (uint32_t)size); + printf("Found %u stlink programmers\n", size); - for (size_t n = 0; n < size; n++) { - if (size > 1) printf("%u.\n", (uint32_t)n+1); + for (uint32_t n = 0; n < size; n++) { + if (size > 1) printf("%u.\n", n+1); stlink_print_info(stdevs[n]); } @@ -107,11 +107,11 @@ static int32_t print_data(int32_t ac, char **av) { if (strcmp(av[1], "--serial") == 0) { printf("%s\n", sl->serial); } else if (strcmp(av[1], "--flash") == 0) { - printf("0x%x\n", (uint32_t)sl->flash_size); + printf("0x%x\n", sl->flash_size); } else if (strcmp(av[1], "--pagesize") == 0) { - printf("0x%x\n", (uint32_t)sl->flash_pgsz); + printf("0x%x\n", sl->flash_pgsz); } else if (strcmp(av[1], "--sram") == 0) { - printf("0x%x\n", (uint32_t)sl->sram_size); + printf("0x%x\n", sl->sram_size); } else if (strcmp(av[1], "--chipid") == 0) { printf("0x%.4x\n", sl->chip_id); } else if (strcmp(av[1], "--descr") == 0) { diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 431e37eec..7232f0f69 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -554,7 +554,7 @@ static const char* const memory_map_template_F4_DE = char* make_memory_map(stlink_t *sl) { // this will be freed in serve() - const size_t sz = 4096; + const uint32_t sz = 4096; char* map = malloc(sz); map[0] = '\0'; @@ -566,42 +566,42 @@ char* make_memory_map(stlink_t *sl) { strcpy(map, memory_map_template_F4_DE); } else if (sl->core_id == STM32_CORE_ID_M7F_SWD) { snprintf(map, sz, memory_map_template_F7, - (uint32_t)sl->sram_size); + sl->sram_size); } else if (sl->chip_id == STM32_CHIPID_H74xxx) { snprintf(map, sz, memory_map_template_H7, - (uint32_t)sl->flash_size, - (uint32_t)sl->flash_pgsz); + sl->flash_size, + sl->flash_pgsz); } else if (sl->chip_id == STM32_CHIPID_F4_HD) { strcpy(map, memory_map_template_F4_HD); } else if (sl->chip_id == STM32_CHIPID_F2) { snprintf(map, sz, memory_map_template_F2, - (uint32_t)sl->flash_size, - (uint32_t)sl->sram_size, - (uint32_t)sl->flash_size - 0x20000, - (uint32_t)sl->sys_base, - (uint32_t)sl->sys_size); + sl->flash_size, + sl->sram_size, + sl->flash_size - 0x20000, + sl->sys_base, + sl->sys_size); } else if ((sl->chip_id == STM32_CHIPID_L4) || (sl->chip_id == STM32_CHIPID_L43x_L44x) || (sl->chip_id == STM32_CHIPID_L45x_L46x)) { snprintf(map, sz, memory_map_template_L4, - (uint32_t)sl->flash_size, - (uint32_t)sl->flash_size); + sl->flash_size, + sl->flash_size); } else if (sl->chip_id == STM32_CHIPID_L496x_L4A6x) { snprintf(map, sz, memory_map_template_L496, - (uint32_t)sl->flash_size, - (uint32_t)sl->flash_size); + sl->flash_size, + sl->flash_size); } else if (sl->chip_id == STM32_CHIPID_H72x) { snprintf(map, sz, memory_map_template_H72x3x, - (uint32_t)sl->flash_size, - (uint32_t)sl->flash_pgsz); + sl->flash_size, + sl->flash_pgsz); } else { snprintf(map, sz, memory_map_template, - (uint32_t)sl->flash_size, - (uint32_t)sl->sram_size, - (uint32_t)sl->flash_size, - (uint32_t)sl->flash_pgsz, - (uint32_t)sl->sys_base, - (uint32_t)sl->sys_size); + sl->flash_size, + sl->sram_size, + sl->flash_size, + sl->flash_pgsz, + sl->sys_base, + sl->sys_size); } return(map); @@ -1074,8 +1074,8 @@ static void cache_sync(stlink_t *sl) { if (ccr & (STLINK_REG_CM7_CCR_IC | STLINK_REG_CM7_CCR_DC)) { cache_flush(sl, ccr); } } -static size_t unhexify(const char *in, char *out, size_t out_count) { - size_t i; +static uint32_t unhexify(const char *in, char *out, uint32_t out_count) { + uint32_t i; uint32_t c; for (i = 0; i < out_count; i++) { @@ -1248,9 +1248,9 @@ int32_t serve(stlink_t *sl, st_state_t *st) { params = separator + 1; } - size_t hex_len = strlen(params); - size_t alloc_size = (hex_len / 2) + 1; - size_t cmd_len; + uint32_t hex_len = strlen(params); + uint32_t alloc_size = (hex_len / 2) + 1; + uint32_t cmd_len; char *cmd = malloc(alloc_size); if (cmd == NULL) { @@ -1669,7 +1669,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { uint32_t adj_start = start % 4; uint32_t count_rnd = (count + adj_start + 4 - 1) / 4 * 4; - if (count_rnd > sl->flash_pgsz) { count_rnd = (uint32_t)sl->flash_pgsz; } + if (count_rnd > sl->flash_pgsz) { count_rnd = sl->flash_pgsz; } if (count_rnd > 0x1800) { count_rnd = 0x1800; } diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index f1e9382d0..af2afcdbf 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -262,7 +262,7 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { */ uint8_t* mem = NULL; - size_t size = 0; + uint32_t size = 0; uint32_t begin = 0; int32_t res = stlink_parse_ihex(gui->filename, 0, &mem, &size, &begin); diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index b13a1c961..027239694 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -47,8 +47,7 @@ uint32_t calculate_F7_sectornum(uint32_t flashaddr) { } } -uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, - uint32_t bank) { +uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, uint32_t bank) { flashaddr &= ~((bank == BANK_1) ? STM32_FLASH_BASE @@ -68,7 +67,7 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { sl->chip_id == STM32_CHIPID_L4Rx) { // this chip use dual banked flash if (flashopt & (uint32_t)(1lu << FLASH_L4_OPTR_DUALBANK)) { - uint32_t banksize = (uint32_t)sl->flash_size / 2; + uint32_t banksize = sl->flash_size / 2; if (flashaddr >= banksize) { flashaddr -= banksize; @@ -79,5 +78,5 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { // For 1MB chips without the dual-bank option set, the page address will // overflow into the BKER bit, which gives us the correct bank:page value. - return (bker | flashaddr / (uint32_t)sl->flash_pgsz); + return (bker | flashaddr / sl->flash_pgsz); } diff --git a/src/stlink-lib/calculate.h b/src/stlink-lib/calculate.h index 64dfb51b2..ca0a39df6 100644 --- a/src/stlink-lib/calculate.h +++ b/src/stlink-lib/calculate.h @@ -9,7 +9,7 @@ uint32_t calculate_F4_sectornum(uint32_t); uint32_t calculate_F7_sectornum(uint32_t); -uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, unsigned); +uint32_t calculate_H7_sectornum(stlink_t *, uint32_t, uint32_t); uint32_t calculate_L4_page(stlink_t *, uint32_t); #endif // CALCULATE_H diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index a4abf90d8..0392f15ff 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -196,7 +196,7 @@ void process_chipfile(char *fname) { void init_chipids(char *dir_to_scan) { DIR *d; - size_t nl; // namelen + uint32_t nl; // namelen struct dirent *dir; if (!dir_to_scan) { diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index d6477281d..70ecdd3a2 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -56,7 +56,7 @@ int32_t stlink_jtag_reset(stlink_t *, int32_t); int32_t stlink_soft_reset(stlink_t *, int32_t); void _parse_version(stlink_t *, stlink_version_t *); static uint8_t stlink_parse_hex(const char *); -static int32_t stlink_read(stlink_t *, stm32_addr_t, size_t, save_block_fn, void *); +static int32_t stlink_read(stlink_t *, stm32_addr_t, uint32_t, save_block_fn, void *); static bool stlink_fread_ihex_init(struct stlink_fread_ihex_worker_arg *, int32_t, stm32_addr_t); static bool stlink_fread_ihex_worker(void *, uint8_t *, ssize_t); static bool stlink_fread_ihex_finalize(struct stlink_fread_ihex_worker_arg *); @@ -323,8 +323,8 @@ int32_t stlink_load_device_params(stlink_t *sl) { } ILOG("%s: %u KiB SRAM, %u KiB flash in at least %u %s pages.\n", - params->dev_type, (uint32_t)(sl->sram_size / 1024), (uint32_t)(sl->flash_size / 1024), - (sl->flash_pgsz < 1024) ? (uint32_t)(sl->flash_pgsz) : (uint32_t)(sl->flash_pgsz / 1024), + params->dev_type, (sl->sram_size / 1024), (sl->flash_size / 1024), + (sl->flash_pgsz < 1024) ? sl->flash_pgsz : (sl->flash_pgsz / 1024), (sl->flash_pgsz < 1024) ? "byte" : "KiB"); return (0); @@ -609,7 +609,7 @@ int32_t stlink_trace_disable(stlink_t *sl) { } // 276 -int32_t stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { +int32_t stlink_trace_read(stlink_t *sl, uint8_t *buf, uint32_t size) { return (sl->backend->trace_read(sl, buf, size)); } @@ -645,8 +645,8 @@ int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, stm32_a // write the file in sram at addr int32_t error = -1; - size_t off; - size_t len; + uint32_t off; + uint32_t len; // check addr range is inside the sram if (addr < sl->sram_base) { @@ -671,7 +671,7 @@ int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, stm32_a // do the copy by 1kB blocks for (off = 0; off < len; off += 1024) { - size_t size = 1024; + uint32_t size = 1024; if ((off + size) > len) { size = len - off; @@ -683,12 +683,12 @@ int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, stm32_a size += 2; } // round size if needed - stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); + stlink_write_mem32(sl, addr + off, (uint16_t)size); } if (length > len) { memcpy(sl->q_buf, data + len, length - len); - stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(length - len)); + stlink_write_mem8(sl, addr + len, (uint16_t)(length - len)); } error = 0; // success @@ -703,8 +703,8 @@ int32_t stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { // write the file in sram at addr int32_t error = -1; - size_t off; - size_t len; + uint32_t off; + uint32_t len; mapped_file_t mf = MAPPED_FILE_INITIALIZER; if (map_file(&mf, path) == -1) { @@ -739,7 +739,7 @@ int32_t stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { // do the copy by 1kB blocks for (off = 0; off < len; off += 1024) { - size_t size = 1024; + uint32_t size = 1024; if ((off + size) > len) { size = len - off; @@ -751,12 +751,12 @@ int32_t stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { size += 2; } // round size if needed - stlink_write_mem32(sl, addr + (uint32_t)off, (uint16_t)size); + stlink_write_mem32(sl, addr + off, (uint16_t)size); } if (mf.len > len) { memcpy(sl->q_buf, mf.base + len, mf.len - len); - stlink_write_mem8(sl, addr + (uint32_t)len, (uint16_t)(mf.len - len)); + stlink_write_mem8(sl, addr + len, (uint16_t)(mf.len - len)); } // check the file has been written @@ -774,9 +774,9 @@ int32_t stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { } // 302 -int32_t stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t addr, size_t size) { +int32_t stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t addr, uint32_t size) { // read size bytes from addr to file - ILOG("read from address %#010x size %u\n", addr, (uint32_t)size); + ILOG("read from address %#010x size %u\n", addr, size); int32_t error; int32_t fd = open(path, O_RDWR | O_TRUNC | O_CREAT | O_BINARY, 00700); @@ -808,11 +808,11 @@ int32_t stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t } // 300 -int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, size_t size) { +int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, uint32_t size) { // write the buffer right after the loader int32_t ret = 0; - size_t chunk = size & ~0x3; - size_t rem = size & 0x3; + uint32_t chunk = size & ~0x3; + uint32_t rem = size & 0x3; if (chunk) { memcpy(sl->q_buf, buf, chunk); @@ -821,7 +821,7 @@ int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *bu if (rem && !ret) { memcpy(sl->q_buf, buf + chunk, rem); - ret = stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, (uint16_t)rem); + ret = stlink_write_mem8(sl, (fl->buf_addr) + chunk, (uint16_t)rem); } return (ret); @@ -865,12 +865,12 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { } } - return ((uint32_t)sl->flash_pgsz); + return (sl->flash_pgsz); } // 279 int32_t stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **mem, - size_t *size, uint32_t *begin) { + uint32_t *size, uint32_t *begin) { int32_t res = 0; *begin = UINT32_MAX; uint8_t *data = NULL; @@ -896,7 +896,7 @@ int32_t stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **me data = calloc(*size, 1); // use calloc to get NULL if out of memory if (!data) { - ELOG("Cannot allocate %u bytes\n", (uint32_t)(*size)); + ELOG("Cannot allocate %u bytes\n", (*size)); res = -1; break; } @@ -926,7 +926,7 @@ int32_t stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **me break; } - size_t l = strlen(line); + uint32_t l = strlen(line); while (l > 0 && (line[l - 1] == '\n' || line[l - 1] == '\r')) { --l; @@ -942,7 +942,7 @@ int32_t stlink_parse_ihex(const char *path, uint8_t erased_pattern, uint8_t **me uint8_t chksum = 0; // check sum - for (size_t i = 1; i < l; i += 2) { + for (uint32_t i = 1; i < l; i += 2) { chksum += stlink_parse_hex(line + i); } @@ -1215,8 +1215,7 @@ void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { } } -static int32_t stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, - save_block_fn fn, void *fn_arg) { +static int32_t stlink_read(stlink_t *sl, stm32_addr_t addr, uint32_t size, save_block_fn fn, void *fn_arg) { int32_t error = -1; @@ -1228,10 +1227,10 @@ static int32_t stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, size = sl->flash_size; } - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; + uint32_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; - for (size_t off = 0; off < size; off += cmp_size) { - size_t aligned_size; + for (uint32_t off = 0; off < size; off += cmp_size) { + uint32_t aligned_size; // adjust last page size if ((off + cmp_size) > size) { @@ -1244,7 +1243,7 @@ static int32_t stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, aligned_size = (cmp_size + 4) & ~(4 - 1); } - stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); + stlink_read_mem32(sl, addr + off, (uint16_t)aligned_size); if (!fn(fn_arg, sl->q_buf, aligned_size)) { goto on_error; diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 194fa7aab..70c8a2216 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1027,10 +1027,8 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); // check pecr.prglock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -1069,16 +1067,14 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // set the page to erase if (sl->flash_type == STM32_FLASH_TYPE_G0) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, FLASH_Gx_CR, &val); // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. val &= ~(0x3F << 3); val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_Gx_CR, val); } else if (sl->flash_type == STM32_FLASH_TYPE_G4) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, FLASH_Gx_CR, &val); // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. val &= ~(0x7F << 3); @@ -1088,13 +1084,11 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { uint32_t flash_page; stlink_read_debug32(sl, FLASH_L5_NSCR, &val); if (sl->flash_pgsz == 0x800 && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) { - flash_page = (flashaddr - STM32_FLASH_BASE - sl->flash_size/2) / - (uint32_t)(sl->flash_pgsz); + flash_page = (flashaddr - STM32_FLASH_BASE - sl->flash_size/2) / sl->flash_pgsz; // set bank 2 for erasure val |= (1 << FLASH_L5_NSCR_NSBKER); } else { - flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); // set bank 1 for erasure val &= ~(1 << FLASH_L5_NSCR_NSBKER); } @@ -1103,8 +1097,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_L5_NSCR, val); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { - uint32_t flash_page = - ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, FLASH_WB_CR, &val); // sec 3.10.5 - PNB[7:0] is offset by 3. @@ -1133,8 +1126,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { uint32_t bank = (flashaddr < STM32_H7_FLASH_BANK2_BASE) ? BANK_1 : BANK_2; unlock_flash_if(sl); // unlock if locked - uint32_t sector = calculate_H7_sectornum( - sl, flashaddr, bank); // calculate the actual page from the address + uint32_t sector = calculate_H7_sectornum(sl, flashaddr, bank); // calculate the actual page from the address write_flash_cr_snb(sl, sector, bank); // select the page to erase set_flash_cr_strt(sl, bank); // start erase operation wait_flash_busy(sl); // wait for completion @@ -1147,7 +1139,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { return check_flash_error(sl); } -int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size) { +int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, uint32_t size, bool align_size) { // Check the address and size validity if (stlink_check_address_range_validity(sl, base_addr, size) < 0) { return -1; @@ -1247,7 +1239,7 @@ int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, stm32_ * Therfore it is turned off by default. */ if (sl->opt) { - idx = (uint32_t)length; + idx = length; for (num_empty = 0; num_empty != length; ++num_empty) if (data[--idx] != erased_pattern) { @@ -1270,9 +1262,8 @@ int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, stm32_ * still flash the whole file even if ignoring message is printed. */ err = stlink_write_flash(sl, addr, data, - (num_empty == length) ? (uint32_t)length - : (uint32_t)length - num_empty, - num_empty == length); + (num_empty == length) ? length : length - num_empty, + num_empty == length); stlink_fwrite_finalize(sl, addr); return (err); } @@ -1358,12 +1349,12 @@ int32_t stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { * @return 0 for success, -ve for failure */ int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length) { - size_t off; - size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; + uint32_t off; + uint32_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; ILOG("Starting verification of write complete\n"); for (off = 0; off < length; off += cmp_size) { - size_t aligned_size; + uint32_t aligned_size; // adjust last page size if ((off + cmp_size) > length) { @@ -1376,10 +1367,10 @@ int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *d aligned_size = (cmp_size + 4) & ~(4 - 1); } - stlink_read_mem32(sl, address + (uint32_t)off, (uint16_t)aligned_size); + stlink_read_mem32(sl, address + off, (uint16_t)aligned_size); if (memcmp(sl->q_buf, data + off, cmp_size)) { - ELOG("Verification of flash failed at offset: %u\n", (uint32_t)off); + ELOG("Verification of flash failed at offset: %u\n", off); return (-1); } } @@ -1389,7 +1380,7 @@ int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *d } // Check if an address and size are within the flash -int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size) { +int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, uint32_t size) { uint32_t logvar; if (addr < sl->flash_base || addr >= (sl->flash_base + sl->flash_size)) { logvar = sl->flash_base + sl->flash_size - 1; @@ -1436,7 +1427,7 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 ELOG("addr not a multiple of current pagesize (%u bytes), not supported, " "check page start address and compare with flash module organisation " "in related ST reference manual of your device.\n", - (uint32_t)(sl->flash_pgsz)); + sl->flash_pgsz); return (-1); } diff --git a/src/stlink-lib/common_flash.h b/src/stlink-lib/common_flash.h index fd1e51b9d..9b2b84057 100644 --- a/src/stlink-lib/common_flash.h +++ b/src/stlink-lib/common_flash.h @@ -37,13 +37,13 @@ void clear_flash_cr_pg(stlink_t *, uint32_t); // static void set_flash_cr_strt(stlink_t *sl, uint32_t bank); // static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank); int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr); -int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, size_t size, bool align_size); +int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, uint32_t size, bool align_size); int32_t stlink_erase_flash_mass(stlink_t *sl); int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, stm32_addr_t addr); int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr); int32_t stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr); int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); -int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, size_t size); +int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, uint32_t size); int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint8_t eraseonly); void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 2bac1ace0..a862bd0e7 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -162,7 +162,7 @@ static const uint8_t loader_code_stm32f7_lv[] = { int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { - size_t size = 0; + uint32_t size = 0; uint32_t dfsr, cfsr, hfsr; /* Interrupt masking according to DDI0419C, Table C1-7 firstly force halt */ @@ -172,8 +172,7 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { /* and only then disable interrupts */ stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_MASKINTS); + STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_MASKINTS); // allocate the loader in SRAM if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { @@ -182,7 +181,7 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { } // allocate a one page buffer in SRAM right after loader - fl->buf_addr = fl->loader_addr + (uint32_t)size; + fl->buf_addr = fl->loader_addr + size; ILOG("Successfully loaded flash loader in sram\n"); // set address of IWDG key register for reset it @@ -210,9 +209,9 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { } static int32_t loader_v_dependent_assignment(stlink_t *sl, - const uint8_t **loader_code, size_t *loader_size, - const uint8_t *high_v_loader, size_t high_v_loader_size, - const uint8_t *low_v_loader, size_t low_v_loader_size) { + const uint8_t **loader_code, uint32_t *loader_size, + const uint8_t *high_v_loader, uint32_t high_v_loader_size, + const uint8_t *low_v_loader, uint32_t low_v_loader_size) { int32_t retval = 0; if ( sl->version.stlink_v == 1) { @@ -239,9 +238,9 @@ static int32_t loader_v_dependent_assignment(stlink_t *sl, return(retval); } -int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { +int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, uint32_t* size) { const uint8_t* loader_code; - size_t loader_size; + uint32_t loader_size; if (sl->chip_id == STM32_CHIPID_L1_MD || sl->chip_id == STM32_CHIPID_L1_CAT2 || @@ -330,13 +329,13 @@ int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size return(0); // success } -int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { +int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, uint32_t size) { struct stlink_reg rr; uint32_t timeout; uint32_t flash_base = 0; uint32_t dhcsr, dfsr, cfsr, hfsr; - DLOG("Running flash loader, write address:%#x, size: %u\n", target, (uint32_t)size); + DLOG("Running flash loader, write address:%#x, size: %u\n", target, size); if (write_buffer_to_sram(sl, fl, buf, size) == -1) { ELOG("write_buffer_to_sram() == -1\n"); @@ -350,7 +349,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t /* Setup core */ stlink_write_reg(sl, fl->buf_addr, 0); // source stlink_write_reg(sl, target, 1); // target - stlink_write_reg(sl, (uint32_t)size, 2); // count + stlink_write_reg(sl, size, 2); // count stlink_write_reg(sl, flash_base, 3); // flash register base // only used on VL/F1_XL, but harmless for others stlink_write_reg(sl, fl->loader_addr, 15); // pc register @@ -417,8 +416,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t WLOG("Loader state: R2 0x%X R15 0x%X\n", rr.r[2], rr.r[15]); if (dhcsr != 0x3000B || dfsr || cfsr || hfsr) { - WLOG("MCU state: DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X\n", - dhcsr, dfsr, cfsr, hfsr); + WLOG("MCU state: DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X\n", dhcsr, dfsr, cfsr, hfsr); } return(-1); @@ -450,8 +448,7 @@ int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, for (count = 0; count < num_half_pages; count++) { if (use_loader) { - ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, - base + count * pagesize, pagesize); + ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize); if (ret && count == 0) { /* It seems that stm32lx devices have a problem when it is blank */ WLOG("Failed to use flash loader, fallback to soft write\n"); @@ -461,7 +458,7 @@ int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, if (!use_loader) { ret = 0; for (off = 0; off < pagesize && !ret; off += 64) { - size_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; + uint32_t chunk = (pagesize - off > 64) ? 64 : pagesize - off; memcpy(sl->q_buf, base + count * pagesize + off, chunk); ret = stlink_write_mem32(sl, addr + count * pagesize + off, (uint16_t)chunk); } @@ -632,9 +629,7 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { ILOG("enabling 32-bit flash writes\n"); write_flash_cr_psiz(sl, 2, BANK_1); } else { - ILOG("Target voltage (%d mV) too low for 32-bit flash, " - "using 8-bit flash writes\n", - voltage); + ILOG("Target voltage (%d mV) too low for 32-bit flash, using 8-bit flash writes\n", voltage); write_flash_cr_psiz(sl, 0, BANK_1); } } @@ -656,10 +651,8 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { uint32_t flash_regs_base = get_stm32l0_flash_base(sl); // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); // check pecr.pelock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -669,10 +662,8 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { } // unlock program memory - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, - FLASH_L0_PRGKEY2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, FLASH_L0_PRGKEY2); // check pecr.prglock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -728,17 +719,15 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { } int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { - size_t off; + uint32_t off; if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || (sl->flash_type == STM32_FLASH_TYPE_L4)) { - size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; + uint32_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; for (off = 0; off < len;) { - size_t size = len - off > buf_size ? buf_size : len - off; - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (uint32_t)(addr + off)); + uint32_t size = len - off > buf_size ? buf_size : len - off; + if (stlink_flash_loader_run(sl, fl, addr + off, base + off, size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (addr + off)); check_flash_error(sl); return (-1); } @@ -749,38 +738,34 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - DLOG("Starting %3u page write\r\n", (uint32_t)(len / sl->flash_pgsz)); + DLOG("Starting %3u page write\n", len / sl->flash_pgsz); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (uint32_t)(off / sl->flash_pgsz + 1), - (uint32_t)(len / sl->flash_pgsz)); + fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); fflush(stdout); } // write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); data = 0; memcpy(&data, base + off, (len - off) < 4 ? (len - off) : 4); - stlink_write_debug32(sl, addr + (uint32_t)off, data); + stlink_write_debug32(sl, addr + off, data); wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } fprintf(stdout, "\n"); // flash writes happen as 2 words at a time if ((off / sizeof(uint32_t)) % 2 != 0) { - stlink_write_debug32(sl, addr + (uint32_t)off, - 0); // write a single word of zeros - wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear + stlink_write_debug32(sl, addr + off, 0); // write a single word of zeros + wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear } } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - uint32_t pagesize = (flash_regs_base == FLASH_L0_REGS_ADDR)? - L0_WRITE_BLOCK_SIZE:L1_WRITE_BLOCK_SIZE; + uint32_t pagesize = (flash_regs_base == FLASH_L0_REGS_ADDR)? L0_WRITE_BLOCK_SIZE : L1_WRITE_BLOCK_SIZE; - DLOG("Starting %3u page write\r\n", (uint32_t)(len / sl->flash_pgsz)); + DLOG("Starting %3u page write\r\n", len / sl->flash_pgsz); off = 0; @@ -797,14 +782,12 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t uint32_t data; if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", - (uint32_t)(off / sl->flash_pgsz + 1), - (uint32_t)(len / sl->flash_pgsz)); + fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); fflush(stdout); } write_uint32((unsigned char *)&data, *(uint32_t *)(base + off)); - stlink_write_debug32(sl, addr + (uint32_t)off, data); + stlink_write_debug32(sl, addr + off, data); // wait for sr.busy to be cleared do { @@ -814,22 +797,19 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t // TODO: check redo write operation } fprintf(stdout, "\n"); - } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { int32_t write_block_count = 0; for (off = 0; off < len; off += sl->flash_pgsz) { // adjust last write size - size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; + uint32_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; // unlock and set programming mode unlock_flash_if(sl); DLOG("Finished unlocking flash, running loader!\n"); - if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, - size) == -1) { - ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", - (uint32_t)(addr + off)); + if (stlink_flash_loader_run(sl, fl, addr + off, base + off, size) == -1) { + ELOG("stlink_flash_loader_run(%#x) failed! == -1\n", (addr + off)); check_flash_error(sl); return (-1); } @@ -840,7 +820,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t // show progress; writing procedure is slow and previous errors are // misleading fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, - (uint32_t)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); + (len + sl->flash_pgsz - 1) / sl->flash_pgsz); fflush(stdout); } } @@ -850,17 +830,16 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { for (off = 0; off < len;) { // Program STM32H7x with 64-byte Flash words - size_t chunk = (len - off > 64) ? 64 : len - off; + uint32_t chunk = (len - off > 64) ? 64 : len - off; memcpy(sl->q_buf, base + off, chunk); - stlink_write_mem32(sl, addr + (uint32_t)off, 64); + stlink_write_mem32(sl, addr + off, 64); wait_flash_busy(sl); off += chunk; if (sl->verbose >= 1) { // show progress - fprintf(stdout, "\r%u/%u bytes written", (uint32_t)off, - (uint32_t)len); + fprintf(stdout, "\r%u/%u bytes written", off, len); fflush(stdout); } } diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 06eb53d12..33edc7ac6 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -9,11 +9,11 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t* fl); // static int32_t loader_v_dependent_assignment(stlink_t *sl, -// const uint8_t **loader_code, size_t *loader_size, -// const uint8_t *high_v_loader, size_t high_v_loader_size, -// const uint8_t *low_v_loader, size_t low_v_loader_size); -int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); -int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); +// const uint8_t **loader_code, uint32_t *loader_size, +// const uint8_t *high_v_loader, uint32_t high_v_loader_size, +// const uint8_t *low_v_loader, uint32_t low_v_loader_size); +int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, uint32_t* size); +int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, uint32_t size); /* === Functions from old header file flashloader.h === */ diff --git a/src/stlink-lib/map_file.c b/src/stlink-lib/map_file.c index 5e3d14a5d..e8c4b71a3 100644 --- a/src/stlink-lib/map_file.c +++ b/src/stlink-lib/map_file.c @@ -28,17 +28,17 @@ * STLINK2 Maybe STLINK V1 needs smaller value! */ int32_t check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { - size_t off; - size_t n_cmp = sl->flash_pgsz; + uint32_t off; + uint32_t n_cmp = sl->flash_pgsz; if (n_cmp > 0x1800) { n_cmp = 0x1800; } for (off = 0; off < mf->len; off += n_cmp) { - size_t aligned_size; + uint32_t aligned_size; - size_t cmp_size = n_cmp; // adjust last page size + uint32_t cmp_size = n_cmp; // adjust last page size if ((off + n_cmp) > mf->len) { cmp_size = mf->len - off; @@ -50,7 +50,7 @@ int32_t check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { aligned_size = (cmp_size + 4) & ~(4 - 1); } - stlink_read_mem32(sl, addr + (uint32_t)off, (uint16_t)aligned_size); + stlink_read_mem32(sl, addr + off, (uint16_t)aligned_size); if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { return (-1); @@ -80,7 +80,7 @@ int32_t map_file(mapped_file_t *mf, const char *path) { // on 32 bit systems, check if there is an overflow if (st.st_size > (off_t)MAX_FILE_SIZE /*1 GB*/ ) { // limit file size to 1 GB - fprintf(stderr, "mmap() size_t overflow for file %s\n", path); + fprintf(stderr, "mmap() uint32_t overflow for file %s\n", path); goto on_error; } } diff --git a/src/stlink-lib/map_file.h b/src/stlink-lib/map_file.h index ba50e25e9..f25602d1e 100644 --- a/src/stlink-lib/map_file.h +++ b/src/stlink-lib/map_file.h @@ -20,7 +20,7 @@ /* Memory mapped file */ typedef struct mapped_file { uint8_t *base; - size_t len; + uint32_t len; } mapped_file_t; #define MAPPED_FILE_INITIALIZER \ diff --git a/src/stlink-lib/md5.c b/src/stlink-lib/md5.c index 9481acf0f..a5347de59 100644 --- a/src/stlink-lib/md5.c +++ b/src/stlink-lib/md5.c @@ -34,7 +34,7 @@ void stlink_checksum(mapped_file_t *mp) { uint32_t sum = 0; uint8_t *mp_byte = (uint8_t *)mp->base; - for (size_t i = 0; i < mp->len; ++i) { + for (uint32_t i = 0; i < mp->len; ++i) { sum += mp_byte[i]; } diff --git a/src/stlink-lib/option_bytes.h b/src/stlink-lib/option_bytes.h index ffeef8a0f..7ab3e2952 100644 --- a/src/stlink-lib/option_bytes.h +++ b/src/stlink-lib/option_bytes.h @@ -44,4 +44,4 @@ int32_t stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte); int32_t stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t* option_byte); int32_t stlink_write_option_bytes_boot_add32(stlink_t *sl, uint32_t option_bytes_boot_add); -#endif // OPTION_BYTES_H \ No newline at end of file +#endif // OPTION_BYTES_H diff --git a/src/stlink-lib/read_write.c b/src/stlink-lib/read_write.c index 6ee697d66..9149080af 100644 --- a/src/stlink-lib/read_write.c +++ b/src/stlink-lib/read_write.c @@ -36,7 +36,7 @@ int32_t stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { ret = sl->backend->read_debug32(sl, addr, data); if (!ret) - DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); + DLOG("*** stlink_read_debug32 %#010x at %#010x\n", *data, addr); return (ret); } diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index 0aa7a0d68..d7f844b51 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -103,7 +103,7 @@ #define STLINK_FALSE 0x81 static void clear_cdb(struct stlink_libsg *sl) { - for (size_t i = 0; i < sizeof(sl->cdb_cmd_blk); i++) { sl->cdb_cmd_blk[i] = 0; } + for (uint32_t i = 0; i < sizeof(sl->cdb_cmd_blk); i++) { sl->cdb_cmd_blk[i] = 0; } // set default sl->cdb_cmd_blk[0] = STLINK_DEBUG_COMMAND; diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index fc1dcbb4e..772fb147f 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -90,8 +90,8 @@ void _stlink_usb_close(stlink_t* sl) { } } -ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, size_t txsize, - unsigned char* rxbuf, size_t rxsize, int32_t check_error, const char *cmd) { +ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, uint32_t txsize, + unsigned char* rxbuf, uint32_t rxsize, int32_t check_error, const char *cmd) { // Note: txbuf and rxbuf can point to the same area int32_t res, t, retry = 0; @@ -168,7 +168,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char } static inline int32_t send_only(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, - size_t txsize, const char *cmd) { + uint32_t txsize, const char *cmd) { return((int32_t)send_recv(handle, terminate, txbuf, txsize, NULL, 0, CMD_CHECK_NO, cmd)); } @@ -1000,7 +1000,7 @@ int32_t _stlink_usb_disable_trace(stlink_t* sl) { return(size<0?-1:0); } -int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size) { +int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, uint32_t size) { struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; unsigned char* const cmd = sl->c_buf; @@ -1160,7 +1160,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, if (ret) { continue; } // could not open device - size_t serial_len = stlink_serial(handle, &desc, sl->serial); + uint32_t serial_len = stlink_serial(handle, &desc, sl->serial); libusb_close(handle); @@ -1300,12 +1300,12 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, return(NULL); } -static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int32_t freq) { +static uint32_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int32_t freq) { stlink_t **_sldevs; libusb_device *dev; int32_t i = 0; - size_t slcnt = 0; - size_t slcur = 0; + uint32_t slcnt = 0; + uint32_t slcur = 0; /* Count STLINKs */ while ((dev = devs[i++]) != NULL) { @@ -1363,7 +1363,7 @@ static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], e break; } - size_t serial_len = stlink_serial(handle, &desc, serial); + uint32_t serial_len = stlink_serial(handle, &desc, serial); libusb_close(handle); @@ -1388,7 +1388,7 @@ size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t libusb_device **devs; stlink_t **sldevs; - size_t slcnt = 0; + uint32_t slcnt = 0; int32_t r; ssize_t cnt; @@ -1410,10 +1410,10 @@ size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t return(slcnt); } -void stlink_probe_usb_free(stlink_t ***stdevs, size_t size) { +void stlink_probe_usb_free(stlink_t ***stdevs, uint32_t size) { if (stdevs == NULL || *stdevs == NULL || size == 0) { return; } - for (size_t n = 0; n < size; n++) { stlink_close((*stdevs)[n]); } + for (uint32_t n = 0; n < size; n++) { stlink_close((*stdevs)[n]); } free(*stdevs); *stdevs = NULL; diff --git a/src/stlink-lib/usb.h b/src/stlink-lib/usb.h index dd30cc529..2ec7490ad 100644 --- a/src/stlink-lib/usb.h +++ b/src/stlink-lib/usb.h @@ -62,10 +62,10 @@ struct stlink_libusb { // static inline uint32_t le_to_h_u32(const uint8_t* buf); // static int32_t _stlink_match_speed_map(const uint32_t *map, uint32_t map_size, uint32_t khz); void _stlink_usb_close(stlink_t* sl); -ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, size_t txsize, - unsigned char* rxbuf, size_t rxsize, int32_t check_error, const char *cmd); +ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, uint32_t txsize, + unsigned char* rxbuf, uint32_t rxsize, int32_t check_error, const char *cmd); // static inline int32_t send_only(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, -// size_t txsize, const char *cmd); +// uint32_t txsize, const char *cmd); // static int32_t fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint32_t len); int32_t _stlink_usb_version(stlink_t *sl); int32_t _stlink_usb_target_voltage(stlink_t *sl); @@ -96,14 +96,14 @@ int32_t _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_ int32_t _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int32_t idx); int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency); int32_t _stlink_usb_disable_trace(stlink_t* sl); -int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, size_t size); +int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, uint32_t size); // static stlink_backend_t _stlink_usb_backend = { }; size_t stlink_serial(struct libusb_device_handle *handle, struct libusb_device_descriptor *desc, char *serial); stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, char serial[STLINK_SERIAL_BUFFER_SIZE], int32_t freq); -// static size_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int32_t freq); +// static uint32_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int32_t freq); size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t freq); -void stlink_probe_usb_free(stlink_t **stdevs[], size_t size); +void stlink_probe_usb_free(stlink_t **stdevs[], uint32_t size); #endif // USB_H diff --git a/src/win32/getopt/getopt.c b/src/win32/getopt/getopt.c index 7bc8d2d20..417b0aecf 100644 --- a/src/win32/getopt/getopt.c +++ b/src/win32/getopt/getopt.c @@ -134,7 +134,7 @@ int32_t getopt_long(int32_t argc, const struct option* o = longopts; const struct option* match = NULL; int32_t num_matches = 0; - size_t argument_name_length = 0; + uint32_t argument_name_length = 0; const char* current_argument = NULL; int32_t retval = -1; diff --git a/src/win32/mmap.c b/src/win32/mmap.c index ea8a3cb37..7e76b3344 100644 --- a/src/win32/mmap.c +++ b/src/win32/mmap.c @@ -6,7 +6,7 @@ #include "mmap.h" -void *mmap (void *addr, size_t len, int32_t prot, int32_t flags, int32_t fd, int64_t offset) { +void *mmap (void *addr, uint32_t len, int32_t prot, int32_t flags, int32_t fd, int64_t offset) { void *buf; ssize_t count; @@ -32,7 +32,7 @@ void *mmap (void *addr, size_t len, int32_t prot, int32_t flags, int32_t fd, int (void)flags; } -int32_t munmap (void *addr, size_t len) { +int32_t munmap (void *addr, uint32_t len) { free (addr); return(0); (void)len; diff --git a/src/win32/mmap.h b/src/win32/mmap.h index e8bbab0bc..633816b50 100644 --- a/src/win32/mmap.h +++ b/src/win32/mmap.h @@ -15,8 +15,8 @@ #define MAP_ANONYMOUS (1 << 5) #define MAP_FAILED ((void *)-1) -void *mmap(void *addr, size_t len, int32_t prot, int32_t flags, int32_t fd, int64_t offset); -int32_t munmap(void *addr, size_t len); +void *mmap(void *addr, uint32_t len, int32_t prot, int32_t flags, int32_t fd, int64_t offset); +int32_t munmap(void *addr, uint32_t len); #endif // STLINK_HAVE_SYS_MMAN_H diff --git a/tests/flash.c b/tests/flash.c index a40be0c74..67436ecb1 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -26,7 +26,7 @@ static bool cmp_strings(const char * s1, const char * s2) { } } -static bool cmp_mem(const uint8_t * s1, const uint8_t * s2, size_t size) { +static bool cmp_mem(const uint8_t * s1, const uint8_t * s2, uint32_t size) { if (s1 == NULL || s2 == NULL) { return (s1 == s2); } else { @@ -231,7 +231,7 @@ static struct Test tests[] = { int32_t main() { bool allOk = true; - for (size_t i = 0; i < sizeof(tests) / sizeof(tests[0]); ++i) + for (uint32_t i = 0; i < sizeof(tests) / sizeof(tests[0]); ++i) if (!execute_test(&tests[i])) allOk = false; From 5d3f3ec7f492b76ce7f1ba4327eeeeeff13c5be8 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 10 Jun 2023 21:37:01 +0200 Subject: [PATCH 1385/1435] Set flash_type for STM32H5 devices --- config/chips/H5xx.chip | 2 +- config/chips/L5x5xx.chip | 2 +- config/chips/U5x5.chip | 2 +- inc/stm32.h | 2 +- src/stlink-lib/chipid.c | 4 +-- src/stlink-lib/common_flash.c | 52 ++++++++++++++++------------------- src/stlink-lib/flash_loader.c | 12 ++++---- 7 files changed, 36 insertions(+), 40 deletions(-) diff --git a/config/chips/H5xx.chip b/config/chips/H5xx.chip index a1c438999..8484fbc18 100644 --- a/config/chips/H5xx.chip +++ b/config/chips/H5xx.chip @@ -3,7 +3,7 @@ dev_type STM32H5xx ref_manual_id 0481 chip_id 0x484 // STM32_CHIPID_H5xx -flash_type L5_U5 // ? +flash_type L5_U5_H5 flash_size_reg 0x08fff80c flash_pagesize 0x2000 // 8 KB sram_size 0xa0000 // 640 KB diff --git a/config/chips/L5x5xx.chip b/config/chips/L5x5xx.chip index 0f205a62b..eace313d0 100644 --- a/config/chips/L5x5xx.chip +++ b/config/chips/L5x5xx.chip @@ -3,7 +3,7 @@ dev_type STM32L5x2xx ref_manual_id 0438 chip_id 0x472 // STM32_CHIPID_L5x2xx -flash_type L5_U5 +flash_type L5_U5_H5 flash_size_reg 0x0bfa05e0 flash_pagesize 0x1000 // 4 KB sram_size 0x40000 // 256 KB diff --git a/config/chips/U5x5.chip b/config/chips/U5x5.chip index 5f71436ef..82964b1c3 100644 --- a/config/chips/U5x5.chip +++ b/config/chips/U5x5.chip @@ -3,7 +3,7 @@ dev_type STM32U5x5 ref_manual_id 0456 chip_id 0x482 // STM32_CHIPID_U5x5 -flash_type L5_U5 +flash_type L5_U5_H5 flash_size_reg 0x0bfa07a0 flash_pagesize 0x2000 // 8 KB sram_size 0xc4800 // 786 KB diff --git a/inc/stm32.h b/inc/stm32.h index eee1b0433..cf9a8a2ad 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -60,7 +60,7 @@ enum stm32_flash_type { STM32_FLASH_TYPE_H7 = 7, STM32_FLASH_TYPE_L0_L1 = 8, STM32_FLASH_TYPE_L4 = 9, - STM32_FLASH_TYPE_L5_U5 = 10, + STM32_FLASH_TYPE_L5_U5_H5 = 10, STM32_FLASH_TYPE_WB_WL = 11, }; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 0392f15ff..06edb26f3 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -115,8 +115,8 @@ void process_chipfile(char *fname) { ts->flash_type = STM32_FLASH_TYPE_L0_L1; } else if (strcmp(value, "L4") == 0) { ts->flash_type = STM32_FLASH_TYPE_L4; - } else if (strcmp(value, "L5_U5") == 0) { - ts->flash_type = STM32_FLASH_TYPE_L5_U5; + } else if (strcmp(value, "L5_U5_H5") == 0) { + ts->flash_type = STM32_FLASH_TYPE_L5_U5_H5; } else if (strcmp(value, "WB_WL") == 0) { ts->flash_type = STM32_FLASH_TYPE_WB_WL; } else { diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 70c8a2216..f2281ac11 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -56,7 +56,7 @@ uint32_t read_flash_cr(stlink_t *sl, uint32_t bank) { reg = (bank == BANK_1) ? FLASH_H7_CR1 : FLASH_H7_CR2; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { reg = FLASH_L4_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { reg = FLASH_WB_CR; @@ -101,7 +101,7 @@ void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = FLASH_L4_CR; cr_lock_shift = FLASH_L4_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; cr_lock_shift = FLASH_L5_NSCR_NSLOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { @@ -147,7 +147,7 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { sr_reg = FLASH_L4_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { sr_reg = FLASH_L5_NSSR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_reg = FLASH_WB_SR; @@ -190,7 +190,7 @@ void clear_flash_error(stlink_t *sl) { case STM32_FLASH_TYPE_L4: write_flash_sr(sl, BANK_1, FLASH_L4_SR_ERROR_MASK); break; - case STM32_FLASH_TYPE_L5_U5: + case STM32_FLASH_TYPE_L5_U5_H5: write_flash_sr(sl, BANK_1, FLASH_L5_NSSR_ERROR_MASK); break; case STM32_FLASH_TYPE_WB_WL: @@ -220,7 +220,7 @@ uint32_t read_flash_sr(stlink_t *sl, uint32_t bank) { sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { sr_reg = FLASH_L4_SR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { sr_reg = FLASH_L5_NSSR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_reg = FLASH_WB_SR; @@ -252,7 +252,7 @@ uint32_t is_flash_busy(stlink_t *sl) { sr_busy_shift = FLASH_H7_SR_QW; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { sr_busy_shift = FLASH_L4_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { sr_busy_shift = FLASH_L5_NSSR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { sr_busy_shift = FLASH_WB_SR_BSY; @@ -335,7 +335,7 @@ int32_t check_flash_error(stlink_t *sl) { PROGERR = (1 << FLASH_L4_SR_PROGERR); PGAERR = (1 << FLASH_L4_SR_PGAERR); break; - case STM32_FLASH_TYPE_L5_U5: + case STM32_FLASH_TYPE_L5_U5_H5: res = read_flash_sr(sl, BANK_1) & FLASH_L5_NSSR_ERROR_MASK; WRPERR = (1 << FLASH_L5_NSSR_NSWRPERR); PROGERR = (1 << FLASH_L5_NSSR_NSPROGERR); @@ -401,7 +401,7 @@ static inline uint32_t is_flash_locked(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = FLASH_L4_CR; cr_lock_shift = FLASH_L4_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; cr_lock_shift = FLASH_L5_NSCR_NSLOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { @@ -448,7 +448,7 @@ static void unlock_flash(stlink_t *sl) { flash_key2 = FLASH_L0_PEKEY2; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { key_reg = FLASH_L4_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { // Set voltage scaling to range 0 to perform flash operations (RM0438 p. 183) uint32_t mask = (0b11 << STM32L5_PWR_CR1_VOS); uint32_t val; @@ -526,7 +526,7 @@ int32_t lock_flash_option(stlink_t *sl) { optcr_reg = FLASH_L4_CR; optlock_shift = FLASH_L4_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_L5_U5: + case STM32_FLASH_TYPE_L5_U5_H5: optcr_reg = FLASH_L5_NSCR; optlock_shift = FLASH_L5_NSCR_OPTLOCK; break; @@ -601,7 +601,7 @@ static bool is_flash_option_locked(stlink_t *sl) { optcr_reg = FLASH_L4_CR; optlock_shift = FLASH_L4_CR_OPTLOCK; break; - case STM32_FLASH_TYPE_L5_U5: + case STM32_FLASH_TYPE_L5_U5_H5: optcr_reg = FLASH_L5_NSCR; optlock_shift = FLASH_L5_NSCR_OPTLOCK; break; @@ -658,7 +658,7 @@ static int32_t unlock_flash_option(stlink_t *sl) { case STM32_FLASH_TYPE_L4: optkey_reg = FLASH_L4_OPTKEYR; break; - case STM32_FLASH_TYPE_L5_U5: + case STM32_FLASH_TYPE_L5_U5_H5: optkey_reg = FLASH_L5_OPTKEYR; break; case STM32_FLASH_TYPE_WB_WL: @@ -734,7 +734,7 @@ void clear_flash_cr_pg(stlink_t *sl, uint32_t bank) { bit = FLASH_H7_CR_PG; } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = FLASH_L4_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = FLASH_WB_CR; @@ -801,7 +801,7 @@ static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = FLASH_Gx_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = FLASH_WB_CR; @@ -820,7 +820,7 @@ static void clear_flash_cr_per(stlink_t *sl, uint32_t bank) { if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = FLASH_Gx_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = FLASH_WB_CR; @@ -867,7 +867,7 @@ static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = FLASH_L4_CR; cr_strt = (1 << FLASH_L4_CR_STRT); - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; cr_strt = (1 << FLASH_L5_NSCR_NSSTRT); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { @@ -910,7 +910,7 @@ static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank) { cr_reg = FLASH_L4_CR; cr_mer = (1 << FLASH_L4_CR_MER1) | (1 << FLASH_L4_CR_MER2); cr_pg = (1 << FLASH_L4_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; cr_mer = (1 << FLASH_L5_NSCR_NSMER1) | (1 << FLASH_L5_NSCR_NSMER2); cr_pg = (1 << FLASH_L5_NSCR_NSPG); @@ -1059,7 +1059,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || sl->flash_type == STM32_FLASH_TYPE_WB_WL) { uint32_t val; unlock_flash_if(sl); @@ -1080,7 +1080,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val &= ~(0x7F << 3); val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_Gx_CR, val); - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { uint32_t flash_page; stlink_read_debug32(sl, FLASH_L5_NSCR, &val); if (sl->flash_pgsz == 0x800 && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) { @@ -1182,7 +1182,7 @@ int32_t stlink_erase_flash_mass(stlink_t *sl) { // TODO: User MER bit to mass-erase WB series. if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || - sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sl->flash_type == STM32_FLASH_TYPE_WB_WL) { err = stlink_erase_flash_section(sl, sl->flash_base, sl->flash_size, false); @@ -1191,8 +1191,7 @@ int32_t stlink_erase_flash_mass(stlink_t *sl) { clear_flash_error(sl); unlock_flash_if(sl); - if (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_id != STM32_CHIPID_H7Ax) { + if (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { @@ -1205,8 +1204,7 @@ int32_t stlink_erase_flash_mass(stlink_t *sl) { sl, BANK_1); // start erase operation, reset by hw with busy bit if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || - (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 } @@ -1217,8 +1215,7 @@ int32_t stlink_erase_flash_mass(stlink_t *sl) { // reset the mass erase bit set_flash_cr_mer(sl, 0, BANK_1); if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || - (sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { + (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { set_flash_cr_mer(sl, 0, BANK_2); } @@ -1316,8 +1313,7 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { * still flash the whole file even if ignoring message is printed. */ err = stlink_write_flash(sl, addr, mf.base, - (num_empty == mf.len) ? (uint32_t)mf.len - : (uint32_t)mf.len - num_empty, + (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty, num_empty == mf.len); stlink_fwrite_finalize(sl, addr); unmap_file(&mf); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index a862bd0e7..0ab8cf6c1 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -501,7 +501,7 @@ static void set_flash_cr_pg(stlink_t *sl, uint32_t bank) { cr_reg = FLASH_L4_CR; x &= ~FLASH_L4_CR_OPBITS; x |= (1 << FLASH_L4_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || @@ -556,7 +556,7 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr) { rcc_dma_mask = STM32L0_RCC_DMAEN; } break; - case STM32_FLASH_TYPE_L5_U5: + case STM32_FLASH_TYPE_L5_U5_H5: rcc = STM32L5_RCC_AHB1ENR; rcc_dma_mask = STM32L5_RCC_DMAEN; break; @@ -639,8 +639,8 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5) { - ILOG("Starting Flash write for WB/G0/G4/L5/U5\n"); + sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { + ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5\n"); unlock_flash_if(sl); // unlock flash if necessary set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit @@ -737,7 +737,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5) { + sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { DLOG("Starting %3u page write\n", len / sl->flash_pgsz); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; @@ -864,7 +864,7 @@ int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { (sl->flash_type == STM32_FLASH_TYPE_G4) || (sl->flash_type == STM32_FLASH_TYPE_H7) || (sl->flash_type == STM32_FLASH_TYPE_L4) || - (sl->flash_type == STM32_FLASH_TYPE_L5_U5) || + (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) || (sl->flash_type == STM32_FLASH_TYPE_WB_WL)) { clear_flash_cr_pg(sl, BANK_1); From 2c337615c945f79fa882ca6714279125e2619d11 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 11 Jun 2023 14:29:23 +0200 Subject: [PATCH 1386/1435] [refactoring] Clean-up for stlink-flash & -info - Ensure proper function declaration - Checked & revised header includes --- CMakeLists.txt | 3 +++ inc/stlink.h | 9 ++------- src/st-flash/flash.c | 20 ++++++++++++++----- src/st-flash/flash.h | 36 +++++++++------------------------ src/st-flash/flash_opts.c | 15 +++++++++++--- src/st-flash/flash_opts.h | 40 +++++++++++++++++++++++++++++++++++++ src/st-info/info.c | 14 ++++++++++--- src/st-info/info.h | 18 +++++++++++++++++ src/st-trace/trace.c | 5 ++++- src/st-util/gdb-server.c | 14 ++++++++----- src/stlink-gui/gui.c | 5 ++++- src/stlink-lib/chipid.h | 2 +- src/stlink-lib/usb.c | 42 +++++++++++++++++++-------------------- tests/flash.c | 1 + tests/sg.c | 3 +++ tests/usb.c | 3 +++ 16 files changed, 155 insertions(+), 75 deletions(-) create mode 100644 src/st-flash/flash_opts.h create mode 100644 src/st-info/info.h diff --git a/CMakeLists.txt b/CMakeLists.txt index 2a82ea983..511144eae 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -154,6 +154,9 @@ include_directories(${PROJECT_BINARY_DIR}/inc) # contains version.h include_directories(src) include_directories(src/st-flash) +include_directories(src/st-info) +include_directories(src/st-trace) +include_directories(src/st-util) include_directories(src/stlink-lib) ## Set installation directory for header files diff --git a/inc/stlink.h b/inc/stlink.h index d5d036725..ed93b34b7 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -234,6 +234,8 @@ struct _stlink { uint32_t max_trace_freq; // set by stlink_open_usb() }; +/* Functions defined in common.c */ + int32_t stlink_enter_swd_mode(stlink_t *sl); int32_t stlink_enter_jtag_mode(stlink_t *sl); int32_t stlink_exit_debug_mode(stlink_t *sl); @@ -284,14 +286,7 @@ int32_t stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t int32_t stlink_load_device_params(stlink_t *sl); int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect); -#include -#include -#include -#include -#include #include -#include -#include #ifdef __cplusplus } diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 9a648bd63..711d7d2eb 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -1,23 +1,33 @@ -/* Simple wrapper around the stlink_flash_write function */ +/* + * File: flash.c + * + * Tool st-flash - Simple wrapper around the stlink_flash_write function + */ -#include #include +#include #include #include #include #include -#include + +#if defined(_WIN32) +#include +#else #include +#endif // _WIN32 #include #include +#include "flash.h" +#include "flash_opts.h" +#include #include #include #include - -#include "flash.h" +#include static stlink_t *connected_stlink = NULL; diff --git a/src/st-flash/flash.h b/src/st-flash/flash.h index 84c171158..889b2e4c4 100644 --- a/src/st-flash/flash.h +++ b/src/st-flash/flash.h @@ -1,36 +1,18 @@ +/* + * File: flash.h + * + * Tool st-flash + */ + #ifndef FLASH_H #define FLASH_H -#include - -#include - #define DEBUG_LOG_LEVEL 100 #define STND_LOG_LEVEL 50 #define ENABLE_OPT 1 -enum flash_cmd {FLASH_CMD_NONE = 0, FLASH_CMD_WRITE = 1, FLASH_CMD_READ = 2, FLASH_CMD_ERASE = 3, CMD_RESET = 4}; -enum flash_format {FLASH_FORMAT_BINARY = 0, FLASH_FORMAT_IHEX = 1}; -enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1, FLASH_OTP = 2, FLASH_OPTION_BYTES = 3, FLASH_OPTION_BYTES_BOOT_ADD = 4, FLASH_OPTCR = 5, FLASH_OPTCR1 = 6}; -struct flash_opts { - enum flash_cmd cmd; - uint8_t serial[STLINK_SERIAL_BUFFER_SIZE]; - const char* filename; - stm32_addr_t addr; - uint32_t size; - int32_t reset; - int32_t log_level; - enum flash_format format; - enum flash_area area; - uint32_t val; - uint32_t flash_size; // --flash=n[k, M] - int32_t opt; // enable empty tail data drop optimization - int32_t freq; // --freq=n[k, M] frequency of JTAG/SWD - enum connect_type connect; -}; - -#define FLASH_OPTS_INITIALIZER {0, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} - -int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av); +// static stlink_t *connected_stlink = NULL; +// static void cleanup(int32_t signum); +// static void usage(void); #endif // FLASH_H diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 35763ad50..358074793 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -1,12 +1,21 @@ +/* + * File: flash_opts.c + * + * Flash Options + */ + #include -#include #include +#include #include -#include - +#include +#include +#include "flash_opts.h" #include "flash.h" +#include + static bool starts_with(const char * str, const char * prefix) { uint32_t n = strlen(prefix); diff --git a/src/st-flash/flash_opts.h b/src/st-flash/flash_opts.h new file mode 100644 index 000000000..0c0083db6 --- /dev/null +++ b/src/st-flash/flash_opts.h @@ -0,0 +1,40 @@ +/* + * File: flash_opts.h + * + * Flash Options + */ + +#ifndef FLASH_OPTS_H +#define FLASH_OPTS_H + +#define FLASH_OPTS_INITIALIZER {0, { 0 }, NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} + +enum flash_cmd {FLASH_CMD_NONE = 0, FLASH_CMD_WRITE = 1, FLASH_CMD_READ = 2, FLASH_CMD_ERASE = 3, CMD_RESET = 4}; +enum flash_format {FLASH_FORMAT_BINARY = 0, FLASH_FORMAT_IHEX = 1}; +enum flash_area {FLASH_MAIN_MEMORY = 0, FLASH_SYSTEM_MEMORY = 1, FLASH_OTP = 2, FLASH_OPTION_BYTES = 3, FLASH_OPTION_BYTES_BOOT_ADD = 4, FLASH_OPTCR = 5, FLASH_OPTCR1 = 6}; + +struct flash_opts { + enum flash_cmd cmd; + uint8_t serial[STLINK_SERIAL_BUFFER_SIZE]; + const char* filename; + stm32_addr_t addr; + uint32_t size; + int32_t reset; + int32_t log_level; + enum flash_format format; + enum flash_area area; + uint32_t val; + uint32_t flash_size; // --flash=n[k, M] + int32_t opt; // enable empty tail data drop optimization + int32_t freq; // --freq=n[k, M] frequency of JTAG/SWD + enum connect_type connect; +}; + +// static bool starts_with(const char * str, const char * prefix); +// static int32_t get_long_integer_from_char_array (const char *const str, uint64_t *read_value); +// static int32_t get_integer_from_char_array (const char *const str, uint32_t *read_value); +// static int32_t invalid_args(const char *expected); +// static int32_t bad_arg(const char *arg); +int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av); + +#endif // FLASH_OPTS_H diff --git a/src/st-info/info.c b/src/st-info/info.c index b6ec0ccd2..664db7b2a 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -1,11 +1,19 @@ -#include +/* + * File: stinfo.c + * + * Tool st-info + */ + #include -#include +#include #include -#include #include +#include "info.h" + +#include #include +#include static void usage(void) { puts("st-info --version"); diff --git a/src/st-info/info.h b/src/st-info/info.h new file mode 100644 index 000000000..8e978e678 --- /dev/null +++ b/src/st-info/info.h @@ -0,0 +1,18 @@ +/* + * File: info.h + * + * Tool st-info + */ + +#ifndef INFO_H +#define INFO_H + +// static void usage(void); +// static void stlink_print_version(stlink_t *sl); +// static void stlink_print_info(stlink_t *sl); + +// static void stlink_probe(enum connect_type connect, int32_t freq) { }; +static int32_t print_data(int32_t ac, char **av); +int32_t main(int32_t ac, char** av); + +#endif // INFO_H \ No newline at end of file diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index ccbd74e16..56170d7c0 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -10,9 +10,12 @@ #include #include +#include + +#include #include #include -#include +#include #define DEFAULT_LOGGING_LEVEL 50 #define DEBUG_LOGGING_LEVEL 100 diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 7232f0f69..9f9d93844 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -27,14 +27,18 @@ #endif #include -#include -#include -#include -#include -#include "gdb-remote.h" #include "gdb-server.h" +#include "gdb-remote.h" #include "semihosting.h" +#include +#include +#include +#include +#include +#include +#include + #define FLASH_BASE 0x08000000 // Semihosting doesn't have a short option, we define a value to identify it diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index af2afcdbf..5853e5ec4 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -5,9 +5,12 @@ #include #include -#include #include "gui.h" +#include +#include +#include + #define MEM_READ_SIZE 1024 #ifndef G_VALUE_INIT diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index a72a40be9..6726a7420 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -21,7 +21,7 @@ struct stlink_chipid_params { uint32_t option_base; uint32_t option_size; uint32_t flags; - struct stlink_chipid_params * next; + struct stlink_chipid_params *next; }; struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chipid); diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 772fb147f..c2425b6cd 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -103,8 +103,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char ELOG("%s send request failed: %s\n", cmd, libusb_error_name(t)); return(-1); } else if ((size_t)res != txsize) { - ELOG("%s send request wrote %u bytes, instead of %u\n", - cmd, (uint32_t)res, (uint32_t)txsize); + ELOG("%s send request wrote %u bytes, instead of %u\n", cmd, (uint32_t)res, (uint32_t)txsize); } if (rxsize != 0) { @@ -215,7 +214,7 @@ int32_t _stlink_usb_version(stlink_t *sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_REP_LEN, "GET_VERSION"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_target_voltage(stlink_t *sl) { @@ -279,7 +278,7 @@ int32_t _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { write_uint32(&cmd[i + 4], data); size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "WRITEDEBUGREG"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_get_rw_status(stlink_t *sl) { @@ -302,7 +301,7 @@ int32_t _stlink_usb_get_rw_status(stlink_t *sl) { ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2, CMD_CHECK_STATUS, "GETLASTRWSTATUS"); } - return(ret<0?-1:0); + return(ret < 0 ? -1 : 0); } int32_t _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -450,7 +449,7 @@ int32_t _stlink_usb_status(stlink_t * sl) { sl->core_stat = TARGET_UNKNOWN; } - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_force_debug(stlink_t *sl) { @@ -473,7 +472,7 @@ int32_t _stlink_usb_force_debug(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_FORCEDEBUG; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "FORCEDEBUG"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_enter_swd_mode(stlink_t * sl) { @@ -490,7 +489,7 @@ int32_t _stlink_usb_enter_swd_mode(stlink_t * sl) { cmd[i++] = STLINK_DEBUG_ENTER_SWD; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "ENTER_SWD"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_exit_dfu_mode(stlink_t* sl) { @@ -503,7 +502,7 @@ int32_t _stlink_usb_exit_dfu_mode(stlink_t* sl) { cmd[i++] = STLINK_DFU_EXIT; size = send_only(slu, 1, cmd, slu->cmd_len, "DFU_EXIT"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } @@ -526,7 +525,7 @@ int32_t _stlink_usb_reset(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RESETSYS"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_jtag_reset(stlink_t * sl, int32_t value) { @@ -542,7 +541,7 @@ int32_t _stlink_usb_jtag_reset(stlink_t * sl, int32_t value) { cmd[i++] = value; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "DRIVE_NRST"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } @@ -556,7 +555,7 @@ int32_t _stlink_usb_step(stlink_t* sl) { _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_STEP | STLINK_REG_DHCSR_C_MASKINTS | STLINK_REG_DHCSR_C_DEBUGEN); return _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | - STLINK_REG_DHCSR_C_DEBUGEN); + STLINK_REG_DHCSR_C_DEBUGEN); } unsigned char* const data = sl->q_buf; @@ -569,7 +568,7 @@ int32_t _stlink_usb_step(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_STEPCORE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "STEPCORE"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } /** @@ -583,8 +582,7 @@ int32_t _stlink_usb_run(stlink_t* sl, enum run_type type) { int32_t res; if (sl->version.jtag_api != STLINK_JTAG_API_V1) { - res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | ((type==RUN_FLASH_LOADER)?STLINK_REG_DHCSR_C_MASKINTS:0)); return(res); } @@ -600,7 +598,7 @@ int32_t _stlink_usb_run(stlink_t* sl, enum run_type type) { cmd[i++] = STLINK_DEBUG_RUNCORE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RUNCORE"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { @@ -643,7 +641,7 @@ int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { cmd[i++] = (clk_divisor >> 8) & 0xFF; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "SWD_SET_FREQ"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } else if (sl->version.stlink_v == 3) { int32_t speed_index; uint32_t map[STLINK_V3_MAX_FREQ_NB]; @@ -684,7 +682,7 @@ int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8, CMD_CHECK_STATUS, "SET_COM_FREQ"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } else if (clk_freq) { WLOG("ST-Link firmware does not support frequency setup\n"); } @@ -703,7 +701,7 @@ int32_t _stlink_usb_exit_debug_mode(stlink_t *sl) { size = send_only(slu, 1, cmd, slu->cmd_len, "DEBUG_EXIT"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -963,7 +961,7 @@ int32_t _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { write_uint32(&cmd[i], reg); size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "WRITEREG"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { @@ -981,7 +979,7 @@ int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "START_TRACE_RX"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_disable_trace(stlink_t* sl) { @@ -997,7 +995,7 @@ int32_t _stlink_usb_disable_trace(stlink_t* sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "STOP_TRACE_RX"); - return(size<0?-1:0); + return(size < 0 ? -1 : 0); } int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, uint32_t size) { diff --git a/tests/flash.c b/tests/flash.c index 67436ecb1..f4c838d5d 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -7,6 +7,7 @@ #include #include +#include #if defined(_MSC_VER) #include diff --git a/tests/sg.c b/tests/sg.c index 32dcd9a62..6881266ab 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -7,6 +7,9 @@ #include +#include +#include + #if defined(_MSC_VER) #define __attribute__(x) #endif diff --git a/tests/usb.c b/tests/usb.c index 56f0d9c1f..9acd0b02d 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -6,6 +6,9 @@ #include +#include +#include + static void usage(void) { puts("test-usb --reset"); puts("test-usb --no-reset"); From b72f5b5acf8997a299d9eac4d6cc2dfc5322e144 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 12 Jun 2023 11:56:21 +0200 Subject: [PATCH 1387/1435] Fixed compilation on Windows - [doc] Updated installation instructions - Fixed cmd bug in mingw64-build.bat - Fixed cmake building for WIN32 --- CMakeLists.txt | 19 ++++++++++++++++++- doc/compiling.md | 16 +++++++++------- mingw64-build.bat | 5 +++-- 3 files changed, 30 insertions(+), 10 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 511144eae..7e7d92705 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -74,7 +74,7 @@ include(${CMAKE_MODULE_PATH}/get_version.cmake) # Determine project version include(GNUInstallDirs) # Define GNU standard installation directories -# Define install directory /usr/local/share +# Define install directory for st-link shared files cmake_host_system_information(RESULT OS_NAME QUERY OS_NAME) message(STATUS "Checking for OS_NAME: ${OS_NAME}") @@ -160,7 +160,11 @@ include_directories(src/st-util) include_directories(src/stlink-lib) ## Set installation directory for header files +if (WIN32) +set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR} CACHE PATH "Main include install directory") +else () set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} CACHE PATH "Main include install directory") +endif () ## Subordinate CMakeLists for version config & header installation add_subdirectory(inc) @@ -275,6 +279,15 @@ install(TARGETS ${STLINK_LIB_SHARED} RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR} ) +# Copy libusb DLL-library to binary output folder +if (WIN32) +file(COPY ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/dll/libusb-1.0.dll + DESTINATION ${CMAKE_INSTALL_BINDIR}) +file(COPY ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/dll/libusb-1.0.dll + DESTINATION ${CMAKE_INSTALL_PREFIX}/${CMAKE_INSTALL_BINDIR}) +endif () + + ### # Static library ### @@ -369,7 +382,11 @@ endif () ### # MCU configuration files +if (WIN32) +set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_PREFIX}/config/chips) +else () set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}/chips) +endif () add_definitions( -DSTLINK_CHIPS_DIR="${CMAKE_CHIPS_DIR}" ) file(GLOB CHIP_FILES ${CMAKE_SOURCE_DIR}/config/chips/*.chip) install(FILES ${CHIP_FILES} DESTINATION ${CMAKE_CHIPS_DIR}) diff --git a/doc/compiling.md b/doc/compiling.md index eec46bb3d..775d2363e 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -8,7 +8,8 @@ On Windows users should ensure that the following software is installed: - `git` (_optional, but recommended_) - `cmake` -- `MinGW-w64` (7.0.0 or later) with GCC toolchain 8.1.0 +- `7-zip` +- `MinGW-w64` ### Installation @@ -17,13 +18,13 @@ On Windows users should ensure that the following software is installed: Ensure that you add cmake to the $PATH system variable when following the instructions by the setup assistant. 3. Install -- _EITHER_: **MinGW-w64** from (mingw-w64-install.exe)
      -- _OR_: **MSVC toolchain** from Visual Studio Build Tools 2019 + - _EITHER_: Download **MinGW-w64** from . Extract content to `C:\mingw-w64\` and add `C:\mingw-w64\bin\` to PATH-Variable.
      + - _OR_: **MSVC toolchain** from Visual Studio Build Tools 2019 4. Create a new destination folder at a place of your choice 5. Open the command-line (cmd.exe) and execute `cd C:\$Path-to-your-destination-folder$\` 6. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git`from the command-line (cmd.exe)
      - or download the stlink zip-sourcefolder from the Release page on GitHub + or download and extract the stlink zip-sourcefolder from the Release page on GitHub. #### MSVC toolchain - minimal installation @@ -48,11 +49,12 @@ Visual Studio IDE is not necessary, only Windows SDK & build tools are required #### MinGW-w64 -1. Use the command-line to move to the `scripts` directory within the source-folder: `cd stlink\scripts\` -2. Execute `./mingw64-build.bat` +1. Open command-line with administrator privileges +2. Move to the `stlink` directory +3. Execute `mingw64-build.bat` NOTE:
      -Per default the build script (currently) uses `C:\Program Files\mingw-w64\x86_64-8.1.0-release-win32-sjlj-rt_v6-rev0\mingw64\bin`.
      +Per default the build script (currently) uses `C:\mingw-w64\x86_64-8.1.0-release-win32-sjlj-rt_v6-rev0\mingw64\bin`.
      When installing different toolchains make sure to update the path in the `mingw64-build.bat`.
      This can be achieved by opening the .bat file with a common text editor. diff --git a/mingw64-build.bat b/mingw64-build.bat index eeaacddab..b52e529e2 100644 --- a/mingw64-build.bat +++ b/mingw64-build.bat @@ -2,8 +2,9 @@ mkdir build-mingw cd build-mingw -set PATH=C:\Program Files (x86)\CMake\bin;C:\Program Files\CMake\bin;C:\Program Files\mingw-w64\x86_64-8.1.0-win32-sjlj-rt_v6-rev0\mingw64\bin;%PATH% +set PATH=C:\Program Files (x86)\CMake\bin;C:\Program Files\CMake\bin;C:\mingw-w64\x86_64-8.1.0-win32-sjlj-rt_v6-rev0\mingw64\bin;%PATH% cmake -G "MinGW Makefiles" .. mingw32-make -mingw32-make install DESTDIR=install +mingw32-make install mingw32-make package +cd .. From 101d77bf7e6c32c9e9b565301bd6dd9092c033cc Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 24 Jun 2023 23:55:12 +0200 Subject: [PATCH 1388/1435] Formatting & style fixes. --- CMakeLists.txt | 36 +++---- cmake/modules/Findlibusb.cmake | 18 ++-- cmake/modules/c_flags.cmake | 8 +- cmake/modules/get_version.cmake | 16 +-- cmake/modules/pandocology.cmake | 38 ++++---- cmake/packaging/cpack_config.cmake | 2 +- doc/man/CMakeLists.txt | 6 +- src/st-flash/flash.c | 6 +- src/st-flash/flash_opts.c | 56 +++++------ src/st-info/info.c | 16 +-- src/st-util/gdb-remote.c | 24 ++--- src/st-util/gdb-server.c | 66 ++++++------- src/st-util/semihosting.c | 80 +++++++-------- src/stlink-gui/CMakeLists.txt | 4 +- src/stlink-gui/gui.c | 38 ++++---- src/stlink-lib/flash_loader.c | 30 +++--- src/stlink-lib/lib_md5.c | 2 +- src/stlink-lib/sg.c | 144 +++++++++++++-------------- src/stlink-lib/usb.c | 150 ++++++++++++++--------------- src/win32/getopt/getopt.c | 10 +- src/win32/mmap.c | 12 +-- src/win32/sys_time.c | 4 +- src/win32/win32_socket.c | 28 +++--- tests/flash.c | 4 +- tests/sg.c | 4 +- tests/usb.c | 4 +- 26 files changed, 402 insertions(+), 404 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 7e7d92705..c0957a034 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -91,7 +91,7 @@ else () set(CMAKE_C_FLAGS_MINSIZEREL_INIT "/MT /O1 /Ob1 /D NDEBUG") set(CMAKE_C_FLAGS_RELEASE_INIT "/MT /O2 /Ob2 /D NDEBUG") set(CMAKE_C_FLAGS_RELWITHDEBINFO_INIT "/MT /Zi /O2 /Ob1 /D NDEBUG") -endif () +endif() ### @@ -111,10 +111,10 @@ if (_stack_chk_fail_exists) set(SSP_LIB -static ssp) else () set(SSP_LIB ssp) - endif () + endif() else () set(SSP_LIB "") -endif () +endif() CHECK_INCLUDE_FILE(sys/mman.h STLINK_HAVE_SYS_MMAN_H) if (STLINK_HAVE_SYS_MMAN_H) @@ -129,17 +129,17 @@ endif() CHECK_INCLUDE_FILE(unistd.h STLINK_HAVE_UNISTD_H) if (STLINK_HAVE_UNISTD_H) add_definitions(-DSTLINK_HAVE_UNISTD_H) -endif () +endif() CHECK_INCLUDE_FILE(dirent.h STLINK_HAVE_DIRENT_H) if (STLINK_HAVE_DIRENT_H) add_definitions(-DSTLINK_HAVE_DIRENT_H) -endif () +endif() if (MSVC) # Use string.h rather than strings.h and disable annoying warnings add_definitions(-DHAVE_STRING_H -D_CRT_SECURE_NO_WARNINGS -D_CRT_NONSTDC_NO_WARNINGS /wd4710) -endif () +endif() ### @@ -164,7 +164,7 @@ if (WIN32) set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR} CACHE PATH "Main include install directory") else () set(STLINK_INCLUDE_PATH ${CMAKE_INSTALL_INCLUDEDIR}/${PROJECT_NAME} CACHE PATH "Main include install directory") -endif () +endif() ## Subordinate CMakeLists for version config & header installation add_subdirectory(inc) @@ -218,7 +218,7 @@ if (WIN32) # Add drop-in replacement for unistd.h to sources include_directories(src/win32/unistd) set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/unistd/unistd.h") - endif () + endif() if (NOT STLINK_HAVE_SYS_MMAN_H) include_directories(src/win32/mmap) @@ -230,12 +230,12 @@ if (WIN32) set(STLINK_SOURCE "${STLINK_SOURCE};src/win32/sys_time.c") set(STLINK_HEADERS "${STLINK_HEADERS};src/win32/sys_time.h") endif() -endif () +endif() ## Include test execution for test-targets for target Debug if (${CMAKE_BUILD_TYPE} MATCHES "Debug") include(CTest) -endif () +endif() ### @@ -271,7 +271,7 @@ if (WIN32) # ... with Windows libraries target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB} wsock32 ws2_32) else () target_link_libraries(${STLINK_LIB_SHARED} ${LIBUSB_LIBRARY} ${SSP_LIB}) -endif () +endif() install(TARGETS ${STLINK_LIB_SHARED} ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} @@ -285,7 +285,7 @@ file(COPY ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/dll/libusb-1.0.dll DESTINATION ${CMAKE_INSTALL_BINDIR}) file(COPY ${LIBUSB_WIN_OUTPUT_FOLDER}/MinGW64/dll/libusb-1.0.dll DESTINATION ${CMAKE_INSTALL_PREFIX}/${CMAKE_INSTALL_BINDIR}) -endif () +endif() ### @@ -317,7 +317,7 @@ if (WIN32) # ... with Windows libraries target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB} wsock32 ws2_32) else () target_link_libraries(${STLINK_LIB_STATIC} ${LIBUSB_LIBRARY} ${SSP_LIB}) -endif () +endif() install(TARGETS ${STLINK_LIB_STATIC} ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR}) @@ -336,7 +336,7 @@ if (MSVC) include_directories(src/win32/getopt) set(ST-UTIL_SOURCES "${ST-UTIL_SOURCES};src/win32/getopt/getopt.c") set(ST-TRACE_SOURCES "${ST-TRACE_SOURCES};src/win32/getopt/getopt.c") -endif () +endif() add_executable(st-flash ${ST-FLASH_SOURCES}) add_executable(st-info ${ST-INFO_SOURCES}) @@ -353,7 +353,7 @@ else () target_link_libraries(st-info ${STLINK_LIB_SHARED} ${SSP_LIB}) target_link_libraries(st-util ${STLINK_LIB_SHARED} ${SSP_LIB}) target_link_libraries(st-trace ${STLINK_LIB_SHARED} ${SSP_LIB}) -endif () +endif() install(TARGETS st-flash DESTINATION ${CMAKE_INSTALL_BINDIR}) install(TARGETS st-info DESTINATION ${CMAKE_INSTALL_BINDIR}) @@ -374,7 +374,7 @@ if (CMAKE_SYSTEM_NAME STREQUAL "Linux") set(STLINK_UDEV_RULES_DIR "/lib/udev/rules.d" CACHE PATH "udev rules directory") file(GLOB RULES_FILES ${CMAKE_SOURCE_DIR}/config/udev/rules.d/*.rules) install(FILES ${RULES_FILES} DESTINATION ${STLINK_UDEV_RULES_DIR}) -endif () +endif() ### @@ -386,7 +386,7 @@ if (WIN32) set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_PREFIX}/config/chips) else () set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}/chips) -endif () +endif() add_definitions( -DSTLINK_CHIPS_DIR="${CMAKE_CHIPS_DIR}" ) file(GLOB CHIP_FILES ${CMAKE_SOURCE_DIR}/config/chips/*.chip) install(FILES ${CHIP_FILES} DESTINATION ${CMAKE_CHIPS_DIR}) @@ -413,4 +413,4 @@ if (NOT TARGET uninstall) uninstall COMMAND ${CMAKE_COMMAND} -P ${CMAKE_CURRENT_BINARY_DIR}/cmake/cmake_uninstall.cmake ) -endif () +endif() diff --git a/cmake/modules/Findlibusb.cmake b/cmake/modules/Findlibusb.cmake index 6f0a21da6..830060486 100644 --- a/cmake/modules/Findlibusb.cmake +++ b/cmake/modules/Findlibusb.cmake @@ -24,7 +24,7 @@ if (CMAKE_SYSTEM_NAME STREQUAL "FreeBSD") # FreeBSD; libusb is mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) if (NOT LIBUSB_FOUND) message(FATAL_ERROR "Expected libusb library not found on your system! Verify your system integrity.") - endif () + endif() elseif (CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") # OpenBSD; libusb-1.0 is available from ports FIND_PATH( @@ -41,7 +41,7 @@ elseif (CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") # OpenBSD; libusb-1.0 mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) if (NOT LIBUSB_FOUND) message(FATAL_ERROR "No libusb-1.0 library found on your system! Install libusb-1.0 from ports or packages.") - endif () + endif() elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-toolchain on Debian # MinGW/MSYS/MSVC: 64-bit or 32-bit? @@ -51,7 +51,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to else () message(STATUS "=== Building for Windows (i686) ===") set(ARCH 32) - endif () + endif() if (WIN32 AND NOT EXISTS "/etc/debian_version") # Skip this for Debian... # Preparations for installing libusb library @@ -63,7 +63,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to elseif (EXISTS "/etc/debian_version" AND MINGW) # ... only for cross-building on Debian set(LIBUSB_WIN_ARCHIVE_PATH ${CMAKE_SOURCE_DIR}/build-mingw-${ARCH}/${LIBUSB_WIN_ARCHIVE}) set(LIBUSB_WIN_OUTPUT_FOLDER ${CMAKE_SOURCE_DIR}/build-mingw-${ARCH}/3rdparty/libusb-${LIBUSB_WIN_VERSION}) - endif () + endif() # Get libusb package if (EXISTS ${LIBUSB_WIN_ARCHIVE_PATH}) # ... should the package be already there (for whatever reason) @@ -74,7 +74,7 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to https://sourceforge.net/projects/libusb/files/libusb-1.0/libusb-${LIBUSB_WIN_VERSION}/libusb-${LIBUSB_WIN_VERSION}.7z/download ${LIBUSB_WIN_ARCHIVE_PATH} EXPECTED_MD5 aabe177bde869bfad34278335eaf8955 ) - endif () + endif() file(MAKE_DIRECTORY ${LIBUSB_WIN_OUTPUT_FOLDER}) @@ -110,9 +110,9 @@ elseif (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW)) # Windows or MinGW-to NO_DEFAULT_PATH NO_CMAKE_FIND_ROOT_PATH ) - endif () + endif() message(STATUS "Missing libusb library has been installed") - endif () + endif() FIND_PACKAGE_HANDLE_STANDARD_ARGS(libusb DEFAULT_MSG LIBUSB_LIBRARY LIBUSB_INCLUDE_DIR) mark_as_advanced(LIBUSB_INCLUDE_DIR LIBUSB_LIBRARY) @@ -132,5 +132,5 @@ else () if (NOT LIBUSB_FOUND) message(FATAL_ERROR "libusb library not found on your system! Install libusb 1.0.x from your package repository.") - endif () -endif () + endif() +endif() diff --git a/cmake/modules/c_flags.cmake b/cmake/modules/c_flags.cmake index 6e22d4ff3..d30f45ec9 100644 --- a/cmake/modules/c_flags.cmake +++ b/cmake/modules/c_flags.cmake @@ -14,7 +14,7 @@ function(add_cflag_if_supported flag) if (C_SUPPORTS${flagclean}) set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${flag}" PARENT_SCOPE) - endif () + endif() endfunction() add_cflag_if_supported("-Wall") @@ -38,14 +38,14 @@ add_cflag_if_supported("-Wimplicit-function-declaration") ## if (NOT CMAKE_SYSTEM_NAME STREQUAL "OpenBSD") add_cflag_if_supported("-Wredundant-decls") -endif () +endif() if (NOT (WIN32 OR (EXISTS "/etc/debian_version" AND MINGW))) add_cflag_if_supported("-fPIC") -endif () +endif() if (${CMAKE_BUILD_TYPE} MATCHES "Debug") add_cflag_if_supported("-ggdb") else () add_cflag_if_supported("-Werror") -endif () +endif() diff --git a/cmake/modules/get_version.cmake b/cmake/modules/get_version.cmake index 8211d9c84..07c5793df 100644 --- a/cmake/modules/get_version.cmake +++ b/cmake/modules/get_version.cmake @@ -28,7 +28,7 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") ) if (res EQUAL 1) set(PROJECT_VERSION "${PROJECT_VERSION}-dirty") - endif () + endif() # Strip a leading v off of the version as proceeding code expects just the version numbering. string(REGEX REPLACE "^v" "" PROJECT_VERSION ${PROJECT_VERSION}) @@ -53,14 +53,14 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") # ...the version does not match with git-version string if (NOT __version_str STREQUAL __version_file) message(STATUS "Rewrite ${PROJECT_SOURCE_DIR}/.version with ${__version_str}!") - endif () + endif() elseif (NOT EXISTS "${PROJECT_SOURCE_DIR}/.version") # No local .version file found: Create a new one... file(WRITE "${PROJECT_SOURCE_DIR}/.version" ${__version_str}) - endif () + endif() message(STATUS "stlink version: ${PROJECT_VERSION}") message(STATUS "Major ${PROJECT_VERSION_MAJOR} Minor ${PROJECT_VERSION_MINOR} Patch ${PROJECT_VERSION_PATCH}") @@ -68,13 +68,13 @@ if (GIT_FOUND AND EXISTS "${PROJECT_SOURCE_DIR}/.git") else (len EQUAL 3) message(STATUS "Failed to extract version parts from \"${PROJECT_VERSION}\"") set(ERROR_FLAG "1") - endif (len EQUAL 3) + endif(len EQUAL 3) else (GIT_DESCRIBE_RESULT EQUAL 0) message(WARNING "git describe failed: ${GIT_DESCRIBE_ERROR}") set(ERROR_FLAG "1") endif(GIT_DESCRIBE_RESULT EQUAL 0) -endif () +endif() ## # Failure to read version via git @@ -101,9 +101,9 @@ if (NOT GIT_FOUND OR NOT EXISTS "${PROJECT_SOURCE_DIR}/.git" OR ERROR_FLAG EQUAL set(__detect_version 1) else () message(STATUS "Fail to extract version parts from \"${PROJECT_VERSION}\"") - endif () + endif() else (EXISTS ${PROJECT_SOURCE_DIR}/.version) message(STATUS "File \"${PROJECT_SOURCE_DIR}/.version\" does not exist.") message(FATAL_ERROR "Unable to determine project version") - endif () -endif () + endif() +endif() diff --git a/cmake/modules/pandocology.cmake b/cmake/modules/pandocology.cmake index ff9053197..24cd4b9a1 100644 --- a/cmake/modules/pandocology.cmake +++ b/cmake/modules/pandocology.cmake @@ -45,7 +45,7 @@ include(CMakeParseArguments) if (NOT EXISTS ${PANDOC_EXECUTABLE}) find_program(PANDOC_EXECUTABLE pandoc) mark_as_advanced(PANDOC_EXECUTABLE) -endif () +endif() ############################################################################### # Based on code from UseLATEX @@ -133,7 +133,7 @@ This process created the file `CMakeCache.txt' and the directory `CMakeFiles'. Please delete them: $ rm -r CMakeFiles/ CmakeCache.txt ") - ENDif () + endif() endfunction() # This builds a document @@ -171,7 +171,7 @@ function(add_document target_name) if (NOT PANDOC_EXECUTABLE) message(WARNING "Pandoc not found. Install Pandoc (http://johnmacfarlane.net/pandoc/) or set cache variable PANDOC_EXECUTABLE.") return() - endif () + endif() set(options EXPORT_ARCHIVE NO_EXPORT_PRODUCT EXPORT_PDF DIRECT_TEX_TO_PDF VERBOSE) set(oneValueArgs PRODUCT_DIRECTORY) @@ -188,29 +188,29 @@ function(add_document target_name) if (NOT "${target_extension}" STREQUAL ".tex" AND NOT "${target_extension}" STREQUAL ".latex") # if (NOT "${target_extension}" STREQUAL ".tex") MESSAGE(FATAL_ERROR "Target '${target_name}': Cannot use 'EXPORT_PDF' for target of type '${target_extension}': target type must be '.tex' or '.latex'") - endif () - endif () + endif() + endif() if (${ADD_DOCUMENT_DIRECT_TEX_TO_PDF}) list(LENGTH ${ADD_DOCUMENT_SOURCES} SOURCE_LEN) if (SOURCE_LEN GREATER 1) MESSAGE(FATAL_ERROR "Target '${target_name}': Only one source can be specified when using the 'DIRECT_TEX_TO_PDF' option") - endif () + endif() # set(ADD_DOCUMENT_SOURCES, list(GET ${ADD_DOCUMENT_SOURCES} 1)) pandocology_get_file_stemname(source_stemname ${ADD_DOCUMENT_SOURCES}) pandocology_get_file_extension(source_extension ${ADD_DOCUMENT_SOURCES}) if (NOT "${source_extension}" STREQUAL ".tex" AND NOT "${source_extension}" STREQUAL ".latex") MESSAGE(FATAL_ERROR "Target '${target_name}': Cannot use 'DIRECT_TEX_TO_PDF' for source of type '${source_extension}': source type must be '.tex' or '.latex'") - endif () + endif() SET(check_target ${source_stemname}.pdf) IF (NOT ${check_target} STREQUAL ${target_name}) MESSAGE(FATAL_ERROR "Target '${target_name}': Must use target name of '${check_target}' if using 'DIRECT_TEX_TO_PDF'") - endif () - endif () + endif() + endif() ## set up output directory if ("${ADD_DOCUMENT_PRODUCT_DIRECTORY}" STREQUAL "") set(ADD_DOCUMENT_PRODUCT_DIRECTORY "product") - endif () + endif() get_filename_component(product_directory ${CMAKE_BINARY_DIR}/${ADD_DOCUMENT_PRODUCT_DIRECTORY} ABSOLUTE) # get_filename_component(absolute_product_path ${product_directory}/${target_name} ABSOLUTE) @@ -232,7 +232,7 @@ function(add_document target_name) pandocology_add_input_dir(${CMAKE_CURRENT_SOURCE_DIR}/${resource_dir} ${CMAKE_CURRENT_BINARY_DIR} build_resources) if (${ADD_DOCUMENT_EXPORT_ARCHIVE}) pandocology_add_input_dir(${CMAKE_CURRENT_SOURCE_DIR}/${resource_dir} ${product_directory} exported_resources) - endif () + endif() endforeach() ## primary command @@ -255,7 +255,7 @@ function(add_document target_name) # we produce the target in the source directory, in case other build targets require it as a source COMMAND latexmk -gg -halt-on-error -interaction=nonstopmode -file-line-error -pdf ${build_sources} 2>/dev/null >/dev/null || (grep --no-messages -A8 ".*:[0-9]*:.*" ${target_stemname}.log && false) ) - endif () + endif() add_to_make_clean(${CMAKE_CURRENT_BINARY_DIR}/${target_name}) else() add_custom_command( @@ -267,7 +267,7 @@ function(add_document target_name) COMMAND ${PANDOC_EXECUTABLE} ${build_sources} ${ADD_DOCUMENT_PANDOC_DIRECTIVES} -o ${target_name} ) add_to_make_clean(${CMAKE_CURRENT_BINARY_DIR}/${target_name}) - endif () + endif() ## figure out what all is going to be produced by this build set, and set ## those as dependencies of the primary target @@ -275,14 +275,14 @@ function(add_document target_name) set(primary_target_dependencies ${primary_target_dependencies} ${CMAKE_CURRENT_BINARY_DIR}/${target_name}) if (NOT ${ADD_DOCUMENT_NO_EXPORT_PRODUCT}) set(primary_target_dependencies ${primary_target_dependencies} ${product_directory}/${target_name}) - endif () + endif() if (${ADD_DOCUMENT_EXPORT_PDF}) set(primary_target_dependencies ${primary_target_dependencies} ${CMAKE_CURRENT_BINARY_DIR}/${target_stemname}.pdf) set(primary_target_dependencies ${primary_target_dependencies} ${product_directory}/${target_stemname}.pdf) - endif () + endif() if (${ADD_DOCUMENT_EXPORT_ARCHIVE}) set(primary_target_dependencies ${primary_target_dependencies} ${product_directory}/${target_stemname}.tbz) - endif () + endif() ## primary target # # target cannot have same (absolute name) as dependencies: @@ -326,7 +326,7 @@ function(add_document target_name) ) add_to_make_clean(${CMAKE_CURRENT_BINARY_DIR}/${target_stemname}.pdf) add_to_make_clean(${product_directory}/${target_stemname}.pdf) - endif () + endif() ## copy products if (NOT ${ADD_DOCUMENT_NO_EXPORT_PRODUCT}) @@ -336,7 +336,7 @@ function(add_document target_name) COMMAND ${CMAKE_COMMAND} -E copy ${target_name} ${product_directory} ) add_to_make_clean(${product_directory}/${target_name}) - endif () + endif() ## copy resources if (${ADD_DOCUMENT_EXPORT_ARCHIVE}) @@ -359,7 +359,7 @@ function(add_document target_name) # ALL # DEPENDS ${product_directory}/${target_stemname}.tbz # ) - endif () + endif() endfunction(add_document) diff --git a/cmake/packaging/cpack_config.cmake b/cmake/packaging/cpack_config.cmake index 57d4803d7..17de607ef 100644 --- a/cmake/packaging/cpack_config.cmake +++ b/cmake/packaging/cpack_config.cmake @@ -101,7 +101,7 @@ elseif (EXISTS "/etc/debian_version" AND NOT EXISTS WIN32) # Package-build is av else () # No package configuration on other platforms ... -endif () +endif() ### diff --git a/doc/man/CMakeLists.txt b/doc/man/CMakeLists.txt index 1b7d6501f..f225c85b7 100644 --- a/doc/man/CMakeLists.txt +++ b/doc/man/CMakeLists.txt @@ -17,7 +17,7 @@ if (${STLINK_GENERATE_MANPAGES}) endforeach () else () message(STATUS "Manpage generation disabled") -endif () +endif() # Install from output folder or this folder foreach (manpage ${MANPAGES}) @@ -27,10 +27,10 @@ foreach (manpage ${MANPAGES}) set(f "${CMAKE_CURRENT_SOURCE_DIR}/${manpage}.1") else() message(AUTHOR_WARNING "Manpage ${manpage} not generated") - endif () + endif() if (f AND NOT WIN32) install(FILES ${f} DESTINATION ${CMAKE_INSTALL_DATADIR}/man/man1) unset(f) - endif () + endif() endforeach () diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 711d7d2eb..ba6d1f4bb 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -75,7 +75,7 @@ int32_t main(int32_t ac, char** av) { if (flash_get_opts(&o, ac - 1, av + 1) == -1) { printf("invalid command line\n"); usage(); - return(-1); + return (-1); } printf("st-flash %s\n", STLINK_VERSION); @@ -83,7 +83,7 @@ int32_t main(int32_t ac, char** av) { sl = stlink_open_usb(o.log_level, o.connect, (char *)o.serial, o.freq); - if (sl == NULL) { return(-1); } + if (sl == NULL) { return (-1); } if (sl->flash_type == STM32_FLASH_TYPE_UNKNOWN) { printf("Failed to connect to target\n"); @@ -299,5 +299,5 @@ int32_t main(int32_t ac, char** av) { stlink_close(sl); free(mem); - return(err); + return (err); } diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 358074793..300203a3f 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -19,7 +19,7 @@ static bool starts_with(const char * str, const char * prefix) { uint32_t n = strlen(prefix); - if (strlen(str) < n) { return(false); } + if (strlen(str) < n) { return (false); } return (0 == strncmp(str, prefix, n)); } @@ -49,11 +49,11 @@ static int32_t get_long_integer_from_char_array (const char *const str, uint64_t } else if (tail[0] == '\0') { /* value not changed */ } else { - return(-1); + return (-1); } *read_value = value; - return(0); + return (0); } // support positive integer from 0 to UINT32_MAX @@ -65,24 +65,24 @@ static int32_t get_integer_from_char_array (const char *const str, uint32_t *rea int32_t result = get_long_integer_from_char_array (str, &value); if (result != 0) { - return(result); + return (result); } else if (value > UINT32_MAX) { fprintf (stderr, "*** Error: Integer greater than UINT32_MAX, cannot convert to int32_t\n"); - return(-1); + return (-1); } else { *read_value = value; - return(0); + return (0); } } static int32_t invalid_args(const char *expected) { fprintf(stderr, "*** Error: Expected args for this command: %s\n", expected); - return(-1); + return (-1); } static int32_t bad_arg(const char *arg) { fprintf(stderr, "*** Error: Invalid value for %s\n", arg); - return(-1); + return (-1); } int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { @@ -111,7 +111,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { ac--; av++; - if (ac < 1) { return(-1); } + if (ac < 1) { return (-1); } serial = av[0]; } else { @@ -127,7 +127,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { ac--; av++; - if (ac < 1) { return(-1); } + if (ac < 1) { return (-1); } area = av[0]; } else { @@ -149,7 +149,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { } else if (strcmp(area, "optcr1") == 0) { o->area = FLASH_OPTCR1; } else { - return(-1); + return (-1); } } else if (strcmp(av[0], "--freq") == 0) { @@ -157,17 +157,17 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { av++; if (ac < 1) { - return(-1); + return (-1); } o->freq = arg_parse_freq(av[0]); if (o->freq < 0) { - return(-1); + return (-1); } } else if (starts_with(av[0], "--freq=")) { o->freq = arg_parse_freq(av[0] + strlen("--freq=")); if (o->freq < 0) { - return(-1); + return (-1); } } else if (strcmp(av[0], "--format") == 0 || starts_with(av[0], "--format=")) { const char * format; @@ -176,7 +176,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { ac--; av++; - if (ac < 1) { return(-1); } + if (ac < 1) { return (-1); } format = av[0]; } else { @@ -188,7 +188,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { } else if (strcmp(format, "ihex") == 0) { o->format = FLASH_FORMAT_IHEX; } else { - return(bad_arg("format")); + return (bad_arg("format")); } } else if ( starts_with(av[0], "--flash=")) { const char *arg = av[0] + strlen("--flash="); @@ -197,7 +197,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { result = get_integer_from_char_array(arg, &flash_size); if (result != 0) { - return(bad_arg ("--flash")); + return (bad_arg ("--flash")); } else { o->flash_size = (size_t)flash_size; } @@ -217,18 +217,18 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { // command and (optional) device name while (ac >= 1) { if (strcmp(av[0], "erase") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return (-1); } o->cmd = FLASH_CMD_ERASE; } else if (strcmp(av[0], "read") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return (-1); } o->cmd = FLASH_CMD_READ; } else if (strcmp(av[0], "write") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return (-1); } o->cmd = FLASH_CMD_WRITE; } else if (strcmp(av[0], "reset") == 0) { - if (o->cmd != FLASH_CMD_NONE) { return(-1); } + if (o->cmd != FLASH_CMD_NONE) { return (-1); } o->cmd = CMD_RESET; } else { @@ -241,10 +241,10 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { switch (o->cmd) { case FLASH_CMD_NONE: // no command found - return(-1); + return (-1); case FLASH_CMD_ERASE: // no more arguments expected - if (ac != 0 && ac != 2) { return(-1); } + if (ac != 0 && ac != 2) { return (-1); } if (ac == 2) { uint32_t address; result = get_integer_from_char_array(av[0], &address); @@ -336,7 +336,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { result = get_integer_from_char_array(av[0], &val); if (result != 0) { - return(bad_arg ("val")); + return (bad_arg ("val")); } else { o->val = val; } @@ -369,16 +369,16 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { result = get_integer_from_char_array(av[1], &addr); if (result != 0) { - return(bad_arg ("addr")); + return (bad_arg ("addr")); } else { o->addr = (stm32_addr_t)addr; } } else if (o->format == FLASH_FORMAT_IHEX) { // expect filename - if (ac != 1) { return(invalid_args("write ")); } + if (ac != 1) { return (invalid_args("write ")); } o->filename = av[0]; } else { - return(-1); // should have been caught during format parsing + return (-1); // should have been caught during format parsing } break; @@ -386,5 +386,5 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { default: break; } - return(0); + return (0); } diff --git a/src/st-info/info.c b/src/st-info/info.c index 664db7b2a..ffdf521cc 100644 --- a/src/st-info/info.c +++ b/src/st-info/info.c @@ -74,7 +74,7 @@ static int32_t print_data(int32_t ac, char **av) { if (strcmp(av[1], "--version") == 0) { printf("v%s\n", STLINK_VERSION); - return(0); + return (0); } init_chipids(STLINK_CHIPS_DIR); @@ -99,18 +99,18 @@ static int32_t print_data(int32_t ac, char **av) { printf("Incorrect argument: %s\n\n", av[i]); usage(); - return(-1); + return (-1); } // probe needs all devices unclaimed if (strcmp(av[1], "--probe") == 0) { stlink_probe(connect, freq); - return(0); + return (0); } // open first st-link device sl = stlink_open_usb(0, connect, NULL, freq); - if (sl == NULL) { return(-1); } + if (sl == NULL) { return (-1); } if (strcmp(av[1], "--serial") == 0) { printf("%s\n", sl->serial); @@ -124,7 +124,7 @@ static int32_t print_data(int32_t ac, char **av) { printf("0x%.4x\n", sl->chip_id); } else if (strcmp(av[1], "--descr") == 0) { const struct stlink_chipid_params *params = stlink_chipid_get_params(sl->chip_id); - if (params == NULL) { return(-1); } + if (params == NULL) { return (-1); } printf("%s\n", params->dev_type); } @@ -134,7 +134,7 @@ static int32_t print_data(int32_t ac, char **av) { stlink_close(sl); } - return(0); + return (0); } int32_t main(int32_t ac, char** av) { @@ -142,10 +142,10 @@ int32_t main(int32_t ac, char** av) { if (ac < 2) { usage(); - return(-1); + return (-1); } err = print_data(ac, av); - return(err); + return (err); } diff --git a/src/st-util/gdb-remote.c b/src/st-util/gdb-remote.c index 7d0f2c731..25ca4da5b 100644 --- a/src/st-util/gdb-remote.c +++ b/src/st-util/gdb-remote.c @@ -42,19 +42,19 @@ int32_t gdb_send_packet(int32_t fd, char* data) { while (1) { if (write(fd, packet, length) != length) { free(packet); - return(-2); + return (-2); } char ack; if (read(fd, &ack, 1) != 1) { free(packet); - return(-2); + return (-2); } if (ack == '+') { free(packet); - return(0); + return (0); } } } @@ -69,7 +69,7 @@ int32_t gdb_recv_packet(int32_t fd, char** buffer) { uint32_t state; if (packet_buffer == NULL) { - return(-2); + return (-2); } start: @@ -88,7 +88,7 @@ int32_t gdb_recv_packet(int32_t fd, char** buffer) { while (state != 4) { if (read(fd, &c, 1) != 1) { free(packet_buffer); - return(-2); + return (-2); } switch (state) { @@ -117,7 +117,7 @@ int32_t gdb_recv_packet(int32_t fd, char** buffer) { packet_buffer = p; } else { free(packet_buffer); - return(-2); + return (-2); } } } @@ -143,7 +143,7 @@ int32_t gdb_recv_packet(int32_t fd, char** buffer) { if (write(fd, &nack, 1) != 1) { free(packet_buffer); - return(-2); + return (-2); } goto start; @@ -152,14 +152,14 @@ int32_t gdb_recv_packet(int32_t fd, char** buffer) { if (write(fd, &ack, 1) != 1) { free(packet_buffer); - return(-2); + return (-2); } } packet_buffer[packet_idx] = 0; *buffer = packet_buffer; - return(packet_idx); + return (packet_idx); } /* @@ -176,13 +176,13 @@ int32_t gdb_check_for_interrupt(int32_t fd) { char c; if (read(fd, &c, 1) != 1) { - return(-2); + return (-2); } if (c == '\x03') { - return(1); // ^C + return (1); // ^C } } - return(0); + return (0); } diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 9f9d93844..8a187fb24 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -214,7 +214,7 @@ int32_t parse_options(int32_t argc, char** argv, st_state_t *st) { printf("\n"); } - return(0); + return (0); } int32_t main(int32_t argc, char** argv) { @@ -233,11 +233,11 @@ int32_t main(int32_t argc, char** argv) { init_chipids (STLINK_CHIPS_DIR); sl = stlink_open_usb(state.logging_level, state.connect_mode, state.serialnumber, state.freq); - if (sl == NULL) { return(1); } + if (sl == NULL) { return (1); } if (sl->chip_id == STM32_CHIPID_UNKNOWN) { ELOG("Unsupported Target (Chip ID is %#010x, Core ID is %#010x).\n", sl->chip_id, sl->core_id); - return(1); + return (1); } sl->verbose = 0; @@ -275,7 +275,7 @@ int32_t main(int32_t argc, char** argv) { stlink_exit_debug_mode(sl); stlink_close(sl); - return(0); + return (0); } static const char* const target_description = @@ -608,7 +608,7 @@ char* make_memory_map(stlink_t *sl) { sl->sys_size); } - return(map); + return (map); } #define DATA_WATCH_NUM 4 @@ -676,12 +676,12 @@ static int32_t add_data_watchpoint(stlink_t *sl, enum watchfun wf, stm32_addr_t // just to make sure the matched bit is clear ! stlink_read_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), &dummy); - return(0); + return (0); } } DLOG("failure: add watchpoints addr %x wf %u len %u\n", addr, wf, len); - return(-1); + return (-1); } static int32_t delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { @@ -694,13 +694,13 @@ static int32_t delete_data_watchpoint(stlink_t *sl, stm32_addr_t addr) { data_watches[i].fun = WATCHDISABLED; stlink_write_debug32(sl, STLINK_REG_CM3_DWT_FUNn(i), 0); - return(0); + return (0); } } DLOG("failure: delete watchpoint addr %x\n", addr); - return(-1); + return (-1); } static int32_t code_break_num; @@ -746,9 +746,9 @@ static void init_code_breakpoints(stlink_t *sl) { static int32_t has_breakpoint(stm32_addr_t addr) { for (int32_t i = 0; i < code_break_num; i++) - if (code_breaks[i].addr == addr) { return(1); } + if (code_breaks[i].addr == addr) { return (1); } - return(0); + return (0); } static int32_t update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int32_t set) { @@ -758,7 +758,7 @@ static int32_t update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int32_t s if (addr & 1) { ELOG("update_code_breakpoint: unaligned address %08x\n", addr); - return(-1); + return (-1); } if (code_break_rev == CODE_BREAK_REV_V1) { @@ -778,9 +778,9 @@ static int32_t update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int32_t s if (id == -1) { if (set) - return(-1); // free slot not found + return (-1); // free slot not found else - return(0); // breakpoint is already removed + return (0); // breakpoint is already removed } struct code_hw_breakpoint* bp = &code_breaks[id]; @@ -802,7 +802,7 @@ static int32_t update_code_breakpoint(stlink_t *sl, stm32_addr_t addr, int32_t s stlink_write_debug32(sl, STLINK_REG_CM3_FP_COMPn(id), mask); } - return(0); + return (0); } @@ -820,14 +820,14 @@ static int32_t flash_add_block(stm32_addr_t addr, uint32_t length, stlink_t *sl) if (addr < FLASH_BASE || addr + length > FLASH_BASE + sl->flash_size) { ELOG("flash_add_block: incorrect bounds\n"); - return(-1); + return (-1); } stlink_calculate_pagesize(sl, addr); if (addr % FLASH_PAGE != 0 || length % FLASH_PAGE != 0) { ELOG("flash_add_block: unaligned block\n"); - return(-1); + return (-1); } struct flash_block* new = malloc(sizeof(struct flash_block)); @@ -838,7 +838,7 @@ static int32_t flash_add_block(stm32_addr_t addr, uint32_t length, stlink_t *sl) memset(new->data, stlink_get_erased_pattern(sl), length); flash_root = new; - return(0); + return (0); } static int32_t flash_populate(stm32_addr_t addr, uint8_t* data, uint32_t length) { @@ -871,7 +871,7 @@ static int32_t flash_populate(stm32_addr_t addr, uint8_t* data, uint32_t length) if (fit_blocks == 0) { ELOG("Unfit data block %08x -> %04x\n", addr, length); - return(-1); + return (-1); } if (fit_length != length) { @@ -879,7 +879,7 @@ static int32_t flash_populate(stm32_addr_t addr, uint8_t* data, uint32_t length) WLOG("(this is not an error, just a GDB glitch)\n"); } - return(0); + return (0); } static int32_t flash_go(stlink_t *sl, st_state_t *st) { @@ -935,7 +935,7 @@ static int32_t flash_go(stlink_t *sl, st_state_t *st) { } flash_root = NULL; - return(error); + return (error); } struct cache_level_desc { @@ -967,7 +967,7 @@ static uint32_t ceil_log2(uint32_t v) { for (res = 0; (1U << res) < v; res++); - return(res); + return (res); } static void read_cache_level_desc(stlink_t *sl, struct cache_level_desc *desc) { @@ -1083,12 +1083,12 @@ static uint32_t unhexify(const char *in, char *out, uint32_t out_count) { uint32_t c; for (i = 0; i < out_count; i++) { - if (sscanf(in + (2 * i), "%02x", &c) != 1) { return(i); } + if (sscanf(in + (2 * i), "%02x", &c) != 1) { return (i); } out[i] = (char)c; } - return(i); + return (i); } int32_t serve(stlink_t *sl, st_state_t *st) { @@ -1096,7 +1096,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { if (!IS_SOCK_VALID(sock)) { perror("socket"); - return(1); + return (1); } uint32_t val = 1; @@ -1111,13 +1111,13 @@ int32_t serve(stlink_t *sl, st_state_t *st) { if (bind(sock, (struct sockaddr *)&serv_addr, sizeof(serv_addr)) < 0) { perror("bind"); close_socket(sock); - return(1); + return (1); } if (listen(sock, 5) < 0) { perror("listen"); close_socket(sock); - return(1); + return (1); } ILOG("Listening at *:%d...\n", st->listen_port); @@ -1128,7 +1128,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { if (!IS_SOCK_VALID(client)) { perror("accept"); close_socket(sock); - return(1); + return (1); } close_socket(sock); @@ -1169,7 +1169,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { if (status < 0) { ELOG("cannot recv: %d\n", status); close_socket(client); - return(1); + return (1); } DLOG("recv: %s\n", packet); @@ -1447,7 +1447,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { if (status < 0) { ELOG("cannot check for int: %d\n", status); close_socket(client); - return(1); + return (1); } if (status == 1) { @@ -1884,7 +1884,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { free(reply); free(packet); close_socket(client); - return(1); + return (1); } free(reply); @@ -1892,12 +1892,12 @@ int32_t serve(stlink_t *sl, st_state_t *st) { if (critical_error) { close_socket(client); - return(1); + return (1); } free(packet); } close_socket(client); - return(0); + return (0); } diff --git a/src/st-util/semihosting.c b/src/st-util/semihosting.c index 93a6cf7cc..a200a7408 100644 --- a/src/st-util/semihosting.c +++ b/src/st-util/semihosting.c @@ -16,13 +16,13 @@ static int32_t mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { int32_t offset = addr % 4; int32_t len = 4; - if (sl == NULL || data == NULL) { return(-1); } + if (sl == NULL || data == NULL) { return (-1); } // read address and length must be aligned - if (stlink_read_mem32(sl, addr - offset, len) != 0) { return(-1); } + if (stlink_read_mem32(sl, addr - offset, len) != 0) { return (-1); } *data = sl->q_buf[offset]; - return(0); + return (0); } #ifdef UNUSED @@ -30,26 +30,26 @@ static int32_t mem_read_u16(stlink_t *sl, uint32_t addr, uint16_t *data) { int32_t offset = addr % 4; int32_t len = (offset > 2 ? 8 : 4); - if (sl == NULL || data == NULL) { return(-1); } + if (sl == NULL || data == NULL) { return (-1); } // read address and length must be aligned - if (stlink_read_mem32(sl, addr - offset, len) != 0) { return(-1); } + if (stlink_read_mem32(sl, addr - offset, len) != 0) { return (-1); } memcpy(data, &sl->q_buf[offset], sizeof(*data)); - return(0); + return (0); } static int32_t mem_read_u32(stlink_t *sl, uint32_t addr, uint32_t *data) { int32_t offset = addr % 4; int32_t len = (offset > 0 ? 8 : 4); - if (sl == NULL || data == NULL) { return(-1); } + if (sl == NULL || data == NULL) { return (-1); } // read address and length must be aligned - if (stlink_read_mem32(sl, addr - offset, len) != 0) { return(-1); } + if (stlink_read_mem32(sl, addr - offset, len) != 0) { return (-1); } memcpy(data, &sl->q_buf[offset], sizeof(*data)); - return(0); + return (0); } #endif @@ -57,16 +57,16 @@ static int32_t mem_read(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { int32_t offset = addr % 4; int32_t read_len = len + offset; - if (sl == NULL || data == NULL) { return(-1); } + if (sl == NULL || data == NULL) { return (-1); } // align read size if ((read_len % 4) != 0) { read_len += 4 - (read_len % 4); } // address and length must be aligned - if (stlink_read_mem32(sl, addr - offset, read_len) != 0) { return(-1); } + if (stlink_read_mem32(sl, addr - offset, read_len) != 0) { return (-1); } memcpy(data, &sl->q_buf[offset], len); - return(0); + return (0); } static int32_t mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) { @@ -77,12 +77,12 @@ static int32_t mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) * the requested bytes. (perhaps reading the whole area is faster??). * If 16 and 8 bit writes are available, then they could be used instead. * Just return when the length is zero avoiding unneeded work. */ - if (len == 0) { return(0); } + if (len == 0) { return (0); } int32_t offset = addr % 4; int32_t write_len = len + offset; - if (sl == NULL || data == NULL) { return(-1); } + if (sl == NULL || data == NULL) { return (-1); } // align read size if ((write_len % 4) != 0) { write_len += 4 - (write_len % 4); } @@ -90,9 +90,9 @@ static int32_t mem_write(stlink_t *sl, uint32_t addr, void *data, uint16_t len) memcpy(&sl->q_buf[offset], data, len); // address and length must be aligned - if (stlink_write_mem32(sl, addr - offset, write_len) != 0) { return(-1); } + if (stlink_write_mem32(sl, addr - offset, write_len) != 0) { return (-1); } - return(0); + return (0); } /* For the SYS_WRITE0 call, we don't know the size of the null-terminated buffer @@ -132,7 +132,7 @@ static int32_t saved_errno = 0; int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { - if (sl == NULL || ret == NULL) { return(-1); } + if (sl == NULL || ret == NULL) { return (-1); } DLOG("Do semihosting R0=0x%08x R1=0x%08x\n", r0, r1); @@ -148,7 +148,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (mem_read(sl, r1, args, sizeof(args)) != 0) { DLOG("Semihosting SYS_OPEN error: cannot read args from target memory\n"); *ret = -1; - return(-1); + return (-1); } name_address = args[0]; @@ -159,7 +159,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { /* Invalid mode */ DLOG("Semihosting SYS_OPEN error: invalid mode %d\n", mode); *ret = -1; - return(-1); + return (-1); } /* Add the trailing zero that is not counted in the length argument (see @@ -170,7 +170,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (name_len > MAX_BUFFER_SIZE) { DLOG("Semihosting SYS_OPEN error: name buffer size is too big %d\n", name_len); *ret = -1; - return(-1); + return (-1); } name = malloc(name_len); @@ -178,14 +178,14 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (name == NULL) { DLOG("Semihosting SYS_OPEN error: cannot allocate name buffer\n"); *ret = -1; - return(-1); + return (-1); } if (mem_read(sl, name_address, name, name_len) != 0) { free(name); *ret = -1; DLOG("Semihosting SYS_OPEN error: cannot read name from target memory\n"); - return(-1); + return (-1); } DLOG("Semihosting: open('%s', (SH open mode)%d, 0644)\n", name, mode); @@ -206,7 +206,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (mem_read(sl, r1, args, sizeof(args)) != 0) { DLOG("Semihosting SYS_CLOSE error: cannot read args from target memory\n"); *ret = -1; - return(-1); + return (-1); } fd = (int32_t)args[0]; @@ -230,7 +230,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (mem_read(sl, r1, args, sizeof(args)) != 0) { DLOG("Semihosting SYS_WRITE error: cannot read args from target memory\n"); *ret = -1; - return(-1); + return (-1); } fd = (int32_t)args[0]; @@ -241,7 +241,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { DLOG("Semihosting SYS_WRITE error: buffer size is too big %d\n", buffer_len); *ret = buffer_len; - return(-1); + return (-1); } buffer = malloc(buffer_len); @@ -249,14 +249,14 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (buffer == NULL) { DLOG("Semihosting SYS_WRITE error: cannot allocate buffer\n"); *ret = buffer_len; - return(-1); + return (-1); } if (mem_read(sl, buffer_address, buffer, buffer_len) != 0) { DLOG("Semihosting SYS_WRITE error: cannot read buffer from target memory\n"); free(buffer); *ret = buffer_len; - return(-1); + return (-1); } DLOG("Semihosting: write(%d, target_addr:0x%08x, %u)\n", fd, buffer_address, buffer_len); @@ -286,7 +286,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (mem_read(sl, r1, args, sizeof(args)) != 0) { DLOG("Semihosting SYS_READ error: cannot read args from target memory\n"); *ret = -1; - return(-1); + return (-1); } fd = (int32_t)args[0]; @@ -296,7 +296,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (buffer_len > MAX_BUFFER_SIZE) { DLOG("Semihosting SYS_READ error: buffer size is too big %d\n", buffer_len); *ret = buffer_len; - return(-1); + return (-1); } buffer = malloc(buffer_len); @@ -304,7 +304,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (buffer == NULL) { DLOG("Semihosting SYS_READ error: cannot allocatebuffer\n"); *ret = buffer_len; - return(-1); + return (-1); } DLOG("Semihosting: read(%d, target_addr:0x%08x, %u)\n", fd, buffer_address, @@ -320,7 +320,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { DLOG("Semihosting SYS_READ error: cannot write buffer to target memory\n"); free(buffer); *ret = buffer_len; - return(-1); + return (-1); } else { *ret = buffer_len - (uint32_t)read_result; } @@ -346,7 +346,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (mem_read(sl, r1, args, sizeof(args)) != 0) { DLOG("Semihosting SYS_REMOVE error: cannot read args from target memory\n"); *ret = -1; - return(-1); + return (-1); } name_address = args[0]; @@ -361,7 +361,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { DLOG("Semihosting SYS_REMOVE error: name buffer size is too big %d\n", name_len); *ret = -1; - return(-1); + return (-1); } name = malloc(name_len); @@ -369,14 +369,14 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (name == NULL) { DLOG("Semihosting SYS_REMOVE error: cannot allocate name buffer\n"); *ret = -1; - return(-1); + return (-1); } if (mem_read(sl, name_address, name, name_len) != 0) { free(name); *ret = -1; DLOG("Semihosting SYS_REMOVE error: cannot read name from target memory\n"); - return(-1); + return (-1); } DLOG("Semihosting: unlink('%s')\n", name); @@ -395,7 +395,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { if (mem_read(sl, r1, args, sizeof(args)) != 0) { DLOG("Semihosting SYS_SEEK error: cannot read args from target memory\n"); *ret = -1; - return(-1); + return (-1); } fd = (int32_t)args[0]; @@ -435,11 +435,11 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { while (true) { if (mem_read(sl, r1, buf, WRITE0_BUFFER_SIZE) != 0) { DLOG("Semihosting WRITE0: cannot read target memory at 0x%08x\n", r1); - return(-1); + return (-1); } for (int32_t i = 0; i < WRITE0_BUFFER_SIZE; i++) { - if (buf[i] == 0) { return(0); } + if (buf[i] == 0) { return (0); } fprintf(stderr, "%c", buf[i]); } @@ -451,7 +451,7 @@ int32_t do_semihosting (stlink_t *sl, uint32_t r0, uint32_t r1, uint32_t *ret) { } default: fprintf(stderr, "semihosting: unsupported call %#x\n", r0); - return(-1); + return (-1); } - return(0); + return (0); } diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index fb4478bdc..bbfcc20a3 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -31,5 +31,5 @@ if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_BINDIR}) - endif () -endif () + endif() +endif() diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index 5853e5ec4..4b312c8a1 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -63,7 +63,7 @@ static gboolean set_info_error_message_idle(STlinkGUI *gui) { gui->error_message = NULL; } - return(FALSE); + return (FALSE); } static void stlink_gui_set_info_error_message(STlinkGUI *gui, const gchar *message) { @@ -156,15 +156,15 @@ static guint32 hexstr_to_guint32(const gchar *str, GError **err) { if ((errno == ERANGE && val == UINT_MAX) || (errno != 0 && val == 0)) { g_set_error(err, g_quark_from_string("hextou32"), 1, "Invalid hexstring"); - return(UINT32_MAX); + return (UINT32_MAX); } if (end_ptr == str) { g_set_error(err, g_quark_from_string("hextou32"), 2, "Invalid hexstring"); - return(UINT32_MAX); + return (UINT32_MAX); } - return(val); + return (val); } static void stlink_gui_update_mem_view(STlinkGUI *gui, struct mem_t *mem, GtkTreeView *view) { @@ -182,7 +182,7 @@ static void stlink_gui_update_mem_view(STlinkGUI *gui, struct mem_t *mem, GtkTre static gboolean stlink_gui_update_devmem_view(STlinkGUI *gui) { stlink_gui_update_mem_view(gui, &gui->flash_mem, gui->devmem_treeview); - return(FALSE); + return (FALSE); } static gpointer stlink_gui_populate_devmem_view(gpointer data) { @@ -220,7 +220,7 @@ static gpointer stlink_gui_populate_devmem_view(gpointer data) { stlink_gui_set_info_error_message(gui, "Failed to read memory"); g_free(gui->flash_mem.memory); gui->flash_mem.memory = NULL; - return(NULL); + return (NULL); } memcpy(gui->flash_mem.memory + off, gui->sl->q_buf, n_read); @@ -228,7 +228,7 @@ static gpointer stlink_gui_populate_devmem_view(gpointer data) { } g_idle_add((GSourceFunc)stlink_gui_update_devmem_view, gui); - return(NULL); + return (NULL); } static gboolean stlink_gui_update_filemem_view(STlinkGUI *gui) { @@ -240,7 +240,7 @@ static gboolean stlink_gui_update_filemem_view(STlinkGUI *gui) { g_free(basename); stlink_gui_update_mem_view(gui, &gui->file_mem, gui->filemem_treeview); - return(FALSE); + return (FALSE); } static gpointer stlink_gui_populate_filemem_view(gpointer data) { @@ -338,7 +338,7 @@ out: g_object_unref(file); } g_idle_add((GSourceFunc)stlink_gui_update_filemem_view, gui); - return(NULL); + return (NULL); } static void mem_jmp(GtkTreeView *view, @@ -438,13 +438,13 @@ static gchar *dev_format_chip_id(guint32 chip_id) { params = stlink_chipid_get_params(chip_id); - if (!params) { return(g_strdup_printf("0x%x", chip_id)); } + if (!params) { return (g_strdup_printf("0x%x", chip_id)); } - return(g_strdup(params->dev_type)); + return (g_strdup(params->dev_type)); } static gchar *dev_format_mem_size(gsize flash_size) { - return(g_strdup_printf("%u kB", (uint32_t)(flash_size / 1024))); + return (g_strdup_printf("%u kB", (uint32_t)(flash_size / 1024))); } @@ -585,7 +585,7 @@ static gboolean stlink_gui_write_flash_update(STlinkGUI *gui) { stlink_gui_set_sensitivity(gui, TRUE); gui->progress.activity_mode = FALSE; gtk_widget_hide(GTK_WIDGET(gui->progress.bar)); - return(FALSE); + return (FALSE); } static gpointer stlink_gui_write_flash(gpointer data) { @@ -601,7 +601,7 @@ static gpointer stlink_gui_write_flash(gpointer data) { } g_idle_add((GSourceFunc)stlink_gui_write_flash_update, gui); - return(NULL); + return (NULL); } static void flash_button_cb(GtkWidget *widget, gpointer data) { @@ -648,13 +648,13 @@ int32_t export_to_file(const char*filename, const struct mem_t flash_mem) { printf("%s\n", filename); FILE * f = fopen(filename, "w"); - if (f == NULL) { return(-1); } + if (f == NULL) { return (-1); } for (gsize i = 0; i < flash_mem.size; i++) - if (fputc(flash_mem.memory[i], f) == EOF) { return(-1); } + if (fputc(flash_mem.memory[i], f) == EOF) { return (-1); } fclose(f); - return(0); + return (0); } static void export_button_cb(GtkWidget *widget, gpointer data) { @@ -697,7 +697,7 @@ static gboolean progress_pulse_timeout(STlinkGUI *gui) { gtk_progress_bar_set_fraction(gui->progress.bar, gui->progress.fraction); } - return(TRUE); + return (TRUE); } static void notebook_switch_page_cb(GtkNotebook *notebook, @@ -901,5 +901,5 @@ int32_t main(int32_t argc, char **argv) { stlink_gui_init_dnd(gui); gtk_main(); - return(0); + return (0); } diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 0ab8cf6c1..0f12c3131 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -177,7 +177,7 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { // allocate the loader in SRAM if (stlink_flash_loader_write_to_sram(sl, &fl->loader_addr, &size) == -1) { WLOG("Failed to write flash loader to sram!\n"); - return(-1); + return (-1); } // allocate a one page buffer in SRAM right after loader @@ -205,7 +205,7 @@ int32_t stlink_flash_loader_init(stlink_t *sl, flash_loader_t *fl) { stlink_write_debug32(sl, STLINK_REG_HFSR, hfsr); } - return(0); + return (0); } static int32_t loader_v_dependent_assignment(stlink_t *sl, @@ -235,7 +235,7 @@ static int32_t loader_v_dependent_assignment(stlink_t *sl, } } - return(retval); + return (retval); } int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, uint32_t* size) { @@ -285,7 +285,7 @@ int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, uint loader_code_stm32f4, sizeof(loader_code_stm32f4), loader_code_stm32f4_lv, sizeof(loader_code_stm32f4_lv)); - if (retval == -1) { return(retval); } + if (retval == -1) { return (retval); } } else if (sl->core_id == STM32_CORE_ID_M7F_SWD || sl->chip_id == STM32_CHIPID_F7 || sl->chip_id == STM32_CHIPID_F76xxx || @@ -296,7 +296,7 @@ int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, uint loader_code_stm32f7, sizeof(loader_code_stm32f7), loader_code_stm32f7_lv, sizeof(loader_code_stm32f7_lv)); - if (retval == -1) { return(retval); } + if (retval == -1) { return (retval); } } else if (sl->chip_id == STM32_CHIPID_F0 || sl->chip_id == STM32_CHIPID_F04 || sl->chip_id == STM32_CHIPID_F0_CAN || @@ -315,18 +315,18 @@ int32_t stlink_flash_loader_write_to_sram(stlink_t *sl, stm32_addr_t* addr, uint } else { ELOG("unknown coreid, not sure what flash loader to use, aborting! coreid: %x, chipid: %x\n", sl->core_id, sl->chip_id); - return(-1); + return (-1); } memcpy(sl->q_buf, loader_code, loader_size); int32_t ret = stlink_write_mem32(sl, sl->sram_base, (uint16_t)loader_size); - if (ret) { return(ret); } + if (ret) { return (ret); } *addr = sl->sram_base; *size = loader_size; - return(0); // success + return (0); // success } int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, uint32_t size) { @@ -339,7 +339,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t if (write_buffer_to_sram(sl, fl, buf, size) == -1) { ELOG("write_buffer_to_sram() == -1\n"); - return(-1); + return (-1); } if ((sl->flash_type == STM32_FLASH_TYPE_F1_XL) && (target >= FLASH_BANK2_START_ADDR)) { @@ -404,7 +404,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t goto error; } - return(0); + return (0); error: dhcsr = dfsr = cfsr = hfsr = 0; @@ -419,7 +419,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t WLOG("MCU state: DHCSR 0x%X DFSR 0x%X CFSR 0x%X HFSR 0x%X\n", dhcsr, dfsr, cfsr, hfsr); } - return(-1); + return (-1); } @@ -868,8 +868,7 @@ int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { (sl->flash_type == STM32_FLASH_TYPE_WB_WL)) { clear_flash_cr_pg(sl, BANK_1); - if ((sl->flash_type == STM32_FLASH_TYPE_H7 && - sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || + if ((sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK) || sl->flash_type == STM32_FLASH_TYPE_F1_XL) { clear_flash_cr_pg(sl, BANK_2); } @@ -886,9 +885,8 @@ int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { // enable interrupt if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { - stlink_write_debug32(sl, STLINK_REG_DHCSR, - STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | - (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); + stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | + (dhcsr & (~STLINK_REG_DHCSR_C_MASKINTS))); } // restore DMA state diff --git a/src/stlink-lib/lib_md5.c b/src/stlink-lib/lib_md5.c index 71703273c..62e77252e 100644 --- a/src/stlink-lib/lib_md5.c +++ b/src/stlink-lib/lib_md5.c @@ -152,7 +152,7 @@ static void* TransformFunction(Md5Context* ctx, void const* data, uintmax_t size #undef GET #undef SET - return(ptr); + return (ptr); } /* EXPORTED FUNCTIONS */ diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index d7f844b51..b744389ba 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -141,12 +141,12 @@ static int32_t get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t if (ret != LIBUSB_SUCCESS) { WLOG("%s: receiving failed: %d\n", __func__, ret); - return(-1); + return (-1); } if (transferred != sizeof(csw)) { WLOG("%s: received unexpected amount: %d\n", __func__, transferred); - return(-1); + return (-1); } uint32_t rsig = read_uint32(csw, 0); @@ -157,12 +157,12 @@ static int32_t get_usb_mass_storage_status(libusb_device_handle *handle, uint8_t if (rsig != USB_CSW_SIGNATURE) { WLOG("status signature was invalid: %#x\n", rsig); - return(-1); + return (-1); } *tag = rtag; uint8_t rstatus = csw[12]; - return(rstatus); + return (rstatus); } static int32_t dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { @@ -176,7 +176,7 @@ static int32_t dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { sprintf(dbugp, "]\n"); DLOG("%s",dbugblah); - return(0); + return (0); } /** @@ -239,10 +239,10 @@ int32_t send_usb_mass_storage_command(libusb_device_handle *handle, uint8_t endp if (ret != LIBUSB_SUCCESS) { WLOG("sending failed: %d\n", ret); - return(-1); + return (-1); } - return(this_tag); + return (this_tag); } /** @@ -332,7 +332,7 @@ int32_t send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_ if (ret != LIBUSB_SUCCESS) { WLOG("sending failed: %d\n", ret); - return(-1); + return (-1); } // now, swallow up the status, so that things behave nicely... @@ -342,7 +342,7 @@ int32_t send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_ if (status < 0) { WLOG("receiving status failed: %d\n", status); - return(-1); + return (-1); } if (status != 0) { @@ -351,10 +351,10 @@ int32_t send_usb_data_only(libusb_device_handle *handle, unsigned char endpoint_ if (status == 1) { get_sense(handle, endpoint_in, endpoint_out); - return(-1); + return (-1); } - return(real_transferred); + return (real_transferred); } int32_t stlink_q(stlink_t *sl) { @@ -386,7 +386,7 @@ int32_t stlink_q(stlink_t *sl) { if (ret != LIBUSB_SUCCESS) { WLOG("Receiving failed: %d\n", ret); - return(-1); + return (-1); } if (real_transferred != rx_length) { @@ -400,7 +400,7 @@ int32_t stlink_q(stlink_t *sl) { if (status < 0) { WLOG("receiving status failed: %d\n", status); - return(-1); + return (-1); } if (status != 0) { @@ -409,7 +409,7 @@ int32_t stlink_q(stlink_t *sl) { if (status == 1) { get_sense(sg->usb_handle, sg->ep_rep, sg->ep_req); - return(-1); + return (-1); } if (received_tag != tag) { @@ -418,10 +418,10 @@ int32_t stlink_q(stlink_t *sl) { } if (rx_length > 0 && real_transferred != rx_length) { - return(-1); + return (-1); } - return(0); + return (0); } // TODO: thinking, cleanup @@ -448,7 +448,7 @@ int32_t _stlink_sg_version(stlink_t *stl) { sl->cdb_cmd_blk[0] = STLINK_GET_VERSION; stl->q_len = 6; sl->q_addr = 0; - return(stlink_q(stl)); + return (stlink_q(stl)); } // Get stlink mode: @@ -461,9 +461,9 @@ int32_t _stlink_sg_current_mode(stlink_t *stl) { stl->q_len = 2; sl->q_addr = 0; - if (stlink_q(stl)) { return(-1); } + if (stlink_q(stl)) { return (-1); } - return(stl->q_buf[0]); + return (stl->q_buf[0]); } // exit the mass mode and enter the swd debug mode. @@ -473,7 +473,7 @@ int32_t _stlink_sg_enter_swd_mode(stlink_t *sl) { sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_ENTER; sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_SWD; sl->q_len = 0; // >0 -> aboard - return(stlink_q(sl)); + return (stlink_q(sl)); } // exit the mass mode and enter the jtag debug mode. @@ -485,7 +485,7 @@ int32_t _stlink_sg_enter_jtag_mode(stlink_t *sl) { sg->cdb_cmd_blk[1] = STLINK_DEBUG_APIV1_ENTER; sg->cdb_cmd_blk[2] = STLINK_DEBUG_ENTER_JTAG_RESET; sl->q_len = 0; - return(stlink_q(sl)); + return (stlink_q(sl)); } // XXX kernel driver performs reset, the device temporally disappears @@ -497,7 +497,7 @@ int32_t _stlink_sg_exit_dfu_mode(stlink_t *sl) { sg->cdb_cmd_blk[0] = STLINK_DFU_COMMAND; sg->cdb_cmd_blk[1] = STLINK_DFU_EXIT; sl->q_len = 0; // ?? - return(stlink_q(sl)); + return (stlink_q(sl)); /* [135121.844564] sd 19:0:0:0: [sdb] Unhandled error code [135121.844569] sd 19:0:0:0: [sdb] Result: hostbyte=DID_ERROR driverbyte=DRIVER_OK @@ -552,10 +552,10 @@ int32_t _stlink_sg_core_id(stlink_t *sl) { sg->q_addr = 0; ret = stlink_q(sl); - if (ret) { return(ret); } + if (ret) { return (ret); } sl->core_id = read_uint32(sl->q_buf, 0); - return(0); + return (0); } // arm-core reset -> halted state. @@ -566,17 +566,17 @@ int32_t _stlink_sg_reset(stlink_t *sl) { sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } // Reset through AIRCR so NRST does not need to be connected if (stlink_write_debug32(sl, STLINK_REG_AIRCR, STLINK_REG_AIRCR_VECTKEY | \ STLINK_REG_AIRCR_SYSRESETREQ)) { - return(-1); + return (-1); } stlink_stat(sl, "core reset"); - return(0); + return (0); } // arm-core reset -> halted state. @@ -588,11 +588,11 @@ int32_t _stlink_sg_jtag_reset(stlink_t *sl, int32_t value) { sl->q_len = 3; sg->q_addr = 2; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } stlink_stat(sl, "core reset"); - return(0); + return (0); } // arm-core status: halted or running. @@ -602,7 +602,7 @@ int32_t _stlink_sg_status(stlink_t *sl) { sg->cdb_cmd_blk[1] = STLINK_DEBUG_GETSTATUS; sl->q_len = 2; sg->q_addr = 0; - return(stlink_q(sl)); + return (stlink_q(sl)); } // force the core into the debug mode -> halted state. @@ -613,10 +613,10 @@ int32_t _stlink_sg_force_debug(stlink_t *sl) { sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } stlink_stat(sl, "force debug"); - return(0); + return (0); } // read all arm-core registers. @@ -628,7 +628,7 @@ int32_t _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { sl->q_len = 84; sg->q_addr = 0; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } stlink_print_data(sl); @@ -648,7 +648,7 @@ int32_t _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { regp->rw = read_uint32(sl->q_buf, 76); regp->rw2 = read_uint32(sl->q_buf, 80); - if (sl->verbose < 2) { return(0); } + if (sl->verbose < 2) { return (0); } DLOG("xpsr = 0x%08x\n", regp->xpsr); DLOG("main_sp = 0x%08x\n", regp->main_sp); @@ -656,7 +656,7 @@ int32_t _stlink_sg_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("rw = 0x%08x\n", regp->rw); DLOG("rw2 = 0x%08x\n", regp->rw2); - return(0); + return (0); } // read an arm-core register, the index must be in the range 0..20. @@ -671,7 +671,7 @@ int32_t _stlink_sg_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp sl->q_len = 4; sg->q_addr = 0; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } // 0 | 1 | ... | 15 | 16 | 17 | 18 | 19 | 20 // 0-3 | 4-7 | ... | 60-63 | 64-67 | 68-71 | 72-75 | 76-79 | 80-83 @@ -701,7 +701,7 @@ int32_t _stlink_sg_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp regp->r[r_idx] = r; } - return(0); + return (0); } // write an arm-core register. Index: @@ -719,10 +719,10 @@ int32_t _stlink_sg_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } stlink_stat(sl, "write reg"); - return(0); + return (0); } // write a register of the debug module of the core. @@ -752,11 +752,11 @@ int32_t _stlink_sg_run(stlink_t *sl, enum run_type type) { sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } stlink_stat(sl, "run core"); - return(0); + return (0); } // step the arm-core. @@ -767,10 +767,10 @@ int32_t _stlink_sg_step(stlink_t *sl) { sl->q_len = 2; sg->q_addr = 0; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } stlink_stat(sl, "step core"); - return(0); + return (0); } // TODO: test and make delegate! @@ -823,10 +823,10 @@ int32_t _stlink_sg_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { sl->q_len = len; sg->q_addr = addr; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } stlink_print_data(sl); - return(0); + return (0); } // write a "len" bytes from the sl->q_buf to the memory, max 64 Bytes. @@ -845,16 +845,16 @@ int32_t _stlink_sg_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { ret = send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } // This sends the data... ret = send_usb_data_only(sg->usb_handle, sg->ep_req, sg->ep_rep, sl->q_buf, len); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } stlink_print_data(sl); - return(0); + return (0); } // write a "len" bytes from the sl->q_buf to the memory, max Q_BUF_LEN bytes. @@ -873,16 +873,16 @@ int32_t _stlink_sg_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { ret = send_usb_mass_storage_command(sg->usb_handle, sg->ep_req, sg->cdb_cmd_blk, CDB_SL, 0, 0, 0); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } // This sends the data... ret = send_usb_data_only(sg->usb_handle, sg->ep_req, sg->ep_rep, sl->q_buf, len); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } stlink_print_data(sl); - return(0); + return (0); } // write one DWORD data to memory @@ -894,7 +894,7 @@ int32_t _stlink_sg_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { write_uint32(sg->cdb_cmd_blk + 2, addr); write_uint32(sg->cdb_cmd_blk + 6, data); sl->q_len = 2; - return(stlink_q(sl)); + return (stlink_q(sl)); } // read one DWORD data from memory @@ -906,10 +906,10 @@ int32_t _stlink_sg_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { write_uint32(sg->cdb_cmd_blk + 2, addr); sl->q_len = 8; - if (stlink_q(sl)) { return(-1); } + if (stlink_q(sl)) { return (-1); } *data = read_uint32(sl->q_buf, 4); - return(0); + return (0); } // exit the jtag or swd mode and enter the mass mode. @@ -919,10 +919,10 @@ int32_t _stlink_sg_exit_debug_mode(stlink_t *stl) { clear_cdb(sl); sl->cdb_cmd_blk[1] = STLINK_DEBUG_EXIT; stl->q_len = 0; // >0 -> aboard - return(stlink_q(stl)); + return (stlink_q(stl)); } - return(0); + return (0); } // 1) open a sg device, switch the stlink from dfu to mass mode @@ -975,7 +975,7 @@ static stlink_t* stlink_open(const int32_t verbose) { if (slsg != NULL) { free(slsg); } - return(NULL); + return (NULL); } memset(sl, 0, sizeof(stlink_t)); @@ -984,7 +984,7 @@ static stlink_t* stlink_open(const int32_t verbose) { WLOG("failed to init libusb context, wrong version of libraries?\n"); free(sl); free(slsg); - return(NULL); + return (NULL); } #if LIBUSB_API_VERSION < 0x01000106 @@ -1001,7 +1001,7 @@ static stlink_t* stlink_open(const int32_t verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return(NULL); + return (NULL); } // TODO: Could read the interface config descriptor, and assert lots of the assumptions @@ -1015,7 +1015,7 @@ static stlink_t* stlink_open(const int32_t verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return(NULL); + return (NULL); } DLOG("Kernel driver was successfully detached\n"); @@ -1030,7 +1030,7 @@ static stlink_t* stlink_open(const int32_t verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return(NULL); + return (NULL); } @@ -1046,7 +1046,7 @@ static stlink_t* stlink_open(const int32_t verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return(NULL); + return (NULL); } } @@ -1056,7 +1056,7 @@ static stlink_t* stlink_open(const int32_t verbose) { libusb_exit(slsg->libusb_ctx); free(sl); free(slsg); - return(NULL); + return (NULL); } // assumption: endpoint config is fixed mang. really. @@ -1072,7 +1072,7 @@ static stlink_t* stlink_open(const int32_t verbose) { sl->core_stat = TARGET_UNKNOWN; slsg->q_addr = 0; - return(sl); + return (sl); } @@ -1082,24 +1082,24 @@ stlink_t* stlink_v1_open_inner(const int32_t verbose) { if (sl == NULL) { ELOG("Could not open stlink device\n"); - return(NULL); + return (NULL); } stlink_version(sl); if ((sl->version.st_vid != STLINK_USB_VID_ST) || (sl->version.stlink_pid != STLINK_USB_PID_STLINK)) { ELOG("WTF? successfully opened, but unable to read version details. BROKEN!\n"); - return(NULL); + return (NULL); } DLOG("Reading current mode...\n"); switch (stlink_current_mode(sl)) { case STLINK_DEV_MASS_MODE: - return(sl); + return (sl); case STLINK_DEV_DEBUG_MODE: // TODO go to mass? - return(sl); + return (sl); default: ILOG("Current mode unusable, trying to get back to a useful state...\n"); break; @@ -1113,16 +1113,16 @@ stlink_t* stlink_v1_open_inner(const int32_t verbose) { if ((sl->version.st_vid != STLINK_USB_VID_ST) || (sl->version.stlink_pid != STLINK_USB_PID_STLINK)) { ELOG("WTF? successfully opened, but unable to read version details. BROKEN!\n"); - return(NULL); + return (NULL); } - return(sl); + return (sl); } stlink_t* stlink_v1_open(const int32_t verbose, int32_t reset) { stlink_t *sl = stlink_v1_open_inner(verbose); - if (sl == NULL) { return(NULL); } + if (sl == NULL) { return (NULL); } // by now, it _must_ be fully open and in a useful mode.... stlink_enter_swd_mode(sl); @@ -1132,5 +1132,5 @@ stlink_t* stlink_v1_open(const int32_t verbose, int32_t reset) { stlink_load_device_params(sl); ILOG("Successfully opened a stlink v1 debugger\n"); - return(sl); + return (sl); } diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index c2425b6cd..0934fe368 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -30,7 +30,7 @@ #include "register.h" static inline uint32_t le_to_h_u32(const uint8_t* buf) { - return((uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24)); + return ((uint32_t)((uint32_t)buf[0] | (uint32_t)buf[1] << 8 | (uint32_t)buf[2] << 16 | (uint32_t)buf[3] << 24)); } static int32_t _stlink_match_speed_map(const uint32_t *map, uint32_t map_size, uint32_t khz) { @@ -73,7 +73,7 @@ static int32_t _stlink_match_speed_map(const uint32_t *map, uint32_t map_size, u ILOG("Unable to match requested speed %d kHz, using %d kHz\n", khz, map[speed_index]); } - return(speed_index); + return (speed_index); } void _stlink_usb_close(stlink_t* sl) { @@ -101,7 +101,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char if (t) { ELOG("%s send request failed: %s\n", cmd, libusb_error_name(t)); - return(-1); + return (-1); } else if ((size_t)res != txsize) { ELOG("%s send request wrote %u bytes, instead of %u\n", cmd, (uint32_t)res, (uint32_t)txsize); } @@ -111,7 +111,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char if (t) { ELOG("%s read reply failed: %s\n", cmd, libusb_error_name(t)); - return(-1); + return (-1); } /* Checking the command execution status stored in the first byte of the response */ @@ -139,7 +139,7 @@ ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char default: DLOG("%s error (0x%02X)\n", cmd, rxbuf[0]); break; } - return(-1); + return (-1); } if (check_error == CMD_CHECK_REP_LEN && res != (int32_t)rxsize) { @@ -155,20 +155,20 @@ ssize_t send_recv(struct stlink_libusb* handle, int32_t terminate, unsigned char if (t) { ELOG("%s read storage failed: %s\n", cmd, libusb_error_name(t)); - return(-1); + return (-1); } // The STLink doesn't seem to evaluate the sequence number. handle->sg_transfer_idx++; } - return(res); + return (res); } } static inline int32_t send_only(struct stlink_libusb* handle, int32_t terminate, unsigned char* txbuf, uint32_t txsize, const char *cmd) { - return((int32_t)send_recv(handle, terminate, txbuf, txsize, NULL, 0, CMD_CHECK_NO, cmd)); + return ((int32_t)send_recv(handle, terminate, txbuf, txsize, NULL, 0, CMD_CHECK_NO, cmd)); } @@ -190,7 +190,7 @@ static int32_t fill_command(stlink_t * sl, enum SCSI_Generic_Direction dir, uint cmd[i++] = 0; // logical unit cmd[i++] = 0xa; // command length } - return(i); + return (i); } int32_t _stlink_usb_version(stlink_t *sl) { @@ -214,7 +214,7 @@ int32_t _stlink_usb_version(stlink_t *sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_REP_LEN, "GET_VERSION"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_target_voltage(stlink_t *sl) { @@ -232,14 +232,14 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_REP_LEN, "GET_TARGET_VOLTAGE"); if (size < 0) { - return(-1); + return (-1); } factor = (rdata[3] << 24) | (rdata[2] << 16) | (rdata[1] << 8) | (rdata[0] << 0); reading = (rdata[7] << 24) | (rdata[6] << 16) | (rdata[5] << 8) | (rdata[4] << 0); voltage = 2400 * reading / factor; - return(voltage); + return (voltage); } int32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { @@ -256,12 +256,12 @@ int32_t _stlink_usb_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "READDEBUGREG"); if (size < 0) { - return(-1); + return (-1); } *data = read_uint32(rdata, 4); - return(0); + return (0); } int32_t _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { @@ -278,11 +278,11 @@ int32_t _stlink_usb_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { write_uint32(&cmd[i + 4], data); size = send_recv(slu, 1, cmd, slu->cmd_len, rdata, rep_len, CMD_CHECK_RETRY, "WRITEDEBUGREG"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_get_rw_status(stlink_t *sl) { - if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return(0); } + if (sl->version.jtag_api == STLINK_JTAG_API_V1) { return (0); } unsigned char* const rdata = sl->q_buf; struct stlink_libusb * const slu = sl->backend_data; @@ -301,7 +301,7 @@ int32_t _stlink_usb_get_rw_status(stlink_t *sl) { ret = send_recv(slu, 1, cmd, slu->cmd_len, rdata, 2, CMD_CHECK_STATUS, "GETLASTRWSTATUS"); } - return(ret < 0 ? -1 : 0); + return (ret < 0 ? -1 : 0); } int32_t _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -317,13 +317,13 @@ int32_t _stlink_usb_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint16(&cmd[i + 4], len); ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_32BIT"); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } ret = send_only(slu, 1, data, len, "WRITEMEM_32BIT"); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } - return(_stlink_usb_get_rw_status(sl)); + return (_stlink_usb_get_rw_status(sl)); } int32_t _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -345,13 +345,13 @@ int32_t _stlink_usb_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { write_uint16(&cmd[i + 4], len); ret = send_only(slu, 0, cmd, slu->cmd_len, "WRITEMEM_8BIT"); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } ret = send_only(slu, 1, data, len, "WRITEMEM_8BIT"); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } - return(0); + return (0); } int32_t _stlink_usb_current_mode(stlink_t * sl) { @@ -366,10 +366,10 @@ int32_t _stlink_usb_current_mode(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_CURRENT_MODE"); if (size < 0) { - return(-1); + return (-1); } - return(sl->q_buf[0]); + return (sl->q_buf[0]); } int32_t _stlink_usb_core_id(stlink_t * sl) { @@ -393,12 +393,12 @@ int32_t _stlink_usb_core_id(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READ_IDCODES"); if (size < 0) { - return(-1); + return (-1); } sl->core_id = read_uint32(data, offset); - return(0); + return (0); } int32_t _stlink_usb_status_v2(stlink_t *sl) { @@ -420,11 +420,11 @@ int32_t _stlink_usb_status_v2(stlink_t *sl) { } } - return(result); + return (result); } int32_t _stlink_usb_status(stlink_t * sl) { - if (sl->version.jtag_api != STLINK_JTAG_API_V1) { return(_stlink_usb_status_v2(sl)); } + if (sl->version.jtag_api != STLINK_JTAG_API_V1) { return (_stlink_usb_status_v2(sl)); } struct stlink_libusb * const slu = sl->backend_data; unsigned char* const data = sl->q_buf; @@ -449,7 +449,7 @@ int32_t _stlink_usb_status(stlink_t * sl) { sl->core_stat = TARGET_UNKNOWN; } - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_force_debug(stlink_t *sl) { @@ -459,7 +459,7 @@ int32_t _stlink_usb_force_debug(stlink_t *sl) { if (sl->version.jtag_api != STLINK_JTAG_API_V1) { res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_HALT | STLINK_REG_DHCSR_C_DEBUGEN); - return(res); + return (res); } unsigned char* const data = sl->q_buf; @@ -472,7 +472,7 @@ int32_t _stlink_usb_force_debug(stlink_t *sl) { cmd[i++] = STLINK_DEBUG_FORCEDEBUG; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "FORCEDEBUG"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_enter_swd_mode(stlink_t * sl) { @@ -489,7 +489,7 @@ int32_t _stlink_usb_enter_swd_mode(stlink_t * sl) { cmd[i++] = STLINK_DEBUG_ENTER_SWD; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "ENTER_SWD"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_exit_dfu_mode(stlink_t* sl) { @@ -502,7 +502,7 @@ int32_t _stlink_usb_exit_dfu_mode(stlink_t* sl) { cmd[i++] = STLINK_DFU_EXIT; size = send_only(slu, 1, cmd, slu->cmd_len, "DFU_EXIT"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } @@ -525,7 +525,7 @@ int32_t _stlink_usb_reset(stlink_t * sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RESETSYS"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_jtag_reset(stlink_t * sl, int32_t value) { @@ -541,7 +541,7 @@ int32_t _stlink_usb_jtag_reset(stlink_t * sl, int32_t value) { cmd[i++] = value; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "DRIVE_NRST"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } @@ -568,7 +568,7 @@ int32_t _stlink_usb_step(stlink_t* sl) { cmd[i++] = STLINK_DEBUG_STEPCORE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "STEPCORE"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } /** @@ -584,7 +584,7 @@ int32_t _stlink_usb_run(stlink_t* sl, enum run_type type) { if (sl->version.jtag_api != STLINK_JTAG_API_V1) { res = _stlink_usb_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY | STLINK_REG_DHCSR_C_DEBUGEN | ((type==RUN_FLASH_LOADER)?STLINK_REG_DHCSR_C_MASKINTS:0)); - return(res); + return (res); } @@ -598,7 +598,7 @@ int32_t _stlink_usb_run(stlink_t* sl, enum run_type type) { cmd[i++] = STLINK_DEBUG_RUNCORE; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "RUNCORE"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { @@ -641,7 +641,7 @@ int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { cmd[i++] = (clk_divisor >> 8) & 0xFF; size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "SWD_SET_FREQ"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } else if (sl->version.stlink_v == 3) { int32_t speed_index; uint32_t map[STLINK_V3_MAX_FREQ_NB]; @@ -653,7 +653,7 @@ int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, 52, CMD_CHECK_STATUS, "GET_COM_FREQ"); if (size < 0) { - return(-1); + return (-1); } int32_t speeds_size = data[8]; @@ -682,12 +682,12 @@ int32_t _stlink_usb_set_swdclk(stlink_t* sl, int32_t clk_freq) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, 8, CMD_CHECK_STATUS, "SET_COM_FREQ"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } else if (clk_freq) { WLOG("ST-Link firmware does not support frequency setup\n"); } - return(-1); + return (-1); } int32_t _stlink_usb_exit_debug_mode(stlink_t *sl) { @@ -701,7 +701,7 @@ int32_t _stlink_usb_exit_debug_mode(stlink_t *sl) { size = send_only(slu, 1, cmd, slu->cmd_len, "DEBUG_EXIT"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -718,13 +718,13 @@ int32_t _stlink_usb_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, len, CMD_CHECK_NO, "READMEM_32BIT"); if (size < 0) { - return(-1); + return (-1); } sl->q_len = (int32_t)size; stlink_print_data(sl); - return(0); + return (0); } int32_t _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { @@ -746,7 +746,7 @@ int32_t _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "READALLREGS"); if (size < 0) { - return(-1); + return (-1); } /* V1: regs data from offset 0 */ @@ -763,7 +763,7 @@ int32_t _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { regp->rw = read_uint32(sl->q_buf, reg_offset + 76); regp->rw2 = read_uint32(sl->q_buf, reg_offset + 80); - if (sl->verbose < 2) { return(0); } + if (sl->verbose < 2) { return (0); } DLOG("xpsr = 0x%08x\n", regp->xpsr); DLOG("main_sp = 0x%08x\n", regp->main_sp); @@ -771,7 +771,7 @@ int32_t _stlink_usb_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { DLOG("rw = 0x%08x\n", regp->rw); DLOG("rw2 = 0x%08x\n", regp->rw2); - return(0); + return (0); } int32_t _stlink_usb_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { @@ -796,7 +796,7 @@ int32_t _stlink_usb_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *reg size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "READREG"); if (size < 0) { - return(-1); + return (-1); } sl->q_len = (int32_t)size; @@ -824,7 +824,7 @@ int32_t _stlink_usb_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *reg regp->r[r_idx] = r; } - return(0); + return (0); } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ @@ -838,11 +838,11 @@ int32_t _stlink_usb_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stl ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } ret = _stlink_usb_read_mem32(sl, STLINK_REG_DCRDR, 4); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } r = read_uint32(sl->q_buf, 0); DLOG("r_idx (%2d) = 0x%08x\n", r_idx, r); @@ -862,7 +862,7 @@ int32_t _stlink_usb_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stl break; } - return(0); + return (0); } int32_t _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { @@ -870,19 +870,19 @@ int32_t _stlink_usb_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *r ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } ret = _stlink_usb_read_unsupported_reg(sl, 0x21, regp); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } for (int32_t i = 0; i < 32; i++) { ret = _stlink_usb_read_unsupported_reg(sl, 0x40 + i, regp); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } } - return(0); + return (0); } /* See section C1.6 of the ARMv7-M Architecture Reference Manual */ @@ -893,7 +893,7 @@ int32_t _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_ /* These are held in the same register */ ret = _stlink_usb_read_unsupported_reg(sl, 0x14, regp); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } val = (uint8_t)(val >> 24); @@ -931,14 +931,14 @@ int32_t _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_ ret = _stlink_usb_write_mem32(sl, STLINK_REG_DCRDR, 4); - if (ret == -1) { return(ret); } + if (ret == -1) { return (ret); } sl->q_buf[0] = (unsigned char)r_idx; sl->q_buf[1] = 0; sl->q_buf[2] = 0x01; sl->q_buf[3] = 0; - return(_stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4)); + return (_stlink_usb_write_mem32(sl, STLINK_REG_DCRSR, 4)); } int32_t _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { @@ -961,7 +961,7 @@ int32_t _stlink_usb_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { write_uint32(&cmd[i], reg); size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_RETRY, "WRITEREG"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { @@ -979,7 +979,7 @@ int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "START_TRACE_RX"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_disable_trace(stlink_t* sl) { @@ -995,7 +995,7 @@ int32_t _stlink_usb_disable_trace(stlink_t* sl) { size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "STOP_TRACE_RX"); - return(size < 0 ? -1 : 0); + return (size < 0 ? -1 : 0); } int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, uint32_t size) { @@ -1010,10 +1010,10 @@ int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, uint32_t size) { ssize_t send_size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_NO, "GET_TRACE_NB"); if (send_size < 0) { - return(-1); + return (-1); } else if (send_size != 2) { ELOG("STLINK_DEBUG_APIV2_GET_TRACE_NB reply size %d\n", (int32_t)send_size); - return(-1); + return (-1); } uint16_t trace_count = read_uint16(sl->q_buf, 0); @@ -1029,7 +1029,7 @@ int32_t _stlink_usb_read_trace(stlink_t* sl, uint8_t* buf, uint32_t size) { if (t || res != (int32_t)trace_count) { ELOG("read_trace read error %d\n", t); - return(-1); + return (-1); } } @@ -1282,11 +1282,11 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, _stlink_usb_set_swdclk(sl, freq); stlink_target_connect(sl, connect); - return(sl); + return (sl); on_libusb_error: stlink_close(sl); - return(NULL); + return (NULL); on_error: if (slu->libusb_ctx) { libusb_exit(slu->libusb_ctx); } @@ -1295,7 +1295,7 @@ stlink_t *stlink_open_usb(enum ugly_loglevel verbose, enum connect_type connect, if (sl != NULL) { free(sl); } if (slu != NULL) { free(slu); } - return(NULL); + return (NULL); } static uint32_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], enum connect_type connect, int32_t freq) { @@ -1329,7 +1329,7 @@ static uint32_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], if (!_sldevs) { *sldevs = NULL; - return(0); + return (0); } /* Open STLINKS and attach them to list */ @@ -1379,7 +1379,7 @@ static uint32_t stlink_probe_usb_devs(libusb_device **devs, stlink_t **sldevs[], *sldevs = _sldevs; - return(slcur); + return (slcur); } size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t freq) { @@ -1392,11 +1392,11 @@ size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t r = libusb_init(NULL); - if (r < 0) { return(0); } + if (r < 0) { return (0); } cnt = libusb_get_device_list(NULL, &devs); - if (cnt < 0) { return(0); } + if (cnt < 0) { return (0); } slcnt = stlink_probe_usb_devs(devs, &sldevs, connect, freq); libusb_free_device_list(devs, 1); @@ -1405,7 +1405,7 @@ size_t stlink_probe_usb(stlink_t **stdevs[], enum connect_type connect, int32_t *stdevs = sldevs; - return(slcnt); + return (slcnt); } void stlink_probe_usb_free(stlink_t ***stdevs, uint32_t size) { diff --git a/src/win32/getopt/getopt.c b/src/win32/getopt/getopt.c index 417b0aecf..3347da34d 100644 --- a/src/win32/getopt/getopt.c +++ b/src/win32/getopt/getopt.c @@ -118,11 +118,11 @@ int32_t getopt(int32_t argc, char* const argv[], const char* optstring) { if (optcursor == NULL || *++optcursor == '\0') { ++optind; } - return(optchar); + return (optchar); no_more_optchars: optcursor = NULL; - return(-1); + return (-1); } /* Implementation based on http://www.kernel.org/doc/man-pages/online/pages/man3/getopt.3.html */ @@ -141,10 +141,10 @@ int32_t getopt_long(int32_t argc, optarg = NULL; optopt = 0; - if (optind >= argc) { return(-1); } + if (optind >= argc) { return (-1); } if (strlen(argv[optind]) < 3 || strncmp(argv[optind], "--", 2) != 0) { - return(getopt(argc, argv, optstring)); + return (getopt(argc, argv, optstring)); } // it's an option; starts with -- and is longer than two chars @@ -198,5 +198,5 @@ int32_t getopt_long(int32_t argc, } ++optind; - return(retval); + return (retval); } diff --git a/src/win32/mmap.c b/src/win32/mmap.c index 7e76b3344..8bddb5094 100644 --- a/src/win32/mmap.c +++ b/src/win32/mmap.c @@ -10,30 +10,30 @@ void *mmap (void *addr, uint32_t len, int32_t prot, int32_t flags, int32_t fd, i void *buf; ssize_t count; - if ( addr || fd == -1 || (prot & PROT_WRITE)) { return(MAP_FAILED); } + if ( addr || fd == -1 || (prot & PROT_WRITE)) { return (MAP_FAILED); } buf = malloc(len); - if ( NULL == buf ) { return(MAP_FAILED); } + if ( NULL == buf ) { return (MAP_FAILED); } if (lseek(fd, offset, SEEK_SET) != offset) { free(buf); - return(MAP_FAILED); + return (MAP_FAILED); } count = read(fd, buf, len); if (count != (ssize_t)len) { free (buf); - return(MAP_FAILED); + return (MAP_FAILED); } - return(buf); + return (buf); (void)flags; } int32_t munmap (void *addr, uint32_t len) { free (addr); - return(0); + return (0); (void)len; } diff --git a/src/win32/sys_time.c b/src/win32/sys_time.c index a09d8df67..f1ebd63b9 100644 --- a/src/win32/sys_time.c +++ b/src/win32/sys_time.c @@ -12,7 +12,7 @@ int32_t gettimeofday(struct timeval *tv, struct timezone *tz) { ULARGE_INTEGER ulint; static int32_t tzflag = 0; - if(NULL != tv) { + if (NULL != tv) { GetSystemTimeAsFileTime(&ftime); ulint.LowPart = ftime.dwLowDateTime; ulint.HighPart = ftime.dwHighDateTime; @@ -21,7 +21,7 @@ int32_t gettimeofday(struct timeval *tv, struct timezone *tz) { tv->tv_usec = (int32_t)(ulint.QuadPart % 10000000L); } - if(NULL != tz) { + if (NULL != tz) { if (!tzflag) { _tzset(); tzflag++; diff --git a/src/win32/win32_socket.c b/src/win32/win32_socket.c index 46b4532a7..d3038882b 100644 --- a/src/win32/win32_socket.c +++ b/src/win32/win32_socket.c @@ -68,7 +68,7 @@ int32_t win32_poll(struct pollfd *fds, uint32_t nfds, int32_t timo) { printf("Exiting select rc=%d\n", rc); #endif - if (rc <= 0) { return(rc); } + if (rc <= 0) { return (rc); } if (rc > 0) { for ( i = 0; i < nfds; ++i) { @@ -98,7 +98,7 @@ int32_t win32_poll(struct pollfd *fds, uint32_t nfds, int32_t timo) { } } - return(rc); + return (rc); } static void set_connect_errno(int32_t winsock_err) { @@ -135,7 +135,7 @@ SOCKET win32_socket(int32_t domain, int32_t type, int32_t protocol) { if (fd == INVALID_SOCKET) { set_socket_errno(WSAGetLastError()); } - return(fd); + return (fd); } /* @@ -149,7 +149,7 @@ int32_t win32_connect(SOCKET fd, struct sockaddr *addr, socklen_t addr_len) { if (rc == SOCKET_ERROR) { set_connect_errno(WSAGetLastError()); } - return(rc); + return (rc); } /* A wrapper around the accept() function. @@ -164,7 +164,7 @@ SOCKET win32_accept(SOCKET fd, struct sockaddr *addr, socklen_t *addr_len) { newfd = (SOCKET)-1; } - return(newfd); + return (newfd); } /* A wrapper around the shutdown() function. @@ -177,7 +177,7 @@ int32_t win32_shutdown(SOCKET fd, int32_t mode) { if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } - return(rc); + return (rc); } int32_t win32_close_socket(SOCKET fd) { @@ -185,7 +185,7 @@ int32_t win32_close_socket(SOCKET fd) { if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } - return(rc); + return (rc); } ssize_t win32_write_socket(SOCKET fd, void *buf, int32_t n) { @@ -193,7 +193,7 @@ ssize_t win32_write_socket(SOCKET fd, void *buf, int32_t n) { if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } - return(rc); + return (rc); } ssize_t win32_read_socket(SOCKET fd, void *buf, int32_t n) { @@ -201,7 +201,7 @@ ssize_t win32_read_socket(SOCKET fd, void *buf, int32_t n) { if (rc == SOCKET_ERROR) { set_socket_errno(WSAGetLastError()); } - return(rc); + return (rc); } @@ -244,7 +244,7 @@ char * win32_strtok_r(char *s, const char *delim, char **lasts) { } *lasts = s; - return(tok); + return (tok); } } while (sc != 0); @@ -260,7 +260,7 @@ char *win32_strsep (char **stringp, const char *delim) { char *tok; if ((s = *stringp) == NULL) { - return(NULL); + return (NULL); } for (tok = s; ;) { @@ -276,7 +276,7 @@ char *win32_strsep (char **stringp, const char *delim) { } *stringp = s; - return(tok); + return (tok); } } while (sc != 0); @@ -301,7 +301,7 @@ int32_t usleep(uint32_t waitTime) { WaitForSingleObject(timer, INFINITE); CloseHandle(timer); - return(0); + return (0); } LARGE_INTEGER perf_cnt, start, now; @@ -313,7 +313,7 @@ int32_t usleep(uint32_t waitTime) { QueryPerformanceCounter((LARGE_INTEGER*)&now); } while ((now.QuadPart - start.QuadPart) / (float)perf_cnt.QuadPart * 1000 * 1000 < waitTime); - return(0); + return (0); } #endif diff --git a/tests/flash.c b/tests/flash.c index f4c838d5d..4d9ac5185 100644 --- a/tests/flash.c +++ b/tests/flash.c @@ -49,7 +49,7 @@ static bool execute_test(const struct Test * test) { strcpy(cmd_line, test->cmd_line); for (char * tok = strtok(cmd_line, " "); tok; tok = strtok(NULL, " ")) { - if ((size_t)ac >= sizeof(av) / sizeof(av[0])) return(false); + if ((size_t)ac >= sizeof(av) / sizeof(av[0])) return (false); av[ac] = tok; ++ac; @@ -75,7 +75,7 @@ static bool execute_test(const struct Test * test) { } printf("[%s] (%d) %s\n", ret ? "OK" : "ERROR", res, test->cmd_line); - return(ret); + return (ret); } static struct Test tests[] = { diff --git a/tests/sg.c b/tests/sg.c index 6881266ab..67d804b23 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -44,7 +44,7 @@ int32_t main(void) { // main() ripped out of old stlink-hw.c stlink_t *sl = stlink_v1_open(99, 1); - if (sl == NULL) return(0); + if (sl == NULL) return (0); // we are in mass mode, go to swd stlink_enter_swd_mode(sl); @@ -212,5 +212,5 @@ int32_t main(void) { // main() ripped out of old stlink-hw.c // fflush(stderr); // fflush(stdout); - return(EXIT_SUCCESS); + return (EXIT_SUCCESS); } diff --git a/tests/usb.c b/tests/usb.c index 9acd0b02d..5dbb1d83c 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -29,7 +29,7 @@ int32_t main(int32_t ac, char** av) { if (reset == 0) { usage(); - return(0); + return (0); } sl = stlink_open_usb(10, reset, NULL, 0); @@ -125,5 +125,5 @@ int32_t main(int32_t ac, char** av) { stlink_close(sl); } - return(0); + return (0); } From 041517bd4a8caf7dbf17b0c7d8004272cbaefa43 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 25 Jun 2023 15:31:13 +0200 Subject: [PATCH 1389/1435] Fixed flashing on STM32G0/G4 dual bank devices (Closes #1310) --- src/stlink-lib/common_flash.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index f2281ac11..885be9c74 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -307,6 +307,9 @@ int32_t check_flash_error(stlink_t *sl) { case STM32_FLASH_TYPE_G0: case STM32_FLASH_TYPE_G4: res = read_flash_sr(sl, BANK_1) & FLASH_Gx_SR_ERROR_MASK; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + res |= read_flash_sr(sl, BANK_2) & FLASH_Gx_SR_ERROR_MASK; + } WRPERR = (1 << FLASH_Gx_SR_WRPERR); PROGERR = (1 << FLASH_Gx_SR_PROGERR); PGAERR = (1 << FLASH_Gx_SR_PGAERR); @@ -1013,10 +1016,8 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if ((val & (1 << 0)) || (val & (1 << 1))) { // disable pecr protection - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY1); - stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, - FLASH_L0_PEKEY2); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY1); + stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, FLASH_L0_PEKEY2); // check pecr.pelock is cleared stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); @@ -1118,8 +1119,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { clear_flash_cr_pg(sl, bank); // clear the pg bit set_flash_cr_per(sl, bank); // set the page erase bit write_flash_ar(sl, flashaddr, bank); // select the page to erase - set_flash_cr_strt(sl, - bank); // start erase operation, reset by hw with busy bit + set_flash_cr_strt(sl, bank); // start erase operation, reset by hw with busy bit wait_flash_busy(sl); clear_flash_cr_per(sl, bank); // clear the page erase bit lock_flash(sl); @@ -1180,7 +1180,7 @@ int32_t stlink_erase_flash_section(stlink_t *sl, stm32_addr_t base_addr, uint32_ int32_t stlink_erase_flash_mass(stlink_t *sl) { int32_t err = 0; - // TODO: User MER bit to mass-erase WB series. + // TODO: Use MER bit to mass-erase WB series. if (sl->flash_type == STM32_FLASH_TYPE_L0_L1 || sl->flash_type == STM32_FLASH_TYPE_WB_WL) { @@ -1193,15 +1193,14 @@ int32_t stlink_erase_flash_mass(stlink_t *sl) { if (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_id != STM32_CHIPID_H7Ax) { // set parallelism - write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); + write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_1); if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); } } set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit - set_flash_cr_strt( - sl, BANK_1); // start erase operation, reset by hw with busy bit + set_flash_cr_strt(sl, BANK_1); // start erase operation, reset by hw with busy bit if (sl->flash_type == STM32_FLASH_TYPE_F1_XL || (sl->flash_type == STM32_FLASH_TYPE_H7 && sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { @@ -1246,8 +1245,7 @@ int32_t stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, stm32_ num_empty -= (num_empty & 3); // Round down to words if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, - erased_pattern); + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); } } else { num_empty = 0; @@ -1300,8 +1298,7 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { num_empty -= (num_empty & 3); // round down to words if (num_empty != 0) { - ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, - erased_pattern); + ILOG("Ignoring %d bytes of 0x%02x at end of file\n", num_empty, erased_pattern); } } else { num_empty = 0; From 8fad9be9d0b055069b3f4fcdc3dc17014a6ce9cb Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 25 Jun 2023 15:45:33 +0200 Subject: [PATCH 1390/1435] [refactoring] Clean-up for stlink-lib - Moved declarations for read/write functions to read_write.h . - Checked & revised header includes - Changed some datatypes for write_buffer_to_sram() to avoid explicit casting. --- SECURITY.md | 2 +- inc/stlink.h | 24 +++---------- src/st-trace/trace.c | 1 + src/st-util/gdb-server.c | 1 + src/st-util/semihosting.c | 3 +- src/stlink-gui/gui.c | 1 + src/stlink-lib/calculate.c | 1 + src/stlink-lib/common.c | 11 +++--- src/stlink-lib/common_flash.c | 1 + src/stlink-lib/flash_loader.c | 1 + src/stlink-lib/map_file.c | 2 ++ src/stlink-lib/option_bytes.c | 1 + src/stlink-lib/read_write.c | 67 +++++++++++++++++++---------------- src/stlink-lib/read_write.h | 27 ++++++++++++++ src/stlink-lib/sg.c | 1 + src/stlink-lib/usb.c | 1 + tests/sg.c | 1 + tests/usb.c | 1 + 18 files changed, 90 insertions(+), 57 deletions(-) create mode 100644 src/stlink-lib/read_write.h diff --git a/SECURITY.md b/SECURITY.md index 9ace47066..054641822 100644 --- a/SECURITY.md +++ b/SECURITY.md @@ -7,7 +7,7 @@ The following versions of the stlink toolset are currently being supported.
      #include +#include #include #include diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 8a187fb24..d001395e9 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include diff --git a/src/st-util/semihosting.c b/src/st-util/semihosting.c index a200a7408..8e9828ce8 100644 --- a/src/st-util/semihosting.c +++ b/src/st-util/semihosting.c @@ -8,9 +8,10 @@ #include #include +#include "semihosting.h" #include -#include "semihosting.h" +#include static int32_t mem_read_u8(stlink_t *sl, uint32_t addr, uint8_t *data) { int32_t offset = addr % 4; diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index 4b312c8a1..e3eec34b8 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -9,6 +9,7 @@ #include #include +#include #include #define MEM_READ_SIZE 1024 diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index 027239694..a7344e0b0 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -10,6 +10,7 @@ #include "calculate.h" #include "common_flash.h" +#include "read_write.h" uint32_t calculate_F4_sectornum(uint32_t flashaddr) { uint32_t offset = 0; diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 70ecdd3a2..dbfcc8b9e 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -25,6 +25,7 @@ #include "logging.h" #include "map_file.h" #include "md5.h" +#include "read_write.h" #include "register.h" #include "usb.h" @@ -808,20 +809,20 @@ int32_t stlink_fread(stlink_t *sl, const char *path, bool is_ihex, stm32_addr_t } // 300 -int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, uint32_t size) { +int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, uint16_t size) { // write the buffer right after the loader int32_t ret = 0; - uint32_t chunk = size & ~0x3; - uint32_t rem = size & 0x3; + uint16_t chunk = size & ~0x3; + uint16_t rem = size & 0x3; if (chunk) { memcpy(sl->q_buf, buf, chunk); - ret = stlink_write_mem32(sl, fl->buf_addr, (uint16_t)chunk); + ret = stlink_write_mem32(sl, fl->buf_addr, chunk); } if (rem && !ret) { memcpy(sl->q_buf, buf + chunk, rem); - ret = stlink_write_mem8(sl, (fl->buf_addr) + chunk, (uint16_t)rem); + ret = stlink_write_mem8(sl, (fl->buf_addr) + chunk, rem); } return (ret); diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 885be9c74..3038b53e7 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -18,6 +18,7 @@ #include "logging.h" #include "map_file.h" #include "md5.h" +#include "read_write.h" #define DEBUG_FLASH 0 diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 0f12c3131..e1e9e9995 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -16,6 +16,7 @@ #include "common_flash.h" #include "helper.h" #include "logging.h" +#include "read_write.h" #include "register.h" #define FLASH_REGS_BANK2_OFS 0x40 diff --git a/src/stlink-lib/map_file.c b/src/stlink-lib/map_file.c index e8c4b71a3..118c80d34 100644 --- a/src/stlink-lib/map_file.c +++ b/src/stlink-lib/map_file.c @@ -15,6 +15,8 @@ #include #include "map_file.h" +#include "read_write.h" + #ifndef O_BINARY #define O_BINARY 0 #endif diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index c84ace348..ee03dced9 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -16,6 +16,7 @@ #include "logging.h" #include "map_file.h" #include "md5.h" +#include "read_write.h" /** * Read option control register F0 diff --git a/src/stlink-lib/read_write.c b/src/stlink-lib/read_write.c index 9149080af..4e43d8aa5 100644 --- a/src/stlink-lib/read_write.c +++ b/src/stlink-lib/read_write.c @@ -1,8 +1,15 @@ +/* + * File: read_write.c + * + * Read and write operations + */ + #include #include #include #include +#include "read_write.h" #include "logging.h" @@ -10,11 +17,8 @@ // https://commandcenter.blogspot.com/2012/04/byte-order-fallacy.html // These functions encode and decode little endian uint16 and uint32 values. -void write_uint32(unsigned char *buf, uint32_t ui) { - buf[0] = ui; - buf[1] = ui >> 8; - buf[2] = ui >> 16; - buf[3] = ui >> 24; +uint16_t read_uint16(const unsigned char *c, const int32_t pt) { + return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); } void write_uint16(unsigned char *buf, uint16_t ui) { @@ -27,8 +31,11 @@ uint32_t read_uint32(const unsigned char *c, const int32_t pt) { ((uint32_t)c[pt + 2] << 16) | ((uint32_t)c[pt + 3] << 24); } -uint16_t read_uint16(const unsigned char *c, const int32_t pt) { - return ((uint16_t)c[pt]) | ((uint16_t)c[pt + 1] << 8); +void write_uint32(unsigned char *buf, uint32_t ui) { + buf[0] = ui; + buf[1] = ui >> 8; + buf[2] = ui >> 16; + buf[3] = ui >> 24; } int32_t stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { @@ -46,26 +53,26 @@ int32_t stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { return sl->backend->write_debug32(sl, addr, data); } -int32_t stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); +int32_t stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_read_mem32 ***\n"); - if (len % 4 != 0) { + if (len % 4 != 0) { // !!! never ever: fw gives just wrong values ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); return (-1); } - return (sl->backend->write_mem32(sl, addr, len)); + return (sl->backend->read_mem32(sl, addr, len)); } -int32_t stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_read_mem32 ***\n"); +int32_t stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { + DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); - if (len % 4 != 0) { // !!! never ever: fw gives just wrong values + if (len % 4 != 0) { ELOG("Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); return (-1); } - return (sl->backend->read_mem32(sl, addr, len)); + return (sl->backend->write_mem32(sl, addr, len)); } int32_t stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { @@ -73,21 +80,6 @@ int32_t stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { return (sl->backend->write_mem8(sl, addr, len)); } -int32_t stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_regs ***\n"); - return (sl->backend->read_all_regs(sl, regp)); -} - -int32_t stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { - DLOG("*** stlink_read_all_unsupported_regs ***\n"); - return (sl->backend->read_all_unsupported_regs(sl, regp)); -} - -int32_t stlink_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { - DLOG("*** stlink_write_reg\n"); - return (sl->backend->write_reg(sl, reg, idx)); -} - int32_t stlink_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { DLOG("*** stlink_read_reg\n"); DLOG(" (%d) ***\n", r_idx); @@ -100,6 +92,11 @@ int32_t stlink_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { return (sl->backend->read_reg(sl, r_idx, regp)); } +int32_t stlink_write_reg(stlink_t *sl, uint32_t reg, int32_t idx) { + DLOG("*** stlink_write_reg\n"); + return (sl->backend->write_reg(sl, reg, idx)); +} + int32_t stlink_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp) { int32_t r_convert; @@ -145,3 +142,13 @@ int32_t stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int32_t r_idx, return (sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); } + +int32_t stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { + DLOG("*** stlink_read_all_regs ***\n"); + return (sl->backend->read_all_regs(sl, regp)); +} + +int32_t stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { + DLOG("*** stlink_read_all_unsupported_regs ***\n"); + return (sl->backend->read_all_unsupported_regs(sl, regp)); +} diff --git a/src/stlink-lib/read_write.h b/src/stlink-lib/read_write.h new file mode 100644 index 000000000..b9ca082c8 --- /dev/null +++ b/src/stlink-lib/read_write.h @@ -0,0 +1,27 @@ +/* + * File: read_write.h + * + * Read and write operations + */ + +#ifndef READ_WRITE_H +#define READ_WRITE_H + +uint16_t read_uint16(const unsigned char *c, const int32_t pt); +void write_uint16(unsigned char *buf, uint16_t ui); +uint32_t read_uint32(const unsigned char *c, const int32_t pt); +void write_uint32(unsigned char *buf, uint32_t ui); + +int32_t stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data); +int32_t stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data); +int32_t stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len); +int32_t stlink_read_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t stlink_write_reg(stlink_t *sl, uint32_t reg, int32_t idx); +int32_t stlink_read_unsupported_reg(stlink_t *sl, int32_t r_idx, struct stlink_reg *regp); +int32_t stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int32_t r_idx, struct stlink_reg *regp); +int32_t stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp); +int32_t stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp); + +#endif // READ_WRITE_H diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index b744389ba..d9bd8ab6a 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -95,6 +95,7 @@ #include "commands.h" #include "logging.h" +#include "read_write.h" #include "register.h" #include "usb.h" // #include // TODO: Check use diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 0934fe368..30134e161 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -27,6 +27,7 @@ #include "commands.h" #include "logging.h" +#include "read_write.h" #include "register.h" static inline uint32_t le_to_h_u32(const uint8_t* buf) { diff --git a/tests/sg.c b/tests/sg.c index 67d804b23..1284bb15b 100644 --- a/tests/sg.c +++ b/tests/sg.c @@ -8,6 +8,7 @@ #include #include +#include #include #if defined(_MSC_VER) diff --git a/tests/usb.c b/tests/usb.c index 5dbb1d83c..f8b60c306 100644 --- a/tests/usb.c +++ b/tests/usb.c @@ -6,6 +6,7 @@ #include +#include #include #include From 2f27e8ec98db7dcba9437aae3c6e33e90ca3b674 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 27 Jun 2023 08:24:09 +0200 Subject: [PATCH 1391/1435] Fixed chip recovery after reset (Closes #1260) --- src/st-flash/flash.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index ba6d1f4bb..0577ee179 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -287,10 +287,9 @@ int32_t main(int32_t ac, char** av) { } } - if (o.reset) { - stlink_reset(sl, RESET_AUTO); - stlink_run(sl, RUN_NORMAL); - } + if (o.reset) stlink_reset(sl, RESET_AUTO); + + stlink_run(sl, RUN_NORMAL); err = 0; // success From 457d971a40e8882765baaea1fa4015489825b09f Mon Sep 17 00:00:00 2001 From: Meo Date: Mon, 3 Jul 2023 09:59:26 +0800 Subject: [PATCH 1392/1435] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 6d188f0df..80d39a28a 100644 --- a/README.md +++ b/README.md @@ -74,7 +74,7 @@ We recommend to install `stlink-tools` from the package repository of the used d - Debian Linux: [(Link)](https://github.com/stlink-org/stlink/releases) - Ubuntu Linux: [(Link)](https://github.com/stlink-org/stlink/releases) -- Arch Linux: [(Link)](https://www.archlinux.org/packages/community/x86_64/stlink) +- Arch Linux: [(Link)](https://archlinux.org/packages/extra/x86_64/stlink/) - Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) - Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) - FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) From 682ec389b720f164c42aafe1b0d7614abc29a12f Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 9 Jul 2023 00:38:49 +0200 Subject: [PATCH 1393/1435] [doc] Corrected compiling manual (Closes #1317) --- doc/compiling.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/compiling.md b/doc/compiling.md index 775d2363e..45cf38aa1 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -125,7 +125,7 @@ or execute (Debian-based systems only): `apt-get install gcc build-essential cma 4. Run `make install` to full install the package with complete system integration. This might require sudo permissions. 5. Run `make debug` to create the _Debug_ target (_optional_)
      The debug target is only necessary in order to modify the sources and to run under a debugger. -6. Run `make package`to build a Debian Package. The generated packages can be found in the subdirectory `./build/dist`. +6. Run `make package`to build a Debian Package. The generated packages can be found in the subdirectory `./build/Release/dist`. As an option you may also install to an individual user-defined folder e.g `$HOME` with `make install DESTDIR=$HOME`. From 4b69bdd3e95f7077991d198550aaa76405e54ce4 Mon Sep 17 00:00:00 2001 From: Martin Mares Date: Tue, 15 Aug 2023 10:44:18 +0200 Subject: [PATCH 1394/1435] CMake: Avoid hard-wired /usr/local/share Instead of defining own CMAKE_INSTALL_SHAREDIR, use existing CMAKE_INSTALL_FULL_DATADIR. This way, CMAKE_INSTALL_PREFIX is respected. --- CMakeLists.txt | 5 +---- src/stlink-gui/CMakeLists.txt | 8 ++++---- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 7e7d92705..31825945f 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -78,9 +78,6 @@ include(GNUInstallDirs) # Define GNU standard installation directories cmake_host_system_information(RESULT OS_NAME QUERY OS_NAME) message(STATUS "Checking for OS_NAME: ${OS_NAME}") -message(STATUS "set(CMAKE_INSTALL_SHAREDIR /usr/local/share)") -set(CMAKE_INSTALL_SHAREDIR /usr/local/share/) - ## Set C build flags if (NOT MSVC) @@ -385,7 +382,7 @@ endif () if (WIN32) set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_PREFIX}/config/chips) else () -set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}/chips) +set(CMAKE_CHIPS_DIR ${CMAKE_INSTALL_FULL_DATADIR}/${PROJECT_NAME}/chips) endif () add_definitions( -DSTLINK_CHIPS_DIR="${CMAKE_CHIPS_DIR}" ) file(GLOB CHIP_FILES ${CMAKE_SOURCE_DIR}/config/chips/*.chip) diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index fb4478bdc..f9b6c3fb9 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -16,19 +16,19 @@ if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) # Install desktop application entry install(FILES stlink-gui.desktop - DESTINATION ${CMAKE_INSTALL_SHAREDIR}/applications) + DESTINATION ${CMAKE_INSTALL_FULL_DATADIR}/applications) # Install icons install(FILES icons/stlink-gui.svg - DESTINATION ${CMAKE_INSTALL_SHAREDIR}/icons/hicolor/scalable/apps) + DESTINATION ${CMAKE_INSTALL_FULL_DATADIR}/icons/hicolor/scalable/apps) set(GUI_SOURCES gui.c gui.h) ## stlink-gui add_executable(stlink-gui ${GUI_SOURCES}) - install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}) + install(FILES stlink-gui.ui DESTINATION ${CMAKE_INSTALL_FULL_DATADIR}/${PROJECT_NAME}) set_target_properties(stlink-gui PROPERTIES - COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_SHAREDIR}/${PROJECT_NAME}") + COMPILE_DEFINITIONS STLINK_UI_DIR="${CMAKE_INSTALL_FULL_DATADIR}/${PROJECT_NAME}") target_link_libraries(stlink-gui ${STLINK_LIB_SHARED} ${SSP_LIB} ${GTK3_LDFLAGS}) install(TARGETS stlink-gui DESTINATION ${CMAKE_BINDIR}) endif () From 270efb3535a968ec639dfe5d20bb69462ab71fd6 Mon Sep 17 00:00:00 2001 From: ArmoredPony Date: Wed, 16 Aug 2023 18:05:37 +0400 Subject: [PATCH 1395/1435] fixed unknown option -u --- src/st-util/gdb-server.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 9f9d93844..629eb4c6f 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -149,7 +149,7 @@ int32_t parse_options(int32_t argc, char** argv, st_state_t *st) { int32_t c; int32_t q; - while ((c = getopt_long(argc, argv, "hv::p:mn", long_options, &option_index)) != -1) + while ((c = getopt_long(argc, argv, "hv::p:mnu", long_options, &option_index)) != -1) switch (c) { case 0: break; From 2e6cf7d806cf8ec0a88c88119e5d69bf4f67e564 Mon Sep 17 00:00:00 2001 From: andrew Date: Sun, 27 Aug 2023 01:45:57 -0700 Subject: [PATCH 1396/1435] Fix use of uninitialized flash_loader_t in stm32l1_write_half_pages stm32l1_write_half_pages uses a local flash_loader_t that is never initialized. This results in stlink_flash_loader_run using uninitialized values for fl->buf_addr and fl->loader_addr when copying the buffer and initializing the source register and PC before running the core to execute the flashloader. Pass the flash_loader_t from stlink_flashloader_write through to stm32l1_write_half_pages and use that one instead of an uninitialized local structure. --- src/stlink-lib/flash_loader.c | 7 +++---- src/stlink-lib/flash_loader.h | 2 +- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 0ab8cf6c1..94a0dc41f 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -428,12 +428,11 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t #define L1_WRITE_BLOCK_SIZE 0x80 #define L0_WRITE_BLOCK_SIZE 0x40 -int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize) { +int32_t stm32l1_write_half_pages(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize) { uint32_t count, off; uint32_t num_half_pages = len / pagesize; uint32_t val; uint32_t flash_regs_base = get_stm32l0_flash_base(sl); - flash_loader_t fl; bool use_loader = true; int32_t ret = 0; @@ -448,7 +447,7 @@ int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, for (count = 0; count < num_half_pages; count++) { if (use_loader) { - ret = stlink_flash_loader_run(sl, &fl, addr + count * pagesize, base + count * pagesize, pagesize); + ret = stlink_flash_loader_run(sl, fl, addr + count * pagesize, base + count * pagesize, pagesize); if (ret && count == 0) { /* It seems that stm32lx devices have a problem when it is blank */ WLOG("Failed to use flash loader, fallback to soft write\n"); @@ -770,7 +769,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t off = 0; if (len > pagesize) { - if (stm32l1_write_half_pages(sl, addr, base, len, pagesize)) { + if (stm32l1_write_half_pages(sl, fl, addr, base, len, pagesize)) { return (-1); } else { off = (size_t)(len / pagesize) * pagesize; diff --git a/src/stlink-lib/flash_loader.h b/src/stlink-lib/flash_loader.h index 33edc7ac6..6ac2e4f80 100644 --- a/src/stlink-lib/flash_loader.h +++ b/src/stlink-lib/flash_loader.h @@ -18,7 +18,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t /* === Functions from old header file flashloader.h === */ -int32_t stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize); +int32_t stm32l1_write_half_pages(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint32_t pagesize); // static void set_flash_cr_pg(stlink_t *sl, uint32_t bank); // static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr); int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl); From 1861b8dc9f7e70f4034bddabfe3b1e112dcd483f Mon Sep 17 00:00:00 2001 From: andrew Date: Sun, 27 Aug 2023 11:01:45 -0700 Subject: [PATCH 1397/1435] Fix stm32lx flash loader on STM32L0 STM32L0 chips use loader_code_stm32lx, but this flash loader is built for armv7-m and uses instructions that are unsupported on STM32L0 (which have Cortex M0+ cores implementing armv6-m). In particular, loader_code_stm32lx uses variants of add-immediate that do not update the condition flags ( `add r0, r0, #4` ). These are 32bit instructions in armv7-m and are not available in armv6-m. Enable loader_code_stm32lx to run on both armv6-m and armv7-m by building for armv6-m, which requires changing the `add` instructions to `adds` instructions that do update condition flags (which is ok because the subs updates the condition flags again before the branch). --- flashloaders/Makefile | 5 +++++ flashloaders/stm32lx.s | 4 ++-- src/stlink-lib/flash_loader.c | 8 ++++---- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/flashloaders/Makefile b/flashloaders/Makefile index 68ce5a881..73080c644 100644 --- a/flashloaders/Makefile +++ b/flashloaders/Makefile @@ -30,6 +30,11 @@ stm32f0.o: stm32f0.s stm32vl.o: stm32f0.s $(CC) stm32f0.s $(CFLAGS_ARMV7_M) -o stm32vl.o +# separate rule for STM32Lx. +# Built for ARMv6-M target to be compatible with both Cortex M0 and Cortex M3. +stm32lx.o: stm32lx.s + $(CC) stm32lx.s $(CFLAGS_ARMV6_M) -o stm32lx.o + # generic rule for all other ARMv7-M %.o: %.s $(CC) $< $(CFLAGS_ARMV7_M) -o $@ diff --git a/flashloaders/stm32lx.s b/flashloaders/stm32lx.s index 69acdea7b..263f1f829 100644 --- a/flashloaders/stm32lx.s +++ b/flashloaders/stm32lx.s @@ -17,8 +17,8 @@ loop: str r4, [r1] # increment address - add r0, r0, #4 - add r1, r1, #4 + adds r0, r0, #4 + adds r1, r1, #4 # loop if count > 0 subs r2, r2, #4 diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 94a0dc41f..040a7ab09 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -68,12 +68,12 @@ static const uint8_t loader_code_stm32f0[] = { 0x14, 0x00, 0x00, 0x00 }; -// flashloaders/stm32lx.s +// flashloaders/stm32lx.s -- compiled for armv6-m for compatibility with both +// armv6-m cores (STM32L0) and armv7-m cores (STM32L1) static const uint8_t loader_code_stm32lx[] = { 0x04, 0x68, 0x0c, 0x60, - 0x00, 0xf1, 0x04, 0x00, - 0x01, 0xf1, 0x04, 0x01, - 0x04, 0x3a, 0xf7, 0xdc, + 0x04, 0x30, 0x04, 0x31, + 0x04, 0x3a, 0xf9, 0xdc, 0x00, 0xbe, 0x00, 0x00 }; From 7475ec7f30edcff72b7c38cc221b29aaefe93220 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 2 Sep 2023 17:18:09 +0200 Subject: [PATCH 1398/1435] General Project Update - Updated CHANGELOG.md - Updated README.md - Minor fixes & updates in documentation. --- CHANGELOG.md | 9 ++- README.md | 7 ++- SECURITY.md | 2 +- doc/compiling.md | 2 + flashloaders/cleanroom.md | 125 ++------------------------------------ 5 files changed, 22 insertions(+), 123 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index c930999cd..9b6cccdf9 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -37,6 +37,7 @@ Updates & changes: - [refactoring] General maintenance for code structure ([#903](https://github.com/stlink-org/stlink/pull/903), [#1090](https://github.com/stlink-org/stlink/pull/1090), [#1199](https://github.com/stlink-org/stlink/pull/1199), [#1212](https://github.com/stlink-org/stlink/pull/1212), [#1216](https://github.com/stlink-org/stlink/pull/1216), [#1228](https://github.com/stlink-org/stlink/pull/1228)) - Added instructions for bug-reports and feature-requests to contribution guidelines ([#906](https://github.com/stlink-org/stlink/pull/906)) - Added travis CI configuration for macOS 10.14 to maintain capability for 32-bit compilation (commit [#f5ada94](https://github.com/stlink-org/stlink/commit/f5ada9474cdb87ff37de0d4eb9e75622b5870646)) +- [refactoring] Clean code with unified variable type ([#909](https://github.com/stlink-org/stlink/pull/909), commit [#5e85fd0](https://github.com/stlink-org/stlink/commit/5e85fd063908f89499180c28fe5e9ba74868b272)) - Updated description of chip id 0x0457 to L01x/L02x ([#1143](https://github.com/stlink-org/stlink/pull/1143), [#1144](https://github.com/stlink-org/stlink/pull/1144)) - [doc] Human-readable flash_type in chip-id files ([#1155](https://github.com/stlink-org/stlink/pull/1155), commit [#1745bf5](https://github.com/stlink-org/stlink/commit/1745bf5193c4d3186d4f6fde59cc86e9bad6e61b)) - Dropped execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) @@ -51,9 +52,13 @@ Updates & changes: - [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), commit [#43498de](https://github.com/stlink-org/stlink/commit/43498dedf651260ef34197e512d35e3ad7142401)) - End of support for macOS ([#1269](https://github.com/stlink-org/stlink/pull/1269), [#1296](https://github.com/stlink-org/stlink/pull/1296), commit [#61ff09e](https://github.com/stlink-org/stlink/commit/61ff09e5274d46a46ae58bc4ffe44fe90a887ea6)) - [doc] Added device ID for GD32F303VET6 ([#1288](https://github.com/stlink-org/stlink/pull/1288)) +- [doc] Fixed broken links ([#1312](https://github.com/stlink-org/stlink/pull/1312)) +- [doc] Updated package source link for Arch Linux ([#1318](https://github.com/stlink-org/stlink/pull/1318)) +- CMake: Avoid hard-wired /usr/local/share ([#1325](https://github.com/stlink-org/stlink/pull/1325)) Fixes: +- Fixed some flashing issues on STM32L0 ([#681](https://github.com/stlink-org/stlink/pull/681), [#1203](https://github.com/stlink-org/stlink/pull/1203), [#1225](https://github.com/stlink-org/stlink/pull/1225), [#1253](https://github.com/stlink-org/stlink/pull/1253), [#1289](https://github.com/stlink-org/stlink/pull/1289), [#1330](https://github.com/stlink-org/stlink/pull/1330)) - cmake: Install shared libraries in proper directories ([#1098](https://github.com/stlink-org/stlink/pull/1098), [#1138](https://github.com/stlink-org/stlink/pull/1138), [#1154](https://github.com/stlink-org/stlink/pull/1154)) - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) - Fixed clearance of the H7 dual bank flag ([#1146](https://github.com/stlink-org/stlink/pull/1146), [#1147](https://github.com/stlink-org/stlink/pull/1147)) @@ -84,9 +89,11 @@ Fixes: - Fixed st-trace reconnect on Windows ([#1272](https://github.com/stlink-org/stlink/pull/1272), [#1292](https://github.com/stlink-org/stlink/pull/1292)) - [compilation] Corrected path to stlink/chips subdirectory ([#1276](https://github.com/stlink-org/stlink/pull/1276), [#1279](https://github.com/stlink-org/stlink/pull/1279)) - [compilation] Fixed GUI compilation failure on OpenBSD i386 ([#1284](https://github.com/stlink-org/stlink/pull/1284)) +- [STM32U5x5]: Last bytes are not written (flashed) when len()%16 <= 8 ([#1303](https://github.com/stlink-org/stlink/pull/1303), [#1315](https://github.com/stlink-org/stlink/pull/1315)) - Fixed unbounded write and check return values of sscanf ([#1306](https://github.com/stlink-org/stlink/pull/1306)) - Added null check for return value of stlink_chipid_get_params() ([#1307](https://github.com/stlink-org/stlink/pull/1307)) - Fixed warning in a few *.cmake files ([#1309](https://github.com/stlink-org/stlink/pull/1309)) +- Notification "unknown option -- u" in tool st-util ([#1326](https://github.com/stlink-org/stlink/pull/1326), [#1327](https://github.com/stlink-org/stlink/pull/1327)) # v1.7.0 @@ -98,7 +105,7 @@ Features: - Extended set of cmd line arguments for st-info and st-util ([#332](https://github.com/stlink-org/stlink/pull/332), [#990](https://github.com/stlink-org/stlink/pull/990), [#1091](https://github.com/stlink-org/stlink/pull/1091), [#1114](https://github.com/stlink-org/stlink/pull/1114)) - Extended support for STM32H7 & rework of software reset ([#532](https://github.com/stlink-org/stlink/pull/532), [#801](https://github.com/stlink-org/stlink/pull/801), [#868](https://github.com/stlink-org/stlink/pull/868), [#1008](https://github.com/stlink-org/stlink/pull/1008), [#1059](https://github.com/stlink-org/stlink/pull/1059), [#1063](https://github.com/stlink-org/stlink/pull/1063), [#1071](https://github.com/stlink-org/stlink/pull/1071)) -- Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052), [#1184](https://github.com/stlink-org/stlink/pull/1184)) +- Added support for STM32H742/743/753 ([#671](https://github.com/stlink-org/stlink/pull/671), [#793](https://github.com/stlink-org/stlink/pull/793), [#823](https://github.com/stlink-org/stlink/pull/823), [#998](https://github.com/stlink-org/stlink/pull/998), [#1052](https://github.com/stlink-org/stlink/pull/1052), [#1184](https://github.com/stlink-org/stlink/pull/1184), [#1324](https://github.com/stlink-org/stlink/pull/1324)) - Official support for STLINK-V3 programmers (commit [#5e0a502](https://github.com/stlink-org/stlink/commit/5e0a502df812495bfa96fa9116a19f1306152b17), [#820](https://github.com/stlink-org/stlink/pull/820), [#1022](https://github.com/stlink-org/stlink/pull/1022), [#1025](https://github.com/stlink-org/stlink/pull/1025)) - Added preliminary support for STM32L5x2 ([#904](https://github.com/stlink-org/stlink/pull/904), [#999](https://github.com/stlink-org/stlink/pull/999)) - Option bytes on the STM32F767 ZIT6 Nucleo-144 ([#968](https://github.com/stlink-org/stlink/pull/968), [#997](https://github.com/stlink-org/stlink/pull/997)) diff --git a/README.md b/README.md index 6d188f0df..05f87658d 100644 --- a/README.md +++ b/README.md @@ -78,7 +78,12 @@ We recommend to install `stlink-tools` from the package repository of the used d - Alpine Linux: [(Link)](https://pkgs.alpinelinux.org/packages?name=stlink) - Fedora: [(Link)](https://src.fedoraproject.org/rpms/stlink) - FreeBSD: Users can install from [freshports](https://www.freshports.org/devel/stlink) -- MacOS: **Support for macOS will end with v1.8.0.** Please use v1.7.0 (current ***master*** branch) and the related documentation instead. + +**macOS**: + +**Support for macOS will be dropped with v1.8.0.** + +Please use v1.7.0 instead, **but note that this version is no longer maintained and supported!** ## Installation from source (advanced users) diff --git a/SECURITY.md b/SECURITY.md index 054641822..13432b927 100644 --- a/SECURITY.md +++ b/SECURITY.md @@ -7,7 +7,7 @@ The following versions of the stlink toolset are currently being supported.
      Date: Mon, 4 Sep 2023 16:21:55 +0200 Subject: [PATCH 1399/1435] Prefix all CDB bytes with 0x, including zeros --- src/stlink-lib/sg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/sg.c b/src/stlink-lib/sg.c index d7f844b51..c0e43547b 100644 --- a/src/stlink-lib/sg.c +++ b/src/stlink-lib/sg.c @@ -171,7 +171,7 @@ static int32_t dump_CDB_command(uint8_t *cdb, uint8_t cdb_len) { dbugp += sprintf(dbugp, "Sending CDB ["); for (uint8_t i = 0; i < cdb_len; i++) { - dbugp += sprintf(dbugp, " %#02x", (uint32_t)cdb[i]); + dbugp += sprintf(dbugp, " 0x%02x", (uint32_t)cdb[i]); } sprintf(dbugp, "]\n"); From a0c02161085401ecfce3dfcfd9c7ee63931a6b05 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 14 Sep 2023 11:35:35 +0200 Subject: [PATCH 1400/1435] Updated behaviour on Reset Fixes an issue where early breakpoints did not trigger. (Closes #1198) (Closes #1246) (Closes #1319) --- src/st-util/gdb-server.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index a0bc3f0a1..71f24fb60 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -1318,7 +1318,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { reply = strdup("E00"); } - ret = stlink_reset(sl, RESET_AUTO); + ret = stlink_reset(sl, RESET_SOFT_AND_HALT); if (ret) { DLOG("Rcmd: reset failed with reset\n"); reply = strdup("E00"); @@ -1835,7 +1835,7 @@ int32_t serve(stlink_t *sl, st_state_t *st) { case 'R': { // reset the core. - ret = stlink_reset(sl, RESET_AUTO); + ret = stlink_reset(sl, RESET_SOFT_AND_HALT); if (ret) { DLOG("R packet : stlink_reset failed\n"); } init_code_breakpoints(sl); From df7c7d21728f9804225c04912b45e34578b0d9ca Mon Sep 17 00:00:00 2001 From: Brian Date: Wed, 11 Oct 2023 19:55:50 -0400 Subject: [PATCH 1401/1435] Add CodeQL Workflow for Code Security Analysis Add CodeQL Workflow for Code Security Analysis This pull request introduces a CodeQL workflow to enhance the security analysis of our repository. CodeQL is a powerful static analysis tool that helps identify and mitigate security vulnerabilities in our codebase. By integrating this workflow into our GitHub Actions, we can proactively identify and address potential issues before they become security threats. We added a new CodeQL workflow file (.github/workflows/codeql.yml) that - Runs on every push and pull request to the main branch. - Excludes queries with a high false positive rate or low-severity findings. - Does not display results for third-party code, focusing only on our own codebase. Testing: To validate the functionality of this workflow, we have run several test scans on the codebase and reviewed the results. The workflow successfully compiles the project, identifies issues, and provides actionable insights while reducing noise by excluding certain queries and third-party code. Deployment: Once this pull request is merged, the CodeQL workflow will be active and automatically run on every push and pull request to the main branch. To view the results of these code scans, please follow these steps: 1. Under the repository name, click on the Security tab. 2. In the left sidebar, click Code scanning alerts. Additional Information: - You can further customize the workflow to adapt to your specific needs by modifying the workflow file. - For more information on CodeQL and how to interpret its results, refer to the GitHub documentation and the CodeQL documentation. Signed-off-by: Brian --- .github/workflows/codeql-buildscript.sh | 6 ++ .github/workflows/codeql.yml | 123 ++++++++++++++++++++++++ 2 files changed, 129 insertions(+) create mode 100644 .github/workflows/codeql-buildscript.sh create mode 100644 .github/workflows/codeql.yml diff --git a/.github/workflows/codeql-buildscript.sh b/.github/workflows/codeql-buildscript.sh new file mode 100644 index 000000000..d626d4283 --- /dev/null +++ b/.github/workflows/codeql-buildscript.sh @@ -0,0 +1,6 @@ +#!/usr/bin/env bash + +sudo apt-get -y update +sudo apt-get -y install libusb-1.0 libusb-1.0-0-dev libgtk-3-dev +make clean +make release -j$(nproc) diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml new file mode 100644 index 000000000..eaa9599bd --- /dev/null +++ b/.github/workflows/codeql.yml @@ -0,0 +1,123 @@ +# For most projects, this workflow file will not need changing; you simply need +# to commit it to your repository. +# +# You may wish to alter this file to override the set of languages analyzed, +# or to provide custom queries or build logic. +# +# ******** NOTE ******** +# We have attempted to detect the languages in your repository. Please check +# the `language` matrix defined below to confirm you have the correct set of +# supported CodeQL languages. +# +name: "CodeQL" + +on: + push: + branches: [ "main", "master" ] + pull_request: + # The branches below must be a subset of the branches above + branches: [ "main", "master" ] + schedule: + - cron: '28 21 * * 0' + +jobs: + analyze: + name: Analyze + # Runner size impacts CodeQL analysis time. To learn more, please see: + # - https://gh.io/recommended-hardware-resources-for-running-codeql + # - https://gh.io/supported-runners-and-hardware-resources + # - https://gh.io/using-larger-runners + # Consider using larger runners for possible analysis time improvements. + runs-on: ${{ (matrix.language == 'swift' && 'macos-latest') || 'ubuntu-20.04' }} + timeout-minutes: ${{ (matrix.language == 'swift' && 120) || 360 }} + permissions: + actions: read + contents: read + security-events: write + + strategy: + fail-fast: false + matrix: + language: [ 'cpp' ] + # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python', 'ruby', 'swift' ] + # Use only 'java' to analyze code written in Java, Kotlin or both + # Use only 'javascript' to analyze code written in JavaScript, TypeScript or both + # Learn more about CodeQL language support at https://aka.ms/codeql-docs/language-support + + steps: + - name: Checkout repository + uses: actions/checkout@v3 + with: + submodules: recursive + + # Initializes the CodeQL tools for scanning. + - name: Initialize CodeQL + uses: github/codeql-action/init@v2 + with: + languages: ${{ matrix.language }} + # If you wish to specify custom queries, you can do so here or in a config file. + # By default, queries listed here will override any specified in a config file. + # Prefix the list here with "+" to use these queries and those in the config file. + + # For more details on CodeQL's query packs, refer to: https://docs.github.com/en/code-security/code-scanning/automatically-scanning-your-code-for-vulnerabilities-and-errors/configuring-code-scanning#using-queries-in-ql-packs + # queries: security-extended,security-and-quality + queries: security-and-quality + + + # Autobuild attempts to build any compiled languages (C/C++, C#, Go, Java, or Swift). + # If this step fails, then you should remove it and run the build manually (see below) + #- name: Autobuild + # uses: github/codeql-action/autobuild@v2 + + # ℹ️ Command-line programs to run using the OS shell. + # 📚 See https://docs.github.com/en/actions/using-workflows/workflow-syntax-for-github-actions#jobsjob_idstepsrun + + # If the Autobuild fails above, remove it and uncomment the following three lines. + # modify them (or add more) to build your code if your project, please refer to the EXAMPLE below for guidance. + + - run: | + ./.github/workflows/codeql-buildscript.sh + + - name: Perform CodeQL Analysis + uses: github/codeql-action/analyze@v2 + with: + category: "/language:${{matrix.language}}" + upload: false + id: step1 + + # Filter out rules with low severity or high false positve rate + # Also filter out warnings in third-party code + - name: Filter out unwanted errors and warnings + uses: advanced-security/filter-sarif@v1 + with: + patterns: | + -**:cpp/path-injection + -**:cpp/world-writable-file-creation + -**:cpp/poorly-documented-function + -**:cpp/potentially-dangerous-function + -**:cpp/use-of-goto + -**:cpp/integer-multiplication-cast-to-long + -**:cpp/comparison-with-wider-type + -**:cpp/leap-year/* + -**:cpp/ambiguously-signed-bit-field + -**:cpp/suspicious-pointer-scaling + -**:cpp/suspicious-pointer-scaling-void + -**:cpp/unsigned-comparison-zero + -**/third*party/** + -**/3rd*party/** + -**/external/** + input: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif + output: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif + + - name: Upload SARIF + uses: github/codeql-action/upload-sarif@v2 + with: + sarif_file: ${{ steps.step1.outputs.sarif-output }} + category: "/language:${{matrix.language}}" + + - name: Archive CodeQL results + uses: actions/upload-artifact@v3 + with: + name: codeql-results + path: ${{ steps.step1.outputs.sarif-output }} + retention-days: 5 \ No newline at end of file From 3387ca5b425072b06c95831665ab9c9a63caf811 Mon Sep 17 00:00:00 2001 From: Daniele Cattaneo Date: Sat, 14 Oct 2023 17:48:17 +0200 Subject: [PATCH 1402/1435] Do not crash when the STLink chip returns a voltage factor of zero. --- src/stlink-lib/usb.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index 30134e161..d3a57c33f 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -238,7 +238,13 @@ int32_t _stlink_usb_target_voltage(stlink_t *sl) { factor = (rdata[3] << 24) | (rdata[2] << 16) | (rdata[1] << 8) | (rdata[0] << 0); reading = (rdata[7] << 24) | (rdata[6] << 16) | (rdata[5] << 8) | (rdata[4] << 0); - voltage = 2400 * reading / factor; + DLOG("target voltage factor=%08x reading=%08x\n", factor, reading); + if (factor != 0 && reading != 0) { + voltage = 2400 * reading / factor; + } else { + DLOG("voltage reading failed at device side, bad STLink chip?\n"); + voltage = 0; + } return (voltage); } From ed8fa62d098ad52bafc78507146899b5738f01d8 Mon Sep 17 00:00:00 2001 From: Brian Date: Wed, 18 Oct 2023 16:49:46 -0400 Subject: [PATCH 1403/1435] Add CodeQL Workflow for Code Security Analysis Add CodeQL Workflow for Code Security Analysis This pull request introduces a CodeQL workflow to enhance the security analysis of our repository. CodeQL is a powerful static analysis tool that helps identify and mitigate security vulnerabilities in our codebase. By integrating this workflow into our GitHub Actions, we can proactively identify and address potential issues before they become security threats. We added a new CodeQL workflow file (.github/workflows/codeql.yml) that - Runs on every pull request (functionality to run on every push to main branches is included as a comment for convenience). - Runs daily. - Excludes queries with a high false positive rate or low-severity findings. - Does not display results for git submodules, focusing only on our own codebase. Testing: To validate the functionality of this workflow, we have run several test scans on the codebase and reviewed the results. The workflow successfully compiles the project, identifies issues, and provides actionable insights while reducing noise by excluding certain queries and third-party code. Deployment: Once this pull request is merged, the CodeQL workflow will be active and automatically run on every push and pull request to the main branch. To view the results of these code scans, please follow these steps: 1. Under the repository name, click on the Security tab. 2. In the left sidebar, click Code scanning alerts. Additional Information: - You can further customize the workflow to adapt to your specific needs by modifying the workflow file. - For more information on CodeQL and how to interpret its results, refer to the GitHub documentation and the CodeQL documentation (https://codeql.github.com/ and https://codeql.github.com/docs/). Signed-off-by: Brian --- .github/workflows/codeql.yml | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index eaa9599bd..3ef873fc8 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -14,11 +14,10 @@ name: "CodeQL" on: push: branches: [ "main", "master" ] - pull_request: - # The branches below must be a subset of the branches above - branches: [ "main", "master" ] schedule: - - cron: '28 21 * * 0' + - cron: '0 0 * * *' + pull_request: + branches: '*' jobs: analyze: @@ -103,21 +102,25 @@ jobs: -**:cpp/suspicious-pointer-scaling -**:cpp/suspicious-pointer-scaling-void -**:cpp/unsigned-comparison-zero - -**/third*party/** - -**/3rd*party/** - -**/external/** + -**/cmake*/Modules/** input: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif output: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif - - name: Upload SARIF + - name: Upload CodeQL results to code scanning uses: github/codeql-action/upload-sarif@v2 with: sarif_file: ${{ steps.step1.outputs.sarif-output }} category: "/language:${{matrix.language}}" - - name: Archive CodeQL results + - name: Upload CodeQL results as an artifact + if: success() || failure() uses: actions/upload-artifact@v3 with: name: codeql-results path: ${{ steps.step1.outputs.sarif-output }} - retention-days: 5 \ No newline at end of file + retention-days: 5 + + - name: Fail if an error is found + run: | + ./.github/workflows/fail_on_error.py \ + ${{ steps.step1.outputs.sarif-output }}/cpp.sarif From b9a0a49a5423706433796605fb1511882603f635 Mon Sep 17 00:00:00 2001 From: Brian Date: Fri, 20 Oct 2023 01:02:15 -0400 Subject: [PATCH 1404/1435] Add CodeQL Workflow for Code Security Analysis Add CodeQL Workflow for Code Security Analysis This pull request introduces a CodeQL workflow to enhance the security analysis of our repository. CodeQL is a powerful static analysis tool that helps identify and mitigate security vulnerabilities in our codebase. By integrating this workflow into our GitHub Actions, we can proactively identify and address potential issues before they become security threats. We added a new CodeQL workflow file (.github/workflows/codeql.yml) that - Runs on every pull request (functionality to run on every push to main branches is included as a comment for convenience). - Runs daily. - Excludes queries with a high false positive rate or low-severity findings. - Does not display results for git submodules, focusing only on our own codebase. Testing: To validate the functionality of this workflow, we have run several test scans on the codebase and reviewed the results. The workflow successfully compiles the project, identifies issues, and provides actionable insights while reducing noise by excluding certain queries and third-party code. Deployment: Once this pull request is merged, the CodeQL workflow will be active and automatically run on every push and pull request to the main branch. To view the results of these code scans, please follow these steps: 1. Under the repository name, click on the Security tab. 2. In the left sidebar, click Code scanning alerts. Additional Information: - You can further customize the workflow to adapt to your specific needs by modifying the workflow file. - For more information on CodeQL and how to interpret its results, refer to the GitHub documentation and the CodeQL documentation (https://codeql.github.com/ and https://codeql.github.com/docs/). Signed-off-by: Brian --- .github/workflows/fail_on_error.py | 34 ++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100755 .github/workflows/fail_on_error.py diff --git a/.github/workflows/fail_on_error.py b/.github/workflows/fail_on_error.py new file mode 100755 index 000000000..29791742b --- /dev/null +++ b/.github/workflows/fail_on_error.py @@ -0,0 +1,34 @@ +#!/usr/bin/env python3 + +import json +import sys + +# Return whether SARIF file contains error-level results +def codeql_sarif_contain_error(filename): + with open(filename, 'r') as f: + s = json.load(f) + + for run in s.get('runs', []): + rules_metadata = run['tool']['driver']['rules'] + if not rules_metadata: + rules_metadata = run['tool']['extensions'][0]['rules'] + + for res in run.get('results', []): + if 'ruleIndex' in res: + rule_index = res['ruleIndex'] + elif 'rule' in res and 'index' in res['rule']: + rule_index = res['rule']['index'] + else: + continue + try: + rule_level = rules_metadata[rule_index]['defaultConfiguration']['level'] + except IndexError as e: + print(e, rule_index, len(rules_metadata)) + else: + if rule_level == 'error': + return True + return False + +if __name__ == "__main__": + if codeql_sarif_contain_error(sys.argv[1]): + sys.exit(1) From abf354a1558215fe9909c5d2c4947dd9aa35eb6c Mon Sep 17 00:00:00 2001 From: Brian Date: Sun, 29 Oct 2023 15:28:16 -0400 Subject: [PATCH 1405/1435] Add CodeQL Workflow for Code Security Analysis Add CodeQL Workflow for Code Security Analysis This pull request introduces a CodeQL workflow to enhance the security analysis of our repository. CodeQL is a powerful static analysis tool that helps identify and mitigate security vulnerabilities in our codebase. By integrating this workflow into our GitHub Actions, we can proactively identify and address potential issues before they become security threats. We added a new CodeQL workflow file (.github/workflows/codeql.yml) that - Runs on every pull request (functionality to run on every push to main branches is included as a comment for convenience). - Runs daily. - Excludes queries with a high false positive rate or low-severity findings. - Does not display results for git submodules, focusing only on our own codebase. Testing: To validate the functionality of this workflow, we have run several test scans on the codebase and reviewed the results. The workflow successfully compiles the project, identifies issues, and provides actionable insights while reducing noise by excluding certain queries and third-party code. Deployment: Once this pull request is merged, the CodeQL workflow will be active and automatically run on every push and pull request to the main branch. To view the results of these code scans, please follow these steps: 1. Under the repository name, click on the Security tab. 2. In the left sidebar, click Code scanning alerts. Additional Information: - You can further customize the workflow to adapt to your specific needs by modifying the workflow file. - For more information on CodeQL and how to interpret its results, refer to the GitHub documentation and the CodeQL documentation (https://codeql.github.com/ and https://codeql.github.com/docs/). Signed-off-by: Brian --- .github/workflows/codeql.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml index 3ef873fc8..816492278 100644 --- a/.github/workflows/codeql.yml +++ b/.github/workflows/codeql.yml @@ -12,8 +12,8 @@ name: "CodeQL" on: - push: - branches: [ "main", "master" ] + # push: + # branches: [ "main", "master" ] schedule: - cron: '0 0 * * *' pull_request: From 2d21188cdce20cfdcf9126044a2368a6ccc8dfc0 Mon Sep 17 00:00:00 2001 From: Mirko Date: Wed, 8 Nov 2023 14:51:19 +0000 Subject: [PATCH 1406/1435] first commit --- config/chips/L45x_L46x.chip | 2 ++ config/chips/L496x_L4A6x.chip | 2 ++ src/st-flash/flash.c | 24 +++++++++++++++ src/st-flash/flash_opts.c | 18 +++++------- src/stlink-lib/chipid.c | 16 ++++++++-- src/stlink-lib/chipid.h | 2 ++ src/stlink-lib/common.c | 3 ++ src/stlink-lib/common_flash.c | 55 ++++++++++++++++++++++++++++++++++- src/stlink-lib/common_flash.h | 2 ++ 9 files changed, 111 insertions(+), 13 deletions(-) diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index cbe948c1f..1c8fc2e1f 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -12,3 +12,5 @@ bootrom_size 0x7000 // 28 KB option_base 0x0 option_size 0x0 flags swo +otp_base 0x1fff7000 +otp_size 0x400 // 1 KB \ No newline at end of file diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 24788c092..8a4a93b1c 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -12,3 +12,5 @@ bootrom_size 0x7000 // 28 KB option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE option_size 0x4 // 4 B flags swo +otp_base 0x1fff7000 +otp_size 0x400 // 1 KB \ No newline at end of file diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 0577ee179..6553298c3 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -61,6 +61,7 @@ static void usage(void) { puts("example write option control register1 byte: ./st-flash --area=optcr write 0xXXXXXXXX"); puts("example read option control register1 byte: ./st-flash --area=optcr1 read"); puts("example write option control register1 byte: ./st-flash --area=optcr1 write 0xXXXXXXXX"); + puts("example read OTP area: ./st-flash --area=otp read [path]"); } int32_t main(int32_t ac, char** av) { @@ -180,6 +181,18 @@ int32_t main(int32_t ac, char** av) { DLOG("@@@@ Write %d (%0#10x) to option bytes boot address\n", o.val, o.val); err = stlink_write_option_bytes_boot_add32(sl, o.val); + } else if (o.area == FLASH_OTP) { + if(sl->otp_base == 0) { + err = -1; + printf("OTP Write Not implimented\n"); + goto on_error; + } + err = stlink_fwrite_flash(sl, o.filename, o.addr); + + if (err == -1) { + printf("stlink_fwrite_flash() == -1\n"); + goto on_error; + } } else { err = -1; printf("Unknown memory region\n"); @@ -284,6 +297,17 @@ int32_t main(int32_t ac, char** av) { } else { printf("%08x\n",option_byte); } + } else if (o.area == FLASH_OTP) { + if(sl->otp_base == 0) { + err = -1; + printf("OTP Read not implimented\n"); + goto on_error; + } + err = stlink_fread(sl, o.filename, 0, sl->otp_base, sl->otp_size); + if (err == -1) { + printf("could not read OTP area (%d)\n", err); + goto on_error; + } } } diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 300203a3f..cf80407d1 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -86,7 +86,6 @@ static int32_t bad_arg(const char *arg) { } int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { - // defaults memset(o, 0, sizeof(*o)); o->log_level = STND_LOG_LEVEL; @@ -270,13 +269,13 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { if (ac != 3) { return invalid_args("read "); } o->filename = av[0]; - uint32_t address; - result = get_integer_from_char_array(av[1], &address); - if (result != 0) { - return bad_arg ("addr"); - } else { - o->addr = (stm32_addr_t) address; - } + uint32_t address; + result = get_integer_from_char_array(av[1], &address); + if (result != 0) { + return bad_arg ("addr"); + } else { + o->addr = (stm32_addr_t) address; + } uint32_t size; result = get_integer_from_char_array(av[2], &size); @@ -288,8 +287,7 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { break; } else if (o->area == FLASH_OTP) { - return bad_arg("TODO: otp not implemented yet"); - if (ac > 1) { return invalid_args("otp read: [path]"); } + if (ac > 1 || ac ==0 ) { return invalid_args("otp read: [path]"); } if (ac > 0) { o->filename = av[0]; } break; } else if (o->area == FLASH_OPTION_BYTES) { diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 06edb26f3..1b6fc13f7 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -34,6 +34,7 @@ void dump_a_chip(struct stlink_chipid_params *dev) { DLOG("option_base 0x%x\n", dev->option_base); DLOG("option_size 0x%x\n", dev->option_size); DLOG("flags %d\n\n", dev->flags); + DLOG("otp_base %d\n\n", dev->otp_base); } struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { @@ -57,7 +58,6 @@ void process_chipfile(char *fname) { // fprintf (stderr, "processing chip-id file %s.\n", fname); fp = fopen(fname, "r"); - if (!fp) { perror(fname); return; @@ -180,8 +180,19 @@ void process_chipfile(char *fname) { fprintf(stderr, "Unknown flags word in %s: '%s'\n", fname, p); } } - sscanf(value, "%x", &ts->flags); + } else if (strcmp(word, "otp_base") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->otp_base) < 1) { + fprintf(stderr, "Failed to parse option size\n"); + } + } else if (strcmp(word, "otp_size") == 0) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + if (sscanf(value, "%i", &ts->otp_size) < 1) { + fprintf(stderr, "Failed to parse option size\n"); + } } else { fprintf(stderr, "Unknown keyword in %s: %s\n", fname, word); } @@ -191,6 +202,7 @@ void process_chipfile(char *fname) { devicelist = ts; } + #if defined(STLINK_HAVE_DIRENT_H) #include diff --git a/src/stlink-lib/chipid.h b/src/stlink-lib/chipid.h index 6726a7420..cf97e6609 100644 --- a/src/stlink-lib/chipid.h +++ b/src/stlink-lib/chipid.h @@ -21,6 +21,8 @@ struct stlink_chipid_params { uint32_t option_base; uint32_t option_size; uint32_t flags; + uint32_t otp_base; + uint32_t otp_size; struct stlink_chipid_params *next; }; diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index dbfcc8b9e..c470f9095 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -290,6 +290,9 @@ int32_t stlink_load_device_params(stlink_t *sl) { sl->option_base = params->option_base; sl->option_size = params->option_size; sl->chip_flags = params->flags; + sl->otp_base = params->otp_base; + sl->otp_size = params->otp_size; + // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 3038b53e7..60d8f42fb 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1310,9 +1310,17 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { * If the file is identified to be all-empty and four-bytes aligned, * still flash the whole file even if ignoring message is printed. */ - err = stlink_write_flash(sl, addr, mf.base, + + /* In case the address is within the OTP area we use a different flash method */ + if(addr >= sl->otp_base && addr <= sl->otp_base + sl->otp_size) { + err = stlink_write_otp(sl, addr, mf.base, + (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty); + } else { + err = stlink_write_flash(sl, addr, mf.base, (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty, num_empty == mf.len); + } + stlink_fwrite_finalize(sl, addr); unmap_file(&mf); return (err); @@ -1389,6 +1397,22 @@ int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, uin return 0; } +// Check if an address and size are within the flash (otp area) +int32_t stlink_check_address_range_validity_otp(stlink_t *sl, stm32_addr_t addr, uint32_t size) { + uint32_t logvar; + if (addr < sl->otp_base || addr >= (sl->otp_base + sl->otp_size)) { + logvar = sl->otp_base + sl->otp_size - 1; + ELOG("Invalid address, it should be within 0x%08x - 0x%08x\n", sl->otp_base, logvar); + return (-1); + } + if ((addr + size) > (sl->otp_base + sl->otp_size)) { + logvar = sl->otp_base + sl->otp_size - addr; + ELOG("The size exceeds the size of the OTP Area (0x%08x bytes available)\n", logvar); + return (-1); + } + return 0; +} + // Check if an address is aligned with the beginning of a page int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr) { stm32_addr_t page = sl->flash_base; @@ -1408,6 +1432,9 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 int32_t ret; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); + + (void)eraseonly; + // check addr range is inside the flash stlink_calculate_pagesize(sl, addr); @@ -1437,7 +1464,33 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 if (eraseonly) { return (0); } + + ret = stlink_flashloader_start(sl, &fl); + if (ret) + return ret; + ret = stlink_flashloader_write(sl, &fl, addr, base, len); + if (ret) + return ret; + ret = stlink_flashloader_stop(sl, &fl); + if (ret) + return ret; + + return (stlink_verify_write_flash(sl, addr, base, len)); +} + +int32_t stlink_write_otp(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { + int32_t ret; + flash_loader_t fl; + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); + + // Check the address and size validity + if (stlink_check_address_range_validity_otp(sl, addr, len) < 0) { + return (-1); + } + // make sure we've loaded the context with the chip details + stlink_core_id(sl); + ret = stlink_flashloader_start(sl, &fl); if (ret) return ret; diff --git a/src/stlink-lib/common_flash.h b/src/stlink-lib/common_flash.h index 9b2b84057..238f0403e 100644 --- a/src/stlink-lib/common_flash.h +++ b/src/stlink-lib/common_flash.h @@ -44,8 +44,10 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr); int32_t stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr); int32_t stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length); int32_t stlink_check_address_range_validity(stlink_t *sl, stm32_addr_t addr, uint32_t size); +int32_t stlink_check_address_range_validity_otp(stlink_t *sl, stm32_addr_t addr, uint32_t size); int32_t stlink_check_address_alignment(stlink_t *sl, stm32_addr_t addr); int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len, uint8_t eraseonly); +int32_t stlink_write_otp(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len); void stlink_fwrite_finalize(stlink_t *, stm32_addr_t); #endif // COMMON_FLASH_H From b1d99a2fc22af6935f714525641a01483c076b3c Mon Sep 17 00:00:00 2001 From: Mirko Date: Wed, 8 Nov 2023 15:04:10 +0000 Subject: [PATCH 1407/1435] cleaning ident --- config/chips/L45x_L46x.chip | 2 +- config/chips/L496x_L4A6x.chip | 2 +- src/st-flash/flash.c | 4 ++-- src/st-flash/flash_opts.c | 15 ++++++++------- src/stlink-lib/chipid.c | 2 +- src/stlink-lib/common.c | 1 - 6 files changed, 13 insertions(+), 13 deletions(-) diff --git a/config/chips/L45x_L46x.chip b/config/chips/L45x_L46x.chip index 1c8fc2e1f..c32030be9 100644 --- a/config/chips/L45x_L46x.chip +++ b/config/chips/L45x_L46x.chip @@ -13,4 +13,4 @@ option_base 0x0 option_size 0x0 flags swo otp_base 0x1fff7000 -otp_size 0x400 // 1 KB \ No newline at end of file +otp_size 0x400 // 1 KB diff --git a/config/chips/L496x_L4A6x.chip b/config/chips/L496x_L4A6x.chip index 8a4a93b1c..65fa3dcbc 100644 --- a/config/chips/L496x_L4A6x.chip +++ b/config/chips/L496x_L4A6x.chip @@ -13,4 +13,4 @@ option_base 0x1fff7800 // STM32_L4_OPTION_BYTES_BASE option_size 0x4 // 4 B flags swo otp_base 0x1fff7000 -otp_size 0x400 // 1 KB \ No newline at end of file +otp_size 0x400 // 1 KB diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index 6553298c3..c2cd77a47 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -184,7 +184,7 @@ int32_t main(int32_t ac, char** av) { } else if (o.area == FLASH_OTP) { if(sl->otp_base == 0) { err = -1; - printf("OTP Write Not implimented\n"); + printf("OTP Write NOT implemented\n"); goto on_error; } err = stlink_fwrite_flash(sl, o.filename, o.addr); @@ -300,7 +300,7 @@ int32_t main(int32_t ac, char** av) { } else if (o.area == FLASH_OTP) { if(sl->otp_base == 0) { err = -1; - printf("OTP Read not implimented\n"); + printf("OTP Read NOT implemented\n"); goto on_error; } err = stlink_fread(sl, o.filename, 0, sl->otp_base, sl->otp_size); diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index cf80407d1..8f88f6ea7 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -86,6 +86,7 @@ static int32_t bad_arg(const char *arg) { } int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { + // defaults memset(o, 0, sizeof(*o)); o->log_level = STND_LOG_LEVEL; @@ -269,13 +270,13 @@ int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { if (ac != 3) { return invalid_args("read "); } o->filename = av[0]; - uint32_t address; - result = get_integer_from_char_array(av[1], &address); - if (result != 0) { - return bad_arg ("addr"); - } else { - o->addr = (stm32_addr_t) address; - } + uint32_t address; + result = get_integer_from_char_array(av[1], &address); + if (result != 0) { + return bad_arg ("addr"); + } else { + o->addr = (stm32_addr_t) address; + } uint32_t size; result = get_integer_from_char_array(av[2], &size); diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 1b6fc13f7..77cbfb15d 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -58,6 +58,7 @@ void process_chipfile(char *fname) { // fprintf (stderr, "processing chip-id file %s.\n", fname); fp = fopen(fname, "r"); + if (!fp) { perror(fname); return; @@ -202,7 +203,6 @@ void process_chipfile(char *fname) { devicelist = ts; } - #if defined(STLINK_HAVE_DIRENT_H) #include diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index c470f9095..337fe6efa 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -293,7 +293,6 @@ int32_t stlink_load_device_params(stlink_t *sl) { sl->otp_base = params->otp_base; sl->otp_size = params->otp_size; - // medium and low devices have the same chipid. ram size depends on flash // size. STM32F100xx datasheet Doc ID 16455 Table 2 if (sl->chip_id == STM32_CHIPID_F1_VL_MD_LD && sl->flash_size < 64 * 1024) { From 3cb15d7da2deb69a38940d1fa82570771252951b Mon Sep 17 00:00:00 2001 From: Mirko Date: Wed, 8 Nov 2023 15:14:19 +0000 Subject: [PATCH 1408/1435] final --- src/st-flash/flash.c | 1 + src/st-flash/flash_opts.c | 2 +- src/stlink-lib/chipid.c | 2 ++ src/stlink-lib/common_flash.c | 3 --- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/st-flash/flash.c b/src/st-flash/flash.c index c2cd77a47..0b7c0cfca 100644 --- a/src/st-flash/flash.c +++ b/src/st-flash/flash.c @@ -62,6 +62,7 @@ static void usage(void) { puts("example read option control register1 byte: ./st-flash --area=optcr1 read"); puts("example write option control register1 byte: ./st-flash --area=optcr1 write 0xXXXXXXXX"); puts("example read OTP area: ./st-flash --area=otp read [path]"); + puts("example write OTP area: ./st-flash --area=otp write [path] 0xXXXXXXXX"); } int32_t main(int32_t ac, char** av) { diff --git a/src/st-flash/flash_opts.c b/src/st-flash/flash_opts.c index 8f88f6ea7..e2d4154fe 100644 --- a/src/st-flash/flash_opts.c +++ b/src/st-flash/flash_opts.c @@ -86,7 +86,7 @@ static int32_t bad_arg(const char *arg) { } int32_t flash_get_opts(struct flash_opts* o, int32_t ac, char** av) { - + // defaults memset(o, 0, sizeof(*o)); o->log_level = STND_LOG_LEVEL; diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 77cbfb15d..ceeed3114 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -35,6 +35,7 @@ void dump_a_chip(struct stlink_chipid_params *dev) { DLOG("option_size 0x%x\n", dev->option_size); DLOG("flags %d\n\n", dev->flags); DLOG("otp_base %d\n\n", dev->otp_base); + DLOG("otp_size %d\n\n", dev->otp_size); } struct stlink_chipid_params *stlink_chipid_get_params(uint32_t chip_id) { @@ -181,6 +182,7 @@ void process_chipfile(char *fname) { fprintf(stderr, "Unknown flags word in %s: '%s'\n", fname, p); } } + sscanf(value, "%x", &ts->flags); } else if (strcmp(word, "otp_base") == 0) { buf[strlen(buf) - 1] = 0; // chomp newline diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 60d8f42fb..5005a632f 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1320,7 +1320,6 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty, num_empty == mf.len); } - stlink_fwrite_finalize(sl, addr); unmap_file(&mf); return (err); @@ -1433,8 +1432,6 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); - (void)eraseonly; - // check addr range is inside the flash stlink_calculate_pagesize(sl, addr); From e122764f214fb9821b173a63f7ae18690611dc0a Mon Sep 17 00:00:00 2001 From: Mirko Date: Wed, 8 Nov 2023 22:58:05 +0000 Subject: [PATCH 1409/1435] forgot to include this --- inc/stlink.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/inc/stlink.h b/inc/stlink.h index dec608e97..557a9eeaa 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -232,6 +232,9 @@ struct _stlink { uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx uint32_t max_trace_freq; // set by stlink_open_usb() + + uint32_t otp_base; + uint32_t otp_size; }; /* Functions defined in common.c */ From 99a2be4d287198ea8072e0db1865fc1757255b7b Mon Sep 17 00:00:00 2001 From: rcubee Date: Sat, 11 Nov 2023 17:27:05 +0100 Subject: [PATCH 1410/1435] initial commit --- c0.patch | 618 ++++++++++++++++++++++++++++++++++ doc/supported_devices.md | 1 + inc/stm32.h | 30 +- inc/stm32flash.h | 24 ++ src/stlink-lib/chipid.c | 4 +- src/stlink-lib/common_flash.c | 98 ++++-- src/stlink-lib/flash_loader.c | 31 +- src/stlink-lib/option_bytes.c | 107 +++++- 8 files changed, 870 insertions(+), 43 deletions(-) create mode 100644 c0.patch diff --git a/c0.patch b/c0.patch new file mode 100644 index 000000000..5b59834d6 --- /dev/null +++ b/c0.patch @@ -0,0 +1,618 @@ +diff --git a/doc/supported_devices.md b/doc/supported_devices.md +index 2e96dcd..103c7fb 100644 +--- a/doc/supported_devices.md ++++ b/doc/supported_devices.md +@@ -6,6 +6,7 @@ More commonly these are: + | Product-Family | ARM Cortex Core | Product Line | + | -------------- | --------------- | ---------------------------------------------------------- | + | STM32F0 | M0 | | ++| STM32C0 | M0+ | | + | STM32G0 | M0+ | | + | STM32L0 | M0+ | | + | STM32F10**0** | M3 | Value line | +diff --git a/inc/stm32.h b/inc/stm32.h +index cf9a8a2..017ea0a 100644 +--- a/inc/stm32.h ++++ b/inc/stm32.h +@@ -51,17 +51,18 @@ enum stm32_core_id { + /* STM32 flash types */ + enum stm32_flash_type { + STM32_FLASH_TYPE_UNKNOWN = 0, +- STM32_FLASH_TYPE_F0_F1_F3 = 1, +- STM32_FLASH_TYPE_F1_XL = 2, +- STM32_FLASH_TYPE_F2_F4 = 3, +- STM32_FLASH_TYPE_F7 = 4, +- STM32_FLASH_TYPE_G0 = 5, +- STM32_FLASH_TYPE_G4 = 6, +- STM32_FLASH_TYPE_H7 = 7, +- STM32_FLASH_TYPE_L0_L1 = 8, +- STM32_FLASH_TYPE_L4 = 9, +- STM32_FLASH_TYPE_L5_U5_H5 = 10, +- STM32_FLASH_TYPE_WB_WL = 11, ++ STM32_FLASH_TYPE_C0 = 1, ++ STM32_FLASH_TYPE_F0_F1_F3 = 2, ++ STM32_FLASH_TYPE_F1_XL = 3, ++ STM32_FLASH_TYPE_F2_F4 = 4, ++ STM32_FLASH_TYPE_F7 = 5, ++ STM32_FLASH_TYPE_G0 = 6, ++ STM32_FLASH_TYPE_G4 = 7, ++ STM32_FLASH_TYPE_H7 = 8, ++ STM32_FLASH_TYPE_L0_L1 = 9, ++ STM32_FLASH_TYPE_L4 = 10, ++ STM32_FLASH_TYPE_L5_U5_H5 = 11, ++ STM32_FLASH_TYPE_WB_WL = 12, + }; + + /* STM32 chip-ids */ +@@ -102,6 +103,7 @@ enum stm32_chipids { + STM32_CHIPID_F0 = 0x440, + STM32_CHIPID_F412 = 0x441, + STM32_CHIPID_F09x = 0x442, ++ STM32_CHIPID_C011xx = 0x443, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ + STM32_CHIPID_F0xx_SMALL = 0x444, + STM32_CHIPID_F04 = 0x445, + STM32_CHIPID_F303_HD = 0x446, /* high density */ +@@ -111,6 +113,7 @@ enum stm32_chipids { + STM32_CHIPID_H74xxx = 0x450, /* RM0433, p.3189 */ + STM32_CHIPID_F76xxx = 0x451, + STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ ++ STM32_CHIPID_C031xx = 0x453, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ + STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ + STM32_CHIPID_L0_CAT1 = 0x457, + STM32_CHIPID_F410 = 0x458, +@@ -136,6 +139,8 @@ enum stm32_chipids { + }; + + /* Constant STM32 option bytes base memory address */ ++#define STM32_C0_OPTION_BYTES_BASE ((uint32_t)0x1fff7800) ++ + #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14) + + #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201c) +@@ -189,6 +194,9 @@ enum stm32_chipids { + #define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 + #define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 + ++#define STM32C0_RCC_AHBENR 0x40021038 // RM0490 (revision 3), section 5.4.25 "RCC register map" ++#define STM32C0_RCC_DMAEN 0x00000001 // DMAEN // RM0490 (revision 3), section 5.4.25 "RCC register map" ++ + #define STM32F1_RCC_AHBENR 0x40021014 + #define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN + +diff --git a/inc/stm32flash.h b/inc/stm32flash.h +index 69c6206..b5e47e0 100644 +--- a/inc/stm32flash.h ++++ b/inc/stm32flash.h +@@ -58,6 +58,30 @@ + #define FLASH_OBR_OFF ((uint32_t)0x1c) + #define FLASH_WRPR_OFF ((uint32_t)0x20) + ++// == STM32C0 == (RM0490) ++// C0 Flash registers ++#define FLASH_C0_REGS_ADDR ((uint32_t)0x40022000) ++#define FLASH_C0_KEYR (FLASH_C0_REGS_ADDR + 0x08) ++#define FLASH_C0_OPT_KEYR (FLASH_C0_REGS_ADDR + 0x0C) ++#define FLASH_C0_SR (FLASH_C0_REGS_ADDR + 0x10) ++#define FLASH_C0_CR (FLASH_C0_REGS_ADDR + 0x14) ++#define FLASH_C0_OPTR (FLASH_C0_REGS_ADDR + 0x20) ++ ++// C0 Flash control register ++#define FLASH_C0_CR_PNB 3 ++#define FLASH_C0_CR_STRT 16 ++#define FLASH_C0_CR_OPTSTRT 17 ++#define FLASH_C0_CR_OBL_LAUNCH 27 ++#define FLASH_C0_CR_OPTLOCK 30 ++#define FLASH_C0_CR_LOCK 31 ++ ++// C0 Flash status register ++#define FLASH_C0_SR_ERROR_MASK 0xC3F8 // [15:14], [9:3] ++#define FLASH_C0_SR_PROGERR 3 ++#define FLASH_C0_SR_WRPERR 4 ++#define FLASH_C0_SR_PGAERR 5 ++#define FLASH_C0_SR_BSY 16 ++ + // == STM32F0 == + #define FLASH_F0_OPTKEY1 0x45670123 + #define FLASH_F0_OPTKEY2 0xcdef89ab +diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c +index 06edb26..86f01f4 100644 +--- a/src/stlink-lib/chipid.c ++++ b/src/stlink-lib/chipid.c +@@ -97,7 +97,9 @@ void process_chipfile(char *fname) { + buf[strlen(buf) - 1] = 0; // chomp newline + sscanf(buf, "%*s %n", &nc); + // Match human readable flash_type with enum stm32_flash_type { }. +- if (strcmp(value, "F0_F1_F3") == 0) { ++ if(strcmp(value, "C0") == 0) { ++ ts->flash_type = STM32_FLASH_TYPE_C0; ++ } else if (strcmp(value, "F0_F1_F3") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; + } else if (strcmp(value, "F1_XL") == 0) { + ts->flash_type = STM32_FLASH_TYPE_F1_XL; +diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c +index 3038b53..491cf46 100644 +--- a/src/stlink-lib/common_flash.c ++++ b/src/stlink-lib/common_flash.c +@@ -46,7 +46,9 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { + uint32_t read_flash_cr(stlink_t *sl, uint32_t bank) { + uint32_t reg, res; + +- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ reg = FLASH_C0_CR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + reg = FLASH_F4_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + reg = FLASH_F7_CR; +@@ -77,7 +79,10 @@ void lock_flash(stlink_t *sl) { + uint32_t cr_lock_shift = 0, cr_reg = 0, n = 0, cr2_reg = 0; + uint32_t cr_mask = 0xffffffffu; + +- if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ cr_lock_shift = FLASH_C0_CR_LOCK; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { +@@ -132,8 +137,10 @@ void lock_flash(stlink_t *sl) { + static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) { + uint32_t sr_reg; + +- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || +- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ sr_reg = FLASH_C0_SR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || ++ sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + sr_reg = FLASH_F4_SR; +@@ -162,6 +169,9 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) + + void clear_flash_error(stlink_t *sl) { + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ write_flash_sr(sl, BANK_1, FLASH_C0_SR_ERROR_MASK); ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); + break; +@@ -205,8 +215,10 @@ void clear_flash_error(stlink_t *sl) { + uint32_t read_flash_sr(stlink_t *sl, uint32_t bank) { + uint32_t res, sr_reg; + +- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || +- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ sr_reg = FLASH_C0_SR; ++ } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || ++ (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + sr_reg = FLASH_F4_SR; +@@ -238,9 +250,11 @@ uint32_t is_flash_busy(stlink_t *sl) { + uint32_t sr_busy_shift; + uint32_t res; + +- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || +- (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || +- (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ sr_busy_shift = FLASH_C0_SR_BSY; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || ++ sl->flash_type == STM32_FLASH_TYPE_F1_XL || ++ sl->flash_type == STM32_FLASH_TYPE_L0_L1) { + sr_busy_shift = FLASH_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + sr_busy_shift = FLASH_F4_SR_BSY; +@@ -286,6 +300,12 @@ int32_t check_flash_error(stlink_t *sl) { + WRPERR = PROGERR = PGAERR = 0; + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ res = read_flash_sr(sl, BANK_1) & FLASH_C0_SR_ERROR_MASK; ++ WRPERR = (1 << FLASH_C0_SR_WRPERR); ++ PROGERR = (1 << FLASH_C0_SR_PROGERR); ++ PGAERR = (1 << FLASH_C0_SR_PGAERR); ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; +@@ -382,8 +402,11 @@ static inline uint32_t is_flash_locked(stlink_t *sl) { + uint32_t cr_reg; + uint32_t n; + +- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || +- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ cr_lock_shift = FLASH_C0_CR_LOCK; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || ++ sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + cr_reg = FLASH_CR; + cr_lock_shift = FLASH_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { +@@ -429,7 +452,9 @@ static void unlock_flash(stlink_t *sl) { + * definitive lock of the FPEC block until next reset. + */ + +- if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ key_reg = FLASH_C0_KEYR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + key_reg = FLASH_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { + key_reg = FLASH_KEYR; +@@ -497,6 +522,10 @@ int32_t lock_flash_option(stlink_t *sl) { + int32_t active_bit_level = 1; + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ optcr_reg = FLASH_C0_CR; ++ optlock_shift = FLASH_C0_CR_OPTLOCK; ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; +@@ -574,6 +603,10 @@ static bool is_flash_option_locked(stlink_t *sl) { + uint32_t n; + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ optcr_reg = FLASH_C0_CR; ++ optlock_shift = FLASH_C0_CR_OPTLOCK; ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + optcr_reg = FLASH_CR; +@@ -633,6 +666,9 @@ static int32_t unlock_flash_option(stlink_t *sl) { + uint32_t optkey2 = FLASH_OPTKEY2; + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ optkey_reg = FLASH_C0_OPT_KEYR; ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + optkey_reg = FLASH_OPTKEYR; +@@ -726,7 +762,9 @@ void clear_flash_cr_pg(stlink_t *sl, uint32_t bank) { + uint32_t cr_reg, n; + uint32_t bit = FLASH_CR_PG; + +- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; +@@ -802,8 +840,10 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, uint32_t bank) { + static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { + uint32_t cr_reg, val; + +- if (sl->flash_type == STM32_FLASH_TYPE_G0 || +- sl->flash_type == STM32_FLASH_TYPE_G4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || ++ sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = FLASH_Gx_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { + cr_reg = FLASH_L5_NSCR; +@@ -821,8 +861,10 @@ static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { + static void clear_flash_cr_per(stlink_t *sl, uint32_t bank) { + uint32_t cr_reg; + +- if (sl->flash_type == STM32_FLASH_TYPE_G0 || +- sl->flash_type == STM32_FLASH_TYPE_G4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || ++ sl->flash_type == STM32_FLASH_TYPE_G4) { + cr_reg = FLASH_Gx_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { + cr_reg = FLASH_L5_NSCR; +@@ -855,7 +897,10 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { + static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { + uint32_t val, cr_reg, cr_strt; + +- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ cr_strt = 1 << FLASH_C0_CR_STRT; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + cr_strt = 1 << FLASH_F4_CR_STRT; + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { +@@ -890,7 +935,11 @@ static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { + static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank) { + uint32_t val, cr_reg, cr_mer, cr_pg; + +- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ cr_mer = 1 << FLASH_CR_MER; ++ cr_pg = 1 << FLASH_CR_PG; ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; +@@ -1062,7 +1111,8 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || + sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || +- sl->flash_type == STM32_FLASH_TYPE_WB_WL) { ++ sl->flash_type == STM32_FLASH_TYPE_WB_WL || ++ sl->flash_type == STM32_FLASH_TYPE_C0) { + uint32_t val; + unlock_flash_if(sl); + set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit +@@ -1107,6 +1157,14 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { + val |= ((flash_page & 0xFF) << 3); + + stlink_write_debug32(sl, FLASH_WB_CR, val); ++ } else if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); ++ stlink_read_debug32(sl, FLASH_C0_CR, &val); ++ ++ val &= ~(0xF << FLASH_C0_CR_PNB); ++ val |= ((flash_page & 0xF) << FLASH_C0_CR_PNB); ++ ++ stlink_write_debug32(sl, FLASH_C0_CR, val); + } + + set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit +diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c +index ea1f6d9..0d01dfd 100644 +--- a/src/stlink-lib/flash_loader.c ++++ b/src/stlink-lib/flash_loader.c +@@ -491,12 +491,15 @@ static void set_flash_cr_pg(stlink_t *sl, uint32_t bank) { + + x = read_flash_cr(sl, bank); + +- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { ++ if (sl->flash_type == STM32_FLASH_TYPE_C0) { ++ cr_reg = FLASH_C0_CR; ++ x |= (1 << FLASH_CR_PG); ++ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + cr_reg = FLASH_F4_CR; +- x |= 1 << FLASH_CR_PG; ++ x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { + cr_reg = FLASH_F7_CR; +- x |= 1 << FLASH_CR_PG; ++ x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { + cr_reg = FLASH_L4_CR; + x &= ~FLASH_L4_CR_OPBITS; +@@ -528,6 +531,10 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr) { + rcc = rcc_dma_mask = value = 0; + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ rcc = STM32C0_RCC_AHBENR; ++ rcc_dma_mask = STM32C0_RCC_DMAEN; ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + rcc = STM32F1_RCC_AHBENR; +@@ -639,8 +646,9 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || +- sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { +- ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5\n"); ++ sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || ++ sl->flash_type == STM32_FLASH_TYPE_C0) { ++ ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5/C0\n"); + + unlock_flash_if(sl); // unlock flash if necessary + set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit +@@ -720,6 +728,7 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { + + int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { + uint32_t off; ++ + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || + (sl->flash_type == STM32_FLASH_TYPE_L4)) { +@@ -737,13 +746,14 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t + } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4 || +- sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { ++ sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || ++ sl->flash_type == STM32_FLASH_TYPE_C0) { + DLOG("Starting %3u page write\n", len / sl->flash_pgsz); + for (off = 0; off < len; off += sizeof(uint32_t)) { + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { +- fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); ++ fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); + fflush(stdout); + } + +@@ -782,7 +792,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t + uint32_t data; + + if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { +- fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); ++ fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); + fflush(stdout); + } + +@@ -819,7 +829,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t + if (sl->verbose >= 1) { + // show progress; writing procedure is slow and previous errors are + // misleading +- fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, ++ fprintf(stdout, "\r%3u/%-3u pages written", ++write_block_count, + (len + sl->flash_pgsz - 1) / sl->flash_pgsz); + fflush(stdout); + } +@@ -856,7 +866,8 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t + int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { + uint32_t dhcsr; + +- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || ++ if ((sl->flash_type == STM32_FLASH_TYPE_C0) || ++ (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || + (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || + (sl->flash_type == STM32_FLASH_TYPE_F7) || +diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c +index ee03dce..2ee45c9 100644 +--- a/src/stlink-lib/option_bytes.c ++++ b/src/stlink-lib/option_bytes.c +@@ -18,6 +18,101 @@ + #include "md5.h" + #include "read_write.h" + ++/** ++ * Read option control register C0 ++ * @param sl ++ * @param option_byte ++ * @return 0 on success, -ve on failure. ++ */ ++static int32_t stlink_read_option_control_register_c0(stlink_t *sl, uint32_t *option_byte) { ++ return stlink_read_debug32(sl, FLASH_C0_OPTR, option_byte); ++} ++ ++/** ++ * Read option bytes C0 ++ * @param sl ++ * @param option_byte ++ * @return 0 on success, -ve on failure. ++ */ ++static int32_t stlink_read_option_bytes_c0(stlink_t *sl, uint32_t *option_byte) { ++ return stlink_read_option_control_register_c0(sl, option_byte); ++} ++ ++/** ++ * Write option control register C0 ++ * @param sl ++ * @param option_cr ++ * @return 0 on success, -ve on failure. ++ */ ++static int32_t stlink_write_option_control_register_c0(stlink_t *sl, uint32_t option_cr) { ++ int32_t ret = 0; ++ ++ clear_flash_error(sl); ++ ++ if ((ret = stlink_write_debug32(sl, FLASH_C0_OPTR, option_cr))) ++ return ret; ++ ++ wait_flash_busy(sl); ++ ++ uint32_t cr_reg = (1 << FLASH_C0_CR_OPTSTRT); ++ if ((ret = stlink_write_debug32(sl, FLASH_C0_CR, cr_reg))) ++ return ret; ++ ++ wait_flash_busy(sl); ++ ++ if ((ret = check_flash_error(sl))) ++ return ret; ++ ++ // trigger the load of option bytes into option registers ++ cr_reg = (1 << FLASH_C0_CR_OBL_LAUNCH); ++ stlink_write_debug32(sl, FLASH_C0_CR, cr_reg); ++ ++ return ret; ++} ++ ++/** ++ * Write option bytes C0 ++ * @param sl ++ * @param addr of the memory mapped option bytes ++ * @param base option bytes ++ * @param len of option bytes ++ * @return 0 on success, -ve on failure. ++ */ ++static int32_t stlink_write_option_bytes_c0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { ++#if 0 ++ uint32_t val; ++ int32_t ret = 0; ++ (void)len; ++ uint32_t data; ++ ++ clear_flash_error(sl); ++ ++ write_uint32((unsigned char *)&data, *(uint32_t *)(base)); ++ WLOG("Writing option bytes %#10x to %#10x\n", data, addr); ++ stlink_write_debug32(sl, FLASH_C0_OPTR, data); ++ ++ stlink_read_debug32(sl, FLASH_C0_CR, &val); ++ val |= (1 << FLASH_C0_CR_OPTSTRT); ++ stlink_write_debug32(sl, FLASH_C0_CR, val); ++ ++ wait_flash_busy(sl); ++ ++ ret = check_flash_error(sl); ++ ++ // trigger the load of option bytes into option registers ++ stlink_read_debug32(sl, FLASH_C0_CR, &val); ++ val |= (1 << FLASH_C0_CR_OBL_LAUNCH); ++ stlink_write_debug32(sl, FLASH_C0_CR, val); ++ ++ return (ret); ++#else ++ (void)addr; ++ (void)len; ++ ++ return stlink_write_option_control_register_c0(sl, *(uint32_t*)base); ++#endif ++} ++ + /** + * Read option control register F0 + * @param sl +@@ -745,7 +840,6 @@ int32_t stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_debug32(sl, sl->option_base, option_byte); + } + +- + /** + * Write option bytes + * @param sl +@@ -785,6 +879,9 @@ int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base + } + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ ret = stlink_write_option_bytes_c0(sl, addr, base, len); ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + ret = stlink_write_option_bytes_f0(sl, addr, base, len); +@@ -870,6 +967,8 @@ int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byt + } + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ return stlink_read_option_control_register_c0(sl, option_byte); + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + return stlink_read_option_control_register_f0(sl, option_byte); +@@ -904,6 +1003,9 @@ int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) + } + + switch (sl->flash_type) { ++ case STM32_FLASH_TYPE_C0: ++ ret = stlink_write_option_control_register_c0(sl, option_cr); ++ break; + case STM32_FLASH_TYPE_F0_F1_F3: + case STM32_FLASH_TYPE_F1_XL: + ret = stlink_write_option_control_register_f0(sl, option_cr); +@@ -1009,6 +1111,9 @@ int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { + } + + switch (sl->chip_id) { ++ case STM32_CHIPID_C011xx: ++ case STM32_CHIPID_C031xx: ++ return stlink_read_option_bytes_c0(sl, option_byte); + case STM32_CHIPID_F2: + return stlink_read_option_bytes_f2(sl, option_byte); + case STM32_CHIPID_F4: diff --git a/doc/supported_devices.md b/doc/supported_devices.md index 2e96dcd39..103c7fb5f 100644 --- a/doc/supported_devices.md +++ b/doc/supported_devices.md @@ -6,6 +6,7 @@ More commonly these are: | Product-Family | ARM Cortex Core | Product Line | | -------------- | --------------- | ---------------------------------------------------------- | | STM32F0 | M0 | | +| STM32C0 | M0+ | | | STM32G0 | M0+ | | | STM32L0 | M0+ | | | STM32F10**0** | M3 | Value line | diff --git a/inc/stm32.h b/inc/stm32.h index cf9a8a2ad..017ea0af6 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -51,17 +51,18 @@ enum stm32_core_id { /* STM32 flash types */ enum stm32_flash_type { STM32_FLASH_TYPE_UNKNOWN = 0, - STM32_FLASH_TYPE_F0_F1_F3 = 1, - STM32_FLASH_TYPE_F1_XL = 2, - STM32_FLASH_TYPE_F2_F4 = 3, - STM32_FLASH_TYPE_F7 = 4, - STM32_FLASH_TYPE_G0 = 5, - STM32_FLASH_TYPE_G4 = 6, - STM32_FLASH_TYPE_H7 = 7, - STM32_FLASH_TYPE_L0_L1 = 8, - STM32_FLASH_TYPE_L4 = 9, - STM32_FLASH_TYPE_L5_U5_H5 = 10, - STM32_FLASH_TYPE_WB_WL = 11, + STM32_FLASH_TYPE_C0 = 1, + STM32_FLASH_TYPE_F0_F1_F3 = 2, + STM32_FLASH_TYPE_F1_XL = 3, + STM32_FLASH_TYPE_F2_F4 = 4, + STM32_FLASH_TYPE_F7 = 5, + STM32_FLASH_TYPE_G0 = 6, + STM32_FLASH_TYPE_G4 = 7, + STM32_FLASH_TYPE_H7 = 8, + STM32_FLASH_TYPE_L0_L1 = 9, + STM32_FLASH_TYPE_L4 = 10, + STM32_FLASH_TYPE_L5_U5_H5 = 11, + STM32_FLASH_TYPE_WB_WL = 12, }; /* STM32 chip-ids */ @@ -102,6 +103,7 @@ enum stm32_chipids { STM32_CHIPID_F0 = 0x440, STM32_CHIPID_F412 = 0x441, STM32_CHIPID_F09x = 0x442, + STM32_CHIPID_C011xx = 0x443, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ STM32_CHIPID_F0xx_SMALL = 0x444, STM32_CHIPID_F04 = 0x445, STM32_CHIPID_F303_HD = 0x446, /* high density */ @@ -111,6 +113,7 @@ enum stm32_chipids { STM32_CHIPID_H74xxx = 0x450, /* RM0433, p.3189 */ STM32_CHIPID_F76xxx = 0x451, STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ + STM32_CHIPID_C031xx = 0x453, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ STM32_CHIPID_L0_CAT1 = 0x457, STM32_CHIPID_F410 = 0x458, @@ -136,6 +139,8 @@ enum stm32_chipids { }; /* Constant STM32 option bytes base memory address */ +#define STM32_C0_OPTION_BYTES_BASE ((uint32_t)0x1fff7800) + #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14) #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201c) @@ -189,6 +194,9 @@ enum stm32_chipids { #define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 #define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 +#define STM32C0_RCC_AHBENR 0x40021038 // RM0490 (revision 3), section 5.4.25 "RCC register map" +#define STM32C0_RCC_DMAEN 0x00000001 // DMAEN // RM0490 (revision 3), section 5.4.25 "RCC register map" + #define STM32F1_RCC_AHBENR 0x40021014 #define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 69c6206ee..b5e47e0d3 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -58,6 +58,30 @@ #define FLASH_OBR_OFF ((uint32_t)0x1c) #define FLASH_WRPR_OFF ((uint32_t)0x20) +// == STM32C0 == (RM0490) +// C0 Flash registers +#define FLASH_C0_REGS_ADDR ((uint32_t)0x40022000) +#define FLASH_C0_KEYR (FLASH_C0_REGS_ADDR + 0x08) +#define FLASH_C0_OPT_KEYR (FLASH_C0_REGS_ADDR + 0x0C) +#define FLASH_C0_SR (FLASH_C0_REGS_ADDR + 0x10) +#define FLASH_C0_CR (FLASH_C0_REGS_ADDR + 0x14) +#define FLASH_C0_OPTR (FLASH_C0_REGS_ADDR + 0x20) + +// C0 Flash control register +#define FLASH_C0_CR_PNB 3 +#define FLASH_C0_CR_STRT 16 +#define FLASH_C0_CR_OPTSTRT 17 +#define FLASH_C0_CR_OBL_LAUNCH 27 +#define FLASH_C0_CR_OPTLOCK 30 +#define FLASH_C0_CR_LOCK 31 + +// C0 Flash status register +#define FLASH_C0_SR_ERROR_MASK 0xC3F8 // [15:14], [9:3] +#define FLASH_C0_SR_PROGERR 3 +#define FLASH_C0_SR_WRPERR 4 +#define FLASH_C0_SR_PGAERR 5 +#define FLASH_C0_SR_BSY 16 + // == STM32F0 == #define FLASH_F0_OPTKEY1 0x45670123 #define FLASH_F0_OPTKEY2 0xcdef89ab diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c index 06edb26f3..86f01f4df 100644 --- a/src/stlink-lib/chipid.c +++ b/src/stlink-lib/chipid.c @@ -97,7 +97,9 @@ void process_chipfile(char *fname) { buf[strlen(buf) - 1] = 0; // chomp newline sscanf(buf, "%*s %n", &nc); // Match human readable flash_type with enum stm32_flash_type { }. - if (strcmp(value, "F0_F1_F3") == 0) { + if(strcmp(value, "C0") == 0) { + ts->flash_type = STM32_FLASH_TYPE_C0; + } else if (strcmp(value, "F0_F1_F3") == 0) { ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; } else if (strcmp(value, "F1_XL") == 0) { ts->flash_type = STM32_FLASH_TYPE_F1_XL; diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 3038b53e7..491cf462d 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -46,7 +46,9 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { uint32_t read_flash_cr(stlink_t *sl, uint32_t bank) { uint32_t reg, res; - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + reg = FLASH_C0_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { reg = FLASH_F7_CR; @@ -77,7 +79,10 @@ void lock_flash(stlink_t *sl) { uint32_t cr_lock_shift = 0, cr_reg = 0, n = 0, cr2_reg = 0; uint32_t cr_mask = 0xffffffffu; - if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + cr_lock_shift = FLASH_C0_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { @@ -132,8 +137,10 @@ void lock_flash(stlink_t *sl) { static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) { uint32_t sr_reg; - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + sr_reg = FLASH_C0_SR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; @@ -162,6 +169,9 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) void clear_flash_error(stlink_t *sl) { switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + write_flash_sr(sl, BANK_1, FLASH_C0_SR_ERROR_MASK); + break; case STM32_FLASH_TYPE_F0_F1_F3: write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); break; @@ -205,8 +215,10 @@ void clear_flash_error(stlink_t *sl) { uint32_t read_flash_sr(stlink_t *sl, uint32_t bank) { uint32_t res, sr_reg; - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + sr_reg = FLASH_C0_SR; + } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; @@ -238,9 +250,11 @@ uint32_t is_flash_busy(stlink_t *sl) { uint32_t sr_busy_shift; uint32_t res; - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || - (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + sr_busy_shift = FLASH_C0_SR_BSY; + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL || + sl->flash_type == STM32_FLASH_TYPE_L0_L1) { sr_busy_shift = FLASH_SR_BSY; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_busy_shift = FLASH_F4_SR_BSY; @@ -286,6 +300,12 @@ int32_t check_flash_error(stlink_t *sl) { WRPERR = PROGERR = PGAERR = 0; switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + res = read_flash_sr(sl, BANK_1) & FLASH_C0_SR_ERROR_MASK; + WRPERR = (1 << FLASH_C0_SR_WRPERR); + PROGERR = (1 << FLASH_C0_SR_PROGERR); + PGAERR = (1 << FLASH_C0_SR_PGAERR); + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; @@ -382,8 +402,11 @@ static inline uint32_t is_flash_locked(stlink_t *sl) { uint32_t cr_reg; uint32_t n; - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + cr_lock_shift = FLASH_C0_CR_LOCK; + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || + sl->flash_type == STM32_FLASH_TYPE_F1_XL) { cr_reg = FLASH_CR; cr_lock_shift = FLASH_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { @@ -429,7 +452,9 @@ static void unlock_flash(stlink_t *sl) { * definitive lock of the FPEC block until next reset. */ - if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + key_reg = FLASH_C0_KEYR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { key_reg = FLASH_KEYR; } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { key_reg = FLASH_KEYR; @@ -497,6 +522,10 @@ int32_t lock_flash_option(stlink_t *sl) { int32_t active_bit_level = 1; switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + optcr_reg = FLASH_C0_CR; + optlock_shift = FLASH_C0_CR_OPTLOCK; + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; @@ -574,6 +603,10 @@ static bool is_flash_option_locked(stlink_t *sl) { uint32_t n; switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + optcr_reg = FLASH_C0_CR; + optlock_shift = FLASH_C0_CR_OPTLOCK; + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: optcr_reg = FLASH_CR; @@ -633,6 +666,9 @@ static int32_t unlock_flash_option(stlink_t *sl) { uint32_t optkey2 = FLASH_OPTKEY2; switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + optkey_reg = FLASH_C0_OPT_KEYR; + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: optkey_reg = FLASH_OPTKEYR; @@ -726,7 +762,9 @@ void clear_flash_cr_pg(stlink_t *sl, uint32_t bank) { uint32_t cr_reg, n; uint32_t bit = FLASH_CR_PG; - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; @@ -802,8 +840,10 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, uint32_t bank) { static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { uint32_t cr_reg, val; - if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = FLASH_Gx_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; @@ -821,8 +861,10 @@ static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { static void clear_flash_cr_per(stlink_t *sl, uint32_t bank) { uint32_t cr_reg; - if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || + sl->flash_type == STM32_FLASH_TYPE_G4) { cr_reg = FLASH_Gx_CR; } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { cr_reg = FLASH_L5_NSCR; @@ -855,7 +897,10 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { uint32_t val, cr_reg, cr_strt; - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + cr_strt = 1 << FLASH_C0_CR_STRT; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_strt = 1 << FLASH_F4_CR_STRT; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { @@ -890,7 +935,11 @@ static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank) { uint32_t val, cr_reg, cr_mer, cr_pg; - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + cr_mer = 1 << FLASH_CR_MER; + cr_pg = 1 << FLASH_CR_PG; + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; cr_mer = 1 << FLASH_CR_MER; cr_pg = 1 << FLASH_CR_PG; @@ -1062,7 +1111,8 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || - sl->flash_type == STM32_FLASH_TYPE_WB_WL) { + sl->flash_type == STM32_FLASH_TYPE_WB_WL || + sl->flash_type == STM32_FLASH_TYPE_C0) { uint32_t val; unlock_flash_if(sl); set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit @@ -1107,6 +1157,14 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val |= ((flash_page & 0xFF) << 3); stlink_write_debug32(sl, FLASH_WB_CR, val); + } else if (sl->flash_type == STM32_FLASH_TYPE_C0) { + uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); + stlink_read_debug32(sl, FLASH_C0_CR, &val); + + val &= ~(0xF << FLASH_C0_CR_PNB); + val |= ((flash_page & 0xF) << FLASH_C0_CR_PNB); + + stlink_write_debug32(sl, FLASH_C0_CR, val); } set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index ea1f6d97a..0d01dfd61 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -491,12 +491,15 @@ static void set_flash_cr_pg(stlink_t *sl, uint32_t bank) { x = read_flash_cr(sl, bank); - if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { + if (sl->flash_type == STM32_FLASH_TYPE_C0) { + cr_reg = FLASH_C0_CR; + x |= (1 << FLASH_CR_PG); + } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { cr_reg = FLASH_F4_CR; - x |= 1 << FLASH_CR_PG; + x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { cr_reg = FLASH_F7_CR; - x |= 1 << FLASH_CR_PG; + x |= (1 << FLASH_CR_PG); } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { cr_reg = FLASH_L4_CR; x &= ~FLASH_L4_CR_OPBITS; @@ -528,6 +531,10 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr) { rcc = rcc_dma_mask = value = 0; switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + rcc = STM32C0_RCC_AHBENR; + rcc_dma_mask = STM32C0_RCC_DMAEN; + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: rcc = STM32F1_RCC_AHBENR; @@ -639,8 +646,9 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { - ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5\n"); + sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || + sl->flash_type == STM32_FLASH_TYPE_C0) { + ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5/C0\n"); unlock_flash_if(sl); // unlock flash if necessary set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit @@ -720,6 +728,7 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { uint32_t off; + if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || (sl->flash_type == STM32_FLASH_TYPE_L4)) { @@ -737,13 +746,14 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { + sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || + sl->flash_type == STM32_FLASH_TYPE_C0) { DLOG("Starting %3u page write\n", len / sl->flash_pgsz); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); + fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); fflush(stdout); } @@ -782,7 +792,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t uint32_t data; if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { - fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); + fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); fflush(stdout); } @@ -819,7 +829,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t if (sl->verbose >= 1) { // show progress; writing procedure is slow and previous errors are // misleading - fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, + fprintf(stdout, "\r%3u/%-3u pages written", ++write_block_count, (len + sl->flash_pgsz - 1) / sl->flash_pgsz); fflush(stdout); } @@ -856,7 +866,8 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { uint32_t dhcsr; - if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || + if ((sl->flash_type == STM32_FLASH_TYPE_C0) || + (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || (sl->flash_type == STM32_FLASH_TYPE_F7) || diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index ee03dced9..2ee45c901 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -18,6 +18,101 @@ #include "md5.h" #include "read_write.h" +/** + * Read option control register C0 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +static int32_t stlink_read_option_control_register_c0(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_debug32(sl, FLASH_C0_OPTR, option_byte); +} + +/** + * Read option bytes C0 + * @param sl + * @param option_byte + * @return 0 on success, -ve on failure. + */ +static int32_t stlink_read_option_bytes_c0(stlink_t *sl, uint32_t *option_byte) { + return stlink_read_option_control_register_c0(sl, option_byte); +} + +/** + * Write option control register C0 + * @param sl + * @param option_cr + * @return 0 on success, -ve on failure. + */ +static int32_t stlink_write_option_control_register_c0(stlink_t *sl, uint32_t option_cr) { + int32_t ret = 0; + + clear_flash_error(sl); + + if ((ret = stlink_write_debug32(sl, FLASH_C0_OPTR, option_cr))) + return ret; + + wait_flash_busy(sl); + + uint32_t cr_reg = (1 << FLASH_C0_CR_OPTSTRT); + if ((ret = stlink_write_debug32(sl, FLASH_C0_CR, cr_reg))) + return ret; + + wait_flash_busy(sl); + + if ((ret = check_flash_error(sl))) + return ret; + + // trigger the load of option bytes into option registers + cr_reg = (1 << FLASH_C0_CR_OBL_LAUNCH); + stlink_write_debug32(sl, FLASH_C0_CR, cr_reg); + + return ret; +} + +/** + * Write option bytes C0 + * @param sl + * @param addr of the memory mapped option bytes + * @param base option bytes + * @param len of option bytes + * @return 0 on success, -ve on failure. + */ +static int32_t stlink_write_option_bytes_c0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { +#if 0 + uint32_t val; + int32_t ret = 0; + (void)len; + uint32_t data; + + clear_flash_error(sl); + + write_uint32((unsigned char *)&data, *(uint32_t *)(base)); + WLOG("Writing option bytes %#10x to %#10x\n", data, addr); + stlink_write_debug32(sl, FLASH_C0_OPTR, data); + + stlink_read_debug32(sl, FLASH_C0_CR, &val); + val |= (1 << FLASH_C0_CR_OPTSTRT); + stlink_write_debug32(sl, FLASH_C0_CR, val); + + wait_flash_busy(sl); + + ret = check_flash_error(sl); + + // trigger the load of option bytes into option registers + stlink_read_debug32(sl, FLASH_C0_CR, &val); + val |= (1 << FLASH_C0_CR_OBL_LAUNCH); + stlink_write_debug32(sl, FLASH_C0_CR, val); + + return (ret); +#else + (void)addr; + (void)len; + + return stlink_write_option_control_register_c0(sl, *(uint32_t*)base); +#endif +} + /** * Read option control register F0 * @param sl @@ -745,7 +840,6 @@ int32_t stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { return stlink_read_debug32(sl, sl->option_base, option_byte); } - /** * Write option bytes * @param sl @@ -785,6 +879,9 @@ int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base } switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + ret = stlink_write_option_bytes_c0(sl, addr, base, len); + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_bytes_f0(sl, addr, base, len); @@ -870,6 +967,8 @@ int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byt } switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + return stlink_read_option_control_register_c0(sl, option_byte); case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: return stlink_read_option_control_register_f0(sl, option_byte); @@ -904,6 +1003,9 @@ int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) } switch (sl->flash_type) { + case STM32_FLASH_TYPE_C0: + ret = stlink_write_option_control_register_c0(sl, option_cr); + break; case STM32_FLASH_TYPE_F0_F1_F3: case STM32_FLASH_TYPE_F1_XL: ret = stlink_write_option_control_register_f0(sl, option_cr); @@ -1009,6 +1111,9 @@ int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { } switch (sl->chip_id) { + case STM32_CHIPID_C011xx: + case STM32_CHIPID_C031xx: + return stlink_read_option_bytes_c0(sl, option_byte); case STM32_CHIPID_F2: return stlink_read_option_bytes_f2(sl, option_byte); case STM32_CHIPID_F4: From eb083ae7539eccd3532156a829b3a8008736485b Mon Sep 17 00:00:00 2001 From: rcubee Date: Sat, 11 Nov 2023 17:40:28 +0100 Subject: [PATCH 1411/1435] removed redundant lines --- src/stlink-lib/option_bytes.c | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c index 2ee45c901..d49c346ef 100644 --- a/src/stlink-lib/option_bytes.c +++ b/src/stlink-lib/option_bytes.c @@ -79,38 +79,10 @@ static int32_t stlink_write_option_control_register_c0(stlink_t *sl, uint32_t op * @return 0 on success, -ve on failure. */ static int32_t stlink_write_option_bytes_c0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { -#if 0 - uint32_t val; - int32_t ret = 0; - (void)len; - uint32_t data; - - clear_flash_error(sl); - - write_uint32((unsigned char *)&data, *(uint32_t *)(base)); - WLOG("Writing option bytes %#10x to %#10x\n", data, addr); - stlink_write_debug32(sl, FLASH_C0_OPTR, data); - - stlink_read_debug32(sl, FLASH_C0_CR, &val); - val |= (1 << FLASH_C0_CR_OPTSTRT); - stlink_write_debug32(sl, FLASH_C0_CR, val); - - wait_flash_busy(sl); - - ret = check_flash_error(sl); - - // trigger the load of option bytes into option registers - stlink_read_debug32(sl, FLASH_C0_CR, &val); - val |= (1 << FLASH_C0_CR_OBL_LAUNCH); - stlink_write_debug32(sl, FLASH_C0_CR, val); - - return (ret); -#else (void)addr; (void)len; return stlink_write_option_control_register_c0(sl, *(uint32_t*)base); -#endif } /** From 4a7b8cdb2678e64fccedf4f49508c4f5ce80868e Mon Sep 17 00:00:00 2001 From: rcubee Date: Sat, 11 Nov 2023 18:19:04 +0100 Subject: [PATCH 1412/1435] removed the patch file itself --- c0.patch | 618 ------------------------------------------------------- 1 file changed, 618 deletions(-) delete mode 100644 c0.patch diff --git a/c0.patch b/c0.patch deleted file mode 100644 index 5b59834d6..000000000 --- a/c0.patch +++ /dev/null @@ -1,618 +0,0 @@ -diff --git a/doc/supported_devices.md b/doc/supported_devices.md -index 2e96dcd..103c7fb 100644 ---- a/doc/supported_devices.md -+++ b/doc/supported_devices.md -@@ -6,6 +6,7 @@ More commonly these are: - | Product-Family | ARM Cortex Core | Product Line | - | -------------- | --------------- | ---------------------------------------------------------- | - | STM32F0 | M0 | | -+| STM32C0 | M0+ | | - | STM32G0 | M0+ | | - | STM32L0 | M0+ | | - | STM32F10**0** | M3 | Value line | -diff --git a/inc/stm32.h b/inc/stm32.h -index cf9a8a2..017ea0a 100644 ---- a/inc/stm32.h -+++ b/inc/stm32.h -@@ -51,17 +51,18 @@ enum stm32_core_id { - /* STM32 flash types */ - enum stm32_flash_type { - STM32_FLASH_TYPE_UNKNOWN = 0, -- STM32_FLASH_TYPE_F0_F1_F3 = 1, -- STM32_FLASH_TYPE_F1_XL = 2, -- STM32_FLASH_TYPE_F2_F4 = 3, -- STM32_FLASH_TYPE_F7 = 4, -- STM32_FLASH_TYPE_G0 = 5, -- STM32_FLASH_TYPE_G4 = 6, -- STM32_FLASH_TYPE_H7 = 7, -- STM32_FLASH_TYPE_L0_L1 = 8, -- STM32_FLASH_TYPE_L4 = 9, -- STM32_FLASH_TYPE_L5_U5_H5 = 10, -- STM32_FLASH_TYPE_WB_WL = 11, -+ STM32_FLASH_TYPE_C0 = 1, -+ STM32_FLASH_TYPE_F0_F1_F3 = 2, -+ STM32_FLASH_TYPE_F1_XL = 3, -+ STM32_FLASH_TYPE_F2_F4 = 4, -+ STM32_FLASH_TYPE_F7 = 5, -+ STM32_FLASH_TYPE_G0 = 6, -+ STM32_FLASH_TYPE_G4 = 7, -+ STM32_FLASH_TYPE_H7 = 8, -+ STM32_FLASH_TYPE_L0_L1 = 9, -+ STM32_FLASH_TYPE_L4 = 10, -+ STM32_FLASH_TYPE_L5_U5_H5 = 11, -+ STM32_FLASH_TYPE_WB_WL = 12, - }; - - /* STM32 chip-ids */ -@@ -102,6 +103,7 @@ enum stm32_chipids { - STM32_CHIPID_F0 = 0x440, - STM32_CHIPID_F412 = 0x441, - STM32_CHIPID_F09x = 0x442, -+ STM32_CHIPID_C011xx = 0x443, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ - STM32_CHIPID_F0xx_SMALL = 0x444, - STM32_CHIPID_F04 = 0x445, - STM32_CHIPID_F303_HD = 0x446, /* high density */ -@@ -111,6 +113,7 @@ enum stm32_chipids { - STM32_CHIPID_H74xxx = 0x450, /* RM0433, p.3189 */ - STM32_CHIPID_F76xxx = 0x451, - STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ -+ STM32_CHIPID_C031xx = 0x453, /* RM0490 (revision 3), section 26.10.1 "DBG device ID code register (DBG_IDCODE)" */ - STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ - STM32_CHIPID_L0_CAT1 = 0x457, - STM32_CHIPID_F410 = 0x458, -@@ -136,6 +139,8 @@ enum stm32_chipids { - }; - - /* Constant STM32 option bytes base memory address */ -+#define STM32_C0_OPTION_BYTES_BASE ((uint32_t)0x1fff7800) -+ - #define STM32_F4_OPTION_BYTES_BASE ((uint32_t)0x40023c14) - - #define STM32_H7_OPTION_BYTES_BASE ((uint32_t)0x5200201c) -@@ -189,6 +194,9 @@ enum stm32_chipids { - #define STM32WB_DBGMCU_APB1FZR1_WWDG_STOP 11 - #define STM32WB_DBGMCU_APB1FZR1_IWDG_STOP 12 - -+#define STM32C0_RCC_AHBENR 0x40021038 // RM0490 (revision 3), section 5.4.25 "RCC register map" -+#define STM32C0_RCC_DMAEN 0x00000001 // DMAEN // RM0490 (revision 3), section 5.4.25 "RCC register map" -+ - #define STM32F1_RCC_AHBENR 0x40021014 - #define STM32F1_RCC_DMAEN 0x00000003 // DMA2EN | DMA1EN - -diff --git a/inc/stm32flash.h b/inc/stm32flash.h -index 69c6206..b5e47e0 100644 ---- a/inc/stm32flash.h -+++ b/inc/stm32flash.h -@@ -58,6 +58,30 @@ - #define FLASH_OBR_OFF ((uint32_t)0x1c) - #define FLASH_WRPR_OFF ((uint32_t)0x20) - -+// == STM32C0 == (RM0490) -+// C0 Flash registers -+#define FLASH_C0_REGS_ADDR ((uint32_t)0x40022000) -+#define FLASH_C0_KEYR (FLASH_C0_REGS_ADDR + 0x08) -+#define FLASH_C0_OPT_KEYR (FLASH_C0_REGS_ADDR + 0x0C) -+#define FLASH_C0_SR (FLASH_C0_REGS_ADDR + 0x10) -+#define FLASH_C0_CR (FLASH_C0_REGS_ADDR + 0x14) -+#define FLASH_C0_OPTR (FLASH_C0_REGS_ADDR + 0x20) -+ -+// C0 Flash control register -+#define FLASH_C0_CR_PNB 3 -+#define FLASH_C0_CR_STRT 16 -+#define FLASH_C0_CR_OPTSTRT 17 -+#define FLASH_C0_CR_OBL_LAUNCH 27 -+#define FLASH_C0_CR_OPTLOCK 30 -+#define FLASH_C0_CR_LOCK 31 -+ -+// C0 Flash status register -+#define FLASH_C0_SR_ERROR_MASK 0xC3F8 // [15:14], [9:3] -+#define FLASH_C0_SR_PROGERR 3 -+#define FLASH_C0_SR_WRPERR 4 -+#define FLASH_C0_SR_PGAERR 5 -+#define FLASH_C0_SR_BSY 16 -+ - // == STM32F0 == - #define FLASH_F0_OPTKEY1 0x45670123 - #define FLASH_F0_OPTKEY2 0xcdef89ab -diff --git a/src/stlink-lib/chipid.c b/src/stlink-lib/chipid.c -index 06edb26..86f01f4 100644 ---- a/src/stlink-lib/chipid.c -+++ b/src/stlink-lib/chipid.c -@@ -97,7 +97,9 @@ void process_chipfile(char *fname) { - buf[strlen(buf) - 1] = 0; // chomp newline - sscanf(buf, "%*s %n", &nc); - // Match human readable flash_type with enum stm32_flash_type { }. -- if (strcmp(value, "F0_F1_F3") == 0) { -+ if(strcmp(value, "C0") == 0) { -+ ts->flash_type = STM32_FLASH_TYPE_C0; -+ } else if (strcmp(value, "F0_F1_F3") == 0) { - ts->flash_type = STM32_FLASH_TYPE_F0_F1_F3; - } else if (strcmp(value, "F1_XL") == 0) { - ts->flash_type = STM32_FLASH_TYPE_F1_XL; -diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c -index 3038b53..491cf46 100644 ---- a/src/stlink-lib/common_flash.c -+++ b/src/stlink-lib/common_flash.c -@@ -46,7 +46,9 @@ uint32_t get_stm32l0_flash_base(stlink_t *sl) { - uint32_t read_flash_cr(stlink_t *sl, uint32_t bank) { - uint32_t reg, res; - -- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ reg = FLASH_C0_CR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - reg = FLASH_F4_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - reg = FLASH_F7_CR; -@@ -77,7 +79,10 @@ void lock_flash(stlink_t *sl) { - uint32_t cr_lock_shift = 0, cr_reg = 0, n = 0, cr2_reg = 0; - uint32_t cr_mask = 0xffffffffu; - -- if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ cr_lock_shift = FLASH_C0_CR_LOCK; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { -@@ -132,8 +137,10 @@ void lock_flash(stlink_t *sl) { - static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) { - uint32_t sr_reg; - -- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ sr_reg = FLASH_C0_SR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || -+ sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - sr_reg = FLASH_F4_SR; -@@ -162,6 +169,9 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) - - void clear_flash_error(stlink_t *sl) { - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ write_flash_sr(sl, BANK_1, FLASH_C0_SR_ERROR_MASK); -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); - break; -@@ -205,8 +215,10 @@ void clear_flash_error(stlink_t *sl) { - uint32_t read_flash_sr(stlink_t *sl, uint32_t bank) { - uint32_t res, sr_reg; - -- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ sr_reg = FLASH_C0_SR; -+ } else if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -+ (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { - sr_reg = (bank == BANK_1) ? FLASH_SR : FLASH_SR2; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - sr_reg = FLASH_F4_SR; -@@ -238,9 +250,11 @@ uint32_t is_flash_busy(stlink_t *sl) { - uint32_t sr_busy_shift; - uint32_t res; - -- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -- (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || -- (sl->flash_type == STM32_FLASH_TYPE_L0_L1)) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ sr_busy_shift = FLASH_C0_SR_BSY; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || -+ sl->flash_type == STM32_FLASH_TYPE_F1_XL || -+ sl->flash_type == STM32_FLASH_TYPE_L0_L1) { - sr_busy_shift = FLASH_SR_BSY; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - sr_busy_shift = FLASH_F4_SR_BSY; -@@ -286,6 +300,12 @@ int32_t check_flash_error(stlink_t *sl) { - WRPERR = PROGERR = PGAERR = 0; - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ res = read_flash_sr(sl, BANK_1) & FLASH_C0_SR_ERROR_MASK; -+ WRPERR = (1 << FLASH_C0_SR_WRPERR); -+ PROGERR = (1 << FLASH_C0_SR_PROGERR); -+ PGAERR = (1 << FLASH_C0_SR_PGAERR); -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; -@@ -382,8 +402,11 @@ static inline uint32_t is_flash_locked(stlink_t *sl) { - uint32_t cr_reg; - uint32_t n; - -- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -- (sl->flash_type == STM32_FLASH_TYPE_F1_XL)) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ cr_lock_shift = FLASH_C0_CR_LOCK; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3 || -+ sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - cr_reg = FLASH_CR; - cr_lock_shift = FLASH_CR_LOCK; - } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -@@ -429,7 +452,9 @@ static void unlock_flash(stlink_t *sl) { - * definitive lock of the FPEC block until next reset. - */ - -- if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ key_reg = FLASH_C0_KEYR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) { - key_reg = FLASH_KEYR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F1_XL) { - key_reg = FLASH_KEYR; -@@ -497,6 +522,10 @@ int32_t lock_flash_option(stlink_t *sl) { - int32_t active_bit_level = 1; - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ optcr_reg = FLASH_C0_CR; -+ optlock_shift = FLASH_C0_CR_OPTLOCK; -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; -@@ -574,6 +603,10 @@ static bool is_flash_option_locked(stlink_t *sl) { - uint32_t n; - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ optcr_reg = FLASH_C0_CR; -+ optlock_shift = FLASH_C0_CR_OPTLOCK; -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - optcr_reg = FLASH_CR; -@@ -633,6 +666,9 @@ static int32_t unlock_flash_option(stlink_t *sl) { - uint32_t optkey2 = FLASH_OPTKEY2; - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ optkey_reg = FLASH_C0_OPT_KEYR; -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - optkey_reg = FLASH_OPTKEYR; -@@ -726,7 +762,9 @@ void clear_flash_cr_pg(stlink_t *sl, uint32_t bank) { - uint32_t cr_reg, n; - uint32_t bit = FLASH_CR_PG; - -- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; -@@ -802,8 +840,10 @@ static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, uint32_t bank) { - static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { - uint32_t cr_reg, val; - -- if (sl->flash_type == STM32_FLASH_TYPE_G0 || -- sl->flash_type == STM32_FLASH_TYPE_G4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || -+ sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = FLASH_Gx_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { - cr_reg = FLASH_L5_NSCR; -@@ -821,8 +861,10 @@ static void set_flash_cr_per(stlink_t *sl, uint32_t bank) { - static void clear_flash_cr_per(stlink_t *sl, uint32_t bank) { - uint32_t cr_reg; - -- if (sl->flash_type == STM32_FLASH_TYPE_G0 || -- sl->flash_type == STM32_FLASH_TYPE_G4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || -+ sl->flash_type == STM32_FLASH_TYPE_G4) { - cr_reg = FLASH_Gx_CR; - } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { - cr_reg = FLASH_L5_NSCR; -@@ -855,7 +897,10 @@ static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { - static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { - uint32_t val, cr_reg, cr_strt; - -- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ cr_strt = 1 << FLASH_C0_CR_STRT; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - cr_strt = 1 << FLASH_F4_CR_STRT; - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { -@@ -890,7 +935,11 @@ static void set_flash_cr_strt(stlink_t *sl, uint32_t bank) { - static void set_flash_cr_mer(stlink_t *sl, bool v, uint32_t bank) { - uint32_t val, cr_reg, cr_mer, cr_pg; - -- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ cr_mer = 1 << FLASH_CR_MER; -+ cr_pg = 1 << FLASH_CR_PG; -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; - cr_mer = 1 << FLASH_CR_MER; - cr_pg = 1 << FLASH_CR_PG; -@@ -1062,7 +1111,8 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4 || - sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || -- sl->flash_type == STM32_FLASH_TYPE_WB_WL) { -+ sl->flash_type == STM32_FLASH_TYPE_WB_WL || -+ sl->flash_type == STM32_FLASH_TYPE_C0) { - uint32_t val; - unlock_flash_if(sl); - set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit -@@ -1107,6 +1157,14 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { - val |= ((flash_page & 0xFF) << 3); - - stlink_write_debug32(sl, FLASH_WB_CR, val); -+ } else if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); -+ stlink_read_debug32(sl, FLASH_C0_CR, &val); -+ -+ val &= ~(0xF << FLASH_C0_CR_PNB); -+ val |= ((flash_page & 0xF) << FLASH_C0_CR_PNB); -+ -+ stlink_write_debug32(sl, FLASH_C0_CR, val); - } - - set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit -diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c -index ea1f6d9..0d01dfd 100644 ---- a/src/stlink-lib/flash_loader.c -+++ b/src/stlink-lib/flash_loader.c -@@ -491,12 +491,15 @@ static void set_flash_cr_pg(stlink_t *sl, uint32_t bank) { - - x = read_flash_cr(sl, bank); - -- if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { -+ if (sl->flash_type == STM32_FLASH_TYPE_C0) { -+ cr_reg = FLASH_C0_CR; -+ x |= (1 << FLASH_CR_PG); -+ } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { - cr_reg = FLASH_F4_CR; -- x |= 1 << FLASH_CR_PG; -+ x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - cr_reg = FLASH_F7_CR; -- x |= 1 << FLASH_CR_PG; -+ x |= (1 << FLASH_CR_PG); - } else if (sl->flash_type == STM32_FLASH_TYPE_L4) { - cr_reg = FLASH_L4_CR; - x &= ~FLASH_L4_CR_OPBITS; -@@ -528,6 +531,10 @@ static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int32_t bckpRstr) { - rcc = rcc_dma_mask = value = 0; - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ rcc = STM32C0_RCC_AHBENR; -+ rcc_dma_mask = STM32C0_RCC_DMAEN; -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - rcc = STM32F1_RCC_AHBENR; -@@ -639,8 +646,9 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4 || -- sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { -- ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5\n"); -+ sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || -+ sl->flash_type == STM32_FLASH_TYPE_C0) { -+ ILOG("Starting Flash write for WB/G0/G4/L5/U5/H5/C0\n"); - - unlock_flash_if(sl); // unlock flash if necessary - set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit -@@ -720,6 +728,7 @@ int32_t stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { - - int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t addr, uint8_t *base, uint32_t len) { - uint32_t off; -+ - if ((sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || - (sl->flash_type == STM32_FLASH_TYPE_L4)) { -@@ -737,13 +746,14 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t - } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL || - sl->flash_type == STM32_FLASH_TYPE_G0 || - sl->flash_type == STM32_FLASH_TYPE_G4 || -- sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { -+ sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || -+ sl->flash_type == STM32_FLASH_TYPE_C0) { - DLOG("Starting %3u page write\n", len / sl->flash_pgsz); - for (off = 0; off < len; off += sizeof(uint32_t)) { - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { -- fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); -+ fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); - fflush(stdout); - } - -@@ -782,7 +792,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t - uint32_t data; - - if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { -- fprintf(stdout, "\r%3u/%3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); -+ fprintf(stdout, "\r%3u/%-3u pages written", (off / sl->flash_pgsz + 1), (len / sl->flash_pgsz)); - fflush(stdout); - } - -@@ -819,7 +829,7 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t - if (sl->verbose >= 1) { - // show progress; writing procedure is slow and previous errors are - // misleading -- fprintf(stdout, "\r%3u/%3u pages written", ++write_block_count, -+ fprintf(stdout, "\r%3u/%-3u pages written", ++write_block_count, - (len + sl->flash_pgsz - 1) / sl->flash_pgsz); - fflush(stdout); - } -@@ -856,7 +866,8 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t - int32_t stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { - uint32_t dhcsr; - -- if ((sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || -+ if ((sl->flash_type == STM32_FLASH_TYPE_C0) || -+ (sl->flash_type == STM32_FLASH_TYPE_F0_F1_F3) || - (sl->flash_type == STM32_FLASH_TYPE_F1_XL) || - (sl->flash_type == STM32_FLASH_TYPE_F2_F4) || - (sl->flash_type == STM32_FLASH_TYPE_F7) || -diff --git a/src/stlink-lib/option_bytes.c b/src/stlink-lib/option_bytes.c -index ee03dce..2ee45c9 100644 ---- a/src/stlink-lib/option_bytes.c -+++ b/src/stlink-lib/option_bytes.c -@@ -18,6 +18,101 @@ - #include "md5.h" - #include "read_write.h" - -+/** -+ * Read option control register C0 -+ * @param sl -+ * @param option_byte -+ * @return 0 on success, -ve on failure. -+ */ -+static int32_t stlink_read_option_control_register_c0(stlink_t *sl, uint32_t *option_byte) { -+ return stlink_read_debug32(sl, FLASH_C0_OPTR, option_byte); -+} -+ -+/** -+ * Read option bytes C0 -+ * @param sl -+ * @param option_byte -+ * @return 0 on success, -ve on failure. -+ */ -+static int32_t stlink_read_option_bytes_c0(stlink_t *sl, uint32_t *option_byte) { -+ return stlink_read_option_control_register_c0(sl, option_byte); -+} -+ -+/** -+ * Write option control register C0 -+ * @param sl -+ * @param option_cr -+ * @return 0 on success, -ve on failure. -+ */ -+static int32_t stlink_write_option_control_register_c0(stlink_t *sl, uint32_t option_cr) { -+ int32_t ret = 0; -+ -+ clear_flash_error(sl); -+ -+ if ((ret = stlink_write_debug32(sl, FLASH_C0_OPTR, option_cr))) -+ return ret; -+ -+ wait_flash_busy(sl); -+ -+ uint32_t cr_reg = (1 << FLASH_C0_CR_OPTSTRT); -+ if ((ret = stlink_write_debug32(sl, FLASH_C0_CR, cr_reg))) -+ return ret; -+ -+ wait_flash_busy(sl); -+ -+ if ((ret = check_flash_error(sl))) -+ return ret; -+ -+ // trigger the load of option bytes into option registers -+ cr_reg = (1 << FLASH_C0_CR_OBL_LAUNCH); -+ stlink_write_debug32(sl, FLASH_C0_CR, cr_reg); -+ -+ return ret; -+} -+ -+/** -+ * Write option bytes C0 -+ * @param sl -+ * @param addr of the memory mapped option bytes -+ * @param base option bytes -+ * @param len of option bytes -+ * @return 0 on success, -ve on failure. -+ */ -+static int32_t stlink_write_option_bytes_c0(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint32_t len) { -+#if 0 -+ uint32_t val; -+ int32_t ret = 0; -+ (void)len; -+ uint32_t data; -+ -+ clear_flash_error(sl); -+ -+ write_uint32((unsigned char *)&data, *(uint32_t *)(base)); -+ WLOG("Writing option bytes %#10x to %#10x\n", data, addr); -+ stlink_write_debug32(sl, FLASH_C0_OPTR, data); -+ -+ stlink_read_debug32(sl, FLASH_C0_CR, &val); -+ val |= (1 << FLASH_C0_CR_OPTSTRT); -+ stlink_write_debug32(sl, FLASH_C0_CR, val); -+ -+ wait_flash_busy(sl); -+ -+ ret = check_flash_error(sl); -+ -+ // trigger the load of option bytes into option registers -+ stlink_read_debug32(sl, FLASH_C0_CR, &val); -+ val |= (1 << FLASH_C0_CR_OBL_LAUNCH); -+ stlink_write_debug32(sl, FLASH_C0_CR, val); -+ -+ return (ret); -+#else -+ (void)addr; -+ (void)len; -+ -+ return stlink_write_option_control_register_c0(sl, *(uint32_t*)base); -+#endif -+} -+ - /** - * Read option control register F0 - * @param sl -@@ -745,7 +840,6 @@ int32_t stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { - return stlink_read_debug32(sl, sl->option_base, option_byte); - } - -- - /** - * Write option bytes - * @param sl -@@ -785,6 +879,9 @@ int32_t stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base - } - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ ret = stlink_write_option_bytes_c0(sl, addr, base, len); -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - ret = stlink_write_option_bytes_f0(sl, addr, base, len); -@@ -870,6 +967,8 @@ int32_t stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byt - } - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ return stlink_read_option_control_register_c0(sl, option_byte); - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - return stlink_read_option_control_register_f0(sl, option_byte); -@@ -904,6 +1003,9 @@ int32_t stlink_write_option_control_register32(stlink_t *sl, uint32_t option_cr) - } - - switch (sl->flash_type) { -+ case STM32_FLASH_TYPE_C0: -+ ret = stlink_write_option_control_register_c0(sl, option_cr); -+ break; - case STM32_FLASH_TYPE_F0_F1_F3: - case STM32_FLASH_TYPE_F1_XL: - ret = stlink_write_option_control_register_f0(sl, option_cr); -@@ -1009,6 +1111,9 @@ int32_t stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { - } - - switch (sl->chip_id) { -+ case STM32_CHIPID_C011xx: -+ case STM32_CHIPID_C031xx: -+ return stlink_read_option_bytes_c0(sl, option_byte); - case STM32_CHIPID_F2: - return stlink_read_option_bytes_f2(sl, option_byte); - case STM32_CHIPID_F4: From e286f243efaf73e4fec1cf99e532e695c6383316 Mon Sep 17 00:00:00 2001 From: Marcelo Barros de Almeida Date: Tue, 14 Nov 2023 00:27:19 -0300 Subject: [PATCH 1413/1435] Fixing support for U5 chips (original U5x5.chip was not handling all U5 chips ) --- config/chips/U535_U545.chip | 14 ++++++++++++++ config/chips/U55Fx_U5Gx.chip | 14 ++++++++++++++ config/chips/{U5x5.chip => U575_U585.chip} | 6 +++--- config/chips/U59x_U5Ax.chip | 14 ++++++++++++++ inc/stm32.h | 5 ++++- src/stlink-lib/common_flash.c | 12 ++++++++---- 6 files changed, 57 insertions(+), 8 deletions(-) create mode 100644 config/chips/U535_U545.chip create mode 100644 config/chips/U55Fx_U5Gx.chip rename config/chips/{U5x5.chip => U575_U585.chip} (67%) create mode 100644 config/chips/U59x_U5Ax.chip diff --git a/config/chips/U535_U545.chip b/config/chips/U535_U545.chip new file mode 100644 index 000000000..84ca3c914 --- /dev/null +++ b/config/chips/U535_U545.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32U535 / STM32U545 device +# +dev_type STM32U535_U545 +ref_manual_id 0456 +chip_id 0x455 // STM32U535/545 +flash_type L5_U5_H5 +flash_size_reg 0x0bfa07a0 +flash_pagesize 0x2000 // 8 KB +sram_size 0x44800 // 274 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/U55Fx_U5Gx.chip b/config/chips/U55Fx_U5Gx.chip new file mode 100644 index 000000000..6c7eca784 --- /dev/null +++ b/config/chips/U55Fx_U5Gx.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32U5Fx / STM32U5Gx device +# +dev_type STM32U5Fx_U5Gx +ref_manual_id 0456 +chip_id 0x476 // STM32U5Fx5/5Gx +flash_type L5_U5_H5 +flash_size_reg 0x0bfa07a0 +flash_pagesize 0x2000 // 8 KB +sram_size 0x2f4800 // 3026 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags none diff --git a/config/chips/U5x5.chip b/config/chips/U575_U585.chip similarity index 67% rename from config/chips/U5x5.chip rename to config/chips/U575_U585.chip index 82964b1c3..fa2fb86fa 100644 --- a/config/chips/U5x5.chip +++ b/config/chips/U575_U585.chip @@ -1,8 +1,8 @@ -# Chip-ID file for STM32U5x5 device +# Chip-ID file for STM32U575 / STM32U585 device # -dev_type STM32U5x5 +dev_type STM32U575_U585 ref_manual_id 0456 -chip_id 0x482 // STM32_CHIPID_U5x5 +chip_id 0x482 // STM32U575/585 flash_type L5_U5_H5 flash_size_reg 0x0bfa07a0 flash_pagesize 0x2000 // 8 KB diff --git a/config/chips/U59x_U5Ax.chip b/config/chips/U59x_U5Ax.chip new file mode 100644 index 000000000..6be20855e --- /dev/null +++ b/config/chips/U59x_U5Ax.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32U59x / STM32U5Ax device +# +dev_type STM32U59x_U5Ax +ref_manual_id 0456 +chip_id 0x481 // STM32U59x/5Ax +flash_type L5_U5_H5 +flash_size_reg 0x0bfa07a0 +flash_pagesize 0x2000 // 8 KB +sram_size 0x274800 // 2514 KB +bootrom_base 0x0bf90000 +bootrom_size 0x8000 // 32 KB +option_base 0x0 +option_size 0x0 +flags none diff --git a/inc/stm32.h b/inc/stm32.h index cf9a8a2ad..b716ac44e 100644 --- a/inc/stm32.h +++ b/inc/stm32.h @@ -111,6 +111,7 @@ enum stm32_chipids { STM32_CHIPID_H74xxx = 0x450, /* RM0433, p.3189 */ STM32_CHIPID_F76xxx = 0x451, STM32_CHIPID_F72xxx = 0x452, /* Nucleo F722ZE board */ + STM32_CHIPID_U535_U545 = 0x455, /* RM0456, p.3604 */ STM32_CHIPID_G0_CAT4 = 0x456, /* G051/G061 */ STM32_CHIPID_L0_CAT1 = 0x457, STM32_CHIPID_F410 = 0x458, @@ -126,9 +127,11 @@ enum stm32_chipids { STM32_CHIPID_L4Rx = 0x470, /* RM0432, p.2247, found on the STM32L4R9I-DISCO board */ STM32_CHIPID_L4PX = 0x471, /* RM0432, p.2247 */ STM32_CHIPID_L5x2xx = 0x472, /* RM0438, p.2157 */ + STM32_CHIPID_U5Fx_U5Gx = 0x476, /* RM0456, p.3604 */ STM32_CHIPID_G4_CAT4 = 0x479, STM32_CHIPID_H7Ax = 0x480, /* RM0455, p.2863 */ - STM32_CHIPID_U5x5 = 0x482, /* RM0456, p.2991 */ + STM32_CHIPID_U59x_U5Ax = 0x481, /* RM0456, p.3604 */ + STM32_CHIPID_U575_U585 = 0x482, /* RM0456, p.3604 */ STM32_CHIPID_H72x = 0x483, /* RM0468, p.3199 */ STM32_CHIPID_H5xx = 0x484, /* RM0481, p.3085 */ STM32_CHIPID_WB55 = 0x495, diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 3038b53e7..ab754cb77 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1082,10 +1082,12 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { val &= ~(0x7F << 3); val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_Gx_CR, val); + // STM32L5x2xx has two banks with 2k pages or single with 4k pages + // STM32H5xx, STM32U535, STM32U545, STM32U575 or STM32U585 have 2 banks with 8k pages } else if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5) { uint32_t flash_page; stlink_read_debug32(sl, FLASH_L5_NSCR, &val); - if (sl->flash_pgsz == 0x800 && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) { + if ((sl->flash_pgsz == 0x800 || sl->flash_pgsz == 0x2000) && (flashaddr - STM32_FLASH_BASE) >= sl->flash_size/2) { flash_page = (flashaddr - STM32_FLASH_BASE - sl->flash_size/2) / sl->flash_pgsz; // set bank 2 for erasure val |= (1 << FLASH_L5_NSCR_NSBKER); @@ -1094,9 +1096,11 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // set bank 1 for erasure val &= ~(1 << FLASH_L5_NSCR_NSBKER); } - // sec 6.9.9 - val &= ~(0x7F << 3); - val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); + // sec 7.9.9 for U5, 6.9.9 for L5 (for L7 we have 7 bits instead 8 bits for U5 but + // the bit position for 8th bit reserved. + // Maybe the best solution is to handle each one separately. + val &= ~(0xFF << 3); + val |= ((flash_page & 0xFF) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_L5_NSCR, val); } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); From 5df53adb2c65f100c307824034b49eccd24931f3 Mon Sep 17 00:00:00 2001 From: Marcelo Barros de Almeida Date: Tue, 14 Nov 2023 07:39:56 -0300 Subject: [PATCH 1414/1435] Missing swo and dualback flags in U6 chip models --- config/chips/U535_U545.chip | 2 +- config/chips/U55Fx_U5Gx.chip | 2 +- config/chips/U575_U585.chip | 2 +- config/chips/U59x_U5Ax.chip | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/config/chips/U535_U545.chip b/config/chips/U535_U545.chip index 84ca3c914..adc0560dd 100644 --- a/config/chips/U535_U545.chip +++ b/config/chips/U535_U545.chip @@ -11,4 +11,4 @@ bootrom_base 0x0bf90000 bootrom_size 0x8000 // 32 KB option_base 0x0 option_size 0x0 -flags none +flags swo dualbank diff --git a/config/chips/U55Fx_U5Gx.chip b/config/chips/U55Fx_U5Gx.chip index 6c7eca784..b9c79b235 100644 --- a/config/chips/U55Fx_U5Gx.chip +++ b/config/chips/U55Fx_U5Gx.chip @@ -11,4 +11,4 @@ bootrom_base 0x0bf90000 bootrom_size 0x8000 // 32 KB option_base 0x0 option_size 0x0 -flags none +flags swo dualbank diff --git a/config/chips/U575_U585.chip b/config/chips/U575_U585.chip index fa2fb86fa..6724d00f5 100644 --- a/config/chips/U575_U585.chip +++ b/config/chips/U575_U585.chip @@ -11,4 +11,4 @@ bootrom_base 0x0bf90000 bootrom_size 0x10000 // 64 KB option_base 0x0 option_size 0x0 -flags none +flags swo dualbank diff --git a/config/chips/U59x_U5Ax.chip b/config/chips/U59x_U5Ax.chip index 6be20855e..9b45a411c 100644 --- a/config/chips/U59x_U5Ax.chip +++ b/config/chips/U59x_U5Ax.chip @@ -11,4 +11,4 @@ bootrom_base 0x0bf90000 bootrom_size 0x8000 // 32 KB option_base 0x0 option_size 0x0 -flags none +flags swo dualbank From 3fd714052485156f7be332d0da1d8bbc30ccbce8 Mon Sep 17 00:00:00 2001 From: rcubee Date: Tue, 14 Nov 2023 17:30:00 +0100 Subject: [PATCH 1415/1435] forgot to include these --- config/chips/C011xx.chip | 14 ++++++++++++++ config/chips/C031xx.chip | 14 ++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 config/chips/C011xx.chip create mode 100644 config/chips/C031xx.chip diff --git a/config/chips/C011xx.chip b/config/chips/C011xx.chip new file mode 100644 index 000000000..9124c6a1e --- /dev/null +++ b/config/chips/C011xx.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32C011xx device +# +dev_type STM32C011xx +ref_manual_id 0490 +chip_id 0x453 // STM32_CHIPID_C011xx +flash_type C0 +flash_size_reg 0x1fff75a0 +flash_pagesize 0x800 // 2 KB +sram_size 0x1800 // 6 KB +bootrom_base 0x1fff0000 +bootrom_size 0x1800 // 6 KB +option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE +option_size 0x80 // 128 B +flags none diff --git a/config/chips/C031xx.chip b/config/chips/C031xx.chip new file mode 100644 index 000000000..30017ae90 --- /dev/null +++ b/config/chips/C031xx.chip @@ -0,0 +1,14 @@ +# Chip-ID file for STM32C031xx device +# +dev_type STM32C031xx +ref_manual_id 0490 +chip_id 0x453 // STM32_CHIPID_C031xx +flash_type C0 +flash_size_reg 0x1fff75a0 +flash_pagesize 0x800 // 2 KB +sram_size 0x3000 // 12 KB +bootrom_base 0x1fff0000 +bootrom_size 0x1800 // 6 KB +option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE +option_size 0x80 // 128 B +flags none From cf840b5f3d8d4154efb8058adeddb20e14c934cd Mon Sep 17 00:00:00 2001 From: rcubee Date: Tue, 14 Nov 2023 17:38:12 +0100 Subject: [PATCH 1416/1435] fixed formatting --- config/chips/C011xx.chip | 4 ++-- config/chips/C031xx.chip | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/config/chips/C011xx.chip b/config/chips/C011xx.chip index 9124c6a1e..b961a18f8 100644 --- a/config/chips/C011xx.chip +++ b/config/chips/C011xx.chip @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB sram_size 0x1800 // 6 KB bootrom_base 0x1fff0000 bootrom_size 0x1800 // 6 KB -option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE -option_size 0x80 // 128 B +option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE +option_size 0x80 // 128 B flags none diff --git a/config/chips/C031xx.chip b/config/chips/C031xx.chip index 30017ae90..921c1f1fa 100644 --- a/config/chips/C031xx.chip +++ b/config/chips/C031xx.chip @@ -9,6 +9,6 @@ flash_pagesize 0x800 // 2 KB sram_size 0x3000 // 12 KB bootrom_base 0x1fff0000 bootrom_size 0x1800 // 6 KB -option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE -option_size 0x80 // 128 B +option_base 0x1fff7800 // STM32_C0_OPTION_BYTES_BASE +option_size 0x80 // 128 B flags none From 0d16dbac9a7cb89dddc92f1c5b1a1274362d6906 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Wed, 22 Nov 2023 01:13:44 +0100 Subject: [PATCH 1417/1435] CodeQL Workflow Maintenance - Removed incompatible workflow - Updated existing workflow --- .github/workflows/codeql-analysis.yml | 14 +-- .github/workflows/codeql-buildscript.sh | 6 -- .github/workflows/codeql.yml | 126 ------------------------ .github/workflows/fail_on_error.py | 34 ------- 4 files changed, 7 insertions(+), 173 deletions(-) delete mode 100644 .github/workflows/codeql-buildscript.sh delete mode 100644 .github/workflows/codeql.yml delete mode 100755 .github/workflows/fail_on_error.py diff --git a/.github/workflows/codeql-analysis.yml b/.github/workflows/codeql-analysis.yml index 55a21294f..94f256249 100644 --- a/.github/workflows/codeql-analysis.yml +++ b/.github/workflows/codeql-analysis.yml @@ -13,12 +13,12 @@ name: "CodeQL" on: push: - branches: [ testing, develop, master ] + branches: [testing, develop, master] pull_request: # The branches below must be a subset of the branches above - branches: [ testing, develop ] + branches: [testing, develop] schedule: - - cron: '00 20 * * 1' + - cron: "00 20 * * 1" jobs: analyze: @@ -28,7 +28,7 @@ jobs: strategy: fail-fast: false matrix: - language: [ 'cpp' ] + language: ["cpp"] # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python' ] # Learn more: # https://docs.github.com/en/free-pro-team@latest/github/finding-security-vulnerabilities-and-errors-in-your-code/configuring-code-scanning#changing-the-languages-that-are-analyzed @@ -41,7 +41,7 @@ jobs: # Initializes the CodeQL tools for scanning. - name: Initialize CodeQL - uses: github/codeql-action/init@v1 + uses: github/codeql-action/init@v2 with: languages: ${{ matrix.language }} # If you wish to specify custom queries, you can do so here or in a config file. @@ -52,7 +52,7 @@ jobs: # Autobuild attempts to build any compiled languages (C/C++, C#, or Java). # If this step fails, then you should remove it and run the build manually (see below) - name: Autobuild - uses: github/codeql-action/autobuild@v1 + uses: github/codeql-action/autobuild@v2 # ℹ️ Command-line programs to run using the OS shell. # 📚 https://git.io/JvXDl @@ -66,4 +66,4 @@ jobs: # make release - name: Perform CodeQL Analysis - uses: github/codeql-action/analyze@v1 + uses: github/codeql-action/analyze@v2 diff --git a/.github/workflows/codeql-buildscript.sh b/.github/workflows/codeql-buildscript.sh deleted file mode 100644 index d626d4283..000000000 --- a/.github/workflows/codeql-buildscript.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/usr/bin/env bash - -sudo apt-get -y update -sudo apt-get -y install libusb-1.0 libusb-1.0-0-dev libgtk-3-dev -make clean -make release -j$(nproc) diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml deleted file mode 100644 index 816492278..000000000 --- a/.github/workflows/codeql.yml +++ /dev/null @@ -1,126 +0,0 @@ -# For most projects, this workflow file will not need changing; you simply need -# to commit it to your repository. -# -# You may wish to alter this file to override the set of languages analyzed, -# or to provide custom queries or build logic. -# -# ******** NOTE ******** -# We have attempted to detect the languages in your repository. Please check -# the `language` matrix defined below to confirm you have the correct set of -# supported CodeQL languages. -# -name: "CodeQL" - -on: - # push: - # branches: [ "main", "master" ] - schedule: - - cron: '0 0 * * *' - pull_request: - branches: '*' - -jobs: - analyze: - name: Analyze - # Runner size impacts CodeQL analysis time. To learn more, please see: - # - https://gh.io/recommended-hardware-resources-for-running-codeql - # - https://gh.io/supported-runners-and-hardware-resources - # - https://gh.io/using-larger-runners - # Consider using larger runners for possible analysis time improvements. - runs-on: ${{ (matrix.language == 'swift' && 'macos-latest') || 'ubuntu-20.04' }} - timeout-minutes: ${{ (matrix.language == 'swift' && 120) || 360 }} - permissions: - actions: read - contents: read - security-events: write - - strategy: - fail-fast: false - matrix: - language: [ 'cpp' ] - # CodeQL supports [ 'cpp', 'csharp', 'go', 'java', 'javascript', 'python', 'ruby', 'swift' ] - # Use only 'java' to analyze code written in Java, Kotlin or both - # Use only 'javascript' to analyze code written in JavaScript, TypeScript or both - # Learn more about CodeQL language support at https://aka.ms/codeql-docs/language-support - - steps: - - name: Checkout repository - uses: actions/checkout@v3 - with: - submodules: recursive - - # Initializes the CodeQL tools for scanning. - - name: Initialize CodeQL - uses: github/codeql-action/init@v2 - with: - languages: ${{ matrix.language }} - # If you wish to specify custom queries, you can do so here or in a config file. - # By default, queries listed here will override any specified in a config file. - # Prefix the list here with "+" to use these queries and those in the config file. - - # For more details on CodeQL's query packs, refer to: https://docs.github.com/en/code-security/code-scanning/automatically-scanning-your-code-for-vulnerabilities-and-errors/configuring-code-scanning#using-queries-in-ql-packs - # queries: security-extended,security-and-quality - queries: security-and-quality - - - # Autobuild attempts to build any compiled languages (C/C++, C#, Go, Java, or Swift). - # If this step fails, then you should remove it and run the build manually (see below) - #- name: Autobuild - # uses: github/codeql-action/autobuild@v2 - - # ℹ️ Command-line programs to run using the OS shell. - # 📚 See https://docs.github.com/en/actions/using-workflows/workflow-syntax-for-github-actions#jobsjob_idstepsrun - - # If the Autobuild fails above, remove it and uncomment the following three lines. - # modify them (or add more) to build your code if your project, please refer to the EXAMPLE below for guidance. - - - run: | - ./.github/workflows/codeql-buildscript.sh - - - name: Perform CodeQL Analysis - uses: github/codeql-action/analyze@v2 - with: - category: "/language:${{matrix.language}}" - upload: false - id: step1 - - # Filter out rules with low severity or high false positve rate - # Also filter out warnings in third-party code - - name: Filter out unwanted errors and warnings - uses: advanced-security/filter-sarif@v1 - with: - patterns: | - -**:cpp/path-injection - -**:cpp/world-writable-file-creation - -**:cpp/poorly-documented-function - -**:cpp/potentially-dangerous-function - -**:cpp/use-of-goto - -**:cpp/integer-multiplication-cast-to-long - -**:cpp/comparison-with-wider-type - -**:cpp/leap-year/* - -**:cpp/ambiguously-signed-bit-field - -**:cpp/suspicious-pointer-scaling - -**:cpp/suspicious-pointer-scaling-void - -**:cpp/unsigned-comparison-zero - -**/cmake*/Modules/** - input: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif - output: ${{ steps.step1.outputs.sarif-output }}/cpp.sarif - - - name: Upload CodeQL results to code scanning - uses: github/codeql-action/upload-sarif@v2 - with: - sarif_file: ${{ steps.step1.outputs.sarif-output }} - category: "/language:${{matrix.language}}" - - - name: Upload CodeQL results as an artifact - if: success() || failure() - uses: actions/upload-artifact@v3 - with: - name: codeql-results - path: ${{ steps.step1.outputs.sarif-output }} - retention-days: 5 - - - name: Fail if an error is found - run: | - ./.github/workflows/fail_on_error.py \ - ${{ steps.step1.outputs.sarif-output }}/cpp.sarif diff --git a/.github/workflows/fail_on_error.py b/.github/workflows/fail_on_error.py deleted file mode 100755 index 29791742b..000000000 --- a/.github/workflows/fail_on_error.py +++ /dev/null @@ -1,34 +0,0 @@ -#!/usr/bin/env python3 - -import json -import sys - -# Return whether SARIF file contains error-level results -def codeql_sarif_contain_error(filename): - with open(filename, 'r') as f: - s = json.load(f) - - for run in s.get('runs', []): - rules_metadata = run['tool']['driver']['rules'] - if not rules_metadata: - rules_metadata = run['tool']['extensions'][0]['rules'] - - for res in run.get('results', []): - if 'ruleIndex' in res: - rule_index = res['ruleIndex'] - elif 'rule' in res and 'index' in res['rule']: - rule_index = res['rule']['index'] - else: - continue - try: - rule_level = rules_metadata[rule_index]['defaultConfiguration']['level'] - except IndexError as e: - print(e, rule_index, len(rules_metadata)) - else: - if rule_level == 'error': - return True - return False - -if __name__ == "__main__": - if codeql_sarif_contain_error(sys.argv[1]): - sys.exit(1) From 033007fd2713aba630d28c706499959dc8792277 Mon Sep 17 00:00:00 2001 From: Mirko Matonti Date: Thu, 23 Nov 2023 17:46:09 +0000 Subject: [PATCH 1418/1435] pr adjustment --- src/stlink-lib/common_flash.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 5005a632f..7172352ee 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1312,7 +1312,7 @@ int32_t stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { */ /* In case the address is within the OTP area we use a different flash method */ - if(addr >= sl->otp_base && addr <= sl->otp_base + sl->otp_size) { + if(addr >= sl->otp_base && addr < sl->otp_base + sl->otp_size) { err = stlink_write_otp(sl, addr, mf.base, (num_empty == mf.len) ? (uint32_t)mf.len : (uint32_t)mf.len - num_empty); } else { @@ -1404,7 +1404,7 @@ int32_t stlink_check_address_range_validity_otp(stlink_t *sl, stm32_addr_t addr, ELOG("Invalid address, it should be within 0x%08x - 0x%08x\n", sl->otp_base, logvar); return (-1); } - if ((addr + size) > (sl->otp_base + sl->otp_size)) { + if ((addr + size) >= (sl->otp_base + sl->otp_size)) { logvar = sl->otp_base + sl->otp_size - addr; ELOG("The size exceeds the size of the OTP Area (0x%08x bytes available)\n", logvar); return (-1); @@ -1431,7 +1431,7 @@ int32_t stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, uint3 int32_t ret; flash_loader_t fl; ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", len, len, addr, addr); - + // check addr range is inside the flash stlink_calculate_pagesize(sl, addr); From 7dcb1302d8b91b2217c4ce50cb255aa8e78ab001 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 24 Nov 2023 18:21:31 +0100 Subject: [PATCH 1419/1435] Fixes for STM32H7 & STM32G0B1 devices - Fixed flash lock for STM32H7 dual bank devices - Fixed flash erase issue on STM32G0B1 (Closes #1321) --- src/stlink-lib/calculate.c | 2 +- src/stlink-lib/common_flash.c | 28 ++++++++++++---------------- 2 files changed, 13 insertions(+), 17 deletions(-) diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index a7344e0b0..1230875fd 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -66,7 +66,7 @@ uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { if (sl->chip_id == STM32_CHIPID_L4 || sl->chip_id == STM32_CHIPID_L496x_L4A6x || sl->chip_id == STM32_CHIPID_L4Rx) { - // this chip use dual banked flash + // these chips use dual bank flash if (flashopt & (uint32_t)(1lu << FLASH_L4_OPTR_DUALBANK)) { uint32_t banksize = sl->flash_size / 2; diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 6f2a47f43..ef6b8370c 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -101,6 +101,11 @@ void lock_flash(stlink_t *sl) { cr_lock_shift = FLASH_Gx_CR_LOCK; } else if (sl->flash_type == STM32_FLASH_TYPE_H7) { cr_reg = FLASH_H7_CR1; + if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { + cr2_reg = FLASH_H7_CR2; + } + cr_lock_shift = FLASH_H7_CR_LOCK; + cr_mask = ~(1u << FLASH_H7_CR_SER); } else if (sl->flash_type == STM32_FLASH_TYPE_L0_L1) { cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; cr_lock_shift = FLASH_L0_PELOCK; @@ -113,11 +118,6 @@ void lock_flash(stlink_t *sl) { } else if (sl->flash_type == STM32_FLASH_TYPE_WB_WL) { cr_reg = FLASH_WB_CR; cr_lock_shift = FLASH_WB_CR_LOCK; - if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { - cr2_reg = FLASH_H7_CR2; - } - cr_lock_shift = FLASH_H7_CR_LOCK; - cr_mask = ~(1u << FLASH_H7_CR_SER); } else { ELOG("unsupported flash method, abort\n"); return; @@ -1014,11 +1014,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { unlock_flash_if(sl); // select the page to erase - if ((sl->chip_id == STM32_CHIPID_L4) || - (sl->chip_id == STM32_CHIPID_L43x_L44x) || - (sl->chip_id == STM32_CHIPID_L45x_L46x) || - (sl->chip_id == STM32_CHIPID_L496x_L4A6x) || - (sl->chip_id == STM32_CHIPID_L4Rx)) { + if (sl->flash_type == STM32_FLASH_TYPE_L4) { // calculate the actual bank+page from the address uint32_t page = calculate_L4_page(sl, flashaddr); @@ -1121,16 +1117,16 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { if (sl->flash_type == STM32_FLASH_TYPE_G0) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, FLASH_Gx_CR, &val); - // sec 3.7.5 - PNB[5:0] is offset by 3. PER is 0x2. - val &= ~(0x3F << 3); - val |= ((flash_page & 0x3F) << 3) | (1 << FLASH_CR_PER); + // sec 3.7.5 - PNB[9:0] is offset by 3. PER is 0x2. + val &= ~(0x3FF << 3); + val |= ((flash_page & 0x3FF) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_Gx_CR, val); } else if (sl->flash_type == STM32_FLASH_TYPE_G4) { uint32_t flash_page = ((flashaddr - STM32_FLASH_BASE) / sl->flash_pgsz); stlink_read_debug32(sl, FLASH_Gx_CR, &val); - // sec 3.7.5 - PNB[6:0] is offset by 3. PER is 0x2. - val &= ~(0x7F << 3); - val |= ((flash_page & 0x7F) << 3) | (1 << FLASH_CR_PER); + // sec 3.7.5 - PNB[9:0] is offset by 3. PER is 0x2. + val &= ~(0x7FF << 3); + val |= ((flash_page & 0x7FF) << 3) | (1 << FLASH_CR_PER); stlink_write_debug32(sl, FLASH_Gx_CR, val); // STM32L5x2xx has two banks with 2k pages or single with 4k pages // STM32H5xx, STM32U535, STM32U545, STM32U575 or STM32U585 have 2 banks with 8k pages From 3efa7932fb7f062f31693c6a2a00941ecf64431b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Fri, 24 Nov 2023 20:22:50 +0100 Subject: [PATCH 1420/1435] Fixed memory allocation for stlink-gui (Closes #1356) --- src/stlink-gui/gui.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-gui/gui.c b/src/stlink-gui/gui.c index e3eec34b8..51ee293e8 100644 --- a/src/stlink-gui/gui.c +++ b/src/stlink-gui/gui.c @@ -313,7 +313,7 @@ static gpointer stlink_gui_populate_filemem_view(gpointer data) { goto out_input; } - gui->file_mem.size = (gsize) file_info; + gui->file_mem.size = file_size; gui->file_mem.memory = g_malloc(gui->file_mem.size); for (off = 0; off < (gint)gui->file_mem.size; off += MEM_READ_SIZE) { From ba335a47ab3ad820461ac0175dc0d540090c978c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 27 Nov 2023 22:00:27 +0100 Subject: [PATCH 1421/1435] STM32F76xxx: Added flashing in dual bank mode (Closes #1174) --- inc/stlink.h | 28 ++++++----- inc/stm32flash.h | 59 +++++++++++----------- src/stlink-lib/calculate.c | 8 ++- src/stlink-lib/common.c | 94 ++++++++++++++++++++++++++++++++++- src/stlink-lib/common_flash.c | 4 +- src/stlink-lib/flash_loader.c | 4 +- 6 files changed, 145 insertions(+), 52 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 557a9eeaa..920822a85 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -199,23 +199,23 @@ struct _stlink { // transport layer verboseness: 0 for no debug info, 10 for lots int32_t verbose; int32_t opt; - uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID - uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram - enum target_state core_stat; // set by stlink_status() + uint32_t core_id; // set by stlink_core_id(), result from STLINK_DEBUGREADCOREID + uint32_t chip_id; // set by stlink_load_device_params(), used to identify flash and sram + enum target_state core_stat; // set by stlink_status() char serial[STLINK_SERIAL_BUFFER_SIZE]; - int32_t freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR + int32_t freq; // set by stlink_open_usb(), values: STLINK_SWDCLK_xxx_DIVISOR enum stm32_flash_type flash_type; // stlink_chipid_params.flash_type, set by stlink_load_device_params(), values: STM32_FLASH_TYPE_xx - stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() - uint32_t flash_size; // calculated by stlink_load_device_params() - uint32_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() + stm32_addr_t flash_base; // STM32_FLASH_BASE, set by stlink_load_device_params() + uint32_t flash_size; // calculated by stlink_load_device_params() + uint32_t flash_pgsz; // stlink_chipid_params.flash_pagesize, set by stlink_load_device_params() /* sram settings */ - stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() - uint32_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() + stm32_addr_t sram_base; // STM32_SRAM_BASE, set by stlink_load_device_params() + uint32_t sram_size; // stlink_chipid_params.sram_size, set by stlink_load_device_params() /* option settings */ stm32_addr_t option_base; @@ -224,14 +224,16 @@ struct _stlink { // bootloader // sys_base and sys_size are not used by the tools, but are only there to download the bootloader code // (see tests/sg.c) - stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() - uint32_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() + stm32_addr_t sys_base; // stlink_chipid_params.bootrom_base, set by stlink_load_device_params() + uint32_t sys_size; // stlink_chipid_params.bootrom_size, set by stlink_load_device_params() struct stlink_version_ version; - uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx + uint32_t chip_flags; // stlink_chipid_params.flags, set by stlink_load_device_params(), values: CHIP_F_xxx - uint32_t max_trace_freq; // set by stlink_open_usb() + uint32_t max_trace_freq; // set by stlink_open_usb() + + bool dual_bank; // set for F7xxx devices by reading optcr uint32_t otp_base; uint32_t otp_size; diff --git a/inc/stm32flash.h b/inc/stm32flash.h index b5e47e0d3..4fed8b597 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -142,6 +142,7 @@ #define FLASH_F7_OPTCR_START 1 #define FLASH_F7_OPTCR1_BOOT_ADD0 0 #define FLASH_F7_OPTCR1_BOOT_ADD1 16 +#define FLASH_F7_OPTCR_DBANK (29) /* FLASH_OPTCR Dual Bank Mode */ // F7 Flash control register #define FLASH_F7_CR_STRT 16 @@ -152,12 +153,12 @@ // F7 Flash status register #define FLASH_F7_SR_BSY 16 -#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ -#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ -#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ -#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ -#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ -#define FLASH_F7_SR_EOP 0 /* End of operation */ +#define FLASH_F7_SR_ERS_ERR 7 /* Erase Sequence Error */ +#define FLASH_F7_SR_PGP_ERR 6 /* Programming parallelism error */ +#define FLASH_F7_SR_PGA_ERR 5 /* Programming alignment error */ +#define FLASH_F7_SR_WRP_ERR 4 /* Write protection error */ +#define FLASH_F7_SR_OP_ERR 1 /* Operation error */ +#define FLASH_F7_SR_EOP 0 /* End of operation */ #define FLASH_F7_SR_ERROR_MASK \ ((1 << FLASH_F7_SR_ERS_ERR) | (1 << FLASH_F7_SR_PGP_ERR) | \ (1 << FLASH_F7_SR_PGA_ERR) | (1 << FLASH_F7_SR_WRP_ERR) | \ @@ -196,8 +197,8 @@ #define FLASH_Gx_SR_PROGERR (3) #define FLASH_Gx_SR_WRPERR (4) #define FLASH_Gx_SR_PGAERR (5) -#define FLASH_Gx_SR_BSY (16) /* FLASH_SR Busy */ -#define FLASH_Gx_SR_EOP (0) /* FLASH_EOP End of Operation */ +#define FLASH_Gx_SR_BSY (16) /* FLASH_SR Busy */ +#define FLASH_Gx_SR_EOP (0) /* FLASH_EOP End of Operation */ // == STM32G0 == (RM0444 Table 1, sec. 3.7) // Mostly the same as G4 chips, but the notation @@ -272,8 +273,8 @@ #define FLASH_H7_SR_WRPERR 17 #define FLASH_H7_SR_PGSERR 18 #define FLASH_H7_SR_STRBERR 19 -#define FLASH_H7_SR_ERROR_MASK \ - ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ +#define FLASH_H7_SR_ERROR_MASK \ + ((1 << FLASH_H7_SR_PGSERR) | (1 << FLASH_H7_SR_STRBERR) | \ (1 << FLASH_H7_SR_WRPERR)) // == STM32L0/L1/L4/L5 == @@ -332,27 +333,27 @@ #define FLASH_L4_OPTR (FLASH_REGS_ADDR + 0x20) // L4 Flash status register -#define FLASH_L4_SR_ERROR_MASK 0x3f8 /* SR [9:3] */ +#define FLASH_L4_SR_ERROR_MASK 0x3f8 // SR [9:3] #define FLASH_L4_SR_PROGERR 3 #define FLASH_L4_SR_WRPERR 4 #define FLASH_L4_SR_PGAERR 5 #define FLASH_L4_SR_BSY 16 // L4 Flash control register -#define FLASH_L4_CR_LOCK 31 /* Lock control register */ -#define FLASH_L4_CR_OPTLOCK 30 /* Lock option bytes */ -#define FLASH_L4_CR_PG 0 /* Program */ -#define FLASH_L4_CR_PER 1 /* Page erase */ -#define FLASH_L4_CR_MER1 2 /* Bank 1 erase */ -#define FLASH_L4_CR_MER2 15 /* Bank 2 erase */ -#define FLASH_L4_CR_STRT 16 /* Start command */ -#define FLASH_L4_CR_OPTSTRT 17 /* Start writing option bytes */ -#define FLASH_L4_CR_BKER 11 /* Bank select for page erase */ -#define FLASH_L4_CR_PNB 3 /* Page number (8 bits) */ -#define FLASH_L4_CR_OBL_LAUNCH 27 /* Option bytes reload */ +#define FLASH_L4_CR_LOCK 31 /* Lock control register */ +#define FLASH_L4_CR_OPTLOCK 30 /* Lock option bytes */ +#define FLASH_L4_CR_PG 0 /* Program */ +#define FLASH_L4_CR_PER 1 /* Page erase */ +#define FLASH_L4_CR_MER1 2 /* Bank 1 erase */ +#define FLASH_L4_CR_MER2 15 /* Bank 2 erase */ +#define FLASH_L4_CR_STRT 16 /* Start command */ +#define FLASH_L4_CR_OPTSTRT 17 /* Start writing option bytes */ +#define FLASH_L4_CR_BKER 11 /* Bank select for page erase */ +#define FLASH_L4_CR_PNB 3 /* Page number (8 bits) */ +#define FLASH_L4_CR_OBL_LAUNCH 27 /* Option bytes reload */ // Bits requesting flash operations (useful when we want to clear them) -#define FLASH_L4_CR_OPBITS \ - (uint32_t)((1lu << FLASH_L4_CR_PG) | (1lu << FLASH_L4_CR_PER) | \ +#define FLASH_L4_CR_OPBITS \ + (uint32_t)((1lu << FLASH_L4_CR_PG) | (1lu << FLASH_L4_CR_PER) | \ (1lu << FLASH_L4_CR_MER1) | (1lu << FLASH_L4_CR_MER1)) // Page is fully specified by BKER and PNB #define FLASH_L4_CR_PAGEMASK (uint32_t)(0x1fflu << FLASH_L4_CR_PNB) @@ -428,10 +429,10 @@ #define FLASH_WB_CR_LOCK (31) /* Lock */ // WB Flash status register -#define FLASH_WB_SR_ERROR_MASK (0x3f8) /* SR [9:3] */ -#define FLASH_WB_SR_PROGERR (3) /* Programming alignment error */ -#define FLASH_WB_SR_WRPERR (4) /* Write protection error */ -#define FLASH_WB_SR_PGAERR (5) /* Programming error */ -#define FLASH_WB_SR_BSY (16) /* Busy */ +#define FLASH_WB_SR_ERROR_MASK (0x3f8) // SR [9:3] +#define FLASH_WB_SR_PROGERR (3) /* Programming alignment error */ +#define FLASH_WB_SR_WRPERR (4) /* Write protection error */ +#define FLASH_WB_SR_PGAERR (5) /* Programming error */ +#define FLASH_WB_SR_BSY (16) /* Busy */ #endif // STM32FLASH_H diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index 1230875fd..a8a66a844 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -36,7 +36,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr) { } } -uint32_t calculate_F7_sectornum(uint32_t flashaddr) { +uint32_t calculate_F7_sectornum_old(uint32_t flashaddr) { flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address if (flashaddr < 0x20000) { @@ -49,10 +49,8 @@ uint32_t calculate_F7_sectornum(uint32_t flashaddr) { } uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, uint32_t bank) { - flashaddr &= - ~((bank == BANK_1) - ? STM32_FLASH_BASE - : STM32_H7_FLASH_BANK2_BASE); // sector holding the flash address + // sector holding the flash address + flashaddr &= ~((bank == BANK_1) ? STM32_FLASH_BASE : STM32_H7_FLASH_BANK2_BASE); return (flashaddr / sl->flash_pgsz); } diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 337fe6efa..4ff90ef3d 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -318,6 +318,19 @@ int32_t stlink_load_device_params(stlink_t *sl) { } } + // F76xxx device with dual bank + if (sl->chip_id == STM32_CHIPID_F76xxx) { + // Check the nDBANK bit in OPTCR + uint32_t optcr; + stlink_read_option_control_register32(sl, & optcr); + + if (!(optcr & (1 << STM32F7_FLASH_OPTCR_DBANK))) + { + sl->dual_bank = true; + } + DLOG("*** stm32f76xx dual-bank %d ***\n", sl->dual_bank); + } + // H7 devices with small flash has one bank if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && sl->flash_type == STM32_FLASH_TYPE_H7) { @@ -830,8 +843,87 @@ int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *bu return (ret); } +/* STM32F7 Series Flash memory dual bank mode + * See application note AN4826 pp.18 + */ + +struct sectors_f7 { + int sector; + uint32_t base; + uint32_t size; +}; + +static const struct sectors_f7 f7_single[] = { + { 0, 0x08000000, 0x8000 }, + { 1, 0x08008000, 0x8000 }, + { 2, 0x08010000, 0x8000 }, + { 3, 0x08018000, 0x8000 }, + { 4, 0x08020000, 0x20000 }, + { 5, 0x08040000, 0x40000 }, + { 6, 0x08080000, 0x40000 }, + { 7, 0x080C0000, 0x40000 }, + { 0, 0, 0 }, +}; + +static const struct sectors_f7 f7_dual[] = { + { 0, 0x08000000, 0x4000 }, + { 1, 0x08004000, 0x4000 }, + { 2, 0x08008000, 0x4000 }, + { 3, 0x0800C000, 0x4000 }, + { 4, 0x08010000, 0x10000 }, + { 5, 0x08020000, 0x20000 }, + { 6, 0x08040000, 0x20000 }, + { 7, 0x08060000, 0x20000 }, + { 8, 0x08080000, 0x20000 }, + { 9, 0x080A0000, 0x20000 }, + { 10, 0x080C0000, 0x20000 }, + { 11, 0x080E0000, 0x20000 }, + { 12, 0x08100000, 0x4000 }, + { 13, 0x08104000, 0x4000 }, + { 14, 0x08108000, 0x4000 }, + { 15, 0x0810C000, 0x4000 }, + { 16, 0x08110000, 0x10000 }, + { 17, 0x08120000, 0x20000 }, + { 18, 0x08140000, 0x20000 }, + { 19, 0x08160000, 0x20000 }, + { 20, 0x08180000, 0x20000 }, + { 21, 0x081A0000, 0x20000 }, + { 22, 0x081C0000, 0x20000 }, + { 23, 0x081E0000, 0x20000 }, + { 0, 0, 0 }, +}; + +static const struct sectors_f7 *get_f7_info(stlink_t *sl) { + return sl->dual_bank ? f7_dual : f7_single; +} + +static const struct sectors_f7 *find_sector(stlink_t *sl, uint32_t flashaddr) { + for (const struct sectors_f7 *s = get_f7_info(sl); s->base; s++) { + const uint32_t end = s->base + s->size; + if ((s->base <= flashaddr) && (flashaddr < end)) { + return s; + } + } + fprintf(stderr, "Bad address %#x\n", flashaddr); + exit(0); +} + +uint32_t calculate_F7_sectornum(stlink_t *sl, uint32_t flashaddr) { + if (sl->chip_id == STM32_CHIPID_F76xxx) { + const struct sectors_f7 *s = find_sector(sl, flashaddr); + return s->sector; + } + return calculate_F7_sectornum_old(flashaddr); +} + // 291 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { + + if (sl->chip_id == STM32_CHIPID_F76xxx) { + const struct sectors_f7 *s = find_sector(sl, flashaddr); + return s->size; + } + if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || @@ -857,7 +949,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { } } else if (sl->chip_id == STM32_CHIPID_F7 || sl->chip_id == STM32_CHIPID_F76xxx) { - uint32_t sector = calculate_F7_sectornum(flashaddr); + uint32_t sector = calculate_F7_sectornum(sl, flashaddr); if (sector < 4) { sl->flash_pgsz = 0x8000; diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index ef6b8370c..fc377a471 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -145,7 +145,7 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - sr_reg = FLASH_F7_SR; + sr_reg = (bank == BANK_1) ? FLASH_F7_SR1 : FLASH_F7_SR2; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = FLASH_Gx_SR; @@ -1025,7 +1025,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } else if (sl->chip_id == STM32_CHIPID_F7 || sl->chip_id == STM32_CHIPID_F76xxx) { // calculate the actual page from the address - uint32_t sector = calculate_F7_sectornum(flashaddr); + uint32_t sector = calculate_F7_sectornum(sl, flashaddr); fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 0d01dfd61..9511c9282 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -363,7 +363,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t /* Run loader */ stlink_run(sl, RUN_FLASH_LOADER); -/* +/* * This piece of code used to try to spin for .1 second by waiting doing 10000 rounds of 10 µs. * But because this usually runs on Unix-like OSes, the 10 µs get rounded up to the "tick" * (actually almost two ticks) of the system. 1 ms. Thus, the ten thousand attempts, when @@ -393,7 +393,7 @@ int32_t stlink_flash_loader_run(stlink_t *sl, flash_loader_t* fl, stm32_addr_t t // check written byte count stlink_read_reg(sl, 2, &rr); - /* + /* * The chunk size for loading is not rounded. The flash loader * subtracts the size of the written block (1-8 bytes) from * the remaining size each time. A negative value may mean that From 8f2b289f20372583ae5f2889069e56df3c71477c Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 27 Nov 2023 23:41:27 +0100 Subject: [PATCH 1422/1435] Info on HW breakpoints for external bus - [doc] Updated tutorial.md (Closes #1219) - Moved memory maps into separate file. --- doc/tutorial.md | 32 +++--- src/st-util/gdb-server.c | 214 +------------------------------------- src/st-util/memory-map.h | 217 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 238 insertions(+), 225 deletions(-) create mode 100644 src/st-util/memory-map.h diff --git a/doc/tutorial.md b/doc/tutorial.md index 53ecabe7d..736c4283b 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -2,18 +2,18 @@ ## Available tools and options -| Option | Tool | Description | Available
      since | -| --------------------- | ---------------------------------- | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | -------------------- | -| --flash=n[k, M] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6
      to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
      Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional
      "k" or "M" to multiply the given value by 1k (1024) or 1M (1024 x 1024) respectively.
      One can read arbitary addresses of memory out to a binary file with: `st-flash read out.bin 0x8000000 4096`.
      In this example `4096 bytes` are read and subsequently written to `out.bin`.
      Binary files (here: `in.bin`) are written into flash memory with: `st-flash write in.bin 0x8000000` | v1.4.0 | -| --format | st-flash | Specify file image format to read or write. Valid formats are `binary` and `ihex`. | v1.3.0 | -| --freq=n[k, M] | st-info
      st-flash
      st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
      This option solely accepts decimal values with the unit `Hz` being left out. Valid frequencies are:
      `5k, 15k, 25k, 50k, 100k, 125k, 240k, 480k, 950k, 1200k (1.2M), 1800k (1.8M), 4000k (4M)`. | v1.6.1 | -| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
      This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | -| --reset | st-flash | Trigger a reset after flashing. The default uses the hardware reset through `NRST` pin.
      A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | -| --connect-under-reset | st-info
      st-flash
      st-util | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful
      when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | -| --hot-plug | st-info
      st-flash
      st-util | Connect to the target without reset. | v1.6.2 | -| --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | -| --version | st-info
      st-flash
      st-util | Print version information. | v1.3.0 | -| --help | st-flash
      st-util | Print list of available commands. | | +| Option | Tool | Description | Available
      since | +| --------------------- | ---------------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ | -------------------- | +| --flash=n[k, M] | st-flash | One can specify `--flash=128k` for example, to override the default value of 64k for the STM32F103C8T6 to assume 128k of flash being present. This option accepts decimal (128k), octal 0200k, or hex 0x80k values.
      Leaving the multiplier out is equally valid, e.g.: `--flash=0x20000`. The size may be followed by an optional "k" or "M" to multiply the given value by 1k (1024) or 1M (1024 x 1024) respectively.
      One can read arbitary addresses of memory out to a binary file with: `st-flash read out.bin 0x8000000 4096`. In this example `4096 bytes` are read and subsequently written to `out.bin`.
      Binary files (here: `in.bin`) are written into flash memory with: `st-flash write in.bin 0x8000000` | v1.4.0 | +| --format | st-flash | Specify file image format to read or write.
      Valid formats are `binary` and `ihex`. | v1.3.0 | +| --freq=n[k, M] | st-info
      st-flash
      st-util | The frequency of the SWD/JTAG interface can be specified, to override the default 1800 kHz configuration.
      This option solely accepts decimal values with the unit `Hz` being left out. Valid frequencies are:
      `5k, 15k, 25k, 50k, 100k, 125k, 240k, 480k, 950k, 1200k (1.2M), 1800k (1.8M), 4000k (4M)`. | v1.6.1 | +| --opt | st-flash | Optimisation can be enabled in order to skip flashing empty (0x00 or 0xff) bytes at the end of binary file.
      This may cause some garbage data left after a flash operation. This option was enabled by default in earlier releases. | v1.6.1 | +| --reset | st-flash | Trigger a reset after flashing. The default uses the hardware reset through `NRST` pin.
      A software reset (via `AIRCR`; since v1.5.1) is used, if the hardware reset failed (`NRST` pin not connected). | v1.0.0 | +| --connect-under-reset | st-info
      st-flash
      st-util | Connect under reset. Option makes it possible to connect to the device before code execution. This is useful when the target contains code that lets the device go to sleep, disables debug pins or other special code. | v1.6.1 | +| --hot-plug | st-info
      st-flash
      st-util | Connect to the target without reset. | v1.6.2 | +| --probe | st-info | Display hardware information about the connected programmer and target MCU. | v1.2.0 | +| --version | st-info
      st-flash
      st-util | Print version information. | v1.3.0 | +| --help | st-flash
      st-util | Print list of available commands. | | ### Reading & Writing Option Bytes @@ -156,6 +156,14 @@ Here flashing of the device is now possible with and without the `--reset` optio The debug command `(gdb) monitor jtag_reset` sends a _hard reset_ signal via the `NRST` pin to reset the device and allows for flashing it (again). +### e) Note on setting hardware breakpoints for external bus (Example: STM32H735-DK) + +GDB is setting breakpoints based on the XML memory map designation of `rom` or `ram`, which is hardcoded in st-util for a given processor. +However the external bus can be *RAM* or *ROM* depending on design. + +The STM32H735-DK has external FLASH at address 0x90000000. As a result, because the entire external memory range is `ram` as it could be either, +software breakpoints (Z0) get sent when a breakpoint is created and they never get tripped as the memory area is read only. + --- ( Content below is currently unrevised and may be outdated as of Mar 2021. ) diff --git a/src/st-util/gdb-server.c b/src/st-util/gdb-server.c index 71f24fb60..28e06231a 100644 --- a/src/st-util/gdb-server.c +++ b/src/st-util/gdb-server.c @@ -29,6 +29,7 @@ #include #include "gdb-server.h" #include "gdb-remote.h" +#include "memory-map.h" #include "semihosting.h" #include @@ -344,219 +345,6 @@ static const char* const target_description = " " ""; -static const char* const memory_map_template_F4 = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // ccm ram - " " // sram - " " // Sectors 0..3 - " 0x4000" // 16kB - " " - " " // Sector 4 - " 0x10000" // 64kB - " " - " " // Sectors 5..11 - " 0x20000" // 128kB - " " - " " // peripheral regs - " " // AHB3 Peripherals - " " // cortex regs - " " // bootrom - " " // option byte area - ""; - -static const char* const memory_map_template_F4_HD = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // ccm ram - " " // sram - " " // fmc bank 1 (nor/psram/sram) - " " // fmc bank 2 & 3 (nand flash) - " " // fmc bank 4 (pc card) - " " // fmc sdram bank 1 & 2 - " " // Sectors 0..3 - " 0x4000" // 16kB - " " - " " // Sector 4 - " 0x10000" // 64kB - " " - " " // Sectors 5..11 - " 0x20000" // 128kB - " " - " " // peripheral regs - " " // cortex regs - " " // bootrom - " " // option byte area - ""; - -static const char* const memory_map_template_F2 = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram - " " // Sectors 0..3 - " 0x4000" // 16kB - " " - " " // Sector 4 - " 0x10000" // 64kB - " " - " " // Sectors 5.. - " 0x20000" // 128kB - " " - " " // peripheral regs - " " // cortex regs - " " // bootrom - " " // option byte area - ""; - -static const char* const memory_map_template_L4 = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // SRAM2 (32kB) - " " // SRAM1 (96kB) - " " - " 0x800" - " " - " " // peripheral regs - " " // AHB3 Peripherals - " " // cortex regs - " " // bootrom - " " // option byte area - " " // option byte area - ""; - -static const char* const memory_map_template_L496 = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // SRAM2 (64kB) - " " // SRAM1 + aliased SRAM2 (256 + 64 = 320kB) - " " - " 0x800" - " " - " " // peripheral regs - " " // AHB3 Peripherals - " " // cortex regs - " " // bootrom - " " // option byte area - " " // option byte area - ""; - -static const char* const memory_map_template = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram 8kB - " " - " 0x%x" - " " - " " // peripheral regs - " " // cortex regs - " " // bootrom - " " // option byte area - ""; - -static const char* const memory_map_template_F7 = - "" - "" - "" - " " // ITCM ram 16kB - " " // ITCM flash - " " // sram - " " // Sectors 0..3 - " 0x8000" // 32kB - " " - " " // Sector 4 - " 0x20000" // 128kB - " " - " " // Sectors 5..7 - " 0x40000" // 128kB - " " - " " // peripheral regs - " " // AHB3 Peripherals - " " // cortex regs - " " // bootrom - " " // option byte area - ""; - -static const char* const memory_map_template_H7 = - "" - "" - "" - " " // ITCMRAM 64kB - " " // DTCMRAM 128kB - " " // RAM D1 512kB - " " // RAM D2 288kB - " " // RAM D3 64kB - " " - " 0x%x" - " " - " " // peripheral regs - " " // cortex regs - " " // bootrom - ""; - -static const char* const memory_map_template_H72x3x = - "" - "" - "" - " " // ITCMRAM 64kB + Optional remap - " " // DTCMRAM 128kB - " " // RAM D1 320kB - " " // RAM D2 23kB - " " // RAM D3 16kB - " " // Backup RAM 4kB - " " - " 0x%x" - " " - " " // peripheral regs - " " // External Memory - " " // External device - " " // cortex regs - " " // bootrom - ""; - -static const char* const memory_map_template_F4_DE = - "" - "" - "" - " " // code = sram, bootrom or flash; flash is bigger - " " // sram - " " // Sectors 0..3 - " 0x4000" // 16kB - " " - " " // Sector 4 - " 0x10000" // 64kB - " " - " " // Sectors 5..7 - " 0x20000" // 128kB - " " - " " // peripheral regs - " " // cortex regs - " " // bootrom - " " // otp - " " // option byte area - ""; - char* make_memory_map(stlink_t *sl) { // this will be freed in serve() const uint32_t sz = 4096; diff --git a/src/st-util/memory-map.h b/src/st-util/memory-map.h new file mode 100644 index 000000000..6f34eedac --- /dev/null +++ b/src/st-util/memory-map.h @@ -0,0 +1,217 @@ +#ifndef MEMORY_MAP_H +#define MEMORY_MAP_H + +static const char* const memory_map_template_F4 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // ccm ram + " " // sram + " " // Sectors 0...3 + " 0x4000" // 16 kB + " " + " " // Sector 4 + " 0x10000" // 64 kB + " " + " " // Sectors 5...11 + " 0x20000" // 128 kB + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + +static const char* const memory_map_template_F4_HD = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // ccm ram + " " // sram + " " // fmc bank 1 (nor/psram/sram) + " " // fmc bank 2 & 3 (nand flash) + " " // fmc bank 4 (pc card) + " " // fmc sdram bank 1 & 2 + " " // Sectors 0...3 + " 0x4000" // 16 kB + " " + " " // Sector 4 + " 0x10000" // 64 kB + " " + " " // Sectors 5...11 + " 0x20000" // 128 kB + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + +static const char* const memory_map_template_F2 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM + " " // Sectors 0...3 + " 0x4000" // 16 kB + " " + " " // Sector 4 + " 0x10000" // 64 kB + " " + " " // Sectors 5... + " 0x20000" // 128 kB + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + +static const char* const memory_map_template_L4 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM2 (32 kB) + " " // SRAM1 (96 kB) + " " + " 0x800" + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + " " // option byte area + ""; + +static const char* const memory_map_template_L496 = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM2 (64 kB) + " " // SRAM1 + aliased SRAM2 (256 + 64 = 320 kB) + " " + " 0x800" + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + " " // option byte area + ""; + +static const char* const memory_map_template = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM (8 kB) + " " + " 0x%x" + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + +static const char* const memory_map_template_F7 = + "" + "" + "" + " " // ITCM ram 16 kB + " " // ITCM flash + " " // SRAM + " " // Sectors 0...3 + " 0x8000" // 32 kB + " " + " " // Sector 4 + " 0x20000" // 128 kB + " " + " " // Sectors 5...7 + " 0x40000" // 128 kB + " " + " " // peripheral regs + " " // AHB3 Peripherals + " " // cortex regs + " " // bootrom + " " // option byte area + ""; + +static const char* const memory_map_template_H7 = + "" + "" + "" + " " // ITCMRAM 64 kB + " " // DTCMRAM 128 kB + " " // RAM D1 512 kB + " " // RAM D2 288 kB + " " // RAM D3 64 kB + " " + " 0x%x" + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + ""; + +static const char* const memory_map_template_H72x3x = + "" + "" + "" + " " // ITCMRAM 64 kB + Optional remap + " " // DTCMRAM 128 kB + " " // RAM D1 320 kB + " " // RAM D2 23 kB + " " // RAM D3 16 kB + " " // Backup RAM 4 kB + " " + " 0x%x" + " " + " " // peripheral regs + " " // External Memory + " " // External device + " " // cortex regs + " " // bootrom + ""; + +static const char* const memory_map_template_F4_DE = + "" + "" + "" + " " // code = sram, bootrom or flash; flash is bigger + " " // SRAM + " " // Sectors 0..3 + " 0x4000" // 16 kB + " " + " " // Sector 4 + " 0x10000" // 64 kB + " " + " " // Sectors 5..7 + " 0x20000" // 128 kB + " " + " " // peripheral regs + " " // cortex regs + " " // bootrom + " " // otp + " " // option byte area + ""; + +#endif // MEMORY_MAP_H \ No newline at end of file From 81575cb2d9fd1db32dd12581baf642447e5ab623 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 23 Dec 2023 17:45:17 +0100 Subject: [PATCH 1423/1435] [doc] Updated udev directory (#1358) --- doc/compiling.md | 2 +- doc/tutorial.md | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index 8936f6a58..e2c686c0a 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -165,7 +165,7 @@ Within the sourcefolder of the project, these rules are located in the subdirect Afterwards it may be necessary to reload the udev rules: ```sh -$ sudo cp -a config/udev/rules.d/* /etc/udev/rules.d/ +$ sudo cp -a config/udev/rules.d/* /lib/udev/rules.d/ $ sudo udevadm control --reload-rules $ sudo udevadm trigger ``` diff --git a/doc/tutorial.md b/doc/tutorial.md index 736c4283b..36c80c674 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -62,7 +62,7 @@ On my system I see the following: crw-rw-rw- 1 root root 189, 528 Jan 24 17:52 /dev/bus/usb/005/017 ``` -which is world writable (this is from the `MODE:="0666"` below). I have several files in my `/etc/udev/rules.d` directory. In this particular case, the `49-stlinkv2-1.rules` file contains the following: +which is world writable (this is from the `MODE:="0666"` below). I have several files in my `/lib/udev/rules.d` directory. In this particular case, the `49-stlinkv2-1.rules` file contains the following: ``` # STM32 nucleo boards, with onboard STLINK/V2-1 @@ -81,7 +81,7 @@ SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", \ and the `idVendor` of `0483` and `idProduct` of `374b` matches the vendor id from the `lsusb` output. -Make sure that you have all 3 files from [/config/udev/rules.d](https://github.com/stlink-org/stlink/tree/master/config/udev/rules.d) in your `/etc/udev/rules.d` directory. After copying new files or editing existing files in `/etc/udev/ruled.d` you should run the following: +Make sure that you have all 3 files from [/config/udev/rules.d](https://github.com/stlink-org/stlink/tree/master/config/udev/rules.d) in your `/lib/udev/rules.d` directory. After copying new files or editing existing files in `/lib/udev/rules.d` you should run the following: ``` sudo udevadm control --reload-rules From 135a5472d9fd52d252774dce2b5d05cdc25dd458 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 24 Dec 2023 00:01:35 +0100 Subject: [PATCH 1424/1435] Reverted commit ba335a47 "STM32F76xxx: Added flashing in dual bank mode" --- inc/stlink.h | 2 - inc/stm32flash.h | 1 - src/stlink-lib/calculate.c | 2 +- src/stlink-lib/common.c | 91 ----------------------------------- src/stlink-lib/common_flash.c | 4 +- 5 files changed, 3 insertions(+), 97 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 920822a85..788392d72 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -233,8 +233,6 @@ struct _stlink { uint32_t max_trace_freq; // set by stlink_open_usb() - bool dual_bank; // set for F7xxx devices by reading optcr - uint32_t otp_base; uint32_t otp_size; }; diff --git a/inc/stm32flash.h b/inc/stm32flash.h index 4fed8b597..a5081d694 100644 --- a/inc/stm32flash.h +++ b/inc/stm32flash.h @@ -142,7 +142,6 @@ #define FLASH_F7_OPTCR_START 1 #define FLASH_F7_OPTCR1_BOOT_ADD0 0 #define FLASH_F7_OPTCR1_BOOT_ADD1 16 -#define FLASH_F7_OPTCR_DBANK (29) /* FLASH_OPTCR Dual Bank Mode */ // F7 Flash control register #define FLASH_F7_CR_STRT 16 diff --git a/src/stlink-lib/calculate.c b/src/stlink-lib/calculate.c index a8a66a844..95a94143b 100644 --- a/src/stlink-lib/calculate.c +++ b/src/stlink-lib/calculate.c @@ -36,7 +36,7 @@ uint32_t calculate_F4_sectornum(uint32_t flashaddr) { } } -uint32_t calculate_F7_sectornum_old(uint32_t flashaddr) { +uint32_t calculate_F7_sectornum(uint32_t flashaddr) { flashaddr &= ~STM32_FLASH_BASE; // Page now holding the actual flash address if (flashaddr < 0x20000) { diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 4ff90ef3d..57aa53a25 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -318,19 +318,6 @@ int32_t stlink_load_device_params(stlink_t *sl) { } } - // F76xxx device with dual bank - if (sl->chip_id == STM32_CHIPID_F76xxx) { - // Check the nDBANK bit in OPTCR - uint32_t optcr; - stlink_read_option_control_register32(sl, & optcr); - - if (!(optcr & (1 << STM32F7_FLASH_OPTCR_DBANK))) - { - sl->dual_bank = true; - } - DLOG("*** stm32f76xx dual-bank %d ***\n", sl->dual_bank); - } - // H7 devices with small flash has one bank if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && sl->flash_type == STM32_FLASH_TYPE_H7) { @@ -843,87 +830,9 @@ int32_t write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *bu return (ret); } -/* STM32F7 Series Flash memory dual bank mode - * See application note AN4826 pp.18 - */ - -struct sectors_f7 { - int sector; - uint32_t base; - uint32_t size; -}; - -static const struct sectors_f7 f7_single[] = { - { 0, 0x08000000, 0x8000 }, - { 1, 0x08008000, 0x8000 }, - { 2, 0x08010000, 0x8000 }, - { 3, 0x08018000, 0x8000 }, - { 4, 0x08020000, 0x20000 }, - { 5, 0x08040000, 0x40000 }, - { 6, 0x08080000, 0x40000 }, - { 7, 0x080C0000, 0x40000 }, - { 0, 0, 0 }, -}; - -static const struct sectors_f7 f7_dual[] = { - { 0, 0x08000000, 0x4000 }, - { 1, 0x08004000, 0x4000 }, - { 2, 0x08008000, 0x4000 }, - { 3, 0x0800C000, 0x4000 }, - { 4, 0x08010000, 0x10000 }, - { 5, 0x08020000, 0x20000 }, - { 6, 0x08040000, 0x20000 }, - { 7, 0x08060000, 0x20000 }, - { 8, 0x08080000, 0x20000 }, - { 9, 0x080A0000, 0x20000 }, - { 10, 0x080C0000, 0x20000 }, - { 11, 0x080E0000, 0x20000 }, - { 12, 0x08100000, 0x4000 }, - { 13, 0x08104000, 0x4000 }, - { 14, 0x08108000, 0x4000 }, - { 15, 0x0810C000, 0x4000 }, - { 16, 0x08110000, 0x10000 }, - { 17, 0x08120000, 0x20000 }, - { 18, 0x08140000, 0x20000 }, - { 19, 0x08160000, 0x20000 }, - { 20, 0x08180000, 0x20000 }, - { 21, 0x081A0000, 0x20000 }, - { 22, 0x081C0000, 0x20000 }, - { 23, 0x081E0000, 0x20000 }, - { 0, 0, 0 }, -}; - -static const struct sectors_f7 *get_f7_info(stlink_t *sl) { - return sl->dual_bank ? f7_dual : f7_single; -} - -static const struct sectors_f7 *find_sector(stlink_t *sl, uint32_t flashaddr) { - for (const struct sectors_f7 *s = get_f7_info(sl); s->base; s++) { - const uint32_t end = s->base + s->size; - if ((s->base <= flashaddr) && (flashaddr < end)) { - return s; - } - } - fprintf(stderr, "Bad address %#x\n", flashaddr); - exit(0); -} - -uint32_t calculate_F7_sectornum(stlink_t *sl, uint32_t flashaddr) { - if (sl->chip_id == STM32_CHIPID_F76xxx) { - const struct sectors_f7 *s = find_sector(sl, flashaddr); - return s->sector; - } - return calculate_F7_sectornum_old(flashaddr); -} - // 291 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { - if (sl->chip_id == STM32_CHIPID_F76xxx) { - const struct sectors_f7 *s = find_sector(sl, flashaddr); - return s->size; - } - if ((sl->chip_id == STM32_CHIPID_F2) || (sl->chip_id == STM32_CHIPID_F4) || (sl->chip_id == STM32_CHIPID_F4_DE) || diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index fc377a471..ef6b8370c 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -145,7 +145,7 @@ static inline int32_t write_flash_sr(stlink_t *sl, uint32_t bank, uint32_t val) } else if (sl->flash_type == STM32_FLASH_TYPE_F2_F4) { sr_reg = FLASH_F4_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_F7) { - sr_reg = (bank == BANK_1) ? FLASH_F7_SR1 : FLASH_F7_SR2; + sr_reg = FLASH_F7_SR; } else if (sl->flash_type == STM32_FLASH_TYPE_G0 || sl->flash_type == STM32_FLASH_TYPE_G4) { sr_reg = FLASH_Gx_SR; @@ -1025,7 +1025,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { } else if (sl->chip_id == STM32_CHIPID_F7 || sl->chip_id == STM32_CHIPID_F76xxx) { // calculate the actual page from the address - uint32_t sector = calculate_F7_sectornum(sl, flashaddr); + uint32_t sector = calculate_F7_sectornum(flashaddr); fprintf(stderr, "EraseFlash - Sector:0x%x Size:0x%x ", sector, stlink_calculate_pagesize(sl, flashaddr)); From a60c24cbc040fe63b12172e93d0d99778b30eaca Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 24 Dec 2023 00:34:29 +0100 Subject: [PATCH 1425/1435] General Project Update - [doc] Updated system requirements - Updated CHANGELOG.md - Updated list of contributors --- CHANGELOG.md | 19 +++++++--- contributors.txt | 16 +++++---- doc/version_support.md | 67 ++++++++++++++++------------------- src/stlink-gui/CMakeLists.txt | 2 +- 4 files changed, 55 insertions(+), 49 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 9b6cccdf9..c477eb54a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,7 +2,7 @@ # v1.8.0 -Release date: 2023-xx-xx +Release date: 2024-xx-xx This release drops support for macOS and some older operating systems. Check project README for details. Removed Travis CI integration as it is no longer functional. @@ -16,7 +16,7 @@ Features: - Support for writing option bytes on STM32F0/F1/F3 ([#346](https://github.com/stlink-org/stlink/pull/346), [#458](https://github.com/stlink-org/stlink/pull/458), [#808](https://github.com/stlink-org/stlink/pull/808), [#1084](https://github.com/stlink-org/stlink/pull/1084), [#1112](https://github.com/stlink-org/stlink/pull/1112)) - Initial support for STM32 L5 & U5 devices and minor changes ([#1005](https://github.com/stlink-org/stlink/pull/1005), [#1096](https://github.com/stlink-org/stlink/pull/1096), [#1247](https://github.com/stlink-org/stlink/pull/1247), [#1300](https://github.com/stlink-org/stlink/pull/1300), [#1301](https://github.com/stlink-org/stlink/pull/1301)) -- Added chip-IDs for STM32G0B0/G0B1/G0C1/G050/G051/G061 ([#1140](https://github.com/stlink-org/stlink/pull/1140)) +- Added chip-IDs for STM32G0B0/G0B1/G0C1/G050/G051/G061 ([#1140](https://github.com/stlink-org/stlink/pull/1140), [#1359](https://github.com/stlink-org/stlink/pull/1359)) - Added option byte info for STM32F411XX ([#1141](https://github.com/stlink-org/stlink/pull/1141)) - Expanded and revised list of chips ([#1145](https://github.com/stlink-org/stlink/pull/1145), [#1164](https://github.com/stlink-org/stlink/pull/1164)) - STM32H72X/3X: Added full access to all device memory ([#1158](https://github.com/stlink-org/stlink/pull/1158), [#1159](https://github.com/stlink-org/stlink/pull/1159)) @@ -29,7 +29,9 @@ Features: - Added parametres option_base, option_size for F401xD_xE ([#1235](https://github.com/stlink-org/stlink/pull/1235)) - Added support for option bytes to F1xx_XLD (GD32F30x) ([#1250](https://github.com/stlink-org/stlink/pull/1250)) - Added option byte address for L4Rx devices ([#1254](https://github.com/stlink-org/stlink/pull/1254)) -- Added udev-rule rule for the STLink v3 MINIE programmer ([#1274](https://github.com/stlink-org/stlink/pull/1274), [#1281](https://github.com/stlink-org/stlink/pull/1281)) +- Added udev-rule rule for the STLink v3 MINIE programmer ([#1274](https://github.com/stlink-org/stlink/pull/1274), [#1281](https://github.com/stlink-org/stlink/pull/1281), [#1358](https://github.com/stlink-org/stlink/pull/1358)) +- Added support for STM32C0x1 devices ([#1329](https://github.com/stlink-org/stlink/pull/1329), [#1354](https://github.com/stlink-org/stlink/pull/1354)) +- First Implementation of the OTP Read/Write function ([#1352](https://github.com/stlink-org/stlink/pull/1352), [#1353](https://github.com/stlink-org/stlink/pull/1353)) Updates & changes: @@ -42,11 +44,13 @@ Updates & changes: - [doc] Human-readable flash_type in chip-id files ([#1155](https://github.com/stlink-org/stlink/pull/1155), commit [#1745bf5](https://github.com/stlink-org/stlink/commit/1745bf5193c4d3186d4f6fde59cc86e9bad6e61b)) - Dropped execute bits from source code files ([#1167](https://github.com/stlink-org/stlink/pull/1167)) - Use proper Markdown headers for supported MCUs ([#1168](https://github.com/stlink-org/stlink/pull/1168)) +- Ability to flash F7 devices when in dual-bank mode ([#1174](https://github.com/stlink-org/stlink/pull/1174)) - Removed redundant array ([#1178](https://github.com/stlink-org/stlink/pull/1178)) - Updated chip config files from the library structs ([#1181](https://github.com/stlink-org/stlink/pull/1181)) - [doc] Corrected file path in tutorial ([#1186](https://github.com/stlink-org/stlink/pull/1186)) - Improved chipid checks and printouts ([#1188](https://github.com/stlink-org/stlink/pull/1188)) - [refactoring] Sourcefile 'common.c' ([#1218](https://github.com/stlink-org/stlink/pull/1218), [#1220](https://github.com/stlink-org/stlink/pull/1220)) +- [STM32H735]: Set hardware breakpoints for external bus ([#1219](https://github.com/stlink-org/stlink/pull/1219)) - Set C standard through cmake variables ([#1221](https://github.com/stlink-org/stlink/pull/1221)) - [doc] Added make install to the macOS compiling instructions ([#1259](https://github.com/stlink-org/stlink/pull/1259)) - [doc] Linux Install from code Documentation improvement ([#1263](https://github.com/stlink-org/stlink/pull/1263), commit [#43498de](https://github.com/stlink-org/stlink/commit/43498dedf651260ef34197e512d35e3ad7142401)) @@ -56,12 +60,13 @@ Updates & changes: - [doc] Updated package source link for Arch Linux ([#1318](https://github.com/stlink-org/stlink/pull/1318)) - CMake: Avoid hard-wired /usr/local/share ([#1325](https://github.com/stlink-org/stlink/pull/1325)) + Fixes: - Fixed some flashing issues on STM32L0 ([#681](https://github.com/stlink-org/stlink/pull/681), [#1203](https://github.com/stlink-org/stlink/pull/1203), [#1225](https://github.com/stlink-org/stlink/pull/1225), [#1253](https://github.com/stlink-org/stlink/pull/1253), [#1289](https://github.com/stlink-org/stlink/pull/1289), [#1330](https://github.com/stlink-org/stlink/pull/1330)) - cmake: Install shared libraries in proper directories ([#1098](https://github.com/stlink-org/stlink/pull/1098), [#1138](https://github.com/stlink-org/stlink/pull/1138), [#1154](https://github.com/stlink-org/stlink/pull/1154)) - cmake: Install shared libraries in proper directories ([#1142](https://github.com/stlink-org/stlink/pull/1142)) -- Fixed clearance of the H7 dual bank flag ([#1146](https://github.com/stlink-org/stlink/pull/1146), [#1147](https://github.com/stlink-org/stlink/pull/1147)) +- Fixed clearance of the H7 dual bank flag ([#1146](https://github.com/stlink-org/stlink/pull/1146), [#1147](https://github.com/stlink-org/stlink/pull/1147), [#1342](https://github.com/stlink-org/stlink/pull/1342)) - Fix for 'libusb_devices were leaked' when no ST-LINK programmer was found ([#1150](https://github.com/stlink-org/stlink/pull/1150)) - Set of fixes and improvements ([#1153](https://github.com/stlink-org/stlink/pull/1153), [#1154](https://github.com/stlink-org/stlink/pull/1154)) - Removed limit check for WRITEMEM_32BIT ([#1157](https://github.com/stlink-org/stlink/pull/1157)) @@ -75,7 +80,7 @@ Fixes: - st-flash and other utilities search for chip files in the wrong directory ([#1180](https://github.com/stlink-org/stlink/pull/1180), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) - Fixed broken build on 32 bit systems ([#985](https://github.com/stlink-org/stlink/pull/985), [#1175](https://github.com/stlink-org/stlink/pull/1175), commit [#c8fc656](https://github.com/stlink-org/stlink/commit/c8fc6561fead79ad49c09d82bab864745086792c)) - Define 'SSIZE_MAX' if not defined ([#1183](https://github.com/stlink-org/stlink/pull/1183)) -- STM32G031G8: BOOT_LOCK is not possible to change on option bytes address 0x1FFF7870 ([#1194](https://github.com/stlink-org/stlink/pull/1194)) +- [STM32G031G8]: BOOT_LOCK is not possible to change on option bytes address 0x1FFF7870 ([#1194](https://github.com/stlink-org/stlink/pull/1194)) - Fixed compliation for OpenBSD 7.0 ([#1202](https://github.com/stlink-org/stlink/pull/1202)) - Included 'SSIZE_MAX' from 'limits.h' in 'src/common.c' ([#1207](https://github.com/stlink-org/stlink/pull/1207)) - Fix for libusb_kernel_driver_active & error handling for st.st_size () ([#1210](https://github.com/stlink-org/stlink/pull/1210), [#1211](https://github.com/stlink-org/stlink/pull/1211), [#1214](https://github.com/stlink-org/stlink/pull/1214)) @@ -93,7 +98,11 @@ Fixes: - Fixed unbounded write and check return values of sscanf ([#1306](https://github.com/stlink-org/stlink/pull/1306)) - Added null check for return value of stlink_chipid_get_params() ([#1307](https://github.com/stlink-org/stlink/pull/1307)) - Fixed warning in a few *.cmake files ([#1309](https://github.com/stlink-org/stlink/pull/1309)) +- Fixed support for STM32U5 chips ([#1320](https://github.com/stlink-org/stlink/pull/1320), [#1355](https://github.com/stlink-org/stlink/pull/1355)) +- [STM32G0B1]: Erase fails starting page 64 ([#1321](https://github.com/stlink-org/stlink/pull/1321)) - Notification "unknown option -- u" in tool st-util ([#1326](https://github.com/stlink-org/stlink/pull/1326), [#1327](https://github.com/stlink-org/stlink/pull/1327)) +- Do not crash when the STLink chip returns a voltage factor of zero ([#1343](https://github.com/stlink-org/stlink/pull/1343)) +- stlink-gui: failed to allocate 139988352155568 bytes ([#1356](https://github.com/stlink-org/stlink/pull/1356)) # v1.7.0 diff --git a/contributors.txt b/contributors.txt index 2425ae7f0..dacb4e4af 100644 --- a/contributors.txt +++ b/contributors.txt @@ -4,7 +4,7 @@ Alexey Cherevatenko Alexey Panarin Anatoli Klassen [dev26th] Andrea Mucignat -Andrew Andrianov [necromant] +Andrew Andrianov [nekromant] Andrey Yurovsky Andy Isaacson Andreas Sandberg [andysan] @@ -52,10 +52,10 @@ Greg Meiste [meisteg] Grzegorz Szymaszek [gszy] Guillaume Revaillot [grevaillot] Gwenhael Goavec-Merou [trabucayre] -Hakkavélin +[Hakkavélin] Halt Hammerzeit +Hsu Pu [hsupu] [hydroconstructor] -htk Ian Griffiths Jack Peel Jakub Tyszkowski @@ -68,6 +68,7 @@ Jens Hoffmann Jerome Lambourg Jim Paris Jiří Netolický +Jerry Jacobs [xor-gate] Jerry Nosky [jnosky] Jochen Wilhelmy [Jochen0x90h] John Hall [simplerobot] @@ -90,7 +91,6 @@ Michael Pratt [prattmic] Michael Sparmann Mike Szczys Magnus Lundin [mlu] -mux Ned Konz Nic McDonald Nicolas Schodet @@ -98,7 +98,7 @@ Oleksiy Slyshyk [slyshykO] Olivier Croquette Olivier Gay Onno Kortmann -orangeudav +[orangeudav] Pavel Kirienko Pekka Nikander Pete Nelson @@ -107,6 +107,7 @@ Peter Zotov Petteri Aimonen Piotr Haber [RafaelLeeImg] +[rcubee] Rene Hopf [rene-dev] Robin Kreis Roger Wolff [rewolff] @@ -117,11 +118,11 @@ Sean Simmons Sergey Alirzaev Simon Derr [sderr] Simon Wright -[simplerobot] Stany Marcel Stefan Misik Sven Wegener -Tarek Bochkati [tarek-bochkati] (STMicroelectronics) +Tarek Bochkati [tarek-bochkati] +[texane] Timothy Lee [timothytylee] Tuomo Kaikkonen Theodore A. Roth @@ -136,6 +137,7 @@ Vasiliy Glazov [Vascom] Vegard Storheil Eriksen Viacheslav Dobromyslov Victor Mayoral Vilches +[whitequark] William Ransohoff [WRansohoff] Wojciech A. Koszek Woodrow Douglass diff --git a/doc/version_support.md b/doc/version_support.md index 022fb5e4d..c87ad1772 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -25,42 +25,34 @@ Maintained versions of: Other Linux-/Unix-based Operating Systems: -| Operating System | libusb | cmake | libgtk-dev | Notes | -| ------------------------ | ------------------------------ | ---------- | ----------- | ------------------------ | -| Debian Sid | 1.0.24 | 3.22.1 | 3.24.31 | | -| Debian 11 (Bullseye) | 1.0.24 | 3.**18.4** | 3.24.24 | | -| Debian 10 (Buster) | 1.0.**22** | 3.**13.4** | 3.24.**5** | | -| | | | | | -| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.**16.3** | 3.24.**18** | | -| | | | | | -| Alpine 3.15 | 1.0.24 | 3.21.3 | 3.24.30 | End of Support: Nov 2023 | -| Alpine 3.14 | 1.0.24 | 3.20.3 | 3.24.28 | End of Support: May 2023 | -| | | | | | -| FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | -| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | -| | | | | | -| NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | -| NetBSD 8.x | 1.0.24 | 3.**19.7** | 3.24.27 | | -| | | | | | -| CentOS 9 Stream [x64] | 1.0.24 (`libusbx`) | 3.20.3 | 3.24.30 | | -| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | | -| | | | | | -| ALT Linux Sisyphus | 1.0.24 | 3.22.1 | 3.24.31 | | -| ALT Linux P10 | 1.0.24 | 3.20.5 | 3.24.31 | | -| ALT Linux P9 | 1.0.**22** | 3.**16.3** | 3.24.29 | | -| | | | | | -| OpenMandriva Rolling | 1.0.24 | 3.22.1 | 3.24.31 | | -| OpenMandriva Cooker | 1.0.24 | 3.22.1 | 3.24.31 | | -| OpenMandriva Lx 4.2 | 1.0.24 | 3.**19.3** | 3.24.24 | | -| | | | | | -| Arch Linux | 1.0.24 | 3.22.1 | - | | -| KaOS [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | -| Mageia Cauldron | 1.0.24 | 3.22.1 | 3.24.31 | | -| PCLinuxOS [x64] | (?) | 3.22.1 | 3.24.31 | | -| Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | -| Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | -| Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | -| Adélie 1.0 | 1.0.23 | 3.**16.4** | 3.24.23 | | +| Operating System | libusb | cmake | libgtk-dev | End of
      OS-Support | +| ------------------------ | ------------------------------ | ---------- | ----------- | ---------------------- | +| Debian Sid | 1.0.24 | 3.22.1 | 3.24.31 | | +| Debian 11 (Bullseye) | 1.0.24 | 3.**18.4** | 3.24.24 | | +| Debian 10 (Buster) | 1.0.**22** | 3.**13.4** | 3.24.**5** | Jun 2024 | +| | | | | | +| Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.**16.3** | 3.24.**18** | May 2025 | +| | | | | | +| FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | +| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | Dec 2023 | +| | | | | | +| NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | +| NetBSD 8.x | 1.0.24 | 3.**19.7** | 3.24.27 | | +| | | | | | +| CentOS 9 Stream [x64] | 1.0.24 (`libusbx`) | 3.20.3 | 3.24.30 | | +| CentOS 8 Stream [x64] | 1.0.23 (`libusbx`) | 3.20.2 | 3.**22.30** | May 2024 | +| | | | | | +| ALT Linux Sisyphus | 1.0.24 | 3.22.1 | 3.24.31 | | +| ALT Linux P10 | 1.0.24 | 3.20.5 | 3.24.31 | | +| ALT Linux P9 | 1.0.**22** | 3.**16.3** | 3.24.29 | | +| | | | | | +| KaOS [x64] | 1.0.24 | 3.22.1 | 3.24.31 | | +| Mageia Cauldron | 1.0.24 | 3.22.1 | 3.24.31 | | +| PCLinuxOS [x64] | (?) | 3.22.1 | 3.24.31 | | +| Solus [x64] | 1.0.24 | 3.22.1 | 3.24.30 | | +| Void Linux | 1.0.24 | 3.22.1 | 3.24.31 | | +| Slackware Current | 1.0.24 | 3.21.4 | 3.24.31 | | +| Adélie 1.0 | 1.0.23 | 3.**16.4** | 3.24.23 | | ## Unsupported Operating Systems (as of Release v1.8.0) @@ -68,9 +60,12 @@ Systems with highlighted versions remain compatible with this toolset. | Operating System | libusb | cmake | End of
      OS-Support | | ---------------------------------------- | ------------------------------ | ---------- | ---------------------- | +| Alpine 3.15 | 1.0.**24** | 3.**21.3** | Nov 2023 | | Fedora 35 [x64] | 1.0.**24** | 3.**21.3** | Dec 2022 | +| Alpine 3.14 | 1.0.**24** | 3.**20.3** | May 2023 | | CentOS / Rocky Linux / AlmaLinux 8 [x64] | 1.0.**23** (`libusbx`) | 3.**20.3** | Dec 2021 | | Fedora 34 [x64] | 1.0.**24** (`libusbx`) | 3.**19.7** | Jun 2022 | +| OpenMandriva Lx 4.2 | 1.0.**24** | 3.**19.3** | Mar 2023 | | Mageia 8 | 1.0.**24** | 3.**19.2** | Aug 2022 | | Alpine 3.13 | 1.0.**24** | 3.**18.4** | Nov 2022 | | Ubuntu 21.04 (Hirsute) | 1.0.**24** | 3.**18.4** | Jan 2022 | diff --git a/src/stlink-gui/CMakeLists.txt b/src/stlink-gui/CMakeLists.txt index 042e8d37d..062814e42 100644 --- a/src/stlink-gui/CMakeLists.txt +++ b/src/stlink-gui/CMakeLists.txt @@ -2,7 +2,7 @@ # Build GUI ### -if (NOT WIN32 AND NOT CMAKE_CROSSCOMPILING) +if (NOT WIN32) find_package(PkgConfig) pkg_check_modules(GTK3 gtk+-3.0) From 5613f281c5b8b4abe0e0f94149e5d6a4b7afa1c1 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 24 Dec 2023 00:46:56 +0100 Subject: [PATCH 1426/1435] Fixed compilation error. --- src/stlink-lib/common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index 57aa53a25..c9bf67157 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -858,7 +858,7 @@ uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { } } else if (sl->chip_id == STM32_CHIPID_F7 || sl->chip_id == STM32_CHIPID_F76xxx) { - uint32_t sector = calculate_F7_sectornum(sl, flashaddr); + uint32_t sector = calculate_F7_sectornum(flashaddr); if (sector < 4) { sl->flash_pgsz = 0x8000; From c1efbec7a77eec1dc9611d448c4870cb6121ea2e Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 24 Dec 2023 11:47:51 +0100 Subject: [PATCH 1427/1435] Fixed incorrect chip-ID for STM32C01x MCU --- config/chips/C011xx.chip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/chips/C011xx.chip b/config/chips/C011xx.chip index b961a18f8..eac66ca68 100644 --- a/config/chips/C011xx.chip +++ b/config/chips/C011xx.chip @@ -2,7 +2,7 @@ # dev_type STM32C011xx ref_manual_id 0490 -chip_id 0x453 // STM32_CHIPID_C011xx +chip_id 0x443 // STM32_CHIPID_C011xx flash_type C0 flash_size_reg 0x1fff75a0 flash_pagesize 0x800 // 2 KB From e7f41b2965d95eff75114c6f89f13c24cb7357a2 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 24 Dec 2023 12:08:08 +0100 Subject: [PATCH 1428/1435] Support for STLINK/v2 & /v3 max trace buffers --- inc/stlink.h | 9 ++++++++- src/st-trace/trace.c | 2 +- src/stlink-lib/usb.c | 9 ++++++++- 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/inc/stlink.h b/inc/stlink.h index 788392d72..0c3675083 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -66,7 +66,8 @@ enum target_state { #define STLINK_V3_MAX_FREQ_NB 10 -#define STLINK_TRACE_BUF_LEN 2048 +#define STLINK_V2_TRACE_BUF_LEN 2048 +#define STLINK_V3_TRACE_BUF_LEN 8192 #define STLINK_V2_MAX_TRACE_FREQUENCY 2000000 #define STLINK_V3_MAX_TRACE_FREQUENCY 24000000 #define STLINK_DEFAULT_TRACE_FREQUENCY 2000000 @@ -273,7 +274,13 @@ int32_t stlink_fread(stlink_t* sl, const char* path, bool is_ihex, stm32_addr_t int32_t stlink_load_device_params(stlink_t *sl); int32_t stlink_target_connect(stlink_t *sl, enum connect_type connect); +#include +#include +#include +#include +#include #include +#include #ifdef __cplusplus } diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 04557794a..4ef03c07b 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -425,7 +425,7 @@ static trace_state update_trace(st_trace_t *trace, uint8_t c) { } static bool read_trace(stlink_t *stlink, st_trace_t *trace) { - uint8_t buffer[STLINK_TRACE_BUF_LEN]; + uint8_t buffer[max_trace_buf_len]; int32_t length = stlink_trace_read(stlink, buffer, sizeof(buffer)); if (length < 0) { diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index d3a57c33f..b0d0494cf 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -977,11 +977,18 @@ int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t rep_len = 2; + uint32_t max_trace_buf_len; + + if(sl->version.stlink_v == 2) { + max_trace_buf_len = STLINK_V2_TRACE_BUF_LEN; + } else (sl->version.stlink_v == 3) { + max_trace_buf_len = STLINK_V3_TRACE_BUF_LEN; + } int32_t i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; cmd[i++] = STLINK_DEBUG_APIV2_START_TRACE_RX; - write_uint16(&cmd[i + 0], 2 * STLINK_TRACE_BUF_LEN); + write_uint16(&cmd[i + 0], 2 * max_trace_buf_len); write_uint32(&cmd[i + 2], frequency); size = send_recv(slu, 1, cmd, slu->cmd_len, data, rep_len, CMD_CHECK_STATUS, "START_TRACE_RX"); From 45c31e91696db3f44f2fb4aee51ba2c869fa81f7 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 24 Dec 2023 12:26:01 +0100 Subject: [PATCH 1429/1435] Added interface for spdlog (optional) --- src/stlink-lib/logging.h | 17 +++++++++++++++++ src/stlink-lib/spdlog_wrapper.h | 14 ++++++++++++++ 2 files changed, 31 insertions(+) create mode 100644 src/stlink-lib/spdlog_wrapper.h diff --git a/src/stlink-lib/logging.h b/src/stlink-lib/logging.h index cb49a7af3..560e20eca 100644 --- a/src/stlink-lib/logging.h +++ b/src/stlink-lib/logging.h @@ -8,10 +8,16 @@ #ifndef LOGGING_H #define LOGGING_H +#include +#include "spdlog_wrapper.h" + #ifdef __cplusplus extern "C" { #endif // __cplusplus +/* Optional: Enable interface for SPDLOG to replace UglyLogging */ +// #define SPDLOG_LOGGING + enum ugly_loglevel { UDEBUG = 90, UINFO = 50, @@ -44,6 +50,17 @@ int32_t ugly_libusb_log_level(enum ugly_loglevel v); #define ELOG_HELPER(format, ...) ugly_log(UERROR, UGLY_LOG_FILE, format, __VA_ARGS__) #define ELOG(...) ugly_log(UERROR, UGLY_LOG_FILE, __VA_ARGS__) +#if defined(SPDLOG_LOGGING) +#undef DLOG_HELPER +#undef ILOG_HELPER +#undef WLOG_HELPER +#undef ELOG_HELPER +#define DLOG(...) spdlogLog(UDEBUG, __VA_ARGS__) +#define ILOG(...) spdlogLog(UINFO, __VA_ARGS__) +#define WLOG(...) spdlogLog(UWARN, __VA_ARGS__) +#define ELOG(...) spdlogLog(UERROR, __VA_ARGS__) +#endif // SPDLOG_LOGGING + #ifdef __cplusplus } #endif // __cplusplus diff --git a/src/stlink-lib/spdlog_wrapper.h b/src/stlink-lib/spdlog_wrapper.h new file mode 100644 index 000000000..26f34c8b5 --- /dev/null +++ b/src/stlink-lib/spdlog_wrapper.h @@ -0,0 +1,14 @@ +#ifndef _SPDLOG_WRAPPER_ +#define _SPDLOG_WRAPPER_ + +#ifdef __cplusplus +#define EXTERNC extern "C" +#else +#define EXTERNC +#endif + +EXTERNC int spdlogLog(int level, const char *str, ...); + +#undef EXTERNC + +#endif \ No newline at end of file From 816730f4f7517611e5ff3a03067ae0a673fb72bd Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 24 Dec 2023 19:15:03 +0100 Subject: [PATCH 1430/1435] [refactoring] Clean-up & bugfix for st-trace --- inc/stlink.h | 3 - src/st-trace/trace.c | 159 ++++++++++++++++------------------------ src/st-trace/trace.h | 24 ++++++ src/stlink-lib/common.c | 17 ----- src/stlink-lib/usb.c | 6 +- 5 files changed, 90 insertions(+), 119 deletions(-) create mode 100644 src/st-trace/trace.h diff --git a/inc/stlink.h b/inc/stlink.h index 0c3675083..d516e5c4f 100644 --- a/inc/stlink.h +++ b/inc/stlink.h @@ -255,9 +255,6 @@ int32_t stlink_current_mode(stlink_t *sl); int32_t stlink_force_debug(stlink_t *sl); int32_t stlink_target_voltage(stlink_t *sl); int32_t stlink_set_swdclk(stlink_t *sl, int32_t freq_khz); -int32_t stlink_trace_enable(stlink_t* sl, uint32_t frequency); -int32_t stlink_trace_disable(stlink_t* sl); -int32_t stlink_trace_read(stlink_t* sl, uint8_t* buf, uint32_t size); int32_t stlink_parse_ihex(const char* path, uint8_t erased_pattern, uint8_t* *mem, uint32_t* size, uint32_t* begin); uint8_t stlink_get_erased_pattern(stlink_t *sl); int32_t stlink_mwrite_sram(stlink_t *sl, uint8_t* data, uint32_t length, stm32_addr_t addr); diff --git a/src/st-trace/trace.c b/src/st-trace/trace.c index 4ef03c07b..591e29252 100644 --- a/src/st-trace/trace.c +++ b/src/st-trace/trace.c @@ -97,6 +97,20 @@ BOOL WINAPI CtrlHandler(DWORD fdwCtrlType) { } #endif +int32_t stlink_trace_enable(stlink_t *sl, uint32_t frequency) { + DLOG("*** stlink_trace_enable ***\n"); + return (sl->backend->trace_enable(sl, frequency)); +} + +int32_t stlink_trace_disable(stlink_t *sl) { + DLOG("*** stlink_trace_disable ***\n"); + return (sl->backend->trace_disable(sl)); +} + +int32_t stlink_trace_read(stlink_t *sl, uint8_t *buf, uint32_t size) { + return (sl->backend->trace_read(sl, buf, size)); +} + static void usage(void) { puts("st-trace - usage:"); puts(" -h, --help Print this help"); @@ -112,8 +126,7 @@ static void usage(void) { puts(" -f, --force Ignore most initialization errors"); } -static bool parse_frequency(char* text, uint32_t* result) -{ +static bool parse_frequency(char* text, uint32_t* result) { if (text == NULL) { ELOG("Invalid frequency.\n"); return false; @@ -193,12 +206,10 @@ bool parse_options(int32_t argc, char **argv, st_settings_t *settings) { ugly_init(settings->logging_level); break; case 'c': - if (!parse_frequency(optarg, &settings->core_frequency)) - error = true; + if (!parse_frequency(optarg, &settings->core_frequency)) error = true; break; case 't': - if (!parse_frequency(optarg, &settings->trace_frequency)) - error = true; + if (!parse_frequency(optarg, &settings->trace_frequency)) error = true; break; case 'n': settings->reset_board = false; @@ -226,29 +237,24 @@ bool parse_options(int32_t argc, char **argv, st_settings_t *settings) { error = true; } - if (error && !settings->force) - return false; + if (error && !settings->force) return false; return true; } static stlink_t *stlink_connect(const st_settings_t *settings) { - return stlink_open_usb(settings->logging_level, false, - settings->serial_number, 0); + return stlink_open_usb(settings->logging_level, false, settings->serial_number, 0); } -static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, - uint32_t trace_frequency) { +static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, uint32_t trace_frequency) { if (stlink_force_debug(stlink)) { ELOG("Unable to debug device\n"); - if (!settings->force) - return false; + if (!settings->force) return false; } if (settings->reset_board && stlink_reset(stlink, RESET_SOFT_AND_HALT)) { ELOG("Unable to reset device\n"); - if (!settings->force) - return false; + if (!settings->force) return false; } stlink_write_debug32(stlink, STLINK_REG_DHCSR, @@ -262,29 +268,24 @@ static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION2, 0); stlink_write_debug32(stlink, STLINK_REG_DWT_FUNCTION3, 0); stlink_write_debug32(stlink, STLINK_REG_DWT_CTRL, 0); - stlink_write_debug32( - stlink, STLINK_REG_DBGMCU_CR, + stlink_write_debug32(stlink, STLINK_REG_DBGMCU_CR, STLINK_REG_DBGMCU_CR_DBG_SLEEP | STLINK_REG_DBGMCU_CR_DBG_STOP | STLINK_REG_DBGMCU_CR_DBG_STANDBY | STLINK_REG_DBGMCU_CR_TRACE_IOEN | STLINK_REG_DBGMCU_CR_TRACE_MODE_ASYNC); if (stlink_trace_enable(stlink, trace_frequency)) { ELOG("Unable to turn on tracing in stlink\n"); - if (!settings->force) - return false; + if (!settings->force) return false; } - stlink_write_debug32(stlink, STLINK_REG_TPI_CSPSR, - STLINK_REG_TPI_CSPSR_PORT_SIZE_1); + stlink_write_debug32(stlink, STLINK_REG_TPI_CSPSR, STLINK_REG_TPI_CSPSR_PORT_SIZE_1); if (settings->core_frequency) { uint32_t prescaler = settings->core_frequency / trace_frequency - 1; if (prescaler > STLINK_REG_TPI_ACPR_MAX) { - ELOG("Trace frequency prescaler %d out of range. Try setting a faster " - "trace frequency.\n", - prescaler); - if (!settings->force) - return false; + ELOG("Trace frequency prescaler %d out of range. Try setting a faster " + "trace frequency.\n", prescaler); + if (!settings->force) return false; } stlink_write_debug32(stlink, STLINK_REG_TPI_ACPR, prescaler); // Set TPIU_ACPR clock divisor @@ -294,12 +295,11 @@ static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, stlink_write_debug32(stlink, STLINK_REG_TPI_SPPR, STLINK_REG_TPI_SPPR_SWO_NRZ); stlink_write_debug32(stlink, STLINK_REG_ITM_LAR, STLINK_REG_ITM_LAR_KEY); - stlink_write_debug32(stlink, STLINK_REG_ITM_TCC, - 0x00000400); // Set sync counter + stlink_write_debug32(stlink, STLINK_REG_ITM_TCC, 0x00000400); // Set sync counter stlink_write_debug32(stlink, STLINK_REG_ITM_TCR, STLINK_REG_ITM_TCR_TRACE_BUS_ID_1 | - STLINK_REG_ITM_TCR_TS_ENA | - STLINK_REG_ITM_TCR_ITM_ENA); + STLINK_REG_ITM_TCR_TS_ENA | + STLINK_REG_ITM_TCR_ITM_ENA); stlink_write_debug32(stlink, STLINK_REG_ITM_TER, STLINK_REG_ITM_TER_PORTS_ALL); stlink_write_debug32(stlink, STLINK_REG_ITM_TPR, @@ -333,9 +333,7 @@ static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, static trace_state update_trace_idle(st_trace_t *trace, uint8_t c) { // Handle a trace byte when we are in the idle state. - if (TRACE_OP_IS_TARGET_SOURCE(c)) { - return TRACE_STATE_TARGET_SOURCE; - } + if (TRACE_OP_IS_TARGET_SOURCE(c)) return TRACE_STATE_TARGET_SOURCE; if (TRACE_OP_IS_SOURCE(c)) { uint8_t size = TRACE_OP_GET_SOURCE_SIZE(c); @@ -345,36 +343,28 @@ static trace_state update_trace_idle(st_trace_t *trace, uint8_t c) { WLOG("Unsupported source 0x%x size %d\n", addr, size); trace->unknown_sources |= (1 << addr); } - if (size == 1) - return TRACE_STATE_SKIP_1; - if (size == 2) - return TRACE_STATE_SKIP_2; - if (size == 3) - return TRACE_STATE_SKIP_4; + if (size == 1) return TRACE_STATE_SKIP_1; + if (size == 2) return TRACE_STATE_SKIP_2; + if (size == 3) return TRACE_STATE_SKIP_4; } if (TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) { trace->count_time_packets++; - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME - : TRACE_STATE_IDLE; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; } if (TRACE_OP_IS_EXTENSION(c)) { - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME - : TRACE_STATE_IDLE; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; } - if (TRACE_OP_IS_OVERFLOW(c)) { - trace->count_hw_overflow++; - } + if (TRACE_OP_IS_OVERFLOW(c)) trace->count_hw_overflow++; if (!(trace->unknown_opcodes[c / 8] & (1 << c % 8))) WLOG("Unknown opcode 0x%02x\n", c); trace->unknown_opcodes[c / 8] |= (1 << c % 8); trace->count_error++; - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME - : TRACE_STATE_IDLE; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; } static trace_state update_trace(st_trace_t *trace, uint8_t c) { @@ -383,8 +373,7 @@ static trace_state update_trace(st_trace_t *trace, uint8_t c) { // Parse the input using a state machine. if (trace->state == TRACE_STATE_UNKNOWN) { - if (TRACE_OP_IS_TARGET_SOURCE(c) || TRACE_OP_IS_LOCAL_TIME(c) || - TRACE_OP_IS_GLOBAL_TIME(c)) + if (TRACE_OP_IS_TARGET_SOURCE(c) || TRACE_OP_IS_LOCAL_TIME(c) || TRACE_OP_IS_GLOBAL_TIME(c)) trace->state = TRACE_STATE_IDLE; } @@ -394,14 +383,12 @@ static trace_state update_trace(st_trace_t *trace, uint8_t c) { case TRACE_STATE_TARGET_SOURCE: putchar(c); - if (c == '\n') - fflush(stdout); + if (c == '\n') fflush(stdout); trace->count_target_data++; return TRACE_STATE_IDLE; case TRACE_STATE_SKIP_FRAME: - return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME - : TRACE_STATE_IDLE; + return TRACE_OP_GET_CONTINUATION(c) ? TRACE_STATE_SKIP_FRAME : TRACE_STATE_IDLE; case TRACE_STATE_SKIP_4: return TRACE_STATE_SKIP_3; @@ -425,7 +412,7 @@ static trace_state update_trace(st_trace_t *trace, uint8_t c) { } static bool read_trace(stlink_t *stlink, st_trace_t *trace) { - uint8_t buffer[max_trace_buf_len]; + uint8_t* buffer = 0; int32_t length = stlink_trace_read(stlink, buffer, sizeof(buffer)); if (length < 0) { @@ -453,8 +440,7 @@ static bool read_trace(stlink_t *stlink, st_trace_t *trace) { return true; } -static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, - uint32_t trace_frequency) { +static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, uint32_t trace_frequency) { // Only check configuration one time after the first 10 seconds of running. time_t elapsed_time_s = time(NULL) - trace->start_time; if (trace->configuration_checked || elapsed_time_s < 10) { @@ -469,8 +455,7 @@ static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, bool error_bad_data = (trace->count_error > 1 || trace->unknown_sources > 0); bool error_dropped_data = (trace->count_sw_overflow > 0); - if (!error_no_data && !error_low_data && !error_bad_data && - !error_dropped_data) + if (!error_no_data && !error_low_data && !error_bad_data && !error_dropped_data) return; WLOG("****\n"); @@ -487,8 +472,7 @@ static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, stlink_read_debug32(stlink, STLINK_REG_TPI_ACPR, &prescaler); if (prescaler) { uint32_t system_clock_speed = (prescaler + 1) * trace_frequency; - WLOG("Verify the system clock is running at %d Hz.\n", - system_clock_speed); + WLOG("Verify the system clock is running at %d Hz.\n", system_clock_speed); } WLOG("Try specifying the system clock with the --clock=XX command line " "option.\n"); @@ -510,11 +494,8 @@ static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, uint32_t offset = 0; for (uint32_t i = 0; i <= 0xFF; i++) if (trace->unknown_opcodes[i / 8] & (1 << i % 8)) { - uint32_t n = - snprintf(buffer + offset, sizeof(buffer) - offset, "%02x, ", i); - if (n >= sizeof(buffer) - offset) { - break; - } + uint32_t n = snprintf(buffer + offset, sizeof(buffer) - offset, "%02x, ", i); + if (n >= sizeof(buffer) - offset) break; offset += n; } WLOG("Unknown Opcodes: %s\n", buffer); @@ -523,11 +504,8 @@ static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, offset = 0; for (uint32_t i = 0; i < 32; i++) if (trace->unknown_sources & (1 << i)) { - uint32_t n = - snprintf(buffer + offset, sizeof(buffer) - offset, "%d, ", i); - if (n >= sizeof(buffer) - offset) { - break; - } + uint32_t n = snprintf(buffer + offset, sizeof(buffer) - offset, "%d, ", i); + if (n >= sizeof(buffer) - offset) break; offset += n; } WLOG("Unknown Sources: %s\n", buffer); @@ -583,48 +561,38 @@ int32_t main(int32_t argc, char **argv) { if (stlink->chip_id == STM32_CHIPID_UNKNOWN) { ELOG("Your stlink is not connected to a device\n"); - if (!settings.force) - return APP_RESULT_STLINK_MISSING_DEVICE; + if (!settings.force) return APP_RESULT_STLINK_MISSING_DEVICE; } if (!(stlink->version.flags & STLINK_F_HAS_TRACE)) { ELOG("Your stlink does not support tracing\n"); - if (!settings.force) - return APP_RESULT_STLINK_UNSUPPORTED_LINK; + if (!settings.force) return APP_RESULT_STLINK_UNSUPPORTED_LINK; } if (!(stlink->chip_flags & CHIP_F_HAS_SWO_TRACING)) { - const struct stlink_chipid_params *params = - stlink_chipid_get_params(stlink->chip_id); - ELOG("We do not support SWO output for device '%s'\n", - params ? params->dev_type : ""); - if (!settings.force) - return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; + const struct stlink_chipid_params *params = stlink_chipid_get_params(stlink->chip_id); + ELOG("We do not support SWO output for device '%s'\n", params ? params->dev_type : ""); + if (!settings.force) return APP_RESULT_STLINK_UNSUPPORTED_DEVICE; } uint32_t trace_frequency = settings.trace_frequency; - if (!trace_frequency) - trace_frequency = STLINK_DEFAULT_TRACE_FREQUENCY; + if (!trace_frequency) trace_frequency = STLINK_DEFAULT_TRACE_FREQUENCY; uint32_t max_trace_freq = stlink->max_trace_freq; uint32_t min_trace_freq = 0; if (settings.core_frequency != 0) { - if (max_trace_freq > settings.core_frequency / 5) - max_trace_freq = settings.core_frequency / 5; + if (max_trace_freq > settings.core_frequency / 5) max_trace_freq = settings.core_frequency / 5; min_trace_freq = settings.core_frequency / (STLINK_REG_TPI_ACPR_MAX + 1); } - if (trace_frequency > max_trace_freq || - trace_frequency < min_trace_freq) { - ELOG("Invalid trace frequency %d (min %d max %d)\n", trace_frequency, - min_trace_freq, max_trace_freq); - if (!settings.force) - return APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY; + if (trace_frequency > max_trace_freq || trace_frequency < min_trace_freq) { + ELOG("Invalid trace frequency %d (min %d max %d)\n", trace_frequency, min_trace_freq, + max_trace_freq); + if (!settings.force) return APP_RESULT_UNSUPPORTED_TRACE_FREQUENCY; } if (!enable_trace(stlink, &settings, trace_frequency)) { ELOG("Unable to enable trace mode\n"); - if (!settings.force) - return APP_RESULT_STLINK_STATE_ERROR; + if (!settings.force) return APP_RESULT_STLINK_STATE_ERROR; } ILOG("Reading Trace\n"); @@ -634,8 +602,7 @@ int32_t main(int32_t argc, char **argv) { if (stlink_run(stlink, RUN_NORMAL)) { ELOG("Unable to run device\n"); - if (!settings.force) - return APP_RESULT_STLINK_STATE_ERROR; + if (!settings.force) return APP_RESULT_STLINK_STATE_ERROR; } while (!g_abort_trace && read_trace(stlink, &trace)) { diff --git a/src/st-trace/trace.h b/src/st-trace/trace.h new file mode 100644 index 000000000..8dfc7e42d --- /dev/null +++ b/src/st-trace/trace.h @@ -0,0 +1,24 @@ +/* + * File: trace.h + * + * Tool st-trace + */ + +#ifndef TRACE_H +#define TRACE_H + +int32_t stlink_trace_enable(stlink_t* sl, uint32_t frequency); +int32_t stlink_trace_disable(stlink_t* sl); +int32_t stlink_trace_read(stlink_t* sl, uint8_t* buf, uint32_t size); + +static void usage(void); +static bool parse_frequency(char* text, uint32_t* result); +bool parse_options(int32_t argc, char **argv, st_settings_t *settings); +static stlink_t *stlink_connect(const st_settings_t *settings); +static bool enable_trace(stlink_t *stlink, const st_settings_t *settings, uint32_t trace_frequency); +static trace_state update_trace_idle(st_trace_t *trace, uint8_t c); +static trace_state update_trace(st_trace_t *trace, uint8_t c); +static bool read_trace(stlink_t *stlink, st_trace_t *trace); +static void check_for_configuration_error(stlink_t *stlink, st_trace_t *trace, uint32_t trace_frequency); + +#endif // TRACE_H \ No newline at end of file diff --git a/src/stlink-lib/common.c b/src/stlink-lib/common.c index c9bf67157..3e49a779d 100644 --- a/src/stlink-lib/common.c +++ b/src/stlink-lib/common.c @@ -599,23 +599,6 @@ int32_t stlink_current_mode(stlink_t *sl) { return (STLINK_DEV_UNKNOWN_MODE); } -// 274 -int32_t stlink_trace_enable(stlink_t *sl, uint32_t frequency) { - DLOG("*** stlink_trace_enable ***\n"); - return (sl->backend->trace_enable(sl, frequency)); -} - -// 275 -int32_t stlink_trace_disable(stlink_t *sl) { - DLOG("*** stlink_trace_disable ***\n"); - return (sl->backend->trace_disable(sl)); -} - -// 276 -int32_t stlink_trace_read(stlink_t *sl, uint8_t *buf, uint32_t size) { - return (sl->backend->trace_read(sl, buf, size)); -} - // 294 void stlink_print_data(stlink_t *sl) { if (sl->q_len <= 0 || sl->verbose < UDEBUG) { diff --git a/src/stlink-lib/usb.c b/src/stlink-lib/usb.c index b0d0494cf..83e2652ea 100644 --- a/src/stlink-lib/usb.c +++ b/src/stlink-lib/usb.c @@ -977,13 +977,13 @@ int32_t _stlink_usb_enable_trace(stlink_t* sl, uint32_t frequency) { unsigned char* const cmd = sl->c_buf; ssize_t size; uint32_t rep_len = 2; - uint32_t max_trace_buf_len; + uint32_t max_trace_buf_len = 0; if(sl->version.stlink_v == 2) { max_trace_buf_len = STLINK_V2_TRACE_BUF_LEN; - } else (sl->version.stlink_v == 3) { + } else if (sl->version.stlink_v == 3) { max_trace_buf_len = STLINK_V3_TRACE_BUF_LEN; - } + }; int32_t i = fill_command(sl, SG_DXFER_TO_DEV, rep_len); cmd[i++] = STLINK_DEBUG_COMMAND; From 8c581c3eec91248de028c332a06ea276bbb2e969 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Mon, 25 Dec 2023 14:40:10 +0100 Subject: [PATCH 1431/1435] Updated CHANGELOG.md --- CHANGELOG.md | 1 + src/stlink-lib/common_flash.c | 4 +--- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index c477eb54a..c1f998600 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -95,6 +95,7 @@ Fixes: - [compilation] Corrected path to stlink/chips subdirectory ([#1276](https://github.com/stlink-org/stlink/pull/1276), [#1279](https://github.com/stlink-org/stlink/pull/1279)) - [compilation] Fixed GUI compilation failure on OpenBSD i386 ([#1284](https://github.com/stlink-org/stlink/pull/1284)) - [STM32U5x5]: Last bytes are not written (flashed) when len()%16 <= 8 ([#1303](https://github.com/stlink-org/stlink/pull/1303), [#1315](https://github.com/stlink-org/stlink/pull/1315)) +- [STM32WLE]: Erase flash fails on second page ([#1305](https://github.com/stlink-org/stlink/pull/1305), commit [#7dcb130](https://github.com/stlink-org/stlink/commit/7dcb1302d8b91b2217c4ce50cb255aa8e78ab001)) - Fixed unbounded write and check return values of sscanf ([#1306](https://github.com/stlink-org/stlink/pull/1306)) - Added null check for return value of stlink_chipid_get_params() ([#1307](https://github.com/stlink-org/stlink/pull/1307)) - Fixed warning in a few *.cmake files ([#1309](https://github.com/stlink-org/stlink/pull/1309)) diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index ef6b8370c..6a519f1fc 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -387,9 +387,7 @@ int32_t check_flash_error(stlink_t *sl) { res &= ~PGAERR; } - if (res) { - ELOG("Flash programming error: %#010x\n", res); - } + if (res) ELOG("Flash programming error: %#010x\n", res); return (-1); } From 0145baeb2e3bac31bf9d3cbd0dab38d70618d46b Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sat, 20 Jan 2024 13:00:52 +0100 Subject: [PATCH 1432/1435] Fixed memory alignment for STM32L5/U5/H5 chips (Closes #1362) --- src/stlink-lib/common_flash.c | 2 +- src/stlink-lib/flash_loader.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/stlink-lib/common_flash.c b/src/stlink-lib/common_flash.c index 6a519f1fc..aa8db5bfd 100644 --- a/src/stlink-lib/common_flash.c +++ b/src/stlink-lib/common_flash.c @@ -1140,7 +1140,7 @@ int32_t stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { // set bank 1 for erasure val &= ~(1 << FLASH_L5_NSCR_NSBKER); } - // sec 7.9.9 for U5, 6.9.9 for L5 (for L7 we have 7 bits instead 8 bits for U5 but + // sec 7.9.9 for U5, 6.9.9 for L5 (for L7 we have 7 bits instead of 8 bits for U5 but // the bit position for 8th bit reserved. // Maybe the best solution is to handle each one separately. val &= ~(0xFF << 3); diff --git a/src/stlink-lib/flash_loader.c b/src/stlink-lib/flash_loader.c index 9511c9282..16c717ca7 100644 --- a/src/stlink-lib/flash_loader.c +++ b/src/stlink-lib/flash_loader.c @@ -748,6 +748,11 @@ int32_t stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, stm32_addr_t sl->flash_type == STM32_FLASH_TYPE_G4 || sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 || sl->flash_type == STM32_FLASH_TYPE_C0) { + + if (sl->flash_type == STM32_FLASH_TYPE_L5_U5_H5 && (len % 16)) { + WLOG("Data size is aligned to 16 byte"); + len += 16 - len%16; + } DLOG("Starting %3u page write\n", len / sl->flash_pgsz); for (off = 0; off < len; off += sizeof(uint32_t)) { uint32_t data; From 32e8dcc8b5dbed7b6412e7838ea1b2c41f0247fd Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Sun, 21 Jan 2024 14:43:22 +0100 Subject: [PATCH 1433/1435] [doc] Updated tutorial: Access to the UART via a virtual COM port (Closes #1334) --- doc/tutorial.md | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/doc/tutorial.md b/doc/tutorial.md index 36c80c674..da09978e7 100644 --- a/doc/tutorial.md +++ b/doc/tutorial.md @@ -43,7 +43,7 @@ The stlink-gui offers the following features: Within the GUI main window tooltips explain the available user elements. -## Solutions to common problems +## HowTos & solutions to common problems ### a) Verify if udev rules are set correctly (by Dave Hylands) @@ -164,6 +164,17 @@ However the external bus can be *RAM* or *ROM* depending on design. The STM32H735-DK has external FLASH at address 0x90000000. As a result, because the entire external memory range is `ram` as it could be either, software breakpoints (Z0) get sent when a breakpoint is created and they never get tripped as the memory area is read only. +### f) UART-Access via a virtual COM port + +Access to the Universal Asynchronous Receiver Transmitter (UART) via a virtual COM port is not related to the stlink toolset itself. It is an independent feature that should natively be available on UNIX-based operating systems. Windows operating systems require the installation of a virtual COM device driver. The appropriate device driver is downloaded and installed automatically via Windows Update in the background as soon as the device is plugged-in for the first time. A connected ST-LINK programmer with UART functionality is detected as a CDC (ACM) USB device. After each reset the device will be reloaded and will pop up as `/dev/ttyACM0` or `/dev/ttyACM1` depending on the specific design. + +UART connections to the interface are typically initiated with a serial terminal. For UNIX operating systems we recommend to use either [minicom](https://en.wikipedia.org/wiki/Minicom) (terminal-based) or [cutecom](https://cutecom.sourceforge.net/) (GUI-based). Windows users should have a look at [Teraterm](https://github.com/TeraTermProject/teraterm). + +Most common and established settings for the interface are 115200 or 9600 baud together with the `8-N-1` configuration, standing for (8) data bits, no parity bit (N) and (1) stop bit. Please refer to relevant literature on the UART interface for more detailed technical information and limitations. + +Note: On some debian-based UNIX-based systems the `modemmanager` package is installed by default. In has been reported that this tool unfortunately may delay the release of the serial port to applications which is handled by the operating system in the background. Subseqently the CDC/ACM device is also delayed after each reset. This typically includes not only the connection itself, but also some programming operations (at least those using the mass storage emulation). However one can not predict the behaviour exactly - in some cases the boards may be essentially useless or even working fairly well. +Proper determined functionality can be achieved by uninstalling the `modemmanager` package or by setting an appropriate `udev` device rule. + --- ( Content below is currently unrevised and may be outdated as of Mar 2021. ) From 926e7efe4c44fdf1deac0138c6c78965d49e7dc3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Tue, 30 Jan 2024 23:40:04 +0100 Subject: [PATCH 1434/1435] General Project Update - Updated build script for Windows - [doc] Updated documentation on: --> compile instructions --> release preparation steps --> list of supported devices --> OS version support status --- doc/compiling.md | 38 ++------------------------------------ doc/release.md | 14 +++++++------- doc/supported_devices.md | 7 +++++-- doc/version_support.md | 2 +- mingw64-build.bat | 2 +- 5 files changed, 16 insertions(+), 47 deletions(-) diff --git a/doc/compiling.md b/doc/compiling.md index e2c686c0a..804781faa 100644 --- a/doc/compiling.md +++ b/doc/compiling.md @@ -16,35 +16,14 @@ On Windows users should ensure that the following software is installed: 1. Install `git` from 2. Install `cmake` from
      Ensure that you add cmake to the $PATH system variable when following the instructions by the setup assistant. -3. Install - - - _EITHER_: Download **MinGW-w64** from . Extract content to `C:\mingw-w64\` and add `C:\mingw-w64\bin\` to PATH-Variable.
      - - _OR_: **MSVC toolchain** from Visual Studio Build Tools 2019 +3. Install MinGW-w64
      + Download **MinGW-w64** from . Extract content to `C:\mingw-w64\` and add `C:\mingw-w64\bin\` to PATH-Variable.
      4. Create a new destination folder at a place of your choice 5. Open the command-line (cmd.exe) and execute `cd C:\$Path-to-your-destination-folder$\` 6. Fetch the project sourcefiles by running `git clone https://github.com/stlink-org/stlink.git`from the command-line (cmd.exe)
      or download and extract the stlink zip-sourcefolder from the Release page on GitHub. -#### MSVC toolchain - minimal installation - -Visual Studio IDE is not necessary, only Windows SDK & build tools are required (~3,3GB). - -1. Open -2. Navigate through menus as follows (might change overtime) - - `All downloads > Tools for Visual Studio 2019 > Build Tools for Visual Studio 2019 > Download` - -3. Start downloaded executable. After Visual Studio Installer bootstraps and main window pops up, open `Individual Components` tab, and pick - -- latest build tools (eg. `MSVC v142 - VS 2019 C++ x64/x86 build tools (v14.25)`) -- latest Windows SDK (eg. `Windows 10 SDK (10.0.18362.0)`) - -4. After installation finishes, you can press `Launch` button in Visual Studio Installer's main menu. - - Thus you can open `Developer Command Prompt for VS 2019`. It is `cmd.exe` instance with adjusted PATHs including eg. `msbuild`. - - Alternatively, you can use `Developer Powershell for VS 2019` which is the same thing for `powershell.exe`. Both are available from Start menu. - - Another option is to add `msbuild` to PATH manually. Its location should be `C:\Program Files (x86)\Microsoft Visual Studio\2019\BuildTools\MSBuild\Current\Bin`. Then, it should be available from any `powershell.exe` or `cmd.exe` session. - ### Building #### MinGW-w64 @@ -58,19 +37,6 @@ Per default the build script (currently) uses `C:\mingw-w64\x86_64-8.1.0-release When installing different toolchains make sure to update the path in the `mingw64-build.bat`.
      This can be achieved by opening the .bat file with a common text editor. -#### MSVC toolchain - -1. In a command prompt, change the directory to the folder where the stlink files were cloned (or unzipped) to. -2. Make sure the build folder exists (`mkdir build` if not). -3. From the build folder, run cmake (`cd build; cmake ..`). - -This will create a solution file `stlink.sln` in the build folder. -Now, you can build whole `stlink` suite using following command: - -``` -msbuild /m /p:Configuration=Release stlink.sln -``` - Options: - `/m` - compilation runs in parallel utilizing multiple cores diff --git a/doc/release.md b/doc/release.md index 7d5ead83c..25cb2d5ff 100644 --- a/doc/release.md +++ b/doc/release.md @@ -3,12 +3,12 @@ Release This document describes the necessary steps for developers to create a release: -1. Update `CHANGELOG.md`, `cmake/packaging/deb/changelog` & `cmake/packaging/rpm/changelog` +1. Update changelog (`CHANGELOG.md`, `cmake/packaging/deb/changelog` & `cmake/packaging/rpm/changelog`) 2. Update `.version` with semantic version: `x.x.x` 3. Update `README.md` with semantic version `x.x.x` in commits badge -4. Merge `develop` into `master` -5. Create and push git tag and commits `git tag x.x.x` -6. Create binary packages (.rpm / .deb / .zip) with `make package && sh ./cmake/packaging/windows/generate_binaries.sh` -7. Upload packages to the [release page](https://github.com/stlink-org/stlink/releases) of this project -8. Merge `master` into `develop` -9. Update GitHub security policy (/SECURITY.md) +4. Update GitHub security policy (`SECURITY.md`) +5. Merge `develop` into `master` +6. Create and push git tag and commits `git tag x.x.x` +7. Create binary packages (.rpm / .deb / .zip) with `make package && sh ./cmake/packaging/windows/generate_binaries.sh` +8. Upload packages to the [release page](https://github.com/stlink-org/stlink/releases) of this project +9. Merge `master` into `develop` diff --git a/doc/supported_devices.md b/doc/supported_devices.md index 103c7fb5f..b22b1c11a 100644 --- a/doc/supported_devices.md +++ b/doc/supported_devices.md @@ -30,10 +30,13 @@ More commonly these are: | STM32F4 | M4F | | | STM32G4 | M4F | | | STM32L4 | M4F | | -| STM32F7 | M4F | | -| STM32H7 | M4F | | +| STM32F7 | M7F | | +| STM32H7 | M7F | | | STM32WB | M4F | | | STM32WL | M4 | | +| STM32L5 | M33 | | +| STM32H5 | M33 | | +| STM32U5 | M33 | | # Chinese Clone-Chips [may work, but without support!] diff --git a/doc/version_support.md b/doc/version_support.md index c87ad1772..c0c8389dd 100644 --- a/doc/version_support.md +++ b/doc/version_support.md @@ -34,7 +34,6 @@ Other Linux-/Unix-based Operating Systems: | Ubuntu 20.04 LTS (Focal) | 1.0.23 | 3.**16.3** | 3.24.**18** | May 2025 | | | | | | | | FreeBSD 13.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | | -| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.22.1 | 3.24.31 | Dec 2023 | | | | | | | | NetBSD 9.x | 1.0.24 | 3.21.2 | 3.24.30 | | | NetBSD 8.x | 1.0.24 | 3.**19.7** | 3.24.27 | | @@ -60,6 +59,7 @@ Systems with highlighted versions remain compatible with this toolset. | Operating System | libusb | cmake | End of
      OS-Support | | ---------------------------------------- | ------------------------------ | ---------- | ---------------------- | +| FreeBSD 12.x | 1.0.**16-18** (API 0x01000102) | 3.**22.1** | Dec 2023 | | Alpine 3.15 | 1.0.**24** | 3.**21.3** | Nov 2023 | | Fedora 35 [x64] | 1.0.**24** | 3.**21.3** | Dec 2022 | | Alpine 3.14 | 1.0.**24** | 3.**20.3** | May 2023 | diff --git a/mingw64-build.bat b/mingw64-build.bat index b52e529e2..bc50c97a3 100644 --- a/mingw64-build.bat +++ b/mingw64-build.bat @@ -2,7 +2,7 @@ mkdir build-mingw cd build-mingw -set PATH=C:\Program Files (x86)\CMake\bin;C:\Program Files\CMake\bin;C:\mingw-w64\x86_64-8.1.0-win32-sjlj-rt_v6-rev0\mingw64\bin;%PATH% +set PATH=C:\Program Files\CMake\bin;C:\mingw-w64\x86_64-13.2.0-release-win32-seh-msvcrt-rt_v11-rev1\mingw64\bin;%PATH% cmake -G "MinGW Makefiles" .. mingw32-make mingw32-make install From 133c2564dee478ed2fcf634ae217441ac723b3e3 Mon Sep 17 00:00:00 2001 From: nightwalker-87 <15526941+Nightwalker-87@users.noreply.github.com> Date: Thu, 1 Feb 2024 00:00:02 +0100 Subject: [PATCH 1435/1435] Release v1.8.0 --- .version | 2 +- CHANGELOG.md | 9 +++++---- README.md | 4 ++-- SECURITY.md | 1 + cmake/packaging/deb/changelog | 6 ++++++ cmake/packaging/rpm/changelog | 3 +++ 6 files changed, 18 insertions(+), 7 deletions(-) diff --git a/.version b/.version index bd8bf882d..27f9cd322 100644 --- a/.version +++ b/.version @@ -1 +1 @@ -1.7.0 +1.8.0 diff --git a/CHANGELOG.md b/CHANGELOG.md index c1f998600..5c618a752 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -2,14 +2,14 @@ # v1.8.0 -Release date: 2024-xx-xx +Release date: 2024-02-01 This release drops support for macOS and some older operating systems. Check project README for details. Removed Travis CI integration as it is no longer functional. Updated system requirements: -- `cmake` >= 3.10.2 -- `libusb` >= 1.0.21 +- `cmake` >= 3.13.0 +- `libusb` >= 1.0.22 - `libgtk-dev` >= 3.22.30 Features: @@ -59,7 +59,7 @@ Updates & changes: - [doc] Fixed broken links ([#1312](https://github.com/stlink-org/stlink/pull/1312)) - [doc] Updated package source link for Arch Linux ([#1318](https://github.com/stlink-org/stlink/pull/1318)) - CMake: Avoid hard-wired /usr/local/share ([#1325](https://github.com/stlink-org/stlink/pull/1325)) - +- [doc] Provide access to the UART via virtual com port ([#1334](https://github.com/stlink-org/stlink/pull/1334), commit [#32e8dcc](https://github.com/stlink-org/stlink/commit/32e8dcc8b5dbed7b6412e7838ea1b2c41f0247fd)) Fixes: @@ -104,6 +104,7 @@ Fixes: - Notification "unknown option -- u" in tool st-util ([#1326](https://github.com/stlink-org/stlink/pull/1326), [#1327](https://github.com/stlink-org/stlink/pull/1327)) - Do not crash when the STLink chip returns a voltage factor of zero ([#1343](https://github.com/stlink-org/stlink/pull/1343)) - stlink-gui: failed to allocate 139988352155568 bytes ([#1356](https://github.com/stlink-org/stlink/pull/1356)) +- [STM32U575RGT6]: Verification failed at offset 43008 ([#1362](https://github.com/stlink-org/stlink/pull/1362), commit [#0145bae](https://github.com/stlink-org/stlink/commit/0145baeb2e3bac31bf9d3cbd0dab38d70618d46b)) # v1.7.0 diff --git a/README.md b/README.md index ad1bfe910..93cdac07d 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ [![BSD licensed](https://img.shields.io/badge/license-BSD-blue.svg)](https://raw.githubusercontent.com/hyperium/hyper/master/LICENSE) [![GitHub release](https://img.shields.io/github/release/stlink-org/stlink.svg)](https://github.com/stlink-org/stlink/releases/latest) [![Downloads](https://img.shields.io/github/downloads/stlink-org/stlink/total)](https://github.com/stlink-org/stlink/releases/latest) -![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.7.0/develop) +![GitHub commits](https://img.shields.io/github/commits-since/stlink-org/stlink/v1.8.0/develop) ![GitHub activity](https://img.shields.io/github/commit-activity/m/stlink-org/stlink) ![GitHub contributors](https://img.shields.io/github/contributors/stlink-org/stlink) [![CodeQL](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml/badge.svg)](https://github.com/stlink-org/stlink/actions/workflows/codeql-analysis.yml) @@ -81,7 +81,7 @@ We recommend to install `stlink-tools` from the package repository of the used d **macOS**: -**Support for macOS will be dropped with v1.8.0.** +**Support for macOS has been dropped with v1.8.0.** Please use v1.7.0 instead, **but note that this version is no longer maintained and supported!** diff --git a/SECURITY.md b/SECURITY.md index 13432b927..3a357bafc 100644 --- a/SECURITY.md +++ b/SECURITY.md @@ -7,6 +7,7 @@ The following versions of the stlink toolset are currently being supported.
      Thu, 01 Feb 2024 00:00:00 +0100 + stlink (1.7.0) unstable; urgency=medium * Release v1.7.0 diff --git a/cmake/packaging/rpm/changelog b/cmake/packaging/rpm/changelog index 3d1c76996..36853060d 100644 --- a/cmake/packaging/rpm/changelog +++ b/cmake/packaging/rpm/changelog @@ -1,3 +1,6 @@ +* Thu Feb 01 2024 Nightwalker-87 - 1.8.0 +- Release v1.8.0 + * Sun Apr 25 2021 Nightwalker-87 - 1.7.0 - Release v1.7.0

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\section{Installing a GNU toolchain} \section{Installing STLINK} \paragraph{} -STLINK is an opensource software to program and debug the discovery kits. Those +STLINK is open source software to program and debug ST's STM32 Discovery kits. Those kits have an onboard chip that translates USB commands sent by the host PC into -JTAG commands. This chip is called STLINK, which is confusing since the software -has the same name. It comes into 2 versions (STLINK v1 and v2). From a software +JTAG/SWD commands. This chip is called STLINK, (yes, isn't that confusing? suggest a better +name!) and comes in 2 versions (STLINK v1 and v2). From a software point of view, those versions differ only in the transport layer used to communicate -(v1 uses SCSI passthru commands, while v2 uses raw USB). +(v1 uses SCSI passthru commands, while v2 uses raw USB). From a user point of view, they +are identical. \paragraph{} Before continuing, the following dependencies must be met: \begin{itemize} \item libusb-1.0 -\item libsgutils2 (optionnal) \end{itemize} \paragraph{} @@ -78,7 +78,7 @@ \section{Installing STLINK} \begin{small} \begin{lstlisting}[frame=tb] $> cd stlink.git -$> make CONFIG_USE_LIBSG=0 +$> make \end{lstlisting} \end{small} It includes: @@ -95,13 +95,20 @@ \section{Building and running a program} A simple LED blinking example is provided in the example directory. It is built using:\\ \begin{small} \begin{lstlisting}[frame=tb] -# update the make option accordingly to your architecture cd stlink.git/example/blink ; PATH=$TOOLCHAIN_PATH/bin:$PATH make \end{lstlisting} \end{small} This builds three files, one for each of the Discovery boards currently -available. +available, linked to run from SRAM. (So no risk of overwriting anything you didn't mean to) +These blink examples can safely be used to verify that: + +\begin{itemize} +\item Your installed toolchain is capable of compiling for cortex M3/M4 targets +\item stlink is functional +\item Your arm-none-eabi-gdb is functional +\item Your board is functional +\end{itemize} \paragraph{} A GDB server must be started to interact with the STM32. Depending on the discovery kit you @@ -109,10 +116,10 @@ \section{Building and running a program} \begin{small} \begin{lstlisting}[frame=tb] # STM32VL discovery kit (onboard ST-link) -$> sudo ./st-util --stlinkv1 [-d /dev/sg2] +$> ./st-util --stlinkv1 # STM32L or STM32F4 discovery kit (onboard ST-link/V2) -$> sudo ./st-util +$> ./st-util # Full help for other options (listen port, version) $> ./st-util --help @@ -140,7 +147,8 @@ \section{Building and running a program} memory map, GDB knows this address belongs to SRAM. To load the program in SRAM, simply use:\\ \begin{small} \begin{lstlisting}[frame=tb] -$> load blink.elf +$> # Choose one as appropriate for your Discovery kit +$> load blink_32L.elf | load blink_32VL.elf | load blink_F4.elf \end{lstlisting} \end{small} @@ -154,8 +162,7 @@ \section{Building and running a program} \end{small} \paragraph{} -The board BLUE and GREEN leds should be blinking (those leds are near the user and reset buttons). - +All the LEDs on the board should now be blinking in time (those leds are near the user and reset buttons). \newpage \section{Reading and writing to flash} @@ -168,13 +175,13 @@ \section{Reading and writing to flash} $> cd stlink.git/flash ; # stlinkv1 command to read 4096 from flash into out.bin -$> ./flash read /dev/sg2 out.bin 0x8000000 4096 +$> ./flash read v1 out.bin 0x8000000 4096 # stlinkv2 command $> ./flash read out.bin 0x8000000 4096 # stlinkv1 command to write the file in.bin into flash -$> ./flash write /dev/sg2 in.bin 0x8000000 +$> ./flash write v1 in.bin 0x8000000 # stlinkv2 command $> ./flash write in.bin 0x8000000 @@ -225,16 +232,6 @@ \subsection{libstm32l\_discovery} \end{lstlisting} \end{small} -\subsection{STM32VL support} -\paragraph{} -It seems support for STM32VL is quite broken. If it does not work, try build STLINK using libsg: -\begin{small} -\begin{lstlisting}[frame=tb] -$> cd stlink.git -$> make CONFIG_USE_LIBSG=1 -\end{lstlisting} -\end{small} - \newpage \section{References} diff --git a/flash/main.c b/flash/main.c index 849b5d6cd..44157816e 100644 --- a/flash/main.c +++ b/flash/main.c @@ -88,8 +88,7 @@ int main(int ac, char** av) if (o.devname != NULL) /* stlinkv1 */ { - static const int scsi_verbose = 2; - sl = stlink_v1_open(o.devname, scsi_verbose); + sl = stlink_v1_open(100); if (sl == NULL) goto on_error; } else /* stlinkv2 */ From e2245196082f8cac03b0a57a12198d9396c3ca85 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 02:30:13 +0000 Subject: [PATCH 0036/1435] Include a udev rules file for v1 boards too, for permissions --- 49-stlinkv1.rules | 11 +++++++++++ README | 6 +++--- 2 files changed, 14 insertions(+), 3 deletions(-) create mode 100644 49-stlinkv1.rules diff --git a/49-stlinkv1.rules b/49-stlinkv1.rules new file mode 100644 index 000000000..d474d6a40 --- /dev/null +++ b/49-stlinkv1.rules @@ -0,0 +1,11 @@ +# stm32 discovery boards, with onboard st/linkv1 +# ie, STM32VL + +SUBSYSTEMS=="usb", ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3744", \ + MODE:="0666", \ + SYMLINK+="stlinkv1_%n" + +# If you share your linux system with other users, or just don't like the +# idea of write permission for everybody, you can replace MODE:="0666" with +# OWNER:="yourusername" to create the device owned by you, or with +# GROUP:="somegroupname" and mange access using standard unix groups. diff --git a/README b/README index 109aa2500..470c52a59 100644 --- a/README +++ b/README @@ -75,13 +75,13 @@ for GDB. Setting up udev rules ===================== -For convenience, you may install udev rules file, 49-stlinkv2.rules, located +For convenience, you may install udev rules file, 49-stlinkv*.rules, located in the root of repository. You will need to copy it to /etc/udev/rules.d, and then either reboot or execute $ udevadm control --reload-rules -Udev will now create a /dev/stlinkv2_XX file, with the appropriate permissions. -This is currently all the device is for, (only one stlinkv2 is supported at +Udev will now create a /dev/stlinkv2_XX or /dev/stlinkv1_XX file, with the appropriate permissions. +This is currently all the device is for, (only one stlink of each version is supported at any time presently) Running programs from SRAM From 52b626bd16ae76df6c40d93c1d10efd334f01cec Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 4 Nov 2011 02:31:17 +0000 Subject: [PATCH 0037/1435] netbeans project update for flash utility --- nbproject/configurations.xml | 365 +++++++++++++++++++++++++++++++++++ nbproject/project.xml | 4 + 2 files changed, 369 insertions(+) diff --git a/nbproject/configurations.xml b/nbproject/configurations.xml index 47cfb040a..e129c44f6 100644 --- a/nbproject/configurations.xml +++ b/nbproject/configurations.xml @@ -839,5 +839,370 @@ + + + LOCAL_SOURCES + default + + + + flash + ${MAKE} -f Makefile + ${MAKE} -f Makefile clean + + + + DEBUG + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + src + + + CONFIG_USE_LIBSG=1 + CONFIG_USE_LIBUSB=1 + + + + + + + src + + + CONFIG_USE_LIBSG=1 + CONFIG_USE_LIBUSB=1 + + + + + + + . + + + DEBUG=1 + + + + + + + + + + diff --git a/nbproject/project.xml b/nbproject/project.xml index 580df1074..946c06f6f 100644 --- a/nbproject/project.xml +++ b/nbproject/project.xml @@ -21,6 +21,10 @@ gdbserver 0 + + flash + 0 + From fb9d6399a71ddd962d466692fc9d026e1b057c46 Mon Sep 17 00:00:00 2001 From: Petteri Aimonen Date: Thu, 10 Nov 2011 21:38:16 +0200 Subject: [PATCH 0038/1435] Fixed a bug that caused gdb to display wrong registers when using stlink ver 1. --- src/stlink-sg.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 2bbbaf9d9..1868eba18 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -707,9 +707,6 @@ void _stlink_sg_force_debug(stlink_t *sl) { void _stlink_sg_read_all_regs(stlink_t *sl, reg *regp) { struct stlink_libsg *sg = sl->backend_data; - /* unused */ - regp = regp; - clear_cdb(sg); sg->cdb_cmd_blk[1] = STLINK_DEBUG_READALLREGS; sl->q_len = 84; @@ -722,23 +719,23 @@ void _stlink_sg_read_all_regs(stlink_t *sl, reg *regp) { // 0-3 | 4-7 | ... | 60-63 | 64-67 | 68-71 | 72-75 | 76-79 | 80-83 // r0 | r1 | ... | r15 | xpsr | main_sp | process_sp | rw | rw2 for (int i = 0; i < 16; i++) { - sg->reg.r[i] = read_uint32(sl->q_buf, 4 * i); + regp->r[i] = read_uint32(sl->q_buf, 4 * i); if (sl->verbose > 1) - DLOG("r%2d = 0x%08x\n", i, sg->reg.r[i]); + DLOG("r%2d = 0x%08x\n", i, regp->r[i]); } - sg->reg.xpsr = read_uint32(sl->q_buf, 64); - sg->reg.main_sp = read_uint32(sl->q_buf, 68); - sg->reg.process_sp = read_uint32(sl->q_buf, 72); - sg->reg.rw = read_uint32(sl->q_buf, 76); - sg->reg.rw2 = read_uint32(sl->q_buf, 80); + regp->xpsr = read_uint32(sl->q_buf, 64); + regp->main_sp = read_uint32(sl->q_buf, 68); + regp->process_sp = read_uint32(sl->q_buf, 72); + regp->rw = read_uint32(sl->q_buf, 76); + regp->rw2 = read_uint32(sl->q_buf, 80); if (sl->verbose < 2) return; - DLOG("xpsr = 0x%08x\n", sg->reg.xpsr); - DLOG("main_sp = 0x%08x\n", sg->reg.main_sp); - DLOG("process_sp = 0x%08x\n", sg->reg.process_sp); - DLOG("rw = 0x%08x\n", sg->reg.rw); - DLOG("rw2 = 0x%08x\n", sg->reg.rw2); + DLOG("xpsr = 0x%08x\n", regp->xpsr); + DLOG("main_sp = 0x%08x\n", regp->main_sp); + DLOG("process_sp = 0x%08x\n", regp->process_sp); + DLOG("rw = 0x%08x\n", regp->rw); + DLOG("rw2 = 0x%08x\n", regp->rw2); } // Read an arm-core register, the index must be in the range 0..20. From e9a205ff98bea6a3a902352711a3980ccd4518be Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Fri, 11 Nov 2011 15:38:09 +0000 Subject: [PATCH 0039/1435] Finish removing sg-utils dependencies. The code deps were removed, but the flags stayed in some makefiles. --- flash/Makefile | 16 ---------------- gdbserver/Makefile | 15 --------------- 2 files changed, 31 deletions(-) diff --git a/flash/Makefile b/flash/Makefile index 8a30b4113..6e1675422 100644 --- a/flash/Makefile +++ b/flash/Makefile @@ -1,10 +1,3 @@ -# make ... for both libusb and libsg -# -# make CONFIG_USE_LIBSG=0 ... -# for just libusb -# -CC=gcc - CFLAGS+=-g CFLAGS+=-DCONFIG_USE_LIBUSB=1 CFLAGS+=-DDEBUG @@ -14,15 +7,6 @@ CFLAGS+=-I../src LDFLAGS=-lusb-1.0 -L.. -lstlink -ifeq ($(CONFIG_USE_LIBSG),) -CONFIG_USE_LIBSG=1 -endif - -ifneq ($(CONFIG_USE_LIBSG),0) -CFLAGS+=-DCONFIG_USE_LIBSG=1 -LDFLAGS+=-lsgutils2 -endif - SRCS=main.c OBJS=$(SRCS:.c=.o) diff --git a/gdbserver/Makefile b/gdbserver/Makefile index a8d1b90aa..e73103dfb 100644 --- a/gdbserver/Makefile +++ b/gdbserver/Makefile @@ -1,9 +1,3 @@ -# make ... for both libusb and libsg -# -# make CONFIG_USE_LIBSG=0 ... -# for just libusb -# - PRG := st-util OBJS = gdb-remote.o gdb-server.o @@ -11,15 +5,6 @@ CFLAGS+=-g -Wall -Werror -std=gnu99 -I../src CFLAGS+=-DCONFIG_USE_LIBUSB=1 LDFLAGS=-lusb-1.0 -L.. -lstlink -ifeq ($(CONFIG_USE_LIBSG),) -CONFIG_USE_LIBSG=1 -endif - -ifneq ($(CONFIG_USE_LIBSG),0) -CFLAGS+=-DCONFIG_USE_LIBSG=1 -LDFLAGS+=-lsgutils2 -endif - all: $(PRG) $(PRG): $(OBJS) From 5a5d36fdc3f1732d595fe923e45433d9e32077af Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 12 Nov 2011 20:36:43 +0000 Subject: [PATCH 0040/1435] Move all the flash size mapping from gdb server into core. All the device params like flash size and page size should all be in the core open routines, not _only_ in the gdbserver. (This should stop it from ending up duplicated in the core, and get rid of some of the hacks that were turning up. All of this is chip specific!) --- gdbserver/gdb-server.c | 76 +++------------------- src/stlink-common.c | 44 +++++++++++++ src/stlink-common.h | 141 +++++++++++++++++++++++++++++++++++++---- src/stlink-sg.c | 16 +---- src/stlink-usb.c | 40 +----------- 5 files changed, 185 insertions(+), 132 deletions(-) diff --git a/gdbserver/gdb-server.c b/gdbserver/gdb-server.c index bcb3c974b..ce0549e7a 100644 --- a/gdbserver/gdb-server.c +++ b/gdbserver/gdb-server.c @@ -45,39 +45,6 @@ static const char* current_memory_map = NULL; #define CORE_M3_R2 0x4BA00477 #define CORE_M4_R0 0x2BA01477 -struct chip_params { - uint32_t chip_id; - char* description; - uint32_t flash_size_reg; - uint32_t max_flash_size, flash_pagesize; - uint32_t sram_size; - uint32_t bootrom_base, bootrom_size; -} const devices[] = { - { 0x410, "F1 Medium-density device", 0x1ffff7e0, - 0x20000, 0x400, 0x5000, 0x1ffff000, 0x800 }, // table 2, pm0063 - { 0x411, "F2 device", 0, /* No flash size register found in the docs*/ - 0x100000, 0x20000, 0x20000, 0x1fff0000, 0x7800 }, // table 1, pm0059 - { 0x412, "F1 Low-density device", 0x1ffff7e0, - 0x8000, 0x400, 0x2800, 0x1ffff000, 0x800 }, // table 1, pm0063 - { 0x413, "F4 device", 0x1FFF7A10, - 0x100000, 0x20000, 0x30000, 0x1fff0000, 0x7800 }, // table 1, pm0081 - { 0x414, "F1 High-density device", 0x1ffff7e0, - 0x80000, 0x800, 0x10000, 0x1ffff000, 0x800 }, // table 3 pm0063 - // This ignores the EEPROM! (and uses the page erase size, - // not the sector write protection...) - { 0x416, "L1 Med-density device", 0x1FF8004C, // table 1, pm0062 - 0x20000, 0x100, 0x4000, 0x1ff00000, 0x1000 }, - { 0x418, "F1 Connectivity line device", 0x1ffff7e0, - 0x40000, 0x800, 0x10000, 0x1fffb000, 0x4800 }, - { 0x420, "F1 Medium-density value line device", 0x1ffff7e0, - 0x20000, 0x400, 0x2000, 0x1ffff000, 0x800 }, - { 0x428, "F1 High-density value line device", 0x1ffff7e0, - 0x80000, 0x800, 0x8000, 0x1ffff000, 0x800 }, - { 0x430, "F1 XL-density device", 0x1ffff7e0, // pm0068 - 0x100000, 0x800, 0x18000, 0x1fffe000, 0x1800 }, - { 0 } -}; - typedef struct _st_state_t { // things from command line, bleh int stlink_version; @@ -89,7 +56,7 @@ typedef struct _st_state_t { int serve(stlink_t *sl, int port); -char* make_memory_map(const struct chip_params *params, uint32_t flash_size); +char* make_memory_map(stlink_t *sl); int parse_options(int argc, char** argv, st_state_t *st) { @@ -201,6 +168,8 @@ int main(int argc, char** argv) { if(sl == NULL) return 1; break; } + + // ALLLL of this should move into "stlink_open_xxx" if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { if (stlink_current_mode(sl) == STLINK_DEV_DFU_MODE) { @@ -220,34 +189,7 @@ int main(int argc, char** argv) { printf("Chip ID is %08x, Core ID is %08x.\n", chip_id, core_id); - const struct chip_params* params = NULL; - - for(int i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { - if(devices[i].chip_id == (chip_id & 0xFFF)) { - params = &devices[i]; - break; - } - } - - if(params == NULL) { - fprintf(stderr, "Cannot recognize the connected device!\n"); - return 0; - } - - printf("Device connected: %s\n", params->description); - printf("Device parameters: SRAM: 0x%x bytes, Flash: up to 0x%x bytes in pages of 0x%x bytes\n", - params->sram_size, params->max_flash_size, params->flash_pagesize); - - FLASH_PAGE = params->flash_pagesize; - - uint32_t flash_size; - - stlink_read_mem32(sl, params->flash_size_reg, 4); - flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8); - - printf("Flash size is %d KiB.\n", flash_size); - // memory map is in 1k blocks. - current_memory_map = make_memory_map(params, flash_size * 0x400); + current_memory_map = make_memory_map(sl); while(serve(sl, state.listen_port) == 0); @@ -275,16 +217,16 @@ static const char* const memory_map_template = " " // option byte area ""; -char* make_memory_map(const struct chip_params *params, uint32_t flash_size) { +char* make_memory_map(stlink_t *sl) { /* This will be freed in serve() */ char* map = malloc(4096); map[0] = '\0'; snprintf(map, 4096, memory_map_template, - flash_size, - params->sram_size, - flash_size, params->flash_pagesize, - params->bootrom_base, params->bootrom_size); + sl->flash_size, + sl->sram_size, + sl->flash_size, sl->flash_pgsz, + sl->sys_base, sl->sys_size); return map; } diff --git a/src/stlink-common.c b/src/stlink-common.c index f58c34405..89c263046 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -305,6 +305,50 @@ void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { return; } +/** + * reads and decodes the flash parameters, as dynamically as possible + * @param sl + * @return 0 for success, or -1 for unsupported core type. + */ +int stlink_load_device_params(stlink_t *sl) { + ILOG("Loading device parameters....\n"); + chip_params_t *params = NULL; + uint32_t chip_id = stlink_chip_id(sl); + for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { + if(devices[i].chip_id == (chip_id & 0xFFF)) { + params = &devices[i]; + break; + } + } + if (params == NULL) { + WLOG("unknown chip id! %#x\n", chip_id); + return -1; + } + + // These are fixed... + sl->flash_base = STM32_FLASH_BASE; + sl->sram_base = STM32_SRAM_BASE; + + // read flash size from hardware, if possible... + if ((chip_id & 0xFFF) == STM32_CHIPID_F2) { + sl->flash_size = 0; // FIXME - need to work this out some other way, just set to max possible? + } else { + stlink_read_mem32(sl, params->flash_size_reg, 4); + uint32_t flash_size = sl->q_buf[0] | (sl->q_buf[1] << 8); + sl->flash_size = flash_size * 1024; + } + sl->flash_pgsz = params->flash_pagesize; + sl->sram_size = params->sram_size; + sl->sys_base = params->bootrom_base; + sl->sys_size = params->bootrom_size; + + ILOG("Device connected is: %s\n", params->description); + ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n", + sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, + sl->flash_pgsz); + return 0; +} + void stlink_reset(stlink_t *sl) { DLOG("*** stlink_reset ***\n"); sl->backend->reset(sl); diff --git a/src/stlink-common.h b/src/stlink-common.h index bcd60aae1..5534b6f32 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -80,10 +80,134 @@ extern "C" { #define STM32VL_CORE_ID 0x1ba01477 #define STM32L_CORE_ID 0x2ba01477 #define STM32F4_CORE_ID 0x2ba01477 + +// stm32 chipids, only lower 12 bits.. +#define STM32_CHIPID_F1_MEDIUM 0x410 +#define STM32_CHIPID_F2 0x411 +#define STM32_CHIPID_F1_LOW 0x412 +#define STM32_CHIPID_F4 0x413 +#define STM32_CHIPID_F1_HIGH 0x414 +#define STM32_CHIPID_L1_MEDIUM 0x416 +#define STM32_CHIPID_F1_CONN 0x418 +#define STM32_CHIPID_F1_VL_MEDIUM 0x420 +#define STM32_CHIPID_F1_VL_HIGH 0x428 +#define STM32_CHIPID_F1_XL 0x430 + +// Constant STM32 memory map figures +#define STM32_FLASH_BASE 0x08000000 +#define STM32_SRAM_BASE 0x20000000 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/ #define C_BUF_LEN 32 + typedef struct chip_params_ { + uint32_t chip_id; + char* description; + uint32_t flash_size_reg; + uint32_t flash_pagesize; + uint32_t sram_size; + uint32_t bootrom_base, bootrom_size; + } chip_params_t; + + + // These maps are from a combination of the Programming Manuals, and + // also the Reference manuals. (flash size reg is normally in ref man) + static const chip_params_t devices[] = { + { // table 2, PM0063 + .chip_id = 0x410, + .description = "F1 Medium-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x5000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { // table 1, PM0059 + .chip_id = 0x411, + .description = "F2 device", + .flash_size_reg = 0, /* no flash size reg found in the docs! */ + .flash_pagesize = 0x20000, + .sram_size = 0x20000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { // PM0063 + .chip_id = 0x412, + .description = "F1 Low-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2800, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = 0x413, + .description = "F4 device", + .flash_size_reg = 0x1FFF7A10, + .flash_pagesize = 0x20000, + .sram_size = 0x30000, + .bootrom_base = 0x1fff0000, + .bootrom_size = 0x7800 + }, + { + .chip_id = 0x414, + .description = "F1 High-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + // This ignores the EEPROM! (and uses the page erase size, + // not the sector write protection...) + .chip_id = 0x416, + .description = "L1 Med-density device", + .flash_size_reg = 0x1ff8004c, + .flash_pagesize = 0x100, + .sram_size = 0x4000, + .bootrom_base = 0x1ff00000, + .bootrom_size = 0x1000 + }, + { + .chip_id = 0x418, + .description = "F1 Connectivity line device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x10000, + .bootrom_base = 0x1fffb000, + .bootrom_size = 0x4800 + }, + { + .chip_id = 0x420, + .description = "F1 Medium-density Value Line device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x400, + .sram_size = 0x2000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = 0x428, + .description = "F1 High-density value line device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x8000, + .bootrom_base = 0x1ffff000, + .bootrom_size = 0x800 + }, + { + .chip_id = 0x430, + .description = "F1 XL-density device", + .flash_size_reg = 0x1ffff7e0, + .flash_pagesize = 0x800, + .sram_size = 0x18000, + .bootrom_base = 0x1fffe000, + .bootrom_size = 0x1800 + } + }; + + typedef struct { uint32_t r[16]; uint32_t xpsr; @@ -161,29 +285,21 @@ extern "C" { uint32_t core_id; int core_stat; - - - /* medium density stm32 flash settings */ -#define STM32_FLASH_BASE 0x08000000 -#define STM32_FLASH_SIZE (128 * 1024) #define STM32_FLASH_PGSZ 1024 #define STM32L_FLASH_PGSZ 256 stm32_addr_t flash_base; size_t flash_size; size_t flash_pgsz; - /* in flash system memory */ -#define STM32_SYSTEM_BASE 0x1ffff000 -#define STM32_SYSTEM_SIZE (2 * 1024) - stm32_addr_t sys_base; - size_t sys_size; - /* sram settings */ -#define STM32_SRAM_BASE 0x20000000 #define STM32_SRAM_SIZE (8 * 1024) #define STM32L_SRAM_SIZE (16 * 1024) stm32_addr_t sram_base; size_t sram_size; + + // bootloader + stm32_addr_t sys_base; + size_t sys_size; struct stlink_version_ version; }; @@ -236,6 +352,7 @@ extern "C" { int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size); int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size); int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size); + int stlink_load_device_params(stlink_t *sl); diff --git a/src/stlink-sg.c b/src/stlink-sg.c index 1868eba18..fd10c16eb 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -1100,19 +1100,6 @@ static stlink_t* stlink_open(const int verbose) { sl->core_stat = STLINK_CORE_STAT_UNKNOWN; slsg->q_addr = 0; - /* flash memory settings */ - sl->flash_base = STM32_FLASH_BASE; - sl->flash_size = STM32_FLASH_SIZE; - sl->flash_pgsz = STM32_FLASH_PGSZ; - - /* system memory */ - sl->sys_base = STM32_SYSTEM_BASE; - sl->sys_size = STM32_SYSTEM_SIZE; - - /* sram memory settings */ - sl->sram_base = STM32_SRAM_BASE; - sl->sram_size = STM32_SRAM_SIZE; - return sl; } @@ -1127,7 +1114,7 @@ stlink_t* stlink_v1_open(const int verbose) { } stlink_version(sl); - + stlink_load_device_params(sl); if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { ugly_log(UERROR, LOG_TAG, "WTF? successfully opened, but unable to read version details. BROKEN!\n"); @@ -1160,5 +1147,6 @@ stlink_t* stlink_v1_open(const int verbose) { } // re-query device info stlink_version(sl); + stlink_load_device_params(sl); return sl; } diff --git a/src/stlink-usb.c b/src/stlink-usb.c index 785f7beca..b4df70efb 100644 --- a/src/stlink-usb.c +++ b/src/stlink-usb.c @@ -673,45 +673,7 @@ stlink_t* stlink_open_usb(const int verbose) { } stlink_version(sl); - - /* per device family initialization */ - stlink_core_id(sl); - if (sl->core_id == STM32L_CORE_ID) { - - /* flash memory settings */ - sl->flash_base = STM32_FLASH_BASE; - sl->flash_size = STM32_FLASH_SIZE; - sl->flash_pgsz = STM32L_FLASH_PGSZ; - - /* system memory */ - sl->sys_base = STM32_SYSTEM_BASE; - sl->sys_size = STM32_SYSTEM_SIZE; - - /* sram memory settings */ - sl->sram_base = STM32_SRAM_BASE; - sl->sram_size = STM32L_SRAM_SIZE; - - } else if (sl->core_id == STM32VL_CORE_ID) { - - /* flash memory settings */ - sl->flash_base = STM32_FLASH_BASE; - sl->flash_size = STM32_FLASH_SIZE; - sl->flash_pgsz = STM32_FLASH_PGSZ; - - /* system memory */ - sl->sys_base = STM32_SYSTEM_BASE; - sl->sys_size = STM32_SYSTEM_SIZE; - - /* sram memory settings */ - sl->sram_base = STM32_SRAM_BASE; - sl->sram_size = STM32_SRAM_SIZE; - - } else { - - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); - goto on_libusb_error; - - } + stlink_load_device_params(sl); error = 0; From 0c587eedfd33396cc6da94850e0dfcac15a953f2 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 12 Nov 2011 20:45:41 +0000 Subject: [PATCH 0041/1435] Read chip and core id in device param loading. Instead of expecting everyone to read it every time they need to check it. Just assume it's always there. --- src/stlink-common.c | 5 +++-- src/stlink-common.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 89c263046..3391f4ff6 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -314,6 +314,7 @@ int stlink_load_device_params(stlink_t *sl) { ILOG("Loading device parameters....\n"); chip_params_t *params = NULL; uint32_t chip_id = stlink_chip_id(sl); + sl->chip_id = chip_id; for(size_t i = 0; i < sizeof(devices) / sizeof(devices[0]); i++) { if(devices[i].chip_id == (chip_id & 0xFFF)) { params = &devices[i]; @@ -342,6 +343,8 @@ int stlink_load_device_params(stlink_t *sl) { sl->sys_base = params->bootrom_base; sl->sys_size = params->bootrom_size; + sl->core_id = stlink_core_id(sl); + ILOG("Device connected is: %s\n", params->description); ILOG("SRAM size: %#x bytes (%d KiB), Flash: %#x bytes (%d KiB) in pages of %zd bytes\n", sl->sram_size, sl->sram_size / 1024, sl->flash_size, sl->flash_size / 1024, @@ -742,7 +745,6 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) { /* page an addr in the page to erase */ - stlink_core_id(sl); if (sl->core_id == STM32L_CORE_ID) { #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) @@ -1020,7 +1022,6 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned } } - stlink_core_id(sl); if (sl->core_id == STM32L_CORE_ID) { /* use fast word write. todo: half page. */ diff --git a/src/stlink-common.h b/src/stlink-common.h index 5534b6f32..9279c37f5 100644 --- a/src/stlink-common.h +++ b/src/stlink-common.h @@ -283,6 +283,7 @@ extern "C" { // transport layer verboseness: 0 for no debug info, 10 for lots int verbose; uint32_t core_id; + uint32_t chip_id; int core_stat; #define STM32_FLASH_PGSZ 1024 From 3c6f2f5231a11bc73e3bce0003318d0f87614ad1 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 01:25:56 +0000 Subject: [PATCH 0042/1435] Fix flash writing for VL cores. The change from run->step breaks the VL cores. Need to double check that this still works for L cores. The whole flash writing needs to be better abstracted. Lots more informational debug. --- src/stlink-common.c | 112 ++++++++++++++++++++++++-------------------- 1 file changed, 61 insertions(+), 51 deletions(-) diff --git a/src/stlink-common.c b/src/stlink-common.c index 3391f4ff6..4286cf001 100644 --- a/src/stlink-common.c +++ b/src/stlink-common.c @@ -24,7 +24,7 @@ /* todo: stm32l15xxx flash memory, pm0062 manual */ /* stm32f FPEC flash controller interface, pm0063 manual */ - +// TODO - all of this needs to be abstracted out.... #define FLASH_REGS_ADDR 0x40022000 #define FLASH_REGS_SIZE 0x28 @@ -412,7 +412,7 @@ void stlink_version(stlink_t *sl) { } void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { - DLOG("*** stlink_write_mem32 ***\n"); + DLOG("*** stlink_write_mem32 %u bytes to %#x\n", len, addr); if (len % 4 != 0) { fprintf(stderr, "Error: Data length doesn't have a 32 bit alignment: +%d byte.\n", len % 4); return; @@ -744,7 +744,7 @@ int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, s int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) { /* page an addr in the page to erase */ - + ILOG("Erasing flash page at addr: %#x\n", page); if (sl->core_id == STM32L_CORE_ID) { #define STM32L_FLASH_REGS_ADDR ((uint32_t)0x40023c00) @@ -853,7 +853,7 @@ int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t page) lock_flash(sl); } else { - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); + WLOG("unknown coreid: %x\n", sl->core_id); return -1; } @@ -891,13 +891,13 @@ int init_flash_loader(stlink_t *sl, flash_loader_t* fl) { /* allocate the loader in sram */ if (write_loader_to_sram(sl, &fl->loader_addr, &size) == -1) { - fprintf(stderr, "write_loader_to_sram() == -1\n"); + WLOG("Failed to write flash loader to sram!\n"); return -1; } /* allocate a one page buffer in sram right after loader */ fl->buf_addr = fl->loader_addr + size; - + ILOG("Successfully loaded flash loader in sram\n"); return 0; } @@ -960,7 +960,7 @@ int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size) { } else { - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); + WLOG("unknown coreid, not sure what flash loader to use, aborting!: %x\n", sl->core_id); return -1; } @@ -994,33 +994,38 @@ int stlink_fcheck_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned len) { size_t off; flash_loader_t fl; - + ILOG("Attempting to write %d (%#x) bytes to stm32 address: %u (%#x)\n", + len, len, addr, addr); /* check addr range is inside the flash */ if (addr < sl->flash_base) { - fprintf(stderr, "addr too low\n"); + WLOG("addr too low\n"); return -1; } else if ((addr + len) < addr) { - fprintf(stderr, "addr overruns\n"); + WLOG("addr overruns\n"); return -1; } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { - fprintf(stderr, "addr too high\n"); + WLOG("addr too high\n"); return -1; } else if ((addr & 1) || (len & 1)) { - fprintf(stderr, "unaligned addr or size\n"); + WLOG("unaligned addr or size\n"); return -1; } else if (addr & (sl->flash_pgsz - 1)) { - fprintf(stderr, "addr not a multiple of pagesize, not supported\n"); + WLOG("addr not a multiple of pagesize, not supported\n"); return -1; } /* erase each page */ + int page_count = 0; for (off = 0; off < len; off += sl->flash_pgsz) { /* addr must be an addr inside the page */ if (stlink_erase_flash_page(sl, addr + off) == -1) { - fprintf(stderr, "erase_flash_page(0x%zx) == -1\n", addr + off); - return -1; + WLOG("Failed to erase_flash_page(%#zx) == -1\n", addr + off); + return -1; } + page_count++; } + ILOG("Finished erasing %d pages of %d (%#x) bytes\n", + page_count, sl->flash_pgsz, sl->flash_pgsz); if (sl->core_id == STM32L_CORE_ID) { @@ -1139,39 +1144,41 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned val = read_uint32(sl->q_buf, 0) | (1 << 0) | (1 << 1) | (1 << 2); write_uint32(sl->q_buf, val); stlink_write_mem32(sl, STM32L_FLASH_PECR, sizeof(uint32_t)); - } - else if (sl->core_id == STM32VL_CORE_ID) - { - /* flash loader initialization */ - if (init_flash_loader(sl, &fl) == -1) { - fprintf(stderr, "init_flash_loader() == -1\n"); - return -1; - } + } else if (sl->core_id == STM32VL_CORE_ID) { + ILOG("Starting Flash write for VL core id\n"); + /* flash loader initialization */ + if (init_flash_loader(sl, &fl) == -1) { + WLOG("init_flash_loader() == -1\n"); + return -1; + } - /* write each page. above WRITE_BLOCK_SIZE fails? */ + /* write each page. above WRITE_BLOCK_SIZE fails? */ #define WRITE_BLOCK_SIZE 0x40 - for (off = 0; off < len; off += WRITE_BLOCK_SIZE) - { - /* adjust last write size */ - size_t size = WRITE_BLOCK_SIZE; - if ((off + WRITE_BLOCK_SIZE) > len) size = len - off; - - /* unlock and set programming mode */ - unlock_flash_if(sl); - set_flash_cr_pg(sl); - - if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { - fprintf(stderr, "run_flash_loader(0x%zx) == -1\n", addr + off); - return -1; + int write_block_count = 0; + for (off = 0; off < len; off += WRITE_BLOCK_SIZE) { + ILOG("Writing flash block %d of size %d (%#x)\n", write_block_count, + WRITE_BLOCK_SIZE, WRITE_BLOCK_SIZE); + /* adjust last write size */ + size_t size = WRITE_BLOCK_SIZE; + if ((off + WRITE_BLOCK_SIZE) > len) size = len - off; + + /* unlock and set programming mode */ + unlock_flash_if(sl); + set_flash_cr_pg(sl); + //DLOG("Finished setting flash cr pg, running loader!\n"); + if (run_flash_loader(sl, &fl, addr + off, base + off, size) == -1) { + WLOG("run_flash_loader(%#zx) failed! == -1\n", addr + off); + return -1; + } + lock_flash(sl); + DLOG("Finished writing block %d\n", write_block_count++); } - - lock_flash(sl); - } } else { - fprintf(stderr, "unknown coreid: %x\n", sl->core_id); - return -1; + WLOG("unknown coreid, not sure how to write: %x\n", sl->core_id); + return -1; } + ILOG("Starting verification of write complete\n"); for (off = 0; off < len; off += sl->flash_pgsz) { size_t aligned_size; @@ -1189,32 +1196,35 @@ int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t* base, unsigned if (memcmp(sl->q_buf, base + off, cmp_size)) return -1; } - + ILOG("Flash written and verified! jolly good!\n"); return 0; } +/** + * Write the given binary file into flash at address "addr" + * @param sl + * @param path readable file path, should be binary image + * @param addr where to start writing + * @return 0 on success, -ve on failure. + */ int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr) { /* write the file in flash at addr */ - int err; mapped_file_t mf = MAPPED_FILE_INITIALIZER; - if (map_file(&mf, path) == -1) { - fprintf(stderr, "map_file() == -1\n"); + WLOG("map_file() == -1\n"); return -1; } - err = stlink_write_flash(sl, addr, mf.base, mf.len); - unmap_file(&mf); - return err; } int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size) { reg rr; - + DLOG("Running flash loader, write address:%#x, size: %zd\n", target, size); + // FIXME This can never return -1 if (write_buffer_to_sram(sl, fl, buf, size) == -1) { fprintf(stderr, "write_buffer_to_sram() == -1\n"); return -1; @@ -1250,7 +1260,7 @@ int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, cons } /* run loader */ - stlink_step(sl); + stlink_run(sl); /* wait until done (reaches breakpoint) */ while (is_core_halted(sl) == 0) ; From 77f2d8b76c218e9edceaba71c6cc4f8724da49a1 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 14 Nov 2011 02:25:31 +0000 Subject: [PATCH 0043/1435] Don't try reading device params in bad USB modes. You cannot read device params when we're not in debug mode and trying to will fill the USB buffer with garbage, and you will have to unplug and replug and start again. (which will fail, because, you're in the wrong mode... :) --- src/stlink-sg.c | 36 +++++++++++++++++++++++++++--------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/src/stlink-sg.c b/src/stlink-sg.c index fd10c16eb..c4392dbfe 100644 --- a/src/stlink-sg.c +++ b/src/stlink-sg.c @@ -1104,8 +1104,7 @@ static stlink_t* stlink_open(const int verbose) { } - -stlink_t* stlink_v1_open(const int verbose) { +stlink_t* stlink_v1_open_inner(const int verbose) { ugly_init(verbose); stlink_t *sl = stlink_open(verbose); if (sl == NULL) { @@ -1114,7 +1113,6 @@ stlink_t* stlink_v1_open(const int verbose) { } stlink_version(sl); - stlink_load_device_params(sl); if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { ugly_log(UERROR, LOG_TAG, "WTF? successfully opened, but unable to read version details. BROKEN!\n"); @@ -1123,11 +1121,14 @@ stlink_t* stlink_v1_open(const int verbose) { DLOG("Reading current mode...\n"); switch (stlink_current_mode(sl)) { - case STLINK_DEV_MASS_MODE: - return sl; - case STLINK_DEV_DEBUG_MODE: - // TODO go to mass? + case STLINK_DEV_MASS_MODE: return sl; + case STLINK_DEV_DEBUG_MODE: + // TODO go to mass? + return sl; + default: + ILOG("Current mode unusable, trying to get back to a useful state...\n"); + break; } DLOG("Attempting to exit DFU mode\n"); @@ -1145,8 +1146,25 @@ stlink_t* stlink_v1_open(const int verbose) { fputs("Error: could not open stlink device\n", stderr); return NULL; } - // re-query device info + // re-query device info (and retest) stlink_version(sl); - stlink_load_device_params(sl); + if ((sl->version.st_vid != USB_ST_VID) || (sl->version.stlink_pid != USB_STLINK_PID)) { + ugly_log(UERROR, LOG_TAG, + "WTF? successfully opened, but unable to read version details. BROKEN!\n"); + return NULL; + } + return sl; +} + +stlink_t* stlink_v1_open(const int verbose) { + stlink_t *sl = stlink_v1_open_inner(verbose); + if (sl == NULL) { + fputs("Error: could not open stlink device\n", stderr); + return NULL; + } + // by now, it _must_ be fully open and in a useful mode.... + stlink_enter_swd_mode(sl); + stlink_load_device_params(sl); + ILOG("Successfully opened a stlink v1 debugger\n"); return sl; } From 29cf5d590c76ef157d9697a5871b12b8af770f00 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 7 Nov 2011 22:00:13 +0000 Subject: [PATCH 0044/1435] Restructure libs source to support multi platform The "libstm32l_discovery" was actually the ST std periph library, plus the CMSIS core files. Renamed it as such, and restructured the directories and naming to make this easier to contain the std periph drivers for more than just one board. Verified with the LCD demo makefile, and loading it in sram again. --- example/lcd/Makefile | 21 +++++--- example/libs_stm/build/Makefile | 37 ++++++++++++++ .../inc/base/stdint.h | 0 .../inc/core_support/core_cm3.c | 0 .../inc/core_support/core_cm3.h | 0 .../inc/device_support/stm32l1xx.h | 0 .../inc/device_support/system_stm32l1xx.h | 0 .../inc => libs_stm/inc/stm32l1xx}/misc.h | 0 .../inc/stm32l1xx}/stm32l1xx_adc.h | 0 .../inc/stm32l1xx}/stm32l1xx_comp.h | 0 .../inc/stm32l1xx}/stm32l1xx_crc.h | 0 .../inc/stm32l1xx}/stm32l1xx_dac.h | 0 .../inc/stm32l1xx}/stm32l1xx_dbgmcu.h | 0 .../inc/stm32l1xx}/stm32l1xx_dma.h | 0 .../inc/stm32l1xx}/stm32l1xx_exti.h | 0 .../inc/stm32l1xx}/stm32l1xx_flash.h | 0 .../inc/stm32l1xx}/stm32l1xx_gpio.h | 0 .../inc/stm32l1xx}/stm32l1xx_i2c.h | 0 .../inc/stm32l1xx}/stm32l1xx_iwdg.h | 0 .../inc/stm32l1xx}/stm32l1xx_lcd.h | 0 .../inc/stm32l1xx}/stm32l1xx_pwr.h | 0 .../inc/stm32l1xx}/stm32l1xx_rcc.h | 0 .../inc/stm32l1xx}/stm32l1xx_rtc.h | 0 .../inc/stm32l1xx}/stm32l1xx_spi.h | 0 .../inc/stm32l1xx}/stm32l1xx_syscfg.h | 0 .../inc/stm32l1xx}/stm32l1xx_tim.h | 0 .../inc/stm32l1xx}/stm32l1xx_usart.h | 0 .../inc/stm32l1xx}/stm32l1xx_wwdg.h | 0 .../src => libs_stm/src/stm32l1xx}/misc.c | 0 .../src/stm32l1xx}/stm32l1xx_adc.c | 0 .../src/stm32l1xx}/stm32l1xx_comp.c | 0 .../src/stm32l1xx}/stm32l1xx_crc.c | 0 .../src/stm32l1xx}/stm32l1xx_dac.c | 0 .../src/stm32l1xx}/stm32l1xx_dbgmcu.c | 0 .../src/stm32l1xx}/stm32l1xx_dma.c | 0 .../src/stm32l1xx}/stm32l1xx_exti.c | 0 .../src/stm32l1xx}/stm32l1xx_flash.c | 0 .../src/stm32l1xx}/stm32l1xx_flash_ramfunc.c | 0 .../src/stm32l1xx}/stm32l1xx_gpio.c | 0 .../src/stm32l1xx}/stm32l1xx_i2c.c | 0 .../src/stm32l1xx}/stm32l1xx_iwdg.c | 0 .../src/stm32l1xx}/stm32l1xx_lcd.c | 0 .../src/stm32l1xx}/stm32l1xx_pwr.c | 0 .../src/stm32l1xx}/stm32l1xx_rcc.c | 0 .../src/stm32l1xx}/stm32l1xx_rtc.c | 0 .../src/stm32l1xx}/stm32l1xx_spi.c | 0 .../src/stm32l1xx}/stm32l1xx_syscfg.c | 0 .../src/stm32l1xx}/stm32l1xx_tim.c | 0 .../src/stm32l1xx}/stm32l1xx_usart.c | 0 .../src/stm32l1xx}/stm32l1xx_wwdg.c | 0 example/libstm32l_discovery/build/Makefile | 51 ------------------- 51 files changed, 52 insertions(+), 57 deletions(-) create mode 100644 example/libs_stm/build/Makefile rename example/{libstm32l_discovery => libs_stm}/inc/base/stdint.h (100%) rename example/{libstm32l_discovery => libs_stm}/inc/core_support/core_cm3.c (100%) rename example/{libstm32l_discovery => libs_stm}/inc/core_support/core_cm3.h (100%) rename example/{libstm32l_discovery => libs_stm}/inc/device_support/stm32l1xx.h (100%) rename example/{libstm32l_discovery => libs_stm}/inc/device_support/system_stm32l1xx.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/misc.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_adc.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_comp.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_crc.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_dac.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_dbgmcu.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_dma.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_exti.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_flash.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_gpio.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_i2c.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_iwdg.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_lcd.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_pwr.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_rcc.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_rtc.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_spi.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_syscfg.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_tim.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_usart.h (100%) rename example/{libstm32l_discovery/inc => libs_stm/inc/stm32l1xx}/stm32l1xx_wwdg.h (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/misc.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_adc.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_comp.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_crc.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_dac.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_dbgmcu.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_dma.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_exti.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_flash.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_flash_ramfunc.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_gpio.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_i2c.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_iwdg.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_lcd.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_pwr.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_rcc.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_rtc.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_spi.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_syscfg.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_tim.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_usart.c (100%) rename example/{libstm32l_discovery/src => libs_stm/src/stm32l1xx}/stm32l1xx_wwdg.c (100%) delete mode 100644 example/libstm32l_discovery/build/Makefile diff --git a/example/lcd/Makefile b/example/lcd/Makefile index 0f31ae68b..8bfdbbbfa 100644 --- a/example/lcd/Makefile +++ b/example/lcd/Makefile @@ -7,11 +7,20 @@ CFLAGS+=-mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc CFLAGS+=-I. -# stm32l_discovery lib -CFLAGS+=-I../libstm32l_discovery/inc -CFLAGS+=-I../libstm32l_discovery/inc/base -CFLAGS+=-I../libstm32l_discovery/inc/core_support -CFLAGS+=-I../libstm32l_discovery/inc/device_support + +PLATFORM=stm32l1xx +LIBS_STM_PATH=../libs_stm + +INC_CORE_SUPPORT=$(LIBS_STM_PATH)/inc/core_support +SRC_CORE_SUPPORT=$(LIBS_STM_PATH)/inc/core_support +INC_DEVICE_SUPPORT=$(LIBS_STM_PATH)/inc/device_support +INC_PLATFORM=$(LIBS_STM_PATH)/inc/$(PLATFORM) + +CFLAGS+=-I$(INC_CORE_SUPPORT) +CFLAGS+=-I$(INC_DEVICE_SUPPORT) +CFLAGS+=-I$(INC_PLATFORM) +CFLAGS+=-I$(LIBS_STM_PATH)/inc/base + # to run from SRAM CFLAGS+=-Wl,-T,linker_stm32l.lds @@ -25,7 +34,7 @@ OBJS=$(SRCS:.c=.o) all: $(ELF) $(ELF): $(OBJS) - $(CC) $(CFLAGS) -o $@ $(OBJS) -L../libstm32l_discovery/build -lstm32l_discovery + $(CC) $(CFLAGS) -o $@ $(OBJS) -L$(LIBS_STM_PATH)/build -lstm32l_discovery %.o: %.c $(CC) $(CFLAGS) -c -o $@ $^ diff --git a/example/libs_stm/build/Makefile b/example/libs_stm/build/Makefile new file mode 100644 index 000000000..d96e48c59 --- /dev/null +++ b/example/libs_stm/build/Makefile @@ -0,0 +1,37 @@ +LIB = libstm32l_discovery.a + +CC = arm-none-eabi-gcc +AR = arm-none-eabi-ar +RANLIB = arm-none-eabi-ranlib + +PLATFORM=stm32l1xx + +INC_CORE_SUPPORT=../inc/core_support +SRC_CORE_SUPPORT=../inc/core_support +INC_DEVICE_SUPPORT=../inc/device_support +INC_PLATFORM=../inc/$(PLATFORM) +SRC_PLATFORM=../src/$(PLATFORM) + +CFLAGS = -Wall -O2 -mlittle-endian -mthumb +CFLAGS += -mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc +CFLAGS += -I$(INC_PLATFORM) -I$(INC_DEVICE_SUPPORT) -I$(INC_CORE_SUPPORT) -I../inc/base + +SRCS=$(wildcard $(SRC_PLATFORM)/*.c) +SRCS+=$(SRC_CORE_SUPPORT)/core_cm3.c + +OBJS = $(SRCS:.c=.o) + +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) -r $(LIB) $(OBJS) + $(RANLIB) $(LIB) + +%.o : %.c + $(CC) $(CFLAGS) -c -o $@ $^ + +clean: + -rm -f $(OBJS) + -rm -f $(LIB) + +.PHONY: all clean diff --git a/example/libstm32l_discovery/inc/base/stdint.h b/example/libs_stm/inc/base/stdint.h similarity index 100% rename from example/libstm32l_discovery/inc/base/stdint.h rename to example/libs_stm/inc/base/stdint.h diff --git a/example/libstm32l_discovery/inc/core_support/core_cm3.c b/example/libs_stm/inc/core_support/core_cm3.c similarity index 100% rename from example/libstm32l_discovery/inc/core_support/core_cm3.c rename to example/libs_stm/inc/core_support/core_cm3.c diff --git a/example/libstm32l_discovery/inc/core_support/core_cm3.h b/example/libs_stm/inc/core_support/core_cm3.h similarity index 100% rename from example/libstm32l_discovery/inc/core_support/core_cm3.h rename to example/libs_stm/inc/core_support/core_cm3.h diff --git a/example/libstm32l_discovery/inc/device_support/stm32l1xx.h b/example/libs_stm/inc/device_support/stm32l1xx.h similarity index 100% rename from example/libstm32l_discovery/inc/device_support/stm32l1xx.h rename to example/libs_stm/inc/device_support/stm32l1xx.h diff --git a/example/libstm32l_discovery/inc/device_support/system_stm32l1xx.h b/example/libs_stm/inc/device_support/system_stm32l1xx.h similarity index 100% rename from example/libstm32l_discovery/inc/device_support/system_stm32l1xx.h rename to example/libs_stm/inc/device_support/system_stm32l1xx.h diff --git a/example/libstm32l_discovery/inc/misc.h b/example/libs_stm/inc/stm32l1xx/misc.h similarity index 100% rename from example/libstm32l_discovery/inc/misc.h rename to example/libs_stm/inc/stm32l1xx/misc.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_adc.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_adc.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_adc.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_adc.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_comp.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_comp.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_comp.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_comp.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_crc.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_crc.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_crc.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_crc.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_dac.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_dac.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_dac.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_dac.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_dbgmcu.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_dbgmcu.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_dbgmcu.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_dbgmcu.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_dma.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_dma.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_dma.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_dma.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_exti.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_exti.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_exti.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_exti.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_flash.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_flash.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_flash.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_flash.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_gpio.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_gpio.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_gpio.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_gpio.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_i2c.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_i2c.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_i2c.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_i2c.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_iwdg.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_iwdg.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_iwdg.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_iwdg.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_lcd.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_lcd.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_lcd.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_lcd.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_pwr.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_pwr.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_pwr.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_pwr.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_rcc.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_rcc.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_rcc.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_rcc.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_rtc.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_rtc.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_rtc.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_rtc.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_spi.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_spi.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_spi.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_spi.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_syscfg.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_syscfg.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_syscfg.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_syscfg.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_tim.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_tim.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_tim.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_tim.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_usart.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_usart.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_usart.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_usart.h diff --git a/example/libstm32l_discovery/inc/stm32l1xx_wwdg.h b/example/libs_stm/inc/stm32l1xx/stm32l1xx_wwdg.h similarity index 100% rename from example/libstm32l_discovery/inc/stm32l1xx_wwdg.h rename to example/libs_stm/inc/stm32l1xx/stm32l1xx_wwdg.h diff --git a/example/libstm32l_discovery/src/misc.c b/example/libs_stm/src/stm32l1xx/misc.c similarity index 100% rename from example/libstm32l_discovery/src/misc.c rename to example/libs_stm/src/stm32l1xx/misc.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_adc.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_adc.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_adc.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_adc.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_comp.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_comp.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_comp.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_comp.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_crc.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_crc.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_crc.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_crc.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_dac.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_dac.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_dac.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_dac.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_dbgmcu.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_dbgmcu.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_dbgmcu.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_dbgmcu.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_dma.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_dma.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_dma.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_dma.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_exti.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_exti.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_exti.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_exti.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_flash.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_flash.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_flash.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_flash.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_flash_ramfunc.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_flash_ramfunc.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_flash_ramfunc.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_flash_ramfunc.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_gpio.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_gpio.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_gpio.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_gpio.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_i2c.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_i2c.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_i2c.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_i2c.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_iwdg.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_iwdg.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_iwdg.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_iwdg.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_lcd.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_lcd.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_lcd.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_lcd.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_pwr.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_pwr.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_pwr.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_pwr.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_rcc.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_rcc.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_rcc.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_rcc.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_rtc.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_rtc.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_rtc.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_rtc.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_spi.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_spi.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_spi.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_spi.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_syscfg.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_syscfg.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_syscfg.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_syscfg.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_tim.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_tim.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_tim.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_tim.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_usart.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_usart.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_usart.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_usart.c diff --git a/example/libstm32l_discovery/src/stm32l1xx_wwdg.c b/example/libs_stm/src/stm32l1xx/stm32l1xx_wwdg.c similarity index 100% rename from example/libstm32l_discovery/src/stm32l1xx_wwdg.c rename to example/libs_stm/src/stm32l1xx/stm32l1xx_wwdg.c diff --git a/example/libstm32l_discovery/build/Makefile b/example/libstm32l_discovery/build/Makefile deleted file mode 100644 index 09d3b71f0..000000000 --- a/example/libstm32l_discovery/build/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -LIB = libstm32l_discovery.a - -CC = arm-none-eabi-gcc -AR = arm-none-eabi-ar -RANLIB = arm-none-eabi-ranlib - -CFLAGS = -Wall -O2 -mlittle-endian -mthumb -CFLAGS += -mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc -CFLAGS += -I../inc -I../inc/device_support -I../inc/core_support -I../inc/base - -SRCS = \ -../src/misc.c \ -../src/stm32l1xx_adc.c \ -../src/stm32l1xx_comp.c \ -../src/stm32l1xx_crc.c \ -../src/stm32l1xx_dac.c \ -../src/stm32l1xx_dbgmcu.c \ -../src/stm32l1xx_dma.c \ -../src/stm32l1xx_exti.c \ -../src/stm32l1xx_flash.c \ -../src/stm32l1xx_flash_ramfunc.c \ -../src/stm32l1xx_gpio.c \ -../src/stm32l1xx_i2c.c \ -../src/stm32l1xx_iwdg.c \ -../src/stm32l1xx_lcd.c \ -../src/stm32l1xx_pwr.c \ -../src/stm32l1xx_rcc.c \ -../src/stm32l1xx_rtc.c \ -../src/stm32l1xx_spi.c \ -../src/stm32l1xx_syscfg.c \ -../src/stm32l1xx_tim.c \ -../src/stm32l1xx_usart.c \ -../src/stm32l1xx_wwdg.c \ -../inc/core_support/core_cm3.c - -OBJS = $(SRCS:.c=.o) - -all: $(LIB) - -$(LIB): $(OBJS) - $(AR) -r $(LIB) $(OBJS) - $(RANLIB) $(LIB) - -%.o : %.c - $(CC) $(CFLAGS) -c -o $@ $^ - -clean: - -rm -f $(OBJS) - -rm -f $(LIB) - -.PHONY: all clean From 3ec53a0d34016839cf6583117dd549da88aa63c7 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 7 Nov 2011 22:55:20 +0000 Subject: [PATCH 0045/1435] Rename 32L specific examples --- example/{lcd => 32l_lcd}/Makefile | 16 ++++++---------- example/{lcd => 32l_lcd}/discover_board.h | 0 example/{lcd => 32l_lcd}/linker_stm32l.lds | 0 example/{lcd => 32l_lcd}/main.c | 0 example/{lcd => 32l_lcd}/stm32l_discovery_lcd.c | 0 example/{lcd => 32l_lcd}/stm32l_discovery_lcd.h | 0 6 files changed, 6 insertions(+), 10 deletions(-) rename example/{lcd => 32l_lcd}/Makefile (56%) rename example/{lcd => 32l_lcd}/discover_board.h (100%) rename example/{lcd => 32l_lcd}/linker_stm32l.lds (100%) rename example/{lcd => 32l_lcd}/main.c (100%) rename example/{lcd => 32l_lcd}/stm32l_discovery_lcd.c (100%) rename example/{lcd => 32l_lcd}/stm32l_discovery_lcd.h (100%) diff --git a/example/lcd/Makefile b/example/32l_lcd/Makefile similarity index 56% rename from example/lcd/Makefile rename to example/32l_lcd/Makefile index 8bfdbbbfa..fce21946e 100644 --- a/example/lcd/Makefile +++ b/example/32l_lcd/Makefile @@ -11,20 +11,16 @@ CFLAGS+=-I. PLATFORM=stm32l1xx LIBS_STM_PATH=../libs_stm -INC_CORE_SUPPORT=$(LIBS_STM_PATH)/inc/core_support -SRC_CORE_SUPPORT=$(LIBS_STM_PATH)/inc/core_support -INC_DEVICE_SUPPORT=$(LIBS_STM_PATH)/inc/device_support -INC_PLATFORM=$(LIBS_STM_PATH)/inc/$(PLATFORM) - -CFLAGS+=-I$(INC_CORE_SUPPORT) -CFLAGS+=-I$(INC_DEVICE_SUPPORT) -CFLAGS+=-I$(INC_PLATFORM) CFLAGS+=-I$(LIBS_STM_PATH)/inc/base - +CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM) # to run from SRAM CFLAGS+=-Wl,-T,linker_stm32l.lds +LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32l_discovery + SRCS=\ main.c\ stm32l_discovery_lcd.c @@ -34,7 +30,7 @@ OBJS=$(SRCS:.c=.o) all: $(ELF) $(ELF): $(OBJS) - $(CC) $(CFLAGS) -o $@ $(OBJS) -L$(LIBS_STM_PATH)/build -lstm32l_discovery + $(CC) $(CFLAGS) -o $@ $(OBJS) $(LDFLAGS) %.o: %.c $(CC) $(CFLAGS) -c -o $@ $^ diff --git a/example/lcd/discover_board.h b/example/32l_lcd/discover_board.h similarity index 100% rename from example/lcd/discover_board.h rename to example/32l_lcd/discover_board.h diff --git a/example/lcd/linker_stm32l.lds b/example/32l_lcd/linker_stm32l.lds similarity index 100% rename from example/lcd/linker_stm32l.lds rename to example/32l_lcd/linker_stm32l.lds diff --git a/example/lcd/main.c b/example/32l_lcd/main.c similarity index 100% rename from example/lcd/main.c rename to example/32l_lcd/main.c diff --git a/example/lcd/stm32l_discovery_lcd.c b/example/32l_lcd/stm32l_discovery_lcd.c similarity index 100% rename from example/lcd/stm32l_discovery_lcd.c rename to example/32l_lcd/stm32l_discovery_lcd.c diff --git a/example/lcd/stm32l_discovery_lcd.h b/example/32l_lcd/stm32l_discovery_lcd.h similarity index 100% rename from example/lcd/stm32l_discovery_lcd.h rename to example/32l_lcd/stm32l_discovery_lcd.h From d69cad884996b01fb993b3df16c1050adaca5daa Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 7 Nov 2011 22:56:15 +0000 Subject: [PATCH 0046/1435] Rename board specific demos as appropriate --- example/{dac => 32l_dac}/Makefile | 0 example/{dac => 32l_dac}/discover_board.h | 0 example/{dac => 32l_dac}/main.c | 0 example/{dac => 32l_dac}/startup_stm32l1xx_md.s | 0 example/{dac => 32l_dac}/stm32_flash.ld | 0 example/{dac => 32l_dac}/system_stm32l1xx.c | 0 6 files changed, 0 insertions(+), 0 deletions(-) rename example/{dac => 32l_dac}/Makefile (100%) rename example/{dac => 32l_dac}/discover_board.h (100%) rename example/{dac => 32l_dac}/main.c (100%) rename example/{dac => 32l_dac}/startup_stm32l1xx_md.s (100%) rename example/{dac => 32l_dac}/stm32_flash.ld (100%) rename example/{dac => 32l_dac}/system_stm32l1xx.c (100%) diff --git a/example/dac/Makefile b/example/32l_dac/Makefile similarity index 100% rename from example/dac/Makefile rename to example/32l_dac/Makefile diff --git a/example/dac/discover_board.h b/example/32l_dac/discover_board.h similarity index 100% rename from example/dac/discover_board.h rename to example/32l_dac/discover_board.h diff --git a/example/dac/main.c b/example/32l_dac/main.c similarity index 100% rename from example/dac/main.c rename to example/32l_dac/main.c diff --git a/example/dac/startup_stm32l1xx_md.s b/example/32l_dac/startup_stm32l1xx_md.s similarity index 100% rename from example/dac/startup_stm32l1xx_md.s rename to example/32l_dac/startup_stm32l1xx_md.s diff --git a/example/dac/stm32_flash.ld b/example/32l_dac/stm32_flash.ld similarity index 100% rename from example/dac/stm32_flash.ld rename to example/32l_dac/stm32_flash.ld diff --git a/example/dac/system_stm32l1xx.c b/example/32l_dac/system_stm32l1xx.c similarity index 100% rename from example/dac/system_stm32l1xx.c rename to example/32l_dac/system_stm32l1xx.c From 518fe1b0d0b45ab6a9ec217f8b1ce51850077e97 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Mon, 7 Nov 2011 22:56:34 +0000 Subject: [PATCH 0047/1435] Fix compile error with new libraries --- example/32l_dac/Makefile | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/example/32l_dac/Makefile b/example/32l_dac/Makefile index 84db69ec3..4bd6eb454 100644 --- a/example/32l_dac/Makefile +++ b/example/32l_dac/Makefile @@ -5,25 +5,22 @@ CC=arm-none-eabi-gcc OBJCOPY=arm-none-eabi-objcopy CFLAGS=-O3 -mlittle-endian -mthumb -ifeq ($(CONFIG_STM32L_DISCOVERY), 1) - CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY=1 -else ifeq ($(CONFIG_STM32VL_DISCOVERY), 1) - CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32VL_DISCOVERY=1 -else ifeq ($(CONFIG_STM32F4_DISCOVERY), 1) - CFLAGS+=-mcpu=cortex-m4 -DCONFIG_STM32F4_DISCOVERY=1 -else -$(error "must specify CONFIG_ for board!") -endif +CFLAGS+=-mcpu=cortex-m3 -DCONFIG_STM32L_DISCOVERY=1 CFLAGS+=-ffreestanding -nostdlib -nostdinc # to run from FLASH CFLAGS+=-Wl,-T,stm32_flash.ld +PLATFORM=stm32l1xx +LIBS_STM_PATH=../libs_stm + # stm32l_discovery lib -CFLAGS+=-I../libstm32l_discovery/inc -CFLAGS+=-I../libstm32l_discovery/inc/base -CFLAGS+=-I../libstm32l_discovery/inc/core_support -CFLAGS+=-I../libstm32l_discovery/inc/device_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/base +CFLAGS+=-I$(LIBS_STM_PATH)/inc/core_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/device_support +CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM) + +LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32l_discovery all: $(BIN_IMAGE) @@ -31,7 +28,7 @@ $(BIN_IMAGE): $(EXECUTABLE) $(OBJCOPY) -O binary $^ $@ $(EXECUTABLE): main.c system_stm32l1xx.c startup_stm32l1xx_md.s - $(CC) $(CFLAGS) $^ -o $@ -L../libstm32l_discovery/build -lstm32l_discovery + $(CC) $(CFLAGS) $^ -o $@ $(LDFLAGS) clean: rm -rf $(EXECUTABLE) From fd1e3f5f2eba9e3a0b0d3e665737dd1c232b4a73 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 8 Nov 2011 00:57:54 +0000 Subject: [PATCH 0048/1435] Build libraries for stm32l1xx and stm32f10x These libraries IGNORE assert_param. Maybe later. --- example/32l_lcd/Makefile | 2 +- example/libs_stm/README | 9 + example/libs_stm/build/Makefile | 37 +- example/libs_stm/build/Makefile.common | 34 + example/libs_stm/build/Makefile.f10x | 5 + example/libs_stm/build/Makefile.l1xx | 5 + .../libs_stm/inc/device_support/stm32f10x.h | 8227 +++++++++++++++++ .../inc/device_support/system_stm32f10x.h | 97 + example/libs_stm/inc/stm32f10x/misc.h | 219 + .../libs_stm/inc/stm32f10x/stm32f10x_adc.h | 482 + .../libs_stm/inc/stm32f10x/stm32f10x_bkp.h | 194 + .../libs_stm/inc/stm32f10x/stm32f10x_can.h | 535 ++ .../libs_stm/inc/stm32f10x/stm32f10x_cec.h | 209 + .../libs_stm/inc/stm32f10x/stm32f10x_crc.h | 93 + .../libs_stm/inc/stm32f10x/stm32f10x_dac.h | 316 + .../libs_stm/inc/stm32f10x/stm32f10x_dbgmcu.h | 118 + .../libs_stm/inc/stm32f10x/stm32f10x_dma.h | 437 + .../libs_stm/inc/stm32f10x/stm32f10x_exti.h | 183 + .../libs_stm/inc/stm32f10x/stm32f10x_flash.h | 425 + .../libs_stm/inc/stm32f10x/stm32f10x_fsmc.h | 716 ++ .../libs_stm/inc/stm32f10x/stm32f10x_gpio.h | 379 + .../libs_stm/inc/stm32f10x/stm32f10x_i2c.h | 670 ++ .../libs_stm/inc/stm32f10x/stm32f10x_iwdg.h | 139 + .../libs_stm/inc/stm32f10x/stm32f10x_pwr.h | 155 + .../libs_stm/inc/stm32f10x/stm32f10x_rcc.h | 726 ++ .../libs_stm/inc/stm32f10x/stm32f10x_rtc.h | 134 + .../libs_stm/inc/stm32f10x/stm32f10x_sdio.h | 530 ++ .../libs_stm/inc/stm32f10x/stm32f10x_spi.h | 490 + .../libs_stm/inc/stm32f10x/stm32f10x_tim.h | 1133 +++ .../libs_stm/inc/stm32f10x/stm32f10x_usart.h | 411 + .../libs_stm/inc/stm32f10x/stm32f10x_wwdg.h | 114 + ..._Notes_for_STM32F10x_StdPeriph_Driver.html | 203 + example/libs_stm/src/stm32f10x/misc.c | 223 + .../libs_stm/src/stm32f10x/stm32f10x_adc.c | 1306 +++ .../libs_stm/src/stm32f10x/stm32f10x_bkp.c | 311 + .../libs_stm/src/stm32f10x/stm32f10x_can.c | 990 ++ .../libs_stm/src/stm32f10x/stm32f10x_cec.c | 432 + .../libs_stm/src/stm32f10x/stm32f10x_crc.c | 163 + .../libs_stm/src/stm32f10x/stm32f10x_dac.c | 579 ++ .../libs_stm/src/stm32f10x/stm32f10x_dbgmcu.c | 161 + .../libs_stm/src/stm32f10x/stm32f10x_dma.c | 693 ++ .../libs_stm/src/stm32f10x/stm32f10x_exti.c | 268 + .../libs_stm/src/stm32f10x/stm32f10x_flash.c | 1735 ++++ .../libs_stm/src/stm32f10x/stm32f10x_fsmc.c | 858 ++ .../libs_stm/src/stm32f10x/stm32f10x_gpio.c | 642 ++ .../libs_stm/src/stm32f10x/stm32f10x_i2c.c | 1285 +++ .../libs_stm/src/stm32f10x/stm32f10x_iwdg.c | 189 + .../libs_stm/src/stm32f10x/stm32f10x_pwr.c | 316 + .../libs_stm/src/stm32f10x/stm32f10x_rcc.c | 1477 +++ .../libs_stm/src/stm32f10x/stm32f10x_rtc.c | 341 + .../libs_stm/src/stm32f10x/stm32f10x_sdio.c | 798 ++ .../libs_stm/src/stm32f10x/stm32f10x_spi.c | 907 ++ .../libs_stm/src/stm32f10x/stm32f10x_tim.c | 2834 ++++++ .../libs_stm/src/stm32f10x/stm32f10x_usart.c | 1054 +++ .../libs_stm/src/stm32f10x/stm32f10x_wwdg.c | 223 + 55 files changed, 35179 insertions(+), 33 deletions(-) create mode 100644 example/libs_stm/README create mode 100644 example/libs_stm/build/Makefile.common create mode 100644 example/libs_stm/build/Makefile.f10x create mode 100644 example/libs_stm/build/Makefile.l1xx create mode 100644 example/libs_stm/inc/device_support/stm32f10x.h create mode 100644 example/libs_stm/inc/device_support/system_stm32f10x.h create mode 100644 example/libs_stm/inc/stm32f10x/misc.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_adc.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_bkp.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_can.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_cec.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_crc.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_dac.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_dbgmcu.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_dma.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_exti.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_flash.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_fsmc.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_gpio.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_i2c.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_iwdg.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_pwr.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_rcc.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_rtc.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_sdio.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_spi.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_tim.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_usart.h create mode 100644 example/libs_stm/inc/stm32f10x/stm32f10x_wwdg.h create mode 100644 example/libs_stm/src/stm32f10x/Release_Notes_for_STM32F10x_StdPeriph_Driver.html create mode 100644 example/libs_stm/src/stm32f10x/misc.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_adc.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_bkp.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_can.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_cec.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_crc.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_dac.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_dbgmcu.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_dma.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_exti.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_flash.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_fsmc.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_gpio.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_i2c.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_iwdg.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_pwr.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_rcc.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_rtc.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_sdio.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_spi.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_tim.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_usart.c create mode 100644 example/libs_stm/src/stm32f10x/stm32f10x_wwdg.c diff --git a/example/32l_lcd/Makefile b/example/32l_lcd/Makefile index fce21946e..fdb79c304 100644 --- a/example/32l_lcd/Makefile +++ b/example/32l_lcd/Makefile @@ -19,7 +19,7 @@ CFLAGS+=-I$(LIBS_STM_PATH)/inc/$(PLATFORM) # to run from SRAM CFLAGS+=-Wl,-T,linker_stm32l.lds -LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32l_discovery +LDFLAGS+=-L$(LIBS_STM_PATH)/build -lstm32_stdperiph_l1xx SRCS=\ main.c\ diff --git a/example/libs_stm/README b/example/libs_stm/README new file mode 100644 index 000000000..c3dcc4e4b --- /dev/null +++ b/example/libs_stm/README @@ -0,0 +1,9 @@ +This directory contains the StdPeriph libraries from ST, and the CMSIS core and device +support, all from ST. + +Issues: +* No tracking of which version of which library (yet) +* Both of these define assert_param() as empty. That may not be what you + want! + + diff --git a/example/libs_stm/build/Makefile b/example/libs_stm/build/Makefile index d96e48c59..d35e3d69f 100644 --- a/example/libs_stm/build/Makefile +++ b/example/libs_stm/build/Makefile @@ -1,37 +1,10 @@ -LIB = libstm32l_discovery.a -CC = arm-none-eabi-gcc -AR = arm-none-eabi-ar -RANLIB = arm-none-eabi-ranlib - -PLATFORM=stm32l1xx - -INC_CORE_SUPPORT=../inc/core_support -SRC_CORE_SUPPORT=../inc/core_support -INC_DEVICE_SUPPORT=../inc/device_support -INC_PLATFORM=../inc/$(PLATFORM) -SRC_PLATFORM=../src/$(PLATFORM) - -CFLAGS = -Wall -O2 -mlittle-endian -mthumb -CFLAGS += -mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc -CFLAGS += -I$(INC_PLATFORM) -I$(INC_DEVICE_SUPPORT) -I$(INC_CORE_SUPPORT) -I../inc/base - -SRCS=$(wildcard $(SRC_PLATFORM)/*.c) -SRCS+=$(SRC_CORE_SUPPORT)/core_cm3.c - -OBJS = $(SRCS:.c=.o) - -all: $(LIB) - -$(LIB): $(OBJS) - $(AR) -r $(LIB) $(OBJS) - $(RANLIB) $(LIB) - -%.o : %.c - $(CC) $(CFLAGS) -c -o $@ $^ +all: + make -f Makefile.f10x + make -f Makefile.l1xx clean: - -rm -f $(OBJS) - -rm -f $(LIB) + make -f Makefile.f10x clean + make -f Makefile.l1xx clean .PHONY: all clean diff --git a/example/libs_stm/build/Makefile.common b/example/libs_stm/build/Makefile.common new file mode 100644 index 000000000..954413e1b --- /dev/null +++ b/example/libs_stm/build/Makefile.common @@ -0,0 +1,34 @@ +CC = arm-none-eabi-gcc +AR = arm-none-eabi-ar +RANLIB = arm-none-eabi-ranlib + + +INC_CORE_SUPPORT=../inc/core_support +SRC_CORE_SUPPORT=../inc/core_support +INC_DEVICE_SUPPORT=../inc/device_support +INC_PLATFORM=../inc/$(PLATFORM) +SRC_PLATFORM=../src/$(PLATFORM) + +CFLAGS += -Wall -O2 -mlittle-endian -mthumb +CFLAGS += -mcpu=cortex-m3 -ffreestanding -nostdlib -nostdinc +CFLAGS += -I$(INC_PLATFORM) -I$(INC_DEVICE_SUPPORT) -I$(INC_CORE_SUPPORT) -I../inc/base + +SRCS=$(wildcard $(SRC_PLATFORM)/*.c) +SRCS+=$(SRC_CORE_SUPPORT)/core_cm3.c + +OBJS = $(SRCS:.c=.o) + +all: $(LIB) + +$(LIB): $(OBJS) + $(AR) -r $(LIB) $(OBJS) + $(RANLIB) $(LIB) + +%.o : %.c + $(CC) $(CFLAGS) -c -o $@ $^ + +clean: + -rm -f $(OBJS) + -rm -f $(LIB) + +.PHONY: all clean diff --git a/example/libs_stm/build/Makefile.f10x b/example/libs_stm/build/Makefile.f10x new file mode 100644 index 000000000..dfe0376ab --- /dev/null +++ b/example/libs_stm/build/Makefile.f10x @@ -0,0 +1,5 @@ +LIB = libstm32_stdperiph_f10x.a +PLATFORM=stm32f10x +CFLAGS+= -mcpu=cortex-m3 + +include Makefile.common diff --git a/example/libs_stm/build/Makefile.l1xx b/example/libs_stm/build/Makefile.l1xx new file mode 100644 index 000000000..7469ff58f --- /dev/null +++ b/example/libs_stm/build/Makefile.l1xx @@ -0,0 +1,5 @@ +LIB = libstm32_stdperiph_l1xx.a +PLATFORM=stm32l1xx +CFLAGS+=-mcpu=cortex-m3 + +include Makefile.common diff --git a/example/libs_stm/inc/device_support/stm32f10x.h b/example/libs_stm/inc/device_support/stm32f10x.h new file mode 100644 index 000000000..9d124002e --- /dev/null +++ b/example/libs_stm/inc/device_support/stm32f10x.h @@ -0,0 +1,8227 @@ +/** + ****************************************************************************** + * @file stm32f10x.h + * @author MCD Application Team + * @version V3.3.0 + * @date 04/16/2010 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for STM32F10x Connectivity line, High + * density, Medium density, Medium density Value line, Low density + * and Low density Value line and XL-density devices. + ****************************************************************************** + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *